Commit | Line | Data |
---|---|---|
b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
4a58c4bd | 3 | 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
16 | any later version. |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
42a68e18 | 28 | #include "as.h" |
5287ad62 | 29 | #include <limits.h> |
037e8744 | 30 | #include <stdarg.h> |
c19d1205 | 31 | #define NO_RELOC 0 |
3882b010 | 32 | #include "safe-ctype.h" |
b99bd4ef NC |
33 | #include "subsegs.h" |
34 | #include "obstack.h" | |
b99bd4ef | 35 | |
f263249b RE |
36 | #include "opcode/arm.h" |
37 | ||
b99bd4ef NC |
38 | #ifdef OBJ_ELF |
39 | #include "elf/arm.h" | |
a394c00f | 40 | #include "dw2gencfi.h" |
b99bd4ef NC |
41 | #endif |
42 | ||
f0927246 NC |
43 | #include "dwarf2dbg.h" |
44 | ||
7ed4c4c5 NC |
45 | #ifdef OBJ_ELF |
46 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
47 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
48 | ||
49 | /* This structure holds the unwinding state. */ | |
50 | ||
51 | static struct | |
52 | { | |
c19d1205 ZW |
53 | symbolS * proc_start; |
54 | symbolS * table_entry; | |
55 | symbolS * personality_routine; | |
56 | int personality_index; | |
7ed4c4c5 | 57 | /* The segment containing the function. */ |
c19d1205 ZW |
58 | segT saved_seg; |
59 | subsegT saved_subseg; | |
7ed4c4c5 NC |
60 | /* Opcodes generated from this function. */ |
61 | unsigned char * opcodes; | |
c19d1205 ZW |
62 | int opcode_count; |
63 | int opcode_alloc; | |
7ed4c4c5 | 64 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 65 | offsetT frame_size; |
7ed4c4c5 NC |
66 | /* We don't add stack adjustment opcodes immediately so that we can merge |
67 | multiple adjustments. We can also omit the final adjustment | |
68 | when using a frame pointer. */ | |
c19d1205 | 69 | offsetT pending_offset; |
7ed4c4c5 | 70 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
71 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
72 | offsetT fp_offset; | |
73 | int fp_reg; | |
7ed4c4c5 | 74 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 75 | unsigned fp_used:1; |
7ed4c4c5 | 76 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 77 | unsigned sp_restored:1; |
7ed4c4c5 NC |
78 | } unwind; |
79 | ||
8b1ad454 NC |
80 | #endif /* OBJ_ELF */ |
81 | ||
4962c51a MS |
82 | /* Results from operand parsing worker functions. */ |
83 | ||
84 | typedef enum | |
85 | { | |
86 | PARSE_OPERAND_SUCCESS, | |
87 | PARSE_OPERAND_FAIL, | |
88 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
89 | } parse_operand_result; | |
90 | ||
33a392fb PB |
91 | enum arm_float_abi |
92 | { | |
93 | ARM_FLOAT_ABI_HARD, | |
94 | ARM_FLOAT_ABI_SOFTFP, | |
95 | ARM_FLOAT_ABI_SOFT | |
96 | }; | |
97 | ||
c19d1205 | 98 | /* Types of processor to assemble for. */ |
b99bd4ef | 99 | #ifndef CPU_DEFAULT |
8a59fff3 MGD |
100 | /* The code that was here used to select a default CPU depending on compiler |
101 | pre-defines which were only present when doing native builds, thus | |
102 | changing gas' default behaviour depending upon the build host. | |
103 | ||
104 | If you have a target that requires a default CPU option then the you | |
105 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
106 | #endif |
107 | ||
108 | #ifndef FPU_DEFAULT | |
c820d418 MM |
109 | # ifdef TE_LINUX |
110 | # define FPU_DEFAULT FPU_ARCH_FPA | |
111 | # elif defined (TE_NetBSD) | |
112 | # ifdef OBJ_ELF | |
113 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
114 | # else | |
115 | /* Legacy a.out format. */ | |
116 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
117 | # endif | |
4e7fd91e PB |
118 | # elif defined (TE_VXWORKS) |
119 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
120 | # else |
121 | /* For backwards compatibility, default to FPA. */ | |
122 | # define FPU_DEFAULT FPU_ARCH_FPA | |
123 | # endif | |
124 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 125 | |
c19d1205 | 126 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 127 | |
e74cfd16 PB |
128 | static arm_feature_set cpu_variant; |
129 | static arm_feature_set arm_arch_used; | |
130 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 131 | |
b99bd4ef | 132 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
133 | static int uses_apcs_26 = FALSE; |
134 | static int atpcs = FALSE; | |
b34976b6 AM |
135 | static int support_interwork = FALSE; |
136 | static int uses_apcs_float = FALSE; | |
c19d1205 | 137 | static int pic_code = FALSE; |
845b51d6 | 138 | static int fix_v4bx = FALSE; |
278df34e NS |
139 | /* Warn on using deprecated features. */ |
140 | static int warn_on_deprecated = TRUE; | |
141 | ||
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
179 | static const arm_feature_set arm_ext_v4t_5 = | |
180 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
e74cfd16 | 187 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); |
b2a5fbdc | 188 | static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0); |
62b3e311 | 189 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
9e3c6df6 | 190 | static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); |
7e806470 PB |
191 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
192 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
9e3c6df6 | 197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); |
7e806470 | 198 | static const arm_feature_set arm_ext_m = |
b2a5fbdc | 199 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0); |
60e5ef9f | 200 | static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0); |
f4c65163 | 201 | static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0); |
b2a5fbdc | 202 | static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0); |
eea54501 | 203 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0); |
90ec0d68 | 204 | static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0); |
e74cfd16 PB |
205 | |
206 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
207 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
208 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
209 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
251665fc | 210 | static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; |
e74cfd16 | 211 | |
2d447fca JM |
212 | static const arm_feature_set arm_cext_iwmmxt2 = |
213 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
214 | static const arm_feature_set arm_cext_iwmmxt = |
215 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
216 | static const arm_feature_set arm_cext_xscale = | |
217 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
218 | static const arm_feature_set arm_cext_maverick = | |
219 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
220 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
221 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
222 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
223 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
224 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
225 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
62f3b8c8 | 226 | static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); |
5287ad62 | 227 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
228 | static const arm_feature_set fpu_vfp_ext_d32 = |
229 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
230 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
231 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
232 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
62f3b8c8 PB |
233 | static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); |
234 | static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); | |
235 | static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); | |
e74cfd16 | 236 | |
33a392fb | 237 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
238 | /* Record user cpu selection for object attributes. */ |
239 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
240 | /* Must be long enough to hold any of the names in arm_cpus. */ |
241 | static char selected_cpu_name[16]; | |
8d67f500 NC |
242 | |
243 | /* Return if no cpu was selected on command-line. */ | |
244 | static bfd_boolean | |
245 | no_cpu_selected (void) | |
246 | { | |
247 | return selected_cpu.core == arm_arch_none.core | |
248 | && selected_cpu.coproc == arm_arch_none.coproc; | |
249 | } | |
250 | ||
7cc69913 | 251 | #ifdef OBJ_ELF |
deeaaff8 DJ |
252 | # ifdef EABI_DEFAULT |
253 | static int meabi_flags = EABI_DEFAULT; | |
254 | # else | |
d507cf36 | 255 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 256 | # endif |
e1da3f5b | 257 | |
ee3c0378 AS |
258 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
259 | ||
e1da3f5b | 260 | bfd_boolean |
5f4273c7 | 261 | arm_is_eabi (void) |
e1da3f5b PB |
262 | { |
263 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
264 | } | |
7cc69913 | 265 | #endif |
b99bd4ef | 266 | |
b99bd4ef | 267 | #ifdef OBJ_ELF |
c19d1205 | 268 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
269 | symbolS * GOT_symbol; |
270 | #endif | |
271 | ||
b99bd4ef NC |
272 | /* 0: assemble for ARM, |
273 | 1: assemble for Thumb, | |
274 | 2: assemble for Thumb even though target CPU does not support thumb | |
275 | instructions. */ | |
276 | static int thumb_mode = 0; | |
8dc2430f NC |
277 | /* A value distinct from the possible values for thumb_mode that we |
278 | can use to record whether thumb_mode has been copied into the | |
279 | tc_frag_data field of a frag. */ | |
280 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 281 | |
e07e6e58 NC |
282 | /* Specifies the intrinsic IT insn behavior mode. */ |
283 | enum implicit_it_mode | |
284 | { | |
285 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
286 | IMPLICIT_IT_MODE_ARM = 0x01, | |
287 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
288 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
289 | }; | |
290 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
291 | ||
c19d1205 ZW |
292 | /* If unified_syntax is true, we are processing the new unified |
293 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
294 | ||
295 | - Immediate operands do not require a # prefix. | |
296 | - Conditional affixes always appear at the end of the | |
297 | instruction. (For backward compatibility, those instructions | |
298 | that formerly had them in the middle, continue to accept them | |
299 | there.) | |
300 | - The IT instruction may appear, and if it does is validated | |
301 | against subsequent conditional affixes. It does not generate | |
302 | machine code. | |
303 | ||
304 | Important differences from the old Thumb mode: | |
305 | ||
306 | - Immediate operands do not require a # prefix. | |
307 | - Most of the V6T2 instructions are only available in unified mode. | |
308 | - The .N and .W suffixes are recognized and honored (it is an error | |
309 | if they cannot be honored). | |
310 | - All instructions set the flags if and only if they have an 's' affix. | |
311 | - Conditional affixes may be used. They are validated against | |
312 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
313 | conditional affix except in the scope of an IT instruction. */ | |
314 | ||
315 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 316 | |
5287ad62 JB |
317 | enum neon_el_type |
318 | { | |
dcbf9037 | 319 | NT_invtype, |
5287ad62 JB |
320 | NT_untyped, |
321 | NT_integer, | |
322 | NT_float, | |
323 | NT_poly, | |
324 | NT_signed, | |
dcbf9037 | 325 | NT_unsigned |
5287ad62 JB |
326 | }; |
327 | ||
328 | struct neon_type_el | |
329 | { | |
330 | enum neon_el_type type; | |
331 | unsigned size; | |
332 | }; | |
333 | ||
334 | #define NEON_MAX_TYPE_ELS 4 | |
335 | ||
336 | struct neon_type | |
337 | { | |
338 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
339 | unsigned elems; | |
340 | }; | |
341 | ||
e07e6e58 NC |
342 | enum it_instruction_type |
343 | { | |
344 | OUTSIDE_IT_INSN, | |
345 | INSIDE_IT_INSN, | |
346 | INSIDE_IT_LAST_INSN, | |
347 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
348 | if inside, should be the last one. */ | |
349 | NEUTRAL_IT_INSN, /* This could be either inside or outside, | |
350 | i.e. BKPT and NOP. */ | |
351 | IT_INSN /* The IT insn has been parsed. */ | |
352 | }; | |
353 | ||
b99bd4ef NC |
354 | struct arm_it |
355 | { | |
c19d1205 | 356 | const char * error; |
b99bd4ef | 357 | unsigned long instruction; |
c19d1205 ZW |
358 | int size; |
359 | int size_req; | |
360 | int cond; | |
037e8744 JB |
361 | /* "uncond_value" is set to the value in place of the conditional field in |
362 | unconditional versions of the instruction, or -1 if nothing is | |
363 | appropriate. */ | |
364 | int uncond_value; | |
5287ad62 | 365 | struct neon_type vectype; |
88714cb8 DG |
366 | /* This does not indicate an actual NEON instruction, only that |
367 | the mnemonic accepts neon-style type suffixes. */ | |
368 | int is_neon; | |
0110f2b8 PB |
369 | /* Set to the opcode if the instruction needs relaxation. |
370 | Zero if the instruction is not relaxed. */ | |
371 | unsigned long relax; | |
b99bd4ef NC |
372 | struct |
373 | { | |
374 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
375 | expressionS exp; |
376 | int pc_rel; | |
b99bd4ef | 377 | } reloc; |
b99bd4ef | 378 | |
e07e6e58 NC |
379 | enum it_instruction_type it_insn_type; |
380 | ||
c19d1205 ZW |
381 | struct |
382 | { | |
383 | unsigned reg; | |
ca3f61f7 | 384 | signed int imm; |
dcbf9037 | 385 | struct neon_type_el vectype; |
ca3f61f7 NC |
386 | unsigned present : 1; /* Operand present. */ |
387 | unsigned isreg : 1; /* Operand was a register. */ | |
388 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
389 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
390 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 391 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
392 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
393 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
394 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 395 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 396 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 397 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
398 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
399 | unsigned writeback : 1; /* Operand has trailing ! */ | |
400 | unsigned preind : 1; /* Preindexed address. */ | |
401 | unsigned postind : 1; /* Postindexed address. */ | |
402 | unsigned negative : 1; /* Index register was negated. */ | |
403 | unsigned shifted : 1; /* Shift applied to operation. */ | |
404 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
c19d1205 | 405 | } operands[6]; |
b99bd4ef NC |
406 | }; |
407 | ||
c19d1205 | 408 | static struct arm_it inst; |
b99bd4ef NC |
409 | |
410 | #define NUM_FLOAT_VALS 8 | |
411 | ||
05d2d07e | 412 | const char * fp_const[] = |
b99bd4ef NC |
413 | { |
414 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
415 | }; | |
416 | ||
c19d1205 | 417 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
418 | #define MAX_LITTLENUMS 6 |
419 | ||
420 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
421 | ||
422 | #define FAIL (-1) | |
423 | #define SUCCESS (0) | |
424 | ||
425 | #define SUFF_S 1 | |
426 | #define SUFF_D 2 | |
427 | #define SUFF_E 3 | |
428 | #define SUFF_P 4 | |
429 | ||
c19d1205 ZW |
430 | #define CP_T_X 0x00008000 |
431 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 432 | |
c19d1205 ZW |
433 | #define CONDS_BIT 0x00100000 |
434 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
435 | |
436 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
437 | ||
438 | struct asm_cond | |
439 | { | |
d3ce72d0 | 440 | const char * template_name; |
c921be7d | 441 | unsigned long value; |
b99bd4ef NC |
442 | }; |
443 | ||
c19d1205 | 444 | #define COND_ALWAYS 0xE |
b99bd4ef | 445 | |
b99bd4ef NC |
446 | struct asm_psr |
447 | { | |
d3ce72d0 | 448 | const char * template_name; |
c921be7d | 449 | unsigned long field; |
b99bd4ef NC |
450 | }; |
451 | ||
62b3e311 PB |
452 | struct asm_barrier_opt |
453 | { | |
d3ce72d0 | 454 | const char * template_name; |
c921be7d | 455 | unsigned long value; |
62b3e311 PB |
456 | }; |
457 | ||
2d2255b5 | 458 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
459 | #define SPSR_BIT (1 << 22) |
460 | ||
c19d1205 ZW |
461 | /* The individual PSR flag bits. */ |
462 | #define PSR_c (1 << 16) | |
463 | #define PSR_x (1 << 17) | |
464 | #define PSR_s (1 << 18) | |
465 | #define PSR_f (1 << 19) | |
b99bd4ef | 466 | |
c19d1205 | 467 | struct reloc_entry |
bfae80f2 | 468 | { |
c921be7d NC |
469 | char * name; |
470 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
471 | }; |
472 | ||
5287ad62 | 473 | enum vfp_reg_pos |
bfae80f2 | 474 | { |
5287ad62 JB |
475 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
476 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
477 | }; |
478 | ||
479 | enum vfp_ldstm_type | |
480 | { | |
481 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
482 | }; | |
483 | ||
dcbf9037 JB |
484 | /* Bits for DEFINED field in neon_typed_alias. */ |
485 | #define NTA_HASTYPE 1 | |
486 | #define NTA_HASINDEX 2 | |
487 | ||
488 | struct neon_typed_alias | |
489 | { | |
c921be7d NC |
490 | unsigned char defined; |
491 | unsigned char index; | |
492 | struct neon_type_el eltype; | |
dcbf9037 JB |
493 | }; |
494 | ||
c19d1205 ZW |
495 | /* ARM register categories. This includes coprocessor numbers and various |
496 | architecture extensions' registers. */ | |
497 | enum arm_reg_type | |
bfae80f2 | 498 | { |
c19d1205 ZW |
499 | REG_TYPE_RN, |
500 | REG_TYPE_CP, | |
501 | REG_TYPE_CN, | |
502 | REG_TYPE_FN, | |
503 | REG_TYPE_VFS, | |
504 | REG_TYPE_VFD, | |
5287ad62 | 505 | REG_TYPE_NQ, |
037e8744 | 506 | REG_TYPE_VFSD, |
5287ad62 | 507 | REG_TYPE_NDQ, |
037e8744 | 508 | REG_TYPE_NSDQ, |
c19d1205 ZW |
509 | REG_TYPE_VFC, |
510 | REG_TYPE_MVF, | |
511 | REG_TYPE_MVD, | |
512 | REG_TYPE_MVFX, | |
513 | REG_TYPE_MVDX, | |
514 | REG_TYPE_MVAX, | |
515 | REG_TYPE_DSPSC, | |
516 | REG_TYPE_MMXWR, | |
517 | REG_TYPE_MMXWC, | |
518 | REG_TYPE_MMXWCG, | |
519 | REG_TYPE_XSCALE, | |
90ec0d68 | 520 | REG_TYPE_RNB |
bfae80f2 RE |
521 | }; |
522 | ||
dcbf9037 JB |
523 | /* Structure for a hash table entry for a register. |
524 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
525 | information which states whether a vector type or index is specified (for a | |
526 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
527 | struct reg_entry |
528 | { | |
c921be7d | 529 | const char * name; |
90ec0d68 | 530 | unsigned int number; |
c921be7d NC |
531 | unsigned char type; |
532 | unsigned char builtin; | |
533 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
534 | }; |
535 | ||
c19d1205 | 536 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 537 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
538 | { |
539 | N_("ARM register expected"), | |
540 | N_("bad or missing co-processor number"), | |
541 | N_("co-processor register expected"), | |
542 | N_("FPA register expected"), | |
543 | N_("VFP single precision register expected"), | |
5287ad62 JB |
544 | N_("VFP/Neon double precision register expected"), |
545 | N_("Neon quad precision register expected"), | |
037e8744 | 546 | N_("VFP single or double precision register expected"), |
5287ad62 | 547 | N_("Neon double or quad precision register expected"), |
037e8744 | 548 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
549 | N_("VFP system register expected"), |
550 | N_("Maverick MVF register expected"), | |
551 | N_("Maverick MVD register expected"), | |
552 | N_("Maverick MVFX register expected"), | |
553 | N_("Maverick MVDX register expected"), | |
554 | N_("Maverick MVAX register expected"), | |
555 | N_("Maverick DSPSC register expected"), | |
556 | N_("iWMMXt data register expected"), | |
557 | N_("iWMMXt control register expected"), | |
558 | N_("iWMMXt scalar register expected"), | |
559 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
560 | }; |
561 | ||
c19d1205 ZW |
562 | /* Some well known registers that we refer to directly elsewhere. */ |
563 | #define REG_SP 13 | |
564 | #define REG_LR 14 | |
565 | #define REG_PC 15 | |
404ff6b5 | 566 | |
b99bd4ef NC |
567 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
568 | take 2: */ | |
c19d1205 | 569 | #define INSN_SIZE 4 |
b99bd4ef NC |
570 | |
571 | struct asm_opcode | |
572 | { | |
573 | /* Basic string to match. */ | |
d3ce72d0 | 574 | const char * template_name; |
c19d1205 ZW |
575 | |
576 | /* Parameters to instruction. */ | |
5be8be5d | 577 | unsigned int operands[8]; |
c19d1205 ZW |
578 | |
579 | /* Conditional tag - see opcode_lookup. */ | |
580 | unsigned int tag : 4; | |
b99bd4ef NC |
581 | |
582 | /* Basic instruction code. */ | |
c19d1205 | 583 | unsigned int avalue : 28; |
b99bd4ef | 584 | |
c19d1205 ZW |
585 | /* Thumb-format instruction code. */ |
586 | unsigned int tvalue; | |
b99bd4ef | 587 | |
90e4755a | 588 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
589 | const arm_feature_set * avariant; |
590 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
591 | |
592 | /* Function to call to encode instruction in ARM format. */ | |
593 | void (* aencode) (void); | |
b99bd4ef | 594 | |
c19d1205 ZW |
595 | /* Function to call to encode instruction in Thumb format. */ |
596 | void (* tencode) (void); | |
b99bd4ef NC |
597 | }; |
598 | ||
a737bd4d NC |
599 | /* Defines for various bits that we will want to toggle. */ |
600 | #define INST_IMMEDIATE 0x02000000 | |
601 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 602 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
603 | #define SHIFT_BY_REG 0x00000010 |
604 | #define PRE_INDEX 0x01000000 | |
605 | #define INDEX_UP 0x00800000 | |
606 | #define WRITE_BACK 0x00200000 | |
607 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 608 | #define CPSI_MMOD 0x00020000 |
90e4755a | 609 | |
a737bd4d NC |
610 | #define LITERAL_MASK 0xf000f000 |
611 | #define OPCODE_MASK 0xfe1fffff | |
612 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 613 | |
efd81785 PB |
614 | #define T2_SUBS_PC_LR 0xf3de8f00 |
615 | ||
a737bd4d | 616 | #define DATA_OP_SHIFT 21 |
90e4755a | 617 | |
ef8d22e6 PB |
618 | #define T2_OPCODE_MASK 0xfe1fffff |
619 | #define T2_DATA_OP_SHIFT 21 | |
620 | ||
a737bd4d NC |
621 | /* Codes to distinguish the arithmetic instructions. */ |
622 | #define OPCODE_AND 0 | |
623 | #define OPCODE_EOR 1 | |
624 | #define OPCODE_SUB 2 | |
625 | #define OPCODE_RSB 3 | |
626 | #define OPCODE_ADD 4 | |
627 | #define OPCODE_ADC 5 | |
628 | #define OPCODE_SBC 6 | |
629 | #define OPCODE_RSC 7 | |
630 | #define OPCODE_TST 8 | |
631 | #define OPCODE_TEQ 9 | |
632 | #define OPCODE_CMP 10 | |
633 | #define OPCODE_CMN 11 | |
634 | #define OPCODE_ORR 12 | |
635 | #define OPCODE_MOV 13 | |
636 | #define OPCODE_BIC 14 | |
637 | #define OPCODE_MVN 15 | |
90e4755a | 638 | |
ef8d22e6 PB |
639 | #define T2_OPCODE_AND 0 |
640 | #define T2_OPCODE_BIC 1 | |
641 | #define T2_OPCODE_ORR 2 | |
642 | #define T2_OPCODE_ORN 3 | |
643 | #define T2_OPCODE_EOR 4 | |
644 | #define T2_OPCODE_ADD 8 | |
645 | #define T2_OPCODE_ADC 10 | |
646 | #define T2_OPCODE_SBC 11 | |
647 | #define T2_OPCODE_SUB 13 | |
648 | #define T2_OPCODE_RSB 14 | |
649 | ||
a737bd4d NC |
650 | #define T_OPCODE_MUL 0x4340 |
651 | #define T_OPCODE_TST 0x4200 | |
652 | #define T_OPCODE_CMN 0x42c0 | |
653 | #define T_OPCODE_NEG 0x4240 | |
654 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 655 | |
a737bd4d NC |
656 | #define T_OPCODE_ADD_R3 0x1800 |
657 | #define T_OPCODE_SUB_R3 0x1a00 | |
658 | #define T_OPCODE_ADD_HI 0x4400 | |
659 | #define T_OPCODE_ADD_ST 0xb000 | |
660 | #define T_OPCODE_SUB_ST 0xb080 | |
661 | #define T_OPCODE_ADD_SP 0xa800 | |
662 | #define T_OPCODE_ADD_PC 0xa000 | |
663 | #define T_OPCODE_ADD_I8 0x3000 | |
664 | #define T_OPCODE_SUB_I8 0x3800 | |
665 | #define T_OPCODE_ADD_I3 0x1c00 | |
666 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 667 | |
a737bd4d NC |
668 | #define T_OPCODE_ASR_R 0x4100 |
669 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
670 | #define T_OPCODE_LSR_R 0x40c0 |
671 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
672 | #define T_OPCODE_ASR_I 0x1000 |
673 | #define T_OPCODE_LSL_I 0x0000 | |
674 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 675 | |
a737bd4d NC |
676 | #define T_OPCODE_MOV_I8 0x2000 |
677 | #define T_OPCODE_CMP_I8 0x2800 | |
678 | #define T_OPCODE_CMP_LR 0x4280 | |
679 | #define T_OPCODE_MOV_HR 0x4600 | |
680 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 681 | |
a737bd4d NC |
682 | #define T_OPCODE_LDR_PC 0x4800 |
683 | #define T_OPCODE_LDR_SP 0x9800 | |
684 | #define T_OPCODE_STR_SP 0x9000 | |
685 | #define T_OPCODE_LDR_IW 0x6800 | |
686 | #define T_OPCODE_STR_IW 0x6000 | |
687 | #define T_OPCODE_LDR_IH 0x8800 | |
688 | #define T_OPCODE_STR_IH 0x8000 | |
689 | #define T_OPCODE_LDR_IB 0x7800 | |
690 | #define T_OPCODE_STR_IB 0x7000 | |
691 | #define T_OPCODE_LDR_RW 0x5800 | |
692 | #define T_OPCODE_STR_RW 0x5000 | |
693 | #define T_OPCODE_LDR_RH 0x5a00 | |
694 | #define T_OPCODE_STR_RH 0x5200 | |
695 | #define T_OPCODE_LDR_RB 0x5c00 | |
696 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 697 | |
a737bd4d NC |
698 | #define T_OPCODE_PUSH 0xb400 |
699 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 700 | |
2fc8bdac | 701 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 702 | |
a737bd4d | 703 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 704 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 705 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 706 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
707 | |
708 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 709 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
710 | #define BAD_PC _("r15 not allowed here") |
711 | #define BAD_COND _("instruction cannot be conditional") | |
712 | #define BAD_OVERLAP _("registers may not be the same") | |
713 | #define BAD_HIREG _("lo register required") | |
714 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 715 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
716 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
717 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 718 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
719 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
720 | #define BAD_IT_COND _("incorrect condition in IT block") | |
721 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 722 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
723 | #define BAD_PC_ADDRESSING \ |
724 | _("cannot use register index with PC-relative addressing") | |
725 | #define BAD_PC_WRITEBACK \ | |
726 | _("cannot use writeback with PC-relative addressing") | |
c19d1205 | 727 | |
c921be7d NC |
728 | static struct hash_control * arm_ops_hsh; |
729 | static struct hash_control * arm_cond_hsh; | |
730 | static struct hash_control * arm_shift_hsh; | |
731 | static struct hash_control * arm_psr_hsh; | |
732 | static struct hash_control * arm_v7m_psr_hsh; | |
733 | static struct hash_control * arm_reg_hsh; | |
734 | static struct hash_control * arm_reloc_hsh; | |
735 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 736 | |
b99bd4ef NC |
737 | /* Stuff needed to resolve the label ambiguity |
738 | As: | |
739 | ... | |
740 | label: <insn> | |
741 | may differ from: | |
742 | ... | |
743 | label: | |
5f4273c7 | 744 | <insn> */ |
b99bd4ef NC |
745 | |
746 | symbolS * last_label_seen; | |
b34976b6 | 747 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 748 | |
3d0c9500 NC |
749 | /* Literal pool structure. Held on a per-section |
750 | and per-sub-section basis. */ | |
a737bd4d | 751 | |
c19d1205 | 752 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 753 | typedef struct literal_pool |
b99bd4ef | 754 | { |
c921be7d NC |
755 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
756 | unsigned int next_free_entry; | |
757 | unsigned int id; | |
758 | symbolS * symbol; | |
759 | segT section; | |
760 | subsegT sub_section; | |
761 | struct literal_pool * next; | |
3d0c9500 | 762 | } literal_pool; |
b99bd4ef | 763 | |
3d0c9500 NC |
764 | /* Pointer to a linked list of literal pools. */ |
765 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 766 | |
e07e6e58 NC |
767 | #ifdef OBJ_ELF |
768 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
769 | #else | |
770 | static struct current_it now_it; | |
771 | #endif | |
772 | ||
773 | static inline int | |
774 | now_it_compatible (int cond) | |
775 | { | |
776 | return (cond & ~1) == (now_it.cc & ~1); | |
777 | } | |
778 | ||
779 | static inline int | |
780 | conditional_insn (void) | |
781 | { | |
782 | return inst.cond != COND_ALWAYS; | |
783 | } | |
784 | ||
785 | static int in_it_block (void); | |
786 | ||
787 | static int handle_it_state (void); | |
788 | ||
789 | static void force_automatic_it_block_close (void); | |
790 | ||
c921be7d NC |
791 | static void it_fsm_post_encode (void); |
792 | ||
e07e6e58 NC |
793 | #define set_it_insn_type(type) \ |
794 | do \ | |
795 | { \ | |
796 | inst.it_insn_type = type; \ | |
797 | if (handle_it_state () == FAIL) \ | |
798 | return; \ | |
799 | } \ | |
800 | while (0) | |
801 | ||
c921be7d NC |
802 | #define set_it_insn_type_nonvoid(type, failret) \ |
803 | do \ | |
804 | { \ | |
805 | inst.it_insn_type = type; \ | |
806 | if (handle_it_state () == FAIL) \ | |
807 | return failret; \ | |
808 | } \ | |
809 | while(0) | |
810 | ||
e07e6e58 NC |
811 | #define set_it_insn_type_last() \ |
812 | do \ | |
813 | { \ | |
814 | if (inst.cond == COND_ALWAYS) \ | |
815 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ | |
816 | else \ | |
817 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ | |
818 | } \ | |
819 | while (0) | |
820 | ||
c19d1205 | 821 | /* Pure syntax. */ |
b99bd4ef | 822 | |
c19d1205 ZW |
823 | /* This array holds the chars that always start a comment. If the |
824 | pre-processor is disabled, these aren't very useful. */ | |
825 | const char comment_chars[] = "@"; | |
3d0c9500 | 826 | |
c19d1205 ZW |
827 | /* This array holds the chars that only start a comment at the beginning of |
828 | a line. If the line seems to have the form '# 123 filename' | |
829 | .line and .file directives will appear in the pre-processed output. */ | |
830 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
831 | first line of the input file. This is because the compiler outputs | |
832 | #NO_APP at the beginning of its output. */ | |
833 | /* Also note that comments like this one will always work. */ | |
834 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 835 | |
c19d1205 | 836 | const char line_separator_chars[] = ";"; |
b99bd4ef | 837 | |
c19d1205 ZW |
838 | /* Chars that can be used to separate mant |
839 | from exp in floating point numbers. */ | |
840 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 841 | |
c19d1205 ZW |
842 | /* Chars that mean this number is a floating point constant. */ |
843 | /* As in 0f12.456 */ | |
844 | /* or 0d1.2345e12 */ | |
b99bd4ef | 845 | |
c19d1205 | 846 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 847 | |
c19d1205 ZW |
848 | /* Prefix characters that indicate the start of an immediate |
849 | value. */ | |
850 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 851 | |
c19d1205 ZW |
852 | /* Separator character handling. */ |
853 | ||
854 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
855 | ||
856 | static inline int | |
857 | skip_past_char (char ** str, char c) | |
858 | { | |
859 | if (**str == c) | |
860 | { | |
861 | (*str)++; | |
862 | return SUCCESS; | |
3d0c9500 | 863 | } |
c19d1205 ZW |
864 | else |
865 | return FAIL; | |
866 | } | |
c921be7d | 867 | |
c19d1205 | 868 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 869 | |
c19d1205 ZW |
870 | /* Arithmetic expressions (possibly involving symbols). */ |
871 | ||
872 | /* Return TRUE if anything in the expression is a bignum. */ | |
873 | ||
874 | static int | |
875 | walk_no_bignums (symbolS * sp) | |
876 | { | |
877 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
878 | return 1; | |
879 | ||
880 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 881 | { |
c19d1205 ZW |
882 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
883 | || (symbol_get_value_expression (sp)->X_op_symbol | |
884 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
885 | } |
886 | ||
c19d1205 | 887 | return 0; |
3d0c9500 NC |
888 | } |
889 | ||
c19d1205 ZW |
890 | static int in_my_get_expression = 0; |
891 | ||
892 | /* Third argument to my_get_expression. */ | |
893 | #define GE_NO_PREFIX 0 | |
894 | #define GE_IMM_PREFIX 1 | |
895 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
896 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
897 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
898 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 899 | |
b99bd4ef | 900 | static int |
c19d1205 | 901 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 902 | { |
c19d1205 ZW |
903 | char * save_in; |
904 | segT seg; | |
b99bd4ef | 905 | |
c19d1205 ZW |
906 | /* In unified syntax, all prefixes are optional. */ |
907 | if (unified_syntax) | |
5287ad62 JB |
908 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
909 | : GE_OPT_PREFIX; | |
b99bd4ef | 910 | |
c19d1205 | 911 | switch (prefix_mode) |
b99bd4ef | 912 | { |
c19d1205 ZW |
913 | case GE_NO_PREFIX: break; |
914 | case GE_IMM_PREFIX: | |
915 | if (!is_immediate_prefix (**str)) | |
916 | { | |
917 | inst.error = _("immediate expression requires a # prefix"); | |
918 | return FAIL; | |
919 | } | |
920 | (*str)++; | |
921 | break; | |
922 | case GE_OPT_PREFIX: | |
5287ad62 | 923 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
924 | if (is_immediate_prefix (**str)) |
925 | (*str)++; | |
926 | break; | |
927 | default: abort (); | |
928 | } | |
b99bd4ef | 929 | |
c19d1205 | 930 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 931 | |
c19d1205 ZW |
932 | save_in = input_line_pointer; |
933 | input_line_pointer = *str; | |
934 | in_my_get_expression = 1; | |
935 | seg = expression (ep); | |
936 | in_my_get_expression = 0; | |
937 | ||
f86adc07 | 938 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 939 | { |
f86adc07 | 940 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
941 | *str = input_line_pointer; |
942 | input_line_pointer = save_in; | |
943 | if (inst.error == NULL) | |
f86adc07 NS |
944 | inst.error = (ep->X_op == O_absent |
945 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
946 | return 1; |
947 | } | |
b99bd4ef | 948 | |
c19d1205 ZW |
949 | #ifdef OBJ_AOUT |
950 | if (seg != absolute_section | |
951 | && seg != text_section | |
952 | && seg != data_section | |
953 | && seg != bss_section | |
954 | && seg != undefined_section) | |
955 | { | |
956 | inst.error = _("bad segment"); | |
957 | *str = input_line_pointer; | |
958 | input_line_pointer = save_in; | |
959 | return 1; | |
b99bd4ef | 960 | } |
87975d2a AM |
961 | #else |
962 | (void) seg; | |
c19d1205 | 963 | #endif |
b99bd4ef | 964 | |
c19d1205 ZW |
965 | /* Get rid of any bignums now, so that we don't generate an error for which |
966 | we can't establish a line number later on. Big numbers are never valid | |
967 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
968 | if (prefix_mode != GE_OPT_PREFIX_BIG |
969 | && (ep->X_op == O_big | |
970 | || (ep->X_add_symbol | |
971 | && (walk_no_bignums (ep->X_add_symbol) | |
972 | || (ep->X_op_symbol | |
973 | && walk_no_bignums (ep->X_op_symbol)))))) | |
c19d1205 ZW |
974 | { |
975 | inst.error = _("invalid constant"); | |
976 | *str = input_line_pointer; | |
977 | input_line_pointer = save_in; | |
978 | return 1; | |
979 | } | |
b99bd4ef | 980 | |
c19d1205 ZW |
981 | *str = input_line_pointer; |
982 | input_line_pointer = save_in; | |
983 | return 0; | |
b99bd4ef NC |
984 | } |
985 | ||
c19d1205 ZW |
986 | /* Turn a string in input_line_pointer into a floating point constant |
987 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
988 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
989 | returned, or NULL on OK. | |
b99bd4ef | 990 | |
c19d1205 ZW |
991 | Note that fp constants aren't represent in the normal way on the ARM. |
992 | In big endian mode, things are as expected. However, in little endian | |
993 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
994 | within the words. For example, (double) 1.1 in big endian mode is | |
995 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
996 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 997 | |
c19d1205 | 998 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 999 | |
c19d1205 ZW |
1000 | char * |
1001 | md_atof (int type, char * litP, int * sizeP) | |
1002 | { | |
1003 | int prec; | |
1004 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1005 | char *t; | |
1006 | int i; | |
b99bd4ef | 1007 | |
c19d1205 ZW |
1008 | switch (type) |
1009 | { | |
1010 | case 'f': | |
1011 | case 'F': | |
1012 | case 's': | |
1013 | case 'S': | |
1014 | prec = 2; | |
1015 | break; | |
b99bd4ef | 1016 | |
c19d1205 ZW |
1017 | case 'd': |
1018 | case 'D': | |
1019 | case 'r': | |
1020 | case 'R': | |
1021 | prec = 4; | |
1022 | break; | |
b99bd4ef | 1023 | |
c19d1205 ZW |
1024 | case 'x': |
1025 | case 'X': | |
499ac353 | 1026 | prec = 5; |
c19d1205 | 1027 | break; |
b99bd4ef | 1028 | |
c19d1205 ZW |
1029 | case 'p': |
1030 | case 'P': | |
499ac353 | 1031 | prec = 5; |
c19d1205 | 1032 | break; |
a737bd4d | 1033 | |
c19d1205 ZW |
1034 | default: |
1035 | *sizeP = 0; | |
499ac353 | 1036 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1037 | } |
b99bd4ef | 1038 | |
c19d1205 ZW |
1039 | t = atof_ieee (input_line_pointer, type, words); |
1040 | if (t) | |
1041 | input_line_pointer = t; | |
499ac353 | 1042 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1043 | |
c19d1205 ZW |
1044 | if (target_big_endian) |
1045 | { | |
1046 | for (i = 0; i < prec; i++) | |
1047 | { | |
499ac353 NC |
1048 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1049 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1050 | } |
1051 | } | |
1052 | else | |
1053 | { | |
e74cfd16 | 1054 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1055 | for (i = prec - 1; i >= 0; i--) |
1056 | { | |
499ac353 NC |
1057 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1058 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1059 | } |
1060 | else | |
1061 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1062 | For an 8 byte float the order is 1 0 3 2. */ | |
1063 | for (i = 0; i < prec; i += 2) | |
1064 | { | |
499ac353 NC |
1065 | md_number_to_chars (litP, (valueT) words[i + 1], |
1066 | sizeof (LITTLENUM_TYPE)); | |
1067 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1068 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1069 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1070 | } |
1071 | } | |
b99bd4ef | 1072 | |
499ac353 | 1073 | return NULL; |
c19d1205 | 1074 | } |
b99bd4ef | 1075 | |
c19d1205 ZW |
1076 | /* We handle all bad expressions here, so that we can report the faulty |
1077 | instruction in the error message. */ | |
1078 | void | |
91d6fa6a | 1079 | md_operand (expressionS * exp) |
c19d1205 ZW |
1080 | { |
1081 | if (in_my_get_expression) | |
91d6fa6a | 1082 | exp->X_op = O_illegal; |
b99bd4ef NC |
1083 | } |
1084 | ||
c19d1205 | 1085 | /* Immediate values. */ |
b99bd4ef | 1086 | |
c19d1205 ZW |
1087 | /* Generic immediate-value read function for use in directives. |
1088 | Accepts anything that 'expression' can fold to a constant. | |
1089 | *val receives the number. */ | |
1090 | #ifdef OBJ_ELF | |
1091 | static int | |
1092 | immediate_for_directive (int *val) | |
b99bd4ef | 1093 | { |
c19d1205 ZW |
1094 | expressionS exp; |
1095 | exp.X_op = O_illegal; | |
b99bd4ef | 1096 | |
c19d1205 ZW |
1097 | if (is_immediate_prefix (*input_line_pointer)) |
1098 | { | |
1099 | input_line_pointer++; | |
1100 | expression (&exp); | |
1101 | } | |
b99bd4ef | 1102 | |
c19d1205 ZW |
1103 | if (exp.X_op != O_constant) |
1104 | { | |
1105 | as_bad (_("expected #constant")); | |
1106 | ignore_rest_of_line (); | |
1107 | return FAIL; | |
1108 | } | |
1109 | *val = exp.X_add_number; | |
1110 | return SUCCESS; | |
b99bd4ef | 1111 | } |
c19d1205 | 1112 | #endif |
b99bd4ef | 1113 | |
c19d1205 | 1114 | /* Register parsing. */ |
b99bd4ef | 1115 | |
c19d1205 ZW |
1116 | /* Generic register parser. CCP points to what should be the |
1117 | beginning of a register name. If it is indeed a valid register | |
1118 | name, advance CCP over it and return the reg_entry structure; | |
1119 | otherwise return NULL. Does not issue diagnostics. */ | |
1120 | ||
1121 | static struct reg_entry * | |
1122 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1123 | { |
c19d1205 ZW |
1124 | char *start = *ccp; |
1125 | char *p; | |
1126 | struct reg_entry *reg; | |
b99bd4ef | 1127 | |
c19d1205 ZW |
1128 | #ifdef REGISTER_PREFIX |
1129 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1130 | return NULL; |
c19d1205 ZW |
1131 | start++; |
1132 | #endif | |
1133 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1134 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1135 | start++; | |
1136 | #endif | |
b99bd4ef | 1137 | |
c19d1205 ZW |
1138 | p = start; |
1139 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1140 | return NULL; | |
b99bd4ef | 1141 | |
c19d1205 ZW |
1142 | do |
1143 | p++; | |
1144 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1145 | ||
1146 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1147 | ||
1148 | if (!reg) | |
1149 | return NULL; | |
1150 | ||
1151 | *ccp = p; | |
1152 | return reg; | |
b99bd4ef NC |
1153 | } |
1154 | ||
1155 | static int | |
dcbf9037 JB |
1156 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
1157 | enum arm_reg_type type) | |
b99bd4ef | 1158 | { |
c19d1205 ZW |
1159 | /* Alternative syntaxes are accepted for a few register classes. */ |
1160 | switch (type) | |
1161 | { | |
1162 | case REG_TYPE_MVF: | |
1163 | case REG_TYPE_MVD: | |
1164 | case REG_TYPE_MVFX: | |
1165 | case REG_TYPE_MVDX: | |
1166 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1167 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1168 | return reg->number; |
1169 | break; | |
69b97547 | 1170 | |
c19d1205 ZW |
1171 | case REG_TYPE_CP: |
1172 | /* For backward compatibility, a bare number is valid here. */ | |
1173 | { | |
1174 | unsigned long processor = strtoul (start, ccp, 10); | |
1175 | if (*ccp != start && processor <= 15) | |
1176 | return processor; | |
1177 | } | |
6057a28f | 1178 | |
c19d1205 ZW |
1179 | case REG_TYPE_MMXWC: |
1180 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1181 | instructions that take WC registers. */ | |
79134647 | 1182 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1183 | return reg->number; |
6057a28f | 1184 | break; |
c19d1205 | 1185 | |
6057a28f | 1186 | default: |
c19d1205 | 1187 | break; |
6057a28f NC |
1188 | } |
1189 | ||
dcbf9037 JB |
1190 | return FAIL; |
1191 | } | |
1192 | ||
1193 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1194 | return value is the register number or FAIL. */ | |
1195 | ||
1196 | static int | |
1197 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1198 | { | |
1199 | char *start = *ccp; | |
1200 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1201 | int ret; | |
1202 | ||
1203 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1204 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1205 | return FAIL; | |
1206 | ||
1207 | if (reg && reg->type == type) | |
1208 | return reg->number; | |
1209 | ||
1210 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1211 | return ret; | |
1212 | ||
c19d1205 ZW |
1213 | *ccp = start; |
1214 | return FAIL; | |
1215 | } | |
69b97547 | 1216 | |
dcbf9037 JB |
1217 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1218 | character. Does no verification at this stage that the type fits the opcode | |
1219 | properly. E.g., | |
1220 | ||
1221 | .i32.i32.s16 | |
1222 | .s32.f32 | |
1223 | .u16 | |
1224 | ||
1225 | Can all be legally parsed by this function. | |
1226 | ||
1227 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1228 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1229 | type, FAIL if not. */ | |
1230 | ||
1231 | static int | |
1232 | parse_neon_type (struct neon_type *type, char **str) | |
1233 | { | |
1234 | char *ptr = *str; | |
1235 | ||
1236 | if (type) | |
1237 | type->elems = 0; | |
1238 | ||
1239 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1240 | { | |
1241 | enum neon_el_type thistype = NT_untyped; | |
1242 | unsigned thissize = -1u; | |
1243 | ||
1244 | if (*ptr != '.') | |
1245 | break; | |
1246 | ||
1247 | ptr++; | |
1248 | ||
1249 | /* Just a size without an explicit type. */ | |
1250 | if (ISDIGIT (*ptr)) | |
1251 | goto parsesize; | |
1252 | ||
1253 | switch (TOLOWER (*ptr)) | |
1254 | { | |
1255 | case 'i': thistype = NT_integer; break; | |
1256 | case 'f': thistype = NT_float; break; | |
1257 | case 'p': thistype = NT_poly; break; | |
1258 | case 's': thistype = NT_signed; break; | |
1259 | case 'u': thistype = NT_unsigned; break; | |
037e8744 JB |
1260 | case 'd': |
1261 | thistype = NT_float; | |
1262 | thissize = 64; | |
1263 | ptr++; | |
1264 | goto done; | |
dcbf9037 JB |
1265 | default: |
1266 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1267 | return FAIL; | |
1268 | } | |
1269 | ||
1270 | ptr++; | |
1271 | ||
1272 | /* .f is an abbreviation for .f32. */ | |
1273 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1274 | thissize = 32; | |
1275 | else | |
1276 | { | |
1277 | parsesize: | |
1278 | thissize = strtoul (ptr, &ptr, 10); | |
1279 | ||
1280 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
1281 | && thissize != 64) | |
1282 | { | |
1283 | as_bad (_("bad size %d in type specifier"), thissize); | |
1284 | return FAIL; | |
1285 | } | |
1286 | } | |
1287 | ||
037e8744 | 1288 | done: |
dcbf9037 JB |
1289 | if (type) |
1290 | { | |
1291 | type->el[type->elems].type = thistype; | |
1292 | type->el[type->elems].size = thissize; | |
1293 | type->elems++; | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | /* Empty/missing type is not a successful parse. */ | |
1298 | if (type->elems == 0) | |
1299 | return FAIL; | |
1300 | ||
1301 | *str = ptr; | |
1302 | ||
1303 | return SUCCESS; | |
1304 | } | |
1305 | ||
1306 | /* Errors may be set multiple times during parsing or bit encoding | |
1307 | (particularly in the Neon bits), but usually the earliest error which is set | |
1308 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1309 | errors by calling this function. */ | |
1310 | ||
1311 | static void | |
1312 | first_error (const char *err) | |
1313 | { | |
1314 | if (!inst.error) | |
1315 | inst.error = err; | |
1316 | } | |
1317 | ||
1318 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1319 | static int | |
1320 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1321 | { | |
1322 | char *str = *ccp; | |
1323 | struct neon_type optype; | |
1324 | ||
1325 | if (*str == '.') | |
1326 | { | |
1327 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
1328 | { | |
1329 | if (optype.elems == 1) | |
1330 | *vectype = optype.el[0]; | |
1331 | else | |
1332 | { | |
1333 | first_error (_("only one type should be specified for operand")); | |
1334 | return FAIL; | |
1335 | } | |
1336 | } | |
1337 | else | |
1338 | { | |
1339 | first_error (_("vector type expected")); | |
1340 | return FAIL; | |
1341 | } | |
1342 | } | |
1343 | else | |
1344 | return FAIL; | |
5f4273c7 | 1345 | |
dcbf9037 | 1346 | *ccp = str; |
5f4273c7 | 1347 | |
dcbf9037 JB |
1348 | return SUCCESS; |
1349 | } | |
1350 | ||
1351 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1352 | a 4-bit integer. */ | |
1353 | ||
1354 | #define NEON_ALL_LANES 15 | |
1355 | #define NEON_INTERLEAVE_LANES 14 | |
1356 | ||
1357 | /* Parse either a register or a scalar, with an optional type. Return the | |
1358 | register number, and optionally fill in the actual type of the register | |
1359 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1360 | type/index information in *TYPEINFO. */ | |
1361 | ||
1362 | static int | |
1363 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
1364 | enum arm_reg_type *rtype, | |
1365 | struct neon_typed_alias *typeinfo) | |
1366 | { | |
1367 | char *str = *ccp; | |
1368 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1369 | struct neon_typed_alias atype; | |
1370 | struct neon_type_el parsetype; | |
1371 | ||
1372 | atype.defined = 0; | |
1373 | atype.index = -1; | |
1374 | atype.eltype.type = NT_invtype; | |
1375 | atype.eltype.size = -1; | |
1376 | ||
1377 | /* Try alternate syntax for some types of register. Note these are mutually | |
1378 | exclusive with the Neon syntax extensions. */ | |
1379 | if (reg == NULL) | |
1380 | { | |
1381 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1382 | if (altreg != FAIL) | |
1383 | *ccp = str; | |
1384 | if (typeinfo) | |
1385 | *typeinfo = atype; | |
1386 | return altreg; | |
1387 | } | |
1388 | ||
037e8744 JB |
1389 | /* Undo polymorphism when a set of register types may be accepted. */ |
1390 | if ((type == REG_TYPE_NDQ | |
1391 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1392 | || (type == REG_TYPE_VFSD | |
1393 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
1394 | || (type == REG_TYPE_NSDQ | |
1395 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD | |
f512f76f NC |
1396 | || reg->type == REG_TYPE_NQ)) |
1397 | || (type == REG_TYPE_MMXWC | |
1398 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1399 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1400 | |
1401 | if (type != reg->type) | |
1402 | return FAIL; | |
1403 | ||
1404 | if (reg->neon) | |
1405 | atype = *reg->neon; | |
5f4273c7 | 1406 | |
dcbf9037 JB |
1407 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1408 | { | |
1409 | if ((atype.defined & NTA_HASTYPE) != 0) | |
1410 | { | |
1411 | first_error (_("can't redefine type for operand")); | |
1412 | return FAIL; | |
1413 | } | |
1414 | atype.defined |= NTA_HASTYPE; | |
1415 | atype.eltype = parsetype; | |
1416 | } | |
5f4273c7 | 1417 | |
dcbf9037 JB |
1418 | if (skip_past_char (&str, '[') == SUCCESS) |
1419 | { | |
1420 | if (type != REG_TYPE_VFD) | |
1421 | { | |
1422 | first_error (_("only D registers may be indexed")); | |
1423 | return FAIL; | |
1424 | } | |
5f4273c7 | 1425 | |
dcbf9037 JB |
1426 | if ((atype.defined & NTA_HASINDEX) != 0) |
1427 | { | |
1428 | first_error (_("can't change index for operand")); | |
1429 | return FAIL; | |
1430 | } | |
1431 | ||
1432 | atype.defined |= NTA_HASINDEX; | |
1433 | ||
1434 | if (skip_past_char (&str, ']') == SUCCESS) | |
1435 | atype.index = NEON_ALL_LANES; | |
1436 | else | |
1437 | { | |
1438 | expressionS exp; | |
1439 | ||
1440 | my_get_expression (&exp, &str, GE_NO_PREFIX); | |
1441 | ||
1442 | if (exp.X_op != O_constant) | |
1443 | { | |
1444 | first_error (_("constant expression required")); | |
1445 | return FAIL; | |
1446 | } | |
1447 | ||
1448 | if (skip_past_char (&str, ']') == FAIL) | |
1449 | return FAIL; | |
1450 | ||
1451 | atype.index = exp.X_add_number; | |
1452 | } | |
1453 | } | |
5f4273c7 | 1454 | |
dcbf9037 JB |
1455 | if (typeinfo) |
1456 | *typeinfo = atype; | |
5f4273c7 | 1457 | |
dcbf9037 JB |
1458 | if (rtype) |
1459 | *rtype = type; | |
5f4273c7 | 1460 | |
dcbf9037 | 1461 | *ccp = str; |
5f4273c7 | 1462 | |
dcbf9037 JB |
1463 | return reg->number; |
1464 | } | |
1465 | ||
1466 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1467 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1468 | register (e.g. Neon double or quad reg when either has been requested). | |
1469 | - If this is a Neon vector type with additional type information, fill | |
1470 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1471 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1472 | |
1473 | static int | |
1474 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
1475 | enum arm_reg_type *rtype, struct neon_type_el *vectype) | |
1476 | { | |
1477 | struct neon_typed_alias atype; | |
1478 | char *str = *ccp; | |
1479 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1480 | ||
1481 | if (reg == FAIL) | |
1482 | return FAIL; | |
1483 | ||
0855e32b NS |
1484 | /* Do not allow regname(... to parse as a register. */ |
1485 | if (*str == '(') | |
1486 | return FAIL; | |
1487 | ||
dcbf9037 JB |
1488 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1489 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1490 | { | |
1491 | first_error (_("register operand expected, but got scalar")); | |
1492 | return FAIL; | |
1493 | } | |
1494 | ||
1495 | if (vectype) | |
1496 | *vectype = atype.eltype; | |
1497 | ||
1498 | *ccp = str; | |
1499 | ||
1500 | return reg; | |
1501 | } | |
1502 | ||
1503 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1504 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1505 | ||
5287ad62 JB |
1506 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1507 | have enough information to be able to do a good job bounds-checking. So, we | |
1508 | just do easy checks here, and do further checks later. */ | |
1509 | ||
1510 | static int | |
dcbf9037 | 1511 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1512 | { |
dcbf9037 | 1513 | int reg; |
5287ad62 | 1514 | char *str = *ccp; |
dcbf9037 | 1515 | struct neon_typed_alias atype; |
5f4273c7 | 1516 | |
dcbf9037 | 1517 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1518 | |
dcbf9037 | 1519 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1520 | return FAIL; |
5f4273c7 | 1521 | |
dcbf9037 | 1522 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1523 | { |
dcbf9037 | 1524 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1525 | return FAIL; |
1526 | } | |
dcbf9037 | 1527 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1528 | { |
dcbf9037 | 1529 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1530 | return FAIL; |
1531 | } | |
5f4273c7 | 1532 | |
dcbf9037 JB |
1533 | if (type) |
1534 | *type = atype.eltype; | |
5f4273c7 | 1535 | |
5287ad62 | 1536 | *ccp = str; |
5f4273c7 | 1537 | |
dcbf9037 | 1538 | return reg * 16 + atype.index; |
5287ad62 JB |
1539 | } |
1540 | ||
c19d1205 | 1541 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1542 | |
c19d1205 ZW |
1543 | static long |
1544 | parse_reg_list (char ** strp) | |
1545 | { | |
1546 | char * str = * strp; | |
1547 | long range = 0; | |
1548 | int another_range; | |
a737bd4d | 1549 | |
c19d1205 ZW |
1550 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1551 | do | |
6057a28f | 1552 | { |
c19d1205 | 1553 | another_range = 0; |
a737bd4d | 1554 | |
c19d1205 ZW |
1555 | if (*str == '{') |
1556 | { | |
1557 | int in_range = 0; | |
1558 | int cur_reg = -1; | |
a737bd4d | 1559 | |
c19d1205 ZW |
1560 | str++; |
1561 | do | |
1562 | { | |
1563 | int reg; | |
6057a28f | 1564 | |
dcbf9037 | 1565 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1566 | { |
dcbf9037 | 1567 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1568 | return FAIL; |
1569 | } | |
a737bd4d | 1570 | |
c19d1205 ZW |
1571 | if (in_range) |
1572 | { | |
1573 | int i; | |
a737bd4d | 1574 | |
c19d1205 ZW |
1575 | if (reg <= cur_reg) |
1576 | { | |
dcbf9037 | 1577 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1578 | return FAIL; |
1579 | } | |
40a18ebd | 1580 | |
c19d1205 ZW |
1581 | for (i = cur_reg + 1; i < reg; i++) |
1582 | { | |
1583 | if (range & (1 << i)) | |
1584 | as_tsktsk | |
1585 | (_("Warning: duplicated register (r%d) in register list"), | |
1586 | i); | |
1587 | else | |
1588 | range |= 1 << i; | |
1589 | } | |
1590 | in_range = 0; | |
1591 | } | |
a737bd4d | 1592 | |
c19d1205 ZW |
1593 | if (range & (1 << reg)) |
1594 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1595 | reg); | |
1596 | else if (reg <= cur_reg) | |
1597 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1598 | |
c19d1205 ZW |
1599 | range |= 1 << reg; |
1600 | cur_reg = reg; | |
1601 | } | |
1602 | while (skip_past_comma (&str) != FAIL | |
1603 | || (in_range = 1, *str++ == '-')); | |
1604 | str--; | |
a737bd4d | 1605 | |
c19d1205 ZW |
1606 | if (*str++ != '}') |
1607 | { | |
dcbf9037 | 1608 | first_error (_("missing `}'")); |
c19d1205 ZW |
1609 | return FAIL; |
1610 | } | |
1611 | } | |
1612 | else | |
1613 | { | |
91d6fa6a | 1614 | expressionS exp; |
40a18ebd | 1615 | |
91d6fa6a | 1616 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1617 | return FAIL; |
40a18ebd | 1618 | |
91d6fa6a | 1619 | if (exp.X_op == O_constant) |
c19d1205 | 1620 | { |
91d6fa6a NC |
1621 | if (exp.X_add_number |
1622 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1623 | { |
1624 | inst.error = _("invalid register mask"); | |
1625 | return FAIL; | |
1626 | } | |
a737bd4d | 1627 | |
91d6fa6a | 1628 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1629 | { |
91d6fa6a | 1630 | int regno = range & exp.X_add_number; |
a737bd4d | 1631 | |
c19d1205 ZW |
1632 | regno &= -regno; |
1633 | regno = (1 << regno) - 1; | |
1634 | as_tsktsk | |
1635 | (_("Warning: duplicated register (r%d) in register list"), | |
1636 | regno); | |
1637 | } | |
a737bd4d | 1638 | |
91d6fa6a | 1639 | range |= exp.X_add_number; |
c19d1205 ZW |
1640 | } |
1641 | else | |
1642 | { | |
1643 | if (inst.reloc.type != 0) | |
1644 | { | |
1645 | inst.error = _("expression too complex"); | |
1646 | return FAIL; | |
1647 | } | |
a737bd4d | 1648 | |
91d6fa6a | 1649 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1650 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1651 | inst.reloc.pc_rel = 0; | |
1652 | } | |
1653 | } | |
a737bd4d | 1654 | |
c19d1205 ZW |
1655 | if (*str == '|' || *str == '+') |
1656 | { | |
1657 | str++; | |
1658 | another_range = 1; | |
1659 | } | |
a737bd4d | 1660 | } |
c19d1205 | 1661 | while (another_range); |
a737bd4d | 1662 | |
c19d1205 ZW |
1663 | *strp = str; |
1664 | return range; | |
a737bd4d NC |
1665 | } |
1666 | ||
5287ad62 JB |
1667 | /* Types of registers in a list. */ |
1668 | ||
1669 | enum reg_list_els | |
1670 | { | |
1671 | REGLIST_VFP_S, | |
1672 | REGLIST_VFP_D, | |
1673 | REGLIST_NEON_D | |
1674 | }; | |
1675 | ||
c19d1205 ZW |
1676 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1677 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1678 | register. Parses registers of type ETYPE. |
1679 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1680 | - Q registers can be used to specify pairs of D registers | |
1681 | - { } can be omitted from around a singleton register list | |
1682 | FIXME: This is not implemented, as it would require backtracking in | |
1683 | some cases, e.g.: | |
1684 | vtbl.8 d3,d4,d5 | |
1685 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1686 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1687 | - 32 D registers may be used (also true for VFPv3). |
1688 | FIXME: Types are ignored in these register lists, which is probably a | |
1689 | bug. */ | |
6057a28f | 1690 | |
c19d1205 | 1691 | static int |
037e8744 | 1692 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1693 | { |
037e8744 | 1694 | char *str = *ccp; |
c19d1205 ZW |
1695 | int base_reg; |
1696 | int new_base; | |
21d799b5 | 1697 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1698 | int max_regs = 0; |
c19d1205 ZW |
1699 | int count = 0; |
1700 | int warned = 0; | |
1701 | unsigned long mask = 0; | |
a737bd4d | 1702 | int i; |
6057a28f | 1703 | |
037e8744 | 1704 | if (*str != '{') |
5287ad62 JB |
1705 | { |
1706 | inst.error = _("expecting {"); | |
1707 | return FAIL; | |
1708 | } | |
6057a28f | 1709 | |
037e8744 | 1710 | str++; |
6057a28f | 1711 | |
5287ad62 | 1712 | switch (etype) |
c19d1205 | 1713 | { |
5287ad62 | 1714 | case REGLIST_VFP_S: |
c19d1205 ZW |
1715 | regtype = REG_TYPE_VFS; |
1716 | max_regs = 32; | |
5287ad62 | 1717 | break; |
5f4273c7 | 1718 | |
5287ad62 JB |
1719 | case REGLIST_VFP_D: |
1720 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1721 | break; |
5f4273c7 | 1722 | |
b7fc2769 JB |
1723 | case REGLIST_NEON_D: |
1724 | regtype = REG_TYPE_NDQ; | |
1725 | break; | |
1726 | } | |
1727 | ||
1728 | if (etype != REGLIST_VFP_S) | |
1729 | { | |
b1cc4aeb PB |
1730 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1731 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
5287ad62 JB |
1732 | { |
1733 | max_regs = 32; | |
1734 | if (thumb_mode) | |
1735 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 1736 | fpu_vfp_ext_d32); |
5287ad62 JB |
1737 | else |
1738 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 1739 | fpu_vfp_ext_d32); |
5287ad62 JB |
1740 | } |
1741 | else | |
1742 | max_regs = 16; | |
c19d1205 | 1743 | } |
6057a28f | 1744 | |
c19d1205 | 1745 | base_reg = max_regs; |
a737bd4d | 1746 | |
c19d1205 ZW |
1747 | do |
1748 | { | |
5287ad62 | 1749 | int setmask = 1, addregs = 1; |
dcbf9037 | 1750 | |
037e8744 | 1751 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1752 | |
c19d1205 | 1753 | if (new_base == FAIL) |
a737bd4d | 1754 | { |
dcbf9037 | 1755 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1756 | return FAIL; |
1757 | } | |
5f4273c7 | 1758 | |
b7fc2769 JB |
1759 | if (new_base >= max_regs) |
1760 | { | |
1761 | first_error (_("register out of range in list")); | |
1762 | return FAIL; | |
1763 | } | |
5f4273c7 | 1764 | |
5287ad62 JB |
1765 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1766 | if (regtype == REG_TYPE_NQ) | |
1767 | { | |
1768 | setmask = 3; | |
1769 | addregs = 2; | |
1770 | } | |
1771 | ||
c19d1205 ZW |
1772 | if (new_base < base_reg) |
1773 | base_reg = new_base; | |
a737bd4d | 1774 | |
5287ad62 | 1775 | if (mask & (setmask << new_base)) |
c19d1205 | 1776 | { |
dcbf9037 | 1777 | first_error (_("invalid register list")); |
c19d1205 | 1778 | return FAIL; |
a737bd4d | 1779 | } |
a737bd4d | 1780 | |
c19d1205 ZW |
1781 | if ((mask >> new_base) != 0 && ! warned) |
1782 | { | |
1783 | as_tsktsk (_("register list not in ascending order")); | |
1784 | warned = 1; | |
1785 | } | |
0bbf2aa4 | 1786 | |
5287ad62 JB |
1787 | mask |= setmask << new_base; |
1788 | count += addregs; | |
0bbf2aa4 | 1789 | |
037e8744 | 1790 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1791 | { |
1792 | int high_range; | |
0bbf2aa4 | 1793 | |
037e8744 | 1794 | str++; |
0bbf2aa4 | 1795 | |
037e8744 | 1796 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
dcbf9037 | 1797 | == FAIL) |
c19d1205 ZW |
1798 | { |
1799 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1800 | return FAIL; | |
1801 | } | |
0bbf2aa4 | 1802 | |
b7fc2769 JB |
1803 | if (high_range >= max_regs) |
1804 | { | |
1805 | first_error (_("register out of range in list")); | |
1806 | return FAIL; | |
1807 | } | |
1808 | ||
5287ad62 JB |
1809 | if (regtype == REG_TYPE_NQ) |
1810 | high_range = high_range + 1; | |
1811 | ||
c19d1205 ZW |
1812 | if (high_range <= new_base) |
1813 | { | |
1814 | inst.error = _("register range not in ascending order"); | |
1815 | return FAIL; | |
1816 | } | |
0bbf2aa4 | 1817 | |
5287ad62 | 1818 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1819 | { |
5287ad62 | 1820 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1821 | { |
c19d1205 ZW |
1822 | inst.error = _("invalid register list"); |
1823 | return FAIL; | |
0bbf2aa4 | 1824 | } |
c19d1205 | 1825 | |
5287ad62 JB |
1826 | mask |= setmask << new_base; |
1827 | count += addregs; | |
0bbf2aa4 | 1828 | } |
0bbf2aa4 | 1829 | } |
0bbf2aa4 | 1830 | } |
037e8744 | 1831 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1832 | |
037e8744 | 1833 | str++; |
0bbf2aa4 | 1834 | |
c19d1205 ZW |
1835 | /* Sanity check -- should have raised a parse error above. */ |
1836 | if (count == 0 || count > max_regs) | |
1837 | abort (); | |
1838 | ||
1839 | *pbase = base_reg; | |
1840 | ||
1841 | /* Final test -- the registers must be consecutive. */ | |
1842 | mask >>= base_reg; | |
1843 | for (i = 0; i < count; i++) | |
1844 | { | |
1845 | if ((mask & (1u << i)) == 0) | |
1846 | { | |
1847 | inst.error = _("non-contiguous register range"); | |
1848 | return FAIL; | |
1849 | } | |
1850 | } | |
1851 | ||
037e8744 JB |
1852 | *ccp = str; |
1853 | ||
c19d1205 | 1854 | return count; |
b99bd4ef NC |
1855 | } |
1856 | ||
dcbf9037 JB |
1857 | /* True if two alias types are the same. */ |
1858 | ||
c921be7d | 1859 | static bfd_boolean |
dcbf9037 JB |
1860 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1861 | { | |
1862 | if (!a && !b) | |
c921be7d | 1863 | return TRUE; |
5f4273c7 | 1864 | |
dcbf9037 | 1865 | if (!a || !b) |
c921be7d | 1866 | return FALSE; |
dcbf9037 JB |
1867 | |
1868 | if (a->defined != b->defined) | |
c921be7d | 1869 | return FALSE; |
5f4273c7 | 1870 | |
dcbf9037 JB |
1871 | if ((a->defined & NTA_HASTYPE) != 0 |
1872 | && (a->eltype.type != b->eltype.type | |
1873 | || a->eltype.size != b->eltype.size)) | |
c921be7d | 1874 | return FALSE; |
dcbf9037 JB |
1875 | |
1876 | if ((a->defined & NTA_HASINDEX) != 0 | |
1877 | && (a->index != b->index)) | |
c921be7d | 1878 | return FALSE; |
5f4273c7 | 1879 | |
c921be7d | 1880 | return TRUE; |
dcbf9037 JB |
1881 | } |
1882 | ||
5287ad62 JB |
1883 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1884 | The base register is put in *PBASE. | |
dcbf9037 | 1885 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1886 | the return value. |
1887 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1888 | Bits [6:5] encode the list length (minus one). |
1889 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1890 | |
5287ad62 | 1891 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1892 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1893 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1894 | ||
1895 | static int | |
dcbf9037 JB |
1896 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
1897 | struct neon_type_el *eltype) | |
5287ad62 JB |
1898 | { |
1899 | char *ptr = *str; | |
1900 | int base_reg = -1; | |
1901 | int reg_incr = -1; | |
1902 | int count = 0; | |
1903 | int lane = -1; | |
1904 | int leading_brace = 0; | |
1905 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1906 | const char *const incr_error = _("register stride must be 1 or 2"); |
1907 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1908 | struct neon_typed_alias firsttype; |
5f4273c7 | 1909 | |
5287ad62 JB |
1910 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1911 | leading_brace = 1; | |
5f4273c7 | 1912 | |
5287ad62 JB |
1913 | do |
1914 | { | |
dcbf9037 JB |
1915 | struct neon_typed_alias atype; |
1916 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1917 | ||
5287ad62 JB |
1918 | if (getreg == FAIL) |
1919 | { | |
dcbf9037 | 1920 | first_error (_(reg_expected_msgs[rtype])); |
5287ad62 JB |
1921 | return FAIL; |
1922 | } | |
5f4273c7 | 1923 | |
5287ad62 JB |
1924 | if (base_reg == -1) |
1925 | { | |
1926 | base_reg = getreg; | |
1927 | if (rtype == REG_TYPE_NQ) | |
1928 | { | |
1929 | reg_incr = 1; | |
5287ad62 | 1930 | } |
dcbf9037 | 1931 | firsttype = atype; |
5287ad62 JB |
1932 | } |
1933 | else if (reg_incr == -1) | |
1934 | { | |
1935 | reg_incr = getreg - base_reg; | |
1936 | if (reg_incr < 1 || reg_incr > 2) | |
1937 | { | |
dcbf9037 | 1938 | first_error (_(incr_error)); |
5287ad62 JB |
1939 | return FAIL; |
1940 | } | |
1941 | } | |
1942 | else if (getreg != base_reg + reg_incr * count) | |
1943 | { | |
dcbf9037 JB |
1944 | first_error (_(incr_error)); |
1945 | return FAIL; | |
1946 | } | |
1947 | ||
c921be7d | 1948 | if (! neon_alias_types_same (&atype, &firsttype)) |
dcbf9037 JB |
1949 | { |
1950 | first_error (_(type_error)); | |
5287ad62 JB |
1951 | return FAIL; |
1952 | } | |
5f4273c7 | 1953 | |
5287ad62 JB |
1954 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
1955 | modes. */ | |
1956 | if (ptr[0] == '-') | |
1957 | { | |
dcbf9037 | 1958 | struct neon_typed_alias htype; |
5287ad62 JB |
1959 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
1960 | if (lane == -1) | |
1961 | lane = NEON_INTERLEAVE_LANES; | |
1962 | else if (lane != NEON_INTERLEAVE_LANES) | |
1963 | { | |
dcbf9037 | 1964 | first_error (_(type_error)); |
5287ad62 JB |
1965 | return FAIL; |
1966 | } | |
1967 | if (reg_incr == -1) | |
1968 | reg_incr = 1; | |
1969 | else if (reg_incr != 1) | |
1970 | { | |
dcbf9037 | 1971 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
5287ad62 JB |
1972 | return FAIL; |
1973 | } | |
1974 | ptr++; | |
dcbf9037 | 1975 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
5287ad62 JB |
1976 | if (hireg == FAIL) |
1977 | { | |
dcbf9037 JB |
1978 | first_error (_(reg_expected_msgs[rtype])); |
1979 | return FAIL; | |
1980 | } | |
c921be7d | 1981 | if (! neon_alias_types_same (&htype, &firsttype)) |
dcbf9037 JB |
1982 | { |
1983 | first_error (_(type_error)); | |
5287ad62 JB |
1984 | return FAIL; |
1985 | } | |
1986 | count += hireg + dregs - getreg; | |
1987 | continue; | |
1988 | } | |
5f4273c7 | 1989 | |
5287ad62 JB |
1990 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
1991 | if (rtype == REG_TYPE_NQ) | |
1992 | { | |
1993 | count += 2; | |
1994 | continue; | |
1995 | } | |
5f4273c7 | 1996 | |
dcbf9037 | 1997 | if ((atype.defined & NTA_HASINDEX) != 0) |
5287ad62 | 1998 | { |
dcbf9037 JB |
1999 | if (lane == -1) |
2000 | lane = atype.index; | |
2001 | else if (lane != atype.index) | |
5287ad62 | 2002 | { |
dcbf9037 JB |
2003 | first_error (_(type_error)); |
2004 | return FAIL; | |
5287ad62 JB |
2005 | } |
2006 | } | |
2007 | else if (lane == -1) | |
2008 | lane = NEON_INTERLEAVE_LANES; | |
2009 | else if (lane != NEON_INTERLEAVE_LANES) | |
2010 | { | |
dcbf9037 | 2011 | first_error (_(type_error)); |
5287ad62 JB |
2012 | return FAIL; |
2013 | } | |
2014 | count++; | |
2015 | } | |
2016 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2017 | |
5287ad62 JB |
2018 | /* No lane set by [x]. We must be interleaving structures. */ |
2019 | if (lane == -1) | |
2020 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2021 | |
5287ad62 JB |
2022 | /* Sanity check. */ |
2023 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2024 | || (count > 1 && reg_incr == -1)) | |
2025 | { | |
dcbf9037 | 2026 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2027 | return FAIL; |
2028 | } | |
2029 | ||
2030 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2031 | { | |
dcbf9037 | 2032 | first_error (_("expected }")); |
5287ad62 JB |
2033 | return FAIL; |
2034 | } | |
5f4273c7 | 2035 | |
5287ad62 JB |
2036 | if (reg_incr == -1) |
2037 | reg_incr = 1; | |
2038 | ||
dcbf9037 JB |
2039 | if (eltype) |
2040 | *eltype = firsttype.eltype; | |
2041 | ||
5287ad62 JB |
2042 | *pbase = base_reg; |
2043 | *str = ptr; | |
5f4273c7 | 2044 | |
5287ad62 JB |
2045 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2046 | } | |
2047 | ||
c19d1205 ZW |
2048 | /* Parse an explicit relocation suffix on an expression. This is |
2049 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2050 | arm_reloc_hsh contains no entries, so this function can only | |
2051 | succeed if there is no () after the word. Returns -1 on error, | |
2052 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
2053 | static int | |
2054 | parse_reloc (char **str) | |
b99bd4ef | 2055 | { |
c19d1205 ZW |
2056 | struct reloc_entry *r; |
2057 | char *p, *q; | |
b99bd4ef | 2058 | |
c19d1205 ZW |
2059 | if (**str != '(') |
2060 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2061 | |
c19d1205 ZW |
2062 | p = *str + 1; |
2063 | q = p; | |
2064 | ||
2065 | while (*q && *q != ')' && *q != ',') | |
2066 | q++; | |
2067 | if (*q != ')') | |
2068 | return -1; | |
2069 | ||
21d799b5 NC |
2070 | if ((r = (struct reloc_entry *) |
2071 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2072 | return -1; |
2073 | ||
2074 | *str = q + 1; | |
2075 | return r->reloc; | |
b99bd4ef NC |
2076 | } |
2077 | ||
c19d1205 ZW |
2078 | /* Directives: register aliases. */ |
2079 | ||
dcbf9037 | 2080 | static struct reg_entry * |
90ec0d68 | 2081 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2082 | { |
d3ce72d0 | 2083 | struct reg_entry *new_reg; |
c19d1205 | 2084 | const char *name; |
b99bd4ef | 2085 | |
d3ce72d0 | 2086 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2087 | { |
d3ce72d0 | 2088 | if (new_reg->builtin) |
c19d1205 | 2089 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2090 | |
c19d1205 ZW |
2091 | /* Only warn about a redefinition if it's not defined as the |
2092 | same register. */ | |
d3ce72d0 | 2093 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2094 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2095 | |
d929913e | 2096 | return NULL; |
c19d1205 | 2097 | } |
b99bd4ef | 2098 | |
c19d1205 | 2099 | name = xstrdup (str); |
d3ce72d0 | 2100 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2101 | |
d3ce72d0 NC |
2102 | new_reg->name = name; |
2103 | new_reg->number = number; | |
2104 | new_reg->type = type; | |
2105 | new_reg->builtin = FALSE; | |
2106 | new_reg->neon = NULL; | |
b99bd4ef | 2107 | |
d3ce72d0 | 2108 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2109 | abort (); |
5f4273c7 | 2110 | |
d3ce72d0 | 2111 | return new_reg; |
dcbf9037 JB |
2112 | } |
2113 | ||
2114 | static void | |
2115 | insert_neon_reg_alias (char *str, int number, int type, | |
2116 | struct neon_typed_alias *atype) | |
2117 | { | |
2118 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2119 | |
dcbf9037 JB |
2120 | if (!reg) |
2121 | { | |
2122 | first_error (_("attempt to redefine typed alias")); | |
2123 | return; | |
2124 | } | |
5f4273c7 | 2125 | |
dcbf9037 JB |
2126 | if (atype) |
2127 | { | |
21d799b5 NC |
2128 | reg->neon = (struct neon_typed_alias *) |
2129 | xmalloc (sizeof (struct neon_typed_alias)); | |
dcbf9037 JB |
2130 | *reg->neon = *atype; |
2131 | } | |
c19d1205 | 2132 | } |
b99bd4ef | 2133 | |
c19d1205 | 2134 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2135 | |
c19d1205 | 2136 | new_register_name .req existing_register_name |
b99bd4ef | 2137 | |
c19d1205 | 2138 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2139 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2140 | |
d929913e | 2141 | static bfd_boolean |
c19d1205 ZW |
2142 | create_register_alias (char * newname, char *p) |
2143 | { | |
2144 | struct reg_entry *old; | |
2145 | char *oldname, *nbuf; | |
2146 | size_t nlen; | |
b99bd4ef | 2147 | |
c19d1205 ZW |
2148 | /* The input scrubber ensures that whitespace after the mnemonic is |
2149 | collapsed to single spaces. */ | |
2150 | oldname = p; | |
2151 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2152 | return FALSE; |
b99bd4ef | 2153 | |
c19d1205 ZW |
2154 | oldname += 6; |
2155 | if (*oldname == '\0') | |
d929913e | 2156 | return FALSE; |
b99bd4ef | 2157 | |
21d799b5 | 2158 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2159 | if (!old) |
b99bd4ef | 2160 | { |
c19d1205 | 2161 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2162 | return TRUE; |
b99bd4ef NC |
2163 | } |
2164 | ||
c19d1205 ZW |
2165 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2166 | the desired alias name, and p points to its end. If not, then | |
2167 | the desired alias name is in the global original_case_string. */ | |
2168 | #ifdef TC_CASE_SENSITIVE | |
2169 | nlen = p - newname; | |
2170 | #else | |
2171 | newname = original_case_string; | |
2172 | nlen = strlen (newname); | |
2173 | #endif | |
b99bd4ef | 2174 | |
21d799b5 | 2175 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2176 | memcpy (nbuf, newname, nlen); |
2177 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2178 | |
c19d1205 ZW |
2179 | /* Create aliases under the new name as stated; an all-lowercase |
2180 | version of the new name; and an all-uppercase version of the new | |
2181 | name. */ | |
d929913e NC |
2182 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2183 | { | |
2184 | for (p = nbuf; *p; p++) | |
2185 | *p = TOUPPER (*p); | |
c19d1205 | 2186 | |
d929913e NC |
2187 | if (strncmp (nbuf, newname, nlen)) |
2188 | { | |
2189 | /* If this attempt to create an additional alias fails, do not bother | |
2190 | trying to create the all-lower case alias. We will fail and issue | |
2191 | a second, duplicate error message. This situation arises when the | |
2192 | programmer does something like: | |
2193 | foo .req r0 | |
2194 | Foo .req r1 | |
2195 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2196 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2197 | first .req. */ |
2198 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2199 | return TRUE; | |
2200 | } | |
c19d1205 | 2201 | |
d929913e NC |
2202 | for (p = nbuf; *p; p++) |
2203 | *p = TOLOWER (*p); | |
c19d1205 | 2204 | |
d929913e NC |
2205 | if (strncmp (nbuf, newname, nlen)) |
2206 | insert_reg_alias (nbuf, old->number, old->type); | |
2207 | } | |
c19d1205 | 2208 | |
d929913e | 2209 | return TRUE; |
b99bd4ef NC |
2210 | } |
2211 | ||
dcbf9037 JB |
2212 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2213 | X .dn d5.s32[1] | |
2214 | Y .qn 6.s16 | |
2215 | Z .dn d7 | |
2216 | T .dn Z[0] | |
2217 | These typed registers can be used instead of the types specified after the | |
2218 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2219 | specified directly, e.g.: | |
5f4273c7 | 2220 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2221 | |
c921be7d | 2222 | static bfd_boolean |
dcbf9037 JB |
2223 | create_neon_reg_alias (char *newname, char *p) |
2224 | { | |
2225 | enum arm_reg_type basetype; | |
2226 | struct reg_entry *basereg; | |
2227 | struct reg_entry mybasereg; | |
2228 | struct neon_type ntype; | |
2229 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2230 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2231 | int namelen; |
5f4273c7 | 2232 | |
dcbf9037 JB |
2233 | typeinfo.defined = 0; |
2234 | typeinfo.eltype.type = NT_invtype; | |
2235 | typeinfo.eltype.size = -1; | |
2236 | typeinfo.index = -1; | |
5f4273c7 | 2237 | |
dcbf9037 | 2238 | nameend = p; |
5f4273c7 | 2239 | |
dcbf9037 JB |
2240 | if (strncmp (p, " .dn ", 5) == 0) |
2241 | basetype = REG_TYPE_VFD; | |
2242 | else if (strncmp (p, " .qn ", 5) == 0) | |
2243 | basetype = REG_TYPE_NQ; | |
2244 | else | |
c921be7d | 2245 | return FALSE; |
5f4273c7 | 2246 | |
dcbf9037 | 2247 | p += 5; |
5f4273c7 | 2248 | |
dcbf9037 | 2249 | if (*p == '\0') |
c921be7d | 2250 | return FALSE; |
5f4273c7 | 2251 | |
dcbf9037 JB |
2252 | basereg = arm_reg_parse_multi (&p); |
2253 | ||
2254 | if (basereg && basereg->type != basetype) | |
2255 | { | |
2256 | as_bad (_("bad type for register")); | |
c921be7d | 2257 | return FALSE; |
dcbf9037 JB |
2258 | } |
2259 | ||
2260 | if (basereg == NULL) | |
2261 | { | |
2262 | expressionS exp; | |
2263 | /* Try parsing as an integer. */ | |
2264 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2265 | if (exp.X_op != O_constant) | |
2266 | { | |
2267 | as_bad (_("expression must be constant")); | |
c921be7d | 2268 | return FALSE; |
dcbf9037 JB |
2269 | } |
2270 | basereg = &mybasereg; | |
2271 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
2272 | : exp.X_add_number; | |
2273 | basereg->neon = 0; | |
2274 | } | |
2275 | ||
2276 | if (basereg->neon) | |
2277 | typeinfo = *basereg->neon; | |
2278 | ||
2279 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2280 | { | |
2281 | /* We got a type. */ | |
2282 | if (typeinfo.defined & NTA_HASTYPE) | |
2283 | { | |
2284 | as_bad (_("can't redefine the type of a register alias")); | |
c921be7d | 2285 | return FALSE; |
dcbf9037 | 2286 | } |
5f4273c7 | 2287 | |
dcbf9037 JB |
2288 | typeinfo.defined |= NTA_HASTYPE; |
2289 | if (ntype.elems != 1) | |
2290 | { | |
2291 | as_bad (_("you must specify a single type only")); | |
c921be7d | 2292 | return FALSE; |
dcbf9037 JB |
2293 | } |
2294 | typeinfo.eltype = ntype.el[0]; | |
2295 | } | |
5f4273c7 | 2296 | |
dcbf9037 JB |
2297 | if (skip_past_char (&p, '[') == SUCCESS) |
2298 | { | |
2299 | expressionS exp; | |
2300 | /* We got a scalar index. */ | |
5f4273c7 | 2301 | |
dcbf9037 JB |
2302 | if (typeinfo.defined & NTA_HASINDEX) |
2303 | { | |
2304 | as_bad (_("can't redefine the index of a scalar alias")); | |
c921be7d | 2305 | return FALSE; |
dcbf9037 | 2306 | } |
5f4273c7 | 2307 | |
dcbf9037 | 2308 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2309 | |
dcbf9037 JB |
2310 | if (exp.X_op != O_constant) |
2311 | { | |
2312 | as_bad (_("scalar index must be constant")); | |
c921be7d | 2313 | return FALSE; |
dcbf9037 | 2314 | } |
5f4273c7 | 2315 | |
dcbf9037 JB |
2316 | typeinfo.defined |= NTA_HASINDEX; |
2317 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2318 | |
dcbf9037 JB |
2319 | if (skip_past_char (&p, ']') == FAIL) |
2320 | { | |
2321 | as_bad (_("expecting ]")); | |
c921be7d | 2322 | return FALSE; |
dcbf9037 JB |
2323 | } |
2324 | } | |
2325 | ||
15735687 NS |
2326 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2327 | the desired alias name, and p points to its end. If not, then | |
2328 | the desired alias name is in the global original_case_string. */ | |
2329 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2330 | namelen = nameend - newname; |
15735687 NS |
2331 | #else |
2332 | newname = original_case_string; | |
2333 | namelen = strlen (newname); | |
2334 | #endif | |
2335 | ||
21d799b5 | 2336 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2337 | strncpy (namebuf, newname, namelen); |
2338 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2339 | |
dcbf9037 JB |
2340 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
2341 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2342 | |
dcbf9037 JB |
2343 | /* Insert name in all uppercase. */ |
2344 | for (p = namebuf; *p; p++) | |
2345 | *p = TOUPPER (*p); | |
5f4273c7 | 2346 | |
dcbf9037 JB |
2347 | if (strncmp (namebuf, newname, namelen)) |
2348 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2349 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2350 | |
dcbf9037 JB |
2351 | /* Insert name in all lowercase. */ |
2352 | for (p = namebuf; *p; p++) | |
2353 | *p = TOLOWER (*p); | |
5f4273c7 | 2354 | |
dcbf9037 JB |
2355 | if (strncmp (namebuf, newname, namelen)) |
2356 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2357 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2358 | |
c921be7d | 2359 | return TRUE; |
dcbf9037 JB |
2360 | } |
2361 | ||
c19d1205 ZW |
2362 | /* Should never be called, as .req goes between the alias and the |
2363 | register name, not at the beginning of the line. */ | |
c921be7d | 2364 | |
b99bd4ef | 2365 | static void |
c19d1205 | 2366 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2367 | { |
c19d1205 ZW |
2368 | as_bad (_("invalid syntax for .req directive")); |
2369 | } | |
b99bd4ef | 2370 | |
dcbf9037 JB |
2371 | static void |
2372 | s_dn (int a ATTRIBUTE_UNUSED) | |
2373 | { | |
2374 | as_bad (_("invalid syntax for .dn directive")); | |
2375 | } | |
2376 | ||
2377 | static void | |
2378 | s_qn (int a ATTRIBUTE_UNUSED) | |
2379 | { | |
2380 | as_bad (_("invalid syntax for .qn directive")); | |
2381 | } | |
2382 | ||
c19d1205 ZW |
2383 | /* The .unreq directive deletes an alias which was previously defined |
2384 | by .req. For example: | |
b99bd4ef | 2385 | |
c19d1205 ZW |
2386 | my_alias .req r11 |
2387 | .unreq my_alias */ | |
b99bd4ef NC |
2388 | |
2389 | static void | |
c19d1205 | 2390 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2391 | { |
c19d1205 ZW |
2392 | char * name; |
2393 | char saved_char; | |
b99bd4ef | 2394 | |
c19d1205 ZW |
2395 | name = input_line_pointer; |
2396 | ||
2397 | while (*input_line_pointer != 0 | |
2398 | && *input_line_pointer != ' ' | |
2399 | && *input_line_pointer != '\n') | |
2400 | ++input_line_pointer; | |
2401 | ||
2402 | saved_char = *input_line_pointer; | |
2403 | *input_line_pointer = 0; | |
2404 | ||
2405 | if (!*name) | |
2406 | as_bad (_("invalid syntax for .unreq directive")); | |
2407 | else | |
2408 | { | |
21d799b5 NC |
2409 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
2410 | name); | |
c19d1205 ZW |
2411 | |
2412 | if (!reg) | |
2413 | as_bad (_("unknown register alias '%s'"), name); | |
2414 | else if (reg->builtin) | |
a1727c1a | 2415 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2416 | name); |
2417 | else | |
2418 | { | |
d929913e NC |
2419 | char * p; |
2420 | char * nbuf; | |
2421 | ||
db0bc284 | 2422 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2423 | free ((char *) reg->name); |
dcbf9037 JB |
2424 | if (reg->neon) |
2425 | free (reg->neon); | |
c19d1205 | 2426 | free (reg); |
d929913e NC |
2427 | |
2428 | /* Also locate the all upper case and all lower case versions. | |
2429 | Do not complain if we cannot find one or the other as it | |
2430 | was probably deleted above. */ | |
5f4273c7 | 2431 | |
d929913e NC |
2432 | nbuf = strdup (name); |
2433 | for (p = nbuf; *p; p++) | |
2434 | *p = TOUPPER (*p); | |
21d799b5 | 2435 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2436 | if (reg) |
2437 | { | |
db0bc284 | 2438 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2439 | free ((char *) reg->name); |
2440 | if (reg->neon) | |
2441 | free (reg->neon); | |
2442 | free (reg); | |
2443 | } | |
2444 | ||
2445 | for (p = nbuf; *p; p++) | |
2446 | *p = TOLOWER (*p); | |
21d799b5 | 2447 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2448 | if (reg) |
2449 | { | |
db0bc284 | 2450 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2451 | free ((char *) reg->name); |
2452 | if (reg->neon) | |
2453 | free (reg->neon); | |
2454 | free (reg); | |
2455 | } | |
2456 | ||
2457 | free (nbuf); | |
c19d1205 ZW |
2458 | } |
2459 | } | |
b99bd4ef | 2460 | |
c19d1205 | 2461 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2462 | demand_empty_rest_of_line (); |
2463 | } | |
2464 | ||
c19d1205 ZW |
2465 | /* Directives: Instruction set selection. */ |
2466 | ||
2467 | #ifdef OBJ_ELF | |
2468 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2469 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2470 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2471 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2472 | ||
cd000bff DJ |
2473 | /* Create a new mapping symbol for the transition to STATE. */ |
2474 | ||
2475 | static void | |
2476 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2477 | { |
a737bd4d | 2478 | symbolS * symbolP; |
c19d1205 ZW |
2479 | const char * symname; |
2480 | int type; | |
b99bd4ef | 2481 | |
c19d1205 | 2482 | switch (state) |
b99bd4ef | 2483 | { |
c19d1205 ZW |
2484 | case MAP_DATA: |
2485 | symname = "$d"; | |
2486 | type = BSF_NO_FLAGS; | |
2487 | break; | |
2488 | case MAP_ARM: | |
2489 | symname = "$a"; | |
2490 | type = BSF_NO_FLAGS; | |
2491 | break; | |
2492 | case MAP_THUMB: | |
2493 | symname = "$t"; | |
2494 | type = BSF_NO_FLAGS; | |
2495 | break; | |
c19d1205 ZW |
2496 | default: |
2497 | abort (); | |
2498 | } | |
2499 | ||
cd000bff | 2500 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2501 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2502 | ||
2503 | switch (state) | |
2504 | { | |
2505 | case MAP_ARM: | |
2506 | THUMB_SET_FUNC (symbolP, 0); | |
2507 | ARM_SET_THUMB (symbolP, 0); | |
2508 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2509 | break; | |
2510 | ||
2511 | case MAP_THUMB: | |
2512 | THUMB_SET_FUNC (symbolP, 1); | |
2513 | ARM_SET_THUMB (symbolP, 1); | |
2514 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2515 | break; | |
2516 | ||
2517 | case MAP_DATA: | |
2518 | default: | |
cd000bff DJ |
2519 | break; |
2520 | } | |
2521 | ||
2522 | /* Save the mapping symbols for future reference. Also check that | |
2523 | we do not place two mapping symbols at the same offset within a | |
2524 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2525 | check_mapping_symbols. |
2526 | ||
2527 | If .fill or other data filling directive generates zero sized data, | |
2528 | the mapping symbol for the following code will have the same value | |
2529 | as the one generated for the data filling directive. In this case, | |
2530 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2531 | if (value == 0) |
2532 | { | |
2de7820f JZ |
2533 | if (frag->tc_frag_data.first_map != NULL) |
2534 | { | |
2535 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2536 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2537 | } | |
cd000bff DJ |
2538 | frag->tc_frag_data.first_map = symbolP; |
2539 | } | |
2540 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2541 | { |
2542 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2543 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2544 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2545 | } | |
cd000bff DJ |
2546 | frag->tc_frag_data.last_map = symbolP; |
2547 | } | |
2548 | ||
2549 | /* We must sometimes convert a region marked as code to data during | |
2550 | code alignment, if an odd number of bytes have to be padded. The | |
2551 | code mapping symbol is pushed to an aligned address. */ | |
2552 | ||
2553 | static void | |
2554 | insert_data_mapping_symbol (enum mstate state, | |
2555 | valueT value, fragS *frag, offsetT bytes) | |
2556 | { | |
2557 | /* If there was already a mapping symbol, remove it. */ | |
2558 | if (frag->tc_frag_data.last_map != NULL | |
2559 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2560 | { | |
2561 | symbolS *symp = frag->tc_frag_data.last_map; | |
2562 | ||
2563 | if (value == 0) | |
2564 | { | |
2565 | know (frag->tc_frag_data.first_map == symp); | |
2566 | frag->tc_frag_data.first_map = NULL; | |
2567 | } | |
2568 | frag->tc_frag_data.last_map = NULL; | |
2569 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2570 | } |
cd000bff DJ |
2571 | |
2572 | make_mapping_symbol (MAP_DATA, value, frag); | |
2573 | make_mapping_symbol (state, value + bytes, frag); | |
2574 | } | |
2575 | ||
2576 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2577 | ||
2578 | /* Set the mapping state to STATE. Only call this when about to | |
2579 | emit some STATE bytes to the file. */ | |
2580 | ||
2581 | void | |
2582 | mapping_state (enum mstate state) | |
2583 | { | |
940b5ce0 DJ |
2584 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2585 | ||
cd000bff DJ |
2586 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
2587 | ||
2588 | if (mapstate == state) | |
2589 | /* The mapping symbol has already been emitted. | |
2590 | There is nothing else to do. */ | |
2591 | return; | |
2592 | else if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
2593 | /* This case will be evaluated later in the next else. */ | |
2594 | return; | |
2595 | else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) | |
2596 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2597 | { | |
2598 | /* Only add the symbol if the offset is > 0: | |
2599 | if we're at the first frag, check it's size > 0; | |
2600 | if we're not at the first frag, then for sure | |
2601 | the offset is > 0. */ | |
2602 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2603 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2604 | ||
2605 | if (add_symbol) | |
2606 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2607 | } | |
2608 | ||
2609 | mapping_state_2 (state, 0); | |
2610 | #undef TRANSITION | |
2611 | } | |
2612 | ||
2613 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2614 | allocated. Put the mapping symbol that far back. */ | |
2615 | ||
2616 | static void | |
2617 | mapping_state_2 (enum mstate state, int max_chars) | |
2618 | { | |
940b5ce0 DJ |
2619 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2620 | ||
2621 | if (!SEG_NORMAL (now_seg)) | |
2622 | return; | |
2623 | ||
cd000bff DJ |
2624 | if (mapstate == state) |
2625 | /* The mapping symbol has already been emitted. | |
2626 | There is nothing else to do. */ | |
2627 | return; | |
2628 | ||
cd000bff DJ |
2629 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2630 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 ZW |
2631 | } |
2632 | #else | |
d3106081 NS |
2633 | #define mapping_state(x) ((void)0) |
2634 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2635 | #endif |
2636 | ||
2637 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2638 | ||
4343666d | 2639 | #ifdef OBJ_COFF |
c19d1205 ZW |
2640 | static symbolS * |
2641 | find_real_start (symbolS * symbolP) | |
2642 | { | |
2643 | char * real_start; | |
2644 | const char * name = S_GET_NAME (symbolP); | |
2645 | symbolS * new_target; | |
2646 | ||
2647 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2648 | #define STUB_NAME ".real_start_of" | |
2649 | ||
2650 | if (name == NULL) | |
2651 | abort (); | |
2652 | ||
37f6032b ZW |
2653 | /* The compiler may generate BL instructions to local labels because |
2654 | it needs to perform a branch to a far away location. These labels | |
2655 | do not have a corresponding ".real_start_of" label. We check | |
2656 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2657 | the ".real_start_of" convention for nonlocal branches. */ | |
2658 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2659 | return symbolP; |
2660 | ||
37f6032b | 2661 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2662 | new_target = symbol_find (real_start); |
2663 | ||
2664 | if (new_target == NULL) | |
2665 | { | |
bd3ba5d1 | 2666 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2667 | new_target = symbolP; |
2668 | } | |
2669 | ||
c19d1205 ZW |
2670 | return new_target; |
2671 | } | |
4343666d | 2672 | #endif |
c19d1205 ZW |
2673 | |
2674 | static void | |
2675 | opcode_select (int width) | |
2676 | { | |
2677 | switch (width) | |
2678 | { | |
2679 | case 16: | |
2680 | if (! thumb_mode) | |
2681 | { | |
e74cfd16 | 2682 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2683 | as_bad (_("selected processor does not support THUMB opcodes")); |
2684 | ||
2685 | thumb_mode = 1; | |
2686 | /* No need to force the alignment, since we will have been | |
2687 | coming from ARM mode, which is word-aligned. */ | |
2688 | record_alignment (now_seg, 1); | |
2689 | } | |
c19d1205 ZW |
2690 | break; |
2691 | ||
2692 | case 32: | |
2693 | if (thumb_mode) | |
2694 | { | |
e74cfd16 | 2695 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2696 | as_bad (_("selected processor does not support ARM opcodes")); |
2697 | ||
2698 | thumb_mode = 0; | |
2699 | ||
2700 | if (!need_pass_2) | |
2701 | frag_align (2, 0, 0); | |
2702 | ||
2703 | record_alignment (now_seg, 1); | |
2704 | } | |
c19d1205 ZW |
2705 | break; |
2706 | ||
2707 | default: | |
2708 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2709 | } | |
2710 | } | |
2711 | ||
2712 | static void | |
2713 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2714 | { | |
2715 | opcode_select (32); | |
2716 | demand_empty_rest_of_line (); | |
2717 | } | |
2718 | ||
2719 | static void | |
2720 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2721 | { | |
2722 | opcode_select (16); | |
2723 | demand_empty_rest_of_line (); | |
2724 | } | |
2725 | ||
2726 | static void | |
2727 | s_code (int unused ATTRIBUTE_UNUSED) | |
2728 | { | |
2729 | int temp; | |
2730 | ||
2731 | temp = get_absolute_expression (); | |
2732 | switch (temp) | |
2733 | { | |
2734 | case 16: | |
2735 | case 32: | |
2736 | opcode_select (temp); | |
2737 | break; | |
2738 | ||
2739 | default: | |
2740 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2741 | } | |
2742 | } | |
2743 | ||
2744 | static void | |
2745 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2746 | { | |
2747 | /* If we are not already in thumb mode go into it, EVEN if | |
2748 | the target processor does not support thumb instructions. | |
2749 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2750 | to compile interworking support functions even if the | |
2751 | target processor should not support interworking. */ | |
2752 | if (! thumb_mode) | |
2753 | { | |
2754 | thumb_mode = 2; | |
2755 | record_alignment (now_seg, 1); | |
2756 | } | |
2757 | ||
2758 | demand_empty_rest_of_line (); | |
2759 | } | |
2760 | ||
2761 | static void | |
2762 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2763 | { | |
2764 | s_thumb (0); | |
2765 | ||
2766 | /* The following label is the name/address of the start of a Thumb function. | |
2767 | We need to know this for the interworking support. */ | |
2768 | label_is_thumb_function_name = TRUE; | |
2769 | } | |
2770 | ||
2771 | /* Perform a .set directive, but also mark the alias as | |
2772 | being a thumb function. */ | |
2773 | ||
2774 | static void | |
2775 | s_thumb_set (int equiv) | |
2776 | { | |
2777 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2778 | We cannot just call that code as we need to get at the symbol that | |
2779 | is created. */ | |
2780 | char * name; | |
2781 | char delim; | |
2782 | char * end_name; | |
2783 | symbolS * symbolP; | |
2784 | ||
2785 | /* Especial apologies for the random logic: | |
2786 | This just grew, and could be parsed much more simply! | |
2787 | Dean - in haste. */ | |
2788 | name = input_line_pointer; | |
2789 | delim = get_symbol_end (); | |
2790 | end_name = input_line_pointer; | |
2791 | *end_name = delim; | |
2792 | ||
2793 | if (*input_line_pointer != ',') | |
2794 | { | |
2795 | *end_name = 0; | |
2796 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2797 | *end_name = delim; |
2798 | ignore_rest_of_line (); | |
2799 | return; | |
2800 | } | |
2801 | ||
2802 | input_line_pointer++; | |
2803 | *end_name = 0; | |
2804 | ||
2805 | if (name[0] == '.' && name[1] == '\0') | |
2806 | { | |
2807 | /* XXX - this should not happen to .thumb_set. */ | |
2808 | abort (); | |
2809 | } | |
2810 | ||
2811 | if ((symbolP = symbol_find (name)) == NULL | |
2812 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2813 | { | |
2814 | #ifndef NO_LISTING | |
2815 | /* When doing symbol listings, play games with dummy fragments living | |
2816 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2817 | for this symbol. */ |
b99bd4ef NC |
2818 | if (listing & LISTING_SYMBOLS) |
2819 | { | |
2820 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2821 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2822 | |
2823 | memset (dummy_frag, 0, sizeof (fragS)); | |
2824 | dummy_frag->fr_type = rs_fill; | |
2825 | dummy_frag->line = listing_tail; | |
2826 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2827 | dummy_frag->fr_symbol = symbolP; | |
2828 | } | |
2829 | else | |
2830 | #endif | |
2831 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2832 | ||
2833 | #ifdef OBJ_COFF | |
2834 | /* "set" symbols are local unless otherwise specified. */ | |
2835 | SF_SET_LOCAL (symbolP); | |
2836 | #endif /* OBJ_COFF */ | |
2837 | } /* Make a new symbol. */ | |
2838 | ||
2839 | symbol_table_insert (symbolP); | |
2840 | ||
2841 | * end_name = delim; | |
2842 | ||
2843 | if (equiv | |
2844 | && S_IS_DEFINED (symbolP) | |
2845 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2846 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2847 | ||
2848 | pseudo_set (symbolP); | |
2849 | ||
2850 | demand_empty_rest_of_line (); | |
2851 | ||
c19d1205 | 2852 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2853 | |
2854 | THUMB_SET_FUNC (symbolP, 1); | |
2855 | ARM_SET_THUMB (symbolP, 1); | |
2856 | #if defined OBJ_ELF || defined OBJ_COFF | |
2857 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2858 | #endif | |
2859 | } | |
2860 | ||
c19d1205 | 2861 | /* Directives: Mode selection. */ |
b99bd4ef | 2862 | |
c19d1205 ZW |
2863 | /* .syntax [unified|divided] - choose the new unified syntax |
2864 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2865 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2866 | static void |
c19d1205 | 2867 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2868 | { |
c19d1205 ZW |
2869 | char *name, delim; |
2870 | ||
2871 | name = input_line_pointer; | |
2872 | delim = get_symbol_end (); | |
2873 | ||
2874 | if (!strcasecmp (name, "unified")) | |
2875 | unified_syntax = TRUE; | |
2876 | else if (!strcasecmp (name, "divided")) | |
2877 | unified_syntax = FALSE; | |
2878 | else | |
2879 | { | |
2880 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2881 | return; | |
2882 | } | |
2883 | *input_line_pointer = delim; | |
b99bd4ef NC |
2884 | demand_empty_rest_of_line (); |
2885 | } | |
2886 | ||
c19d1205 ZW |
2887 | /* Directives: sectioning and alignment. */ |
2888 | ||
2889 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2890 | ||
b99bd4ef | 2891 | static void |
c19d1205 | 2892 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2893 | { |
a737bd4d | 2894 | int temp; |
dce323d1 | 2895 | bfd_boolean fill_p; |
c19d1205 ZW |
2896 | long temp_fill; |
2897 | long max_alignment = 15; | |
b99bd4ef NC |
2898 | |
2899 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2900 | if (temp > max_alignment) |
2901 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2902 | else if (temp < 0) | |
b99bd4ef | 2903 | { |
c19d1205 ZW |
2904 | as_bad (_("alignment negative. 0 assumed.")); |
2905 | temp = 0; | |
2906 | } | |
b99bd4ef | 2907 | |
c19d1205 ZW |
2908 | if (*input_line_pointer == ',') |
2909 | { | |
2910 | input_line_pointer++; | |
2911 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2912 | fill_p = TRUE; |
b99bd4ef | 2913 | } |
c19d1205 | 2914 | else |
dce323d1 PB |
2915 | { |
2916 | fill_p = FALSE; | |
2917 | temp_fill = 0; | |
2918 | } | |
b99bd4ef | 2919 | |
c19d1205 ZW |
2920 | if (!temp) |
2921 | temp = 2; | |
b99bd4ef | 2922 | |
c19d1205 ZW |
2923 | /* Only make a frag if we HAVE to. */ |
2924 | if (temp && !need_pass_2) | |
dce323d1 PB |
2925 | { |
2926 | if (!fill_p && subseg_text_p (now_seg)) | |
2927 | frag_align_code (temp, 0); | |
2928 | else | |
2929 | frag_align (temp, (int) temp_fill, 0); | |
2930 | } | |
c19d1205 ZW |
2931 | demand_empty_rest_of_line (); |
2932 | ||
2933 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
2934 | } |
2935 | ||
c19d1205 ZW |
2936 | static void |
2937 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2938 | { |
c19d1205 ZW |
2939 | /* We don't support putting frags in the BSS segment, we fake it by |
2940 | marking in_bss, then looking at s_skip for clues. */ | |
2941 | subseg_set (bss_section, 0); | |
2942 | demand_empty_rest_of_line (); | |
cd000bff DJ |
2943 | |
2944 | #ifdef md_elf_section_change_hook | |
2945 | md_elf_section_change_hook (); | |
2946 | #endif | |
c19d1205 | 2947 | } |
b99bd4ef | 2948 | |
c19d1205 ZW |
2949 | static void |
2950 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2951 | { | |
2952 | /* Never make frag if expect extra pass. */ | |
2953 | if (!need_pass_2) | |
2954 | frag_align (1, 0, 0); | |
b99bd4ef | 2955 | |
c19d1205 | 2956 | record_alignment (now_seg, 1); |
b99bd4ef | 2957 | |
c19d1205 | 2958 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2959 | } |
2960 | ||
c19d1205 | 2961 | /* Directives: Literal pools. */ |
a737bd4d | 2962 | |
c19d1205 ZW |
2963 | static literal_pool * |
2964 | find_literal_pool (void) | |
a737bd4d | 2965 | { |
c19d1205 | 2966 | literal_pool * pool; |
a737bd4d | 2967 | |
c19d1205 | 2968 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 2969 | { |
c19d1205 ZW |
2970 | if (pool->section == now_seg |
2971 | && pool->sub_section == now_subseg) | |
2972 | break; | |
a737bd4d NC |
2973 | } |
2974 | ||
c19d1205 | 2975 | return pool; |
a737bd4d NC |
2976 | } |
2977 | ||
c19d1205 ZW |
2978 | static literal_pool * |
2979 | find_or_make_literal_pool (void) | |
a737bd4d | 2980 | { |
c19d1205 ZW |
2981 | /* Next literal pool ID number. */ |
2982 | static unsigned int latest_pool_num = 1; | |
2983 | literal_pool * pool; | |
a737bd4d | 2984 | |
c19d1205 | 2985 | pool = find_literal_pool (); |
a737bd4d | 2986 | |
c19d1205 | 2987 | if (pool == NULL) |
a737bd4d | 2988 | { |
c19d1205 | 2989 | /* Create a new pool. */ |
21d799b5 | 2990 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
2991 | if (! pool) |
2992 | return NULL; | |
a737bd4d | 2993 | |
c19d1205 ZW |
2994 | pool->next_free_entry = 0; |
2995 | pool->section = now_seg; | |
2996 | pool->sub_section = now_subseg; | |
2997 | pool->next = list_of_pools; | |
2998 | pool->symbol = NULL; | |
2999 | ||
3000 | /* Add it to the list. */ | |
3001 | list_of_pools = pool; | |
a737bd4d | 3002 | } |
a737bd4d | 3003 | |
c19d1205 ZW |
3004 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3005 | if (pool->symbol == NULL) | |
a737bd4d | 3006 | { |
c19d1205 ZW |
3007 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3008 | (valueT) 0, &zero_address_frag); | |
3009 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3010 | } |
3011 | ||
c19d1205 ZW |
3012 | /* Done. */ |
3013 | return pool; | |
a737bd4d NC |
3014 | } |
3015 | ||
c19d1205 | 3016 | /* Add the literal in the global 'inst' |
5f4273c7 | 3017 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3018 | |
3019 | static int | |
c19d1205 | 3020 | add_to_lit_pool (void) |
b99bd4ef | 3021 | { |
c19d1205 ZW |
3022 | literal_pool * pool; |
3023 | unsigned int entry; | |
b99bd4ef | 3024 | |
c19d1205 ZW |
3025 | pool = find_or_make_literal_pool (); |
3026 | ||
3027 | /* Check if this literal value is already in the pool. */ | |
3028 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3029 | { |
c19d1205 ZW |
3030 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
3031 | && (inst.reloc.exp.X_op == O_constant) | |
3032 | && (pool->literals[entry].X_add_number | |
3033 | == inst.reloc.exp.X_add_number) | |
3034 | && (pool->literals[entry].X_unsigned | |
3035 | == inst.reloc.exp.X_unsigned)) | |
3036 | break; | |
3037 | ||
3038 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3039 | && (inst.reloc.exp.X_op == O_symbol) | |
3040 | && (pool->literals[entry].X_add_number | |
3041 | == inst.reloc.exp.X_add_number) | |
3042 | && (pool->literals[entry].X_add_symbol | |
3043 | == inst.reloc.exp.X_add_symbol) | |
3044 | && (pool->literals[entry].X_op_symbol | |
3045 | == inst.reloc.exp.X_op_symbol)) | |
3046 | break; | |
b99bd4ef NC |
3047 | } |
3048 | ||
c19d1205 ZW |
3049 | /* Do we need to create a new entry? */ |
3050 | if (entry == pool->next_free_entry) | |
3051 | { | |
3052 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3053 | { | |
3054 | inst.error = _("literal pool overflow"); | |
3055 | return FAIL; | |
3056 | } | |
3057 | ||
3058 | pool->literals[entry] = inst.reloc.exp; | |
3059 | pool->next_free_entry += 1; | |
3060 | } | |
b99bd4ef | 3061 | |
c19d1205 ZW |
3062 | inst.reloc.exp.X_op = O_symbol; |
3063 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
3064 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 3065 | |
c19d1205 | 3066 | return SUCCESS; |
b99bd4ef NC |
3067 | } |
3068 | ||
c19d1205 ZW |
3069 | /* Can't use symbol_new here, so have to create a symbol and then at |
3070 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3071 | |
c19d1205 ZW |
3072 | static void |
3073 | symbol_locate (symbolS * symbolP, | |
3074 | const char * name, /* It is copied, the caller can modify. */ | |
3075 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3076 | valueT valu, /* Symbol value. */ | |
3077 | fragS * frag) /* Associated fragment. */ | |
3078 | { | |
3079 | unsigned int name_length; | |
3080 | char * preserved_copy_of_name; | |
e16bb312 | 3081 | |
c19d1205 ZW |
3082 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3083 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3084 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3085 | |
c19d1205 ZW |
3086 | #ifdef tc_canonicalize_symbol_name |
3087 | preserved_copy_of_name = | |
3088 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3089 | #endif | |
b99bd4ef | 3090 | |
c19d1205 | 3091 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3092 | |
c19d1205 ZW |
3093 | S_SET_SEGMENT (symbolP, segment); |
3094 | S_SET_VALUE (symbolP, valu); | |
3095 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3096 | |
c19d1205 | 3097 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3098 | |
c19d1205 ZW |
3099 | /* Link to end of symbol chain. */ |
3100 | { | |
3101 | extern int symbol_table_frozen; | |
b99bd4ef | 3102 | |
c19d1205 ZW |
3103 | if (symbol_table_frozen) |
3104 | abort (); | |
3105 | } | |
b99bd4ef | 3106 | |
c19d1205 | 3107 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3108 | |
c19d1205 | 3109 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3110 | |
c19d1205 ZW |
3111 | #ifdef tc_symbol_new_hook |
3112 | tc_symbol_new_hook (symbolP); | |
3113 | #endif | |
3114 | ||
3115 | #ifdef DEBUG_SYMS | |
3116 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3117 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3118 | } |
3119 | ||
b99bd4ef | 3120 | |
c19d1205 ZW |
3121 | static void |
3122 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3123 | { |
c19d1205 ZW |
3124 | unsigned int entry; |
3125 | literal_pool * pool; | |
3126 | char sym_name[20]; | |
b99bd4ef | 3127 | |
c19d1205 ZW |
3128 | pool = find_literal_pool (); |
3129 | if (pool == NULL | |
3130 | || pool->symbol == NULL | |
3131 | || pool->next_free_entry == 0) | |
3132 | return; | |
b99bd4ef | 3133 | |
c19d1205 | 3134 | mapping_state (MAP_DATA); |
b99bd4ef | 3135 | |
c19d1205 ZW |
3136 | /* Align pool as you have word accesses. |
3137 | Only make a frag if we have to. */ | |
3138 | if (!need_pass_2) | |
3139 | frag_align (2, 0, 0); | |
b99bd4ef | 3140 | |
c19d1205 | 3141 | record_alignment (now_seg, 2); |
b99bd4ef | 3142 | |
c19d1205 | 3143 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3144 | |
c19d1205 ZW |
3145 | symbol_locate (pool->symbol, sym_name, now_seg, |
3146 | (valueT) frag_now_fix (), frag_now); | |
3147 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3148 | |
c19d1205 | 3149 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3150 | |
c19d1205 ZW |
3151 | #if defined OBJ_COFF || defined OBJ_ELF |
3152 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3153 | #endif | |
6c43fab6 | 3154 | |
c19d1205 ZW |
3155 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
3156 | /* First output the expression in the instruction to the pool. */ | |
3157 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
b99bd4ef | 3158 | |
c19d1205 ZW |
3159 | /* Mark the pool as empty. */ |
3160 | pool->next_free_entry = 0; | |
3161 | pool->symbol = NULL; | |
b99bd4ef NC |
3162 | } |
3163 | ||
c19d1205 ZW |
3164 | #ifdef OBJ_ELF |
3165 | /* Forward declarations for functions below, in the MD interface | |
3166 | section. */ | |
3167 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3168 | static valueT create_unwind_entry (int); | |
3169 | static void start_unwind_section (const segT, int); | |
3170 | static void add_unwind_opcode (valueT, int); | |
3171 | static void flush_pending_unwind (void); | |
b99bd4ef | 3172 | |
c19d1205 | 3173 | /* Directives: Data. */ |
b99bd4ef | 3174 | |
c19d1205 ZW |
3175 | static void |
3176 | s_arm_elf_cons (int nbytes) | |
3177 | { | |
3178 | expressionS exp; | |
b99bd4ef | 3179 | |
c19d1205 ZW |
3180 | #ifdef md_flush_pending_output |
3181 | md_flush_pending_output (); | |
3182 | #endif | |
b99bd4ef | 3183 | |
c19d1205 | 3184 | if (is_it_end_of_statement ()) |
b99bd4ef | 3185 | { |
c19d1205 ZW |
3186 | demand_empty_rest_of_line (); |
3187 | return; | |
b99bd4ef NC |
3188 | } |
3189 | ||
c19d1205 ZW |
3190 | #ifdef md_cons_align |
3191 | md_cons_align (nbytes); | |
3192 | #endif | |
b99bd4ef | 3193 | |
c19d1205 ZW |
3194 | mapping_state (MAP_DATA); |
3195 | do | |
b99bd4ef | 3196 | { |
c19d1205 ZW |
3197 | int reloc; |
3198 | char *base = input_line_pointer; | |
b99bd4ef | 3199 | |
c19d1205 | 3200 | expression (& exp); |
b99bd4ef | 3201 | |
c19d1205 ZW |
3202 | if (exp.X_op != O_symbol) |
3203 | emit_expr (&exp, (unsigned int) nbytes); | |
3204 | else | |
3205 | { | |
3206 | char *before_reloc = input_line_pointer; | |
3207 | reloc = parse_reloc (&input_line_pointer); | |
3208 | if (reloc == -1) | |
3209 | { | |
3210 | as_bad (_("unrecognized relocation suffix")); | |
3211 | ignore_rest_of_line (); | |
3212 | return; | |
3213 | } | |
3214 | else if (reloc == BFD_RELOC_UNUSED) | |
3215 | emit_expr (&exp, (unsigned int) nbytes); | |
3216 | else | |
3217 | { | |
21d799b5 NC |
3218 | reloc_howto_type *howto = (reloc_howto_type *) |
3219 | bfd_reloc_type_lookup (stdoutput, | |
3220 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3221 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3222 | |
2fc8bdac ZW |
3223 | if (reloc == BFD_RELOC_ARM_PLT32) |
3224 | { | |
3225 | as_bad (_("(plt) is only valid on branch targets")); | |
3226 | reloc = BFD_RELOC_UNUSED; | |
3227 | size = 0; | |
3228 | } | |
3229 | ||
c19d1205 | 3230 | if (size > nbytes) |
2fc8bdac | 3231 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3232 | howto->name, nbytes); |
3233 | else | |
3234 | { | |
3235 | /* We've parsed an expression stopping at O_symbol. | |
3236 | But there may be more expression left now that we | |
3237 | have parsed the relocation marker. Parse it again. | |
3238 | XXX Surely there is a cleaner way to do this. */ | |
3239 | char *p = input_line_pointer; | |
3240 | int offset; | |
21d799b5 | 3241 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3242 | memcpy (save_buf, base, input_line_pointer - base); |
3243 | memmove (base + (input_line_pointer - before_reloc), | |
3244 | base, before_reloc - base); | |
3245 | ||
3246 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3247 | expression (&exp); | |
3248 | memcpy (base, save_buf, p - base); | |
3249 | ||
3250 | offset = nbytes - size; | |
3251 | p = frag_more ((int) nbytes); | |
3252 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
21d799b5 | 3253 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3254 | } |
3255 | } | |
3256 | } | |
b99bd4ef | 3257 | } |
c19d1205 | 3258 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3259 | |
c19d1205 ZW |
3260 | /* Put terminator back into stream. */ |
3261 | input_line_pointer --; | |
3262 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3263 | } |
3264 | ||
c921be7d NC |
3265 | /* Emit an expression containing a 32-bit thumb instruction. |
3266 | Implementation based on put_thumb32_insn. */ | |
3267 | ||
3268 | static void | |
3269 | emit_thumb32_expr (expressionS * exp) | |
3270 | { | |
3271 | expressionS exp_high = *exp; | |
3272 | ||
3273 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3274 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3275 | exp->X_add_number &= 0xffff; | |
3276 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3277 | } | |
3278 | ||
3279 | /* Guess the instruction size based on the opcode. */ | |
3280 | ||
3281 | static int | |
3282 | thumb_insn_size (int opcode) | |
3283 | { | |
3284 | if ((unsigned int) opcode < 0xe800u) | |
3285 | return 2; | |
3286 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3287 | return 4; | |
3288 | else | |
3289 | return 0; | |
3290 | } | |
3291 | ||
3292 | static bfd_boolean | |
3293 | emit_insn (expressionS *exp, int nbytes) | |
3294 | { | |
3295 | int size = 0; | |
3296 | ||
3297 | if (exp->X_op == O_constant) | |
3298 | { | |
3299 | size = nbytes; | |
3300 | ||
3301 | if (size == 0) | |
3302 | size = thumb_insn_size (exp->X_add_number); | |
3303 | ||
3304 | if (size != 0) | |
3305 | { | |
3306 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3307 | { | |
3308 | as_bad (_(".inst.n operand too big. "\ | |
3309 | "Use .inst.w instead")); | |
3310 | size = 0; | |
3311 | } | |
3312 | else | |
3313 | { | |
3314 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3315 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3316 | else | |
3317 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3318 | ||
3319 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3320 | emit_thumb32_expr (exp); | |
3321 | else | |
3322 | emit_expr (exp, (unsigned int) size); | |
3323 | ||
3324 | it_fsm_post_encode (); | |
3325 | } | |
3326 | } | |
3327 | else | |
3328 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3329 | "Use .inst.n/.inst.w instead")); | |
3330 | } | |
3331 | else | |
3332 | as_bad (_("constant expression required")); | |
3333 | ||
3334 | return (size != 0); | |
3335 | } | |
3336 | ||
3337 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3338 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3339 | ||
3340 | static void | |
3341 | s_arm_elf_inst (int nbytes) | |
3342 | { | |
3343 | if (is_it_end_of_statement ()) | |
3344 | { | |
3345 | demand_empty_rest_of_line (); | |
3346 | return; | |
3347 | } | |
3348 | ||
3349 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3350 | but will ensure not to be in DATA state. */ | |
3351 | ||
3352 | if (thumb_mode) | |
3353 | mapping_state (MAP_THUMB); | |
3354 | else | |
3355 | { | |
3356 | if (nbytes != 0) | |
3357 | { | |
3358 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3359 | ignore_rest_of_line (); | |
3360 | return; | |
3361 | } | |
3362 | ||
3363 | nbytes = 4; | |
3364 | ||
3365 | mapping_state (MAP_ARM); | |
3366 | } | |
3367 | ||
3368 | do | |
3369 | { | |
3370 | expressionS exp; | |
3371 | ||
3372 | expression (& exp); | |
3373 | ||
3374 | if (! emit_insn (& exp, nbytes)) | |
3375 | { | |
3376 | ignore_rest_of_line (); | |
3377 | return; | |
3378 | } | |
3379 | } | |
3380 | while (*input_line_pointer++ == ','); | |
3381 | ||
3382 | /* Put terminator back into stream. */ | |
3383 | input_line_pointer --; | |
3384 | demand_empty_rest_of_line (); | |
3385 | } | |
b99bd4ef | 3386 | |
c19d1205 | 3387 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3388 | |
c19d1205 ZW |
3389 | static void |
3390 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3391 | { | |
3392 | expressionS exp; | |
3393 | char *p; | |
3394 | valueT highbit; | |
b99bd4ef | 3395 | |
c19d1205 ZW |
3396 | highbit = 0; |
3397 | if (*input_line_pointer == '1') | |
3398 | highbit = 0x80000000; | |
3399 | else if (*input_line_pointer != '0') | |
3400 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3401 | |
c19d1205 ZW |
3402 | input_line_pointer++; |
3403 | if (*input_line_pointer != ',') | |
3404 | as_bad (_("missing comma")); | |
3405 | input_line_pointer++; | |
b99bd4ef | 3406 | |
c19d1205 ZW |
3407 | #ifdef md_flush_pending_output |
3408 | md_flush_pending_output (); | |
3409 | #endif | |
b99bd4ef | 3410 | |
c19d1205 ZW |
3411 | #ifdef md_cons_align |
3412 | md_cons_align (4); | |
3413 | #endif | |
b99bd4ef | 3414 | |
c19d1205 | 3415 | mapping_state (MAP_DATA); |
b99bd4ef | 3416 | |
c19d1205 | 3417 | expression (&exp); |
b99bd4ef | 3418 | |
c19d1205 ZW |
3419 | p = frag_more (4); |
3420 | md_number_to_chars (p, highbit, 4); | |
3421 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3422 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3423 | |
c19d1205 | 3424 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3425 | } |
3426 | ||
c19d1205 | 3427 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3428 | |
c19d1205 | 3429 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3430 | |
c19d1205 ZW |
3431 | static void |
3432 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3433 | { | |
3434 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3435 | if (unwind.proc_start) |
3436 | { | |
c921be7d | 3437 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3438 | return; |
3439 | } | |
3440 | ||
c19d1205 ZW |
3441 | /* Mark the start of the function. */ |
3442 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3443 | |
c19d1205 ZW |
3444 | /* Reset the rest of the unwind info. */ |
3445 | unwind.opcode_count = 0; | |
3446 | unwind.table_entry = NULL; | |
3447 | unwind.personality_routine = NULL; | |
3448 | unwind.personality_index = -1; | |
3449 | unwind.frame_size = 0; | |
3450 | unwind.fp_offset = 0; | |
fdfde340 | 3451 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3452 | unwind.fp_used = 0; |
3453 | unwind.sp_restored = 0; | |
3454 | } | |
b99bd4ef | 3455 | |
b99bd4ef | 3456 | |
c19d1205 ZW |
3457 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3458 | for the function. */ | |
b99bd4ef | 3459 | |
c19d1205 ZW |
3460 | static void |
3461 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3462 | { | |
3463 | demand_empty_rest_of_line (); | |
921e5f0a | 3464 | if (!unwind.proc_start) |
c921be7d | 3465 | as_bad (MISSING_FNSTART); |
921e5f0a | 3466 | |
c19d1205 | 3467 | if (unwind.table_entry) |
6decc662 | 3468 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3469 | |
c19d1205 ZW |
3470 | create_unwind_entry (1); |
3471 | } | |
a737bd4d | 3472 | |
c19d1205 | 3473 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3474 | |
c19d1205 ZW |
3475 | static void |
3476 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3477 | { | |
3478 | long where; | |
3479 | char *ptr; | |
3480 | valueT val; | |
940b5ce0 | 3481 | unsigned int marked_pr_dependency; |
f02232aa | 3482 | |
c19d1205 | 3483 | demand_empty_rest_of_line (); |
f02232aa | 3484 | |
921e5f0a PB |
3485 | if (!unwind.proc_start) |
3486 | { | |
c921be7d | 3487 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3488 | return; |
3489 | } | |
3490 | ||
c19d1205 ZW |
3491 | /* Add eh table entry. */ |
3492 | if (unwind.table_entry == NULL) | |
3493 | val = create_unwind_entry (0); | |
3494 | else | |
3495 | val = 0; | |
f02232aa | 3496 | |
c19d1205 ZW |
3497 | /* Add index table entry. This is two words. */ |
3498 | start_unwind_section (unwind.saved_seg, 1); | |
3499 | frag_align (2, 0, 0); | |
3500 | record_alignment (now_seg, 2); | |
b99bd4ef | 3501 | |
c19d1205 ZW |
3502 | ptr = frag_more (8); |
3503 | where = frag_now_fix () - 8; | |
f02232aa | 3504 | |
c19d1205 ZW |
3505 | /* Self relative offset of the function start. */ |
3506 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3507 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3508 | |
c19d1205 ZW |
3509 | /* Indicate dependency on EHABI-defined personality routines to the |
3510 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3511 | marked_pr_dependency |
3512 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3513 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3514 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3515 | { | |
5f4273c7 NC |
3516 | static const char *const name[] = |
3517 | { | |
3518 | "__aeabi_unwind_cpp_pr0", | |
3519 | "__aeabi_unwind_cpp_pr1", | |
3520 | "__aeabi_unwind_cpp_pr2" | |
3521 | }; | |
c19d1205 ZW |
3522 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3523 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3524 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3525 | |= 1 << unwind.personality_index; |
c19d1205 | 3526 | } |
f02232aa | 3527 | |
c19d1205 ZW |
3528 | if (val) |
3529 | /* Inline exception table entry. */ | |
3530 | md_number_to_chars (ptr + 4, val, 4); | |
3531 | else | |
3532 | /* Self relative offset of the table entry. */ | |
3533 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3534 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3535 | |
c19d1205 ZW |
3536 | /* Restore the original section. */ |
3537 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3538 | |
3539 | unwind.proc_start = NULL; | |
c19d1205 | 3540 | } |
f02232aa | 3541 | |
f02232aa | 3542 | |
c19d1205 | 3543 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3544 | |
c19d1205 ZW |
3545 | static void |
3546 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3547 | { | |
3548 | demand_empty_rest_of_line (); | |
921e5f0a | 3549 | if (!unwind.proc_start) |
c921be7d | 3550 | as_bad (MISSING_FNSTART); |
921e5f0a | 3551 | |
c19d1205 ZW |
3552 | if (unwind.personality_routine || unwind.personality_index != -1) |
3553 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3554 | |
c19d1205 ZW |
3555 | unwind.personality_index = -2; |
3556 | } | |
b99bd4ef | 3557 | |
b99bd4ef | 3558 | |
c19d1205 | 3559 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3560 | |
c19d1205 ZW |
3561 | static void |
3562 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3563 | { | |
3564 | expressionS exp; | |
b99bd4ef | 3565 | |
921e5f0a | 3566 | if (!unwind.proc_start) |
c921be7d | 3567 | as_bad (MISSING_FNSTART); |
921e5f0a | 3568 | |
c19d1205 ZW |
3569 | if (unwind.personality_routine || unwind.personality_index != -1) |
3570 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3571 | |
c19d1205 | 3572 | expression (&exp); |
b99bd4ef | 3573 | |
c19d1205 ZW |
3574 | if (exp.X_op != O_constant |
3575 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3576 | { |
c19d1205 ZW |
3577 | as_bad (_("bad personality routine number")); |
3578 | ignore_rest_of_line (); | |
3579 | return; | |
b99bd4ef NC |
3580 | } |
3581 | ||
c19d1205 | 3582 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3583 | |
c19d1205 ZW |
3584 | demand_empty_rest_of_line (); |
3585 | } | |
e16bb312 | 3586 | |
e16bb312 | 3587 | |
c19d1205 | 3588 | /* Parse a personality directive. */ |
e16bb312 | 3589 | |
c19d1205 ZW |
3590 | static void |
3591 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3592 | { | |
3593 | char *name, *p, c; | |
a737bd4d | 3594 | |
921e5f0a | 3595 | if (!unwind.proc_start) |
c921be7d | 3596 | as_bad (MISSING_FNSTART); |
921e5f0a | 3597 | |
c19d1205 ZW |
3598 | if (unwind.personality_routine || unwind.personality_index != -1) |
3599 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3600 | |
c19d1205 ZW |
3601 | name = input_line_pointer; |
3602 | c = get_symbol_end (); | |
3603 | p = input_line_pointer; | |
3604 | unwind.personality_routine = symbol_find_or_make (name); | |
3605 | *p = c; | |
3606 | demand_empty_rest_of_line (); | |
3607 | } | |
e16bb312 | 3608 | |
e16bb312 | 3609 | |
c19d1205 | 3610 | /* Parse a directive saving core registers. */ |
e16bb312 | 3611 | |
c19d1205 ZW |
3612 | static void |
3613 | s_arm_unwind_save_core (void) | |
e16bb312 | 3614 | { |
c19d1205 ZW |
3615 | valueT op; |
3616 | long range; | |
3617 | int n; | |
e16bb312 | 3618 | |
c19d1205 ZW |
3619 | range = parse_reg_list (&input_line_pointer); |
3620 | if (range == FAIL) | |
e16bb312 | 3621 | { |
c19d1205 ZW |
3622 | as_bad (_("expected register list")); |
3623 | ignore_rest_of_line (); | |
3624 | return; | |
3625 | } | |
e16bb312 | 3626 | |
c19d1205 | 3627 | demand_empty_rest_of_line (); |
e16bb312 | 3628 | |
c19d1205 ZW |
3629 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3630 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3631 | ip because it is clobbered by calls. */ | |
3632 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3633 | && (range & 0x3000) == 0x1000) | |
3634 | { | |
3635 | unwind.opcode_count--; | |
3636 | unwind.sp_restored = 0; | |
3637 | range = (range | 0x2000) & ~0x1000; | |
3638 | unwind.pending_offset = 0; | |
3639 | } | |
e16bb312 | 3640 | |
01ae4198 DJ |
3641 | /* Pop r4-r15. */ |
3642 | if (range & 0xfff0) | |
c19d1205 | 3643 | { |
01ae4198 DJ |
3644 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3645 | registers starting with r4, plus maybe r14. */ | |
3646 | for (n = 0; n < 8; n++) | |
3647 | { | |
3648 | /* Break at the first non-saved register. */ | |
3649 | if ((range & (1 << (n + 4))) == 0) | |
3650 | break; | |
3651 | } | |
3652 | /* See if there are any other bits set. */ | |
3653 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3654 | { | |
3655 | /* Use the long form. */ | |
3656 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3657 | add_unwind_opcode (op, 2); | |
3658 | } | |
0dd132b6 | 3659 | else |
01ae4198 DJ |
3660 | { |
3661 | /* Use the short form. */ | |
3662 | if (range & 0x4000) | |
3663 | op = 0xa8; /* Pop r14. */ | |
3664 | else | |
3665 | op = 0xa0; /* Do not pop r14. */ | |
3666 | op |= (n - 1); | |
3667 | add_unwind_opcode (op, 1); | |
3668 | } | |
c19d1205 | 3669 | } |
0dd132b6 | 3670 | |
c19d1205 ZW |
3671 | /* Pop r0-r3. */ |
3672 | if (range & 0xf) | |
3673 | { | |
3674 | op = 0xb100 | (range & 0xf); | |
3675 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3676 | } |
3677 | ||
c19d1205 ZW |
3678 | /* Record the number of bytes pushed. */ |
3679 | for (n = 0; n < 16; n++) | |
3680 | { | |
3681 | if (range & (1 << n)) | |
3682 | unwind.frame_size += 4; | |
3683 | } | |
0dd132b6 NC |
3684 | } |
3685 | ||
c19d1205 ZW |
3686 | |
3687 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3688 | |
3689 | static void | |
c19d1205 | 3690 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3691 | { |
c19d1205 ZW |
3692 | expressionS exp; |
3693 | int num_regs; | |
3694 | valueT op; | |
b99bd4ef | 3695 | |
c19d1205 ZW |
3696 | /* Get Number of registers to transfer. */ |
3697 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3698 | expression (&exp); | |
3699 | else | |
3700 | exp.X_op = O_illegal; | |
b99bd4ef | 3701 | |
c19d1205 | 3702 | if (exp.X_op != O_constant) |
b99bd4ef | 3703 | { |
c19d1205 ZW |
3704 | as_bad (_("expected , <constant>")); |
3705 | ignore_rest_of_line (); | |
b99bd4ef NC |
3706 | return; |
3707 | } | |
3708 | ||
c19d1205 ZW |
3709 | num_regs = exp.X_add_number; |
3710 | ||
3711 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3712 | { |
c19d1205 ZW |
3713 | as_bad (_("number of registers must be in the range [1:4]")); |
3714 | ignore_rest_of_line (); | |
b99bd4ef NC |
3715 | return; |
3716 | } | |
3717 | ||
c19d1205 | 3718 | demand_empty_rest_of_line (); |
b99bd4ef | 3719 | |
c19d1205 ZW |
3720 | if (reg == 4) |
3721 | { | |
3722 | /* Short form. */ | |
3723 | op = 0xb4 | (num_regs - 1); | |
3724 | add_unwind_opcode (op, 1); | |
3725 | } | |
b99bd4ef NC |
3726 | else |
3727 | { | |
c19d1205 ZW |
3728 | /* Long form. */ |
3729 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
3730 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3731 | } |
c19d1205 | 3732 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
3733 | } |
3734 | ||
c19d1205 | 3735 | |
fa073d69 MS |
3736 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
3737 | ||
3738 | static void | |
3739 | s_arm_unwind_save_vfp_armv6 (void) | |
3740 | { | |
3741 | int count; | |
3742 | unsigned int start; | |
3743 | valueT op; | |
3744 | int num_vfpv3_regs = 0; | |
3745 | int num_regs_below_16; | |
3746 | ||
3747 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
3748 | if (count == FAIL) | |
3749 | { | |
3750 | as_bad (_("expected register list")); | |
3751 | ignore_rest_of_line (); | |
3752 | return; | |
3753 | } | |
3754 | ||
3755 | demand_empty_rest_of_line (); | |
3756 | ||
3757 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
3758 | than FSTMX/FLDMX-style ones). */ | |
3759 | ||
3760 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
3761 | if (start >= 16) | |
3762 | num_vfpv3_regs = count; | |
3763 | else if (start + count > 16) | |
3764 | num_vfpv3_regs = start + count - 16; | |
3765 | ||
3766 | if (num_vfpv3_regs > 0) | |
3767 | { | |
3768 | int start_offset = start > 16 ? start - 16 : 0; | |
3769 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
3770 | add_unwind_opcode (op, 2); | |
3771 | } | |
3772 | ||
3773 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
3774 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 3775 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
3776 | if (num_regs_below_16 > 0) |
3777 | { | |
3778 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
3779 | add_unwind_opcode (op, 2); | |
3780 | } | |
3781 | ||
3782 | unwind.frame_size += count * 8; | |
3783 | } | |
3784 | ||
3785 | ||
3786 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
3787 | |
3788 | static void | |
c19d1205 | 3789 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 3790 | { |
c19d1205 | 3791 | int count; |
ca3f61f7 | 3792 | unsigned int reg; |
c19d1205 | 3793 | valueT op; |
b99bd4ef | 3794 | |
5287ad62 | 3795 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 3796 | if (count == FAIL) |
b99bd4ef | 3797 | { |
c19d1205 ZW |
3798 | as_bad (_("expected register list")); |
3799 | ignore_rest_of_line (); | |
b99bd4ef NC |
3800 | return; |
3801 | } | |
3802 | ||
c19d1205 | 3803 | demand_empty_rest_of_line (); |
b99bd4ef | 3804 | |
c19d1205 | 3805 | if (reg == 8) |
b99bd4ef | 3806 | { |
c19d1205 ZW |
3807 | /* Short form. */ |
3808 | op = 0xb8 | (count - 1); | |
3809 | add_unwind_opcode (op, 1); | |
b99bd4ef | 3810 | } |
c19d1205 | 3811 | else |
b99bd4ef | 3812 | { |
c19d1205 ZW |
3813 | /* Long form. */ |
3814 | op = 0xb300 | (reg << 4) | (count - 1); | |
3815 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3816 | } |
c19d1205 ZW |
3817 | unwind.frame_size += count * 8 + 4; |
3818 | } | |
b99bd4ef | 3819 | |
b99bd4ef | 3820 | |
c19d1205 ZW |
3821 | /* Parse a directive saving iWMMXt data registers. */ |
3822 | ||
3823 | static void | |
3824 | s_arm_unwind_save_mmxwr (void) | |
3825 | { | |
3826 | int reg; | |
3827 | int hi_reg; | |
3828 | int i; | |
3829 | unsigned mask = 0; | |
3830 | valueT op; | |
b99bd4ef | 3831 | |
c19d1205 ZW |
3832 | if (*input_line_pointer == '{') |
3833 | input_line_pointer++; | |
b99bd4ef | 3834 | |
c19d1205 | 3835 | do |
b99bd4ef | 3836 | { |
dcbf9037 | 3837 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 3838 | |
c19d1205 | 3839 | if (reg == FAIL) |
b99bd4ef | 3840 | { |
9b7132d3 | 3841 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 3842 | goto error; |
b99bd4ef NC |
3843 | } |
3844 | ||
c19d1205 ZW |
3845 | if (mask >> reg) |
3846 | as_tsktsk (_("register list not in ascending order")); | |
3847 | mask |= 1 << reg; | |
b99bd4ef | 3848 | |
c19d1205 ZW |
3849 | if (*input_line_pointer == '-') |
3850 | { | |
3851 | input_line_pointer++; | |
dcbf9037 | 3852 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
3853 | if (hi_reg == FAIL) |
3854 | { | |
9b7132d3 | 3855 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
3856 | goto error; |
3857 | } | |
3858 | else if (reg >= hi_reg) | |
3859 | { | |
3860 | as_bad (_("bad register range")); | |
3861 | goto error; | |
3862 | } | |
3863 | for (; reg < hi_reg; reg++) | |
3864 | mask |= 1 << reg; | |
3865 | } | |
3866 | } | |
3867 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 3868 | |
c19d1205 ZW |
3869 | if (*input_line_pointer == '}') |
3870 | input_line_pointer++; | |
b99bd4ef | 3871 | |
c19d1205 | 3872 | demand_empty_rest_of_line (); |
b99bd4ef | 3873 | |
708587a4 | 3874 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3875 | the list. */ |
3876 | flush_pending_unwind (); | |
b99bd4ef | 3877 | |
c19d1205 | 3878 | for (i = 0; i < 16; i++) |
b99bd4ef | 3879 | { |
c19d1205 ZW |
3880 | if (mask & (1 << i)) |
3881 | unwind.frame_size += 8; | |
b99bd4ef NC |
3882 | } |
3883 | ||
c19d1205 ZW |
3884 | /* Attempt to combine with a previous opcode. We do this because gcc |
3885 | likes to output separate unwind directives for a single block of | |
3886 | registers. */ | |
3887 | if (unwind.opcode_count > 0) | |
b99bd4ef | 3888 | { |
c19d1205 ZW |
3889 | i = unwind.opcodes[unwind.opcode_count - 1]; |
3890 | if ((i & 0xf8) == 0xc0) | |
3891 | { | |
3892 | i &= 7; | |
3893 | /* Only merge if the blocks are contiguous. */ | |
3894 | if (i < 6) | |
3895 | { | |
3896 | if ((mask & 0xfe00) == (1 << 9)) | |
3897 | { | |
3898 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
3899 | unwind.opcode_count--; | |
3900 | } | |
3901 | } | |
3902 | else if (i == 6 && unwind.opcode_count >= 2) | |
3903 | { | |
3904 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
3905 | reg = i >> 4; | |
3906 | i &= 0xf; | |
b99bd4ef | 3907 | |
c19d1205 ZW |
3908 | op = 0xffff << (reg - 1); |
3909 | if (reg > 0 | |
87a1fd79 | 3910 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
3911 | { |
3912 | op = (1 << (reg + i + 1)) - 1; | |
3913 | op &= ~((1 << reg) - 1); | |
3914 | mask |= op; | |
3915 | unwind.opcode_count -= 2; | |
3916 | } | |
3917 | } | |
3918 | } | |
b99bd4ef NC |
3919 | } |
3920 | ||
c19d1205 ZW |
3921 | hi_reg = 15; |
3922 | /* We want to generate opcodes in the order the registers have been | |
3923 | saved, ie. descending order. */ | |
3924 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 3925 | { |
c19d1205 ZW |
3926 | /* Save registers in blocks. */ |
3927 | if (reg < 0 | |
3928 | || !(mask & (1 << reg))) | |
3929 | { | |
3930 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 3931 | preceding block. */ |
c19d1205 ZW |
3932 | if (reg != hi_reg) |
3933 | { | |
3934 | if (reg == 9) | |
3935 | { | |
3936 | /* Short form. */ | |
3937 | op = 0xc0 | (hi_reg - 10); | |
3938 | add_unwind_opcode (op, 1); | |
3939 | } | |
3940 | else | |
3941 | { | |
3942 | /* Long form. */ | |
3943 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
3944 | add_unwind_opcode (op, 2); | |
3945 | } | |
3946 | } | |
3947 | hi_reg = reg - 1; | |
3948 | } | |
b99bd4ef NC |
3949 | } |
3950 | ||
c19d1205 ZW |
3951 | return; |
3952 | error: | |
3953 | ignore_rest_of_line (); | |
b99bd4ef NC |
3954 | } |
3955 | ||
3956 | static void | |
c19d1205 | 3957 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 3958 | { |
c19d1205 ZW |
3959 | int reg; |
3960 | int hi_reg; | |
3961 | unsigned mask = 0; | |
3962 | valueT op; | |
b99bd4ef | 3963 | |
c19d1205 ZW |
3964 | if (*input_line_pointer == '{') |
3965 | input_line_pointer++; | |
b99bd4ef | 3966 | |
c19d1205 | 3967 | do |
b99bd4ef | 3968 | { |
dcbf9037 | 3969 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 3970 | |
c19d1205 ZW |
3971 | if (reg == FAIL) |
3972 | { | |
9b7132d3 | 3973 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3974 | goto error; |
3975 | } | |
b99bd4ef | 3976 | |
c19d1205 ZW |
3977 | reg -= 8; |
3978 | if (mask >> reg) | |
3979 | as_tsktsk (_("register list not in ascending order")); | |
3980 | mask |= 1 << reg; | |
b99bd4ef | 3981 | |
c19d1205 ZW |
3982 | if (*input_line_pointer == '-') |
3983 | { | |
3984 | input_line_pointer++; | |
dcbf9037 | 3985 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
3986 | if (hi_reg == FAIL) |
3987 | { | |
9b7132d3 | 3988 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
3989 | goto error; |
3990 | } | |
3991 | else if (reg >= hi_reg) | |
3992 | { | |
3993 | as_bad (_("bad register range")); | |
3994 | goto error; | |
3995 | } | |
3996 | for (; reg < hi_reg; reg++) | |
3997 | mask |= 1 << reg; | |
3998 | } | |
b99bd4ef | 3999 | } |
c19d1205 | 4000 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4001 | |
c19d1205 ZW |
4002 | if (*input_line_pointer == '}') |
4003 | input_line_pointer++; | |
b99bd4ef | 4004 | |
c19d1205 ZW |
4005 | demand_empty_rest_of_line (); |
4006 | ||
708587a4 | 4007 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4008 | the list. */ |
4009 | flush_pending_unwind (); | |
b99bd4ef | 4010 | |
c19d1205 | 4011 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4012 | { |
c19d1205 ZW |
4013 | if (mask & (1 << reg)) |
4014 | unwind.frame_size += 4; | |
b99bd4ef | 4015 | } |
c19d1205 ZW |
4016 | op = 0xc700 | mask; |
4017 | add_unwind_opcode (op, 2); | |
4018 | return; | |
4019 | error: | |
4020 | ignore_rest_of_line (); | |
b99bd4ef NC |
4021 | } |
4022 | ||
c19d1205 | 4023 | |
fa073d69 MS |
4024 | /* Parse an unwind_save directive. |
4025 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4026 | |
b99bd4ef | 4027 | static void |
fa073d69 | 4028 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4029 | { |
c19d1205 ZW |
4030 | char *peek; |
4031 | struct reg_entry *reg; | |
4032 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4033 | |
921e5f0a | 4034 | if (!unwind.proc_start) |
c921be7d | 4035 | as_bad (MISSING_FNSTART); |
921e5f0a | 4036 | |
c19d1205 ZW |
4037 | /* Figure out what sort of save we have. */ |
4038 | peek = input_line_pointer; | |
b99bd4ef | 4039 | |
c19d1205 | 4040 | if (*peek == '{') |
b99bd4ef | 4041 | { |
c19d1205 ZW |
4042 | had_brace = TRUE; |
4043 | peek++; | |
b99bd4ef NC |
4044 | } |
4045 | ||
c19d1205 | 4046 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4047 | |
c19d1205 | 4048 | if (!reg) |
b99bd4ef | 4049 | { |
c19d1205 ZW |
4050 | as_bad (_("register expected")); |
4051 | ignore_rest_of_line (); | |
b99bd4ef NC |
4052 | return; |
4053 | } | |
4054 | ||
c19d1205 | 4055 | switch (reg->type) |
b99bd4ef | 4056 | { |
c19d1205 ZW |
4057 | case REG_TYPE_FN: |
4058 | if (had_brace) | |
4059 | { | |
4060 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4061 | ignore_rest_of_line (); | |
4062 | return; | |
4063 | } | |
93ac2687 | 4064 | input_line_pointer = peek; |
c19d1205 | 4065 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4066 | return; |
c19d1205 ZW |
4067 | |
4068 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
fa073d69 MS |
4069 | case REG_TYPE_VFD: |
4070 | if (arch_v6) | |
4071 | s_arm_unwind_save_vfp_armv6 (); | |
4072 | else | |
4073 | s_arm_unwind_save_vfp (); | |
4074 | return; | |
c19d1205 ZW |
4075 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; |
4076 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
4077 | ||
4078 | default: | |
4079 | as_bad (_(".unwind_save does not support this kind of register")); | |
4080 | ignore_rest_of_line (); | |
b99bd4ef | 4081 | } |
c19d1205 | 4082 | } |
b99bd4ef | 4083 | |
b99bd4ef | 4084 | |
c19d1205 ZW |
4085 | /* Parse an unwind_movsp directive. */ |
4086 | ||
4087 | static void | |
4088 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4089 | { | |
4090 | int reg; | |
4091 | valueT op; | |
4fa3602b | 4092 | int offset; |
c19d1205 | 4093 | |
921e5f0a | 4094 | if (!unwind.proc_start) |
c921be7d | 4095 | as_bad (MISSING_FNSTART); |
921e5f0a | 4096 | |
dcbf9037 | 4097 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4098 | if (reg == FAIL) |
b99bd4ef | 4099 | { |
9b7132d3 | 4100 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4101 | ignore_rest_of_line (); |
b99bd4ef NC |
4102 | return; |
4103 | } | |
4fa3602b PB |
4104 | |
4105 | /* Optional constant. */ | |
4106 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4107 | { | |
4108 | if (immediate_for_directive (&offset) == FAIL) | |
4109 | return; | |
4110 | } | |
4111 | else | |
4112 | offset = 0; | |
4113 | ||
c19d1205 | 4114 | demand_empty_rest_of_line (); |
b99bd4ef | 4115 | |
c19d1205 | 4116 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4117 | { |
c19d1205 | 4118 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4119 | return; |
4120 | } | |
4121 | ||
c19d1205 ZW |
4122 | if (unwind.fp_reg != REG_SP) |
4123 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4124 | |
c19d1205 ZW |
4125 | /* Generate opcode to restore the value. */ |
4126 | op = 0x90 | reg; | |
4127 | add_unwind_opcode (op, 1); | |
4128 | ||
4129 | /* Record the information for later. */ | |
4130 | unwind.fp_reg = reg; | |
4fa3602b | 4131 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4132 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4133 | } |
4134 | ||
c19d1205 ZW |
4135 | /* Parse an unwind_pad directive. */ |
4136 | ||
b05fe5cf | 4137 | static void |
c19d1205 | 4138 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4139 | { |
c19d1205 | 4140 | int offset; |
b05fe5cf | 4141 | |
921e5f0a | 4142 | if (!unwind.proc_start) |
c921be7d | 4143 | as_bad (MISSING_FNSTART); |
921e5f0a | 4144 | |
c19d1205 ZW |
4145 | if (immediate_for_directive (&offset) == FAIL) |
4146 | return; | |
b99bd4ef | 4147 | |
c19d1205 ZW |
4148 | if (offset & 3) |
4149 | { | |
4150 | as_bad (_("stack increment must be multiple of 4")); | |
4151 | ignore_rest_of_line (); | |
4152 | return; | |
4153 | } | |
b99bd4ef | 4154 | |
c19d1205 ZW |
4155 | /* Don't generate any opcodes, just record the details for later. */ |
4156 | unwind.frame_size += offset; | |
4157 | unwind.pending_offset += offset; | |
4158 | ||
4159 | demand_empty_rest_of_line (); | |
4160 | } | |
4161 | ||
4162 | /* Parse an unwind_setfp directive. */ | |
4163 | ||
4164 | static void | |
4165 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4166 | { |
c19d1205 ZW |
4167 | int sp_reg; |
4168 | int fp_reg; | |
4169 | int offset; | |
4170 | ||
921e5f0a | 4171 | if (!unwind.proc_start) |
c921be7d | 4172 | as_bad (MISSING_FNSTART); |
921e5f0a | 4173 | |
dcbf9037 | 4174 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4175 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4176 | sp_reg = FAIL; | |
4177 | else | |
dcbf9037 | 4178 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4179 | |
c19d1205 ZW |
4180 | if (fp_reg == FAIL || sp_reg == FAIL) |
4181 | { | |
4182 | as_bad (_("expected <reg>, <reg>")); | |
4183 | ignore_rest_of_line (); | |
4184 | return; | |
4185 | } | |
b99bd4ef | 4186 | |
c19d1205 ZW |
4187 | /* Optional constant. */ |
4188 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4189 | { | |
4190 | if (immediate_for_directive (&offset) == FAIL) | |
4191 | return; | |
4192 | } | |
4193 | else | |
4194 | offset = 0; | |
a737bd4d | 4195 | |
c19d1205 | 4196 | demand_empty_rest_of_line (); |
a737bd4d | 4197 | |
fdfde340 | 4198 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4199 | { |
c19d1205 ZW |
4200 | as_bad (_("register must be either sp or set by a previous" |
4201 | "unwind_movsp directive")); | |
4202 | return; | |
a737bd4d NC |
4203 | } |
4204 | ||
c19d1205 ZW |
4205 | /* Don't generate any opcodes, just record the information for later. */ |
4206 | unwind.fp_reg = fp_reg; | |
4207 | unwind.fp_used = 1; | |
fdfde340 | 4208 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4209 | unwind.fp_offset = unwind.frame_size - offset; |
4210 | else | |
4211 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4212 | } |
4213 | ||
c19d1205 ZW |
4214 | /* Parse an unwind_raw directive. */ |
4215 | ||
4216 | static void | |
4217 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4218 | { |
c19d1205 | 4219 | expressionS exp; |
708587a4 | 4220 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4221 | unsigned char op[16]; |
4222 | int count; | |
a737bd4d | 4223 | |
921e5f0a | 4224 | if (!unwind.proc_start) |
c921be7d | 4225 | as_bad (MISSING_FNSTART); |
921e5f0a | 4226 | |
c19d1205 ZW |
4227 | expression (&exp); |
4228 | if (exp.X_op == O_constant | |
4229 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4230 | { |
c19d1205 ZW |
4231 | unwind.frame_size += exp.X_add_number; |
4232 | expression (&exp); | |
4233 | } | |
4234 | else | |
4235 | exp.X_op = O_illegal; | |
a737bd4d | 4236 | |
c19d1205 ZW |
4237 | if (exp.X_op != O_constant) |
4238 | { | |
4239 | as_bad (_("expected <offset>, <opcode>")); | |
4240 | ignore_rest_of_line (); | |
4241 | return; | |
4242 | } | |
a737bd4d | 4243 | |
c19d1205 | 4244 | count = 0; |
a737bd4d | 4245 | |
c19d1205 ZW |
4246 | /* Parse the opcode. */ |
4247 | for (;;) | |
4248 | { | |
4249 | if (count >= 16) | |
4250 | { | |
4251 | as_bad (_("unwind opcode too long")); | |
4252 | ignore_rest_of_line (); | |
a737bd4d | 4253 | } |
c19d1205 | 4254 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4255 | { |
c19d1205 ZW |
4256 | as_bad (_("invalid unwind opcode")); |
4257 | ignore_rest_of_line (); | |
4258 | return; | |
a737bd4d | 4259 | } |
c19d1205 | 4260 | op[count++] = exp.X_add_number; |
a737bd4d | 4261 | |
c19d1205 ZW |
4262 | /* Parse the next byte. */ |
4263 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4264 | break; | |
a737bd4d | 4265 | |
c19d1205 ZW |
4266 | expression (&exp); |
4267 | } | |
b99bd4ef | 4268 | |
c19d1205 ZW |
4269 | /* Add the opcode bytes in reverse order. */ |
4270 | while (count--) | |
4271 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4272 | |
c19d1205 | 4273 | demand_empty_rest_of_line (); |
b99bd4ef | 4274 | } |
ee065d83 PB |
4275 | |
4276 | ||
4277 | /* Parse a .eabi_attribute directive. */ | |
4278 | ||
4279 | static void | |
4280 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4281 | { | |
ee3c0378 AS |
4282 | int tag = s_vendor_attribute (OBJ_ATTR_PROC); |
4283 | ||
4284 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4285 | attributes_set_explicitly[tag] = 1; | |
ee065d83 PB |
4286 | } |
4287 | ||
0855e32b NS |
4288 | /* Emit a tls fix for the symbol. */ |
4289 | ||
4290 | static void | |
4291 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4292 | { | |
4293 | char *p; | |
4294 | expressionS exp; | |
4295 | #ifdef md_flush_pending_output | |
4296 | md_flush_pending_output (); | |
4297 | #endif | |
4298 | ||
4299 | #ifdef md_cons_align | |
4300 | md_cons_align (4); | |
4301 | #endif | |
4302 | ||
4303 | /* Since we're just labelling the code, there's no need to define a | |
4304 | mapping symbol. */ | |
4305 | expression (&exp); | |
4306 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4307 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4308 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4309 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4310 | } | |
cdf9ccec | 4311 | #endif /* OBJ_ELF */ |
0855e32b | 4312 | |
ee065d83 | 4313 | static void s_arm_arch (int); |
7a1d4c38 | 4314 | static void s_arm_object_arch (int); |
ee065d83 PB |
4315 | static void s_arm_cpu (int); |
4316 | static void s_arm_fpu (int); | |
69133863 | 4317 | static void s_arm_arch_extension (int); |
b99bd4ef | 4318 | |
f0927246 NC |
4319 | #ifdef TE_PE |
4320 | ||
4321 | static void | |
5f4273c7 | 4322 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4323 | { |
4324 | expressionS exp; | |
4325 | ||
4326 | do | |
4327 | { | |
4328 | expression (&exp); | |
4329 | if (exp.X_op == O_symbol) | |
4330 | exp.X_op = O_secrel; | |
4331 | ||
4332 | emit_expr (&exp, 4); | |
4333 | } | |
4334 | while (*input_line_pointer++ == ','); | |
4335 | ||
4336 | input_line_pointer--; | |
4337 | demand_empty_rest_of_line (); | |
4338 | } | |
4339 | #endif /* TE_PE */ | |
4340 | ||
c19d1205 ZW |
4341 | /* This table describes all the machine specific pseudo-ops the assembler |
4342 | has to support. The fields are: | |
4343 | pseudo-op name without dot | |
4344 | function to call to execute this pseudo-op | |
4345 | Integer arg to pass to the function. */ | |
b99bd4ef | 4346 | |
c19d1205 | 4347 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4348 | { |
c19d1205 ZW |
4349 | /* Never called because '.req' does not start a line. */ |
4350 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4351 | /* Following two are likewise never called. */ |
4352 | { "dn", s_dn, 0 }, | |
4353 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4354 | { "unreq", s_unreq, 0 }, |
4355 | { "bss", s_bss, 0 }, | |
4356 | { "align", s_align, 0 }, | |
4357 | { "arm", s_arm, 0 }, | |
4358 | { "thumb", s_thumb, 0 }, | |
4359 | { "code", s_code, 0 }, | |
4360 | { "force_thumb", s_force_thumb, 0 }, | |
4361 | { "thumb_func", s_thumb_func, 0 }, | |
4362 | { "thumb_set", s_thumb_set, 0 }, | |
4363 | { "even", s_even, 0 }, | |
4364 | { "ltorg", s_ltorg, 0 }, | |
4365 | { "pool", s_ltorg, 0 }, | |
4366 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4367 | { "cpu", s_arm_cpu, 0 }, |
4368 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4369 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4370 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4371 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4372 | #ifdef OBJ_ELF |
c921be7d NC |
4373 | { "word", s_arm_elf_cons, 4 }, |
4374 | { "long", s_arm_elf_cons, 4 }, | |
4375 | { "inst.n", s_arm_elf_inst, 2 }, | |
4376 | { "inst.w", s_arm_elf_inst, 4 }, | |
4377 | { "inst", s_arm_elf_inst, 0 }, | |
4378 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4379 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4380 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4381 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4382 | { "personality", s_arm_unwind_personality, 0 }, | |
4383 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4384 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4385 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4386 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4387 | { "movsp", s_arm_unwind_movsp, 0 }, |
4388 | { "pad", s_arm_unwind_pad, 0 }, | |
4389 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4390 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4391 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4392 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4393 | #else |
4394 | { "word", cons, 4}, | |
f0927246 NC |
4395 | |
4396 | /* These are used for dwarf. */ | |
4397 | {"2byte", cons, 2}, | |
4398 | {"4byte", cons, 4}, | |
4399 | {"8byte", cons, 8}, | |
4400 | /* These are used for dwarf2. */ | |
4401 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4402 | { "loc", dwarf2_directive_loc, 0 }, | |
4403 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4404 | #endif |
4405 | { "extend", float_cons, 'x' }, | |
4406 | { "ldouble", float_cons, 'x' }, | |
4407 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4408 | #ifdef TE_PE |
4409 | {"secrel32", pe_directive_secrel, 0}, | |
4410 | #endif | |
c19d1205 ZW |
4411 | { 0, 0, 0 } |
4412 | }; | |
4413 | \f | |
4414 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4415 | |
c19d1205 ZW |
4416 | /* Generic immediate-value read function for use in insn parsing. |
4417 | STR points to the beginning of the immediate (the leading #); | |
4418 | VAL receives the value; if the value is outside [MIN, MAX] | |
4419 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4420 | optional. */ | |
b99bd4ef | 4421 | |
c19d1205 ZW |
4422 | static int |
4423 | parse_immediate (char **str, int *val, int min, int max, | |
4424 | bfd_boolean prefix_opt) | |
4425 | { | |
4426 | expressionS exp; | |
4427 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4428 | if (exp.X_op != O_constant) | |
b99bd4ef | 4429 | { |
c19d1205 ZW |
4430 | inst.error = _("constant expression required"); |
4431 | return FAIL; | |
4432 | } | |
b99bd4ef | 4433 | |
c19d1205 ZW |
4434 | if (exp.X_add_number < min || exp.X_add_number > max) |
4435 | { | |
4436 | inst.error = _("immediate value out of range"); | |
4437 | return FAIL; | |
4438 | } | |
b99bd4ef | 4439 | |
c19d1205 ZW |
4440 | *val = exp.X_add_number; |
4441 | return SUCCESS; | |
4442 | } | |
b99bd4ef | 4443 | |
5287ad62 | 4444 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4445 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4446 | instructions. Puts the result directly in inst.operands[i]. */ |
4447 | ||
4448 | static int | |
4449 | parse_big_immediate (char **str, int i) | |
4450 | { | |
4451 | expressionS exp; | |
4452 | char *ptr = *str; | |
4453 | ||
4454 | my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); | |
4455 | ||
4456 | if (exp.X_op == O_constant) | |
036dc3f7 PB |
4457 | { |
4458 | inst.operands[i].imm = exp.X_add_number & 0xffffffff; | |
4459 | /* If we're on a 64-bit host, then a 64-bit number can be returned using | |
4460 | O_constant. We have to be careful not to break compilation for | |
4461 | 32-bit X_add_number, though. */ | |
58ad575f | 4462 | if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 PB |
4463 | { |
4464 | /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ | |
4465 | inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; | |
4466 | inst.operands[i].regisimm = 1; | |
4467 | } | |
4468 | } | |
5287ad62 | 4469 | else if (exp.X_op == O_big |
95b75c01 | 4470 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32) |
5287ad62 JB |
4471 | { |
4472 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4473 | |
5287ad62 JB |
4474 | /* Bignums have their least significant bits in |
4475 | generic_bignum[0]. Make sure we put 32 bits in imm and | |
4476 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4477 | gas_assert (parts != 0); |
95b75c01 NC |
4478 | |
4479 | /* Make sure that the number is not too big. | |
4480 | PR 11972: Bignums can now be sign-extended to the | |
4481 | size of a .octa so check that the out of range bits | |
4482 | are all zero or all one. */ | |
4483 | if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64) | |
4484 | { | |
4485 | LITTLENUM_TYPE m = -1; | |
4486 | ||
4487 | if (generic_bignum[parts * 2] != 0 | |
4488 | && generic_bignum[parts * 2] != m) | |
4489 | return FAIL; | |
4490 | ||
4491 | for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++) | |
4492 | if (generic_bignum[j] != generic_bignum[j-1]) | |
4493 | return FAIL; | |
4494 | } | |
4495 | ||
5287ad62 JB |
4496 | inst.operands[i].imm = 0; |
4497 | for (j = 0; j < parts; j++, idx++) | |
4498 | inst.operands[i].imm |= generic_bignum[idx] | |
4499 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4500 | inst.operands[i].reg = 0; | |
4501 | for (j = 0; j < parts; j++, idx++) | |
4502 | inst.operands[i].reg |= generic_bignum[idx] | |
4503 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4504 | inst.operands[i].regisimm = 1; | |
4505 | } | |
4506 | else | |
4507 | return FAIL; | |
5f4273c7 | 4508 | |
5287ad62 JB |
4509 | *str = ptr; |
4510 | ||
4511 | return SUCCESS; | |
4512 | } | |
4513 | ||
c19d1205 ZW |
4514 | /* Returns the pseudo-register number of an FPA immediate constant, |
4515 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4516 | |
c19d1205 ZW |
4517 | static int |
4518 | parse_fpa_immediate (char ** str) | |
4519 | { | |
4520 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4521 | char * save_in; | |
4522 | expressionS exp; | |
4523 | int i; | |
4524 | int j; | |
b99bd4ef | 4525 | |
c19d1205 ZW |
4526 | /* First try and match exact strings, this is to guarantee |
4527 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4528 | |
c19d1205 ZW |
4529 | for (i = 0; fp_const[i]; i++) |
4530 | { | |
4531 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4532 | { |
c19d1205 | 4533 | char *start = *str; |
b99bd4ef | 4534 | |
c19d1205 ZW |
4535 | *str += strlen (fp_const[i]); |
4536 | if (is_end_of_line[(unsigned char) **str]) | |
4537 | return i + 8; | |
4538 | *str = start; | |
4539 | } | |
4540 | } | |
b99bd4ef | 4541 | |
c19d1205 ZW |
4542 | /* Just because we didn't get a match doesn't mean that the constant |
4543 | isn't valid, just that it is in a format that we don't | |
4544 | automatically recognize. Try parsing it with the standard | |
4545 | expression routines. */ | |
b99bd4ef | 4546 | |
c19d1205 | 4547 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4548 | |
c19d1205 ZW |
4549 | /* Look for a raw floating point number. */ |
4550 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4551 | && is_end_of_line[(unsigned char) *save_in]) | |
4552 | { | |
4553 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4554 | { | |
4555 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4556 | { |
c19d1205 ZW |
4557 | if (words[j] != fp_values[i][j]) |
4558 | break; | |
b99bd4ef NC |
4559 | } |
4560 | ||
c19d1205 | 4561 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4562 | { |
c19d1205 ZW |
4563 | *str = save_in; |
4564 | return i + 8; | |
b99bd4ef NC |
4565 | } |
4566 | } | |
4567 | } | |
b99bd4ef | 4568 | |
c19d1205 ZW |
4569 | /* Try and parse a more complex expression, this will probably fail |
4570 | unless the code uses a floating point prefix (eg "0f"). */ | |
4571 | save_in = input_line_pointer; | |
4572 | input_line_pointer = *str; | |
4573 | if (expression (&exp) == absolute_section | |
4574 | && exp.X_op == O_big | |
4575 | && exp.X_add_number < 0) | |
4576 | { | |
4577 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4578 | Ditto for 15. */ | |
4579 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4580 | { | |
4581 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4582 | { | |
4583 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4584 | { | |
4585 | if (words[j] != fp_values[i][j]) | |
4586 | break; | |
4587 | } | |
b99bd4ef | 4588 | |
c19d1205 ZW |
4589 | if (j == MAX_LITTLENUMS) |
4590 | { | |
4591 | *str = input_line_pointer; | |
4592 | input_line_pointer = save_in; | |
4593 | return i + 8; | |
4594 | } | |
4595 | } | |
4596 | } | |
b99bd4ef NC |
4597 | } |
4598 | ||
c19d1205 ZW |
4599 | *str = input_line_pointer; |
4600 | input_line_pointer = save_in; | |
4601 | inst.error = _("invalid FPA immediate expression"); | |
4602 | return FAIL; | |
b99bd4ef NC |
4603 | } |
4604 | ||
136da414 JB |
4605 | /* Returns 1 if a number has "quarter-precision" float format |
4606 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4607 | ||
4608 | static int | |
4609 | is_quarter_float (unsigned imm) | |
4610 | { | |
4611 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4612 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4613 | } | |
4614 | ||
4615 | /* Parse an 8-bit "quarter-precision" floating point number of the form: | |
4616 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4617 | The zero and minus-zero cases need special handling, since they can't be |
4618 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4619 | loaded as integer constants. */ | |
136da414 JB |
4620 | |
4621 | static unsigned | |
4622 | parse_qfloat_immediate (char **ccp, int *immed) | |
4623 | { | |
4624 | char *str = *ccp; | |
c96612cc | 4625 | char *fpnum; |
136da414 | 4626 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4627 | int found_fpchar = 0; |
5f4273c7 | 4628 | |
136da414 | 4629 | skip_past_char (&str, '#'); |
5f4273c7 | 4630 | |
c96612cc JB |
4631 | /* We must not accidentally parse an integer as a floating-point number. Make |
4632 | sure that the value we parse is not an integer by checking for special | |
4633 | characters '.' or 'e'. | |
4634 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4635 | information isn't in a very usable state at parse time. */ | |
4636 | fpnum = str; | |
4637 | skip_whitespace (fpnum); | |
4638 | ||
4639 | if (strncmp (fpnum, "0x", 2) == 0) | |
4640 | return FAIL; | |
4641 | else | |
4642 | { | |
4643 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
4644 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') | |
4645 | { | |
4646 | found_fpchar = 1; | |
4647 | break; | |
4648 | } | |
4649 | ||
4650 | if (!found_fpchar) | |
4651 | return FAIL; | |
4652 | } | |
5f4273c7 | 4653 | |
136da414 JB |
4654 | if ((str = atof_ieee (str, 's', words)) != NULL) |
4655 | { | |
4656 | unsigned fpword = 0; | |
4657 | int i; | |
5f4273c7 | 4658 | |
136da414 JB |
4659 | /* Our FP word must be 32 bits (single-precision FP). */ |
4660 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
4661 | { | |
4662 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
4663 | fpword |= words[i]; | |
4664 | } | |
5f4273c7 | 4665 | |
c96612cc | 4666 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
136da414 JB |
4667 | *immed = fpword; |
4668 | else | |
4669 | return FAIL; | |
4670 | ||
4671 | *ccp = str; | |
5f4273c7 | 4672 | |
136da414 JB |
4673 | return SUCCESS; |
4674 | } | |
5f4273c7 | 4675 | |
136da414 JB |
4676 | return FAIL; |
4677 | } | |
4678 | ||
c19d1205 ZW |
4679 | /* Shift operands. */ |
4680 | enum shift_kind | |
b99bd4ef | 4681 | { |
c19d1205 ZW |
4682 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
4683 | }; | |
b99bd4ef | 4684 | |
c19d1205 ZW |
4685 | struct asm_shift_name |
4686 | { | |
4687 | const char *name; | |
4688 | enum shift_kind kind; | |
4689 | }; | |
b99bd4ef | 4690 | |
c19d1205 ZW |
4691 | /* Third argument to parse_shift. */ |
4692 | enum parse_shift_mode | |
4693 | { | |
4694 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
4695 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
4696 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
4697 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
4698 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
4699 | }; | |
b99bd4ef | 4700 | |
c19d1205 ZW |
4701 | /* Parse a <shift> specifier on an ARM data processing instruction. |
4702 | This has three forms: | |
b99bd4ef | 4703 | |
c19d1205 ZW |
4704 | (LSL|LSR|ASL|ASR|ROR) Rs |
4705 | (LSL|LSR|ASL|ASR|ROR) #imm | |
4706 | RRX | |
b99bd4ef | 4707 | |
c19d1205 ZW |
4708 | Note that ASL is assimilated to LSL in the instruction encoding, and |
4709 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 4710 | |
c19d1205 ZW |
4711 | static int |
4712 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 4713 | { |
c19d1205 ZW |
4714 | const struct asm_shift_name *shift_name; |
4715 | enum shift_kind shift; | |
4716 | char *s = *str; | |
4717 | char *p = s; | |
4718 | int reg; | |
b99bd4ef | 4719 | |
c19d1205 ZW |
4720 | for (p = *str; ISALPHA (*p); p++) |
4721 | ; | |
b99bd4ef | 4722 | |
c19d1205 | 4723 | if (p == *str) |
b99bd4ef | 4724 | { |
c19d1205 ZW |
4725 | inst.error = _("shift expression expected"); |
4726 | return FAIL; | |
b99bd4ef NC |
4727 | } |
4728 | ||
21d799b5 NC |
4729 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
4730 | p - *str); | |
c19d1205 ZW |
4731 | |
4732 | if (shift_name == NULL) | |
b99bd4ef | 4733 | { |
c19d1205 ZW |
4734 | inst.error = _("shift expression expected"); |
4735 | return FAIL; | |
b99bd4ef NC |
4736 | } |
4737 | ||
c19d1205 | 4738 | shift = shift_name->kind; |
b99bd4ef | 4739 | |
c19d1205 ZW |
4740 | switch (mode) |
4741 | { | |
4742 | case NO_SHIFT_RESTRICT: | |
4743 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 4744 | |
c19d1205 ZW |
4745 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
4746 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
4747 | { | |
4748 | inst.error = _("'LSL' or 'ASR' required"); | |
4749 | return FAIL; | |
4750 | } | |
4751 | break; | |
b99bd4ef | 4752 | |
c19d1205 ZW |
4753 | case SHIFT_LSL_IMMEDIATE: |
4754 | if (shift != SHIFT_LSL) | |
4755 | { | |
4756 | inst.error = _("'LSL' required"); | |
4757 | return FAIL; | |
4758 | } | |
4759 | break; | |
b99bd4ef | 4760 | |
c19d1205 ZW |
4761 | case SHIFT_ASR_IMMEDIATE: |
4762 | if (shift != SHIFT_ASR) | |
4763 | { | |
4764 | inst.error = _("'ASR' required"); | |
4765 | return FAIL; | |
4766 | } | |
4767 | break; | |
b99bd4ef | 4768 | |
c19d1205 ZW |
4769 | default: abort (); |
4770 | } | |
b99bd4ef | 4771 | |
c19d1205 ZW |
4772 | if (shift != SHIFT_RRX) |
4773 | { | |
4774 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
4775 | skip_whitespace (p); | |
b99bd4ef | 4776 | |
c19d1205 | 4777 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 4778 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4779 | { |
4780 | inst.operands[i].imm = reg; | |
4781 | inst.operands[i].immisreg = 1; | |
4782 | } | |
4783 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4784 | return FAIL; | |
4785 | } | |
4786 | inst.operands[i].shift_kind = shift; | |
4787 | inst.operands[i].shifted = 1; | |
4788 | *str = p; | |
4789 | return SUCCESS; | |
b99bd4ef NC |
4790 | } |
4791 | ||
c19d1205 | 4792 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 4793 | |
c19d1205 ZW |
4794 | #<immediate> |
4795 | #<immediate>, <rotate> | |
4796 | <Rm> | |
4797 | <Rm>, <shift> | |
b99bd4ef | 4798 | |
c19d1205 ZW |
4799 | where <shift> is defined by parse_shift above, and <rotate> is a |
4800 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 4801 | is deferred to md_apply_fix. */ |
b99bd4ef | 4802 | |
c19d1205 ZW |
4803 | static int |
4804 | parse_shifter_operand (char **str, int i) | |
4805 | { | |
4806 | int value; | |
91d6fa6a | 4807 | expressionS exp; |
b99bd4ef | 4808 | |
dcbf9037 | 4809 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4810 | { |
4811 | inst.operands[i].reg = value; | |
4812 | inst.operands[i].isreg = 1; | |
b99bd4ef | 4813 | |
c19d1205 ZW |
4814 | /* parse_shift will override this if appropriate */ |
4815 | inst.reloc.exp.X_op = O_constant; | |
4816 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 4817 | |
c19d1205 ZW |
4818 | if (skip_past_comma (str) == FAIL) |
4819 | return SUCCESS; | |
b99bd4ef | 4820 | |
c19d1205 ZW |
4821 | /* Shift operation on register. */ |
4822 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
4823 | } |
4824 | ||
c19d1205 ZW |
4825 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
4826 | return FAIL; | |
b99bd4ef | 4827 | |
c19d1205 | 4828 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 4829 | { |
c19d1205 | 4830 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 4831 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 4832 | return FAIL; |
b99bd4ef | 4833 | |
91d6fa6a | 4834 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
4835 | { |
4836 | inst.error = _("constant expression expected"); | |
4837 | return FAIL; | |
4838 | } | |
b99bd4ef | 4839 | |
91d6fa6a | 4840 | value = exp.X_add_number; |
c19d1205 ZW |
4841 | if (value < 0 || value > 30 || value % 2 != 0) |
4842 | { | |
4843 | inst.error = _("invalid rotation"); | |
4844 | return FAIL; | |
4845 | } | |
4846 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
4847 | { | |
4848 | inst.error = _("invalid constant"); | |
4849 | return FAIL; | |
4850 | } | |
09d92015 | 4851 | |
55cf6793 | 4852 | /* Convert to decoded value. md_apply_fix will put it back. */ |
c19d1205 ZW |
4853 | inst.reloc.exp.X_add_number |
4854 | = (((inst.reloc.exp.X_add_number << (32 - value)) | |
4855 | | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); | |
09d92015 MM |
4856 | } |
4857 | ||
c19d1205 ZW |
4858 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
4859 | inst.reloc.pc_rel = 0; | |
4860 | return SUCCESS; | |
09d92015 MM |
4861 | } |
4862 | ||
4962c51a MS |
4863 | /* Group relocation information. Each entry in the table contains the |
4864 | textual name of the relocation as may appear in assembler source | |
4865 | and must end with a colon. | |
4866 | Along with this textual name are the relocation codes to be used if | |
4867 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
4868 | an LDR, an LDRS, or an LDC. */ | |
4869 | ||
4870 | struct group_reloc_table_entry | |
4871 | { | |
4872 | const char *name; | |
4873 | int alu_code; | |
4874 | int ldr_code; | |
4875 | int ldrs_code; | |
4876 | int ldc_code; | |
4877 | }; | |
4878 | ||
4879 | typedef enum | |
4880 | { | |
4881 | /* Varieties of non-ALU group relocation. */ | |
4882 | ||
4883 | GROUP_LDR, | |
4884 | GROUP_LDRS, | |
4885 | GROUP_LDC | |
4886 | } group_reloc_type; | |
4887 | ||
4888 | static struct group_reloc_table_entry group_reloc_table[] = | |
4889 | { /* Program counter relative: */ | |
4890 | { "pc_g0_nc", | |
4891 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
4892 | 0, /* LDR */ | |
4893 | 0, /* LDRS */ | |
4894 | 0 }, /* LDC */ | |
4895 | { "pc_g0", | |
4896 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
4897 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
4898 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
4899 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
4900 | { "pc_g1_nc", | |
4901 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
4902 | 0, /* LDR */ | |
4903 | 0, /* LDRS */ | |
4904 | 0 }, /* LDC */ | |
4905 | { "pc_g1", | |
4906 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
4907 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
4908 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
4909 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
4910 | { "pc_g2", | |
4911 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
4912 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
4913 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
4914 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
4915 | /* Section base relative */ | |
4916 | { "sb_g0_nc", | |
4917 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
4918 | 0, /* LDR */ | |
4919 | 0, /* LDRS */ | |
4920 | 0 }, /* LDC */ | |
4921 | { "sb_g0", | |
4922 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
4923 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
4924 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
4925 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
4926 | { "sb_g1_nc", | |
4927 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
4928 | 0, /* LDR */ | |
4929 | 0, /* LDRS */ | |
4930 | 0 }, /* LDC */ | |
4931 | { "sb_g1", | |
4932 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
4933 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
4934 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
4935 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
4936 | { "sb_g2", | |
4937 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
4938 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
4939 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
4940 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
4941 | ||
4942 | /* Given the address of a pointer pointing to the textual name of a group | |
4943 | relocation as may appear in assembler source, attempt to find its details | |
4944 | in group_reloc_table. The pointer will be updated to the character after | |
4945 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
4946 | otherwise. On success, *entry will be updated to point at the relevant | |
4947 | group_reloc_table entry. */ | |
4948 | ||
4949 | static int | |
4950 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
4951 | { | |
4952 | unsigned int i; | |
4953 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
4954 | { | |
4955 | int length = strlen (group_reloc_table[i].name); | |
4956 | ||
5f4273c7 NC |
4957 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
4958 | && (*str)[length] == ':') | |
4962c51a MS |
4959 | { |
4960 | *out = &group_reloc_table[i]; | |
4961 | *str += (length + 1); | |
4962 | return SUCCESS; | |
4963 | } | |
4964 | } | |
4965 | ||
4966 | return FAIL; | |
4967 | } | |
4968 | ||
4969 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
4970 | (as for parse_shifter_operand) where group relocations are allowed: | |
4971 | ||
4972 | #<immediate> | |
4973 | #<immediate>, <rotate> | |
4974 | #:<group_reloc>:<expression> | |
4975 | <Rm> | |
4976 | <Rm>, <shift> | |
4977 | ||
4978 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
4979 | The hashes are optional. | |
4980 | ||
4981 | Everything else is as for parse_shifter_operand. */ | |
4982 | ||
4983 | static parse_operand_result | |
4984 | parse_shifter_operand_group_reloc (char **str, int i) | |
4985 | { | |
4986 | /* Determine if we have the sequence of characters #: or just : | |
4987 | coming next. If we do, then we check for a group relocation. | |
4988 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
4989 | ||
4990 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
4991 | || (*str)[0] == ':') | |
4992 | { | |
4993 | struct group_reloc_table_entry *entry; | |
4994 | ||
4995 | if ((*str)[0] == '#') | |
4996 | (*str) += 2; | |
4997 | else | |
4998 | (*str)++; | |
4999 | ||
5000 | /* Try to parse a group relocation. Anything else is an error. */ | |
5001 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
5002 | { | |
5003 | inst.error = _("unknown group relocation"); | |
5004 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5005 | } | |
5006 | ||
5007 | /* We now have the group relocation table entry corresponding to | |
5008 | the name in the assembler source. Next, we parse the expression. */ | |
5009 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) | |
5010 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5011 | ||
5012 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 5013 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 5014 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
5015 | |
5016 | return PARSE_OPERAND_SUCCESS; | |
5017 | } | |
5018 | else | |
5019 | return parse_shifter_operand (str, i) == SUCCESS | |
5020 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; | |
5021 | ||
5022 | /* Never reached. */ | |
5023 | } | |
5024 | ||
8e560766 MGD |
5025 | /* Parse a Neon alignment expression. Information is written to |
5026 | inst.operands[i]. We assume the initial ':' has been skipped. | |
5027 | ||
5028 | align .imm = align << 8, .immisalign=1, .preind=0 */ | |
5029 | static parse_operand_result | |
5030 | parse_neon_alignment (char **str, int i) | |
5031 | { | |
5032 | char *p = *str; | |
5033 | expressionS exp; | |
5034 | ||
5035 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5036 | ||
5037 | if (exp.X_op != O_constant) | |
5038 | { | |
5039 | inst.error = _("alignment must be constant"); | |
5040 | return PARSE_OPERAND_FAIL; | |
5041 | } | |
5042 | ||
5043 | inst.operands[i].imm = exp.X_add_number << 8; | |
5044 | inst.operands[i].immisalign = 1; | |
5045 | /* Alignments are not pre-indexes. */ | |
5046 | inst.operands[i].preind = 0; | |
5047 | ||
5048 | *str = p; | |
5049 | return PARSE_OPERAND_SUCCESS; | |
5050 | } | |
5051 | ||
c19d1205 ZW |
5052 | /* Parse all forms of an ARM address expression. Information is written |
5053 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5054 | |
c19d1205 | 5055 | Preindexed addressing (.preind=1): |
09d92015 | 5056 | |
c19d1205 ZW |
5057 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5058 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5059 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5060 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5061 | |
c19d1205 | 5062 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5063 | |
c19d1205 | 5064 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5065 | |
c19d1205 ZW |
5066 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5067 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5068 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5069 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5070 | |
c19d1205 | 5071 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5072 | |
c19d1205 | 5073 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5074 | |
c19d1205 | 5075 | Other: |
09d92015 | 5076 | |
c19d1205 ZW |
5077 | [Rn]{!} shorthand for [Rn,#0]{!} |
5078 | =immediate .isreg=0 .reloc.exp=immediate | |
5079 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5080 | |
c19d1205 ZW |
5081 | It is the caller's responsibility to check for addressing modes not |
5082 | supported by the instruction, and to set inst.reloc.type. */ | |
5083 | ||
4962c51a MS |
5084 | static parse_operand_result |
5085 | parse_address_main (char **str, int i, int group_relocations, | |
5086 | group_reloc_type group_type) | |
09d92015 | 5087 | { |
c19d1205 ZW |
5088 | char *p = *str; |
5089 | int reg; | |
09d92015 | 5090 | |
c19d1205 | 5091 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5092 | { |
c19d1205 ZW |
5093 | if (skip_past_char (&p, '=') == FAIL) |
5094 | { | |
974da60d | 5095 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5096 | inst.reloc.pc_rel = 1; |
5097 | inst.operands[i].reg = REG_PC; | |
5098 | inst.operands[i].isreg = 1; | |
5099 | inst.operands[i].preind = 1; | |
5100 | } | |
974da60d | 5101 | /* Otherwise a load-constant pseudo op, no special treatment needed here. */ |
09d92015 | 5102 | |
c19d1205 | 5103 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
4962c51a | 5104 | return PARSE_OPERAND_FAIL; |
09d92015 | 5105 | |
c19d1205 | 5106 | *str = p; |
4962c51a | 5107 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5108 | } |
5109 | ||
dcbf9037 | 5110 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5111 | { |
c19d1205 | 5112 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5113 | return PARSE_OPERAND_FAIL; |
09d92015 | 5114 | } |
c19d1205 ZW |
5115 | inst.operands[i].reg = reg; |
5116 | inst.operands[i].isreg = 1; | |
09d92015 | 5117 | |
c19d1205 | 5118 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5119 | { |
c19d1205 | 5120 | inst.operands[i].preind = 1; |
09d92015 | 5121 | |
c19d1205 ZW |
5122 | if (*p == '+') p++; |
5123 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5124 | ||
dcbf9037 | 5125 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5126 | { |
c19d1205 ZW |
5127 | inst.operands[i].imm = reg; |
5128 | inst.operands[i].immisreg = 1; | |
5129 | ||
5130 | if (skip_past_comma (&p) == SUCCESS) | |
5131 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5132 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5133 | } |
5287ad62 | 5134 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5135 | { |
5136 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5137 | code before we get to see it here. This may be subject to | |
5138 | change. */ | |
5139 | parse_operand_result result = parse_neon_alignment (&p, i); | |
5140 | ||
5141 | if (result != PARSE_OPERAND_SUCCESS) | |
5142 | return result; | |
5143 | } | |
c19d1205 ZW |
5144 | else |
5145 | { | |
5146 | if (inst.operands[i].negative) | |
5147 | { | |
5148 | inst.operands[i].negative = 0; | |
5149 | p--; | |
5150 | } | |
4962c51a | 5151 | |
5f4273c7 NC |
5152 | if (group_relocations |
5153 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5154 | { |
5155 | struct group_reloc_table_entry *entry; | |
5156 | ||
5157 | /* Skip over the #: or : sequence. */ | |
5158 | if (*p == '#') | |
5159 | p += 2; | |
5160 | else | |
5161 | p++; | |
5162 | ||
5163 | /* Try to parse a group relocation. Anything else is an | |
5164 | error. */ | |
5165 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) | |
5166 | { | |
5167 | inst.error = _("unknown group relocation"); | |
5168 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5169 | } | |
5170 | ||
5171 | /* We now have the group relocation table entry corresponding to | |
5172 | the name in the assembler source. Next, we parse the | |
5173 | expression. */ | |
5174 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5175 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5176 | ||
5177 | /* Record the relocation type. */ | |
5178 | switch (group_type) | |
5179 | { | |
5180 | case GROUP_LDR: | |
21d799b5 | 5181 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; |
4962c51a MS |
5182 | break; |
5183 | ||
5184 | case GROUP_LDRS: | |
21d799b5 | 5185 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; |
4962c51a MS |
5186 | break; |
5187 | ||
5188 | case GROUP_LDC: | |
21d799b5 | 5189 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; |
4962c51a MS |
5190 | break; |
5191 | ||
5192 | default: | |
9c2799c2 | 5193 | gas_assert (0); |
4962c51a MS |
5194 | } |
5195 | ||
5196 | if (inst.reloc.type == 0) | |
5197 | { | |
5198 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5199 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5200 | } | |
5201 | } | |
5202 | else | |
26d97720 NS |
5203 | { |
5204 | char *q = p; | |
5205 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5206 | return PARSE_OPERAND_FAIL; | |
5207 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
5208 | if (inst.reloc.exp.X_op == O_constant | |
5209 | && inst.reloc.exp.X_add_number == 0) | |
5210 | { | |
5211 | skip_whitespace (q); | |
5212 | if (*q == '#') | |
5213 | { | |
5214 | q++; | |
5215 | skip_whitespace (q); | |
5216 | } | |
5217 | if (*q == '-') | |
5218 | inst.operands[i].negative = 1; | |
5219 | } | |
5220 | } | |
09d92015 MM |
5221 | } |
5222 | } | |
8e560766 MGD |
5223 | else if (skip_past_char (&p, ':') == SUCCESS) |
5224 | { | |
5225 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5226 | before we get to see it here. This may be subject to change. */ | |
5227 | parse_operand_result result = parse_neon_alignment (&p, i); | |
5228 | ||
5229 | if (result != PARSE_OPERAND_SUCCESS) | |
5230 | return result; | |
5231 | } | |
09d92015 | 5232 | |
c19d1205 | 5233 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5234 | { |
c19d1205 | 5235 | inst.error = _("']' expected"); |
4962c51a | 5236 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5237 | } |
5238 | ||
c19d1205 ZW |
5239 | if (skip_past_char (&p, '!') == SUCCESS) |
5240 | inst.operands[i].writeback = 1; | |
09d92015 | 5241 | |
c19d1205 | 5242 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5243 | { |
c19d1205 ZW |
5244 | if (skip_past_char (&p, '{') == SUCCESS) |
5245 | { | |
5246 | /* [Rn], {expr} - unindexed, with option */ | |
5247 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5248 | 0, 255, TRUE) == FAIL) |
4962c51a | 5249 | return PARSE_OPERAND_FAIL; |
09d92015 | 5250 | |
c19d1205 ZW |
5251 | if (skip_past_char (&p, '}') == FAIL) |
5252 | { | |
5253 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5254 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5255 | } |
5256 | if (inst.operands[i].preind) | |
5257 | { | |
5258 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5259 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5260 | } |
5261 | *str = p; | |
4962c51a | 5262 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5263 | } |
c19d1205 ZW |
5264 | else |
5265 | { | |
5266 | inst.operands[i].postind = 1; | |
5267 | inst.operands[i].writeback = 1; | |
09d92015 | 5268 | |
c19d1205 ZW |
5269 | if (inst.operands[i].preind) |
5270 | { | |
5271 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5272 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5273 | } |
09d92015 | 5274 | |
c19d1205 ZW |
5275 | if (*p == '+') p++; |
5276 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5277 | |
dcbf9037 | 5278 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5279 | { |
5287ad62 JB |
5280 | /* We might be using the immediate for alignment already. If we |
5281 | are, OR the register number into the low-order bits. */ | |
5282 | if (inst.operands[i].immisalign) | |
5283 | inst.operands[i].imm |= reg; | |
5284 | else | |
5285 | inst.operands[i].imm = reg; | |
c19d1205 | 5286 | inst.operands[i].immisreg = 1; |
a737bd4d | 5287 | |
c19d1205 ZW |
5288 | if (skip_past_comma (&p) == SUCCESS) |
5289 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5290 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5291 | } |
5292 | else | |
5293 | { | |
26d97720 | 5294 | char *q = p; |
c19d1205 ZW |
5295 | if (inst.operands[i].negative) |
5296 | { | |
5297 | inst.operands[i].negative = 0; | |
5298 | p--; | |
5299 | } | |
5300 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5301 | return PARSE_OPERAND_FAIL; |
26d97720 NS |
5302 | /* If the offset is 0, find out if it's a +0 or -0. */ |
5303 | if (inst.reloc.exp.X_op == O_constant | |
5304 | && inst.reloc.exp.X_add_number == 0) | |
5305 | { | |
5306 | skip_whitespace (q); | |
5307 | if (*q == '#') | |
5308 | { | |
5309 | q++; | |
5310 | skip_whitespace (q); | |
5311 | } | |
5312 | if (*q == '-') | |
5313 | inst.operands[i].negative = 1; | |
5314 | } | |
c19d1205 ZW |
5315 | } |
5316 | } | |
a737bd4d NC |
5317 | } |
5318 | ||
c19d1205 ZW |
5319 | /* If at this point neither .preind nor .postind is set, we have a |
5320 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5321 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5322 | { | |
5323 | inst.operands[i].preind = 1; | |
5324 | inst.reloc.exp.X_op = O_constant; | |
5325 | inst.reloc.exp.X_add_number = 0; | |
5326 | } | |
5327 | *str = p; | |
4962c51a MS |
5328 | return PARSE_OPERAND_SUCCESS; |
5329 | } | |
5330 | ||
5331 | static int | |
5332 | parse_address (char **str, int i) | |
5333 | { | |
21d799b5 | 5334 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
4962c51a MS |
5335 | ? SUCCESS : FAIL; |
5336 | } | |
5337 | ||
5338 | static parse_operand_result | |
5339 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5340 | { | |
5341 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5342 | } |
5343 | ||
b6895b4f PB |
5344 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5345 | static int | |
5346 | parse_half (char **str) | |
5347 | { | |
5348 | char * p; | |
5f4273c7 | 5349 | |
b6895b4f PB |
5350 | p = *str; |
5351 | skip_past_char (&p, '#'); | |
5f4273c7 | 5352 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5353 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5354 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5355 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5356 | ||
5357 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5358 | { | |
5359 | p += 9; | |
5f4273c7 | 5360 | skip_whitespace (p); |
b6895b4f PB |
5361 | } |
5362 | ||
5363 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5364 | return FAIL; | |
5365 | ||
5366 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5367 | { | |
5368 | if (inst.reloc.exp.X_op != O_constant) | |
5369 | { | |
5370 | inst.error = _("constant expression expected"); | |
5371 | return FAIL; | |
5372 | } | |
5373 | if (inst.reloc.exp.X_add_number < 0 | |
5374 | || inst.reloc.exp.X_add_number > 0xffff) | |
5375 | { | |
5376 | inst.error = _("immediate value out of range"); | |
5377 | return FAIL; | |
5378 | } | |
5379 | } | |
5380 | *str = p; | |
5381 | return SUCCESS; | |
5382 | } | |
5383 | ||
c19d1205 | 5384 | /* Miscellaneous. */ |
a737bd4d | 5385 | |
c19d1205 ZW |
5386 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5387 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5388 | static int | |
d2cd1205 | 5389 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 5390 | { |
c19d1205 ZW |
5391 | char *p; |
5392 | unsigned long psr_field; | |
62b3e311 PB |
5393 | const struct asm_psr *psr; |
5394 | char *start; | |
d2cd1205 | 5395 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 5396 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 5397 | |
a4482bb6 NC |
5398 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
5399 | be TRUE, but we want to ignore it in this case as we are building for any | |
5400 | CPU type, including non-m variants. */ | |
5401 | if (selected_cpu.core == arm_arch_any.core) | |
5402 | m_profile = FALSE; | |
5403 | ||
c19d1205 ZW |
5404 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5405 | feature for ease of use and backwards compatibility. */ | |
5406 | p = *str; | |
62b3e311 | 5407 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
5408 | { |
5409 | if (m_profile) | |
5410 | goto unsupported_psr; | |
5411 | ||
5412 | psr_field = SPSR_BIT; | |
5413 | } | |
5414 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
5415 | { | |
5416 | if (m_profile) | |
5417 | goto unsupported_psr; | |
5418 | ||
5419 | psr_field = 0; | |
5420 | } | |
5421 | else if (strncasecmp (p, "APSR", 4) == 0) | |
5422 | { | |
5423 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
5424 | and ARMv7-R architecture CPUs. */ | |
5425 | is_apsr = TRUE; | |
5426 | psr_field = 0; | |
5427 | } | |
5428 | else if (m_profile) | |
62b3e311 PB |
5429 | { |
5430 | start = p; | |
5431 | do | |
5432 | p++; | |
5433 | while (ISALNUM (*p) || *p == '_'); | |
5434 | ||
d2cd1205 JB |
5435 | if (strncasecmp (start, "iapsr", 5) == 0 |
5436 | || strncasecmp (start, "eapsr", 5) == 0 | |
5437 | || strncasecmp (start, "xpsr", 4) == 0 | |
5438 | || strncasecmp (start, "psr", 3) == 0) | |
5439 | p = start + strcspn (start, "rR") + 1; | |
5440 | ||
21d799b5 NC |
5441 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
5442 | p - start); | |
d2cd1205 | 5443 | |
62b3e311 PB |
5444 | if (!psr) |
5445 | return FAIL; | |
09d92015 | 5446 | |
d2cd1205 JB |
5447 | /* If APSR is being written, a bitfield may be specified. Note that |
5448 | APSR itself is handled above. */ | |
5449 | if (psr->field <= 3) | |
5450 | { | |
5451 | psr_field = psr->field; | |
5452 | is_apsr = TRUE; | |
5453 | goto check_suffix; | |
5454 | } | |
5455 | ||
62b3e311 | 5456 | *str = p; |
d2cd1205 JB |
5457 | /* M-profile MSR instructions have the mask field set to "10", except |
5458 | *PSR variants which modify APSR, which may use a different mask (and | |
5459 | have been handled already). Do that by setting the PSR_f field | |
5460 | here. */ | |
5461 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 5462 | } |
d2cd1205 JB |
5463 | else |
5464 | goto unsupported_psr; | |
09d92015 | 5465 | |
62b3e311 | 5466 | p += 4; |
d2cd1205 | 5467 | check_suffix: |
c19d1205 ZW |
5468 | if (*p == '_') |
5469 | { | |
5470 | /* A suffix follows. */ | |
c19d1205 ZW |
5471 | p++; |
5472 | start = p; | |
a737bd4d | 5473 | |
c19d1205 ZW |
5474 | do |
5475 | p++; | |
5476 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5477 | |
d2cd1205 JB |
5478 | if (is_apsr) |
5479 | { | |
5480 | /* APSR uses a notation for bits, rather than fields. */ | |
5481 | unsigned int nzcvq_bits = 0; | |
5482 | unsigned int g_bit = 0; | |
5483 | char *bit; | |
5484 | ||
5485 | for (bit = start; bit != p; bit++) | |
5486 | { | |
5487 | switch (TOLOWER (*bit)) | |
5488 | { | |
5489 | case 'n': | |
5490 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
5491 | break; | |
5492 | ||
5493 | case 'z': | |
5494 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
5495 | break; | |
5496 | ||
5497 | case 'c': | |
5498 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
5499 | break; | |
5500 | ||
5501 | case 'v': | |
5502 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
5503 | break; | |
5504 | ||
5505 | case 'q': | |
5506 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
5507 | break; | |
5508 | ||
5509 | case 'g': | |
5510 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
5511 | break; | |
5512 | ||
5513 | default: | |
5514 | inst.error = _("unexpected bit specified after APSR"); | |
5515 | return FAIL; | |
5516 | } | |
5517 | } | |
5518 | ||
5519 | if (nzcvq_bits == 0x1f) | |
5520 | psr_field |= PSR_f; | |
5521 | ||
5522 | if (g_bit == 0x1) | |
5523 | { | |
5524 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
5525 | { | |
5526 | inst.error = _("selected processor does not " | |
5527 | "support DSP extension"); | |
5528 | return FAIL; | |
5529 | } | |
5530 | ||
5531 | psr_field |= PSR_s; | |
5532 | } | |
5533 | ||
5534 | if ((nzcvq_bits & 0x20) != 0 | |
5535 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
5536 | || (g_bit & 0x2) != 0) | |
5537 | { | |
5538 | inst.error = _("bad bitmask specified after APSR"); | |
5539 | return FAIL; | |
5540 | } | |
5541 | } | |
5542 | else | |
5543 | { | |
5544 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, | |
5545 | p - start); | |
5546 | if (!psr) | |
5547 | goto error; | |
a737bd4d | 5548 | |
d2cd1205 JB |
5549 | psr_field |= psr->field; |
5550 | } | |
a737bd4d | 5551 | } |
c19d1205 | 5552 | else |
a737bd4d | 5553 | { |
c19d1205 ZW |
5554 | if (ISALNUM (*p)) |
5555 | goto error; /* Garbage after "[CS]PSR". */ | |
5556 | ||
d2cd1205 JB |
5557 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
5558 | is deprecated, but allow it anyway. */ | |
5559 | if (is_apsr && lhs) | |
5560 | { | |
5561 | psr_field |= PSR_f; | |
5562 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
5563 | "deprecated")); | |
5564 | } | |
5565 | else if (!m_profile) | |
5566 | /* These bits are never right for M-profile devices: don't set them | |
5567 | (only code paths which read/write APSR reach here). */ | |
5568 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5569 | } |
c19d1205 ZW |
5570 | *str = p; |
5571 | return psr_field; | |
a737bd4d | 5572 | |
d2cd1205 JB |
5573 | unsupported_psr: |
5574 | inst.error = _("selected processor does not support requested special " | |
5575 | "purpose register"); | |
5576 | return FAIL; | |
5577 | ||
c19d1205 ZW |
5578 | error: |
5579 | inst.error = _("flag for {c}psr instruction expected"); | |
5580 | return FAIL; | |
a737bd4d NC |
5581 | } |
5582 | ||
c19d1205 ZW |
5583 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5584 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5585 | |
c19d1205 ZW |
5586 | static int |
5587 | parse_cps_flags (char **str) | |
a737bd4d | 5588 | { |
c19d1205 ZW |
5589 | int val = 0; |
5590 | int saw_a_flag = 0; | |
5591 | char *s = *str; | |
a737bd4d | 5592 | |
c19d1205 ZW |
5593 | for (;;) |
5594 | switch (*s++) | |
5595 | { | |
5596 | case '\0': case ',': | |
5597 | goto done; | |
a737bd4d | 5598 | |
c19d1205 ZW |
5599 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5600 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5601 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5602 | |
c19d1205 ZW |
5603 | default: |
5604 | inst.error = _("unrecognized CPS flag"); | |
5605 | return FAIL; | |
5606 | } | |
a737bd4d | 5607 | |
c19d1205 ZW |
5608 | done: |
5609 | if (saw_a_flag == 0) | |
a737bd4d | 5610 | { |
c19d1205 ZW |
5611 | inst.error = _("missing CPS flags"); |
5612 | return FAIL; | |
a737bd4d | 5613 | } |
a737bd4d | 5614 | |
c19d1205 ZW |
5615 | *str = s - 1; |
5616 | return val; | |
a737bd4d NC |
5617 | } |
5618 | ||
c19d1205 ZW |
5619 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5620 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5621 | |
5622 | static int | |
c19d1205 | 5623 | parse_endian_specifier (char **str) |
a737bd4d | 5624 | { |
c19d1205 ZW |
5625 | int little_endian; |
5626 | char *s = *str; | |
a737bd4d | 5627 | |
c19d1205 ZW |
5628 | if (strncasecmp (s, "BE", 2)) |
5629 | little_endian = 0; | |
5630 | else if (strncasecmp (s, "LE", 2)) | |
5631 | little_endian = 1; | |
5632 | else | |
a737bd4d | 5633 | { |
c19d1205 | 5634 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5635 | return FAIL; |
5636 | } | |
5637 | ||
c19d1205 | 5638 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 5639 | { |
c19d1205 | 5640 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5641 | return FAIL; |
5642 | } | |
5643 | ||
c19d1205 ZW |
5644 | *str = s + 2; |
5645 | return little_endian; | |
5646 | } | |
a737bd4d | 5647 | |
c19d1205 ZW |
5648 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
5649 | value suitable for poking into the rotate field of an sxt or sxta | |
5650 | instruction, or FAIL on error. */ | |
5651 | ||
5652 | static int | |
5653 | parse_ror (char **str) | |
5654 | { | |
5655 | int rot; | |
5656 | char *s = *str; | |
5657 | ||
5658 | if (strncasecmp (s, "ROR", 3) == 0) | |
5659 | s += 3; | |
5660 | else | |
a737bd4d | 5661 | { |
c19d1205 | 5662 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
5663 | return FAIL; |
5664 | } | |
c19d1205 ZW |
5665 | |
5666 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
5667 | return FAIL; | |
5668 | ||
5669 | switch (rot) | |
a737bd4d | 5670 | { |
c19d1205 ZW |
5671 | case 0: *str = s; return 0x0; |
5672 | case 8: *str = s; return 0x1; | |
5673 | case 16: *str = s; return 0x2; | |
5674 | case 24: *str = s; return 0x3; | |
5675 | ||
5676 | default: | |
5677 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
5678 | return FAIL; |
5679 | } | |
c19d1205 | 5680 | } |
a737bd4d | 5681 | |
c19d1205 ZW |
5682 | /* Parse a conditional code (from conds[] below). The value returned is in the |
5683 | range 0 .. 14, or FAIL. */ | |
5684 | static int | |
5685 | parse_cond (char **str) | |
5686 | { | |
c462b453 | 5687 | char *q; |
c19d1205 | 5688 | const struct asm_cond *c; |
c462b453 PB |
5689 | int n; |
5690 | /* Condition codes are always 2 characters, so matching up to | |
5691 | 3 characters is sufficient. */ | |
5692 | char cond[3]; | |
a737bd4d | 5693 | |
c462b453 PB |
5694 | q = *str; |
5695 | n = 0; | |
5696 | while (ISALPHA (*q) && n < 3) | |
5697 | { | |
e07e6e58 | 5698 | cond[n] = TOLOWER (*q); |
c462b453 PB |
5699 | q++; |
5700 | n++; | |
5701 | } | |
a737bd4d | 5702 | |
21d799b5 | 5703 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 5704 | if (!c) |
a737bd4d | 5705 | { |
c19d1205 | 5706 | inst.error = _("condition required"); |
a737bd4d NC |
5707 | return FAIL; |
5708 | } | |
5709 | ||
c19d1205 ZW |
5710 | *str = q; |
5711 | return c->value; | |
5712 | } | |
5713 | ||
62b3e311 PB |
5714 | /* Parse an option for a barrier instruction. Returns the encoding for the |
5715 | option, or FAIL. */ | |
5716 | static int | |
5717 | parse_barrier (char **str) | |
5718 | { | |
5719 | char *p, *q; | |
5720 | const struct asm_barrier_opt *o; | |
5721 | ||
5722 | p = q = *str; | |
5723 | while (ISALPHA (*q)) | |
5724 | q++; | |
5725 | ||
21d799b5 NC |
5726 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
5727 | q - p); | |
62b3e311 PB |
5728 | if (!o) |
5729 | return FAIL; | |
5730 | ||
5731 | *str = q; | |
5732 | return o->value; | |
5733 | } | |
5734 | ||
92e90b6e PB |
5735 | /* Parse the operands of a table branch instruction. Similar to a memory |
5736 | operand. */ | |
5737 | static int | |
5738 | parse_tb (char **str) | |
5739 | { | |
5740 | char * p = *str; | |
5741 | int reg; | |
5742 | ||
5743 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
5744 | { |
5745 | inst.error = _("'[' expected"); | |
5746 | return FAIL; | |
5747 | } | |
92e90b6e | 5748 | |
dcbf9037 | 5749 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5750 | { |
5751 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5752 | return FAIL; | |
5753 | } | |
5754 | inst.operands[0].reg = reg; | |
5755 | ||
5756 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
5757 | { |
5758 | inst.error = _("',' expected"); | |
5759 | return FAIL; | |
5760 | } | |
5f4273c7 | 5761 | |
dcbf9037 | 5762 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5763 | { |
5764 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5765 | return FAIL; | |
5766 | } | |
5767 | inst.operands[0].imm = reg; | |
5768 | ||
5769 | if (skip_past_comma (&p) == SUCCESS) | |
5770 | { | |
5771 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
5772 | return FAIL; | |
5773 | if (inst.reloc.exp.X_add_number != 1) | |
5774 | { | |
5775 | inst.error = _("invalid shift"); | |
5776 | return FAIL; | |
5777 | } | |
5778 | inst.operands[0].shifted = 1; | |
5779 | } | |
5780 | ||
5781 | if (skip_past_char (&p, ']') == FAIL) | |
5782 | { | |
5783 | inst.error = _("']' expected"); | |
5784 | return FAIL; | |
5785 | } | |
5786 | *str = p; | |
5787 | return SUCCESS; | |
5788 | } | |
5789 | ||
5287ad62 JB |
5790 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
5791 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
5792 | Up to four operands may be read; this function handles setting the |
5793 | ".present" field for each read operand itself. | |
5287ad62 JB |
5794 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
5795 | else returns FAIL. */ | |
5796 | ||
5797 | static int | |
5798 | parse_neon_mov (char **str, int *which_operand) | |
5799 | { | |
5800 | int i = *which_operand, val; | |
5801 | enum arm_reg_type rtype; | |
5802 | char *ptr = *str; | |
dcbf9037 | 5803 | struct neon_type_el optype; |
5f4273c7 | 5804 | |
dcbf9037 | 5805 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5806 | { |
5807 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
5808 | inst.operands[i].reg = val; | |
5809 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 5810 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5811 | inst.operands[i++].present = 1; |
5812 | ||
5813 | if (skip_past_comma (&ptr) == FAIL) | |
5814 | goto wanted_comma; | |
5f4273c7 | 5815 | |
dcbf9037 | 5816 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5287ad62 | 5817 | goto wanted_arm; |
5f4273c7 | 5818 | |
5287ad62 JB |
5819 | inst.operands[i].reg = val; |
5820 | inst.operands[i].isreg = 1; | |
5821 | inst.operands[i].present = 1; | |
5822 | } | |
037e8744 | 5823 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
dcbf9037 | 5824 | != FAIL) |
5287ad62 JB |
5825 | { |
5826 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
5827 | if (skip_past_comma (&ptr) == FAIL) | |
5828 | goto wanted_comma; | |
5f4273c7 | 5829 | |
5287ad62 JB |
5830 | inst.operands[i].reg = val; |
5831 | inst.operands[i].isreg = 1; | |
5832 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5833 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5834 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5835 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5836 | inst.operands[i++].present = 1; |
5837 | ||
dcbf9037 | 5838 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 5839 | { |
037e8744 JB |
5840 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
5841 | Case 13: VMOV <Sd>, <Rm> */ | |
5287ad62 JB |
5842 | inst.operands[i].reg = val; |
5843 | inst.operands[i].isreg = 1; | |
037e8744 | 5844 | inst.operands[i].present = 1; |
5287ad62 JB |
5845 | |
5846 | if (rtype == REG_TYPE_NQ) | |
5847 | { | |
dcbf9037 | 5848 | first_error (_("can't use Neon quad register here")); |
5287ad62 JB |
5849 | return FAIL; |
5850 | } | |
037e8744 JB |
5851 | else if (rtype != REG_TYPE_VFS) |
5852 | { | |
5853 | i++; | |
5854 | if (skip_past_comma (&ptr) == FAIL) | |
5855 | goto wanted_comma; | |
5856 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5857 | goto wanted_arm; | |
5858 | inst.operands[i].reg = val; | |
5859 | inst.operands[i].isreg = 1; | |
5860 | inst.operands[i].present = 1; | |
5861 | } | |
5287ad62 | 5862 | } |
037e8744 JB |
5863 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
5864 | &optype)) != FAIL) | |
5287ad62 JB |
5865 | { |
5866 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
037e8744 JB |
5867 | Case 1: VMOV<c><q> <Dd>, <Dm> |
5868 | Case 8: VMOV.F32 <Sd>, <Sm> | |
5869 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
5287ad62 JB |
5870 | |
5871 | inst.operands[i].reg = val; | |
5872 | inst.operands[i].isreg = 1; | |
5873 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5874 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5875 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5876 | inst.operands[i].vectype = optype; |
5287ad62 | 5877 | inst.operands[i].present = 1; |
5f4273c7 | 5878 | |
037e8744 JB |
5879 | if (skip_past_comma (&ptr) == SUCCESS) |
5880 | { | |
5881 | /* Case 15. */ | |
5882 | i++; | |
5883 | ||
5884 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5885 | goto wanted_arm; | |
5886 | ||
5887 | inst.operands[i].reg = val; | |
5888 | inst.operands[i].isreg = 1; | |
5889 | inst.operands[i++].present = 1; | |
5f4273c7 | 5890 | |
037e8744 JB |
5891 | if (skip_past_comma (&ptr) == FAIL) |
5892 | goto wanted_comma; | |
5f4273c7 | 5893 | |
037e8744 JB |
5894 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5895 | goto wanted_arm; | |
5f4273c7 | 5896 | |
037e8744 JB |
5897 | inst.operands[i].reg = val; |
5898 | inst.operands[i].isreg = 1; | |
5899 | inst.operands[i++].present = 1; | |
5900 | } | |
5287ad62 | 5901 | } |
4641781c PB |
5902 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
5903 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> | |
5904 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
5905 | Case 10: VMOV.F32 <Sd>, #<imm> | |
5906 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
5907 | inst.operands[i].immisfloat = 1; | |
5908 | else if (parse_big_immediate (&ptr, i) == SUCCESS) | |
5909 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> | |
5910 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
5911 | ; | |
5287ad62 JB |
5912 | else |
5913 | { | |
dcbf9037 | 5914 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
5287ad62 JB |
5915 | return FAIL; |
5916 | } | |
5917 | } | |
dcbf9037 | 5918 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5919 | { |
5920 | /* Cases 6, 7. */ | |
5921 | inst.operands[i].reg = val; | |
5922 | inst.operands[i].isreg = 1; | |
5923 | inst.operands[i++].present = 1; | |
5f4273c7 | 5924 | |
5287ad62 JB |
5925 | if (skip_past_comma (&ptr) == FAIL) |
5926 | goto wanted_comma; | |
5f4273c7 | 5927 | |
dcbf9037 | 5928 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5929 | { |
5930 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
5931 | inst.operands[i].reg = val; | |
5932 | inst.operands[i].isscalar = 1; | |
5933 | inst.operands[i].present = 1; | |
dcbf9037 | 5934 | inst.operands[i].vectype = optype; |
5287ad62 | 5935 | } |
dcbf9037 | 5936 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5937 | { |
5938 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
5939 | inst.operands[i].reg = val; | |
5940 | inst.operands[i].isreg = 1; | |
5941 | inst.operands[i++].present = 1; | |
5f4273c7 | 5942 | |
5287ad62 JB |
5943 | if (skip_past_comma (&ptr) == FAIL) |
5944 | goto wanted_comma; | |
5f4273c7 | 5945 | |
037e8744 | 5946 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
dcbf9037 | 5947 | == FAIL) |
5287ad62 | 5948 | { |
037e8744 | 5949 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); |
5287ad62 JB |
5950 | return FAIL; |
5951 | } | |
5952 | ||
5953 | inst.operands[i].reg = val; | |
5954 | inst.operands[i].isreg = 1; | |
037e8744 JB |
5955 | inst.operands[i].isvec = 1; |
5956 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
dcbf9037 | 5957 | inst.operands[i].vectype = optype; |
5287ad62 | 5958 | inst.operands[i].present = 1; |
5f4273c7 | 5959 | |
037e8744 JB |
5960 | if (rtype == REG_TYPE_VFS) |
5961 | { | |
5962 | /* Case 14. */ | |
5963 | i++; | |
5964 | if (skip_past_comma (&ptr) == FAIL) | |
5965 | goto wanted_comma; | |
5966 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
5967 | &optype)) == FAIL) | |
5968 | { | |
5969 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
5970 | return FAIL; | |
5971 | } | |
5972 | inst.operands[i].reg = val; | |
5973 | inst.operands[i].isreg = 1; | |
5974 | inst.operands[i].isvec = 1; | |
5975 | inst.operands[i].issingle = 1; | |
5976 | inst.operands[i].vectype = optype; | |
5977 | inst.operands[i].present = 1; | |
5978 | } | |
5979 | } | |
5980 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) | |
5981 | != FAIL) | |
5982 | { | |
5983 | /* Case 13. */ | |
5984 | inst.operands[i].reg = val; | |
5985 | inst.operands[i].isreg = 1; | |
5986 | inst.operands[i].isvec = 1; | |
5987 | inst.operands[i].issingle = 1; | |
5988 | inst.operands[i].vectype = optype; | |
5989 | inst.operands[i++].present = 1; | |
5287ad62 JB |
5990 | } |
5991 | } | |
5992 | else | |
5993 | { | |
dcbf9037 | 5994 | first_error (_("parse error")); |
5287ad62 JB |
5995 | return FAIL; |
5996 | } | |
5997 | ||
5998 | /* Successfully parsed the operands. Update args. */ | |
5999 | *which_operand = i; | |
6000 | *str = ptr; | |
6001 | return SUCCESS; | |
6002 | ||
5f4273c7 | 6003 | wanted_comma: |
dcbf9037 | 6004 | first_error (_("expected comma")); |
5287ad62 | 6005 | return FAIL; |
5f4273c7 NC |
6006 | |
6007 | wanted_arm: | |
dcbf9037 | 6008 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6009 | return FAIL; |
5287ad62 JB |
6010 | } |
6011 | ||
5be8be5d DG |
6012 | /* Use this macro when the operand constraints are different |
6013 | for ARM and THUMB (e.g. ldrd). */ | |
6014 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6015 | ((arm_operand) | ((thumb_operand) << 16)) | |
6016 | ||
c19d1205 ZW |
6017 | /* Matcher codes for parse_operands. */ |
6018 | enum operand_parse_code | |
6019 | { | |
6020 | OP_stop, /* end of line */ | |
6021 | ||
6022 | OP_RR, /* ARM register */ | |
6023 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6024 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6025 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
55881a11 MGD |
6026 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
6027 | optional trailing ! */ | |
c19d1205 ZW |
6028 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6029 | OP_RCP, /* Coprocessor number */ | |
6030 | OP_RCN, /* Coprocessor register */ | |
6031 | OP_RF, /* FPA register */ | |
6032 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6033 | OP_RVD, /* VFP double precision register (0..15) */ |
6034 | OP_RND, /* Neon double precision register (0..31) */ | |
6035 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 6036 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 6037 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 6038 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6039 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6040 | OP_RVC, /* VFP control register */ |
6041 | OP_RMF, /* Maverick F register */ | |
6042 | OP_RMD, /* Maverick D register */ | |
6043 | OP_RMFX, /* Maverick FX register */ | |
6044 | OP_RMDX, /* Maverick DX register */ | |
6045 | OP_RMAX, /* Maverick AX register */ | |
6046 | OP_RMDS, /* Maverick DSPSC register */ | |
6047 | OP_RIWR, /* iWMMXt wR register */ | |
6048 | OP_RIWC, /* iWMMXt wC register */ | |
6049 | OP_RIWG, /* iWMMXt wCG register */ | |
6050 | OP_RXA, /* XScale accumulator register */ | |
6051 | ||
6052 | OP_REGLST, /* ARM register list */ | |
6053 | OP_VRSLST, /* VFP single-precision register list */ | |
6054 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6055 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6056 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6057 | OP_NSTRLST, /* Neon element/structure list */ | |
6058 | ||
5287ad62 | 6059 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6060 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
5287ad62 | 6061 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 6062 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
6063 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
6064 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
6065 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6066 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 6067 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 6068 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
6069 | |
6070 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6071 | OP_I7, /* immediate value 0 .. 7 */ |
6072 | OP_I15, /* 0 .. 15 */ | |
6073 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6074 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6075 | OP_I31, /* 0 .. 31 */ |
6076 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6077 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6078 | OP_I32z, /* 0 .. 32 */ |
6079 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6080 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6081 | OP_I64, /* 1 .. 64 */ |
6082 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6083 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6084 | |
6085 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6086 | OP_I7b, /* 0 .. 7 */ | |
6087 | OP_I15b, /* 0 .. 15 */ | |
6088 | OP_I31b, /* 0 .. 31 */ | |
6089 | ||
6090 | OP_SH, /* shifter operand */ | |
4962c51a | 6091 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6092 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
6093 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
6094 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
6095 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
6096 | OP_EXP, /* arbitrary expression */ |
6097 | OP_EXPi, /* same, with optional immediate prefix */ | |
6098 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 6099 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
6100 | |
6101 | OP_CPSF, /* CPS flags */ | |
6102 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
6103 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
6104 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 6105 | OP_COND, /* conditional code */ |
92e90b6e | 6106 | OP_TB, /* Table branch. */ |
c19d1205 | 6107 | |
037e8744 JB |
6108 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
6109 | ||
c19d1205 ZW |
6110 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
6111 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
6112 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
6113 | OP_RF_IF, /* FPA register or immediate */ | |
6114 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 6115 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
6116 | |
6117 | /* Optional operands. */ | |
6118 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
6119 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 6120 | OP_oI32b, /* 1 .. 32 */ |
c19d1205 ZW |
6121 | OP_oIffffb, /* 0 .. 65535 */ |
6122 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
6123 | ||
6124 | OP_oRR, /* ARM register */ | |
6125 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 6126 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 6127 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
6128 | OP_oRND, /* Optional Neon double precision register */ |
6129 | OP_oRNQ, /* Optional Neon quad precision register */ | |
6130 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 6131 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
6132 | OP_oSHll, /* LSL immediate */ |
6133 | OP_oSHar, /* ASR immediate */ | |
6134 | OP_oSHllar, /* LSL or ASR immediate */ | |
6135 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 6136 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 6137 | |
5be8be5d DG |
6138 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
6139 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
6140 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
6141 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
6142 | ||
c19d1205 ZW |
6143 | OP_FIRST_OPTIONAL = OP_oI7b |
6144 | }; | |
a737bd4d | 6145 | |
c19d1205 ZW |
6146 | /* Generic instruction operand parser. This does no encoding and no |
6147 | semantic validation; it merely squirrels values away in the inst | |
6148 | structure. Returns SUCCESS or FAIL depending on whether the | |
6149 | specified grammar matched. */ | |
6150 | static int | |
5be8be5d | 6151 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 6152 | { |
5be8be5d | 6153 | unsigned const int *upat = pattern; |
c19d1205 ZW |
6154 | char *backtrack_pos = 0; |
6155 | const char *backtrack_error = 0; | |
6156 | int i, val, backtrack_index = 0; | |
5287ad62 | 6157 | enum arm_reg_type rtype; |
4962c51a | 6158 | parse_operand_result result; |
5be8be5d | 6159 | unsigned int op_parse_code; |
c19d1205 | 6160 | |
e07e6e58 NC |
6161 | #define po_char_or_fail(chr) \ |
6162 | do \ | |
6163 | { \ | |
6164 | if (skip_past_char (&str, chr) == FAIL) \ | |
6165 | goto bad_args; \ | |
6166 | } \ | |
6167 | while (0) | |
c19d1205 | 6168 | |
e07e6e58 NC |
6169 | #define po_reg_or_fail(regtype) \ |
6170 | do \ | |
dcbf9037 | 6171 | { \ |
e07e6e58 NC |
6172 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
6173 | & inst.operands[i].vectype); \ | |
6174 | if (val == FAIL) \ | |
6175 | { \ | |
6176 | first_error (_(reg_expected_msgs[regtype])); \ | |
6177 | goto failure; \ | |
6178 | } \ | |
6179 | inst.operands[i].reg = val; \ | |
6180 | inst.operands[i].isreg = 1; \ | |
6181 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6182 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6183 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
6184 | || rtype == REG_TYPE_VFD \ | |
6185 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 6186 | } \ |
e07e6e58 NC |
6187 | while (0) |
6188 | ||
6189 | #define po_reg_or_goto(regtype, label) \ | |
6190 | do \ | |
6191 | { \ | |
6192 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
6193 | & inst.operands[i].vectype); \ | |
6194 | if (val == FAIL) \ | |
6195 | goto label; \ | |
dcbf9037 | 6196 | \ |
e07e6e58 NC |
6197 | inst.operands[i].reg = val; \ |
6198 | inst.operands[i].isreg = 1; \ | |
6199 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6200 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6201 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
6202 | || rtype == REG_TYPE_VFD \ | |
6203 | || rtype == REG_TYPE_NQ); \ | |
6204 | } \ | |
6205 | while (0) | |
6206 | ||
6207 | #define po_imm_or_fail(min, max, popt) \ | |
6208 | do \ | |
6209 | { \ | |
6210 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6211 | goto failure; \ | |
6212 | inst.operands[i].imm = val; \ | |
6213 | } \ | |
6214 | while (0) | |
6215 | ||
6216 | #define po_scalar_or_goto(elsz, label) \ | |
6217 | do \ | |
6218 | { \ | |
6219 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6220 | if (val == FAIL) \ | |
6221 | goto label; \ | |
6222 | inst.operands[i].reg = val; \ | |
6223 | inst.operands[i].isscalar = 1; \ | |
6224 | } \ | |
6225 | while (0) | |
6226 | ||
6227 | #define po_misc_or_fail(expr) \ | |
6228 | do \ | |
6229 | { \ | |
6230 | if (expr) \ | |
6231 | goto failure; \ | |
6232 | } \ | |
6233 | while (0) | |
6234 | ||
6235 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6236 | do \ | |
6237 | { \ | |
6238 | result = expr; \ | |
6239 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6240 | backtrack_pos = 0; \ | |
6241 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6242 | goto failure; \ | |
6243 | } \ | |
6244 | while (0) | |
4962c51a | 6245 | |
52e7f43d RE |
6246 | #define po_barrier_or_imm(str) \ |
6247 | do \ | |
6248 | { \ | |
6249 | val = parse_barrier (&str); \ | |
6250 | if (val == FAIL) \ | |
6251 | { \ | |
6252 | if (ISALPHA (*str)) \ | |
6253 | goto failure; \ | |
6254 | else \ | |
6255 | goto immediate; \ | |
6256 | } \ | |
6257 | else \ | |
6258 | { \ | |
6259 | if ((inst.instruction & 0xf0) == 0x60 \ | |
6260 | && val != 0xf) \ | |
6261 | { \ | |
6262 | /* ISB can only take SY as an option. */ \ | |
6263 | inst.error = _("invalid barrier type"); \ | |
6264 | goto failure; \ | |
6265 | } \ | |
6266 | } \ | |
6267 | } \ | |
6268 | while (0) | |
6269 | ||
c19d1205 ZW |
6270 | skip_whitespace (str); |
6271 | ||
6272 | for (i = 0; upat[i] != OP_stop; i++) | |
6273 | { | |
5be8be5d DG |
6274 | op_parse_code = upat[i]; |
6275 | if (op_parse_code >= 1<<16) | |
6276 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6277 | : (op_parse_code & ((1<<16)-1)); | |
6278 | ||
6279 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6280 | { |
6281 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6282 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6283 | backtrack_pos = str; |
6284 | backtrack_error = inst.error; | |
6285 | backtrack_index = i; | |
6286 | } | |
6287 | ||
b6702015 | 6288 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6289 | po_char_or_fail (','); |
6290 | ||
5be8be5d | 6291 | switch (op_parse_code) |
c19d1205 ZW |
6292 | { |
6293 | /* Registers */ | |
6294 | case OP_oRRnpc: | |
5be8be5d | 6295 | case OP_oRRnpcsp: |
c19d1205 | 6296 | case OP_RRnpc: |
5be8be5d | 6297 | case OP_RRnpcsp: |
c19d1205 ZW |
6298 | case OP_oRR: |
6299 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6300 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6301 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6302 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6303 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6304 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
5287ad62 JB |
6305 | case OP_oRND: |
6306 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; | |
cd2cf30b PB |
6307 | case OP_RVC: |
6308 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6309 | break; | |
6310 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6311 | coproc_reg: | |
6312 | po_reg_or_fail (REG_TYPE_CN); | |
6313 | break; | |
c19d1205 ZW |
6314 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6315 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6316 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6317 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6318 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6319 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6320 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6321 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6322 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6323 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
5287ad62 JB |
6324 | case OP_oRNQ: |
6325 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; | |
6326 | case OP_oRNDQ: | |
6327 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; | |
037e8744 JB |
6328 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6329 | case OP_oRNSDQ: | |
6330 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5287ad62 JB |
6331 | |
6332 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6333 | scalars are accepted here, so deal with those in later code. */ | |
6334 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6335 | ||
5287ad62 JB |
6336 | case OP_RNDQ_I0: |
6337 | { | |
6338 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6339 | break; | |
6340 | try_imm0: | |
6341 | po_imm_or_fail (0, 0, TRUE); | |
6342 | } | |
6343 | break; | |
6344 | ||
037e8744 JB |
6345 | case OP_RVSD_I0: |
6346 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6347 | break; | |
6348 | ||
5287ad62 JB |
6349 | case OP_RR_RNSC: |
6350 | { | |
6351 | po_scalar_or_goto (8, try_rr); | |
6352 | break; | |
6353 | try_rr: | |
6354 | po_reg_or_fail (REG_TYPE_RN); | |
6355 | } | |
6356 | break; | |
6357 | ||
037e8744 JB |
6358 | case OP_RNSDQ_RNSC: |
6359 | { | |
6360 | po_scalar_or_goto (8, try_nsdq); | |
6361 | break; | |
6362 | try_nsdq: | |
6363 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6364 | } | |
6365 | break; | |
6366 | ||
5287ad62 JB |
6367 | case OP_RNDQ_RNSC: |
6368 | { | |
6369 | po_scalar_or_goto (8, try_ndq); | |
6370 | break; | |
6371 | try_ndq: | |
6372 | po_reg_or_fail (REG_TYPE_NDQ); | |
6373 | } | |
6374 | break; | |
6375 | ||
6376 | case OP_RND_RNSC: | |
6377 | { | |
6378 | po_scalar_or_goto (8, try_vfd); | |
6379 | break; | |
6380 | try_vfd: | |
6381 | po_reg_or_fail (REG_TYPE_VFD); | |
6382 | } | |
6383 | break; | |
6384 | ||
6385 | case OP_VMOV: | |
6386 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6387 | not careful then bad things might happen. */ | |
6388 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6389 | break; | |
6390 | ||
4316f0d2 | 6391 | case OP_RNDQ_Ibig: |
5287ad62 | 6392 | { |
4316f0d2 | 6393 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); |
5287ad62 | 6394 | break; |
4316f0d2 | 6395 | try_immbig: |
5287ad62 JB |
6396 | /* There's a possibility of getting a 64-bit immediate here, so |
6397 | we need special handling. */ | |
6398 | if (parse_big_immediate (&str, i) == FAIL) | |
6399 | { | |
6400 | inst.error = _("immediate value is out of range"); | |
6401 | goto failure; | |
6402 | } | |
6403 | } | |
6404 | break; | |
6405 | ||
6406 | case OP_RNDQ_I63b: | |
6407 | { | |
6408 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6409 | break; | |
6410 | try_shimm: | |
6411 | po_imm_or_fail (0, 63, TRUE); | |
6412 | } | |
6413 | break; | |
c19d1205 ZW |
6414 | |
6415 | case OP_RRnpcb: | |
6416 | po_char_or_fail ('['); | |
6417 | po_reg_or_fail (REG_TYPE_RN); | |
6418 | po_char_or_fail (']'); | |
6419 | break; | |
a737bd4d | 6420 | |
55881a11 | 6421 | case OP_RRnpctw: |
c19d1205 | 6422 | case OP_RRw: |
b6702015 | 6423 | case OP_oRRw: |
c19d1205 ZW |
6424 | po_reg_or_fail (REG_TYPE_RN); |
6425 | if (skip_past_char (&str, '!') == SUCCESS) | |
6426 | inst.operands[i].writeback = 1; | |
6427 | break; | |
6428 | ||
6429 | /* Immediates */ | |
6430 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6431 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6432 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
5287ad62 | 6433 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6434 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6435 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
5287ad62 | 6436 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6437 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
5287ad62 JB |
6438 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6439 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6440 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6441 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6442 | |
6443 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6444 | case OP_oI7b: | |
6445 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6446 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6447 | case OP_oI31b: | |
6448 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
5287ad62 | 6449 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
c19d1205 ZW |
6450 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6451 | ||
6452 | /* Immediate variants */ | |
6453 | case OP_oI255c: | |
6454 | po_char_or_fail ('{'); | |
6455 | po_imm_or_fail (0, 255, TRUE); | |
6456 | po_char_or_fail ('}'); | |
6457 | break; | |
6458 | ||
6459 | case OP_I31w: | |
6460 | /* The expression parser chokes on a trailing !, so we have | |
6461 | to find it first and zap it. */ | |
6462 | { | |
6463 | char *s = str; | |
6464 | while (*s && *s != ',') | |
6465 | s++; | |
6466 | if (s[-1] == '!') | |
6467 | { | |
6468 | s[-1] = '\0'; | |
6469 | inst.operands[i].writeback = 1; | |
6470 | } | |
6471 | po_imm_or_fail (0, 31, TRUE); | |
6472 | if (str == s - 1) | |
6473 | str = s; | |
6474 | } | |
6475 | break; | |
6476 | ||
6477 | /* Expressions */ | |
6478 | case OP_EXPi: EXPi: | |
6479 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6480 | GE_OPT_PREFIX)); | |
6481 | break; | |
6482 | ||
6483 | case OP_EXP: | |
6484 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6485 | GE_NO_PREFIX)); | |
6486 | break; | |
6487 | ||
6488 | case OP_EXPr: EXPr: | |
6489 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6490 | GE_NO_PREFIX)); | |
6491 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6492 | { |
c19d1205 ZW |
6493 | val = parse_reloc (&str); |
6494 | if (val == -1) | |
6495 | { | |
6496 | inst.error = _("unrecognized relocation suffix"); | |
6497 | goto failure; | |
6498 | } | |
6499 | else if (val != BFD_RELOC_UNUSED) | |
6500 | { | |
6501 | inst.operands[i].imm = val; | |
6502 | inst.operands[i].hasreloc = 1; | |
6503 | } | |
a737bd4d | 6504 | } |
c19d1205 | 6505 | break; |
a737bd4d | 6506 | |
b6895b4f PB |
6507 | /* Operand for MOVW or MOVT. */ |
6508 | case OP_HALF: | |
6509 | po_misc_or_fail (parse_half (&str)); | |
6510 | break; | |
6511 | ||
e07e6e58 | 6512 | /* Register or expression. */ |
c19d1205 ZW |
6513 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6514 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6515 | |
e07e6e58 | 6516 | /* Register or immediate. */ |
c19d1205 ZW |
6517 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6518 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6519 | |
c19d1205 ZW |
6520 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6521 | IF: | |
6522 | if (!is_immediate_prefix (*str)) | |
6523 | goto bad_args; | |
6524 | str++; | |
6525 | val = parse_fpa_immediate (&str); | |
6526 | if (val == FAIL) | |
6527 | goto failure; | |
6528 | /* FPA immediates are encoded as registers 8-15. | |
6529 | parse_fpa_immediate has already applied the offset. */ | |
6530 | inst.operands[i].reg = val; | |
6531 | inst.operands[i].isreg = 1; | |
6532 | break; | |
09d92015 | 6533 | |
2d447fca JM |
6534 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6535 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6536 | ||
e07e6e58 | 6537 | /* Two kinds of register. */ |
c19d1205 ZW |
6538 | case OP_RIWR_RIWC: |
6539 | { | |
6540 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6541 | if (!rege |
6542 | || (rege->type != REG_TYPE_MMXWR | |
6543 | && rege->type != REG_TYPE_MMXWC | |
6544 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6545 | { |
6546 | inst.error = _("iWMMXt data or control register expected"); | |
6547 | goto failure; | |
6548 | } | |
6549 | inst.operands[i].reg = rege->number; | |
6550 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6551 | } | |
6552 | break; | |
09d92015 | 6553 | |
41adaa5c JM |
6554 | case OP_RIWC_RIWG: |
6555 | { | |
6556 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6557 | if (!rege | |
6558 | || (rege->type != REG_TYPE_MMXWC | |
6559 | && rege->type != REG_TYPE_MMXWCG)) | |
6560 | { | |
6561 | inst.error = _("iWMMXt control register expected"); | |
6562 | goto failure; | |
6563 | } | |
6564 | inst.operands[i].reg = rege->number; | |
6565 | inst.operands[i].isreg = 1; | |
6566 | } | |
6567 | break; | |
6568 | ||
c19d1205 ZW |
6569 | /* Misc */ |
6570 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6571 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6572 | case OP_oROR: val = parse_ror (&str); break; | |
c19d1205 | 6573 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
6574 | case OP_oBARRIER_I15: |
6575 | po_barrier_or_imm (str); break; | |
6576 | immediate: | |
6577 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
6578 | goto failure; | |
6579 | break; | |
c19d1205 | 6580 | |
d2cd1205 JB |
6581 | case OP_wPSR: |
6582 | case OP_rPSR: | |
90ec0d68 MGD |
6583 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
6584 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
6585 | { | |
6586 | inst.error = _("Banked registers are not available with this " | |
6587 | "architecture."); | |
6588 | goto failure; | |
6589 | } | |
6590 | break; | |
d2cd1205 JB |
6591 | try_psr: |
6592 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
6593 | break; | |
037e8744 JB |
6594 | |
6595 | case OP_APSR_RR: | |
6596 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6597 | break; | |
6598 | try_apsr: | |
6599 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
6600 | instruction). */ | |
6601 | if (strncasecmp (str, "APSR_", 5) == 0) | |
6602 | { | |
6603 | unsigned found = 0; | |
6604 | str += 5; | |
6605 | while (found < 15) | |
6606 | switch (*str++) | |
6607 | { | |
6608 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
6609 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
6610 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
6611 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
6612 | default: found = 16; | |
6613 | } | |
6614 | if (found != 15) | |
6615 | goto failure; | |
6616 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
6617 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
6618 | inst.operands[i].reg = REG_PC; | |
037e8744 JB |
6619 | } |
6620 | else | |
6621 | goto failure; | |
6622 | break; | |
6623 | ||
92e90b6e PB |
6624 | case OP_TB: |
6625 | po_misc_or_fail (parse_tb (&str)); | |
6626 | break; | |
6627 | ||
e07e6e58 | 6628 | /* Register lists. */ |
c19d1205 ZW |
6629 | case OP_REGLST: |
6630 | val = parse_reg_list (&str); | |
6631 | if (*str == '^') | |
6632 | { | |
6633 | inst.operands[1].writeback = 1; | |
6634 | str++; | |
6635 | } | |
6636 | break; | |
09d92015 | 6637 | |
c19d1205 | 6638 | case OP_VRSLST: |
5287ad62 | 6639 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 6640 | break; |
09d92015 | 6641 | |
c19d1205 | 6642 | case OP_VRDLST: |
5287ad62 | 6643 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 6644 | break; |
a737bd4d | 6645 | |
037e8744 JB |
6646 | case OP_VRSDLST: |
6647 | /* Allow Q registers too. */ | |
6648 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6649 | REGLIST_NEON_D); | |
6650 | if (val == FAIL) | |
6651 | { | |
6652 | inst.error = NULL; | |
6653 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6654 | REGLIST_VFP_S); | |
6655 | inst.operands[i].issingle = 1; | |
6656 | } | |
6657 | break; | |
6658 | ||
5287ad62 JB |
6659 | case OP_NRDLST: |
6660 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6661 | REGLIST_NEON_D); | |
6662 | break; | |
6663 | ||
6664 | case OP_NSTRLST: | |
dcbf9037 JB |
6665 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
6666 | &inst.operands[i].vectype); | |
5287ad62 JB |
6667 | break; |
6668 | ||
c19d1205 ZW |
6669 | /* Addressing modes */ |
6670 | case OP_ADDR: | |
6671 | po_misc_or_fail (parse_address (&str, i)); | |
6672 | break; | |
09d92015 | 6673 | |
4962c51a MS |
6674 | case OP_ADDRGLDR: |
6675 | po_misc_or_fail_no_backtrack ( | |
6676 | parse_address_group_reloc (&str, i, GROUP_LDR)); | |
6677 | break; | |
6678 | ||
6679 | case OP_ADDRGLDRS: | |
6680 | po_misc_or_fail_no_backtrack ( | |
6681 | parse_address_group_reloc (&str, i, GROUP_LDRS)); | |
6682 | break; | |
6683 | ||
6684 | case OP_ADDRGLDC: | |
6685 | po_misc_or_fail_no_backtrack ( | |
6686 | parse_address_group_reloc (&str, i, GROUP_LDC)); | |
6687 | break; | |
6688 | ||
c19d1205 ZW |
6689 | case OP_SH: |
6690 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
6691 | break; | |
09d92015 | 6692 | |
4962c51a MS |
6693 | case OP_SHG: |
6694 | po_misc_or_fail_no_backtrack ( | |
6695 | parse_shifter_operand_group_reloc (&str, i)); | |
6696 | break; | |
6697 | ||
c19d1205 ZW |
6698 | case OP_oSHll: |
6699 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
6700 | break; | |
09d92015 | 6701 | |
c19d1205 ZW |
6702 | case OP_oSHar: |
6703 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
6704 | break; | |
09d92015 | 6705 | |
c19d1205 ZW |
6706 | case OP_oSHllar: |
6707 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
6708 | break; | |
09d92015 | 6709 | |
c19d1205 | 6710 | default: |
5be8be5d | 6711 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 6712 | } |
09d92015 | 6713 | |
c19d1205 ZW |
6714 | /* Various value-based sanity checks and shared operations. We |
6715 | do not signal immediate failures for the register constraints; | |
6716 | this allows a syntax error to take precedence. */ | |
5be8be5d | 6717 | switch (op_parse_code) |
c19d1205 ZW |
6718 | { |
6719 | case OP_oRRnpc: | |
6720 | case OP_RRnpc: | |
6721 | case OP_RRnpcb: | |
6722 | case OP_RRw: | |
b6702015 | 6723 | case OP_oRRw: |
c19d1205 ZW |
6724 | case OP_RRnpc_I0: |
6725 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
6726 | inst.error = BAD_PC; | |
6727 | break; | |
09d92015 | 6728 | |
5be8be5d DG |
6729 | case OP_oRRnpcsp: |
6730 | case OP_RRnpcsp: | |
6731 | if (inst.operands[i].isreg) | |
6732 | { | |
6733 | if (inst.operands[i].reg == REG_PC) | |
6734 | inst.error = BAD_PC; | |
6735 | else if (inst.operands[i].reg == REG_SP) | |
6736 | inst.error = BAD_SP; | |
6737 | } | |
6738 | break; | |
6739 | ||
55881a11 MGD |
6740 | case OP_RRnpctw: |
6741 | if (inst.operands[i].isreg | |
6742 | && inst.operands[i].reg == REG_PC | |
6743 | && (inst.operands[i].writeback || thumb)) | |
6744 | inst.error = BAD_PC; | |
6745 | break; | |
6746 | ||
c19d1205 ZW |
6747 | case OP_CPSF: |
6748 | case OP_ENDI: | |
6749 | case OP_oROR: | |
d2cd1205 JB |
6750 | case OP_wPSR: |
6751 | case OP_rPSR: | |
c19d1205 | 6752 | case OP_COND: |
52e7f43d | 6753 | case OP_oBARRIER_I15: |
c19d1205 ZW |
6754 | case OP_REGLST: |
6755 | case OP_VRSLST: | |
6756 | case OP_VRDLST: | |
037e8744 | 6757 | case OP_VRSDLST: |
5287ad62 JB |
6758 | case OP_NRDLST: |
6759 | case OP_NSTRLST: | |
c19d1205 ZW |
6760 | if (val == FAIL) |
6761 | goto failure; | |
6762 | inst.operands[i].imm = val; | |
6763 | break; | |
a737bd4d | 6764 | |
c19d1205 ZW |
6765 | default: |
6766 | break; | |
6767 | } | |
09d92015 | 6768 | |
c19d1205 ZW |
6769 | /* If we get here, this operand was successfully parsed. */ |
6770 | inst.operands[i].present = 1; | |
6771 | continue; | |
09d92015 | 6772 | |
c19d1205 | 6773 | bad_args: |
09d92015 | 6774 | inst.error = BAD_ARGS; |
c19d1205 ZW |
6775 | |
6776 | failure: | |
6777 | if (!backtrack_pos) | |
d252fdde PB |
6778 | { |
6779 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 6780 | default here just in case. */ |
d252fdde PB |
6781 | if (!inst.error) |
6782 | inst.error = _("syntax error"); | |
6783 | return FAIL; | |
6784 | } | |
c19d1205 ZW |
6785 | |
6786 | /* Do not backtrack over a trailing optional argument that | |
6787 | absorbed some text. We will only fail again, with the | |
6788 | 'garbage following instruction' error message, which is | |
6789 | probably less helpful than the current one. */ | |
6790 | if (backtrack_index == i && backtrack_pos != str | |
6791 | && upat[i+1] == OP_stop) | |
d252fdde PB |
6792 | { |
6793 | if (!inst.error) | |
6794 | inst.error = _("syntax error"); | |
6795 | return FAIL; | |
6796 | } | |
c19d1205 ZW |
6797 | |
6798 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
6799 | str = backtrack_pos; | |
6800 | inst.error = backtrack_error; | |
6801 | inst.operands[backtrack_index].present = 0; | |
6802 | i = backtrack_index; | |
6803 | backtrack_pos = 0; | |
09d92015 | 6804 | } |
09d92015 | 6805 | |
c19d1205 ZW |
6806 | /* Check that we have parsed all the arguments. */ |
6807 | if (*str != '\0' && !inst.error) | |
6808 | inst.error = _("garbage following instruction"); | |
09d92015 | 6809 | |
c19d1205 | 6810 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
6811 | } |
6812 | ||
c19d1205 ZW |
6813 | #undef po_char_or_fail |
6814 | #undef po_reg_or_fail | |
6815 | #undef po_reg_or_goto | |
6816 | #undef po_imm_or_fail | |
5287ad62 | 6817 | #undef po_scalar_or_fail |
52e7f43d | 6818 | #undef po_barrier_or_imm |
e07e6e58 | 6819 | |
c19d1205 | 6820 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
6821 | #define constraint(expr, err) \ |
6822 | do \ | |
c19d1205 | 6823 | { \ |
e07e6e58 NC |
6824 | if (expr) \ |
6825 | { \ | |
6826 | inst.error = err; \ | |
6827 | return; \ | |
6828 | } \ | |
c19d1205 | 6829 | } \ |
e07e6e58 | 6830 | while (0) |
c19d1205 | 6831 | |
fdfde340 JM |
6832 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
6833 | instructions are unpredictable if these registers are used. This | |
6834 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
6835 | #define reject_bad_reg(reg) \ | |
6836 | do \ | |
6837 | if (reg == REG_SP || reg == REG_PC) \ | |
6838 | { \ | |
6839 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
6840 | return; \ | |
6841 | } \ | |
6842 | while (0) | |
6843 | ||
94206790 MM |
6844 | /* If REG is R13 (the stack pointer), warn that its use is |
6845 | deprecated. */ | |
6846 | #define warn_deprecated_sp(reg) \ | |
6847 | do \ | |
6848 | if (warn_on_deprecated && reg == REG_SP) \ | |
6849 | as_warn (_("use of r13 is deprecated")); \ | |
6850 | while (0) | |
6851 | ||
c19d1205 ZW |
6852 | /* Functions for operand encoding. ARM, then Thumb. */ |
6853 | ||
6854 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
6855 | ||
6856 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
6857 | return the encoded form. Otherwise, return FAIL. */ | |
6858 | ||
6859 | static unsigned int | |
6860 | encode_arm_immediate (unsigned int val) | |
09d92015 | 6861 | { |
c19d1205 ZW |
6862 | unsigned int a, i; |
6863 | ||
6864 | for (i = 0; i < 32; i += 2) | |
6865 | if ((a = rotate_left (val, i)) <= 0xff) | |
6866 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
6867 | ||
6868 | return FAIL; | |
09d92015 MM |
6869 | } |
6870 | ||
c19d1205 ZW |
6871 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
6872 | return the encoded form. Otherwise, return FAIL. */ | |
6873 | static unsigned int | |
6874 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 6875 | { |
c19d1205 | 6876 | unsigned int a, i; |
09d92015 | 6877 | |
9c3c69f2 | 6878 | if (val <= 0xff) |
c19d1205 | 6879 | return val; |
a737bd4d | 6880 | |
9c3c69f2 | 6881 | for (i = 1; i <= 24; i++) |
09d92015 | 6882 | { |
9c3c69f2 PB |
6883 | a = val >> i; |
6884 | if ((val & ~(0xff << i)) == 0) | |
6885 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 6886 | } |
a737bd4d | 6887 | |
c19d1205 ZW |
6888 | a = val & 0xff; |
6889 | if (val == ((a << 16) | a)) | |
6890 | return 0x100 | a; | |
6891 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
6892 | return 0x300 | a; | |
09d92015 | 6893 | |
c19d1205 ZW |
6894 | a = val & 0xff00; |
6895 | if (val == ((a << 16) | a)) | |
6896 | return 0x200 | (a >> 8); | |
a737bd4d | 6897 | |
c19d1205 | 6898 | return FAIL; |
09d92015 | 6899 | } |
5287ad62 | 6900 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
6901 | |
6902 | static void | |
5287ad62 JB |
6903 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
6904 | { | |
6905 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
6906 | && reg > 15) | |
6907 | { | |
b1cc4aeb | 6908 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
5287ad62 JB |
6909 | { |
6910 | if (thumb_mode) | |
6911 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 6912 | fpu_vfp_ext_d32); |
5287ad62 JB |
6913 | else |
6914 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 6915 | fpu_vfp_ext_d32); |
5287ad62 JB |
6916 | } |
6917 | else | |
6918 | { | |
dcbf9037 | 6919 | first_error (_("D register out of range for selected VFP version")); |
5287ad62 JB |
6920 | return; |
6921 | } | |
6922 | } | |
6923 | ||
c19d1205 | 6924 | switch (pos) |
09d92015 | 6925 | { |
c19d1205 ZW |
6926 | case VFP_REG_Sd: |
6927 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
6928 | break; | |
6929 | ||
6930 | case VFP_REG_Sn: | |
6931 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
6932 | break; | |
6933 | ||
6934 | case VFP_REG_Sm: | |
6935 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
6936 | break; | |
6937 | ||
5287ad62 JB |
6938 | case VFP_REG_Dd: |
6939 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
6940 | break; | |
5f4273c7 | 6941 | |
5287ad62 JB |
6942 | case VFP_REG_Dn: |
6943 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
6944 | break; | |
5f4273c7 | 6945 | |
5287ad62 JB |
6946 | case VFP_REG_Dm: |
6947 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
6948 | break; | |
6949 | ||
c19d1205 ZW |
6950 | default: |
6951 | abort (); | |
09d92015 | 6952 | } |
09d92015 MM |
6953 | } |
6954 | ||
c19d1205 | 6955 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 6956 | if any, is handled by md_apply_fix. */ |
09d92015 | 6957 | static void |
c19d1205 | 6958 | encode_arm_shift (int i) |
09d92015 | 6959 | { |
c19d1205 ZW |
6960 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
6961 | inst.instruction |= SHIFT_ROR << 5; | |
6962 | else | |
09d92015 | 6963 | { |
c19d1205 ZW |
6964 | inst.instruction |= inst.operands[i].shift_kind << 5; |
6965 | if (inst.operands[i].immisreg) | |
6966 | { | |
6967 | inst.instruction |= SHIFT_BY_REG; | |
6968 | inst.instruction |= inst.operands[i].imm << 8; | |
6969 | } | |
6970 | else | |
6971 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 6972 | } |
c19d1205 | 6973 | } |
09d92015 | 6974 | |
c19d1205 ZW |
6975 | static void |
6976 | encode_arm_shifter_operand (int i) | |
6977 | { | |
6978 | if (inst.operands[i].isreg) | |
09d92015 | 6979 | { |
c19d1205 ZW |
6980 | inst.instruction |= inst.operands[i].reg; |
6981 | encode_arm_shift (i); | |
09d92015 | 6982 | } |
c19d1205 ZW |
6983 | else |
6984 | inst.instruction |= INST_IMMEDIATE; | |
09d92015 MM |
6985 | } |
6986 | ||
c19d1205 | 6987 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 6988 | static void |
c19d1205 | 6989 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 6990 | { |
9c2799c2 | 6991 | gas_assert (inst.operands[i].isreg); |
c19d1205 | 6992 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 6993 | |
c19d1205 | 6994 | if (inst.operands[i].preind) |
09d92015 | 6995 | { |
c19d1205 ZW |
6996 | if (is_t) |
6997 | { | |
6998 | inst.error = _("instruction does not accept preindexed addressing"); | |
6999 | return; | |
7000 | } | |
7001 | inst.instruction |= PRE_INDEX; | |
7002 | if (inst.operands[i].writeback) | |
7003 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7004 | |
c19d1205 ZW |
7005 | } |
7006 | else if (inst.operands[i].postind) | |
7007 | { | |
9c2799c2 | 7008 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
7009 | if (is_t) |
7010 | inst.instruction |= WRITE_BACK; | |
7011 | } | |
7012 | else /* unindexed - only for coprocessor */ | |
09d92015 | 7013 | { |
c19d1205 | 7014 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
7015 | return; |
7016 | } | |
7017 | ||
c19d1205 ZW |
7018 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
7019 | && (((inst.instruction & 0x000f0000) >> 16) | |
7020 | == ((inst.instruction & 0x0000f000) >> 12))) | |
7021 | as_warn ((inst.instruction & LOAD_BIT) | |
7022 | ? _("destination register same as write-back base") | |
7023 | : _("source register same as write-back base")); | |
09d92015 MM |
7024 | } |
7025 | ||
c19d1205 ZW |
7026 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7027 | ARM-format mode 2 load or store instruction. If is_t is true, | |
7028 | reject forms that cannot be used with a T instruction (i.e. not | |
7029 | post-indexed). */ | |
a737bd4d | 7030 | static void |
c19d1205 | 7031 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 7032 | { |
5be8be5d DG |
7033 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
7034 | ||
c19d1205 | 7035 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7036 | |
c19d1205 | 7037 | if (inst.operands[i].immisreg) |
09d92015 | 7038 | { |
5be8be5d DG |
7039 | constraint ((inst.operands[i].imm == REG_PC |
7040 | || (is_pc && inst.operands[i].writeback)), | |
7041 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7042 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
7043 | inst.instruction |= inst.operands[i].imm; | |
7044 | if (!inst.operands[i].negative) | |
7045 | inst.instruction |= INDEX_UP; | |
7046 | if (inst.operands[i].shifted) | |
7047 | { | |
7048 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
7049 | inst.instruction |= SHIFT_ROR << 5; | |
7050 | else | |
7051 | { | |
7052 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
7053 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
7054 | } | |
7055 | } | |
09d92015 | 7056 | } |
c19d1205 | 7057 | else /* immediate offset in inst.reloc */ |
09d92015 | 7058 | { |
5be8be5d DG |
7059 | if (is_pc && !inst.reloc.pc_rel) |
7060 | { | |
7061 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
7062 | |
7063 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
7064 | cannot use PC in addressing. | |
7065 | PC cannot be used in writeback addressing, either. */ | |
7066 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 7067 | BAD_PC_ADDRESSING); |
23a10334 | 7068 | |
dc5ec521 | 7069 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
7070 | if (warn_on_deprecated |
7071 | && !is_load | |
7072 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
7073 | as_warn (_("use of PC in this instruction is deprecated")); | |
5be8be5d DG |
7074 | } |
7075 | ||
c19d1205 | 7076 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
26d97720 NS |
7077 | { |
7078 | /* Prefer + for zero encoded value. */ | |
7079 | if (!inst.operands[i].negative) | |
7080 | inst.instruction |= INDEX_UP; | |
7081 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
7082 | } | |
09d92015 | 7083 | } |
09d92015 MM |
7084 | } |
7085 | ||
c19d1205 ZW |
7086 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7087 | ARM-format mode 3 load or store instruction. Reject forms that | |
7088 | cannot be used with such instructions. If is_t is true, reject | |
7089 | forms that cannot be used with a T instruction (i.e. not | |
7090 | post-indexed). */ | |
7091 | static void | |
7092 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 7093 | { |
c19d1205 | 7094 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 7095 | { |
c19d1205 ZW |
7096 | inst.error = _("instruction does not accept scaled register index"); |
7097 | return; | |
09d92015 | 7098 | } |
a737bd4d | 7099 | |
c19d1205 | 7100 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7101 | |
c19d1205 ZW |
7102 | if (inst.operands[i].immisreg) |
7103 | { | |
5be8be5d DG |
7104 | constraint ((inst.operands[i].imm == REG_PC |
7105 | || inst.operands[i].reg == REG_PC), | |
7106 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7107 | inst.instruction |= inst.operands[i].imm; |
7108 | if (!inst.operands[i].negative) | |
7109 | inst.instruction |= INDEX_UP; | |
7110 | } | |
7111 | else /* immediate offset in inst.reloc */ | |
7112 | { | |
5be8be5d DG |
7113 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
7114 | && inst.operands[i].writeback), | |
7115 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7116 | inst.instruction |= HWOFFSET_IMM; |
7117 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
26d97720 NS |
7118 | { |
7119 | /* Prefer + for zero encoded value. */ | |
7120 | if (!inst.operands[i].negative) | |
7121 | inst.instruction |= INDEX_UP; | |
7122 | ||
7123 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
7124 | } | |
c19d1205 | 7125 | } |
a737bd4d NC |
7126 | } |
7127 | ||
c19d1205 ZW |
7128 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7129 | ARM-format instruction. Reject all forms which cannot be encoded | |
7130 | into a coprocessor load/store instruction. If wb_ok is false, | |
7131 | reject use of writeback; if unind_ok is false, reject use of | |
7132 | unindexed addressing. If reloc_override is not 0, use it instead | |
4962c51a MS |
7133 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
7134 | (in which case it is preserved). */ | |
09d92015 | 7135 | |
c19d1205 ZW |
7136 | static int |
7137 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 7138 | { |
c19d1205 | 7139 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7140 | |
9c2799c2 | 7141 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 7142 | |
c19d1205 | 7143 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 7144 | { |
9c2799c2 | 7145 | gas_assert (!inst.operands[i].writeback); |
c19d1205 ZW |
7146 | if (!unind_ok) |
7147 | { | |
7148 | inst.error = _("instruction does not support unindexed addressing"); | |
7149 | return FAIL; | |
7150 | } | |
7151 | inst.instruction |= inst.operands[i].imm; | |
7152 | inst.instruction |= INDEX_UP; | |
7153 | return SUCCESS; | |
09d92015 | 7154 | } |
a737bd4d | 7155 | |
c19d1205 ZW |
7156 | if (inst.operands[i].preind) |
7157 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 7158 | |
c19d1205 | 7159 | if (inst.operands[i].writeback) |
09d92015 | 7160 | { |
c19d1205 ZW |
7161 | if (inst.operands[i].reg == REG_PC) |
7162 | { | |
7163 | inst.error = _("pc may not be used with write-back"); | |
7164 | return FAIL; | |
7165 | } | |
7166 | if (!wb_ok) | |
7167 | { | |
7168 | inst.error = _("instruction does not support writeback"); | |
7169 | return FAIL; | |
7170 | } | |
7171 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7172 | } |
a737bd4d | 7173 | |
c19d1205 | 7174 | if (reloc_override) |
21d799b5 | 7175 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; |
4962c51a MS |
7176 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC |
7177 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
7178 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
7179 | { | |
7180 | if (thumb_mode) | |
7181 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
7182 | else | |
7183 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
7184 | } | |
7185 | ||
26d97720 NS |
7186 | /* Prefer + for zero encoded value. */ |
7187 | if (!inst.operands[i].negative) | |
7188 | inst.instruction |= INDEX_UP; | |
7189 | ||
c19d1205 ZW |
7190 | return SUCCESS; |
7191 | } | |
a737bd4d | 7192 | |
c19d1205 ZW |
7193 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
7194 | Determine whether it can be performed with a move instruction; if | |
7195 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
7196 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
7197 | load and return FALSE. If this is not a valid thing to do in the | |
7198 | current context, set inst.error and return TRUE. | |
a737bd4d | 7199 | |
c19d1205 ZW |
7200 | inst.operands[i] describes the destination register. */ |
7201 | ||
c921be7d | 7202 | static bfd_boolean |
c19d1205 ZW |
7203 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) |
7204 | { | |
53365c0d PB |
7205 | unsigned long tbit; |
7206 | ||
7207 | if (thumb_p) | |
7208 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
7209 | else | |
7210 | tbit = LOAD_BIT; | |
7211 | ||
7212 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 7213 | { |
c19d1205 | 7214 | inst.error = _("invalid pseudo operation"); |
c921be7d | 7215 | return TRUE; |
09d92015 | 7216 | } |
c19d1205 | 7217 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
7218 | { |
7219 | inst.error = _("constant expression expected"); | |
c921be7d | 7220 | return TRUE; |
09d92015 | 7221 | } |
c19d1205 | 7222 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 7223 | { |
c19d1205 ZW |
7224 | if (thumb_p) |
7225 | { | |
53365c0d | 7226 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
7227 | { |
7228 | /* This can be done with a mov(1) instruction. */ | |
7229 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
7230 | inst.instruction |= inst.reloc.exp.X_add_number; | |
c921be7d | 7231 | return TRUE; |
c19d1205 ZW |
7232 | } |
7233 | } | |
7234 | else | |
7235 | { | |
7236 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
7237 | if (value != FAIL) | |
7238 | { | |
7239 | /* This can be done with a mov instruction. */ | |
7240 | inst.instruction &= LITERAL_MASK; | |
7241 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
7242 | inst.instruction |= value & 0xfff; | |
c921be7d | 7243 | return TRUE; |
c19d1205 | 7244 | } |
09d92015 | 7245 | |
c19d1205 ZW |
7246 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
7247 | if (value != FAIL) | |
7248 | { | |
7249 | /* This can be done with a mvn instruction. */ | |
7250 | inst.instruction &= LITERAL_MASK; | |
7251 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
7252 | inst.instruction |= value & 0xfff; | |
c921be7d | 7253 | return TRUE; |
c19d1205 ZW |
7254 | } |
7255 | } | |
09d92015 MM |
7256 | } |
7257 | ||
c19d1205 ZW |
7258 | if (add_to_lit_pool () == FAIL) |
7259 | { | |
7260 | inst.error = _("literal pool insertion failed"); | |
c921be7d | 7261 | return TRUE; |
c19d1205 ZW |
7262 | } |
7263 | inst.operands[1].reg = REG_PC; | |
7264 | inst.operands[1].isreg = 1; | |
7265 | inst.operands[1].preind = 1; | |
7266 | inst.reloc.pc_rel = 1; | |
7267 | inst.reloc.type = (thumb_p | |
7268 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
7269 | : (mode_3 | |
7270 | ? BFD_RELOC_ARM_HWLITERAL | |
7271 | : BFD_RELOC_ARM_LITERAL)); | |
c921be7d | 7272 | return FALSE; |
09d92015 MM |
7273 | } |
7274 | ||
5f4273c7 | 7275 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
7276 | First some generics; their names are taken from the conventional |
7277 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 7278 | |
a737bd4d | 7279 | static void |
c19d1205 | 7280 | do_noargs (void) |
09d92015 | 7281 | { |
c19d1205 | 7282 | } |
a737bd4d | 7283 | |
c19d1205 ZW |
7284 | static void |
7285 | do_rd (void) | |
7286 | { | |
7287 | inst.instruction |= inst.operands[0].reg << 12; | |
7288 | } | |
a737bd4d | 7289 | |
c19d1205 ZW |
7290 | static void |
7291 | do_rd_rm (void) | |
7292 | { | |
7293 | inst.instruction |= inst.operands[0].reg << 12; | |
7294 | inst.instruction |= inst.operands[1].reg; | |
7295 | } | |
09d92015 | 7296 | |
c19d1205 ZW |
7297 | static void |
7298 | do_rd_rn (void) | |
7299 | { | |
7300 | inst.instruction |= inst.operands[0].reg << 12; | |
7301 | inst.instruction |= inst.operands[1].reg << 16; | |
7302 | } | |
a737bd4d | 7303 | |
c19d1205 ZW |
7304 | static void |
7305 | do_rn_rd (void) | |
7306 | { | |
7307 | inst.instruction |= inst.operands[0].reg << 16; | |
7308 | inst.instruction |= inst.operands[1].reg << 12; | |
7309 | } | |
09d92015 | 7310 | |
c19d1205 ZW |
7311 | static void |
7312 | do_rd_rm_rn (void) | |
7313 | { | |
9a64e435 | 7314 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 7315 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 7316 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
7317 | { |
7318 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
7319 | _("Rn must not overlap other operands")); | |
7320 | ||
7321 | /* SWP{b} is deprecated for ARMv6* and ARMv7. */ | |
7322 | if (warn_on_deprecated | |
7323 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
7324 | as_warn (_("swp{b} use is deprecated for this architecture")); | |
7325 | ||
7326 | } | |
c19d1205 ZW |
7327 | inst.instruction |= inst.operands[0].reg << 12; |
7328 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 7329 | inst.instruction |= Rn << 16; |
c19d1205 | 7330 | } |
09d92015 | 7331 | |
c19d1205 ZW |
7332 | static void |
7333 | do_rd_rn_rm (void) | |
7334 | { | |
7335 | inst.instruction |= inst.operands[0].reg << 12; | |
7336 | inst.instruction |= inst.operands[1].reg << 16; | |
7337 | inst.instruction |= inst.operands[2].reg; | |
7338 | } | |
a737bd4d | 7339 | |
c19d1205 ZW |
7340 | static void |
7341 | do_rm_rd_rn (void) | |
7342 | { | |
5be8be5d DG |
7343 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
7344 | constraint (((inst.reloc.exp.X_op != O_constant | |
7345 | && inst.reloc.exp.X_op != O_illegal) | |
7346 | || inst.reloc.exp.X_add_number != 0), | |
7347 | BAD_ADDR_MODE); | |
c19d1205 ZW |
7348 | inst.instruction |= inst.operands[0].reg; |
7349 | inst.instruction |= inst.operands[1].reg << 12; | |
7350 | inst.instruction |= inst.operands[2].reg << 16; | |
7351 | } | |
09d92015 | 7352 | |
c19d1205 ZW |
7353 | static void |
7354 | do_imm0 (void) | |
7355 | { | |
7356 | inst.instruction |= inst.operands[0].imm; | |
7357 | } | |
09d92015 | 7358 | |
c19d1205 ZW |
7359 | static void |
7360 | do_rd_cpaddr (void) | |
7361 | { | |
7362 | inst.instruction |= inst.operands[0].reg << 12; | |
7363 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 7364 | } |
a737bd4d | 7365 | |
c19d1205 ZW |
7366 | /* ARM instructions, in alphabetical order by function name (except |
7367 | that wrapper functions appear immediately after the function they | |
7368 | wrap). */ | |
09d92015 | 7369 | |
c19d1205 ZW |
7370 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
7371 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
7372 | |
7373 | static void | |
c19d1205 | 7374 | do_adr (void) |
09d92015 | 7375 | { |
c19d1205 | 7376 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 7377 | |
c19d1205 ZW |
7378 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7379 | out to be negative. */ | |
7380 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 7381 | inst.reloc.pc_rel = 1; |
2fc8bdac | 7382 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 7383 | } |
b99bd4ef | 7384 | |
c19d1205 ZW |
7385 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
7386 | into a relative address of the form: | |
7387 | add rd, pc, #low(label-.-8)" | |
7388 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 7389 | |
c19d1205 ZW |
7390 | static void |
7391 | do_adrl (void) | |
7392 | { | |
7393 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 7394 | |
c19d1205 ZW |
7395 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7396 | out to be negative. */ | |
7397 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
7398 | inst.reloc.pc_rel = 1; |
7399 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 7400 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
7401 | } |
7402 | ||
b99bd4ef | 7403 | static void |
c19d1205 | 7404 | do_arit (void) |
b99bd4ef | 7405 | { |
c19d1205 ZW |
7406 | if (!inst.operands[1].present) |
7407 | inst.operands[1].reg = inst.operands[0].reg; | |
7408 | inst.instruction |= inst.operands[0].reg << 12; | |
7409 | inst.instruction |= inst.operands[1].reg << 16; | |
7410 | encode_arm_shifter_operand (2); | |
7411 | } | |
b99bd4ef | 7412 | |
62b3e311 PB |
7413 | static void |
7414 | do_barrier (void) | |
7415 | { | |
7416 | if (inst.operands[0].present) | |
7417 | { | |
7418 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
7419 | && inst.operands[0].imm > 0xf |
7420 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 7421 | _("bad barrier type")); |
62b3e311 PB |
7422 | inst.instruction |= inst.operands[0].imm; |
7423 | } | |
7424 | else | |
7425 | inst.instruction |= 0xf; | |
7426 | } | |
7427 | ||
c19d1205 ZW |
7428 | static void |
7429 | do_bfc (void) | |
7430 | { | |
7431 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
7432 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7433 | /* The instruction encoding stores the LSB and MSB, | |
7434 | not the LSB and width. */ | |
7435 | inst.instruction |= inst.operands[0].reg << 12; | |
7436 | inst.instruction |= inst.operands[1].imm << 7; | |
7437 | inst.instruction |= (msb - 1) << 16; | |
7438 | } | |
b99bd4ef | 7439 | |
c19d1205 ZW |
7440 | static void |
7441 | do_bfi (void) | |
7442 | { | |
7443 | unsigned int msb; | |
b99bd4ef | 7444 | |
c19d1205 ZW |
7445 | /* #0 in second position is alternative syntax for bfc, which is |
7446 | the same instruction but with REG_PC in the Rm field. */ | |
7447 | if (!inst.operands[1].isreg) | |
7448 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 7449 | |
c19d1205 ZW |
7450 | msb = inst.operands[2].imm + inst.operands[3].imm; |
7451 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7452 | /* The instruction encoding stores the LSB and MSB, | |
7453 | not the LSB and width. */ | |
7454 | inst.instruction |= inst.operands[0].reg << 12; | |
7455 | inst.instruction |= inst.operands[1].reg; | |
7456 | inst.instruction |= inst.operands[2].imm << 7; | |
7457 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
7458 | } |
7459 | ||
b99bd4ef | 7460 | static void |
c19d1205 | 7461 | do_bfx (void) |
b99bd4ef | 7462 | { |
c19d1205 ZW |
7463 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
7464 | _("bit-field extends past end of register")); | |
7465 | inst.instruction |= inst.operands[0].reg << 12; | |
7466 | inst.instruction |= inst.operands[1].reg; | |
7467 | inst.instruction |= inst.operands[2].imm << 7; | |
7468 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
7469 | } | |
09d92015 | 7470 | |
c19d1205 ZW |
7471 | /* ARM V5 breakpoint instruction (argument parse) |
7472 | BKPT <16 bit unsigned immediate> | |
7473 | Instruction is not conditional. | |
7474 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
7475 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 7476 | |
c19d1205 ZW |
7477 | static void |
7478 | do_bkpt (void) | |
7479 | { | |
7480 | /* Top 12 of 16 bits to bits 19:8. */ | |
7481 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 7482 | |
c19d1205 ZW |
7483 | /* Bottom 4 of 16 bits to bits 3:0. */ |
7484 | inst.instruction |= inst.operands[0].imm & 0xf; | |
7485 | } | |
09d92015 | 7486 | |
c19d1205 ZW |
7487 | static void |
7488 | encode_branch (int default_reloc) | |
7489 | { | |
7490 | if (inst.operands[0].hasreloc) | |
7491 | { | |
0855e32b NS |
7492 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
7493 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
7494 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
7495 | inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 | |
7496 | ? BFD_RELOC_ARM_PLT32 | |
7497 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 7498 | } |
b99bd4ef | 7499 | else |
9ae92b05 | 7500 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
2fc8bdac | 7501 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
7502 | } |
7503 | ||
b99bd4ef | 7504 | static void |
c19d1205 | 7505 | do_branch (void) |
b99bd4ef | 7506 | { |
39b41c9c PB |
7507 | #ifdef OBJ_ELF |
7508 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7509 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7510 | else | |
7511 | #endif | |
7512 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
7513 | } | |
7514 | ||
7515 | static void | |
7516 | do_bl (void) | |
7517 | { | |
7518 | #ifdef OBJ_ELF | |
7519 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7520 | { | |
7521 | if (inst.cond == COND_ALWAYS) | |
7522 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
7523 | else | |
7524 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7525 | } | |
7526 | else | |
7527 | #endif | |
7528 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 7529 | } |
b99bd4ef | 7530 | |
c19d1205 ZW |
7531 | /* ARM V5 branch-link-exchange instruction (argument parse) |
7532 | BLX <target_addr> ie BLX(1) | |
7533 | BLX{<condition>} <Rm> ie BLX(2) | |
7534 | Unfortunately, there are two different opcodes for this mnemonic. | |
7535 | So, the insns[].value is not used, and the code here zaps values | |
7536 | into inst.instruction. | |
7537 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 7538 | |
c19d1205 ZW |
7539 | static void |
7540 | do_blx (void) | |
7541 | { | |
7542 | if (inst.operands[0].isreg) | |
b99bd4ef | 7543 | { |
c19d1205 ZW |
7544 | /* Arg is a register; the opcode provided by insns[] is correct. |
7545 | It is not illegal to do "blx pc", just useless. */ | |
7546 | if (inst.operands[0].reg == REG_PC) | |
7547 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 7548 | |
c19d1205 ZW |
7549 | inst.instruction |= inst.operands[0].reg; |
7550 | } | |
7551 | else | |
b99bd4ef | 7552 | { |
c19d1205 | 7553 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
7554 | conditionally, and the opcode must be adjusted. |
7555 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
7556 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 7557 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 7558 | inst.instruction = 0xfa000000; |
267bf995 | 7559 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 7560 | } |
c19d1205 ZW |
7561 | } |
7562 | ||
7563 | static void | |
7564 | do_bx (void) | |
7565 | { | |
845b51d6 PB |
7566 | bfd_boolean want_reloc; |
7567 | ||
c19d1205 ZW |
7568 | if (inst.operands[0].reg == REG_PC) |
7569 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 7570 | |
c19d1205 | 7571 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
7572 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
7573 | it is for ARMv4t or earlier. */ | |
7574 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
7575 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
7576 | want_reloc = TRUE; | |
7577 | ||
5ad34203 | 7578 | #ifdef OBJ_ELF |
845b51d6 | 7579 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 7580 | #endif |
584206db | 7581 | want_reloc = FALSE; |
845b51d6 PB |
7582 | |
7583 | if (want_reloc) | |
7584 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
7585 | } |
7586 | ||
c19d1205 ZW |
7587 | |
7588 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
7589 | |
7590 | static void | |
c19d1205 | 7591 | do_bxj (void) |
a737bd4d | 7592 | { |
c19d1205 ZW |
7593 | if (inst.operands[0].reg == REG_PC) |
7594 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
7595 | ||
7596 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
7597 | } |
7598 | ||
c19d1205 ZW |
7599 | /* Co-processor data operation: |
7600 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
7601 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
7602 | static void | |
7603 | do_cdp (void) | |
7604 | { | |
7605 | inst.instruction |= inst.operands[0].reg << 8; | |
7606 | inst.instruction |= inst.operands[1].imm << 20; | |
7607 | inst.instruction |= inst.operands[2].reg << 12; | |
7608 | inst.instruction |= inst.operands[3].reg << 16; | |
7609 | inst.instruction |= inst.operands[4].reg; | |
7610 | inst.instruction |= inst.operands[5].imm << 5; | |
7611 | } | |
a737bd4d NC |
7612 | |
7613 | static void | |
c19d1205 | 7614 | do_cmp (void) |
a737bd4d | 7615 | { |
c19d1205 ZW |
7616 | inst.instruction |= inst.operands[0].reg << 16; |
7617 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
7618 | } |
7619 | ||
c19d1205 ZW |
7620 | /* Transfer between coprocessor and ARM registers. |
7621 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
7622 | MRC2 | |
7623 | MCR{cond} | |
7624 | MCR2 | |
7625 | ||
7626 | No special properties. */ | |
09d92015 MM |
7627 | |
7628 | static void | |
c19d1205 | 7629 | do_co_reg (void) |
09d92015 | 7630 | { |
fdfde340 JM |
7631 | unsigned Rd; |
7632 | ||
7633 | Rd = inst.operands[2].reg; | |
7634 | if (thumb_mode) | |
7635 | { | |
7636 | if (inst.instruction == 0xee000010 | |
7637 | || inst.instruction == 0xfe000010) | |
7638 | /* MCR, MCR2 */ | |
7639 | reject_bad_reg (Rd); | |
7640 | else | |
7641 | /* MRC, MRC2 */ | |
7642 | constraint (Rd == REG_SP, BAD_SP); | |
7643 | } | |
7644 | else | |
7645 | { | |
7646 | /* MCR */ | |
7647 | if (inst.instruction == 0xe000010) | |
7648 | constraint (Rd == REG_PC, BAD_PC); | |
7649 | } | |
7650 | ||
7651 | ||
c19d1205 ZW |
7652 | inst.instruction |= inst.operands[0].reg << 8; |
7653 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 7654 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
7655 | inst.instruction |= inst.operands[3].reg << 16; |
7656 | inst.instruction |= inst.operands[4].reg; | |
7657 | inst.instruction |= inst.operands[5].imm << 5; | |
7658 | } | |
09d92015 | 7659 | |
c19d1205 ZW |
7660 | /* Transfer between coprocessor register and pair of ARM registers. |
7661 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
7662 | MCRR2 | |
7663 | MRRC{cond} | |
7664 | MRRC2 | |
b99bd4ef | 7665 | |
c19d1205 | 7666 | Two XScale instructions are special cases of these: |
09d92015 | 7667 | |
c19d1205 ZW |
7668 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
7669 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 7670 | |
5f4273c7 | 7671 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 7672 | |
c19d1205 ZW |
7673 | static void |
7674 | do_co_reg2c (void) | |
7675 | { | |
fdfde340 JM |
7676 | unsigned Rd, Rn; |
7677 | ||
7678 | Rd = inst.operands[2].reg; | |
7679 | Rn = inst.operands[3].reg; | |
7680 | ||
7681 | if (thumb_mode) | |
7682 | { | |
7683 | reject_bad_reg (Rd); | |
7684 | reject_bad_reg (Rn); | |
7685 | } | |
7686 | else | |
7687 | { | |
7688 | constraint (Rd == REG_PC, BAD_PC); | |
7689 | constraint (Rn == REG_PC, BAD_PC); | |
7690 | } | |
7691 | ||
c19d1205 ZW |
7692 | inst.instruction |= inst.operands[0].reg << 8; |
7693 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
7694 | inst.instruction |= Rd << 12; |
7695 | inst.instruction |= Rn << 16; | |
c19d1205 | 7696 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
7697 | } |
7698 | ||
c19d1205 ZW |
7699 | static void |
7700 | do_cpsi (void) | |
7701 | { | |
7702 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
7703 | if (inst.operands[1].present) |
7704 | { | |
7705 | inst.instruction |= CPSI_MMOD; | |
7706 | inst.instruction |= inst.operands[1].imm; | |
7707 | } | |
c19d1205 | 7708 | } |
b99bd4ef | 7709 | |
62b3e311 PB |
7710 | static void |
7711 | do_dbg (void) | |
7712 | { | |
7713 | inst.instruction |= inst.operands[0].imm; | |
7714 | } | |
7715 | ||
eea54501 MGD |
7716 | static void |
7717 | do_div (void) | |
7718 | { | |
7719 | unsigned Rd, Rn, Rm; | |
7720 | ||
7721 | Rd = inst.operands[0].reg; | |
7722 | Rn = (inst.operands[1].present | |
7723 | ? inst.operands[1].reg : Rd); | |
7724 | Rm = inst.operands[2].reg; | |
7725 | ||
7726 | constraint ((Rd == REG_PC), BAD_PC); | |
7727 | constraint ((Rn == REG_PC), BAD_PC); | |
7728 | constraint ((Rm == REG_PC), BAD_PC); | |
7729 | ||
7730 | inst.instruction |= Rd << 16; | |
7731 | inst.instruction |= Rn << 0; | |
7732 | inst.instruction |= Rm << 8; | |
7733 | } | |
7734 | ||
b99bd4ef | 7735 | static void |
c19d1205 | 7736 | do_it (void) |
b99bd4ef | 7737 | { |
c19d1205 | 7738 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
7739 | process it to do the validation as if in |
7740 | thumb mode, just in case the code gets | |
7741 | assembled for thumb using the unified syntax. */ | |
7742 | ||
c19d1205 | 7743 | inst.size = 0; |
e07e6e58 NC |
7744 | if (unified_syntax) |
7745 | { | |
7746 | set_it_insn_type (IT_INSN); | |
7747 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
7748 | now_it.cc = inst.operands[0].imm; | |
7749 | } | |
09d92015 | 7750 | } |
b99bd4ef | 7751 | |
09d92015 | 7752 | static void |
c19d1205 | 7753 | do_ldmstm (void) |
ea6ef066 | 7754 | { |
c19d1205 ZW |
7755 | int base_reg = inst.operands[0].reg; |
7756 | int range = inst.operands[1].imm; | |
ea6ef066 | 7757 | |
c19d1205 ZW |
7758 | inst.instruction |= base_reg << 16; |
7759 | inst.instruction |= range; | |
ea6ef066 | 7760 | |
c19d1205 ZW |
7761 | if (inst.operands[1].writeback) |
7762 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 7763 | |
c19d1205 | 7764 | if (inst.operands[0].writeback) |
ea6ef066 | 7765 | { |
c19d1205 ZW |
7766 | inst.instruction |= WRITE_BACK; |
7767 | /* Check for unpredictable uses of writeback. */ | |
7768 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 7769 | { |
c19d1205 ZW |
7770 | /* Not allowed in LDM type 2. */ |
7771 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
7772 | && ((range & (1 << REG_PC)) == 0)) | |
7773 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7774 | /* Only allowed if base reg not in list for other types. */ | |
7775 | else if (range & (1 << base_reg)) | |
7776 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
7777 | } | |
7778 | else /* STM. */ | |
7779 | { | |
7780 | /* Not allowed for type 2. */ | |
7781 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
7782 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7783 | /* Only allowed if base reg not in list, or first in list. */ | |
7784 | else if ((range & (1 << base_reg)) | |
7785 | && (range & ((1 << base_reg) - 1))) | |
7786 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 7787 | } |
ea6ef066 | 7788 | } |
a737bd4d NC |
7789 | } |
7790 | ||
c19d1205 ZW |
7791 | /* ARMv5TE load-consecutive (argument parse) |
7792 | Mode is like LDRH. | |
7793 | ||
7794 | LDRccD R, mode | |
7795 | STRccD R, mode. */ | |
7796 | ||
a737bd4d | 7797 | static void |
c19d1205 | 7798 | do_ldrd (void) |
a737bd4d | 7799 | { |
c19d1205 | 7800 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 7801 | _("first transfer register must be even")); |
c19d1205 ZW |
7802 | constraint (inst.operands[1].present |
7803 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 7804 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
7805 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
7806 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 7807 | |
c19d1205 ZW |
7808 | if (!inst.operands[1].present) |
7809 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 7810 | |
c56791bb RE |
7811 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
7812 | register and the first register written; we have to diagnose | |
7813 | overlap between the base and the second register written here. */ | |
ea6ef066 | 7814 | |
c56791bb RE |
7815 | if (inst.operands[2].reg == inst.operands[1].reg |
7816 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
7817 | as_warn (_("base register written back, and overlaps " | |
7818 | "second transfer register")); | |
b05fe5cf | 7819 | |
c56791bb RE |
7820 | if (!(inst.instruction & V4_STR_BIT)) |
7821 | { | |
c19d1205 | 7822 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
7823 | destination (even if not write-back). */ |
7824 | if (inst.operands[2].immisreg | |
7825 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
7826 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
7827 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 7828 | } |
c19d1205 ZW |
7829 | inst.instruction |= inst.operands[0].reg << 12; |
7830 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
7831 | } |
7832 | ||
7833 | static void | |
c19d1205 | 7834 | do_ldrex (void) |
b05fe5cf | 7835 | { |
c19d1205 ZW |
7836 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
7837 | || inst.operands[1].postind || inst.operands[1].writeback | |
7838 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
7839 | || inst.operands[1].negative |
7840 | /* This can arise if the programmer has written | |
7841 | strex rN, rM, foo | |
7842 | or if they have mistakenly used a register name as the last | |
7843 | operand, eg: | |
7844 | strex rN, rM, rX | |
7845 | It is very difficult to distinguish between these two cases | |
7846 | because "rX" might actually be a label. ie the register | |
7847 | name has been occluded by a symbol of the same name. So we | |
7848 | just generate a general 'bad addressing mode' type error | |
7849 | message and leave it up to the programmer to discover the | |
7850 | true cause and fix their mistake. */ | |
7851 | || (inst.operands[1].reg == REG_PC), | |
7852 | BAD_ADDR_MODE); | |
b05fe5cf | 7853 | |
c19d1205 ZW |
7854 | constraint (inst.reloc.exp.X_op != O_constant |
7855 | || inst.reloc.exp.X_add_number != 0, | |
7856 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 7857 | |
5be8be5d DG |
7858 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
7859 | ||
c19d1205 ZW |
7860 | inst.instruction |= inst.operands[0].reg << 12; |
7861 | inst.instruction |= inst.operands[1].reg << 16; | |
7862 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
7863 | } |
7864 | ||
7865 | static void | |
c19d1205 | 7866 | do_ldrexd (void) |
b05fe5cf | 7867 | { |
c19d1205 ZW |
7868 | constraint (inst.operands[0].reg % 2 != 0, |
7869 | _("even register required")); | |
7870 | constraint (inst.operands[1].present | |
7871 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7872 | _("can only load two consecutive registers")); | |
7873 | /* If op 1 were present and equal to PC, this function wouldn't | |
7874 | have been called in the first place. */ | |
7875 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 7876 | |
c19d1205 ZW |
7877 | inst.instruction |= inst.operands[0].reg << 12; |
7878 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
7879 | } |
7880 | ||
7881 | static void | |
c19d1205 | 7882 | do_ldst (void) |
b05fe5cf | 7883 | { |
c19d1205 ZW |
7884 | inst.instruction |= inst.operands[0].reg << 12; |
7885 | if (!inst.operands[1].isreg) | |
7886 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 7887 | return; |
c19d1205 | 7888 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7889 | } |
7890 | ||
7891 | static void | |
c19d1205 | 7892 | do_ldstt (void) |
b05fe5cf | 7893 | { |
c19d1205 ZW |
7894 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7895 | reject [Rn,...]. */ | |
7896 | if (inst.operands[1].preind) | |
b05fe5cf | 7897 | { |
bd3ba5d1 NC |
7898 | constraint (inst.reloc.exp.X_op != O_constant |
7899 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7900 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7901 | |
c19d1205 ZW |
7902 | inst.operands[1].preind = 0; |
7903 | inst.operands[1].postind = 1; | |
7904 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7905 | } |
c19d1205 ZW |
7906 | inst.instruction |= inst.operands[0].reg << 12; |
7907 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
7908 | } | |
b05fe5cf | 7909 | |
c19d1205 | 7910 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 7911 | |
c19d1205 ZW |
7912 | static void |
7913 | do_ldstv4 (void) | |
7914 | { | |
ff4a8d2b | 7915 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
7916 | inst.instruction |= inst.operands[0].reg << 12; |
7917 | if (!inst.operands[1].isreg) | |
7918 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 7919 | return; |
c19d1205 | 7920 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7921 | } |
7922 | ||
7923 | static void | |
c19d1205 | 7924 | do_ldsttv4 (void) |
b05fe5cf | 7925 | { |
c19d1205 ZW |
7926 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7927 | reject [Rn,...]. */ | |
7928 | if (inst.operands[1].preind) | |
b05fe5cf | 7929 | { |
bd3ba5d1 NC |
7930 | constraint (inst.reloc.exp.X_op != O_constant |
7931 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7932 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7933 | |
c19d1205 ZW |
7934 | inst.operands[1].preind = 0; |
7935 | inst.operands[1].postind = 1; | |
7936 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7937 | } |
c19d1205 ZW |
7938 | inst.instruction |= inst.operands[0].reg << 12; |
7939 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
7940 | } | |
b05fe5cf | 7941 | |
c19d1205 ZW |
7942 | /* Co-processor register load/store. |
7943 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
7944 | static void | |
7945 | do_lstc (void) | |
7946 | { | |
7947 | inst.instruction |= inst.operands[0].reg << 8; | |
7948 | inst.instruction |= inst.operands[1].reg << 12; | |
7949 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
7950 | } |
7951 | ||
b05fe5cf | 7952 | static void |
c19d1205 | 7953 | do_mlas (void) |
b05fe5cf | 7954 | { |
8fb9d7b9 | 7955 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 7956 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 7957 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 7958 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 7959 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 7960 | |
c19d1205 ZW |
7961 | inst.instruction |= inst.operands[0].reg << 16; |
7962 | inst.instruction |= inst.operands[1].reg; | |
7963 | inst.instruction |= inst.operands[2].reg << 8; | |
7964 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 7965 | } |
b05fe5cf | 7966 | |
c19d1205 ZW |
7967 | static void |
7968 | do_mov (void) | |
7969 | { | |
7970 | inst.instruction |= inst.operands[0].reg << 12; | |
7971 | encode_arm_shifter_operand (1); | |
7972 | } | |
b05fe5cf | 7973 | |
c19d1205 ZW |
7974 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
7975 | static void | |
7976 | do_mov16 (void) | |
7977 | { | |
b6895b4f PB |
7978 | bfd_vma imm; |
7979 | bfd_boolean top; | |
7980 | ||
7981 | top = (inst.instruction & 0x00400000) != 0; | |
7982 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
7983 | _(":lower16: not allowed this instruction")); | |
7984 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
7985 | _(":upper16: not allowed instruction")); | |
c19d1205 | 7986 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
7987 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
7988 | { | |
7989 | imm = inst.reloc.exp.X_add_number; | |
7990 | /* The value is in two pieces: 0:11, 16:19. */ | |
7991 | inst.instruction |= (imm & 0x00000fff); | |
7992 | inst.instruction |= (imm & 0x0000f000) << 4; | |
7993 | } | |
b05fe5cf | 7994 | } |
b99bd4ef | 7995 | |
037e8744 JB |
7996 | static void do_vfp_nsyn_opcode (const char *); |
7997 | ||
7998 | static int | |
7999 | do_vfp_nsyn_mrs (void) | |
8000 | { | |
8001 | if (inst.operands[0].isvec) | |
8002 | { | |
8003 | if (inst.operands[1].reg != 1) | |
8004 | first_error (_("operand 1 must be FPSCR")); | |
8005 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
8006 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
8007 | do_vfp_nsyn_opcode ("fmstat"); | |
8008 | } | |
8009 | else if (inst.operands[1].isvec) | |
8010 | do_vfp_nsyn_opcode ("fmrx"); | |
8011 | else | |
8012 | return FAIL; | |
5f4273c7 | 8013 | |
037e8744 JB |
8014 | return SUCCESS; |
8015 | } | |
8016 | ||
8017 | static int | |
8018 | do_vfp_nsyn_msr (void) | |
8019 | { | |
8020 | if (inst.operands[0].isvec) | |
8021 | do_vfp_nsyn_opcode ("fmxr"); | |
8022 | else | |
8023 | return FAIL; | |
8024 | ||
8025 | return SUCCESS; | |
8026 | } | |
8027 | ||
f7c21dc7 NC |
8028 | static void |
8029 | do_vmrs (void) | |
8030 | { | |
8031 | unsigned Rt = inst.operands[0].reg; | |
8032 | ||
8033 | if (thumb_mode && inst.operands[0].reg == REG_SP) | |
8034 | { | |
8035 | inst.error = BAD_SP; | |
8036 | return; | |
8037 | } | |
8038 | ||
8039 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
8040 | if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC) | |
8041 | { | |
8042 | inst.error = BAD_PC; | |
8043 | return; | |
8044 | } | |
8045 | ||
8046 | if (inst.operands[1].reg != 1) | |
8047 | first_error (_("operand 1 must be FPSCR")); | |
8048 | ||
8049 | inst.instruction |= (Rt << 12); | |
8050 | } | |
8051 | ||
8052 | static void | |
8053 | do_vmsr (void) | |
8054 | { | |
8055 | unsigned Rt = inst.operands[1].reg; | |
8056 | ||
8057 | if (thumb_mode) | |
8058 | reject_bad_reg (Rt); | |
8059 | else if (Rt == REG_PC) | |
8060 | { | |
8061 | inst.error = BAD_PC; | |
8062 | return; | |
8063 | } | |
8064 | ||
8065 | if (inst.operands[0].reg != 1) | |
8066 | first_error (_("operand 0 must be FPSCR")); | |
8067 | ||
8068 | inst.instruction |= (Rt << 12); | |
8069 | } | |
8070 | ||
b99bd4ef | 8071 | static void |
c19d1205 | 8072 | do_mrs (void) |
b99bd4ef | 8073 | { |
90ec0d68 MGD |
8074 | unsigned br; |
8075 | ||
037e8744 JB |
8076 | if (do_vfp_nsyn_mrs () == SUCCESS) |
8077 | return; | |
8078 | ||
ff4a8d2b | 8079 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 8080 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
8081 | |
8082 | if (inst.operands[1].isreg) | |
8083 | { | |
8084 | br = inst.operands[1].reg; | |
8085 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000)) | |
8086 | as_bad (_("bad register for mrs")); | |
8087 | } | |
8088 | else | |
8089 | { | |
8090 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
8091 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
8092 | != (PSR_c|PSR_f), | |
d2cd1205 | 8093 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
8094 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
8095 | } | |
8096 | ||
8097 | inst.instruction |= br; | |
c19d1205 | 8098 | } |
b99bd4ef | 8099 | |
c19d1205 ZW |
8100 | /* Two possible forms: |
8101 | "{C|S}PSR_<field>, Rm", | |
8102 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 8103 | |
c19d1205 ZW |
8104 | static void |
8105 | do_msr (void) | |
8106 | { | |
037e8744 JB |
8107 | if (do_vfp_nsyn_msr () == SUCCESS) |
8108 | return; | |
8109 | ||
c19d1205 ZW |
8110 | inst.instruction |= inst.operands[0].imm; |
8111 | if (inst.operands[1].isreg) | |
8112 | inst.instruction |= inst.operands[1].reg; | |
8113 | else | |
b99bd4ef | 8114 | { |
c19d1205 ZW |
8115 | inst.instruction |= INST_IMMEDIATE; |
8116 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
8117 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 8118 | } |
b99bd4ef NC |
8119 | } |
8120 | ||
c19d1205 ZW |
8121 | static void |
8122 | do_mul (void) | |
a737bd4d | 8123 | { |
ff4a8d2b NC |
8124 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
8125 | ||
c19d1205 ZW |
8126 | if (!inst.operands[2].present) |
8127 | inst.operands[2].reg = inst.operands[0].reg; | |
8128 | inst.instruction |= inst.operands[0].reg << 16; | |
8129 | inst.instruction |= inst.operands[1].reg; | |
8130 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 8131 | |
8fb9d7b9 MS |
8132 | if (inst.operands[0].reg == inst.operands[1].reg |
8133 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
8134 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
8135 | } |
8136 | ||
c19d1205 ZW |
8137 | /* Long Multiply Parser |
8138 | UMULL RdLo, RdHi, Rm, Rs | |
8139 | SMULL RdLo, RdHi, Rm, Rs | |
8140 | UMLAL RdLo, RdHi, Rm, Rs | |
8141 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
8142 | |
8143 | static void | |
c19d1205 | 8144 | do_mull (void) |
b99bd4ef | 8145 | { |
c19d1205 ZW |
8146 | inst.instruction |= inst.operands[0].reg << 12; |
8147 | inst.instruction |= inst.operands[1].reg << 16; | |
8148 | inst.instruction |= inst.operands[2].reg; | |
8149 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 8150 | |
682b27ad PB |
8151 | /* rdhi and rdlo must be different. */ |
8152 | if (inst.operands[0].reg == inst.operands[1].reg) | |
8153 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8154 | ||
8155 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
8156 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 8157 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 8158 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
8159 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
8160 | } | |
b99bd4ef | 8161 | |
c19d1205 ZW |
8162 | static void |
8163 | do_nop (void) | |
8164 | { | |
e7495e45 NS |
8165 | if (inst.operands[0].present |
8166 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
8167 | { |
8168 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
8169 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
8170 | inst.instruction |= 0x0320f000; |
8171 | if (inst.operands[0].present) | |
8172 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 8173 | } |
b99bd4ef NC |
8174 | } |
8175 | ||
c19d1205 ZW |
8176 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
8177 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
8178 | Condition defaults to COND_ALWAYS. | |
8179 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
8180 | |
8181 | static void | |
c19d1205 | 8182 | do_pkhbt (void) |
b99bd4ef | 8183 | { |
c19d1205 ZW |
8184 | inst.instruction |= inst.operands[0].reg << 12; |
8185 | inst.instruction |= inst.operands[1].reg << 16; | |
8186 | inst.instruction |= inst.operands[2].reg; | |
8187 | if (inst.operands[3].present) | |
8188 | encode_arm_shift (3); | |
8189 | } | |
b99bd4ef | 8190 | |
c19d1205 | 8191 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 8192 | |
c19d1205 ZW |
8193 | static void |
8194 | do_pkhtb (void) | |
8195 | { | |
8196 | if (!inst.operands[3].present) | |
b99bd4ef | 8197 | { |
c19d1205 ZW |
8198 | /* If the shift specifier is omitted, turn the instruction |
8199 | into pkhbt rd, rm, rn. */ | |
8200 | inst.instruction &= 0xfff00010; | |
8201 | inst.instruction |= inst.operands[0].reg << 12; | |
8202 | inst.instruction |= inst.operands[1].reg; | |
8203 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8204 | } |
8205 | else | |
8206 | { | |
c19d1205 ZW |
8207 | inst.instruction |= inst.operands[0].reg << 12; |
8208 | inst.instruction |= inst.operands[1].reg << 16; | |
8209 | inst.instruction |= inst.operands[2].reg; | |
8210 | encode_arm_shift (3); | |
b99bd4ef NC |
8211 | } |
8212 | } | |
8213 | ||
c19d1205 | 8214 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 8215 | MP Extensions: Preload for write |
c19d1205 | 8216 | |
60e5ef9f | 8217 | PLD(W) <addr_mode> |
c19d1205 ZW |
8218 | |
8219 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
8220 | |
8221 | static void | |
c19d1205 | 8222 | do_pld (void) |
b99bd4ef | 8223 | { |
c19d1205 ZW |
8224 | constraint (!inst.operands[0].isreg, |
8225 | _("'[' expected after PLD mnemonic")); | |
8226 | constraint (inst.operands[0].postind, | |
8227 | _("post-indexed expression used in preload instruction")); | |
8228 | constraint (inst.operands[0].writeback, | |
8229 | _("writeback used in preload instruction")); | |
8230 | constraint (!inst.operands[0].preind, | |
8231 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
8232 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
8233 | } | |
b99bd4ef | 8234 | |
62b3e311 PB |
8235 | /* ARMv7: PLI <addr_mode> */ |
8236 | static void | |
8237 | do_pli (void) | |
8238 | { | |
8239 | constraint (!inst.operands[0].isreg, | |
8240 | _("'[' expected after PLI mnemonic")); | |
8241 | constraint (inst.operands[0].postind, | |
8242 | _("post-indexed expression used in preload instruction")); | |
8243 | constraint (inst.operands[0].writeback, | |
8244 | _("writeback used in preload instruction")); | |
8245 | constraint (!inst.operands[0].preind, | |
8246 | _("unindexed addressing used in preload instruction")); | |
8247 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
8248 | inst.instruction &= ~PRE_INDEX; | |
8249 | } | |
8250 | ||
c19d1205 ZW |
8251 | static void |
8252 | do_push_pop (void) | |
8253 | { | |
8254 | inst.operands[1] = inst.operands[0]; | |
8255 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
8256 | inst.operands[0].isreg = 1; | |
8257 | inst.operands[0].writeback = 1; | |
8258 | inst.operands[0].reg = REG_SP; | |
8259 | do_ldmstm (); | |
8260 | } | |
b99bd4ef | 8261 | |
c19d1205 ZW |
8262 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
8263 | word at the specified address and the following word | |
8264 | respectively. | |
8265 | Unconditionally executed. | |
8266 | Error if Rn is R15. */ | |
b99bd4ef | 8267 | |
c19d1205 ZW |
8268 | static void |
8269 | do_rfe (void) | |
8270 | { | |
8271 | inst.instruction |= inst.operands[0].reg << 16; | |
8272 | if (inst.operands[0].writeback) | |
8273 | inst.instruction |= WRITE_BACK; | |
8274 | } | |
b99bd4ef | 8275 | |
c19d1205 | 8276 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 8277 | |
c19d1205 ZW |
8278 | static void |
8279 | do_ssat (void) | |
8280 | { | |
8281 | inst.instruction |= inst.operands[0].reg << 12; | |
8282 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
8283 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8284 | |
c19d1205 ZW |
8285 | if (inst.operands[3].present) |
8286 | encode_arm_shift (3); | |
b99bd4ef NC |
8287 | } |
8288 | ||
c19d1205 | 8289 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
8290 | |
8291 | static void | |
c19d1205 | 8292 | do_usat (void) |
b99bd4ef | 8293 | { |
c19d1205 ZW |
8294 | inst.instruction |= inst.operands[0].reg << 12; |
8295 | inst.instruction |= inst.operands[1].imm << 16; | |
8296 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8297 | |
c19d1205 ZW |
8298 | if (inst.operands[3].present) |
8299 | encode_arm_shift (3); | |
b99bd4ef NC |
8300 | } |
8301 | ||
c19d1205 | 8302 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
8303 | |
8304 | static void | |
c19d1205 | 8305 | do_ssat16 (void) |
09d92015 | 8306 | { |
c19d1205 ZW |
8307 | inst.instruction |= inst.operands[0].reg << 12; |
8308 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
8309 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
8310 | } |
8311 | ||
c19d1205 ZW |
8312 | static void |
8313 | do_usat16 (void) | |
a737bd4d | 8314 | { |
c19d1205 ZW |
8315 | inst.instruction |= inst.operands[0].reg << 12; |
8316 | inst.instruction |= inst.operands[1].imm << 16; | |
8317 | inst.instruction |= inst.operands[2].reg; | |
8318 | } | |
a737bd4d | 8319 | |
c19d1205 ZW |
8320 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
8321 | preserving the other bits. | |
a737bd4d | 8322 | |
c19d1205 ZW |
8323 | setend <endian_specifier>, where <endian_specifier> is either |
8324 | BE or LE. */ | |
a737bd4d | 8325 | |
c19d1205 ZW |
8326 | static void |
8327 | do_setend (void) | |
8328 | { | |
8329 | if (inst.operands[0].imm) | |
8330 | inst.instruction |= 0x200; | |
a737bd4d NC |
8331 | } |
8332 | ||
8333 | static void | |
c19d1205 | 8334 | do_shift (void) |
a737bd4d | 8335 | { |
c19d1205 ZW |
8336 | unsigned int Rm = (inst.operands[1].present |
8337 | ? inst.operands[1].reg | |
8338 | : inst.operands[0].reg); | |
a737bd4d | 8339 | |
c19d1205 ZW |
8340 | inst.instruction |= inst.operands[0].reg << 12; |
8341 | inst.instruction |= Rm; | |
8342 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 8343 | { |
c19d1205 ZW |
8344 | inst.instruction |= inst.operands[2].reg << 8; |
8345 | inst.instruction |= SHIFT_BY_REG; | |
a737bd4d NC |
8346 | } |
8347 | else | |
c19d1205 | 8348 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
8349 | } |
8350 | ||
09d92015 | 8351 | static void |
3eb17e6b | 8352 | do_smc (void) |
09d92015 | 8353 | { |
3eb17e6b | 8354 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 8355 | inst.reloc.pc_rel = 0; |
09d92015 MM |
8356 | } |
8357 | ||
90ec0d68 MGD |
8358 | static void |
8359 | do_hvc (void) | |
8360 | { | |
8361 | inst.reloc.type = BFD_RELOC_ARM_HVC; | |
8362 | inst.reloc.pc_rel = 0; | |
8363 | } | |
8364 | ||
09d92015 | 8365 | static void |
c19d1205 | 8366 | do_swi (void) |
09d92015 | 8367 | { |
c19d1205 ZW |
8368 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
8369 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
8370 | } |
8371 | ||
c19d1205 ZW |
8372 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
8373 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
8374 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
8375 | Error if any register is R15. */ | |
e16bb312 | 8376 | |
c19d1205 ZW |
8377 | static void |
8378 | do_smla (void) | |
e16bb312 | 8379 | { |
c19d1205 ZW |
8380 | inst.instruction |= inst.operands[0].reg << 16; |
8381 | inst.instruction |= inst.operands[1].reg; | |
8382 | inst.instruction |= inst.operands[2].reg << 8; | |
8383 | inst.instruction |= inst.operands[3].reg << 12; | |
8384 | } | |
a737bd4d | 8385 | |
c19d1205 ZW |
8386 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
8387 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
8388 | Error if any register is R15. | |
8389 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 8390 | |
c19d1205 ZW |
8391 | static void |
8392 | do_smlal (void) | |
8393 | { | |
8394 | inst.instruction |= inst.operands[0].reg << 12; | |
8395 | inst.instruction |= inst.operands[1].reg << 16; | |
8396 | inst.instruction |= inst.operands[2].reg; | |
8397 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 8398 | |
c19d1205 ZW |
8399 | if (inst.operands[0].reg == inst.operands[1].reg) |
8400 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8401 | } | |
a737bd4d | 8402 | |
c19d1205 ZW |
8403 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
8404 | SMULxy{cond} Rd,Rm,Rs | |
8405 | Error if any register is R15. */ | |
a737bd4d | 8406 | |
c19d1205 ZW |
8407 | static void |
8408 | do_smul (void) | |
8409 | { | |
8410 | inst.instruction |= inst.operands[0].reg << 16; | |
8411 | inst.instruction |= inst.operands[1].reg; | |
8412 | inst.instruction |= inst.operands[2].reg << 8; | |
8413 | } | |
a737bd4d | 8414 | |
b6702015 PB |
8415 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
8416 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 8417 | |
c19d1205 ZW |
8418 | static void |
8419 | do_srs (void) | |
8420 | { | |
b6702015 PB |
8421 | int reg; |
8422 | ||
8423 | if (inst.operands[0].present) | |
8424 | { | |
8425 | reg = inst.operands[0].reg; | |
fdfde340 | 8426 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
8427 | } |
8428 | else | |
fdfde340 | 8429 | reg = REG_SP; |
b6702015 PB |
8430 | |
8431 | inst.instruction |= reg << 16; | |
8432 | inst.instruction |= inst.operands[1].imm; | |
8433 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
8434 | inst.instruction |= WRITE_BACK; |
8435 | } | |
a737bd4d | 8436 | |
c19d1205 | 8437 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 8438 | |
c19d1205 ZW |
8439 | static void |
8440 | do_strex (void) | |
8441 | { | |
8442 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8443 | || inst.operands[2].postind || inst.operands[2].writeback | |
8444 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
8445 | || inst.operands[2].negative |
8446 | /* See comment in do_ldrex(). */ | |
8447 | || (inst.operands[2].reg == REG_PC), | |
8448 | BAD_ADDR_MODE); | |
a737bd4d | 8449 | |
c19d1205 ZW |
8450 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8451 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 8452 | |
c19d1205 ZW |
8453 | constraint (inst.reloc.exp.X_op != O_constant |
8454 | || inst.reloc.exp.X_add_number != 0, | |
8455 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 8456 | |
c19d1205 ZW |
8457 | inst.instruction |= inst.operands[0].reg << 12; |
8458 | inst.instruction |= inst.operands[1].reg; | |
8459 | inst.instruction |= inst.operands[2].reg << 16; | |
8460 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
8461 | } |
8462 | ||
8463 | static void | |
c19d1205 | 8464 | do_strexd (void) |
e16bb312 | 8465 | { |
c19d1205 ZW |
8466 | constraint (inst.operands[1].reg % 2 != 0, |
8467 | _("even register required")); | |
8468 | constraint (inst.operands[2].present | |
8469 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
8470 | _("can only store two consecutive registers")); | |
8471 | /* If op 2 were present and equal to PC, this function wouldn't | |
8472 | have been called in the first place. */ | |
8473 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 8474 | |
c19d1205 ZW |
8475 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8476 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
8477 | || inst.operands[0].reg == inst.operands[3].reg, | |
8478 | BAD_OVERLAP); | |
e16bb312 | 8479 | |
c19d1205 ZW |
8480 | inst.instruction |= inst.operands[0].reg << 12; |
8481 | inst.instruction |= inst.operands[1].reg; | |
8482 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
8483 | } |
8484 | ||
c19d1205 ZW |
8485 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
8486 | extends it to 32-bits, and adds the result to a value in another | |
8487 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
8488 | before extracting the 16-bit value. | |
8489 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
8490 | Condition defaults to COND_ALWAYS. | |
8491 | Error if any register uses R15. */ | |
8492 | ||
e16bb312 | 8493 | static void |
c19d1205 | 8494 | do_sxtah (void) |
e16bb312 | 8495 | { |
c19d1205 ZW |
8496 | inst.instruction |= inst.operands[0].reg << 12; |
8497 | inst.instruction |= inst.operands[1].reg << 16; | |
8498 | inst.instruction |= inst.operands[2].reg; | |
8499 | inst.instruction |= inst.operands[3].imm << 10; | |
8500 | } | |
e16bb312 | 8501 | |
c19d1205 | 8502 | /* ARM V6 SXTH. |
e16bb312 | 8503 | |
c19d1205 ZW |
8504 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
8505 | Condition defaults to COND_ALWAYS. | |
8506 | Error if any register uses R15. */ | |
e16bb312 NC |
8507 | |
8508 | static void | |
c19d1205 | 8509 | do_sxth (void) |
e16bb312 | 8510 | { |
c19d1205 ZW |
8511 | inst.instruction |= inst.operands[0].reg << 12; |
8512 | inst.instruction |= inst.operands[1].reg; | |
8513 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 8514 | } |
c19d1205 ZW |
8515 | \f |
8516 | /* VFP instructions. In a logical order: SP variant first, monad | |
8517 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
8518 | |
8519 | static void | |
c19d1205 | 8520 | do_vfp_sp_monadic (void) |
e16bb312 | 8521 | { |
5287ad62 JB |
8522 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8523 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8524 | } |
8525 | ||
8526 | static void | |
c19d1205 | 8527 | do_vfp_sp_dyadic (void) |
e16bb312 | 8528 | { |
5287ad62 JB |
8529 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8530 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
8531 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
8532 | } |
8533 | ||
8534 | static void | |
c19d1205 | 8535 | do_vfp_sp_compare_z (void) |
e16bb312 | 8536 | { |
5287ad62 | 8537 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
8538 | } |
8539 | ||
8540 | static void | |
c19d1205 | 8541 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 8542 | { |
5287ad62 JB |
8543 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
8544 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8545 | } |
8546 | ||
8547 | static void | |
c19d1205 | 8548 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 8549 | { |
5287ad62 JB |
8550 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8551 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
8552 | } |
8553 | ||
8554 | static void | |
c19d1205 | 8555 | do_vfp_reg_from_sp (void) |
e16bb312 | 8556 | { |
c19d1205 | 8557 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 8558 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
8559 | } |
8560 | ||
8561 | static void | |
c19d1205 | 8562 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 8563 | { |
c19d1205 ZW |
8564 | constraint (inst.operands[2].imm != 2, |
8565 | _("only two consecutive VFP SP registers allowed here")); | |
8566 | inst.instruction |= inst.operands[0].reg << 12; | |
8567 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 8568 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
8569 | } |
8570 | ||
8571 | static void | |
c19d1205 | 8572 | do_vfp_sp_from_reg (void) |
e16bb312 | 8573 | { |
5287ad62 | 8574 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 8575 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
8576 | } |
8577 | ||
8578 | static void | |
c19d1205 | 8579 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 8580 | { |
c19d1205 ZW |
8581 | constraint (inst.operands[0].imm != 2, |
8582 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 8583 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
8584 | inst.instruction |= inst.operands[1].reg << 12; |
8585 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
8586 | } |
8587 | ||
8588 | static void | |
c19d1205 | 8589 | do_vfp_sp_ldst (void) |
e16bb312 | 8590 | { |
5287ad62 | 8591 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 8592 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8593 | } |
8594 | ||
8595 | static void | |
c19d1205 | 8596 | do_vfp_dp_ldst (void) |
e16bb312 | 8597 | { |
5287ad62 | 8598 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 8599 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8600 | } |
8601 | ||
c19d1205 | 8602 | |
e16bb312 | 8603 | static void |
c19d1205 | 8604 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8605 | { |
c19d1205 ZW |
8606 | if (inst.operands[0].writeback) |
8607 | inst.instruction |= WRITE_BACK; | |
8608 | else | |
8609 | constraint (ldstm_type != VFP_LDSTMIA, | |
8610 | _("this addressing mode requires base-register writeback")); | |
8611 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 8612 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 8613 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
8614 | } |
8615 | ||
8616 | static void | |
c19d1205 | 8617 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8618 | { |
c19d1205 | 8619 | int count; |
e16bb312 | 8620 | |
c19d1205 ZW |
8621 | if (inst.operands[0].writeback) |
8622 | inst.instruction |= WRITE_BACK; | |
8623 | else | |
8624 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
8625 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 8626 | |
c19d1205 | 8627 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 8628 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 8629 | |
c19d1205 ZW |
8630 | count = inst.operands[1].imm << 1; |
8631 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
8632 | count += 1; | |
e16bb312 | 8633 | |
c19d1205 | 8634 | inst.instruction |= count; |
e16bb312 NC |
8635 | } |
8636 | ||
8637 | static void | |
c19d1205 | 8638 | do_vfp_sp_ldstmia (void) |
e16bb312 | 8639 | { |
c19d1205 | 8640 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8641 | } |
8642 | ||
8643 | static void | |
c19d1205 | 8644 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 8645 | { |
c19d1205 | 8646 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8647 | } |
8648 | ||
8649 | static void | |
c19d1205 | 8650 | do_vfp_dp_ldstmia (void) |
e16bb312 | 8651 | { |
c19d1205 | 8652 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8653 | } |
8654 | ||
8655 | static void | |
c19d1205 | 8656 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 8657 | { |
c19d1205 | 8658 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8659 | } |
8660 | ||
8661 | static void | |
c19d1205 | 8662 | do_vfp_xp_ldstmia (void) |
e16bb312 | 8663 | { |
c19d1205 ZW |
8664 | vfp_dp_ldstm (VFP_LDSTMIAX); |
8665 | } | |
e16bb312 | 8666 | |
c19d1205 ZW |
8667 | static void |
8668 | do_vfp_xp_ldstmdb (void) | |
8669 | { | |
8670 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 8671 | } |
5287ad62 JB |
8672 | |
8673 | static void | |
8674 | do_vfp_dp_rd_rm (void) | |
8675 | { | |
8676 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8677 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
8678 | } | |
8679 | ||
8680 | static void | |
8681 | do_vfp_dp_rn_rd (void) | |
8682 | { | |
8683 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
8684 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8685 | } | |
8686 | ||
8687 | static void | |
8688 | do_vfp_dp_rd_rn (void) | |
8689 | { | |
8690 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8691 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8692 | } | |
8693 | ||
8694 | static void | |
8695 | do_vfp_dp_rd_rn_rm (void) | |
8696 | { | |
8697 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8698 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8699 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
8700 | } | |
8701 | ||
8702 | static void | |
8703 | do_vfp_dp_rd (void) | |
8704 | { | |
8705 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8706 | } | |
8707 | ||
8708 | static void | |
8709 | do_vfp_dp_rm_rd_rn (void) | |
8710 | { | |
8711 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
8712 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8713 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
8714 | } | |
8715 | ||
8716 | /* VFPv3 instructions. */ | |
8717 | static void | |
8718 | do_vfp_sp_const (void) | |
8719 | { | |
8720 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
8721 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8722 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8723 | } |
8724 | ||
8725 | static void | |
8726 | do_vfp_dp_const (void) | |
8727 | { | |
8728 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
8729 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8730 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8731 | } |
8732 | ||
8733 | static void | |
8734 | vfp_conv (int srcsize) | |
8735 | { | |
8736 | unsigned immbits = srcsize - inst.operands[1].imm; | |
8737 | inst.instruction |= (immbits & 1) << 5; | |
8738 | inst.instruction |= (immbits >> 1); | |
8739 | } | |
8740 | ||
8741 | static void | |
8742 | do_vfp_sp_conv_16 (void) | |
8743 | { | |
8744 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8745 | vfp_conv (16); | |
8746 | } | |
8747 | ||
8748 | static void | |
8749 | do_vfp_dp_conv_16 (void) | |
8750 | { | |
8751 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8752 | vfp_conv (16); | |
8753 | } | |
8754 | ||
8755 | static void | |
8756 | do_vfp_sp_conv_32 (void) | |
8757 | { | |
8758 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8759 | vfp_conv (32); | |
8760 | } | |
8761 | ||
8762 | static void | |
8763 | do_vfp_dp_conv_32 (void) | |
8764 | { | |
8765 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8766 | vfp_conv (32); | |
8767 | } | |
c19d1205 ZW |
8768 | \f |
8769 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 8770 | |
c19d1205 ZW |
8771 | static void |
8772 | do_fpa_cmp (void) | |
8773 | { | |
8774 | inst.instruction |= inst.operands[0].reg << 16; | |
8775 | inst.instruction |= inst.operands[1].reg; | |
8776 | } | |
b99bd4ef NC |
8777 | |
8778 | static void | |
c19d1205 | 8779 | do_fpa_ldmstm (void) |
b99bd4ef | 8780 | { |
c19d1205 ZW |
8781 | inst.instruction |= inst.operands[0].reg << 12; |
8782 | switch (inst.operands[1].imm) | |
8783 | { | |
8784 | case 1: inst.instruction |= CP_T_X; break; | |
8785 | case 2: inst.instruction |= CP_T_Y; break; | |
8786 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
8787 | case 4: break; | |
8788 | default: abort (); | |
8789 | } | |
b99bd4ef | 8790 | |
c19d1205 ZW |
8791 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
8792 | { | |
8793 | /* The instruction specified "ea" or "fd", so we can only accept | |
8794 | [Rn]{!}. The instruction does not really support stacking or | |
8795 | unstacking, so we have to emulate these by setting appropriate | |
8796 | bits and offsets. */ | |
8797 | constraint (inst.reloc.exp.X_op != O_constant | |
8798 | || inst.reloc.exp.X_add_number != 0, | |
8799 | _("this instruction does not support indexing")); | |
b99bd4ef | 8800 | |
c19d1205 ZW |
8801 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
8802 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 8803 | |
c19d1205 ZW |
8804 | if (!(inst.instruction & INDEX_UP)) |
8805 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 8806 | |
c19d1205 ZW |
8807 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
8808 | { | |
8809 | inst.operands[2].preind = 0; | |
8810 | inst.operands[2].postind = 1; | |
8811 | } | |
8812 | } | |
b99bd4ef | 8813 | |
c19d1205 | 8814 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 8815 | } |
c19d1205 ZW |
8816 | \f |
8817 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 8818 | |
c19d1205 ZW |
8819 | static void |
8820 | do_iwmmxt_tandorc (void) | |
8821 | { | |
8822 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
8823 | } | |
b99bd4ef | 8824 | |
c19d1205 ZW |
8825 | static void |
8826 | do_iwmmxt_textrc (void) | |
8827 | { | |
8828 | inst.instruction |= inst.operands[0].reg << 12; | |
8829 | inst.instruction |= inst.operands[1].imm; | |
8830 | } | |
b99bd4ef NC |
8831 | |
8832 | static void | |
c19d1205 | 8833 | do_iwmmxt_textrm (void) |
b99bd4ef | 8834 | { |
c19d1205 ZW |
8835 | inst.instruction |= inst.operands[0].reg << 12; |
8836 | inst.instruction |= inst.operands[1].reg << 16; | |
8837 | inst.instruction |= inst.operands[2].imm; | |
8838 | } | |
b99bd4ef | 8839 | |
c19d1205 ZW |
8840 | static void |
8841 | do_iwmmxt_tinsr (void) | |
8842 | { | |
8843 | inst.instruction |= inst.operands[0].reg << 16; | |
8844 | inst.instruction |= inst.operands[1].reg << 12; | |
8845 | inst.instruction |= inst.operands[2].imm; | |
8846 | } | |
b99bd4ef | 8847 | |
c19d1205 ZW |
8848 | static void |
8849 | do_iwmmxt_tmia (void) | |
8850 | { | |
8851 | inst.instruction |= inst.operands[0].reg << 5; | |
8852 | inst.instruction |= inst.operands[1].reg; | |
8853 | inst.instruction |= inst.operands[2].reg << 12; | |
8854 | } | |
b99bd4ef | 8855 | |
c19d1205 ZW |
8856 | static void |
8857 | do_iwmmxt_waligni (void) | |
8858 | { | |
8859 | inst.instruction |= inst.operands[0].reg << 12; | |
8860 | inst.instruction |= inst.operands[1].reg << 16; | |
8861 | inst.instruction |= inst.operands[2].reg; | |
8862 | inst.instruction |= inst.operands[3].imm << 20; | |
8863 | } | |
b99bd4ef | 8864 | |
2d447fca JM |
8865 | static void |
8866 | do_iwmmxt_wmerge (void) | |
8867 | { | |
8868 | inst.instruction |= inst.operands[0].reg << 12; | |
8869 | inst.instruction |= inst.operands[1].reg << 16; | |
8870 | inst.instruction |= inst.operands[2].reg; | |
8871 | inst.instruction |= inst.operands[3].imm << 21; | |
8872 | } | |
8873 | ||
c19d1205 ZW |
8874 | static void |
8875 | do_iwmmxt_wmov (void) | |
8876 | { | |
8877 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
8878 | inst.instruction |= inst.operands[0].reg << 12; | |
8879 | inst.instruction |= inst.operands[1].reg << 16; | |
8880 | inst.instruction |= inst.operands[1].reg; | |
8881 | } | |
b99bd4ef | 8882 | |
c19d1205 ZW |
8883 | static void |
8884 | do_iwmmxt_wldstbh (void) | |
8885 | { | |
8f06b2d8 | 8886 | int reloc; |
c19d1205 | 8887 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
8888 | if (thumb_mode) |
8889 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
8890 | else | |
8891 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
8892 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
8893 | } |
8894 | ||
c19d1205 ZW |
8895 | static void |
8896 | do_iwmmxt_wldstw (void) | |
8897 | { | |
8898 | /* RIWR_RIWC clears .isreg for a control register. */ | |
8899 | if (!inst.operands[0].isreg) | |
8900 | { | |
8901 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
8902 | inst.instruction |= 0xf0000000; | |
8903 | } | |
b99bd4ef | 8904 | |
c19d1205 ZW |
8905 | inst.instruction |= inst.operands[0].reg << 12; |
8906 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
8907 | } | |
b99bd4ef NC |
8908 | |
8909 | static void | |
c19d1205 | 8910 | do_iwmmxt_wldstd (void) |
b99bd4ef | 8911 | { |
c19d1205 | 8912 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
8913 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
8914 | && inst.operands[1].immisreg) | |
8915 | { | |
8916 | inst.instruction &= ~0x1a000ff; | |
8917 | inst.instruction |= (0xf << 28); | |
8918 | if (inst.operands[1].preind) | |
8919 | inst.instruction |= PRE_INDEX; | |
8920 | if (!inst.operands[1].negative) | |
8921 | inst.instruction |= INDEX_UP; | |
8922 | if (inst.operands[1].writeback) | |
8923 | inst.instruction |= WRITE_BACK; | |
8924 | inst.instruction |= inst.operands[1].reg << 16; | |
8925 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
8926 | inst.instruction |= inst.operands[1].imm; | |
8927 | } | |
8928 | else | |
8929 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 8930 | } |
b99bd4ef | 8931 | |
c19d1205 ZW |
8932 | static void |
8933 | do_iwmmxt_wshufh (void) | |
8934 | { | |
8935 | inst.instruction |= inst.operands[0].reg << 12; | |
8936 | inst.instruction |= inst.operands[1].reg << 16; | |
8937 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
8938 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
8939 | } | |
b99bd4ef | 8940 | |
c19d1205 ZW |
8941 | static void |
8942 | do_iwmmxt_wzero (void) | |
8943 | { | |
8944 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
8945 | inst.instruction |= inst.operands[0].reg; | |
8946 | inst.instruction |= inst.operands[0].reg << 12; | |
8947 | inst.instruction |= inst.operands[0].reg << 16; | |
8948 | } | |
2d447fca JM |
8949 | |
8950 | static void | |
8951 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
8952 | { | |
8953 | if (inst.operands[2].isreg) | |
8954 | do_rd_rn_rm (); | |
8955 | else { | |
8956 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
8957 | _("immediate operand requires iWMMXt2")); | |
8958 | do_rd_rn (); | |
8959 | if (inst.operands[2].imm == 0) | |
8960 | { | |
8961 | switch ((inst.instruction >> 20) & 0xf) | |
8962 | { | |
8963 | case 4: | |
8964 | case 5: | |
8965 | case 6: | |
5f4273c7 | 8966 | case 7: |
2d447fca JM |
8967 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
8968 | inst.operands[2].imm = 16; | |
8969 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
8970 | break; | |
8971 | case 8: | |
8972 | case 9: | |
8973 | case 10: | |
8974 | case 11: | |
8975 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
8976 | inst.operands[2].imm = 32; | |
8977 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
8978 | break; | |
8979 | case 12: | |
8980 | case 13: | |
8981 | case 14: | |
8982 | case 15: | |
8983 | { | |
8984 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
8985 | unsigned long wrn; | |
8986 | wrn = (inst.instruction >> 16) & 0xf; | |
8987 | inst.instruction &= 0xff0fff0f; | |
8988 | inst.instruction |= wrn; | |
8989 | /* Bail out here; the instruction is now assembled. */ | |
8990 | return; | |
8991 | } | |
8992 | } | |
8993 | } | |
8994 | /* Map 32 -> 0, etc. */ | |
8995 | inst.operands[2].imm &= 0x1f; | |
8996 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
8997 | } | |
8998 | } | |
c19d1205 ZW |
8999 | \f |
9000 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
9001 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 9002 | |
c19d1205 | 9003 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 9004 | |
c19d1205 ZW |
9005 | static void |
9006 | do_mav_triple (void) | |
9007 | { | |
9008 | inst.instruction |= inst.operands[0].reg << 16; | |
9009 | inst.instruction |= inst.operands[1].reg; | |
9010 | inst.instruction |= inst.operands[2].reg << 12; | |
9011 | } | |
b99bd4ef | 9012 | |
c19d1205 ZW |
9013 | /* Insns like "foo W,X,Y,Z". |
9014 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 9015 | |
c19d1205 ZW |
9016 | static void |
9017 | do_mav_quad (void) | |
9018 | { | |
9019 | inst.instruction |= inst.operands[0].reg << 5; | |
9020 | inst.instruction |= inst.operands[1].reg << 12; | |
9021 | inst.instruction |= inst.operands[2].reg << 16; | |
9022 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
9023 | } |
9024 | ||
c19d1205 ZW |
9025 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
9026 | static void | |
9027 | do_mav_dspsc (void) | |
a737bd4d | 9028 | { |
c19d1205 ZW |
9029 | inst.instruction |= inst.operands[1].reg << 12; |
9030 | } | |
a737bd4d | 9031 | |
c19d1205 ZW |
9032 | /* Maverick shift immediate instructions. |
9033 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
9034 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 9035 | |
c19d1205 ZW |
9036 | static void |
9037 | do_mav_shift (void) | |
9038 | { | |
9039 | int imm = inst.operands[2].imm; | |
a737bd4d | 9040 | |
c19d1205 ZW |
9041 | inst.instruction |= inst.operands[0].reg << 12; |
9042 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 9043 | |
c19d1205 ZW |
9044 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
9045 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
9046 | Bit 4 should be 0. */ | |
9047 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 9048 | |
c19d1205 ZW |
9049 | inst.instruction |= imm; |
9050 | } | |
9051 | \f | |
9052 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 9053 | |
c19d1205 ZW |
9054 | /* Xscale multiply-accumulate (argument parse) |
9055 | MIAcc acc0,Rm,Rs | |
9056 | MIAPHcc acc0,Rm,Rs | |
9057 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 9058 | |
c19d1205 ZW |
9059 | static void |
9060 | do_xsc_mia (void) | |
9061 | { | |
9062 | inst.instruction |= inst.operands[1].reg; | |
9063 | inst.instruction |= inst.operands[2].reg << 12; | |
9064 | } | |
a737bd4d | 9065 | |
c19d1205 | 9066 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 9067 | |
c19d1205 | 9068 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 9069 | |
c19d1205 ZW |
9070 | static void |
9071 | do_xsc_mar (void) | |
9072 | { | |
9073 | inst.instruction |= inst.operands[1].reg << 12; | |
9074 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9075 | } |
9076 | ||
c19d1205 | 9077 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 9078 | |
c19d1205 | 9079 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
9080 | |
9081 | static void | |
c19d1205 | 9082 | do_xsc_mra (void) |
b99bd4ef | 9083 | { |
c19d1205 ZW |
9084 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
9085 | inst.instruction |= inst.operands[0].reg << 12; | |
9086 | inst.instruction |= inst.operands[1].reg << 16; | |
9087 | } | |
9088 | \f | |
9089 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 9090 | |
c19d1205 ZW |
9091 | /* inst.operands[i] is a shifted-register operand; encode |
9092 | it into inst.instruction in the format used by Thumb32. */ | |
9093 | ||
9094 | static void | |
9095 | encode_thumb32_shifted_operand (int i) | |
9096 | { | |
9097 | unsigned int value = inst.reloc.exp.X_add_number; | |
9098 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 9099 | |
9c3c69f2 PB |
9100 | constraint (inst.operands[i].immisreg, |
9101 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
9102 | inst.instruction |= inst.operands[i].reg; |
9103 | if (shift == SHIFT_RRX) | |
9104 | inst.instruction |= SHIFT_ROR << 4; | |
9105 | else | |
b99bd4ef | 9106 | { |
c19d1205 ZW |
9107 | constraint (inst.reloc.exp.X_op != O_constant, |
9108 | _("expression too complex")); | |
9109 | ||
9110 | constraint (value > 32 | |
9111 | || (value == 32 && (shift == SHIFT_LSL | |
9112 | || shift == SHIFT_ROR)), | |
9113 | _("shift expression is too large")); | |
9114 | ||
9115 | if (value == 0) | |
9116 | shift = SHIFT_LSL; | |
9117 | else if (value == 32) | |
9118 | value = 0; | |
9119 | ||
9120 | inst.instruction |= shift << 4; | |
9121 | inst.instruction |= (value & 0x1c) << 10; | |
9122 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 9123 | } |
c19d1205 | 9124 | } |
b99bd4ef | 9125 | |
b99bd4ef | 9126 | |
c19d1205 ZW |
9127 | /* inst.operands[i] was set up by parse_address. Encode it into a |
9128 | Thumb32 format load or store instruction. Reject forms that cannot | |
9129 | be used with such instructions. If is_t is true, reject forms that | |
9130 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
9131 | that cannot be used with a D instruction. If it is a store insn, |
9132 | reject PC in Rn. */ | |
b99bd4ef | 9133 | |
c19d1205 ZW |
9134 | static void |
9135 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
9136 | { | |
5be8be5d | 9137 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
9138 | |
9139 | constraint (!inst.operands[i].isreg, | |
53365c0d | 9140 | _("Instruction does not support =N addresses")); |
b99bd4ef | 9141 | |
c19d1205 ZW |
9142 | inst.instruction |= inst.operands[i].reg << 16; |
9143 | if (inst.operands[i].immisreg) | |
b99bd4ef | 9144 | { |
5be8be5d | 9145 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
9146 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
9147 | constraint (inst.operands[i].negative, | |
9148 | _("Thumb does not support negative register indexing")); | |
9149 | constraint (inst.operands[i].postind, | |
9150 | _("Thumb does not support register post-indexing")); | |
9151 | constraint (inst.operands[i].writeback, | |
9152 | _("Thumb does not support register indexing with writeback")); | |
9153 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
9154 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 9155 | |
f40d1643 | 9156 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 9157 | if (inst.operands[i].shifted) |
b99bd4ef | 9158 | { |
c19d1205 ZW |
9159 | constraint (inst.reloc.exp.X_op != O_constant, |
9160 | _("expression too complex")); | |
9c3c69f2 PB |
9161 | constraint (inst.reloc.exp.X_add_number < 0 |
9162 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 9163 | _("shift out of range")); |
9c3c69f2 | 9164 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
9165 | } |
9166 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9167 | } | |
9168 | else if (inst.operands[i].preind) | |
9169 | { | |
5be8be5d | 9170 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 9171 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 9172 | _("cannot use writeback with this instruction")); |
5be8be5d DG |
9173 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0) |
9174 | && !inst.reloc.pc_rel, BAD_PC_ADDRESSING); | |
c19d1205 ZW |
9175 | |
9176 | if (is_d) | |
9177 | { | |
9178 | inst.instruction |= 0x01000000; | |
9179 | if (inst.operands[i].writeback) | |
9180 | inst.instruction |= 0x00200000; | |
b99bd4ef | 9181 | } |
c19d1205 | 9182 | else |
b99bd4ef | 9183 | { |
c19d1205 ZW |
9184 | inst.instruction |= 0x00000c00; |
9185 | if (inst.operands[i].writeback) | |
9186 | inst.instruction |= 0x00000100; | |
b99bd4ef | 9187 | } |
c19d1205 | 9188 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 9189 | } |
c19d1205 | 9190 | else if (inst.operands[i].postind) |
b99bd4ef | 9191 | { |
9c2799c2 | 9192 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
9193 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
9194 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
9195 | ||
9196 | if (is_d) | |
9197 | inst.instruction |= 0x00200000; | |
9198 | else | |
9199 | inst.instruction |= 0x00000900; | |
9200 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
9201 | } | |
9202 | else /* unindexed - only for coprocessor */ | |
9203 | inst.error = _("instruction does not accept unindexed addressing"); | |
9204 | } | |
9205 | ||
9206 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
9207 | encodings (the latter only in post-V6T2 cores). The index is the | |
9208 | value used in the insns table below. When there is more than one | |
9209 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
9210 | holds variant (1). |
9211 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 9212 | #define T16_32_TAB \ |
21d799b5 NC |
9213 | X(_adc, 4140, eb400000), \ |
9214 | X(_adcs, 4140, eb500000), \ | |
9215 | X(_add, 1c00, eb000000), \ | |
9216 | X(_adds, 1c00, eb100000), \ | |
9217 | X(_addi, 0000, f1000000), \ | |
9218 | X(_addis, 0000, f1100000), \ | |
9219 | X(_add_pc,000f, f20f0000), \ | |
9220 | X(_add_sp,000d, f10d0000), \ | |
9221 | X(_adr, 000f, f20f0000), \ | |
9222 | X(_and, 4000, ea000000), \ | |
9223 | X(_ands, 4000, ea100000), \ | |
9224 | X(_asr, 1000, fa40f000), \ | |
9225 | X(_asrs, 1000, fa50f000), \ | |
9226 | X(_b, e000, f000b000), \ | |
9227 | X(_bcond, d000, f0008000), \ | |
9228 | X(_bic, 4380, ea200000), \ | |
9229 | X(_bics, 4380, ea300000), \ | |
9230 | X(_cmn, 42c0, eb100f00), \ | |
9231 | X(_cmp, 2800, ebb00f00), \ | |
9232 | X(_cpsie, b660, f3af8400), \ | |
9233 | X(_cpsid, b670, f3af8600), \ | |
9234 | X(_cpy, 4600, ea4f0000), \ | |
9235 | X(_dec_sp,80dd, f1ad0d00), \ | |
9236 | X(_eor, 4040, ea800000), \ | |
9237 | X(_eors, 4040, ea900000), \ | |
9238 | X(_inc_sp,00dd, f10d0d00), \ | |
9239 | X(_ldmia, c800, e8900000), \ | |
9240 | X(_ldr, 6800, f8500000), \ | |
9241 | X(_ldrb, 7800, f8100000), \ | |
9242 | X(_ldrh, 8800, f8300000), \ | |
9243 | X(_ldrsb, 5600, f9100000), \ | |
9244 | X(_ldrsh, 5e00, f9300000), \ | |
9245 | X(_ldr_pc,4800, f85f0000), \ | |
9246 | X(_ldr_pc2,4800, f85f0000), \ | |
9247 | X(_ldr_sp,9800, f85d0000), \ | |
9248 | X(_lsl, 0000, fa00f000), \ | |
9249 | X(_lsls, 0000, fa10f000), \ | |
9250 | X(_lsr, 0800, fa20f000), \ | |
9251 | X(_lsrs, 0800, fa30f000), \ | |
9252 | X(_mov, 2000, ea4f0000), \ | |
9253 | X(_movs, 2000, ea5f0000), \ | |
9254 | X(_mul, 4340, fb00f000), \ | |
9255 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
9256 | X(_mvn, 43c0, ea6f0000), \ | |
9257 | X(_mvns, 43c0, ea7f0000), \ | |
9258 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
9259 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
9260 | X(_orr, 4300, ea400000), \ | |
9261 | X(_orrs, 4300, ea500000), \ | |
9262 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
9263 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
9264 | X(_rev, ba00, fa90f080), \ | |
9265 | X(_rev16, ba40, fa90f090), \ | |
9266 | X(_revsh, bac0, fa90f0b0), \ | |
9267 | X(_ror, 41c0, fa60f000), \ | |
9268 | X(_rors, 41c0, fa70f000), \ | |
9269 | X(_sbc, 4180, eb600000), \ | |
9270 | X(_sbcs, 4180, eb700000), \ | |
9271 | X(_stmia, c000, e8800000), \ | |
9272 | X(_str, 6000, f8400000), \ | |
9273 | X(_strb, 7000, f8000000), \ | |
9274 | X(_strh, 8000, f8200000), \ | |
9275 | X(_str_sp,9000, f84d0000), \ | |
9276 | X(_sub, 1e00, eba00000), \ | |
9277 | X(_subs, 1e00, ebb00000), \ | |
9278 | X(_subi, 8000, f1a00000), \ | |
9279 | X(_subis, 8000, f1b00000), \ | |
9280 | X(_sxtb, b240, fa4ff080), \ | |
9281 | X(_sxth, b200, fa0ff080), \ | |
9282 | X(_tst, 4200, ea100f00), \ | |
9283 | X(_uxtb, b2c0, fa5ff080), \ | |
9284 | X(_uxth, b280, fa1ff080), \ | |
9285 | X(_nop, bf00, f3af8000), \ | |
9286 | X(_yield, bf10, f3af8001), \ | |
9287 | X(_wfe, bf20, f3af8002), \ | |
9288 | X(_wfi, bf30, f3af8003), \ | |
9289 | X(_sev, bf40, f3af8004), | |
c19d1205 ZW |
9290 | |
9291 | /* To catch errors in encoding functions, the codes are all offset by | |
9292 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
9293 | as 16-bit instructions. */ | |
21d799b5 | 9294 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
9295 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
9296 | #undef X | |
9297 | ||
9298 | #define X(a,b,c) 0x##b | |
9299 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
9300 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
9301 | #undef X | |
9302 | ||
9303 | #define X(a,b,c) 0x##c | |
9304 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
9305 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
9306 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
9307 | #undef X |
9308 | #undef T16_32_TAB | |
9309 | ||
9310 | /* Thumb instruction encoders, in alphabetical order. */ | |
9311 | ||
92e90b6e | 9312 | /* ADDW or SUBW. */ |
c921be7d | 9313 | |
92e90b6e PB |
9314 | static void |
9315 | do_t_add_sub_w (void) | |
9316 | { | |
9317 | int Rd, Rn; | |
9318 | ||
9319 | Rd = inst.operands[0].reg; | |
9320 | Rn = inst.operands[1].reg; | |
9321 | ||
539d4391 NC |
9322 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
9323 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
9324 | if (Rn == REG_SP) | |
9325 | constraint (Rd == REG_PC, BAD_PC); | |
9326 | else | |
9327 | reject_bad_reg (Rd); | |
fdfde340 | 9328 | |
92e90b6e PB |
9329 | inst.instruction |= (Rn << 16) | (Rd << 8); |
9330 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9331 | } | |
9332 | ||
c19d1205 ZW |
9333 | /* Parse an add or subtract instruction. We get here with inst.instruction |
9334 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
9335 | ||
9336 | static void | |
9337 | do_t_add_sub (void) | |
9338 | { | |
9339 | int Rd, Rs, Rn; | |
9340 | ||
9341 | Rd = inst.operands[0].reg; | |
9342 | Rs = (inst.operands[1].present | |
9343 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9344 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9345 | ||
e07e6e58 NC |
9346 | if (Rd == REG_PC) |
9347 | set_it_insn_type_last (); | |
9348 | ||
c19d1205 ZW |
9349 | if (unified_syntax) |
9350 | { | |
0110f2b8 PB |
9351 | bfd_boolean flags; |
9352 | bfd_boolean narrow; | |
9353 | int opcode; | |
9354 | ||
9355 | flags = (inst.instruction == T_MNEM_adds | |
9356 | || inst.instruction == T_MNEM_subs); | |
9357 | if (flags) | |
e07e6e58 | 9358 | narrow = !in_it_block (); |
0110f2b8 | 9359 | else |
e07e6e58 | 9360 | narrow = in_it_block (); |
c19d1205 | 9361 | if (!inst.operands[2].isreg) |
b99bd4ef | 9362 | { |
16805f35 PB |
9363 | int add; |
9364 | ||
fdfde340 JM |
9365 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
9366 | ||
16805f35 PB |
9367 | add = (inst.instruction == T_MNEM_add |
9368 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
9369 | opcode = 0; |
9370 | if (inst.size_req != 4) | |
9371 | { | |
0110f2b8 PB |
9372 | /* Attempt to use a narrow opcode, with relaxation if |
9373 | appropriate. */ | |
9374 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
9375 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
9376 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
9377 | opcode = T_MNEM_add_sp; | |
9378 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
9379 | opcode = T_MNEM_add_pc; | |
9380 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
9381 | { | |
9382 | if (flags) | |
9383 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
9384 | else | |
9385 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
9386 | } | |
9387 | if (opcode) | |
9388 | { | |
9389 | inst.instruction = THUMB_OP16(opcode); | |
9390 | inst.instruction |= (Rd << 4) | Rs; | |
9391 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9392 | if (inst.size_req != 2) | |
9393 | inst.relax = opcode; | |
9394 | } | |
9395 | else | |
9396 | constraint (inst.size_req == 2, BAD_HIREG); | |
9397 | } | |
9398 | if (inst.size_req == 4 | |
9399 | || (inst.size_req != 2 && !opcode)) | |
9400 | { | |
efd81785 PB |
9401 | if (Rd == REG_PC) |
9402 | { | |
fdfde340 | 9403 | constraint (add, BAD_PC); |
efd81785 PB |
9404 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
9405 | _("only SUBS PC, LR, #const allowed")); | |
9406 | constraint (inst.reloc.exp.X_op != O_constant, | |
9407 | _("expression too complex")); | |
9408 | constraint (inst.reloc.exp.X_add_number < 0 | |
9409 | || inst.reloc.exp.X_add_number > 0xff, | |
9410 | _("immediate value out of range")); | |
9411 | inst.instruction = T2_SUBS_PC_LR | |
9412 | | inst.reloc.exp.X_add_number; | |
9413 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9414 | return; | |
9415 | } | |
9416 | else if (Rs == REG_PC) | |
16805f35 PB |
9417 | { |
9418 | /* Always use addw/subw. */ | |
9419 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
9420 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9421 | } | |
9422 | else | |
9423 | { | |
9424 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9425 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
9426 | | 0x10000000; | |
9427 | if (flags) | |
9428 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9429 | else | |
9430 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
9431 | } | |
dc4503c6 PB |
9432 | inst.instruction |= Rd << 8; |
9433 | inst.instruction |= Rs << 16; | |
0110f2b8 | 9434 | } |
b99bd4ef | 9435 | } |
c19d1205 ZW |
9436 | else |
9437 | { | |
9438 | Rn = inst.operands[2].reg; | |
9439 | /* See if we can do this with a 16-bit instruction. */ | |
9440 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
9441 | { | |
e27ec89e PB |
9442 | if (Rd > 7 || Rs > 7 || Rn > 7) |
9443 | narrow = FALSE; | |
9444 | ||
9445 | if (narrow) | |
c19d1205 | 9446 | { |
e27ec89e PB |
9447 | inst.instruction = ((inst.instruction == T_MNEM_adds |
9448 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
9449 | ? T_OPCODE_ADD_R3 |
9450 | : T_OPCODE_SUB_R3); | |
9451 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
9452 | return; | |
9453 | } | |
b99bd4ef | 9454 | |
7e806470 | 9455 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 9456 | { |
7e806470 PB |
9457 | /* Thumb-1 cores (except v6-M) require at least one high |
9458 | register in a narrow non flag setting add. */ | |
9459 | if (Rd > 7 || Rn > 7 | |
9460 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
9461 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 9462 | { |
7e806470 PB |
9463 | if (Rd == Rn) |
9464 | { | |
9465 | Rn = Rs; | |
9466 | Rs = Rd; | |
9467 | } | |
c19d1205 ZW |
9468 | inst.instruction = T_OPCODE_ADD_HI; |
9469 | inst.instruction |= (Rd & 8) << 4; | |
9470 | inst.instruction |= (Rd & 7); | |
9471 | inst.instruction |= Rn << 3; | |
9472 | return; | |
9473 | } | |
c19d1205 ZW |
9474 | } |
9475 | } | |
c921be7d | 9476 | |
fdfde340 JM |
9477 | constraint (Rd == REG_PC, BAD_PC); |
9478 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
9479 | constraint (Rs == REG_PC, BAD_PC); | |
9480 | reject_bad_reg (Rn); | |
9481 | ||
c19d1205 ZW |
9482 | /* If we get here, it can't be done in 16 bits. */ |
9483 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
9484 | _("shift must be constant")); | |
9485 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9486 | inst.instruction |= Rd << 8; | |
9487 | inst.instruction |= Rs << 16; | |
9488 | encode_thumb32_shifted_operand (2); | |
9489 | } | |
9490 | } | |
9491 | else | |
9492 | { | |
9493 | constraint (inst.instruction == T_MNEM_adds | |
9494 | || inst.instruction == T_MNEM_subs, | |
9495 | BAD_THUMB32); | |
b99bd4ef | 9496 | |
c19d1205 | 9497 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 9498 | { |
c19d1205 ZW |
9499 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
9500 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
9501 | BAD_HIREG); | |
9502 | ||
9503 | inst.instruction = (inst.instruction == T_MNEM_add | |
9504 | ? 0x0000 : 0x8000); | |
9505 | inst.instruction |= (Rd << 4) | Rs; | |
9506 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
9507 | return; |
9508 | } | |
9509 | ||
c19d1205 ZW |
9510 | Rn = inst.operands[2].reg; |
9511 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 9512 | |
c19d1205 ZW |
9513 | /* We now have Rd, Rs, and Rn set to registers. */ |
9514 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 9515 | { |
c19d1205 ZW |
9516 | /* Can't do this for SUB. */ |
9517 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
9518 | inst.instruction = T_OPCODE_ADD_HI; | |
9519 | inst.instruction |= (Rd & 8) << 4; | |
9520 | inst.instruction |= (Rd & 7); | |
9521 | if (Rs == Rd) | |
9522 | inst.instruction |= Rn << 3; | |
9523 | else if (Rn == Rd) | |
9524 | inst.instruction |= Rs << 3; | |
9525 | else | |
9526 | constraint (1, _("dest must overlap one source register")); | |
9527 | } | |
9528 | else | |
9529 | { | |
9530 | inst.instruction = (inst.instruction == T_MNEM_add | |
9531 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
9532 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 9533 | } |
b99bd4ef | 9534 | } |
b99bd4ef NC |
9535 | } |
9536 | ||
c19d1205 ZW |
9537 | static void |
9538 | do_t_adr (void) | |
9539 | { | |
fdfde340 JM |
9540 | unsigned Rd; |
9541 | ||
9542 | Rd = inst.operands[0].reg; | |
9543 | reject_bad_reg (Rd); | |
9544 | ||
9545 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
9546 | { |
9547 | /* Defer to section relaxation. */ | |
9548 | inst.relax = inst.instruction; | |
9549 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 9550 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
9551 | } |
9552 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 9553 | { |
0110f2b8 | 9554 | /* Generate a 32-bit opcode. */ |
e9f89963 | 9555 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 9556 | inst.instruction |= Rd << 8; |
e9f89963 PB |
9557 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
9558 | inst.reloc.pc_rel = 1; | |
9559 | } | |
9560 | else | |
9561 | { | |
0110f2b8 | 9562 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
9563 | inst.instruction = THUMB_OP16 (inst.instruction); |
9564 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9565 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
9566 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 9567 | |
fdfde340 | 9568 | inst.instruction |= Rd << 4; |
e9f89963 | 9569 | } |
c19d1205 | 9570 | } |
b99bd4ef | 9571 | |
c19d1205 ZW |
9572 | /* Arithmetic instructions for which there is just one 16-bit |
9573 | instruction encoding, and it allows only two low registers. | |
9574 | For maximal compatibility with ARM syntax, we allow three register | |
9575 | operands even when Thumb-32 instructions are not available, as long | |
9576 | as the first two are identical. For instance, both "sbc r0,r1" and | |
9577 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 9578 | static void |
c19d1205 | 9579 | do_t_arit3 (void) |
b99bd4ef | 9580 | { |
c19d1205 | 9581 | int Rd, Rs, Rn; |
b99bd4ef | 9582 | |
c19d1205 ZW |
9583 | Rd = inst.operands[0].reg; |
9584 | Rs = (inst.operands[1].present | |
9585 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9586 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9587 | Rn = inst.operands[2].reg; | |
b99bd4ef | 9588 | |
fdfde340 JM |
9589 | reject_bad_reg (Rd); |
9590 | reject_bad_reg (Rs); | |
9591 | if (inst.operands[2].isreg) | |
9592 | reject_bad_reg (Rn); | |
9593 | ||
c19d1205 | 9594 | if (unified_syntax) |
b99bd4ef | 9595 | { |
c19d1205 ZW |
9596 | if (!inst.operands[2].isreg) |
9597 | { | |
9598 | /* For an immediate, we always generate a 32-bit opcode; | |
9599 | section relaxation will shrink it later if possible. */ | |
9600 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9601 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9602 | inst.instruction |= Rd << 8; | |
9603 | inst.instruction |= Rs << 16; | |
9604 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9605 | } | |
9606 | else | |
9607 | { | |
e27ec89e PB |
9608 | bfd_boolean narrow; |
9609 | ||
c19d1205 | 9610 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9611 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9612 | narrow = !in_it_block (); |
e27ec89e | 9613 | else |
e07e6e58 | 9614 | narrow = in_it_block (); |
e27ec89e PB |
9615 | |
9616 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9617 | narrow = FALSE; | |
9618 | if (inst.operands[2].shifted) | |
9619 | narrow = FALSE; | |
9620 | if (inst.size_req == 4) | |
9621 | narrow = FALSE; | |
9622 | ||
9623 | if (narrow | |
c19d1205 ZW |
9624 | && Rd == Rs) |
9625 | { | |
9626 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9627 | inst.instruction |= Rd; | |
9628 | inst.instruction |= Rn << 3; | |
9629 | return; | |
9630 | } | |
b99bd4ef | 9631 | |
c19d1205 ZW |
9632 | /* If we get here, it can't be done in 16 bits. */ |
9633 | constraint (inst.operands[2].shifted | |
9634 | && inst.operands[2].immisreg, | |
9635 | _("shift must be constant")); | |
9636 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9637 | inst.instruction |= Rd << 8; | |
9638 | inst.instruction |= Rs << 16; | |
9639 | encode_thumb32_shifted_operand (2); | |
9640 | } | |
a737bd4d | 9641 | } |
c19d1205 | 9642 | else |
b99bd4ef | 9643 | { |
c19d1205 ZW |
9644 | /* On its face this is a lie - the instruction does set the |
9645 | flags. However, the only supported mnemonic in this mode | |
9646 | says it doesn't. */ | |
9647 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9648 | |
c19d1205 ZW |
9649 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9650 | _("unshifted register required")); | |
9651 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9652 | constraint (Rd != Rs, | |
9653 | _("dest and source1 must be the same register")); | |
a737bd4d | 9654 | |
c19d1205 ZW |
9655 | inst.instruction = THUMB_OP16 (inst.instruction); |
9656 | inst.instruction |= Rd; | |
9657 | inst.instruction |= Rn << 3; | |
b99bd4ef | 9658 | } |
a737bd4d | 9659 | } |
b99bd4ef | 9660 | |
c19d1205 ZW |
9661 | /* Similarly, but for instructions where the arithmetic operation is |
9662 | commutative, so we can allow either of them to be different from | |
9663 | the destination operand in a 16-bit instruction. For instance, all | |
9664 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
9665 | accepted. */ | |
9666 | static void | |
9667 | do_t_arit3c (void) | |
a737bd4d | 9668 | { |
c19d1205 | 9669 | int Rd, Rs, Rn; |
b99bd4ef | 9670 | |
c19d1205 ZW |
9671 | Rd = inst.operands[0].reg; |
9672 | Rs = (inst.operands[1].present | |
9673 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9674 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9675 | Rn = inst.operands[2].reg; | |
c921be7d | 9676 | |
fdfde340 JM |
9677 | reject_bad_reg (Rd); |
9678 | reject_bad_reg (Rs); | |
9679 | if (inst.operands[2].isreg) | |
9680 | reject_bad_reg (Rn); | |
a737bd4d | 9681 | |
c19d1205 | 9682 | if (unified_syntax) |
a737bd4d | 9683 | { |
c19d1205 | 9684 | if (!inst.operands[2].isreg) |
b99bd4ef | 9685 | { |
c19d1205 ZW |
9686 | /* For an immediate, we always generate a 32-bit opcode; |
9687 | section relaxation will shrink it later if possible. */ | |
9688 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9689 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9690 | inst.instruction |= Rd << 8; | |
9691 | inst.instruction |= Rs << 16; | |
9692 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 9693 | } |
c19d1205 | 9694 | else |
a737bd4d | 9695 | { |
e27ec89e PB |
9696 | bfd_boolean narrow; |
9697 | ||
c19d1205 | 9698 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9699 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9700 | narrow = !in_it_block (); |
e27ec89e | 9701 | else |
e07e6e58 | 9702 | narrow = in_it_block (); |
e27ec89e PB |
9703 | |
9704 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9705 | narrow = FALSE; | |
9706 | if (inst.operands[2].shifted) | |
9707 | narrow = FALSE; | |
9708 | if (inst.size_req == 4) | |
9709 | narrow = FALSE; | |
9710 | ||
9711 | if (narrow) | |
a737bd4d | 9712 | { |
c19d1205 | 9713 | if (Rd == Rs) |
a737bd4d | 9714 | { |
c19d1205 ZW |
9715 | inst.instruction = THUMB_OP16 (inst.instruction); |
9716 | inst.instruction |= Rd; | |
9717 | inst.instruction |= Rn << 3; | |
9718 | return; | |
a737bd4d | 9719 | } |
c19d1205 | 9720 | if (Rd == Rn) |
a737bd4d | 9721 | { |
c19d1205 ZW |
9722 | inst.instruction = THUMB_OP16 (inst.instruction); |
9723 | inst.instruction |= Rd; | |
9724 | inst.instruction |= Rs << 3; | |
9725 | return; | |
a737bd4d NC |
9726 | } |
9727 | } | |
c19d1205 ZW |
9728 | |
9729 | /* If we get here, it can't be done in 16 bits. */ | |
9730 | constraint (inst.operands[2].shifted | |
9731 | && inst.operands[2].immisreg, | |
9732 | _("shift must be constant")); | |
9733 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9734 | inst.instruction |= Rd << 8; | |
9735 | inst.instruction |= Rs << 16; | |
9736 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 9737 | } |
b99bd4ef | 9738 | } |
c19d1205 ZW |
9739 | else |
9740 | { | |
9741 | /* On its face this is a lie - the instruction does set the | |
9742 | flags. However, the only supported mnemonic in this mode | |
9743 | says it doesn't. */ | |
9744 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9745 | |
c19d1205 ZW |
9746 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9747 | _("unshifted register required")); | |
9748 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9749 | ||
9750 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9751 | inst.instruction |= Rd; | |
9752 | ||
9753 | if (Rd == Rs) | |
9754 | inst.instruction |= Rn << 3; | |
9755 | else if (Rd == Rn) | |
9756 | inst.instruction |= Rs << 3; | |
9757 | else | |
9758 | constraint (1, _("dest must overlap one source register")); | |
9759 | } | |
a737bd4d NC |
9760 | } |
9761 | ||
62b3e311 PB |
9762 | static void |
9763 | do_t_barrier (void) | |
9764 | { | |
9765 | if (inst.operands[0].present) | |
9766 | { | |
9767 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
9768 | && inst.operands[0].imm > 0xf |
9769 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 9770 | _("bad barrier type")); |
62b3e311 PB |
9771 | inst.instruction |= inst.operands[0].imm; |
9772 | } | |
9773 | else | |
9774 | inst.instruction |= 0xf; | |
9775 | } | |
9776 | ||
c19d1205 ZW |
9777 | static void |
9778 | do_t_bfc (void) | |
a737bd4d | 9779 | { |
fdfde340 | 9780 | unsigned Rd; |
c19d1205 ZW |
9781 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
9782 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9783 | /* The instruction encoding stores the LSB and MSB, | |
9784 | not the LSB and width. */ | |
fdfde340 JM |
9785 | Rd = inst.operands[0].reg; |
9786 | reject_bad_reg (Rd); | |
9787 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
9788 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
9789 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
9790 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9791 | } |
9792 | ||
c19d1205 ZW |
9793 | static void |
9794 | do_t_bfi (void) | |
b99bd4ef | 9795 | { |
fdfde340 | 9796 | int Rd, Rn; |
c19d1205 | 9797 | unsigned int msb; |
b99bd4ef | 9798 | |
fdfde340 JM |
9799 | Rd = inst.operands[0].reg; |
9800 | reject_bad_reg (Rd); | |
9801 | ||
c19d1205 ZW |
9802 | /* #0 in second position is alternative syntax for bfc, which is |
9803 | the same instruction but with REG_PC in the Rm field. */ | |
9804 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
9805 | Rn = REG_PC; |
9806 | else | |
9807 | { | |
9808 | Rn = inst.operands[1].reg; | |
9809 | reject_bad_reg (Rn); | |
9810 | } | |
b99bd4ef | 9811 | |
c19d1205 ZW |
9812 | msb = inst.operands[2].imm + inst.operands[3].imm; |
9813 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9814 | /* The instruction encoding stores the LSB and MSB, | |
9815 | not the LSB and width. */ | |
fdfde340 JM |
9816 | inst.instruction |= Rd << 8; |
9817 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9818 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9819 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9820 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9821 | } |
9822 | ||
c19d1205 ZW |
9823 | static void |
9824 | do_t_bfx (void) | |
b99bd4ef | 9825 | { |
fdfde340 JM |
9826 | unsigned Rd, Rn; |
9827 | ||
9828 | Rd = inst.operands[0].reg; | |
9829 | Rn = inst.operands[1].reg; | |
9830 | ||
9831 | reject_bad_reg (Rd); | |
9832 | reject_bad_reg (Rn); | |
9833 | ||
c19d1205 ZW |
9834 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
9835 | _("bit-field extends past end of register")); | |
fdfde340 JM |
9836 | inst.instruction |= Rd << 8; |
9837 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9838 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9839 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9840 | inst.instruction |= inst.operands[3].imm - 1; | |
9841 | } | |
b99bd4ef | 9842 | |
c19d1205 ZW |
9843 | /* ARM V5 Thumb BLX (argument parse) |
9844 | BLX <target_addr> which is BLX(1) | |
9845 | BLX <Rm> which is BLX(2) | |
9846 | Unfortunately, there are two different opcodes for this mnemonic. | |
9847 | So, the insns[].value is not used, and the code here zaps values | |
9848 | into inst.instruction. | |
b99bd4ef | 9849 | |
c19d1205 ZW |
9850 | ??? How to take advantage of the additional two bits of displacement |
9851 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 9852 | |
c19d1205 ZW |
9853 | static void |
9854 | do_t_blx (void) | |
9855 | { | |
e07e6e58 NC |
9856 | set_it_insn_type_last (); |
9857 | ||
c19d1205 | 9858 | if (inst.operands[0].isreg) |
fdfde340 JM |
9859 | { |
9860 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
9861 | /* We have a register, so this is BLX(2). */ | |
9862 | inst.instruction |= inst.operands[0].reg << 3; | |
9863 | } | |
b99bd4ef NC |
9864 | else |
9865 | { | |
c19d1205 | 9866 | /* No register. This must be BLX(1). */ |
2fc8bdac | 9867 | inst.instruction = 0xf000e800; |
0855e32b | 9868 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
9869 | } |
9870 | } | |
9871 | ||
c19d1205 ZW |
9872 | static void |
9873 | do_t_branch (void) | |
b99bd4ef | 9874 | { |
0110f2b8 | 9875 | int opcode; |
dfa9f0d5 | 9876 | int cond; |
9ae92b05 | 9877 | int reloc; |
dfa9f0d5 | 9878 | |
e07e6e58 NC |
9879 | cond = inst.cond; |
9880 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
9881 | ||
9882 | if (in_it_block ()) | |
dfa9f0d5 PB |
9883 | { |
9884 | /* Conditional branches inside IT blocks are encoded as unconditional | |
9885 | branches. */ | |
9886 | cond = COND_ALWAYS; | |
dfa9f0d5 PB |
9887 | } |
9888 | else | |
9889 | cond = inst.cond; | |
9890 | ||
9891 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
9892 | opcode = T_MNEM_bcond; |
9893 | else | |
9894 | opcode = inst.instruction; | |
9895 | ||
12d6b0b7 RS |
9896 | if (unified_syntax |
9897 | && (inst.size_req == 4 | |
10960bfb PB |
9898 | || (inst.size_req != 2 |
9899 | && (inst.operands[0].hasreloc | |
9900 | || inst.reloc.exp.X_op == O_constant)))) | |
c19d1205 | 9901 | { |
0110f2b8 | 9902 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 9903 | if (cond == COND_ALWAYS) |
9ae92b05 | 9904 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
9905 | else |
9906 | { | |
9c2799c2 | 9907 | gas_assert (cond != 0xF); |
dfa9f0d5 | 9908 | inst.instruction |= cond << 22; |
9ae92b05 | 9909 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
9910 | } |
9911 | } | |
b99bd4ef NC |
9912 | else |
9913 | { | |
0110f2b8 | 9914 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 9915 | if (cond == COND_ALWAYS) |
9ae92b05 | 9916 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 9917 | else |
b99bd4ef | 9918 | { |
dfa9f0d5 | 9919 | inst.instruction |= cond << 8; |
9ae92b05 | 9920 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 9921 | } |
0110f2b8 PB |
9922 | /* Allow section relaxation. */ |
9923 | if (unified_syntax && inst.size_req != 2) | |
9924 | inst.relax = opcode; | |
b99bd4ef | 9925 | } |
9ae92b05 | 9926 | inst.reloc.type = reloc; |
c19d1205 | 9927 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
9928 | } |
9929 | ||
9930 | static void | |
c19d1205 | 9931 | do_t_bkpt (void) |
b99bd4ef | 9932 | { |
dfa9f0d5 PB |
9933 | constraint (inst.cond != COND_ALWAYS, |
9934 | _("instruction is always unconditional")); | |
c19d1205 | 9935 | if (inst.operands[0].present) |
b99bd4ef | 9936 | { |
c19d1205 ZW |
9937 | constraint (inst.operands[0].imm > 255, |
9938 | _("immediate value out of range")); | |
9939 | inst.instruction |= inst.operands[0].imm; | |
e07e6e58 | 9940 | set_it_insn_type (NEUTRAL_IT_INSN); |
b99bd4ef | 9941 | } |
b99bd4ef NC |
9942 | } |
9943 | ||
9944 | static void | |
c19d1205 | 9945 | do_t_branch23 (void) |
b99bd4ef | 9946 | { |
e07e6e58 | 9947 | set_it_insn_type_last (); |
0855e32b NS |
9948 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
9949 | ||
9950 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in | |
9951 | this file. We used to simply ignore the PLT reloc type here -- | |
9952 | the branch encoding is now needed to deal with TLSCALL relocs. | |
9953 | So if we see a PLT reloc now, put it back to how it used to be to | |
9954 | keep the preexisting behaviour. */ | |
9955 | if (inst.reloc.type == BFD_RELOC_ARM_PLT32) | |
9956 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 9957 | |
4343666d | 9958 | #if defined(OBJ_COFF) |
c19d1205 ZW |
9959 | /* If the destination of the branch is a defined symbol which does not have |
9960 | the THUMB_FUNC attribute, then we must be calling a function which has | |
9961 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
9962 | function and change the branch to refer to that function instead. */ | |
9963 | if ( inst.reloc.exp.X_op == O_symbol | |
9964 | && inst.reloc.exp.X_add_symbol != NULL | |
9965 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
9966 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
9967 | inst.reloc.exp.X_add_symbol = | |
9968 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 9969 | #endif |
90e4755a RE |
9970 | } |
9971 | ||
9972 | static void | |
c19d1205 | 9973 | do_t_bx (void) |
90e4755a | 9974 | { |
e07e6e58 | 9975 | set_it_insn_type_last (); |
c19d1205 ZW |
9976 | inst.instruction |= inst.operands[0].reg << 3; |
9977 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
9978 | should cause the alignment to be checked once it is known. This is | |
9979 | because BX PC only works if the instruction is word aligned. */ | |
9980 | } | |
90e4755a | 9981 | |
c19d1205 ZW |
9982 | static void |
9983 | do_t_bxj (void) | |
9984 | { | |
fdfde340 | 9985 | int Rm; |
90e4755a | 9986 | |
e07e6e58 | 9987 | set_it_insn_type_last (); |
fdfde340 JM |
9988 | Rm = inst.operands[0].reg; |
9989 | reject_bad_reg (Rm); | |
9990 | inst.instruction |= Rm << 16; | |
90e4755a RE |
9991 | } |
9992 | ||
9993 | static void | |
c19d1205 | 9994 | do_t_clz (void) |
90e4755a | 9995 | { |
fdfde340 JM |
9996 | unsigned Rd; |
9997 | unsigned Rm; | |
9998 | ||
9999 | Rd = inst.operands[0].reg; | |
10000 | Rm = inst.operands[1].reg; | |
10001 | ||
10002 | reject_bad_reg (Rd); | |
10003 | reject_bad_reg (Rm); | |
10004 | ||
10005 | inst.instruction |= Rd << 8; | |
10006 | inst.instruction |= Rm << 16; | |
10007 | inst.instruction |= Rm; | |
c19d1205 | 10008 | } |
90e4755a | 10009 | |
dfa9f0d5 PB |
10010 | static void |
10011 | do_t_cps (void) | |
10012 | { | |
e07e6e58 | 10013 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
10014 | inst.instruction |= inst.operands[0].imm; |
10015 | } | |
10016 | ||
c19d1205 ZW |
10017 | static void |
10018 | do_t_cpsi (void) | |
10019 | { | |
e07e6e58 | 10020 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 10021 | if (unified_syntax |
62b3e311 PB |
10022 | && (inst.operands[1].present || inst.size_req == 4) |
10023 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 10024 | { |
c19d1205 ZW |
10025 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
10026 | inst.instruction = 0xf3af8000; | |
10027 | inst.instruction |= imod << 9; | |
10028 | inst.instruction |= inst.operands[0].imm << 5; | |
10029 | if (inst.operands[1].present) | |
10030 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 10031 | } |
c19d1205 | 10032 | else |
90e4755a | 10033 | { |
62b3e311 PB |
10034 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
10035 | && (inst.operands[0].imm & 4), | |
10036 | _("selected processor does not support 'A' form " | |
10037 | "of this instruction")); | |
10038 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
10039 | _("Thumb does not support the 2-argument " |
10040 | "form of this instruction")); | |
10041 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 10042 | } |
90e4755a RE |
10043 | } |
10044 | ||
c19d1205 ZW |
10045 | /* THUMB CPY instruction (argument parse). */ |
10046 | ||
90e4755a | 10047 | static void |
c19d1205 | 10048 | do_t_cpy (void) |
90e4755a | 10049 | { |
c19d1205 | 10050 | if (inst.size_req == 4) |
90e4755a | 10051 | { |
c19d1205 ZW |
10052 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
10053 | inst.instruction |= inst.operands[0].reg << 8; | |
10054 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 10055 | } |
c19d1205 | 10056 | else |
90e4755a | 10057 | { |
c19d1205 ZW |
10058 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
10059 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
10060 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 10061 | } |
90e4755a RE |
10062 | } |
10063 | ||
90e4755a | 10064 | static void |
25fe350b | 10065 | do_t_cbz (void) |
90e4755a | 10066 | { |
e07e6e58 | 10067 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
10068 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10069 | inst.instruction |= inst.operands[0].reg; | |
10070 | inst.reloc.pc_rel = 1; | |
10071 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
10072 | } | |
90e4755a | 10073 | |
62b3e311 PB |
10074 | static void |
10075 | do_t_dbg (void) | |
10076 | { | |
10077 | inst.instruction |= inst.operands[0].imm; | |
10078 | } | |
10079 | ||
10080 | static void | |
10081 | do_t_div (void) | |
10082 | { | |
fdfde340 JM |
10083 | unsigned Rd, Rn, Rm; |
10084 | ||
10085 | Rd = inst.operands[0].reg; | |
10086 | Rn = (inst.operands[1].present | |
10087 | ? inst.operands[1].reg : Rd); | |
10088 | Rm = inst.operands[2].reg; | |
10089 | ||
10090 | reject_bad_reg (Rd); | |
10091 | reject_bad_reg (Rn); | |
10092 | reject_bad_reg (Rm); | |
10093 | ||
10094 | inst.instruction |= Rd << 8; | |
10095 | inst.instruction |= Rn << 16; | |
10096 | inst.instruction |= Rm; | |
62b3e311 PB |
10097 | } |
10098 | ||
c19d1205 ZW |
10099 | static void |
10100 | do_t_hint (void) | |
10101 | { | |
10102 | if (unified_syntax && inst.size_req == 4) | |
10103 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10104 | else | |
10105 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10106 | } | |
90e4755a | 10107 | |
c19d1205 ZW |
10108 | static void |
10109 | do_t_it (void) | |
10110 | { | |
10111 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 10112 | |
e07e6e58 NC |
10113 | set_it_insn_type (IT_INSN); |
10114 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
10115 | now_it.cc = cond; | |
e27ec89e PB |
10116 | |
10117 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 10118 | if ((cond & 0x1) == 0x0) |
90e4755a | 10119 | { |
c19d1205 | 10120 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 10121 | |
c19d1205 ZW |
10122 | if ((mask & 0x7) == 0) |
10123 | /* no conversion needed */; | |
10124 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
10125 | mask ^= 0x8; |
10126 | else if ((mask & 0x1) == 0) | |
10127 | mask ^= 0xC; | |
c19d1205 | 10128 | else |
e27ec89e | 10129 | mask ^= 0xE; |
90e4755a | 10130 | |
e27ec89e PB |
10131 | inst.instruction &= 0xfff0; |
10132 | inst.instruction |= mask; | |
c19d1205 | 10133 | } |
90e4755a | 10134 | |
c19d1205 ZW |
10135 | inst.instruction |= cond << 4; |
10136 | } | |
90e4755a | 10137 | |
3c707909 PB |
10138 | /* Helper function used for both push/pop and ldm/stm. */ |
10139 | static void | |
10140 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
10141 | { | |
10142 | bfd_boolean load; | |
10143 | ||
10144 | load = (inst.instruction & (1 << 20)) != 0; | |
10145 | ||
10146 | if (mask & (1 << 13)) | |
10147 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
10148 | |
10149 | if ((mask & (1 << base)) != 0 | |
10150 | && writeback) | |
10151 | inst.error = _("having the base register in the register list when " | |
10152 | "using write back is UNPREDICTABLE"); | |
10153 | ||
3c707909 PB |
10154 | if (load) |
10155 | { | |
e07e6e58 NC |
10156 | if (mask & (1 << 15)) |
10157 | { | |
10158 | if (mask & (1 << 14)) | |
10159 | inst.error = _("LR and PC should not both be in register list"); | |
10160 | else | |
10161 | set_it_insn_type_last (); | |
10162 | } | |
3c707909 PB |
10163 | } |
10164 | else | |
10165 | { | |
10166 | if (mask & (1 << 15)) | |
10167 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
10168 | } |
10169 | ||
10170 | if ((mask & (mask - 1)) == 0) | |
10171 | { | |
10172 | /* Single register transfers implemented as str/ldr. */ | |
10173 | if (writeback) | |
10174 | { | |
10175 | if (inst.instruction & (1 << 23)) | |
10176 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
10177 | else | |
10178 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
10179 | } | |
10180 | else | |
10181 | { | |
10182 | if (inst.instruction & (1 << 23)) | |
10183 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
10184 | else | |
10185 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
10186 | } | |
10187 | ||
10188 | inst.instruction |= 0xf8400000; | |
10189 | if (load) | |
10190 | inst.instruction |= 0x00100000; | |
10191 | ||
5f4273c7 | 10192 | mask = ffs (mask) - 1; |
3c707909 PB |
10193 | mask <<= 12; |
10194 | } | |
10195 | else if (writeback) | |
10196 | inst.instruction |= WRITE_BACK; | |
10197 | ||
10198 | inst.instruction |= mask; | |
10199 | inst.instruction |= base << 16; | |
10200 | } | |
10201 | ||
c19d1205 ZW |
10202 | static void |
10203 | do_t_ldmstm (void) | |
10204 | { | |
10205 | /* This really doesn't seem worth it. */ | |
10206 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
10207 | _("expression too complex")); | |
10208 | constraint (inst.operands[1].writeback, | |
10209 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 10210 | |
c19d1205 ZW |
10211 | if (unified_syntax) |
10212 | { | |
3c707909 PB |
10213 | bfd_boolean narrow; |
10214 | unsigned mask; | |
10215 | ||
10216 | narrow = FALSE; | |
c19d1205 ZW |
10217 | /* See if we can use a 16-bit instruction. */ |
10218 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
10219 | && inst.size_req != 4 | |
3c707909 | 10220 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 10221 | { |
3c707909 | 10222 | mask = 1 << inst.operands[0].reg; |
90e4755a | 10223 | |
eab4f823 | 10224 | if (inst.operands[0].reg <= 7) |
90e4755a | 10225 | { |
3c707909 | 10226 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
10227 | ? inst.operands[0].writeback |
10228 | : (inst.operands[0].writeback | |
10229 | == !(inst.operands[1].imm & mask))) | |
10230 | { | |
10231 | if (inst.instruction == T_MNEM_stmia | |
10232 | && (inst.operands[1].imm & mask) | |
10233 | && (inst.operands[1].imm & (mask - 1))) | |
10234 | as_warn (_("value stored for r%d is UNKNOWN"), | |
10235 | inst.operands[0].reg); | |
3c707909 | 10236 | |
eab4f823 MGD |
10237 | inst.instruction = THUMB_OP16 (inst.instruction); |
10238 | inst.instruction |= inst.operands[0].reg << 8; | |
10239 | inst.instruction |= inst.operands[1].imm; | |
10240 | narrow = TRUE; | |
10241 | } | |
10242 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
10243 | { | |
10244 | /* This means 1 register in reg list one of 3 situations: | |
10245 | 1. Instruction is stmia, but without writeback. | |
10246 | 2. lmdia without writeback, but with Rn not in | |
10247 | reglist. | |
10248 | 3. ldmia with writeback, but with Rn in reglist. | |
10249 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
10250 | case 1 and 2 which can be converted into a 16-bit | |
10251 | str or ldr. The SP cases are handled below. */ | |
10252 | unsigned long opcode; | |
10253 | /* First, record an error for Case 3. */ | |
10254 | if (inst.operands[1].imm & mask | |
10255 | && inst.operands[0].writeback) | |
10256 | inst.error = | |
10257 | _("having the base register in the register list when " | |
10258 | "using write back is UNPREDICTABLE"); | |
10259 | ||
10260 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
10261 | : T_MNEM_ldr); | |
10262 | inst.instruction = THUMB_OP16 (opcode); | |
10263 | inst.instruction |= inst.operands[0].reg << 3; | |
10264 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
10265 | narrow = TRUE; | |
10266 | } | |
90e4755a | 10267 | } |
eab4f823 | 10268 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 10269 | { |
eab4f823 MGD |
10270 | if (inst.operands[0].writeback) |
10271 | { | |
10272 | inst.instruction = | |
10273 | THUMB_OP16 (inst.instruction == T_MNEM_stmia | |
10274 | ? T_MNEM_push : T_MNEM_pop); | |
10275 | inst.instruction |= inst.operands[1].imm; | |
10276 | narrow = TRUE; | |
10277 | } | |
10278 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
10279 | { | |
10280 | inst.instruction = | |
10281 | THUMB_OP16 (inst.instruction == T_MNEM_stmia | |
10282 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); | |
10283 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); | |
10284 | narrow = TRUE; | |
10285 | } | |
90e4755a | 10286 | } |
3c707909 PB |
10287 | } |
10288 | ||
10289 | if (!narrow) | |
10290 | { | |
c19d1205 ZW |
10291 | if (inst.instruction < 0xffff) |
10292 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 10293 | |
5f4273c7 NC |
10294 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
10295 | inst.operands[0].writeback); | |
90e4755a RE |
10296 | } |
10297 | } | |
c19d1205 | 10298 | else |
90e4755a | 10299 | { |
c19d1205 ZW |
10300 | constraint (inst.operands[0].reg > 7 |
10301 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
10302 | constraint (inst.instruction != T_MNEM_ldmia |
10303 | && inst.instruction != T_MNEM_stmia, | |
10304 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 10305 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 10306 | { |
c19d1205 ZW |
10307 | if (!inst.operands[0].writeback) |
10308 | as_warn (_("this instruction will write back the base register")); | |
10309 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
10310 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 10311 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 10312 | inst.operands[0].reg); |
f03698e6 | 10313 | } |
c19d1205 | 10314 | else |
90e4755a | 10315 | { |
c19d1205 ZW |
10316 | if (!inst.operands[0].writeback |
10317 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10318 | as_warn (_("this instruction will write back the base register")); | |
10319 | else if (inst.operands[0].writeback | |
10320 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10321 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
10322 | } |
10323 | ||
c19d1205 ZW |
10324 | inst.instruction = THUMB_OP16 (inst.instruction); |
10325 | inst.instruction |= inst.operands[0].reg << 8; | |
10326 | inst.instruction |= inst.operands[1].imm; | |
10327 | } | |
10328 | } | |
e28cd48c | 10329 | |
c19d1205 ZW |
10330 | static void |
10331 | do_t_ldrex (void) | |
10332 | { | |
10333 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
10334 | || inst.operands[1].postind || inst.operands[1].writeback | |
10335 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
10336 | || inst.operands[1].negative, | |
01cfc07f | 10337 | BAD_ADDR_MODE); |
e28cd48c | 10338 | |
5be8be5d DG |
10339 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
10340 | ||
c19d1205 ZW |
10341 | inst.instruction |= inst.operands[0].reg << 12; |
10342 | inst.instruction |= inst.operands[1].reg << 16; | |
10343 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
10344 | } | |
e28cd48c | 10345 | |
c19d1205 ZW |
10346 | static void |
10347 | do_t_ldrexd (void) | |
10348 | { | |
10349 | if (!inst.operands[1].present) | |
1cac9012 | 10350 | { |
c19d1205 ZW |
10351 | constraint (inst.operands[0].reg == REG_LR, |
10352 | _("r14 not allowed as first register " | |
10353 | "when second register is omitted")); | |
10354 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 10355 | } |
c19d1205 ZW |
10356 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
10357 | BAD_OVERLAP); | |
b99bd4ef | 10358 | |
c19d1205 ZW |
10359 | inst.instruction |= inst.operands[0].reg << 12; |
10360 | inst.instruction |= inst.operands[1].reg << 8; | |
10361 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10362 | } |
10363 | ||
10364 | static void | |
c19d1205 | 10365 | do_t_ldst (void) |
b99bd4ef | 10366 | { |
0110f2b8 PB |
10367 | unsigned long opcode; |
10368 | int Rn; | |
10369 | ||
e07e6e58 NC |
10370 | if (inst.operands[0].isreg |
10371 | && !inst.operands[0].preind | |
10372 | && inst.operands[0].reg == REG_PC) | |
10373 | set_it_insn_type_last (); | |
10374 | ||
0110f2b8 | 10375 | opcode = inst.instruction; |
c19d1205 | 10376 | if (unified_syntax) |
b99bd4ef | 10377 | { |
53365c0d PB |
10378 | if (!inst.operands[1].isreg) |
10379 | { | |
10380 | if (opcode <= 0xffff) | |
10381 | inst.instruction = THUMB_OP32 (opcode); | |
10382 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10383 | return; | |
10384 | } | |
0110f2b8 PB |
10385 | if (inst.operands[1].isreg |
10386 | && !inst.operands[1].writeback | |
c19d1205 ZW |
10387 | && !inst.operands[1].shifted && !inst.operands[1].postind |
10388 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
10389 | && opcode <= 0xffff |
10390 | && inst.size_req != 4) | |
c19d1205 | 10391 | { |
0110f2b8 PB |
10392 | /* Insn may have a 16-bit form. */ |
10393 | Rn = inst.operands[1].reg; | |
10394 | if (inst.operands[1].immisreg) | |
10395 | { | |
10396 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 10397 | /* [Rn, Rik] */ |
0110f2b8 PB |
10398 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
10399 | goto op16; | |
5be8be5d DG |
10400 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
10401 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
10402 | } |
10403 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
10404 | && opcode != T_MNEM_ldrsb) | |
10405 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
10406 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
10407 | { | |
10408 | /* [Rn, #const] */ | |
10409 | if (Rn > 7) | |
10410 | { | |
10411 | if (Rn == REG_PC) | |
10412 | { | |
10413 | if (inst.reloc.pc_rel) | |
10414 | opcode = T_MNEM_ldr_pc2; | |
10415 | else | |
10416 | opcode = T_MNEM_ldr_pc; | |
10417 | } | |
10418 | else | |
10419 | { | |
10420 | if (opcode == T_MNEM_ldr) | |
10421 | opcode = T_MNEM_ldr_sp; | |
10422 | else | |
10423 | opcode = T_MNEM_str_sp; | |
10424 | } | |
10425 | inst.instruction = inst.operands[0].reg << 8; | |
10426 | } | |
10427 | else | |
10428 | { | |
10429 | inst.instruction = inst.operands[0].reg; | |
10430 | inst.instruction |= inst.operands[1].reg << 3; | |
10431 | } | |
10432 | inst.instruction |= THUMB_OP16 (opcode); | |
10433 | if (inst.size_req == 2) | |
10434 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10435 | else | |
10436 | inst.relax = opcode; | |
10437 | return; | |
10438 | } | |
c19d1205 | 10439 | } |
0110f2b8 | 10440 | /* Definitely a 32-bit variant. */ |
5be8be5d | 10441 | |
8d67f500 NC |
10442 | /* Warning for Erratum 752419. */ |
10443 | if (opcode == T_MNEM_ldr | |
10444 | && inst.operands[0].reg == REG_SP | |
10445 | && inst.operands[1].writeback == 1 | |
10446 | && !inst.operands[1].immisreg) | |
10447 | { | |
10448 | if (no_cpu_selected () | |
10449 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
10450 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) | |
10451 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
10452 | as_warn (_("This instruction may be unpredictable " | |
10453 | "if executed on M-profile cores " | |
10454 | "with interrupts enabled.")); | |
10455 | } | |
10456 | ||
5be8be5d DG |
10457 | /* Do some validations regarding addressing modes. */ |
10458 | if (inst.operands[1].immisreg && opcode != T_MNEM_ldr | |
10459 | && opcode != T_MNEM_str) | |
10460 | reject_bad_reg (inst.operands[1].imm); | |
10461 | ||
0110f2b8 | 10462 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
10463 | inst.instruction |= inst.operands[0].reg << 12; |
10464 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
b99bd4ef NC |
10465 | return; |
10466 | } | |
10467 | ||
c19d1205 ZW |
10468 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10469 | ||
10470 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 10471 | { |
c19d1205 ZW |
10472 | /* Only [Rn,Rm] is acceptable. */ |
10473 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
10474 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
10475 | || inst.operands[1].postind || inst.operands[1].shifted | |
10476 | || inst.operands[1].negative, | |
10477 | _("Thumb does not support this addressing mode")); | |
10478 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10479 | goto op16; | |
b99bd4ef | 10480 | } |
5f4273c7 | 10481 | |
c19d1205 ZW |
10482 | inst.instruction = THUMB_OP16 (inst.instruction); |
10483 | if (!inst.operands[1].isreg) | |
10484 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10485 | return; | |
b99bd4ef | 10486 | |
c19d1205 ZW |
10487 | constraint (!inst.operands[1].preind |
10488 | || inst.operands[1].shifted | |
10489 | || inst.operands[1].writeback, | |
10490 | _("Thumb does not support this addressing mode")); | |
10491 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 10492 | { |
c19d1205 ZW |
10493 | constraint (inst.instruction & 0x0600, |
10494 | _("byte or halfword not valid for base register")); | |
10495 | constraint (inst.operands[1].reg == REG_PC | |
10496 | && !(inst.instruction & THUMB_LOAD_BIT), | |
10497 | _("r15 based store not allowed")); | |
10498 | constraint (inst.operands[1].immisreg, | |
10499 | _("invalid base register for register offset")); | |
b99bd4ef | 10500 | |
c19d1205 ZW |
10501 | if (inst.operands[1].reg == REG_PC) |
10502 | inst.instruction = T_OPCODE_LDR_PC; | |
10503 | else if (inst.instruction & THUMB_LOAD_BIT) | |
10504 | inst.instruction = T_OPCODE_LDR_SP; | |
10505 | else | |
10506 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 10507 | |
c19d1205 ZW |
10508 | inst.instruction |= inst.operands[0].reg << 8; |
10509 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10510 | return; | |
10511 | } | |
90e4755a | 10512 | |
c19d1205 ZW |
10513 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
10514 | if (!inst.operands[1].immisreg) | |
10515 | { | |
10516 | /* Immediate offset. */ | |
10517 | inst.instruction |= inst.operands[0].reg; | |
10518 | inst.instruction |= inst.operands[1].reg << 3; | |
10519 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10520 | return; | |
10521 | } | |
90e4755a | 10522 | |
c19d1205 ZW |
10523 | /* Register offset. */ |
10524 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
10525 | constraint (inst.operands[1].negative, | |
10526 | _("Thumb does not support this addressing mode")); | |
90e4755a | 10527 | |
c19d1205 ZW |
10528 | op16: |
10529 | switch (inst.instruction) | |
10530 | { | |
10531 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
10532 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
10533 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
10534 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
10535 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
10536 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
10537 | case 0x5600 /* ldrsb */: | |
10538 | case 0x5e00 /* ldrsh */: break; | |
10539 | default: abort (); | |
10540 | } | |
90e4755a | 10541 | |
c19d1205 ZW |
10542 | inst.instruction |= inst.operands[0].reg; |
10543 | inst.instruction |= inst.operands[1].reg << 3; | |
10544 | inst.instruction |= inst.operands[1].imm << 6; | |
10545 | } | |
90e4755a | 10546 | |
c19d1205 ZW |
10547 | static void |
10548 | do_t_ldstd (void) | |
10549 | { | |
10550 | if (!inst.operands[1].present) | |
b99bd4ef | 10551 | { |
c19d1205 ZW |
10552 | inst.operands[1].reg = inst.operands[0].reg + 1; |
10553 | constraint (inst.operands[0].reg == REG_LR, | |
10554 | _("r14 not allowed here")); | |
b99bd4ef | 10555 | } |
c19d1205 ZW |
10556 | inst.instruction |= inst.operands[0].reg << 12; |
10557 | inst.instruction |= inst.operands[1].reg << 8; | |
10558 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
10559 | } |
10560 | ||
c19d1205 ZW |
10561 | static void |
10562 | do_t_ldstt (void) | |
10563 | { | |
10564 | inst.instruction |= inst.operands[0].reg << 12; | |
10565 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
10566 | } | |
a737bd4d | 10567 | |
b99bd4ef | 10568 | static void |
c19d1205 | 10569 | do_t_mla (void) |
b99bd4ef | 10570 | { |
fdfde340 | 10571 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 10572 | |
fdfde340 JM |
10573 | Rd = inst.operands[0].reg; |
10574 | Rn = inst.operands[1].reg; | |
10575 | Rm = inst.operands[2].reg; | |
10576 | Ra = inst.operands[3].reg; | |
10577 | ||
10578 | reject_bad_reg (Rd); | |
10579 | reject_bad_reg (Rn); | |
10580 | reject_bad_reg (Rm); | |
10581 | reject_bad_reg (Ra); | |
10582 | ||
10583 | inst.instruction |= Rd << 8; | |
10584 | inst.instruction |= Rn << 16; | |
10585 | inst.instruction |= Rm; | |
10586 | inst.instruction |= Ra << 12; | |
c19d1205 | 10587 | } |
b99bd4ef | 10588 | |
c19d1205 ZW |
10589 | static void |
10590 | do_t_mlal (void) | |
10591 | { | |
fdfde340 JM |
10592 | unsigned RdLo, RdHi, Rn, Rm; |
10593 | ||
10594 | RdLo = inst.operands[0].reg; | |
10595 | RdHi = inst.operands[1].reg; | |
10596 | Rn = inst.operands[2].reg; | |
10597 | Rm = inst.operands[3].reg; | |
10598 | ||
10599 | reject_bad_reg (RdLo); | |
10600 | reject_bad_reg (RdHi); | |
10601 | reject_bad_reg (Rn); | |
10602 | reject_bad_reg (Rm); | |
10603 | ||
10604 | inst.instruction |= RdLo << 12; | |
10605 | inst.instruction |= RdHi << 8; | |
10606 | inst.instruction |= Rn << 16; | |
10607 | inst.instruction |= Rm; | |
c19d1205 | 10608 | } |
b99bd4ef | 10609 | |
c19d1205 ZW |
10610 | static void |
10611 | do_t_mov_cmp (void) | |
10612 | { | |
fdfde340 JM |
10613 | unsigned Rn, Rm; |
10614 | ||
10615 | Rn = inst.operands[0].reg; | |
10616 | Rm = inst.operands[1].reg; | |
10617 | ||
e07e6e58 NC |
10618 | if (Rn == REG_PC) |
10619 | set_it_insn_type_last (); | |
10620 | ||
c19d1205 | 10621 | if (unified_syntax) |
b99bd4ef | 10622 | { |
c19d1205 ZW |
10623 | int r0off = (inst.instruction == T_MNEM_mov |
10624 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 10625 | unsigned long opcode; |
3d388997 PB |
10626 | bfd_boolean narrow; |
10627 | bfd_boolean low_regs; | |
10628 | ||
fdfde340 | 10629 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 10630 | opcode = inst.instruction; |
e07e6e58 | 10631 | if (in_it_block ()) |
0110f2b8 | 10632 | narrow = opcode != T_MNEM_movs; |
3d388997 | 10633 | else |
0110f2b8 | 10634 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
10635 | if (inst.size_req == 4 |
10636 | || inst.operands[1].shifted) | |
10637 | narrow = FALSE; | |
10638 | ||
efd81785 PB |
10639 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
10640 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
10641 | && !inst.operands[1].shifted | |
fdfde340 JM |
10642 | && Rn == REG_PC |
10643 | && Rm == REG_LR) | |
efd81785 PB |
10644 | { |
10645 | inst.instruction = T2_SUBS_PC_LR; | |
10646 | return; | |
10647 | } | |
10648 | ||
fdfde340 JM |
10649 | if (opcode == T_MNEM_cmp) |
10650 | { | |
10651 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
10652 | if (narrow) |
10653 | { | |
10654 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
10655 | but valid. */ | |
10656 | warn_deprecated_sp (Rm); | |
10657 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
10658 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
10659 | tools reject R15, so we do too. */ | |
10660 | constraint (Rm == REG_PC, BAD_PC); | |
10661 | } | |
10662 | else | |
10663 | reject_bad_reg (Rm); | |
fdfde340 JM |
10664 | } |
10665 | else if (opcode == T_MNEM_mov | |
10666 | || opcode == T_MNEM_movs) | |
10667 | { | |
10668 | if (inst.operands[1].isreg) | |
10669 | { | |
10670 | if (opcode == T_MNEM_movs) | |
10671 | { | |
10672 | reject_bad_reg (Rn); | |
10673 | reject_bad_reg (Rm); | |
10674 | } | |
76fa04a4 MGD |
10675 | else if (narrow) |
10676 | { | |
10677 | /* This is mov.n. */ | |
10678 | if ((Rn == REG_SP || Rn == REG_PC) | |
10679 | && (Rm == REG_SP || Rm == REG_PC)) | |
10680 | { | |
10681 | as_warn (_("Use of r%u as a source register is " | |
10682 | "deprecated when r%u is the destination " | |
10683 | "register."), Rm, Rn); | |
10684 | } | |
10685 | } | |
10686 | else | |
10687 | { | |
10688 | /* This is mov.w. */ | |
10689 | constraint (Rn == REG_PC, BAD_PC); | |
10690 | constraint (Rm == REG_PC, BAD_PC); | |
10691 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
10692 | } | |
fdfde340 JM |
10693 | } |
10694 | else | |
10695 | reject_bad_reg (Rn); | |
10696 | } | |
10697 | ||
c19d1205 ZW |
10698 | if (!inst.operands[1].isreg) |
10699 | { | |
0110f2b8 | 10700 | /* Immediate operand. */ |
e07e6e58 | 10701 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
10702 | narrow = 0; |
10703 | if (low_regs && narrow) | |
10704 | { | |
10705 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 10706 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
10707 | if (inst.size_req == 2) |
10708 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
10709 | else | |
10710 | inst.relax = opcode; | |
10711 | } | |
10712 | else | |
10713 | { | |
10714 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10715 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10716 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
10717 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
10718 | } | |
c19d1205 | 10719 | } |
728ca7c9 PB |
10720 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
10721 | && (inst.instruction == T_MNEM_mov | |
10722 | || inst.instruction == T_MNEM_movs)) | |
10723 | { | |
10724 | /* Register shifts are encoded as separate shift instructions. */ | |
10725 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
10726 | ||
e07e6e58 | 10727 | if (in_it_block ()) |
728ca7c9 PB |
10728 | narrow = !flags; |
10729 | else | |
10730 | narrow = flags; | |
10731 | ||
10732 | if (inst.size_req == 4) | |
10733 | narrow = FALSE; | |
10734 | ||
10735 | if (!low_regs || inst.operands[1].imm > 7) | |
10736 | narrow = FALSE; | |
10737 | ||
fdfde340 | 10738 | if (Rn != Rm) |
728ca7c9 PB |
10739 | narrow = FALSE; |
10740 | ||
10741 | switch (inst.operands[1].shift_kind) | |
10742 | { | |
10743 | case SHIFT_LSL: | |
10744 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
10745 | break; | |
10746 | case SHIFT_ASR: | |
10747 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
10748 | break; | |
10749 | case SHIFT_LSR: | |
10750 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
10751 | break; | |
10752 | case SHIFT_ROR: | |
10753 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
10754 | break; | |
10755 | default: | |
5f4273c7 | 10756 | abort (); |
728ca7c9 PB |
10757 | } |
10758 | ||
10759 | inst.instruction = opcode; | |
10760 | if (narrow) | |
10761 | { | |
fdfde340 | 10762 | inst.instruction |= Rn; |
728ca7c9 PB |
10763 | inst.instruction |= inst.operands[1].imm << 3; |
10764 | } | |
10765 | else | |
10766 | { | |
10767 | if (flags) | |
10768 | inst.instruction |= CONDS_BIT; | |
10769 | ||
fdfde340 JM |
10770 | inst.instruction |= Rn << 8; |
10771 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
10772 | inst.instruction |= inst.operands[1].imm; |
10773 | } | |
10774 | } | |
3d388997 | 10775 | else if (!narrow) |
c19d1205 | 10776 | { |
728ca7c9 PB |
10777 | /* Some mov with immediate shift have narrow variants. |
10778 | Register shifts are handled above. */ | |
10779 | if (low_regs && inst.operands[1].shifted | |
10780 | && (inst.instruction == T_MNEM_mov | |
10781 | || inst.instruction == T_MNEM_movs)) | |
10782 | { | |
e07e6e58 | 10783 | if (in_it_block ()) |
728ca7c9 PB |
10784 | narrow = (inst.instruction == T_MNEM_mov); |
10785 | else | |
10786 | narrow = (inst.instruction == T_MNEM_movs); | |
10787 | } | |
10788 | ||
10789 | if (narrow) | |
10790 | { | |
10791 | switch (inst.operands[1].shift_kind) | |
10792 | { | |
10793 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
10794 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
10795 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
10796 | default: narrow = FALSE; break; | |
10797 | } | |
10798 | } | |
10799 | ||
10800 | if (narrow) | |
10801 | { | |
fdfde340 JM |
10802 | inst.instruction |= Rn; |
10803 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
10804 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
10805 | } | |
10806 | else | |
10807 | { | |
10808 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10809 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
10810 | encode_thumb32_shifted_operand (1); |
10811 | } | |
c19d1205 ZW |
10812 | } |
10813 | else | |
10814 | switch (inst.instruction) | |
10815 | { | |
10816 | case T_MNEM_mov: | |
10817 | inst.instruction = T_OPCODE_MOV_HR; | |
fdfde340 JM |
10818 | inst.instruction |= (Rn & 0x8) << 4; |
10819 | inst.instruction |= (Rn & 0x7); | |
10820 | inst.instruction |= Rm << 3; | |
c19d1205 | 10821 | break; |
b99bd4ef | 10822 | |
c19d1205 ZW |
10823 | case T_MNEM_movs: |
10824 | /* We know we have low registers at this point. | |
941a8a52 MGD |
10825 | Generate LSLS Rd, Rs, #0. */ |
10826 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
10827 | inst.instruction |= Rn; |
10828 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10829 | break; |
10830 | ||
10831 | case T_MNEM_cmp: | |
3d388997 | 10832 | if (low_regs) |
c19d1205 ZW |
10833 | { |
10834 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
10835 | inst.instruction |= Rn; |
10836 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10837 | } |
10838 | else | |
10839 | { | |
10840 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
10841 | inst.instruction |= (Rn & 0x8) << 4; |
10842 | inst.instruction |= (Rn & 0x7); | |
10843 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10844 | } |
10845 | break; | |
10846 | } | |
b99bd4ef NC |
10847 | return; |
10848 | } | |
10849 | ||
c19d1205 | 10850 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
10851 | |
10852 | /* PR 10443: Do not silently ignore shifted operands. */ | |
10853 | constraint (inst.operands[1].shifted, | |
10854 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
10855 | ||
c19d1205 | 10856 | if (inst.operands[1].isreg) |
b99bd4ef | 10857 | { |
fdfde340 | 10858 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 10859 | { |
c19d1205 ZW |
10860 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
10861 | since a MOV instruction produces unpredictable results. */ | |
10862 | if (inst.instruction == T_OPCODE_MOV_I8) | |
10863 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 10864 | else |
c19d1205 | 10865 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 10866 | |
fdfde340 JM |
10867 | inst.instruction |= Rn; |
10868 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
10869 | } |
10870 | else | |
10871 | { | |
c19d1205 ZW |
10872 | if (inst.instruction == T_OPCODE_MOV_I8) |
10873 | inst.instruction = T_OPCODE_MOV_HR; | |
10874 | else | |
10875 | inst.instruction = T_OPCODE_CMP_HR; | |
10876 | do_t_cpy (); | |
b99bd4ef NC |
10877 | } |
10878 | } | |
c19d1205 | 10879 | else |
b99bd4ef | 10880 | { |
fdfde340 | 10881 | constraint (Rn > 7, |
c19d1205 | 10882 | _("only lo regs allowed with immediate")); |
fdfde340 | 10883 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
10884 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
10885 | } | |
10886 | } | |
b99bd4ef | 10887 | |
c19d1205 ZW |
10888 | static void |
10889 | do_t_mov16 (void) | |
10890 | { | |
fdfde340 | 10891 | unsigned Rd; |
b6895b4f PB |
10892 | bfd_vma imm; |
10893 | bfd_boolean top; | |
10894 | ||
10895 | top = (inst.instruction & 0x00800000) != 0; | |
10896 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
10897 | { | |
10898 | constraint (top, _(":lower16: not allowed this instruction")); | |
10899 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
10900 | } | |
10901 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
10902 | { | |
10903 | constraint (!top, _(":upper16: not allowed this instruction")); | |
10904 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
10905 | } | |
10906 | ||
fdfde340 JM |
10907 | Rd = inst.operands[0].reg; |
10908 | reject_bad_reg (Rd); | |
10909 | ||
10910 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
10911 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
10912 | { | |
10913 | imm = inst.reloc.exp.X_add_number; | |
10914 | inst.instruction |= (imm & 0xf000) << 4; | |
10915 | inst.instruction |= (imm & 0x0800) << 15; | |
10916 | inst.instruction |= (imm & 0x0700) << 4; | |
10917 | inst.instruction |= (imm & 0x00ff); | |
10918 | } | |
c19d1205 | 10919 | } |
b99bd4ef | 10920 | |
c19d1205 ZW |
10921 | static void |
10922 | do_t_mvn_tst (void) | |
10923 | { | |
fdfde340 | 10924 | unsigned Rn, Rm; |
c921be7d | 10925 | |
fdfde340 JM |
10926 | Rn = inst.operands[0].reg; |
10927 | Rm = inst.operands[1].reg; | |
10928 | ||
10929 | if (inst.instruction == T_MNEM_cmp | |
10930 | || inst.instruction == T_MNEM_cmn) | |
10931 | constraint (Rn == REG_PC, BAD_PC); | |
10932 | else | |
10933 | reject_bad_reg (Rn); | |
10934 | reject_bad_reg (Rm); | |
10935 | ||
c19d1205 ZW |
10936 | if (unified_syntax) |
10937 | { | |
10938 | int r0off = (inst.instruction == T_MNEM_mvn | |
10939 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
10940 | bfd_boolean narrow; |
10941 | ||
10942 | if (inst.size_req == 4 | |
10943 | || inst.instruction > 0xffff | |
10944 | || inst.operands[1].shifted | |
fdfde340 | 10945 | || Rn > 7 || Rm > 7) |
3d388997 PB |
10946 | narrow = FALSE; |
10947 | else if (inst.instruction == T_MNEM_cmn) | |
10948 | narrow = TRUE; | |
10949 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 10950 | narrow = !in_it_block (); |
3d388997 | 10951 | else |
e07e6e58 | 10952 | narrow = in_it_block (); |
3d388997 | 10953 | |
c19d1205 | 10954 | if (!inst.operands[1].isreg) |
b99bd4ef | 10955 | { |
c19d1205 ZW |
10956 | /* For an immediate, we always generate a 32-bit opcode; |
10957 | section relaxation will shrink it later if possible. */ | |
10958 | if (inst.instruction < 0xffff) | |
10959 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10960 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10961 | inst.instruction |= Rn << r0off; |
c19d1205 | 10962 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 10963 | } |
c19d1205 | 10964 | else |
b99bd4ef | 10965 | { |
c19d1205 | 10966 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 10967 | if (narrow) |
b99bd4ef | 10968 | { |
c19d1205 | 10969 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10970 | inst.instruction |= Rn; |
10971 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10972 | } |
c19d1205 | 10973 | else |
b99bd4ef | 10974 | { |
c19d1205 ZW |
10975 | constraint (inst.operands[1].shifted |
10976 | && inst.operands[1].immisreg, | |
10977 | _("shift must be constant")); | |
10978 | if (inst.instruction < 0xffff) | |
10979 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10980 | inst.instruction |= Rn << r0off; |
c19d1205 | 10981 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 10982 | } |
b99bd4ef NC |
10983 | } |
10984 | } | |
10985 | else | |
10986 | { | |
c19d1205 ZW |
10987 | constraint (inst.instruction > 0xffff |
10988 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
10989 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
10990 | _("unshifted register required")); | |
fdfde340 | 10991 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 10992 | BAD_HIREG); |
b99bd4ef | 10993 | |
c19d1205 | 10994 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
10995 | inst.instruction |= Rn; |
10996 | inst.instruction |= Rm << 3; | |
b99bd4ef | 10997 | } |
b99bd4ef NC |
10998 | } |
10999 | ||
b05fe5cf | 11000 | static void |
c19d1205 | 11001 | do_t_mrs (void) |
b05fe5cf | 11002 | { |
fdfde340 | 11003 | unsigned Rd; |
037e8744 JB |
11004 | |
11005 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
11006 | return; | |
11007 | ||
90ec0d68 MGD |
11008 | Rd = inst.operands[0].reg; |
11009 | reject_bad_reg (Rd); | |
11010 | inst.instruction |= Rd << 8; | |
11011 | ||
11012 | if (inst.operands[1].isreg) | |
62b3e311 | 11013 | { |
90ec0d68 MGD |
11014 | unsigned br = inst.operands[1].reg; |
11015 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
11016 | as_bad (_("bad register for mrs")); | |
11017 | ||
11018 | inst.instruction |= br & (0xf << 16); | |
11019 | inst.instruction |= (br & 0x300) >> 4; | |
11020 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
11021 | } |
11022 | else | |
11023 | { | |
90ec0d68 | 11024 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 11025 | |
d2cd1205 JB |
11026 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
11027 | constraint (flags != 0, _("selected processor does not support " | |
11028 | "requested special purpose register")); | |
90ec0d68 | 11029 | else |
d2cd1205 JB |
11030 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
11031 | devices). */ | |
11032 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
11033 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 11034 | |
90ec0d68 MGD |
11035 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
11036 | inst.instruction |= inst.operands[1].imm & 0xff; | |
11037 | inst.instruction |= 0xf0000; | |
11038 | } | |
c19d1205 | 11039 | } |
b05fe5cf | 11040 | |
c19d1205 ZW |
11041 | static void |
11042 | do_t_msr (void) | |
11043 | { | |
62b3e311 | 11044 | int flags; |
fdfde340 | 11045 | unsigned Rn; |
62b3e311 | 11046 | |
037e8744 JB |
11047 | if (do_vfp_nsyn_msr () == SUCCESS) |
11048 | return; | |
11049 | ||
c19d1205 ZW |
11050 | constraint (!inst.operands[1].isreg, |
11051 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
11052 | |
11053 | if (inst.operands[0].isreg) | |
11054 | flags = (int)(inst.operands[0].reg); | |
11055 | else | |
11056 | flags = inst.operands[0].imm; | |
11057 | ||
d2cd1205 | 11058 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 11059 | { |
d2cd1205 JB |
11060 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
11061 | ||
11062 | constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
11063 | && (bits & ~(PSR_s | PSR_f)) != 0) | |
11064 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
11065 | && bits != PSR_f), | |
11066 | _("selected processor does not support requested special " | |
11067 | "purpose register")); | |
62b3e311 PB |
11068 | } |
11069 | else | |
d2cd1205 JB |
11070 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
11071 | "requested special purpose register")); | |
c921be7d | 11072 | |
fdfde340 JM |
11073 | Rn = inst.operands[1].reg; |
11074 | reject_bad_reg (Rn); | |
11075 | ||
62b3e311 | 11076 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
11077 | inst.instruction |= (flags & 0xf0000) >> 8; |
11078 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 11079 | inst.instruction |= (flags & 0xff); |
fdfde340 | 11080 | inst.instruction |= Rn << 16; |
c19d1205 | 11081 | } |
b05fe5cf | 11082 | |
c19d1205 ZW |
11083 | static void |
11084 | do_t_mul (void) | |
11085 | { | |
17828f45 | 11086 | bfd_boolean narrow; |
fdfde340 | 11087 | unsigned Rd, Rn, Rm; |
17828f45 | 11088 | |
c19d1205 ZW |
11089 | if (!inst.operands[2].present) |
11090 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 11091 | |
fdfde340 JM |
11092 | Rd = inst.operands[0].reg; |
11093 | Rn = inst.operands[1].reg; | |
11094 | Rm = inst.operands[2].reg; | |
11095 | ||
17828f45 | 11096 | if (unified_syntax) |
b05fe5cf | 11097 | { |
17828f45 | 11098 | if (inst.size_req == 4 |
fdfde340 JM |
11099 | || (Rd != Rn |
11100 | && Rd != Rm) | |
11101 | || Rn > 7 | |
11102 | || Rm > 7) | |
17828f45 JM |
11103 | narrow = FALSE; |
11104 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 11105 | narrow = !in_it_block (); |
17828f45 | 11106 | else |
e07e6e58 | 11107 | narrow = in_it_block (); |
b05fe5cf | 11108 | } |
c19d1205 | 11109 | else |
b05fe5cf | 11110 | { |
17828f45 | 11111 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 11112 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 11113 | BAD_HIREG); |
17828f45 JM |
11114 | narrow = TRUE; |
11115 | } | |
b05fe5cf | 11116 | |
17828f45 JM |
11117 | if (narrow) |
11118 | { | |
11119 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 11120 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 11121 | inst.instruction |= Rd; |
b05fe5cf | 11122 | |
fdfde340 JM |
11123 | if (Rd == Rn) |
11124 | inst.instruction |= Rm << 3; | |
11125 | else if (Rd == Rm) | |
11126 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
11127 | else |
11128 | constraint (1, _("dest must overlap one source register")); | |
11129 | } | |
17828f45 JM |
11130 | else |
11131 | { | |
e07e6e58 NC |
11132 | constraint (inst.instruction != T_MNEM_mul, |
11133 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
11134 | /* 32-bit MUL. */ |
11135 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11136 | inst.instruction |= Rd << 8; |
11137 | inst.instruction |= Rn << 16; | |
11138 | inst.instruction |= Rm << 0; | |
11139 | ||
11140 | reject_bad_reg (Rd); | |
11141 | reject_bad_reg (Rn); | |
11142 | reject_bad_reg (Rm); | |
17828f45 | 11143 | } |
c19d1205 | 11144 | } |
b05fe5cf | 11145 | |
c19d1205 ZW |
11146 | static void |
11147 | do_t_mull (void) | |
11148 | { | |
fdfde340 | 11149 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 11150 | |
fdfde340 JM |
11151 | RdLo = inst.operands[0].reg; |
11152 | RdHi = inst.operands[1].reg; | |
11153 | Rn = inst.operands[2].reg; | |
11154 | Rm = inst.operands[3].reg; | |
11155 | ||
11156 | reject_bad_reg (RdLo); | |
11157 | reject_bad_reg (RdHi); | |
11158 | reject_bad_reg (Rn); | |
11159 | reject_bad_reg (Rm); | |
11160 | ||
11161 | inst.instruction |= RdLo << 12; | |
11162 | inst.instruction |= RdHi << 8; | |
11163 | inst.instruction |= Rn << 16; | |
11164 | inst.instruction |= Rm; | |
11165 | ||
11166 | if (RdLo == RdHi) | |
c19d1205 ZW |
11167 | as_tsktsk (_("rdhi and rdlo must be different")); |
11168 | } | |
b05fe5cf | 11169 | |
c19d1205 ZW |
11170 | static void |
11171 | do_t_nop (void) | |
11172 | { | |
e07e6e58 NC |
11173 | set_it_insn_type (NEUTRAL_IT_INSN); |
11174 | ||
c19d1205 ZW |
11175 | if (unified_syntax) |
11176 | { | |
11177 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 11178 | { |
c19d1205 ZW |
11179 | inst.instruction = THUMB_OP32 (inst.instruction); |
11180 | inst.instruction |= inst.operands[0].imm; | |
11181 | } | |
11182 | else | |
11183 | { | |
bc2d1808 NC |
11184 | /* PR9722: Check for Thumb2 availability before |
11185 | generating a thumb2 nop instruction. */ | |
afa62d5e | 11186 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
11187 | { |
11188 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11189 | inst.instruction |= inst.operands[0].imm << 4; | |
11190 | } | |
11191 | else | |
11192 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
11193 | } |
11194 | } | |
11195 | else | |
11196 | { | |
11197 | constraint (inst.operands[0].present, | |
11198 | _("Thumb does not support NOP with hints")); | |
11199 | inst.instruction = 0x46c0; | |
11200 | } | |
11201 | } | |
b05fe5cf | 11202 | |
c19d1205 ZW |
11203 | static void |
11204 | do_t_neg (void) | |
11205 | { | |
11206 | if (unified_syntax) | |
11207 | { | |
3d388997 PB |
11208 | bfd_boolean narrow; |
11209 | ||
11210 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11211 | narrow = !in_it_block (); |
3d388997 | 11212 | else |
e07e6e58 | 11213 | narrow = in_it_block (); |
3d388997 PB |
11214 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11215 | narrow = FALSE; | |
11216 | if (inst.size_req == 4) | |
11217 | narrow = FALSE; | |
11218 | ||
11219 | if (!narrow) | |
c19d1205 ZW |
11220 | { |
11221 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11222 | inst.instruction |= inst.operands[0].reg << 8; | |
11223 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
11224 | } |
11225 | else | |
11226 | { | |
c19d1205 ZW |
11227 | inst.instruction = THUMB_OP16 (inst.instruction); |
11228 | inst.instruction |= inst.operands[0].reg; | |
11229 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
11230 | } |
11231 | } | |
11232 | else | |
11233 | { | |
c19d1205 ZW |
11234 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
11235 | BAD_HIREG); | |
11236 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
11237 | ||
11238 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11239 | inst.instruction |= inst.operands[0].reg; | |
11240 | inst.instruction |= inst.operands[1].reg << 3; | |
11241 | } | |
11242 | } | |
11243 | ||
1c444d06 JM |
11244 | static void |
11245 | do_t_orn (void) | |
11246 | { | |
11247 | unsigned Rd, Rn; | |
11248 | ||
11249 | Rd = inst.operands[0].reg; | |
11250 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
11251 | ||
fdfde340 JM |
11252 | reject_bad_reg (Rd); |
11253 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
11254 | reject_bad_reg (Rn); | |
11255 | ||
1c444d06 JM |
11256 | inst.instruction |= Rd << 8; |
11257 | inst.instruction |= Rn << 16; | |
11258 | ||
11259 | if (!inst.operands[2].isreg) | |
11260 | { | |
11261 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11262 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11263 | } | |
11264 | else | |
11265 | { | |
11266 | unsigned Rm; | |
11267 | ||
11268 | Rm = inst.operands[2].reg; | |
fdfde340 | 11269 | reject_bad_reg (Rm); |
1c444d06 JM |
11270 | |
11271 | constraint (inst.operands[2].shifted | |
11272 | && inst.operands[2].immisreg, | |
11273 | _("shift must be constant")); | |
11274 | encode_thumb32_shifted_operand (2); | |
11275 | } | |
11276 | } | |
11277 | ||
c19d1205 ZW |
11278 | static void |
11279 | do_t_pkhbt (void) | |
11280 | { | |
fdfde340 JM |
11281 | unsigned Rd, Rn, Rm; |
11282 | ||
11283 | Rd = inst.operands[0].reg; | |
11284 | Rn = inst.operands[1].reg; | |
11285 | Rm = inst.operands[2].reg; | |
11286 | ||
11287 | reject_bad_reg (Rd); | |
11288 | reject_bad_reg (Rn); | |
11289 | reject_bad_reg (Rm); | |
11290 | ||
11291 | inst.instruction |= Rd << 8; | |
11292 | inst.instruction |= Rn << 16; | |
11293 | inst.instruction |= Rm; | |
c19d1205 ZW |
11294 | if (inst.operands[3].present) |
11295 | { | |
11296 | unsigned int val = inst.reloc.exp.X_add_number; | |
11297 | constraint (inst.reloc.exp.X_op != O_constant, | |
11298 | _("expression too complex")); | |
11299 | inst.instruction |= (val & 0x1c) << 10; | |
11300 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 11301 | } |
c19d1205 | 11302 | } |
b05fe5cf | 11303 | |
c19d1205 ZW |
11304 | static void |
11305 | do_t_pkhtb (void) | |
11306 | { | |
11307 | if (!inst.operands[3].present) | |
1ef52f49 NC |
11308 | { |
11309 | unsigned Rtmp; | |
11310 | ||
11311 | inst.instruction &= ~0x00000020; | |
11312 | ||
11313 | /* PR 10168. Swap the Rm and Rn registers. */ | |
11314 | Rtmp = inst.operands[1].reg; | |
11315 | inst.operands[1].reg = inst.operands[2].reg; | |
11316 | inst.operands[2].reg = Rtmp; | |
11317 | } | |
c19d1205 | 11318 | do_t_pkhbt (); |
b05fe5cf ZW |
11319 | } |
11320 | ||
c19d1205 ZW |
11321 | static void |
11322 | do_t_pld (void) | |
11323 | { | |
fdfde340 JM |
11324 | if (inst.operands[0].immisreg) |
11325 | reject_bad_reg (inst.operands[0].imm); | |
11326 | ||
c19d1205 ZW |
11327 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
11328 | } | |
b05fe5cf | 11329 | |
c19d1205 ZW |
11330 | static void |
11331 | do_t_push_pop (void) | |
b99bd4ef | 11332 | { |
e9f89963 | 11333 | unsigned mask; |
5f4273c7 | 11334 | |
c19d1205 ZW |
11335 | constraint (inst.operands[0].writeback, |
11336 | _("push/pop do not support {reglist}^")); | |
11337 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
11338 | _("expression too complex")); | |
b99bd4ef | 11339 | |
e9f89963 PB |
11340 | mask = inst.operands[0].imm; |
11341 | if ((mask & ~0xff) == 0) | |
3c707909 | 11342 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
c19d1205 | 11343 | else if ((inst.instruction == T_MNEM_push |
e9f89963 | 11344 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 11345 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 11346 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 11347 | { |
c19d1205 ZW |
11348 | inst.instruction = THUMB_OP16 (inst.instruction); |
11349 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 11350 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
11351 | } |
11352 | else if (unified_syntax) | |
11353 | { | |
3c707909 | 11354 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 11355 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
11356 | } |
11357 | else | |
11358 | { | |
11359 | inst.error = _("invalid register list to push/pop instruction"); | |
11360 | return; | |
11361 | } | |
c19d1205 | 11362 | } |
b99bd4ef | 11363 | |
c19d1205 ZW |
11364 | static void |
11365 | do_t_rbit (void) | |
11366 | { | |
fdfde340 JM |
11367 | unsigned Rd, Rm; |
11368 | ||
11369 | Rd = inst.operands[0].reg; | |
11370 | Rm = inst.operands[1].reg; | |
11371 | ||
11372 | reject_bad_reg (Rd); | |
11373 | reject_bad_reg (Rm); | |
11374 | ||
11375 | inst.instruction |= Rd << 8; | |
11376 | inst.instruction |= Rm << 16; | |
11377 | inst.instruction |= Rm; | |
c19d1205 | 11378 | } |
b99bd4ef | 11379 | |
c19d1205 ZW |
11380 | static void |
11381 | do_t_rev (void) | |
11382 | { | |
fdfde340 JM |
11383 | unsigned Rd, Rm; |
11384 | ||
11385 | Rd = inst.operands[0].reg; | |
11386 | Rm = inst.operands[1].reg; | |
11387 | ||
11388 | reject_bad_reg (Rd); | |
11389 | reject_bad_reg (Rm); | |
11390 | ||
11391 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
11392 | && inst.size_req != 4) |
11393 | { | |
11394 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
11395 | inst.instruction |= Rd; |
11396 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11397 | } |
11398 | else if (unified_syntax) | |
11399 | { | |
11400 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11401 | inst.instruction |= Rd << 8; |
11402 | inst.instruction |= Rm << 16; | |
11403 | inst.instruction |= Rm; | |
c19d1205 ZW |
11404 | } |
11405 | else | |
11406 | inst.error = BAD_HIREG; | |
11407 | } | |
b99bd4ef | 11408 | |
1c444d06 JM |
11409 | static void |
11410 | do_t_rrx (void) | |
11411 | { | |
11412 | unsigned Rd, Rm; | |
11413 | ||
11414 | Rd = inst.operands[0].reg; | |
11415 | Rm = inst.operands[1].reg; | |
11416 | ||
fdfde340 JM |
11417 | reject_bad_reg (Rd); |
11418 | reject_bad_reg (Rm); | |
c921be7d | 11419 | |
1c444d06 JM |
11420 | inst.instruction |= Rd << 8; |
11421 | inst.instruction |= Rm; | |
11422 | } | |
11423 | ||
c19d1205 ZW |
11424 | static void |
11425 | do_t_rsb (void) | |
11426 | { | |
fdfde340 | 11427 | unsigned Rd, Rs; |
b99bd4ef | 11428 | |
c19d1205 ZW |
11429 | Rd = inst.operands[0].reg; |
11430 | Rs = (inst.operands[1].present | |
11431 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11432 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 11433 | |
fdfde340 JM |
11434 | reject_bad_reg (Rd); |
11435 | reject_bad_reg (Rs); | |
11436 | if (inst.operands[2].isreg) | |
11437 | reject_bad_reg (inst.operands[2].reg); | |
11438 | ||
c19d1205 ZW |
11439 | inst.instruction |= Rd << 8; |
11440 | inst.instruction |= Rs << 16; | |
11441 | if (!inst.operands[2].isreg) | |
11442 | { | |
026d3abb PB |
11443 | bfd_boolean narrow; |
11444 | ||
11445 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 11446 | narrow = !in_it_block (); |
026d3abb | 11447 | else |
e07e6e58 | 11448 | narrow = in_it_block (); |
026d3abb PB |
11449 | |
11450 | if (Rd > 7 || Rs > 7) | |
11451 | narrow = FALSE; | |
11452 | ||
11453 | if (inst.size_req == 4 || !unified_syntax) | |
11454 | narrow = FALSE; | |
11455 | ||
11456 | if (inst.reloc.exp.X_op != O_constant | |
11457 | || inst.reloc.exp.X_add_number != 0) | |
11458 | narrow = FALSE; | |
11459 | ||
11460 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
11461 | relaxation, but it doesn't seem worth the hassle. */ | |
11462 | if (narrow) | |
11463 | { | |
11464 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11465 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
11466 | inst.instruction |= Rs << 3; | |
11467 | inst.instruction |= Rd; | |
11468 | } | |
11469 | else | |
11470 | { | |
11471 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11472 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11473 | } | |
c19d1205 ZW |
11474 | } |
11475 | else | |
11476 | encode_thumb32_shifted_operand (2); | |
11477 | } | |
b99bd4ef | 11478 | |
c19d1205 ZW |
11479 | static void |
11480 | do_t_setend (void) | |
11481 | { | |
e07e6e58 | 11482 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11483 | if (inst.operands[0].imm) |
11484 | inst.instruction |= 0x8; | |
11485 | } | |
b99bd4ef | 11486 | |
c19d1205 ZW |
11487 | static void |
11488 | do_t_shift (void) | |
11489 | { | |
11490 | if (!inst.operands[1].present) | |
11491 | inst.operands[1].reg = inst.operands[0].reg; | |
11492 | ||
11493 | if (unified_syntax) | |
11494 | { | |
3d388997 PB |
11495 | bfd_boolean narrow; |
11496 | int shift_kind; | |
11497 | ||
11498 | switch (inst.instruction) | |
11499 | { | |
11500 | case T_MNEM_asr: | |
11501 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
11502 | case T_MNEM_lsl: | |
11503 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
11504 | case T_MNEM_lsr: | |
11505 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
11506 | case T_MNEM_ror: | |
11507 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
11508 | default: abort (); | |
11509 | } | |
11510 | ||
11511 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11512 | narrow = !in_it_block (); |
3d388997 | 11513 | else |
e07e6e58 | 11514 | narrow = in_it_block (); |
3d388997 PB |
11515 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11516 | narrow = FALSE; | |
11517 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
11518 | narrow = FALSE; | |
11519 | if (inst.operands[2].isreg | |
11520 | && (inst.operands[1].reg != inst.operands[0].reg | |
11521 | || inst.operands[2].reg > 7)) | |
11522 | narrow = FALSE; | |
11523 | if (inst.size_req == 4) | |
11524 | narrow = FALSE; | |
11525 | ||
fdfde340 JM |
11526 | reject_bad_reg (inst.operands[0].reg); |
11527 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 11528 | |
3d388997 | 11529 | if (!narrow) |
c19d1205 ZW |
11530 | { |
11531 | if (inst.operands[2].isreg) | |
b99bd4ef | 11532 | { |
fdfde340 | 11533 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
11534 | inst.instruction = THUMB_OP32 (inst.instruction); |
11535 | inst.instruction |= inst.operands[0].reg << 8; | |
11536 | inst.instruction |= inst.operands[1].reg << 16; | |
11537 | inst.instruction |= inst.operands[2].reg; | |
11538 | } | |
11539 | else | |
11540 | { | |
11541 | inst.operands[1].shifted = 1; | |
3d388997 | 11542 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
11543 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
11544 | ? T_MNEM_movs : T_MNEM_mov); | |
11545 | inst.instruction |= inst.operands[0].reg << 8; | |
11546 | encode_thumb32_shifted_operand (1); | |
11547 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
11548 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
11549 | } |
11550 | } | |
11551 | else | |
11552 | { | |
c19d1205 | 11553 | if (inst.operands[2].isreg) |
b99bd4ef | 11554 | { |
3d388997 | 11555 | switch (shift_kind) |
b99bd4ef | 11556 | { |
3d388997 PB |
11557 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
11558 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
11559 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
11560 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 11561 | default: abort (); |
b99bd4ef | 11562 | } |
5f4273c7 | 11563 | |
c19d1205 ZW |
11564 | inst.instruction |= inst.operands[0].reg; |
11565 | inst.instruction |= inst.operands[2].reg << 3; | |
b99bd4ef NC |
11566 | } |
11567 | else | |
11568 | { | |
3d388997 | 11569 | switch (shift_kind) |
b99bd4ef | 11570 | { |
3d388997 PB |
11571 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
11572 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11573 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 11574 | default: abort (); |
b99bd4ef | 11575 | } |
c19d1205 ZW |
11576 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11577 | inst.instruction |= inst.operands[0].reg; | |
11578 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11579 | } |
11580 | } | |
c19d1205 ZW |
11581 | } |
11582 | else | |
11583 | { | |
11584 | constraint (inst.operands[0].reg > 7 | |
11585 | || inst.operands[1].reg > 7, BAD_HIREG); | |
11586 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 11587 | |
c19d1205 ZW |
11588 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
11589 | { | |
11590 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
11591 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
11592 | _("source1 and dest must be same register")); | |
b99bd4ef | 11593 | |
c19d1205 ZW |
11594 | switch (inst.instruction) |
11595 | { | |
11596 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
11597 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
11598 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
11599 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
11600 | default: abort (); | |
11601 | } | |
5f4273c7 | 11602 | |
c19d1205 ZW |
11603 | inst.instruction |= inst.operands[0].reg; |
11604 | inst.instruction |= inst.operands[2].reg << 3; | |
11605 | } | |
11606 | else | |
b99bd4ef | 11607 | { |
c19d1205 ZW |
11608 | switch (inst.instruction) |
11609 | { | |
11610 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
11611 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
11612 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
11613 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
11614 | default: abort (); | |
11615 | } | |
11616 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
11617 | inst.instruction |= inst.operands[0].reg; | |
11618 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11619 | } |
11620 | } | |
b99bd4ef NC |
11621 | } |
11622 | ||
11623 | static void | |
c19d1205 | 11624 | do_t_simd (void) |
b99bd4ef | 11625 | { |
fdfde340 JM |
11626 | unsigned Rd, Rn, Rm; |
11627 | ||
11628 | Rd = inst.operands[0].reg; | |
11629 | Rn = inst.operands[1].reg; | |
11630 | Rm = inst.operands[2].reg; | |
11631 | ||
11632 | reject_bad_reg (Rd); | |
11633 | reject_bad_reg (Rn); | |
11634 | reject_bad_reg (Rm); | |
11635 | ||
11636 | inst.instruction |= Rd << 8; | |
11637 | inst.instruction |= Rn << 16; | |
11638 | inst.instruction |= Rm; | |
c19d1205 | 11639 | } |
b99bd4ef | 11640 | |
03ee1b7f NC |
11641 | static void |
11642 | do_t_simd2 (void) | |
11643 | { | |
11644 | unsigned Rd, Rn, Rm; | |
11645 | ||
11646 | Rd = inst.operands[0].reg; | |
11647 | Rm = inst.operands[1].reg; | |
11648 | Rn = inst.operands[2].reg; | |
11649 | ||
11650 | reject_bad_reg (Rd); | |
11651 | reject_bad_reg (Rn); | |
11652 | reject_bad_reg (Rm); | |
11653 | ||
11654 | inst.instruction |= Rd << 8; | |
11655 | inst.instruction |= Rn << 16; | |
11656 | inst.instruction |= Rm; | |
11657 | } | |
11658 | ||
c19d1205 | 11659 | static void |
3eb17e6b | 11660 | do_t_smc (void) |
c19d1205 ZW |
11661 | { |
11662 | unsigned int value = inst.reloc.exp.X_add_number; | |
f4c65163 MGD |
11663 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
11664 | _("SMC is not permitted on this architecture")); | |
c19d1205 ZW |
11665 | constraint (inst.reloc.exp.X_op != O_constant, |
11666 | _("expression too complex")); | |
11667 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11668 | inst.instruction |= (value & 0xf000) >> 12; | |
11669 | inst.instruction |= (value & 0x0ff0); | |
11670 | inst.instruction |= (value & 0x000f) << 16; | |
11671 | } | |
b99bd4ef | 11672 | |
90ec0d68 MGD |
11673 | static void |
11674 | do_t_hvc (void) | |
11675 | { | |
11676 | unsigned int value = inst.reloc.exp.X_add_number; | |
11677 | ||
11678 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11679 | inst.instruction |= (value & 0x0fff); | |
11680 | inst.instruction |= (value & 0xf000) << 4; | |
11681 | } | |
11682 | ||
c19d1205 | 11683 | static void |
3a21c15a | 11684 | do_t_ssat_usat (int bias) |
c19d1205 | 11685 | { |
fdfde340 JM |
11686 | unsigned Rd, Rn; |
11687 | ||
11688 | Rd = inst.operands[0].reg; | |
11689 | Rn = inst.operands[2].reg; | |
11690 | ||
11691 | reject_bad_reg (Rd); | |
11692 | reject_bad_reg (Rn); | |
11693 | ||
11694 | inst.instruction |= Rd << 8; | |
3a21c15a | 11695 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 11696 | inst.instruction |= Rn << 16; |
b99bd4ef | 11697 | |
c19d1205 | 11698 | if (inst.operands[3].present) |
b99bd4ef | 11699 | { |
3a21c15a NC |
11700 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
11701 | ||
11702 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11703 | ||
c19d1205 ZW |
11704 | constraint (inst.reloc.exp.X_op != O_constant, |
11705 | _("expression too complex")); | |
b99bd4ef | 11706 | |
3a21c15a | 11707 | if (shift_amount != 0) |
6189168b | 11708 | { |
3a21c15a NC |
11709 | constraint (shift_amount > 31, |
11710 | _("shift expression is too large")); | |
11711 | ||
c19d1205 | 11712 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
11713 | inst.instruction |= 0x00200000; /* sh bit. */ |
11714 | ||
11715 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
11716 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
11717 | } |
11718 | } | |
b99bd4ef | 11719 | } |
c921be7d | 11720 | |
3a21c15a NC |
11721 | static void |
11722 | do_t_ssat (void) | |
11723 | { | |
11724 | do_t_ssat_usat (1); | |
11725 | } | |
b99bd4ef | 11726 | |
0dd132b6 | 11727 | static void |
c19d1205 | 11728 | do_t_ssat16 (void) |
0dd132b6 | 11729 | { |
fdfde340 JM |
11730 | unsigned Rd, Rn; |
11731 | ||
11732 | Rd = inst.operands[0].reg; | |
11733 | Rn = inst.operands[2].reg; | |
11734 | ||
11735 | reject_bad_reg (Rd); | |
11736 | reject_bad_reg (Rn); | |
11737 | ||
11738 | inst.instruction |= Rd << 8; | |
c19d1205 | 11739 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 11740 | inst.instruction |= Rn << 16; |
c19d1205 | 11741 | } |
0dd132b6 | 11742 | |
c19d1205 ZW |
11743 | static void |
11744 | do_t_strex (void) | |
11745 | { | |
11746 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
11747 | || inst.operands[2].postind || inst.operands[2].writeback | |
11748 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
11749 | || inst.operands[2].negative, | |
01cfc07f | 11750 | BAD_ADDR_MODE); |
0dd132b6 | 11751 | |
5be8be5d DG |
11752 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
11753 | ||
c19d1205 ZW |
11754 | inst.instruction |= inst.operands[0].reg << 8; |
11755 | inst.instruction |= inst.operands[1].reg << 12; | |
11756 | inst.instruction |= inst.operands[2].reg << 16; | |
11757 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
11758 | } |
11759 | ||
b99bd4ef | 11760 | static void |
c19d1205 | 11761 | do_t_strexd (void) |
b99bd4ef | 11762 | { |
c19d1205 ZW |
11763 | if (!inst.operands[2].present) |
11764 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 11765 | |
c19d1205 ZW |
11766 | constraint (inst.operands[0].reg == inst.operands[1].reg |
11767 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 11768 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 11769 | BAD_OVERLAP); |
b99bd4ef | 11770 | |
c19d1205 ZW |
11771 | inst.instruction |= inst.operands[0].reg; |
11772 | inst.instruction |= inst.operands[1].reg << 12; | |
11773 | inst.instruction |= inst.operands[2].reg << 8; | |
11774 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
11775 | } |
11776 | ||
11777 | static void | |
c19d1205 | 11778 | do_t_sxtah (void) |
b99bd4ef | 11779 | { |
fdfde340 JM |
11780 | unsigned Rd, Rn, Rm; |
11781 | ||
11782 | Rd = inst.operands[0].reg; | |
11783 | Rn = inst.operands[1].reg; | |
11784 | Rm = inst.operands[2].reg; | |
11785 | ||
11786 | reject_bad_reg (Rd); | |
11787 | reject_bad_reg (Rn); | |
11788 | reject_bad_reg (Rm); | |
11789 | ||
11790 | inst.instruction |= Rd << 8; | |
11791 | inst.instruction |= Rn << 16; | |
11792 | inst.instruction |= Rm; | |
c19d1205 ZW |
11793 | inst.instruction |= inst.operands[3].imm << 4; |
11794 | } | |
b99bd4ef | 11795 | |
c19d1205 ZW |
11796 | static void |
11797 | do_t_sxth (void) | |
11798 | { | |
fdfde340 JM |
11799 | unsigned Rd, Rm; |
11800 | ||
11801 | Rd = inst.operands[0].reg; | |
11802 | Rm = inst.operands[1].reg; | |
11803 | ||
11804 | reject_bad_reg (Rd); | |
11805 | reject_bad_reg (Rm); | |
c921be7d NC |
11806 | |
11807 | if (inst.instruction <= 0xffff | |
11808 | && inst.size_req != 4 | |
fdfde340 | 11809 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 11810 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 11811 | { |
c19d1205 | 11812 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11813 | inst.instruction |= Rd; |
11814 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11815 | } |
c19d1205 | 11816 | else if (unified_syntax) |
b99bd4ef | 11817 | { |
c19d1205 ZW |
11818 | if (inst.instruction <= 0xffff) |
11819 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11820 | inst.instruction |= Rd << 8; |
11821 | inst.instruction |= Rm; | |
c19d1205 | 11822 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 11823 | } |
c19d1205 | 11824 | else |
b99bd4ef | 11825 | { |
c19d1205 ZW |
11826 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
11827 | _("Thumb encoding does not support rotation")); | |
11828 | constraint (1, BAD_HIREG); | |
b99bd4ef | 11829 | } |
c19d1205 | 11830 | } |
b99bd4ef | 11831 | |
c19d1205 ZW |
11832 | static void |
11833 | do_t_swi (void) | |
11834 | { | |
b2a5fbdc MGD |
11835 | /* We have to do the following check manually as ARM_EXT_OS only applies |
11836 | to ARM_EXT_V6M. */ | |
11837 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) | |
11838 | { | |
ac7f631b NC |
11839 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) |
11840 | /* This only applies to the v6m howver, not later architectures. */ | |
11841 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) | |
b2a5fbdc MGD |
11842 | as_bad (_("SVC is not permitted on this architecture")); |
11843 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); | |
11844 | } | |
11845 | ||
c19d1205 ZW |
11846 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
11847 | } | |
b99bd4ef | 11848 | |
92e90b6e PB |
11849 | static void |
11850 | do_t_tb (void) | |
11851 | { | |
fdfde340 | 11852 | unsigned Rn, Rm; |
92e90b6e PB |
11853 | int half; |
11854 | ||
11855 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 11856 | set_it_insn_type_last (); |
dfa9f0d5 PB |
11857 | constraint (inst.operands[0].immisreg, |
11858 | _("instruction requires register index")); | |
fdfde340 JM |
11859 | |
11860 | Rn = inst.operands[0].reg; | |
11861 | Rm = inst.operands[0].imm; | |
c921be7d | 11862 | |
fdfde340 JM |
11863 | constraint (Rn == REG_SP, BAD_SP); |
11864 | reject_bad_reg (Rm); | |
11865 | ||
92e90b6e PB |
11866 | constraint (!half && inst.operands[0].shifted, |
11867 | _("instruction does not allow shifted index")); | |
fdfde340 | 11868 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
11869 | } |
11870 | ||
c19d1205 ZW |
11871 | static void |
11872 | do_t_usat (void) | |
11873 | { | |
3a21c15a | 11874 | do_t_ssat_usat (0); |
b99bd4ef NC |
11875 | } |
11876 | ||
11877 | static void | |
c19d1205 | 11878 | do_t_usat16 (void) |
b99bd4ef | 11879 | { |
fdfde340 JM |
11880 | unsigned Rd, Rn; |
11881 | ||
11882 | Rd = inst.operands[0].reg; | |
11883 | Rn = inst.operands[2].reg; | |
11884 | ||
11885 | reject_bad_reg (Rd); | |
11886 | reject_bad_reg (Rn); | |
11887 | ||
11888 | inst.instruction |= Rd << 8; | |
c19d1205 | 11889 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 11890 | inst.instruction |= Rn << 16; |
b99bd4ef | 11891 | } |
c19d1205 | 11892 | |
5287ad62 | 11893 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 11894 | |
5287ad62 | 11895 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 11896 | |
5287ad62 JB |
11897 | /* An "invalid" code for the following tables. */ |
11898 | #define N_INV -1u | |
11899 | ||
11900 | struct neon_tab_entry | |
b99bd4ef | 11901 | { |
5287ad62 JB |
11902 | unsigned integer; |
11903 | unsigned float_or_poly; | |
11904 | unsigned scalar_or_imm; | |
11905 | }; | |
5f4273c7 | 11906 | |
5287ad62 JB |
11907 | /* Map overloaded Neon opcodes to their respective encodings. */ |
11908 | #define NEON_ENC_TAB \ | |
11909 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
11910 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
11911 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
11912 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
11913 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
11914 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
11915 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
11916 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
11917 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
11918 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
11919 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
11920 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 11921 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
11922 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
11923 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
11924 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
11925 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
11926 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
11927 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
11928 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
11929 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
11930 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
11931 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
11932 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
11933 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
11934 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
11935 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
11936 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
11937 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
11938 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
11939 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
11940 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
11941 | X(veor, 0x1000110, N_INV, N_INV), \ | |
11942 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
11943 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
11944 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
11945 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
11946 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
11947 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
11948 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
11949 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
11950 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
11951 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
11952 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
11953 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
11954 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
11955 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
11956 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
11957 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
11958 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
11959 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
11960 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
11961 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
11962 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
11963 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
11964 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
11965 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
11966 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
11967 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
11968 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) | |
5287ad62 JB |
11969 | |
11970 | enum neon_opc | |
11971 | { | |
11972 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
11973 | NEON_ENC_TAB | |
11974 | #undef X | |
11975 | }; | |
b99bd4ef | 11976 | |
5287ad62 JB |
11977 | static const struct neon_tab_entry neon_enc_tab[] = |
11978 | { | |
11979 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
11980 | NEON_ENC_TAB | |
11981 | #undef X | |
11982 | }; | |
b99bd4ef | 11983 | |
88714cb8 DG |
11984 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
11985 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11986 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11987 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11988 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11989 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11990 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11991 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
11992 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
11993 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
11994 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 11995 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 11996 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 11997 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
5287ad62 | 11998 | |
88714cb8 DG |
11999 | #define NEON_ENCODE(type, inst) \ |
12000 | do \ | |
12001 | { \ | |
12002 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
12003 | inst.is_neon = 1; \ | |
12004 | } \ | |
12005 | while (0) | |
12006 | ||
12007 | #define check_neon_suffixes \ | |
12008 | do \ | |
12009 | { \ | |
12010 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
12011 | { \ | |
12012 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
12013 | return; \ | |
12014 | } \ | |
12015 | } \ | |
12016 | while (0) | |
12017 | ||
037e8744 JB |
12018 | /* Define shapes for instruction operands. The following mnemonic characters |
12019 | are used in this table: | |
5287ad62 | 12020 | |
037e8744 | 12021 | F - VFP S<n> register |
5287ad62 JB |
12022 | D - Neon D<n> register |
12023 | Q - Neon Q<n> register | |
12024 | I - Immediate | |
12025 | S - Scalar | |
12026 | R - ARM register | |
12027 | L - D<n> register list | |
5f4273c7 | 12028 | |
037e8744 JB |
12029 | This table is used to generate various data: |
12030 | - enumerations of the form NS_DDR to be used as arguments to | |
12031 | neon_select_shape. | |
12032 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 12033 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 12034 | |
037e8744 JB |
12035 | #define NEON_SHAPE_DEF \ |
12036 | X(3, (D, D, D), DOUBLE), \ | |
12037 | X(3, (Q, Q, Q), QUAD), \ | |
12038 | X(3, (D, D, I), DOUBLE), \ | |
12039 | X(3, (Q, Q, I), QUAD), \ | |
12040 | X(3, (D, D, S), DOUBLE), \ | |
12041 | X(3, (Q, Q, S), QUAD), \ | |
12042 | X(2, (D, D), DOUBLE), \ | |
12043 | X(2, (Q, Q), QUAD), \ | |
12044 | X(2, (D, S), DOUBLE), \ | |
12045 | X(2, (Q, S), QUAD), \ | |
12046 | X(2, (D, R), DOUBLE), \ | |
12047 | X(2, (Q, R), QUAD), \ | |
12048 | X(2, (D, I), DOUBLE), \ | |
12049 | X(2, (Q, I), QUAD), \ | |
12050 | X(3, (D, L, D), DOUBLE), \ | |
12051 | X(2, (D, Q), MIXED), \ | |
12052 | X(2, (Q, D), MIXED), \ | |
12053 | X(3, (D, Q, I), MIXED), \ | |
12054 | X(3, (Q, D, I), MIXED), \ | |
12055 | X(3, (Q, D, D), MIXED), \ | |
12056 | X(3, (D, Q, Q), MIXED), \ | |
12057 | X(3, (Q, Q, D), MIXED), \ | |
12058 | X(3, (Q, D, S), MIXED), \ | |
12059 | X(3, (D, Q, S), MIXED), \ | |
12060 | X(4, (D, D, D, I), DOUBLE), \ | |
12061 | X(4, (Q, Q, Q, I), QUAD), \ | |
12062 | X(2, (F, F), SINGLE), \ | |
12063 | X(3, (F, F, F), SINGLE), \ | |
12064 | X(2, (F, I), SINGLE), \ | |
12065 | X(2, (F, D), MIXED), \ | |
12066 | X(2, (D, F), MIXED), \ | |
12067 | X(3, (F, F, I), MIXED), \ | |
12068 | X(4, (R, R, F, F), SINGLE), \ | |
12069 | X(4, (F, F, R, R), SINGLE), \ | |
12070 | X(3, (D, R, R), DOUBLE), \ | |
12071 | X(3, (R, R, D), DOUBLE), \ | |
12072 | X(2, (S, R), SINGLE), \ | |
12073 | X(2, (R, S), SINGLE), \ | |
12074 | X(2, (F, R), SINGLE), \ | |
12075 | X(2, (R, F), SINGLE) | |
12076 | ||
12077 | #define S2(A,B) NS_##A##B | |
12078 | #define S3(A,B,C) NS_##A##B##C | |
12079 | #define S4(A,B,C,D) NS_##A##B##C##D | |
12080 | ||
12081 | #define X(N, L, C) S##N L | |
12082 | ||
5287ad62 JB |
12083 | enum neon_shape |
12084 | { | |
037e8744 JB |
12085 | NEON_SHAPE_DEF, |
12086 | NS_NULL | |
5287ad62 | 12087 | }; |
b99bd4ef | 12088 | |
037e8744 JB |
12089 | #undef X |
12090 | #undef S2 | |
12091 | #undef S3 | |
12092 | #undef S4 | |
12093 | ||
12094 | enum neon_shape_class | |
12095 | { | |
12096 | SC_SINGLE, | |
12097 | SC_DOUBLE, | |
12098 | SC_QUAD, | |
12099 | SC_MIXED | |
12100 | }; | |
12101 | ||
12102 | #define X(N, L, C) SC_##C | |
12103 | ||
12104 | static enum neon_shape_class neon_shape_class[] = | |
12105 | { | |
12106 | NEON_SHAPE_DEF | |
12107 | }; | |
12108 | ||
12109 | #undef X | |
12110 | ||
12111 | enum neon_shape_el | |
12112 | { | |
12113 | SE_F, | |
12114 | SE_D, | |
12115 | SE_Q, | |
12116 | SE_I, | |
12117 | SE_S, | |
12118 | SE_R, | |
12119 | SE_L | |
12120 | }; | |
12121 | ||
12122 | /* Register widths of above. */ | |
12123 | static unsigned neon_shape_el_size[] = | |
12124 | { | |
12125 | 32, | |
12126 | 64, | |
12127 | 128, | |
12128 | 0, | |
12129 | 32, | |
12130 | 32, | |
12131 | 0 | |
12132 | }; | |
12133 | ||
12134 | struct neon_shape_info | |
12135 | { | |
12136 | unsigned els; | |
12137 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
12138 | }; | |
12139 | ||
12140 | #define S2(A,B) { SE_##A, SE_##B } | |
12141 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
12142 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
12143 | ||
12144 | #define X(N, L, C) { N, S##N L } | |
12145 | ||
12146 | static struct neon_shape_info neon_shape_tab[] = | |
12147 | { | |
12148 | NEON_SHAPE_DEF | |
12149 | }; | |
12150 | ||
12151 | #undef X | |
12152 | #undef S2 | |
12153 | #undef S3 | |
12154 | #undef S4 | |
12155 | ||
5287ad62 JB |
12156 | /* Bit masks used in type checking given instructions. |
12157 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
12158 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
12159 | set, various other bits can be set as well in order to modify the meaning of | |
12160 | the type constraint. */ | |
12161 | ||
12162 | enum neon_type_mask | |
12163 | { | |
8e79c3df CM |
12164 | N_S8 = 0x0000001, |
12165 | N_S16 = 0x0000002, | |
12166 | N_S32 = 0x0000004, | |
12167 | N_S64 = 0x0000008, | |
12168 | N_U8 = 0x0000010, | |
12169 | N_U16 = 0x0000020, | |
12170 | N_U32 = 0x0000040, | |
12171 | N_U64 = 0x0000080, | |
12172 | N_I8 = 0x0000100, | |
12173 | N_I16 = 0x0000200, | |
12174 | N_I32 = 0x0000400, | |
12175 | N_I64 = 0x0000800, | |
12176 | N_8 = 0x0001000, | |
12177 | N_16 = 0x0002000, | |
12178 | N_32 = 0x0004000, | |
12179 | N_64 = 0x0008000, | |
12180 | N_P8 = 0x0010000, | |
12181 | N_P16 = 0x0020000, | |
12182 | N_F16 = 0x0040000, | |
12183 | N_F32 = 0x0080000, | |
12184 | N_F64 = 0x0100000, | |
c921be7d NC |
12185 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
12186 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 12187 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
c921be7d NC |
12188 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
12189 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
12190 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
12191 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
12192 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
12193 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
12194 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 12195 | N_UTYP = 0, |
037e8744 | 12196 | N_MAX_NONSPECIAL = N_F64 |
5287ad62 JB |
12197 | }; |
12198 | ||
dcbf9037 JB |
12199 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
12200 | ||
5287ad62 JB |
12201 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
12202 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
12203 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
12204 | #define N_SUF_32 (N_SU_32 | N_F32) | |
12205 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
12206 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
12207 | ||
12208 | /* Pass this as the first type argument to neon_check_type to ignore types | |
12209 | altogether. */ | |
12210 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
12211 | ||
037e8744 JB |
12212 | /* Select a "shape" for the current instruction (describing register types or |
12213 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
12214 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
12215 | function of operand parsing, so this function doesn't need to be called. | |
12216 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
12217 | |
12218 | static enum neon_shape | |
037e8744 | 12219 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 12220 | { |
037e8744 JB |
12221 | va_list ap; |
12222 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
12223 | |
12224 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
12225 | many arguments we should have, so this makes the assumption that we have | |
12226 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
12227 | true in the future. */ | |
12228 | if (!inst.operands[1].present) | |
12229 | inst.operands[1] = inst.operands[0]; | |
12230 | ||
037e8744 | 12231 | va_start (ap, shape); |
5f4273c7 | 12232 | |
21d799b5 | 12233 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
12234 | { |
12235 | unsigned j; | |
12236 | int matches = 1; | |
12237 | ||
12238 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
12239 | { | |
12240 | if (!inst.operands[j].present) | |
12241 | { | |
12242 | matches = 0; | |
12243 | break; | |
12244 | } | |
12245 | ||
12246 | switch (neon_shape_tab[shape].el[j]) | |
12247 | { | |
12248 | case SE_F: | |
12249 | if (!(inst.operands[j].isreg | |
12250 | && inst.operands[j].isvec | |
12251 | && inst.operands[j].issingle | |
12252 | && !inst.operands[j].isquad)) | |
12253 | matches = 0; | |
12254 | break; | |
12255 | ||
12256 | case SE_D: | |
12257 | if (!(inst.operands[j].isreg | |
12258 | && inst.operands[j].isvec | |
12259 | && !inst.operands[j].isquad | |
12260 | && !inst.operands[j].issingle)) | |
12261 | matches = 0; | |
12262 | break; | |
12263 | ||
12264 | case SE_R: | |
12265 | if (!(inst.operands[j].isreg | |
12266 | && !inst.operands[j].isvec)) | |
12267 | matches = 0; | |
12268 | break; | |
12269 | ||
12270 | case SE_Q: | |
12271 | if (!(inst.operands[j].isreg | |
12272 | && inst.operands[j].isvec | |
12273 | && inst.operands[j].isquad | |
12274 | && !inst.operands[j].issingle)) | |
12275 | matches = 0; | |
12276 | break; | |
12277 | ||
12278 | case SE_I: | |
12279 | if (!(!inst.operands[j].isreg | |
12280 | && !inst.operands[j].isscalar)) | |
12281 | matches = 0; | |
12282 | break; | |
12283 | ||
12284 | case SE_S: | |
12285 | if (!(!inst.operands[j].isreg | |
12286 | && inst.operands[j].isscalar)) | |
12287 | matches = 0; | |
12288 | break; | |
12289 | ||
12290 | case SE_L: | |
12291 | break; | |
12292 | } | |
3fde54a2 JZ |
12293 | if (!matches) |
12294 | break; | |
037e8744 JB |
12295 | } |
12296 | if (matches) | |
5287ad62 | 12297 | break; |
037e8744 | 12298 | } |
5f4273c7 | 12299 | |
037e8744 | 12300 | va_end (ap); |
5287ad62 | 12301 | |
037e8744 JB |
12302 | if (shape == NS_NULL && first_shape != NS_NULL) |
12303 | first_error (_("invalid instruction shape")); | |
5287ad62 | 12304 | |
037e8744 JB |
12305 | return shape; |
12306 | } | |
5287ad62 | 12307 | |
037e8744 JB |
12308 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
12309 | means the Q bit should be set). */ | |
12310 | ||
12311 | static int | |
12312 | neon_quad (enum neon_shape shape) | |
12313 | { | |
12314 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 12315 | } |
037e8744 | 12316 | |
5287ad62 JB |
12317 | static void |
12318 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
12319 | unsigned *g_size) | |
12320 | { | |
12321 | /* Allow modification to be made to types which are constrained to be | |
12322 | based on the key element, based on bits set alongside N_EQK. */ | |
12323 | if ((typebits & N_EQK) != 0) | |
12324 | { | |
12325 | if ((typebits & N_HLF) != 0) | |
12326 | *g_size /= 2; | |
12327 | else if ((typebits & N_DBL) != 0) | |
12328 | *g_size *= 2; | |
12329 | if ((typebits & N_SGN) != 0) | |
12330 | *g_type = NT_signed; | |
12331 | else if ((typebits & N_UNS) != 0) | |
12332 | *g_type = NT_unsigned; | |
12333 | else if ((typebits & N_INT) != 0) | |
12334 | *g_type = NT_integer; | |
12335 | else if ((typebits & N_FLT) != 0) | |
12336 | *g_type = NT_float; | |
dcbf9037 JB |
12337 | else if ((typebits & N_SIZ) != 0) |
12338 | *g_type = NT_untyped; | |
5287ad62 JB |
12339 | } |
12340 | } | |
5f4273c7 | 12341 | |
5287ad62 JB |
12342 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
12343 | operand type, i.e. the single type specified in a Neon instruction when it | |
12344 | is the only one given. */ | |
12345 | ||
12346 | static struct neon_type_el | |
12347 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
12348 | { | |
12349 | struct neon_type_el dest = *key; | |
5f4273c7 | 12350 | |
9c2799c2 | 12351 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 12352 | |
5287ad62 JB |
12353 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
12354 | ||
12355 | return dest; | |
12356 | } | |
12357 | ||
12358 | /* Convert Neon type and size into compact bitmask representation. */ | |
12359 | ||
12360 | static enum neon_type_mask | |
12361 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
12362 | { | |
12363 | switch (type) | |
12364 | { | |
12365 | case NT_untyped: | |
12366 | switch (size) | |
12367 | { | |
12368 | case 8: return N_8; | |
12369 | case 16: return N_16; | |
12370 | case 32: return N_32; | |
12371 | case 64: return N_64; | |
12372 | default: ; | |
12373 | } | |
12374 | break; | |
12375 | ||
12376 | case NT_integer: | |
12377 | switch (size) | |
12378 | { | |
12379 | case 8: return N_I8; | |
12380 | case 16: return N_I16; | |
12381 | case 32: return N_I32; | |
12382 | case 64: return N_I64; | |
12383 | default: ; | |
12384 | } | |
12385 | break; | |
12386 | ||
12387 | case NT_float: | |
037e8744 JB |
12388 | switch (size) |
12389 | { | |
8e79c3df | 12390 | case 16: return N_F16; |
037e8744 JB |
12391 | case 32: return N_F32; |
12392 | case 64: return N_F64; | |
12393 | default: ; | |
12394 | } | |
5287ad62 JB |
12395 | break; |
12396 | ||
12397 | case NT_poly: | |
12398 | switch (size) | |
12399 | { | |
12400 | case 8: return N_P8; | |
12401 | case 16: return N_P16; | |
12402 | default: ; | |
12403 | } | |
12404 | break; | |
12405 | ||
12406 | case NT_signed: | |
12407 | switch (size) | |
12408 | { | |
12409 | case 8: return N_S8; | |
12410 | case 16: return N_S16; | |
12411 | case 32: return N_S32; | |
12412 | case 64: return N_S64; | |
12413 | default: ; | |
12414 | } | |
12415 | break; | |
12416 | ||
12417 | case NT_unsigned: | |
12418 | switch (size) | |
12419 | { | |
12420 | case 8: return N_U8; | |
12421 | case 16: return N_U16; | |
12422 | case 32: return N_U32; | |
12423 | case 64: return N_U64; | |
12424 | default: ; | |
12425 | } | |
12426 | break; | |
12427 | ||
12428 | default: ; | |
12429 | } | |
5f4273c7 | 12430 | |
5287ad62 JB |
12431 | return N_UTYP; |
12432 | } | |
12433 | ||
12434 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
12435 | handles the case where a single bit is set in the mask. */ | |
12436 | ||
dcbf9037 | 12437 | static int |
5287ad62 JB |
12438 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
12439 | enum neon_type_mask mask) | |
12440 | { | |
dcbf9037 JB |
12441 | if ((mask & N_EQK) != 0) |
12442 | return FAIL; | |
12443 | ||
5287ad62 JB |
12444 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
12445 | *size = 8; | |
dcbf9037 | 12446 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) |
5287ad62 | 12447 | *size = 16; |
dcbf9037 | 12448 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 12449 | *size = 32; |
037e8744 | 12450 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) |
5287ad62 | 12451 | *size = 64; |
dcbf9037 JB |
12452 | else |
12453 | return FAIL; | |
12454 | ||
5287ad62 JB |
12455 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
12456 | *type = NT_signed; | |
dcbf9037 | 12457 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 12458 | *type = NT_unsigned; |
dcbf9037 | 12459 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 12460 | *type = NT_integer; |
dcbf9037 | 12461 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 12462 | *type = NT_untyped; |
dcbf9037 | 12463 | else if ((mask & (N_P8 | N_P16)) != 0) |
5287ad62 | 12464 | *type = NT_poly; |
037e8744 | 12465 | else if ((mask & (N_F32 | N_F64)) != 0) |
5287ad62 | 12466 | *type = NT_float; |
dcbf9037 JB |
12467 | else |
12468 | return FAIL; | |
5f4273c7 | 12469 | |
dcbf9037 | 12470 | return SUCCESS; |
5287ad62 JB |
12471 | } |
12472 | ||
12473 | /* Modify a bitmask of allowed types. This is only needed for type | |
12474 | relaxation. */ | |
12475 | ||
12476 | static unsigned | |
12477 | modify_types_allowed (unsigned allowed, unsigned mods) | |
12478 | { | |
12479 | unsigned size; | |
12480 | enum neon_el_type type; | |
12481 | unsigned destmask; | |
12482 | int i; | |
5f4273c7 | 12483 | |
5287ad62 | 12484 | destmask = 0; |
5f4273c7 | 12485 | |
5287ad62 JB |
12486 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
12487 | { | |
21d799b5 NC |
12488 | if (el_type_of_type_chk (&type, &size, |
12489 | (enum neon_type_mask) (allowed & i)) == SUCCESS) | |
dcbf9037 JB |
12490 | { |
12491 | neon_modify_type_size (mods, &type, &size); | |
12492 | destmask |= type_chk_of_el_type (type, size); | |
12493 | } | |
5287ad62 | 12494 | } |
5f4273c7 | 12495 | |
5287ad62 JB |
12496 | return destmask; |
12497 | } | |
12498 | ||
12499 | /* Check type and return type classification. | |
12500 | The manual states (paraphrase): If one datatype is given, it indicates the | |
12501 | type given in: | |
12502 | - the second operand, if there is one | |
12503 | - the operand, if there is no second operand | |
12504 | - the result, if there are no operands. | |
12505 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
12506 | which is set on a per-instruction basis, which is the one which matters when | |
12507 | only one data type is written. | |
12508 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 12509 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
12510 | |
12511 | static struct neon_type_el | |
12512 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
12513 | { | |
12514 | va_list ap; | |
12515 | unsigned i, pass, key_el = 0; | |
12516 | unsigned types[NEON_MAX_TYPE_ELS]; | |
12517 | enum neon_el_type k_type = NT_invtype; | |
12518 | unsigned k_size = -1u; | |
12519 | struct neon_type_el badtype = {NT_invtype, -1}; | |
12520 | unsigned key_allowed = 0; | |
12521 | ||
12522 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
12523 | Fill in the missing operand here, if it was omitted. */ | |
12524 | if (els > 1 && !inst.operands[1].present) | |
12525 | inst.operands[1] = inst.operands[0]; | |
12526 | ||
12527 | /* Suck up all the varargs. */ | |
12528 | va_start (ap, ns); | |
12529 | for (i = 0; i < els; i++) | |
12530 | { | |
12531 | unsigned thisarg = va_arg (ap, unsigned); | |
12532 | if (thisarg == N_IGNORE_TYPE) | |
12533 | { | |
12534 | va_end (ap); | |
12535 | return badtype; | |
12536 | } | |
12537 | types[i] = thisarg; | |
12538 | if ((thisarg & N_KEY) != 0) | |
12539 | key_el = i; | |
12540 | } | |
12541 | va_end (ap); | |
12542 | ||
dcbf9037 JB |
12543 | if (inst.vectype.elems > 0) |
12544 | for (i = 0; i < els; i++) | |
12545 | if (inst.operands[i].vectype.type != NT_invtype) | |
12546 | { | |
12547 | first_error (_("types specified in both the mnemonic and operands")); | |
12548 | return badtype; | |
12549 | } | |
12550 | ||
5287ad62 JB |
12551 | /* Duplicate inst.vectype elements here as necessary. |
12552 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
12553 | particularly when an insn takes one register and one non-register | |
12554 | operand. */ | |
12555 | if (inst.vectype.elems == 1 && els > 1) | |
12556 | { | |
12557 | unsigned j; | |
12558 | inst.vectype.elems = els; | |
12559 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
12560 | for (j = 0; j < els; j++) | |
dcbf9037 JB |
12561 | if (j != key_el) |
12562 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12563 | types[j]); | |
12564 | } | |
12565 | else if (inst.vectype.elems == 0 && els > 0) | |
12566 | { | |
12567 | unsigned j; | |
12568 | /* No types were given after the mnemonic, so look for types specified | |
12569 | after each operand. We allow some flexibility here; as long as the | |
12570 | "key" operand has a type, we can infer the others. */ | |
12571 | for (j = 0; j < els; j++) | |
12572 | if (inst.operands[j].vectype.type != NT_invtype) | |
12573 | inst.vectype.el[j] = inst.operands[j].vectype; | |
12574 | ||
12575 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
5287ad62 | 12576 | { |
dcbf9037 JB |
12577 | for (j = 0; j < els; j++) |
12578 | if (inst.operands[j].vectype.type == NT_invtype) | |
12579 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12580 | types[j]); | |
12581 | } | |
12582 | else | |
12583 | { | |
12584 | first_error (_("operand types can't be inferred")); | |
12585 | return badtype; | |
5287ad62 JB |
12586 | } |
12587 | } | |
12588 | else if (inst.vectype.elems != els) | |
12589 | { | |
dcbf9037 | 12590 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
12591 | return badtype; |
12592 | } | |
12593 | ||
12594 | for (pass = 0; pass < 2; pass++) | |
12595 | { | |
12596 | for (i = 0; i < els; i++) | |
12597 | { | |
12598 | unsigned thisarg = types[i]; | |
12599 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
12600 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
12601 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
12602 | unsigned g_size = inst.vectype.el[i].size; | |
12603 | ||
12604 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
12605 | integer types if sign-specific variants are unavailable. */ | |
12606 | if ((g_type == NT_signed || g_type == NT_unsigned) | |
12607 | && (types_allowed & N_SU_ALL) == 0) | |
12608 | g_type = NT_integer; | |
12609 | ||
12610 | /* If only untyped args are allowed, decay any more specific types to | |
12611 | them. Some instructions only care about signs for some element | |
12612 | sizes, so handle that properly. */ | |
12613 | if ((g_size == 8 && (types_allowed & N_8) != 0) | |
12614 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
12615 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
12616 | || (g_size == 64 && (types_allowed & N_64) != 0)) | |
12617 | g_type = NT_untyped; | |
12618 | ||
12619 | if (pass == 0) | |
12620 | { | |
12621 | if ((thisarg & N_KEY) != 0) | |
12622 | { | |
12623 | k_type = g_type; | |
12624 | k_size = g_size; | |
12625 | key_allowed = thisarg & ~N_KEY; | |
12626 | } | |
12627 | } | |
12628 | else | |
12629 | { | |
037e8744 JB |
12630 | if ((thisarg & N_VFP) != 0) |
12631 | { | |
99b253c5 NC |
12632 | enum neon_shape_el regshape; |
12633 | unsigned regwidth, match; | |
12634 | ||
12635 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
12636 | if (ns == NS_NULL) | |
12637 | { | |
12638 | first_error (_("invalid instruction shape")); | |
12639 | return badtype; | |
12640 | } | |
12641 | regshape = neon_shape_tab[ns].el[i]; | |
12642 | regwidth = neon_shape_el_size[regshape]; | |
037e8744 JB |
12643 | |
12644 | /* In VFP mode, operands must match register widths. If we | |
12645 | have a key operand, use its width, else use the width of | |
12646 | the current operand. */ | |
12647 | if (k_size != -1u) | |
12648 | match = k_size; | |
12649 | else | |
12650 | match = g_size; | |
12651 | ||
12652 | if (regwidth != match) | |
12653 | { | |
12654 | first_error (_("operand size must match register width")); | |
12655 | return badtype; | |
12656 | } | |
12657 | } | |
5f4273c7 | 12658 | |
5287ad62 JB |
12659 | if ((thisarg & N_EQK) == 0) |
12660 | { | |
12661 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
12662 | ||
12663 | if ((given_type & types_allowed) == 0) | |
12664 | { | |
dcbf9037 | 12665 | first_error (_("bad type in Neon instruction")); |
5287ad62 JB |
12666 | return badtype; |
12667 | } | |
12668 | } | |
12669 | else | |
12670 | { | |
12671 | enum neon_el_type mod_k_type = k_type; | |
12672 | unsigned mod_k_size = k_size; | |
12673 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
12674 | if (g_type != mod_k_type || g_size != mod_k_size) | |
12675 | { | |
dcbf9037 | 12676 | first_error (_("inconsistent types in Neon instruction")); |
5287ad62 JB |
12677 | return badtype; |
12678 | } | |
12679 | } | |
12680 | } | |
12681 | } | |
12682 | } | |
12683 | ||
12684 | return inst.vectype.el[key_el]; | |
12685 | } | |
12686 | ||
037e8744 | 12687 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 12688 | |
037e8744 JB |
12689 | /* Thumb VFP instructions have 0xE in the condition field. */ |
12690 | ||
12691 | static void | |
12692 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 12693 | { |
88714cb8 DG |
12694 | inst.is_neon = 1; |
12695 | ||
5287ad62 | 12696 | if (thumb_mode) |
037e8744 | 12697 | inst.instruction |= 0xe0000000; |
5287ad62 | 12698 | else |
037e8744 | 12699 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
12700 | } |
12701 | ||
037e8744 JB |
12702 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
12703 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
12704 | etc. It is assumed that operand parsing has already been done, and that the | |
12705 | operands are in the form expected by the given opcode (this isn't necessarily | |
12706 | the same as the form in which they were parsed, hence some massaging must | |
12707 | take place before this function is called). | |
12708 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 12709 | |
037e8744 JB |
12710 | static void |
12711 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 12712 | { |
037e8744 | 12713 | const struct asm_opcode *opcode; |
5f4273c7 | 12714 | |
21d799b5 | 12715 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 12716 | |
037e8744 JB |
12717 | if (!opcode) |
12718 | abort (); | |
5287ad62 | 12719 | |
037e8744 JB |
12720 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
12721 | thumb_mode ? *opcode->tvariant : *opcode->avariant), | |
12722 | _(BAD_FPU)); | |
5287ad62 | 12723 | |
88714cb8 DG |
12724 | inst.is_neon = 1; |
12725 | ||
037e8744 JB |
12726 | if (thumb_mode) |
12727 | { | |
12728 | inst.instruction = opcode->tvalue; | |
12729 | opcode->tencode (); | |
12730 | } | |
12731 | else | |
12732 | { | |
12733 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
12734 | opcode->aencode (); | |
12735 | } | |
12736 | } | |
5287ad62 JB |
12737 | |
12738 | static void | |
037e8744 | 12739 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 12740 | { |
037e8744 JB |
12741 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
12742 | ||
12743 | if (rs == NS_FFF) | |
12744 | { | |
12745 | if (is_add) | |
12746 | do_vfp_nsyn_opcode ("fadds"); | |
12747 | else | |
12748 | do_vfp_nsyn_opcode ("fsubs"); | |
12749 | } | |
12750 | else | |
12751 | { | |
12752 | if (is_add) | |
12753 | do_vfp_nsyn_opcode ("faddd"); | |
12754 | else | |
12755 | do_vfp_nsyn_opcode ("fsubd"); | |
12756 | } | |
12757 | } | |
12758 | ||
12759 | /* Check operand types to see if this is a VFP instruction, and if so call | |
12760 | PFN (). */ | |
12761 | ||
12762 | static int | |
12763 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
12764 | { | |
12765 | enum neon_shape rs; | |
12766 | struct neon_type_el et; | |
12767 | ||
12768 | switch (args) | |
12769 | { | |
12770 | case 2: | |
12771 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12772 | et = neon_check_type (2, rs, | |
12773 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12774 | break; | |
5f4273c7 | 12775 | |
037e8744 JB |
12776 | case 3: |
12777 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12778 | et = neon_check_type (3, rs, | |
12779 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12780 | break; | |
12781 | ||
12782 | default: | |
12783 | abort (); | |
12784 | } | |
12785 | ||
12786 | if (et.type != NT_invtype) | |
12787 | { | |
12788 | pfn (rs); | |
12789 | return SUCCESS; | |
12790 | } | |
037e8744 | 12791 | |
99b253c5 | 12792 | inst.error = NULL; |
037e8744 JB |
12793 | return FAIL; |
12794 | } | |
12795 | ||
12796 | static void | |
12797 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
12798 | { | |
12799 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 12800 | |
037e8744 JB |
12801 | if (rs == NS_FFF) |
12802 | { | |
12803 | if (is_mla) | |
12804 | do_vfp_nsyn_opcode ("fmacs"); | |
12805 | else | |
1ee69515 | 12806 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
12807 | } |
12808 | else | |
12809 | { | |
12810 | if (is_mla) | |
12811 | do_vfp_nsyn_opcode ("fmacd"); | |
12812 | else | |
1ee69515 | 12813 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
12814 | } |
12815 | } | |
12816 | ||
62f3b8c8 PB |
12817 | static void |
12818 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
12819 | { | |
12820 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
12821 | ||
12822 | if (rs == NS_FFF) | |
12823 | { | |
12824 | if (is_fma) | |
12825 | do_vfp_nsyn_opcode ("ffmas"); | |
12826 | else | |
12827 | do_vfp_nsyn_opcode ("ffnmas"); | |
12828 | } | |
12829 | else | |
12830 | { | |
12831 | if (is_fma) | |
12832 | do_vfp_nsyn_opcode ("ffmad"); | |
12833 | else | |
12834 | do_vfp_nsyn_opcode ("ffnmad"); | |
12835 | } | |
12836 | } | |
12837 | ||
037e8744 JB |
12838 | static void |
12839 | do_vfp_nsyn_mul (enum neon_shape rs) | |
12840 | { | |
12841 | if (rs == NS_FFF) | |
12842 | do_vfp_nsyn_opcode ("fmuls"); | |
12843 | else | |
12844 | do_vfp_nsyn_opcode ("fmuld"); | |
12845 | } | |
12846 | ||
12847 | static void | |
12848 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
12849 | { | |
12850 | int is_neg = (inst.instruction & 0x80) != 0; | |
12851 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
12852 | ||
12853 | if (rs == NS_FF) | |
12854 | { | |
12855 | if (is_neg) | |
12856 | do_vfp_nsyn_opcode ("fnegs"); | |
12857 | else | |
12858 | do_vfp_nsyn_opcode ("fabss"); | |
12859 | } | |
12860 | else | |
12861 | { | |
12862 | if (is_neg) | |
12863 | do_vfp_nsyn_opcode ("fnegd"); | |
12864 | else | |
12865 | do_vfp_nsyn_opcode ("fabsd"); | |
12866 | } | |
12867 | } | |
12868 | ||
12869 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
12870 | insns belong to Neon, and are handled elsewhere. */ | |
12871 | ||
12872 | static void | |
12873 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
12874 | { | |
12875 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
12876 | if (is_ldm) | |
12877 | { | |
12878 | if (is_dbmode) | |
12879 | do_vfp_nsyn_opcode ("fldmdbs"); | |
12880 | else | |
12881 | do_vfp_nsyn_opcode ("fldmias"); | |
12882 | } | |
12883 | else | |
12884 | { | |
12885 | if (is_dbmode) | |
12886 | do_vfp_nsyn_opcode ("fstmdbs"); | |
12887 | else | |
12888 | do_vfp_nsyn_opcode ("fstmias"); | |
12889 | } | |
12890 | } | |
12891 | ||
037e8744 JB |
12892 | static void |
12893 | do_vfp_nsyn_sqrt (void) | |
12894 | { | |
12895 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12896 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12897 | |
037e8744 JB |
12898 | if (rs == NS_FF) |
12899 | do_vfp_nsyn_opcode ("fsqrts"); | |
12900 | else | |
12901 | do_vfp_nsyn_opcode ("fsqrtd"); | |
12902 | } | |
12903 | ||
12904 | static void | |
12905 | do_vfp_nsyn_div (void) | |
12906 | { | |
12907 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12908 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
12909 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12910 | |
037e8744 JB |
12911 | if (rs == NS_FFF) |
12912 | do_vfp_nsyn_opcode ("fdivs"); | |
12913 | else | |
12914 | do_vfp_nsyn_opcode ("fdivd"); | |
12915 | } | |
12916 | ||
12917 | static void | |
12918 | do_vfp_nsyn_nmul (void) | |
12919 | { | |
12920 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12921 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
12922 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12923 | |
037e8744 JB |
12924 | if (rs == NS_FFF) |
12925 | { | |
88714cb8 | 12926 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12927 | do_vfp_sp_dyadic (); |
12928 | } | |
12929 | else | |
12930 | { | |
88714cb8 | 12931 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12932 | do_vfp_dp_rd_rn_rm (); |
12933 | } | |
12934 | do_vfp_cond_or_thumb (); | |
12935 | } | |
12936 | ||
12937 | static void | |
12938 | do_vfp_nsyn_cmp (void) | |
12939 | { | |
12940 | if (inst.operands[1].isreg) | |
12941 | { | |
12942 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12943 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 12944 | |
037e8744 JB |
12945 | if (rs == NS_FF) |
12946 | { | |
88714cb8 | 12947 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12948 | do_vfp_sp_monadic (); |
12949 | } | |
12950 | else | |
12951 | { | |
88714cb8 | 12952 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12953 | do_vfp_dp_rd_rm (); |
12954 | } | |
12955 | } | |
12956 | else | |
12957 | { | |
12958 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
12959 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
12960 | ||
12961 | switch (inst.instruction & 0x0fffffff) | |
12962 | { | |
12963 | case N_MNEM_vcmp: | |
12964 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
12965 | break; | |
12966 | case N_MNEM_vcmpe: | |
12967 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
12968 | break; | |
12969 | default: | |
12970 | abort (); | |
12971 | } | |
5f4273c7 | 12972 | |
037e8744 JB |
12973 | if (rs == NS_FI) |
12974 | { | |
88714cb8 | 12975 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
12976 | do_vfp_sp_compare_z (); |
12977 | } | |
12978 | else | |
12979 | { | |
88714cb8 | 12980 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
12981 | do_vfp_dp_rd (); |
12982 | } | |
12983 | } | |
12984 | do_vfp_cond_or_thumb (); | |
12985 | } | |
12986 | ||
12987 | static void | |
12988 | nsyn_insert_sp (void) | |
12989 | { | |
12990 | inst.operands[1] = inst.operands[0]; | |
12991 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 12992 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
12993 | inst.operands[0].isreg = 1; |
12994 | inst.operands[0].writeback = 1; | |
12995 | inst.operands[0].present = 1; | |
12996 | } | |
12997 | ||
12998 | static void | |
12999 | do_vfp_nsyn_push (void) | |
13000 | { | |
13001 | nsyn_insert_sp (); | |
13002 | if (inst.operands[1].issingle) | |
13003 | do_vfp_nsyn_opcode ("fstmdbs"); | |
13004 | else | |
13005 | do_vfp_nsyn_opcode ("fstmdbd"); | |
13006 | } | |
13007 | ||
13008 | static void | |
13009 | do_vfp_nsyn_pop (void) | |
13010 | { | |
13011 | nsyn_insert_sp (); | |
13012 | if (inst.operands[1].issingle) | |
22b5b651 | 13013 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 13014 | else |
22b5b651 | 13015 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
13016 | } |
13017 | ||
13018 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
13019 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
13020 | ||
88714cb8 DG |
13021 | static void |
13022 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 13023 | { |
88714cb8 DG |
13024 | unsigned int i = insn->instruction; |
13025 | insn->is_neon = 1; | |
13026 | ||
037e8744 JB |
13027 | if (thumb_mode) |
13028 | { | |
13029 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
13030 | if (i & (1 << 24)) | |
13031 | i |= 1 << 28; | |
5f4273c7 | 13032 | |
037e8744 | 13033 | i &= ~(1 << 24); |
5f4273c7 | 13034 | |
037e8744 JB |
13035 | i |= 0xef000000; |
13036 | } | |
13037 | else | |
13038 | i |= 0xf2000000; | |
5f4273c7 | 13039 | |
88714cb8 | 13040 | insn->instruction = i; |
037e8744 JB |
13041 | } |
13042 | ||
13043 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
13044 | (0, 1, 2, 3). */ | |
13045 | ||
13046 | static unsigned | |
13047 | neon_logbits (unsigned x) | |
13048 | { | |
13049 | return ffs (x) - 4; | |
13050 | } | |
13051 | ||
13052 | #define LOW4(R) ((R) & 0xf) | |
13053 | #define HI1(R) (((R) >> 4) & 1) | |
13054 | ||
13055 | /* Encode insns with bit pattern: | |
13056 | ||
13057 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
13058 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 13059 | |
037e8744 JB |
13060 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
13061 | different meaning for some instruction. */ | |
13062 | ||
13063 | static void | |
13064 | neon_three_same (int isquad, int ubit, int size) | |
13065 | { | |
13066 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13067 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13068 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13069 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13070 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
13071 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
13072 | inst.instruction |= (isquad != 0) << 6; | |
13073 | inst.instruction |= (ubit != 0) << 24; | |
13074 | if (size != -1) | |
13075 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 13076 | |
88714cb8 | 13077 | neon_dp_fixup (&inst); |
037e8744 JB |
13078 | } |
13079 | ||
13080 | /* Encode instructions of the form: | |
13081 | ||
13082 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
13083 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
13084 | |
13085 | Don't write size if SIZE == -1. */ | |
13086 | ||
13087 | static void | |
13088 | neon_two_same (int qbit, int ubit, int size) | |
13089 | { | |
13090 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13091 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13092 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13093 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13094 | inst.instruction |= (qbit != 0) << 6; | |
13095 | inst.instruction |= (ubit != 0) << 24; | |
13096 | ||
13097 | if (size != -1) | |
13098 | inst.instruction |= neon_logbits (size) << 18; | |
13099 | ||
88714cb8 | 13100 | neon_dp_fixup (&inst); |
5287ad62 JB |
13101 | } |
13102 | ||
13103 | /* Neon instruction encoders, in approximate order of appearance. */ | |
13104 | ||
13105 | static void | |
13106 | do_neon_dyadic_i_su (void) | |
13107 | { | |
037e8744 | 13108 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13109 | struct neon_type_el et = neon_check_type (3, rs, |
13110 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 13111 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13112 | } |
13113 | ||
13114 | static void | |
13115 | do_neon_dyadic_i64_su (void) | |
13116 | { | |
037e8744 | 13117 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13118 | struct neon_type_el et = neon_check_type (3, rs, |
13119 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 13120 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13121 | } |
13122 | ||
13123 | static void | |
13124 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
13125 | unsigned immbits) | |
13126 | { | |
13127 | unsigned size = et.size >> 3; | |
13128 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13129 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13130 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13131 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13132 | inst.instruction |= (isquad != 0) << 6; | |
13133 | inst.instruction |= immbits << 16; | |
13134 | inst.instruction |= (size >> 3) << 7; | |
13135 | inst.instruction |= (size & 0x7) << 19; | |
13136 | if (write_ubit) | |
13137 | inst.instruction |= (uval != 0) << 24; | |
13138 | ||
88714cb8 | 13139 | neon_dp_fixup (&inst); |
5287ad62 JB |
13140 | } |
13141 | ||
13142 | static void | |
13143 | do_neon_shl_imm (void) | |
13144 | { | |
13145 | if (!inst.operands[2].isreg) | |
13146 | { | |
037e8744 | 13147 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 13148 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
88714cb8 | 13149 | NEON_ENCODE (IMMED, inst); |
037e8744 | 13150 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
13151 | } |
13152 | else | |
13153 | { | |
037e8744 | 13154 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13155 | struct neon_type_el et = neon_check_type (3, rs, |
13156 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
13157 | unsigned int tmp; |
13158 | ||
13159 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
13160 | vshl.xx Dd, Dm, Dn | |
13161 | whereas other 3-register operations encoded by neon_three_same have | |
13162 | syntax like: | |
13163 | vadd.xx Dd, Dn, Dm | |
13164 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
13165 | here. */ | |
13166 | tmp = inst.operands[2].reg; | |
13167 | inst.operands[2].reg = inst.operands[1].reg; | |
13168 | inst.operands[1].reg = tmp; | |
88714cb8 | 13169 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13170 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13171 | } |
13172 | } | |
13173 | ||
13174 | static void | |
13175 | do_neon_qshl_imm (void) | |
13176 | { | |
13177 | if (!inst.operands[2].isreg) | |
13178 | { | |
037e8744 | 13179 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 13180 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
627907b7 | 13181 | |
88714cb8 | 13182 | NEON_ENCODE (IMMED, inst); |
037e8744 | 13183 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
13184 | inst.operands[2].imm); |
13185 | } | |
13186 | else | |
13187 | { | |
037e8744 | 13188 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13189 | struct neon_type_el et = neon_check_type (3, rs, |
13190 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
13191 | unsigned int tmp; |
13192 | ||
13193 | /* See note in do_neon_shl_imm. */ | |
13194 | tmp = inst.operands[2].reg; | |
13195 | inst.operands[2].reg = inst.operands[1].reg; | |
13196 | inst.operands[1].reg = tmp; | |
88714cb8 | 13197 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13198 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13199 | } |
13200 | } | |
13201 | ||
627907b7 JB |
13202 | static void |
13203 | do_neon_rshl (void) | |
13204 | { | |
13205 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
13206 | struct neon_type_el et = neon_check_type (3, rs, | |
13207 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
13208 | unsigned int tmp; | |
13209 | ||
13210 | tmp = inst.operands[2].reg; | |
13211 | inst.operands[2].reg = inst.operands[1].reg; | |
13212 | inst.operands[1].reg = tmp; | |
13213 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
13214 | } | |
13215 | ||
5287ad62 JB |
13216 | static int |
13217 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
13218 | { | |
036dc3f7 PB |
13219 | /* Handle .I8 pseudo-instructions. */ |
13220 | if (size == 8) | |
5287ad62 | 13221 | { |
5287ad62 JB |
13222 | /* Unfortunately, this will make everything apart from zero out-of-range. |
13223 | FIXME is this the intended semantics? There doesn't seem much point in | |
13224 | accepting .I8 if so. */ | |
13225 | immediate |= immediate << 8; | |
13226 | size = 16; | |
036dc3f7 PB |
13227 | } |
13228 | ||
13229 | if (size >= 32) | |
13230 | { | |
13231 | if (immediate == (immediate & 0x000000ff)) | |
13232 | { | |
13233 | *immbits = immediate; | |
13234 | return 0x1; | |
13235 | } | |
13236 | else if (immediate == (immediate & 0x0000ff00)) | |
13237 | { | |
13238 | *immbits = immediate >> 8; | |
13239 | return 0x3; | |
13240 | } | |
13241 | else if (immediate == (immediate & 0x00ff0000)) | |
13242 | { | |
13243 | *immbits = immediate >> 16; | |
13244 | return 0x5; | |
13245 | } | |
13246 | else if (immediate == (immediate & 0xff000000)) | |
13247 | { | |
13248 | *immbits = immediate >> 24; | |
13249 | return 0x7; | |
13250 | } | |
13251 | if ((immediate & 0xffff) != (immediate >> 16)) | |
13252 | goto bad_immediate; | |
13253 | immediate &= 0xffff; | |
5287ad62 JB |
13254 | } |
13255 | ||
13256 | if (immediate == (immediate & 0x000000ff)) | |
13257 | { | |
13258 | *immbits = immediate; | |
036dc3f7 | 13259 | return 0x9; |
5287ad62 JB |
13260 | } |
13261 | else if (immediate == (immediate & 0x0000ff00)) | |
13262 | { | |
13263 | *immbits = immediate >> 8; | |
036dc3f7 | 13264 | return 0xb; |
5287ad62 JB |
13265 | } |
13266 | ||
13267 | bad_immediate: | |
dcbf9037 | 13268 | first_error (_("immediate value out of range")); |
5287ad62 JB |
13269 | return FAIL; |
13270 | } | |
13271 | ||
13272 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
13273 | A, B, C, D. */ | |
13274 | ||
13275 | static int | |
13276 | neon_bits_same_in_bytes (unsigned imm) | |
13277 | { | |
13278 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) | |
13279 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
13280 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
13281 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
13282 | } | |
13283 | ||
13284 | /* For immediate of above form, return 0bABCD. */ | |
13285 | ||
13286 | static unsigned | |
13287 | neon_squash_bits (unsigned imm) | |
13288 | { | |
13289 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
13290 | | ((imm & 0x01000000) >> 21); | |
13291 | } | |
13292 | ||
136da414 | 13293 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
5287ad62 JB |
13294 | |
13295 | static unsigned | |
13296 | neon_qfloat_bits (unsigned imm) | |
13297 | { | |
136da414 | 13298 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
5287ad62 JB |
13299 | } |
13300 | ||
13301 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
13302 | the instruction. *OP is passed as the initial value of the op field, and | |
13303 | may be set to a different value depending on the constant (i.e. | |
13304 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
5f4273c7 | 13305 | MVN). If the immediate looks like a repeated pattern then also |
036dc3f7 | 13306 | try smaller element sizes. */ |
5287ad62 JB |
13307 | |
13308 | static int | |
c96612cc JB |
13309 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, |
13310 | unsigned *immbits, int *op, int size, | |
13311 | enum neon_el_type type) | |
5287ad62 | 13312 | { |
c96612cc JB |
13313 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is |
13314 | float. */ | |
13315 | if (type == NT_float && !float_p) | |
13316 | return FAIL; | |
13317 | ||
136da414 JB |
13318 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
13319 | { | |
13320 | if (size != 32 || *op == 1) | |
13321 | return FAIL; | |
13322 | *immbits = neon_qfloat_bits (immlo); | |
13323 | return 0xf; | |
13324 | } | |
036dc3f7 PB |
13325 | |
13326 | if (size == 64) | |
5287ad62 | 13327 | { |
036dc3f7 PB |
13328 | if (neon_bits_same_in_bytes (immhi) |
13329 | && neon_bits_same_in_bytes (immlo)) | |
13330 | { | |
13331 | if (*op == 1) | |
13332 | return FAIL; | |
13333 | *immbits = (neon_squash_bits (immhi) << 4) | |
13334 | | neon_squash_bits (immlo); | |
13335 | *op = 1; | |
13336 | return 0xe; | |
13337 | } | |
13338 | ||
13339 | if (immhi != immlo) | |
13340 | return FAIL; | |
5287ad62 | 13341 | } |
036dc3f7 PB |
13342 | |
13343 | if (size >= 32) | |
5287ad62 | 13344 | { |
036dc3f7 PB |
13345 | if (immlo == (immlo & 0x000000ff)) |
13346 | { | |
13347 | *immbits = immlo; | |
13348 | return 0x0; | |
13349 | } | |
13350 | else if (immlo == (immlo & 0x0000ff00)) | |
13351 | { | |
13352 | *immbits = immlo >> 8; | |
13353 | return 0x2; | |
13354 | } | |
13355 | else if (immlo == (immlo & 0x00ff0000)) | |
13356 | { | |
13357 | *immbits = immlo >> 16; | |
13358 | return 0x4; | |
13359 | } | |
13360 | else if (immlo == (immlo & 0xff000000)) | |
13361 | { | |
13362 | *immbits = immlo >> 24; | |
13363 | return 0x6; | |
13364 | } | |
13365 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
13366 | { | |
13367 | *immbits = (immlo >> 8) & 0xff; | |
13368 | return 0xc; | |
13369 | } | |
13370 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
13371 | { | |
13372 | *immbits = (immlo >> 16) & 0xff; | |
13373 | return 0xd; | |
13374 | } | |
13375 | ||
13376 | if ((immlo & 0xffff) != (immlo >> 16)) | |
13377 | return FAIL; | |
13378 | immlo &= 0xffff; | |
5287ad62 | 13379 | } |
036dc3f7 PB |
13380 | |
13381 | if (size >= 16) | |
5287ad62 | 13382 | { |
036dc3f7 PB |
13383 | if (immlo == (immlo & 0x000000ff)) |
13384 | { | |
13385 | *immbits = immlo; | |
13386 | return 0x8; | |
13387 | } | |
13388 | else if (immlo == (immlo & 0x0000ff00)) | |
13389 | { | |
13390 | *immbits = immlo >> 8; | |
13391 | return 0xa; | |
13392 | } | |
13393 | ||
13394 | if ((immlo & 0xff) != (immlo >> 8)) | |
13395 | return FAIL; | |
13396 | immlo &= 0xff; | |
5287ad62 | 13397 | } |
036dc3f7 PB |
13398 | |
13399 | if (immlo == (immlo & 0x000000ff)) | |
5287ad62 | 13400 | { |
036dc3f7 PB |
13401 | /* Don't allow MVN with 8-bit immediate. */ |
13402 | if (*op == 1) | |
13403 | return FAIL; | |
13404 | *immbits = immlo; | |
13405 | return 0xe; | |
5287ad62 | 13406 | } |
5287ad62 JB |
13407 | |
13408 | return FAIL; | |
13409 | } | |
13410 | ||
13411 | /* Write immediate bits [7:0] to the following locations: | |
13412 | ||
13413 | |28/24|23 19|18 16|15 4|3 0| | |
13414 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
13415 | ||
13416 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
13417 | ||
13418 | static void | |
13419 | neon_write_immbits (unsigned immbits) | |
13420 | { | |
13421 | inst.instruction |= immbits & 0xf; | |
13422 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
13423 | inst.instruction |= ((immbits >> 7) & 0x1) << 24; | |
13424 | } | |
13425 | ||
13426 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
13427 | ||
13428 | static void | |
13429 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
13430 | { | |
13431 | unsigned immlo = xlo ? *xlo : 0; | |
13432 | unsigned immhi = xhi ? *xhi : 0; | |
13433 | ||
13434 | switch (size) | |
13435 | { | |
13436 | case 8: | |
13437 | immlo = (~immlo) & 0xff; | |
13438 | break; | |
13439 | ||
13440 | case 16: | |
13441 | immlo = (~immlo) & 0xffff; | |
13442 | break; | |
13443 | ||
13444 | case 64: | |
13445 | immhi = (~immhi) & 0xffffffff; | |
13446 | /* fall through. */ | |
13447 | ||
13448 | case 32: | |
13449 | immlo = (~immlo) & 0xffffffff; | |
13450 | break; | |
13451 | ||
13452 | default: | |
13453 | abort (); | |
13454 | } | |
13455 | ||
13456 | if (xlo) | |
13457 | *xlo = immlo; | |
13458 | ||
13459 | if (xhi) | |
13460 | *xhi = immhi; | |
13461 | } | |
13462 | ||
13463 | static void | |
13464 | do_neon_logic (void) | |
13465 | { | |
13466 | if (inst.operands[2].present && inst.operands[2].isreg) | |
13467 | { | |
037e8744 | 13468 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13469 | neon_check_type (3, rs, N_IGNORE_TYPE); |
13470 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 13471 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13472 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13473 | } |
13474 | else | |
13475 | { | |
4316f0d2 DG |
13476 | const int three_ops_form = (inst.operands[2].present |
13477 | && !inst.operands[2].isreg); | |
13478 | const int immoperand = (three_ops_form ? 2 : 1); | |
13479 | enum neon_shape rs = (three_ops_form | |
13480 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
13481 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 JB |
13482 | struct neon_type_el et = neon_check_type (2, rs, |
13483 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
21d799b5 | 13484 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
13485 | unsigned immbits; |
13486 | int cmode; | |
5f4273c7 | 13487 | |
5287ad62 JB |
13488 | if (et.type == NT_invtype) |
13489 | return; | |
5f4273c7 | 13490 | |
4316f0d2 DG |
13491 | if (three_ops_form) |
13492 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13493 | _("first and second operands shall be the same register")); | |
13494 | ||
88714cb8 | 13495 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 13496 | |
4316f0d2 | 13497 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
13498 | if (et.size == 64) |
13499 | { | |
13500 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
13501 | pattern. */ | |
4316f0d2 DG |
13502 | if (immbits != (inst.operands[immoperand].regisimm ? |
13503 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
13504 | { |
13505 | /* Set immbits to an invalid constant. */ | |
13506 | immbits = 0xdeadbeef; | |
13507 | } | |
13508 | } | |
13509 | ||
5287ad62 JB |
13510 | switch (opcode) |
13511 | { | |
13512 | case N_MNEM_vbic: | |
036dc3f7 | 13513 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13514 | break; |
5f4273c7 | 13515 | |
5287ad62 | 13516 | case N_MNEM_vorr: |
036dc3f7 | 13517 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13518 | break; |
5f4273c7 | 13519 | |
5287ad62 JB |
13520 | case N_MNEM_vand: |
13521 | /* Pseudo-instruction for VBIC. */ | |
5287ad62 JB |
13522 | neon_invert_size (&immbits, 0, et.size); |
13523 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13524 | break; | |
5f4273c7 | 13525 | |
5287ad62 JB |
13526 | case N_MNEM_vorn: |
13527 | /* Pseudo-instruction for VORR. */ | |
5287ad62 JB |
13528 | neon_invert_size (&immbits, 0, et.size); |
13529 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13530 | break; | |
5f4273c7 | 13531 | |
5287ad62 JB |
13532 | default: |
13533 | abort (); | |
13534 | } | |
13535 | ||
13536 | if (cmode == FAIL) | |
13537 | return; | |
13538 | ||
037e8744 | 13539 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13540 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13541 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13542 | inst.instruction |= cmode << 8; | |
13543 | neon_write_immbits (immbits); | |
5f4273c7 | 13544 | |
88714cb8 | 13545 | neon_dp_fixup (&inst); |
5287ad62 JB |
13546 | } |
13547 | } | |
13548 | ||
13549 | static void | |
13550 | do_neon_bitfield (void) | |
13551 | { | |
037e8744 | 13552 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 13553 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 13554 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13555 | } |
13556 | ||
13557 | static void | |
dcbf9037 JB |
13558 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
13559 | unsigned destbits) | |
5287ad62 | 13560 | { |
037e8744 | 13561 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 JB |
13562 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
13563 | types | N_KEY); | |
5287ad62 JB |
13564 | if (et.type == NT_float) |
13565 | { | |
88714cb8 | 13566 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 13567 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13568 | } |
13569 | else | |
13570 | { | |
88714cb8 | 13571 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13572 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
13573 | } |
13574 | } | |
13575 | ||
13576 | static void | |
13577 | do_neon_dyadic_if_su (void) | |
13578 | { | |
dcbf9037 | 13579 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13580 | } |
13581 | ||
13582 | static void | |
13583 | do_neon_dyadic_if_su_d (void) | |
13584 | { | |
13585 | /* This version only allow D registers, but that constraint is enforced during | |
13586 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 13587 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13588 | } |
13589 | ||
5287ad62 JB |
13590 | static void |
13591 | do_neon_dyadic_if_i_d (void) | |
13592 | { | |
428e3f1f PB |
13593 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13594 | affected if we specify unsigned args. */ | |
13595 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
13596 | } |
13597 | ||
037e8744 JB |
13598 | enum vfp_or_neon_is_neon_bits |
13599 | { | |
13600 | NEON_CHECK_CC = 1, | |
13601 | NEON_CHECK_ARCH = 2 | |
13602 | }; | |
13603 | ||
13604 | /* Call this function if an instruction which may have belonged to the VFP or | |
13605 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
13606 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
13607 | things: | |
13608 | ||
13609 | - Make sure the user hasn't attempted to make a Neon instruction | |
13610 | conditional. | |
13611 | - Alter the value in the condition code field if necessary. | |
13612 | - Make sure that the arch supports Neon instructions. | |
13613 | ||
13614 | Which of these operations take place depends on bits from enum | |
13615 | vfp_or_neon_is_neon_bits. | |
13616 | ||
13617 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
13618 | current instruction's condition is COND_ALWAYS, the condition field is | |
13619 | changed to inst.uncond_value. This is necessary because instructions shared | |
13620 | between VFP and Neon may be conditional for the VFP variants only, and the | |
13621 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
13622 | ||
13623 | static int | |
13624 | vfp_or_neon_is_neon (unsigned check) | |
13625 | { | |
13626 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
13627 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
13628 | { | |
13629 | if (inst.cond != COND_ALWAYS) | |
13630 | { | |
13631 | first_error (_(BAD_COND)); | |
13632 | return FAIL; | |
13633 | } | |
13634 | if (inst.uncond_value != -1) | |
13635 | inst.instruction |= inst.uncond_value << 28; | |
13636 | } | |
5f4273c7 | 13637 | |
037e8744 JB |
13638 | if ((check & NEON_CHECK_ARCH) |
13639 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
13640 | { | |
13641 | first_error (_(BAD_FPU)); | |
13642 | return FAIL; | |
13643 | } | |
5f4273c7 | 13644 | |
037e8744 JB |
13645 | return SUCCESS; |
13646 | } | |
13647 | ||
5287ad62 JB |
13648 | static void |
13649 | do_neon_addsub_if_i (void) | |
13650 | { | |
037e8744 JB |
13651 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
13652 | return; | |
13653 | ||
13654 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13655 | return; | |
13656 | ||
5287ad62 JB |
13657 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13658 | affected if we specify unsigned args. */ | |
dcbf9037 | 13659 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
13660 | } |
13661 | ||
13662 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
13663 | result to be: | |
13664 | V<op> A,B (A is operand 0, B is operand 2) | |
13665 | to mean: | |
13666 | V<op> A,B,A | |
13667 | not: | |
13668 | V<op> A,B,B | |
13669 | so handle that case specially. */ | |
13670 | ||
13671 | static void | |
13672 | neon_exchange_operands (void) | |
13673 | { | |
13674 | void *scratch = alloca (sizeof (inst.operands[0])); | |
13675 | if (inst.operands[1].present) | |
13676 | { | |
13677 | /* Swap operands[1] and operands[2]. */ | |
13678 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
13679 | inst.operands[1] = inst.operands[2]; | |
13680 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
13681 | } | |
13682 | else | |
13683 | { | |
13684 | inst.operands[1] = inst.operands[2]; | |
13685 | inst.operands[2] = inst.operands[0]; | |
13686 | } | |
13687 | } | |
13688 | ||
13689 | static void | |
13690 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
13691 | { | |
13692 | if (inst.operands[2].isreg) | |
13693 | { | |
13694 | if (invert) | |
13695 | neon_exchange_operands (); | |
dcbf9037 | 13696 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
13697 | } |
13698 | else | |
13699 | { | |
037e8744 | 13700 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 JB |
13701 | struct neon_type_el et = neon_check_type (2, rs, |
13702 | N_EQK | N_SIZ, immtypes | N_KEY); | |
5287ad62 | 13703 | |
88714cb8 | 13704 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
13705 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13706 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13707 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13708 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13709 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13710 | inst.instruction |= (et.type == NT_float) << 10; |
13711 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13712 | |
88714cb8 | 13713 | neon_dp_fixup (&inst); |
5287ad62 JB |
13714 | } |
13715 | } | |
13716 | ||
13717 | static void | |
13718 | do_neon_cmp (void) | |
13719 | { | |
13720 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
13721 | } | |
13722 | ||
13723 | static void | |
13724 | do_neon_cmp_inv (void) | |
13725 | { | |
13726 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
13727 | } | |
13728 | ||
13729 | static void | |
13730 | do_neon_ceq (void) | |
13731 | { | |
13732 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
13733 | } | |
13734 | ||
13735 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
13736 | scalars, which are encoded in 5 bits, M : Rm. | |
13737 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
13738 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
13739 | index in M. */ | |
13740 | ||
13741 | static unsigned | |
13742 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
13743 | { | |
dcbf9037 JB |
13744 | unsigned regno = NEON_SCALAR_REG (scalar); |
13745 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
13746 | |
13747 | switch (elsize) | |
13748 | { | |
13749 | case 16: | |
13750 | if (regno > 7 || elno > 3) | |
13751 | goto bad_scalar; | |
13752 | return regno | (elno << 3); | |
5f4273c7 | 13753 | |
5287ad62 JB |
13754 | case 32: |
13755 | if (regno > 15 || elno > 1) | |
13756 | goto bad_scalar; | |
13757 | return regno | (elno << 4); | |
13758 | ||
13759 | default: | |
13760 | bad_scalar: | |
dcbf9037 | 13761 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
13762 | } |
13763 | ||
13764 | return 0; | |
13765 | } | |
13766 | ||
13767 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
13768 | ||
13769 | static void | |
13770 | neon_mul_mac (struct neon_type_el et, int ubit) | |
13771 | { | |
dcbf9037 JB |
13772 | unsigned scalar; |
13773 | ||
13774 | /* Give a more helpful error message if we have an invalid type. */ | |
13775 | if (et.type == NT_invtype) | |
13776 | return; | |
5f4273c7 | 13777 | |
dcbf9037 | 13778 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
13779 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13780 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13781 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13782 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13783 | inst.instruction |= LOW4 (scalar); | |
13784 | inst.instruction |= HI1 (scalar) << 5; | |
13785 | inst.instruction |= (et.type == NT_float) << 8; | |
13786 | inst.instruction |= neon_logbits (et.size) << 20; | |
13787 | inst.instruction |= (ubit != 0) << 24; | |
13788 | ||
88714cb8 | 13789 | neon_dp_fixup (&inst); |
5287ad62 JB |
13790 | } |
13791 | ||
13792 | static void | |
13793 | do_neon_mac_maybe_scalar (void) | |
13794 | { | |
037e8744 JB |
13795 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
13796 | return; | |
13797 | ||
13798 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13799 | return; | |
13800 | ||
5287ad62 JB |
13801 | if (inst.operands[2].isscalar) |
13802 | { | |
037e8744 | 13803 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13804 | struct neon_type_el et = neon_check_type (3, rs, |
13805 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); | |
88714cb8 | 13806 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13807 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13808 | } |
13809 | else | |
428e3f1f PB |
13810 | { |
13811 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
13812 | affected if we specify unsigned args. */ | |
13813 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13814 | } | |
5287ad62 JB |
13815 | } |
13816 | ||
62f3b8c8 PB |
13817 | static void |
13818 | do_neon_fmac (void) | |
13819 | { | |
13820 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
13821 | return; | |
13822 | ||
13823 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13824 | return; | |
13825 | ||
13826 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13827 | } | |
13828 | ||
5287ad62 JB |
13829 | static void |
13830 | do_neon_tst (void) | |
13831 | { | |
037e8744 | 13832 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13833 | struct neon_type_el et = neon_check_type (3, rs, |
13834 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 13835 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13836 | } |
13837 | ||
13838 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
13839 | same types as the MAC equivalents. The polynomial type for this instruction | |
13840 | is encoded the same as the integer type. */ | |
13841 | ||
13842 | static void | |
13843 | do_neon_mul (void) | |
13844 | { | |
037e8744 JB |
13845 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
13846 | return; | |
13847 | ||
13848 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13849 | return; | |
13850 | ||
5287ad62 JB |
13851 | if (inst.operands[2].isscalar) |
13852 | do_neon_mac_maybe_scalar (); | |
13853 | else | |
dcbf9037 | 13854 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
13855 | } |
13856 | ||
13857 | static void | |
13858 | do_neon_qdmulh (void) | |
13859 | { | |
13860 | if (inst.operands[2].isscalar) | |
13861 | { | |
037e8744 | 13862 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13863 | struct neon_type_el et = neon_check_type (3, rs, |
13864 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 13865 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13866 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13867 | } |
13868 | else | |
13869 | { | |
037e8744 | 13870 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13871 | struct neon_type_el et = neon_check_type (3, rs, |
13872 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 13873 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 13874 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 13875 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13876 | } |
13877 | } | |
13878 | ||
13879 | static void | |
13880 | do_neon_fcmp_absolute (void) | |
13881 | { | |
037e8744 | 13882 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13883 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
13884 | /* Size field comes from bit mask. */ | |
037e8744 | 13885 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
13886 | } |
13887 | ||
13888 | static void | |
13889 | do_neon_fcmp_absolute_inv (void) | |
13890 | { | |
13891 | neon_exchange_operands (); | |
13892 | do_neon_fcmp_absolute (); | |
13893 | } | |
13894 | ||
13895 | static void | |
13896 | do_neon_step (void) | |
13897 | { | |
037e8744 | 13898 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 13899 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 13900 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13901 | } |
13902 | ||
13903 | static void | |
13904 | do_neon_abs_neg (void) | |
13905 | { | |
037e8744 JB |
13906 | enum neon_shape rs; |
13907 | struct neon_type_el et; | |
5f4273c7 | 13908 | |
037e8744 JB |
13909 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
13910 | return; | |
13911 | ||
13912 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13913 | return; | |
13914 | ||
13915 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
13916 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 13917 | |
5287ad62 JB |
13918 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13919 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13920 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13921 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13922 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13923 | inst.instruction |= (et.type == NT_float) << 10; |
13924 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13925 | |
88714cb8 | 13926 | neon_dp_fixup (&inst); |
5287ad62 JB |
13927 | } |
13928 | ||
13929 | static void | |
13930 | do_neon_sli (void) | |
13931 | { | |
037e8744 | 13932 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13933 | struct neon_type_el et = neon_check_type (2, rs, |
13934 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13935 | int imm = inst.operands[2].imm; | |
13936 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
13937 | _("immediate out of range for insert")); | |
037e8744 | 13938 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
13939 | } |
13940 | ||
13941 | static void | |
13942 | do_neon_sri (void) | |
13943 | { | |
037e8744 | 13944 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13945 | struct neon_type_el et = neon_check_type (2, rs, |
13946 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
13947 | int imm = inst.operands[2].imm; | |
13948 | constraint (imm < 1 || (unsigned)imm > et.size, | |
13949 | _("immediate out of range for insert")); | |
037e8744 | 13950 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
13951 | } |
13952 | ||
13953 | static void | |
13954 | do_neon_qshlu_imm (void) | |
13955 | { | |
037e8744 | 13956 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
13957 | struct neon_type_el et = neon_check_type (2, rs, |
13958 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
13959 | int imm = inst.operands[2].imm; | |
13960 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
13961 | _("immediate out of range for shift")); | |
13962 | /* Only encodes the 'U present' variant of the instruction. | |
13963 | In this case, signed types have OP (bit 8) set to 0. | |
13964 | Unsigned types have OP set to 1. */ | |
13965 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
13966 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 13967 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
13968 | } |
13969 | ||
13970 | static void | |
13971 | do_neon_qmovn (void) | |
13972 | { | |
13973 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13974 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
13975 | /* Saturating move where operands can be signed or unsigned, and the | |
13976 | destination has the same signedness. */ | |
88714cb8 | 13977 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13978 | if (et.type == NT_unsigned) |
13979 | inst.instruction |= 0xc0; | |
13980 | else | |
13981 | inst.instruction |= 0x80; | |
13982 | neon_two_same (0, 1, et.size / 2); | |
13983 | } | |
13984 | ||
13985 | static void | |
13986 | do_neon_qmovun (void) | |
13987 | { | |
13988 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
13989 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
13990 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 13991 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
13992 | neon_two_same (0, 1, et.size / 2); |
13993 | } | |
13994 | ||
13995 | static void | |
13996 | do_neon_rshift_sat_narrow (void) | |
13997 | { | |
13998 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
13999 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14000 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14001 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14002 | int imm = inst.operands[2].imm; | |
14003 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14004 | right. */ | |
14005 | et.size /= 2; | |
5f4273c7 | 14006 | |
5287ad62 JB |
14007 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
14008 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
14009 | if (imm == 0) | |
14010 | { | |
14011 | inst.operands[2].present = 0; | |
14012 | inst.instruction = N_MNEM_vqmovn; | |
14013 | do_neon_qmovn (); | |
14014 | return; | |
14015 | } | |
5f4273c7 | 14016 | |
5287ad62 JB |
14017 | constraint (imm < 1 || (unsigned)imm > et.size, |
14018 | _("immediate out of range")); | |
14019 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); | |
14020 | } | |
14021 | ||
14022 | static void | |
14023 | do_neon_rshift_sat_narrow_u (void) | |
14024 | { | |
14025 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14026 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14027 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14028 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14029 | int imm = inst.operands[2].imm; | |
14030 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14031 | right. */ | |
14032 | et.size /= 2; | |
14033 | ||
14034 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
14035 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
14036 | if (imm == 0) | |
14037 | { | |
14038 | inst.operands[2].present = 0; | |
14039 | inst.instruction = N_MNEM_vqmovun; | |
14040 | do_neon_qmovun (); | |
14041 | return; | |
14042 | } | |
14043 | ||
14044 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14045 | _("immediate out of range")); | |
14046 | /* FIXME: The manual is kind of unclear about what value U should have in | |
14047 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
14048 | must be 1. */ | |
14049 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
14050 | } | |
14051 | ||
14052 | static void | |
14053 | do_neon_movn (void) | |
14054 | { | |
14055 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14056 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 14057 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14058 | neon_two_same (0, 1, et.size / 2); |
14059 | } | |
14060 | ||
14061 | static void | |
14062 | do_neon_rshift_narrow (void) | |
14063 | { | |
14064 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14065 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
14066 | int imm = inst.operands[2].imm; | |
14067 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14068 | right. */ | |
14069 | et.size /= 2; | |
5f4273c7 | 14070 | |
5287ad62 JB |
14071 | /* If immediate is zero then we are a pseudo-instruction for |
14072 | VMOVN.I<size> <Dd>, <Qm> */ | |
14073 | if (imm == 0) | |
14074 | { | |
14075 | inst.operands[2].present = 0; | |
14076 | inst.instruction = N_MNEM_vmovn; | |
14077 | do_neon_movn (); | |
14078 | return; | |
14079 | } | |
5f4273c7 | 14080 | |
5287ad62 JB |
14081 | constraint (imm < 1 || (unsigned)imm > et.size, |
14082 | _("immediate out of range for narrowing operation")); | |
14083 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); | |
14084 | } | |
14085 | ||
14086 | static void | |
14087 | do_neon_shll (void) | |
14088 | { | |
14089 | /* FIXME: Type checking when lengthening. */ | |
14090 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
14091 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
14092 | unsigned imm = inst.operands[2].imm; | |
14093 | ||
14094 | if (imm == et.size) | |
14095 | { | |
14096 | /* Maximum shift variant. */ | |
88714cb8 | 14097 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14098 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14099 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14100 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14101 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14102 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14103 | |
88714cb8 | 14104 | neon_dp_fixup (&inst); |
5287ad62 JB |
14105 | } |
14106 | else | |
14107 | { | |
14108 | /* A more-specific type check for non-max versions. */ | |
14109 | et = neon_check_type (2, NS_QDI, | |
14110 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
88714cb8 | 14111 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14112 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
14113 | } | |
14114 | } | |
14115 | ||
037e8744 | 14116 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
14117 | the current instruction is. */ |
14118 | ||
14119 | static int | |
14120 | neon_cvt_flavour (enum neon_shape rs) | |
14121 | { | |
037e8744 JB |
14122 | #define CVT_VAR(C,X,Y) \ |
14123 | et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ | |
14124 | if (et.type != NT_invtype) \ | |
14125 | { \ | |
14126 | inst.error = NULL; \ | |
14127 | return (C); \ | |
5287ad62 JB |
14128 | } |
14129 | struct neon_type_el et; | |
037e8744 JB |
14130 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
14131 | || rs == NS_FF) ? N_VFP : 0; | |
14132 | /* The instruction versions which take an immediate take one register | |
14133 | argument, which is extended to the width of the full register. Thus the | |
14134 | "source" and "destination" registers must have the same width. Hack that | |
14135 | here by making the size equal to the key (wider, in this case) operand. */ | |
14136 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 14137 | |
5287ad62 JB |
14138 | CVT_VAR (0, N_S32, N_F32); |
14139 | CVT_VAR (1, N_U32, N_F32); | |
14140 | CVT_VAR (2, N_F32, N_S32); | |
14141 | CVT_VAR (3, N_F32, N_U32); | |
8e79c3df CM |
14142 | /* Half-precision conversions. */ |
14143 | CVT_VAR (4, N_F32, N_F16); | |
14144 | CVT_VAR (5, N_F16, N_F32); | |
5f4273c7 | 14145 | |
037e8744 | 14146 | whole_reg = N_VFP; |
5f4273c7 | 14147 | |
037e8744 | 14148 | /* VFP instructions. */ |
8e79c3df CM |
14149 | CVT_VAR (6, N_F32, N_F64); |
14150 | CVT_VAR (7, N_F64, N_F32); | |
14151 | CVT_VAR (8, N_S32, N_F64 | key); | |
14152 | CVT_VAR (9, N_U32, N_F64 | key); | |
14153 | CVT_VAR (10, N_F64 | key, N_S32); | |
14154 | CVT_VAR (11, N_F64 | key, N_U32); | |
037e8744 | 14155 | /* VFP instructions with bitshift. */ |
8e79c3df CM |
14156 | CVT_VAR (12, N_F32 | key, N_S16); |
14157 | CVT_VAR (13, N_F32 | key, N_U16); | |
14158 | CVT_VAR (14, N_F64 | key, N_S16); | |
14159 | CVT_VAR (15, N_F64 | key, N_U16); | |
14160 | CVT_VAR (16, N_S16, N_F32 | key); | |
14161 | CVT_VAR (17, N_U16, N_F32 | key); | |
14162 | CVT_VAR (18, N_S16, N_F64 | key); | |
14163 | CVT_VAR (19, N_U16, N_F64 | key); | |
5f4273c7 | 14164 | |
5287ad62 JB |
14165 | return -1; |
14166 | #undef CVT_VAR | |
14167 | } | |
14168 | ||
037e8744 JB |
14169 | /* Neon-syntax VFP conversions. */ |
14170 | ||
5287ad62 | 14171 | static void |
037e8744 | 14172 | do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
5287ad62 | 14173 | { |
037e8744 | 14174 | const char *opname = 0; |
5f4273c7 | 14175 | |
037e8744 | 14176 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 14177 | { |
037e8744 JB |
14178 | /* Conversions with immediate bitshift. */ |
14179 | const char *enc[] = | |
14180 | { | |
14181 | "ftosls", | |
14182 | "ftouls", | |
14183 | "fsltos", | |
14184 | "fultos", | |
14185 | NULL, | |
14186 | NULL, | |
8e79c3df CM |
14187 | NULL, |
14188 | NULL, | |
037e8744 JB |
14189 | "ftosld", |
14190 | "ftould", | |
14191 | "fsltod", | |
14192 | "fultod", | |
14193 | "fshtos", | |
14194 | "fuhtos", | |
14195 | "fshtod", | |
14196 | "fuhtod", | |
14197 | "ftoshs", | |
14198 | "ftouhs", | |
14199 | "ftoshd", | |
14200 | "ftouhd" | |
14201 | }; | |
14202 | ||
14203 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
14204 | { | |
14205 | opname = enc[flavour]; | |
14206 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14207 | _("operands 0 and 1 must be the same register")); | |
14208 | inst.operands[1] = inst.operands[2]; | |
14209 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
14210 | } | |
5287ad62 JB |
14211 | } |
14212 | else | |
14213 | { | |
037e8744 JB |
14214 | /* Conversions without bitshift. */ |
14215 | const char *enc[] = | |
14216 | { | |
14217 | "ftosis", | |
14218 | "ftouis", | |
14219 | "fsitos", | |
14220 | "fuitos", | |
8e79c3df CM |
14221 | "NULL", |
14222 | "NULL", | |
037e8744 JB |
14223 | "fcvtsd", |
14224 | "fcvtds", | |
14225 | "ftosid", | |
14226 | "ftouid", | |
14227 | "fsitod", | |
14228 | "fuitod" | |
14229 | }; | |
14230 | ||
14231 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
14232 | opname = enc[flavour]; | |
14233 | } | |
14234 | ||
14235 | if (opname) | |
14236 | do_vfp_nsyn_opcode (opname); | |
14237 | } | |
14238 | ||
14239 | static void | |
14240 | do_vfp_nsyn_cvtz (void) | |
14241 | { | |
14242 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
14243 | int flavour = neon_cvt_flavour (rs); | |
14244 | const char *enc[] = | |
14245 | { | |
14246 | "ftosizs", | |
14247 | "ftouizs", | |
14248 | NULL, | |
14249 | NULL, | |
14250 | NULL, | |
14251 | NULL, | |
8e79c3df CM |
14252 | NULL, |
14253 | NULL, | |
037e8744 JB |
14254 | "ftosizd", |
14255 | "ftouizd" | |
14256 | }; | |
14257 | ||
14258 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) | |
14259 | do_vfp_nsyn_opcode (enc[flavour]); | |
14260 | } | |
f31fef98 | 14261 | |
037e8744 | 14262 | static void |
e3e535bc | 14263 | do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED) |
037e8744 JB |
14264 | { |
14265 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 14266 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
037e8744 JB |
14267 | int flavour = neon_cvt_flavour (rs); |
14268 | ||
e3e535bc NC |
14269 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
14270 | if (round_to_zero | |
14271 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) | |
14272 | && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9) | |
14273 | && (rs == NS_FD || rs == NS_FF)) | |
14274 | { | |
14275 | do_vfp_nsyn_cvtz (); | |
14276 | return; | |
14277 | } | |
14278 | ||
037e8744 | 14279 | /* VFP rather than Neon conversions. */ |
8e79c3df | 14280 | if (flavour >= 6) |
037e8744 JB |
14281 | { |
14282 | do_vfp_nsyn_cvt (rs, flavour); | |
14283 | return; | |
14284 | } | |
14285 | ||
14286 | switch (rs) | |
14287 | { | |
14288 | case NS_DDI: | |
14289 | case NS_QQI: | |
14290 | { | |
35997600 NC |
14291 | unsigned immbits; |
14292 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
14293 | ||
037e8744 JB |
14294 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
14295 | return; | |
14296 | ||
14297 | /* Fixed-point conversion with #0 immediate is encoded as an | |
14298 | integer conversion. */ | |
14299 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
14300 | goto int_encode; | |
35997600 | 14301 | immbits = 32 - inst.operands[2].imm; |
88714cb8 | 14302 | NEON_ENCODE (IMMED, inst); |
037e8744 JB |
14303 | if (flavour != -1) |
14304 | inst.instruction |= enctab[flavour]; | |
14305 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14306 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14307 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14308 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14309 | inst.instruction |= neon_quad (rs) << 6; | |
14310 | inst.instruction |= 1 << 21; | |
14311 | inst.instruction |= immbits << 16; | |
14312 | ||
88714cb8 | 14313 | neon_dp_fixup (&inst); |
037e8744 JB |
14314 | } |
14315 | break; | |
14316 | ||
14317 | case NS_DD: | |
14318 | case NS_QQ: | |
14319 | int_encode: | |
14320 | { | |
14321 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
14322 | ||
88714cb8 | 14323 | NEON_ENCODE (INTEGER, inst); |
037e8744 JB |
14324 | |
14325 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14326 | return; | |
14327 | ||
14328 | if (flavour != -1) | |
14329 | inst.instruction |= enctab[flavour]; | |
14330 | ||
14331 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14332 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14333 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14334 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14335 | inst.instruction |= neon_quad (rs) << 6; | |
14336 | inst.instruction |= 2 << 18; | |
14337 | ||
88714cb8 | 14338 | neon_dp_fixup (&inst); |
037e8744 JB |
14339 | } |
14340 | break; | |
14341 | ||
8e79c3df CM |
14342 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
14343 | case NS_QD: | |
14344 | case NS_DQ: | |
14345 | ||
14346 | if ((rs == NS_DQ) | |
14347 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
14348 | { | |
14349 | as_bad (_("operand size must match register width")); | |
14350 | break; | |
14351 | } | |
14352 | ||
14353 | if ((rs == NS_QD) | |
14354 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
14355 | { | |
14356 | as_bad (_("operand size must match register width")); | |
14357 | break; | |
14358 | } | |
14359 | ||
14360 | if (rs == NS_DQ) | |
14361 | inst.instruction = 0x3b60600; | |
14362 | else | |
14363 | inst.instruction = 0x3b60700; | |
14364 | ||
14365 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14366 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14367 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14368 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 14369 | neon_dp_fixup (&inst); |
8e79c3df CM |
14370 | break; |
14371 | ||
037e8744 JB |
14372 | default: |
14373 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
14374 | do_vfp_nsyn_cvt (rs, flavour); | |
5287ad62 | 14375 | } |
5287ad62 JB |
14376 | } |
14377 | ||
e3e535bc NC |
14378 | static void |
14379 | do_neon_cvtr (void) | |
14380 | { | |
14381 | do_neon_cvt_1 (FALSE); | |
14382 | } | |
14383 | ||
14384 | static void | |
14385 | do_neon_cvt (void) | |
14386 | { | |
14387 | do_neon_cvt_1 (TRUE); | |
14388 | } | |
14389 | ||
8e79c3df CM |
14390 | static void |
14391 | do_neon_cvtb (void) | |
14392 | { | |
14393 | inst.instruction = 0xeb20a40; | |
14394 | ||
14395 | /* The sizes are attached to the mnemonic. */ | |
14396 | if (inst.vectype.el[0].type != NT_invtype | |
14397 | && inst.vectype.el[0].size == 16) | |
14398 | inst.instruction |= 0x00010000; | |
14399 | ||
14400 | /* Programmer's syntax: the sizes are attached to the operands. */ | |
14401 | else if (inst.operands[0].vectype.type != NT_invtype | |
14402 | && inst.operands[0].vectype.size == 16) | |
14403 | inst.instruction |= 0x00010000; | |
14404 | ||
14405 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
14406 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
14407 | do_vfp_cond_or_thumb (); | |
14408 | } | |
14409 | ||
14410 | ||
14411 | static void | |
14412 | do_neon_cvtt (void) | |
14413 | { | |
14414 | do_neon_cvtb (); | |
14415 | inst.instruction |= 0x80; | |
14416 | } | |
14417 | ||
5287ad62 JB |
14418 | static void |
14419 | neon_move_immediate (void) | |
14420 | { | |
037e8744 JB |
14421 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
14422 | struct neon_type_el et = neon_check_type (2, rs, | |
14423 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 14424 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 14425 | int op, cmode, float_p; |
5287ad62 | 14426 | |
037e8744 JB |
14427 | constraint (et.type == NT_invtype, |
14428 | _("operand size must be specified for immediate VMOV")); | |
14429 | ||
5287ad62 JB |
14430 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
14431 | op = (inst.instruction & (1 << 5)) != 0; | |
14432 | ||
14433 | immlo = inst.operands[1].imm; | |
14434 | if (inst.operands[1].regisimm) | |
14435 | immhi = inst.operands[1].reg; | |
14436 | ||
14437 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
14438 | _("immediate has bits set outside the operand size")); | |
14439 | ||
c96612cc JB |
14440 | float_p = inst.operands[1].immisfloat; |
14441 | ||
14442 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
136da414 | 14443 | et.size, et.type)) == FAIL) |
5287ad62 JB |
14444 | { |
14445 | /* Invert relevant bits only. */ | |
14446 | neon_invert_size (&immlo, &immhi, et.size); | |
14447 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
14448 | with one or the other; those cases are caught by | |
14449 | neon_cmode_for_move_imm. */ | |
14450 | op = !op; | |
c96612cc JB |
14451 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
14452 | &op, et.size, et.type)) == FAIL) | |
5287ad62 | 14453 | { |
dcbf9037 | 14454 | first_error (_("immediate out of range")); |
5287ad62 JB |
14455 | return; |
14456 | } | |
14457 | } | |
14458 | ||
14459 | inst.instruction &= ~(1 << 5); | |
14460 | inst.instruction |= op << 5; | |
14461 | ||
14462 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14463 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 14464 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14465 | inst.instruction |= cmode << 8; |
14466 | ||
14467 | neon_write_immbits (immbits); | |
14468 | } | |
14469 | ||
14470 | static void | |
14471 | do_neon_mvn (void) | |
14472 | { | |
14473 | if (inst.operands[1].isreg) | |
14474 | { | |
037e8744 | 14475 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 14476 | |
88714cb8 | 14477 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14478 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14479 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14480 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14481 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14482 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14483 | } |
14484 | else | |
14485 | { | |
88714cb8 | 14486 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14487 | neon_move_immediate (); |
14488 | } | |
14489 | ||
88714cb8 | 14490 | neon_dp_fixup (&inst); |
5287ad62 JB |
14491 | } |
14492 | ||
14493 | /* Encode instructions of form: | |
14494 | ||
14495 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 14496 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
14497 | |
14498 | static void | |
14499 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
14500 | { | |
14501 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14502 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14503 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14504 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14505 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14506 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14507 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
14508 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14509 | |
88714cb8 | 14510 | neon_dp_fixup (&inst); |
5287ad62 JB |
14511 | } |
14512 | ||
14513 | static void | |
14514 | do_neon_dyadic_long (void) | |
14515 | { | |
14516 | /* FIXME: Type checking for lengthening op. */ | |
14517 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14518 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14519 | neon_mixed_length (et, et.size); | |
14520 | } | |
14521 | ||
14522 | static void | |
14523 | do_neon_abal (void) | |
14524 | { | |
14525 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14526 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14527 | neon_mixed_length (et, et.size); | |
14528 | } | |
14529 | ||
14530 | static void | |
14531 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
14532 | { | |
14533 | if (inst.operands[2].isscalar) | |
14534 | { | |
dcbf9037 JB |
14535 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
14536 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); | |
88714cb8 | 14537 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14538 | neon_mul_mac (et, et.type == NT_unsigned); |
14539 | } | |
14540 | else | |
14541 | { | |
14542 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14543 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); | |
88714cb8 | 14544 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14545 | neon_mixed_length (et, et.size); |
14546 | } | |
14547 | } | |
14548 | ||
14549 | static void | |
14550 | do_neon_mac_maybe_scalar_long (void) | |
14551 | { | |
14552 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
14553 | } | |
14554 | ||
14555 | static void | |
14556 | do_neon_dyadic_wide (void) | |
14557 | { | |
14558 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
14559 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14560 | neon_mixed_length (et, et.size); | |
14561 | } | |
14562 | ||
14563 | static void | |
14564 | do_neon_dyadic_narrow (void) | |
14565 | { | |
14566 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14567 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
14568 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
14569 | so force the operand type to integer. */ | |
14570 | et.type = NT_integer; | |
5287ad62 JB |
14571 | neon_mixed_length (et, et.size / 2); |
14572 | } | |
14573 | ||
14574 | static void | |
14575 | do_neon_mul_sat_scalar_long (void) | |
14576 | { | |
14577 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
14578 | } | |
14579 | ||
14580 | static void | |
14581 | do_neon_vmull (void) | |
14582 | { | |
14583 | if (inst.operands[2].isscalar) | |
14584 | do_neon_mac_maybe_scalar_long (); | |
14585 | else | |
14586 | { | |
14587 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14588 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); | |
14589 | if (et.type == NT_poly) | |
88714cb8 | 14590 | NEON_ENCODE (POLY, inst); |
5287ad62 | 14591 | else |
88714cb8 | 14592 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14593 | /* For polynomial encoding, size field must be 0b00 and the U bit must be |
14594 | zero. Should be OK as-is. */ | |
14595 | neon_mixed_length (et, et.size); | |
14596 | } | |
14597 | } | |
14598 | ||
14599 | static void | |
14600 | do_neon_ext (void) | |
14601 | { | |
037e8744 | 14602 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
14603 | struct neon_type_el et = neon_check_type (3, rs, |
14604 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14605 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
14606 | |
14607 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
14608 | _("shift out of range")); | |
5287ad62 JB |
14609 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14610 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14611 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14612 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14613 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14614 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 14615 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 14616 | inst.instruction |= imm << 8; |
5f4273c7 | 14617 | |
88714cb8 | 14618 | neon_dp_fixup (&inst); |
5287ad62 JB |
14619 | } |
14620 | ||
14621 | static void | |
14622 | do_neon_rev (void) | |
14623 | { | |
037e8744 | 14624 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14625 | struct neon_type_el et = neon_check_type (2, rs, |
14626 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14627 | unsigned op = (inst.instruction >> 7) & 3; | |
14628 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
14629 | extract it here to check the elements to be reversed are smaller. | |
14630 | Otherwise we'd get a reserved instruction. */ | |
14631 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 14632 | gas_assert (elsize != 0); |
5287ad62 JB |
14633 | constraint (et.size >= elsize, |
14634 | _("elements must be smaller than reversal region")); | |
037e8744 | 14635 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14636 | } |
14637 | ||
14638 | static void | |
14639 | do_neon_dup (void) | |
14640 | { | |
14641 | if (inst.operands[1].isscalar) | |
14642 | { | |
037e8744 | 14643 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 JB |
14644 | struct neon_type_el et = neon_check_type (2, rs, |
14645 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
5287ad62 | 14646 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 14647 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 14648 | int logsize = neon_logbits (et.size); |
dcbf9037 | 14649 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
14650 | |
14651 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
14652 | return; | |
14653 | ||
88714cb8 | 14654 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14655 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14656 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14657 | inst.instruction |= LOW4 (dm); | |
14658 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 14659 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14660 | inst.instruction |= x << 17; |
14661 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 14662 | |
88714cb8 | 14663 | neon_dp_fixup (&inst); |
5287ad62 JB |
14664 | } |
14665 | else | |
14666 | { | |
037e8744 JB |
14667 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
14668 | struct neon_type_el et = neon_check_type (2, rs, | |
14669 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
5287ad62 | 14670 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 14671 | NEON_ENCODE (ARMREG, inst); |
5287ad62 JB |
14672 | switch (et.size) |
14673 | { | |
14674 | case 8: inst.instruction |= 0x400000; break; | |
14675 | case 16: inst.instruction |= 0x000020; break; | |
14676 | case 32: inst.instruction |= 0x000000; break; | |
14677 | default: break; | |
14678 | } | |
14679 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14680 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
14681 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 14682 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 JB |
14683 | /* The encoding for this instruction is identical for the ARM and Thumb |
14684 | variants, except for the condition field. */ | |
037e8744 | 14685 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14686 | } |
14687 | } | |
14688 | ||
14689 | /* VMOV has particularly many variations. It can be one of: | |
14690 | 0. VMOV<c><q> <Qd>, <Qm> | |
14691 | 1. VMOV<c><q> <Dd>, <Dm> | |
14692 | (Register operations, which are VORR with Rm = Rn.) | |
14693 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
14694 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
14695 | (Immediate loads.) | |
14696 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
14697 | (ARM register to scalar.) | |
14698 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
14699 | (Two ARM registers to vector.) | |
14700 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
14701 | (Scalar to ARM register.) | |
14702 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
14703 | (Vector to two ARM registers.) | |
037e8744 JB |
14704 | 8. VMOV.F32 <Sd>, <Sm> |
14705 | 9. VMOV.F64 <Dd>, <Dm> | |
14706 | (VFP register moves.) | |
14707 | 10. VMOV.F32 <Sd>, #imm | |
14708 | 11. VMOV.F64 <Dd>, #imm | |
14709 | (VFP float immediate load.) | |
14710 | 12. VMOV <Rd>, <Sm> | |
14711 | (VFP single to ARM reg.) | |
14712 | 13. VMOV <Sd>, <Rm> | |
14713 | (ARM reg to VFP single.) | |
14714 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
14715 | (Two ARM regs to two VFP singles.) | |
14716 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
14717 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 14718 | |
037e8744 JB |
14719 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
14720 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 14721 | |
5287ad62 | 14722 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 14723 | |
b7fc2769 JB |
14724 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
14725 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 14726 | |
5287ad62 | 14727 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 14728 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
14729 | |
14730 | static void | |
14731 | do_neon_mov (void) | |
14732 | { | |
037e8744 JB |
14733 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
14734 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
14735 | NS_NULL); | |
14736 | struct neon_type_el et; | |
14737 | const char *ldconst = 0; | |
5287ad62 | 14738 | |
037e8744 | 14739 | switch (rs) |
5287ad62 | 14740 | { |
037e8744 JB |
14741 | case NS_DD: /* case 1/9. */ |
14742 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14743 | /* It is not an error here if no type is given. */ | |
14744 | inst.error = NULL; | |
14745 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14746 | { |
037e8744 JB |
14747 | do_vfp_nsyn_opcode ("fcpyd"); |
14748 | break; | |
5287ad62 | 14749 | } |
037e8744 | 14750 | /* fall through. */ |
5287ad62 | 14751 | |
037e8744 JB |
14752 | case NS_QQ: /* case 0/1. */ |
14753 | { | |
14754 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14755 | return; | |
14756 | /* The architecture manual I have doesn't explicitly state which | |
14757 | value the U bit should have for register->register moves, but | |
14758 | the equivalent VORR instruction has U = 0, so do that. */ | |
14759 | inst.instruction = 0x0200110; | |
14760 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14761 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14762 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14763 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14764 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14765 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14766 | inst.instruction |= neon_quad (rs) << 6; | |
14767 | ||
88714cb8 | 14768 | neon_dp_fixup (&inst); |
037e8744 JB |
14769 | } |
14770 | break; | |
5f4273c7 | 14771 | |
037e8744 JB |
14772 | case NS_DI: /* case 3/11. */ |
14773 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14774 | inst.error = NULL; | |
14775 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14776 | { |
037e8744 JB |
14777 | /* case 11 (fconstd). */ |
14778 | ldconst = "fconstd"; | |
14779 | goto encode_fconstd; | |
5287ad62 | 14780 | } |
037e8744 JB |
14781 | /* fall through. */ |
14782 | ||
14783 | case NS_QI: /* case 2/3. */ | |
14784 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14785 | return; | |
14786 | inst.instruction = 0x0800010; | |
14787 | neon_move_immediate (); | |
88714cb8 | 14788 | neon_dp_fixup (&inst); |
5287ad62 | 14789 | break; |
5f4273c7 | 14790 | |
037e8744 JB |
14791 | case NS_SR: /* case 4. */ |
14792 | { | |
14793 | unsigned bcdebits = 0; | |
91d6fa6a | 14794 | int logsize; |
037e8744 JB |
14795 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); |
14796 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
14797 | ||
91d6fa6a NC |
14798 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
14799 | logsize = neon_logbits (et.size); | |
14800 | ||
037e8744 JB |
14801 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14802 | _(BAD_FPU)); | |
14803 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14804 | && et.size != 32, _(BAD_FPU)); | |
14805 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14806 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14807 | ||
14808 | switch (et.size) | |
14809 | { | |
14810 | case 8: bcdebits = 0x8; break; | |
14811 | case 16: bcdebits = 0x1; break; | |
14812 | case 32: bcdebits = 0x0; break; | |
14813 | default: ; | |
14814 | } | |
14815 | ||
14816 | bcdebits |= x << logsize; | |
14817 | ||
14818 | inst.instruction = 0xe000b10; | |
14819 | do_vfp_cond_or_thumb (); | |
14820 | inst.instruction |= LOW4 (dn) << 16; | |
14821 | inst.instruction |= HI1 (dn) << 7; | |
14822 | inst.instruction |= inst.operands[1].reg << 12; | |
14823 | inst.instruction |= (bcdebits & 3) << 5; | |
14824 | inst.instruction |= (bcdebits >> 2) << 21; | |
14825 | } | |
14826 | break; | |
5f4273c7 | 14827 | |
037e8744 | 14828 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 14829 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
037e8744 | 14830 | _(BAD_FPU)); |
b7fc2769 | 14831 | |
037e8744 JB |
14832 | inst.instruction = 0xc400b10; |
14833 | do_vfp_cond_or_thumb (); | |
14834 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
14835 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
14836 | inst.instruction |= inst.operands[1].reg << 12; | |
14837 | inst.instruction |= inst.operands[2].reg << 16; | |
14838 | break; | |
5f4273c7 | 14839 | |
037e8744 JB |
14840 | case NS_RS: /* case 6. */ |
14841 | { | |
91d6fa6a | 14842 | unsigned logsize; |
037e8744 JB |
14843 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); |
14844 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
14845 | unsigned abcdebits = 0; | |
14846 | ||
91d6fa6a NC |
14847 | et = neon_check_type (2, NS_NULL, |
14848 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
14849 | logsize = neon_logbits (et.size); | |
14850 | ||
037e8744 JB |
14851 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14852 | _(BAD_FPU)); | |
14853 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14854 | && et.size != 32, _(BAD_FPU)); | |
14855 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14856 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14857 | ||
14858 | switch (et.size) | |
14859 | { | |
14860 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
14861 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
14862 | case 32: abcdebits = 0x00; break; | |
14863 | default: ; | |
14864 | } | |
14865 | ||
14866 | abcdebits |= x << logsize; | |
14867 | inst.instruction = 0xe100b10; | |
14868 | do_vfp_cond_or_thumb (); | |
14869 | inst.instruction |= LOW4 (dn) << 16; | |
14870 | inst.instruction |= HI1 (dn) << 7; | |
14871 | inst.instruction |= inst.operands[0].reg << 12; | |
14872 | inst.instruction |= (abcdebits & 3) << 5; | |
14873 | inst.instruction |= (abcdebits >> 2) << 21; | |
14874 | } | |
14875 | break; | |
5f4273c7 | 14876 | |
037e8744 JB |
14877 | case NS_RRD: /* case 7 (fmrrd). */ |
14878 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
14879 | _(BAD_FPU)); | |
14880 | ||
14881 | inst.instruction = 0xc500b10; | |
14882 | do_vfp_cond_or_thumb (); | |
14883 | inst.instruction |= inst.operands[0].reg << 12; | |
14884 | inst.instruction |= inst.operands[1].reg << 16; | |
14885 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14886 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14887 | break; | |
5f4273c7 | 14888 | |
037e8744 JB |
14889 | case NS_FF: /* case 8 (fcpys). */ |
14890 | do_vfp_nsyn_opcode ("fcpys"); | |
14891 | break; | |
5f4273c7 | 14892 | |
037e8744 JB |
14893 | case NS_FI: /* case 10 (fconsts). */ |
14894 | ldconst = "fconsts"; | |
14895 | encode_fconstd: | |
14896 | if (is_quarter_float (inst.operands[1].imm)) | |
5287ad62 | 14897 | { |
037e8744 JB |
14898 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
14899 | do_vfp_nsyn_opcode (ldconst); | |
5287ad62 JB |
14900 | } |
14901 | else | |
037e8744 JB |
14902 | first_error (_("immediate out of range")); |
14903 | break; | |
5f4273c7 | 14904 | |
037e8744 JB |
14905 | case NS_RF: /* case 12 (fmrs). */ |
14906 | do_vfp_nsyn_opcode ("fmrs"); | |
14907 | break; | |
5f4273c7 | 14908 | |
037e8744 JB |
14909 | case NS_FR: /* case 13 (fmsr). */ |
14910 | do_vfp_nsyn_opcode ("fmsr"); | |
14911 | break; | |
5f4273c7 | 14912 | |
037e8744 JB |
14913 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
14914 | (one of which is a list), but we have parsed four. Do some fiddling to | |
14915 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
14916 | expect. */ | |
14917 | case NS_RRFF: /* case 14 (fmrrs). */ | |
14918 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
14919 | _("VFP registers must be adjacent")); | |
14920 | inst.operands[2].imm = 2; | |
14921 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
14922 | do_vfp_nsyn_opcode ("fmrrs"); | |
14923 | break; | |
5f4273c7 | 14924 | |
037e8744 JB |
14925 | case NS_FFRR: /* case 15 (fmsrr). */ |
14926 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
14927 | _("VFP registers must be adjacent")); | |
14928 | inst.operands[1] = inst.operands[2]; | |
14929 | inst.operands[2] = inst.operands[3]; | |
14930 | inst.operands[0].imm = 2; | |
14931 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
14932 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 14933 | break; |
5f4273c7 | 14934 | |
5287ad62 JB |
14935 | default: |
14936 | abort (); | |
14937 | } | |
14938 | } | |
14939 | ||
14940 | static void | |
14941 | do_neon_rshift_round_imm (void) | |
14942 | { | |
037e8744 | 14943 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14944 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
14945 | int imm = inst.operands[2].imm; | |
14946 | ||
14947 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
14948 | if (imm == 0) | |
14949 | { | |
14950 | inst.operands[2].present = 0; | |
14951 | do_neon_mov (); | |
14952 | return; | |
14953 | } | |
14954 | ||
14955 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14956 | _("immediate out of range for shift")); | |
037e8744 | 14957 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
14958 | et.size - imm); |
14959 | } | |
14960 | ||
14961 | static void | |
14962 | do_neon_movl (void) | |
14963 | { | |
14964 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
14965 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14966 | unsigned sizebits = et.size >> 3; | |
14967 | inst.instruction |= sizebits << 19; | |
14968 | neon_two_same (0, et.type == NT_unsigned, -1); | |
14969 | } | |
14970 | ||
14971 | static void | |
14972 | do_neon_trn (void) | |
14973 | { | |
037e8744 | 14974 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14975 | struct neon_type_el et = neon_check_type (2, rs, |
14976 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 14977 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 14978 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14979 | } |
14980 | ||
14981 | static void | |
14982 | do_neon_zip_uzp (void) | |
14983 | { | |
037e8744 | 14984 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14985 | struct neon_type_el et = neon_check_type (2, rs, |
14986 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14987 | if (rs == NS_DD && et.size == 32) | |
14988 | { | |
14989 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
14990 | inst.instruction = N_MNEM_vtrn; | |
14991 | do_neon_trn (); | |
14992 | return; | |
14993 | } | |
037e8744 | 14994 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14995 | } |
14996 | ||
14997 | static void | |
14998 | do_neon_sat_abs_neg (void) | |
14999 | { | |
037e8744 | 15000 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15001 | struct neon_type_el et = neon_check_type (2, rs, |
15002 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15003 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15004 | } |
15005 | ||
15006 | static void | |
15007 | do_neon_pair_long (void) | |
15008 | { | |
037e8744 | 15009 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15010 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
15011 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
15012 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 15013 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15014 | } |
15015 | ||
15016 | static void | |
15017 | do_neon_recip_est (void) | |
15018 | { | |
037e8744 | 15019 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15020 | struct neon_type_el et = neon_check_type (2, rs, |
15021 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
15022 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 15023 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15024 | } |
15025 | ||
15026 | static void | |
15027 | do_neon_cls (void) | |
15028 | { | |
037e8744 | 15029 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15030 | struct neon_type_el et = neon_check_type (2, rs, |
15031 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15032 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15033 | } |
15034 | ||
15035 | static void | |
15036 | do_neon_clz (void) | |
15037 | { | |
037e8744 | 15038 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15039 | struct neon_type_el et = neon_check_type (2, rs, |
15040 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 15041 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15042 | } |
15043 | ||
15044 | static void | |
15045 | do_neon_cnt (void) | |
15046 | { | |
037e8744 | 15047 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15048 | struct neon_type_el et = neon_check_type (2, rs, |
15049 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 15050 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15051 | } |
15052 | ||
15053 | static void | |
15054 | do_neon_swp (void) | |
15055 | { | |
037e8744 JB |
15056 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
15057 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
15058 | } |
15059 | ||
15060 | static void | |
15061 | do_neon_tbl_tbx (void) | |
15062 | { | |
15063 | unsigned listlenbits; | |
dcbf9037 | 15064 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 15065 | |
5287ad62 JB |
15066 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
15067 | { | |
dcbf9037 | 15068 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
15069 | return; |
15070 | } | |
5f4273c7 | 15071 | |
5287ad62 JB |
15072 | listlenbits = inst.operands[1].imm - 1; |
15073 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15074 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15075 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15076 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15077 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15078 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15079 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 15080 | |
88714cb8 | 15081 | neon_dp_fixup (&inst); |
5287ad62 JB |
15082 | } |
15083 | ||
15084 | static void | |
15085 | do_neon_ldm_stm (void) | |
15086 | { | |
15087 | /* P, U and L bits are part of bitmask. */ | |
15088 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
15089 | unsigned offsetbits = inst.operands[1].imm * 2; | |
15090 | ||
037e8744 JB |
15091 | if (inst.operands[1].issingle) |
15092 | { | |
15093 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
15094 | return; | |
15095 | } | |
15096 | ||
5287ad62 JB |
15097 | constraint (is_dbmode && !inst.operands[0].writeback, |
15098 | _("writeback (!) must be used for VLDMDB and VSTMDB")); | |
15099 | ||
15100 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
15101 | _("register list must contain at least 1 and at most 16 " | |
15102 | "registers")); | |
15103 | ||
15104 | inst.instruction |= inst.operands[0].reg << 16; | |
15105 | inst.instruction |= inst.operands[0].writeback << 21; | |
15106 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
15107 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
15108 | ||
15109 | inst.instruction |= offsetbits; | |
5f4273c7 | 15110 | |
037e8744 | 15111 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
15112 | } |
15113 | ||
15114 | static void | |
15115 | do_neon_ldr_str (void) | |
15116 | { | |
5287ad62 | 15117 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 15118 | |
6844b2c2 MGD |
15119 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
15120 | And is UNPREDICTABLE in thumb mode. */ | |
15121 | if (!is_ldr | |
15122 | && inst.operands[1].reg == REG_PC | |
15123 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
15124 | { | |
15125 | if (!thumb_mode && warn_on_deprecated) | |
15126 | as_warn (_("Use of PC here is deprecated")); | |
15127 | else | |
15128 | inst.error = _("Use of PC here is UNPREDICTABLE"); | |
15129 | } | |
15130 | ||
037e8744 JB |
15131 | if (inst.operands[0].issingle) |
15132 | { | |
cd2f129f JB |
15133 | if (is_ldr) |
15134 | do_vfp_nsyn_opcode ("flds"); | |
15135 | else | |
15136 | do_vfp_nsyn_opcode ("fsts"); | |
5287ad62 JB |
15137 | } |
15138 | else | |
5287ad62 | 15139 | { |
cd2f129f JB |
15140 | if (is_ldr) |
15141 | do_vfp_nsyn_opcode ("fldd"); | |
5287ad62 | 15142 | else |
cd2f129f | 15143 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 15144 | } |
5287ad62 JB |
15145 | } |
15146 | ||
15147 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
15148 | instructions. */ | |
15149 | ||
15150 | static void | |
15151 | do_neon_ld_st_interleave (void) | |
15152 | { | |
037e8744 | 15153 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
5287ad62 JB |
15154 | N_8 | N_16 | N_32 | N_64); |
15155 | unsigned alignbits = 0; | |
15156 | unsigned idx; | |
15157 | /* The bits in this table go: | |
15158 | 0: register stride of one (0) or two (1) | |
15159 | 1,2: register list length, minus one (1, 2, 3, 4). | |
15160 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
15161 | We use -1 for invalid entries. */ | |
15162 | const int typetable[] = | |
15163 | { | |
15164 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
15165 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
15166 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
15167 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
15168 | }; | |
15169 | int typebits; | |
15170 | ||
dcbf9037 JB |
15171 | if (et.type == NT_invtype) |
15172 | return; | |
15173 | ||
5287ad62 JB |
15174 | if (inst.operands[1].immisalign) |
15175 | switch (inst.operands[1].imm >> 8) | |
15176 | { | |
15177 | case 64: alignbits = 1; break; | |
15178 | case 128: | |
e23c0ad8 JZ |
15179 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
15180 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) | |
5287ad62 JB |
15181 | goto bad_alignment; |
15182 | alignbits = 2; | |
15183 | break; | |
15184 | case 256: | |
e23c0ad8 | 15185 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
5287ad62 JB |
15186 | goto bad_alignment; |
15187 | alignbits = 3; | |
15188 | break; | |
15189 | default: | |
15190 | bad_alignment: | |
dcbf9037 | 15191 | first_error (_("bad alignment")); |
5287ad62 JB |
15192 | return; |
15193 | } | |
15194 | ||
15195 | inst.instruction |= alignbits << 4; | |
15196 | inst.instruction |= neon_logbits (et.size) << 6; | |
15197 | ||
15198 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
15199 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
15200 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
15201 | up the right value for "type" in a table based on this value and the given | |
15202 | list style, then stick it back. */ | |
15203 | idx = ((inst.operands[0].imm >> 4) & 7) | |
15204 | | (((inst.instruction >> 8) & 3) << 3); | |
15205 | ||
15206 | typebits = typetable[idx]; | |
5f4273c7 | 15207 | |
5287ad62 JB |
15208 | constraint (typebits == -1, _("bad list type for instruction")); |
15209 | ||
15210 | inst.instruction &= ~0xf00; | |
15211 | inst.instruction |= typebits << 8; | |
15212 | } | |
15213 | ||
15214 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
15215 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
15216 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
15217 | values, terminated with -1. */ | |
15218 | ||
15219 | static int | |
15220 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
15221 | { | |
15222 | va_list ap; | |
15223 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 15224 | |
5287ad62 JB |
15225 | if (!inst.operands[1].immisalign) |
15226 | { | |
15227 | *do_align = 0; | |
15228 | return SUCCESS; | |
15229 | } | |
5f4273c7 | 15230 | |
5287ad62 JB |
15231 | va_start (ap, do_align); |
15232 | ||
15233 | do | |
15234 | { | |
15235 | thissize = va_arg (ap, int); | |
15236 | if (thissize == -1) | |
15237 | break; | |
15238 | thisalign = va_arg (ap, int); | |
15239 | ||
15240 | if (size == thissize && align == thisalign) | |
15241 | result = SUCCESS; | |
15242 | } | |
15243 | while (result != SUCCESS); | |
15244 | ||
15245 | va_end (ap); | |
15246 | ||
15247 | if (result == SUCCESS) | |
15248 | *do_align = 1; | |
15249 | else | |
dcbf9037 | 15250 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 15251 | |
5287ad62 JB |
15252 | return result; |
15253 | } | |
15254 | ||
15255 | static void | |
15256 | do_neon_ld_st_lane (void) | |
15257 | { | |
037e8744 | 15258 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
15259 | int align_good, do_align = 0; |
15260 | int logsize = neon_logbits (et.size); | |
15261 | int align = inst.operands[1].imm >> 8; | |
15262 | int n = (inst.instruction >> 8) & 3; | |
15263 | int max_el = 64 / et.size; | |
5f4273c7 | 15264 | |
dcbf9037 JB |
15265 | if (et.type == NT_invtype) |
15266 | return; | |
5f4273c7 | 15267 | |
5287ad62 JB |
15268 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
15269 | _("bad list length")); | |
15270 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, | |
15271 | _("scalar index out of range")); | |
15272 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 | |
15273 | && et.size == 8, | |
15274 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 15275 | |
5287ad62 JB |
15276 | switch (n) |
15277 | { | |
15278 | case 0: /* VLD1 / VST1. */ | |
15279 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
15280 | 32, 32, -1); | |
15281 | if (align_good == FAIL) | |
15282 | return; | |
15283 | if (do_align) | |
15284 | { | |
15285 | unsigned alignbits = 0; | |
15286 | switch (et.size) | |
15287 | { | |
15288 | case 16: alignbits = 0x1; break; | |
15289 | case 32: alignbits = 0x3; break; | |
15290 | default: ; | |
15291 | } | |
15292 | inst.instruction |= alignbits << 4; | |
15293 | } | |
15294 | break; | |
15295 | ||
15296 | case 1: /* VLD2 / VST2. */ | |
15297 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
15298 | 32, 64, -1); | |
15299 | if (align_good == FAIL) | |
15300 | return; | |
15301 | if (do_align) | |
15302 | inst.instruction |= 1 << 4; | |
15303 | break; | |
15304 | ||
15305 | case 2: /* VLD3 / VST3. */ | |
15306 | constraint (inst.operands[1].immisalign, | |
15307 | _("can't use alignment with this instruction")); | |
15308 | break; | |
15309 | ||
15310 | case 3: /* VLD4 / VST4. */ | |
15311 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15312 | 16, 64, 32, 64, 32, 128, -1); | |
15313 | if (align_good == FAIL) | |
15314 | return; | |
15315 | if (do_align) | |
15316 | { | |
15317 | unsigned alignbits = 0; | |
15318 | switch (et.size) | |
15319 | { | |
15320 | case 8: alignbits = 0x1; break; | |
15321 | case 16: alignbits = 0x1; break; | |
15322 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
15323 | default: ; | |
15324 | } | |
15325 | inst.instruction |= alignbits << 4; | |
15326 | } | |
15327 | break; | |
15328 | ||
15329 | default: ; | |
15330 | } | |
15331 | ||
15332 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
15333 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15334 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 15335 | |
5287ad62 JB |
15336 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
15337 | inst.instruction |= logsize << 10; | |
15338 | } | |
15339 | ||
15340 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
15341 | ||
15342 | static void | |
15343 | do_neon_ld_dup (void) | |
15344 | { | |
037e8744 | 15345 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
15346 | int align_good, do_align = 0; |
15347 | ||
dcbf9037 JB |
15348 | if (et.type == NT_invtype) |
15349 | return; | |
15350 | ||
5287ad62 JB |
15351 | switch ((inst.instruction >> 8) & 3) |
15352 | { | |
15353 | case 0: /* VLD1. */ | |
9c2799c2 | 15354 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 JB |
15355 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
15356 | &do_align, 16, 16, 32, 32, -1); | |
15357 | if (align_good == FAIL) | |
15358 | return; | |
15359 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) | |
15360 | { | |
15361 | case 1: break; | |
15362 | case 2: inst.instruction |= 1 << 5; break; | |
dcbf9037 | 15363 | default: first_error (_("bad list length")); return; |
5287ad62 JB |
15364 | } |
15365 | inst.instruction |= neon_logbits (et.size) << 6; | |
15366 | break; | |
15367 | ||
15368 | case 1: /* VLD2. */ | |
15369 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
15370 | &do_align, 8, 16, 16, 32, 32, 64, -1); | |
15371 | if (align_good == FAIL) | |
15372 | return; | |
15373 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, | |
15374 | _("bad list length")); | |
15375 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15376 | inst.instruction |= 1 << 5; | |
15377 | inst.instruction |= neon_logbits (et.size) << 6; | |
15378 | break; | |
15379 | ||
15380 | case 2: /* VLD3. */ | |
15381 | constraint (inst.operands[1].immisalign, | |
15382 | _("can't use alignment with this instruction")); | |
15383 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, | |
15384 | _("bad list length")); | |
15385 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15386 | inst.instruction |= 1 << 5; | |
15387 | inst.instruction |= neon_logbits (et.size) << 6; | |
15388 | break; | |
15389 | ||
15390 | case 3: /* VLD4. */ | |
15391 | { | |
15392 | int align = inst.operands[1].imm >> 8; | |
15393 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15394 | 16, 64, 32, 64, 32, 128, -1); | |
15395 | if (align_good == FAIL) | |
15396 | return; | |
15397 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
15398 | _("bad list length")); | |
15399 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15400 | inst.instruction |= 1 << 5; | |
15401 | if (et.size == 32 && align == 128) | |
15402 | inst.instruction |= 0x3 << 6; | |
15403 | else | |
15404 | inst.instruction |= neon_logbits (et.size) << 6; | |
15405 | } | |
15406 | break; | |
15407 | ||
15408 | default: ; | |
15409 | } | |
15410 | ||
15411 | inst.instruction |= do_align << 4; | |
15412 | } | |
15413 | ||
15414 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
15415 | apart from bits [11:4]. */ | |
15416 | ||
15417 | static void | |
15418 | do_neon_ldx_stx (void) | |
15419 | { | |
b1a769ed DG |
15420 | if (inst.operands[1].isreg) |
15421 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
15422 | ||
5287ad62 JB |
15423 | switch (NEON_LANE (inst.operands[0].imm)) |
15424 | { | |
15425 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 15426 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
15427 | do_neon_ld_st_interleave (); |
15428 | break; | |
5f4273c7 | 15429 | |
5287ad62 | 15430 | case NEON_ALL_LANES: |
88714cb8 | 15431 | NEON_ENCODE (DUP, inst); |
5287ad62 JB |
15432 | do_neon_ld_dup (); |
15433 | break; | |
5f4273c7 | 15434 | |
5287ad62 | 15435 | default: |
88714cb8 | 15436 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
15437 | do_neon_ld_st_lane (); |
15438 | } | |
15439 | ||
15440 | /* L bit comes from bit mask. */ | |
15441 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15442 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15443 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 15444 | |
5287ad62 JB |
15445 | if (inst.operands[1].postind) |
15446 | { | |
15447 | int postreg = inst.operands[1].imm & 0xf; | |
15448 | constraint (!inst.operands[1].immisreg, | |
15449 | _("post-index must be a register")); | |
15450 | constraint (postreg == 0xd || postreg == 0xf, | |
15451 | _("bad register for post-index")); | |
15452 | inst.instruction |= postreg; | |
15453 | } | |
15454 | else if (inst.operands[1].writeback) | |
15455 | { | |
15456 | inst.instruction |= 0xd; | |
15457 | } | |
15458 | else | |
5f4273c7 NC |
15459 | inst.instruction |= 0xf; |
15460 | ||
5287ad62 JB |
15461 | if (thumb_mode) |
15462 | inst.instruction |= 0xf9000000; | |
15463 | else | |
15464 | inst.instruction |= 0xf4000000; | |
15465 | } | |
5287ad62 JB |
15466 | \f |
15467 | /* Overall per-instruction processing. */ | |
15468 | ||
15469 | /* We need to be able to fix up arbitrary expressions in some statements. | |
15470 | This is so that we can handle symbols that are an arbitrary distance from | |
15471 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
15472 | which returns part of an address in a form which will be valid for | |
15473 | a data instruction. We do this by pushing the expression into a symbol | |
15474 | in the expr_section, and creating a fix for that. */ | |
15475 | ||
15476 | static void | |
15477 | fix_new_arm (fragS * frag, | |
15478 | int where, | |
15479 | short int size, | |
15480 | expressionS * exp, | |
15481 | int pc_rel, | |
15482 | int reloc) | |
15483 | { | |
15484 | fixS * new_fix; | |
15485 | ||
15486 | switch (exp->X_op) | |
15487 | { | |
15488 | case O_constant: | |
6e7ce2cd PB |
15489 | if (pc_rel) |
15490 | { | |
15491 | /* Create an absolute valued symbol, so we have something to | |
15492 | refer to in the object file. Unfortunately for us, gas's | |
15493 | generic expression parsing will already have folded out | |
15494 | any use of .set foo/.type foo %function that may have | |
15495 | been used to set type information of the target location, | |
15496 | that's being specified symbolically. We have to presume | |
15497 | the user knows what they are doing. */ | |
15498 | char name[16 + 8]; | |
15499 | symbolS *symbol; | |
15500 | ||
15501 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
15502 | ||
15503 | symbol = symbol_find_or_make (name); | |
15504 | S_SET_SEGMENT (symbol, absolute_section); | |
15505 | symbol_set_frag (symbol, &zero_address_frag); | |
15506 | S_SET_VALUE (symbol, exp->X_add_number); | |
15507 | exp->X_op = O_symbol; | |
15508 | exp->X_add_symbol = symbol; | |
15509 | exp->X_add_number = 0; | |
15510 | } | |
15511 | /* FALLTHROUGH */ | |
5287ad62 JB |
15512 | case O_symbol: |
15513 | case O_add: | |
15514 | case O_subtract: | |
21d799b5 NC |
15515 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
15516 | (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15517 | break; |
15518 | ||
15519 | default: | |
21d799b5 NC |
15520 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
15521 | pc_rel, (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15522 | break; |
15523 | } | |
15524 | ||
15525 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
15526 | instruction. */ | |
15527 | new_fix->tc_fix_data = thumb_mode; | |
15528 | } | |
15529 | ||
15530 | /* Create a frg for an instruction requiring relaxation. */ | |
15531 | static void | |
15532 | output_relax_insn (void) | |
15533 | { | |
15534 | char * to; | |
15535 | symbolS *sym; | |
0110f2b8 PB |
15536 | int offset; |
15537 | ||
6e1cb1a6 PB |
15538 | /* The size of the instruction is unknown, so tie the debug info to the |
15539 | start of the instruction. */ | |
15540 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 15541 | |
0110f2b8 PB |
15542 | switch (inst.reloc.exp.X_op) |
15543 | { | |
15544 | case O_symbol: | |
15545 | sym = inst.reloc.exp.X_add_symbol; | |
15546 | offset = inst.reloc.exp.X_add_number; | |
15547 | break; | |
15548 | case O_constant: | |
15549 | sym = NULL; | |
15550 | offset = inst.reloc.exp.X_add_number; | |
15551 | break; | |
15552 | default: | |
15553 | sym = make_expr_symbol (&inst.reloc.exp); | |
15554 | offset = 0; | |
15555 | break; | |
15556 | } | |
15557 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
15558 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
15559 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
15560 | } |
15561 | ||
15562 | /* Write a 32-bit thumb instruction to buf. */ | |
15563 | static void | |
15564 | put_thumb32_insn (char * buf, unsigned long insn) | |
15565 | { | |
15566 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
15567 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
15568 | } | |
15569 | ||
b99bd4ef | 15570 | static void |
c19d1205 | 15571 | output_inst (const char * str) |
b99bd4ef | 15572 | { |
c19d1205 | 15573 | char * to = NULL; |
b99bd4ef | 15574 | |
c19d1205 | 15575 | if (inst.error) |
b99bd4ef | 15576 | { |
c19d1205 | 15577 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
15578 | return; |
15579 | } | |
5f4273c7 NC |
15580 | if (inst.relax) |
15581 | { | |
15582 | output_relax_insn (); | |
0110f2b8 | 15583 | return; |
5f4273c7 | 15584 | } |
c19d1205 ZW |
15585 | if (inst.size == 0) |
15586 | return; | |
b99bd4ef | 15587 | |
c19d1205 | 15588 | to = frag_more (inst.size); |
8dc2430f NC |
15589 | /* PR 9814: Record the thumb mode into the current frag so that we know |
15590 | what type of NOP padding to use, if necessary. We override any previous | |
15591 | setting so that if the mode has changed then the NOPS that we use will | |
15592 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 15593 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
15594 | |
15595 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 15596 | { |
9c2799c2 | 15597 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 15598 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 15599 | } |
c19d1205 | 15600 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 15601 | { |
9c2799c2 | 15602 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
15603 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
15604 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 15605 | } |
c19d1205 ZW |
15606 | else |
15607 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 15608 | |
c19d1205 ZW |
15609 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
15610 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
15611 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
15612 | inst.reloc.type); | |
b99bd4ef | 15613 | |
c19d1205 | 15614 | dwarf2_emit_insn (inst.size); |
c19d1205 | 15615 | } |
b99bd4ef | 15616 | |
e07e6e58 NC |
15617 | static char * |
15618 | output_it_inst (int cond, int mask, char * to) | |
15619 | { | |
15620 | unsigned long instruction = 0xbf00; | |
15621 | ||
15622 | mask &= 0xf; | |
15623 | instruction |= mask; | |
15624 | instruction |= cond << 4; | |
15625 | ||
15626 | if (to == NULL) | |
15627 | { | |
15628 | to = frag_more (2); | |
15629 | #ifdef OBJ_ELF | |
15630 | dwarf2_emit_insn (2); | |
15631 | #endif | |
15632 | } | |
15633 | ||
15634 | md_number_to_chars (to, instruction, 2); | |
15635 | ||
15636 | return to; | |
15637 | } | |
15638 | ||
c19d1205 ZW |
15639 | /* Tag values used in struct asm_opcode's tag field. */ |
15640 | enum opcode_tag | |
15641 | { | |
15642 | OT_unconditional, /* Instruction cannot be conditionalized. | |
15643 | The ARM condition field is still 0xE. */ | |
15644 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
15645 | and carries 0xF in its ARM condition field. */ | |
15646 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 JB |
15647 | OT_csuffixF, /* Some forms of the instruction take a conditional |
15648 | suffix, others place 0xF where the condition field | |
15649 | would be. */ | |
c19d1205 ZW |
15650 | OT_cinfix3, /* Instruction takes a conditional infix, |
15651 | beginning at character index 3. (In | |
15652 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
15653 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
15654 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
15655 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
15656 | character index 3, even in unified mode. Used for | |
15657 | legacy instructions where suffix and infix forms | |
15658 | may be ambiguous. */ | |
c19d1205 | 15659 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 15660 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
15661 | OT_odd_infix_unc, /* This is the unconditional variant of an |
15662 | instruction that takes a conditional infix | |
15663 | at an unusual position. In unified mode, | |
15664 | this variant will accept a suffix. */ | |
15665 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
15666 | are the conditional variants of instructions that | |
15667 | take conditional infixes in unusual positions. | |
15668 | The infix appears at character index | |
15669 | (tag - OT_odd_infix_0). These are not accepted | |
15670 | in unified mode. */ | |
15671 | }; | |
b99bd4ef | 15672 | |
c19d1205 ZW |
15673 | /* Subroutine of md_assemble, responsible for looking up the primary |
15674 | opcode from the mnemonic the user wrote. STR points to the | |
15675 | beginning of the mnemonic. | |
15676 | ||
15677 | This is not simply a hash table lookup, because of conditional | |
15678 | variants. Most instructions have conditional variants, which are | |
15679 | expressed with a _conditional affix_ to the mnemonic. If we were | |
15680 | to encode each conditional variant as a literal string in the opcode | |
15681 | table, it would have approximately 20,000 entries. | |
15682 | ||
15683 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
15684 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
15685 | instructions take the affix as an infix, notably the s-variants of | |
15686 | the arithmetic instructions. Of those instructions, all but six | |
15687 | have the infix appear after the third character of the mnemonic. | |
15688 | ||
15689 | Accordingly, the algorithm for looking up primary opcodes given | |
15690 | an identifier is: | |
15691 | ||
15692 | 1. Look up the identifier in the opcode table. | |
15693 | If we find a match, go to step U. | |
15694 | ||
15695 | 2. Look up the last two characters of the identifier in the | |
15696 | conditions table. If we find a match, look up the first N-2 | |
15697 | characters of the identifier in the opcode table. If we | |
15698 | find a match, go to step CE. | |
15699 | ||
15700 | 3. Look up the fourth and fifth characters of the identifier in | |
15701 | the conditions table. If we find a match, extract those | |
15702 | characters from the identifier, and look up the remaining | |
15703 | characters in the opcode table. If we find a match, go | |
15704 | to step CM. | |
15705 | ||
15706 | 4. Fail. | |
15707 | ||
15708 | U. Examine the tag field of the opcode structure, in case this is | |
15709 | one of the six instructions with its conditional infix in an | |
15710 | unusual place. If it is, the tag tells us where to find the | |
15711 | infix; look it up in the conditions table and set inst.cond | |
15712 | accordingly. Otherwise, this is an unconditional instruction. | |
15713 | Again set inst.cond accordingly. Return the opcode structure. | |
15714 | ||
15715 | CE. Examine the tag field to make sure this is an instruction that | |
15716 | should receive a conditional suffix. If it is not, fail. | |
15717 | Otherwise, set inst.cond from the suffix we already looked up, | |
15718 | and return the opcode structure. | |
15719 | ||
15720 | CM. Examine the tag field to make sure this is an instruction that | |
15721 | should receive a conditional infix after the third character. | |
15722 | If it is not, fail. Otherwise, undo the edits to the current | |
15723 | line of input and proceed as for case CE. */ | |
15724 | ||
15725 | static const struct asm_opcode * | |
15726 | opcode_lookup (char **str) | |
15727 | { | |
15728 | char *end, *base; | |
15729 | char *affix; | |
15730 | const struct asm_opcode *opcode; | |
15731 | const struct asm_cond *cond; | |
e3cb604e | 15732 | char save[2]; |
c19d1205 ZW |
15733 | |
15734 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 15735 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 15736 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 15737 | if (*end == ' ' || *end == '.') |
c19d1205 | 15738 | break; |
b99bd4ef | 15739 | |
c19d1205 | 15740 | if (end == base) |
c921be7d | 15741 | return NULL; |
b99bd4ef | 15742 | |
5287ad62 | 15743 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 15744 | if (end[0] == '.') |
b99bd4ef | 15745 | { |
5287ad62 | 15746 | int offset = 2; |
5f4273c7 | 15747 | |
267d2029 JB |
15748 | /* The .w and .n suffixes are only valid if the unified syntax is in |
15749 | use. */ | |
15750 | if (unified_syntax && end[1] == 'w') | |
c19d1205 | 15751 | inst.size_req = 4; |
267d2029 | 15752 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
15753 | inst.size_req = 2; |
15754 | else | |
5287ad62 JB |
15755 | offset = 0; |
15756 | ||
15757 | inst.vectype.elems = 0; | |
15758 | ||
15759 | *str = end + offset; | |
b99bd4ef | 15760 | |
5f4273c7 | 15761 | if (end[offset] == '.') |
5287ad62 | 15762 | { |
267d2029 JB |
15763 | /* See if we have a Neon type suffix (possible in either unified or |
15764 | non-unified ARM syntax mode). */ | |
dcbf9037 | 15765 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
c921be7d | 15766 | return NULL; |
5287ad62 JB |
15767 | } |
15768 | else if (end[offset] != '\0' && end[offset] != ' ') | |
c921be7d | 15769 | return NULL; |
b99bd4ef | 15770 | } |
c19d1205 ZW |
15771 | else |
15772 | *str = end; | |
b99bd4ef | 15773 | |
c19d1205 | 15774 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 NC |
15775 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15776 | end - base); | |
c19d1205 | 15777 | if (opcode) |
b99bd4ef | 15778 | { |
c19d1205 ZW |
15779 | /* step U */ |
15780 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 15781 | { |
c19d1205 ZW |
15782 | inst.cond = COND_ALWAYS; |
15783 | return opcode; | |
b99bd4ef | 15784 | } |
b99bd4ef | 15785 | |
278df34e | 15786 | if (warn_on_deprecated && unified_syntax) |
c19d1205 ZW |
15787 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15788 | affix = base + (opcode->tag - OT_odd_infix_0); | |
21d799b5 | 15789 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 15790 | gas_assert (cond); |
b99bd4ef | 15791 | |
c19d1205 ZW |
15792 | inst.cond = cond->value; |
15793 | return opcode; | |
15794 | } | |
b99bd4ef | 15795 | |
c19d1205 ZW |
15796 | /* Cannot have a conditional suffix on a mnemonic of less than two |
15797 | characters. */ | |
15798 | if (end - base < 3) | |
c921be7d | 15799 | return NULL; |
b99bd4ef | 15800 | |
c19d1205 ZW |
15801 | /* Look for suffixed mnemonic. */ |
15802 | affix = end - 2; | |
21d799b5 NC |
15803 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
15804 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
15805 | affix - base); | |
c19d1205 ZW |
15806 | if (opcode && cond) |
15807 | { | |
15808 | /* step CE */ | |
15809 | switch (opcode->tag) | |
15810 | { | |
e3cb604e PB |
15811 | case OT_cinfix3_legacy: |
15812 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
15813 | break; | |
15814 | ||
c19d1205 | 15815 | case OT_cinfix3: |
088fa78e | 15816 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
15817 | case OT_odd_infix_unc: |
15818 | if (!unified_syntax) | |
e3cb604e | 15819 | return 0; |
c19d1205 ZW |
15820 | /* else fall through */ |
15821 | ||
15822 | case OT_csuffix: | |
037e8744 | 15823 | case OT_csuffixF: |
c19d1205 ZW |
15824 | case OT_csuf_or_in3: |
15825 | inst.cond = cond->value; | |
15826 | return opcode; | |
15827 | ||
15828 | case OT_unconditional: | |
15829 | case OT_unconditionalF: | |
dfa9f0d5 | 15830 | if (thumb_mode) |
c921be7d | 15831 | inst.cond = cond->value; |
dfa9f0d5 PB |
15832 | else |
15833 | { | |
c921be7d | 15834 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
15835 | inst.error = BAD_COND; |
15836 | inst.cond = COND_ALWAYS; | |
15837 | } | |
c19d1205 | 15838 | return opcode; |
b99bd4ef | 15839 | |
c19d1205 | 15840 | default: |
c921be7d | 15841 | return NULL; |
c19d1205 ZW |
15842 | } |
15843 | } | |
b99bd4ef | 15844 | |
c19d1205 ZW |
15845 | /* Cannot have a usual-position infix on a mnemonic of less than |
15846 | six characters (five would be a suffix). */ | |
15847 | if (end - base < 6) | |
c921be7d | 15848 | return NULL; |
b99bd4ef | 15849 | |
c19d1205 ZW |
15850 | /* Look for infixed mnemonic in the usual position. */ |
15851 | affix = base + 3; | |
21d799b5 | 15852 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 15853 | if (!cond) |
c921be7d | 15854 | return NULL; |
e3cb604e PB |
15855 | |
15856 | memcpy (save, affix, 2); | |
15857 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 NC |
15858 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15859 | (end - base) - 2); | |
e3cb604e PB |
15860 | memmove (affix + 2, affix, (end - affix) - 2); |
15861 | memcpy (affix, save, 2); | |
15862 | ||
088fa78e KH |
15863 | if (opcode |
15864 | && (opcode->tag == OT_cinfix3 | |
15865 | || opcode->tag == OT_cinfix3_deprecated | |
15866 | || opcode->tag == OT_csuf_or_in3 | |
15867 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 15868 | { |
c921be7d | 15869 | /* Step CM. */ |
278df34e | 15870 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
15871 | && (opcode->tag == OT_cinfix3 |
15872 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
15873 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15874 | ||
15875 | inst.cond = cond->value; | |
15876 | return opcode; | |
b99bd4ef NC |
15877 | } |
15878 | ||
c921be7d | 15879 | return NULL; |
b99bd4ef NC |
15880 | } |
15881 | ||
e07e6e58 NC |
15882 | /* This function generates an initial IT instruction, leaving its block |
15883 | virtually open for the new instructions. Eventually, | |
15884 | the mask will be updated by now_it_add_mask () each time | |
15885 | a new instruction needs to be included in the IT block. | |
15886 | Finally, the block is closed with close_automatic_it_block (). | |
15887 | The block closure can be requested either from md_assemble (), | |
15888 | a tencode (), or due to a label hook. */ | |
15889 | ||
15890 | static void | |
15891 | new_automatic_it_block (int cond) | |
15892 | { | |
15893 | now_it.state = AUTOMATIC_IT_BLOCK; | |
15894 | now_it.mask = 0x18; | |
15895 | now_it.cc = cond; | |
15896 | now_it.block_length = 1; | |
cd000bff | 15897 | mapping_state (MAP_THUMB); |
e07e6e58 NC |
15898 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
15899 | } | |
15900 | ||
15901 | /* Close an automatic IT block. | |
15902 | See comments in new_automatic_it_block (). */ | |
15903 | ||
15904 | static void | |
15905 | close_automatic_it_block (void) | |
15906 | { | |
15907 | now_it.mask = 0x10; | |
15908 | now_it.block_length = 0; | |
15909 | } | |
15910 | ||
15911 | /* Update the mask of the current automatically-generated IT | |
15912 | instruction. See comments in new_automatic_it_block (). */ | |
15913 | ||
15914 | static void | |
15915 | now_it_add_mask (int cond) | |
15916 | { | |
15917 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
15918 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
15919 | | ((bitvalue) << (nbit))) | |
e07e6e58 | 15920 | const int resulting_bit = (cond & 1); |
c921be7d | 15921 | |
e07e6e58 NC |
15922 | now_it.mask &= 0xf; |
15923 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
15924 | resulting_bit, | |
15925 | (5 - now_it.block_length)); | |
15926 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
15927 | 1, | |
15928 | ((5 - now_it.block_length) - 1) ); | |
15929 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); | |
15930 | ||
15931 | #undef CLEAR_BIT | |
15932 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
15933 | } |
15934 | ||
15935 | /* The IT blocks handling machinery is accessed through the these functions: | |
15936 | it_fsm_pre_encode () from md_assemble () | |
15937 | set_it_insn_type () optional, from the tencode functions | |
15938 | set_it_insn_type_last () ditto | |
15939 | in_it_block () ditto | |
15940 | it_fsm_post_encode () from md_assemble () | |
15941 | force_automatic_it_block_close () from label habdling functions | |
15942 | ||
15943 | Rationale: | |
15944 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
15945 | initializing the IT insn type with a generic initial value depending | |
15946 | on the inst.condition. | |
15947 | 2) During the tencode function, two things may happen: | |
15948 | a) The tencode function overrides the IT insn type by | |
15949 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
15950 | b) The tencode function queries the IT block state by | |
15951 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
15952 | ||
15953 | Both set_it_insn_type and in_it_block run the internal FSM state | |
15954 | handling function (handle_it_state), because: a) setting the IT insn | |
15955 | type may incur in an invalid state (exiting the function), | |
15956 | and b) querying the state requires the FSM to be updated. | |
15957 | Specifically we want to avoid creating an IT block for conditional | |
15958 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
15959 | determine whether an IT block is required until the tencode () routine | |
15960 | has decided what type of instruction this actually it. | |
15961 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
15962 | set_it_insn_type has to be called first. | |
15963 | ||
15964 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
15965 | determines the insn IT type depending on the inst.cond code. | |
15966 | When a tencode () routine encodes an instruction that can be | |
15967 | either outside an IT block, or, in the case of being inside, has to be | |
15968 | the last one, set_it_insn_type_last () will determine the proper | |
15969 | IT instruction type based on the inst.cond code. Otherwise, | |
15970 | set_it_insn_type can be called for overriding that logic or | |
15971 | for covering other cases. | |
15972 | ||
15973 | Calling handle_it_state () may not transition the IT block state to | |
15974 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
15975 | still queried. Instead, if the FSM determines that the state should | |
15976 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
15977 | after the tencode () function: that's what it_fsm_post_encode () does. | |
15978 | ||
15979 | Since in_it_block () calls the state handling function to get an | |
15980 | updated state, an error may occur (due to invalid insns combination). | |
15981 | In that case, inst.error is set. | |
15982 | Therefore, inst.error has to be checked after the execution of | |
15983 | the tencode () routine. | |
15984 | ||
15985 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
15986 | any pending state change (if any) that didn't take place in | |
15987 | handle_it_state () as explained above. */ | |
15988 | ||
15989 | static void | |
15990 | it_fsm_pre_encode (void) | |
15991 | { | |
15992 | if (inst.cond != COND_ALWAYS) | |
15993 | inst.it_insn_type = INSIDE_IT_INSN; | |
15994 | else | |
15995 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
15996 | ||
15997 | now_it.state_handled = 0; | |
15998 | } | |
15999 | ||
16000 | /* IT state FSM handling function. */ | |
16001 | ||
16002 | static int | |
16003 | handle_it_state (void) | |
16004 | { | |
16005 | now_it.state_handled = 1; | |
16006 | ||
16007 | switch (now_it.state) | |
16008 | { | |
16009 | case OUTSIDE_IT_BLOCK: | |
16010 | switch (inst.it_insn_type) | |
16011 | { | |
16012 | case OUTSIDE_IT_INSN: | |
16013 | break; | |
16014 | ||
16015 | case INSIDE_IT_INSN: | |
16016 | case INSIDE_IT_LAST_INSN: | |
16017 | if (thumb_mode == 0) | |
16018 | { | |
c921be7d | 16019 | if (unified_syntax |
e07e6e58 NC |
16020 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
16021 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
16022 | " for Thumb.")); | |
16023 | } | |
16024 | else | |
16025 | { | |
16026 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
16027 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
16028 | { | |
16029 | /* Automatically generate the IT instruction. */ | |
16030 | new_automatic_it_block (inst.cond); | |
16031 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
16032 | close_automatic_it_block (); | |
16033 | } | |
16034 | else | |
16035 | { | |
16036 | inst.error = BAD_OUT_IT; | |
16037 | return FAIL; | |
16038 | } | |
16039 | } | |
16040 | break; | |
16041 | ||
16042 | case IF_INSIDE_IT_LAST_INSN: | |
16043 | case NEUTRAL_IT_INSN: | |
16044 | break; | |
16045 | ||
16046 | case IT_INSN: | |
16047 | now_it.state = MANUAL_IT_BLOCK; | |
16048 | now_it.block_length = 0; | |
16049 | break; | |
16050 | } | |
16051 | break; | |
16052 | ||
16053 | case AUTOMATIC_IT_BLOCK: | |
16054 | /* Three things may happen now: | |
16055 | a) We should increment current it block size; | |
16056 | b) We should close current it block (closing insn or 4 insns); | |
16057 | c) We should close current it block and start a new one (due | |
16058 | to incompatible conditions or | |
16059 | 4 insns-length block reached). */ | |
16060 | ||
16061 | switch (inst.it_insn_type) | |
16062 | { | |
16063 | case OUTSIDE_IT_INSN: | |
16064 | /* The closure of the block shall happen immediatelly, | |
16065 | so any in_it_block () call reports the block as closed. */ | |
16066 | force_automatic_it_block_close (); | |
16067 | break; | |
16068 | ||
16069 | case INSIDE_IT_INSN: | |
16070 | case INSIDE_IT_LAST_INSN: | |
16071 | case IF_INSIDE_IT_LAST_INSN: | |
16072 | now_it.block_length++; | |
16073 | ||
16074 | if (now_it.block_length > 4 | |
16075 | || !now_it_compatible (inst.cond)) | |
16076 | { | |
16077 | force_automatic_it_block_close (); | |
16078 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
16079 | new_automatic_it_block (inst.cond); | |
16080 | } | |
16081 | else | |
16082 | { | |
16083 | now_it_add_mask (inst.cond); | |
16084 | } | |
16085 | ||
16086 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
16087 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
16088 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
16089 | close_automatic_it_block (); | |
16090 | break; | |
16091 | ||
16092 | case NEUTRAL_IT_INSN: | |
16093 | now_it.block_length++; | |
16094 | ||
16095 | if (now_it.block_length > 4) | |
16096 | force_automatic_it_block_close (); | |
16097 | else | |
16098 | now_it_add_mask (now_it.cc & 1); | |
16099 | break; | |
16100 | ||
16101 | case IT_INSN: | |
16102 | close_automatic_it_block (); | |
16103 | now_it.state = MANUAL_IT_BLOCK; | |
16104 | break; | |
16105 | } | |
16106 | break; | |
16107 | ||
16108 | case MANUAL_IT_BLOCK: | |
16109 | { | |
16110 | /* Check conditional suffixes. */ | |
16111 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
16112 | int is_last; | |
16113 | now_it.mask <<= 1; | |
16114 | now_it.mask &= 0x1f; | |
16115 | is_last = (now_it.mask == 0x10); | |
16116 | ||
16117 | switch (inst.it_insn_type) | |
16118 | { | |
16119 | case OUTSIDE_IT_INSN: | |
16120 | inst.error = BAD_NOT_IT; | |
16121 | return FAIL; | |
16122 | ||
16123 | case INSIDE_IT_INSN: | |
16124 | if (cond != inst.cond) | |
16125 | { | |
16126 | inst.error = BAD_IT_COND; | |
16127 | return FAIL; | |
16128 | } | |
16129 | break; | |
16130 | ||
16131 | case INSIDE_IT_LAST_INSN: | |
16132 | case IF_INSIDE_IT_LAST_INSN: | |
16133 | if (cond != inst.cond) | |
16134 | { | |
16135 | inst.error = BAD_IT_COND; | |
16136 | return FAIL; | |
16137 | } | |
16138 | if (!is_last) | |
16139 | { | |
16140 | inst.error = BAD_BRANCH; | |
16141 | return FAIL; | |
16142 | } | |
16143 | break; | |
16144 | ||
16145 | case NEUTRAL_IT_INSN: | |
16146 | /* The BKPT instruction is unconditional even in an IT block. */ | |
16147 | break; | |
16148 | ||
16149 | case IT_INSN: | |
16150 | inst.error = BAD_IT_IT; | |
16151 | return FAIL; | |
16152 | } | |
16153 | } | |
16154 | break; | |
16155 | } | |
16156 | ||
16157 | return SUCCESS; | |
16158 | } | |
16159 | ||
16160 | static void | |
16161 | it_fsm_post_encode (void) | |
16162 | { | |
16163 | int is_last; | |
16164 | ||
16165 | if (!now_it.state_handled) | |
16166 | handle_it_state (); | |
16167 | ||
16168 | is_last = (now_it.mask == 0x10); | |
16169 | if (is_last) | |
16170 | { | |
16171 | now_it.state = OUTSIDE_IT_BLOCK; | |
16172 | now_it.mask = 0; | |
16173 | } | |
16174 | } | |
16175 | ||
16176 | static void | |
16177 | force_automatic_it_block_close (void) | |
16178 | { | |
16179 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
16180 | { | |
16181 | close_automatic_it_block (); | |
16182 | now_it.state = OUTSIDE_IT_BLOCK; | |
16183 | now_it.mask = 0; | |
16184 | } | |
16185 | } | |
16186 | ||
16187 | static int | |
16188 | in_it_block (void) | |
16189 | { | |
16190 | if (!now_it.state_handled) | |
16191 | handle_it_state (); | |
16192 | ||
16193 | return now_it.state != OUTSIDE_IT_BLOCK; | |
16194 | } | |
16195 | ||
c19d1205 ZW |
16196 | void |
16197 | md_assemble (char *str) | |
b99bd4ef | 16198 | { |
c19d1205 ZW |
16199 | char *p = str; |
16200 | const struct asm_opcode * opcode; | |
b99bd4ef | 16201 | |
c19d1205 ZW |
16202 | /* Align the previous label if needed. */ |
16203 | if (last_label_seen != NULL) | |
b99bd4ef | 16204 | { |
c19d1205 ZW |
16205 | symbol_set_frag (last_label_seen, frag_now); |
16206 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
16207 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
16208 | } |
16209 | ||
c19d1205 ZW |
16210 | memset (&inst, '\0', sizeof (inst)); |
16211 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 16212 | |
c19d1205 ZW |
16213 | opcode = opcode_lookup (&p); |
16214 | if (!opcode) | |
b99bd4ef | 16215 | { |
c19d1205 | 16216 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 16217 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d NC |
16218 | if (! create_register_alias (str, p) |
16219 | && ! create_neon_reg_alias (str, p)) | |
c19d1205 | 16220 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 16221 | |
b99bd4ef NC |
16222 | return; |
16223 | } | |
16224 | ||
278df34e | 16225 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
088fa78e KH |
16226 | as_warn (_("s suffix on comparison instruction is deprecated")); |
16227 | ||
037e8744 JB |
16228 | /* The value which unconditional instructions should have in place of the |
16229 | condition field. */ | |
16230 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
16231 | ||
c19d1205 | 16232 | if (thumb_mode) |
b99bd4ef | 16233 | { |
e74cfd16 | 16234 | arm_feature_set variant; |
8f06b2d8 PB |
16235 | |
16236 | variant = cpu_variant; | |
16237 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
16238 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
16239 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 16240 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
16241 | if (!opcode->tvariant |
16242 | || (thumb_mode == 1 | |
16243 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 16244 | { |
bf3eeda7 | 16245 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
16246 | return; |
16247 | } | |
c19d1205 ZW |
16248 | if (inst.cond != COND_ALWAYS && !unified_syntax |
16249 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 16250 | { |
c19d1205 | 16251 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
16252 | return; |
16253 | } | |
16254 | ||
752d5da4 | 16255 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 16256 | { |
7e806470 | 16257 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
16258 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
16259 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
16260 | { | |
16261 | /* Two things are addressed here. | |
16262 | 1) Implicit require narrow instructions on Thumb-1. | |
16263 | This avoids relaxation accidentally introducing Thumb-2 | |
16264 | instructions. | |
16265 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
16266 | if (inst.size_req == 0) | |
16267 | inst.size_req = 2; | |
16268 | else if (inst.size_req == 4) | |
16269 | { | |
bf3eeda7 | 16270 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
16271 | return; |
16272 | } | |
16273 | } | |
076d447c PB |
16274 | } |
16275 | ||
c19d1205 ZW |
16276 | inst.instruction = opcode->tvalue; |
16277 | ||
5be8be5d | 16278 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
e07e6e58 NC |
16279 | { |
16280 | /* Prepare the it_insn_type for those encodings that don't set | |
16281 | it. */ | |
16282 | it_fsm_pre_encode (); | |
c19d1205 | 16283 | |
e07e6e58 NC |
16284 | opcode->tencode (); |
16285 | ||
16286 | it_fsm_post_encode (); | |
16287 | } | |
e27ec89e | 16288 | |
0110f2b8 | 16289 | if (!(inst.error || inst.relax)) |
b99bd4ef | 16290 | { |
9c2799c2 | 16291 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
16292 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
16293 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 16294 | { |
c19d1205 | 16295 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
16296 | return; |
16297 | } | |
16298 | } | |
076d447c PB |
16299 | |
16300 | /* Something has gone badly wrong if we try to relax a fixed size | |
16301 | instruction. */ | |
9c2799c2 | 16302 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 16303 | |
e74cfd16 PB |
16304 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
16305 | *opcode->tvariant); | |
ee065d83 | 16306 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 16307 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 16308 | anything other than bl/blx and v6-M instructions. |
ee065d83 | 16309 | This is overly pessimistic for relaxable instructions. */ |
7e806470 PB |
16310 | if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) |
16311 | || inst.relax) | |
e07e6e58 NC |
16312 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
16313 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
16314 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
16315 | arm_ext_v6t2); | |
cd000bff | 16316 | |
88714cb8 DG |
16317 | check_neon_suffixes; |
16318 | ||
cd000bff | 16319 | if (!inst.error) |
c877a2f2 NC |
16320 | { |
16321 | mapping_state (MAP_THUMB); | |
16322 | } | |
c19d1205 | 16323 | } |
3e9e4fcf | 16324 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 16325 | { |
845b51d6 PB |
16326 | bfd_boolean is_bx; |
16327 | ||
16328 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
16329 | is_bx = (opcode->aencode == do_bx); | |
16330 | ||
c19d1205 | 16331 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
16332 | if (!(is_bx && fix_v4bx) |
16333 | && !(opcode->avariant && | |
16334 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 16335 | { |
bf3eeda7 | 16336 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 16337 | return; |
b99bd4ef | 16338 | } |
c19d1205 | 16339 | if (inst.size_req) |
b99bd4ef | 16340 | { |
c19d1205 ZW |
16341 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
16342 | return; | |
b99bd4ef NC |
16343 | } |
16344 | ||
c19d1205 ZW |
16345 | inst.instruction = opcode->avalue; |
16346 | if (opcode->tag == OT_unconditionalF) | |
16347 | inst.instruction |= 0xF << 28; | |
16348 | else | |
16349 | inst.instruction |= inst.cond << 28; | |
16350 | inst.size = INSN_SIZE; | |
5be8be5d | 16351 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
e07e6e58 NC |
16352 | { |
16353 | it_fsm_pre_encode (); | |
16354 | opcode->aencode (); | |
16355 | it_fsm_post_encode (); | |
16356 | } | |
ee065d83 PB |
16357 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
16358 | on a hypothetical non-thumb v5 core. */ | |
845b51d6 | 16359 | if (is_bx) |
e74cfd16 | 16360 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 16361 | else |
e74cfd16 PB |
16362 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
16363 | *opcode->avariant); | |
88714cb8 DG |
16364 | |
16365 | check_neon_suffixes; | |
16366 | ||
cd000bff | 16367 | if (!inst.error) |
c877a2f2 NC |
16368 | { |
16369 | mapping_state (MAP_ARM); | |
16370 | } | |
b99bd4ef | 16371 | } |
3e9e4fcf JB |
16372 | else |
16373 | { | |
16374 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
16375 | "-- `%s'"), str); | |
16376 | return; | |
16377 | } | |
c19d1205 ZW |
16378 | output_inst (str); |
16379 | } | |
b99bd4ef | 16380 | |
e07e6e58 NC |
16381 | static void |
16382 | check_it_blocks_finished (void) | |
16383 | { | |
16384 | #ifdef OBJ_ELF | |
16385 | asection *sect; | |
16386 | ||
16387 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
16388 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
16389 | == MANUAL_IT_BLOCK) | |
16390 | { | |
16391 | as_warn (_("section '%s' finished with an open IT block."), | |
16392 | sect->name); | |
16393 | } | |
16394 | #else | |
16395 | if (now_it.state == MANUAL_IT_BLOCK) | |
16396 | as_warn (_("file finished with an open IT block.")); | |
16397 | #endif | |
16398 | } | |
16399 | ||
c19d1205 ZW |
16400 | /* Various frobbings of labels and their addresses. */ |
16401 | ||
16402 | void | |
16403 | arm_start_line_hook (void) | |
16404 | { | |
16405 | last_label_seen = NULL; | |
b99bd4ef NC |
16406 | } |
16407 | ||
c19d1205 ZW |
16408 | void |
16409 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 16410 | { |
c19d1205 | 16411 | last_label_seen = sym; |
b99bd4ef | 16412 | |
c19d1205 | 16413 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 16414 | |
c19d1205 ZW |
16415 | #if defined OBJ_COFF || defined OBJ_ELF |
16416 | ARM_SET_INTERWORK (sym, support_interwork); | |
16417 | #endif | |
b99bd4ef | 16418 | |
e07e6e58 NC |
16419 | force_automatic_it_block_close (); |
16420 | ||
5f4273c7 | 16421 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
16422 | as Thumb functions. This is because these labels, whilst |
16423 | they exist inside Thumb code, are not the entry points for | |
16424 | possible ARM->Thumb calls. Also, these labels can be used | |
16425 | as part of a computed goto or switch statement. eg gcc | |
16426 | can generate code that looks like this: | |
b99bd4ef | 16427 | |
c19d1205 ZW |
16428 | ldr r2, [pc, .Laaa] |
16429 | lsl r3, r3, #2 | |
16430 | ldr r2, [r3, r2] | |
16431 | mov pc, r2 | |
b99bd4ef | 16432 | |
c19d1205 ZW |
16433 | .Lbbb: .word .Lxxx |
16434 | .Lccc: .word .Lyyy | |
16435 | ..etc... | |
16436 | .Laaa: .word Lbbb | |
b99bd4ef | 16437 | |
c19d1205 ZW |
16438 | The first instruction loads the address of the jump table. |
16439 | The second instruction converts a table index into a byte offset. | |
16440 | The third instruction gets the jump address out of the table. | |
16441 | The fourth instruction performs the jump. | |
b99bd4ef | 16442 | |
c19d1205 ZW |
16443 | If the address stored at .Laaa is that of a symbol which has the |
16444 | Thumb_Func bit set, then the linker will arrange for this address | |
16445 | to have the bottom bit set, which in turn would mean that the | |
16446 | address computation performed by the third instruction would end | |
16447 | up with the bottom bit set. Since the ARM is capable of unaligned | |
16448 | word loads, the instruction would then load the incorrect address | |
16449 | out of the jump table, and chaos would ensue. */ | |
16450 | if (label_is_thumb_function_name | |
16451 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
16452 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 16453 | { |
c19d1205 ZW |
16454 | /* When the address of a Thumb function is taken the bottom |
16455 | bit of that address should be set. This will allow | |
16456 | interworking between Arm and Thumb functions to work | |
16457 | correctly. */ | |
b99bd4ef | 16458 | |
c19d1205 | 16459 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 16460 | |
c19d1205 | 16461 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 16462 | } |
07a53e5c | 16463 | |
07a53e5c | 16464 | dwarf2_emit_label (sym); |
b99bd4ef NC |
16465 | } |
16466 | ||
c921be7d | 16467 | bfd_boolean |
c19d1205 | 16468 | arm_data_in_code (void) |
b99bd4ef | 16469 | { |
c19d1205 | 16470 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 16471 | { |
c19d1205 ZW |
16472 | *input_line_pointer = '/'; |
16473 | input_line_pointer += 5; | |
16474 | *input_line_pointer = 0; | |
c921be7d | 16475 | return TRUE; |
b99bd4ef NC |
16476 | } |
16477 | ||
c921be7d | 16478 | return FALSE; |
b99bd4ef NC |
16479 | } |
16480 | ||
c19d1205 ZW |
16481 | char * |
16482 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 16483 | { |
c19d1205 | 16484 | int len; |
b99bd4ef | 16485 | |
c19d1205 ZW |
16486 | if (thumb_mode && (len = strlen (name)) > 5 |
16487 | && streq (name + len - 5, "/data")) | |
16488 | *(name + len - 5) = 0; | |
b99bd4ef | 16489 | |
c19d1205 | 16490 | return name; |
b99bd4ef | 16491 | } |
c19d1205 ZW |
16492 | \f |
16493 | /* Table of all register names defined by default. The user can | |
16494 | define additional names with .req. Note that all register names | |
16495 | should appear in both upper and lowercase variants. Some registers | |
16496 | also have mixed-case names. */ | |
b99bd4ef | 16497 | |
dcbf9037 | 16498 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 16499 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 16500 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
16501 | #define REGSET(p,t) \ |
16502 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
16503 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
16504 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
16505 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
16506 | #define REGSETH(p,t) \ |
16507 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
16508 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
16509 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
16510 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
16511 | #define REGSET2(p,t) \ | |
16512 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
16513 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
16514 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
16515 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
16516 | #define SPLRBANK(base,bank,t) \ |
16517 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
16518 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
16519 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
16520 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
16521 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
16522 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 16523 | |
c19d1205 | 16524 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 16525 | { |
c19d1205 ZW |
16526 | /* ARM integer registers. */ |
16527 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 16528 | |
c19d1205 ZW |
16529 | /* ATPCS synonyms. */ |
16530 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
16531 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
16532 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 16533 | |
c19d1205 ZW |
16534 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
16535 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
16536 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 16537 | |
c19d1205 ZW |
16538 | /* Well-known aliases. */ |
16539 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
16540 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
16541 | ||
16542 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
16543 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
16544 | ||
16545 | /* Coprocessor numbers. */ | |
16546 | REGSET(p, CP), REGSET(P, CP), | |
16547 | ||
16548 | /* Coprocessor register numbers. The "cr" variants are for backward | |
16549 | compatibility. */ | |
16550 | REGSET(c, CN), REGSET(C, CN), | |
16551 | REGSET(cr, CN), REGSET(CR, CN), | |
16552 | ||
90ec0d68 MGD |
16553 | /* ARM banked registers. */ |
16554 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
16555 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
16556 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
16557 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
16558 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
16559 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
16560 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
16561 | ||
16562 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
16563 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
16564 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
16565 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
16566 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
16567 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB), | |
16568 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), | |
16569 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
16570 | ||
16571 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
16572 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
16573 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
16574 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
16575 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
16576 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
16577 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
16578 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), | |
16579 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), | |
16580 | ||
c19d1205 ZW |
16581 | /* FPA registers. */ |
16582 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
16583 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
16584 | ||
16585 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
16586 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
16587 | ||
16588 | /* VFP SP registers. */ | |
5287ad62 JB |
16589 | REGSET(s,VFS), REGSET(S,VFS), |
16590 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
16591 | |
16592 | /* VFP DP Registers. */ | |
5287ad62 JB |
16593 | REGSET(d,VFD), REGSET(D,VFD), |
16594 | /* Extra Neon DP registers. */ | |
16595 | REGSETH(d,VFD), REGSETH(D,VFD), | |
16596 | ||
16597 | /* Neon QP registers. */ | |
16598 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
16599 | |
16600 | /* VFP control registers. */ | |
16601 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
16602 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
16603 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
16604 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
16605 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
16606 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
16607 | |
16608 | /* Maverick DSP coprocessor registers. */ | |
16609 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
16610 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
16611 | ||
16612 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
16613 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
16614 | REGDEF(dspsc,0,DSPSC), | |
16615 | ||
16616 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
16617 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
16618 | REGDEF(DSPSC,0,DSPSC), | |
16619 | ||
16620 | /* iWMMXt data registers - p0, c0-15. */ | |
16621 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
16622 | ||
16623 | /* iWMMXt control registers - p1, c0-3. */ | |
16624 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
16625 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
16626 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
16627 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
16628 | ||
16629 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
16630 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
16631 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
16632 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
16633 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
16634 | ||
16635 | /* XScale accumulator registers. */ | |
16636 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
16637 | }; | |
16638 | #undef REGDEF | |
16639 | #undef REGNUM | |
16640 | #undef REGSET | |
7ed4c4c5 | 16641 | |
c19d1205 ZW |
16642 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
16643 | within psr_required_here. */ | |
16644 | static const struct asm_psr psrs[] = | |
16645 | { | |
16646 | /* Backward compatibility notation. Note that "all" is no longer | |
16647 | truly all possible PSR bits. */ | |
16648 | {"all", PSR_c | PSR_f}, | |
16649 | {"flg", PSR_f}, | |
16650 | {"ctl", PSR_c}, | |
16651 | ||
16652 | /* Individual flags. */ | |
16653 | {"f", PSR_f}, | |
16654 | {"c", PSR_c}, | |
16655 | {"x", PSR_x}, | |
16656 | {"s", PSR_s}, | |
59b42a0d | 16657 | |
c19d1205 ZW |
16658 | /* Combinations of flags. */ |
16659 | {"fs", PSR_f | PSR_s}, | |
16660 | {"fx", PSR_f | PSR_x}, | |
16661 | {"fc", PSR_f | PSR_c}, | |
16662 | {"sf", PSR_s | PSR_f}, | |
16663 | {"sx", PSR_s | PSR_x}, | |
16664 | {"sc", PSR_s | PSR_c}, | |
16665 | {"xf", PSR_x | PSR_f}, | |
16666 | {"xs", PSR_x | PSR_s}, | |
16667 | {"xc", PSR_x | PSR_c}, | |
16668 | {"cf", PSR_c | PSR_f}, | |
16669 | {"cs", PSR_c | PSR_s}, | |
16670 | {"cx", PSR_c | PSR_x}, | |
16671 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
16672 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
16673 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
16674 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
16675 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
16676 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
16677 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
16678 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
16679 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
16680 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
16681 | {"scf", PSR_s | PSR_c | PSR_f}, | |
16682 | {"scx", PSR_s | PSR_c | PSR_x}, | |
16683 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
16684 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
16685 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
16686 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
16687 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
16688 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
16689 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
16690 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
16691 | {"csf", PSR_c | PSR_s | PSR_f}, | |
16692 | {"csx", PSR_c | PSR_s | PSR_x}, | |
16693 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
16694 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
16695 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
16696 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
16697 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
16698 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
16699 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
16700 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
16701 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
16702 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
16703 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
16704 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
16705 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
16706 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
16707 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
16708 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
16709 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
16710 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
16711 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
16712 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
16713 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
16714 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
16715 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
16716 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
16717 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
16718 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
16719 | }; | |
16720 | ||
62b3e311 PB |
16721 | /* Table of V7M psr names. */ |
16722 | static const struct asm_psr v7m_psrs[] = | |
16723 | { | |
2b744c99 PB |
16724 | {"apsr", 0 }, {"APSR", 0 }, |
16725 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
16726 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
16727 | {"psr", 3 }, {"PSR", 3 }, | |
16728 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
16729 | {"ipsr", 5 }, {"IPSR", 5 }, | |
16730 | {"epsr", 6 }, {"EPSR", 6 }, | |
16731 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
16732 | {"msp", 8 }, {"MSP", 8 }, | |
16733 | {"psp", 9 }, {"PSP", 9 }, | |
16734 | {"primask", 16}, {"PRIMASK", 16}, | |
16735 | {"basepri", 17}, {"BASEPRI", 17}, | |
00bbc0bd NC |
16736 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, |
16737 | {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */ | |
2b744c99 PB |
16738 | {"faultmask", 19}, {"FAULTMASK", 19}, |
16739 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
16740 | }; |
16741 | ||
c19d1205 ZW |
16742 | /* Table of all shift-in-operand names. */ |
16743 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 16744 | { |
c19d1205 ZW |
16745 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
16746 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
16747 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
16748 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
16749 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
16750 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
16751 | }; | |
b99bd4ef | 16752 | |
c19d1205 ZW |
16753 | /* Table of all explicit relocation names. */ |
16754 | #ifdef OBJ_ELF | |
16755 | static struct reloc_entry reloc_names[] = | |
16756 | { | |
16757 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
16758 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
16759 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
16760 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
16761 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
16762 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
16763 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
16764 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
16765 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
16766 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 16767 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
16768 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
16769 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
16770 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, | |
16771 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, | |
16772 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, | |
16773 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, | |
16774 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ} | |
c19d1205 ZW |
16775 | }; |
16776 | #endif | |
b99bd4ef | 16777 | |
c19d1205 ZW |
16778 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
16779 | static const struct asm_cond conds[] = | |
16780 | { | |
16781 | {"eq", 0x0}, | |
16782 | {"ne", 0x1}, | |
16783 | {"cs", 0x2}, {"hs", 0x2}, | |
16784 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
16785 | {"mi", 0x4}, | |
16786 | {"pl", 0x5}, | |
16787 | {"vs", 0x6}, | |
16788 | {"vc", 0x7}, | |
16789 | {"hi", 0x8}, | |
16790 | {"ls", 0x9}, | |
16791 | {"ge", 0xa}, | |
16792 | {"lt", 0xb}, | |
16793 | {"gt", 0xc}, | |
16794 | {"le", 0xd}, | |
16795 | {"al", 0xe} | |
16796 | }; | |
bfae80f2 | 16797 | |
62b3e311 PB |
16798 | static struct asm_barrier_opt barrier_opt_names[] = |
16799 | { | |
52e7f43d RE |
16800 | { "sy", 0xf }, { "SY", 0xf }, |
16801 | { "un", 0x7 }, { "UN", 0x7 }, | |
16802 | { "st", 0xe }, { "ST", 0xe }, | |
16803 | { "unst", 0x6 }, { "UNST", 0x6 }, | |
16804 | { "ish", 0xb }, { "ISH", 0xb }, | |
16805 | { "sh", 0xb }, { "SH", 0xb }, | |
16806 | { "ishst", 0xa }, { "ISHST", 0xa }, | |
16807 | { "shst", 0xa }, { "SHST", 0xa }, | |
16808 | { "nsh", 0x7 }, { "NSH", 0x7 }, | |
16809 | { "nshst", 0x6 }, { "NSHST", 0x6 }, | |
16810 | { "osh", 0x3 }, { "OSH", 0x3 }, | |
16811 | { "oshst", 0x2 }, { "OSHST", 0x2 } | |
62b3e311 PB |
16812 | }; |
16813 | ||
c19d1205 ZW |
16814 | /* Table of ARM-format instructions. */ |
16815 | ||
16816 | /* Macros for gluing together operand strings. N.B. In all cases | |
16817 | other than OPS0, the trailing OP_stop comes from default | |
16818 | zero-initialization of the unspecified elements of the array. */ | |
16819 | #define OPS0() { OP_stop, } | |
16820 | #define OPS1(a) { OP_##a, } | |
16821 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
16822 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
16823 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
16824 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
16825 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
16826 | ||
5be8be5d DG |
16827 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
16828 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
16829 | MIX_ARM_THUMB_OPERANDS macro. | |
16830 | In order to use these macros, prefix the number of operands with _ | |
16831 | e.g. _3. */ | |
16832 | #define OPS_1(a) { a, } | |
16833 | #define OPS_2(a,b) { a,b, } | |
16834 | #define OPS_3(a,b,c) { a,b,c, } | |
16835 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
16836 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
16837 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
16838 | ||
c19d1205 ZW |
16839 | /* These macros abstract out the exact format of the mnemonic table and |
16840 | save some repeated characters. */ | |
16841 | ||
16842 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
16843 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16844 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16845 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16846 | |
16847 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
16848 | a T_MNEM_xyz enumerator. */ | |
16849 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 16850 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16851 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16852 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16853 | |
16854 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
16855 | infix after the third character. */ | |
16856 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16857 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16858 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 16859 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16860 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 16861 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 16862 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 16863 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 16864 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 16865 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16866 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16867 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 16868 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16869 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16870 | |
16871 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
16872 | appear in the condition table. */ | |
16873 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16874 | { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ |
1887dd22 | 16875 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16876 | |
16877 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
16878 | TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ |
16879 | TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ | |
16880 | TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ | |
16881 | TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ | |
16882 | TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ | |
16883 | TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ | |
16884 | TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ | |
16885 | TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ | |
16886 | TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ | |
16887 | TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ | |
16888 | TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ | |
16889 | TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ | |
16890 | TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ | |
16891 | TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ | |
16892 | TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ | |
16893 | TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ | |
16894 | TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ | |
16895 | TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ | |
16896 | TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) | |
c19d1205 ZW |
16897 | |
16898 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
16899 | TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) |
16900 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
21d799b5 | 16901 | TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16902 | |
16903 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
16904 | field is still 0xE. Many of the Thumb variants can be executed |
16905 | conditionally, so this is checked separately. */ | |
c19d1205 | 16906 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16907 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 16908 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16909 | |
16910 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
16911 | condition code field. */ | |
16912 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16913 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 16914 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16915 | |
16916 | /* ARM-only variants of all the above. */ | |
6a86118a | 16917 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 16918 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
16919 | |
16920 | #define C3(mnem, op, nops, ops, ae) \ | |
16921 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
16922 | ||
e3cb604e PB |
16923 | /* Legacy mnemonics that always have conditional infix after the third |
16924 | character. */ | |
16925 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16926 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
16927 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
16928 | ||
8f06b2d8 PB |
16929 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
16930 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16931 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 16932 | |
e3cb604e PB |
16933 | /* Legacy coprocessor instructions where conditional infix and conditional |
16934 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
16935 | not just the potentially ambiguous ones. */ | |
16936 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16937 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
16938 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
16939 | ||
16940 | /* Coprocessor, takes either a suffix or a position-3 infix | |
16941 | (for an FPA corner case). */ | |
16942 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 16943 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 16944 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 16945 | |
6a86118a | 16946 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
16947 | { m1 #m2 m3, OPS##nops ops, \ |
16948 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
16949 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
16950 | ||
16951 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
16952 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
16953 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
16954 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
16955 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
16956 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
16957 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
16958 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
16959 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
16960 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
16961 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
16962 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
16963 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
16964 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
16965 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
16966 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
16967 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
16968 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
16969 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
16970 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
16971 | |
16972 | #define UE(mnem, op, nops, ops, ae) \ | |
16973 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
16974 | ||
16975 | #define UF(mnem, op, nops, ops, ae) \ | |
16976 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
16977 | ||
5287ad62 JB |
16978 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
16979 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
16980 | use the same encoding function for each. */ | |
16981 | #define NUF(mnem, op, nops, ops, enc) \ | |
16982 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
16983 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
16984 | ||
16985 | /* Neon data processing, version which indirects through neon_enc_tab for | |
16986 | the various overloaded versions of opcodes. */ | |
16987 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 16988 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
16989 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
16990 | ||
16991 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
16992 | version. */ | |
037e8744 JB |
16993 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
16994 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
16995 | THUMB_VARIANT, do_##enc, do_##enc } |
16996 | ||
037e8744 | 16997 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 16998 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
16999 | |
17000 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 17001 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 17002 | |
5287ad62 | 17003 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 17004 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 17005 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
17006 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
17007 | ||
037e8744 | 17008 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 17009 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
17010 | |
17011 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 17012 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 17013 | |
c19d1205 ZW |
17014 | #define do_0 0 |
17015 | ||
c19d1205 | 17016 | static const struct asm_opcode insns[] = |
bfae80f2 | 17017 | { |
e74cfd16 PB |
17018 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
17019 | #define THUMB_VARIANT &arm_ext_v4t | |
21d799b5 NC |
17020 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
17021 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
17022 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
17023 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
17024 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
17025 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
17026 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
17027 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
17028 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
17029 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
17030 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
17031 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
17032 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
17033 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
17034 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
17035 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
17036 | |
17037 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
17038 | for setting PSR flag bits. They are obsolete in V6 and do not | |
17039 | have Thumb equivalents. */ | |
21d799b5 NC |
17040 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
17041 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
17042 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
17043 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
17044 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
17045 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
17046 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
17047 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
17048 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
17049 | ||
17050 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
17051 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
17052 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
17053 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
17054 | ||
17055 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
17056 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
17057 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
17058 | OP_RRnpc), | |
17059 | OP_ADDRGLDR),ldst, t_ldst), | |
17060 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
17061 | |
17062 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17063 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17064 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17065 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17066 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17067 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17068 | ||
17069 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
17070 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
17071 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
17072 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 17073 | |
c19d1205 | 17074 | /* Pseudo ops. */ |
21d799b5 | 17075 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 17076 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 17077 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
c19d1205 ZW |
17078 | |
17079 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
17080 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
17081 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
17082 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
17083 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
17084 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
17085 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
17086 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
17087 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
17088 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
17089 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
17090 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
17091 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 17092 | |
16a4cf17 | 17093 | /* These may simplify to neg. */ |
21d799b5 NC |
17094 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
17095 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 17096 | |
c921be7d NC |
17097 | #undef THUMB_VARIANT |
17098 | #define THUMB_VARIANT & arm_ext_v6 | |
17099 | ||
21d799b5 | 17100 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
17101 | |
17102 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
17103 | #undef THUMB_VARIANT |
17104 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17105 | ||
21d799b5 NC |
17106 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
17107 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
17108 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 17109 | |
5be8be5d DG |
17110 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
17111 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
17112 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
17113 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 17114 | |
21d799b5 NC |
17115 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
17116 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 17117 | |
21d799b5 NC |
17118 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
17119 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
17120 | |
17121 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 17122 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
17123 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
17124 | ||
17125 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
17126 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
17127 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
17128 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
17129 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
17130 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
17131 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
17132 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
17133 | ||
c921be7d NC |
17134 | #undef ARM_VARIANT |
17135 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
17136 | #undef THUMB_VARIANT | |
17137 | #define THUMB_VARIANT & arm_ext_v4t | |
17138 | ||
21d799b5 NC |
17139 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
17140 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 17141 | |
c921be7d NC |
17142 | #undef THUMB_VARIANT |
17143 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17144 | ||
21d799b5 | 17145 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
17146 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
17147 | ||
17148 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
17149 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
17150 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17151 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17152 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17153 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17154 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 17155 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 17156 | |
c921be7d NC |
17157 | #undef ARM_VARIANT |
17158 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
17159 | ||
21d799b5 | 17160 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
17161 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
17162 | ||
c921be7d NC |
17163 | #undef ARM_VARIANT |
17164 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
17165 | #undef THUMB_VARIANT | |
17166 | #define THUMB_VARIANT & arm_ext_msr | |
17167 | ||
d2cd1205 JB |
17168 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
17169 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 17170 | |
c921be7d NC |
17171 | #undef ARM_VARIANT |
17172 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
17173 | #undef THUMB_VARIANT | |
17174 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17175 | ||
21d799b5 NC |
17176 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
17177 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17178 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17179 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17180 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17181 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17182 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17183 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 17184 | |
c921be7d NC |
17185 | #undef ARM_VARIANT |
17186 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
17187 | #undef THUMB_VARIANT | |
17188 | #define THUMB_VARIANT & arm_ext_v4t | |
17189 | ||
5be8be5d DG |
17190 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
17191 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17192 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17193 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17194 | tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17195 | tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 17196 | |
c921be7d NC |
17197 | #undef ARM_VARIANT |
17198 | #define ARM_VARIANT & arm_ext_v4t_5 | |
17199 | ||
c19d1205 ZW |
17200 | /* ARM Architecture 4T. */ |
17201 | /* Note: bx (and blx) are required on V5, even if the processor does | |
17202 | not support Thumb. */ | |
21d799b5 | 17203 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 17204 | |
c921be7d NC |
17205 | #undef ARM_VARIANT |
17206 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
17207 | #undef THUMB_VARIANT | |
17208 | #define THUMB_VARIANT & arm_ext_v5t | |
17209 | ||
c19d1205 ZW |
17210 | /* Note: blx has 2 variants; the .value coded here is for |
17211 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
17212 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
17213 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 17214 | |
c921be7d NC |
17215 | #undef THUMB_VARIANT |
17216 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17217 | ||
21d799b5 NC |
17218 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
17219 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17220 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17221 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17222 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17223 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
17224 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
17225 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 17226 | |
c921be7d NC |
17227 | #undef ARM_VARIANT |
17228 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ | |
9e3c6df6 PB |
17229 | #undef THUMB_VARIANT |
17230 | #define THUMB_VARIANT &arm_ext_v5exp | |
c921be7d | 17231 | |
21d799b5 NC |
17232 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
17233 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
17234 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
17235 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 17236 | |
21d799b5 NC |
17237 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
17238 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 17239 | |
21d799b5 NC |
17240 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
17241 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
17242 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
17243 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 17244 | |
21d799b5 NC |
17245 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
17246 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17247 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17248 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 17249 | |
21d799b5 NC |
17250 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
17251 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 17252 | |
03ee1b7f NC |
17253 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
17254 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
17255 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
17256 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 17257 | |
c921be7d NC |
17258 | #undef ARM_VARIANT |
17259 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ | |
9e3c6df6 PB |
17260 | #undef THUMB_VARIANT |
17261 | #define THUMB_VARIANT &arm_ext_v6t2 | |
c921be7d | 17262 | |
21d799b5 | 17263 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
17264 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
17265 | ldrd, t_ldstd), | |
17266 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
17267 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 17268 | |
21d799b5 NC |
17269 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
17270 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 17271 | |
c921be7d NC |
17272 | #undef ARM_VARIANT |
17273 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
17274 | ||
21d799b5 | 17275 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 17276 | |
c921be7d NC |
17277 | #undef ARM_VARIANT |
17278 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
17279 | #undef THUMB_VARIANT | |
17280 | #define THUMB_VARIANT & arm_ext_v6 | |
17281 | ||
21d799b5 NC |
17282 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
17283 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
17284 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17285 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17286 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17287 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17288 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17289 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17290 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17291 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 17292 | |
c921be7d NC |
17293 | #undef THUMB_VARIANT |
17294 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17295 | ||
5be8be5d DG |
17296 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
17297 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
17298 | strex, t_strex), | |
21d799b5 NC |
17299 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
17300 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 17301 | |
21d799b5 NC |
17302 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
17303 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 17304 | |
9e3c6df6 | 17305 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
17306 | #undef THUMB_VARIANT |
17307 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 PB |
17308 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
17309 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
17310 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
17311 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
17312 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
17313 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
17314 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
17315 | TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
17316 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
17317 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), | |
17318 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), | |
17319 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), | |
c921be7d | 17320 | |
9e3c6df6 PB |
17321 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
17322 | #undef THUMB_VARIANT | |
17323 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
17324 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
17325 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
17326 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
17327 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17328 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17329 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17330 | /* Old name for QASX. */ |
21d799b5 NC |
17331 | TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17332 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17333 | /* Old name for QSAX. */ |
21d799b5 NC |
17334 | TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17335 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17336 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17337 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17338 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17339 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17340 | /* Old name for SASX. */ |
21d799b5 NC |
17341 | TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17342 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17343 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17344 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17345 | /* Old name for SHASX. */ |
21d799b5 NC |
17346 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17347 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17348 | /* Old name for SHSAX. */ |
21d799b5 NC |
17349 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17350 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17351 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17352 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17353 | /* Old name for SSAX. */ |
21d799b5 NC |
17354 | TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17355 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17356 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17357 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17358 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17359 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17360 | /* Old name for UASX. */ |
21d799b5 NC |
17361 | TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17362 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17363 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17364 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17365 | /* Old name for UHASX. */ |
21d799b5 NC |
17366 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17367 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17368 | /* Old name for UHSAX. */ |
21d799b5 NC |
17369 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17370 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17371 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17372 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17373 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17374 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17375 | /* Old name for UQASX. */ |
21d799b5 NC |
17376 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17377 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17378 | /* Old name for UQSAX. */ |
21d799b5 NC |
17379 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17380 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17381 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17382 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17383 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17384 | /* Old name for USAX. */ |
21d799b5 NC |
17385 | TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17386 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
21d799b5 NC |
17387 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
17388 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17389 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17390 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17391 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17392 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17393 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17394 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17395 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17396 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17397 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17398 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17399 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17400 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17401 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17402 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17403 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17404 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17405 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17406 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17407 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17408 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17409 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17410 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17411 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17412 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17413 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
17414 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
17415 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
17416 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17417 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17418 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 17419 | |
c921be7d NC |
17420 | #undef ARM_VARIANT |
17421 | #define ARM_VARIANT & arm_ext_v6k | |
17422 | #undef THUMB_VARIANT | |
17423 | #define THUMB_VARIANT & arm_ext_v6k | |
17424 | ||
21d799b5 NC |
17425 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
17426 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
17427 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
17428 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 17429 | |
c921be7d NC |
17430 | #undef THUMB_VARIANT |
17431 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
17432 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
17433 | ldrexd, t_ldrexd), | |
17434 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
17435 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 17436 | |
c921be7d NC |
17437 | #undef THUMB_VARIANT |
17438 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
17439 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
17440 | rd_rn, rd_rn), | |
17441 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
17442 | rd_rn, rd_rn), | |
17443 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
17444 | strex, rm_rd_rn), | |
17445 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
17446 | strex, rm_rd_rn), | |
21d799b5 | 17447 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 17448 | |
c921be7d | 17449 | #undef ARM_VARIANT |
f4c65163 MGD |
17450 | #define ARM_VARIANT & arm_ext_sec |
17451 | #undef THUMB_VARIANT | |
17452 | #define THUMB_VARIANT & arm_ext_sec | |
c921be7d | 17453 | |
21d799b5 | 17454 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 17455 | |
90ec0d68 MGD |
17456 | #undef ARM_VARIANT |
17457 | #define ARM_VARIANT & arm_ext_virt | |
17458 | #undef THUMB_VARIANT | |
17459 | #define THUMB_VARIANT & arm_ext_virt | |
17460 | ||
17461 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
17462 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
17463 | ||
c921be7d NC |
17464 | #undef ARM_VARIANT |
17465 | #define ARM_VARIANT & arm_ext_v6t2 | |
f4c65163 MGD |
17466 | #undef THUMB_VARIANT |
17467 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 17468 | |
21d799b5 NC |
17469 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
17470 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
17471 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
17472 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 17473 | |
21d799b5 NC |
17474 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
17475 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17476 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17477 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 17478 | |
5be8be5d DG |
17479 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
17480 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17481 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17482 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 17483 | |
bf3eeda7 NS |
17484 | /* Thumb-only instructions. */ |
17485 | #undef ARM_VARIANT | |
17486 | #define ARM_VARIANT NULL | |
17487 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
17488 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
17489 | |
17490 | /* ARM does not really have an IT instruction, so always allow it. | |
17491 | The opcode is copied from Thumb in order to allow warnings in | |
17492 | -mimplicit-it=[never | arm] modes. */ | |
17493 | #undef ARM_VARIANT | |
17494 | #define ARM_VARIANT & arm_ext_v1 | |
17495 | ||
21d799b5 NC |
17496 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
17497 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
17498 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
17499 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
17500 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
17501 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
17502 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
17503 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
17504 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
17505 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
17506 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
17507 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
17508 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
17509 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
17510 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 17511 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
17512 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
17513 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 17514 | |
92e90b6e | 17515 | /* Thumb2 only instructions. */ |
c921be7d NC |
17516 | #undef ARM_VARIANT |
17517 | #define ARM_VARIANT NULL | |
92e90b6e | 17518 | |
21d799b5 NC |
17519 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
17520 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
17521 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
17522 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
17523 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
17524 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 17525 | |
eea54501 MGD |
17526 | /* Hardware division instructions. */ |
17527 | #undef ARM_VARIANT | |
17528 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
17529 | #undef THUMB_VARIANT |
17530 | #define THUMB_VARIANT & arm_ext_div | |
17531 | ||
eea54501 MGD |
17532 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
17533 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 17534 | |
7e806470 | 17535 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
17536 | #undef ARM_VARIANT |
17537 | #define ARM_VARIANT & arm_ext_barrier | |
17538 | #undef THUMB_VARIANT | |
17539 | #define THUMB_VARIANT & arm_ext_barrier | |
17540 | ||
52e7f43d RE |
17541 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier), |
17542 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier), | |
17543 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier), | |
7e806470 | 17544 | |
62b3e311 | 17545 | /* ARM V7 instructions. */ |
c921be7d NC |
17546 | #undef ARM_VARIANT |
17547 | #define ARM_VARIANT & arm_ext_v7 | |
17548 | #undef THUMB_VARIANT | |
17549 | #define THUMB_VARIANT & arm_ext_v7 | |
17550 | ||
21d799b5 NC |
17551 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
17552 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 17553 | |
60e5ef9f MGD |
17554 | #undef ARM_VARIANT |
17555 | #define ARM_VARIANT & arm_ext_mp | |
17556 | #undef THUMB_VARIANT | |
17557 | #define THUMB_VARIANT & arm_ext_mp | |
17558 | ||
17559 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
17560 | ||
c921be7d NC |
17561 | #undef ARM_VARIANT |
17562 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
17563 | ||
21d799b5 NC |
17564 | cCE("wfs", e200110, 1, (RR), rd), |
17565 | cCE("rfs", e300110, 1, (RR), rd), | |
17566 | cCE("wfc", e400110, 1, (RR), rd), | |
17567 | cCE("rfc", e500110, 1, (RR), rd), | |
17568 | ||
17569 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17570 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17571 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17572 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17573 | ||
17574 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17575 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17576 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17577 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17578 | ||
17579 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
17580 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
17581 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
17582 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
17583 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
17584 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
17585 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
17586 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
17587 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
17588 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
17589 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
17590 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
17591 | ||
17592 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
17593 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
17594 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
17595 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
17596 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
17597 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
17598 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
17599 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
17600 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
17601 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
17602 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
17603 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
17604 | ||
17605 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
17606 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
17607 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
17608 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
17609 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
17610 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
17611 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
17612 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
17613 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
17614 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
17615 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
17616 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
17617 | ||
17618 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
17619 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
17620 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
17621 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
17622 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
17623 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
17624 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
17625 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
17626 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
17627 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
17628 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
17629 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
17630 | ||
17631 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
17632 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
17633 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
17634 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
17635 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
17636 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
17637 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
17638 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
17639 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
17640 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
17641 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
17642 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
17643 | ||
17644 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
17645 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
17646 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
17647 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
17648 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
17649 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
17650 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
17651 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
17652 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
17653 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
17654 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
17655 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
17656 | ||
17657 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
17658 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
17659 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
17660 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
17661 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
17662 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
17663 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
17664 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
17665 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
17666 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
17667 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
17668 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
17669 | ||
17670 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
17671 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
17672 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
17673 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
17674 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
17675 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
17676 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
17677 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
17678 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
17679 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
17680 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
17681 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
17682 | ||
17683 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
17684 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
17685 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
17686 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
17687 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
17688 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
17689 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
17690 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
17691 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
17692 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
17693 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
17694 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
17695 | ||
17696 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
17697 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
17698 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
17699 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
17700 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
17701 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
17702 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
17703 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
17704 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
17705 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
17706 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
17707 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
17708 | ||
17709 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
17710 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
17711 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
17712 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
17713 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
17714 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
17715 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
17716 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
17717 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
17718 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
17719 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
17720 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
17721 | ||
17722 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
17723 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
17724 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
17725 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
17726 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
17727 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
17728 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
17729 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
17730 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
17731 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
17732 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
17733 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
17734 | ||
17735 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
17736 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
17737 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
17738 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
17739 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
17740 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
17741 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
17742 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
17743 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
17744 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
17745 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
17746 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
17747 | ||
17748 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
17749 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
17750 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
17751 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
17752 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
17753 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
17754 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
17755 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
17756 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
17757 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
17758 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
17759 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
17760 | ||
17761 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
17762 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
17763 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
17764 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
17765 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
17766 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
17767 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
17768 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
17769 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
17770 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
17771 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
17772 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
17773 | ||
17774 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
17775 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
17776 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
17777 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
17778 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
17779 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
17780 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
17781 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
17782 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
17783 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
17784 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
17785 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
17786 | ||
17787 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17788 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17789 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17790 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17791 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17792 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17793 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17794 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17795 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17796 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17797 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17798 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17799 | ||
17800 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17801 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17802 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17803 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17804 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17805 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17806 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17807 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17808 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17809 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17810 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17811 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17812 | ||
17813 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17814 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17815 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17816 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17817 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17818 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17819 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17820 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17821 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17822 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17823 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17824 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17825 | ||
17826 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17827 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17828 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17829 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17830 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17831 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17832 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17833 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17834 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17835 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17836 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17837 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17838 | ||
17839 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17840 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17841 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17842 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17843 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17844 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17845 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17846 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17847 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17848 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17849 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17850 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17851 | ||
17852 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17853 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17854 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17855 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17856 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17857 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17858 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17859 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17860 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17861 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17862 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17863 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17864 | ||
17865 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17866 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17867 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17868 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17869 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17870 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17871 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17872 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17873 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17874 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17875 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17876 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17877 | ||
17878 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17879 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17880 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17881 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17882 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17883 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17884 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17885 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17886 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17887 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17888 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17889 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17890 | ||
17891 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17892 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17893 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17894 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17895 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17896 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17897 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17898 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17899 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17900 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17901 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17902 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17903 | ||
17904 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17905 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17906 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17907 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17908 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17909 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17910 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17911 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17912 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17913 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17914 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17915 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17916 | ||
17917 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17918 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17919 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17920 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17921 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17922 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17923 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17924 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17925 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17926 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17927 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17928 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17929 | ||
17930 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17931 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17932 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17933 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17934 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17935 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17936 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17937 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17938 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17939 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17940 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17941 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17942 | ||
17943 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17944 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17945 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17946 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17947 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17948 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17949 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17950 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17951 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17952 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17953 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17954 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17955 | ||
17956 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
17957 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
17958 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
17959 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
17960 | ||
17961 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
17962 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
17963 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
17964 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
17965 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
17966 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
17967 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
17968 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
17969 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
17970 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
17971 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
17972 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 17973 | |
c19d1205 ZW |
17974 | /* The implementation of the FIX instruction is broken on some |
17975 | assemblers, in that it accepts a precision specifier as well as a | |
17976 | rounding specifier, despite the fact that this is meaningless. | |
17977 | To be more compatible, we accept it as well, though of course it | |
17978 | does not set any bits. */ | |
21d799b5 NC |
17979 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
17980 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
17981 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
17982 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
17983 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
17984 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
17985 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
17986 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
17987 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
17988 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
17989 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
17990 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
17991 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 17992 | |
c19d1205 | 17993 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
17994 | #undef ARM_VARIANT |
17995 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
17996 | ||
21d799b5 NC |
17997 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
17998 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
17999 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18000 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18001 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18002 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 18003 | |
c921be7d NC |
18004 | #undef ARM_VARIANT |
18005 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
18006 | ||
c19d1205 | 18007 | /* Moves and type conversions. */ |
21d799b5 NC |
18008 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
18009 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
18010 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
18011 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
f7c21dc7 NC |
18012 | cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs), |
18013 | cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
18014 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
18015 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18016 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18017 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18018 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18019 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18020 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
18021 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
18022 | |
18023 | /* Memory operations. */ | |
21d799b5 NC |
18024 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
18025 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
18026 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
18027 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18028 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18029 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18030 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18031 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18032 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18033 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18034 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18035 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18036 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18037 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18038 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18039 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18040 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18041 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 18042 | |
c19d1205 | 18043 | /* Monadic operations. */ |
21d799b5 NC |
18044 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
18045 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18046 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
18047 | |
18048 | /* Dyadic operations. */ | |
21d799b5 NC |
18049 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
18050 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18051 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18052 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18053 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18054 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18055 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18056 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18057 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 18058 | |
c19d1205 | 18059 | /* Comparisons. */ |
21d799b5 NC |
18060 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
18061 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
18062 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18063 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 18064 | |
62f3b8c8 PB |
18065 | /* Double precision load/store are still present on single precision |
18066 | implementations. */ | |
18067 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
18068 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
18069 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
18070 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18071 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18072 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18073 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18074 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18075 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18076 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 18077 | |
c921be7d NC |
18078 | #undef ARM_VARIANT |
18079 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
18080 | ||
c19d1205 | 18081 | /* Moves and type conversions. */ |
21d799b5 NC |
18082 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
18083 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18084 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18085 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
18086 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
18087 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
18088 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
18089 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18090 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18091 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18092 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18093 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18094 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 18095 | |
c19d1205 | 18096 | /* Monadic operations. */ |
21d799b5 NC |
18097 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
18098 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
18099 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
18100 | |
18101 | /* Dyadic operations. */ | |
21d799b5 NC |
18102 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
18103 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18104 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18105 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18106 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18107 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18108 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18109 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18110 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 18111 | |
c19d1205 | 18112 | /* Comparisons. */ |
21d799b5 NC |
18113 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
18114 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
18115 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
18116 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 18117 | |
c921be7d NC |
18118 | #undef ARM_VARIANT |
18119 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
18120 | ||
21d799b5 NC |
18121 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
18122 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
18123 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
18124 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 18125 | |
037e8744 JB |
18126 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
18127 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
18128 | #undef ARM_VARIANT |
18129 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
18130 | #undef THUMB_VARIANT | |
18131 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
18132 | ||
037e8744 JB |
18133 | /* These mnemonics are unique to VFP. */ |
18134 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
18135 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
18136 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
18137 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18138 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18139 | nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
18140 | nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
037e8744 JB |
18141 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
18142 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
18143 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
18144 | ||
18145 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
18146 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
18147 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
18148 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 18149 | |
21d799b5 NC |
18150 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
18151 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
18152 | |
18153 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
18154 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
18155 | ||
55881a11 MGD |
18156 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
18157 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18158 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18159 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18160 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18161 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
18162 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
18163 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 18164 | |
e3e535bc NC |
18165 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), |
18166 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), | |
21d799b5 NC |
18167 | nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb), |
18168 | nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt), | |
f31fef98 | 18169 | |
037e8744 JB |
18170 | |
18171 | /* NOTE: All VMOV encoding is special-cased! */ | |
18172 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
18173 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
18174 | ||
c921be7d NC |
18175 | #undef THUMB_VARIANT |
18176 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
18177 | #undef ARM_VARIANT | |
18178 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
18179 | ||
5287ad62 JB |
18180 | /* Data processing with three registers of the same length. */ |
18181 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
18182 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
18183 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
18184 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18185 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18186 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18187 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18188 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18189 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18190 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18191 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
18192 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
18193 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
18194 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
18195 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
18196 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
18197 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
18198 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
18199 | /* If not immediate, fall back to neon_dyadic_i64_su. |
18200 | shl_imm should accept I8 I16 I32 I64, | |
18201 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
18202 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
18203 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
18204 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
18205 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 18206 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
18207 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
18208 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18209 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18210 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18211 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18212 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18213 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18214 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18215 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
18216 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
18217 | /* Bitfield ops, untyped. */ |
18218 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18219 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18220 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18221 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18222 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18223 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18224 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
18225 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
18226 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
18227 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
18228 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
18229 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
18230 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
18231 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
18232 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
18233 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
18234 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
18235 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
18236 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
18237 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
18238 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
18239 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
18240 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 18241 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
18242 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
18243 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 18244 | /* As above, D registers only. */ |
21d799b5 NC |
18245 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
18246 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 18247 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
18248 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
18249 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
18250 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 18251 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
18252 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
18253 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
18254 | /* vtst takes sizes 8, 16, 32. */ |
18255 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
18256 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
18257 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 18258 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 18259 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
18260 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
18261 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
18262 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
18263 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
18264 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
18265 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
18266 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
18267 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
18268 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
18269 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
18270 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
18271 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
18272 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
18273 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
18274 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
18275 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
18276 | ||
18277 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 18278 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
18279 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
18280 | ||
18281 | /* Data processing with two registers and a shift amount. */ | |
18282 | /* Right shifts, and variants with rounding. | |
18283 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18284 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
18285 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
18286 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
18287 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
18288 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
18289 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
18290 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
18291 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
18292 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
18293 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
18294 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
18295 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
18296 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
18297 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18298 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
18299 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
18300 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
18301 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
18302 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
18303 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
18304 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
18305 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
18306 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
18307 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
18308 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
18309 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
18310 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 18311 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 18312 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 18313 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 18314 | |
4316f0d2 DG |
18315 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
18316 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
18317 | |
18318 | /* Data processing, three registers of different lengths. */ | |
18319 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
18320 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
18321 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18322 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18323 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18324 | /* If not scalar, fall back to neon_dyadic_long. | |
18325 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
18326 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
18327 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
18328 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
18329 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
18330 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
18331 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
18332 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18333 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18334 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18335 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18336 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
18337 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
18338 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
18339 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
18340 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
18341 | S16 S32 U16 U32. */ | |
21d799b5 | 18342 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
18343 | |
18344 | /* Extract. Size 8. */ | |
3b8d421e PB |
18345 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
18346 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
18347 | |
18348 | /* Two registers, miscellaneous. */ | |
18349 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
18350 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
18351 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
18352 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
18353 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
18354 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
18355 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
18356 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
18357 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
18358 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
18359 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
18360 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
18361 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 18362 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 18363 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 18364 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 18365 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 18366 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
18367 | /* VZIP / VUZP. Sizes 8 16 32. */ |
18368 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
18369 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
18370 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
18371 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
18372 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
18373 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
18374 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
18375 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
18376 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
18377 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
18378 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
18379 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
18380 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
18381 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
18382 | /* Reciprocal estimates. Types U32 F32. */ | |
18383 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
18384 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
18385 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
18386 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
18387 | /* VCLS. Types S8 S16 S32. */ | |
18388 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
18389 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
18390 | /* VCLZ. Types I8 I16 I32. */ | |
18391 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
18392 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
18393 | /* VCNT. Size 8. */ | |
18394 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
18395 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
18396 | /* Two address, untyped. */ | |
18397 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
18398 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
18399 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
18400 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
18401 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
18402 | |
18403 | /* Table lookup. Size 8. */ | |
18404 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
18405 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
18406 | ||
c921be7d NC |
18407 | #undef THUMB_VARIANT |
18408 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
18409 | #undef ARM_VARIANT | |
18410 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
18411 | ||
5287ad62 | 18412 | /* Neon element/structure load/store. */ |
21d799b5 NC |
18413 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
18414 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18415 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18416 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18417 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18418 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18419 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18420 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 18421 | |
c921be7d | 18422 | #undef THUMB_VARIANT |
62f3b8c8 PB |
18423 | #define THUMB_VARIANT &fpu_vfp_ext_v3xd |
18424 | #undef ARM_VARIANT | |
18425 | #define ARM_VARIANT &fpu_vfp_ext_v3xd | |
18426 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), | |
18427 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18428 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18429 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18430 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18431 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18432 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18433 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18434 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18435 | ||
18436 | #undef THUMB_VARIANT | |
c921be7d NC |
18437 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
18438 | #undef ARM_VARIANT | |
18439 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
18440 | ||
21d799b5 | 18441 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 18442 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18443 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18444 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18445 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18446 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18447 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18448 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18449 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 18450 | |
62f3b8c8 PB |
18451 | #undef ARM_VARIANT |
18452 | #define ARM_VARIANT &fpu_vfp_ext_fma | |
18453 | #undef THUMB_VARIANT | |
18454 | #define THUMB_VARIANT &fpu_vfp_ext_fma | |
18455 | /* Mnemonics shared by Neon and VFP. These are included in the | |
18456 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
18457 | FMA instructions. */ | |
18458 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
18459 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
18460 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
18461 | the v form should always be used. */ | |
18462 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18463 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18464 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18465 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18466 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18467 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18468 | ||
5287ad62 | 18469 | #undef THUMB_VARIANT |
c921be7d NC |
18470 | #undef ARM_VARIANT |
18471 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
18472 | ||
21d799b5 NC |
18473 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
18474 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18475 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18476 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18477 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18478 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18479 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
18480 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 18481 | |
c921be7d NC |
18482 | #undef ARM_VARIANT |
18483 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
18484 | ||
21d799b5 NC |
18485 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
18486 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
18487 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
18488 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
18489 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
18490 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
18491 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
18492 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
18493 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
18494 | cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18495 | cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18496 | cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18497 | cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18498 | cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18499 | cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18500 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18501 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18502 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18503 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
18504 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
18505 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18506 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18507 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18508 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18509 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18510 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18511 | cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn), | |
18512 | cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn), | |
18513 | cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn), | |
18514 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), | |
18515 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
18516 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
18517 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
18518 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
18519 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
18520 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
18521 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
18522 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18523 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18524 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18525 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18526 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18527 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18528 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18529 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18530 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18531 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
18532 | cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18533 | cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18534 | cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18535 | cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18536 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18537 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18538 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18539 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18540 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18541 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18542 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18543 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18544 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18545 | cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18546 | cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18547 | cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18548 | cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18549 | cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18550 | cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18551 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18552 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18553 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18554 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18555 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18556 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18557 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18558 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18559 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18560 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18561 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18562 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18563 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18564 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18565 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18566 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18567 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18568 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18569 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18570 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18571 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18572 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18573 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
18574 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18575 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18576 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18577 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18578 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18579 | cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18580 | cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18581 | cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18582 | cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18583 | cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18584 | cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18585 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18586 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18587 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18588 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18589 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18590 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18591 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18592 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18593 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18594 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18595 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
18596 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18597 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18598 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18599 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18600 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18601 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18602 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18603 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18604 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18605 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18606 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18607 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18608 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18609 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18610 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18611 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18612 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18613 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18614 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18615 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18616 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18617 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18618 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18619 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18620 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18621 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18622 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18623 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18624 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18625 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18626 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18627 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
18628 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
18629 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
18630 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
18631 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
18632 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
18633 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18634 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18635 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18636 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
18637 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
18638 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
18639 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
18640 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
18641 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
18642 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18643 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18644 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18645 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18646 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 18647 | |
c921be7d NC |
18648 | #undef ARM_VARIANT |
18649 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
18650 | ||
21d799b5 NC |
18651 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
18652 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
18653 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
18654 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
18655 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
18656 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
18657 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18658 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18659 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18660 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18661 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18662 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18663 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18664 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18665 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18666 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18667 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18668 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18669 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18670 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18671 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
18672 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18673 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18674 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18675 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18676 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18677 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18678 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18679 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18680 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18681 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18682 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18683 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18684 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18685 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18686 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18687 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18688 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18689 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18690 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18691 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18692 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18693 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18694 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18695 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18696 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18697 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18698 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18699 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18700 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18701 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18702 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18703 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18704 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18705 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18706 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18707 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 18708 | |
c921be7d NC |
18709 | #undef ARM_VARIANT |
18710 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
18711 | ||
21d799b5 NC |
18712 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
18713 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18714 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18715 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18716 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
18717 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18718 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18719 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18720 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
18721 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
18722 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
18723 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
18724 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
18725 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
18726 | cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd), | |
18727 | cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn), | |
18728 | cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd), | |
18729 | cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn), | |
18730 | cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn), | |
18731 | cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn), | |
18732 | cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn), | |
18733 | cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn), | |
18734 | cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn), | |
18735 | cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn), | |
18736 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), | |
18737 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
18738 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
18739 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
18740 | cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
18741 | cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd), | |
18742 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), | |
18743 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
18744 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
18745 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
18746 | cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn), | |
18747 | cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn), | |
18748 | cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn), | |
18749 | cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn), | |
18750 | cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn), | |
18751 | cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn), | |
18752 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), | |
18753 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
18754 | cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
18755 | cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
18756 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
18757 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
18758 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
18759 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
18760 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
18761 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
18762 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
18763 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
18764 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
18765 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
18766 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18767 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18768 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18769 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18770 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18771 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18772 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
18773 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
18774 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
18775 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
18776 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18777 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18778 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18779 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18780 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18781 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18782 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18783 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18784 | cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18785 | cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18786 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
18787 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
18788 | }; |
18789 | #undef ARM_VARIANT | |
18790 | #undef THUMB_VARIANT | |
18791 | #undef TCE | |
18792 | #undef TCM | |
18793 | #undef TUE | |
18794 | #undef TUF | |
18795 | #undef TCC | |
8f06b2d8 | 18796 | #undef cCE |
e3cb604e PB |
18797 | #undef cCL |
18798 | #undef C3E | |
c19d1205 ZW |
18799 | #undef CE |
18800 | #undef CM | |
18801 | #undef UE | |
18802 | #undef UF | |
18803 | #undef UT | |
5287ad62 JB |
18804 | #undef NUF |
18805 | #undef nUF | |
18806 | #undef NCE | |
18807 | #undef nCE | |
c19d1205 ZW |
18808 | #undef OPS0 |
18809 | #undef OPS1 | |
18810 | #undef OPS2 | |
18811 | #undef OPS3 | |
18812 | #undef OPS4 | |
18813 | #undef OPS5 | |
18814 | #undef OPS6 | |
18815 | #undef do_0 | |
18816 | \f | |
18817 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 18818 | |
c19d1205 ZW |
18819 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
18820 | for use in the a.out file, and stores them in the array pointed to by buf. | |
18821 | This knows about the endian-ness of the target machine and does | |
18822 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
18823 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
18824 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 18825 | |
c19d1205 ZW |
18826 | void |
18827 | md_number_to_chars (char * buf, valueT val, int n) | |
18828 | { | |
18829 | if (target_big_endian) | |
18830 | number_to_chars_bigendian (buf, val, n); | |
18831 | else | |
18832 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
18833 | } |
18834 | ||
c19d1205 ZW |
18835 | static valueT |
18836 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 18837 | { |
c19d1205 ZW |
18838 | valueT result = 0; |
18839 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 18840 | |
c19d1205 | 18841 | if (target_big_endian) |
b99bd4ef | 18842 | { |
c19d1205 ZW |
18843 | while (n--) |
18844 | { | |
18845 | result <<= 8; | |
18846 | result |= (*where++ & 255); | |
18847 | } | |
b99bd4ef | 18848 | } |
c19d1205 | 18849 | else |
b99bd4ef | 18850 | { |
c19d1205 ZW |
18851 | while (n--) |
18852 | { | |
18853 | result <<= 8; | |
18854 | result |= (where[n] & 255); | |
18855 | } | |
bfae80f2 | 18856 | } |
b99bd4ef | 18857 | |
c19d1205 | 18858 | return result; |
bfae80f2 | 18859 | } |
b99bd4ef | 18860 | |
c19d1205 | 18861 | /* MD interface: Sections. */ |
b99bd4ef | 18862 | |
0110f2b8 PB |
18863 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
18864 | 2 bytes. */ | |
18865 | ||
c19d1205 | 18866 | int |
0110f2b8 | 18867 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
18868 | segT segtype ATTRIBUTE_UNUSED) |
18869 | { | |
0110f2b8 PB |
18870 | fragp->fr_var = 2; |
18871 | return 2; | |
18872 | } | |
18873 | ||
18874 | /* Convert a machine dependent frag. */ | |
18875 | ||
18876 | void | |
18877 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
18878 | { | |
18879 | unsigned long insn; | |
18880 | unsigned long old_op; | |
18881 | char *buf; | |
18882 | expressionS exp; | |
18883 | fixS *fixp; | |
18884 | int reloc_type; | |
18885 | int pc_rel; | |
18886 | int opcode; | |
18887 | ||
18888 | buf = fragp->fr_literal + fragp->fr_fix; | |
18889 | ||
18890 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
18891 | if (fragp->fr_symbol) |
18892 | { | |
0110f2b8 PB |
18893 | exp.X_op = O_symbol; |
18894 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
18895 | } |
18896 | else | |
18897 | { | |
0110f2b8 | 18898 | exp.X_op = O_constant; |
5f4273c7 | 18899 | } |
0110f2b8 PB |
18900 | exp.X_add_number = fragp->fr_offset; |
18901 | opcode = fragp->fr_subtype; | |
18902 | switch (opcode) | |
18903 | { | |
18904 | case T_MNEM_ldr_pc: | |
18905 | case T_MNEM_ldr_pc2: | |
18906 | case T_MNEM_ldr_sp: | |
18907 | case T_MNEM_str_sp: | |
18908 | case T_MNEM_ldr: | |
18909 | case T_MNEM_ldrb: | |
18910 | case T_MNEM_ldrh: | |
18911 | case T_MNEM_str: | |
18912 | case T_MNEM_strb: | |
18913 | case T_MNEM_strh: | |
18914 | if (fragp->fr_var == 4) | |
18915 | { | |
5f4273c7 | 18916 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
18917 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
18918 | { | |
18919 | insn |= (old_op & 0x700) << 4; | |
18920 | } | |
18921 | else | |
18922 | { | |
18923 | insn |= (old_op & 7) << 12; | |
18924 | insn |= (old_op & 0x38) << 13; | |
18925 | } | |
18926 | insn |= 0x00000c00; | |
18927 | put_thumb32_insn (buf, insn); | |
18928 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
18929 | } | |
18930 | else | |
18931 | { | |
18932 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
18933 | } | |
18934 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
18935 | break; | |
18936 | case T_MNEM_adr: | |
18937 | if (fragp->fr_var == 4) | |
18938 | { | |
18939 | insn = THUMB_OP32 (opcode); | |
18940 | insn |= (old_op & 0xf0) << 4; | |
18941 | put_thumb32_insn (buf, insn); | |
18942 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
18943 | } | |
18944 | else | |
18945 | { | |
18946 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
18947 | exp.X_add_number -= 4; | |
18948 | } | |
18949 | pc_rel = 1; | |
18950 | break; | |
18951 | case T_MNEM_mov: | |
18952 | case T_MNEM_movs: | |
18953 | case T_MNEM_cmp: | |
18954 | case T_MNEM_cmn: | |
18955 | if (fragp->fr_var == 4) | |
18956 | { | |
18957 | int r0off = (opcode == T_MNEM_mov | |
18958 | || opcode == T_MNEM_movs) ? 0 : 8; | |
18959 | insn = THUMB_OP32 (opcode); | |
18960 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
18961 | insn |= (old_op & 0x700) << r0off; | |
18962 | put_thumb32_insn (buf, insn); | |
18963 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
18964 | } | |
18965 | else | |
18966 | { | |
18967 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
18968 | } | |
18969 | pc_rel = 0; | |
18970 | break; | |
18971 | case T_MNEM_b: | |
18972 | if (fragp->fr_var == 4) | |
18973 | { | |
18974 | insn = THUMB_OP32(opcode); | |
18975 | put_thumb32_insn (buf, insn); | |
18976 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
18977 | } | |
18978 | else | |
18979 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
18980 | pc_rel = 1; | |
18981 | break; | |
18982 | case T_MNEM_bcond: | |
18983 | if (fragp->fr_var == 4) | |
18984 | { | |
18985 | insn = THUMB_OP32(opcode); | |
18986 | insn |= (old_op & 0xf00) << 14; | |
18987 | put_thumb32_insn (buf, insn); | |
18988 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
18989 | } | |
18990 | else | |
18991 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
18992 | pc_rel = 1; | |
18993 | break; | |
18994 | case T_MNEM_add_sp: | |
18995 | case T_MNEM_add_pc: | |
18996 | case T_MNEM_inc_sp: | |
18997 | case T_MNEM_dec_sp: | |
18998 | if (fragp->fr_var == 4) | |
18999 | { | |
19000 | /* ??? Choose between add and addw. */ | |
19001 | insn = THUMB_OP32 (opcode); | |
19002 | insn |= (old_op & 0xf0) << 4; | |
19003 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
19004 | if (opcode == T_MNEM_add_pc) |
19005 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
19006 | else | |
19007 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
19008 | } |
19009 | else | |
19010 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19011 | pc_rel = 0; | |
19012 | break; | |
19013 | ||
19014 | case T_MNEM_addi: | |
19015 | case T_MNEM_addis: | |
19016 | case T_MNEM_subi: | |
19017 | case T_MNEM_subis: | |
19018 | if (fragp->fr_var == 4) | |
19019 | { | |
19020 | insn = THUMB_OP32 (opcode); | |
19021 | insn |= (old_op & 0xf0) << 4; | |
19022 | insn |= (old_op & 0xf) << 16; | |
19023 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
19024 | if (insn & (1 << 20)) |
19025 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
19026 | else | |
19027 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
19028 | } |
19029 | else | |
19030 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19031 | pc_rel = 0; | |
19032 | break; | |
19033 | default: | |
5f4273c7 | 19034 | abort (); |
0110f2b8 PB |
19035 | } |
19036 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 19037 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
19038 | fixp->fx_file = fragp->fr_file; |
19039 | fixp->fx_line = fragp->fr_line; | |
19040 | fragp->fr_fix += fragp->fr_var; | |
19041 | } | |
19042 | ||
19043 | /* Return the size of a relaxable immediate operand instruction. | |
19044 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
19045 | static int | |
19046 | relax_immediate (fragS *fragp, int size, int shift) | |
19047 | { | |
19048 | offsetT offset; | |
19049 | offsetT mask; | |
19050 | offsetT low; | |
19051 | ||
19052 | /* ??? Should be able to do better than this. */ | |
19053 | if (fragp->fr_symbol) | |
19054 | return 4; | |
19055 | ||
19056 | low = (1 << shift) - 1; | |
19057 | mask = (1 << (shift + size)) - (1 << shift); | |
19058 | offset = fragp->fr_offset; | |
19059 | /* Force misaligned offsets to 32-bit variant. */ | |
19060 | if (offset & low) | |
5e77afaa | 19061 | return 4; |
0110f2b8 PB |
19062 | if (offset & ~mask) |
19063 | return 4; | |
19064 | return 2; | |
19065 | } | |
19066 | ||
5e77afaa PB |
19067 | /* Get the address of a symbol during relaxation. */ |
19068 | static addressT | |
5f4273c7 | 19069 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
19070 | { |
19071 | fragS *sym_frag; | |
19072 | addressT addr; | |
19073 | symbolS *sym; | |
19074 | ||
19075 | sym = fragp->fr_symbol; | |
19076 | sym_frag = symbol_get_frag (sym); | |
19077 | know (S_GET_SEGMENT (sym) != absolute_section | |
19078 | || sym_frag == &zero_address_frag); | |
19079 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
19080 | ||
19081 | /* If frag has yet to be reached on this pass, assume it will | |
19082 | move by STRETCH just as we did. If this is not so, it will | |
19083 | be because some frag between grows, and that will force | |
19084 | another pass. */ | |
19085 | ||
19086 | if (stretch != 0 | |
19087 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
19088 | { |
19089 | fragS *f; | |
19090 | ||
19091 | /* Adjust stretch for any alignment frag. Note that if have | |
19092 | been expanding the earlier code, the symbol may be | |
19093 | defined in what appears to be an earlier frag. FIXME: | |
19094 | This doesn't handle the fr_subtype field, which specifies | |
19095 | a maximum number of bytes to skip when doing an | |
19096 | alignment. */ | |
19097 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
19098 | { | |
19099 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
19100 | { | |
19101 | if (stretch < 0) | |
19102 | stretch = - ((- stretch) | |
19103 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
19104 | else | |
19105 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
19106 | if (stretch == 0) | |
19107 | break; | |
19108 | } | |
19109 | } | |
19110 | if (f != NULL) | |
19111 | addr += stretch; | |
19112 | } | |
5e77afaa PB |
19113 | |
19114 | return addr; | |
19115 | } | |
19116 | ||
0110f2b8 PB |
19117 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
19118 | load. */ | |
19119 | static int | |
5e77afaa | 19120 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
19121 | { |
19122 | addressT addr; | |
19123 | offsetT val; | |
19124 | ||
19125 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
19126 | if (fragp->fr_symbol == NULL |
19127 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
19128 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
19129 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
19130 | return 4; |
19131 | ||
5f4273c7 | 19132 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
19133 | addr = fragp->fr_address + fragp->fr_fix; |
19134 | addr = (addr + 4) & ~3; | |
5e77afaa | 19135 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 19136 | if (val & 3) |
5e77afaa | 19137 | return 4; |
0110f2b8 PB |
19138 | val -= addr; |
19139 | if (val < 0 || val > 1020) | |
19140 | return 4; | |
19141 | return 2; | |
19142 | } | |
19143 | ||
19144 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
19145 | static int | |
19146 | relax_addsub (fragS *fragp, asection *sec) | |
19147 | { | |
19148 | char *buf; | |
19149 | int op; | |
19150 | ||
19151 | buf = fragp->fr_literal + fragp->fr_fix; | |
19152 | op = bfd_get_16(sec->owner, buf); | |
19153 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
19154 | return relax_immediate (fragp, 8, 0); | |
19155 | else | |
19156 | return relax_immediate (fragp, 3, 0); | |
19157 | } | |
19158 | ||
19159 | ||
19160 | /* Return the size of a relaxable branch instruction. BITS is the | |
19161 | size of the offset field in the narrow instruction. */ | |
19162 | ||
19163 | static int | |
5e77afaa | 19164 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
19165 | { |
19166 | addressT addr; | |
19167 | offsetT val; | |
19168 | offsetT limit; | |
19169 | ||
19170 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 19171 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
19172 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
19173 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
19174 | return 4; |
19175 | ||
267bf995 RR |
19176 | #ifdef OBJ_ELF |
19177 | if (S_IS_DEFINED (fragp->fr_symbol) | |
19178 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
19179 | return 4; | |
0d9b4b55 NC |
19180 | |
19181 | /* PR 12532. Global symbols with default visibility might | |
19182 | be preempted, so do not relax relocations to them. */ | |
19183 | if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT) | |
19184 | && (! S_IS_LOCAL (fragp->fr_symbol))) | |
19185 | return 4; | |
267bf995 RR |
19186 | #endif |
19187 | ||
5f4273c7 | 19188 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
19189 | addr = fragp->fr_address + fragp->fr_fix + 4; |
19190 | val -= addr; | |
19191 | ||
19192 | /* Offset is a signed value *2 */ | |
19193 | limit = 1 << bits; | |
19194 | if (val >= limit || val < -limit) | |
19195 | return 4; | |
19196 | return 2; | |
19197 | } | |
19198 | ||
19199 | ||
19200 | /* Relax a machine dependent frag. This returns the amount by which | |
19201 | the current size of the frag should change. */ | |
19202 | ||
19203 | int | |
5e77afaa | 19204 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
19205 | { |
19206 | int oldsize; | |
19207 | int newsize; | |
19208 | ||
19209 | oldsize = fragp->fr_var; | |
19210 | switch (fragp->fr_subtype) | |
19211 | { | |
19212 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 19213 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
19214 | break; |
19215 | case T_MNEM_ldr_pc: | |
19216 | case T_MNEM_ldr_sp: | |
19217 | case T_MNEM_str_sp: | |
5f4273c7 | 19218 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
19219 | break; |
19220 | case T_MNEM_ldr: | |
19221 | case T_MNEM_str: | |
5f4273c7 | 19222 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
19223 | break; |
19224 | case T_MNEM_ldrh: | |
19225 | case T_MNEM_strh: | |
5f4273c7 | 19226 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
19227 | break; |
19228 | case T_MNEM_ldrb: | |
19229 | case T_MNEM_strb: | |
5f4273c7 | 19230 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
19231 | break; |
19232 | case T_MNEM_adr: | |
5f4273c7 | 19233 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
19234 | break; |
19235 | case T_MNEM_mov: | |
19236 | case T_MNEM_movs: | |
19237 | case T_MNEM_cmp: | |
19238 | case T_MNEM_cmn: | |
5f4273c7 | 19239 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
19240 | break; |
19241 | case T_MNEM_b: | |
5f4273c7 | 19242 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
19243 | break; |
19244 | case T_MNEM_bcond: | |
5f4273c7 | 19245 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
19246 | break; |
19247 | case T_MNEM_add_sp: | |
19248 | case T_MNEM_add_pc: | |
19249 | newsize = relax_immediate (fragp, 8, 2); | |
19250 | break; | |
19251 | case T_MNEM_inc_sp: | |
19252 | case T_MNEM_dec_sp: | |
19253 | newsize = relax_immediate (fragp, 7, 2); | |
19254 | break; | |
19255 | case T_MNEM_addi: | |
19256 | case T_MNEM_addis: | |
19257 | case T_MNEM_subi: | |
19258 | case T_MNEM_subis: | |
19259 | newsize = relax_addsub (fragp, sec); | |
19260 | break; | |
19261 | default: | |
5f4273c7 | 19262 | abort (); |
0110f2b8 | 19263 | } |
5e77afaa PB |
19264 | |
19265 | fragp->fr_var = newsize; | |
19266 | /* Freeze wide instructions that are at or before the same location as | |
19267 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
19268 | Don't freeze them unconditionally because targets may be artificially |
19269 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 19270 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 19271 | { |
0110f2b8 | 19272 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 19273 | frag_wane (fragp); |
0110f2b8 | 19274 | } |
5e77afaa | 19275 | |
0110f2b8 | 19276 | return newsize - oldsize; |
c19d1205 | 19277 | } |
b99bd4ef | 19278 | |
c19d1205 | 19279 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 19280 | |
c19d1205 ZW |
19281 | valueT |
19282 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
19283 | valueT size) | |
19284 | { | |
f0927246 NC |
19285 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
19286 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
19287 | { | |
19288 | /* For a.out, force the section size to be aligned. If we don't do | |
19289 | this, BFD will align it for us, but it will not write out the | |
19290 | final bytes of the section. This may be a bug in BFD, but it is | |
19291 | easier to fix it here since that is how the other a.out targets | |
19292 | work. */ | |
19293 | int align; | |
19294 | ||
19295 | align = bfd_get_section_alignment (stdoutput, segment); | |
19296 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
19297 | } | |
c19d1205 | 19298 | #endif |
f0927246 NC |
19299 | |
19300 | return size; | |
bfae80f2 | 19301 | } |
b99bd4ef | 19302 | |
c19d1205 ZW |
19303 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
19304 | of an rs_align_code fragment. */ | |
19305 | ||
19306 | void | |
19307 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 19308 | { |
e7495e45 NS |
19309 | static char const arm_noop[2][2][4] = |
19310 | { | |
19311 | { /* ARMv1 */ | |
19312 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
19313 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
19314 | }, | |
19315 | { /* ARMv6k */ | |
19316 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
19317 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
19318 | }, | |
19319 | }; | |
19320 | static char const thumb_noop[2][2][2] = | |
19321 | { | |
19322 | { /* Thumb-1 */ | |
19323 | {0xc0, 0x46}, /* LE */ | |
19324 | {0x46, 0xc0}, /* BE */ | |
19325 | }, | |
19326 | { /* Thumb-2 */ | |
19327 | {0x00, 0xbf}, /* LE */ | |
19328 | {0xbf, 0x00} /* BE */ | |
19329 | } | |
19330 | }; | |
19331 | static char const wide_thumb_noop[2][4] = | |
19332 | { /* Wide Thumb-2 */ | |
19333 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
19334 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
19335 | }; | |
c921be7d | 19336 | |
e7495e45 | 19337 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
19338 | char * p; |
19339 | const char * noop; | |
e7495e45 | 19340 | const char *narrow_noop = NULL; |
cd000bff DJ |
19341 | #ifdef OBJ_ELF |
19342 | enum mstate state; | |
19343 | #endif | |
bfae80f2 | 19344 | |
c19d1205 | 19345 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
19346 | return; |
19347 | ||
c19d1205 ZW |
19348 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
19349 | p = fragP->fr_literal + fragP->fr_fix; | |
19350 | fix = 0; | |
bfae80f2 | 19351 | |
c19d1205 ZW |
19352 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
19353 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 19354 | |
cd000bff | 19355 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 19356 | |
cd000bff | 19357 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 19358 | { |
e7495e45 NS |
19359 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
19360 | { | |
19361 | narrow_noop = thumb_noop[1][target_big_endian]; | |
19362 | noop = wide_thumb_noop[target_big_endian]; | |
19363 | } | |
c19d1205 | 19364 | else |
e7495e45 NS |
19365 | noop = thumb_noop[0][target_big_endian]; |
19366 | noop_size = 2; | |
cd000bff DJ |
19367 | #ifdef OBJ_ELF |
19368 | state = MAP_THUMB; | |
19369 | #endif | |
7ed4c4c5 NC |
19370 | } |
19371 | else | |
19372 | { | |
e7495e45 NS |
19373 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] |
19374 | [target_big_endian]; | |
19375 | noop_size = 4; | |
cd000bff DJ |
19376 | #ifdef OBJ_ELF |
19377 | state = MAP_ARM; | |
19378 | #endif | |
7ed4c4c5 | 19379 | } |
c921be7d | 19380 | |
e7495e45 | 19381 | fragP->fr_var = noop_size; |
c921be7d | 19382 | |
c19d1205 | 19383 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 19384 | { |
c19d1205 | 19385 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
19386 | #ifdef OBJ_ELF |
19387 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
19388 | #endif | |
c19d1205 ZW |
19389 | memset (p, 0, fix); |
19390 | p += fix; | |
19391 | bytes -= fix; | |
a737bd4d | 19392 | } |
a737bd4d | 19393 | |
e7495e45 NS |
19394 | if (narrow_noop) |
19395 | { | |
19396 | if (bytes & noop_size) | |
19397 | { | |
19398 | /* Insert a narrow noop. */ | |
19399 | memcpy (p, narrow_noop, noop_size); | |
19400 | p += noop_size; | |
19401 | bytes -= noop_size; | |
19402 | fix += noop_size; | |
19403 | } | |
19404 | ||
19405 | /* Use wide noops for the remainder */ | |
19406 | noop_size = 4; | |
19407 | } | |
19408 | ||
c19d1205 | 19409 | while (bytes >= noop_size) |
a737bd4d | 19410 | { |
c19d1205 ZW |
19411 | memcpy (p, noop, noop_size); |
19412 | p += noop_size; | |
19413 | bytes -= noop_size; | |
19414 | fix += noop_size; | |
a737bd4d NC |
19415 | } |
19416 | ||
c19d1205 | 19417 | fragP->fr_fix += fix; |
a737bd4d NC |
19418 | } |
19419 | ||
c19d1205 ZW |
19420 | /* Called from md_do_align. Used to create an alignment |
19421 | frag in a code section. */ | |
19422 | ||
19423 | void | |
19424 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 19425 | { |
c19d1205 | 19426 | char * p; |
7ed4c4c5 | 19427 | |
c19d1205 | 19428 | /* We assume that there will never be a requirement |
6ec8e702 | 19429 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 19430 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
19431 | { |
19432 | char err_msg[128]; | |
19433 | ||
19434 | sprintf (err_msg, | |
19435 | _("alignments greater than %d bytes not supported in .text sections."), | |
19436 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 19437 | as_fatal ("%s", err_msg); |
6ec8e702 | 19438 | } |
bfae80f2 | 19439 | |
c19d1205 ZW |
19440 | p = frag_var (rs_align_code, |
19441 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
19442 | 1, | |
19443 | (relax_substateT) max, | |
19444 | (symbolS *) NULL, | |
19445 | (offsetT) n, | |
19446 | (char *) NULL); | |
19447 | *p = 0; | |
19448 | } | |
bfae80f2 | 19449 | |
8dc2430f NC |
19450 | /* Perform target specific initialisation of a frag. |
19451 | Note - despite the name this initialisation is not done when the frag | |
19452 | is created, but only when its type is assigned. A frag can be created | |
19453 | and used a long time before its type is set, so beware of assuming that | |
19454 | this initialisationis performed first. */ | |
bfae80f2 | 19455 | |
cd000bff DJ |
19456 | #ifndef OBJ_ELF |
19457 | void | |
19458 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
19459 | { | |
19460 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 19461 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
19462 | } |
19463 | ||
19464 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 19465 | void |
cd000bff | 19466 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 19467 | { |
8dc2430f NC |
19468 | /* If the current ARM vs THUMB mode has not already |
19469 | been recorded into this frag then do so now. */ | |
cd000bff DJ |
19470 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
19471 | { | |
19472 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; | |
19473 | ||
19474 | /* Record a mapping symbol for alignment frags. We will delete this | |
19475 | later if the alignment ends up empty. */ | |
19476 | switch (fragP->fr_type) | |
19477 | { | |
19478 | case rs_align: | |
19479 | case rs_align_test: | |
19480 | case rs_fill: | |
19481 | mapping_state_2 (MAP_DATA, max_chars); | |
19482 | break; | |
19483 | case rs_align_code: | |
19484 | mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); | |
19485 | break; | |
19486 | default: | |
19487 | break; | |
19488 | } | |
19489 | } | |
bfae80f2 RE |
19490 | } |
19491 | ||
c19d1205 ZW |
19492 | /* When we change sections we need to issue a new mapping symbol. */ |
19493 | ||
19494 | void | |
19495 | arm_elf_change_section (void) | |
bfae80f2 | 19496 | { |
c19d1205 ZW |
19497 | /* Link an unlinked unwind index table section to the .text section. */ |
19498 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
19499 | && elf_linked_to_section (now_seg) == NULL) | |
19500 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
19501 | } |
19502 | ||
c19d1205 ZW |
19503 | int |
19504 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 19505 | { |
c19d1205 ZW |
19506 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
19507 | return SHT_ARM_EXIDX; | |
e45d0630 | 19508 | |
c19d1205 ZW |
19509 | return -1; |
19510 | } | |
19511 | \f | |
19512 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 19513 | |
c19d1205 | 19514 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 19515 | |
5f4273c7 | 19516 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 19517 | |
bfae80f2 | 19518 | static void |
c19d1205 | 19519 | flush_pending_unwind (void) |
bfae80f2 | 19520 | { |
c19d1205 | 19521 | offsetT offset; |
bfae80f2 | 19522 | |
c19d1205 ZW |
19523 | offset = unwind.pending_offset; |
19524 | unwind.pending_offset = 0; | |
19525 | if (offset != 0) | |
19526 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
19527 | } |
19528 | ||
c19d1205 ZW |
19529 | /* Add an opcode to this list for this function. Two-byte opcodes should |
19530 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
19531 | order. */ | |
19532 | ||
bfae80f2 | 19533 | static void |
c19d1205 | 19534 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 19535 | { |
c19d1205 ZW |
19536 | /* Add any deferred stack adjustment. */ |
19537 | if (unwind.pending_offset) | |
19538 | flush_pending_unwind (); | |
bfae80f2 | 19539 | |
c19d1205 | 19540 | unwind.sp_restored = 0; |
bfae80f2 | 19541 | |
c19d1205 | 19542 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 19543 | { |
c19d1205 ZW |
19544 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
19545 | if (unwind.opcodes) | |
21d799b5 NC |
19546 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
19547 | unwind.opcode_alloc); | |
c19d1205 | 19548 | else |
21d799b5 | 19549 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 19550 | } |
c19d1205 | 19551 | while (length > 0) |
bfae80f2 | 19552 | { |
c19d1205 ZW |
19553 | length--; |
19554 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
19555 | op >>= 8; | |
19556 | unwind.opcode_count++; | |
bfae80f2 | 19557 | } |
bfae80f2 RE |
19558 | } |
19559 | ||
c19d1205 ZW |
19560 | /* Add unwind opcodes to adjust the stack pointer. */ |
19561 | ||
bfae80f2 | 19562 | static void |
c19d1205 | 19563 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 19564 | { |
c19d1205 | 19565 | valueT op; |
bfae80f2 | 19566 | |
c19d1205 | 19567 | if (offset > 0x200) |
bfae80f2 | 19568 | { |
c19d1205 ZW |
19569 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
19570 | char bytes[5]; | |
19571 | int n; | |
19572 | valueT o; | |
bfae80f2 | 19573 | |
c19d1205 ZW |
19574 | /* Long form: 0xb2, uleb128. */ |
19575 | /* This might not fit in a word so add the individual bytes, | |
19576 | remembering the list is built in reverse order. */ | |
19577 | o = (valueT) ((offset - 0x204) >> 2); | |
19578 | if (o == 0) | |
19579 | add_unwind_opcode (0, 1); | |
bfae80f2 | 19580 | |
c19d1205 ZW |
19581 | /* Calculate the uleb128 encoding of the offset. */ |
19582 | n = 0; | |
19583 | while (o) | |
19584 | { | |
19585 | bytes[n] = o & 0x7f; | |
19586 | o >>= 7; | |
19587 | if (o) | |
19588 | bytes[n] |= 0x80; | |
19589 | n++; | |
19590 | } | |
19591 | /* Add the insn. */ | |
19592 | for (; n; n--) | |
19593 | add_unwind_opcode (bytes[n - 1], 1); | |
19594 | add_unwind_opcode (0xb2, 1); | |
19595 | } | |
19596 | else if (offset > 0x100) | |
bfae80f2 | 19597 | { |
c19d1205 ZW |
19598 | /* Two short opcodes. */ |
19599 | add_unwind_opcode (0x3f, 1); | |
19600 | op = (offset - 0x104) >> 2; | |
19601 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19602 | } |
c19d1205 ZW |
19603 | else if (offset > 0) |
19604 | { | |
19605 | /* Short opcode. */ | |
19606 | op = (offset - 4) >> 2; | |
19607 | add_unwind_opcode (op, 1); | |
19608 | } | |
19609 | else if (offset < 0) | |
bfae80f2 | 19610 | { |
c19d1205 ZW |
19611 | offset = -offset; |
19612 | while (offset > 0x100) | |
bfae80f2 | 19613 | { |
c19d1205 ZW |
19614 | add_unwind_opcode (0x7f, 1); |
19615 | offset -= 0x100; | |
bfae80f2 | 19616 | } |
c19d1205 ZW |
19617 | op = ((offset - 4) >> 2) | 0x40; |
19618 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19619 | } |
bfae80f2 RE |
19620 | } |
19621 | ||
c19d1205 ZW |
19622 | /* Finish the list of unwind opcodes for this function. */ |
19623 | static void | |
19624 | finish_unwind_opcodes (void) | |
bfae80f2 | 19625 | { |
c19d1205 | 19626 | valueT op; |
bfae80f2 | 19627 | |
c19d1205 | 19628 | if (unwind.fp_used) |
bfae80f2 | 19629 | { |
708587a4 | 19630 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
19631 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
19632 | flush_pending_unwind (); | |
bfae80f2 | 19633 | |
c19d1205 ZW |
19634 | /* After restoring sp from the frame pointer. */ |
19635 | op = 0x90 | unwind.fp_reg; | |
19636 | add_unwind_opcode (op, 1); | |
19637 | } | |
19638 | else | |
19639 | flush_pending_unwind (); | |
bfae80f2 RE |
19640 | } |
19641 | ||
bfae80f2 | 19642 | |
c19d1205 ZW |
19643 | /* Start an exception table entry. If idx is nonzero this is an index table |
19644 | entry. */ | |
bfae80f2 RE |
19645 | |
19646 | static void | |
c19d1205 | 19647 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 19648 | { |
c19d1205 ZW |
19649 | const char * text_name; |
19650 | const char * prefix; | |
19651 | const char * prefix_once; | |
19652 | const char * group_name; | |
19653 | size_t prefix_len; | |
19654 | size_t text_len; | |
19655 | char * sec_name; | |
19656 | size_t sec_name_len; | |
19657 | int type; | |
19658 | int flags; | |
19659 | int linkonce; | |
bfae80f2 | 19660 | |
c19d1205 | 19661 | if (idx) |
bfae80f2 | 19662 | { |
c19d1205 ZW |
19663 | prefix = ELF_STRING_ARM_unwind; |
19664 | prefix_once = ELF_STRING_ARM_unwind_once; | |
19665 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 19666 | } |
c19d1205 | 19667 | else |
bfae80f2 | 19668 | { |
c19d1205 ZW |
19669 | prefix = ELF_STRING_ARM_unwind_info; |
19670 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
19671 | type = SHT_PROGBITS; | |
bfae80f2 RE |
19672 | } |
19673 | ||
c19d1205 ZW |
19674 | text_name = segment_name (text_seg); |
19675 | if (streq (text_name, ".text")) | |
19676 | text_name = ""; | |
19677 | ||
19678 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
19679 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 19680 | { |
c19d1205 ZW |
19681 | prefix = prefix_once; |
19682 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
19683 | } |
19684 | ||
c19d1205 ZW |
19685 | prefix_len = strlen (prefix); |
19686 | text_len = strlen (text_name); | |
19687 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 19688 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
19689 | memcpy (sec_name, prefix, prefix_len); |
19690 | memcpy (sec_name + prefix_len, text_name, text_len); | |
19691 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 19692 | |
c19d1205 ZW |
19693 | flags = SHF_ALLOC; |
19694 | linkonce = 0; | |
19695 | group_name = 0; | |
bfae80f2 | 19696 | |
c19d1205 ZW |
19697 | /* Handle COMDAT group. */ |
19698 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 19699 | { |
c19d1205 ZW |
19700 | group_name = elf_group_name (text_seg); |
19701 | if (group_name == NULL) | |
19702 | { | |
bd3ba5d1 | 19703 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
19704 | segment_name (text_seg)); |
19705 | ignore_rest_of_line (); | |
19706 | return; | |
19707 | } | |
19708 | flags |= SHF_GROUP; | |
19709 | linkonce = 1; | |
bfae80f2 RE |
19710 | } |
19711 | ||
c19d1205 | 19712 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 19713 | |
5f4273c7 | 19714 | /* Set the section link for index tables. */ |
c19d1205 ZW |
19715 | if (idx) |
19716 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
19717 | } |
19718 | ||
bfae80f2 | 19719 | |
c19d1205 ZW |
19720 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
19721 | personality routine data. Returns zero, or the index table value for | |
19722 | and inline entry. */ | |
19723 | ||
19724 | static valueT | |
19725 | create_unwind_entry (int have_data) | |
bfae80f2 | 19726 | { |
c19d1205 ZW |
19727 | int size; |
19728 | addressT where; | |
19729 | char *ptr; | |
19730 | /* The current word of data. */ | |
19731 | valueT data; | |
19732 | /* The number of bytes left in this word. */ | |
19733 | int n; | |
bfae80f2 | 19734 | |
c19d1205 | 19735 | finish_unwind_opcodes (); |
bfae80f2 | 19736 | |
c19d1205 ZW |
19737 | /* Remember the current text section. */ |
19738 | unwind.saved_seg = now_seg; | |
19739 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 19740 | |
c19d1205 | 19741 | start_unwind_section (now_seg, 0); |
bfae80f2 | 19742 | |
c19d1205 | 19743 | if (unwind.personality_routine == NULL) |
bfae80f2 | 19744 | { |
c19d1205 ZW |
19745 | if (unwind.personality_index == -2) |
19746 | { | |
19747 | if (have_data) | |
5f4273c7 | 19748 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
19749 | return 1; /* EXIDX_CANTUNWIND. */ |
19750 | } | |
bfae80f2 | 19751 | |
c19d1205 ZW |
19752 | /* Use a default personality routine if none is specified. */ |
19753 | if (unwind.personality_index == -1) | |
19754 | { | |
19755 | if (unwind.opcode_count > 3) | |
19756 | unwind.personality_index = 1; | |
19757 | else | |
19758 | unwind.personality_index = 0; | |
19759 | } | |
bfae80f2 | 19760 | |
c19d1205 ZW |
19761 | /* Space for the personality routine entry. */ |
19762 | if (unwind.personality_index == 0) | |
19763 | { | |
19764 | if (unwind.opcode_count > 3) | |
19765 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 19766 | |
c19d1205 ZW |
19767 | if (!have_data) |
19768 | { | |
19769 | /* All the data is inline in the index table. */ | |
19770 | data = 0x80; | |
19771 | n = 3; | |
19772 | while (unwind.opcode_count > 0) | |
19773 | { | |
19774 | unwind.opcode_count--; | |
19775 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19776 | n--; | |
19777 | } | |
bfae80f2 | 19778 | |
c19d1205 ZW |
19779 | /* Pad with "finish" opcodes. */ |
19780 | while (n--) | |
19781 | data = (data << 8) | 0xb0; | |
bfae80f2 | 19782 | |
c19d1205 ZW |
19783 | return data; |
19784 | } | |
19785 | size = 0; | |
19786 | } | |
19787 | else | |
19788 | /* We get two opcodes "free" in the first word. */ | |
19789 | size = unwind.opcode_count - 2; | |
19790 | } | |
19791 | else | |
19792 | /* An extra byte is required for the opcode count. */ | |
19793 | size = unwind.opcode_count + 1; | |
bfae80f2 | 19794 | |
c19d1205 ZW |
19795 | size = (size + 3) >> 2; |
19796 | if (size > 0xff) | |
19797 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 19798 | |
c19d1205 ZW |
19799 | frag_align (2, 0, 0); |
19800 | record_alignment (now_seg, 2); | |
19801 | unwind.table_entry = expr_build_dot (); | |
19802 | ||
19803 | /* Allocate the table entry. */ | |
19804 | ptr = frag_more ((size << 2) + 4); | |
19805 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 19806 | |
c19d1205 | 19807 | switch (unwind.personality_index) |
bfae80f2 | 19808 | { |
c19d1205 ZW |
19809 | case -1: |
19810 | /* ??? Should this be a PLT generating relocation? */ | |
19811 | /* Custom personality routine. */ | |
19812 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
19813 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 19814 | |
c19d1205 ZW |
19815 | where += 4; |
19816 | ptr += 4; | |
bfae80f2 | 19817 | |
c19d1205 ZW |
19818 | /* Set the first byte to the number of additional words. */ |
19819 | data = size - 1; | |
19820 | n = 3; | |
19821 | break; | |
bfae80f2 | 19822 | |
c19d1205 ZW |
19823 | /* ABI defined personality routines. */ |
19824 | case 0: | |
19825 | /* Three opcodes bytes are packed into the first word. */ | |
19826 | data = 0x80; | |
19827 | n = 3; | |
19828 | break; | |
bfae80f2 | 19829 | |
c19d1205 ZW |
19830 | case 1: |
19831 | case 2: | |
19832 | /* The size and first two opcode bytes go in the first word. */ | |
19833 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
19834 | n = 2; | |
19835 | break; | |
bfae80f2 | 19836 | |
c19d1205 ZW |
19837 | default: |
19838 | /* Should never happen. */ | |
19839 | abort (); | |
19840 | } | |
bfae80f2 | 19841 | |
c19d1205 ZW |
19842 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
19843 | time. */ | |
19844 | while (unwind.opcode_count > 0) | |
19845 | { | |
19846 | if (n == 0) | |
19847 | { | |
19848 | md_number_to_chars (ptr, data, 4); | |
19849 | ptr += 4; | |
19850 | n = 4; | |
19851 | data = 0; | |
19852 | } | |
19853 | unwind.opcode_count--; | |
19854 | n--; | |
19855 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19856 | } | |
19857 | ||
19858 | /* Finish off the last word. */ | |
19859 | if (n < 4) | |
19860 | { | |
19861 | /* Pad with "finish" opcodes. */ | |
19862 | while (n--) | |
19863 | data = (data << 8) | 0xb0; | |
19864 | ||
19865 | md_number_to_chars (ptr, data, 4); | |
19866 | } | |
19867 | ||
19868 | if (!have_data) | |
19869 | { | |
19870 | /* Add an empty descriptor if there is no user-specified data. */ | |
19871 | ptr = frag_more (4); | |
19872 | md_number_to_chars (ptr, 0, 4); | |
19873 | } | |
19874 | ||
19875 | return 0; | |
bfae80f2 RE |
19876 | } |
19877 | ||
f0927246 NC |
19878 | |
19879 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
19880 | ||
19881 | void | |
19882 | tc_arm_frame_initial_instructions (void) | |
19883 | { | |
19884 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
19885 | } | |
19886 | #endif /* OBJ_ELF */ | |
19887 | ||
c19d1205 ZW |
19888 | /* Convert REGNAME to a DWARF-2 register number. */ |
19889 | ||
19890 | int | |
1df69f4f | 19891 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 19892 | { |
1df69f4f | 19893 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
c19d1205 ZW |
19894 | |
19895 | if (reg == FAIL) | |
19896 | return -1; | |
19897 | ||
19898 | return reg; | |
bfae80f2 RE |
19899 | } |
19900 | ||
f0927246 | 19901 | #ifdef TE_PE |
c19d1205 | 19902 | void |
f0927246 | 19903 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 19904 | { |
91d6fa6a | 19905 | expressionS exp; |
bfae80f2 | 19906 | |
91d6fa6a NC |
19907 | exp.X_op = O_secrel; |
19908 | exp.X_add_symbol = symbol; | |
19909 | exp.X_add_number = 0; | |
19910 | emit_expr (&exp, size); | |
f0927246 NC |
19911 | } |
19912 | #endif | |
bfae80f2 | 19913 | |
c19d1205 | 19914 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 19915 | |
2fc8bdac ZW |
19916 | /* Return the address within the segment that a PC-relative fixup is |
19917 | relative to. For ARM, PC-relative fixups applied to instructions | |
19918 | are generally relative to the location of the fixup plus 8 bytes. | |
19919 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
19920 | require special handling. */ | |
bfae80f2 | 19921 | |
c19d1205 | 19922 | long |
2fc8bdac | 19923 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 19924 | { |
2fc8bdac ZW |
19925 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
19926 | ||
19927 | /* If this is pc-relative and we are going to emit a relocation | |
19928 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
19929 | will need. Otherwise we want to use the calculated base. |
19930 | For WinCE we skip the bias for externals as well, since this | |
19931 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 19932 | if (fixP->fx_pcrel |
2fc8bdac | 19933 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
19934 | || (arm_force_relocation (fixP) |
19935 | #ifdef TE_WINCE | |
19936 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
19937 | #endif | |
19938 | ))) | |
2fc8bdac | 19939 | base = 0; |
bfae80f2 | 19940 | |
267bf995 | 19941 | |
c19d1205 | 19942 | switch (fixP->fx_r_type) |
bfae80f2 | 19943 | { |
2fc8bdac ZW |
19944 | /* PC relative addressing on the Thumb is slightly odd as the |
19945 | bottom two bits of the PC are forced to zero for the | |
19946 | calculation. This happens *after* application of the | |
19947 | pipeline offset. However, Thumb adrl already adjusts for | |
19948 | this, so we need not do it again. */ | |
c19d1205 | 19949 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 19950 | return base & ~3; |
c19d1205 ZW |
19951 | |
19952 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
19953 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 19954 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 19955 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 19956 | return (base + 4) & ~3; |
c19d1205 | 19957 | |
2fc8bdac ZW |
19958 | /* Thumb branches are simply offset by +4. */ |
19959 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
19960 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
19961 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
19962 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 19963 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 19964 | return base + 4; |
bfae80f2 | 19965 | |
267bf995 | 19966 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
19967 | if (fixP->fx_addsy |
19968 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 19969 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
19970 | && ARM_IS_FUNC (fixP->fx_addsy) |
19971 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19972 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
19973 | return base + 4; | |
19974 | ||
00adf2d4 JB |
19975 | /* BLX is like branches above, but forces the low two bits of PC to |
19976 | zero. */ | |
486499d0 CL |
19977 | case BFD_RELOC_THUMB_PCREL_BLX: |
19978 | if (fixP->fx_addsy | |
19979 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 19980 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
19981 | && THUMB_IS_FUNC (fixP->fx_addsy) |
19982 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19983 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
19984 | return (base + 4) & ~3; |
19985 | ||
2fc8bdac ZW |
19986 | /* ARM mode branches are offset by +8. However, the Windows CE |
19987 | loader expects the relocation not to take this into account. */ | |
267bf995 | 19988 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
19989 | if (fixP->fx_addsy |
19990 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 19991 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
19992 | && ARM_IS_FUNC (fixP->fx_addsy) |
19993 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
19994 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 19995 | return base + 8; |
267bf995 | 19996 | |
486499d0 CL |
19997 | case BFD_RELOC_ARM_PCREL_CALL: |
19998 | if (fixP->fx_addsy | |
19999 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20000 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20001 | && THUMB_IS_FUNC (fixP->fx_addsy) |
20002 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20003 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 20004 | return base + 8; |
267bf995 | 20005 | |
2fc8bdac | 20006 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 20007 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 20008 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 20009 | #ifdef TE_WINCE |
5f4273c7 | 20010 | /* When handling fixups immediately, because we have already |
53baae48 NC |
20011 | discovered the value of a symbol, or the address of the frag involved |
20012 | we must account for the offset by +8, as the OS loader will never see the reloc. | |
20013 | see fixup_segment() in write.c | |
20014 | The S_IS_EXTERNAL test handles the case of global symbols. | |
20015 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
20016 | if (fixP->fx_pcrel | |
20017 | && fixP->fx_addsy != NULL | |
20018 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20019 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
20020 | return base + 8; | |
2fc8bdac | 20021 | return base; |
c19d1205 | 20022 | #else |
2fc8bdac | 20023 | return base + 8; |
c19d1205 | 20024 | #endif |
2fc8bdac | 20025 | |
267bf995 | 20026 | |
2fc8bdac ZW |
20027 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
20028 | branches, the Windows CE loader *does* expect the relocation | |
20029 | to take this into account. */ | |
20030 | case BFD_RELOC_ARM_OFFSET_IMM: | |
20031 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
20032 | case BFD_RELOC_ARM_HWLITERAL: | |
20033 | case BFD_RELOC_ARM_LITERAL: | |
20034 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
20035 | return base + 8; | |
20036 | ||
20037 | ||
20038 | /* Other PC-relative relocations are un-offset. */ | |
20039 | default: | |
20040 | return base; | |
20041 | } | |
bfae80f2 RE |
20042 | } |
20043 | ||
c19d1205 ZW |
20044 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
20045 | Otherwise we have no need to default values of symbols. */ | |
20046 | ||
20047 | symbolS * | |
20048 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 20049 | { |
c19d1205 ZW |
20050 | #ifdef OBJ_ELF |
20051 | if (name[0] == '_' && name[1] == 'G' | |
20052 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
20053 | { | |
20054 | if (!GOT_symbol) | |
20055 | { | |
20056 | if (symbol_find (name)) | |
bd3ba5d1 | 20057 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 20058 | |
c19d1205 ZW |
20059 | GOT_symbol = symbol_new (name, undefined_section, |
20060 | (valueT) 0, & zero_address_frag); | |
20061 | } | |
bfae80f2 | 20062 | |
c19d1205 | 20063 | return GOT_symbol; |
bfae80f2 | 20064 | } |
c19d1205 | 20065 | #endif |
bfae80f2 | 20066 | |
c921be7d | 20067 | return NULL; |
bfae80f2 RE |
20068 | } |
20069 | ||
55cf6793 | 20070 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
20071 | computed as two separate immediate values, added together. We |
20072 | already know that this value cannot be computed by just one ARM | |
20073 | instruction. */ | |
20074 | ||
20075 | static unsigned int | |
20076 | validate_immediate_twopart (unsigned int val, | |
20077 | unsigned int * highpart) | |
bfae80f2 | 20078 | { |
c19d1205 ZW |
20079 | unsigned int a; |
20080 | unsigned int i; | |
bfae80f2 | 20081 | |
c19d1205 ZW |
20082 | for (i = 0; i < 32; i += 2) |
20083 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
20084 | { | |
20085 | if (a & 0xff00) | |
20086 | { | |
20087 | if (a & ~ 0xffff) | |
20088 | continue; | |
20089 | * highpart = (a >> 8) | ((i + 24) << 7); | |
20090 | } | |
20091 | else if (a & 0xff0000) | |
20092 | { | |
20093 | if (a & 0xff000000) | |
20094 | continue; | |
20095 | * highpart = (a >> 16) | ((i + 16) << 7); | |
20096 | } | |
20097 | else | |
20098 | { | |
9c2799c2 | 20099 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
20100 | * highpart = (a >> 24) | ((i + 8) << 7); |
20101 | } | |
bfae80f2 | 20102 | |
c19d1205 ZW |
20103 | return (a & 0xff) | (i << 7); |
20104 | } | |
bfae80f2 | 20105 | |
c19d1205 | 20106 | return FAIL; |
bfae80f2 RE |
20107 | } |
20108 | ||
c19d1205 ZW |
20109 | static int |
20110 | validate_offset_imm (unsigned int val, int hwse) | |
20111 | { | |
20112 | if ((hwse && val > 255) || val > 4095) | |
20113 | return FAIL; | |
20114 | return val; | |
20115 | } | |
bfae80f2 | 20116 | |
55cf6793 | 20117 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
20118 | negative immediate constant by altering the instruction. A bit of |
20119 | a hack really. | |
20120 | MOV <-> MVN | |
20121 | AND <-> BIC | |
20122 | ADC <-> SBC | |
20123 | by inverting the second operand, and | |
20124 | ADD <-> SUB | |
20125 | CMP <-> CMN | |
20126 | by negating the second operand. */ | |
bfae80f2 | 20127 | |
c19d1205 ZW |
20128 | static int |
20129 | negate_data_op (unsigned long * instruction, | |
20130 | unsigned long value) | |
bfae80f2 | 20131 | { |
c19d1205 ZW |
20132 | int op, new_inst; |
20133 | unsigned long negated, inverted; | |
bfae80f2 | 20134 | |
c19d1205 ZW |
20135 | negated = encode_arm_immediate (-value); |
20136 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 20137 | |
c19d1205 ZW |
20138 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
20139 | switch (op) | |
bfae80f2 | 20140 | { |
c19d1205 ZW |
20141 | /* First negates. */ |
20142 | case OPCODE_SUB: /* ADD <-> SUB */ | |
20143 | new_inst = OPCODE_ADD; | |
20144 | value = negated; | |
20145 | break; | |
bfae80f2 | 20146 | |
c19d1205 ZW |
20147 | case OPCODE_ADD: |
20148 | new_inst = OPCODE_SUB; | |
20149 | value = negated; | |
20150 | break; | |
bfae80f2 | 20151 | |
c19d1205 ZW |
20152 | case OPCODE_CMP: /* CMP <-> CMN */ |
20153 | new_inst = OPCODE_CMN; | |
20154 | value = negated; | |
20155 | break; | |
bfae80f2 | 20156 | |
c19d1205 ZW |
20157 | case OPCODE_CMN: |
20158 | new_inst = OPCODE_CMP; | |
20159 | value = negated; | |
20160 | break; | |
bfae80f2 | 20161 | |
c19d1205 ZW |
20162 | /* Now Inverted ops. */ |
20163 | case OPCODE_MOV: /* MOV <-> MVN */ | |
20164 | new_inst = OPCODE_MVN; | |
20165 | value = inverted; | |
20166 | break; | |
bfae80f2 | 20167 | |
c19d1205 ZW |
20168 | case OPCODE_MVN: |
20169 | new_inst = OPCODE_MOV; | |
20170 | value = inverted; | |
20171 | break; | |
bfae80f2 | 20172 | |
c19d1205 ZW |
20173 | case OPCODE_AND: /* AND <-> BIC */ |
20174 | new_inst = OPCODE_BIC; | |
20175 | value = inverted; | |
20176 | break; | |
bfae80f2 | 20177 | |
c19d1205 ZW |
20178 | case OPCODE_BIC: |
20179 | new_inst = OPCODE_AND; | |
20180 | value = inverted; | |
20181 | break; | |
bfae80f2 | 20182 | |
c19d1205 ZW |
20183 | case OPCODE_ADC: /* ADC <-> SBC */ |
20184 | new_inst = OPCODE_SBC; | |
20185 | value = inverted; | |
20186 | break; | |
bfae80f2 | 20187 | |
c19d1205 ZW |
20188 | case OPCODE_SBC: |
20189 | new_inst = OPCODE_ADC; | |
20190 | value = inverted; | |
20191 | break; | |
bfae80f2 | 20192 | |
c19d1205 ZW |
20193 | /* We cannot do anything. */ |
20194 | default: | |
20195 | return FAIL; | |
b99bd4ef NC |
20196 | } |
20197 | ||
c19d1205 ZW |
20198 | if (value == (unsigned) FAIL) |
20199 | return FAIL; | |
20200 | ||
20201 | *instruction &= OPCODE_MASK; | |
20202 | *instruction |= new_inst << DATA_OP_SHIFT; | |
20203 | return value; | |
b99bd4ef NC |
20204 | } |
20205 | ||
ef8d22e6 PB |
20206 | /* Like negate_data_op, but for Thumb-2. */ |
20207 | ||
20208 | static unsigned int | |
16dd5e42 | 20209 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
20210 | { |
20211 | int op, new_inst; | |
20212 | int rd; | |
16dd5e42 | 20213 | unsigned int negated, inverted; |
ef8d22e6 PB |
20214 | |
20215 | negated = encode_thumb32_immediate (-value); | |
20216 | inverted = encode_thumb32_immediate (~value); | |
20217 | ||
20218 | rd = (*instruction >> 8) & 0xf; | |
20219 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
20220 | switch (op) | |
20221 | { | |
20222 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
20223 | case T2_OPCODE_SUB: | |
20224 | new_inst = T2_OPCODE_ADD; | |
20225 | value = negated; | |
20226 | break; | |
20227 | ||
20228 | case T2_OPCODE_ADD: | |
20229 | new_inst = T2_OPCODE_SUB; | |
20230 | value = negated; | |
20231 | break; | |
20232 | ||
20233 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
20234 | case T2_OPCODE_ORR: | |
20235 | new_inst = T2_OPCODE_ORN; | |
20236 | value = inverted; | |
20237 | break; | |
20238 | ||
20239 | case T2_OPCODE_ORN: | |
20240 | new_inst = T2_OPCODE_ORR; | |
20241 | value = inverted; | |
20242 | break; | |
20243 | ||
20244 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
20245 | case T2_OPCODE_AND: | |
20246 | new_inst = T2_OPCODE_BIC; | |
20247 | if (rd == 15) | |
20248 | value = FAIL; | |
20249 | else | |
20250 | value = inverted; | |
20251 | break; | |
20252 | ||
20253 | case T2_OPCODE_BIC: | |
20254 | new_inst = T2_OPCODE_AND; | |
20255 | value = inverted; | |
20256 | break; | |
20257 | ||
20258 | /* ADC <-> SBC */ | |
20259 | case T2_OPCODE_ADC: | |
20260 | new_inst = T2_OPCODE_SBC; | |
20261 | value = inverted; | |
20262 | break; | |
20263 | ||
20264 | case T2_OPCODE_SBC: | |
20265 | new_inst = T2_OPCODE_ADC; | |
20266 | value = inverted; | |
20267 | break; | |
20268 | ||
20269 | /* We cannot do anything. */ | |
20270 | default: | |
20271 | return FAIL; | |
20272 | } | |
20273 | ||
16dd5e42 | 20274 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
20275 | return FAIL; |
20276 | ||
20277 | *instruction &= T2_OPCODE_MASK; | |
20278 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
20279 | return value; | |
20280 | } | |
20281 | ||
8f06b2d8 PB |
20282 | /* Read a 32-bit thumb instruction from buf. */ |
20283 | static unsigned long | |
20284 | get_thumb32_insn (char * buf) | |
20285 | { | |
20286 | unsigned long insn; | |
20287 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
20288 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20289 | ||
20290 | return insn; | |
20291 | } | |
20292 | ||
a8bc6c78 PB |
20293 | |
20294 | /* We usually want to set the low bit on the address of thumb function | |
20295 | symbols. In particular .word foo - . should have the low bit set. | |
20296 | Generic code tries to fold the difference of two symbols to | |
20297 | a constant. Prevent this and force a relocation when the first symbols | |
20298 | is a thumb function. */ | |
c921be7d NC |
20299 | |
20300 | bfd_boolean | |
a8bc6c78 PB |
20301 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
20302 | { | |
20303 | if (op == O_subtract | |
20304 | && l->X_op == O_symbol | |
20305 | && r->X_op == O_symbol | |
20306 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
20307 | { | |
20308 | l->X_op = O_subtract; | |
20309 | l->X_op_symbol = r->X_add_symbol; | |
20310 | l->X_add_number -= r->X_add_number; | |
c921be7d | 20311 | return TRUE; |
a8bc6c78 | 20312 | } |
c921be7d | 20313 | |
a8bc6c78 | 20314 | /* Process as normal. */ |
c921be7d | 20315 | return FALSE; |
a8bc6c78 PB |
20316 | } |
20317 | ||
4a42ebbc RR |
20318 | /* Encode Thumb2 unconditional branches and calls. The encoding |
20319 | for the 2 are identical for the immediate values. */ | |
20320 | ||
20321 | static void | |
20322 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
20323 | { | |
20324 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
20325 | offsetT newval; | |
20326 | offsetT newval2; | |
20327 | addressT S, I1, I2, lo, hi; | |
20328 | ||
20329 | S = (value >> 24) & 0x01; | |
20330 | I1 = (value >> 23) & 0x01; | |
20331 | I2 = (value >> 22) & 0x01; | |
20332 | hi = (value >> 12) & 0x3ff; | |
20333 | lo = (value >> 1) & 0x7ff; | |
20334 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20335 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20336 | newval |= (S << 10) | hi; | |
20337 | newval2 &= ~T2I1I2MASK; | |
20338 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
20339 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20340 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
20341 | } | |
20342 | ||
c19d1205 | 20343 | void |
55cf6793 | 20344 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
20345 | valueT * valP, |
20346 | segT seg) | |
20347 | { | |
20348 | offsetT value = * valP; | |
20349 | offsetT newval; | |
20350 | unsigned int newimm; | |
20351 | unsigned long temp; | |
20352 | int sign; | |
20353 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 20354 | |
9c2799c2 | 20355 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 20356 | |
c19d1205 | 20357 | /* Note whether this will delete the relocation. */ |
4962c51a | 20358 | |
c19d1205 ZW |
20359 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
20360 | fixP->fx_done = 1; | |
b99bd4ef | 20361 | |
adbaf948 | 20362 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 20363 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
20364 | for emit_reloc. */ |
20365 | value &= 0xffffffff; | |
20366 | value ^= 0x80000000; | |
5f4273c7 | 20367 | value -= 0x80000000; |
adbaf948 ZW |
20368 | |
20369 | *valP = value; | |
c19d1205 | 20370 | fixP->fx_addnumber = value; |
b99bd4ef | 20371 | |
adbaf948 ZW |
20372 | /* Same treatment for fixP->fx_offset. */ |
20373 | fixP->fx_offset &= 0xffffffff; | |
20374 | fixP->fx_offset ^= 0x80000000; | |
20375 | fixP->fx_offset -= 0x80000000; | |
20376 | ||
c19d1205 | 20377 | switch (fixP->fx_r_type) |
b99bd4ef | 20378 | { |
c19d1205 ZW |
20379 | case BFD_RELOC_NONE: |
20380 | /* This will need to go in the object file. */ | |
20381 | fixP->fx_done = 0; | |
20382 | break; | |
b99bd4ef | 20383 | |
c19d1205 ZW |
20384 | case BFD_RELOC_ARM_IMMEDIATE: |
20385 | /* We claim that this fixup has been processed here, | |
20386 | even if in fact we generate an error because we do | |
20387 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20388 | fixP->fx_done = 1; | |
b99bd4ef | 20389 | |
77db8e2e | 20390 | if (fixP->fx_addsy) |
b99bd4ef | 20391 | { |
77db8e2e | 20392 | const char *msg = 0; |
b99bd4ef | 20393 | |
77db8e2e NC |
20394 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
20395 | msg = _("undefined symbol %s used as an immediate value"); | |
20396 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
20397 | msg = _("symbol %s is in a different section"); | |
20398 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
20399 | msg = _("symbol %s is weak and may be overridden later"); | |
20400 | ||
20401 | if (msg) | |
20402 | { | |
20403 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20404 | msg, S_GET_NAME (fixP->fx_addsy)); | |
20405 | break; | |
20406 | } | |
42e5fcbf AS |
20407 | } |
20408 | ||
c19d1205 ZW |
20409 | newimm = encode_arm_immediate (value); |
20410 | temp = md_chars_to_number (buf, INSN_SIZE); | |
20411 | ||
20412 | /* If the instruction will fail, see if we can fix things up by | |
20413 | changing the opcode. */ | |
20414 | if (newimm == (unsigned int) FAIL | |
20415 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 20416 | { |
c19d1205 ZW |
20417 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20418 | _("invalid constant (%lx) after fixup"), | |
20419 | (unsigned long) value); | |
20420 | break; | |
b99bd4ef | 20421 | } |
b99bd4ef | 20422 | |
c19d1205 ZW |
20423 | newimm |= (temp & 0xfffff000); |
20424 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
20425 | break; | |
b99bd4ef | 20426 | |
c19d1205 ZW |
20427 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
20428 | { | |
20429 | unsigned int highpart = 0; | |
20430 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 20431 | |
77db8e2e | 20432 | if (fixP->fx_addsy) |
42e5fcbf | 20433 | { |
77db8e2e | 20434 | const char *msg = 0; |
42e5fcbf | 20435 | |
77db8e2e NC |
20436 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
20437 | msg = _("undefined symbol %s used as an immediate value"); | |
20438 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
20439 | msg = _("symbol %s is in a different section"); | |
20440 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
20441 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 20442 | |
77db8e2e NC |
20443 | if (msg) |
20444 | { | |
20445 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20446 | msg, S_GET_NAME (fixP->fx_addsy)); | |
20447 | break; | |
20448 | } | |
20449 | } | |
20450 | ||
c19d1205 ZW |
20451 | newimm = encode_arm_immediate (value); |
20452 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 20453 | |
c19d1205 ZW |
20454 | /* If the instruction will fail, see if we can fix things up by |
20455 | changing the opcode. */ | |
20456 | if (newimm == (unsigned int) FAIL | |
20457 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
20458 | { | |
20459 | /* No ? OK - try using two ADD instructions to generate | |
20460 | the value. */ | |
20461 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 20462 | |
c19d1205 ZW |
20463 | /* Yes - then make sure that the second instruction is |
20464 | also an add. */ | |
20465 | if (newimm != (unsigned int) FAIL) | |
20466 | newinsn = temp; | |
20467 | /* Still No ? Try using a negated value. */ | |
20468 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
20469 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
20470 | /* Otherwise - give up. */ | |
20471 | else | |
20472 | { | |
20473 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20474 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
20475 | (long) value); | |
20476 | break; | |
20477 | } | |
b99bd4ef | 20478 | |
c19d1205 ZW |
20479 | /* Replace the first operand in the 2nd instruction (which |
20480 | is the PC) with the destination register. We have | |
20481 | already added in the PC in the first instruction and we | |
20482 | do not want to do it again. */ | |
20483 | newinsn &= ~ 0xf0000; | |
20484 | newinsn |= ((newinsn & 0x0f000) << 4); | |
20485 | } | |
b99bd4ef | 20486 | |
c19d1205 ZW |
20487 | newimm |= (temp & 0xfffff000); |
20488 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 20489 | |
c19d1205 ZW |
20490 | highpart |= (newinsn & 0xfffff000); |
20491 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
20492 | } | |
20493 | break; | |
b99bd4ef | 20494 | |
c19d1205 | 20495 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
20496 | if (!fixP->fx_done && seg->use_rela_p) |
20497 | value = 0; | |
20498 | ||
c19d1205 | 20499 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 20500 | sign = value > 0; |
b99bd4ef | 20501 | |
c19d1205 ZW |
20502 | if (value < 0) |
20503 | value = - value; | |
b99bd4ef | 20504 | |
c19d1205 | 20505 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 20506 | { |
c19d1205 ZW |
20507 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
20508 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20509 | _("invalid literal constant: pool needs to be closer")); | |
20510 | else | |
20511 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20512 | _("bad immediate value for offset (%ld)"), | |
20513 | (long) value); | |
20514 | break; | |
f03698e6 RE |
20515 | } |
20516 | ||
c19d1205 | 20517 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
20518 | if (value == 0) |
20519 | newval &= 0xfffff000; | |
20520 | else | |
20521 | { | |
20522 | newval &= 0xff7ff000; | |
20523 | newval |= value | (sign ? INDEX_UP : 0); | |
20524 | } | |
c19d1205 ZW |
20525 | md_number_to_chars (buf, newval, INSN_SIZE); |
20526 | break; | |
b99bd4ef | 20527 | |
c19d1205 ZW |
20528 | case BFD_RELOC_ARM_OFFSET_IMM8: |
20529 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 20530 | sign = value > 0; |
b99bd4ef | 20531 | |
c19d1205 ZW |
20532 | if (value < 0) |
20533 | value = - value; | |
b99bd4ef | 20534 | |
c19d1205 | 20535 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 20536 | { |
c19d1205 ZW |
20537 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
20538 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20539 | _("invalid literal constant: pool needs to be closer")); | |
20540 | else | |
f9d4405b | 20541 | as_bad (_("bad immediate value for 8-bit offset (%ld)"), |
c19d1205 ZW |
20542 | (long) value); |
20543 | break; | |
b99bd4ef NC |
20544 | } |
20545 | ||
c19d1205 | 20546 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
20547 | if (value == 0) |
20548 | newval &= 0xfffff0f0; | |
20549 | else | |
20550 | { | |
20551 | newval &= 0xff7ff0f0; | |
20552 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
20553 | } | |
c19d1205 ZW |
20554 | md_number_to_chars (buf, newval, INSN_SIZE); |
20555 | break; | |
b99bd4ef | 20556 | |
c19d1205 ZW |
20557 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
20558 | if (value < 0 || value > 1020 || value % 4 != 0) | |
20559 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20560 | _("bad immediate value for offset (%ld)"), (long) value); | |
20561 | value /= 4; | |
b99bd4ef | 20562 | |
c19d1205 | 20563 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
20564 | newval |= value; |
20565 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
20566 | break; | |
b99bd4ef | 20567 | |
c19d1205 ZW |
20568 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
20569 | /* This is a complicated relocation used for all varieties of Thumb32 | |
20570 | load/store instruction with immediate offset: | |
20571 | ||
20572 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
20573 | *4, optional writeback(W) | |
20574 | (doubleword load/store) | |
20575 | ||
20576 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
20577 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
20578 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
20579 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
20580 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
20581 | ||
20582 | Uppercase letters indicate bits that are already encoded at | |
20583 | this point. Lowercase letters are our problem. For the | |
20584 | second block of instructions, the secondary opcode nybble | |
20585 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
20586 | a PC-relative operation. */ | |
20587 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20588 | newval <<= 16; | |
20589 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 20590 | |
c19d1205 | 20591 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 20592 | { |
c19d1205 ZW |
20593 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
20594 | if (value >= 0) | |
20595 | newval |= (1 << 23); | |
20596 | else | |
20597 | value = -value; | |
20598 | if (value % 4 != 0) | |
20599 | { | |
20600 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20601 | _("offset not a multiple of 4")); | |
20602 | break; | |
20603 | } | |
20604 | value /= 4; | |
216d22bc | 20605 | if (value > 0xff) |
c19d1205 ZW |
20606 | { |
20607 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20608 | _("offset out of range")); | |
20609 | break; | |
20610 | } | |
20611 | newval &= ~0xff; | |
b99bd4ef | 20612 | } |
c19d1205 | 20613 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 20614 | { |
c19d1205 ZW |
20615 | /* PC-relative, 12-bit offset. */ |
20616 | if (value >= 0) | |
20617 | newval |= (1 << 23); | |
20618 | else | |
20619 | value = -value; | |
216d22bc | 20620 | if (value > 0xfff) |
c19d1205 ZW |
20621 | { |
20622 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20623 | _("offset out of range")); | |
20624 | break; | |
20625 | } | |
20626 | newval &= ~0xfff; | |
b99bd4ef | 20627 | } |
c19d1205 | 20628 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 20629 | { |
c19d1205 ZW |
20630 | /* Writeback: 8-bit, +/- offset. */ |
20631 | if (value >= 0) | |
20632 | newval |= (1 << 9); | |
20633 | else | |
20634 | value = -value; | |
216d22bc | 20635 | if (value > 0xff) |
c19d1205 ZW |
20636 | { |
20637 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20638 | _("offset out of range")); | |
20639 | break; | |
20640 | } | |
20641 | newval &= ~0xff; | |
b99bd4ef | 20642 | } |
c19d1205 | 20643 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 20644 | { |
c19d1205 | 20645 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 20646 | if (value < 0 || value > 0xff) |
b99bd4ef | 20647 | { |
c19d1205 ZW |
20648 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20649 | _("offset out of range")); | |
20650 | break; | |
b99bd4ef | 20651 | } |
c19d1205 ZW |
20652 | newval &= ~0xff; |
20653 | newval |= value; | |
b99bd4ef NC |
20654 | } |
20655 | else | |
b99bd4ef | 20656 | { |
c19d1205 ZW |
20657 | /* Positive 12-bit or negative 8-bit offset. */ |
20658 | int limit; | |
20659 | if (value >= 0) | |
b99bd4ef | 20660 | { |
c19d1205 ZW |
20661 | newval |= (1 << 23); |
20662 | limit = 0xfff; | |
20663 | } | |
20664 | else | |
20665 | { | |
20666 | value = -value; | |
20667 | limit = 0xff; | |
20668 | } | |
20669 | if (value > limit) | |
20670 | { | |
20671 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20672 | _("offset out of range")); | |
20673 | break; | |
b99bd4ef | 20674 | } |
c19d1205 | 20675 | newval &= ~limit; |
b99bd4ef | 20676 | } |
b99bd4ef | 20677 | |
c19d1205 ZW |
20678 | newval |= value; |
20679 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
20680 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
20681 | break; | |
404ff6b5 | 20682 | |
c19d1205 ZW |
20683 | case BFD_RELOC_ARM_SHIFT_IMM: |
20684 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20685 | if (((unsigned long) value) > 32 | |
20686 | || (value == 32 | |
20687 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
20688 | { | |
20689 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20690 | _("shift expression is too large")); | |
20691 | break; | |
20692 | } | |
404ff6b5 | 20693 | |
c19d1205 ZW |
20694 | if (value == 0) |
20695 | /* Shifts of zero must be done as lsl. */ | |
20696 | newval &= ~0x60; | |
20697 | else if (value == 32) | |
20698 | value = 0; | |
20699 | newval &= 0xfffff07f; | |
20700 | newval |= (value & 0x1f) << 7; | |
20701 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20702 | break; | |
404ff6b5 | 20703 | |
c19d1205 | 20704 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 20705 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 20706 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 20707 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
20708 | /* We claim that this fixup has been processed here, |
20709 | even if in fact we generate an error because we do | |
20710 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20711 | fixP->fx_done = 1; | |
404ff6b5 | 20712 | |
c19d1205 ZW |
20713 | if (fixP->fx_addsy |
20714 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
20715 | { | |
20716 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20717 | _("undefined symbol %s used as an immediate value"), | |
20718 | S_GET_NAME (fixP->fx_addsy)); | |
20719 | break; | |
20720 | } | |
404ff6b5 | 20721 | |
c19d1205 ZW |
20722 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20723 | newval <<= 16; | |
20724 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 20725 | |
16805f35 PB |
20726 | newimm = FAIL; |
20727 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
20728 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
20729 | { |
20730 | newimm = encode_thumb32_immediate (value); | |
20731 | if (newimm == (unsigned int) FAIL) | |
20732 | newimm = thumb32_negate_data_op (&newval, value); | |
20733 | } | |
16805f35 PB |
20734 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
20735 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 20736 | { |
16805f35 PB |
20737 | /* Turn add/sum into addw/subw. */ |
20738 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
20739 | newval = (newval & 0xfeffffff) | 0x02000000; | |
40f246e3 NC |
20740 | /* No flat 12-bit imm encoding for addsw/subsw. */ |
20741 | if ((newval & 0x00100000) == 0) | |
e9f89963 | 20742 | { |
40f246e3 NC |
20743 | /* 12 bit immediate for addw/subw. */ |
20744 | if (value < 0) | |
20745 | { | |
20746 | value = -value; | |
20747 | newval ^= 0x00a00000; | |
20748 | } | |
20749 | if (value > 0xfff) | |
20750 | newimm = (unsigned int) FAIL; | |
20751 | else | |
20752 | newimm = value; | |
e9f89963 | 20753 | } |
92e90b6e | 20754 | } |
cc8a6dd0 | 20755 | |
c19d1205 | 20756 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 20757 | { |
c19d1205 ZW |
20758 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20759 | _("invalid constant (%lx) after fixup"), | |
20760 | (unsigned long) value); | |
20761 | break; | |
3631a3c8 NC |
20762 | } |
20763 | ||
c19d1205 ZW |
20764 | newval |= (newimm & 0x800) << 15; |
20765 | newval |= (newimm & 0x700) << 4; | |
20766 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 20767 | |
c19d1205 ZW |
20768 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
20769 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
20770 | break; | |
a737bd4d | 20771 | |
3eb17e6b | 20772 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
20773 | if (((unsigned long) value) > 0xffff) |
20774 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 20775 | _("invalid smc expression")); |
2fc8bdac | 20776 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20777 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
20778 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20779 | break; | |
a737bd4d | 20780 | |
90ec0d68 MGD |
20781 | case BFD_RELOC_ARM_HVC: |
20782 | if (((unsigned long) value) > 0xffff) | |
20783 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20784 | _("invalid hvc expression")); | |
20785 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20786 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
20787 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20788 | break; | |
20789 | ||
c19d1205 | 20790 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 20791 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
20792 | { |
20793 | if (((unsigned long) value) > 0xff) | |
20794 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20795 | _("invalid swi expression")); | |
2fc8bdac | 20796 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
20797 | newval |= value; |
20798 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20799 | } | |
20800 | else | |
20801 | { | |
20802 | if (((unsigned long) value) > 0x00ffffff) | |
20803 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20804 | _("invalid swi expression")); | |
2fc8bdac | 20805 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20806 | newval |= value; |
20807 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20808 | } | |
20809 | break; | |
a737bd4d | 20810 | |
c19d1205 ZW |
20811 | case BFD_RELOC_ARM_MULTI: |
20812 | if (((unsigned long) value) > 0xffff) | |
20813 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20814 | _("invalid expression in load/store multiple")); | |
20815 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
20816 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20817 | break; | |
a737bd4d | 20818 | |
c19d1205 | 20819 | #ifdef OBJ_ELF |
39b41c9c | 20820 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
20821 | |
20822 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
20823 | && fixP->fx_addsy | |
34e77a92 | 20824 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20825 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
20826 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20827 | /* Flip the bl to blx. This is a simple flip | |
20828 | bit here because we generate PCREL_CALL for | |
20829 | unconditional bls. */ | |
20830 | { | |
20831 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20832 | newval = newval | 0x10000000; | |
20833 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20834 | temp = 1; | |
20835 | fixP->fx_done = 1; | |
20836 | } | |
39b41c9c PB |
20837 | else |
20838 | temp = 3; | |
20839 | goto arm_branch_common; | |
20840 | ||
20841 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
20842 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20843 | && fixP->fx_addsy | |
34e77a92 | 20844 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20845 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
20846 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20847 | { | |
20848 | /* This would map to a bl<cond>, b<cond>, | |
20849 | b<always> to a Thumb function. We | |
20850 | need to force a relocation for this particular | |
20851 | case. */ | |
20852 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20853 | fixP->fx_done = 0; | |
20854 | } | |
20855 | ||
2fc8bdac | 20856 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 20857 | #endif |
39b41c9c PB |
20858 | case BFD_RELOC_ARM_PCREL_BRANCH: |
20859 | temp = 3; | |
20860 | goto arm_branch_common; | |
a737bd4d | 20861 | |
39b41c9c | 20862 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 20863 | |
39b41c9c | 20864 | temp = 1; |
267bf995 RR |
20865 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20866 | && fixP->fx_addsy | |
34e77a92 | 20867 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20868 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
20869 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
20870 | { | |
20871 | /* Flip the blx to a bl and warn. */ | |
20872 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
20873 | newval = 0xeb000000; | |
20874 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
20875 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
20876 | name); | |
20877 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20878 | temp = 3; | |
20879 | fixP->fx_done = 1; | |
20880 | } | |
20881 | ||
20882 | #ifdef OBJ_ELF | |
20883 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
20884 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; | |
20885 | #endif | |
20886 | ||
39b41c9c | 20887 | arm_branch_common: |
c19d1205 | 20888 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
20889 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
20890 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
20891 | also be be clear. */ | |
20892 | if (value & temp) | |
c19d1205 | 20893 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
20894 | _("misaligned branch destination")); |
20895 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
20896 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
20897 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20898 | _("branch out of range")); | |
a737bd4d | 20899 | |
2fc8bdac | 20900 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 20901 | { |
2fc8bdac ZW |
20902 | newval = md_chars_to_number (buf, INSN_SIZE); |
20903 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
20904 | /* Set the H bit on BLX instructions. */ |
20905 | if (temp == 1) | |
20906 | { | |
20907 | if (value & 2) | |
20908 | newval |= 0x01000000; | |
20909 | else | |
20910 | newval &= ~0x01000000; | |
20911 | } | |
2fc8bdac | 20912 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 20913 | } |
c19d1205 | 20914 | break; |
a737bd4d | 20915 | |
25fe350b MS |
20916 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
20917 | /* CBZ can only branch forward. */ | |
a737bd4d | 20918 | |
738755b0 MS |
20919 | /* Attempts to use CBZ to branch to the next instruction |
20920 | (which, strictly speaking, are prohibited) will be turned into | |
20921 | no-ops. | |
20922 | ||
20923 | FIXME: It may be better to remove the instruction completely and | |
20924 | perform relaxation. */ | |
20925 | if (value == -2) | |
2fc8bdac ZW |
20926 | { |
20927 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 20928 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
20929 | md_number_to_chars (buf, newval, THUMB_SIZE); |
20930 | } | |
738755b0 MS |
20931 | else |
20932 | { | |
20933 | if (value & ~0x7e) | |
20934 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20935 | _("branch out of range")); | |
20936 | ||
20937 | if (fixP->fx_done || !seg->use_rela_p) | |
20938 | { | |
20939 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20940 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
20941 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20942 | } | |
20943 | } | |
c19d1205 | 20944 | break; |
a737bd4d | 20945 | |
c19d1205 | 20946 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac ZW |
20947 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
20948 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20949 | _("branch out of range")); | |
a737bd4d | 20950 | |
2fc8bdac ZW |
20951 | if (fixP->fx_done || !seg->use_rela_p) |
20952 | { | |
20953 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20954 | newval |= (value & 0x1ff) >> 1; | |
20955 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20956 | } | |
c19d1205 | 20957 | break; |
a737bd4d | 20958 | |
c19d1205 | 20959 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac ZW |
20960 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
20961 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20962 | _("branch out of range")); | |
a737bd4d | 20963 | |
2fc8bdac ZW |
20964 | if (fixP->fx_done || !seg->use_rela_p) |
20965 | { | |
20966 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20967 | newval |= (value & 0xfff) >> 1; | |
20968 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20969 | } | |
c19d1205 | 20970 | break; |
a737bd4d | 20971 | |
c19d1205 | 20972 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
20973 | if (fixP->fx_addsy |
20974 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20975 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20976 | && ARM_IS_FUNC (fixP->fx_addsy) |
20977 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20978 | { | |
20979 | /* Force a relocation for a branch 20 bits wide. */ | |
20980 | fixP->fx_done = 0; | |
20981 | } | |
2fc8bdac ZW |
20982 | if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) |
20983 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20984 | _("conditional branch out of range")); | |
404ff6b5 | 20985 | |
2fc8bdac ZW |
20986 | if (fixP->fx_done || !seg->use_rela_p) |
20987 | { | |
20988 | offsetT newval2; | |
20989 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 20990 | |
2fc8bdac ZW |
20991 | S = (value & 0x00100000) >> 20; |
20992 | J2 = (value & 0x00080000) >> 19; | |
20993 | J1 = (value & 0x00040000) >> 18; | |
20994 | hi = (value & 0x0003f000) >> 12; | |
20995 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 20996 | |
2fc8bdac ZW |
20997 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20998 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20999 | newval |= (S << 10) | hi; | |
21000 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
21001 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21002 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
21003 | } | |
c19d1205 | 21004 | break; |
6c43fab6 | 21005 | |
c19d1205 | 21006 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
21007 | |
21008 | /* If there is a blx from a thumb state function to | |
21009 | another thumb function flip this to a bl and warn | |
21010 | about it. */ | |
21011 | ||
21012 | if (fixP->fx_addsy | |
34e77a92 | 21013 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21014 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21015 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
21016 | { | |
21017 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
21018 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
21019 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
21020 | name); | |
21021 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21022 | newval = newval | 0x1000; | |
21023 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
21024 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21025 | fixP->fx_done = 1; | |
21026 | } | |
21027 | ||
21028 | ||
21029 | goto thumb_bl_common; | |
21030 | ||
c19d1205 | 21031 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
21032 | |
21033 | /* A bl from Thumb state ISA to an internal ARM state function | |
21034 | is converted to a blx. */ | |
21035 | if (fixP->fx_addsy | |
21036 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21037 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21038 | && ARM_IS_FUNC (fixP->fx_addsy) |
21039 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21040 | { | |
21041 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21042 | newval = newval & ~0x1000; | |
21043 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
21044 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
21045 | fixP->fx_done = 1; | |
21046 | } | |
21047 | ||
21048 | thumb_bl_common: | |
21049 | ||
21050 | #ifdef OBJ_ELF | |
21051 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 && | |
21052 | fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
21053 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21054 | #endif | |
21055 | ||
2fc8bdac ZW |
21056 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
21057 | /* For a BLX instruction, make sure that the relocation is rounded up | |
21058 | to a word boundary. This follows the semantics of the instruction | |
21059 | which specifies that bit 1 of the target address will come from bit | |
21060 | 1 of the base address. */ | |
21061 | value = (value + 1) & ~ 1; | |
404ff6b5 | 21062 | |
2fc8bdac | 21063 | |
4a42ebbc RR |
21064 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
21065 | { | |
21066 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
21067 | { | |
21068 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21069 | _("branch out of range")); | |
21070 | } | |
21071 | else if ((value & ~0x1ffffff) | |
21072 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
21073 | { | |
21074 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21075 | _("Thumb2 branch out of range")); | |
21076 | } | |
c19d1205 | 21077 | } |
4a42ebbc RR |
21078 | |
21079 | if (fixP->fx_done || !seg->use_rela_p) | |
21080 | encode_thumb2_b_bl_offset (buf, value); | |
21081 | ||
c19d1205 | 21082 | break; |
404ff6b5 | 21083 | |
c19d1205 | 21084 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac ZW |
21085 | if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) |
21086 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21087 | _("branch out of range")); | |
6c43fab6 | 21088 | |
2fc8bdac | 21089 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 21090 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 21091 | |
2fc8bdac | 21092 | break; |
a737bd4d | 21093 | |
2fc8bdac ZW |
21094 | case BFD_RELOC_8: |
21095 | if (fixP->fx_done || !seg->use_rela_p) | |
21096 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 21097 | break; |
a737bd4d | 21098 | |
c19d1205 | 21099 | case BFD_RELOC_16: |
2fc8bdac | 21100 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 21101 | md_number_to_chars (buf, value, 2); |
c19d1205 | 21102 | break; |
a737bd4d | 21103 | |
c19d1205 | 21104 | #ifdef OBJ_ELF |
0855e32b NS |
21105 | case BFD_RELOC_ARM_TLS_CALL: |
21106 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
21107 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
21108 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
21109 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
21110 | break; | |
21111 | ||
21112 | case BFD_RELOC_ARM_TLS_GOTDESC: | |
c19d1205 ZW |
21113 | case BFD_RELOC_ARM_TLS_GD32: |
21114 | case BFD_RELOC_ARM_TLS_LE32: | |
21115 | case BFD_RELOC_ARM_TLS_IE32: | |
21116 | case BFD_RELOC_ARM_TLS_LDM32: | |
21117 | case BFD_RELOC_ARM_TLS_LDO32: | |
21118 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
21119 | /* fall through */ | |
6c43fab6 | 21120 | |
c19d1205 ZW |
21121 | case BFD_RELOC_ARM_GOT32: |
21122 | case BFD_RELOC_ARM_GOTOFF: | |
2fc8bdac ZW |
21123 | if (fixP->fx_done || !seg->use_rela_p) |
21124 | md_number_to_chars (buf, 0, 4); | |
c19d1205 | 21125 | break; |
b43420e6 NC |
21126 | |
21127 | case BFD_RELOC_ARM_GOT_PREL: | |
21128 | if (fixP->fx_done || !seg->use_rela_p) | |
21129 | md_number_to_chars (buf, value, 4); | |
21130 | break; | |
21131 | ||
9a6f4e97 NS |
21132 | case BFD_RELOC_ARM_TARGET2: |
21133 | /* TARGET2 is not partial-inplace, so we need to write the | |
21134 | addend here for REL targets, because it won't be written out | |
21135 | during reloc processing later. */ | |
21136 | if (fixP->fx_done || !seg->use_rela_p) | |
21137 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
21138 | break; | |
c19d1205 | 21139 | #endif |
6c43fab6 | 21140 | |
c19d1205 ZW |
21141 | case BFD_RELOC_RVA: |
21142 | case BFD_RELOC_32: | |
21143 | case BFD_RELOC_ARM_TARGET1: | |
21144 | case BFD_RELOC_ARM_ROSEGREL32: | |
21145 | case BFD_RELOC_ARM_SBREL32: | |
21146 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
21147 | #ifdef TE_PE |
21148 | case BFD_RELOC_32_SECREL: | |
21149 | #endif | |
2fc8bdac | 21150 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
21151 | #ifdef TE_WINCE |
21152 | /* For WinCE we only do this for pcrel fixups. */ | |
21153 | if (fixP->fx_done || fixP->fx_pcrel) | |
21154 | #endif | |
21155 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 21156 | break; |
6c43fab6 | 21157 | |
c19d1205 ZW |
21158 | #ifdef OBJ_ELF |
21159 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 21160 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
21161 | { |
21162 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
21163 | if ((value ^ (value >> 1)) & 0x40000000) | |
21164 | { | |
21165 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21166 | _("rel31 relocation overflow")); | |
21167 | } | |
21168 | newval |= value & 0x7fffffff; | |
21169 | md_number_to_chars (buf, newval, 4); | |
21170 | } | |
21171 | break; | |
c19d1205 | 21172 | #endif |
a737bd4d | 21173 | |
c19d1205 | 21174 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 21175 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
21176 | if (value < -1023 || value > 1023 || (value & 3)) |
21177 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21178 | _("co-processor offset out of range")); | |
21179 | cp_off_common: | |
26d97720 | 21180 | sign = value > 0; |
c19d1205 ZW |
21181 | if (value < 0) |
21182 | value = -value; | |
8f06b2d8 PB |
21183 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21184 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
21185 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21186 | else | |
21187 | newval = get_thumb32_insn (buf); | |
26d97720 NS |
21188 | if (value == 0) |
21189 | newval &= 0xffffff00; | |
21190 | else | |
21191 | { | |
21192 | newval &= 0xff7fff00; | |
21193 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); | |
21194 | } | |
8f06b2d8 PB |
21195 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21196 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
21197 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21198 | else | |
21199 | put_thumb32_insn (buf, newval); | |
c19d1205 | 21200 | break; |
a737bd4d | 21201 | |
c19d1205 | 21202 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 21203 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
21204 | if (value < -255 || value > 255) |
21205 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21206 | _("co-processor offset out of range")); | |
df7849c5 | 21207 | value *= 4; |
c19d1205 | 21208 | goto cp_off_common; |
6c43fab6 | 21209 | |
c19d1205 ZW |
21210 | case BFD_RELOC_ARM_THUMB_OFFSET: |
21211 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21212 | /* Exactly what ranges, and where the offset is inserted depends | |
21213 | on the type of instruction, we can establish this from the | |
21214 | top 4 bits. */ | |
21215 | switch (newval >> 12) | |
21216 | { | |
21217 | case 4: /* PC load. */ | |
21218 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
21219 | forced to zero for these loads; md_pcrel_from has already | |
21220 | compensated for this. */ | |
21221 | if (value & 3) | |
21222 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21223 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
21224 | (((unsigned long) fixP->fx_frag->fr_address |
21225 | + (unsigned long) fixP->fx_where) & ~3) | |
21226 | + (unsigned long) value); | |
a737bd4d | 21227 | |
c19d1205 ZW |
21228 | if (value & ~0x3fc) |
21229 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21230 | _("invalid offset, value too big (0x%08lX)"), | |
21231 | (long) value); | |
a737bd4d | 21232 | |
c19d1205 ZW |
21233 | newval |= value >> 2; |
21234 | break; | |
a737bd4d | 21235 | |
c19d1205 ZW |
21236 | case 9: /* SP load/store. */ |
21237 | if (value & ~0x3fc) | |
21238 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21239 | _("invalid offset, value too big (0x%08lX)"), | |
21240 | (long) value); | |
21241 | newval |= value >> 2; | |
21242 | break; | |
6c43fab6 | 21243 | |
c19d1205 ZW |
21244 | case 6: /* Word load/store. */ |
21245 | if (value & ~0x7c) | |
21246 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21247 | _("invalid offset, value too big (0x%08lX)"), | |
21248 | (long) value); | |
21249 | newval |= value << 4; /* 6 - 2. */ | |
21250 | break; | |
a737bd4d | 21251 | |
c19d1205 ZW |
21252 | case 7: /* Byte load/store. */ |
21253 | if (value & ~0x1f) | |
21254 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21255 | _("invalid offset, value too big (0x%08lX)"), | |
21256 | (long) value); | |
21257 | newval |= value << 6; | |
21258 | break; | |
a737bd4d | 21259 | |
c19d1205 ZW |
21260 | case 8: /* Halfword load/store. */ |
21261 | if (value & ~0x3e) | |
21262 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21263 | _("invalid offset, value too big (0x%08lX)"), | |
21264 | (long) value); | |
21265 | newval |= value << 5; /* 6 - 1. */ | |
21266 | break; | |
a737bd4d | 21267 | |
c19d1205 ZW |
21268 | default: |
21269 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21270 | "Unable to process relocation for thumb opcode: %lx", | |
21271 | (unsigned long) newval); | |
21272 | break; | |
21273 | } | |
21274 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21275 | break; | |
a737bd4d | 21276 | |
c19d1205 ZW |
21277 | case BFD_RELOC_ARM_THUMB_ADD: |
21278 | /* This is a complicated relocation, since we use it for all of | |
21279 | the following immediate relocations: | |
a737bd4d | 21280 | |
c19d1205 ZW |
21281 | 3bit ADD/SUB |
21282 | 8bit ADD/SUB | |
21283 | 9bit ADD/SUB SP word-aligned | |
21284 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 21285 | |
c19d1205 ZW |
21286 | The type of instruction being processed is encoded in the |
21287 | instruction field: | |
a737bd4d | 21288 | |
c19d1205 ZW |
21289 | 0x8000 SUB |
21290 | 0x00F0 Rd | |
21291 | 0x000F Rs | |
21292 | */ | |
21293 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21294 | { | |
21295 | int rd = (newval >> 4) & 0xf; | |
21296 | int rs = newval & 0xf; | |
21297 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 21298 | |
c19d1205 ZW |
21299 | /* Check for HI regs, only very restricted cases allowed: |
21300 | Adjusting SP, and using PC or SP to get an address. */ | |
21301 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
21302 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
21303 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21304 | _("invalid Hi register with immediate")); | |
a737bd4d | 21305 | |
c19d1205 ZW |
21306 | /* If value is negative, choose the opposite instruction. */ |
21307 | if (value < 0) | |
21308 | { | |
21309 | value = -value; | |
21310 | subtract = !subtract; | |
21311 | if (value < 0) | |
21312 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21313 | _("immediate value out of range")); | |
21314 | } | |
a737bd4d | 21315 | |
c19d1205 ZW |
21316 | if (rd == REG_SP) |
21317 | { | |
21318 | if (value & ~0x1fc) | |
21319 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21320 | _("invalid immediate for stack address calculation")); | |
21321 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
21322 | newval |= value >> 2; | |
21323 | } | |
21324 | else if (rs == REG_PC || rs == REG_SP) | |
21325 | { | |
21326 | if (subtract || value & ~0x3fc) | |
21327 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21328 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
21329 | (unsigned long) value); | |
21330 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
21331 | newval |= rd << 8; | |
21332 | newval |= value >> 2; | |
21333 | } | |
21334 | else if (rs == rd) | |
21335 | { | |
21336 | if (value & ~0xff) | |
21337 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21338 | _("immediate value out of range")); | |
21339 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
21340 | newval |= (rd << 8) | value; | |
21341 | } | |
21342 | else | |
21343 | { | |
21344 | if (value & ~0x7) | |
21345 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21346 | _("immediate value out of range")); | |
21347 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
21348 | newval |= rd | (rs << 3) | (value << 6); | |
21349 | } | |
21350 | } | |
21351 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21352 | break; | |
a737bd4d | 21353 | |
c19d1205 ZW |
21354 | case BFD_RELOC_ARM_THUMB_IMM: |
21355 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21356 | if (value < 0 || value > 255) | |
21357 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 21358 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
21359 | (long) value); |
21360 | newval |= value; | |
21361 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21362 | break; | |
a737bd4d | 21363 | |
c19d1205 ZW |
21364 | case BFD_RELOC_ARM_THUMB_SHIFT: |
21365 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
21366 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
21367 | temp = newval & 0xf800; | |
21368 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
21369 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21370 | _("invalid shift value: %ld"), (long) value); | |
21371 | /* Shifts of zero must be encoded as LSL. */ | |
21372 | if (value == 0) | |
21373 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
21374 | /* Shifts of 32 are encoded as zero. */ | |
21375 | else if (value == 32) | |
21376 | value = 0; | |
21377 | newval |= value << 6; | |
21378 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21379 | break; | |
a737bd4d | 21380 | |
c19d1205 ZW |
21381 | case BFD_RELOC_VTABLE_INHERIT: |
21382 | case BFD_RELOC_VTABLE_ENTRY: | |
21383 | fixP->fx_done = 0; | |
21384 | return; | |
6c43fab6 | 21385 | |
b6895b4f PB |
21386 | case BFD_RELOC_ARM_MOVW: |
21387 | case BFD_RELOC_ARM_MOVT: | |
21388 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21389 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21390 | if (fixP->fx_done || !seg->use_rela_p) | |
21391 | { | |
21392 | /* REL format relocations are limited to a 16-bit addend. */ | |
21393 | if (!fixP->fx_done) | |
21394 | { | |
39623e12 | 21395 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 21396 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 21397 | _("offset out of range")); |
b6895b4f PB |
21398 | } |
21399 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
21400 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
21401 | { | |
21402 | value >>= 16; | |
21403 | } | |
21404 | ||
21405 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
21406 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
21407 | { | |
21408 | newval = get_thumb32_insn (buf); | |
21409 | newval &= 0xfbf08f00; | |
21410 | newval |= (value & 0xf000) << 4; | |
21411 | newval |= (value & 0x0800) << 15; | |
21412 | newval |= (value & 0x0700) << 4; | |
21413 | newval |= (value & 0x00ff); | |
21414 | put_thumb32_insn (buf, newval); | |
21415 | } | |
21416 | else | |
21417 | { | |
21418 | newval = md_chars_to_number (buf, 4); | |
21419 | newval &= 0xfff0f000; | |
21420 | newval |= value & 0x0fff; | |
21421 | newval |= (value & 0xf000) << 4; | |
21422 | md_number_to_chars (buf, newval, 4); | |
21423 | } | |
21424 | } | |
21425 | return; | |
21426 | ||
4962c51a MS |
21427 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21428 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21429 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21430 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21431 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21432 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21433 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21434 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21435 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21436 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 21437 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21438 | if (!seg->use_rela_p) |
21439 | { | |
21440 | bfd_vma insn; | |
21441 | bfd_vma encoded_addend; | |
21442 | bfd_vma addend_abs = abs (value); | |
21443 | ||
21444 | /* Check that the absolute value of the addend can be | |
21445 | expressed as an 8-bit constant plus a rotation. */ | |
21446 | encoded_addend = encode_arm_immediate (addend_abs); | |
21447 | if (encoded_addend == (unsigned int) FAIL) | |
21448 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21449 | _("the offset 0x%08lX is not representable"), | |
495bde8e | 21450 | (unsigned long) addend_abs); |
4962c51a MS |
21451 | |
21452 | /* Extract the instruction. */ | |
21453 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21454 | ||
21455 | /* If the addend is positive, use an ADD instruction. | |
21456 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
21457 | insn &= 0xff1fffff; | |
21458 | if (value < 0) | |
21459 | insn |= 1 << 22; | |
21460 | else | |
21461 | insn |= 1 << 23; | |
21462 | ||
21463 | /* Place the encoded addend into the first 12 bits of the | |
21464 | instruction. */ | |
21465 | insn &= 0xfffff000; | |
21466 | insn |= encoded_addend; | |
5f4273c7 NC |
21467 | |
21468 | /* Update the instruction. */ | |
4962c51a MS |
21469 | md_number_to_chars (buf, insn, INSN_SIZE); |
21470 | } | |
21471 | break; | |
21472 | ||
21473 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21474 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21475 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21476 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21477 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21478 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 21479 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21480 | if (!seg->use_rela_p) |
21481 | { | |
21482 | bfd_vma insn; | |
21483 | bfd_vma addend_abs = abs (value); | |
21484 | ||
21485 | /* Check that the absolute value of the addend can be | |
21486 | encoded in 12 bits. */ | |
21487 | if (addend_abs >= 0x1000) | |
21488 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21489 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), | |
495bde8e | 21490 | (unsigned long) addend_abs); |
4962c51a MS |
21491 | |
21492 | /* Extract the instruction. */ | |
21493 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21494 | ||
21495 | /* If the addend is negative, clear bit 23 of the instruction. | |
21496 | Otherwise set it. */ | |
21497 | if (value < 0) | |
21498 | insn &= ~(1 << 23); | |
21499 | else | |
21500 | insn |= 1 << 23; | |
21501 | ||
21502 | /* Place the absolute value of the addend into the first 12 bits | |
21503 | of the instruction. */ | |
21504 | insn &= 0xfffff000; | |
21505 | insn |= addend_abs; | |
5f4273c7 NC |
21506 | |
21507 | /* Update the instruction. */ | |
4962c51a MS |
21508 | md_number_to_chars (buf, insn, INSN_SIZE); |
21509 | } | |
21510 | break; | |
21511 | ||
21512 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21513 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21514 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21515 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21516 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21517 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 21518 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21519 | if (!seg->use_rela_p) |
21520 | { | |
21521 | bfd_vma insn; | |
21522 | bfd_vma addend_abs = abs (value); | |
21523 | ||
21524 | /* Check that the absolute value of the addend can be | |
21525 | encoded in 8 bits. */ | |
21526 | if (addend_abs >= 0x100) | |
21527 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21528 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), | |
495bde8e | 21529 | (unsigned long) addend_abs); |
4962c51a MS |
21530 | |
21531 | /* Extract the instruction. */ | |
21532 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21533 | ||
21534 | /* If the addend is negative, clear bit 23 of the instruction. | |
21535 | Otherwise set it. */ | |
21536 | if (value < 0) | |
21537 | insn &= ~(1 << 23); | |
21538 | else | |
21539 | insn |= 1 << 23; | |
21540 | ||
21541 | /* Place the first four bits of the absolute value of the addend | |
21542 | into the first 4 bits of the instruction, and the remaining | |
21543 | four into bits 8 .. 11. */ | |
21544 | insn &= 0xfffff0f0; | |
21545 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
5f4273c7 NC |
21546 | |
21547 | /* Update the instruction. */ | |
4962c51a MS |
21548 | md_number_to_chars (buf, insn, INSN_SIZE); |
21549 | } | |
21550 | break; | |
21551 | ||
21552 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21553 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21554 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21555 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21556 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21557 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 21558 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21559 | if (!seg->use_rela_p) |
21560 | { | |
21561 | bfd_vma insn; | |
21562 | bfd_vma addend_abs = abs (value); | |
21563 | ||
21564 | /* Check that the absolute value of the addend is a multiple of | |
21565 | four and, when divided by four, fits in 8 bits. */ | |
21566 | if (addend_abs & 0x3) | |
21567 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21568 | _("bad offset 0x%08lX (must be word-aligned)"), | |
495bde8e | 21569 | (unsigned long) addend_abs); |
4962c51a MS |
21570 | |
21571 | if ((addend_abs >> 2) > 0xff) | |
21572 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21573 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), | |
495bde8e | 21574 | (unsigned long) addend_abs); |
4962c51a MS |
21575 | |
21576 | /* Extract the instruction. */ | |
21577 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21578 | ||
21579 | /* If the addend is negative, clear bit 23 of the instruction. | |
21580 | Otherwise set it. */ | |
21581 | if (value < 0) | |
21582 | insn &= ~(1 << 23); | |
21583 | else | |
21584 | insn |= 1 << 23; | |
21585 | ||
21586 | /* Place the addend (divided by four) into the first eight | |
21587 | bits of the instruction. */ | |
21588 | insn &= 0xfffffff0; | |
21589 | insn |= addend_abs >> 2; | |
5f4273c7 NC |
21590 | |
21591 | /* Update the instruction. */ | |
4962c51a MS |
21592 | md_number_to_chars (buf, insn, INSN_SIZE); |
21593 | } | |
21594 | break; | |
21595 | ||
845b51d6 PB |
21596 | case BFD_RELOC_ARM_V4BX: |
21597 | /* This will need to go in the object file. */ | |
21598 | fixP->fx_done = 0; | |
21599 | break; | |
21600 | ||
c19d1205 ZW |
21601 | case BFD_RELOC_UNUSED: |
21602 | default: | |
21603 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21604 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
21605 | } | |
6c43fab6 RE |
21606 | } |
21607 | ||
c19d1205 ZW |
21608 | /* Translate internal representation of relocation info to BFD target |
21609 | format. */ | |
a737bd4d | 21610 | |
c19d1205 | 21611 | arelent * |
00a97672 | 21612 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 21613 | { |
c19d1205 ZW |
21614 | arelent * reloc; |
21615 | bfd_reloc_code_real_type code; | |
a737bd4d | 21616 | |
21d799b5 | 21617 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 21618 | |
21d799b5 | 21619 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
21620 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
21621 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 21622 | |
2fc8bdac | 21623 | if (fixp->fx_pcrel) |
00a97672 RS |
21624 | { |
21625 | if (section->use_rela_p) | |
21626 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
21627 | else | |
21628 | fixp->fx_offset = reloc->address; | |
21629 | } | |
c19d1205 | 21630 | reloc->addend = fixp->fx_offset; |
a737bd4d | 21631 | |
c19d1205 | 21632 | switch (fixp->fx_r_type) |
a737bd4d | 21633 | { |
c19d1205 ZW |
21634 | case BFD_RELOC_8: |
21635 | if (fixp->fx_pcrel) | |
21636 | { | |
21637 | code = BFD_RELOC_8_PCREL; | |
21638 | break; | |
21639 | } | |
a737bd4d | 21640 | |
c19d1205 ZW |
21641 | case BFD_RELOC_16: |
21642 | if (fixp->fx_pcrel) | |
21643 | { | |
21644 | code = BFD_RELOC_16_PCREL; | |
21645 | break; | |
21646 | } | |
6c43fab6 | 21647 | |
c19d1205 ZW |
21648 | case BFD_RELOC_32: |
21649 | if (fixp->fx_pcrel) | |
21650 | { | |
21651 | code = BFD_RELOC_32_PCREL; | |
21652 | break; | |
21653 | } | |
a737bd4d | 21654 | |
b6895b4f PB |
21655 | case BFD_RELOC_ARM_MOVW: |
21656 | if (fixp->fx_pcrel) | |
21657 | { | |
21658 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
21659 | break; | |
21660 | } | |
21661 | ||
21662 | case BFD_RELOC_ARM_MOVT: | |
21663 | if (fixp->fx_pcrel) | |
21664 | { | |
21665 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
21666 | break; | |
21667 | } | |
21668 | ||
21669 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21670 | if (fixp->fx_pcrel) | |
21671 | { | |
21672 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
21673 | break; | |
21674 | } | |
21675 | ||
21676 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21677 | if (fixp->fx_pcrel) | |
21678 | { | |
21679 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
21680 | break; | |
21681 | } | |
21682 | ||
c19d1205 ZW |
21683 | case BFD_RELOC_NONE: |
21684 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
21685 | case BFD_RELOC_ARM_PCREL_BLX: | |
21686 | case BFD_RELOC_RVA: | |
21687 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
21688 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
21689 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
21690 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21691 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21692 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
21693 | case BFD_RELOC_VTABLE_ENTRY: |
21694 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
21695 | #ifdef TE_PE |
21696 | case BFD_RELOC_32_SECREL: | |
21697 | #endif | |
c19d1205 ZW |
21698 | code = fixp->fx_r_type; |
21699 | break; | |
a737bd4d | 21700 | |
00adf2d4 JB |
21701 | case BFD_RELOC_THUMB_PCREL_BLX: |
21702 | #ifdef OBJ_ELF | |
21703 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
21704 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21705 | else | |
21706 | #endif | |
21707 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
21708 | break; | |
21709 | ||
c19d1205 ZW |
21710 | case BFD_RELOC_ARM_LITERAL: |
21711 | case BFD_RELOC_ARM_HWLITERAL: | |
21712 | /* If this is called then the a literal has | |
21713 | been referenced across a section boundary. */ | |
21714 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21715 | _("literal referenced across section boundary")); | |
21716 | return NULL; | |
a737bd4d | 21717 | |
c19d1205 | 21718 | #ifdef OBJ_ELF |
0855e32b NS |
21719 | case BFD_RELOC_ARM_TLS_CALL: |
21720 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
21721 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
21722 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
21723 | case BFD_RELOC_ARM_GOT32: |
21724 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 21725 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
21726 | case BFD_RELOC_ARM_PLT32: |
21727 | case BFD_RELOC_ARM_TARGET1: | |
21728 | case BFD_RELOC_ARM_ROSEGREL32: | |
21729 | case BFD_RELOC_ARM_SBREL32: | |
21730 | case BFD_RELOC_ARM_PREL31: | |
21731 | case BFD_RELOC_ARM_TARGET2: | |
21732 | case BFD_RELOC_ARM_TLS_LE32: | |
21733 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
21734 | case BFD_RELOC_ARM_PCREL_CALL: |
21735 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
21736 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21737 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21738 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21739 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21740 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21741 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21742 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21743 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21744 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21745 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21746 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21747 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21748 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21749 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21750 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21751 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21752 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21753 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21754 | case BFD_RELOC_ARM_ALU_SB_G2: | |
21755 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21756 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21757 | case BFD_RELOC_ARM_LDR_SB_G2: | |
21758 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21759 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21760 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
21761 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21762 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21763 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 21764 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
21765 | code = fixp->fx_r_type; |
21766 | break; | |
a737bd4d | 21767 | |
0855e32b | 21768 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
21769 | case BFD_RELOC_ARM_TLS_GD32: |
21770 | case BFD_RELOC_ARM_TLS_IE32: | |
21771 | case BFD_RELOC_ARM_TLS_LDM32: | |
21772 | /* BFD will include the symbol's address in the addend. | |
21773 | But we don't want that, so subtract it out again here. */ | |
21774 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
21775 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
21776 | code = fixp->fx_r_type; | |
21777 | break; | |
21778 | #endif | |
a737bd4d | 21779 | |
c19d1205 ZW |
21780 | case BFD_RELOC_ARM_IMMEDIATE: |
21781 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21782 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
21783 | return NULL; | |
a737bd4d | 21784 | |
c19d1205 ZW |
21785 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
21786 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21787 | _("ADRL used for a symbol not defined in the same file")); | |
21788 | return NULL; | |
a737bd4d | 21789 | |
c19d1205 | 21790 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
21791 | if (section->use_rela_p) |
21792 | { | |
21793 | code = fixp->fx_r_type; | |
21794 | break; | |
21795 | } | |
21796 | ||
c19d1205 ZW |
21797 | if (fixp->fx_addsy != NULL |
21798 | && !S_IS_DEFINED (fixp->fx_addsy) | |
21799 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 21800 | { |
c19d1205 ZW |
21801 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21802 | _("undefined local label `%s'"), | |
21803 | S_GET_NAME (fixp->fx_addsy)); | |
21804 | return NULL; | |
a737bd4d NC |
21805 | } |
21806 | ||
c19d1205 ZW |
21807 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21808 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
21809 | return NULL; | |
a737bd4d | 21810 | |
c19d1205 ZW |
21811 | default: |
21812 | { | |
21813 | char * type; | |
6c43fab6 | 21814 | |
c19d1205 ZW |
21815 | switch (fixp->fx_r_type) |
21816 | { | |
21817 | case BFD_RELOC_NONE: type = "NONE"; break; | |
21818 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
21819 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 21820 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
21821 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
21822 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
21823 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 21824 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 21825 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
21826 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
21827 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
21828 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
21829 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
21830 | default: type = _("<unknown>"); break; | |
21831 | } | |
21832 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21833 | _("cannot represent %s relocation in this object file format"), | |
21834 | type); | |
21835 | return NULL; | |
21836 | } | |
a737bd4d | 21837 | } |
6c43fab6 | 21838 | |
c19d1205 ZW |
21839 | #ifdef OBJ_ELF |
21840 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
21841 | && GOT_symbol | |
21842 | && fixp->fx_addsy == GOT_symbol) | |
21843 | { | |
21844 | code = BFD_RELOC_ARM_GOTPC; | |
21845 | reloc->addend = fixp->fx_offset = reloc->address; | |
21846 | } | |
21847 | #endif | |
6c43fab6 | 21848 | |
c19d1205 | 21849 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 21850 | |
c19d1205 ZW |
21851 | if (reloc->howto == NULL) |
21852 | { | |
21853 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21854 | _("cannot represent %s relocation in this object file format"), | |
21855 | bfd_get_reloc_code_name (code)); | |
21856 | return NULL; | |
21857 | } | |
6c43fab6 | 21858 | |
c19d1205 ZW |
21859 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
21860 | vtable entry to be used in the relocation's section offset. */ | |
21861 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
21862 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 21863 | |
c19d1205 | 21864 | return reloc; |
6c43fab6 RE |
21865 | } |
21866 | ||
c19d1205 | 21867 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 21868 | |
c19d1205 ZW |
21869 | void |
21870 | cons_fix_new_arm (fragS * frag, | |
21871 | int where, | |
21872 | int size, | |
21873 | expressionS * exp) | |
6c43fab6 | 21874 | { |
c19d1205 ZW |
21875 | bfd_reloc_code_real_type type; |
21876 | int pcrel = 0; | |
6c43fab6 | 21877 | |
c19d1205 ZW |
21878 | /* Pick a reloc. |
21879 | FIXME: @@ Should look at CPU word size. */ | |
21880 | switch (size) | |
21881 | { | |
21882 | case 1: | |
21883 | type = BFD_RELOC_8; | |
21884 | break; | |
21885 | case 2: | |
21886 | type = BFD_RELOC_16; | |
21887 | break; | |
21888 | case 4: | |
21889 | default: | |
21890 | type = BFD_RELOC_32; | |
21891 | break; | |
21892 | case 8: | |
21893 | type = BFD_RELOC_64; | |
21894 | break; | |
21895 | } | |
6c43fab6 | 21896 | |
f0927246 NC |
21897 | #ifdef TE_PE |
21898 | if (exp->X_op == O_secrel) | |
21899 | { | |
21900 | exp->X_op = O_symbol; | |
21901 | type = BFD_RELOC_32_SECREL; | |
21902 | } | |
21903 | #endif | |
21904 | ||
c19d1205 ZW |
21905 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
21906 | } | |
6c43fab6 | 21907 | |
4343666d | 21908 | #if defined (OBJ_COFF) |
c19d1205 ZW |
21909 | void |
21910 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 21911 | { |
c19d1205 ZW |
21912 | /* If the destination of the branch is a defined symbol which does not have |
21913 | the THUMB_FUNC attribute, then we must be calling a function which has | |
21914 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
21915 | function and change the branch to refer to that function instead. */ | |
21916 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
21917 | && fixP->fx_addsy != NULL | |
21918 | && S_IS_DEFINED (fixP->fx_addsy) | |
21919 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 21920 | { |
c19d1205 | 21921 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 21922 | } |
c19d1205 ZW |
21923 | } |
21924 | #endif | |
6c43fab6 | 21925 | |
267bf995 | 21926 | |
c19d1205 ZW |
21927 | int |
21928 | arm_force_relocation (struct fix * fixp) | |
21929 | { | |
21930 | #if defined (OBJ_COFF) && defined (TE_PE) | |
21931 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
21932 | return 1; | |
21933 | #endif | |
6c43fab6 | 21934 | |
267bf995 RR |
21935 | /* In case we have a call or a branch to a function in ARM ISA mode from |
21936 | a thumb function or vice-versa force the relocation. These relocations | |
21937 | are cleared off for some cores that might have blx and simple transformations | |
21938 | are possible. */ | |
21939 | ||
21940 | #ifdef OBJ_ELF | |
21941 | switch (fixp->fx_r_type) | |
21942 | { | |
21943 | case BFD_RELOC_ARM_PCREL_JUMP: | |
21944 | case BFD_RELOC_ARM_PCREL_CALL: | |
21945 | case BFD_RELOC_THUMB_PCREL_BLX: | |
21946 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
21947 | return 1; | |
21948 | break; | |
21949 | ||
21950 | case BFD_RELOC_ARM_PCREL_BLX: | |
21951 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
21952 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21953 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21954 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
21955 | return 1; | |
21956 | break; | |
21957 | ||
21958 | default: | |
21959 | break; | |
21960 | } | |
21961 | #endif | |
21962 | ||
b5884301 PB |
21963 | /* Resolve these relocations even if the symbol is extern or weak. |
21964 | Technically this is probably wrong due to symbol preemption. | |
21965 | In practice these relocations do not have enough range to be useful | |
21966 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
21967 | expects these references to be resolved. */ | |
c19d1205 ZW |
21968 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
21969 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 21970 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 21971 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
21972 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21973 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
21974 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 21975 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
21976 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
21977 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
21978 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
21979 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
21980 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
21981 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 21982 | return 0; |
a737bd4d | 21983 | |
4962c51a MS |
21984 | /* Always leave these relocations for the linker. */ |
21985 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
21986 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
21987 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
21988 | return 1; | |
21989 | ||
f0291e4c PB |
21990 | /* Always generate relocations against function symbols. */ |
21991 | if (fixp->fx_r_type == BFD_RELOC_32 | |
21992 | && fixp->fx_addsy | |
21993 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
21994 | return 1; | |
21995 | ||
c19d1205 | 21996 | return generic_force_reloc (fixp); |
404ff6b5 AH |
21997 | } |
21998 | ||
0ffdc86c | 21999 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
22000 | /* Relocations against function names must be left unadjusted, |
22001 | so that the linker can use this information to generate interworking | |
22002 | stubs. The MIPS version of this function | |
c19d1205 ZW |
22003 | also prevents relocations that are mips-16 specific, but I do not |
22004 | know why it does this. | |
404ff6b5 | 22005 | |
c19d1205 ZW |
22006 | FIXME: |
22007 | There is one other problem that ought to be addressed here, but | |
22008 | which currently is not: Taking the address of a label (rather | |
22009 | than a function) and then later jumping to that address. Such | |
22010 | addresses also ought to have their bottom bit set (assuming that | |
22011 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 22012 | |
c19d1205 ZW |
22013 | bfd_boolean |
22014 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 22015 | { |
c19d1205 ZW |
22016 | if (fixP->fx_addsy == NULL) |
22017 | return 1; | |
404ff6b5 | 22018 | |
e28387c3 PB |
22019 | /* Preserve relocations against symbols with function type. */ |
22020 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 22021 | return FALSE; |
e28387c3 | 22022 | |
c19d1205 ZW |
22023 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
22024 | && fixP->fx_subsy == NULL) | |
c921be7d | 22025 | return FALSE; |
a737bd4d | 22026 | |
c19d1205 ZW |
22027 | /* We need the symbol name for the VTABLE entries. */ |
22028 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
22029 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 22030 | return FALSE; |
404ff6b5 | 22031 | |
c19d1205 ZW |
22032 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
22033 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
22034 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
22035 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
22036 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
22037 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
22038 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
22039 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
22040 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
0855e32b NS |
22041 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
22042 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
22043 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
22044 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
22045 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 22046 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 22047 | return FALSE; |
a737bd4d | 22048 | |
4962c51a MS |
22049 | /* Similarly for group relocations. */ |
22050 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
22051 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
22052 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 22053 | return FALSE; |
4962c51a | 22054 | |
79947c54 CD |
22055 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
22056 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
22057 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
22058 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
22059 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
22060 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
22061 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
22062 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
22063 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 22064 | return FALSE; |
79947c54 | 22065 | |
c921be7d | 22066 | return TRUE; |
a737bd4d | 22067 | } |
0ffdc86c NC |
22068 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
22069 | ||
22070 | #ifdef OBJ_ELF | |
404ff6b5 | 22071 | |
c19d1205 ZW |
22072 | const char * |
22073 | elf32_arm_target_format (void) | |
404ff6b5 | 22074 | { |
c19d1205 ZW |
22075 | #ifdef TE_SYMBIAN |
22076 | return (target_big_endian | |
22077 | ? "elf32-bigarm-symbian" | |
22078 | : "elf32-littlearm-symbian"); | |
22079 | #elif defined (TE_VXWORKS) | |
22080 | return (target_big_endian | |
22081 | ? "elf32-bigarm-vxworks" | |
22082 | : "elf32-littlearm-vxworks"); | |
22083 | #else | |
22084 | if (target_big_endian) | |
22085 | return "elf32-bigarm"; | |
22086 | else | |
22087 | return "elf32-littlearm"; | |
22088 | #endif | |
404ff6b5 AH |
22089 | } |
22090 | ||
c19d1205 ZW |
22091 | void |
22092 | armelf_frob_symbol (symbolS * symp, | |
22093 | int * puntp) | |
404ff6b5 | 22094 | { |
c19d1205 ZW |
22095 | elf_frob_symbol (symp, puntp); |
22096 | } | |
22097 | #endif | |
404ff6b5 | 22098 | |
c19d1205 | 22099 | /* MD interface: Finalization. */ |
a737bd4d | 22100 | |
c19d1205 ZW |
22101 | void |
22102 | arm_cleanup (void) | |
22103 | { | |
22104 | literal_pool * pool; | |
a737bd4d | 22105 | |
e07e6e58 NC |
22106 | /* Ensure that all the IT blocks are properly closed. */ |
22107 | check_it_blocks_finished (); | |
22108 | ||
c19d1205 ZW |
22109 | for (pool = list_of_pools; pool; pool = pool->next) |
22110 | { | |
5f4273c7 | 22111 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
22112 | subseg_set (pool->section, pool->sub_section); |
22113 | #ifdef OBJ_ELF | |
22114 | arm_elf_change_section (); | |
22115 | #endif | |
22116 | s_ltorg (0); | |
22117 | } | |
404ff6b5 AH |
22118 | } |
22119 | ||
cd000bff DJ |
22120 | #ifdef OBJ_ELF |
22121 | /* Remove any excess mapping symbols generated for alignment frags in | |
22122 | SEC. We may have created a mapping symbol before a zero byte | |
22123 | alignment; remove it if there's a mapping symbol after the | |
22124 | alignment. */ | |
22125 | static void | |
22126 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
22127 | void *dummy ATTRIBUTE_UNUSED) | |
22128 | { | |
22129 | segment_info_type *seginfo = seg_info (sec); | |
22130 | fragS *fragp; | |
22131 | ||
22132 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
22133 | return; | |
22134 | ||
22135 | for (fragp = seginfo->frchainP->frch_root; | |
22136 | fragp != NULL; | |
22137 | fragp = fragp->fr_next) | |
22138 | { | |
22139 | symbolS *sym = fragp->tc_frag_data.last_map; | |
22140 | fragS *next = fragp->fr_next; | |
22141 | ||
22142 | /* Variable-sized frags have been converted to fixed size by | |
22143 | this point. But if this was variable-sized to start with, | |
22144 | there will be a fixed-size frag after it. So don't handle | |
22145 | next == NULL. */ | |
22146 | if (sym == NULL || next == NULL) | |
22147 | continue; | |
22148 | ||
22149 | if (S_GET_VALUE (sym) < next->fr_address) | |
22150 | /* Not at the end of this frag. */ | |
22151 | continue; | |
22152 | know (S_GET_VALUE (sym) == next->fr_address); | |
22153 | ||
22154 | do | |
22155 | { | |
22156 | if (next->tc_frag_data.first_map != NULL) | |
22157 | { | |
22158 | /* Next frag starts with a mapping symbol. Discard this | |
22159 | one. */ | |
22160 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
22161 | break; | |
22162 | } | |
22163 | ||
22164 | if (next->fr_next == NULL) | |
22165 | { | |
22166 | /* This mapping symbol is at the end of the section. Discard | |
22167 | it. */ | |
22168 | know (next->fr_fix == 0 && next->fr_var == 0); | |
22169 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
22170 | break; | |
22171 | } | |
22172 | ||
22173 | /* As long as we have empty frags without any mapping symbols, | |
22174 | keep looking. */ | |
22175 | /* If the next frag is non-empty and does not start with a | |
22176 | mapping symbol, then this mapping symbol is required. */ | |
22177 | if (next->fr_address != next->fr_next->fr_address) | |
22178 | break; | |
22179 | ||
22180 | next = next->fr_next; | |
22181 | } | |
22182 | while (next != NULL); | |
22183 | } | |
22184 | } | |
22185 | #endif | |
22186 | ||
c19d1205 ZW |
22187 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
22188 | ARM ones. */ | |
404ff6b5 | 22189 | |
c19d1205 ZW |
22190 | void |
22191 | arm_adjust_symtab (void) | |
404ff6b5 | 22192 | { |
c19d1205 ZW |
22193 | #ifdef OBJ_COFF |
22194 | symbolS * sym; | |
404ff6b5 | 22195 | |
c19d1205 ZW |
22196 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
22197 | { | |
22198 | if (ARM_IS_THUMB (sym)) | |
22199 | { | |
22200 | if (THUMB_IS_FUNC (sym)) | |
22201 | { | |
22202 | /* Mark the symbol as a Thumb function. */ | |
22203 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
22204 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
22205 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 22206 | |
c19d1205 ZW |
22207 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
22208 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
22209 | else | |
22210 | as_bad (_("%s: unexpected function type: %d"), | |
22211 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
22212 | } | |
22213 | else switch (S_GET_STORAGE_CLASS (sym)) | |
22214 | { | |
22215 | case C_EXT: | |
22216 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
22217 | break; | |
22218 | case C_STAT: | |
22219 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
22220 | break; | |
22221 | case C_LABEL: | |
22222 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
22223 | break; | |
22224 | default: | |
22225 | /* Do nothing. */ | |
22226 | break; | |
22227 | } | |
22228 | } | |
a737bd4d | 22229 | |
c19d1205 ZW |
22230 | if (ARM_IS_INTERWORK (sym)) |
22231 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 22232 | } |
c19d1205 ZW |
22233 | #endif |
22234 | #ifdef OBJ_ELF | |
22235 | symbolS * sym; | |
22236 | char bind; | |
404ff6b5 | 22237 | |
c19d1205 | 22238 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 22239 | { |
c19d1205 ZW |
22240 | if (ARM_IS_THUMB (sym)) |
22241 | { | |
22242 | elf_symbol_type * elf_sym; | |
404ff6b5 | 22243 | |
c19d1205 ZW |
22244 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
22245 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 22246 | |
b0796911 PB |
22247 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
22248 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
22249 | { |
22250 | /* If it's a .thumb_func, declare it as so, | |
22251 | otherwise tag label as .code 16. */ | |
22252 | if (THUMB_IS_FUNC (sym)) | |
35fc36a8 RS |
22253 | elf_sym->internal_elf_sym.st_target_internal |
22254 | = ST_BRANCH_TO_THUMB; | |
3ba67470 | 22255 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
22256 | elf_sym->internal_elf_sym.st_info = |
22257 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
22258 | } | |
22259 | } | |
22260 | } | |
cd000bff DJ |
22261 | |
22262 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
22263 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
22264 | /* Now do generic ELF adjustments. */ |
22265 | elf_adjust_symtab (); | |
c19d1205 | 22266 | #endif |
404ff6b5 AH |
22267 | } |
22268 | ||
c19d1205 | 22269 | /* MD interface: Initialization. */ |
404ff6b5 | 22270 | |
a737bd4d | 22271 | static void |
c19d1205 | 22272 | set_constant_flonums (void) |
a737bd4d | 22273 | { |
c19d1205 | 22274 | int i; |
404ff6b5 | 22275 | |
c19d1205 ZW |
22276 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
22277 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
22278 | abort (); | |
a737bd4d | 22279 | } |
404ff6b5 | 22280 | |
3e9e4fcf JB |
22281 | /* Auto-select Thumb mode if it's the only available instruction set for the |
22282 | given architecture. */ | |
22283 | ||
22284 | static void | |
22285 | autoselect_thumb_from_cpu_variant (void) | |
22286 | { | |
22287 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
22288 | opcode_select (16); | |
22289 | } | |
22290 | ||
c19d1205 ZW |
22291 | void |
22292 | md_begin (void) | |
a737bd4d | 22293 | { |
c19d1205 ZW |
22294 | unsigned mach; |
22295 | unsigned int i; | |
404ff6b5 | 22296 | |
c19d1205 ZW |
22297 | if ( (arm_ops_hsh = hash_new ()) == NULL |
22298 | || (arm_cond_hsh = hash_new ()) == NULL | |
22299 | || (arm_shift_hsh = hash_new ()) == NULL | |
22300 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 22301 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 22302 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
22303 | || (arm_reloc_hsh = hash_new ()) == NULL |
22304 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
22305 | as_fatal (_("virtual memory exhausted")); |
22306 | ||
22307 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 22308 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 22309 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 22310 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 22311 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 22312 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 22313 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 22314 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 22315 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 NC |
22316 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
22317 | (void *) (v7m_psrs + i)); | |
c19d1205 | 22318 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 22319 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
22320 | for (i = 0; |
22321 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
22322 | i++) | |
d3ce72d0 | 22323 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 22324 | (void *) (barrier_opt_names + i)); |
c19d1205 ZW |
22325 | #ifdef OBJ_ELF |
22326 | for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) | |
5a49b8ac | 22327 | hash_insert (arm_reloc_hsh, reloc_names[i].name, (void *) (reloc_names + i)); |
c19d1205 ZW |
22328 | #endif |
22329 | ||
22330 | set_constant_flonums (); | |
404ff6b5 | 22331 | |
c19d1205 ZW |
22332 | /* Set the cpu variant based on the command-line options. We prefer |
22333 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
22334 | -mfpu= over any other way of setting the floating point unit. | |
22335 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 22336 | if (legacy_cpu) |
404ff6b5 | 22337 | { |
e74cfd16 | 22338 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
22339 | as_bad (_("use of old and new-style options to set CPU type")); |
22340 | ||
22341 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 22342 | } |
e74cfd16 | 22343 | else if (!mcpu_cpu_opt) |
c19d1205 | 22344 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 22345 | |
e74cfd16 | 22346 | if (legacy_fpu) |
c19d1205 | 22347 | { |
e74cfd16 | 22348 | if (mfpu_opt) |
c19d1205 | 22349 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
22350 | |
22351 | mfpu_opt = legacy_fpu; | |
22352 | } | |
e74cfd16 | 22353 | else if (!mfpu_opt) |
03b1477f | 22354 | { |
45eb4c1b NS |
22355 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
22356 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
22357 | /* Some environments specify a default FPU. If they don't, infer it |
22358 | from the processor. */ | |
e74cfd16 | 22359 | if (mcpu_fpu_opt) |
03b1477f RE |
22360 | mfpu_opt = mcpu_fpu_opt; |
22361 | else | |
22362 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 22363 | #else |
e74cfd16 | 22364 | mfpu_opt = &fpu_default; |
39c2da32 | 22365 | #endif |
03b1477f RE |
22366 | } |
22367 | ||
e74cfd16 | 22368 | if (!mfpu_opt) |
03b1477f | 22369 | { |
493cb6ef | 22370 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 22371 | mfpu_opt = &fpu_default; |
493cb6ef | 22372 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 22373 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 22374 | else |
e74cfd16 | 22375 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
22376 | } |
22377 | ||
ee065d83 | 22378 | #ifdef CPU_DEFAULT |
e74cfd16 | 22379 | if (!mcpu_cpu_opt) |
ee065d83 | 22380 | { |
e74cfd16 PB |
22381 | mcpu_cpu_opt = &cpu_default; |
22382 | selected_cpu = cpu_default; | |
ee065d83 | 22383 | } |
e74cfd16 PB |
22384 | #else |
22385 | if (mcpu_cpu_opt) | |
22386 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 22387 | else |
e74cfd16 | 22388 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 22389 | #endif |
03b1477f | 22390 | |
e74cfd16 | 22391 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 22392 | |
3e9e4fcf JB |
22393 | autoselect_thumb_from_cpu_variant (); |
22394 | ||
e74cfd16 | 22395 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 22396 | |
f17c130b | 22397 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 22398 | { |
7cc69913 NC |
22399 | unsigned int flags = 0; |
22400 | ||
22401 | #if defined OBJ_ELF | |
22402 | flags = meabi_flags; | |
d507cf36 PB |
22403 | |
22404 | switch (meabi_flags) | |
33a392fb | 22405 | { |
d507cf36 | 22406 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 22407 | #endif |
d507cf36 PB |
22408 | /* Set the flags in the private structure. */ |
22409 | if (uses_apcs_26) flags |= F_APCS26; | |
22410 | if (support_interwork) flags |= F_INTERWORK; | |
22411 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 22412 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 22413 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
22414 | flags |= F_SOFT_FLOAT; |
22415 | ||
d507cf36 PB |
22416 | switch (mfloat_abi_opt) |
22417 | { | |
22418 | case ARM_FLOAT_ABI_SOFT: | |
22419 | case ARM_FLOAT_ABI_SOFTFP: | |
22420 | flags |= F_SOFT_FLOAT; | |
22421 | break; | |
33a392fb | 22422 | |
d507cf36 PB |
22423 | case ARM_FLOAT_ABI_HARD: |
22424 | if (flags & F_SOFT_FLOAT) | |
22425 | as_bad (_("hard-float conflicts with specified fpu")); | |
22426 | break; | |
22427 | } | |
03b1477f | 22428 | |
e74cfd16 PB |
22429 | /* Using pure-endian doubles (even if soft-float). */ |
22430 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 22431 | flags |= F_VFP_FLOAT; |
f17c130b | 22432 | |
fde78edd | 22433 | #if defined OBJ_ELF |
e74cfd16 | 22434 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 22435 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
22436 | break; |
22437 | ||
8cb51566 | 22438 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 22439 | case EF_ARM_EABI_VER5: |
c19d1205 | 22440 | /* No additional flags to set. */ |
d507cf36 PB |
22441 | break; |
22442 | ||
22443 | default: | |
22444 | abort (); | |
22445 | } | |
7cc69913 | 22446 | #endif |
b99bd4ef NC |
22447 | bfd_set_private_flags (stdoutput, flags); |
22448 | ||
22449 | /* We have run out flags in the COFF header to encode the | |
22450 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 22451 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
22452 | if (atpcs) |
22453 | { | |
22454 | asection * sec; | |
22455 | ||
22456 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
22457 | ||
22458 | if (sec != NULL) | |
22459 | { | |
22460 | bfd_set_section_flags | |
22461 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
22462 | bfd_set_section_size (stdoutput, sec, 0); | |
22463 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
22464 | } | |
22465 | } | |
7cc69913 | 22466 | } |
f17c130b | 22467 | #endif |
b99bd4ef NC |
22468 | |
22469 | /* Record the CPU type as well. */ | |
2d447fca JM |
22470 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
22471 | mach = bfd_mach_arm_iWMMXt2; | |
22472 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 22473 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 22474 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 22475 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 22476 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 22477 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 22478 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 22479 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 22480 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 22481 | { |
e74cfd16 | 22482 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
22483 | mach = bfd_mach_arm_5T; |
22484 | else | |
22485 | mach = bfd_mach_arm_5; | |
22486 | } | |
e74cfd16 | 22487 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 22488 | { |
e74cfd16 | 22489 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
22490 | mach = bfd_mach_arm_4T; |
22491 | else | |
22492 | mach = bfd_mach_arm_4; | |
22493 | } | |
e74cfd16 | 22494 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 22495 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
22496 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
22497 | mach = bfd_mach_arm_3; | |
22498 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
22499 | mach = bfd_mach_arm_2a; | |
22500 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
22501 | mach = bfd_mach_arm_2; | |
22502 | else | |
22503 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
22504 | |
22505 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
22506 | } | |
22507 | ||
c19d1205 | 22508 | /* Command line processing. */ |
b99bd4ef | 22509 | |
c19d1205 ZW |
22510 | /* md_parse_option |
22511 | Invocation line includes a switch not recognized by the base assembler. | |
22512 | See if it's a processor-specific option. | |
b99bd4ef | 22513 | |
c19d1205 ZW |
22514 | This routine is somewhat complicated by the need for backwards |
22515 | compatibility (since older releases of gcc can't be changed). | |
22516 | The new options try to make the interface as compatible as | |
22517 | possible with GCC. | |
b99bd4ef | 22518 | |
c19d1205 | 22519 | New options (supported) are: |
b99bd4ef | 22520 | |
c19d1205 ZW |
22521 | -mcpu=<cpu name> Assemble for selected processor |
22522 | -march=<architecture name> Assemble for selected architecture | |
22523 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
22524 | -EB/-mbig-endian Big-endian | |
22525 | -EL/-mlittle-endian Little-endian | |
22526 | -k Generate PIC code | |
22527 | -mthumb Start in Thumb mode | |
22528 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 22529 | |
278df34e | 22530 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 22531 | |
c19d1205 | 22532 | For now we will also provide support for: |
b99bd4ef | 22533 | |
c19d1205 ZW |
22534 | -mapcs-32 32-bit Program counter |
22535 | -mapcs-26 26-bit Program counter | |
22536 | -macps-float Floats passed in FP registers | |
22537 | -mapcs-reentrant Reentrant code | |
22538 | -matpcs | |
22539 | (sometime these will probably be replaced with -mapcs=<list of options> | |
22540 | and -matpcs=<list of options>) | |
b99bd4ef | 22541 | |
c19d1205 ZW |
22542 | The remaining options are only supported for back-wards compatibility. |
22543 | Cpu variants, the arm part is optional: | |
22544 | -m[arm]1 Currently not supported. | |
22545 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
22546 | -m[arm]3 Arm 3 processor | |
22547 | -m[arm]6[xx], Arm 6 processors | |
22548 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
22549 | -m[arm]8[10] Arm 8 processors | |
22550 | -m[arm]9[20][tdmi] Arm 9 processors | |
22551 | -mstrongarm[110[0]] StrongARM processors | |
22552 | -mxscale XScale processors | |
22553 | -m[arm]v[2345[t[e]]] Arm architectures | |
22554 | -mall All (except the ARM1) | |
22555 | FP variants: | |
22556 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
22557 | -mfpe-old (No float load/store multiples) | |
22558 | -mvfpxd VFP Single precision | |
22559 | -mvfp All VFP | |
22560 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 22561 | |
c19d1205 ZW |
22562 | The following CPU names are recognized: |
22563 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
22564 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
22565 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
22566 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
22567 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
22568 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
22569 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 22570 | |
c19d1205 | 22571 | */ |
b99bd4ef | 22572 | |
c19d1205 | 22573 | const char * md_shortopts = "m:k"; |
b99bd4ef | 22574 | |
c19d1205 ZW |
22575 | #ifdef ARM_BI_ENDIAN |
22576 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
22577 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 22578 | #else |
c19d1205 ZW |
22579 | #if TARGET_BYTES_BIG_ENDIAN |
22580 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 22581 | #else |
c19d1205 ZW |
22582 | #define OPTION_EL (OPTION_MD_BASE + 1) |
22583 | #endif | |
b99bd4ef | 22584 | #endif |
845b51d6 | 22585 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 22586 | |
c19d1205 | 22587 | struct option md_longopts[] = |
b99bd4ef | 22588 | { |
c19d1205 ZW |
22589 | #ifdef OPTION_EB |
22590 | {"EB", no_argument, NULL, OPTION_EB}, | |
22591 | #endif | |
22592 | #ifdef OPTION_EL | |
22593 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 22594 | #endif |
845b51d6 | 22595 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
22596 | {NULL, no_argument, NULL, 0} |
22597 | }; | |
b99bd4ef | 22598 | |
c19d1205 | 22599 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 22600 | |
c19d1205 | 22601 | struct arm_option_table |
b99bd4ef | 22602 | { |
c19d1205 ZW |
22603 | char *option; /* Option name to match. */ |
22604 | char *help; /* Help information. */ | |
22605 | int *var; /* Variable to change. */ | |
22606 | int value; /* What to change it to. */ | |
22607 | char *deprecated; /* If non-null, print this message. */ | |
22608 | }; | |
b99bd4ef | 22609 | |
c19d1205 ZW |
22610 | struct arm_option_table arm_opts[] = |
22611 | { | |
22612 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
22613 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
22614 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
22615 | &support_interwork, 1, NULL}, | |
22616 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
22617 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
22618 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
22619 | 1, NULL}, | |
22620 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
22621 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
22622 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
22623 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
22624 | NULL}, | |
b99bd4ef | 22625 | |
c19d1205 ZW |
22626 | /* These are recognized by the assembler, but have no affect on code. */ |
22627 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
22628 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
22629 | |
22630 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
22631 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
22632 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
22633 | {NULL, NULL, NULL, 0, NULL} |
22634 | }; | |
22635 | ||
22636 | struct arm_legacy_option_table | |
22637 | { | |
22638 | char *option; /* Option name to match. */ | |
22639 | const arm_feature_set **var; /* Variable to change. */ | |
22640 | const arm_feature_set value; /* What to change it to. */ | |
22641 | char *deprecated; /* If non-null, print this message. */ | |
22642 | }; | |
b99bd4ef | 22643 | |
e74cfd16 PB |
22644 | const struct arm_legacy_option_table arm_legacy_opts[] = |
22645 | { | |
c19d1205 ZW |
22646 | /* DON'T add any new processors to this list -- we want the whole list |
22647 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
22648 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
22649 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
22650 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
22651 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
22652 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
22653 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
22654 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
22655 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
22656 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22657 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22658 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22659 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22660 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22661 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22662 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22663 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22664 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22665 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22666 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22667 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22668 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22669 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22670 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22671 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22672 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22673 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22674 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22675 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22676 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22677 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22678 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22679 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22680 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22681 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22682 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22683 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22684 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22685 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22686 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22687 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22688 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22689 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22690 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22691 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22692 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22693 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22694 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22695 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22696 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22697 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22698 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22699 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22700 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22701 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22702 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22703 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22704 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22705 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22706 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22707 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22708 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22709 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22710 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22711 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22712 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22713 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22714 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22715 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22716 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
22717 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 22718 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 22719 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22720 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 22721 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22722 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
22723 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
22724 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
22725 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 22726 | |
c19d1205 | 22727 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22728 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
22729 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
22730 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22731 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22732 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22733 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22734 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22735 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22736 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22737 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22738 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22739 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22740 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22741 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22742 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22743 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22744 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
22745 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 22746 | |
c19d1205 | 22747 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22748 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
22749 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
22750 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
22751 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 22752 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 22753 | |
e74cfd16 | 22754 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 22755 | }; |
7ed4c4c5 | 22756 | |
c19d1205 | 22757 | struct arm_cpu_option_table |
7ed4c4c5 | 22758 | { |
c19d1205 | 22759 | char *name; |
e74cfd16 | 22760 | const arm_feature_set value; |
c19d1205 ZW |
22761 | /* For some CPUs we assume an FPU unless the user explicitly sets |
22762 | -mfpu=... */ | |
e74cfd16 | 22763 | const arm_feature_set default_fpu; |
ee065d83 PB |
22764 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
22765 | case. */ | |
22766 | const char *canonical_name; | |
c19d1205 | 22767 | }; |
7ed4c4c5 | 22768 | |
c19d1205 ZW |
22769 | /* This list should, at a minimum, contain all the cpu names |
22770 | recognized by GCC. */ | |
e74cfd16 | 22771 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 22772 | { |
ee065d83 PB |
22773 | {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, |
22774 | {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, | |
22775 | {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, | |
22776 | {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
22777 | {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, | |
22778 | {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22779 | {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22780 | {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22781 | {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22782 | {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22783 | {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22784 | {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22785 | {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22786 | {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22787 | {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22788 | {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, | |
22789 | {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22790 | {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22791 | {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22792 | {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22793 | {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22794 | {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22795 | {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22796 | {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22797 | {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22798 | {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22799 | {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22800 | {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, | |
22801 | {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22802 | {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22803 | {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22804 | {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22805 | {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22806 | {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22807 | {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22808 | {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22809 | {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22810 | {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
22811 | {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22812 | {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, | |
22813 | {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22814 | {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22815 | {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
22816 | {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, | |
7fac0536 NC |
22817 | {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, |
22818 | {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, | |
c19d1205 ZW |
22819 | /* For V5 or later processors we default to using VFP; but the user |
22820 | should really set the FPU type explicitly. */ | |
ee065d83 PB |
22821 | {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, |
22822 | {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22823 | {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
22824 | {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, | |
22825 | {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
22826 | {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
22827 | {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, | |
22828 | {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22829 | {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, | |
22830 | {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, | |
22831 | {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22832 | {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22833 | {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22834 | {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22835 | {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22836 | {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, | |
22837 | {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, | |
22838 | {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22839 | {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22840 | {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, | |
22841 | {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, | |
4a58c4bd NC |
22842 | {"fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, |
22843 | {"fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22844 | {"fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
22845 | {"fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, | |
7fac0536 | 22846 | {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, |
ee065d83 PB |
22847 | {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, |
22848 | {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, | |
22849 | {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, | |
22850 | {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, | |
4ff9b924 MGD |
22851 | {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"}, |
22852 | {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"}, | |
ee065d83 PB |
22853 | {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, |
22854 | {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, | |
22855 | {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, | |
22856 | {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, | |
f4c65163 MGD |
22857 | {"cortex-a5", ARM_ARCH_V7A_MP_SEC, |
22858 | FPU_NONE, "Cortex-A5"}, | |
22859 | {"cortex-a8", ARM_ARCH_V7A_SEC, | |
22860 | ARM_FEATURE (0, FPU_VFP_V3 | |
5287ad62 | 22861 | | FPU_NEON_EXT_V1), |
4ff9b924 | 22862 | "Cortex-A8"}, |
f4c65163 MGD |
22863 | {"cortex-a9", ARM_ARCH_V7A_MP_SEC, |
22864 | ARM_FEATURE (0, FPU_VFP_V3 | |
15290f0a | 22865 | | FPU_NEON_EXT_V1), |
4ff9b924 | 22866 | "Cortex-A9"}, |
90ec0d68 | 22867 | {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT, |
eea54501 | 22868 | FPU_ARCH_NEON_VFP_V4, |
dbb1f804 | 22869 | "Cortex-A15"}, |
4ff9b924 MGD |
22870 | {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"}, |
22871 | {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, | |
22872 | "Cortex-R4F"}, | |
3b2f0793 PB |
22873 | {"cortex-r5", ARM_ARCH_V7R_IDIV, |
22874 | FPU_NONE, "Cortex-R5"}, | |
4ff9b924 MGD |
22875 | {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"}, |
22876 | {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"}, | |
b2a5fbdc MGD |
22877 | {"cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"}, |
22878 | {"cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"}, | |
c19d1205 | 22879 | /* ??? XSCALE is really an architecture. */ |
ee065d83 | 22880 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 22881 | /* ??? iwmmxt is not a processor. */ |
ee065d83 | 22882 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, |
2d447fca | 22883 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, |
ee065d83 | 22884 | {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, |
c19d1205 | 22885 | /* Maverick */ |
e07e6e58 | 22886 | {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, |
e74cfd16 | 22887 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} |
c19d1205 | 22888 | }; |
7ed4c4c5 | 22889 | |
c19d1205 | 22890 | struct arm_arch_option_table |
7ed4c4c5 | 22891 | { |
c19d1205 | 22892 | char *name; |
e74cfd16 PB |
22893 | const arm_feature_set value; |
22894 | const arm_feature_set default_fpu; | |
c19d1205 | 22895 | }; |
7ed4c4c5 | 22896 | |
c19d1205 ZW |
22897 | /* This list should, at a minimum, contain all the architecture names |
22898 | recognized by GCC. */ | |
e74cfd16 | 22899 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 ZW |
22900 | { |
22901 | {"all", ARM_ANY, FPU_ARCH_FPA}, | |
22902 | {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, | |
22903 | {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, | |
22904 | {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
22905 | {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, | |
22906 | {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, | |
22907 | {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, | |
22908 | {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, | |
22909 | {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, | |
22910 | {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, | |
22911 | {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, | |
22912 | {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, | |
22913 | {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, | |
22914 | {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, | |
22915 | {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, | |
22916 | {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, | |
22917 | {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, | |
22918 | {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
22919 | {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, | |
22920 | {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, | |
22921 | {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, | |
22922 | {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, | |
22923 | {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, | |
22924 | {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, | |
22925 | {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, | |
22926 | {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, | |
7e806470 | 22927 | {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP}, |
b2a5fbdc | 22928 | {"armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP}, |
62b3e311 | 22929 | {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, |
c450d570 PB |
22930 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
22931 | Accept the non-dashed form for compatibility with old toolchains. */ | |
62b3e311 PB |
22932 | {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
22933 | {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
22934 | {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
c450d570 PB |
22935 | {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, |
22936 | {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, | |
22937 | {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, | |
9e3c6df6 | 22938 | {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP}, |
c19d1205 ZW |
22939 | {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, |
22940 | {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, | |
2d447fca | 22941 | {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, |
e74cfd16 | 22942 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
c19d1205 | 22943 | }; |
7ed4c4c5 | 22944 | |
69133863 MGD |
22945 | /* ISA extensions in the co-processor and main instruction set space. */ |
22946 | struct arm_option_extension_value_table | |
c19d1205 ZW |
22947 | { |
22948 | char *name; | |
e74cfd16 | 22949 | const arm_feature_set value; |
69133863 | 22950 | const arm_feature_set allowed_archs; |
c19d1205 | 22951 | }; |
7ed4c4c5 | 22952 | |
69133863 MGD |
22953 | /* The following table must be in alphabetical order with a NULL last entry. |
22954 | */ | |
22955 | static const struct arm_option_extension_value_table arm_extensions[] = | |
c19d1205 | 22956 | { |
eea54501 | 22957 | {"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), |
3b2f0793 | 22958 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)}, |
69133863 MGD |
22959 | {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY}, |
22960 | {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY}, | |
22961 | {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY}, | |
60e5ef9f MGD |
22962 | {"mp", ARM_FEATURE (ARM_EXT_MP, 0), |
22963 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)}, | |
b2a5fbdc MGD |
22964 | {"os", ARM_FEATURE (ARM_EXT_OS, 0), |
22965 | ARM_FEATURE (ARM_EXT_V6M, 0)}, | |
f4c65163 MGD |
22966 | {"sec", ARM_FEATURE (ARM_EXT_SEC, 0), |
22967 | ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)}, | |
90ec0d68 MGD |
22968 | {"virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | ARM_EXT_DIV, 0), |
22969 | ARM_FEATURE (ARM_EXT_V7A, 0)}, | |
69133863 | 22970 | {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY}, |
60e5ef9f | 22971 | {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} |
69133863 MGD |
22972 | }; |
22973 | ||
22974 | /* ISA floating-point and Advanced SIMD extensions. */ | |
22975 | struct arm_option_fpu_value_table | |
22976 | { | |
22977 | char *name; | |
22978 | const arm_feature_set value; | |
c19d1205 | 22979 | }; |
7ed4c4c5 | 22980 | |
c19d1205 ZW |
22981 | /* This list should, at a minimum, contain all the fpu names |
22982 | recognized by GCC. */ | |
69133863 | 22983 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
22984 | { |
22985 | {"softfpa", FPU_NONE}, | |
22986 | {"fpe", FPU_ARCH_FPE}, | |
22987 | {"fpe2", FPU_ARCH_FPE}, | |
22988 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
22989 | {"fpa", FPU_ARCH_FPA}, | |
22990 | {"fpa10", FPU_ARCH_FPA}, | |
22991 | {"fpa11", FPU_ARCH_FPA}, | |
22992 | {"arm7500fe", FPU_ARCH_FPA}, | |
22993 | {"softvfp", FPU_ARCH_VFP}, | |
22994 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
22995 | {"vfp", FPU_ARCH_VFP_V2}, | |
22996 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 22997 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
22998 | {"vfp10", FPU_ARCH_VFP_V2}, |
22999 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
23000 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
23001 | {"vfpv2", FPU_ARCH_VFP_V2}, |
23002 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 23003 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 23004 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
23005 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
23006 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
23007 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
23008 | {"arm1020t", FPU_ARCH_VFP_V1}, |
23009 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
23010 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
23011 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
23012 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 23013 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 23014 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
23015 | {"vfpv4", FPU_ARCH_VFP_V4}, |
23016 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 23017 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
62f3b8c8 | 23018 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
e74cfd16 PB |
23019 | {NULL, ARM_ARCH_NONE} |
23020 | }; | |
23021 | ||
23022 | struct arm_option_value_table | |
23023 | { | |
23024 | char *name; | |
23025 | long value; | |
c19d1205 | 23026 | }; |
7ed4c4c5 | 23027 | |
e74cfd16 | 23028 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
23029 | { |
23030 | {"hard", ARM_FLOAT_ABI_HARD}, | |
23031 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
23032 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 23033 | {NULL, 0} |
c19d1205 | 23034 | }; |
7ed4c4c5 | 23035 | |
c19d1205 | 23036 | #ifdef OBJ_ELF |
3a4a14e9 | 23037 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 23038 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
23039 | { |
23040 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
23041 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 23042 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 23043 | {NULL, 0} |
c19d1205 ZW |
23044 | }; |
23045 | #endif | |
7ed4c4c5 | 23046 | |
c19d1205 ZW |
23047 | struct arm_long_option_table |
23048 | { | |
23049 | char * option; /* Substring to match. */ | |
23050 | char * help; /* Help information. */ | |
23051 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
23052 | char * deprecated; /* If non-null, print this message. */ | |
23053 | }; | |
7ed4c4c5 | 23054 | |
c921be7d | 23055 | static bfd_boolean |
e74cfd16 | 23056 | arm_parse_extension (char * str, const arm_feature_set **opt_p) |
7ed4c4c5 | 23057 | { |
21d799b5 NC |
23058 | arm_feature_set *ext_set = (arm_feature_set *) |
23059 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 | 23060 | |
69133863 MGD |
23061 | /* We insist on extensions being specified in alphabetical order, and with |
23062 | extensions being added before being removed. We achieve this by having | |
23063 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
23064 | ADDING_VALUE variable to indicate whether we are adding an extension (1) | |
23065 | or removing it (0) and only allowing it to change in the order | |
23066 | -1 -> 1 -> 0. */ | |
23067 | const struct arm_option_extension_value_table * opt = NULL; | |
23068 | int adding_value = -1; | |
23069 | ||
e74cfd16 PB |
23070 | /* Copy the feature set, so that we can modify it. */ |
23071 | *ext_set = **opt_p; | |
23072 | *opt_p = ext_set; | |
23073 | ||
c19d1205 | 23074 | while (str != NULL && *str != 0) |
7ed4c4c5 | 23075 | { |
c19d1205 | 23076 | char * ext; |
69133863 | 23077 | size_t optlen; |
7ed4c4c5 | 23078 | |
c19d1205 ZW |
23079 | if (*str != '+') |
23080 | { | |
23081 | as_bad (_("invalid architectural extension")); | |
c921be7d | 23082 | return FALSE; |
c19d1205 | 23083 | } |
7ed4c4c5 | 23084 | |
c19d1205 ZW |
23085 | str++; |
23086 | ext = strchr (str, '+'); | |
7ed4c4c5 | 23087 | |
c19d1205 ZW |
23088 | if (ext != NULL) |
23089 | optlen = ext - str; | |
23090 | else | |
23091 | optlen = strlen (str); | |
7ed4c4c5 | 23092 | |
69133863 MGD |
23093 | if (optlen >= 2 |
23094 | && strncmp (str, "no", 2) == 0) | |
23095 | { | |
23096 | if (adding_value != 0) | |
23097 | { | |
23098 | adding_value = 0; | |
23099 | opt = arm_extensions; | |
23100 | } | |
23101 | ||
23102 | optlen -= 2; | |
23103 | str += 2; | |
23104 | } | |
23105 | else if (optlen > 0) | |
23106 | { | |
23107 | if (adding_value == -1) | |
23108 | { | |
23109 | adding_value = 1; | |
23110 | opt = arm_extensions; | |
23111 | } | |
23112 | else if (adding_value != 1) | |
23113 | { | |
23114 | as_bad (_("must specify extensions to add before specifying " | |
23115 | "those to remove")); | |
23116 | return FALSE; | |
23117 | } | |
23118 | } | |
23119 | ||
c19d1205 ZW |
23120 | if (optlen == 0) |
23121 | { | |
23122 | as_bad (_("missing architectural extension")); | |
c921be7d | 23123 | return FALSE; |
c19d1205 | 23124 | } |
7ed4c4c5 | 23125 | |
69133863 MGD |
23126 | gas_assert (adding_value != -1); |
23127 | gas_assert (opt != NULL); | |
23128 | ||
23129 | /* Scan over the options table trying to find an exact match. */ | |
23130 | for (; opt->name != NULL; opt++) | |
23131 | if (strncmp (opt->name, str, optlen) == 0 | |
23132 | && strlen (opt->name) == optlen) | |
c19d1205 | 23133 | { |
69133863 MGD |
23134 | /* Check we can apply the extension to this architecture. */ |
23135 | if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs)) | |
23136 | { | |
23137 | as_bad (_("extension does not apply to the base architecture")); | |
23138 | return FALSE; | |
23139 | } | |
23140 | ||
23141 | /* Add or remove the extension. */ | |
23142 | if (adding_value) | |
23143 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); | |
23144 | else | |
23145 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value); | |
23146 | ||
c19d1205 ZW |
23147 | break; |
23148 | } | |
7ed4c4c5 | 23149 | |
c19d1205 ZW |
23150 | if (opt->name == NULL) |
23151 | { | |
69133863 MGD |
23152 | /* Did we fail to find an extension because it wasn't specified in |
23153 | alphabetical order, or because it does not exist? */ | |
23154 | ||
23155 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
23156 | if (strncmp (opt->name, str, optlen) == 0) | |
23157 | break; | |
23158 | ||
23159 | if (opt->name == NULL) | |
23160 | as_bad (_("unknown architectural extension `%s'"), str); | |
23161 | else | |
23162 | as_bad (_("architectural extensions must be specified in " | |
23163 | "alphabetical order")); | |
23164 | ||
c921be7d | 23165 | return FALSE; |
c19d1205 | 23166 | } |
69133863 MGD |
23167 | else |
23168 | { | |
23169 | /* We should skip the extension we've just matched the next time | |
23170 | round. */ | |
23171 | opt++; | |
23172 | } | |
7ed4c4c5 | 23173 | |
c19d1205 ZW |
23174 | str = ext; |
23175 | }; | |
7ed4c4c5 | 23176 | |
c921be7d | 23177 | return TRUE; |
c19d1205 | 23178 | } |
7ed4c4c5 | 23179 | |
c921be7d | 23180 | static bfd_boolean |
c19d1205 | 23181 | arm_parse_cpu (char * str) |
7ed4c4c5 | 23182 | { |
e74cfd16 | 23183 | const struct arm_cpu_option_table * opt; |
c19d1205 ZW |
23184 | char * ext = strchr (str, '+'); |
23185 | int optlen; | |
7ed4c4c5 | 23186 | |
c19d1205 ZW |
23187 | if (ext != NULL) |
23188 | optlen = ext - str; | |
7ed4c4c5 | 23189 | else |
c19d1205 | 23190 | optlen = strlen (str); |
7ed4c4c5 | 23191 | |
c19d1205 | 23192 | if (optlen == 0) |
7ed4c4c5 | 23193 | { |
c19d1205 | 23194 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 23195 | return FALSE; |
7ed4c4c5 NC |
23196 | } |
23197 | ||
c19d1205 ZW |
23198 | for (opt = arm_cpus; opt->name != NULL; opt++) |
23199 | if (strncmp (opt->name, str, optlen) == 0) | |
23200 | { | |
e74cfd16 PB |
23201 | mcpu_cpu_opt = &opt->value; |
23202 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 23203 | if (opt->canonical_name) |
5f4273c7 | 23204 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
23205 | else |
23206 | { | |
23207 | int i; | |
c921be7d | 23208 | |
ee065d83 PB |
23209 | for (i = 0; i < optlen; i++) |
23210 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
23211 | selected_cpu_name[i] = 0; | |
23212 | } | |
7ed4c4c5 | 23213 | |
c19d1205 ZW |
23214 | if (ext != NULL) |
23215 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 23216 | |
c921be7d | 23217 | return TRUE; |
c19d1205 | 23218 | } |
7ed4c4c5 | 23219 | |
c19d1205 | 23220 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 23221 | return FALSE; |
7ed4c4c5 NC |
23222 | } |
23223 | ||
c921be7d | 23224 | static bfd_boolean |
c19d1205 | 23225 | arm_parse_arch (char * str) |
7ed4c4c5 | 23226 | { |
e74cfd16 | 23227 | const struct arm_arch_option_table *opt; |
c19d1205 ZW |
23228 | char *ext = strchr (str, '+'); |
23229 | int optlen; | |
7ed4c4c5 | 23230 | |
c19d1205 ZW |
23231 | if (ext != NULL) |
23232 | optlen = ext - str; | |
7ed4c4c5 | 23233 | else |
c19d1205 | 23234 | optlen = strlen (str); |
7ed4c4c5 | 23235 | |
c19d1205 | 23236 | if (optlen == 0) |
7ed4c4c5 | 23237 | { |
c19d1205 | 23238 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 23239 | return FALSE; |
7ed4c4c5 NC |
23240 | } |
23241 | ||
c19d1205 | 23242 | for (opt = arm_archs; opt->name != NULL; opt++) |
69133863 | 23243 | if (strncmp (opt->name, str, optlen) == 0) |
c19d1205 | 23244 | { |
e74cfd16 PB |
23245 | march_cpu_opt = &opt->value; |
23246 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 23247 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 23248 | |
c19d1205 ZW |
23249 | if (ext != NULL) |
23250 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 23251 | |
c921be7d | 23252 | return TRUE; |
c19d1205 ZW |
23253 | } |
23254 | ||
23255 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 23256 | return FALSE; |
7ed4c4c5 | 23257 | } |
eb043451 | 23258 | |
c921be7d | 23259 | static bfd_boolean |
c19d1205 ZW |
23260 | arm_parse_fpu (char * str) |
23261 | { | |
69133863 | 23262 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 23263 | |
c19d1205 ZW |
23264 | for (opt = arm_fpus; opt->name != NULL; opt++) |
23265 | if (streq (opt->name, str)) | |
23266 | { | |
e74cfd16 | 23267 | mfpu_opt = &opt->value; |
c921be7d | 23268 | return TRUE; |
c19d1205 | 23269 | } |
b99bd4ef | 23270 | |
c19d1205 | 23271 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 23272 | return FALSE; |
c19d1205 ZW |
23273 | } |
23274 | ||
c921be7d | 23275 | static bfd_boolean |
c19d1205 | 23276 | arm_parse_float_abi (char * str) |
b99bd4ef | 23277 | { |
e74cfd16 | 23278 | const struct arm_option_value_table * opt; |
b99bd4ef | 23279 | |
c19d1205 ZW |
23280 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
23281 | if (streq (opt->name, str)) | |
23282 | { | |
23283 | mfloat_abi_opt = opt->value; | |
c921be7d | 23284 | return TRUE; |
c19d1205 | 23285 | } |
cc8a6dd0 | 23286 | |
c19d1205 | 23287 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 23288 | return FALSE; |
c19d1205 | 23289 | } |
b99bd4ef | 23290 | |
c19d1205 | 23291 | #ifdef OBJ_ELF |
c921be7d | 23292 | static bfd_boolean |
c19d1205 ZW |
23293 | arm_parse_eabi (char * str) |
23294 | { | |
e74cfd16 | 23295 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 23296 | |
c19d1205 ZW |
23297 | for (opt = arm_eabis; opt->name != NULL; opt++) |
23298 | if (streq (opt->name, str)) | |
23299 | { | |
23300 | meabi_flags = opt->value; | |
c921be7d | 23301 | return TRUE; |
c19d1205 ZW |
23302 | } |
23303 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 23304 | return FALSE; |
c19d1205 ZW |
23305 | } |
23306 | #endif | |
cc8a6dd0 | 23307 | |
c921be7d | 23308 | static bfd_boolean |
e07e6e58 NC |
23309 | arm_parse_it_mode (char * str) |
23310 | { | |
c921be7d | 23311 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
23312 | |
23313 | if (streq ("arm", str)) | |
23314 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
23315 | else if (streq ("thumb", str)) | |
23316 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
23317 | else if (streq ("always", str)) | |
23318 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
23319 | else if (streq ("never", str)) | |
23320 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
23321 | else | |
23322 | { | |
23323 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
23324 | "arm, thumb, always, or never."), str); | |
c921be7d | 23325 | ret = FALSE; |
e07e6e58 NC |
23326 | } |
23327 | ||
23328 | return ret; | |
23329 | } | |
23330 | ||
c19d1205 ZW |
23331 | struct arm_long_option_table arm_long_opts[] = |
23332 | { | |
23333 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
23334 | arm_parse_cpu, NULL}, | |
23335 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
23336 | arm_parse_arch, NULL}, | |
23337 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
23338 | arm_parse_fpu, NULL}, | |
23339 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
23340 | arm_parse_float_abi, NULL}, | |
23341 | #ifdef OBJ_ELF | |
7fac0536 | 23342 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
23343 | arm_parse_eabi, NULL}, |
23344 | #endif | |
e07e6e58 NC |
23345 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
23346 | arm_parse_it_mode, NULL}, | |
c19d1205 ZW |
23347 | {NULL, NULL, 0, NULL} |
23348 | }; | |
cc8a6dd0 | 23349 | |
c19d1205 ZW |
23350 | int |
23351 | md_parse_option (int c, char * arg) | |
23352 | { | |
23353 | struct arm_option_table *opt; | |
e74cfd16 | 23354 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 23355 | struct arm_long_option_table *lopt; |
b99bd4ef | 23356 | |
c19d1205 | 23357 | switch (c) |
b99bd4ef | 23358 | { |
c19d1205 ZW |
23359 | #ifdef OPTION_EB |
23360 | case OPTION_EB: | |
23361 | target_big_endian = 1; | |
23362 | break; | |
23363 | #endif | |
cc8a6dd0 | 23364 | |
c19d1205 ZW |
23365 | #ifdef OPTION_EL |
23366 | case OPTION_EL: | |
23367 | target_big_endian = 0; | |
23368 | break; | |
23369 | #endif | |
b99bd4ef | 23370 | |
845b51d6 PB |
23371 | case OPTION_FIX_V4BX: |
23372 | fix_v4bx = TRUE; | |
23373 | break; | |
23374 | ||
c19d1205 ZW |
23375 | case 'a': |
23376 | /* Listing option. Just ignore these, we don't support additional | |
23377 | ones. */ | |
23378 | return 0; | |
b99bd4ef | 23379 | |
c19d1205 ZW |
23380 | default: |
23381 | for (opt = arm_opts; opt->option != NULL; opt++) | |
23382 | { | |
23383 | if (c == opt->option[0] | |
23384 | && ((arg == NULL && opt->option[1] == 0) | |
23385 | || streq (arg, opt->option + 1))) | |
23386 | { | |
c19d1205 | 23387 | /* If the option is deprecated, tell the user. */ |
278df34e | 23388 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
23389 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
23390 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 23391 | |
c19d1205 ZW |
23392 | if (opt->var != NULL) |
23393 | *opt->var = opt->value; | |
cc8a6dd0 | 23394 | |
c19d1205 ZW |
23395 | return 1; |
23396 | } | |
23397 | } | |
b99bd4ef | 23398 | |
e74cfd16 PB |
23399 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
23400 | { | |
23401 | if (c == fopt->option[0] | |
23402 | && ((arg == NULL && fopt->option[1] == 0) | |
23403 | || streq (arg, fopt->option + 1))) | |
23404 | { | |
e74cfd16 | 23405 | /* If the option is deprecated, tell the user. */ |
278df34e | 23406 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
23407 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
23408 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
23409 | |
23410 | if (fopt->var != NULL) | |
23411 | *fopt->var = &fopt->value; | |
23412 | ||
23413 | return 1; | |
23414 | } | |
23415 | } | |
23416 | ||
c19d1205 ZW |
23417 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
23418 | { | |
23419 | /* These options are expected to have an argument. */ | |
23420 | if (c == lopt->option[0] | |
23421 | && arg != NULL | |
23422 | && strncmp (arg, lopt->option + 1, | |
23423 | strlen (lopt->option + 1)) == 0) | |
23424 | { | |
c19d1205 | 23425 | /* If the option is deprecated, tell the user. */ |
278df34e | 23426 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
23427 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
23428 | _(lopt->deprecated)); | |
b99bd4ef | 23429 | |
c19d1205 ZW |
23430 | /* Call the sup-option parser. */ |
23431 | return lopt->func (arg + strlen (lopt->option) - 1); | |
23432 | } | |
23433 | } | |
a737bd4d | 23434 | |
c19d1205 ZW |
23435 | return 0; |
23436 | } | |
a394c00f | 23437 | |
c19d1205 ZW |
23438 | return 1; |
23439 | } | |
a394c00f | 23440 | |
c19d1205 ZW |
23441 | void |
23442 | md_show_usage (FILE * fp) | |
a394c00f | 23443 | { |
c19d1205 ZW |
23444 | struct arm_option_table *opt; |
23445 | struct arm_long_option_table *lopt; | |
a394c00f | 23446 | |
c19d1205 | 23447 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 23448 | |
c19d1205 ZW |
23449 | for (opt = arm_opts; opt->option != NULL; opt++) |
23450 | if (opt->help != NULL) | |
23451 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 23452 | |
c19d1205 ZW |
23453 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
23454 | if (lopt->help != NULL) | |
23455 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 23456 | |
c19d1205 ZW |
23457 | #ifdef OPTION_EB |
23458 | fprintf (fp, _("\ | |
23459 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
23460 | #endif |
23461 | ||
c19d1205 ZW |
23462 | #ifdef OPTION_EL |
23463 | fprintf (fp, _("\ | |
23464 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 23465 | #endif |
845b51d6 PB |
23466 | |
23467 | fprintf (fp, _("\ | |
23468 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 23469 | } |
ee065d83 PB |
23470 | |
23471 | ||
23472 | #ifdef OBJ_ELF | |
62b3e311 PB |
23473 | typedef struct |
23474 | { | |
23475 | int val; | |
23476 | arm_feature_set flags; | |
23477 | } cpu_arch_ver_table; | |
23478 | ||
23479 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
23480 | least features first. */ | |
23481 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
23482 | { | |
23483 | {1, ARM_ARCH_V4}, | |
23484 | {2, ARM_ARCH_V4T}, | |
23485 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 23486 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
23487 | {4, ARM_ARCH_V5TE}, |
23488 | {5, ARM_ARCH_V5TEJ}, | |
23489 | {6, ARM_ARCH_V6}, | |
7e806470 | 23490 | {9, ARM_ARCH_V6K}, |
f4c65163 | 23491 | {7, ARM_ARCH_V6Z}, |
91e22acd | 23492 | {11, ARM_ARCH_V6M}, |
b2a5fbdc | 23493 | {12, ARM_ARCH_V6SM}, |
7e806470 | 23494 | {8, ARM_ARCH_V6T2}, |
62b3e311 PB |
23495 | {10, ARM_ARCH_V7A}, |
23496 | {10, ARM_ARCH_V7R}, | |
23497 | {10, ARM_ARCH_V7M}, | |
23498 | {0, ARM_ARCH_NONE} | |
23499 | }; | |
23500 | ||
ee3c0378 AS |
23501 | /* Set an attribute if it has not already been set by the user. */ |
23502 | static void | |
23503 | aeabi_set_attribute_int (int tag, int value) | |
23504 | { | |
23505 | if (tag < 1 | |
23506 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
23507 | || !attributes_set_explicitly[tag]) | |
23508 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
23509 | } | |
23510 | ||
23511 | static void | |
23512 | aeabi_set_attribute_string (int tag, const char *value) | |
23513 | { | |
23514 | if (tag < 1 | |
23515 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
23516 | || !attributes_set_explicitly[tag]) | |
23517 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
23518 | } | |
23519 | ||
ee065d83 PB |
23520 | /* Set the public EABI object attributes. */ |
23521 | static void | |
23522 | aeabi_set_public_attributes (void) | |
23523 | { | |
23524 | int arch; | |
90ec0d68 | 23525 | int virt_sec = 0; |
e74cfd16 | 23526 | arm_feature_set flags; |
62b3e311 PB |
23527 | arm_feature_set tmp; |
23528 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
23529 | |
23530 | /* Choose the architecture based on the capabilities of the requested cpu | |
23531 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
23532 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
23533 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
23534 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
7a1d4c38 PB |
23535 | /*Allow the user to override the reported architecture. */ |
23536 | if (object_arch) | |
23537 | { | |
23538 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
23539 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
23540 | } | |
23541 | ||
251665fc MGD |
23542 | /* We need to make sure that the attributes do not identify us as v6S-M |
23543 | when the only v6S-M feature in use is the Operating System Extensions. */ | |
23544 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) | |
23545 | if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) | |
23546 | ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); | |
23547 | ||
62b3e311 PB |
23548 | tmp = flags; |
23549 | arch = 0; | |
23550 | for (p = cpu_arch_ver; p->val; p++) | |
23551 | { | |
23552 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
23553 | { | |
23554 | arch = p->val; | |
23555 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
23556 | } | |
23557 | } | |
ee065d83 | 23558 | |
9e3c6df6 PB |
23559 | /* The table lookup above finds the last architecture to contribute |
23560 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
23561 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
23562 | We can not search for the last entry which is entirely used, | |
23563 | because if no CPU is specified we build up only those flags | |
23564 | actually used. Perhaps we should separate out the specified | |
23565 | and implicit cases. Avoid taking this path for -march=all by | |
23566 | checking for contradictory v7-A / v7-M features. */ | |
23567 | if (arch == 10 | |
23568 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
23569 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
23570 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
23571 | arch = 13; | |
23572 | ||
ee065d83 PB |
23573 | /* Tag_CPU_name. */ |
23574 | if (selected_cpu_name[0]) | |
23575 | { | |
91d6fa6a | 23576 | char *q; |
ee065d83 | 23577 | |
91d6fa6a NC |
23578 | q = selected_cpu_name; |
23579 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
23580 | { |
23581 | int i; | |
5f4273c7 | 23582 | |
91d6fa6a NC |
23583 | q += 4; |
23584 | for (i = 0; q[i]; i++) | |
23585 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 23586 | } |
91d6fa6a | 23587 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 23588 | } |
62f3b8c8 | 23589 | |
ee065d83 | 23590 | /* Tag_CPU_arch. */ |
ee3c0378 | 23591 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 23592 | |
62b3e311 PB |
23593 | /* Tag_CPU_arch_profile. */ |
23594 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
ee3c0378 | 23595 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A'); |
62b3e311 | 23596 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
ee3c0378 | 23597 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R'); |
7e806470 | 23598 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
ee3c0378 | 23599 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M'); |
62f3b8c8 | 23600 | |
ee065d83 | 23601 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
23602 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
23603 | || arch == 0) | |
23604 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 23605 | |
ee065d83 | 23606 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
23607 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
23608 | || arch == 0) | |
23609 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
23610 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 23611 | |
ee065d83 | 23612 | /* Tag_VFP_arch. */ |
62f3b8c8 PB |
23613 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
23614 | aeabi_set_attribute_int (Tag_VFP_arch, | |
23615 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
23616 | ? 5 : 6); | |
23617 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
ee3c0378 | 23618 | aeabi_set_attribute_int (Tag_VFP_arch, 3); |
ada65aa3 | 23619 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
ee3c0378 AS |
23620 | aeabi_set_attribute_int (Tag_VFP_arch, 4); |
23621 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) | |
23622 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
23623 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
23624 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) | |
23625 | aeabi_set_attribute_int (Tag_VFP_arch, 1); | |
62f3b8c8 | 23626 | |
4547cb56 NC |
23627 | /* Tag_ABI_HardFP_use. */ |
23628 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
23629 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
23630 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
23631 | ||
ee065d83 | 23632 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
23633 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
23634 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
23635 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
23636 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 23637 | |
ee3c0378 | 23638 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
8e79c3df | 23639 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) |
62f3b8c8 PB |
23640 | aeabi_set_attribute_int |
23641 | (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma) | |
23642 | ? 2 : 1)); | |
23643 | ||
ee3c0378 | 23644 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
62f3b8c8 | 23645 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16)) |
ee3c0378 | 23646 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 NC |
23647 | |
23648 | /* Tag_DIV_use. */ | |
eea54501 MGD |
23649 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)) |
23650 | aeabi_set_attribute_int (Tag_DIV_use, 2); | |
23651 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div)) | |
4547cb56 | 23652 | aeabi_set_attribute_int (Tag_DIV_use, 0); |
4547cb56 NC |
23653 | else |
23654 | aeabi_set_attribute_int (Tag_DIV_use, 1); | |
60e5ef9f MGD |
23655 | |
23656 | /* Tag_MP_extension_use. */ | |
23657 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
23658 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
23659 | |
23660 | /* Tag Virtualization_use. */ | |
23661 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
23662 | virt_sec |= 1; |
23663 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
23664 | virt_sec |= 2; | |
23665 | if (virt_sec != 0) | |
23666 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
23667 | } |
23668 | ||
104d59d1 | 23669 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
23670 | void |
23671 | arm_md_end (void) | |
23672 | { | |
ee065d83 PB |
23673 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
23674 | return; | |
23675 | ||
23676 | aeabi_set_public_attributes (); | |
ee065d83 | 23677 | } |
8463be01 | 23678 | #endif /* OBJ_ELF */ |
ee065d83 PB |
23679 | |
23680 | ||
23681 | /* Parse a .cpu directive. */ | |
23682 | ||
23683 | static void | |
23684 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
23685 | { | |
e74cfd16 | 23686 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
23687 | char *name; |
23688 | char saved_char; | |
23689 | ||
23690 | name = input_line_pointer; | |
5f4273c7 | 23691 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23692 | input_line_pointer++; |
23693 | saved_char = *input_line_pointer; | |
23694 | *input_line_pointer = 0; | |
23695 | ||
23696 | /* Skip the first "all" entry. */ | |
23697 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
23698 | if (streq (opt->name, name)) | |
23699 | { | |
e74cfd16 PB |
23700 | mcpu_cpu_opt = &opt->value; |
23701 | selected_cpu = opt->value; | |
ee065d83 | 23702 | if (opt->canonical_name) |
5f4273c7 | 23703 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
23704 | else |
23705 | { | |
23706 | int i; | |
23707 | for (i = 0; opt->name[i]; i++) | |
23708 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
23709 | selected_cpu_name[i] = 0; | |
23710 | } | |
e74cfd16 | 23711 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
23712 | *input_line_pointer = saved_char; |
23713 | demand_empty_rest_of_line (); | |
23714 | return; | |
23715 | } | |
23716 | as_bad (_("unknown cpu `%s'"), name); | |
23717 | *input_line_pointer = saved_char; | |
23718 | ignore_rest_of_line (); | |
23719 | } | |
23720 | ||
23721 | ||
23722 | /* Parse a .arch directive. */ | |
23723 | ||
23724 | static void | |
23725 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
23726 | { | |
e74cfd16 | 23727 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
23728 | char saved_char; |
23729 | char *name; | |
23730 | ||
23731 | name = input_line_pointer; | |
5f4273c7 | 23732 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23733 | input_line_pointer++; |
23734 | saved_char = *input_line_pointer; | |
23735 | *input_line_pointer = 0; | |
23736 | ||
23737 | /* Skip the first "all" entry. */ | |
23738 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
23739 | if (streq (opt->name, name)) | |
23740 | { | |
e74cfd16 PB |
23741 | mcpu_cpu_opt = &opt->value; |
23742 | selected_cpu = opt->value; | |
5f4273c7 | 23743 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 23744 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
23745 | *input_line_pointer = saved_char; |
23746 | demand_empty_rest_of_line (); | |
23747 | return; | |
23748 | } | |
23749 | ||
23750 | as_bad (_("unknown architecture `%s'\n"), name); | |
23751 | *input_line_pointer = saved_char; | |
23752 | ignore_rest_of_line (); | |
23753 | } | |
23754 | ||
23755 | ||
7a1d4c38 PB |
23756 | /* Parse a .object_arch directive. */ |
23757 | ||
23758 | static void | |
23759 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
23760 | { | |
23761 | const struct arm_arch_option_table *opt; | |
23762 | char saved_char; | |
23763 | char *name; | |
23764 | ||
23765 | name = input_line_pointer; | |
5f4273c7 | 23766 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
23767 | input_line_pointer++; |
23768 | saved_char = *input_line_pointer; | |
23769 | *input_line_pointer = 0; | |
23770 | ||
23771 | /* Skip the first "all" entry. */ | |
23772 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
23773 | if (streq (opt->name, name)) | |
23774 | { | |
23775 | object_arch = &opt->value; | |
23776 | *input_line_pointer = saved_char; | |
23777 | demand_empty_rest_of_line (); | |
23778 | return; | |
23779 | } | |
23780 | ||
23781 | as_bad (_("unknown architecture `%s'\n"), name); | |
23782 | *input_line_pointer = saved_char; | |
23783 | ignore_rest_of_line (); | |
23784 | } | |
23785 | ||
69133863 MGD |
23786 | /* Parse a .arch_extension directive. */ |
23787 | ||
23788 | static void | |
23789 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
23790 | { | |
23791 | const struct arm_option_extension_value_table *opt; | |
23792 | char saved_char; | |
23793 | char *name; | |
23794 | int adding_value = 1; | |
23795 | ||
23796 | name = input_line_pointer; | |
23797 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
23798 | input_line_pointer++; | |
23799 | saved_char = *input_line_pointer; | |
23800 | *input_line_pointer = 0; | |
23801 | ||
23802 | if (strlen (name) >= 2 | |
23803 | && strncmp (name, "no", 2) == 0) | |
23804 | { | |
23805 | adding_value = 0; | |
23806 | name += 2; | |
23807 | } | |
23808 | ||
23809 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
23810 | if (streq (opt->name, name)) | |
23811 | { | |
23812 | if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs)) | |
23813 | { | |
23814 | as_bad (_("architectural extension `%s' is not allowed for the " | |
23815 | "current base architecture"), name); | |
23816 | break; | |
23817 | } | |
23818 | ||
23819 | if (adding_value) | |
23820 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value); | |
23821 | else | |
23822 | ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value); | |
23823 | ||
23824 | mcpu_cpu_opt = &selected_cpu; | |
23825 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
23826 | *input_line_pointer = saved_char; | |
23827 | demand_empty_rest_of_line (); | |
23828 | return; | |
23829 | } | |
23830 | ||
23831 | if (opt->name == NULL) | |
23832 | as_bad (_("unknown architecture `%s'\n"), name); | |
23833 | ||
23834 | *input_line_pointer = saved_char; | |
23835 | ignore_rest_of_line (); | |
23836 | } | |
23837 | ||
ee065d83 PB |
23838 | /* Parse a .fpu directive. */ |
23839 | ||
23840 | static void | |
23841 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
23842 | { | |
69133863 | 23843 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
23844 | char saved_char; |
23845 | char *name; | |
23846 | ||
23847 | name = input_line_pointer; | |
5f4273c7 | 23848 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23849 | input_line_pointer++; |
23850 | saved_char = *input_line_pointer; | |
23851 | *input_line_pointer = 0; | |
5f4273c7 | 23852 | |
ee065d83 PB |
23853 | for (opt = arm_fpus; opt->name != NULL; opt++) |
23854 | if (streq (opt->name, name)) | |
23855 | { | |
e74cfd16 PB |
23856 | mfpu_opt = &opt->value; |
23857 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
23858 | *input_line_pointer = saved_char; |
23859 | demand_empty_rest_of_line (); | |
23860 | return; | |
23861 | } | |
23862 | ||
23863 | as_bad (_("unknown floating point format `%s'\n"), name); | |
23864 | *input_line_pointer = saved_char; | |
23865 | ignore_rest_of_line (); | |
23866 | } | |
ee065d83 | 23867 | |
794ba86a | 23868 | /* Copy symbol information. */ |
f31fef98 | 23869 | |
794ba86a DJ |
23870 | void |
23871 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
23872 | { | |
23873 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
23874 | } | |
e04befd0 | 23875 | |
f31fef98 | 23876 | #ifdef OBJ_ELF |
e04befd0 AS |
23877 | /* Given a symbolic attribute NAME, return the proper integer value. |
23878 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 23879 | |
e04befd0 AS |
23880 | int |
23881 | arm_convert_symbolic_attribute (const char *name) | |
23882 | { | |
f31fef98 NC |
23883 | static const struct |
23884 | { | |
23885 | const char * name; | |
23886 | const int tag; | |
23887 | } | |
23888 | attribute_table[] = | |
23889 | { | |
23890 | /* When you modify this table you should | |
23891 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 23892 | #define T(tag) {#tag, tag} |
f31fef98 NC |
23893 | T (Tag_CPU_raw_name), |
23894 | T (Tag_CPU_name), | |
23895 | T (Tag_CPU_arch), | |
23896 | T (Tag_CPU_arch_profile), | |
23897 | T (Tag_ARM_ISA_use), | |
23898 | T (Tag_THUMB_ISA_use), | |
75375b3e | 23899 | T (Tag_FP_arch), |
f31fef98 NC |
23900 | T (Tag_VFP_arch), |
23901 | T (Tag_WMMX_arch), | |
23902 | T (Tag_Advanced_SIMD_arch), | |
23903 | T (Tag_PCS_config), | |
23904 | T (Tag_ABI_PCS_R9_use), | |
23905 | T (Tag_ABI_PCS_RW_data), | |
23906 | T (Tag_ABI_PCS_RO_data), | |
23907 | T (Tag_ABI_PCS_GOT_use), | |
23908 | T (Tag_ABI_PCS_wchar_t), | |
23909 | T (Tag_ABI_FP_rounding), | |
23910 | T (Tag_ABI_FP_denormal), | |
23911 | T (Tag_ABI_FP_exceptions), | |
23912 | T (Tag_ABI_FP_user_exceptions), | |
23913 | T (Tag_ABI_FP_number_model), | |
75375b3e | 23914 | T (Tag_ABI_align_needed), |
f31fef98 | 23915 | T (Tag_ABI_align8_needed), |
75375b3e | 23916 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
23917 | T (Tag_ABI_align8_preserved), |
23918 | T (Tag_ABI_enum_size), | |
23919 | T (Tag_ABI_HardFP_use), | |
23920 | T (Tag_ABI_VFP_args), | |
23921 | T (Tag_ABI_WMMX_args), | |
23922 | T (Tag_ABI_optimization_goals), | |
23923 | T (Tag_ABI_FP_optimization_goals), | |
23924 | T (Tag_compatibility), | |
23925 | T (Tag_CPU_unaligned_access), | |
75375b3e | 23926 | T (Tag_FP_HP_extension), |
f31fef98 NC |
23927 | T (Tag_VFP_HP_extension), |
23928 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
23929 | T (Tag_MPextension_use), |
23930 | T (Tag_DIV_use), | |
f31fef98 NC |
23931 | T (Tag_nodefaults), |
23932 | T (Tag_also_compatible_with), | |
23933 | T (Tag_conformance), | |
23934 | T (Tag_T2EE_use), | |
23935 | T (Tag_Virtualization_use), | |
cd21e546 | 23936 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 23937 | #undef T |
f31fef98 | 23938 | }; |
e04befd0 AS |
23939 | unsigned int i; |
23940 | ||
23941 | if (name == NULL) | |
23942 | return -1; | |
23943 | ||
f31fef98 | 23944 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 23945 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
23946 | return attribute_table[i].tag; |
23947 | ||
23948 | return -1; | |
23949 | } | |
267bf995 RR |
23950 | |
23951 | ||
23952 | /* Apply sym value for relocations only in the case that | |
23953 | they are for local symbols and you have the respective | |
23954 | architectural feature for blx and simple switches. */ | |
23955 | int | |
23956 | arm_apply_sym_value (struct fix * fixP) | |
23957 | { | |
23958 | if (fixP->fx_addsy | |
23959 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
34e77a92 | 23960 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
23961 | { |
23962 | switch (fixP->fx_r_type) | |
23963 | { | |
23964 | case BFD_RELOC_ARM_PCREL_BLX: | |
23965 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
23966 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
23967 | return 1; | |
23968 | break; | |
23969 | ||
23970 | case BFD_RELOC_ARM_PCREL_CALL: | |
23971 | case BFD_RELOC_THUMB_PCREL_BLX: | |
23972 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
23973 | return 1; | |
23974 | break; | |
23975 | ||
23976 | default: | |
23977 | break; | |
23978 | } | |
23979 | ||
23980 | } | |
23981 | return 0; | |
23982 | } | |
f31fef98 | 23983 | #endif /* OBJ_ELF */ |