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7be9a312 MH |
1 | /* tc-d10v.c -- Assembler code for the Mitsubishi D10V |
2 | ||
3 | Copyright (C) 1996 Free Software Foundation. | |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <ctype.h> | |
24 | #include "as.h" | |
25 | #include "subsegs.h" | |
26 | #include "opcode/d10v.h" | |
27 | #include "elf/ppc.h" | |
28 | ||
29 | const char comment_chars[] = "#;"; | |
30 | const char line_comment_chars[] = "#"; | |
31 | const char line_separator_chars[] = ""; | |
32 | const char *md_shortopts = ""; | |
33 | const char EXP_CHARS[] = "eE"; | |
34 | const char FLT_CHARS[] = "dD"; | |
35 | ||
0ef32559 MH |
36 | |
37 | /* fixups */ | |
38 | #define MAX_INSN_FIXUPS (5) | |
39 | struct d10v_fixup | |
40 | { | |
41 | expressionS exp; | |
42 | bfd_reloc_code_real_type reloc; | |
43 | }; | |
44 | ||
45 | typedef struct _fixups | |
46 | { | |
47 | int fc; | |
48 | struct d10v_fixup fix[MAX_INSN_FIXUPS]; | |
49 | struct _fixups *next; | |
50 | } Fixups; | |
51 | ||
52 | static Fixups FixUps[2]; | |
53 | static Fixups *fixups; | |
54 | ||
7be9a312 MH |
55 | /* local functions */ |
56 | static int reg_name_search PARAMS ((char *name)); | |
0ef32559 | 57 | static int register_name PARAMS ((expressionS *expressionP)); |
7be9a312 MH |
58 | static int postfix PARAMS ((char *p)); |
59 | static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op)); | |
60 | static int get_operands PARAMS ((expressionS exp[])); | |
61 | static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers)); | |
0ef32559 MH |
62 | static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); |
63 | static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); | |
7be9a312 | 64 | static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, |
0ef32559 | 65 | struct d10v_opcode *opcode2, unsigned long insn2, int exec_type, Fixups *fx)); |
7be9a312 | 66 | static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode)); |
0ef32559 MH |
67 | static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type, |
68 | offsetT value, int left)); | |
7be9a312 | 69 | |
7be9a312 MH |
70 | |
71 | struct option md_longopts[] = { | |
72 | {NULL, no_argument, NULL, 0} | |
73 | }; | |
74 | size_t md_longopts_size = sizeof(md_longopts); | |
75 | ||
76 | /* The target specific pseudo-ops which we support. */ | |
77 | const pseudo_typeS md_pseudo_table[] = | |
78 | { | |
7be9a312 MH |
79 | { NULL, NULL, 0 } |
80 | }; | |
81 | ||
82 | /* Opcode hash table. */ | |
83 | static struct hash_control *d10v_hash; | |
84 | ||
7be9a312 MH |
85 | /* reg_name_search does a binary search of the pre_defined_registers |
86 | array to see if "name" is a valid regiter name. Returns the register | |
87 | number from the array on success, or -1 on failure. */ | |
88 | ||
89 | static int | |
90 | reg_name_search (name) | |
91 | char *name; | |
92 | { | |
93 | int middle, low, high; | |
94 | int cmp; | |
95 | ||
96 | low = 0; | |
0ef32559 | 97 | high = reg_name_cnt() - 1; |
7be9a312 MH |
98 | |
99 | do | |
100 | { | |
101 | middle = (low + high) / 2; | |
102 | cmp = strcasecmp (name, pre_defined_registers[middle].name); | |
103 | if (cmp < 0) | |
104 | high = middle - 1; | |
105 | else if (cmp > 0) | |
106 | low = middle + 1; | |
107 | else | |
108 | return pre_defined_registers[middle].value; | |
109 | } | |
110 | while (low <= high); | |
111 | return -1; | |
112 | } | |
113 | ||
0ef32559 MH |
114 | /* register_name() checks the string at input_line_pointer |
115 | to see if it is a valid register name */ | |
7be9a312 | 116 | |
0ef32559 | 117 | static int |
7be9a312 MH |
118 | register_name (expressionP) |
119 | expressionS *expressionP; | |
120 | { | |
121 | int reg_number; | |
0ef32559 MH |
122 | char c, *p = input_line_pointer; |
123 | ||
124 | while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')') | |
125 | p++; | |
7be9a312 | 126 | |
0ef32559 MH |
127 | c = *p; |
128 | if (c) | |
129 | *p++ = 0; | |
7be9a312 | 130 | |
0ef32559 MH |
131 | /* look to see if it's in the register table */ |
132 | reg_number = reg_name_search (input_line_pointer); | |
133 | if (reg_number >= 0) | |
134 | { | |
135 | expressionP->X_op = O_register; | |
136 | /* temporarily store a pointer to the string here */ | |
137 | expressionP->X_op_symbol = (struct symbol *)input_line_pointer; | |
138 | expressionP->X_add_number = reg_number; | |
139 | input_line_pointer = p; | |
140 | return 1; | |
7be9a312 | 141 | } |
0ef32559 MH |
142 | if (c) |
143 | *(p-1) = c; | |
144 | return 0; | |
7be9a312 MH |
145 | } |
146 | ||
147 | void | |
148 | md_show_usage (stream) | |
149 | FILE *stream; | |
150 | { | |
151 | fprintf(stream, "D10V options:\n\ | |
152 | none yet\n"); | |
153 | } | |
154 | ||
155 | int | |
156 | md_parse_option (c, arg) | |
157 | int c; | |
158 | char *arg; | |
159 | { | |
160 | return 0; | |
161 | } | |
162 | ||
163 | symbolS * | |
164 | md_undefined_symbol (name) | |
165 | char *name; | |
166 | { | |
167 | return 0; | |
168 | } | |
169 | ||
170 | char * | |
171 | md_atof (type, litp, sizep) | |
172 | int type; | |
173 | char *litp; | |
174 | int *sizep; | |
175 | { | |
176 | return ""; | |
177 | } | |
178 | ||
179 | void | |
180 | md_convert_frag (abfd, sec, fragP) | |
181 | bfd *abfd; | |
182 | asection *sec; | |
183 | fragS *fragP; | |
184 | { | |
0ef32559 | 185 | printf ("call to md_convert_frag \n"); |
7be9a312 MH |
186 | abort (); |
187 | } | |
188 | ||
189 | valueT | |
190 | md_section_align (seg, addr) | |
191 | asection *seg; | |
192 | valueT addr; | |
193 | { | |
194 | int align = bfd_get_section_alignment (stdoutput, seg); | |
195 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
196 | } | |
197 | ||
0ef32559 | 198 | |
7be9a312 MH |
199 | void |
200 | md_begin () | |
201 | { | |
202 | char *prev_name = ""; | |
203 | struct d10v_opcode *opcode; | |
204 | d10v_hash = hash_new(); | |
205 | ||
206 | /* Insert unique names into hash table. The D10v instruction set | |
207 | has many identical opcode names that have different opcodes based | |
208 | on the operands. This hash table then provides a quick index to | |
209 | the first opcode with a particular name in the opcode table. */ | |
210 | ||
211 | for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++) | |
212 | { | |
213 | if (strcmp (prev_name, opcode->name)) | |
214 | { | |
215 | prev_name = (char *)opcode->name; | |
216 | hash_insert (d10v_hash, opcode->name, (char *) opcode); | |
217 | } | |
218 | } | |
0ef32559 MH |
219 | |
220 | fixups = &FixUps[0]; | |
221 | FixUps[0].next = &FixUps[1]; | |
222 | FixUps[1].next = &FixUps[0]; | |
7be9a312 MH |
223 | } |
224 | ||
225 | ||
226 | /* this function removes the postincrement or postdecrement | |
227 | operator ( '+' or '-' ) from an expression */ | |
228 | ||
229 | static int postfix (p) | |
230 | char *p; | |
231 | { | |
232 | while (*p != '-' && *p != '+') | |
233 | { | |
234 | if (*p==0 || *p=='\n' || *p=='\r') | |
235 | break; | |
236 | p++; | |
237 | } | |
238 | ||
239 | if (*p == '-') | |
240 | { | |
241 | *p = ' '; | |
242 | return (-1); | |
243 | } | |
244 | if (*p == '+') | |
245 | { | |
246 | *p = ' '; | |
247 | return (1); | |
248 | } | |
249 | ||
250 | return (0); | |
251 | } | |
252 | ||
253 | ||
254 | static bfd_reloc_code_real_type | |
255 | get_reloc (op) | |
256 | struct d10v_operand *op; | |
257 | { | |
258 | int bits = op->bits; | |
259 | ||
260 | /* printf("get_reloc: bits=%d address=%d\n",bits,op->flags & OPERAND_ADDR); */ | |
261 | if (bits <= 4) | |
262 | return (0); | |
263 | ||
264 | if (op->flags & OPERAND_ADDR) | |
265 | { | |
0ef32559 MH |
266 | if (bits == 8) |
267 | return (BFD_RELOC_D10V_10_PCREL_R); | |
7be9a312 MH |
268 | else |
269 | return (BFD_RELOC_D10V_18_PCREL); | |
270 | } | |
271 | ||
272 | return (BFD_RELOC_16); | |
273 | } | |
274 | ||
275 | /* get_operands parses a string of operands and returns | |
276 | an array of expressions */ | |
277 | ||
278 | static int | |
279 | get_operands (exp) | |
280 | expressionS exp[]; | |
281 | { | |
282 | char *p = input_line_pointer; | |
283 | int numops = 0; | |
284 | int post = 0; | |
285 | ||
286 | while (*p) | |
287 | { | |
288 | while (*p == ' ' || *p == '\t' || *p == ',') | |
289 | p++; | |
290 | if (*p==0 || *p=='\n' || *p=='\r') | |
291 | break; | |
292 | ||
293 | if (*p == '@') | |
294 | { | |
295 | p++; | |
296 | exp[numops].X_op = O_absent; | |
297 | if (*p == '(') | |
298 | { | |
299 | p++; | |
300 | exp[numops].X_add_number = OPERAND_ATPAR; | |
301 | } | |
302 | else if (*p == '-') | |
303 | { | |
304 | p++; | |
305 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
306 | } | |
307 | else | |
308 | { | |
309 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
310 | post = postfix (p); | |
311 | } | |
312 | numops++; | |
313 | continue; | |
314 | } | |
315 | ||
316 | if (*p == ')') | |
317 | { | |
318 | /* just skip the trailing paren */ | |
319 | p++; | |
320 | continue; | |
321 | } | |
322 | ||
323 | input_line_pointer = p; | |
0ef32559 MH |
324 | |
325 | ||
7be9a312 | 326 | /* check to see if it might be a register name */ |
0ef32559 MH |
327 | if (!register_name (&exp[numops])) |
328 | { | |
329 | /* parse as an expression */ | |
330 | expression (&exp[numops]); | |
331 | } | |
7be9a312 MH |
332 | |
333 | if (exp[numops].X_op == O_illegal) | |
334 | as_bad ("illegal operand"); | |
335 | else if (exp[numops].X_op == O_absent) | |
336 | as_bad ("missing operand"); | |
337 | ||
338 | numops++; | |
339 | p = input_line_pointer; | |
340 | } | |
341 | ||
342 | switch (post) | |
343 | { | |
344 | case -1: /* postdecrement mode */ | |
345 | exp[numops].X_op = O_absent; | |
346 | exp[numops++].X_add_number = OPERAND_MINUS; | |
347 | break; | |
348 | case 1: /* postincrement mode */ | |
349 | exp[numops].X_op = O_absent; | |
350 | exp[numops++].X_add_number = OPERAND_PLUS; | |
351 | break; | |
352 | } | |
353 | ||
354 | exp[numops].X_op = 0; | |
355 | return (numops); | |
356 | } | |
357 | ||
358 | static unsigned long | |
0ef32559 | 359 | d10v_insert_operand (insn, op_type, value, left) |
7be9a312 MH |
360 | unsigned long insn; |
361 | int op_type; | |
362 | offsetT value; | |
0ef32559 | 363 | int left; |
7be9a312 MH |
364 | { |
365 | int shift, bits; | |
366 | ||
367 | shift = d10v_operands[op_type].shift; | |
0ef32559 MH |
368 | if (left) |
369 | shift += 15; | |
370 | ||
7be9a312 | 371 | bits = d10v_operands[op_type].bits; |
93050391 | 372 | |
7be9a312 MH |
373 | /* truncate to the proper number of bits */ |
374 | /* FIXME: overflow checking here? */ | |
375 | value &= 0x7FFFFFFF >> (31 - bits); | |
376 | insn |= (value << shift); | |
377 | ||
378 | return insn; | |
379 | } | |
380 | ||
381 | ||
382 | /* build_insn takes a pointer to the opcode entry in the opcode table | |
383 | and the array of operand expressions and returns the instruction */ | |
384 | ||
385 | static unsigned long | |
386 | build_insn (opcode, opers) | |
387 | struct d10v_opcode *opcode; | |
388 | expressionS *opers; | |
389 | { | |
390 | int i, bits, shift, flags; | |
391 | unsigned long insn; | |
392 | unsigned int number; | |
393 | insn = opcode->opcode; | |
394 | ||
395 | for (i=0;opcode->operands[i];i++) | |
396 | { | |
397 | flags = d10v_operands[opcode->operands[i]].flags; | |
398 | bits = d10v_operands[opcode->operands[i]].bits; | |
399 | shift = d10v_operands[opcode->operands[i]].shift; | |
400 | number = opers[i].X_add_number; | |
401 | ||
402 | if (flags & OPERAND_REG) | |
403 | { | |
404 | number &= REGISTER_MASK; | |
405 | if (opcode->format == LONG_L) | |
406 | shift += 15; | |
407 | } | |
408 | ||
409 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant) | |
410 | { | |
411 | /* now create a fixup */ | |
412 | ||
413 | /* | |
414 | printf("need a fixup: "); | |
415 | print_expr_1(stdout,&opers[i]); | |
416 | printf("\n"); | |
417 | */ | |
418 | ||
0ef32559 | 419 | if (fixups->fc >= MAX_INSN_FIXUPS) |
7be9a312 | 420 | as_fatal ("too many fixups"); |
0ef32559 | 421 | fixups->fix[fixups->fc].exp = opers[i]; |
7be9a312 MH |
422 | |
423 | /* put the operand number here for now. We can look up | |
424 | the reloc type and/or fixup the instruction in md_apply_fix() */ | |
0ef32559 MH |
425 | fixups->fix[fixups->fc].reloc = opcode->operands[i]; |
426 | (fixups->fc)++; | |
7be9a312 MH |
427 | } |
428 | ||
429 | /* truncate to the proper number of bits */ | |
430 | /* FIXME: overflow checking here? */ | |
431 | number &= 0x7FFFFFFF >> (31 - bits); | |
432 | insn = insn | (number << shift); | |
433 | } | |
434 | return insn; | |
435 | } | |
436 | ||
437 | /* write out a long form instruction */ | |
438 | static void | |
0ef32559 | 439 | write_long (opcode, insn, fx) |
7be9a312 MH |
440 | struct d10v_opcode *opcode; |
441 | unsigned long insn; | |
0ef32559 | 442 | Fixups *fx; |
7be9a312 MH |
443 | { |
444 | int i; | |
445 | char *f = frag_more(4); | |
446 | ||
447 | insn |= FM11; | |
0ef32559 | 448 | /* printf("INSN: %08x\n",insn); */ |
7be9a312 MH |
449 | number_to_chars_bigendian (f, insn, 4); |
450 | ||
0ef32559 | 451 | for (i=0; i < fx->fc; i++) |
7be9a312 | 452 | { |
0ef32559 | 453 | if (get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc])) |
7be9a312 MH |
454 | { |
455 | /* | |
456 | printf("fix_new_exp: where:%x size:4\n ",f - frag_now->fr_literal); | |
0ef32559 | 457 | print_expr_1(stdout,&(fx->fix[i].exp)); |
7be9a312 MH |
458 | printf("\n"); |
459 | */ | |
0ef32559 | 460 | |
7be9a312 MH |
461 | fix_new_exp (frag_now, |
462 | f - frag_now->fr_literal, | |
463 | 4, | |
0ef32559 | 464 | &(fx->fix[i].exp), |
7be9a312 | 465 | 1, |
0ef32559 | 466 | fx->fix[i].reloc); |
7be9a312 MH |
467 | } |
468 | } | |
0ef32559 | 469 | fx->fc = 0; |
7be9a312 MH |
470 | } |
471 | ||
0ef32559 | 472 | |
7be9a312 MH |
473 | /* write out a short form instruction by itself */ |
474 | static void | |
0ef32559 | 475 | write_1_short (opcode, insn, fx) |
7be9a312 MH |
476 | struct d10v_opcode *opcode; |
477 | unsigned long insn; | |
0ef32559 | 478 | Fixups *fx; |
7be9a312 MH |
479 | { |
480 | char *f = frag_more(4); | |
481 | int i; | |
482 | ||
483 | insn |= FM00 | (NOP << 15); | |
0ef32559 | 484 | /* printf("INSN: %08x\n",insn); */ |
7be9a312 | 485 | number_to_chars_bigendian (f, insn, 4); |
0ef32559 | 486 | for (i=0; i < fx->fc; i++) |
7be9a312 | 487 | { |
0ef32559 | 488 | if (get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc])) |
7be9a312 MH |
489 | { |
490 | /* | |
491 | printf("fix_new_exp: where:%x size:4\n ",f - frag_now->fr_literal); | |
0ef32559 | 492 | print_expr_1(stdout,&(fx->fix[i].exp)); |
7be9a312 MH |
493 | printf("\n"); |
494 | */ | |
495 | ||
496 | fix_new_exp (frag_now, | |
497 | f - frag_now->fr_literal, | |
498 | 4, | |
0ef32559 | 499 | &(fx->fix[i].exp), |
7be9a312 | 500 | 1, |
0ef32559 | 501 | fx->fix[i].reloc); |
7be9a312 MH |
502 | } |
503 | } | |
0ef32559 | 504 | fx->fc = 0; |
7be9a312 MH |
505 | } |
506 | ||
507 | /* write out a short form instruction if possible */ | |
508 | /* return number of instructions not written out */ | |
509 | static int | |
0ef32559 | 510 | write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) |
7be9a312 MH |
511 | struct d10v_opcode *opcode1, *opcode2; |
512 | unsigned long insn1, insn2; | |
513 | int exec_type; | |
0ef32559 | 514 | Fixups *fx; |
7be9a312 MH |
515 | { |
516 | unsigned long insn; | |
0ef32559 MH |
517 | char *f; |
518 | int i,j; | |
7be9a312 MH |
519 | |
520 | if(opcode1->exec_type == BRANCH_LINK) | |
521 | { | |
522 | /* subroutines must be called from 32-bit boundaries */ | |
523 | /* so the return address will be correct */ | |
0ef32559 | 524 | write_1_short (opcode1, insn1, fx->next); |
7be9a312 MH |
525 | return (1); |
526 | } | |
527 | ||
528 | switch (exec_type) | |
529 | { | |
530 | case 0: | |
531 | if (opcode1->unit == IU) | |
532 | { | |
0ef32559 | 533 | /* reverse sequential */ |
7be9a312 MH |
534 | insn = FM10 | (insn2 << 15) | insn1; |
535 | } | |
536 | else | |
537 | { | |
0ef32559 MH |
538 | insn = FM01 | (insn1 << 15) | insn2; |
539 | fx = fx->next; | |
7be9a312 MH |
540 | } |
541 | break; | |
542 | case 1: /* parallel */ | |
543 | insn = FM00 | (insn1 << 15) | insn2; | |
0ef32559 | 544 | fx = fx->next; |
7be9a312 MH |
545 | break; |
546 | case 2: /* sequential */ | |
547 | insn = FM01 | (insn1 << 15) | insn2; | |
0ef32559 | 548 | fx = fx->next; |
7be9a312 MH |
549 | break; |
550 | case 3: /* reverse sequential */ | |
551 | insn = FM10 | (insn1 << 15) | insn2; | |
552 | break; | |
553 | default: | |
554 | as_fatal("unknown execution type passed to write_2_short()"); | |
555 | } | |
556 | ||
557 | /* printf("INSN: %08x\n",insn); */ | |
0ef32559 MH |
558 | f = frag_more(4); |
559 | number_to_chars_bigendian (f, insn, 4); | |
560 | ||
561 | for (j=0; j<2; j++) | |
562 | { | |
563 | bfd_reloc_code_real_type reloc; | |
564 | for (i=0; i < fx->fc; i++) | |
565 | { | |
566 | reloc = get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc]); | |
567 | if (reloc) | |
568 | { | |
569 | if ( (reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) ) | |
570 | fx->fix[i].reloc |= 1024; | |
571 | ||
572 | /* | |
573 | printf("fix_new_exp: where:%x reloc:%d\n ",f - frag_now->fr_literal,fx->fix[i].reloc); | |
574 | print_expr_1(stdout,&(fx->fix[i].exp)); | |
575 | printf("\n"); | |
576 | */ | |
577 | fix_new_exp (frag_now, | |
578 | f - frag_now->fr_literal, | |
579 | 4, | |
580 | &(fx->fix[i].exp), | |
581 | 1, | |
582 | fx->fix[i].reloc); | |
583 | } | |
584 | } | |
585 | fx->fc = 0; | |
586 | fx = fx->next; | |
587 | } | |
588 | ||
7be9a312 MH |
589 | return (0); |
590 | } | |
591 | ||
592 | ||
593 | /* This is the main entry point for the machine-dependent assembler. str points to a | |
594 | machine-dependent instruction. This function is supposed to emit the frags/bytes | |
595 | it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing | |
596 | and leaves the difficult stuff to do_assemble(). | |
597 | */ | |
598 | ||
599 | static unsigned long prev_insn; | |
600 | static struct d10v_opcode *prev_opcode = 0; | |
0ef32559 MH |
601 | static subsegT prev_subseg; |
602 | static segT prev_seg; | |
7be9a312 MH |
603 | |
604 | void | |
605 | md_assemble (str) | |
606 | char *str; | |
607 | { | |
608 | struct d10v_opcode *opcode; | |
609 | unsigned long insn; | |
610 | int t=0; | |
611 | char *str2; | |
612 | ||
613 | /* printf("md_assemble: str=%s\n",str); */ | |
0ef32559 | 614 | |
7be9a312 MH |
615 | /* look for the special multiple instruction seperators */ |
616 | str2 = strstr (str, "||"); | |
617 | if (str2) | |
618 | t = 1; | |
619 | else | |
620 | { | |
621 | str2 = strstr (str, "->"); | |
622 | if (str2) | |
623 | t = 2; | |
624 | else | |
625 | { | |
626 | str2 = strstr (str, "<-"); | |
627 | if (str2) | |
628 | t = 3; | |
629 | } | |
630 | } | |
631 | ||
632 | ||
633 | /* str2 points to the seperator, if one */ | |
634 | if (str2) | |
635 | { | |
636 | *str2 = 0; | |
637 | ||
638 | /* if two instructions are present and we already have one saved | |
639 | then first write it out */ | |
640 | if (prev_opcode) | |
0ef32559 | 641 | write_1_short (prev_opcode, prev_insn, fixups->next); |
7be9a312 MH |
642 | |
643 | /* assemble first instruction and save it */ | |
644 | prev_insn = do_assemble (str, &prev_opcode); | |
0ef32559 | 645 | fixups = fixups->next; |
7be9a312 MH |
646 | str = str2 + 2; |
647 | } | |
648 | ||
649 | insn = do_assemble (str, &opcode); | |
650 | ||
651 | /* if this is a long instruction, write it and any previous short instruction */ | |
652 | if (opcode->format & LONG_OPCODE) | |
653 | { | |
654 | if (t) | |
655 | as_fatal("Unable to mix instructions as specified"); | |
656 | if (prev_opcode) | |
657 | { | |
0ef32559 | 658 | write_1_short (prev_opcode, prev_insn, fixups->next); |
7be9a312 MH |
659 | prev_opcode = NULL; |
660 | } | |
0ef32559 | 661 | write_long (opcode, insn, fixups); |
7be9a312 MH |
662 | prev_opcode = NULL; |
663 | return; | |
664 | } | |
665 | ||
0ef32559 | 666 | if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, t, fixups) == 0)) |
7be9a312 MH |
667 | { |
668 | /* no instructions saved */ | |
669 | prev_opcode = NULL; | |
670 | } | |
671 | else | |
672 | { | |
673 | if (t) | |
674 | as_fatal("Unable to mix instructions as specified"); | |
675 | /* save off last instruction so it may be packed on next pass */ | |
676 | prev_opcode = opcode; | |
677 | prev_insn = insn; | |
0ef32559 MH |
678 | prev_seg = now_seg; |
679 | prev_subseg = now_subseg; | |
680 | fixups = fixups->next; | |
7be9a312 MH |
681 | } |
682 | } | |
683 | ||
684 | ||
685 | static unsigned long | |
686 | do_assemble (str, opcode) | |
687 | char *str; | |
688 | struct d10v_opcode **opcode; | |
689 | { | |
690 | struct d10v_opcode *next_opcode; | |
691 | unsigned char *op_start, *save; | |
692 | unsigned char *op_end; | |
693 | char name[20]; | |
694 | int nlen = 0, i, match, numops; | |
695 | expressionS myops[6]; | |
696 | unsigned long insn; | |
697 | ||
0ef32559 | 698 | /* printf("do_assemble: str=%s\n",str); */ |
7be9a312 MH |
699 | |
700 | /* Drop leading whitespace */ | |
701 | while (*str == ' ') | |
702 | str++; | |
703 | ||
704 | /* find the opcode end */ | |
705 | for (op_start = op_end = (unsigned char *) (str); | |
706 | *op_end | |
707 | && nlen < 20 | |
708 | && !is_end_of_line[*op_end] && *op_end != ' '; | |
709 | op_end++) | |
710 | { | |
711 | name[nlen] = op_start[nlen]; | |
712 | nlen++; | |
713 | } | |
714 | name[nlen] = 0; | |
715 | ||
716 | if (nlen == 0) | |
717 | as_bad ("can't find opcode "); | |
718 | ||
719 | /* find the first opcode with the proper name */ | |
720 | *opcode = (struct d10v_opcode *)hash_find (d10v_hash, name); | |
721 | if (*opcode == NULL) | |
722 | { | |
723 | as_bad ("unknown opcode"); | |
724 | return; | |
725 | } | |
726 | ||
727 | save = input_line_pointer; | |
728 | input_line_pointer = op_end; | |
729 | ||
730 | /* get all the operands and save them as expressions */ | |
731 | numops = get_operands (myops); | |
732 | ||
733 | /* now search the opcode table table for one with operands */ | |
734 | /* that match what we've got */ | |
735 | do | |
736 | { | |
737 | match = 1; | |
738 | for (i = 0; (*opcode)->operands[i]; i++) | |
739 | { | |
740 | int flags = d10v_operands[(*opcode)->operands[i]].flags; | |
741 | ||
742 | if (myops[i].X_op==0) | |
743 | { | |
744 | match=0; | |
745 | break; | |
746 | } | |
747 | ||
748 | if (flags & OPERAND_REG) | |
749 | { | |
750 | if ((myops[i].X_op != O_register) || | |
751 | ((flags & OPERAND_ACC) != (myops[i].X_add_number & OPERAND_ACC)) || | |
752 | ((flags & OPERAND_FLAG) != (myops[i].X_add_number & OPERAND_FLAG)) || | |
753 | ((flags & OPERAND_CONTROL) != (myops[i].X_add_number & OPERAND_CONTROL))) | |
754 | { | |
755 | match=0; | |
756 | break; | |
757 | } | |
758 | } | |
759 | ||
760 | if (((flags & OPERAND_MINUS) && ((myops[i].X_op != O_absent) || (myops[i].X_add_number != OPERAND_MINUS))) || | |
761 | ((flags & OPERAND_PLUS) && ((myops[i].X_op != O_absent) || (myops[i].X_add_number != OPERAND_PLUS))) || | |
762 | ((flags & OPERAND_ATMINUS) && ((myops[i].X_op != O_absent) || (myops[i].X_add_number != OPERAND_ATMINUS))) || | |
763 | ((flags & OPERAND_ATPAR) && ((myops[i].X_op != O_absent) || (myops[i].X_add_number != OPERAND_ATPAR))) || | |
764 | ((flags & OPERAND_ATSIGN) && ((myops[i].X_op != O_absent) || (myops[i].X_add_number != OPERAND_ATSIGN)))) | |
765 | { | |
766 | match=0; | |
767 | break; | |
768 | } | |
769 | } | |
770 | ||
771 | /* we're only done if the operands matched AND there | |
772 | are no more to check */ | |
773 | if (match && myops[i].X_op==0) | |
774 | break; | |
775 | ||
776 | next_opcode = (*opcode)+1; | |
777 | if (next_opcode->opcode == 0) | |
778 | break; | |
779 | if (strcmp(next_opcode->name, (*opcode)->name)) | |
780 | break; | |
781 | (*opcode) = next_opcode; | |
782 | } while (!match); | |
783 | ||
784 | if (!match) | |
785 | { | |
786 | as_bad ("bad opcode or operands"); | |
787 | return (0); | |
788 | } | |
789 | ||
790 | /* Check that all registers that are required to be even are. */ | |
791 | /* Also, if any operands were marked as registers, but were really symbols */ | |
792 | /* fix that here. */ | |
793 | for (i=0; (*opcode)->operands[i]; i++) | |
794 | { | |
795 | if ((d10v_operands[(*opcode)->operands[i]].flags & OPERAND_EVEN) && | |
796 | (myops[i].X_add_number & 1)) | |
797 | as_fatal("Register number must be EVEN"); | |
798 | if (myops[i].X_op == O_register) | |
799 | { | |
800 | if (!(d10v_operands[(*opcode)->operands[i]].flags & OPERAND_REG)) | |
801 | { | |
802 | myops[i].X_op = O_symbol; | |
0ef32559 | 803 | myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol); |
7be9a312 | 804 | myops[i].X_add_number = 0; |
0ef32559 | 805 | myops[i].X_op_symbol = NULL; |
7be9a312 MH |
806 | /* FIXME create a fixup */ |
807 | } | |
808 | } | |
809 | } | |
810 | ||
811 | input_line_pointer = save; | |
812 | ||
813 | /* at this point, we have "opcode" pointing to the opcode entry in the | |
814 | d10v opcode table, with myops filled out with the operands. */ | |
815 | insn = build_insn ((*opcode), myops); | |
816 | /* printf("sub-insn = %lx\n",insn); */ | |
817 | ||
818 | return (insn); | |
819 | } | |
820 | ||
821 | ||
822 | /* if while processing a fixup, a reloc really needs to be created */ | |
823 | /* then it is done here */ | |
824 | ||
825 | arelent * | |
826 | tc_gen_reloc (seg, fixp) | |
827 | asection *seg; | |
828 | fixS *fixp; | |
829 | { | |
830 | arelent *reloc; | |
831 | reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent)); | |
832 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
833 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
834 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
835 | if (reloc->howto == (reloc_howto_type *) NULL) | |
836 | { | |
837 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
838 | "reloc %d not supported by object file format", (int)fixp->fx_r_type); | |
839 | return NULL; | |
840 | } | |
841 | reloc->addend = fixp->fx_addnumber; | |
842 | /* printf("tc_gen_reloc: addr=%x addend=%x\n", reloc->address, reloc->addend); */ | |
843 | return reloc; | |
844 | } | |
845 | ||
846 | int | |
847 | md_estimate_size_before_relax (fragp, seg) | |
848 | fragS *fragp; | |
849 | asection *seg; | |
850 | { | |
851 | abort (); | |
852 | return 0; | |
853 | } | |
854 | ||
855 | long | |
856 | md_pcrel_from_section (fixp, sec) | |
857 | fixS *fixp; | |
858 | segT sec; | |
859 | { | |
860 | return 0; | |
861 | /* return fixp->fx_frag->fr_address + fixp->fx_where; */ | |
862 | } | |
863 | ||
864 | int | |
865 | md_apply_fix3 (fixp, valuep, seg) | |
866 | fixS *fixp; | |
867 | valueT *valuep; | |
868 | segT seg; | |
869 | { | |
7be9a312 MH |
870 | char *where; |
871 | unsigned long insn; | |
93050391 | 872 | long value; |
7be9a312 | 873 | int op_type; |
0ef32559 | 874 | int left=0; |
7be9a312 MH |
875 | |
876 | if (fixp->fx_addsy == (symbolS *) NULL) | |
877 | { | |
878 | value = *valuep; | |
879 | fixp->fx_done = 1; | |
880 | } | |
881 | else if (fixp->fx_pcrel) | |
882 | value = *valuep; | |
883 | else | |
884 | { | |
885 | value = fixp->fx_offset; | |
886 | if (fixp->fx_subsy != (symbolS *) NULL) | |
887 | { | |
888 | if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) | |
889 | value -= S_GET_VALUE (fixp->fx_subsy); | |
890 | else | |
891 | { | |
892 | /* We don't actually support subtracting a symbol. */ | |
893 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
894 | "expression too complex"); | |
895 | } | |
896 | } | |
897 | } | |
898 | ||
0ef32559 | 899 | /* printf("md_apply_fix: value=0x%x type=%d\n", value, fixp->fx_r_type); */ |
7be9a312 MH |
900 | |
901 | op_type = fixp->fx_r_type; | |
0ef32559 MH |
902 | if (op_type & 1024) |
903 | { | |
904 | op_type -= 1024; | |
905 | fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L; | |
906 | left = 1; | |
907 | } | |
908 | else | |
909 | fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]); | |
7be9a312 MH |
910 | |
911 | /* Fetch the instruction, insert the fully resolved operand | |
912 | value, and stuff the instruction back again. */ | |
913 | where = fixp->fx_frag->fr_literal + fixp->fx_where; | |
914 | insn = bfd_getb32 ((unsigned char *) where); | |
7be9a312 | 915 | |
93050391 MH |
916 | switch (fixp->fx_r_type) |
917 | { | |
918 | case BFD_RELOC_D10V_10_PCREL_L: | |
919 | case BFD_RELOC_D10V_10_PCREL_R: | |
920 | case BFD_RELOC_D10V_18_PCREL: | |
921 | /* instruction addresses are always right-shifted by 2 | |
922 | and pc-relative */ | |
923 | if (!fixp->fx_pcrel) | |
924 | value -= fixp->fx_where; | |
925 | value >>= 2; | |
926 | default: | |
927 | break; | |
928 | } | |
929 | /* printf(" insn=%x value=%x where=%x pcrel=%x\n",insn,value,fixp->fx_where,fixp->fx_pcrel); */ | |
930 | ||
931 | insn = d10v_insert_operand (insn, op_type, (offsetT)value, left); | |
7be9a312 MH |
932 | |
933 | /* printf(" new insn=%x\n",insn); */ | |
934 | ||
935 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
936 | ||
937 | if (fixp->fx_done) | |
938 | return 1; | |
939 | ||
940 | fixp->fx_addnumber = value; | |
941 | return 1; | |
942 | } | |
943 | ||
7be9a312 | 944 | |
0ef32559 MH |
945 | /* d10v_cleanup() is called after the assembler has finished parsing the input |
946 | file or after a label is defined. Because the D10V assembler sometimes saves short | |
947 | instructions to see if it can package them with the next instruction, there may | |
948 | be a short instruction that still needs written. */ | |
7be9a312 | 949 | int |
0ef32559 | 950 | d10v_cleanup() |
7be9a312 | 951 | { |
0ef32559 MH |
952 | segT seg; |
953 | subsegT subseg; | |
954 | ||
7be9a312 MH |
955 | if (prev_opcode) |
956 | { | |
0ef32559 MH |
957 | seg = now_seg; |
958 | subseg = now_subseg; | |
959 | subseg_set (prev_seg, prev_subseg); | |
960 | write_1_short (prev_opcode, prev_insn, fixups); | |
961 | subseg_set (seg, subseg); | |
7be9a312 MH |
962 | prev_opcode = NULL; |
963 | } | |
964 | return 1; | |
965 | } |