Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-d10v.c -- Assembler code for the Mitsubishi D10V |
fbdbf472 | 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
f7e42eb4 | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
e0c6ed95 | 25 | #include "subsegs.h" |
252b5132 RH |
26 | #include "opcode/d10v.h" |
27 | #include "elf/ppc.h" | |
28 | ||
29 | const char comment_chars[] = ";"; | |
30 | const char line_comment_chars[] = "#"; | |
31 | const char line_separator_chars[] = ""; | |
32 | const char *md_shortopts = "O"; | |
33 | const char EXP_CHARS[] = "eE"; | |
34 | const char FLT_CHARS[] = "dD"; | |
35 | ||
36 | int Optimizing = 0; | |
37 | ||
38 | #define AT_WORD_P(X) ((X)->X_op == O_right_shift \ | |
39 | && (X)->X_op_symbol != NULL \ | |
a77f5182 ILT |
40 | && symbol_constant_p ((X)->X_op_symbol) \ |
41 | && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT) | |
252b5132 RH |
42 | #define AT_WORD_RIGHT_SHIFT 2 |
43 | ||
e0c6ed95 | 44 | /* Fixups. */ |
252b5132 RH |
45 | #define MAX_INSN_FIXUPS (5) |
46 | struct d10v_fixup | |
47 | { | |
48 | expressionS exp; | |
49 | int operand; | |
50 | int pcrel; | |
51 | int size; | |
52 | bfd_reloc_code_real_type reloc; | |
53 | }; | |
54 | ||
55 | typedef struct _fixups | |
56 | { | |
57 | int fc; | |
58 | struct d10v_fixup fix[MAX_INSN_FIXUPS]; | |
59 | struct _fixups *next; | |
60 | } Fixups; | |
61 | ||
62 | static Fixups FixUps[2]; | |
63 | static Fixups *fixups; | |
64 | ||
0f94f4c8 NC |
65 | static int do_not_ignore_hash = 0; |
66 | ||
0a44c2b1 | 67 | typedef int packing_type; |
e0c6ed95 AM |
68 | #define PACK_UNSPEC (0) /* Packing order not specified. */ |
69 | #define PACK_PARALLEL (1) /* "||" */ | |
70 | #define PACK_LEFT_RIGHT (2) /* "->" */ | |
71 | #define PACK_RIGHT_LEFT (3) /* "<-" */ | |
72 | static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */ | |
0a44c2b1 | 73 | |
bccba5f0 | 74 | /* True if instruction swapping warnings should be inhibited. |
bfb32b52 | 75 | --nowarnswap. */ |
bccba5f0 NC |
76 | static boolean flag_warn_suppress_instructionswap; |
77 | ||
78 | /* True if instruction packing should be performed when --gstabs is specified. | |
79 | --gstabs-packing, --no-gstabs-packing. */ | |
80 | static boolean flag_allow_gstabs_packing = 1; | |
252b5132 | 81 | |
e0c6ed95 | 82 | /* Local functions. */ |
252b5132 RH |
83 | static int reg_name_search PARAMS ((char *name)); |
84 | static int register_name PARAMS ((expressionS *expressionP)); | |
85 | static int check_range PARAMS ((unsigned long num, int bits, int flags)); | |
86 | static int postfix PARAMS ((char *p)); | |
87 | static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op)); | |
88 | static int get_operands PARAMS ((expressionS exp[])); | |
89 | static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[])); | |
90 | static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn)); | |
bccba5f0 | 91 | static void write_long PARAMS ((unsigned long insn, Fixups *fx)); |
252b5132 | 92 | static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); |
e0c6ed95 | 93 | static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, |
0a44c2b1 | 94 | struct d10v_opcode *opcode2, unsigned long insn2, packing_type exec_type, Fixups *fx)); |
252b5132 RH |
95 | static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode)); |
96 | static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type, | |
97 | offsetT value, int left, fixS *fix)); | |
e0c6ed95 | 98 | static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, |
252b5132 | 99 | struct d10v_opcode *opcode2, unsigned long insn2, |
0a44c2b1 | 100 | packing_type exec_type)); |
fbdbf472 | 101 | |
cc8a6dd0 KH |
102 | static void check_resource_conflict PARAMS ((struct d10v_opcode *opcode1, |
103 | unsigned long insn1, | |
104 | struct d10v_opcode *opcode2, | |
fbdbf472 TR |
105 | unsigned long insn2)); |
106 | ||
252b5132 RH |
107 | static symbolS * find_symbol_matching_register PARAMS ((expressionS *)); |
108 | ||
109 | struct option md_longopts[] = | |
110 | { | |
111 | #define OPTION_NOWARNSWAP (OPTION_MD_BASE) | |
112 | {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP}, | |
bccba5f0 NC |
113 | #define OPTION_GSTABSPACKING (OPTION_MD_BASE + 1) |
114 | {"gstabspacking", no_argument, NULL, OPTION_GSTABSPACKING}, | |
115 | {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING}, | |
116 | #define OPTION_NOGSTABSPACKING (OPTION_MD_BASE + 2) | |
117 | {"nogstabspacking", no_argument, NULL, OPTION_NOGSTABSPACKING}, | |
118 | {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING}, | |
252b5132 RH |
119 | {NULL, no_argument, NULL, 0} |
120 | }; | |
ab3e48dc KH |
121 | |
122 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
123 | |
124 | static void d10v_dot_word PARAMS ((int)); | |
125 | ||
126 | /* The target specific pseudo-ops which we support. */ | |
127 | const pseudo_typeS md_pseudo_table[] = | |
128 | { | |
129 | { "word", d10v_dot_word, 2 }, | |
130 | { NULL, NULL, 0 } | |
131 | }; | |
132 | ||
133 | /* Opcode hash table. */ | |
134 | static struct hash_control *d10v_hash; | |
135 | ||
e0c6ed95 AM |
136 | /* Do a binary search of the d10v_predefined_registers array to see if |
137 | NAME is a valid regiter name. Return the register number from the | |
138 | array on success, or -1 on failure. */ | |
252b5132 RH |
139 | |
140 | static int | |
141 | reg_name_search (name) | |
142 | char *name; | |
143 | { | |
144 | int middle, low, high; | |
145 | int cmp; | |
146 | ||
147 | low = 0; | |
e0c6ed95 | 148 | high = d10v_reg_name_cnt () - 1; |
252b5132 RH |
149 | |
150 | do | |
151 | { | |
152 | middle = (low + high) / 2; | |
153 | cmp = strcasecmp (name, d10v_predefined_registers[middle].name); | |
154 | if (cmp < 0) | |
155 | high = middle - 1; | |
156 | else if (cmp > 0) | |
157 | low = middle + 1; | |
e0c6ed95 AM |
158 | else |
159 | return d10v_predefined_registers[middle].value; | |
252b5132 RH |
160 | } |
161 | while (low <= high); | |
162 | return -1; | |
163 | } | |
164 | ||
e0c6ed95 AM |
165 | /* Check the string at input_line_pointer |
166 | to see if it is a valid register name. */ | |
252b5132 RH |
167 | |
168 | static int | |
169 | register_name (expressionP) | |
170 | expressionS *expressionP; | |
171 | { | |
172 | int reg_number; | |
173 | char c, *p = input_line_pointer; | |
e0c6ed95 AM |
174 | |
175 | while (*p | |
176 | && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')') | |
252b5132 RH |
177 | p++; |
178 | ||
179 | c = *p; | |
180 | if (c) | |
181 | *p++ = 0; | |
182 | ||
e0c6ed95 | 183 | /* Look to see if it's in the register table. */ |
252b5132 | 184 | reg_number = reg_name_search (input_line_pointer); |
e0c6ed95 | 185 | if (reg_number >= 0) |
252b5132 RH |
186 | { |
187 | expressionP->X_op = O_register; | |
e0c6ed95 AM |
188 | /* Temporarily store a pointer to the string here. */ |
189 | expressionP->X_op_symbol = (symbolS *) input_line_pointer; | |
252b5132 RH |
190 | expressionP->X_add_number = reg_number; |
191 | input_line_pointer = p; | |
192 | return 1; | |
193 | } | |
194 | if (c) | |
e0c6ed95 | 195 | *(p - 1) = c; |
252b5132 RH |
196 | return 0; |
197 | } | |
198 | ||
252b5132 RH |
199 | static int |
200 | check_range (num, bits, flags) | |
201 | unsigned long num; | |
202 | int bits; | |
203 | int flags; | |
204 | { | |
bccba5f0 | 205 | long min, max; |
e0c6ed95 | 206 | int retval = 0; |
252b5132 | 207 | |
e0c6ed95 | 208 | /* Don't bother checking 16-bit values. */ |
252b5132 RH |
209 | if (bits == 16) |
210 | return 0; | |
211 | ||
212 | if (flags & OPERAND_SHIFT) | |
213 | { | |
e0c6ed95 AM |
214 | /* All special shift operands are unsigned and <= 16. |
215 | We allow 0 for now. */ | |
216 | if (num > 16) | |
252b5132 RH |
217 | return 1; |
218 | else | |
219 | return 0; | |
220 | } | |
221 | ||
222 | if (flags & OPERAND_SIGNED) | |
223 | { | |
e0c6ed95 | 224 | /* Signed 3-bit integers are restricted to the (-2, 3) range. */ |
c43185de DN |
225 | if (flags & RESTRICTED_NUM3) |
226 | { | |
227 | if ((long) num < -2 || (long) num > 3) | |
228 | retval = 1; | |
229 | } | |
230 | else | |
231 | { | |
e0c6ed95 AM |
232 | max = (1 << (bits - 1)) - 1; |
233 | min = - (1 << (bits - 1)); | |
c43185de DN |
234 | if (((long) num > max) || ((long) num < min)) |
235 | retval = 1; | |
236 | } | |
252b5132 RH |
237 | } |
238 | else | |
239 | { | |
240 | max = (1 << bits) - 1; | |
241 | min = 0; | |
bccba5f0 | 242 | if (((long) num > max) || ((long) num < min)) |
252b5132 RH |
243 | retval = 1; |
244 | } | |
245 | return retval; | |
246 | } | |
247 | ||
252b5132 RH |
248 | void |
249 | md_show_usage (stream) | |
e0c6ed95 | 250 | FILE *stream; |
252b5132 | 251 | { |
e0c6ed95 | 252 | fprintf (stream, _("D10V options:\n\ |
bccba5f0 NC |
253 | -O Optimize. Will do some operations in parallel.\n\ |
254 | --gstabs-packing Pack adjacent short instructions together even\n\ | |
255 | when --gstabs is specified. On by default.\n\ | |
256 | --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\ | |
257 | instructions together.\n")); | |
e0c6ed95 | 258 | } |
252b5132 RH |
259 | |
260 | int | |
261 | md_parse_option (c, arg) | |
262 | int c; | |
bccba5f0 | 263 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
264 | { |
265 | switch (c) | |
266 | { | |
267 | case 'O': | |
e0c6ed95 | 268 | /* Optimize. Will attempt to parallelize operations. */ |
252b5132 RH |
269 | Optimizing = 1; |
270 | break; | |
271 | case OPTION_NOWARNSWAP: | |
272 | flag_warn_suppress_instructionswap = 1; | |
273 | break; | |
bccba5f0 NC |
274 | case OPTION_GSTABSPACKING: |
275 | flag_allow_gstabs_packing = 1; | |
276 | break; | |
277 | case OPTION_NOGSTABSPACKING: | |
278 | flag_allow_gstabs_packing = 0; | |
279 | break; | |
252b5132 RH |
280 | default: |
281 | return 0; | |
282 | } | |
283 | return 1; | |
284 | } | |
285 | ||
286 | symbolS * | |
287 | md_undefined_symbol (name) | |
bccba5f0 | 288 | char *name ATTRIBUTE_UNUSED; |
252b5132 RH |
289 | { |
290 | return 0; | |
291 | } | |
292 | ||
e0c6ed95 AM |
293 | /* Turn a string in input_line_pointer into a floating point constant |
294 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
295 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
296 | returned, or NULL on OK. */ | |
297 | ||
252b5132 RH |
298 | char * |
299 | md_atof (type, litP, sizeP) | |
300 | int type; | |
301 | char *litP; | |
302 | int *sizeP; | |
303 | { | |
304 | int prec; | |
305 | LITTLENUM_TYPE words[4]; | |
306 | char *t; | |
307 | int i; | |
e0c6ed95 | 308 | |
252b5132 RH |
309 | switch (type) |
310 | { | |
311 | case 'f': | |
312 | prec = 2; | |
313 | break; | |
314 | case 'd': | |
315 | prec = 4; | |
316 | break; | |
317 | default: | |
318 | *sizeP = 0; | |
319 | return _("bad call to md_atof"); | |
320 | } | |
321 | ||
322 | t = atof_ieee (input_line_pointer, type, words); | |
323 | if (t) | |
324 | input_line_pointer = t; | |
e0c6ed95 | 325 | |
252b5132 | 326 | *sizeP = prec * 2; |
e0c6ed95 | 327 | |
252b5132 RH |
328 | for (i = 0; i < prec; i++) |
329 | { | |
330 | md_number_to_chars (litP, (valueT) words[i], 2); | |
e0c6ed95 | 331 | litP += 2; |
252b5132 RH |
332 | } |
333 | return NULL; | |
334 | } | |
335 | ||
336 | void | |
337 | md_convert_frag (abfd, sec, fragP) | |
bccba5f0 NC |
338 | bfd *abfd ATTRIBUTE_UNUSED; |
339 | asection *sec ATTRIBUTE_UNUSED; | |
340 | fragS *fragP ATTRIBUTE_UNUSED; | |
252b5132 RH |
341 | { |
342 | abort (); | |
343 | } | |
344 | ||
345 | valueT | |
346 | md_section_align (seg, addr) | |
347 | asection *seg; | |
348 | valueT addr; | |
349 | { | |
350 | int align = bfd_get_section_alignment (stdoutput, seg); | |
351 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
352 | } | |
353 | ||
252b5132 RH |
354 | void |
355 | md_begin () | |
356 | { | |
357 | char *prev_name = ""; | |
358 | struct d10v_opcode *opcode; | |
e0c6ed95 | 359 | d10v_hash = hash_new (); |
252b5132 RH |
360 | |
361 | /* Insert unique names into hash table. The D10v instruction set | |
362 | has many identical opcode names that have different opcodes based | |
363 | on the operands. This hash table then provides a quick index to | |
364 | the first opcode with a particular name in the opcode table. */ | |
365 | ||
e0c6ed95 | 366 | for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++) |
252b5132 RH |
367 | { |
368 | if (strcmp (prev_name, opcode->name)) | |
369 | { | |
e0c6ed95 | 370 | prev_name = (char *) opcode->name; |
252b5132 RH |
371 | hash_insert (d10v_hash, opcode->name, (char *) opcode); |
372 | } | |
373 | } | |
374 | ||
375 | fixups = &FixUps[0]; | |
376 | FixUps[0].next = &FixUps[1]; | |
377 | FixUps[1].next = &FixUps[0]; | |
378 | } | |
379 | ||
e0c6ed95 AM |
380 | /* Remove the postincrement or postdecrement operator ( '+' or '-' ) |
381 | from an expression. */ | |
252b5132 | 382 | |
e0c6ed95 AM |
383 | static int |
384 | postfix (p) | |
252b5132 RH |
385 | char *p; |
386 | { | |
e0c6ed95 | 387 | while (*p != '-' && *p != '+') |
252b5132 | 388 | { |
e0c6ed95 | 389 | if (*p == 0 || *p == '\n' || *p == '\r') |
252b5132 RH |
390 | break; |
391 | p++; | |
392 | } | |
393 | ||
e0c6ed95 | 394 | if (*p == '-') |
252b5132 RH |
395 | { |
396 | *p = ' '; | |
397 | return (-1); | |
398 | } | |
e0c6ed95 | 399 | if (*p == '+') |
252b5132 RH |
400 | { |
401 | *p = ' '; | |
402 | return (1); | |
403 | } | |
404 | ||
405 | return (0); | |
406 | } | |
407 | ||
e0c6ed95 AM |
408 | static bfd_reloc_code_real_type |
409 | get_reloc (op) | |
252b5132 RH |
410 | struct d10v_operand *op; |
411 | { | |
412 | int bits = op->bits; | |
413 | ||
e0c6ed95 | 414 | if (bits <= 4) |
252b5132 | 415 | return (0); |
e0c6ed95 AM |
416 | |
417 | if (op->flags & OPERAND_ADDR) | |
252b5132 RH |
418 | { |
419 | if (bits == 8) | |
420 | return (BFD_RELOC_D10V_10_PCREL_R); | |
421 | else | |
422 | return (BFD_RELOC_D10V_18_PCREL); | |
423 | } | |
424 | ||
425 | return (BFD_RELOC_16); | |
426 | } | |
427 | ||
e0c6ed95 | 428 | /* Parse a string of operands. Return an array of expressions. */ |
252b5132 RH |
429 | |
430 | static int | |
e0c6ed95 | 431 | get_operands (exp) |
252b5132 RH |
432 | expressionS exp[]; |
433 | { | |
434 | char *p = input_line_pointer; | |
435 | int numops = 0; | |
436 | int post = 0; | |
0f94f4c8 | 437 | int uses_at = 0; |
e0c6ed95 AM |
438 | |
439 | while (*p) | |
252b5132 | 440 | { |
e0c6ed95 | 441 | while (*p == ' ' || *p == '\t' || *p == ',') |
252b5132 | 442 | p++; |
e0c6ed95 | 443 | if (*p == 0 || *p == '\n' || *p == '\r') |
252b5132 | 444 | break; |
e0c6ed95 AM |
445 | |
446 | if (*p == '@') | |
252b5132 | 447 | { |
0f94f4c8 | 448 | uses_at = 1; |
e0c6ed95 | 449 | |
252b5132 RH |
450 | p++; |
451 | exp[numops].X_op = O_absent; | |
e0c6ed95 | 452 | if (*p == '(') |
252b5132 RH |
453 | { |
454 | p++; | |
455 | exp[numops].X_add_number = OPERAND_ATPAR; | |
456 | } | |
e0c6ed95 | 457 | else if (*p == '-') |
252b5132 RH |
458 | { |
459 | p++; | |
460 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
461 | } | |
462 | else | |
463 | { | |
464 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
3543a2f1 AO |
465 | if (*p == '+') |
466 | { | |
8c0392a9 AO |
467 | numops++; |
468 | exp[numops].X_op = O_absent; | |
469 | exp[numops].X_add_number = OPERAND_PLUS; | |
470 | p++; | |
3543a2f1 | 471 | } |
252b5132 RH |
472 | post = postfix (p); |
473 | } | |
474 | numops++; | |
475 | continue; | |
476 | } | |
477 | ||
e0c6ed95 | 478 | if (*p == ')') |
252b5132 | 479 | { |
e0c6ed95 | 480 | /* Just skip the trailing paren. */ |
252b5132 RH |
481 | p++; |
482 | continue; | |
483 | } | |
484 | ||
485 | input_line_pointer = p; | |
486 | ||
e0c6ed95 | 487 | /* Check to see if it might be a register name. */ |
252b5132 RH |
488 | if (!register_name (&exp[numops])) |
489 | { | |
e0c6ed95 | 490 | /* Parse as an expression. */ |
0f94f4c8 NC |
491 | if (uses_at) |
492 | { | |
493 | /* Any expression that involves the indirect addressing | |
494 | cannot also involve immediate addressing. Therefore | |
495 | the use of the hash character is illegal. */ | |
496 | int save = do_not_ignore_hash; | |
497 | do_not_ignore_hash = 1; | |
e0c6ed95 | 498 | |
0f94f4c8 | 499 | expression (&exp[numops]); |
e0c6ed95 | 500 | |
0f94f4c8 NC |
501 | do_not_ignore_hash = save; |
502 | } | |
503 | else | |
504 | expression (&exp[numops]); | |
252b5132 RH |
505 | } |
506 | ||
507 | if (strncasecmp (input_line_pointer, "@word", 5) == 0) | |
508 | { | |
509 | input_line_pointer += 5; | |
510 | if (exp[numops].X_op == O_register) | |
511 | { | |
e0c6ed95 | 512 | /* If it looked like a register name but was followed by |
252b5132 | 513 | "@word" then it was really a symbol, so change it to |
e0c6ed95 | 514 | one. */ |
252b5132 | 515 | exp[numops].X_op = O_symbol; |
e0c6ed95 AM |
516 | exp[numops].X_add_symbol = |
517 | symbol_find_or_make ((char *) exp[numops].X_op_symbol); | |
252b5132 RH |
518 | } |
519 | ||
e0c6ed95 | 520 | /* Check for identifier@word+constant. */ |
252b5132 | 521 | if (*input_line_pointer == '-' || *input_line_pointer == '+') |
e0c6ed95 | 522 | { |
e0c6ed95 AM |
523 | expressionS new_exp; |
524 | expression (&new_exp); | |
525 | exp[numops].X_add_number = new_exp.X_add_number; | |
526 | } | |
252b5132 | 527 | |
e0c6ed95 | 528 | /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */ |
252b5132 RH |
529 | { |
530 | expressionS new_exp; | |
531 | memset (&new_exp, 0, sizeof new_exp); | |
532 | new_exp.X_add_number = AT_WORD_RIGHT_SHIFT; | |
533 | new_exp.X_op = O_constant; | |
534 | new_exp.X_unsigned = 1; | |
535 | exp[numops].X_op_symbol = make_expr_symbol (&new_exp); | |
536 | exp[numops].X_op = O_right_shift; | |
537 | } | |
538 | ||
539 | know (AT_WORD_P (&exp[numops])); | |
540 | } | |
e0c6ed95 AM |
541 | |
542 | if (exp[numops].X_op == O_illegal) | |
252b5132 | 543 | as_bad (_("illegal operand")); |
e0c6ed95 | 544 | else if (exp[numops].X_op == O_absent) |
252b5132 RH |
545 | as_bad (_("missing operand")); |
546 | ||
547 | numops++; | |
548 | p = input_line_pointer; | |
549 | } | |
550 | ||
e0c6ed95 | 551 | switch (post) |
252b5132 | 552 | { |
e0c6ed95 | 553 | case -1: /* Postdecrement mode. */ |
252b5132 RH |
554 | exp[numops].X_op = O_absent; |
555 | exp[numops++].X_add_number = OPERAND_MINUS; | |
556 | break; | |
e0c6ed95 | 557 | case 1: /* Postincrement mode. */ |
252b5132 RH |
558 | exp[numops].X_op = O_absent; |
559 | exp[numops++].X_add_number = OPERAND_PLUS; | |
560 | break; | |
561 | } | |
562 | ||
563 | exp[numops].X_op = 0; | |
564 | return (numops); | |
565 | } | |
566 | ||
567 | static unsigned long | |
e0c6ed95 | 568 | d10v_insert_operand (insn, op_type, value, left, fix) |
252b5132 RH |
569 | unsigned long insn; |
570 | int op_type; | |
571 | offsetT value; | |
572 | int left; | |
573 | fixS *fix; | |
574 | { | |
575 | int shift, bits; | |
576 | ||
577 | shift = d10v_operands[op_type].shift; | |
578 | if (left) | |
579 | shift += 15; | |
580 | ||
581 | bits = d10v_operands[op_type].bits; | |
582 | ||
e0c6ed95 | 583 | /* Truncate to the proper number of bits. */ |
252b5132 | 584 | if (check_range (value, bits, d10v_operands[op_type].flags)) |
ab3e48dc | 585 | as_bad_where (fix->fx_file, fix->fx_line, |
fbdbf472 | 586 | _("operand out of range: %ld"), (long) value); |
252b5132 RH |
587 | |
588 | value &= 0x7FFFFFFF >> (31 - bits); | |
589 | insn |= (value << shift); | |
590 | ||
591 | return insn; | |
592 | } | |
593 | ||
e0c6ed95 AM |
594 | /* Take a pointer to the opcode entry in the opcode table and the |
595 | array of operand expressions. Return the instruction. */ | |
252b5132 RH |
596 | |
597 | static unsigned long | |
e0c6ed95 | 598 | build_insn (opcode, opers, insn) |
252b5132 RH |
599 | struct d10v_opcode *opcode; |
600 | expressionS *opers; | |
601 | unsigned long insn; | |
602 | { | |
603 | int i, bits, shift, flags, format; | |
604 | unsigned long number; | |
e0c6ed95 AM |
605 | |
606 | /* The insn argument is only used for the DIVS kludge. */ | |
252b5132 RH |
607 | if (insn) |
608 | format = LONG_R; | |
609 | else | |
610 | { | |
611 | insn = opcode->opcode; | |
612 | format = opcode->format; | |
613 | } | |
e0c6ed95 AM |
614 | |
615 | for (i = 0; opcode->operands[i]; i++) | |
252b5132 RH |
616 | { |
617 | flags = d10v_operands[opcode->operands[i]].flags; | |
618 | bits = d10v_operands[opcode->operands[i]].bits; | |
619 | shift = d10v_operands[opcode->operands[i]].shift; | |
620 | number = opers[i].X_add_number; | |
621 | ||
e0c6ed95 | 622 | if (flags & OPERAND_REG) |
252b5132 RH |
623 | { |
624 | number &= REGISTER_MASK; | |
625 | if (format == LONG_L) | |
626 | shift += 15; | |
627 | } | |
628 | ||
e0c6ed95 | 629 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant) |
252b5132 | 630 | { |
e0c6ed95 | 631 | /* Now create a fixup. */ |
252b5132 RH |
632 | |
633 | if (fixups->fc >= MAX_INSN_FIXUPS) | |
634 | as_fatal (_("too many fixups")); | |
635 | ||
636 | if (AT_WORD_P (&opers[i])) | |
637 | { | |
e0c6ed95 | 638 | /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD). */ |
252b5132 RH |
639 | fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18; |
640 | opers[i].X_op = O_symbol; | |
e0c6ed95 | 641 | opers[i].X_op_symbol = NULL; /* Should free it. */ |
252b5132 RH |
642 | /* number is left shifted by AT_WORD_RIGHT_SHIFT so |
643 | that, it is aligned with the symbol's value. Later, | |
644 | BFD_RELOC_D10V_18 will right shift (symbol_value + | |
e0c6ed95 | 645 | X_add_number). */ |
252b5132 RH |
646 | number <<= AT_WORD_RIGHT_SHIFT; |
647 | opers[i].X_add_number = number; | |
648 | } | |
649 | else | |
e0c6ed95 AM |
650 | fixups->fix[fixups->fc].reloc = |
651 | get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]); | |
252b5132 | 652 | |
e0c6ed95 | 653 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 || |
252b5132 | 654 | fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18) |
e0c6ed95 | 655 | fixups->fix[fixups->fc].size = 2; |
252b5132 RH |
656 | else |
657 | fixups->fix[fixups->fc].size = 4; | |
e0c6ed95 | 658 | |
252b5132 RH |
659 | fixups->fix[fixups->fc].exp = opers[i]; |
660 | fixups->fix[fixups->fc].operand = opcode->operands[i]; | |
e0c6ed95 AM |
661 | fixups->fix[fixups->fc].pcrel = |
662 | (flags & OPERAND_ADDR) ? true : false; | |
252b5132 RH |
663 | (fixups->fc)++; |
664 | } | |
665 | ||
e0c6ed95 | 666 | /* Truncate to the proper number of bits. */ |
252b5132 | 667 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) |
fbdbf472 | 668 | as_bad (_("operand out of range: %lu"), number); |
252b5132 RH |
669 | number &= 0x7FFFFFFF >> (31 - bits); |
670 | insn = insn | (number << shift); | |
671 | } | |
672 | ||
cc8a6dd0 KH |
673 | /* kludge: for DIVS, we need to put the operands in twice on the second |
674 | pass, format is changed to LONG_R to force the second set of operands | |
fbdbf472 | 675 | to not be shifted over 15. */ |
e0c6ed95 | 676 | if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L)) |
252b5132 | 677 | insn = build_insn (opcode, opers, insn); |
e0c6ed95 | 678 | |
252b5132 RH |
679 | return insn; |
680 | } | |
681 | ||
e0c6ed95 AM |
682 | /* Write out a long form instruction. */ |
683 | ||
252b5132 | 684 | static void |
bccba5f0 | 685 | write_long (insn, fx) |
252b5132 RH |
686 | unsigned long insn; |
687 | Fixups *fx; | |
688 | { | |
689 | int i, where; | |
e0c6ed95 | 690 | char *f = frag_more (4); |
252b5132 RH |
691 | |
692 | insn |= FM11; | |
693 | number_to_chars_bigendian (f, insn, 4); | |
694 | ||
e0c6ed95 | 695 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
696 | { |
697 | if (fx->fix[i].reloc) | |
e0c6ed95 AM |
698 | { |
699 | where = f - frag_now->fr_literal; | |
252b5132 RH |
700 | if (fx->fix[i].size == 2) |
701 | where += 2; | |
702 | ||
703 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
e0c6ed95 | 704 | fx->fix[i].operand |= 4096; |
252b5132 RH |
705 | |
706 | fix_new_exp (frag_now, | |
707 | where, | |
708 | fx->fix[i].size, | |
709 | &(fx->fix[i].exp), | |
710 | fx->fix[i].pcrel, | |
711 | fx->fix[i].operand|2048); | |
712 | } | |
713 | } | |
714 | fx->fc = 0; | |
715 | } | |
716 | ||
e0c6ed95 | 717 | /* Write out a short form instruction by itself. */ |
252b5132 | 718 | |
252b5132 | 719 | static void |
e0c6ed95 | 720 | write_1_short (opcode, insn, fx) |
252b5132 RH |
721 | struct d10v_opcode *opcode; |
722 | unsigned long insn; | |
723 | Fixups *fx; | |
724 | { | |
e0c6ed95 | 725 | char *f = frag_more (4); |
252b5132 RH |
726 | int i, where; |
727 | ||
728 | if (opcode->exec_type & PARONLY) | |
729 | as_fatal (_("Instruction must be executed in parallel with another instruction.")); | |
730 | ||
cc8a6dd0 KH |
731 | /* The other container needs to be NOP. |
732 | According to 4.3.1: for FM=00, sub-instructions performed only by IU | |
fbdbf472 | 733 | cannot be encoded in L-container. */ |
252b5132 | 734 | if (opcode->unit == IU) |
e0c6ed95 | 735 | insn |= FM00 | (NOP << 15); /* Right container. */ |
252b5132 | 736 | else |
e0c6ed95 | 737 | insn = FM00 | (insn << 15) | NOP; /* Left container. */ |
252b5132 RH |
738 | |
739 | number_to_chars_bigendian (f, insn, 4); | |
e0c6ed95 | 740 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
741 | { |
742 | if (fx->fix[i].reloc) | |
e0c6ed95 AM |
743 | { |
744 | where = f - frag_now->fr_literal; | |
252b5132 RH |
745 | if (fx->fix[i].size == 2) |
746 | where += 2; | |
747 | ||
748 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
e0c6ed95 | 749 | fx->fix[i].operand |= 4096; |
252b5132 | 750 | |
e0c6ed95 AM |
751 | /* If it's an R reloc, we may have to switch it to L. */ |
752 | if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) | |
753 | && (opcode->unit != IU)) | |
252b5132 RH |
754 | fx->fix[i].operand |= 1024; |
755 | ||
756 | fix_new_exp (frag_now, | |
e0c6ed95 | 757 | where, |
252b5132 RH |
758 | fx->fix[i].size, |
759 | &(fx->fix[i].exp), | |
760 | fx->fix[i].pcrel, | |
761 | fx->fix[i].operand|2048); | |
762 | } | |
763 | } | |
764 | fx->fc = 0; | |
765 | } | |
766 | ||
0a44c2b1 DL |
767 | /* Expects two short instructions. |
768 | If possible, writes out both as a single packed instruction. | |
769 | Otherwise, writes out the first one, packed with a NOP. | |
e0c6ed95 | 770 | Returns number of instructions not written out. */ |
0a44c2b1 | 771 | |
252b5132 | 772 | static int |
e0c6ed95 | 773 | write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) |
252b5132 RH |
774 | struct d10v_opcode *opcode1, *opcode2; |
775 | unsigned long insn1, insn2; | |
0a44c2b1 | 776 | packing_type exec_type; |
252b5132 RH |
777 | Fixups *fx; |
778 | { | |
779 | unsigned long insn; | |
780 | char *f; | |
e0c6ed95 | 781 | int i, j, where; |
252b5132 | 782 | |
e0c6ed95 AM |
783 | if ((exec_type != PACK_PARALLEL) |
784 | && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY))) | |
252b5132 | 785 | as_fatal (_("Instruction must be executed in parallel")); |
252b5132 | 786 | |
e0c6ed95 AM |
787 | if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE)) |
788 | as_fatal (_("Long instructions may not be combined.")); | |
252b5132 | 789 | |
e0c6ed95 | 790 | switch (exec_type) |
252b5132 | 791 | { |
e0c6ed95 | 792 | case PACK_UNSPEC: /* Order not specified. */ |
0a44c2b1 DL |
793 | if (opcode1->exec_type & ALONE) |
794 | { | |
fbdbf472 | 795 | /* Case of a short branch on a separate GAS line. Pack with NOP. */ |
0a44c2b1 DL |
796 | write_1_short (opcode1, insn1, fx->next); |
797 | return 1; | |
798 | } | |
e0c6ed95 AM |
799 | if (Optimizing |
800 | && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
252b5132 | 801 | { |
e0c6ed95 | 802 | /* Parallel. */ |
252b5132 RH |
803 | if (opcode1->unit == IU) |
804 | insn = FM00 | (insn2 << 15) | insn1; | |
805 | else if (opcode2->unit == MU) | |
806 | insn = FM00 | (insn2 << 15) | insn1; | |
807 | else | |
c2c607a4 | 808 | insn = FM00 | (insn1 << 15) | insn2; |
252b5132 | 809 | } |
e0c6ed95 AM |
810 | else if (opcode1->unit == IU) |
811 | /* Reverse sequential with IU opcode1 on right and done first. */ | |
0a44c2b1 | 812 | insn = FM10 | (insn2 << 15) | insn1; |
252b5132 | 813 | else |
c2c607a4 AO |
814 | /* Sequential with non-IU opcode1 on left and done first. */ |
815 | insn = FM01 | (insn1 << 15) | insn2; | |
252b5132 | 816 | break; |
252b5132 | 817 | |
0a44c2b1 DL |
818 | case PACK_PARALLEL: |
819 | if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ) | |
e0c6ed95 AM |
820 | as_fatal |
821 | (_("One of these instructions may not be executed in parallel.")); | |
252b5132 RH |
822 | if (opcode1->unit == IU) |
823 | { | |
824 | if (opcode2->unit == IU) | |
825 | as_fatal (_("Two IU instructions may not be executed in parallel")); | |
e0c6ed95 | 826 | if (!flag_warn_suppress_instructionswap) |
252b5132 | 827 | as_warn (_("Swapping instruction order")); |
e0c6ed95 | 828 | insn = FM00 | (insn2 << 15) | insn1; |
252b5132 RH |
829 | } |
830 | else if (opcode2->unit == MU) | |
831 | { | |
832 | if (opcode1->unit == MU) | |
833 | as_fatal (_("Two MU instructions may not be executed in parallel")); | |
e0c6ed95 | 834 | if (!flag_warn_suppress_instructionswap) |
252b5132 RH |
835 | as_warn (_("Swapping instruction order")); |
836 | insn = FM00 | (insn2 << 15) | insn1; | |
837 | } | |
838 | else | |
c2c607a4 | 839 | insn = FM00 | (insn1 << 15) | insn2; |
fbdbf472 | 840 | check_resource_conflict (opcode1, insn1, opcode2, insn2); |
252b5132 | 841 | break; |
0a44c2b1 | 842 | |
0a44c2b1 | 843 | case PACK_LEFT_RIGHT: |
252b5132 | 844 | if (opcode1->unit != IU) |
e0c6ed95 | 845 | insn = FM01 | (insn1 << 15) | insn2; |
252b5132 RH |
846 | else if (opcode2->unit == MU || opcode2->unit == EITHER) |
847 | { | |
e0c6ed95 | 848 | if (!flag_warn_suppress_instructionswap) |
252b5132 | 849 | as_warn (_("Swapping instruction order")); |
0a44c2b1 | 850 | insn = FM10 | (insn2 << 15) | insn1; |
252b5132 RH |
851 | } |
852 | else | |
853 | as_fatal (_("IU instruction may not be in the left container")); | |
0a44c2b1 DL |
854 | if (opcode1->exec_type & ALONE) |
855 | as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); | |
252b5132 | 856 | break; |
0a44c2b1 | 857 | |
0a44c2b1 | 858 | case PACK_RIGHT_LEFT: |
252b5132 RH |
859 | if (opcode2->unit != MU) |
860 | insn = FM10 | (insn1 << 15) | insn2; | |
861 | else if (opcode1->unit == IU || opcode1->unit == EITHER) | |
862 | { | |
e0c6ed95 | 863 | if (!flag_warn_suppress_instructionswap) |
252b5132 | 864 | as_warn (_("Swapping instruction order")); |
e0c6ed95 | 865 | insn = FM01 | (insn2 << 15) | insn1; |
252b5132 RH |
866 | } |
867 | else | |
868 | as_fatal (_("MU instruction may not be in the right container")); | |
0a44c2b1 DL |
869 | if (opcode2->exec_type & ALONE) |
870 | as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); | |
252b5132 | 871 | break; |
0a44c2b1 | 872 | |
252b5132 RH |
873 | default: |
874 | as_fatal (_("unknown execution type passed to write_2_short()")); | |
875 | } | |
876 | ||
e0c6ed95 | 877 | f = frag_more (4); |
252b5132 RH |
878 | number_to_chars_bigendian (f, insn, 4); |
879 | ||
c2c607a4 AO |
880 | /* Process fixup chains. fx refers to insn2 when j == 0, and to |
881 | insn1 when j == 1. Yes, it's reversed. */ | |
0a44c2b1 | 882 | |
e0c6ed95 | 883 | for (j = 0; j < 2; j++) |
252b5132 | 884 | { |
e0c6ed95 | 885 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
886 | { |
887 | if (fx->fix[i].reloc) | |
888 | { | |
e0c6ed95 | 889 | where = f - frag_now->fr_literal; |
252b5132 RH |
890 | if (fx->fix[i].size == 2) |
891 | where += 2; | |
e0c6ed95 | 892 | |
c2c607a4 AO |
893 | if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R |
894 | /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to | |
895 | the instruction in the L container has to be | |
896 | adjusted to BDF_RELOC_D10V_10_PCREL_L. When | |
897 | j==0, we're processing insn2's operands, so we | |
898 | want to mark the operand if insn2 is *not* in the | |
899 | R container. When j==1, we're processing insn1's | |
900 | operands, so we want to mark the operand if insn2 | |
901 | *is* in the R container. Note that, if two | |
902 | instructions are identical, we're never going to | |
903 | swap them, so the test is safe. */ | |
904 | && j == ((insn & 0x7fff) == insn2)) | |
252b5132 | 905 | fx->fix[i].operand |= 1024; |
e0c6ed95 | 906 | |
252b5132 | 907 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) |
e0c6ed95 | 908 | fx->fix[i].operand |= 4096; |
252b5132 RH |
909 | |
910 | fix_new_exp (frag_now, | |
e0c6ed95 | 911 | where, |
252b5132 RH |
912 | fx->fix[i].size, |
913 | &(fx->fix[i].exp), | |
914 | fx->fix[i].pcrel, | |
915 | fx->fix[i].operand|2048); | |
916 | } | |
917 | } | |
918 | fx->fc = 0; | |
919 | fx = fx->next; | |
920 | } | |
921 | return (0); | |
922 | } | |
923 | ||
e0c6ed95 AM |
924 | /* Check 2 instructions and determine if they can be safely |
925 | executed in parallel. Return 1 if they can be. */ | |
252b5132 | 926 | |
252b5132 RH |
927 | static int |
928 | parallel_ok (op1, insn1, op2, insn2, exec_type) | |
929 | struct d10v_opcode *op1, *op2; | |
930 | unsigned long insn1, insn2; | |
0a44c2b1 | 931 | packing_type exec_type; |
252b5132 RH |
932 | { |
933 | int i, j, flags, mask, shift, regno; | |
934 | unsigned long ins, mod[2], used[2]; | |
935 | struct d10v_opcode *op; | |
936 | ||
937 | if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0 | |
938 | || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0 | |
939 | || (op1->unit == BOTH) || (op2->unit == BOTH) | |
940 | || (op1->unit == IU && op2->unit == IU) | |
941 | || (op1->unit == MU && op2->unit == MU)) | |
942 | return 0; | |
943 | ||
0a44c2b1 | 944 | /* If this is auto parallization, and either instruction is a branch, |
e0c6ed95 | 945 | don't parallel. */ |
0a44c2b1 | 946 | if (exec_type == PACK_UNSPEC |
cc8a6dd0 | 947 | && (op1->exec_type & (ALONE | BRANCH) |
fbdbf472 | 948 | || op2->exec_type & (ALONE | BRANCH))) |
252b5132 RH |
949 | return 0; |
950 | ||
951 | /* The idea here is to create two sets of bitmasks (mod and used) | |
952 | which indicate which registers are modified or used by each | |
953 | instruction. The operation can only be done in parallel if | |
954 | instruction 1 and instruction 2 modify different registers, and | |
955 | the first instruction does not modify registers that the second | |
956 | is using (The second instruction can modify registers that the | |
957 | first is using as they are only written back after the first | |
958 | instruction has completed). Accesses to control registers, PSW, | |
959 | and memory are treated as accesses to a single register. So if | |
960 | both instructions write memory or if the first instruction writes | |
961 | memory and the second reads, then they cannot be done in | |
962 | parallel. Likewise, if the first instruction mucks with the psw | |
963 | and the second reads the PSW (which includes C, F0, and F1), then | |
e0c6ed95 | 964 | they cannot operate safely in parallel. */ |
252b5132 | 965 | |
cc8a6dd0 KH |
966 | /* The bitmasks (mod and used) look like this (bit 31 = MSB). |
967 | r0-r15 0-15 | |
fbdbf472 TR |
968 | a0-a1 16-17 |
969 | cr (not psw) 18 | |
970 | psw 19 | |
971 | mem 20 */ | |
252b5132 | 972 | |
e0c6ed95 | 973 | for (j = 0; j < 2; j++) |
252b5132 RH |
974 | { |
975 | if (j == 0) | |
976 | { | |
977 | op = op1; | |
978 | ins = insn1; | |
979 | } | |
980 | else | |
981 | { | |
982 | op = op2; | |
983 | ins = insn2; | |
984 | } | |
985 | mod[j] = used[j] = 0; | |
986 | if (op->exec_type & BRANCH_LINK) | |
987 | mod[j] |= 1 << 13; | |
988 | ||
989 | for (i = 0; op->operands[i]; i++) | |
990 | { | |
991 | flags = d10v_operands[op->operands[i]].flags; | |
992 | shift = d10v_operands[op->operands[i]].shift; | |
993 | mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); | |
994 | if (flags & OPERAND_REG) | |
995 | { | |
996 | regno = (ins >> shift) & mask; | |
e0c6ed95 | 997 | if (flags & (OPERAND_ACC0 | OPERAND_ACC1)) |
252b5132 | 998 | regno += 16; |
e0c6ed95 AM |
999 | else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */ |
1000 | { | |
252b5132 RH |
1001 | if (regno == 0) |
1002 | regno = 19; | |
1003 | else | |
e0c6ed95 | 1004 | regno = 18; |
252b5132 | 1005 | } |
e0c6ed95 | 1006 | else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG)) |
252b5132 | 1007 | regno = 19; |
e0c6ed95 AM |
1008 | |
1009 | if (flags & OPERAND_DEST) | |
252b5132 RH |
1010 | { |
1011 | mod[j] |= 1 << regno; | |
1012 | if (flags & OPERAND_EVEN) | |
1013 | mod[j] |= 1 << (regno + 1); | |
1014 | } | |
1015 | else | |
1016 | { | |
e0c6ed95 | 1017 | used[j] |= 1 << regno; |
252b5132 RH |
1018 | if (flags & OPERAND_EVEN) |
1019 | used[j] |= 1 << (regno + 1); | |
1020 | ||
1021 | /* Auto inc/dec also modifies the register. */ | |
e0c6ed95 AM |
1022 | if (op->operands[i + 1] != 0 |
1023 | && (d10v_operands[op->operands[i + 1]].flags | |
252b5132 RH |
1024 | & (OPERAND_PLUS | OPERAND_MINUS)) != 0) |
1025 | mod[j] |= 1 << regno; | |
1026 | } | |
1027 | } | |
1028 | else if (flags & OPERAND_ATMINUS) | |
1029 | { | |
e0c6ed95 | 1030 | /* SP implicitly used/modified. */ |
252b5132 RH |
1031 | mod[j] |= 1 << 15; |
1032 | used[j] |= 1 << 15; | |
1033 | } | |
1034 | } | |
1035 | if (op->exec_type & RMEM) | |
1036 | used[j] |= 1 << 20; | |
1037 | else if (op->exec_type & WMEM) | |
1038 | mod[j] |= 1 << 20; | |
1039 | else if (op->exec_type & RF0) | |
1040 | used[j] |= 1 << 19; | |
1041 | else if (op->exec_type & WF0) | |
1042 | mod[j] |= 1 << 19; | |
1043 | else if (op->exec_type & WCAR) | |
1044 | mod[j] |= 1 << 19; | |
1045 | } | |
1046 | if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0) | |
1047 | return 1; | |
1048 | return 0; | |
1049 | } | |
1050 | ||
fbdbf472 TR |
1051 | /* Determine if there are any resource conflicts among two manually |
1052 | parallelized instructions. Some of this was lifted from parallel_ok. */ | |
1053 | ||
cc8a6dd0 | 1054 | static void |
fbdbf472 TR |
1055 | check_resource_conflict (op1, insn1, op2, insn2) |
1056 | struct d10v_opcode *op1, *op2; | |
1057 | unsigned long insn1, insn2; | |
1058 | { | |
1059 | int i, j, flags, mask, shift, regno; | |
1060 | unsigned long ins, mod[2], used[2]; | |
1061 | struct d10v_opcode *op; | |
1062 | ||
1063 | if ((op1->exec_type & SEQ) | |
1064 | || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY))) | |
1065 | { | |
1066 | as_warn (_("packing conflict: %s must dispatch sequentially"), | |
1067 | op1->name); | |
1068 | return; | |
1069 | } | |
1070 | ||
1071 | if ((op2->exec_type & SEQ) | |
1072 | || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY))) | |
1073 | { | |
1074 | as_warn (_("packing conflict: %s must dispatch sequentially"), | |
1075 | op2->name); | |
1076 | return; | |
1077 | } | |
1078 | ||
1079 | /* The idea here is to create two sets of bitmasks (mod and used) | |
1080 | which indicate which registers are modified or used by each | |
1081 | instruction. The operation can only be done in parallel if | |
1082 | instruction 1 and instruction 2 modify different registers, and | |
1083 | the first instruction does not modify registers that the second | |
1084 | is using (The second instruction can modify registers that the | |
1085 | first is using as they are only written back after the first | |
1086 | instruction has completed). Accesses to control registers | |
1087 | and memory are treated as accesses to a single register. So if | |
1088 | both instructions write memory or if the first instruction writes | |
1089 | memory and the second reads, then they cannot be done in | |
1090 | parallel. We treat reads to the PSW (which includes C, F0, and F1) | |
1091 | in isolation. So simultaneously writing C and F0 in two different | |
1092 | sub-instructions is permitted. */ | |
1093 | ||
1094 | /* The bitmasks (mod and used) look like this (bit 31 = MSB). | |
1095 | r0-r15 0-15 | |
1096 | a0-a1 16-17 | |
1097 | cr (not psw) 18 | |
1098 | psw(other) 19 | |
1099 | mem 20 | |
1100 | psw(C flag) 21 | |
1101 | psw(F0 flag) 22 */ | |
1102 | ||
1103 | for (j = 0; j < 2; j++) | |
1104 | { | |
1105 | if (j == 0) | |
1106 | { | |
1107 | op = op1; | |
1108 | ins = insn1; | |
1109 | } | |
1110 | else | |
1111 | { | |
1112 | op = op2; | |
1113 | ins = insn2; | |
1114 | } | |
1115 | mod[j] = used[j] = 0; | |
1116 | if (op->exec_type & BRANCH_LINK) | |
1117 | mod[j] |= 1 << 13; | |
1118 | ||
1119 | for (i = 0; op->operands[i]; i++) | |
1120 | { | |
1121 | flags = d10v_operands[op->operands[i]].flags; | |
1122 | shift = d10v_operands[op->operands[i]].shift; | |
1123 | mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); | |
1124 | if (flags & OPERAND_REG) | |
1125 | { | |
1126 | regno = (ins >> shift) & mask; | |
1127 | if (flags & (OPERAND_ACC0 | OPERAND_ACC1)) | |
1128 | regno += 16; | |
1129 | else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */ | |
cc8a6dd0 | 1130 | { |
fbdbf472 TR |
1131 | if (regno == 0) |
1132 | regno = 19; | |
1133 | else | |
cc8a6dd0 | 1134 | regno = 18; |
fbdbf472 TR |
1135 | } |
1136 | else if (flags & OPERAND_FFLAG) | |
1137 | regno = 22; | |
1138 | else if (flags & OPERAND_CFLAG) | |
1139 | regno = 21; | |
cc8a6dd0 KH |
1140 | |
1141 | if ( flags & OPERAND_DEST ) | |
fbdbf472 TR |
1142 | { |
1143 | mod[j] |= 1 << regno; | |
1144 | if (flags & OPERAND_EVEN) | |
1145 | mod[j] |= 1 << (regno + 1); | |
1146 | } | |
cc8a6dd0 KH |
1147 | else |
1148 | { | |
1149 | used[j] |= 1 << regno ; | |
1150 | if (flags & OPERAND_EVEN) | |
1151 | used[j] |= 1 << (regno + 1); | |
1152 | ||
1153 | /* Auto inc/dec also modifies the register. */ | |
1154 | if (op->operands[i+1] != 0 | |
1155 | && (d10v_operands[op->operands[i+1]].flags | |
1156 | & (OPERAND_PLUS | OPERAND_MINUS)) != 0) | |
1157 | mod[j] |= 1 << regno; | |
1158 | } | |
fbdbf472 TR |
1159 | } |
1160 | else if (flags & OPERAND_ATMINUS) | |
1161 | { | |
1162 | /* SP implicitly used/modified. */ | |
1163 | mod[j] |= 1 << 15; | |
1164 | used[j] |= 1 << 15; | |
1165 | } | |
1166 | } | |
1167 | if (op->exec_type & RMEM) | |
1168 | used[j] |= 1 << 20; | |
1169 | else if (op->exec_type & WMEM) | |
1170 | mod[j] |= 1 << 20; | |
1171 | else if (op->exec_type & RF0) | |
1172 | used[j] |= 1 << 22; | |
1173 | else if (op->exec_type & WF0) | |
1174 | mod[j] |= 1 << 22; | |
1175 | else if (op->exec_type & WCAR) | |
1176 | mod[j] |= 1 << 21; | |
1177 | } | |
1178 | if ((mod[0] & mod[1]) == 0) | |
1179 | return; | |
1180 | else | |
1181 | { | |
1182 | unsigned long x; | |
1183 | x = mod[0] & mod[1]; | |
1184 | ||
1185 | for (j = 0; j <= 15; j++) | |
1186 | if (x & (1 << j)) | |
1187 | as_warn (_("resource conflict (R%d)"), j); | |
1188 | for (j = 16; j <= 17; j++) | |
1189 | if (x & (1 << j)) | |
1190 | as_warn (_("resource conflict (A%d)"), j - 16); | |
1191 | if (x & (1 << 19)) | |
1192 | as_warn (_("resource conflict (PSW)")); | |
1193 | if (x & (1 << 21)) | |
1194 | as_warn (_("resource conflict (C flag)")); | |
1195 | if (x & (1 << 22)) | |
1196 | as_warn (_("resource conflict (F flag)")); | |
1197 | } | |
1198 | } | |
1199 | ||
e0c6ed95 AM |
1200 | /* This is the main entry point for the machine-dependent assembler. |
1201 | STR points to a machine-dependent instruction. This function is | |
1202 | supposed to emit the frags/bytes it assembles to. For the D10V, it | |
1203 | mostly handles the special VLIW parsing and packing and leaves the | |
1204 | difficult stuff to do_assemble(). */ | |
252b5132 RH |
1205 | |
1206 | static unsigned long prev_insn; | |
1207 | static struct d10v_opcode *prev_opcode = 0; | |
1208 | static subsegT prev_subseg; | |
1209 | static segT prev_seg = 0;; | |
252b5132 RH |
1210 | |
1211 | void | |
1212 | md_assemble (str) | |
1213 | char *str; | |
1214 | { | |
e0c6ed95 | 1215 | /* etype is saved extype. For multi-line instructions. */ |
0a44c2b1 | 1216 | |
e0c6ed95 | 1217 | packing_type extype = PACK_UNSPEC; /* Parallel, etc. */ |
0a44c2b1 | 1218 | |
e0c6ed95 | 1219 | struct d10v_opcode *opcode; |
252b5132 | 1220 | unsigned long insn; |
e0c6ed95 | 1221 | char *str2; |
252b5132 | 1222 | |
0a44c2b1 | 1223 | if (etype == PACK_UNSPEC) |
252b5132 | 1224 | { |
e0c6ed95 | 1225 | /* Look for the special multiple instruction separators. */ |
252b5132 | 1226 | str2 = strstr (str, "||"); |
e0c6ed95 | 1227 | if (str2) |
0a44c2b1 | 1228 | extype = PACK_PARALLEL; |
252b5132 RH |
1229 | else |
1230 | { | |
1231 | str2 = strstr (str, "->"); | |
e0c6ed95 | 1232 | if (str2) |
0a44c2b1 | 1233 | extype = PACK_LEFT_RIGHT; |
252b5132 RH |
1234 | else |
1235 | { | |
1236 | str2 = strstr (str, "<-"); | |
e0c6ed95 | 1237 | if (str2) |
0a44c2b1 | 1238 | extype = PACK_RIGHT_LEFT; |
252b5132 RH |
1239 | } |
1240 | } | |
fbdbf472 TR |
1241 | |
1242 | /* str2 points to the separator, if there is one. */ | |
e0c6ed95 | 1243 | if (str2) |
252b5132 RH |
1244 | { |
1245 | *str2 = 0; | |
e0c6ed95 AM |
1246 | |
1247 | /* If two instructions are present and we already have one saved, | |
1248 | then first write out the saved one. */ | |
252b5132 | 1249 | d10v_cleanup (); |
e0c6ed95 AM |
1250 | |
1251 | /* Assemble first instruction and save it. */ | |
252b5132 | 1252 | prev_insn = do_assemble (str, &prev_opcode); |
3cd4dda7 DD |
1253 | prev_seg = now_seg; |
1254 | prev_subseg = now_subseg; | |
bccba5f0 | 1255 | if (prev_insn == (unsigned long) -1) |
252b5132 RH |
1256 | as_fatal (_("can't find opcode ")); |
1257 | fixups = fixups->next; | |
1258 | str = str2 + 2; | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | insn = do_assemble (str, &opcode); | |
bccba5f0 | 1263 | if (insn == (unsigned long) -1) |
252b5132 | 1264 | { |
0a44c2b1 | 1265 | if (extype != PACK_UNSPEC) |
252b5132 RH |
1266 | { |
1267 | etype = extype; | |
1268 | return; | |
1269 | } | |
1270 | as_fatal (_("can't find opcode ")); | |
1271 | } | |
1272 | ||
0a44c2b1 | 1273 | if (etype != PACK_UNSPEC) |
252b5132 RH |
1274 | { |
1275 | extype = etype; | |
0a44c2b1 | 1276 | etype = PACK_UNSPEC; |
252b5132 RH |
1277 | } |
1278 | ||
e0c6ed95 AM |
1279 | /* If this is a long instruction, write it and any previous short |
1280 | instruction. */ | |
1281 | if (opcode->format & LONG_OPCODE) | |
252b5132 | 1282 | { |
e0c6ed95 | 1283 | if (extype != PACK_UNSPEC) |
252b5132 RH |
1284 | as_fatal (_("Unable to mix instructions as specified")); |
1285 | d10v_cleanup (); | |
bccba5f0 | 1286 | write_long (insn, fixups); |
252b5132 RH |
1287 | prev_opcode = NULL; |
1288 | return; | |
1289 | } | |
e0c6ed95 AM |
1290 | |
1291 | if (prev_opcode | |
1292 | && prev_seg | |
1293 | && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
0a44c2b1 | 1294 | d10v_cleanup (); |
e0c6ed95 AM |
1295 | |
1296 | if (prev_opcode | |
cc8a6dd0 | 1297 | && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype, |
fbdbf472 | 1298 | fixups))) |
252b5132 | 1299 | { |
e0c6ed95 | 1300 | /* No instructions saved. */ |
252b5132 RH |
1301 | prev_opcode = NULL; |
1302 | } | |
1303 | else | |
1304 | { | |
e0c6ed95 | 1305 | if (extype != PACK_UNSPEC) |
252b5132 | 1306 | as_fatal (_("Unable to mix instructions as specified")); |
e0c6ed95 | 1307 | /* Save last instruction so it may be packed on next pass. */ |
252b5132 RH |
1308 | prev_opcode = opcode; |
1309 | prev_insn = insn; | |
1310 | prev_seg = now_seg; | |
1311 | prev_subseg = now_subseg; | |
1312 | fixups = fixups->next; | |
1313 | } | |
1314 | } | |
1315 | ||
e0c6ed95 AM |
1316 | /* Assemble a single instruction. |
1317 | Return an opcode, or -1 (an invalid opcode) on error. */ | |
252b5132 RH |
1318 | |
1319 | static unsigned long | |
e0c6ed95 | 1320 | do_assemble (str, opcode) |
252b5132 RH |
1321 | char *str; |
1322 | struct d10v_opcode **opcode; | |
1323 | { | |
1324 | unsigned char *op_start, *save; | |
1325 | unsigned char *op_end; | |
1326 | char name[20]; | |
1327 | int nlen = 0; | |
1328 | expressionS myops[6]; | |
1329 | unsigned long insn; | |
1330 | ||
1331 | /* Drop leading whitespace. */ | |
1332 | while (*str == ' ') | |
1333 | str++; | |
1334 | ||
1335 | /* Find the opcode end. */ | |
1336 | for (op_start = op_end = (unsigned char *) (str); | |
1337 | *op_end | |
1338 | && nlen < 20 | |
1339 | && !is_end_of_line[*op_end] && *op_end != ' '; | |
1340 | op_end++) | |
1341 | { | |
3882b010 | 1342 | name[nlen] = TOLOWER (op_start[nlen]); |
252b5132 RH |
1343 | nlen++; |
1344 | } | |
1345 | name[nlen] = 0; | |
1346 | ||
1347 | if (nlen == 0) | |
1348 | return -1; | |
e0c6ed95 | 1349 | |
252b5132 | 1350 | /* Find the first opcode with the proper name. */ |
e0c6ed95 | 1351 | *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name); |
252b5132 | 1352 | if (*opcode == NULL) |
e0c6ed95 | 1353 | as_fatal (_("unknown opcode: %s"), name); |
252b5132 RH |
1354 | |
1355 | save = input_line_pointer; | |
1356 | input_line_pointer = op_end; | |
1357 | *opcode = find_opcode (*opcode, myops); | |
1358 | if (*opcode == 0) | |
1359 | return -1; | |
1360 | input_line_pointer = save; | |
1361 | ||
e0c6ed95 | 1362 | insn = build_insn ((*opcode), myops, 0); |
252b5132 RH |
1363 | return (insn); |
1364 | } | |
1365 | ||
fbdbf472 | 1366 | /* Find the symbol which has the same name as the register in exp. */ |
e0c6ed95 | 1367 | |
252b5132 RH |
1368 | static symbolS * |
1369 | find_symbol_matching_register (exp) | |
e0c6ed95 | 1370 | expressionS *exp; |
252b5132 RH |
1371 | { |
1372 | int i; | |
e0c6ed95 | 1373 | |
252b5132 RH |
1374 | if (exp->X_op != O_register) |
1375 | return NULL; | |
e0c6ed95 | 1376 | |
252b5132 RH |
1377 | /* Find the name of the register. */ |
1378 | for (i = d10v_reg_name_cnt (); i--;) | |
e0c6ed95 | 1379 | if (d10v_predefined_registers[i].value == exp->X_add_number) |
252b5132 RH |
1380 | break; |
1381 | ||
1382 | if (i < 0) | |
1383 | abort (); | |
1384 | ||
1385 | /* Now see if a symbol has been defined with the same name. */ | |
e0c6ed95 | 1386 | return symbol_find (d10v_predefined_registers[i].name); |
252b5132 RH |
1387 | } |
1388 | ||
e0c6ed95 AM |
1389 | /* Get a pointer to an entry in the opcode table. |
1390 | The function must look at all opcodes with the same name and use | |
1391 | the operands to choose the correct opcode. */ | |
252b5132 RH |
1392 | |
1393 | static struct d10v_opcode * | |
1394 | find_opcode (opcode, myops) | |
1395 | struct d10v_opcode *opcode; | |
1396 | expressionS myops[]; | |
1397 | { | |
bccba5f0 | 1398 | int i, match; |
252b5132 RH |
1399 | struct d10v_opcode *next_opcode; |
1400 | ||
e0c6ed95 | 1401 | /* Get all the operands and save them as expressions. */ |
252b5132 RH |
1402 | get_operands (myops); |
1403 | ||
e0c6ed95 AM |
1404 | /* Now see if the operand is a fake. If so, find the correct size |
1405 | instruction, if possible. */ | |
252b5132 RH |
1406 | if (opcode->format == OPCODE_FAKE) |
1407 | { | |
1408 | int opnum = opcode->operands[0]; | |
1409 | int flags; | |
e0c6ed95 | 1410 | |
252b5132 RH |
1411 | if (myops[opnum].X_op == O_register) |
1412 | { | |
1413 | myops[opnum].X_op = O_symbol; | |
e0c6ed95 AM |
1414 | myops[opnum].X_add_symbol = |
1415 | symbol_find_or_make ((char *) myops[opnum].X_op_symbol); | |
252b5132 RH |
1416 | myops[opnum].X_add_number = 0; |
1417 | myops[opnum].X_op_symbol = NULL; | |
1418 | } | |
1419 | ||
e0c6ed95 | 1420 | next_opcode = opcode + 1; |
252b5132 RH |
1421 | |
1422 | /* If the first operand is supposed to be a register, make sure | |
1423 | we got a valid one. */ | |
1424 | flags = d10v_operands[next_opcode->operands[0]].flags; | |
1425 | if (flags & OPERAND_REG) | |
1426 | { | |
1427 | int X_op = myops[0].X_op; | |
1428 | int num = myops[0].X_add_number; | |
1429 | ||
1430 | if (X_op != O_register | |
1431 | || (num & ~flags | |
1432 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 | |
55aa1bc4 AO |
1433 | | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)) |
1434 | || ((flags & OPERAND_SP) && ! (num & OPERAND_SP))) | |
252b5132 RH |
1435 | { |
1436 | as_bad (_("bad opcode or operands")); | |
1437 | return 0; | |
1438 | } | |
1439 | } | |
1440 | ||
e0c6ed95 AM |
1441 | if (myops[opnum].X_op == O_constant |
1442 | || (myops[opnum].X_op == O_symbol | |
1443 | && S_IS_DEFINED (myops[opnum].X_add_symbol) | |
1444 | && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg))) | |
252b5132 | 1445 | { |
e0c6ed95 | 1446 | for (i = 0; opcode->operands[i + 1]; i++) |
252b5132 RH |
1447 | { |
1448 | int bits = d10v_operands[next_opcode->operands[opnum]].bits; | |
1449 | int flags = d10v_operands[next_opcode->operands[opnum]].flags; | |
1450 | if (flags & OPERAND_ADDR) | |
1451 | bits += 2; | |
e0c6ed95 | 1452 | |
252b5132 RH |
1453 | if (myops[opnum].X_op == O_constant) |
1454 | { | |
1455 | if (!check_range (myops[opnum].X_add_number, bits, flags)) | |
fbdbf472 | 1456 | break; |
252b5132 RH |
1457 | } |
1458 | else | |
1459 | { | |
e0c6ed95 AM |
1460 | fragS *sym_frag; |
1461 | fragS *f; | |
3db10f32 NC |
1462 | unsigned long current_position; |
1463 | unsigned long symbol_position; | |
1464 | unsigned long value; | |
1465 | boolean found_symbol; | |
e0c6ed95 | 1466 | |
3db10f32 NC |
1467 | /* Calculate the address of the current instruction |
1468 | and the address of the symbol. Do this by summing | |
1469 | the offsets of previous frags until we reach the | |
1470 | frag containing the symbol, and the current frag. */ | |
1471 | sym_frag = symbol_get_frag (myops[opnum].X_add_symbol); | |
1472 | found_symbol = false; | |
1473 | ||
e0c6ed95 AM |
1474 | current_position = |
1475 | obstack_next_free (&frchain_now->frch_obstack) | |
1476 | - frag_now->fr_literal; | |
3db10f32 | 1477 | symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol); |
e0c6ed95 | 1478 | |
3db10f32 NC |
1479 | for (f = frchain_now->frch_root; f; f = f->fr_next) |
1480 | { | |
1481 | current_position += f->fr_fix + f->fr_offset; | |
e0c6ed95 | 1482 | |
3db10f32 NC |
1483 | if (f == sym_frag) |
1484 | found_symbol = true; | |
e0c6ed95 | 1485 | |
3db10f32 NC |
1486 | if (! found_symbol) |
1487 | symbol_position += f->fr_fix + f->fr_offset; | |
1488 | } | |
252b5132 | 1489 | |
3db10f32 | 1490 | value = symbol_position; |
e0c6ed95 | 1491 | |
252b5132 | 1492 | if (flags & OPERAND_ADDR) |
3db10f32 | 1493 | value -= current_position; |
e0c6ed95 | 1494 | |
252b5132 RH |
1495 | if (AT_WORD_P (&myops[opnum])) |
1496 | { | |
1497 | if (bits > 4) | |
1498 | { | |
1499 | bits += 2; | |
1500 | if (!check_range (value, bits, flags)) | |
fbdbf472 | 1501 | break; |
252b5132 RH |
1502 | } |
1503 | } | |
1504 | else if (!check_range (value, bits, flags)) | |
fbdbf472 | 1505 | break; |
252b5132 RH |
1506 | } |
1507 | next_opcode++; | |
1508 | } | |
fbdbf472 TR |
1509 | |
1510 | if (opcode->operands [i + 1] == 0) | |
1511 | as_fatal (_("value out of range")); | |
1512 | else | |
1513 | opcode = next_opcode; | |
252b5132 RH |
1514 | } |
1515 | else | |
1516 | { | |
e0c6ed95 | 1517 | /* Not a constant, so use a long instruction. */ |
fbdbf472 | 1518 | opcode += 2; |
252b5132 RH |
1519 | } |
1520 | } | |
fbdbf472 TR |
1521 | |
1522 | match = 0; | |
cc8a6dd0 | 1523 | |
fbdbf472 TR |
1524 | /* Now search the opcode table table for one with operands |
1525 | that matches what we've got. */ | |
1526 | while (!match) | |
252b5132 | 1527 | { |
fbdbf472 TR |
1528 | match = 1; |
1529 | for (i = 0; opcode->operands[i]; i++) | |
252b5132 | 1530 | { |
fbdbf472 TR |
1531 | int flags = d10v_operands[opcode->operands[i]].flags; |
1532 | int X_op = myops[i].X_op; | |
1533 | int num = myops[i].X_add_number; | |
1534 | ||
1535 | if (X_op == 0) | |
252b5132 | 1536 | { |
fbdbf472 TR |
1537 | match = 0; |
1538 | break; | |
1539 | } | |
252b5132 | 1540 | |
fbdbf472 TR |
1541 | if (flags & OPERAND_REG) |
1542 | { | |
1543 | if ((X_op != O_register) | |
1544 | || (num & ~flags | |
1545 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 | |
1546 | | OPERAND_FFLAG | OPERAND_CFLAG | |
1547 | | OPERAND_CONTROL)) | |
1548 | || ((flags & OPERAND_SP) && ! (num & OPERAND_SP))) | |
252b5132 RH |
1549 | { |
1550 | match = 0; | |
1551 | break; | |
1552 | } | |
fbdbf472 | 1553 | } |
e0c6ed95 | 1554 | |
fbdbf472 TR |
1555 | if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) || |
1556 | ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) || | |
1557 | ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) || | |
1558 | ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) || | |
1559 | ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR))))) | |
1560 | { | |
1561 | match = 0; | |
1562 | break; | |
1563 | } | |
e0c6ed95 | 1564 | |
cc8a6dd0 KH |
1565 | /* Unfortunatly, for the indirect operand in instructions such |
1566 | as ``ldb r1, @(c,r14)'' this function can be passed | |
1567 | X_op == O_register (because 'c' is a valid register name). | |
1568 | However we cannot just ignore the case when X_op == O_register | |
1569 | but flags & OPERAND_REG is null, so we check to see if a symbol | |
1570 | of the same name as the register exists. If the symbol does | |
1571 | exist, then the parser was unable to distinguish the two cases | |
fbdbf472 | 1572 | and we fix things here. (Ref: PR14826) */ |
e0c6ed95 | 1573 | |
fbdbf472 TR |
1574 | if (!(flags & OPERAND_REG) && (X_op == O_register)) |
1575 | { | |
1576 | symbolS * sym; | |
cc8a6dd0 | 1577 | |
fbdbf472 | 1578 | sym = find_symbol_matching_register (& myops[i]); |
e0c6ed95 | 1579 | |
fbdbf472 TR |
1580 | if (sym != NULL) |
1581 | { | |
1582 | myops[i].X_op = X_op = O_symbol; | |
1583 | myops[i].X_add_symbol = sym; | |
252b5132 | 1584 | } |
fbdbf472 TR |
1585 | else |
1586 | as_bad | |
1587 | (_("illegal operand - register name found where none expected")); | |
252b5132 | 1588 | } |
fbdbf472 | 1589 | } |
e0c6ed95 | 1590 | |
fbdbf472 | 1591 | /* We're only done if the operands matched so far AND there |
252b5132 | 1592 | are no more to check. */ |
fbdbf472 TR |
1593 | if (match && myops[i].X_op == 0) |
1594 | break; | |
1595 | else | |
1596 | match = 0; | |
252b5132 | 1597 | |
fbdbf472 | 1598 | next_opcode = opcode + 1; |
e0c6ed95 | 1599 | |
fbdbf472 TR |
1600 | if (next_opcode->opcode == 0) |
1601 | break; | |
e0c6ed95 | 1602 | |
fbdbf472 TR |
1603 | if (strcmp (next_opcode->name, opcode->name)) |
1604 | break; | |
e0c6ed95 | 1605 | |
fbdbf472 | 1606 | opcode = next_opcode; |
252b5132 RH |
1607 | } |
1608 | ||
e0c6ed95 | 1609 | if (!match) |
252b5132 RH |
1610 | { |
1611 | as_bad (_("bad opcode or operands")); | |
1612 | return (0); | |
1613 | } | |
1614 | ||
e0c6ed95 AM |
1615 | /* Check that all registers that are required to be even are. |
1616 | Also, if any operands were marked as registers, but were really symbols, | |
1617 | fix that here. */ | |
1618 | for (i = 0; opcode->operands[i]; i++) | |
252b5132 RH |
1619 | { |
1620 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) && | |
e0c6ed95 | 1621 | (myops[i].X_add_number & 1)) |
252b5132 | 1622 | as_fatal (_("Register number must be EVEN")); |
461448d8 AO |
1623 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_NOSP) |
1624 | && (myops[i].X_add_number & OPERAND_SP)) | |
1625 | as_bad (_("Unsupported use of sp")); | |
252b5132 RH |
1626 | if (myops[i].X_op == O_register) |
1627 | { | |
e0c6ed95 | 1628 | if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG)) |
252b5132 RH |
1629 | { |
1630 | myops[i].X_op = O_symbol; | |
e0c6ed95 AM |
1631 | myops[i].X_add_symbol = |
1632 | symbol_find_or_make ((char *) myops[i].X_op_symbol); | |
252b5132 RH |
1633 | myops[i].X_add_number = 0; |
1634 | myops[i].X_op_symbol = NULL; | |
1635 | } | |
1636 | } | |
fbdbf472 TR |
1637 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_CONTROL) |
1638 | && (myops[i].X_add_number == OPERAND_CONTROL + 4 | |
1639 | || myops[i].X_add_number == OPERAND_CONTROL + 5 | |
1640 | || myops[i].X_add_number == OPERAND_CONTROL + 6 | |
1641 | || myops[i].X_add_number == OPERAND_CONTROL + 12 | |
1642 | || myops[i].X_add_number == OPERAND_CONTROL + 13 | |
1643 | || myops[i].X_add_number == OPERAND_CONTROL + 15)) | |
1644 | as_warn (_("cr%ld is a reserved control register"), | |
1645 | myops[i].X_add_number - OPERAND_CONTROL); | |
252b5132 RH |
1646 | } |
1647 | return opcode; | |
1648 | } | |
1649 | ||
e0c6ed95 AM |
1650 | /* If while processing a fixup, a reloc really needs to be created. |
1651 | Then it is done here. */ | |
1652 | ||
252b5132 RH |
1653 | arelent * |
1654 | tc_gen_reloc (seg, fixp) | |
bccba5f0 | 1655 | asection *seg ATTRIBUTE_UNUSED; |
252b5132 RH |
1656 | fixS *fixp; |
1657 | { | |
1658 | arelent *reloc; | |
1659 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
310b5aa2 ILT |
1660 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
1661 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
1662 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
1663 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
1664 | if (reloc->howto == (reloc_howto_type *) NULL) | |
1665 | { | |
1666 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
e0c6ed95 AM |
1667 | _("reloc %d not supported by object file format"), |
1668 | (int) fixp->fx_r_type); | |
252b5132 RH |
1669 | return NULL; |
1670 | } | |
1671 | ||
1672 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1673 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1674 | reloc->address = fixp->fx_offset; | |
cc8a6dd0 | 1675 | |
252b5132 | 1676 | reloc->addend = fixp->fx_addnumber; |
cc8a6dd0 | 1677 | |
252b5132 RH |
1678 | return reloc; |
1679 | } | |
1680 | ||
1681 | int | |
1682 | md_estimate_size_before_relax (fragp, seg) | |
bccba5f0 NC |
1683 | fragS *fragp ATTRIBUTE_UNUSED; |
1684 | asection *seg ATTRIBUTE_UNUSED; | |
252b5132 RH |
1685 | { |
1686 | abort (); | |
1687 | return 0; | |
e0c6ed95 | 1688 | } |
252b5132 RH |
1689 | |
1690 | long | |
1691 | md_pcrel_from_section (fixp, sec) | |
1692 | fixS *fixp; | |
1693 | segT sec; | |
1694 | { | |
e0c6ed95 AM |
1695 | if (fixp->fx_addsy != (symbolS *) NULL |
1696 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
1697 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
252b5132 RH |
1698 | return 0; |
1699 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1700 | } | |
1701 | ||
94f592af NC |
1702 | void |
1703 | md_apply_fix3 (fixP, valP, seg) | |
1704 | fixS *fixP; | |
1705 | valueT * valP; | |
bccba5f0 | 1706 | segT seg ATTRIBUTE_UNUSED; |
252b5132 RH |
1707 | { |
1708 | char *where; | |
1709 | unsigned long insn; | |
94f592af | 1710 | long value = * (long *) valP; |
252b5132 | 1711 | int op_type; |
e0c6ed95 | 1712 | int left = 0; |
252b5132 | 1713 | |
94f592af NC |
1714 | if (fixP->fx_addsy == (symbolS *) NULL) |
1715 | fixP->fx_done = 1; | |
1716 | ||
1717 | else if (fixP->fx_pcrel) | |
1718 | ; | |
1719 | ||
252b5132 RH |
1720 | else |
1721 | { | |
94f592af NC |
1722 | value = fixP->fx_offset; |
1723 | ||
1724 | if (fixP->fx_subsy != (symbolS *) NULL) | |
252b5132 | 1725 | { |
94f592af NC |
1726 | if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) |
1727 | value -= S_GET_VALUE (fixP->fx_subsy); | |
252b5132 RH |
1728 | else |
1729 | { | |
1730 | /* We don't actually support subtracting a symbol. */ | |
94f592af | 1731 | as_bad_where (fixP->fx_file, fixP->fx_line, |
252b5132 RH |
1732 | _("expression too complex")); |
1733 | } | |
1734 | } | |
1735 | } | |
1736 | ||
94f592af | 1737 | op_type = fixP->fx_r_type; |
252b5132 RH |
1738 | if (op_type & 2048) |
1739 | { | |
1740 | op_type -= 2048; | |
1741 | if (op_type & 1024) | |
1742 | { | |
1743 | op_type -= 1024; | |
94f592af | 1744 | fixP->fx_r_type = BFD_RELOC_D10V_10_PCREL_L; |
252b5132 RH |
1745 | left = 1; |
1746 | } | |
1747 | else if (op_type & 4096) | |
1748 | { | |
1749 | op_type -= 4096; | |
94f592af | 1750 | fixP->fx_r_type = BFD_RELOC_D10V_18; |
252b5132 RH |
1751 | } |
1752 | else | |
94f592af | 1753 | fixP->fx_r_type = |
e0c6ed95 | 1754 | get_reloc ((struct d10v_operand *) &d10v_operands[op_type]); |
252b5132 RH |
1755 | } |
1756 | ||
1757 | /* Fetch the instruction, insert the fully resolved operand | |
1758 | value, and stuff the instruction back again. */ | |
94f592af | 1759 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
1760 | insn = bfd_getb32 ((unsigned char *) where); |
1761 | ||
94f592af | 1762 | switch (fixP->fx_r_type) |
252b5132 RH |
1763 | { |
1764 | case BFD_RELOC_D10V_10_PCREL_L: | |
1765 | case BFD_RELOC_D10V_10_PCREL_R: | |
1766 | case BFD_RELOC_D10V_18_PCREL: | |
fbdbf472 TR |
1767 | /* If the fix is relative to a global symbol, not a section |
1768 | symbol, then ignore the offset. | |
1769 | XXX - Do we have to worry about branches to a symbol + offset ? */ | |
1770 | if (fixP->fx_addsy != NULL | |
1771 | && S_IS_EXTERN (fixP->fx_addsy) ) | |
cc8a6dd0 KH |
1772 | { |
1773 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); | |
1774 | segment_info_type *segf = seg_info(fseg); | |
fbdbf472 TR |
1775 | |
1776 | if ( segf && segf->sym != fixP->fx_addsy) | |
1777 | value = 0; | |
cc8a6dd0 | 1778 | } |
fbdbf472 | 1779 | /* Drop through. */ |
252b5132 | 1780 | case BFD_RELOC_D10V_18: |
e0c6ed95 | 1781 | /* Instruction addresses are always right-shifted by 2. */ |
252b5132 | 1782 | value >>= AT_WORD_RIGHT_SHIFT; |
94f592af | 1783 | if (fixP->fx_size == 2) |
252b5132 RH |
1784 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); |
1785 | else | |
1786 | { | |
1787 | struct d10v_opcode *rep, *repi; | |
1788 | ||
1789 | rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep"); | |
1790 | repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi"); | |
1791 | if ((insn & FM11) == FM11 | |
cc8a6dd0 | 1792 | && ((repi != NULL |
fbdbf472 | 1793 | && (insn & repi->mask) == (unsigned) repi->opcode) |
cc8a6dd0 | 1794 | || (rep != NULL |
fbdbf472 | 1795 | && (insn & rep->mask) == (unsigned) rep->opcode)) |
252b5132 RH |
1796 | && value < 4) |
1797 | as_fatal | |
1798 | (_("line %d: rep or repi must include at least 4 instructions"), | |
94f592af | 1799 | fixP->fx_line); |
e0c6ed95 | 1800 | insn = |
94f592af | 1801 | d10v_insert_operand (insn, op_type, (offsetT) value, left, fixP); |
e0c6ed95 | 1802 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); |
252b5132 RH |
1803 | } |
1804 | break; | |
1805 | case BFD_RELOC_32: | |
1806 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
1807 | break; | |
1808 | case BFD_RELOC_16: | |
1809 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1810 | break; | |
1811 | ||
1812 | case BFD_RELOC_VTABLE_INHERIT: | |
1813 | case BFD_RELOC_VTABLE_ENTRY: | |
94f592af NC |
1814 | fixP->fx_done = 0; |
1815 | return; | |
252b5132 RH |
1816 | |
1817 | default: | |
e0c6ed95 | 1818 | as_fatal (_("line %d: unknown relocation type: 0x%x"), |
94f592af | 1819 | fixP->fx_line, fixP->fx_r_type); |
252b5132 | 1820 | } |
252b5132 RH |
1821 | } |
1822 | ||
bccba5f0 NC |
1823 | /* d10v_cleanup() is called after the assembler has finished parsing |
1824 | the input file, when a label is read from the input file, or when a | |
1825 | stab directive is output. Because the D10V assembler sometimes | |
e0c6ed95 AM |
1826 | saves short instructions to see if it can package them with the |
1827 | next instruction, there may be a short instruction that still needs | |
1828 | to be written. | |
1829 | ||
0a44c2b1 DL |
1830 | NOTE: accesses a global, etype. |
1831 | NOTE: invoked by various macros such as md_cleanup: see. */ | |
e0c6ed95 | 1832 | |
252b5132 RH |
1833 | int |
1834 | d10v_cleanup () | |
1835 | { | |
1836 | segT seg; | |
1837 | subsegT subseg; | |
1838 | ||
bccba5f0 NC |
1839 | /* If cleanup was invoked because the assembler encountered, e.g., a |
1840 | user label, we write out the pending instruction, if any. If it | |
1841 | was invoked because the assembler is outputting a piece of line | |
1842 | debugging information, though, we write out the pending | |
1843 | instruction only if the --no-gstabs-packing command line switch | |
1844 | has been specified. */ | |
1845 | if (prev_opcode | |
1846 | && etype == PACK_UNSPEC | |
1847 | && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing)) | |
252b5132 RH |
1848 | { |
1849 | seg = now_seg; | |
1850 | subseg = now_subseg; | |
bccba5f0 | 1851 | |
252b5132 RH |
1852 | if (prev_seg) |
1853 | subseg_set (prev_seg, prev_subseg); | |
bccba5f0 | 1854 | |
252b5132 RH |
1855 | write_1_short (prev_opcode, prev_insn, fixups->next); |
1856 | subseg_set (seg, subseg); | |
1857 | prev_opcode = NULL; | |
1858 | } | |
1859 | return 1; | |
1860 | } | |
1861 | ||
fbdbf472 TR |
1862 | /* Like normal .word, except support @word. |
1863 | Clobbers input_line_pointer, checks end-of-line. */ | |
e0c6ed95 | 1864 | |
252b5132 | 1865 | static void |
bccba5f0 NC |
1866 | d10v_dot_word (dummy) |
1867 | int dummy ATTRIBUTE_UNUSED; | |
252b5132 RH |
1868 | { |
1869 | expressionS exp; | |
252b5132 | 1870 | char *p; |
252b5132 RH |
1871 | |
1872 | if (is_it_end_of_statement ()) | |
1873 | { | |
1874 | demand_empty_rest_of_line (); | |
1875 | return; | |
1876 | } | |
1877 | ||
1878 | do | |
1879 | { | |
1880 | expression (&exp); | |
1881 | if (!strncasecmp (input_line_pointer, "@word", 5)) | |
1882 | { | |
1883 | exp.X_add_number = 0; | |
1884 | input_line_pointer += 5; | |
e0c6ed95 | 1885 | |
252b5132 | 1886 | p = frag_more (2); |
e0c6ed95 | 1887 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, |
252b5132 RH |
1888 | &exp, 0, BFD_RELOC_D10V_18); |
1889 | } | |
1890 | else | |
1891 | emit_expr (&exp, 2); | |
1892 | } | |
1893 | while (*input_line_pointer++ == ','); | |
1894 | ||
e0c6ed95 | 1895 | input_line_pointer--; /* Put terminator back into stream. */ |
252b5132 RH |
1896 | demand_empty_rest_of_line (); |
1897 | } | |
1898 | ||
e0c6ed95 AM |
1899 | /* Mitsubishi asked that we support some old syntax that apparently |
1900 | had immediate operands starting with '#'. This is in some of their | |
1901 | sample code but is not documented (although it appears in some | |
1902 | examples in their assembler manual). For now, we'll solve this | |
1903 | compatibility problem by simply ignoring any '#' at the beginning | |
1904 | of an operand. */ | |
252b5132 | 1905 | |
fbdbf472 TR |
1906 | /* Operands that begin with '#' should fall through to here. |
1907 | From expr.c. */ | |
252b5132 | 1908 | |
e0c6ed95 | 1909 | void |
252b5132 RH |
1910 | md_operand (expressionP) |
1911 | expressionS *expressionP; | |
1912 | { | |
0f94f4c8 | 1913 | if (*input_line_pointer == '#' && ! do_not_ignore_hash) |
252b5132 RH |
1914 | { |
1915 | input_line_pointer++; | |
1916 | expression (expressionP); | |
1917 | } | |
1918 | } | |
1919 | ||
1920 | boolean | |
1921 | d10v_fix_adjustable (fixP) | |
e0c6ed95 | 1922 | fixS *fixP; |
252b5132 | 1923 | { |
252b5132 RH |
1924 | if (fixP->fx_addsy == NULL) |
1925 | return 1; | |
e0c6ed95 | 1926 | |
76b999d0 TR |
1927 | /* Prevent all adjustments to global and weak symbols or symbols in |
1928 | merge sections. */ | |
1929 | if ((S_IS_EXTERN (fixP->fx_addsy) | |
1930 | || (S_IS_WEAK (fixP->fx_addsy)) | |
1931 | || (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0)) | |
252b5132 RH |
1932 | return 0; |
1933 | ||
e0c6ed95 | 1934 | /* We need the symbol name for the VTABLE entries. */ |
252b5132 RH |
1935 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1936 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1937 | return 0; | |
1938 | ||
1939 | return 1; | |
1940 | } | |
1941 | ||
1942 | int | |
1943 | d10v_force_relocation (fixp) | |
e0c6ed95 | 1944 | fixS *fixp; |
252b5132 RH |
1945 | { |
1946 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1947 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1948 | return 1; | |
1949 | ||
1950 | return 0; | |
1951 | } |