Commit | Line | Data |
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252b5132 | 1 | /* tc-d10v.c -- Assembler code for the Mitsubishi D10V |
49309057 | 2 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | #include "opcode/d10v.h" | |
26 | #include "elf/ppc.h" | |
27 | ||
28 | const char comment_chars[] = ";"; | |
29 | const char line_comment_chars[] = "#"; | |
30 | const char line_separator_chars[] = ""; | |
31 | const char *md_shortopts = "O"; | |
32 | const char EXP_CHARS[] = "eE"; | |
33 | const char FLT_CHARS[] = "dD"; | |
34 | ||
35 | int Optimizing = 0; | |
36 | ||
37 | #define AT_WORD_P(X) ((X)->X_op == O_right_shift \ | |
38 | && (X)->X_op_symbol != NULL \ | |
39 | && (X)->X_op_symbol->sy_value.X_op == O_constant \ | |
40 | && (X)->X_op_symbol->sy_value.X_add_number == AT_WORD_RIGHT_SHIFT) | |
41 | #define AT_WORD_RIGHT_SHIFT 2 | |
42 | ||
43 | ||
44 | /* fixups */ | |
45 | #define MAX_INSN_FIXUPS (5) | |
46 | struct d10v_fixup | |
47 | { | |
48 | expressionS exp; | |
49 | int operand; | |
50 | int pcrel; | |
51 | int size; | |
52 | bfd_reloc_code_real_type reloc; | |
53 | }; | |
54 | ||
55 | typedef struct _fixups | |
56 | { | |
57 | int fc; | |
58 | struct d10v_fixup fix[MAX_INSN_FIXUPS]; | |
59 | struct _fixups *next; | |
60 | } Fixups; | |
61 | ||
62 | static Fixups FixUps[2]; | |
63 | static Fixups *fixups; | |
64 | ||
0f94f4c8 NC |
65 | static int do_not_ignore_hash = 0; |
66 | ||
252b5132 RH |
67 | /* True if instruction swapping warnings should be inhibited. */ |
68 | static unsigned char flag_warn_suppress_instructionswap; /* --nowarnswap */ | |
69 | ||
70 | /* local functions */ | |
71 | static int reg_name_search PARAMS ((char *name)); | |
72 | static int register_name PARAMS ((expressionS *expressionP)); | |
73 | static int check_range PARAMS ((unsigned long num, int bits, int flags)); | |
74 | static int postfix PARAMS ((char *p)); | |
75 | static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op)); | |
76 | static int get_operands PARAMS ((expressionS exp[])); | |
77 | static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[])); | |
78 | static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn)); | |
79 | static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); | |
80 | static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); | |
81 | static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, | |
82 | struct d10v_opcode *opcode2, unsigned long insn2, int exec_type, Fixups *fx)); | |
83 | static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode)); | |
84 | static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type, | |
85 | offsetT value, int left, fixS *fix)); | |
86 | static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, | |
87 | struct d10v_opcode *opcode2, unsigned long insn2, | |
88 | int exec_type)); | |
89 | static symbolS * find_symbol_matching_register PARAMS ((expressionS *)); | |
90 | ||
91 | struct option md_longopts[] = | |
92 | { | |
93 | #define OPTION_NOWARNSWAP (OPTION_MD_BASE) | |
94 | {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP}, | |
95 | {NULL, no_argument, NULL, 0} | |
96 | }; | |
97 | size_t md_longopts_size = sizeof(md_longopts); | |
98 | ||
99 | static void d10v_dot_word PARAMS ((int)); | |
100 | ||
101 | /* The target specific pseudo-ops which we support. */ | |
102 | const pseudo_typeS md_pseudo_table[] = | |
103 | { | |
104 | { "word", d10v_dot_word, 2 }, | |
105 | { NULL, NULL, 0 } | |
106 | }; | |
107 | ||
108 | /* Opcode hash table. */ | |
109 | static struct hash_control *d10v_hash; | |
110 | ||
111 | /* reg_name_search does a binary search of the d10v_predefined_registers | |
112 | array to see if "name" is a valid regiter name. Returns the register | |
113 | number from the array on success, or -1 on failure. */ | |
114 | ||
115 | static int | |
116 | reg_name_search (name) | |
117 | char *name; | |
118 | { | |
119 | int middle, low, high; | |
120 | int cmp; | |
121 | ||
122 | low = 0; | |
123 | high = d10v_reg_name_cnt() - 1; | |
124 | ||
125 | do | |
126 | { | |
127 | middle = (low + high) / 2; | |
128 | cmp = strcasecmp (name, d10v_predefined_registers[middle].name); | |
129 | if (cmp < 0) | |
130 | high = middle - 1; | |
131 | else if (cmp > 0) | |
132 | low = middle + 1; | |
133 | else | |
134 | return d10v_predefined_registers[middle].value; | |
135 | } | |
136 | while (low <= high); | |
137 | return -1; | |
138 | } | |
139 | ||
140 | /* register_name() checks the string at input_line_pointer | |
141 | to see if it is a valid register name */ | |
142 | ||
143 | static int | |
144 | register_name (expressionP) | |
145 | expressionS *expressionP; | |
146 | { | |
147 | int reg_number; | |
148 | char c, *p = input_line_pointer; | |
149 | ||
150 | while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')') | |
151 | p++; | |
152 | ||
153 | c = *p; | |
154 | if (c) | |
155 | *p++ = 0; | |
156 | ||
157 | /* look to see if it's in the register table */ | |
158 | reg_number = reg_name_search (input_line_pointer); | |
159 | if (reg_number >= 0) | |
160 | { | |
161 | expressionP->X_op = O_register; | |
162 | /* temporarily store a pointer to the string here */ | |
49309057 | 163 | expressionP->X_op_symbol = (symbolS *)input_line_pointer; |
252b5132 RH |
164 | expressionP->X_add_number = reg_number; |
165 | input_line_pointer = p; | |
166 | return 1; | |
167 | } | |
168 | if (c) | |
169 | *(p-1) = c; | |
170 | return 0; | |
171 | } | |
172 | ||
173 | ||
174 | static int | |
175 | check_range (num, bits, flags) | |
176 | unsigned long num; | |
177 | int bits; | |
178 | int flags; | |
179 | { | |
180 | long min, max, bit1; | |
181 | int retval=0; | |
182 | ||
183 | /* don't bother checking 16-bit values */ | |
184 | if (bits == 16) | |
185 | return 0; | |
186 | ||
187 | if (flags & OPERAND_SHIFT) | |
188 | { | |
189 | /* all special shift operands are unsigned */ | |
190 | /* and <= 16. We allow 0 for now. */ | |
191 | if (num>16) | |
192 | return 1; | |
193 | else | |
194 | return 0; | |
195 | } | |
196 | ||
197 | if (flags & OPERAND_SIGNED) | |
198 | { | |
199 | max = (1 << (bits - 1))-1; | |
200 | min = - (1 << (bits - 1)); | |
201 | if (((long)num > max) || ((long)num < min)) | |
202 | retval = 1; | |
203 | } | |
204 | else | |
205 | { | |
206 | max = (1 << bits) - 1; | |
207 | min = 0; | |
208 | if ((num > max) || (num < min)) | |
209 | retval = 1; | |
210 | } | |
211 | return retval; | |
212 | } | |
213 | ||
214 | ||
215 | void | |
216 | md_show_usage (stream) | |
217 | FILE *stream; | |
218 | { | |
219 | fprintf(stream, _("D10V options:\n\ | |
220 | -O optimize. Will do some operations in parallel.\n")); | |
221 | } | |
222 | ||
223 | int | |
224 | md_parse_option (c, arg) | |
225 | int c; | |
226 | char *arg; | |
227 | { | |
228 | switch (c) | |
229 | { | |
230 | case 'O': | |
231 | /* Optimize. Will attempt to parallelize operations */ | |
232 | Optimizing = 1; | |
233 | break; | |
234 | case OPTION_NOWARNSWAP: | |
235 | flag_warn_suppress_instructionswap = 1; | |
236 | break; | |
237 | default: | |
238 | return 0; | |
239 | } | |
240 | return 1; | |
241 | } | |
242 | ||
243 | symbolS * | |
244 | md_undefined_symbol (name) | |
245 | char *name; | |
246 | { | |
247 | return 0; | |
248 | } | |
249 | ||
250 | /* Turn a string in input_line_pointer into a floating point constant of type | |
251 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
252 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
253 | */ | |
254 | char * | |
255 | md_atof (type, litP, sizeP) | |
256 | int type; | |
257 | char *litP; | |
258 | int *sizeP; | |
259 | { | |
260 | int prec; | |
261 | LITTLENUM_TYPE words[4]; | |
262 | char *t; | |
263 | int i; | |
264 | ||
265 | switch (type) | |
266 | { | |
267 | case 'f': | |
268 | prec = 2; | |
269 | break; | |
270 | case 'd': | |
271 | prec = 4; | |
272 | break; | |
273 | default: | |
274 | *sizeP = 0; | |
275 | return _("bad call to md_atof"); | |
276 | } | |
277 | ||
278 | t = atof_ieee (input_line_pointer, type, words); | |
279 | if (t) | |
280 | input_line_pointer = t; | |
281 | ||
282 | *sizeP = prec * 2; | |
283 | ||
284 | for (i = 0; i < prec; i++) | |
285 | { | |
286 | md_number_to_chars (litP, (valueT) words[i], 2); | |
287 | litP += 2; | |
288 | } | |
289 | return NULL; | |
290 | } | |
291 | ||
292 | void | |
293 | md_convert_frag (abfd, sec, fragP) | |
294 | bfd *abfd; | |
295 | asection *sec; | |
296 | fragS *fragP; | |
297 | { | |
298 | abort (); | |
299 | } | |
300 | ||
301 | valueT | |
302 | md_section_align (seg, addr) | |
303 | asection *seg; | |
304 | valueT addr; | |
305 | { | |
306 | int align = bfd_get_section_alignment (stdoutput, seg); | |
307 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
308 | } | |
309 | ||
310 | ||
311 | void | |
312 | md_begin () | |
313 | { | |
314 | char *prev_name = ""; | |
315 | struct d10v_opcode *opcode; | |
316 | d10v_hash = hash_new(); | |
317 | ||
318 | /* Insert unique names into hash table. The D10v instruction set | |
319 | has many identical opcode names that have different opcodes based | |
320 | on the operands. This hash table then provides a quick index to | |
321 | the first opcode with a particular name in the opcode table. */ | |
322 | ||
323 | for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++) | |
324 | { | |
325 | if (strcmp (prev_name, opcode->name)) | |
326 | { | |
327 | prev_name = (char *)opcode->name; | |
328 | hash_insert (d10v_hash, opcode->name, (char *) opcode); | |
329 | } | |
330 | } | |
331 | ||
332 | fixups = &FixUps[0]; | |
333 | FixUps[0].next = &FixUps[1]; | |
334 | FixUps[1].next = &FixUps[0]; | |
335 | } | |
336 | ||
337 | ||
338 | /* this function removes the postincrement or postdecrement | |
339 | operator ( '+' or '-' ) from an expression */ | |
340 | ||
341 | static int postfix (p) | |
342 | char *p; | |
343 | { | |
344 | while (*p != '-' && *p != '+') | |
345 | { | |
346 | if (*p==0 || *p=='\n' || *p=='\r') | |
347 | break; | |
348 | p++; | |
349 | } | |
350 | ||
351 | if (*p == '-') | |
352 | { | |
353 | *p = ' '; | |
354 | return (-1); | |
355 | } | |
356 | if (*p == '+') | |
357 | { | |
358 | *p = ' '; | |
359 | return (1); | |
360 | } | |
361 | ||
362 | return (0); | |
363 | } | |
364 | ||
365 | ||
366 | static bfd_reloc_code_real_type | |
367 | get_reloc (op) | |
368 | struct d10v_operand *op; | |
369 | { | |
370 | int bits = op->bits; | |
371 | ||
372 | if (bits <= 4) | |
373 | return (0); | |
374 | ||
375 | if (op->flags & OPERAND_ADDR) | |
376 | { | |
377 | if (bits == 8) | |
378 | return (BFD_RELOC_D10V_10_PCREL_R); | |
379 | else | |
380 | return (BFD_RELOC_D10V_18_PCREL); | |
381 | } | |
382 | ||
383 | return (BFD_RELOC_16); | |
384 | } | |
385 | ||
386 | ||
387 | /* get_operands parses a string of operands and returns | |
388 | an array of expressions */ | |
389 | ||
390 | static int | |
391 | get_operands (exp) | |
392 | expressionS exp[]; | |
393 | { | |
394 | char *p = input_line_pointer; | |
395 | int numops = 0; | |
396 | int post = 0; | |
0f94f4c8 NC |
397 | int uses_at = 0; |
398 | ||
252b5132 RH |
399 | while (*p) |
400 | { | |
401 | while (*p == ' ' || *p == '\t' || *p == ',') | |
402 | p++; | |
403 | if (*p==0 || *p=='\n' || *p=='\r') | |
404 | break; | |
405 | ||
406 | if (*p == '@') | |
407 | { | |
0f94f4c8 NC |
408 | uses_at = 1; |
409 | ||
252b5132 RH |
410 | p++; |
411 | exp[numops].X_op = O_absent; | |
412 | if (*p == '(') | |
413 | { | |
414 | p++; | |
415 | exp[numops].X_add_number = OPERAND_ATPAR; | |
416 | } | |
417 | else if (*p == '-') | |
418 | { | |
419 | p++; | |
420 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
421 | } | |
422 | else | |
423 | { | |
424 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
425 | post = postfix (p); | |
426 | } | |
427 | numops++; | |
428 | continue; | |
429 | } | |
430 | ||
431 | if (*p == ')') | |
432 | { | |
433 | /* just skip the trailing paren */ | |
434 | p++; | |
435 | continue; | |
436 | } | |
437 | ||
438 | input_line_pointer = p; | |
439 | ||
440 | /* check to see if it might be a register name */ | |
441 | if (!register_name (&exp[numops])) | |
442 | { | |
443 | /* parse as an expression */ | |
0f94f4c8 NC |
444 | if (uses_at) |
445 | { | |
446 | /* Any expression that involves the indirect addressing | |
447 | cannot also involve immediate addressing. Therefore | |
448 | the use of the hash character is illegal. */ | |
449 | int save = do_not_ignore_hash; | |
450 | do_not_ignore_hash = 1; | |
451 | ||
452 | expression (&exp[numops]); | |
453 | ||
454 | do_not_ignore_hash = save; | |
455 | } | |
456 | else | |
457 | expression (&exp[numops]); | |
252b5132 RH |
458 | } |
459 | ||
460 | if (strncasecmp (input_line_pointer, "@word", 5) == 0) | |
461 | { | |
462 | input_line_pointer += 5; | |
463 | if (exp[numops].X_op == O_register) | |
464 | { | |
465 | /* if it looked like a register name but was followed by | |
466 | "@word" then it was really a symbol, so change it to | |
467 | one */ | |
468 | exp[numops].X_op = O_symbol; | |
469 | exp[numops].X_add_symbol = symbol_find_or_make ((char *)exp[numops].X_op_symbol); | |
470 | } | |
471 | ||
472 | /* check for identifier@word+constant */ | |
473 | if (*input_line_pointer == '-' || *input_line_pointer == '+') | |
474 | { | |
475 | char *orig_line = input_line_pointer; | |
476 | expressionS new_exp; | |
477 | expression (&new_exp); | |
478 | exp[numops].X_add_number = new_exp.X_add_number; | |
479 | } | |
480 | ||
481 | /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */ | |
482 | { | |
483 | expressionS new_exp; | |
484 | memset (&new_exp, 0, sizeof new_exp); | |
485 | new_exp.X_add_number = AT_WORD_RIGHT_SHIFT; | |
486 | new_exp.X_op = O_constant; | |
487 | new_exp.X_unsigned = 1; | |
488 | exp[numops].X_op_symbol = make_expr_symbol (&new_exp); | |
489 | exp[numops].X_op = O_right_shift; | |
490 | } | |
491 | ||
492 | know (AT_WORD_P (&exp[numops])); | |
493 | } | |
494 | ||
495 | if (exp[numops].X_op == O_illegal) | |
496 | as_bad (_("illegal operand")); | |
497 | else if (exp[numops].X_op == O_absent) | |
498 | as_bad (_("missing operand")); | |
499 | ||
500 | numops++; | |
501 | p = input_line_pointer; | |
502 | } | |
503 | ||
504 | switch (post) | |
505 | { | |
506 | case -1: /* postdecrement mode */ | |
507 | exp[numops].X_op = O_absent; | |
508 | exp[numops++].X_add_number = OPERAND_MINUS; | |
509 | break; | |
510 | case 1: /* postincrement mode */ | |
511 | exp[numops].X_op = O_absent; | |
512 | exp[numops++].X_add_number = OPERAND_PLUS; | |
513 | break; | |
514 | } | |
515 | ||
516 | exp[numops].X_op = 0; | |
517 | return (numops); | |
518 | } | |
519 | ||
520 | static unsigned long | |
521 | d10v_insert_operand (insn, op_type, value, left, fix) | |
522 | unsigned long insn; | |
523 | int op_type; | |
524 | offsetT value; | |
525 | int left; | |
526 | fixS *fix; | |
527 | { | |
528 | int shift, bits; | |
529 | ||
530 | shift = d10v_operands[op_type].shift; | |
531 | if (left) | |
532 | shift += 15; | |
533 | ||
534 | bits = d10v_operands[op_type].bits; | |
535 | ||
536 | /* truncate to the proper number of bits */ | |
537 | if (check_range (value, bits, d10v_operands[op_type].flags)) | |
538 | as_bad_where (fix->fx_file, fix->fx_line, _("operand out of range: %d"), value); | |
539 | ||
540 | value &= 0x7FFFFFFF >> (31 - bits); | |
541 | insn |= (value << shift); | |
542 | ||
543 | return insn; | |
544 | } | |
545 | ||
546 | ||
547 | /* build_insn takes a pointer to the opcode entry in the opcode table | |
548 | and the array of operand expressions and returns the instruction */ | |
549 | ||
550 | static unsigned long | |
551 | build_insn (opcode, opers, insn) | |
552 | struct d10v_opcode *opcode; | |
553 | expressionS *opers; | |
554 | unsigned long insn; | |
555 | { | |
556 | int i, bits, shift, flags, format; | |
557 | unsigned long number; | |
558 | ||
559 | /* the insn argument is only used for the DIVS kludge */ | |
560 | if (insn) | |
561 | format = LONG_R; | |
562 | else | |
563 | { | |
564 | insn = opcode->opcode; | |
565 | format = opcode->format; | |
566 | } | |
567 | ||
568 | for (i=0;opcode->operands[i];i++) | |
569 | { | |
570 | flags = d10v_operands[opcode->operands[i]].flags; | |
571 | bits = d10v_operands[opcode->operands[i]].bits; | |
572 | shift = d10v_operands[opcode->operands[i]].shift; | |
573 | number = opers[i].X_add_number; | |
574 | ||
575 | if (flags & OPERAND_REG) | |
576 | { | |
577 | number &= REGISTER_MASK; | |
578 | if (format == LONG_L) | |
579 | shift += 15; | |
580 | } | |
581 | ||
582 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant) | |
583 | { | |
584 | /* now create a fixup */ | |
585 | ||
586 | if (fixups->fc >= MAX_INSN_FIXUPS) | |
587 | as_fatal (_("too many fixups")); | |
588 | ||
589 | if (AT_WORD_P (&opers[i])) | |
590 | { | |
591 | /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */ | |
592 | fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18; | |
593 | opers[i].X_op = O_symbol; | |
594 | opers[i].X_op_symbol = NULL; /* Should free it */ | |
595 | /* number is left shifted by AT_WORD_RIGHT_SHIFT so | |
596 | that, it is aligned with the symbol's value. Later, | |
597 | BFD_RELOC_D10V_18 will right shift (symbol_value + | |
598 | X_add_number). */ | |
599 | number <<= AT_WORD_RIGHT_SHIFT; | |
600 | opers[i].X_add_number = number; | |
601 | } | |
602 | else | |
603 | fixups->fix[fixups->fc].reloc = | |
604 | get_reloc((struct d10v_operand *)&d10v_operands[opcode->operands[i]]); | |
605 | ||
606 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 || | |
607 | fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18) | |
608 | fixups->fix[fixups->fc].size = 2; | |
609 | else | |
610 | fixups->fix[fixups->fc].size = 4; | |
611 | ||
612 | fixups->fix[fixups->fc].exp = opers[i]; | |
613 | fixups->fix[fixups->fc].operand = opcode->operands[i]; | |
614 | fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) ? true : false; | |
615 | (fixups->fc)++; | |
616 | } | |
617 | ||
618 | /* truncate to the proper number of bits */ | |
619 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) | |
620 | as_bad (_("operand out of range: %d"),number); | |
621 | number &= 0x7FFFFFFF >> (31 - bits); | |
622 | insn = insn | (number << shift); | |
623 | } | |
624 | ||
625 | /* kludge: for DIVS, we need to put the operands in twice */ | |
626 | /* on the second pass, format is changed to LONG_R to force */ | |
627 | /* the second set of operands to not be shifted over 15 */ | |
628 | if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L)) | |
629 | insn = build_insn (opcode, opers, insn); | |
630 | ||
631 | return insn; | |
632 | } | |
633 | ||
634 | /* write out a long form instruction */ | |
635 | static void | |
636 | write_long (opcode, insn, fx) | |
637 | struct d10v_opcode *opcode; | |
638 | unsigned long insn; | |
639 | Fixups *fx; | |
640 | { | |
641 | int i, where; | |
642 | char *f = frag_more(4); | |
643 | ||
644 | insn |= FM11; | |
645 | number_to_chars_bigendian (f, insn, 4); | |
646 | ||
647 | for (i=0; i < fx->fc; i++) | |
648 | { | |
649 | if (fx->fix[i].reloc) | |
650 | { | |
651 | where = f - frag_now->fr_literal; | |
652 | if (fx->fix[i].size == 2) | |
653 | where += 2; | |
654 | ||
655 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
656 | fx->fix[i].operand |= 4096; | |
657 | ||
658 | fix_new_exp (frag_now, | |
659 | where, | |
660 | fx->fix[i].size, | |
661 | &(fx->fix[i].exp), | |
662 | fx->fix[i].pcrel, | |
663 | fx->fix[i].operand|2048); | |
664 | } | |
665 | } | |
666 | fx->fc = 0; | |
667 | } | |
668 | ||
669 | ||
670 | /* write out a short form instruction by itself */ | |
671 | static void | |
672 | write_1_short (opcode, insn, fx) | |
673 | struct d10v_opcode *opcode; | |
674 | unsigned long insn; | |
675 | Fixups *fx; | |
676 | { | |
677 | char *f = frag_more(4); | |
678 | int i, where; | |
679 | ||
680 | if (opcode->exec_type & PARONLY) | |
681 | as_fatal (_("Instruction must be executed in parallel with another instruction.")); | |
682 | ||
683 | /* the other container needs to be NOP */ | |
684 | /* according to 4.3.1: for FM=00, sub-instructions performed only | |
685 | by IU cannot be encoded in L-container. */ | |
686 | if (opcode->unit == IU) | |
687 | insn |= FM00 | (NOP << 15); /* right container */ | |
688 | else | |
689 | insn = FM00 | (insn << 15) | NOP; /* left container */ | |
690 | ||
691 | number_to_chars_bigendian (f, insn, 4); | |
692 | for (i=0; i < fx->fc; i++) | |
693 | { | |
694 | if (fx->fix[i].reloc) | |
695 | { | |
696 | where = f - frag_now->fr_literal; | |
697 | if (fx->fix[i].size == 2) | |
698 | where += 2; | |
699 | ||
700 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
701 | fx->fix[i].operand |= 4096; | |
702 | ||
703 | /* if it's an R reloc, we may have to switch it to L */ | |
704 | if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) ) | |
705 | fx->fix[i].operand |= 1024; | |
706 | ||
707 | fix_new_exp (frag_now, | |
708 | where, | |
709 | fx->fix[i].size, | |
710 | &(fx->fix[i].exp), | |
711 | fx->fix[i].pcrel, | |
712 | fx->fix[i].operand|2048); | |
713 | } | |
714 | } | |
715 | fx->fc = 0; | |
716 | } | |
717 | ||
718 | /* write out a short form instruction if possible */ | |
719 | /* return number of instructions not written out */ | |
720 | static int | |
721 | write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) | |
722 | struct d10v_opcode *opcode1, *opcode2; | |
723 | unsigned long insn1, insn2; | |
724 | int exec_type; | |
725 | Fixups *fx; | |
726 | { | |
727 | unsigned long insn; | |
728 | char *f; | |
729 | int i,j, where; | |
730 | ||
731 | if ( (exec_type != 1) && ((opcode1->exec_type & PARONLY) | |
732 | || (opcode2->exec_type & PARONLY))) | |
733 | as_fatal (_("Instruction must be executed in parallel")); | |
734 | ||
735 | if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE)) | |
736 | as_fatal (_("Long instructions may not be combined.")); | |
737 | ||
738 | if(opcode1->exec_type & BRANCH_LINK && exec_type == 0) | |
739 | { | |
740 | /* Instructions paired with a subroutine call are executed before the | |
741 | subroutine, so don't do these pairings unless explicitly requested. */ | |
742 | write_1_short (opcode1, insn1, fx->next); | |
743 | return (1); | |
744 | } | |
745 | ||
746 | switch (exec_type) | |
747 | { | |
748 | case 0: /* order not specified */ | |
749 | if ( Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
750 | { | |
751 | /* parallel */ | |
752 | if (opcode1->unit == IU) | |
753 | insn = FM00 | (insn2 << 15) | insn1; | |
754 | else if (opcode2->unit == MU) | |
755 | insn = FM00 | (insn2 << 15) | insn1; | |
756 | else | |
757 | { | |
758 | insn = FM00 | (insn1 << 15) | insn2; | |
759 | fx = fx->next; | |
760 | } | |
761 | } | |
762 | else if (opcode1->unit == IU) | |
763 | { | |
764 | /* reverse sequential */ | |
765 | insn = FM10 | (insn2 << 15) | insn1; | |
766 | } | |
767 | else | |
768 | { | |
769 | /* sequential */ | |
770 | insn = FM01 | (insn1 << 15) | insn2; | |
771 | fx = fx->next; | |
772 | } | |
773 | break; | |
774 | case 1: /* parallel */ | |
775 | if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ) | |
776 | as_fatal (_("One of these instructions may not be executed in parallel.")); | |
777 | ||
778 | if (opcode1->unit == IU) | |
779 | { | |
780 | if (opcode2->unit == IU) | |
781 | as_fatal (_("Two IU instructions may not be executed in parallel")); | |
782 | if (!flag_warn_suppress_instructionswap) | |
783 | as_warn (_("Swapping instruction order")); | |
784 | insn = FM00 | (insn2 << 15) | insn1; | |
785 | } | |
786 | else if (opcode2->unit == MU) | |
787 | { | |
788 | if (opcode1->unit == MU) | |
789 | as_fatal (_("Two MU instructions may not be executed in parallel")); | |
790 | if (!flag_warn_suppress_instructionswap) | |
791 | as_warn (_("Swapping instruction order")); | |
792 | insn = FM00 | (insn2 << 15) | insn1; | |
793 | } | |
794 | else | |
795 | { | |
796 | insn = FM00 | (insn1 << 15) | insn2; | |
797 | fx = fx->next; | |
798 | } | |
799 | break; | |
800 | case 2: /* sequential */ | |
801 | if (opcode1->unit != IU) | |
802 | insn = FM01 | (insn1 << 15) | insn2; | |
803 | else if (opcode2->unit == MU || opcode2->unit == EITHER) | |
804 | { | |
805 | if (!flag_warn_suppress_instructionswap) | |
806 | as_warn (_("Swapping instruction order")); | |
807 | insn = FM10 | (insn2 << 15) | insn1; | |
808 | } | |
809 | else | |
810 | as_fatal (_("IU instruction may not be in the left container")); | |
811 | fx = fx->next; | |
812 | break; | |
813 | case 3: /* reverse sequential */ | |
814 | if (opcode2->unit != MU) | |
815 | insn = FM10 | (insn1 << 15) | insn2; | |
816 | else if (opcode1->unit == IU || opcode1->unit == EITHER) | |
817 | { | |
818 | if (!flag_warn_suppress_instructionswap) | |
819 | as_warn (_("Swapping instruction order")); | |
820 | insn = FM01 | (insn2 << 15) | insn1; | |
821 | } | |
822 | else | |
823 | as_fatal (_("MU instruction may not be in the right container")); | |
824 | fx = fx->next; | |
825 | break; | |
826 | default: | |
827 | as_fatal (_("unknown execution type passed to write_2_short()")); | |
828 | } | |
829 | ||
830 | f = frag_more(4); | |
831 | number_to_chars_bigendian (f, insn, 4); | |
832 | ||
833 | for (j=0; j<2; j++) | |
834 | { | |
835 | for (i=0; i < fx->fc; i++) | |
836 | { | |
837 | if (fx->fix[i].reloc) | |
838 | { | |
839 | where = f - frag_now->fr_literal; | |
840 | if (fx->fix[i].size == 2) | |
841 | where += 2; | |
842 | ||
843 | if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) ) | |
844 | fx->fix[i].operand |= 1024; | |
845 | ||
846 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
847 | fx->fix[i].operand |= 4096; | |
848 | ||
849 | fix_new_exp (frag_now, | |
850 | where, | |
851 | fx->fix[i].size, | |
852 | &(fx->fix[i].exp), | |
853 | fx->fix[i].pcrel, | |
854 | fx->fix[i].operand|2048); | |
855 | } | |
856 | } | |
857 | fx->fc = 0; | |
858 | fx = fx->next; | |
859 | } | |
860 | return (0); | |
861 | } | |
862 | ||
863 | ||
864 | /* Check 2 instructions and determine if they can be safely */ | |
865 | /* executed in parallel. Returns 1 if they can be. */ | |
866 | static int | |
867 | parallel_ok (op1, insn1, op2, insn2, exec_type) | |
868 | struct d10v_opcode *op1, *op2; | |
869 | unsigned long insn1, insn2; | |
870 | int exec_type; | |
871 | { | |
872 | int i, j, flags, mask, shift, regno; | |
873 | unsigned long ins, mod[2], used[2]; | |
874 | struct d10v_opcode *op; | |
875 | ||
876 | if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0 | |
877 | || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0 | |
878 | || (op1->unit == BOTH) || (op2->unit == BOTH) | |
879 | || (op1->unit == IU && op2->unit == IU) | |
880 | || (op1->unit == MU && op2->unit == MU)) | |
881 | return 0; | |
882 | ||
883 | /* If the first instruction is a branch and this is auto parallazation, | |
884 | don't combine with any second instruction. */ | |
885 | if (exec_type == 0 && (op1->exec_type & BRANCH) != 0) | |
886 | return 0; | |
887 | ||
888 | /* The idea here is to create two sets of bitmasks (mod and used) | |
889 | which indicate which registers are modified or used by each | |
890 | instruction. The operation can only be done in parallel if | |
891 | instruction 1 and instruction 2 modify different registers, and | |
892 | the first instruction does not modify registers that the second | |
893 | is using (The second instruction can modify registers that the | |
894 | first is using as they are only written back after the first | |
895 | instruction has completed). Accesses to control registers, PSW, | |
896 | and memory are treated as accesses to a single register. So if | |
897 | both instructions write memory or if the first instruction writes | |
898 | memory and the second reads, then they cannot be done in | |
899 | parallel. Likewise, if the first instruction mucks with the psw | |
900 | and the second reads the PSW (which includes C, F0, and F1), then | |
901 | they cannot operate safely in parallel. */ | |
902 | ||
903 | /* the bitmasks (mod and used) look like this (bit 31 = MSB) */ | |
904 | /* r0-r15 0-15 */ | |
905 | /* a0-a1 16-17 */ | |
906 | /* cr (not psw) 18 */ | |
907 | /* psw 19 */ | |
908 | /* mem 20 */ | |
909 | ||
910 | for (j=0;j<2;j++) | |
911 | { | |
912 | if (j == 0) | |
913 | { | |
914 | op = op1; | |
915 | ins = insn1; | |
916 | } | |
917 | else | |
918 | { | |
919 | op = op2; | |
920 | ins = insn2; | |
921 | } | |
922 | mod[j] = used[j] = 0; | |
923 | if (op->exec_type & BRANCH_LINK) | |
924 | mod[j] |= 1 << 13; | |
925 | ||
926 | for (i = 0; op->operands[i]; i++) | |
927 | { | |
928 | flags = d10v_operands[op->operands[i]].flags; | |
929 | shift = d10v_operands[op->operands[i]].shift; | |
930 | mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); | |
931 | if (flags & OPERAND_REG) | |
932 | { | |
933 | regno = (ins >> shift) & mask; | |
934 | if (flags & (OPERAND_ACC0|OPERAND_ACC1)) | |
935 | regno += 16; | |
936 | else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */ | |
937 | { | |
938 | if (regno == 0) | |
939 | regno = 19; | |
940 | else | |
941 | regno = 18; | |
942 | } | |
943 | else if (flags & (OPERAND_FFLAG|OPERAND_CFLAG)) | |
944 | regno = 19; | |
945 | ||
946 | if ( flags & OPERAND_DEST ) | |
947 | { | |
948 | mod[j] |= 1 << regno; | |
949 | if (flags & OPERAND_EVEN) | |
950 | mod[j] |= 1 << (regno + 1); | |
951 | } | |
952 | else | |
953 | { | |
954 | used[j] |= 1 << regno ; | |
955 | if (flags & OPERAND_EVEN) | |
956 | used[j] |= 1 << (regno + 1); | |
957 | ||
958 | /* Auto inc/dec also modifies the register. */ | |
959 | if (op->operands[i+1] != 0 | |
960 | && (d10v_operands[op->operands[i+1]].flags | |
961 | & (OPERAND_PLUS | OPERAND_MINUS)) != 0) | |
962 | mod[j] |= 1 << regno; | |
963 | } | |
964 | } | |
965 | else if (flags & OPERAND_ATMINUS) | |
966 | { | |
967 | /* SP implicitly used/modified */ | |
968 | mod[j] |= 1 << 15; | |
969 | used[j] |= 1 << 15; | |
970 | } | |
971 | } | |
972 | if (op->exec_type & RMEM) | |
973 | used[j] |= 1 << 20; | |
974 | else if (op->exec_type & WMEM) | |
975 | mod[j] |= 1 << 20; | |
976 | else if (op->exec_type & RF0) | |
977 | used[j] |= 1 << 19; | |
978 | else if (op->exec_type & WF0) | |
979 | mod[j] |= 1 << 19; | |
980 | else if (op->exec_type & WCAR) | |
981 | mod[j] |= 1 << 19; | |
982 | } | |
983 | if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0) | |
984 | return 1; | |
985 | return 0; | |
986 | } | |
987 | ||
988 | ||
989 | /* This is the main entry point for the machine-dependent assembler. str points to a | |
990 | machine-dependent instruction. This function is supposed to emit the frags/bytes | |
991 | it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing | |
992 | and leaves the difficult stuff to do_assemble(). | |
993 | */ | |
994 | ||
995 | static unsigned long prev_insn; | |
996 | static struct d10v_opcode *prev_opcode = 0; | |
997 | static subsegT prev_subseg; | |
998 | static segT prev_seg = 0;; | |
999 | static int etype = 0; /* saved extype. used for multiline instructions */ | |
1000 | ||
1001 | void | |
1002 | md_assemble (str) | |
1003 | char *str; | |
1004 | { | |
1005 | struct d10v_opcode * opcode; | |
1006 | unsigned long insn; | |
1007 | int extype = 0; /* execution type; parallel, etc */ | |
1008 | char * str2; | |
1009 | ||
1010 | if (etype == 0) | |
1011 | { | |
1012 | /* look for the special multiple instruction separators */ | |
1013 | str2 = strstr (str, "||"); | |
1014 | if (str2) | |
1015 | extype = 1; | |
1016 | else | |
1017 | { | |
1018 | str2 = strstr (str, "->"); | |
1019 | if (str2) | |
1020 | extype = 2; | |
1021 | else | |
1022 | { | |
1023 | str2 = strstr (str, "<-"); | |
1024 | if (str2) | |
1025 | extype = 3; | |
1026 | } | |
1027 | } | |
1028 | /* str2 points to the separator, if one */ | |
1029 | if (str2) | |
1030 | { | |
1031 | *str2 = 0; | |
1032 | ||
1033 | /* if two instructions are present and we already have one saved | |
1034 | then first write it out */ | |
1035 | d10v_cleanup (); | |
1036 | ||
1037 | /* assemble first instruction and save it */ | |
1038 | prev_insn = do_assemble (str, &prev_opcode); | |
1039 | if (prev_insn == -1) | |
1040 | as_fatal (_("can't find opcode ")); | |
1041 | fixups = fixups->next; | |
1042 | str = str2 + 2; | |
1043 | } | |
1044 | } | |
1045 | ||
1046 | insn = do_assemble (str, &opcode); | |
1047 | if (insn == -1) | |
1048 | { | |
1049 | if (extype) | |
1050 | { | |
1051 | etype = extype; | |
1052 | return; | |
1053 | } | |
1054 | as_fatal (_("can't find opcode ")); | |
1055 | } | |
1056 | ||
1057 | if (etype) | |
1058 | { | |
1059 | extype = etype; | |
1060 | etype = 0; | |
1061 | } | |
1062 | ||
1063 | /* if this is a long instruction, write it and any previous short instruction */ | |
1064 | if (opcode->format & LONG_OPCODE) | |
1065 | { | |
1066 | if (extype) | |
1067 | as_fatal (_("Unable to mix instructions as specified")); | |
1068 | d10v_cleanup (); | |
1069 | write_long (opcode, insn, fixups); | |
1070 | prev_opcode = NULL; | |
1071 | return; | |
1072 | } | |
1073 | ||
1074 | if (prev_opcode && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
1075 | d10v_cleanup(); | |
1076 | ||
1077 | if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0)) | |
1078 | { | |
1079 | /* no instructions saved */ | |
1080 | prev_opcode = NULL; | |
1081 | } | |
1082 | else | |
1083 | { | |
1084 | if (extype) | |
1085 | as_fatal (_("Unable to mix instructions as specified")); | |
1086 | /* save off last instruction so it may be packed on next pass */ | |
1087 | prev_opcode = opcode; | |
1088 | prev_insn = insn; | |
1089 | prev_seg = now_seg; | |
1090 | prev_subseg = now_subseg; | |
1091 | fixups = fixups->next; | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | ||
1096 | /* do_assemble assembles a single instruction and returns an opcode */ | |
1097 | /* it returns -1 (an invalid opcode) on error */ | |
1098 | ||
1099 | static unsigned long | |
1100 | do_assemble (str, opcode) | |
1101 | char *str; | |
1102 | struct d10v_opcode **opcode; | |
1103 | { | |
1104 | unsigned char *op_start, *save; | |
1105 | unsigned char *op_end; | |
1106 | char name[20]; | |
1107 | int nlen = 0; | |
1108 | expressionS myops[6]; | |
1109 | unsigned long insn; | |
1110 | ||
1111 | /* Drop leading whitespace. */ | |
1112 | while (*str == ' ') | |
1113 | str++; | |
1114 | ||
1115 | /* Find the opcode end. */ | |
1116 | for (op_start = op_end = (unsigned char *) (str); | |
1117 | *op_end | |
1118 | && nlen < 20 | |
1119 | && !is_end_of_line[*op_end] && *op_end != ' '; | |
1120 | op_end++) | |
1121 | { | |
1122 | name[nlen] = tolower (op_start[nlen]); | |
1123 | nlen++; | |
1124 | } | |
1125 | name[nlen] = 0; | |
1126 | ||
1127 | if (nlen == 0) | |
1128 | return -1; | |
1129 | ||
1130 | /* Find the first opcode with the proper name. */ | |
1131 | *opcode = (struct d10v_opcode *)hash_find (d10v_hash, name); | |
1132 | if (*opcode == NULL) | |
1133 | as_fatal (_("unknown opcode: %s"),name); | |
1134 | ||
1135 | save = input_line_pointer; | |
1136 | input_line_pointer = op_end; | |
1137 | *opcode = find_opcode (*opcode, myops); | |
1138 | if (*opcode == 0) | |
1139 | return -1; | |
1140 | input_line_pointer = save; | |
1141 | ||
1142 | insn = build_insn ((*opcode), myops, 0); | |
1143 | return (insn); | |
1144 | } | |
1145 | ||
1146 | /* Find the symbol which has the same name as the register in the given expression. */ | |
1147 | static symbolS * | |
1148 | find_symbol_matching_register (exp) | |
1149 | expressionS * exp; | |
1150 | { | |
1151 | int i; | |
1152 | ||
1153 | if (exp->X_op != O_register) | |
1154 | return NULL; | |
1155 | ||
1156 | /* Find the name of the register. */ | |
1157 | for (i = d10v_reg_name_cnt (); i--;) | |
1158 | if (d10v_predefined_registers [i].value == exp->X_add_number) | |
1159 | break; | |
1160 | ||
1161 | if (i < 0) | |
1162 | abort (); | |
1163 | ||
1164 | /* Now see if a symbol has been defined with the same name. */ | |
1165 | return symbol_find (d10v_predefined_registers [i].name); | |
1166 | } | |
1167 | ||
1168 | ||
1169 | /* find_opcode() gets a pointer to an entry in the opcode table. */ | |
1170 | /* It must look at all opcodes with the same name and use the operands */ | |
1171 | /* to choose the correct opcode. */ | |
1172 | ||
1173 | static struct d10v_opcode * | |
1174 | find_opcode (opcode, myops) | |
1175 | struct d10v_opcode *opcode; | |
1176 | expressionS myops[]; | |
1177 | { | |
1178 | int i, match, done; | |
1179 | struct d10v_opcode *next_opcode; | |
1180 | ||
1181 | /* get all the operands and save them as expressions */ | |
1182 | get_operands (myops); | |
1183 | ||
1184 | /* now see if the operand is a fake. If so, find the correct size */ | |
1185 | /* instruction, if possible */ | |
1186 | if (opcode->format == OPCODE_FAKE) | |
1187 | { | |
1188 | int opnum = opcode->operands[0]; | |
1189 | int flags; | |
1190 | ||
1191 | if (myops[opnum].X_op == O_register) | |
1192 | { | |
1193 | myops[opnum].X_op = O_symbol; | |
1194 | myops[opnum].X_add_symbol = symbol_find_or_make ((char *)myops[opnum].X_op_symbol); | |
1195 | myops[opnum].X_add_number = 0; | |
1196 | myops[opnum].X_op_symbol = NULL; | |
1197 | } | |
1198 | ||
1199 | next_opcode=opcode+1; | |
1200 | ||
1201 | /* If the first operand is supposed to be a register, make sure | |
1202 | we got a valid one. */ | |
1203 | flags = d10v_operands[next_opcode->operands[0]].flags; | |
1204 | if (flags & OPERAND_REG) | |
1205 | { | |
1206 | int X_op = myops[0].X_op; | |
1207 | int num = myops[0].X_add_number; | |
1208 | ||
1209 | if (X_op != O_register | |
1210 | || (num & ~flags | |
1211 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 | |
1212 | | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL))) | |
1213 | { | |
1214 | as_bad (_("bad opcode or operands")); | |
1215 | return 0; | |
1216 | } | |
1217 | } | |
1218 | ||
1219 | if (myops[opnum].X_op == O_constant || (myops[opnum].X_op == O_symbol && | |
1220 | S_IS_DEFINED(myops[opnum].X_add_symbol) && | |
1221 | (S_GET_SEGMENT(myops[opnum].X_add_symbol) == now_seg))) | |
1222 | { | |
1223 | for (i=0; opcode->operands[i+1]; i++) | |
1224 | { | |
1225 | int bits = d10v_operands[next_opcode->operands[opnum]].bits; | |
1226 | int flags = d10v_operands[next_opcode->operands[opnum]].flags; | |
1227 | if (flags & OPERAND_ADDR) | |
1228 | bits += 2; | |
1229 | if (myops[opnum].X_op == O_constant) | |
1230 | { | |
1231 | if (!check_range (myops[opnum].X_add_number, bits, flags)) | |
1232 | return next_opcode; | |
1233 | } | |
1234 | else | |
1235 | { | |
1236 | fragS *f; | |
1237 | long value; | |
1238 | /* calculate the current address by running through the previous frags */ | |
1239 | /* and adding our current offset */ | |
1240 | for (value = 0, f = frchain_now->frch_root; f; f = f->fr_next) | |
1241 | value += f->fr_fix + f->fr_offset; | |
1242 | ||
1243 | if (flags & OPERAND_ADDR) | |
1244 | value = S_GET_VALUE(myops[opnum].X_add_symbol) - value - | |
1245 | (obstack_next_free(&frchain_now->frch_obstack) - frag_now->fr_literal); | |
1246 | else | |
1247 | value = S_GET_VALUE(myops[opnum].X_add_symbol); | |
1248 | ||
1249 | if (AT_WORD_P (&myops[opnum])) | |
1250 | { | |
1251 | if (bits > 4) | |
1252 | { | |
1253 | bits += 2; | |
1254 | if (!check_range (value, bits, flags)) | |
1255 | return next_opcode; | |
1256 | } | |
1257 | } | |
1258 | else if (!check_range (value, bits, flags)) | |
1259 | return next_opcode; | |
1260 | } | |
1261 | next_opcode++; | |
1262 | } | |
1263 | as_fatal (_("value out of range")); | |
1264 | } | |
1265 | else | |
1266 | { | |
1267 | /* not a constant, so use a long instruction */ | |
1268 | return opcode+2; | |
1269 | } | |
1270 | } | |
1271 | else | |
1272 | { | |
1273 | match = 0; | |
1274 | /* now search the opcode table table for one with operands */ | |
1275 | /* that matches what we've got */ | |
1276 | while (!match) | |
1277 | { | |
1278 | match = 1; | |
1279 | for (i = 0; opcode->operands[i]; i++) | |
1280 | { | |
1281 | int flags = d10v_operands[opcode->operands[i]].flags; | |
1282 | int X_op = myops[i].X_op; | |
1283 | int num = myops[i].X_add_number; | |
1284 | ||
1285 | if (X_op == 0) | |
1286 | { | |
1287 | match = 0; | |
1288 | break; | |
1289 | } | |
1290 | ||
1291 | if (flags & OPERAND_REG) | |
1292 | { | |
1293 | if ((X_op != O_register) | |
1294 | || (num & ~flags | |
1295 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 | |
1296 | | OPERAND_FFLAG | OPERAND_CFLAG | |
1297 | | OPERAND_CONTROL))) | |
1298 | { | |
1299 | match = 0; | |
1300 | break; | |
1301 | } | |
1302 | } | |
1303 | ||
1304 | if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) || | |
1305 | ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) || | |
1306 | ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) || | |
1307 | ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) || | |
1308 | ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN)))) | |
1309 | { | |
1310 | match = 0; | |
1311 | break; | |
1312 | } | |
1313 | ||
1314 | /* Unfortunatly, for the indirect operand in instructions such as | |
1315 | ``ldb r1, @(c,r14)'' this function can be passed X_op == O_register | |
1316 | (because 'c' is a valid register name). However we cannot just | |
1317 | ignore the case when X_op == O_register but flags & OPERAND_REG is | |
1318 | null, so we check to see if a symbol of the same name as the register | |
1319 | exists. If the symbol does exist, then the parser was unable to | |
1320 | distinguish the two cases and we fix things here. (Ref: PR14826) */ | |
1321 | ||
1322 | if (!(flags & OPERAND_REG) && (X_op == O_register)) | |
1323 | { | |
1324 | symbolS * sym; | |
1325 | ||
1326 | sym = find_symbol_matching_register (& myops[i]); | |
1327 | ||
1328 | if (sym != NULL) | |
1329 | { | |
1330 | myops [i].X_op == X_op == O_symbol; | |
1331 | myops [i].X_add_symbol = sym; | |
1332 | } | |
1333 | else | |
1334 | as_bad | |
1335 | (_("illegal operand - register name found where none expected")); | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | /* We're only done if the operands matched so far AND there | |
1340 | are no more to check. */ | |
1341 | if (match && myops[i].X_op == 0) | |
1342 | break; | |
1343 | else | |
1344 | match = 0; | |
1345 | ||
1346 | next_opcode = opcode + 1; | |
1347 | ||
1348 | if (next_opcode->opcode == 0) | |
1349 | break; | |
1350 | ||
1351 | if (strcmp (next_opcode->name, opcode->name)) | |
1352 | break; | |
1353 | ||
1354 | opcode = next_opcode; | |
1355 | } | |
1356 | } | |
1357 | ||
1358 | if (!match) | |
1359 | { | |
1360 | as_bad (_("bad opcode or operands")); | |
1361 | return (0); | |
1362 | } | |
1363 | ||
1364 | /* Check that all registers that are required to be even are. */ | |
1365 | /* Also, if any operands were marked as registers, but were really symbols */ | |
1366 | /* fix that here. */ | |
1367 | for (i=0; opcode->operands[i]; i++) | |
1368 | { | |
1369 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) && | |
1370 | (myops[i].X_add_number & 1)) | |
1371 | as_fatal (_("Register number must be EVEN")); | |
1372 | if (myops[i].X_op == O_register) | |
1373 | { | |
1374 | if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG)) | |
1375 | { | |
1376 | myops[i].X_op = O_symbol; | |
1377 | myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol); | |
1378 | myops[i].X_add_number = 0; | |
1379 | myops[i].X_op_symbol = NULL; | |
1380 | } | |
1381 | } | |
1382 | } | |
1383 | return opcode; | |
1384 | } | |
1385 | ||
1386 | /* if while processing a fixup, a reloc really needs to be created */ | |
1387 | /* then it is done here */ | |
1388 | ||
1389 | arelent * | |
1390 | tc_gen_reloc (seg, fixp) | |
1391 | asection *seg; | |
1392 | fixS *fixp; | |
1393 | { | |
1394 | arelent *reloc; | |
1395 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
310b5aa2 ILT |
1396 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
1397 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
1398 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
1399 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
1400 | if (reloc->howto == (reloc_howto_type *) NULL) | |
1401 | { | |
1402 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1403 | _("reloc %d not supported by object file format"), (int)fixp->fx_r_type); | |
1404 | return NULL; | |
1405 | } | |
1406 | ||
1407 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1408 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1409 | reloc->address = fixp->fx_offset; | |
1410 | ||
1411 | reloc->addend = fixp->fx_addnumber; | |
1412 | ||
1413 | return reloc; | |
1414 | } | |
1415 | ||
1416 | int | |
1417 | md_estimate_size_before_relax (fragp, seg) | |
1418 | fragS *fragp; | |
1419 | asection *seg; | |
1420 | { | |
1421 | abort (); | |
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | long | |
1426 | md_pcrel_from_section (fixp, sec) | |
1427 | fixS *fixp; | |
1428 | segT sec; | |
1429 | { | |
1430 | if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) || | |
1431 | (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
1432 | return 0; | |
1433 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1434 | } | |
1435 | ||
1436 | int | |
1437 | md_apply_fix3 (fixp, valuep, seg) | |
1438 | fixS *fixp; | |
1439 | valueT *valuep; | |
1440 | segT seg; | |
1441 | { | |
1442 | char *where; | |
1443 | unsigned long insn; | |
1444 | long value; | |
1445 | int op_type; | |
1446 | int left=0; | |
1447 | ||
1448 | if (fixp->fx_addsy == (symbolS *) NULL) | |
1449 | { | |
1450 | value = *valuep; | |
1451 | fixp->fx_done = 1; | |
1452 | } | |
1453 | else if (fixp->fx_pcrel) | |
1454 | value = *valuep; | |
1455 | else | |
1456 | { | |
1457 | value = fixp->fx_offset; | |
1458 | if (fixp->fx_subsy != (symbolS *) NULL) | |
1459 | { | |
1460 | if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) | |
1461 | value -= S_GET_VALUE (fixp->fx_subsy); | |
1462 | else | |
1463 | { | |
1464 | /* We don't actually support subtracting a symbol. */ | |
1465 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1466 | _("expression too complex")); | |
1467 | } | |
1468 | } | |
1469 | } | |
1470 | ||
1471 | op_type = fixp->fx_r_type; | |
1472 | if (op_type & 2048) | |
1473 | { | |
1474 | op_type -= 2048; | |
1475 | if (op_type & 1024) | |
1476 | { | |
1477 | op_type -= 1024; | |
1478 | fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L; | |
1479 | left = 1; | |
1480 | } | |
1481 | else if (op_type & 4096) | |
1482 | { | |
1483 | op_type -= 4096; | |
1484 | fixp->fx_r_type = BFD_RELOC_D10V_18; | |
1485 | } | |
1486 | else | |
1487 | fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]); | |
1488 | } | |
1489 | ||
1490 | /* Fetch the instruction, insert the fully resolved operand | |
1491 | value, and stuff the instruction back again. */ | |
1492 | where = fixp->fx_frag->fr_literal + fixp->fx_where; | |
1493 | insn = bfd_getb32 ((unsigned char *) where); | |
1494 | ||
1495 | switch (fixp->fx_r_type) | |
1496 | { | |
1497 | case BFD_RELOC_D10V_10_PCREL_L: | |
1498 | case BFD_RELOC_D10V_10_PCREL_R: | |
1499 | case BFD_RELOC_D10V_18_PCREL: | |
1500 | case BFD_RELOC_D10V_18: | |
1501 | /* instruction addresses are always right-shifted by 2 */ | |
1502 | value >>= AT_WORD_RIGHT_SHIFT; | |
1503 | if (fixp->fx_size == 2) | |
1504 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1505 | else | |
1506 | { | |
1507 | struct d10v_opcode *rep, *repi; | |
1508 | ||
1509 | rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep"); | |
1510 | repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi"); | |
1511 | if ((insn & FM11) == FM11 | |
1512 | && (repi != NULL && (insn & repi->mask) == repi->opcode | |
1513 | || rep != NULL && (insn & rep->mask) == rep->opcode) | |
1514 | && value < 4) | |
1515 | as_fatal | |
1516 | (_("line %d: rep or repi must include at least 4 instructions"), | |
1517 | fixp->fx_line); | |
1518 | insn = d10v_insert_operand (insn, op_type, (offsetT)value, left, fixp); | |
1519 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1520 | } | |
1521 | break; | |
1522 | case BFD_RELOC_32: | |
1523 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
1524 | break; | |
1525 | case BFD_RELOC_16: | |
1526 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1527 | break; | |
1528 | ||
1529 | case BFD_RELOC_VTABLE_INHERIT: | |
1530 | case BFD_RELOC_VTABLE_ENTRY: | |
1531 | fixp->fx_done = 0; | |
1532 | return 1; | |
1533 | ||
1534 | default: | |
1535 | as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp->fx_line,fixp->fx_r_type); | |
1536 | } | |
1537 | return 0; | |
1538 | } | |
1539 | ||
1540 | /* d10v_cleanup() is called after the assembler has finished parsing the input | |
1541 | file or after a label is defined. Because the D10V assembler sometimes saves short | |
1542 | instructions to see if it can package them with the next instruction, there may | |
1543 | be a short instruction that still needs written. */ | |
1544 | int | |
1545 | d10v_cleanup () | |
1546 | { | |
1547 | segT seg; | |
1548 | subsegT subseg; | |
1549 | ||
1550 | if (prev_opcode && etype == 0) | |
1551 | { | |
1552 | seg = now_seg; | |
1553 | subseg = now_subseg; | |
1554 | if (prev_seg) | |
1555 | subseg_set (prev_seg, prev_subseg); | |
1556 | write_1_short (prev_opcode, prev_insn, fixups->next); | |
1557 | subseg_set (seg, subseg); | |
1558 | prev_opcode = NULL; | |
1559 | } | |
1560 | return 1; | |
1561 | } | |
1562 | ||
1563 | /* Like normal .word, except support @word */ | |
1564 | /* clobbers input_line_pointer, checks end-of-line. */ | |
1565 | static void | |
1566 | d10v_dot_word (nbytes) | |
1567 | register int nbytes; /* 1=.byte, 2=.word, 4=.long */ | |
1568 | { | |
1569 | expressionS exp; | |
1570 | bfd_reloc_code_real_type reloc; | |
1571 | char *p; | |
1572 | int offset; | |
1573 | ||
1574 | if (is_it_end_of_statement ()) | |
1575 | { | |
1576 | demand_empty_rest_of_line (); | |
1577 | return; | |
1578 | } | |
1579 | ||
1580 | do | |
1581 | { | |
1582 | expression (&exp); | |
1583 | if (!strncasecmp (input_line_pointer, "@word", 5)) | |
1584 | { | |
1585 | exp.X_add_number = 0; | |
1586 | input_line_pointer += 5; | |
1587 | ||
1588 | p = frag_more (2); | |
1589 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
1590 | &exp, 0, BFD_RELOC_D10V_18); | |
1591 | } | |
1592 | else | |
1593 | emit_expr (&exp, 2); | |
1594 | } | |
1595 | while (*input_line_pointer++ == ','); | |
1596 | ||
1597 | input_line_pointer--; /* Put terminator back into stream. */ | |
1598 | demand_empty_rest_of_line (); | |
1599 | } | |
1600 | ||
1601 | ||
1602 | /* Mitsubishi asked that we support some old syntax that apparently */ | |
1603 | /* had immediate operands starting with '#'. This is in some of their */ | |
1604 | /* sample code but is not documented (although it appears in some */ | |
1605 | /* examples in their assembler manual). For now, we'll solve this */ | |
1606 | /* compatibility problem by simply ignoring any '#' at the beginning */ | |
1607 | /* of an operand. */ | |
1608 | ||
1609 | /* operands that begin with '#' should fall through to here */ | |
1610 | /* from expr.c */ | |
1611 | ||
1612 | void | |
1613 | md_operand (expressionP) | |
1614 | expressionS *expressionP; | |
1615 | { | |
0f94f4c8 | 1616 | if (*input_line_pointer == '#' && ! do_not_ignore_hash) |
252b5132 RH |
1617 | { |
1618 | input_line_pointer++; | |
1619 | expression (expressionP); | |
1620 | } | |
1621 | } | |
1622 | ||
1623 | boolean | |
1624 | d10v_fix_adjustable (fixP) | |
1625 | fixS *fixP; | |
1626 | { | |
1627 | ||
1628 | if (fixP->fx_addsy == NULL) | |
1629 | return 1; | |
1630 | ||
1631 | /* Prevent all adjustments to global symbols. */ | |
1632 | if (S_IS_EXTERN (fixP->fx_addsy)) | |
1633 | return 0; | |
1634 | if (S_IS_WEAK (fixP->fx_addsy)) | |
1635 | return 0; | |
1636 | ||
1637 | /* We need the symbol name for the VTABLE entries */ | |
1638 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1639 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1640 | return 0; | |
1641 | ||
1642 | return 1; | |
1643 | } | |
1644 | ||
1645 | int | |
1646 | d10v_force_relocation (fixp) | |
1647 | struct fix *fixp; | |
1648 | { | |
1649 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1650 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1651 | return 1; | |
1652 | ||
1653 | return 0; | |
1654 | } |