Commit | Line | Data |
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252b5132 | 1 | /* tc-d10v.c -- Assembler code for the Mitsubishi D10V |
f7e42eb4 NC |
2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 |
3 | Free Software Foundation, Inc. | |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #include <stdio.h> | |
252b5132 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
e0c6ed95 | 25 | #include "subsegs.h" |
252b5132 RH |
26 | #include "opcode/d10v.h" |
27 | #include "elf/ppc.h" | |
bccba5f0 | 28 | //#include "read.h" |
252b5132 RH |
29 | |
30 | const char comment_chars[] = ";"; | |
31 | const char line_comment_chars[] = "#"; | |
32 | const char line_separator_chars[] = ""; | |
33 | const char *md_shortopts = "O"; | |
34 | const char EXP_CHARS[] = "eE"; | |
35 | const char FLT_CHARS[] = "dD"; | |
36 | ||
37 | int Optimizing = 0; | |
38 | ||
39 | #define AT_WORD_P(X) ((X)->X_op == O_right_shift \ | |
40 | && (X)->X_op_symbol != NULL \ | |
a77f5182 ILT |
41 | && symbol_constant_p ((X)->X_op_symbol) \ |
42 | && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT) | |
252b5132 RH |
43 | #define AT_WORD_RIGHT_SHIFT 2 |
44 | ||
e0c6ed95 | 45 | /* Fixups. */ |
252b5132 RH |
46 | #define MAX_INSN_FIXUPS (5) |
47 | struct d10v_fixup | |
48 | { | |
49 | expressionS exp; | |
50 | int operand; | |
51 | int pcrel; | |
52 | int size; | |
53 | bfd_reloc_code_real_type reloc; | |
54 | }; | |
55 | ||
56 | typedef struct _fixups | |
57 | { | |
58 | int fc; | |
59 | struct d10v_fixup fix[MAX_INSN_FIXUPS]; | |
60 | struct _fixups *next; | |
61 | } Fixups; | |
62 | ||
63 | static Fixups FixUps[2]; | |
64 | static Fixups *fixups; | |
65 | ||
0f94f4c8 NC |
66 | static int do_not_ignore_hash = 0; |
67 | ||
0a44c2b1 | 68 | typedef int packing_type; |
e0c6ed95 AM |
69 | #define PACK_UNSPEC (0) /* Packing order not specified. */ |
70 | #define PACK_PARALLEL (1) /* "||" */ | |
71 | #define PACK_LEFT_RIGHT (2) /* "->" */ | |
72 | #define PACK_RIGHT_LEFT (3) /* "<-" */ | |
73 | static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */ | |
0a44c2b1 | 74 | |
bccba5f0 | 75 | /* True if instruction swapping warnings should be inhibited. |
bfb32b52 | 76 | --nowarnswap. */ |
bccba5f0 NC |
77 | static boolean flag_warn_suppress_instructionswap; |
78 | ||
79 | /* True if instruction packing should be performed when --gstabs is specified. | |
80 | --gstabs-packing, --no-gstabs-packing. */ | |
81 | static boolean flag_allow_gstabs_packing = 1; | |
252b5132 | 82 | |
e0c6ed95 | 83 | /* Local functions. */ |
252b5132 RH |
84 | static int reg_name_search PARAMS ((char *name)); |
85 | static int register_name PARAMS ((expressionS *expressionP)); | |
86 | static int check_range PARAMS ((unsigned long num, int bits, int flags)); | |
87 | static int postfix PARAMS ((char *p)); | |
88 | static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op)); | |
89 | static int get_operands PARAMS ((expressionS exp[])); | |
90 | static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[])); | |
91 | static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn)); | |
bccba5f0 | 92 | static void write_long PARAMS ((unsigned long insn, Fixups *fx)); |
252b5132 | 93 | static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); |
e0c6ed95 | 94 | static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, |
0a44c2b1 | 95 | struct d10v_opcode *opcode2, unsigned long insn2, packing_type exec_type, Fixups *fx)); |
252b5132 RH |
96 | static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode)); |
97 | static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type, | |
98 | offsetT value, int left, fixS *fix)); | |
e0c6ed95 | 99 | static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, |
252b5132 | 100 | struct d10v_opcode *opcode2, unsigned long insn2, |
0a44c2b1 | 101 | packing_type exec_type)); |
252b5132 RH |
102 | static symbolS * find_symbol_matching_register PARAMS ((expressionS *)); |
103 | ||
104 | struct option md_longopts[] = | |
105 | { | |
106 | #define OPTION_NOWARNSWAP (OPTION_MD_BASE) | |
107 | {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP}, | |
bccba5f0 NC |
108 | #define OPTION_GSTABSPACKING (OPTION_MD_BASE + 1) |
109 | {"gstabspacking", no_argument, NULL, OPTION_GSTABSPACKING}, | |
110 | {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING}, | |
111 | #define OPTION_NOGSTABSPACKING (OPTION_MD_BASE + 2) | |
112 | {"nogstabspacking", no_argument, NULL, OPTION_NOGSTABSPACKING}, | |
113 | {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING}, | |
252b5132 RH |
114 | {NULL, no_argument, NULL, 0} |
115 | }; | |
ab3e48dc KH |
116 | |
117 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
118 | |
119 | static void d10v_dot_word PARAMS ((int)); | |
120 | ||
121 | /* The target specific pseudo-ops which we support. */ | |
122 | const pseudo_typeS md_pseudo_table[] = | |
123 | { | |
124 | { "word", d10v_dot_word, 2 }, | |
125 | { NULL, NULL, 0 } | |
126 | }; | |
127 | ||
128 | /* Opcode hash table. */ | |
129 | static struct hash_control *d10v_hash; | |
130 | ||
e0c6ed95 AM |
131 | /* Do a binary search of the d10v_predefined_registers array to see if |
132 | NAME is a valid regiter name. Return the register number from the | |
133 | array on success, or -1 on failure. */ | |
252b5132 RH |
134 | |
135 | static int | |
136 | reg_name_search (name) | |
137 | char *name; | |
138 | { | |
139 | int middle, low, high; | |
140 | int cmp; | |
141 | ||
142 | low = 0; | |
e0c6ed95 | 143 | high = d10v_reg_name_cnt () - 1; |
252b5132 RH |
144 | |
145 | do | |
146 | { | |
147 | middle = (low + high) / 2; | |
148 | cmp = strcasecmp (name, d10v_predefined_registers[middle].name); | |
149 | if (cmp < 0) | |
150 | high = middle - 1; | |
151 | else if (cmp > 0) | |
152 | low = middle + 1; | |
e0c6ed95 AM |
153 | else |
154 | return d10v_predefined_registers[middle].value; | |
252b5132 RH |
155 | } |
156 | while (low <= high); | |
157 | return -1; | |
158 | } | |
159 | ||
e0c6ed95 AM |
160 | /* Check the string at input_line_pointer |
161 | to see if it is a valid register name. */ | |
252b5132 RH |
162 | |
163 | static int | |
164 | register_name (expressionP) | |
165 | expressionS *expressionP; | |
166 | { | |
167 | int reg_number; | |
168 | char c, *p = input_line_pointer; | |
e0c6ed95 AM |
169 | |
170 | while (*p | |
171 | && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')') | |
252b5132 RH |
172 | p++; |
173 | ||
174 | c = *p; | |
175 | if (c) | |
176 | *p++ = 0; | |
177 | ||
e0c6ed95 | 178 | /* Look to see if it's in the register table. */ |
252b5132 | 179 | reg_number = reg_name_search (input_line_pointer); |
e0c6ed95 | 180 | if (reg_number >= 0) |
252b5132 RH |
181 | { |
182 | expressionP->X_op = O_register; | |
e0c6ed95 AM |
183 | /* Temporarily store a pointer to the string here. */ |
184 | expressionP->X_op_symbol = (symbolS *) input_line_pointer; | |
252b5132 RH |
185 | expressionP->X_add_number = reg_number; |
186 | input_line_pointer = p; | |
187 | return 1; | |
188 | } | |
189 | if (c) | |
e0c6ed95 | 190 | *(p - 1) = c; |
252b5132 RH |
191 | return 0; |
192 | } | |
193 | ||
252b5132 RH |
194 | static int |
195 | check_range (num, bits, flags) | |
196 | unsigned long num; | |
197 | int bits; | |
198 | int flags; | |
199 | { | |
bccba5f0 | 200 | long min, max; |
e0c6ed95 | 201 | int retval = 0; |
252b5132 | 202 | |
e0c6ed95 | 203 | /* Don't bother checking 16-bit values. */ |
252b5132 RH |
204 | if (bits == 16) |
205 | return 0; | |
206 | ||
207 | if (flags & OPERAND_SHIFT) | |
208 | { | |
e0c6ed95 AM |
209 | /* All special shift operands are unsigned and <= 16. |
210 | We allow 0 for now. */ | |
211 | if (num > 16) | |
252b5132 RH |
212 | return 1; |
213 | else | |
214 | return 0; | |
215 | } | |
216 | ||
217 | if (flags & OPERAND_SIGNED) | |
218 | { | |
e0c6ed95 | 219 | /* Signed 3-bit integers are restricted to the (-2, 3) range. */ |
c43185de DN |
220 | if (flags & RESTRICTED_NUM3) |
221 | { | |
222 | if ((long) num < -2 || (long) num > 3) | |
223 | retval = 1; | |
224 | } | |
225 | else | |
226 | { | |
e0c6ed95 AM |
227 | max = (1 << (bits - 1)) - 1; |
228 | min = - (1 << (bits - 1)); | |
c43185de DN |
229 | if (((long) num > max) || ((long) num < min)) |
230 | retval = 1; | |
231 | } | |
252b5132 RH |
232 | } |
233 | else | |
234 | { | |
235 | max = (1 << bits) - 1; | |
236 | min = 0; | |
bccba5f0 | 237 | if (((long) num > max) || ((long) num < min)) |
252b5132 RH |
238 | retval = 1; |
239 | } | |
240 | return retval; | |
241 | } | |
242 | ||
252b5132 RH |
243 | void |
244 | md_show_usage (stream) | |
e0c6ed95 | 245 | FILE *stream; |
252b5132 | 246 | { |
e0c6ed95 | 247 | fprintf (stream, _("D10V options:\n\ |
bccba5f0 NC |
248 | -O Optimize. Will do some operations in parallel.\n\ |
249 | --gstabs-packing Pack adjacent short instructions together even\n\ | |
250 | when --gstabs is specified. On by default.\n\ | |
251 | --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\ | |
252 | instructions together.\n")); | |
e0c6ed95 | 253 | } |
252b5132 RH |
254 | |
255 | int | |
256 | md_parse_option (c, arg) | |
257 | int c; | |
bccba5f0 | 258 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
259 | { |
260 | switch (c) | |
261 | { | |
262 | case 'O': | |
e0c6ed95 | 263 | /* Optimize. Will attempt to parallelize operations. */ |
252b5132 RH |
264 | Optimizing = 1; |
265 | break; | |
266 | case OPTION_NOWARNSWAP: | |
267 | flag_warn_suppress_instructionswap = 1; | |
268 | break; | |
bccba5f0 NC |
269 | case OPTION_GSTABSPACKING: |
270 | flag_allow_gstabs_packing = 1; | |
271 | break; | |
272 | case OPTION_NOGSTABSPACKING: | |
273 | flag_allow_gstabs_packing = 0; | |
274 | break; | |
252b5132 RH |
275 | default: |
276 | return 0; | |
277 | } | |
278 | return 1; | |
279 | } | |
280 | ||
281 | symbolS * | |
282 | md_undefined_symbol (name) | |
bccba5f0 | 283 | char *name ATTRIBUTE_UNUSED; |
252b5132 RH |
284 | { |
285 | return 0; | |
286 | } | |
287 | ||
e0c6ed95 AM |
288 | /* Turn a string in input_line_pointer into a floating point constant |
289 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
290 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
291 | returned, or NULL on OK. */ | |
292 | ||
252b5132 RH |
293 | char * |
294 | md_atof (type, litP, sizeP) | |
295 | int type; | |
296 | char *litP; | |
297 | int *sizeP; | |
298 | { | |
299 | int prec; | |
300 | LITTLENUM_TYPE words[4]; | |
301 | char *t; | |
302 | int i; | |
e0c6ed95 | 303 | |
252b5132 RH |
304 | switch (type) |
305 | { | |
306 | case 'f': | |
307 | prec = 2; | |
308 | break; | |
309 | case 'd': | |
310 | prec = 4; | |
311 | break; | |
312 | default: | |
313 | *sizeP = 0; | |
314 | return _("bad call to md_atof"); | |
315 | } | |
316 | ||
317 | t = atof_ieee (input_line_pointer, type, words); | |
318 | if (t) | |
319 | input_line_pointer = t; | |
e0c6ed95 | 320 | |
252b5132 | 321 | *sizeP = prec * 2; |
e0c6ed95 | 322 | |
252b5132 RH |
323 | for (i = 0; i < prec; i++) |
324 | { | |
325 | md_number_to_chars (litP, (valueT) words[i], 2); | |
e0c6ed95 | 326 | litP += 2; |
252b5132 RH |
327 | } |
328 | return NULL; | |
329 | } | |
330 | ||
331 | void | |
332 | md_convert_frag (abfd, sec, fragP) | |
bccba5f0 NC |
333 | bfd *abfd ATTRIBUTE_UNUSED; |
334 | asection *sec ATTRIBUTE_UNUSED; | |
335 | fragS *fragP ATTRIBUTE_UNUSED; | |
252b5132 RH |
336 | { |
337 | abort (); | |
338 | } | |
339 | ||
340 | valueT | |
341 | md_section_align (seg, addr) | |
342 | asection *seg; | |
343 | valueT addr; | |
344 | { | |
345 | int align = bfd_get_section_alignment (stdoutput, seg); | |
346 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
347 | } | |
348 | ||
252b5132 RH |
349 | void |
350 | md_begin () | |
351 | { | |
352 | char *prev_name = ""; | |
353 | struct d10v_opcode *opcode; | |
e0c6ed95 | 354 | d10v_hash = hash_new (); |
252b5132 RH |
355 | |
356 | /* Insert unique names into hash table. The D10v instruction set | |
357 | has many identical opcode names that have different opcodes based | |
358 | on the operands. This hash table then provides a quick index to | |
359 | the first opcode with a particular name in the opcode table. */ | |
360 | ||
e0c6ed95 | 361 | for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++) |
252b5132 RH |
362 | { |
363 | if (strcmp (prev_name, opcode->name)) | |
364 | { | |
e0c6ed95 | 365 | prev_name = (char *) opcode->name; |
252b5132 RH |
366 | hash_insert (d10v_hash, opcode->name, (char *) opcode); |
367 | } | |
368 | } | |
369 | ||
370 | fixups = &FixUps[0]; | |
371 | FixUps[0].next = &FixUps[1]; | |
372 | FixUps[1].next = &FixUps[0]; | |
373 | } | |
374 | ||
e0c6ed95 AM |
375 | /* Remove the postincrement or postdecrement operator ( '+' or '-' ) |
376 | from an expression. */ | |
252b5132 | 377 | |
e0c6ed95 AM |
378 | static int |
379 | postfix (p) | |
252b5132 RH |
380 | char *p; |
381 | { | |
e0c6ed95 | 382 | while (*p != '-' && *p != '+') |
252b5132 | 383 | { |
e0c6ed95 | 384 | if (*p == 0 || *p == '\n' || *p == '\r') |
252b5132 RH |
385 | break; |
386 | p++; | |
387 | } | |
388 | ||
e0c6ed95 | 389 | if (*p == '-') |
252b5132 RH |
390 | { |
391 | *p = ' '; | |
392 | return (-1); | |
393 | } | |
e0c6ed95 | 394 | if (*p == '+') |
252b5132 RH |
395 | { |
396 | *p = ' '; | |
397 | return (1); | |
398 | } | |
399 | ||
400 | return (0); | |
401 | } | |
402 | ||
e0c6ed95 AM |
403 | static bfd_reloc_code_real_type |
404 | get_reloc (op) | |
252b5132 RH |
405 | struct d10v_operand *op; |
406 | { | |
407 | int bits = op->bits; | |
408 | ||
e0c6ed95 | 409 | if (bits <= 4) |
252b5132 | 410 | return (0); |
e0c6ed95 AM |
411 | |
412 | if (op->flags & OPERAND_ADDR) | |
252b5132 RH |
413 | { |
414 | if (bits == 8) | |
415 | return (BFD_RELOC_D10V_10_PCREL_R); | |
416 | else | |
417 | return (BFD_RELOC_D10V_18_PCREL); | |
418 | } | |
419 | ||
420 | return (BFD_RELOC_16); | |
421 | } | |
422 | ||
e0c6ed95 | 423 | /* Parse a string of operands. Return an array of expressions. */ |
252b5132 RH |
424 | |
425 | static int | |
e0c6ed95 | 426 | get_operands (exp) |
252b5132 RH |
427 | expressionS exp[]; |
428 | { | |
429 | char *p = input_line_pointer; | |
430 | int numops = 0; | |
431 | int post = 0; | |
0f94f4c8 | 432 | int uses_at = 0; |
e0c6ed95 AM |
433 | |
434 | while (*p) | |
252b5132 | 435 | { |
e0c6ed95 | 436 | while (*p == ' ' || *p == '\t' || *p == ',') |
252b5132 | 437 | p++; |
e0c6ed95 | 438 | if (*p == 0 || *p == '\n' || *p == '\r') |
252b5132 | 439 | break; |
e0c6ed95 AM |
440 | |
441 | if (*p == '@') | |
252b5132 | 442 | { |
0f94f4c8 | 443 | uses_at = 1; |
e0c6ed95 | 444 | |
252b5132 RH |
445 | p++; |
446 | exp[numops].X_op = O_absent; | |
e0c6ed95 | 447 | if (*p == '(') |
252b5132 RH |
448 | { |
449 | p++; | |
450 | exp[numops].X_add_number = OPERAND_ATPAR; | |
451 | } | |
e0c6ed95 | 452 | else if (*p == '-') |
252b5132 RH |
453 | { |
454 | p++; | |
455 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
456 | } | |
457 | else | |
458 | { | |
459 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
3543a2f1 AO |
460 | if (*p == '+') |
461 | { | |
462 | exp[++numops].X_add_number = OPERAND_PLUS; | |
463 | ++p; | |
464 | } | |
252b5132 RH |
465 | post = postfix (p); |
466 | } | |
467 | numops++; | |
468 | continue; | |
469 | } | |
470 | ||
e0c6ed95 | 471 | if (*p == ')') |
252b5132 | 472 | { |
e0c6ed95 | 473 | /* Just skip the trailing paren. */ |
252b5132 RH |
474 | p++; |
475 | continue; | |
476 | } | |
477 | ||
478 | input_line_pointer = p; | |
479 | ||
e0c6ed95 | 480 | /* Check to see if it might be a register name. */ |
252b5132 RH |
481 | if (!register_name (&exp[numops])) |
482 | { | |
e0c6ed95 | 483 | /* Parse as an expression. */ |
0f94f4c8 NC |
484 | if (uses_at) |
485 | { | |
486 | /* Any expression that involves the indirect addressing | |
487 | cannot also involve immediate addressing. Therefore | |
488 | the use of the hash character is illegal. */ | |
489 | int save = do_not_ignore_hash; | |
490 | do_not_ignore_hash = 1; | |
e0c6ed95 | 491 | |
0f94f4c8 | 492 | expression (&exp[numops]); |
e0c6ed95 | 493 | |
0f94f4c8 NC |
494 | do_not_ignore_hash = save; |
495 | } | |
496 | else | |
497 | expression (&exp[numops]); | |
252b5132 RH |
498 | } |
499 | ||
500 | if (strncasecmp (input_line_pointer, "@word", 5) == 0) | |
501 | { | |
502 | input_line_pointer += 5; | |
503 | if (exp[numops].X_op == O_register) | |
504 | { | |
e0c6ed95 | 505 | /* If it looked like a register name but was followed by |
252b5132 | 506 | "@word" then it was really a symbol, so change it to |
e0c6ed95 | 507 | one. */ |
252b5132 | 508 | exp[numops].X_op = O_symbol; |
e0c6ed95 AM |
509 | exp[numops].X_add_symbol = |
510 | symbol_find_or_make ((char *) exp[numops].X_op_symbol); | |
252b5132 RH |
511 | } |
512 | ||
e0c6ed95 | 513 | /* Check for identifier@word+constant. */ |
252b5132 | 514 | if (*input_line_pointer == '-' || *input_line_pointer == '+') |
e0c6ed95 | 515 | { |
e0c6ed95 AM |
516 | expressionS new_exp; |
517 | expression (&new_exp); | |
518 | exp[numops].X_add_number = new_exp.X_add_number; | |
519 | } | |
252b5132 | 520 | |
e0c6ed95 | 521 | /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */ |
252b5132 RH |
522 | { |
523 | expressionS new_exp; | |
524 | memset (&new_exp, 0, sizeof new_exp); | |
525 | new_exp.X_add_number = AT_WORD_RIGHT_SHIFT; | |
526 | new_exp.X_op = O_constant; | |
527 | new_exp.X_unsigned = 1; | |
528 | exp[numops].X_op_symbol = make_expr_symbol (&new_exp); | |
529 | exp[numops].X_op = O_right_shift; | |
530 | } | |
531 | ||
532 | know (AT_WORD_P (&exp[numops])); | |
533 | } | |
e0c6ed95 AM |
534 | |
535 | if (exp[numops].X_op == O_illegal) | |
252b5132 | 536 | as_bad (_("illegal operand")); |
e0c6ed95 | 537 | else if (exp[numops].X_op == O_absent) |
252b5132 RH |
538 | as_bad (_("missing operand")); |
539 | ||
540 | numops++; | |
541 | p = input_line_pointer; | |
542 | } | |
543 | ||
e0c6ed95 | 544 | switch (post) |
252b5132 | 545 | { |
e0c6ed95 | 546 | case -1: /* Postdecrement mode. */ |
252b5132 RH |
547 | exp[numops].X_op = O_absent; |
548 | exp[numops++].X_add_number = OPERAND_MINUS; | |
549 | break; | |
e0c6ed95 | 550 | case 1: /* Postincrement mode. */ |
252b5132 RH |
551 | exp[numops].X_op = O_absent; |
552 | exp[numops++].X_add_number = OPERAND_PLUS; | |
553 | break; | |
554 | } | |
555 | ||
556 | exp[numops].X_op = 0; | |
557 | return (numops); | |
558 | } | |
559 | ||
560 | static unsigned long | |
e0c6ed95 | 561 | d10v_insert_operand (insn, op_type, value, left, fix) |
252b5132 RH |
562 | unsigned long insn; |
563 | int op_type; | |
564 | offsetT value; | |
565 | int left; | |
566 | fixS *fix; | |
567 | { | |
568 | int shift, bits; | |
569 | ||
570 | shift = d10v_operands[op_type].shift; | |
571 | if (left) | |
572 | shift += 15; | |
573 | ||
574 | bits = d10v_operands[op_type].bits; | |
575 | ||
e0c6ed95 | 576 | /* Truncate to the proper number of bits. */ |
252b5132 | 577 | if (check_range (value, bits, d10v_operands[op_type].flags)) |
ab3e48dc KH |
578 | as_bad_where (fix->fx_file, fix->fx_line, |
579 | _("operand out of range: %d"), value); | |
252b5132 RH |
580 | |
581 | value &= 0x7FFFFFFF >> (31 - bits); | |
582 | insn |= (value << shift); | |
583 | ||
584 | return insn; | |
585 | } | |
586 | ||
e0c6ed95 AM |
587 | /* Take a pointer to the opcode entry in the opcode table and the |
588 | array of operand expressions. Return the instruction. */ | |
252b5132 RH |
589 | |
590 | static unsigned long | |
e0c6ed95 | 591 | build_insn (opcode, opers, insn) |
252b5132 RH |
592 | struct d10v_opcode *opcode; |
593 | expressionS *opers; | |
594 | unsigned long insn; | |
595 | { | |
596 | int i, bits, shift, flags, format; | |
597 | unsigned long number; | |
e0c6ed95 AM |
598 | |
599 | /* The insn argument is only used for the DIVS kludge. */ | |
252b5132 RH |
600 | if (insn) |
601 | format = LONG_R; | |
602 | else | |
603 | { | |
604 | insn = opcode->opcode; | |
605 | format = opcode->format; | |
606 | } | |
e0c6ed95 AM |
607 | |
608 | for (i = 0; opcode->operands[i]; i++) | |
252b5132 RH |
609 | { |
610 | flags = d10v_operands[opcode->operands[i]].flags; | |
611 | bits = d10v_operands[opcode->operands[i]].bits; | |
612 | shift = d10v_operands[opcode->operands[i]].shift; | |
613 | number = opers[i].X_add_number; | |
614 | ||
e0c6ed95 | 615 | if (flags & OPERAND_REG) |
252b5132 RH |
616 | { |
617 | number &= REGISTER_MASK; | |
618 | if (format == LONG_L) | |
619 | shift += 15; | |
620 | } | |
621 | ||
e0c6ed95 | 622 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant) |
252b5132 | 623 | { |
e0c6ed95 | 624 | /* Now create a fixup. */ |
252b5132 RH |
625 | |
626 | if (fixups->fc >= MAX_INSN_FIXUPS) | |
627 | as_fatal (_("too many fixups")); | |
628 | ||
629 | if (AT_WORD_P (&opers[i])) | |
630 | { | |
e0c6ed95 | 631 | /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD). */ |
252b5132 RH |
632 | fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18; |
633 | opers[i].X_op = O_symbol; | |
e0c6ed95 | 634 | opers[i].X_op_symbol = NULL; /* Should free it. */ |
252b5132 RH |
635 | /* number is left shifted by AT_WORD_RIGHT_SHIFT so |
636 | that, it is aligned with the symbol's value. Later, | |
637 | BFD_RELOC_D10V_18 will right shift (symbol_value + | |
e0c6ed95 | 638 | X_add_number). */ |
252b5132 RH |
639 | number <<= AT_WORD_RIGHT_SHIFT; |
640 | opers[i].X_add_number = number; | |
641 | } | |
642 | else | |
e0c6ed95 AM |
643 | fixups->fix[fixups->fc].reloc = |
644 | get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]); | |
252b5132 | 645 | |
e0c6ed95 | 646 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 || |
252b5132 | 647 | fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18) |
e0c6ed95 | 648 | fixups->fix[fixups->fc].size = 2; |
252b5132 RH |
649 | else |
650 | fixups->fix[fixups->fc].size = 4; | |
e0c6ed95 | 651 | |
252b5132 RH |
652 | fixups->fix[fixups->fc].exp = opers[i]; |
653 | fixups->fix[fixups->fc].operand = opcode->operands[i]; | |
e0c6ed95 AM |
654 | fixups->fix[fixups->fc].pcrel = |
655 | (flags & OPERAND_ADDR) ? true : false; | |
252b5132 RH |
656 | (fixups->fc)++; |
657 | } | |
658 | ||
e0c6ed95 | 659 | /* Truncate to the proper number of bits. */ |
252b5132 | 660 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) |
e0c6ed95 | 661 | as_bad (_("operand out of range: %d"), number); |
252b5132 RH |
662 | number &= 0x7FFFFFFF >> (31 - bits); |
663 | insn = insn | (number << shift); | |
664 | } | |
665 | ||
e0c6ed95 AM |
666 | /* kludge: for DIVS, we need to put the operands in twice */ |
667 | /* on the second pass, format is changed to LONG_R to force | |
668 | the second set of operands to not be shifted over 15. */ | |
669 | if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L)) | |
252b5132 | 670 | insn = build_insn (opcode, opers, insn); |
e0c6ed95 | 671 | |
252b5132 RH |
672 | return insn; |
673 | } | |
674 | ||
e0c6ed95 AM |
675 | /* Write out a long form instruction. */ |
676 | ||
252b5132 | 677 | static void |
bccba5f0 | 678 | write_long (insn, fx) |
252b5132 RH |
679 | unsigned long insn; |
680 | Fixups *fx; | |
681 | { | |
682 | int i, where; | |
e0c6ed95 | 683 | char *f = frag_more (4); |
252b5132 RH |
684 | |
685 | insn |= FM11; | |
686 | number_to_chars_bigendian (f, insn, 4); | |
687 | ||
e0c6ed95 | 688 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
689 | { |
690 | if (fx->fix[i].reloc) | |
e0c6ed95 AM |
691 | { |
692 | where = f - frag_now->fr_literal; | |
252b5132 RH |
693 | if (fx->fix[i].size == 2) |
694 | where += 2; | |
695 | ||
696 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
e0c6ed95 | 697 | fx->fix[i].operand |= 4096; |
252b5132 RH |
698 | |
699 | fix_new_exp (frag_now, | |
700 | where, | |
701 | fx->fix[i].size, | |
702 | &(fx->fix[i].exp), | |
703 | fx->fix[i].pcrel, | |
704 | fx->fix[i].operand|2048); | |
705 | } | |
706 | } | |
707 | fx->fc = 0; | |
708 | } | |
709 | ||
e0c6ed95 | 710 | /* Write out a short form instruction by itself. */ |
252b5132 | 711 | |
252b5132 | 712 | static void |
e0c6ed95 | 713 | write_1_short (opcode, insn, fx) |
252b5132 RH |
714 | struct d10v_opcode *opcode; |
715 | unsigned long insn; | |
716 | Fixups *fx; | |
717 | { | |
e0c6ed95 | 718 | char *f = frag_more (4); |
252b5132 RH |
719 | int i, where; |
720 | ||
721 | if (opcode->exec_type & PARONLY) | |
722 | as_fatal (_("Instruction must be executed in parallel with another instruction.")); | |
723 | ||
e0c6ed95 AM |
724 | /* The other container needs to be NOP. */ |
725 | /* According to 4.3.1: for FM=00, sub-instructions performed only | |
726 | by IU cannot be encoded in L-container. */ | |
252b5132 | 727 | if (opcode->unit == IU) |
e0c6ed95 | 728 | insn |= FM00 | (NOP << 15); /* Right container. */ |
252b5132 | 729 | else |
e0c6ed95 | 730 | insn = FM00 | (insn << 15) | NOP; /* Left container. */ |
252b5132 RH |
731 | |
732 | number_to_chars_bigendian (f, insn, 4); | |
e0c6ed95 | 733 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
734 | { |
735 | if (fx->fix[i].reloc) | |
e0c6ed95 AM |
736 | { |
737 | where = f - frag_now->fr_literal; | |
252b5132 RH |
738 | if (fx->fix[i].size == 2) |
739 | where += 2; | |
740 | ||
741 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) | |
e0c6ed95 | 742 | fx->fix[i].operand |= 4096; |
252b5132 | 743 | |
e0c6ed95 AM |
744 | /* If it's an R reloc, we may have to switch it to L. */ |
745 | if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) | |
746 | && (opcode->unit != IU)) | |
252b5132 RH |
747 | fx->fix[i].operand |= 1024; |
748 | ||
749 | fix_new_exp (frag_now, | |
e0c6ed95 | 750 | where, |
252b5132 RH |
751 | fx->fix[i].size, |
752 | &(fx->fix[i].exp), | |
753 | fx->fix[i].pcrel, | |
754 | fx->fix[i].operand|2048); | |
755 | } | |
756 | } | |
757 | fx->fc = 0; | |
758 | } | |
759 | ||
0a44c2b1 DL |
760 | /* Expects two short instructions. |
761 | If possible, writes out both as a single packed instruction. | |
762 | Otherwise, writes out the first one, packed with a NOP. | |
e0c6ed95 | 763 | Returns number of instructions not written out. */ |
0a44c2b1 | 764 | |
252b5132 | 765 | static int |
e0c6ed95 | 766 | write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) |
252b5132 RH |
767 | struct d10v_opcode *opcode1, *opcode2; |
768 | unsigned long insn1, insn2; | |
0a44c2b1 | 769 | packing_type exec_type; |
252b5132 RH |
770 | Fixups *fx; |
771 | { | |
772 | unsigned long insn; | |
773 | char *f; | |
e0c6ed95 | 774 | int i, j, where; |
252b5132 | 775 | |
e0c6ed95 AM |
776 | if ((exec_type != PACK_PARALLEL) |
777 | && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY))) | |
252b5132 | 778 | as_fatal (_("Instruction must be executed in parallel")); |
252b5132 | 779 | |
e0c6ed95 AM |
780 | if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE)) |
781 | as_fatal (_("Long instructions may not be combined.")); | |
252b5132 | 782 | |
e0c6ed95 | 783 | switch (exec_type) |
252b5132 | 784 | { |
e0c6ed95 | 785 | case PACK_UNSPEC: /* Order not specified. */ |
0a44c2b1 DL |
786 | if (opcode1->exec_type & ALONE) |
787 | { | |
e0c6ed95 AM |
788 | /* Case of a short branch on a separate GAS line. |
789 | Pack with NOP. */ | |
0a44c2b1 DL |
790 | write_1_short (opcode1, insn1, fx->next); |
791 | return 1; | |
792 | } | |
e0c6ed95 AM |
793 | if (Optimizing |
794 | && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
252b5132 | 795 | { |
e0c6ed95 | 796 | /* Parallel. */ |
252b5132 RH |
797 | if (opcode1->unit == IU) |
798 | insn = FM00 | (insn2 << 15) | insn1; | |
799 | else if (opcode2->unit == MU) | |
800 | insn = FM00 | (insn2 << 15) | insn1; | |
801 | else | |
c2c607a4 | 802 | insn = FM00 | (insn1 << 15) | insn2; |
252b5132 | 803 | } |
e0c6ed95 AM |
804 | else if (opcode1->unit == IU) |
805 | /* Reverse sequential with IU opcode1 on right and done first. */ | |
0a44c2b1 | 806 | insn = FM10 | (insn2 << 15) | insn1; |
252b5132 | 807 | else |
c2c607a4 AO |
808 | /* Sequential with non-IU opcode1 on left and done first. */ |
809 | insn = FM01 | (insn1 << 15) | insn2; | |
252b5132 | 810 | break; |
252b5132 | 811 | |
0a44c2b1 DL |
812 | case PACK_PARALLEL: |
813 | if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ) | |
e0c6ed95 AM |
814 | as_fatal |
815 | (_("One of these instructions may not be executed in parallel.")); | |
252b5132 RH |
816 | if (opcode1->unit == IU) |
817 | { | |
818 | if (opcode2->unit == IU) | |
819 | as_fatal (_("Two IU instructions may not be executed in parallel")); | |
e0c6ed95 | 820 | if (!flag_warn_suppress_instructionswap) |
252b5132 | 821 | as_warn (_("Swapping instruction order")); |
e0c6ed95 | 822 | insn = FM00 | (insn2 << 15) | insn1; |
252b5132 RH |
823 | } |
824 | else if (opcode2->unit == MU) | |
825 | { | |
826 | if (opcode1->unit == MU) | |
827 | as_fatal (_("Two MU instructions may not be executed in parallel")); | |
e0c6ed95 | 828 | if (!flag_warn_suppress_instructionswap) |
252b5132 RH |
829 | as_warn (_("Swapping instruction order")); |
830 | insn = FM00 | (insn2 << 15) | insn1; | |
831 | } | |
832 | else | |
c2c607a4 | 833 | insn = FM00 | (insn1 << 15) | insn2; |
252b5132 | 834 | break; |
0a44c2b1 | 835 | |
0a44c2b1 | 836 | case PACK_LEFT_RIGHT: |
252b5132 | 837 | if (opcode1->unit != IU) |
e0c6ed95 | 838 | insn = FM01 | (insn1 << 15) | insn2; |
252b5132 RH |
839 | else if (opcode2->unit == MU || opcode2->unit == EITHER) |
840 | { | |
e0c6ed95 | 841 | if (!flag_warn_suppress_instructionswap) |
252b5132 | 842 | as_warn (_("Swapping instruction order")); |
0a44c2b1 | 843 | insn = FM10 | (insn2 << 15) | insn1; |
252b5132 RH |
844 | } |
845 | else | |
846 | as_fatal (_("IU instruction may not be in the left container")); | |
0a44c2b1 DL |
847 | if (opcode1->exec_type & ALONE) |
848 | as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); | |
252b5132 | 849 | break; |
0a44c2b1 | 850 | |
0a44c2b1 | 851 | case PACK_RIGHT_LEFT: |
252b5132 RH |
852 | if (opcode2->unit != MU) |
853 | insn = FM10 | (insn1 << 15) | insn2; | |
854 | else if (opcode1->unit == IU || opcode1->unit == EITHER) | |
855 | { | |
e0c6ed95 | 856 | if (!flag_warn_suppress_instructionswap) |
252b5132 | 857 | as_warn (_("Swapping instruction order")); |
e0c6ed95 | 858 | insn = FM01 | (insn2 << 15) | insn1; |
252b5132 RH |
859 | } |
860 | else | |
861 | as_fatal (_("MU instruction may not be in the right container")); | |
0a44c2b1 DL |
862 | if (opcode2->exec_type & ALONE) |
863 | as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); | |
252b5132 | 864 | break; |
0a44c2b1 | 865 | |
252b5132 RH |
866 | default: |
867 | as_fatal (_("unknown execution type passed to write_2_short()")); | |
868 | } | |
869 | ||
e0c6ed95 | 870 | f = frag_more (4); |
252b5132 RH |
871 | number_to_chars_bigendian (f, insn, 4); |
872 | ||
c2c607a4 AO |
873 | /* Process fixup chains. fx refers to insn2 when j == 0, and to |
874 | insn1 when j == 1. Yes, it's reversed. */ | |
0a44c2b1 | 875 | |
e0c6ed95 | 876 | for (j = 0; j < 2; j++) |
252b5132 | 877 | { |
e0c6ed95 | 878 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
879 | { |
880 | if (fx->fix[i].reloc) | |
881 | { | |
e0c6ed95 | 882 | where = f - frag_now->fr_literal; |
252b5132 RH |
883 | if (fx->fix[i].size == 2) |
884 | where += 2; | |
e0c6ed95 | 885 | |
c2c607a4 AO |
886 | if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R |
887 | /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to | |
888 | the instruction in the L container has to be | |
889 | adjusted to BDF_RELOC_D10V_10_PCREL_L. When | |
890 | j==0, we're processing insn2's operands, so we | |
891 | want to mark the operand if insn2 is *not* in the | |
892 | R container. When j==1, we're processing insn1's | |
893 | operands, so we want to mark the operand if insn2 | |
894 | *is* in the R container. Note that, if two | |
895 | instructions are identical, we're never going to | |
896 | swap them, so the test is safe. */ | |
897 | && j == ((insn & 0x7fff) == insn2)) | |
252b5132 | 898 | fx->fix[i].operand |= 1024; |
e0c6ed95 | 899 | |
252b5132 | 900 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) |
e0c6ed95 | 901 | fx->fix[i].operand |= 4096; |
252b5132 RH |
902 | |
903 | fix_new_exp (frag_now, | |
e0c6ed95 | 904 | where, |
252b5132 RH |
905 | fx->fix[i].size, |
906 | &(fx->fix[i].exp), | |
907 | fx->fix[i].pcrel, | |
908 | fx->fix[i].operand|2048); | |
909 | } | |
910 | } | |
911 | fx->fc = 0; | |
912 | fx = fx->next; | |
913 | } | |
914 | return (0); | |
915 | } | |
916 | ||
e0c6ed95 AM |
917 | /* Check 2 instructions and determine if they can be safely |
918 | executed in parallel. Return 1 if they can be. */ | |
252b5132 | 919 | |
252b5132 RH |
920 | static int |
921 | parallel_ok (op1, insn1, op2, insn2, exec_type) | |
922 | struct d10v_opcode *op1, *op2; | |
923 | unsigned long insn1, insn2; | |
0a44c2b1 | 924 | packing_type exec_type; |
252b5132 RH |
925 | { |
926 | int i, j, flags, mask, shift, regno; | |
927 | unsigned long ins, mod[2], used[2]; | |
928 | struct d10v_opcode *op; | |
929 | ||
930 | if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0 | |
931 | || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0 | |
932 | || (op1->unit == BOTH) || (op2->unit == BOTH) | |
933 | || (op1->unit == IU && op2->unit == IU) | |
934 | || (op1->unit == MU && op2->unit == MU)) | |
935 | return 0; | |
936 | ||
0a44c2b1 | 937 | /* If this is auto parallization, and either instruction is a branch, |
e0c6ed95 | 938 | don't parallel. */ |
0a44c2b1 DL |
939 | if (exec_type == PACK_UNSPEC |
940 | && (op1->exec_type & ALONE || op2->exec_type & ALONE)) | |
252b5132 RH |
941 | return 0; |
942 | ||
943 | /* The idea here is to create two sets of bitmasks (mod and used) | |
944 | which indicate which registers are modified or used by each | |
945 | instruction. The operation can only be done in parallel if | |
946 | instruction 1 and instruction 2 modify different registers, and | |
947 | the first instruction does not modify registers that the second | |
948 | is using (The second instruction can modify registers that the | |
949 | first is using as they are only written back after the first | |
950 | instruction has completed). Accesses to control registers, PSW, | |
951 | and memory are treated as accesses to a single register. So if | |
952 | both instructions write memory or if the first instruction writes | |
953 | memory and the second reads, then they cannot be done in | |
954 | parallel. Likewise, if the first instruction mucks with the psw | |
955 | and the second reads the PSW (which includes C, F0, and F1), then | |
e0c6ed95 | 956 | they cannot operate safely in parallel. */ |
252b5132 | 957 | |
e0c6ed95 AM |
958 | /* The bitmasks (mod and used) look like this (bit 31 = MSB). */ |
959 | /* r0-r15 0-15 */ | |
960 | /* a0-a1 16-17 */ | |
961 | /* cr (not psw) 18 */ | |
962 | /* psw 19 */ | |
963 | /* mem 20 */ | |
252b5132 | 964 | |
e0c6ed95 | 965 | for (j = 0; j < 2; j++) |
252b5132 RH |
966 | { |
967 | if (j == 0) | |
968 | { | |
969 | op = op1; | |
970 | ins = insn1; | |
971 | } | |
972 | else | |
973 | { | |
974 | op = op2; | |
975 | ins = insn2; | |
976 | } | |
977 | mod[j] = used[j] = 0; | |
978 | if (op->exec_type & BRANCH_LINK) | |
979 | mod[j] |= 1 << 13; | |
980 | ||
981 | for (i = 0; op->operands[i]; i++) | |
982 | { | |
983 | flags = d10v_operands[op->operands[i]].flags; | |
984 | shift = d10v_operands[op->operands[i]].shift; | |
985 | mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); | |
986 | if (flags & OPERAND_REG) | |
987 | { | |
988 | regno = (ins >> shift) & mask; | |
e0c6ed95 | 989 | if (flags & (OPERAND_ACC0 | OPERAND_ACC1)) |
252b5132 | 990 | regno += 16; |
e0c6ed95 AM |
991 | else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */ |
992 | { | |
252b5132 RH |
993 | if (regno == 0) |
994 | regno = 19; | |
995 | else | |
e0c6ed95 | 996 | regno = 18; |
252b5132 | 997 | } |
e0c6ed95 | 998 | else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG)) |
252b5132 | 999 | regno = 19; |
e0c6ed95 AM |
1000 | |
1001 | if (flags & OPERAND_DEST) | |
252b5132 RH |
1002 | { |
1003 | mod[j] |= 1 << regno; | |
1004 | if (flags & OPERAND_EVEN) | |
1005 | mod[j] |= 1 << (regno + 1); | |
1006 | } | |
1007 | else | |
1008 | { | |
e0c6ed95 | 1009 | used[j] |= 1 << regno; |
252b5132 RH |
1010 | if (flags & OPERAND_EVEN) |
1011 | used[j] |= 1 << (regno + 1); | |
1012 | ||
1013 | /* Auto inc/dec also modifies the register. */ | |
e0c6ed95 AM |
1014 | if (op->operands[i + 1] != 0 |
1015 | && (d10v_operands[op->operands[i + 1]].flags | |
252b5132 RH |
1016 | & (OPERAND_PLUS | OPERAND_MINUS)) != 0) |
1017 | mod[j] |= 1 << regno; | |
1018 | } | |
1019 | } | |
1020 | else if (flags & OPERAND_ATMINUS) | |
1021 | { | |
e0c6ed95 | 1022 | /* SP implicitly used/modified. */ |
252b5132 RH |
1023 | mod[j] |= 1 << 15; |
1024 | used[j] |= 1 << 15; | |
1025 | } | |
1026 | } | |
1027 | if (op->exec_type & RMEM) | |
1028 | used[j] |= 1 << 20; | |
1029 | else if (op->exec_type & WMEM) | |
1030 | mod[j] |= 1 << 20; | |
1031 | else if (op->exec_type & RF0) | |
1032 | used[j] |= 1 << 19; | |
1033 | else if (op->exec_type & WF0) | |
1034 | mod[j] |= 1 << 19; | |
1035 | else if (op->exec_type & WCAR) | |
1036 | mod[j] |= 1 << 19; | |
1037 | } | |
1038 | if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0) | |
1039 | return 1; | |
1040 | return 0; | |
1041 | } | |
1042 | ||
e0c6ed95 AM |
1043 | /* This is the main entry point for the machine-dependent assembler. |
1044 | STR points to a machine-dependent instruction. This function is | |
1045 | supposed to emit the frags/bytes it assembles to. For the D10V, it | |
1046 | mostly handles the special VLIW parsing and packing and leaves the | |
1047 | difficult stuff to do_assemble(). */ | |
252b5132 RH |
1048 | |
1049 | static unsigned long prev_insn; | |
1050 | static struct d10v_opcode *prev_opcode = 0; | |
1051 | static subsegT prev_subseg; | |
1052 | static segT prev_seg = 0;; | |
252b5132 RH |
1053 | |
1054 | void | |
1055 | md_assemble (str) | |
1056 | char *str; | |
1057 | { | |
e0c6ed95 | 1058 | /* etype is saved extype. For multi-line instructions. */ |
0a44c2b1 | 1059 | |
e0c6ed95 | 1060 | packing_type extype = PACK_UNSPEC; /* Parallel, etc. */ |
0a44c2b1 | 1061 | |
e0c6ed95 | 1062 | struct d10v_opcode *opcode; |
252b5132 | 1063 | unsigned long insn; |
e0c6ed95 | 1064 | char *str2; |
252b5132 | 1065 | |
0a44c2b1 | 1066 | if (etype == PACK_UNSPEC) |
252b5132 | 1067 | { |
e0c6ed95 | 1068 | /* Look for the special multiple instruction separators. */ |
252b5132 | 1069 | str2 = strstr (str, "||"); |
e0c6ed95 | 1070 | if (str2) |
0a44c2b1 | 1071 | extype = PACK_PARALLEL; |
252b5132 RH |
1072 | else |
1073 | { | |
1074 | str2 = strstr (str, "->"); | |
e0c6ed95 | 1075 | if (str2) |
0a44c2b1 | 1076 | extype = PACK_LEFT_RIGHT; |
252b5132 RH |
1077 | else |
1078 | { | |
1079 | str2 = strstr (str, "<-"); | |
e0c6ed95 | 1080 | if (str2) |
0a44c2b1 | 1081 | extype = PACK_RIGHT_LEFT; |
252b5132 RH |
1082 | } |
1083 | } | |
e0c6ed95 AM |
1084 | /* STR2 points to the separator, if there is one. */ |
1085 | if (str2) | |
252b5132 RH |
1086 | { |
1087 | *str2 = 0; | |
e0c6ed95 AM |
1088 | |
1089 | /* If two instructions are present and we already have one saved, | |
1090 | then first write out the saved one. */ | |
252b5132 | 1091 | d10v_cleanup (); |
e0c6ed95 AM |
1092 | |
1093 | /* Assemble first instruction and save it. */ | |
252b5132 | 1094 | prev_insn = do_assemble (str, &prev_opcode); |
3cd4dda7 DD |
1095 | prev_seg = now_seg; |
1096 | prev_subseg = now_subseg; | |
bccba5f0 | 1097 | if (prev_insn == (unsigned long) -1) |
252b5132 RH |
1098 | as_fatal (_("can't find opcode ")); |
1099 | fixups = fixups->next; | |
1100 | str = str2 + 2; | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | insn = do_assemble (str, &opcode); | |
bccba5f0 | 1105 | if (insn == (unsigned long) -1) |
252b5132 | 1106 | { |
0a44c2b1 | 1107 | if (extype != PACK_UNSPEC) |
252b5132 RH |
1108 | { |
1109 | etype = extype; | |
1110 | return; | |
1111 | } | |
1112 | as_fatal (_("can't find opcode ")); | |
1113 | } | |
1114 | ||
0a44c2b1 | 1115 | if (etype != PACK_UNSPEC) |
252b5132 RH |
1116 | { |
1117 | extype = etype; | |
0a44c2b1 | 1118 | etype = PACK_UNSPEC; |
252b5132 RH |
1119 | } |
1120 | ||
e0c6ed95 AM |
1121 | /* If this is a long instruction, write it and any previous short |
1122 | instruction. */ | |
1123 | if (opcode->format & LONG_OPCODE) | |
252b5132 | 1124 | { |
e0c6ed95 | 1125 | if (extype != PACK_UNSPEC) |
252b5132 RH |
1126 | as_fatal (_("Unable to mix instructions as specified")); |
1127 | d10v_cleanup (); | |
bccba5f0 | 1128 | write_long (insn, fixups); |
252b5132 RH |
1129 | prev_opcode = NULL; |
1130 | return; | |
1131 | } | |
e0c6ed95 AM |
1132 | |
1133 | if (prev_opcode | |
1134 | && prev_seg | |
1135 | && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
0a44c2b1 | 1136 | d10v_cleanup (); |
e0c6ed95 AM |
1137 | |
1138 | if (prev_opcode | |
1139 | && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0)) | |
252b5132 | 1140 | { |
e0c6ed95 | 1141 | /* No instructions saved. */ |
252b5132 RH |
1142 | prev_opcode = NULL; |
1143 | } | |
1144 | else | |
1145 | { | |
e0c6ed95 | 1146 | if (extype != PACK_UNSPEC) |
252b5132 | 1147 | as_fatal (_("Unable to mix instructions as specified")); |
e0c6ed95 | 1148 | /* Save last instruction so it may be packed on next pass. */ |
252b5132 RH |
1149 | prev_opcode = opcode; |
1150 | prev_insn = insn; | |
1151 | prev_seg = now_seg; | |
1152 | prev_subseg = now_subseg; | |
1153 | fixups = fixups->next; | |
1154 | } | |
1155 | } | |
1156 | ||
e0c6ed95 AM |
1157 | /* Assemble a single instruction. |
1158 | Return an opcode, or -1 (an invalid opcode) on error. */ | |
252b5132 RH |
1159 | |
1160 | static unsigned long | |
e0c6ed95 | 1161 | do_assemble (str, opcode) |
252b5132 RH |
1162 | char *str; |
1163 | struct d10v_opcode **opcode; | |
1164 | { | |
1165 | unsigned char *op_start, *save; | |
1166 | unsigned char *op_end; | |
1167 | char name[20]; | |
1168 | int nlen = 0; | |
1169 | expressionS myops[6]; | |
1170 | unsigned long insn; | |
1171 | ||
1172 | /* Drop leading whitespace. */ | |
1173 | while (*str == ' ') | |
1174 | str++; | |
1175 | ||
1176 | /* Find the opcode end. */ | |
1177 | for (op_start = op_end = (unsigned char *) (str); | |
1178 | *op_end | |
1179 | && nlen < 20 | |
1180 | && !is_end_of_line[*op_end] && *op_end != ' '; | |
1181 | op_end++) | |
1182 | { | |
3882b010 | 1183 | name[nlen] = TOLOWER (op_start[nlen]); |
252b5132 RH |
1184 | nlen++; |
1185 | } | |
1186 | name[nlen] = 0; | |
1187 | ||
1188 | if (nlen == 0) | |
1189 | return -1; | |
e0c6ed95 | 1190 | |
252b5132 | 1191 | /* Find the first opcode with the proper name. */ |
e0c6ed95 | 1192 | *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name); |
252b5132 | 1193 | if (*opcode == NULL) |
e0c6ed95 | 1194 | as_fatal (_("unknown opcode: %s"), name); |
252b5132 RH |
1195 | |
1196 | save = input_line_pointer; | |
1197 | input_line_pointer = op_end; | |
1198 | *opcode = find_opcode (*opcode, myops); | |
1199 | if (*opcode == 0) | |
1200 | return -1; | |
1201 | input_line_pointer = save; | |
1202 | ||
e0c6ed95 | 1203 | insn = build_insn ((*opcode), myops, 0); |
252b5132 RH |
1204 | return (insn); |
1205 | } | |
1206 | ||
e0c6ed95 AM |
1207 | /* Find the symbol which has the same name as the register in EXP. */ |
1208 | ||
252b5132 RH |
1209 | static symbolS * |
1210 | find_symbol_matching_register (exp) | |
e0c6ed95 | 1211 | expressionS *exp; |
252b5132 RH |
1212 | { |
1213 | int i; | |
e0c6ed95 | 1214 | |
252b5132 RH |
1215 | if (exp->X_op != O_register) |
1216 | return NULL; | |
e0c6ed95 | 1217 | |
252b5132 RH |
1218 | /* Find the name of the register. */ |
1219 | for (i = d10v_reg_name_cnt (); i--;) | |
e0c6ed95 | 1220 | if (d10v_predefined_registers[i].value == exp->X_add_number) |
252b5132 RH |
1221 | break; |
1222 | ||
1223 | if (i < 0) | |
1224 | abort (); | |
1225 | ||
1226 | /* Now see if a symbol has been defined with the same name. */ | |
e0c6ed95 | 1227 | return symbol_find (d10v_predefined_registers[i].name); |
252b5132 RH |
1228 | } |
1229 | ||
e0c6ed95 AM |
1230 | /* Get a pointer to an entry in the opcode table. |
1231 | The function must look at all opcodes with the same name and use | |
1232 | the operands to choose the correct opcode. */ | |
252b5132 RH |
1233 | |
1234 | static struct d10v_opcode * | |
1235 | find_opcode (opcode, myops) | |
1236 | struct d10v_opcode *opcode; | |
1237 | expressionS myops[]; | |
1238 | { | |
bccba5f0 | 1239 | int i, match; |
252b5132 RH |
1240 | struct d10v_opcode *next_opcode; |
1241 | ||
e0c6ed95 | 1242 | /* Get all the operands and save them as expressions. */ |
252b5132 RH |
1243 | get_operands (myops); |
1244 | ||
e0c6ed95 AM |
1245 | /* Now see if the operand is a fake. If so, find the correct size |
1246 | instruction, if possible. */ | |
252b5132 RH |
1247 | if (opcode->format == OPCODE_FAKE) |
1248 | { | |
1249 | int opnum = opcode->operands[0]; | |
1250 | int flags; | |
e0c6ed95 | 1251 | |
252b5132 RH |
1252 | if (myops[opnum].X_op == O_register) |
1253 | { | |
1254 | myops[opnum].X_op = O_symbol; | |
e0c6ed95 AM |
1255 | myops[opnum].X_add_symbol = |
1256 | symbol_find_or_make ((char *) myops[opnum].X_op_symbol); | |
252b5132 RH |
1257 | myops[opnum].X_add_number = 0; |
1258 | myops[opnum].X_op_symbol = NULL; | |
1259 | } | |
1260 | ||
e0c6ed95 | 1261 | next_opcode = opcode + 1; |
252b5132 RH |
1262 | |
1263 | /* If the first operand is supposed to be a register, make sure | |
1264 | we got a valid one. */ | |
1265 | flags = d10v_operands[next_opcode->operands[0]].flags; | |
1266 | if (flags & OPERAND_REG) | |
1267 | { | |
1268 | int X_op = myops[0].X_op; | |
1269 | int num = myops[0].X_add_number; | |
1270 | ||
1271 | if (X_op != O_register | |
1272 | || (num & ~flags | |
1273 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 | |
55aa1bc4 AO |
1274 | | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)) |
1275 | || ((flags & OPERAND_SP) && ! (num & OPERAND_SP))) | |
252b5132 RH |
1276 | { |
1277 | as_bad (_("bad opcode or operands")); | |
1278 | return 0; | |
1279 | } | |
1280 | } | |
1281 | ||
e0c6ed95 AM |
1282 | if (myops[opnum].X_op == O_constant |
1283 | || (myops[opnum].X_op == O_symbol | |
1284 | && S_IS_DEFINED (myops[opnum].X_add_symbol) | |
1285 | && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg))) | |
252b5132 | 1286 | { |
e0c6ed95 | 1287 | for (i = 0; opcode->operands[i + 1]; i++) |
252b5132 RH |
1288 | { |
1289 | int bits = d10v_operands[next_opcode->operands[opnum]].bits; | |
1290 | int flags = d10v_operands[next_opcode->operands[opnum]].flags; | |
1291 | if (flags & OPERAND_ADDR) | |
1292 | bits += 2; | |
e0c6ed95 | 1293 | |
252b5132 RH |
1294 | if (myops[opnum].X_op == O_constant) |
1295 | { | |
1296 | if (!check_range (myops[opnum].X_add_number, bits, flags)) | |
1297 | return next_opcode; | |
1298 | } | |
1299 | else | |
1300 | { | |
e0c6ed95 AM |
1301 | fragS *sym_frag; |
1302 | fragS *f; | |
3db10f32 NC |
1303 | unsigned long current_position; |
1304 | unsigned long symbol_position; | |
1305 | unsigned long value; | |
1306 | boolean found_symbol; | |
e0c6ed95 | 1307 | |
3db10f32 NC |
1308 | /* Calculate the address of the current instruction |
1309 | and the address of the symbol. Do this by summing | |
1310 | the offsets of previous frags until we reach the | |
1311 | frag containing the symbol, and the current frag. */ | |
1312 | sym_frag = symbol_get_frag (myops[opnum].X_add_symbol); | |
1313 | found_symbol = false; | |
1314 | ||
e0c6ed95 AM |
1315 | current_position = |
1316 | obstack_next_free (&frchain_now->frch_obstack) | |
1317 | - frag_now->fr_literal; | |
3db10f32 | 1318 | symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol); |
e0c6ed95 | 1319 | |
3db10f32 NC |
1320 | for (f = frchain_now->frch_root; f; f = f->fr_next) |
1321 | { | |
1322 | current_position += f->fr_fix + f->fr_offset; | |
e0c6ed95 | 1323 | |
3db10f32 NC |
1324 | if (f == sym_frag) |
1325 | found_symbol = true; | |
e0c6ed95 | 1326 | |
3db10f32 NC |
1327 | if (! found_symbol) |
1328 | symbol_position += f->fr_fix + f->fr_offset; | |
1329 | } | |
252b5132 | 1330 | |
3db10f32 | 1331 | value = symbol_position; |
e0c6ed95 | 1332 | |
252b5132 | 1333 | if (flags & OPERAND_ADDR) |
3db10f32 | 1334 | value -= current_position; |
e0c6ed95 | 1335 | |
252b5132 RH |
1336 | if (AT_WORD_P (&myops[opnum])) |
1337 | { | |
1338 | if (bits > 4) | |
1339 | { | |
1340 | bits += 2; | |
1341 | if (!check_range (value, bits, flags)) | |
1342 | return next_opcode; | |
1343 | } | |
1344 | } | |
1345 | else if (!check_range (value, bits, flags)) | |
1346 | return next_opcode; | |
1347 | } | |
1348 | next_opcode++; | |
1349 | } | |
1350 | as_fatal (_("value out of range")); | |
1351 | } | |
1352 | else | |
1353 | { | |
e0c6ed95 AM |
1354 | /* Not a constant, so use a long instruction. */ |
1355 | return opcode + 2; | |
252b5132 RH |
1356 | } |
1357 | } | |
1358 | else | |
1359 | { | |
1360 | match = 0; | |
e0c6ed95 AM |
1361 | /* Now search the opcode table table for one with operands |
1362 | that matches what we've got. */ | |
252b5132 RH |
1363 | while (!match) |
1364 | { | |
1365 | match = 1; | |
e0c6ed95 | 1366 | for (i = 0; opcode->operands[i]; i++) |
252b5132 RH |
1367 | { |
1368 | int flags = d10v_operands[opcode->operands[i]].flags; | |
1369 | int X_op = myops[i].X_op; | |
1370 | int num = myops[i].X_add_number; | |
1371 | ||
1372 | if (X_op == 0) | |
1373 | { | |
1374 | match = 0; | |
1375 | break; | |
1376 | } | |
e0c6ed95 | 1377 | |
252b5132 RH |
1378 | if (flags & OPERAND_REG) |
1379 | { | |
1380 | if ((X_op != O_register) | |
1381 | || (num & ~flags | |
1382 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 | |
1383 | | OPERAND_FFLAG | OPERAND_CFLAG | |
55aa1bc4 AO |
1384 | | OPERAND_CONTROL)) |
1385 | || ((flags & OPERAND_SP) && ! (num & OPERAND_SP))) | |
252b5132 RH |
1386 | { |
1387 | match = 0; | |
1388 | break; | |
1389 | } | |
1390 | } | |
e0c6ed95 | 1391 | |
252b5132 RH |
1392 | if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) || |
1393 | ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) || | |
1394 | ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) || | |
1395 | ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) || | |
d9fd9852 | 1396 | ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR))))) |
252b5132 RH |
1397 | { |
1398 | match = 0; | |
1399 | break; | |
1400 | } | |
e0c6ed95 AM |
1401 | |
1402 | /* Unfortunatly, for the indirect operand in | |
1403 | instructions such as ``ldb r1, @(c,r14)'' this | |
1404 | function can be passed X_op == O_register (because | |
1405 | 'c' is a valid register name). However we cannot | |
1406 | just ignore the case when X_op == O_register but | |
1407 | flags & OPERAND_REG is null, so we check to see if a | |
1408 | symbol of the same name as the register exists. If | |
1409 | the symbol does exist, then the parser was unable to | |
1410 | distinguish the two cases and we fix things here. | |
1411 | (Ref: PR14826) */ | |
1412 | ||
252b5132 RH |
1413 | if (!(flags & OPERAND_REG) && (X_op == O_register)) |
1414 | { | |
e0c6ed95 AM |
1415 | symbolS *sym = find_symbol_matching_register (&myops[i]); |
1416 | ||
252b5132 RH |
1417 | if (sym != NULL) |
1418 | { | |
e0c6ed95 AM |
1419 | myops[i].X_op = X_op = O_symbol; |
1420 | myops[i].X_add_symbol = sym; | |
252b5132 RH |
1421 | } |
1422 | else | |
1423 | as_bad | |
1424 | (_("illegal operand - register name found where none expected")); | |
1425 | } | |
1426 | } | |
e0c6ed95 | 1427 | |
252b5132 RH |
1428 | /* We're only done if the operands matched so far AND there |
1429 | are no more to check. */ | |
e0c6ed95 | 1430 | if (match && myops[i].X_op == 0) |
252b5132 RH |
1431 | break; |
1432 | else | |
1433 | match = 0; | |
1434 | ||
1435 | next_opcode = opcode + 1; | |
e0c6ed95 AM |
1436 | |
1437 | if (next_opcode->opcode == 0) | |
252b5132 | 1438 | break; |
e0c6ed95 | 1439 | |
252b5132 RH |
1440 | if (strcmp (next_opcode->name, opcode->name)) |
1441 | break; | |
e0c6ed95 | 1442 | |
252b5132 RH |
1443 | opcode = next_opcode; |
1444 | } | |
1445 | } | |
1446 | ||
e0c6ed95 | 1447 | if (!match) |
252b5132 RH |
1448 | { |
1449 | as_bad (_("bad opcode or operands")); | |
1450 | return (0); | |
1451 | } | |
1452 | ||
e0c6ed95 AM |
1453 | /* Check that all registers that are required to be even are. |
1454 | Also, if any operands were marked as registers, but were really symbols, | |
1455 | fix that here. */ | |
1456 | for (i = 0; opcode->operands[i]; i++) | |
252b5132 RH |
1457 | { |
1458 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) && | |
e0c6ed95 | 1459 | (myops[i].X_add_number & 1)) |
252b5132 | 1460 | as_fatal (_("Register number must be EVEN")); |
461448d8 AO |
1461 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_NOSP) |
1462 | && (myops[i].X_add_number & OPERAND_SP)) | |
1463 | as_bad (_("Unsupported use of sp")); | |
252b5132 RH |
1464 | if (myops[i].X_op == O_register) |
1465 | { | |
e0c6ed95 | 1466 | if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG)) |
252b5132 RH |
1467 | { |
1468 | myops[i].X_op = O_symbol; | |
e0c6ed95 AM |
1469 | myops[i].X_add_symbol = |
1470 | symbol_find_or_make ((char *) myops[i].X_op_symbol); | |
252b5132 RH |
1471 | myops[i].X_add_number = 0; |
1472 | myops[i].X_op_symbol = NULL; | |
1473 | } | |
1474 | } | |
1475 | } | |
1476 | return opcode; | |
1477 | } | |
1478 | ||
e0c6ed95 AM |
1479 | /* If while processing a fixup, a reloc really needs to be created. |
1480 | Then it is done here. */ | |
1481 | ||
252b5132 RH |
1482 | arelent * |
1483 | tc_gen_reloc (seg, fixp) | |
bccba5f0 | 1484 | asection *seg ATTRIBUTE_UNUSED; |
252b5132 RH |
1485 | fixS *fixp; |
1486 | { | |
1487 | arelent *reloc; | |
1488 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
310b5aa2 ILT |
1489 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
1490 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
1491 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
1492 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
1493 | if (reloc->howto == (reloc_howto_type *) NULL) | |
1494 | { | |
1495 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
e0c6ed95 AM |
1496 | _("reloc %d not supported by object file format"), |
1497 | (int) fixp->fx_r_type); | |
252b5132 RH |
1498 | return NULL; |
1499 | } | |
1500 | ||
1501 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1502 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1503 | reloc->address = fixp->fx_offset; | |
1504 | ||
1505 | reloc->addend = fixp->fx_addnumber; | |
1506 | ||
1507 | return reloc; | |
1508 | } | |
1509 | ||
1510 | int | |
1511 | md_estimate_size_before_relax (fragp, seg) | |
bccba5f0 NC |
1512 | fragS *fragp ATTRIBUTE_UNUSED; |
1513 | asection *seg ATTRIBUTE_UNUSED; | |
252b5132 RH |
1514 | { |
1515 | abort (); | |
1516 | return 0; | |
e0c6ed95 | 1517 | } |
252b5132 RH |
1518 | |
1519 | long | |
1520 | md_pcrel_from_section (fixp, sec) | |
1521 | fixS *fixp; | |
1522 | segT sec; | |
1523 | { | |
e0c6ed95 AM |
1524 | if (fixp->fx_addsy != (symbolS *) NULL |
1525 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
1526 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
252b5132 RH |
1527 | return 0; |
1528 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1529 | } | |
1530 | ||
94f592af NC |
1531 | void |
1532 | md_apply_fix3 (fixP, valP, seg) | |
1533 | fixS *fixP; | |
1534 | valueT * valP; | |
bccba5f0 | 1535 | segT seg ATTRIBUTE_UNUSED; |
252b5132 RH |
1536 | { |
1537 | char *where; | |
1538 | unsigned long insn; | |
94f592af | 1539 | long value = * (long *) valP; |
252b5132 | 1540 | int op_type; |
e0c6ed95 | 1541 | int left = 0; |
252b5132 | 1542 | |
94f592af NC |
1543 | if (fixP->fx_addsy == (symbolS *) NULL) |
1544 | fixP->fx_done = 1; | |
1545 | ||
1546 | else if (fixP->fx_pcrel) | |
1547 | ; | |
1548 | ||
252b5132 RH |
1549 | else |
1550 | { | |
94f592af NC |
1551 | value = fixP->fx_offset; |
1552 | ||
1553 | if (fixP->fx_subsy != (symbolS *) NULL) | |
252b5132 | 1554 | { |
94f592af NC |
1555 | if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) |
1556 | value -= S_GET_VALUE (fixP->fx_subsy); | |
252b5132 RH |
1557 | else |
1558 | { | |
1559 | /* We don't actually support subtracting a symbol. */ | |
94f592af | 1560 | as_bad_where (fixP->fx_file, fixP->fx_line, |
252b5132 RH |
1561 | _("expression too complex")); |
1562 | } | |
1563 | } | |
1564 | } | |
1565 | ||
94f592af | 1566 | op_type = fixP->fx_r_type; |
252b5132 RH |
1567 | if (op_type & 2048) |
1568 | { | |
1569 | op_type -= 2048; | |
1570 | if (op_type & 1024) | |
1571 | { | |
1572 | op_type -= 1024; | |
94f592af | 1573 | fixP->fx_r_type = BFD_RELOC_D10V_10_PCREL_L; |
252b5132 RH |
1574 | left = 1; |
1575 | } | |
1576 | else if (op_type & 4096) | |
1577 | { | |
1578 | op_type -= 4096; | |
94f592af | 1579 | fixP->fx_r_type = BFD_RELOC_D10V_18; |
252b5132 RH |
1580 | } |
1581 | else | |
94f592af | 1582 | fixP->fx_r_type = |
e0c6ed95 | 1583 | get_reloc ((struct d10v_operand *) &d10v_operands[op_type]); |
252b5132 RH |
1584 | } |
1585 | ||
1586 | /* Fetch the instruction, insert the fully resolved operand | |
1587 | value, and stuff the instruction back again. */ | |
94f592af | 1588 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
1589 | insn = bfd_getb32 ((unsigned char *) where); |
1590 | ||
94f592af | 1591 | switch (fixP->fx_r_type) |
252b5132 RH |
1592 | { |
1593 | case BFD_RELOC_D10V_10_PCREL_L: | |
1594 | case BFD_RELOC_D10V_10_PCREL_R: | |
1595 | case BFD_RELOC_D10V_18_PCREL: | |
1596 | case BFD_RELOC_D10V_18: | |
e0c6ed95 | 1597 | /* Instruction addresses are always right-shifted by 2. */ |
252b5132 | 1598 | value >>= AT_WORD_RIGHT_SHIFT; |
94f592af | 1599 | if (fixP->fx_size == 2) |
252b5132 RH |
1600 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); |
1601 | else | |
1602 | { | |
1603 | struct d10v_opcode *rep, *repi; | |
1604 | ||
1605 | rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep"); | |
1606 | repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi"); | |
1607 | if ((insn & FM11) == FM11 | |
bccba5f0 NC |
1608 | && ( (repi != NULL && (insn & repi->mask) == (unsigned) repi->opcode) |
1609 | || (rep != NULL && (insn & rep->mask) == (unsigned) rep->opcode)) | |
252b5132 RH |
1610 | && value < 4) |
1611 | as_fatal | |
1612 | (_("line %d: rep or repi must include at least 4 instructions"), | |
94f592af | 1613 | fixP->fx_line); |
e0c6ed95 | 1614 | insn = |
94f592af | 1615 | d10v_insert_operand (insn, op_type, (offsetT) value, left, fixP); |
e0c6ed95 | 1616 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); |
252b5132 RH |
1617 | } |
1618 | break; | |
1619 | case BFD_RELOC_32: | |
1620 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
1621 | break; | |
1622 | case BFD_RELOC_16: | |
1623 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1624 | break; | |
1625 | ||
1626 | case BFD_RELOC_VTABLE_INHERIT: | |
1627 | case BFD_RELOC_VTABLE_ENTRY: | |
94f592af NC |
1628 | fixP->fx_done = 0; |
1629 | return; | |
252b5132 RH |
1630 | |
1631 | default: | |
e0c6ed95 | 1632 | as_fatal (_("line %d: unknown relocation type: 0x%x"), |
94f592af | 1633 | fixP->fx_line, fixP->fx_r_type); |
252b5132 | 1634 | } |
252b5132 RH |
1635 | } |
1636 | ||
bccba5f0 NC |
1637 | /* d10v_cleanup() is called after the assembler has finished parsing |
1638 | the input file, when a label is read from the input file, or when a | |
1639 | stab directive is output. Because the D10V assembler sometimes | |
e0c6ed95 AM |
1640 | saves short instructions to see if it can package them with the |
1641 | next instruction, there may be a short instruction that still needs | |
1642 | to be written. | |
1643 | ||
0a44c2b1 DL |
1644 | NOTE: accesses a global, etype. |
1645 | NOTE: invoked by various macros such as md_cleanup: see. */ | |
e0c6ed95 | 1646 | |
252b5132 RH |
1647 | int |
1648 | d10v_cleanup () | |
1649 | { | |
1650 | segT seg; | |
1651 | subsegT subseg; | |
1652 | ||
bccba5f0 NC |
1653 | /* If cleanup was invoked because the assembler encountered, e.g., a |
1654 | user label, we write out the pending instruction, if any. If it | |
1655 | was invoked because the assembler is outputting a piece of line | |
1656 | debugging information, though, we write out the pending | |
1657 | instruction only if the --no-gstabs-packing command line switch | |
1658 | has been specified. */ | |
1659 | if (prev_opcode | |
1660 | && etype == PACK_UNSPEC | |
1661 | && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing)) | |
252b5132 RH |
1662 | { |
1663 | seg = now_seg; | |
1664 | subseg = now_subseg; | |
bccba5f0 | 1665 | |
252b5132 RH |
1666 | if (prev_seg) |
1667 | subseg_set (prev_seg, prev_subseg); | |
bccba5f0 | 1668 | |
252b5132 | 1669 | write_1_short (prev_opcode, prev_insn, fixups->next); |
bccba5f0 | 1670 | |
252b5132 RH |
1671 | subseg_set (seg, subseg); |
1672 | prev_opcode = NULL; | |
1673 | } | |
1674 | return 1; | |
1675 | } | |
1676 | ||
e0c6ed95 AM |
1677 | /* Like normal .word, except support @word. */ |
1678 | /* Clobbers input_line_pointer, checks end-of-line. */ | |
1679 | ||
252b5132 | 1680 | static void |
bccba5f0 NC |
1681 | d10v_dot_word (dummy) |
1682 | int dummy ATTRIBUTE_UNUSED; | |
252b5132 RH |
1683 | { |
1684 | expressionS exp; | |
252b5132 | 1685 | char *p; |
252b5132 RH |
1686 | |
1687 | if (is_it_end_of_statement ()) | |
1688 | { | |
1689 | demand_empty_rest_of_line (); | |
1690 | return; | |
1691 | } | |
1692 | ||
1693 | do | |
1694 | { | |
1695 | expression (&exp); | |
1696 | if (!strncasecmp (input_line_pointer, "@word", 5)) | |
1697 | { | |
1698 | exp.X_add_number = 0; | |
1699 | input_line_pointer += 5; | |
e0c6ed95 | 1700 | |
252b5132 | 1701 | p = frag_more (2); |
e0c6ed95 | 1702 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, |
252b5132 RH |
1703 | &exp, 0, BFD_RELOC_D10V_18); |
1704 | } | |
1705 | else | |
1706 | emit_expr (&exp, 2); | |
1707 | } | |
1708 | while (*input_line_pointer++ == ','); | |
1709 | ||
e0c6ed95 | 1710 | input_line_pointer--; /* Put terminator back into stream. */ |
252b5132 RH |
1711 | demand_empty_rest_of_line (); |
1712 | } | |
1713 | ||
e0c6ed95 AM |
1714 | /* Mitsubishi asked that we support some old syntax that apparently |
1715 | had immediate operands starting with '#'. This is in some of their | |
1716 | sample code but is not documented (although it appears in some | |
1717 | examples in their assembler manual). For now, we'll solve this | |
1718 | compatibility problem by simply ignoring any '#' at the beginning | |
1719 | of an operand. */ | |
252b5132 | 1720 | |
e0c6ed95 AM |
1721 | /* Operands that begin with '#' should fall through to here. */ |
1722 | /* From expr.c. */ | |
252b5132 | 1723 | |
e0c6ed95 | 1724 | void |
252b5132 RH |
1725 | md_operand (expressionP) |
1726 | expressionS *expressionP; | |
1727 | { | |
0f94f4c8 | 1728 | if (*input_line_pointer == '#' && ! do_not_ignore_hash) |
252b5132 RH |
1729 | { |
1730 | input_line_pointer++; | |
1731 | expression (expressionP); | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | boolean | |
1736 | d10v_fix_adjustable (fixP) | |
e0c6ed95 | 1737 | fixS *fixP; |
252b5132 | 1738 | { |
252b5132 RH |
1739 | if (fixP->fx_addsy == NULL) |
1740 | return 1; | |
e0c6ed95 AM |
1741 | |
1742 | /* Prevent all adjustments to global symbols. */ | |
252b5132 RH |
1743 | if (S_IS_EXTERN (fixP->fx_addsy)) |
1744 | return 0; | |
1745 | if (S_IS_WEAK (fixP->fx_addsy)) | |
1746 | return 0; | |
1747 | ||
e0c6ed95 | 1748 | /* We need the symbol name for the VTABLE entries. */ |
252b5132 RH |
1749 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1750 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1751 | return 0; | |
1752 | ||
1753 | return 1; | |
1754 | } | |
1755 | ||
1756 | int | |
1757 | d10v_force_relocation (fixp) | |
e0c6ed95 | 1758 | fixS *fixp; |
252b5132 RH |
1759 | { |
1760 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1761 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1762 | return 1; | |
1763 | ||
1764 | return 0; | |
1765 | } |