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252b5132 | 1 | /* tc-d30v.c -- Assembler code for the Mitsubishi D30V |
49309057 | 2 | Copyright (C) 1997, 1998, 1999 Free Software Foundation. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include <ctype.h> | |
23 | #include "as.h" | |
24 | #include "subsegs.h" | |
25 | #include "opcode/d30v.h" | |
26 | ||
27 | const char comment_chars[] = ";"; | |
28 | const char line_comment_chars[] = "#"; | |
29 | const char line_separator_chars[] = ""; | |
30 | const char *md_shortopts = "OnNcC"; | |
31 | const char EXP_CHARS[] = "eE"; | |
32 | const char FLT_CHARS[] = "dD"; | |
33 | ||
ba09cd8d DN |
34 | #if HAVE_LIMITS_H |
35 | #include <limits.h> | |
36 | #endif | |
37 | ||
38 | #ifndef CHAR_BIT | |
39 | #define CHAR_BIT 8 | |
40 | #endif | |
41 | ||
252b5132 RH |
42 | #define NOP_MULTIPLY 1 |
43 | #define NOP_ALL 2 | |
44 | static int warn_nops = 0; | |
45 | static int Optimizing = 0; | |
46 | static int warn_register_name_conflicts = 1; | |
47 | ||
48 | #define FORCE_SHORT 1 | |
49 | #define FORCE_LONG 2 | |
50 | ||
51 | /* EXEC types. */ | |
52 | typedef enum _exec_type | |
53 | { | |
54 | EXEC_UNKNOWN, /* no order specified */ | |
55 | EXEC_PARALLEL, /* done in parallel (FM=00) */ | |
56 | EXEC_SEQ, /* sequential (FM=01) */ | |
57 | EXEC_REVSEQ /* reverse sequential (FM=10) */ | |
58 | } exec_type_enum; | |
59 | ||
60 | /* fixups */ | |
61 | #define MAX_INSN_FIXUPS (5) | |
62 | struct d30v_fixup | |
63 | { | |
64 | expressionS exp; | |
65 | int operand; | |
66 | int pcrel; | |
67 | int size; | |
68 | bfd_reloc_code_real_type reloc; | |
69 | }; | |
70 | ||
71 | typedef struct _fixups | |
72 | { | |
73 | int fc; | |
74 | struct d30v_fixup fix[MAX_INSN_FIXUPS]; | |
75 | struct _fixups *next; | |
76 | } Fixups; | |
77 | ||
78 | static Fixups FixUps[2]; | |
79 | static Fixups *fixups; | |
80 | ||
81 | /* Whether current and previous instruction are word multiply insns. */ | |
82 | static int cur_mul32_p = 0; | |
83 | static int prev_mul32_p = 0; | |
84 | ||
85 | /* The flag_explicitly_parallel is true iff the instruction being assembled | |
86 | has been explicitly written as a parallel short-instruction pair by the | |
87 | human programmer. It is used in parallel_ok() to distinguish between | |
88 | those dangerous parallelizations attempted by the human, which are to be | |
89 | allowed, and those attempted by the assembler, which are not. It is set | |
90 | from md_assemble(). */ | |
91 | static int flag_explicitly_parallel = 0; | |
92 | static int flag_xp_state = 0; | |
93 | ||
94 | /* Whether current and previous left sub-instruction disables | |
95 | execution of right sub-instruction. */ | |
96 | static int cur_left_kills_right_p = 0; | |
97 | static int prev_left_kills_right_p = 0; | |
98 | ||
99 | /* The known current alignment of the current section. */ | |
100 | static int d30v_current_align; | |
101 | static segT d30v_current_align_seg; | |
102 | ||
103 | /* The last seen label in the current section. This is used to auto-align | |
104 | labels preceeding instructions. */ | |
105 | static symbolS *d30v_last_label; | |
106 | ||
107 | /* Two nops */ | |
108 | #define NOP_LEFT ((long long) NOP << 32) | |
109 | #define NOP_RIGHT ((long long) NOP) | |
110 | #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT) | |
111 | ||
112 | /* local functions */ | |
113 | static int reg_name_search PARAMS ((char *name)); | |
114 | static int register_name PARAMS ((expressionS *expressionP)); | |
115 | static int check_range PARAMS ((unsigned long num, int bits, int flags)); | |
116 | static int postfix PARAMS ((char *p)); | |
117 | static bfd_reloc_code_real_type get_reloc PARAMS ((struct d30v_operand *op, int rel_flag)); | |
118 | static int get_operands PARAMS ((expressionS exp[], int cmp_hack)); | |
119 | static struct d30v_format *find_format PARAMS ((struct d30v_opcode *opcode, | |
120 | expressionS ops[],int fsize, int cmp_hack)); | |
121 | static long long build_insn PARAMS ((struct d30v_insn *opcode, expressionS *opers)); | |
122 | static void write_long PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx)); | |
123 | static void write_1_short PARAMS ((struct d30v_insn *opcode, long long insn, | |
124 | Fixups *fx, int use_sequential)); | |
125 | static int write_2_short PARAMS ((struct d30v_insn *opcode1, long long insn1, | |
126 | struct d30v_insn *opcode2, long long insn2, exec_type_enum exec_type, Fixups *fx)); | |
127 | static long long do_assemble PARAMS ((char *str, struct d30v_insn *opcode, | |
128 | int shortp, int is_parallel)); | |
129 | static int parallel_ok PARAMS ((struct d30v_insn *opcode1, unsigned long insn1, | |
130 | struct d30v_insn *opcode2, unsigned long insn2, | |
131 | exec_type_enum exec_type)); | |
132 | static void d30v_number_to_chars PARAMS ((char *buf, long long value, int nbytes)); | |
133 | static void check_size PARAMS ((long value, int bits, char *file, int line)); | |
134 | static void d30v_align PARAMS ((int, char *, symbolS *)); | |
135 | static void s_d30v_align PARAMS ((int)); | |
136 | static void s_d30v_text PARAMS ((int)); | |
137 | static void s_d30v_data PARAMS ((int)); | |
138 | static void s_d30v_section PARAMS ((int)); | |
139 | ||
140 | struct option md_longopts[] = { | |
141 | {NULL, no_argument, NULL, 0} | |
142 | }; | |
143 | size_t md_longopts_size = sizeof(md_longopts); | |
144 | ||
145 | ||
146 | /* The target specific pseudo-ops which we support. */ | |
147 | const pseudo_typeS md_pseudo_table[] = | |
148 | { | |
149 | { "word", cons, 4 }, | |
150 | { "hword", cons, 2 }, | |
151 | { "align", s_d30v_align, 0 }, | |
152 | { "text", s_d30v_text, 0 }, | |
153 | { "data", s_d30v_data, 0 }, | |
154 | { "section", s_d30v_section, 0 }, | |
155 | { "section.s", s_d30v_section, 0 }, | |
156 | { "sect", s_d30v_section, 0 }, | |
157 | { "sect.s", s_d30v_section, 0 }, | |
158 | { NULL, NULL, 0 } | |
159 | }; | |
160 | ||
161 | /* Opcode hash table. */ | |
162 | static struct hash_control *d30v_hash; | |
163 | ||
164 | /* reg_name_search does a binary search of the pre_defined_registers | |
165 | array to see if "name" is a valid regiter name. Returns the register | |
166 | number from the array on success, or -1 on failure. */ | |
167 | ||
168 | static int | |
169 | reg_name_search (name) | |
170 | char *name; | |
171 | { | |
172 | int middle, low, high; | |
173 | int cmp; | |
174 | ||
175 | low = 0; | |
176 | high = reg_name_cnt () - 1; | |
177 | ||
178 | do | |
179 | { | |
180 | middle = (low + high) / 2; | |
181 | cmp = strcasecmp (name, pre_defined_registers[middle].name); | |
182 | if (cmp < 0) | |
183 | high = middle - 1; | |
184 | else if (cmp > 0) | |
185 | low = middle + 1; | |
186 | else | |
187 | { | |
188 | if (symbol_find (name) != NULL) | |
189 | { | |
190 | if (warn_register_name_conflicts) | |
191 | as_warn (_("Register name %s conflicts with symbol of the same name"), | |
192 | name); | |
193 | } | |
194 | ||
195 | return pre_defined_registers[middle].value; | |
196 | } | |
197 | } | |
198 | while (low <= high); | |
199 | ||
200 | return -1; | |
201 | } | |
202 | ||
203 | /* register_name() checks the string at input_line_pointer | |
204 | to see if it is a valid register name. */ | |
205 | ||
206 | static int | |
207 | register_name (expressionP) | |
208 | expressionS *expressionP; | |
209 | { | |
210 | int reg_number; | |
211 | char c, *p = input_line_pointer; | |
212 | ||
213 | while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')') | |
214 | p++; | |
215 | ||
216 | c = *p; | |
217 | if (c) | |
218 | *p++ = 0; | |
219 | ||
220 | /* look to see if it's in the register table */ | |
221 | reg_number = reg_name_search (input_line_pointer); | |
222 | if (reg_number >= 0) | |
223 | { | |
224 | expressionP->X_op = O_register; | |
225 | /* temporarily store a pointer to the string here */ | |
49309057 | 226 | expressionP->X_op_symbol = (symbolS *)input_line_pointer; |
252b5132 RH |
227 | expressionP->X_add_number = reg_number; |
228 | input_line_pointer = p; | |
229 | return 1; | |
230 | } | |
231 | if (c) | |
232 | *(p-1) = c; | |
233 | return 0; | |
234 | } | |
235 | ||
236 | ||
237 | static int | |
238 | check_range (num, bits, flags) | |
239 | unsigned long num; | |
240 | int bits; | |
241 | int flags; | |
242 | { | |
243 | long min, max; | |
244 | int retval=0; | |
245 | ||
246 | /* don't bother checking 32-bit values */ | |
ba09cd8d | 247 | if (bits == 32 && sizeof(unsigned long) * CHAR_BIT == 32) |
252b5132 RH |
248 | return 0; |
249 | ||
ba09cd8d DN |
250 | /* Sign extend signed values to unsigned long */ |
251 | if ((flags & OPERAND_SIGNED) && (num & ((unsigned long)1 << (bits - 1)))) | |
252 | num |= ((long)-1 << (bits - 1)); | |
253 | ||
252b5132 RH |
254 | if (flags & OPERAND_SHIFT) |
255 | { | |
256 | /* We know that all shifts are right by three bits.... */ | |
257 | ||
258 | if (flags & OPERAND_SIGNED) | |
ba09cd8d DN |
259 | num = (unsigned long) ( (long) num >= 0) |
260 | ? ( ((long) num) >> 3 ) | |
261 | : ( (num >> 3) | ((unsigned long)-1 << (32 - 3)) ); | |
252b5132 RH |
262 | else |
263 | num >>= 3; | |
264 | } | |
265 | ||
266 | if (flags & OPERAND_SIGNED) | |
267 | { | |
ba09cd8d DN |
268 | max = ((unsigned long)1 << (bits - 1)) - 1; |
269 | min = - ((unsigned long)1 << (bits - 1)); | |
252b5132 RH |
270 | if (((long)num > max) || ((long)num < min)) |
271 | retval = 1; | |
272 | } | |
273 | else | |
274 | { | |
ba09cd8d | 275 | max = ((unsigned long)1 << bits) - 1; |
252b5132 RH |
276 | min = 0; |
277 | if ((num > max) || (num < min)) | |
278 | retval = 1; | |
279 | } | |
280 | ||
281 | return retval; | |
282 | } | |
283 | ||
284 | ||
285 | void | |
286 | md_show_usage (stream) | |
287 | FILE *stream; | |
288 | { | |
289 | fprintf (stream, _("\nD30V options:\n\ | |
290 | -O Make adjacent short instructions parallel if possible.\n\ | |
291 | -n Warn about all NOPs inserted by the assembler.\n\ | |
292 | -N Warn about NOPs inserted after word multiplies.\n\ | |
293 | -c Warn about symbols whoes names match register names.\n\ | |
294 | -C Opposite of -C. -c is the default.\n")); | |
295 | } | |
296 | ||
297 | int | |
298 | md_parse_option (c, arg) | |
299 | int c; | |
300 | char *arg; | |
301 | { | |
302 | switch (c) | |
303 | { | |
304 | /* Optimize. Will attempt to parallelize operations */ | |
305 | case 'O': | |
306 | Optimizing = 1; | |
307 | break; | |
308 | ||
309 | /* Warn about all NOPS that the assembler inserts. */ | |
310 | case 'n': | |
311 | warn_nops = NOP_ALL; | |
312 | break; | |
313 | ||
314 | /* Warn about the NOPS that the assembler inserts because of the | |
315 | multiply hazard. */ | |
316 | case 'N': | |
317 | warn_nops = NOP_MULTIPLY; | |
318 | break; | |
319 | ||
320 | case 'c': | |
321 | warn_register_name_conflicts = 1; | |
322 | break; | |
323 | ||
324 | case 'C': | |
325 | warn_register_name_conflicts = 0; | |
326 | break; | |
327 | ||
328 | default: | |
329 | return 0; | |
330 | } | |
331 | return 1; | |
332 | } | |
333 | ||
334 | symbolS * | |
335 | md_undefined_symbol (name) | |
336 | char *name; | |
337 | { | |
338 | return 0; | |
339 | } | |
340 | ||
341 | /* Turn a string in input_line_pointer into a floating point constant of type | |
342 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS | |
343 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. | |
344 | */ | |
345 | char * | |
346 | md_atof (type, litP, sizeP) | |
347 | int type; | |
348 | char *litP; | |
349 | int *sizeP; | |
350 | { | |
351 | int prec; | |
352 | LITTLENUM_TYPE words[4]; | |
353 | char *t; | |
354 | int i; | |
355 | ||
356 | switch (type) | |
357 | { | |
358 | case 'f': | |
359 | prec = 2; | |
360 | break; | |
361 | case 'd': | |
362 | prec = 4; | |
363 | break; | |
364 | default: | |
365 | *sizeP = 0; | |
366 | return _("bad call to md_atof"); | |
367 | } | |
368 | ||
369 | t = atof_ieee (input_line_pointer, type, words); | |
370 | if (t) | |
371 | input_line_pointer = t; | |
372 | ||
373 | *sizeP = prec * 2; | |
374 | ||
375 | for (i = 0; i < prec; i++) | |
376 | { | |
377 | md_number_to_chars (litP, (valueT) words[i], 2); | |
378 | litP += 2; | |
379 | } | |
380 | return NULL; | |
381 | } | |
382 | ||
383 | void | |
384 | md_convert_frag (abfd, sec, fragP) | |
385 | bfd *abfd; | |
386 | asection *sec; | |
387 | fragS *fragP; | |
388 | { | |
389 | abort (); | |
390 | } | |
391 | ||
392 | valueT | |
393 | md_section_align (seg, addr) | |
394 | asection *seg; | |
395 | valueT addr; | |
396 | { | |
397 | int align = bfd_get_section_alignment (stdoutput, seg); | |
398 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
399 | } | |
400 | ||
401 | ||
402 | void | |
403 | md_begin () | |
404 | { | |
405 | struct d30v_opcode * opcode; | |
406 | d30v_hash = hash_new (); | |
407 | ||
408 | /* Insert opcode names into a hash table. */ | |
409 | for (opcode = (struct d30v_opcode *)d30v_opcode_table; opcode->name; opcode++) | |
410 | hash_insert (d30v_hash, opcode->name, (char *) opcode); | |
411 | ||
412 | fixups = &FixUps[0]; | |
413 | FixUps[0].next = &FixUps[1]; | |
414 | FixUps[1].next = &FixUps[0]; | |
415 | ||
416 | d30v_current_align_seg = now_seg; | |
417 | } | |
418 | ||
419 | ||
420 | /* this function removes the postincrement or postdecrement | |
421 | operator ( '+' or '-' ) from an expression */ | |
422 | ||
423 | static int postfix (p) | |
424 | char *p; | |
425 | { | |
426 | while (*p != '-' && *p != '+') | |
427 | { | |
428 | if (*p==0 || *p=='\n' || *p=='\r' || *p==' ' || *p==',') | |
429 | break; | |
430 | p++; | |
431 | } | |
432 | ||
433 | if (*p == '-') | |
434 | { | |
435 | *p = ' '; | |
436 | return (-1); | |
437 | } | |
438 | if (*p == '+') | |
439 | { | |
440 | *p = ' '; | |
441 | return (1); | |
442 | } | |
443 | ||
444 | return (0); | |
445 | } | |
446 | ||
447 | ||
448 | static bfd_reloc_code_real_type | |
449 | get_reloc (op, rel_flag) | |
450 | struct d30v_operand *op; | |
451 | int rel_flag; | |
452 | { | |
453 | switch (op->bits) | |
454 | { | |
455 | case 6: | |
456 | if (op->flags & OPERAND_SHIFT) | |
457 | return BFD_RELOC_D30V_9_PCREL; | |
458 | else | |
459 | return BFD_RELOC_D30V_6; | |
460 | break; | |
461 | case 12: | |
462 | if (!(op->flags & OPERAND_SHIFT)) | |
463 | as_warn (_("unexpected 12-bit reloc type")); | |
464 | if (rel_flag == RELOC_PCREL) | |
465 | return BFD_RELOC_D30V_15_PCREL; | |
466 | else | |
467 | return BFD_RELOC_D30V_15; | |
468 | case 18: | |
469 | if (!(op->flags & OPERAND_SHIFT)) | |
470 | as_warn (_("unexpected 18-bit reloc type")); | |
471 | if (rel_flag == RELOC_PCREL) | |
472 | return BFD_RELOC_D30V_21_PCREL; | |
473 | else | |
474 | return BFD_RELOC_D30V_21; | |
475 | case 32: | |
476 | if (rel_flag == RELOC_PCREL) | |
477 | return BFD_RELOC_D30V_32_PCREL; | |
478 | else | |
479 | return BFD_RELOC_D30V_32; | |
480 | default: | |
481 | return 0; | |
482 | } | |
483 | } | |
484 | ||
485 | /* get_operands parses a string of operands and returns | |
486 | an array of expressions */ | |
487 | ||
488 | static int | |
489 | get_operands (exp, cmp_hack) | |
490 | expressionS exp[]; | |
491 | int cmp_hack; | |
492 | { | |
493 | char *p = input_line_pointer; | |
494 | int numops = 0; | |
495 | int post = 0; | |
496 | ||
497 | if (cmp_hack) | |
498 | { | |
499 | exp[numops].X_op = O_absent; | |
500 | exp[numops++].X_add_number = cmp_hack - 1; | |
501 | } | |
502 | ||
503 | while (*p) | |
504 | { | |
505 | while (*p == ' ' || *p == '\t' || *p == ',') | |
506 | p++; | |
507 | if (*p==0 || *p=='\n' || *p=='\r') | |
508 | break; | |
509 | ||
510 | if (*p == '@') | |
511 | { | |
512 | p++; | |
513 | exp[numops].X_op = O_absent; | |
514 | if (*p == '(') | |
515 | { | |
516 | p++; | |
517 | exp[numops].X_add_number = OPERAND_ATPAR; | |
518 | post = postfix (p); | |
519 | } | |
520 | else if (*p == '-') | |
521 | { | |
522 | p++; | |
523 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
524 | } | |
525 | else | |
526 | { | |
527 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
528 | post = postfix (p); | |
529 | } | |
530 | numops++; | |
531 | continue; | |
532 | } | |
533 | ||
534 | if (*p == ')') | |
535 | { | |
536 | /* just skip the trailing paren */ | |
537 | p++; | |
538 | continue; | |
539 | } | |
540 | ||
541 | input_line_pointer = p; | |
542 | ||
543 | /* check to see if it might be a register name */ | |
544 | if (!register_name (&exp[numops])) | |
545 | { | |
546 | /* parse as an expression */ | |
547 | expression (&exp[numops]); | |
548 | } | |
549 | ||
550 | if (exp[numops].X_op == O_illegal) | |
551 | as_bad (_("illegal operand")); | |
552 | else if (exp[numops].X_op == O_absent) | |
553 | as_bad (_("missing operand")); | |
554 | ||
555 | numops++; | |
556 | p = input_line_pointer; | |
557 | ||
558 | switch (post) | |
559 | { | |
560 | case -1: /* postdecrement mode */ | |
561 | exp[numops].X_op = O_absent; | |
562 | exp[numops++].X_add_number = OPERAND_MINUS; | |
563 | break; | |
564 | case 1: /* postincrement mode */ | |
565 | exp[numops].X_op = O_absent; | |
566 | exp[numops++].X_add_number = OPERAND_PLUS; | |
567 | break; | |
568 | } | |
569 | post = 0; | |
570 | } | |
571 | ||
572 | exp[numops].X_op = 0; | |
573 | return (numops); | |
574 | } | |
575 | ||
576 | /* build_insn generates the instruction. It does everything */ | |
577 | /* but write the FM bits. */ | |
578 | ||
579 | static long long | |
580 | build_insn (opcode, opers) | |
581 | struct d30v_insn *opcode; | |
582 | expressionS *opers; | |
583 | { | |
584 | int i, length, bits, shift, flags; | |
585 | unsigned int number, id=0; | |
586 | long long insn; | |
587 | struct d30v_opcode *op = opcode->op; | |
588 | struct d30v_format *form = opcode->form; | |
589 | ||
590 | insn = opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18; | |
591 | ||
592 | for (i=0; form->operands[i]; i++) | |
593 | { | |
594 | flags = d30v_operand_table[form->operands[i]].flags; | |
595 | ||
596 | /* must be a register or number */ | |
597 | if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM) && | |
598 | !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL)) | |
599 | continue; | |
600 | ||
601 | bits = d30v_operand_table[form->operands[i]].bits; | |
602 | if (flags & OPERAND_SHIFT) | |
603 | bits += 3; | |
604 | ||
605 | length = d30v_operand_table[form->operands[i]].length; | |
606 | shift = 12 - d30v_operand_table[form->operands[i]].position; | |
607 | if (opers[i].X_op != O_symbol) | |
608 | number = opers[i].X_add_number; | |
609 | else | |
610 | number = 0; | |
611 | if (flags & OPERAND_REG) | |
612 | { | |
613 | /* check for mvfsys or mvtsys control registers */ | |
614 | if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG) | |
615 | { | |
616 | /* PSWL or PSWH */ | |
617 | id = (number & 0x7f) - MAX_CONTROL_REG; | |
618 | number = 0; | |
619 | } | |
620 | else if (number & OPERAND_FLAG) | |
621 | { | |
622 | id = 3; /* number is a flag register */ | |
623 | } | |
624 | number &= 0x7F; | |
625 | } | |
626 | else if (flags & OPERAND_SPECIAL) | |
627 | { | |
628 | number = id; | |
629 | } | |
630 | ||
631 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant && !(flags & OPERAND_NAME)) | |
632 | { | |
633 | /* now create a fixup */ | |
634 | ||
635 | if (fixups->fc >= MAX_INSN_FIXUPS) | |
636 | as_fatal (_("too many fixups")); | |
637 | ||
638 | fixups->fix[fixups->fc].reloc = | |
639 | get_reloc ((struct d30v_operand *)&d30v_operand_table[form->operands[i]], op->reloc_flag); | |
640 | fixups->fix[fixups->fc].size = 4; | |
641 | fixups->fix[fixups->fc].exp = opers[i]; | |
642 | fixups->fix[fixups->fc].operand = form->operands[i]; | |
643 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL) | |
644 | fixups->fix[fixups->fc].pcrel = RELOC_PCREL; | |
645 | else | |
646 | fixups->fix[fixups->fc].pcrel = op->reloc_flag; | |
647 | (fixups->fc)++; | |
648 | } | |
649 | ||
650 | /* truncate to the proper number of bits */ | |
651 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) | |
652 | as_bad (_("operand out of range: %d"),number); | |
653 | if (bits < 31) | |
654 | number &= 0x7FFFFFFF >> (31 - bits); | |
655 | if (flags & OPERAND_SHIFT) | |
656 | number >>= 3; | |
657 | if (bits == 32) | |
658 | { | |
659 | /* it's a LONG instruction */ | |
660 | insn |= (number >> 26); /* top 6 bits */ | |
661 | insn <<= 32; /* shift the first word over */ | |
662 | insn |= ((number & 0x03FC0000) << 2); /* next 8 bits */ | |
663 | insn |= number & 0x0003FFFF; /* bottom 18 bits */ | |
664 | } | |
665 | else | |
666 | insn |= number << shift; | |
667 | } | |
668 | return insn; | |
669 | } | |
670 | ||
671 | ||
672 | /* write out a long form instruction */ | |
673 | static void | |
674 | write_long (opcode, insn, fx) | |
675 | struct d30v_insn *opcode; | |
676 | long long insn; | |
677 | Fixups *fx; | |
678 | { | |
679 | int i, where; | |
680 | char *f = frag_more (8); | |
681 | ||
682 | insn |= FM11; | |
683 | d30v_number_to_chars (f, insn, 8); | |
684 | ||
685 | for (i=0; i < fx->fc; i++) | |
686 | { | |
687 | if (fx->fix[i].reloc) | |
688 | { | |
689 | where = f - frag_now->fr_literal; | |
690 | fix_new_exp (frag_now, | |
691 | where, | |
692 | fx->fix[i].size, | |
693 | &(fx->fix[i].exp), | |
694 | fx->fix[i].pcrel, | |
695 | fx->fix[i].reloc); | |
696 | } | |
697 | } | |
698 | fx->fc = 0; | |
699 | } | |
700 | ||
701 | ||
702 | /* Write out a short form instruction by itself. */ | |
703 | static void | |
704 | write_1_short (opcode, insn, fx, use_sequential) | |
705 | struct d30v_insn *opcode; | |
706 | long long insn; | |
707 | Fixups *fx; | |
708 | int use_sequential; | |
709 | { | |
710 | char *f = frag_more (8); | |
711 | int i, where; | |
712 | ||
713 | if (warn_nops == NOP_ALL) | |
714 | as_warn (_("%s NOP inserted"), use_sequential ? | |
715 | _("sequential") : _("parallel")); | |
716 | ||
717 | /* The other container needs to be NOP. */ | |
718 | if (use_sequential) | |
719 | { | |
720 | /* Use a sequential NOP rather than a parallel one, | |
721 | as the current instruction is a FLAG_MUL32 type one | |
722 | and the next instruction is a load. */ | |
723 | ||
724 | /* According to 4.3.1: for FM=01, sub-instructions performed | |
725 | only by IU cannot be encoded in L-container. */ | |
726 | ||
727 | if (opcode->op->unit == IU) | |
728 | insn |= FM10 | NOP_LEFT; /* right then left */ | |
729 | else | |
730 | insn = FM01 | (insn << 32) | NOP_RIGHT; /* left then right */ | |
731 | } | |
732 | else | |
733 | { | |
734 | /* According to 4.3.1: for FM=00, sub-instructions performed | |
735 | only by IU cannot be encoded in L-container. */ | |
736 | ||
737 | if (opcode->op->unit == IU) | |
738 | insn |= FM00 | NOP_LEFT; /* right container */ | |
739 | else | |
740 | insn = FM00 | (insn << 32) | NOP_RIGHT; /* left container */ | |
741 | } | |
742 | ||
743 | d30v_number_to_chars (f, insn, 8); | |
744 | ||
745 | for (i=0; i < fx->fc; i++) | |
746 | { | |
747 | if (fx->fix[i].reloc) | |
748 | { | |
749 | where = f - frag_now->fr_literal; | |
750 | fix_new_exp (frag_now, | |
751 | where, | |
752 | fx->fix[i].size, | |
753 | &(fx->fix[i].exp), | |
754 | fx->fix[i].pcrel, | |
755 | fx->fix[i].reloc); | |
756 | } | |
757 | } | |
758 | fx->fc = 0; | |
759 | } | |
760 | ||
761 | /* Write out a short form instruction if possible. | |
762 | Return number of instructions not written out. */ | |
763 | static int | |
764 | write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) | |
765 | struct d30v_insn *opcode1, *opcode2; | |
766 | long long insn1, insn2; | |
767 | exec_type_enum exec_type; | |
768 | Fixups *fx; | |
769 | { | |
770 | long long insn = NOP2; | |
771 | char *f; | |
772 | int i,j, where; | |
773 | ||
774 | if (exec_type == EXEC_SEQ | |
775 | && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)) | |
776 | && ((opcode1->op->flags_used & FLAG_DELAY) == 0) | |
777 | && ((opcode1->ecc == ECC_AL) || ! Optimizing)) | |
778 | { | |
779 | /* Unconditional, non-delayed branches kill instructions in | |
780 | the right bin. Conditional branches don't always but if | |
781 | we are not optimizing, then we have been asked to produce | |
782 | an error about such constructs. For the purposes of this | |
783 | test, subroutine calls are considered to be branches. */ | |
784 | write_1_short (opcode1, insn1, fx->next, false); | |
785 | return 1; | |
786 | } | |
787 | ||
788 | /* Note: we do not have to worry about subroutine calls occuring | |
789 | in the right hand container. The return address is always | |
790 | aligned to the next 64 bit boundary, be that 64 or 32 bit away. */ | |
791 | ||
792 | switch (exec_type) | |
793 | { | |
794 | case EXEC_UNKNOWN: /* Order not specified. */ | |
795 | if (Optimizing | |
796 | && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type) | |
797 | && ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU | |
798 | || opcode1->op->unit == MU) | |
799 | && | |
800 | ( opcode2->op->unit == EITHER_BUT_PREFER_MU | |
801 | || opcode2->op->unit == MU))) | |
802 | { | |
803 | /* parallel */ | |
804 | exec_type = EXEC_PARALLEL; | |
805 | ||
806 | if (opcode1->op->unit == IU | |
807 | || opcode2->op->unit == MU | |
808 | || opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
809 | insn = FM00 | (insn2 << 32) | insn1; | |
810 | else | |
811 | { | |
812 | insn = FM00 | (insn1 << 32) | insn2; | |
813 | fx = fx->next; | |
814 | } | |
815 | } | |
0825afba JR |
816 | else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR) |
817 | && ((opcode1->op->flags_used & FLAG_DELAY) == 0) | |
818 | && ((opcode1->ecc == ECC_AL) || ! Optimizing)) | |
819 | || opcode1->op->flags_used & FLAG_RP) | |
252b5132 RH |
820 | { |
821 | /* We must emit (non-delayed) branch type instructions | |
822 | on their own with nothing in the right container. */ | |
0825afba JR |
823 | /* We must treat repeat instructions likewise, since the |
824 | following instruction has to be separate from the repeat | |
825 | in order to be repeated. */ | |
252b5132 RH |
826 | write_1_short (opcode1, insn1, fx->next, false); |
827 | return 1; | |
828 | } | |
829 | else if (prev_left_kills_right_p) | |
830 | { | |
831 | /* The left instruction kils the right slot, so we | |
832 | must leave it empty. */ | |
833 | write_1_short (opcode1, insn1, fx->next, false); | |
834 | return 1; | |
835 | } | |
836 | else if (opcode1->op->unit == IU | |
837 | || (opcode1->op->unit == EITHER | |
838 | && opcode2->op->unit == EITHER_BUT_PREFER_MU)) | |
839 | { | |
840 | /* reverse sequential */ | |
841 | insn = FM10 | (insn2 << 32) | insn1; | |
842 | exec_type = EXEC_REVSEQ; | |
843 | } | |
844 | else | |
845 | { | |
846 | /* sequential */ | |
847 | insn = FM01 | (insn1 << 32) | insn2; | |
848 | fx = fx->next; | |
849 | exec_type = EXEC_SEQ; | |
850 | } | |
851 | break; | |
852 | ||
853 | case EXEC_PARALLEL: /* parallel */ | |
854 | flag_explicitly_parallel = flag_xp_state; | |
855 | if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
856 | as_bad (_("Instructions may not be executed in parallel")); | |
857 | else if (opcode1->op->unit == IU) | |
858 | { | |
859 | if (opcode2->op->unit == IU) | |
860 | as_bad (_("Two IU instructions may not be executed in parallel")); | |
861 | as_warn (_("Swapping instruction order")); | |
862 | insn = FM00 | (insn2 << 32) | insn1; | |
863 | } | |
864 | else if (opcode2->op->unit == MU) | |
865 | { | |
866 | if (opcode1->op->unit == MU) | |
867 | as_bad (_("Two MU instructions may not be executed in parallel")); | |
868 | else if (opcode1->op->unit == EITHER_BUT_PREFER_MU) | |
869 | as_warn (_("Executing %s in IU may not work"), opcode1->op->name); | |
870 | as_warn (_("Swapping instruction order")); | |
871 | insn = FM00 | (insn2 << 32) | insn1; | |
872 | } | |
873 | else | |
874 | { | |
875 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
876 | as_warn (_("Executing %s in IU may not work"), opcode2->op->name); | |
877 | ||
878 | insn = FM00 | (insn1 << 32) | insn2; | |
879 | fx = fx->next; | |
880 | } | |
881 | flag_explicitly_parallel = 0; | |
882 | break; | |
883 | ||
884 | case EXEC_SEQ: /* sequential */ | |
885 | if (opcode1->op->unit == IU) | |
886 | as_bad (_("IU instruction may not be in the left container")); | |
887 | if (prev_left_kills_right_p) | |
888 | as_bad (_("special left instruction `%s' kills instruction " | |
889 | "`%s' in right container"), | |
890 | opcode1->op->name, opcode2->op->name); | |
891 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
892 | as_warn (_("Executing %s in IU may not work"), opcode2->op->name); | |
893 | insn = FM01 | (insn1 << 32) | insn2; | |
894 | fx = fx->next; | |
895 | break; | |
896 | ||
897 | case EXEC_REVSEQ: /* reverse sequential */ | |
898 | if (opcode2->op->unit == MU) | |
899 | as_bad (_("MU instruction may not be in the right container")); | |
900 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
901 | as_warn (_("Executing %s in IU may not work"), opcode2->op->name); | |
902 | insn = FM10 | (insn1 << 32) | insn2; | |
903 | fx = fx->next; | |
904 | break; | |
905 | ||
906 | default: | |
907 | as_fatal (_("unknown execution type passed to write_2_short()")); | |
908 | } | |
909 | ||
910 | /* printf ("writing out %llx\n",insn); */ | |
911 | f = frag_more (8); | |
912 | d30v_number_to_chars (f, insn, 8); | |
913 | ||
914 | /* If the previous instruction was a 32-bit multiply but it is put into a | |
915 | parallel container, mark the current instruction as being a 32-bit | |
916 | multiply. */ | |
917 | if (prev_mul32_p && exec_type == EXEC_PARALLEL) | |
918 | cur_mul32_p = 1; | |
919 | ||
920 | for (j=0; j<2; j++) | |
921 | { | |
922 | for (i=0; i < fx->fc; i++) | |
923 | { | |
924 | if (fx->fix[i].reloc) | |
925 | { | |
926 | where = (f - frag_now->fr_literal) + 4*j; | |
927 | ||
928 | fix_new_exp (frag_now, | |
929 | where, | |
930 | fx->fix[i].size, | |
931 | &(fx->fix[i].exp), | |
932 | fx->fix[i].pcrel, | |
933 | fx->fix[i].reloc); | |
934 | } | |
935 | } | |
936 | ||
937 | fx->fc = 0; | |
938 | fx = fx->next; | |
939 | } | |
940 | ||
941 | return 0; | |
942 | } | |
943 | ||
944 | ||
945 | /* Check 2 instructions and determine if they can be safely */ | |
946 | /* executed in parallel. Returns 1 if they can be. */ | |
947 | static int | |
948 | parallel_ok (op1, insn1, op2, insn2, exec_type) | |
949 | struct d30v_insn *op1, *op2; | |
950 | unsigned long insn1, insn2; | |
951 | exec_type_enum exec_type; | |
952 | { | |
953 | int i, j, shift, regno, bits, ecc; | |
954 | unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2; | |
955 | unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2]; | |
956 | struct d30v_format *f; | |
957 | struct d30v_opcode *op; | |
958 | ||
959 | /* section 4.3: both instructions must not be IU or MU only */ | |
960 | if ((op1->op->unit == IU && op2->op->unit == IU) | |
961 | || (op1->op->unit == MU && op2->op->unit == MU)) | |
962 | return 0; | |
963 | ||
964 | /* first instruction must not be a jump to safely optimize, unless this | |
965 | is an explicit parallel operation. */ | |
966 | if (exec_type != EXEC_PARALLEL | |
967 | && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR))) | |
968 | return 0; | |
969 | ||
970 | /* If one instruction is /TX or /XT and the other is /FX or /XF respectively, | |
971 | then it is safe to allow the two to be done as parallel ops, since only | |
972 | one will ever be executed at a time. */ | |
973 | if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX) | |
974 | || (op1->ecc == ECC_FX && op2->ecc == ECC_TX) | |
975 | || (op1->ecc == ECC_XT && op2->ecc == ECC_XF) | |
976 | || (op1->ecc == ECC_XF && op2->ecc == ECC_XT)) | |
977 | return 1; | |
978 | ||
979 | /* [0] r0-r31 | |
980 | [1] r32-r63 | |
981 | [2] a0, a1, flag registers */ | |
982 | ||
983 | for (j = 0; j < 2; j++) | |
984 | { | |
985 | if (j == 0) | |
986 | { | |
987 | f = op1->form; | |
988 | op = op1->op; | |
989 | ecc = op1->ecc; | |
990 | ins = insn1; | |
991 | } | |
992 | else | |
993 | { | |
994 | f = op2->form; | |
995 | op = op2->op; | |
996 | ecc = op2->ecc; | |
997 | ins = insn2; | |
998 | } | |
999 | flag_reg[j] = 0; | |
1000 | mod_reg[j][0] = mod_reg[j][1] = 0; | |
1001 | used_reg[j][0] = used_reg[j][1] = 0; | |
1002 | ||
1003 | if (flag_explicitly_parallel) | |
1004 | { | |
1005 | /* For human specified parallel instructions we have been asked | |
1006 | to ignore the possibility that both instructions could modify | |
1007 | bits in the PSW, so we initialise the mod & used arrays to 0. | |
1008 | We have been asked, however, to refuse to allow parallel | |
1009 | instructions which explicitly set the same flag register, | |
1010 | eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test | |
1011 | for the use of a flag register and set a bit in the mod or used | |
1012 | array appropriately. */ | |
1013 | ||
1014 | mod_reg[j][2] = 0; | |
1015 | used_reg[j][2] = 0; | |
1016 | } | |
1017 | else | |
1018 | { | |
1019 | mod_reg[j][2] = (op->flags_set & FLAG_ALL); | |
1020 | used_reg[j][2] = (op->flags_used & FLAG_ALL); | |
1021 | } | |
1022 | ||
1023 | /* BSR/JSR always sets R62 */ | |
1024 | if (op->flags_used & FLAG_JSR) | |
1025 | mod_reg[j][1] = (1L << (62-32)); | |
1026 | ||
1027 | /* conditional execution affects the flags_used */ | |
1028 | switch (ecc) | |
1029 | { | |
1030 | case ECC_TX: | |
1031 | case ECC_FX: | |
1032 | used_reg[j][2] |= flag_reg[j] = FLAG_0; | |
1033 | break; | |
1034 | ||
1035 | case ECC_XT: | |
1036 | case ECC_XF: | |
1037 | used_reg[j][2] |= flag_reg[j] = FLAG_1; | |
1038 | break; | |
1039 | ||
1040 | case ECC_TT: | |
1041 | case ECC_TF: | |
1042 | used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1); | |
1043 | break; | |
1044 | } | |
1045 | ||
1046 | for (i = 0; f->operands[i]; i++) | |
1047 | { | |
1048 | flags = d30v_operand_table[f->operands[i]].flags; | |
1049 | shift = 12 - d30v_operand_table[f->operands[i]].position; | |
1050 | bits = d30v_operand_table[f->operands[i]].bits; | |
1051 | if (bits == 32) | |
1052 | mask = 0xffffffff; | |
1053 | else | |
1054 | mask = 0x7FFFFFFF >> (31 - bits); | |
1055 | ||
1056 | if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS)) | |
1057 | { | |
1058 | /* this is a post-increment or post-decrement */ | |
1059 | /* the previous register needs to be marked as modified */ | |
1060 | ||
1061 | shift = 12 - d30v_operand_table[f->operands[i-1]].position; | |
1062 | regno = (ins >> shift) & 0x3f; | |
1063 | if (regno >= 32) | |
1064 | mod_reg[j][1] |= 1L << (regno - 32); | |
1065 | else | |
1066 | mod_reg[j][0] |= 1L << regno; | |
1067 | } | |
1068 | else if (flags & OPERAND_REG) | |
1069 | { | |
1070 | regno = (ins >> shift) & mask; | |
1071 | /* the memory write functions don't have a destination register */ | |
1072 | if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM)) | |
1073 | { | |
1074 | /* MODIFIED registers and flags */ | |
1075 | if (flags & OPERAND_ACC) | |
1076 | { | |
1077 | if (regno == 0) | |
1078 | mod_reg[j][2] |= FLAG_A0; | |
1079 | else if (regno == 1) | |
1080 | mod_reg[j][2] |= FLAG_A1; | |
1081 | else | |
1082 | abort (); | |
1083 | } | |
1084 | else if (flags & OPERAND_FLAG) | |
1085 | mod_reg[j][2] |= 1L << regno; | |
1086 | else if (!(flags & OPERAND_CONTROL)) | |
1087 | { | |
1088 | int r, z; | |
1089 | ||
1090 | /* need to check if there are two destination */ | |
1091 | /* registers, for example ld2w */ | |
1092 | if (flags & OPERAND_2REG) | |
1093 | z = 1; | |
1094 | else | |
1095 | z = 0; | |
1096 | ||
1097 | for (r = regno; r <= regno + z; r++) | |
1098 | { | |
1099 | if (r >= 32) | |
1100 | mod_reg[j][1] |= 1L << (r - 32); | |
1101 | else | |
1102 | mod_reg[j][0] |= 1L << r; | |
1103 | } | |
1104 | } | |
1105 | } | |
1106 | else | |
1107 | { | |
1108 | /* USED, but not modified registers and flags */ | |
1109 | if (flags & OPERAND_ACC) | |
1110 | { | |
1111 | if (regno == 0) | |
1112 | used_reg[j][2] |= FLAG_A0; | |
1113 | else if (regno == 1) | |
1114 | used_reg[j][2] |= FLAG_A1; | |
1115 | else | |
1116 | abort (); | |
1117 | } | |
1118 | else if (flags & OPERAND_FLAG) | |
1119 | used_reg[j][2] |= 1L << regno; | |
1120 | else if (!(flags & OPERAND_CONTROL)) | |
1121 | { | |
1122 | int r, z; | |
1123 | ||
1124 | /* need to check if there are two source */ | |
1125 | /* registers, for example st2w */ | |
1126 | if (flags & OPERAND_2REG) | |
1127 | z = 1; | |
1128 | else | |
1129 | z = 0; | |
1130 | ||
1131 | for (r = regno; r <= regno + z; r++) | |
1132 | { | |
1133 | if (r >= 32) | |
1134 | used_reg[j][1] |= 1L << (r - 32); | |
1135 | else | |
1136 | used_reg[j][0] |= 1L << r; | |
1137 | } | |
1138 | } | |
1139 | } | |
1140 | } | |
1141 | } | |
1142 | } | |
1143 | ||
1144 | flags_set1 = op1->op->flags_set; | |
1145 | flags_set2 = op2->op->flags_set; | |
1146 | flags_used1 = op1->op->flags_used; | |
1147 | flags_used2 = op2->op->flags_used; | |
1148 | ||
1149 | /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */ | |
1150 | if (((flags_set1 & (FLAG_MEM | FLAG_2WORD)) == (FLAG_MEM | FLAG_2WORD) | |
1151 | && (flags_used2 & FLAG_ADDSUBppp) != 0) | |
1152 | || ((flags_set2 & (FLAG_MEM | FLAG_2WORD)) == (FLAG_MEM | FLAG_2WORD) | |
1153 | && (flags_used1 & FLAG_ADDSUBppp) != 0)) | |
1154 | return 0; | |
1155 | ||
1156 | /* Load instruction combined with half-word multiply is illegal. */ | |
1157 | if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16)) | |
1158 | || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16))) | |
1159 | return 0; | |
1160 | ||
1161 | /* Specifically allow add || add by removing carry, overflow bits dependency. | |
1162 | This is safe, even if an addc follows since the IU takes the argument in | |
1163 | the right container, and it writes its results last. | |
1164 | However, don't paralellize add followed by addc or sub followed by | |
1165 | subb. */ | |
1166 | ||
1167 | if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA | |
1168 | && (used_reg[0][2] & ~flag_reg[0]) == 0 | |
1169 | && (used_reg[1][2] & ~flag_reg[1]) == 0 | |
1170 | && op1->op->unit == EITHER && op2->op->unit == EITHER) | |
1171 | { | |
1172 | mod_reg[0][2] = mod_reg[1][2] = 0; | |
1173 | } | |
1174 | ||
1175 | for (j = 0; j < 3; j++) | |
1176 | { | |
1177 | /* If the second instruction depends on the first, we obviously | |
1178 | cannot parallelize. Note, the mod flag implies use, so | |
1179 | check that as well. */ | |
1180 | /* If flag_explicitly_parallel is set, then the case of the | |
1181 | second instruction using a register the first instruction | |
1182 | modifies is assumed to be okay; we trust the human. We | |
1183 | don't trust the human if both instructions modify the same | |
1184 | register but we do trust the human if they modify the same | |
1185 | flags. */ | |
1186 | /* We have now been requested not to trust the human if the | |
1187 | instructions modify the same flag registers either. */ | |
1188 | if (flag_explicitly_parallel) | |
1189 | { | |
1190 | if ((mod_reg[0][j] & mod_reg[1][j]) != 0) | |
1191 | return 0; | |
1192 | } | |
1193 | else | |
1194 | if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0) | |
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | return 1; | |
1199 | } | |
1200 | ||
1201 | ||
1202 | /* This is the main entry point for the machine-dependent assembler. str points to a | |
1203 | machine-dependent instruction. This function is supposed to emit the frags/bytes | |
1204 | it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing | |
1205 | and leaves the difficult stuff to do_assemble(). */ | |
1206 | ||
1207 | static long long prev_insn = -1; | |
1208 | static struct d30v_insn prev_opcode; | |
1209 | static subsegT prev_subseg; | |
1210 | static segT prev_seg = 0; | |
1211 | ||
1212 | void | |
1213 | md_assemble (str) | |
1214 | char *str; | |
1215 | { | |
1216 | struct d30v_insn opcode; | |
1217 | long long insn; | |
1218 | exec_type_enum extype = EXEC_UNKNOWN; /* execution type; parallel, etc */ | |
1219 | static exec_type_enum etype = EXEC_UNKNOWN; /* saved extype. used for multiline instructions */ | |
1220 | char *str2; | |
1221 | ||
1222 | if ((prev_insn != -1) && prev_seg | |
1223 | && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
1224 | d30v_cleanup (false); | |
1225 | ||
1226 | if (d30v_current_align < 3) | |
1227 | d30v_align (3, NULL, d30v_last_label); | |
1228 | else if (d30v_current_align > 3) | |
1229 | d30v_current_align = 3; | |
1230 | d30v_last_label = NULL; | |
1231 | ||
1232 | flag_explicitly_parallel = 0; | |
1233 | flag_xp_state = 0; | |
1234 | if (etype == EXEC_UNKNOWN) | |
1235 | { | |
1236 | /* look for the special multiple instruction separators */ | |
1237 | str2 = strstr (str, "||"); | |
1238 | if (str2) | |
1239 | { | |
1240 | extype = EXEC_PARALLEL; | |
1241 | flag_xp_state = 1; | |
1242 | } | |
1243 | else | |
1244 | { | |
1245 | str2 = strstr (str, "->"); | |
1246 | if (str2) | |
1247 | extype = EXEC_SEQ; | |
1248 | else | |
1249 | { | |
1250 | str2 = strstr (str, "<-"); | |
1251 | if (str2) | |
1252 | extype = EXEC_REVSEQ; | |
1253 | } | |
1254 | } | |
1255 | /* str2 points to the separator, if one */ | |
1256 | if (str2) | |
1257 | { | |
1258 | *str2 = 0; | |
1259 | ||
1260 | /* if two instructions are present and we already have one saved | |
1261 | then first write it out */ | |
1262 | d30v_cleanup (false); | |
1263 | ||
1264 | /* Assemble first instruction and save it. */ | |
1265 | prev_insn = do_assemble (str, &prev_opcode, 1, 0); | |
1266 | if (prev_insn == -1) | |
1267 | as_bad (_("Cannot assemble instruction")); | |
1268 | if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG) | |
1269 | as_bad (_("First opcode is long. Unable to mix instructions as specified.")); | |
1270 | fixups = fixups->next; | |
1271 | str = str2 + 2; | |
1272 | prev_seg = now_seg; | |
1273 | prev_subseg = now_subseg; | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | insn = do_assemble (str, &opcode, | |
1278 | (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN), | |
1279 | extype == EXEC_PARALLEL); | |
1280 | if (insn == -1) | |
1281 | { | |
1282 | if (extype != EXEC_UNKNOWN) | |
1283 | etype = extype; | |
1284 | as_bad (_("Cannot assemble instruction")); | |
1285 | return; | |
1286 | } | |
1287 | ||
1288 | if (etype != EXEC_UNKNOWN) | |
1289 | { | |
1290 | extype = etype; | |
1291 | etype = EXEC_UNKNOWN; | |
1292 | } | |
1293 | ||
1294 | /* Word multiply instructions must not be followed by either a load or a | |
1295 | 16-bit multiply instruction in the next cycle. */ | |
1296 | if ( (extype != EXEC_REVSEQ) | |
1297 | && prev_mul32_p | |
1298 | && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1299 | { | |
1300 | /* However, load and multiply should able to be combined in a parallel | |
1301 | operation, so check for that first. */ | |
1302 | if (prev_insn != -1 | |
1303 | && (opcode.op->flags_used & FLAG_MEM) | |
1304 | && opcode.form->form < LONG | |
1305 | && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN)) | |
1306 | && parallel_ok (&prev_opcode, (long)prev_insn, | |
1307 | &opcode, (long)insn, extype) | |
1308 | && write_2_short (&prev_opcode, (long)prev_insn, | |
1309 | &opcode, (long)insn, extype, fixups) == 0) | |
1310 | { | |
1311 | /* no instructions saved */ | |
1312 | prev_insn = -1; | |
1313 | return; | |
1314 | } | |
1315 | else | |
1316 | { | |
1317 | /* Can't parallelize, flush previous instruction and emit a word of NOPS, | |
1318 | unless the previous instruction is a NOP, in which case just flush it, | |
1319 | as this will generate a word of NOPs for us. */ | |
1320 | ||
1321 | if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0)) | |
1322 | d30v_cleanup (false); | |
1323 | else | |
1324 | { | |
1325 | char * f; | |
1326 | ||
1327 | if (prev_insn != -1) | |
1328 | d30v_cleanup (true); | |
1329 | else | |
1330 | { | |
1331 | f = frag_more (8); | |
1332 | d30v_number_to_chars (f, NOP2, 8); | |
1333 | ||
1334 | if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY) | |
1335 | { | |
1336 | if (opcode.op->flags_used & FLAG_MEM) | |
1337 | as_warn (_("word of NOPs added between word multiply and load")); | |
1338 | else | |
1339 | as_warn (_("word of NOPs added between word multiply and 16-bit multiply")); | |
1340 | } | |
1341 | } | |
1342 | } | |
1343 | ||
1344 | extype = EXEC_UNKNOWN; | |
1345 | } | |
1346 | } | |
1347 | else if ( (extype == EXEC_REVSEQ) | |
1348 | && cur_mul32_p | |
1349 | && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1350 | { | |
1351 | /* Can't parallelize, flush current instruction and add a sequential NOP. */ | |
1352 | write_1_short (& opcode, (long) insn, fixups->next->next, true); | |
1353 | ||
1354 | /* Make the previous instruction the current one. */ | |
1355 | extype = EXEC_UNKNOWN; | |
1356 | insn = prev_insn; | |
1357 | now_seg = prev_seg; | |
1358 | now_subseg = prev_subseg; | |
1359 | prev_insn = -1; | |
1360 | cur_mul32_p = prev_mul32_p; | |
1361 | prev_mul32_p = 0; | |
1362 | memcpy (&opcode, &prev_opcode, sizeof (prev_opcode)); | |
1363 | } | |
1364 | ||
1365 | /* If this is a long instruction, write it and any previous short instruction. */ | |
1366 | if (opcode.form->form >= LONG) | |
1367 | { | |
1368 | if (extype != EXEC_UNKNOWN) | |
1369 | as_bad (_("Instruction uses long version, so it cannot be mixed as specified")); | |
1370 | d30v_cleanup (false); | |
1371 | write_long (& opcode, insn, fixups); | |
1372 | prev_insn = -1; | |
1373 | } | |
1374 | else if ((prev_insn != -1) | |
1375 | && (write_2_short | |
1376 | (& prev_opcode, (long) prev_insn, & opcode, | |
1377 | (long) insn, extype, fixups) == 0)) | |
1378 | { | |
1379 | /* No instructions saved. */ | |
1380 | prev_insn = -1; | |
1381 | } | |
1382 | else | |
1383 | { | |
1384 | if (extype != EXEC_UNKNOWN) | |
1385 | as_bad (_("Unable to mix instructions as specified")); | |
1386 | ||
1387 | /* Save off last instruction so it may be packed on next pass. */ | |
1388 | memcpy (&prev_opcode, &opcode, sizeof (prev_opcode)); | |
1389 | prev_insn = insn; | |
1390 | prev_seg = now_seg; | |
1391 | prev_subseg = now_subseg; | |
1392 | fixups = fixups->next; | |
1393 | prev_mul32_p = cur_mul32_p; | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | ||
1398 | /* do_assemble assembles a single instruction and returns an opcode */ | |
1399 | /* it returns -1 (an invalid opcode) on error */ | |
1400 | ||
1401 | #define NAME_BUF_LEN 20 | |
1402 | ||
1403 | static long long | |
1404 | do_assemble (str, opcode, shortp, is_parallel) | |
1405 | char *str; | |
1406 | struct d30v_insn *opcode; | |
1407 | int shortp; | |
1408 | int is_parallel; | |
1409 | { | |
1410 | unsigned char * op_start; | |
1411 | unsigned char * save; | |
1412 | unsigned char * op_end; | |
1413 | char name [NAME_BUF_LEN]; | |
1414 | int cmp_hack; | |
1415 | int nlen = 0; | |
1416 | int fsize = (shortp ? FORCE_SHORT : 0); | |
1417 | expressionS myops [6]; | |
1418 | long long insn; | |
1419 | ||
1420 | /* Drop leading whitespace */ | |
1421 | while (* str == ' ') | |
1422 | str ++; | |
1423 | ||
1424 | /* find the opcode end */ | |
1425 | for (op_start = op_end = (unsigned char *) (str); | |
1426 | * op_end | |
1427 | && nlen < (NAME_BUF_LEN - 1) | |
1428 | && * op_end != '/' | |
1429 | && !is_end_of_line[*op_end] && *op_end != ' '; | |
1430 | op_end++) | |
1431 | { | |
1432 | name[nlen] = tolower (op_start[nlen]); | |
1433 | nlen++; | |
1434 | } | |
1435 | ||
1436 | if (nlen == 0) | |
1437 | return -1; | |
1438 | ||
1439 | name[nlen] = 0; | |
1440 | ||
1441 | /* if there is an execution condition code, handle it */ | |
1442 | if (*op_end == '/') | |
1443 | { | |
1444 | int i = 0; | |
1445 | while ( (i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2)) | |
1446 | i++; | |
1447 | ||
1448 | if (i == ECC_MAX) | |
1449 | { | |
1450 | char tmp[4]; | |
1451 | strncpy (tmp, op_end + 1, 2); | |
1452 | tmp[2] = 0; | |
1453 | as_bad (_("unknown condition code: %s"),tmp); | |
1454 | return -1; | |
1455 | } | |
1456 | /* printf ("condition code=%d\n",i); */ | |
1457 | opcode->ecc = i; | |
1458 | op_end += 3; | |
1459 | } | |
1460 | else | |
1461 | opcode->ecc = ECC_AL; | |
1462 | ||
1463 | ||
1464 | /* CMP and CMPU change their name based on condition codes */ | |
1465 | if (!strncmp (name, "cmp", 3)) | |
1466 | { | |
1467 | int p,i; | |
1468 | char **str = (char **)d30v_cc_names; | |
1469 | if (name[3] == 'u') | |
1470 | p = 4; | |
1471 | else | |
1472 | p = 3; | |
1473 | ||
1474 | for (i=1; *str && strncmp (*str, & name[p], 2); i++, str++) | |
1475 | ; | |
1476 | ||
1477 | /* cmpu only supports some condition codes */ | |
1478 | if (p == 4) | |
1479 | { | |
1480 | if (i < 3 || i > 6) | |
1481 | { | |
1482 | name[p+2]=0; | |
1483 | as_bad (_("cmpu doesn't support condition code %s"),&name[p]); | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | if (!*str) | |
1488 | { | |
1489 | name[p+2]=0; | |
1490 | as_bad (_("unknown condition code: %s"),&name[p]); | |
1491 | } | |
1492 | ||
1493 | cmp_hack = i; | |
1494 | name[p] = 0; | |
1495 | } | |
1496 | else | |
1497 | cmp_hack = 0; | |
1498 | ||
1499 | /* printf("cmp_hack=%d\n",cmp_hack); */ | |
1500 | ||
1501 | /* need to look for .s or .l */ | |
1502 | if (name[nlen-2] == '.') | |
1503 | { | |
1504 | switch (name[nlen-1]) | |
1505 | { | |
1506 | case 's': | |
1507 | fsize = FORCE_SHORT; | |
1508 | break; | |
1509 | case 'l': | |
1510 | fsize = FORCE_LONG; | |
1511 | break; | |
1512 | } | |
1513 | name[nlen-2] = 0; | |
1514 | } | |
1515 | ||
1516 | /* find the first opcode with the proper name */ | |
1517 | opcode->op = (struct d30v_opcode *)hash_find (d30v_hash, name); | |
1518 | if (opcode->op == NULL) | |
1519 | { | |
1520 | as_bad (_("unknown opcode: %s"),name); | |
1521 | return -1; | |
1522 | } | |
1523 | ||
1524 | save = input_line_pointer; | |
1525 | input_line_pointer = op_end; | |
1526 | while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack))) | |
1527 | { | |
1528 | opcode->op++; | |
1529 | if (opcode->op->name == NULL || strcmp (opcode->op->name, name)) | |
1530 | { | |
1531 | as_bad (_("operands for opcode `%s' do not match any valid format"), name); | |
1532 | return -1; | |
1533 | } | |
1534 | } | |
1535 | input_line_pointer = save; | |
1536 | ||
1537 | insn = build_insn (opcode, myops); | |
1538 | ||
1539 | /* Propigate multiply status */ | |
1540 | if (insn != -1) | |
1541 | { | |
1542 | if (is_parallel && prev_mul32_p) | |
1543 | cur_mul32_p = 1; | |
1544 | else | |
1545 | { | |
1546 | prev_mul32_p = cur_mul32_p; | |
1547 | cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0; | |
1548 | } | |
1549 | } | |
1550 | ||
1551 | /* Propagate left_kills_right status */ | |
1552 | if (insn != -1) | |
1553 | { | |
1554 | prev_left_kills_right_p = cur_left_kills_right_p; | |
1555 | ||
1556 | if (opcode->op->flags_set & FLAG_LKR) | |
1557 | { | |
1558 | cur_left_kills_right_p = 1; | |
1559 | ||
1560 | if (strcmp (opcode->op->name, "mvtsys") == 0) | |
1561 | { | |
1562 | /* Left kills right for only mvtsys only for PSW/PSWH/PSWL/flags target. */ | |
1563 | if ((myops[0].X_op == O_register) && | |
1564 | ((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */ | |
1565 | (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */ | |
1566 | (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */ | |
1567 | (myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */ | |
1568 | (myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */ | |
1569 | (myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */ | |
1570 | (myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */ | |
1571 | (myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */ | |
1572 | (myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */ | |
1573 | (myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */ | |
1574 | (myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */ | |
1575 | { | |
1576 | cur_left_kills_right_p = 1; | |
1577 | } | |
1578 | else | |
1579 | { | |
1580 | /* Other mvtsys target registers don't kill right instruction. */ | |
1581 | cur_left_kills_right_p = 0; | |
1582 | } | |
1583 | } /* mvtsys */ | |
1584 | } | |
1585 | else | |
1586 | cur_left_kills_right_p = 0; | |
1587 | } | |
1588 | ||
1589 | return insn; | |
1590 | } | |
1591 | ||
1592 | ||
1593 | /* find_format() gets a pointer to an entry in the format table. | |
1594 | It must look at all formats for an opcode and use the operands | |
1595 | to choose the correct one. Returns NULL on error. */ | |
1596 | ||
1597 | static struct d30v_format * | |
1598 | find_format (opcode, myops, fsize, cmp_hack) | |
1599 | struct d30v_opcode *opcode; | |
1600 | expressionS myops[]; | |
1601 | int fsize; | |
1602 | int cmp_hack; | |
1603 | { | |
1604 | int numops, match, index, i=0, j, k; | |
1605 | struct d30v_format *fm; | |
1606 | ||
1607 | if (opcode == NULL) | |
1608 | return NULL; | |
1609 | ||
1610 | /* Get all the operands and save them as expressions. */ | |
1611 | numops = get_operands (myops, cmp_hack); | |
1612 | ||
1613 | while ((index = opcode->format[i++]) != 0) | |
1614 | { | |
1615 | if (fsize == FORCE_SHORT && index >= LONG) | |
1616 | continue; | |
1617 | ||
1618 | if (fsize == FORCE_LONG && index < LONG) | |
1619 | continue; | |
1620 | ||
1621 | fm = (struct d30v_format *)&d30v_format_table[index]; | |
1622 | k = index; | |
1623 | while (fm->form == index) | |
1624 | { | |
1625 | match = 1; | |
1626 | /* Now check the operands for compatibility. */ | |
1627 | for (j = 0; match && fm->operands[j]; j++) | |
1628 | { | |
1629 | int flags = d30v_operand_table[fm->operands[j]].flags; | |
1630 | int bits = d30v_operand_table[fm->operands[j]].bits; | |
1631 | int X_op = myops[j].X_op; | |
1632 | int num = myops[j].X_add_number; | |
1633 | ||
1634 | if (flags & OPERAND_SPECIAL) | |
1635 | break; | |
1636 | else if (X_op == O_illegal) | |
1637 | match = 0; | |
1638 | else if (flags & OPERAND_REG) | |
1639 | { | |
1640 | if (X_op != O_register | |
1641 | || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC)) | |
1642 | || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC)) | |
1643 | || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG)) | |
1644 | || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG)) | |
1645 | || ((flags & OPERAND_CONTROL) | |
1646 | && !(num & (OPERAND_CONTROL | OPERAND_FLAG)))) | |
1647 | { | |
1648 | match = 0; | |
1649 | } | |
1650 | } | |
1651 | else if (((flags & OPERAND_MINUS) | |
1652 | && (X_op != O_absent || num != OPERAND_MINUS)) | |
1653 | || ((flags & OPERAND_PLUS) | |
1654 | && (X_op != O_absent || num != OPERAND_PLUS)) | |
1655 | || ((flags & OPERAND_ATMINUS) | |
1656 | && (X_op != O_absent || num != OPERAND_ATMINUS)) | |
1657 | || ((flags & OPERAND_ATPAR) | |
1658 | && (X_op != O_absent || num != OPERAND_ATPAR)) | |
1659 | || ((flags & OPERAND_ATSIGN) | |
1660 | && (X_op != O_absent || num != OPERAND_ATSIGN))) | |
1661 | { | |
1662 | match=0; | |
1663 | } | |
1664 | else if (flags & OPERAND_NUM) | |
1665 | { | |
1666 | /* A number can be a constant or symbol expression. */ | |
1667 | ||
1668 | /* If we have found a register name, but that name also | |
1669 | matches a symbol, then re-parse the name as an expression. */ | |
1670 | if (X_op == O_register | |
1671 | && symbol_find ((char *) myops[j].X_op_symbol)) | |
1672 | { | |
1673 | input_line_pointer = (char *) myops[j].X_op_symbol; | |
1674 | expression (& myops[j]); | |
1675 | } | |
1676 | ||
1677 | /* Turn an expression into a symbol for later resolution. */ | |
1678 | if (X_op != O_absent && X_op != O_constant | |
1679 | && X_op != O_symbol && X_op != O_register | |
1680 | && X_op != O_big) | |
1681 | { | |
1682 | symbolS *sym = make_expr_symbol (&myops[j]); | |
1683 | myops[j].X_op = X_op = O_symbol; | |
1684 | myops[j].X_add_symbol = sym; | |
1685 | myops[j].X_add_number = num = 0; | |
1686 | } | |
1687 | ||
1688 | if (fm->form >= LONG) | |
1689 | { | |
1690 | /* If we're testing for a LONG format, either fits. */ | |
1691 | if (X_op != O_constant && X_op != O_symbol) | |
1692 | match = 0; | |
1693 | } | |
1694 | else if (fm->form < LONG | |
1695 | && ((fsize == FORCE_SHORT && X_op == O_symbol) | |
1696 | || (fm->form == SHORT_D2 && j == 0))) | |
1697 | match = 1; | |
1698 | /* This is the tricky part. Will the constant or symbol | |
1699 | fit into the space in the current format? */ | |
1700 | else if (X_op == O_constant) | |
1701 | { | |
1702 | if (check_range (num, bits, flags)) | |
1703 | match = 0; | |
1704 | } | |
1705 | else if (X_op == O_symbol | |
1706 | && S_IS_DEFINED (myops[j].X_add_symbol) | |
1707 | && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg | |
1708 | && opcode->reloc_flag == RELOC_PCREL) | |
1709 | { | |
1710 | /* If the symbol is defined, see if the value will fit | |
1711 | into the form we're considering. */ | |
1712 | fragS *f; | |
1713 | long value; | |
1714 | ||
1715 | /* Calculate the current address by running through the | |
1716 | previous frags and adding our current offset. */ | |
1717 | value = 0; | |
1718 | for (f = frchain_now->frch_root; f; f = f->fr_next) | |
1719 | value += f->fr_fix + f->fr_offset; | |
1720 | value = (S_GET_VALUE (myops[j].X_add_symbol) - value | |
1721 | - (obstack_next_free (&frchain_now->frch_obstack) | |
1722 | - frag_now->fr_literal)); | |
1723 | if (check_range (value, bits, flags)) | |
1724 | match = 0; | |
1725 | } | |
1726 | else | |
1727 | match = 0; | |
1728 | } | |
1729 | } | |
1730 | /* printf("through the loop: match=%d\n",match); */ | |
1731 | /* We're only done if the operands matched so far AND there | |
1732 | are no more to check. */ | |
1733 | if (match && myops[j].X_op == 0) | |
1734 | { | |
1735 | /* Final check - issue a warning if an odd numbered register | |
1736 | is used as the first register in an instruction that reads | |
1737 | or writes 2 registers. */ | |
1738 | ||
1739 | for (j = 0; fm->operands[j]; j++) | |
1740 | if (myops[j].X_op == O_register | |
1741 | && (myops[j].X_add_number & 1) | |
1742 | && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG)) | |
1743 | as_warn (\ | |
1744 | _("Odd numbered register used as target of multi-register instruction")); | |
1745 | ||
1746 | return fm; | |
1747 | } | |
1748 | fm = (struct d30v_format *)&d30v_format_table[++k]; | |
1749 | } | |
1750 | /* printf("trying another format: i=%d\n",i); */ | |
1751 | } | |
1752 | return NULL; | |
1753 | } | |
1754 | ||
1755 | /* if while processing a fixup, a reloc really needs to be created */ | |
1756 | /* then it is done here */ | |
1757 | ||
1758 | arelent * | |
1759 | tc_gen_reloc (seg, fixp) | |
1760 | asection *seg; | |
1761 | fixS *fixp; | |
1762 | { | |
1763 | arelent *reloc; | |
1764 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
310b5aa2 ILT |
1765 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
1766 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
1767 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
1768 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
1769 | if (reloc->howto == (reloc_howto_type *) NULL) | |
1770 | { | |
1771 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1772 | _("reloc %d not supported by object file format"), (int)fixp->fx_r_type); | |
1773 | return NULL; | |
1774 | } | |
1775 | reloc->addend = fixp->fx_addnumber; | |
1776 | return reloc; | |
1777 | } | |
1778 | ||
1779 | int | |
1780 | md_estimate_size_before_relax (fragp, seg) | |
1781 | fragS *fragp; | |
1782 | asection *seg; | |
1783 | { | |
1784 | abort (); | |
1785 | return 0; | |
1786 | } | |
1787 | ||
1788 | long | |
1789 | md_pcrel_from_section (fixp, sec) | |
1790 | fixS *fixp; | |
1791 | segT sec; | |
1792 | { | |
1793 | if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) || | |
1794 | (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
1795 | return 0; | |
1796 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1797 | } | |
1798 | ||
1799 | int | |
1800 | md_apply_fix3 (fixp, valuep, seg) | |
1801 | fixS * fixp; | |
1802 | valueT * valuep; | |
1803 | segT seg; | |
1804 | { | |
1805 | char * where; | |
1806 | unsigned long insn, insn2; | |
1807 | long value; | |
1808 | ||
1809 | if (fixp->fx_addsy == (symbolS *) NULL) | |
1810 | { | |
1811 | value = * valuep; | |
1812 | fixp->fx_done = 1; | |
1813 | } | |
1814 | else if (fixp->fx_pcrel) | |
1815 | value = * valuep; | |
1816 | else | |
1817 | { | |
1818 | value = fixp->fx_offset; | |
1819 | ||
1820 | if (fixp->fx_subsy != (symbolS *) NULL) | |
1821 | { | |
1822 | if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) | |
1823 | value -= S_GET_VALUE (fixp->fx_subsy); | |
1824 | else | |
1825 | { | |
1826 | /* We don't actually support subtracting a symbol. */ | |
1827 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1828 | _("expression too complex")); | |
1829 | } | |
1830 | } | |
1831 | } | |
1832 | ||
1833 | /* Fetch the instruction, insert the fully resolved operand | |
1834 | value, and stuff the instruction back again. */ | |
1835 | where = fixp->fx_frag->fr_literal + fixp->fx_where; | |
1836 | insn = bfd_getb32 ((unsigned char *) where); | |
1837 | ||
1838 | switch (fixp->fx_r_type) | |
1839 | { | |
1840 | case BFD_RELOC_8: /* Check for a bad .byte directive. */ | |
1841 | if (fixp->fx_addsy != NULL) | |
1842 | as_bad (_("line %d: unable to place address of symbol '%s' into a byte"), | |
1843 | fixp->fx_line, S_GET_NAME (fixp->fx_addsy)); | |
1844 | else if (((unsigned)value) > 0xff) | |
1845 | as_bad (_("line %d: unable to place value %x into a byte"), | |
1846 | fixp->fx_line, value); | |
1847 | else | |
1848 | * (unsigned char *) where = value; | |
1849 | break; | |
1850 | ||
1851 | case BFD_RELOC_16: /* Check for a bad .short directive. */ | |
1852 | if (fixp->fx_addsy != NULL) | |
1853 | as_bad (_("line %d: unable to place address of symbol '%s' into a short"), | |
1854 | fixp->fx_line, S_GET_NAME (fixp->fx_addsy)); | |
1855 | else if (((unsigned)value) > 0xffff) | |
1856 | as_bad (_("line %d: unable to place value %x into a short"), | |
1857 | fixp->fx_line, value); | |
1858 | else | |
1859 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1860 | break; | |
1861 | ||
1862 | case BFD_RELOC_64: /* Check for a bad .quad directive. */ | |
1863 | if (fixp->fx_addsy != NULL) | |
1864 | as_bad (_("line %d: unable to place address of symbol '%s' into a quad"), | |
1865 | fixp->fx_line, S_GET_NAME (fixp->fx_addsy)); | |
1866 | else | |
1867 | { | |
1868 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
1869 | bfd_putb32 (0, ((unsigned char *) where) + 4); | |
1870 | } | |
1871 | break; | |
1872 | ||
1873 | case BFD_RELOC_D30V_6: | |
1874 | check_size (value, 6, fixp->fx_file, fixp->fx_line); | |
1875 | insn |= value & 0x3F; | |
1876 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1877 | break; | |
1878 | ||
1879 | case BFD_RELOC_D30V_9_PCREL: | |
1880 | if (fixp->fx_where & 0x7) | |
1881 | { | |
1882 | if (fixp->fx_done) | |
1883 | value += 4; | |
1884 | else | |
1885 | fixp->fx_r_type = BFD_RELOC_D30V_9_PCREL_R; | |
1886 | } | |
1887 | check_size (value, 9, fixp->fx_file, fixp->fx_line); | |
1888 | insn |= ((value >> 3) & 0x3F) << 12; | |
1889 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1890 | break; | |
1891 | ||
1892 | case BFD_RELOC_D30V_15: | |
1893 | check_size (value, 15, fixp->fx_file, fixp->fx_line); | |
1894 | insn |= (value >> 3) & 0xFFF; | |
1895 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1896 | break; | |
1897 | ||
1898 | case BFD_RELOC_D30V_15_PCREL: | |
1899 | if (fixp->fx_where & 0x7) | |
1900 | { | |
1901 | if (fixp->fx_done) | |
1902 | value += 4; | |
1903 | else | |
1904 | fixp->fx_r_type = BFD_RELOC_D30V_15_PCREL_R; | |
1905 | } | |
1906 | check_size (value, 15, fixp->fx_file, fixp->fx_line); | |
1907 | insn |= (value >> 3) & 0xFFF; | |
1908 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1909 | break; | |
1910 | ||
1911 | case BFD_RELOC_D30V_21: | |
1912 | check_size (value, 21, fixp->fx_file, fixp->fx_line); | |
1913 | insn |= (value >> 3) & 0x3FFFF; | |
1914 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1915 | break; | |
1916 | ||
1917 | case BFD_RELOC_D30V_21_PCREL: | |
1918 | if (fixp->fx_where & 0x7) | |
1919 | { | |
1920 | if (fixp->fx_done) | |
1921 | value += 4; | |
1922 | else | |
1923 | fixp->fx_r_type = BFD_RELOC_D30V_21_PCREL_R; | |
1924 | } | |
1925 | check_size (value, 21, fixp->fx_file, fixp->fx_line); | |
1926 | insn |= (value >> 3) & 0x3FFFF; | |
1927 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1928 | break; | |
1929 | ||
1930 | case BFD_RELOC_D30V_32: | |
1931 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
1932 | insn |= (value >> 26) & 0x3F; /* top 6 bits */ | |
1933 | insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */ | |
1934 | insn2 |= value & 0x0003FFFF; /* bottom 18 bits */ | |
1935 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1936 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
1937 | break; | |
1938 | ||
1939 | case BFD_RELOC_D30V_32_PCREL: | |
1940 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
1941 | insn |= (value >> 26) & 0x3F; /* top 6 bits */ | |
1942 | insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */ | |
1943 | insn2 |= value & 0x0003FFFF; /* bottom 18 bits */ | |
1944 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1945 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
1946 | break; | |
1947 | ||
1948 | case BFD_RELOC_32: | |
1949 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
1950 | break; | |
1951 | ||
1952 | default: | |
1953 | as_bad (_("line %d: unknown relocation type: 0x%x"), | |
1954 | fixp->fx_line,fixp->fx_r_type); | |
1955 | } | |
1956 | ||
1957 | return 0; | |
1958 | } | |
1959 | ||
1960 | ||
1961 | /* d30v_cleanup() is called after the assembler has finished parsing the input | |
1962 | file or after a label is defined. Because the D30V assembler sometimes saves short | |
1963 | instructions to see if it can package them with the next instruction, there may | |
1964 | be a short instruction that still needs written. */ | |
1965 | int | |
1966 | d30v_cleanup (use_sequential) | |
1967 | int use_sequential; | |
1968 | { | |
1969 | segT seg; | |
1970 | subsegT subseg; | |
1971 | ||
1972 | if (prev_insn != -1) | |
1973 | { | |
1974 | seg = now_seg; | |
1975 | subseg = now_subseg; | |
1976 | subseg_set (prev_seg, prev_subseg); | |
1977 | write_1_short (&prev_opcode, (long)prev_insn, fixups->next, use_sequential); | |
1978 | subseg_set (seg, subseg); | |
1979 | prev_insn = -1; | |
1980 | if (use_sequential) | |
1981 | prev_mul32_p = false; | |
1982 | } | |
1983 | return 1; | |
1984 | } | |
1985 | ||
1986 | static void | |
1987 | d30v_number_to_chars (buf, value, n) | |
1988 | char *buf; /* Return 'nbytes' of chars here. */ | |
1989 | long long value; /* The value of the bits. */ | |
1990 | int n; /* Number of bytes in the output. */ | |
1991 | { | |
1992 | while (n--) | |
1993 | { | |
1994 | buf[n] = value & 0xff; | |
1995 | value >>= 8; | |
1996 | } | |
1997 | } | |
1998 | ||
1999 | ||
2000 | /* This function is called at the start of every line. */ | |
2001 | /* it checks to see if the first character is a '.' */ | |
2002 | /* which indicates the start of a pseudo-op. If it is, */ | |
2003 | /* then write out any unwritten instructions */ | |
2004 | ||
2005 | void | |
2006 | d30v_start_line () | |
2007 | { | |
2008 | char *c = input_line_pointer; | |
2009 | ||
2010 | while (isspace (*c)) | |
2011 | c++; | |
2012 | ||
2013 | if (*c == '.') | |
2014 | d30v_cleanup (false); | |
2015 | } | |
2016 | ||
2017 | static void | |
2018 | check_size (value, bits, file, line) | |
2019 | long value; | |
2020 | int bits; | |
2021 | char *file; | |
2022 | int line; | |
2023 | { | |
2024 | int tmp, max; | |
2025 | ||
2026 | if (value < 0) | |
2027 | tmp = ~value; | |
2028 | else | |
2029 | tmp = value; | |
2030 | ||
2031 | max = (1 << (bits - 1)) - 1; | |
2032 | ||
2033 | if (tmp > max) | |
2034 | as_bad_where (file, line, _("value too large to fit in %d bits"), bits); | |
2035 | ||
2036 | return; | |
2037 | } | |
2038 | ||
2039 | /* d30v_frob_label() is called when after a label is recognized. */ | |
2040 | ||
2041 | void | |
2042 | d30v_frob_label (lab) | |
2043 | symbolS *lab; | |
2044 | { | |
2045 | /* Emit any pending instructions. */ | |
2046 | d30v_cleanup (false); | |
2047 | ||
2048 | /* Update the label's address with the current output pointer. */ | |
7dcc9865 | 2049 | symbol_set_frag (lab, frag_now); |
252b5132 RH |
2050 | S_SET_VALUE (lab, (valueT) frag_now_fix ()); |
2051 | ||
2052 | /* Record this label for future adjustment after we find out what | |
2053 | kind of data it references, and the required alignment therewith. */ | |
2054 | d30v_last_label = lab; | |
2055 | } | |
2056 | ||
2057 | /* Hook into cons for capturing alignment changes. */ | |
2058 | ||
2059 | void | |
2060 | d30v_cons_align (size) | |
2061 | int size; | |
2062 | { | |
2063 | int log_size; | |
2064 | ||
2065 | log_size = 0; | |
2066 | while ((size >>= 1) != 0) | |
2067 | ++log_size; | |
2068 | ||
2069 | if (d30v_current_align < log_size) | |
2070 | d30v_align (log_size, (char *) NULL, NULL); | |
2071 | else if (d30v_current_align > log_size) | |
2072 | d30v_current_align = log_size; | |
2073 | d30v_last_label = NULL; | |
2074 | } | |
2075 | ||
2076 | /* Called internally to handle all alignment needs. This takes care | |
2077 | of eliding calls to frag_align if'n the cached current alignment | |
2078 | says we've already got it, as well as taking care of the auto-aligning | |
2079 | labels wrt code. */ | |
2080 | ||
2081 | static void | |
2082 | d30v_align (n, pfill, label) | |
2083 | int n; | |
2084 | char *pfill; | |
2085 | symbolS *label; | |
2086 | { | |
2087 | /* The front end is prone to changing segments out from under us | |
2088 | temporarily when -g is in effect. */ | |
2089 | int switched_seg_p = (d30v_current_align_seg != now_seg); | |
2090 | ||
2091 | /* Do not assume that if 'd30v_current_align >= n' and | |
2092 | '! switched_seg_p' that it is safe to avoid performing | |
2093 | this alignement request. The alignment of the current frag | |
2094 | can be changed under our feet, for example by a .ascii | |
2095 | directive in the source code. cf testsuite/gas/d30v/reloc.s */ | |
2096 | ||
2097 | d30v_cleanup (false); | |
2098 | ||
2099 | if (pfill == NULL) | |
2100 | { | |
2101 | if (n > 2 | |
2102 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
2103 | { | |
2104 | static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 }; | |
2105 | ||
2106 | /* First, make sure we're on a four-byte boundary, in case | |
2107 | someone has been putting .byte values the text section. */ | |
2108 | if (d30v_current_align < 2 || switched_seg_p) | |
2109 | frag_align (2, 0, 0); | |
2110 | frag_align_pattern (n, nop, sizeof nop, 0); | |
2111 | } | |
2112 | else | |
2113 | frag_align (n, 0, 0); | |
2114 | } | |
2115 | else | |
2116 | frag_align (n, *pfill, 0); | |
2117 | ||
2118 | if (!switched_seg_p) | |
2119 | d30v_current_align = n; | |
2120 | ||
2121 | if (label != NULL) | |
2122 | { | |
2123 | symbolS * sym; | |
2124 | int label_seen = false; | |
2125 | struct frag * old_frag; | |
2126 | valueT old_value; | |
2127 | valueT new_value; | |
2128 | ||
2129 | assert (S_GET_SEGMENT (label) == now_seg); | |
2130 | ||
7dcc9865 | 2131 | old_frag = symbol_get_frag (label); |
252b5132 RH |
2132 | old_value = S_GET_VALUE (label); |
2133 | new_value = (valueT) frag_now_fix (); | |
2134 | ||
2135 | /* It is possible to have more than one label at a particular | |
2136 | address, especially if debugging is enabled, so we must | |
2137 | take care to adjust all the labels at this address in this | |
2138 | fragment. To save time we search from the end of the symbol | |
2139 | list, backwards, since the symbols we are interested in are | |
2140 | almost certainly the ones that were most recently added. | |
2141 | Also to save time we stop searching once we have seen at least | |
2142 | one matching label, and we encounter a label that is no longer | |
2143 | in the target fragment. Note, this search is guaranteed to | |
2144 | find at least one match when sym == label, so no special case | |
2145 | code is necessary. */ | |
7dcc9865 | 2146 | for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym)) |
252b5132 | 2147 | { |
7dcc9865 ILT |
2148 | if (symbol_get_frag (sym) == old_frag |
2149 | && S_GET_VALUE (sym) == old_value) | |
252b5132 RH |
2150 | { |
2151 | label_seen = true; | |
7dcc9865 | 2152 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
2153 | S_SET_VALUE (sym, new_value); |
2154 | } | |
7dcc9865 | 2155 | else if (label_seen && symbol_get_frag (sym) != old_frag) |
252b5132 RH |
2156 | break; |
2157 | } | |
2158 | } | |
2159 | ||
2160 | record_alignment (now_seg, n); | |
2161 | } | |
2162 | ||
2163 | /* Handle the .align pseudo-op. This aligns to a power of two. We | |
2164 | hook here to latch the current alignment. */ | |
2165 | ||
2166 | static void | |
2167 | s_d30v_align (ignore) | |
2168 | int ignore; | |
2169 | { | |
2170 | int align; | |
2171 | char fill, *pfill = NULL; | |
2172 | long max_alignment = 15; | |
2173 | ||
2174 | align = get_absolute_expression (); | |
2175 | if (align > max_alignment) | |
2176 | { | |
2177 | align = max_alignment; | |
2178 | as_warn (_("Alignment too large: %d assumed"), align); | |
2179 | } | |
2180 | else if (align < 0) | |
2181 | { | |
2182 | as_warn (_("Alignment negative: 0 assumed")); | |
2183 | align = 0; | |
2184 | } | |
2185 | ||
2186 | if (*input_line_pointer == ',') | |
2187 | { | |
2188 | input_line_pointer++; | |
2189 | fill = get_absolute_expression (); | |
2190 | pfill = &fill; | |
2191 | } | |
2192 | ||
2193 | d30v_last_label = NULL; | |
2194 | d30v_align (align, pfill, NULL); | |
2195 | ||
2196 | demand_empty_rest_of_line (); | |
2197 | } | |
2198 | ||
2199 | /* Handle the .text pseudo-op. This is like the usual one, but it | |
2200 | clears the saved last label and resets known alignment. */ | |
2201 | ||
2202 | static void | |
2203 | s_d30v_text (i) | |
2204 | int i; | |
2205 | ||
2206 | { | |
2207 | s_text (i); | |
2208 | d30v_last_label = NULL; | |
2209 | d30v_current_align = 0; | |
2210 | d30v_current_align_seg = now_seg; | |
2211 | } | |
2212 | ||
2213 | /* Handle the .data pseudo-op. This is like the usual one, but it | |
2214 | clears the saved last label and resets known alignment. */ | |
2215 | ||
2216 | static void | |
2217 | s_d30v_data (i) | |
2218 | int i; | |
2219 | { | |
2220 | s_data (i); | |
2221 | d30v_last_label = NULL; | |
2222 | d30v_current_align = 0; | |
2223 | d30v_current_align_seg = now_seg; | |
2224 | } | |
2225 | ||
2226 | /* Handle the .section pseudo-op. This is like the usual one, but it | |
2227 | clears the saved last label and resets known alignment. */ | |
2228 | ||
2229 | static void | |
2230 | s_d30v_section (ignore) | |
2231 | int ignore; | |
2232 | { | |
2233 | obj_elf_section (ignore); | |
2234 | d30v_last_label = NULL; | |
2235 | d30v_current_align = 0; | |
2236 | d30v_current_align_seg = now_seg; | |
2237 | } |