Commit | Line | Data |
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252b5132 | 1 | /* tc-d30v.c -- Assembler code for the Mitsubishi D30V |
ec2655a6 | 2 | Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007 |
2132e3a3 | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
19 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
2fd5405a | 24 | #include "subsegs.h" |
252b5132 RH |
25 | #include "opcode/d30v.h" |
26 | ||
ea1562b3 NC |
27 | const char comment_chars[] = ";"; |
28 | const char line_comment_chars[] = "#"; | |
252b5132 | 29 | const char line_separator_chars[] = ""; |
ea1562b3 NC |
30 | const char *md_shortopts = "OnNcC"; |
31 | const char EXP_CHARS[] = "eE"; | |
32 | const char FLT_CHARS[] = "dD"; | |
252b5132 | 33 | |
ba09cd8d DN |
34 | #if HAVE_LIMITS_H |
35 | #include <limits.h> | |
36 | #endif | |
37 | ||
38 | #ifndef CHAR_BIT | |
39 | #define CHAR_BIT 8 | |
40 | #endif | |
41 | ||
252b5132 RH |
42 | #define NOP_MULTIPLY 1 |
43 | #define NOP_ALL 2 | |
44 | static int warn_nops = 0; | |
45 | static int Optimizing = 0; | |
46 | static int warn_register_name_conflicts = 1; | |
47 | ||
48 | #define FORCE_SHORT 1 | |
49 | #define FORCE_LONG 2 | |
50 | ||
51 | /* EXEC types. */ | |
52 | typedef enum _exec_type | |
53 | { | |
ea1562b3 NC |
54 | EXEC_UNKNOWN, /* No order specified. */ |
55 | EXEC_PARALLEL, /* Done in parallel (FM=00). */ | |
56 | EXEC_SEQ, /* Sequential (FM=01). */ | |
57 | EXEC_REVSEQ /* Reverse sequential (FM=10). */ | |
252b5132 RH |
58 | } exec_type_enum; |
59 | ||
2fd5405a | 60 | /* Fixups. */ |
ea1562b3 NC |
61 | #define MAX_INSN_FIXUPS 5 |
62 | ||
252b5132 RH |
63 | struct d30v_fixup |
64 | { | |
65 | expressionS exp; | |
66 | int operand; | |
67 | int pcrel; | |
68 | int size; | |
69 | bfd_reloc_code_real_type reloc; | |
70 | }; | |
71 | ||
72 | typedef struct _fixups | |
73 | { | |
74 | int fc; | |
75 | struct d30v_fixup fix[MAX_INSN_FIXUPS]; | |
76 | struct _fixups *next; | |
77 | } Fixups; | |
78 | ||
79 | static Fixups FixUps[2]; | |
80 | static Fixups *fixups; | |
81 | ||
82 | /* Whether current and previous instruction are word multiply insns. */ | |
83 | static int cur_mul32_p = 0; | |
84 | static int prev_mul32_p = 0; | |
85 | ||
86 | /* The flag_explicitly_parallel is true iff the instruction being assembled | |
87 | has been explicitly written as a parallel short-instruction pair by the | |
2fd5405a | 88 | human programmer. It is used in parallel_ok () to distinguish between |
252b5132 RH |
89 | those dangerous parallelizations attempted by the human, which are to be |
90 | allowed, and those attempted by the assembler, which are not. It is set | |
2fd5405a NC |
91 | from md_assemble (). */ |
92 | static int flag_explicitly_parallel = 0; | |
252b5132 RH |
93 | static int flag_xp_state = 0; |
94 | ||
95 | /* Whether current and previous left sub-instruction disables | |
96 | execution of right sub-instruction. */ | |
97 | static int cur_left_kills_right_p = 0; | |
98 | static int prev_left_kills_right_p = 0; | |
99 | ||
100 | /* The known current alignment of the current section. */ | |
101 | static int d30v_current_align; | |
102 | static segT d30v_current_align_seg; | |
103 | ||
104 | /* The last seen label in the current section. This is used to auto-align | |
2d2255b5 | 105 | labels preceding instructions. */ |
252b5132 RH |
106 | static symbolS *d30v_last_label; |
107 | ||
2fd5405a | 108 | /* Two nops. */ |
252b5132 RH |
109 | #define NOP_LEFT ((long long) NOP << 32) |
110 | #define NOP_RIGHT ((long long) NOP) | |
111 | #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT) | |
112 | ||
2fd5405a NC |
113 | struct option md_longopts[] = |
114 | { | |
252b5132 RH |
115 | {NULL, no_argument, NULL, 0} |
116 | }; | |
252b5132 | 117 | |
2fd5405a | 118 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 119 | |
252b5132 RH |
120 | /* Opcode hash table. */ |
121 | static struct hash_control *d30v_hash; | |
122 | ||
2fd5405a NC |
123 | /* Do a binary search of the pre_defined_registers array to see if |
124 | NAME is a valid regiter name. Return the register number from the | |
125 | array on success, or -1 on failure. */ | |
252b5132 RH |
126 | |
127 | static int | |
ea1562b3 | 128 | reg_name_search (char *name) |
252b5132 RH |
129 | { |
130 | int middle, low, high; | |
131 | int cmp; | |
132 | ||
133 | low = 0; | |
134 | high = reg_name_cnt () - 1; | |
135 | ||
136 | do | |
137 | { | |
138 | middle = (low + high) / 2; | |
139 | cmp = strcasecmp (name, pre_defined_registers[middle].name); | |
140 | if (cmp < 0) | |
141 | high = middle - 1; | |
142 | else if (cmp > 0) | |
143 | low = middle + 1; | |
144 | else | |
145 | { | |
146 | if (symbol_find (name) != NULL) | |
147 | { | |
148 | if (warn_register_name_conflicts) | |
149 | as_warn (_("Register name %s conflicts with symbol of the same name"), | |
150 | name); | |
151 | } | |
2fd5405a | 152 | |
252b5132 RH |
153 | return pre_defined_registers[middle].value; |
154 | } | |
155 | } | |
156 | while (low <= high); | |
2fd5405a | 157 | |
252b5132 RH |
158 | return -1; |
159 | } | |
160 | ||
2fd5405a NC |
161 | /* Check the string at input_line_pointer to see if it is a valid |
162 | register name. */ | |
252b5132 RH |
163 | |
164 | static int | |
ea1562b3 | 165 | register_name (expressionS *expressionP) |
252b5132 RH |
166 | { |
167 | int reg_number; | |
168 | char c, *p = input_line_pointer; | |
2fd5405a NC |
169 | |
170 | while (*p && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')') | |
252b5132 RH |
171 | p++; |
172 | ||
173 | c = *p; | |
174 | if (c) | |
175 | *p++ = 0; | |
176 | ||
2fd5405a | 177 | /* Look to see if it's in the register table. */ |
252b5132 | 178 | reg_number = reg_name_search (input_line_pointer); |
2fd5405a | 179 | if (reg_number >= 0) |
252b5132 RH |
180 | { |
181 | expressionP->X_op = O_register; | |
2fd5405a NC |
182 | /* Temporarily store a pointer to the string here. */ |
183 | expressionP->X_op_symbol = (symbolS *) input_line_pointer; | |
252b5132 RH |
184 | expressionP->X_add_number = reg_number; |
185 | input_line_pointer = p; | |
186 | return 1; | |
187 | } | |
188 | if (c) | |
2fd5405a | 189 | *(p - 1) = c; |
252b5132 RH |
190 | return 0; |
191 | } | |
192 | ||
252b5132 | 193 | static int |
ea1562b3 | 194 | check_range (unsigned long num, int bits, int flags) |
252b5132 RH |
195 | { |
196 | long min, max; | |
252b5132 | 197 | |
bf80011a RH |
198 | /* Don't bother checking 32-bit values. */ |
199 | if (bits == 32) | |
200 | { | |
2fd5405a | 201 | if (sizeof (unsigned long) * CHAR_BIT == 32) |
cc8a6dd0 | 202 | return 0; |
bf80011a RH |
203 | |
204 | /* We don't record signed or unsigned for 32-bit quantities. | |
205 | Allow either. */ | |
2fd5405a NC |
206 | min = -((unsigned long) 1 << (bits - 1)); |
207 | max = ((unsigned long) 1 << bits) - 1; | |
30cdfbed | 208 | return (long) num < min || (long) num > max; |
bf80011a | 209 | } |
252b5132 RH |
210 | |
211 | if (flags & OPERAND_SHIFT) | |
212 | { | |
2fd5405a | 213 | /* We know that all shifts are right by three bits. */ |
30cdfbed | 214 | num >>= 3; |
2fd5405a | 215 | |
252b5132 | 216 | if (flags & OPERAND_SIGNED) |
30cdfbed AM |
217 | { |
218 | unsigned long sign_bit = ((unsigned long) -1L >> 4) + 1; | |
219 | num = (num ^ sign_bit) - sign_bit; | |
220 | } | |
252b5132 RH |
221 | } |
222 | ||
223 | if (flags & OPERAND_SIGNED) | |
224 | { | |
2fd5405a NC |
225 | max = ((unsigned long) 1 << (bits - 1)) - 1; |
226 | min = - ((unsigned long) 1 << (bits - 1)); | |
30cdfbed | 227 | return (long) num > max || (long) num < min; |
252b5132 RH |
228 | } |
229 | else | |
230 | { | |
2fd5405a | 231 | max = ((unsigned long) 1 << bits) - 1; |
30cdfbed | 232 | return num > (unsigned long) max; |
252b5132 | 233 | } |
252b5132 RH |
234 | } |
235 | ||
252b5132 | 236 | void |
ea1562b3 | 237 | md_show_usage (FILE *stream) |
252b5132 RH |
238 | { |
239 | fprintf (stream, _("\nD30V options:\n\ | |
240 | -O Make adjacent short instructions parallel if possible.\n\ | |
241 | -n Warn about all NOPs inserted by the assembler.\n\ | |
242 | -N Warn about NOPs inserted after word multiplies.\n\ | |
243 | -c Warn about symbols whoes names match register names.\n\ | |
244 | -C Opposite of -C. -c is the default.\n")); | |
245 | } | |
246 | ||
247 | int | |
ea1562b3 | 248 | md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) |
252b5132 RH |
249 | { |
250 | switch (c) | |
251 | { | |
2fd5405a | 252 | /* Optimize. Will attempt to parallelize operations. */ |
252b5132 RH |
253 | case 'O': |
254 | Optimizing = 1; | |
255 | break; | |
256 | ||
257 | /* Warn about all NOPS that the assembler inserts. */ | |
258 | case 'n': | |
259 | warn_nops = NOP_ALL; | |
260 | break; | |
261 | ||
262 | /* Warn about the NOPS that the assembler inserts because of the | |
263 | multiply hazard. */ | |
264 | case 'N': | |
265 | warn_nops = NOP_MULTIPLY; | |
266 | break; | |
267 | ||
268 | case 'c': | |
269 | warn_register_name_conflicts = 1; | |
270 | break; | |
271 | ||
272 | case 'C': | |
273 | warn_register_name_conflicts = 0; | |
274 | break; | |
2fd5405a | 275 | |
252b5132 RH |
276 | default: |
277 | return 0; | |
278 | } | |
279 | return 1; | |
280 | } | |
281 | ||
282 | symbolS * | |
ea1562b3 | 283 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
284 | { |
285 | return 0; | |
286 | } | |
287 | ||
2fd5405a NC |
288 | /* Turn a string in input_line_pointer into a floating point constant |
289 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
290 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
291 | returned, or NULL on OK. */ | |
292 | ||
252b5132 | 293 | char * |
ea1562b3 | 294 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
295 | { |
296 | int prec; | |
297 | LITTLENUM_TYPE words[4]; | |
298 | char *t; | |
299 | int i; | |
2fd5405a | 300 | |
252b5132 RH |
301 | switch (type) |
302 | { | |
303 | case 'f': | |
304 | prec = 2; | |
305 | break; | |
306 | case 'd': | |
307 | prec = 4; | |
308 | break; | |
309 | default: | |
310 | *sizeP = 0; | |
311 | return _("bad call to md_atof"); | |
312 | } | |
313 | ||
314 | t = atof_ieee (input_line_pointer, type, words); | |
315 | if (t) | |
316 | input_line_pointer = t; | |
2fd5405a | 317 | |
252b5132 | 318 | *sizeP = prec * 2; |
2fd5405a | 319 | |
252b5132 RH |
320 | for (i = 0; i < prec; i++) |
321 | { | |
322 | md_number_to_chars (litP, (valueT) words[i], 2); | |
2fd5405a | 323 | litP += 2; |
252b5132 RH |
324 | } |
325 | return NULL; | |
326 | } | |
327 | ||
328 | void | |
ea1562b3 NC |
329 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
330 | asection *sec ATTRIBUTE_UNUSED, | |
331 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
332 | { |
333 | abort (); | |
334 | } | |
335 | ||
336 | valueT | |
ea1562b3 | 337 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
338 | { |
339 | int align = bfd_get_section_alignment (stdoutput, seg); | |
340 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
341 | } | |
342 | ||
252b5132 | 343 | void |
ea1562b3 | 344 | md_begin (void) |
252b5132 | 345 | { |
2fd5405a | 346 | struct d30v_opcode *opcode; |
252b5132 RH |
347 | d30v_hash = hash_new (); |
348 | ||
2fd5405a NC |
349 | /* Insert opcode names into a hash table. */ |
350 | for (opcode = (struct d30v_opcode *) d30v_opcode_table; opcode->name; opcode++) | |
252b5132 RH |
351 | hash_insert (d30v_hash, opcode->name, (char *) opcode); |
352 | ||
353 | fixups = &FixUps[0]; | |
354 | FixUps[0].next = &FixUps[1]; | |
355 | FixUps[1].next = &FixUps[0]; | |
356 | ||
357 | d30v_current_align_seg = now_seg; | |
358 | } | |
359 | ||
2fd5405a NC |
360 | /* Remove the postincrement or postdecrement operator ( '+' or '-' ) |
361 | from an expression. */ | |
252b5132 | 362 | |
2fd5405a | 363 | static int |
ea1562b3 | 364 | postfix (char *p) |
252b5132 | 365 | { |
2fd5405a | 366 | while (*p != '-' && *p != '+') |
252b5132 | 367 | { |
2fd5405a | 368 | if (*p == 0 || *p == '\n' || *p == '\r' || *p == ' ' || *p == ',') |
252b5132 RH |
369 | break; |
370 | p++; | |
371 | } | |
372 | ||
2fd5405a | 373 | if (*p == '-') |
252b5132 RH |
374 | { |
375 | *p = ' '; | |
2fd5405a | 376 | return -1; |
252b5132 | 377 | } |
81d4177b | 378 | |
2fd5405a | 379 | if (*p == '+') |
252b5132 RH |
380 | { |
381 | *p = ' '; | |
2fd5405a | 382 | return 1; |
252b5132 RH |
383 | } |
384 | ||
2fd5405a | 385 | return 0; |
252b5132 RH |
386 | } |
387 | ||
2fd5405a | 388 | static bfd_reloc_code_real_type |
ea1562b3 | 389 | get_reloc (struct d30v_operand *op, int rel_flag) |
252b5132 RH |
390 | { |
391 | switch (op->bits) | |
392 | { | |
393 | case 6: | |
394 | if (op->flags & OPERAND_SHIFT) | |
395 | return BFD_RELOC_D30V_9_PCREL; | |
396 | else | |
397 | return BFD_RELOC_D30V_6; | |
398 | break; | |
399 | case 12: | |
400 | if (!(op->flags & OPERAND_SHIFT)) | |
401 | as_warn (_("unexpected 12-bit reloc type")); | |
402 | if (rel_flag == RELOC_PCREL) | |
403 | return BFD_RELOC_D30V_15_PCREL; | |
404 | else | |
405 | return BFD_RELOC_D30V_15; | |
406 | case 18: | |
407 | if (!(op->flags & OPERAND_SHIFT)) | |
408 | as_warn (_("unexpected 18-bit reloc type")); | |
409 | if (rel_flag == RELOC_PCREL) | |
410 | return BFD_RELOC_D30V_21_PCREL; | |
411 | else | |
412 | return BFD_RELOC_D30V_21; | |
413 | case 32: | |
414 | if (rel_flag == RELOC_PCREL) | |
415 | return BFD_RELOC_D30V_32_PCREL; | |
416 | else | |
417 | return BFD_RELOC_D30V_32; | |
418 | default: | |
419 | return 0; | |
420 | } | |
421 | } | |
422 | ||
2fd5405a | 423 | /* Parse a string of operands and return an array of expressions. */ |
252b5132 RH |
424 | |
425 | static int | |
ea1562b3 | 426 | get_operands (expressionS exp[], int cmp_hack) |
252b5132 RH |
427 | { |
428 | char *p = input_line_pointer; | |
429 | int numops = 0; | |
430 | int post = 0; | |
431 | ||
432 | if (cmp_hack) | |
433 | { | |
434 | exp[numops].X_op = O_absent; | |
435 | exp[numops++].X_add_number = cmp_hack - 1; | |
436 | } | |
437 | ||
2fd5405a | 438 | while (*p) |
252b5132 | 439 | { |
2fd5405a | 440 | while (*p == ' ' || *p == '\t' || *p == ',') |
252b5132 | 441 | p++; |
81d4177b | 442 | |
2fd5405a NC |
443 | if (*p == 0 || *p == '\n' || *p == '\r') |
444 | break; | |
445 | ||
446 | if (*p == '@') | |
252b5132 RH |
447 | { |
448 | p++; | |
449 | exp[numops].X_op = O_absent; | |
2fd5405a | 450 | if (*p == '(') |
252b5132 RH |
451 | { |
452 | p++; | |
453 | exp[numops].X_add_number = OPERAND_ATPAR; | |
454 | post = postfix (p); | |
455 | } | |
2fd5405a | 456 | else if (*p == '-') |
252b5132 RH |
457 | { |
458 | p++; | |
459 | exp[numops].X_add_number = OPERAND_ATMINUS; | |
460 | } | |
461 | else | |
462 | { | |
463 | exp[numops].X_add_number = OPERAND_ATSIGN; | |
464 | post = postfix (p); | |
465 | } | |
466 | numops++; | |
467 | continue; | |
468 | } | |
469 | ||
2fd5405a | 470 | if (*p == ')') |
252b5132 | 471 | { |
2fd5405a | 472 | /* Just skip the trailing paren. */ |
252b5132 RH |
473 | p++; |
474 | continue; | |
475 | } | |
476 | ||
477 | input_line_pointer = p; | |
478 | ||
2fd5405a | 479 | /* Check to see if it might be a register name. */ |
252b5132 RH |
480 | if (!register_name (&exp[numops])) |
481 | { | |
2fd5405a | 482 | /* Parse as an expression. */ |
252b5132 RH |
483 | expression (&exp[numops]); |
484 | } | |
485 | ||
2fd5405a | 486 | if (exp[numops].X_op == O_illegal) |
252b5132 | 487 | as_bad (_("illegal operand")); |
2fd5405a | 488 | else if (exp[numops].X_op == O_absent) |
252b5132 RH |
489 | as_bad (_("missing operand")); |
490 | ||
491 | numops++; | |
492 | p = input_line_pointer; | |
493 | ||
2fd5405a | 494 | switch (post) |
252b5132 | 495 | { |
2fd5405a NC |
496 | case -1: |
497 | /* Postdecrement mode. */ | |
252b5132 RH |
498 | exp[numops].X_op = O_absent; |
499 | exp[numops++].X_add_number = OPERAND_MINUS; | |
500 | break; | |
2fd5405a NC |
501 | case 1: |
502 | /* Postincrement mode. */ | |
252b5132 RH |
503 | exp[numops].X_op = O_absent; |
504 | exp[numops++].X_add_number = OPERAND_PLUS; | |
505 | break; | |
506 | } | |
507 | post = 0; | |
508 | } | |
509 | ||
510 | exp[numops].X_op = 0; | |
81d4177b | 511 | |
2fd5405a | 512 | return numops; |
252b5132 RH |
513 | } |
514 | ||
2fd5405a NC |
515 | /* Generate the instruction. |
516 | It does everything but write the FM bits. */ | |
252b5132 RH |
517 | |
518 | static long long | |
ea1562b3 | 519 | build_insn (struct d30v_insn *opcode, expressionS *opers) |
252b5132 RH |
520 | { |
521 | int i, length, bits, shift, flags; | |
2fd5405a | 522 | unsigned long number, id = 0; |
252b5132 RH |
523 | long long insn; |
524 | struct d30v_opcode *op = opcode->op; | |
525 | struct d30v_format *form = opcode->form; | |
526 | ||
2fd5405a NC |
527 | insn = |
528 | opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18; | |
252b5132 | 529 | |
2fd5405a NC |
530 | for (i = 0; form->operands[i]; i++) |
531 | { | |
252b5132 RH |
532 | flags = d30v_operand_table[form->operands[i]].flags; |
533 | ||
2fd5405a NC |
534 | /* Must be a register or number. */ |
535 | if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM) | |
536 | && !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL)) | |
252b5132 RH |
537 | continue; |
538 | ||
539 | bits = d30v_operand_table[form->operands[i]].bits; | |
540 | if (flags & OPERAND_SHIFT) | |
541 | bits += 3; | |
542 | ||
543 | length = d30v_operand_table[form->operands[i]].length; | |
544 | shift = 12 - d30v_operand_table[form->operands[i]].position; | |
545 | if (opers[i].X_op != O_symbol) | |
546 | number = opers[i].X_add_number; | |
547 | else | |
548 | number = 0; | |
549 | if (flags & OPERAND_REG) | |
550 | { | |
2fd5405a | 551 | /* Check for mvfsys or mvtsys control registers. */ |
252b5132 RH |
552 | if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG) |
553 | { | |
2fd5405a | 554 | /* PSWL or PSWH. */ |
252b5132 RH |
555 | id = (number & 0x7f) - MAX_CONTROL_REG; |
556 | number = 0; | |
557 | } | |
558 | else if (number & OPERAND_FLAG) | |
ea1562b3 NC |
559 | /* NUMBER is a flag register. */ |
560 | id = 3; | |
561 | ||
252b5132 RH |
562 | number &= 0x7F; |
563 | } | |
564 | else if (flags & OPERAND_SPECIAL) | |
ea1562b3 | 565 | number = id; |
252b5132 | 566 | |
2fd5405a NC |
567 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant |
568 | && !(flags & OPERAND_NAME)) | |
252b5132 | 569 | { |
2fd5405a | 570 | /* Now create a fixup. */ |
252b5132 RH |
571 | if (fixups->fc >= MAX_INSN_FIXUPS) |
572 | as_fatal (_("too many fixups")); | |
573 | ||
2fd5405a NC |
574 | fixups->fix[fixups->fc].reloc = |
575 | get_reloc ((struct d30v_operand *) &d30v_operand_table[form->operands[i]], op->reloc_flag); | |
252b5132 RH |
576 | fixups->fix[fixups->fc].size = 4; |
577 | fixups->fix[fixups->fc].exp = opers[i]; | |
578 | fixups->fix[fixups->fc].operand = form->operands[i]; | |
579 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL) | |
580 | fixups->fix[fixups->fc].pcrel = RELOC_PCREL; | |
581 | else | |
582 | fixups->fix[fixups->fc].pcrel = op->reloc_flag; | |
583 | (fixups->fc)++; | |
584 | } | |
585 | ||
2fd5405a | 586 | /* Truncate to the proper number of bits. */ |
252b5132 | 587 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) |
ebf19f1b | 588 | as_bad (_("operand out of range: %ld"), number); |
252b5132 RH |
589 | if (bits < 31) |
590 | number &= 0x7FFFFFFF >> (31 - bits); | |
591 | if (flags & OPERAND_SHIFT) | |
592 | number >>= 3; | |
593 | if (bits == 32) | |
594 | { | |
2fd5405a | 595 | /* It's a LONG instruction. */ |
ea1562b3 NC |
596 | insn |= ((number & 0xffffffff) >> 26); /* Top 6 bits. */ |
597 | insn <<= 32; /* Shift the first word over. */ | |
598 | insn |= ((number & 0x03FC0000) << 2); /* Next 8 bits. */ | |
599 | insn |= number & 0x0003FFFF; /* Bottom 18 bits. */ | |
252b5132 RH |
600 | } |
601 | else | |
602 | insn |= number << shift; | |
603 | } | |
81d4177b | 604 | |
252b5132 RH |
605 | return insn; |
606 | } | |
607 | ||
ea1562b3 NC |
608 | static void |
609 | d30v_number_to_chars (char *buf, /* Return 'nbytes' of chars here. */ | |
610 | long long value, /* The value of the bits. */ | |
611 | int n) /* Number of bytes in the output. */ | |
612 | { | |
613 | while (n--) | |
614 | { | |
615 | buf[n] = value & 0xff; | |
616 | value >>= 8; | |
617 | } | |
618 | } | |
619 | ||
2fd5405a | 620 | /* Write out a long form instruction. */ |
252b5132 | 621 | |
252b5132 | 622 | static void |
ea1562b3 NC |
623 | write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED, |
624 | long long insn, | |
625 | Fixups *fx) | |
252b5132 RH |
626 | { |
627 | int i, where; | |
628 | char *f = frag_more (8); | |
629 | ||
630 | insn |= FM11; | |
631 | d30v_number_to_chars (f, insn, 8); | |
632 | ||
2fd5405a | 633 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
634 | { |
635 | if (fx->fix[i].reloc) | |
2fd5405a NC |
636 | { |
637 | where = f - frag_now->fr_literal; | |
ea1562b3 NC |
638 | fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp), |
639 | fx->fix[i].pcrel, fx->fix[i].reloc); | |
252b5132 RH |
640 | } |
641 | } | |
81d4177b | 642 | |
252b5132 RH |
643 | fx->fc = 0; |
644 | } | |
645 | ||
252b5132 | 646 | /* Write out a short form instruction by itself. */ |
2fd5405a | 647 | |
252b5132 | 648 | static void |
ea1562b3 NC |
649 | write_1_short (struct d30v_insn *opcode, |
650 | long long insn, | |
651 | Fixups *fx, | |
652 | int use_sequential) | |
252b5132 RH |
653 | { |
654 | char *f = frag_more (8); | |
655 | int i, where; | |
656 | ||
657 | if (warn_nops == NOP_ALL) | |
658 | as_warn (_("%s NOP inserted"), use_sequential ? | |
659 | _("sequential") : _("parallel")); | |
660 | ||
2fd5405a | 661 | /* The other container needs to be NOP. */ |
252b5132 RH |
662 | if (use_sequential) |
663 | { | |
664 | /* Use a sequential NOP rather than a parallel one, | |
665 | as the current instruction is a FLAG_MUL32 type one | |
666 | and the next instruction is a load. */ | |
2fd5405a | 667 | |
252b5132 | 668 | /* According to 4.3.1: for FM=01, sub-instructions performed |
2fd5405a | 669 | only by IU cannot be encoded in L-container. */ |
252b5132 | 670 | if (opcode->op->unit == IU) |
2fd5405a NC |
671 | /* Right then left. */ |
672 | insn |= FM10 | NOP_LEFT; | |
252b5132 | 673 | else |
2fd5405a NC |
674 | /* Left then right. */ |
675 | insn = FM01 | (insn << 32) | NOP_RIGHT; | |
252b5132 RH |
676 | } |
677 | else | |
678 | { | |
679 | /* According to 4.3.1: for FM=00, sub-instructions performed | |
2fd5405a | 680 | only by IU cannot be encoded in L-container. */ |
252b5132 | 681 | if (opcode->op->unit == IU) |
2fd5405a NC |
682 | /* Right container. */ |
683 | insn |= FM00 | NOP_LEFT; | |
252b5132 | 684 | else |
2fd5405a NC |
685 | /* Left container. */ |
686 | insn = FM00 | (insn << 32) | NOP_RIGHT; | |
252b5132 RH |
687 | } |
688 | ||
689 | d30v_number_to_chars (f, insn, 8); | |
690 | ||
2fd5405a | 691 | for (i = 0; i < fx->fc; i++) |
252b5132 RH |
692 | { |
693 | if (fx->fix[i].reloc) | |
2fd5405a NC |
694 | { |
695 | where = f - frag_now->fr_literal; | |
252b5132 | 696 | fix_new_exp (frag_now, |
2fd5405a | 697 | where, |
252b5132 RH |
698 | fx->fix[i].size, |
699 | &(fx->fix[i].exp), | |
700 | fx->fix[i].pcrel, | |
701 | fx->fix[i].reloc); | |
702 | } | |
703 | } | |
81d4177b | 704 | |
252b5132 RH |
705 | fx->fc = 0; |
706 | } | |
707 | ||
2fd5405a NC |
708 | /* Check 2 instructions and determine if they can be safely |
709 | executed in parallel. Return 1 if they can be. */ | |
252b5132 | 710 | |
252b5132 | 711 | static int |
ea1562b3 NC |
712 | parallel_ok (struct d30v_insn *op1, |
713 | unsigned long insn1, | |
714 | struct d30v_insn *op2, | |
715 | unsigned long insn2, | |
716 | exec_type_enum exec_type) | |
252b5132 RH |
717 | { |
718 | int i, j, shift, regno, bits, ecc; | |
719 | unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2; | |
720 | unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2]; | |
721 | struct d30v_format *f; | |
722 | struct d30v_opcode *op; | |
723 | ||
2fd5405a | 724 | /* Section 4.3: Both instructions must not be IU or MU only. */ |
252b5132 RH |
725 | if ((op1->op->unit == IU && op2->op->unit == IU) |
726 | || (op1->op->unit == MU && op2->op->unit == MU)) | |
727 | return 0; | |
728 | ||
2fd5405a | 729 | /* First instruction must not be a jump to safely optimize, unless this |
252b5132 RH |
730 | is an explicit parallel operation. */ |
731 | if (exec_type != EXEC_PARALLEL | |
732 | && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR))) | |
733 | return 0; | |
734 | ||
735 | /* If one instruction is /TX or /XT and the other is /FX or /XF respectively, | |
736 | then it is safe to allow the two to be done as parallel ops, since only | |
737 | one will ever be executed at a time. */ | |
738 | if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX) | |
739 | || (op1->ecc == ECC_FX && op2->ecc == ECC_TX) | |
740 | || (op1->ecc == ECC_XT && op2->ecc == ECC_XF) | |
741 | || (op1->ecc == ECC_XF && op2->ecc == ECC_XT)) | |
2fd5405a | 742 | return 1; |
252b5132 RH |
743 | |
744 | /* [0] r0-r31 | |
745 | [1] r32-r63 | |
2fd5405a | 746 | [2] a0, a1, flag registers. */ |
252b5132 RH |
747 | for (j = 0; j < 2; j++) |
748 | { | |
749 | if (j == 0) | |
750 | { | |
751 | f = op1->form; | |
752 | op = op1->op; | |
753 | ecc = op1->ecc; | |
754 | ins = insn1; | |
755 | } | |
756 | else | |
757 | { | |
758 | f = op2->form; | |
759 | op = op2->op; | |
760 | ecc = op2->ecc; | |
761 | ins = insn2; | |
762 | } | |
81d4177b | 763 | |
252b5132 RH |
764 | flag_reg[j] = 0; |
765 | mod_reg[j][0] = mod_reg[j][1] = 0; | |
766 | used_reg[j][0] = used_reg[j][1] = 0; | |
767 | ||
768 | if (flag_explicitly_parallel) | |
769 | { | |
770 | /* For human specified parallel instructions we have been asked | |
771 | to ignore the possibility that both instructions could modify | |
772 | bits in the PSW, so we initialise the mod & used arrays to 0. | |
773 | We have been asked, however, to refuse to allow parallel | |
774 | instructions which explicitly set the same flag register, | |
775 | eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test | |
776 | for the use of a flag register and set a bit in the mod or used | |
777 | array appropriately. */ | |
252b5132 RH |
778 | mod_reg[j][2] = 0; |
779 | used_reg[j][2] = 0; | |
780 | } | |
781 | else | |
782 | { | |
783 | mod_reg[j][2] = (op->flags_set & FLAG_ALL); | |
784 | used_reg[j][2] = (op->flags_used & FLAG_ALL); | |
785 | } | |
2fd5405a NC |
786 | |
787 | /* BSR/JSR always sets R62. */ | |
252b5132 | 788 | if (op->flags_used & FLAG_JSR) |
2fd5405a | 789 | mod_reg[j][1] = (1L << (62 - 32)); |
252b5132 | 790 | |
2fd5405a | 791 | /* Conditional execution affects the flags_used. */ |
252b5132 RH |
792 | switch (ecc) |
793 | { | |
794 | case ECC_TX: | |
795 | case ECC_FX: | |
796 | used_reg[j][2] |= flag_reg[j] = FLAG_0; | |
797 | break; | |
798 | ||
799 | case ECC_XT: | |
800 | case ECC_XF: | |
801 | used_reg[j][2] |= flag_reg[j] = FLAG_1; | |
802 | break; | |
803 | ||
804 | case ECC_TT: | |
805 | case ECC_TF: | |
806 | used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1); | |
807 | break; | |
808 | } | |
809 | ||
810 | for (i = 0; f->operands[i]; i++) | |
811 | { | |
812 | flags = d30v_operand_table[f->operands[i]].flags; | |
813 | shift = 12 - d30v_operand_table[f->operands[i]].position; | |
814 | bits = d30v_operand_table[f->operands[i]].bits; | |
815 | if (bits == 32) | |
816 | mask = 0xffffffff; | |
817 | else | |
818 | mask = 0x7FFFFFFF >> (31 - bits); | |
819 | ||
820 | if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS)) | |
821 | { | |
2fd5405a NC |
822 | /* This is a post-increment or post-decrement. |
823 | The previous register needs to be marked as modified. */ | |
824 | shift = 12 - d30v_operand_table[f->operands[i - 1]].position; | |
252b5132 RH |
825 | regno = (ins >> shift) & 0x3f; |
826 | if (regno >= 32) | |
827 | mod_reg[j][1] |= 1L << (regno - 32); | |
828 | else | |
829 | mod_reg[j][0] |= 1L << regno; | |
830 | } | |
831 | else if (flags & OPERAND_REG) | |
832 | { | |
833 | regno = (ins >> shift) & mask; | |
2fd5405a NC |
834 | /* The memory write functions don't have a destination |
835 | register. */ | |
252b5132 RH |
836 | if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM)) |
837 | { | |
2fd5405a | 838 | /* MODIFIED registers and flags. */ |
252b5132 RH |
839 | if (flags & OPERAND_ACC) |
840 | { | |
841 | if (regno == 0) | |
842 | mod_reg[j][2] |= FLAG_A0; | |
843 | else if (regno == 1) | |
844 | mod_reg[j][2] |= FLAG_A1; | |
845 | else | |
846 | abort (); | |
847 | } | |
848 | else if (flags & OPERAND_FLAG) | |
849 | mod_reg[j][2] |= 1L << regno; | |
850 | else if (!(flags & OPERAND_CONTROL)) | |
851 | { | |
852 | int r, z; | |
853 | ||
2fd5405a NC |
854 | /* Need to check if there are two destination |
855 | registers, for example ld2w. */ | |
252b5132 RH |
856 | if (flags & OPERAND_2REG) |
857 | z = 1; | |
858 | else | |
859 | z = 0; | |
860 | ||
861 | for (r = regno; r <= regno + z; r++) | |
2fd5405a | 862 | { |
252b5132 RH |
863 | if (r >= 32) |
864 | mod_reg[j][1] |= 1L << (r - 32); | |
865 | else | |
866 | mod_reg[j][0] |= 1L << r; | |
867 | } | |
868 | } | |
869 | } | |
870 | else | |
871 | { | |
2fd5405a | 872 | /* USED, but not modified registers and flags. */ |
252b5132 RH |
873 | if (flags & OPERAND_ACC) |
874 | { | |
875 | if (regno == 0) | |
876 | used_reg[j][2] |= FLAG_A0; | |
877 | else if (regno == 1) | |
878 | used_reg[j][2] |= FLAG_A1; | |
879 | else | |
880 | abort (); | |
881 | } | |
882 | else if (flags & OPERAND_FLAG) | |
883 | used_reg[j][2] |= 1L << regno; | |
884 | else if (!(flags & OPERAND_CONTROL)) | |
885 | { | |
886 | int r, z; | |
887 | ||
2fd5405a NC |
888 | /* Need to check if there are two source |
889 | registers, for example st2w. */ | |
252b5132 RH |
890 | if (flags & OPERAND_2REG) |
891 | z = 1; | |
892 | else | |
893 | z = 0; | |
894 | ||
895 | for (r = regno; r <= regno + z; r++) | |
2fd5405a | 896 | { |
252b5132 RH |
897 | if (r >= 32) |
898 | used_reg[j][1] |= 1L << (r - 32); | |
899 | else | |
900 | used_reg[j][0] |= 1L << r; | |
901 | } | |
902 | } | |
903 | } | |
904 | } | |
905 | } | |
906 | } | |
2fd5405a | 907 | |
252b5132 RH |
908 | flags_set1 = op1->op->flags_set; |
909 | flags_set2 = op2->op->flags_set; | |
910 | flags_used1 = op1->op->flags_used; | |
911 | flags_used2 = op2->op->flags_used; | |
912 | ||
25f2196d CC |
913 | /* Check for illegal combinations with ADDppp/SUBppp. */ |
914 | if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0 | |
252b5132 | 915 | && (flags_used2 & FLAG_ADDSUBppp) != 0) |
25f2196d | 916 | || ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0 |
252b5132 RH |
917 | && (flags_used1 & FLAG_ADDSUBppp) != 0)) |
918 | return 0; | |
919 | ||
920 | /* Load instruction combined with half-word multiply is illegal. */ | |
921 | if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16)) | |
922 | || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16))) | |
923 | return 0; | |
924 | ||
925 | /* Specifically allow add || add by removing carry, overflow bits dependency. | |
926 | This is safe, even if an addc follows since the IU takes the argument in | |
927 | the right container, and it writes its results last. | |
928 | However, don't paralellize add followed by addc or sub followed by | |
929 | subb. */ | |
252b5132 RH |
930 | if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA |
931 | && (used_reg[0][2] & ~flag_reg[0]) == 0 | |
932 | && (used_reg[1][2] & ~flag_reg[1]) == 0 | |
933 | && op1->op->unit == EITHER && op2->op->unit == EITHER) | |
934 | { | |
935 | mod_reg[0][2] = mod_reg[1][2] = 0; | |
936 | } | |
937 | ||
938 | for (j = 0; j < 3; j++) | |
939 | { | |
940 | /* If the second instruction depends on the first, we obviously | |
941 | cannot parallelize. Note, the mod flag implies use, so | |
942 | check that as well. */ | |
2fd5405a | 943 | /* If flag_explicitly_parallel is set, then the case of the |
252b5132 RH |
944 | second instruction using a register the first instruction |
945 | modifies is assumed to be okay; we trust the human. We | |
946 | don't trust the human if both instructions modify the same | |
947 | register but we do trust the human if they modify the same | |
2fd5405a | 948 | flags. */ |
252b5132 RH |
949 | /* We have now been requested not to trust the human if the |
950 | instructions modify the same flag registers either. */ | |
951 | if (flag_explicitly_parallel) | |
952 | { | |
953 | if ((mod_reg[0][j] & mod_reg[1][j]) != 0) | |
954 | return 0; | |
955 | } | |
956 | else | |
cc8a6dd0 | 957 | if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0) |
252b5132 RH |
958 | return 0; |
959 | } | |
960 | ||
961 | return 1; | |
962 | } | |
963 | ||
ea1562b3 NC |
964 | /* Write out a short form instruction if possible. |
965 | Return number of instructions not written out. */ | |
252b5132 | 966 | |
ea1562b3 NC |
967 | static int |
968 | write_2_short (struct d30v_insn *opcode1, | |
969 | long long insn1, | |
970 | struct d30v_insn *opcode2, | |
971 | long long insn2, | |
972 | exec_type_enum exec_type, | |
973 | Fixups *fx) | |
252b5132 | 974 | { |
ea1562b3 NC |
975 | long long insn = NOP2; |
976 | char *f; | |
977 | int i, j, where; | |
252b5132 | 978 | |
ea1562b3 NC |
979 | if (exec_type == EXEC_SEQ |
980 | && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)) | |
981 | && ((opcode1->op->flags_used & FLAG_DELAY) == 0) | |
982 | && ((opcode1->ecc == ECC_AL) || ! Optimizing)) | |
983 | { | |
984 | /* Unconditional, non-delayed branches kill instructions in | |
985 | the right bin. Conditional branches don't always but if | |
986 | we are not optimizing, then we have been asked to produce | |
987 | an error about such constructs. For the purposes of this | |
988 | test, subroutine calls are considered to be branches. */ | |
989 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
990 | return 1; | |
991 | } | |
252b5132 | 992 | |
ea1562b3 NC |
993 | /* Note: we do not have to worry about subroutine calls occurring |
994 | in the right hand container. The return address is always | |
995 | aligned to the next 64 bit boundary, be that 64 or 32 bit away. */ | |
996 | switch (exec_type) | |
252b5132 | 997 | { |
ea1562b3 NC |
998 | case EXEC_UNKNOWN: /* Order not specified. */ |
999 | if (Optimizing | |
1000 | && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type) | |
1001 | && ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU | |
1002 | || opcode1->op->unit == MU) | |
1003 | && | |
1004 | ( opcode2->op->unit == EITHER_BUT_PREFER_MU | |
1005 | || opcode2->op->unit == MU))) | |
252b5132 | 1006 | { |
ea1562b3 NC |
1007 | /* Parallel. */ |
1008 | exec_type = EXEC_PARALLEL; | |
1009 | ||
1010 | if (opcode1->op->unit == IU | |
1011 | || opcode2->op->unit == MU | |
1012 | || opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1013 | insn = FM00 | (insn2 << 32) | insn1; | |
252b5132 RH |
1014 | else |
1015 | { | |
ea1562b3 NC |
1016 | insn = FM00 | (insn1 << 32) | insn2; |
1017 | fx = fx->next; | |
252b5132 RH |
1018 | } |
1019 | } | |
ea1562b3 NC |
1020 | else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR) |
1021 | && ((opcode1->op->flags_used & FLAG_DELAY) == 0)) | |
1022 | || opcode1->op->flags_used & FLAG_RP) | |
1023 | { | |
1024 | /* We must emit (non-delayed) branch type instructions | |
1025 | on their own with nothing in the right container. */ | |
1026 | /* We must treat repeat instructions likewise, since the | |
1027 | following instruction has to be separate from the repeat | |
1028 | in order to be repeated. */ | |
1029 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
1030 | return 1; | |
1031 | } | |
1032 | else if (prev_left_kills_right_p) | |
1033 | { | |
1034 | /* The left instruction kils the right slot, so we | |
1035 | must leave it empty. */ | |
1036 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
1037 | return 1; | |
1038 | } | |
1039 | else if (opcode1->op->unit == IU) | |
1040 | { | |
1041 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1042 | { | |
1043 | /* Case 103810 is a request from Mitsubishi that opcodes | |
1044 | with EITHER_BUT_PREFER_MU should not be executed in | |
1045 | reverse sequential order. */ | |
1046 | write_1_short (opcode1, insn1, fx->next, FALSE); | |
1047 | return 1; | |
1048 | } | |
81d4177b | 1049 | |
ea1562b3 NC |
1050 | /* Reverse sequential. */ |
1051 | insn = FM10 | (insn2 << 32) | insn1; | |
1052 | exec_type = EXEC_REVSEQ; | |
1053 | } | |
1054 | else | |
252b5132 | 1055 | { |
ea1562b3 NC |
1056 | /* Sequential. */ |
1057 | insn = FM01 | (insn1 << 32) | insn2; | |
1058 | fx = fx->next; | |
1059 | exec_type = EXEC_SEQ; | |
1060 | } | |
1061 | break; | |
2fd5405a | 1062 | |
ea1562b3 NC |
1063 | case EXEC_PARALLEL: /* Parallel. */ |
1064 | flag_explicitly_parallel = flag_xp_state; | |
1065 | if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) | |
1066 | as_bad (_("Instructions may not be executed in parallel")); | |
1067 | else if (opcode1->op->unit == IU) | |
1068 | { | |
1069 | if (opcode2->op->unit == IU) | |
1070 | as_bad (_("Two IU instructions may not be executed in parallel")); | |
1071 | as_warn (_("Swapping instruction order")); | |
1072 | insn = FM00 | (insn2 << 32) | insn1; | |
1073 | } | |
1074 | else if (opcode2->op->unit == MU) | |
1075 | { | |
1076 | if (opcode1->op->unit == MU) | |
1077 | as_bad (_("Two MU instructions may not be executed in parallel")); | |
1078 | else if (opcode1->op->unit == EITHER_BUT_PREFER_MU) | |
1079 | as_warn (_("Executing %s in IU may not work"), opcode1->op->name); | |
1080 | as_warn (_("Swapping instruction order")); | |
1081 | insn = FM00 | (insn2 << 32) | insn1; | |
1082 | } | |
1083 | else | |
1084 | { | |
1085 | if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1086 | as_warn (_("Executing %s in IU may not work in parallel execution"), | |
1087 | opcode2->op->name); | |
2fd5405a | 1088 | |
ea1562b3 NC |
1089 | insn = FM00 | (insn1 << 32) | insn2; |
1090 | fx = fx->next; | |
252b5132 | 1091 | } |
ea1562b3 NC |
1092 | flag_explicitly_parallel = 0; |
1093 | break; | |
252b5132 | 1094 | |
ea1562b3 NC |
1095 | case EXEC_SEQ: /* Sequential. */ |
1096 | if (opcode1->op->unit == IU) | |
1097 | as_bad (_("IU instruction may not be in the left container")); | |
1098 | if (prev_left_kills_right_p) | |
1099 | as_bad (_("special left instruction `%s' kills instruction " | |
1100 | "`%s' in right container"), | |
1101 | opcode1->op->name, opcode2->op->name); | |
1102 | insn = FM01 | (insn1 << 32) | insn2; | |
1103 | fx = fx->next; | |
1104 | break; | |
252b5132 | 1105 | |
ea1562b3 NC |
1106 | case EXEC_REVSEQ: /* Reverse sequential. */ |
1107 | if (opcode2->op->unit == MU) | |
1108 | as_bad (_("MU instruction may not be in the right container")); | |
1109 | if (opcode1->op->unit == EITHER_BUT_PREFER_MU) | |
1110 | as_warn (_("Executing %s in reverse serial with %s may not work"), | |
1111 | opcode1->op->name, opcode2->op->name); | |
1112 | else if (opcode2->op->unit == EITHER_BUT_PREFER_MU) | |
1113 | as_warn (_("Executing %s in IU in reverse serial may not work"), | |
1114 | opcode2->op->name); | |
1115 | insn = FM10 | (insn1 << 32) | insn2; | |
1116 | fx = fx->next; | |
1117 | break; | |
1118 | ||
1119 | default: | |
1120 | as_fatal (_("unknown execution type passed to write_2_short()")); | |
252b5132 RH |
1121 | } |
1122 | ||
ea1562b3 NC |
1123 | f = frag_more (8); |
1124 | d30v_number_to_chars (f, insn, 8); | |
1125 | ||
1126 | /* If the previous instruction was a 32-bit multiply but it is put into a | |
1127 | parallel container, mark the current instruction as being a 32-bit | |
1128 | multiply. */ | |
1129 | if (prev_mul32_p && exec_type == EXEC_PARALLEL) | |
1130 | cur_mul32_p = 1; | |
1131 | ||
1132 | for (j = 0; j < 2; j++) | |
252b5132 | 1133 | { |
ea1562b3 | 1134 | for (i = 0; i < fx->fc; i++) |
252b5132 | 1135 | { |
ea1562b3 | 1136 | if (fx->fix[i].reloc) |
252b5132 | 1137 | { |
ea1562b3 | 1138 | where = (f - frag_now->fr_literal) + 4 * j; |
2fd5405a | 1139 | |
ea1562b3 NC |
1140 | fix_new_exp (frag_now, |
1141 | where, | |
1142 | fx->fix[i].size, | |
1143 | &(fx->fix[i].exp), | |
1144 | fx->fix[i].pcrel, | |
1145 | fx->fix[i].reloc); | |
252b5132 | 1146 | } |
252b5132 | 1147 | } |
ea1562b3 NC |
1148 | |
1149 | fx->fc = 0; | |
1150 | fx = fx->next; | |
252b5132 | 1151 | } |
2fd5405a | 1152 | |
ea1562b3 NC |
1153 | return 0; |
1154 | } | |
252b5132 | 1155 | |
ea1562b3 NC |
1156 | /* Get a pointer to an entry in the format table. |
1157 | It must look at all formats for an opcode and use the operands | |
1158 | to choose the correct one. Return NULL on error. */ | |
1159 | ||
1160 | static struct d30v_format * | |
1161 | find_format (struct d30v_opcode *opcode, | |
1162 | expressionS myops[], | |
1163 | int fsize, | |
1164 | int cmp_hack) | |
1165 | { | |
1166 | int numops, match, index, i = 0, j, k; | |
1167 | struct d30v_format *fm; | |
1168 | ||
1169 | if (opcode == NULL) | |
1170 | return NULL; | |
1171 | ||
1172 | /* Get all the operands and save them as expressions. */ | |
1173 | numops = get_operands (myops, cmp_hack); | |
1174 | ||
1175 | while ((index = opcode->format[i++]) != 0) | |
252b5132 | 1176 | { |
ea1562b3 NC |
1177 | if (fsize == FORCE_SHORT && index >= LONG) |
1178 | continue; | |
2fd5405a | 1179 | |
ea1562b3 NC |
1180 | if (fsize == FORCE_LONG && index < LONG) |
1181 | continue; | |
1182 | ||
1183 | fm = (struct d30v_format *) &d30v_format_table[index]; | |
1184 | k = index; | |
1185 | while (fm->form == index) | |
1186 | { | |
1187 | match = 1; | |
1188 | /* Now check the operands for compatibility. */ | |
1189 | for (j = 0; match && fm->operands[j]; j++) | |
1190 | { | |
1191 | int flags = d30v_operand_table[fm->operands[j]].flags; | |
1192 | int bits = d30v_operand_table[fm->operands[j]].bits; | |
1193 | int X_op = myops[j].X_op; | |
1194 | int num = myops[j].X_add_number; | |
1195 | ||
1196 | if (flags & OPERAND_SPECIAL) | |
1197 | break; | |
1198 | else if (X_op == O_illegal) | |
1199 | match = 0; | |
1200 | else if (flags & OPERAND_REG) | |
1201 | { | |
1202 | if (X_op != O_register | |
1203 | || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC)) | |
1204 | || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC)) | |
1205 | || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG)) | |
1206 | || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG)) | |
1207 | || ((flags & OPERAND_CONTROL) | |
1208 | && !(num & (OPERAND_CONTROL | OPERAND_FLAG)))) | |
1209 | match = 0; | |
1210 | } | |
1211 | else if (((flags & OPERAND_MINUS) | |
1212 | && (X_op != O_absent || num != OPERAND_MINUS)) | |
1213 | || ((flags & OPERAND_PLUS) | |
1214 | && (X_op != O_absent || num != OPERAND_PLUS)) | |
1215 | || ((flags & OPERAND_ATMINUS) | |
1216 | && (X_op != O_absent || num != OPERAND_ATMINUS)) | |
1217 | || ((flags & OPERAND_ATPAR) | |
1218 | && (X_op != O_absent || num != OPERAND_ATPAR)) | |
1219 | || ((flags & OPERAND_ATSIGN) | |
1220 | && (X_op != O_absent || num != OPERAND_ATSIGN))) | |
1221 | match = 0; | |
1222 | else if (flags & OPERAND_NUM) | |
1223 | { | |
1224 | /* A number can be a constant or symbol expression. */ | |
1225 | ||
1226 | /* If we have found a register name, but that name | |
1227 | also matches a symbol, then re-parse the name as | |
1228 | an expression. */ | |
1229 | if (X_op == O_register | |
1230 | && symbol_find ((char *) myops[j].X_op_symbol)) | |
1231 | { | |
1232 | input_line_pointer = (char *) myops[j].X_op_symbol; | |
1233 | expression (&myops[j]); | |
1234 | } | |
1235 | ||
1236 | /* Turn an expression into a symbol for later resolution. */ | |
1237 | if (X_op != O_absent && X_op != O_constant | |
1238 | && X_op != O_symbol && X_op != O_register | |
1239 | && X_op != O_big) | |
1240 | { | |
1241 | symbolS *sym = make_expr_symbol (&myops[j]); | |
1242 | myops[j].X_op = X_op = O_symbol; | |
1243 | myops[j].X_add_symbol = sym; | |
1244 | myops[j].X_add_number = num = 0; | |
1245 | } | |
1246 | ||
1247 | if (fm->form >= LONG) | |
1248 | { | |
1249 | /* If we're testing for a LONG format, either fits. */ | |
1250 | if (X_op != O_constant && X_op != O_symbol) | |
1251 | match = 0; | |
1252 | } | |
1253 | else if (fm->form < LONG | |
1254 | && ((fsize == FORCE_SHORT && X_op == O_symbol) | |
1255 | || (fm->form == SHORT_D2 && j == 0))) | |
1256 | match = 1; | |
1257 | ||
1258 | /* This is the tricky part. Will the constant or symbol | |
1259 | fit into the space in the current format? */ | |
1260 | else if (X_op == O_constant) | |
1261 | { | |
1262 | if (check_range (num, bits, flags)) | |
1263 | match = 0; | |
1264 | } | |
1265 | else if (X_op == O_symbol | |
1266 | && S_IS_DEFINED (myops[j].X_add_symbol) | |
1267 | && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg | |
1268 | && opcode->reloc_flag == RELOC_PCREL) | |
1269 | { | |
1270 | /* If the symbol is defined, see if the value will fit | |
1271 | into the form we're considering. */ | |
1272 | fragS *f; | |
1273 | long value; | |
1274 | ||
1275 | /* Calculate the current address by running through the | |
1276 | previous frags and adding our current offset. */ | |
1277 | value = 0; | |
1278 | for (f = frchain_now->frch_root; f; f = f->fr_next) | |
1279 | value += f->fr_fix + f->fr_offset; | |
1280 | value = (S_GET_VALUE (myops[j].X_add_symbol) - value | |
1281 | - (obstack_next_free (&frchain_now->frch_obstack) | |
1282 | - frag_now->fr_literal)); | |
1283 | if (check_range (value, bits, flags)) | |
1284 | match = 0; | |
1285 | } | |
1286 | else | |
1287 | match = 0; | |
1288 | } | |
1289 | } | |
1290 | /* We're only done if the operands matched so far AND there | |
1291 | are no more to check. */ | |
1292 | if (match && myops[j].X_op == 0) | |
1293 | { | |
1294 | /* Final check - issue a warning if an odd numbered register | |
1295 | is used as the first register in an instruction that reads | |
1296 | or writes 2 registers. */ | |
1297 | ||
1298 | for (j = 0; fm->operands[j]; j++) | |
1299 | if (myops[j].X_op == O_register | |
1300 | && (myops[j].X_add_number & 1) | |
1301 | && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG)) | |
1302 | as_warn (_("Odd numbered register used as target of multi-register instruction")); | |
1303 | ||
1304 | return fm; | |
1305 | } | |
1306 | fm = (struct d30v_format *) &d30v_format_table[++k]; | |
1307 | } | |
252b5132 | 1308 | } |
ea1562b3 | 1309 | return NULL; |
252b5132 RH |
1310 | } |
1311 | ||
2fd5405a NC |
1312 | /* Assemble a single instruction and return an opcode. |
1313 | Return -1 (an invalid opcode) on error. */ | |
252b5132 RH |
1314 | |
1315 | #define NAME_BUF_LEN 20 | |
1316 | ||
1317 | static long long | |
ea1562b3 NC |
1318 | do_assemble (char *str, |
1319 | struct d30v_insn *opcode, | |
1320 | int shortp, | |
1321 | int is_parallel) | |
252b5132 | 1322 | { |
2132e3a3 AM |
1323 | char *op_start; |
1324 | char *save; | |
1325 | char *op_end; | |
2fd5405a NC |
1326 | char name[NAME_BUF_LEN]; |
1327 | int cmp_hack; | |
1328 | int nlen = 0; | |
1329 | int fsize = (shortp ? FORCE_SHORT : 0); | |
1330 | expressionS myops[6]; | |
1331 | long long insn; | |
1332 | ||
1333 | /* Drop leading whitespace. */ | |
1334 | while (*str == ' ') | |
1335 | str++; | |
1336 | ||
1337 | /* Find the opcode end. */ | |
2132e3a3 | 1338 | for (op_start = op_end = str; |
2fd5405a | 1339 | *op_end |
252b5132 | 1340 | && nlen < (NAME_BUF_LEN - 1) |
2fd5405a | 1341 | && *op_end != '/' |
2132e3a3 | 1342 | && !is_end_of_line[(unsigned char) *op_end] && *op_end != ' '; |
252b5132 RH |
1343 | op_end++) |
1344 | { | |
3882b010 | 1345 | name[nlen] = TOLOWER (op_start[nlen]); |
252b5132 RH |
1346 | nlen++; |
1347 | } | |
1348 | ||
1349 | if (nlen == 0) | |
1350 | return -1; | |
1351 | ||
1352 | name[nlen] = 0; | |
1353 | ||
2fd5405a | 1354 | /* If there is an execution condition code, handle it. */ |
252b5132 RH |
1355 | if (*op_end == '/') |
1356 | { | |
1357 | int i = 0; | |
2fd5405a | 1358 | while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2)) |
252b5132 | 1359 | i++; |
2fd5405a | 1360 | |
252b5132 RH |
1361 | if (i == ECC_MAX) |
1362 | { | |
1363 | char tmp[4]; | |
1364 | strncpy (tmp, op_end + 1, 2); | |
1365 | tmp[2] = 0; | |
2fd5405a | 1366 | as_bad (_("unknown condition code: %s"), tmp); |
252b5132 RH |
1367 | return -1; |
1368 | } | |
252b5132 RH |
1369 | opcode->ecc = i; |
1370 | op_end += 3; | |
1371 | } | |
1372 | else | |
1373 | opcode->ecc = ECC_AL; | |
252b5132 | 1374 | |
2fd5405a | 1375 | /* CMP and CMPU change their name based on condition codes. */ |
252b5132 RH |
1376 | if (!strncmp (name, "cmp", 3)) |
1377 | { | |
2fd5405a NC |
1378 | int p, i; |
1379 | char **str = (char **) d30v_cc_names; | |
252b5132 RH |
1380 | if (name[3] == 'u') |
1381 | p = 4; | |
1382 | else | |
1383 | p = 3; | |
1384 | ||
2fd5405a | 1385 | for (i = 1; *str && strncmp (*str, &name[p], 2); i++, str++) |
252b5132 RH |
1386 | ; |
1387 | ||
2fd5405a | 1388 | /* cmpu only supports some condition codes. */ |
252b5132 RH |
1389 | if (p == 4) |
1390 | { | |
1391 | if (i < 3 || i > 6) | |
1392 | { | |
2fd5405a NC |
1393 | name[p + 2] = 0; |
1394 | as_bad (_("cmpu doesn't support condition code %s"), &name[p]); | |
252b5132 RH |
1395 | } |
1396 | } | |
1397 | ||
1398 | if (!*str) | |
1399 | { | |
2fd5405a NC |
1400 | name[p + 2] = 0; |
1401 | as_bad (_("unknown condition code: %s"), &name[p]); | |
252b5132 | 1402 | } |
2fd5405a | 1403 | |
252b5132 RH |
1404 | cmp_hack = i; |
1405 | name[p] = 0; | |
1406 | } | |
1407 | else | |
1408 | cmp_hack = 0; | |
252b5132 | 1409 | |
2fd5405a NC |
1410 | /* Need to look for .s or .l. */ |
1411 | if (name[nlen - 2] == '.') | |
252b5132 | 1412 | { |
2fd5405a | 1413 | switch (name[nlen - 1]) |
252b5132 RH |
1414 | { |
1415 | case 's': | |
1416 | fsize = FORCE_SHORT; | |
1417 | break; | |
1418 | case 'l': | |
1419 | fsize = FORCE_LONG; | |
1420 | break; | |
1421 | } | |
2fd5405a | 1422 | name[nlen - 2] = 0; |
252b5132 RH |
1423 | } |
1424 | ||
2fd5405a NC |
1425 | /* Find the first opcode with the proper name. */ |
1426 | opcode->op = (struct d30v_opcode *) hash_find (d30v_hash, name); | |
252b5132 RH |
1427 | if (opcode->op == NULL) |
1428 | { | |
2fd5405a | 1429 | as_bad (_("unknown opcode: %s"), name); |
252b5132 RH |
1430 | return -1; |
1431 | } | |
1432 | ||
1433 | save = input_line_pointer; | |
1434 | input_line_pointer = op_end; | |
1435 | while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack))) | |
1436 | { | |
1437 | opcode->op++; | |
1438 | if (opcode->op->name == NULL || strcmp (opcode->op->name, name)) | |
1439 | { | |
2fd5405a NC |
1440 | as_bad (_("operands for opcode `%s' do not match any valid format"), |
1441 | name); | |
252b5132 RH |
1442 | return -1; |
1443 | } | |
1444 | } | |
1445 | input_line_pointer = save; | |
1446 | ||
2fd5405a | 1447 | insn = build_insn (opcode, myops); |
252b5132 | 1448 | |
2d2255b5 | 1449 | /* Propagate multiply status. */ |
252b5132 RH |
1450 | if (insn != -1) |
1451 | { | |
1452 | if (is_parallel && prev_mul32_p) | |
1453 | cur_mul32_p = 1; | |
1454 | else | |
1455 | { | |
1456 | prev_mul32_p = cur_mul32_p; | |
1457 | cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0; | |
1458 | } | |
1459 | } | |
1460 | ||
2fd5405a | 1461 | /* Propagate left_kills_right status. */ |
252b5132 RH |
1462 | if (insn != -1) |
1463 | { | |
1464 | prev_left_kills_right_p = cur_left_kills_right_p; | |
1465 | ||
1466 | if (opcode->op->flags_set & FLAG_LKR) | |
1467 | { | |
1468 | cur_left_kills_right_p = 1; | |
2fd5405a | 1469 | |
252b5132 RH |
1470 | if (strcmp (opcode->op->name, "mvtsys") == 0) |
1471 | { | |
2fd5405a NC |
1472 | /* Left kills right for only mvtsys only for |
1473 | PSW/PSWH/PSWL/flags target. */ | |
252b5132 RH |
1474 | if ((myops[0].X_op == O_register) && |
1475 | ((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */ | |
1476 | (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */ | |
1477 | (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */ | |
1478 | (myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */ | |
1479 | (myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */ | |
1480 | (myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */ | |
1481 | (myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */ | |
1482 | (myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */ | |
1483 | (myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */ | |
1484 | (myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */ | |
1485 | (myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */ | |
1486 | { | |
1487 | cur_left_kills_right_p = 1; | |
1488 | } | |
1489 | else | |
1490 | { | |
2fd5405a NC |
1491 | /* Other mvtsys target registers don't kill right |
1492 | instruction. */ | |
252b5132 RH |
1493 | cur_left_kills_right_p = 0; |
1494 | } | |
1495 | } /* mvtsys */ | |
1496 | } | |
1497 | else | |
1498 | cur_left_kills_right_p = 0; | |
1499 | } | |
1500 | ||
1501 | return insn; | |
1502 | } | |
1503 | ||
ea1562b3 NC |
1504 | /* Called internally to handle all alignment needs. This takes care |
1505 | of eliding calls to frag_align if'n the cached current alignment | |
1506 | says we've already got it, as well as taking care of the auto-aligning | |
1507 | labels wrt code. */ | |
252b5132 | 1508 | |
ea1562b3 NC |
1509 | static void |
1510 | d30v_align (int n, char *pfill, symbolS *label) | |
252b5132 | 1511 | { |
ea1562b3 NC |
1512 | /* The front end is prone to changing segments out from under us |
1513 | temporarily when -g is in effect. */ | |
1514 | int switched_seg_p = (d30v_current_align_seg != now_seg); | |
2fd5405a | 1515 | |
ea1562b3 NC |
1516 | /* Do not assume that if 'd30v_current_align >= n' and |
1517 | '! switched_seg_p' that it is safe to avoid performing | |
1518 | this alignment request. The alignment of the current frag | |
1519 | can be changed under our feet, for example by a .ascii | |
1520 | directive in the source code. cf testsuite/gas/d30v/reloc.s */ | |
1521 | d30v_cleanup (FALSE); | |
252b5132 | 1522 | |
ea1562b3 | 1523 | if (pfill == NULL) |
252b5132 | 1524 | { |
ea1562b3 NC |
1525 | if (n > 2 |
1526 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
1527 | { | |
1528 | static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 }; | |
252b5132 | 1529 | |
ea1562b3 NC |
1530 | /* First, make sure we're on a four-byte boundary, in case |
1531 | someone has been putting .byte values the text section. */ | |
1532 | if (d30v_current_align < 2 || switched_seg_p) | |
1533 | frag_align (2, 0, 0); | |
1534 | frag_align_pattern (n, nop, sizeof nop, 0); | |
1535 | } | |
1536 | else | |
1537 | frag_align (n, 0, 0); | |
1538 | } | |
1539 | else | |
1540 | frag_align (n, *pfill, 0); | |
252b5132 | 1541 | |
ea1562b3 NC |
1542 | if (!switched_seg_p) |
1543 | d30v_current_align = n; | |
2fd5405a | 1544 | |
ea1562b3 NC |
1545 | if (label != NULL) |
1546 | { | |
1547 | symbolS *sym; | |
1548 | int label_seen = FALSE; | |
1549 | struct frag *old_frag; | |
1550 | valueT old_value; | |
1551 | valueT new_value; | |
252b5132 | 1552 | |
ea1562b3 | 1553 | assert (S_GET_SEGMENT (label) == now_seg); |
2fd5405a | 1554 | |
ea1562b3 NC |
1555 | old_frag = symbol_get_frag (label); |
1556 | old_value = S_GET_VALUE (label); | |
1557 | new_value = (valueT) frag_now_fix (); | |
252b5132 | 1558 | |
ea1562b3 NC |
1559 | /* It is possible to have more than one label at a particular |
1560 | address, especially if debugging is enabled, so we must | |
1561 | take care to adjust all the labels at this address in this | |
1562 | fragment. To save time we search from the end of the symbol | |
1563 | list, backwards, since the symbols we are interested in are | |
1564 | almost certainly the ones that were most recently added. | |
1565 | Also to save time we stop searching once we have seen at least | |
1566 | one matching label, and we encounter a label that is no longer | |
1567 | in the target fragment. Note, this search is guaranteed to | |
1568 | find at least one match when sym == label, so no special case | |
1569 | code is necessary. */ | |
1570 | for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym)) | |
1571 | { | |
1572 | if (symbol_get_frag (sym) == old_frag | |
1573 | && S_GET_VALUE (sym) == old_value) | |
1574 | { | |
1575 | label_seen = TRUE; | |
1576 | symbol_set_frag (sym, frag_now); | |
1577 | S_SET_VALUE (sym, new_value); | |
1578 | } | |
1579 | else if (label_seen && symbol_get_frag (sym) != old_frag) | |
1580 | break; | |
1581 | } | |
1582 | } | |
2fd5405a | 1583 | |
ea1562b3 NC |
1584 | record_alignment (now_seg, n); |
1585 | } | |
252b5132 | 1586 | |
ea1562b3 NC |
1587 | /* This is the main entry point for the machine-dependent assembler. |
1588 | STR points to a machine-dependent instruction. This function is | |
1589 | supposed to emit the frags/bytes it assembles to. For the D30V, it | |
1590 | mostly handles the special VLIW parsing and packing and leaves the | |
1591 | difficult stuff to do_assemble (). */ | |
1592 | ||
1593 | static long long prev_insn = -1; | |
1594 | static struct d30v_insn prev_opcode; | |
1595 | static subsegT prev_subseg; | |
1596 | static segT prev_seg = 0; | |
1597 | ||
1598 | void | |
1599 | md_assemble (char *str) | |
1600 | { | |
1601 | struct d30v_insn opcode; | |
1602 | long long insn; | |
1603 | /* Execution type; parallel, etc. */ | |
1604 | exec_type_enum extype = EXEC_UNKNOWN; | |
1605 | /* Saved extype. Used for multiline instructions. */ | |
1606 | static exec_type_enum etype = EXEC_UNKNOWN; | |
1607 | char *str2; | |
1608 | ||
1609 | if ((prev_insn != -1) && prev_seg | |
1610 | && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) | |
1611 | d30v_cleanup (FALSE); | |
1612 | ||
1613 | if (d30v_current_align < 3) | |
1614 | d30v_align (3, NULL, d30v_last_label); | |
1615 | else if (d30v_current_align > 3) | |
1616 | d30v_current_align = 3; | |
1617 | d30v_last_label = NULL; | |
1618 | ||
1619 | flag_explicitly_parallel = 0; | |
1620 | flag_xp_state = 0; | |
1621 | if (etype == EXEC_UNKNOWN) | |
1622 | { | |
1623 | /* Look for the special multiple instruction separators. */ | |
1624 | str2 = strstr (str, "||"); | |
1625 | if (str2) | |
1626 | { | |
1627 | extype = EXEC_PARALLEL; | |
1628 | flag_xp_state = 1; | |
1629 | } | |
1630 | else | |
1631 | { | |
1632 | str2 = strstr (str, "->"); | |
1633 | if (str2) | |
1634 | extype = EXEC_SEQ; | |
1635 | else | |
1636 | { | |
1637 | str2 = strstr (str, "<-"); | |
1638 | if (str2) | |
1639 | extype = EXEC_REVSEQ; | |
1640 | } | |
1641 | } | |
1642 | ||
1643 | /* STR2 points to the separator, if one. */ | |
1644 | if (str2) | |
1645 | { | |
1646 | *str2 = 0; | |
1647 | ||
1648 | /* If two instructions are present and we already have one saved, | |
1649 | then first write it out. */ | |
1650 | d30v_cleanup (FALSE); | |
1651 | ||
1652 | /* Assemble first instruction and save it. */ | |
1653 | prev_insn = do_assemble (str, &prev_opcode, 1, 0); | |
1654 | if (prev_insn == -1) | |
1655 | as_bad (_("Cannot assemble instruction")); | |
1656 | if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG) | |
1657 | as_bad (_("First opcode is long. Unable to mix instructions as specified.")); | |
1658 | fixups = fixups->next; | |
1659 | str = str2 + 2; | |
1660 | prev_seg = now_seg; | |
1661 | prev_subseg = now_subseg; | |
1662 | } | |
1663 | } | |
1664 | ||
1665 | insn = do_assemble (str, &opcode, | |
1666 | (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN), | |
1667 | extype == EXEC_PARALLEL); | |
1668 | if (insn == -1) | |
1669 | { | |
1670 | if (extype != EXEC_UNKNOWN) | |
1671 | etype = extype; | |
1672 | as_bad (_("Cannot assemble instruction")); | |
1673 | return; | |
1674 | } | |
1675 | ||
1676 | if (etype != EXEC_UNKNOWN) | |
1677 | { | |
1678 | extype = etype; | |
1679 | etype = EXEC_UNKNOWN; | |
1680 | } | |
1681 | ||
1682 | /* Word multiply instructions must not be followed by either a load or a | |
1683 | 16-bit multiply instruction in the next cycle. */ | |
1684 | if ( (extype != EXEC_REVSEQ) | |
1685 | && prev_mul32_p | |
1686 | && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1687 | { | |
1688 | /* However, load and multiply should able to be combined in a parallel | |
1689 | operation, so check for that first. */ | |
1690 | if (prev_insn != -1 | |
1691 | && (opcode.op->flags_used & FLAG_MEM) | |
1692 | && opcode.form->form < LONG | |
1693 | && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN)) | |
1694 | && parallel_ok (&prev_opcode, (long) prev_insn, | |
1695 | &opcode, (long) insn, extype) | |
1696 | && write_2_short (&prev_opcode, (long) prev_insn, | |
1697 | &opcode, (long) insn, extype, fixups) == 0) | |
1698 | { | |
1699 | /* No instructions saved. */ | |
1700 | prev_insn = -1; | |
1701 | return; | |
1702 | } | |
1703 | else | |
1704 | { | |
1705 | /* Can't parallelize, flush previous instruction and emit a | |
1706 | word of NOPS, unless the previous instruction is a NOP, | |
1707 | in which case just flush it, as this will generate a word | |
1708 | of NOPs for us. */ | |
1709 | ||
1710 | if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0)) | |
1711 | d30v_cleanup (FALSE); | |
1712 | else | |
1713 | { | |
1714 | char *f; | |
1715 | ||
1716 | if (prev_insn != -1) | |
1717 | d30v_cleanup (TRUE); | |
1718 | else | |
1719 | { | |
1720 | f = frag_more (8); | |
1721 | d30v_number_to_chars (f, NOP2, 8); | |
1722 | ||
1723 | if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY) | |
1724 | { | |
1725 | if (opcode.op->flags_used & FLAG_MEM) | |
1726 | as_warn (_("word of NOPs added between word multiply and load")); | |
1727 | else | |
1728 | as_warn (_("word of NOPs added between word multiply and 16-bit multiply")); | |
252b5132 | 1729 | } |
252b5132 RH |
1730 | } |
1731 | } | |
252b5132 | 1732 | |
ea1562b3 NC |
1733 | extype = EXEC_UNKNOWN; |
1734 | } | |
1735 | } | |
1736 | else if ( (extype == EXEC_REVSEQ) | |
1737 | && cur_mul32_p | |
1738 | && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) | |
1739 | { | |
1740 | /* Can't parallelize, flush current instruction and add a | |
1741 | sequential NOP. */ | |
1742 | write_1_short (&opcode, (long) insn, fixups->next->next, TRUE); | |
1743 | ||
1744 | /* Make the previous instruction the current one. */ | |
1745 | extype = EXEC_UNKNOWN; | |
1746 | insn = prev_insn; | |
1747 | now_seg = prev_seg; | |
1748 | now_subseg = prev_subseg; | |
1749 | prev_insn = -1; | |
1750 | cur_mul32_p = prev_mul32_p; | |
1751 | prev_mul32_p = 0; | |
1752 | memcpy (&opcode, &prev_opcode, sizeof (prev_opcode)); | |
1753 | } | |
1754 | ||
1755 | /* If this is a long instruction, write it and any previous short | |
1756 | instruction. */ | |
1757 | if (opcode.form->form >= LONG) | |
1758 | { | |
1759 | if (extype != EXEC_UNKNOWN) | |
1760 | as_bad (_("Instruction uses long version, so it cannot be mixed as specified")); | |
1761 | d30v_cleanup (FALSE); | |
1762 | write_long (&opcode, insn, fixups); | |
1763 | prev_insn = -1; | |
1764 | } | |
1765 | else if ((prev_insn != -1) | |
1766 | && (write_2_short | |
1767 | (&prev_opcode, (long) prev_insn, &opcode, | |
1768 | (long) insn, extype, fixups) == 0)) | |
1769 | { | |
1770 | /* No instructions saved. */ | |
1771 | prev_insn = -1; | |
1772 | } | |
1773 | else | |
1774 | { | |
1775 | if (extype != EXEC_UNKNOWN) | |
1776 | as_bad (_("Unable to mix instructions as specified")); | |
1777 | ||
1778 | /* Save off last instruction so it may be packed on next pass. */ | |
1779 | memcpy (&prev_opcode, &opcode, sizeof (prev_opcode)); | |
1780 | prev_insn = insn; | |
1781 | prev_seg = now_seg; | |
1782 | prev_subseg = now_subseg; | |
1783 | fixups = fixups->next; | |
1784 | prev_mul32_p = cur_mul32_p; | |
1785 | } | |
1786 | } | |
1787 | ||
1788 | /* If while processing a fixup, a reloc really needs to be created, | |
1789 | then it is done here. */ | |
1790 | ||
1791 | arelent * | |
1792 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) | |
1793 | { | |
1794 | arelent *reloc; | |
1795 | reloc = xmalloc (sizeof (arelent)); | |
1796 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); | |
1797 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
1798 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1799 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
1800 | if (reloc->howto == NULL) | |
1801 | { | |
1802 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1803 | _("reloc %d not supported by object file format"), | |
1804 | (int) fixp->fx_r_type); | |
1805 | return NULL; | |
1806 | } | |
1807 | ||
1808 | reloc->addend = 0; | |
1809 | return reloc; | |
1810 | } | |
1811 | ||
1812 | int | |
1813 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, | |
1814 | asection *seg ATTRIBUTE_UNUSED) | |
1815 | { | |
1816 | abort (); | |
1817 | return 0; | |
1818 | } | |
1819 | ||
1820 | long | |
1821 | md_pcrel_from_section (fixS *fixp, segT sec) | |
1822 | { | |
1823 | if (fixp->fx_addsy != (symbolS *) NULL | |
1824 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
1825 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
1826 | return 0; | |
1827 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
1828 | } | |
1829 | ||
1830 | /* Called after the assembler has finished parsing the input file or | |
1831 | after a label is defined. Because the D30V assembler sometimes | |
1832 | saves short instructions to see if it can package them with the | |
1833 | next instruction, there may be a short instruction that still needs | |
1834 | written. */ | |
1835 | ||
1836 | int | |
1837 | d30v_cleanup (int use_sequential) | |
1838 | { | |
1839 | segT seg; | |
1840 | subsegT subseg; | |
1841 | ||
1842 | if (prev_insn != -1) | |
1843 | { | |
1844 | seg = now_seg; | |
1845 | subseg = now_subseg; | |
1846 | subseg_set (prev_seg, prev_subseg); | |
1847 | write_1_short (&prev_opcode, (long) prev_insn, fixups->next, | |
1848 | use_sequential); | |
1849 | subseg_set (seg, subseg); | |
1850 | prev_insn = -1; | |
1851 | if (use_sequential) | |
1852 | prev_mul32_p = FALSE; | |
1853 | } | |
1854 | ||
1855 | return 1; | |
1856 | } | |
1857 | ||
1858 | /* This function is called at the start of every line. It checks to | |
1859 | see if the first character is a '.', which indicates the start of a | |
1860 | pseudo-op. If it is, then write out any unwritten instructions. */ | |
1861 | ||
1862 | void | |
1863 | d30v_start_line (void) | |
1864 | { | |
1865 | char *c = input_line_pointer; | |
1866 | ||
1867 | while (ISSPACE (*c)) | |
1868 | c++; | |
1869 | ||
1870 | if (*c == '.') | |
1871 | d30v_cleanup (FALSE); | |
1872 | } | |
1873 | ||
1874 | static void | |
1875 | check_size (long value, int bits, char *file, int line) | |
1876 | { | |
1877 | int tmp, max; | |
1878 | ||
1879 | if (value < 0) | |
1880 | tmp = ~value; | |
1881 | else | |
1882 | tmp = value; | |
1883 | ||
1884 | max = (1 << (bits - 1)) - 1; | |
2fd5405a | 1885 | |
ea1562b3 NC |
1886 | if (tmp > max) |
1887 | as_bad_where (file, line, _("value too large to fit in %d bits"), bits); | |
252b5132 RH |
1888 | } |
1889 | ||
ea1562b3 | 1890 | /* d30v_frob_label() is called when after a label is recognized. */ |
2fd5405a | 1891 | |
ea1562b3 NC |
1892 | void |
1893 | d30v_frob_label (symbolS *lab) | |
252b5132 | 1894 | { |
ea1562b3 NC |
1895 | /* Emit any pending instructions. */ |
1896 | d30v_cleanup (FALSE); | |
a161fe53 | 1897 | |
ea1562b3 NC |
1898 | /* Update the label's address with the current output pointer. */ |
1899 | symbol_set_frag (lab, frag_now); | |
1900 | S_SET_VALUE (lab, (valueT) frag_now_fix ()); | |
252b5132 | 1901 | |
ea1562b3 NC |
1902 | /* Record this label for future adjustment after we find out what |
1903 | kind of data it references, and the required alignment therewith. */ | |
1904 | d30v_last_label = lab; | |
2fd5405a | 1905 | } |
252b5132 | 1906 | |
ea1562b3 NC |
1907 | /* Hook into cons for capturing alignment changes. */ |
1908 | ||
1909 | void | |
1910 | d30v_cons_align (int size) | |
252b5132 | 1911 | { |
ea1562b3 NC |
1912 | int log_size; |
1913 | ||
1914 | log_size = 0; | |
1915 | while ((size >>= 1) != 0) | |
1916 | ++log_size; | |
1917 | ||
1918 | if (d30v_current_align < log_size) | |
1919 | d30v_align (log_size, (char *) NULL, NULL); | |
1920 | else if (d30v_current_align > log_size) | |
1921 | d30v_current_align = log_size; | |
1922 | d30v_last_label = NULL; | |
252b5132 RH |
1923 | } |
1924 | ||
94f592af | 1925 | void |
55cf6793 | 1926 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 1927 | { |
2fd5405a | 1928 | char *where; |
252b5132 | 1929 | unsigned long insn, insn2; |
a161fe53 | 1930 | long value = *valP; |
94f592af NC |
1931 | |
1932 | if (fixP->fx_addsy == (symbolS *) NULL) | |
1933 | fixP->fx_done = 1; | |
1934 | ||
a161fe53 AM |
1935 | /* We don't support subtracting a symbol. */ |
1936 | if (fixP->fx_subsy != (symbolS *) NULL) | |
1937 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
2fd5405a | 1938 | |
252b5132 RH |
1939 | /* Fetch the instruction, insert the fully resolved operand |
1940 | value, and stuff the instruction back again. */ | |
94f592af | 1941 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 1942 | insn = bfd_getb32 ((unsigned char *) where); |
2fd5405a | 1943 | |
94f592af | 1944 | switch (fixP->fx_r_type) |
252b5132 RH |
1945 | { |
1946 | case BFD_RELOC_8: /* Check for a bad .byte directive. */ | |
94f592af | 1947 | if (fixP->fx_addsy != NULL) |
252b5132 | 1948 | as_bad (_("line %d: unable to place address of symbol '%s' into a byte"), |
94f592af | 1949 | fixP->fx_line, S_GET_NAME (fixP->fx_addsy)); |
252b5132 | 1950 | else if (((unsigned)value) > 0xff) |
ebf19f1b | 1951 | as_bad (_("line %d: unable to place value %lx into a byte"), |
94f592af | 1952 | fixP->fx_line, value); |
252b5132 | 1953 | else |
2fd5405a | 1954 | *(unsigned char *) where = value; |
252b5132 | 1955 | break; |
2fd5405a | 1956 | |
252b5132 | 1957 | case BFD_RELOC_16: /* Check for a bad .short directive. */ |
94f592af | 1958 | if (fixP->fx_addsy != NULL) |
252b5132 | 1959 | as_bad (_("line %d: unable to place address of symbol '%s' into a short"), |
94f592af | 1960 | fixP->fx_line, S_GET_NAME (fixP->fx_addsy)); |
252b5132 | 1961 | else if (((unsigned)value) > 0xffff) |
ebf19f1b | 1962 | as_bad (_("line %d: unable to place value %lx into a short"), |
94f592af | 1963 | fixP->fx_line, value); |
252b5132 RH |
1964 | else |
1965 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); | |
1966 | break; | |
2fd5405a | 1967 | |
252b5132 | 1968 | case BFD_RELOC_64: /* Check for a bad .quad directive. */ |
94f592af | 1969 | if (fixP->fx_addsy != NULL) |
252b5132 | 1970 | as_bad (_("line %d: unable to place address of symbol '%s' into a quad"), |
94f592af | 1971 | fixP->fx_line, S_GET_NAME (fixP->fx_addsy)); |
252b5132 RH |
1972 | else |
1973 | { | |
1974 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
1975 | bfd_putb32 (0, ((unsigned char *) where) + 4); | |
1976 | } | |
1977 | break; | |
2fd5405a | 1978 | |
252b5132 | 1979 | case BFD_RELOC_D30V_6: |
94f592af | 1980 | check_size (value, 6, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
1981 | insn |= value & 0x3F; |
1982 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1983 | break; | |
1984 | ||
1985 | case BFD_RELOC_D30V_9_PCREL: | |
94f592af | 1986 | if (fixP->fx_where & 0x7) |
252b5132 | 1987 | { |
94f592af | 1988 | if (fixP->fx_done) |
252b5132 RH |
1989 | value += 4; |
1990 | else | |
94f592af | 1991 | fixP->fx_r_type = BFD_RELOC_D30V_9_PCREL_R; |
252b5132 | 1992 | } |
94f592af | 1993 | check_size (value, 9, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
1994 | insn |= ((value >> 3) & 0x3F) << 12; |
1995 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
1996 | break; | |
1997 | ||
1998 | case BFD_RELOC_D30V_15: | |
94f592af | 1999 | check_size (value, 15, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
2000 | insn |= (value >> 3) & 0xFFF; |
2001 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
2002 | break; | |
2003 | ||
2004 | case BFD_RELOC_D30V_15_PCREL: | |
94f592af | 2005 | if (fixP->fx_where & 0x7) |
252b5132 | 2006 | { |
94f592af | 2007 | if (fixP->fx_done) |
252b5132 RH |
2008 | value += 4; |
2009 | else | |
94f592af | 2010 | fixP->fx_r_type = BFD_RELOC_D30V_15_PCREL_R; |
252b5132 | 2011 | } |
94f592af | 2012 | check_size (value, 15, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
2013 | insn |= (value >> 3) & 0xFFF; |
2014 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
2015 | break; | |
2016 | ||
2017 | case BFD_RELOC_D30V_21: | |
94f592af | 2018 | check_size (value, 21, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
2019 | insn |= (value >> 3) & 0x3FFFF; |
2020 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
2021 | break; | |
2022 | ||
2023 | case BFD_RELOC_D30V_21_PCREL: | |
94f592af | 2024 | if (fixP->fx_where & 0x7) |
252b5132 | 2025 | { |
94f592af | 2026 | if (fixP->fx_done) |
252b5132 RH |
2027 | value += 4; |
2028 | else | |
94f592af | 2029 | fixP->fx_r_type = BFD_RELOC_D30V_21_PCREL_R; |
252b5132 | 2030 | } |
94f592af | 2031 | check_size (value, 21, fixP->fx_file, fixP->fx_line); |
252b5132 RH |
2032 | insn |= (value >> 3) & 0x3FFFF; |
2033 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); | |
2034 | break; | |
2035 | ||
2036 | case BFD_RELOC_D30V_32: | |
2037 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
2fd5405a NC |
2038 | insn |= (value >> 26) & 0x3F; /* Top 6 bits. */ |
2039 | insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */ | |
2040 | insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */ | |
252b5132 RH |
2041 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); |
2042 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
2043 | break; | |
2044 | ||
2045 | case BFD_RELOC_D30V_32_PCREL: | |
2046 | insn2 = bfd_getb32 ((unsigned char *) where + 4); | |
81d4177b KH |
2047 | insn |= (value >> 26) & 0x3F; /* Top 6 bits. */ |
2048 | insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */ | |
2049 | insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */ | |
252b5132 RH |
2050 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); |
2051 | bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); | |
2052 | break; | |
2053 | ||
2054 | case BFD_RELOC_32: | |
2055 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); | |
2056 | break; | |
2057 | ||
2058 | default: | |
2059 | as_bad (_("line %d: unknown relocation type: 0x%x"), | |
94f592af | 2060 | fixP->fx_line, fixP->fx_r_type); |
252b5132 | 2061 | } |
252b5132 RH |
2062 | } |
2063 | ||
252b5132 RH |
2064 | /* Handle the .align pseudo-op. This aligns to a power of two. We |
2065 | hook here to latch the current alignment. */ | |
2066 | ||
2067 | static void | |
ea1562b3 | 2068 | s_d30v_align (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
2069 | { |
2070 | int align; | |
2071 | char fill, *pfill = NULL; | |
2072 | long max_alignment = 15; | |
2073 | ||
2074 | align = get_absolute_expression (); | |
2075 | if (align > max_alignment) | |
2076 | { | |
2077 | align = max_alignment; | |
2078 | as_warn (_("Alignment too large: %d assumed"), align); | |
2079 | } | |
2080 | else if (align < 0) | |
2081 | { | |
2082 | as_warn (_("Alignment negative: 0 assumed")); | |
2083 | align = 0; | |
2084 | } | |
2085 | ||
2086 | if (*input_line_pointer == ',') | |
2087 | { | |
2088 | input_line_pointer++; | |
2089 | fill = get_absolute_expression (); | |
2090 | pfill = &fill; | |
2091 | } | |
2092 | ||
2093 | d30v_last_label = NULL; | |
2094 | d30v_align (align, pfill, NULL); | |
2095 | ||
2096 | demand_empty_rest_of_line (); | |
2097 | } | |
2098 | ||
2099 | /* Handle the .text pseudo-op. This is like the usual one, but it | |
2100 | clears the saved last label and resets known alignment. */ | |
2101 | ||
2102 | static void | |
ea1562b3 | 2103 | s_d30v_text (int i) |
252b5132 RH |
2104 | |
2105 | { | |
2106 | s_text (i); | |
2107 | d30v_last_label = NULL; | |
2108 | d30v_current_align = 0; | |
2109 | d30v_current_align_seg = now_seg; | |
2110 | } | |
2111 | ||
2112 | /* Handle the .data pseudo-op. This is like the usual one, but it | |
2113 | clears the saved last label and resets known alignment. */ | |
2114 | ||
2115 | static void | |
ea1562b3 | 2116 | s_d30v_data (int i) |
252b5132 RH |
2117 | { |
2118 | s_data (i); | |
2119 | d30v_last_label = NULL; | |
2120 | d30v_current_align = 0; | |
2121 | d30v_current_align_seg = now_seg; | |
2122 | } | |
2123 | ||
2124 | /* Handle the .section pseudo-op. This is like the usual one, but it | |
2125 | clears the saved last label and resets known alignment. */ | |
2126 | ||
2127 | static void | |
ea1562b3 | 2128 | s_d30v_section (int ignore) |
252b5132 RH |
2129 | { |
2130 | obj_elf_section (ignore); | |
2131 | d30v_last_label = NULL; | |
2132 | d30v_current_align = 0; | |
2133 | d30v_current_align_seg = now_seg; | |
2134 | } | |
ea1562b3 NC |
2135 | |
2136 | /* The target specific pseudo-ops which we support. */ | |
2137 | const pseudo_typeS md_pseudo_table[] = | |
2138 | { | |
2139 | { "word", cons, 4 }, | |
2140 | { "hword", cons, 2 }, | |
2141 | { "align", s_d30v_align, 0 }, | |
2142 | { "text", s_d30v_text, 0 }, | |
2143 | { "data", s_d30v_data, 0 }, | |
2144 | { "section", s_d30v_section, 0 }, | |
2145 | { "section.s", s_d30v_section, 0 }, | |
2146 | { "sect", s_d30v_section, 0 }, | |
2147 | { "sect.s", s_d30v_section, 0 }, | |
2148 | { NULL, NULL, 0 } | |
2149 | }; | |
2150 |