Commit | Line | Data |
---|---|---|
c2dcd04e | 1 | /* tc-h8300.c -- Assemble code for the Renesas H8/300 |
cc8a6dd0 | 2 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, |
2132e3a3 | 3 | 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
252b5132 | 21 | |
bc0d738a | 22 | /* Written By Steve Chamberlain <sac@cygnus.com>. */ |
252b5132 RH |
23 | |
24 | #include <stdio.h> | |
25 | #include "as.h" | |
26 | #include "subsegs.h" | |
27 | #include "bfd.h" | |
2c8714f2 | 28 | #include "dwarf2dbg.h" |
2c8714f2 | 29 | |
252b5132 RH |
30 | #define DEFINE_TABLE |
31 | #define h8_opcodes ops | |
32 | #include "opcode/h8300.h" | |
3882b010 | 33 | #include "safe-ctype.h" |
252b5132 | 34 | |
7e0de7bf JL |
35 | #ifdef OBJ_ELF |
36 | #include "elf/h8.h" | |
7e0de7bf JL |
37 | #endif |
38 | ||
63a0b638 | 39 | const char comment_chars[] = ";"; |
252b5132 | 40 | const char line_comment_chars[] = "#"; |
63a0b638 | 41 | const char line_separator_chars[] = ""; |
252b5132 | 42 | |
600e9c99 KH |
43 | static void sbranch (int); |
44 | static void h8300hmode (int); | |
45 | static void h8300smode (int); | |
46 | static void h8300hnmode (int); | |
47 | static void h8300snmode (int); | |
48 | static void h8300sxmode (int); | |
49 | static void h8300sxnmode (int); | |
b54a3392 | 50 | static void pint (int); |
252b5132 | 51 | |
66faad26 KH |
52 | int Hmode; |
53 | int Smode; | |
54 | int Nmode; | |
55 | int SXmode; | |
3048287a | 56 | |
d4e2de6b | 57 | #define PSIZE (Hmode && !Nmode ? L_32 : L_16) |
3048287a | 58 | |
600e9c99 | 59 | static int bsize = L_8; /* Default branch displacement. */ |
252b5132 | 60 | |
a720f7bc KD |
61 | struct h8_instruction |
62 | { | |
63 | int length; | |
64 | int noperands; | |
65 | int idx; | |
66 | int size; | |
67 | const struct h8_opcode *opcode; | |
68 | }; | |
69 | ||
600e9c99 | 70 | static struct h8_instruction *h8_instructions; |
a720f7bc | 71 | |
600e9c99 | 72 | static void |
b54a3392 | 73 | h8300hmode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
74 | { |
75 | Hmode = 1; | |
76 | Smode = 0; | |
83e20b45 JL |
77 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) |
78 | as_warn (_("could not set architecture and machine")); | |
252b5132 RH |
79 | } |
80 | ||
600e9c99 | 81 | static void |
b54a3392 | 82 | h8300smode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
83 | { |
84 | Smode = 1; | |
85 | Hmode = 1; | |
83e20b45 JL |
86 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) |
87 | as_warn (_("could not set architecture and machine")); | |
252b5132 | 88 | } |
70d6ecf3 | 89 | |
600e9c99 | 90 | static void |
b54a3392 | 91 | h8300hnmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
92 | { |
93 | Hmode = 1; | |
94 | Smode = 0; | |
95 | Nmode = 1; | |
8d9cd6b1 NC |
96 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) |
97 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
98 | } |
99 | ||
600e9c99 | 100 | static void |
b54a3392 | 101 | h8300snmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
102 | { |
103 | Smode = 1; | |
104 | Hmode = 1; | |
105 | Nmode = 1; | |
8d9cd6b1 NC |
106 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) |
107 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
108 | } |
109 | ||
600e9c99 | 110 | static void |
b54a3392 | 111 | h8300sxmode (int arg ATTRIBUTE_UNUSED) |
7ee7b84d MS |
112 | { |
113 | Smode = 1; | |
114 | Hmode = 1; | |
115 | SXmode = 1; | |
7ee7b84d MS |
116 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) |
117 | as_warn (_("could not set architecture and machine")); | |
7ee7b84d MS |
118 | } |
119 | ||
600e9c99 | 120 | static void |
b54a3392 | 121 | h8300sxnmode (int arg ATTRIBUTE_UNUSED) |
f4984206 RS |
122 | { |
123 | Smode = 1; | |
124 | Hmode = 1; | |
125 | SXmode = 1; | |
126 | Nmode = 1; | |
f4984206 RS |
127 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) |
128 | as_warn (_("could not set architecture and machine")); | |
f4984206 RS |
129 | } |
130 | ||
600e9c99 | 131 | static void |
b54a3392 | 132 | sbranch (int size) |
252b5132 RH |
133 | { |
134 | bsize = size; | |
135 | } | |
136 | ||
70d6ecf3 | 137 | static void |
b54a3392 | 138 | pint (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
139 | { |
140 | cons (Hmode ? 4 : 2); | |
141 | } | |
142 | ||
3048287a NC |
143 | /* This table describes all the machine specific pseudo-ops the assembler |
144 | has to support. The fields are: | |
145 | pseudo-op name without dot | |
146 | function to call to execute this pseudo-op | |
147 | Integer arg to pass to the function. */ | |
148 | ||
252b5132 RH |
149 | const pseudo_typeS md_pseudo_table[] = |
150 | { | |
7ee7b84d | 151 | {"h8300h", h8300hmode, 0}, |
8d9cd6b1 | 152 | {"h8300hn", h8300hnmode, 0}, |
7ee7b84d | 153 | {"h8300s", h8300smode, 0}, |
8d9cd6b1 | 154 | {"h8300sn", h8300snmode, 0}, |
7ee7b84d | 155 | {"h8300sx", h8300sxmode, 0}, |
f4984206 | 156 | {"h8300sxn", h8300sxnmode, 0}, |
252b5132 RH |
157 | {"sbranch", sbranch, L_8}, |
158 | {"lbranch", sbranch, L_16}, | |
159 | ||
160 | {"int", pint, 0}, | |
161 | {"data.b", cons, 1}, | |
162 | {"data.w", cons, 2}, | |
163 | {"data.l", cons, 4}, | |
164 | {"form", listing_psize, 0}, | |
165 | {"heading", listing_title, 0}, | |
7ee7b84d MS |
166 | {"import", s_ignore, 0}, |
167 | {"page", listing_eject, 0}, | |
252b5132 RH |
168 | {"program", s_ignore, 0}, |
169 | {0, 0, 0} | |
170 | }; | |
171 | ||
252b5132 RH |
172 | const char EXP_CHARS[] = "eE"; |
173 | ||
3048287a NC |
174 | /* Chars that mean this number is a floating point constant |
175 | As in 0f12.456 | |
176 | or 0d1.2345e12. */ | |
252b5132 RH |
177 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
178 | ||
3048287a | 179 | static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ |
252b5132 | 180 | |
70d6ecf3 AM |
181 | /* This function is called once, at assembler startup time. This |
182 | should set up all the tables, etc. that the MD part of the assembler | |
183 | needs. */ | |
3048287a | 184 | |
252b5132 | 185 | void |
b54a3392 | 186 | md_begin (void) |
252b5132 | 187 | { |
a720f7bc | 188 | unsigned int nopcodes; |
7ee7b84d | 189 | struct h8_opcode *p, *p1; |
a720f7bc | 190 | struct h8_instruction *pi; |
252b5132 RH |
191 | char prev_buffer[100]; |
192 | int idx = 0; | |
193 | ||
83e20b45 JL |
194 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300)) |
195 | as_warn (_("could not set architecture and machine")); | |
83e20b45 | 196 | |
252b5132 RH |
197 | opcode_hash_control = hash_new (); |
198 | prev_buffer[0] = 0; | |
199 | ||
a720f7bc KD |
200 | nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); |
201 | ||
202 | h8_instructions = (struct h8_instruction *) | |
203 | xmalloc (nopcodes * sizeof (struct h8_instruction)); | |
204 | ||
7ee7b84d MS |
205 | pi = h8_instructions; |
206 | p1 = h8_opcodes; | |
207 | /* We do a minimum amount of sorting on the opcode table; this is to | |
208 | make it easy to describe the mova instructions without unnecessary | |
209 | code duplication. | |
210 | Sorting only takes place inside blocks of instructions of the form | |
211 | X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ | |
212 | while (p1) | |
252b5132 | 213 | { |
7ee7b84d MS |
214 | struct h8_opcode *first_skipped = 0; |
215 | int len, cmplen = 0; | |
216 | char *src = p1->name; | |
217 | char *dst, *buffer; | |
252b5132 | 218 | |
7ee7b84d MS |
219 | if (p1->name == 0) |
220 | break; | |
221 | /* Strip off any . part when inserting the opcode and only enter | |
222 | unique codes into the hash table. */ | |
223 | dst = buffer = malloc (strlen (src) + 1); | |
252b5132 RH |
224 | while (*src) |
225 | { | |
226 | if (*src == '.') | |
227 | { | |
228 | src++; | |
252b5132 RH |
229 | break; |
230 | } | |
7ee7b84d MS |
231 | if (*src == '/') |
232 | cmplen = src - p1->name + 1; | |
252b5132 RH |
233 | *dst++ = *src++; |
234 | } | |
7ee7b84d MS |
235 | *dst = 0; |
236 | len = dst - buffer; | |
237 | if (cmplen == 0) | |
238 | cmplen = len; | |
239 | hash_insert (opcode_hash_control, buffer, (char *) pi); | |
240 | strcpy (prev_buffer, buffer); | |
241 | idx++; | |
242 | ||
243 | for (p = p1; p->name; p++) | |
252b5132 | 244 | { |
7ee7b84d MS |
245 | /* A negative TIME is used to indicate that we've added this opcode |
246 | already. */ | |
247 | if (p->time == -1) | |
248 | continue; | |
249 | if (strncmp (p->name, buffer, cmplen) != 0 | |
250 | || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' | |
251 | && p->name[cmplen - 1] != '/')) | |
252 | { | |
253 | if (first_skipped == 0) | |
254 | first_skipped = p; | |
255 | break; | |
256 | } | |
257 | if (strncmp (p->name, buffer, len) != 0) | |
258 | { | |
259 | if (first_skipped == 0) | |
260 | first_skipped = p; | |
261 | continue; | |
262 | } | |
263 | ||
264 | p->time = -1; | |
265 | pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; | |
266 | pi->idx = idx; | |
252b5132 | 267 | |
7ee7b84d MS |
268 | /* Find the number of operands. */ |
269 | pi->noperands = 0; | |
270 | while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) | |
271 | pi->noperands++; | |
70d6ecf3 | 272 | |
7ee7b84d MS |
273 | /* Find the length of the opcode in bytes. */ |
274 | pi->length = 0; | |
275 | while (p->data.nib[pi->length * 2] != (op_type) E) | |
276 | pi->length++; | |
a720f7bc | 277 | |
7ee7b84d MS |
278 | pi->opcode = p; |
279 | pi++; | |
280 | } | |
281 | p1 = first_skipped; | |
252b5132 RH |
282 | } |
283 | ||
a720f7bc KD |
284 | /* Add entry for the NULL vector terminator. */ |
285 | pi->length = 0; | |
286 | pi->noperands = 0; | |
287 | pi->idx = 0; | |
288 | pi->size = 0; | |
7ee7b84d | 289 | pi->opcode = 0; |
a720f7bc | 290 | |
252b5132 RH |
291 | linkrelax = 1; |
292 | } | |
293 | ||
252b5132 RH |
294 | struct h8_op |
295 | { | |
296 | op_type mode; | |
297 | unsigned reg; | |
298 | expressionS exp; | |
299 | }; | |
300 | ||
b54a3392 KH |
301 | static void clever_message (const struct h8_instruction *, struct h8_op *); |
302 | static void fix_operand_size (struct h8_op *, int); | |
303 | static void build_bytes (const struct h8_instruction *, struct h8_op *); | |
304 | static void do_a_fix_imm (int, int, struct h8_op *, int); | |
305 | static void check_operand (struct h8_op *, unsigned int, char *); | |
306 | static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; | |
307 | static char *get_operands (unsigned, char *, struct h8_op *); | |
308 | static void get_operand (char **, struct h8_op *, int); | |
309 | static int parse_reg (char *, op_type *, unsigned *, int); | |
310 | static char *skip_colonthing (char *, int *); | |
311 | static char *parse_exp (char *, struct h8_op *); | |
312 | ||
313 | static int constant_fits_width_p (struct h8_op *, unsigned int); | |
314 | static int constant_fits_size_p (struct h8_op *, int, int); | |
7ee7b84d | 315 | |
252b5132 RH |
316 | /* |
317 | parse operands | |
318 | WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp | |
319 | r0l,r0h,..r7l,r7h | |
320 | @WREG | |
321 | @WREG+ | |
322 | @-WREG | |
323 | #const | |
324 | ccr | |
325 | */ | |
326 | ||
bc0d738a NC |
327 | /* Try to parse a reg name. Return the number of chars consumed. */ |
328 | ||
40f09f82 | 329 | static int |
b54a3392 | 330 | parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) |
252b5132 RH |
331 | { |
332 | char *end; | |
333 | int len; | |
334 | ||
70d6ecf3 | 335 | /* Cribbed from get_symbol_end. */ |
252b5132 RH |
336 | if (!is_name_beginner (*src) || *src == '\001') |
337 | return 0; | |
70d6ecf3 | 338 | end = src + 1; |
7ee7b84d | 339 | while ((is_part_of_name (*end) && *end != '.') || *end == '\001') |
252b5132 RH |
340 | end++; |
341 | len = end - src; | |
342 | ||
7ee7b84d | 343 | if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
344 | { |
345 | *mode = PSIZE | REG | direction; | |
346 | *reg = 7; | |
347 | return len; | |
348 | } | |
7ee7b84d MS |
349 | if (len == 3 && |
350 | TOLOWER (src[0]) == 'c' && | |
351 | TOLOWER (src[1]) == 'c' && | |
352 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
353 | { |
354 | *mode = CCR; | |
355 | *reg = 0; | |
356 | return len; | |
357 | } | |
7ee7b84d MS |
358 | if (len == 3 && |
359 | TOLOWER (src[0]) == 'e' && | |
360 | TOLOWER (src[1]) == 'x' && | |
361 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
362 | { |
363 | *mode = EXR; | |
7ee7b84d MS |
364 | *reg = 1; |
365 | return len; | |
366 | } | |
367 | if (len == 3 && | |
368 | TOLOWER (src[0]) == 'v' && | |
369 | TOLOWER (src[1]) == 'b' && | |
370 | TOLOWER (src[2]) == 'r') | |
371 | { | |
372 | *mode = VBR; | |
373 | *reg = 6; | |
374 | return len; | |
375 | } | |
376 | if (len == 3 && | |
377 | TOLOWER (src[0]) == 's' && | |
378 | TOLOWER (src[1]) == 'b' && | |
379 | TOLOWER (src[2]) == 'r') | |
380 | { | |
381 | *mode = SBR; | |
382 | *reg = 7; | |
252b5132 RH |
383 | return len; |
384 | } | |
7ee7b84d | 385 | if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
386 | { |
387 | *mode = PSIZE | REG | direction; | |
388 | *reg = 6; | |
389 | return len; | |
390 | } | |
7ee7b84d MS |
391 | if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
392 | src[2] >= '0' && src[2] <= '7') | |
252b5132 RH |
393 | { |
394 | *mode = L_32 | REG | direction; | |
395 | *reg = src[2] - '0'; | |
396 | if (!Hmode) | |
397 | as_warn (_("Reg not valid for H8/300")); | |
398 | return len; | |
399 | } | |
7ee7b84d | 400 | if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') |
252b5132 RH |
401 | { |
402 | *mode = L_16 | REG | direction; | |
403 | *reg = src[1] - '0' + 8; | |
404 | if (!Hmode) | |
405 | as_warn (_("Reg not valid for H8/300")); | |
406 | return len; | |
407 | } | |
408 | ||
7ee7b84d | 409 | if (TOLOWER (src[0]) == 'r') |
252b5132 RH |
410 | { |
411 | if (src[1] >= '0' && src[1] <= '7') | |
412 | { | |
7ee7b84d | 413 | if (len == 3 && TOLOWER (src[2]) == 'l') |
252b5132 RH |
414 | { |
415 | *mode = L_8 | REG | direction; | |
416 | *reg = (src[1] - '0') + 8; | |
417 | return len; | |
418 | } | |
7ee7b84d | 419 | if (len == 3 && TOLOWER (src[2]) == 'h') |
252b5132 RH |
420 | { |
421 | *mode = L_8 | REG | direction; | |
422 | *reg = (src[1] - '0'); | |
423 | return len; | |
424 | } | |
425 | if (len == 2) | |
426 | { | |
427 | *mode = L_16 | REG | direction; | |
428 | *reg = (src[1] - '0'); | |
429 | return len; | |
430 | } | |
431 | } | |
432 | } | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
1b680e4f RS |
437 | |
438 | /* Parse an immediate or address-related constant and store it in OP. | |
439 | If the user also specifies the operand's size, store that size | |
440 | in OP->MODE, otherwise leave it for later code to decide. */ | |
441 | ||
40f09f82 | 442 | static char * |
b54a3392 | 443 | parse_exp (char *src, struct h8_op *op) |
252b5132 | 444 | { |
1b680e4f | 445 | char *save; |
252b5132 | 446 | |
1b680e4f RS |
447 | save = input_line_pointer; |
448 | input_line_pointer = src; | |
449 | expression (&op->exp); | |
450 | if (op->exp.X_op == O_absent) | |
252b5132 | 451 | as_bad (_("missing operand")); |
1b680e4f | 452 | src = input_line_pointer; |
252b5132 | 453 | input_line_pointer = save; |
1b680e4f RS |
454 | |
455 | return skip_colonthing (src, &op->mode); | |
252b5132 RH |
456 | } |
457 | ||
1b680e4f RS |
458 | |
459 | /* If SRC starts with an explicit operand size, skip it and store the size | |
460 | in *MODE. Leave *MODE unchanged otherwise. */ | |
461 | ||
252b5132 | 462 | static char * |
b54a3392 | 463 | skip_colonthing (char *src, int *mode) |
252b5132 | 464 | { |
1b680e4f | 465 | if (*src == ':') |
252b5132 | 466 | { |
1b680e4f | 467 | src++; |
252b5132 | 468 | *mode &= ~SIZE; |
1b680e4f | 469 | if (src[0] == '8' && !ISDIGIT (src[1])) |
7ee7b84d | 470 | *mode |= L_8; |
1b680e4f | 471 | else if (src[0] == '2' && !ISDIGIT (src[1])) |
7ee7b84d | 472 | *mode |= L_2; |
1b680e4f | 473 | else if (src[0] == '3' && !ISDIGIT (src[1])) |
7ee7b84d | 474 | *mode |= L_3; |
1b680e4f | 475 | else if (src[0] == '4' && !ISDIGIT (src[1])) |
7ee7b84d | 476 | *mode |= L_4; |
1b680e4f | 477 | else if (src[0] == '5' && !ISDIGIT (src[1])) |
7ee7b84d | 478 | *mode |= L_5; |
1b680e4f | 479 | else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) |
7ee7b84d | 480 | *mode |= L_24; |
1b680e4f | 481 | else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) |
7ee7b84d | 482 | *mode |= L_32; |
1b680e4f | 483 | else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) |
7ee7b84d | 484 | *mode |= L_16; |
252b5132 | 485 | else |
7ee7b84d MS |
486 | as_bad (_("invalid operand size requested")); |
487 | ||
1b680e4f RS |
488 | while (ISDIGIT (*src)) |
489 | src++; | |
252b5132 | 490 | } |
1b680e4f | 491 | return src; |
252b5132 RH |
492 | } |
493 | ||
494 | /* The many forms of operand: | |
495 | ||
496 | Rn Register direct | |
497 | @Rn Register indirect | |
498 | @(exp[:16], Rn) Register indirect with displacement | |
499 | @Rn+ | |
500 | @-Rn | |
70d6ecf3 AM |
501 | @aa:8 absolute 8 bit |
502 | @aa:16 absolute 16 bit | |
252b5132 RH |
503 | @aa absolute 16 bit |
504 | ||
505 | #xx[:size] immediate data | |
70d6ecf3 | 506 | @(exp:[8], pc) pc rel |
3048287a | 507 | @@aa[:8] memory indirect. */ |
252b5132 | 508 | |
7ee7b84d | 509 | static int |
b54a3392 | 510 | constant_fits_width_p (struct h8_op *operand, unsigned int width) |
7ee7b84d MS |
511 | { |
512 | return ((operand->exp.X_add_number & ~width) == 0 | |
513 | || (operand->exp.X_add_number | width) == (unsigned)(~0)); | |
514 | } | |
515 | ||
516 | static int | |
b54a3392 | 517 | constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) |
7ee7b84d MS |
518 | { |
519 | offsetT num = operand->exp.X_add_number; | |
520 | if (no_symbols | |
521 | && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) | |
522 | return 0; | |
523 | switch (size) | |
524 | { | |
525 | case L_2: | |
526 | return (num & ~3) == 0; | |
527 | case L_3: | |
528 | return (num & ~7) == 0; | |
529 | case L_3NZ: | |
530 | return num >= 1 && num < 8; | |
531 | case L_4: | |
532 | return (num & ~15) == 0; | |
533 | case L_5: | |
534 | return num >= 1 && num < 32; | |
535 | case L_8: | |
536 | return (num & ~0xFF) == 0 || ((unsigned)num | 0x7F) == ~0u; | |
537 | case L_8U: | |
538 | return (num & ~0xFF) == 0; | |
539 | case L_16: | |
540 | return (num & ~0xFFFF) == 0 || ((unsigned)num | 0x7FFF) == ~0u; | |
541 | case L_16U: | |
542 | return (num & ~0xFFFF) == 0; | |
543 | case L_32: | |
544 | return 1; | |
545 | default: | |
546 | abort (); | |
547 | } | |
548 | } | |
549 | ||
252b5132 | 550 | static void |
b54a3392 | 551 | get_operand (char **ptr, struct h8_op *op, int direction) |
252b5132 RH |
552 | { |
553 | char *src = *ptr; | |
554 | op_type mode; | |
555 | unsigned int num; | |
556 | unsigned int len; | |
557 | ||
7ee7b84d | 558 | op->mode = 0; |
252b5132 | 559 | |
3048287a NC |
560 | /* Check for '(' and ')' for instructions ldm and stm. */ |
561 | if (src[0] == '(' && src[8] == ')') | |
562 | ++ src; | |
563 | ||
252b5132 RH |
564 | /* Gross. Gross. ldm and stm have a format not easily handled |
565 | by get_operand. We deal with it explicitly here. */ | |
7ee7b84d MS |
566 | if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
567 | ISDIGIT (src[2]) && src[3] == '-' && | |
568 | TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) | |
252b5132 RH |
569 | { |
570 | int low, high; | |
571 | ||
572 | low = src[2] - '0'; | |
573 | high = src[6] - '0'; | |
574 | ||
4892e510 NC |
575 | /* Check register pair's validity as per tech note TN-H8*-193A/E |
576 | from Renesas for H8S and H8SX hardware manual. */ | |
577 | if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) | |
578 | && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) | |
579 | && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) | |
580 | && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) | |
581 | && !(low == 4 && (high == 5 || high == 6)) | |
b4f16abb | 582 | && !(low == 4 && high == 7 && SXmode) |
4892e510 NC |
583 | && !(low == 5 && (high == 6 || high == 7) && SXmode) |
584 | && !(low == 6 && high == 7 && SXmode)) | |
252b5132 RH |
585 | as_bad (_("Invalid register list for ldm/stm\n")); |
586 | ||
252b5132 RH |
587 | /* Even sicker. We encode two registers into op->reg. One |
588 | for the low register to save, the other for the high | |
589 | register to save; we also set the high bit in op->reg | |
590 | so we know this is "very special". */ | |
591 | op->reg = 0x80000000 | (high << 8) | low; | |
592 | op->mode = REG; | |
3048287a NC |
593 | if (src[7] == ')') |
594 | *ptr = src + 8; | |
595 | else | |
596 | *ptr = src + 7; | |
252b5132 RH |
597 | return; |
598 | } | |
599 | ||
600 | len = parse_reg (src, &op->mode, &op->reg, direction); | |
601 | if (len) | |
602 | { | |
7ee7b84d MS |
603 | src += len; |
604 | if (*src == '.') | |
605 | { | |
606 | int size = op->mode & SIZE; | |
607 | switch (src[1]) | |
608 | { | |
609 | case 'l': case 'L': | |
610 | if (size != L_32) | |
611 | as_warn (_("mismatch between register and suffix")); | |
612 | op->mode = (op->mode & ~MODE) | LOWREG; | |
613 | break; | |
614 | case 'w': case 'W': | |
615 | if (size != L_32 && size != L_16) | |
616 | as_warn (_("mismatch between register and suffix")); | |
617 | op->mode = (op->mode & ~MODE) | LOWREG; | |
618 | op->mode = (op->mode & ~SIZE) | L_16; | |
619 | break; | |
620 | case 'b': case 'B': | |
621 | op->mode = (op->mode & ~MODE) | LOWREG; | |
622 | if (size != L_32 && size != L_8) | |
623 | as_warn (_("mismatch between register and suffix")); | |
624 | op->mode = (op->mode & ~MODE) | LOWREG; | |
625 | op->mode = (op->mode & ~SIZE) | L_8; | |
626 | break; | |
627 | default: | |
628 | as_warn ("invalid suffix after register."); | |
629 | break; | |
630 | } | |
631 | src += 2; | |
632 | } | |
633 | *ptr = src; | |
252b5132 RH |
634 | return; |
635 | } | |
636 | ||
637 | if (*src == '@') | |
638 | { | |
639 | src++; | |
640 | if (*src == '@') | |
641 | { | |
1b680e4f | 642 | *ptr = parse_exp (src + 1, op); |
7ee7b84d MS |
643 | if (op->exp.X_add_number >= 0x100) |
644 | { | |
d4e2de6b | 645 | int divisor = 1; |
7ee7b84d MS |
646 | |
647 | op->mode = VECIND; | |
648 | /* FIXME : 2? or 4? */ | |
649 | if (op->exp.X_add_number >= 0x400) | |
650 | as_bad (_("address too high for vector table jmp/jsr")); | |
651 | else if (op->exp.X_add_number >= 0x200) | |
652 | divisor = 4; | |
653 | else | |
654 | divisor = 2; | |
655 | ||
656 | op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; | |
657 | } | |
658 | else | |
659 | op->mode = MEMIND; | |
252b5132 | 660 | return; |
252b5132 RH |
661 | } |
662 | ||
7ee7b84d | 663 | if (*src == '-' || *src == '+') |
252b5132 | 664 | { |
1b680e4f | 665 | len = parse_reg (src + 1, &mode, &num, direction); |
252b5132 RH |
666 | if (len == 0) |
667 | { | |
70d6ecf3 | 668 | /* Oops, not a reg after all, must be ordinary exp. */ |
1b680e4f RS |
669 | op->mode = ABS | direction; |
670 | *ptr = parse_exp (src, op); | |
252b5132 | 671 | return; |
252b5132 RH |
672 | } |
673 | ||
d4e2de6b NC |
674 | if (((mode & SIZE) != PSIZE) |
675 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
676 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 677 | as_bad (_("Wrong size pointer register for architecture.")); |
1b680e4f RS |
678 | |
679 | op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; | |
252b5132 | 680 | op->reg = num; |
1b680e4f | 681 | *ptr = src + 1 + len; |
252b5132 RH |
682 | return; |
683 | } | |
684 | if (*src == '(') | |
685 | { | |
252b5132 RH |
686 | src++; |
687 | ||
7ee7b84d MS |
688 | /* See if this is @(ERn.x, PC). */ |
689 | len = parse_reg (src, &mode, &op->reg, direction); | |
690 | if (len != 0 && (mode & MODE) == REG && src[len] == '.') | |
691 | { | |
692 | switch (TOLOWER (src[len + 1])) | |
693 | { | |
694 | case 'b': | |
695 | mode = PCIDXB | direction; | |
696 | break; | |
697 | case 'w': | |
698 | mode = PCIDXW | direction; | |
699 | break; | |
700 | case 'l': | |
701 | mode = PCIDXL | direction; | |
702 | break; | |
703 | default: | |
704 | mode = 0; | |
705 | break; | |
706 | } | |
707 | if (mode | |
708 | && src[len + 2] == ',' | |
709 | && TOLOWER (src[len + 3]) != 'p' | |
710 | && TOLOWER (src[len + 4]) != 'c' | |
711 | && src[len + 5] != ')') | |
712 | { | |
713 | *ptr = src + len + 6; | |
714 | op->mode |= mode; | |
715 | return; | |
716 | } | |
717 | /* Fall through into disp case - the grammar is somewhat | |
718 | ambiguous, so we should try whether it's a DISP operand | |
719 | after all ("ER3.L" might be a poorly named label...). */ | |
720 | } | |
721 | ||
722 | /* Disp. */ | |
723 | ||
70d6ecf3 | 724 | /* Start off assuming a 16 bit offset. */ |
252b5132 | 725 | |
1b680e4f | 726 | src = parse_exp (src, op); |
252b5132 RH |
727 | if (*src == ')') |
728 | { | |
252b5132 | 729 | op->mode |= ABS | direction; |
1b680e4f | 730 | *ptr = src + 1; |
252b5132 RH |
731 | return; |
732 | } | |
733 | ||
734 | if (*src != ',') | |
735 | { | |
736 | as_bad (_("expected @(exp, reg16)")); | |
737 | return; | |
252b5132 RH |
738 | } |
739 | src++; | |
740 | ||
741 | len = parse_reg (src, &mode, &op->reg, direction); | |
7ee7b84d | 742 | if (len == 0 || (mode & MODE) != REG) |
252b5132 RH |
743 | { |
744 | as_bad (_("expected @(exp, reg16)")); | |
745 | return; | |
746 | } | |
252b5132 | 747 | src += len; |
7ee7b84d MS |
748 | if (src[0] == '.') |
749 | { | |
750 | switch (TOLOWER (src[1])) | |
751 | { | |
752 | case 'b': | |
753 | op->mode |= INDEXB | direction; | |
754 | break; | |
755 | case 'w': | |
756 | op->mode |= INDEXW | direction; | |
757 | break; | |
758 | case 'l': | |
759 | op->mode |= INDEXL | direction; | |
760 | break; | |
761 | default: | |
762 | as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); | |
763 | } | |
764 | src += 2; | |
765 | op->reg &= 7; | |
766 | } | |
767 | else | |
768 | op->mode |= DISP | direction; | |
1b680e4f | 769 | src = skip_colonthing (src, &op->mode); |
252b5132 RH |
770 | |
771 | if (*src != ')' && '(') | |
772 | { | |
773 | as_bad (_("expected @(exp, reg16)")); | |
774 | return; | |
775 | } | |
776 | *ptr = src + 1; | |
252b5132 RH |
777 | return; |
778 | } | |
779 | len = parse_reg (src, &mode, &num, direction); | |
780 | ||
781 | if (len) | |
782 | { | |
783 | src += len; | |
7ee7b84d | 784 | if (*src == '+' || *src == '-') |
252b5132 | 785 | { |
d4e2de6b NC |
786 | if (((mode & SIZE) != PSIZE) |
787 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
788 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 789 | as_bad (_("Wrong size pointer register for architecture.")); |
7ee7b84d | 790 | op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; |
252b5132 | 791 | op->reg = num; |
7ee7b84d | 792 | src++; |
252b5132 RH |
793 | *ptr = src; |
794 | return; | |
795 | } | |
d4e2de6b NC |
796 | if (((mode & SIZE) != PSIZE) |
797 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
798 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 RH |
799 | as_bad (_("Wrong size pointer register for architecture.")); |
800 | ||
801 | op->mode = direction | IND | PSIZE; | |
802 | op->reg = num; | |
803 | *ptr = src; | |
804 | ||
805 | return; | |
806 | } | |
807 | else | |
808 | { | |
809 | /* must be a symbol */ | |
810 | ||
811 | op->mode = ABS | direction; | |
1b680e4f | 812 | *ptr = parse_exp (src, op); |
252b5132 RH |
813 | return; |
814 | } | |
815 | } | |
816 | ||
252b5132 RH |
817 | if (*src == '#') |
818 | { | |
252b5132 | 819 | op->mode = IMM; |
1b680e4f | 820 | *ptr = parse_exp (src + 1, op); |
252b5132 RH |
821 | return; |
822 | } | |
7ee7b84d MS |
823 | else if (strncmp (src, "mach", 4) == 0 || |
824 | strncmp (src, "macl", 4) == 0 || | |
825 | strncmp (src, "MACH", 4) == 0 || | |
826 | strncmp (src, "MACL", 4) == 0) | |
252b5132 | 827 | { |
7ee7b84d | 828 | op->reg = TOLOWER (src[3]) == 'l'; |
252b5132 RH |
829 | op->mode = MACREG; |
830 | *ptr = src + 4; | |
831 | return; | |
832 | } | |
833 | else | |
834 | { | |
1b680e4f RS |
835 | op->mode = PCREL; |
836 | *ptr = parse_exp (src, op); | |
252b5132 RH |
837 | } |
838 | } | |
839 | ||
70d6ecf3 | 840 | static char * |
b54a3392 | 841 | get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) |
252b5132 RH |
842 | { |
843 | char *ptr = op_end; | |
844 | ||
845 | switch (noperands) | |
846 | { | |
847 | case 0: | |
252b5132 RH |
848 | break; |
849 | ||
850 | case 1: | |
851 | ptr++; | |
7ee7b84d | 852 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
853 | if (*ptr == ',') |
854 | { | |
855 | ptr++; | |
7ee7b84d | 856 | get_operand (&ptr, operand + 1, DST); |
252b5132 | 857 | } |
252b5132 | 858 | break; |
70d6ecf3 | 859 | |
252b5132 RH |
860 | case 2: |
861 | ptr++; | |
7ee7b84d | 862 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
863 | if (*ptr == ',') |
864 | ptr++; | |
7ee7b84d MS |
865 | get_operand (&ptr, operand + 1, DST); |
866 | break; | |
867 | ||
868 | case 3: | |
869 | ptr++; | |
870 | get_operand (&ptr, operand + 0, SRC); | |
871 | if (*ptr == ',') | |
872 | ptr++; | |
873 | get_operand (&ptr, operand + 1, DST); | |
874 | if (*ptr == ',') | |
875 | ptr++; | |
876 | get_operand (&ptr, operand + 2, OP3); | |
252b5132 RH |
877 | break; |
878 | ||
879 | default: | |
880 | abort (); | |
881 | } | |
882 | ||
252b5132 RH |
883 | return ptr; |
884 | } | |
885 | ||
7ee7b84d MS |
886 | /* MOVA has special requirements. Rather than adding twice the amount of |
887 | addressing modes, we simply special case it a bit. */ | |
888 | static void | |
889 | get_mova_operands (char *op_end, struct h8_op *operand) | |
890 | { | |
891 | char *ptr = op_end; | |
892 | ||
893 | if (ptr[1] != '@' || ptr[2] != '(') | |
894 | goto error; | |
895 | ptr += 3; | |
896 | operand[0].mode = 0; | |
1b680e4f | 897 | ptr = parse_exp (ptr, &operand[0]); |
7ee7b84d MS |
898 | |
899 | if (*ptr !=',') | |
900 | goto error; | |
901 | ptr++; | |
902 | get_operand (&ptr, operand + 1, DST); | |
903 | ||
904 | if (*ptr =='.') | |
905 | { | |
906 | ptr++; | |
907 | switch (*ptr++) | |
908 | { | |
909 | case 'b': case 'B': | |
910 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
911 | break; | |
912 | case 'w': case 'W': | |
913 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
914 | break; | |
915 | case 'l': case 'L': | |
916 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
917 | break; | |
918 | default: | |
919 | goto error; | |
920 | } | |
921 | } | |
922 | else if ((operand[1].mode & MODE) == LOWREG) | |
923 | { | |
924 | switch (operand[1].mode & SIZE) | |
925 | { | |
926 | case L_8: | |
927 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
928 | break; | |
929 | case L_16: | |
930 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
931 | break; | |
932 | case L_32: | |
933 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
934 | break; | |
935 | default: | |
936 | goto error; | |
937 | } | |
938 | } | |
939 | else | |
940 | goto error; | |
941 | ||
942 | if (*ptr++ != ')' || *ptr++ != ',') | |
943 | goto error; | |
944 | get_operand (&ptr, operand + 2, OP3); | |
945 | /* See if we can use the short form of MOVA. */ | |
946 | if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) | |
947 | && (operand[2].mode & MODE) == REG | |
948 | && (operand[1].reg & 7) == (operand[2].reg & 7)) | |
949 | { | |
950 | operand[1].mode = operand[2].mode = 0; | |
951 | operand[0].reg = operand[2].reg & 7; | |
952 | } | |
953 | return; | |
954 | ||
955 | error: | |
956 | as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); | |
7ee7b84d MS |
957 | } |
958 | ||
959 | static void | |
960 | get_rtsl_operands (char *ptr, struct h8_op *operand) | |
961 | { | |
2132e3a3 AM |
962 | int mode, len, type = 0; |
963 | unsigned int num, num2; | |
7ee7b84d MS |
964 | |
965 | ptr++; | |
966 | if (*ptr == '(') | |
967 | { | |
968 | ptr++; | |
969 | type = 1; | |
970 | } | |
971 | len = parse_reg (ptr, &mode, &num, SRC); | |
972 | if (len == 0 || (mode & MODE) != REG) | |
973 | { | |
974 | as_bad (_("expected register")); | |
975 | return; | |
976 | } | |
0613284f RS |
977 | ptr += len; |
978 | if (*ptr == '-') | |
7ee7b84d | 979 | { |
0613284f | 980 | len = parse_reg (++ptr, &mode, &num2, SRC); |
7ee7b84d MS |
981 | if (len == 0 || (mode & MODE) != REG) |
982 | { | |
983 | as_bad (_("expected register")); | |
984 | return; | |
985 | } | |
986 | ptr += len; | |
7ee7b84d MS |
987 | /* CONST_xxx are used as placeholders in the opcode table. */ |
988 | num = num2 - num; | |
2132e3a3 | 989 | if (num > 3) |
7ee7b84d MS |
990 | { |
991 | as_bad (_("invalid register list")); | |
992 | return; | |
993 | } | |
994 | } | |
995 | else | |
996 | num2 = num, num = 0; | |
0613284f RS |
997 | if (type == 1 && *ptr++ != ')') |
998 | { | |
999 | as_bad (_("expected closing paren")); | |
1000 | return; | |
1001 | } | |
7ee7b84d MS |
1002 | operand[0].mode = RS32; |
1003 | operand[1].mode = RD32; | |
1004 | operand[0].reg = num; | |
1005 | operand[1].reg = num2; | |
1006 | } | |
1007 | ||
252b5132 RH |
1008 | /* Passed a pointer to a list of opcodes which use different |
1009 | addressing modes, return the opcode which matches the opcodes | |
70d6ecf3 | 1010 | provided. */ |
3048287a | 1011 | |
a720f7bc | 1012 | static const struct h8_instruction * |
b54a3392 KH |
1013 | get_specific (const struct h8_instruction *instruction, |
1014 | struct h8_op *operands, int size) | |
252b5132 | 1015 | { |
a720f7bc | 1016 | const struct h8_instruction *this_try = instruction; |
7ee7b84d | 1017 | const struct h8_instruction *found_other = 0, *found_mismatched = 0; |
252b5132 | 1018 | int found = 0; |
a720f7bc | 1019 | int this_index = instruction->idx; |
7ee7b84d | 1020 | int noperands = 0; |
252b5132 RH |
1021 | |
1022 | /* There's only one ldm/stm and it's easier to just | |
1023 | get out quick for them. */ | |
7ee7b84d MS |
1024 | if (OP_KIND (instruction->opcode->how) == O_LDM |
1025 | || OP_KIND (instruction->opcode->how) == O_STM) | |
252b5132 RH |
1026 | return this_try; |
1027 | ||
7ee7b84d MS |
1028 | while (noperands < 3 && operands[noperands].mode != 0) |
1029 | noperands++; | |
1030 | ||
a720f7bc | 1031 | while (this_index == instruction->idx && !found) |
252b5132 | 1032 | { |
7ee7b84d | 1033 | int this_size; |
252b5132 | 1034 | |
7ee7b84d | 1035 | found = 1; |
a720f7bc | 1036 | this_try = instruction++; |
7ee7b84d | 1037 | this_size = this_try->opcode->how & SN; |
252b5132 | 1038 | |
7ee7b84d MS |
1039 | if (this_try->noperands != noperands) |
1040 | found = 0; | |
1041 | else if (this_try->noperands > 0) | |
252b5132 | 1042 | { |
3048287a | 1043 | int i; |
252b5132 RH |
1044 | |
1045 | for (i = 0; i < this_try->noperands && found; i++) | |
1046 | { | |
a720f7bc | 1047 | op_type op = this_try->opcode->args.nib[i]; |
7ee7b84d MS |
1048 | int op_mode = op & MODE; |
1049 | int op_size = op & SIZE; | |
252b5132 | 1050 | int x = operands[i].mode; |
7ee7b84d MS |
1051 | int x_mode = x & MODE; |
1052 | int x_size = x & SIZE; | |
252b5132 | 1053 | |
7ee7b84d | 1054 | if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) |
252b5132 | 1055 | { |
7ee7b84d MS |
1056 | if ((x_size == L_8 && (operands[i].reg & 8) == 0) |
1057 | || (x_size == L_16 && (operands[i].reg & 8) == 8)) | |
1058 | as_warn (_("can't use high part of register in operand %d"), i); | |
1059 | ||
1060 | if (x_size != op_size) | |
1061 | found = 0; | |
252b5132 | 1062 | } |
7ee7b84d | 1063 | else if (op_mode == REG) |
252b5132 | 1064 | { |
7ee7b84d MS |
1065 | if (x_mode == LOWREG) |
1066 | x_mode = REG; | |
1067 | if (x_mode != REG) | |
252b5132 RH |
1068 | found = 0; |
1069 | ||
7ee7b84d MS |
1070 | if (x_size == L_P) |
1071 | x_size = (Hmode ? L_32 : L_16); | |
1072 | if (op_size == L_P) | |
1073 | op_size = (Hmode ? L_32 : L_16); | |
252b5132 | 1074 | |
70d6ecf3 | 1075 | /* The size of the reg is v important. */ |
7ee7b84d | 1076 | if (op_size != x_size) |
252b5132 RH |
1077 | found = 0; |
1078 | } | |
7ee7b84d | 1079 | else if (op_mode & CTRL) /* control register */ |
252b5132 | 1080 | { |
7ee7b84d MS |
1081 | if (!(x_mode & CTRL)) |
1082 | found = 0; | |
1083 | ||
1084 | switch (x_mode) | |
1085 | { | |
1086 | case CCR: | |
1087 | if (op_mode != CCR && | |
1088 | op_mode != CCR_EXR && | |
1089 | op_mode != CC_EX_VB_SB) | |
1090 | found = 0; | |
1091 | break; | |
1092 | case EXR: | |
1093 | if (op_mode != EXR && | |
1094 | op_mode != CCR_EXR && | |
1095 | op_mode != CC_EX_VB_SB) | |
1096 | found = 0; | |
1097 | break; | |
1098 | case MACH: | |
1099 | if (op_mode != MACH && | |
1100 | op_mode != MACREG) | |
1101 | found = 0; | |
1102 | break; | |
1103 | case MACL: | |
1104 | if (op_mode != MACL && | |
1105 | op_mode != MACREG) | |
1106 | found = 0; | |
1107 | break; | |
1108 | case VBR: | |
1109 | if (op_mode != VBR && | |
1110 | op_mode != VBR_SBR && | |
1111 | op_mode != CC_EX_VB_SB) | |
1112 | found = 0; | |
1113 | break; | |
1114 | case SBR: | |
1115 | if (op_mode != SBR && | |
1116 | op_mode != VBR_SBR && | |
1117 | op_mode != CC_EX_VB_SB) | |
1118 | found = 0; | |
1119 | break; | |
1120 | } | |
1121 | } | |
1122 | else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) | |
1123 | { | |
1124 | operands[i].mode &= ~MODE; | |
252b5132 | 1125 | operands[i].mode |= ABSJMP; |
70d6ecf3 | 1126 | /* But it may not be 24 bits long. */ |
7ee7b84d | 1127 | if (x_mode == ABS && !Hmode) |
252b5132 RH |
1128 | { |
1129 | operands[i].mode &= ~SIZE; | |
1130 | operands[i].mode |= L_16; | |
1131 | } | |
7ee7b84d MS |
1132 | if ((operands[i].mode & SIZE) == L_32 |
1133 | && (op_mode & SIZE) != L_32) | |
1134 | found = 0; | |
252b5132 | 1135 | } |
7ee7b84d | 1136 | else if (x_mode == IMM && op_mode != IMM) |
252b5132 | 1137 | { |
7ee7b84d MS |
1138 | offsetT num = operands[i].exp.X_add_number; |
1139 | if (op_mode == KBIT || op_mode == DBIT) | |
1140 | /* This is ok if the immediate value is sensible. */; | |
1141 | else if (op_mode == CONST_2) | |
1142 | found = num == 2; | |
1143 | else if (op_mode == CONST_4) | |
1144 | found = num == 4; | |
1145 | else if (op_mode == CONST_8) | |
1146 | found = num == 8; | |
1147 | else if (op_mode == CONST_16) | |
1148 | found = num == 16; | |
1149 | else | |
1150 | found = 0; | |
252b5132 | 1151 | } |
7ee7b84d | 1152 | else if (op_mode == PCREL && op_mode == x_mode) |
252b5132 | 1153 | { |
ba18dd6f | 1154 | /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: |
7ee7b84d | 1155 | If x_size is L_8, promote it. */ |
ba18dd6f AO |
1156 | if (OP_KIND (this_try->opcode->how) == O_MOVSD |
1157 | || OP_KIND (this_try->opcode->how) == O_BSRBC | |
1158 | || OP_KIND (this_try->opcode->how) == O_BSRBS) | |
7ee7b84d MS |
1159 | if (x_size == L_8) |
1160 | x_size = L_16; | |
1161 | ||
70d6ecf3 | 1162 | /* The size of the displacement is important. */ |
7ee7b84d | 1163 | if (op_size != x_size) |
252b5132 RH |
1164 | found = 0; |
1165 | } | |
7ee7b84d MS |
1166 | else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS |
1167 | || op_mode == INDEXB || op_mode == INDEXW | |
1168 | || op_mode == INDEXL) | |
1169 | && op_mode == x_mode) | |
252b5132 RH |
1170 | { |
1171 | /* Promote a L_24 to L_32 if it makes us match. */ | |
7ee7b84d | 1172 | if (x_size == L_24 && op_size == L_32) |
252b5132 | 1173 | { |
7ee7b84d MS |
1174 | x &= ~SIZE; |
1175 | x |= x_size = L_32; | |
252b5132 | 1176 | } |
7ee7b84d | 1177 | |
7ee7b84d | 1178 | if (((x_size == L_16 && op_size == L_16U) |
2d0d09ca | 1179 | || (x_size == L_8 && op_size == L_8U) |
7ee7b84d MS |
1180 | || (x_size == L_3 && op_size == L_3NZ)) |
1181 | /* We're deliberately more permissive for ABS modes. */ | |
1182 | && (op_mode == ABS | |
1183 | || constant_fits_size_p (operands + i, op_size, | |
1184 | op & NO_SYMBOLS))) | |
1185 | x_size = op_size; | |
1186 | ||
1187 | if (x_size != 0 && op_size != x_size) | |
1188 | found = 0; | |
1189 | else if (x_size == 0 | |
1190 | && ! constant_fits_size_p (operands + i, op_size, | |
1191 | op & NO_SYMBOLS)) | |
252b5132 RH |
1192 | found = 0; |
1193 | } | |
7ee7b84d | 1194 | else if (op_mode != x_mode) |
252b5132 RH |
1195 | { |
1196 | found = 0; | |
70d6ecf3 | 1197 | } |
252b5132 RH |
1198 | } |
1199 | } | |
7ee7b84d MS |
1200 | if (found) |
1201 | { | |
1202 | if ((this_try->opcode->available == AV_H8SX && ! SXmode) | |
d4ea8842 | 1203 | || (this_try->opcode->available == AV_H8S && ! Smode) |
7ee7b84d MS |
1204 | || (this_try->opcode->available == AV_H8H && ! Hmode)) |
1205 | found = 0, found_other = this_try; | |
1206 | else if (this_size != size && (this_size != SN && size != SN)) | |
1207 | found_mismatched = this_try, found = 0; | |
1208 | ||
1209 | } | |
252b5132 RH |
1210 | } |
1211 | if (found) | |
1212 | return this_try; | |
7ee7b84d MS |
1213 | if (found_other) |
1214 | { | |
1215 | as_warn (_("Opcode `%s' with these operand types not available in %s mode"), | |
1216 | found_other->opcode->name, | |
1217 | (! Hmode && ! Smode ? "H8/300" | |
1218 | : SXmode ? "H8sx" | |
1219 | : Smode ? "H8/300S" | |
1220 | : "H8/300H")); | |
1221 | } | |
1222 | else if (found_mismatched) | |
1223 | { | |
1224 | as_warn (_("mismatch between opcode size and operand size")); | |
1225 | return found_mismatched; | |
1226 | } | |
1227 | return 0; | |
252b5132 RH |
1228 | } |
1229 | ||
1230 | static void | |
b54a3392 | 1231 | check_operand (struct h8_op *operand, unsigned int width, char *string) |
252b5132 RH |
1232 | { |
1233 | if (operand->exp.X_add_symbol == 0 | |
1234 | && operand->exp.X_op_symbol == 0) | |
1235 | { | |
70d6ecf3 AM |
1236 | /* No symbol involved, let's look at offset, it's dangerous if |
1237 | any of the high bits are not 0 or ff's, find out by oring or | |
1238 | anding with the width and seeing if the answer is 0 or all | |
1239 | fs. */ | |
252b5132 | 1240 | |
7ee7b84d | 1241 | if (! constant_fits_width_p (operand, width)) |
252b5132 | 1242 | { |
70d6ecf3 | 1243 | if (width == 255 |
252b5132 RH |
1244 | && (operand->exp.X_add_number & 0xff00) == 0xff00) |
1245 | { | |
1246 | /* Just ignore this one - which happens when trying to | |
1247 | fit a 16 bit address truncated into an 8 bit address | |
1248 | of something like bset. */ | |
1249 | } | |
166e23f9 KH |
1250 | else if (strcmp (string, "@") == 0 |
1251 | && width == 0xffff | |
1252 | && (operand->exp.X_add_number & 0xff8000) == 0xff8000) | |
1253 | { | |
1254 | /* Just ignore this one - which happens when trying to | |
1255 | fit a 24 bit address truncated into a 16 bit address | |
1256 | of something like mov.w. */ | |
1257 | } | |
70d6ecf3 | 1258 | else |
252b5132 RH |
1259 | { |
1260 | as_warn (_("operand %s0x%lx out of range."), string, | |
1261 | (unsigned long) operand->exp.X_add_number); | |
1262 | } | |
1263 | } | |
1264 | } | |
252b5132 RH |
1265 | } |
1266 | ||
1267 | /* RELAXMODE has one of 3 values: | |
1268 | ||
1269 | 0 Output a "normal" reloc, no relaxing possible for this insn/reloc | |
1270 | ||
1271 | 1 Output a relaxable 24bit absolute mov.w address relocation | |
1272 | (may relax into a 16bit absolute address). | |
1273 | ||
1274 | 2 Output a relaxable 16/24 absolute mov.b address relocation | |
1275 | (may relax into an 8bit absolute address). */ | |
1276 | ||
1277 | static void | |
b54a3392 | 1278 | do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode) |
252b5132 RH |
1279 | { |
1280 | int idx; | |
1281 | int size; | |
1282 | int where; | |
7ee7b84d | 1283 | char *bytes = frag_now->fr_literal + offset; |
252b5132 | 1284 | |
7ee7b84d | 1285 | char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; |
252b5132 RH |
1286 | |
1287 | if (operand->exp.X_add_symbol == 0) | |
1288 | { | |
252b5132 RH |
1289 | switch (operand->mode & SIZE) |
1290 | { | |
1291 | case L_2: | |
1292 | check_operand (operand, 0x3, t); | |
7ee7b84d | 1293 | bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); |
252b5132 RH |
1294 | break; |
1295 | case L_3: | |
7ee7b84d | 1296 | case L_3NZ: |
252b5132 | 1297 | check_operand (operand, 0x7, t); |
7ee7b84d MS |
1298 | bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); |
1299 | break; | |
1300 | case L_4: | |
1301 | check_operand (operand, 0xF, t); | |
1302 | bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); | |
1303 | break; | |
1304 | case L_5: | |
1305 | check_operand (operand, 0x1F, t); | |
1306 | bytes[0] |= operand->exp.X_add_number & 31; | |
252b5132 RH |
1307 | break; |
1308 | case L_8: | |
7ee7b84d | 1309 | case L_8U: |
252b5132 | 1310 | check_operand (operand, 0xff, t); |
7ee7b84d | 1311 | bytes[0] |= operand->exp.X_add_number; |
252b5132 RH |
1312 | break; |
1313 | case L_16: | |
7ee7b84d | 1314 | case L_16U: |
252b5132 | 1315 | check_operand (operand, 0xffff, t); |
7ee7b84d MS |
1316 | bytes[0] |= operand->exp.X_add_number >> 8; |
1317 | bytes[1] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1318 | break; |
1319 | case L_24: | |
1320 | check_operand (operand, 0xffffff, t); | |
7ee7b84d MS |
1321 | bytes[0] |= operand->exp.X_add_number >> 16; |
1322 | bytes[1] |= operand->exp.X_add_number >> 8; | |
1323 | bytes[2] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1324 | break; |
1325 | ||
1326 | case L_32: | |
70d6ecf3 | 1327 | /* This should be done with bfd. */ |
7ee7b84d MS |
1328 | bytes[0] |= operand->exp.X_add_number >> 24; |
1329 | bytes[1] |= operand->exp.X_add_number >> 16; | |
1330 | bytes[2] |= operand->exp.X_add_number >> 8; | |
1331 | bytes[3] |= operand->exp.X_add_number >> 0; | |
4132022d AM |
1332 | if (relaxmode != 0) |
1333 | { | |
1334 | idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; | |
1335 | fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); | |
1336 | } | |
252b5132 RH |
1337 | break; |
1338 | } | |
252b5132 RH |
1339 | } |
1340 | else | |
1341 | { | |
1342 | switch (operand->mode & SIZE) | |
1343 | { | |
252b5132 RH |
1344 | case L_24: |
1345 | case L_32: | |
1346 | size = 4; | |
1347 | where = (operand->mode & SIZE) == L_24 ? -1 : 0; | |
1348 | if (relaxmode == 2) | |
1349 | idx = R_MOV24B1; | |
1350 | else if (relaxmode == 1) | |
1351 | idx = R_MOVL1; | |
1352 | else | |
1353 | idx = R_RELLONG; | |
1354 | break; | |
1355 | default: | |
70d6ecf3 | 1356 | as_bad (_("Can't work out size of operand.\n")); |
252b5132 | 1357 | case L_16: |
7ee7b84d | 1358 | case L_16U: |
252b5132 RH |
1359 | size = 2; |
1360 | where = 0; | |
1361 | if (relaxmode == 2) | |
1362 | idx = R_MOV16B1; | |
1363 | else | |
1364 | idx = R_RELWORD; | |
4132022d AM |
1365 | operand->exp.X_add_number = |
1366 | ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
7ee7b84d | 1367 | operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; |
252b5132 RH |
1368 | break; |
1369 | case L_8: | |
1370 | size = 1; | |
1371 | where = 0; | |
1372 | idx = R_RELBYTE; | |
4132022d AM |
1373 | operand->exp.X_add_number = |
1374 | ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
7ee7b84d | 1375 | operand->exp.X_add_number |= bytes[0]; |
252b5132 RH |
1376 | } |
1377 | ||
1378 | fix_new_exp (frag_now, | |
1379 | offset + where, | |
1380 | size, | |
1381 | &operand->exp, | |
1382 | 0, | |
1383 | idx); | |
1384 | } | |
252b5132 RH |
1385 | } |
1386 | ||
70d6ecf3 | 1387 | /* Now we know what sort of opcodes it is, let's build the bytes. */ |
3048287a | 1388 | |
252b5132 | 1389 | static void |
b54a3392 | 1390 | build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) |
252b5132 | 1391 | { |
3048287a | 1392 | int i; |
252b5132 | 1393 | char *output = frag_more (this_try->length); |
a720f7bc | 1394 | op_type *nibble_ptr = this_try->opcode->data.nib; |
252b5132 RH |
1395 | op_type c; |
1396 | unsigned int nibble_count = 0; | |
7ee7b84d | 1397 | int op_at[3]; |
3048287a | 1398 | int nib = 0; |
252b5132 | 1399 | int movb = 0; |
7ee7b84d | 1400 | char asnibbles[100]; |
252b5132 | 1401 | char *p = asnibbles; |
7ee7b84d | 1402 | int high, low; |
252b5132 | 1403 | |
d4ea8842 | 1404 | if (!Hmode && this_try->opcode->available != AV_H8) |
252b5132 | 1405 | as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), |
a720f7bc | 1406 | this_try->opcode->name); |
d4ea8842 MS |
1407 | else if (!Smode |
1408 | && this_try->opcode->available != AV_H8 | |
1409 | && this_try->opcode->available != AV_H8H) | |
1410 | as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), | |
1411 | this_try->opcode->name); | |
1412 | else if (!SXmode | |
1413 | && this_try->opcode->available != AV_H8 | |
1414 | && this_try->opcode->available != AV_H8H | |
1415 | && this_try->opcode->available != AV_H8S) | |
1416 | as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), | |
1417 | this_try->opcode->name); | |
252b5132 | 1418 | |
7ee7b84d | 1419 | while (*nibble_ptr != (op_type) E) |
252b5132 RH |
1420 | { |
1421 | int d; | |
7ee7b84d MS |
1422 | |
1423 | nib = 0; | |
252b5132 RH |
1424 | c = *nibble_ptr++; |
1425 | ||
7ee7b84d | 1426 | d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; |
252b5132 RH |
1427 | |
1428 | if (c < 16) | |
3048287a | 1429 | nib = c; |
252b5132 RH |
1430 | else |
1431 | { | |
7ee7b84d MS |
1432 | int c2 = c & MODE; |
1433 | ||
1434 | if (c2 == REG || c2 == LOWREG | |
1435 | || c2 == IND || c2 == PREINC || c2 == PREDEC | |
1436 | || c2 == POSTINC || c2 == POSTDEC) | |
1437 | { | |
1438 | nib = operand[d].reg; | |
1439 | if (c2 == LOWREG) | |
1440 | nib &= 7; | |
1441 | } | |
1442 | ||
1443 | else if (c & CTRL) /* Control reg operand. */ | |
3048287a NC |
1444 | nib = operand[d].reg; |
1445 | ||
252b5132 | 1446 | else if ((c & DISPREG) == (DISPREG)) |
7ee7b84d MS |
1447 | { |
1448 | nib = operand[d].reg; | |
1449 | } | |
1450 | else if (c2 == ABS) | |
252b5132 RH |
1451 | { |
1452 | operand[d].mode = c; | |
7ee7b84d | 1453 | op_at[d] = nibble_count; |
252b5132 RH |
1454 | nib = 0; |
1455 | } | |
7ee7b84d MS |
1456 | else if (c2 == IMM || c2 == PCREL || c2 == ABS |
1457 | || (c & ABSJMP) || c2 == DISP) | |
252b5132 RH |
1458 | { |
1459 | operand[d].mode = c; | |
7ee7b84d | 1460 | op_at[d] = nibble_count; |
252b5132 RH |
1461 | nib = 0; |
1462 | } | |
7ee7b84d | 1463 | else if ((c & IGNORE) || (c & DATA)) |
3048287a NC |
1464 | nib = 0; |
1465 | ||
7ee7b84d | 1466 | else if (c2 == DBIT) |
252b5132 RH |
1467 | { |
1468 | switch (operand[0].exp.X_add_number) | |
1469 | { | |
1470 | case 1: | |
1471 | nib = c; | |
1472 | break; | |
1473 | case 2: | |
1474 | nib = 0x8 | c; | |
1475 | break; | |
1476 | default: | |
1477 | as_bad (_("Need #1 or #2 here")); | |
1478 | } | |
1479 | } | |
7ee7b84d | 1480 | else if (c2 == KBIT) |
252b5132 RH |
1481 | { |
1482 | switch (operand[0].exp.X_add_number) | |
1483 | { | |
1484 | case 1: | |
1485 | nib = 0; | |
1486 | break; | |
1487 | case 2: | |
1488 | nib = 8; | |
1489 | break; | |
1490 | case 4: | |
1491 | if (!Hmode) | |
1492 | as_warn (_("#4 not valid on H8/300.")); | |
1493 | nib = 9; | |
1494 | break; | |
1495 | ||
1496 | default: | |
1497 | as_bad (_("Need #1 or #2 here")); | |
1498 | break; | |
1499 | } | |
70d6ecf3 | 1500 | /* Stop it making a fix. */ |
252b5132 RH |
1501 | operand[0].mode = 0; |
1502 | } | |
1503 | ||
1504 | if (c & MEMRELAX) | |
3048287a | 1505 | operand[d].mode |= MEMRELAX; |
252b5132 RH |
1506 | |
1507 | if (c & B31) | |
3048287a | 1508 | nib |= 0x8; |
252b5132 | 1509 | |
7ee7b84d MS |
1510 | if (c & B21) |
1511 | nib |= 0x4; | |
1512 | ||
1513 | if (c & B11) | |
1514 | nib |= 0x2; | |
1515 | ||
1516 | if (c & B01) | |
1517 | nib |= 0x1; | |
1518 | ||
1519 | if (c2 == MACREG) | |
252b5132 | 1520 | { |
f0c56b90 NC |
1521 | if (operand[0].mode == MACREG) |
1522 | /* stmac has mac[hl] as the first operand. */ | |
1523 | nib = 2 + operand[0].reg; | |
1524 | else | |
1525 | /* ldmac has mac[hl] as the second operand. */ | |
1526 | nib = 2 + operand[1].reg; | |
252b5132 RH |
1527 | } |
1528 | } | |
1529 | nibble_count++; | |
1530 | ||
1531 | *p++ = nib; | |
1532 | } | |
1533 | ||
1534 | /* Disgusting. Why, oh why didn't someone ask us for advice | |
1535 | on the assembler format. */ | |
7ee7b84d | 1536 | if (OP_KIND (this_try->opcode->how) == O_LDM) |
252b5132 | 1537 | { |
7ee7b84d MS |
1538 | high = (operand[1].reg >> 8) & 0xf; |
1539 | low = (operand[1].reg) & 0xf; | |
252b5132 | 1540 | asnibbles[2] = high - low; |
7ee7b84d MS |
1541 | asnibbles[7] = high; |
1542 | } | |
1543 | else if (OP_KIND (this_try->opcode->how) == O_STM) | |
1544 | { | |
1545 | high = (operand[0].reg >> 8) & 0xf; | |
1546 | low = (operand[0].reg) & 0xf; | |
1547 | asnibbles[2] = high - low; | |
1548 | asnibbles[7] = low; | |
252b5132 RH |
1549 | } |
1550 | ||
1551 | for (i = 0; i < this_try->length; i++) | |
3048287a | 1552 | output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; |
252b5132 | 1553 | |
ca9a79a1 NC |
1554 | /* Note if this is a movb or a bit manipulation instruction |
1555 | there is a special relaxation which only applies. */ | |
1556 | if ( this_try->opcode->how == O (O_MOV, SB) | |
1557 | || this_try->opcode->how == O (O_BCLR, SB) | |
1558 | || this_try->opcode->how == O (O_BAND, SB) | |
1559 | || this_try->opcode->how == O (O_BIAND, SB) | |
1560 | || this_try->opcode->how == O (O_BILD, SB) | |
1561 | || this_try->opcode->how == O (O_BIOR, SB) | |
1562 | || this_try->opcode->how == O (O_BIST, SB) | |
1563 | || this_try->opcode->how == O (O_BIXOR, SB) | |
1564 | || this_try->opcode->how == O (O_BLD, SB) | |
1565 | || this_try->opcode->how == O (O_BNOT, SB) | |
1566 | || this_try->opcode->how == O (O_BOR, SB) | |
1567 | || this_try->opcode->how == O (O_BSET, SB) | |
1568 | || this_try->opcode->how == O (O_BST, SB) | |
1569 | || this_try->opcode->how == O (O_BTST, SB) | |
1570 | || this_try->opcode->how == O (O_BXOR, SB)) | |
252b5132 RH |
1571 | movb = 1; |
1572 | ||
70d6ecf3 | 1573 | /* Output any fixes. */ |
7ee7b84d | 1574 | for (i = 0; i < this_try->noperands; i++) |
252b5132 RH |
1575 | { |
1576 | int x = operand[i].mode; | |
7ee7b84d | 1577 | int x_mode = x & MODE; |
252b5132 | 1578 | |
7ee7b84d MS |
1579 | if (x_mode == IMM || x_mode == DISP) |
1580 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1581 | op_at[i] & 1, operand + i, (x & MEMRELAX) != 0); | |
3048287a | 1582 | |
7ee7b84d MS |
1583 | else if (x_mode == ABS) |
1584 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1585 | op_at[i] & 1, operand + i, | |
1586 | (x & MEMRELAX) ? movb + 1 : 0); | |
3048287a | 1587 | |
7ee7b84d | 1588 | else if (x_mode == PCREL) |
252b5132 | 1589 | { |
7ee7b84d | 1590 | int size16 = (x & SIZE) == L_16; |
252b5132 RH |
1591 | int size = size16 ? 2 : 1; |
1592 | int type = size16 ? R_PCRWORD : R_PCRBYTE; | |
36ed2fff | 1593 | fixS *fixP; |
252b5132 RH |
1594 | |
1595 | check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); | |
1596 | ||
1597 | if (operand[i].exp.X_add_number & 1) | |
3048287a NC |
1598 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1599 | (unsigned long) operand->exp.X_add_number); | |
36ed2fff JL |
1600 | #ifndef OBJ_ELF |
1601 | /* The COFF port has always been off by one, changing it | |
1602 | now would be an incompatible change, so we leave it as-is. | |
1603 | ||
1604 | We don't want to do this for ELF as we want to be | |
1605 | compatible with the proposed ELF format from Hitachi. */ | |
252b5132 | 1606 | operand[i].exp.X_add_number -= 1; |
36ed2fff | 1607 | #endif |
7ee7b84d MS |
1608 | if (size16) |
1609 | { | |
1610 | operand[i].exp.X_add_number = | |
1611 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
1612 | } | |
1613 | else | |
1614 | { | |
1615 | operand[i].exp.X_add_number = | |
1616 | ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
1617 | } | |
1618 | ||
1619 | /* For BRA/S. */ | |
1620 | if (! size16) | |
1621 | operand[i].exp.X_add_number |= output[op_at[i] / 2]; | |
252b5132 | 1622 | |
36ed2fff | 1623 | fixP = fix_new_exp (frag_now, |
7ee7b84d | 1624 | output - frag_now->fr_literal + op_at[i] / 2, |
36ed2fff JL |
1625 | size, |
1626 | &operand[i].exp, | |
1627 | 1, | |
1628 | type); | |
1629 | fixP->fx_signed = 1; | |
252b5132 | 1630 | } |
7ee7b84d | 1631 | else if (x_mode == MEMIND) |
252b5132 | 1632 | { |
252b5132 RH |
1633 | check_operand (operand + i, 0xff, "@@"); |
1634 | fix_new_exp (frag_now, | |
1635 | output - frag_now->fr_literal + 1, | |
1636 | 1, | |
1637 | &operand[i].exp, | |
1638 | 0, | |
1639 | R_MEM_INDIRECT); | |
1640 | } | |
7ee7b84d MS |
1641 | else if (x_mode == VECIND) |
1642 | { | |
1643 | check_operand (operand + i, 0x7f, "@@"); | |
1644 | /* FIXME: approximating the effect of "B31" here... | |
1645 | This is very hackish, and ought to be done a better way. */ | |
1646 | operand[i].exp.X_add_number |= 0x80; | |
1647 | fix_new_exp (frag_now, | |
1648 | output - frag_now->fr_literal + 1, | |
1649 | 1, | |
1650 | &operand[i].exp, | |
1651 | 0, | |
1652 | R_MEM_INDIRECT); | |
1653 | } | |
252b5132 RH |
1654 | else if (x & ABSJMP) |
1655 | { | |
3c1ba8a3 | 1656 | int where = 0; |
7ee7b84d | 1657 | bfd_reloc_code_real_type reloc_type = R_JMPL1; |
3c1ba8a3 JL |
1658 | |
1659 | #ifdef OBJ_ELF | |
1660 | /* To be compatible with the proposed H8 ELF format, we | |
1661 | want the relocation's offset to point to the first byte | |
1662 | that will be modified, not to the start of the instruction. */ | |
7ee7b84d MS |
1663 | |
1664 | if ((operand->mode & SIZE) == L_32) | |
1665 | { | |
1666 | where = 2; | |
1667 | reloc_type = R_RELLONG; | |
1668 | } | |
1669 | else | |
1670 | where = 1; | |
3c1ba8a3 | 1671 | #endif |
de342d07 | 1672 | |
70d6ecf3 | 1673 | /* This jmp may be a jump or a branch. */ |
252b5132 | 1674 | |
7ee7b84d MS |
1675 | check_operand (operand + i, |
1676 | SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, | |
1677 | "@"); | |
3048287a | 1678 | |
252b5132 | 1679 | if (operand[i].exp.X_add_number & 1) |
3048287a NC |
1680 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1681 | (unsigned long) operand->exp.X_add_number); | |
1682 | ||
252b5132 | 1683 | if (!Hmode) |
70d6ecf3 | 1684 | operand[i].exp.X_add_number = |
4132022d | 1685 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
252b5132 | 1686 | fix_new_exp (frag_now, |
3c1ba8a3 | 1687 | output - frag_now->fr_literal + where, |
252b5132 RH |
1688 | 4, |
1689 | &operand[i].exp, | |
1690 | 0, | |
7ee7b84d | 1691 | reloc_type); |
252b5132 RH |
1692 | } |
1693 | } | |
252b5132 RH |
1694 | } |
1695 | ||
70d6ecf3 AM |
1696 | /* Try to give an intelligent error message for common and simple to |
1697 | detect errors. */ | |
3048287a | 1698 | |
252b5132 | 1699 | static void |
b54a3392 KH |
1700 | clever_message (const struct h8_instruction *instruction, |
1701 | struct h8_op *operand) | |
252b5132 | 1702 | { |
70d6ecf3 | 1703 | /* Find out if there was more than one possible opcode. */ |
252b5132 | 1704 | |
a720f7bc | 1705 | if ((instruction + 1)->idx != instruction->idx) |
252b5132 | 1706 | { |
3048287a | 1707 | int argn; |
252b5132 | 1708 | |
70d6ecf3 AM |
1709 | /* Only one opcode of this flavour, try to guess which operand |
1710 | didn't match. */ | |
a720f7bc | 1711 | for (argn = 0; argn < instruction->noperands; argn++) |
252b5132 | 1712 | { |
a720f7bc | 1713 | switch (instruction->opcode->args.nib[argn]) |
252b5132 RH |
1714 | { |
1715 | case RD16: | |
1716 | if (operand[argn].mode != RD16) | |
1717 | { | |
1718 | as_bad (_("destination operand must be 16 bit register")); | |
1719 | return; | |
1720 | ||
1721 | } | |
1722 | break; | |
1723 | ||
1724 | case RS8: | |
252b5132 RH |
1725 | if (operand[argn].mode != RS8) |
1726 | { | |
1727 | as_bad (_("source operand must be 8 bit register")); | |
1728 | return; | |
1729 | } | |
1730 | break; | |
1731 | ||
1732 | case ABS16DST: | |
1733 | if (operand[argn].mode != ABS16DST) | |
1734 | { | |
1735 | as_bad (_("destination operand must be 16bit absolute address")); | |
1736 | return; | |
1737 | } | |
1738 | break; | |
1739 | case RD8: | |
1740 | if (operand[argn].mode != RD8) | |
1741 | { | |
1742 | as_bad (_("destination operand must be 8 bit register")); | |
1743 | return; | |
1744 | } | |
1745 | break; | |
1746 | ||
252b5132 RH |
1747 | case ABS16SRC: |
1748 | if (operand[argn].mode != ABS16SRC) | |
1749 | { | |
1750 | as_bad (_("source operand must be 16bit absolute address")); | |
1751 | return; | |
1752 | } | |
1753 | break; | |
1754 | ||
1755 | } | |
1756 | } | |
1757 | } | |
1758 | as_bad (_("invalid operands")); | |
1759 | } | |
1760 | ||
d4ea8842 | 1761 | |
1b680e4f RS |
1762 | /* If OPERAND is part of an address, adjust its size and value given |
1763 | that it addresses SIZE bytes. | |
d4ea8842 | 1764 | |
1b680e4f RS |
1765 | This function decides how big non-immediate constants are when no |
1766 | size was explicitly given. It also scales down the assembly-level | |
d4ea8842 MS |
1767 | displacement in an @(d:2,ERn) operand. */ |
1768 | ||
1769 | static void | |
b54a3392 | 1770 | fix_operand_size (struct h8_op *operand, int size) |
d4ea8842 | 1771 | { |
1b680e4f | 1772 | if (SXmode && (operand->mode & MODE) == DISP) |
d4ea8842 MS |
1773 | { |
1774 | /* If the user didn't specify an operand width, see if we | |
1775 | can use @(d:2,ERn). */ | |
1b680e4f RS |
1776 | if ((operand->mode & SIZE) == 0 |
1777 | && operand->exp.X_add_symbol == 0 | |
1778 | && operand->exp.X_op_symbol == 0 | |
d4ea8842 MS |
1779 | && (operand->exp.X_add_number == size |
1780 | || operand->exp.X_add_number == size * 2 | |
1781 | || operand->exp.X_add_number == size * 3)) | |
1782 | operand->mode |= L_2; | |
1783 | ||
1784 | /* Scale down the displacement in an @(d:2,ERn) operand. | |
1785 | X_add_number then contains the desired field value. */ | |
1786 | if ((operand->mode & SIZE) == L_2) | |
1787 | { | |
1788 | if (operand->exp.X_add_number % size != 0) | |
1789 | as_warn (_("operand/size mis-match")); | |
1790 | operand->exp.X_add_number /= size; | |
1791 | } | |
1792 | } | |
1793 | ||
d4ea8842 MS |
1794 | if ((operand->mode & SIZE) == 0) |
1795 | switch (operand->mode & MODE) | |
1796 | { | |
1797 | case DISP: | |
1798 | case INDEXB: | |
1799 | case INDEXW: | |
1800 | case INDEXL: | |
1801 | case ABS: | |
1b680e4f RS |
1802 | /* Pick a 24-bit address unless we know that a 16-bit address |
1803 | is safe. get_specific() will relax L_24 into L_32 where | |
1804 | necessary. */ | |
1805 | if (Hmode | |
d4e2de6b | 1806 | && !Nmode |
1b680e4f RS |
1807 | && (operand->exp.X_add_number < -32768 |
1808 | || operand->exp.X_add_number > 32767 | |
1809 | || operand->exp.X_add_symbol != 0 | |
1810 | || operand->exp.X_op_symbol != 0)) | |
1811 | operand->mode |= L_24; | |
1812 | else | |
1813 | operand->mode |= L_16; | |
1814 | break; | |
1815 | ||
1816 | case PCREL: | |
1817 | /* This condition is long standing, though somewhat suspect. */ | |
1818 | if (operand->exp.X_add_number > -128 | |
1819 | && operand->exp.X_add_number < 127) | |
1820 | operand->mode |= L_8; | |
1821 | else | |
1822 | operand->mode |= L_16; | |
d4ea8842 MS |
1823 | break; |
1824 | } | |
1825 | } | |
1826 | ||
1827 | ||
70d6ecf3 AM |
1828 | /* This is the guts of the machine-dependent assembler. STR points to |
1829 | a machine dependent instruction. This function is supposed to emit | |
1830 | the frags/bytes it assembles. */ | |
3048287a | 1831 | |
252b5132 | 1832 | void |
b54a3392 | 1833 | md_assemble (char *str) |
252b5132 RH |
1834 | { |
1835 | char *op_start; | |
1836 | char *op_end; | |
7ee7b84d | 1837 | struct h8_op operand[3]; |
a720f7bc KD |
1838 | const struct h8_instruction *instruction; |
1839 | const struct h8_instruction *prev_instruction; | |
252b5132 RH |
1840 | |
1841 | char *dot = 0; | |
0c0b9be0 | 1842 | char *slash = 0; |
252b5132 | 1843 | char c; |
7ee7b84d | 1844 | int size, i; |
252b5132 | 1845 | |
70d6ecf3 | 1846 | /* Drop leading whitespace. */ |
252b5132 RH |
1847 | while (*str == ' ') |
1848 | str++; | |
1849 | ||
70d6ecf3 | 1850 | /* Find the op code end. */ |
252b5132 RH |
1851 | for (op_start = op_end = str; |
1852 | *op_end != 0 && *op_end != ' '; | |
1853 | op_end++) | |
1854 | { | |
1855 | if (*op_end == '.') | |
1856 | { | |
1857 | dot = op_end + 1; | |
1858 | *op_end = 0; | |
1859 | op_end += 2; | |
1860 | break; | |
1861 | } | |
0c0b9be0 AO |
1862 | else if (*op_end == '/' && ! slash) |
1863 | slash = op_end; | |
252b5132 RH |
1864 | } |
1865 | ||
252b5132 RH |
1866 | if (op_end == op_start) |
1867 | { | |
1868 | as_bad (_("can't find opcode ")); | |
1869 | } | |
1870 | c = *op_end; | |
1871 | ||
1872 | *op_end = 0; | |
1873 | ||
0c0b9be0 AO |
1874 | /* The assembler stops scanning the opcode at slashes, so it fails |
1875 | to make characters following them lower case. Fix them. */ | |
1876 | if (slash) | |
1877 | while (*++slash) | |
1878 | *slash = TOLOWER (*slash); | |
1879 | ||
a720f7bc KD |
1880 | instruction = (const struct h8_instruction *) |
1881 | hash_find (opcode_hash_control, op_start); | |
252b5132 | 1882 | |
a720f7bc | 1883 | if (instruction == NULL) |
252b5132 RH |
1884 | { |
1885 | as_bad (_("unknown opcode")); | |
1886 | return; | |
1887 | } | |
1888 | ||
70d6ecf3 | 1889 | /* We used to set input_line_pointer to the result of get_operands, |
252b5132 RH |
1890 | but that is wrong. Our caller assumes we don't change it. */ |
1891 | ||
7ee7b84d MS |
1892 | operand[0].mode = 0; |
1893 | operand[1].mode = 0; | |
1894 | operand[2].mode = 0; | |
1895 | ||
1896 | if (OP_KIND (instruction->opcode->how) == O_MOVAB | |
1897 | || OP_KIND (instruction->opcode->how) == O_MOVAW | |
1898 | || OP_KIND (instruction->opcode->how) == O_MOVAL) | |
1899 | get_mova_operands (op_end, operand); | |
1900 | else if (OP_KIND (instruction->opcode->how) == O_RTEL | |
1901 | || OP_KIND (instruction->opcode->how) == O_RTSL) | |
1902 | get_rtsl_operands (op_end, operand); | |
1903 | else | |
1904 | get_operands (instruction->noperands, op_end, operand); | |
1905 | ||
252b5132 | 1906 | *op_end = c; |
a720f7bc | 1907 | prev_instruction = instruction; |
252b5132 | 1908 | |
4892e510 NC |
1909 | /* Now we have operands from instruction. |
1910 | Let's check them out for ldm and stm. */ | |
1911 | if (OP_KIND (instruction->opcode->how) == O_LDM) | |
1912 | { | |
1913 | /* The first operand must be @er7+, and the | |
1914 | second operand must be a register pair. */ | |
1915 | if ((operand[0].mode != RSINC) | |
1916 | || (operand[0].reg != 7) | |
1917 | || ((operand[1].reg & 0x80000000) == 0)) | |
1918 | as_bad (_("invalid operand in ldm")); | |
1919 | } | |
1920 | else if (OP_KIND (instruction->opcode->how) == O_STM) | |
1921 | { | |
1922 | /* The first operand must be a register pair, | |
1923 | and the second operand must be @-er7. */ | |
1924 | if (((operand[0].reg & 0x80000000) == 0) | |
1925 | || (operand[1].mode != RDDEC) | |
1926 | || (operand[1].reg != 7)) | |
1927 | as_bad (_("invalid operand in stm")); | |
1928 | } | |
1929 | ||
252b5132 RH |
1930 | size = SN; |
1931 | if (dot) | |
1932 | { | |
0c0b9be0 | 1933 | switch (TOLOWER (*dot)) |
252b5132 RH |
1934 | { |
1935 | case 'b': | |
1936 | size = SB; | |
1937 | break; | |
1938 | ||
1939 | case 'w': | |
1940 | size = SW; | |
1941 | break; | |
1942 | ||
1943 | case 'l': | |
1944 | size = SL; | |
1945 | break; | |
1946 | } | |
1947 | } | |
7ee7b84d MS |
1948 | if (OP_KIND (instruction->opcode->how) == O_MOVAB || |
1949 | OP_KIND (instruction->opcode->how) == O_MOVAW || | |
1950 | OP_KIND (instruction->opcode->how) == O_MOVAL) | |
252b5132 | 1951 | { |
d4ea8842 MS |
1952 | switch (operand[0].mode & MODE) |
1953 | { | |
7ee7b84d MS |
1954 | case INDEXB: |
1955 | default: | |
d4ea8842 | 1956 | fix_operand_size (&operand[1], 1); |
7ee7b84d MS |
1957 | break; |
1958 | case INDEXW: | |
d4ea8842 | 1959 | fix_operand_size (&operand[1], 2); |
7ee7b84d MS |
1960 | break; |
1961 | case INDEXL: | |
d4ea8842 | 1962 | fix_operand_size (&operand[1], 4); |
7ee7b84d | 1963 | break; |
252b5132 RH |
1964 | } |
1965 | } | |
7ee7b84d MS |
1966 | else |
1967 | { | |
d4ea8842 MS |
1968 | for (i = 0; i < 3 && operand[i].mode != 0; i++) |
1969 | switch (size) | |
1970 | { | |
7ee7b84d MS |
1971 | case SN: |
1972 | case SB: | |
1973 | default: | |
d4ea8842 | 1974 | fix_operand_size (&operand[i], 1); |
7ee7b84d MS |
1975 | break; |
1976 | case SW: | |
d4ea8842 | 1977 | fix_operand_size (&operand[i], 2); |
7ee7b84d MS |
1978 | break; |
1979 | case SL: | |
d4ea8842 | 1980 | fix_operand_size (&operand[i], 4); |
7ee7b84d MS |
1981 | break; |
1982 | } | |
1983 | } | |
252b5132 | 1984 | |
d4ea8842 MS |
1985 | instruction = get_specific (instruction, operand, size); |
1986 | ||
1987 | if (instruction == 0) | |
1988 | { | |
1989 | /* Couldn't find an opcode which matched the operands. */ | |
1990 | char *where = frag_more (2); | |
1991 | ||
1992 | where[0] = 0x0; | |
1993 | where[1] = 0x0; | |
1994 | clever_message (prev_instruction, operand); | |
1995 | ||
1996 | return; | |
1997 | } | |
1998 | ||
a720f7bc | 1999 | build_bytes (instruction, operand); |
2c8714f2 | 2000 | |
2c8714f2 | 2001 | dwarf2_emit_insn (instruction->length); |
252b5132 RH |
2002 | } |
2003 | ||
2004 | symbolS * | |
b54a3392 | 2005 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
2006 | { |
2007 | return 0; | |
2008 | } | |
2009 | ||
252b5132 RH |
2010 | /* Various routines to kill one day */ |
2011 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
2012 | #define MAX_LITTLENUMS 6 | |
2013 | ||
70d6ecf3 AM |
2014 | /* Turn a string in input_line_pointer into a floating point constant |
2015 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
bc0d738a | 2016 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
70d6ecf3 | 2017 | returned, or NULL on OK. */ |
bc0d738a | 2018 | |
252b5132 | 2019 | char * |
b54a3392 | 2020 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
2021 | { |
2022 | int prec; | |
2023 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2024 | LITTLENUM_TYPE *wordP; | |
2025 | char *t; | |
252b5132 RH |
2026 | |
2027 | switch (type) | |
2028 | { | |
2029 | case 'f': | |
2030 | case 'F': | |
2031 | case 's': | |
2032 | case 'S': | |
2033 | prec = 2; | |
2034 | break; | |
2035 | ||
2036 | case 'd': | |
2037 | case 'D': | |
2038 | case 'r': | |
2039 | case 'R': | |
2040 | prec = 4; | |
2041 | break; | |
2042 | ||
2043 | case 'x': | |
2044 | case 'X': | |
2045 | prec = 6; | |
2046 | break; | |
2047 | ||
2048 | case 'p': | |
2049 | case 'P': | |
2050 | prec = 6; | |
2051 | break; | |
2052 | ||
2053 | default: | |
2054 | *sizeP = 0; | |
2055 | return _("Bad call to MD_ATOF()"); | |
2056 | } | |
2057 | t = atof_ieee (input_line_pointer, type, words); | |
2058 | if (t) | |
2059 | input_line_pointer = t; | |
2060 | ||
2061 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
2062 | for (wordP = words; prec--;) | |
2063 | { | |
2064 | md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); | |
2065 | litP += sizeof (LITTLENUM_TYPE); | |
2066 | } | |
2067 | return 0; | |
2068 | } | |
2069 | \f | |
5a38dc70 | 2070 | const char *md_shortopts = ""; |
252b5132 RH |
2071 | struct option md_longopts[] = { |
2072 | {NULL, no_argument, NULL, 0} | |
2073 | }; | |
70d6ecf3 AM |
2074 | |
2075 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
2076 | |
2077 | int | |
b54a3392 | 2078 | md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) |
252b5132 RH |
2079 | { |
2080 | return 0; | |
2081 | } | |
2082 | ||
2083 | void | |
b54a3392 | 2084 | md_show_usage (FILE *stream ATTRIBUTE_UNUSED) |
252b5132 RH |
2085 | { |
2086 | } | |
2087 | \f | |
b54a3392 | 2088 | void tc_aout_fix_to_chars (void); |
3048287a | 2089 | |
252b5132 | 2090 | void |
b54a3392 | 2091 | tc_aout_fix_to_chars (void) |
252b5132 RH |
2092 | { |
2093 | printf (_("call to tc_aout_fix_to_chars \n")); | |
2094 | abort (); | |
2095 | } | |
2096 | ||
2097 | void | |
7be1c489 | 2098 | md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, |
b54a3392 KH |
2099 | segT seg ATTRIBUTE_UNUSED, |
2100 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
2101 | { |
2102 | printf (_("call to md_convert_frag \n")); | |
2103 | abort (); | |
2104 | } | |
2105 | ||
3c1ba8a3 | 2106 | valueT |
b54a3392 | 2107 | md_section_align (segT segment, valueT size) |
3c1ba8a3 JL |
2108 | { |
2109 | int align = bfd_get_section_alignment (stdoutput, segment); | |
2110 | return ((size + (1 << align) - 1) & (-1 << align)); | |
2111 | } | |
252b5132 RH |
2112 | |
2113 | void | |
55cf6793 | 2114 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 RH |
2115 | { |
2116 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
a161fe53 | 2117 | long val = *valP; |
252b5132 RH |
2118 | |
2119 | switch (fixP->fx_size) | |
2120 | { | |
2121 | case 1: | |
2122 | *buf++ = val; | |
2123 | break; | |
2124 | case 2: | |
2125 | *buf++ = (val >> 8); | |
2126 | *buf++ = val; | |
2127 | break; | |
2128 | case 4: | |
2129 | *buf++ = (val >> 24); | |
2130 | *buf++ = (val >> 16); | |
2131 | *buf++ = (val >> 8); | |
2132 | *buf++ = val; | |
2133 | break; | |
2134 | default: | |
2135 | abort (); | |
2136 | } | |
94f592af NC |
2137 | |
2138 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) | |
2139 | fixP->fx_done = 1; | |
252b5132 RH |
2140 | } |
2141 | ||
2142 | int | |
b54a3392 KH |
2143 | md_estimate_size_before_relax (register fragS *fragP ATTRIBUTE_UNUSED, |
2144 | register segT segment_type ATTRIBUTE_UNUSED) | |
252b5132 RH |
2145 | { |
2146 | printf (_("call tomd_estimate_size_before_relax \n")); | |
2147 | abort (); | |
2148 | } | |
2149 | ||
70d6ecf3 | 2150 | /* Put number into target byte order. */ |
252b5132 | 2151 | void |
b54a3392 | 2152 | md_number_to_chars (char *ptr, valueT use, int nbytes) |
252b5132 RH |
2153 | { |
2154 | number_to_chars_bigendian (ptr, use, nbytes); | |
2155 | } | |
70d6ecf3 | 2156 | |
252b5132 | 2157 | long |
b54a3392 | 2158 | md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 RH |
2159 | { |
2160 | abort (); | |
2161 | } | |
2162 | ||
f333765f | 2163 | arelent * |
b54a3392 | 2164 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
f333765f JL |
2165 | { |
2166 | arelent *rel; | |
2167 | bfd_reloc_code_real_type r_type; | |
2168 | ||
de342d07 JL |
2169 | if (fixp->fx_addsy && fixp->fx_subsy) |
2170 | { | |
2171 | if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) | |
2172 | || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) | |
2173 | { | |
2174 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2175 | "Difference of symbols in different sections is not supported"); | |
2176 | return NULL; | |
2177 | } | |
2178 | } | |
2179 | ||
f333765f JL |
2180 | rel = (arelent *) xmalloc (sizeof (arelent)); |
2181 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2182 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
2183 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2184 | rel->addend = fixp->fx_offset; | |
2185 | ||
2186 | r_type = fixp->fx_r_type; | |
2187 | ||
2188 | #define DEBUG 0 | |
2189 | #if DEBUG | |
2190 | fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); | |
2191 | fflush(stderr); | |
2192 | #endif | |
2193 | rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); | |
2194 | if (rel->howto == NULL) | |
2195 | { | |
2196 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2197 | _("Cannot represent relocation type %s"), | |
2198 | bfd_get_reloc_code_name (r_type)); | |
2199 | return NULL; | |
2200 | } | |
2201 | ||
2202 | return rel; | |
2203 | } |