Commit | Line | Data |
---|---|---|
c2dcd04e | 1 | /* tc-h8300.c -- Assemble code for the Renesas H8/300 |
cc8a6dd0 | 2 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, |
c2dcd04e | 3 | 2001, 2002, 2003 Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
bc0d738a | 22 | /* Written By Steve Chamberlain <sac@cygnus.com>. */ |
252b5132 RH |
23 | |
24 | #include <stdio.h> | |
25 | #include "as.h" | |
26 | #include "subsegs.h" | |
27 | #include "bfd.h" | |
2c8714f2 NC |
28 | |
29 | #ifdef BFD_ASSEMBLER | |
30 | #include "dwarf2dbg.h" | |
31 | #endif | |
32 | ||
252b5132 RH |
33 | #define DEFINE_TABLE |
34 | #define h8_opcodes ops | |
35 | #include "opcode/h8300.h" | |
3882b010 | 36 | #include "safe-ctype.h" |
252b5132 | 37 | |
7e0de7bf JL |
38 | #ifdef OBJ_ELF |
39 | #include "elf/h8.h" | |
7e0de7bf JL |
40 | #endif |
41 | ||
63a0b638 | 42 | const char comment_chars[] = ";"; |
252b5132 | 43 | const char line_comment_chars[] = "#"; |
63a0b638 | 44 | const char line_separator_chars[] = ""; |
252b5132 | 45 | |
1b680e4f RS |
46 | void cons PARAMS ((int)); |
47 | void sbranch PARAMS ((int)); | |
48 | void h8300hmode PARAMS ((int)); | |
49 | void h8300smode PARAMS ((int)); | |
50 | void h8300hnmode PARAMS ((int)); | |
51 | void h8300snmode PARAMS ((int)); | |
52 | void h8300sxmode PARAMS ((int)); | |
53 | void h8300sxnmode PARAMS ((int)); | |
54 | static void pint PARAMS ((int)); | |
252b5132 RH |
55 | |
56 | int Hmode; | |
57 | int Smode; | |
8d9cd6b1 | 58 | int Nmode; |
7ee7b84d | 59 | int SXmode; |
3048287a | 60 | |
d4e2de6b | 61 | #define PSIZE (Hmode && !Nmode ? L_32 : L_16) |
3048287a | 62 | |
c2dcd04e | 63 | int bsize = L_8; /* Default branch displacement. */ |
252b5132 | 64 | |
a720f7bc KD |
65 | struct h8_instruction |
66 | { | |
67 | int length; | |
68 | int noperands; | |
69 | int idx; | |
70 | int size; | |
71 | const struct h8_opcode *opcode; | |
72 | }; | |
73 | ||
74 | struct h8_instruction *h8_instructions; | |
75 | ||
252b5132 | 76 | void |
3048287a NC |
77 | h8300hmode (arg) |
78 | int arg ATTRIBUTE_UNUSED; | |
252b5132 RH |
79 | { |
80 | Hmode = 1; | |
81 | Smode = 0; | |
83e20b45 JL |
82 | #ifdef BFD_ASSEMBLER |
83 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) | |
84 | as_warn (_("could not set architecture and machine")); | |
85 | #endif | |
252b5132 RH |
86 | } |
87 | ||
88 | void | |
3048287a NC |
89 | h8300smode (arg) |
90 | int arg ATTRIBUTE_UNUSED; | |
252b5132 RH |
91 | { |
92 | Smode = 1; | |
93 | Hmode = 1; | |
83e20b45 JL |
94 | #ifdef BFD_ASSEMBLER |
95 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) | |
96 | as_warn (_("could not set architecture and machine")); | |
97 | #endif | |
252b5132 | 98 | } |
70d6ecf3 | 99 | |
8d9cd6b1 NC |
100 | void |
101 | h8300hnmode (arg) | |
102 | int arg ATTRIBUTE_UNUSED; | |
103 | { | |
104 | Hmode = 1; | |
105 | Smode = 0; | |
106 | Nmode = 1; | |
107 | #ifdef BFD_ASSEMBLER | |
108 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) | |
109 | as_warn (_("could not set architecture and machine")); | |
110 | #endif | |
111 | } | |
112 | ||
113 | void | |
114 | h8300snmode (arg) | |
115 | int arg ATTRIBUTE_UNUSED; | |
116 | { | |
117 | Smode = 1; | |
118 | Hmode = 1; | |
119 | Nmode = 1; | |
120 | #ifdef BFD_ASSEMBLER | |
121 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) | |
122 | as_warn (_("could not set architecture and machine")); | |
123 | #endif | |
124 | } | |
125 | ||
7ee7b84d MS |
126 | void |
127 | h8300sxmode (arg) | |
128 | int arg ATTRIBUTE_UNUSED; | |
129 | { | |
130 | Smode = 1; | |
131 | Hmode = 1; | |
132 | SXmode = 1; | |
133 | #ifdef BFD_ASSEMBLER | |
134 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) | |
135 | as_warn (_("could not set architecture and machine")); | |
136 | #endif | |
137 | } | |
138 | ||
f4984206 RS |
139 | void |
140 | h8300sxnmode (arg) | |
141 | int arg ATTRIBUTE_UNUSED; | |
142 | { | |
143 | Smode = 1; | |
144 | Hmode = 1; | |
145 | SXmode = 1; | |
146 | Nmode = 1; | |
147 | #ifdef BFD_ASSEMBLER | |
148 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) | |
149 | as_warn (_("could not set architecture and machine")); | |
150 | #endif | |
151 | } | |
152 | ||
252b5132 RH |
153 | void |
154 | sbranch (size) | |
155 | int size; | |
156 | { | |
157 | bsize = size; | |
158 | } | |
159 | ||
70d6ecf3 | 160 | static void |
3048287a NC |
161 | pint (arg) |
162 | int arg ATTRIBUTE_UNUSED; | |
252b5132 RH |
163 | { |
164 | cons (Hmode ? 4 : 2); | |
165 | } | |
166 | ||
3048287a NC |
167 | /* This table describes all the machine specific pseudo-ops the assembler |
168 | has to support. The fields are: | |
169 | pseudo-op name without dot | |
170 | function to call to execute this pseudo-op | |
171 | Integer arg to pass to the function. */ | |
172 | ||
252b5132 RH |
173 | const pseudo_typeS md_pseudo_table[] = |
174 | { | |
7ee7b84d | 175 | {"h8300h", h8300hmode, 0}, |
8d9cd6b1 | 176 | {"h8300hn", h8300hnmode, 0}, |
7ee7b84d | 177 | {"h8300s", h8300smode, 0}, |
8d9cd6b1 | 178 | {"h8300sn", h8300snmode, 0}, |
7ee7b84d | 179 | {"h8300sx", h8300sxmode, 0}, |
f4984206 | 180 | {"h8300sxn", h8300sxnmode, 0}, |
252b5132 RH |
181 | {"sbranch", sbranch, L_8}, |
182 | {"lbranch", sbranch, L_16}, | |
183 | ||
184 | {"int", pint, 0}, | |
185 | {"data.b", cons, 1}, | |
186 | {"data.w", cons, 2}, | |
187 | {"data.l", cons, 4}, | |
188 | {"form", listing_psize, 0}, | |
189 | {"heading", listing_title, 0}, | |
7ee7b84d MS |
190 | {"import", s_ignore, 0}, |
191 | {"page", listing_eject, 0}, | |
252b5132 RH |
192 | {"program", s_ignore, 0}, |
193 | {0, 0, 0} | |
194 | }; | |
195 | ||
196 | const int md_reloc_size; | |
197 | ||
198 | const char EXP_CHARS[] = "eE"; | |
199 | ||
3048287a NC |
200 | /* Chars that mean this number is a floating point constant |
201 | As in 0f12.456 | |
202 | or 0d1.2345e12. */ | |
252b5132 RH |
203 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
204 | ||
3048287a | 205 | static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ |
252b5132 | 206 | |
70d6ecf3 AM |
207 | /* This function is called once, at assembler startup time. This |
208 | should set up all the tables, etc. that the MD part of the assembler | |
209 | needs. */ | |
3048287a | 210 | |
252b5132 RH |
211 | void |
212 | md_begin () | |
213 | { | |
a720f7bc | 214 | unsigned int nopcodes; |
7ee7b84d | 215 | struct h8_opcode *p, *p1; |
a720f7bc | 216 | struct h8_instruction *pi; |
252b5132 RH |
217 | char prev_buffer[100]; |
218 | int idx = 0; | |
219 | ||
83e20b45 JL |
220 | #ifdef BFD_ASSEMBLER |
221 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300)) | |
222 | as_warn (_("could not set architecture and machine")); | |
223 | #endif | |
224 | ||
252b5132 RH |
225 | opcode_hash_control = hash_new (); |
226 | prev_buffer[0] = 0; | |
227 | ||
a720f7bc KD |
228 | nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); |
229 | ||
230 | h8_instructions = (struct h8_instruction *) | |
231 | xmalloc (nopcodes * sizeof (struct h8_instruction)); | |
232 | ||
7ee7b84d MS |
233 | pi = h8_instructions; |
234 | p1 = h8_opcodes; | |
235 | /* We do a minimum amount of sorting on the opcode table; this is to | |
236 | make it easy to describe the mova instructions without unnecessary | |
237 | code duplication. | |
238 | Sorting only takes place inside blocks of instructions of the form | |
239 | X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ | |
240 | while (p1) | |
252b5132 | 241 | { |
7ee7b84d MS |
242 | struct h8_opcode *first_skipped = 0; |
243 | int len, cmplen = 0; | |
244 | char *src = p1->name; | |
245 | char *dst, *buffer; | |
252b5132 | 246 | |
7ee7b84d MS |
247 | if (p1->name == 0) |
248 | break; | |
249 | /* Strip off any . part when inserting the opcode and only enter | |
250 | unique codes into the hash table. */ | |
251 | dst = buffer = malloc (strlen (src) + 1); | |
252b5132 RH |
252 | while (*src) |
253 | { | |
254 | if (*src == '.') | |
255 | { | |
256 | src++; | |
252b5132 RH |
257 | break; |
258 | } | |
7ee7b84d MS |
259 | if (*src == '/') |
260 | cmplen = src - p1->name + 1; | |
252b5132 RH |
261 | *dst++ = *src++; |
262 | } | |
7ee7b84d MS |
263 | *dst = 0; |
264 | len = dst - buffer; | |
265 | if (cmplen == 0) | |
266 | cmplen = len; | |
267 | hash_insert (opcode_hash_control, buffer, (char *) pi); | |
268 | strcpy (prev_buffer, buffer); | |
269 | idx++; | |
270 | ||
271 | for (p = p1; p->name; p++) | |
252b5132 | 272 | { |
7ee7b84d MS |
273 | /* A negative TIME is used to indicate that we've added this opcode |
274 | already. */ | |
275 | if (p->time == -1) | |
276 | continue; | |
277 | if (strncmp (p->name, buffer, cmplen) != 0 | |
278 | || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' | |
279 | && p->name[cmplen - 1] != '/')) | |
280 | { | |
281 | if (first_skipped == 0) | |
282 | first_skipped = p; | |
283 | break; | |
284 | } | |
285 | if (strncmp (p->name, buffer, len) != 0) | |
286 | { | |
287 | if (first_skipped == 0) | |
288 | first_skipped = p; | |
289 | continue; | |
290 | } | |
291 | ||
292 | p->time = -1; | |
293 | pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; | |
294 | pi->idx = idx; | |
252b5132 | 295 | |
7ee7b84d MS |
296 | /* Find the number of operands. */ |
297 | pi->noperands = 0; | |
298 | while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) | |
299 | pi->noperands++; | |
70d6ecf3 | 300 | |
7ee7b84d MS |
301 | /* Find the length of the opcode in bytes. */ |
302 | pi->length = 0; | |
303 | while (p->data.nib[pi->length * 2] != (op_type) E) | |
304 | pi->length++; | |
a720f7bc | 305 | |
7ee7b84d MS |
306 | pi->opcode = p; |
307 | pi++; | |
308 | } | |
309 | p1 = first_skipped; | |
252b5132 RH |
310 | } |
311 | ||
a720f7bc KD |
312 | /* Add entry for the NULL vector terminator. */ |
313 | pi->length = 0; | |
314 | pi->noperands = 0; | |
315 | pi->idx = 0; | |
316 | pi->size = 0; | |
7ee7b84d | 317 | pi->opcode = 0; |
a720f7bc | 318 | |
252b5132 RH |
319 | linkrelax = 1; |
320 | } | |
321 | ||
252b5132 RH |
322 | struct h8_exp |
323 | { | |
324 | char *e_beg; | |
325 | char *e_end; | |
326 | expressionS e_exp; | |
327 | }; | |
70d6ecf3 | 328 | |
252b5132 RH |
329 | struct h8_op |
330 | { | |
331 | op_type mode; | |
332 | unsigned reg; | |
333 | expressionS exp; | |
334 | }; | |
335 | ||
a720f7bc | 336 | static void clever_message PARAMS ((const struct h8_instruction *, struct h8_op *)); |
d4ea8842 | 337 | static void fix_operand_size PARAMS ((struct h8_op *, int)); |
a720f7bc | 338 | static void build_bytes PARAMS ((const struct h8_instruction *, struct h8_op *)); |
7ee7b84d | 339 | static void do_a_fix_imm PARAMS ((int, int, struct h8_op *, int)); |
3048287a | 340 | static void check_operand PARAMS ((struct h8_op *, unsigned int, char *)); |
a720f7bc | 341 | static const struct h8_instruction * get_specific PARAMS ((const struct h8_instruction *, struct h8_op *, int)); |
1b680e4f RS |
342 | static char *get_operands PARAMS ((unsigned, char *, struct h8_op *)); |
343 | static void get_operand PARAMS ((char **, struct h8_op *, int)); | |
344 | static int parse_reg PARAMS ((char *, op_type *, unsigned *, int)); | |
345 | static char *skip_colonthing PARAMS ((char *, int *)); | |
346 | static char *parse_exp PARAMS ((char *, struct h8_op *)); | |
3048287a | 347 | |
7ee7b84d MS |
348 | static int constant_fits_width_p PARAMS ((struct h8_op *, unsigned int)); |
349 | static int constant_fits_size_p PARAMS ((struct h8_op *, int, int)); | |
350 | ||
252b5132 RH |
351 | /* |
352 | parse operands | |
353 | WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp | |
354 | r0l,r0h,..r7l,r7h | |
355 | @WREG | |
356 | @WREG+ | |
357 | @-WREG | |
358 | #const | |
359 | ccr | |
360 | */ | |
361 | ||
bc0d738a NC |
362 | /* Try to parse a reg name. Return the number of chars consumed. */ |
363 | ||
40f09f82 | 364 | static int |
252b5132 RH |
365 | parse_reg (src, mode, reg, direction) |
366 | char *src; | |
367 | op_type *mode; | |
368 | unsigned int *reg; | |
369 | int direction; | |
252b5132 RH |
370 | { |
371 | char *end; | |
372 | int len; | |
373 | ||
70d6ecf3 | 374 | /* Cribbed from get_symbol_end. */ |
252b5132 RH |
375 | if (!is_name_beginner (*src) || *src == '\001') |
376 | return 0; | |
70d6ecf3 | 377 | end = src + 1; |
7ee7b84d | 378 | while ((is_part_of_name (*end) && *end != '.') || *end == '\001') |
252b5132 RH |
379 | end++; |
380 | len = end - src; | |
381 | ||
7ee7b84d | 382 | if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
383 | { |
384 | *mode = PSIZE | REG | direction; | |
385 | *reg = 7; | |
386 | return len; | |
387 | } | |
7ee7b84d MS |
388 | if (len == 3 && |
389 | TOLOWER (src[0]) == 'c' && | |
390 | TOLOWER (src[1]) == 'c' && | |
391 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
392 | { |
393 | *mode = CCR; | |
394 | *reg = 0; | |
395 | return len; | |
396 | } | |
7ee7b84d MS |
397 | if (len == 3 && |
398 | TOLOWER (src[0]) == 'e' && | |
399 | TOLOWER (src[1]) == 'x' && | |
400 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
401 | { |
402 | *mode = EXR; | |
7ee7b84d MS |
403 | *reg = 1; |
404 | return len; | |
405 | } | |
406 | if (len == 3 && | |
407 | TOLOWER (src[0]) == 'v' && | |
408 | TOLOWER (src[1]) == 'b' && | |
409 | TOLOWER (src[2]) == 'r') | |
410 | { | |
411 | *mode = VBR; | |
412 | *reg = 6; | |
413 | return len; | |
414 | } | |
415 | if (len == 3 && | |
416 | TOLOWER (src[0]) == 's' && | |
417 | TOLOWER (src[1]) == 'b' && | |
418 | TOLOWER (src[2]) == 'r') | |
419 | { | |
420 | *mode = SBR; | |
421 | *reg = 7; | |
252b5132 RH |
422 | return len; |
423 | } | |
7ee7b84d | 424 | if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
425 | { |
426 | *mode = PSIZE | REG | direction; | |
427 | *reg = 6; | |
428 | return len; | |
429 | } | |
7ee7b84d MS |
430 | if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
431 | src[2] >= '0' && src[2] <= '7') | |
252b5132 RH |
432 | { |
433 | *mode = L_32 | REG | direction; | |
434 | *reg = src[2] - '0'; | |
435 | if (!Hmode) | |
436 | as_warn (_("Reg not valid for H8/300")); | |
437 | return len; | |
438 | } | |
7ee7b84d | 439 | if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') |
252b5132 RH |
440 | { |
441 | *mode = L_16 | REG | direction; | |
442 | *reg = src[1] - '0' + 8; | |
443 | if (!Hmode) | |
444 | as_warn (_("Reg not valid for H8/300")); | |
445 | return len; | |
446 | } | |
447 | ||
7ee7b84d | 448 | if (TOLOWER (src[0]) == 'r') |
252b5132 RH |
449 | { |
450 | if (src[1] >= '0' && src[1] <= '7') | |
451 | { | |
7ee7b84d | 452 | if (len == 3 && TOLOWER (src[2]) == 'l') |
252b5132 RH |
453 | { |
454 | *mode = L_8 | REG | direction; | |
455 | *reg = (src[1] - '0') + 8; | |
456 | return len; | |
457 | } | |
7ee7b84d | 458 | if (len == 3 && TOLOWER (src[2]) == 'h') |
252b5132 RH |
459 | { |
460 | *mode = L_8 | REG | direction; | |
461 | *reg = (src[1] - '0'); | |
462 | return len; | |
463 | } | |
464 | if (len == 2) | |
465 | { | |
466 | *mode = L_16 | REG | direction; | |
467 | *reg = (src[1] - '0'); | |
468 | return len; | |
469 | } | |
470 | } | |
471 | } | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
1b680e4f RS |
476 | |
477 | /* Parse an immediate or address-related constant and store it in OP. | |
478 | If the user also specifies the operand's size, store that size | |
479 | in OP->MODE, otherwise leave it for later code to decide. */ | |
480 | ||
40f09f82 | 481 | static char * |
1b680e4f RS |
482 | parse_exp (src, op) |
483 | char *src; | |
484 | struct h8_op *op; | |
252b5132 | 485 | { |
1b680e4f | 486 | char *save; |
252b5132 | 487 | |
1b680e4f RS |
488 | save = input_line_pointer; |
489 | input_line_pointer = src; | |
490 | expression (&op->exp); | |
491 | if (op->exp.X_op == O_absent) | |
252b5132 | 492 | as_bad (_("missing operand")); |
1b680e4f | 493 | src = input_line_pointer; |
252b5132 | 494 | input_line_pointer = save; |
1b680e4f RS |
495 | |
496 | return skip_colonthing (src, &op->mode); | |
252b5132 RH |
497 | } |
498 | ||
1b680e4f RS |
499 | |
500 | /* If SRC starts with an explicit operand size, skip it and store the size | |
501 | in *MODE. Leave *MODE unchanged otherwise. */ | |
502 | ||
252b5132 | 503 | static char * |
1b680e4f RS |
504 | skip_colonthing (src, mode) |
505 | char *src; | |
252b5132 RH |
506 | int *mode; |
507 | { | |
1b680e4f | 508 | if (*src == ':') |
252b5132 | 509 | { |
1b680e4f | 510 | src++; |
252b5132 | 511 | *mode &= ~SIZE; |
1b680e4f | 512 | if (src[0] == '8' && !ISDIGIT (src[1])) |
7ee7b84d | 513 | *mode |= L_8; |
1b680e4f | 514 | else if (src[0] == '2' && !ISDIGIT (src[1])) |
7ee7b84d | 515 | *mode |= L_2; |
1b680e4f | 516 | else if (src[0] == '3' && !ISDIGIT (src[1])) |
7ee7b84d | 517 | *mode |= L_3; |
1b680e4f | 518 | else if (src[0] == '4' && !ISDIGIT (src[1])) |
7ee7b84d | 519 | *mode |= L_4; |
1b680e4f | 520 | else if (src[0] == '5' && !ISDIGIT (src[1])) |
7ee7b84d | 521 | *mode |= L_5; |
1b680e4f | 522 | else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) |
7ee7b84d | 523 | *mode |= L_24; |
1b680e4f | 524 | else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) |
7ee7b84d | 525 | *mode |= L_32; |
1b680e4f | 526 | else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) |
7ee7b84d | 527 | *mode |= L_16; |
252b5132 | 528 | else |
7ee7b84d MS |
529 | as_bad (_("invalid operand size requested")); |
530 | ||
1b680e4f RS |
531 | while (ISDIGIT (*src)) |
532 | src++; | |
252b5132 | 533 | } |
1b680e4f | 534 | return src; |
252b5132 RH |
535 | } |
536 | ||
537 | /* The many forms of operand: | |
538 | ||
539 | Rn Register direct | |
540 | @Rn Register indirect | |
541 | @(exp[:16], Rn) Register indirect with displacement | |
542 | @Rn+ | |
543 | @-Rn | |
70d6ecf3 AM |
544 | @aa:8 absolute 8 bit |
545 | @aa:16 absolute 16 bit | |
252b5132 RH |
546 | @aa absolute 16 bit |
547 | ||
548 | #xx[:size] immediate data | |
70d6ecf3 | 549 | @(exp:[8], pc) pc rel |
3048287a | 550 | @@aa[:8] memory indirect. */ |
252b5132 | 551 | |
7ee7b84d MS |
552 | static int |
553 | constant_fits_width_p (operand, width) | |
554 | struct h8_op *operand; | |
555 | unsigned int width; | |
556 | { | |
557 | return ((operand->exp.X_add_number & ~width) == 0 | |
558 | || (operand->exp.X_add_number | width) == (unsigned)(~0)); | |
559 | } | |
560 | ||
561 | static int | |
562 | constant_fits_size_p (operand, size, no_symbols) | |
563 | struct h8_op *operand; | |
564 | int size, no_symbols; | |
565 | { | |
566 | offsetT num = operand->exp.X_add_number; | |
567 | if (no_symbols | |
568 | && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) | |
569 | return 0; | |
570 | switch (size) | |
571 | { | |
572 | case L_2: | |
573 | return (num & ~3) == 0; | |
574 | case L_3: | |
575 | return (num & ~7) == 0; | |
576 | case L_3NZ: | |
577 | return num >= 1 && num < 8; | |
578 | case L_4: | |
579 | return (num & ~15) == 0; | |
580 | case L_5: | |
581 | return num >= 1 && num < 32; | |
582 | case L_8: | |
583 | return (num & ~0xFF) == 0 || ((unsigned)num | 0x7F) == ~0u; | |
584 | case L_8U: | |
585 | return (num & ~0xFF) == 0; | |
586 | case L_16: | |
587 | return (num & ~0xFFFF) == 0 || ((unsigned)num | 0x7FFF) == ~0u; | |
588 | case L_16U: | |
589 | return (num & ~0xFFFF) == 0; | |
590 | case L_32: | |
591 | return 1; | |
592 | default: | |
593 | abort (); | |
594 | } | |
595 | } | |
596 | ||
252b5132 | 597 | static void |
7ee7b84d | 598 | get_operand (ptr, op, direction) |
252b5132 RH |
599 | char **ptr; |
600 | struct h8_op *op; | |
252b5132 RH |
601 | int direction; |
602 | { | |
603 | char *src = *ptr; | |
604 | op_type mode; | |
605 | unsigned int num; | |
606 | unsigned int len; | |
607 | ||
7ee7b84d | 608 | op->mode = 0; |
252b5132 | 609 | |
3048287a NC |
610 | /* Check for '(' and ')' for instructions ldm and stm. */ |
611 | if (src[0] == '(' && src[8] == ')') | |
612 | ++ src; | |
613 | ||
252b5132 RH |
614 | /* Gross. Gross. ldm and stm have a format not easily handled |
615 | by get_operand. We deal with it explicitly here. */ | |
7ee7b84d MS |
616 | if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
617 | ISDIGIT (src[2]) && src[3] == '-' && | |
618 | TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) | |
252b5132 RH |
619 | { |
620 | int low, high; | |
621 | ||
622 | low = src[2] - '0'; | |
623 | high = src[6] - '0'; | |
624 | ||
7ee7b84d | 625 | if (high == low) |
252b5132 RH |
626 | as_bad (_("Invalid register list for ldm/stm\n")); |
627 | ||
7ee7b84d | 628 | if (high < low) |
252b5132 RH |
629 | as_bad (_("Invalid register list for ldm/stm\n")); |
630 | ||
631 | if (high - low > 3) | |
7ee7b84d | 632 | as_bad (_("Invalid register list for ldm/stm)\n")); |
252b5132 RH |
633 | |
634 | /* Even sicker. We encode two registers into op->reg. One | |
635 | for the low register to save, the other for the high | |
636 | register to save; we also set the high bit in op->reg | |
637 | so we know this is "very special". */ | |
638 | op->reg = 0x80000000 | (high << 8) | low; | |
639 | op->mode = REG; | |
3048287a NC |
640 | if (src[7] == ')') |
641 | *ptr = src + 8; | |
642 | else | |
643 | *ptr = src + 7; | |
252b5132 RH |
644 | return; |
645 | } | |
646 | ||
647 | len = parse_reg (src, &op->mode, &op->reg, direction); | |
648 | if (len) | |
649 | { | |
7ee7b84d MS |
650 | src += len; |
651 | if (*src == '.') | |
652 | { | |
653 | int size = op->mode & SIZE; | |
654 | switch (src[1]) | |
655 | { | |
656 | case 'l': case 'L': | |
657 | if (size != L_32) | |
658 | as_warn (_("mismatch between register and suffix")); | |
659 | op->mode = (op->mode & ~MODE) | LOWREG; | |
660 | break; | |
661 | case 'w': case 'W': | |
662 | if (size != L_32 && size != L_16) | |
663 | as_warn (_("mismatch between register and suffix")); | |
664 | op->mode = (op->mode & ~MODE) | LOWREG; | |
665 | op->mode = (op->mode & ~SIZE) | L_16; | |
666 | break; | |
667 | case 'b': case 'B': | |
668 | op->mode = (op->mode & ~MODE) | LOWREG; | |
669 | if (size != L_32 && size != L_8) | |
670 | as_warn (_("mismatch between register and suffix")); | |
671 | op->mode = (op->mode & ~MODE) | LOWREG; | |
672 | op->mode = (op->mode & ~SIZE) | L_8; | |
673 | break; | |
674 | default: | |
675 | as_warn ("invalid suffix after register."); | |
676 | break; | |
677 | } | |
678 | src += 2; | |
679 | } | |
680 | *ptr = src; | |
252b5132 RH |
681 | return; |
682 | } | |
683 | ||
684 | if (*src == '@') | |
685 | { | |
686 | src++; | |
687 | if (*src == '@') | |
688 | { | |
1b680e4f | 689 | *ptr = parse_exp (src + 1, op); |
7ee7b84d MS |
690 | if (op->exp.X_add_number >= 0x100) |
691 | { | |
d4e2de6b | 692 | int divisor = 1; |
7ee7b84d MS |
693 | |
694 | op->mode = VECIND; | |
695 | /* FIXME : 2? or 4? */ | |
696 | if (op->exp.X_add_number >= 0x400) | |
697 | as_bad (_("address too high for vector table jmp/jsr")); | |
698 | else if (op->exp.X_add_number >= 0x200) | |
699 | divisor = 4; | |
700 | else | |
701 | divisor = 2; | |
702 | ||
703 | op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; | |
704 | } | |
705 | else | |
706 | op->mode = MEMIND; | |
252b5132 | 707 | return; |
252b5132 RH |
708 | } |
709 | ||
7ee7b84d | 710 | if (*src == '-' || *src == '+') |
252b5132 | 711 | { |
1b680e4f | 712 | len = parse_reg (src + 1, &mode, &num, direction); |
252b5132 RH |
713 | if (len == 0) |
714 | { | |
70d6ecf3 | 715 | /* Oops, not a reg after all, must be ordinary exp. */ |
1b680e4f RS |
716 | op->mode = ABS | direction; |
717 | *ptr = parse_exp (src, op); | |
252b5132 | 718 | return; |
252b5132 RH |
719 | } |
720 | ||
d4e2de6b NC |
721 | if (((mode & SIZE) != PSIZE) |
722 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
723 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 724 | as_bad (_("Wrong size pointer register for architecture.")); |
1b680e4f RS |
725 | |
726 | op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; | |
252b5132 | 727 | op->reg = num; |
1b680e4f | 728 | *ptr = src + 1 + len; |
252b5132 RH |
729 | return; |
730 | } | |
731 | if (*src == '(') | |
732 | { | |
252b5132 RH |
733 | src++; |
734 | ||
7ee7b84d MS |
735 | /* See if this is @(ERn.x, PC). */ |
736 | len = parse_reg (src, &mode, &op->reg, direction); | |
737 | if (len != 0 && (mode & MODE) == REG && src[len] == '.') | |
738 | { | |
739 | switch (TOLOWER (src[len + 1])) | |
740 | { | |
741 | case 'b': | |
742 | mode = PCIDXB | direction; | |
743 | break; | |
744 | case 'w': | |
745 | mode = PCIDXW | direction; | |
746 | break; | |
747 | case 'l': | |
748 | mode = PCIDXL | direction; | |
749 | break; | |
750 | default: | |
751 | mode = 0; | |
752 | break; | |
753 | } | |
754 | if (mode | |
755 | && src[len + 2] == ',' | |
756 | && TOLOWER (src[len + 3]) != 'p' | |
757 | && TOLOWER (src[len + 4]) != 'c' | |
758 | && src[len + 5] != ')') | |
759 | { | |
760 | *ptr = src + len + 6; | |
761 | op->mode |= mode; | |
762 | return; | |
763 | } | |
764 | /* Fall through into disp case - the grammar is somewhat | |
765 | ambiguous, so we should try whether it's a DISP operand | |
766 | after all ("ER3.L" might be a poorly named label...). */ | |
767 | } | |
768 | ||
769 | /* Disp. */ | |
770 | ||
70d6ecf3 | 771 | /* Start off assuming a 16 bit offset. */ |
252b5132 | 772 | |
1b680e4f | 773 | src = parse_exp (src, op); |
252b5132 RH |
774 | if (*src == ')') |
775 | { | |
252b5132 | 776 | op->mode |= ABS | direction; |
1b680e4f | 777 | *ptr = src + 1; |
252b5132 RH |
778 | return; |
779 | } | |
780 | ||
781 | if (*src != ',') | |
782 | { | |
783 | as_bad (_("expected @(exp, reg16)")); | |
784 | return; | |
252b5132 RH |
785 | } |
786 | src++; | |
787 | ||
788 | len = parse_reg (src, &mode, &op->reg, direction); | |
7ee7b84d | 789 | if (len == 0 || (mode & MODE) != REG) |
252b5132 RH |
790 | { |
791 | as_bad (_("expected @(exp, reg16)")); | |
792 | return; | |
793 | } | |
252b5132 | 794 | src += len; |
7ee7b84d MS |
795 | if (src[0] == '.') |
796 | { | |
797 | switch (TOLOWER (src[1])) | |
798 | { | |
799 | case 'b': | |
800 | op->mode |= INDEXB | direction; | |
801 | break; | |
802 | case 'w': | |
803 | op->mode |= INDEXW | direction; | |
804 | break; | |
805 | case 'l': | |
806 | op->mode |= INDEXL | direction; | |
807 | break; | |
808 | default: | |
809 | as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); | |
810 | } | |
811 | src += 2; | |
812 | op->reg &= 7; | |
813 | } | |
814 | else | |
815 | op->mode |= DISP | direction; | |
1b680e4f | 816 | src = skip_colonthing (src, &op->mode); |
252b5132 RH |
817 | |
818 | if (*src != ')' && '(') | |
819 | { | |
820 | as_bad (_("expected @(exp, reg16)")); | |
821 | return; | |
822 | } | |
823 | *ptr = src + 1; | |
252b5132 RH |
824 | return; |
825 | } | |
826 | len = parse_reg (src, &mode, &num, direction); | |
827 | ||
828 | if (len) | |
829 | { | |
830 | src += len; | |
7ee7b84d | 831 | if (*src == '+' || *src == '-') |
252b5132 | 832 | { |
d4e2de6b NC |
833 | if (((mode & SIZE) != PSIZE) |
834 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
835 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 836 | as_bad (_("Wrong size pointer register for architecture.")); |
7ee7b84d | 837 | op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; |
252b5132 | 838 | op->reg = num; |
7ee7b84d | 839 | src++; |
252b5132 RH |
840 | *ptr = src; |
841 | return; | |
842 | } | |
d4e2de6b NC |
843 | if (((mode & SIZE) != PSIZE) |
844 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
845 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 RH |
846 | as_bad (_("Wrong size pointer register for architecture.")); |
847 | ||
848 | op->mode = direction | IND | PSIZE; | |
849 | op->reg = num; | |
850 | *ptr = src; | |
851 | ||
852 | return; | |
853 | } | |
854 | else | |
855 | { | |
856 | /* must be a symbol */ | |
857 | ||
858 | op->mode = ABS | direction; | |
1b680e4f | 859 | *ptr = parse_exp (src, op); |
252b5132 RH |
860 | return; |
861 | } | |
862 | } | |
863 | ||
252b5132 RH |
864 | if (*src == '#') |
865 | { | |
252b5132 | 866 | op->mode = IMM; |
1b680e4f | 867 | *ptr = parse_exp (src + 1, op); |
252b5132 RH |
868 | return; |
869 | } | |
7ee7b84d MS |
870 | else if (strncmp (src, "mach", 4) == 0 || |
871 | strncmp (src, "macl", 4) == 0 || | |
872 | strncmp (src, "MACH", 4) == 0 || | |
873 | strncmp (src, "MACL", 4) == 0) | |
252b5132 | 874 | { |
7ee7b84d | 875 | op->reg = TOLOWER (src[3]) == 'l'; |
252b5132 RH |
876 | op->mode = MACREG; |
877 | *ptr = src + 4; | |
878 | return; | |
879 | } | |
880 | else | |
881 | { | |
1b680e4f RS |
882 | op->mode = PCREL; |
883 | *ptr = parse_exp (src, op); | |
252b5132 RH |
884 | } |
885 | } | |
886 | ||
70d6ecf3 | 887 | static char * |
252b5132 RH |
888 | get_operands (noperands, op_end, operand) |
889 | unsigned int noperands; | |
890 | char *op_end; | |
891 | struct h8_op *operand; | |
892 | { | |
893 | char *ptr = op_end; | |
894 | ||
895 | switch (noperands) | |
896 | { | |
897 | case 0: | |
252b5132 RH |
898 | break; |
899 | ||
900 | case 1: | |
901 | ptr++; | |
7ee7b84d | 902 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
903 | if (*ptr == ',') |
904 | { | |
905 | ptr++; | |
7ee7b84d | 906 | get_operand (&ptr, operand + 1, DST); |
252b5132 | 907 | } |
252b5132 | 908 | break; |
70d6ecf3 | 909 | |
252b5132 RH |
910 | case 2: |
911 | ptr++; | |
7ee7b84d | 912 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
913 | if (*ptr == ',') |
914 | ptr++; | |
7ee7b84d MS |
915 | get_operand (&ptr, operand + 1, DST); |
916 | break; | |
917 | ||
918 | case 3: | |
919 | ptr++; | |
920 | get_operand (&ptr, operand + 0, SRC); | |
921 | if (*ptr == ',') | |
922 | ptr++; | |
923 | get_operand (&ptr, operand + 1, DST); | |
924 | if (*ptr == ',') | |
925 | ptr++; | |
926 | get_operand (&ptr, operand + 2, OP3); | |
252b5132 RH |
927 | break; |
928 | ||
929 | default: | |
930 | abort (); | |
931 | } | |
932 | ||
252b5132 RH |
933 | return ptr; |
934 | } | |
935 | ||
7ee7b84d MS |
936 | /* MOVA has special requirements. Rather than adding twice the amount of |
937 | addressing modes, we simply special case it a bit. */ | |
938 | static void | |
939 | get_mova_operands (char *op_end, struct h8_op *operand) | |
940 | { | |
941 | char *ptr = op_end; | |
942 | ||
943 | if (ptr[1] != '@' || ptr[2] != '(') | |
944 | goto error; | |
945 | ptr += 3; | |
946 | operand[0].mode = 0; | |
1b680e4f | 947 | ptr = parse_exp (ptr, &operand[0]); |
7ee7b84d MS |
948 | |
949 | if (*ptr !=',') | |
950 | goto error; | |
951 | ptr++; | |
952 | get_operand (&ptr, operand + 1, DST); | |
953 | ||
954 | if (*ptr =='.') | |
955 | { | |
956 | ptr++; | |
957 | switch (*ptr++) | |
958 | { | |
959 | case 'b': case 'B': | |
960 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
961 | break; | |
962 | case 'w': case 'W': | |
963 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
964 | break; | |
965 | case 'l': case 'L': | |
966 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
967 | break; | |
968 | default: | |
969 | goto error; | |
970 | } | |
971 | } | |
972 | else if ((operand[1].mode & MODE) == LOWREG) | |
973 | { | |
974 | switch (operand[1].mode & SIZE) | |
975 | { | |
976 | case L_8: | |
977 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
978 | break; | |
979 | case L_16: | |
980 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
981 | break; | |
982 | case L_32: | |
983 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
984 | break; | |
985 | default: | |
986 | goto error; | |
987 | } | |
988 | } | |
989 | else | |
990 | goto error; | |
991 | ||
992 | if (*ptr++ != ')' || *ptr++ != ',') | |
993 | goto error; | |
994 | get_operand (&ptr, operand + 2, OP3); | |
995 | /* See if we can use the short form of MOVA. */ | |
996 | if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) | |
997 | && (operand[2].mode & MODE) == REG | |
998 | && (operand[1].reg & 7) == (operand[2].reg & 7)) | |
999 | { | |
1000 | operand[1].mode = operand[2].mode = 0; | |
1001 | operand[0].reg = operand[2].reg & 7; | |
1002 | } | |
1003 | return; | |
1004 | ||
1005 | error: | |
1006 | as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); | |
1007 | return; | |
1008 | } | |
1009 | ||
1010 | static void | |
1011 | get_rtsl_operands (char *ptr, struct h8_op *operand) | |
1012 | { | |
1013 | int mode, num, num2, len, type = 0; | |
1014 | ||
1015 | ptr++; | |
1016 | if (*ptr == '(') | |
1017 | { | |
1018 | ptr++; | |
1019 | type = 1; | |
1020 | } | |
1021 | len = parse_reg (ptr, &mode, &num, SRC); | |
1022 | if (len == 0 || (mode & MODE) != REG) | |
1023 | { | |
1024 | as_bad (_("expected register")); | |
1025 | return; | |
1026 | } | |
0613284f RS |
1027 | ptr += len; |
1028 | if (*ptr == '-') | |
7ee7b84d | 1029 | { |
0613284f | 1030 | len = parse_reg (++ptr, &mode, &num2, SRC); |
7ee7b84d MS |
1031 | if (len == 0 || (mode & MODE) != REG) |
1032 | { | |
1033 | as_bad (_("expected register")); | |
1034 | return; | |
1035 | } | |
1036 | ptr += len; | |
7ee7b84d MS |
1037 | /* CONST_xxx are used as placeholders in the opcode table. */ |
1038 | num = num2 - num; | |
0613284f | 1039 | if (num < 0 || num > 3) |
7ee7b84d MS |
1040 | { |
1041 | as_bad (_("invalid register list")); | |
1042 | return; | |
1043 | } | |
1044 | } | |
1045 | else | |
1046 | num2 = num, num = 0; | |
0613284f RS |
1047 | if (type == 1 && *ptr++ != ')') |
1048 | { | |
1049 | as_bad (_("expected closing paren")); | |
1050 | return; | |
1051 | } | |
7ee7b84d MS |
1052 | operand[0].mode = RS32; |
1053 | operand[1].mode = RD32; | |
1054 | operand[0].reg = num; | |
1055 | operand[1].reg = num2; | |
1056 | } | |
1057 | ||
252b5132 RH |
1058 | /* Passed a pointer to a list of opcodes which use different |
1059 | addressing modes, return the opcode which matches the opcodes | |
70d6ecf3 | 1060 | provided. */ |
3048287a | 1061 | |
a720f7bc KD |
1062 | static const struct h8_instruction * |
1063 | get_specific (instruction, operands, size) | |
1064 | const struct h8_instruction *instruction; | |
252b5132 RH |
1065 | struct h8_op *operands; |
1066 | int size; | |
1067 | { | |
a720f7bc | 1068 | const struct h8_instruction *this_try = instruction; |
7ee7b84d | 1069 | const struct h8_instruction *found_other = 0, *found_mismatched = 0; |
252b5132 | 1070 | int found = 0; |
a720f7bc | 1071 | int this_index = instruction->idx; |
7ee7b84d | 1072 | int noperands = 0; |
252b5132 RH |
1073 | |
1074 | /* There's only one ldm/stm and it's easier to just | |
1075 | get out quick for them. */ | |
7ee7b84d MS |
1076 | if (OP_KIND (instruction->opcode->how) == O_LDM |
1077 | || OP_KIND (instruction->opcode->how) == O_STM) | |
252b5132 RH |
1078 | return this_try; |
1079 | ||
7ee7b84d MS |
1080 | while (noperands < 3 && operands[noperands].mode != 0) |
1081 | noperands++; | |
1082 | ||
a720f7bc | 1083 | while (this_index == instruction->idx && !found) |
252b5132 | 1084 | { |
7ee7b84d | 1085 | int this_size; |
252b5132 | 1086 | |
7ee7b84d | 1087 | found = 1; |
a720f7bc | 1088 | this_try = instruction++; |
7ee7b84d | 1089 | this_size = this_try->opcode->how & SN; |
252b5132 | 1090 | |
7ee7b84d MS |
1091 | if (this_try->noperands != noperands) |
1092 | found = 0; | |
1093 | else if (this_try->noperands > 0) | |
252b5132 | 1094 | { |
3048287a | 1095 | int i; |
252b5132 RH |
1096 | |
1097 | for (i = 0; i < this_try->noperands && found; i++) | |
1098 | { | |
a720f7bc | 1099 | op_type op = this_try->opcode->args.nib[i]; |
7ee7b84d MS |
1100 | int op_mode = op & MODE; |
1101 | int op_size = op & SIZE; | |
252b5132 | 1102 | int x = operands[i].mode; |
7ee7b84d MS |
1103 | int x_mode = x & MODE; |
1104 | int x_size = x & SIZE; | |
252b5132 | 1105 | |
7ee7b84d | 1106 | if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) |
252b5132 | 1107 | { |
7ee7b84d MS |
1108 | if ((x_size == L_8 && (operands[i].reg & 8) == 0) |
1109 | || (x_size == L_16 && (operands[i].reg & 8) == 8)) | |
1110 | as_warn (_("can't use high part of register in operand %d"), i); | |
1111 | ||
1112 | if (x_size != op_size) | |
1113 | found = 0; | |
252b5132 | 1114 | } |
7ee7b84d | 1115 | else if (op_mode == REG) |
252b5132 | 1116 | { |
7ee7b84d MS |
1117 | if (x_mode == LOWREG) |
1118 | x_mode = REG; | |
1119 | if (x_mode != REG) | |
252b5132 RH |
1120 | found = 0; |
1121 | ||
7ee7b84d MS |
1122 | if (x_size == L_P) |
1123 | x_size = (Hmode ? L_32 : L_16); | |
1124 | if (op_size == L_P) | |
1125 | op_size = (Hmode ? L_32 : L_16); | |
252b5132 | 1126 | |
70d6ecf3 | 1127 | /* The size of the reg is v important. */ |
7ee7b84d | 1128 | if (op_size != x_size) |
252b5132 RH |
1129 | found = 0; |
1130 | } | |
7ee7b84d | 1131 | else if (op_mode & CTRL) /* control register */ |
252b5132 | 1132 | { |
7ee7b84d MS |
1133 | if (!(x_mode & CTRL)) |
1134 | found = 0; | |
1135 | ||
1136 | switch (x_mode) | |
1137 | { | |
1138 | case CCR: | |
1139 | if (op_mode != CCR && | |
1140 | op_mode != CCR_EXR && | |
1141 | op_mode != CC_EX_VB_SB) | |
1142 | found = 0; | |
1143 | break; | |
1144 | case EXR: | |
1145 | if (op_mode != EXR && | |
1146 | op_mode != CCR_EXR && | |
1147 | op_mode != CC_EX_VB_SB) | |
1148 | found = 0; | |
1149 | break; | |
1150 | case MACH: | |
1151 | if (op_mode != MACH && | |
1152 | op_mode != MACREG) | |
1153 | found = 0; | |
1154 | break; | |
1155 | case MACL: | |
1156 | if (op_mode != MACL && | |
1157 | op_mode != MACREG) | |
1158 | found = 0; | |
1159 | break; | |
1160 | case VBR: | |
1161 | if (op_mode != VBR && | |
1162 | op_mode != VBR_SBR && | |
1163 | op_mode != CC_EX_VB_SB) | |
1164 | found = 0; | |
1165 | break; | |
1166 | case SBR: | |
1167 | if (op_mode != SBR && | |
1168 | op_mode != VBR_SBR && | |
1169 | op_mode != CC_EX_VB_SB) | |
1170 | found = 0; | |
1171 | break; | |
1172 | } | |
1173 | } | |
1174 | else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) | |
1175 | { | |
1176 | operands[i].mode &= ~MODE; | |
252b5132 | 1177 | operands[i].mode |= ABSJMP; |
70d6ecf3 | 1178 | /* But it may not be 24 bits long. */ |
7ee7b84d | 1179 | if (x_mode == ABS && !Hmode) |
252b5132 RH |
1180 | { |
1181 | operands[i].mode &= ~SIZE; | |
1182 | operands[i].mode |= L_16; | |
1183 | } | |
7ee7b84d MS |
1184 | if ((operands[i].mode & SIZE) == L_32 |
1185 | && (op_mode & SIZE) != L_32) | |
1186 | found = 0; | |
252b5132 | 1187 | } |
7ee7b84d | 1188 | else if (x_mode == IMM && op_mode != IMM) |
252b5132 | 1189 | { |
7ee7b84d MS |
1190 | offsetT num = operands[i].exp.X_add_number; |
1191 | if (op_mode == KBIT || op_mode == DBIT) | |
1192 | /* This is ok if the immediate value is sensible. */; | |
1193 | else if (op_mode == CONST_2) | |
1194 | found = num == 2; | |
1195 | else if (op_mode == CONST_4) | |
1196 | found = num == 4; | |
1197 | else if (op_mode == CONST_8) | |
1198 | found = num == 8; | |
1199 | else if (op_mode == CONST_16) | |
1200 | found = num == 16; | |
1201 | else | |
1202 | found = 0; | |
252b5132 | 1203 | } |
7ee7b84d | 1204 | else if (op_mode == PCREL && op_mode == x_mode) |
252b5132 | 1205 | { |
ba18dd6f | 1206 | /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: |
7ee7b84d | 1207 | If x_size is L_8, promote it. */ |
ba18dd6f AO |
1208 | if (OP_KIND (this_try->opcode->how) == O_MOVSD |
1209 | || OP_KIND (this_try->opcode->how) == O_BSRBC | |
1210 | || OP_KIND (this_try->opcode->how) == O_BSRBS) | |
7ee7b84d MS |
1211 | if (x_size == L_8) |
1212 | x_size = L_16; | |
1213 | ||
70d6ecf3 | 1214 | /* The size of the displacement is important. */ |
7ee7b84d | 1215 | if (op_size != x_size) |
252b5132 RH |
1216 | found = 0; |
1217 | } | |
7ee7b84d MS |
1218 | else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS |
1219 | || op_mode == INDEXB || op_mode == INDEXW | |
1220 | || op_mode == INDEXL) | |
1221 | && op_mode == x_mode) | |
252b5132 RH |
1222 | { |
1223 | /* Promote a L_24 to L_32 if it makes us match. */ | |
7ee7b84d | 1224 | if (x_size == L_24 && op_size == L_32) |
252b5132 | 1225 | { |
7ee7b84d MS |
1226 | x &= ~SIZE; |
1227 | x |= x_size = L_32; | |
252b5132 | 1228 | } |
7ee7b84d MS |
1229 | |
1230 | #if 0 /* ??? */ | |
252b5132 | 1231 | /* Promote an L8 to L_16 if it makes us match. */ |
7ee7b84d | 1232 | if ((op_mode == ABS || op_mode == DISP) && x_size == L_8) |
252b5132 | 1233 | { |
7ee7b84d MS |
1234 | if (op_size == L_16) |
1235 | x_size = L_16; | |
252b5132 | 1236 | } |
7ee7b84d MS |
1237 | #endif |
1238 | ||
1239 | if (((x_size == L_16 && op_size == L_16U) | |
2d0d09ca | 1240 | || (x_size == L_8 && op_size == L_8U) |
7ee7b84d MS |
1241 | || (x_size == L_3 && op_size == L_3NZ)) |
1242 | /* We're deliberately more permissive for ABS modes. */ | |
1243 | && (op_mode == ABS | |
1244 | || constant_fits_size_p (operands + i, op_size, | |
1245 | op & NO_SYMBOLS))) | |
1246 | x_size = op_size; | |
1247 | ||
1248 | if (x_size != 0 && op_size != x_size) | |
1249 | found = 0; | |
1250 | else if (x_size == 0 | |
1251 | && ! constant_fits_size_p (operands + i, op_size, | |
1252 | op & NO_SYMBOLS)) | |
252b5132 RH |
1253 | found = 0; |
1254 | } | |
7ee7b84d | 1255 | else if (op_mode != x_mode) |
252b5132 RH |
1256 | { |
1257 | found = 0; | |
70d6ecf3 | 1258 | } |
252b5132 RH |
1259 | } |
1260 | } | |
7ee7b84d MS |
1261 | if (found) |
1262 | { | |
1263 | if ((this_try->opcode->available == AV_H8SX && ! SXmode) | |
d4ea8842 | 1264 | || (this_try->opcode->available == AV_H8S && ! Smode) |
7ee7b84d MS |
1265 | || (this_try->opcode->available == AV_H8H && ! Hmode)) |
1266 | found = 0, found_other = this_try; | |
1267 | else if (this_size != size && (this_size != SN && size != SN)) | |
1268 | found_mismatched = this_try, found = 0; | |
1269 | ||
1270 | } | |
252b5132 RH |
1271 | } |
1272 | if (found) | |
1273 | return this_try; | |
7ee7b84d MS |
1274 | if (found_other) |
1275 | { | |
1276 | as_warn (_("Opcode `%s' with these operand types not available in %s mode"), | |
1277 | found_other->opcode->name, | |
1278 | (! Hmode && ! Smode ? "H8/300" | |
1279 | : SXmode ? "H8sx" | |
1280 | : Smode ? "H8/300S" | |
1281 | : "H8/300H")); | |
1282 | } | |
1283 | else if (found_mismatched) | |
1284 | { | |
1285 | as_warn (_("mismatch between opcode size and operand size")); | |
1286 | return found_mismatched; | |
1287 | } | |
1288 | return 0; | |
252b5132 RH |
1289 | } |
1290 | ||
1291 | static void | |
1292 | check_operand (operand, width, string) | |
1293 | struct h8_op *operand; | |
1294 | unsigned int width; | |
1295 | char *string; | |
1296 | { | |
1297 | if (operand->exp.X_add_symbol == 0 | |
1298 | && operand->exp.X_op_symbol == 0) | |
1299 | { | |
70d6ecf3 AM |
1300 | /* No symbol involved, let's look at offset, it's dangerous if |
1301 | any of the high bits are not 0 or ff's, find out by oring or | |
1302 | anding with the width and seeing if the answer is 0 or all | |
1303 | fs. */ | |
252b5132 | 1304 | |
7ee7b84d | 1305 | if (! constant_fits_width_p (operand, width)) |
252b5132 | 1306 | { |
70d6ecf3 | 1307 | if (width == 255 |
252b5132 RH |
1308 | && (operand->exp.X_add_number & 0xff00) == 0xff00) |
1309 | { | |
1310 | /* Just ignore this one - which happens when trying to | |
1311 | fit a 16 bit address truncated into an 8 bit address | |
1312 | of something like bset. */ | |
1313 | } | |
166e23f9 KH |
1314 | else if (strcmp (string, "@") == 0 |
1315 | && width == 0xffff | |
1316 | && (operand->exp.X_add_number & 0xff8000) == 0xff8000) | |
1317 | { | |
1318 | /* Just ignore this one - which happens when trying to | |
1319 | fit a 24 bit address truncated into a 16 bit address | |
1320 | of something like mov.w. */ | |
1321 | } | |
70d6ecf3 | 1322 | else |
252b5132 RH |
1323 | { |
1324 | as_warn (_("operand %s0x%lx out of range."), string, | |
1325 | (unsigned long) operand->exp.X_add_number); | |
1326 | } | |
1327 | } | |
1328 | } | |
252b5132 RH |
1329 | } |
1330 | ||
1331 | /* RELAXMODE has one of 3 values: | |
1332 | ||
1333 | 0 Output a "normal" reloc, no relaxing possible for this insn/reloc | |
1334 | ||
1335 | 1 Output a relaxable 24bit absolute mov.w address relocation | |
1336 | (may relax into a 16bit absolute address). | |
1337 | ||
1338 | 2 Output a relaxable 16/24 absolute mov.b address relocation | |
1339 | (may relax into an 8bit absolute address). */ | |
1340 | ||
1341 | static void | |
7ee7b84d MS |
1342 | do_a_fix_imm (offset, nibble, operand, relaxmode) |
1343 | int offset, nibble; | |
252b5132 RH |
1344 | struct h8_op *operand; |
1345 | int relaxmode; | |
1346 | { | |
1347 | int idx; | |
1348 | int size; | |
1349 | int where; | |
7ee7b84d | 1350 | char *bytes = frag_now->fr_literal + offset; |
252b5132 | 1351 | |
7ee7b84d | 1352 | char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; |
252b5132 RH |
1353 | |
1354 | if (operand->exp.X_add_symbol == 0) | |
1355 | { | |
252b5132 RH |
1356 | switch (operand->mode & SIZE) |
1357 | { | |
1358 | case L_2: | |
1359 | check_operand (operand, 0x3, t); | |
7ee7b84d | 1360 | bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); |
252b5132 RH |
1361 | break; |
1362 | case L_3: | |
7ee7b84d | 1363 | case L_3NZ: |
252b5132 | 1364 | check_operand (operand, 0x7, t); |
7ee7b84d MS |
1365 | bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); |
1366 | break; | |
1367 | case L_4: | |
1368 | check_operand (operand, 0xF, t); | |
1369 | bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); | |
1370 | break; | |
1371 | case L_5: | |
1372 | check_operand (operand, 0x1F, t); | |
1373 | bytes[0] |= operand->exp.X_add_number & 31; | |
252b5132 RH |
1374 | break; |
1375 | case L_8: | |
7ee7b84d | 1376 | case L_8U: |
252b5132 | 1377 | check_operand (operand, 0xff, t); |
7ee7b84d | 1378 | bytes[0] |= operand->exp.X_add_number; |
252b5132 RH |
1379 | break; |
1380 | case L_16: | |
7ee7b84d | 1381 | case L_16U: |
252b5132 | 1382 | check_operand (operand, 0xffff, t); |
7ee7b84d MS |
1383 | bytes[0] |= operand->exp.X_add_number >> 8; |
1384 | bytes[1] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1385 | break; |
1386 | case L_24: | |
1387 | check_operand (operand, 0xffffff, t); | |
7ee7b84d MS |
1388 | bytes[0] |= operand->exp.X_add_number >> 16; |
1389 | bytes[1] |= operand->exp.X_add_number >> 8; | |
1390 | bytes[2] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1391 | break; |
1392 | ||
1393 | case L_32: | |
70d6ecf3 | 1394 | /* This should be done with bfd. */ |
7ee7b84d MS |
1395 | bytes[0] |= operand->exp.X_add_number >> 24; |
1396 | bytes[1] |= operand->exp.X_add_number >> 16; | |
1397 | bytes[2] |= operand->exp.X_add_number >> 8; | |
1398 | bytes[3] |= operand->exp.X_add_number >> 0; | |
4132022d AM |
1399 | if (relaxmode != 0) |
1400 | { | |
1401 | idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; | |
1402 | fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); | |
1403 | } | |
252b5132 RH |
1404 | break; |
1405 | } | |
252b5132 RH |
1406 | } |
1407 | else | |
1408 | { | |
1409 | switch (operand->mode & SIZE) | |
1410 | { | |
252b5132 RH |
1411 | case L_24: |
1412 | case L_32: | |
1413 | size = 4; | |
1414 | where = (operand->mode & SIZE) == L_24 ? -1 : 0; | |
1415 | if (relaxmode == 2) | |
1416 | idx = R_MOV24B1; | |
1417 | else if (relaxmode == 1) | |
1418 | idx = R_MOVL1; | |
1419 | else | |
1420 | idx = R_RELLONG; | |
1421 | break; | |
1422 | default: | |
70d6ecf3 | 1423 | as_bad (_("Can't work out size of operand.\n")); |
252b5132 | 1424 | case L_16: |
7ee7b84d | 1425 | case L_16U: |
252b5132 RH |
1426 | size = 2; |
1427 | where = 0; | |
1428 | if (relaxmode == 2) | |
1429 | idx = R_MOV16B1; | |
1430 | else | |
1431 | idx = R_RELWORD; | |
4132022d AM |
1432 | operand->exp.X_add_number = |
1433 | ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
7ee7b84d | 1434 | operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; |
252b5132 RH |
1435 | break; |
1436 | case L_8: | |
1437 | size = 1; | |
1438 | where = 0; | |
1439 | idx = R_RELBYTE; | |
4132022d AM |
1440 | operand->exp.X_add_number = |
1441 | ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
7ee7b84d | 1442 | operand->exp.X_add_number |= bytes[0]; |
252b5132 RH |
1443 | } |
1444 | ||
1445 | fix_new_exp (frag_now, | |
1446 | offset + where, | |
1447 | size, | |
1448 | &operand->exp, | |
1449 | 0, | |
1450 | idx); | |
1451 | } | |
252b5132 RH |
1452 | } |
1453 | ||
70d6ecf3 | 1454 | /* Now we know what sort of opcodes it is, let's build the bytes. */ |
3048287a | 1455 | |
252b5132 RH |
1456 | static void |
1457 | build_bytes (this_try, operand) | |
a720f7bc | 1458 | const struct h8_instruction *this_try; |
252b5132 RH |
1459 | struct h8_op *operand; |
1460 | { | |
3048287a | 1461 | int i; |
252b5132 | 1462 | char *output = frag_more (this_try->length); |
a720f7bc | 1463 | op_type *nibble_ptr = this_try->opcode->data.nib; |
252b5132 RH |
1464 | op_type c; |
1465 | unsigned int nibble_count = 0; | |
7ee7b84d | 1466 | int op_at[3]; |
3048287a | 1467 | int nib = 0; |
252b5132 | 1468 | int movb = 0; |
7ee7b84d | 1469 | char asnibbles[100]; |
252b5132 | 1470 | char *p = asnibbles; |
7ee7b84d | 1471 | int high, low; |
252b5132 | 1472 | |
d4ea8842 | 1473 | if (!Hmode && this_try->opcode->available != AV_H8) |
252b5132 | 1474 | as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), |
a720f7bc | 1475 | this_try->opcode->name); |
d4ea8842 MS |
1476 | else if (!Smode |
1477 | && this_try->opcode->available != AV_H8 | |
1478 | && this_try->opcode->available != AV_H8H) | |
1479 | as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), | |
1480 | this_try->opcode->name); | |
1481 | else if (!SXmode | |
1482 | && this_try->opcode->available != AV_H8 | |
1483 | && this_try->opcode->available != AV_H8H | |
1484 | && this_try->opcode->available != AV_H8S) | |
1485 | as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), | |
1486 | this_try->opcode->name); | |
252b5132 | 1487 | |
7ee7b84d | 1488 | while (*nibble_ptr != (op_type) E) |
252b5132 RH |
1489 | { |
1490 | int d; | |
7ee7b84d MS |
1491 | |
1492 | nib = 0; | |
252b5132 RH |
1493 | c = *nibble_ptr++; |
1494 | ||
7ee7b84d | 1495 | d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; |
252b5132 RH |
1496 | |
1497 | if (c < 16) | |
3048287a | 1498 | nib = c; |
252b5132 RH |
1499 | else |
1500 | { | |
7ee7b84d MS |
1501 | int c2 = c & MODE; |
1502 | ||
1503 | if (c2 == REG || c2 == LOWREG | |
1504 | || c2 == IND || c2 == PREINC || c2 == PREDEC | |
1505 | || c2 == POSTINC || c2 == POSTDEC) | |
1506 | { | |
1507 | nib = operand[d].reg; | |
1508 | if (c2 == LOWREG) | |
1509 | nib &= 7; | |
1510 | } | |
1511 | ||
1512 | else if (c & CTRL) /* Control reg operand. */ | |
3048287a NC |
1513 | nib = operand[d].reg; |
1514 | ||
252b5132 | 1515 | else if ((c & DISPREG) == (DISPREG)) |
7ee7b84d MS |
1516 | { |
1517 | nib = operand[d].reg; | |
1518 | } | |
1519 | else if (c2 == ABS) | |
252b5132 RH |
1520 | { |
1521 | operand[d].mode = c; | |
7ee7b84d | 1522 | op_at[d] = nibble_count; |
252b5132 RH |
1523 | nib = 0; |
1524 | } | |
7ee7b84d MS |
1525 | else if (c2 == IMM || c2 == PCREL || c2 == ABS |
1526 | || (c & ABSJMP) || c2 == DISP) | |
252b5132 RH |
1527 | { |
1528 | operand[d].mode = c; | |
7ee7b84d | 1529 | op_at[d] = nibble_count; |
252b5132 RH |
1530 | nib = 0; |
1531 | } | |
7ee7b84d | 1532 | else if ((c & IGNORE) || (c & DATA)) |
3048287a NC |
1533 | nib = 0; |
1534 | ||
7ee7b84d | 1535 | else if (c2 == DBIT) |
252b5132 RH |
1536 | { |
1537 | switch (operand[0].exp.X_add_number) | |
1538 | { | |
1539 | case 1: | |
1540 | nib = c; | |
1541 | break; | |
1542 | case 2: | |
1543 | nib = 0x8 | c; | |
1544 | break; | |
1545 | default: | |
1546 | as_bad (_("Need #1 or #2 here")); | |
1547 | } | |
1548 | } | |
7ee7b84d | 1549 | else if (c2 == KBIT) |
252b5132 RH |
1550 | { |
1551 | switch (operand[0].exp.X_add_number) | |
1552 | { | |
1553 | case 1: | |
1554 | nib = 0; | |
1555 | break; | |
1556 | case 2: | |
1557 | nib = 8; | |
1558 | break; | |
1559 | case 4: | |
1560 | if (!Hmode) | |
1561 | as_warn (_("#4 not valid on H8/300.")); | |
1562 | nib = 9; | |
1563 | break; | |
1564 | ||
1565 | default: | |
1566 | as_bad (_("Need #1 or #2 here")); | |
1567 | break; | |
1568 | } | |
70d6ecf3 | 1569 | /* Stop it making a fix. */ |
252b5132 RH |
1570 | operand[0].mode = 0; |
1571 | } | |
1572 | ||
1573 | if (c & MEMRELAX) | |
3048287a | 1574 | operand[d].mode |= MEMRELAX; |
252b5132 RH |
1575 | |
1576 | if (c & B31) | |
3048287a | 1577 | nib |= 0x8; |
252b5132 | 1578 | |
7ee7b84d MS |
1579 | if (c & B21) |
1580 | nib |= 0x4; | |
1581 | ||
1582 | if (c & B11) | |
1583 | nib |= 0x2; | |
1584 | ||
1585 | if (c & B01) | |
1586 | nib |= 0x1; | |
1587 | ||
1588 | if (c2 == MACREG) | |
252b5132 | 1589 | { |
f0c56b90 NC |
1590 | if (operand[0].mode == MACREG) |
1591 | /* stmac has mac[hl] as the first operand. */ | |
1592 | nib = 2 + operand[0].reg; | |
1593 | else | |
1594 | /* ldmac has mac[hl] as the second operand. */ | |
1595 | nib = 2 + operand[1].reg; | |
252b5132 RH |
1596 | } |
1597 | } | |
1598 | nibble_count++; | |
1599 | ||
1600 | *p++ = nib; | |
1601 | } | |
1602 | ||
1603 | /* Disgusting. Why, oh why didn't someone ask us for advice | |
1604 | on the assembler format. */ | |
7ee7b84d | 1605 | if (OP_KIND (this_try->opcode->how) == O_LDM) |
252b5132 | 1606 | { |
7ee7b84d MS |
1607 | high = (operand[1].reg >> 8) & 0xf; |
1608 | low = (operand[1].reg) & 0xf; | |
252b5132 | 1609 | asnibbles[2] = high - low; |
7ee7b84d MS |
1610 | asnibbles[7] = high; |
1611 | } | |
1612 | else if (OP_KIND (this_try->opcode->how) == O_STM) | |
1613 | { | |
1614 | high = (operand[0].reg >> 8) & 0xf; | |
1615 | low = (operand[0].reg) & 0xf; | |
1616 | asnibbles[2] = high - low; | |
1617 | asnibbles[7] = low; | |
252b5132 RH |
1618 | } |
1619 | ||
1620 | for (i = 0; i < this_try->length; i++) | |
3048287a | 1621 | output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; |
252b5132 RH |
1622 | |
1623 | /* Note if this is a movb instruction -- there's a special relaxation | |
1624 | which only applies to them. */ | |
7ee7b84d | 1625 | if (this_try->opcode->how == O (O_MOV, SB)) |
252b5132 RH |
1626 | movb = 1; |
1627 | ||
70d6ecf3 | 1628 | /* Output any fixes. */ |
7ee7b84d | 1629 | for (i = 0; i < this_try->noperands; i++) |
252b5132 RH |
1630 | { |
1631 | int x = operand[i].mode; | |
7ee7b84d | 1632 | int x_mode = x & MODE; |
252b5132 | 1633 | |
7ee7b84d MS |
1634 | if (x_mode == IMM || x_mode == DISP) |
1635 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1636 | op_at[i] & 1, operand + i, (x & MEMRELAX) != 0); | |
3048287a | 1637 | |
7ee7b84d MS |
1638 | else if (x_mode == ABS) |
1639 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1640 | op_at[i] & 1, operand + i, | |
1641 | (x & MEMRELAX) ? movb + 1 : 0); | |
3048287a | 1642 | |
7ee7b84d | 1643 | else if (x_mode == PCREL) |
252b5132 | 1644 | { |
7ee7b84d | 1645 | int size16 = (x & SIZE) == L_16; |
252b5132 RH |
1646 | int size = size16 ? 2 : 1; |
1647 | int type = size16 ? R_PCRWORD : R_PCRBYTE; | |
36ed2fff | 1648 | fixS *fixP; |
252b5132 RH |
1649 | |
1650 | check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); | |
1651 | ||
1652 | if (operand[i].exp.X_add_number & 1) | |
3048287a NC |
1653 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1654 | (unsigned long) operand->exp.X_add_number); | |
36ed2fff JL |
1655 | #ifndef OBJ_ELF |
1656 | /* The COFF port has always been off by one, changing it | |
1657 | now would be an incompatible change, so we leave it as-is. | |
1658 | ||
1659 | We don't want to do this for ELF as we want to be | |
1660 | compatible with the proposed ELF format from Hitachi. */ | |
252b5132 | 1661 | operand[i].exp.X_add_number -= 1; |
36ed2fff | 1662 | #endif |
7ee7b84d MS |
1663 | if (size16) |
1664 | { | |
1665 | operand[i].exp.X_add_number = | |
1666 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
1667 | } | |
1668 | else | |
1669 | { | |
1670 | operand[i].exp.X_add_number = | |
1671 | ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
1672 | } | |
1673 | ||
1674 | /* For BRA/S. */ | |
1675 | if (! size16) | |
1676 | operand[i].exp.X_add_number |= output[op_at[i] / 2]; | |
252b5132 | 1677 | |
36ed2fff | 1678 | fixP = fix_new_exp (frag_now, |
7ee7b84d | 1679 | output - frag_now->fr_literal + op_at[i] / 2, |
36ed2fff JL |
1680 | size, |
1681 | &operand[i].exp, | |
1682 | 1, | |
1683 | type); | |
1684 | fixP->fx_signed = 1; | |
252b5132 | 1685 | } |
7ee7b84d | 1686 | else if (x_mode == MEMIND) |
252b5132 | 1687 | { |
252b5132 RH |
1688 | check_operand (operand + i, 0xff, "@@"); |
1689 | fix_new_exp (frag_now, | |
1690 | output - frag_now->fr_literal + 1, | |
1691 | 1, | |
1692 | &operand[i].exp, | |
1693 | 0, | |
1694 | R_MEM_INDIRECT); | |
1695 | } | |
7ee7b84d MS |
1696 | else if (x_mode == VECIND) |
1697 | { | |
1698 | check_operand (operand + i, 0x7f, "@@"); | |
1699 | /* FIXME: approximating the effect of "B31" here... | |
1700 | This is very hackish, and ought to be done a better way. */ | |
1701 | operand[i].exp.X_add_number |= 0x80; | |
1702 | fix_new_exp (frag_now, | |
1703 | output - frag_now->fr_literal + 1, | |
1704 | 1, | |
1705 | &operand[i].exp, | |
1706 | 0, | |
1707 | R_MEM_INDIRECT); | |
1708 | } | |
252b5132 RH |
1709 | else if (x & ABSJMP) |
1710 | { | |
3c1ba8a3 | 1711 | int where = 0; |
7ee7b84d | 1712 | bfd_reloc_code_real_type reloc_type = R_JMPL1; |
3c1ba8a3 JL |
1713 | |
1714 | #ifdef OBJ_ELF | |
1715 | /* To be compatible with the proposed H8 ELF format, we | |
1716 | want the relocation's offset to point to the first byte | |
1717 | that will be modified, not to the start of the instruction. */ | |
7ee7b84d MS |
1718 | |
1719 | if ((operand->mode & SIZE) == L_32) | |
1720 | { | |
1721 | where = 2; | |
1722 | reloc_type = R_RELLONG; | |
1723 | } | |
1724 | else | |
1725 | where = 1; | |
3c1ba8a3 | 1726 | #endif |
de342d07 | 1727 | |
70d6ecf3 | 1728 | /* This jmp may be a jump or a branch. */ |
252b5132 | 1729 | |
7ee7b84d MS |
1730 | check_operand (operand + i, |
1731 | SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, | |
1732 | "@"); | |
3048287a | 1733 | |
252b5132 | 1734 | if (operand[i].exp.X_add_number & 1) |
3048287a NC |
1735 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1736 | (unsigned long) operand->exp.X_add_number); | |
1737 | ||
252b5132 | 1738 | if (!Hmode) |
70d6ecf3 | 1739 | operand[i].exp.X_add_number = |
4132022d | 1740 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
252b5132 | 1741 | fix_new_exp (frag_now, |
3c1ba8a3 | 1742 | output - frag_now->fr_literal + where, |
252b5132 RH |
1743 | 4, |
1744 | &operand[i].exp, | |
1745 | 0, | |
7ee7b84d | 1746 | reloc_type); |
252b5132 RH |
1747 | } |
1748 | } | |
252b5132 RH |
1749 | } |
1750 | ||
70d6ecf3 AM |
1751 | /* Try to give an intelligent error message for common and simple to |
1752 | detect errors. */ | |
3048287a | 1753 | |
252b5132 | 1754 | static void |
a720f7bc KD |
1755 | clever_message (instruction, operand) |
1756 | const struct h8_instruction *instruction; | |
252b5132 RH |
1757 | struct h8_op *operand; |
1758 | { | |
70d6ecf3 | 1759 | /* Find out if there was more than one possible opcode. */ |
252b5132 | 1760 | |
a720f7bc | 1761 | if ((instruction + 1)->idx != instruction->idx) |
252b5132 | 1762 | { |
3048287a | 1763 | int argn; |
252b5132 | 1764 | |
70d6ecf3 AM |
1765 | /* Only one opcode of this flavour, try to guess which operand |
1766 | didn't match. */ | |
a720f7bc | 1767 | for (argn = 0; argn < instruction->noperands; argn++) |
252b5132 | 1768 | { |
a720f7bc | 1769 | switch (instruction->opcode->args.nib[argn]) |
252b5132 RH |
1770 | { |
1771 | case RD16: | |
1772 | if (operand[argn].mode != RD16) | |
1773 | { | |
1774 | as_bad (_("destination operand must be 16 bit register")); | |
1775 | return; | |
1776 | ||
1777 | } | |
1778 | break; | |
1779 | ||
1780 | case RS8: | |
252b5132 RH |
1781 | if (operand[argn].mode != RS8) |
1782 | { | |
1783 | as_bad (_("source operand must be 8 bit register")); | |
1784 | return; | |
1785 | } | |
1786 | break; | |
1787 | ||
1788 | case ABS16DST: | |
1789 | if (operand[argn].mode != ABS16DST) | |
1790 | { | |
1791 | as_bad (_("destination operand must be 16bit absolute address")); | |
1792 | return; | |
1793 | } | |
1794 | break; | |
1795 | case RD8: | |
1796 | if (operand[argn].mode != RD8) | |
1797 | { | |
1798 | as_bad (_("destination operand must be 8 bit register")); | |
1799 | return; | |
1800 | } | |
1801 | break; | |
1802 | ||
252b5132 RH |
1803 | case ABS16SRC: |
1804 | if (operand[argn].mode != ABS16SRC) | |
1805 | { | |
1806 | as_bad (_("source operand must be 16bit absolute address")); | |
1807 | return; | |
1808 | } | |
1809 | break; | |
1810 | ||
1811 | } | |
1812 | } | |
1813 | } | |
1814 | as_bad (_("invalid operands")); | |
1815 | } | |
1816 | ||
d4ea8842 | 1817 | |
1b680e4f RS |
1818 | /* If OPERAND is part of an address, adjust its size and value given |
1819 | that it addresses SIZE bytes. | |
d4ea8842 | 1820 | |
1b680e4f RS |
1821 | This function decides how big non-immediate constants are when no |
1822 | size was explicitly given. It also scales down the assembly-level | |
d4ea8842 MS |
1823 | displacement in an @(d:2,ERn) operand. */ |
1824 | ||
1825 | static void | |
1826 | fix_operand_size (operand, size) | |
1827 | struct h8_op *operand; | |
1828 | int size; | |
1829 | { | |
1b680e4f | 1830 | if (SXmode && (operand->mode & MODE) == DISP) |
d4ea8842 MS |
1831 | { |
1832 | /* If the user didn't specify an operand width, see if we | |
1833 | can use @(d:2,ERn). */ | |
1b680e4f RS |
1834 | if ((operand->mode & SIZE) == 0 |
1835 | && operand->exp.X_add_symbol == 0 | |
1836 | && operand->exp.X_op_symbol == 0 | |
d4ea8842 MS |
1837 | && (operand->exp.X_add_number == size |
1838 | || operand->exp.X_add_number == size * 2 | |
1839 | || operand->exp.X_add_number == size * 3)) | |
1840 | operand->mode |= L_2; | |
1841 | ||
1842 | /* Scale down the displacement in an @(d:2,ERn) operand. | |
1843 | X_add_number then contains the desired field value. */ | |
1844 | if ((operand->mode & SIZE) == L_2) | |
1845 | { | |
1846 | if (operand->exp.X_add_number % size != 0) | |
1847 | as_warn (_("operand/size mis-match")); | |
1848 | operand->exp.X_add_number /= size; | |
1849 | } | |
1850 | } | |
1851 | ||
d4ea8842 MS |
1852 | if ((operand->mode & SIZE) == 0) |
1853 | switch (operand->mode & MODE) | |
1854 | { | |
1855 | case DISP: | |
1856 | case INDEXB: | |
1857 | case INDEXW: | |
1858 | case INDEXL: | |
1859 | case ABS: | |
1b680e4f RS |
1860 | /* Pick a 24-bit address unless we know that a 16-bit address |
1861 | is safe. get_specific() will relax L_24 into L_32 where | |
1862 | necessary. */ | |
1863 | if (Hmode | |
d4e2de6b | 1864 | && !Nmode |
1b680e4f RS |
1865 | && (operand->exp.X_add_number < -32768 |
1866 | || operand->exp.X_add_number > 32767 | |
1867 | || operand->exp.X_add_symbol != 0 | |
1868 | || operand->exp.X_op_symbol != 0)) | |
1869 | operand->mode |= L_24; | |
1870 | else | |
1871 | operand->mode |= L_16; | |
1872 | break; | |
1873 | ||
1874 | case PCREL: | |
1875 | /* This condition is long standing, though somewhat suspect. */ | |
1876 | if (operand->exp.X_add_number > -128 | |
1877 | && operand->exp.X_add_number < 127) | |
1878 | operand->mode |= L_8; | |
1879 | else | |
1880 | operand->mode |= L_16; | |
d4ea8842 MS |
1881 | break; |
1882 | } | |
1883 | } | |
1884 | ||
1885 | ||
70d6ecf3 AM |
1886 | /* This is the guts of the machine-dependent assembler. STR points to |
1887 | a machine dependent instruction. This function is supposed to emit | |
1888 | the frags/bytes it assembles. */ | |
3048287a | 1889 | |
252b5132 RH |
1890 | void |
1891 | md_assemble (str) | |
1892 | char *str; | |
1893 | { | |
1894 | char *op_start; | |
1895 | char *op_end; | |
7ee7b84d | 1896 | struct h8_op operand[3]; |
a720f7bc KD |
1897 | const struct h8_instruction *instruction; |
1898 | const struct h8_instruction *prev_instruction; | |
252b5132 RH |
1899 | |
1900 | char *dot = 0; | |
0c0b9be0 | 1901 | char *slash = 0; |
252b5132 | 1902 | char c; |
7ee7b84d | 1903 | int size, i; |
252b5132 | 1904 | |
70d6ecf3 | 1905 | /* Drop leading whitespace. */ |
252b5132 RH |
1906 | while (*str == ' ') |
1907 | str++; | |
1908 | ||
70d6ecf3 | 1909 | /* Find the op code end. */ |
252b5132 RH |
1910 | for (op_start = op_end = str; |
1911 | *op_end != 0 && *op_end != ' '; | |
1912 | op_end++) | |
1913 | { | |
1914 | if (*op_end == '.') | |
1915 | { | |
1916 | dot = op_end + 1; | |
1917 | *op_end = 0; | |
1918 | op_end += 2; | |
1919 | break; | |
1920 | } | |
0c0b9be0 AO |
1921 | else if (*op_end == '/' && ! slash) |
1922 | slash = op_end; | |
252b5132 RH |
1923 | } |
1924 | ||
252b5132 RH |
1925 | if (op_end == op_start) |
1926 | { | |
1927 | as_bad (_("can't find opcode ")); | |
1928 | } | |
1929 | c = *op_end; | |
1930 | ||
1931 | *op_end = 0; | |
1932 | ||
0c0b9be0 AO |
1933 | /* The assembler stops scanning the opcode at slashes, so it fails |
1934 | to make characters following them lower case. Fix them. */ | |
1935 | if (slash) | |
1936 | while (*++slash) | |
1937 | *slash = TOLOWER (*slash); | |
1938 | ||
a720f7bc KD |
1939 | instruction = (const struct h8_instruction *) |
1940 | hash_find (opcode_hash_control, op_start); | |
252b5132 | 1941 | |
a720f7bc | 1942 | if (instruction == NULL) |
252b5132 RH |
1943 | { |
1944 | as_bad (_("unknown opcode")); | |
1945 | return; | |
1946 | } | |
1947 | ||
70d6ecf3 | 1948 | /* We used to set input_line_pointer to the result of get_operands, |
252b5132 RH |
1949 | but that is wrong. Our caller assumes we don't change it. */ |
1950 | ||
7ee7b84d MS |
1951 | operand[0].mode = 0; |
1952 | operand[1].mode = 0; | |
1953 | operand[2].mode = 0; | |
1954 | ||
1955 | if (OP_KIND (instruction->opcode->how) == O_MOVAB | |
1956 | || OP_KIND (instruction->opcode->how) == O_MOVAW | |
1957 | || OP_KIND (instruction->opcode->how) == O_MOVAL) | |
1958 | get_mova_operands (op_end, operand); | |
1959 | else if (OP_KIND (instruction->opcode->how) == O_RTEL | |
1960 | || OP_KIND (instruction->opcode->how) == O_RTSL) | |
1961 | get_rtsl_operands (op_end, operand); | |
1962 | else | |
1963 | get_operands (instruction->noperands, op_end, operand); | |
1964 | ||
252b5132 | 1965 | *op_end = c; |
a720f7bc | 1966 | prev_instruction = instruction; |
252b5132 RH |
1967 | |
1968 | size = SN; | |
1969 | if (dot) | |
1970 | { | |
0c0b9be0 | 1971 | switch (TOLOWER (*dot)) |
252b5132 RH |
1972 | { |
1973 | case 'b': | |
1974 | size = SB; | |
1975 | break; | |
1976 | ||
1977 | case 'w': | |
1978 | size = SW; | |
1979 | break; | |
1980 | ||
1981 | case 'l': | |
1982 | size = SL; | |
1983 | break; | |
1984 | } | |
1985 | } | |
7ee7b84d MS |
1986 | if (OP_KIND (instruction->opcode->how) == O_MOVAB || |
1987 | OP_KIND (instruction->opcode->how) == O_MOVAW || | |
1988 | OP_KIND (instruction->opcode->how) == O_MOVAL) | |
252b5132 | 1989 | { |
d4ea8842 MS |
1990 | switch (operand[0].mode & MODE) |
1991 | { | |
7ee7b84d MS |
1992 | case INDEXB: |
1993 | default: | |
d4ea8842 | 1994 | fix_operand_size (&operand[1], 1); |
7ee7b84d MS |
1995 | break; |
1996 | case INDEXW: | |
d4ea8842 | 1997 | fix_operand_size (&operand[1], 2); |
7ee7b84d MS |
1998 | break; |
1999 | case INDEXL: | |
d4ea8842 | 2000 | fix_operand_size (&operand[1], 4); |
7ee7b84d | 2001 | break; |
252b5132 RH |
2002 | } |
2003 | } | |
7ee7b84d MS |
2004 | else |
2005 | { | |
d4ea8842 MS |
2006 | for (i = 0; i < 3 && operand[i].mode != 0; i++) |
2007 | switch (size) | |
2008 | { | |
7ee7b84d MS |
2009 | case SN: |
2010 | case SB: | |
2011 | default: | |
d4ea8842 | 2012 | fix_operand_size (&operand[i], 1); |
7ee7b84d MS |
2013 | break; |
2014 | case SW: | |
d4ea8842 | 2015 | fix_operand_size (&operand[i], 2); |
7ee7b84d MS |
2016 | break; |
2017 | case SL: | |
d4ea8842 | 2018 | fix_operand_size (&operand[i], 4); |
7ee7b84d MS |
2019 | break; |
2020 | } | |
2021 | } | |
252b5132 | 2022 | |
d4ea8842 MS |
2023 | instruction = get_specific (instruction, operand, size); |
2024 | ||
2025 | if (instruction == 0) | |
2026 | { | |
2027 | /* Couldn't find an opcode which matched the operands. */ | |
2028 | char *where = frag_more (2); | |
2029 | ||
2030 | where[0] = 0x0; | |
2031 | where[1] = 0x0; | |
2032 | clever_message (prev_instruction, operand); | |
2033 | ||
2034 | return; | |
2035 | } | |
2036 | ||
a720f7bc | 2037 | build_bytes (instruction, operand); |
2c8714f2 NC |
2038 | |
2039 | #ifdef BFD_ASSEMBLER | |
2040 | dwarf2_emit_insn (instruction->length); | |
2041 | #endif | |
252b5132 RH |
2042 | } |
2043 | ||
5facebfc | 2044 | #ifndef BFD_ASSEMBLER |
252b5132 RH |
2045 | void |
2046 | tc_crawl_symbol_chain (headers) | |
70d6ecf3 | 2047 | object_headers *headers ATTRIBUTE_UNUSED; |
252b5132 RH |
2048 | { |
2049 | printf (_("call to tc_crawl_symbol_chain \n")); | |
2050 | } | |
f333765f | 2051 | #endif |
252b5132 RH |
2052 | |
2053 | symbolS * | |
2054 | md_undefined_symbol (name) | |
dbbc7809 | 2055 | char *name ATTRIBUTE_UNUSED; |
252b5132 RH |
2056 | { |
2057 | return 0; | |
2058 | } | |
2059 | ||
5facebfc | 2060 | #ifndef BFD_ASSEMBLER |
252b5132 RH |
2061 | void |
2062 | tc_headers_hook (headers) | |
70d6ecf3 | 2063 | object_headers *headers ATTRIBUTE_UNUSED; |
252b5132 RH |
2064 | { |
2065 | printf (_("call to tc_headers_hook \n")); | |
2066 | } | |
f333765f | 2067 | #endif |
252b5132 RH |
2068 | |
2069 | /* Various routines to kill one day */ | |
2070 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
2071 | #define MAX_LITTLENUMS 6 | |
2072 | ||
70d6ecf3 AM |
2073 | /* Turn a string in input_line_pointer into a floating point constant |
2074 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
bc0d738a | 2075 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
70d6ecf3 | 2076 | returned, or NULL on OK. */ |
bc0d738a | 2077 | |
252b5132 RH |
2078 | char * |
2079 | md_atof (type, litP, sizeP) | |
2080 | char type; | |
2081 | char *litP; | |
2082 | int *sizeP; | |
2083 | { | |
2084 | int prec; | |
2085 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2086 | LITTLENUM_TYPE *wordP; | |
2087 | char *t; | |
252b5132 RH |
2088 | |
2089 | switch (type) | |
2090 | { | |
2091 | case 'f': | |
2092 | case 'F': | |
2093 | case 's': | |
2094 | case 'S': | |
2095 | prec = 2; | |
2096 | break; | |
2097 | ||
2098 | case 'd': | |
2099 | case 'D': | |
2100 | case 'r': | |
2101 | case 'R': | |
2102 | prec = 4; | |
2103 | break; | |
2104 | ||
2105 | case 'x': | |
2106 | case 'X': | |
2107 | prec = 6; | |
2108 | break; | |
2109 | ||
2110 | case 'p': | |
2111 | case 'P': | |
2112 | prec = 6; | |
2113 | break; | |
2114 | ||
2115 | default: | |
2116 | *sizeP = 0; | |
2117 | return _("Bad call to MD_ATOF()"); | |
2118 | } | |
2119 | t = atof_ieee (input_line_pointer, type, words); | |
2120 | if (t) | |
2121 | input_line_pointer = t; | |
2122 | ||
2123 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
2124 | for (wordP = words; prec--;) | |
2125 | { | |
2126 | md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); | |
2127 | litP += sizeof (LITTLENUM_TYPE); | |
2128 | } | |
2129 | return 0; | |
2130 | } | |
2131 | \f | |
5a38dc70 | 2132 | const char *md_shortopts = ""; |
252b5132 RH |
2133 | struct option md_longopts[] = { |
2134 | {NULL, no_argument, NULL, 0} | |
2135 | }; | |
70d6ecf3 AM |
2136 | |
2137 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
2138 | |
2139 | int | |
2140 | md_parse_option (c, arg) | |
dbbc7809 JL |
2141 | int c ATTRIBUTE_UNUSED; |
2142 | char *arg ATTRIBUTE_UNUSED; | |
252b5132 RH |
2143 | { |
2144 | return 0; | |
2145 | } | |
2146 | ||
2147 | void | |
2148 | md_show_usage (stream) | |
dbbc7809 | 2149 | FILE *stream ATTRIBUTE_UNUSED; |
252b5132 RH |
2150 | { |
2151 | } | |
2152 | \f | |
3048287a NC |
2153 | void tc_aout_fix_to_chars PARAMS ((void)); |
2154 | ||
252b5132 RH |
2155 | void |
2156 | tc_aout_fix_to_chars () | |
2157 | { | |
2158 | printf (_("call to tc_aout_fix_to_chars \n")); | |
2159 | abort (); | |
2160 | } | |
2161 | ||
2162 | void | |
2163 | md_convert_frag (headers, seg, fragP) | |
36ed2fff JL |
2164 | #ifdef BFD_ASSEMBLER |
2165 | bfd *headers ATTRIBUTE_UNUSED; | |
2166 | #else | |
dbbc7809 | 2167 | object_headers *headers ATTRIBUTE_UNUSED; |
36ed2fff | 2168 | #endif |
dbbc7809 JL |
2169 | segT seg ATTRIBUTE_UNUSED; |
2170 | fragS *fragP ATTRIBUTE_UNUSED; | |
252b5132 RH |
2171 | { |
2172 | printf (_("call to md_convert_frag \n")); | |
2173 | abort (); | |
2174 | } | |
2175 | ||
3c1ba8a3 JL |
2176 | #ifdef BFD_ASSEMBLER |
2177 | valueT | |
2178 | md_section_align (segment, size) | |
2179 | segT segment; | |
2180 | valueT size; | |
2181 | { | |
2182 | int align = bfd_get_section_alignment (stdoutput, segment); | |
2183 | return ((size + (1 << align) - 1) & (-1 << align)); | |
2184 | } | |
2185 | #else | |
70d6ecf3 | 2186 | valueT |
252b5132 RH |
2187 | md_section_align (seg, size) |
2188 | segT seg; | |
2189 | valueT size; | |
2190 | { | |
70d6ecf3 | 2191 | return ((size + (1 << section_alignment[(int) seg]) - 1) |
cc8a6dd0 | 2192 | & (-1 << section_alignment[(int) seg])); |
252b5132 | 2193 | } |
3c1ba8a3 JL |
2194 | #endif |
2195 | ||
252b5132 RH |
2196 | |
2197 | void | |
94f592af | 2198 | md_apply_fix3 (fixP, valP, seg) |
252b5132 | 2199 | fixS *fixP; |
94f592af NC |
2200 | valueT *valP; |
2201 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 RH |
2202 | { |
2203 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
a161fe53 | 2204 | long val = *valP; |
252b5132 RH |
2205 | |
2206 | switch (fixP->fx_size) | |
2207 | { | |
2208 | case 1: | |
2209 | *buf++ = val; | |
2210 | break; | |
2211 | case 2: | |
2212 | *buf++ = (val >> 8); | |
2213 | *buf++ = val; | |
2214 | break; | |
2215 | case 4: | |
2216 | *buf++ = (val >> 24); | |
2217 | *buf++ = (val >> 16); | |
2218 | *buf++ = (val >> 8); | |
2219 | *buf++ = val; | |
2220 | break; | |
2221 | default: | |
2222 | abort (); | |
2223 | } | |
94f592af NC |
2224 | |
2225 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) | |
2226 | fixP->fx_done = 1; | |
252b5132 RH |
2227 | } |
2228 | ||
2229 | int | |
2230 | md_estimate_size_before_relax (fragP, segment_type) | |
dbbc7809 JL |
2231 | register fragS *fragP ATTRIBUTE_UNUSED; |
2232 | register segT segment_type ATTRIBUTE_UNUSED; | |
252b5132 RH |
2233 | { |
2234 | printf (_("call tomd_estimate_size_before_relax \n")); | |
2235 | abort (); | |
2236 | } | |
2237 | ||
70d6ecf3 | 2238 | /* Put number into target byte order. */ |
252b5132 RH |
2239 | void |
2240 | md_number_to_chars (ptr, use, nbytes) | |
2241 | char *ptr; | |
2242 | valueT use; | |
2243 | int nbytes; | |
2244 | { | |
2245 | number_to_chars_bigendian (ptr, use, nbytes); | |
2246 | } | |
70d6ecf3 | 2247 | |
252b5132 RH |
2248 | long |
2249 | md_pcrel_from (fixP) | |
dbbc7809 | 2250 | fixS *fixP ATTRIBUTE_UNUSED; |
252b5132 RH |
2251 | { |
2252 | abort (); | |
2253 | } | |
2254 | ||
5facebfc | 2255 | #ifndef BFD_ASSEMBLER |
252b5132 RH |
2256 | void |
2257 | tc_reloc_mangle (fix_ptr, intr, base) | |
2258 | fixS *fix_ptr; | |
2259 | struct internal_reloc *intr; | |
2260 | bfd_vma base; | |
2261 | ||
2262 | { | |
2263 | symbolS *symbol_ptr; | |
2264 | ||
2265 | symbol_ptr = fix_ptr->fx_addsy; | |
2266 | ||
2267 | /* If this relocation is attached to a symbol then it's ok | |
70d6ecf3 | 2268 | to output it. */ |
252b5132 RH |
2269 | if (fix_ptr->fx_r_type == TC_CONS_RELOC) |
2270 | { | |
2271 | /* cons likes to create reloc32's whatever the size of the reloc.. | |
2272 | */ | |
2273 | switch (fix_ptr->fx_size) | |
2274 | { | |
2275 | case 4: | |
2276 | intr->r_type = R_RELLONG; | |
2277 | break; | |
2278 | case 2: | |
2279 | intr->r_type = R_RELWORD; | |
2280 | break; | |
2281 | case 1: | |
2282 | intr->r_type = R_RELBYTE; | |
2283 | break; | |
2284 | default: | |
2285 | abort (); | |
252b5132 | 2286 | } |
252b5132 RH |
2287 | } |
2288 | else | |
2289 | { | |
2290 | intr->r_type = fix_ptr->fx_r_type; | |
2291 | } | |
2292 | ||
2293 | intr->r_vaddr = fix_ptr->fx_frag->fr_address + fix_ptr->fx_where + base; | |
2294 | intr->r_offset = fix_ptr->fx_offset; | |
2295 | ||
2296 | if (symbol_ptr) | |
2297 | { | |
2298 | if (symbol_ptr->sy_number != -1) | |
2299 | intr->r_symndx = symbol_ptr->sy_number; | |
2300 | else | |
2301 | { | |
2302 | symbolS *segsym; | |
2303 | ||
2304 | /* This case arises when a reference is made to `.'. */ | |
2305 | segsym = seg_info (S_GET_SEGMENT (symbol_ptr))->dot; | |
2306 | if (segsym == NULL) | |
2307 | intr->r_symndx = -1; | |
2308 | else | |
2309 | { | |
2310 | intr->r_symndx = segsym->sy_number; | |
2311 | intr->r_offset += S_GET_VALUE (symbol_ptr); | |
2312 | } | |
2313 | } | |
2314 | } | |
2315 | else | |
2316 | intr->r_symndx = -1; | |
252b5132 | 2317 | } |
5facebfc | 2318 | #else /* BFD_ASSEMBLER */ |
f333765f JL |
2319 | arelent * |
2320 | tc_gen_reloc (section, fixp) | |
2321 | asection *section ATTRIBUTE_UNUSED; | |
2322 | fixS *fixp; | |
2323 | { | |
2324 | arelent *rel; | |
2325 | bfd_reloc_code_real_type r_type; | |
2326 | ||
de342d07 JL |
2327 | if (fixp->fx_addsy && fixp->fx_subsy) |
2328 | { | |
2329 | if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) | |
2330 | || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) | |
2331 | { | |
2332 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2333 | "Difference of symbols in different sections is not supported"); | |
2334 | return NULL; | |
2335 | } | |
2336 | } | |
2337 | ||
f333765f JL |
2338 | rel = (arelent *) xmalloc (sizeof (arelent)); |
2339 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2340 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
2341 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2342 | rel->addend = fixp->fx_offset; | |
2343 | ||
2344 | r_type = fixp->fx_r_type; | |
2345 | ||
2346 | #define DEBUG 0 | |
2347 | #if DEBUG | |
2348 | fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); | |
2349 | fflush(stderr); | |
2350 | #endif | |
2351 | rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); | |
2352 | if (rel->howto == NULL) | |
2353 | { | |
2354 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2355 | _("Cannot represent relocation type %s"), | |
2356 | bfd_get_reloc_code_name (r_type)); | |
2357 | return NULL; | |
2358 | } | |
2359 | ||
2360 | return rel; | |
2361 | } | |
2362 | #endif |