opcodes/
[deliverable/binutils-gdb.git] / gas / config / tc-h8300.c
CommitLineData
c2dcd04e 1/* tc-h8300.c -- Assemble code for the Renesas H8/300
cc8a6dd0 2 Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
ec2655a6 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132
RH
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
ec2655a6 9 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
bc0d738a 22/* Written By Steve Chamberlain <sac@cygnus.com>. */
252b5132 23
252b5132
RH
24#include "as.h"
25#include "subsegs.h"
2c8714f2 26#include "dwarf2dbg.h"
2c8714f2 27
252b5132
RH
28#define DEFINE_TABLE
29#define h8_opcodes ops
30#include "opcode/h8300.h"
3882b010 31#include "safe-ctype.h"
252b5132 32
7e0de7bf
JL
33#ifdef OBJ_ELF
34#include "elf/h8.h"
7e0de7bf
JL
35#endif
36
63a0b638 37const char comment_chars[] = ";";
252b5132 38const char line_comment_chars[] = "#";
63a0b638 39const char line_separator_chars[] = "";
252b5132 40
600e9c99
KH
41static void sbranch (int);
42static void h8300hmode (int);
43static void h8300smode (int);
44static void h8300hnmode (int);
45static void h8300snmode (int);
46static void h8300sxmode (int);
47static void h8300sxnmode (int);
b54a3392 48static void pint (int);
252b5132 49
66faad26
KH
50int Hmode;
51int Smode;
52int Nmode;
53int SXmode;
3048287a 54
d4e2de6b 55#define PSIZE (Hmode && !Nmode ? L_32 : L_16)
3048287a 56
600e9c99 57static int bsize = L_8; /* Default branch displacement. */
252b5132 58
a720f7bc
KD
59struct h8_instruction
60{
61 int length;
62 int noperands;
63 int idx;
64 int size;
65 const struct h8_opcode *opcode;
66};
67
600e9c99 68static struct h8_instruction *h8_instructions;
a720f7bc 69
600e9c99 70static void
b54a3392 71h8300hmode (int arg ATTRIBUTE_UNUSED)
252b5132
RH
72{
73 Hmode = 1;
74 Smode = 0;
83e20b45
JL
75 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h))
76 as_warn (_("could not set architecture and machine"));
252b5132
RH
77}
78
600e9c99 79static void
b54a3392 80h8300smode (int arg ATTRIBUTE_UNUSED)
252b5132
RH
81{
82 Smode = 1;
83 Hmode = 1;
83e20b45
JL
84 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s))
85 as_warn (_("could not set architecture and machine"));
252b5132 86}
70d6ecf3 87
600e9c99 88static void
b54a3392 89h8300hnmode (int arg ATTRIBUTE_UNUSED)
8d9cd6b1
NC
90{
91 Hmode = 1;
92 Smode = 0;
93 Nmode = 1;
8d9cd6b1
NC
94 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn))
95 as_warn (_("could not set architecture and machine"));
8d9cd6b1
NC
96}
97
600e9c99 98static void
b54a3392 99h8300snmode (int arg ATTRIBUTE_UNUSED)
8d9cd6b1
NC
100{
101 Smode = 1;
102 Hmode = 1;
103 Nmode = 1;
8d9cd6b1
NC
104 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn))
105 as_warn (_("could not set architecture and machine"));
8d9cd6b1
NC
106}
107
600e9c99 108static void
b54a3392 109h8300sxmode (int arg ATTRIBUTE_UNUSED)
7ee7b84d
MS
110{
111 Smode = 1;
112 Hmode = 1;
113 SXmode = 1;
7ee7b84d
MS
114 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx))
115 as_warn (_("could not set architecture and machine"));
7ee7b84d
MS
116}
117
600e9c99 118static void
b54a3392 119h8300sxnmode (int arg ATTRIBUTE_UNUSED)
f4984206
RS
120{
121 Smode = 1;
122 Hmode = 1;
123 SXmode = 1;
124 Nmode = 1;
f4984206
RS
125 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn))
126 as_warn (_("could not set architecture and machine"));
f4984206
RS
127}
128
600e9c99 129static void
b54a3392 130sbranch (int size)
252b5132
RH
131{
132 bsize = size;
133}
134
70d6ecf3 135static void
b54a3392 136pint (int arg ATTRIBUTE_UNUSED)
252b5132
RH
137{
138 cons (Hmode ? 4 : 2);
139}
140
3048287a
NC
141/* This table describes all the machine specific pseudo-ops the assembler
142 has to support. The fields are:
143 pseudo-op name without dot
144 function to call to execute this pseudo-op
145 Integer arg to pass to the function. */
146
252b5132
RH
147const pseudo_typeS md_pseudo_table[] =
148{
7ee7b84d 149 {"h8300h", h8300hmode, 0},
8d9cd6b1 150 {"h8300hn", h8300hnmode, 0},
7ee7b84d 151 {"h8300s", h8300smode, 0},
8d9cd6b1 152 {"h8300sn", h8300snmode, 0},
7ee7b84d 153 {"h8300sx", h8300sxmode, 0},
f4984206 154 {"h8300sxn", h8300sxnmode, 0},
252b5132
RH
155 {"sbranch", sbranch, L_8},
156 {"lbranch", sbranch, L_16},
157
158 {"int", pint, 0},
159 {"data.b", cons, 1},
160 {"data.w", cons, 2},
161 {"data.l", cons, 4},
162 {"form", listing_psize, 0},
163 {"heading", listing_title, 0},
7ee7b84d
MS
164 {"import", s_ignore, 0},
165 {"page", listing_eject, 0},
252b5132
RH
166 {"program", s_ignore, 0},
167 {0, 0, 0}
168};
169
252b5132
RH
170const char EXP_CHARS[] = "eE";
171
3048287a
NC
172/* Chars that mean this number is a floating point constant
173 As in 0f12.456
174 or 0d1.2345e12. */
252b5132
RH
175const char FLT_CHARS[] = "rRsSfFdDxXpP";
176
3048287a 177static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */
252b5132 178
70d6ecf3
AM
179/* This function is called once, at assembler startup time. This
180 should set up all the tables, etc. that the MD part of the assembler
181 needs. */
3048287a 182
252b5132 183void
b54a3392 184md_begin (void)
252b5132 185{
a720f7bc 186 unsigned int nopcodes;
7ee7b84d 187 struct h8_opcode *p, *p1;
a720f7bc 188 struct h8_instruction *pi;
252b5132
RH
189 char prev_buffer[100];
190 int idx = 0;
191
83e20b45
JL
192 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300))
193 as_warn (_("could not set architecture and machine"));
83e20b45 194
252b5132
RH
195 opcode_hash_control = hash_new ();
196 prev_buffer[0] = 0;
197
a720f7bc
KD
198 nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode);
199
200 h8_instructions = (struct h8_instruction *)
201 xmalloc (nopcodes * sizeof (struct h8_instruction));
202
7ee7b84d
MS
203 pi = h8_instructions;
204 p1 = h8_opcodes;
205 /* We do a minimum amount of sorting on the opcode table; this is to
206 make it easy to describe the mova instructions without unnecessary
207 code duplication.
208 Sorting only takes place inside blocks of instructions of the form
209 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */
210 while (p1)
252b5132 211 {
7ee7b84d
MS
212 struct h8_opcode *first_skipped = 0;
213 int len, cmplen = 0;
214 char *src = p1->name;
215 char *dst, *buffer;
252b5132 216
7ee7b84d
MS
217 if (p1->name == 0)
218 break;
219 /* Strip off any . part when inserting the opcode and only enter
220 unique codes into the hash table. */
221 dst = buffer = malloc (strlen (src) + 1);
252b5132
RH
222 while (*src)
223 {
224 if (*src == '.')
225 {
226 src++;
252b5132
RH
227 break;
228 }
7ee7b84d
MS
229 if (*src == '/')
230 cmplen = src - p1->name + 1;
252b5132
RH
231 *dst++ = *src++;
232 }
7ee7b84d
MS
233 *dst = 0;
234 len = dst - buffer;
235 if (cmplen == 0)
236 cmplen = len;
237 hash_insert (opcode_hash_control, buffer, (char *) pi);
238 strcpy (prev_buffer, buffer);
239 idx++;
240
241 for (p = p1; p->name; p++)
252b5132 242 {
7ee7b84d
MS
243 /* A negative TIME is used to indicate that we've added this opcode
244 already. */
245 if (p->time == -1)
246 continue;
247 if (strncmp (p->name, buffer, cmplen) != 0
248 || (p->name[cmplen] != '\0' && p->name[cmplen] != '.'
249 && p->name[cmplen - 1] != '/'))
250 {
251 if (first_skipped == 0)
252 first_skipped = p;
253 break;
254 }
255 if (strncmp (p->name, buffer, len) != 0)
256 {
257 if (first_skipped == 0)
258 first_skipped = p;
259 continue;
260 }
261
262 p->time = -1;
263 pi->size = p->name[len] == '.' ? p->name[len + 1] : 0;
264 pi->idx = idx;
252b5132 265
7ee7b84d
MS
266 /* Find the number of operands. */
267 pi->noperands = 0;
268 while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E)
269 pi->noperands++;
70d6ecf3 270
7ee7b84d
MS
271 /* Find the length of the opcode in bytes. */
272 pi->length = 0;
273 while (p->data.nib[pi->length * 2] != (op_type) E)
274 pi->length++;
a720f7bc 275
7ee7b84d
MS
276 pi->opcode = p;
277 pi++;
278 }
279 p1 = first_skipped;
252b5132
RH
280 }
281
a720f7bc
KD
282 /* Add entry for the NULL vector terminator. */
283 pi->length = 0;
284 pi->noperands = 0;
285 pi->idx = 0;
286 pi->size = 0;
7ee7b84d 287 pi->opcode = 0;
a720f7bc 288
252b5132
RH
289 linkrelax = 1;
290}
291
252b5132
RH
292struct h8_op
293{
294 op_type mode;
295 unsigned reg;
296 expressionS exp;
297};
298
b54a3392
KH
299static void clever_message (const struct h8_instruction *, struct h8_op *);
300static void fix_operand_size (struct h8_op *, int);
301static void build_bytes (const struct h8_instruction *, struct h8_op *);
302static void do_a_fix_imm (int, int, struct h8_op *, int);
303static void check_operand (struct h8_op *, unsigned int, char *);
304static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ;
305static char *get_operands (unsigned, char *, struct h8_op *);
306static void get_operand (char **, struct h8_op *, int);
307static int parse_reg (char *, op_type *, unsigned *, int);
308static char *skip_colonthing (char *, int *);
309static char *parse_exp (char *, struct h8_op *);
310
311static int constant_fits_width_p (struct h8_op *, unsigned int);
312static int constant_fits_size_p (struct h8_op *, int, int);
7ee7b84d 313
252b5132
RH
314/*
315 parse operands
316 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp
317 r0l,r0h,..r7l,r7h
318 @WREG
319 @WREG+
320 @-WREG
321 #const
322 ccr
323*/
324
bc0d738a
NC
325/* Try to parse a reg name. Return the number of chars consumed. */
326
40f09f82 327static int
b54a3392 328parse_reg (char *src, op_type *mode, unsigned int *reg, int direction)
252b5132
RH
329{
330 char *end;
331 int len;
332
70d6ecf3 333 /* Cribbed from get_symbol_end. */
252b5132
RH
334 if (!is_name_beginner (*src) || *src == '\001')
335 return 0;
70d6ecf3 336 end = src + 1;
7ee7b84d 337 while ((is_part_of_name (*end) && *end != '.') || *end == '\001')
252b5132
RH
338 end++;
339 len = end - src;
340
7ee7b84d 341 if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p')
252b5132
RH
342 {
343 *mode = PSIZE | REG | direction;
344 *reg = 7;
345 return len;
346 }
7ee7b84d
MS
347 if (len == 3 &&
348 TOLOWER (src[0]) == 'c' &&
349 TOLOWER (src[1]) == 'c' &&
350 TOLOWER (src[2]) == 'r')
252b5132
RH
351 {
352 *mode = CCR;
353 *reg = 0;
354 return len;
355 }
7ee7b84d
MS
356 if (len == 3 &&
357 TOLOWER (src[0]) == 'e' &&
358 TOLOWER (src[1]) == 'x' &&
359 TOLOWER (src[2]) == 'r')
252b5132
RH
360 {
361 *mode = EXR;
7ee7b84d
MS
362 *reg = 1;
363 return len;
364 }
365 if (len == 3 &&
366 TOLOWER (src[0]) == 'v' &&
367 TOLOWER (src[1]) == 'b' &&
368 TOLOWER (src[2]) == 'r')
369 {
370 *mode = VBR;
371 *reg = 6;
372 return len;
373 }
374 if (len == 3 &&
375 TOLOWER (src[0]) == 's' &&
376 TOLOWER (src[1]) == 'b' &&
377 TOLOWER (src[2]) == 'r')
378 {
379 *mode = SBR;
380 *reg = 7;
252b5132
RH
381 return len;
382 }
7ee7b84d 383 if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p')
252b5132
RH
384 {
385 *mode = PSIZE | REG | direction;
386 *reg = 6;
387 return len;
388 }
7ee7b84d
MS
389 if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' &&
390 src[2] >= '0' && src[2] <= '7')
252b5132
RH
391 {
392 *mode = L_32 | REG | direction;
393 *reg = src[2] - '0';
394 if (!Hmode)
395 as_warn (_("Reg not valid for H8/300"));
396 return len;
397 }
7ee7b84d 398 if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7')
252b5132
RH
399 {
400 *mode = L_16 | REG | direction;
401 *reg = src[1] - '0' + 8;
402 if (!Hmode)
403 as_warn (_("Reg not valid for H8/300"));
404 return len;
405 }
406
7ee7b84d 407 if (TOLOWER (src[0]) == 'r')
252b5132
RH
408 {
409 if (src[1] >= '0' && src[1] <= '7')
410 {
7ee7b84d 411 if (len == 3 && TOLOWER (src[2]) == 'l')
252b5132
RH
412 {
413 *mode = L_8 | REG | direction;
414 *reg = (src[1] - '0') + 8;
415 return len;
416 }
7ee7b84d 417 if (len == 3 && TOLOWER (src[2]) == 'h')
252b5132
RH
418 {
419 *mode = L_8 | REG | direction;
420 *reg = (src[1] - '0');
421 return len;
422 }
423 if (len == 2)
424 {
425 *mode = L_16 | REG | direction;
426 *reg = (src[1] - '0');
427 return len;
428 }
429 }
430 }
431
432 return 0;
433}
434
1b680e4f
RS
435
436/* Parse an immediate or address-related constant and store it in OP.
437 If the user also specifies the operand's size, store that size
438 in OP->MODE, otherwise leave it for later code to decide. */
439
40f09f82 440static char *
b54a3392 441parse_exp (char *src, struct h8_op *op)
252b5132 442{
1b680e4f 443 char *save;
252b5132 444
1b680e4f
RS
445 save = input_line_pointer;
446 input_line_pointer = src;
447 expression (&op->exp);
448 if (op->exp.X_op == O_absent)
252b5132 449 as_bad (_("missing operand"));
1b680e4f 450 src = input_line_pointer;
252b5132 451 input_line_pointer = save;
1b680e4f
RS
452
453 return skip_colonthing (src, &op->mode);
252b5132
RH
454}
455
1b680e4f
RS
456
457/* If SRC starts with an explicit operand size, skip it and store the size
458 in *MODE. Leave *MODE unchanged otherwise. */
459
252b5132 460static char *
b54a3392 461skip_colonthing (char *src, int *mode)
252b5132 462{
1b680e4f 463 if (*src == ':')
252b5132 464 {
1b680e4f 465 src++;
252b5132 466 *mode &= ~SIZE;
1b680e4f 467 if (src[0] == '8' && !ISDIGIT (src[1]))
7ee7b84d 468 *mode |= L_8;
1b680e4f 469 else if (src[0] == '2' && !ISDIGIT (src[1]))
7ee7b84d 470 *mode |= L_2;
1b680e4f 471 else if (src[0] == '3' && !ISDIGIT (src[1]))
7ee7b84d 472 *mode |= L_3;
1b680e4f 473 else if (src[0] == '4' && !ISDIGIT (src[1]))
7ee7b84d 474 *mode |= L_4;
1b680e4f 475 else if (src[0] == '5' && !ISDIGIT (src[1]))
7ee7b84d 476 *mode |= L_5;
1b680e4f 477 else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2]))
7ee7b84d 478 *mode |= L_24;
1b680e4f 479 else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2]))
7ee7b84d 480 *mode |= L_32;
1b680e4f 481 else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2]))
7ee7b84d 482 *mode |= L_16;
252b5132 483 else
7ee7b84d
MS
484 as_bad (_("invalid operand size requested"));
485
1b680e4f
RS
486 while (ISDIGIT (*src))
487 src++;
252b5132 488 }
1b680e4f 489 return src;
252b5132
RH
490}
491
492/* The many forms of operand:
493
494 Rn Register direct
495 @Rn Register indirect
496 @(exp[:16], Rn) Register indirect with displacement
497 @Rn+
498 @-Rn
70d6ecf3
AM
499 @aa:8 absolute 8 bit
500 @aa:16 absolute 16 bit
252b5132
RH
501 @aa absolute 16 bit
502
503 #xx[:size] immediate data
70d6ecf3 504 @(exp:[8], pc) pc rel
3048287a 505 @@aa[:8] memory indirect. */
252b5132 506
7ee7b84d 507static int
b54a3392 508constant_fits_width_p (struct h8_op *operand, unsigned int width)
7ee7b84d
MS
509{
510 return ((operand->exp.X_add_number & ~width) == 0
511 || (operand->exp.X_add_number | width) == (unsigned)(~0));
512}
513
514static int
b54a3392 515constant_fits_size_p (struct h8_op *operand, int size, int no_symbols)
7ee7b84d
MS
516{
517 offsetT num = operand->exp.X_add_number;
518 if (no_symbols
519 && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0))
520 return 0;
521 switch (size)
522 {
523 case L_2:
524 return (num & ~3) == 0;
525 case L_3:
526 return (num & ~7) == 0;
527 case L_3NZ:
528 return num >= 1 && num < 8;
529 case L_4:
530 return (num & ~15) == 0;
531 case L_5:
532 return num >= 1 && num < 32;
533 case L_8:
534 return (num & ~0xFF) == 0 || ((unsigned)num | 0x7F) == ~0u;
535 case L_8U:
536 return (num & ~0xFF) == 0;
537 case L_16:
538 return (num & ~0xFFFF) == 0 || ((unsigned)num | 0x7FFF) == ~0u;
539 case L_16U:
540 return (num & ~0xFFFF) == 0;
541 case L_32:
542 return 1;
543 default:
544 abort ();
545 }
546}
547
252b5132 548static void
b54a3392 549get_operand (char **ptr, struct h8_op *op, int direction)
252b5132
RH
550{
551 char *src = *ptr;
552 op_type mode;
553 unsigned int num;
554 unsigned int len;
555
7ee7b84d 556 op->mode = 0;
252b5132 557
3048287a
NC
558 /* Check for '(' and ')' for instructions ldm and stm. */
559 if (src[0] == '(' && src[8] == ')')
560 ++ src;
561
252b5132
RH
562 /* Gross. Gross. ldm and stm have a format not easily handled
563 by get_operand. We deal with it explicitly here. */
7ee7b84d
MS
564 if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' &&
565 ISDIGIT (src[2]) && src[3] == '-' &&
566 TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6]))
252b5132
RH
567 {
568 int low, high;
569
570 low = src[2] - '0';
571 high = src[6] - '0';
572
4892e510
NC
573 /* Check register pair's validity as per tech note TN-H8*-193A/E
574 from Renesas for H8S and H8SX hardware manual. */
575 if ( !(low == 0 && (high == 1 || high == 2 || high == 3))
576 && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode)
577 && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode)))
578 && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode)
579 && !(low == 4 && (high == 5 || high == 6))
b4f16abb 580 && !(low == 4 && high == 7 && SXmode)
4892e510
NC
581 && !(low == 5 && (high == 6 || high == 7) && SXmode)
582 && !(low == 6 && high == 7 && SXmode))
252b5132
RH
583 as_bad (_("Invalid register list for ldm/stm\n"));
584
252b5132
RH
585 /* Even sicker. We encode two registers into op->reg. One
586 for the low register to save, the other for the high
587 register to save; we also set the high bit in op->reg
588 so we know this is "very special". */
589 op->reg = 0x80000000 | (high << 8) | low;
590 op->mode = REG;
3048287a
NC
591 if (src[7] == ')')
592 *ptr = src + 8;
593 else
594 *ptr = src + 7;
252b5132
RH
595 return;
596 }
597
598 len = parse_reg (src, &op->mode, &op->reg, direction);
599 if (len)
600 {
7ee7b84d
MS
601 src += len;
602 if (*src == '.')
603 {
604 int size = op->mode & SIZE;
605 switch (src[1])
606 {
607 case 'l': case 'L':
608 if (size != L_32)
609 as_warn (_("mismatch between register and suffix"));
610 op->mode = (op->mode & ~MODE) | LOWREG;
611 break;
612 case 'w': case 'W':
613 if (size != L_32 && size != L_16)
614 as_warn (_("mismatch between register and suffix"));
615 op->mode = (op->mode & ~MODE) | LOWREG;
616 op->mode = (op->mode & ~SIZE) | L_16;
617 break;
618 case 'b': case 'B':
619 op->mode = (op->mode & ~MODE) | LOWREG;
620 if (size != L_32 && size != L_8)
621 as_warn (_("mismatch between register and suffix"));
622 op->mode = (op->mode & ~MODE) | LOWREG;
623 op->mode = (op->mode & ~SIZE) | L_8;
624 break;
625 default:
626 as_warn ("invalid suffix after register.");
627 break;
628 }
629 src += 2;
630 }
631 *ptr = src;
252b5132
RH
632 return;
633 }
634
635 if (*src == '@')
636 {
637 src++;
638 if (*src == '@')
639 {
1b680e4f 640 *ptr = parse_exp (src + 1, op);
7ee7b84d
MS
641 if (op->exp.X_add_number >= 0x100)
642 {
d4e2de6b 643 int divisor = 1;
7ee7b84d
MS
644
645 op->mode = VECIND;
646 /* FIXME : 2? or 4? */
647 if (op->exp.X_add_number >= 0x400)
648 as_bad (_("address too high for vector table jmp/jsr"));
649 else if (op->exp.X_add_number >= 0x200)
650 divisor = 4;
651 else
652 divisor = 2;
653
654 op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80;
655 }
656 else
657 op->mode = MEMIND;
252b5132 658 return;
252b5132
RH
659 }
660
7ee7b84d 661 if (*src == '-' || *src == '+')
252b5132 662 {
1b680e4f 663 len = parse_reg (src + 1, &mode, &num, direction);
252b5132
RH
664 if (len == 0)
665 {
70d6ecf3 666 /* Oops, not a reg after all, must be ordinary exp. */
1b680e4f
RS
667 op->mode = ABS | direction;
668 *ptr = parse_exp (src, op);
252b5132 669 return;
252b5132
RH
670 }
671
d4e2de6b
NC
672 if (((mode & SIZE) != PSIZE)
673 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
674 && (!Nmode || ((mode & SIZE) != L_32)))
252b5132 675 as_bad (_("Wrong size pointer register for architecture."));
1b680e4f
RS
676
677 op->mode = src[0] == '-' ? RDPREDEC : RDPREINC;
252b5132 678 op->reg = num;
1b680e4f 679 *ptr = src + 1 + len;
252b5132
RH
680 return;
681 }
682 if (*src == '(')
683 {
252b5132
RH
684 src++;
685
7ee7b84d
MS
686 /* See if this is @(ERn.x, PC). */
687 len = parse_reg (src, &mode, &op->reg, direction);
688 if (len != 0 && (mode & MODE) == REG && src[len] == '.')
689 {
690 switch (TOLOWER (src[len + 1]))
691 {
692 case 'b':
693 mode = PCIDXB | direction;
694 break;
695 case 'w':
696 mode = PCIDXW | direction;
697 break;
698 case 'l':
699 mode = PCIDXL | direction;
700 break;
701 default:
702 mode = 0;
703 break;
704 }
705 if (mode
706 && src[len + 2] == ','
707 && TOLOWER (src[len + 3]) != 'p'
708 && TOLOWER (src[len + 4]) != 'c'
709 && src[len + 5] != ')')
710 {
711 *ptr = src + len + 6;
712 op->mode |= mode;
713 return;
714 }
715 /* Fall through into disp case - the grammar is somewhat
716 ambiguous, so we should try whether it's a DISP operand
717 after all ("ER3.L" might be a poorly named label...). */
718 }
719
720 /* Disp. */
721
70d6ecf3 722 /* Start off assuming a 16 bit offset. */
252b5132 723
1b680e4f 724 src = parse_exp (src, op);
252b5132
RH
725 if (*src == ')')
726 {
252b5132 727 op->mode |= ABS | direction;
1b680e4f 728 *ptr = src + 1;
252b5132
RH
729 return;
730 }
731
732 if (*src != ',')
733 {
734 as_bad (_("expected @(exp, reg16)"));
735 return;
252b5132
RH
736 }
737 src++;
738
739 len = parse_reg (src, &mode, &op->reg, direction);
7ee7b84d 740 if (len == 0 || (mode & MODE) != REG)
252b5132
RH
741 {
742 as_bad (_("expected @(exp, reg16)"));
743 return;
744 }
252b5132 745 src += len;
7ee7b84d
MS
746 if (src[0] == '.')
747 {
748 switch (TOLOWER (src[1]))
749 {
750 case 'b':
751 op->mode |= INDEXB | direction;
752 break;
753 case 'w':
754 op->mode |= INDEXW | direction;
755 break;
756 case 'l':
757 op->mode |= INDEXL | direction;
758 break;
759 default:
760 as_bad (_("expected .L, .W or .B for register in indexed addressing mode"));
761 }
762 src += 2;
763 op->reg &= 7;
764 }
765 else
766 op->mode |= DISP | direction;
1b680e4f 767 src = skip_colonthing (src, &op->mode);
252b5132
RH
768
769 if (*src != ')' && '(')
770 {
771 as_bad (_("expected @(exp, reg16)"));
772 return;
773 }
774 *ptr = src + 1;
252b5132
RH
775 return;
776 }
777 len = parse_reg (src, &mode, &num, direction);
778
779 if (len)
780 {
781 src += len;
7ee7b84d 782 if (*src == '+' || *src == '-')
252b5132 783 {
d4e2de6b
NC
784 if (((mode & SIZE) != PSIZE)
785 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
786 && (!Nmode || ((mode & SIZE) != L_32)))
252b5132 787 as_bad (_("Wrong size pointer register for architecture."));
7ee7b84d 788 op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC;
252b5132 789 op->reg = num;
7ee7b84d 790 src++;
252b5132
RH
791 *ptr = src;
792 return;
793 }
d4e2de6b
NC
794 if (((mode & SIZE) != PSIZE)
795 /* For Normal mode accept 16 bit and 32 bit pointer registers. */
796 && (!Nmode || ((mode & SIZE) != L_32)))
252b5132
RH
797 as_bad (_("Wrong size pointer register for architecture."));
798
799 op->mode = direction | IND | PSIZE;
800 op->reg = num;
801 *ptr = src;
802
803 return;
804 }
805 else
806 {
807 /* must be a symbol */
808
809 op->mode = ABS | direction;
1b680e4f 810 *ptr = parse_exp (src, op);
252b5132
RH
811 return;
812 }
813 }
814
252b5132
RH
815 if (*src == '#')
816 {
252b5132 817 op->mode = IMM;
1b680e4f 818 *ptr = parse_exp (src + 1, op);
252b5132
RH
819 return;
820 }
7ee7b84d
MS
821 else if (strncmp (src, "mach", 4) == 0 ||
822 strncmp (src, "macl", 4) == 0 ||
823 strncmp (src, "MACH", 4) == 0 ||
824 strncmp (src, "MACL", 4) == 0)
252b5132 825 {
7ee7b84d 826 op->reg = TOLOWER (src[3]) == 'l';
252b5132
RH
827 op->mode = MACREG;
828 *ptr = src + 4;
829 return;
830 }
831 else
832 {
1b680e4f
RS
833 op->mode = PCREL;
834 *ptr = parse_exp (src, op);
252b5132
RH
835 }
836}
837
70d6ecf3 838static char *
b54a3392 839get_operands (unsigned int noperands, char *op_end, struct h8_op *operand)
252b5132
RH
840{
841 char *ptr = op_end;
842
843 switch (noperands)
844 {
845 case 0:
252b5132
RH
846 break;
847
848 case 1:
849 ptr++;
7ee7b84d 850 get_operand (&ptr, operand + 0, SRC);
252b5132
RH
851 if (*ptr == ',')
852 {
853 ptr++;
7ee7b84d 854 get_operand (&ptr, operand + 1, DST);
252b5132 855 }
252b5132 856 break;
70d6ecf3 857
252b5132
RH
858 case 2:
859 ptr++;
7ee7b84d 860 get_operand (&ptr, operand + 0, SRC);
252b5132
RH
861 if (*ptr == ',')
862 ptr++;
7ee7b84d
MS
863 get_operand (&ptr, operand + 1, DST);
864 break;
865
866 case 3:
867 ptr++;
868 get_operand (&ptr, operand + 0, SRC);
869 if (*ptr == ',')
870 ptr++;
871 get_operand (&ptr, operand + 1, DST);
872 if (*ptr == ',')
873 ptr++;
874 get_operand (&ptr, operand + 2, OP3);
252b5132
RH
875 break;
876
877 default:
878 abort ();
879 }
880
252b5132
RH
881 return ptr;
882}
883
7ee7b84d
MS
884/* MOVA has special requirements. Rather than adding twice the amount of
885 addressing modes, we simply special case it a bit. */
886static void
887get_mova_operands (char *op_end, struct h8_op *operand)
888{
889 char *ptr = op_end;
890
891 if (ptr[1] != '@' || ptr[2] != '(')
892 goto error;
893 ptr += 3;
894 operand[0].mode = 0;
1b680e4f 895 ptr = parse_exp (ptr, &operand[0]);
7ee7b84d
MS
896
897 if (*ptr !=',')
898 goto error;
899 ptr++;
900 get_operand (&ptr, operand + 1, DST);
901
902 if (*ptr =='.')
903 {
904 ptr++;
905 switch (*ptr++)
906 {
907 case 'b': case 'B':
908 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB;
909 break;
910 case 'w': case 'W':
911 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW;
912 break;
913 case 'l': case 'L':
914 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL;
915 break;
916 default:
917 goto error;
918 }
919 }
920 else if ((operand[1].mode & MODE) == LOWREG)
921 {
922 switch (operand[1].mode & SIZE)
923 {
924 case L_8:
925 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB;
926 break;
927 case L_16:
928 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW;
929 break;
930 case L_32:
931 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL;
932 break;
933 default:
934 goto error;
935 }
936 }
937 else
938 goto error;
939
940 if (*ptr++ != ')' || *ptr++ != ',')
941 goto error;
942 get_operand (&ptr, operand + 2, OP3);
943 /* See if we can use the short form of MOVA. */
944 if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG)
945 && (operand[2].mode & MODE) == REG
946 && (operand[1].reg & 7) == (operand[2].reg & 7))
947 {
948 operand[1].mode = operand[2].mode = 0;
949 operand[0].reg = operand[2].reg & 7;
950 }
951 return;
952
953 error:
954 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\""));
7ee7b84d
MS
955}
956
957static void
958get_rtsl_operands (char *ptr, struct h8_op *operand)
959{
2132e3a3
AM
960 int mode, len, type = 0;
961 unsigned int num, num2;
7ee7b84d
MS
962
963 ptr++;
964 if (*ptr == '(')
965 {
966 ptr++;
967 type = 1;
968 }
969 len = parse_reg (ptr, &mode, &num, SRC);
970 if (len == 0 || (mode & MODE) != REG)
971 {
972 as_bad (_("expected register"));
973 return;
974 }
0613284f
RS
975 ptr += len;
976 if (*ptr == '-')
7ee7b84d 977 {
0613284f 978 len = parse_reg (++ptr, &mode, &num2, SRC);
7ee7b84d
MS
979 if (len == 0 || (mode & MODE) != REG)
980 {
981 as_bad (_("expected register"));
982 return;
983 }
984 ptr += len;
7ee7b84d
MS
985 /* CONST_xxx are used as placeholders in the opcode table. */
986 num = num2 - num;
2132e3a3 987 if (num > 3)
7ee7b84d
MS
988 {
989 as_bad (_("invalid register list"));
990 return;
991 }
992 }
993 else
994 num2 = num, num = 0;
0613284f
RS
995 if (type == 1 && *ptr++ != ')')
996 {
997 as_bad (_("expected closing paren"));
998 return;
999 }
7ee7b84d
MS
1000 operand[0].mode = RS32;
1001 operand[1].mode = RD32;
1002 operand[0].reg = num;
1003 operand[1].reg = num2;
1004}
1005
252b5132
RH
1006/* Passed a pointer to a list of opcodes which use different
1007 addressing modes, return the opcode which matches the opcodes
70d6ecf3 1008 provided. */
3048287a 1009
a720f7bc 1010static const struct h8_instruction *
b54a3392
KH
1011get_specific (const struct h8_instruction *instruction,
1012 struct h8_op *operands, int size)
252b5132 1013{
a720f7bc 1014 const struct h8_instruction *this_try = instruction;
7ee7b84d 1015 const struct h8_instruction *found_other = 0, *found_mismatched = 0;
252b5132 1016 int found = 0;
a720f7bc 1017 int this_index = instruction->idx;
7ee7b84d 1018 int noperands = 0;
252b5132
RH
1019
1020 /* There's only one ldm/stm and it's easier to just
1021 get out quick for them. */
7ee7b84d
MS
1022 if (OP_KIND (instruction->opcode->how) == O_LDM
1023 || OP_KIND (instruction->opcode->how) == O_STM)
252b5132
RH
1024 return this_try;
1025
7ee7b84d
MS
1026 while (noperands < 3 && operands[noperands].mode != 0)
1027 noperands++;
1028
a720f7bc 1029 while (this_index == instruction->idx && !found)
252b5132 1030 {
7ee7b84d 1031 int this_size;
252b5132 1032
7ee7b84d 1033 found = 1;
a720f7bc 1034 this_try = instruction++;
7ee7b84d 1035 this_size = this_try->opcode->how & SN;
252b5132 1036
7ee7b84d
MS
1037 if (this_try->noperands != noperands)
1038 found = 0;
1039 else if (this_try->noperands > 0)
252b5132 1040 {
3048287a 1041 int i;
252b5132
RH
1042
1043 for (i = 0; i < this_try->noperands && found; i++)
1044 {
a720f7bc 1045 op_type op = this_try->opcode->args.nib[i];
7ee7b84d
MS
1046 int op_mode = op & MODE;
1047 int op_size = op & SIZE;
252b5132 1048 int x = operands[i].mode;
7ee7b84d
MS
1049 int x_mode = x & MODE;
1050 int x_size = x & SIZE;
252b5132 1051
7ee7b84d 1052 if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG))
252b5132 1053 {
7ee7b84d
MS
1054 if ((x_size == L_8 && (operands[i].reg & 8) == 0)
1055 || (x_size == L_16 && (operands[i].reg & 8) == 8))
1056 as_warn (_("can't use high part of register in operand %d"), i);
1057
1058 if (x_size != op_size)
1059 found = 0;
252b5132 1060 }
7ee7b84d 1061 else if (op_mode == REG)
252b5132 1062 {
7ee7b84d
MS
1063 if (x_mode == LOWREG)
1064 x_mode = REG;
1065 if (x_mode != REG)
252b5132
RH
1066 found = 0;
1067
7ee7b84d
MS
1068 if (x_size == L_P)
1069 x_size = (Hmode ? L_32 : L_16);
1070 if (op_size == L_P)
1071 op_size = (Hmode ? L_32 : L_16);
252b5132 1072
70d6ecf3 1073 /* The size of the reg is v important. */
7ee7b84d 1074 if (op_size != x_size)
252b5132
RH
1075 found = 0;
1076 }
7ee7b84d 1077 else if (op_mode & CTRL) /* control register */
252b5132 1078 {
7ee7b84d
MS
1079 if (!(x_mode & CTRL))
1080 found = 0;
1081
1082 switch (x_mode)
1083 {
1084 case CCR:
1085 if (op_mode != CCR &&
1086 op_mode != CCR_EXR &&
1087 op_mode != CC_EX_VB_SB)
1088 found = 0;
1089 break;
1090 case EXR:
1091 if (op_mode != EXR &&
1092 op_mode != CCR_EXR &&
1093 op_mode != CC_EX_VB_SB)
1094 found = 0;
1095 break;
1096 case MACH:
1097 if (op_mode != MACH &&
1098 op_mode != MACREG)
1099 found = 0;
1100 break;
1101 case MACL:
1102 if (op_mode != MACL &&
1103 op_mode != MACREG)
1104 found = 0;
1105 break;
1106 case VBR:
1107 if (op_mode != VBR &&
1108 op_mode != VBR_SBR &&
1109 op_mode != CC_EX_VB_SB)
1110 found = 0;
1111 break;
1112 case SBR:
1113 if (op_mode != SBR &&
1114 op_mode != VBR_SBR &&
1115 op_mode != CC_EX_VB_SB)
1116 found = 0;
1117 break;
1118 }
1119 }
1120 else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL))
1121 {
1122 operands[i].mode &= ~MODE;
252b5132 1123 operands[i].mode |= ABSJMP;
70d6ecf3 1124 /* But it may not be 24 bits long. */
7ee7b84d 1125 if (x_mode == ABS && !Hmode)
252b5132
RH
1126 {
1127 operands[i].mode &= ~SIZE;
1128 operands[i].mode |= L_16;
1129 }
7ee7b84d
MS
1130 if ((operands[i].mode & SIZE) == L_32
1131 && (op_mode & SIZE) != L_32)
1132 found = 0;
252b5132 1133 }
7ee7b84d 1134 else if (x_mode == IMM && op_mode != IMM)
252b5132 1135 {
7ee7b84d
MS
1136 offsetT num = operands[i].exp.X_add_number;
1137 if (op_mode == KBIT || op_mode == DBIT)
1138 /* This is ok if the immediate value is sensible. */;
1139 else if (op_mode == CONST_2)
1140 found = num == 2;
1141 else if (op_mode == CONST_4)
1142 found = num == 4;
1143 else if (op_mode == CONST_8)
1144 found = num == 8;
1145 else if (op_mode == CONST_16)
1146 found = num == 16;
1147 else
1148 found = 0;
252b5132 1149 }
7ee7b84d 1150 else if (op_mode == PCREL && op_mode == x_mode)
252b5132 1151 {
ba18dd6f 1152 /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour:
7ee7b84d 1153 If x_size is L_8, promote it. */
ba18dd6f
AO
1154 if (OP_KIND (this_try->opcode->how) == O_MOVSD
1155 || OP_KIND (this_try->opcode->how) == O_BSRBC
1156 || OP_KIND (this_try->opcode->how) == O_BSRBS)
7ee7b84d
MS
1157 if (x_size == L_8)
1158 x_size = L_16;
1159
70d6ecf3 1160 /* The size of the displacement is important. */
7ee7b84d 1161 if (op_size != x_size)
252b5132
RH
1162 found = 0;
1163 }
7ee7b84d
MS
1164 else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS
1165 || op_mode == INDEXB || op_mode == INDEXW
1166 || op_mode == INDEXL)
1167 && op_mode == x_mode)
252b5132
RH
1168 {
1169 /* Promote a L_24 to L_32 if it makes us match. */
7ee7b84d 1170 if (x_size == L_24 && op_size == L_32)
252b5132 1171 {
7ee7b84d
MS
1172 x &= ~SIZE;
1173 x |= x_size = L_32;
252b5132 1174 }
7ee7b84d 1175
7ee7b84d 1176 if (((x_size == L_16 && op_size == L_16U)
2d0d09ca 1177 || (x_size == L_8 && op_size == L_8U)
7ee7b84d
MS
1178 || (x_size == L_3 && op_size == L_3NZ))
1179 /* We're deliberately more permissive for ABS modes. */
1180 && (op_mode == ABS
1181 || constant_fits_size_p (operands + i, op_size,
1182 op & NO_SYMBOLS)))
1183 x_size = op_size;
1184
1185 if (x_size != 0 && op_size != x_size)
1186 found = 0;
1187 else if (x_size == 0
1188 && ! constant_fits_size_p (operands + i, op_size,
1189 op & NO_SYMBOLS))
252b5132
RH
1190 found = 0;
1191 }
7ee7b84d 1192 else if (op_mode != x_mode)
252b5132
RH
1193 {
1194 found = 0;
70d6ecf3 1195 }
252b5132
RH
1196 }
1197 }
7ee7b84d
MS
1198 if (found)
1199 {
1200 if ((this_try->opcode->available == AV_H8SX && ! SXmode)
d4ea8842 1201 || (this_try->opcode->available == AV_H8S && ! Smode)
7ee7b84d
MS
1202 || (this_try->opcode->available == AV_H8H && ! Hmode))
1203 found = 0, found_other = this_try;
1204 else if (this_size != size && (this_size != SN && size != SN))
1205 found_mismatched = this_try, found = 0;
1206
1207 }
252b5132
RH
1208 }
1209 if (found)
1210 return this_try;
7ee7b84d
MS
1211 if (found_other)
1212 {
1213 as_warn (_("Opcode `%s' with these operand types not available in %s mode"),
1214 found_other->opcode->name,
1215 (! Hmode && ! Smode ? "H8/300"
1216 : SXmode ? "H8sx"
1217 : Smode ? "H8/300S"
1218 : "H8/300H"));
1219 }
1220 else if (found_mismatched)
1221 {
1222 as_warn (_("mismatch between opcode size and operand size"));
1223 return found_mismatched;
1224 }
1225 return 0;
252b5132
RH
1226}
1227
1228static void
b54a3392 1229check_operand (struct h8_op *operand, unsigned int width, char *string)
252b5132
RH
1230{
1231 if (operand->exp.X_add_symbol == 0
1232 && operand->exp.X_op_symbol == 0)
1233 {
70d6ecf3
AM
1234 /* No symbol involved, let's look at offset, it's dangerous if
1235 any of the high bits are not 0 or ff's, find out by oring or
1236 anding with the width and seeing if the answer is 0 or all
1237 fs. */
252b5132 1238
7ee7b84d 1239 if (! constant_fits_width_p (operand, width))
252b5132 1240 {
70d6ecf3 1241 if (width == 255
252b5132
RH
1242 && (operand->exp.X_add_number & 0xff00) == 0xff00)
1243 {
1244 /* Just ignore this one - which happens when trying to
1245 fit a 16 bit address truncated into an 8 bit address
1246 of something like bset. */
1247 }
166e23f9
KH
1248 else if (strcmp (string, "@") == 0
1249 && width == 0xffff
1250 && (operand->exp.X_add_number & 0xff8000) == 0xff8000)
1251 {
1252 /* Just ignore this one - which happens when trying to
1253 fit a 24 bit address truncated into a 16 bit address
1254 of something like mov.w. */
1255 }
70d6ecf3 1256 else
252b5132
RH
1257 {
1258 as_warn (_("operand %s0x%lx out of range."), string,
1259 (unsigned long) operand->exp.X_add_number);
1260 }
1261 }
1262 }
252b5132
RH
1263}
1264
1265/* RELAXMODE has one of 3 values:
1266
1267 0 Output a "normal" reloc, no relaxing possible for this insn/reloc
1268
1269 1 Output a relaxable 24bit absolute mov.w address relocation
1270 (may relax into a 16bit absolute address).
1271
1272 2 Output a relaxable 16/24 absolute mov.b address relocation
1273 (may relax into an 8bit absolute address). */
1274
1275static void
b54a3392 1276do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode)
252b5132
RH
1277{
1278 int idx;
1279 int size;
1280 int where;
7ee7b84d 1281 char *bytes = frag_now->fr_literal + offset;
252b5132 1282
7ee7b84d 1283 char *t = ((operand->mode & MODE) == IMM) ? "#" : "@";
252b5132
RH
1284
1285 if (operand->exp.X_add_symbol == 0)
1286 {
252b5132
RH
1287 switch (operand->mode & SIZE)
1288 {
1289 case L_2:
1290 check_operand (operand, 0x3, t);
7ee7b84d 1291 bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4);
252b5132
RH
1292 break;
1293 case L_3:
7ee7b84d 1294 case L_3NZ:
252b5132 1295 check_operand (operand, 0x7, t);
7ee7b84d
MS
1296 bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4);
1297 break;
1298 case L_4:
1299 check_operand (operand, 0xF, t);
1300 bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4);
1301 break;
1302 case L_5:
1303 check_operand (operand, 0x1F, t);
1304 bytes[0] |= operand->exp.X_add_number & 31;
252b5132
RH
1305 break;
1306 case L_8:
7ee7b84d 1307 case L_8U:
252b5132 1308 check_operand (operand, 0xff, t);
7ee7b84d 1309 bytes[0] |= operand->exp.X_add_number;
252b5132
RH
1310 break;
1311 case L_16:
7ee7b84d 1312 case L_16U:
252b5132 1313 check_operand (operand, 0xffff, t);
7ee7b84d
MS
1314 bytes[0] |= operand->exp.X_add_number >> 8;
1315 bytes[1] |= operand->exp.X_add_number >> 0;
252b5132
RH
1316 break;
1317 case L_24:
1318 check_operand (operand, 0xffffff, t);
7ee7b84d
MS
1319 bytes[0] |= operand->exp.X_add_number >> 16;
1320 bytes[1] |= operand->exp.X_add_number >> 8;
1321 bytes[2] |= operand->exp.X_add_number >> 0;
252b5132
RH
1322 break;
1323
1324 case L_32:
70d6ecf3 1325 /* This should be done with bfd. */
7ee7b84d
MS
1326 bytes[0] |= operand->exp.X_add_number >> 24;
1327 bytes[1] |= operand->exp.X_add_number >> 16;
1328 bytes[2] |= operand->exp.X_add_number >> 8;
1329 bytes[3] |= operand->exp.X_add_number >> 0;
4132022d
AM
1330 if (relaxmode != 0)
1331 {
1332 idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1;
1333 fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx);
1334 }
252b5132
RH
1335 break;
1336 }
252b5132
RH
1337 }
1338 else
1339 {
1340 switch (operand->mode & SIZE)
1341 {
252b5132
RH
1342 case L_24:
1343 case L_32:
1344 size = 4;
1345 where = (operand->mode & SIZE) == L_24 ? -1 : 0;
1346 if (relaxmode == 2)
1347 idx = R_MOV24B1;
1348 else if (relaxmode == 1)
1349 idx = R_MOVL1;
1350 else
1351 idx = R_RELLONG;
1352 break;
1353 default:
70d6ecf3 1354 as_bad (_("Can't work out size of operand.\n"));
252b5132 1355 case L_16:
7ee7b84d 1356 case L_16U:
252b5132
RH
1357 size = 2;
1358 where = 0;
1359 if (relaxmode == 2)
1360 idx = R_MOV16B1;
1361 else
1362 idx = R_RELWORD;
4132022d
AM
1363 operand->exp.X_add_number =
1364 ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000;
7ee7b84d 1365 operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1];
252b5132
RH
1366 break;
1367 case L_8:
1368 size = 1;
1369 where = 0;
1370 idx = R_RELBYTE;
4132022d
AM
1371 operand->exp.X_add_number =
1372 ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80;
7ee7b84d 1373 operand->exp.X_add_number |= bytes[0];
252b5132
RH
1374 }
1375
1376 fix_new_exp (frag_now,
1377 offset + where,
1378 size,
1379 &operand->exp,
1380 0,
1381 idx);
1382 }
252b5132
RH
1383}
1384
70d6ecf3 1385/* Now we know what sort of opcodes it is, let's build the bytes. */
3048287a 1386
252b5132 1387static void
b54a3392 1388build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
252b5132 1389{
3048287a 1390 int i;
252b5132 1391 char *output = frag_more (this_try->length);
d1e50f8a 1392 const op_type *nibble_ptr = this_try->opcode->data.nib;
252b5132
RH
1393 op_type c;
1394 unsigned int nibble_count = 0;
7ee7b84d 1395 int op_at[3];
3048287a 1396 int nib = 0;
252b5132 1397 int movb = 0;
7ee7b84d 1398 char asnibbles[100];
252b5132 1399 char *p = asnibbles;
7ee7b84d 1400 int high, low;
252b5132 1401
d4ea8842 1402 if (!Hmode && this_try->opcode->available != AV_H8)
252b5132 1403 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"),
a720f7bc 1404 this_try->opcode->name);
d4ea8842
MS
1405 else if (!Smode
1406 && this_try->opcode->available != AV_H8
1407 && this_try->opcode->available != AV_H8H)
1408 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"),
1409 this_try->opcode->name);
1410 else if (!SXmode
1411 && this_try->opcode->available != AV_H8
1412 && this_try->opcode->available != AV_H8H
1413 && this_try->opcode->available != AV_H8S)
1414 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"),
1415 this_try->opcode->name);
252b5132 1416
7ee7b84d 1417 while (*nibble_ptr != (op_type) E)
252b5132
RH
1418 {
1419 int d;
7ee7b84d
MS
1420
1421 nib = 0;
252b5132
RH
1422 c = *nibble_ptr++;
1423
7ee7b84d 1424 d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0;
252b5132
RH
1425
1426 if (c < 16)
3048287a 1427 nib = c;
252b5132
RH
1428 else
1429 {
7ee7b84d
MS
1430 int c2 = c & MODE;
1431
1432 if (c2 == REG || c2 == LOWREG
1433 || c2 == IND || c2 == PREINC || c2 == PREDEC
1434 || c2 == POSTINC || c2 == POSTDEC)
1435 {
1436 nib = operand[d].reg;
1437 if (c2 == LOWREG)
1438 nib &= 7;
1439 }
1440
1441 else if (c & CTRL) /* Control reg operand. */
3048287a
NC
1442 nib = operand[d].reg;
1443
252b5132 1444 else if ((c & DISPREG) == (DISPREG))
7ee7b84d
MS
1445 {
1446 nib = operand[d].reg;
1447 }
1448 else if (c2 == ABS)
252b5132
RH
1449 {
1450 operand[d].mode = c;
7ee7b84d 1451 op_at[d] = nibble_count;
252b5132
RH
1452 nib = 0;
1453 }
7ee7b84d
MS
1454 else if (c2 == IMM || c2 == PCREL || c2 == ABS
1455 || (c & ABSJMP) || c2 == DISP)
252b5132
RH
1456 {
1457 operand[d].mode = c;
7ee7b84d 1458 op_at[d] = nibble_count;
252b5132
RH
1459 nib = 0;
1460 }
7ee7b84d 1461 else if ((c & IGNORE) || (c & DATA))
3048287a
NC
1462 nib = 0;
1463
7ee7b84d 1464 else if (c2 == DBIT)
252b5132
RH
1465 {
1466 switch (operand[0].exp.X_add_number)
1467 {
1468 case 1:
1469 nib = c;
1470 break;
1471 case 2:
1472 nib = 0x8 | c;
1473 break;
1474 default:
1475 as_bad (_("Need #1 or #2 here"));
1476 }
1477 }
7ee7b84d 1478 else if (c2 == KBIT)
252b5132
RH
1479 {
1480 switch (operand[0].exp.X_add_number)
1481 {
1482 case 1:
1483 nib = 0;
1484 break;
1485 case 2:
1486 nib = 8;
1487 break;
1488 case 4:
1489 if (!Hmode)
1490 as_warn (_("#4 not valid on H8/300."));
1491 nib = 9;
1492 break;
1493
1494 default:
1495 as_bad (_("Need #1 or #2 here"));
1496 break;
1497 }
70d6ecf3 1498 /* Stop it making a fix. */
252b5132
RH
1499 operand[0].mode = 0;
1500 }
1501
1502 if (c & MEMRELAX)
3048287a 1503 operand[d].mode |= MEMRELAX;
252b5132
RH
1504
1505 if (c & B31)
3048287a 1506 nib |= 0x8;
252b5132 1507
7ee7b84d
MS
1508 if (c & B21)
1509 nib |= 0x4;
1510
1511 if (c & B11)
1512 nib |= 0x2;
1513
1514 if (c & B01)
1515 nib |= 0x1;
1516
1517 if (c2 == MACREG)
252b5132 1518 {
f0c56b90
NC
1519 if (operand[0].mode == MACREG)
1520 /* stmac has mac[hl] as the first operand. */
1521 nib = 2 + operand[0].reg;
1522 else
1523 /* ldmac has mac[hl] as the second operand. */
1524 nib = 2 + operand[1].reg;
252b5132
RH
1525 }
1526 }
1527 nibble_count++;
1528
1529 *p++ = nib;
1530 }
1531
1532 /* Disgusting. Why, oh why didn't someone ask us for advice
1533 on the assembler format. */
7ee7b84d 1534 if (OP_KIND (this_try->opcode->how) == O_LDM)
252b5132 1535 {
7ee7b84d
MS
1536 high = (operand[1].reg >> 8) & 0xf;
1537 low = (operand[1].reg) & 0xf;
252b5132 1538 asnibbles[2] = high - low;
7ee7b84d
MS
1539 asnibbles[7] = high;
1540 }
1541 else if (OP_KIND (this_try->opcode->how) == O_STM)
1542 {
1543 high = (operand[0].reg >> 8) & 0xf;
1544 low = (operand[0].reg) & 0xf;
1545 asnibbles[2] = high - low;
1546 asnibbles[7] = low;
252b5132
RH
1547 }
1548
1549 for (i = 0; i < this_try->length; i++)
3048287a 1550 output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1];
252b5132 1551
ca9a79a1
NC
1552 /* Note if this is a movb or a bit manipulation instruction
1553 there is a special relaxation which only applies. */
1554 if ( this_try->opcode->how == O (O_MOV, SB)
1555 || this_try->opcode->how == O (O_BCLR, SB)
1556 || this_try->opcode->how == O (O_BAND, SB)
1557 || this_try->opcode->how == O (O_BIAND, SB)
1558 || this_try->opcode->how == O (O_BILD, SB)
1559 || this_try->opcode->how == O (O_BIOR, SB)
1560 || this_try->opcode->how == O (O_BIST, SB)
1561 || this_try->opcode->how == O (O_BIXOR, SB)
1562 || this_try->opcode->how == O (O_BLD, SB)
1563 || this_try->opcode->how == O (O_BNOT, SB)
1564 || this_try->opcode->how == O (O_BOR, SB)
1565 || this_try->opcode->how == O (O_BSET, SB)
1566 || this_try->opcode->how == O (O_BST, SB)
1567 || this_try->opcode->how == O (O_BTST, SB)
1568 || this_try->opcode->how == O (O_BXOR, SB))
252b5132
RH
1569 movb = 1;
1570
70d6ecf3 1571 /* Output any fixes. */
7ee7b84d 1572 for (i = 0; i < this_try->noperands; i++)
252b5132
RH
1573 {
1574 int x = operand[i].mode;
7ee7b84d 1575 int x_mode = x & MODE;
252b5132 1576
7ee7b84d
MS
1577 if (x_mode == IMM || x_mode == DISP)
1578 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2,
1579 op_at[i] & 1, operand + i, (x & MEMRELAX) != 0);
3048287a 1580
7ee7b84d
MS
1581 else if (x_mode == ABS)
1582 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2,
1583 op_at[i] & 1, operand + i,
1584 (x & MEMRELAX) ? movb + 1 : 0);
3048287a 1585
7ee7b84d 1586 else if (x_mode == PCREL)
252b5132 1587 {
7ee7b84d 1588 int size16 = (x & SIZE) == L_16;
252b5132
RH
1589 int size = size16 ? 2 : 1;
1590 int type = size16 ? R_PCRWORD : R_PCRBYTE;
36ed2fff 1591 fixS *fixP;
252b5132
RH
1592
1593 check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@");
1594
1595 if (operand[i].exp.X_add_number & 1)
3048287a
NC
1596 as_warn (_("branch operand has odd offset (%lx)\n"),
1597 (unsigned long) operand->exp.X_add_number);
36ed2fff
JL
1598#ifndef OBJ_ELF
1599 /* The COFF port has always been off by one, changing it
1600 now would be an incompatible change, so we leave it as-is.
1601
1602 We don't want to do this for ELF as we want to be
1603 compatible with the proposed ELF format from Hitachi. */
252b5132 1604 operand[i].exp.X_add_number -= 1;
36ed2fff 1605#endif
7ee7b84d
MS
1606 if (size16)
1607 {
1608 operand[i].exp.X_add_number =
1609 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000;
1610 }
1611 else
1612 {
1613 operand[i].exp.X_add_number =
1614 ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80;
1615 }
1616
1617 /* For BRA/S. */
1618 if (! size16)
1619 operand[i].exp.X_add_number |= output[op_at[i] / 2];
252b5132 1620
36ed2fff 1621 fixP = fix_new_exp (frag_now,
7ee7b84d 1622 output - frag_now->fr_literal + op_at[i] / 2,
36ed2fff
JL
1623 size,
1624 &operand[i].exp,
1625 1,
1626 type);
1627 fixP->fx_signed = 1;
252b5132 1628 }
7ee7b84d 1629 else if (x_mode == MEMIND)
252b5132 1630 {
252b5132
RH
1631 check_operand (operand + i, 0xff, "@@");
1632 fix_new_exp (frag_now,
1633 output - frag_now->fr_literal + 1,
1634 1,
1635 &operand[i].exp,
1636 0,
1637 R_MEM_INDIRECT);
1638 }
7ee7b84d
MS
1639 else if (x_mode == VECIND)
1640 {
1641 check_operand (operand + i, 0x7f, "@@");
1642 /* FIXME: approximating the effect of "B31" here...
1643 This is very hackish, and ought to be done a better way. */
1644 operand[i].exp.X_add_number |= 0x80;
1645 fix_new_exp (frag_now,
1646 output - frag_now->fr_literal + 1,
1647 1,
1648 &operand[i].exp,
1649 0,
1650 R_MEM_INDIRECT);
1651 }
252b5132
RH
1652 else if (x & ABSJMP)
1653 {
3c1ba8a3 1654 int where = 0;
7ee7b84d 1655 bfd_reloc_code_real_type reloc_type = R_JMPL1;
3c1ba8a3
JL
1656
1657#ifdef OBJ_ELF
1658 /* To be compatible with the proposed H8 ELF format, we
1659 want the relocation's offset to point to the first byte
1660 that will be modified, not to the start of the instruction. */
7ee7b84d
MS
1661
1662 if ((operand->mode & SIZE) == L_32)
1663 {
1664 where = 2;
1665 reloc_type = R_RELLONG;
1666 }
1667 else
1668 where = 1;
3c1ba8a3 1669#endif
de342d07 1670
70d6ecf3 1671 /* This jmp may be a jump or a branch. */
252b5132 1672
7ee7b84d
MS
1673 check_operand (operand + i,
1674 SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff,
1675 "@");
3048287a 1676
252b5132 1677 if (operand[i].exp.X_add_number & 1)
3048287a
NC
1678 as_warn (_("branch operand has odd offset (%lx)\n"),
1679 (unsigned long) operand->exp.X_add_number);
1680
252b5132 1681 if (!Hmode)
70d6ecf3 1682 operand[i].exp.X_add_number =
4132022d 1683 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000;
252b5132 1684 fix_new_exp (frag_now,
3c1ba8a3 1685 output - frag_now->fr_literal + where,
252b5132
RH
1686 4,
1687 &operand[i].exp,
1688 0,
7ee7b84d 1689 reloc_type);
252b5132
RH
1690 }
1691 }
252b5132
RH
1692}
1693
70d6ecf3
AM
1694/* Try to give an intelligent error message for common and simple to
1695 detect errors. */
3048287a 1696
252b5132 1697static void
b54a3392
KH
1698clever_message (const struct h8_instruction *instruction,
1699 struct h8_op *operand)
252b5132 1700{
70d6ecf3 1701 /* Find out if there was more than one possible opcode. */
252b5132 1702
a720f7bc 1703 if ((instruction + 1)->idx != instruction->idx)
252b5132 1704 {
3048287a 1705 int argn;
252b5132 1706
70d6ecf3
AM
1707 /* Only one opcode of this flavour, try to guess which operand
1708 didn't match. */
a720f7bc 1709 for (argn = 0; argn < instruction->noperands; argn++)
252b5132 1710 {
a720f7bc 1711 switch (instruction->opcode->args.nib[argn])
252b5132
RH
1712 {
1713 case RD16:
1714 if (operand[argn].mode != RD16)
1715 {
1716 as_bad (_("destination operand must be 16 bit register"));
1717 return;
1718
1719 }
1720 break;
1721
1722 case RS8:
252b5132
RH
1723 if (operand[argn].mode != RS8)
1724 {
1725 as_bad (_("source operand must be 8 bit register"));
1726 return;
1727 }
1728 break;
1729
1730 case ABS16DST:
1731 if (operand[argn].mode != ABS16DST)
1732 {
1733 as_bad (_("destination operand must be 16bit absolute address"));
1734 return;
1735 }
1736 break;
1737 case RD8:
1738 if (operand[argn].mode != RD8)
1739 {
1740 as_bad (_("destination operand must be 8 bit register"));
1741 return;
1742 }
1743 break;
1744
252b5132
RH
1745 case ABS16SRC:
1746 if (operand[argn].mode != ABS16SRC)
1747 {
1748 as_bad (_("source operand must be 16bit absolute address"));
1749 return;
1750 }
1751 break;
1752
1753 }
1754 }
1755 }
1756 as_bad (_("invalid operands"));
1757}
1758
d4ea8842 1759
1b680e4f
RS
1760/* If OPERAND is part of an address, adjust its size and value given
1761 that it addresses SIZE bytes.
d4ea8842 1762
1b680e4f
RS
1763 This function decides how big non-immediate constants are when no
1764 size was explicitly given. It also scales down the assembly-level
d4ea8842
MS
1765 displacement in an @(d:2,ERn) operand. */
1766
1767static void
b54a3392 1768fix_operand_size (struct h8_op *operand, int size)
d4ea8842 1769{
1b680e4f 1770 if (SXmode && (operand->mode & MODE) == DISP)
d4ea8842
MS
1771 {
1772 /* If the user didn't specify an operand width, see if we
1773 can use @(d:2,ERn). */
1b680e4f
RS
1774 if ((operand->mode & SIZE) == 0
1775 && operand->exp.X_add_symbol == 0
1776 && operand->exp.X_op_symbol == 0
d4ea8842
MS
1777 && (operand->exp.X_add_number == size
1778 || operand->exp.X_add_number == size * 2
1779 || operand->exp.X_add_number == size * 3))
1780 operand->mode |= L_2;
1781
1782 /* Scale down the displacement in an @(d:2,ERn) operand.
1783 X_add_number then contains the desired field value. */
1784 if ((operand->mode & SIZE) == L_2)
1785 {
1786 if (operand->exp.X_add_number % size != 0)
1787 as_warn (_("operand/size mis-match"));
1788 operand->exp.X_add_number /= size;
1789 }
1790 }
1791
d4ea8842
MS
1792 if ((operand->mode & SIZE) == 0)
1793 switch (operand->mode & MODE)
1794 {
1795 case DISP:
1796 case INDEXB:
1797 case INDEXW:
1798 case INDEXL:
1799 case ABS:
1b680e4f
RS
1800 /* Pick a 24-bit address unless we know that a 16-bit address
1801 is safe. get_specific() will relax L_24 into L_32 where
1802 necessary. */
1803 if (Hmode
d4e2de6b 1804 && !Nmode
1b680e4f
RS
1805 && (operand->exp.X_add_number < -32768
1806 || operand->exp.X_add_number > 32767
1807 || operand->exp.X_add_symbol != 0
1808 || operand->exp.X_op_symbol != 0))
1809 operand->mode |= L_24;
1810 else
1811 operand->mode |= L_16;
1812 break;
1813
1814 case PCREL:
1815 /* This condition is long standing, though somewhat suspect. */
1816 if (operand->exp.X_add_number > -128
1817 && operand->exp.X_add_number < 127)
1818 operand->mode |= L_8;
1819 else
1820 operand->mode |= L_16;
d4ea8842
MS
1821 break;
1822 }
1823}
1824
1825
70d6ecf3
AM
1826/* This is the guts of the machine-dependent assembler. STR points to
1827 a machine dependent instruction. This function is supposed to emit
1828 the frags/bytes it assembles. */
3048287a 1829
252b5132 1830void
b54a3392 1831md_assemble (char *str)
252b5132
RH
1832{
1833 char *op_start;
1834 char *op_end;
7ee7b84d 1835 struct h8_op operand[3];
a720f7bc
KD
1836 const struct h8_instruction *instruction;
1837 const struct h8_instruction *prev_instruction;
252b5132
RH
1838
1839 char *dot = 0;
0c0b9be0 1840 char *slash = 0;
252b5132 1841 char c;
7ee7b84d 1842 int size, i;
252b5132 1843
70d6ecf3 1844 /* Drop leading whitespace. */
252b5132
RH
1845 while (*str == ' ')
1846 str++;
1847
70d6ecf3 1848 /* Find the op code end. */
252b5132
RH
1849 for (op_start = op_end = str;
1850 *op_end != 0 && *op_end != ' ';
1851 op_end++)
1852 {
1853 if (*op_end == '.')
1854 {
1855 dot = op_end + 1;
1856 *op_end = 0;
1857 op_end += 2;
1858 break;
1859 }
0c0b9be0
AO
1860 else if (*op_end == '/' && ! slash)
1861 slash = op_end;
252b5132
RH
1862 }
1863
252b5132
RH
1864 if (op_end == op_start)
1865 {
1866 as_bad (_("can't find opcode "));
1867 }
1868 c = *op_end;
1869
1870 *op_end = 0;
1871
0c0b9be0
AO
1872 /* The assembler stops scanning the opcode at slashes, so it fails
1873 to make characters following them lower case. Fix them. */
1874 if (slash)
1875 while (*++slash)
1876 *slash = TOLOWER (*slash);
1877
a720f7bc
KD
1878 instruction = (const struct h8_instruction *)
1879 hash_find (opcode_hash_control, op_start);
252b5132 1880
a720f7bc 1881 if (instruction == NULL)
252b5132
RH
1882 {
1883 as_bad (_("unknown opcode"));
1884 return;
1885 }
1886
70d6ecf3 1887 /* We used to set input_line_pointer to the result of get_operands,
252b5132
RH
1888 but that is wrong. Our caller assumes we don't change it. */
1889
7ee7b84d
MS
1890 operand[0].mode = 0;
1891 operand[1].mode = 0;
1892 operand[2].mode = 0;
1893
1894 if (OP_KIND (instruction->opcode->how) == O_MOVAB
1895 || OP_KIND (instruction->opcode->how) == O_MOVAW
1896 || OP_KIND (instruction->opcode->how) == O_MOVAL)
1897 get_mova_operands (op_end, operand);
1898 else if (OP_KIND (instruction->opcode->how) == O_RTEL
1899 || OP_KIND (instruction->opcode->how) == O_RTSL)
1900 get_rtsl_operands (op_end, operand);
1901 else
1902 get_operands (instruction->noperands, op_end, operand);
1903
252b5132 1904 *op_end = c;
a720f7bc 1905 prev_instruction = instruction;
252b5132 1906
4892e510
NC
1907 /* Now we have operands from instruction.
1908 Let's check them out for ldm and stm. */
1909 if (OP_KIND (instruction->opcode->how) == O_LDM)
1910 {
1911 /* The first operand must be @er7+, and the
1912 second operand must be a register pair. */
1913 if ((operand[0].mode != RSINC)
1914 || (operand[0].reg != 7)
1915 || ((operand[1].reg & 0x80000000) == 0))
1916 as_bad (_("invalid operand in ldm"));
1917 }
1918 else if (OP_KIND (instruction->opcode->how) == O_STM)
1919 {
1920 /* The first operand must be a register pair,
1921 and the second operand must be @-er7. */
1922 if (((operand[0].reg & 0x80000000) == 0)
1923 || (operand[1].mode != RDDEC)
1924 || (operand[1].reg != 7))
1925 as_bad (_("invalid operand in stm"));
1926 }
1927
252b5132
RH
1928 size = SN;
1929 if (dot)
1930 {
0c0b9be0 1931 switch (TOLOWER (*dot))
252b5132
RH
1932 {
1933 case 'b':
1934 size = SB;
1935 break;
1936
1937 case 'w':
1938 size = SW;
1939 break;
1940
1941 case 'l':
1942 size = SL;
1943 break;
1944 }
1945 }
7ee7b84d
MS
1946 if (OP_KIND (instruction->opcode->how) == O_MOVAB ||
1947 OP_KIND (instruction->opcode->how) == O_MOVAW ||
1948 OP_KIND (instruction->opcode->how) == O_MOVAL)
252b5132 1949 {
d4ea8842
MS
1950 switch (operand[0].mode & MODE)
1951 {
7ee7b84d
MS
1952 case INDEXB:
1953 default:
d4ea8842 1954 fix_operand_size (&operand[1], 1);
7ee7b84d
MS
1955 break;
1956 case INDEXW:
d4ea8842 1957 fix_operand_size (&operand[1], 2);
7ee7b84d
MS
1958 break;
1959 case INDEXL:
d4ea8842 1960 fix_operand_size (&operand[1], 4);
7ee7b84d 1961 break;
252b5132
RH
1962 }
1963 }
7ee7b84d
MS
1964 else
1965 {
d4ea8842
MS
1966 for (i = 0; i < 3 && operand[i].mode != 0; i++)
1967 switch (size)
1968 {
7ee7b84d
MS
1969 case SN:
1970 case SB:
1971 default:
d4ea8842 1972 fix_operand_size (&operand[i], 1);
7ee7b84d
MS
1973 break;
1974 case SW:
d4ea8842 1975 fix_operand_size (&operand[i], 2);
7ee7b84d
MS
1976 break;
1977 case SL:
d4ea8842 1978 fix_operand_size (&operand[i], 4);
7ee7b84d
MS
1979 break;
1980 }
1981 }
252b5132 1982
d4ea8842
MS
1983 instruction = get_specific (instruction, operand, size);
1984
1985 if (instruction == 0)
1986 {
1987 /* Couldn't find an opcode which matched the operands. */
1988 char *where = frag_more (2);
1989
1990 where[0] = 0x0;
1991 where[1] = 0x0;
1992 clever_message (prev_instruction, operand);
1993
1994 return;
1995 }
1996
a720f7bc 1997 build_bytes (instruction, operand);
2c8714f2 1998
2c8714f2 1999 dwarf2_emit_insn (instruction->length);
252b5132
RH
2000}
2001
2002symbolS *
b54a3392 2003md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH
2004{
2005 return 0;
2006}
2007
252b5132
RH
2008/* Various routines to kill one day */
2009/* Equal to MAX_PRECISION in atof-ieee.c */
2010#define MAX_LITTLENUMS 6
2011
70d6ecf3
AM
2012/* Turn a string in input_line_pointer into a floating point constant
2013 of type TYPE, and store the appropriate bytes in *LITP. The number
bc0d738a 2014 of LITTLENUMS emitted is stored in *SIZEP. An error message is
70d6ecf3 2015 returned, or NULL on OK. */
bc0d738a 2016
252b5132 2017char *
b54a3392 2018md_atof (int type, char *litP, int *sizeP)
252b5132
RH
2019{
2020 int prec;
2021 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2022 LITTLENUM_TYPE *wordP;
2023 char *t;
252b5132
RH
2024
2025 switch (type)
2026 {
2027 case 'f':
2028 case 'F':
2029 case 's':
2030 case 'S':
2031 prec = 2;
2032 break;
2033
2034 case 'd':
2035 case 'D':
2036 case 'r':
2037 case 'R':
2038 prec = 4;
2039 break;
2040
2041 case 'x':
2042 case 'X':
2043 prec = 6;
2044 break;
2045
2046 case 'p':
2047 case 'P':
2048 prec = 6;
2049 break;
2050
2051 default:
2052 *sizeP = 0;
2053 return _("Bad call to MD_ATOF()");
2054 }
2055 t = atof_ieee (input_line_pointer, type, words);
2056 if (t)
2057 input_line_pointer = t;
2058
2059 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2060 for (wordP = words; prec--;)
2061 {
2062 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
2063 litP += sizeof (LITTLENUM_TYPE);
2064 }
2065 return 0;
2066}
2067\f
5a38dc70 2068const char *md_shortopts = "";
252b5132
RH
2069struct option md_longopts[] = {
2070 {NULL, no_argument, NULL, 0}
2071};
70d6ecf3
AM
2072
2073size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH
2074
2075int
b54a3392 2076md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
252b5132
RH
2077{
2078 return 0;
2079}
2080
2081void
b54a3392 2082md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
252b5132
RH
2083{
2084}
2085\f
b54a3392 2086void tc_aout_fix_to_chars (void);
3048287a 2087
252b5132 2088void
b54a3392 2089tc_aout_fix_to_chars (void)
252b5132
RH
2090{
2091 printf (_("call to tc_aout_fix_to_chars \n"));
2092 abort ();
2093}
2094
2095void
7be1c489 2096md_convert_frag (bfd *headers ATTRIBUTE_UNUSED,
b54a3392
KH
2097 segT seg ATTRIBUTE_UNUSED,
2098 fragS *fragP ATTRIBUTE_UNUSED)
252b5132
RH
2099{
2100 printf (_("call to md_convert_frag \n"));
2101 abort ();
2102}
2103
3c1ba8a3 2104valueT
b54a3392 2105md_section_align (segT segment, valueT size)
3c1ba8a3
JL
2106{
2107 int align = bfd_get_section_alignment (stdoutput, segment);
2108 return ((size + (1 << align) - 1) & (-1 << align));
2109}
252b5132
RH
2110
2111void
55cf6793 2112md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132
RH
2113{
2114 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
a161fe53 2115 long val = *valP;
252b5132
RH
2116
2117 switch (fixP->fx_size)
2118 {
2119 case 1:
2120 *buf++ = val;
2121 break;
2122 case 2:
2123 *buf++ = (val >> 8);
2124 *buf++ = val;
2125 break;
2126 case 4:
2127 *buf++ = (val >> 24);
2128 *buf++ = (val >> 16);
2129 *buf++ = (val >> 8);
2130 *buf++ = val;
2131 break;
550c1888
NC
2132 case 8:
2133 /* This can arise when the .quad or .8byte pseudo-ops are used.
2134 Returning here (without setting fx_done) will cause the code
2135 to attempt to generate a reloc which will then fail with the
2136 slightly more helpful error message: "Cannot represent
2137 relocation type BFD_RELOC_64". */
2138 return;
252b5132
RH
2139 default:
2140 abort ();
2141 }
94f592af
NC
2142
2143 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
2144 fixP->fx_done = 1;
252b5132
RH
2145}
2146
2147int
c85dd50d
NC
2148md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
2149 segT segment_type ATTRIBUTE_UNUSED)
252b5132 2150{
c85dd50d 2151 printf (_("call to md_estimate_size_before_relax \n"));
252b5132
RH
2152 abort ();
2153}
2154
70d6ecf3 2155/* Put number into target byte order. */
252b5132 2156void
b54a3392 2157md_number_to_chars (char *ptr, valueT use, int nbytes)
252b5132
RH
2158{
2159 number_to_chars_bigendian (ptr, use, nbytes);
2160}
70d6ecf3 2161
252b5132 2162long
b54a3392 2163md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED)
252b5132
RH
2164{
2165 abort ();
2166}
2167
f333765f 2168arelent *
b54a3392 2169tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
f333765f
JL
2170{
2171 arelent *rel;
2172 bfd_reloc_code_real_type r_type;
2173
de342d07
JL
2174 if (fixp->fx_addsy && fixp->fx_subsy)
2175 {
2176 if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy))
2177 || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section)
2178 {
2179 as_bad_where (fixp->fx_file, fixp->fx_line,
c85dd50d 2180 _("Difference of symbols in different sections is not supported"));
de342d07
JL
2181 return NULL;
2182 }
2183 }
2184
c85dd50d
NC
2185 rel = xmalloc (sizeof (arelent));
2186 rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
f333765f
JL
2187 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
2188 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
2189 rel->addend = fixp->fx_offset;
2190
2191 r_type = fixp->fx_r_type;
2192
2193#define DEBUG 0
2194#if DEBUG
2195 fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type));
c85dd50d 2196 fflush (stderr);
f333765f
JL
2197#endif
2198 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type);
2199 if (rel->howto == NULL)
2200 {
2201 as_bad_where (fixp->fx_file, fixp->fx_line,
2202 _("Cannot represent relocation type %s"),
2203 bfd_get_reloc_code_name (r_type));
2204 return NULL;
2205 }
2206
2207 return rel;
2208}
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