* gas/h8300/h8sx_disp2.[sd]: New test.
[deliverable/binutils-gdb.git] / gas / config / tc-h8300.c
CommitLineData
c2dcd04e 1/* tc-h8300.c -- Assemble code for the Renesas H8/300
cc8a6dd0 2 Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
c2dcd04e 3 2001, 2002, 2003 Free Software Foundation, Inc.
252b5132
RH
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
bc0d738a 22/* Written By Steve Chamberlain <sac@cygnus.com>. */
252b5132
RH
23
24#include <stdio.h>
25#include "as.h"
26#include "subsegs.h"
27#include "bfd.h"
2c8714f2
NC
28
29#ifdef BFD_ASSEMBLER
30#include "dwarf2dbg.h"
31#endif
32
252b5132
RH
33#define DEFINE_TABLE
34#define h8_opcodes ops
35#include "opcode/h8300.h"
3882b010 36#include "safe-ctype.h"
252b5132 37
7e0de7bf
JL
38#ifdef OBJ_ELF
39#include "elf/h8.h"
7e0de7bf
JL
40#endif
41
63a0b638 42const char comment_chars[] = ";";
252b5132 43const char line_comment_chars[] = "#";
63a0b638 44const char line_separator_chars[] = "";
252b5132 45
3048287a
NC
46void cons PARAMS ((int));
47void sbranch PARAMS ((int));
48void h8300hmode PARAMS ((int));
49void h8300smode PARAMS ((int));
8d9cd6b1
NC
50void h8300hnmode PARAMS ((int));
51void h8300snmode PARAMS ((int));
7ee7b84d 52void h8300sxmode PARAMS ((int));
3048287a 53static void pint PARAMS ((int));
252b5132
RH
54
55int Hmode;
56int Smode;
8d9cd6b1 57int Nmode;
7ee7b84d 58int SXmode;
3048287a 59
252b5132 60#define PSIZE (Hmode ? L_32 : L_16)
252b5132 61#define DSYMMODE (Hmode ? L_24 : L_16)
3048287a 62
c2dcd04e 63int bsize = L_8; /* Default branch displacement. */
252b5132 64
a720f7bc
KD
65struct h8_instruction
66{
67 int length;
68 int noperands;
69 int idx;
70 int size;
71 const struct h8_opcode *opcode;
72};
73
74struct h8_instruction *h8_instructions;
75
252b5132 76void
3048287a
NC
77h8300hmode (arg)
78 int arg ATTRIBUTE_UNUSED;
252b5132
RH
79{
80 Hmode = 1;
81 Smode = 0;
83e20b45
JL
82#ifdef BFD_ASSEMBLER
83 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h))
84 as_warn (_("could not set architecture and machine"));
85#endif
252b5132
RH
86}
87
88void
3048287a
NC
89h8300smode (arg)
90 int arg ATTRIBUTE_UNUSED;
252b5132
RH
91{
92 Smode = 1;
93 Hmode = 1;
83e20b45
JL
94#ifdef BFD_ASSEMBLER
95 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s))
96 as_warn (_("could not set architecture and machine"));
97#endif
252b5132 98}
70d6ecf3 99
8d9cd6b1
NC
100void
101h8300hnmode (arg)
102 int arg ATTRIBUTE_UNUSED;
103{
104 Hmode = 1;
105 Smode = 0;
106 Nmode = 1;
107#ifdef BFD_ASSEMBLER
108 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn))
109 as_warn (_("could not set architecture and machine"));
110#endif
111}
112
113void
114h8300snmode (arg)
115 int arg ATTRIBUTE_UNUSED;
116{
117 Smode = 1;
118 Hmode = 1;
119 Nmode = 1;
120#ifdef BFD_ASSEMBLER
121 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn))
122 as_warn (_("could not set architecture and machine"));
123#endif
124}
125
7ee7b84d
MS
126void
127h8300sxmode (arg)
128 int arg ATTRIBUTE_UNUSED;
129{
130 Smode = 1;
131 Hmode = 1;
132 SXmode = 1;
133#ifdef BFD_ASSEMBLER
134 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx))
135 as_warn (_("could not set architecture and machine"));
136#endif
137}
138
f4984206
RS
139void
140h8300sxnmode (arg)
141 int arg ATTRIBUTE_UNUSED;
142{
143 Smode = 1;
144 Hmode = 1;
145 SXmode = 1;
146 Nmode = 1;
147#ifdef BFD_ASSEMBLER
148 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn))
149 as_warn (_("could not set architecture and machine"));
150#endif
151}
152
252b5132
RH
153void
154sbranch (size)
155 int size;
156{
157 bsize = size;
158}
159
70d6ecf3 160static void
3048287a
NC
161pint (arg)
162 int arg ATTRIBUTE_UNUSED;
252b5132
RH
163{
164 cons (Hmode ? 4 : 2);
165}
166
3048287a
NC
167/* This table describes all the machine specific pseudo-ops the assembler
168 has to support. The fields are:
169 pseudo-op name without dot
170 function to call to execute this pseudo-op
171 Integer arg to pass to the function. */
172
252b5132
RH
173const pseudo_typeS md_pseudo_table[] =
174{
7ee7b84d 175 {"h8300h", h8300hmode, 0},
8d9cd6b1 176 {"h8300hn", h8300hnmode, 0},
7ee7b84d 177 {"h8300s", h8300smode, 0},
8d9cd6b1 178 {"h8300sn", h8300snmode, 0},
7ee7b84d 179 {"h8300sx", h8300sxmode, 0},
f4984206 180 {"h8300sxn", h8300sxnmode, 0},
252b5132
RH
181 {"sbranch", sbranch, L_8},
182 {"lbranch", sbranch, L_16},
183
184 {"int", pint, 0},
185 {"data.b", cons, 1},
186 {"data.w", cons, 2},
187 {"data.l", cons, 4},
188 {"form", listing_psize, 0},
189 {"heading", listing_title, 0},
7ee7b84d
MS
190 {"import", s_ignore, 0},
191 {"page", listing_eject, 0},
252b5132
RH
192 {"program", s_ignore, 0},
193 {0, 0, 0}
194};
195
196const int md_reloc_size;
197
198const char EXP_CHARS[] = "eE";
199
3048287a
NC
200/* Chars that mean this number is a floating point constant
201 As in 0f12.456
202 or 0d1.2345e12. */
252b5132
RH
203const char FLT_CHARS[] = "rRsSfFdDxXpP";
204
3048287a 205static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */
252b5132 206
70d6ecf3
AM
207/* This function is called once, at assembler startup time. This
208 should set up all the tables, etc. that the MD part of the assembler
209 needs. */
3048287a 210
252b5132
RH
211void
212md_begin ()
213{
a720f7bc 214 unsigned int nopcodes;
7ee7b84d 215 struct h8_opcode *p, *p1;
a720f7bc 216 struct h8_instruction *pi;
252b5132
RH
217 char prev_buffer[100];
218 int idx = 0;
219
83e20b45
JL
220#ifdef BFD_ASSEMBLER
221 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300))
222 as_warn (_("could not set architecture and machine"));
223#endif
224
252b5132
RH
225 opcode_hash_control = hash_new ();
226 prev_buffer[0] = 0;
227
a720f7bc
KD
228 nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode);
229
230 h8_instructions = (struct h8_instruction *)
231 xmalloc (nopcodes * sizeof (struct h8_instruction));
232
7ee7b84d
MS
233 pi = h8_instructions;
234 p1 = h8_opcodes;
235 /* We do a minimum amount of sorting on the opcode table; this is to
236 make it easy to describe the mova instructions without unnecessary
237 code duplication.
238 Sorting only takes place inside blocks of instructions of the form
239 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */
240 while (p1)
252b5132 241 {
7ee7b84d
MS
242 struct h8_opcode *first_skipped = 0;
243 int len, cmplen = 0;
244 char *src = p1->name;
245 char *dst, *buffer;
252b5132 246
7ee7b84d
MS
247 if (p1->name == 0)
248 break;
249 /* Strip off any . part when inserting the opcode and only enter
250 unique codes into the hash table. */
251 dst = buffer = malloc (strlen (src) + 1);
252b5132
RH
252 while (*src)
253 {
254 if (*src == '.')
255 {
256 src++;
252b5132
RH
257 break;
258 }
7ee7b84d
MS
259 if (*src == '/')
260 cmplen = src - p1->name + 1;
252b5132
RH
261 *dst++ = *src++;
262 }
7ee7b84d
MS
263 *dst = 0;
264 len = dst - buffer;
265 if (cmplen == 0)
266 cmplen = len;
267 hash_insert (opcode_hash_control, buffer, (char *) pi);
268 strcpy (prev_buffer, buffer);
269 idx++;
270
271 for (p = p1; p->name; p++)
252b5132 272 {
7ee7b84d
MS
273 /* A negative TIME is used to indicate that we've added this opcode
274 already. */
275 if (p->time == -1)
276 continue;
277 if (strncmp (p->name, buffer, cmplen) != 0
278 || (p->name[cmplen] != '\0' && p->name[cmplen] != '.'
279 && p->name[cmplen - 1] != '/'))
280 {
281 if (first_skipped == 0)
282 first_skipped = p;
283 break;
284 }
285 if (strncmp (p->name, buffer, len) != 0)
286 {
287 if (first_skipped == 0)
288 first_skipped = p;
289 continue;
290 }
291
292 p->time = -1;
293 pi->size = p->name[len] == '.' ? p->name[len + 1] : 0;
294 pi->idx = idx;
252b5132 295
7ee7b84d
MS
296 /* Find the number of operands. */
297 pi->noperands = 0;
298 while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E)
299 pi->noperands++;
70d6ecf3 300
7ee7b84d
MS
301 /* Find the length of the opcode in bytes. */
302 pi->length = 0;
303 while (p->data.nib[pi->length * 2] != (op_type) E)
304 pi->length++;
a720f7bc 305
7ee7b84d
MS
306 pi->opcode = p;
307 pi++;
308 }
309 p1 = first_skipped;
252b5132
RH
310 }
311
a720f7bc
KD
312 /* Add entry for the NULL vector terminator. */
313 pi->length = 0;
314 pi->noperands = 0;
315 pi->idx = 0;
316 pi->size = 0;
7ee7b84d 317 pi->opcode = 0;
a720f7bc 318
252b5132
RH
319 linkrelax = 1;
320}
321
252b5132
RH
322struct h8_exp
323{
324 char *e_beg;
325 char *e_end;
326 expressionS e_exp;
327};
70d6ecf3 328
252b5132
RH
329struct h8_op
330{
331 op_type mode;
332 unsigned reg;
333 expressionS exp;
334};
335
a720f7bc 336static void clever_message PARAMS ((const struct h8_instruction *, struct h8_op *));
d4ea8842 337static void fix_operand_size PARAMS ((struct h8_op *, int));
a720f7bc 338static void build_bytes PARAMS ((const struct h8_instruction *, struct h8_op *));
7ee7b84d 339static void do_a_fix_imm PARAMS ((int, int, struct h8_op *, int));
3048287a 340static void check_operand PARAMS ((struct h8_op *, unsigned int, char *));
a720f7bc 341static const struct h8_instruction * get_specific PARAMS ((const struct h8_instruction *, struct h8_op *, int));
3048287a 342static char * get_operands PARAMS ((unsigned, char *, struct h8_op *));
7ee7b84d 343static void get_operand PARAMS ((char **, struct h8_op *, int));
3048287a
NC
344static char * skip_colonthing PARAMS ((char *, expressionS *, int *));
345static char * parse_exp PARAMS ((char *, expressionS *));
346static int parse_reg PARAMS ((char *, op_type *, unsigned *, int));
347char * colonmod24 PARAMS ((struct h8_op *, char *));
348
7ee7b84d
MS
349static int constant_fits_width_p PARAMS ((struct h8_op *, unsigned int));
350static int constant_fits_size_p PARAMS ((struct h8_op *, int, int));
351
252b5132
RH
352/*
353 parse operands
354 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp
355 r0l,r0h,..r7l,r7h
356 @WREG
357 @WREG+
358 @-WREG
359 #const
360 ccr
361*/
362
bc0d738a
NC
363/* Try to parse a reg name. Return the number of chars consumed. */
364
40f09f82 365static int
252b5132
RH
366parse_reg (src, mode, reg, direction)
367 char *src;
368 op_type *mode;
369 unsigned int *reg;
370 int direction;
252b5132
RH
371{
372 char *end;
373 int len;
374
70d6ecf3 375 /* Cribbed from get_symbol_end. */
252b5132
RH
376 if (!is_name_beginner (*src) || *src == '\001')
377 return 0;
70d6ecf3 378 end = src + 1;
7ee7b84d 379 while ((is_part_of_name (*end) && *end != '.') || *end == '\001')
252b5132
RH
380 end++;
381 len = end - src;
382
7ee7b84d 383 if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p')
252b5132
RH
384 {
385 *mode = PSIZE | REG | direction;
386 *reg = 7;
387 return len;
388 }
7ee7b84d
MS
389 if (len == 3 &&
390 TOLOWER (src[0]) == 'c' &&
391 TOLOWER (src[1]) == 'c' &&
392 TOLOWER (src[2]) == 'r')
252b5132
RH
393 {
394 *mode = CCR;
395 *reg = 0;
396 return len;
397 }
7ee7b84d
MS
398 if (len == 3 &&
399 TOLOWER (src[0]) == 'e' &&
400 TOLOWER (src[1]) == 'x' &&
401 TOLOWER (src[2]) == 'r')
252b5132
RH
402 {
403 *mode = EXR;
7ee7b84d
MS
404 *reg = 1;
405 return len;
406 }
407 if (len == 3 &&
408 TOLOWER (src[0]) == 'v' &&
409 TOLOWER (src[1]) == 'b' &&
410 TOLOWER (src[2]) == 'r')
411 {
412 *mode = VBR;
413 *reg = 6;
414 return len;
415 }
416 if (len == 3 &&
417 TOLOWER (src[0]) == 's' &&
418 TOLOWER (src[1]) == 'b' &&
419 TOLOWER (src[2]) == 'r')
420 {
421 *mode = SBR;
422 *reg = 7;
252b5132
RH
423 return len;
424 }
7ee7b84d 425 if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p')
252b5132
RH
426 {
427 *mode = PSIZE | REG | direction;
428 *reg = 6;
429 return len;
430 }
7ee7b84d
MS
431 if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' &&
432 src[2] >= '0' && src[2] <= '7')
252b5132
RH
433 {
434 *mode = L_32 | REG | direction;
435 *reg = src[2] - '0';
436 if (!Hmode)
437 as_warn (_("Reg not valid for H8/300"));
438 return len;
439 }
7ee7b84d 440 if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7')
252b5132
RH
441 {
442 *mode = L_16 | REG | direction;
443 *reg = src[1] - '0' + 8;
444 if (!Hmode)
445 as_warn (_("Reg not valid for H8/300"));
446 return len;
447 }
448
7ee7b84d 449 if (TOLOWER (src[0]) == 'r')
252b5132
RH
450 {
451 if (src[1] >= '0' && src[1] <= '7')
452 {
7ee7b84d 453 if (len == 3 && TOLOWER (src[2]) == 'l')
252b5132
RH
454 {
455 *mode = L_8 | REG | direction;
456 *reg = (src[1] - '0') + 8;
457 return len;
458 }
7ee7b84d 459 if (len == 3 && TOLOWER (src[2]) == 'h')
252b5132
RH
460 {
461 *mode = L_8 | REG | direction;
462 *reg = (src[1] - '0');
463 return len;
464 }
465 if (len == 2)
466 {
467 *mode = L_16 | REG | direction;
468 *reg = (src[1] - '0');
469 return len;
470 }
471 }
472 }
473
474 return 0;
475}
476
40f09f82 477static char *
252b5132
RH
478parse_exp (s, op)
479 char *s;
70d6ecf3 480 expressionS *op;
252b5132
RH
481{
482 char *save = input_line_pointer;
483 char *new;
484
485 input_line_pointer = s;
486 expression (op);
487 if (op->X_op == O_absent)
488 as_bad (_("missing operand"));
489 new = input_line_pointer;
490 input_line_pointer = save;
491 return new;
492}
493
494static char *
495skip_colonthing (ptr, exp, mode)
496 char *ptr;
dbbc7809 497 expressionS *exp ATTRIBUTE_UNUSED;
252b5132
RH
498 int *mode;
499{
500 if (*ptr == ':')
501 {
502 ptr++;
503 *mode &= ~SIZE;
7ee7b84d
MS
504 if (ptr[0] == '8' && ! ISDIGIT (ptr[1]))
505 *mode |= L_8;
506 else if (ptr[0] == '2' && ! ISDIGIT (ptr[1]))
507 *mode |= L_2;
508 else if (ptr[0] == '3' && ! ISDIGIT (ptr[1]))
509 *mode |= L_3;
510 else if (ptr[0] == '4' && ! ISDIGIT (ptr[1]))
511 *mode |= L_4;
512 else if (ptr[0] == '5' && ! ISDIGIT (ptr[1]))
513 *mode |= L_5;
514 else if (ptr[0] == '2' && ptr[1] == '4')
515 *mode |= L_24;
516 else if (ptr[0] == '3' && ptr[1] == '2')
517 *mode |= L_32;
518 else if (ptr[0] == '1' && ptr[1] == '6')
519 *mode |= L_16;
252b5132 520 else
7ee7b84d
MS
521 as_bad (_("invalid operand size requested"));
522
523 while (ISDIGIT (*ptr))
524 ptr++;
252b5132
RH
525 }
526 return ptr;
527}
528
529/* The many forms of operand:
530
531 Rn Register direct
532 @Rn Register indirect
533 @(exp[:16], Rn) Register indirect with displacement
534 @Rn+
535 @-Rn
70d6ecf3
AM
536 @aa:8 absolute 8 bit
537 @aa:16 absolute 16 bit
252b5132
RH
538 @aa absolute 16 bit
539
540 #xx[:size] immediate data
70d6ecf3 541 @(exp:[8], pc) pc rel
3048287a 542 @@aa[:8] memory indirect. */
252b5132
RH
543
544char *
545colonmod24 (op, src)
546 struct h8_op *op;
547 char *src;
252b5132
RH
548{
549 int mode = 0;
550 src = skip_colonthing (src, &op->exp, &mode);
551
552 if (!mode)
553 {
d4ea8842
MS
554 /* If the operand is a 16-bit constant integer, leave fix_operand_size
555 to calculate its size. Otherwise choose a default here. */
252b5132
RH
556 if (op->exp.X_add_number < -32768
557 || op->exp.X_add_number > 32767)
558 {
559 if (Hmode)
560 mode = L_24;
561 else
562 mode = L_16;
563 }
564 else if (op->exp.X_add_symbol
565 || op->exp.X_op_symbol)
566 mode = DSYMMODE;
252b5132 567 }
3048287a 568
252b5132
RH
569 op->mode |= mode;
570 return src;
252b5132
RH
571}
572
7ee7b84d
MS
573static int
574constant_fits_width_p (operand, width)
575 struct h8_op *operand;
576 unsigned int width;
577{
578 return ((operand->exp.X_add_number & ~width) == 0
579 || (operand->exp.X_add_number | width) == (unsigned)(~0));
580}
581
582static int
583constant_fits_size_p (operand, size, no_symbols)
584 struct h8_op *operand;
585 int size, no_symbols;
586{
587 offsetT num = operand->exp.X_add_number;
588 if (no_symbols
589 && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0))
590 return 0;
591 switch (size)
592 {
593 case L_2:
594 return (num & ~3) == 0;
595 case L_3:
596 return (num & ~7) == 0;
597 case L_3NZ:
598 return num >= 1 && num < 8;
599 case L_4:
600 return (num & ~15) == 0;
601 case L_5:
602 return num >= 1 && num < 32;
603 case L_8:
604 return (num & ~0xFF) == 0 || ((unsigned)num | 0x7F) == ~0u;
605 case L_8U:
606 return (num & ~0xFF) == 0;
607 case L_16:
608 return (num & ~0xFFFF) == 0 || ((unsigned)num | 0x7FFF) == ~0u;
609 case L_16U:
610 return (num & ~0xFFFF) == 0;
611 case L_32:
612 return 1;
613 default:
614 abort ();
615 }
616}
617
252b5132 618static void
7ee7b84d 619get_operand (ptr, op, direction)
252b5132
RH
620 char **ptr;
621 struct h8_op *op;
252b5132
RH
622 int direction;
623{
624 char *src = *ptr;
625 op_type mode;
626 unsigned int num;
627 unsigned int len;
628
7ee7b84d 629 op->mode = 0;
252b5132 630
3048287a
NC
631 /* Check for '(' and ')' for instructions ldm and stm. */
632 if (src[0] == '(' && src[8] == ')')
633 ++ src;
634
252b5132
RH
635 /* Gross. Gross. ldm and stm have a format not easily handled
636 by get_operand. We deal with it explicitly here. */
7ee7b84d
MS
637 if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' &&
638 ISDIGIT (src[2]) && src[3] == '-' &&
639 TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6]))
252b5132
RH
640 {
641 int low, high;
642
643 low = src[2] - '0';
644 high = src[6] - '0';
645
7ee7b84d 646 if (high == low)
252b5132
RH
647 as_bad (_("Invalid register list for ldm/stm\n"));
648
7ee7b84d 649 if (high < low)
252b5132
RH
650 as_bad (_("Invalid register list for ldm/stm\n"));
651
652 if (high - low > 3)
7ee7b84d 653 as_bad (_("Invalid register list for ldm/stm)\n"));
252b5132
RH
654
655 /* Even sicker. We encode two registers into op->reg. One
656 for the low register to save, the other for the high
657 register to save; we also set the high bit in op->reg
658 so we know this is "very special". */
659 op->reg = 0x80000000 | (high << 8) | low;
660 op->mode = REG;
3048287a
NC
661 if (src[7] == ')')
662 *ptr = src + 8;
663 else
664 *ptr = src + 7;
252b5132
RH
665 return;
666 }
667
668 len = parse_reg (src, &op->mode, &op->reg, direction);
669 if (len)
670 {
7ee7b84d
MS
671 src += len;
672 if (*src == '.')
673 {
674 int size = op->mode & SIZE;
675 switch (src[1])
676 {
677 case 'l': case 'L':
678 if (size != L_32)
679 as_warn (_("mismatch between register and suffix"));
680 op->mode = (op->mode & ~MODE) | LOWREG;
681 break;
682 case 'w': case 'W':
683 if (size != L_32 && size != L_16)
684 as_warn (_("mismatch between register and suffix"));
685 op->mode = (op->mode & ~MODE) | LOWREG;
686 op->mode = (op->mode & ~SIZE) | L_16;
687 break;
688 case 'b': case 'B':
689 op->mode = (op->mode & ~MODE) | LOWREG;
690 if (size != L_32 && size != L_8)
691 as_warn (_("mismatch between register and suffix"));
692 op->mode = (op->mode & ~MODE) | LOWREG;
693 op->mode = (op->mode & ~SIZE) | L_8;
694 break;
695 default:
696 as_warn ("invalid suffix after register.");
697 break;
698 }
699 src += 2;
700 }
701 *ptr = src;
252b5132
RH
702 return;
703 }
704
705 if (*src == '@')
706 {
707 src++;
708 if (*src == '@')
709 {
710 src++;
711 src = parse_exp (src, &op->exp);
712
713 src = skip_colonthing (src, &op->exp, &op->mode);
714
715 *ptr = src;
716
7ee7b84d
MS
717 if (op->exp.X_add_number >= 0x100)
718 {
719 int divisor;
720
721 op->mode = VECIND;
722 /* FIXME : 2? or 4? */
723 if (op->exp.X_add_number >= 0x400)
724 as_bad (_("address too high for vector table jmp/jsr"));
725 else if (op->exp.X_add_number >= 0x200)
726 divisor = 4;
727 else
728 divisor = 2;
729
730 op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80;
731 }
732 else
733 op->mode = MEMIND;
734
252b5132 735 return;
252b5132
RH
736 }
737
7ee7b84d 738 if (*src == '-' || *src == '+')
252b5132 739 {
7ee7b84d 740 char c = *src;
252b5132
RH
741 src++;
742 len = parse_reg (src, &mode, &num, direction);
743 if (len == 0)
744 {
70d6ecf3 745 /* Oops, not a reg after all, must be ordinary exp. */
252b5132 746 src--;
70d6ecf3 747 /* Must be a symbol. */
252b5132
RH
748 op->mode = ABS | PSIZE | direction;
749 *ptr = skip_colonthing (parse_exp (src, &op->exp),
750 &op->exp, &op->mode);
751
752 return;
252b5132
RH
753 }
754
252b5132
RH
755 if ((mode & SIZE) != PSIZE)
756 as_bad (_("Wrong size pointer register for architecture."));
7ee7b84d 757 op->mode = c == '-' ? RDPREDEC : RDPREINC;
252b5132
RH
758 op->reg = num;
759 *ptr = src + len;
760 return;
761 }
762 if (*src == '(')
763 {
252b5132
RH
764 src++;
765
7ee7b84d
MS
766 /* See if this is @(ERn.x, PC). */
767 len = parse_reg (src, &mode, &op->reg, direction);
768 if (len != 0 && (mode & MODE) == REG && src[len] == '.')
769 {
770 switch (TOLOWER (src[len + 1]))
771 {
772 case 'b':
773 mode = PCIDXB | direction;
774 break;
775 case 'w':
776 mode = PCIDXW | direction;
777 break;
778 case 'l':
779 mode = PCIDXL | direction;
780 break;
781 default:
782 mode = 0;
783 break;
784 }
785 if (mode
786 && src[len + 2] == ','
787 && TOLOWER (src[len + 3]) != 'p'
788 && TOLOWER (src[len + 4]) != 'c'
789 && src[len + 5] != ')')
790 {
791 *ptr = src + len + 6;
792 op->mode |= mode;
793 return;
794 }
795 /* Fall through into disp case - the grammar is somewhat
796 ambiguous, so we should try whether it's a DISP operand
797 after all ("ER3.L" might be a poorly named label...). */
798 }
799
800 /* Disp. */
801
70d6ecf3 802 /* Start off assuming a 16 bit offset. */
252b5132
RH
803
804 src = parse_exp (src, &op->exp);
805
806 src = colonmod24 (op, src);
807
808 if (*src == ')')
809 {
810 src++;
811 op->mode |= ABS | direction;
812 *ptr = src;
813 return;
814 }
815
816 if (*src != ',')
817 {
818 as_bad (_("expected @(exp, reg16)"));
819 return;
820
821 }
822 src++;
823
824 len = parse_reg (src, &mode, &op->reg, direction);
7ee7b84d 825 if (len == 0 || (mode & MODE) != REG)
252b5132
RH
826 {
827 as_bad (_("expected @(exp, reg16)"));
828 return;
829 }
252b5132 830 src += len;
7ee7b84d
MS
831 if (src[0] == '.')
832 {
833 switch (TOLOWER (src[1]))
834 {
835 case 'b':
836 op->mode |= INDEXB | direction;
837 break;
838 case 'w':
839 op->mode |= INDEXW | direction;
840 break;
841 case 'l':
842 op->mode |= INDEXL | direction;
843 break;
844 default:
845 as_bad (_("expected .L, .W or .B for register in indexed addressing mode"));
846 }
847 src += 2;
848 op->reg &= 7;
849 }
850 else
851 op->mode |= DISP | direction;
252b5132
RH
852 src = skip_colonthing (src, &op->exp, &op->mode);
853
854 if (*src != ')' && '(')
855 {
856 as_bad (_("expected @(exp, reg16)"));
857 return;
858 }
859 *ptr = src + 1;
860
861 return;
862 }
863 len = parse_reg (src, &mode, &num, direction);
864
865 if (len)
866 {
867 src += len;
7ee7b84d 868 if (*src == '+' || *src == '-')
252b5132 869 {
252b5132
RH
870 if ((mode & SIZE) != PSIZE)
871 as_bad (_("Wrong size pointer register for architecture."));
7ee7b84d 872 op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC;
252b5132 873 op->reg = num;
7ee7b84d 874 src++;
252b5132
RH
875 *ptr = src;
876 return;
877 }
878 if ((mode & SIZE) != PSIZE)
879 as_bad (_("Wrong size pointer register for architecture."));
880
881 op->mode = direction | IND | PSIZE;
882 op->reg = num;
883 *ptr = src;
884
885 return;
886 }
887 else
888 {
889 /* must be a symbol */
890
891 op->mode = ABS | direction;
892 src = parse_exp (src, &op->exp);
893
894 *ptr = colonmod24 (op, src);
895
896 return;
897 }
898 }
899
252b5132
RH
900 if (*src == '#')
901 {
902 src++;
903 op->mode = IMM;
904 src = parse_exp (src, &op->exp);
905 *ptr = skip_colonthing (src, &op->exp, &op->mode);
906
907 return;
908 }
7ee7b84d
MS
909 else if (strncmp (src, "mach", 4) == 0 ||
910 strncmp (src, "macl", 4) == 0 ||
911 strncmp (src, "MACH", 4) == 0 ||
912 strncmp (src, "MACL", 4) == 0)
252b5132 913 {
7ee7b84d 914 op->reg = TOLOWER (src[3]) == 'l';
252b5132
RH
915 op->mode = MACREG;
916 *ptr = src + 4;
917 return;
918 }
919 else
920 {
921 src = parse_exp (src, &op->exp);
922 /* Trailing ':' size ? */
923 if (*src == ':')
924 {
925 if (src[1] == '1' && src[2] == '6')
926 {
927 op->mode = PCREL | L_16;
928 src += 3;
929 }
930 else if (src[1] == '8')
931 {
932 op->mode = PCREL | L_8;
933 src += 2;
934 }
935 else
3048287a 936 as_bad (_("expect :8 or :16 here"));
252b5132
RH
937 }
938 else
7ee7b84d
MS
939 {
940 int val = op->exp.X_add_number;
941
942 op->mode = PCREL;
943 if (-128 < val && val < 127)
944 op->mode |= L_8;
945 else
946 op->mode |= L_16;
947 }
3048287a 948
252b5132
RH
949 *ptr = src;
950 }
951}
952
70d6ecf3 953static char *
252b5132
RH
954get_operands (noperands, op_end, operand)
955 unsigned int noperands;
956 char *op_end;
957 struct h8_op *operand;
958{
959 char *ptr = op_end;
960
961 switch (noperands)
962 {
963 case 0:
252b5132
RH
964 break;
965
966 case 1:
967 ptr++;
7ee7b84d 968 get_operand (&ptr, operand + 0, SRC);
252b5132
RH
969 if (*ptr == ',')
970 {
971 ptr++;
7ee7b84d 972 get_operand (&ptr, operand + 1, DST);
252b5132 973 }
252b5132 974 break;
70d6ecf3 975
252b5132
RH
976 case 2:
977 ptr++;
7ee7b84d 978 get_operand (&ptr, operand + 0, SRC);
252b5132
RH
979 if (*ptr == ',')
980 ptr++;
7ee7b84d
MS
981 get_operand (&ptr, operand + 1, DST);
982 break;
983
984 case 3:
985 ptr++;
986 get_operand (&ptr, operand + 0, SRC);
987 if (*ptr == ',')
988 ptr++;
989 get_operand (&ptr, operand + 1, DST);
990 if (*ptr == ',')
991 ptr++;
992 get_operand (&ptr, operand + 2, OP3);
252b5132
RH
993 break;
994
995 default:
996 abort ();
997 }
998
252b5132
RH
999 return ptr;
1000}
1001
7ee7b84d
MS
1002/* MOVA has special requirements. Rather than adding twice the amount of
1003 addressing modes, we simply special case it a bit. */
1004static void
1005get_mova_operands (char *op_end, struct h8_op *operand)
1006{
1007 char *ptr = op_end;
1008
1009 if (ptr[1] != '@' || ptr[2] != '(')
1010 goto error;
1011 ptr += 3;
1012 operand[0].mode = 0;
1013 ptr = parse_exp (ptr, &operand[0].exp);
1014 ptr = colonmod24 (operand + 0, ptr);
1015
1016 if (*ptr !=',')
1017 goto error;
1018 ptr++;
1019 get_operand (&ptr, operand + 1, DST);
1020
1021 if (*ptr =='.')
1022 {
1023 ptr++;
1024 switch (*ptr++)
1025 {
1026 case 'b': case 'B':
1027 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB;
1028 break;
1029 case 'w': case 'W':
1030 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW;
1031 break;
1032 case 'l': case 'L':
1033 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL;
1034 break;
1035 default:
1036 goto error;
1037 }
1038 }
1039 else if ((operand[1].mode & MODE) == LOWREG)
1040 {
1041 switch (operand[1].mode & SIZE)
1042 {
1043 case L_8:
1044 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB;
1045 break;
1046 case L_16:
1047 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW;
1048 break;
1049 case L_32:
1050 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL;
1051 break;
1052 default:
1053 goto error;
1054 }
1055 }
1056 else
1057 goto error;
1058
1059 if (*ptr++ != ')' || *ptr++ != ',')
1060 goto error;
1061 get_operand (&ptr, operand + 2, OP3);
1062 /* See if we can use the short form of MOVA. */
1063 if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG)
1064 && (operand[2].mode & MODE) == REG
1065 && (operand[1].reg & 7) == (operand[2].reg & 7))
1066 {
1067 operand[1].mode = operand[2].mode = 0;
1068 operand[0].reg = operand[2].reg & 7;
1069 }
1070 return;
1071
1072 error:
1073 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\""));
1074 return;
1075}
1076
1077static void
1078get_rtsl_operands (char *ptr, struct h8_op *operand)
1079{
1080 int mode, num, num2, len, type = 0;
1081
1082 ptr++;
1083 if (*ptr == '(')
1084 {
1085 ptr++;
1086 type = 1;
1087 }
1088 len = parse_reg (ptr, &mode, &num, SRC);
1089 if (len == 0 || (mode & MODE) != REG)
1090 {
1091 as_bad (_("expected register"));
1092 return;
1093 }
1094 if (type == 1)
1095 {
1096 ptr += len;
1097 if (*ptr++ != '-')
1098 {
1099 as_bad (_("expected register list"));
1100 return;
1101 }
1102 len = parse_reg (ptr, &mode, &num2, SRC);
1103 if (len == 0 || (mode & MODE) != REG)
1104 {
1105 as_bad (_("expected register"));
1106 return;
1107 }
1108 ptr += len;
1109 if (*ptr++ != ')')
1110 {
1111 as_bad (_("expected closing paren"));
1112 return;
1113 }
1114 /* CONST_xxx are used as placeholders in the opcode table. */
1115 num = num2 - num;
1116 if (num < 1 || num > 3)
1117 {
1118 as_bad (_("invalid register list"));
1119 return;
1120 }
1121 }
1122 else
1123 num2 = num, num = 0;
1124 operand[0].mode = RS32;
1125 operand[1].mode = RD32;
1126 operand[0].reg = num;
1127 operand[1].reg = num2;
1128}
1129
252b5132
RH
1130/* Passed a pointer to a list of opcodes which use different
1131 addressing modes, return the opcode which matches the opcodes
70d6ecf3 1132 provided. */
3048287a 1133
a720f7bc
KD
1134static const struct h8_instruction *
1135get_specific (instruction, operands, size)
1136 const struct h8_instruction *instruction;
252b5132
RH
1137 struct h8_op *operands;
1138 int size;
1139{
a720f7bc 1140 const struct h8_instruction *this_try = instruction;
7ee7b84d 1141 const struct h8_instruction *found_other = 0, *found_mismatched = 0;
252b5132 1142 int found = 0;
a720f7bc 1143 int this_index = instruction->idx;
7ee7b84d 1144 int noperands = 0;
252b5132
RH
1145
1146 /* There's only one ldm/stm and it's easier to just
1147 get out quick for them. */
7ee7b84d
MS
1148 if (OP_KIND (instruction->opcode->how) == O_LDM
1149 || OP_KIND (instruction->opcode->how) == O_STM)
252b5132
RH
1150 return this_try;
1151
7ee7b84d
MS
1152 while (noperands < 3 && operands[noperands].mode != 0)
1153 noperands++;
1154
a720f7bc 1155 while (this_index == instruction->idx && !found)
252b5132 1156 {
7ee7b84d 1157 int this_size;
252b5132 1158
7ee7b84d 1159 found = 1;
a720f7bc 1160 this_try = instruction++;
7ee7b84d 1161 this_size = this_try->opcode->how & SN;
252b5132 1162
7ee7b84d
MS
1163 if (this_try->noperands != noperands)
1164 found = 0;
1165 else if (this_try->noperands > 0)
252b5132 1166 {
3048287a 1167 int i;
252b5132
RH
1168
1169 for (i = 0; i < this_try->noperands && found; i++)
1170 {
a720f7bc 1171 op_type op = this_try->opcode->args.nib[i];
7ee7b84d
MS
1172 int op_mode = op & MODE;
1173 int op_size = op & SIZE;
252b5132 1174 int x = operands[i].mode;
7ee7b84d
MS
1175 int x_mode = x & MODE;
1176 int x_size = x & SIZE;
252b5132 1177
7ee7b84d 1178 if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG))
252b5132 1179 {
7ee7b84d
MS
1180 if ((x_size == L_8 && (operands[i].reg & 8) == 0)
1181 || (x_size == L_16 && (operands[i].reg & 8) == 8))
1182 as_warn (_("can't use high part of register in operand %d"), i);
1183
1184 if (x_size != op_size)
1185 found = 0;
252b5132 1186 }
7ee7b84d 1187 else if (op_mode == REG)
252b5132 1188 {
7ee7b84d
MS
1189 if (x_mode == LOWREG)
1190 x_mode = REG;
1191 if (x_mode != REG)
252b5132
RH
1192 found = 0;
1193
7ee7b84d
MS
1194 if (x_size == L_P)
1195 x_size = (Hmode ? L_32 : L_16);
1196 if (op_size == L_P)
1197 op_size = (Hmode ? L_32 : L_16);
252b5132 1198
70d6ecf3 1199 /* The size of the reg is v important. */
7ee7b84d 1200 if (op_size != x_size)
252b5132
RH
1201 found = 0;
1202 }
7ee7b84d 1203 else if (op_mode & CTRL) /* control register */
252b5132 1204 {
7ee7b84d
MS
1205 if (!(x_mode & CTRL))
1206 found = 0;
1207
1208 switch (x_mode)
1209 {
1210 case CCR:
1211 if (op_mode != CCR &&
1212 op_mode != CCR_EXR &&
1213 op_mode != CC_EX_VB_SB)
1214 found = 0;
1215 break;
1216 case EXR:
1217 if (op_mode != EXR &&
1218 op_mode != CCR_EXR &&
1219 op_mode != CC_EX_VB_SB)
1220 found = 0;
1221 break;
1222 case MACH:
1223 if (op_mode != MACH &&
1224 op_mode != MACREG)
1225 found = 0;
1226 break;
1227 case MACL:
1228 if (op_mode != MACL &&
1229 op_mode != MACREG)
1230 found = 0;
1231 break;
1232 case VBR:
1233 if (op_mode != VBR &&
1234 op_mode != VBR_SBR &&
1235 op_mode != CC_EX_VB_SB)
1236 found = 0;
1237 break;
1238 case SBR:
1239 if (op_mode != SBR &&
1240 op_mode != VBR_SBR &&
1241 op_mode != CC_EX_VB_SB)
1242 found = 0;
1243 break;
1244 }
1245 }
1246 else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL))
1247 {
1248 operands[i].mode &= ~MODE;
252b5132 1249 operands[i].mode |= ABSJMP;
70d6ecf3 1250 /* But it may not be 24 bits long. */
7ee7b84d 1251 if (x_mode == ABS && !Hmode)
252b5132
RH
1252 {
1253 operands[i].mode &= ~SIZE;
1254 operands[i].mode |= L_16;
1255 }
7ee7b84d
MS
1256 if ((operands[i].mode & SIZE) == L_32
1257 && (op_mode & SIZE) != L_32)
1258 found = 0;
252b5132 1259 }
7ee7b84d 1260 else if (x_mode == IMM && op_mode != IMM)
252b5132 1261 {
7ee7b84d
MS
1262 offsetT num = operands[i].exp.X_add_number;
1263 if (op_mode == KBIT || op_mode == DBIT)
1264 /* This is ok if the immediate value is sensible. */;
1265 else if (op_mode == CONST_2)
1266 found = num == 2;
1267 else if (op_mode == CONST_4)
1268 found = num == 4;
1269 else if (op_mode == CONST_8)
1270 found = num == 8;
1271 else if (op_mode == CONST_16)
1272 found = num == 16;
1273 else
1274 found = 0;
252b5132 1275 }
7ee7b84d 1276 else if (op_mode == PCREL && op_mode == x_mode)
252b5132 1277 {
7ee7b84d
MS
1278 /* movsd only comes in PCREL16 flavour:
1279 If x_size is L_8, promote it. */
1280 if (OP_KIND (this_try->opcode->how) == O_MOVSD)
1281 if (x_size == L_8)
1282 x_size = L_16;
1283
70d6ecf3 1284 /* The size of the displacement is important. */
7ee7b84d 1285 if (op_size != x_size)
252b5132
RH
1286 found = 0;
1287 }
7ee7b84d
MS
1288 else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS
1289 || op_mode == INDEXB || op_mode == INDEXW
1290 || op_mode == INDEXL)
1291 && op_mode == x_mode)
252b5132
RH
1292 {
1293 /* Promote a L_24 to L_32 if it makes us match. */
7ee7b84d 1294 if (x_size == L_24 && op_size == L_32)
252b5132 1295 {
7ee7b84d
MS
1296 x &= ~SIZE;
1297 x |= x_size = L_32;
252b5132 1298 }
7ee7b84d
MS
1299
1300#if 0 /* ??? */
252b5132 1301 /* Promote an L8 to L_16 if it makes us match. */
7ee7b84d 1302 if ((op_mode == ABS || op_mode == DISP) && x_size == L_8)
252b5132 1303 {
7ee7b84d
MS
1304 if (op_size == L_16)
1305 x_size = L_16;
252b5132 1306 }
7ee7b84d
MS
1307#endif
1308
1309 if (((x_size == L_16 && op_size == L_16U)
1310 || (x_size == L_3 && op_size == L_3NZ))
1311 /* We're deliberately more permissive for ABS modes. */
1312 && (op_mode == ABS
1313 || constant_fits_size_p (operands + i, op_size,
1314 op & NO_SYMBOLS)))
1315 x_size = op_size;
1316
1317 if (x_size != 0 && op_size != x_size)
1318 found = 0;
1319 else if (x_size == 0
1320 && ! constant_fits_size_p (operands + i, op_size,
1321 op & NO_SYMBOLS))
252b5132
RH
1322 found = 0;
1323 }
7ee7b84d 1324 else if (op_mode != x_mode)
252b5132
RH
1325 {
1326 found = 0;
70d6ecf3 1327 }
252b5132
RH
1328 }
1329 }
7ee7b84d
MS
1330 if (found)
1331 {
1332 if ((this_try->opcode->available == AV_H8SX && ! SXmode)
d4ea8842 1333 || (this_try->opcode->available == AV_H8S && ! Smode)
7ee7b84d
MS
1334 || (this_try->opcode->available == AV_H8H && ! Hmode))
1335 found = 0, found_other = this_try;
1336 else if (this_size != size && (this_size != SN && size != SN))
1337 found_mismatched = this_try, found = 0;
1338
1339 }
252b5132
RH
1340 }
1341 if (found)
1342 return this_try;
7ee7b84d
MS
1343 if (found_other)
1344 {
1345 as_warn (_("Opcode `%s' with these operand types not available in %s mode"),
1346 found_other->opcode->name,
1347 (! Hmode && ! Smode ? "H8/300"
1348 : SXmode ? "H8sx"
1349 : Smode ? "H8/300S"
1350 : "H8/300H"));
1351 }
1352 else if (found_mismatched)
1353 {
1354 as_warn (_("mismatch between opcode size and operand size"));
1355 return found_mismatched;
1356 }
1357 return 0;
252b5132
RH
1358}
1359
1360static void
1361check_operand (operand, width, string)
1362 struct h8_op *operand;
1363 unsigned int width;
1364 char *string;
1365{
1366 if (operand->exp.X_add_symbol == 0
1367 && operand->exp.X_op_symbol == 0)
1368 {
70d6ecf3
AM
1369 /* No symbol involved, let's look at offset, it's dangerous if
1370 any of the high bits are not 0 or ff's, find out by oring or
1371 anding with the width and seeing if the answer is 0 or all
1372 fs. */
252b5132 1373
7ee7b84d 1374 if (! constant_fits_width_p (operand, width))
252b5132 1375 {
70d6ecf3 1376 if (width == 255
252b5132
RH
1377 && (operand->exp.X_add_number & 0xff00) == 0xff00)
1378 {
1379 /* Just ignore this one - which happens when trying to
1380 fit a 16 bit address truncated into an 8 bit address
1381 of something like bset. */
1382 }
166e23f9
KH
1383 else if (strcmp (string, "@") == 0
1384 && width == 0xffff
1385 && (operand->exp.X_add_number & 0xff8000) == 0xff8000)
1386 {
1387 /* Just ignore this one - which happens when trying to
1388 fit a 24 bit address truncated into a 16 bit address
1389 of something like mov.w. */
1390 }
70d6ecf3 1391 else
252b5132
RH
1392 {
1393 as_warn (_("operand %s0x%lx out of range."), string,
1394 (unsigned long) operand->exp.X_add_number);
1395 }
1396 }
1397 }
252b5132
RH
1398}
1399
1400/* RELAXMODE has one of 3 values:
1401
1402 0 Output a "normal" reloc, no relaxing possible for this insn/reloc
1403
1404 1 Output a relaxable 24bit absolute mov.w address relocation
1405 (may relax into a 16bit absolute address).
1406
1407 2 Output a relaxable 16/24 absolute mov.b address relocation
1408 (may relax into an 8bit absolute address). */
1409
1410static void
7ee7b84d
MS
1411do_a_fix_imm (offset, nibble, operand, relaxmode)
1412 int offset, nibble;
252b5132
RH
1413 struct h8_op *operand;
1414 int relaxmode;
1415{
1416 int idx;
1417 int size;
1418 int where;
7ee7b84d 1419 char *bytes = frag_now->fr_literal + offset;
252b5132 1420
7ee7b84d 1421 char *t = ((operand->mode & MODE) == IMM) ? "#" : "@";
252b5132
RH
1422
1423 if (operand->exp.X_add_symbol == 0)
1424 {
252b5132
RH
1425 switch (operand->mode & SIZE)
1426 {
1427 case L_2:
1428 check_operand (operand, 0x3, t);
7ee7b84d 1429 bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4);
252b5132
RH
1430 break;
1431 case L_3:
7ee7b84d 1432 case L_3NZ:
252b5132 1433 check_operand (operand, 0x7, t);
7ee7b84d
MS
1434 bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4);
1435 break;
1436 case L_4:
1437 check_operand (operand, 0xF, t);
1438 bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4);
1439 break;
1440 case L_5:
1441 check_operand (operand, 0x1F, t);
1442 bytes[0] |= operand->exp.X_add_number & 31;
252b5132
RH
1443 break;
1444 case L_8:
7ee7b84d 1445 case L_8U:
252b5132 1446 check_operand (operand, 0xff, t);
7ee7b84d 1447 bytes[0] |= operand->exp.X_add_number;
252b5132
RH
1448 break;
1449 case L_16:
7ee7b84d 1450 case L_16U:
252b5132 1451 check_operand (operand, 0xffff, t);
7ee7b84d
MS
1452 bytes[0] |= operand->exp.X_add_number >> 8;
1453 bytes[1] |= operand->exp.X_add_number >> 0;
252b5132
RH
1454 break;
1455 case L_24:
1456 check_operand (operand, 0xffffff, t);
7ee7b84d
MS
1457 bytes[0] |= operand->exp.X_add_number >> 16;
1458 bytes[1] |= operand->exp.X_add_number >> 8;
1459 bytes[2] |= operand->exp.X_add_number >> 0;
252b5132
RH
1460 break;
1461
1462 case L_32:
70d6ecf3 1463 /* This should be done with bfd. */
7ee7b84d
MS
1464 bytes[0] |= operand->exp.X_add_number >> 24;
1465 bytes[1] |= operand->exp.X_add_number >> 16;
1466 bytes[2] |= operand->exp.X_add_number >> 8;
1467 bytes[3] |= operand->exp.X_add_number >> 0;
4132022d
AM
1468 if (relaxmode != 0)
1469 {
1470 idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1;
1471 fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx);
1472 }
252b5132
RH
1473 break;
1474 }
252b5132
RH
1475 }
1476 else
1477 {
1478 switch (operand->mode & SIZE)
1479 {
252b5132
RH
1480 case L_24:
1481 case L_32:
1482 size = 4;
1483 where = (operand->mode & SIZE) == L_24 ? -1 : 0;
1484 if (relaxmode == 2)
1485 idx = R_MOV24B1;
1486 else if (relaxmode == 1)
1487 idx = R_MOVL1;
1488 else
1489 idx = R_RELLONG;
1490 break;
1491 default:
70d6ecf3 1492 as_bad (_("Can't work out size of operand.\n"));
252b5132 1493 case L_16:
7ee7b84d 1494 case L_16U:
252b5132
RH
1495 size = 2;
1496 where = 0;
1497 if (relaxmode == 2)
1498 idx = R_MOV16B1;
1499 else
1500 idx = R_RELWORD;
4132022d
AM
1501 operand->exp.X_add_number =
1502 ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000;
7ee7b84d 1503 operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1];
252b5132
RH
1504 break;
1505 case L_8:
1506 size = 1;
1507 where = 0;
1508 idx = R_RELBYTE;
4132022d
AM
1509 operand->exp.X_add_number =
1510 ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80;
7ee7b84d 1511 operand->exp.X_add_number |= bytes[0];
252b5132
RH
1512 }
1513
1514 fix_new_exp (frag_now,
1515 offset + where,
1516 size,
1517 &operand->exp,
1518 0,
1519 idx);
1520 }
252b5132
RH
1521}
1522
70d6ecf3 1523/* Now we know what sort of opcodes it is, let's build the bytes. */
3048287a 1524
252b5132
RH
1525static void
1526build_bytes (this_try, operand)
a720f7bc 1527 const struct h8_instruction *this_try;
252b5132
RH
1528 struct h8_op *operand;
1529{
3048287a 1530 int i;
252b5132 1531 char *output = frag_more (this_try->length);
a720f7bc 1532 op_type *nibble_ptr = this_try->opcode->data.nib;
252b5132
RH
1533 op_type c;
1534 unsigned int nibble_count = 0;
7ee7b84d 1535 int op_at[3];
3048287a 1536 int nib = 0;
252b5132 1537 int movb = 0;
7ee7b84d 1538 char asnibbles[100];
252b5132 1539 char *p = asnibbles;
7ee7b84d 1540 int high, low;
252b5132 1541
d4ea8842 1542 if (!Hmode && this_try->opcode->available != AV_H8)
252b5132 1543 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"),
a720f7bc 1544 this_try->opcode->name);
d4ea8842
MS
1545 else if (!Smode
1546 && this_try->opcode->available != AV_H8
1547 && this_try->opcode->available != AV_H8H)
1548 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"),
1549 this_try->opcode->name);
1550 else if (!SXmode
1551 && this_try->opcode->available != AV_H8
1552 && this_try->opcode->available != AV_H8H
1553 && this_try->opcode->available != AV_H8S)
1554 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"),
1555 this_try->opcode->name);
252b5132 1556
7ee7b84d 1557 while (*nibble_ptr != (op_type) E)
252b5132
RH
1558 {
1559 int d;
7ee7b84d
MS
1560
1561 nib = 0;
252b5132
RH
1562 c = *nibble_ptr++;
1563
7ee7b84d 1564 d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0;
252b5132
RH
1565
1566 if (c < 16)
3048287a 1567 nib = c;
252b5132
RH
1568 else
1569 {
7ee7b84d
MS
1570 int c2 = c & MODE;
1571
1572 if (c2 == REG || c2 == LOWREG
1573 || c2 == IND || c2 == PREINC || c2 == PREDEC
1574 || c2 == POSTINC || c2 == POSTDEC)
1575 {
1576 nib = operand[d].reg;
1577 if (c2 == LOWREG)
1578 nib &= 7;
1579 }
1580
1581 else if (c & CTRL) /* Control reg operand. */
3048287a
NC
1582 nib = operand[d].reg;
1583
252b5132 1584 else if ((c & DISPREG) == (DISPREG))
7ee7b84d
MS
1585 {
1586 nib = operand[d].reg;
1587 }
1588 else if (c2 == ABS)
252b5132
RH
1589 {
1590 operand[d].mode = c;
7ee7b84d 1591 op_at[d] = nibble_count;
252b5132
RH
1592 nib = 0;
1593 }
7ee7b84d
MS
1594 else if (c2 == IMM || c2 == PCREL || c2 == ABS
1595 || (c & ABSJMP) || c2 == DISP)
252b5132
RH
1596 {
1597 operand[d].mode = c;
7ee7b84d 1598 op_at[d] = nibble_count;
252b5132
RH
1599 nib = 0;
1600 }
7ee7b84d 1601 else if ((c & IGNORE) || (c & DATA))
3048287a
NC
1602 nib = 0;
1603
7ee7b84d 1604 else if (c2 == DBIT)
252b5132
RH
1605 {
1606 switch (operand[0].exp.X_add_number)
1607 {
1608 case 1:
1609 nib = c;
1610 break;
1611 case 2:
1612 nib = 0x8 | c;
1613 break;
1614 default:
1615 as_bad (_("Need #1 or #2 here"));
1616 }
1617 }
7ee7b84d 1618 else if (c2 == KBIT)
252b5132
RH
1619 {
1620 switch (operand[0].exp.X_add_number)
1621 {
1622 case 1:
1623 nib = 0;
1624 break;
1625 case 2:
1626 nib = 8;
1627 break;
1628 case 4:
1629 if (!Hmode)
1630 as_warn (_("#4 not valid on H8/300."));
1631 nib = 9;
1632 break;
1633
1634 default:
1635 as_bad (_("Need #1 or #2 here"));
1636 break;
1637 }
70d6ecf3 1638 /* Stop it making a fix. */
252b5132
RH
1639 operand[0].mode = 0;
1640 }
1641
1642 if (c & MEMRELAX)
3048287a 1643 operand[d].mode |= MEMRELAX;
252b5132
RH
1644
1645 if (c & B31)
3048287a 1646 nib |= 0x8;
252b5132 1647
7ee7b84d
MS
1648 if (c & B21)
1649 nib |= 0x4;
1650
1651 if (c & B11)
1652 nib |= 0x2;
1653
1654 if (c & B01)
1655 nib |= 0x1;
1656
1657 if (c2 == MACREG)
252b5132 1658 {
f0c56b90
NC
1659 if (operand[0].mode == MACREG)
1660 /* stmac has mac[hl] as the first operand. */
1661 nib = 2 + operand[0].reg;
1662 else
1663 /* ldmac has mac[hl] as the second operand. */
1664 nib = 2 + operand[1].reg;
252b5132
RH
1665 }
1666 }
1667 nibble_count++;
1668
1669 *p++ = nib;
1670 }
1671
1672 /* Disgusting. Why, oh why didn't someone ask us for advice
1673 on the assembler format. */
7ee7b84d 1674 if (OP_KIND (this_try->opcode->how) == O_LDM)
252b5132 1675 {
7ee7b84d
MS
1676 high = (operand[1].reg >> 8) & 0xf;
1677 low = (operand[1].reg) & 0xf;
252b5132 1678 asnibbles[2] = high - low;
7ee7b84d
MS
1679 asnibbles[7] = high;
1680 }
1681 else if (OP_KIND (this_try->opcode->how) == O_STM)
1682 {
1683 high = (operand[0].reg >> 8) & 0xf;
1684 low = (operand[0].reg) & 0xf;
1685 asnibbles[2] = high - low;
1686 asnibbles[7] = low;
252b5132
RH
1687 }
1688
1689 for (i = 0; i < this_try->length; i++)
3048287a 1690 output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1];
252b5132
RH
1691
1692 /* Note if this is a movb instruction -- there's a special relaxation
1693 which only applies to them. */
7ee7b84d 1694 if (this_try->opcode->how == O (O_MOV, SB))
252b5132
RH
1695 movb = 1;
1696
70d6ecf3 1697 /* Output any fixes. */
7ee7b84d 1698 for (i = 0; i < this_try->noperands; i++)
252b5132
RH
1699 {
1700 int x = operand[i].mode;
7ee7b84d 1701 int x_mode = x & MODE;
252b5132 1702
7ee7b84d
MS
1703 if (x_mode == IMM || x_mode == DISP)
1704 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2,
1705 op_at[i] & 1, operand + i, (x & MEMRELAX) != 0);
3048287a 1706
7ee7b84d
MS
1707 else if (x_mode == ABS)
1708 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2,
1709 op_at[i] & 1, operand + i,
1710 (x & MEMRELAX) ? movb + 1 : 0);
3048287a 1711
7ee7b84d 1712 else if (x_mode == PCREL)
252b5132 1713 {
7ee7b84d 1714 int size16 = (x & SIZE) == L_16;
252b5132
RH
1715 int size = size16 ? 2 : 1;
1716 int type = size16 ? R_PCRWORD : R_PCRBYTE;
36ed2fff 1717 fixS *fixP;
252b5132
RH
1718
1719 check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@");
1720
1721 if (operand[i].exp.X_add_number & 1)
3048287a
NC
1722 as_warn (_("branch operand has odd offset (%lx)\n"),
1723 (unsigned long) operand->exp.X_add_number);
36ed2fff
JL
1724#ifndef OBJ_ELF
1725 /* The COFF port has always been off by one, changing it
1726 now would be an incompatible change, so we leave it as-is.
1727
1728 We don't want to do this for ELF as we want to be
1729 compatible with the proposed ELF format from Hitachi. */
252b5132 1730 operand[i].exp.X_add_number -= 1;
36ed2fff 1731#endif
7ee7b84d
MS
1732 if (size16)
1733 {
1734 operand[i].exp.X_add_number =
1735 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000;
1736 }
1737 else
1738 {
1739 operand[i].exp.X_add_number =
1740 ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80;
1741 }
1742
1743 /* For BRA/S. */
1744 if (! size16)
1745 operand[i].exp.X_add_number |= output[op_at[i] / 2];
252b5132 1746
36ed2fff 1747 fixP = fix_new_exp (frag_now,
7ee7b84d 1748 output - frag_now->fr_literal + op_at[i] / 2,
36ed2fff
JL
1749 size,
1750 &operand[i].exp,
1751 1,
1752 type);
1753 fixP->fx_signed = 1;
252b5132 1754 }
7ee7b84d 1755 else if (x_mode == MEMIND)
252b5132 1756 {
252b5132
RH
1757 check_operand (operand + i, 0xff, "@@");
1758 fix_new_exp (frag_now,
1759 output - frag_now->fr_literal + 1,
1760 1,
1761 &operand[i].exp,
1762 0,
1763 R_MEM_INDIRECT);
1764 }
7ee7b84d
MS
1765 else if (x_mode == VECIND)
1766 {
1767 check_operand (operand + i, 0x7f, "@@");
1768 /* FIXME: approximating the effect of "B31" here...
1769 This is very hackish, and ought to be done a better way. */
1770 operand[i].exp.X_add_number |= 0x80;
1771 fix_new_exp (frag_now,
1772 output - frag_now->fr_literal + 1,
1773 1,
1774 &operand[i].exp,
1775 0,
1776 R_MEM_INDIRECT);
1777 }
252b5132
RH
1778 else if (x & ABSJMP)
1779 {
3c1ba8a3 1780 int where = 0;
7ee7b84d 1781 bfd_reloc_code_real_type reloc_type = R_JMPL1;
3c1ba8a3
JL
1782
1783#ifdef OBJ_ELF
1784 /* To be compatible with the proposed H8 ELF format, we
1785 want the relocation's offset to point to the first byte
1786 that will be modified, not to the start of the instruction. */
7ee7b84d
MS
1787
1788 if ((operand->mode & SIZE) == L_32)
1789 {
1790 where = 2;
1791 reloc_type = R_RELLONG;
1792 }
1793 else
1794 where = 1;
3c1ba8a3 1795#endif
de342d07 1796
70d6ecf3 1797 /* This jmp may be a jump or a branch. */
252b5132 1798
7ee7b84d
MS
1799 check_operand (operand + i,
1800 SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff,
1801 "@");
3048287a 1802
252b5132 1803 if (operand[i].exp.X_add_number & 1)
3048287a
NC
1804 as_warn (_("branch operand has odd offset (%lx)\n"),
1805 (unsigned long) operand->exp.X_add_number);
1806
252b5132 1807 if (!Hmode)
70d6ecf3 1808 operand[i].exp.X_add_number =
4132022d 1809 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000;
252b5132 1810 fix_new_exp (frag_now,
3c1ba8a3 1811 output - frag_now->fr_literal + where,
252b5132
RH
1812 4,
1813 &operand[i].exp,
1814 0,
7ee7b84d 1815 reloc_type);
252b5132
RH
1816 }
1817 }
252b5132
RH
1818}
1819
70d6ecf3
AM
1820/* Try to give an intelligent error message for common and simple to
1821 detect errors. */
3048287a 1822
252b5132 1823static void
a720f7bc
KD
1824clever_message (instruction, operand)
1825 const struct h8_instruction *instruction;
252b5132
RH
1826 struct h8_op *operand;
1827{
70d6ecf3 1828 /* Find out if there was more than one possible opcode. */
252b5132 1829
a720f7bc 1830 if ((instruction + 1)->idx != instruction->idx)
252b5132 1831 {
3048287a 1832 int argn;
252b5132 1833
70d6ecf3
AM
1834 /* Only one opcode of this flavour, try to guess which operand
1835 didn't match. */
a720f7bc 1836 for (argn = 0; argn < instruction->noperands; argn++)
252b5132 1837 {
a720f7bc 1838 switch (instruction->opcode->args.nib[argn])
252b5132
RH
1839 {
1840 case RD16:
1841 if (operand[argn].mode != RD16)
1842 {
1843 as_bad (_("destination operand must be 16 bit register"));
1844 return;
1845
1846 }
1847 break;
1848
1849 case RS8:
252b5132
RH
1850 if (operand[argn].mode != RS8)
1851 {
1852 as_bad (_("source operand must be 8 bit register"));
1853 return;
1854 }
1855 break;
1856
1857 case ABS16DST:
1858 if (operand[argn].mode != ABS16DST)
1859 {
1860 as_bad (_("destination operand must be 16bit absolute address"));
1861 return;
1862 }
1863 break;
1864 case RD8:
1865 if (operand[argn].mode != RD8)
1866 {
1867 as_bad (_("destination operand must be 8 bit register"));
1868 return;
1869 }
1870 break;
1871
252b5132
RH
1872 case ABS16SRC:
1873 if (operand[argn].mode != ABS16SRC)
1874 {
1875 as_bad (_("source operand must be 16bit absolute address"));
1876 return;
1877 }
1878 break;
1879
1880 }
1881 }
1882 }
1883 as_bad (_("invalid operands"));
1884}
1885
d4ea8842
MS
1886
1887/* Adjust OPERAND's value and size given that it is accessing a field
1888 of SIZE bytes.
1889
1890 This function handles the choice between @(d:2,ERn) and @(d:16,ERn)
1891 when no size is explicitly given. It also scales down the assembly-level
1892 displacement in an @(d:2,ERn) operand. */
1893
1894static void
1895fix_operand_size (operand, size)
1896 struct h8_op *operand;
1897 int size;
1898{
1899 if ((operand->mode & MODE) == DISP)
1900 {
1901 /* If the user didn't specify an operand width, see if we
1902 can use @(d:2,ERn). */
1903 if (SXmode
1904 && (operand->mode & SIZE) == 0
1905 && (operand->exp.X_add_number == size
1906 || operand->exp.X_add_number == size * 2
1907 || operand->exp.X_add_number == size * 3))
1908 operand->mode |= L_2;
1909
1910 /* Scale down the displacement in an @(d:2,ERn) operand.
1911 X_add_number then contains the desired field value. */
1912 if ((operand->mode & SIZE) == L_2)
1913 {
1914 if (operand->exp.X_add_number % size != 0)
1915 as_warn (_("operand/size mis-match"));
1916 operand->exp.X_add_number /= size;
1917 }
1918 }
1919
1920 /* If the operand needs a size but doesn't have one yet, it must be
1921 a 16-bit integer (see colonmod24). */
1922 if ((operand->mode & SIZE) == 0)
1923 switch (operand->mode & MODE)
1924 {
1925 case DISP:
1926 case INDEXB:
1927 case INDEXW:
1928 case INDEXL:
1929 case ABS:
1930 operand->mode |= L_16;
1931 break;
1932 }
1933}
1934
1935
70d6ecf3
AM
1936/* This is the guts of the machine-dependent assembler. STR points to
1937 a machine dependent instruction. This function is supposed to emit
1938 the frags/bytes it assembles. */
3048287a 1939
252b5132
RH
1940void
1941md_assemble (str)
1942 char *str;
1943{
1944 char *op_start;
1945 char *op_end;
7ee7b84d 1946 struct h8_op operand[3];
a720f7bc
KD
1947 const struct h8_instruction *instruction;
1948 const struct h8_instruction *prev_instruction;
252b5132
RH
1949
1950 char *dot = 0;
1951 char c;
7ee7b84d 1952 int size, i;
252b5132 1953
70d6ecf3 1954 /* Drop leading whitespace. */
252b5132
RH
1955 while (*str == ' ')
1956 str++;
1957
70d6ecf3 1958 /* Find the op code end. */
252b5132
RH
1959 for (op_start = op_end = str;
1960 *op_end != 0 && *op_end != ' ';
1961 op_end++)
1962 {
1963 if (*op_end == '.')
1964 {
1965 dot = op_end + 1;
1966 *op_end = 0;
1967 op_end += 2;
1968 break;
1969 }
1970 }
1971
252b5132
RH
1972 if (op_end == op_start)
1973 {
1974 as_bad (_("can't find opcode "));
1975 }
1976 c = *op_end;
1977
1978 *op_end = 0;
1979
a720f7bc
KD
1980 instruction = (const struct h8_instruction *)
1981 hash_find (opcode_hash_control, op_start);
252b5132 1982
a720f7bc 1983 if (instruction == NULL)
252b5132
RH
1984 {
1985 as_bad (_("unknown opcode"));
1986 return;
1987 }
1988
70d6ecf3 1989 /* We used to set input_line_pointer to the result of get_operands,
252b5132
RH
1990 but that is wrong. Our caller assumes we don't change it. */
1991
7ee7b84d
MS
1992 operand[0].mode = 0;
1993 operand[1].mode = 0;
1994 operand[2].mode = 0;
1995
1996 if (OP_KIND (instruction->opcode->how) == O_MOVAB
1997 || OP_KIND (instruction->opcode->how) == O_MOVAW
1998 || OP_KIND (instruction->opcode->how) == O_MOVAL)
1999 get_mova_operands (op_end, operand);
2000 else if (OP_KIND (instruction->opcode->how) == O_RTEL
2001 || OP_KIND (instruction->opcode->how) == O_RTSL)
2002 get_rtsl_operands (op_end, operand);
2003 else
2004 get_operands (instruction->noperands, op_end, operand);
2005
252b5132 2006 *op_end = c;
a720f7bc 2007 prev_instruction = instruction;
252b5132
RH
2008
2009 size = SN;
2010 if (dot)
2011 {
2012 switch (*dot)
2013 {
2014 case 'b':
2015 size = SB;
2016 break;
2017
2018 case 'w':
2019 size = SW;
2020 break;
2021
2022 case 'l':
2023 size = SL;
2024 break;
2025 }
2026 }
7ee7b84d
MS
2027 if (OP_KIND (instruction->opcode->how) == O_MOVAB ||
2028 OP_KIND (instruction->opcode->how) == O_MOVAW ||
2029 OP_KIND (instruction->opcode->how) == O_MOVAL)
252b5132 2030 {
d4ea8842
MS
2031 switch (operand[0].mode & MODE)
2032 {
7ee7b84d
MS
2033 case INDEXB:
2034 default:
d4ea8842 2035 fix_operand_size (&operand[1], 1);
7ee7b84d
MS
2036 break;
2037 case INDEXW:
d4ea8842 2038 fix_operand_size (&operand[1], 2);
7ee7b84d
MS
2039 break;
2040 case INDEXL:
d4ea8842 2041 fix_operand_size (&operand[1], 4);
7ee7b84d 2042 break;
252b5132
RH
2043 }
2044 }
7ee7b84d
MS
2045 else
2046 {
d4ea8842
MS
2047 for (i = 0; i < 3 && operand[i].mode != 0; i++)
2048 switch (size)
2049 {
7ee7b84d
MS
2050 case SN:
2051 case SB:
2052 default:
d4ea8842 2053 fix_operand_size (&operand[i], 1);
7ee7b84d
MS
2054 break;
2055 case SW:
d4ea8842 2056 fix_operand_size (&operand[i], 2);
7ee7b84d
MS
2057 break;
2058 case SL:
d4ea8842 2059 fix_operand_size (&operand[i], 4);
7ee7b84d
MS
2060 break;
2061 }
2062 }
252b5132 2063
d4ea8842
MS
2064 instruction = get_specific (instruction, operand, size);
2065
2066 if (instruction == 0)
2067 {
2068 /* Couldn't find an opcode which matched the operands. */
2069 char *where = frag_more (2);
2070
2071 where[0] = 0x0;
2072 where[1] = 0x0;
2073 clever_message (prev_instruction, operand);
2074
2075 return;
2076 }
2077
a720f7bc 2078 build_bytes (instruction, operand);
2c8714f2
NC
2079
2080#ifdef BFD_ASSEMBLER
2081 dwarf2_emit_insn (instruction->length);
2082#endif
252b5132
RH
2083}
2084
5facebfc 2085#ifndef BFD_ASSEMBLER
252b5132
RH
2086void
2087tc_crawl_symbol_chain (headers)
70d6ecf3 2088 object_headers *headers ATTRIBUTE_UNUSED;
252b5132
RH
2089{
2090 printf (_("call to tc_crawl_symbol_chain \n"));
2091}
f333765f 2092#endif
252b5132
RH
2093
2094symbolS *
2095md_undefined_symbol (name)
dbbc7809 2096 char *name ATTRIBUTE_UNUSED;
252b5132
RH
2097{
2098 return 0;
2099}
2100
5facebfc 2101#ifndef BFD_ASSEMBLER
252b5132
RH
2102void
2103tc_headers_hook (headers)
70d6ecf3 2104 object_headers *headers ATTRIBUTE_UNUSED;
252b5132
RH
2105{
2106 printf (_("call to tc_headers_hook \n"));
2107}
f333765f 2108#endif
252b5132
RH
2109
2110/* Various routines to kill one day */
2111/* Equal to MAX_PRECISION in atof-ieee.c */
2112#define MAX_LITTLENUMS 6
2113
70d6ecf3
AM
2114/* Turn a string in input_line_pointer into a floating point constant
2115 of type TYPE, and store the appropriate bytes in *LITP. The number
bc0d738a 2116 of LITTLENUMS emitted is stored in *SIZEP. An error message is
70d6ecf3 2117 returned, or NULL on OK. */
bc0d738a 2118
252b5132
RH
2119char *
2120md_atof (type, litP, sizeP)
2121 char type;
2122 char *litP;
2123 int *sizeP;
2124{
2125 int prec;
2126 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2127 LITTLENUM_TYPE *wordP;
2128 char *t;
252b5132
RH
2129
2130 switch (type)
2131 {
2132 case 'f':
2133 case 'F':
2134 case 's':
2135 case 'S':
2136 prec = 2;
2137 break;
2138
2139 case 'd':
2140 case 'D':
2141 case 'r':
2142 case 'R':
2143 prec = 4;
2144 break;
2145
2146 case 'x':
2147 case 'X':
2148 prec = 6;
2149 break;
2150
2151 case 'p':
2152 case 'P':
2153 prec = 6;
2154 break;
2155
2156 default:
2157 *sizeP = 0;
2158 return _("Bad call to MD_ATOF()");
2159 }
2160 t = atof_ieee (input_line_pointer, type, words);
2161 if (t)
2162 input_line_pointer = t;
2163
2164 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2165 for (wordP = words; prec--;)
2166 {
2167 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
2168 litP += sizeof (LITTLENUM_TYPE);
2169 }
2170 return 0;
2171}
2172\f
5a38dc70 2173const char *md_shortopts = "";
252b5132
RH
2174struct option md_longopts[] = {
2175 {NULL, no_argument, NULL, 0}
2176};
70d6ecf3
AM
2177
2178size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH
2179
2180int
2181md_parse_option (c, arg)
dbbc7809
JL
2182 int c ATTRIBUTE_UNUSED;
2183 char *arg ATTRIBUTE_UNUSED;
252b5132
RH
2184{
2185 return 0;
2186}
2187
2188void
2189md_show_usage (stream)
dbbc7809 2190 FILE *stream ATTRIBUTE_UNUSED;
252b5132
RH
2191{
2192}
2193\f
3048287a
NC
2194void tc_aout_fix_to_chars PARAMS ((void));
2195
252b5132
RH
2196void
2197tc_aout_fix_to_chars ()
2198{
2199 printf (_("call to tc_aout_fix_to_chars \n"));
2200 abort ();
2201}
2202
2203void
2204md_convert_frag (headers, seg, fragP)
36ed2fff
JL
2205#ifdef BFD_ASSEMBLER
2206 bfd *headers ATTRIBUTE_UNUSED;
2207#else
dbbc7809 2208 object_headers *headers ATTRIBUTE_UNUSED;
36ed2fff 2209#endif
dbbc7809
JL
2210 segT seg ATTRIBUTE_UNUSED;
2211 fragS *fragP ATTRIBUTE_UNUSED;
252b5132
RH
2212{
2213 printf (_("call to md_convert_frag \n"));
2214 abort ();
2215}
2216
3c1ba8a3
JL
2217#ifdef BFD_ASSEMBLER
2218valueT
2219md_section_align (segment, size)
2220 segT segment;
2221 valueT size;
2222{
2223 int align = bfd_get_section_alignment (stdoutput, segment);
2224 return ((size + (1 << align) - 1) & (-1 << align));
2225}
2226#else
70d6ecf3 2227valueT
252b5132
RH
2228md_section_align (seg, size)
2229 segT seg;
2230 valueT size;
2231{
70d6ecf3 2232 return ((size + (1 << section_alignment[(int) seg]) - 1)
cc8a6dd0 2233 & (-1 << section_alignment[(int) seg]));
252b5132 2234}
3c1ba8a3
JL
2235#endif
2236
252b5132
RH
2237
2238void
94f592af 2239md_apply_fix3 (fixP, valP, seg)
252b5132 2240 fixS *fixP;
94f592af
NC
2241 valueT *valP;
2242 segT seg ATTRIBUTE_UNUSED;
252b5132
RH
2243{
2244 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
a161fe53 2245 long val = *valP;
252b5132
RH
2246
2247 switch (fixP->fx_size)
2248 {
2249 case 1:
2250 *buf++ = val;
2251 break;
2252 case 2:
2253 *buf++ = (val >> 8);
2254 *buf++ = val;
2255 break;
2256 case 4:
2257 *buf++ = (val >> 24);
2258 *buf++ = (val >> 16);
2259 *buf++ = (val >> 8);
2260 *buf++ = val;
2261 break;
2262 default:
2263 abort ();
2264 }
94f592af
NC
2265
2266 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
2267 fixP->fx_done = 1;
252b5132
RH
2268}
2269
2270int
2271md_estimate_size_before_relax (fragP, segment_type)
dbbc7809
JL
2272 register fragS *fragP ATTRIBUTE_UNUSED;
2273 register segT segment_type ATTRIBUTE_UNUSED;
252b5132
RH
2274{
2275 printf (_("call tomd_estimate_size_before_relax \n"));
2276 abort ();
2277}
2278
70d6ecf3 2279/* Put number into target byte order. */
252b5132
RH
2280void
2281md_number_to_chars (ptr, use, nbytes)
2282 char *ptr;
2283 valueT use;
2284 int nbytes;
2285{
2286 number_to_chars_bigendian (ptr, use, nbytes);
2287}
70d6ecf3 2288
252b5132
RH
2289long
2290md_pcrel_from (fixP)
dbbc7809 2291 fixS *fixP ATTRIBUTE_UNUSED;
252b5132
RH
2292{
2293 abort ();
2294}
2295
5facebfc 2296#ifndef BFD_ASSEMBLER
252b5132
RH
2297void
2298tc_reloc_mangle (fix_ptr, intr, base)
2299 fixS *fix_ptr;
2300 struct internal_reloc *intr;
2301 bfd_vma base;
2302
2303{
2304 symbolS *symbol_ptr;
2305
2306 symbol_ptr = fix_ptr->fx_addsy;
2307
2308 /* If this relocation is attached to a symbol then it's ok
70d6ecf3 2309 to output it. */
252b5132
RH
2310 if (fix_ptr->fx_r_type == TC_CONS_RELOC)
2311 {
2312 /* cons likes to create reloc32's whatever the size of the reloc..
2313 */
2314 switch (fix_ptr->fx_size)
2315 {
2316 case 4:
2317 intr->r_type = R_RELLONG;
2318 break;
2319 case 2:
2320 intr->r_type = R_RELWORD;
2321 break;
2322 case 1:
2323 intr->r_type = R_RELBYTE;
2324 break;
2325 default:
2326 abort ();
252b5132 2327 }
252b5132
RH
2328 }
2329 else
2330 {
2331 intr->r_type = fix_ptr->fx_r_type;
2332 }
2333
2334 intr->r_vaddr = fix_ptr->fx_frag->fr_address + fix_ptr->fx_where + base;
2335 intr->r_offset = fix_ptr->fx_offset;
2336
2337 if (symbol_ptr)
2338 {
2339 if (symbol_ptr->sy_number != -1)
2340 intr->r_symndx = symbol_ptr->sy_number;
2341 else
2342 {
2343 symbolS *segsym;
2344
2345 /* This case arises when a reference is made to `.'. */
2346 segsym = seg_info (S_GET_SEGMENT (symbol_ptr))->dot;
2347 if (segsym == NULL)
2348 intr->r_symndx = -1;
2349 else
2350 {
2351 intr->r_symndx = segsym->sy_number;
2352 intr->r_offset += S_GET_VALUE (symbol_ptr);
2353 }
2354 }
2355 }
2356 else
2357 intr->r_symndx = -1;
252b5132 2358}
5facebfc 2359#else /* BFD_ASSEMBLER */
f333765f
JL
2360arelent *
2361tc_gen_reloc (section, fixp)
2362 asection *section ATTRIBUTE_UNUSED;
2363 fixS *fixp;
2364{
2365 arelent *rel;
2366 bfd_reloc_code_real_type r_type;
2367
de342d07
JL
2368 if (fixp->fx_addsy && fixp->fx_subsy)
2369 {
2370 if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy))
2371 || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section)
2372 {
2373 as_bad_where (fixp->fx_file, fixp->fx_line,
2374 "Difference of symbols in different sections is not supported");
2375 return NULL;
2376 }
2377 }
2378
f333765f
JL
2379 rel = (arelent *) xmalloc (sizeof (arelent));
2380 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2381 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
2382 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
2383 rel->addend = fixp->fx_offset;
2384
2385 r_type = fixp->fx_r_type;
2386
2387#define DEBUG 0
2388#if DEBUG
2389 fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type));
2390 fflush(stderr);
2391#endif
2392 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type);
2393 if (rel->howto == NULL)
2394 {
2395 as_bad_where (fixp->fx_file, fixp->fx_line,
2396 _("Cannot represent relocation type %s"),
2397 bfd_get_reloc_code_name (r_type));
2398 return NULL;
2399 }
2400
2401 return rel;
2402}
2403#endif
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