Commit | Line | Data |
---|---|---|
c2dcd04e | 1 | /* tc-h8300.c -- Assemble code for the Renesas H8/300 |
cc8a6dd0 | 2 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, |
2132e3a3 | 3 | 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
252b5132 | 21 | |
bc0d738a | 22 | /* Written By Steve Chamberlain <sac@cygnus.com>. */ |
252b5132 RH |
23 | |
24 | #include <stdio.h> | |
25 | #include "as.h" | |
26 | #include "subsegs.h" | |
27 | #include "bfd.h" | |
2c8714f2 NC |
28 | |
29 | #ifdef BFD_ASSEMBLER | |
30 | #include "dwarf2dbg.h" | |
31 | #endif | |
32 | ||
252b5132 RH |
33 | #define DEFINE_TABLE |
34 | #define h8_opcodes ops | |
35 | #include "opcode/h8300.h" | |
3882b010 | 36 | #include "safe-ctype.h" |
252b5132 | 37 | |
7e0de7bf JL |
38 | #ifdef OBJ_ELF |
39 | #include "elf/h8.h" | |
7e0de7bf JL |
40 | #endif |
41 | ||
63a0b638 | 42 | const char comment_chars[] = ";"; |
252b5132 | 43 | const char line_comment_chars[] = "#"; |
63a0b638 | 44 | const char line_separator_chars[] = ""; |
252b5132 | 45 | |
600e9c99 KH |
46 | static void sbranch (int); |
47 | static void h8300hmode (int); | |
48 | static void h8300smode (int); | |
49 | static void h8300hnmode (int); | |
50 | static void h8300snmode (int); | |
51 | static void h8300sxmode (int); | |
52 | static void h8300sxnmode (int); | |
b54a3392 | 53 | static void pint (int); |
252b5132 | 54 | |
66faad26 KH |
55 | int Hmode; |
56 | int Smode; | |
57 | int Nmode; | |
58 | int SXmode; | |
3048287a | 59 | |
d4e2de6b | 60 | #define PSIZE (Hmode && !Nmode ? L_32 : L_16) |
3048287a | 61 | |
600e9c99 | 62 | static int bsize = L_8; /* Default branch displacement. */ |
252b5132 | 63 | |
a720f7bc KD |
64 | struct h8_instruction |
65 | { | |
66 | int length; | |
67 | int noperands; | |
68 | int idx; | |
69 | int size; | |
70 | const struct h8_opcode *opcode; | |
71 | }; | |
72 | ||
600e9c99 | 73 | static struct h8_instruction *h8_instructions; |
a720f7bc | 74 | |
600e9c99 | 75 | static void |
b54a3392 | 76 | h8300hmode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
77 | { |
78 | Hmode = 1; | |
79 | Smode = 0; | |
83e20b45 JL |
80 | #ifdef BFD_ASSEMBLER |
81 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) | |
82 | as_warn (_("could not set architecture and machine")); | |
83 | #endif | |
252b5132 RH |
84 | } |
85 | ||
600e9c99 | 86 | static void |
b54a3392 | 87 | h8300smode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
88 | { |
89 | Smode = 1; | |
90 | Hmode = 1; | |
83e20b45 JL |
91 | #ifdef BFD_ASSEMBLER |
92 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) | |
93 | as_warn (_("could not set architecture and machine")); | |
94 | #endif | |
252b5132 | 95 | } |
70d6ecf3 | 96 | |
600e9c99 | 97 | static void |
b54a3392 | 98 | h8300hnmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
99 | { |
100 | Hmode = 1; | |
101 | Smode = 0; | |
102 | Nmode = 1; | |
103 | #ifdef BFD_ASSEMBLER | |
104 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) | |
105 | as_warn (_("could not set architecture and machine")); | |
106 | #endif | |
107 | } | |
108 | ||
600e9c99 | 109 | static void |
b54a3392 | 110 | h8300snmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
111 | { |
112 | Smode = 1; | |
113 | Hmode = 1; | |
114 | Nmode = 1; | |
115 | #ifdef BFD_ASSEMBLER | |
116 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) | |
117 | as_warn (_("could not set architecture and machine")); | |
118 | #endif | |
119 | } | |
120 | ||
600e9c99 | 121 | static void |
b54a3392 | 122 | h8300sxmode (int arg ATTRIBUTE_UNUSED) |
7ee7b84d MS |
123 | { |
124 | Smode = 1; | |
125 | Hmode = 1; | |
126 | SXmode = 1; | |
127 | #ifdef BFD_ASSEMBLER | |
128 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) | |
129 | as_warn (_("could not set architecture and machine")); | |
130 | #endif | |
131 | } | |
132 | ||
600e9c99 | 133 | static void |
b54a3392 | 134 | h8300sxnmode (int arg ATTRIBUTE_UNUSED) |
f4984206 RS |
135 | { |
136 | Smode = 1; | |
137 | Hmode = 1; | |
138 | SXmode = 1; | |
139 | Nmode = 1; | |
140 | #ifdef BFD_ASSEMBLER | |
141 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) | |
142 | as_warn (_("could not set architecture and machine")); | |
143 | #endif | |
144 | } | |
145 | ||
600e9c99 | 146 | static void |
b54a3392 | 147 | sbranch (int size) |
252b5132 RH |
148 | { |
149 | bsize = size; | |
150 | } | |
151 | ||
70d6ecf3 | 152 | static void |
b54a3392 | 153 | pint (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
154 | { |
155 | cons (Hmode ? 4 : 2); | |
156 | } | |
157 | ||
3048287a NC |
158 | /* This table describes all the machine specific pseudo-ops the assembler |
159 | has to support. The fields are: | |
160 | pseudo-op name without dot | |
161 | function to call to execute this pseudo-op | |
162 | Integer arg to pass to the function. */ | |
163 | ||
252b5132 RH |
164 | const pseudo_typeS md_pseudo_table[] = |
165 | { | |
7ee7b84d | 166 | {"h8300h", h8300hmode, 0}, |
8d9cd6b1 | 167 | {"h8300hn", h8300hnmode, 0}, |
7ee7b84d | 168 | {"h8300s", h8300smode, 0}, |
8d9cd6b1 | 169 | {"h8300sn", h8300snmode, 0}, |
7ee7b84d | 170 | {"h8300sx", h8300sxmode, 0}, |
f4984206 | 171 | {"h8300sxn", h8300sxnmode, 0}, |
252b5132 RH |
172 | {"sbranch", sbranch, L_8}, |
173 | {"lbranch", sbranch, L_16}, | |
174 | ||
175 | {"int", pint, 0}, | |
176 | {"data.b", cons, 1}, | |
177 | {"data.w", cons, 2}, | |
178 | {"data.l", cons, 4}, | |
179 | {"form", listing_psize, 0}, | |
180 | {"heading", listing_title, 0}, | |
7ee7b84d MS |
181 | {"import", s_ignore, 0}, |
182 | {"page", listing_eject, 0}, | |
252b5132 RH |
183 | {"program", s_ignore, 0}, |
184 | {0, 0, 0} | |
185 | }; | |
186 | ||
187 | const int md_reloc_size; | |
188 | ||
189 | const char EXP_CHARS[] = "eE"; | |
190 | ||
3048287a NC |
191 | /* Chars that mean this number is a floating point constant |
192 | As in 0f12.456 | |
193 | or 0d1.2345e12. */ | |
252b5132 RH |
194 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
195 | ||
3048287a | 196 | static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ |
252b5132 | 197 | |
70d6ecf3 AM |
198 | /* This function is called once, at assembler startup time. This |
199 | should set up all the tables, etc. that the MD part of the assembler | |
200 | needs. */ | |
3048287a | 201 | |
252b5132 | 202 | void |
b54a3392 | 203 | md_begin (void) |
252b5132 | 204 | { |
a720f7bc | 205 | unsigned int nopcodes; |
7ee7b84d | 206 | struct h8_opcode *p, *p1; |
a720f7bc | 207 | struct h8_instruction *pi; |
252b5132 RH |
208 | char prev_buffer[100]; |
209 | int idx = 0; | |
210 | ||
83e20b45 JL |
211 | #ifdef BFD_ASSEMBLER |
212 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300)) | |
213 | as_warn (_("could not set architecture and machine")); | |
214 | #endif | |
215 | ||
252b5132 RH |
216 | opcode_hash_control = hash_new (); |
217 | prev_buffer[0] = 0; | |
218 | ||
a720f7bc KD |
219 | nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); |
220 | ||
221 | h8_instructions = (struct h8_instruction *) | |
222 | xmalloc (nopcodes * sizeof (struct h8_instruction)); | |
223 | ||
7ee7b84d MS |
224 | pi = h8_instructions; |
225 | p1 = h8_opcodes; | |
226 | /* We do a minimum amount of sorting on the opcode table; this is to | |
227 | make it easy to describe the mova instructions without unnecessary | |
228 | code duplication. | |
229 | Sorting only takes place inside blocks of instructions of the form | |
230 | X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ | |
231 | while (p1) | |
252b5132 | 232 | { |
7ee7b84d MS |
233 | struct h8_opcode *first_skipped = 0; |
234 | int len, cmplen = 0; | |
235 | char *src = p1->name; | |
236 | char *dst, *buffer; | |
252b5132 | 237 | |
7ee7b84d MS |
238 | if (p1->name == 0) |
239 | break; | |
240 | /* Strip off any . part when inserting the opcode and only enter | |
241 | unique codes into the hash table. */ | |
242 | dst = buffer = malloc (strlen (src) + 1); | |
252b5132 RH |
243 | while (*src) |
244 | { | |
245 | if (*src == '.') | |
246 | { | |
247 | src++; | |
252b5132 RH |
248 | break; |
249 | } | |
7ee7b84d MS |
250 | if (*src == '/') |
251 | cmplen = src - p1->name + 1; | |
252b5132 RH |
252 | *dst++ = *src++; |
253 | } | |
7ee7b84d MS |
254 | *dst = 0; |
255 | len = dst - buffer; | |
256 | if (cmplen == 0) | |
257 | cmplen = len; | |
258 | hash_insert (opcode_hash_control, buffer, (char *) pi); | |
259 | strcpy (prev_buffer, buffer); | |
260 | idx++; | |
261 | ||
262 | for (p = p1; p->name; p++) | |
252b5132 | 263 | { |
7ee7b84d MS |
264 | /* A negative TIME is used to indicate that we've added this opcode |
265 | already. */ | |
266 | if (p->time == -1) | |
267 | continue; | |
268 | if (strncmp (p->name, buffer, cmplen) != 0 | |
269 | || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' | |
270 | && p->name[cmplen - 1] != '/')) | |
271 | { | |
272 | if (first_skipped == 0) | |
273 | first_skipped = p; | |
274 | break; | |
275 | } | |
276 | if (strncmp (p->name, buffer, len) != 0) | |
277 | { | |
278 | if (first_skipped == 0) | |
279 | first_skipped = p; | |
280 | continue; | |
281 | } | |
282 | ||
283 | p->time = -1; | |
284 | pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; | |
285 | pi->idx = idx; | |
252b5132 | 286 | |
7ee7b84d MS |
287 | /* Find the number of operands. */ |
288 | pi->noperands = 0; | |
289 | while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) | |
290 | pi->noperands++; | |
70d6ecf3 | 291 | |
7ee7b84d MS |
292 | /* Find the length of the opcode in bytes. */ |
293 | pi->length = 0; | |
294 | while (p->data.nib[pi->length * 2] != (op_type) E) | |
295 | pi->length++; | |
a720f7bc | 296 | |
7ee7b84d MS |
297 | pi->opcode = p; |
298 | pi++; | |
299 | } | |
300 | p1 = first_skipped; | |
252b5132 RH |
301 | } |
302 | ||
a720f7bc KD |
303 | /* Add entry for the NULL vector terminator. */ |
304 | pi->length = 0; | |
305 | pi->noperands = 0; | |
306 | pi->idx = 0; | |
307 | pi->size = 0; | |
7ee7b84d | 308 | pi->opcode = 0; |
a720f7bc | 309 | |
252b5132 RH |
310 | linkrelax = 1; |
311 | } | |
312 | ||
252b5132 RH |
313 | struct h8_op |
314 | { | |
315 | op_type mode; | |
316 | unsigned reg; | |
317 | expressionS exp; | |
318 | }; | |
319 | ||
b54a3392 KH |
320 | static void clever_message (const struct h8_instruction *, struct h8_op *); |
321 | static void fix_operand_size (struct h8_op *, int); | |
322 | static void build_bytes (const struct h8_instruction *, struct h8_op *); | |
323 | static void do_a_fix_imm (int, int, struct h8_op *, int); | |
324 | static void check_operand (struct h8_op *, unsigned int, char *); | |
325 | static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; | |
326 | static char *get_operands (unsigned, char *, struct h8_op *); | |
327 | static void get_operand (char **, struct h8_op *, int); | |
328 | static int parse_reg (char *, op_type *, unsigned *, int); | |
329 | static char *skip_colonthing (char *, int *); | |
330 | static char *parse_exp (char *, struct h8_op *); | |
331 | ||
332 | static int constant_fits_width_p (struct h8_op *, unsigned int); | |
333 | static int constant_fits_size_p (struct h8_op *, int, int); | |
7ee7b84d | 334 | |
252b5132 RH |
335 | /* |
336 | parse operands | |
337 | WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp | |
338 | r0l,r0h,..r7l,r7h | |
339 | @WREG | |
340 | @WREG+ | |
341 | @-WREG | |
342 | #const | |
343 | ccr | |
344 | */ | |
345 | ||
bc0d738a NC |
346 | /* Try to parse a reg name. Return the number of chars consumed. */ |
347 | ||
40f09f82 | 348 | static int |
b54a3392 | 349 | parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) |
252b5132 RH |
350 | { |
351 | char *end; | |
352 | int len; | |
353 | ||
70d6ecf3 | 354 | /* Cribbed from get_symbol_end. */ |
252b5132 RH |
355 | if (!is_name_beginner (*src) || *src == '\001') |
356 | return 0; | |
70d6ecf3 | 357 | end = src + 1; |
7ee7b84d | 358 | while ((is_part_of_name (*end) && *end != '.') || *end == '\001') |
252b5132 RH |
359 | end++; |
360 | len = end - src; | |
361 | ||
7ee7b84d | 362 | if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
363 | { |
364 | *mode = PSIZE | REG | direction; | |
365 | *reg = 7; | |
366 | return len; | |
367 | } | |
7ee7b84d MS |
368 | if (len == 3 && |
369 | TOLOWER (src[0]) == 'c' && | |
370 | TOLOWER (src[1]) == 'c' && | |
371 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
372 | { |
373 | *mode = CCR; | |
374 | *reg = 0; | |
375 | return len; | |
376 | } | |
7ee7b84d MS |
377 | if (len == 3 && |
378 | TOLOWER (src[0]) == 'e' && | |
379 | TOLOWER (src[1]) == 'x' && | |
380 | TOLOWER (src[2]) == 'r') | |
252b5132 RH |
381 | { |
382 | *mode = EXR; | |
7ee7b84d MS |
383 | *reg = 1; |
384 | return len; | |
385 | } | |
386 | if (len == 3 && | |
387 | TOLOWER (src[0]) == 'v' && | |
388 | TOLOWER (src[1]) == 'b' && | |
389 | TOLOWER (src[2]) == 'r') | |
390 | { | |
391 | *mode = VBR; | |
392 | *reg = 6; | |
393 | return len; | |
394 | } | |
395 | if (len == 3 && | |
396 | TOLOWER (src[0]) == 's' && | |
397 | TOLOWER (src[1]) == 'b' && | |
398 | TOLOWER (src[2]) == 'r') | |
399 | { | |
400 | *mode = SBR; | |
401 | *reg = 7; | |
252b5132 RH |
402 | return len; |
403 | } | |
7ee7b84d | 404 | if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
405 | { |
406 | *mode = PSIZE | REG | direction; | |
407 | *reg = 6; | |
408 | return len; | |
409 | } | |
7ee7b84d MS |
410 | if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
411 | src[2] >= '0' && src[2] <= '7') | |
252b5132 RH |
412 | { |
413 | *mode = L_32 | REG | direction; | |
414 | *reg = src[2] - '0'; | |
415 | if (!Hmode) | |
416 | as_warn (_("Reg not valid for H8/300")); | |
417 | return len; | |
418 | } | |
7ee7b84d | 419 | if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') |
252b5132 RH |
420 | { |
421 | *mode = L_16 | REG | direction; | |
422 | *reg = src[1] - '0' + 8; | |
423 | if (!Hmode) | |
424 | as_warn (_("Reg not valid for H8/300")); | |
425 | return len; | |
426 | } | |
427 | ||
7ee7b84d | 428 | if (TOLOWER (src[0]) == 'r') |
252b5132 RH |
429 | { |
430 | if (src[1] >= '0' && src[1] <= '7') | |
431 | { | |
7ee7b84d | 432 | if (len == 3 && TOLOWER (src[2]) == 'l') |
252b5132 RH |
433 | { |
434 | *mode = L_8 | REG | direction; | |
435 | *reg = (src[1] - '0') + 8; | |
436 | return len; | |
437 | } | |
7ee7b84d | 438 | if (len == 3 && TOLOWER (src[2]) == 'h') |
252b5132 RH |
439 | { |
440 | *mode = L_8 | REG | direction; | |
441 | *reg = (src[1] - '0'); | |
442 | return len; | |
443 | } | |
444 | if (len == 2) | |
445 | { | |
446 | *mode = L_16 | REG | direction; | |
447 | *reg = (src[1] - '0'); | |
448 | return len; | |
449 | } | |
450 | } | |
451 | } | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
1b680e4f RS |
456 | |
457 | /* Parse an immediate or address-related constant and store it in OP. | |
458 | If the user also specifies the operand's size, store that size | |
459 | in OP->MODE, otherwise leave it for later code to decide. */ | |
460 | ||
40f09f82 | 461 | static char * |
b54a3392 | 462 | parse_exp (char *src, struct h8_op *op) |
252b5132 | 463 | { |
1b680e4f | 464 | char *save; |
252b5132 | 465 | |
1b680e4f RS |
466 | save = input_line_pointer; |
467 | input_line_pointer = src; | |
468 | expression (&op->exp); | |
469 | if (op->exp.X_op == O_absent) | |
252b5132 | 470 | as_bad (_("missing operand")); |
1b680e4f | 471 | src = input_line_pointer; |
252b5132 | 472 | input_line_pointer = save; |
1b680e4f RS |
473 | |
474 | return skip_colonthing (src, &op->mode); | |
252b5132 RH |
475 | } |
476 | ||
1b680e4f RS |
477 | |
478 | /* If SRC starts with an explicit operand size, skip it and store the size | |
479 | in *MODE. Leave *MODE unchanged otherwise. */ | |
480 | ||
252b5132 | 481 | static char * |
b54a3392 | 482 | skip_colonthing (char *src, int *mode) |
252b5132 | 483 | { |
1b680e4f | 484 | if (*src == ':') |
252b5132 | 485 | { |
1b680e4f | 486 | src++; |
252b5132 | 487 | *mode &= ~SIZE; |
1b680e4f | 488 | if (src[0] == '8' && !ISDIGIT (src[1])) |
7ee7b84d | 489 | *mode |= L_8; |
1b680e4f | 490 | else if (src[0] == '2' && !ISDIGIT (src[1])) |
7ee7b84d | 491 | *mode |= L_2; |
1b680e4f | 492 | else if (src[0] == '3' && !ISDIGIT (src[1])) |
7ee7b84d | 493 | *mode |= L_3; |
1b680e4f | 494 | else if (src[0] == '4' && !ISDIGIT (src[1])) |
7ee7b84d | 495 | *mode |= L_4; |
1b680e4f | 496 | else if (src[0] == '5' && !ISDIGIT (src[1])) |
7ee7b84d | 497 | *mode |= L_5; |
1b680e4f | 498 | else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) |
7ee7b84d | 499 | *mode |= L_24; |
1b680e4f | 500 | else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) |
7ee7b84d | 501 | *mode |= L_32; |
1b680e4f | 502 | else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) |
7ee7b84d | 503 | *mode |= L_16; |
252b5132 | 504 | else |
7ee7b84d MS |
505 | as_bad (_("invalid operand size requested")); |
506 | ||
1b680e4f RS |
507 | while (ISDIGIT (*src)) |
508 | src++; | |
252b5132 | 509 | } |
1b680e4f | 510 | return src; |
252b5132 RH |
511 | } |
512 | ||
513 | /* The many forms of operand: | |
514 | ||
515 | Rn Register direct | |
516 | @Rn Register indirect | |
517 | @(exp[:16], Rn) Register indirect with displacement | |
518 | @Rn+ | |
519 | @-Rn | |
70d6ecf3 AM |
520 | @aa:8 absolute 8 bit |
521 | @aa:16 absolute 16 bit | |
252b5132 RH |
522 | @aa absolute 16 bit |
523 | ||
524 | #xx[:size] immediate data | |
70d6ecf3 | 525 | @(exp:[8], pc) pc rel |
3048287a | 526 | @@aa[:8] memory indirect. */ |
252b5132 | 527 | |
7ee7b84d | 528 | static int |
b54a3392 | 529 | constant_fits_width_p (struct h8_op *operand, unsigned int width) |
7ee7b84d MS |
530 | { |
531 | return ((operand->exp.X_add_number & ~width) == 0 | |
532 | || (operand->exp.X_add_number | width) == (unsigned)(~0)); | |
533 | } | |
534 | ||
535 | static int | |
b54a3392 | 536 | constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) |
7ee7b84d MS |
537 | { |
538 | offsetT num = operand->exp.X_add_number; | |
539 | if (no_symbols | |
540 | && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) | |
541 | return 0; | |
542 | switch (size) | |
543 | { | |
544 | case L_2: | |
545 | return (num & ~3) == 0; | |
546 | case L_3: | |
547 | return (num & ~7) == 0; | |
548 | case L_3NZ: | |
549 | return num >= 1 && num < 8; | |
550 | case L_4: | |
551 | return (num & ~15) == 0; | |
552 | case L_5: | |
553 | return num >= 1 && num < 32; | |
554 | case L_8: | |
555 | return (num & ~0xFF) == 0 || ((unsigned)num | 0x7F) == ~0u; | |
556 | case L_8U: | |
557 | return (num & ~0xFF) == 0; | |
558 | case L_16: | |
559 | return (num & ~0xFFFF) == 0 || ((unsigned)num | 0x7FFF) == ~0u; | |
560 | case L_16U: | |
561 | return (num & ~0xFFFF) == 0; | |
562 | case L_32: | |
563 | return 1; | |
564 | default: | |
565 | abort (); | |
566 | } | |
567 | } | |
568 | ||
252b5132 | 569 | static void |
b54a3392 | 570 | get_operand (char **ptr, struct h8_op *op, int direction) |
252b5132 RH |
571 | { |
572 | char *src = *ptr; | |
573 | op_type mode; | |
574 | unsigned int num; | |
575 | unsigned int len; | |
576 | ||
7ee7b84d | 577 | op->mode = 0; |
252b5132 | 578 | |
3048287a NC |
579 | /* Check for '(' and ')' for instructions ldm and stm. */ |
580 | if (src[0] == '(' && src[8] == ')') | |
581 | ++ src; | |
582 | ||
252b5132 RH |
583 | /* Gross. Gross. ldm and stm have a format not easily handled |
584 | by get_operand. We deal with it explicitly here. */ | |
7ee7b84d MS |
585 | if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
586 | ISDIGIT (src[2]) && src[3] == '-' && | |
587 | TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) | |
252b5132 RH |
588 | { |
589 | int low, high; | |
590 | ||
591 | low = src[2] - '0'; | |
592 | high = src[6] - '0'; | |
593 | ||
4892e510 NC |
594 | /* Check register pair's validity as per tech note TN-H8*-193A/E |
595 | from Renesas for H8S and H8SX hardware manual. */ | |
596 | if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) | |
597 | && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) | |
598 | && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) | |
599 | && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) | |
600 | && !(low == 4 && (high == 5 || high == 6)) | |
b4f16abb | 601 | && !(low == 4 && high == 7 && SXmode) |
4892e510 NC |
602 | && !(low == 5 && (high == 6 || high == 7) && SXmode) |
603 | && !(low == 6 && high == 7 && SXmode)) | |
252b5132 RH |
604 | as_bad (_("Invalid register list for ldm/stm\n")); |
605 | ||
252b5132 RH |
606 | /* Even sicker. We encode two registers into op->reg. One |
607 | for the low register to save, the other for the high | |
608 | register to save; we also set the high bit in op->reg | |
609 | so we know this is "very special". */ | |
610 | op->reg = 0x80000000 | (high << 8) | low; | |
611 | op->mode = REG; | |
3048287a NC |
612 | if (src[7] == ')') |
613 | *ptr = src + 8; | |
614 | else | |
615 | *ptr = src + 7; | |
252b5132 RH |
616 | return; |
617 | } | |
618 | ||
619 | len = parse_reg (src, &op->mode, &op->reg, direction); | |
620 | if (len) | |
621 | { | |
7ee7b84d MS |
622 | src += len; |
623 | if (*src == '.') | |
624 | { | |
625 | int size = op->mode & SIZE; | |
626 | switch (src[1]) | |
627 | { | |
628 | case 'l': case 'L': | |
629 | if (size != L_32) | |
630 | as_warn (_("mismatch between register and suffix")); | |
631 | op->mode = (op->mode & ~MODE) | LOWREG; | |
632 | break; | |
633 | case 'w': case 'W': | |
634 | if (size != L_32 && size != L_16) | |
635 | as_warn (_("mismatch between register and suffix")); | |
636 | op->mode = (op->mode & ~MODE) | LOWREG; | |
637 | op->mode = (op->mode & ~SIZE) | L_16; | |
638 | break; | |
639 | case 'b': case 'B': | |
640 | op->mode = (op->mode & ~MODE) | LOWREG; | |
641 | if (size != L_32 && size != L_8) | |
642 | as_warn (_("mismatch between register and suffix")); | |
643 | op->mode = (op->mode & ~MODE) | LOWREG; | |
644 | op->mode = (op->mode & ~SIZE) | L_8; | |
645 | break; | |
646 | default: | |
647 | as_warn ("invalid suffix after register."); | |
648 | break; | |
649 | } | |
650 | src += 2; | |
651 | } | |
652 | *ptr = src; | |
252b5132 RH |
653 | return; |
654 | } | |
655 | ||
656 | if (*src == '@') | |
657 | { | |
658 | src++; | |
659 | if (*src == '@') | |
660 | { | |
1b680e4f | 661 | *ptr = parse_exp (src + 1, op); |
7ee7b84d MS |
662 | if (op->exp.X_add_number >= 0x100) |
663 | { | |
d4e2de6b | 664 | int divisor = 1; |
7ee7b84d MS |
665 | |
666 | op->mode = VECIND; | |
667 | /* FIXME : 2? or 4? */ | |
668 | if (op->exp.X_add_number >= 0x400) | |
669 | as_bad (_("address too high for vector table jmp/jsr")); | |
670 | else if (op->exp.X_add_number >= 0x200) | |
671 | divisor = 4; | |
672 | else | |
673 | divisor = 2; | |
674 | ||
675 | op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; | |
676 | } | |
677 | else | |
678 | op->mode = MEMIND; | |
252b5132 | 679 | return; |
252b5132 RH |
680 | } |
681 | ||
7ee7b84d | 682 | if (*src == '-' || *src == '+') |
252b5132 | 683 | { |
1b680e4f | 684 | len = parse_reg (src + 1, &mode, &num, direction); |
252b5132 RH |
685 | if (len == 0) |
686 | { | |
70d6ecf3 | 687 | /* Oops, not a reg after all, must be ordinary exp. */ |
1b680e4f RS |
688 | op->mode = ABS | direction; |
689 | *ptr = parse_exp (src, op); | |
252b5132 | 690 | return; |
252b5132 RH |
691 | } |
692 | ||
d4e2de6b NC |
693 | if (((mode & SIZE) != PSIZE) |
694 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
695 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 696 | as_bad (_("Wrong size pointer register for architecture.")); |
1b680e4f RS |
697 | |
698 | op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; | |
252b5132 | 699 | op->reg = num; |
1b680e4f | 700 | *ptr = src + 1 + len; |
252b5132 RH |
701 | return; |
702 | } | |
703 | if (*src == '(') | |
704 | { | |
252b5132 RH |
705 | src++; |
706 | ||
7ee7b84d MS |
707 | /* See if this is @(ERn.x, PC). */ |
708 | len = parse_reg (src, &mode, &op->reg, direction); | |
709 | if (len != 0 && (mode & MODE) == REG && src[len] == '.') | |
710 | { | |
711 | switch (TOLOWER (src[len + 1])) | |
712 | { | |
713 | case 'b': | |
714 | mode = PCIDXB | direction; | |
715 | break; | |
716 | case 'w': | |
717 | mode = PCIDXW | direction; | |
718 | break; | |
719 | case 'l': | |
720 | mode = PCIDXL | direction; | |
721 | break; | |
722 | default: | |
723 | mode = 0; | |
724 | break; | |
725 | } | |
726 | if (mode | |
727 | && src[len + 2] == ',' | |
728 | && TOLOWER (src[len + 3]) != 'p' | |
729 | && TOLOWER (src[len + 4]) != 'c' | |
730 | && src[len + 5] != ')') | |
731 | { | |
732 | *ptr = src + len + 6; | |
733 | op->mode |= mode; | |
734 | return; | |
735 | } | |
736 | /* Fall through into disp case - the grammar is somewhat | |
737 | ambiguous, so we should try whether it's a DISP operand | |
738 | after all ("ER3.L" might be a poorly named label...). */ | |
739 | } | |
740 | ||
741 | /* Disp. */ | |
742 | ||
70d6ecf3 | 743 | /* Start off assuming a 16 bit offset. */ |
252b5132 | 744 | |
1b680e4f | 745 | src = parse_exp (src, op); |
252b5132 RH |
746 | if (*src == ')') |
747 | { | |
252b5132 | 748 | op->mode |= ABS | direction; |
1b680e4f | 749 | *ptr = src + 1; |
252b5132 RH |
750 | return; |
751 | } | |
752 | ||
753 | if (*src != ',') | |
754 | { | |
755 | as_bad (_("expected @(exp, reg16)")); | |
756 | return; | |
252b5132 RH |
757 | } |
758 | src++; | |
759 | ||
760 | len = parse_reg (src, &mode, &op->reg, direction); | |
7ee7b84d | 761 | if (len == 0 || (mode & MODE) != REG) |
252b5132 RH |
762 | { |
763 | as_bad (_("expected @(exp, reg16)")); | |
764 | return; | |
765 | } | |
252b5132 | 766 | src += len; |
7ee7b84d MS |
767 | if (src[0] == '.') |
768 | { | |
769 | switch (TOLOWER (src[1])) | |
770 | { | |
771 | case 'b': | |
772 | op->mode |= INDEXB | direction; | |
773 | break; | |
774 | case 'w': | |
775 | op->mode |= INDEXW | direction; | |
776 | break; | |
777 | case 'l': | |
778 | op->mode |= INDEXL | direction; | |
779 | break; | |
780 | default: | |
781 | as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); | |
782 | } | |
783 | src += 2; | |
784 | op->reg &= 7; | |
785 | } | |
786 | else | |
787 | op->mode |= DISP | direction; | |
1b680e4f | 788 | src = skip_colonthing (src, &op->mode); |
252b5132 RH |
789 | |
790 | if (*src != ')' && '(') | |
791 | { | |
792 | as_bad (_("expected @(exp, reg16)")); | |
793 | return; | |
794 | } | |
795 | *ptr = src + 1; | |
252b5132 RH |
796 | return; |
797 | } | |
798 | len = parse_reg (src, &mode, &num, direction); | |
799 | ||
800 | if (len) | |
801 | { | |
802 | src += len; | |
7ee7b84d | 803 | if (*src == '+' || *src == '-') |
252b5132 | 804 | { |
d4e2de6b NC |
805 | if (((mode & SIZE) != PSIZE) |
806 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
807 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 808 | as_bad (_("Wrong size pointer register for architecture.")); |
7ee7b84d | 809 | op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; |
252b5132 | 810 | op->reg = num; |
7ee7b84d | 811 | src++; |
252b5132 RH |
812 | *ptr = src; |
813 | return; | |
814 | } | |
d4e2de6b NC |
815 | if (((mode & SIZE) != PSIZE) |
816 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
817 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 RH |
818 | as_bad (_("Wrong size pointer register for architecture.")); |
819 | ||
820 | op->mode = direction | IND | PSIZE; | |
821 | op->reg = num; | |
822 | *ptr = src; | |
823 | ||
824 | return; | |
825 | } | |
826 | else | |
827 | { | |
828 | /* must be a symbol */ | |
829 | ||
830 | op->mode = ABS | direction; | |
1b680e4f | 831 | *ptr = parse_exp (src, op); |
252b5132 RH |
832 | return; |
833 | } | |
834 | } | |
835 | ||
252b5132 RH |
836 | if (*src == '#') |
837 | { | |
252b5132 | 838 | op->mode = IMM; |
1b680e4f | 839 | *ptr = parse_exp (src + 1, op); |
252b5132 RH |
840 | return; |
841 | } | |
7ee7b84d MS |
842 | else if (strncmp (src, "mach", 4) == 0 || |
843 | strncmp (src, "macl", 4) == 0 || | |
844 | strncmp (src, "MACH", 4) == 0 || | |
845 | strncmp (src, "MACL", 4) == 0) | |
252b5132 | 846 | { |
7ee7b84d | 847 | op->reg = TOLOWER (src[3]) == 'l'; |
252b5132 RH |
848 | op->mode = MACREG; |
849 | *ptr = src + 4; | |
850 | return; | |
851 | } | |
852 | else | |
853 | { | |
1b680e4f RS |
854 | op->mode = PCREL; |
855 | *ptr = parse_exp (src, op); | |
252b5132 RH |
856 | } |
857 | } | |
858 | ||
70d6ecf3 | 859 | static char * |
b54a3392 | 860 | get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) |
252b5132 RH |
861 | { |
862 | char *ptr = op_end; | |
863 | ||
864 | switch (noperands) | |
865 | { | |
866 | case 0: | |
252b5132 RH |
867 | break; |
868 | ||
869 | case 1: | |
870 | ptr++; | |
7ee7b84d | 871 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
872 | if (*ptr == ',') |
873 | { | |
874 | ptr++; | |
7ee7b84d | 875 | get_operand (&ptr, operand + 1, DST); |
252b5132 | 876 | } |
252b5132 | 877 | break; |
70d6ecf3 | 878 | |
252b5132 RH |
879 | case 2: |
880 | ptr++; | |
7ee7b84d | 881 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
882 | if (*ptr == ',') |
883 | ptr++; | |
7ee7b84d MS |
884 | get_operand (&ptr, operand + 1, DST); |
885 | break; | |
886 | ||
887 | case 3: | |
888 | ptr++; | |
889 | get_operand (&ptr, operand + 0, SRC); | |
890 | if (*ptr == ',') | |
891 | ptr++; | |
892 | get_operand (&ptr, operand + 1, DST); | |
893 | if (*ptr == ',') | |
894 | ptr++; | |
895 | get_operand (&ptr, operand + 2, OP3); | |
252b5132 RH |
896 | break; |
897 | ||
898 | default: | |
899 | abort (); | |
900 | } | |
901 | ||
252b5132 RH |
902 | return ptr; |
903 | } | |
904 | ||
7ee7b84d MS |
905 | /* MOVA has special requirements. Rather than adding twice the amount of |
906 | addressing modes, we simply special case it a bit. */ | |
907 | static void | |
908 | get_mova_operands (char *op_end, struct h8_op *operand) | |
909 | { | |
910 | char *ptr = op_end; | |
911 | ||
912 | if (ptr[1] != '@' || ptr[2] != '(') | |
913 | goto error; | |
914 | ptr += 3; | |
915 | operand[0].mode = 0; | |
1b680e4f | 916 | ptr = parse_exp (ptr, &operand[0]); |
7ee7b84d MS |
917 | |
918 | if (*ptr !=',') | |
919 | goto error; | |
920 | ptr++; | |
921 | get_operand (&ptr, operand + 1, DST); | |
922 | ||
923 | if (*ptr =='.') | |
924 | { | |
925 | ptr++; | |
926 | switch (*ptr++) | |
927 | { | |
928 | case 'b': case 'B': | |
929 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
930 | break; | |
931 | case 'w': case 'W': | |
932 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
933 | break; | |
934 | case 'l': case 'L': | |
935 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
936 | break; | |
937 | default: | |
938 | goto error; | |
939 | } | |
940 | } | |
941 | else if ((operand[1].mode & MODE) == LOWREG) | |
942 | { | |
943 | switch (operand[1].mode & SIZE) | |
944 | { | |
945 | case L_8: | |
946 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
947 | break; | |
948 | case L_16: | |
949 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
950 | break; | |
951 | case L_32: | |
952 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
953 | break; | |
954 | default: | |
955 | goto error; | |
956 | } | |
957 | } | |
958 | else | |
959 | goto error; | |
960 | ||
961 | if (*ptr++ != ')' || *ptr++ != ',') | |
962 | goto error; | |
963 | get_operand (&ptr, operand + 2, OP3); | |
964 | /* See if we can use the short form of MOVA. */ | |
965 | if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) | |
966 | && (operand[2].mode & MODE) == REG | |
967 | && (operand[1].reg & 7) == (operand[2].reg & 7)) | |
968 | { | |
969 | operand[1].mode = operand[2].mode = 0; | |
970 | operand[0].reg = operand[2].reg & 7; | |
971 | } | |
972 | return; | |
973 | ||
974 | error: | |
975 | as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); | |
7ee7b84d MS |
976 | } |
977 | ||
978 | static void | |
979 | get_rtsl_operands (char *ptr, struct h8_op *operand) | |
980 | { | |
2132e3a3 AM |
981 | int mode, len, type = 0; |
982 | unsigned int num, num2; | |
7ee7b84d MS |
983 | |
984 | ptr++; | |
985 | if (*ptr == '(') | |
986 | { | |
987 | ptr++; | |
988 | type = 1; | |
989 | } | |
990 | len = parse_reg (ptr, &mode, &num, SRC); | |
991 | if (len == 0 || (mode & MODE) != REG) | |
992 | { | |
993 | as_bad (_("expected register")); | |
994 | return; | |
995 | } | |
0613284f RS |
996 | ptr += len; |
997 | if (*ptr == '-') | |
7ee7b84d | 998 | { |
0613284f | 999 | len = parse_reg (++ptr, &mode, &num2, SRC); |
7ee7b84d MS |
1000 | if (len == 0 || (mode & MODE) != REG) |
1001 | { | |
1002 | as_bad (_("expected register")); | |
1003 | return; | |
1004 | } | |
1005 | ptr += len; | |
7ee7b84d MS |
1006 | /* CONST_xxx are used as placeholders in the opcode table. */ |
1007 | num = num2 - num; | |
2132e3a3 | 1008 | if (num > 3) |
7ee7b84d MS |
1009 | { |
1010 | as_bad (_("invalid register list")); | |
1011 | return; | |
1012 | } | |
1013 | } | |
1014 | else | |
1015 | num2 = num, num = 0; | |
0613284f RS |
1016 | if (type == 1 && *ptr++ != ')') |
1017 | { | |
1018 | as_bad (_("expected closing paren")); | |
1019 | return; | |
1020 | } | |
7ee7b84d MS |
1021 | operand[0].mode = RS32; |
1022 | operand[1].mode = RD32; | |
1023 | operand[0].reg = num; | |
1024 | operand[1].reg = num2; | |
1025 | } | |
1026 | ||
252b5132 RH |
1027 | /* Passed a pointer to a list of opcodes which use different |
1028 | addressing modes, return the opcode which matches the opcodes | |
70d6ecf3 | 1029 | provided. */ |
3048287a | 1030 | |
a720f7bc | 1031 | static const struct h8_instruction * |
b54a3392 KH |
1032 | get_specific (const struct h8_instruction *instruction, |
1033 | struct h8_op *operands, int size) | |
252b5132 | 1034 | { |
a720f7bc | 1035 | const struct h8_instruction *this_try = instruction; |
7ee7b84d | 1036 | const struct h8_instruction *found_other = 0, *found_mismatched = 0; |
252b5132 | 1037 | int found = 0; |
a720f7bc | 1038 | int this_index = instruction->idx; |
7ee7b84d | 1039 | int noperands = 0; |
252b5132 RH |
1040 | |
1041 | /* There's only one ldm/stm and it's easier to just | |
1042 | get out quick for them. */ | |
7ee7b84d MS |
1043 | if (OP_KIND (instruction->opcode->how) == O_LDM |
1044 | || OP_KIND (instruction->opcode->how) == O_STM) | |
252b5132 RH |
1045 | return this_try; |
1046 | ||
7ee7b84d MS |
1047 | while (noperands < 3 && operands[noperands].mode != 0) |
1048 | noperands++; | |
1049 | ||
a720f7bc | 1050 | while (this_index == instruction->idx && !found) |
252b5132 | 1051 | { |
7ee7b84d | 1052 | int this_size; |
252b5132 | 1053 | |
7ee7b84d | 1054 | found = 1; |
a720f7bc | 1055 | this_try = instruction++; |
7ee7b84d | 1056 | this_size = this_try->opcode->how & SN; |
252b5132 | 1057 | |
7ee7b84d MS |
1058 | if (this_try->noperands != noperands) |
1059 | found = 0; | |
1060 | else if (this_try->noperands > 0) | |
252b5132 | 1061 | { |
3048287a | 1062 | int i; |
252b5132 RH |
1063 | |
1064 | for (i = 0; i < this_try->noperands && found; i++) | |
1065 | { | |
a720f7bc | 1066 | op_type op = this_try->opcode->args.nib[i]; |
7ee7b84d MS |
1067 | int op_mode = op & MODE; |
1068 | int op_size = op & SIZE; | |
252b5132 | 1069 | int x = operands[i].mode; |
7ee7b84d MS |
1070 | int x_mode = x & MODE; |
1071 | int x_size = x & SIZE; | |
252b5132 | 1072 | |
7ee7b84d | 1073 | if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) |
252b5132 | 1074 | { |
7ee7b84d MS |
1075 | if ((x_size == L_8 && (operands[i].reg & 8) == 0) |
1076 | || (x_size == L_16 && (operands[i].reg & 8) == 8)) | |
1077 | as_warn (_("can't use high part of register in operand %d"), i); | |
1078 | ||
1079 | if (x_size != op_size) | |
1080 | found = 0; | |
252b5132 | 1081 | } |
7ee7b84d | 1082 | else if (op_mode == REG) |
252b5132 | 1083 | { |
7ee7b84d MS |
1084 | if (x_mode == LOWREG) |
1085 | x_mode = REG; | |
1086 | if (x_mode != REG) | |
252b5132 RH |
1087 | found = 0; |
1088 | ||
7ee7b84d MS |
1089 | if (x_size == L_P) |
1090 | x_size = (Hmode ? L_32 : L_16); | |
1091 | if (op_size == L_P) | |
1092 | op_size = (Hmode ? L_32 : L_16); | |
252b5132 | 1093 | |
70d6ecf3 | 1094 | /* The size of the reg is v important. */ |
7ee7b84d | 1095 | if (op_size != x_size) |
252b5132 RH |
1096 | found = 0; |
1097 | } | |
7ee7b84d | 1098 | else if (op_mode & CTRL) /* control register */ |
252b5132 | 1099 | { |
7ee7b84d MS |
1100 | if (!(x_mode & CTRL)) |
1101 | found = 0; | |
1102 | ||
1103 | switch (x_mode) | |
1104 | { | |
1105 | case CCR: | |
1106 | if (op_mode != CCR && | |
1107 | op_mode != CCR_EXR && | |
1108 | op_mode != CC_EX_VB_SB) | |
1109 | found = 0; | |
1110 | break; | |
1111 | case EXR: | |
1112 | if (op_mode != EXR && | |
1113 | op_mode != CCR_EXR && | |
1114 | op_mode != CC_EX_VB_SB) | |
1115 | found = 0; | |
1116 | break; | |
1117 | case MACH: | |
1118 | if (op_mode != MACH && | |
1119 | op_mode != MACREG) | |
1120 | found = 0; | |
1121 | break; | |
1122 | case MACL: | |
1123 | if (op_mode != MACL && | |
1124 | op_mode != MACREG) | |
1125 | found = 0; | |
1126 | break; | |
1127 | case VBR: | |
1128 | if (op_mode != VBR && | |
1129 | op_mode != VBR_SBR && | |
1130 | op_mode != CC_EX_VB_SB) | |
1131 | found = 0; | |
1132 | break; | |
1133 | case SBR: | |
1134 | if (op_mode != SBR && | |
1135 | op_mode != VBR_SBR && | |
1136 | op_mode != CC_EX_VB_SB) | |
1137 | found = 0; | |
1138 | break; | |
1139 | } | |
1140 | } | |
1141 | else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) | |
1142 | { | |
1143 | operands[i].mode &= ~MODE; | |
252b5132 | 1144 | operands[i].mode |= ABSJMP; |
70d6ecf3 | 1145 | /* But it may not be 24 bits long. */ |
7ee7b84d | 1146 | if (x_mode == ABS && !Hmode) |
252b5132 RH |
1147 | { |
1148 | operands[i].mode &= ~SIZE; | |
1149 | operands[i].mode |= L_16; | |
1150 | } | |
7ee7b84d MS |
1151 | if ((operands[i].mode & SIZE) == L_32 |
1152 | && (op_mode & SIZE) != L_32) | |
1153 | found = 0; | |
252b5132 | 1154 | } |
7ee7b84d | 1155 | else if (x_mode == IMM && op_mode != IMM) |
252b5132 | 1156 | { |
7ee7b84d MS |
1157 | offsetT num = operands[i].exp.X_add_number; |
1158 | if (op_mode == KBIT || op_mode == DBIT) | |
1159 | /* This is ok if the immediate value is sensible. */; | |
1160 | else if (op_mode == CONST_2) | |
1161 | found = num == 2; | |
1162 | else if (op_mode == CONST_4) | |
1163 | found = num == 4; | |
1164 | else if (op_mode == CONST_8) | |
1165 | found = num == 8; | |
1166 | else if (op_mode == CONST_16) | |
1167 | found = num == 16; | |
1168 | else | |
1169 | found = 0; | |
252b5132 | 1170 | } |
7ee7b84d | 1171 | else if (op_mode == PCREL && op_mode == x_mode) |
252b5132 | 1172 | { |
ba18dd6f | 1173 | /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: |
7ee7b84d | 1174 | If x_size is L_8, promote it. */ |
ba18dd6f AO |
1175 | if (OP_KIND (this_try->opcode->how) == O_MOVSD |
1176 | || OP_KIND (this_try->opcode->how) == O_BSRBC | |
1177 | || OP_KIND (this_try->opcode->how) == O_BSRBS) | |
7ee7b84d MS |
1178 | if (x_size == L_8) |
1179 | x_size = L_16; | |
1180 | ||
70d6ecf3 | 1181 | /* The size of the displacement is important. */ |
7ee7b84d | 1182 | if (op_size != x_size) |
252b5132 RH |
1183 | found = 0; |
1184 | } | |
7ee7b84d MS |
1185 | else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS |
1186 | || op_mode == INDEXB || op_mode == INDEXW | |
1187 | || op_mode == INDEXL) | |
1188 | && op_mode == x_mode) | |
252b5132 RH |
1189 | { |
1190 | /* Promote a L_24 to L_32 if it makes us match. */ | |
7ee7b84d | 1191 | if (x_size == L_24 && op_size == L_32) |
252b5132 | 1192 | { |
7ee7b84d MS |
1193 | x &= ~SIZE; |
1194 | x |= x_size = L_32; | |
252b5132 | 1195 | } |
7ee7b84d | 1196 | |
7ee7b84d | 1197 | if (((x_size == L_16 && op_size == L_16U) |
2d0d09ca | 1198 | || (x_size == L_8 && op_size == L_8U) |
7ee7b84d MS |
1199 | || (x_size == L_3 && op_size == L_3NZ)) |
1200 | /* We're deliberately more permissive for ABS modes. */ | |
1201 | && (op_mode == ABS | |
1202 | || constant_fits_size_p (operands + i, op_size, | |
1203 | op & NO_SYMBOLS))) | |
1204 | x_size = op_size; | |
1205 | ||
1206 | if (x_size != 0 && op_size != x_size) | |
1207 | found = 0; | |
1208 | else if (x_size == 0 | |
1209 | && ! constant_fits_size_p (operands + i, op_size, | |
1210 | op & NO_SYMBOLS)) | |
252b5132 RH |
1211 | found = 0; |
1212 | } | |
7ee7b84d | 1213 | else if (op_mode != x_mode) |
252b5132 RH |
1214 | { |
1215 | found = 0; | |
70d6ecf3 | 1216 | } |
252b5132 RH |
1217 | } |
1218 | } | |
7ee7b84d MS |
1219 | if (found) |
1220 | { | |
1221 | if ((this_try->opcode->available == AV_H8SX && ! SXmode) | |
d4ea8842 | 1222 | || (this_try->opcode->available == AV_H8S && ! Smode) |
7ee7b84d MS |
1223 | || (this_try->opcode->available == AV_H8H && ! Hmode)) |
1224 | found = 0, found_other = this_try; | |
1225 | else if (this_size != size && (this_size != SN && size != SN)) | |
1226 | found_mismatched = this_try, found = 0; | |
1227 | ||
1228 | } | |
252b5132 RH |
1229 | } |
1230 | if (found) | |
1231 | return this_try; | |
7ee7b84d MS |
1232 | if (found_other) |
1233 | { | |
1234 | as_warn (_("Opcode `%s' with these operand types not available in %s mode"), | |
1235 | found_other->opcode->name, | |
1236 | (! Hmode && ! Smode ? "H8/300" | |
1237 | : SXmode ? "H8sx" | |
1238 | : Smode ? "H8/300S" | |
1239 | : "H8/300H")); | |
1240 | } | |
1241 | else if (found_mismatched) | |
1242 | { | |
1243 | as_warn (_("mismatch between opcode size and operand size")); | |
1244 | return found_mismatched; | |
1245 | } | |
1246 | return 0; | |
252b5132 RH |
1247 | } |
1248 | ||
1249 | static void | |
b54a3392 | 1250 | check_operand (struct h8_op *operand, unsigned int width, char *string) |
252b5132 RH |
1251 | { |
1252 | if (operand->exp.X_add_symbol == 0 | |
1253 | && operand->exp.X_op_symbol == 0) | |
1254 | { | |
70d6ecf3 AM |
1255 | /* No symbol involved, let's look at offset, it's dangerous if |
1256 | any of the high bits are not 0 or ff's, find out by oring or | |
1257 | anding with the width and seeing if the answer is 0 or all | |
1258 | fs. */ | |
252b5132 | 1259 | |
7ee7b84d | 1260 | if (! constant_fits_width_p (operand, width)) |
252b5132 | 1261 | { |
70d6ecf3 | 1262 | if (width == 255 |
252b5132 RH |
1263 | && (operand->exp.X_add_number & 0xff00) == 0xff00) |
1264 | { | |
1265 | /* Just ignore this one - which happens when trying to | |
1266 | fit a 16 bit address truncated into an 8 bit address | |
1267 | of something like bset. */ | |
1268 | } | |
166e23f9 KH |
1269 | else if (strcmp (string, "@") == 0 |
1270 | && width == 0xffff | |
1271 | && (operand->exp.X_add_number & 0xff8000) == 0xff8000) | |
1272 | { | |
1273 | /* Just ignore this one - which happens when trying to | |
1274 | fit a 24 bit address truncated into a 16 bit address | |
1275 | of something like mov.w. */ | |
1276 | } | |
70d6ecf3 | 1277 | else |
252b5132 RH |
1278 | { |
1279 | as_warn (_("operand %s0x%lx out of range."), string, | |
1280 | (unsigned long) operand->exp.X_add_number); | |
1281 | } | |
1282 | } | |
1283 | } | |
252b5132 RH |
1284 | } |
1285 | ||
1286 | /* RELAXMODE has one of 3 values: | |
1287 | ||
1288 | 0 Output a "normal" reloc, no relaxing possible for this insn/reloc | |
1289 | ||
1290 | 1 Output a relaxable 24bit absolute mov.w address relocation | |
1291 | (may relax into a 16bit absolute address). | |
1292 | ||
1293 | 2 Output a relaxable 16/24 absolute mov.b address relocation | |
1294 | (may relax into an 8bit absolute address). */ | |
1295 | ||
1296 | static void | |
b54a3392 | 1297 | do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode) |
252b5132 RH |
1298 | { |
1299 | int idx; | |
1300 | int size; | |
1301 | int where; | |
7ee7b84d | 1302 | char *bytes = frag_now->fr_literal + offset; |
252b5132 | 1303 | |
7ee7b84d | 1304 | char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; |
252b5132 RH |
1305 | |
1306 | if (operand->exp.X_add_symbol == 0) | |
1307 | { | |
252b5132 RH |
1308 | switch (operand->mode & SIZE) |
1309 | { | |
1310 | case L_2: | |
1311 | check_operand (operand, 0x3, t); | |
7ee7b84d | 1312 | bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); |
252b5132 RH |
1313 | break; |
1314 | case L_3: | |
7ee7b84d | 1315 | case L_3NZ: |
252b5132 | 1316 | check_operand (operand, 0x7, t); |
7ee7b84d MS |
1317 | bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); |
1318 | break; | |
1319 | case L_4: | |
1320 | check_operand (operand, 0xF, t); | |
1321 | bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); | |
1322 | break; | |
1323 | case L_5: | |
1324 | check_operand (operand, 0x1F, t); | |
1325 | bytes[0] |= operand->exp.X_add_number & 31; | |
252b5132 RH |
1326 | break; |
1327 | case L_8: | |
7ee7b84d | 1328 | case L_8U: |
252b5132 | 1329 | check_operand (operand, 0xff, t); |
7ee7b84d | 1330 | bytes[0] |= operand->exp.X_add_number; |
252b5132 RH |
1331 | break; |
1332 | case L_16: | |
7ee7b84d | 1333 | case L_16U: |
252b5132 | 1334 | check_operand (operand, 0xffff, t); |
7ee7b84d MS |
1335 | bytes[0] |= operand->exp.X_add_number >> 8; |
1336 | bytes[1] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1337 | break; |
1338 | case L_24: | |
1339 | check_operand (operand, 0xffffff, t); | |
7ee7b84d MS |
1340 | bytes[0] |= operand->exp.X_add_number >> 16; |
1341 | bytes[1] |= operand->exp.X_add_number >> 8; | |
1342 | bytes[2] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1343 | break; |
1344 | ||
1345 | case L_32: | |
70d6ecf3 | 1346 | /* This should be done with bfd. */ |
7ee7b84d MS |
1347 | bytes[0] |= operand->exp.X_add_number >> 24; |
1348 | bytes[1] |= operand->exp.X_add_number >> 16; | |
1349 | bytes[2] |= operand->exp.X_add_number >> 8; | |
1350 | bytes[3] |= operand->exp.X_add_number >> 0; | |
4132022d AM |
1351 | if (relaxmode != 0) |
1352 | { | |
1353 | idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; | |
1354 | fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); | |
1355 | } | |
252b5132 RH |
1356 | break; |
1357 | } | |
252b5132 RH |
1358 | } |
1359 | else | |
1360 | { | |
1361 | switch (operand->mode & SIZE) | |
1362 | { | |
252b5132 RH |
1363 | case L_24: |
1364 | case L_32: | |
1365 | size = 4; | |
1366 | where = (operand->mode & SIZE) == L_24 ? -1 : 0; | |
1367 | if (relaxmode == 2) | |
1368 | idx = R_MOV24B1; | |
1369 | else if (relaxmode == 1) | |
1370 | idx = R_MOVL1; | |
1371 | else | |
1372 | idx = R_RELLONG; | |
1373 | break; | |
1374 | default: | |
70d6ecf3 | 1375 | as_bad (_("Can't work out size of operand.\n")); |
252b5132 | 1376 | case L_16: |
7ee7b84d | 1377 | case L_16U: |
252b5132 RH |
1378 | size = 2; |
1379 | where = 0; | |
1380 | if (relaxmode == 2) | |
1381 | idx = R_MOV16B1; | |
1382 | else | |
1383 | idx = R_RELWORD; | |
4132022d AM |
1384 | operand->exp.X_add_number = |
1385 | ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
7ee7b84d | 1386 | operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; |
252b5132 RH |
1387 | break; |
1388 | case L_8: | |
1389 | size = 1; | |
1390 | where = 0; | |
1391 | idx = R_RELBYTE; | |
4132022d AM |
1392 | operand->exp.X_add_number = |
1393 | ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
7ee7b84d | 1394 | operand->exp.X_add_number |= bytes[0]; |
252b5132 RH |
1395 | } |
1396 | ||
1397 | fix_new_exp (frag_now, | |
1398 | offset + where, | |
1399 | size, | |
1400 | &operand->exp, | |
1401 | 0, | |
1402 | idx); | |
1403 | } | |
252b5132 RH |
1404 | } |
1405 | ||
70d6ecf3 | 1406 | /* Now we know what sort of opcodes it is, let's build the bytes. */ |
3048287a | 1407 | |
252b5132 | 1408 | static void |
b54a3392 | 1409 | build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) |
252b5132 | 1410 | { |
3048287a | 1411 | int i; |
252b5132 | 1412 | char *output = frag_more (this_try->length); |
a720f7bc | 1413 | op_type *nibble_ptr = this_try->opcode->data.nib; |
252b5132 RH |
1414 | op_type c; |
1415 | unsigned int nibble_count = 0; | |
7ee7b84d | 1416 | int op_at[3]; |
3048287a | 1417 | int nib = 0; |
252b5132 | 1418 | int movb = 0; |
7ee7b84d | 1419 | char asnibbles[100]; |
252b5132 | 1420 | char *p = asnibbles; |
7ee7b84d | 1421 | int high, low; |
252b5132 | 1422 | |
d4ea8842 | 1423 | if (!Hmode && this_try->opcode->available != AV_H8) |
252b5132 | 1424 | as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), |
a720f7bc | 1425 | this_try->opcode->name); |
d4ea8842 MS |
1426 | else if (!Smode |
1427 | && this_try->opcode->available != AV_H8 | |
1428 | && this_try->opcode->available != AV_H8H) | |
1429 | as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), | |
1430 | this_try->opcode->name); | |
1431 | else if (!SXmode | |
1432 | && this_try->opcode->available != AV_H8 | |
1433 | && this_try->opcode->available != AV_H8H | |
1434 | && this_try->opcode->available != AV_H8S) | |
1435 | as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), | |
1436 | this_try->opcode->name); | |
252b5132 | 1437 | |
7ee7b84d | 1438 | while (*nibble_ptr != (op_type) E) |
252b5132 RH |
1439 | { |
1440 | int d; | |
7ee7b84d MS |
1441 | |
1442 | nib = 0; | |
252b5132 RH |
1443 | c = *nibble_ptr++; |
1444 | ||
7ee7b84d | 1445 | d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; |
252b5132 RH |
1446 | |
1447 | if (c < 16) | |
3048287a | 1448 | nib = c; |
252b5132 RH |
1449 | else |
1450 | { | |
7ee7b84d MS |
1451 | int c2 = c & MODE; |
1452 | ||
1453 | if (c2 == REG || c2 == LOWREG | |
1454 | || c2 == IND || c2 == PREINC || c2 == PREDEC | |
1455 | || c2 == POSTINC || c2 == POSTDEC) | |
1456 | { | |
1457 | nib = operand[d].reg; | |
1458 | if (c2 == LOWREG) | |
1459 | nib &= 7; | |
1460 | } | |
1461 | ||
1462 | else if (c & CTRL) /* Control reg operand. */ | |
3048287a NC |
1463 | nib = operand[d].reg; |
1464 | ||
252b5132 | 1465 | else if ((c & DISPREG) == (DISPREG)) |
7ee7b84d MS |
1466 | { |
1467 | nib = operand[d].reg; | |
1468 | } | |
1469 | else if (c2 == ABS) | |
252b5132 RH |
1470 | { |
1471 | operand[d].mode = c; | |
7ee7b84d | 1472 | op_at[d] = nibble_count; |
252b5132 RH |
1473 | nib = 0; |
1474 | } | |
7ee7b84d MS |
1475 | else if (c2 == IMM || c2 == PCREL || c2 == ABS |
1476 | || (c & ABSJMP) || c2 == DISP) | |
252b5132 RH |
1477 | { |
1478 | operand[d].mode = c; | |
7ee7b84d | 1479 | op_at[d] = nibble_count; |
252b5132 RH |
1480 | nib = 0; |
1481 | } | |
7ee7b84d | 1482 | else if ((c & IGNORE) || (c & DATA)) |
3048287a NC |
1483 | nib = 0; |
1484 | ||
7ee7b84d | 1485 | else if (c2 == DBIT) |
252b5132 RH |
1486 | { |
1487 | switch (operand[0].exp.X_add_number) | |
1488 | { | |
1489 | case 1: | |
1490 | nib = c; | |
1491 | break; | |
1492 | case 2: | |
1493 | nib = 0x8 | c; | |
1494 | break; | |
1495 | default: | |
1496 | as_bad (_("Need #1 or #2 here")); | |
1497 | } | |
1498 | } | |
7ee7b84d | 1499 | else if (c2 == KBIT) |
252b5132 RH |
1500 | { |
1501 | switch (operand[0].exp.X_add_number) | |
1502 | { | |
1503 | case 1: | |
1504 | nib = 0; | |
1505 | break; | |
1506 | case 2: | |
1507 | nib = 8; | |
1508 | break; | |
1509 | case 4: | |
1510 | if (!Hmode) | |
1511 | as_warn (_("#4 not valid on H8/300.")); | |
1512 | nib = 9; | |
1513 | break; | |
1514 | ||
1515 | default: | |
1516 | as_bad (_("Need #1 or #2 here")); | |
1517 | break; | |
1518 | } | |
70d6ecf3 | 1519 | /* Stop it making a fix. */ |
252b5132 RH |
1520 | operand[0].mode = 0; |
1521 | } | |
1522 | ||
1523 | if (c & MEMRELAX) | |
3048287a | 1524 | operand[d].mode |= MEMRELAX; |
252b5132 RH |
1525 | |
1526 | if (c & B31) | |
3048287a | 1527 | nib |= 0x8; |
252b5132 | 1528 | |
7ee7b84d MS |
1529 | if (c & B21) |
1530 | nib |= 0x4; | |
1531 | ||
1532 | if (c & B11) | |
1533 | nib |= 0x2; | |
1534 | ||
1535 | if (c & B01) | |
1536 | nib |= 0x1; | |
1537 | ||
1538 | if (c2 == MACREG) | |
252b5132 | 1539 | { |
f0c56b90 NC |
1540 | if (operand[0].mode == MACREG) |
1541 | /* stmac has mac[hl] as the first operand. */ | |
1542 | nib = 2 + operand[0].reg; | |
1543 | else | |
1544 | /* ldmac has mac[hl] as the second operand. */ | |
1545 | nib = 2 + operand[1].reg; | |
252b5132 RH |
1546 | } |
1547 | } | |
1548 | nibble_count++; | |
1549 | ||
1550 | *p++ = nib; | |
1551 | } | |
1552 | ||
1553 | /* Disgusting. Why, oh why didn't someone ask us for advice | |
1554 | on the assembler format. */ | |
7ee7b84d | 1555 | if (OP_KIND (this_try->opcode->how) == O_LDM) |
252b5132 | 1556 | { |
7ee7b84d MS |
1557 | high = (operand[1].reg >> 8) & 0xf; |
1558 | low = (operand[1].reg) & 0xf; | |
252b5132 | 1559 | asnibbles[2] = high - low; |
7ee7b84d MS |
1560 | asnibbles[7] = high; |
1561 | } | |
1562 | else if (OP_KIND (this_try->opcode->how) == O_STM) | |
1563 | { | |
1564 | high = (operand[0].reg >> 8) & 0xf; | |
1565 | low = (operand[0].reg) & 0xf; | |
1566 | asnibbles[2] = high - low; | |
1567 | asnibbles[7] = low; | |
252b5132 RH |
1568 | } |
1569 | ||
1570 | for (i = 0; i < this_try->length; i++) | |
3048287a | 1571 | output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; |
252b5132 | 1572 | |
ca9a79a1 NC |
1573 | /* Note if this is a movb or a bit manipulation instruction |
1574 | there is a special relaxation which only applies. */ | |
1575 | if ( this_try->opcode->how == O (O_MOV, SB) | |
1576 | || this_try->opcode->how == O (O_BCLR, SB) | |
1577 | || this_try->opcode->how == O (O_BAND, SB) | |
1578 | || this_try->opcode->how == O (O_BIAND, SB) | |
1579 | || this_try->opcode->how == O (O_BILD, SB) | |
1580 | || this_try->opcode->how == O (O_BIOR, SB) | |
1581 | || this_try->opcode->how == O (O_BIST, SB) | |
1582 | || this_try->opcode->how == O (O_BIXOR, SB) | |
1583 | || this_try->opcode->how == O (O_BLD, SB) | |
1584 | || this_try->opcode->how == O (O_BNOT, SB) | |
1585 | || this_try->opcode->how == O (O_BOR, SB) | |
1586 | || this_try->opcode->how == O (O_BSET, SB) | |
1587 | || this_try->opcode->how == O (O_BST, SB) | |
1588 | || this_try->opcode->how == O (O_BTST, SB) | |
1589 | || this_try->opcode->how == O (O_BXOR, SB)) | |
252b5132 RH |
1590 | movb = 1; |
1591 | ||
70d6ecf3 | 1592 | /* Output any fixes. */ |
7ee7b84d | 1593 | for (i = 0; i < this_try->noperands; i++) |
252b5132 RH |
1594 | { |
1595 | int x = operand[i].mode; | |
7ee7b84d | 1596 | int x_mode = x & MODE; |
252b5132 | 1597 | |
7ee7b84d MS |
1598 | if (x_mode == IMM || x_mode == DISP) |
1599 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1600 | op_at[i] & 1, operand + i, (x & MEMRELAX) != 0); | |
3048287a | 1601 | |
7ee7b84d MS |
1602 | else if (x_mode == ABS) |
1603 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1604 | op_at[i] & 1, operand + i, | |
1605 | (x & MEMRELAX) ? movb + 1 : 0); | |
3048287a | 1606 | |
7ee7b84d | 1607 | else if (x_mode == PCREL) |
252b5132 | 1608 | { |
7ee7b84d | 1609 | int size16 = (x & SIZE) == L_16; |
252b5132 RH |
1610 | int size = size16 ? 2 : 1; |
1611 | int type = size16 ? R_PCRWORD : R_PCRBYTE; | |
36ed2fff | 1612 | fixS *fixP; |
252b5132 RH |
1613 | |
1614 | check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); | |
1615 | ||
1616 | if (operand[i].exp.X_add_number & 1) | |
3048287a NC |
1617 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1618 | (unsigned long) operand->exp.X_add_number); | |
36ed2fff JL |
1619 | #ifndef OBJ_ELF |
1620 | /* The COFF port has always been off by one, changing it | |
1621 | now would be an incompatible change, so we leave it as-is. | |
1622 | ||
1623 | We don't want to do this for ELF as we want to be | |
1624 | compatible with the proposed ELF format from Hitachi. */ | |
252b5132 | 1625 | operand[i].exp.X_add_number -= 1; |
36ed2fff | 1626 | #endif |
7ee7b84d MS |
1627 | if (size16) |
1628 | { | |
1629 | operand[i].exp.X_add_number = | |
1630 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
1631 | } | |
1632 | else | |
1633 | { | |
1634 | operand[i].exp.X_add_number = | |
1635 | ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
1636 | } | |
1637 | ||
1638 | /* For BRA/S. */ | |
1639 | if (! size16) | |
1640 | operand[i].exp.X_add_number |= output[op_at[i] / 2]; | |
252b5132 | 1641 | |
36ed2fff | 1642 | fixP = fix_new_exp (frag_now, |
7ee7b84d | 1643 | output - frag_now->fr_literal + op_at[i] / 2, |
36ed2fff JL |
1644 | size, |
1645 | &operand[i].exp, | |
1646 | 1, | |
1647 | type); | |
1648 | fixP->fx_signed = 1; | |
252b5132 | 1649 | } |
7ee7b84d | 1650 | else if (x_mode == MEMIND) |
252b5132 | 1651 | { |
252b5132 RH |
1652 | check_operand (operand + i, 0xff, "@@"); |
1653 | fix_new_exp (frag_now, | |
1654 | output - frag_now->fr_literal + 1, | |
1655 | 1, | |
1656 | &operand[i].exp, | |
1657 | 0, | |
1658 | R_MEM_INDIRECT); | |
1659 | } | |
7ee7b84d MS |
1660 | else if (x_mode == VECIND) |
1661 | { | |
1662 | check_operand (operand + i, 0x7f, "@@"); | |
1663 | /* FIXME: approximating the effect of "B31" here... | |
1664 | This is very hackish, and ought to be done a better way. */ | |
1665 | operand[i].exp.X_add_number |= 0x80; | |
1666 | fix_new_exp (frag_now, | |
1667 | output - frag_now->fr_literal + 1, | |
1668 | 1, | |
1669 | &operand[i].exp, | |
1670 | 0, | |
1671 | R_MEM_INDIRECT); | |
1672 | } | |
252b5132 RH |
1673 | else if (x & ABSJMP) |
1674 | { | |
3c1ba8a3 | 1675 | int where = 0; |
7ee7b84d | 1676 | bfd_reloc_code_real_type reloc_type = R_JMPL1; |
3c1ba8a3 JL |
1677 | |
1678 | #ifdef OBJ_ELF | |
1679 | /* To be compatible with the proposed H8 ELF format, we | |
1680 | want the relocation's offset to point to the first byte | |
1681 | that will be modified, not to the start of the instruction. */ | |
7ee7b84d MS |
1682 | |
1683 | if ((operand->mode & SIZE) == L_32) | |
1684 | { | |
1685 | where = 2; | |
1686 | reloc_type = R_RELLONG; | |
1687 | } | |
1688 | else | |
1689 | where = 1; | |
3c1ba8a3 | 1690 | #endif |
de342d07 | 1691 | |
70d6ecf3 | 1692 | /* This jmp may be a jump or a branch. */ |
252b5132 | 1693 | |
7ee7b84d MS |
1694 | check_operand (operand + i, |
1695 | SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, | |
1696 | "@"); | |
3048287a | 1697 | |
252b5132 | 1698 | if (operand[i].exp.X_add_number & 1) |
3048287a NC |
1699 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1700 | (unsigned long) operand->exp.X_add_number); | |
1701 | ||
252b5132 | 1702 | if (!Hmode) |
70d6ecf3 | 1703 | operand[i].exp.X_add_number = |
4132022d | 1704 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
252b5132 | 1705 | fix_new_exp (frag_now, |
3c1ba8a3 | 1706 | output - frag_now->fr_literal + where, |
252b5132 RH |
1707 | 4, |
1708 | &operand[i].exp, | |
1709 | 0, | |
7ee7b84d | 1710 | reloc_type); |
252b5132 RH |
1711 | } |
1712 | } | |
252b5132 RH |
1713 | } |
1714 | ||
70d6ecf3 AM |
1715 | /* Try to give an intelligent error message for common and simple to |
1716 | detect errors. */ | |
3048287a | 1717 | |
252b5132 | 1718 | static void |
b54a3392 KH |
1719 | clever_message (const struct h8_instruction *instruction, |
1720 | struct h8_op *operand) | |
252b5132 | 1721 | { |
70d6ecf3 | 1722 | /* Find out if there was more than one possible opcode. */ |
252b5132 | 1723 | |
a720f7bc | 1724 | if ((instruction + 1)->idx != instruction->idx) |
252b5132 | 1725 | { |
3048287a | 1726 | int argn; |
252b5132 | 1727 | |
70d6ecf3 AM |
1728 | /* Only one opcode of this flavour, try to guess which operand |
1729 | didn't match. */ | |
a720f7bc | 1730 | for (argn = 0; argn < instruction->noperands; argn++) |
252b5132 | 1731 | { |
a720f7bc | 1732 | switch (instruction->opcode->args.nib[argn]) |
252b5132 RH |
1733 | { |
1734 | case RD16: | |
1735 | if (operand[argn].mode != RD16) | |
1736 | { | |
1737 | as_bad (_("destination operand must be 16 bit register")); | |
1738 | return; | |
1739 | ||
1740 | } | |
1741 | break; | |
1742 | ||
1743 | case RS8: | |
252b5132 RH |
1744 | if (operand[argn].mode != RS8) |
1745 | { | |
1746 | as_bad (_("source operand must be 8 bit register")); | |
1747 | return; | |
1748 | } | |
1749 | break; | |
1750 | ||
1751 | case ABS16DST: | |
1752 | if (operand[argn].mode != ABS16DST) | |
1753 | { | |
1754 | as_bad (_("destination operand must be 16bit absolute address")); | |
1755 | return; | |
1756 | } | |
1757 | break; | |
1758 | case RD8: | |
1759 | if (operand[argn].mode != RD8) | |
1760 | { | |
1761 | as_bad (_("destination operand must be 8 bit register")); | |
1762 | return; | |
1763 | } | |
1764 | break; | |
1765 | ||
252b5132 RH |
1766 | case ABS16SRC: |
1767 | if (operand[argn].mode != ABS16SRC) | |
1768 | { | |
1769 | as_bad (_("source operand must be 16bit absolute address")); | |
1770 | return; | |
1771 | } | |
1772 | break; | |
1773 | ||
1774 | } | |
1775 | } | |
1776 | } | |
1777 | as_bad (_("invalid operands")); | |
1778 | } | |
1779 | ||
d4ea8842 | 1780 | |
1b680e4f RS |
1781 | /* If OPERAND is part of an address, adjust its size and value given |
1782 | that it addresses SIZE bytes. | |
d4ea8842 | 1783 | |
1b680e4f RS |
1784 | This function decides how big non-immediate constants are when no |
1785 | size was explicitly given. It also scales down the assembly-level | |
d4ea8842 MS |
1786 | displacement in an @(d:2,ERn) operand. */ |
1787 | ||
1788 | static void | |
b54a3392 | 1789 | fix_operand_size (struct h8_op *operand, int size) |
d4ea8842 | 1790 | { |
1b680e4f | 1791 | if (SXmode && (operand->mode & MODE) == DISP) |
d4ea8842 MS |
1792 | { |
1793 | /* If the user didn't specify an operand width, see if we | |
1794 | can use @(d:2,ERn). */ | |
1b680e4f RS |
1795 | if ((operand->mode & SIZE) == 0 |
1796 | && operand->exp.X_add_symbol == 0 | |
1797 | && operand->exp.X_op_symbol == 0 | |
d4ea8842 MS |
1798 | && (operand->exp.X_add_number == size |
1799 | || operand->exp.X_add_number == size * 2 | |
1800 | || operand->exp.X_add_number == size * 3)) | |
1801 | operand->mode |= L_2; | |
1802 | ||
1803 | /* Scale down the displacement in an @(d:2,ERn) operand. | |
1804 | X_add_number then contains the desired field value. */ | |
1805 | if ((operand->mode & SIZE) == L_2) | |
1806 | { | |
1807 | if (operand->exp.X_add_number % size != 0) | |
1808 | as_warn (_("operand/size mis-match")); | |
1809 | operand->exp.X_add_number /= size; | |
1810 | } | |
1811 | } | |
1812 | ||
d4ea8842 MS |
1813 | if ((operand->mode & SIZE) == 0) |
1814 | switch (operand->mode & MODE) | |
1815 | { | |
1816 | case DISP: | |
1817 | case INDEXB: | |
1818 | case INDEXW: | |
1819 | case INDEXL: | |
1820 | case ABS: | |
1b680e4f RS |
1821 | /* Pick a 24-bit address unless we know that a 16-bit address |
1822 | is safe. get_specific() will relax L_24 into L_32 where | |
1823 | necessary. */ | |
1824 | if (Hmode | |
d4e2de6b | 1825 | && !Nmode |
1b680e4f RS |
1826 | && (operand->exp.X_add_number < -32768 |
1827 | || operand->exp.X_add_number > 32767 | |
1828 | || operand->exp.X_add_symbol != 0 | |
1829 | || operand->exp.X_op_symbol != 0)) | |
1830 | operand->mode |= L_24; | |
1831 | else | |
1832 | operand->mode |= L_16; | |
1833 | break; | |
1834 | ||
1835 | case PCREL: | |
1836 | /* This condition is long standing, though somewhat suspect. */ | |
1837 | if (operand->exp.X_add_number > -128 | |
1838 | && operand->exp.X_add_number < 127) | |
1839 | operand->mode |= L_8; | |
1840 | else | |
1841 | operand->mode |= L_16; | |
d4ea8842 MS |
1842 | break; |
1843 | } | |
1844 | } | |
1845 | ||
1846 | ||
70d6ecf3 AM |
1847 | /* This is the guts of the machine-dependent assembler. STR points to |
1848 | a machine dependent instruction. This function is supposed to emit | |
1849 | the frags/bytes it assembles. */ | |
3048287a | 1850 | |
252b5132 | 1851 | void |
b54a3392 | 1852 | md_assemble (char *str) |
252b5132 RH |
1853 | { |
1854 | char *op_start; | |
1855 | char *op_end; | |
7ee7b84d | 1856 | struct h8_op operand[3]; |
a720f7bc KD |
1857 | const struct h8_instruction *instruction; |
1858 | const struct h8_instruction *prev_instruction; | |
252b5132 RH |
1859 | |
1860 | char *dot = 0; | |
0c0b9be0 | 1861 | char *slash = 0; |
252b5132 | 1862 | char c; |
7ee7b84d | 1863 | int size, i; |
252b5132 | 1864 | |
70d6ecf3 | 1865 | /* Drop leading whitespace. */ |
252b5132 RH |
1866 | while (*str == ' ') |
1867 | str++; | |
1868 | ||
70d6ecf3 | 1869 | /* Find the op code end. */ |
252b5132 RH |
1870 | for (op_start = op_end = str; |
1871 | *op_end != 0 && *op_end != ' '; | |
1872 | op_end++) | |
1873 | { | |
1874 | if (*op_end == '.') | |
1875 | { | |
1876 | dot = op_end + 1; | |
1877 | *op_end = 0; | |
1878 | op_end += 2; | |
1879 | break; | |
1880 | } | |
0c0b9be0 AO |
1881 | else if (*op_end == '/' && ! slash) |
1882 | slash = op_end; | |
252b5132 RH |
1883 | } |
1884 | ||
252b5132 RH |
1885 | if (op_end == op_start) |
1886 | { | |
1887 | as_bad (_("can't find opcode ")); | |
1888 | } | |
1889 | c = *op_end; | |
1890 | ||
1891 | *op_end = 0; | |
1892 | ||
0c0b9be0 AO |
1893 | /* The assembler stops scanning the opcode at slashes, so it fails |
1894 | to make characters following them lower case. Fix them. */ | |
1895 | if (slash) | |
1896 | while (*++slash) | |
1897 | *slash = TOLOWER (*slash); | |
1898 | ||
a720f7bc KD |
1899 | instruction = (const struct h8_instruction *) |
1900 | hash_find (opcode_hash_control, op_start); | |
252b5132 | 1901 | |
a720f7bc | 1902 | if (instruction == NULL) |
252b5132 RH |
1903 | { |
1904 | as_bad (_("unknown opcode")); | |
1905 | return; | |
1906 | } | |
1907 | ||
70d6ecf3 | 1908 | /* We used to set input_line_pointer to the result of get_operands, |
252b5132 RH |
1909 | but that is wrong. Our caller assumes we don't change it. */ |
1910 | ||
7ee7b84d MS |
1911 | operand[0].mode = 0; |
1912 | operand[1].mode = 0; | |
1913 | operand[2].mode = 0; | |
1914 | ||
1915 | if (OP_KIND (instruction->opcode->how) == O_MOVAB | |
1916 | || OP_KIND (instruction->opcode->how) == O_MOVAW | |
1917 | || OP_KIND (instruction->opcode->how) == O_MOVAL) | |
1918 | get_mova_operands (op_end, operand); | |
1919 | else if (OP_KIND (instruction->opcode->how) == O_RTEL | |
1920 | || OP_KIND (instruction->opcode->how) == O_RTSL) | |
1921 | get_rtsl_operands (op_end, operand); | |
1922 | else | |
1923 | get_operands (instruction->noperands, op_end, operand); | |
1924 | ||
252b5132 | 1925 | *op_end = c; |
a720f7bc | 1926 | prev_instruction = instruction; |
252b5132 | 1927 | |
4892e510 NC |
1928 | /* Now we have operands from instruction. |
1929 | Let's check them out for ldm and stm. */ | |
1930 | if (OP_KIND (instruction->opcode->how) == O_LDM) | |
1931 | { | |
1932 | /* The first operand must be @er7+, and the | |
1933 | second operand must be a register pair. */ | |
1934 | if ((operand[0].mode != RSINC) | |
1935 | || (operand[0].reg != 7) | |
1936 | || ((operand[1].reg & 0x80000000) == 0)) | |
1937 | as_bad (_("invalid operand in ldm")); | |
1938 | } | |
1939 | else if (OP_KIND (instruction->opcode->how) == O_STM) | |
1940 | { | |
1941 | /* The first operand must be a register pair, | |
1942 | and the second operand must be @-er7. */ | |
1943 | if (((operand[0].reg & 0x80000000) == 0) | |
1944 | || (operand[1].mode != RDDEC) | |
1945 | || (operand[1].reg != 7)) | |
1946 | as_bad (_("invalid operand in stm")); | |
1947 | } | |
1948 | ||
252b5132 RH |
1949 | size = SN; |
1950 | if (dot) | |
1951 | { | |
0c0b9be0 | 1952 | switch (TOLOWER (*dot)) |
252b5132 RH |
1953 | { |
1954 | case 'b': | |
1955 | size = SB; | |
1956 | break; | |
1957 | ||
1958 | case 'w': | |
1959 | size = SW; | |
1960 | break; | |
1961 | ||
1962 | case 'l': | |
1963 | size = SL; | |
1964 | break; | |
1965 | } | |
1966 | } | |
7ee7b84d MS |
1967 | if (OP_KIND (instruction->opcode->how) == O_MOVAB || |
1968 | OP_KIND (instruction->opcode->how) == O_MOVAW || | |
1969 | OP_KIND (instruction->opcode->how) == O_MOVAL) | |
252b5132 | 1970 | { |
d4ea8842 MS |
1971 | switch (operand[0].mode & MODE) |
1972 | { | |
7ee7b84d MS |
1973 | case INDEXB: |
1974 | default: | |
d4ea8842 | 1975 | fix_operand_size (&operand[1], 1); |
7ee7b84d MS |
1976 | break; |
1977 | case INDEXW: | |
d4ea8842 | 1978 | fix_operand_size (&operand[1], 2); |
7ee7b84d MS |
1979 | break; |
1980 | case INDEXL: | |
d4ea8842 | 1981 | fix_operand_size (&operand[1], 4); |
7ee7b84d | 1982 | break; |
252b5132 RH |
1983 | } |
1984 | } | |
7ee7b84d MS |
1985 | else |
1986 | { | |
d4ea8842 MS |
1987 | for (i = 0; i < 3 && operand[i].mode != 0; i++) |
1988 | switch (size) | |
1989 | { | |
7ee7b84d MS |
1990 | case SN: |
1991 | case SB: | |
1992 | default: | |
d4ea8842 | 1993 | fix_operand_size (&operand[i], 1); |
7ee7b84d MS |
1994 | break; |
1995 | case SW: | |
d4ea8842 | 1996 | fix_operand_size (&operand[i], 2); |
7ee7b84d MS |
1997 | break; |
1998 | case SL: | |
d4ea8842 | 1999 | fix_operand_size (&operand[i], 4); |
7ee7b84d MS |
2000 | break; |
2001 | } | |
2002 | } | |
252b5132 | 2003 | |
d4ea8842 MS |
2004 | instruction = get_specific (instruction, operand, size); |
2005 | ||
2006 | if (instruction == 0) | |
2007 | { | |
2008 | /* Couldn't find an opcode which matched the operands. */ | |
2009 | char *where = frag_more (2); | |
2010 | ||
2011 | where[0] = 0x0; | |
2012 | where[1] = 0x0; | |
2013 | clever_message (prev_instruction, operand); | |
2014 | ||
2015 | return; | |
2016 | } | |
2017 | ||
a720f7bc | 2018 | build_bytes (instruction, operand); |
2c8714f2 NC |
2019 | |
2020 | #ifdef BFD_ASSEMBLER | |
2021 | dwarf2_emit_insn (instruction->length); | |
2022 | #endif | |
252b5132 RH |
2023 | } |
2024 | ||
5facebfc | 2025 | #ifndef BFD_ASSEMBLER |
252b5132 | 2026 | void |
b54a3392 | 2027 | tc_crawl_symbol_chain (object_headers *headers ATTRIBUTE_UNUSED) |
252b5132 RH |
2028 | { |
2029 | printf (_("call to tc_crawl_symbol_chain \n")); | |
2030 | } | |
f333765f | 2031 | #endif |
252b5132 RH |
2032 | |
2033 | symbolS * | |
b54a3392 | 2034 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
2035 | { |
2036 | return 0; | |
2037 | } | |
2038 | ||
5facebfc | 2039 | #ifndef BFD_ASSEMBLER |
252b5132 | 2040 | void |
b54a3392 | 2041 | tc_headers_hook (object_headers *headers ATTRIBUTE_UNUSED) |
252b5132 RH |
2042 | { |
2043 | printf (_("call to tc_headers_hook \n")); | |
2044 | } | |
f333765f | 2045 | #endif |
252b5132 RH |
2046 | |
2047 | /* Various routines to kill one day */ | |
2048 | /* Equal to MAX_PRECISION in atof-ieee.c */ | |
2049 | #define MAX_LITTLENUMS 6 | |
2050 | ||
70d6ecf3 AM |
2051 | /* Turn a string in input_line_pointer into a floating point constant |
2052 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
bc0d738a | 2053 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
70d6ecf3 | 2054 | returned, or NULL on OK. */ |
bc0d738a | 2055 | |
252b5132 | 2056 | char * |
b54a3392 | 2057 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
2058 | { |
2059 | int prec; | |
2060 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2061 | LITTLENUM_TYPE *wordP; | |
2062 | char *t; | |
252b5132 RH |
2063 | |
2064 | switch (type) | |
2065 | { | |
2066 | case 'f': | |
2067 | case 'F': | |
2068 | case 's': | |
2069 | case 'S': | |
2070 | prec = 2; | |
2071 | break; | |
2072 | ||
2073 | case 'd': | |
2074 | case 'D': | |
2075 | case 'r': | |
2076 | case 'R': | |
2077 | prec = 4; | |
2078 | break; | |
2079 | ||
2080 | case 'x': | |
2081 | case 'X': | |
2082 | prec = 6; | |
2083 | break; | |
2084 | ||
2085 | case 'p': | |
2086 | case 'P': | |
2087 | prec = 6; | |
2088 | break; | |
2089 | ||
2090 | default: | |
2091 | *sizeP = 0; | |
2092 | return _("Bad call to MD_ATOF()"); | |
2093 | } | |
2094 | t = atof_ieee (input_line_pointer, type, words); | |
2095 | if (t) | |
2096 | input_line_pointer = t; | |
2097 | ||
2098 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
2099 | for (wordP = words; prec--;) | |
2100 | { | |
2101 | md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); | |
2102 | litP += sizeof (LITTLENUM_TYPE); | |
2103 | } | |
2104 | return 0; | |
2105 | } | |
2106 | \f | |
5a38dc70 | 2107 | const char *md_shortopts = ""; |
252b5132 RH |
2108 | struct option md_longopts[] = { |
2109 | {NULL, no_argument, NULL, 0} | |
2110 | }; | |
70d6ecf3 AM |
2111 | |
2112 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 RH |
2113 | |
2114 | int | |
b54a3392 | 2115 | md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) |
252b5132 RH |
2116 | { |
2117 | return 0; | |
2118 | } | |
2119 | ||
2120 | void | |
b54a3392 | 2121 | md_show_usage (FILE *stream ATTRIBUTE_UNUSED) |
252b5132 RH |
2122 | { |
2123 | } | |
2124 | \f | |
b54a3392 | 2125 | void tc_aout_fix_to_chars (void); |
3048287a | 2126 | |
252b5132 | 2127 | void |
b54a3392 | 2128 | tc_aout_fix_to_chars (void) |
252b5132 RH |
2129 | { |
2130 | printf (_("call to tc_aout_fix_to_chars \n")); | |
2131 | abort (); | |
2132 | } | |
2133 | ||
2134 | void | |
b54a3392 | 2135 | md_convert_frag ( |
36ed2fff | 2136 | #ifdef BFD_ASSEMBLER |
b54a3392 | 2137 | bfd *headers ATTRIBUTE_UNUSED, |
36ed2fff | 2138 | #else |
b54a3392 | 2139 | object_headers *headers ATTRIBUTE_UNUSED, |
36ed2fff | 2140 | #endif |
b54a3392 KH |
2141 | segT seg ATTRIBUTE_UNUSED, |
2142 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
2143 | { |
2144 | printf (_("call to md_convert_frag \n")); | |
2145 | abort (); | |
2146 | } | |
2147 | ||
3c1ba8a3 JL |
2148 | #ifdef BFD_ASSEMBLER |
2149 | valueT | |
b54a3392 | 2150 | md_section_align (segT segment, valueT size) |
3c1ba8a3 JL |
2151 | { |
2152 | int align = bfd_get_section_alignment (stdoutput, segment); | |
2153 | return ((size + (1 << align) - 1) & (-1 << align)); | |
2154 | } | |
2155 | #else | |
70d6ecf3 | 2156 | valueT |
b54a3392 | 2157 | md_section_align (segT seg, valueT size) |
252b5132 | 2158 | { |
70d6ecf3 | 2159 | return ((size + (1 << section_alignment[(int) seg]) - 1) |
cc8a6dd0 | 2160 | & (-1 << section_alignment[(int) seg])); |
252b5132 | 2161 | } |
3c1ba8a3 JL |
2162 | #endif |
2163 | ||
252b5132 RH |
2164 | |
2165 | void | |
55cf6793 | 2166 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 RH |
2167 | { |
2168 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
a161fe53 | 2169 | long val = *valP; |
252b5132 RH |
2170 | |
2171 | switch (fixP->fx_size) | |
2172 | { | |
2173 | case 1: | |
2174 | *buf++ = val; | |
2175 | break; | |
2176 | case 2: | |
2177 | *buf++ = (val >> 8); | |
2178 | *buf++ = val; | |
2179 | break; | |
2180 | case 4: | |
2181 | *buf++ = (val >> 24); | |
2182 | *buf++ = (val >> 16); | |
2183 | *buf++ = (val >> 8); | |
2184 | *buf++ = val; | |
2185 | break; | |
2186 | default: | |
2187 | abort (); | |
2188 | } | |
94f592af NC |
2189 | |
2190 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) | |
2191 | fixP->fx_done = 1; | |
252b5132 RH |
2192 | } |
2193 | ||
2194 | int | |
b54a3392 KH |
2195 | md_estimate_size_before_relax (register fragS *fragP ATTRIBUTE_UNUSED, |
2196 | register segT segment_type ATTRIBUTE_UNUSED) | |
252b5132 RH |
2197 | { |
2198 | printf (_("call tomd_estimate_size_before_relax \n")); | |
2199 | abort (); | |
2200 | } | |
2201 | ||
70d6ecf3 | 2202 | /* Put number into target byte order. */ |
252b5132 | 2203 | void |
b54a3392 | 2204 | md_number_to_chars (char *ptr, valueT use, int nbytes) |
252b5132 RH |
2205 | { |
2206 | number_to_chars_bigendian (ptr, use, nbytes); | |
2207 | } | |
70d6ecf3 | 2208 | |
252b5132 | 2209 | long |
b54a3392 | 2210 | md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 RH |
2211 | { |
2212 | abort (); | |
2213 | } | |
2214 | ||
5facebfc | 2215 | #ifndef BFD_ASSEMBLER |
252b5132 | 2216 | void |
b54a3392 | 2217 | tc_reloc_mangle (fixS *fix_ptr, struct internal_reloc *intr, bfd_vma base) |
252b5132 RH |
2218 | { |
2219 | symbolS *symbol_ptr; | |
2220 | ||
2221 | symbol_ptr = fix_ptr->fx_addsy; | |
2222 | ||
2223 | /* If this relocation is attached to a symbol then it's ok | |
70d6ecf3 | 2224 | to output it. */ |
252b5132 RH |
2225 | if (fix_ptr->fx_r_type == TC_CONS_RELOC) |
2226 | { | |
2227 | /* cons likes to create reloc32's whatever the size of the reloc.. | |
2228 | */ | |
2229 | switch (fix_ptr->fx_size) | |
2230 | { | |
2231 | case 4: | |
2232 | intr->r_type = R_RELLONG; | |
2233 | break; | |
2234 | case 2: | |
2235 | intr->r_type = R_RELWORD; | |
2236 | break; | |
2237 | case 1: | |
2238 | intr->r_type = R_RELBYTE; | |
2239 | break; | |
2240 | default: | |
2241 | abort (); | |
252b5132 | 2242 | } |
252b5132 RH |
2243 | } |
2244 | else | |
2245 | { | |
2246 | intr->r_type = fix_ptr->fx_r_type; | |
2247 | } | |
2248 | ||
2249 | intr->r_vaddr = fix_ptr->fx_frag->fr_address + fix_ptr->fx_where + base; | |
2250 | intr->r_offset = fix_ptr->fx_offset; | |
2251 | ||
2252 | if (symbol_ptr) | |
2253 | { | |
2254 | if (symbol_ptr->sy_number != -1) | |
2255 | intr->r_symndx = symbol_ptr->sy_number; | |
2256 | else | |
2257 | { | |
2258 | symbolS *segsym; | |
2259 | ||
2260 | /* This case arises when a reference is made to `.'. */ | |
2261 | segsym = seg_info (S_GET_SEGMENT (symbol_ptr))->dot; | |
2262 | if (segsym == NULL) | |
2263 | intr->r_symndx = -1; | |
2264 | else | |
2265 | { | |
2266 | intr->r_symndx = segsym->sy_number; | |
2267 | intr->r_offset += S_GET_VALUE (symbol_ptr); | |
2268 | } | |
2269 | } | |
2270 | } | |
2271 | else | |
2272 | intr->r_symndx = -1; | |
252b5132 | 2273 | } |
5facebfc | 2274 | #else /* BFD_ASSEMBLER */ |
f333765f | 2275 | arelent * |
b54a3392 | 2276 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
f333765f JL |
2277 | { |
2278 | arelent *rel; | |
2279 | bfd_reloc_code_real_type r_type; | |
2280 | ||
de342d07 JL |
2281 | if (fixp->fx_addsy && fixp->fx_subsy) |
2282 | { | |
2283 | if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) | |
2284 | || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) | |
2285 | { | |
2286 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2287 | "Difference of symbols in different sections is not supported"); | |
2288 | return NULL; | |
2289 | } | |
2290 | } | |
2291 | ||
f333765f JL |
2292 | rel = (arelent *) xmalloc (sizeof (arelent)); |
2293 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
2294 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
2295 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2296 | rel->addend = fixp->fx_offset; | |
2297 | ||
2298 | r_type = fixp->fx_r_type; | |
2299 | ||
2300 | #define DEBUG 0 | |
2301 | #if DEBUG | |
2302 | fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); | |
2303 | fflush(stderr); | |
2304 | #endif | |
2305 | rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); | |
2306 | if (rel->howto == NULL) | |
2307 | { | |
2308 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2309 | _("Cannot represent relocation type %s"), | |
2310 | bfd_get_reloc_code_name (r_type)); | |
2311 | return NULL; | |
2312 | } | |
2313 | ||
2314 | return rel; | |
2315 | } | |
2316 | #endif |