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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
89e7505f
L		 36#ifdef TE_LINUX
37/* Default to compress debug sections for Linux. */
151411f8 38enum compressed_debug_section_type flag_compress_debug
189ebcf9 39 = COMPRESS_DEBUG_GABI_ZLIB;
89e7505f
L		 40#endif
41
252b5132
RH		 42#ifndef REGISTER_WARNINGS
43#define REGISTER_WARNINGS 1
44#endif
45
c3332e24 46#ifndef INFER_ADDR_PREFIX
eecb386c 47#define INFER_ADDR_PREFIX 1
c3332e24
AM		 48#endif
49
29b0f896
AM		 50#ifndef DEFAULT_ARCH
51#define DEFAULT_ARCH "i386"
246fcdee 52#endif
252b5132 53
edde18a5
AM		 54#ifndef INLINE
55#if __GNUC__ >= 2
56#define INLINE __inline__
57#else
58#define INLINE
59#endif
60#endif
61
6305a203
L		 62/* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 67#define WAIT_PREFIX 0
68#define SEG_PREFIX 1
69#define ADDR_PREFIX 2
70#define DATA_PREFIX 3
c32fa91d 71#define REP_PREFIX 4
42164a71 72#define HLE_PREFIX REP_PREFIX
7e8b059b 73#define BND_PREFIX REP_PREFIX
c32fa91d
L		 74#define LOCK_PREFIX 5
75#define REX_PREFIX 6 /* must come last. */
76#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 77
78/* we define the syntax here (modulo base,index,scale syntax) */
79#define REGISTER_PREFIX '%'
80#define IMMEDIATE_PREFIX '$'
81#define ABSOLUTE_PREFIX '*'
82
83/* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85#define WORD_MNEM_SUFFIX 'w'
86#define BYTE_MNEM_SUFFIX 'b'
87#define SHORT_MNEM_SUFFIX 's'
88#define LONG_MNEM_SUFFIX 'l'
89#define QWORD_MNEM_SUFFIX 'q'
90#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 91#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 92#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 93/* Intel Syntax. Use a non-ascii letter since since it never appears
94 in instructions. */
95#define LONG_DOUBLE_MNEM_SUFFIX '\1'
96
97#define END_OF_INSN '\0'
98
99/*
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
104 END.
105 */
106typedef struct
107{
d3ce72d0
NC		 108 const insn_template *start;
109 const insn_template *end;
6305a203
L		 110}
111templates;
112
113/* 386 operand encoding bytes: see 386 book for details of this. */
114typedef struct
115{
116 unsigned int regmem; /* codes register or memory operand */
117 unsigned int reg; /* codes register operand (or extended opcode) */
118 unsigned int mode; /* how to interpret regmem & reg */
119}
120modrm_byte;
121
122/* x86-64 extension prefix. */
123typedef int rex_byte;
124
6305a203
L		 125/* 386 opcode byte to code indirect addressing. */
126typedef struct
127{
128 unsigned base;
129 unsigned index;
130 unsigned scale;
131}
132sib_byte;
133
6305a203
L		 134/* x86 arch names, types and features */
135typedef struct
136{
137 const char *name; /* arch name */
8a2c8fef 138 unsigned int len; /* arch string length */
6305a203
L		 139 enum processor_type type; /* arch type */
140 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 141 unsigned int skip; /* show_arch should skip this. */
22109423 142 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 143}
144arch_entry;
145
78f12dd3 146static void update_code_flag (int, int);
e3bb37b5
L		 147static void set_code_flag (int);
148static void set_16bit_gcc_code_flag (int);
149static void set_intel_syntax (int);
1efbbeb4 150static void set_intel_mnemonic (int);
db51cc60 151static void set_allow_index_reg (int);
7bab8ab5 152static void set_check (int);
e3bb37b5 153static void set_cpu_arch (int);
6482c264 154#ifdef TE_PE
e3bb37b5 155static void pe_directive_secrel (int);
6482c264 156#endif
e3bb37b5
L		 157static void signed_cons (int);
158static char *output_invalid (int c);
ee86248c
JB		 159static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 const char *);
161static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 const char *);
a7619375 163static int i386_att_operand (char *);
e3bb37b5 164static int i386_intel_operand (char *, int);
ee86248c
JB		 165static int i386_intel_simplify (expressionS *);
166static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 167static const reg_entry *parse_register (char *, char **);
168static char *parse_insn (char *, char *);
169static char *parse_operands (char *, const char *);
170static void swap_operands (void);
4d456e3d 171static void swap_2_operands (int, int);
e3bb37b5
L		 172static void optimize_imm (void);
173static void optimize_disp (void);
d3ce72d0 174static const insn_template *match_template (void);
e3bb37b5
L		 175static int check_string (void);
176static int process_suffix (void);
177static int check_byte_reg (void);
178static int check_long_reg (void);
179static int check_qword_reg (void);
180static int check_word_reg (void);
181static int finalize_imm (void);
182static int process_operands (void);
183static const seg_entry *build_modrm_byte (void);
184static void output_insn (void);
185static void output_imm (fragS *, offsetT);
186static void output_disp (fragS *, offsetT);
29b0f896 187#ifndef I386COFF
e3bb37b5 188static void s_bss (int);
252b5132 189#endif
17d4e2a2
L		 190#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191static void handle_large_common (int small ATTRIBUTE_UNUSED);
192#endif
252b5132 193
a847613f 194static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 195
43234a1e
L		 196/* This struct describes rounding control and SAE in the instruction. */
197struct RC_Operation
198{
199 enum rc_type
200 {
201 rne = 0,
202 rd,
203 ru,
204 rz,
205 saeonly
206 } type;
207 int operand;
208};
209
210static struct RC_Operation rc_op;
211
212/* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215struct Mask_Operation
216{
217 const reg_entry *mask;
218 unsigned int zeroing;
219 /* The operand where this operation is associated. */
220 int operand;
221};
222
223static struct Mask_Operation mask_op;
224
225/* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 broadcast factor. */
227struct Broadcast_Operation
228{
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
230 int type;
231
232 /* Index of broadcasted operand. */
233 int operand;
234};
235
236static struct Broadcast_Operation broadcast_op;
237
c0f3af97
L		 238/* VEX prefix. */
239typedef struct
240{
43234a1e
L		 241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes[4];
c0f3af97
L		 243 unsigned int length;
244 /* Destination or source register specifier. */
245 const reg_entry *register_specifier;
246} vex_prefix;
247
252b5132 248/* 'md_assemble ()' gathers together information and puts it into a
47926f60 249 i386_insn. */
252b5132 250
520dc8e8
AM		 251union i386_op
252 {
253 expressionS *disps;
254 expressionS *imms;
255 const reg_entry *regs;
256 };
257
a65babc9
L		 258enum i386_error
259 {
86e026a4 260 operand_size_mismatch,
a65babc9
L		 261 operand_type_mismatch,
262 register_type_mismatch,
263 number_of_operands_mismatch,
264 invalid_instruction_suffix,
265 bad_imm4,
266 old_gcc_only,
267 unsupported_with_intel_mnemonic,
268 unsupported_syntax,
6c30d220
L		 269 unsupported,
270 invalid_vsib_address,
7bab8ab5 271 invalid_vector_register_set,
43234a1e
L		 272 unsupported_vector_index_register,
273 unsupported_broadcast,
274 broadcast_not_on_src_operand,
275 broadcast_needed,
276 unsupported_masking,
277 mask_not_on_destination,
278 no_default_mask,
279 unsupported_rc_sae,
280 rc_sae_operand_not_last_imm,
281 invalid_register_operand,
282 try_vector_disp8
a65babc9
L		 283 };
284
252b5132
RH		 285struct _i386_insn
286 {
47926f60 287 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 288 insn_template tm;
252b5132 289
7d5e4556
L		 290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
252b5132
RH		 292 char suffix;
293
47926f60 294 /* OPERANDS gives the number of given operands. */
252b5132
RH		 295 unsigned int operands;
296
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
47926f60 299 operands. */
252b5132
RH		 300 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
301
302 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 303 use OP[i] for the corresponding operand. */
40fb9820 304 i386_operand_type types[MAX_OPERANDS];
252b5132 305
520dc8e8
AM		 306 /* Displacement expression, immediate expression, or register for each
307 operand. */
308 union i386_op op[MAX_OPERANDS];
252b5132 309
3e73aa7c
JH		 310 /* Flags for operands. */
311 unsigned int flags[MAX_OPERANDS];
312#define Operand_PCrel 1
313
252b5132 314 /* Relocation type for operand */
f86103b7 315 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 316
252b5132
RH		 317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry *base_reg;
320 const reg_entry *index_reg;
321 unsigned int log2_scale_factor;
322
323 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 324 explicit segment overrides are given. */
ce8a8b2f 325 const seg_entry *seg[2];
252b5132
RH		 326
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
b6169b20 352 /* Swap operand in encoding. */
4473e004 353 unsigned int swap_operand;
891edac4 354
a501d77e
L		 355 /* Prefer 8bit or 32bit displacement in encoding. */
356 enum
357 {
358 disp_encoding_default = 0,
359 disp_encoding_8bit,
360 disp_encoding_32bit
361 } disp_encoding;
f8a5c266 362
d5de92cf
L		 363 /* REP prefix. */
364 const char *rep_prefix;
365
165de32a
L		 366 /* HLE prefix. */
367 const char *hle_prefix;
42164a71 368
7e8b059b
L		 369 /* Have BND prefix. */
370 const char *bnd_prefix;
371
43234a1e
L		 372 /* Need VREX to support upper 16 registers. */
373 int need_vrex;
374
891edac4 375 /* Error message. */
a65babc9 376 enum i386_error error;
252b5132
RH		 377 };
378
379typedef struct _i386_insn i386_insn;
380
43234a1e
L		 381/* Link RC type with corresponding string, that'll be looked for in
382 asm. */
383struct RC_name
384{
385 enum rc_type type;
386 const char *name;
387 unsigned int len;
388};
389
390static const struct RC_name RC_NamesTable[] =
391{
392 { rne, STRING_COMMA_LEN ("rn-sae") },
393 { rd, STRING_COMMA_LEN ("rd-sae") },
394 { ru, STRING_COMMA_LEN ("ru-sae") },
395 { rz, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly, STRING_COMMA_LEN ("sae") },
397};
398
252b5132
RH		 399/* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 401const char extra_symbol_chars[] = "*%-([{"
252b5132 402#ifdef LEX_AT
32137342
NC		 403 "@"
404#endif
405#ifdef LEX_QM
406 "?"
252b5132 407#endif
32137342 408 ;
252b5132 409
29b0f896
AM		 410#if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 412 && !defined (TE_GNU) \
29b0f896 413 && !defined (TE_LINUX) \
8d63c93e
RM		 414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
29b0f896 416 && !defined (TE_FreeBSD) \
5b806d27 417 && !defined (TE_DragonFly) \
29b0f896 418 && !defined (TE_NetBSD)))
252b5132 419/* This array holds the chars that always start a comment. If the
b3b91714
AM		 420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422const char *i386_comment_chars = "#/";
423#define SVR4_COMMENT_CHARS 1
252b5132 424#define PREFIX_SEPARATOR '\\'
252b5132 425
b3b91714
AM		 426#else
427const char *i386_comment_chars = "#";
428#define PREFIX_SEPARATOR '/'
429#endif
430
252b5132
RH		 431/* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 435 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
252b5132 438 '/' isn't otherwise defined. */
b3b91714 439const char line_comment_chars[] = "#/";
252b5132 440
63a0b638 441const char line_separator_chars[] = ";";
252b5132 442
ce8a8b2f
AM		 443/* Chars that can be used to separate mant from exp in floating point
444 nums. */
252b5132
RH		 445const char EXP_CHARS[] = "eE";
446
ce8a8b2f
AM		 447/* Chars that mean this number is a floating point constant
448 As in 0f12.456
449 or 0d1.2345e12. */
252b5132
RH		 450const char FLT_CHARS[] = "fFdDxX";
451
ce8a8b2f 452/* Tables for lexical analysis. */
252b5132
RH		 453static char mnemonic_chars[256];
454static char register_chars[256];
455static char operand_chars[256];
456static char identifier_chars[256];
457static char digit_chars[256];
458
ce8a8b2f 459/* Lexical macros. */
252b5132
RH		 460#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461#define is_operand_char(x) (operand_chars[(unsigned char) x])
462#define is_register_char(x) (register_chars[(unsigned char) x])
463#define is_space_char(x) ((x) == ' ')
464#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465#define is_digit_char(x) (digit_chars[(unsigned char) x])
466
0234cb7c 467/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 468static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
469
470/* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
47926f60 473 assembler instruction). */
252b5132 474static char save_stack[32];
ce8a8b2f 475static char *save_stack_p;
252b5132
RH		 476#define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478#define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
480
47926f60 481/* The instruction we're assembling. */
252b5132
RH		 482static i386_insn i;
483
484/* Possible templates for current insn. */
485static const templates *current_templates;
486
31b2323c
L		 487/* Per instruction expressionS buffers: max displacements & immediates. */
488static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
489static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 490
47926f60 491/* Current operand we are working on. */
ee86248c 492static int this_operand = -1;
252b5132 493
3e73aa7c
JH		 494/* We support four different modes. FLAG_CODE variable is used to distinguish
495 these. */
496
497enum flag_code {
498 CODE_32BIT,
499 CODE_16BIT,
500 CODE_64BIT };
501
502static enum flag_code flag_code;
4fa24527 503static unsigned int object_64bit;
862be3fb 504static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 505static int use_rela_relocations = 0;
506
7af8ed2d
NC		 507#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
510
351f65ca
L		 511/* The ELF ABI to use. */
512enum x86_elf_abi
513{
514 I386_ABI,
7f56bc95
L		 515 X86_64_ABI,
516 X86_64_X32_ABI
351f65ca
L		 517};
518
519static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 520#endif
351f65ca 521
167ad85b
TG		 522#if defined (TE_PE) || defined (TE_PEP)
523/* Use big object file format. */
524static int use_big_obj = 0;
525#endif
526
8dcea932
L		 527#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
528/* 1 if generating code for a shared library. */
529static int shared = 0;
530#endif
531
47926f60
KH		 532/* 1 for intel syntax,
533 0 if att syntax. */
534static int intel_syntax = 0;
252b5132 535
1efbbeb4
L		 536/* 1 for intel mnemonic,
537 0 if att mnemonic. */
538static int intel_mnemonic = !SYSV386_COMPAT;
539
5209009a 540/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 541static int old_gcc = OLDGCC_COMPAT;
542
a60de03c
JB		 543/* 1 if pseudo registers are permitted. */
544static int allow_pseudo_reg = 0;
545
47926f60
KH		 546/* 1 if register prefix % not required. */
547static int allow_naked_reg = 0;
252b5132 548
7e8b059b
L		 549/* 1 if the assembler should add BND prefix for all control-tranferring
550 instructions supporting it, even if this prefix wasn't specified
551 explicitly. */
552static int add_bnd_prefix = 0;
553
ba104c83 554/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 555static int allow_index_reg = 0;
556
d022bddd
IT		 557/* 1 if the assembler should ignore LOCK prefix, even if it was
558 specified explicitly. */
559static int omit_lock_prefix = 0;
560
7bab8ab5 561static enum check_kind
daf50ae7 562 {
7bab8ab5
JB		 563 check_none = 0,
564 check_warning,
565 check_error
daf50ae7 566 }
7bab8ab5 567sse_check, operand_check = check_warning;
daf50ae7 568
2ca3ace5
L		 569/* Register prefix used for error message. */
570static const char *register_prefix = "%";
571
47926f60
KH		 572/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
573 leave, push, and pop instructions so that gcc has the same stack
574 frame as in 32 bit mode. */
575static char stackop_size = '\0';
eecb386c 576
12b55ccc
L		 577/* Non-zero to optimize code alignment. */
578int optimize_align_code = 1;
579
47926f60
KH		 580/* Non-zero to quieten some warnings. */
581static int quiet_warnings = 0;
a38cf1db 582
47926f60
KH		 583/* CPU name. */
584static const char *cpu_arch_name = NULL;
6305a203 585static char *cpu_sub_arch_name = NULL;
a38cf1db 586
47926f60 587/* CPU feature flags. */
40fb9820
L		 588static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
589
ccc9c027
L		 590/* If we have selected a cpu we are generating instructions for. */
591static int cpu_arch_tune_set = 0;
592
9103f4f4 593/* Cpu we are generating instructions for. */
fbf3f584 594enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 595
596/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 597static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 598
ccc9c027 599/* CPU instruction set architecture used. */
fbf3f584 600enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 601
9103f4f4 602/* CPU feature flags of instruction set architecture used. */
fbf3f584 603i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 604
fddf5b5b
AM		 605/* If set, conditional jumps are not automatically promoted to handle
606 larger than a byte offset. */
607static unsigned int no_cond_jump_promotion = 0;
608
c0f3af97
L		 609/* Encode SSE instructions with VEX prefix. */
610static unsigned int sse2avx;
611
539f890d
L		 612/* Encode scalar AVX instructions with specific vector length. */
613static enum
614 {
615 vex128 = 0,
616 vex256
617 } avxscalar;
618
43234a1e
L		 619/* Encode scalar EVEX LIG instructions with specific vector length. */
620static enum
621 {
622 evexl128 = 0,
623 evexl256,
624 evexl512
625 } evexlig;
626
627/* Encode EVEX WIG instructions with specific evex.w. */
628static enum
629 {
630 evexw0 = 0,
631 evexw1
632 } evexwig;
633
d3d3c6db
IT		 634/* Value to encode in EVEX RC bits, for SAE-only instructions. */
635static enum rc_type evexrcig = rne;
636
29b0f896 637/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 638static symbolS *GOT_symbol;
29b0f896 639
a4447b93
RH		 640/* The dwarf2 return column, adjusted for 32 or 64 bit. */
641unsigned int x86_dwarf2_return_column;
642
643/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
644int x86_cie_data_alignment;
645
252b5132 646/* Interface to relax_segment.
fddf5b5b
AM		 647 There are 3 major relax states for 386 jump insns because the
648 different types of jumps add different sizes to frags when we're
649 figuring out what sort of jump to choose to reach a given label. */
252b5132 650
47926f60 651/* Types. */
93c2a809
AM		 652#define UNCOND_JUMP 0
653#define COND_JUMP 1
654#define COND_JUMP86 2
fddf5b5b 655
47926f60 656/* Sizes. */
252b5132
RH		 657#define CODE16 1
658#define SMALL 0
29b0f896 659#define SMALL16 (SMALL | CODE16)
252b5132 660#define BIG 2
29b0f896 661#define BIG16 (BIG | CODE16)
252b5132
RH		 662
663#ifndef INLINE
664#ifdef __GNUC__
665#define INLINE __inline__
666#else
667#define INLINE
668#endif
669#endif
670
fddf5b5b
AM		 671#define ENCODE_RELAX_STATE(type, size) \
672 ((relax_substateT) (((type) << 2) | (size)))
673#define TYPE_FROM_RELAX_STATE(s) \
674 ((s) >> 2)
675#define DISP_SIZE_FROM_RELAX_STATE(s) \
676 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 677
678/* This table is used by relax_frag to promote short jumps to long
679 ones where necessary. SMALL (short) jumps may be promoted to BIG
680 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
681 don't allow a short jump in a 32 bit code segment to be promoted to
682 a 16 bit offset jump because it's slower (requires data size
683 prefix), and doesn't work, unless the destination is in the bottom
684 64k of the code segment (The top 16 bits of eip are zeroed). */
685
686const relax_typeS md_relax_table[] =
687{
24eab124
AM		 688 /* The fields are:
689 1) most positive reach of this state,
690 2) most negative reach of this state,
93c2a809 691 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 692 4) which index into the table to try if we can't fit into this one. */
252b5132 693
fddf5b5b 694 /* UNCOND_JUMP states. */
93c2a809
AM		 695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
697 /* dword jmp adds 4 bytes to frag:
698 0 extra opcode bytes, 4 displacement bytes. */
252b5132 699 {0, 0, 4, 0},
93c2a809
AM		 700 /* word jmp adds 2 byte2 to frag:
701 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 702 {0, 0, 2, 0},
703
93c2a809
AM		 704 /* COND_JUMP states. */
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
707 /* dword conditionals adds 5 bytes to frag:
708 1 extra opcode byte, 4 displacement bytes. */
709 {0, 0, 5, 0},
fddf5b5b 710 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 711 1 extra opcode byte, 2 displacement bytes. */
712 {0, 0, 3, 0},
713
714 /* COND_JUMP86 states. */
715 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
717 /* dword conditionals adds 5 bytes to frag:
718 1 extra opcode byte, 4 displacement bytes. */
719 {0, 0, 5, 0},
720 /* word conditionals add 4 bytes to frag:
721 1 displacement byte and a 3 byte long branch insn. */
722 {0, 0, 4, 0}
252b5132
RH		 723};
724
9103f4f4
L		 725static const arch_entry cpu_arch[] =
726{
89507696
JB		 727 /* Do not replace the first two entries - i386_target_format()
728 relies on them being there in this order. */
8a2c8fef 729 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 730 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 732 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 734 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 736 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 738 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 740 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 742 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 744 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 746 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 748 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 750 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 752 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 754 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 756 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 758 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 760 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 762 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 764 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 766 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 768 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 770 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 772 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 773 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
774 CPU_K1OM_FLAGS, 0, 0 },
81486035
L		 775 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
776 CPU_IAMCU_FLAGS, 0, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 778 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 780 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 782 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 784 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 786 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 788 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 790 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 791 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 792 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 793 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 794 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 795 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
796 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 797 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
798 CPU_BDVER4_FLAGS, 0, 0 },
029f3522 799 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
3739860c 800 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 801 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
802 CPU_BTVER1_FLAGS, 0, 0 },
803 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
804 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 806 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 808 CPU_287_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 810 CPU_387_FLAGS, 0, 0 },
8a2c8fef 811 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 812 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 813 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 814 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 815 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 816 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 817 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 818 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 819 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 820 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 822 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 824 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 826 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 828 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 829 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 830 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 831 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 832 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 833 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 834 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 835 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
836 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 837 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
838 CPU_AVX512F_FLAGS, 0, 0 },
839 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
840 CPU_AVX512CD_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
842 CPU_AVX512ER_FLAGS, 0, 0 },
843 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
844 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 845 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
846 CPU_AVX512DQ_FLAGS, 0, 0 },
847 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
848 CPU_AVX512BW_FLAGS, 0, 0 },
849 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
850 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 852 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 853 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 854 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 855 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
856 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 858 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 860 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 861 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 862 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 863 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
864 CPU_XSAVEC_FLAGS, 0, 0 },
865 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
866 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 867 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 868 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 870 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 872 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 873 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 874 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 875 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 876 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 877 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 878 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 879 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
880 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 882 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 884 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 886 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 888 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 890 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 891 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
892 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 894 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 895 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
896 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 897 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
898 CPU_HLE_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
900 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 901 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
902 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 904 CPU_CLFLUSH_FLAGS, 0, 0 },
905 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
906 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 908 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 910 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 912 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 914 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 916 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 917 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 918 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 920 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 922 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 924 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 925 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
926 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 927 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
928 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 929 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
930 CPU_ADX_FLAGS, 0, 0 },
931 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
932 CPU_RDSEED_FLAGS, 0, 0 },
933 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
934 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 935 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
936 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 937 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
938 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 939 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
940 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 941 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
942 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 943 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
944 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 945 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
946 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 947 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
948 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 949 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
950 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 951 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
952 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 953 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
954 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 955 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
956 CPU_CLZERO_FLAGS, 0, 0 },
9916071f
AP		 957 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
958 CPU_MWAITX_FLAGS, 0, 0 },
e413e4e9
AM		 959};
960
704209c0 961#ifdef I386COFF
a6c24e68
NC		 962/* Like s_lcomm_internal in gas/read.c but the alignment string
963 is allowed to be optional. */
964
965static symbolS *
966pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
967{
968 addressT align = 0;
969
970 SKIP_WHITESPACE ();
971
7ab9ffdd 972 if (needs_align
a6c24e68
NC		 973 && *input_line_pointer == ',')
974 {
975 align = parse_align (needs_align - 1);
7ab9ffdd 976
a6c24e68
NC		 977 if (align == (addressT) -1)
978 return NULL;
979 }
980 else
981 {
982 if (size >= 8)
983 align = 3;
984 else if (size >= 4)
985 align = 2;
986 else if (size >= 2)
987 align = 1;
988 else
989 align = 0;
990 }
991
992 bss_alloc (symbolP, size, align);
993 return symbolP;
994}
995
704209c0 996static void
a6c24e68
NC		 997pe_lcomm (int needs_align)
998{
999 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1000}
704209c0 1001#endif
a6c24e68 1002
29b0f896
AM		 1003const pseudo_typeS md_pseudo_table[] =
1004{
1005#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1006 {"align", s_align_bytes, 0},
1007#else
1008 {"align", s_align_ptwo, 0},
1009#endif
1010 {"arch", set_cpu_arch, 0},
1011#ifndef I386COFF
1012 {"bss", s_bss, 0},
a6c24e68
NC		 1013#else
1014 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1015#endif
1016 {"ffloat", float_cons, 'f'},
1017 {"dfloat", float_cons, 'd'},
1018 {"tfloat", float_cons, 'x'},
1019 {"value", cons, 2},
d182319b 1020 {"slong", signed_cons, 4},
29b0f896
AM		 1021 {"noopt", s_ignore, 0},
1022 {"optim", s_ignore, 0},
1023 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1024 {"code16", set_code_flag, CODE_16BIT},
1025 {"code32", set_code_flag, CODE_32BIT},
1026 {"code64", set_code_flag, CODE_64BIT},
1027 {"intel_syntax", set_intel_syntax, 1},
1028 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1029 {"intel_mnemonic", set_intel_mnemonic, 1},
1030 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1031 {"allow_index_reg", set_allow_index_reg, 1},
1032 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1033 {"sse_check", set_check, 0},
1034 {"operand_check", set_check, 1},
3b22753a
L		 1035#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1036 {"largecomm", handle_large_common, 0},
07a53e5c 1037#else
e3bb37b5 1038 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1039 {"loc", dwarf2_directive_loc, 0},
1040 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1041#endif
6482c264
NC		 1042#ifdef TE_PE
1043 {"secrel32", pe_directive_secrel, 0},
1044#endif
29b0f896
AM		 1045 {0, 0, 0}
1046};
1047
1048/* For interface with expression (). */
1049extern char *input_line_pointer;
1050
1051/* Hash table for instruction mnemonic lookup. */
1052static struct hash_control *op_hash;
1053
1054/* Hash table for register lookup. */
1055static struct hash_control *reg_hash;
1056\f
252b5132 1057void
e3bb37b5 1058i386_align_code (fragS *fragP, int count)
252b5132 1059{
ce8a8b2f
AM		 1060 /* Various efficient no-op patterns for aligning code labels.
1061 Note: Don't try to assemble the instructions in the comments.
1062 0L and 0w are not legal. */
252b5132
RH		 1063 static const char f32_1[] =
1064 {0x90}; /* nop */
1065 static const char f32_2[] =
ccc9c027 1066 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1067 static const char f32_3[] =
1068 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1069 static const char f32_4[] =
1070 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1071 static const char f32_5[] =
1072 {0x90, /* nop */
1073 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1074 static const char f32_6[] =
1075 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1076 static const char f32_7[] =
1077 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1078 static const char f32_8[] =
1079 {0x90, /* nop */
1080 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1081 static const char f32_9[] =
1082 {0x89,0xf6, /* movl %esi,%esi */
1083 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1084 static const char f32_10[] =
1085 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1086 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1087 static const char f32_11[] =
1088 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f32_12[] =
1091 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1092 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1093 static const char f32_13[] =
1094 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1095 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1096 static const char f32_14[] =
1097 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1098 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1099 static const char f16_3[] =
1100 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1101 static const char f16_4[] =
1102 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1103 static const char f16_5[] =
1104 {0x90, /* nop */
1105 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1106 static const char f16_6[] =
1107 {0x89,0xf6, /* mov %si,%si */
1108 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1109 static const char f16_7[] =
1110 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1111 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1112 static const char f16_8[] =
1113 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1114 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1115 static const char jump_31[] =
1116 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1117 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1118 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1119 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1120 static const char *const f32_patt[] = {
1121 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1122 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1123 };
1124 static const char *const f16_patt[] = {
76bc74dc 1125 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1126 };
ccc9c027
L		 1127 /* nopl (%[re]ax) */
1128 static const char alt_3[] =
1129 {0x0f,0x1f,0x00};
1130 /* nopl 0(%[re]ax) */
1131 static const char alt_4[] =
1132 {0x0f,0x1f,0x40,0x00};
1133 /* nopl 0(%[re]ax,%[re]ax,1) */
1134 static const char alt_5[] =
1135 {0x0f,0x1f,0x44,0x00,0x00};
1136 /* nopw 0(%[re]ax,%[re]ax,1) */
1137 static const char alt_6[] =
1138 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1139 /* nopl 0L(%[re]ax) */
1140 static const char alt_7[] =
1141 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1142 /* nopl 0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_8[] =
1144 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1145 /* nopw 0L(%[re]ax,%[re]ax,1) */
1146 static const char alt_9[] =
1147 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1148 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_10[] =
1150 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
80b8656c 1151 static const char *const alt_patt[] = {
ccc9c027 1152 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1153 alt_9, alt_10
ccc9c027 1154 };
252b5132 1155
76bc74dc
L		 1156 /* Only align for at least a positive non-zero boundary. */
1157 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1158 return;
3e73aa7c 1159
ccc9c027
L		 1160 /* We need to decide which NOP sequence to use for 32bit and
1161 64bit. When -mtune= is used:
4eed87de 1162
76bc74dc
L		 1163 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1164 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1165 2. For the rest, alt_patt will be used.
1166
1167 When -mtune= isn't used, alt_patt will be used if
22109423 1168 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1169 be used.
ccc9c027
L		 1170
1171 When -march= or .arch is used, we can't use anything beyond
1172 cpu_arch_isa_flags. */
1173
1174 if (flag_code == CODE_16BIT)
1175 {
ccc9c027 1176 if (count > 8)
33fef721 1177 {
76bc74dc
L		 1178 memcpy (fragP->fr_literal + fragP->fr_fix,
1179 jump_31, count);
1180 /* Adjust jump offset. */
1181 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1182 }
76bc74dc
L		 1183 else
1184 memcpy (fragP->fr_literal + fragP->fr_fix,
1185 f16_patt[count - 1], count);
252b5132 1186 }
33fef721 1187 else
ccc9c027
L		 1188 {
1189 const char *const *patt = NULL;
1190
fbf3f584 1191 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1192 {
1193 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1194 switch (cpu_arch_tune)
1195 {
1196 case PROCESSOR_UNKNOWN:
1197 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1198 optimize with nops. */
1199 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1200 patt = alt_patt;
ccc9c027
L		 1201 else
1202 patt = f32_patt;
1203 break;
ccc9c027
L		 1204 case PROCESSOR_PENTIUM4:
1205 case PROCESSOR_NOCONA:
ef05d495 1206 case PROCESSOR_CORE:
76bc74dc 1207 case PROCESSOR_CORE2:
bd5295b2 1208 case PROCESSOR_COREI7:
3632d14b 1209 case PROCESSOR_L1OM:
7a9068fe 1210 case PROCESSOR_K1OM:
76bc74dc 1211 case PROCESSOR_GENERIC64:
ccc9c027
L		 1212 case PROCESSOR_K6:
1213 case PROCESSOR_ATHLON:
1214 case PROCESSOR_K8:
4eed87de 1215 case PROCESSOR_AMDFAM10:
8aedb9fe 1216 case PROCESSOR_BD:
029f3522 1217 case PROCESSOR_ZNVER:
7b458c12 1218 case PROCESSOR_BT:
80b8656c 1219 patt = alt_patt;
ccc9c027 1220 break;
76bc74dc 1221 case PROCESSOR_I386:
ccc9c027
L		 1222 case PROCESSOR_I486:
1223 case PROCESSOR_PENTIUM:
2dde1948 1224 case PROCESSOR_PENTIUMPRO:
81486035 1225 case PROCESSOR_IAMCU:
ccc9c027
L		 1226 case PROCESSOR_GENERIC32:
1227 patt = f32_patt;
1228 break;
4eed87de 1229 }
ccc9c027
L		 1230 }
1231 else
1232 {
fbf3f584 1233 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1234 {
1235 case PROCESSOR_UNKNOWN:
e6a14101 1236 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1237 PROCESSOR_UNKNOWN. */
1238 abort ();
1239 break;
1240
76bc74dc 1241 case PROCESSOR_I386:
ccc9c027
L		 1242 case PROCESSOR_I486:
1243 case PROCESSOR_PENTIUM:
81486035 1244 case PROCESSOR_IAMCU:
ccc9c027
L		 1245 case PROCESSOR_K6:
1246 case PROCESSOR_ATHLON:
1247 case PROCESSOR_K8:
4eed87de 1248 case PROCESSOR_AMDFAM10:
8aedb9fe 1249 case PROCESSOR_BD:
029f3522 1250 case PROCESSOR_ZNVER:
7b458c12 1251 case PROCESSOR_BT:
ccc9c027
L		 1252 case PROCESSOR_GENERIC32:
1253 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1254 with nops. */
1255 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1256 patt = alt_patt;
ccc9c027
L		 1257 else
1258 patt = f32_patt;
1259 break;
76bc74dc
L		 1260 case PROCESSOR_PENTIUMPRO:
1261 case PROCESSOR_PENTIUM4:
1262 case PROCESSOR_NOCONA:
1263 case PROCESSOR_CORE:
ef05d495 1264 case PROCESSOR_CORE2:
bd5295b2 1265 case PROCESSOR_COREI7:
3632d14b 1266 case PROCESSOR_L1OM:
7a9068fe 1267 case PROCESSOR_K1OM:
22109423 1268 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1269 patt = alt_patt;
ccc9c027
L		 1270 else
1271 patt = f32_patt;
1272 break;
1273 case PROCESSOR_GENERIC64:
80b8656c 1274 patt = alt_patt;
ccc9c027 1275 break;
4eed87de 1276 }
ccc9c027
L		 1277 }
1278
76bc74dc
L		 1279 if (patt == f32_patt)
1280 {
1281 /* If the padding is less than 15 bytes, we use the normal
1282 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1283 its offset. */
1284 int limit;
76ba9986 1285
711eedef
L		 1286 /* For 64bit, the limit is 3 bytes. */
1287 if (flag_code == CODE_64BIT
1288 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1289 limit = 3;
1290 else
1291 limit = 15;
1292 if (count < limit)
76bc74dc
L		 1293 memcpy (fragP->fr_literal + fragP->fr_fix,
1294 patt[count - 1], count);
1295 else
1296 {
1297 memcpy (fragP->fr_literal + fragP->fr_fix,
1298 jump_31, count);
1299 /* Adjust jump offset. */
1300 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1301 }
1302 }
1303 else
1304 {
80b8656c
L		 1305 /* Maximum length of an instruction is 10 byte. If the
1306 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1307 we have to break it into smaller pieces. */
1308 int padding = count;
80b8656c 1309 while (padding > 10)
76bc74dc 1310 {
80b8656c 1311 padding -= 10;
76bc74dc 1312 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1313 patt [9], 10);
76bc74dc
L		 1314 }
1315
1316 if (padding)
1317 memcpy (fragP->fr_literal + fragP->fr_fix,
1318 patt [padding - 1], padding);
1319 }
ccc9c027 1320 }
33fef721 1321 fragP->fr_var = count;
252b5132
RH		 1322}
1323
c6fb90c8 1324static INLINE int
0dfbf9d7 1325operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1326{
0dfbf9d7 1327 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1328 {
1329 case 3:
0dfbf9d7 1330 if (x->array[2])
c6fb90c8
L		 1331 return 0;
1332 case 2:
0dfbf9d7 1333 if (x->array[1])
c6fb90c8
L		 1334 return 0;
1335 case 1:
0dfbf9d7 1336 return !x->array[0];
c6fb90c8
L		 1337 default:
1338 abort ();
1339 }
40fb9820
L		 1340}
1341
c6fb90c8 1342static INLINE void
0dfbf9d7 1343operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1344{
0dfbf9d7 1345 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1346 {
1347 case 3:
0dfbf9d7 1348 x->array[2] = v;
c6fb90c8 1349 case 2:
0dfbf9d7 1350 x->array[1] = v;
c6fb90c8 1351 case 1:
0dfbf9d7 1352 x->array[0] = v;
c6fb90c8
L		 1353 break;
1354 default:
1355 abort ();
1356 }
1357}
40fb9820 1358
c6fb90c8 1359static INLINE int
0dfbf9d7
L		 1360operand_type_equal (const union i386_operand_type *x,
1361 const union i386_operand_type *y)
c6fb90c8 1362{
0dfbf9d7 1363 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1364 {
1365 case 3:
0dfbf9d7 1366 if (x->array[2] != y->array[2])
c6fb90c8
L		 1367 return 0;
1368 case 2:
0dfbf9d7 1369 if (x->array[1] != y->array[1])
c6fb90c8
L		 1370 return 0;
1371 case 1:
0dfbf9d7 1372 return x->array[0] == y->array[0];
c6fb90c8
L		 1373 break;
1374 default:
1375 abort ();
1376 }
1377}
40fb9820 1378
0dfbf9d7
L		 1379static INLINE int
1380cpu_flags_all_zero (const union i386_cpu_flags *x)
1381{
1382 switch (ARRAY_SIZE(x->array))
1383 {
1384 case 3:
1385 if (x->array[2])
1386 return 0;
1387 case 2:
1388 if (x->array[1])
1389 return 0;
1390 case 1:
1391 return !x->array[0];
1392 default:
1393 abort ();
1394 }
1395}
1396
0dfbf9d7
L		 1397static INLINE int
1398cpu_flags_equal (const union i386_cpu_flags *x,
1399 const union i386_cpu_flags *y)
1400{
1401 switch (ARRAY_SIZE(x->array))
1402 {
1403 case 3:
1404 if (x->array[2] != y->array[2])
1405 return 0;
1406 case 2:
1407 if (x->array[1] != y->array[1])
1408 return 0;
1409 case 1:
1410 return x->array[0] == y->array[0];
1411 break;
1412 default:
1413 abort ();
1414 }
1415}
c6fb90c8
L		 1416
1417static INLINE int
1418cpu_flags_check_cpu64 (i386_cpu_flags f)
1419{
1420 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1421 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1422}
1423
c6fb90c8
L		 1424static INLINE i386_cpu_flags
1425cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1426{
c6fb90c8
L		 1427 switch (ARRAY_SIZE (x.array))
1428 {
1429 case 3:
1430 x.array [2] &= y.array [2];
1431 case 2:
1432 x.array [1] &= y.array [1];
1433 case 1:
1434 x.array [0] &= y.array [0];
1435 break;
1436 default:
1437 abort ();
1438 }
1439 return x;
1440}
40fb9820 1441
c6fb90c8
L		 1442static INLINE i386_cpu_flags
1443cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1444{
c6fb90c8 1445 switch (ARRAY_SIZE (x.array))
40fb9820 1446 {
c6fb90c8
L		 1447 case 3:
1448 x.array [2] |= y.array [2];
1449 case 2:
1450 x.array [1] |= y.array [1];
1451 case 1:
1452 x.array [0] |= y.array [0];
40fb9820
L		 1453 break;
1454 default:
1455 abort ();
1456 }
40fb9820
L		 1457 return x;
1458}
1459
309d3373
JB		 1460static INLINE i386_cpu_flags
1461cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1462{
1463 switch (ARRAY_SIZE (x.array))
1464 {
1465 case 3:
1466 x.array [2] &= ~y.array [2];
1467 case 2:
1468 x.array [1] &= ~y.array [1];
1469 case 1:
1470 x.array [0] &= ~y.array [0];
1471 break;
1472 default:
1473 abort ();
1474 }
1475 return x;
1476}
1477
81486035
L		 1478static int
1479valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1480{
1481 if (cpu_arch_isa == PROCESSOR_IAMCU)
1482 {
1483 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1484 i386_cpu_flags compat_flags;
1485 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1486 return cpu_flags_all_zero (&compat_flags);
1487 }
1488 else
1489 return 1;
1490}
1491
c0f3af97
L		 1492#define CPU_FLAGS_ARCH_MATCH 0x1
1493#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1494#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1495#define CPU_FLAGS_PCLMUL_MATCH 0x8
1496#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1497
a5ff0eb2 1498#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1499 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1500 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1501#define CPU_FLAGS_PERFECT_MATCH \
1502 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1503
1504/* Return CPU flags match bits. */
3629bb00 1505
40fb9820 1506static int
d3ce72d0 1507cpu_flags_match (const insn_template *t)
40fb9820 1508{
c0f3af97
L		 1509 i386_cpu_flags x = t->cpu_flags;
1510 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1511
1512 x.bitfield.cpu64 = 0;
1513 x.bitfield.cpuno64 = 0;
1514
0dfbf9d7 1515 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1516 {
1517 /* This instruction is available on all archs. */
1518 match |= CPU_FLAGS_32BIT_MATCH;
1519 }
3629bb00
L		 1520 else
1521 {
c0f3af97 1522 /* This instruction is available only on some archs. */
3629bb00
L		 1523 i386_cpu_flags cpu = cpu_arch_flags;
1524
1525 cpu.bitfield.cpu64 = 0;
1526 cpu.bitfield.cpuno64 = 0;
1527 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1528 if (!cpu_flags_all_zero (&cpu))
1529 {
a5ff0eb2
L		 1530 if (x.bitfield.cpuavx)
1531 {
ce2f5b3c 1532 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1533 if (cpu.bitfield.cpuavx)
1534 {
1535 /* Check SSE2AVX. */
1536 if (!t->opcode_modifier.sse2avx|| sse2avx)
1537 {
1538 match |= (CPU_FLAGS_ARCH_MATCH
1539 | CPU_FLAGS_AVX_MATCH);
1540 /* Check AES. */
1541 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1542 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1543 /* Check PCLMUL. */
1544 if (!x.bitfield.cpupclmul
1545 || cpu.bitfield.cpupclmul)
1546 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1547 }
1548 }
1549 else
1550 match |= CPU_FLAGS_ARCH_MATCH;
1551 }
1552 else
c0f3af97
L		 1553 match |= CPU_FLAGS_32BIT_MATCH;
1554 }
3629bb00 1555 }
c0f3af97 1556 return match;
40fb9820
L		 1557}
1558
c6fb90c8
L		 1559static INLINE i386_operand_type
1560operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1561{
c6fb90c8
L		 1562 switch (ARRAY_SIZE (x.array))
1563 {
1564 case 3:
1565 x.array [2] &= y.array [2];
1566 case 2:
1567 x.array [1] &= y.array [1];
1568 case 1:
1569 x.array [0] &= y.array [0];
1570 break;
1571 default:
1572 abort ();
1573 }
1574 return x;
40fb9820
L		 1575}
1576
c6fb90c8
L		 1577static INLINE i386_operand_type
1578operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1579{
c6fb90c8 1580 switch (ARRAY_SIZE (x.array))
40fb9820 1581 {
c6fb90c8
L		 1582 case 3:
1583 x.array [2] |= y.array [2];
1584 case 2:
1585 x.array [1] |= y.array [1];
1586 case 1:
1587 x.array [0] |= y.array [0];
40fb9820
L		 1588 break;
1589 default:
1590 abort ();
1591 }
c6fb90c8
L		 1592 return x;
1593}
40fb9820 1594
c6fb90c8
L		 1595static INLINE i386_operand_type
1596operand_type_xor (i386_operand_type x, i386_operand_type y)
1597{
1598 switch (ARRAY_SIZE (x.array))
1599 {
1600 case 3:
1601 x.array [2] ^= y.array [2];
1602 case 2:
1603 x.array [1] ^= y.array [1];
1604 case 1:
1605 x.array [0] ^= y.array [0];
1606 break;
1607 default:
1608 abort ();
1609 }
40fb9820
L		 1610 return x;
1611}
1612
1613static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1614static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1615static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1616static const i386_operand_type inoutportreg
1617 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1618static const i386_operand_type reg16_inoutportreg
1619 = OPERAND_TYPE_REG16_INOUTPORTREG;
1620static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1621static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1622static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1623static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1624static const i386_operand_type anydisp
1625 = OPERAND_TYPE_ANYDISP;
40fb9820 1626static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1627static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1628static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1629static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1630static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1631static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1632static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1633static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1634static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1635static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1636static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1637static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1638static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1639static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1640
1641enum operand_type
1642{
1643 reg,
40fb9820
L		 1644 imm,
1645 disp,
1646 anymem
1647};
1648
c6fb90c8 1649static INLINE int
40fb9820
L		 1650operand_type_check (i386_operand_type t, enum operand_type c)
1651{
1652 switch (c)
1653 {
1654 case reg:
1655 return (t.bitfield.reg8
1656 || t.bitfield.reg16
1657 || t.bitfield.reg32
1658 || t.bitfield.reg64);
1659
40fb9820
L		 1660 case imm:
1661 return (t.bitfield.imm8
1662 || t.bitfield.imm8s
1663 || t.bitfield.imm16
1664 || t.bitfield.imm32
1665 || t.bitfield.imm32s
1666 || t.bitfield.imm64);
1667
1668 case disp:
1669 return (t.bitfield.disp8
1670 || t.bitfield.disp16
1671 || t.bitfield.disp32
1672 || t.bitfield.disp32s
1673 || t.bitfield.disp64);
1674
1675 case anymem:
1676 return (t.bitfield.disp8
1677 || t.bitfield.disp16
1678 || t.bitfield.disp32
1679 || t.bitfield.disp32s
1680 || t.bitfield.disp64
1681 || t.bitfield.baseindex);
1682
1683 default:
1684 abort ();
1685 }
2cfe26b6
AM		 1686
1687 return 0;
40fb9820
L		 1688}
1689
5c07affc
L		 1690/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1691 operand J for instruction template T. */
1692
1693static INLINE int
d3ce72d0 1694match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1695{
1696 return !((i.types[j].bitfield.byte
1697 && !t->operand_types[j].bitfield.byte)
1698 || (i.types[j].bitfield.word
1699 && !t->operand_types[j].bitfield.word)
1700 || (i.types[j].bitfield.dword
1701 && !t->operand_types[j].bitfield.dword)
1702 || (i.types[j].bitfield.qword
1703 && !t->operand_types[j].bitfield.qword));
1704}
1705
1706/* Return 1 if there is no conflict in any size on operand J for
1707 instruction template T. */
1708
1709static INLINE int
d3ce72d0 1710match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1711{
1712 return (match_reg_size (t, j)
1713 && !((i.types[j].bitfield.unspecified
af508cb9 1714 && !i.broadcast
5c07affc
L		 1715 && !t->operand_types[j].bitfield.unspecified)
1716 || (i.types[j].bitfield.fword
1717 && !t->operand_types[j].bitfield.fword)
1718 || (i.types[j].bitfield.tbyte
1719 && !t->operand_types[j].bitfield.tbyte)
1720 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1721 && !t->operand_types[j].bitfield.xmmword)
1722 || (i.types[j].bitfield.ymmword
43234a1e
L		 1723 && !t->operand_types[j].bitfield.ymmword)
1724 || (i.types[j].bitfield.zmmword
1725 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1726}
1727
1728/* Return 1 if there is no size conflict on any operands for
1729 instruction template T. */
1730
1731static INLINE int
d3ce72d0 1732operand_size_match (const insn_template *t)
5c07affc
L		 1733{
1734 unsigned int j;
1735 int match = 1;
1736
1737 /* Don't check jump instructions. */
1738 if (t->opcode_modifier.jump
1739 || t->opcode_modifier.jumpbyte
1740 || t->opcode_modifier.jumpdword
1741 || t->opcode_modifier.jumpintersegment)
1742 return match;
1743
1744 /* Check memory and accumulator operand size. */
1745 for (j = 0; j < i.operands; j++)
1746 {
1747 if (t->operand_types[j].bitfield.anysize)
1748 continue;
1749
1750 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1751 {
1752 match = 0;
1753 break;
1754 }
1755
1756 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1757 {
1758 match = 0;
1759 break;
1760 }
1761 }
1762
891edac4 1763 if (match)
5c07affc 1764 return match;
891edac4
L		 1765 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1766 {
1767mismatch:
86e026a4 1768 i.error = operand_size_mismatch;
891edac4
L		 1769 return 0;
1770 }
5c07affc
L		 1771
1772 /* Check reverse. */
9c2799c2 1773 gas_assert (i.operands == 2);
5c07affc
L		 1774
1775 match = 1;
1776 for (j = 0; j < 2; j++)
1777 {
1778 if (t->operand_types[j].bitfield.acc
1779 && !match_reg_size (t, j ? 0 : 1))
891edac4 1780 goto mismatch;
5c07affc
L		 1781
1782 if (i.types[j].bitfield.mem
1783 && !match_mem_size (t, j ? 0 : 1))
891edac4 1784 goto mismatch;
5c07affc
L		 1785 }
1786
1787 return match;
1788}
1789
c6fb90c8 1790static INLINE int
40fb9820
L		 1791operand_type_match (i386_operand_type overlap,
1792 i386_operand_type given)
1793{
1794 i386_operand_type temp = overlap;
1795
1796 temp.bitfield.jumpabsolute = 0;
7d5e4556 1797 temp.bitfield.unspecified = 0;
5c07affc
L		 1798 temp.bitfield.byte = 0;
1799 temp.bitfield.word = 0;
1800 temp.bitfield.dword = 0;
1801 temp.bitfield.fword = 0;
1802 temp.bitfield.qword = 0;
1803 temp.bitfield.tbyte = 0;
1804 temp.bitfield.xmmword = 0;
c0f3af97 1805 temp.bitfield.ymmword = 0;
43234a1e 1806 temp.bitfield.zmmword = 0;
0dfbf9d7 1807 if (operand_type_all_zero (&temp))
891edac4 1808 goto mismatch;
40fb9820 1809
891edac4
L		 1810 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1811 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1812 return 1;
1813
1814mismatch:
a65babc9 1815 i.error = operand_type_mismatch;
891edac4 1816 return 0;
40fb9820
L		 1817}
1818
7d5e4556 1819/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1820 unless the expected operand type register overlap is null.
1821 Note that Acc in a template matches every size of reg. */
1822
c6fb90c8 1823static INLINE int
40fb9820
L		 1824operand_type_register_match (i386_operand_type m0,
1825 i386_operand_type g0,
1826 i386_operand_type t0,
1827 i386_operand_type m1,
1828 i386_operand_type g1,
1829 i386_operand_type t1)
1830{
1831 if (!operand_type_check (g0, reg))
1832 return 1;
1833
1834 if (!operand_type_check (g1, reg))
1835 return 1;
1836
1837 if (g0.bitfield.reg8 == g1.bitfield.reg8
1838 && g0.bitfield.reg16 == g1.bitfield.reg16
1839 && g0.bitfield.reg32 == g1.bitfield.reg32
1840 && g0.bitfield.reg64 == g1.bitfield.reg64)
1841 return 1;
1842
1843 if (m0.bitfield.acc)
1844 {
1845 t0.bitfield.reg8 = 1;
1846 t0.bitfield.reg16 = 1;
1847 t0.bitfield.reg32 = 1;
1848 t0.bitfield.reg64 = 1;
1849 }
1850
1851 if (m1.bitfield.acc)
1852 {
1853 t1.bitfield.reg8 = 1;
1854 t1.bitfield.reg16 = 1;
1855 t1.bitfield.reg32 = 1;
1856 t1.bitfield.reg64 = 1;
1857 }
1858
891edac4
L		 1859 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1860 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1861 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1862 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1863 return 1;
1864
a65babc9 1865 i.error = register_type_mismatch;
891edac4
L		 1866
1867 return 0;
40fb9820
L		 1868}
1869
4c692bc7
JB		 1870static INLINE unsigned int
1871register_number (const reg_entry *r)
1872{
1873 unsigned int nr = r->reg_num;
1874
1875 if (r->reg_flags & RegRex)
1876 nr += 8;
1877
1878 return nr;
1879}
1880
252b5132 1881static INLINE unsigned int
40fb9820 1882mode_from_disp_size (i386_operand_type t)
252b5132 1883{
43234a1e 1884 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1885 return 1;
1886 else if (t.bitfield.disp16
1887 || t.bitfield.disp32
1888 || t.bitfield.disp32s)
1889 return 2;
1890 else
1891 return 0;
252b5132
RH		 1892}
1893
1894static INLINE int
65879393 1895fits_in_signed_byte (addressT num)
252b5132 1896{
65879393 1897 return num + 0x80 <= 0xff;
47926f60 1898}
252b5132
RH		 1899
1900static INLINE int
65879393 1901fits_in_unsigned_byte (addressT num)
252b5132 1902{
65879393 1903 return num <= 0xff;
47926f60 1904}
252b5132
RH		 1905
1906static INLINE int
65879393 1907fits_in_unsigned_word (addressT num)
252b5132 1908{
65879393 1909 return num <= 0xffff;
47926f60 1910}
252b5132
RH		 1911
1912static INLINE int
65879393 1913fits_in_signed_word (addressT num)
252b5132 1914{
65879393 1915 return num + 0x8000 <= 0xffff;
47926f60 1916}
2a962e6d 1917
3e73aa7c 1918static INLINE int
65879393 1919fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1920{
1921#ifndef BFD64
1922 return 1;
1923#else
65879393 1924 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1925#endif
1926} /* fits_in_signed_long() */
2a962e6d 1927
3e73aa7c 1928static INLINE int
65879393 1929fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1930{
1931#ifndef BFD64
1932 return 1;
1933#else
65879393 1934 return num <= 0xffffffff;
3e73aa7c
JH		 1935#endif
1936} /* fits_in_unsigned_long() */
252b5132 1937
43234a1e
L		 1938static INLINE int
1939fits_in_vec_disp8 (offsetT num)
1940{
1941 int shift = i.memshift;
1942 unsigned int mask;
1943
1944 if (shift == -1)
1945 abort ();
1946
1947 mask = (1 << shift) - 1;
1948
1949 /* Return 0 if NUM isn't properly aligned. */
1950 if ((num & mask))
1951 return 0;
1952
1953 /* Check if NUM will fit in 8bit after shift. */
1954 return fits_in_signed_byte (num >> shift);
1955}
1956
a683cc34
SP		 1957static INLINE int
1958fits_in_imm4 (offsetT num)
1959{
1960 return (num & 0xf) == num;
1961}
1962
40fb9820 1963static i386_operand_type
e3bb37b5 1964smallest_imm_type (offsetT num)
252b5132 1965{
40fb9820 1966 i386_operand_type t;
7ab9ffdd 1967
0dfbf9d7 1968 operand_type_set (&t, 0);
40fb9820
L		 1969 t.bitfield.imm64 = 1;
1970
1971 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1972 {
1973 /* This code is disabled on the 486 because all the Imm1 forms
1974 in the opcode table are slower on the i486. They're the
1975 versions with the implicitly specified single-position
1976 displacement, which has another syntax if you really want to
1977 use that form. */
40fb9820
L		 1978 t.bitfield.imm1 = 1;
1979 t.bitfield.imm8 = 1;
1980 t.bitfield.imm8s = 1;
1981 t.bitfield.imm16 = 1;
1982 t.bitfield.imm32 = 1;
1983 t.bitfield.imm32s = 1;
1984 }
1985 else if (fits_in_signed_byte (num))
1986 {
1987 t.bitfield.imm8 = 1;
1988 t.bitfield.imm8s = 1;
1989 t.bitfield.imm16 = 1;
1990 t.bitfield.imm32 = 1;
1991 t.bitfield.imm32s = 1;
1992 }
1993 else if (fits_in_unsigned_byte (num))
1994 {
1995 t.bitfield.imm8 = 1;
1996 t.bitfield.imm16 = 1;
1997 t.bitfield.imm32 = 1;
1998 t.bitfield.imm32s = 1;
1999 }
2000 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2001 {
2002 t.bitfield.imm16 = 1;
2003 t.bitfield.imm32 = 1;
2004 t.bitfield.imm32s = 1;
2005 }
2006 else if (fits_in_signed_long (num))
2007 {
2008 t.bitfield.imm32 = 1;
2009 t.bitfield.imm32s = 1;
2010 }
2011 else if (fits_in_unsigned_long (num))
2012 t.bitfield.imm32 = 1;
2013
2014 return t;
47926f60 2015}
252b5132 2016
847f7ad4 2017static offsetT
e3bb37b5 2018offset_in_range (offsetT val, int size)
847f7ad4 2019{
508866be 2020 addressT mask;
ba2adb93 2021
847f7ad4
AM		 2022 switch (size)
2023 {
508866be
L		 2024 case 1: mask = ((addressT) 1 << 8) - 1; break;
2025 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2026 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2027#ifdef BFD64
2028 case 8: mask = ((addressT) 2 << 63) - 1; break;
2029#endif
47926f60 2030 default: abort ();
847f7ad4
AM		 2031 }
2032
9de868bf
L		 2033#ifdef BFD64
2034 /* If BFD64, sign extend val for 32bit address mode. */
2035 if (flag_code != CODE_64BIT
2036 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2037 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2038 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2039#endif
ba2adb93 2040
47926f60 2041 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2042 {
2043 char buf1[40], buf2[40];
2044
2045 sprint_value (buf1, val);
2046 sprint_value (buf2, val & mask);
2047 as_warn (_("%s shortened to %s"), buf1, buf2);
2048 }
2049 return val & mask;
2050}
2051
c32fa91d
L		 2052enum PREFIX_GROUP
2053{
2054 PREFIX_EXIST = 0,
2055 PREFIX_LOCK,
2056 PREFIX_REP,
2057 PREFIX_OTHER
2058};
2059
2060/* Returns
2061 a. PREFIX_EXIST if attempting to add a prefix where one from the
2062 same class already exists.
2063 b. PREFIX_LOCK if lock prefix is added.
2064 c. PREFIX_REP if rep/repne prefix is added.
2065 d. PREFIX_OTHER if other prefix is added.
2066 */
2067
2068static enum PREFIX_GROUP
e3bb37b5 2069add_prefix (unsigned int prefix)
252b5132 2070{
c32fa91d 2071 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2072 unsigned int q;
252b5132 2073
29b0f896
AM		 2074 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2075 && flag_code == CODE_64BIT)
b1905489 2076 {
161a04f6
L		 2077 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2078 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2079 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2080 ret = PREFIX_EXIST;
b1905489
JB		 2081 q = REX_PREFIX;
2082 }
3e73aa7c 2083 else
b1905489
JB		 2084 {
2085 switch (prefix)
2086 {
2087 default:
2088 abort ();
2089
2090 case CS_PREFIX_OPCODE:
2091 case DS_PREFIX_OPCODE:
2092 case ES_PREFIX_OPCODE:
2093 case FS_PREFIX_OPCODE:
2094 case GS_PREFIX_OPCODE:
2095 case SS_PREFIX_OPCODE:
2096 q = SEG_PREFIX;
2097 break;
2098
2099 case REPNE_PREFIX_OPCODE:
2100 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2101 q = REP_PREFIX;
2102 ret = PREFIX_REP;
2103 break;
2104
b1905489 2105 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2106 q = LOCK_PREFIX;
2107 ret = PREFIX_LOCK;
b1905489
JB		 2108 break;
2109
2110 case FWAIT_OPCODE:
2111 q = WAIT_PREFIX;
2112 break;
2113
2114 case ADDR_PREFIX_OPCODE:
2115 q = ADDR_PREFIX;
2116 break;
2117
2118 case DATA_PREFIX_OPCODE:
2119 q = DATA_PREFIX;
2120 break;
2121 }
2122 if (i.prefix[q] != 0)
c32fa91d 2123 ret = PREFIX_EXIST;
b1905489 2124 }
252b5132 2125
b1905489 2126 if (ret)
252b5132 2127 {
b1905489
JB		 2128 if (!i.prefix[q])
2129 ++i.prefixes;
2130 i.prefix[q] |= prefix;
252b5132 2131 }
b1905489
JB		 2132 else
2133 as_bad (_("same type of prefix used twice"));
252b5132 2134
252b5132
RH		 2135 return ret;
2136}
2137
2138static void
78f12dd3 2139update_code_flag (int value, int check)
eecb386c 2140{
78f12dd3
L		 2141 PRINTF_LIKE ((*as_error));
2142
1e9cc1c2 2143 flag_code = (enum flag_code) value;
40fb9820
L		 2144 if (flag_code == CODE_64BIT)
2145 {
2146 cpu_arch_flags.bitfield.cpu64 = 1;
2147 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2148 }
2149 else
2150 {
2151 cpu_arch_flags.bitfield.cpu64 = 0;
2152 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2153 }
2154 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2155 {
78f12dd3
L		 2156 if (check)
2157 as_error = as_fatal;
2158 else
2159 as_error = as_bad;
2160 (*as_error) (_("64bit mode not supported on `%s'."),
2161 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2162 }
40fb9820 2163 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2164 {
78f12dd3
L		 2165 if (check)
2166 as_error = as_fatal;
2167 else
2168 as_error = as_bad;
2169 (*as_error) (_("32bit mode not supported on `%s'."),
2170 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2171 }
eecb386c
AM		 2172 stackop_size = '\0';
2173}
2174
78f12dd3
L		 2175static void
2176set_code_flag (int value)
2177{
2178 update_code_flag (value, 0);
2179}
2180
eecb386c 2181static void
e3bb37b5 2182set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2183{
1e9cc1c2 2184 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2185 if (flag_code != CODE_16BIT)
2186 abort ();
2187 cpu_arch_flags.bitfield.cpu64 = 0;
2188 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2189 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2190}
2191
2192static void
e3bb37b5 2193set_intel_syntax (int syntax_flag)
252b5132
RH		 2194{
2195 /* Find out if register prefixing is specified. */
2196 int ask_naked_reg = 0;
2197
2198 SKIP_WHITESPACE ();
29b0f896 2199 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2200 {
d02603dc
NC		 2201 char *string;
2202 int e = get_symbol_name (&string);
252b5132 2203
47926f60 2204 if (strcmp (string, "prefix") == 0)
252b5132 2205 ask_naked_reg = 1;
47926f60 2206 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2207 ask_naked_reg = -1;
2208 else
d0b47220 2209 as_bad (_("bad argument to syntax directive."));
d02603dc 2210 (void) restore_line_pointer (e);
252b5132
RH		 2211 }
2212 demand_empty_rest_of_line ();
c3332e24 2213
252b5132
RH		 2214 intel_syntax = syntax_flag;
2215
2216 if (ask_naked_reg == 0)
f86103b7
AM		 2217 allow_naked_reg = (intel_syntax
2218 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2219 else
2220 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2221
ee86248c 2222 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2223
e4a3b5a4 2224 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2225 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2226 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2227}
2228
1efbbeb4
L		 2229static void
2230set_intel_mnemonic (int mnemonic_flag)
2231{
e1d4d893 2232 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2233}
2234
db51cc60
L		 2235static void
2236set_allow_index_reg (int flag)
2237{
2238 allow_index_reg = flag;
2239}
2240
cb19c032 2241static void
7bab8ab5 2242set_check (int what)
cb19c032 2243{
7bab8ab5
JB		 2244 enum check_kind *kind;
2245 const char *str;
2246
2247 if (what)
2248 {
2249 kind = &operand_check;
2250 str = "operand";
2251 }
2252 else
2253 {
2254 kind = &sse_check;
2255 str = "sse";
2256 }
2257
cb19c032
L		 2258 SKIP_WHITESPACE ();
2259
2260 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2261 {
d02603dc
NC		 2262 char *string;
2263 int e = get_symbol_name (&string);
cb19c032
L		 2264
2265 if (strcmp (string, "none") == 0)
7bab8ab5 2266 *kind = check_none;
cb19c032 2267 else if (strcmp (string, "warning") == 0)
7bab8ab5 2268 *kind = check_warning;
cb19c032 2269 else if (strcmp (string, "error") == 0)
7bab8ab5 2270 *kind = check_error;
cb19c032 2271 else
7bab8ab5 2272 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2273 (void) restore_line_pointer (e);
cb19c032
L		 2274 }
2275 else
7bab8ab5 2276 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2277
2278 demand_empty_rest_of_line ();
2279}
2280
8a9036a4
L		 2281static void
2282check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2283 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2284{
2285#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2286 static const char *arch;
2287
2288 /* Intel LIOM is only supported on ELF. */
2289 if (!IS_ELF)
2290 return;
2291
2292 if (!arch)
2293 {
2294 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2295 use default_arch. */
2296 arch = cpu_arch_name;
2297 if (!arch)
2298 arch = default_arch;
2299 }
2300
81486035
L		 2301 /* If we are targeting Intel MCU, we must enable it. */
2302 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2303 || new_flag.bitfield.cpuiamcu)
2304 return;
2305
3632d14b 2306 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2307 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2308 || new_flag.bitfield.cpul1om)
8a9036a4 2309 return;
76ba9986 2310
7a9068fe
L		 2311 /* If we are targeting Intel K1OM, we must enable it. */
2312 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2313 || new_flag.bitfield.cpuk1om)
2314 return;
2315
8a9036a4
L		 2316 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2317#endif
2318}
2319
e413e4e9 2320static void
e3bb37b5 2321set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2322{
47926f60 2323 SKIP_WHITESPACE ();
e413e4e9 2324
29b0f896 2325 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2326 {
d02603dc
NC		 2327 char *string;
2328 int e = get_symbol_name (&string);
91d6fa6a 2329 unsigned int j;
40fb9820 2330 i386_cpu_flags flags;
e413e4e9 2331
91d6fa6a 2332 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2333 {
91d6fa6a 2334 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2335 {
91d6fa6a 2336 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2337
5c6af06e
JB		 2338 if (*string != '.')
2339 {
91d6fa6a 2340 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2341 cpu_sub_arch_name = NULL;
91d6fa6a 2342 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2343 if (flag_code == CODE_64BIT)
2344 {
2345 cpu_arch_flags.bitfield.cpu64 = 1;
2346 cpu_arch_flags.bitfield.cpuno64 = 0;
2347 }
2348 else
2349 {
2350 cpu_arch_flags.bitfield.cpu64 = 0;
2351 cpu_arch_flags.bitfield.cpuno64 = 1;
2352 }
91d6fa6a
NC		 2353 cpu_arch_isa = cpu_arch[j].type;
2354 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2355 if (!cpu_arch_tune_set)
2356 {
2357 cpu_arch_tune = cpu_arch_isa;
2358 cpu_arch_tune_flags = cpu_arch_isa_flags;
2359 }
5c6af06e
JB		 2360 break;
2361 }
40fb9820 2362
22109423 2363 if (!cpu_arch[j].negated)
309d3373 2364 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2365 cpu_arch[j].flags);
309d3373
JB		 2366 else
2367 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2368 cpu_arch[j].flags);
81486035
L		 2369
2370 if (!valid_iamcu_cpu_flags (&flags))
2371 as_fatal (_("`%s' isn't valid for Intel MCU"),
2372 cpu_arch[j].name);
2373 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2374 {
6305a203
L		 2375 if (cpu_sub_arch_name)
2376 {
2377 char *name = cpu_sub_arch_name;
2378 cpu_sub_arch_name = concat (name,
91d6fa6a 2379 cpu_arch[j].name,
1bf57e9f 2380 (const char *) NULL);
6305a203
L		 2381 free (name);
2382 }
2383 else
91d6fa6a 2384 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2385 cpu_arch_flags = flags;
a586129e 2386 cpu_arch_isa_flags = flags;
5c6af06e 2387 }
d02603dc 2388 (void) restore_line_pointer (e);
5c6af06e
JB		 2389 demand_empty_rest_of_line ();
2390 return;
e413e4e9
AM		 2391 }
2392 }
91d6fa6a 2393 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2394 as_bad (_("no such architecture: `%s'"), string);
2395
2396 *input_line_pointer = e;
2397 }
2398 else
2399 as_bad (_("missing cpu architecture"));
2400
fddf5b5b
AM		 2401 no_cond_jump_promotion = 0;
2402 if (*input_line_pointer == ','
29b0f896 2403 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2404 {
d02603dc
NC		 2405 char *string;
2406 char e;
2407
2408 ++input_line_pointer;
2409 e = get_symbol_name (&string);
fddf5b5b
AM		 2410
2411 if (strcmp (string, "nojumps") == 0)
2412 no_cond_jump_promotion = 1;
2413 else if (strcmp (string, "jumps") == 0)
2414 ;
2415 else
2416 as_bad (_("no such architecture modifier: `%s'"), string);
2417
d02603dc 2418 (void) restore_line_pointer (e);
fddf5b5b
AM		 2419 }
2420
e413e4e9
AM		 2421 demand_empty_rest_of_line ();
2422}
2423
8a9036a4
L		 2424enum bfd_architecture
2425i386_arch (void)
2426{
3632d14b 2427 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2428 {
2429 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2430 || flag_code != CODE_64BIT)
2431 as_fatal (_("Intel L1OM is 64bit ELF only"));
2432 return bfd_arch_l1om;
2433 }
7a9068fe
L		 2434 else if (cpu_arch_isa == PROCESSOR_K1OM)
2435 {
2436 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2437 || flag_code != CODE_64BIT)
2438 as_fatal (_("Intel K1OM is 64bit ELF only"));
2439 return bfd_arch_k1om;
2440 }
81486035
L		 2441 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2442 {
2443 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2444 || flag_code == CODE_64BIT)
2445 as_fatal (_("Intel MCU is 32bit ELF only"));
2446 return bfd_arch_iamcu;
2447 }
8a9036a4
L		 2448 else
2449 return bfd_arch_i386;
2450}
2451
b9d79e03 2452unsigned long
7016a5d5 2453i386_mach (void)
b9d79e03 2454{
351f65ca 2455 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2456 {
3632d14b 2457 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2458 {
351f65ca
L		 2459 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2460 || default_arch[6] != '\0')
8a9036a4
L		 2461 as_fatal (_("Intel L1OM is 64bit ELF only"));
2462 return bfd_mach_l1om;
2463 }
7a9068fe
L		 2464 else if (cpu_arch_isa == PROCESSOR_K1OM)
2465 {
2466 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2467 || default_arch[6] != '\0')
2468 as_fatal (_("Intel K1OM is 64bit ELF only"));
2469 return bfd_mach_k1om;
2470 }
351f65ca 2471 else if (default_arch[6] == '\0')
8a9036a4 2472 return bfd_mach_x86_64;
351f65ca
L		 2473 else
2474 return bfd_mach_x64_32;
8a9036a4 2475 }
5197d474
L		 2476 else if (!strcmp (default_arch, "i386")
2477 || !strcmp (default_arch, "iamcu"))
81486035
L		 2478 {
2479 if (cpu_arch_isa == PROCESSOR_IAMCU)
2480 {
2481 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2482 as_fatal (_("Intel MCU is 32bit ELF only"));
2483 return bfd_mach_i386_iamcu;
2484 }
2485 else
2486 return bfd_mach_i386_i386;
2487 }
b9d79e03 2488 else
2b5d6a91 2489 as_fatal (_("unknown architecture"));
b9d79e03 2490}
b9d79e03 2491\f
252b5132 2492void
7016a5d5 2493md_begin (void)
252b5132
RH		 2494{
2495 const char *hash_err;
2496
47926f60 2497 /* Initialize op_hash hash table. */
252b5132
RH		 2498 op_hash = hash_new ();
2499
2500 {
d3ce72d0 2501 const insn_template *optab;
29b0f896 2502 templates *core_optab;
252b5132 2503
47926f60
KH		 2504 /* Setup for loop. */
2505 optab = i386_optab;
252b5132
RH		 2506 core_optab = (templates *) xmalloc (sizeof (templates));
2507 core_optab->start = optab;
2508
2509 while (1)
2510 {
2511 ++optab;
2512 if (optab->name == NULL
2513 || strcmp (optab->name, (optab - 1)->name) != 0)
2514 {
2515 /* different name --> ship out current template list;
47926f60 2516 add to hash table; & begin anew. */
252b5132
RH		 2517 core_optab->end = optab;
2518 hash_err = hash_insert (op_hash,
2519 (optab - 1)->name,
5a49b8ac 2520 (void *) core_optab);
252b5132
RH		 2521 if (hash_err)
2522 {
b37df7c4 2523 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2524 (optab - 1)->name,
2525 hash_err);
2526 }
2527 if (optab->name == NULL)
2528 break;
2529 core_optab = (templates *) xmalloc (sizeof (templates));
2530 core_optab->start = optab;
2531 }
2532 }
2533 }
2534
47926f60 2535 /* Initialize reg_hash hash table. */
252b5132
RH		 2536 reg_hash = hash_new ();
2537 {
29b0f896 2538 const reg_entry *regtab;
c3fe08fa 2539 unsigned int regtab_size = i386_regtab_size;
252b5132 2540
c3fe08fa 2541 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2542 {
5a49b8ac 2543 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2544 if (hash_err)
b37df7c4 2545 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2546 regtab->reg_name,
2547 hash_err);
252b5132
RH		 2548 }
2549 }
2550
47926f60 2551 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2552 {
29b0f896
AM		 2553 int c;
2554 char *p;
252b5132
RH		 2555
2556 for (c = 0; c < 256; c++)
2557 {
3882b010 2558 if (ISDIGIT (c))
252b5132
RH		 2559 {
2560 digit_chars[c] = c;
2561 mnemonic_chars[c] = c;
2562 register_chars[c] = c;
2563 operand_chars[c] = c;
2564 }
3882b010 2565 else if (ISLOWER (c))
252b5132
RH		 2566 {
2567 mnemonic_chars[c] = c;
2568 register_chars[c] = c;
2569 operand_chars[c] = c;
2570 }
3882b010 2571 else if (ISUPPER (c))
252b5132 2572 {
3882b010 2573 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2574 register_chars[c] = mnemonic_chars[c];
2575 operand_chars[c] = c;
2576 }
43234a1e
L		 2577 else if (c == '{' || c == '}')
2578 operand_chars[c] = c;
252b5132 2579
3882b010 2580 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2581 identifier_chars[c] = c;
2582 else if (c >= 128)
2583 {
2584 identifier_chars[c] = c;
2585 operand_chars[c] = c;
2586 }
2587 }
2588
2589#ifdef LEX_AT
2590 identifier_chars['@'] = '@';
32137342
NC		 2591#endif
2592#ifdef LEX_QM
2593 identifier_chars['?'] = '?';
2594 operand_chars['?'] = '?';
252b5132 2595#endif
252b5132 2596 digit_chars['-'] = '-';
c0f3af97 2597 mnemonic_chars['_'] = '_';
791fe849 2598 mnemonic_chars['-'] = '-';
0003779b 2599 mnemonic_chars['.'] = '.';
252b5132
RH		 2600 identifier_chars['_'] = '_';
2601 identifier_chars['.'] = '.';
2602
2603 for (p = operand_special_chars; *p != '\0'; p++)
2604 operand_chars[(unsigned char) *p] = *p;
2605 }
2606
a4447b93
RH		 2607 if (flag_code == CODE_64BIT)
2608 {
ca19b261
KT		 2609#if defined (OBJ_COFF) && defined (TE_PE)
2610 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2611 ? 32 : 16);
2612#else
a4447b93 2613 x86_dwarf2_return_column = 16;
ca19b261 2614#endif
61ff971f 2615 x86_cie_data_alignment = -8;
a4447b93
RH		 2616 }
2617 else
2618 {
2619 x86_dwarf2_return_column = 8;
2620 x86_cie_data_alignment = -4;
2621 }
252b5132
RH		 2622}
2623
2624void
e3bb37b5 2625i386_print_statistics (FILE *file)
252b5132
RH		 2626{
2627 hash_print_statistics (file, "i386 opcode", op_hash);
2628 hash_print_statistics (file, "i386 register", reg_hash);
2629}
2630\f
252b5132
RH		 2631#ifdef DEBUG386
2632
ce8a8b2f 2633/* Debugging routines for md_assemble. */
d3ce72d0 2634static void pte (insn_template *);
40fb9820 2635static void pt (i386_operand_type);
e3bb37b5
L		 2636static void pe (expressionS *);
2637static void ps (symbolS *);
252b5132
RH		 2638
2639static void
e3bb37b5 2640pi (char *line, i386_insn *x)
252b5132 2641{
09137c09 2642 unsigned int j;
252b5132
RH		 2643
2644 fprintf (stdout, "%s: template ", line);
2645 pte (&x->tm);
09f131f2
JH		 2646 fprintf (stdout, " address: base %s index %s scale %x\n",
2647 x->base_reg ? x->base_reg->reg_name : "none",
2648 x->index_reg ? x->index_reg->reg_name : "none",
2649 x->log2_scale_factor);
2650 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2651 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2652 fprintf (stdout, " sib: base %x index %x scale %x\n",
2653 x->sib.base, x->sib.index, x->sib.scale);
2654 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2655 (x->rex & REX_W) != 0,
2656 (x->rex & REX_R) != 0,
2657 (x->rex & REX_X) != 0,
2658 (x->rex & REX_B) != 0);
09137c09 2659 for (j = 0; j < x->operands; j++)
252b5132 2660 {
09137c09
SP		 2661 fprintf (stdout, " #%d: ", j + 1);
2662 pt (x->types[j]);
252b5132 2663 fprintf (stdout, "\n");
09137c09
SP		 2664 if (x->types[j].bitfield.reg8
2665 || x->types[j].bitfield.reg16
2666 || x->types[j].bitfield.reg32
2667 || x->types[j].bitfield.reg64
2668 || x->types[j].bitfield.regmmx
2669 || x->types[j].bitfield.regxmm
2670 || x->types[j].bitfield.regymm
43234a1e 2671 || x->types[j].bitfield.regzmm
09137c09
SP		 2672 || x->types[j].bitfield.sreg2
2673 || x->types[j].bitfield.sreg3
2674 || x->types[j].bitfield.control
2675 || x->types[j].bitfield.debug
2676 || x->types[j].bitfield.test)
2677 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2678 if (operand_type_check (x->types[j], imm))
2679 pe (x->op[j].imms);
2680 if (operand_type_check (x->types[j], disp))
2681 pe (x->op[j].disps);
252b5132
RH		 2682 }
2683}
2684
2685static void
d3ce72d0 2686pte (insn_template *t)
252b5132 2687{
09137c09 2688 unsigned int j;
252b5132 2689 fprintf (stdout, " %d operands ", t->operands);
47926f60 2690 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2691 if (t->extension_opcode != None)
2692 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2693 if (t->opcode_modifier.d)
252b5132 2694 fprintf (stdout, "D");
40fb9820 2695 if (t->opcode_modifier.w)
252b5132
RH		 2696 fprintf (stdout, "W");
2697 fprintf (stdout, "\n");
09137c09 2698 for (j = 0; j < t->operands; j++)
252b5132 2699 {
09137c09
SP		 2700 fprintf (stdout, " #%d type ", j + 1);
2701 pt (t->operand_types[j]);
252b5132
RH		 2702 fprintf (stdout, "\n");
2703 }
2704}
2705
2706static void
e3bb37b5 2707pe (expressionS *e)
252b5132 2708{
24eab124 2709 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2710 fprintf (stdout, " add_number %ld (%lx)\n",
2711 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2712 if (e->X_add_symbol)
2713 {
2714 fprintf (stdout, " add_symbol ");
2715 ps (e->X_add_symbol);
2716 fprintf (stdout, "\n");
2717 }
2718 if (e->X_op_symbol)
2719 {
2720 fprintf (stdout, " op_symbol ");
2721 ps (e->X_op_symbol);
2722 fprintf (stdout, "\n");
2723 }
2724}
2725
2726static void
e3bb37b5 2727ps (symbolS *s)
252b5132
RH		 2728{
2729 fprintf (stdout, "%s type %s%s",
2730 S_GET_NAME (s),
2731 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2732 segment_name (S_GET_SEGMENT (s)));
2733}
2734
7b81dfbb 2735static struct type_name
252b5132 2736 {
40fb9820
L		 2737 i386_operand_type mask;
2738 const char *name;
252b5132 2739 }
7b81dfbb 2740const type_names[] =
252b5132 2741{
40fb9820
L		 2742 { OPERAND_TYPE_REG8, "r8" },
2743 { OPERAND_TYPE_REG16, "r16" },
2744 { OPERAND_TYPE_REG32, "r32" },
2745 { OPERAND_TYPE_REG64, "r64" },
2746 { OPERAND_TYPE_IMM8, "i8" },
2747 { OPERAND_TYPE_IMM8, "i8s" },
2748 { OPERAND_TYPE_IMM16, "i16" },
2749 { OPERAND_TYPE_IMM32, "i32" },
2750 { OPERAND_TYPE_IMM32S, "i32s" },
2751 { OPERAND_TYPE_IMM64, "i64" },
2752 { OPERAND_TYPE_IMM1, "i1" },
2753 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2754 { OPERAND_TYPE_DISP8, "d8" },
2755 { OPERAND_TYPE_DISP16, "d16" },
2756 { OPERAND_TYPE_DISP32, "d32" },
2757 { OPERAND_TYPE_DISP32S, "d32s" },
2758 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2759 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2760 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2761 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2762 { OPERAND_TYPE_CONTROL, "control reg" },
2763 { OPERAND_TYPE_TEST, "test reg" },
2764 { OPERAND_TYPE_DEBUG, "debug reg" },
2765 { OPERAND_TYPE_FLOATREG, "FReg" },
2766 { OPERAND_TYPE_FLOATACC, "FAcc" },
2767 { OPERAND_TYPE_SREG2, "SReg2" },
2768 { OPERAND_TYPE_SREG3, "SReg3" },
2769 { OPERAND_TYPE_ACC, "Acc" },
2770 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2771 { OPERAND_TYPE_REGMMX, "rMMX" },
2772 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2773 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2774 { OPERAND_TYPE_REGZMM, "rZMM" },
2775 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2776 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2777};
2778
2779static void
40fb9820 2780pt (i386_operand_type t)
252b5132 2781{
40fb9820 2782 unsigned int j;
c6fb90c8 2783 i386_operand_type a;
252b5132 2784
40fb9820 2785 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2786 {
2787 a = operand_type_and (t, type_names[j].mask);
0349dc08 2788 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2789 fprintf (stdout, "%s, ", type_names[j].name);
2790 }
252b5132
RH		 2791 fflush (stdout);
2792}
2793
2794#endif /* DEBUG386 */
2795\f
252b5132 2796static bfd_reloc_code_real_type
3956db08 2797reloc (unsigned int size,
64e74474
AM		 2798 int pcrel,
2799 int sign,
2800 bfd_reloc_code_real_type other)
252b5132 2801{
47926f60 2802 if (other != NO_RELOC)
3956db08 2803 {
91d6fa6a 2804 reloc_howto_type *rel;
3956db08
JB		 2805
2806 if (size == 8)
2807 switch (other)
2808 {
64e74474
AM		 2809 case BFD_RELOC_X86_64_GOT32:
2810 return BFD_RELOC_X86_64_GOT64;
2811 break;
553d1284
L		 2812 case BFD_RELOC_X86_64_GOTPLT64:
2813 return BFD_RELOC_X86_64_GOTPLT64;
2814 break;
64e74474
AM		 2815 case BFD_RELOC_X86_64_PLTOFF64:
2816 return BFD_RELOC_X86_64_PLTOFF64;
2817 break;
2818 case BFD_RELOC_X86_64_GOTPC32:
2819 other = BFD_RELOC_X86_64_GOTPC64;
2820 break;
2821 case BFD_RELOC_X86_64_GOTPCREL:
2822 other = BFD_RELOC_X86_64_GOTPCREL64;
2823 break;
2824 case BFD_RELOC_X86_64_TPOFF32:
2825 other = BFD_RELOC_X86_64_TPOFF64;
2826 break;
2827 case BFD_RELOC_X86_64_DTPOFF32:
2828 other = BFD_RELOC_X86_64_DTPOFF64;
2829 break;
2830 default:
2831 break;
3956db08 2832 }
e05278af 2833
8ce3d284 2834#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2835 if (other == BFD_RELOC_SIZE32)
2836 {
2837 if (size == 8)
1ab668bf 2838 other = BFD_RELOC_SIZE64;
8fd4256d 2839 if (pcrel)
1ab668bf
AM		 2840 {
2841 as_bad (_("there are no pc-relative size relocations"));
2842 return NO_RELOC;
2843 }
8fd4256d 2844 }
8ce3d284 2845#endif
8fd4256d 2846
e05278af 2847 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2848 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2849 sign = -1;
2850
91d6fa6a
NC		 2851 rel = bfd_reloc_type_lookup (stdoutput, other);
2852 if (!rel)
3956db08 2853 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2854 else if (size != bfd_get_reloc_size (rel))
3956db08 2855 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2856 bfd_get_reloc_size (rel),
3956db08 2857 size);
91d6fa6a 2858 else if (pcrel && !rel->pc_relative)
3956db08 2859 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2860 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2861 && !sign)
91d6fa6a 2862 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2863 && sign > 0))
3956db08
JB		 2864 as_bad (_("relocated field and relocation type differ in signedness"));
2865 else
2866 return other;
2867 return NO_RELOC;
2868 }
252b5132
RH		 2869
2870 if (pcrel)
2871 {
3e73aa7c 2872 if (!sign)
3956db08 2873 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2874 switch (size)
2875 {
2876 case 1: return BFD_RELOC_8_PCREL;
2877 case 2: return BFD_RELOC_16_PCREL;
d258b828 2878 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2879 case 8: return BFD_RELOC_64_PCREL;
252b5132 2880 }
3956db08 2881 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2882 }
2883 else
2884 {
3956db08 2885 if (sign > 0)
e5cb08ac 2886 switch (size)
3e73aa7c
JH		 2887 {
2888 case 4: return BFD_RELOC_X86_64_32S;
2889 }
2890 else
2891 switch (size)
2892 {
2893 case 1: return BFD_RELOC_8;
2894 case 2: return BFD_RELOC_16;
2895 case 4: return BFD_RELOC_32;
2896 case 8: return BFD_RELOC_64;
2897 }
3956db08
JB		 2898 as_bad (_("cannot do %s %u byte relocation"),
2899 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2900 }
2901
0cc9e1d3 2902 return NO_RELOC;
252b5132
RH		 2903}
2904
47926f60
KH		 2905/* Here we decide which fixups can be adjusted to make them relative to
2906 the beginning of the section instead of the symbol. Basically we need
2907 to make sure that the dynamic relocations are done correctly, so in
2908 some cases we force the original symbol to be used. */
2909
252b5132 2910int
e3bb37b5 2911tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2912{
6d249963 2913#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2914 if (!IS_ELF)
31312f95
AM		 2915 return 1;
2916
a161fe53
AM		 2917 /* Don't adjust pc-relative references to merge sections in 64-bit
2918 mode. */
2919 if (use_rela_relocations
2920 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2921 && fixP->fx_pcrel)
252b5132 2922 return 0;
31312f95 2923
8d01d9a9
AJ		 2924 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2925 and changed later by validate_fix. */
2926 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2927 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2928 return 0;
2929
8fd4256d
L		 2930 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2931 for size relocations. */
2932 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2933 || fixP->fx_r_type == BFD_RELOC_SIZE64
2934 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2935 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2936 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2942 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2943 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2944 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2945 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2946 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2947 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2948 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2949 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2950 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2951 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2953 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2954 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2955 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2956 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2957 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2958 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2959 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2960 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2961 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2962 return 0;
31312f95 2963#endif
252b5132
RH		 2964 return 1;
2965}
252b5132 2966
b4cac588 2967static int
e3bb37b5 2968intel_float_operand (const char *mnemonic)
252b5132 2969{
9306ca4a
JB		 2970 /* Note that the value returned is meaningful only for opcodes with (memory)
2971 operands, hence the code here is free to improperly handle opcodes that
2972 have no operands (for better performance and smaller code). */
2973
2974 if (mnemonic[0] != 'f')
2975 return 0; /* non-math */
2976
2977 switch (mnemonic[1])
2978 {
2979 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2980 the fs segment override prefix not currently handled because no
2981 call path can make opcodes without operands get here */
2982 case 'i':
2983 return 2 /* integer op */;
2984 case 'l':
2985 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2986 return 3; /* fldcw/fldenv */
2987 break;
2988 case 'n':
2989 if (mnemonic[2] != 'o' /* fnop */)
2990 return 3; /* non-waiting control op */
2991 break;
2992 case 'r':
2993 if (mnemonic[2] == 's')
2994 return 3; /* frstor/frstpm */
2995 break;
2996 case 's':
2997 if (mnemonic[2] == 'a')
2998 return 3; /* fsave */
2999 if (mnemonic[2] == 't')
3000 {
3001 switch (mnemonic[3])
3002 {
3003 case 'c': /* fstcw */
3004 case 'd': /* fstdw */
3005 case 'e': /* fstenv */
3006 case 's': /* fsts[gw] */
3007 return 3;
3008 }
3009 }
3010 break;
3011 case 'x':
3012 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3013 return 0; /* fxsave/fxrstor are not really math ops */
3014 break;
3015 }
252b5132 3016
9306ca4a 3017 return 1;
252b5132
RH		 3018}
3019
c0f3af97
L		 3020/* Build the VEX prefix. */
3021
3022static void
d3ce72d0 3023build_vex_prefix (const insn_template *t)
c0f3af97
L		 3024{
3025 unsigned int register_specifier;
3026 unsigned int implied_prefix;
3027 unsigned int vector_length;
3028
3029 /* Check register specifier. */
3030 if (i.vex.register_specifier)
43234a1e
L		 3031 {
3032 register_specifier =
3033 ~register_number (i.vex.register_specifier) & 0xf;
3034 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3035 }
c0f3af97
L		 3036 else
3037 register_specifier = 0xf;
3038
fa99fab2
L		 3039 /* Use 2-byte VEX prefix by swappping destination and source
3040 operand. */
3041 if (!i.swap_operand
3042 && i.operands == i.reg_operands
7f399153 3043 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3044 && i.tm.opcode_modifier.s
3045 && i.rex == REX_B)
3046 {
3047 unsigned int xchg = i.operands - 1;
3048 union i386_op temp_op;
3049 i386_operand_type temp_type;
3050
3051 temp_type = i.types[xchg];
3052 i.types[xchg] = i.types[0];
3053 i.types[0] = temp_type;
3054 temp_op = i.op[xchg];
3055 i.op[xchg] = i.op[0];
3056 i.op[0] = temp_op;
3057
9c2799c2 3058 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3059
3060 i.rex = REX_R;
3061 xchg = i.rm.regmem;
3062 i.rm.regmem = i.rm.reg;
3063 i.rm.reg = xchg;
3064
3065 /* Use the next insn. */
3066 i.tm = t[1];
3067 }
3068
539f890d
L		 3069 if (i.tm.opcode_modifier.vex == VEXScalar)
3070 vector_length = avxscalar;
3071 else
3072 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3073
3074 switch ((i.tm.base_opcode >> 8) & 0xff)
3075 {
3076 case 0:
3077 implied_prefix = 0;
3078 break;
3079 case DATA_PREFIX_OPCODE:
3080 implied_prefix = 1;
3081 break;
3082 case REPE_PREFIX_OPCODE:
3083 implied_prefix = 2;
3084 break;
3085 case REPNE_PREFIX_OPCODE:
3086 implied_prefix = 3;
3087 break;
3088 default:
3089 abort ();
3090 }
3091
3092 /* Use 2-byte VEX prefix if possible. */
7f399153 3093 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3094 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3095 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3096 {
3097 /* 2-byte VEX prefix. */
3098 unsigned int r;
3099
3100 i.vex.length = 2;
3101 i.vex.bytes[0] = 0xc5;
3102
3103 /* Check the REX.R bit. */
3104 r = (i.rex & REX_R) ? 0 : 1;
3105 i.vex.bytes[1] = (r << 7
3106 | register_specifier << 3
3107 | vector_length << 2
3108 | implied_prefix);
3109 }
3110 else
3111 {
3112 /* 3-byte VEX prefix. */
3113 unsigned int m, w;
3114
f88c9eb0 3115 i.vex.length = 3;
f88c9eb0 3116
7f399153 3117 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3118 {
7f399153
L		 3119 case VEX0F:
3120 m = 0x1;
80de6e00 3121 i.vex.bytes[0] = 0xc4;
7f399153
L		 3122 break;
3123 case VEX0F38:
3124 m = 0x2;
80de6e00 3125 i.vex.bytes[0] = 0xc4;
7f399153
L		 3126 break;
3127 case VEX0F3A:
3128 m = 0x3;
80de6e00 3129 i.vex.bytes[0] = 0xc4;
7f399153
L		 3130 break;
3131 case XOP08:
5dd85c99
SP		 3132 m = 0x8;
3133 i.vex.bytes[0] = 0x8f;
7f399153
L		 3134 break;
3135 case XOP09:
f88c9eb0
SP		 3136 m = 0x9;
3137 i.vex.bytes[0] = 0x8f;
7f399153
L		 3138 break;
3139 case XOP0A:
f88c9eb0
SP		 3140 m = 0xa;
3141 i.vex.bytes[0] = 0x8f;
7f399153
L		 3142 break;
3143 default:
3144 abort ();
f88c9eb0 3145 }
c0f3af97 3146
c0f3af97
L		 3147 /* The high 3 bits of the second VEX byte are 1's compliment
3148 of RXB bits from REX. */
3149 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3150
3151 /* Check the REX.W bit. */
3152 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3153 if (i.tm.opcode_modifier.vexw == VEXW1)
3154 w = 1;
c0f3af97
L		 3155
3156 i.vex.bytes[2] = (w << 7
3157 | register_specifier << 3
3158 | vector_length << 2
3159 | implied_prefix);
3160 }
3161}
3162
43234a1e
L		 3163/* Build the EVEX prefix. */
3164
3165static void
3166build_evex_prefix (void)
3167{
3168 unsigned int register_specifier;
3169 unsigned int implied_prefix;
3170 unsigned int m, w;
3171 rex_byte vrex_used = 0;
3172
3173 /* Check register specifier. */
3174 if (i.vex.register_specifier)
3175 {
3176 gas_assert ((i.vrex & REX_X) == 0);
3177
3178 register_specifier = i.vex.register_specifier->reg_num;
3179 if ((i.vex.register_specifier->reg_flags & RegRex))
3180 register_specifier += 8;
3181 /* The upper 16 registers are encoded in the fourth byte of the
3182 EVEX prefix. */
3183 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3184 i.vex.bytes[3] = 0x8;
3185 register_specifier = ~register_specifier & 0xf;
3186 }
3187 else
3188 {
3189 register_specifier = 0xf;
3190
3191 /* Encode upper 16 vector index register in the fourth byte of
3192 the EVEX prefix. */
3193 if (!(i.vrex & REX_X))
3194 i.vex.bytes[3] = 0x8;
3195 else
3196 vrex_used |= REX_X;
3197 }
3198
3199 switch ((i.tm.base_opcode >> 8) & 0xff)
3200 {
3201 case 0:
3202 implied_prefix = 0;
3203 break;
3204 case DATA_PREFIX_OPCODE:
3205 implied_prefix = 1;
3206 break;
3207 case REPE_PREFIX_OPCODE:
3208 implied_prefix = 2;
3209 break;
3210 case REPNE_PREFIX_OPCODE:
3211 implied_prefix = 3;
3212 break;
3213 default:
3214 abort ();
3215 }
3216
3217 /* 4 byte EVEX prefix. */
3218 i.vex.length = 4;
3219 i.vex.bytes[0] = 0x62;
3220
3221 /* mmmm bits. */
3222 switch (i.tm.opcode_modifier.vexopcode)
3223 {
3224 case VEX0F:
3225 m = 1;
3226 break;
3227 case VEX0F38:
3228 m = 2;
3229 break;
3230 case VEX0F3A:
3231 m = 3;
3232 break;
3233 default:
3234 abort ();
3235 break;
3236 }
3237
3238 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3239 bits from REX. */
3240 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3241
3242 /* The fifth bit of the second EVEX byte is 1's compliment of the
3243 REX_R bit in VREX. */
3244 if (!(i.vrex & REX_R))
3245 i.vex.bytes[1] |= 0x10;
3246 else
3247 vrex_used |= REX_R;
3248
3249 if ((i.reg_operands + i.imm_operands) == i.operands)
3250 {
3251 /* When all operands are registers, the REX_X bit in REX is not
3252 used. We reuse it to encode the upper 16 registers, which is
3253 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3254 as 1's compliment. */
3255 if ((i.vrex & REX_B))
3256 {
3257 vrex_used |= REX_B;
3258 i.vex.bytes[1] &= ~0x40;
3259 }
3260 }
3261
3262 /* EVEX instructions shouldn't need the REX prefix. */
3263 i.vrex &= ~vrex_used;
3264 gas_assert (i.vrex == 0);
3265
3266 /* Check the REX.W bit. */
3267 w = (i.rex & REX_W) ? 1 : 0;
3268 if (i.tm.opcode_modifier.vexw)
3269 {
3270 if (i.tm.opcode_modifier.vexw == VEXW1)
3271 w = 1;
3272 }
3273 /* If w is not set it means we are dealing with WIG instruction. */
3274 else if (!w)
3275 {
3276 if (evexwig == evexw1)
3277 w = 1;
3278 }
3279
3280 /* Encode the U bit. */
3281 implied_prefix |= 0x4;
3282
3283 /* The third byte of the EVEX prefix. */
3284 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3285
3286 /* The fourth byte of the EVEX prefix. */
3287 /* The zeroing-masking bit. */
3288 if (i.mask && i.mask->zeroing)
3289 i.vex.bytes[3] |= 0x80;
3290
3291 /* Don't always set the broadcast bit if there is no RC. */
3292 if (!i.rounding)
3293 {
3294 /* Encode the vector length. */
3295 unsigned int vec_length;
3296
3297 switch (i.tm.opcode_modifier.evex)
3298 {
3299 case EVEXLIG: /* LL' is ignored */
3300 vec_length = evexlig << 5;
3301 break;
3302 case EVEX128:
3303 vec_length = 0 << 5;
3304 break;
3305 case EVEX256:
3306 vec_length = 1 << 5;
3307 break;
3308 case EVEX512:
3309 vec_length = 2 << 5;
3310 break;
3311 default:
3312 abort ();
3313 break;
3314 }
3315 i.vex.bytes[3] |= vec_length;
3316 /* Encode the broadcast bit. */
3317 if (i.broadcast)
3318 i.vex.bytes[3] |= 0x10;
3319 }
3320 else
3321 {
3322 if (i.rounding->type != saeonly)
3323 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3324 else
d3d3c6db 3325 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3326 }
3327
3328 if (i.mask && i.mask->mask)
3329 i.vex.bytes[3] |= i.mask->mask->reg_num;
3330}
3331
65da13b5
L		 3332static void
3333process_immext (void)
3334{
3335 expressionS *exp;
3336
4c692bc7
JB		 3337 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3338 && i.operands > 0)
65da13b5 3339 {
4c692bc7
JB		 3340 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3341 with an opcode suffix which is coded in the same place as an
3342 8-bit immediate field would be.
3343 Here we check those operands and remove them afterwards. */
65da13b5
L		 3344 unsigned int x;
3345
3346 for (x = 0; x < i.operands; x++)
4c692bc7 3347 if (register_number (i.op[x].regs) != x)
65da13b5 3348 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3349 register_prefix, i.op[x].regs->reg_name, x + 1,
3350 i.tm.name);
3351
3352 i.operands = 0;
65da13b5
L		 3353 }
3354
9916071f
AP		 3355 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3356 {
3357 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3358 suffix which is coded in the same place as an 8-bit immediate
3359 field would be.
3360 Here we check those operands and remove them afterwards. */
3361 unsigned int x;
3362
3363 if (i.operands != 3)
3364 abort();
3365
3366 for (x = 0; x < 2; x++)
3367 if (register_number (i.op[x].regs) != x)
3368 goto bad_register_operand;
3369
3370 /* Check for third operand for mwaitx/monitorx insn. */
3371 if (register_number (i.op[x].regs)
3372 != (x + (i.tm.extension_opcode == 0xfb)))
3373 {
3374bad_register_operand:
3375 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3376 register_prefix, i.op[x].regs->reg_name, x+1,
3377 i.tm.name);
3378 }
3379
3380 i.operands = 0;
3381 }
3382
c0f3af97 3383 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3384 which is coded in the same place as an 8-bit immediate field
3385 would be. Here we fake an 8-bit immediate operand from the
3386 opcode suffix stored in tm.extension_opcode.
3387
c1e679ec 3388 AVX instructions also use this encoding, for some of
c0f3af97 3389 3 argument instructions. */
65da13b5 3390
43234a1e 3391 gas_assert (i.imm_operands <= 1
7ab9ffdd 3392 && (i.operands <= 2
43234a1e
L		 3393 || ((i.tm.opcode_modifier.vex
3394 || i.tm.opcode_modifier.evex)
7ab9ffdd 3395 && i.operands <= 4)));
65da13b5
L		 3396
3397 exp = &im_expressions[i.imm_operands++];
3398 i.op[i.operands].imms = exp;
3399 i.types[i.operands] = imm8;
3400 i.operands++;
3401 exp->X_op = O_constant;
3402 exp->X_add_number = i.tm.extension_opcode;
3403 i.tm.extension_opcode = None;
3404}
3405
42164a71
L		 3406
3407static int
3408check_hle (void)
3409{
3410 switch (i.tm.opcode_modifier.hleprefixok)
3411 {
3412 default:
3413 abort ();
82c2def5 3414 case HLEPrefixNone:
165de32a
L		 3415 as_bad (_("invalid instruction `%s' after `%s'"),
3416 i.tm.name, i.hle_prefix);
42164a71 3417 return 0;
82c2def5 3418 case HLEPrefixLock:
42164a71
L		 3419 if (i.prefix[LOCK_PREFIX])
3420 return 1;
165de32a 3421 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3422 return 0;
82c2def5 3423 case HLEPrefixAny:
42164a71 3424 return 1;
82c2def5 3425 case HLEPrefixRelease:
42164a71
L		 3426 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3427 {
3428 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3429 i.tm.name);
3430 return 0;
3431 }
3432 if (i.mem_operands == 0
3433 || !operand_type_check (i.types[i.operands - 1], anymem))
3434 {
3435 as_bad (_("memory destination needed for instruction `%s'"
3436 " after `xrelease'"), i.tm.name);
3437 return 0;
3438 }
3439 return 1;
3440 }
3441}
3442
252b5132
RH		 3443/* This is the guts of the machine-dependent assembler. LINE points to a
3444 machine dependent instruction. This function is supposed to emit
3445 the frags/bytes it assembles to. */
3446
3447void
65da13b5 3448md_assemble (char *line)
252b5132 3449{
40fb9820 3450 unsigned int j;
252b5132 3451 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3452 const insn_template *t;
252b5132 3453
47926f60 3454 /* Initialize globals. */
252b5132
RH		 3455 memset (&i, '\0', sizeof (i));
3456 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3457 i.reloc[j] = NO_RELOC;
252b5132
RH		 3458 memset (disp_expressions, '\0', sizeof (disp_expressions));
3459 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3460 save_stack_p = save_stack;
252b5132
RH		 3461
3462 /* First parse an instruction mnemonic & call i386_operand for the operands.
3463 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3464 start of a (possibly prefixed) mnemonic. */
252b5132 3465
29b0f896
AM		 3466 line = parse_insn (line, mnemonic);
3467 if (line == NULL)
3468 return;
252b5132 3469
29b0f896 3470 line = parse_operands (line, mnemonic);
ee86248c 3471 this_operand = -1;
29b0f896
AM		 3472 if (line == NULL)
3473 return;
252b5132 3474
29b0f896
AM		 3475 /* Now we've parsed the mnemonic into a set of templates, and have the
3476 operands at hand. */
3477
3478 /* All intel opcodes have reversed operands except for "bound" and
3479 "enter". We also don't reverse intersegment "jmp" and "call"
3480 instructions with 2 immediate operands so that the immediate segment
050dfa73 3481 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3482 if (intel_syntax
3483 && i.operands > 1
29b0f896 3484 && (strcmp (mnemonic, "bound") != 0)
30123838 3485 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3486 && !(operand_type_check (i.types[0], imm)
3487 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3488 swap_operands ();
3489
ec56d5c0
JB		 3490 /* The order of the immediates should be reversed
3491 for 2 immediates extrq and insertq instructions */
3492 if (i.imm_operands == 2
3493 && (strcmp (mnemonic, "extrq") == 0
3494 || strcmp (mnemonic, "insertq") == 0))
3495 swap_2_operands (0, 1);
3496
29b0f896
AM		 3497 if (i.imm_operands)
3498 optimize_imm ();
3499
b300c311
L		 3500 /* Don't optimize displacement for movabs since it only takes 64bit
3501 displacement. */
3502 if (i.disp_operands
a501d77e 3503 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3504 && (flag_code != CODE_64BIT
3505 || strcmp (mnemonic, "movabs") != 0))
3506 optimize_disp ();
29b0f896
AM		 3507
3508 /* Next, we find a template that matches the given insn,
3509 making sure the overlap of the given operands types is consistent
3510 with the template operand types. */
252b5132 3511
fa99fab2 3512 if (!(t = match_template ()))
29b0f896 3513 return;
252b5132 3514
7bab8ab5 3515 if (sse_check != check_none
81f8a913 3516 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3517 && (i.tm.cpu_flags.bitfield.cpusse
3518 || i.tm.cpu_flags.bitfield.cpusse2
3519 || i.tm.cpu_flags.bitfield.cpusse3
3520 || i.tm.cpu_flags.bitfield.cpussse3
3521 || i.tm.cpu_flags.bitfield.cpusse4_1
3522 || i.tm.cpu_flags.bitfield.cpusse4_2))
3523 {
7bab8ab5 3524 (sse_check == check_warning
daf50ae7
L		 3525 ? as_warn
3526 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3527 }
3528
321fd21e
L		 3529 /* Zap movzx and movsx suffix. The suffix has been set from
3530 "word ptr" or "byte ptr" on the source operand in Intel syntax
3531 or extracted from mnemonic in AT&T syntax. But we'll use
3532 the destination register to choose the suffix for encoding. */
3533 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3534 {
321fd21e
L		 3535 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3536 there is no suffix, the default will be byte extension. */
3537 if (i.reg_operands != 2
3538 && !i.suffix
7ab9ffdd 3539 && intel_syntax)
321fd21e
L		 3540 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3541
3542 i.suffix = 0;
cd61ebfe 3543 }
24eab124 3544
40fb9820 3545 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3546 if (!add_prefix (FWAIT_OPCODE))
3547 return;
252b5132 3548
d5de92cf
L		 3549 /* Check if REP prefix is OK. */
3550 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3551 {
3552 as_bad (_("invalid instruction `%s' after `%s'"),
3553 i.tm.name, i.rep_prefix);
3554 return;
3555 }
3556
c1ba0266
L		 3557 /* Check for lock without a lockable instruction. Destination operand
3558 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3559 if (i.prefix[LOCK_PREFIX]
3560 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3561 || i.mem_operands == 0
3562 || (i.tm.base_opcode != 0x86
3563 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3564 {
3565 as_bad (_("expecting lockable instruction after `lock'"));
3566 return;
3567 }
3568
42164a71 3569 /* Check if HLE prefix is OK. */
165de32a 3570 if (i.hle_prefix && !check_hle ())
42164a71
L		 3571 return;
3572
7e8b059b
L		 3573 /* Check BND prefix. */
3574 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3575 as_bad (_("expecting valid branch instruction after `bnd'"));
3576
3577 if (i.tm.cpu_flags.bitfield.cpumpx
3578 && flag_code == CODE_64BIT
3579 && i.prefix[ADDR_PREFIX])
3580 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3581
3582 /* Insert BND prefix. */
3583 if (add_bnd_prefix
3584 && i.tm.opcode_modifier.bndprefixok
3585 && !i.prefix[BND_PREFIX])
3586 add_prefix (BND_PREFIX_OPCODE);
3587
29b0f896 3588 /* Check string instruction segment overrides. */
40fb9820 3589 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3590 {
3591 if (!check_string ())
5dd0794d 3592 return;
fc0763e6 3593 i.disp_operands = 0;
29b0f896 3594 }
5dd0794d 3595
29b0f896
AM		 3596 if (!process_suffix ())
3597 return;
e413e4e9 3598
bc0844ae
L		 3599 /* Update operand types. */
3600 for (j = 0; j < i.operands; j++)
3601 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3602
29b0f896
AM		 3603 /* Make still unresolved immediate matches conform to size of immediate
3604 given in i.suffix. */
3605 if (!finalize_imm ())
3606 return;
252b5132 3607
40fb9820 3608 if (i.types[0].bitfield.imm1)
29b0f896 3609 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3610
9afe6eb8
L		 3611 /* We only need to check those implicit registers for instructions
3612 with 3 operands or less. */
3613 if (i.operands <= 3)
3614 for (j = 0; j < i.operands; j++)
3615 if (i.types[j].bitfield.inoutportreg
3616 || i.types[j].bitfield.shiftcount
3617 || i.types[j].bitfield.acc
3618 || i.types[j].bitfield.floatacc)
3619 i.reg_operands--;
40fb9820 3620
c0f3af97
L		 3621 /* ImmExt should be processed after SSE2AVX. */
3622 if (!i.tm.opcode_modifier.sse2avx
3623 && i.tm.opcode_modifier.immext)
65da13b5 3624 process_immext ();
252b5132 3625
29b0f896
AM		 3626 /* For insns with operands there are more diddles to do to the opcode. */
3627 if (i.operands)
3628 {
3629 if (!process_operands ())
3630 return;
3631 }
40fb9820 3632 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3633 {
3634 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3635 as_warn (_("translating to `%sp'"), i.tm.name);
3636 }
252b5132 3637
9e5e5283
L		 3638 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3639 {
3640 if (flag_code == CODE_16BIT)
3641 {
3642 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3643 i.tm.name);
3644 return;
3645 }
c0f3af97 3646
9e5e5283
L		 3647 if (i.tm.opcode_modifier.vex)
3648 build_vex_prefix (t);
3649 else
3650 build_evex_prefix ();
3651 }
43234a1e 3652
5dd85c99
SP		 3653 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3654 instructions may define INT_OPCODE as well, so avoid this corner
3655 case for those instructions that use MODRM. */
3656 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3657 && !i.tm.opcode_modifier.modrm
3658 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3659 {
3660 i.tm.base_opcode = INT3_OPCODE;
3661 i.imm_operands = 0;
3662 }
252b5132 3663
40fb9820
L		 3664 if ((i.tm.opcode_modifier.jump
3665 || i.tm.opcode_modifier.jumpbyte
3666 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3667 && i.op[0].disps->X_op == O_constant)
3668 {
3669 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3670 the absolute address given by the constant. Since ix86 jumps and
3671 calls are pc relative, we need to generate a reloc. */
3672 i.op[0].disps->X_add_symbol = &abs_symbol;
3673 i.op[0].disps->X_op = O_symbol;
3674 }
252b5132 3675
40fb9820 3676 if (i.tm.opcode_modifier.rex64)
161a04f6 3677 i.rex |= REX_W;
252b5132 3678
29b0f896
AM		 3679 /* For 8 bit registers we need an empty rex prefix. Also if the
3680 instruction already has a prefix, we need to convert old
3681 registers to new ones. */
773f551c 3682
40fb9820 3683 if ((i.types[0].bitfield.reg8
29b0f896 3684 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3685 || (i.types[1].bitfield.reg8
29b0f896 3686 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3687 || ((i.types[0].bitfield.reg8
3688 || i.types[1].bitfield.reg8)
29b0f896
AM		 3689 && i.rex != 0))
3690 {
3691 int x;
726c5dcd 3692
29b0f896
AM		 3693 i.rex |= REX_OPCODE;
3694 for (x = 0; x < 2; x++)
3695 {
3696 /* Look for 8 bit operand that uses old registers. */
40fb9820 3697 if (i.types[x].bitfield.reg8
29b0f896 3698 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3699 {
29b0f896
AM		 3700 /* In case it is "hi" register, give up. */
3701 if (i.op[x].regs->reg_num > 3)
a540244d 3702 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3703 "instruction requiring REX prefix."),
a540244d 3704 register_prefix, i.op[x].regs->reg_name);
773f551c 3705
29b0f896
AM		 3706 /* Otherwise it is equivalent to the extended register.
3707 Since the encoding doesn't change this is merely
3708 cosmetic cleanup for debug output. */
3709
3710 i.op[x].regs = i.op[x].regs + 8;
773f551c 3711 }
29b0f896
AM		 3712 }
3713 }
773f551c 3714
7ab9ffdd 3715 if (i.rex != 0)
29b0f896
AM		 3716 add_prefix (REX_OPCODE | i.rex);
3717
3718 /* We are ready to output the insn. */
3719 output_insn ();
3720}
3721
3722static char *
e3bb37b5 3723parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3724{
3725 char *l = line;
3726 char *token_start = l;
3727 char *mnem_p;
5c6af06e 3728 int supported;
d3ce72d0 3729 const insn_template *t;
b6169b20 3730 char *dot_p = NULL;
29b0f896 3731
29b0f896
AM		 3732 while (1)
3733 {
3734 mnem_p = mnemonic;
3735 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3736 {
b6169b20
L		 3737 if (*mnem_p == '.')
3738 dot_p = mnem_p;
29b0f896
AM		 3739 mnem_p++;
3740 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3741 {
29b0f896
AM		 3742 as_bad (_("no such instruction: `%s'"), token_start);
3743 return NULL;
3744 }
3745 l++;
3746 }
3747 if (!is_space_char (*l)
3748 && *l != END_OF_INSN
e44823cf
JB		 3749 && (intel_syntax
3750 || (*l != PREFIX_SEPARATOR
3751 && *l != ',')))
29b0f896
AM		 3752 {
3753 as_bad (_("invalid character %s in mnemonic"),
3754 output_invalid (*l));
3755 return NULL;
3756 }
3757 if (token_start == l)
3758 {
e44823cf 3759 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3760 as_bad (_("expecting prefix; got nothing"));
3761 else
3762 as_bad (_("expecting mnemonic; got nothing"));
3763 return NULL;
3764 }
45288df1 3765
29b0f896 3766 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3767 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3768
29b0f896
AM		 3769 if (*l != END_OF_INSN
3770 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3771 && current_templates
40fb9820 3772 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3773 {
c6fb90c8 3774 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3775 {
3776 as_bad ((flag_code != CODE_64BIT
3777 ? _("`%s' is only supported in 64-bit mode")
3778 : _("`%s' is not supported in 64-bit mode")),
3779 current_templates->start->name);
3780 return NULL;
3781 }
29b0f896
AM		 3782 /* If we are in 16-bit mode, do not allow addr16 or data16.
3783 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3784 if ((current_templates->start->opcode_modifier.size16
3785 || current_templates->start->opcode_modifier.size32)
29b0f896 3786 && flag_code != CODE_64BIT
40fb9820 3787 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3788 ^ (flag_code == CODE_16BIT)))
3789 {
3790 as_bad (_("redundant %s prefix"),
3791 current_templates->start->name);
3792 return NULL;
45288df1 3793 }
29b0f896
AM		 3794 /* Add prefix, checking for repeated prefixes. */
3795 switch (add_prefix (current_templates->start->base_opcode))
3796 {
c32fa91d 3797 case PREFIX_EXIST:
29b0f896 3798 return NULL;
c32fa91d 3799 case PREFIX_REP:
42164a71 3800 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3801 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3802 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3803 i.bnd_prefix = current_templates->start->name;
42164a71 3804 else
d5de92cf 3805 i.rep_prefix = current_templates->start->name;
29b0f896 3806 break;
c32fa91d
L		 3807 default:
3808 break;
29b0f896
AM		 3809 }
3810 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3811 token_start = ++l;
3812 }
3813 else
3814 break;
3815 }
45288df1 3816
30a55f88 3817 if (!current_templates)
b6169b20 3818 {
f8a5c266
L		 3819 /* Check if we should swap operand or force 32bit displacement in
3820 encoding. */
30a55f88
L		 3821 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3822 i.swap_operand = 1;
8d63c93e 3823 else if (mnem_p - 3 == dot_p
a501d77e
L		 3824 && dot_p[1] == 'd'
3825 && dot_p[2] == '8')
3826 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3827 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3828 && dot_p[1] == 'd'
3829 && dot_p[2] == '3'
3830 && dot_p[3] == '2')
a501d77e 3831 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3832 else
3833 goto check_suffix;
3834 mnem_p = dot_p;
3835 *dot_p = '\0';
d3ce72d0 3836 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3837 }
3838
29b0f896
AM		 3839 if (!current_templates)
3840 {
b6169b20 3841check_suffix:
29b0f896
AM		 3842 /* See if we can get a match by trimming off a suffix. */
3843 switch (mnem_p[-1])
3844 {
3845 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3846 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3847 i.suffix = SHORT_MNEM_SUFFIX;
3848 else
29b0f896
AM		 3849 case BYTE_MNEM_SUFFIX:
3850 case QWORD_MNEM_SUFFIX:
3851 i.suffix = mnem_p[-1];
3852 mnem_p[-1] = '\0';
d3ce72d0
NC		 3853 current_templates = (const templates *) hash_find (op_hash,
3854 mnemonic);
29b0f896
AM		 3855 break;
3856 case SHORT_MNEM_SUFFIX:
3857 case LONG_MNEM_SUFFIX:
3858 if (!intel_syntax)
3859 {
3860 i.suffix = mnem_p[-1];
3861 mnem_p[-1] = '\0';
d3ce72d0
NC		 3862 current_templates = (const templates *) hash_find (op_hash,
3863 mnemonic);
29b0f896
AM		 3864 }
3865 break;
252b5132 3866
29b0f896
AM		 3867 /* Intel Syntax. */
3868 case 'd':
3869 if (intel_syntax)
3870 {
9306ca4a 3871 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3872 i.suffix = SHORT_MNEM_SUFFIX;
3873 else
3874 i.suffix = LONG_MNEM_SUFFIX;
3875 mnem_p[-1] = '\0';
d3ce72d0
NC		 3876 current_templates = (const templates *) hash_find (op_hash,
3877 mnemonic);
29b0f896
AM		 3878 }
3879 break;
3880 }
3881 if (!current_templates)
3882 {
3883 as_bad (_("no such instruction: `%s'"), token_start);
3884 return NULL;
3885 }
3886 }
252b5132 3887
40fb9820
L		 3888 if (current_templates->start->opcode_modifier.jump
3889 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3890 {
3891 /* Check for a branch hint. We allow ",pt" and ",pn" for
3892 predict taken and predict not taken respectively.
3893 I'm not sure that branch hints actually do anything on loop
3894 and jcxz insns (JumpByte) for current Pentium4 chips. They
3895 may work in the future and it doesn't hurt to accept them
3896 now. */
3897 if (l[0] == ',' && l[1] == 'p')
3898 {
3899 if (l[2] == 't')
3900 {
3901 if (!add_prefix (DS_PREFIX_OPCODE))
3902 return NULL;
3903 l += 3;
3904 }
3905 else if (l[2] == 'n')
3906 {
3907 if (!add_prefix (CS_PREFIX_OPCODE))
3908 return NULL;
3909 l += 3;
3910 }
3911 }
3912 }
3913 /* Any other comma loses. */
3914 if (*l == ',')
3915 {
3916 as_bad (_("invalid character %s in mnemonic"),
3917 output_invalid (*l));
3918 return NULL;
3919 }
252b5132 3920
29b0f896 3921 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3922 supported = 0;
3923 for (t = current_templates->start; t < current_templates->end; ++t)
3924 {
c0f3af97
L		 3925 supported |= cpu_flags_match (t);
3926 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3927 goto skip;
5c6af06e 3928 }
3629bb00 3929
c0f3af97 3930 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3931 {
3932 as_bad (flag_code == CODE_64BIT
3933 ? _("`%s' is not supported in 64-bit mode")
3934 : _("`%s' is only supported in 64-bit mode"),
3935 current_templates->start->name);
3936 return NULL;
3937 }
c0f3af97 3938 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3939 {
3629bb00 3940 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3941 current_templates->start->name,
41aacd83 3942 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3943 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3944 return NULL;
29b0f896 3945 }
3629bb00
L		 3946
3947skip:
3948 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3949 && (flag_code != CODE_16BIT))
29b0f896
AM		 3950 {
3951 as_warn (_("use .code16 to ensure correct addressing mode"));
3952 }
252b5132 3953
29b0f896
AM		 3954 return l;
3955}
252b5132 3956
29b0f896 3957static char *
e3bb37b5 3958parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3959{
3960 char *token_start;
3138f287 3961
29b0f896
AM		 3962 /* 1 if operand is pending after ','. */
3963 unsigned int expecting_operand = 0;
252b5132 3964
29b0f896
AM		 3965 /* Non-zero if operand parens not balanced. */
3966 unsigned int paren_not_balanced;
3967
3968 while (*l != END_OF_INSN)
3969 {
3970 /* Skip optional white space before operand. */
3971 if (is_space_char (*l))
3972 ++l;
d02603dc 3973 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 3974 {
3975 as_bad (_("invalid character %s before operand %d"),
3976 output_invalid (*l),
3977 i.operands + 1);
3978 return NULL;
3979 }
d02603dc 3980 token_start = l; /* After white space. */
29b0f896
AM		 3981 paren_not_balanced = 0;
3982 while (paren_not_balanced || *l != ',')
3983 {
3984 if (*l == END_OF_INSN)
3985 {
3986 if (paren_not_balanced)
3987 {
3988 if (!intel_syntax)
3989 as_bad (_("unbalanced parenthesis in operand %d."),
3990 i.operands + 1);
3991 else
3992 as_bad (_("unbalanced brackets in operand %d."),
3993 i.operands + 1);
3994 return NULL;
3995 }
3996 else
3997 break; /* we are done */
3998 }
d02603dc 3999 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4000 {
4001 as_bad (_("invalid character %s in operand %d"),
4002 output_invalid (*l),
4003 i.operands + 1);
4004 return NULL;
4005 }
4006 if (!intel_syntax)
4007 {
4008 if (*l == '(')
4009 ++paren_not_balanced;
4010 if (*l == ')')
4011 --paren_not_balanced;
4012 }
4013 else
4014 {
4015 if (*l == '[')
4016 ++paren_not_balanced;
4017 if (*l == ']')
4018 --paren_not_balanced;
4019 }
4020 l++;
4021 }
4022 if (l != token_start)
4023 { /* Yes, we've read in another operand. */
4024 unsigned int operand_ok;
4025 this_operand = i.operands++;
7d5e4556 4026 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4027 if (i.operands > MAX_OPERANDS)
4028 {
4029 as_bad (_("spurious operands; (%d operands/instruction max)"),
4030 MAX_OPERANDS);
4031 return NULL;
4032 }
4033 /* Now parse operand adding info to 'i' as we go along. */
4034 END_STRING_AND_SAVE (l);
4035
4036 if (intel_syntax)
4037 operand_ok =
4038 i386_intel_operand (token_start,
4039 intel_float_operand (mnemonic));
4040 else
a7619375 4041 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4042
4043 RESTORE_END_STRING (l);
4044 if (!operand_ok)
4045 return NULL;
4046 }
4047 else
4048 {
4049 if (expecting_operand)
4050 {
4051 expecting_operand_after_comma:
4052 as_bad (_("expecting operand after ','; got nothing"));
4053 return NULL;
4054 }
4055 if (*l == ',')
4056 {
4057 as_bad (_("expecting operand before ','; got nothing"));
4058 return NULL;
4059 }
4060 }
7f3f1ea2 4061
29b0f896
AM		 4062 /* Now *l must be either ',' or END_OF_INSN. */
4063 if (*l == ',')
4064 {
4065 if (*++l == END_OF_INSN)
4066 {
4067 /* Just skip it, if it's \n complain. */
4068 goto expecting_operand_after_comma;
4069 }
4070 expecting_operand = 1;
4071 }
4072 }
4073 return l;
4074}
7f3f1ea2 4075
050dfa73 4076static void
4d456e3d 4077swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4078{
4079 union i386_op temp_op;
40fb9820 4080 i386_operand_type temp_type;
050dfa73 4081 enum bfd_reloc_code_real temp_reloc;
4eed87de 4082
050dfa73
MM		 4083 temp_type = i.types[xchg2];
4084 i.types[xchg2] = i.types[xchg1];
4085 i.types[xchg1] = temp_type;
4086 temp_op = i.op[xchg2];
4087 i.op[xchg2] = i.op[xchg1];
4088 i.op[xchg1] = temp_op;
4089 temp_reloc = i.reloc[xchg2];
4090 i.reloc[xchg2] = i.reloc[xchg1];
4091 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4092
4093 if (i.mask)
4094 {
4095 if (i.mask->operand == xchg1)
4096 i.mask->operand = xchg2;
4097 else if (i.mask->operand == xchg2)
4098 i.mask->operand = xchg1;
4099 }
4100 if (i.broadcast)
4101 {
4102 if (i.broadcast->operand == xchg1)
4103 i.broadcast->operand = xchg2;
4104 else if (i.broadcast->operand == xchg2)
4105 i.broadcast->operand = xchg1;
4106 }
4107 if (i.rounding)
4108 {
4109 if (i.rounding->operand == xchg1)
4110 i.rounding->operand = xchg2;
4111 else if (i.rounding->operand == xchg2)
4112 i.rounding->operand = xchg1;
4113 }
050dfa73
MM		 4114}
4115
29b0f896 4116static void
e3bb37b5 4117swap_operands (void)
29b0f896 4118{
b7c61d9a 4119 switch (i.operands)
050dfa73 4120 {
c0f3af97 4121 case 5:
b7c61d9a 4122 case 4:
4d456e3d 4123 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4124 case 3:
4125 case 2:
4d456e3d 4126 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4127 break;
4128 default:
4129 abort ();
29b0f896 4130 }
29b0f896
AM		 4131
4132 if (i.mem_operands == 2)
4133 {
4134 const seg_entry *temp_seg;
4135 temp_seg = i.seg[0];
4136 i.seg[0] = i.seg[1];
4137 i.seg[1] = temp_seg;
4138 }
4139}
252b5132 4140
29b0f896
AM		 4141/* Try to ensure constant immediates are represented in the smallest
4142 opcode possible. */
4143static void
e3bb37b5 4144optimize_imm (void)
29b0f896
AM		 4145{
4146 char guess_suffix = 0;
4147 int op;
252b5132 4148
29b0f896
AM		 4149 if (i.suffix)
4150 guess_suffix = i.suffix;
4151 else if (i.reg_operands)
4152 {
4153 /* Figure out a suffix from the last register operand specified.
4154 We can't do this properly yet, ie. excluding InOutPortReg,
4155 but the following works for instructions with immediates.
4156 In any case, we can't set i.suffix yet. */
4157 for (op = i.operands; --op >= 0;)
40fb9820 4158 if (i.types[op].bitfield.reg8)
7ab9ffdd 4159 {
40fb9820
L		 4160 guess_suffix = BYTE_MNEM_SUFFIX;
4161 break;
4162 }
4163 else if (i.types[op].bitfield.reg16)
252b5132 4164 {
40fb9820
L		 4165 guess_suffix = WORD_MNEM_SUFFIX;
4166 break;
4167 }
4168 else if (i.types[op].bitfield.reg32)
4169 {
4170 guess_suffix = LONG_MNEM_SUFFIX;
4171 break;
4172 }
4173 else if (i.types[op].bitfield.reg64)
4174 {
4175 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4176 break;
252b5132 4177 }
29b0f896
AM		 4178 }
4179 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4180 guess_suffix = WORD_MNEM_SUFFIX;
4181
4182 for (op = i.operands; --op >= 0;)
40fb9820 4183 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4184 {
4185 switch (i.op[op].imms->X_op)
252b5132 4186 {
29b0f896
AM		 4187 case O_constant:
4188 /* If a suffix is given, this operand may be shortened. */
4189 switch (guess_suffix)
252b5132 4190 {
29b0f896 4191 case LONG_MNEM_SUFFIX:
40fb9820
L		 4192 i.types[op].bitfield.imm32 = 1;
4193 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4194 break;
4195 case WORD_MNEM_SUFFIX:
40fb9820
L		 4196 i.types[op].bitfield.imm16 = 1;
4197 i.types[op].bitfield.imm32 = 1;
4198 i.types[op].bitfield.imm32s = 1;
4199 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4200 break;
4201 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4202 i.types[op].bitfield.imm8 = 1;
4203 i.types[op].bitfield.imm8s = 1;
4204 i.types[op].bitfield.imm16 = 1;
4205 i.types[op].bitfield.imm32 = 1;
4206 i.types[op].bitfield.imm32s = 1;
4207 i.types[op].bitfield.imm64 = 1;
29b0f896 4208 break;
252b5132 4209 }
252b5132 4210
29b0f896
AM		 4211 /* If this operand is at most 16 bits, convert it
4212 to a signed 16 bit number before trying to see
4213 whether it will fit in an even smaller size.
4214 This allows a 16-bit operand such as $0xffe0 to
4215 be recognised as within Imm8S range. */
40fb9820 4216 if ((i.types[op].bitfield.imm16)
29b0f896 4217 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4218 {
29b0f896
AM		 4219 i.op[op].imms->X_add_number =
4220 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4221 }
40fb9820 4222 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4223 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4224 == 0))
4225 {
4226 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4227 ^ ((offsetT) 1 << 31))
4228 - ((offsetT) 1 << 31));
4229 }
40fb9820 4230 i.types[op]
c6fb90c8
L		 4231 = operand_type_or (i.types[op],
4232 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4233
29b0f896
AM		 4234 /* We must avoid matching of Imm32 templates when 64bit
4235 only immediate is available. */
4236 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4237 i.types[op].bitfield.imm32 = 0;
29b0f896 4238 break;
252b5132 4239
29b0f896
AM		 4240 case O_absent:
4241 case O_register:
4242 abort ();
4243
4244 /* Symbols and expressions. */
4245 default:
9cd96992
JB		 4246 /* Convert symbolic operand to proper sizes for matching, but don't
4247 prevent matching a set of insns that only supports sizes other
4248 than those matching the insn suffix. */
4249 {
40fb9820 4250 i386_operand_type mask, allowed;
d3ce72d0 4251 const insn_template *t;
9cd96992 4252
0dfbf9d7
L		 4253 operand_type_set (&mask, 0);
4254 operand_type_set (&allowed, 0);
40fb9820 4255
4eed87de
AM		 4256 for (t = current_templates->start;
4257 t < current_templates->end;
4258 ++t)
c6fb90c8
L		 4259 allowed = operand_type_or (allowed,
4260 t->operand_types[op]);
9cd96992
JB		 4261 switch (guess_suffix)
4262 {
4263 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4264 mask.bitfield.imm64 = 1;
4265 mask.bitfield.imm32s = 1;
9cd96992
JB		 4266 break;
4267 case LONG_MNEM_SUFFIX:
40fb9820 4268 mask.bitfield.imm32 = 1;
9cd96992
JB		 4269 break;
4270 case WORD_MNEM_SUFFIX:
40fb9820 4271 mask.bitfield.imm16 = 1;
9cd96992
JB		 4272 break;
4273 case BYTE_MNEM_SUFFIX:
40fb9820 4274 mask.bitfield.imm8 = 1;
9cd96992
JB		 4275 break;
4276 default:
9cd96992
JB		 4277 break;
4278 }
c6fb90c8 4279 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4280 if (!operand_type_all_zero (&allowed))
c6fb90c8 4281 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4282 }
29b0f896 4283 break;
252b5132 4284 }
29b0f896
AM		 4285 }
4286}
47926f60 4287
29b0f896
AM		 4288/* Try to use the smallest displacement type too. */
4289static void
e3bb37b5 4290optimize_disp (void)
29b0f896
AM		 4291{
4292 int op;
3e73aa7c 4293
29b0f896 4294 for (op = i.operands; --op >= 0;)
40fb9820 4295 if (operand_type_check (i.types[op], disp))
252b5132 4296 {
b300c311 4297 if (i.op[op].disps->X_op == O_constant)
252b5132 4298 {
91d6fa6a 4299 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4300
40fb9820 4301 if (i.types[op].bitfield.disp16
91d6fa6a 4302 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4303 {
4304 /* If this operand is at most 16 bits, convert
4305 to a signed 16 bit number and don't use 64bit
4306 displacement. */
91d6fa6a 4307 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4308 i.types[op].bitfield.disp64 = 0;
b300c311 4309 }
40fb9820 4310 if (i.types[op].bitfield.disp32
91d6fa6a 4311 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4312 {
4313 /* If this operand is at most 32 bits, convert
4314 to a signed 32 bit number and don't use 64bit
4315 displacement. */
91d6fa6a
NC		 4316 op_disp &= (((offsetT) 2 << 31) - 1);
4317 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4318 i.types[op].bitfield.disp64 = 0;
b300c311 4319 }
91d6fa6a 4320 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4321 {
40fb9820
L		 4322 i.types[op].bitfield.disp8 = 0;
4323 i.types[op].bitfield.disp16 = 0;
4324 i.types[op].bitfield.disp32 = 0;
4325 i.types[op].bitfield.disp32s = 0;
4326 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4327 i.op[op].disps = 0;
4328 i.disp_operands--;
4329 }
4330 else if (flag_code == CODE_64BIT)
4331 {
91d6fa6a 4332 if (fits_in_signed_long (op_disp))
28a9d8f5 4333 {
40fb9820
L		 4334 i.types[op].bitfield.disp64 = 0;
4335 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4336 }
0e1147d9 4337 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4338 && fits_in_unsigned_long (op_disp))
40fb9820 4339 i.types[op].bitfield.disp32 = 1;
b300c311 4340 }
40fb9820
L		 4341 if ((i.types[op].bitfield.disp32
4342 || i.types[op].bitfield.disp32s
4343 || i.types[op].bitfield.disp16)
91d6fa6a 4344 && fits_in_signed_byte (op_disp))
40fb9820 4345 i.types[op].bitfield.disp8 = 1;
252b5132 4346 }
67a4f2b7
AO		 4347 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4348 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4349 {
4350 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4351 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4352 i.types[op].bitfield.disp8 = 0;
4353 i.types[op].bitfield.disp16 = 0;
4354 i.types[op].bitfield.disp32 = 0;
4355 i.types[op].bitfield.disp32s = 0;
4356 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4357 }
4358 else
b300c311 4359 /* We only support 64bit displacement on constants. */
40fb9820 4360 i.types[op].bitfield.disp64 = 0;
252b5132 4361 }
29b0f896
AM		 4362}
4363
6c30d220
L		 4364/* Check if operands are valid for the instruction. */
4365
4366static int
4367check_VecOperands (const insn_template *t)
4368{
43234a1e
L		 4369 unsigned int op;
4370
6c30d220
L		 4371 /* Without VSIB byte, we can't have a vector register for index. */
4372 if (!t->opcode_modifier.vecsib
4373 && i.index_reg
4374 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4375 || i.index_reg->reg_type.bitfield.regymm
4376 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4377 {
4378 i.error = unsupported_vector_index_register;
4379 return 1;
4380 }
4381
ad8ecc81
MZ		 4382 /* Check if default mask is allowed. */
4383 if (t->opcode_modifier.nodefmask
4384 && (!i.mask || i.mask->mask->reg_num == 0))
4385 {
4386 i.error = no_default_mask;
4387 return 1;
4388 }
4389
7bab8ab5
JB		 4390 /* For VSIB byte, we need a vector register for index, and all vector
4391 registers must be distinct. */
4392 if (t->opcode_modifier.vecsib)
4393 {
4394 if (!i.index_reg
6c30d220
L		 4395 || !((t->opcode_modifier.vecsib == VecSIB128
4396 && i.index_reg->reg_type.bitfield.regxmm)
4397 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4398 && i.index_reg->reg_type.bitfield.regymm)
4399 || (t->opcode_modifier.vecsib == VecSIB512
4400 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4401 {
4402 i.error = invalid_vsib_address;
4403 return 1;
4404 }
4405
43234a1e
L		 4406 gas_assert (i.reg_operands == 2 || i.mask);
4407 if (i.reg_operands == 2 && !i.mask)
4408 {
4409 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4410 || i.types[0].bitfield.regymm);
43234a1e 4411 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4412 || i.types[2].bitfield.regymm);
43234a1e
L		 4413 if (operand_check == check_none)
4414 return 0;
4415 if (register_number (i.op[0].regs)
4416 != register_number (i.index_reg)
4417 && register_number (i.op[2].regs)
4418 != register_number (i.index_reg)
4419 && register_number (i.op[0].regs)
4420 != register_number (i.op[2].regs))
4421 return 0;
4422 if (operand_check == check_error)
4423 {
4424 i.error = invalid_vector_register_set;
4425 return 1;
4426 }
4427 as_warn (_("mask, index, and destination registers should be distinct"));
4428 }
8444f82a
MZ		 4429 else if (i.reg_operands == 1 && i.mask)
4430 {
4431 if ((i.types[1].bitfield.regymm
4432 || i.types[1].bitfield.regzmm)
4433 && (register_number (i.op[1].regs)
4434 == register_number (i.index_reg)))
4435 {
4436 if (operand_check == check_error)
4437 {
4438 i.error = invalid_vector_register_set;
4439 return 1;
4440 }
4441 if (operand_check != check_none)
4442 as_warn (_("index and destination registers should be distinct"));
4443 }
4444 }
43234a1e 4445 }
7bab8ab5 4446
43234a1e
L		 4447 /* Check if broadcast is supported by the instruction and is applied
4448 to the memory operand. */
4449 if (i.broadcast)
4450 {
4451 int broadcasted_opnd_size;
4452
4453 /* Check if specified broadcast is supported in this instruction,
4454 and it's applied to memory operand of DWORD or QWORD type,
4455 depending on VecESize. */
4456 if (i.broadcast->type != t->opcode_modifier.broadcast
4457 || !i.types[i.broadcast->operand].bitfield.mem
4458 || (t->opcode_modifier.vecesize == 0
4459 && !i.types[i.broadcast->operand].bitfield.dword
4460 && !i.types[i.broadcast->operand].bitfield.unspecified)
4461 || (t->opcode_modifier.vecesize == 1
4462 && !i.types[i.broadcast->operand].bitfield.qword
4463 && !i.types[i.broadcast->operand].bitfield.unspecified))
4464 goto bad_broadcast;
4465
4466 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4467 if (i.broadcast->type == BROADCAST_1TO16)
4468 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4469 else if (i.broadcast->type == BROADCAST_1TO8)
4470 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4471 else if (i.broadcast->type == BROADCAST_1TO4)
4472 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4473 else if (i.broadcast->type == BROADCAST_1TO2)
4474 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4475 else
4476 goto bad_broadcast;
4477
4478 if ((broadcasted_opnd_size == 256
4479 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4480 || (broadcasted_opnd_size == 512
4481 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4482 {
4483 bad_broadcast:
4484 i.error = unsupported_broadcast;
4485 return 1;
4486 }
4487 }
4488 /* If broadcast is supported in this instruction, we need to check if
4489 operand of one-element size isn't specified without broadcast. */
4490 else if (t->opcode_modifier.broadcast && i.mem_operands)
4491 {
4492 /* Find memory operand. */
4493 for (op = 0; op < i.operands; op++)
4494 if (operand_type_check (i.types[op], anymem))
4495 break;
4496 gas_assert (op < i.operands);
4497 /* Check size of the memory operand. */
4498 if ((t->opcode_modifier.vecesize == 0
4499 && i.types[op].bitfield.dword)
4500 || (t->opcode_modifier.vecesize == 1
4501 && i.types[op].bitfield.qword))
4502 {
4503 i.error = broadcast_needed;
4504 return 1;
4505 }
4506 }
4507
4508 /* Check if requested masking is supported. */
4509 if (i.mask
4510 && (!t->opcode_modifier.masking
4511 || (i.mask->zeroing
4512 && t->opcode_modifier.masking == MERGING_MASKING)))
4513 {
4514 i.error = unsupported_masking;
4515 return 1;
4516 }
4517
4518 /* Check if masking is applied to dest operand. */
4519 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4520 {
4521 i.error = mask_not_on_destination;
4522 return 1;
4523 }
4524
43234a1e
L		 4525 /* Check RC/SAE. */
4526 if (i.rounding)
4527 {
4528 if ((i.rounding->type != saeonly
4529 && !t->opcode_modifier.staticrounding)
4530 || (i.rounding->type == saeonly
4531 && (t->opcode_modifier.staticrounding
4532 || !t->opcode_modifier.sae)))
4533 {
4534 i.error = unsupported_rc_sae;
4535 return 1;
4536 }
4537 /* If the instruction has several immediate operands and one of
4538 them is rounding, the rounding operand should be the last
4539 immediate operand. */
4540 if (i.imm_operands > 1
4541 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4542 {
43234a1e 4543 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4544 return 1;
4545 }
6c30d220
L		 4546 }
4547
43234a1e
L		 4548 /* Check vector Disp8 operand. */
4549 if (t->opcode_modifier.disp8memshift)
4550 {
4551 if (i.broadcast)
4552 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4553 else
4554 i.memshift = t->opcode_modifier.disp8memshift;
4555
4556 for (op = 0; op < i.operands; op++)
4557 if (operand_type_check (i.types[op], disp)
4558 && i.op[op].disps->X_op == O_constant)
4559 {
4560 offsetT value = i.op[op].disps->X_add_number;
4561 int vec_disp8_ok = fits_in_vec_disp8 (value);
4562 if (t->operand_types [op].bitfield.vec_disp8)
4563 {
4564 if (vec_disp8_ok)
4565 i.types[op].bitfield.vec_disp8 = 1;
4566 else
4567 {
4568 /* Vector insn can only have Vec_Disp8/Disp32 in
4569 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4570 mode. */
4571 i.types[op].bitfield.disp8 = 0;
4572 if (flag_code != CODE_16BIT)
4573 i.types[op].bitfield.disp16 = 0;
4574 }
4575 }
4576 else if (flag_code != CODE_16BIT)
4577 {
4578 /* One form of this instruction supports vector Disp8.
4579 Try vector Disp8 if we need to use Disp32. */
4580 if (vec_disp8_ok && !fits_in_signed_byte (value))
4581 {
4582 i.error = try_vector_disp8;
4583 return 1;
4584 }
4585 }
4586 }
4587 }
4588 else
4589 i.memshift = -1;
4590
6c30d220
L		 4591 return 0;
4592}
4593
43f3e2ee 4594/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4595 operand types. */
4596
4597static int
4598VEX_check_operands (const insn_template *t)
4599{
43234a1e
L		 4600 /* VREX is only valid with EVEX prefix. */
4601 if (i.need_vrex && !t->opcode_modifier.evex)
4602 {
4603 i.error = invalid_register_operand;
4604 return 1;
4605 }
4606
a683cc34
SP		 4607 if (!t->opcode_modifier.vex)
4608 return 0;
4609
4610 /* Only check VEX_Imm4, which must be the first operand. */
4611 if (t->operand_types[0].bitfield.vec_imm4)
4612 {
4613 if (i.op[0].imms->X_op != O_constant
4614 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4615 {
a65babc9 4616 i.error = bad_imm4;
891edac4
L		 4617 return 1;
4618 }
a683cc34
SP		 4619
4620 /* Turn off Imm8 so that update_imm won't complain. */
4621 i.types[0] = vec_imm4;
4622 }
4623
4624 return 0;
4625}
4626
d3ce72d0 4627static const insn_template *
e3bb37b5 4628match_template (void)
29b0f896
AM		 4629{
4630 /* Points to template once we've found it. */
d3ce72d0 4631 const insn_template *t;
40fb9820 4632 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4633 i386_operand_type overlap4;
29b0f896 4634 unsigned int found_reverse_match;
40fb9820
L		 4635 i386_opcode_modifier suffix_check;
4636 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4637 int addr_prefix_disp;
a5c311ca 4638 unsigned int j;
3629bb00 4639 unsigned int found_cpu_match;
45664ddb 4640 unsigned int check_register;
5614d22c 4641 enum i386_error specific_error = 0;
29b0f896 4642
c0f3af97
L		 4643#if MAX_OPERANDS != 5
4644# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4645#endif
4646
29b0f896 4647 found_reverse_match = 0;
539e75ad 4648 addr_prefix_disp = -1;
40fb9820
L		 4649
4650 memset (&suffix_check, 0, sizeof (suffix_check));
4651 if (i.suffix == BYTE_MNEM_SUFFIX)
4652 suffix_check.no_bsuf = 1;
4653 else if (i.suffix == WORD_MNEM_SUFFIX)
4654 suffix_check.no_wsuf = 1;
4655 else if (i.suffix == SHORT_MNEM_SUFFIX)
4656 suffix_check.no_ssuf = 1;
4657 else if (i.suffix == LONG_MNEM_SUFFIX)
4658 suffix_check.no_lsuf = 1;
4659 else if (i.suffix == QWORD_MNEM_SUFFIX)
4660 suffix_check.no_qsuf = 1;
4661 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4662 suffix_check.no_ldsuf = 1;
29b0f896 4663
01559ecc
L		 4664 /* Must have right number of operands. */
4665 i.error = number_of_operands_mismatch;
4666
45aa61fe 4667 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4668 {
539e75ad
L		 4669 addr_prefix_disp = -1;
4670
29b0f896
AM		 4671 if (i.operands != t->operands)
4672 continue;
4673
50aecf8c 4674 /* Check processor support. */
a65babc9 4675 i.error = unsupported;
c0f3af97
L		 4676 found_cpu_match = (cpu_flags_match (t)
4677 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4678 if (!found_cpu_match)
4679 continue;
4680
e1d4d893 4681 /* Check old gcc support. */
a65babc9 4682 i.error = old_gcc_only;
e1d4d893
L		 4683 if (!old_gcc && t->opcode_modifier.oldgcc)
4684 continue;
4685
4686 /* Check AT&T mnemonic. */
a65babc9 4687 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4688 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4689 continue;
4690
891edac4 4691 /* Check AT&T/Intel syntax. */
a65babc9 4692 i.error = unsupported_syntax;
5c07affc
L		 4693 if ((intel_syntax && t->opcode_modifier.attsyntax)
4694 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4695 continue;
4696
20592a94 4697 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4698 i.error = invalid_instruction_suffix;
567e4e96
L		 4699 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4700 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4701 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4702 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4703 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4704 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4705 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4706 continue;
4707
5c07affc 4708 if (!operand_size_match (t))
7d5e4556 4709 continue;
539e75ad 4710
5c07affc
L		 4711 for (j = 0; j < MAX_OPERANDS; j++)
4712 operand_types[j] = t->operand_types[j];
4713
45aa61fe
AM		 4714 /* In general, don't allow 64-bit operands in 32-bit mode. */
4715 if (i.suffix == QWORD_MNEM_SUFFIX
4716 && flag_code != CODE_64BIT
4717 && (intel_syntax
40fb9820 4718 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4719 && !intel_float_operand (t->name))
4720 : intel_float_operand (t->name) != 2)
40fb9820 4721 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4722 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4723 && !operand_types[0].bitfield.regymm
4724 && !operand_types[0].bitfield.regzmm)
40fb9820 4725 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4726 && operand_types[t->operands > 1].bitfield.regxmm
4727 && operand_types[t->operands > 1].bitfield.regymm
4728 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4729 && (t->base_opcode != 0x0fc7
4730 || t->extension_opcode != 1 /* cmpxchg8b */))
4731 continue;
4732
192dc9c6
JB		 4733 /* In general, don't allow 32-bit operands on pre-386. */
4734 else if (i.suffix == LONG_MNEM_SUFFIX
4735 && !cpu_arch_flags.bitfield.cpui386
4736 && (intel_syntax
4737 ? (!t->opcode_modifier.ignoresize
4738 && !intel_float_operand (t->name))
4739 : intel_float_operand (t->name) != 2)
4740 && ((!operand_types[0].bitfield.regmmx
4741 && !operand_types[0].bitfield.regxmm)
4742 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4743 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4744 continue;
4745
29b0f896 4746 /* Do not verify operands when there are none. */
50aecf8c 4747 else
29b0f896 4748 {
c6fb90c8 4749 if (!t->operands)
2dbab7d5
L		 4750 /* We've found a match; break out of loop. */
4751 break;
29b0f896 4752 }
252b5132 4753
539e75ad
L		 4754 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4755 into Disp32/Disp16/Disp32 operand. */
4756 if (i.prefix[ADDR_PREFIX] != 0)
4757 {
40fb9820 4758 /* There should be only one Disp operand. */
539e75ad
L		 4759 switch (flag_code)
4760 {
4761 case CODE_16BIT:
40fb9820
L		 4762 for (j = 0; j < MAX_OPERANDS; j++)
4763 {
4764 if (operand_types[j].bitfield.disp16)
4765 {
4766 addr_prefix_disp = j;
4767 operand_types[j].bitfield.disp32 = 1;
4768 operand_types[j].bitfield.disp16 = 0;
4769 break;
4770 }
4771 }
539e75ad
L		 4772 break;
4773 case CODE_32BIT:
40fb9820
L		 4774 for (j = 0; j < MAX_OPERANDS; j++)
4775 {
4776 if (operand_types[j].bitfield.disp32)
4777 {
4778 addr_prefix_disp = j;
4779 operand_types[j].bitfield.disp32 = 0;
4780 operand_types[j].bitfield.disp16 = 1;
4781 break;
4782 }
4783 }
539e75ad
L		 4784 break;
4785 case CODE_64BIT:
40fb9820
L		 4786 for (j = 0; j < MAX_OPERANDS; j++)
4787 {
4788 if (operand_types[j].bitfield.disp64)
4789 {
4790 addr_prefix_disp = j;
4791 operand_types[j].bitfield.disp64 = 0;
4792 operand_types[j].bitfield.disp32 = 1;
4793 break;
4794 }
4795 }
539e75ad
L		 4796 break;
4797 }
539e75ad
L		 4798 }
4799
56ffb741
L		 4800 /* We check register size if needed. */
4801 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4802 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4803 switch (t->operands)
4804 {
4805 case 1:
40fb9820 4806 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4807 continue;
4808 break;
4809 case 2:
8b38ad71
L		 4810 /* xchg %eax, %eax is a special case. It is an aliase for nop
4811 only in 32bit mode and we can use opcode 0x90. In 64bit
4812 mode, we can't use 0x90 for xchg %eax, %eax since it should
4813 zero-extend %eax to %rax. */
4814 if (flag_code == CODE_64BIT
4815 && t->base_opcode == 0x90
0dfbf9d7
L		 4816 && operand_type_equal (&i.types [0], &acc32)
4817 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4818 continue;
b6169b20
L		 4819 if (i.swap_operand)
4820 {
4821 /* If we swap operand in encoding, we either match
4822 the next one or reverse direction of operands. */
4823 if (t->opcode_modifier.s)
4824 continue;
4825 else if (t->opcode_modifier.d)
4826 goto check_reverse;
4827 }
4828
29b0f896 4829 case 3:
fa99fab2
L		 4830 /* If we swap operand in encoding, we match the next one. */
4831 if (i.swap_operand && t->opcode_modifier.s)
4832 continue;
f48ff2ae 4833 case 4:
c0f3af97 4834 case 5:
c6fb90c8 4835 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4836 if (!operand_type_match (overlap0, i.types[0])
4837 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4838 || (check_register
4839 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4840 operand_types[0],
4841 overlap1, i.types[1],
4842 operand_types[1])))
29b0f896
AM		 4843 {
4844 /* Check if other direction is valid ... */
40fb9820 4845 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4846 continue;
4847
b6169b20 4848check_reverse:
29b0f896 4849 /* Try reversing direction of operands. */
c6fb90c8
L		 4850 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4851 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4852 if (!operand_type_match (overlap0, i.types[0])
4853 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4854 || (check_register
4855 && !operand_type_register_match (overlap0,
4856 i.types[0],
4857 operand_types[1],
4858 overlap1,
4859 i.types[1],
4860 operand_types[0])))
29b0f896
AM		 4861 {
4862 /* Does not match either direction. */
4863 continue;
4864 }
4865 /* found_reverse_match holds which of D or FloatDR
4866 we've found. */
40fb9820 4867 if (t->opcode_modifier.d)
8a2ed489 4868 found_reverse_match = Opcode_D;
40fb9820 4869 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4870 found_reverse_match = Opcode_FloatD;
4871 else
4872 found_reverse_match = 0;
40fb9820 4873 if (t->opcode_modifier.floatr)
8a2ed489 4874 found_reverse_match |= Opcode_FloatR;
29b0f896 4875 }
f48ff2ae 4876 else
29b0f896 4877 {
f48ff2ae 4878 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4879 switch (t->operands)
4880 {
c0f3af97
L		 4881 case 5:
4882 overlap4 = operand_type_and (i.types[4],
4883 operand_types[4]);
d1cbb4db 4884 case 4:
c6fb90c8
L		 4885 overlap3 = operand_type_and (i.types[3],
4886 operand_types[3]);
d1cbb4db 4887 case 3:
c6fb90c8
L		 4888 overlap2 = operand_type_and (i.types[2],
4889 operand_types[2]);
d1cbb4db
L		 4890 break;
4891 }
29b0f896 4892
f48ff2ae
L		 4893 switch (t->operands)
4894 {
c0f3af97
L		 4895 case 5:
4896 if (!operand_type_match (overlap4, i.types[4])
4897 || !operand_type_register_match (overlap3,
4898 i.types[3],
4899 operand_types[3],
4900 overlap4,
4901 i.types[4],
4902 operand_types[4]))
4903 continue;
f48ff2ae 4904 case 4:
40fb9820 4905 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4906 || (check_register
4907 && !operand_type_register_match (overlap2,
4908 i.types[2],
4909 operand_types[2],
4910 overlap3,
4911 i.types[3],
4912 operand_types[3])))
f48ff2ae
L		 4913 continue;
4914 case 3:
4915 /* Here we make use of the fact that there are no
4916 reverse match 3 operand instructions, and all 3
4917 operand instructions only need to be checked for
4918 register consistency between operands 2 and 3. */
40fb9820 4919 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4920 || (check_register
4921 && !operand_type_register_match (overlap1,
4922 i.types[1],
4923 operand_types[1],
4924 overlap2,
4925 i.types[2],
4926 operand_types[2])))
f48ff2ae
L		 4927 continue;
4928 break;
4929 }
29b0f896 4930 }
f48ff2ae 4931 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4932 slip through to break. */
4933 }
3629bb00 4934 if (!found_cpu_match)
29b0f896
AM		 4935 {
4936 found_reverse_match = 0;
4937 continue;
4938 }
c0f3af97 4939
5614d22c
JB		 4940 /* Check if vector and VEX operands are valid. */
4941 if (check_VecOperands (t) || VEX_check_operands (t))
4942 {
4943 specific_error = i.error;
4944 continue;
4945 }
a683cc34 4946
29b0f896
AM		 4947 /* We've found a match; break out of loop. */
4948 break;
4949 }
4950
4951 if (t == current_templates->end)
4952 {
4953 /* We found no match. */
a65babc9 4954 const char *err_msg;
5614d22c 4955 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4956 {
4957 default:
4958 abort ();
86e026a4 4959 case operand_size_mismatch:
a65babc9
L		 4960 err_msg = _("operand size mismatch");
4961 break;
4962 case operand_type_mismatch:
4963 err_msg = _("operand type mismatch");
4964 break;
4965 case register_type_mismatch:
4966 err_msg = _("register type mismatch");
4967 break;
4968 case number_of_operands_mismatch:
4969 err_msg = _("number of operands mismatch");
4970 break;
4971 case invalid_instruction_suffix:
4972 err_msg = _("invalid instruction suffix");
4973 break;
4974 case bad_imm4:
4a2608e3 4975 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4976 break;
4977 case old_gcc_only:
4978 err_msg = _("only supported with old gcc");
4979 break;
4980 case unsupported_with_intel_mnemonic:
4981 err_msg = _("unsupported with Intel mnemonic");
4982 break;
4983 case unsupported_syntax:
4984 err_msg = _("unsupported syntax");
4985 break;
4986 case unsupported:
35262a23 4987 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4988 current_templates->start->name);
4989 return NULL;
6c30d220
L		 4990 case invalid_vsib_address:
4991 err_msg = _("invalid VSIB address");
4992 break;
7bab8ab5
JB		 4993 case invalid_vector_register_set:
4994 err_msg = _("mask, index, and destination registers must be distinct");
4995 break;
6c30d220
L		 4996 case unsupported_vector_index_register:
4997 err_msg = _("unsupported vector index register");
4998 break;
43234a1e
L		 4999 case unsupported_broadcast:
5000 err_msg = _("unsupported broadcast");
5001 break;
5002 case broadcast_not_on_src_operand:
5003 err_msg = _("broadcast not on source memory operand");
5004 break;
5005 case broadcast_needed:
5006 err_msg = _("broadcast is needed for operand of such type");
5007 break;
5008 case unsupported_masking:
5009 err_msg = _("unsupported masking");
5010 break;
5011 case mask_not_on_destination:
5012 err_msg = _("mask not on destination operand");
5013 break;
5014 case no_default_mask:
5015 err_msg = _("default mask isn't allowed");
5016 break;
5017 case unsupported_rc_sae:
5018 err_msg = _("unsupported static rounding/sae");
5019 break;
5020 case rc_sae_operand_not_last_imm:
5021 if (intel_syntax)
5022 err_msg = _("RC/SAE operand must precede immediate operands");
5023 else
5024 err_msg = _("RC/SAE operand must follow immediate operands");
5025 break;
5026 case invalid_register_operand:
5027 err_msg = _("invalid register operand");
5028 break;
a65babc9
L		 5029 }
5030 as_bad (_("%s for `%s'"), err_msg,
891edac4 5031 current_templates->start->name);
fa99fab2 5032 return NULL;
29b0f896 5033 }
252b5132 5034
29b0f896
AM		 5035 if (!quiet_warnings)
5036 {
5037 if (!intel_syntax
40fb9820
L		 5038 && (i.types[0].bitfield.jumpabsolute
5039 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5040 {
5041 as_warn (_("indirect %s without `*'"), t->name);
5042 }
5043
40fb9820
L		 5044 if (t->opcode_modifier.isprefix
5045 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5046 {
5047 /* Warn them that a data or address size prefix doesn't
5048 affect assembly of the next line of code. */
5049 as_warn (_("stand-alone `%s' prefix"), t->name);
5050 }
5051 }
5052
5053 /* Copy the template we found. */
5054 i.tm = *t;
539e75ad
L		 5055
5056 if (addr_prefix_disp != -1)
5057 i.tm.operand_types[addr_prefix_disp]
5058 = operand_types[addr_prefix_disp];
5059
29b0f896
AM		 5060 if (found_reverse_match)
5061 {
5062 /* If we found a reverse match we must alter the opcode
5063 direction bit. found_reverse_match holds bits to change
5064 (different for int & float insns). */
5065
5066 i.tm.base_opcode ^= found_reverse_match;
5067
539e75ad
L		 5068 i.tm.operand_types[0] = operand_types[1];
5069 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5070 }
5071
fa99fab2 5072 return t;
29b0f896
AM		 5073}
5074
5075static int
e3bb37b5 5076check_string (void)
29b0f896 5077{
40fb9820
L		 5078 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5079 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5080 {
5081 if (i.seg[0] != NULL && i.seg[0] != &es)
5082 {
a87af027 5083 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5084 i.tm.name,
a87af027
JB		 5085 mem_op + 1,
5086 register_prefix);
29b0f896
AM		 5087 return 0;
5088 }
5089 /* There's only ever one segment override allowed per instruction.
5090 This instruction possibly has a legal segment override on the
5091 second operand, so copy the segment to where non-string
5092 instructions store it, allowing common code. */
5093 i.seg[0] = i.seg[1];
5094 }
40fb9820 5095 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5096 {
5097 if (i.seg[1] != NULL && i.seg[1] != &es)
5098 {
a87af027 5099 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5100 i.tm.name,
a87af027
JB		 5101 mem_op + 2,
5102 register_prefix);
29b0f896
AM		 5103 return 0;
5104 }
5105 }
5106 return 1;
5107}
5108
5109static int
543613e9 5110process_suffix (void)
29b0f896
AM		 5111{
5112 /* If matched instruction specifies an explicit instruction mnemonic
5113 suffix, use it. */
40fb9820
L		 5114 if (i.tm.opcode_modifier.size16)
5115 i.suffix = WORD_MNEM_SUFFIX;
5116 else if (i.tm.opcode_modifier.size32)
5117 i.suffix = LONG_MNEM_SUFFIX;
5118 else if (i.tm.opcode_modifier.size64)
5119 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5120 else if (i.reg_operands)
5121 {
5122 /* If there's no instruction mnemonic suffix we try to invent one
5123 based on register operands. */
5124 if (!i.suffix)
5125 {
5126 /* We take i.suffix from the last register operand specified,
5127 Destination register type is more significant than source
381d071f
L		 5128 register type. crc32 in SSE4.2 prefers source register
5129 type. */
5130 if (i.tm.base_opcode == 0xf20f38f1)
5131 {
40fb9820
L		 5132 if (i.types[0].bitfield.reg16)
5133 i.suffix = WORD_MNEM_SUFFIX;
5134 else if (i.types[0].bitfield.reg32)
5135 i.suffix = LONG_MNEM_SUFFIX;
5136 else if (i.types[0].bitfield.reg64)
5137 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5138 }
9344ff29 5139 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5140 {
40fb9820 5141 if (i.types[0].bitfield.reg8)
20592a94
L		 5142 i.suffix = BYTE_MNEM_SUFFIX;
5143 }
381d071f
L		 5144
5145 if (!i.suffix)
5146 {
5147 int op;
5148
20592a94
L		 5149 if (i.tm.base_opcode == 0xf20f38f1
5150 || i.tm.base_opcode == 0xf20f38f0)
5151 {
5152 /* We have to know the operand size for crc32. */
5153 as_bad (_("ambiguous memory operand size for `%s`"),
5154 i.tm.name);
5155 return 0;
5156 }
5157
381d071f 5158 for (op = i.operands; --op >= 0;)
40fb9820 5159 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5160 {
40fb9820
L		 5161 if (i.types[op].bitfield.reg8)
5162 {
5163 i.suffix = BYTE_MNEM_SUFFIX;
5164 break;
5165 }
5166 else if (i.types[op].bitfield.reg16)
5167 {
5168 i.suffix = WORD_MNEM_SUFFIX;
5169 break;
5170 }
5171 else if (i.types[op].bitfield.reg32)
5172 {
5173 i.suffix = LONG_MNEM_SUFFIX;
5174 break;
5175 }
5176 else if (i.types[op].bitfield.reg64)
5177 {
5178 i.suffix = QWORD_MNEM_SUFFIX;
5179 break;
5180 }
381d071f
L		 5181 }
5182 }
29b0f896
AM		 5183 }
5184 else if (i.suffix == BYTE_MNEM_SUFFIX)
5185 {
2eb952a4
L		 5186 if (intel_syntax
5187 && i.tm.opcode_modifier.ignoresize
5188 && i.tm.opcode_modifier.no_bsuf)
5189 i.suffix = 0;
5190 else if (!check_byte_reg ())
29b0f896
AM		 5191 return 0;
5192 }
5193 else if (i.suffix == LONG_MNEM_SUFFIX)
5194 {
2eb952a4
L		 5195 if (intel_syntax
5196 && i.tm.opcode_modifier.ignoresize
5197 && i.tm.opcode_modifier.no_lsuf)
5198 i.suffix = 0;
5199 else if (!check_long_reg ())
29b0f896
AM		 5200 return 0;
5201 }
5202 else if (i.suffix == QWORD_MNEM_SUFFIX)
5203 {
955e1e6a
L		 5204 if (intel_syntax
5205 && i.tm.opcode_modifier.ignoresize
5206 && i.tm.opcode_modifier.no_qsuf)
5207 i.suffix = 0;
5208 else if (!check_qword_reg ())
29b0f896
AM		 5209 return 0;
5210 }
5211 else if (i.suffix == WORD_MNEM_SUFFIX)
5212 {
2eb952a4
L		 5213 if (intel_syntax
5214 && i.tm.opcode_modifier.ignoresize
5215 && i.tm.opcode_modifier.no_wsuf)
5216 i.suffix = 0;
5217 else if (!check_word_reg ())
29b0f896
AM		 5218 return 0;
5219 }
c0f3af97 5220 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5221 || i.suffix == YMMWORD_MNEM_SUFFIX
5222 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5223 {
43234a1e 5224 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5225 should check if it is a valid suffix. */
5226 }
40fb9820 5227 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5228 /* Do nothing if the instruction is going to ignore the prefix. */
5229 ;
5230 else
5231 abort ();
5232 }
40fb9820 5233 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5234 && !i.suffix
5235 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5236 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5237 {
5238 i.suffix = stackop_size;
5239 }
9306ca4a
JB		 5240 else if (intel_syntax
5241 && !i.suffix
40fb9820
L		 5242 && (i.tm.operand_types[0].bitfield.jumpabsolute
5243 || i.tm.opcode_modifier.jumpbyte
5244 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5245 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5246 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5247 {
5248 switch (flag_code)
5249 {
5250 case CODE_64BIT:
40fb9820 5251 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5252 {
5253 i.suffix = QWORD_MNEM_SUFFIX;
5254 break;
5255 }
5256 case CODE_32BIT:
40fb9820 5257 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5258 i.suffix = LONG_MNEM_SUFFIX;
5259 break;
5260 case CODE_16BIT:
40fb9820 5261 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5262 i.suffix = WORD_MNEM_SUFFIX;
5263 break;
5264 }
5265 }
252b5132 5266
9306ca4a 5267 if (!i.suffix)
29b0f896 5268 {
9306ca4a
JB		 5269 if (!intel_syntax)
5270 {
40fb9820 5271 if (i.tm.opcode_modifier.w)
9306ca4a 5272 {
4eed87de
AM		 5273 as_bad (_("no instruction mnemonic suffix given and "
5274 "no register operands; can't size instruction"));
9306ca4a
JB		 5275 return 0;
5276 }
5277 }
5278 else
5279 {
40fb9820 5280 unsigned int suffixes;
7ab9ffdd 5281
40fb9820
L		 5282 suffixes = !i.tm.opcode_modifier.no_bsuf;
5283 if (!i.tm.opcode_modifier.no_wsuf)
5284 suffixes |= 1 << 1;
5285 if (!i.tm.opcode_modifier.no_lsuf)
5286 suffixes |= 1 << 2;
fc4adea1 5287 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5288 suffixes |= 1 << 3;
5289 if (!i.tm.opcode_modifier.no_ssuf)
5290 suffixes |= 1 << 4;
5291 if (!i.tm.opcode_modifier.no_qsuf)
5292 suffixes |= 1 << 5;
5293
5294 /* There are more than suffix matches. */
5295 if (i.tm.opcode_modifier.w
9306ca4a 5296 || ((suffixes & (suffixes - 1))
40fb9820
L		 5297 && !i.tm.opcode_modifier.defaultsize
5298 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5299 {
5300 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5301 return 0;
5302 }
5303 }
29b0f896 5304 }
252b5132 5305
9306ca4a
JB		 5306 /* Change the opcode based on the operand size given by i.suffix;
5307 We don't need to change things for byte insns. */
5308
582d5edd
L		 5309 if (i.suffix
5310 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5311 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5312 && i.suffix != YMMWORD_MNEM_SUFFIX
5313 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5314 {
5315 /* It's not a byte, select word/dword operation. */
40fb9820 5316 if (i.tm.opcode_modifier.w)
29b0f896 5317 {
40fb9820 5318 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5319 i.tm.base_opcode |= 8;
5320 else
5321 i.tm.base_opcode |= 1;
5322 }
0f3f3d8b 5323
29b0f896
AM		 5324 /* Now select between word & dword operations via the operand
5325 size prefix, except for instructions that will ignore this
5326 prefix anyway. */
ca61edf2 5327 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5328 {
ca61edf2
L		 5329 /* The address size override prefix changes the size of the
5330 first operand. */
40fb9820
L		 5331 if ((flag_code == CODE_32BIT
5332 && i.op->regs[0].reg_type.bitfield.reg16)
5333 || (flag_code != CODE_32BIT
5334 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5335 if (!add_prefix (ADDR_PREFIX_OPCODE))
5336 return 0;
5337 }
5338 else if (i.suffix != QWORD_MNEM_SUFFIX
5339 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5340 && !i.tm.opcode_modifier.ignoresize
5341 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5342 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5343 || (flag_code == CODE_64BIT
40fb9820 5344 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5345 {
5346 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5347
40fb9820 5348 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5349 prefix = ADDR_PREFIX_OPCODE;
252b5132 5350
29b0f896
AM		 5351 if (!add_prefix (prefix))
5352 return 0;
24eab124 5353 }
252b5132 5354
29b0f896
AM		 5355 /* Set mode64 for an operand. */
5356 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5357 && flag_code == CODE_64BIT
40fb9820 5358 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5359 {
5360 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5361 need rex64. cmpxchg8b is also a special case. */
5362 if (! (i.operands == 2
5363 && i.tm.base_opcode == 0x90
5364 && i.tm.extension_opcode == None
0dfbf9d7
L		 5365 && operand_type_equal (&i.types [0], &acc64)
5366 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5367 && ! (i.operands == 1
5368 && i.tm.base_opcode == 0xfc7
5369 && i.tm.extension_opcode == 1
40fb9820
L		 5370 && !operand_type_check (i.types [0], reg)
5371 && operand_type_check (i.types [0], anymem)))
f6bee062 5372 i.rex |= REX_W;
46e883c5 5373 }
3e73aa7c 5374
29b0f896
AM		 5375 /* Size floating point instruction. */
5376 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5377 if (i.tm.opcode_modifier.floatmf)
543613e9 5378 i.tm.base_opcode ^= 4;
29b0f896 5379 }
7ecd2f8b 5380
29b0f896
AM		 5381 return 1;
5382}
3e73aa7c 5383
29b0f896 5384static int
543613e9 5385check_byte_reg (void)
29b0f896
AM		 5386{
5387 int op;
543613e9 5388
29b0f896
AM		 5389 for (op = i.operands; --op >= 0;)
5390 {
5391 /* If this is an eight bit register, it's OK. If it's the 16 or
5392 32 bit version of an eight bit register, we will just use the
5393 low portion, and that's OK too. */
40fb9820 5394 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5395 continue;
5396
5a819eb9
JB		 5397 /* I/O port address operands are OK too. */
5398 if (i.tm.operand_types[op].bitfield.inoutportreg)
5399 continue;
5400
9344ff29
L		 5401 /* crc32 doesn't generate this warning. */
5402 if (i.tm.base_opcode == 0xf20f38f0)
5403 continue;
5404
40fb9820
L		 5405 if ((i.types[op].bitfield.reg16
5406 || i.types[op].bitfield.reg32
5407 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5408 && i.op[op].regs->reg_num < 4
5409 /* Prohibit these changes in 64bit mode, since the lowering
5410 would be more complicated. */
5411 && flag_code != CODE_64BIT)
29b0f896 5412 {
29b0f896 5413#if REGISTER_WARNINGS
5a819eb9 5414 if (!quiet_warnings)
a540244d
L		 5415 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5416 register_prefix,
40fb9820 5417 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5418 ? REGNAM_AL - REGNAM_AX
5419 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5420 register_prefix,
29b0f896
AM		 5421 i.op[op].regs->reg_name,
5422 i.suffix);
5423#endif
5424 continue;
5425 }
5426 /* Any other register is bad. */
40fb9820
L		 5427 if (i.types[op].bitfield.reg16
5428 || i.types[op].bitfield.reg32
5429 || i.types[op].bitfield.reg64
5430 || i.types[op].bitfield.regmmx
5431 || i.types[op].bitfield.regxmm
c0f3af97 5432 || i.types[op].bitfield.regymm
43234a1e 5433 || i.types[op].bitfield.regzmm
40fb9820
L		 5434 || i.types[op].bitfield.sreg2
5435 || i.types[op].bitfield.sreg3
5436 || i.types[op].bitfield.control
5437 || i.types[op].bitfield.debug
5438 || i.types[op].bitfield.test
5439 || i.types[op].bitfield.floatreg
5440 || i.types[op].bitfield.floatacc)
29b0f896 5441 {
a540244d
L		 5442 as_bad (_("`%s%s' not allowed with `%s%c'"),
5443 register_prefix,
29b0f896
AM		 5444 i.op[op].regs->reg_name,
5445 i.tm.name,
5446 i.suffix);
5447 return 0;
5448 }
5449 }
5450 return 1;
5451}
5452
5453static int
e3bb37b5 5454check_long_reg (void)
29b0f896
AM		 5455{
5456 int op;
5457
5458 for (op = i.operands; --op >= 0;)
5459 /* Reject eight bit registers, except where the template requires
5460 them. (eg. movzb) */
40fb9820
L		 5461 if (i.types[op].bitfield.reg8
5462 && (i.tm.operand_types[op].bitfield.reg16
5463 || i.tm.operand_types[op].bitfield.reg32
5464 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5465 {
a540244d
L		 5466 as_bad (_("`%s%s' not allowed with `%s%c'"),
5467 register_prefix,
29b0f896
AM		 5468 i.op[op].regs->reg_name,
5469 i.tm.name,
5470 i.suffix);
5471 return 0;
5472 }
e4630f71 5473 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5474 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5475 && i.types[op].bitfield.reg16
5476 && (i.tm.operand_types[op].bitfield.reg32
5477 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5478 {
5479 /* Prohibit these changes in the 64bit mode, since the
5480 lowering is more complicated. */
5481 if (flag_code == CODE_64BIT)
252b5132 5482 {
2b5d6a91 5483 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5484 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5485 i.suffix);
5486 return 0;
252b5132 5487 }
29b0f896 5488#if REGISTER_WARNINGS
cecf1424
JB		 5489 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5490 register_prefix,
5491 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5492 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5493#endif
252b5132 5494 }
e4630f71 5495 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5496 else if (i.types[op].bitfield.reg64
5497 && (i.tm.operand_types[op].bitfield.reg32
5498 || i.tm.operand_types[op].bitfield.acc))
252b5132 5499 {
34828aad 5500 if (intel_syntax
ca61edf2 5501 && i.tm.opcode_modifier.toqword
40fb9820 5502 && !i.types[0].bitfield.regxmm)
34828aad 5503 {
ca61edf2 5504 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5505 i.suffix = QWORD_MNEM_SUFFIX;
5506 }
5507 else
5508 {
2b5d6a91 5509 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5510 register_prefix, i.op[op].regs->reg_name,
5511 i.suffix);
5512 return 0;
5513 }
29b0f896
AM		 5514 }
5515 return 1;
5516}
252b5132 5517
29b0f896 5518static int
e3bb37b5 5519check_qword_reg (void)
29b0f896
AM		 5520{
5521 int op;
252b5132 5522
29b0f896
AM		 5523 for (op = i.operands; --op >= 0; )
5524 /* Reject eight bit registers, except where the template requires
5525 them. (eg. movzb) */
40fb9820
L		 5526 if (i.types[op].bitfield.reg8
5527 && (i.tm.operand_types[op].bitfield.reg16
5528 || i.tm.operand_types[op].bitfield.reg32
5529 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5530 {
a540244d
L		 5531 as_bad (_("`%s%s' not allowed with `%s%c'"),
5532 register_prefix,
29b0f896
AM		 5533 i.op[op].regs->reg_name,
5534 i.tm.name,
5535 i.suffix);
5536 return 0;
5537 }
e4630f71 5538 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5539 else if ((i.types[op].bitfield.reg16
5540 || i.types[op].bitfield.reg32)
5541 && (i.tm.operand_types[op].bitfield.reg32
5542 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5543 {
5544 /* Prohibit these changes in the 64bit mode, since the
5545 lowering is more complicated. */
34828aad 5546 if (intel_syntax
ca61edf2 5547 && i.tm.opcode_modifier.todword
40fb9820 5548 && !i.types[0].bitfield.regxmm)
34828aad 5549 {
ca61edf2 5550 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5551 i.suffix = LONG_MNEM_SUFFIX;
5552 }
5553 else
5554 {
2b5d6a91 5555 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5556 register_prefix, i.op[op].regs->reg_name,
5557 i.suffix);
5558 return 0;
5559 }
252b5132 5560 }
29b0f896
AM		 5561 return 1;
5562}
252b5132 5563
29b0f896 5564static int
e3bb37b5 5565check_word_reg (void)
29b0f896
AM		 5566{
5567 int op;
5568 for (op = i.operands; --op >= 0;)
5569 /* Reject eight bit registers, except where the template requires
5570 them. (eg. movzb) */
40fb9820
L		 5571 if (i.types[op].bitfield.reg8
5572 && (i.tm.operand_types[op].bitfield.reg16
5573 || i.tm.operand_types[op].bitfield.reg32
5574 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5575 {
a540244d
L		 5576 as_bad (_("`%s%s' not allowed with `%s%c'"),
5577 register_prefix,
29b0f896
AM		 5578 i.op[op].regs->reg_name,
5579 i.tm.name,
5580 i.suffix);
5581 return 0;
5582 }
e4630f71 5583 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5584 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5585 && (i.types[op].bitfield.reg32
5586 || i.types[op].bitfield.reg64)
40fb9820
L		 5587 && (i.tm.operand_types[op].bitfield.reg16
5588 || i.tm.operand_types[op].bitfield.acc))
252b5132 5589 {
29b0f896
AM		 5590 /* Prohibit these changes in the 64bit mode, since the
5591 lowering is more complicated. */
5592 if (flag_code == CODE_64BIT)
252b5132 5593 {
2b5d6a91 5594 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5595 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5596 i.suffix);
5597 return 0;
252b5132 5598 }
29b0f896 5599#if REGISTER_WARNINGS
cecf1424
JB		 5600 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5601 register_prefix,
5602 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5603 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5604#endif
5605 }
5606 return 1;
5607}
252b5132 5608
29b0f896 5609static int
40fb9820 5610update_imm (unsigned int j)
29b0f896 5611{
bc0844ae 5612 i386_operand_type overlap = i.types[j];
40fb9820
L		 5613 if ((overlap.bitfield.imm8
5614 || overlap.bitfield.imm8s
5615 || overlap.bitfield.imm16
5616 || overlap.bitfield.imm32
5617 || overlap.bitfield.imm32s
5618 || overlap.bitfield.imm64)
0dfbf9d7
L		 5619 && !operand_type_equal (&overlap, &imm8)
5620 && !operand_type_equal (&overlap, &imm8s)
5621 && !operand_type_equal (&overlap, &imm16)
5622 && !operand_type_equal (&overlap, &imm32)
5623 && !operand_type_equal (&overlap, &imm32s)
5624 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5625 {
5626 if (i.suffix)
5627 {
40fb9820
L		 5628 i386_operand_type temp;
5629
0dfbf9d7 5630 operand_type_set (&temp, 0);
7ab9ffdd 5631 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5632 {
5633 temp.bitfield.imm8 = overlap.bitfield.imm8;
5634 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5635 }
5636 else if (i.suffix == WORD_MNEM_SUFFIX)
5637 temp.bitfield.imm16 = overlap.bitfield.imm16;
5638 else if (i.suffix == QWORD_MNEM_SUFFIX)
5639 {
5640 temp.bitfield.imm64 = overlap.bitfield.imm64;
5641 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5642 }
5643 else
5644 temp.bitfield.imm32 = overlap.bitfield.imm32;
5645 overlap = temp;
29b0f896 5646 }
0dfbf9d7
L		 5647 else if (operand_type_equal (&overlap, &imm16_32_32s)
5648 || operand_type_equal (&overlap, &imm16_32)
5649 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5650 {
40fb9820 5651 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5652 overlap = imm16;
40fb9820 5653 else
65da13b5 5654 overlap = imm32s;
29b0f896 5655 }
0dfbf9d7
L		 5656 if (!operand_type_equal (&overlap, &imm8)
5657 && !operand_type_equal (&overlap, &imm8s)
5658 && !operand_type_equal (&overlap, &imm16)
5659 && !operand_type_equal (&overlap, &imm32)
5660 && !operand_type_equal (&overlap, &imm32s)
5661 && !operand_type_equal (&overlap, &imm64))
29b0f896 5662 {
4eed87de
AM		 5663 as_bad (_("no instruction mnemonic suffix given; "
5664 "can't determine immediate size"));
29b0f896
AM		 5665 return 0;
5666 }
5667 }
40fb9820 5668 i.types[j] = overlap;
29b0f896 5669
40fb9820
L		 5670 return 1;
5671}
5672
5673static int
5674finalize_imm (void)
5675{
bc0844ae 5676 unsigned int j, n;
29b0f896 5677
bc0844ae
L		 5678 /* Update the first 2 immediate operands. */
5679 n = i.operands > 2 ? 2 : i.operands;
5680 if (n)
5681 {
5682 for (j = 0; j < n; j++)
5683 if (update_imm (j) == 0)
5684 return 0;
40fb9820 5685
bc0844ae
L		 5686 /* The 3rd operand can't be immediate operand. */
5687 gas_assert (operand_type_check (i.types[2], imm) == 0);
5688 }
29b0f896
AM		 5689
5690 return 1;
5691}
5692
c0f3af97
L		 5693static int
5694bad_implicit_operand (int xmm)
5695{
91d6fa6a
NC		 5696 const char *ireg = xmm ? "xmm0" : "ymm0";
5697
c0f3af97
L		 5698 if (intel_syntax)
5699 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5700 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5701 else
5702 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5703 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5704 return 0;
5705}
5706
29b0f896 5707static int
e3bb37b5 5708process_operands (void)
29b0f896
AM		 5709{
5710 /* Default segment register this instruction will use for memory
5711 accesses. 0 means unknown. This is only for optimizing out
5712 unnecessary segment overrides. */
5713 const seg_entry *default_seg = 0;
5714
2426c15f 5715 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5716 {
91d6fa6a
NC		 5717 unsigned int dupl = i.operands;
5718 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5719 unsigned int j;
5720
c0f3af97 5721 /* The destination must be an xmm register. */
9c2799c2 5722 gas_assert (i.reg_operands
91d6fa6a 5723 && MAX_OPERANDS > dupl
7ab9ffdd 5724 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5725
5726 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5727 {
c0f3af97 5728 /* The first operand is implicit and must be xmm0. */
9c2799c2 5729 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5730 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5731 return bad_implicit_operand (1);
5732
8cd7925b 5733 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5734 {
5735 /* Keep xmm0 for instructions with VEX prefix and 3
5736 sources. */
5737 goto duplicate;
5738 }
e2ec9d29 5739 else
c0f3af97
L		 5740 {
5741 /* We remove the first xmm0 and keep the number of
5742 operands unchanged, which in fact duplicates the
5743 destination. */
5744 for (j = 1; j < i.operands; j++)
5745 {
5746 i.op[j - 1] = i.op[j];
5747 i.types[j - 1] = i.types[j];
5748 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5749 }
5750 }
5751 }
5752 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5753 {
91d6fa6a 5754 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5755 && (i.tm.opcode_modifier.vexsources
5756 == VEX3SOURCES));
c0f3af97
L		 5757
5758 /* Add the implicit xmm0 for instructions with VEX prefix
5759 and 3 sources. */
5760 for (j = i.operands; j > 0; j--)
5761 {
5762 i.op[j] = i.op[j - 1];
5763 i.types[j] = i.types[j - 1];
5764 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5765 }
5766 i.op[0].regs
5767 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5768 i.types[0] = regxmm;
c0f3af97
L		 5769 i.tm.operand_types[0] = regxmm;
5770
5771 i.operands += 2;
5772 i.reg_operands += 2;
5773 i.tm.operands += 2;
5774
91d6fa6a 5775 dupl++;
c0f3af97 5776 dest++;
91d6fa6a
NC		 5777 i.op[dupl] = i.op[dest];
5778 i.types[dupl] = i.types[dest];
5779 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5780 }
c0f3af97
L		 5781 else
5782 {
5783duplicate:
5784 i.operands++;
5785 i.reg_operands++;
5786 i.tm.operands++;
5787
91d6fa6a
NC		 5788 i.op[dupl] = i.op[dest];
5789 i.types[dupl] = i.types[dest];
5790 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5791 }
5792
5793 if (i.tm.opcode_modifier.immext)
5794 process_immext ();
5795 }
5796 else if (i.tm.opcode_modifier.firstxmm0)
5797 {
5798 unsigned int j;
5799
43234a1e 5800 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5801 gas_assert (i.reg_operands
7ab9ffdd 5802 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5803 || operand_type_equal (&i.types[0], &regymm)
5804 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5805 if (register_number (i.op[0].regs) != 0)
c0f3af97 5806 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5807
5808 for (j = 1; j < i.operands; j++)
5809 {
5810 i.op[j - 1] = i.op[j];
5811 i.types[j - 1] = i.types[j];
5812
5813 /* We need to adjust fields in i.tm since they are used by
5814 build_modrm_byte. */
5815 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5816 }
5817
e2ec9d29
L		 5818 i.operands--;
5819 i.reg_operands--;
e2ec9d29
L		 5820 i.tm.operands--;
5821 }
5822 else if (i.tm.opcode_modifier.regkludge)
5823 {
5824 /* The imul $imm, %reg instruction is converted into
5825 imul $imm, %reg, %reg, and the clr %reg instruction
5826 is converted into xor %reg, %reg. */
5827
5828 unsigned int first_reg_op;
5829
5830 if (operand_type_check (i.types[0], reg))
5831 first_reg_op = 0;
5832 else
5833 first_reg_op = 1;
5834 /* Pretend we saw the extra register operand. */
9c2799c2 5835 gas_assert (i.reg_operands == 1
7ab9ffdd 5836 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5837 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5838 i.types[first_reg_op + 1] = i.types[first_reg_op];
5839 i.operands++;
5840 i.reg_operands++;
29b0f896
AM		 5841 }
5842
40fb9820 5843 if (i.tm.opcode_modifier.shortform)
29b0f896 5844 {
40fb9820
L		 5845 if (i.types[0].bitfield.sreg2
5846 || i.types[0].bitfield.sreg3)
29b0f896 5847 {
4eed87de
AM		 5848 if (i.tm.base_opcode == POP_SEG_SHORT
5849 && i.op[0].regs->reg_num == 1)
29b0f896 5850 {
a87af027 5851 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5852 return 0;
29b0f896 5853 }
4eed87de
AM		 5854 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5855 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5856 i.rex |= REX_B;
4eed87de
AM		 5857 }
5858 else
5859 {
7ab9ffdd 5860 /* The register or float register operand is in operand
85f10a01 5861 0 or 1. */
40fb9820 5862 unsigned int op;
7ab9ffdd
L		 5863
5864 if (i.types[0].bitfield.floatreg
5865 || operand_type_check (i.types[0], reg))
5866 op = 0;
5867 else
5868 op = 1;
4eed87de
AM		 5869 /* Register goes in low 3 bits of opcode. */
5870 i.tm.base_opcode |= i.op[op].regs->reg_num;
5871 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5872 i.rex |= REX_B;
40fb9820 5873 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5874 {
4eed87de
AM		 5875 /* Warn about some common errors, but press on regardless.
5876 The first case can be generated by gcc (<= 2.8.1). */
5877 if (i.operands == 2)
5878 {
5879 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5880 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5881 register_prefix, i.op[!intel_syntax].regs->reg_name,
5882 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5883 }
5884 else
5885 {
5886 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5887 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5888 register_prefix, i.op[0].regs->reg_name);
4eed87de 5889 }
29b0f896
AM		 5890 }
5891 }
5892 }
40fb9820 5893 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5894 {
5895 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5896 must be put into the modrm byte). Now, we make the modrm and
5897 index base bytes based on all the info we've collected. */
29b0f896
AM		 5898
5899 default_seg = build_modrm_byte ();
5900 }
8a2ed489 5901 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5902 {
5903 default_seg = &ds;
5904 }
40fb9820 5905 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5906 {
5907 /* For the string instructions that allow a segment override
5908 on one of their operands, the default segment is ds. */
5909 default_seg = &ds;
5910 }
5911
75178d9d
L		 5912 if (i.tm.base_opcode == 0x8d /* lea */
5913 && i.seg[0]
5914 && !quiet_warnings)
30123838 5915 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5916
5917 /* If a segment was explicitly specified, and the specified segment
5918 is not the default, use an opcode prefix to select it. If we
5919 never figured out what the default segment is, then default_seg
5920 will be zero at this point, and the specified segment prefix will
5921 always be used. */
29b0f896
AM		 5922 if ((i.seg[0]) && (i.seg[0] != default_seg))
5923 {
5924 if (!add_prefix (i.seg[0]->seg_prefix))
5925 return 0;
5926 }
5927 return 1;
5928}
5929
5930static const seg_entry *
e3bb37b5 5931build_modrm_byte (void)
29b0f896
AM		 5932{
5933 const seg_entry *default_seg = 0;
c0f3af97 5934 unsigned int source, dest;
8cd7925b 5935 int vex_3_sources;
c0f3af97
L		 5936
5937 /* The first operand of instructions with VEX prefix and 3 sources
5938 must be VEX_Imm4. */
8cd7925b 5939 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5940 if (vex_3_sources)
5941 {
91d6fa6a 5942 unsigned int nds, reg_slot;
4c2c6516 5943 expressionS *exp;
c0f3af97 5944
922d8de8 5945 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5946 && i.tm.opcode_modifier.immext)
5947 {
5948 dest = i.operands - 2;
5949 gas_assert (dest == 3);
5950 }
922d8de8 5951 else
a683cc34 5952 dest = i.operands - 1;
c0f3af97 5953 nds = dest - 1;
922d8de8 5954
a683cc34
SP		 5955 /* There are 2 kinds of instructions:
5956 1. 5 operands: 4 register operands or 3 register operands
5957 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5958 VexW0 or VexW1. The destination must be either XMM, YMM or
5959 ZMM register.
a683cc34
SP		 5960 2. 4 operands: 4 register operands or 3 register operands
5961 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5962 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5963 || (i.reg_operands == 3 && i.mem_operands == 1))
5964 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5965 && (i.tm.opcode_modifier.veximmext
5966 || (i.imm_operands == 1
5967 && i.types[0].bitfield.vec_imm4
5968 && (i.tm.opcode_modifier.vexw == VEXW0
5969 || i.tm.opcode_modifier.vexw == VEXW1)
5970 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5971 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5972 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5973
5974 if (i.imm_operands == 0)
5975 {
5976 /* When there is no immediate operand, generate an 8bit
5977 immediate operand to encode the first operand. */
5978 exp = &im_expressions[i.imm_operands++];
5979 i.op[i.operands].imms = exp;
5980 i.types[i.operands] = imm8;
5981 i.operands++;
5982 /* If VexW1 is set, the first operand is the source and
5983 the second operand is encoded in the immediate operand. */
5984 if (i.tm.opcode_modifier.vexw == VEXW1)
5985 {
5986 source = 0;
5987 reg_slot = 1;
5988 }
5989 else
5990 {
5991 source = 1;
5992 reg_slot = 0;
5993 }
5994
5995 /* FMA swaps REG and NDS. */
5996 if (i.tm.cpu_flags.bitfield.cpufma)
5997 {
5998 unsigned int tmp;
5999 tmp = reg_slot;
6000 reg_slot = nds;
6001 nds = tmp;
6002 }
6003
24981e7b
L		 6004 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6005 &regxmm)
a683cc34 6006 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6007 &regymm)
6008 || operand_type_equal (&i.tm.operand_types[reg_slot],
6009 &regzmm));
a683cc34 6010 exp->X_op = O_constant;
4c692bc7 6011 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6012 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6013 }
922d8de8 6014 else
a683cc34
SP		 6015 {
6016 unsigned int imm_slot;
6017
6018 if (i.tm.opcode_modifier.vexw == VEXW0)
6019 {
6020 /* If VexW0 is set, the third operand is the source and
6021 the second operand is encoded in the immediate
6022 operand. */
6023 source = 2;
6024 reg_slot = 1;
6025 }
6026 else
6027 {
6028 /* VexW1 is set, the second operand is the source and
6029 the third operand is encoded in the immediate
6030 operand. */
6031 source = 1;
6032 reg_slot = 2;
6033 }
6034
6035 if (i.tm.opcode_modifier.immext)
6036 {
6037 /* When ImmExt is set, the immdiate byte is the last
6038 operand. */
6039 imm_slot = i.operands - 1;
6040 source--;
6041 reg_slot--;
6042 }
6043 else
6044 {
6045 imm_slot = 0;
6046
6047 /* Turn on Imm8 so that output_imm will generate it. */
6048 i.types[imm_slot].bitfield.imm8 = 1;
6049 }
6050
24981e7b
L		 6051 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6052 &regxmm)
6053 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6054 &regymm)
6055 || operand_type_equal (&i.tm.operand_types[reg_slot],
6056 &regzmm));
a683cc34 6057 i.op[imm_slot].imms->X_add_number
4c692bc7 6058 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6059 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6060 }
6061
6062 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6063 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6064 &regymm)
6065 || operand_type_equal (&i.tm.operand_types[nds],
6066 &regzmm));
dae39acc 6067 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6068 }
6069 else
6070 source = dest = 0;
29b0f896
AM		 6071
6072 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6073 implicit registers do not count. If there are 3 register
6074 operands, it must be a instruction with VexNDS. For a
6075 instruction with VexNDD, the destination register is encoded
6076 in VEX prefix. If there are 4 register operands, it must be
6077 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6078 if (i.mem_operands == 0
6079 && ((i.reg_operands == 2
2426c15f 6080 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6081 || (i.reg_operands == 3
2426c15f 6082 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6083 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6084 {
cab737b9
L		 6085 switch (i.operands)
6086 {
6087 case 2:
6088 source = 0;
6089 break;
6090 case 3:
c81128dc
L		 6091 /* When there are 3 operands, one of them may be immediate,
6092 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6093 the first operand must be shift count register (cl) or it
6094 is an instruction with VexNDS. */
9c2799c2 6095 gas_assert (i.imm_operands == 1
7ab9ffdd 6096 || (i.imm_operands == 0
2426c15f 6097 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6098 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6099 if (operand_type_check (i.types[0], imm)
6100 || i.types[0].bitfield.shiftcount)
6101 source = 1;
6102 else
6103 source = 0;
cab737b9
L		 6104 break;
6105 case 4:
368d64cc
L		 6106 /* When there are 4 operands, the first two must be 8bit
6107 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6108 one.
6109
6110 For instructions with VexNDS, if the first operand
6111 an imm8, the source operand is the 2nd one. If the last
6112 operand is imm8, the source operand is the first one. */
9c2799c2 6113 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6114 && i.types[0].bitfield.imm8
6115 && i.types[1].bitfield.imm8)
2426c15f 6116 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6117 && i.imm_operands == 1
6118 && (i.types[0].bitfield.imm8
43234a1e
L		 6119 || i.types[i.operands - 1].bitfield.imm8
6120 || i.rounding)));
9f2670f2
L		 6121 if (i.imm_operands == 2)
6122 source = 2;
6123 else
c0f3af97
L		 6124 {
6125 if (i.types[0].bitfield.imm8)
6126 source = 1;
6127 else
6128 source = 0;
6129 }
c0f3af97
L		 6130 break;
6131 case 5:
43234a1e
L		 6132 if (i.tm.opcode_modifier.evex)
6133 {
6134 /* For EVEX instructions, when there are 5 operands, the
6135 first one must be immediate operand. If the second one
6136 is immediate operand, the source operand is the 3th
6137 one. If the last one is immediate operand, the source
6138 operand is the 2nd one. */
6139 gas_assert (i.imm_operands == 2
6140 && i.tm.opcode_modifier.sae
6141 && operand_type_check (i.types[0], imm));
6142 if (operand_type_check (i.types[1], imm))
6143 source = 2;
6144 else if (operand_type_check (i.types[4], imm))
6145 source = 1;
6146 else
6147 abort ();
6148 }
cab737b9
L		 6149 break;
6150 default:
6151 abort ();
6152 }
6153
c0f3af97
L		 6154 if (!vex_3_sources)
6155 {
6156 dest = source + 1;
6157
43234a1e
L		 6158 /* RC/SAE operand could be between DEST and SRC. That happens
6159 when one operand is GPR and the other one is XMM/YMM/ZMM
6160 register. */
6161 if (i.rounding && i.rounding->operand == (int) dest)
6162 dest++;
6163
2426c15f 6164 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6165 {
43234a1e
L		 6166 /* For instructions with VexNDS, the register-only source
6167 operand must be 32/64bit integer, XMM, YMM or ZMM
6168 register. It is encoded in VEX prefix. We need to
6169 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6170
6171 i386_operand_type op;
6172 unsigned int vvvv;
6173
6174 /* Check register-only source operand when two source
6175 operands are swapped. */
6176 if (!i.tm.operand_types[source].bitfield.baseindex
6177 && i.tm.operand_types[dest].bitfield.baseindex)
6178 {
6179 vvvv = source;
6180 source = dest;
6181 }
6182 else
6183 vvvv = dest;
6184
6185 op = i.tm.operand_types[vvvv];
fa99fab2 6186 op.bitfield.regmem = 0;
c0f3af97 6187 if ((dest + 1) >= i.operands
ac4eb736
AM		 6188 || (!op.bitfield.reg32
6189 && op.bitfield.reg64
f12dc422 6190 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6191 && !operand_type_equal (&op, &regymm)
6192 && !operand_type_equal (&op, &regzmm)
6193 && !operand_type_equal (&op, &regmask)))
c0f3af97 6194 abort ();
f12dc422 6195 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6196 dest++;
6197 }
6198 }
29b0f896
AM		 6199
6200 i.rm.mode = 3;
6201 /* One of the register operands will be encoded in the i.tm.reg
6202 field, the other in the combined i.tm.mode and i.tm.regmem
6203 fields. If no form of this instruction supports a memory
6204 destination operand, then we assume the source operand may
6205 sometimes be a memory operand and so we need to store the
6206 destination in the i.rm.reg field. */
40fb9820
L		 6207 if (!i.tm.operand_types[dest].bitfield.regmem
6208 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6209 {
6210 i.rm.reg = i.op[dest].regs->reg_num;
6211 i.rm.regmem = i.op[source].regs->reg_num;
6212 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6213 i.rex |= REX_R;
43234a1e
L		 6214 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6215 i.vrex |= REX_R;
29b0f896 6216 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6217 i.rex |= REX_B;
43234a1e
L		 6218 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6219 i.vrex |= REX_B;
29b0f896
AM		 6220 }
6221 else
6222 {
6223 i.rm.reg = i.op[source].regs->reg_num;
6224 i.rm.regmem = i.op[dest].regs->reg_num;
6225 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6226 i.rex |= REX_B;
43234a1e
L		 6227 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6228 i.vrex |= REX_B;
29b0f896 6229 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6230 i.rex |= REX_R;
43234a1e
L		 6231 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6232 i.vrex |= REX_R;
29b0f896 6233 }
161a04f6 6234 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6235 {
40fb9820
L		 6236 if (!i.types[0].bitfield.control
6237 && !i.types[1].bitfield.control)
c4a530c5 6238 abort ();
161a04f6 6239 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6240 add_prefix (LOCK_PREFIX_OPCODE);
6241 }
29b0f896
AM		 6242 }
6243 else
6244 { /* If it's not 2 reg operands... */
c0f3af97
L		 6245 unsigned int mem;
6246
29b0f896
AM		 6247 if (i.mem_operands)
6248 {
6249 unsigned int fake_zero_displacement = 0;
99018f42 6250 unsigned int op;
4eed87de 6251
7ab9ffdd
L		 6252 for (op = 0; op < i.operands; op++)
6253 if (operand_type_check (i.types[op], anymem))
6254 break;
7ab9ffdd 6255 gas_assert (op < i.operands);
29b0f896 6256
6c30d220
L		 6257 if (i.tm.opcode_modifier.vecsib)
6258 {
6259 if (i.index_reg->reg_num == RegEiz
6260 || i.index_reg->reg_num == RegRiz)
6261 abort ();
6262
6263 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6264 if (!i.base_reg)
6265 {
6266 i.sib.base = NO_BASE_REGISTER;
6267 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6268 /* No Vec_Disp8 if there is no base. */
6269 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6270 i.types[op].bitfield.disp8 = 0;
6271 i.types[op].bitfield.disp16 = 0;
6272 i.types[op].bitfield.disp64 = 0;
6273 if (flag_code != CODE_64BIT)
6274 {
6275 /* Must be 32 bit */
6276 i.types[op].bitfield.disp32 = 1;
6277 i.types[op].bitfield.disp32s = 0;
6278 }
6279 else
6280 {
6281 i.types[op].bitfield.disp32 = 0;
6282 i.types[op].bitfield.disp32s = 1;
6283 }
6284 }
6285 i.sib.index = i.index_reg->reg_num;
6286 if ((i.index_reg->reg_flags & RegRex) != 0)
6287 i.rex |= REX_X;
43234a1e
L		 6288 if ((i.index_reg->reg_flags & RegVRex) != 0)
6289 i.vrex |= REX_X;
6c30d220
L		 6290 }
6291
29b0f896
AM		 6292 default_seg = &ds;
6293
6294 if (i.base_reg == 0)
6295 {
6296 i.rm.mode = 0;
6297 if (!i.disp_operands)
6c30d220
L		 6298 {
6299 fake_zero_displacement = 1;
6300 /* Instructions with VSIB byte need 32bit displacement
6301 if there is no base register. */
6302 if (i.tm.opcode_modifier.vecsib)
6303 i.types[op].bitfield.disp32 = 1;
6304 }
29b0f896
AM		 6305 if (i.index_reg == 0)
6306 {
6c30d220 6307 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6308 /* Operand is just <disp> */
20f0a1fc 6309 if (flag_code == CODE_64BIT)
29b0f896
AM		 6310 {
6311 /* 64bit mode overwrites the 32bit absolute
6312 addressing by RIP relative addressing and
6313 absolute addressing is encoded by one of the
6314 redundant SIB forms. */
6315 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6316 i.sib.base = NO_BASE_REGISTER;
6317 i.sib.index = NO_INDEX_REGISTER;
fc225355 6318 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6319 ? disp32s : disp32);
20f0a1fc 6320 }
fc225355
L		 6321 else if ((flag_code == CODE_16BIT)
6322 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6323 {
6324 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6325 i.types[op] = disp16;
20f0a1fc
NC		 6326 }
6327 else
6328 {
6329 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6330 i.types[op] = disp32;
29b0f896
AM		 6331 }
6332 }
6c30d220 6333 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6334 {
6c30d220 6335 /* !i.base_reg && i.index_reg */
db51cc60
L		 6336 if (i.index_reg->reg_num == RegEiz
6337 || i.index_reg->reg_num == RegRiz)
6338 i.sib.index = NO_INDEX_REGISTER;
6339 else
6340 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6341 i.sib.base = NO_BASE_REGISTER;
6342 i.sib.scale = i.log2_scale_factor;
6343 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6344 /* No Vec_Disp8 if there is no base. */
6345 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6346 i.types[op].bitfield.disp8 = 0;
6347 i.types[op].bitfield.disp16 = 0;
6348 i.types[op].bitfield.disp64 = 0;
29b0f896 6349 if (flag_code != CODE_64BIT)
40fb9820
L		 6350 {
6351 /* Must be 32 bit */
6352 i.types[op].bitfield.disp32 = 1;
6353 i.types[op].bitfield.disp32s = 0;
6354 }
29b0f896 6355 else
40fb9820
L		 6356 {
6357 i.types[op].bitfield.disp32 = 0;
6358 i.types[op].bitfield.disp32s = 1;
6359 }
29b0f896 6360 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6361 i.rex |= REX_X;
29b0f896
AM		 6362 }
6363 }
6364 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6365 else if (i.base_reg->reg_num == RegRip ||
6366 i.base_reg->reg_num == RegEip)
29b0f896 6367 {
6c30d220 6368 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6369 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6370 i.types[op].bitfield.disp8 = 0;
6371 i.types[op].bitfield.disp16 = 0;
6372 i.types[op].bitfield.disp32 = 0;
6373 i.types[op].bitfield.disp32s = 1;
6374 i.types[op].bitfield.disp64 = 0;
43234a1e 6375 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6376 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6377 if (! i.disp_operands)
6378 fake_zero_displacement = 1;
29b0f896 6379 }
40fb9820 6380 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6381 {
6c30d220 6382 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6383 switch (i.base_reg->reg_num)
6384 {
6385 case 3: /* (%bx) */
6386 if (i.index_reg == 0)
6387 i.rm.regmem = 7;
6388 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6389 i.rm.regmem = i.index_reg->reg_num - 6;
6390 break;
6391 case 5: /* (%bp) */
6392 default_seg = &ss;
6393 if (i.index_reg == 0)
6394 {
6395 i.rm.regmem = 6;
40fb9820 6396 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6397 {
6398 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6399 if (i.tm.operand_types[op].bitfield.vec_disp8)
6400 i.types[op].bitfield.vec_disp8 = 1;
6401 else
6402 i.types[op].bitfield.disp8 = 1;
252b5132 6403 fake_zero_displacement = 1;
29b0f896
AM		 6404 }
6405 }
6406 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6407 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6408 break;
6409 default: /* (%si) -> 4 or (%di) -> 5 */
6410 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6411 }
6412 i.rm.mode = mode_from_disp_size (i.types[op]);
6413 }
6414 else /* i.base_reg and 32/64 bit mode */
6415 {
6416 if (flag_code == CODE_64BIT
40fb9820
L		 6417 && operand_type_check (i.types[op], disp))
6418 {
6419 i386_operand_type temp;
0dfbf9d7 6420 operand_type_set (&temp, 0);
40fb9820 6421 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6422 temp.bitfield.vec_disp8
6423 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6424 i.types[op] = temp;
6425 if (i.prefix[ADDR_PREFIX] == 0)
6426 i.types[op].bitfield.disp32s = 1;
6427 else
6428 i.types[op].bitfield.disp32 = 1;
6429 }
20f0a1fc 6430
6c30d220
L		 6431 if (!i.tm.opcode_modifier.vecsib)
6432 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6433 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6434 i.rex |= REX_B;
29b0f896
AM		 6435 i.sib.base = i.base_reg->reg_num;
6436 /* x86-64 ignores REX prefix bit here to avoid decoder
6437 complications. */
848930b2
JB		 6438 if (!(i.base_reg->reg_flags & RegRex)
6439 && (i.base_reg->reg_num == EBP_REG_NUM
6440 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6441 default_seg = &ss;
848930b2 6442 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6443 {
848930b2 6444 fake_zero_displacement = 1;
43234a1e
L		 6445 if (i.tm.operand_types [op].bitfield.vec_disp8)
6446 i.types[op].bitfield.vec_disp8 = 1;
6447 else
6448 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6449 }
6450 i.sib.scale = i.log2_scale_factor;
6451 if (i.index_reg == 0)
6452 {
6c30d220 6453 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6454 /* <disp>(%esp) becomes two byte modrm with no index
6455 register. We've already stored the code for esp
6456 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6457 Any base register besides %esp will not use the
6458 extra modrm byte. */
6459 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6460 }
6c30d220 6461 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6462 {
db51cc60
L		 6463 if (i.index_reg->reg_num == RegEiz
6464 || i.index_reg->reg_num == RegRiz)
6465 i.sib.index = NO_INDEX_REGISTER;
6466 else
6467 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6468 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6469 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6470 i.rex |= REX_X;
29b0f896 6471 }
67a4f2b7
AO		 6472
6473 if (i.disp_operands
6474 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6475 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6476 i.rm.mode = 0;
6477 else
a501d77e
L		 6478 {
6479 if (!fake_zero_displacement
6480 && !i.disp_operands
6481 && i.disp_encoding)
6482 {
6483 fake_zero_displacement = 1;
6484 if (i.disp_encoding == disp_encoding_8bit)
6485 i.types[op].bitfield.disp8 = 1;
6486 else
6487 i.types[op].bitfield.disp32 = 1;
6488 }
6489 i.rm.mode = mode_from_disp_size (i.types[op]);
6490 }
29b0f896 6491 }
252b5132 6492
29b0f896
AM		 6493 if (fake_zero_displacement)
6494 {
6495 /* Fakes a zero displacement assuming that i.types[op]
6496 holds the correct displacement size. */
6497 expressionS *exp;
6498
9c2799c2 6499 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6500 exp = &disp_expressions[i.disp_operands++];
6501 i.op[op].disps = exp;
6502 exp->X_op = O_constant;
6503 exp->X_add_number = 0;
6504 exp->X_add_symbol = (symbolS *) 0;
6505 exp->X_op_symbol = (symbolS *) 0;
6506 }
c0f3af97
L		 6507
6508 mem = op;
29b0f896 6509 }
c0f3af97
L		 6510 else
6511 mem = ~0;
252b5132 6512
8c43a48b 6513 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6514 {
6515 if (operand_type_check (i.types[0], imm))
6516 i.vex.register_specifier = NULL;
6517 else
6518 {
6519 /* VEX.vvvv encodes one of the sources when the first
6520 operand is not an immediate. */
1ef99a7b 6521 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6522 i.vex.register_specifier = i.op[0].regs;
6523 else
6524 i.vex.register_specifier = i.op[1].regs;
6525 }
6526
6527 /* Destination is a XMM register encoded in the ModRM.reg
6528 and VEX.R bit. */
6529 i.rm.reg = i.op[2].regs->reg_num;
6530 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6531 i.rex |= REX_R;
6532
6533 /* ModRM.rm and VEX.B encodes the other source. */
6534 if (!i.mem_operands)
6535 {
6536 i.rm.mode = 3;
6537
1ef99a7b 6538 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6539 i.rm.regmem = i.op[1].regs->reg_num;
6540 else
6541 i.rm.regmem = i.op[0].regs->reg_num;
6542
6543 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6544 i.rex |= REX_B;
6545 }
6546 }
2426c15f 6547 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6548 {
6549 i.vex.register_specifier = i.op[2].regs;
6550 if (!i.mem_operands)
6551 {
6552 i.rm.mode = 3;
6553 i.rm.regmem = i.op[1].regs->reg_num;
6554 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6555 i.rex |= REX_B;
6556 }
6557 }
29b0f896
AM		 6558 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6559 (if any) based on i.tm.extension_opcode. Again, we must be
6560 careful to make sure that segment/control/debug/test/MMX
6561 registers are coded into the i.rm.reg field. */
f88c9eb0 6562 else if (i.reg_operands)
29b0f896 6563 {
99018f42 6564 unsigned int op;
7ab9ffdd
L		 6565 unsigned int vex_reg = ~0;
6566
6567 for (op = 0; op < i.operands; op++)
6568 if (i.types[op].bitfield.reg8
6569 || i.types[op].bitfield.reg16
6570 || i.types[op].bitfield.reg32
6571 || i.types[op].bitfield.reg64
6572 || i.types[op].bitfield.regmmx
6573 || i.types[op].bitfield.regxmm
6574 || i.types[op].bitfield.regymm
7e8b059b 6575 || i.types[op].bitfield.regbnd
43234a1e
L		 6576 || i.types[op].bitfield.regzmm
6577 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6578 || i.types[op].bitfield.sreg2
6579 || i.types[op].bitfield.sreg3
6580 || i.types[op].bitfield.control
6581 || i.types[op].bitfield.debug
6582 || i.types[op].bitfield.test)
6583 break;
c0209578 6584
7ab9ffdd
L		 6585 if (vex_3_sources)
6586 op = dest;
2426c15f 6587 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6588 {
6589 /* For instructions with VexNDS, the register-only
6590 source operand is encoded in VEX prefix. */
6591 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6592
7ab9ffdd 6593 if (op > mem)
c0f3af97 6594 {
7ab9ffdd
L		 6595 vex_reg = op++;
6596 gas_assert (op < i.operands);
c0f3af97
L		 6597 }
6598 else
c0f3af97 6599 {
f12dc422
L		 6600 /* Check register-only source operand when two source
6601 operands are swapped. */
6602 if (!i.tm.operand_types[op].bitfield.baseindex
6603 && i.tm.operand_types[op + 1].bitfield.baseindex)
6604 {
6605 vex_reg = op;
6606 op += 2;
6607 gas_assert (mem == (vex_reg + 1)
6608 && op < i.operands);
6609 }
6610 else
6611 {
6612 vex_reg = op + 1;
6613 gas_assert (vex_reg < i.operands);
6614 }
c0f3af97 6615 }
7ab9ffdd 6616 }
2426c15f 6617 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6618 {
f12dc422 6619 /* For instructions with VexNDD, the register destination
7ab9ffdd 6620 is encoded in VEX prefix. */
f12dc422
L		 6621 if (i.mem_operands == 0)
6622 {
6623 /* There is no memory operand. */
6624 gas_assert ((op + 2) == i.operands);
6625 vex_reg = op + 1;
6626 }
6627 else
8d63c93e 6628 {
f12dc422
L		 6629 /* There are only 2 operands. */
6630 gas_assert (op < 2 && i.operands == 2);
6631 vex_reg = 1;
6632 }
7ab9ffdd
L		 6633 }
6634 else
6635 gas_assert (op < i.operands);
99018f42 6636
7ab9ffdd
L		 6637 if (vex_reg != (unsigned int) ~0)
6638 {
f12dc422 6639 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6640
f12dc422
L		 6641 if (type->bitfield.reg32 != 1
6642 && type->bitfield.reg64 != 1
6643 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6644 && !operand_type_equal (type, &regymm)
6645 && !operand_type_equal (type, &regzmm)
6646 && !operand_type_equal (type, &regmask))
7ab9ffdd 6647 abort ();
f88c9eb0 6648
7ab9ffdd
L		 6649 i.vex.register_specifier = i.op[vex_reg].regs;
6650 }
6651
1b9f0c97
L		 6652 /* Don't set OP operand twice. */
6653 if (vex_reg != op)
7ab9ffdd 6654 {
1b9f0c97
L		 6655 /* If there is an extension opcode to put here, the
6656 register number must be put into the regmem field. */
6657 if (i.tm.extension_opcode != None)
6658 {
6659 i.rm.regmem = i.op[op].regs->reg_num;
6660 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6661 i.rex |= REX_B;
43234a1e
L		 6662 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6663 i.vrex |= REX_B;
1b9f0c97
L		 6664 }
6665 else
6666 {
6667 i.rm.reg = i.op[op].regs->reg_num;
6668 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6669 i.rex |= REX_R;
43234a1e
L		 6670 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6671 i.vrex |= REX_R;
1b9f0c97 6672 }
7ab9ffdd 6673 }
252b5132 6674
29b0f896
AM		 6675 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6676 must set it to 3 to indicate this is a register operand
6677 in the regmem field. */
6678 if (!i.mem_operands)
6679 i.rm.mode = 3;
6680 }
252b5132 6681
29b0f896 6682 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6683 if (i.tm.extension_opcode != None)
29b0f896
AM		 6684 i.rm.reg = i.tm.extension_opcode;
6685 }
6686 return default_seg;
6687}
252b5132 6688
29b0f896 6689static void
e3bb37b5 6690output_branch (void)
29b0f896
AM		 6691{
6692 char *p;
f8a5c266 6693 int size;
29b0f896
AM		 6694 int code16;
6695 int prefix;
6696 relax_substateT subtype;
6697 symbolS *sym;
6698 offsetT off;
6699
f8a5c266 6700 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6701 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6702
6703 prefix = 0;
6704 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6705 {
29b0f896
AM		 6706 prefix = 1;
6707 i.prefixes -= 1;
6708 code16 ^= CODE16;
252b5132 6709 }
29b0f896
AM		 6710 /* Pentium4 branch hints. */
6711 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6712 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6713 {
29b0f896
AM		 6714 prefix++;
6715 i.prefixes--;
6716 }
6717 if (i.prefix[REX_PREFIX] != 0)
6718 {
6719 prefix++;
6720 i.prefixes--;
2f66722d
AM		 6721 }
6722
7e8b059b
L		 6723 /* BND prefixed jump. */
6724 if (i.prefix[BND_PREFIX] != 0)
6725 {
6726 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6727 i.prefixes -= 1;
6728 }
6729
29b0f896
AM		 6730 if (i.prefixes != 0 && !intel_syntax)
6731 as_warn (_("skipping prefixes on this instruction"));
6732
6733 /* It's always a symbol; End frag & setup for relax.
6734 Make sure there is enough room in this frag for the largest
6735 instruction we may generate in md_convert_frag. This is 2
6736 bytes for the opcode and room for the prefix and largest
6737 displacement. */
6738 frag_grow (prefix + 2 + 4);
6739 /* Prefix and 1 opcode byte go in fr_fix. */
6740 p = frag_more (prefix + 1);
6741 if (i.prefix[DATA_PREFIX] != 0)
6742 *p++ = DATA_PREFIX_OPCODE;
6743 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6744 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6745 *p++ = i.prefix[SEG_PREFIX];
6746 if (i.prefix[REX_PREFIX] != 0)
6747 *p++ = i.prefix[REX_PREFIX];
6748 *p = i.tm.base_opcode;
6749
6750 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6751 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6752 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6753 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6754 else
f8a5c266 6755 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6756 subtype |= code16;
3e73aa7c 6757
29b0f896
AM		 6758 sym = i.op[0].disps->X_add_symbol;
6759 off = i.op[0].disps->X_add_number;
3e73aa7c 6760
29b0f896
AM		 6761 if (i.op[0].disps->X_op != O_constant
6762 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6763 {
29b0f896
AM		 6764 /* Handle complex expressions. */
6765 sym = make_expr_symbol (i.op[0].disps);
6766 off = 0;
6767 }
3e73aa7c 6768
29b0f896
AM		 6769 /* 1 possible extra opcode + 4 byte displacement go in var part.
6770 Pass reloc in fr_var. */
d258b828 6771 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6772}
3e73aa7c 6773
29b0f896 6774static void
e3bb37b5 6775output_jump (void)
29b0f896
AM		 6776{
6777 char *p;
6778 int size;
3e02c1cc 6779 fixS *fixP;
29b0f896 6780
40fb9820 6781 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6782 {
6783 /* This is a loop or jecxz type instruction. */
6784 size = 1;
6785 if (i.prefix[ADDR_PREFIX] != 0)
6786 {
6787 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6788 i.prefixes -= 1;
6789 }
6790 /* Pentium4 branch hints. */
6791 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6792 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6793 {
6794 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6795 i.prefixes--;
3e73aa7c
JH		 6796 }
6797 }
29b0f896
AM		 6798 else
6799 {
6800 int code16;
3e73aa7c 6801
29b0f896
AM		 6802 code16 = 0;
6803 if (flag_code == CODE_16BIT)
6804 code16 = CODE16;
3e73aa7c 6805
29b0f896
AM		 6806 if (i.prefix[DATA_PREFIX] != 0)
6807 {
6808 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6809 i.prefixes -= 1;
6810 code16 ^= CODE16;
6811 }
252b5132 6812
29b0f896
AM		 6813 size = 4;
6814 if (code16)
6815 size = 2;
6816 }
9fcc94b6 6817
29b0f896
AM		 6818 if (i.prefix[REX_PREFIX] != 0)
6819 {
6820 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6821 i.prefixes -= 1;
6822 }
252b5132 6823
7e8b059b
L		 6824 /* BND prefixed jump. */
6825 if (i.prefix[BND_PREFIX] != 0)
6826 {
6827 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6828 i.prefixes -= 1;
6829 }
6830
29b0f896
AM		 6831 if (i.prefixes != 0 && !intel_syntax)
6832 as_warn (_("skipping prefixes on this instruction"));
e0890092 6833
42164a71
L		 6834 p = frag_more (i.tm.opcode_length + size);
6835 switch (i.tm.opcode_length)
6836 {
6837 case 2:
6838 *p++ = i.tm.base_opcode >> 8;
6839 case 1:
6840 *p++ = i.tm.base_opcode;
6841 break;
6842 default:
6843 abort ();
6844 }
e0890092 6845
3e02c1cc 6846 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6847 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6848
6849 /* All jumps handled here are signed, but don't use a signed limit
6850 check for 32 and 16 bit jumps as we want to allow wrap around at
6851 4G and 64k respectively. */
6852 if (size == 1)
6853 fixP->fx_signed = 1;
29b0f896 6854}
e0890092 6855
29b0f896 6856static void
e3bb37b5 6857output_interseg_jump (void)
29b0f896
AM		 6858{
6859 char *p;
6860 int size;
6861 int prefix;
6862 int code16;
252b5132 6863
29b0f896
AM		 6864 code16 = 0;
6865 if (flag_code == CODE_16BIT)
6866 code16 = CODE16;
a217f122 6867
29b0f896
AM		 6868 prefix = 0;
6869 if (i.prefix[DATA_PREFIX] != 0)
6870 {
6871 prefix = 1;
6872 i.prefixes -= 1;
6873 code16 ^= CODE16;
6874 }
6875 if (i.prefix[REX_PREFIX] != 0)
6876 {
6877 prefix++;
6878 i.prefixes -= 1;
6879 }
252b5132 6880
29b0f896
AM		 6881 size = 4;
6882 if (code16)
6883 size = 2;
252b5132 6884
29b0f896
AM		 6885 if (i.prefixes != 0 && !intel_syntax)
6886 as_warn (_("skipping prefixes on this instruction"));
252b5132 6887
29b0f896
AM		 6888 /* 1 opcode; 2 segment; offset */
6889 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6890
29b0f896
AM		 6891 if (i.prefix[DATA_PREFIX] != 0)
6892 *p++ = DATA_PREFIX_OPCODE;
252b5132 6893
29b0f896
AM		 6894 if (i.prefix[REX_PREFIX] != 0)
6895 *p++ = i.prefix[REX_PREFIX];
252b5132 6896
29b0f896
AM		 6897 *p++ = i.tm.base_opcode;
6898 if (i.op[1].imms->X_op == O_constant)
6899 {
6900 offsetT n = i.op[1].imms->X_add_number;
252b5132 6901
29b0f896
AM		 6902 if (size == 2
6903 && !fits_in_unsigned_word (n)
6904 && !fits_in_signed_word (n))
6905 {
6906 as_bad (_("16-bit jump out of range"));
6907 return;
6908 }
6909 md_number_to_chars (p, n, size);
6910 }
6911 else
6912 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6913 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6914 if (i.op[0].imms->X_op != O_constant)
6915 as_bad (_("can't handle non absolute segment in `%s'"),
6916 i.tm.name);
6917 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6918}
a217f122 6919
29b0f896 6920static void
e3bb37b5 6921output_insn (void)
29b0f896 6922{
2bbd9c25
JJ		 6923 fragS *insn_start_frag;
6924 offsetT insn_start_off;
6925
29b0f896
AM		 6926 /* Tie dwarf2 debug info to the address at the start of the insn.
6927 We can't do this after the insn has been output as the current
6928 frag may have been closed off. eg. by frag_var. */
6929 dwarf2_emit_insn (0);
6930
2bbd9c25
JJ		 6931 insn_start_frag = frag_now;
6932 insn_start_off = frag_now_fix ();
6933
29b0f896 6934 /* Output jumps. */
40fb9820 6935 if (i.tm.opcode_modifier.jump)
29b0f896 6936 output_branch ();
40fb9820
L		 6937 else if (i.tm.opcode_modifier.jumpbyte
6938 || i.tm.opcode_modifier.jumpdword)
29b0f896 6939 output_jump ();
40fb9820 6940 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6941 output_interseg_jump ();
6942 else
6943 {
6944 /* Output normal instructions here. */
6945 char *p;
6946 unsigned char *q;
47465058 6947 unsigned int j;
331d2d0d 6948 unsigned int prefix;
4dffcebc 6949
d022bddd
IT		 6950 /* Some processors fail on LOCK prefix. This options makes
6951 assembler ignore LOCK prefix and serves as a workaround. */
6952 if (omit_lock_prefix)
6953 {
6954 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6955 return;
6956 i.prefix[LOCK_PREFIX] = 0;
6957 }
6958
43234a1e
L		 6959 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6960 don't need the explicit prefix. */
6961 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6962 {
c0f3af97 6963 switch (i.tm.opcode_length)
bc4bd9ab 6964 {
c0f3af97
L		 6965 case 3:
6966 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6967 {
c0f3af97
L		 6968 prefix = (i.tm.base_opcode >> 24) & 0xff;
6969 goto check_prefix;
6970 }
6971 break;
6972 case 2:
6973 if ((i.tm.base_opcode & 0xff0000) != 0)
6974 {
6975 prefix = (i.tm.base_opcode >> 16) & 0xff;
6976 if (i.tm.cpu_flags.bitfield.cpupadlock)
6977 {
4dffcebc 6978check_prefix:
c0f3af97 6979 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6980 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6981 != REPE_PREFIX_OPCODE))
6982 add_prefix (prefix);
6983 }
6984 else
4dffcebc
L		 6985 add_prefix (prefix);
6986 }
c0f3af97
L		 6987 break;
6988 case 1:
6989 break;
6990 default:
6991 abort ();
bc4bd9ab 6992 }
c0f3af97 6993
6d19a37a 6994#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 6995 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6996 R_X86_64_GOTTPOFF relocation so that linker can safely
6997 perform IE->LE optimization. */
6998 if (x86_elf_abi == X86_64_X32_ABI
6999 && i.operands == 2
7000 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7001 && i.prefix[REX_PREFIX] == 0)
7002 add_prefix (REX_OPCODE);
6d19a37a 7003#endif
cf61b747 7004
c0f3af97
L		 7005 /* The prefix bytes. */
7006 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7007 if (*q)
7008 FRAG_APPEND_1_CHAR (*q);
0f10071e 7009 }
ae5c1c7b 7010 else
c0f3af97
L		 7011 {
7012 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7013 if (*q)
7014 switch (j)
7015 {
7016 case REX_PREFIX:
7017 /* REX byte is encoded in VEX prefix. */
7018 break;
7019 case SEG_PREFIX:
7020 case ADDR_PREFIX:
7021 FRAG_APPEND_1_CHAR (*q);
7022 break;
7023 default:
7024 /* There should be no other prefixes for instructions
7025 with VEX prefix. */
7026 abort ();
7027 }
7028
43234a1e
L		 7029 /* For EVEX instructions i.vrex should become 0 after
7030 build_evex_prefix. For VEX instructions upper 16 registers
7031 aren't available, so VREX should be 0. */
7032 if (i.vrex)
7033 abort ();
c0f3af97
L		 7034 /* Now the VEX prefix. */
7035 p = frag_more (i.vex.length);
7036 for (j = 0; j < i.vex.length; j++)
7037 p[j] = i.vex.bytes[j];
7038 }
252b5132 7039
29b0f896 7040 /* Now the opcode; be careful about word order here! */
4dffcebc 7041 if (i.tm.opcode_length == 1)
29b0f896
AM		 7042 {
7043 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7044 }
7045 else
7046 {
4dffcebc 7047 switch (i.tm.opcode_length)
331d2d0d 7048 {
43234a1e
L		 7049 case 4:
7050 p = frag_more (4);
7051 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7052 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7053 break;
4dffcebc 7054 case 3:
331d2d0d
L		 7055 p = frag_more (3);
7056 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7057 break;
7058 case 2:
7059 p = frag_more (2);
7060 break;
7061 default:
7062 abort ();
7063 break;
331d2d0d 7064 }
0f10071e 7065
29b0f896
AM		 7066 /* Put out high byte first: can't use md_number_to_chars! */
7067 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7068 *p = i.tm.base_opcode & 0xff;
7069 }
3e73aa7c 7070
29b0f896 7071 /* Now the modrm byte and sib byte (if present). */
40fb9820 7072 if (i.tm.opcode_modifier.modrm)
29b0f896 7073 {
4a3523fa
L		 7074 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7075 | i.rm.reg << 3
7076 | i.rm.mode << 6));
29b0f896
AM		 7077 /* If i.rm.regmem == ESP (4)
7078 && i.rm.mode != (Register mode)
7079 && not 16 bit
7080 ==> need second modrm byte. */
7081 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7082 && i.rm.mode != 3
40fb9820 7083 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7084 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7085 | i.sib.index << 3
7086 | i.sib.scale << 6));
29b0f896 7087 }
3e73aa7c 7088
29b0f896 7089 if (i.disp_operands)
2bbd9c25 7090 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7091
29b0f896 7092 if (i.imm_operands)
2bbd9c25 7093 output_imm (insn_start_frag, insn_start_off);
29b0f896 7094 }
252b5132 7095
29b0f896
AM		 7096#ifdef DEBUG386
7097 if (flag_debug)
7098 {
7b81dfbb 7099 pi ("" /*line*/, &i);
29b0f896
AM		 7100 }
7101#endif /* DEBUG386 */
7102}
252b5132 7103
e205caa7
L		 7104/* Return the size of the displacement operand N. */
7105
7106static int
7107disp_size (unsigned int n)
7108{
7109 int size = 4;
43234a1e
L		 7110
7111 /* Vec_Disp8 has to be 8bit. */
7112 if (i.types[n].bitfield.vec_disp8)
7113 size = 1;
7114 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7115 size = 8;
7116 else if (i.types[n].bitfield.disp8)
7117 size = 1;
7118 else if (i.types[n].bitfield.disp16)
7119 size = 2;
e205caa7
L		 7120 return size;
7121}
7122
7123/* Return the size of the immediate operand N. */
7124
7125static int
7126imm_size (unsigned int n)
7127{
7128 int size = 4;
40fb9820
L		 7129 if (i.types[n].bitfield.imm64)
7130 size = 8;
7131 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7132 size = 1;
7133 else if (i.types[n].bitfield.imm16)
7134 size = 2;
e205caa7
L		 7135 return size;
7136}
7137
29b0f896 7138static void
64e74474 7139output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7140{
7141 char *p;
7142 unsigned int n;
252b5132 7143
29b0f896
AM		 7144 for (n = 0; n < i.operands; n++)
7145 {
43234a1e
L		 7146 if (i.types[n].bitfield.vec_disp8
7147 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7148 {
7149 if (i.op[n].disps->X_op == O_constant)
7150 {
e205caa7 7151 int size = disp_size (n);
43234a1e 7152 offsetT val = i.op[n].disps->X_add_number;
252b5132 7153
43234a1e
L		 7154 if (i.types[n].bitfield.vec_disp8)
7155 val >>= i.memshift;
7156 val = offset_in_range (val, size);
29b0f896
AM		 7157 p = frag_more (size);
7158 md_number_to_chars (p, val, size);
7159 }
7160 else
7161 {
f86103b7 7162 enum bfd_reloc_code_real reloc_type;
e205caa7 7163 int size = disp_size (n);
40fb9820 7164 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7165 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7166
e205caa7 7167 /* We can't have 8 bit displacement here. */
9c2799c2 7168 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7169
29b0f896
AM		 7170 /* The PC relative address is computed relative
7171 to the instruction boundary, so in case immediate
7172 fields follows, we need to adjust the value. */
7173 if (pcrel && i.imm_operands)
7174 {
29b0f896 7175 unsigned int n1;
e205caa7 7176 int sz = 0;
252b5132 7177
29b0f896 7178 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7179 if (operand_type_check (i.types[n1], imm))
252b5132 7180 {
e205caa7
L		 7181 /* Only one immediate is allowed for PC
7182 relative address. */
9c2799c2 7183 gas_assert (sz == 0);
e205caa7
L		 7184 sz = imm_size (n1);
7185 i.op[n].disps->X_add_number -= sz;
252b5132 7186 }
29b0f896 7187 /* We should find the immediate. */
9c2799c2 7188 gas_assert (sz != 0);
29b0f896 7189 }
520dc8e8 7190
29b0f896 7191 p = frag_more (size);
d258b828 7192 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7193 if (GOT_symbol
2bbd9c25 7194 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7195 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7196 || reloc_type == BFD_RELOC_X86_64_32S
7197 || (reloc_type == BFD_RELOC_64
7198 && object_64bit))
d6ab8113
JB		 7199 && (i.op[n].disps->X_op == O_symbol
7200 || (i.op[n].disps->X_op == O_add
7201 && ((symbol_get_value_expression
7202 (i.op[n].disps->X_op_symbol)->X_op)
7203 == O_subtract))))
7204 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7205 {
7206 offsetT add;
7207
7208 if (insn_start_frag == frag_now)
7209 add = (p - frag_now->fr_literal) - insn_start_off;
7210 else
7211 {
7212 fragS *fr;
7213
7214 add = insn_start_frag->fr_fix - insn_start_off;
7215 for (fr = insn_start_frag->fr_next;
7216 fr && fr != frag_now; fr = fr->fr_next)
7217 add += fr->fr_fix;
7218 add += p - frag_now->fr_literal;
7219 }
7220
4fa24527 7221 if (!object_64bit)
7b81dfbb
AJ		 7222 {
7223 reloc_type = BFD_RELOC_386_GOTPC;
7224 i.op[n].imms->X_add_number += add;
7225 }
7226 else if (reloc_type == BFD_RELOC_64)
7227 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7228 else
7b81dfbb
AJ		 7229 /* Don't do the adjustment for x86-64, as there
7230 the pcrel addressing is relative to the _next_
7231 insn, and that is taken care of in other code. */
d6ab8113 7232 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7233 }
062cd5e7 7234 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7235 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7236 }
7237 }
7238 }
7239}
252b5132 7240
29b0f896 7241static void
64e74474 7242output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7243{
7244 char *p;
7245 unsigned int n;
252b5132 7246
29b0f896
AM		 7247 for (n = 0; n < i.operands; n++)
7248 {
43234a1e
L		 7249 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7250 if (i.rounding && (int) n == i.rounding->operand)
7251 continue;
7252
40fb9820 7253 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7254 {
7255 if (i.op[n].imms->X_op == O_constant)
7256 {
e205caa7 7257 int size = imm_size (n);
29b0f896 7258 offsetT val;
b4cac588 7259
29b0f896
AM		 7260 val = offset_in_range (i.op[n].imms->X_add_number,
7261 size);
7262 p = frag_more (size);
7263 md_number_to_chars (p, val, size);
7264 }
7265 else
7266 {
7267 /* Not absolute_section.
7268 Need a 32-bit fixup (don't support 8bit
7269 non-absolute imms). Try to support other
7270 sizes ... */
f86103b7 7271 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7272 int size = imm_size (n);
7273 int sign;
29b0f896 7274
40fb9820 7275 if (i.types[n].bitfield.imm32s
a7d61044 7276 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7277 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7278 sign = 1;
e205caa7
L		 7279 else
7280 sign = 0;
520dc8e8 7281
29b0f896 7282 p = frag_more (size);
d258b828 7283 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7284
2bbd9c25
JJ		 7285 /* This is tough to explain. We end up with this one if we
7286 * have operands that look like
7287 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7288 * obtain the absolute address of the GOT, and it is strongly
7289 * preferable from a performance point of view to avoid using
7290 * a runtime relocation for this. The actual sequence of
7291 * instructions often look something like:
7292 *
7293 * call .L66
7294 * .L66:
7295 * popl %ebx
7296 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7297 *
7298 * The call and pop essentially return the absolute address
7299 * of the label .L66 and store it in %ebx. The linker itself
7300 * will ultimately change the first operand of the addl so
7301 * that %ebx points to the GOT, but to keep things simple, the
7302 * .o file must have this operand set so that it generates not
7303 * the absolute address of .L66, but the absolute address of
7304 * itself. This allows the linker itself simply treat a GOTPC
7305 * relocation as asking for a pcrel offset to the GOT to be
7306 * added in, and the addend of the relocation is stored in the
7307 * operand field for the instruction itself.
7308 *
7309 * Our job here is to fix the operand so that it would add
7310 * the correct offset so that %ebx would point to itself. The
7311 * thing that is tricky is that .-.L66 will point to the
7312 * beginning of the instruction, so we need to further modify
7313 * the operand so that it will point to itself. There are
7314 * other cases where you have something like:
7315 *
7316 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7317 *
7318 * and here no correction would be required. Internally in
7319 * the assembler we treat operands of this form as not being
7320 * pcrel since the '.' is explicitly mentioned, and I wonder
7321 * whether it would simplify matters to do it this way. Who
7322 * knows. In earlier versions of the PIC patches, the
7323 * pcrel_adjust field was used to store the correction, but
7324 * since the expression is not pcrel, I felt it would be
7325 * confusing to do it this way. */
7326
d6ab8113 7327 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7328 || reloc_type == BFD_RELOC_X86_64_32S
7329 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7330 && GOT_symbol
7331 && GOT_symbol == i.op[n].imms->X_add_symbol
7332 && (i.op[n].imms->X_op == O_symbol
7333 || (i.op[n].imms->X_op == O_add
7334 && ((symbol_get_value_expression
7335 (i.op[n].imms->X_op_symbol)->X_op)
7336 == O_subtract))))
7337 {
2bbd9c25
JJ		 7338 offsetT add;
7339
7340 if (insn_start_frag == frag_now)
7341 add = (p - frag_now->fr_literal) - insn_start_off;
7342 else
7343 {
7344 fragS *fr;
7345
7346 add = insn_start_frag->fr_fix - insn_start_off;
7347 for (fr = insn_start_frag->fr_next;
7348 fr && fr != frag_now; fr = fr->fr_next)
7349 add += fr->fr_fix;
7350 add += p - frag_now->fr_literal;
7351 }
7352
4fa24527 7353 if (!object_64bit)
d6ab8113 7354 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7355 else if (size == 4)
d6ab8113 7356 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7357 else if (size == 8)
7358 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7359 i.op[n].imms->X_add_number += add;
29b0f896 7360 }
29b0f896
AM		 7361 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7362 i.op[n].imms, 0, reloc_type);
7363 }
7364 }
7365 }
252b5132
RH		 7366}
7367\f
d182319b
JB		 7368/* x86_cons_fix_new is called via the expression parsing code when a
7369 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7370static int cons_sign = -1;
7371
7372void
e3bb37b5 7373x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7374 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7375{
d258b828 7376 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7377
7378#ifdef TE_PE
7379 if (exp->X_op == O_secrel)
7380 {
7381 exp->X_op = O_symbol;
7382 r = BFD_RELOC_32_SECREL;
7383 }
7384#endif
7385
7386 fix_new_exp (frag, off, len, exp, 0, r);
7387}
7388
357d1bd8
L		 7389/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7390 purpose of the `.dc.a' internal pseudo-op. */
7391
7392int
7393x86_address_bytes (void)
7394{
7395 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7396 return 4;
7397 return stdoutput->arch_info->bits_per_address / 8;
7398}
7399
d382c579
TG		 7400#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7401 || defined (LEX_AT)
d258b828 7402# define lex_got(reloc, adjust, types) NULL
718ddfc0 7403#else
f3c180ae
AM		 7404/* Parse operands of the form
7405 <symbol>@GOTOFF+<nnn>
7406 and similar .plt or .got references.
7407
7408 If we find one, set up the correct relocation in RELOC and copy the
7409 input string, minus the `@GOTOFF' into a malloc'd buffer for
7410 parsing by the calling routine. Return this buffer, and if ADJUST
7411 is non-null set it to the length of the string we removed from the
7412 input line. Otherwise return NULL. */
7413static char *
91d6fa6a 7414lex_got (enum bfd_reloc_code_real *rel,
64e74474 7415 int *adjust,
d258b828 7416 i386_operand_type *types)
f3c180ae 7417{
7b81dfbb
AJ		 7418 /* Some of the relocations depend on the size of what field is to
7419 be relocated. But in our callers i386_immediate and i386_displacement
7420 we don't yet know the operand size (this will be set by insn
7421 matching). Hence we record the word32 relocation here,
7422 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7423 static const struct {
7424 const char *str;
cff8d58a 7425 int len;
4fa24527 7426 const enum bfd_reloc_code_real rel[2];
40fb9820 7427 const i386_operand_type types64;
f3c180ae 7428 } gotrel[] = {
8ce3d284 7429#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7430 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7431 BFD_RELOC_SIZE32 },
7432 OPERAND_TYPE_IMM32_64 },
8ce3d284 7433#endif
cff8d58a
L		 7434 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7435 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7436 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7437 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7438 BFD_RELOC_X86_64_PLT32 },
40fb9820 7439 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7440 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7441 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7442 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7443 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7444 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7445 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7446 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7447 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7448 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7449 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7450 BFD_RELOC_X86_64_TLSGD },
40fb9820 7451 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7452 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7453 _dummy_first_bfd_reloc_code_real },
40fb9820 7454 OPERAND_TYPE_NONE },
cff8d58a
L		 7455 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7456 BFD_RELOC_X86_64_TLSLD },
40fb9820 7457 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7458 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7459 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7460 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7461 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7462 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7463 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7464 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7465 _dummy_first_bfd_reloc_code_real },
40fb9820 7466 OPERAND_TYPE_NONE },
cff8d58a
L		 7467 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7468 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7469 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7470 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7471 _dummy_first_bfd_reloc_code_real },
40fb9820 7472 OPERAND_TYPE_NONE },
cff8d58a
L		 7473 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7474 _dummy_first_bfd_reloc_code_real },
40fb9820 7475 OPERAND_TYPE_NONE },
cff8d58a
L		 7476 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7477 BFD_RELOC_X86_64_GOT32 },
40fb9820 7478 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7479 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7480 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7481 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7482 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7483 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7484 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7485 };
7486 char *cp;
7487 unsigned int j;
7488
d382c579 7489#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7490 if (!IS_ELF)
7491 return NULL;
d382c579 7492#endif
718ddfc0 7493
f3c180ae 7494 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7495 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7496 return NULL;
7497
47465058 7498 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7499 {
cff8d58a 7500 int len = gotrel[j].len;
28f81592 7501 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7502 {
4fa24527 7503 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7504 {
28f81592
AM		 7505 int first, second;
7506 char *tmpbuf, *past_reloc;
f3c180ae 7507
91d6fa6a 7508 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7509
3956db08
JB		 7510 if (types)
7511 {
7512 if (flag_code != CODE_64BIT)
40fb9820
L		 7513 {
7514 types->bitfield.imm32 = 1;
7515 types->bitfield.disp32 = 1;
7516 }
3956db08
JB		 7517 else
7518 *types = gotrel[j].types64;
7519 }
7520
8fd4256d 7521 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7522 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7523
28f81592 7524 /* The length of the first part of our input line. */
f3c180ae 7525 first = cp - input_line_pointer;
28f81592
AM		 7526
7527 /* The second part goes from after the reloc token until
67c11a9b 7528 (and including) an end_of_line char or comma. */
28f81592 7529 past_reloc = cp + 1 + len;
67c11a9b
AM		 7530 cp = past_reloc;
7531 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7532 ++cp;
7533 second = cp + 1 - past_reloc;
28f81592
AM		 7534
7535 /* Allocate and copy string. The trailing NUL shouldn't
7536 be necessary, but be safe. */
1e9cc1c2 7537 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7538 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7539 if (second != 0 && *past_reloc != ' ')
7540 /* Replace the relocation token with ' ', so that
7541 errors like foo@GOTOFF1 will be detected. */
7542 tmpbuf[first++] = ' ';
af89796a
L		 7543 else
7544 /* Increment length by 1 if the relocation token is
7545 removed. */
7546 len++;
7547 if (adjust)
7548 *adjust = len;
0787a12d
AM		 7549 memcpy (tmpbuf + first, past_reloc, second);
7550 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7551 return tmpbuf;
7552 }
7553
4fa24527
JB		 7554 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7555 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7556 return NULL;
7557 }
7558 }
7559
7560 /* Might be a symbol version string. Don't as_bad here. */
7561 return NULL;
7562}
4e4f7c87 7563#endif
f3c180ae 7564
a988325c
NC		 7565#ifdef TE_PE
7566#ifdef lex_got
7567#undef lex_got
7568#endif
7569/* Parse operands of the form
7570 <symbol>@SECREL32+<nnn>
7571
7572 If we find one, set up the correct relocation in RELOC and copy the
7573 input string, minus the `@SECREL32' into a malloc'd buffer for
7574 parsing by the calling routine. Return this buffer, and if ADJUST
7575 is non-null set it to the length of the string we removed from the
34bca508
L		 7576 input line. Otherwise return NULL.
7577
a988325c
NC		 7578 This function is copied from the ELF version above adjusted for PE targets. */
7579
7580static char *
7581lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7582 int *adjust ATTRIBUTE_UNUSED,
d258b828 7583 i386_operand_type *types)
a988325c
NC		 7584{
7585 static const struct
7586 {
7587 const char *str;
7588 int len;
7589 const enum bfd_reloc_code_real rel[2];
7590 const i386_operand_type types64;
7591 }
7592 gotrel[] =
7593 {
7594 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7595 BFD_RELOC_32_SECREL },
7596 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7597 };
7598
7599 char *cp;
7600 unsigned j;
7601
7602 for (cp = input_line_pointer; *cp != '@'; cp++)
7603 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7604 return NULL;
7605
7606 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7607 {
7608 int len = gotrel[j].len;
7609
7610 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7611 {
7612 if (gotrel[j].rel[object_64bit] != 0)
7613 {
7614 int first, second;
7615 char *tmpbuf, *past_reloc;
7616
7617 *rel = gotrel[j].rel[object_64bit];
7618 if (adjust)
7619 *adjust = len;
7620
7621 if (types)
7622 {
7623 if (flag_code != CODE_64BIT)
7624 {
7625 types->bitfield.imm32 = 1;
7626 types->bitfield.disp32 = 1;
7627 }
7628 else
7629 *types = gotrel[j].types64;
7630 }
7631
7632 /* The length of the first part of our input line. */
7633 first = cp - input_line_pointer;
7634
7635 /* The second part goes from after the reloc token until
7636 (and including) an end_of_line char or comma. */
7637 past_reloc = cp + 1 + len;
7638 cp = past_reloc;
7639 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7640 ++cp;
7641 second = cp + 1 - past_reloc;
7642
7643 /* Allocate and copy string. The trailing NUL shouldn't
7644 be necessary, but be safe. */
7645 tmpbuf = (char *) xmalloc (first + second + 2);
7646 memcpy (tmpbuf, input_line_pointer, first);
7647 if (second != 0 && *past_reloc != ' ')
7648 /* Replace the relocation token with ' ', so that
7649 errors like foo@SECLREL321 will be detected. */
7650 tmpbuf[first++] = ' ';
7651 memcpy (tmpbuf + first, past_reloc, second);
7652 tmpbuf[first + second] = '\0';
7653 return tmpbuf;
7654 }
7655
7656 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7657 gotrel[j].str, 1 << (5 + object_64bit));
7658 return NULL;
7659 }
7660 }
7661
7662 /* Might be a symbol version string. Don't as_bad here. */
7663 return NULL;
7664}
7665
7666#endif /* TE_PE */
7667
62ebcb5c 7668bfd_reloc_code_real_type
e3bb37b5 7669x86_cons (expressionS *exp, int size)
f3c180ae 7670{
62ebcb5c
AM		 7671 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7672
ee86248c
JB		 7673 intel_syntax = -intel_syntax;
7674
3c7b9c2c 7675 exp->X_md = 0;
4fa24527 7676 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7677 {
7678 /* Handle @GOTOFF and the like in an expression. */
7679 char *save;
7680 char *gotfree_input_line;
4a57f2cf 7681 int adjust = 0;
f3c180ae
AM		 7682
7683 save = input_line_pointer;
d258b828 7684 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7685 if (gotfree_input_line)
7686 input_line_pointer = gotfree_input_line;
7687
7688 expression (exp);
7689
7690 if (gotfree_input_line)
7691 {
7692 /* expression () has merrily parsed up to the end of line,
7693 or a comma - in the wrong buffer. Transfer how far
7694 input_line_pointer has moved to the right buffer. */
7695 input_line_pointer = (save
7696 + (input_line_pointer - gotfree_input_line)
7697 + adjust);
7698 free (gotfree_input_line);
3992d3b7
AM		 7699 if (exp->X_op == O_constant
7700 || exp->X_op == O_absent
7701 || exp->X_op == O_illegal
0398aac5 7702 || exp->X_op == O_register
3992d3b7
AM		 7703 || exp->X_op == O_big)
7704 {
7705 char c = *input_line_pointer;
7706 *input_line_pointer = 0;
7707 as_bad (_("missing or invalid expression `%s'"), save);
7708 *input_line_pointer = c;
7709 }
f3c180ae
AM		 7710 }
7711 }
7712 else
7713 expression (exp);
ee86248c
JB		 7714
7715 intel_syntax = -intel_syntax;
7716
7717 if (intel_syntax)
7718 i386_intel_simplify (exp);
62ebcb5c
AM		 7719
7720 return got_reloc;
f3c180ae 7721}
f3c180ae 7722
9f32dd5b
L		 7723static void
7724signed_cons (int size)
6482c264 7725{
d182319b
JB		 7726 if (flag_code == CODE_64BIT)
7727 cons_sign = 1;
7728 cons (size);
7729 cons_sign = -1;
6482c264
NC		 7730}
7731
d182319b 7732#ifdef TE_PE
6482c264 7733static void
7016a5d5 7734pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7735{
7736 expressionS exp;
7737
7738 do
7739 {
7740 expression (&exp);
7741 if (exp.X_op == O_symbol)
7742 exp.X_op = O_secrel;
7743
7744 emit_expr (&exp, 4);
7745 }
7746 while (*input_line_pointer++ == ',');
7747
7748 input_line_pointer--;
7749 demand_empty_rest_of_line ();
7750}
6482c264
NC		 7751#endif
7752
43234a1e
L		 7753/* Handle Vector operations. */
7754
7755static char *
7756check_VecOperations (char *op_string, char *op_end)
7757{
7758 const reg_entry *mask;
7759 const char *saved;
7760 char *end_op;
7761
7762 while (*op_string
7763 && (op_end == NULL || op_string < op_end))
7764 {
7765 saved = op_string;
7766 if (*op_string == '{')
7767 {
7768 op_string++;
7769
7770 /* Check broadcasts. */
7771 if (strncmp (op_string, "1to", 3) == 0)
7772 {
7773 int bcst_type;
7774
7775 if (i.broadcast)
7776 goto duplicated_vec_op;
7777
7778 op_string += 3;
7779 if (*op_string == '8')
7780 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7781 else if (*op_string == '4')
7782 bcst_type = BROADCAST_1TO4;
7783 else if (*op_string == '2')
7784 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7785 else if (*op_string == '1'
7786 && *(op_string+1) == '6')
7787 {
7788 bcst_type = BROADCAST_1TO16;
7789 op_string++;
7790 }
7791 else
7792 {
7793 as_bad (_("Unsupported broadcast: `%s'"), saved);
7794 return NULL;
7795 }
7796 op_string++;
7797
7798 broadcast_op.type = bcst_type;
7799 broadcast_op.operand = this_operand;
7800 i.broadcast = &broadcast_op;
7801 }
7802 /* Check masking operation. */
7803 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7804 {
7805 /* k0 can't be used for write mask. */
7806 if (mask->reg_num == 0)
7807 {
7808 as_bad (_("`%s' can't be used for write mask"),
7809 op_string);
7810 return NULL;
7811 }
7812
7813 if (!i.mask)
7814 {
7815 mask_op.mask = mask;
7816 mask_op.zeroing = 0;
7817 mask_op.operand = this_operand;
7818 i.mask = &mask_op;
7819 }
7820 else
7821 {
7822 if (i.mask->mask)
7823 goto duplicated_vec_op;
7824
7825 i.mask->mask = mask;
7826
7827 /* Only "{z}" is allowed here. No need to check
7828 zeroing mask explicitly. */
7829 if (i.mask->operand != this_operand)
7830 {
7831 as_bad (_("invalid write mask `%s'"), saved);
7832 return NULL;
7833 }
7834 }
7835
7836 op_string = end_op;
7837 }
7838 /* Check zeroing-flag for masking operation. */
7839 else if (*op_string == 'z')
7840 {
7841 if (!i.mask)
7842 {
7843 mask_op.mask = NULL;
7844 mask_op.zeroing = 1;
7845 mask_op.operand = this_operand;
7846 i.mask = &mask_op;
7847 }
7848 else
7849 {
7850 if (i.mask->zeroing)
7851 {
7852 duplicated_vec_op:
7853 as_bad (_("duplicated `%s'"), saved);
7854 return NULL;
7855 }
7856
7857 i.mask->zeroing = 1;
7858
7859 /* Only "{%k}" is allowed here. No need to check mask
7860 register explicitly. */
7861 if (i.mask->operand != this_operand)
7862 {
7863 as_bad (_("invalid zeroing-masking `%s'"),
7864 saved);
7865 return NULL;
7866 }
7867 }
7868
7869 op_string++;
7870 }
7871 else
7872 goto unknown_vec_op;
7873
7874 if (*op_string != '}')
7875 {
7876 as_bad (_("missing `}' in `%s'"), saved);
7877 return NULL;
7878 }
7879 op_string++;
7880 continue;
7881 }
7882 unknown_vec_op:
7883 /* We don't know this one. */
7884 as_bad (_("unknown vector operation: `%s'"), saved);
7885 return NULL;
7886 }
7887
7888 return op_string;
7889}
7890
252b5132 7891static int
70e41ade 7892i386_immediate (char *imm_start)
252b5132
RH		 7893{
7894 char *save_input_line_pointer;
f3c180ae 7895 char *gotfree_input_line;
252b5132 7896 segT exp_seg = 0;
47926f60 7897 expressionS *exp;
40fb9820
L		 7898 i386_operand_type types;
7899
0dfbf9d7 7900 operand_type_set (&types, ~0);
252b5132
RH		 7901
7902 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7903 {
31b2323c
L		 7904 as_bad (_("at most %d immediate operands are allowed"),
7905 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7906 return 0;
7907 }
7908
7909 exp = &im_expressions[i.imm_operands++];
520dc8e8 7910 i.op[this_operand].imms = exp;
252b5132
RH		 7911
7912 if (is_space_char (*imm_start))
7913 ++imm_start;
7914
7915 save_input_line_pointer = input_line_pointer;
7916 input_line_pointer = imm_start;
7917
d258b828 7918 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7919 if (gotfree_input_line)
7920 input_line_pointer = gotfree_input_line;
252b5132
RH		 7921
7922 exp_seg = expression (exp);
7923
83183c0c 7924 SKIP_WHITESPACE ();
43234a1e
L		 7925
7926 /* Handle vector operations. */
7927 if (*input_line_pointer == '{')
7928 {
7929 input_line_pointer = check_VecOperations (input_line_pointer,
7930 NULL);
7931 if (input_line_pointer == NULL)
7932 return 0;
7933 }
7934
252b5132 7935 if (*input_line_pointer)
f3c180ae 7936 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7937
7938 input_line_pointer = save_input_line_pointer;
f3c180ae 7939 if (gotfree_input_line)
ee86248c
JB		 7940 {
7941 free (gotfree_input_line);
7942
7943 if (exp->X_op == O_constant || exp->X_op == O_register)
7944 exp->X_op = O_illegal;
7945 }
7946
7947 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7948}
252b5132 7949
ee86248c
JB		 7950static int
7951i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7952 i386_operand_type types, const char *imm_start)
7953{
7954 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7955 {
313c53d1
L		 7956 if (imm_start)
7957 as_bad (_("missing or invalid immediate expression `%s'"),
7958 imm_start);
3992d3b7 7959 return 0;
252b5132 7960 }
3e73aa7c 7961 else if (exp->X_op == O_constant)
252b5132 7962 {
47926f60 7963 /* Size it properly later. */
40fb9820 7964 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7965 /* If not 64bit, sign extend val. */
7966 if (flag_code != CODE_64BIT
4eed87de
AM		 7967 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7968 exp->X_add_number
7969 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7970 }
4c63da97 7971#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7972 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7973 && exp_seg != absolute_section
47926f60 7974 && exp_seg != text_section
24eab124
AM		 7975 && exp_seg != data_section
7976 && exp_seg != bss_section
7977 && exp_seg != undefined_section
f86103b7 7978 && !bfd_is_com_section (exp_seg))
252b5132 7979 {
d0b47220 7980 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7981 return 0;
7982 }
7983#endif
a841bdf5 7984 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 7985 {
313c53d1
L		 7986 if (imm_start)
7987 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7988 return 0;
7989 }
252b5132
RH		 7990 else
7991 {
7992 /* This is an address. The size of the address will be
24eab124 7993 determined later, depending on destination register,
3e73aa7c 7994 suffix, or the default for the section. */
40fb9820
L		 7995 i.types[this_operand].bitfield.imm8 = 1;
7996 i.types[this_operand].bitfield.imm16 = 1;
7997 i.types[this_operand].bitfield.imm32 = 1;
7998 i.types[this_operand].bitfield.imm32s = 1;
7999 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8000 i.types[this_operand] = operand_type_and (i.types[this_operand],
8001 types);
252b5132
RH		 8002 }
8003
8004 return 1;
8005}
8006
551c1ca1 8007static char *
e3bb37b5 8008i386_scale (char *scale)
252b5132 8009{
551c1ca1
AM		 8010 offsetT val;
8011 char *save = input_line_pointer;
252b5132 8012
551c1ca1
AM		 8013 input_line_pointer = scale;
8014 val = get_absolute_expression ();
8015
8016 switch (val)
252b5132 8017 {
551c1ca1 8018 case 1:
252b5132
RH		 8019 i.log2_scale_factor = 0;
8020 break;
551c1ca1 8021 case 2:
252b5132
RH		 8022 i.log2_scale_factor = 1;
8023 break;
551c1ca1 8024 case 4:
252b5132
RH		 8025 i.log2_scale_factor = 2;
8026 break;
551c1ca1 8027 case 8:
252b5132
RH		 8028 i.log2_scale_factor = 3;
8029 break;
8030 default:
a724f0f4
JB		 8031 {
8032 char sep = *input_line_pointer;
8033
8034 *input_line_pointer = '\0';
8035 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8036 scale);
8037 *input_line_pointer = sep;
8038 input_line_pointer = save;
8039 return NULL;
8040 }
252b5132 8041 }
29b0f896 8042 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8043 {
8044 as_warn (_("scale factor of %d without an index register"),
24eab124 8045 1 << i.log2_scale_factor);
252b5132 8046 i.log2_scale_factor = 0;
252b5132 8047 }
551c1ca1
AM		 8048 scale = input_line_pointer;
8049 input_line_pointer = save;
8050 return scale;
252b5132
RH		 8051}
8052
252b5132 8053static int
e3bb37b5 8054i386_displacement (char *disp_start, char *disp_end)
252b5132 8055{
29b0f896 8056 expressionS *exp;
252b5132
RH		 8057 segT exp_seg = 0;
8058 char *save_input_line_pointer;
f3c180ae 8059 char *gotfree_input_line;
40fb9820
L		 8060 int override;
8061 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8062 int ret;
252b5132 8063
31b2323c
L		 8064 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8065 {
8066 as_bad (_("at most %d displacement operands are allowed"),
8067 MAX_MEMORY_OPERANDS);
8068 return 0;
8069 }
8070
0dfbf9d7 8071 operand_type_set (&bigdisp, 0);
40fb9820
L		 8072 if ((i.types[this_operand].bitfield.jumpabsolute)
8073 || (!current_templates->start->opcode_modifier.jump
8074 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8075 {
40fb9820 8076 bigdisp.bitfield.disp32 = 1;
e05278af 8077 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8078 if (flag_code == CODE_64BIT)
8079 {
8080 if (!override)
8081 {
8082 bigdisp.bitfield.disp32s = 1;
8083 bigdisp.bitfield.disp64 = 1;
8084 }
8085 }
8086 else if ((flag_code == CODE_16BIT) ^ override)
8087 {
8088 bigdisp.bitfield.disp32 = 0;
8089 bigdisp.bitfield.disp16 = 1;
8090 }
e05278af
JB		 8091 }
8092 else
8093 {
8094 /* For PC-relative branches, the width of the displacement
8095 is dependent upon data size, not address size. */
e05278af 8096 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8097 if (flag_code == CODE_64BIT)
8098 {
8099 if (override || i.suffix == WORD_MNEM_SUFFIX)
8100 bigdisp.bitfield.disp16 = 1;
8101 else
8102 {
8103 bigdisp.bitfield.disp32 = 1;
8104 bigdisp.bitfield.disp32s = 1;
8105 }
8106 }
8107 else
e05278af
JB		 8108 {
8109 if (!override)
8110 override = (i.suffix == (flag_code != CODE_16BIT
8111 ? WORD_MNEM_SUFFIX
8112 : LONG_MNEM_SUFFIX));
40fb9820
L		 8113 bigdisp.bitfield.disp32 = 1;
8114 if ((flag_code == CODE_16BIT) ^ override)
8115 {
8116 bigdisp.bitfield.disp32 = 0;
8117 bigdisp.bitfield.disp16 = 1;
8118 }
e05278af 8119 }
e05278af 8120 }
c6fb90c8
L		 8121 i.types[this_operand] = operand_type_or (i.types[this_operand],
8122 bigdisp);
252b5132
RH		 8123
8124 exp = &disp_expressions[i.disp_operands];
520dc8e8 8125 i.op[this_operand].disps = exp;
252b5132
RH		 8126 i.disp_operands++;
8127 save_input_line_pointer = input_line_pointer;
8128 input_line_pointer = disp_start;
8129 END_STRING_AND_SAVE (disp_end);
8130
8131#ifndef GCC_ASM_O_HACK
8132#define GCC_ASM_O_HACK 0
8133#endif
8134#if GCC_ASM_O_HACK
8135 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8136 if (i.types[this_operand].bitfield.baseIndex
24eab124 8137 && displacement_string_end[-1] == '+')
252b5132
RH		 8138 {
8139 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8140 constraint within gcc asm statements.
8141 For instance:
8142
8143 #define _set_tssldt_desc(n,addr,limit,type) \
8144 __asm__ __volatile__ ( \
8145 "movw %w2,%0\n\t" \
8146 "movw %w1,2+%0\n\t" \
8147 "rorl $16,%1\n\t" \
8148 "movb %b1,4+%0\n\t" \
8149 "movb %4,5+%0\n\t" \
8150 "movb $0,6+%0\n\t" \
8151 "movb %h1,7+%0\n\t" \
8152 "rorl $16,%1" \
8153 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8154
8155 This works great except that the output assembler ends
8156 up looking a bit weird if it turns out that there is
8157 no offset. You end up producing code that looks like:
8158
8159 #APP
8160 movw $235,(%eax)
8161 movw %dx,2+(%eax)
8162 rorl $16,%edx
8163 movb %dl,4+(%eax)
8164 movb $137,5+(%eax)
8165 movb $0,6+(%eax)
8166 movb %dh,7+(%eax)
8167 rorl $16,%edx
8168 #NO_APP
8169
47926f60 8170 So here we provide the missing zero. */
24eab124
AM		 8171
8172 *displacement_string_end = '0';
252b5132
RH		 8173 }
8174#endif
d258b828 8175 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8176 if (gotfree_input_line)
8177 input_line_pointer = gotfree_input_line;
252b5132 8178
24eab124 8179 exp_seg = expression (exp);
252b5132 8180
636c26b0
AM		 8181 SKIP_WHITESPACE ();
8182 if (*input_line_pointer)
8183 as_bad (_("junk `%s' after expression"), input_line_pointer);
8184#if GCC_ASM_O_HACK
8185 RESTORE_END_STRING (disp_end + 1);
8186#endif
636c26b0 8187 input_line_pointer = save_input_line_pointer;
636c26b0 8188 if (gotfree_input_line)
ee86248c
JB		 8189 {
8190 free (gotfree_input_line);
8191
8192 if (exp->X_op == O_constant || exp->X_op == O_register)
8193 exp->X_op = O_illegal;
8194 }
8195
8196 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8197
8198 RESTORE_END_STRING (disp_end);
8199
8200 return ret;
8201}
8202
8203static int
8204i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8205 i386_operand_type types, const char *disp_start)
8206{
8207 i386_operand_type bigdisp;
8208 int ret = 1;
636c26b0 8209
24eab124
AM		 8210 /* We do this to make sure that the section symbol is in
8211 the symbol table. We will ultimately change the relocation
47926f60 8212 to be relative to the beginning of the section. */
1ae12ab7 8213 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8214 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8215 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8216 {
636c26b0 8217 if (exp->X_op != O_symbol)
3992d3b7 8218 goto inv_disp;
636c26b0 8219
e5cb08ac 8220 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8221 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8222 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8223 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8224 exp->X_op = O_subtract;
8225 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8226 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8227 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8228 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8229 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8230 else
29b0f896 8231 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8232 }
252b5132 8233
3992d3b7
AM		 8234 else if (exp->X_op == O_absent
8235 || exp->X_op == O_illegal
ee86248c 8236 || exp->X_op == O_big)
2daf4fd8 8237 {
3992d3b7
AM		 8238 inv_disp:
8239 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8240 disp_start);
3992d3b7 8241 ret = 0;
2daf4fd8
AM		 8242 }
8243
0e1147d9
L		 8244 else if (flag_code == CODE_64BIT
8245 && !i.prefix[ADDR_PREFIX]
8246 && exp->X_op == O_constant)
8247 {
8248 /* Since displacement is signed extended to 64bit, don't allow
8249 disp32 and turn off disp32s if they are out of range. */
8250 i.types[this_operand].bitfield.disp32 = 0;
8251 if (!fits_in_signed_long (exp->X_add_number))
8252 {
8253 i.types[this_operand].bitfield.disp32s = 0;
8254 if (i.types[this_operand].bitfield.baseindex)
8255 {
8256 as_bad (_("0x%lx out range of signed 32bit displacement"),
8257 (long) exp->X_add_number);
8258 ret = 0;
8259 }
8260 }
8261 }
8262
4c63da97 8263#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8264 else if (exp->X_op != O_constant
8265 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8266 && exp_seg != absolute_section
8267 && exp_seg != text_section
8268 && exp_seg != data_section
8269 && exp_seg != bss_section
8270 && exp_seg != undefined_section
8271 && !bfd_is_com_section (exp_seg))
24eab124 8272 {
d0b47220 8273 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8274 ret = 0;
24eab124 8275 }
252b5132 8276#endif
3956db08 8277
40fb9820
L		 8278 /* Check if this is a displacement only operand. */
8279 bigdisp = i.types[this_operand];
8280 bigdisp.bitfield.disp8 = 0;
8281 bigdisp.bitfield.disp16 = 0;
8282 bigdisp.bitfield.disp32 = 0;
8283 bigdisp.bitfield.disp32s = 0;
8284 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8285 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8286 i.types[this_operand] = operand_type_and (i.types[this_operand],
8287 types);
3956db08 8288
3992d3b7 8289 return ret;
252b5132
RH		 8290}
8291
eecb386c 8292/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8293 Return 1 on success, 0 on a failure. */
8294
252b5132 8295static int
e3bb37b5 8296i386_index_check (const char *operand_string)
252b5132 8297{
fc0763e6 8298 const char *kind = "base/index";
be05d201
L		 8299 enum flag_code addr_mode;
8300
8301 if (i.prefix[ADDR_PREFIX])
8302 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8303 else
8304 {
8305 addr_mode = flag_code;
8306
24eab124 8307#if INFER_ADDR_PREFIX
be05d201
L		 8308 if (i.mem_operands == 0)
8309 {
8310 /* Infer address prefix from the first memory operand. */
8311 const reg_entry *addr_reg = i.base_reg;
8312
8313 if (addr_reg == NULL)
8314 addr_reg = i.index_reg;
eecb386c 8315
be05d201
L		 8316 if (addr_reg)
8317 {
8318 if (addr_reg->reg_num == RegEip
8319 || addr_reg->reg_num == RegEiz
8320 || addr_reg->reg_type.bitfield.reg32)
8321 addr_mode = CODE_32BIT;
8322 else if (flag_code != CODE_64BIT
8323 && addr_reg->reg_type.bitfield.reg16)
8324 addr_mode = CODE_16BIT;
8325
8326 if (addr_mode != flag_code)
8327 {
8328 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8329 i.prefixes += 1;
8330 /* Change the size of any displacement too. At most one
8331 of Disp16 or Disp32 is set.
8332 FIXME. There doesn't seem to be any real need for
8333 separate Disp16 and Disp32 flags. The same goes for
8334 Imm16 and Imm32. Removing them would probably clean
8335 up the code quite a lot. */
8336 if (flag_code != CODE_64BIT
8337 && (i.types[this_operand].bitfield.disp16
8338 || i.types[this_operand].bitfield.disp32))
8339 i.types[this_operand]
8340 = operand_type_xor (i.types[this_operand], disp16_32);
8341 }
8342 }
8343 }
24eab124 8344#endif
be05d201
L		 8345 }
8346
fc0763e6
JB		 8347 if (current_templates->start->opcode_modifier.isstring
8348 && !current_templates->start->opcode_modifier.immext
8349 && (current_templates->end[-1].opcode_modifier.isstring
8350 || i.mem_operands))
8351 {
8352 /* Memory operands of string insns are special in that they only allow
8353 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8354 const reg_entry *expected_reg;
8355 static const char *di_si[][2] =
8356 {
8357 { "esi", "edi" },
8358 { "si", "di" },
8359 { "rsi", "rdi" }
8360 };
8361 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8362
8363 kind = "string address";
8364
8365 if (current_templates->start->opcode_modifier.w)
8366 {
8367 i386_operand_type type = current_templates->end[-1].operand_types[0];
8368
8369 if (!type.bitfield.baseindex
8370 || ((!i.mem_operands != !intel_syntax)
8371 && current_templates->end[-1].operand_types[1]
8372 .bitfield.baseindex))
8373 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8374 expected_reg = hash_find (reg_hash,
8375 di_si[addr_mode][type.bitfield.esseg]);
8376
fc0763e6
JB		 8377 }
8378 else
be05d201 8379 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8380
be05d201
L		 8381 if (i.base_reg != expected_reg
8382 || i.index_reg
fc0763e6 8383 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8384 {
be05d201
L		 8385 /* The second memory operand must have the same size as
8386 the first one. */
8387 if (i.mem_operands
8388 && i.base_reg
8389 && !((addr_mode == CODE_64BIT
8390 && i.base_reg->reg_type.bitfield.reg64)
8391 || (addr_mode == CODE_32BIT
8392 ? i.base_reg->reg_type.bitfield.reg32
8393 : i.base_reg->reg_type.bitfield.reg16)))
8394 goto bad_address;
8395
fc0763e6
JB		 8396 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8397 operand_string,
8398 intel_syntax ? '[' : '(',
8399 register_prefix,
be05d201 8400 expected_reg->reg_name,
fc0763e6 8401 intel_syntax ? ']' : ')');
be05d201 8402 return 1;
fc0763e6 8403 }
be05d201
L		 8404 else
8405 return 1;
8406
8407bad_address:
8408 as_bad (_("`%s' is not a valid %s expression"),
8409 operand_string, kind);
8410 return 0;
3e73aa7c
JH		 8411 }
8412 else
8413 {
be05d201
L		 8414 if (addr_mode != CODE_16BIT)
8415 {
8416 /* 32-bit/64-bit checks. */
8417 if ((i.base_reg
8418 && (addr_mode == CODE_64BIT
8419 ? !i.base_reg->reg_type.bitfield.reg64
8420 : !i.base_reg->reg_type.bitfield.reg32)
8421 && (i.index_reg
8422 || (i.base_reg->reg_num
8423 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8424 || (i.index_reg
8425 && !i.index_reg->reg_type.bitfield.regxmm
8426 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8427 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8428 && ((addr_mode == CODE_64BIT
8429 ? !(i.index_reg->reg_type.bitfield.reg64
8430 || i.index_reg->reg_num == RegRiz)
8431 : !(i.index_reg->reg_type.bitfield.reg32
8432 || i.index_reg->reg_num == RegEiz))
8433 || !i.index_reg->reg_type.bitfield.baseindex)))
8434 goto bad_address;
8435 }
8436 else
3e73aa7c 8437 {
be05d201 8438 /* 16-bit checks. */
3e73aa7c 8439 if ((i.base_reg
40fb9820
L		 8440 && (!i.base_reg->reg_type.bitfield.reg16
8441 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8442 || (i.index_reg
40fb9820
L		 8443 && (!i.index_reg->reg_type.bitfield.reg16
8444 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8445 || !(i.base_reg
8446 && i.base_reg->reg_num < 6
8447 && i.index_reg->reg_num >= 6
8448 && i.log2_scale_factor == 0))))
be05d201 8449 goto bad_address;
3e73aa7c
JH		 8450 }
8451 }
be05d201 8452 return 1;
24eab124 8453}
252b5132 8454
43234a1e
L		 8455/* Handle vector immediates. */
8456
8457static int
8458RC_SAE_immediate (const char *imm_start)
8459{
8460 unsigned int match_found, j;
8461 const char *pstr = imm_start;
8462 expressionS *exp;
8463
8464 if (*pstr != '{')
8465 return 0;
8466
8467 pstr++;
8468 match_found = 0;
8469 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8470 {
8471 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8472 {
8473 if (!i.rounding)
8474 {
8475 rc_op.type = RC_NamesTable[j].type;
8476 rc_op.operand = this_operand;
8477 i.rounding = &rc_op;
8478 }
8479 else
8480 {
8481 as_bad (_("duplicated `%s'"), imm_start);
8482 return 0;
8483 }
8484 pstr += RC_NamesTable[j].len;
8485 match_found = 1;
8486 break;
8487 }
8488 }
8489 if (!match_found)
8490 return 0;
8491
8492 if (*pstr++ != '}')
8493 {
8494 as_bad (_("Missing '}': '%s'"), imm_start);
8495 return 0;
8496 }
8497 /* RC/SAE immediate string should contain nothing more. */;
8498 if (*pstr != 0)
8499 {
8500 as_bad (_("Junk after '}': '%s'"), imm_start);
8501 return 0;
8502 }
8503
8504 exp = &im_expressions[i.imm_operands++];
8505 i.op[this_operand].imms = exp;
8506
8507 exp->X_op = O_constant;
8508 exp->X_add_number = 0;
8509 exp->X_add_symbol = (symbolS *) 0;
8510 exp->X_op_symbol = (symbolS *) 0;
8511
8512 i.types[this_operand].bitfield.imm8 = 1;
8513 return 1;
8514}
8515
fc0763e6 8516/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8517 on error. */
252b5132 8518
252b5132 8519static int
a7619375 8520i386_att_operand (char *operand_string)
252b5132 8521{
af6bdddf
AM		 8522 const reg_entry *r;
8523 char *end_op;
24eab124 8524 char *op_string = operand_string;
252b5132 8525
24eab124 8526 if (is_space_char (*op_string))
252b5132
RH		 8527 ++op_string;
8528
24eab124 8529 /* We check for an absolute prefix (differentiating,
47926f60 8530 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8531 if (*op_string == ABSOLUTE_PREFIX)
8532 {
8533 ++op_string;
8534 if (is_space_char (*op_string))
8535 ++op_string;
40fb9820 8536 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8537 }
252b5132 8538
47926f60 8539 /* Check if operand is a register. */
4d1bb795 8540 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8541 {
40fb9820
L		 8542 i386_operand_type temp;
8543
24eab124
AM		 8544 /* Check for a segment override by searching for ':' after a
8545 segment register. */
8546 op_string = end_op;
8547 if (is_space_char (*op_string))
8548 ++op_string;
40fb9820
L		 8549 if (*op_string == ':'
8550 && (r->reg_type.bitfield.sreg2
8551 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8552 {
8553 switch (r->reg_num)
8554 {
8555 case 0:
8556 i.seg[i.mem_operands] = &es;
8557 break;
8558 case 1:
8559 i.seg[i.mem_operands] = &cs;
8560 break;
8561 case 2:
8562 i.seg[i.mem_operands] = &ss;
8563 break;
8564 case 3:
8565 i.seg[i.mem_operands] = &ds;
8566 break;
8567 case 4:
8568 i.seg[i.mem_operands] = &fs;
8569 break;
8570 case 5:
8571 i.seg[i.mem_operands] = &gs;
8572 break;
8573 }
252b5132 8574
24eab124 8575 /* Skip the ':' and whitespace. */
252b5132
RH		 8576 ++op_string;
8577 if (is_space_char (*op_string))
24eab124 8578 ++op_string;
252b5132 8579
24eab124
AM		 8580 if (!is_digit_char (*op_string)
8581 && !is_identifier_char (*op_string)
8582 && *op_string != '('
8583 && *op_string != ABSOLUTE_PREFIX)
8584 {
8585 as_bad (_("bad memory operand `%s'"), op_string);
8586 return 0;
8587 }
47926f60 8588 /* Handle case of %es:*foo. */
24eab124
AM		 8589 if (*op_string == ABSOLUTE_PREFIX)
8590 {
8591 ++op_string;
8592 if (is_space_char (*op_string))
8593 ++op_string;
40fb9820 8594 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8595 }
8596 goto do_memory_reference;
8597 }
43234a1e
L		 8598
8599 /* Handle vector operations. */
8600 if (*op_string == '{')
8601 {
8602 op_string = check_VecOperations (op_string, NULL);
8603 if (op_string == NULL)
8604 return 0;
8605 }
8606
24eab124
AM		 8607 if (*op_string)
8608 {
d0b47220 8609 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8610 return 0;
8611 }
40fb9820
L		 8612 temp = r->reg_type;
8613 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8614 i.types[this_operand] = operand_type_or (i.types[this_operand],
8615 temp);
7d5e4556 8616 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8617 i.op[this_operand].regs = r;
24eab124
AM		 8618 i.reg_operands++;
8619 }
af6bdddf
AM		 8620 else if (*op_string == REGISTER_PREFIX)
8621 {
8622 as_bad (_("bad register name `%s'"), op_string);
8623 return 0;
8624 }
24eab124 8625 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8626 {
24eab124 8627 ++op_string;
40fb9820 8628 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8629 {
d0b47220 8630 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8631 return 0;
8632 }
8633 if (!i386_immediate (op_string))
8634 return 0;
8635 }
43234a1e
L		 8636 else if (RC_SAE_immediate (operand_string))
8637 {
8638 /* If it is a RC or SAE immediate, do nothing. */
8639 ;
8640 }
24eab124
AM		 8641 else if (is_digit_char (*op_string)
8642 || is_identifier_char (*op_string)
d02603dc 8643 || *op_string == '"'
e5cb08ac 8644 || *op_string == '(')
24eab124 8645 {
47926f60 8646 /* This is a memory reference of some sort. */
af6bdddf 8647 char *base_string;
252b5132 8648
47926f60 8649 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8650 char *displacement_string_start;
8651 char *displacement_string_end;
43234a1e 8652 char *vop_start;
252b5132 8653
24eab124 8654 do_memory_reference:
24eab124 8655 if ((i.mem_operands == 1
40fb9820 8656 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8657 || i.mem_operands == 2)
8658 {
8659 as_bad (_("too many memory references for `%s'"),
8660 current_templates->start->name);
8661 return 0;
8662 }
252b5132 8663
24eab124
AM		 8664 /* Check for base index form. We detect the base index form by
8665 looking for an ')' at the end of the operand, searching
8666 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8667 after the '('. */
af6bdddf 8668 base_string = op_string + strlen (op_string);
c3332e24 8669
43234a1e
L		 8670 /* Handle vector operations. */
8671 vop_start = strchr (op_string, '{');
8672 if (vop_start && vop_start < base_string)
8673 {
8674 if (check_VecOperations (vop_start, base_string) == NULL)
8675 return 0;
8676 base_string = vop_start;
8677 }
8678
af6bdddf
AM		 8679 --base_string;
8680 if (is_space_char (*base_string))
8681 --base_string;
252b5132 8682
47926f60 8683 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8684 displacement_string_start = op_string;
8685 displacement_string_end = base_string + 1;
252b5132 8686
24eab124
AM		 8687 if (*base_string == ')')
8688 {
af6bdddf 8689 char *temp_string;
24eab124
AM		 8690 unsigned int parens_balanced = 1;
8691 /* We've already checked that the number of left & right ()'s are
47926f60 8692 equal, so this loop will not be infinite. */
24eab124
AM		 8693 do
8694 {
8695 base_string--;
8696 if (*base_string == ')')
8697 parens_balanced++;
8698 if (*base_string == '(')
8699 parens_balanced--;
8700 }
8701 while (parens_balanced);
c3332e24 8702
af6bdddf 8703 temp_string = base_string;
c3332e24 8704
24eab124 8705 /* Skip past '(' and whitespace. */
252b5132
RH		 8706 ++base_string;
8707 if (is_space_char (*base_string))
24eab124 8708 ++base_string;
252b5132 8709
af6bdddf 8710 if (*base_string == ','
4eed87de
AM		 8711 || ((i.base_reg = parse_register (base_string, &end_op))
8712 != NULL))
252b5132 8713 {
af6bdddf 8714 displacement_string_end = temp_string;
252b5132 8715
40fb9820 8716 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8717
af6bdddf 8718 if (i.base_reg)
24eab124 8719 {
24eab124
AM		 8720 base_string = end_op;
8721 if (is_space_char (*base_string))
8722 ++base_string;
af6bdddf
AM		 8723 }
8724
8725 /* There may be an index reg or scale factor here. */
8726 if (*base_string == ',')
8727 {
8728 ++base_string;
8729 if (is_space_char (*base_string))
8730 ++base_string;
8731
4eed87de
AM		 8732 if ((i.index_reg = parse_register (base_string, &end_op))
8733 != NULL)
24eab124 8734 {
af6bdddf 8735 base_string = end_op;
24eab124
AM		 8736 if (is_space_char (*base_string))
8737 ++base_string;
af6bdddf
AM		 8738 if (*base_string == ',')
8739 {
8740 ++base_string;
8741 if (is_space_char (*base_string))
8742 ++base_string;
8743 }
e5cb08ac 8744 else if (*base_string != ')')
af6bdddf 8745 {
4eed87de
AM		 8746 as_bad (_("expecting `,' or `)' "
8747 "after index register in `%s'"),
af6bdddf
AM		 8748 operand_string);
8749 return 0;
8750 }
24eab124 8751 }
af6bdddf 8752 else if (*base_string == REGISTER_PREFIX)
24eab124 8753 {
f76bf5e0
L		 8754 end_op = strchr (base_string, ',');
8755 if (end_op)
8756 *end_op = '\0';
af6bdddf 8757 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8758 return 0;
8759 }
252b5132 8760
47926f60 8761 /* Check for scale factor. */
551c1ca1 8762 if (*base_string != ')')
af6bdddf 8763 {
551c1ca1
AM		 8764 char *end_scale = i386_scale (base_string);
8765
8766 if (!end_scale)
af6bdddf 8767 return 0;
24eab124 8768
551c1ca1 8769 base_string = end_scale;
af6bdddf
AM		 8770 if (is_space_char (*base_string))
8771 ++base_string;
8772 if (*base_string != ')')
8773 {
4eed87de
AM		 8774 as_bad (_("expecting `)' "
8775 "after scale factor in `%s'"),
af6bdddf
AM		 8776 operand_string);
8777 return 0;
8778 }
8779 }
8780 else if (!i.index_reg)
24eab124 8781 {
4eed87de
AM		 8782 as_bad (_("expecting index register or scale factor "
8783 "after `,'; got '%c'"),
af6bdddf 8784 *base_string);
24eab124
AM		 8785 return 0;
8786 }
8787 }
af6bdddf 8788 else if (*base_string != ')')
24eab124 8789 {
4eed87de
AM		 8790 as_bad (_("expecting `,' or `)' "
8791 "after base register in `%s'"),
af6bdddf 8792 operand_string);
24eab124
AM		 8793 return 0;
8794 }
c3332e24 8795 }
af6bdddf 8796 else if (*base_string == REGISTER_PREFIX)
c3332e24 8797 {
f76bf5e0
L		 8798 end_op = strchr (base_string, ',');
8799 if (end_op)
8800 *end_op = '\0';
af6bdddf 8801 as_bad (_("bad register name `%s'"), base_string);
24eab124 8802 return 0;
c3332e24 8803 }
24eab124
AM		 8804 }
8805
8806 /* If there's an expression beginning the operand, parse it,
8807 assuming displacement_string_start and
8808 displacement_string_end are meaningful. */
8809 if (displacement_string_start != displacement_string_end)
8810 {
8811 if (!i386_displacement (displacement_string_start,
8812 displacement_string_end))
8813 return 0;
8814 }
8815
8816 /* Special case for (%dx) while doing input/output op. */
8817 if (i.base_reg
0dfbf9d7
L		 8818 && operand_type_equal (&i.base_reg->reg_type,
8819 &reg16_inoutportreg)
24eab124
AM		 8820 && i.index_reg == 0
8821 && i.log2_scale_factor == 0
8822 && i.seg[i.mem_operands] == 0
40fb9820 8823 && !operand_type_check (i.types[this_operand], disp))
24eab124 8824 {
65da13b5 8825 i.types[this_operand] = inoutportreg;
24eab124
AM		 8826 return 1;
8827 }
8828
eecb386c
AM		 8829 if (i386_index_check (operand_string) == 0)
8830 return 0;
5c07affc 8831 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8832 i.mem_operands++;
8833 }
8834 else
ce8a8b2f
AM		 8835 {
8836 /* It's not a memory operand; argh! */
24eab124
AM		 8837 as_bad (_("invalid char %s beginning operand %d `%s'"),
8838 output_invalid (*op_string),
8839 this_operand + 1,
8840 op_string);
8841 return 0;
8842 }
47926f60 8843 return 1; /* Normal return. */
252b5132
RH		 8844}
8845\f
fa94de6b
RM		 8846/* Calculate the maximum variable size (i.e., excluding fr_fix)
8847 that an rs_machine_dependent frag may reach. */
8848
8849unsigned int
8850i386_frag_max_var (fragS *frag)
8851{
8852 /* The only relaxable frags are for jumps.
8853 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8854 gas_assert (frag->fr_type == rs_machine_dependent);
8855 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8856}
8857
b084df0b
L		 8858#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8859static int
8dcea932 8860elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8861{
8862 /* STT_GNU_IFUNC symbol must go through PLT. */
8863 if ((symbol_get_bfdsym (fr_symbol)->flags
8864 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8865 return 0;
8866
8867 if (!S_IS_EXTERNAL (fr_symbol))
8868 /* Symbol may be weak or local. */
8869 return !S_IS_WEAK (fr_symbol);
8870
8dcea932
L		 8871 /* Global symbols with non-default visibility can't be preempted. */
8872 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
8873 return 1;
8874
8875 if (fr_var != NO_RELOC)
8876 switch ((enum bfd_reloc_code_real) fr_var)
8877 {
8878 case BFD_RELOC_386_PLT32:
8879 case BFD_RELOC_X86_64_PLT32:
8880 /* Symbol with PLT relocatin may be preempted. */
8881 return 0;
8882 default:
8883 abort ();
8884 }
8885
b084df0b
L		 8886 /* Global symbols with default visibility in a shared library may be
8887 preempted by another definition. */
8dcea932 8888 return !shared;
b084df0b
L		 8889}
8890#endif
8891
ee7fcc42
AM		 8892/* md_estimate_size_before_relax()
8893
8894 Called just before relax() for rs_machine_dependent frags. The x86
8895 assembler uses these frags to handle variable size jump
8896 instructions.
8897
8898 Any symbol that is now undefined will not become defined.
8899 Return the correct fr_subtype in the frag.
8900 Return the initial "guess for variable size of frag" to caller.
8901 The guess is actually the growth beyond the fixed part. Whatever
8902 we do to grow the fixed or variable part contributes to our
8903 returned value. */
8904
252b5132 8905int
7016a5d5 8906md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8907{
252b5132 8908 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8909 check for un-relaxable symbols. On an ELF system, we can't relax
8910 an externally visible symbol, because it may be overridden by a
8911 shared library. */
8912 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8913#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8914 || (IS_ELF
8dcea932
L		 8915 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
8916 fragP->fr_var))
fbeb56a4
DK		 8917#endif
8918#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8919 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8920 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8921#endif
8922 )
252b5132 8923 {
b98ef147
AM		 8924 /* Symbol is undefined in this segment, or we need to keep a
8925 reloc so that weak symbols can be overridden. */
8926 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8927 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8928 unsigned char *opcode;
8929 int old_fr_fix;
f6af82bd 8930
ee7fcc42 8931 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8932 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8933 else if (size == 2)
f6af82bd
AM		 8934 reloc_type = BFD_RELOC_16_PCREL;
8935 else
8936 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8937
ee7fcc42
AM		 8938 old_fr_fix = fragP->fr_fix;
8939 opcode = (unsigned char *) fragP->fr_opcode;
8940
fddf5b5b 8941 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8942 {
fddf5b5b
AM		 8943 case UNCOND_JUMP:
8944 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8945 opcode[0] = 0xe9;
252b5132 8946 fragP->fr_fix += size;
062cd5e7
AS		 8947 fix_new (fragP, old_fr_fix, size,
8948 fragP->fr_symbol,
8949 fragP->fr_offset, 1,
8950 reloc_type);
252b5132
RH		 8951 break;
8952
fddf5b5b 8953 case COND_JUMP86:
412167cb
AM		 8954 if (size == 2
8955 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8956 {
8957 /* Negate the condition, and branch past an
8958 unconditional jump. */
8959 opcode[0] ^= 1;
8960 opcode[1] = 3;
8961 /* Insert an unconditional jump. */
8962 opcode[2] = 0xe9;
8963 /* We added two extra opcode bytes, and have a two byte
8964 offset. */
8965 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8966 fix_new (fragP, old_fr_fix + 2, 2,
8967 fragP->fr_symbol,
8968 fragP->fr_offset, 1,
8969 reloc_type);
fddf5b5b
AM		 8970 break;
8971 }
8972 /* Fall through. */
8973
8974 case COND_JUMP:
412167cb
AM		 8975 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8976 {
3e02c1cc
AM		 8977 fixS *fixP;
8978
412167cb 8979 fragP->fr_fix += 1;
3e02c1cc
AM		 8980 fixP = fix_new (fragP, old_fr_fix, 1,
8981 fragP->fr_symbol,
8982 fragP->fr_offset, 1,
8983 BFD_RELOC_8_PCREL);
8984 fixP->fx_signed = 1;
412167cb
AM		 8985 break;
8986 }
93c2a809 8987
24eab124 8988 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8989 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8990 opcode[1] = opcode[0] + 0x10;
f6af82bd 8991 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8992 /* We've added an opcode byte. */
8993 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8994 fix_new (fragP, old_fr_fix + 1, size,
8995 fragP->fr_symbol,
8996 fragP->fr_offset, 1,
8997 reloc_type);
252b5132 8998 break;
fddf5b5b
AM		 8999
9000 default:
9001 BAD_CASE (fragP->fr_subtype);
9002 break;
252b5132
RH		 9003 }
9004 frag_wane (fragP);
ee7fcc42 9005 return fragP->fr_fix - old_fr_fix;
252b5132 9006 }
93c2a809 9007
93c2a809
AM		 9008 /* Guess size depending on current relax state. Initially the relax
9009 state will correspond to a short jump and we return 1, because
9010 the variable part of the frag (the branch offset) is one byte
9011 long. However, we can relax a section more than once and in that
9012 case we must either set fr_subtype back to the unrelaxed state,
9013 or return the value for the appropriate branch. */
9014 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9015}
9016
47926f60
KH		 9017/* Called after relax() is finished.
9018
9019 In: Address of frag.
9020 fr_type == rs_machine_dependent.
9021 fr_subtype is what the address relaxed to.
9022
9023 Out: Any fixSs and constants are set up.
9024 Caller will turn frag into a ".space 0". */
9025
252b5132 9026void
7016a5d5
TG		 9027md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9028 fragS *fragP)
252b5132 9029{
29b0f896 9030 unsigned char *opcode;
252b5132 9031 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9032 offsetT target_address;
9033 offsetT opcode_address;
252b5132 9034 unsigned int extension = 0;
847f7ad4 9035 offsetT displacement_from_opcode_start;
252b5132
RH		 9036
9037 opcode = (unsigned char *) fragP->fr_opcode;
9038
47926f60 9039 /* Address we want to reach in file space. */
252b5132 9040 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9041
47926f60 9042 /* Address opcode resides at in file space. */
252b5132
RH		 9043 opcode_address = fragP->fr_address + fragP->fr_fix;
9044
47926f60 9045 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9046 displacement_from_opcode_start = target_address - opcode_address;
9047
fddf5b5b 9048 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9049 {
47926f60
KH		 9050 /* Don't have to change opcode. */
9051 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9052 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9053 }
9054 else
9055 {
9056 if (no_cond_jump_promotion
9057 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9058 as_warn_where (fragP->fr_file, fragP->fr_line,
9059 _("long jump required"));
252b5132 9060
fddf5b5b
AM		 9061 switch (fragP->fr_subtype)
9062 {
9063 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9064 extension = 4; /* 1 opcode + 4 displacement */
9065 opcode[0] = 0xe9;
9066 where_to_put_displacement = &opcode[1];
9067 break;
252b5132 9068
fddf5b5b
AM		 9069 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9070 extension = 2; /* 1 opcode + 2 displacement */
9071 opcode[0] = 0xe9;
9072 where_to_put_displacement = &opcode[1];
9073 break;
252b5132 9074
fddf5b5b
AM		 9075 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9076 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9077 extension = 5; /* 2 opcode + 4 displacement */
9078 opcode[1] = opcode[0] + 0x10;
9079 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9080 where_to_put_displacement = &opcode[2];
9081 break;
252b5132 9082
fddf5b5b
AM		 9083 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9084 extension = 3; /* 2 opcode + 2 displacement */
9085 opcode[1] = opcode[0] + 0x10;
9086 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9087 where_to_put_displacement = &opcode[2];
9088 break;
252b5132 9089
fddf5b5b
AM		 9090 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9091 extension = 4;
9092 opcode[0] ^= 1;
9093 opcode[1] = 3;
9094 opcode[2] = 0xe9;
9095 where_to_put_displacement = &opcode[3];
9096 break;
9097
9098 default:
9099 BAD_CASE (fragP->fr_subtype);
9100 break;
9101 }
252b5132 9102 }
fddf5b5b 9103
7b81dfbb
AJ		 9104 /* If size if less then four we are sure that the operand fits,
9105 but if it's 4, then it could be that the displacement is larger
9106 then -/+ 2GB. */
9107 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9108 && object_64bit
9109 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9110 + ((addressT) 1 << 31))
9111 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9112 {
9113 as_bad_where (fragP->fr_file, fragP->fr_line,
9114 _("jump target out of range"));
9115 /* Make us emit 0. */
9116 displacement_from_opcode_start = extension;
9117 }
47926f60 9118 /* Now put displacement after opcode. */
252b5132
RH		 9119 md_number_to_chars ((char *) where_to_put_displacement,
9120 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9121 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9122 fragP->fr_fix += extension;
9123}
9124\f
7016a5d5 9125/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9126 by our caller that we have all the info we need to fix it up.
9127
7016a5d5
TG		 9128 Parameter valP is the pointer to the value of the bits.
9129
252b5132
RH		 9130 On the 386, immediates, displacements, and data pointers are all in
9131 the same (little-endian) format, so we don't need to care about which
9132 we are handling. */
9133
94f592af 9134void
7016a5d5 9135md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9136{
94f592af 9137 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9138 valueT value = *valP;
252b5132 9139
f86103b7 9140#if !defined (TE_Mach)
93382f6d
AM		 9141 if (fixP->fx_pcrel)
9142 {
9143 switch (fixP->fx_r_type)
9144 {
5865bb77
ILT		 9145 default:
9146 break;
9147
d6ab8113
JB		 9148 case BFD_RELOC_64:
9149 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9150 break;
93382f6d 9151 case BFD_RELOC_32:
ae8887b5 9152 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9153 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9154 break;
9155 case BFD_RELOC_16:
9156 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9157 break;
9158 case BFD_RELOC_8:
9159 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9160 break;
9161 }
9162 }
252b5132 9163
a161fe53 9164 if (fixP->fx_addsy != NULL
31312f95 9165 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9166 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9167 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9168 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9169 && !use_rela_relocations)
252b5132 9170 {
31312f95
AM		 9171 /* This is a hack. There should be a better way to handle this.
9172 This covers for the fact that bfd_install_relocation will
9173 subtract the current location (for partial_inplace, PC relative
9174 relocations); see more below. */
252b5132 9175#ifndef OBJ_AOUT
718ddfc0 9176 if (IS_ELF
252b5132
RH		 9177#ifdef TE_PE
9178 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9179#endif
9180 )
9181 value += fixP->fx_where + fixP->fx_frag->fr_address;
9182#endif
9183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9184 if (IS_ELF)
252b5132 9185 {
6539b54b 9186 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9187
6539b54b 9188 if ((sym_seg == seg
2f66722d 9189 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9190 && sym_seg != absolute_section))
af65af87 9191 && !generic_force_reloc (fixP))
2f66722d
AM		 9192 {
9193 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9194 bfd_install_relocation subtracts them out again. I think
9195 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9196 it. FIXME. */
9197 value += fixP->fx_where + fixP->fx_frag->fr_address;
9198 }
252b5132
RH		 9199 }
9200#endif
9201#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9202 /* For some reason, the PE format does not store a
9203 section address offset for a PC relative symbol. */
9204 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9205 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9206 value += md_pcrel_from (fixP);
9207#endif
9208 }
fbeb56a4 9209#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9210 if (fixP->fx_addsy != NULL
9211 && S_IS_WEAK (fixP->fx_addsy)
9212 /* PR 16858: Do not modify weak function references. */
9213 && ! fixP->fx_pcrel)
fbeb56a4 9214 {
296a8689
NC		 9215#if !defined (TE_PEP)
9216 /* For x86 PE weak function symbols are neither PC-relative
9217 nor do they set S_IS_FUNCTION. So the only reliable way
9218 to detect them is to check the flags of their containing
9219 section. */
9220 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9221 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9222 ;
9223 else
9224#endif
fbeb56a4
DK		 9225 value -= S_GET_VALUE (fixP->fx_addsy);
9226 }
9227#endif
252b5132
RH		 9228
9229 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9230 and we must not disappoint it. */
252b5132 9231#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9232 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9233 switch (fixP->fx_r_type)
9234 {
9235 case BFD_RELOC_386_PLT32:
3e73aa7c 9236 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9237 /* Make the jump instruction point to the address of the operand. At
9238 runtime we merely add the offset to the actual PLT entry. */
9239 value = -4;
9240 break;
31312f95 9241
13ae64f3
JJ		 9242 case BFD_RELOC_386_TLS_GD:
9243 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9244 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9245 case BFD_RELOC_386_TLS_IE:
9246 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9247 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9248 case BFD_RELOC_X86_64_TLSGD:
9249 case BFD_RELOC_X86_64_TLSLD:
9250 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9251 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9252 value = 0; /* Fully resolved at runtime. No addend. */
9253 /* Fallthrough */
9254 case BFD_RELOC_386_TLS_LE:
9255 case BFD_RELOC_386_TLS_LDO_32:
9256 case BFD_RELOC_386_TLS_LE_32:
9257 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9258 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9259 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9260 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9261 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9262 break;
9263
67a4f2b7
AO		 9264 case BFD_RELOC_386_TLS_DESC_CALL:
9265 case BFD_RELOC_X86_64_TLSDESC_CALL:
9266 value = 0; /* Fully resolved at runtime. No addend. */
9267 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9268 fixP->fx_done = 0;
9269 return;
9270
00f7efb6
JJ		 9271 case BFD_RELOC_386_GOT32:
9272 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9273 value = 0; /* Fully resolved at runtime. No addend. */
9274 break;
47926f60
KH		 9275
9276 case BFD_RELOC_VTABLE_INHERIT:
9277 case BFD_RELOC_VTABLE_ENTRY:
9278 fixP->fx_done = 0;
94f592af 9279 return;
47926f60
KH		 9280
9281 default:
9282 break;
9283 }
9284#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9285 *valP = value;
f86103b7 9286#endif /* !defined (TE_Mach) */
3e73aa7c 9287
3e73aa7c 9288 /* Are we finished with this relocation now? */
c6682705 9289 if (fixP->fx_addsy == NULL)
3e73aa7c 9290 fixP->fx_done = 1;
fbeb56a4
DK		 9291#if defined (OBJ_COFF) && defined (TE_PE)
9292 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9293 {
9294 fixP->fx_done = 0;
9295 /* Remember value for tc_gen_reloc. */
9296 fixP->fx_addnumber = value;
9297 /* Clear out the frag for now. */
9298 value = 0;
9299 }
9300#endif
3e73aa7c
JH		 9301 else if (use_rela_relocations)
9302 {
9303 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9304 /* Remember value for tc_gen_reloc. */
9305 fixP->fx_addnumber = value;
3e73aa7c
JH		 9306 value = 0;
9307 }
f86103b7 9308
94f592af 9309 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9310}
252b5132 9311\f
252b5132 9312char *
499ac353 9313md_atof (int type, char *litP, int *sizeP)
252b5132 9314{
499ac353
NC		 9315 /* This outputs the LITTLENUMs in REVERSE order;
9316 in accord with the bigendian 386. */
9317 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9318}
9319\f
2d545b82 9320static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9321
252b5132 9322static char *
e3bb37b5 9323output_invalid (int c)
252b5132 9324{
3882b010 9325 if (ISPRINT (c))
f9f21a03
L		 9326 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9327 "'%c'", c);
252b5132 9328 else
f9f21a03 9329 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9330 "(0x%x)", (unsigned char) c);
252b5132
RH		 9331 return output_invalid_buf;
9332}
9333
af6bdddf 9334/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9335
9336static const reg_entry *
4d1bb795 9337parse_real_register (char *reg_string, char **end_op)
252b5132 9338{
af6bdddf
AM		 9339 char *s = reg_string;
9340 char *p;
252b5132
RH		 9341 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9342 const reg_entry *r;
9343
9344 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9345 if (*s == REGISTER_PREFIX)
9346 ++s;
9347
9348 if (is_space_char (*s))
9349 ++s;
9350
9351 p = reg_name_given;
af6bdddf 9352 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9353 {
9354 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9355 return (const reg_entry *) NULL;
9356 s++;
252b5132
RH		 9357 }
9358
6588847e
DN		 9359 /* For naked regs, make sure that we are not dealing with an identifier.
9360 This prevents confusing an identifier like `eax_var' with register
9361 `eax'. */
9362 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9363 return (const reg_entry *) NULL;
9364
af6bdddf 9365 *end_op = s;
252b5132
RH		 9366
9367 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9368
5f47d35b 9369 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9370 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9371 {
5f47d35b
AM		 9372 if (is_space_char (*s))
9373 ++s;
9374 if (*s == '(')
9375 {
af6bdddf 9376 ++s;
5f47d35b
AM		 9377 if (is_space_char (*s))
9378 ++s;
9379 if (*s >= '0' && *s <= '7')
9380 {
db557034 9381 int fpr = *s - '0';
af6bdddf 9382 ++s;
5f47d35b
AM		 9383 if (is_space_char (*s))
9384 ++s;
9385 if (*s == ')')
9386 {
9387 *end_op = s + 1;
1e9cc1c2 9388 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9389 know (r);
9390 return r + fpr;
5f47d35b 9391 }
5f47d35b 9392 }
47926f60 9393 /* We have "%st(" then garbage. */
5f47d35b
AM		 9394 return (const reg_entry *) NULL;
9395 }
9396 }
9397
a60de03c
JB		 9398 if (r == NULL || allow_pseudo_reg)
9399 return r;
9400
0dfbf9d7 9401 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9402 return (const reg_entry *) NULL;
9403
192dc9c6
JB		 9404 if ((r->reg_type.bitfield.reg32
9405 || r->reg_type.bitfield.sreg3
9406 || r->reg_type.bitfield.control
9407 || r->reg_type.bitfield.debug
9408 || r->reg_type.bitfield.test)
9409 && !cpu_arch_flags.bitfield.cpui386)
9410 return (const reg_entry *) NULL;
9411
309d3373
JB		 9412 if (r->reg_type.bitfield.floatreg
9413 && !cpu_arch_flags.bitfield.cpu8087
9414 && !cpu_arch_flags.bitfield.cpu287
9415 && !cpu_arch_flags.bitfield.cpu387)
9416 return (const reg_entry *) NULL;
9417
192dc9c6
JB		 9418 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9419 return (const reg_entry *) NULL;
9420
9421 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9422 return (const reg_entry *) NULL;
9423
40f12533
L		 9424 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9425 return (const reg_entry *) NULL;
9426
43234a1e
L		 9427 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9428 && !cpu_arch_flags.bitfield.cpuavx512f)
9429 return (const reg_entry *) NULL;
9430
db51cc60 9431 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9432 if (!allow_index_reg
db51cc60
L		 9433 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9434 return (const reg_entry *) NULL;
9435
43234a1e
L		 9436 /* Upper 16 vector register is only available with VREX in 64bit
9437 mode. */
9438 if ((r->reg_flags & RegVRex))
9439 {
9440 if (!cpu_arch_flags.bitfield.cpuvrex
9441 || flag_code != CODE_64BIT)
9442 return (const reg_entry *) NULL;
9443
9444 i.need_vrex = 1;
9445 }
9446
a60de03c
JB		 9447 if (((r->reg_flags & (RegRex64 | RegRex))
9448 || r->reg_type.bitfield.reg64)
40fb9820 9449 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9450 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9451 && flag_code != CODE_64BIT)
20f0a1fc 9452 return (const reg_entry *) NULL;
1ae00879 9453
b7240065
JB		 9454 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9455 return (const reg_entry *) NULL;
9456
252b5132
RH		 9457 return r;
9458}
4d1bb795
JB		 9459
9460/* REG_STRING starts *before* REGISTER_PREFIX. */
9461
9462static const reg_entry *
9463parse_register (char *reg_string, char **end_op)
9464{
9465 const reg_entry *r;
9466
9467 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9468 r = parse_real_register (reg_string, end_op);
9469 else
9470 r = NULL;
9471 if (!r)
9472 {
9473 char *save = input_line_pointer;
9474 char c;
9475 symbolS *symbolP;
9476
9477 input_line_pointer = reg_string;
d02603dc 9478 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9479 symbolP = symbol_find (reg_string);
9480 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9481 {
9482 const expressionS *e = symbol_get_value_expression (symbolP);
9483
0398aac5 9484 know (e->X_op == O_register);
4eed87de 9485 know (e->X_add_number >= 0
c3fe08fa 9486 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9487 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9488 if ((r->reg_flags & RegVRex))
9489 i.need_vrex = 1;
4d1bb795
JB		 9490 *end_op = input_line_pointer;
9491 }
9492 *input_line_pointer = c;
9493 input_line_pointer = save;
9494 }
9495 return r;
9496}
9497
9498int
9499i386_parse_name (char *name, expressionS *e, char *nextcharP)
9500{
9501 const reg_entry *r;
9502 char *end = input_line_pointer;
9503
9504 *end = *nextcharP;
9505 r = parse_register (name, &input_line_pointer);
9506 if (r && end <= input_line_pointer)
9507 {
9508 *nextcharP = *input_line_pointer;
9509 *input_line_pointer = 0;
9510 e->X_op = O_register;
9511 e->X_add_number = r - i386_regtab;
9512 return 1;
9513 }
9514 input_line_pointer = end;
9515 *end = 0;
ee86248c 9516 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9517}
9518
9519void
9520md_operand (expressionS *e)
9521{
ee86248c
JB		 9522 char *end;
9523 const reg_entry *r;
4d1bb795 9524
ee86248c
JB		 9525 switch (*input_line_pointer)
9526 {
9527 case REGISTER_PREFIX:
9528 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9529 if (r)
9530 {
9531 e->X_op = O_register;
9532 e->X_add_number = r - i386_regtab;
9533 input_line_pointer = end;
9534 }
ee86248c
JB		 9535 break;
9536
9537 case '[':
9c2799c2 9538 gas_assert (intel_syntax);
ee86248c
JB		 9539 end = input_line_pointer++;
9540 expression (e);
9541 if (*input_line_pointer == ']')
9542 {
9543 ++input_line_pointer;
9544 e->X_op_symbol = make_expr_symbol (e);
9545 e->X_add_symbol = NULL;
9546 e->X_add_number = 0;
9547 e->X_op = O_index;
9548 }
9549 else
9550 {
9551 e->X_op = O_absent;
9552 input_line_pointer = end;
9553 }
9554 break;
4d1bb795
JB		 9555 }
9556}
9557
252b5132 9558\f
4cc782b5 9559#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9560const char *md_shortopts = "kVQ:sqn";
252b5132 9561#else
12b55ccc 9562const char *md_shortopts = "qn";
252b5132 9563#endif
6e0b89ee 9564
3e73aa7c 9565#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9566#define OPTION_64 (OPTION_MD_BASE + 1)
9567#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9568#define OPTION_MARCH (OPTION_MD_BASE + 3)
9569#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9570#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9571#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9572#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9573#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9574#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9575#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9576#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9577#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9578#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9579#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9580#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9581#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9582#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9583#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9584#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9585#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9586#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9587#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9588#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
b3b91714 9589
99ad8390
NC		 9590struct option md_longopts[] =
9591{
3e73aa7c 9592 {"32", no_argument, NULL, OPTION_32},
321098a5 9593#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9594 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9595 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9596#endif
9597#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9598 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9599 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9600#endif
b3b91714 9601 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9602 {"march", required_argument, NULL, OPTION_MARCH},
9603 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9604 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9605 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9606 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9607 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9608 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9609 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9610 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9611 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9612 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9613 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9614 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9615 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9616# if defined (TE_PE) || defined (TE_PEP)
9617 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9618#endif
a5094208 9619 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9620 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9621 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9622 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9623 {NULL, no_argument, NULL, 0}
9624};
9625size_t md_longopts_size = sizeof (md_longopts);
9626
9627int
9103f4f4 9628md_parse_option (int c, char *arg)
252b5132 9629{
91d6fa6a 9630 unsigned int j;
6305a203 9631 char *arch, *next;
9103f4f4 9632
252b5132
RH		 9633 switch (c)
9634 {
12b55ccc
L		 9635 case 'n':
9636 optimize_align_code = 0;
9637 break;
9638
a38cf1db
AM		 9639 case 'q':
9640 quiet_warnings = 1;
252b5132
RH		 9641 break;
9642
9643#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9644 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9645 should be emitted or not. FIXME: Not implemented. */
9646 case 'Q':
252b5132
RH		 9647 break;
9648
9649 /* -V: SVR4 argument to print version ID. */
9650 case 'V':
9651 print_version_id ();
9652 break;
9653
a38cf1db
AM		 9654 /* -k: Ignore for FreeBSD compatibility. */
9655 case 'k':
252b5132 9656 break;
4cc782b5
ILT		 9657
9658 case 's':
9659 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9660 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9661 break;
8dcea932
L		 9662
9663 case OPTION_MSHARED:
9664 shared = 1;
9665 break;
99ad8390 9666#endif
321098a5 9667#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9668 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9669 case OPTION_64:
9670 {
9671 const char **list, **l;
9672
3e73aa7c
JH		 9673 list = bfd_target_list ();
9674 for (l = list; *l != NULL; l++)
8620418b 9675 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9676 || strcmp (*l, "coff-x86-64") == 0
9677 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9678 || strcmp (*l, "pei-x86-64") == 0
9679 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9680 {
9681 default_arch = "x86_64";
9682 break;
9683 }
3e73aa7c 9684 if (*l == NULL)
2b5d6a91 9685 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9686 free (list);
9687 }
9688 break;
9689#endif
252b5132 9690
351f65ca 9691#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9692 case OPTION_X32:
351f65ca
L		 9693 if (IS_ELF)
9694 {
9695 const char **list, **l;
9696
9697 list = bfd_target_list ();
9698 for (l = list; *l != NULL; l++)
9699 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9700 {
9701 default_arch = "x86_64:32";
9702 break;
9703 }
9704 if (*l == NULL)
2b5d6a91 9705 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9706 free (list);
9707 }
9708 else
9709 as_fatal (_("32bit x86_64 is only supported for ELF"));
9710 break;
9711#endif
9712
6e0b89ee
AM		 9713 case OPTION_32:
9714 default_arch = "i386";
9715 break;
9716
b3b91714
AM		 9717 case OPTION_DIVIDE:
9718#ifdef SVR4_COMMENT_CHARS
9719 {
9720 char *n, *t;
9721 const char *s;
9722
9723 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9724 t = n;
9725 for (s = i386_comment_chars; *s != '\0'; s++)
9726 if (*s != '/')
9727 *t++ = *s;
9728 *t = '\0';
9729 i386_comment_chars = n;
9730 }
9731#endif
9732 break;
9733
9103f4f4 9734 case OPTION_MARCH:
6305a203
L		 9735 arch = xstrdup (arg);
9736 do
9103f4f4 9737 {
6305a203 9738 if (*arch == '.')
2b5d6a91 9739 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9740 next = strchr (arch, '+');
9741 if (next)
9742 *next++ = '\0';
91d6fa6a 9743 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9744 {
91d6fa6a 9745 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9746 {
6305a203 9747 /* Processor. */
1ded5609
JB		 9748 if (! cpu_arch[j].flags.bitfield.cpui386)
9749 continue;
9750
91d6fa6a 9751 cpu_arch_name = cpu_arch[j].name;
6305a203 9752 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9753 cpu_arch_flags = cpu_arch[j].flags;
9754 cpu_arch_isa = cpu_arch[j].type;
9755 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9756 if (!cpu_arch_tune_set)
9757 {
9758 cpu_arch_tune = cpu_arch_isa;
9759 cpu_arch_tune_flags = cpu_arch_isa_flags;
9760 }
9761 break;
9762 }
91d6fa6a
NC		 9763 else if (*cpu_arch [j].name == '.'
9764 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9765 {
9766 /* ISA entension. */
9767 i386_cpu_flags flags;
309d3373 9768
49021df2 9769 if (!cpu_arch[j].negated)
309d3373 9770 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9771 cpu_arch[j].flags);
309d3373
JB		 9772 else
9773 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9774 cpu_arch[j].flags);
81486035
L		 9775
9776 if (!valid_iamcu_cpu_flags (&flags))
9777 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9778 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9779 {
9780 if (cpu_sub_arch_name)
9781 {
9782 char *name = cpu_sub_arch_name;
9783 cpu_sub_arch_name = concat (name,
91d6fa6a 9784 cpu_arch[j].name,
1bf57e9f 9785 (const char *) NULL);
6305a203
L		 9786 free (name);
9787 }
9788 else
91d6fa6a 9789 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9790 cpu_arch_flags = flags;
a586129e 9791 cpu_arch_isa_flags = flags;
6305a203
L		 9792 }
9793 break;
ccc9c027 9794 }
9103f4f4 9795 }
6305a203 9796
91d6fa6a 9797 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9798 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9799
9800 arch = next;
9103f4f4 9801 }
6305a203 9802 while (next != NULL );
9103f4f4
L		 9803 break;
9804
9805 case OPTION_MTUNE:
9806 if (*arg == '.')
2b5d6a91 9807 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9808 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9809 {
91d6fa6a 9810 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9811 {
ccc9c027 9812 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9813 cpu_arch_tune = cpu_arch [j].type;
9814 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9815 break;
9816 }
9817 }
91d6fa6a 9818 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9819 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9820 break;
9821
1efbbeb4
L		 9822 case OPTION_MMNEMONIC:
9823 if (strcasecmp (arg, "att") == 0)
9824 intel_mnemonic = 0;
9825 else if (strcasecmp (arg, "intel") == 0)
9826 intel_mnemonic = 1;
9827 else
2b5d6a91 9828 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9829 break;
9830
9831 case OPTION_MSYNTAX:
9832 if (strcasecmp (arg, "att") == 0)
9833 intel_syntax = 0;
9834 else if (strcasecmp (arg, "intel") == 0)
9835 intel_syntax = 1;
9836 else
2b5d6a91 9837 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9838 break;
9839
9840 case OPTION_MINDEX_REG:
9841 allow_index_reg = 1;
9842 break;
9843
9844 case OPTION_MNAKED_REG:
9845 allow_naked_reg = 1;
9846 break;
9847
9848 case OPTION_MOLD_GCC:
9849 old_gcc = 1;
1efbbeb4
L		 9850 break;
9851
c0f3af97
L		 9852 case OPTION_MSSE2AVX:
9853 sse2avx = 1;
9854 break;
9855
daf50ae7
L		 9856 case OPTION_MSSE_CHECK:
9857 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9858 sse_check = check_error;
daf50ae7 9859 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9860 sse_check = check_warning;
daf50ae7 9861 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9862 sse_check = check_none;
daf50ae7 9863 else
2b5d6a91 9864 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9865 break;
9866
7bab8ab5
JB		 9867 case OPTION_MOPERAND_CHECK:
9868 if (strcasecmp (arg, "error") == 0)
9869 operand_check = check_error;
9870 else if (strcasecmp (arg, "warning") == 0)
9871 operand_check = check_warning;
9872 else if (strcasecmp (arg, "none") == 0)
9873 operand_check = check_none;
9874 else
9875 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9876 break;
9877
539f890d
L		 9878 case OPTION_MAVXSCALAR:
9879 if (strcasecmp (arg, "128") == 0)
9880 avxscalar = vex128;
9881 else if (strcasecmp (arg, "256") == 0)
9882 avxscalar = vex256;
9883 else
2b5d6a91 9884 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9885 break;
9886
7e8b059b
L		 9887 case OPTION_MADD_BND_PREFIX:
9888 add_bnd_prefix = 1;
9889 break;
9890
43234a1e
L		 9891 case OPTION_MEVEXLIG:
9892 if (strcmp (arg, "128") == 0)
9893 evexlig = evexl128;
9894 else if (strcmp (arg, "256") == 0)
9895 evexlig = evexl256;
9896 else if (strcmp (arg, "512") == 0)
9897 evexlig = evexl512;
9898 else
9899 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9900 break;
9901
d3d3c6db
IT		 9902 case OPTION_MEVEXRCIG:
9903 if (strcmp (arg, "rne") == 0)
9904 evexrcig = rne;
9905 else if (strcmp (arg, "rd") == 0)
9906 evexrcig = rd;
9907 else if (strcmp (arg, "ru") == 0)
9908 evexrcig = ru;
9909 else if (strcmp (arg, "rz") == 0)
9910 evexrcig = rz;
9911 else
9912 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9913 break;
9914
43234a1e
L		 9915 case OPTION_MEVEXWIG:
9916 if (strcmp (arg, "0") == 0)
9917 evexwig = evexw0;
9918 else if (strcmp (arg, "1") == 0)
9919 evexwig = evexw1;
9920 else
9921 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9922 break;
9923
167ad85b
TG		 9924# if defined (TE_PE) || defined (TE_PEP)
9925 case OPTION_MBIG_OBJ:
9926 use_big_obj = 1;
9927 break;
9928#endif
9929
a5094208 9930 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9931 if (strcasecmp (arg, "yes") == 0)
9932 omit_lock_prefix = 1;
9933 else if (strcasecmp (arg, "no") == 0)
9934 omit_lock_prefix = 0;
9935 else
9936 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9937 break;
9938
5db04b09
L		 9939 case OPTION_MAMD64:
9940 cpu_arch_flags.bitfield.cpuamd64 = 1;
9941 cpu_arch_flags.bitfield.cpuintel64 = 0;
9942 cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
9943 cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
9944 break;
9945
9946 case OPTION_MINTEL64:
9947 cpu_arch_flags.bitfield.cpuamd64 = 0;
9948 cpu_arch_flags.bitfield.cpuintel64 = 1;
9949 cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
9950 cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
9951 break;
9952
252b5132
RH		 9953 default:
9954 return 0;
9955 }
9956 return 1;
9957}
9958
8a2c8fef
L		 9959#define MESSAGE_TEMPLATE \
9960" "
9961
9962static void
1ded5609 9963show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9964{
9965 static char message[] = MESSAGE_TEMPLATE;
9966 char *start = message + 27;
9967 char *p;
9968 int size = sizeof (MESSAGE_TEMPLATE);
9969 int left;
9970 const char *name;
9971 int len;
9972 unsigned int j;
9973
9974 p = start;
9975 left = size - (start - message);
9976 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9977 {
9978 /* Should it be skipped? */
9979 if (cpu_arch [j].skip)
9980 continue;
9981
9982 name = cpu_arch [j].name;
9983 len = cpu_arch [j].len;
9984 if (*name == '.')
9985 {
9986 /* It is an extension. Skip if we aren't asked to show it. */
9987 if (ext)
9988 {
9989 name++;
9990 len--;
9991 }
9992 else
9993 continue;
9994 }
9995 else if (ext)
9996 {
9997 /* It is an processor. Skip if we show only extension. */
9998 continue;
9999 }
1ded5609
JB		 10000 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10001 {
10002 /* It is an impossible processor - skip. */
10003 continue;
10004 }
8a2c8fef
L		 10005
10006 /* Reserve 2 spaces for ", " or ",\0" */
10007 left -= len + 2;
10008
10009 /* Check if there is any room. */
10010 if (left >= 0)
10011 {
10012 if (p != start)
10013 {
10014 *p++ = ',';
10015 *p++ = ' ';
10016 }
10017 p = mempcpy (p, name, len);
10018 }
10019 else
10020 {
10021 /* Output the current message now and start a new one. */
10022 *p++ = ',';
10023 *p = '\0';
10024 fprintf (stream, "%s\n", message);
10025 p = start;
10026 left = size - (start - message) - len - 2;
8d63c93e 10027
8a2c8fef
L		 10028 gas_assert (left >= 0);
10029
10030 p = mempcpy (p, name, len);
10031 }
10032 }
10033
10034 *p = '\0';
10035 fprintf (stream, "%s\n", message);
10036}
10037
252b5132 10038void
8a2c8fef 10039md_show_usage (FILE *stream)
252b5132 10040{
4cc782b5
ILT		 10041#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10042 fprintf (stream, _("\
a38cf1db
AM		 10043 -Q ignored\n\
10044 -V print assembler version number\n\
b3b91714
AM		 10045 -k ignored\n"));
10046#endif
10047 fprintf (stream, _("\
12b55ccc 10048 -n Do not optimize code alignment\n\
b3b91714
AM		 10049 -q quieten some warnings\n"));
10050#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10051 fprintf (stream, _("\
a38cf1db 10052 -s ignored\n"));
b3b91714 10053#endif
321098a5
L		 10054#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10055 || defined (TE_PE) || defined (TE_PEP))
751d281c 10056 fprintf (stream, _("\
570561f7 10057 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10058#endif
b3b91714
AM		 10059#ifdef SVR4_COMMENT_CHARS
10060 fprintf (stream, _("\
10061 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10062#else
10063 fprintf (stream, _("\
b3b91714 10064 --divide ignored\n"));
4cc782b5 10065#endif
9103f4f4 10066 fprintf (stream, _("\
6305a203 10067 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10068 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10069 show_arch (stream, 0, 1);
8a2c8fef
L		 10070 fprintf (stream, _("\
10071 EXTENSION is combination of:\n"));
1ded5609 10072 show_arch (stream, 1, 0);
6305a203 10073 fprintf (stream, _("\
8a2c8fef 10074 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10075 show_arch (stream, 0, 0);
ba104c83 10076 fprintf (stream, _("\
c0f3af97
L		 10077 -msse2avx encode SSE instructions with VEX prefix\n"));
10078 fprintf (stream, _("\
daf50ae7
L		 10079 -msse-check=[none|error|warning]\n\
10080 check SSE instructions\n"));
10081 fprintf (stream, _("\
7bab8ab5
JB		 10082 -moperand-check=[none|error|warning]\n\
10083 check operand combinations for validity\n"));
10084 fprintf (stream, _("\
539f890d
L		 10085 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10086 length\n"));
10087 fprintf (stream, _("\
43234a1e
L		 10088 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10089 length\n"));
10090 fprintf (stream, _("\
10091 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10092 for EVEX.W bit ignored instructions\n"));
10093 fprintf (stream, _("\
d3d3c6db
IT		 10094 -mevexrcig=[rne|rd|ru|rz]\n\
10095 encode EVEX instructions with specific EVEX.RC value\n\
10096 for SAE-only ignored instructions\n"));
10097 fprintf (stream, _("\
ba104c83
L		 10098 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10099 fprintf (stream, _("\
10100 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10101 fprintf (stream, _("\
10102 -mindex-reg support pseudo index registers\n"));
10103 fprintf (stream, _("\
10104 -mnaked-reg don't require `%%' prefix for registers\n"));
10105 fprintf (stream, _("\
10106 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10107 fprintf (stream, _("\
10108 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10109 fprintf (stream, _("\
10110 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10111# if defined (TE_PE) || defined (TE_PEP)
10112 fprintf (stream, _("\
10113 -mbig-obj generate big object files\n"));
10114#endif
d022bddd
IT		 10115 fprintf (stream, _("\
10116 -momit-lock-prefix=[no|yes]\n\
10117 strip all lock prefixes\n"));
5db04b09
L		 10118 fprintf (stream, _("\
10119 -mamd64 accept only AMD64 ISA\n"));
10120 fprintf (stream, _("\
10121 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10122}
10123
3e73aa7c 10124#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10125 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10126 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10127
10128/* Pick the target format to use. */
10129
47926f60 10130const char *
e3bb37b5 10131i386_target_format (void)
252b5132 10132{
351f65ca
L		 10133 if (!strncmp (default_arch, "x86_64", 6))
10134 {
10135 update_code_flag (CODE_64BIT, 1);
10136 if (default_arch[6] == '\0')
7f56bc95 10137 x86_elf_abi = X86_64_ABI;
351f65ca 10138 else
7f56bc95 10139 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10140 }
3e73aa7c 10141 else if (!strcmp (default_arch, "i386"))
78f12dd3 10142 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10143 else if (!strcmp (default_arch, "iamcu"))
10144 {
10145 update_code_flag (CODE_32BIT, 1);
10146 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10147 {
10148 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10149 cpu_arch_name = "iamcu";
10150 cpu_sub_arch_name = NULL;
10151 cpu_arch_flags = iamcu_flags;
10152 cpu_arch_isa = PROCESSOR_IAMCU;
10153 cpu_arch_isa_flags = iamcu_flags;
10154 if (!cpu_arch_tune_set)
10155 {
10156 cpu_arch_tune = cpu_arch_isa;
10157 cpu_arch_tune_flags = cpu_arch_isa_flags;
10158 }
10159 }
10160 else
10161 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10162 cpu_arch_name);
10163 }
3e73aa7c 10164 else
2b5d6a91 10165 as_fatal (_("unknown architecture"));
89507696
JB		 10166
10167 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10168 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10169 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10170 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10171
252b5132
RH		 10172 switch (OUTPUT_FLAVOR)
10173 {
9384f2ff 10174#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10175 case bfd_target_aout_flavour:
47926f60 10176 return AOUT_TARGET_FORMAT;
4c63da97 10177#endif
9384f2ff
AM		 10178#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10179# if defined (TE_PE) || defined (TE_PEP)
10180 case bfd_target_coff_flavour:
167ad85b
TG		 10181 if (flag_code == CODE_64BIT)
10182 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10183 else
10184 return "pe-i386";
9384f2ff 10185# elif defined (TE_GO32)
0561d57c
JK		 10186 case bfd_target_coff_flavour:
10187 return "coff-go32";
9384f2ff 10188# else
252b5132
RH		 10189 case bfd_target_coff_flavour:
10190 return "coff-i386";
9384f2ff 10191# endif
4c63da97 10192#endif
3e73aa7c 10193#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10194 case bfd_target_elf_flavour:
3e73aa7c 10195 {
351f65ca
L		 10196 const char *format;
10197
10198 switch (x86_elf_abi)
4fa24527 10199 {
351f65ca
L		 10200 default:
10201 format = ELF_TARGET_FORMAT;
10202 break;
7f56bc95 10203 case X86_64_ABI:
351f65ca 10204 use_rela_relocations = 1;
4fa24527 10205 object_64bit = 1;
351f65ca
L		 10206 format = ELF_TARGET_FORMAT64;
10207 break;
7f56bc95 10208 case X86_64_X32_ABI:
4fa24527 10209 use_rela_relocations = 1;
351f65ca 10210 object_64bit = 1;
862be3fb 10211 disallow_64bit_reloc = 1;
351f65ca
L		 10212 format = ELF_TARGET_FORMAT32;
10213 break;
4fa24527 10214 }
3632d14b 10215 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10216 {
7f56bc95 10217 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10218 as_fatal (_("Intel L1OM is 64bit only"));
10219 return ELF_TARGET_L1OM_FORMAT;
10220 }
b49f93f6 10221 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10222 {
10223 if (x86_elf_abi != X86_64_ABI)
10224 as_fatal (_("Intel K1OM is 64bit only"));
10225 return ELF_TARGET_K1OM_FORMAT;
10226 }
81486035
L		 10227 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10228 {
10229 if (x86_elf_abi != I386_ABI)
10230 as_fatal (_("Intel MCU is 32bit only"));
10231 return ELF_TARGET_IAMCU_FORMAT;
10232 }
8a9036a4 10233 else
351f65ca 10234 return format;
3e73aa7c 10235 }
e57f8c65
TG		 10236#endif
10237#if defined (OBJ_MACH_O)
10238 case bfd_target_mach_o_flavour:
d382c579
TG		 10239 if (flag_code == CODE_64BIT)
10240 {
10241 use_rela_relocations = 1;
10242 object_64bit = 1;
10243 return "mach-o-x86-64";
10244 }
10245 else
10246 return "mach-o-i386";
4c63da97 10247#endif
252b5132
RH		 10248 default:
10249 abort ();
10250 return NULL;
10251 }
10252}
10253
47926f60 10254#endif /* OBJ_MAYBE_ more than one */
252b5132 10255\f
252b5132 10256symbolS *
7016a5d5 10257md_undefined_symbol (char *name)
252b5132 10258{
18dc2407
ILT		 10259 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10260 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10261 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10262 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10263 {
10264 if (!GOT_symbol)
10265 {
10266 if (symbol_find (name))
10267 as_bad (_("GOT already in symbol table"));
10268 GOT_symbol = symbol_new (name, undefined_section,
10269 (valueT) 0, &zero_address_frag);
10270 };
10271 return GOT_symbol;
10272 }
252b5132
RH		 10273 return 0;
10274}
10275
10276/* Round up a section size to the appropriate boundary. */
47926f60 10277
252b5132 10278valueT
7016a5d5 10279md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10280{
4c63da97
AM		 10281#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10282 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10283 {
10284 /* For a.out, force the section size to be aligned. If we don't do
10285 this, BFD will align it for us, but it will not write out the
10286 final bytes of the section. This may be a bug in BFD, but it is
10287 easier to fix it here since that is how the other a.out targets
10288 work. */
10289 int align;
10290
10291 align = bfd_get_section_alignment (stdoutput, segment);
10292 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10293 }
252b5132
RH		 10294#endif
10295
10296 return size;
10297}
10298
10299/* On the i386, PC-relative offsets are relative to the start of the
10300 next instruction. That is, the address of the offset, plus its
10301 size, since the offset is always the last part of the insn. */
10302
10303long
e3bb37b5 10304md_pcrel_from (fixS *fixP)
252b5132
RH		 10305{
10306 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10307}
10308
10309#ifndef I386COFF
10310
10311static void
e3bb37b5 10312s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10313{
29b0f896 10314 int temp;
252b5132 10315
8a75718c
JB		 10316#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10317 if (IS_ELF)
10318 obj_elf_section_change_hook ();
10319#endif
252b5132
RH		 10320 temp = get_absolute_expression ();
10321 subseg_set (bss_section, (subsegT) temp);
10322 demand_empty_rest_of_line ();
10323}
10324
10325#endif
10326
252b5132 10327void
e3bb37b5 10328i386_validate_fix (fixS *fixp)
252b5132
RH		 10329{
10330 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10331 {
23df1078
JH		 10332 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10333 {
4fa24527 10334 if (!object_64bit)
23df1078
JH		 10335 abort ();
10336 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10337 }
10338 else
10339 {
4fa24527 10340 if (!object_64bit)
d6ab8113
JB		 10341 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10342 else
10343 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10344 }
252b5132
RH		 10345 fixp->fx_subsy = 0;
10346 }
10347}
10348
252b5132 10349arelent *
7016a5d5 10350tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10351{
10352 arelent *rel;
10353 bfd_reloc_code_real_type code;
10354
10355 switch (fixp->fx_r_type)
10356 {
8ce3d284 10357#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10358 case BFD_RELOC_SIZE32:
10359 case BFD_RELOC_SIZE64:
10360 if (S_IS_DEFINED (fixp->fx_addsy)
10361 && !S_IS_EXTERNAL (fixp->fx_addsy))
10362 {
10363 /* Resolve size relocation against local symbol to size of
10364 the symbol plus addend. */
10365 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10366 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10367 && !fits_in_unsigned_long (value))
10368 as_bad_where (fixp->fx_file, fixp->fx_line,
10369 _("symbol size computation overflow"));
10370 fixp->fx_addsy = NULL;
10371 fixp->fx_subsy = NULL;
10372 md_apply_fix (fixp, (valueT *) &value, NULL);
10373 return NULL;
10374 }
8ce3d284 10375#endif
8fd4256d 10376
3e73aa7c
JH		 10377 case BFD_RELOC_X86_64_PLT32:
10378 case BFD_RELOC_X86_64_GOT32:
10379 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10380 case BFD_RELOC_386_PLT32:
10381 case BFD_RELOC_386_GOT32:
10382 case BFD_RELOC_386_GOTOFF:
10383 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10384 case BFD_RELOC_386_TLS_GD:
10385 case BFD_RELOC_386_TLS_LDM:
10386 case BFD_RELOC_386_TLS_LDO_32:
10387 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10388 case BFD_RELOC_386_TLS_IE:
10389 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10390 case BFD_RELOC_386_TLS_LE_32:
10391 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10392 case BFD_RELOC_386_TLS_GOTDESC:
10393 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10394 case BFD_RELOC_X86_64_TLSGD:
10395 case BFD_RELOC_X86_64_TLSLD:
10396 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10397 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10398 case BFD_RELOC_X86_64_GOTTPOFF:
10399 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10400 case BFD_RELOC_X86_64_TPOFF64:
10401 case BFD_RELOC_X86_64_GOTOFF64:
10402 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10403 case BFD_RELOC_X86_64_GOT64:
10404 case BFD_RELOC_X86_64_GOTPCREL64:
10405 case BFD_RELOC_X86_64_GOTPC64:
10406 case BFD_RELOC_X86_64_GOTPLT64:
10407 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10408 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10409 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10410 case BFD_RELOC_RVA:
10411 case BFD_RELOC_VTABLE_ENTRY:
10412 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10413#ifdef TE_PE
10414 case BFD_RELOC_32_SECREL:
10415#endif
252b5132
RH		 10416 code = fixp->fx_r_type;
10417 break;
dbbaec26
L		 10418 case BFD_RELOC_X86_64_32S:
10419 if (!fixp->fx_pcrel)
10420 {
10421 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10422 code = fixp->fx_r_type;
10423 break;
10424 }
252b5132 10425 default:
93382f6d 10426 if (fixp->fx_pcrel)
252b5132 10427 {
93382f6d
AM		 10428 switch (fixp->fx_size)
10429 {
10430 default:
b091f402
AM		 10431 as_bad_where (fixp->fx_file, fixp->fx_line,
10432 _("can not do %d byte pc-relative relocation"),
10433 fixp->fx_size);
93382f6d
AM		 10434 code = BFD_RELOC_32_PCREL;
10435 break;
10436 case 1: code = BFD_RELOC_8_PCREL; break;
10437 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10438 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10439#ifdef BFD64
10440 case 8: code = BFD_RELOC_64_PCREL; break;
10441#endif
93382f6d
AM		 10442 }
10443 }
10444 else
10445 {
10446 switch (fixp->fx_size)
10447 {
10448 default:
b091f402
AM		 10449 as_bad_where (fixp->fx_file, fixp->fx_line,
10450 _("can not do %d byte relocation"),
10451 fixp->fx_size);
93382f6d
AM		 10452 code = BFD_RELOC_32;
10453 break;
10454 case 1: code = BFD_RELOC_8; break;
10455 case 2: code = BFD_RELOC_16; break;
10456 case 4: code = BFD_RELOC_32; break;
937149dd 10457#ifdef BFD64
3e73aa7c 10458 case 8: code = BFD_RELOC_64; break;
937149dd 10459#endif
93382f6d 10460 }
252b5132
RH		 10461 }
10462 break;
10463 }
252b5132 10464
d182319b
JB		 10465 if ((code == BFD_RELOC_32
10466 || code == BFD_RELOC_32_PCREL
10467 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10468 && GOT_symbol
10469 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10470 {
4fa24527 10471 if (!object_64bit)
d6ab8113
JB		 10472 code = BFD_RELOC_386_GOTPC;
10473 else
10474 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10475 }
7b81dfbb
AJ		 10476 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10477 && GOT_symbol
10478 && fixp->fx_addsy == GOT_symbol)
10479 {
10480 code = BFD_RELOC_X86_64_GOTPC64;
10481 }
252b5132
RH		 10482
10483 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10484 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10485 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10486
10487 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10488
3e73aa7c
JH		 10489 if (!use_rela_relocations)
10490 {
10491 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10492 vtable entry to be used in the relocation's section offset. */
10493 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10494 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10495#if defined (OBJ_COFF) && defined (TE_PE)
10496 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10497 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10498 else
10499#endif
c6682705 10500 rel->addend = 0;
3e73aa7c
JH		 10501 }
10502 /* Use the rela in 64bit mode. */
252b5132 10503 else
3e73aa7c 10504 {
862be3fb
L		 10505 if (disallow_64bit_reloc)
10506 switch (code)
10507 {
862be3fb
L		 10508 case BFD_RELOC_X86_64_DTPOFF64:
10509 case BFD_RELOC_X86_64_TPOFF64:
10510 case BFD_RELOC_64_PCREL:
10511 case BFD_RELOC_X86_64_GOTOFF64:
10512 case BFD_RELOC_X86_64_GOT64:
10513 case BFD_RELOC_X86_64_GOTPCREL64:
10514 case BFD_RELOC_X86_64_GOTPC64:
10515 case BFD_RELOC_X86_64_GOTPLT64:
10516 case BFD_RELOC_X86_64_PLTOFF64:
10517 as_bad_where (fixp->fx_file, fixp->fx_line,
10518 _("cannot represent relocation type %s in x32 mode"),
10519 bfd_get_reloc_code_name (code));
10520 break;
10521 default:
10522 break;
10523 }
10524
062cd5e7
AS		 10525 if (!fixp->fx_pcrel)
10526 rel->addend = fixp->fx_offset;
10527 else
10528 switch (code)
10529 {
10530 case BFD_RELOC_X86_64_PLT32:
10531 case BFD_RELOC_X86_64_GOT32:
10532 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10533 case BFD_RELOC_X86_64_TLSGD:
10534 case BFD_RELOC_X86_64_TLSLD:
10535 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10536 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10537 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10538 rel->addend = fixp->fx_offset - fixp->fx_size;
10539 break;
10540 default:
10541 rel->addend = (section->vma
10542 - fixp->fx_size
10543 + fixp->fx_addnumber
10544 + md_pcrel_from (fixp));
10545 break;
10546 }
3e73aa7c
JH		 10547 }
10548
252b5132
RH		 10549 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10550 if (rel->howto == NULL)
10551 {
10552 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10553 _("cannot represent relocation type %s"),
252b5132
RH		 10554 bfd_get_reloc_code_name (code));
10555 /* Set howto to a garbage value so that we can keep going. */
10556 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10557 gas_assert (rel->howto != NULL);
252b5132
RH		 10558 }
10559
10560 return rel;
10561}
10562
ee86248c 10563#include "tc-i386-intel.c"
54cfded0 10564
a60de03c
JB		 10565void
10566tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10567{
a60de03c
JB		 10568 int saved_naked_reg;
10569 char saved_register_dot;
54cfded0 10570
a60de03c
JB		 10571 saved_naked_reg = allow_naked_reg;
10572 allow_naked_reg = 1;
10573 saved_register_dot = register_chars['.'];
10574 register_chars['.'] = '.';
10575 allow_pseudo_reg = 1;
10576 expression_and_evaluate (exp);
10577 allow_pseudo_reg = 0;
10578 register_chars['.'] = saved_register_dot;
10579 allow_naked_reg = saved_naked_reg;
10580
e96d56a1 10581 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10582 {
a60de03c
JB		 10583 if ((addressT) exp->X_add_number < i386_regtab_size)
10584 {
10585 exp->X_op = O_constant;
10586 exp->X_add_number = i386_regtab[exp->X_add_number]
10587 .dw2_regnum[flag_code >> 1];
10588 }
10589 else
10590 exp->X_op = O_illegal;
54cfded0 10591 }
54cfded0
AM		 10592}
10593
10594void
10595tc_x86_frame_initial_instructions (void)
10596{
a60de03c
JB		 10597 static unsigned int sp_regno[2];
10598
10599 if (!sp_regno[flag_code >> 1])
10600 {
10601 char *saved_input = input_line_pointer;
10602 char sp[][4] = {"esp", "rsp"};
10603 expressionS exp;
a4447b93 10604
a60de03c
JB		 10605 input_line_pointer = sp[flag_code >> 1];
10606 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10607 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10608 sp_regno[flag_code >> 1] = exp.X_add_number;
10609 input_line_pointer = saved_input;
10610 }
a4447b93 10611
61ff971f
L		 10612 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10613 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10614}
d2b2c203 10615
d7921315
L		 10616int
10617x86_dwarf2_addr_size (void)
10618{
10619#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10620 if (x86_elf_abi == X86_64_X32_ABI)
10621 return 4;
10622#endif
10623 return bfd_arch_bits_per_address (stdoutput) / 8;
10624}
10625
d2b2c203
DJ		 10626int
10627i386_elf_section_type (const char *str, size_t len)
10628{
10629 if (flag_code == CODE_64BIT
10630 && len == sizeof ("unwind") - 1
10631 && strncmp (str, "unwind", 6) == 0)
10632 return SHT_X86_64_UNWIND;
10633
10634 return -1;
10635}
bb41ade5 10636
ad5fec3b
EB		 10637#ifdef TE_SOLARIS
10638void
10639i386_solaris_fix_up_eh_frame (segT sec)
10640{
10641 if (flag_code == CODE_64BIT)
10642 elf_section_type (sec) = SHT_X86_64_UNWIND;
10643}
10644#endif
10645
bb41ade5
AM		 10646#ifdef TE_PE
10647void
10648tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10649{
91d6fa6a 10650 expressionS exp;
bb41ade5 10651
91d6fa6a
NC		 10652 exp.X_op = O_secrel;
10653 exp.X_add_symbol = symbol;
10654 exp.X_add_number = 0;
10655 emit_expr (&exp, size);
bb41ade5
AM		 10656}
10657#endif
3b22753a
L		 10658
10659#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10660/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10661
01e1a5bc 10662bfd_vma
3b22753a
L		 10663x86_64_section_letter (int letter, char **ptr_msg)
10664{
10665 if (flag_code == CODE_64BIT)
10666 {
10667 if (letter == 'l')
10668 return SHF_X86_64_LARGE;
10669
8f3bae45 10670 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10671 }
3b22753a 10672 else
8f3bae45 10673 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10674 return -1;
10675}
10676
01e1a5bc 10677bfd_vma
3b22753a
L		 10678x86_64_section_word (char *str, size_t len)
10679{
8620418b 10680 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10681 return SHF_X86_64_LARGE;
10682
10683 return -1;
10684}
10685
10686static void
10687handle_large_common (int small ATTRIBUTE_UNUSED)
10688{
10689 if (flag_code != CODE_64BIT)
10690 {
10691 s_comm_internal (0, elf_common_parse);
10692 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10693 }
10694 else
10695 {
10696 static segT lbss_section;
10697 asection *saved_com_section_ptr = elf_com_section_ptr;
10698 asection *saved_bss_section = bss_section;
10699
10700 if (lbss_section == NULL)
10701 {
10702 flagword applicable;
10703 segT seg = now_seg;
10704 subsegT subseg = now_subseg;
10705
10706 /* The .lbss section is for local .largecomm symbols. */
10707 lbss_section = subseg_new (".lbss", 0);
10708 applicable = bfd_applicable_section_flags (stdoutput);
10709 bfd_set_section_flags (stdoutput, lbss_section,
10710 applicable & SEC_ALLOC);
10711 seg_info (lbss_section)->bss = 1;
10712
10713 subseg_set (seg, subseg);
10714 }
10715
10716 elf_com_section_ptr = &_bfd_elf_large_com_section;
10717 bss_section = lbss_section;
10718
10719 s_comm_internal (0, elf_common_parse);
10720
10721 elf_com_section_ptr = saved_com_section_ptr;
10722 bss_section = saved_bss_section;
10723 }
10724}
10725#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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