Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
c75ef631 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ | |
252b5132 | 29 | |
252b5132 | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
252b5132 | 32 | #include "subsegs.h" |
316e2c05 | 33 | #include "dwarf2dbg.h" |
54cfded0 | 34 | #include "dw2gencfi.h" |
d2b2c203 | 35 | #include "elf/x86-64.h" |
40fb9820 | 36 | #include "opcodes/i386-init.h" |
252b5132 | 37 | |
252b5132 RH |
38 | #ifndef REGISTER_WARNINGS |
39 | #define REGISTER_WARNINGS 1 | |
40 | #endif | |
41 | ||
c3332e24 | 42 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 43 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
44 | #endif |
45 | ||
29b0f896 AM |
46 | #ifndef DEFAULT_ARCH |
47 | #define DEFAULT_ARCH "i386" | |
246fcdee | 48 | #endif |
252b5132 | 49 | |
edde18a5 AM |
50 | #ifndef INLINE |
51 | #if __GNUC__ >= 2 | |
52 | #define INLINE __inline__ | |
53 | #else | |
54 | #define INLINE | |
55 | #endif | |
56 | #endif | |
57 | ||
6305a203 L |
58 | /* Prefixes will be emitted in the order defined below. |
59 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
60 | instruction, and so must come before any prefixes. | |
61 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
c32fa91d | 62 | REP_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
63 | #define WAIT_PREFIX 0 |
64 | #define SEG_PREFIX 1 | |
65 | #define ADDR_PREFIX 2 | |
66 | #define DATA_PREFIX 3 | |
c32fa91d L |
67 | #define REP_PREFIX 4 |
68 | #define LOCK_PREFIX 5 | |
69 | #define REX_PREFIX 6 /* must come last. */ | |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
84 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 85 | #define YMMWORD_MNEM_SUFFIX 'y' |
6305a203 L |
86 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
87 | in instructions. */ | |
88 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
89 | ||
90 | #define END_OF_INSN '\0' | |
91 | ||
92 | /* | |
93 | 'templates' is for grouping together 'template' structures for opcodes | |
94 | of the same name. This is only used for storing the insns in the grand | |
95 | ole hash table of insns. | |
96 | The templates themselves start at START and range up to (but not including) | |
97 | END. | |
98 | */ | |
99 | typedef struct | |
100 | { | |
d3ce72d0 NC |
101 | const insn_template *start; |
102 | const insn_template *end; | |
6305a203 L |
103 | } |
104 | templates; | |
105 | ||
106 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
107 | typedef struct | |
108 | { | |
109 | unsigned int regmem; /* codes register or memory operand */ | |
110 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
111 | unsigned int mode; /* how to interpret regmem & reg */ | |
112 | } | |
113 | modrm_byte; | |
114 | ||
115 | /* x86-64 extension prefix. */ | |
116 | typedef int rex_byte; | |
117 | ||
6305a203 L |
118 | /* 386 opcode byte to code indirect addressing. */ |
119 | typedef struct | |
120 | { | |
121 | unsigned base; | |
122 | unsigned index; | |
123 | unsigned scale; | |
124 | } | |
125 | sib_byte; | |
126 | ||
6305a203 L |
127 | /* x86 arch names, types and features */ |
128 | typedef struct | |
129 | { | |
130 | const char *name; /* arch name */ | |
8a2c8fef | 131 | unsigned int len; /* arch string length */ |
6305a203 L |
132 | enum processor_type type; /* arch type */ |
133 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 134 | unsigned int skip; /* show_arch should skip this. */ |
22109423 | 135 | unsigned int negated; /* turn off indicated flags. */ |
6305a203 L |
136 | } |
137 | arch_entry; | |
138 | ||
78f12dd3 | 139 | static void update_code_flag (int, int); |
e3bb37b5 L |
140 | static void set_code_flag (int); |
141 | static void set_16bit_gcc_code_flag (int); | |
142 | static void set_intel_syntax (int); | |
1efbbeb4 | 143 | static void set_intel_mnemonic (int); |
db51cc60 | 144 | static void set_allow_index_reg (int); |
cb19c032 | 145 | static void set_sse_check (int); |
e3bb37b5 | 146 | static void set_cpu_arch (int); |
6482c264 | 147 | #ifdef TE_PE |
e3bb37b5 | 148 | static void pe_directive_secrel (int); |
6482c264 | 149 | #endif |
e3bb37b5 L |
150 | static void signed_cons (int); |
151 | static char *output_invalid (int c); | |
ee86248c JB |
152 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
153 | const char *); | |
154 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
155 | const char *); | |
a7619375 | 156 | static int i386_att_operand (char *); |
e3bb37b5 | 157 | static int i386_intel_operand (char *, int); |
ee86248c JB |
158 | static int i386_intel_simplify (expressionS *); |
159 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
160 | static const reg_entry *parse_register (char *, char **); |
161 | static char *parse_insn (char *, char *); | |
162 | static char *parse_operands (char *, const char *); | |
163 | static void swap_operands (void); | |
4d456e3d | 164 | static void swap_2_operands (int, int); |
e3bb37b5 L |
165 | static void optimize_imm (void); |
166 | static void optimize_disp (void); | |
d3ce72d0 | 167 | static const insn_template *match_template (void); |
e3bb37b5 L |
168 | static int check_string (void); |
169 | static int process_suffix (void); | |
170 | static int check_byte_reg (void); | |
171 | static int check_long_reg (void); | |
172 | static int check_qword_reg (void); | |
173 | static int check_word_reg (void); | |
174 | static int finalize_imm (void); | |
175 | static int process_operands (void); | |
176 | static const seg_entry *build_modrm_byte (void); | |
177 | static void output_insn (void); | |
178 | static void output_imm (fragS *, offsetT); | |
179 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 180 | #ifndef I386COFF |
e3bb37b5 | 181 | static void s_bss (int); |
252b5132 | 182 | #endif |
17d4e2a2 L |
183 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
184 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
185 | #endif | |
252b5132 | 186 | |
a847613f | 187 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 188 | |
c0f3af97 L |
189 | /* VEX prefix. */ |
190 | typedef struct | |
191 | { | |
192 | /* VEX prefix is either 2 byte or 3 byte. */ | |
193 | unsigned char bytes[3]; | |
194 | unsigned int length; | |
195 | /* Destination or source register specifier. */ | |
196 | const reg_entry *register_specifier; | |
197 | } vex_prefix; | |
198 | ||
252b5132 | 199 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 200 | i386_insn. */ |
252b5132 | 201 | |
520dc8e8 AM |
202 | union i386_op |
203 | { | |
204 | expressionS *disps; | |
205 | expressionS *imms; | |
206 | const reg_entry *regs; | |
207 | }; | |
208 | ||
a65babc9 L |
209 | enum i386_error |
210 | { | |
86e026a4 | 211 | operand_size_mismatch, |
a65babc9 L |
212 | operand_type_mismatch, |
213 | register_type_mismatch, | |
214 | number_of_operands_mismatch, | |
215 | invalid_instruction_suffix, | |
216 | bad_imm4, | |
217 | old_gcc_only, | |
218 | unsupported_with_intel_mnemonic, | |
219 | unsupported_syntax, | |
220 | unsupported | |
221 | }; | |
222 | ||
252b5132 RH |
223 | struct _i386_insn |
224 | { | |
47926f60 | 225 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 226 | insn_template tm; |
252b5132 | 227 | |
7d5e4556 L |
228 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
229 | or qword, if given. */ | |
252b5132 RH |
230 | char suffix; |
231 | ||
47926f60 | 232 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
233 | unsigned int operands; |
234 | ||
235 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
236 | of given register, displacement, memory operands and immediate | |
47926f60 | 237 | operands. */ |
252b5132 RH |
238 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
239 | ||
240 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 241 | use OP[i] for the corresponding operand. */ |
40fb9820 | 242 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 243 | |
520dc8e8 AM |
244 | /* Displacement expression, immediate expression, or register for each |
245 | operand. */ | |
246 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 247 | |
3e73aa7c JH |
248 | /* Flags for operands. */ |
249 | unsigned int flags[MAX_OPERANDS]; | |
250 | #define Operand_PCrel 1 | |
251 | ||
252b5132 | 252 | /* Relocation type for operand */ |
f86103b7 | 253 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 254 | |
252b5132 RH |
255 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
256 | the base index byte below. */ | |
257 | const reg_entry *base_reg; | |
258 | const reg_entry *index_reg; | |
259 | unsigned int log2_scale_factor; | |
260 | ||
261 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 262 | explicit segment overrides are given. */ |
ce8a8b2f | 263 | const seg_entry *seg[2]; |
252b5132 RH |
264 | |
265 | /* PREFIX holds all the given prefix opcodes (usually null). | |
266 | PREFIXES is the number of prefix opcodes. */ | |
267 | unsigned int prefixes; | |
268 | unsigned char prefix[MAX_PREFIXES]; | |
269 | ||
270 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 271 | addressing modes of this insn are encoded. */ |
252b5132 | 272 | modrm_byte rm; |
3e73aa7c | 273 | rex_byte rex; |
252b5132 | 274 | sib_byte sib; |
c0f3af97 | 275 | vex_prefix vex; |
b6169b20 L |
276 | |
277 | /* Swap operand in encoding. */ | |
4473e004 | 278 | unsigned int swap_operand; |
891edac4 | 279 | |
f8a5c266 L |
280 | /* Force 32bit displacement in encoding. */ |
281 | unsigned int disp32_encoding; | |
282 | ||
891edac4 | 283 | /* Error message. */ |
a65babc9 | 284 | enum i386_error error; |
252b5132 RH |
285 | }; |
286 | ||
287 | typedef struct _i386_insn i386_insn; | |
288 | ||
289 | /* List of chars besides those in app.c:symbol_chars that can start an | |
290 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 291 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 292 | #ifdef LEX_AT |
32137342 NC |
293 | "@" |
294 | #endif | |
295 | #ifdef LEX_QM | |
296 | "?" | |
252b5132 | 297 | #endif |
32137342 | 298 | ; |
252b5132 | 299 | |
29b0f896 AM |
300 | #if (defined (TE_I386AIX) \ |
301 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 302 | && !defined (TE_GNU) \ |
29b0f896 | 303 | && !defined (TE_LINUX) \ |
32137342 | 304 | && !defined (TE_NETWARE) \ |
29b0f896 AM |
305 | && !defined (TE_FreeBSD) \ |
306 | && !defined (TE_NetBSD))) | |
252b5132 | 307 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
308 | pre-processor is disabled, these aren't very useful. The option |
309 | --divide will remove '/' from this list. */ | |
310 | const char *i386_comment_chars = "#/"; | |
311 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 312 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 313 | |
b3b91714 AM |
314 | #else |
315 | const char *i386_comment_chars = "#"; | |
316 | #define PREFIX_SEPARATOR '/' | |
317 | #endif | |
318 | ||
252b5132 RH |
319 | /* This array holds the chars that only start a comment at the beginning of |
320 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
321 | .line and .file directives will appear in the pre-processed output. |
322 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 323 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
324 | #NO_APP at the beginning of its output. |
325 | Also note that comments started like this one will always work if | |
252b5132 | 326 | '/' isn't otherwise defined. */ |
b3b91714 | 327 | const char line_comment_chars[] = "#/"; |
252b5132 | 328 | |
63a0b638 | 329 | const char line_separator_chars[] = ";"; |
252b5132 | 330 | |
ce8a8b2f AM |
331 | /* Chars that can be used to separate mant from exp in floating point |
332 | nums. */ | |
252b5132 RH |
333 | const char EXP_CHARS[] = "eE"; |
334 | ||
ce8a8b2f AM |
335 | /* Chars that mean this number is a floating point constant |
336 | As in 0f12.456 | |
337 | or 0d1.2345e12. */ | |
252b5132 RH |
338 | const char FLT_CHARS[] = "fFdDxX"; |
339 | ||
ce8a8b2f | 340 | /* Tables for lexical analysis. */ |
252b5132 RH |
341 | static char mnemonic_chars[256]; |
342 | static char register_chars[256]; | |
343 | static char operand_chars[256]; | |
344 | static char identifier_chars[256]; | |
345 | static char digit_chars[256]; | |
346 | ||
ce8a8b2f | 347 | /* Lexical macros. */ |
252b5132 RH |
348 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
349 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
350 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
351 | #define is_space_char(x) ((x) == ' ') | |
352 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
353 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
354 | ||
0234cb7c | 355 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
356 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
357 | ||
358 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
359 | effect this we maintain a stack of saved characters that we've smashed | |
360 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 361 | assembler instruction). */ |
252b5132 | 362 | static char save_stack[32]; |
ce8a8b2f | 363 | static char *save_stack_p; |
252b5132 RH |
364 | #define END_STRING_AND_SAVE(s) \ |
365 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
366 | #define RESTORE_END_STRING(s) \ | |
367 | do { *(s) = *--save_stack_p; } while (0) | |
368 | ||
47926f60 | 369 | /* The instruction we're assembling. */ |
252b5132 RH |
370 | static i386_insn i; |
371 | ||
372 | /* Possible templates for current insn. */ | |
373 | static const templates *current_templates; | |
374 | ||
31b2323c L |
375 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
376 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
377 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 378 | |
47926f60 | 379 | /* Current operand we are working on. */ |
ee86248c | 380 | static int this_operand = -1; |
252b5132 | 381 | |
3e73aa7c JH |
382 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
383 | these. */ | |
384 | ||
385 | enum flag_code { | |
386 | CODE_32BIT, | |
387 | CODE_16BIT, | |
388 | CODE_64BIT }; | |
389 | ||
390 | static enum flag_code flag_code; | |
4fa24527 | 391 | static unsigned int object_64bit; |
862be3fb | 392 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
393 | static int use_rela_relocations = 0; |
394 | ||
7af8ed2d NC |
395 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
396 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
397 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
398 | ||
351f65ca L |
399 | /* The ELF ABI to use. */ |
400 | enum x86_elf_abi | |
401 | { | |
402 | I386_ABI, | |
7f56bc95 L |
403 | X86_64_ABI, |
404 | X86_64_X32_ABI | |
351f65ca L |
405 | }; |
406 | ||
407 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 408 | #endif |
351f65ca | 409 | |
3e73aa7c | 410 | /* The names used to print error messages. */ |
b77a7acd | 411 | static const char *flag_code_names[] = |
3e73aa7c JH |
412 | { |
413 | "32", | |
414 | "16", | |
415 | "64" | |
416 | }; | |
252b5132 | 417 | |
47926f60 KH |
418 | /* 1 for intel syntax, |
419 | 0 if att syntax. */ | |
420 | static int intel_syntax = 0; | |
252b5132 | 421 | |
1efbbeb4 L |
422 | /* 1 for intel mnemonic, |
423 | 0 if att mnemonic. */ | |
424 | static int intel_mnemonic = !SYSV386_COMPAT; | |
425 | ||
5209009a | 426 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
427 | static int old_gcc = OLDGCC_COMPAT; |
428 | ||
a60de03c JB |
429 | /* 1 if pseudo registers are permitted. */ |
430 | static int allow_pseudo_reg = 0; | |
431 | ||
47926f60 KH |
432 | /* 1 if register prefix % not required. */ |
433 | static int allow_naked_reg = 0; | |
252b5132 | 434 | |
ba104c83 | 435 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
436 | static int allow_index_reg = 0; |
437 | ||
daf50ae7 L |
438 | static enum |
439 | { | |
440 | sse_check_none = 0, | |
441 | sse_check_warning, | |
442 | sse_check_error | |
443 | } | |
444 | sse_check; | |
445 | ||
2ca3ace5 L |
446 | /* Register prefix used for error message. */ |
447 | static const char *register_prefix = "%"; | |
448 | ||
47926f60 KH |
449 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
450 | leave, push, and pop instructions so that gcc has the same stack | |
451 | frame as in 32 bit mode. */ | |
452 | static char stackop_size = '\0'; | |
eecb386c | 453 | |
12b55ccc L |
454 | /* Non-zero to optimize code alignment. */ |
455 | int optimize_align_code = 1; | |
456 | ||
47926f60 KH |
457 | /* Non-zero to quieten some warnings. */ |
458 | static int quiet_warnings = 0; | |
a38cf1db | 459 | |
47926f60 KH |
460 | /* CPU name. */ |
461 | static const char *cpu_arch_name = NULL; | |
6305a203 | 462 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 463 | |
47926f60 | 464 | /* CPU feature flags. */ |
40fb9820 L |
465 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
466 | ||
ccc9c027 L |
467 | /* If we have selected a cpu we are generating instructions for. */ |
468 | static int cpu_arch_tune_set = 0; | |
469 | ||
9103f4f4 | 470 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 471 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
472 | |
473 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 474 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 475 | |
ccc9c027 | 476 | /* CPU instruction set architecture used. */ |
fbf3f584 | 477 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 478 | |
9103f4f4 | 479 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 480 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 481 | |
fddf5b5b AM |
482 | /* If set, conditional jumps are not automatically promoted to handle |
483 | larger than a byte offset. */ | |
484 | static unsigned int no_cond_jump_promotion = 0; | |
485 | ||
c0f3af97 L |
486 | /* Encode SSE instructions with VEX prefix. */ |
487 | static unsigned int sse2avx; | |
488 | ||
539f890d L |
489 | /* Encode scalar AVX instructions with specific vector length. */ |
490 | static enum | |
491 | { | |
492 | vex128 = 0, | |
493 | vex256 | |
494 | } avxscalar; | |
495 | ||
29b0f896 | 496 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 497 | static symbolS *GOT_symbol; |
29b0f896 | 498 | |
a4447b93 RH |
499 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
500 | unsigned int x86_dwarf2_return_column; | |
501 | ||
502 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
503 | int x86_cie_data_alignment; | |
504 | ||
252b5132 | 505 | /* Interface to relax_segment. |
fddf5b5b AM |
506 | There are 3 major relax states for 386 jump insns because the |
507 | different types of jumps add different sizes to frags when we're | |
508 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 509 | |
47926f60 | 510 | /* Types. */ |
93c2a809 AM |
511 | #define UNCOND_JUMP 0 |
512 | #define COND_JUMP 1 | |
513 | #define COND_JUMP86 2 | |
fddf5b5b | 514 | |
47926f60 | 515 | /* Sizes. */ |
252b5132 RH |
516 | #define CODE16 1 |
517 | #define SMALL 0 | |
29b0f896 | 518 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 519 | #define BIG 2 |
29b0f896 | 520 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
521 | |
522 | #ifndef INLINE | |
523 | #ifdef __GNUC__ | |
524 | #define INLINE __inline__ | |
525 | #else | |
526 | #define INLINE | |
527 | #endif | |
528 | #endif | |
529 | ||
fddf5b5b AM |
530 | #define ENCODE_RELAX_STATE(type, size) \ |
531 | ((relax_substateT) (((type) << 2) | (size))) | |
532 | #define TYPE_FROM_RELAX_STATE(s) \ | |
533 | ((s) >> 2) | |
534 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
535 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
536 | |
537 | /* This table is used by relax_frag to promote short jumps to long | |
538 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
539 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
540 | don't allow a short jump in a 32 bit code segment to be promoted to | |
541 | a 16 bit offset jump because it's slower (requires data size | |
542 | prefix), and doesn't work, unless the destination is in the bottom | |
543 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
544 | ||
545 | const relax_typeS md_relax_table[] = | |
546 | { | |
24eab124 AM |
547 | /* The fields are: |
548 | 1) most positive reach of this state, | |
549 | 2) most negative reach of this state, | |
93c2a809 | 550 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 551 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 552 | |
fddf5b5b | 553 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
554 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
555 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
556 | /* dword jmp adds 4 bytes to frag: | |
557 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 558 | {0, 0, 4, 0}, |
93c2a809 AM |
559 | /* word jmp adds 2 byte2 to frag: |
560 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
561 | {0, 0, 2, 0}, |
562 | ||
93c2a809 AM |
563 | /* COND_JUMP states. */ |
564 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
565 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
566 | /* dword conditionals adds 5 bytes to frag: | |
567 | 1 extra opcode byte, 4 displacement bytes. */ | |
568 | {0, 0, 5, 0}, | |
fddf5b5b | 569 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
570 | 1 extra opcode byte, 2 displacement bytes. */ |
571 | {0, 0, 3, 0}, | |
572 | ||
573 | /* COND_JUMP86 states. */ | |
574 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
575 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
576 | /* dword conditionals adds 5 bytes to frag: | |
577 | 1 extra opcode byte, 4 displacement bytes. */ | |
578 | {0, 0, 5, 0}, | |
579 | /* word conditionals add 4 bytes to frag: | |
580 | 1 displacement byte and a 3 byte long branch insn. */ | |
581 | {0, 0, 4, 0} | |
252b5132 RH |
582 | }; |
583 | ||
9103f4f4 L |
584 | static const arch_entry cpu_arch[] = |
585 | { | |
89507696 JB |
586 | /* Do not replace the first two entries - i386_target_format() |
587 | relies on them being there in this order. */ | |
8a2c8fef | 588 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
22109423 | 589 | CPU_GENERIC32_FLAGS, 0, 0 }, |
8a2c8fef | 590 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
22109423 | 591 | CPU_GENERIC64_FLAGS, 0, 0 }, |
8a2c8fef | 592 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
22109423 | 593 | CPU_NONE_FLAGS, 0, 0 }, |
8a2c8fef | 594 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
22109423 | 595 | CPU_I186_FLAGS, 0, 0 }, |
8a2c8fef | 596 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
22109423 | 597 | CPU_I286_FLAGS, 0, 0 }, |
8a2c8fef | 598 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
22109423 | 599 | CPU_I386_FLAGS, 0, 0 }, |
8a2c8fef | 600 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
22109423 | 601 | CPU_I486_FLAGS, 0, 0 }, |
8a2c8fef | 602 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
22109423 | 603 | CPU_I586_FLAGS, 0, 0 }, |
8a2c8fef | 604 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
22109423 | 605 | CPU_I686_FLAGS, 0, 0 }, |
8a2c8fef | 606 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
22109423 | 607 | CPU_I586_FLAGS, 0, 0 }, |
8a2c8fef | 608 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
22109423 | 609 | CPU_PENTIUMPRO_FLAGS, 0, 0 }, |
8a2c8fef | 610 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
22109423 | 611 | CPU_P2_FLAGS, 0, 0 }, |
8a2c8fef | 612 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
22109423 | 613 | CPU_P3_FLAGS, 0, 0 }, |
8a2c8fef | 614 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
22109423 | 615 | CPU_P4_FLAGS, 0, 0 }, |
8a2c8fef | 616 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
22109423 | 617 | CPU_CORE_FLAGS, 0, 0 }, |
8a2c8fef | 618 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
22109423 | 619 | CPU_NOCONA_FLAGS, 0, 0 }, |
8a2c8fef | 620 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
22109423 | 621 | CPU_CORE_FLAGS, 1, 0 }, |
8a2c8fef | 622 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
22109423 | 623 | CPU_CORE_FLAGS, 0, 0 }, |
8a2c8fef | 624 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
22109423 | 625 | CPU_CORE2_FLAGS, 1, 0 }, |
8a2c8fef | 626 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
22109423 | 627 | CPU_CORE2_FLAGS, 0, 0 }, |
8a2c8fef | 628 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
22109423 | 629 | CPU_COREI7_FLAGS, 0, 0 }, |
8a2c8fef | 630 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
22109423 | 631 | CPU_L1OM_FLAGS, 0, 0 }, |
8a2c8fef | 632 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
22109423 | 633 | CPU_K6_FLAGS, 0, 0 }, |
8a2c8fef | 634 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
22109423 | 635 | CPU_K6_2_FLAGS, 0, 0 }, |
8a2c8fef | 636 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
22109423 | 637 | CPU_ATHLON_FLAGS, 0, 0 }, |
8a2c8fef | 638 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
22109423 | 639 | CPU_K8_FLAGS, 1, 0 }, |
8a2c8fef | 640 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
22109423 | 641 | CPU_K8_FLAGS, 0, 0 }, |
8a2c8fef | 642 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
22109423 | 643 | CPU_K8_FLAGS, 0, 0 }, |
8a2c8fef | 644 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
22109423 | 645 | CPU_AMDFAM10_FLAGS, 0, 0 }, |
68339fdf | 646 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1, |
22109423 | 647 | CPU_BDVER1_FLAGS, 0, 0 }, |
8a2c8fef | 648 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
22109423 | 649 | CPU_8087_FLAGS, 0, 0 }, |
8a2c8fef | 650 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
22109423 | 651 | CPU_287_FLAGS, 0, 0 }, |
8a2c8fef | 652 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
22109423 | 653 | CPU_387_FLAGS, 0, 0 }, |
8a2c8fef | 654 | { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN, |
22109423 | 655 | CPU_ANY87_FLAGS, 0, 1 }, |
8a2c8fef | 656 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
22109423 | 657 | CPU_MMX_FLAGS, 0, 0 }, |
8a2c8fef | 658 | { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN, |
22109423 | 659 | CPU_3DNOWA_FLAGS, 0, 1 }, |
8a2c8fef | 660 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
22109423 | 661 | CPU_SSE_FLAGS, 0, 0 }, |
8a2c8fef | 662 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
22109423 | 663 | CPU_SSE2_FLAGS, 0, 0 }, |
8a2c8fef | 664 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
22109423 | 665 | CPU_SSE3_FLAGS, 0, 0 }, |
8a2c8fef | 666 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
22109423 | 667 | CPU_SSSE3_FLAGS, 0, 0 }, |
8a2c8fef | 668 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
22109423 | 669 | CPU_SSE4_1_FLAGS, 0, 0 }, |
8a2c8fef | 670 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
22109423 | 671 | CPU_SSE4_2_FLAGS, 0, 0 }, |
8a2c8fef | 672 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
22109423 | 673 | CPU_SSE4_2_FLAGS, 0, 0 }, |
8a2c8fef | 674 | { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN, |
22109423 | 675 | CPU_ANY_SSE_FLAGS, 0, 1 }, |
8a2c8fef | 676 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
22109423 | 677 | CPU_AVX_FLAGS, 0, 0 }, |
8a2c8fef | 678 | { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN, |
22109423 | 679 | CPU_ANY_AVX_FLAGS, 0, 1 }, |
8a2c8fef | 680 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
22109423 | 681 | CPU_VMX_FLAGS, 0, 0 }, |
8a2c8fef | 682 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
22109423 | 683 | CPU_SMX_FLAGS, 0, 0 }, |
8a2c8fef | 684 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
22109423 | 685 | CPU_XSAVE_FLAGS, 0, 0 }, |
c7b8aa3a | 686 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
22109423 | 687 | CPU_XSAVEOPT_FLAGS, 0, 0 }, |
8a2c8fef | 688 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
22109423 | 689 | CPU_AES_FLAGS, 0, 0 }, |
8a2c8fef | 690 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
22109423 | 691 | CPU_PCLMUL_FLAGS, 0, 0 }, |
8a2c8fef | 692 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
22109423 | 693 | CPU_PCLMUL_FLAGS, 1, 0 }, |
c7b8aa3a | 694 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
22109423 | 695 | CPU_FSGSBASE_FLAGS, 0, 0 }, |
c7b8aa3a | 696 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
22109423 | 697 | CPU_RDRND_FLAGS, 0, 0 }, |
c7b8aa3a | 698 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
22109423 | 699 | CPU_F16C_FLAGS, 0, 0 }, |
8a2c8fef | 700 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
22109423 | 701 | CPU_FMA_FLAGS, 0, 0 }, |
8a2c8fef | 702 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
22109423 | 703 | CPU_FMA4_FLAGS, 0, 0 }, |
8a2c8fef | 704 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
22109423 | 705 | CPU_XOP_FLAGS, 0, 0 }, |
8a2c8fef | 706 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
22109423 | 707 | CPU_LWP_FLAGS, 0, 0 }, |
8a2c8fef | 708 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
22109423 | 709 | CPU_MOVBE_FLAGS, 0, 0 }, |
8a2c8fef | 710 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
22109423 | 711 | CPU_EPT_FLAGS, 0, 0 }, |
8a2c8fef | 712 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
22109423 L |
713 | CPU_CLFLUSH_FLAGS, 0, 0 }, |
714 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, | |
715 | CPU_NOP_FLAGS, 0, 0 }, | |
8a2c8fef | 716 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
22109423 | 717 | CPU_SYSCALL_FLAGS, 0, 0 }, |
8a2c8fef | 718 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
22109423 | 719 | CPU_RDTSCP_FLAGS, 0, 0 }, |
8a2c8fef | 720 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
22109423 | 721 | CPU_3DNOW_FLAGS, 0, 0 }, |
8a2c8fef | 722 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
22109423 | 723 | CPU_3DNOWA_FLAGS, 0, 0 }, |
8a2c8fef | 724 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
22109423 | 725 | CPU_PADLOCK_FLAGS, 0, 0 }, |
8a2c8fef | 726 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
22109423 | 727 | CPU_SVME_FLAGS, 1, 0 }, |
8a2c8fef | 728 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
22109423 | 729 | CPU_SVME_FLAGS, 0, 0 }, |
8a2c8fef | 730 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
22109423 | 731 | CPU_SSE4A_FLAGS, 0, 0 }, |
8a2c8fef | 732 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
22109423 | 733 | CPU_ABM_FLAGS, 0, 0 }, |
87973e9f QN |
734 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
735 | CPU_BMI_FLAGS, 0, 0 }, | |
2a2a0f38 QN |
736 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
737 | CPU_TBM_FLAGS, 0, 0 }, | |
e413e4e9 AM |
738 | }; |
739 | ||
704209c0 | 740 | #ifdef I386COFF |
a6c24e68 NC |
741 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
742 | is allowed to be optional. */ | |
743 | ||
744 | static symbolS * | |
745 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
746 | { | |
747 | addressT align = 0; | |
748 | ||
749 | SKIP_WHITESPACE (); | |
750 | ||
7ab9ffdd | 751 | if (needs_align |
a6c24e68 NC |
752 | && *input_line_pointer == ',') |
753 | { | |
754 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 755 | |
a6c24e68 NC |
756 | if (align == (addressT) -1) |
757 | return NULL; | |
758 | } | |
759 | else | |
760 | { | |
761 | if (size >= 8) | |
762 | align = 3; | |
763 | else if (size >= 4) | |
764 | align = 2; | |
765 | else if (size >= 2) | |
766 | align = 1; | |
767 | else | |
768 | align = 0; | |
769 | } | |
770 | ||
771 | bss_alloc (symbolP, size, align); | |
772 | return symbolP; | |
773 | } | |
774 | ||
704209c0 | 775 | static void |
a6c24e68 NC |
776 | pe_lcomm (int needs_align) |
777 | { | |
778 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
779 | } | |
704209c0 | 780 | #endif |
a6c24e68 | 781 | |
29b0f896 AM |
782 | const pseudo_typeS md_pseudo_table[] = |
783 | { | |
784 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
785 | {"align", s_align_bytes, 0}, | |
786 | #else | |
787 | {"align", s_align_ptwo, 0}, | |
788 | #endif | |
789 | {"arch", set_cpu_arch, 0}, | |
790 | #ifndef I386COFF | |
791 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
792 | #else |
793 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
794 | #endif |
795 | {"ffloat", float_cons, 'f'}, | |
796 | {"dfloat", float_cons, 'd'}, | |
797 | {"tfloat", float_cons, 'x'}, | |
798 | {"value", cons, 2}, | |
d182319b | 799 | {"slong", signed_cons, 4}, |
29b0f896 AM |
800 | {"noopt", s_ignore, 0}, |
801 | {"optim", s_ignore, 0}, | |
802 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
803 | {"code16", set_code_flag, CODE_16BIT}, | |
804 | {"code32", set_code_flag, CODE_32BIT}, | |
805 | {"code64", set_code_flag, CODE_64BIT}, | |
806 | {"intel_syntax", set_intel_syntax, 1}, | |
807 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
808 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
809 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
810 | {"allow_index_reg", set_allow_index_reg, 1}, |
811 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
cb19c032 | 812 | {"sse_check", set_sse_check, 0}, |
3b22753a L |
813 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
814 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 815 | #else |
e3bb37b5 | 816 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
817 | {"loc", dwarf2_directive_loc, 0}, |
818 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 819 | #endif |
6482c264 NC |
820 | #ifdef TE_PE |
821 | {"secrel32", pe_directive_secrel, 0}, | |
822 | #endif | |
29b0f896 AM |
823 | {0, 0, 0} |
824 | }; | |
825 | ||
826 | /* For interface with expression (). */ | |
827 | extern char *input_line_pointer; | |
828 | ||
829 | /* Hash table for instruction mnemonic lookup. */ | |
830 | static struct hash_control *op_hash; | |
831 | ||
832 | /* Hash table for register lookup. */ | |
833 | static struct hash_control *reg_hash; | |
834 | \f | |
252b5132 | 835 | void |
e3bb37b5 | 836 | i386_align_code (fragS *fragP, int count) |
252b5132 | 837 | { |
ce8a8b2f AM |
838 | /* Various efficient no-op patterns for aligning code labels. |
839 | Note: Don't try to assemble the instructions in the comments. | |
840 | 0L and 0w are not legal. */ | |
252b5132 RH |
841 | static const char f32_1[] = |
842 | {0x90}; /* nop */ | |
843 | static const char f32_2[] = | |
ccc9c027 | 844 | {0x66,0x90}; /* xchg %ax,%ax */ |
252b5132 RH |
845 | static const char f32_3[] = |
846 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
847 | static const char f32_4[] = | |
848 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
849 | static const char f32_5[] = | |
850 | {0x90, /* nop */ | |
851 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
852 | static const char f32_6[] = | |
853 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
854 | static const char f32_7[] = | |
855 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
856 | static const char f32_8[] = | |
857 | {0x90, /* nop */ | |
858 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
859 | static const char f32_9[] = | |
860 | {0x89,0xf6, /* movl %esi,%esi */ | |
861 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
862 | static const char f32_10[] = | |
863 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
864 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
865 | static const char f32_11[] = | |
866 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
867 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
868 | static const char f32_12[] = | |
869 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
870 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
871 | static const char f32_13[] = | |
872 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
873 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
874 | static const char f32_14[] = | |
875 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
876 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
c3332e24 AM |
877 | static const char f16_3[] = |
878 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
879 | static const char f16_4[] = |
880 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
881 | static const char f16_5[] = | |
882 | {0x90, /* nop */ | |
883 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
884 | static const char f16_6[] = | |
885 | {0x89,0xf6, /* mov %si,%si */ | |
886 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
887 | static const char f16_7[] = | |
888 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
889 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
890 | static const char f16_8[] = | |
891 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
892 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
76bc74dc L |
893 | static const char jump_31[] = |
894 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ | |
895 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
896 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
897 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
252b5132 RH |
898 | static const char *const f32_patt[] = { |
899 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
76bc74dc | 900 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 RH |
901 | }; |
902 | static const char *const f16_patt[] = { | |
76bc74dc | 903 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 904 | }; |
ccc9c027 L |
905 | /* nopl (%[re]ax) */ |
906 | static const char alt_3[] = | |
907 | {0x0f,0x1f,0x00}; | |
908 | /* nopl 0(%[re]ax) */ | |
909 | static const char alt_4[] = | |
910 | {0x0f,0x1f,0x40,0x00}; | |
911 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
912 | static const char alt_5[] = | |
913 | {0x0f,0x1f,0x44,0x00,0x00}; | |
914 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
915 | static const char alt_6[] = | |
916 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
917 | /* nopl 0L(%[re]ax) */ | |
918 | static const char alt_7[] = | |
919 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
920 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
921 | static const char alt_8[] = | |
922 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
923 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
924 | static const char alt_9[] = | |
925 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
926 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
927 | static const char alt_10[] = | |
928 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
929 | /* data16 | |
930 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
931 | static const char alt_long_11[] = | |
932 | {0x66, | |
933 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
934 | /* data16 | |
935 | data16 | |
936 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
937 | static const char alt_long_12[] = | |
938 | {0x66, | |
939 | 0x66, | |
940 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
941 | /* data16 | |
942 | data16 | |
943 | data16 | |
944 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
945 | static const char alt_long_13[] = | |
946 | {0x66, | |
947 | 0x66, | |
948 | 0x66, | |
949 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
950 | /* data16 | |
951 | data16 | |
952 | data16 | |
953 | data16 | |
954 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
955 | static const char alt_long_14[] = | |
956 | {0x66, | |
957 | 0x66, | |
958 | 0x66, | |
959 | 0x66, | |
960 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
961 | /* data16 | |
962 | data16 | |
963 | data16 | |
964 | data16 | |
965 | data16 | |
966 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
967 | static const char alt_long_15[] = | |
968 | {0x66, | |
969 | 0x66, | |
970 | 0x66, | |
971 | 0x66, | |
972 | 0x66, | |
973 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
974 | /* nopl 0(%[re]ax,%[re]ax,1) | |
975 | nopw 0(%[re]ax,%[re]ax,1) */ | |
976 | static const char alt_short_11[] = | |
977 | {0x0f,0x1f,0x44,0x00,0x00, | |
978 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
979 | /* nopw 0(%[re]ax,%[re]ax,1) | |
980 | nopw 0(%[re]ax,%[re]ax,1) */ | |
981 | static const char alt_short_12[] = | |
982 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
983 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
984 | /* nopw 0(%[re]ax,%[re]ax,1) | |
985 | nopl 0L(%[re]ax) */ | |
986 | static const char alt_short_13[] = | |
987 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
988 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
989 | /* nopl 0L(%[re]ax) | |
990 | nopl 0L(%[re]ax) */ | |
991 | static const char alt_short_14[] = | |
992 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
993 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
994 | /* nopl 0L(%[re]ax) | |
995 | nopl 0L(%[re]ax,%[re]ax,1) */ | |
996 | static const char alt_short_15[] = | |
997 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
998 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
999 | static const char *const alt_short_patt[] = { | |
1000 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
1001 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, | |
1002 | alt_short_14, alt_short_15 | |
1003 | }; | |
1004 | static const char *const alt_long_patt[] = { | |
1005 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
1006 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, | |
1007 | alt_long_14, alt_long_15 | |
1008 | }; | |
252b5132 | 1009 | |
76bc74dc L |
1010 | /* Only align for at least a positive non-zero boundary. */ |
1011 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 1012 | return; |
3e73aa7c | 1013 | |
ccc9c027 L |
1014 | /* We need to decide which NOP sequence to use for 32bit and |
1015 | 64bit. When -mtune= is used: | |
4eed87de | 1016 | |
76bc74dc L |
1017 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1018 | PROCESSOR_GENERIC32, f32_patt will be used. | |
1019 | 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, | |
bd5295b2 L |
1020 | PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and |
1021 | PROCESSOR_GENERIC64, alt_long_patt will be used. | |
76bc74dc | 1022 | 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and |
68339fdf | 1023 | PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt |
69dd9865 | 1024 | will be used. |
ccc9c027 | 1025 | |
76bc74dc | 1026 | When -mtune= isn't used, alt_long_patt will be used if |
22109423 | 1027 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1028 | be used. |
ccc9c027 L |
1029 | |
1030 | When -march= or .arch is used, we can't use anything beyond | |
1031 | cpu_arch_isa_flags. */ | |
1032 | ||
1033 | if (flag_code == CODE_16BIT) | |
1034 | { | |
ccc9c027 | 1035 | if (count > 8) |
33fef721 | 1036 | { |
76bc74dc L |
1037 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1038 | jump_31, count); | |
1039 | /* Adjust jump offset. */ | |
1040 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 1041 | } |
76bc74dc L |
1042 | else |
1043 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1044 | f16_patt[count - 1], count); | |
252b5132 | 1045 | } |
33fef721 | 1046 | else |
ccc9c027 L |
1047 | { |
1048 | const char *const *patt = NULL; | |
1049 | ||
fbf3f584 | 1050 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1051 | { |
1052 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1053 | switch (cpu_arch_tune) | |
1054 | { | |
1055 | case PROCESSOR_UNKNOWN: | |
1056 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1057 | optimize with nops. */ |
1058 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
76bc74dc | 1059 | patt = alt_long_patt; |
ccc9c027 L |
1060 | else |
1061 | patt = f32_patt; | |
1062 | break; | |
ccc9c027 L |
1063 | case PROCESSOR_PENTIUM4: |
1064 | case PROCESSOR_NOCONA: | |
ef05d495 | 1065 | case PROCESSOR_CORE: |
76bc74dc | 1066 | case PROCESSOR_CORE2: |
bd5295b2 | 1067 | case PROCESSOR_COREI7: |
3632d14b | 1068 | case PROCESSOR_L1OM: |
76bc74dc L |
1069 | case PROCESSOR_GENERIC64: |
1070 | patt = alt_long_patt; | |
1071 | break; | |
ccc9c027 L |
1072 | case PROCESSOR_K6: |
1073 | case PROCESSOR_ATHLON: | |
1074 | case PROCESSOR_K8: | |
4eed87de | 1075 | case PROCESSOR_AMDFAM10: |
68339fdf | 1076 | case PROCESSOR_BDVER1: |
ccc9c027 L |
1077 | patt = alt_short_patt; |
1078 | break; | |
76bc74dc | 1079 | case PROCESSOR_I386: |
ccc9c027 L |
1080 | case PROCESSOR_I486: |
1081 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1082 | case PROCESSOR_PENTIUMPRO: |
ccc9c027 L |
1083 | case PROCESSOR_GENERIC32: |
1084 | patt = f32_patt; | |
1085 | break; | |
4eed87de | 1086 | } |
ccc9c027 L |
1087 | } |
1088 | else | |
1089 | { | |
fbf3f584 | 1090 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1091 | { |
1092 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1093 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1094 | PROCESSOR_UNKNOWN. */ |
1095 | abort (); | |
1096 | break; | |
1097 | ||
76bc74dc | 1098 | case PROCESSOR_I386: |
ccc9c027 L |
1099 | case PROCESSOR_I486: |
1100 | case PROCESSOR_PENTIUM: | |
ccc9c027 L |
1101 | case PROCESSOR_K6: |
1102 | case PROCESSOR_ATHLON: | |
1103 | case PROCESSOR_K8: | |
4eed87de | 1104 | case PROCESSOR_AMDFAM10: |
68339fdf | 1105 | case PROCESSOR_BDVER1: |
ccc9c027 L |
1106 | case PROCESSOR_GENERIC32: |
1107 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1108 | with nops. */ |
1109 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
ccc9c027 L |
1110 | patt = alt_short_patt; |
1111 | else | |
1112 | patt = f32_patt; | |
1113 | break; | |
76bc74dc L |
1114 | case PROCESSOR_PENTIUMPRO: |
1115 | case PROCESSOR_PENTIUM4: | |
1116 | case PROCESSOR_NOCONA: | |
1117 | case PROCESSOR_CORE: | |
ef05d495 | 1118 | case PROCESSOR_CORE2: |
bd5295b2 | 1119 | case PROCESSOR_COREI7: |
3632d14b | 1120 | case PROCESSOR_L1OM: |
22109423 | 1121 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
ccc9c027 L |
1122 | patt = alt_long_patt; |
1123 | else | |
1124 | patt = f32_patt; | |
1125 | break; | |
1126 | case PROCESSOR_GENERIC64: | |
76bc74dc | 1127 | patt = alt_long_patt; |
ccc9c027 | 1128 | break; |
4eed87de | 1129 | } |
ccc9c027 L |
1130 | } |
1131 | ||
76bc74dc L |
1132 | if (patt == f32_patt) |
1133 | { | |
1134 | /* If the padding is less than 15 bytes, we use the normal | |
1135 | ones. Otherwise, we use a jump instruction and adjust | |
711eedef L |
1136 | its offset. */ |
1137 | int limit; | |
76ba9986 | 1138 | |
711eedef L |
1139 | /* For 64bit, the limit is 3 bytes. */ |
1140 | if (flag_code == CODE_64BIT | |
1141 | && fragP->tc_frag_data.isa_flags.bitfield.cpulm) | |
1142 | limit = 3; | |
1143 | else | |
1144 | limit = 15; | |
1145 | if (count < limit) | |
76bc74dc L |
1146 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1147 | patt[count - 1], count); | |
1148 | else | |
1149 | { | |
1150 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1151 | jump_31, count); | |
1152 | /* Adjust jump offset. */ | |
1153 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1154 | } | |
1155 | } | |
1156 | else | |
1157 | { | |
1158 | /* Maximum length of an instruction is 15 byte. If the | |
1159 | padding is greater than 15 bytes and we don't use jump, | |
1160 | we have to break it into smaller pieces. */ | |
1161 | int padding = count; | |
1162 | while (padding > 15) | |
1163 | { | |
1164 | padding -= 15; | |
1165 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, | |
1166 | patt [14], 15); | |
1167 | } | |
1168 | ||
1169 | if (padding) | |
1170 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1171 | patt [padding - 1], padding); | |
1172 | } | |
ccc9c027 | 1173 | } |
33fef721 | 1174 | fragP->fr_var = count; |
252b5132 RH |
1175 | } |
1176 | ||
c6fb90c8 | 1177 | static INLINE int |
0dfbf9d7 | 1178 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1179 | { |
0dfbf9d7 | 1180 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1181 | { |
1182 | case 3: | |
0dfbf9d7 | 1183 | if (x->array[2]) |
c6fb90c8 L |
1184 | return 0; |
1185 | case 2: | |
0dfbf9d7 | 1186 | if (x->array[1]) |
c6fb90c8 L |
1187 | return 0; |
1188 | case 1: | |
0dfbf9d7 | 1189 | return !x->array[0]; |
c6fb90c8 L |
1190 | default: |
1191 | abort (); | |
1192 | } | |
40fb9820 L |
1193 | } |
1194 | ||
c6fb90c8 | 1195 | static INLINE void |
0dfbf9d7 | 1196 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1197 | { |
0dfbf9d7 | 1198 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1199 | { |
1200 | case 3: | |
0dfbf9d7 | 1201 | x->array[2] = v; |
c6fb90c8 | 1202 | case 2: |
0dfbf9d7 | 1203 | x->array[1] = v; |
c6fb90c8 | 1204 | case 1: |
0dfbf9d7 | 1205 | x->array[0] = v; |
c6fb90c8 L |
1206 | break; |
1207 | default: | |
1208 | abort (); | |
1209 | } | |
1210 | } | |
40fb9820 | 1211 | |
c6fb90c8 | 1212 | static INLINE int |
0dfbf9d7 L |
1213 | operand_type_equal (const union i386_operand_type *x, |
1214 | const union i386_operand_type *y) | |
c6fb90c8 | 1215 | { |
0dfbf9d7 | 1216 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1217 | { |
1218 | case 3: | |
0dfbf9d7 | 1219 | if (x->array[2] != y->array[2]) |
c6fb90c8 L |
1220 | return 0; |
1221 | case 2: | |
0dfbf9d7 | 1222 | if (x->array[1] != y->array[1]) |
c6fb90c8 L |
1223 | return 0; |
1224 | case 1: | |
0dfbf9d7 | 1225 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1226 | break; |
1227 | default: | |
1228 | abort (); | |
1229 | } | |
1230 | } | |
40fb9820 | 1231 | |
0dfbf9d7 L |
1232 | static INLINE int |
1233 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1234 | { | |
1235 | switch (ARRAY_SIZE(x->array)) | |
1236 | { | |
1237 | case 3: | |
1238 | if (x->array[2]) | |
1239 | return 0; | |
1240 | case 2: | |
1241 | if (x->array[1]) | |
1242 | return 0; | |
1243 | case 1: | |
1244 | return !x->array[0]; | |
1245 | default: | |
1246 | abort (); | |
1247 | } | |
1248 | } | |
1249 | ||
1250 | static INLINE void | |
1251 | cpu_flags_set (union i386_cpu_flags *x, unsigned int v) | |
1252 | { | |
1253 | switch (ARRAY_SIZE(x->array)) | |
1254 | { | |
1255 | case 3: | |
1256 | x->array[2] = v; | |
1257 | case 2: | |
1258 | x->array[1] = v; | |
1259 | case 1: | |
1260 | x->array[0] = v; | |
1261 | break; | |
1262 | default: | |
1263 | abort (); | |
1264 | } | |
1265 | } | |
1266 | ||
1267 | static INLINE int | |
1268 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1269 | const union i386_cpu_flags *y) | |
1270 | { | |
1271 | switch (ARRAY_SIZE(x->array)) | |
1272 | { | |
1273 | case 3: | |
1274 | if (x->array[2] != y->array[2]) | |
1275 | return 0; | |
1276 | case 2: | |
1277 | if (x->array[1] != y->array[1]) | |
1278 | return 0; | |
1279 | case 1: | |
1280 | return x->array[0] == y->array[0]; | |
1281 | break; | |
1282 | default: | |
1283 | abort (); | |
1284 | } | |
1285 | } | |
c6fb90c8 L |
1286 | |
1287 | static INLINE int | |
1288 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1289 | { | |
1290 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1291 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1292 | } |
1293 | ||
c6fb90c8 L |
1294 | static INLINE i386_cpu_flags |
1295 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1296 | { |
c6fb90c8 L |
1297 | switch (ARRAY_SIZE (x.array)) |
1298 | { | |
1299 | case 3: | |
1300 | x.array [2] &= y.array [2]; | |
1301 | case 2: | |
1302 | x.array [1] &= y.array [1]; | |
1303 | case 1: | |
1304 | x.array [0] &= y.array [0]; | |
1305 | break; | |
1306 | default: | |
1307 | abort (); | |
1308 | } | |
1309 | return x; | |
1310 | } | |
40fb9820 | 1311 | |
c6fb90c8 L |
1312 | static INLINE i386_cpu_flags |
1313 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1314 | { |
c6fb90c8 | 1315 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1316 | { |
c6fb90c8 L |
1317 | case 3: |
1318 | x.array [2] |= y.array [2]; | |
1319 | case 2: | |
1320 | x.array [1] |= y.array [1]; | |
1321 | case 1: | |
1322 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1323 | break; |
1324 | default: | |
1325 | abort (); | |
1326 | } | |
40fb9820 L |
1327 | return x; |
1328 | } | |
1329 | ||
309d3373 JB |
1330 | static INLINE i386_cpu_flags |
1331 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1332 | { | |
1333 | switch (ARRAY_SIZE (x.array)) | |
1334 | { | |
1335 | case 3: | |
1336 | x.array [2] &= ~y.array [2]; | |
1337 | case 2: | |
1338 | x.array [1] &= ~y.array [1]; | |
1339 | case 1: | |
1340 | x.array [0] &= ~y.array [0]; | |
1341 | break; | |
1342 | default: | |
1343 | abort (); | |
1344 | } | |
1345 | return x; | |
1346 | } | |
1347 | ||
c0f3af97 L |
1348 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1349 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1350 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1351 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1352 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1353 | |
a5ff0eb2 | 1354 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1355 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1356 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1357 | #define CPU_FLAGS_PERFECT_MATCH \ |
1358 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1359 | ||
1360 | /* Return CPU flags match bits. */ | |
3629bb00 | 1361 | |
40fb9820 | 1362 | static int |
d3ce72d0 | 1363 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1364 | { |
c0f3af97 L |
1365 | i386_cpu_flags x = t->cpu_flags; |
1366 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1367 | |
1368 | x.bitfield.cpu64 = 0; | |
1369 | x.bitfield.cpuno64 = 0; | |
1370 | ||
0dfbf9d7 | 1371 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1372 | { |
1373 | /* This instruction is available on all archs. */ | |
1374 | match |= CPU_FLAGS_32BIT_MATCH; | |
1375 | } | |
3629bb00 L |
1376 | else |
1377 | { | |
c0f3af97 | 1378 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1379 | i386_cpu_flags cpu = cpu_arch_flags; |
1380 | ||
1381 | cpu.bitfield.cpu64 = 0; | |
1382 | cpu.bitfield.cpuno64 = 0; | |
1383 | cpu = cpu_flags_and (x, cpu); | |
c0f3af97 L |
1384 | if (!cpu_flags_all_zero (&cpu)) |
1385 | { | |
a5ff0eb2 L |
1386 | if (x.bitfield.cpuavx) |
1387 | { | |
ce2f5b3c | 1388 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1389 | if (cpu.bitfield.cpuavx) |
1390 | { | |
1391 | /* Check SSE2AVX. */ | |
1392 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1393 | { | |
1394 | match |= (CPU_FLAGS_ARCH_MATCH | |
1395 | | CPU_FLAGS_AVX_MATCH); | |
1396 | /* Check AES. */ | |
1397 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1398 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1399 | /* Check PCLMUL. */ |
1400 | if (!x.bitfield.cpupclmul | |
1401 | || cpu.bitfield.cpupclmul) | |
1402 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1403 | } |
1404 | } | |
1405 | else | |
1406 | match |= CPU_FLAGS_ARCH_MATCH; | |
1407 | } | |
1408 | else | |
c0f3af97 L |
1409 | match |= CPU_FLAGS_32BIT_MATCH; |
1410 | } | |
3629bb00 | 1411 | } |
c0f3af97 | 1412 | return match; |
40fb9820 L |
1413 | } |
1414 | ||
c6fb90c8 L |
1415 | static INLINE i386_operand_type |
1416 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1417 | { |
c6fb90c8 L |
1418 | switch (ARRAY_SIZE (x.array)) |
1419 | { | |
1420 | case 3: | |
1421 | x.array [2] &= y.array [2]; | |
1422 | case 2: | |
1423 | x.array [1] &= y.array [1]; | |
1424 | case 1: | |
1425 | x.array [0] &= y.array [0]; | |
1426 | break; | |
1427 | default: | |
1428 | abort (); | |
1429 | } | |
1430 | return x; | |
40fb9820 L |
1431 | } |
1432 | ||
c6fb90c8 L |
1433 | static INLINE i386_operand_type |
1434 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1435 | { |
c6fb90c8 | 1436 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1437 | { |
c6fb90c8 L |
1438 | case 3: |
1439 | x.array [2] |= y.array [2]; | |
1440 | case 2: | |
1441 | x.array [1] |= y.array [1]; | |
1442 | case 1: | |
1443 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1444 | break; |
1445 | default: | |
1446 | abort (); | |
1447 | } | |
c6fb90c8 L |
1448 | return x; |
1449 | } | |
40fb9820 | 1450 | |
c6fb90c8 L |
1451 | static INLINE i386_operand_type |
1452 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1453 | { | |
1454 | switch (ARRAY_SIZE (x.array)) | |
1455 | { | |
1456 | case 3: | |
1457 | x.array [2] ^= y.array [2]; | |
1458 | case 2: | |
1459 | x.array [1] ^= y.array [1]; | |
1460 | case 1: | |
1461 | x.array [0] ^= y.array [0]; | |
1462 | break; | |
1463 | default: | |
1464 | abort (); | |
1465 | } | |
40fb9820 L |
1466 | return x; |
1467 | } | |
1468 | ||
1469 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1470 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1471 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1472 | static const i386_operand_type inoutportreg |
1473 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1474 | static const i386_operand_type reg16_inoutportreg |
1475 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1476 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1477 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1478 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1479 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1480 | static const i386_operand_type anydisp | |
1481 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1482 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
c0f3af97 | 1483 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
40fb9820 L |
1484 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1485 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1486 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1487 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1488 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1489 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1490 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1491 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1492 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1493 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1494 | |
1495 | enum operand_type | |
1496 | { | |
1497 | reg, | |
40fb9820 L |
1498 | imm, |
1499 | disp, | |
1500 | anymem | |
1501 | }; | |
1502 | ||
c6fb90c8 | 1503 | static INLINE int |
40fb9820 L |
1504 | operand_type_check (i386_operand_type t, enum operand_type c) |
1505 | { | |
1506 | switch (c) | |
1507 | { | |
1508 | case reg: | |
1509 | return (t.bitfield.reg8 | |
1510 | || t.bitfield.reg16 | |
1511 | || t.bitfield.reg32 | |
1512 | || t.bitfield.reg64); | |
1513 | ||
40fb9820 L |
1514 | case imm: |
1515 | return (t.bitfield.imm8 | |
1516 | || t.bitfield.imm8s | |
1517 | || t.bitfield.imm16 | |
1518 | || t.bitfield.imm32 | |
1519 | || t.bitfield.imm32s | |
1520 | || t.bitfield.imm64); | |
1521 | ||
1522 | case disp: | |
1523 | return (t.bitfield.disp8 | |
1524 | || t.bitfield.disp16 | |
1525 | || t.bitfield.disp32 | |
1526 | || t.bitfield.disp32s | |
1527 | || t.bitfield.disp64); | |
1528 | ||
1529 | case anymem: | |
1530 | return (t.bitfield.disp8 | |
1531 | || t.bitfield.disp16 | |
1532 | || t.bitfield.disp32 | |
1533 | || t.bitfield.disp32s | |
1534 | || t.bitfield.disp64 | |
1535 | || t.bitfield.baseindex); | |
1536 | ||
1537 | default: | |
1538 | abort (); | |
1539 | } | |
2cfe26b6 AM |
1540 | |
1541 | return 0; | |
40fb9820 L |
1542 | } |
1543 | ||
5c07affc L |
1544 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1545 | operand J for instruction template T. */ | |
1546 | ||
1547 | static INLINE int | |
d3ce72d0 | 1548 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1549 | { |
1550 | return !((i.types[j].bitfield.byte | |
1551 | && !t->operand_types[j].bitfield.byte) | |
1552 | || (i.types[j].bitfield.word | |
1553 | && !t->operand_types[j].bitfield.word) | |
1554 | || (i.types[j].bitfield.dword | |
1555 | && !t->operand_types[j].bitfield.dword) | |
1556 | || (i.types[j].bitfield.qword | |
1557 | && !t->operand_types[j].bitfield.qword)); | |
1558 | } | |
1559 | ||
1560 | /* Return 1 if there is no conflict in any size on operand J for | |
1561 | instruction template T. */ | |
1562 | ||
1563 | static INLINE int | |
d3ce72d0 | 1564 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1565 | { |
1566 | return (match_reg_size (t, j) | |
1567 | && !((i.types[j].bitfield.unspecified | |
1568 | && !t->operand_types[j].bitfield.unspecified) | |
1569 | || (i.types[j].bitfield.fword | |
1570 | && !t->operand_types[j].bitfield.fword) | |
1571 | || (i.types[j].bitfield.tbyte | |
1572 | && !t->operand_types[j].bitfield.tbyte) | |
1573 | || (i.types[j].bitfield.xmmword | |
c0f3af97 L |
1574 | && !t->operand_types[j].bitfield.xmmword) |
1575 | || (i.types[j].bitfield.ymmword | |
1576 | && !t->operand_types[j].bitfield.ymmword))); | |
5c07affc L |
1577 | } |
1578 | ||
1579 | /* Return 1 if there is no size conflict on any operands for | |
1580 | instruction template T. */ | |
1581 | ||
1582 | static INLINE int | |
d3ce72d0 | 1583 | operand_size_match (const insn_template *t) |
5c07affc L |
1584 | { |
1585 | unsigned int j; | |
1586 | int match = 1; | |
1587 | ||
1588 | /* Don't check jump instructions. */ | |
1589 | if (t->opcode_modifier.jump | |
1590 | || t->opcode_modifier.jumpbyte | |
1591 | || t->opcode_modifier.jumpdword | |
1592 | || t->opcode_modifier.jumpintersegment) | |
1593 | return match; | |
1594 | ||
1595 | /* Check memory and accumulator operand size. */ | |
1596 | for (j = 0; j < i.operands; j++) | |
1597 | { | |
1598 | if (t->operand_types[j].bitfield.anysize) | |
1599 | continue; | |
1600 | ||
1601 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1602 | { | |
1603 | match = 0; | |
1604 | break; | |
1605 | } | |
1606 | ||
1607 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1608 | { | |
1609 | match = 0; | |
1610 | break; | |
1611 | } | |
1612 | } | |
1613 | ||
891edac4 | 1614 | if (match) |
5c07affc | 1615 | return match; |
891edac4 L |
1616 | else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
1617 | { | |
1618 | mismatch: | |
86e026a4 | 1619 | i.error = operand_size_mismatch; |
891edac4 L |
1620 | return 0; |
1621 | } | |
5c07affc L |
1622 | |
1623 | /* Check reverse. */ | |
9c2799c2 | 1624 | gas_assert (i.operands == 2); |
5c07affc L |
1625 | |
1626 | match = 1; | |
1627 | for (j = 0; j < 2; j++) | |
1628 | { | |
1629 | if (t->operand_types[j].bitfield.acc | |
1630 | && !match_reg_size (t, j ? 0 : 1)) | |
891edac4 | 1631 | goto mismatch; |
5c07affc L |
1632 | |
1633 | if (i.types[j].bitfield.mem | |
1634 | && !match_mem_size (t, j ? 0 : 1)) | |
891edac4 | 1635 | goto mismatch; |
5c07affc L |
1636 | } |
1637 | ||
1638 | return match; | |
1639 | } | |
1640 | ||
c6fb90c8 | 1641 | static INLINE int |
40fb9820 L |
1642 | operand_type_match (i386_operand_type overlap, |
1643 | i386_operand_type given) | |
1644 | { | |
1645 | i386_operand_type temp = overlap; | |
1646 | ||
1647 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1648 | temp.bitfield.unspecified = 0; |
5c07affc L |
1649 | temp.bitfield.byte = 0; |
1650 | temp.bitfield.word = 0; | |
1651 | temp.bitfield.dword = 0; | |
1652 | temp.bitfield.fword = 0; | |
1653 | temp.bitfield.qword = 0; | |
1654 | temp.bitfield.tbyte = 0; | |
1655 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1656 | temp.bitfield.ymmword = 0; |
0dfbf9d7 | 1657 | if (operand_type_all_zero (&temp)) |
891edac4 | 1658 | goto mismatch; |
40fb9820 | 1659 | |
891edac4 L |
1660 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
1661 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
1662 | return 1; | |
1663 | ||
1664 | mismatch: | |
a65babc9 | 1665 | i.error = operand_type_mismatch; |
891edac4 | 1666 | return 0; |
40fb9820 L |
1667 | } |
1668 | ||
7d5e4556 | 1669 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1670 | unless the expected operand type register overlap is null. |
1671 | Note that Acc in a template matches every size of reg. */ | |
1672 | ||
c6fb90c8 | 1673 | static INLINE int |
40fb9820 L |
1674 | operand_type_register_match (i386_operand_type m0, |
1675 | i386_operand_type g0, | |
1676 | i386_operand_type t0, | |
1677 | i386_operand_type m1, | |
1678 | i386_operand_type g1, | |
1679 | i386_operand_type t1) | |
1680 | { | |
1681 | if (!operand_type_check (g0, reg)) | |
1682 | return 1; | |
1683 | ||
1684 | if (!operand_type_check (g1, reg)) | |
1685 | return 1; | |
1686 | ||
1687 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1688 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1689 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1690 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1691 | return 1; | |
1692 | ||
1693 | if (m0.bitfield.acc) | |
1694 | { | |
1695 | t0.bitfield.reg8 = 1; | |
1696 | t0.bitfield.reg16 = 1; | |
1697 | t0.bitfield.reg32 = 1; | |
1698 | t0.bitfield.reg64 = 1; | |
1699 | } | |
1700 | ||
1701 | if (m1.bitfield.acc) | |
1702 | { | |
1703 | t1.bitfield.reg8 = 1; | |
1704 | t1.bitfield.reg16 = 1; | |
1705 | t1.bitfield.reg32 = 1; | |
1706 | t1.bitfield.reg64 = 1; | |
1707 | } | |
1708 | ||
891edac4 L |
1709 | if (!(t0.bitfield.reg8 & t1.bitfield.reg8) |
1710 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1711 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1712 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)) | |
1713 | return 1; | |
1714 | ||
a65babc9 | 1715 | i.error = register_type_mismatch; |
891edac4 L |
1716 | |
1717 | return 0; | |
40fb9820 L |
1718 | } |
1719 | ||
252b5132 | 1720 | static INLINE unsigned int |
40fb9820 | 1721 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1722 | { |
40fb9820 L |
1723 | if (t.bitfield.disp8) |
1724 | return 1; | |
1725 | else if (t.bitfield.disp16 | |
1726 | || t.bitfield.disp32 | |
1727 | || t.bitfield.disp32s) | |
1728 | return 2; | |
1729 | else | |
1730 | return 0; | |
252b5132 RH |
1731 | } |
1732 | ||
1733 | static INLINE int | |
e3bb37b5 | 1734 | fits_in_signed_byte (offsetT num) |
252b5132 RH |
1735 | { |
1736 | return (num >= -128) && (num <= 127); | |
47926f60 | 1737 | } |
252b5132 RH |
1738 | |
1739 | static INLINE int | |
e3bb37b5 | 1740 | fits_in_unsigned_byte (offsetT num) |
252b5132 RH |
1741 | { |
1742 | return (num & 0xff) == num; | |
47926f60 | 1743 | } |
252b5132 RH |
1744 | |
1745 | static INLINE int | |
e3bb37b5 | 1746 | fits_in_unsigned_word (offsetT num) |
252b5132 RH |
1747 | { |
1748 | return (num & 0xffff) == num; | |
47926f60 | 1749 | } |
252b5132 RH |
1750 | |
1751 | static INLINE int | |
e3bb37b5 | 1752 | fits_in_signed_word (offsetT num) |
252b5132 RH |
1753 | { |
1754 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 1755 | } |
2a962e6d | 1756 | |
3e73aa7c | 1757 | static INLINE int |
e3bb37b5 | 1758 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1759 | { |
1760 | #ifndef BFD64 | |
1761 | return 1; | |
1762 | #else | |
1763 | return (!(((offsetT) -1 << 31) & num) | |
1764 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
1765 | #endif | |
1766 | } /* fits_in_signed_long() */ | |
2a962e6d | 1767 | |
3e73aa7c | 1768 | static INLINE int |
e3bb37b5 | 1769 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1770 | { |
1771 | #ifndef BFD64 | |
1772 | return 1; | |
1773 | #else | |
1774 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
1775 | #endif | |
1776 | } /* fits_in_unsigned_long() */ | |
252b5132 | 1777 | |
a683cc34 SP |
1778 | static INLINE int |
1779 | fits_in_imm4 (offsetT num) | |
1780 | { | |
1781 | return (num & 0xf) == num; | |
1782 | } | |
1783 | ||
40fb9820 | 1784 | static i386_operand_type |
e3bb37b5 | 1785 | smallest_imm_type (offsetT num) |
252b5132 | 1786 | { |
40fb9820 | 1787 | i386_operand_type t; |
7ab9ffdd | 1788 | |
0dfbf9d7 | 1789 | operand_type_set (&t, 0); |
40fb9820 L |
1790 | t.bitfield.imm64 = 1; |
1791 | ||
1792 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
1793 | { |
1794 | /* This code is disabled on the 486 because all the Imm1 forms | |
1795 | in the opcode table are slower on the i486. They're the | |
1796 | versions with the implicitly specified single-position | |
1797 | displacement, which has another syntax if you really want to | |
1798 | use that form. */ | |
40fb9820 L |
1799 | t.bitfield.imm1 = 1; |
1800 | t.bitfield.imm8 = 1; | |
1801 | t.bitfield.imm8s = 1; | |
1802 | t.bitfield.imm16 = 1; | |
1803 | t.bitfield.imm32 = 1; | |
1804 | t.bitfield.imm32s = 1; | |
1805 | } | |
1806 | else if (fits_in_signed_byte (num)) | |
1807 | { | |
1808 | t.bitfield.imm8 = 1; | |
1809 | t.bitfield.imm8s = 1; | |
1810 | t.bitfield.imm16 = 1; | |
1811 | t.bitfield.imm32 = 1; | |
1812 | t.bitfield.imm32s = 1; | |
1813 | } | |
1814 | else if (fits_in_unsigned_byte (num)) | |
1815 | { | |
1816 | t.bitfield.imm8 = 1; | |
1817 | t.bitfield.imm16 = 1; | |
1818 | t.bitfield.imm32 = 1; | |
1819 | t.bitfield.imm32s = 1; | |
1820 | } | |
1821 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
1822 | { | |
1823 | t.bitfield.imm16 = 1; | |
1824 | t.bitfield.imm32 = 1; | |
1825 | t.bitfield.imm32s = 1; | |
1826 | } | |
1827 | else if (fits_in_signed_long (num)) | |
1828 | { | |
1829 | t.bitfield.imm32 = 1; | |
1830 | t.bitfield.imm32s = 1; | |
1831 | } | |
1832 | else if (fits_in_unsigned_long (num)) | |
1833 | t.bitfield.imm32 = 1; | |
1834 | ||
1835 | return t; | |
47926f60 | 1836 | } |
252b5132 | 1837 | |
847f7ad4 | 1838 | static offsetT |
e3bb37b5 | 1839 | offset_in_range (offsetT val, int size) |
847f7ad4 | 1840 | { |
508866be | 1841 | addressT mask; |
ba2adb93 | 1842 | |
847f7ad4 AM |
1843 | switch (size) |
1844 | { | |
508866be L |
1845 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
1846 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 1847 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
1848 | #ifdef BFD64 |
1849 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
1850 | #endif | |
47926f60 | 1851 | default: abort (); |
847f7ad4 AM |
1852 | } |
1853 | ||
9de868bf L |
1854 | #ifdef BFD64 |
1855 | /* If BFD64, sign extend val for 32bit address mode. */ | |
1856 | if (flag_code != CODE_64BIT | |
1857 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
1858 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
1859 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 1860 | #endif |
ba2adb93 | 1861 | |
47926f60 | 1862 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
1863 | { |
1864 | char buf1[40], buf2[40]; | |
1865 | ||
1866 | sprint_value (buf1, val); | |
1867 | sprint_value (buf2, val & mask); | |
1868 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
1869 | } | |
1870 | return val & mask; | |
1871 | } | |
1872 | ||
c32fa91d L |
1873 | enum PREFIX_GROUP |
1874 | { | |
1875 | PREFIX_EXIST = 0, | |
1876 | PREFIX_LOCK, | |
1877 | PREFIX_REP, | |
1878 | PREFIX_OTHER | |
1879 | }; | |
1880 | ||
1881 | /* Returns | |
1882 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
1883 | same class already exists. | |
1884 | b. PREFIX_LOCK if lock prefix is added. | |
1885 | c. PREFIX_REP if rep/repne prefix is added. | |
1886 | d. PREFIX_OTHER if other prefix is added. | |
1887 | */ | |
1888 | ||
1889 | static enum PREFIX_GROUP | |
e3bb37b5 | 1890 | add_prefix (unsigned int prefix) |
252b5132 | 1891 | { |
c32fa91d | 1892 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 1893 | unsigned int q; |
252b5132 | 1894 | |
29b0f896 AM |
1895 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
1896 | && flag_code == CODE_64BIT) | |
b1905489 | 1897 | { |
161a04f6 L |
1898 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
1899 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
1900 | && (prefix & (REX_R | REX_X | REX_B)))) | |
c32fa91d | 1901 | ret = PREFIX_EXIST; |
b1905489 JB |
1902 | q = REX_PREFIX; |
1903 | } | |
3e73aa7c | 1904 | else |
b1905489 JB |
1905 | { |
1906 | switch (prefix) | |
1907 | { | |
1908 | default: | |
1909 | abort (); | |
1910 | ||
1911 | case CS_PREFIX_OPCODE: | |
1912 | case DS_PREFIX_OPCODE: | |
1913 | case ES_PREFIX_OPCODE: | |
1914 | case FS_PREFIX_OPCODE: | |
1915 | case GS_PREFIX_OPCODE: | |
1916 | case SS_PREFIX_OPCODE: | |
1917 | q = SEG_PREFIX; | |
1918 | break; | |
1919 | ||
1920 | case REPNE_PREFIX_OPCODE: | |
1921 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
1922 | q = REP_PREFIX; |
1923 | ret = PREFIX_REP; | |
1924 | break; | |
1925 | ||
b1905489 | 1926 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
1927 | q = LOCK_PREFIX; |
1928 | ret = PREFIX_LOCK; | |
b1905489 JB |
1929 | break; |
1930 | ||
1931 | case FWAIT_OPCODE: | |
1932 | q = WAIT_PREFIX; | |
1933 | break; | |
1934 | ||
1935 | case ADDR_PREFIX_OPCODE: | |
1936 | q = ADDR_PREFIX; | |
1937 | break; | |
1938 | ||
1939 | case DATA_PREFIX_OPCODE: | |
1940 | q = DATA_PREFIX; | |
1941 | break; | |
1942 | } | |
1943 | if (i.prefix[q] != 0) | |
c32fa91d | 1944 | ret = PREFIX_EXIST; |
b1905489 | 1945 | } |
252b5132 | 1946 | |
b1905489 | 1947 | if (ret) |
252b5132 | 1948 | { |
b1905489 JB |
1949 | if (!i.prefix[q]) |
1950 | ++i.prefixes; | |
1951 | i.prefix[q] |= prefix; | |
252b5132 | 1952 | } |
b1905489 JB |
1953 | else |
1954 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 1955 | |
252b5132 RH |
1956 | return ret; |
1957 | } | |
1958 | ||
1959 | static void | |
78f12dd3 | 1960 | update_code_flag (int value, int check) |
eecb386c | 1961 | { |
78f12dd3 L |
1962 | PRINTF_LIKE ((*as_error)); |
1963 | ||
1e9cc1c2 | 1964 | flag_code = (enum flag_code) value; |
40fb9820 L |
1965 | if (flag_code == CODE_64BIT) |
1966 | { | |
1967 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1968 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
1969 | } |
1970 | else | |
1971 | { | |
1972 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1973 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
1974 | } |
1975 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 1976 | { |
78f12dd3 L |
1977 | if (check) |
1978 | as_error = as_fatal; | |
1979 | else | |
1980 | as_error = as_bad; | |
1981 | (*as_error) (_("64bit mode not supported on `%s'."), | |
1982 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 1983 | } |
40fb9820 | 1984 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 1985 | { |
78f12dd3 L |
1986 | if (check) |
1987 | as_error = as_fatal; | |
1988 | else | |
1989 | as_error = as_bad; | |
1990 | (*as_error) (_("32bit mode not supported on `%s'."), | |
1991 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 1992 | } |
eecb386c AM |
1993 | stackop_size = '\0'; |
1994 | } | |
1995 | ||
78f12dd3 L |
1996 | static void |
1997 | set_code_flag (int value) | |
1998 | { | |
1999 | update_code_flag (value, 0); | |
2000 | } | |
2001 | ||
eecb386c | 2002 | static void |
e3bb37b5 | 2003 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2004 | { |
1e9cc1c2 | 2005 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2006 | if (flag_code != CODE_16BIT) |
2007 | abort (); | |
2008 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2009 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2010 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2011 | } |
2012 | ||
2013 | static void | |
e3bb37b5 | 2014 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2015 | { |
2016 | /* Find out if register prefixing is specified. */ | |
2017 | int ask_naked_reg = 0; | |
2018 | ||
2019 | SKIP_WHITESPACE (); | |
29b0f896 | 2020 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
2021 | { |
2022 | char *string = input_line_pointer; | |
2023 | int e = get_symbol_end (); | |
2024 | ||
47926f60 | 2025 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2026 | ask_naked_reg = 1; |
47926f60 | 2027 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2028 | ask_naked_reg = -1; |
2029 | else | |
d0b47220 | 2030 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
2031 | *input_line_pointer = e; |
2032 | } | |
2033 | demand_empty_rest_of_line (); | |
c3332e24 | 2034 | |
252b5132 RH |
2035 | intel_syntax = syntax_flag; |
2036 | ||
2037 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2038 | allow_naked_reg = (intel_syntax |
2039 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2040 | else |
2041 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2042 | |
ee86248c | 2043 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2044 | |
e4a3b5a4 | 2045 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2046 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2047 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2048 | } |
2049 | ||
1efbbeb4 L |
2050 | static void |
2051 | set_intel_mnemonic (int mnemonic_flag) | |
2052 | { | |
e1d4d893 | 2053 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2054 | } |
2055 | ||
db51cc60 L |
2056 | static void |
2057 | set_allow_index_reg (int flag) | |
2058 | { | |
2059 | allow_index_reg = flag; | |
2060 | } | |
2061 | ||
cb19c032 L |
2062 | static void |
2063 | set_sse_check (int dummy ATTRIBUTE_UNUSED) | |
2064 | { | |
2065 | SKIP_WHITESPACE (); | |
2066 | ||
2067 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2068 | { | |
2069 | char *string = input_line_pointer; | |
2070 | int e = get_symbol_end (); | |
2071 | ||
2072 | if (strcmp (string, "none") == 0) | |
2073 | sse_check = sse_check_none; | |
2074 | else if (strcmp (string, "warning") == 0) | |
2075 | sse_check = sse_check_warning; | |
2076 | else if (strcmp (string, "error") == 0) | |
2077 | sse_check = sse_check_error; | |
2078 | else | |
2079 | as_bad (_("bad argument to sse_check directive.")); | |
2080 | *input_line_pointer = e; | |
2081 | } | |
2082 | else | |
2083 | as_bad (_("missing argument for sse_check directive")); | |
2084 | ||
2085 | demand_empty_rest_of_line (); | |
2086 | } | |
2087 | ||
8a9036a4 L |
2088 | static void |
2089 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2090 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2091 | { |
2092 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2093 | static const char *arch; | |
2094 | ||
2095 | /* Intel LIOM is only supported on ELF. */ | |
2096 | if (!IS_ELF) | |
2097 | return; | |
2098 | ||
2099 | if (!arch) | |
2100 | { | |
2101 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2102 | use default_arch. */ | |
2103 | arch = cpu_arch_name; | |
2104 | if (!arch) | |
2105 | arch = default_arch; | |
2106 | } | |
2107 | ||
3632d14b | 2108 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2109 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2110 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2111 | return; |
76ba9986 | 2112 | |
8a9036a4 L |
2113 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2114 | #endif | |
2115 | } | |
2116 | ||
e413e4e9 | 2117 | static void |
e3bb37b5 | 2118 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2119 | { |
47926f60 | 2120 | SKIP_WHITESPACE (); |
e413e4e9 | 2121 | |
29b0f896 | 2122 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
2123 | { |
2124 | char *string = input_line_pointer; | |
2125 | int e = get_symbol_end (); | |
91d6fa6a | 2126 | unsigned int j; |
40fb9820 | 2127 | i386_cpu_flags flags; |
e413e4e9 | 2128 | |
91d6fa6a | 2129 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2130 | { |
91d6fa6a | 2131 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2132 | { |
91d6fa6a | 2133 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2134 | |
5c6af06e JB |
2135 | if (*string != '.') |
2136 | { | |
91d6fa6a | 2137 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2138 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2139 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2140 | if (flag_code == CODE_64BIT) |
2141 | { | |
2142 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2143 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2144 | } | |
2145 | else | |
2146 | { | |
2147 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2148 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2149 | } | |
91d6fa6a NC |
2150 | cpu_arch_isa = cpu_arch[j].type; |
2151 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2152 | if (!cpu_arch_tune_set) |
2153 | { | |
2154 | cpu_arch_tune = cpu_arch_isa; | |
2155 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2156 | } | |
5c6af06e JB |
2157 | break; |
2158 | } | |
40fb9820 | 2159 | |
22109423 | 2160 | if (!cpu_arch[j].negated) |
309d3373 | 2161 | flags = cpu_flags_or (cpu_arch_flags, |
91d6fa6a | 2162 | cpu_arch[j].flags); |
309d3373 JB |
2163 | else |
2164 | flags = cpu_flags_and_not (cpu_arch_flags, | |
49021df2 | 2165 | cpu_arch[j].flags); |
0dfbf9d7 | 2166 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2167 | { |
6305a203 L |
2168 | if (cpu_sub_arch_name) |
2169 | { | |
2170 | char *name = cpu_sub_arch_name; | |
2171 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2172 | cpu_arch[j].name, |
1bf57e9f | 2173 | (const char *) NULL); |
6305a203 L |
2174 | free (name); |
2175 | } | |
2176 | else | |
91d6fa6a | 2177 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2178 | cpu_arch_flags = flags; |
a586129e | 2179 | cpu_arch_isa_flags = flags; |
5c6af06e JB |
2180 | } |
2181 | *input_line_pointer = e; | |
2182 | demand_empty_rest_of_line (); | |
2183 | return; | |
e413e4e9 AM |
2184 | } |
2185 | } | |
91d6fa6a | 2186 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2187 | as_bad (_("no such architecture: `%s'"), string); |
2188 | ||
2189 | *input_line_pointer = e; | |
2190 | } | |
2191 | else | |
2192 | as_bad (_("missing cpu architecture")); | |
2193 | ||
fddf5b5b AM |
2194 | no_cond_jump_promotion = 0; |
2195 | if (*input_line_pointer == ',' | |
29b0f896 | 2196 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
2197 | { |
2198 | char *string = ++input_line_pointer; | |
2199 | int e = get_symbol_end (); | |
2200 | ||
2201 | if (strcmp (string, "nojumps") == 0) | |
2202 | no_cond_jump_promotion = 1; | |
2203 | else if (strcmp (string, "jumps") == 0) | |
2204 | ; | |
2205 | else | |
2206 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2207 | ||
2208 | *input_line_pointer = e; | |
2209 | } | |
2210 | ||
e413e4e9 AM |
2211 | demand_empty_rest_of_line (); |
2212 | } | |
2213 | ||
8a9036a4 L |
2214 | enum bfd_architecture |
2215 | i386_arch (void) | |
2216 | { | |
3632d14b | 2217 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2218 | { |
2219 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2220 | || flag_code != CODE_64BIT) | |
2221 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2222 | return bfd_arch_l1om; | |
2223 | } | |
2224 | else | |
2225 | return bfd_arch_i386; | |
2226 | } | |
2227 | ||
b9d79e03 JH |
2228 | unsigned long |
2229 | i386_mach () | |
2230 | { | |
351f65ca | 2231 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2232 | { |
3632d14b | 2233 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2234 | { |
351f65ca L |
2235 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2236 | || default_arch[6] != '\0') | |
8a9036a4 L |
2237 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2238 | return bfd_mach_l1om; | |
2239 | } | |
351f65ca | 2240 | else if (default_arch[6] == '\0') |
8a9036a4 | 2241 | return bfd_mach_x86_64; |
351f65ca L |
2242 | else |
2243 | return bfd_mach_x64_32; | |
8a9036a4 | 2244 | } |
b9d79e03 JH |
2245 | else if (!strcmp (default_arch, "i386")) |
2246 | return bfd_mach_i386_i386; | |
2247 | else | |
2248 | as_fatal (_("Unknown architecture")); | |
2249 | } | |
b9d79e03 | 2250 | \f |
252b5132 RH |
2251 | void |
2252 | md_begin () | |
2253 | { | |
2254 | const char *hash_err; | |
2255 | ||
47926f60 | 2256 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2257 | op_hash = hash_new (); |
2258 | ||
2259 | { | |
d3ce72d0 | 2260 | const insn_template *optab; |
29b0f896 | 2261 | templates *core_optab; |
252b5132 | 2262 | |
47926f60 KH |
2263 | /* Setup for loop. */ |
2264 | optab = i386_optab; | |
252b5132 RH |
2265 | core_optab = (templates *) xmalloc (sizeof (templates)); |
2266 | core_optab->start = optab; | |
2267 | ||
2268 | while (1) | |
2269 | { | |
2270 | ++optab; | |
2271 | if (optab->name == NULL | |
2272 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2273 | { | |
2274 | /* different name --> ship out current template list; | |
47926f60 | 2275 | add to hash table; & begin anew. */ |
252b5132 RH |
2276 | core_optab->end = optab; |
2277 | hash_err = hash_insert (op_hash, | |
2278 | (optab - 1)->name, | |
5a49b8ac | 2279 | (void *) core_optab); |
252b5132 RH |
2280 | if (hash_err) |
2281 | { | |
252b5132 RH |
2282 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
2283 | (optab - 1)->name, | |
2284 | hash_err); | |
2285 | } | |
2286 | if (optab->name == NULL) | |
2287 | break; | |
2288 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
2289 | core_optab->start = optab; | |
2290 | } | |
2291 | } | |
2292 | } | |
2293 | ||
47926f60 | 2294 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2295 | reg_hash = hash_new (); |
2296 | { | |
29b0f896 | 2297 | const reg_entry *regtab; |
c3fe08fa | 2298 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2299 | |
c3fe08fa | 2300 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2301 | { |
5a49b8ac | 2302 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2303 | if (hash_err) |
3e73aa7c JH |
2304 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
2305 | regtab->reg_name, | |
2306 | hash_err); | |
252b5132 RH |
2307 | } |
2308 | } | |
2309 | ||
47926f60 | 2310 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2311 | { |
29b0f896 AM |
2312 | int c; |
2313 | char *p; | |
252b5132 RH |
2314 | |
2315 | for (c = 0; c < 256; c++) | |
2316 | { | |
3882b010 | 2317 | if (ISDIGIT (c)) |
252b5132 RH |
2318 | { |
2319 | digit_chars[c] = c; | |
2320 | mnemonic_chars[c] = c; | |
2321 | register_chars[c] = c; | |
2322 | operand_chars[c] = c; | |
2323 | } | |
3882b010 | 2324 | else if (ISLOWER (c)) |
252b5132 RH |
2325 | { |
2326 | mnemonic_chars[c] = c; | |
2327 | register_chars[c] = c; | |
2328 | operand_chars[c] = c; | |
2329 | } | |
3882b010 | 2330 | else if (ISUPPER (c)) |
252b5132 | 2331 | { |
3882b010 | 2332 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2333 | register_chars[c] = mnemonic_chars[c]; |
2334 | operand_chars[c] = c; | |
2335 | } | |
2336 | ||
3882b010 | 2337 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2338 | identifier_chars[c] = c; |
2339 | else if (c >= 128) | |
2340 | { | |
2341 | identifier_chars[c] = c; | |
2342 | operand_chars[c] = c; | |
2343 | } | |
2344 | } | |
2345 | ||
2346 | #ifdef LEX_AT | |
2347 | identifier_chars['@'] = '@'; | |
32137342 NC |
2348 | #endif |
2349 | #ifdef LEX_QM | |
2350 | identifier_chars['?'] = '?'; | |
2351 | operand_chars['?'] = '?'; | |
252b5132 | 2352 | #endif |
252b5132 | 2353 | digit_chars['-'] = '-'; |
c0f3af97 | 2354 | mnemonic_chars['_'] = '_'; |
791fe849 | 2355 | mnemonic_chars['-'] = '-'; |
0003779b | 2356 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2357 | identifier_chars['_'] = '_'; |
2358 | identifier_chars['.'] = '.'; | |
2359 | ||
2360 | for (p = operand_special_chars; *p != '\0'; p++) | |
2361 | operand_chars[(unsigned char) *p] = *p; | |
2362 | } | |
2363 | ||
2364 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 2365 | if (IS_ELF) |
252b5132 RH |
2366 | { |
2367 | record_alignment (text_section, 2); | |
2368 | record_alignment (data_section, 2); | |
2369 | record_alignment (bss_section, 2); | |
2370 | } | |
2371 | #endif | |
a4447b93 RH |
2372 | |
2373 | if (flag_code == CODE_64BIT) | |
2374 | { | |
ca19b261 KT |
2375 | #if defined (OBJ_COFF) && defined (TE_PE) |
2376 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2377 | ? 32 : 16); | |
2378 | #else | |
a4447b93 | 2379 | x86_dwarf2_return_column = 16; |
ca19b261 | 2380 | #endif |
61ff971f | 2381 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2382 | } |
2383 | else | |
2384 | { | |
2385 | x86_dwarf2_return_column = 8; | |
2386 | x86_cie_data_alignment = -4; | |
2387 | } | |
252b5132 RH |
2388 | } |
2389 | ||
2390 | void | |
e3bb37b5 | 2391 | i386_print_statistics (FILE *file) |
252b5132 RH |
2392 | { |
2393 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2394 | hash_print_statistics (file, "i386 register", reg_hash); | |
2395 | } | |
2396 | \f | |
252b5132 RH |
2397 | #ifdef DEBUG386 |
2398 | ||
ce8a8b2f | 2399 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2400 | static void pte (insn_template *); |
40fb9820 | 2401 | static void pt (i386_operand_type); |
e3bb37b5 L |
2402 | static void pe (expressionS *); |
2403 | static void ps (symbolS *); | |
252b5132 RH |
2404 | |
2405 | static void | |
e3bb37b5 | 2406 | pi (char *line, i386_insn *x) |
252b5132 | 2407 | { |
09137c09 | 2408 | unsigned int j; |
252b5132 RH |
2409 | |
2410 | fprintf (stdout, "%s: template ", line); | |
2411 | pte (&x->tm); | |
09f131f2 JH |
2412 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2413 | x->base_reg ? x->base_reg->reg_name : "none", | |
2414 | x->index_reg ? x->index_reg->reg_name : "none", | |
2415 | x->log2_scale_factor); | |
2416 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2417 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2418 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2419 | x->sib.base, x->sib.index, x->sib.scale); | |
2420 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2421 | (x->rex & REX_W) != 0, |
2422 | (x->rex & REX_R) != 0, | |
2423 | (x->rex & REX_X) != 0, | |
2424 | (x->rex & REX_B) != 0); | |
09137c09 | 2425 | for (j = 0; j < x->operands; j++) |
252b5132 | 2426 | { |
09137c09 SP |
2427 | fprintf (stdout, " #%d: ", j + 1); |
2428 | pt (x->types[j]); | |
252b5132 | 2429 | fprintf (stdout, "\n"); |
09137c09 SP |
2430 | if (x->types[j].bitfield.reg8 |
2431 | || x->types[j].bitfield.reg16 | |
2432 | || x->types[j].bitfield.reg32 | |
2433 | || x->types[j].bitfield.reg64 | |
2434 | || x->types[j].bitfield.regmmx | |
2435 | || x->types[j].bitfield.regxmm | |
2436 | || x->types[j].bitfield.regymm | |
2437 | || x->types[j].bitfield.sreg2 | |
2438 | || x->types[j].bitfield.sreg3 | |
2439 | || x->types[j].bitfield.control | |
2440 | || x->types[j].bitfield.debug | |
2441 | || x->types[j].bitfield.test) | |
2442 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2443 | if (operand_type_check (x->types[j], imm)) | |
2444 | pe (x->op[j].imms); | |
2445 | if (operand_type_check (x->types[j], disp)) | |
2446 | pe (x->op[j].disps); | |
252b5132 RH |
2447 | } |
2448 | } | |
2449 | ||
2450 | static void | |
d3ce72d0 | 2451 | pte (insn_template *t) |
252b5132 | 2452 | { |
09137c09 | 2453 | unsigned int j; |
252b5132 | 2454 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2455 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2456 | if (t->extension_opcode != None) |
2457 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2458 | if (t->opcode_modifier.d) |
252b5132 | 2459 | fprintf (stdout, "D"); |
40fb9820 | 2460 | if (t->opcode_modifier.w) |
252b5132 RH |
2461 | fprintf (stdout, "W"); |
2462 | fprintf (stdout, "\n"); | |
09137c09 | 2463 | for (j = 0; j < t->operands; j++) |
252b5132 | 2464 | { |
09137c09 SP |
2465 | fprintf (stdout, " #%d type ", j + 1); |
2466 | pt (t->operand_types[j]); | |
252b5132 RH |
2467 | fprintf (stdout, "\n"); |
2468 | } | |
2469 | } | |
2470 | ||
2471 | static void | |
e3bb37b5 | 2472 | pe (expressionS *e) |
252b5132 | 2473 | { |
24eab124 | 2474 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2475 | fprintf (stdout, " add_number %ld (%lx)\n", |
2476 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2477 | if (e->X_add_symbol) |
2478 | { | |
2479 | fprintf (stdout, " add_symbol "); | |
2480 | ps (e->X_add_symbol); | |
2481 | fprintf (stdout, "\n"); | |
2482 | } | |
2483 | if (e->X_op_symbol) | |
2484 | { | |
2485 | fprintf (stdout, " op_symbol "); | |
2486 | ps (e->X_op_symbol); | |
2487 | fprintf (stdout, "\n"); | |
2488 | } | |
2489 | } | |
2490 | ||
2491 | static void | |
e3bb37b5 | 2492 | ps (symbolS *s) |
252b5132 RH |
2493 | { |
2494 | fprintf (stdout, "%s type %s%s", | |
2495 | S_GET_NAME (s), | |
2496 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2497 | segment_name (S_GET_SEGMENT (s))); | |
2498 | } | |
2499 | ||
7b81dfbb | 2500 | static struct type_name |
252b5132 | 2501 | { |
40fb9820 L |
2502 | i386_operand_type mask; |
2503 | const char *name; | |
252b5132 | 2504 | } |
7b81dfbb | 2505 | const type_names[] = |
252b5132 | 2506 | { |
40fb9820 L |
2507 | { OPERAND_TYPE_REG8, "r8" }, |
2508 | { OPERAND_TYPE_REG16, "r16" }, | |
2509 | { OPERAND_TYPE_REG32, "r32" }, | |
2510 | { OPERAND_TYPE_REG64, "r64" }, | |
2511 | { OPERAND_TYPE_IMM8, "i8" }, | |
2512 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2513 | { OPERAND_TYPE_IMM16, "i16" }, | |
2514 | { OPERAND_TYPE_IMM32, "i32" }, | |
2515 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2516 | { OPERAND_TYPE_IMM64, "i64" }, | |
2517 | { OPERAND_TYPE_IMM1, "i1" }, | |
2518 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2519 | { OPERAND_TYPE_DISP8, "d8" }, | |
2520 | { OPERAND_TYPE_DISP16, "d16" }, | |
2521 | { OPERAND_TYPE_DISP32, "d32" }, | |
2522 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2523 | { OPERAND_TYPE_DISP64, "d64" }, | |
2524 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
2525 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2526 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2527 | { OPERAND_TYPE_TEST, "test reg" }, | |
2528 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2529 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2530 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2531 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2532 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2533 | { OPERAND_TYPE_ACC, "Acc" }, | |
2534 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2535 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2536 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 2537 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
40fb9820 | 2538 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
2539 | }; |
2540 | ||
2541 | static void | |
40fb9820 | 2542 | pt (i386_operand_type t) |
252b5132 | 2543 | { |
40fb9820 | 2544 | unsigned int j; |
c6fb90c8 | 2545 | i386_operand_type a; |
252b5132 | 2546 | |
40fb9820 | 2547 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2548 | { |
2549 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 2550 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
2551 | fprintf (stdout, "%s, ", type_names[j].name); |
2552 | } | |
252b5132 RH |
2553 | fflush (stdout); |
2554 | } | |
2555 | ||
2556 | #endif /* DEBUG386 */ | |
2557 | \f | |
252b5132 | 2558 | static bfd_reloc_code_real_type |
3956db08 | 2559 | reloc (unsigned int size, |
64e74474 AM |
2560 | int pcrel, |
2561 | int sign, | |
2562 | bfd_reloc_code_real_type other) | |
252b5132 | 2563 | { |
47926f60 | 2564 | if (other != NO_RELOC) |
3956db08 | 2565 | { |
91d6fa6a | 2566 | reloc_howto_type *rel; |
3956db08 JB |
2567 | |
2568 | if (size == 8) | |
2569 | switch (other) | |
2570 | { | |
64e74474 AM |
2571 | case BFD_RELOC_X86_64_GOT32: |
2572 | return BFD_RELOC_X86_64_GOT64; | |
2573 | break; | |
2574 | case BFD_RELOC_X86_64_PLTOFF64: | |
2575 | return BFD_RELOC_X86_64_PLTOFF64; | |
2576 | break; | |
2577 | case BFD_RELOC_X86_64_GOTPC32: | |
2578 | other = BFD_RELOC_X86_64_GOTPC64; | |
2579 | break; | |
2580 | case BFD_RELOC_X86_64_GOTPCREL: | |
2581 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2582 | break; | |
2583 | case BFD_RELOC_X86_64_TPOFF32: | |
2584 | other = BFD_RELOC_X86_64_TPOFF64; | |
2585 | break; | |
2586 | case BFD_RELOC_X86_64_DTPOFF32: | |
2587 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2588 | break; | |
2589 | default: | |
2590 | break; | |
3956db08 | 2591 | } |
e05278af JB |
2592 | |
2593 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ | |
f2d8a97c | 2594 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
2595 | sign = -1; |
2596 | ||
91d6fa6a NC |
2597 | rel = bfd_reloc_type_lookup (stdoutput, other); |
2598 | if (!rel) | |
3956db08 | 2599 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 2600 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 2601 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 2602 | bfd_get_reloc_size (rel), |
3956db08 | 2603 | size); |
91d6fa6a | 2604 | else if (pcrel && !rel->pc_relative) |
3956db08 | 2605 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 2606 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 2607 | && !sign) |
91d6fa6a | 2608 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 2609 | && sign > 0)) |
3956db08 JB |
2610 | as_bad (_("relocated field and relocation type differ in signedness")); |
2611 | else | |
2612 | return other; | |
2613 | return NO_RELOC; | |
2614 | } | |
252b5132 RH |
2615 | |
2616 | if (pcrel) | |
2617 | { | |
3e73aa7c | 2618 | if (!sign) |
3956db08 | 2619 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2620 | switch (size) |
2621 | { | |
2622 | case 1: return BFD_RELOC_8_PCREL; | |
2623 | case 2: return BFD_RELOC_16_PCREL; | |
2624 | case 4: return BFD_RELOC_32_PCREL; | |
d6ab8113 | 2625 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2626 | } |
3956db08 | 2627 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2628 | } |
2629 | else | |
2630 | { | |
3956db08 | 2631 | if (sign > 0) |
e5cb08ac | 2632 | switch (size) |
3e73aa7c JH |
2633 | { |
2634 | case 4: return BFD_RELOC_X86_64_32S; | |
2635 | } | |
2636 | else | |
2637 | switch (size) | |
2638 | { | |
2639 | case 1: return BFD_RELOC_8; | |
2640 | case 2: return BFD_RELOC_16; | |
2641 | case 4: return BFD_RELOC_32; | |
2642 | case 8: return BFD_RELOC_64; | |
2643 | } | |
3956db08 JB |
2644 | as_bad (_("cannot do %s %u byte relocation"), |
2645 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
2646 | } |
2647 | ||
0cc9e1d3 | 2648 | return NO_RELOC; |
252b5132 RH |
2649 | } |
2650 | ||
47926f60 KH |
2651 | /* Here we decide which fixups can be adjusted to make them relative to |
2652 | the beginning of the section instead of the symbol. Basically we need | |
2653 | to make sure that the dynamic relocations are done correctly, so in | |
2654 | some cases we force the original symbol to be used. */ | |
2655 | ||
252b5132 | 2656 | int |
e3bb37b5 | 2657 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 2658 | { |
6d249963 | 2659 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 2660 | if (!IS_ELF) |
31312f95 AM |
2661 | return 1; |
2662 | ||
a161fe53 AM |
2663 | /* Don't adjust pc-relative references to merge sections in 64-bit |
2664 | mode. */ | |
2665 | if (use_rela_relocations | |
2666 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
2667 | && fixP->fx_pcrel) | |
252b5132 | 2668 | return 0; |
31312f95 | 2669 | |
8d01d9a9 AJ |
2670 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
2671 | and changed later by validate_fix. */ | |
2672 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
2673 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
2674 | return 0; | |
2675 | ||
ce8a8b2f | 2676 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
2677 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
2678 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
2679 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
2680 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
2681 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
2682 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
2683 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
2684 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
2685 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
2686 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
2687 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
2688 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
2689 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
2690 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
2691 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 2692 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
2693 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
2694 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
2695 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 2696 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
2697 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
2698 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
2699 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
2700 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
2701 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
2702 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
2703 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
2704 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2705 | return 0; | |
31312f95 | 2706 | #endif |
252b5132 RH |
2707 | return 1; |
2708 | } | |
252b5132 | 2709 | |
b4cac588 | 2710 | static int |
e3bb37b5 | 2711 | intel_float_operand (const char *mnemonic) |
252b5132 | 2712 | { |
9306ca4a JB |
2713 | /* Note that the value returned is meaningful only for opcodes with (memory) |
2714 | operands, hence the code here is free to improperly handle opcodes that | |
2715 | have no operands (for better performance and smaller code). */ | |
2716 | ||
2717 | if (mnemonic[0] != 'f') | |
2718 | return 0; /* non-math */ | |
2719 | ||
2720 | switch (mnemonic[1]) | |
2721 | { | |
2722 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
2723 | the fs segment override prefix not currently handled because no | |
2724 | call path can make opcodes without operands get here */ | |
2725 | case 'i': | |
2726 | return 2 /* integer op */; | |
2727 | case 'l': | |
2728 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
2729 | return 3; /* fldcw/fldenv */ | |
2730 | break; | |
2731 | case 'n': | |
2732 | if (mnemonic[2] != 'o' /* fnop */) | |
2733 | return 3; /* non-waiting control op */ | |
2734 | break; | |
2735 | case 'r': | |
2736 | if (mnemonic[2] == 's') | |
2737 | return 3; /* frstor/frstpm */ | |
2738 | break; | |
2739 | case 's': | |
2740 | if (mnemonic[2] == 'a') | |
2741 | return 3; /* fsave */ | |
2742 | if (mnemonic[2] == 't') | |
2743 | { | |
2744 | switch (mnemonic[3]) | |
2745 | { | |
2746 | case 'c': /* fstcw */ | |
2747 | case 'd': /* fstdw */ | |
2748 | case 'e': /* fstenv */ | |
2749 | case 's': /* fsts[gw] */ | |
2750 | return 3; | |
2751 | } | |
2752 | } | |
2753 | break; | |
2754 | case 'x': | |
2755 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
2756 | return 0; /* fxsave/fxrstor are not really math ops */ | |
2757 | break; | |
2758 | } | |
252b5132 | 2759 | |
9306ca4a | 2760 | return 1; |
252b5132 RH |
2761 | } |
2762 | ||
c0f3af97 L |
2763 | /* Build the VEX prefix. */ |
2764 | ||
2765 | static void | |
d3ce72d0 | 2766 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
2767 | { |
2768 | unsigned int register_specifier; | |
2769 | unsigned int implied_prefix; | |
2770 | unsigned int vector_length; | |
2771 | ||
2772 | /* Check register specifier. */ | |
2773 | if (i.vex.register_specifier) | |
2774 | { | |
2775 | register_specifier = i.vex.register_specifier->reg_num; | |
2776 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
2777 | register_specifier += 8; | |
2778 | register_specifier = ~register_specifier & 0xf; | |
2779 | } | |
2780 | else | |
2781 | register_specifier = 0xf; | |
2782 | ||
fa99fab2 L |
2783 | /* Use 2-byte VEX prefix by swappping destination and source |
2784 | operand. */ | |
2785 | if (!i.swap_operand | |
2786 | && i.operands == i.reg_operands | |
7f399153 | 2787 | && i.tm.opcode_modifier.vexopcode == VEX0F |
fa99fab2 L |
2788 | && i.tm.opcode_modifier.s |
2789 | && i.rex == REX_B) | |
2790 | { | |
2791 | unsigned int xchg = i.operands - 1; | |
2792 | union i386_op temp_op; | |
2793 | i386_operand_type temp_type; | |
2794 | ||
2795 | temp_type = i.types[xchg]; | |
2796 | i.types[xchg] = i.types[0]; | |
2797 | i.types[0] = temp_type; | |
2798 | temp_op = i.op[xchg]; | |
2799 | i.op[xchg] = i.op[0]; | |
2800 | i.op[0] = temp_op; | |
2801 | ||
9c2799c2 | 2802 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
2803 | |
2804 | i.rex = REX_R; | |
2805 | xchg = i.rm.regmem; | |
2806 | i.rm.regmem = i.rm.reg; | |
2807 | i.rm.reg = xchg; | |
2808 | ||
2809 | /* Use the next insn. */ | |
2810 | i.tm = t[1]; | |
2811 | } | |
2812 | ||
539f890d L |
2813 | if (i.tm.opcode_modifier.vex == VEXScalar) |
2814 | vector_length = avxscalar; | |
2815 | else | |
2816 | vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; | |
c0f3af97 L |
2817 | |
2818 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
2819 | { | |
2820 | case 0: | |
2821 | implied_prefix = 0; | |
2822 | break; | |
2823 | case DATA_PREFIX_OPCODE: | |
2824 | implied_prefix = 1; | |
2825 | break; | |
2826 | case REPE_PREFIX_OPCODE: | |
2827 | implied_prefix = 2; | |
2828 | break; | |
2829 | case REPNE_PREFIX_OPCODE: | |
2830 | implied_prefix = 3; | |
2831 | break; | |
2832 | default: | |
2833 | abort (); | |
2834 | } | |
2835 | ||
2836 | /* Use 2-byte VEX prefix if possible. */ | |
7f399153 | 2837 | if (i.tm.opcode_modifier.vexopcode == VEX0F |
04251de0 | 2838 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
2839 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
2840 | { | |
2841 | /* 2-byte VEX prefix. */ | |
2842 | unsigned int r; | |
2843 | ||
2844 | i.vex.length = 2; | |
2845 | i.vex.bytes[0] = 0xc5; | |
2846 | ||
2847 | /* Check the REX.R bit. */ | |
2848 | r = (i.rex & REX_R) ? 0 : 1; | |
2849 | i.vex.bytes[1] = (r << 7 | |
2850 | | register_specifier << 3 | |
2851 | | vector_length << 2 | |
2852 | | implied_prefix); | |
2853 | } | |
2854 | else | |
2855 | { | |
2856 | /* 3-byte VEX prefix. */ | |
2857 | unsigned int m, w; | |
2858 | ||
f88c9eb0 | 2859 | i.vex.length = 3; |
f88c9eb0 | 2860 | |
7f399153 | 2861 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 2862 | { |
7f399153 L |
2863 | case VEX0F: |
2864 | m = 0x1; | |
80de6e00 | 2865 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
2866 | break; |
2867 | case VEX0F38: | |
2868 | m = 0x2; | |
80de6e00 | 2869 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
2870 | break; |
2871 | case VEX0F3A: | |
2872 | m = 0x3; | |
80de6e00 | 2873 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
2874 | break; |
2875 | case XOP08: | |
5dd85c99 SP |
2876 | m = 0x8; |
2877 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
2878 | break; |
2879 | case XOP09: | |
f88c9eb0 SP |
2880 | m = 0x9; |
2881 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
2882 | break; |
2883 | case XOP0A: | |
f88c9eb0 SP |
2884 | m = 0xa; |
2885 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
2886 | break; |
2887 | default: | |
2888 | abort (); | |
f88c9eb0 | 2889 | } |
c0f3af97 | 2890 | |
c0f3af97 L |
2891 | /* The high 3 bits of the second VEX byte are 1's compliment |
2892 | of RXB bits from REX. */ | |
2893 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
2894 | ||
2895 | /* Check the REX.W bit. */ | |
2896 | w = (i.rex & REX_W) ? 1 : 0; | |
1ef99a7b | 2897 | if (i.tm.opcode_modifier.vexw) |
c0f3af97 L |
2898 | { |
2899 | if (w) | |
2900 | abort (); | |
2901 | ||
1ef99a7b | 2902 | if (i.tm.opcode_modifier.vexw == VEXW1) |
c0f3af97 L |
2903 | w = 1; |
2904 | } | |
2905 | ||
2906 | i.vex.bytes[2] = (w << 7 | |
2907 | | register_specifier << 3 | |
2908 | | vector_length << 2 | |
2909 | | implied_prefix); | |
2910 | } | |
2911 | } | |
2912 | ||
65da13b5 L |
2913 | static void |
2914 | process_immext (void) | |
2915 | { | |
2916 | expressionS *exp; | |
2917 | ||
2918 | if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0) | |
2919 | { | |
1fed0ba1 L |
2920 | /* SSE3 Instructions have the fixed operands with an opcode |
2921 | suffix which is coded in the same place as an 8-bit immediate | |
2922 | field would be. Here we check those operands and remove them | |
2923 | afterwards. */ | |
65da13b5 L |
2924 | unsigned int x; |
2925 | ||
2926 | for (x = 0; x < i.operands; x++) | |
2927 | if (i.op[x].regs->reg_num != x) | |
2928 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
1fed0ba1 L |
2929 | register_prefix, i.op[x].regs->reg_name, x + 1, |
2930 | i.tm.name); | |
2931 | ||
2932 | i.operands = 0; | |
65da13b5 L |
2933 | } |
2934 | ||
c0f3af97 | 2935 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
2936 | which is coded in the same place as an 8-bit immediate field |
2937 | would be. Here we fake an 8-bit immediate operand from the | |
2938 | opcode suffix stored in tm.extension_opcode. | |
2939 | ||
c1e679ec | 2940 | AVX instructions also use this encoding, for some of |
c0f3af97 | 2941 | 3 argument instructions. */ |
65da13b5 | 2942 | |
9c2799c2 | 2943 | gas_assert (i.imm_operands == 0 |
7ab9ffdd L |
2944 | && (i.operands <= 2 |
2945 | || (i.tm.opcode_modifier.vex | |
2946 | && i.operands <= 4))); | |
65da13b5 L |
2947 | |
2948 | exp = &im_expressions[i.imm_operands++]; | |
2949 | i.op[i.operands].imms = exp; | |
2950 | i.types[i.operands] = imm8; | |
2951 | i.operands++; | |
2952 | exp->X_op = O_constant; | |
2953 | exp->X_add_number = i.tm.extension_opcode; | |
2954 | i.tm.extension_opcode = None; | |
2955 | } | |
2956 | ||
252b5132 RH |
2957 | /* This is the guts of the machine-dependent assembler. LINE points to a |
2958 | machine dependent instruction. This function is supposed to emit | |
2959 | the frags/bytes it assembles to. */ | |
2960 | ||
2961 | void | |
65da13b5 | 2962 | md_assemble (char *line) |
252b5132 | 2963 | { |
40fb9820 | 2964 | unsigned int j; |
252b5132 | 2965 | char mnemonic[MAX_MNEM_SIZE]; |
d3ce72d0 | 2966 | const insn_template *t; |
252b5132 | 2967 | |
47926f60 | 2968 | /* Initialize globals. */ |
252b5132 RH |
2969 | memset (&i, '\0', sizeof (i)); |
2970 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 2971 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
2972 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
2973 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 2974 | save_stack_p = save_stack; |
252b5132 RH |
2975 | |
2976 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
2977 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 2978 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 2979 | |
29b0f896 AM |
2980 | line = parse_insn (line, mnemonic); |
2981 | if (line == NULL) | |
2982 | return; | |
252b5132 | 2983 | |
29b0f896 | 2984 | line = parse_operands (line, mnemonic); |
ee86248c | 2985 | this_operand = -1; |
29b0f896 AM |
2986 | if (line == NULL) |
2987 | return; | |
252b5132 | 2988 | |
29b0f896 AM |
2989 | /* Now we've parsed the mnemonic into a set of templates, and have the |
2990 | operands at hand. */ | |
2991 | ||
2992 | /* All intel opcodes have reversed operands except for "bound" and | |
2993 | "enter". We also don't reverse intersegment "jmp" and "call" | |
2994 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 2995 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
2996 | if (intel_syntax |
2997 | && i.operands > 1 | |
29b0f896 | 2998 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 2999 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
3000 | && !(operand_type_check (i.types[0], imm) |
3001 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
3002 | swap_operands (); |
3003 | ||
ec56d5c0 JB |
3004 | /* The order of the immediates should be reversed |
3005 | for 2 immediates extrq and insertq instructions */ | |
3006 | if (i.imm_operands == 2 | |
3007 | && (strcmp (mnemonic, "extrq") == 0 | |
3008 | || strcmp (mnemonic, "insertq") == 0)) | |
3009 | swap_2_operands (0, 1); | |
3010 | ||
29b0f896 AM |
3011 | if (i.imm_operands) |
3012 | optimize_imm (); | |
3013 | ||
b300c311 L |
3014 | /* Don't optimize displacement for movabs since it only takes 64bit |
3015 | displacement. */ | |
3016 | if (i.disp_operands | |
862be3fb L |
3017 | && !i.disp32_encoding |
3018 | && (flag_code != CODE_64BIT | |
3019 | || strcmp (mnemonic, "movabs") != 0)) | |
3020 | optimize_disp (); | |
29b0f896 AM |
3021 | |
3022 | /* Next, we find a template that matches the given insn, | |
3023 | making sure the overlap of the given operands types is consistent | |
3024 | with the template operand types. */ | |
252b5132 | 3025 | |
fa99fab2 | 3026 | if (!(t = match_template ())) |
29b0f896 | 3027 | return; |
252b5132 | 3028 | |
daf50ae7 | 3029 | if (sse_check != sse_check_none |
81f8a913 | 3030 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
3031 | && (i.tm.cpu_flags.bitfield.cpusse |
3032 | || i.tm.cpu_flags.bitfield.cpusse2 | |
3033 | || i.tm.cpu_flags.bitfield.cpusse3 | |
3034 | || i.tm.cpu_flags.bitfield.cpussse3 | |
3035 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
3036 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
3037 | { | |
3038 | (sse_check == sse_check_warning | |
3039 | ? as_warn | |
3040 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
3041 | } | |
3042 | ||
321fd21e L |
3043 | /* Zap movzx and movsx suffix. The suffix has been set from |
3044 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
3045 | or extracted from mnemonic in AT&T syntax. But we'll use | |
3046 | the destination register to choose the suffix for encoding. */ | |
3047 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 3048 | { |
321fd21e L |
3049 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
3050 | there is no suffix, the default will be byte extension. */ | |
3051 | if (i.reg_operands != 2 | |
3052 | && !i.suffix | |
7ab9ffdd | 3053 | && intel_syntax) |
321fd21e L |
3054 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
3055 | ||
3056 | i.suffix = 0; | |
cd61ebfe | 3057 | } |
24eab124 | 3058 | |
40fb9820 | 3059 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
3060 | if (!add_prefix (FWAIT_OPCODE)) |
3061 | return; | |
252b5132 | 3062 | |
c1ba0266 L |
3063 | /* Check for lock without a lockable instruction. Destination operand |
3064 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
3065 | if (i.prefix[LOCK_PREFIX] |
3066 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
3067 | || i.mem_operands == 0 |
3068 | || (i.tm.base_opcode != 0x86 | |
3069 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
3070 | { |
3071 | as_bad (_("expecting lockable instruction after `lock'")); | |
3072 | return; | |
3073 | } | |
3074 | ||
29b0f896 | 3075 | /* Check string instruction segment overrides. */ |
40fb9820 | 3076 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
3077 | { |
3078 | if (!check_string ()) | |
5dd0794d | 3079 | return; |
fc0763e6 | 3080 | i.disp_operands = 0; |
29b0f896 | 3081 | } |
5dd0794d | 3082 | |
29b0f896 AM |
3083 | if (!process_suffix ()) |
3084 | return; | |
e413e4e9 | 3085 | |
bc0844ae L |
3086 | /* Update operand types. */ |
3087 | for (j = 0; j < i.operands; j++) | |
3088 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3089 | ||
29b0f896 AM |
3090 | /* Make still unresolved immediate matches conform to size of immediate |
3091 | given in i.suffix. */ | |
3092 | if (!finalize_imm ()) | |
3093 | return; | |
252b5132 | 3094 | |
40fb9820 | 3095 | if (i.types[0].bitfield.imm1) |
29b0f896 | 3096 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 3097 | |
9afe6eb8 L |
3098 | /* We only need to check those implicit registers for instructions |
3099 | with 3 operands or less. */ | |
3100 | if (i.operands <= 3) | |
3101 | for (j = 0; j < i.operands; j++) | |
3102 | if (i.types[j].bitfield.inoutportreg | |
3103 | || i.types[j].bitfield.shiftcount | |
3104 | || i.types[j].bitfield.acc | |
3105 | || i.types[j].bitfield.floatacc) | |
3106 | i.reg_operands--; | |
40fb9820 | 3107 | |
c0f3af97 L |
3108 | /* ImmExt should be processed after SSE2AVX. */ |
3109 | if (!i.tm.opcode_modifier.sse2avx | |
3110 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 3111 | process_immext (); |
252b5132 | 3112 | |
29b0f896 AM |
3113 | /* For insns with operands there are more diddles to do to the opcode. */ |
3114 | if (i.operands) | |
3115 | { | |
3116 | if (!process_operands ()) | |
3117 | return; | |
3118 | } | |
40fb9820 | 3119 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
3120 | { |
3121 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
3122 | as_warn (_("translating to `%sp'"), i.tm.name); | |
3123 | } | |
252b5132 | 3124 | |
c0f3af97 | 3125 | if (i.tm.opcode_modifier.vex) |
fa99fab2 | 3126 | build_vex_prefix (t); |
c0f3af97 | 3127 | |
5dd85c99 SP |
3128 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
3129 | instructions may define INT_OPCODE as well, so avoid this corner | |
3130 | case for those instructions that use MODRM. */ | |
3131 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
3132 | && !i.tm.opcode_modifier.modrm |
3133 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
3134 | { |
3135 | i.tm.base_opcode = INT3_OPCODE; | |
3136 | i.imm_operands = 0; | |
3137 | } | |
252b5132 | 3138 | |
40fb9820 L |
3139 | if ((i.tm.opcode_modifier.jump |
3140 | || i.tm.opcode_modifier.jumpbyte | |
3141 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
3142 | && i.op[0].disps->X_op == O_constant) |
3143 | { | |
3144 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
3145 | the absolute address given by the constant. Since ix86 jumps and | |
3146 | calls are pc relative, we need to generate a reloc. */ | |
3147 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
3148 | i.op[0].disps->X_op = O_symbol; | |
3149 | } | |
252b5132 | 3150 | |
40fb9820 | 3151 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 3152 | i.rex |= REX_W; |
252b5132 | 3153 | |
29b0f896 AM |
3154 | /* For 8 bit registers we need an empty rex prefix. Also if the |
3155 | instruction already has a prefix, we need to convert old | |
3156 | registers to new ones. */ | |
773f551c | 3157 | |
40fb9820 | 3158 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 3159 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 3160 | || (i.types[1].bitfield.reg8 |
29b0f896 | 3161 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
3162 | || ((i.types[0].bitfield.reg8 |
3163 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
3164 | && i.rex != 0)) |
3165 | { | |
3166 | int x; | |
726c5dcd | 3167 | |
29b0f896 AM |
3168 | i.rex |= REX_OPCODE; |
3169 | for (x = 0; x < 2; x++) | |
3170 | { | |
3171 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 3172 | if (i.types[x].bitfield.reg8 |
29b0f896 | 3173 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 3174 | { |
29b0f896 AM |
3175 | /* In case it is "hi" register, give up. */ |
3176 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 3177 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 3178 | "instruction requiring REX prefix."), |
a540244d | 3179 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 3180 | |
29b0f896 AM |
3181 | /* Otherwise it is equivalent to the extended register. |
3182 | Since the encoding doesn't change this is merely | |
3183 | cosmetic cleanup for debug output. */ | |
3184 | ||
3185 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 3186 | } |
29b0f896 AM |
3187 | } |
3188 | } | |
773f551c | 3189 | |
7ab9ffdd | 3190 | if (i.rex != 0) |
29b0f896 AM |
3191 | add_prefix (REX_OPCODE | i.rex); |
3192 | ||
3193 | /* We are ready to output the insn. */ | |
3194 | output_insn (); | |
3195 | } | |
3196 | ||
3197 | static char * | |
e3bb37b5 | 3198 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
3199 | { |
3200 | char *l = line; | |
3201 | char *token_start = l; | |
3202 | char *mnem_p; | |
5c6af06e | 3203 | int supported; |
d3ce72d0 | 3204 | const insn_template *t; |
b6169b20 | 3205 | char *dot_p = NULL; |
29b0f896 AM |
3206 | |
3207 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
3208 | const char *expecting_string_instruction = NULL; | |
45288df1 | 3209 | |
29b0f896 AM |
3210 | while (1) |
3211 | { | |
3212 | mnem_p = mnemonic; | |
3213 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
3214 | { | |
b6169b20 L |
3215 | if (*mnem_p == '.') |
3216 | dot_p = mnem_p; | |
29b0f896 AM |
3217 | mnem_p++; |
3218 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 3219 | { |
29b0f896 AM |
3220 | as_bad (_("no such instruction: `%s'"), token_start); |
3221 | return NULL; | |
3222 | } | |
3223 | l++; | |
3224 | } | |
3225 | if (!is_space_char (*l) | |
3226 | && *l != END_OF_INSN | |
e44823cf JB |
3227 | && (intel_syntax |
3228 | || (*l != PREFIX_SEPARATOR | |
3229 | && *l != ','))) | |
29b0f896 AM |
3230 | { |
3231 | as_bad (_("invalid character %s in mnemonic"), | |
3232 | output_invalid (*l)); | |
3233 | return NULL; | |
3234 | } | |
3235 | if (token_start == l) | |
3236 | { | |
e44823cf | 3237 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
3238 | as_bad (_("expecting prefix; got nothing")); |
3239 | else | |
3240 | as_bad (_("expecting mnemonic; got nothing")); | |
3241 | return NULL; | |
3242 | } | |
45288df1 | 3243 | |
29b0f896 | 3244 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 3245 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 3246 | |
29b0f896 AM |
3247 | if (*l != END_OF_INSN |
3248 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
3249 | && current_templates | |
40fb9820 | 3250 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 3251 | { |
c6fb90c8 | 3252 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
3253 | { |
3254 | as_bad ((flag_code != CODE_64BIT | |
3255 | ? _("`%s' is only supported in 64-bit mode") | |
3256 | : _("`%s' is not supported in 64-bit mode")), | |
3257 | current_templates->start->name); | |
3258 | return NULL; | |
3259 | } | |
29b0f896 AM |
3260 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
3261 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
3262 | if ((current_templates->start->opcode_modifier.size16 |
3263 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 3264 | && flag_code != CODE_64BIT |
40fb9820 | 3265 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
3266 | ^ (flag_code == CODE_16BIT))) |
3267 | { | |
3268 | as_bad (_("redundant %s prefix"), | |
3269 | current_templates->start->name); | |
3270 | return NULL; | |
45288df1 | 3271 | } |
29b0f896 AM |
3272 | /* Add prefix, checking for repeated prefixes. */ |
3273 | switch (add_prefix (current_templates->start->base_opcode)) | |
3274 | { | |
c32fa91d | 3275 | case PREFIX_EXIST: |
29b0f896 | 3276 | return NULL; |
c32fa91d | 3277 | case PREFIX_REP: |
29b0f896 AM |
3278 | expecting_string_instruction = current_templates->start->name; |
3279 | break; | |
c32fa91d L |
3280 | default: |
3281 | break; | |
29b0f896 AM |
3282 | } |
3283 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
3284 | token_start = ++l; | |
3285 | } | |
3286 | else | |
3287 | break; | |
3288 | } | |
45288df1 | 3289 | |
30a55f88 | 3290 | if (!current_templates) |
b6169b20 | 3291 | { |
f8a5c266 L |
3292 | /* Check if we should swap operand or force 32bit displacement in |
3293 | encoding. */ | |
30a55f88 L |
3294 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
3295 | i.swap_operand = 1; | |
f8a5c266 L |
3296 | else if (mnem_p - 4 == dot_p |
3297 | && dot_p[1] == 'd' | |
3298 | && dot_p[2] == '3' | |
3299 | && dot_p[3] == '2') | |
3300 | i.disp32_encoding = 1; | |
30a55f88 L |
3301 | else |
3302 | goto check_suffix; | |
3303 | mnem_p = dot_p; | |
3304 | *dot_p = '\0'; | |
d3ce72d0 | 3305 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
3306 | } |
3307 | ||
29b0f896 AM |
3308 | if (!current_templates) |
3309 | { | |
b6169b20 | 3310 | check_suffix: |
29b0f896 AM |
3311 | /* See if we can get a match by trimming off a suffix. */ |
3312 | switch (mnem_p[-1]) | |
3313 | { | |
3314 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
3315 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
3316 | i.suffix = SHORT_MNEM_SUFFIX; | |
3317 | else | |
29b0f896 AM |
3318 | case BYTE_MNEM_SUFFIX: |
3319 | case QWORD_MNEM_SUFFIX: | |
3320 | i.suffix = mnem_p[-1]; | |
3321 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3322 | current_templates = (const templates *) hash_find (op_hash, |
3323 | mnemonic); | |
29b0f896 AM |
3324 | break; |
3325 | case SHORT_MNEM_SUFFIX: | |
3326 | case LONG_MNEM_SUFFIX: | |
3327 | if (!intel_syntax) | |
3328 | { | |
3329 | i.suffix = mnem_p[-1]; | |
3330 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3331 | current_templates = (const templates *) hash_find (op_hash, |
3332 | mnemonic); | |
29b0f896 AM |
3333 | } |
3334 | break; | |
252b5132 | 3335 | |
29b0f896 AM |
3336 | /* Intel Syntax. */ |
3337 | case 'd': | |
3338 | if (intel_syntax) | |
3339 | { | |
9306ca4a | 3340 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
3341 | i.suffix = SHORT_MNEM_SUFFIX; |
3342 | else | |
3343 | i.suffix = LONG_MNEM_SUFFIX; | |
3344 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3345 | current_templates = (const templates *) hash_find (op_hash, |
3346 | mnemonic); | |
29b0f896 AM |
3347 | } |
3348 | break; | |
3349 | } | |
3350 | if (!current_templates) | |
3351 | { | |
3352 | as_bad (_("no such instruction: `%s'"), token_start); | |
3353 | return NULL; | |
3354 | } | |
3355 | } | |
252b5132 | 3356 | |
40fb9820 L |
3357 | if (current_templates->start->opcode_modifier.jump |
3358 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
3359 | { |
3360 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
3361 | predict taken and predict not taken respectively. | |
3362 | I'm not sure that branch hints actually do anything on loop | |
3363 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
3364 | may work in the future and it doesn't hurt to accept them | |
3365 | now. */ | |
3366 | if (l[0] == ',' && l[1] == 'p') | |
3367 | { | |
3368 | if (l[2] == 't') | |
3369 | { | |
3370 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
3371 | return NULL; | |
3372 | l += 3; | |
3373 | } | |
3374 | else if (l[2] == 'n') | |
3375 | { | |
3376 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
3377 | return NULL; | |
3378 | l += 3; | |
3379 | } | |
3380 | } | |
3381 | } | |
3382 | /* Any other comma loses. */ | |
3383 | if (*l == ',') | |
3384 | { | |
3385 | as_bad (_("invalid character %s in mnemonic"), | |
3386 | output_invalid (*l)); | |
3387 | return NULL; | |
3388 | } | |
252b5132 | 3389 | |
29b0f896 | 3390 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
3391 | supported = 0; |
3392 | for (t = current_templates->start; t < current_templates->end; ++t) | |
3393 | { | |
c0f3af97 L |
3394 | supported |= cpu_flags_match (t); |
3395 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 3396 | goto skip; |
5c6af06e | 3397 | } |
3629bb00 | 3398 | |
c0f3af97 | 3399 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
3400 | { |
3401 | as_bad (flag_code == CODE_64BIT | |
3402 | ? _("`%s' is not supported in 64-bit mode") | |
3403 | : _("`%s' is only supported in 64-bit mode"), | |
3404 | current_templates->start->name); | |
3405 | return NULL; | |
3406 | } | |
c0f3af97 | 3407 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 3408 | { |
3629bb00 | 3409 | as_bad (_("`%s' is not supported on `%s%s'"), |
7ab9ffdd | 3410 | current_templates->start->name, |
41aacd83 | 3411 | cpu_arch_name ? cpu_arch_name : default_arch, |
3629bb00 L |
3412 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
3413 | return NULL; | |
29b0f896 | 3414 | } |
3629bb00 L |
3415 | |
3416 | skip: | |
3417 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 3418 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
3419 | { |
3420 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3421 | } | |
252b5132 | 3422 | |
29b0f896 | 3423 | /* Check for rep/repne without a string instruction. */ |
f41bbced | 3424 | if (expecting_string_instruction) |
29b0f896 | 3425 | { |
f41bbced JB |
3426 | static templates override; |
3427 | ||
3428 | for (t = current_templates->start; t < current_templates->end; ++t) | |
40fb9820 | 3429 | if (t->opcode_modifier.isstring) |
f41bbced JB |
3430 | break; |
3431 | if (t >= current_templates->end) | |
3432 | { | |
3433 | as_bad (_("expecting string instruction after `%s'"), | |
64e74474 | 3434 | expecting_string_instruction); |
f41bbced JB |
3435 | return NULL; |
3436 | } | |
3437 | for (override.start = t; t < current_templates->end; ++t) | |
40fb9820 | 3438 | if (!t->opcode_modifier.isstring) |
f41bbced JB |
3439 | break; |
3440 | override.end = t; | |
3441 | current_templates = &override; | |
29b0f896 | 3442 | } |
252b5132 | 3443 | |
29b0f896 AM |
3444 | return l; |
3445 | } | |
252b5132 | 3446 | |
29b0f896 | 3447 | static char * |
e3bb37b5 | 3448 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
3449 | { |
3450 | char *token_start; | |
3138f287 | 3451 | |
29b0f896 AM |
3452 | /* 1 if operand is pending after ','. */ |
3453 | unsigned int expecting_operand = 0; | |
252b5132 | 3454 | |
29b0f896 AM |
3455 | /* Non-zero if operand parens not balanced. */ |
3456 | unsigned int paren_not_balanced; | |
3457 | ||
3458 | while (*l != END_OF_INSN) | |
3459 | { | |
3460 | /* Skip optional white space before operand. */ | |
3461 | if (is_space_char (*l)) | |
3462 | ++l; | |
3463 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
3464 | { | |
3465 | as_bad (_("invalid character %s before operand %d"), | |
3466 | output_invalid (*l), | |
3467 | i.operands + 1); | |
3468 | return NULL; | |
3469 | } | |
3470 | token_start = l; /* after white space */ | |
3471 | paren_not_balanced = 0; | |
3472 | while (paren_not_balanced || *l != ',') | |
3473 | { | |
3474 | if (*l == END_OF_INSN) | |
3475 | { | |
3476 | if (paren_not_balanced) | |
3477 | { | |
3478 | if (!intel_syntax) | |
3479 | as_bad (_("unbalanced parenthesis in operand %d."), | |
3480 | i.operands + 1); | |
3481 | else | |
3482 | as_bad (_("unbalanced brackets in operand %d."), | |
3483 | i.operands + 1); | |
3484 | return NULL; | |
3485 | } | |
3486 | else | |
3487 | break; /* we are done */ | |
3488 | } | |
3489 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
3490 | { | |
3491 | as_bad (_("invalid character %s in operand %d"), | |
3492 | output_invalid (*l), | |
3493 | i.operands + 1); | |
3494 | return NULL; | |
3495 | } | |
3496 | if (!intel_syntax) | |
3497 | { | |
3498 | if (*l == '(') | |
3499 | ++paren_not_balanced; | |
3500 | if (*l == ')') | |
3501 | --paren_not_balanced; | |
3502 | } | |
3503 | else | |
3504 | { | |
3505 | if (*l == '[') | |
3506 | ++paren_not_balanced; | |
3507 | if (*l == ']') | |
3508 | --paren_not_balanced; | |
3509 | } | |
3510 | l++; | |
3511 | } | |
3512 | if (l != token_start) | |
3513 | { /* Yes, we've read in another operand. */ | |
3514 | unsigned int operand_ok; | |
3515 | this_operand = i.operands++; | |
7d5e4556 | 3516 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
3517 | if (i.operands > MAX_OPERANDS) |
3518 | { | |
3519 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
3520 | MAX_OPERANDS); | |
3521 | return NULL; | |
3522 | } | |
3523 | /* Now parse operand adding info to 'i' as we go along. */ | |
3524 | END_STRING_AND_SAVE (l); | |
3525 | ||
3526 | if (intel_syntax) | |
3527 | operand_ok = | |
3528 | i386_intel_operand (token_start, | |
3529 | intel_float_operand (mnemonic)); | |
3530 | else | |
a7619375 | 3531 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
3532 | |
3533 | RESTORE_END_STRING (l); | |
3534 | if (!operand_ok) | |
3535 | return NULL; | |
3536 | } | |
3537 | else | |
3538 | { | |
3539 | if (expecting_operand) | |
3540 | { | |
3541 | expecting_operand_after_comma: | |
3542 | as_bad (_("expecting operand after ','; got nothing")); | |
3543 | return NULL; | |
3544 | } | |
3545 | if (*l == ',') | |
3546 | { | |
3547 | as_bad (_("expecting operand before ','; got nothing")); | |
3548 | return NULL; | |
3549 | } | |
3550 | } | |
7f3f1ea2 | 3551 | |
29b0f896 AM |
3552 | /* Now *l must be either ',' or END_OF_INSN. */ |
3553 | if (*l == ',') | |
3554 | { | |
3555 | if (*++l == END_OF_INSN) | |
3556 | { | |
3557 | /* Just skip it, if it's \n complain. */ | |
3558 | goto expecting_operand_after_comma; | |
3559 | } | |
3560 | expecting_operand = 1; | |
3561 | } | |
3562 | } | |
3563 | return l; | |
3564 | } | |
7f3f1ea2 | 3565 | |
050dfa73 | 3566 | static void |
4d456e3d | 3567 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
3568 | { |
3569 | union i386_op temp_op; | |
40fb9820 | 3570 | i386_operand_type temp_type; |
050dfa73 | 3571 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 3572 | |
050dfa73 MM |
3573 | temp_type = i.types[xchg2]; |
3574 | i.types[xchg2] = i.types[xchg1]; | |
3575 | i.types[xchg1] = temp_type; | |
3576 | temp_op = i.op[xchg2]; | |
3577 | i.op[xchg2] = i.op[xchg1]; | |
3578 | i.op[xchg1] = temp_op; | |
3579 | temp_reloc = i.reloc[xchg2]; | |
3580 | i.reloc[xchg2] = i.reloc[xchg1]; | |
3581 | i.reloc[xchg1] = temp_reloc; | |
3582 | } | |
3583 | ||
29b0f896 | 3584 | static void |
e3bb37b5 | 3585 | swap_operands (void) |
29b0f896 | 3586 | { |
b7c61d9a | 3587 | switch (i.operands) |
050dfa73 | 3588 | { |
c0f3af97 | 3589 | case 5: |
b7c61d9a | 3590 | case 4: |
4d456e3d | 3591 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
3592 | case 3: |
3593 | case 2: | |
4d456e3d | 3594 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
3595 | break; |
3596 | default: | |
3597 | abort (); | |
29b0f896 | 3598 | } |
29b0f896 AM |
3599 | |
3600 | if (i.mem_operands == 2) | |
3601 | { | |
3602 | const seg_entry *temp_seg; | |
3603 | temp_seg = i.seg[0]; | |
3604 | i.seg[0] = i.seg[1]; | |
3605 | i.seg[1] = temp_seg; | |
3606 | } | |
3607 | } | |
252b5132 | 3608 | |
29b0f896 AM |
3609 | /* Try to ensure constant immediates are represented in the smallest |
3610 | opcode possible. */ | |
3611 | static void | |
e3bb37b5 | 3612 | optimize_imm (void) |
29b0f896 AM |
3613 | { |
3614 | char guess_suffix = 0; | |
3615 | int op; | |
252b5132 | 3616 | |
29b0f896 AM |
3617 | if (i.suffix) |
3618 | guess_suffix = i.suffix; | |
3619 | else if (i.reg_operands) | |
3620 | { | |
3621 | /* Figure out a suffix from the last register operand specified. | |
3622 | We can't do this properly yet, ie. excluding InOutPortReg, | |
3623 | but the following works for instructions with immediates. | |
3624 | In any case, we can't set i.suffix yet. */ | |
3625 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3626 | if (i.types[op].bitfield.reg8) |
7ab9ffdd | 3627 | { |
40fb9820 L |
3628 | guess_suffix = BYTE_MNEM_SUFFIX; |
3629 | break; | |
3630 | } | |
3631 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 3632 | { |
40fb9820 L |
3633 | guess_suffix = WORD_MNEM_SUFFIX; |
3634 | break; | |
3635 | } | |
3636 | else if (i.types[op].bitfield.reg32) | |
3637 | { | |
3638 | guess_suffix = LONG_MNEM_SUFFIX; | |
3639 | break; | |
3640 | } | |
3641 | else if (i.types[op].bitfield.reg64) | |
3642 | { | |
3643 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 3644 | break; |
252b5132 | 3645 | } |
29b0f896 AM |
3646 | } |
3647 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
3648 | guess_suffix = WORD_MNEM_SUFFIX; | |
3649 | ||
3650 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3651 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
3652 | { |
3653 | switch (i.op[op].imms->X_op) | |
252b5132 | 3654 | { |
29b0f896 AM |
3655 | case O_constant: |
3656 | /* If a suffix is given, this operand may be shortened. */ | |
3657 | switch (guess_suffix) | |
252b5132 | 3658 | { |
29b0f896 | 3659 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
3660 | i.types[op].bitfield.imm32 = 1; |
3661 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3662 | break; |
3663 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
3664 | i.types[op].bitfield.imm16 = 1; |
3665 | i.types[op].bitfield.imm32 = 1; | |
3666 | i.types[op].bitfield.imm32s = 1; | |
3667 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3668 | break; |
3669 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
3670 | i.types[op].bitfield.imm8 = 1; |
3671 | i.types[op].bitfield.imm8s = 1; | |
3672 | i.types[op].bitfield.imm16 = 1; | |
3673 | i.types[op].bitfield.imm32 = 1; | |
3674 | i.types[op].bitfield.imm32s = 1; | |
3675 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 3676 | break; |
252b5132 | 3677 | } |
252b5132 | 3678 | |
29b0f896 AM |
3679 | /* If this operand is at most 16 bits, convert it |
3680 | to a signed 16 bit number before trying to see | |
3681 | whether it will fit in an even smaller size. | |
3682 | This allows a 16-bit operand such as $0xffe0 to | |
3683 | be recognised as within Imm8S range. */ | |
40fb9820 | 3684 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 3685 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 3686 | { |
29b0f896 AM |
3687 | i.op[op].imms->X_add_number = |
3688 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
3689 | } | |
40fb9820 | 3690 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
3691 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
3692 | == 0)) | |
3693 | { | |
3694 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
3695 | ^ ((offsetT) 1 << 31)) | |
3696 | - ((offsetT) 1 << 31)); | |
3697 | } | |
40fb9820 | 3698 | i.types[op] |
c6fb90c8 L |
3699 | = operand_type_or (i.types[op], |
3700 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 3701 | |
29b0f896 AM |
3702 | /* We must avoid matching of Imm32 templates when 64bit |
3703 | only immediate is available. */ | |
3704 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 3705 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 3706 | break; |
252b5132 | 3707 | |
29b0f896 AM |
3708 | case O_absent: |
3709 | case O_register: | |
3710 | abort (); | |
3711 | ||
3712 | /* Symbols and expressions. */ | |
3713 | default: | |
9cd96992 JB |
3714 | /* Convert symbolic operand to proper sizes for matching, but don't |
3715 | prevent matching a set of insns that only supports sizes other | |
3716 | than those matching the insn suffix. */ | |
3717 | { | |
40fb9820 | 3718 | i386_operand_type mask, allowed; |
d3ce72d0 | 3719 | const insn_template *t; |
9cd96992 | 3720 | |
0dfbf9d7 L |
3721 | operand_type_set (&mask, 0); |
3722 | operand_type_set (&allowed, 0); | |
40fb9820 | 3723 | |
4eed87de AM |
3724 | for (t = current_templates->start; |
3725 | t < current_templates->end; | |
3726 | ++t) | |
c6fb90c8 L |
3727 | allowed = operand_type_or (allowed, |
3728 | t->operand_types[op]); | |
9cd96992 JB |
3729 | switch (guess_suffix) |
3730 | { | |
3731 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
3732 | mask.bitfield.imm64 = 1; |
3733 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
3734 | break; |
3735 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 3736 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
3737 | break; |
3738 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 3739 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
3740 | break; |
3741 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 3742 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
3743 | break; |
3744 | default: | |
9cd96992 JB |
3745 | break; |
3746 | } | |
c6fb90c8 | 3747 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 3748 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 3749 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 3750 | } |
29b0f896 | 3751 | break; |
252b5132 | 3752 | } |
29b0f896 AM |
3753 | } |
3754 | } | |
47926f60 | 3755 | |
29b0f896 AM |
3756 | /* Try to use the smallest displacement type too. */ |
3757 | static void | |
e3bb37b5 | 3758 | optimize_disp (void) |
29b0f896 AM |
3759 | { |
3760 | int op; | |
3e73aa7c | 3761 | |
29b0f896 | 3762 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3763 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 3764 | { |
b300c311 | 3765 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 3766 | { |
91d6fa6a | 3767 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 3768 | |
40fb9820 | 3769 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 3770 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
3771 | { |
3772 | /* If this operand is at most 16 bits, convert | |
3773 | to a signed 16 bit number and don't use 64bit | |
3774 | displacement. */ | |
91d6fa6a | 3775 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 3776 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3777 | } |
40fb9820 | 3778 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 3779 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
3780 | { |
3781 | /* If this operand is at most 32 bits, convert | |
3782 | to a signed 32 bit number and don't use 64bit | |
3783 | displacement. */ | |
91d6fa6a NC |
3784 | op_disp &= (((offsetT) 2 << 31) - 1); |
3785 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 3786 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3787 | } |
91d6fa6a | 3788 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 3789 | { |
40fb9820 L |
3790 | i.types[op].bitfield.disp8 = 0; |
3791 | i.types[op].bitfield.disp16 = 0; | |
3792 | i.types[op].bitfield.disp32 = 0; | |
3793 | i.types[op].bitfield.disp32s = 0; | |
3794 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
3795 | i.op[op].disps = 0; |
3796 | i.disp_operands--; | |
3797 | } | |
3798 | else if (flag_code == CODE_64BIT) | |
3799 | { | |
91d6fa6a | 3800 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 3801 | { |
40fb9820 L |
3802 | i.types[op].bitfield.disp64 = 0; |
3803 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 3804 | } |
0e1147d9 | 3805 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 3806 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 3807 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 3808 | } |
40fb9820 L |
3809 | if ((i.types[op].bitfield.disp32 |
3810 | || i.types[op].bitfield.disp32s | |
3811 | || i.types[op].bitfield.disp16) | |
91d6fa6a | 3812 | && fits_in_signed_byte (op_disp)) |
40fb9820 | 3813 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 3814 | } |
67a4f2b7 AO |
3815 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
3816 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
3817 | { | |
3818 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
3819 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
3820 | i.types[op].bitfield.disp8 = 0; |
3821 | i.types[op].bitfield.disp16 = 0; | |
3822 | i.types[op].bitfield.disp32 = 0; | |
3823 | i.types[op].bitfield.disp32s = 0; | |
3824 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
3825 | } |
3826 | else | |
b300c311 | 3827 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 3828 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 3829 | } |
29b0f896 AM |
3830 | } |
3831 | ||
43f3e2ee | 3832 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
3833 | operand types. */ |
3834 | ||
3835 | static int | |
3836 | VEX_check_operands (const insn_template *t) | |
3837 | { | |
3838 | if (!t->opcode_modifier.vex) | |
3839 | return 0; | |
3840 | ||
3841 | /* Only check VEX_Imm4, which must be the first operand. */ | |
3842 | if (t->operand_types[0].bitfield.vec_imm4) | |
3843 | { | |
3844 | if (i.op[0].imms->X_op != O_constant | |
3845 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 3846 | { |
a65babc9 | 3847 | i.error = bad_imm4; |
891edac4 L |
3848 | return 1; |
3849 | } | |
a683cc34 SP |
3850 | |
3851 | /* Turn off Imm8 so that update_imm won't complain. */ | |
3852 | i.types[0] = vec_imm4; | |
3853 | } | |
3854 | ||
3855 | return 0; | |
3856 | } | |
3857 | ||
d3ce72d0 | 3858 | static const insn_template * |
e3bb37b5 | 3859 | match_template (void) |
29b0f896 AM |
3860 | { |
3861 | /* Points to template once we've found it. */ | |
d3ce72d0 | 3862 | const insn_template *t; |
40fb9820 | 3863 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 3864 | i386_operand_type overlap4; |
29b0f896 | 3865 | unsigned int found_reverse_match; |
40fb9820 L |
3866 | i386_opcode_modifier suffix_check; |
3867 | i386_operand_type operand_types [MAX_OPERANDS]; | |
539e75ad | 3868 | int addr_prefix_disp; |
a5c311ca | 3869 | unsigned int j; |
3629bb00 | 3870 | unsigned int found_cpu_match; |
45664ddb | 3871 | unsigned int check_register; |
29b0f896 | 3872 | |
c0f3af97 L |
3873 | #if MAX_OPERANDS != 5 |
3874 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
3875 | #endif |
3876 | ||
29b0f896 | 3877 | found_reverse_match = 0; |
539e75ad | 3878 | addr_prefix_disp = -1; |
40fb9820 L |
3879 | |
3880 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
3881 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
3882 | suffix_check.no_bsuf = 1; | |
3883 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3884 | suffix_check.no_wsuf = 1; | |
3885 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
3886 | suffix_check.no_ssuf = 1; | |
3887 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
3888 | suffix_check.no_lsuf = 1; | |
3889 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3890 | suffix_check.no_qsuf = 1; | |
3891 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 3892 | suffix_check.no_ldsuf = 1; |
29b0f896 | 3893 | |
01559ecc L |
3894 | /* Must have right number of operands. */ |
3895 | i.error = number_of_operands_mismatch; | |
3896 | ||
45aa61fe | 3897 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 3898 | { |
539e75ad L |
3899 | addr_prefix_disp = -1; |
3900 | ||
29b0f896 AM |
3901 | if (i.operands != t->operands) |
3902 | continue; | |
3903 | ||
50aecf8c | 3904 | /* Check processor support. */ |
a65babc9 | 3905 | i.error = unsupported; |
c0f3af97 L |
3906 | found_cpu_match = (cpu_flags_match (t) |
3907 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
3908 | if (!found_cpu_match) |
3909 | continue; | |
3910 | ||
e1d4d893 | 3911 | /* Check old gcc support. */ |
a65babc9 | 3912 | i.error = old_gcc_only; |
e1d4d893 L |
3913 | if (!old_gcc && t->opcode_modifier.oldgcc) |
3914 | continue; | |
3915 | ||
3916 | /* Check AT&T mnemonic. */ | |
a65babc9 | 3917 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 3918 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
3919 | continue; |
3920 | ||
891edac4 | 3921 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 3922 | i.error = unsupported_syntax; |
5c07affc L |
3923 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
3924 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) | |
1efbbeb4 L |
3925 | continue; |
3926 | ||
20592a94 | 3927 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 3928 | i.error = invalid_instruction_suffix; |
567e4e96 L |
3929 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
3930 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
3931 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
3932 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
3933 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
3934 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
3935 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 AM |
3936 | continue; |
3937 | ||
5c07affc | 3938 | if (!operand_size_match (t)) |
7d5e4556 | 3939 | continue; |
539e75ad | 3940 | |
5c07affc L |
3941 | for (j = 0; j < MAX_OPERANDS; j++) |
3942 | operand_types[j] = t->operand_types[j]; | |
3943 | ||
45aa61fe AM |
3944 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
3945 | if (i.suffix == QWORD_MNEM_SUFFIX | |
3946 | && flag_code != CODE_64BIT | |
3947 | && (intel_syntax | |
40fb9820 | 3948 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
3949 | && !intel_float_operand (t->name)) |
3950 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 3951 | && ((!operand_types[0].bitfield.regmmx |
c0f3af97 L |
3952 | && !operand_types[0].bitfield.regxmm |
3953 | && !operand_types[0].bitfield.regymm) | |
40fb9820 | 3954 | || (!operand_types[t->operands > 1].bitfield.regmmx |
c0f3af97 L |
3955 | && !!operand_types[t->operands > 1].bitfield.regxmm |
3956 | && !!operand_types[t->operands > 1].bitfield.regymm)) | |
45aa61fe AM |
3957 | && (t->base_opcode != 0x0fc7 |
3958 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
3959 | continue; | |
3960 | ||
192dc9c6 JB |
3961 | /* In general, don't allow 32-bit operands on pre-386. */ |
3962 | else if (i.suffix == LONG_MNEM_SUFFIX | |
3963 | && !cpu_arch_flags.bitfield.cpui386 | |
3964 | && (intel_syntax | |
3965 | ? (!t->opcode_modifier.ignoresize | |
3966 | && !intel_float_operand (t->name)) | |
3967 | : intel_float_operand (t->name) != 2) | |
3968 | && ((!operand_types[0].bitfield.regmmx | |
3969 | && !operand_types[0].bitfield.regxmm) | |
3970 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
3971 | && !!operand_types[t->operands > 1].bitfield.regxmm))) | |
3972 | continue; | |
3973 | ||
29b0f896 | 3974 | /* Do not verify operands when there are none. */ |
50aecf8c | 3975 | else |
29b0f896 | 3976 | { |
c6fb90c8 | 3977 | if (!t->operands) |
2dbab7d5 L |
3978 | /* We've found a match; break out of loop. */ |
3979 | break; | |
29b0f896 | 3980 | } |
252b5132 | 3981 | |
539e75ad L |
3982 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
3983 | into Disp32/Disp16/Disp32 operand. */ | |
3984 | if (i.prefix[ADDR_PREFIX] != 0) | |
3985 | { | |
40fb9820 | 3986 | /* There should be only one Disp operand. */ |
539e75ad L |
3987 | switch (flag_code) |
3988 | { | |
3989 | case CODE_16BIT: | |
40fb9820 L |
3990 | for (j = 0; j < MAX_OPERANDS; j++) |
3991 | { | |
3992 | if (operand_types[j].bitfield.disp16) | |
3993 | { | |
3994 | addr_prefix_disp = j; | |
3995 | operand_types[j].bitfield.disp32 = 1; | |
3996 | operand_types[j].bitfield.disp16 = 0; | |
3997 | break; | |
3998 | } | |
3999 | } | |
539e75ad L |
4000 | break; |
4001 | case CODE_32BIT: | |
40fb9820 L |
4002 | for (j = 0; j < MAX_OPERANDS; j++) |
4003 | { | |
4004 | if (operand_types[j].bitfield.disp32) | |
4005 | { | |
4006 | addr_prefix_disp = j; | |
4007 | operand_types[j].bitfield.disp32 = 0; | |
4008 | operand_types[j].bitfield.disp16 = 1; | |
4009 | break; | |
4010 | } | |
4011 | } | |
539e75ad L |
4012 | break; |
4013 | case CODE_64BIT: | |
40fb9820 L |
4014 | for (j = 0; j < MAX_OPERANDS; j++) |
4015 | { | |
4016 | if (operand_types[j].bitfield.disp64) | |
4017 | { | |
4018 | addr_prefix_disp = j; | |
4019 | operand_types[j].bitfield.disp64 = 0; | |
4020 | operand_types[j].bitfield.disp32 = 1; | |
4021 | break; | |
4022 | } | |
4023 | } | |
539e75ad L |
4024 | break; |
4025 | } | |
539e75ad L |
4026 | } |
4027 | ||
56ffb741 L |
4028 | /* We check register size if needed. */ |
4029 | check_register = t->opcode_modifier.checkregsize; | |
c6fb90c8 | 4030 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
4031 | switch (t->operands) |
4032 | { | |
4033 | case 1: | |
40fb9820 | 4034 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
4035 | continue; |
4036 | break; | |
4037 | case 2: | |
8b38ad71 L |
4038 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
4039 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
4040 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
4041 | zero-extend %eax to %rax. */ | |
4042 | if (flag_code == CODE_64BIT | |
4043 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
4044 | && operand_type_equal (&i.types [0], &acc32) |
4045 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 4046 | continue; |
b6169b20 L |
4047 | if (i.swap_operand) |
4048 | { | |
4049 | /* If we swap operand in encoding, we either match | |
4050 | the next one or reverse direction of operands. */ | |
4051 | if (t->opcode_modifier.s) | |
4052 | continue; | |
4053 | else if (t->opcode_modifier.d) | |
4054 | goto check_reverse; | |
4055 | } | |
4056 | ||
29b0f896 | 4057 | case 3: |
fa99fab2 L |
4058 | /* If we swap operand in encoding, we match the next one. */ |
4059 | if (i.swap_operand && t->opcode_modifier.s) | |
4060 | continue; | |
f48ff2ae | 4061 | case 4: |
c0f3af97 | 4062 | case 5: |
c6fb90c8 | 4063 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
4064 | if (!operand_type_match (overlap0, i.types[0]) |
4065 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
4066 | || (check_register |
4067 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
4068 | operand_types[0], |
4069 | overlap1, i.types[1], | |
4070 | operand_types[1]))) | |
29b0f896 AM |
4071 | { |
4072 | /* Check if other direction is valid ... */ | |
40fb9820 | 4073 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
4074 | continue; |
4075 | ||
b6169b20 | 4076 | check_reverse: |
29b0f896 | 4077 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
4078 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
4079 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
4080 | if (!operand_type_match (overlap0, i.types[0]) |
4081 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
4082 | || (check_register |
4083 | && !operand_type_register_match (overlap0, | |
4084 | i.types[0], | |
4085 | operand_types[1], | |
4086 | overlap1, | |
4087 | i.types[1], | |
4088 | operand_types[0]))) | |
29b0f896 AM |
4089 | { |
4090 | /* Does not match either direction. */ | |
4091 | continue; | |
4092 | } | |
4093 | /* found_reverse_match holds which of D or FloatDR | |
4094 | we've found. */ | |
40fb9820 | 4095 | if (t->opcode_modifier.d) |
8a2ed489 | 4096 | found_reverse_match = Opcode_D; |
40fb9820 | 4097 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
4098 | found_reverse_match = Opcode_FloatD; |
4099 | else | |
4100 | found_reverse_match = 0; | |
40fb9820 | 4101 | if (t->opcode_modifier.floatr) |
8a2ed489 | 4102 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 4103 | } |
f48ff2ae | 4104 | else |
29b0f896 | 4105 | { |
f48ff2ae | 4106 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
4107 | switch (t->operands) |
4108 | { | |
c0f3af97 L |
4109 | case 5: |
4110 | overlap4 = operand_type_and (i.types[4], | |
4111 | operand_types[4]); | |
d1cbb4db | 4112 | case 4: |
c6fb90c8 L |
4113 | overlap3 = operand_type_and (i.types[3], |
4114 | operand_types[3]); | |
d1cbb4db | 4115 | case 3: |
c6fb90c8 L |
4116 | overlap2 = operand_type_and (i.types[2], |
4117 | operand_types[2]); | |
d1cbb4db L |
4118 | break; |
4119 | } | |
29b0f896 | 4120 | |
f48ff2ae L |
4121 | switch (t->operands) |
4122 | { | |
c0f3af97 L |
4123 | case 5: |
4124 | if (!operand_type_match (overlap4, i.types[4]) | |
4125 | || !operand_type_register_match (overlap3, | |
4126 | i.types[3], | |
4127 | operand_types[3], | |
4128 | overlap4, | |
4129 | i.types[4], | |
4130 | operand_types[4])) | |
4131 | continue; | |
f48ff2ae | 4132 | case 4: |
40fb9820 | 4133 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
4134 | || (check_register |
4135 | && !operand_type_register_match (overlap2, | |
4136 | i.types[2], | |
4137 | operand_types[2], | |
4138 | overlap3, | |
4139 | i.types[3], | |
4140 | operand_types[3]))) | |
f48ff2ae L |
4141 | continue; |
4142 | case 3: | |
4143 | /* Here we make use of the fact that there are no | |
4144 | reverse match 3 operand instructions, and all 3 | |
4145 | operand instructions only need to be checked for | |
4146 | register consistency between operands 2 and 3. */ | |
40fb9820 | 4147 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
4148 | || (check_register |
4149 | && !operand_type_register_match (overlap1, | |
4150 | i.types[1], | |
4151 | operand_types[1], | |
4152 | overlap2, | |
4153 | i.types[2], | |
4154 | operand_types[2]))) | |
f48ff2ae L |
4155 | continue; |
4156 | break; | |
4157 | } | |
29b0f896 | 4158 | } |
f48ff2ae | 4159 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
4160 | slip through to break. */ |
4161 | } | |
3629bb00 | 4162 | if (!found_cpu_match) |
29b0f896 AM |
4163 | { |
4164 | found_reverse_match = 0; | |
4165 | continue; | |
4166 | } | |
c0f3af97 | 4167 | |
a683cc34 SP |
4168 | /* Check if VEX operands are valid. */ |
4169 | if (VEX_check_operands (t)) | |
4170 | continue; | |
4171 | ||
29b0f896 AM |
4172 | /* We've found a match; break out of loop. */ |
4173 | break; | |
4174 | } | |
4175 | ||
4176 | if (t == current_templates->end) | |
4177 | { | |
4178 | /* We found no match. */ | |
a65babc9 L |
4179 | const char *err_msg; |
4180 | switch (i.error) | |
4181 | { | |
4182 | default: | |
4183 | abort (); | |
86e026a4 | 4184 | case operand_size_mismatch: |
a65babc9 L |
4185 | err_msg = _("operand size mismatch"); |
4186 | break; | |
4187 | case operand_type_mismatch: | |
4188 | err_msg = _("operand type mismatch"); | |
4189 | break; | |
4190 | case register_type_mismatch: | |
4191 | err_msg = _("register type mismatch"); | |
4192 | break; | |
4193 | case number_of_operands_mismatch: | |
4194 | err_msg = _("number of operands mismatch"); | |
4195 | break; | |
4196 | case invalid_instruction_suffix: | |
4197 | err_msg = _("invalid instruction suffix"); | |
4198 | break; | |
4199 | case bad_imm4: | |
4200 | err_msg = _("Imm4 isn't the first operand"); | |
4201 | break; | |
4202 | case old_gcc_only: | |
4203 | err_msg = _("only supported with old gcc"); | |
4204 | break; | |
4205 | case unsupported_with_intel_mnemonic: | |
4206 | err_msg = _("unsupported with Intel mnemonic"); | |
4207 | break; | |
4208 | case unsupported_syntax: | |
4209 | err_msg = _("unsupported syntax"); | |
4210 | break; | |
4211 | case unsupported: | |
4212 | err_msg = _("unsupported"); | |
4213 | break; | |
4214 | } | |
4215 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 4216 | current_templates->start->name); |
fa99fab2 | 4217 | return NULL; |
29b0f896 | 4218 | } |
252b5132 | 4219 | |
29b0f896 AM |
4220 | if (!quiet_warnings) |
4221 | { | |
4222 | if (!intel_syntax | |
40fb9820 L |
4223 | && (i.types[0].bitfield.jumpabsolute |
4224 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
4225 | { |
4226 | as_warn (_("indirect %s without `*'"), t->name); | |
4227 | } | |
4228 | ||
40fb9820 L |
4229 | if (t->opcode_modifier.isprefix |
4230 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
4231 | { |
4232 | /* Warn them that a data or address size prefix doesn't | |
4233 | affect assembly of the next line of code. */ | |
4234 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
4235 | } | |
4236 | } | |
4237 | ||
4238 | /* Copy the template we found. */ | |
4239 | i.tm = *t; | |
539e75ad L |
4240 | |
4241 | if (addr_prefix_disp != -1) | |
4242 | i.tm.operand_types[addr_prefix_disp] | |
4243 | = operand_types[addr_prefix_disp]; | |
4244 | ||
29b0f896 AM |
4245 | if (found_reverse_match) |
4246 | { | |
4247 | /* If we found a reverse match we must alter the opcode | |
4248 | direction bit. found_reverse_match holds bits to change | |
4249 | (different for int & float insns). */ | |
4250 | ||
4251 | i.tm.base_opcode ^= found_reverse_match; | |
4252 | ||
539e75ad L |
4253 | i.tm.operand_types[0] = operand_types[1]; |
4254 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
4255 | } |
4256 | ||
fa99fab2 | 4257 | return t; |
29b0f896 AM |
4258 | } |
4259 | ||
4260 | static int | |
e3bb37b5 | 4261 | check_string (void) |
29b0f896 | 4262 | { |
40fb9820 L |
4263 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
4264 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
4265 | { |
4266 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
4267 | { | |
a87af027 | 4268 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 4269 | i.tm.name, |
a87af027 JB |
4270 | mem_op + 1, |
4271 | register_prefix); | |
29b0f896 AM |
4272 | return 0; |
4273 | } | |
4274 | /* There's only ever one segment override allowed per instruction. | |
4275 | This instruction possibly has a legal segment override on the | |
4276 | second operand, so copy the segment to where non-string | |
4277 | instructions store it, allowing common code. */ | |
4278 | i.seg[0] = i.seg[1]; | |
4279 | } | |
40fb9820 | 4280 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
4281 | { |
4282 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
4283 | { | |
a87af027 | 4284 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 4285 | i.tm.name, |
a87af027 JB |
4286 | mem_op + 2, |
4287 | register_prefix); | |
29b0f896 AM |
4288 | return 0; |
4289 | } | |
4290 | } | |
4291 | return 1; | |
4292 | } | |
4293 | ||
4294 | static int | |
543613e9 | 4295 | process_suffix (void) |
29b0f896 AM |
4296 | { |
4297 | /* If matched instruction specifies an explicit instruction mnemonic | |
4298 | suffix, use it. */ | |
40fb9820 L |
4299 | if (i.tm.opcode_modifier.size16) |
4300 | i.suffix = WORD_MNEM_SUFFIX; | |
4301 | else if (i.tm.opcode_modifier.size32) | |
4302 | i.suffix = LONG_MNEM_SUFFIX; | |
4303 | else if (i.tm.opcode_modifier.size64) | |
4304 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
4305 | else if (i.reg_operands) |
4306 | { | |
4307 | /* If there's no instruction mnemonic suffix we try to invent one | |
4308 | based on register operands. */ | |
4309 | if (!i.suffix) | |
4310 | { | |
4311 | /* We take i.suffix from the last register operand specified, | |
4312 | Destination register type is more significant than source | |
381d071f L |
4313 | register type. crc32 in SSE4.2 prefers source register |
4314 | type. */ | |
4315 | if (i.tm.base_opcode == 0xf20f38f1) | |
4316 | { | |
40fb9820 L |
4317 | if (i.types[0].bitfield.reg16) |
4318 | i.suffix = WORD_MNEM_SUFFIX; | |
4319 | else if (i.types[0].bitfield.reg32) | |
4320 | i.suffix = LONG_MNEM_SUFFIX; | |
4321 | else if (i.types[0].bitfield.reg64) | |
4322 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 4323 | } |
9344ff29 | 4324 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 4325 | { |
40fb9820 | 4326 | if (i.types[0].bitfield.reg8) |
20592a94 L |
4327 | i.suffix = BYTE_MNEM_SUFFIX; |
4328 | } | |
381d071f L |
4329 | |
4330 | if (!i.suffix) | |
4331 | { | |
4332 | int op; | |
4333 | ||
20592a94 L |
4334 | if (i.tm.base_opcode == 0xf20f38f1 |
4335 | || i.tm.base_opcode == 0xf20f38f0) | |
4336 | { | |
4337 | /* We have to know the operand size for crc32. */ | |
4338 | as_bad (_("ambiguous memory operand size for `%s`"), | |
4339 | i.tm.name); | |
4340 | return 0; | |
4341 | } | |
4342 | ||
381d071f | 4343 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4344 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 4345 | { |
40fb9820 L |
4346 | if (i.types[op].bitfield.reg8) |
4347 | { | |
4348 | i.suffix = BYTE_MNEM_SUFFIX; | |
4349 | break; | |
4350 | } | |
4351 | else if (i.types[op].bitfield.reg16) | |
4352 | { | |
4353 | i.suffix = WORD_MNEM_SUFFIX; | |
4354 | break; | |
4355 | } | |
4356 | else if (i.types[op].bitfield.reg32) | |
4357 | { | |
4358 | i.suffix = LONG_MNEM_SUFFIX; | |
4359 | break; | |
4360 | } | |
4361 | else if (i.types[op].bitfield.reg64) | |
4362 | { | |
4363 | i.suffix = QWORD_MNEM_SUFFIX; | |
4364 | break; | |
4365 | } | |
381d071f L |
4366 | } |
4367 | } | |
29b0f896 AM |
4368 | } |
4369 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
4370 | { | |
2eb952a4 L |
4371 | if (intel_syntax |
4372 | && i.tm.opcode_modifier.ignoresize | |
4373 | && i.tm.opcode_modifier.no_bsuf) | |
4374 | i.suffix = 0; | |
4375 | else if (!check_byte_reg ()) | |
29b0f896 AM |
4376 | return 0; |
4377 | } | |
4378 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4379 | { | |
2eb952a4 L |
4380 | if (intel_syntax |
4381 | && i.tm.opcode_modifier.ignoresize | |
4382 | && i.tm.opcode_modifier.no_lsuf) | |
4383 | i.suffix = 0; | |
4384 | else if (!check_long_reg ()) | |
29b0f896 AM |
4385 | return 0; |
4386 | } | |
4387 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4388 | { | |
955e1e6a L |
4389 | if (intel_syntax |
4390 | && i.tm.opcode_modifier.ignoresize | |
4391 | && i.tm.opcode_modifier.no_qsuf) | |
4392 | i.suffix = 0; | |
4393 | else if (!check_qword_reg ()) | |
29b0f896 AM |
4394 | return 0; |
4395 | } | |
4396 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4397 | { | |
2eb952a4 L |
4398 | if (intel_syntax |
4399 | && i.tm.opcode_modifier.ignoresize | |
4400 | && i.tm.opcode_modifier.no_wsuf) | |
4401 | i.suffix = 0; | |
4402 | else if (!check_word_reg ()) | |
29b0f896 AM |
4403 | return 0; |
4404 | } | |
c0f3af97 L |
4405 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
4406 | || i.suffix == YMMWORD_MNEM_SUFFIX) | |
582d5edd | 4407 | { |
c0f3af97 | 4408 | /* Skip if the instruction has x/y suffix. match_template |
582d5edd L |
4409 | should check if it is a valid suffix. */ |
4410 | } | |
40fb9820 | 4411 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
4412 | /* Do nothing if the instruction is going to ignore the prefix. */ |
4413 | ; | |
4414 | else | |
4415 | abort (); | |
4416 | } | |
40fb9820 | 4417 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
4418 | && !i.suffix |
4419 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 4420 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
4421 | { |
4422 | i.suffix = stackop_size; | |
4423 | } | |
9306ca4a JB |
4424 | else if (intel_syntax |
4425 | && !i.suffix | |
40fb9820 L |
4426 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
4427 | || i.tm.opcode_modifier.jumpbyte | |
4428 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
4429 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
4430 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
4431 | { |
4432 | switch (flag_code) | |
4433 | { | |
4434 | case CODE_64BIT: | |
40fb9820 | 4435 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
4436 | { |
4437 | i.suffix = QWORD_MNEM_SUFFIX; | |
4438 | break; | |
4439 | } | |
4440 | case CODE_32BIT: | |
40fb9820 | 4441 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
4442 | i.suffix = LONG_MNEM_SUFFIX; |
4443 | break; | |
4444 | case CODE_16BIT: | |
40fb9820 | 4445 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
4446 | i.suffix = WORD_MNEM_SUFFIX; |
4447 | break; | |
4448 | } | |
4449 | } | |
252b5132 | 4450 | |
9306ca4a | 4451 | if (!i.suffix) |
29b0f896 | 4452 | { |
9306ca4a JB |
4453 | if (!intel_syntax) |
4454 | { | |
40fb9820 | 4455 | if (i.tm.opcode_modifier.w) |
9306ca4a | 4456 | { |
4eed87de AM |
4457 | as_bad (_("no instruction mnemonic suffix given and " |
4458 | "no register operands; can't size instruction")); | |
9306ca4a JB |
4459 | return 0; |
4460 | } | |
4461 | } | |
4462 | else | |
4463 | { | |
40fb9820 | 4464 | unsigned int suffixes; |
7ab9ffdd | 4465 | |
40fb9820 L |
4466 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
4467 | if (!i.tm.opcode_modifier.no_wsuf) | |
4468 | suffixes |= 1 << 1; | |
4469 | if (!i.tm.opcode_modifier.no_lsuf) | |
4470 | suffixes |= 1 << 2; | |
fc4adea1 | 4471 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
4472 | suffixes |= 1 << 3; |
4473 | if (!i.tm.opcode_modifier.no_ssuf) | |
4474 | suffixes |= 1 << 4; | |
4475 | if (!i.tm.opcode_modifier.no_qsuf) | |
4476 | suffixes |= 1 << 5; | |
4477 | ||
4478 | /* There are more than suffix matches. */ | |
4479 | if (i.tm.opcode_modifier.w | |
9306ca4a | 4480 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
4481 | && !i.tm.opcode_modifier.defaultsize |
4482 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
4483 | { |
4484 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
4485 | return 0; | |
4486 | } | |
4487 | } | |
29b0f896 | 4488 | } |
252b5132 | 4489 | |
9306ca4a JB |
4490 | /* Change the opcode based on the operand size given by i.suffix; |
4491 | We don't need to change things for byte insns. */ | |
4492 | ||
582d5edd L |
4493 | if (i.suffix |
4494 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 L |
4495 | && i.suffix != XMMWORD_MNEM_SUFFIX |
4496 | && i.suffix != YMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
4497 | { |
4498 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 4499 | if (i.tm.opcode_modifier.w) |
29b0f896 | 4500 | { |
40fb9820 | 4501 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
4502 | i.tm.base_opcode |= 8; |
4503 | else | |
4504 | i.tm.base_opcode |= 1; | |
4505 | } | |
0f3f3d8b | 4506 | |
29b0f896 AM |
4507 | /* Now select between word & dword operations via the operand |
4508 | size prefix, except for instructions that will ignore this | |
4509 | prefix anyway. */ | |
ca61edf2 | 4510 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 4511 | { |
ca61edf2 L |
4512 | /* The address size override prefix changes the size of the |
4513 | first operand. */ | |
40fb9820 L |
4514 | if ((flag_code == CODE_32BIT |
4515 | && i.op->regs[0].reg_type.bitfield.reg16) | |
4516 | || (flag_code != CODE_32BIT | |
4517 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
4518 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
4519 | return 0; | |
4520 | } | |
4521 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
4522 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
4523 | && !i.tm.opcode_modifier.ignoresize |
4524 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
4525 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
4526 | || (flag_code == CODE_64BIT | |
40fb9820 | 4527 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
4528 | { |
4529 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 4530 | |
40fb9820 | 4531 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 4532 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 4533 | |
29b0f896 AM |
4534 | if (!add_prefix (prefix)) |
4535 | return 0; | |
24eab124 | 4536 | } |
252b5132 | 4537 | |
29b0f896 AM |
4538 | /* Set mode64 for an operand. */ |
4539 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 4540 | && flag_code == CODE_64BIT |
40fb9820 | 4541 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
4542 | { |
4543 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
4544 | need rex64. cmpxchg8b is also a special case. */ |
4545 | if (! (i.operands == 2 | |
4546 | && i.tm.base_opcode == 0x90 | |
4547 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
4548 | && operand_type_equal (&i.types [0], &acc64) |
4549 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
4550 | && ! (i.operands == 1 |
4551 | && i.tm.base_opcode == 0xfc7 | |
4552 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
4553 | && !operand_type_check (i.types [0], reg) |
4554 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 4555 | i.rex |= REX_W; |
46e883c5 | 4556 | } |
3e73aa7c | 4557 | |
29b0f896 AM |
4558 | /* Size floating point instruction. */ |
4559 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 4560 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 4561 | i.tm.base_opcode ^= 4; |
29b0f896 | 4562 | } |
7ecd2f8b | 4563 | |
29b0f896 AM |
4564 | return 1; |
4565 | } | |
3e73aa7c | 4566 | |
29b0f896 | 4567 | static int |
543613e9 | 4568 | check_byte_reg (void) |
29b0f896 AM |
4569 | { |
4570 | int op; | |
543613e9 | 4571 | |
29b0f896 AM |
4572 | for (op = i.operands; --op >= 0;) |
4573 | { | |
4574 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
4575 | 32 bit version of an eight bit register, we will just use the | |
4576 | low portion, and that's OK too. */ | |
40fb9820 | 4577 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
4578 | continue; |
4579 | ||
9344ff29 L |
4580 | /* crc32 doesn't generate this warning. */ |
4581 | if (i.tm.base_opcode == 0xf20f38f0) | |
4582 | continue; | |
4583 | ||
40fb9820 L |
4584 | if ((i.types[op].bitfield.reg16 |
4585 | || i.types[op].bitfield.reg32 | |
4586 | || i.types[op].bitfield.reg64) | |
4587 | && i.op[op].regs->reg_num < 4) | |
29b0f896 AM |
4588 | { |
4589 | /* Prohibit these changes in the 64bit mode, since the | |
4590 | lowering is more complicated. */ | |
4591 | if (flag_code == CODE_64BIT | |
40fb9820 | 4592 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
29b0f896 | 4593 | { |
2ca3ace5 L |
4594 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4595 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4596 | i.suffix); |
4597 | return 0; | |
4598 | } | |
4599 | #if REGISTER_WARNINGS | |
4600 | if (!quiet_warnings | |
40fb9820 | 4601 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
a540244d L |
4602 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4603 | register_prefix, | |
40fb9820 | 4604 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
4605 | ? REGNAM_AL - REGNAM_AX |
4606 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 4607 | register_prefix, |
29b0f896 AM |
4608 | i.op[op].regs->reg_name, |
4609 | i.suffix); | |
4610 | #endif | |
4611 | continue; | |
4612 | } | |
4613 | /* Any other register is bad. */ | |
40fb9820 L |
4614 | if (i.types[op].bitfield.reg16 |
4615 | || i.types[op].bitfield.reg32 | |
4616 | || i.types[op].bitfield.reg64 | |
4617 | || i.types[op].bitfield.regmmx | |
4618 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 4619 | || i.types[op].bitfield.regymm |
40fb9820 L |
4620 | || i.types[op].bitfield.sreg2 |
4621 | || i.types[op].bitfield.sreg3 | |
4622 | || i.types[op].bitfield.control | |
4623 | || i.types[op].bitfield.debug | |
4624 | || i.types[op].bitfield.test | |
4625 | || i.types[op].bitfield.floatreg | |
4626 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 4627 | { |
a540244d L |
4628 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4629 | register_prefix, | |
29b0f896 AM |
4630 | i.op[op].regs->reg_name, |
4631 | i.tm.name, | |
4632 | i.suffix); | |
4633 | return 0; | |
4634 | } | |
4635 | } | |
4636 | return 1; | |
4637 | } | |
4638 | ||
4639 | static int | |
e3bb37b5 | 4640 | check_long_reg (void) |
29b0f896 AM |
4641 | { |
4642 | int op; | |
4643 | ||
4644 | for (op = i.operands; --op >= 0;) | |
4645 | /* Reject eight bit registers, except where the template requires | |
4646 | them. (eg. movzb) */ | |
40fb9820 L |
4647 | if (i.types[op].bitfield.reg8 |
4648 | && (i.tm.operand_types[op].bitfield.reg16 | |
4649 | || i.tm.operand_types[op].bitfield.reg32 | |
4650 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4651 | { |
a540244d L |
4652 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4653 | register_prefix, | |
29b0f896 AM |
4654 | i.op[op].regs->reg_name, |
4655 | i.tm.name, | |
4656 | i.suffix); | |
4657 | return 0; | |
4658 | } | |
4659 | /* Warn if the e prefix on a general reg is missing. */ | |
4660 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4661 | && i.types[op].bitfield.reg16 |
4662 | && (i.tm.operand_types[op].bitfield.reg32 | |
4663 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4664 | { |
4665 | /* Prohibit these changes in the 64bit mode, since the | |
4666 | lowering is more complicated. */ | |
4667 | if (flag_code == CODE_64BIT) | |
252b5132 | 4668 | { |
2ca3ace5 L |
4669 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4670 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4671 | i.suffix); |
4672 | return 0; | |
252b5132 | 4673 | } |
29b0f896 AM |
4674 | #if REGISTER_WARNINGS |
4675 | else | |
a540244d L |
4676 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4677 | register_prefix, | |
29b0f896 | 4678 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
a540244d | 4679 | register_prefix, |
29b0f896 AM |
4680 | i.op[op].regs->reg_name, |
4681 | i.suffix); | |
4682 | #endif | |
252b5132 | 4683 | } |
29b0f896 | 4684 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
4685 | else if (i.types[op].bitfield.reg64 |
4686 | && (i.tm.operand_types[op].bitfield.reg32 | |
4687 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4688 | { |
34828aad | 4689 | if (intel_syntax |
ca61edf2 | 4690 | && i.tm.opcode_modifier.toqword |
40fb9820 | 4691 | && !i.types[0].bitfield.regxmm) |
34828aad | 4692 | { |
ca61edf2 | 4693 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
4694 | i.suffix = QWORD_MNEM_SUFFIX; |
4695 | } | |
4696 | else | |
4697 | { | |
4698 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
4699 | register_prefix, i.op[op].regs->reg_name, | |
4700 | i.suffix); | |
4701 | return 0; | |
4702 | } | |
29b0f896 AM |
4703 | } |
4704 | return 1; | |
4705 | } | |
252b5132 | 4706 | |
29b0f896 | 4707 | static int |
e3bb37b5 | 4708 | check_qword_reg (void) |
29b0f896 AM |
4709 | { |
4710 | int op; | |
252b5132 | 4711 | |
29b0f896 AM |
4712 | for (op = i.operands; --op >= 0; ) |
4713 | /* Reject eight bit registers, except where the template requires | |
4714 | them. (eg. movzb) */ | |
40fb9820 L |
4715 | if (i.types[op].bitfield.reg8 |
4716 | && (i.tm.operand_types[op].bitfield.reg16 | |
4717 | || i.tm.operand_types[op].bitfield.reg32 | |
4718 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4719 | { |
a540244d L |
4720 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4721 | register_prefix, | |
29b0f896 AM |
4722 | i.op[op].regs->reg_name, |
4723 | i.tm.name, | |
4724 | i.suffix); | |
4725 | return 0; | |
4726 | } | |
4727 | /* Warn if the e prefix on a general reg is missing. */ | |
40fb9820 L |
4728 | else if ((i.types[op].bitfield.reg16 |
4729 | || i.types[op].bitfield.reg32) | |
4730 | && (i.tm.operand_types[op].bitfield.reg32 | |
4731 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4732 | { |
4733 | /* Prohibit these changes in the 64bit mode, since the | |
4734 | lowering is more complicated. */ | |
34828aad | 4735 | if (intel_syntax |
ca61edf2 | 4736 | && i.tm.opcode_modifier.todword |
40fb9820 | 4737 | && !i.types[0].bitfield.regxmm) |
34828aad | 4738 | { |
ca61edf2 | 4739 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
4740 | i.suffix = LONG_MNEM_SUFFIX; |
4741 | } | |
4742 | else | |
4743 | { | |
4744 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
4745 | register_prefix, i.op[op].regs->reg_name, | |
4746 | i.suffix); | |
4747 | return 0; | |
4748 | } | |
252b5132 | 4749 | } |
29b0f896 AM |
4750 | return 1; |
4751 | } | |
252b5132 | 4752 | |
29b0f896 | 4753 | static int |
e3bb37b5 | 4754 | check_word_reg (void) |
29b0f896 AM |
4755 | { |
4756 | int op; | |
4757 | for (op = i.operands; --op >= 0;) | |
4758 | /* Reject eight bit registers, except where the template requires | |
4759 | them. (eg. movzb) */ | |
40fb9820 L |
4760 | if (i.types[op].bitfield.reg8 |
4761 | && (i.tm.operand_types[op].bitfield.reg16 | |
4762 | || i.tm.operand_types[op].bitfield.reg32 | |
4763 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4764 | { |
a540244d L |
4765 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4766 | register_prefix, | |
29b0f896 AM |
4767 | i.op[op].regs->reg_name, |
4768 | i.tm.name, | |
4769 | i.suffix); | |
4770 | return 0; | |
4771 | } | |
4772 | /* Warn if the e prefix on a general reg is present. */ | |
4773 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4774 | && i.types[op].bitfield.reg32 |
4775 | && (i.tm.operand_types[op].bitfield.reg16 | |
4776 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4777 | { |
29b0f896 AM |
4778 | /* Prohibit these changes in the 64bit mode, since the |
4779 | lowering is more complicated. */ | |
4780 | if (flag_code == CODE_64BIT) | |
252b5132 | 4781 | { |
2ca3ace5 L |
4782 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4783 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4784 | i.suffix); |
4785 | return 0; | |
252b5132 | 4786 | } |
29b0f896 AM |
4787 | else |
4788 | #if REGISTER_WARNINGS | |
a540244d L |
4789 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4790 | register_prefix, | |
29b0f896 | 4791 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
a540244d | 4792 | register_prefix, |
29b0f896 AM |
4793 | i.op[op].regs->reg_name, |
4794 | i.suffix); | |
4795 | #endif | |
4796 | } | |
4797 | return 1; | |
4798 | } | |
252b5132 | 4799 | |
29b0f896 | 4800 | static int |
40fb9820 | 4801 | update_imm (unsigned int j) |
29b0f896 | 4802 | { |
bc0844ae | 4803 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
4804 | if ((overlap.bitfield.imm8 |
4805 | || overlap.bitfield.imm8s | |
4806 | || overlap.bitfield.imm16 | |
4807 | || overlap.bitfield.imm32 | |
4808 | || overlap.bitfield.imm32s | |
4809 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
4810 | && !operand_type_equal (&overlap, &imm8) |
4811 | && !operand_type_equal (&overlap, &imm8s) | |
4812 | && !operand_type_equal (&overlap, &imm16) | |
4813 | && !operand_type_equal (&overlap, &imm32) | |
4814 | && !operand_type_equal (&overlap, &imm32s) | |
4815 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
4816 | { |
4817 | if (i.suffix) | |
4818 | { | |
40fb9820 L |
4819 | i386_operand_type temp; |
4820 | ||
0dfbf9d7 | 4821 | operand_type_set (&temp, 0); |
7ab9ffdd | 4822 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
4823 | { |
4824 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
4825 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
4826 | } | |
4827 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4828 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
4829 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4830 | { | |
4831 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
4832 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
4833 | } | |
4834 | else | |
4835 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
4836 | overlap = temp; | |
29b0f896 | 4837 | } |
0dfbf9d7 L |
4838 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
4839 | || operand_type_equal (&overlap, &imm16_32) | |
4840 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 4841 | { |
40fb9820 | 4842 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 4843 | overlap = imm16; |
40fb9820 | 4844 | else |
65da13b5 | 4845 | overlap = imm32s; |
29b0f896 | 4846 | } |
0dfbf9d7 L |
4847 | if (!operand_type_equal (&overlap, &imm8) |
4848 | && !operand_type_equal (&overlap, &imm8s) | |
4849 | && !operand_type_equal (&overlap, &imm16) | |
4850 | && !operand_type_equal (&overlap, &imm32) | |
4851 | && !operand_type_equal (&overlap, &imm32s) | |
4852 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 4853 | { |
4eed87de AM |
4854 | as_bad (_("no instruction mnemonic suffix given; " |
4855 | "can't determine immediate size")); | |
29b0f896 AM |
4856 | return 0; |
4857 | } | |
4858 | } | |
40fb9820 | 4859 | i.types[j] = overlap; |
29b0f896 | 4860 | |
40fb9820 L |
4861 | return 1; |
4862 | } | |
4863 | ||
4864 | static int | |
4865 | finalize_imm (void) | |
4866 | { | |
bc0844ae | 4867 | unsigned int j, n; |
29b0f896 | 4868 | |
bc0844ae L |
4869 | /* Update the first 2 immediate operands. */ |
4870 | n = i.operands > 2 ? 2 : i.operands; | |
4871 | if (n) | |
4872 | { | |
4873 | for (j = 0; j < n; j++) | |
4874 | if (update_imm (j) == 0) | |
4875 | return 0; | |
40fb9820 | 4876 | |
bc0844ae L |
4877 | /* The 3rd operand can't be immediate operand. */ |
4878 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
4879 | } | |
29b0f896 AM |
4880 | |
4881 | return 1; | |
4882 | } | |
4883 | ||
c0f3af97 L |
4884 | static int |
4885 | bad_implicit_operand (int xmm) | |
4886 | { | |
91d6fa6a NC |
4887 | const char *ireg = xmm ? "xmm0" : "ymm0"; |
4888 | ||
c0f3af97 L |
4889 | if (intel_syntax) |
4890 | as_bad (_("the last operand of `%s' must be `%s%s'"), | |
91d6fa6a | 4891 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
4892 | else |
4893 | as_bad (_("the first operand of `%s' must be `%s%s'"), | |
91d6fa6a | 4894 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
4895 | return 0; |
4896 | } | |
4897 | ||
29b0f896 | 4898 | static int |
e3bb37b5 | 4899 | process_operands (void) |
29b0f896 AM |
4900 | { |
4901 | /* Default segment register this instruction will use for memory | |
4902 | accesses. 0 means unknown. This is only for optimizing out | |
4903 | unnecessary segment overrides. */ | |
4904 | const seg_entry *default_seg = 0; | |
4905 | ||
2426c15f | 4906 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 4907 | { |
91d6fa6a NC |
4908 | unsigned int dupl = i.operands; |
4909 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
4910 | unsigned int j; |
4911 | ||
c0f3af97 | 4912 | /* The destination must be an xmm register. */ |
9c2799c2 | 4913 | gas_assert (i.reg_operands |
91d6fa6a | 4914 | && MAX_OPERANDS > dupl |
7ab9ffdd | 4915 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 L |
4916 | |
4917 | if (i.tm.opcode_modifier.firstxmm0) | |
e2ec9d29 | 4918 | { |
c0f3af97 | 4919 | /* The first operand is implicit and must be xmm0. */ |
9c2799c2 | 4920 | gas_assert (operand_type_equal (&i.types[0], ®xmm)); |
c0f3af97 L |
4921 | if (i.op[0].regs->reg_num != 0) |
4922 | return bad_implicit_operand (1); | |
4923 | ||
8cd7925b | 4924 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
4925 | { |
4926 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
4927 | sources. */ | |
4928 | goto duplicate; | |
4929 | } | |
e2ec9d29 | 4930 | else |
c0f3af97 L |
4931 | { |
4932 | /* We remove the first xmm0 and keep the number of | |
4933 | operands unchanged, which in fact duplicates the | |
4934 | destination. */ | |
4935 | for (j = 1; j < i.operands; j++) | |
4936 | { | |
4937 | i.op[j - 1] = i.op[j]; | |
4938 | i.types[j - 1] = i.types[j]; | |
4939 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
4940 | } | |
4941 | } | |
4942 | } | |
4943 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 4944 | { |
91d6fa6a | 4945 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
4946 | && (i.tm.opcode_modifier.vexsources |
4947 | == VEX3SOURCES)); | |
c0f3af97 L |
4948 | |
4949 | /* Add the implicit xmm0 for instructions with VEX prefix | |
4950 | and 3 sources. */ | |
4951 | for (j = i.operands; j > 0; j--) | |
4952 | { | |
4953 | i.op[j] = i.op[j - 1]; | |
4954 | i.types[j] = i.types[j - 1]; | |
4955 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
4956 | } | |
4957 | i.op[0].regs | |
4958 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 4959 | i.types[0] = regxmm; |
c0f3af97 L |
4960 | i.tm.operand_types[0] = regxmm; |
4961 | ||
4962 | i.operands += 2; | |
4963 | i.reg_operands += 2; | |
4964 | i.tm.operands += 2; | |
4965 | ||
91d6fa6a | 4966 | dupl++; |
c0f3af97 | 4967 | dest++; |
91d6fa6a NC |
4968 | i.op[dupl] = i.op[dest]; |
4969 | i.types[dupl] = i.types[dest]; | |
4970 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 4971 | } |
c0f3af97 L |
4972 | else |
4973 | { | |
4974 | duplicate: | |
4975 | i.operands++; | |
4976 | i.reg_operands++; | |
4977 | i.tm.operands++; | |
4978 | ||
91d6fa6a NC |
4979 | i.op[dupl] = i.op[dest]; |
4980 | i.types[dupl] = i.types[dest]; | |
4981 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
4982 | } |
4983 | ||
4984 | if (i.tm.opcode_modifier.immext) | |
4985 | process_immext (); | |
4986 | } | |
4987 | else if (i.tm.opcode_modifier.firstxmm0) | |
4988 | { | |
4989 | unsigned int j; | |
4990 | ||
4991 | /* The first operand is implicit and must be xmm0/ymm0. */ | |
9c2799c2 | 4992 | gas_assert (i.reg_operands |
7ab9ffdd L |
4993 | && (operand_type_equal (&i.types[0], ®xmm) |
4994 | || operand_type_equal (&i.types[0], ®ymm))); | |
c0f3af97 L |
4995 | if (i.op[0].regs->reg_num != 0) |
4996 | return bad_implicit_operand (i.types[0].bitfield.regxmm); | |
9fcfb3d7 L |
4997 | |
4998 | for (j = 1; j < i.operands; j++) | |
4999 | { | |
5000 | i.op[j - 1] = i.op[j]; | |
5001 | i.types[j - 1] = i.types[j]; | |
5002 | ||
5003 | /* We need to adjust fields in i.tm since they are used by | |
5004 | build_modrm_byte. */ | |
5005 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
5006 | } | |
5007 | ||
e2ec9d29 L |
5008 | i.operands--; |
5009 | i.reg_operands--; | |
e2ec9d29 L |
5010 | i.tm.operands--; |
5011 | } | |
5012 | else if (i.tm.opcode_modifier.regkludge) | |
5013 | { | |
5014 | /* The imul $imm, %reg instruction is converted into | |
5015 | imul $imm, %reg, %reg, and the clr %reg instruction | |
5016 | is converted into xor %reg, %reg. */ | |
5017 | ||
5018 | unsigned int first_reg_op; | |
5019 | ||
5020 | if (operand_type_check (i.types[0], reg)) | |
5021 | first_reg_op = 0; | |
5022 | else | |
5023 | first_reg_op = 1; | |
5024 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 5025 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 5026 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
5027 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
5028 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
5029 | i.operands++; | |
5030 | i.reg_operands++; | |
29b0f896 AM |
5031 | } |
5032 | ||
40fb9820 | 5033 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 5034 | { |
40fb9820 L |
5035 | if (i.types[0].bitfield.sreg2 |
5036 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 5037 | { |
4eed87de AM |
5038 | if (i.tm.base_opcode == POP_SEG_SHORT |
5039 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 5040 | { |
a87af027 | 5041 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 5042 | return 0; |
29b0f896 | 5043 | } |
4eed87de AM |
5044 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
5045 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5046 | i.rex |= REX_B; |
4eed87de AM |
5047 | } |
5048 | else | |
5049 | { | |
7ab9ffdd | 5050 | /* The register or float register operand is in operand |
85f10a01 | 5051 | 0 or 1. */ |
40fb9820 | 5052 | unsigned int op; |
7ab9ffdd L |
5053 | |
5054 | if (i.types[0].bitfield.floatreg | |
5055 | || operand_type_check (i.types[0], reg)) | |
5056 | op = 0; | |
5057 | else | |
5058 | op = 1; | |
4eed87de AM |
5059 | /* Register goes in low 3 bits of opcode. */ |
5060 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
5061 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5062 | i.rex |= REX_B; |
40fb9820 | 5063 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 5064 | { |
4eed87de AM |
5065 | /* Warn about some common errors, but press on regardless. |
5066 | The first case can be generated by gcc (<= 2.8.1). */ | |
5067 | if (i.operands == 2) | |
5068 | { | |
5069 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 5070 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
5071 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
5072 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
5073 | } |
5074 | else | |
5075 | { | |
5076 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
5077 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
5078 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 5079 | } |
29b0f896 AM |
5080 | } |
5081 | } | |
5082 | } | |
40fb9820 | 5083 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
5084 | { |
5085 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
5086 | must be put into the modrm byte). Now, we make the modrm and |
5087 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
5088 | |
5089 | default_seg = build_modrm_byte (); | |
5090 | } | |
8a2ed489 | 5091 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
5092 | { |
5093 | default_seg = &ds; | |
5094 | } | |
40fb9820 | 5095 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
5096 | { |
5097 | /* For the string instructions that allow a segment override | |
5098 | on one of their operands, the default segment is ds. */ | |
5099 | default_seg = &ds; | |
5100 | } | |
5101 | ||
75178d9d L |
5102 | if (i.tm.base_opcode == 0x8d /* lea */ |
5103 | && i.seg[0] | |
5104 | && !quiet_warnings) | |
30123838 | 5105 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
5106 | |
5107 | /* If a segment was explicitly specified, and the specified segment | |
5108 | is not the default, use an opcode prefix to select it. If we | |
5109 | never figured out what the default segment is, then default_seg | |
5110 | will be zero at this point, and the specified segment prefix will | |
5111 | always be used. */ | |
29b0f896 AM |
5112 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
5113 | { | |
5114 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
5115 | return 0; | |
5116 | } | |
5117 | return 1; | |
5118 | } | |
5119 | ||
5120 | static const seg_entry * | |
e3bb37b5 | 5121 | build_modrm_byte (void) |
29b0f896 AM |
5122 | { |
5123 | const seg_entry *default_seg = 0; | |
c0f3af97 | 5124 | unsigned int source, dest; |
8cd7925b | 5125 | int vex_3_sources; |
c0f3af97 L |
5126 | |
5127 | /* The first operand of instructions with VEX prefix and 3 sources | |
5128 | must be VEX_Imm4. */ | |
8cd7925b | 5129 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
5130 | if (vex_3_sources) |
5131 | { | |
91d6fa6a | 5132 | unsigned int nds, reg_slot; |
4c2c6516 | 5133 | expressionS *exp; |
c0f3af97 | 5134 | |
922d8de8 | 5135 | if (i.tm.opcode_modifier.veximmext |
a683cc34 SP |
5136 | && i.tm.opcode_modifier.immext) |
5137 | { | |
5138 | dest = i.operands - 2; | |
5139 | gas_assert (dest == 3); | |
5140 | } | |
922d8de8 | 5141 | else |
a683cc34 | 5142 | dest = i.operands - 1; |
c0f3af97 | 5143 | nds = dest - 1; |
922d8de8 | 5144 | |
a683cc34 SP |
5145 | /* There are 2 kinds of instructions: |
5146 | 1. 5 operands: 4 register operands or 3 register operands | |
5147 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
5148 | VexW0 or VexW1. The destination must be either XMM or YMM | |
5149 | register. | |
5150 | 2. 4 operands: 4 register operands or 3 register operands | |
5151 | plus 1 memory operand, VexXDS, and VexImmExt */ | |
922d8de8 | 5152 | gas_assert ((i.reg_operands == 4 |
a683cc34 SP |
5153 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
5154 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
5155 | && (i.tm.opcode_modifier.veximmext | |
5156 | || (i.imm_operands == 1 | |
5157 | && i.types[0].bitfield.vec_imm4 | |
5158 | && (i.tm.opcode_modifier.vexw == VEXW0 | |
5159 | || i.tm.opcode_modifier.vexw == VEXW1) | |
5160 | && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) | |
5161 | || operand_type_equal (&i.tm.operand_types[dest], ®ymm))))); | |
5162 | ||
5163 | if (i.imm_operands == 0) | |
5164 | { | |
5165 | /* When there is no immediate operand, generate an 8bit | |
5166 | immediate operand to encode the first operand. */ | |
5167 | exp = &im_expressions[i.imm_operands++]; | |
5168 | i.op[i.operands].imms = exp; | |
5169 | i.types[i.operands] = imm8; | |
5170 | i.operands++; | |
5171 | /* If VexW1 is set, the first operand is the source and | |
5172 | the second operand is encoded in the immediate operand. */ | |
5173 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
5174 | { | |
5175 | source = 0; | |
5176 | reg_slot = 1; | |
5177 | } | |
5178 | else | |
5179 | { | |
5180 | source = 1; | |
5181 | reg_slot = 0; | |
5182 | } | |
5183 | ||
5184 | /* FMA swaps REG and NDS. */ | |
5185 | if (i.tm.cpu_flags.bitfield.cpufma) | |
5186 | { | |
5187 | unsigned int tmp; | |
5188 | tmp = reg_slot; | |
5189 | reg_slot = nds; | |
5190 | nds = tmp; | |
5191 | } | |
5192 | ||
24981e7b L |
5193 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
5194 | ®xmm) | |
a683cc34 SP |
5195 | || operand_type_equal (&i.tm.operand_types[reg_slot], |
5196 | ®ymm)); | |
5197 | exp->X_op = O_constant; | |
5198 | exp->X_add_number | |
5199 | = ((i.op[reg_slot].regs->reg_num | |
24981e7b L |
5200 | + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) |
5201 | << 4); | |
a683cc34 | 5202 | } |
922d8de8 | 5203 | else |
a683cc34 SP |
5204 | { |
5205 | unsigned int imm_slot; | |
5206 | ||
5207 | if (i.tm.opcode_modifier.vexw == VEXW0) | |
5208 | { | |
5209 | /* If VexW0 is set, the third operand is the source and | |
5210 | the second operand is encoded in the immediate | |
5211 | operand. */ | |
5212 | source = 2; | |
5213 | reg_slot = 1; | |
5214 | } | |
5215 | else | |
5216 | { | |
5217 | /* VexW1 is set, the second operand is the source and | |
5218 | the third operand is encoded in the immediate | |
5219 | operand. */ | |
5220 | source = 1; | |
5221 | reg_slot = 2; | |
5222 | } | |
5223 | ||
5224 | if (i.tm.opcode_modifier.immext) | |
5225 | { | |
5226 | /* When ImmExt is set, the immdiate byte is the last | |
5227 | operand. */ | |
5228 | imm_slot = i.operands - 1; | |
5229 | source--; | |
5230 | reg_slot--; | |
5231 | } | |
5232 | else | |
5233 | { | |
5234 | imm_slot = 0; | |
5235 | ||
5236 | /* Turn on Imm8 so that output_imm will generate it. */ | |
5237 | i.types[imm_slot].bitfield.imm8 = 1; | |
5238 | } | |
5239 | ||
24981e7b L |
5240 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
5241 | ®xmm) | |
5242 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
5243 | ®ymm)); | |
a683cc34 SP |
5244 | i.op[imm_slot].imms->X_add_number |
5245 | |= ((i.op[reg_slot].regs->reg_num | |
24981e7b L |
5246 | + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) |
5247 | << 4); | |
a683cc34 SP |
5248 | } |
5249 | ||
5250 | gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) | |
5251 | || operand_type_equal (&i.tm.operand_types[nds], | |
5252 | ®ymm)); | |
dae39acc | 5253 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
5254 | } |
5255 | else | |
5256 | source = dest = 0; | |
29b0f896 AM |
5257 | |
5258 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
5259 | implicit registers do not count. If there are 3 register |
5260 | operands, it must be a instruction with VexNDS. For a | |
5261 | instruction with VexNDD, the destination register is encoded | |
5262 | in VEX prefix. If there are 4 register operands, it must be | |
5263 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
5264 | if (i.mem_operands == 0 |
5265 | && ((i.reg_operands == 2 | |
2426c15f | 5266 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 5267 | || (i.reg_operands == 3 |
2426c15f | 5268 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 5269 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 5270 | { |
cab737b9 L |
5271 | switch (i.operands) |
5272 | { | |
5273 | case 2: | |
5274 | source = 0; | |
5275 | break; | |
5276 | case 3: | |
c81128dc L |
5277 | /* When there are 3 operands, one of them may be immediate, |
5278 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
5279 | the first operand must be shift count register (cl) or it |
5280 | is an instruction with VexNDS. */ | |
9c2799c2 | 5281 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 5282 | || (i.imm_operands == 0 |
2426c15f | 5283 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 5284 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
5285 | if (operand_type_check (i.types[0], imm) |
5286 | || i.types[0].bitfield.shiftcount) | |
5287 | source = 1; | |
5288 | else | |
5289 | source = 0; | |
cab737b9 L |
5290 | break; |
5291 | case 4: | |
368d64cc L |
5292 | /* When there are 4 operands, the first two must be 8bit |
5293 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
5294 | one. |
5295 | ||
5296 | For instructions with VexNDS, if the first operand | |
5297 | an imm8, the source operand is the 2nd one. If the last | |
5298 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 5299 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
5300 | && i.types[0].bitfield.imm8 |
5301 | && i.types[1].bitfield.imm8) | |
2426c15f | 5302 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
5303 | && i.imm_operands == 1 |
5304 | && (i.types[0].bitfield.imm8 | |
5305 | || i.types[i.operands - 1].bitfield.imm8))); | |
9f2670f2 L |
5306 | if (i.imm_operands == 2) |
5307 | source = 2; | |
5308 | else | |
c0f3af97 L |
5309 | { |
5310 | if (i.types[0].bitfield.imm8) | |
5311 | source = 1; | |
5312 | else | |
5313 | source = 0; | |
5314 | } | |
c0f3af97 L |
5315 | break; |
5316 | case 5: | |
cab737b9 L |
5317 | break; |
5318 | default: | |
5319 | abort (); | |
5320 | } | |
5321 | ||
c0f3af97 L |
5322 | if (!vex_3_sources) |
5323 | { | |
5324 | dest = source + 1; | |
5325 | ||
2426c15f | 5326 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 L |
5327 | { |
5328 | /* For instructions with VexNDS, the register-only | |
f12dc422 L |
5329 | source operand must be 32/64bit integer, XMM or |
5330 | YMM register. It is encoded in VEX prefix. We | |
5331 | need to clear RegMem bit before calling | |
5332 | operand_type_equal. */ | |
5333 | ||
5334 | i386_operand_type op; | |
5335 | unsigned int vvvv; | |
5336 | ||
5337 | /* Check register-only source operand when two source | |
5338 | operands are swapped. */ | |
5339 | if (!i.tm.operand_types[source].bitfield.baseindex | |
5340 | && i.tm.operand_types[dest].bitfield.baseindex) | |
5341 | { | |
5342 | vvvv = source; | |
5343 | source = dest; | |
5344 | } | |
5345 | else | |
5346 | vvvv = dest; | |
5347 | ||
5348 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 5349 | op.bitfield.regmem = 0; |
c0f3af97 | 5350 | if ((dest + 1) >= i.operands |
f12dc422 L |
5351 | || (op.bitfield.reg32 != 1 |
5352 | && !op.bitfield.reg64 != 1 | |
5353 | && !operand_type_equal (&op, ®xmm) | |
fa99fab2 | 5354 | && !operand_type_equal (&op, ®ymm))) |
c0f3af97 | 5355 | abort (); |
f12dc422 | 5356 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
5357 | dest++; |
5358 | } | |
5359 | } | |
29b0f896 AM |
5360 | |
5361 | i.rm.mode = 3; | |
5362 | /* One of the register operands will be encoded in the i.tm.reg | |
5363 | field, the other in the combined i.tm.mode and i.tm.regmem | |
5364 | fields. If no form of this instruction supports a memory | |
5365 | destination operand, then we assume the source operand may | |
5366 | sometimes be a memory operand and so we need to store the | |
5367 | destination in the i.rm.reg field. */ | |
40fb9820 L |
5368 | if (!i.tm.operand_types[dest].bitfield.regmem |
5369 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
5370 | { |
5371 | i.rm.reg = i.op[dest].regs->reg_num; | |
5372 | i.rm.regmem = i.op[source].regs->reg_num; | |
5373 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5374 | i.rex |= REX_R; |
29b0f896 | 5375 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5376 | i.rex |= REX_B; |
29b0f896 AM |
5377 | } |
5378 | else | |
5379 | { | |
5380 | i.rm.reg = i.op[source].regs->reg_num; | |
5381 | i.rm.regmem = i.op[dest].regs->reg_num; | |
5382 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5383 | i.rex |= REX_B; |
29b0f896 | 5384 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5385 | i.rex |= REX_R; |
29b0f896 | 5386 | } |
161a04f6 | 5387 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 5388 | { |
40fb9820 L |
5389 | if (!i.types[0].bitfield.control |
5390 | && !i.types[1].bitfield.control) | |
c4a530c5 | 5391 | abort (); |
161a04f6 | 5392 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
5393 | add_prefix (LOCK_PREFIX_OPCODE); |
5394 | } | |
29b0f896 AM |
5395 | } |
5396 | else | |
5397 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
5398 | unsigned int mem; |
5399 | ||
29b0f896 AM |
5400 | if (i.mem_operands) |
5401 | { | |
5402 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 5403 | unsigned int op; |
4eed87de | 5404 | |
7ab9ffdd L |
5405 | for (op = 0; op < i.operands; op++) |
5406 | if (operand_type_check (i.types[op], anymem)) | |
5407 | break; | |
7ab9ffdd | 5408 | gas_assert (op < i.operands); |
29b0f896 AM |
5409 | |
5410 | default_seg = &ds; | |
5411 | ||
5412 | if (i.base_reg == 0) | |
5413 | { | |
5414 | i.rm.mode = 0; | |
5415 | if (!i.disp_operands) | |
5416 | fake_zero_displacement = 1; | |
5417 | if (i.index_reg == 0) | |
5418 | { | |
5419 | /* Operand is just <disp> */ | |
20f0a1fc | 5420 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
5421 | { |
5422 | /* 64bit mode overwrites the 32bit absolute | |
5423 | addressing by RIP relative addressing and | |
5424 | absolute addressing is encoded by one of the | |
5425 | redundant SIB forms. */ | |
5426 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
5427 | i.sib.base = NO_BASE_REGISTER; | |
5428 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 5429 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 5430 | ? disp32s : disp32); |
20f0a1fc | 5431 | } |
fc225355 L |
5432 | else if ((flag_code == CODE_16BIT) |
5433 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
5434 | { |
5435 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 5436 | i.types[op] = disp16; |
20f0a1fc NC |
5437 | } |
5438 | else | |
5439 | { | |
5440 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 5441 | i.types[op] = disp32; |
29b0f896 AM |
5442 | } |
5443 | } | |
5444 | else /* !i.base_reg && i.index_reg */ | |
5445 | { | |
db51cc60 L |
5446 | if (i.index_reg->reg_num == RegEiz |
5447 | || i.index_reg->reg_num == RegRiz) | |
5448 | i.sib.index = NO_INDEX_REGISTER; | |
5449 | else | |
5450 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5451 | i.sib.base = NO_BASE_REGISTER; |
5452 | i.sib.scale = i.log2_scale_factor; | |
5453 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
5454 | i.types[op].bitfield.disp8 = 0; |
5455 | i.types[op].bitfield.disp16 = 0; | |
5456 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 5457 | if (flag_code != CODE_64BIT) |
40fb9820 L |
5458 | { |
5459 | /* Must be 32 bit */ | |
5460 | i.types[op].bitfield.disp32 = 1; | |
5461 | i.types[op].bitfield.disp32s = 0; | |
5462 | } | |
29b0f896 | 5463 | else |
40fb9820 L |
5464 | { |
5465 | i.types[op].bitfield.disp32 = 0; | |
5466 | i.types[op].bitfield.disp32s = 1; | |
5467 | } | |
29b0f896 | 5468 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 5469 | i.rex |= REX_X; |
29b0f896 AM |
5470 | } |
5471 | } | |
5472 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
5473 | else if (i.base_reg->reg_num == RegRip || |
5474 | i.base_reg->reg_num == RegEip) | |
29b0f896 AM |
5475 | { |
5476 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 L |
5477 | i.types[op].bitfield.disp8 = 0; |
5478 | i.types[op].bitfield.disp16 = 0; | |
5479 | i.types[op].bitfield.disp32 = 0; | |
5480 | i.types[op].bitfield.disp32s = 1; | |
5481 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 5482 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
5483 | if (! i.disp_operands) |
5484 | fake_zero_displacement = 1; | |
29b0f896 | 5485 | } |
40fb9820 | 5486 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 AM |
5487 | { |
5488 | switch (i.base_reg->reg_num) | |
5489 | { | |
5490 | case 3: /* (%bx) */ | |
5491 | if (i.index_reg == 0) | |
5492 | i.rm.regmem = 7; | |
5493 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
5494 | i.rm.regmem = i.index_reg->reg_num - 6; | |
5495 | break; | |
5496 | case 5: /* (%bp) */ | |
5497 | default_seg = &ss; | |
5498 | if (i.index_reg == 0) | |
5499 | { | |
5500 | i.rm.regmem = 6; | |
40fb9820 | 5501 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
5502 | { |
5503 | /* fake (%bp) into 0(%bp) */ | |
40fb9820 | 5504 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5505 | fake_zero_displacement = 1; |
29b0f896 AM |
5506 | } |
5507 | } | |
5508 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
5509 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
5510 | break; | |
5511 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
5512 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
5513 | } | |
5514 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
5515 | } | |
5516 | else /* i.base_reg and 32/64 bit mode */ | |
5517 | { | |
5518 | if (flag_code == CODE_64BIT | |
40fb9820 L |
5519 | && operand_type_check (i.types[op], disp)) |
5520 | { | |
5521 | i386_operand_type temp; | |
0dfbf9d7 | 5522 | operand_type_set (&temp, 0); |
40fb9820 L |
5523 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
5524 | i.types[op] = temp; | |
5525 | if (i.prefix[ADDR_PREFIX] == 0) | |
5526 | i.types[op].bitfield.disp32s = 1; | |
5527 | else | |
5528 | i.types[op].bitfield.disp32 = 1; | |
5529 | } | |
20f0a1fc | 5530 | |
29b0f896 AM |
5531 | i.rm.regmem = i.base_reg->reg_num; |
5532 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5533 | i.rex |= REX_B; |
29b0f896 AM |
5534 | i.sib.base = i.base_reg->reg_num; |
5535 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
5536 | complications. */ | |
5537 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
5538 | { | |
5539 | default_seg = &ss; | |
5540 | if (i.disp_operands == 0) | |
5541 | { | |
5542 | fake_zero_displacement = 1; | |
40fb9820 | 5543 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
5544 | } |
5545 | } | |
5546 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
5547 | { | |
5548 | default_seg = &ss; | |
5549 | } | |
5550 | i.sib.scale = i.log2_scale_factor; | |
5551 | if (i.index_reg == 0) | |
5552 | { | |
5553 | /* <disp>(%esp) becomes two byte modrm with no index | |
5554 | register. We've already stored the code for esp | |
5555 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
5556 | Any base register besides %esp will not use the | |
5557 | extra modrm byte. */ | |
5558 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 AM |
5559 | } |
5560 | else | |
5561 | { | |
db51cc60 L |
5562 | if (i.index_reg->reg_num == RegEiz |
5563 | || i.index_reg->reg_num == RegRiz) | |
5564 | i.sib.index = NO_INDEX_REGISTER; | |
5565 | else | |
5566 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5567 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
5568 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5569 | i.rex |= REX_X; |
29b0f896 | 5570 | } |
67a4f2b7 AO |
5571 | |
5572 | if (i.disp_operands | |
5573 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
5574 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
5575 | i.rm.mode = 0; | |
5576 | else | |
5577 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
29b0f896 | 5578 | } |
252b5132 | 5579 | |
29b0f896 AM |
5580 | if (fake_zero_displacement) |
5581 | { | |
5582 | /* Fakes a zero displacement assuming that i.types[op] | |
5583 | holds the correct displacement size. */ | |
5584 | expressionS *exp; | |
5585 | ||
9c2799c2 | 5586 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
5587 | exp = &disp_expressions[i.disp_operands++]; |
5588 | i.op[op].disps = exp; | |
5589 | exp->X_op = O_constant; | |
5590 | exp->X_add_number = 0; | |
5591 | exp->X_add_symbol = (symbolS *) 0; | |
5592 | exp->X_op_symbol = (symbolS *) 0; | |
5593 | } | |
c0f3af97 L |
5594 | |
5595 | mem = op; | |
29b0f896 | 5596 | } |
c0f3af97 L |
5597 | else |
5598 | mem = ~0; | |
252b5132 | 5599 | |
8c43a48b | 5600 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
5601 | { |
5602 | if (operand_type_check (i.types[0], imm)) | |
5603 | i.vex.register_specifier = NULL; | |
5604 | else | |
5605 | { | |
5606 | /* VEX.vvvv encodes one of the sources when the first | |
5607 | operand is not an immediate. */ | |
1ef99a7b | 5608 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
5609 | i.vex.register_specifier = i.op[0].regs; |
5610 | else | |
5611 | i.vex.register_specifier = i.op[1].regs; | |
5612 | } | |
5613 | ||
5614 | /* Destination is a XMM register encoded in the ModRM.reg | |
5615 | and VEX.R bit. */ | |
5616 | i.rm.reg = i.op[2].regs->reg_num; | |
5617 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
5618 | i.rex |= REX_R; | |
5619 | ||
5620 | /* ModRM.rm and VEX.B encodes the other source. */ | |
5621 | if (!i.mem_operands) | |
5622 | { | |
5623 | i.rm.mode = 3; | |
5624 | ||
1ef99a7b | 5625 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
5626 | i.rm.regmem = i.op[1].regs->reg_num; |
5627 | else | |
5628 | i.rm.regmem = i.op[0].regs->reg_num; | |
5629 | ||
5630 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
5631 | i.rex |= REX_B; | |
5632 | } | |
5633 | } | |
2426c15f | 5634 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
5635 | { |
5636 | i.vex.register_specifier = i.op[2].regs; | |
5637 | if (!i.mem_operands) | |
5638 | { | |
5639 | i.rm.mode = 3; | |
5640 | i.rm.regmem = i.op[1].regs->reg_num; | |
5641 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
5642 | i.rex |= REX_B; | |
5643 | } | |
5644 | } | |
29b0f896 AM |
5645 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
5646 | (if any) based on i.tm.extension_opcode. Again, we must be | |
5647 | careful to make sure that segment/control/debug/test/MMX | |
5648 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 5649 | else if (i.reg_operands) |
29b0f896 | 5650 | { |
99018f42 | 5651 | unsigned int op; |
7ab9ffdd L |
5652 | unsigned int vex_reg = ~0; |
5653 | ||
5654 | for (op = 0; op < i.operands; op++) | |
5655 | if (i.types[op].bitfield.reg8 | |
5656 | || i.types[op].bitfield.reg16 | |
5657 | || i.types[op].bitfield.reg32 | |
5658 | || i.types[op].bitfield.reg64 | |
5659 | || i.types[op].bitfield.regmmx | |
5660 | || i.types[op].bitfield.regxmm | |
5661 | || i.types[op].bitfield.regymm | |
5662 | || i.types[op].bitfield.sreg2 | |
5663 | || i.types[op].bitfield.sreg3 | |
5664 | || i.types[op].bitfield.control | |
5665 | || i.types[op].bitfield.debug | |
5666 | || i.types[op].bitfield.test) | |
5667 | break; | |
c0209578 | 5668 | |
7ab9ffdd L |
5669 | if (vex_3_sources) |
5670 | op = dest; | |
2426c15f | 5671 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
5672 | { |
5673 | /* For instructions with VexNDS, the register-only | |
5674 | source operand is encoded in VEX prefix. */ | |
5675 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 5676 | |
7ab9ffdd | 5677 | if (op > mem) |
c0f3af97 | 5678 | { |
7ab9ffdd L |
5679 | vex_reg = op++; |
5680 | gas_assert (op < i.operands); | |
c0f3af97 L |
5681 | } |
5682 | else | |
c0f3af97 | 5683 | { |
f12dc422 L |
5684 | /* Check register-only source operand when two source |
5685 | operands are swapped. */ | |
5686 | if (!i.tm.operand_types[op].bitfield.baseindex | |
5687 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
5688 | { | |
5689 | vex_reg = op; | |
5690 | op += 2; | |
5691 | gas_assert (mem == (vex_reg + 1) | |
5692 | && op < i.operands); | |
5693 | } | |
5694 | else | |
5695 | { | |
5696 | vex_reg = op + 1; | |
5697 | gas_assert (vex_reg < i.operands); | |
5698 | } | |
c0f3af97 | 5699 | } |
7ab9ffdd | 5700 | } |
2426c15f | 5701 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 5702 | { |
f12dc422 | 5703 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 5704 | is encoded in VEX prefix. */ |
f12dc422 L |
5705 | if (i.mem_operands == 0) |
5706 | { | |
5707 | /* There is no memory operand. */ | |
5708 | gas_assert ((op + 2) == i.operands); | |
5709 | vex_reg = op + 1; | |
5710 | } | |
5711 | else | |
5712 | { | |
5713 | /* There are only 2 operands. */ | |
5714 | gas_assert (op < 2 && i.operands == 2); | |
5715 | vex_reg = 1; | |
5716 | } | |
7ab9ffdd L |
5717 | } |
5718 | else | |
5719 | gas_assert (op < i.operands); | |
99018f42 | 5720 | |
7ab9ffdd L |
5721 | if (vex_reg != (unsigned int) ~0) |
5722 | { | |
f12dc422 | 5723 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 5724 | |
f12dc422 L |
5725 | if (type->bitfield.reg32 != 1 |
5726 | && type->bitfield.reg64 != 1 | |
5727 | && !operand_type_equal (type, ®xmm) | |
5728 | && !operand_type_equal (type, ®ymm)) | |
7ab9ffdd | 5729 | abort (); |
f88c9eb0 | 5730 | |
7ab9ffdd L |
5731 | i.vex.register_specifier = i.op[vex_reg].regs; |
5732 | } | |
5733 | ||
1b9f0c97 L |
5734 | /* Don't set OP operand twice. */ |
5735 | if (vex_reg != op) | |
7ab9ffdd | 5736 | { |
1b9f0c97 L |
5737 | /* If there is an extension opcode to put here, the |
5738 | register number must be put into the regmem field. */ | |
5739 | if (i.tm.extension_opcode != None) | |
5740 | { | |
5741 | i.rm.regmem = i.op[op].regs->reg_num; | |
5742 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5743 | i.rex |= REX_B; | |
5744 | } | |
5745 | else | |
5746 | { | |
5747 | i.rm.reg = i.op[op].regs->reg_num; | |
5748 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5749 | i.rex |= REX_R; | |
5750 | } | |
7ab9ffdd | 5751 | } |
252b5132 | 5752 | |
29b0f896 AM |
5753 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
5754 | must set it to 3 to indicate this is a register operand | |
5755 | in the regmem field. */ | |
5756 | if (!i.mem_operands) | |
5757 | i.rm.mode = 3; | |
5758 | } | |
252b5132 | 5759 | |
29b0f896 | 5760 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 5761 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
5762 | i.rm.reg = i.tm.extension_opcode; |
5763 | } | |
5764 | return default_seg; | |
5765 | } | |
252b5132 | 5766 | |
29b0f896 | 5767 | static void |
e3bb37b5 | 5768 | output_branch (void) |
29b0f896 AM |
5769 | { |
5770 | char *p; | |
f8a5c266 | 5771 | int size; |
29b0f896 AM |
5772 | int code16; |
5773 | int prefix; | |
5774 | relax_substateT subtype; | |
5775 | symbolS *sym; | |
5776 | offsetT off; | |
5777 | ||
f8a5c266 L |
5778 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
5779 | size = i.disp32_encoding ? BIG : SMALL; | |
29b0f896 AM |
5780 | |
5781 | prefix = 0; | |
5782 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 5783 | { |
29b0f896 AM |
5784 | prefix = 1; |
5785 | i.prefixes -= 1; | |
5786 | code16 ^= CODE16; | |
252b5132 | 5787 | } |
29b0f896 AM |
5788 | /* Pentium4 branch hints. */ |
5789 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5790 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 5791 | { |
29b0f896 AM |
5792 | prefix++; |
5793 | i.prefixes--; | |
5794 | } | |
5795 | if (i.prefix[REX_PREFIX] != 0) | |
5796 | { | |
5797 | prefix++; | |
5798 | i.prefixes--; | |
2f66722d AM |
5799 | } |
5800 | ||
29b0f896 AM |
5801 | if (i.prefixes != 0 && !intel_syntax) |
5802 | as_warn (_("skipping prefixes on this instruction")); | |
5803 | ||
5804 | /* It's always a symbol; End frag & setup for relax. | |
5805 | Make sure there is enough room in this frag for the largest | |
5806 | instruction we may generate in md_convert_frag. This is 2 | |
5807 | bytes for the opcode and room for the prefix and largest | |
5808 | displacement. */ | |
5809 | frag_grow (prefix + 2 + 4); | |
5810 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
5811 | p = frag_more (prefix + 1); | |
5812 | if (i.prefix[DATA_PREFIX] != 0) | |
5813 | *p++ = DATA_PREFIX_OPCODE; | |
5814 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
5815 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
5816 | *p++ = i.prefix[SEG_PREFIX]; | |
5817 | if (i.prefix[REX_PREFIX] != 0) | |
5818 | *p++ = i.prefix[REX_PREFIX]; | |
5819 | *p = i.tm.base_opcode; | |
5820 | ||
5821 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 5822 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 5823 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 5824 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 5825 | else |
f8a5c266 | 5826 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 5827 | subtype |= code16; |
3e73aa7c | 5828 | |
29b0f896 AM |
5829 | sym = i.op[0].disps->X_add_symbol; |
5830 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 5831 | |
29b0f896 AM |
5832 | if (i.op[0].disps->X_op != O_constant |
5833 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 5834 | { |
29b0f896 AM |
5835 | /* Handle complex expressions. */ |
5836 | sym = make_expr_symbol (i.op[0].disps); | |
5837 | off = 0; | |
5838 | } | |
3e73aa7c | 5839 | |
29b0f896 AM |
5840 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
5841 | Pass reloc in fr_var. */ | |
5842 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
5843 | } | |
3e73aa7c | 5844 | |
29b0f896 | 5845 | static void |
e3bb37b5 | 5846 | output_jump (void) |
29b0f896 AM |
5847 | { |
5848 | char *p; | |
5849 | int size; | |
3e02c1cc | 5850 | fixS *fixP; |
29b0f896 | 5851 | |
40fb9820 | 5852 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
5853 | { |
5854 | /* This is a loop or jecxz type instruction. */ | |
5855 | size = 1; | |
5856 | if (i.prefix[ADDR_PREFIX] != 0) | |
5857 | { | |
5858 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
5859 | i.prefixes -= 1; | |
5860 | } | |
5861 | /* Pentium4 branch hints. */ | |
5862 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5863 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
5864 | { | |
5865 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
5866 | i.prefixes--; | |
3e73aa7c JH |
5867 | } |
5868 | } | |
29b0f896 AM |
5869 | else |
5870 | { | |
5871 | int code16; | |
3e73aa7c | 5872 | |
29b0f896 AM |
5873 | code16 = 0; |
5874 | if (flag_code == CODE_16BIT) | |
5875 | code16 = CODE16; | |
3e73aa7c | 5876 | |
29b0f896 AM |
5877 | if (i.prefix[DATA_PREFIX] != 0) |
5878 | { | |
5879 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
5880 | i.prefixes -= 1; | |
5881 | code16 ^= CODE16; | |
5882 | } | |
252b5132 | 5883 | |
29b0f896 AM |
5884 | size = 4; |
5885 | if (code16) | |
5886 | size = 2; | |
5887 | } | |
9fcc94b6 | 5888 | |
29b0f896 AM |
5889 | if (i.prefix[REX_PREFIX] != 0) |
5890 | { | |
5891 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
5892 | i.prefixes -= 1; | |
5893 | } | |
252b5132 | 5894 | |
29b0f896 AM |
5895 | if (i.prefixes != 0 && !intel_syntax) |
5896 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 5897 | |
29b0f896 AM |
5898 | p = frag_more (1 + size); |
5899 | *p++ = i.tm.base_opcode; | |
e0890092 | 5900 | |
3e02c1cc AM |
5901 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
5902 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
5903 | ||
5904 | /* All jumps handled here are signed, but don't use a signed limit | |
5905 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
5906 | 4G and 64k respectively. */ | |
5907 | if (size == 1) | |
5908 | fixP->fx_signed = 1; | |
29b0f896 | 5909 | } |
e0890092 | 5910 | |
29b0f896 | 5911 | static void |
e3bb37b5 | 5912 | output_interseg_jump (void) |
29b0f896 AM |
5913 | { |
5914 | char *p; | |
5915 | int size; | |
5916 | int prefix; | |
5917 | int code16; | |
252b5132 | 5918 | |
29b0f896 AM |
5919 | code16 = 0; |
5920 | if (flag_code == CODE_16BIT) | |
5921 | code16 = CODE16; | |
a217f122 | 5922 | |
29b0f896 AM |
5923 | prefix = 0; |
5924 | if (i.prefix[DATA_PREFIX] != 0) | |
5925 | { | |
5926 | prefix = 1; | |
5927 | i.prefixes -= 1; | |
5928 | code16 ^= CODE16; | |
5929 | } | |
5930 | if (i.prefix[REX_PREFIX] != 0) | |
5931 | { | |
5932 | prefix++; | |
5933 | i.prefixes -= 1; | |
5934 | } | |
252b5132 | 5935 | |
29b0f896 AM |
5936 | size = 4; |
5937 | if (code16) | |
5938 | size = 2; | |
252b5132 | 5939 | |
29b0f896 AM |
5940 | if (i.prefixes != 0 && !intel_syntax) |
5941 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 5942 | |
29b0f896 AM |
5943 | /* 1 opcode; 2 segment; offset */ |
5944 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 5945 | |
29b0f896 AM |
5946 | if (i.prefix[DATA_PREFIX] != 0) |
5947 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 5948 | |
29b0f896 AM |
5949 | if (i.prefix[REX_PREFIX] != 0) |
5950 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 5951 | |
29b0f896 AM |
5952 | *p++ = i.tm.base_opcode; |
5953 | if (i.op[1].imms->X_op == O_constant) | |
5954 | { | |
5955 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 5956 | |
29b0f896 AM |
5957 | if (size == 2 |
5958 | && !fits_in_unsigned_word (n) | |
5959 | && !fits_in_signed_word (n)) | |
5960 | { | |
5961 | as_bad (_("16-bit jump out of range")); | |
5962 | return; | |
5963 | } | |
5964 | md_number_to_chars (p, n, size); | |
5965 | } | |
5966 | else | |
5967 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
5968 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
5969 | if (i.op[0].imms->X_op != O_constant) | |
5970 | as_bad (_("can't handle non absolute segment in `%s'"), | |
5971 | i.tm.name); | |
5972 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
5973 | } | |
a217f122 | 5974 | |
29b0f896 | 5975 | static void |
e3bb37b5 | 5976 | output_insn (void) |
29b0f896 | 5977 | { |
2bbd9c25 JJ |
5978 | fragS *insn_start_frag; |
5979 | offsetT insn_start_off; | |
5980 | ||
29b0f896 AM |
5981 | /* Tie dwarf2 debug info to the address at the start of the insn. |
5982 | We can't do this after the insn has been output as the current | |
5983 | frag may have been closed off. eg. by frag_var. */ | |
5984 | dwarf2_emit_insn (0); | |
5985 | ||
2bbd9c25 JJ |
5986 | insn_start_frag = frag_now; |
5987 | insn_start_off = frag_now_fix (); | |
5988 | ||
29b0f896 | 5989 | /* Output jumps. */ |
40fb9820 | 5990 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 5991 | output_branch (); |
40fb9820 L |
5992 | else if (i.tm.opcode_modifier.jumpbyte |
5993 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 5994 | output_jump (); |
40fb9820 | 5995 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
5996 | output_interseg_jump (); |
5997 | else | |
5998 | { | |
5999 | /* Output normal instructions here. */ | |
6000 | char *p; | |
6001 | unsigned char *q; | |
47465058 | 6002 | unsigned int j; |
331d2d0d | 6003 | unsigned int prefix; |
4dffcebc | 6004 | |
c0f3af97 L |
6005 | /* Since the VEX prefix contains the implicit prefix, we don't |
6006 | need the explicit prefix. */ | |
6007 | if (!i.tm.opcode_modifier.vex) | |
bc4bd9ab | 6008 | { |
c0f3af97 | 6009 | switch (i.tm.opcode_length) |
bc4bd9ab | 6010 | { |
c0f3af97 L |
6011 | case 3: |
6012 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 6013 | { |
c0f3af97 L |
6014 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
6015 | goto check_prefix; | |
6016 | } | |
6017 | break; | |
6018 | case 2: | |
6019 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
6020 | { | |
6021 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
6022 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
6023 | { | |
4dffcebc | 6024 | check_prefix: |
c0f3af97 | 6025 | if (prefix != REPE_PREFIX_OPCODE |
c32fa91d | 6026 | || (i.prefix[REP_PREFIX] |
c0f3af97 L |
6027 | != REPE_PREFIX_OPCODE)) |
6028 | add_prefix (prefix); | |
6029 | } | |
6030 | else | |
4dffcebc L |
6031 | add_prefix (prefix); |
6032 | } | |
c0f3af97 L |
6033 | break; |
6034 | case 1: | |
6035 | break; | |
6036 | default: | |
6037 | abort (); | |
bc4bd9ab | 6038 | } |
c0f3af97 L |
6039 | |
6040 | /* The prefix bytes. */ | |
6041 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
6042 | if (*q) | |
6043 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 6044 | } |
252b5132 | 6045 | |
c0f3af97 L |
6046 | if (i.tm.opcode_modifier.vex) |
6047 | { | |
6048 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
6049 | if (*q) | |
6050 | switch (j) | |
6051 | { | |
6052 | case REX_PREFIX: | |
6053 | /* REX byte is encoded in VEX prefix. */ | |
6054 | break; | |
6055 | case SEG_PREFIX: | |
6056 | case ADDR_PREFIX: | |
6057 | FRAG_APPEND_1_CHAR (*q); | |
6058 | break; | |
6059 | default: | |
6060 | /* There should be no other prefixes for instructions | |
6061 | with VEX prefix. */ | |
6062 | abort (); | |
6063 | } | |
6064 | ||
6065 | /* Now the VEX prefix. */ | |
6066 | p = frag_more (i.vex.length); | |
6067 | for (j = 0; j < i.vex.length; j++) | |
6068 | p[j] = i.vex.bytes[j]; | |
6069 | } | |
252b5132 | 6070 | |
29b0f896 | 6071 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 6072 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
6073 | { |
6074 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
6075 | } | |
6076 | else | |
6077 | { | |
4dffcebc | 6078 | switch (i.tm.opcode_length) |
331d2d0d | 6079 | { |
4dffcebc | 6080 | case 3: |
331d2d0d L |
6081 | p = frag_more (3); |
6082 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
6083 | break; |
6084 | case 2: | |
6085 | p = frag_more (2); | |
6086 | break; | |
6087 | default: | |
6088 | abort (); | |
6089 | break; | |
331d2d0d | 6090 | } |
0f10071e | 6091 | |
29b0f896 AM |
6092 | /* Put out high byte first: can't use md_number_to_chars! */ |
6093 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
6094 | *p = i.tm.base_opcode & 0xff; | |
6095 | } | |
3e73aa7c | 6096 | |
29b0f896 | 6097 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 6098 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 6099 | { |
4a3523fa L |
6100 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
6101 | | i.rm.reg << 3 | |
6102 | | i.rm.mode << 6)); | |
29b0f896 AM |
6103 | /* If i.rm.regmem == ESP (4) |
6104 | && i.rm.mode != (Register mode) | |
6105 | && not 16 bit | |
6106 | ==> need second modrm byte. */ | |
6107 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
6108 | && i.rm.mode != 3 | |
40fb9820 | 6109 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
6110 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
6111 | | i.sib.index << 3 | |
6112 | | i.sib.scale << 6)); | |
29b0f896 | 6113 | } |
3e73aa7c | 6114 | |
29b0f896 | 6115 | if (i.disp_operands) |
2bbd9c25 | 6116 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 6117 | |
29b0f896 | 6118 | if (i.imm_operands) |
2bbd9c25 | 6119 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 6120 | } |
252b5132 | 6121 | |
29b0f896 AM |
6122 | #ifdef DEBUG386 |
6123 | if (flag_debug) | |
6124 | { | |
7b81dfbb | 6125 | pi ("" /*line*/, &i); |
29b0f896 AM |
6126 | } |
6127 | #endif /* DEBUG386 */ | |
6128 | } | |
252b5132 | 6129 | |
e205caa7 L |
6130 | /* Return the size of the displacement operand N. */ |
6131 | ||
6132 | static int | |
6133 | disp_size (unsigned int n) | |
6134 | { | |
6135 | int size = 4; | |
40fb9820 L |
6136 | if (i.types[n].bitfield.disp64) |
6137 | size = 8; | |
6138 | else if (i.types[n].bitfield.disp8) | |
6139 | size = 1; | |
6140 | else if (i.types[n].bitfield.disp16) | |
6141 | size = 2; | |
e205caa7 L |
6142 | return size; |
6143 | } | |
6144 | ||
6145 | /* Return the size of the immediate operand N. */ | |
6146 | ||
6147 | static int | |
6148 | imm_size (unsigned int n) | |
6149 | { | |
6150 | int size = 4; | |
40fb9820 L |
6151 | if (i.types[n].bitfield.imm64) |
6152 | size = 8; | |
6153 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
6154 | size = 1; | |
6155 | else if (i.types[n].bitfield.imm16) | |
6156 | size = 2; | |
e205caa7 L |
6157 | return size; |
6158 | } | |
6159 | ||
29b0f896 | 6160 | static void |
64e74474 | 6161 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6162 | { |
6163 | char *p; | |
6164 | unsigned int n; | |
252b5132 | 6165 | |
29b0f896 AM |
6166 | for (n = 0; n < i.operands; n++) |
6167 | { | |
40fb9820 | 6168 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
6169 | { |
6170 | if (i.op[n].disps->X_op == O_constant) | |
6171 | { | |
e205caa7 | 6172 | int size = disp_size (n); |
29b0f896 | 6173 | offsetT val; |
252b5132 | 6174 | |
29b0f896 AM |
6175 | val = offset_in_range (i.op[n].disps->X_add_number, |
6176 | size); | |
6177 | p = frag_more (size); | |
6178 | md_number_to_chars (p, val, size); | |
6179 | } | |
6180 | else | |
6181 | { | |
f86103b7 | 6182 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 6183 | int size = disp_size (n); |
40fb9820 | 6184 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 AM |
6185 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
6186 | ||
e205caa7 | 6187 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 6188 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 6189 | |
29b0f896 AM |
6190 | /* The PC relative address is computed relative |
6191 | to the instruction boundary, so in case immediate | |
6192 | fields follows, we need to adjust the value. */ | |
6193 | if (pcrel && i.imm_operands) | |
6194 | { | |
29b0f896 | 6195 | unsigned int n1; |
e205caa7 | 6196 | int sz = 0; |
252b5132 | 6197 | |
29b0f896 | 6198 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 6199 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 6200 | { |
e205caa7 L |
6201 | /* Only one immediate is allowed for PC |
6202 | relative address. */ | |
9c2799c2 | 6203 | gas_assert (sz == 0); |
e205caa7 L |
6204 | sz = imm_size (n1); |
6205 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 6206 | } |
29b0f896 | 6207 | /* We should find the immediate. */ |
9c2799c2 | 6208 | gas_assert (sz != 0); |
29b0f896 | 6209 | } |
520dc8e8 | 6210 | |
29b0f896 | 6211 | p = frag_more (size); |
2bbd9c25 | 6212 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 6213 | if (GOT_symbol |
2bbd9c25 | 6214 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 6215 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6216 | || reloc_type == BFD_RELOC_X86_64_32S |
6217 | || (reloc_type == BFD_RELOC_64 | |
6218 | && object_64bit)) | |
d6ab8113 JB |
6219 | && (i.op[n].disps->X_op == O_symbol |
6220 | || (i.op[n].disps->X_op == O_add | |
6221 | && ((symbol_get_value_expression | |
6222 | (i.op[n].disps->X_op_symbol)->X_op) | |
6223 | == O_subtract)))) | |
6224 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
6225 | { |
6226 | offsetT add; | |
6227 | ||
6228 | if (insn_start_frag == frag_now) | |
6229 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6230 | else | |
6231 | { | |
6232 | fragS *fr; | |
6233 | ||
6234 | add = insn_start_frag->fr_fix - insn_start_off; | |
6235 | for (fr = insn_start_frag->fr_next; | |
6236 | fr && fr != frag_now; fr = fr->fr_next) | |
6237 | add += fr->fr_fix; | |
6238 | add += p - frag_now->fr_literal; | |
6239 | } | |
6240 | ||
4fa24527 | 6241 | if (!object_64bit) |
7b81dfbb AJ |
6242 | { |
6243 | reloc_type = BFD_RELOC_386_GOTPC; | |
6244 | i.op[n].imms->X_add_number += add; | |
6245 | } | |
6246 | else if (reloc_type == BFD_RELOC_64) | |
6247 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 6248 | else |
7b81dfbb AJ |
6249 | /* Don't do the adjustment for x86-64, as there |
6250 | the pcrel addressing is relative to the _next_ | |
6251 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 6252 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 6253 | } |
062cd5e7 | 6254 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 6255 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
6256 | } |
6257 | } | |
6258 | } | |
6259 | } | |
252b5132 | 6260 | |
29b0f896 | 6261 | static void |
64e74474 | 6262 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6263 | { |
6264 | char *p; | |
6265 | unsigned int n; | |
252b5132 | 6266 | |
29b0f896 AM |
6267 | for (n = 0; n < i.operands; n++) |
6268 | { | |
40fb9820 | 6269 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
6270 | { |
6271 | if (i.op[n].imms->X_op == O_constant) | |
6272 | { | |
e205caa7 | 6273 | int size = imm_size (n); |
29b0f896 | 6274 | offsetT val; |
b4cac588 | 6275 | |
29b0f896 AM |
6276 | val = offset_in_range (i.op[n].imms->X_add_number, |
6277 | size); | |
6278 | p = frag_more (size); | |
6279 | md_number_to_chars (p, val, size); | |
6280 | } | |
6281 | else | |
6282 | { | |
6283 | /* Not absolute_section. | |
6284 | Need a 32-bit fixup (don't support 8bit | |
6285 | non-absolute imms). Try to support other | |
6286 | sizes ... */ | |
f86103b7 | 6287 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
6288 | int size = imm_size (n); |
6289 | int sign; | |
29b0f896 | 6290 | |
40fb9820 | 6291 | if (i.types[n].bitfield.imm32s |
a7d61044 | 6292 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 6293 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 6294 | sign = 1; |
e205caa7 L |
6295 | else |
6296 | sign = 0; | |
520dc8e8 | 6297 | |
29b0f896 AM |
6298 | p = frag_more (size); |
6299 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 6300 | |
2bbd9c25 JJ |
6301 | /* This is tough to explain. We end up with this one if we |
6302 | * have operands that look like | |
6303 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
6304 | * obtain the absolute address of the GOT, and it is strongly | |
6305 | * preferable from a performance point of view to avoid using | |
6306 | * a runtime relocation for this. The actual sequence of | |
6307 | * instructions often look something like: | |
6308 | * | |
6309 | * call .L66 | |
6310 | * .L66: | |
6311 | * popl %ebx | |
6312 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
6313 | * | |
6314 | * The call and pop essentially return the absolute address | |
6315 | * of the label .L66 and store it in %ebx. The linker itself | |
6316 | * will ultimately change the first operand of the addl so | |
6317 | * that %ebx points to the GOT, but to keep things simple, the | |
6318 | * .o file must have this operand set so that it generates not | |
6319 | * the absolute address of .L66, but the absolute address of | |
6320 | * itself. This allows the linker itself simply treat a GOTPC | |
6321 | * relocation as asking for a pcrel offset to the GOT to be | |
6322 | * added in, and the addend of the relocation is stored in the | |
6323 | * operand field for the instruction itself. | |
6324 | * | |
6325 | * Our job here is to fix the operand so that it would add | |
6326 | * the correct offset so that %ebx would point to itself. The | |
6327 | * thing that is tricky is that .-.L66 will point to the | |
6328 | * beginning of the instruction, so we need to further modify | |
6329 | * the operand so that it will point to itself. There are | |
6330 | * other cases where you have something like: | |
6331 | * | |
6332 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
6333 | * | |
6334 | * and here no correction would be required. Internally in | |
6335 | * the assembler we treat operands of this form as not being | |
6336 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
6337 | * whether it would simplify matters to do it this way. Who | |
6338 | * knows. In earlier versions of the PIC patches, the | |
6339 | * pcrel_adjust field was used to store the correction, but | |
6340 | * since the expression is not pcrel, I felt it would be | |
6341 | * confusing to do it this way. */ | |
6342 | ||
d6ab8113 | 6343 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6344 | || reloc_type == BFD_RELOC_X86_64_32S |
6345 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
6346 | && GOT_symbol |
6347 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
6348 | && (i.op[n].imms->X_op == O_symbol | |
6349 | || (i.op[n].imms->X_op == O_add | |
6350 | && ((symbol_get_value_expression | |
6351 | (i.op[n].imms->X_op_symbol)->X_op) | |
6352 | == O_subtract)))) | |
6353 | { | |
2bbd9c25 JJ |
6354 | offsetT add; |
6355 | ||
6356 | if (insn_start_frag == frag_now) | |
6357 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6358 | else | |
6359 | { | |
6360 | fragS *fr; | |
6361 | ||
6362 | add = insn_start_frag->fr_fix - insn_start_off; | |
6363 | for (fr = insn_start_frag->fr_next; | |
6364 | fr && fr != frag_now; fr = fr->fr_next) | |
6365 | add += fr->fr_fix; | |
6366 | add += p - frag_now->fr_literal; | |
6367 | } | |
6368 | ||
4fa24527 | 6369 | if (!object_64bit) |
d6ab8113 | 6370 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 6371 | else if (size == 4) |
d6ab8113 | 6372 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
6373 | else if (size == 8) |
6374 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 6375 | i.op[n].imms->X_add_number += add; |
29b0f896 | 6376 | } |
29b0f896 AM |
6377 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
6378 | i.op[n].imms, 0, reloc_type); | |
6379 | } | |
6380 | } | |
6381 | } | |
252b5132 RH |
6382 | } |
6383 | \f | |
d182319b JB |
6384 | /* x86_cons_fix_new is called via the expression parsing code when a |
6385 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
6386 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; | |
6387 | static int cons_sign = -1; | |
6388 | ||
6389 | void | |
e3bb37b5 | 6390 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
64e74474 | 6391 | expressionS *exp) |
d182319b JB |
6392 | { |
6393 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); | |
6394 | ||
6395 | got_reloc = NO_RELOC; | |
6396 | ||
6397 | #ifdef TE_PE | |
6398 | if (exp->X_op == O_secrel) | |
6399 | { | |
6400 | exp->X_op = O_symbol; | |
6401 | r = BFD_RELOC_32_SECREL; | |
6402 | } | |
6403 | #endif | |
6404 | ||
6405 | fix_new_exp (frag, off, len, exp, 0, r); | |
6406 | } | |
6407 | ||
718ddfc0 JB |
6408 | #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) |
6409 | # define lex_got(reloc, adjust, types) NULL | |
6410 | #else | |
f3c180ae AM |
6411 | /* Parse operands of the form |
6412 | <symbol>@GOTOFF+<nnn> | |
6413 | and similar .plt or .got references. | |
6414 | ||
6415 | If we find one, set up the correct relocation in RELOC and copy the | |
6416 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
6417 | parsing by the calling routine. Return this buffer, and if ADJUST | |
6418 | is non-null set it to the length of the string we removed from the | |
6419 | input line. Otherwise return NULL. */ | |
6420 | static char * | |
91d6fa6a | 6421 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 6422 | int *adjust, |
40fb9820 | 6423 | i386_operand_type *types) |
f3c180ae | 6424 | { |
7b81dfbb AJ |
6425 | /* Some of the relocations depend on the size of what field is to |
6426 | be relocated. But in our callers i386_immediate and i386_displacement | |
6427 | we don't yet know the operand size (this will be set by insn | |
6428 | matching). Hence we record the word32 relocation here, | |
6429 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
6430 | static const struct { |
6431 | const char *str; | |
cff8d58a | 6432 | int len; |
4fa24527 | 6433 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 6434 | const i386_operand_type types64; |
f3c180ae | 6435 | } gotrel[] = { |
cff8d58a L |
6436 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
6437 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 6438 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
6439 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
6440 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 6441 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6442 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
6443 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 6444 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
6445 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
6446 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 6447 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
6448 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
6449 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 6450 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6451 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
6452 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 6453 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6454 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
6455 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6456 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6457 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
6458 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 6459 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6460 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
6461 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 6462 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6463 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
6464 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 6465 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
6466 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
6467 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6468 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6469 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
6470 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 6471 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
6472 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
6473 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6474 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6475 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
6476 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6477 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6478 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
6479 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 6480 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
6481 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
6482 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 6483 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6484 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
6485 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 6486 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
6487 | }; |
6488 | char *cp; | |
6489 | unsigned int j; | |
6490 | ||
718ddfc0 JB |
6491 | if (!IS_ELF) |
6492 | return NULL; | |
6493 | ||
f3c180ae | 6494 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 6495 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
6496 | return NULL; |
6497 | ||
47465058 | 6498 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 6499 | { |
cff8d58a | 6500 | int len = gotrel[j].len; |
28f81592 | 6501 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 6502 | { |
4fa24527 | 6503 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 6504 | { |
28f81592 AM |
6505 | int first, second; |
6506 | char *tmpbuf, *past_reloc; | |
f3c180ae | 6507 | |
91d6fa6a | 6508 | *rel = gotrel[j].rel[object_64bit]; |
28f81592 AM |
6509 | if (adjust) |
6510 | *adjust = len; | |
f3c180ae | 6511 | |
3956db08 JB |
6512 | if (types) |
6513 | { | |
6514 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
6515 | { |
6516 | types->bitfield.imm32 = 1; | |
6517 | types->bitfield.disp32 = 1; | |
6518 | } | |
3956db08 JB |
6519 | else |
6520 | *types = gotrel[j].types64; | |
6521 | } | |
6522 | ||
f3c180ae AM |
6523 | if (GOT_symbol == NULL) |
6524 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
6525 | ||
28f81592 | 6526 | /* The length of the first part of our input line. */ |
f3c180ae | 6527 | first = cp - input_line_pointer; |
28f81592 AM |
6528 | |
6529 | /* The second part goes from after the reloc token until | |
67c11a9b | 6530 | (and including) an end_of_line char or comma. */ |
28f81592 | 6531 | past_reloc = cp + 1 + len; |
67c11a9b AM |
6532 | cp = past_reloc; |
6533 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
6534 | ++cp; | |
6535 | second = cp + 1 - past_reloc; | |
28f81592 AM |
6536 | |
6537 | /* Allocate and copy string. The trailing NUL shouldn't | |
6538 | be necessary, but be safe. */ | |
1e9cc1c2 | 6539 | tmpbuf = (char *) xmalloc (first + second + 2); |
f3c180ae | 6540 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
6541 | if (second != 0 && *past_reloc != ' ') |
6542 | /* Replace the relocation token with ' ', so that | |
6543 | errors like foo@GOTOFF1 will be detected. */ | |
6544 | tmpbuf[first++] = ' '; | |
6545 | memcpy (tmpbuf + first, past_reloc, second); | |
6546 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
6547 | return tmpbuf; |
6548 | } | |
6549 | ||
4fa24527 JB |
6550 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
6551 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
6552 | return NULL; |
6553 | } | |
6554 | } | |
6555 | ||
6556 | /* Might be a symbol version string. Don't as_bad here. */ | |
6557 | return NULL; | |
6558 | } | |
6559 | ||
f3c180ae | 6560 | void |
e3bb37b5 | 6561 | x86_cons (expressionS *exp, int size) |
f3c180ae | 6562 | { |
ee86248c JB |
6563 | intel_syntax = -intel_syntax; |
6564 | ||
3c7b9c2c | 6565 | exp->X_md = 0; |
4fa24527 | 6566 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
6567 | { |
6568 | /* Handle @GOTOFF and the like in an expression. */ | |
6569 | char *save; | |
6570 | char *gotfree_input_line; | |
6571 | int adjust; | |
6572 | ||
6573 | save = input_line_pointer; | |
3956db08 | 6574 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
6575 | if (gotfree_input_line) |
6576 | input_line_pointer = gotfree_input_line; | |
6577 | ||
6578 | expression (exp); | |
6579 | ||
6580 | if (gotfree_input_line) | |
6581 | { | |
6582 | /* expression () has merrily parsed up to the end of line, | |
6583 | or a comma - in the wrong buffer. Transfer how far | |
6584 | input_line_pointer has moved to the right buffer. */ | |
6585 | input_line_pointer = (save | |
6586 | + (input_line_pointer - gotfree_input_line) | |
6587 | + adjust); | |
6588 | free (gotfree_input_line); | |
3992d3b7 AM |
6589 | if (exp->X_op == O_constant |
6590 | || exp->X_op == O_absent | |
6591 | || exp->X_op == O_illegal | |
0398aac5 | 6592 | || exp->X_op == O_register |
3992d3b7 AM |
6593 | || exp->X_op == O_big) |
6594 | { | |
6595 | char c = *input_line_pointer; | |
6596 | *input_line_pointer = 0; | |
6597 | as_bad (_("missing or invalid expression `%s'"), save); | |
6598 | *input_line_pointer = c; | |
6599 | } | |
f3c180ae AM |
6600 | } |
6601 | } | |
6602 | else | |
6603 | expression (exp); | |
ee86248c JB |
6604 | |
6605 | intel_syntax = -intel_syntax; | |
6606 | ||
6607 | if (intel_syntax) | |
6608 | i386_intel_simplify (exp); | |
f3c180ae AM |
6609 | } |
6610 | #endif | |
6611 | ||
9f32dd5b L |
6612 | static void |
6613 | signed_cons (int size) | |
6482c264 | 6614 | { |
d182319b JB |
6615 | if (flag_code == CODE_64BIT) |
6616 | cons_sign = 1; | |
6617 | cons (size); | |
6618 | cons_sign = -1; | |
6482c264 NC |
6619 | } |
6620 | ||
d182319b | 6621 | #ifdef TE_PE |
6482c264 NC |
6622 | static void |
6623 | pe_directive_secrel (dummy) | |
6624 | int dummy ATTRIBUTE_UNUSED; | |
6625 | { | |
6626 | expressionS exp; | |
6627 | ||
6628 | do | |
6629 | { | |
6630 | expression (&exp); | |
6631 | if (exp.X_op == O_symbol) | |
6632 | exp.X_op = O_secrel; | |
6633 | ||
6634 | emit_expr (&exp, 4); | |
6635 | } | |
6636 | while (*input_line_pointer++ == ','); | |
6637 | ||
6638 | input_line_pointer--; | |
6639 | demand_empty_rest_of_line (); | |
6640 | } | |
6482c264 NC |
6641 | #endif |
6642 | ||
252b5132 | 6643 | static int |
70e41ade | 6644 | i386_immediate (char *imm_start) |
252b5132 RH |
6645 | { |
6646 | char *save_input_line_pointer; | |
f3c180ae | 6647 | char *gotfree_input_line; |
252b5132 | 6648 | segT exp_seg = 0; |
47926f60 | 6649 | expressionS *exp; |
40fb9820 L |
6650 | i386_operand_type types; |
6651 | ||
0dfbf9d7 | 6652 | operand_type_set (&types, ~0); |
252b5132 RH |
6653 | |
6654 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
6655 | { | |
31b2323c L |
6656 | as_bad (_("at most %d immediate operands are allowed"), |
6657 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
6658 | return 0; |
6659 | } | |
6660 | ||
6661 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 6662 | i.op[this_operand].imms = exp; |
252b5132 RH |
6663 | |
6664 | if (is_space_char (*imm_start)) | |
6665 | ++imm_start; | |
6666 | ||
6667 | save_input_line_pointer = input_line_pointer; | |
6668 | input_line_pointer = imm_start; | |
6669 | ||
3956db08 | 6670 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6671 | if (gotfree_input_line) |
6672 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
6673 | |
6674 | exp_seg = expression (exp); | |
6675 | ||
83183c0c | 6676 | SKIP_WHITESPACE (); |
252b5132 | 6677 | if (*input_line_pointer) |
f3c180ae | 6678 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
6679 | |
6680 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 6681 | if (gotfree_input_line) |
ee86248c JB |
6682 | { |
6683 | free (gotfree_input_line); | |
6684 | ||
6685 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
6686 | exp->X_op = O_illegal; | |
6687 | } | |
6688 | ||
6689 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
6690 | } | |
252b5132 | 6691 | |
ee86248c JB |
6692 | static int |
6693 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
6694 | i386_operand_type types, const char *imm_start) | |
6695 | { | |
6696 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 6697 | { |
313c53d1 L |
6698 | if (imm_start) |
6699 | as_bad (_("missing or invalid immediate expression `%s'"), | |
6700 | imm_start); | |
3992d3b7 | 6701 | return 0; |
252b5132 | 6702 | } |
3e73aa7c | 6703 | else if (exp->X_op == O_constant) |
252b5132 | 6704 | { |
47926f60 | 6705 | /* Size it properly later. */ |
40fb9820 | 6706 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
6707 | /* If not 64bit, sign extend val. */ |
6708 | if (flag_code != CODE_64BIT | |
4eed87de AM |
6709 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
6710 | exp->X_add_number | |
6711 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 6712 | } |
4c63da97 | 6713 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 6714 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 6715 | && exp_seg != absolute_section |
47926f60 | 6716 | && exp_seg != text_section |
24eab124 AM |
6717 | && exp_seg != data_section |
6718 | && exp_seg != bss_section | |
6719 | && exp_seg != undefined_section | |
f86103b7 | 6720 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 6721 | { |
d0b47220 | 6722 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
6723 | return 0; |
6724 | } | |
6725 | #endif | |
bb8f5920 L |
6726 | else if (!intel_syntax && exp->X_op == O_register) |
6727 | { | |
313c53d1 L |
6728 | if (imm_start) |
6729 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
6730 | return 0; |
6731 | } | |
252b5132 RH |
6732 | else |
6733 | { | |
6734 | /* This is an address. The size of the address will be | |
24eab124 | 6735 | determined later, depending on destination register, |
3e73aa7c | 6736 | suffix, or the default for the section. */ |
40fb9820 L |
6737 | i.types[this_operand].bitfield.imm8 = 1; |
6738 | i.types[this_operand].bitfield.imm16 = 1; | |
6739 | i.types[this_operand].bitfield.imm32 = 1; | |
6740 | i.types[this_operand].bitfield.imm32s = 1; | |
6741 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
6742 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
6743 | types); | |
252b5132 RH |
6744 | } |
6745 | ||
6746 | return 1; | |
6747 | } | |
6748 | ||
551c1ca1 | 6749 | static char * |
e3bb37b5 | 6750 | i386_scale (char *scale) |
252b5132 | 6751 | { |
551c1ca1 AM |
6752 | offsetT val; |
6753 | char *save = input_line_pointer; | |
252b5132 | 6754 | |
551c1ca1 AM |
6755 | input_line_pointer = scale; |
6756 | val = get_absolute_expression (); | |
6757 | ||
6758 | switch (val) | |
252b5132 | 6759 | { |
551c1ca1 | 6760 | case 1: |
252b5132 RH |
6761 | i.log2_scale_factor = 0; |
6762 | break; | |
551c1ca1 | 6763 | case 2: |
252b5132 RH |
6764 | i.log2_scale_factor = 1; |
6765 | break; | |
551c1ca1 | 6766 | case 4: |
252b5132 RH |
6767 | i.log2_scale_factor = 2; |
6768 | break; | |
551c1ca1 | 6769 | case 8: |
252b5132 RH |
6770 | i.log2_scale_factor = 3; |
6771 | break; | |
6772 | default: | |
a724f0f4 JB |
6773 | { |
6774 | char sep = *input_line_pointer; | |
6775 | ||
6776 | *input_line_pointer = '\0'; | |
6777 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
6778 | scale); | |
6779 | *input_line_pointer = sep; | |
6780 | input_line_pointer = save; | |
6781 | return NULL; | |
6782 | } | |
252b5132 | 6783 | } |
29b0f896 | 6784 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
6785 | { |
6786 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 6787 | 1 << i.log2_scale_factor); |
252b5132 | 6788 | i.log2_scale_factor = 0; |
252b5132 | 6789 | } |
551c1ca1 AM |
6790 | scale = input_line_pointer; |
6791 | input_line_pointer = save; | |
6792 | return scale; | |
252b5132 RH |
6793 | } |
6794 | ||
252b5132 | 6795 | static int |
e3bb37b5 | 6796 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 6797 | { |
29b0f896 | 6798 | expressionS *exp; |
252b5132 RH |
6799 | segT exp_seg = 0; |
6800 | char *save_input_line_pointer; | |
f3c180ae | 6801 | char *gotfree_input_line; |
40fb9820 L |
6802 | int override; |
6803 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 6804 | int ret; |
252b5132 | 6805 | |
31b2323c L |
6806 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
6807 | { | |
6808 | as_bad (_("at most %d displacement operands are allowed"), | |
6809 | MAX_MEMORY_OPERANDS); | |
6810 | return 0; | |
6811 | } | |
6812 | ||
0dfbf9d7 | 6813 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
6814 | if ((i.types[this_operand].bitfield.jumpabsolute) |
6815 | || (!current_templates->start->opcode_modifier.jump | |
6816 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 6817 | { |
40fb9820 | 6818 | bigdisp.bitfield.disp32 = 1; |
e05278af | 6819 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
6820 | if (flag_code == CODE_64BIT) |
6821 | { | |
6822 | if (!override) | |
6823 | { | |
6824 | bigdisp.bitfield.disp32s = 1; | |
6825 | bigdisp.bitfield.disp64 = 1; | |
6826 | } | |
6827 | } | |
6828 | else if ((flag_code == CODE_16BIT) ^ override) | |
6829 | { | |
6830 | bigdisp.bitfield.disp32 = 0; | |
6831 | bigdisp.bitfield.disp16 = 1; | |
6832 | } | |
e05278af JB |
6833 | } |
6834 | else | |
6835 | { | |
6836 | /* For PC-relative branches, the width of the displacement | |
6837 | is dependent upon data size, not address size. */ | |
e05278af | 6838 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
6839 | if (flag_code == CODE_64BIT) |
6840 | { | |
6841 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
6842 | bigdisp.bitfield.disp16 = 1; | |
6843 | else | |
6844 | { | |
6845 | bigdisp.bitfield.disp32 = 1; | |
6846 | bigdisp.bitfield.disp32s = 1; | |
6847 | } | |
6848 | } | |
6849 | else | |
e05278af JB |
6850 | { |
6851 | if (!override) | |
6852 | override = (i.suffix == (flag_code != CODE_16BIT | |
6853 | ? WORD_MNEM_SUFFIX | |
6854 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
6855 | bigdisp.bitfield.disp32 = 1; |
6856 | if ((flag_code == CODE_16BIT) ^ override) | |
6857 | { | |
6858 | bigdisp.bitfield.disp32 = 0; | |
6859 | bigdisp.bitfield.disp16 = 1; | |
6860 | } | |
e05278af | 6861 | } |
e05278af | 6862 | } |
c6fb90c8 L |
6863 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
6864 | bigdisp); | |
252b5132 RH |
6865 | |
6866 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 6867 | i.op[this_operand].disps = exp; |
252b5132 RH |
6868 | i.disp_operands++; |
6869 | save_input_line_pointer = input_line_pointer; | |
6870 | input_line_pointer = disp_start; | |
6871 | END_STRING_AND_SAVE (disp_end); | |
6872 | ||
6873 | #ifndef GCC_ASM_O_HACK | |
6874 | #define GCC_ASM_O_HACK 0 | |
6875 | #endif | |
6876 | #if GCC_ASM_O_HACK | |
6877 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 6878 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 6879 | && displacement_string_end[-1] == '+') |
252b5132 RH |
6880 | { |
6881 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
6882 | constraint within gcc asm statements. |
6883 | For instance: | |
6884 | ||
6885 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
6886 | __asm__ __volatile__ ( \ | |
6887 | "movw %w2,%0\n\t" \ | |
6888 | "movw %w1,2+%0\n\t" \ | |
6889 | "rorl $16,%1\n\t" \ | |
6890 | "movb %b1,4+%0\n\t" \ | |
6891 | "movb %4,5+%0\n\t" \ | |
6892 | "movb $0,6+%0\n\t" \ | |
6893 | "movb %h1,7+%0\n\t" \ | |
6894 | "rorl $16,%1" \ | |
6895 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
6896 | ||
6897 | This works great except that the output assembler ends | |
6898 | up looking a bit weird if it turns out that there is | |
6899 | no offset. You end up producing code that looks like: | |
6900 | ||
6901 | #APP | |
6902 | movw $235,(%eax) | |
6903 | movw %dx,2+(%eax) | |
6904 | rorl $16,%edx | |
6905 | movb %dl,4+(%eax) | |
6906 | movb $137,5+(%eax) | |
6907 | movb $0,6+(%eax) | |
6908 | movb %dh,7+(%eax) | |
6909 | rorl $16,%edx | |
6910 | #NO_APP | |
6911 | ||
47926f60 | 6912 | So here we provide the missing zero. */ |
24eab124 AM |
6913 | |
6914 | *displacement_string_end = '0'; | |
252b5132 RH |
6915 | } |
6916 | #endif | |
3956db08 | 6917 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6918 | if (gotfree_input_line) |
6919 | input_line_pointer = gotfree_input_line; | |
252b5132 | 6920 | |
24eab124 | 6921 | exp_seg = expression (exp); |
252b5132 | 6922 | |
636c26b0 AM |
6923 | SKIP_WHITESPACE (); |
6924 | if (*input_line_pointer) | |
6925 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
6926 | #if GCC_ASM_O_HACK | |
6927 | RESTORE_END_STRING (disp_end + 1); | |
6928 | #endif | |
636c26b0 | 6929 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 6930 | if (gotfree_input_line) |
ee86248c JB |
6931 | { |
6932 | free (gotfree_input_line); | |
6933 | ||
6934 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
6935 | exp->X_op = O_illegal; | |
6936 | } | |
6937 | ||
6938 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
6939 | ||
6940 | RESTORE_END_STRING (disp_end); | |
6941 | ||
6942 | return ret; | |
6943 | } | |
6944 | ||
6945 | static int | |
6946 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
6947 | i386_operand_type types, const char *disp_start) | |
6948 | { | |
6949 | i386_operand_type bigdisp; | |
6950 | int ret = 1; | |
636c26b0 | 6951 | |
24eab124 AM |
6952 | /* We do this to make sure that the section symbol is in |
6953 | the symbol table. We will ultimately change the relocation | |
47926f60 | 6954 | to be relative to the beginning of the section. */ |
1ae12ab7 | 6955 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
6956 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
6957 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 6958 | { |
636c26b0 | 6959 | if (exp->X_op != O_symbol) |
3992d3b7 | 6960 | goto inv_disp; |
636c26b0 | 6961 | |
e5cb08ac | 6962 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
6963 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
6964 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 6965 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
6966 | exp->X_op = O_subtract; |
6967 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 6968 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 6969 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
6970 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
6971 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 6972 | else |
29b0f896 | 6973 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 6974 | } |
252b5132 | 6975 | |
3992d3b7 AM |
6976 | else if (exp->X_op == O_absent |
6977 | || exp->X_op == O_illegal | |
ee86248c | 6978 | || exp->X_op == O_big) |
2daf4fd8 | 6979 | { |
3992d3b7 AM |
6980 | inv_disp: |
6981 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 6982 | disp_start); |
3992d3b7 | 6983 | ret = 0; |
2daf4fd8 AM |
6984 | } |
6985 | ||
0e1147d9 L |
6986 | else if (flag_code == CODE_64BIT |
6987 | && !i.prefix[ADDR_PREFIX] | |
6988 | && exp->X_op == O_constant) | |
6989 | { | |
6990 | /* Since displacement is signed extended to 64bit, don't allow | |
6991 | disp32 and turn off disp32s if they are out of range. */ | |
6992 | i.types[this_operand].bitfield.disp32 = 0; | |
6993 | if (!fits_in_signed_long (exp->X_add_number)) | |
6994 | { | |
6995 | i.types[this_operand].bitfield.disp32s = 0; | |
6996 | if (i.types[this_operand].bitfield.baseindex) | |
6997 | { | |
6998 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
6999 | (long) exp->X_add_number); | |
7000 | ret = 0; | |
7001 | } | |
7002 | } | |
7003 | } | |
7004 | ||
4c63da97 | 7005 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
7006 | else if (exp->X_op != O_constant |
7007 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
7008 | && exp_seg != absolute_section | |
7009 | && exp_seg != text_section | |
7010 | && exp_seg != data_section | |
7011 | && exp_seg != bss_section | |
7012 | && exp_seg != undefined_section | |
7013 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 7014 | { |
d0b47220 | 7015 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 7016 | ret = 0; |
24eab124 | 7017 | } |
252b5132 | 7018 | #endif |
3956db08 | 7019 | |
40fb9820 L |
7020 | /* Check if this is a displacement only operand. */ |
7021 | bigdisp = i.types[this_operand]; | |
7022 | bigdisp.bitfield.disp8 = 0; | |
7023 | bigdisp.bitfield.disp16 = 0; | |
7024 | bigdisp.bitfield.disp32 = 0; | |
7025 | bigdisp.bitfield.disp32s = 0; | |
7026 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 7027 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
7028 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
7029 | types); | |
3956db08 | 7030 | |
3992d3b7 | 7031 | return ret; |
252b5132 RH |
7032 | } |
7033 | ||
eecb386c | 7034 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
7035 | Return 1 on success, 0 on a failure. */ |
7036 | ||
252b5132 | 7037 | static int |
e3bb37b5 | 7038 | i386_index_check (const char *operand_string) |
252b5132 | 7039 | { |
3e73aa7c | 7040 | int ok; |
fc0763e6 | 7041 | const char *kind = "base/index"; |
24eab124 | 7042 | #if INFER_ADDR_PREFIX |
eecb386c AM |
7043 | int fudged = 0; |
7044 | ||
24eab124 AM |
7045 | tryprefix: |
7046 | #endif | |
3e73aa7c | 7047 | ok = 1; |
fc0763e6 JB |
7048 | if (current_templates->start->opcode_modifier.isstring |
7049 | && !current_templates->start->opcode_modifier.immext | |
7050 | && (current_templates->end[-1].opcode_modifier.isstring | |
7051 | || i.mem_operands)) | |
7052 | { | |
7053 | /* Memory operands of string insns are special in that they only allow | |
7054 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
7055 | unsigned int expected; | |
7056 | ||
7057 | kind = "string address"; | |
7058 | ||
7059 | if (current_templates->start->opcode_modifier.w) | |
7060 | { | |
7061 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
7062 | ||
7063 | if (!type.bitfield.baseindex | |
7064 | || ((!i.mem_operands != !intel_syntax) | |
7065 | && current_templates->end[-1].operand_types[1] | |
7066 | .bitfield.baseindex)) | |
7067 | type = current_templates->end[-1].operand_types[1]; | |
7068 | expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */; | |
7069 | } | |
7070 | else | |
7071 | expected = 3 /* rBX */; | |
7072 | ||
7073 | if (!i.base_reg || i.index_reg | |
7074 | || operand_type_check (i.types[this_operand], disp)) | |
7075 | ok = -1; | |
7076 | else if (!(flag_code == CODE_64BIT | |
7077 | ? i.prefix[ADDR_PREFIX] | |
7078 | ? i.base_reg->reg_type.bitfield.reg32 | |
7079 | : i.base_reg->reg_type.bitfield.reg64 | |
7080 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
7081 | ? i.base_reg->reg_type.bitfield.reg32 | |
7082 | : i.base_reg->reg_type.bitfield.reg16)) | |
7083 | ok = 0; | |
7084 | else if (i.base_reg->reg_num != expected) | |
7085 | ok = -1; | |
7086 | ||
7087 | if (ok < 0) | |
7088 | { | |
7089 | unsigned int j; | |
7090 | ||
7091 | for (j = 0; j < i386_regtab_size; ++j) | |
7092 | if ((flag_code == CODE_64BIT | |
7093 | ? i.prefix[ADDR_PREFIX] | |
7094 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
7095 | : i386_regtab[j].reg_type.bitfield.reg64 | |
7096 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
7097 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
7098 | : i386_regtab[j].reg_type.bitfield.reg16) | |
7099 | && i386_regtab[j].reg_num == expected) | |
7100 | break; | |
9c2799c2 | 7101 | gas_assert (j < i386_regtab_size); |
fc0763e6 JB |
7102 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
7103 | operand_string, | |
7104 | intel_syntax ? '[' : '(', | |
7105 | register_prefix, | |
7106 | i386_regtab[j].reg_name, | |
7107 | intel_syntax ? ']' : ')'); | |
7108 | ok = 1; | |
7109 | } | |
7110 | } | |
7111 | else if (flag_code == CODE_64BIT) | |
64e74474 | 7112 | { |
64e74474 | 7113 | if ((i.base_reg |
40fb9820 L |
7114 | && ((i.prefix[ADDR_PREFIX] == 0 |
7115 | && !i.base_reg->reg_type.bitfield.reg64) | |
7116 | || (i.prefix[ADDR_PREFIX] | |
7117 | && !i.base_reg->reg_type.bitfield.reg32)) | |
7118 | && (i.index_reg | |
9a04903e JB |
7119 | || i.base_reg->reg_num != |
7120 | (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) | |
64e74474 | 7121 | || (i.index_reg |
40fb9820 L |
7122 | && (!i.index_reg->reg_type.bitfield.baseindex |
7123 | || (i.prefix[ADDR_PREFIX] == 0 | |
db51cc60 L |
7124 | && i.index_reg->reg_num != RegRiz |
7125 | && !i.index_reg->reg_type.bitfield.reg64 | |
7126 | ) | |
40fb9820 | 7127 | || (i.prefix[ADDR_PREFIX] |
db51cc60 | 7128 | && i.index_reg->reg_num != RegEiz |
40fb9820 | 7129 | && !i.index_reg->reg_type.bitfield.reg32)))) |
64e74474 | 7130 | ok = 0; |
3e73aa7c JH |
7131 | } |
7132 | else | |
7133 | { | |
7134 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
7135 | { | |
7136 | /* 16bit checks. */ | |
7137 | if ((i.base_reg | |
40fb9820 L |
7138 | && (!i.base_reg->reg_type.bitfield.reg16 |
7139 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 7140 | || (i.index_reg |
40fb9820 L |
7141 | && (!i.index_reg->reg_type.bitfield.reg16 |
7142 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
7143 | || !(i.base_reg |
7144 | && i.base_reg->reg_num < 6 | |
7145 | && i.index_reg->reg_num >= 6 | |
7146 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
7147 | ok = 0; |
7148 | } | |
7149 | else | |
e5cb08ac | 7150 | { |
3e73aa7c JH |
7151 | /* 32bit checks. */ |
7152 | if ((i.base_reg | |
40fb9820 | 7153 | && !i.base_reg->reg_type.bitfield.reg32) |
3e73aa7c | 7154 | || (i.index_reg |
db51cc60 L |
7155 | && ((!i.index_reg->reg_type.bitfield.reg32 |
7156 | && i.index_reg->reg_num != RegEiz) | |
40fb9820 | 7157 | || !i.index_reg->reg_type.bitfield.baseindex))) |
e5cb08ac | 7158 | ok = 0; |
3e73aa7c JH |
7159 | } |
7160 | } | |
7161 | if (!ok) | |
24eab124 AM |
7162 | { |
7163 | #if INFER_ADDR_PREFIX | |
fc0763e6 | 7164 | if (!i.mem_operands && !i.prefix[ADDR_PREFIX]) |
24eab124 AM |
7165 | { |
7166 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
7167 | i.prefixes += 1; | |
b23bac36 AM |
7168 | /* Change the size of any displacement too. At most one of |
7169 | Disp16 or Disp32 is set. | |
7170 | FIXME. There doesn't seem to be any real need for separate | |
7171 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 7172 | Removing them would probably clean up the code quite a lot. */ |
4eed87de | 7173 | if (flag_code != CODE_64BIT |
40fb9820 L |
7174 | && (i.types[this_operand].bitfield.disp16 |
7175 | || i.types[this_operand].bitfield.disp32)) | |
7176 | i.types[this_operand] | |
c6fb90c8 | 7177 | = operand_type_xor (i.types[this_operand], disp16_32); |
eecb386c | 7178 | fudged = 1; |
24eab124 AM |
7179 | goto tryprefix; |
7180 | } | |
eecb386c | 7181 | if (fudged) |
fc0763e6 JB |
7182 | as_bad (_("`%s' is not a valid %s expression"), |
7183 | operand_string, | |
7184 | kind); | |
eecb386c | 7185 | else |
c388dee8 | 7186 | #endif |
fc0763e6 | 7187 | as_bad (_("`%s' is not a valid %s-bit %s expression"), |
eecb386c | 7188 | operand_string, |
fc0763e6 JB |
7189 | flag_code_names[i.prefix[ADDR_PREFIX] |
7190 | ? flag_code == CODE_32BIT | |
7191 | ? CODE_16BIT | |
7192 | : CODE_32BIT | |
7193 | : flag_code], | |
7194 | kind); | |
24eab124 | 7195 | } |
20f0a1fc | 7196 | return ok; |
24eab124 | 7197 | } |
252b5132 | 7198 | |
fc0763e6 | 7199 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 7200 | on error. */ |
252b5132 | 7201 | |
252b5132 | 7202 | static int |
a7619375 | 7203 | i386_att_operand (char *operand_string) |
252b5132 | 7204 | { |
af6bdddf AM |
7205 | const reg_entry *r; |
7206 | char *end_op; | |
24eab124 | 7207 | char *op_string = operand_string; |
252b5132 | 7208 | |
24eab124 | 7209 | if (is_space_char (*op_string)) |
252b5132 RH |
7210 | ++op_string; |
7211 | ||
24eab124 | 7212 | /* We check for an absolute prefix (differentiating, |
47926f60 | 7213 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
7214 | if (*op_string == ABSOLUTE_PREFIX) |
7215 | { | |
7216 | ++op_string; | |
7217 | if (is_space_char (*op_string)) | |
7218 | ++op_string; | |
40fb9820 | 7219 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 7220 | } |
252b5132 | 7221 | |
47926f60 | 7222 | /* Check if operand is a register. */ |
4d1bb795 | 7223 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 7224 | { |
40fb9820 L |
7225 | i386_operand_type temp; |
7226 | ||
24eab124 AM |
7227 | /* Check for a segment override by searching for ':' after a |
7228 | segment register. */ | |
7229 | op_string = end_op; | |
7230 | if (is_space_char (*op_string)) | |
7231 | ++op_string; | |
40fb9820 L |
7232 | if (*op_string == ':' |
7233 | && (r->reg_type.bitfield.sreg2 | |
7234 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
7235 | { |
7236 | switch (r->reg_num) | |
7237 | { | |
7238 | case 0: | |
7239 | i.seg[i.mem_operands] = &es; | |
7240 | break; | |
7241 | case 1: | |
7242 | i.seg[i.mem_operands] = &cs; | |
7243 | break; | |
7244 | case 2: | |
7245 | i.seg[i.mem_operands] = &ss; | |
7246 | break; | |
7247 | case 3: | |
7248 | i.seg[i.mem_operands] = &ds; | |
7249 | break; | |
7250 | case 4: | |
7251 | i.seg[i.mem_operands] = &fs; | |
7252 | break; | |
7253 | case 5: | |
7254 | i.seg[i.mem_operands] = &gs; | |
7255 | break; | |
7256 | } | |
252b5132 | 7257 | |
24eab124 | 7258 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
7259 | ++op_string; |
7260 | if (is_space_char (*op_string)) | |
24eab124 | 7261 | ++op_string; |
252b5132 | 7262 | |
24eab124 AM |
7263 | if (!is_digit_char (*op_string) |
7264 | && !is_identifier_char (*op_string) | |
7265 | && *op_string != '(' | |
7266 | && *op_string != ABSOLUTE_PREFIX) | |
7267 | { | |
7268 | as_bad (_("bad memory operand `%s'"), op_string); | |
7269 | return 0; | |
7270 | } | |
47926f60 | 7271 | /* Handle case of %es:*foo. */ |
24eab124 AM |
7272 | if (*op_string == ABSOLUTE_PREFIX) |
7273 | { | |
7274 | ++op_string; | |
7275 | if (is_space_char (*op_string)) | |
7276 | ++op_string; | |
40fb9820 | 7277 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
7278 | } |
7279 | goto do_memory_reference; | |
7280 | } | |
7281 | if (*op_string) | |
7282 | { | |
d0b47220 | 7283 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
7284 | return 0; |
7285 | } | |
40fb9820 L |
7286 | temp = r->reg_type; |
7287 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
7288 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
7289 | temp); | |
7d5e4556 | 7290 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 7291 | i.op[this_operand].regs = r; |
24eab124 AM |
7292 | i.reg_operands++; |
7293 | } | |
af6bdddf AM |
7294 | else if (*op_string == REGISTER_PREFIX) |
7295 | { | |
7296 | as_bad (_("bad register name `%s'"), op_string); | |
7297 | return 0; | |
7298 | } | |
24eab124 | 7299 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 7300 | { |
24eab124 | 7301 | ++op_string; |
40fb9820 | 7302 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 7303 | { |
d0b47220 | 7304 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
7305 | return 0; |
7306 | } | |
7307 | if (!i386_immediate (op_string)) | |
7308 | return 0; | |
7309 | } | |
7310 | else if (is_digit_char (*op_string) | |
7311 | || is_identifier_char (*op_string) | |
e5cb08ac | 7312 | || *op_string == '(') |
24eab124 | 7313 | { |
47926f60 | 7314 | /* This is a memory reference of some sort. */ |
af6bdddf | 7315 | char *base_string; |
252b5132 | 7316 | |
47926f60 | 7317 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
7318 | char *displacement_string_start; |
7319 | char *displacement_string_end; | |
252b5132 | 7320 | |
24eab124 | 7321 | do_memory_reference: |
24eab124 | 7322 | if ((i.mem_operands == 1 |
40fb9820 | 7323 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
7324 | || i.mem_operands == 2) |
7325 | { | |
7326 | as_bad (_("too many memory references for `%s'"), | |
7327 | current_templates->start->name); | |
7328 | return 0; | |
7329 | } | |
252b5132 | 7330 | |
24eab124 AM |
7331 | /* Check for base index form. We detect the base index form by |
7332 | looking for an ')' at the end of the operand, searching | |
7333 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
7334 | after the '('. */ | |
af6bdddf | 7335 | base_string = op_string + strlen (op_string); |
c3332e24 | 7336 | |
af6bdddf AM |
7337 | --base_string; |
7338 | if (is_space_char (*base_string)) | |
7339 | --base_string; | |
252b5132 | 7340 | |
47926f60 | 7341 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
7342 | displacement_string_start = op_string; |
7343 | displacement_string_end = base_string + 1; | |
252b5132 | 7344 | |
24eab124 AM |
7345 | if (*base_string == ')') |
7346 | { | |
af6bdddf | 7347 | char *temp_string; |
24eab124 AM |
7348 | unsigned int parens_balanced = 1; |
7349 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 7350 | equal, so this loop will not be infinite. */ |
24eab124 AM |
7351 | do |
7352 | { | |
7353 | base_string--; | |
7354 | if (*base_string == ')') | |
7355 | parens_balanced++; | |
7356 | if (*base_string == '(') | |
7357 | parens_balanced--; | |
7358 | } | |
7359 | while (parens_balanced); | |
c3332e24 | 7360 | |
af6bdddf | 7361 | temp_string = base_string; |
c3332e24 | 7362 | |
24eab124 | 7363 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
7364 | ++base_string; |
7365 | if (is_space_char (*base_string)) | |
24eab124 | 7366 | ++base_string; |
252b5132 | 7367 | |
af6bdddf | 7368 | if (*base_string == ',' |
4eed87de AM |
7369 | || ((i.base_reg = parse_register (base_string, &end_op)) |
7370 | != NULL)) | |
252b5132 | 7371 | { |
af6bdddf | 7372 | displacement_string_end = temp_string; |
252b5132 | 7373 | |
40fb9820 | 7374 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 7375 | |
af6bdddf | 7376 | if (i.base_reg) |
24eab124 | 7377 | { |
24eab124 AM |
7378 | base_string = end_op; |
7379 | if (is_space_char (*base_string)) | |
7380 | ++base_string; | |
af6bdddf AM |
7381 | } |
7382 | ||
7383 | /* There may be an index reg or scale factor here. */ | |
7384 | if (*base_string == ',') | |
7385 | { | |
7386 | ++base_string; | |
7387 | if (is_space_char (*base_string)) | |
7388 | ++base_string; | |
7389 | ||
4eed87de AM |
7390 | if ((i.index_reg = parse_register (base_string, &end_op)) |
7391 | != NULL) | |
24eab124 | 7392 | { |
af6bdddf | 7393 | base_string = end_op; |
24eab124 AM |
7394 | if (is_space_char (*base_string)) |
7395 | ++base_string; | |
af6bdddf AM |
7396 | if (*base_string == ',') |
7397 | { | |
7398 | ++base_string; | |
7399 | if (is_space_char (*base_string)) | |
7400 | ++base_string; | |
7401 | } | |
e5cb08ac | 7402 | else if (*base_string != ')') |
af6bdddf | 7403 | { |
4eed87de AM |
7404 | as_bad (_("expecting `,' or `)' " |
7405 | "after index register in `%s'"), | |
af6bdddf AM |
7406 | operand_string); |
7407 | return 0; | |
7408 | } | |
24eab124 | 7409 | } |
af6bdddf | 7410 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 7411 | { |
af6bdddf | 7412 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
7413 | return 0; |
7414 | } | |
252b5132 | 7415 | |
47926f60 | 7416 | /* Check for scale factor. */ |
551c1ca1 | 7417 | if (*base_string != ')') |
af6bdddf | 7418 | { |
551c1ca1 AM |
7419 | char *end_scale = i386_scale (base_string); |
7420 | ||
7421 | if (!end_scale) | |
af6bdddf | 7422 | return 0; |
24eab124 | 7423 | |
551c1ca1 | 7424 | base_string = end_scale; |
af6bdddf AM |
7425 | if (is_space_char (*base_string)) |
7426 | ++base_string; | |
7427 | if (*base_string != ')') | |
7428 | { | |
4eed87de AM |
7429 | as_bad (_("expecting `)' " |
7430 | "after scale factor in `%s'"), | |
af6bdddf AM |
7431 | operand_string); |
7432 | return 0; | |
7433 | } | |
7434 | } | |
7435 | else if (!i.index_reg) | |
24eab124 | 7436 | { |
4eed87de AM |
7437 | as_bad (_("expecting index register or scale factor " |
7438 | "after `,'; got '%c'"), | |
af6bdddf | 7439 | *base_string); |
24eab124 AM |
7440 | return 0; |
7441 | } | |
7442 | } | |
af6bdddf | 7443 | else if (*base_string != ')') |
24eab124 | 7444 | { |
4eed87de AM |
7445 | as_bad (_("expecting `,' or `)' " |
7446 | "after base register in `%s'"), | |
af6bdddf | 7447 | operand_string); |
24eab124 AM |
7448 | return 0; |
7449 | } | |
c3332e24 | 7450 | } |
af6bdddf | 7451 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 7452 | { |
af6bdddf | 7453 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 7454 | return 0; |
c3332e24 | 7455 | } |
24eab124 AM |
7456 | } |
7457 | ||
7458 | /* If there's an expression beginning the operand, parse it, | |
7459 | assuming displacement_string_start and | |
7460 | displacement_string_end are meaningful. */ | |
7461 | if (displacement_string_start != displacement_string_end) | |
7462 | { | |
7463 | if (!i386_displacement (displacement_string_start, | |
7464 | displacement_string_end)) | |
7465 | return 0; | |
7466 | } | |
7467 | ||
7468 | /* Special case for (%dx) while doing input/output op. */ | |
7469 | if (i.base_reg | |
0dfbf9d7 L |
7470 | && operand_type_equal (&i.base_reg->reg_type, |
7471 | ®16_inoutportreg) | |
24eab124 AM |
7472 | && i.index_reg == 0 |
7473 | && i.log2_scale_factor == 0 | |
7474 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 7475 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 7476 | { |
65da13b5 | 7477 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
7478 | return 1; |
7479 | } | |
7480 | ||
eecb386c AM |
7481 | if (i386_index_check (operand_string) == 0) |
7482 | return 0; | |
5c07affc | 7483 | i.types[this_operand].bitfield.mem = 1; |
24eab124 AM |
7484 | i.mem_operands++; |
7485 | } | |
7486 | else | |
ce8a8b2f AM |
7487 | { |
7488 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
7489 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
7490 | output_invalid (*op_string), | |
7491 | this_operand + 1, | |
7492 | op_string); | |
7493 | return 0; | |
7494 | } | |
47926f60 | 7495 | return 1; /* Normal return. */ |
252b5132 RH |
7496 | } |
7497 | \f | |
ee7fcc42 AM |
7498 | /* md_estimate_size_before_relax() |
7499 | ||
7500 | Called just before relax() for rs_machine_dependent frags. The x86 | |
7501 | assembler uses these frags to handle variable size jump | |
7502 | instructions. | |
7503 | ||
7504 | Any symbol that is now undefined will not become defined. | |
7505 | Return the correct fr_subtype in the frag. | |
7506 | Return the initial "guess for variable size of frag" to caller. | |
7507 | The guess is actually the growth beyond the fixed part. Whatever | |
7508 | we do to grow the fixed or variable part contributes to our | |
7509 | returned value. */ | |
7510 | ||
252b5132 RH |
7511 | int |
7512 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
7513 | fragS *fragP; |
7514 | segT segment; | |
252b5132 | 7515 | { |
252b5132 | 7516 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
7517 | check for un-relaxable symbols. On an ELF system, we can't relax |
7518 | an externally visible symbol, because it may be overridden by a | |
7519 | shared library. */ | |
7520 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 7521 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7522 | || (IS_ELF |
31312f95 | 7523 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
915bcca5 L |
7524 | || S_IS_WEAK (fragP->fr_symbol) |
7525 | || ((symbol_get_bfdsym (fragP->fr_symbol)->flags | |
7526 | & BSF_GNU_INDIRECT_FUNCTION)))) | |
fbeb56a4 DK |
7527 | #endif |
7528 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 7529 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 7530 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
7531 | #endif |
7532 | ) | |
252b5132 | 7533 | { |
b98ef147 AM |
7534 | /* Symbol is undefined in this segment, or we need to keep a |
7535 | reloc so that weak symbols can be overridden. */ | |
7536 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 7537 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
7538 | unsigned char *opcode; |
7539 | int old_fr_fix; | |
f6af82bd | 7540 | |
ee7fcc42 | 7541 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 7542 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 7543 | else if (size == 2) |
f6af82bd AM |
7544 | reloc_type = BFD_RELOC_16_PCREL; |
7545 | else | |
7546 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 7547 | |
ee7fcc42 AM |
7548 | old_fr_fix = fragP->fr_fix; |
7549 | opcode = (unsigned char *) fragP->fr_opcode; | |
7550 | ||
fddf5b5b | 7551 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 7552 | { |
fddf5b5b AM |
7553 | case UNCOND_JUMP: |
7554 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 7555 | opcode[0] = 0xe9; |
252b5132 | 7556 | fragP->fr_fix += size; |
062cd5e7 AS |
7557 | fix_new (fragP, old_fr_fix, size, |
7558 | fragP->fr_symbol, | |
7559 | fragP->fr_offset, 1, | |
7560 | reloc_type); | |
252b5132 RH |
7561 | break; |
7562 | ||
fddf5b5b | 7563 | case COND_JUMP86: |
412167cb AM |
7564 | if (size == 2 |
7565 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
7566 | { |
7567 | /* Negate the condition, and branch past an | |
7568 | unconditional jump. */ | |
7569 | opcode[0] ^= 1; | |
7570 | opcode[1] = 3; | |
7571 | /* Insert an unconditional jump. */ | |
7572 | opcode[2] = 0xe9; | |
7573 | /* We added two extra opcode bytes, and have a two byte | |
7574 | offset. */ | |
7575 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
7576 | fix_new (fragP, old_fr_fix + 2, 2, |
7577 | fragP->fr_symbol, | |
7578 | fragP->fr_offset, 1, | |
7579 | reloc_type); | |
fddf5b5b AM |
7580 | break; |
7581 | } | |
7582 | /* Fall through. */ | |
7583 | ||
7584 | case COND_JUMP: | |
412167cb AM |
7585 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
7586 | { | |
3e02c1cc AM |
7587 | fixS *fixP; |
7588 | ||
412167cb | 7589 | fragP->fr_fix += 1; |
3e02c1cc AM |
7590 | fixP = fix_new (fragP, old_fr_fix, 1, |
7591 | fragP->fr_symbol, | |
7592 | fragP->fr_offset, 1, | |
7593 | BFD_RELOC_8_PCREL); | |
7594 | fixP->fx_signed = 1; | |
412167cb AM |
7595 | break; |
7596 | } | |
93c2a809 | 7597 | |
24eab124 | 7598 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 7599 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 7600 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 7601 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
7602 | /* We've added an opcode byte. */ |
7603 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
7604 | fix_new (fragP, old_fr_fix + 1, size, |
7605 | fragP->fr_symbol, | |
7606 | fragP->fr_offset, 1, | |
7607 | reloc_type); | |
252b5132 | 7608 | break; |
fddf5b5b AM |
7609 | |
7610 | default: | |
7611 | BAD_CASE (fragP->fr_subtype); | |
7612 | break; | |
252b5132 RH |
7613 | } |
7614 | frag_wane (fragP); | |
ee7fcc42 | 7615 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 7616 | } |
93c2a809 | 7617 | |
93c2a809 AM |
7618 | /* Guess size depending on current relax state. Initially the relax |
7619 | state will correspond to a short jump and we return 1, because | |
7620 | the variable part of the frag (the branch offset) is one byte | |
7621 | long. However, we can relax a section more than once and in that | |
7622 | case we must either set fr_subtype back to the unrelaxed state, | |
7623 | or return the value for the appropriate branch. */ | |
7624 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
7625 | } |
7626 | ||
47926f60 KH |
7627 | /* Called after relax() is finished. |
7628 | ||
7629 | In: Address of frag. | |
7630 | fr_type == rs_machine_dependent. | |
7631 | fr_subtype is what the address relaxed to. | |
7632 | ||
7633 | Out: Any fixSs and constants are set up. | |
7634 | Caller will turn frag into a ".space 0". */ | |
7635 | ||
252b5132 RH |
7636 | void |
7637 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
7638 | bfd *abfd ATTRIBUTE_UNUSED; |
7639 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 7640 | fragS *fragP; |
252b5132 | 7641 | { |
29b0f896 | 7642 | unsigned char *opcode; |
252b5132 | 7643 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
7644 | offsetT target_address; |
7645 | offsetT opcode_address; | |
252b5132 | 7646 | unsigned int extension = 0; |
847f7ad4 | 7647 | offsetT displacement_from_opcode_start; |
252b5132 RH |
7648 | |
7649 | opcode = (unsigned char *) fragP->fr_opcode; | |
7650 | ||
47926f60 | 7651 | /* Address we want to reach in file space. */ |
252b5132 | 7652 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 7653 | |
47926f60 | 7654 | /* Address opcode resides at in file space. */ |
252b5132 RH |
7655 | opcode_address = fragP->fr_address + fragP->fr_fix; |
7656 | ||
47926f60 | 7657 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
7658 | displacement_from_opcode_start = target_address - opcode_address; |
7659 | ||
fddf5b5b | 7660 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 7661 | { |
47926f60 KH |
7662 | /* Don't have to change opcode. */ |
7663 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 7664 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
7665 | } |
7666 | else | |
7667 | { | |
7668 | if (no_cond_jump_promotion | |
7669 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
7670 | as_warn_where (fragP->fr_file, fragP->fr_line, |
7671 | _("long jump required")); | |
252b5132 | 7672 | |
fddf5b5b AM |
7673 | switch (fragP->fr_subtype) |
7674 | { | |
7675 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
7676 | extension = 4; /* 1 opcode + 4 displacement */ | |
7677 | opcode[0] = 0xe9; | |
7678 | where_to_put_displacement = &opcode[1]; | |
7679 | break; | |
252b5132 | 7680 | |
fddf5b5b AM |
7681 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
7682 | extension = 2; /* 1 opcode + 2 displacement */ | |
7683 | opcode[0] = 0xe9; | |
7684 | where_to_put_displacement = &opcode[1]; | |
7685 | break; | |
252b5132 | 7686 | |
fddf5b5b AM |
7687 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
7688 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
7689 | extension = 5; /* 2 opcode + 4 displacement */ | |
7690 | opcode[1] = opcode[0] + 0x10; | |
7691 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
7692 | where_to_put_displacement = &opcode[2]; | |
7693 | break; | |
252b5132 | 7694 | |
fddf5b5b AM |
7695 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
7696 | extension = 3; /* 2 opcode + 2 displacement */ | |
7697 | opcode[1] = opcode[0] + 0x10; | |
7698 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
7699 | where_to_put_displacement = &opcode[2]; | |
7700 | break; | |
252b5132 | 7701 | |
fddf5b5b AM |
7702 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
7703 | extension = 4; | |
7704 | opcode[0] ^= 1; | |
7705 | opcode[1] = 3; | |
7706 | opcode[2] = 0xe9; | |
7707 | where_to_put_displacement = &opcode[3]; | |
7708 | break; | |
7709 | ||
7710 | default: | |
7711 | BAD_CASE (fragP->fr_subtype); | |
7712 | break; | |
7713 | } | |
252b5132 | 7714 | } |
fddf5b5b | 7715 | |
7b81dfbb AJ |
7716 | /* If size if less then four we are sure that the operand fits, |
7717 | but if it's 4, then it could be that the displacement is larger | |
7718 | then -/+ 2GB. */ | |
7719 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
7720 | && object_64bit | |
7721 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
7722 | + ((addressT) 1 << 31)) |
7723 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
7724 | { |
7725 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
7726 | _("jump target out of range")); | |
7727 | /* Make us emit 0. */ | |
7728 | displacement_from_opcode_start = extension; | |
7729 | } | |
47926f60 | 7730 | /* Now put displacement after opcode. */ |
252b5132 RH |
7731 | md_number_to_chars ((char *) where_to_put_displacement, |
7732 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 7733 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
7734 | fragP->fr_fix += extension; |
7735 | } | |
7736 | \f | |
252b5132 RH |
7737 | /* Apply a fixup (fixS) to segment data, once it has been determined |
7738 | by our caller that we have all the info we need to fix it up. | |
7739 | ||
7740 | On the 386, immediates, displacements, and data pointers are all in | |
7741 | the same (little-endian) format, so we don't need to care about which | |
7742 | we are handling. */ | |
7743 | ||
94f592af | 7744 | void |
55cf6793 | 7745 | md_apply_fix (fixP, valP, seg) |
47926f60 KH |
7746 | /* The fix we're to put in. */ |
7747 | fixS *fixP; | |
47926f60 | 7748 | /* Pointer to the value of the bits. */ |
c6682705 | 7749 | valueT *valP; |
47926f60 KH |
7750 | /* Segment fix is from. */ |
7751 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 7752 | { |
94f592af | 7753 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 7754 | valueT value = *valP; |
252b5132 | 7755 | |
f86103b7 | 7756 | #if !defined (TE_Mach) |
93382f6d AM |
7757 | if (fixP->fx_pcrel) |
7758 | { | |
7759 | switch (fixP->fx_r_type) | |
7760 | { | |
5865bb77 ILT |
7761 | default: |
7762 | break; | |
7763 | ||
d6ab8113 JB |
7764 | case BFD_RELOC_64: |
7765 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
7766 | break; | |
93382f6d | 7767 | case BFD_RELOC_32: |
ae8887b5 | 7768 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
7769 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
7770 | break; | |
7771 | case BFD_RELOC_16: | |
7772 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
7773 | break; | |
7774 | case BFD_RELOC_8: | |
7775 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
7776 | break; | |
7777 | } | |
7778 | } | |
252b5132 | 7779 | |
a161fe53 | 7780 | if (fixP->fx_addsy != NULL |
31312f95 | 7781 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 7782 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 AM |
7783 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
7784 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
7785 | && !use_rela_relocations) | |
252b5132 | 7786 | { |
31312f95 AM |
7787 | /* This is a hack. There should be a better way to handle this. |
7788 | This covers for the fact that bfd_install_relocation will | |
7789 | subtract the current location (for partial_inplace, PC relative | |
7790 | relocations); see more below. */ | |
252b5132 | 7791 | #ifndef OBJ_AOUT |
718ddfc0 | 7792 | if (IS_ELF |
252b5132 RH |
7793 | #ifdef TE_PE |
7794 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
7795 | #endif | |
7796 | ) | |
7797 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
7798 | #endif | |
7799 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 7800 | if (IS_ELF) |
252b5132 | 7801 | { |
6539b54b | 7802 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 7803 | |
6539b54b | 7804 | if ((sym_seg == seg |
2f66722d | 7805 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 7806 | && sym_seg != absolute_section)) |
af65af87 | 7807 | && !generic_force_reloc (fixP)) |
2f66722d AM |
7808 | { |
7809 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
7810 | bfd_install_relocation subtracts them out again. I think |
7811 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
7812 | it. FIXME. */ |
7813 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
7814 | } | |
252b5132 RH |
7815 | } |
7816 | #endif | |
7817 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
7818 | /* For some reason, the PE format does not store a |
7819 | section address offset for a PC relative symbol. */ | |
7820 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 7821 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
7822 | value += md_pcrel_from (fixP); |
7823 | #endif | |
7824 | } | |
fbeb56a4 DK |
7825 | #if defined (OBJ_COFF) && defined (TE_PE) |
7826 | if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
7827 | { | |
7828 | value -= S_GET_VALUE (fixP->fx_addsy); | |
7829 | } | |
7830 | #endif | |
252b5132 RH |
7831 | |
7832 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 7833 | and we must not disappoint it. */ |
252b5132 | 7834 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7835 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
7836 | switch (fixP->fx_r_type) |
7837 | { | |
7838 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 7839 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
7840 | /* Make the jump instruction point to the address of the operand. At |
7841 | runtime we merely add the offset to the actual PLT entry. */ | |
7842 | value = -4; | |
7843 | break; | |
31312f95 | 7844 | |
13ae64f3 JJ |
7845 | case BFD_RELOC_386_TLS_GD: |
7846 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 7847 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
7848 | case BFD_RELOC_386_TLS_IE: |
7849 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 7850 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
7851 | case BFD_RELOC_X86_64_TLSGD: |
7852 | case BFD_RELOC_X86_64_TLSLD: | |
7853 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 7854 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
7855 | value = 0; /* Fully resolved at runtime. No addend. */ |
7856 | /* Fallthrough */ | |
7857 | case BFD_RELOC_386_TLS_LE: | |
7858 | case BFD_RELOC_386_TLS_LDO_32: | |
7859 | case BFD_RELOC_386_TLS_LE_32: | |
7860 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 7861 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 7862 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 7863 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
7864 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
7865 | break; | |
7866 | ||
67a4f2b7 AO |
7867 | case BFD_RELOC_386_TLS_DESC_CALL: |
7868 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
7869 | value = 0; /* Fully resolved at runtime. No addend. */ | |
7870 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7871 | fixP->fx_done = 0; | |
7872 | return; | |
7873 | ||
00f7efb6 JJ |
7874 | case BFD_RELOC_386_GOT32: |
7875 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
7876 | value = 0; /* Fully resolved at runtime. No addend. */ |
7877 | break; | |
47926f60 KH |
7878 | |
7879 | case BFD_RELOC_VTABLE_INHERIT: | |
7880 | case BFD_RELOC_VTABLE_ENTRY: | |
7881 | fixP->fx_done = 0; | |
94f592af | 7882 | return; |
47926f60 KH |
7883 | |
7884 | default: | |
7885 | break; | |
7886 | } | |
7887 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 7888 | *valP = value; |
f86103b7 | 7889 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 7890 | |
3e73aa7c | 7891 | /* Are we finished with this relocation now? */ |
c6682705 | 7892 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 7893 | fixP->fx_done = 1; |
fbeb56a4 DK |
7894 | #if defined (OBJ_COFF) && defined (TE_PE) |
7895 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
7896 | { | |
7897 | fixP->fx_done = 0; | |
7898 | /* Remember value for tc_gen_reloc. */ | |
7899 | fixP->fx_addnumber = value; | |
7900 | /* Clear out the frag for now. */ | |
7901 | value = 0; | |
7902 | } | |
7903 | #endif | |
3e73aa7c JH |
7904 | else if (use_rela_relocations) |
7905 | { | |
7906 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
7907 | /* Remember value for tc_gen_reloc. */ |
7908 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
7909 | value = 0; |
7910 | } | |
f86103b7 | 7911 | |
94f592af | 7912 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 7913 | } |
252b5132 | 7914 | \f |
252b5132 | 7915 | char * |
499ac353 | 7916 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 7917 | { |
499ac353 NC |
7918 | /* This outputs the LITTLENUMs in REVERSE order; |
7919 | in accord with the bigendian 386. */ | |
7920 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
7921 | } |
7922 | \f | |
2d545b82 | 7923 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 7924 | |
252b5132 | 7925 | static char * |
e3bb37b5 | 7926 | output_invalid (int c) |
252b5132 | 7927 | { |
3882b010 | 7928 | if (ISPRINT (c)) |
f9f21a03 L |
7929 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
7930 | "'%c'", c); | |
252b5132 | 7931 | else |
f9f21a03 | 7932 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 7933 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
7934 | return output_invalid_buf; |
7935 | } | |
7936 | ||
af6bdddf | 7937 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
7938 | |
7939 | static const reg_entry * | |
4d1bb795 | 7940 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 7941 | { |
af6bdddf AM |
7942 | char *s = reg_string; |
7943 | char *p; | |
252b5132 RH |
7944 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
7945 | const reg_entry *r; | |
7946 | ||
7947 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
7948 | if (*s == REGISTER_PREFIX) | |
7949 | ++s; | |
7950 | ||
7951 | if (is_space_char (*s)) | |
7952 | ++s; | |
7953 | ||
7954 | p = reg_name_given; | |
af6bdddf | 7955 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
7956 | { |
7957 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
7958 | return (const reg_entry *) NULL; |
7959 | s++; | |
252b5132 RH |
7960 | } |
7961 | ||
6588847e DN |
7962 | /* For naked regs, make sure that we are not dealing with an identifier. |
7963 | This prevents confusing an identifier like `eax_var' with register | |
7964 | `eax'. */ | |
7965 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
7966 | return (const reg_entry *) NULL; | |
7967 | ||
af6bdddf | 7968 | *end_op = s; |
252b5132 RH |
7969 | |
7970 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
7971 | ||
5f47d35b | 7972 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 7973 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 7974 | { |
5f47d35b AM |
7975 | if (is_space_char (*s)) |
7976 | ++s; | |
7977 | if (*s == '(') | |
7978 | { | |
af6bdddf | 7979 | ++s; |
5f47d35b AM |
7980 | if (is_space_char (*s)) |
7981 | ++s; | |
7982 | if (*s >= '0' && *s <= '7') | |
7983 | { | |
db557034 | 7984 | int fpr = *s - '0'; |
af6bdddf | 7985 | ++s; |
5f47d35b AM |
7986 | if (is_space_char (*s)) |
7987 | ++s; | |
7988 | if (*s == ')') | |
7989 | { | |
7990 | *end_op = s + 1; | |
1e9cc1c2 | 7991 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
7992 | know (r); |
7993 | return r + fpr; | |
5f47d35b | 7994 | } |
5f47d35b | 7995 | } |
47926f60 | 7996 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
7997 | return (const reg_entry *) NULL; |
7998 | } | |
7999 | } | |
8000 | ||
a60de03c JB |
8001 | if (r == NULL || allow_pseudo_reg) |
8002 | return r; | |
8003 | ||
0dfbf9d7 | 8004 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
8005 | return (const reg_entry *) NULL; |
8006 | ||
192dc9c6 JB |
8007 | if ((r->reg_type.bitfield.reg32 |
8008 | || r->reg_type.bitfield.sreg3 | |
8009 | || r->reg_type.bitfield.control | |
8010 | || r->reg_type.bitfield.debug | |
8011 | || r->reg_type.bitfield.test) | |
8012 | && !cpu_arch_flags.bitfield.cpui386) | |
8013 | return (const reg_entry *) NULL; | |
8014 | ||
309d3373 JB |
8015 | if (r->reg_type.bitfield.floatreg |
8016 | && !cpu_arch_flags.bitfield.cpu8087 | |
8017 | && !cpu_arch_flags.bitfield.cpu287 | |
8018 | && !cpu_arch_flags.bitfield.cpu387) | |
8019 | return (const reg_entry *) NULL; | |
8020 | ||
192dc9c6 JB |
8021 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
8022 | return (const reg_entry *) NULL; | |
8023 | ||
8024 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) | |
8025 | return (const reg_entry *) NULL; | |
8026 | ||
40f12533 L |
8027 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) |
8028 | return (const reg_entry *) NULL; | |
8029 | ||
db51cc60 | 8030 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 8031 | if (!allow_index_reg |
db51cc60 L |
8032 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
8033 | return (const reg_entry *) NULL; | |
8034 | ||
a60de03c JB |
8035 | if (((r->reg_flags & (RegRex64 | RegRex)) |
8036 | || r->reg_type.bitfield.reg64) | |
40fb9820 | 8037 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 8038 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 8039 | && flag_code != CODE_64BIT) |
20f0a1fc | 8040 | return (const reg_entry *) NULL; |
1ae00879 | 8041 | |
b7240065 JB |
8042 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
8043 | return (const reg_entry *) NULL; | |
8044 | ||
252b5132 RH |
8045 | return r; |
8046 | } | |
4d1bb795 JB |
8047 | |
8048 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
8049 | ||
8050 | static const reg_entry * | |
8051 | parse_register (char *reg_string, char **end_op) | |
8052 | { | |
8053 | const reg_entry *r; | |
8054 | ||
8055 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
8056 | r = parse_real_register (reg_string, end_op); | |
8057 | else | |
8058 | r = NULL; | |
8059 | if (!r) | |
8060 | { | |
8061 | char *save = input_line_pointer; | |
8062 | char c; | |
8063 | symbolS *symbolP; | |
8064 | ||
8065 | input_line_pointer = reg_string; | |
8066 | c = get_symbol_end (); | |
8067 | symbolP = symbol_find (reg_string); | |
8068 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
8069 | { | |
8070 | const expressionS *e = symbol_get_value_expression (symbolP); | |
8071 | ||
0398aac5 | 8072 | know (e->X_op == O_register); |
4eed87de | 8073 | know (e->X_add_number >= 0 |
c3fe08fa | 8074 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 JB |
8075 | r = i386_regtab + e->X_add_number; |
8076 | *end_op = input_line_pointer; | |
8077 | } | |
8078 | *input_line_pointer = c; | |
8079 | input_line_pointer = save; | |
8080 | } | |
8081 | return r; | |
8082 | } | |
8083 | ||
8084 | int | |
8085 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
8086 | { | |
8087 | const reg_entry *r; | |
8088 | char *end = input_line_pointer; | |
8089 | ||
8090 | *end = *nextcharP; | |
8091 | r = parse_register (name, &input_line_pointer); | |
8092 | if (r && end <= input_line_pointer) | |
8093 | { | |
8094 | *nextcharP = *input_line_pointer; | |
8095 | *input_line_pointer = 0; | |
8096 | e->X_op = O_register; | |
8097 | e->X_add_number = r - i386_regtab; | |
8098 | return 1; | |
8099 | } | |
8100 | input_line_pointer = end; | |
8101 | *end = 0; | |
ee86248c | 8102 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
8103 | } |
8104 | ||
8105 | void | |
8106 | md_operand (expressionS *e) | |
8107 | { | |
ee86248c JB |
8108 | char *end; |
8109 | const reg_entry *r; | |
4d1bb795 | 8110 | |
ee86248c JB |
8111 | switch (*input_line_pointer) |
8112 | { | |
8113 | case REGISTER_PREFIX: | |
8114 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
8115 | if (r) |
8116 | { | |
8117 | e->X_op = O_register; | |
8118 | e->X_add_number = r - i386_regtab; | |
8119 | input_line_pointer = end; | |
8120 | } | |
ee86248c JB |
8121 | break; |
8122 | ||
8123 | case '[': | |
9c2799c2 | 8124 | gas_assert (intel_syntax); |
ee86248c JB |
8125 | end = input_line_pointer++; |
8126 | expression (e); | |
8127 | if (*input_line_pointer == ']') | |
8128 | { | |
8129 | ++input_line_pointer; | |
8130 | e->X_op_symbol = make_expr_symbol (e); | |
8131 | e->X_add_symbol = NULL; | |
8132 | e->X_add_number = 0; | |
8133 | e->X_op = O_index; | |
8134 | } | |
8135 | else | |
8136 | { | |
8137 | e->X_op = O_absent; | |
8138 | input_line_pointer = end; | |
8139 | } | |
8140 | break; | |
4d1bb795 JB |
8141 | } |
8142 | } | |
8143 | ||
252b5132 | 8144 | \f |
4cc782b5 | 8145 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 8146 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 8147 | #else |
12b55ccc | 8148 | const char *md_shortopts = "qn"; |
252b5132 | 8149 | #endif |
6e0b89ee | 8150 | |
3e73aa7c | 8151 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
8152 | #define OPTION_64 (OPTION_MD_BASE + 1) |
8153 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
8154 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
8155 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
8156 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
8157 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
8158 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
8159 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
8160 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 8161 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 8162 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
40a9833c | 8163 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12) |
570561f7 | 8164 | #define OPTION_X32 (OPTION_MD_BASE + 13) |
b3b91714 | 8165 | |
99ad8390 NC |
8166 | struct option md_longopts[] = |
8167 | { | |
3e73aa7c | 8168 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 L |
8169 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
8170 | || defined (TE_PE) || defined (TE_PEP)) | |
3e73aa7c | 8171 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
8172 | #endif |
8173 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 8174 | {"x32", no_argument, NULL, OPTION_X32}, |
6e0b89ee | 8175 | #endif |
b3b91714 | 8176 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
8177 | {"march", required_argument, NULL, OPTION_MARCH}, |
8178 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
8179 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
8180 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
8181 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
8182 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
8183 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 8184 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 8185 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
539f890d | 8186 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
252b5132 RH |
8187 | {NULL, no_argument, NULL, 0} |
8188 | }; | |
8189 | size_t md_longopts_size = sizeof (md_longopts); | |
8190 | ||
8191 | int | |
9103f4f4 | 8192 | md_parse_option (int c, char *arg) |
252b5132 | 8193 | { |
91d6fa6a | 8194 | unsigned int j; |
6305a203 | 8195 | char *arch, *next; |
9103f4f4 | 8196 | |
252b5132 RH |
8197 | switch (c) |
8198 | { | |
12b55ccc L |
8199 | case 'n': |
8200 | optimize_align_code = 0; | |
8201 | break; | |
8202 | ||
a38cf1db AM |
8203 | case 'q': |
8204 | quiet_warnings = 1; | |
252b5132 RH |
8205 | break; |
8206 | ||
8207 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
8208 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
8209 | should be emitted or not. FIXME: Not implemented. */ | |
8210 | case 'Q': | |
252b5132 RH |
8211 | break; |
8212 | ||
8213 | /* -V: SVR4 argument to print version ID. */ | |
8214 | case 'V': | |
8215 | print_version_id (); | |
8216 | break; | |
8217 | ||
a38cf1db AM |
8218 | /* -k: Ignore for FreeBSD compatibility. */ |
8219 | case 'k': | |
252b5132 | 8220 | break; |
4cc782b5 ILT |
8221 | |
8222 | case 's': | |
8223 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 8224 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 8225 | break; |
99ad8390 | 8226 | #endif |
321098a5 L |
8227 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
8228 | || defined (TE_PE) || defined (TE_PEP)) | |
3e73aa7c JH |
8229 | case OPTION_64: |
8230 | { | |
8231 | const char **list, **l; | |
8232 | ||
3e73aa7c JH |
8233 | list = bfd_target_list (); |
8234 | for (l = list; *l != NULL; l++) | |
8620418b | 8235 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
8236 | || strcmp (*l, "coff-x86-64") == 0 |
8237 | || strcmp (*l, "pe-x86-64") == 0 | |
8238 | || strcmp (*l, "pei-x86-64") == 0) | |
6e0b89ee AM |
8239 | { |
8240 | default_arch = "x86_64"; | |
8241 | break; | |
8242 | } | |
3e73aa7c | 8243 | if (*l == NULL) |
6e0b89ee | 8244 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
8245 | free (list); |
8246 | } | |
8247 | break; | |
8248 | #endif | |
252b5132 | 8249 | |
351f65ca | 8250 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 8251 | case OPTION_X32: |
351f65ca L |
8252 | if (IS_ELF) |
8253 | { | |
8254 | const char **list, **l; | |
8255 | ||
8256 | list = bfd_target_list (); | |
8257 | for (l = list; *l != NULL; l++) | |
8258 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
8259 | { | |
8260 | default_arch = "x86_64:32"; | |
8261 | break; | |
8262 | } | |
8263 | if (*l == NULL) | |
8264 | as_fatal (_("No compiled in support for 32bit x86_64")); | |
8265 | free (list); | |
8266 | } | |
8267 | else | |
8268 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
8269 | break; | |
8270 | #endif | |
8271 | ||
6e0b89ee AM |
8272 | case OPTION_32: |
8273 | default_arch = "i386"; | |
8274 | break; | |
8275 | ||
b3b91714 AM |
8276 | case OPTION_DIVIDE: |
8277 | #ifdef SVR4_COMMENT_CHARS | |
8278 | { | |
8279 | char *n, *t; | |
8280 | const char *s; | |
8281 | ||
8282 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); | |
8283 | t = n; | |
8284 | for (s = i386_comment_chars; *s != '\0'; s++) | |
8285 | if (*s != '/') | |
8286 | *t++ = *s; | |
8287 | *t = '\0'; | |
8288 | i386_comment_chars = n; | |
8289 | } | |
8290 | #endif | |
8291 | break; | |
8292 | ||
9103f4f4 | 8293 | case OPTION_MARCH: |
6305a203 L |
8294 | arch = xstrdup (arg); |
8295 | do | |
9103f4f4 | 8296 | { |
6305a203 L |
8297 | if (*arch == '.') |
8298 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
8299 | next = strchr (arch, '+'); | |
8300 | if (next) | |
8301 | *next++ = '\0'; | |
91d6fa6a | 8302 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 8303 | { |
91d6fa6a | 8304 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 8305 | { |
6305a203 | 8306 | /* Processor. */ |
1ded5609 JB |
8307 | if (! cpu_arch[j].flags.bitfield.cpui386) |
8308 | continue; | |
8309 | ||
91d6fa6a | 8310 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 8311 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
8312 | cpu_arch_flags = cpu_arch[j].flags; |
8313 | cpu_arch_isa = cpu_arch[j].type; | |
8314 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
8315 | if (!cpu_arch_tune_set) |
8316 | { | |
8317 | cpu_arch_tune = cpu_arch_isa; | |
8318 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
8319 | } | |
8320 | break; | |
8321 | } | |
91d6fa6a NC |
8322 | else if (*cpu_arch [j].name == '.' |
8323 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 L |
8324 | { |
8325 | /* ISA entension. */ | |
8326 | i386_cpu_flags flags; | |
309d3373 | 8327 | |
49021df2 | 8328 | if (!cpu_arch[j].negated) |
309d3373 | 8329 | flags = cpu_flags_or (cpu_arch_flags, |
91d6fa6a | 8330 | cpu_arch[j].flags); |
309d3373 JB |
8331 | else |
8332 | flags = cpu_flags_and_not (cpu_arch_flags, | |
49021df2 | 8333 | cpu_arch[j].flags); |
0dfbf9d7 | 8334 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
8335 | { |
8336 | if (cpu_sub_arch_name) | |
8337 | { | |
8338 | char *name = cpu_sub_arch_name; | |
8339 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 8340 | cpu_arch[j].name, |
1bf57e9f | 8341 | (const char *) NULL); |
6305a203 L |
8342 | free (name); |
8343 | } | |
8344 | else | |
91d6fa6a | 8345 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 8346 | cpu_arch_flags = flags; |
a586129e | 8347 | cpu_arch_isa_flags = flags; |
6305a203 L |
8348 | } |
8349 | break; | |
ccc9c027 | 8350 | } |
9103f4f4 | 8351 | } |
6305a203 | 8352 | |
91d6fa6a | 8353 | if (j >= ARRAY_SIZE (cpu_arch)) |
6305a203 L |
8354 | as_fatal (_("Invalid -march= option: `%s'"), arg); |
8355 | ||
8356 | arch = next; | |
9103f4f4 | 8357 | } |
6305a203 | 8358 | while (next != NULL ); |
9103f4f4 L |
8359 | break; |
8360 | ||
8361 | case OPTION_MTUNE: | |
8362 | if (*arg == '.') | |
8363 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
91d6fa6a | 8364 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 8365 | { |
91d6fa6a | 8366 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 8367 | { |
ccc9c027 | 8368 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
8369 | cpu_arch_tune = cpu_arch [j].type; |
8370 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
8371 | break; |
8372 | } | |
8373 | } | |
91d6fa6a | 8374 | if (j >= ARRAY_SIZE (cpu_arch)) |
9103f4f4 L |
8375 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); |
8376 | break; | |
8377 | ||
1efbbeb4 L |
8378 | case OPTION_MMNEMONIC: |
8379 | if (strcasecmp (arg, "att") == 0) | |
8380 | intel_mnemonic = 0; | |
8381 | else if (strcasecmp (arg, "intel") == 0) | |
8382 | intel_mnemonic = 1; | |
8383 | else | |
8384 | as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg); | |
8385 | break; | |
8386 | ||
8387 | case OPTION_MSYNTAX: | |
8388 | if (strcasecmp (arg, "att") == 0) | |
8389 | intel_syntax = 0; | |
8390 | else if (strcasecmp (arg, "intel") == 0) | |
8391 | intel_syntax = 1; | |
8392 | else | |
8393 | as_fatal (_("Invalid -msyntax= option: `%s'"), arg); | |
8394 | break; | |
8395 | ||
8396 | case OPTION_MINDEX_REG: | |
8397 | allow_index_reg = 1; | |
8398 | break; | |
8399 | ||
8400 | case OPTION_MNAKED_REG: | |
8401 | allow_naked_reg = 1; | |
8402 | break; | |
8403 | ||
8404 | case OPTION_MOLD_GCC: | |
8405 | old_gcc = 1; | |
1efbbeb4 L |
8406 | break; |
8407 | ||
c0f3af97 L |
8408 | case OPTION_MSSE2AVX: |
8409 | sse2avx = 1; | |
8410 | break; | |
8411 | ||
daf50ae7 L |
8412 | case OPTION_MSSE_CHECK: |
8413 | if (strcasecmp (arg, "error") == 0) | |
8414 | sse_check = sse_check_error; | |
8415 | else if (strcasecmp (arg, "warning") == 0) | |
8416 | sse_check = sse_check_warning; | |
8417 | else if (strcasecmp (arg, "none") == 0) | |
8418 | sse_check = sse_check_none; | |
8419 | else | |
8420 | as_fatal (_("Invalid -msse-check= option: `%s'"), arg); | |
8421 | break; | |
8422 | ||
539f890d L |
8423 | case OPTION_MAVXSCALAR: |
8424 | if (strcasecmp (arg, "128") == 0) | |
8425 | avxscalar = vex128; | |
8426 | else if (strcasecmp (arg, "256") == 0) | |
8427 | avxscalar = vex256; | |
8428 | else | |
8429 | as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg); | |
8430 | break; | |
8431 | ||
252b5132 RH |
8432 | default: |
8433 | return 0; | |
8434 | } | |
8435 | return 1; | |
8436 | } | |
8437 | ||
8a2c8fef L |
8438 | #define MESSAGE_TEMPLATE \ |
8439 | " " | |
8440 | ||
8441 | static void | |
1ded5609 | 8442 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
8443 | { |
8444 | static char message[] = MESSAGE_TEMPLATE; | |
8445 | char *start = message + 27; | |
8446 | char *p; | |
8447 | int size = sizeof (MESSAGE_TEMPLATE); | |
8448 | int left; | |
8449 | const char *name; | |
8450 | int len; | |
8451 | unsigned int j; | |
8452 | ||
8453 | p = start; | |
8454 | left = size - (start - message); | |
8455 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
8456 | { | |
8457 | /* Should it be skipped? */ | |
8458 | if (cpu_arch [j].skip) | |
8459 | continue; | |
8460 | ||
8461 | name = cpu_arch [j].name; | |
8462 | len = cpu_arch [j].len; | |
8463 | if (*name == '.') | |
8464 | { | |
8465 | /* It is an extension. Skip if we aren't asked to show it. */ | |
8466 | if (ext) | |
8467 | { | |
8468 | name++; | |
8469 | len--; | |
8470 | } | |
8471 | else | |
8472 | continue; | |
8473 | } | |
8474 | else if (ext) | |
8475 | { | |
8476 | /* It is an processor. Skip if we show only extension. */ | |
8477 | continue; | |
8478 | } | |
1ded5609 JB |
8479 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
8480 | { | |
8481 | /* It is an impossible processor - skip. */ | |
8482 | continue; | |
8483 | } | |
8a2c8fef L |
8484 | |
8485 | /* Reserve 2 spaces for ", " or ",\0" */ | |
8486 | left -= len + 2; | |
8487 | ||
8488 | /* Check if there is any room. */ | |
8489 | if (left >= 0) | |
8490 | { | |
8491 | if (p != start) | |
8492 | { | |
8493 | *p++ = ','; | |
8494 | *p++ = ' '; | |
8495 | } | |
8496 | p = mempcpy (p, name, len); | |
8497 | } | |
8498 | else | |
8499 | { | |
8500 | /* Output the current message now and start a new one. */ | |
8501 | *p++ = ','; | |
8502 | *p = '\0'; | |
8503 | fprintf (stream, "%s\n", message); | |
8504 | p = start; | |
8505 | left = size - (start - message) - len - 2; | |
8506 | ||
8507 | gas_assert (left >= 0); | |
8508 | ||
8509 | p = mempcpy (p, name, len); | |
8510 | } | |
8511 | } | |
8512 | ||
8513 | *p = '\0'; | |
8514 | fprintf (stream, "%s\n", message); | |
8515 | } | |
8516 | ||
252b5132 | 8517 | void |
8a2c8fef | 8518 | md_show_usage (FILE *stream) |
252b5132 | 8519 | { |
4cc782b5 ILT |
8520 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8521 | fprintf (stream, _("\ | |
a38cf1db AM |
8522 | -Q ignored\n\ |
8523 | -V print assembler version number\n\ | |
b3b91714 AM |
8524 | -k ignored\n")); |
8525 | #endif | |
8526 | fprintf (stream, _("\ | |
12b55ccc | 8527 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
8528 | -q quieten some warnings\n")); |
8529 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
8530 | fprintf (stream, _("\ | |
a38cf1db | 8531 | -s ignored\n")); |
b3b91714 | 8532 | #endif |
321098a5 L |
8533 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
8534 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 8535 | fprintf (stream, _("\ |
570561f7 | 8536 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 8537 | #endif |
b3b91714 AM |
8538 | #ifdef SVR4_COMMENT_CHARS |
8539 | fprintf (stream, _("\ | |
8540 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
8541 | #else |
8542 | fprintf (stream, _("\ | |
b3b91714 | 8543 | --divide ignored\n")); |
4cc782b5 | 8544 | #endif |
9103f4f4 | 8545 | fprintf (stream, _("\ |
6305a203 | 8546 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 8547 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 8548 | show_arch (stream, 0, 1); |
8a2c8fef L |
8549 | fprintf (stream, _("\ |
8550 | EXTENSION is combination of:\n")); | |
1ded5609 | 8551 | show_arch (stream, 1, 0); |
6305a203 | 8552 | fprintf (stream, _("\ |
8a2c8fef | 8553 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 8554 | show_arch (stream, 0, 0); |
ba104c83 | 8555 | fprintf (stream, _("\ |
c0f3af97 L |
8556 | -msse2avx encode SSE instructions with VEX prefix\n")); |
8557 | fprintf (stream, _("\ | |
daf50ae7 L |
8558 | -msse-check=[none|error|warning]\n\ |
8559 | check SSE instructions\n")); | |
8560 | fprintf (stream, _("\ | |
539f890d L |
8561 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
8562 | length\n")); | |
8563 | fprintf (stream, _("\ | |
ba104c83 L |
8564 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
8565 | fprintf (stream, _("\ | |
8566 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
8567 | fprintf (stream, _("\ | |
8568 | -mindex-reg support pseudo index registers\n")); | |
8569 | fprintf (stream, _("\ | |
8570 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
8571 | fprintf (stream, _("\ | |
8572 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
252b5132 RH |
8573 | } |
8574 | ||
3e73aa7c | 8575 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 8576 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 8577 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
8578 | |
8579 | /* Pick the target format to use. */ | |
8580 | ||
47926f60 | 8581 | const char * |
e3bb37b5 | 8582 | i386_target_format (void) |
252b5132 | 8583 | { |
351f65ca L |
8584 | if (!strncmp (default_arch, "x86_64", 6)) |
8585 | { | |
8586 | update_code_flag (CODE_64BIT, 1); | |
8587 | if (default_arch[6] == '\0') | |
7f56bc95 | 8588 | x86_elf_abi = X86_64_ABI; |
351f65ca | 8589 | else |
7f56bc95 | 8590 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 8591 | } |
3e73aa7c | 8592 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 8593 | update_code_flag (CODE_32BIT, 1); |
3e73aa7c JH |
8594 | else |
8595 | as_fatal (_("Unknown architecture")); | |
89507696 JB |
8596 | |
8597 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
8598 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
8599 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
8600 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
8601 | ||
252b5132 RH |
8602 | switch (OUTPUT_FLAVOR) |
8603 | { | |
9384f2ff | 8604 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 8605 | case bfd_target_aout_flavour: |
47926f60 | 8606 | return AOUT_TARGET_FORMAT; |
4c63da97 | 8607 | #endif |
9384f2ff AM |
8608 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
8609 | # if defined (TE_PE) || defined (TE_PEP) | |
8610 | case bfd_target_coff_flavour: | |
8611 | return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386"; | |
8612 | # elif defined (TE_GO32) | |
0561d57c JK |
8613 | case bfd_target_coff_flavour: |
8614 | return "coff-go32"; | |
9384f2ff | 8615 | # else |
252b5132 RH |
8616 | case bfd_target_coff_flavour: |
8617 | return "coff-i386"; | |
9384f2ff | 8618 | # endif |
4c63da97 | 8619 | #endif |
3e73aa7c | 8620 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 8621 | case bfd_target_elf_flavour: |
3e73aa7c | 8622 | { |
351f65ca L |
8623 | const char *format; |
8624 | ||
8625 | switch (x86_elf_abi) | |
4fa24527 | 8626 | { |
351f65ca L |
8627 | default: |
8628 | format = ELF_TARGET_FORMAT; | |
8629 | break; | |
7f56bc95 | 8630 | case X86_64_ABI: |
351f65ca | 8631 | use_rela_relocations = 1; |
4fa24527 | 8632 | object_64bit = 1; |
351f65ca L |
8633 | format = ELF_TARGET_FORMAT64; |
8634 | break; | |
7f56bc95 | 8635 | case X86_64_X32_ABI: |
4fa24527 | 8636 | use_rela_relocations = 1; |
351f65ca | 8637 | object_64bit = 1; |
862be3fb | 8638 | disallow_64bit_reloc = 1; |
351f65ca L |
8639 | format = ELF_TARGET_FORMAT32; |
8640 | break; | |
4fa24527 | 8641 | } |
3632d14b | 8642 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 8643 | { |
7f56bc95 | 8644 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
8645 | as_fatal (_("Intel L1OM is 64bit only")); |
8646 | return ELF_TARGET_L1OM_FORMAT; | |
8647 | } | |
8648 | else | |
351f65ca | 8649 | return format; |
3e73aa7c | 8650 | } |
e57f8c65 TG |
8651 | #endif |
8652 | #if defined (OBJ_MACH_O) | |
8653 | case bfd_target_mach_o_flavour: | |
8654 | return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386"; | |
4c63da97 | 8655 | #endif |
252b5132 RH |
8656 | default: |
8657 | abort (); | |
8658 | return NULL; | |
8659 | } | |
8660 | } | |
8661 | ||
47926f60 | 8662 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
8663 | |
8664 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 L |
8665 | void |
8666 | i386_elf_emit_arch_note (void) | |
a847613f | 8667 | { |
718ddfc0 | 8668 | if (IS_ELF && cpu_arch_name != NULL) |
a847613f AM |
8669 | { |
8670 | char *p; | |
8671 | asection *seg = now_seg; | |
8672 | subsegT subseg = now_subseg; | |
8673 | Elf_Internal_Note i_note; | |
8674 | Elf_External_Note e_note; | |
8675 | asection *note_secp; | |
8676 | int len; | |
8677 | ||
8678 | /* Create the .note section. */ | |
8679 | note_secp = subseg_new (".note", 0); | |
8680 | bfd_set_section_flags (stdoutput, | |
8681 | note_secp, | |
8682 | SEC_HAS_CONTENTS | SEC_READONLY); | |
8683 | ||
8684 | /* Process the arch string. */ | |
8685 | len = strlen (cpu_arch_name); | |
8686 | ||
8687 | i_note.namesz = len + 1; | |
8688 | i_note.descsz = 0; | |
8689 | i_note.type = NT_ARCH; | |
8690 | p = frag_more (sizeof (e_note.namesz)); | |
8691 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
8692 | p = frag_more (sizeof (e_note.descsz)); | |
8693 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
8694 | p = frag_more (sizeof (e_note.type)); | |
8695 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
8696 | p = frag_more (len + 1); | |
8697 | strcpy (p, cpu_arch_name); | |
8698 | ||
8699 | frag_align (2, 0, 0); | |
8700 | ||
8701 | subseg_set (seg, subseg); | |
8702 | } | |
8703 | } | |
8704 | #endif | |
252b5132 | 8705 | \f |
252b5132 RH |
8706 | symbolS * |
8707 | md_undefined_symbol (name) | |
8708 | char *name; | |
8709 | { | |
18dc2407 ILT |
8710 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
8711 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
8712 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
8713 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
8714 | { |
8715 | if (!GOT_symbol) | |
8716 | { | |
8717 | if (symbol_find (name)) | |
8718 | as_bad (_("GOT already in symbol table")); | |
8719 | GOT_symbol = symbol_new (name, undefined_section, | |
8720 | (valueT) 0, &zero_address_frag); | |
8721 | }; | |
8722 | return GOT_symbol; | |
8723 | } | |
252b5132 RH |
8724 | return 0; |
8725 | } | |
8726 | ||
8727 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 8728 | |
252b5132 RH |
8729 | valueT |
8730 | md_section_align (segment, size) | |
ab9da554 | 8731 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
8732 | valueT size; |
8733 | { | |
4c63da97 AM |
8734 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
8735 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
8736 | { | |
8737 | /* For a.out, force the section size to be aligned. If we don't do | |
8738 | this, BFD will align it for us, but it will not write out the | |
8739 | final bytes of the section. This may be a bug in BFD, but it is | |
8740 | easier to fix it here since that is how the other a.out targets | |
8741 | work. */ | |
8742 | int align; | |
8743 | ||
8744 | align = bfd_get_section_alignment (stdoutput, segment); | |
8745 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
8746 | } | |
252b5132 RH |
8747 | #endif |
8748 | ||
8749 | return size; | |
8750 | } | |
8751 | ||
8752 | /* On the i386, PC-relative offsets are relative to the start of the | |
8753 | next instruction. That is, the address of the offset, plus its | |
8754 | size, since the offset is always the last part of the insn. */ | |
8755 | ||
8756 | long | |
e3bb37b5 | 8757 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
8758 | { |
8759 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
8760 | } | |
8761 | ||
8762 | #ifndef I386COFF | |
8763 | ||
8764 | static void | |
e3bb37b5 | 8765 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 8766 | { |
29b0f896 | 8767 | int temp; |
252b5132 | 8768 | |
8a75718c JB |
8769 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8770 | if (IS_ELF) | |
8771 | obj_elf_section_change_hook (); | |
8772 | #endif | |
252b5132 RH |
8773 | temp = get_absolute_expression (); |
8774 | subseg_set (bss_section, (subsegT) temp); | |
8775 | demand_empty_rest_of_line (); | |
8776 | } | |
8777 | ||
8778 | #endif | |
8779 | ||
252b5132 | 8780 | void |
e3bb37b5 | 8781 | i386_validate_fix (fixS *fixp) |
252b5132 RH |
8782 | { |
8783 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
8784 | { | |
23df1078 JH |
8785 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
8786 | { | |
4fa24527 | 8787 | if (!object_64bit) |
23df1078 JH |
8788 | abort (); |
8789 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
8790 | } | |
8791 | else | |
8792 | { | |
4fa24527 | 8793 | if (!object_64bit) |
d6ab8113 JB |
8794 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
8795 | else | |
8796 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
23df1078 | 8797 | } |
252b5132 RH |
8798 | fixp->fx_subsy = 0; |
8799 | } | |
8800 | } | |
8801 | ||
252b5132 RH |
8802 | arelent * |
8803 | tc_gen_reloc (section, fixp) | |
ab9da554 | 8804 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
8805 | fixS *fixp; |
8806 | { | |
8807 | arelent *rel; | |
8808 | bfd_reloc_code_real_type code; | |
8809 | ||
8810 | switch (fixp->fx_r_type) | |
8811 | { | |
3e73aa7c JH |
8812 | case BFD_RELOC_X86_64_PLT32: |
8813 | case BFD_RELOC_X86_64_GOT32: | |
8814 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
8815 | case BFD_RELOC_386_PLT32: |
8816 | case BFD_RELOC_386_GOT32: | |
8817 | case BFD_RELOC_386_GOTOFF: | |
8818 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
8819 | case BFD_RELOC_386_TLS_GD: |
8820 | case BFD_RELOC_386_TLS_LDM: | |
8821 | case BFD_RELOC_386_TLS_LDO_32: | |
8822 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
8823 | case BFD_RELOC_386_TLS_IE: |
8824 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
8825 | case BFD_RELOC_386_TLS_LE_32: |
8826 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
8827 | case BFD_RELOC_386_TLS_GOTDESC: |
8828 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
8829 | case BFD_RELOC_X86_64_TLSGD: |
8830 | case BFD_RELOC_X86_64_TLSLD: | |
8831 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 8832 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
8833 | case BFD_RELOC_X86_64_GOTTPOFF: |
8834 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
8835 | case BFD_RELOC_X86_64_TPOFF64: |
8836 | case BFD_RELOC_X86_64_GOTOFF64: | |
8837 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
8838 | case BFD_RELOC_X86_64_GOT64: |
8839 | case BFD_RELOC_X86_64_GOTPCREL64: | |
8840 | case BFD_RELOC_X86_64_GOTPC64: | |
8841 | case BFD_RELOC_X86_64_GOTPLT64: | |
8842 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
8843 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
8844 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
8845 | case BFD_RELOC_RVA: |
8846 | case BFD_RELOC_VTABLE_ENTRY: | |
8847 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
8848 | #ifdef TE_PE |
8849 | case BFD_RELOC_32_SECREL: | |
8850 | #endif | |
252b5132 RH |
8851 | code = fixp->fx_r_type; |
8852 | break; | |
dbbaec26 L |
8853 | case BFD_RELOC_X86_64_32S: |
8854 | if (!fixp->fx_pcrel) | |
8855 | { | |
8856 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
8857 | code = fixp->fx_r_type; | |
8858 | break; | |
8859 | } | |
252b5132 | 8860 | default: |
93382f6d | 8861 | if (fixp->fx_pcrel) |
252b5132 | 8862 | { |
93382f6d AM |
8863 | switch (fixp->fx_size) |
8864 | { | |
8865 | default: | |
b091f402 AM |
8866 | as_bad_where (fixp->fx_file, fixp->fx_line, |
8867 | _("can not do %d byte pc-relative relocation"), | |
8868 | fixp->fx_size); | |
93382f6d AM |
8869 | code = BFD_RELOC_32_PCREL; |
8870 | break; | |
8871 | case 1: code = BFD_RELOC_8_PCREL; break; | |
8872 | case 2: code = BFD_RELOC_16_PCREL; break; | |
8873 | case 4: code = BFD_RELOC_32_PCREL; break; | |
d6ab8113 JB |
8874 | #ifdef BFD64 |
8875 | case 8: code = BFD_RELOC_64_PCREL; break; | |
8876 | #endif | |
93382f6d AM |
8877 | } |
8878 | } | |
8879 | else | |
8880 | { | |
8881 | switch (fixp->fx_size) | |
8882 | { | |
8883 | default: | |
b091f402 AM |
8884 | as_bad_where (fixp->fx_file, fixp->fx_line, |
8885 | _("can not do %d byte relocation"), | |
8886 | fixp->fx_size); | |
93382f6d AM |
8887 | code = BFD_RELOC_32; |
8888 | break; | |
8889 | case 1: code = BFD_RELOC_8; break; | |
8890 | case 2: code = BFD_RELOC_16; break; | |
8891 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 8892 | #ifdef BFD64 |
3e73aa7c | 8893 | case 8: code = BFD_RELOC_64; break; |
937149dd | 8894 | #endif |
93382f6d | 8895 | } |
252b5132 RH |
8896 | } |
8897 | break; | |
8898 | } | |
252b5132 | 8899 | |
d182319b JB |
8900 | if ((code == BFD_RELOC_32 |
8901 | || code == BFD_RELOC_32_PCREL | |
8902 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
8903 | && GOT_symbol |
8904 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 8905 | { |
4fa24527 | 8906 | if (!object_64bit) |
d6ab8113 JB |
8907 | code = BFD_RELOC_386_GOTPC; |
8908 | else | |
8909 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 8910 | } |
7b81dfbb AJ |
8911 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
8912 | && GOT_symbol | |
8913 | && fixp->fx_addsy == GOT_symbol) | |
8914 | { | |
8915 | code = BFD_RELOC_X86_64_GOTPC64; | |
8916 | } | |
252b5132 RH |
8917 | |
8918 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
8919 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
8920 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
8921 | |
8922 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 8923 | |
3e73aa7c JH |
8924 | if (!use_rela_relocations) |
8925 | { | |
8926 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
8927 | vtable entry to be used in the relocation's section offset. */ | |
8928 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
8929 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
8930 | #if defined (OBJ_COFF) && defined (TE_PE) |
8931 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
8932 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
8933 | else | |
8934 | #endif | |
c6682705 | 8935 | rel->addend = 0; |
3e73aa7c JH |
8936 | } |
8937 | /* Use the rela in 64bit mode. */ | |
252b5132 | 8938 | else |
3e73aa7c | 8939 | { |
862be3fb L |
8940 | if (disallow_64bit_reloc) |
8941 | switch (code) | |
8942 | { | |
8943 | case BFD_RELOC_64: | |
8944 | case BFD_RELOC_X86_64_DTPOFF64: | |
8945 | case BFD_RELOC_X86_64_TPOFF64: | |
8946 | case BFD_RELOC_64_PCREL: | |
8947 | case BFD_RELOC_X86_64_GOTOFF64: | |
8948 | case BFD_RELOC_X86_64_GOT64: | |
8949 | case BFD_RELOC_X86_64_GOTPCREL64: | |
8950 | case BFD_RELOC_X86_64_GOTPC64: | |
8951 | case BFD_RELOC_X86_64_GOTPLT64: | |
8952 | case BFD_RELOC_X86_64_PLTOFF64: | |
8953 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
8954 | _("cannot represent relocation type %s in x32 mode"), | |
8955 | bfd_get_reloc_code_name (code)); | |
8956 | break; | |
8957 | default: | |
8958 | break; | |
8959 | } | |
8960 | ||
062cd5e7 AS |
8961 | if (!fixp->fx_pcrel) |
8962 | rel->addend = fixp->fx_offset; | |
8963 | else | |
8964 | switch (code) | |
8965 | { | |
8966 | case BFD_RELOC_X86_64_PLT32: | |
8967 | case BFD_RELOC_X86_64_GOT32: | |
8968 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
8969 | case BFD_RELOC_X86_64_TLSGD: |
8970 | case BFD_RELOC_X86_64_TLSLD: | |
8971 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
8972 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
8973 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
8974 | rel->addend = fixp->fx_offset - fixp->fx_size; |
8975 | break; | |
8976 | default: | |
8977 | rel->addend = (section->vma | |
8978 | - fixp->fx_size | |
8979 | + fixp->fx_addnumber | |
8980 | + md_pcrel_from (fixp)); | |
8981 | break; | |
8982 | } | |
3e73aa7c JH |
8983 | } |
8984 | ||
252b5132 RH |
8985 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
8986 | if (rel->howto == NULL) | |
8987 | { | |
8988 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 8989 | _("cannot represent relocation type %s"), |
252b5132 RH |
8990 | bfd_get_reloc_code_name (code)); |
8991 | /* Set howto to a garbage value so that we can keep going. */ | |
8992 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 8993 | gas_assert (rel->howto != NULL); |
252b5132 RH |
8994 | } |
8995 | ||
8996 | return rel; | |
8997 | } | |
8998 | ||
ee86248c | 8999 | #include "tc-i386-intel.c" |
54cfded0 | 9000 | |
a60de03c JB |
9001 | void |
9002 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 9003 | { |
a60de03c JB |
9004 | int saved_naked_reg; |
9005 | char saved_register_dot; | |
54cfded0 | 9006 | |
a60de03c JB |
9007 | saved_naked_reg = allow_naked_reg; |
9008 | allow_naked_reg = 1; | |
9009 | saved_register_dot = register_chars['.']; | |
9010 | register_chars['.'] = '.'; | |
9011 | allow_pseudo_reg = 1; | |
9012 | expression_and_evaluate (exp); | |
9013 | allow_pseudo_reg = 0; | |
9014 | register_chars['.'] = saved_register_dot; | |
9015 | allow_naked_reg = saved_naked_reg; | |
9016 | ||
e96d56a1 | 9017 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 9018 | { |
a60de03c JB |
9019 | if ((addressT) exp->X_add_number < i386_regtab_size) |
9020 | { | |
9021 | exp->X_op = O_constant; | |
9022 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
9023 | .dw2_regnum[flag_code >> 1]; | |
9024 | } | |
9025 | else | |
9026 | exp->X_op = O_illegal; | |
54cfded0 | 9027 | } |
54cfded0 AM |
9028 | } |
9029 | ||
9030 | void | |
9031 | tc_x86_frame_initial_instructions (void) | |
9032 | { | |
a60de03c JB |
9033 | static unsigned int sp_regno[2]; |
9034 | ||
9035 | if (!sp_regno[flag_code >> 1]) | |
9036 | { | |
9037 | char *saved_input = input_line_pointer; | |
9038 | char sp[][4] = {"esp", "rsp"}; | |
9039 | expressionS exp; | |
a4447b93 | 9040 | |
a60de03c JB |
9041 | input_line_pointer = sp[flag_code >> 1]; |
9042 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 9043 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
9044 | sp_regno[flag_code >> 1] = exp.X_add_number; |
9045 | input_line_pointer = saved_input; | |
9046 | } | |
a4447b93 | 9047 | |
61ff971f L |
9048 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
9049 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 9050 | } |
d2b2c203 DJ |
9051 | |
9052 | int | |
9053 | i386_elf_section_type (const char *str, size_t len) | |
9054 | { | |
9055 | if (flag_code == CODE_64BIT | |
9056 | && len == sizeof ("unwind") - 1 | |
9057 | && strncmp (str, "unwind", 6) == 0) | |
9058 | return SHT_X86_64_UNWIND; | |
9059 | ||
9060 | return -1; | |
9061 | } | |
bb41ade5 | 9062 | |
ad5fec3b EB |
9063 | #ifdef TE_SOLARIS |
9064 | void | |
9065 | i386_solaris_fix_up_eh_frame (segT sec) | |
9066 | { | |
9067 | if (flag_code == CODE_64BIT) | |
9068 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
9069 | } | |
9070 | #endif | |
9071 | ||
bb41ade5 AM |
9072 | #ifdef TE_PE |
9073 | void | |
9074 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
9075 | { | |
91d6fa6a | 9076 | expressionS exp; |
bb41ade5 | 9077 | |
91d6fa6a NC |
9078 | exp.X_op = O_secrel; |
9079 | exp.X_add_symbol = symbol; | |
9080 | exp.X_add_number = 0; | |
9081 | emit_expr (&exp, size); | |
bb41ade5 AM |
9082 | } |
9083 | #endif | |
3b22753a L |
9084 | |
9085 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
9086 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
9087 | ||
01e1a5bc | 9088 | bfd_vma |
3b22753a L |
9089 | x86_64_section_letter (int letter, char **ptr_msg) |
9090 | { | |
9091 | if (flag_code == CODE_64BIT) | |
9092 | { | |
9093 | if (letter == 'l') | |
9094 | return SHF_X86_64_LARGE; | |
9095 | ||
8f3bae45 | 9096 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 9097 | } |
3b22753a | 9098 | else |
8f3bae45 | 9099 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
9100 | return -1; |
9101 | } | |
9102 | ||
01e1a5bc | 9103 | bfd_vma |
3b22753a L |
9104 | x86_64_section_word (char *str, size_t len) |
9105 | { | |
8620418b | 9106 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
9107 | return SHF_X86_64_LARGE; |
9108 | ||
9109 | return -1; | |
9110 | } | |
9111 | ||
9112 | static void | |
9113 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
9114 | { | |
9115 | if (flag_code != CODE_64BIT) | |
9116 | { | |
9117 | s_comm_internal (0, elf_common_parse); | |
9118 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
9119 | } | |
9120 | else | |
9121 | { | |
9122 | static segT lbss_section; | |
9123 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
9124 | asection *saved_bss_section = bss_section; | |
9125 | ||
9126 | if (lbss_section == NULL) | |
9127 | { | |
9128 | flagword applicable; | |
9129 | segT seg = now_seg; | |
9130 | subsegT subseg = now_subseg; | |
9131 | ||
9132 | /* The .lbss section is for local .largecomm symbols. */ | |
9133 | lbss_section = subseg_new (".lbss", 0); | |
9134 | applicable = bfd_applicable_section_flags (stdoutput); | |
9135 | bfd_set_section_flags (stdoutput, lbss_section, | |
9136 | applicable & SEC_ALLOC); | |
9137 | seg_info (lbss_section)->bss = 1; | |
9138 | ||
9139 | subseg_set (seg, subseg); | |
9140 | } | |
9141 | ||
9142 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
9143 | bss_section = lbss_section; | |
9144 | ||
9145 | s_comm_internal (0, elf_common_parse); | |
9146 | ||
9147 | elf_com_section_ptr = saved_com_section_ptr; | |
9148 | bss_section = saved_bss_section; | |
9149 | } | |
9150 | } | |
9151 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |