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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
b3adc24a | 2 | Copyright (C) 1989-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
c3332e24 | 47 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 48 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
49 | #endif |
50 | ||
29b0f896 AM |
51 | #ifndef DEFAULT_ARCH |
52 | #define DEFAULT_ARCH "i386" | |
246fcdee | 53 | #endif |
252b5132 | 54 | |
edde18a5 AM |
55 | #ifndef INLINE |
56 | #if __GNUC__ >= 2 | |
57 | #define INLINE __inline__ | |
58 | #else | |
59 | #define INLINE | |
60 | #endif | |
61 | #endif | |
62 | ||
6305a203 L |
63 | /* Prefixes will be emitted in the order defined below. |
64 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
65 | instruction, and so must come before any prefixes. | |
66 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 67 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
68 | #define WAIT_PREFIX 0 |
69 | #define SEG_PREFIX 1 | |
70 | #define ADDR_PREFIX 2 | |
71 | #define DATA_PREFIX 3 | |
c32fa91d | 72 | #define REP_PREFIX 4 |
42164a71 | 73 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 74 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 75 | #define LOCK_PREFIX 5 |
4e9ac44a L |
76 | #define REX_PREFIX 6 /* must come last. */ |
77 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
78 | |
79 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
80 | #define REGISTER_PREFIX '%' | |
81 | #define IMMEDIATE_PREFIX '$' | |
82 | #define ABSOLUTE_PREFIX '*' | |
83 | ||
84 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
85 | memory operand size in Intel syntax. */ | |
86 | #define WORD_MNEM_SUFFIX 'w' | |
87 | #define BYTE_MNEM_SUFFIX 'b' | |
88 | #define SHORT_MNEM_SUFFIX 's' | |
89 | #define LONG_MNEM_SUFFIX 'l' | |
90 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
91 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
92 | in instructions. */ | |
93 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
94 | ||
95 | #define END_OF_INSN '\0' | |
96 | ||
79dec6b7 JB |
97 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
98 | #define commutative staticrounding | |
99 | ||
6305a203 L |
100 | /* |
101 | 'templates' is for grouping together 'template' structures for opcodes | |
102 | of the same name. This is only used for storing the insns in the grand | |
103 | ole hash table of insns. | |
104 | The templates themselves start at START and range up to (but not including) | |
105 | END. | |
106 | */ | |
107 | typedef struct | |
108 | { | |
d3ce72d0 NC |
109 | const insn_template *start; |
110 | const insn_template *end; | |
6305a203 L |
111 | } |
112 | templates; | |
113 | ||
114 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
115 | typedef struct | |
116 | { | |
117 | unsigned int regmem; /* codes register or memory operand */ | |
118 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
119 | unsigned int mode; /* how to interpret regmem & reg */ | |
120 | } | |
121 | modrm_byte; | |
122 | ||
123 | /* x86-64 extension prefix. */ | |
124 | typedef int rex_byte; | |
125 | ||
6305a203 L |
126 | /* 386 opcode byte to code indirect addressing. */ |
127 | typedef struct | |
128 | { | |
129 | unsigned base; | |
130 | unsigned index; | |
131 | unsigned scale; | |
132 | } | |
133 | sib_byte; | |
134 | ||
6305a203 L |
135 | /* x86 arch names, types and features */ |
136 | typedef struct | |
137 | { | |
138 | const char *name; /* arch name */ | |
8a2c8fef | 139 | unsigned int len; /* arch string length */ |
6305a203 L |
140 | enum processor_type type; /* arch type */ |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 142 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
143 | } |
144 | arch_entry; | |
145 | ||
293f5f65 L |
146 | /* Used to turn off indicated flags. */ |
147 | typedef struct | |
148 | { | |
149 | const char *name; /* arch name */ | |
150 | unsigned int len; /* arch string length */ | |
151 | i386_cpu_flags flags; /* cpu feature flags */ | |
152 | } | |
153 | noarch_entry; | |
154 | ||
78f12dd3 | 155 | static void update_code_flag (int, int); |
e3bb37b5 L |
156 | static void set_code_flag (int); |
157 | static void set_16bit_gcc_code_flag (int); | |
158 | static void set_intel_syntax (int); | |
1efbbeb4 | 159 | static void set_intel_mnemonic (int); |
db51cc60 | 160 | static void set_allow_index_reg (int); |
7bab8ab5 | 161 | static void set_check (int); |
e3bb37b5 | 162 | static void set_cpu_arch (int); |
6482c264 | 163 | #ifdef TE_PE |
e3bb37b5 | 164 | static void pe_directive_secrel (int); |
6482c264 | 165 | #endif |
e3bb37b5 L |
166 | static void signed_cons (int); |
167 | static char *output_invalid (int c); | |
ee86248c JB |
168 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
169 | const char *); | |
170 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
171 | const char *); | |
a7619375 | 172 | static int i386_att_operand (char *); |
e3bb37b5 | 173 | static int i386_intel_operand (char *, int); |
ee86248c JB |
174 | static int i386_intel_simplify (expressionS *); |
175 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
176 | static const reg_entry *parse_register (char *, char **); |
177 | static char *parse_insn (char *, char *); | |
178 | static char *parse_operands (char *, const char *); | |
179 | static void swap_operands (void); | |
4d456e3d | 180 | static void swap_2_operands (int, int); |
48bcea9f | 181 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
182 | static void optimize_imm (void); |
183 | static void optimize_disp (void); | |
83b16ac6 | 184 | static const insn_template *match_template (char); |
e3bb37b5 L |
185 | static int check_string (void); |
186 | static int process_suffix (void); | |
187 | static int check_byte_reg (void); | |
188 | static int check_long_reg (void); | |
189 | static int check_qword_reg (void); | |
190 | static int check_word_reg (void); | |
191 | static int finalize_imm (void); | |
192 | static int process_operands (void); | |
193 | static const seg_entry *build_modrm_byte (void); | |
194 | static void output_insn (void); | |
195 | static void output_imm (fragS *, offsetT); | |
196 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 197 | #ifndef I386COFF |
e3bb37b5 | 198 | static void s_bss (int); |
252b5132 | 199 | #endif |
17d4e2a2 L |
200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
201 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
202 | |
203 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
204 | static unsigned int x86_isa_1_used; | |
205 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
206 | static unsigned int x86_feature_2_used; | |
207 | /* Generate x86 used ISA and feature properties. */ | |
208 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 209 | #endif |
252b5132 | 210 | |
a847613f | 211 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 212 | |
43234a1e L |
213 | /* This struct describes rounding control and SAE in the instruction. */ |
214 | struct RC_Operation | |
215 | { | |
216 | enum rc_type | |
217 | { | |
218 | rne = 0, | |
219 | rd, | |
220 | ru, | |
221 | rz, | |
222 | saeonly | |
223 | } type; | |
224 | int operand; | |
225 | }; | |
226 | ||
227 | static struct RC_Operation rc_op; | |
228 | ||
229 | /* The struct describes masking, applied to OPERAND in the instruction. | |
230 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
231 | whether merging or zeroing mask is used. */ | |
232 | struct Mask_Operation | |
233 | { | |
234 | const reg_entry *mask; | |
235 | unsigned int zeroing; | |
236 | /* The operand where this operation is associated. */ | |
237 | int operand; | |
238 | }; | |
239 | ||
240 | static struct Mask_Operation mask_op; | |
241 | ||
242 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
243 | broadcast factor. */ | |
244 | struct Broadcast_Operation | |
245 | { | |
8e6e0792 | 246 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
247 | int type; |
248 | ||
249 | /* Index of broadcasted operand. */ | |
250 | int operand; | |
4a1b91ea L |
251 | |
252 | /* Number of bytes to broadcast. */ | |
253 | int bytes; | |
43234a1e L |
254 | }; |
255 | ||
256 | static struct Broadcast_Operation broadcast_op; | |
257 | ||
c0f3af97 L |
258 | /* VEX prefix. */ |
259 | typedef struct | |
260 | { | |
43234a1e L |
261 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
262 | unsigned char bytes[4]; | |
c0f3af97 L |
263 | unsigned int length; |
264 | /* Destination or source register specifier. */ | |
265 | const reg_entry *register_specifier; | |
266 | } vex_prefix; | |
267 | ||
252b5132 | 268 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 269 | i386_insn. */ |
252b5132 | 270 | |
520dc8e8 AM |
271 | union i386_op |
272 | { | |
273 | expressionS *disps; | |
274 | expressionS *imms; | |
275 | const reg_entry *regs; | |
276 | }; | |
277 | ||
a65babc9 L |
278 | enum i386_error |
279 | { | |
86e026a4 | 280 | operand_size_mismatch, |
a65babc9 L |
281 | operand_type_mismatch, |
282 | register_type_mismatch, | |
283 | number_of_operands_mismatch, | |
284 | invalid_instruction_suffix, | |
285 | bad_imm4, | |
a65babc9 L |
286 | unsupported_with_intel_mnemonic, |
287 | unsupported_syntax, | |
6c30d220 L |
288 | unsupported, |
289 | invalid_vsib_address, | |
7bab8ab5 | 290 | invalid_vector_register_set, |
43234a1e L |
291 | unsupported_vector_index_register, |
292 | unsupported_broadcast, | |
43234a1e L |
293 | broadcast_needed, |
294 | unsupported_masking, | |
295 | mask_not_on_destination, | |
296 | no_default_mask, | |
297 | unsupported_rc_sae, | |
298 | rc_sae_operand_not_last_imm, | |
299 | invalid_register_operand, | |
a65babc9 L |
300 | }; |
301 | ||
252b5132 RH |
302 | struct _i386_insn |
303 | { | |
47926f60 | 304 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 305 | insn_template tm; |
252b5132 | 306 | |
7d5e4556 L |
307 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
308 | or qword, if given. */ | |
252b5132 RH |
309 | char suffix; |
310 | ||
47926f60 | 311 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
312 | unsigned int operands; |
313 | ||
314 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
315 | of given register, displacement, memory operands and immediate | |
47926f60 | 316 | operands. */ |
252b5132 RH |
317 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
318 | ||
319 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 320 | use OP[i] for the corresponding operand. */ |
40fb9820 | 321 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 322 | |
520dc8e8 AM |
323 | /* Displacement expression, immediate expression, or register for each |
324 | operand. */ | |
325 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 326 | |
3e73aa7c JH |
327 | /* Flags for operands. */ |
328 | unsigned int flags[MAX_OPERANDS]; | |
329 | #define Operand_PCrel 1 | |
c48dadc9 | 330 | #define Operand_Mem 2 |
3e73aa7c | 331 | |
252b5132 | 332 | /* Relocation type for operand */ |
f86103b7 | 333 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 334 | |
252b5132 RH |
335 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
336 | the base index byte below. */ | |
337 | const reg_entry *base_reg; | |
338 | const reg_entry *index_reg; | |
339 | unsigned int log2_scale_factor; | |
340 | ||
341 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 342 | explicit segment overrides are given. */ |
ce8a8b2f | 343 | const seg_entry *seg[2]; |
252b5132 | 344 | |
8325cc63 JB |
345 | /* Copied first memory operand string, for re-checking. */ |
346 | char *memop1_string; | |
347 | ||
252b5132 RH |
348 | /* PREFIX holds all the given prefix opcodes (usually null). |
349 | PREFIXES is the number of prefix opcodes. */ | |
350 | unsigned int prefixes; | |
351 | unsigned char prefix[MAX_PREFIXES]; | |
352 | ||
50128d0c JB |
353 | /* Register is in low 3 bits of opcode. */ |
354 | bfd_boolean short_form; | |
355 | ||
6f2f06be JB |
356 | /* The operand to a branch insn indicates an absolute branch. */ |
357 | bfd_boolean jumpabsolute; | |
358 | ||
b4a3a7b4 L |
359 | /* Has MMX register operands. */ |
360 | bfd_boolean has_regmmx; | |
361 | ||
362 | /* Has XMM register operands. */ | |
363 | bfd_boolean has_regxmm; | |
364 | ||
365 | /* Has YMM register operands. */ | |
366 | bfd_boolean has_regymm; | |
367 | ||
368 | /* Has ZMM register operands. */ | |
369 | bfd_boolean has_regzmm; | |
370 | ||
e379e5f3 L |
371 | /* Has GOTPC or TLS relocation. */ |
372 | bfd_boolean has_gotpc_tls_reloc; | |
373 | ||
252b5132 | 374 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 375 | addressing modes of this insn are encoded. */ |
252b5132 | 376 | modrm_byte rm; |
3e73aa7c | 377 | rex_byte rex; |
43234a1e | 378 | rex_byte vrex; |
252b5132 | 379 | sib_byte sib; |
c0f3af97 | 380 | vex_prefix vex; |
b6169b20 | 381 | |
43234a1e L |
382 | /* Masking attributes. */ |
383 | struct Mask_Operation *mask; | |
384 | ||
385 | /* Rounding control and SAE attributes. */ | |
386 | struct RC_Operation *rounding; | |
387 | ||
388 | /* Broadcasting attributes. */ | |
389 | struct Broadcast_Operation *broadcast; | |
390 | ||
391 | /* Compressed disp8*N attribute. */ | |
392 | unsigned int memshift; | |
393 | ||
86fa6981 L |
394 | /* Prefer load or store in encoding. */ |
395 | enum | |
396 | { | |
397 | dir_encoding_default = 0, | |
398 | dir_encoding_load, | |
64c49ab3 JB |
399 | dir_encoding_store, |
400 | dir_encoding_swap | |
86fa6981 | 401 | } dir_encoding; |
891edac4 | 402 | |
a501d77e L |
403 | /* Prefer 8bit or 32bit displacement in encoding. */ |
404 | enum | |
405 | { | |
406 | disp_encoding_default = 0, | |
407 | disp_encoding_8bit, | |
408 | disp_encoding_32bit | |
409 | } disp_encoding; | |
f8a5c266 | 410 | |
6b6b6807 L |
411 | /* Prefer the REX byte in encoding. */ |
412 | bfd_boolean rex_encoding; | |
413 | ||
b6f8c7c4 L |
414 | /* Disable instruction size optimization. */ |
415 | bfd_boolean no_optimize; | |
416 | ||
86fa6981 L |
417 | /* How to encode vector instructions. */ |
418 | enum | |
419 | { | |
420 | vex_encoding_default = 0, | |
42e04b36 | 421 | vex_encoding_vex, |
86fa6981 L |
422 | vex_encoding_vex3, |
423 | vex_encoding_evex | |
424 | } vec_encoding; | |
425 | ||
d5de92cf L |
426 | /* REP prefix. */ |
427 | const char *rep_prefix; | |
428 | ||
165de32a L |
429 | /* HLE prefix. */ |
430 | const char *hle_prefix; | |
42164a71 | 431 | |
7e8b059b L |
432 | /* Have BND prefix. */ |
433 | const char *bnd_prefix; | |
434 | ||
04ef582a L |
435 | /* Have NOTRACK prefix. */ |
436 | const char *notrack_prefix; | |
437 | ||
891edac4 | 438 | /* Error message. */ |
a65babc9 | 439 | enum i386_error error; |
252b5132 RH |
440 | }; |
441 | ||
442 | typedef struct _i386_insn i386_insn; | |
443 | ||
43234a1e L |
444 | /* Link RC type with corresponding string, that'll be looked for in |
445 | asm. */ | |
446 | struct RC_name | |
447 | { | |
448 | enum rc_type type; | |
449 | const char *name; | |
450 | unsigned int len; | |
451 | }; | |
452 | ||
453 | static const struct RC_name RC_NamesTable[] = | |
454 | { | |
455 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
456 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
457 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
458 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
459 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
460 | }; | |
461 | ||
252b5132 RH |
462 | /* List of chars besides those in app.c:symbol_chars that can start an |
463 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 464 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 465 | #ifdef LEX_AT |
32137342 NC |
466 | "@" |
467 | #endif | |
468 | #ifdef LEX_QM | |
469 | "?" | |
252b5132 | 470 | #endif |
32137342 | 471 | ; |
252b5132 | 472 | |
29b0f896 AM |
473 | #if (defined (TE_I386AIX) \ |
474 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 475 | && !defined (TE_GNU) \ |
29b0f896 | 476 | && !defined (TE_LINUX) \ |
8d63c93e | 477 | && !defined (TE_NACL) \ |
29b0f896 | 478 | && !defined (TE_FreeBSD) \ |
5b806d27 | 479 | && !defined (TE_DragonFly) \ |
29b0f896 | 480 | && !defined (TE_NetBSD))) |
252b5132 | 481 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
482 | pre-processor is disabled, these aren't very useful. The option |
483 | --divide will remove '/' from this list. */ | |
484 | const char *i386_comment_chars = "#/"; | |
485 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 486 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 487 | |
b3b91714 AM |
488 | #else |
489 | const char *i386_comment_chars = "#"; | |
490 | #define PREFIX_SEPARATOR '/' | |
491 | #endif | |
492 | ||
252b5132 RH |
493 | /* This array holds the chars that only start a comment at the beginning of |
494 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
495 | .line and .file directives will appear in the pre-processed output. |
496 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 497 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
498 | #NO_APP at the beginning of its output. |
499 | Also note that comments started like this one will always work if | |
252b5132 | 500 | '/' isn't otherwise defined. */ |
b3b91714 | 501 | const char line_comment_chars[] = "#/"; |
252b5132 | 502 | |
63a0b638 | 503 | const char line_separator_chars[] = ";"; |
252b5132 | 504 | |
ce8a8b2f AM |
505 | /* Chars that can be used to separate mant from exp in floating point |
506 | nums. */ | |
252b5132 RH |
507 | const char EXP_CHARS[] = "eE"; |
508 | ||
ce8a8b2f AM |
509 | /* Chars that mean this number is a floating point constant |
510 | As in 0f12.456 | |
511 | or 0d1.2345e12. */ | |
252b5132 RH |
512 | const char FLT_CHARS[] = "fFdDxX"; |
513 | ||
ce8a8b2f | 514 | /* Tables for lexical analysis. */ |
252b5132 RH |
515 | static char mnemonic_chars[256]; |
516 | static char register_chars[256]; | |
517 | static char operand_chars[256]; | |
518 | static char identifier_chars[256]; | |
519 | static char digit_chars[256]; | |
520 | ||
ce8a8b2f | 521 | /* Lexical macros. */ |
252b5132 RH |
522 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
523 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
524 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
525 | #define is_space_char(x) ((x) == ' ') | |
526 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
527 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
528 | ||
0234cb7c | 529 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
530 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
531 | ||
532 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
533 | effect this we maintain a stack of saved characters that we've smashed | |
534 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 535 | assembler instruction). */ |
252b5132 | 536 | static char save_stack[32]; |
ce8a8b2f | 537 | static char *save_stack_p; |
252b5132 RH |
538 | #define END_STRING_AND_SAVE(s) \ |
539 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
540 | #define RESTORE_END_STRING(s) \ | |
541 | do { *(s) = *--save_stack_p; } while (0) | |
542 | ||
47926f60 | 543 | /* The instruction we're assembling. */ |
252b5132 RH |
544 | static i386_insn i; |
545 | ||
546 | /* Possible templates for current insn. */ | |
547 | static const templates *current_templates; | |
548 | ||
31b2323c L |
549 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
550 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
551 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 552 | |
47926f60 | 553 | /* Current operand we are working on. */ |
ee86248c | 554 | static int this_operand = -1; |
252b5132 | 555 | |
3e73aa7c JH |
556 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
557 | these. */ | |
558 | ||
559 | enum flag_code { | |
560 | CODE_32BIT, | |
561 | CODE_16BIT, | |
562 | CODE_64BIT }; | |
563 | ||
564 | static enum flag_code flag_code; | |
4fa24527 | 565 | static unsigned int object_64bit; |
862be3fb | 566 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 567 | static int use_rela_relocations = 0; |
e379e5f3 L |
568 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
569 | static const char *tls_get_addr; | |
3e73aa7c | 570 | |
7af8ed2d NC |
571 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
572 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
573 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
574 | ||
351f65ca L |
575 | /* The ELF ABI to use. */ |
576 | enum x86_elf_abi | |
577 | { | |
578 | I386_ABI, | |
7f56bc95 L |
579 | X86_64_ABI, |
580 | X86_64_X32_ABI | |
351f65ca L |
581 | }; |
582 | ||
583 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 584 | #endif |
351f65ca | 585 | |
167ad85b TG |
586 | #if defined (TE_PE) || defined (TE_PEP) |
587 | /* Use big object file format. */ | |
588 | static int use_big_obj = 0; | |
589 | #endif | |
590 | ||
8dcea932 L |
591 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
592 | /* 1 if generating code for a shared library. */ | |
593 | static int shared = 0; | |
594 | #endif | |
595 | ||
47926f60 KH |
596 | /* 1 for intel syntax, |
597 | 0 if att syntax. */ | |
598 | static int intel_syntax = 0; | |
252b5132 | 599 | |
4b5aaf5f L |
600 | static enum x86_64_isa |
601 | { | |
602 | amd64 = 1, /* AMD64 ISA. */ | |
603 | intel64 /* Intel64 ISA. */ | |
604 | } isa64; | |
e89c5eaa | 605 | |
1efbbeb4 L |
606 | /* 1 for intel mnemonic, |
607 | 0 if att mnemonic. */ | |
608 | static int intel_mnemonic = !SYSV386_COMPAT; | |
609 | ||
a60de03c JB |
610 | /* 1 if pseudo registers are permitted. */ |
611 | static int allow_pseudo_reg = 0; | |
612 | ||
47926f60 KH |
613 | /* 1 if register prefix % not required. */ |
614 | static int allow_naked_reg = 0; | |
252b5132 | 615 | |
33eaf5de | 616 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
617 | instructions supporting it, even if this prefix wasn't specified |
618 | explicitly. */ | |
619 | static int add_bnd_prefix = 0; | |
620 | ||
ba104c83 | 621 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
622 | static int allow_index_reg = 0; |
623 | ||
d022bddd IT |
624 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
625 | specified explicitly. */ | |
626 | static int omit_lock_prefix = 0; | |
627 | ||
e4e00185 AS |
628 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
629 | "lock addl $0, (%{re}sp)". */ | |
630 | static int avoid_fence = 0; | |
631 | ||
e379e5f3 L |
632 | /* Type of the previous instruction. */ |
633 | static struct | |
634 | { | |
635 | segT seg; | |
636 | const char *file; | |
637 | const char *name; | |
638 | unsigned int line; | |
639 | enum last_insn_kind | |
640 | { | |
641 | last_insn_other = 0, | |
642 | last_insn_directive, | |
643 | last_insn_prefix | |
644 | } kind; | |
645 | } last_insn; | |
646 | ||
0cb4071e L |
647 | /* 1 if the assembler should generate relax relocations. */ |
648 | ||
649 | static int generate_relax_relocations | |
650 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
651 | ||
7bab8ab5 | 652 | static enum check_kind |
daf50ae7 | 653 | { |
7bab8ab5 JB |
654 | check_none = 0, |
655 | check_warning, | |
656 | check_error | |
daf50ae7 | 657 | } |
7bab8ab5 | 658 | sse_check, operand_check = check_warning; |
daf50ae7 | 659 | |
e379e5f3 L |
660 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
661 | static int align_branch_power = 0; | |
662 | ||
663 | /* Types of branches to align. */ | |
664 | enum align_branch_kind | |
665 | { | |
666 | align_branch_none = 0, | |
667 | align_branch_jcc = 1, | |
668 | align_branch_fused = 2, | |
669 | align_branch_jmp = 3, | |
670 | align_branch_call = 4, | |
671 | align_branch_indirect = 5, | |
672 | align_branch_ret = 6 | |
673 | }; | |
674 | ||
675 | /* Type bits of branches to align. */ | |
676 | enum align_branch_bit | |
677 | { | |
678 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
679 | align_branch_fused_bit = 1 << align_branch_fused, | |
680 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
681 | align_branch_call_bit = 1 << align_branch_call, | |
682 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
683 | align_branch_ret_bit = 1 << align_branch_ret | |
684 | }; | |
685 | ||
686 | static unsigned int align_branch = (align_branch_jcc_bit | |
687 | | align_branch_fused_bit | |
688 | | align_branch_jmp_bit); | |
689 | ||
79d72f45 HL |
690 | /* Types of condition jump used by macro-fusion. */ |
691 | enum mf_jcc_kind | |
692 | { | |
693 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
694 | mf_jcc_jc, /* base opcode 0x72 */ | |
695 | mf_jcc_je, /* base opcode 0x74 */ | |
696 | mf_jcc_jna, /* base opcode 0x76 */ | |
697 | mf_jcc_js, /* base opcode 0x78 */ | |
698 | mf_jcc_jp, /* base opcode 0x7a */ | |
699 | mf_jcc_jl, /* base opcode 0x7c */ | |
700 | mf_jcc_jle, /* base opcode 0x7e */ | |
701 | }; | |
702 | ||
703 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
704 | enum mf_cmp_kind | |
705 | { | |
706 | mf_cmp_test_and, /* test/cmp */ | |
707 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
708 | mf_cmp_incdec /* inc/dec */ | |
709 | }; | |
710 | ||
e379e5f3 L |
711 | /* The maximum padding size for fused jcc. CMP like instruction can |
712 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
713 | prefixes. */ | |
714 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
715 | ||
716 | /* The maximum number of prefixes added for an instruction. */ | |
717 | static unsigned int align_branch_prefix_size = 5; | |
718 | ||
b6f8c7c4 L |
719 | /* Optimization: |
720 | 1. Clear the REX_W bit with register operand if possible. | |
721 | 2. Above plus use 128bit vector instruction to clear the full vector | |
722 | register. | |
723 | */ | |
724 | static int optimize = 0; | |
725 | ||
726 | /* Optimization: | |
727 | 1. Clear the REX_W bit with register operand if possible. | |
728 | 2. Above plus use 128bit vector instruction to clear the full vector | |
729 | register. | |
730 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
731 | "testb $imm7,%r8". | |
732 | */ | |
733 | static int optimize_for_space = 0; | |
734 | ||
2ca3ace5 L |
735 | /* Register prefix used for error message. */ |
736 | static const char *register_prefix = "%"; | |
737 | ||
47926f60 KH |
738 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
739 | leave, push, and pop instructions so that gcc has the same stack | |
740 | frame as in 32 bit mode. */ | |
741 | static char stackop_size = '\0'; | |
eecb386c | 742 | |
12b55ccc L |
743 | /* Non-zero to optimize code alignment. */ |
744 | int optimize_align_code = 1; | |
745 | ||
47926f60 KH |
746 | /* Non-zero to quieten some warnings. */ |
747 | static int quiet_warnings = 0; | |
a38cf1db | 748 | |
47926f60 KH |
749 | /* CPU name. */ |
750 | static const char *cpu_arch_name = NULL; | |
6305a203 | 751 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 752 | |
47926f60 | 753 | /* CPU feature flags. */ |
40fb9820 L |
754 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
755 | ||
ccc9c027 L |
756 | /* If we have selected a cpu we are generating instructions for. */ |
757 | static int cpu_arch_tune_set = 0; | |
758 | ||
9103f4f4 | 759 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 760 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
761 | |
762 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 763 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 764 | |
ccc9c027 | 765 | /* CPU instruction set architecture used. */ |
fbf3f584 | 766 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 767 | |
9103f4f4 | 768 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 769 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 770 | |
fddf5b5b AM |
771 | /* If set, conditional jumps are not automatically promoted to handle |
772 | larger than a byte offset. */ | |
773 | static unsigned int no_cond_jump_promotion = 0; | |
774 | ||
c0f3af97 L |
775 | /* Encode SSE instructions with VEX prefix. */ |
776 | static unsigned int sse2avx; | |
777 | ||
539f890d L |
778 | /* Encode scalar AVX instructions with specific vector length. */ |
779 | static enum | |
780 | { | |
781 | vex128 = 0, | |
782 | vex256 | |
783 | } avxscalar; | |
784 | ||
03751133 L |
785 | /* Encode VEX WIG instructions with specific vex.w. */ |
786 | static enum | |
787 | { | |
788 | vexw0 = 0, | |
789 | vexw1 | |
790 | } vexwig; | |
791 | ||
43234a1e L |
792 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
793 | static enum | |
794 | { | |
795 | evexl128 = 0, | |
796 | evexl256, | |
797 | evexl512 | |
798 | } evexlig; | |
799 | ||
800 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
801 | static enum | |
802 | { | |
803 | evexw0 = 0, | |
804 | evexw1 | |
805 | } evexwig; | |
806 | ||
d3d3c6db IT |
807 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
808 | static enum rc_type evexrcig = rne; | |
809 | ||
29b0f896 | 810 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 811 | static symbolS *GOT_symbol; |
29b0f896 | 812 | |
a4447b93 RH |
813 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
814 | unsigned int x86_dwarf2_return_column; | |
815 | ||
816 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
817 | int x86_cie_data_alignment; | |
818 | ||
252b5132 | 819 | /* Interface to relax_segment. |
fddf5b5b AM |
820 | There are 3 major relax states for 386 jump insns because the |
821 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
822 | figuring out what sort of jump to choose to reach a given label. |
823 | ||
824 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
825 | branches which are handled by md_estimate_size_before_relax() and | |
826 | i386_generic_table_relax_frag(). */ | |
252b5132 | 827 | |
47926f60 | 828 | /* Types. */ |
93c2a809 AM |
829 | #define UNCOND_JUMP 0 |
830 | #define COND_JUMP 1 | |
831 | #define COND_JUMP86 2 | |
e379e5f3 L |
832 | #define BRANCH_PADDING 3 |
833 | #define BRANCH_PREFIX 4 | |
834 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 835 | |
47926f60 | 836 | /* Sizes. */ |
252b5132 RH |
837 | #define CODE16 1 |
838 | #define SMALL 0 | |
29b0f896 | 839 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 840 | #define BIG 2 |
29b0f896 | 841 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
842 | |
843 | #ifndef INLINE | |
844 | #ifdef __GNUC__ | |
845 | #define INLINE __inline__ | |
846 | #else | |
847 | #define INLINE | |
848 | #endif | |
849 | #endif | |
850 | ||
fddf5b5b AM |
851 | #define ENCODE_RELAX_STATE(type, size) \ |
852 | ((relax_substateT) (((type) << 2) | (size))) | |
853 | #define TYPE_FROM_RELAX_STATE(s) \ | |
854 | ((s) >> 2) | |
855 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
856 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
857 | |
858 | /* This table is used by relax_frag to promote short jumps to long | |
859 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
860 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
861 | don't allow a short jump in a 32 bit code segment to be promoted to | |
862 | a 16 bit offset jump because it's slower (requires data size | |
863 | prefix), and doesn't work, unless the destination is in the bottom | |
864 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
865 | ||
866 | const relax_typeS md_relax_table[] = | |
867 | { | |
24eab124 AM |
868 | /* The fields are: |
869 | 1) most positive reach of this state, | |
870 | 2) most negative reach of this state, | |
93c2a809 | 871 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 872 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 873 | |
fddf5b5b | 874 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
875 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
876 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
877 | /* dword jmp adds 4 bytes to frag: | |
878 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 879 | {0, 0, 4, 0}, |
93c2a809 AM |
880 | /* word jmp adds 2 byte2 to frag: |
881 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
882 | {0, 0, 2, 0}, |
883 | ||
93c2a809 AM |
884 | /* COND_JUMP states. */ |
885 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
886 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
887 | /* dword conditionals adds 5 bytes to frag: | |
888 | 1 extra opcode byte, 4 displacement bytes. */ | |
889 | {0, 0, 5, 0}, | |
fddf5b5b | 890 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
891 | 1 extra opcode byte, 2 displacement bytes. */ |
892 | {0, 0, 3, 0}, | |
893 | ||
894 | /* COND_JUMP86 states. */ | |
895 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
896 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
897 | /* dword conditionals adds 5 bytes to frag: | |
898 | 1 extra opcode byte, 4 displacement bytes. */ | |
899 | {0, 0, 5, 0}, | |
900 | /* word conditionals add 4 bytes to frag: | |
901 | 1 displacement byte and a 3 byte long branch insn. */ | |
902 | {0, 0, 4, 0} | |
252b5132 RH |
903 | }; |
904 | ||
9103f4f4 L |
905 | static const arch_entry cpu_arch[] = |
906 | { | |
89507696 JB |
907 | /* Do not replace the first two entries - i386_target_format() |
908 | relies on them being there in this order. */ | |
8a2c8fef | 909 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 910 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 911 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 912 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 913 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 915 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 917 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 919 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 920 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 922 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 923 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 924 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 925 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 926 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 927 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 928 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 929 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 930 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 931 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 932 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 933 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 934 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 935 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 936 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 937 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 938 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 939 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 940 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 941 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 942 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 943 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 944 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 945 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 946 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 947 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 948 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 949 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 950 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 951 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 952 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 953 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 954 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 955 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 956 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 957 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 958 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 959 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 960 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 961 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 962 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 963 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 964 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 965 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 966 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 967 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 968 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 969 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 970 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 971 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 972 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 973 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 974 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 975 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 976 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 977 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 978 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 979 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 980 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
981 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
982 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 983 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 984 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 985 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 986 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 987 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 988 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 989 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 990 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 991 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 992 | CPU_387_FLAGS, 0 }, |
1848e567 L |
993 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
994 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
995 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
996 | CPU_CMOV_FLAGS, 0 }, | |
997 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
998 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 999 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1000 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 1001 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 1002 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 1003 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1004 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 1005 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1006 | CPU_SSE3_FLAGS, 0 }, |
af5c13b0 L |
1007 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
1008 | CPU_SSE4A_FLAGS, 0 }, | |
8a2c8fef | 1009 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1010 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 1011 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1012 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 1013 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1014 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1015 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1016 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1017 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1018 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 1019 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1020 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 1021 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 1022 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 1023 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1024 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 1025 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 1026 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 1027 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 1028 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 1029 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 1030 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 1031 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1032 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 1033 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 1034 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 1035 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1036 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 1037 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 1038 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 1039 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1040 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 1041 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 1042 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 1043 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1044 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 1045 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 1046 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 1047 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 1048 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 1049 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 1050 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 1051 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1052 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 1053 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1054 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 1055 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 1056 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 1057 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1058 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 1059 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 1060 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 1061 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1062 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 1063 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1064 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 1065 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1066 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 1067 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1068 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 1069 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1070 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 1071 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 1072 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 1073 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 1074 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 1075 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 1076 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 1077 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1078 | CPU_LZCNT_FLAGS, 0 }, |
272a84b1 L |
1079 | { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN, |
1080 | CPU_POPCNT_FLAGS, 0 }, | |
42164a71 | 1081 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 1082 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 1083 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1084 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 1085 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1086 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 1087 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 1088 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 1089 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1090 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 1091 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 1092 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 1093 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1094 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1095 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1096 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1097 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1098 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1099 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1100 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1101 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1102 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1103 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1104 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1105 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1106 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1107 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1108 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1109 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1110 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1111 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1112 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1113 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1114 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1115 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1116 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1117 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1118 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1119 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1120 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1121 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1122 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1123 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1124 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1125 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1126 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1127 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1128 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1129 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1130 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1131 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1132 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1133 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1134 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1135 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1136 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1137 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1138 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1139 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1140 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1141 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1142 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1143 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1144 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1145 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1146 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1147 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1148 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1149 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1150 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1151 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1152 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1153 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1154 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1155 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1156 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1157 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1158 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1159 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1160 | CPU_IBT_FLAGS, 0 }, | |
1161 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1162 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1163 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1164 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1165 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1166 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1167 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1168 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1169 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1170 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1171 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1172 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1173 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1174 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1175 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1176 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1177 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1178 | CPU_MOVDIRI_FLAGS, 0 }, | |
1179 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1180 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1181 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1182 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1183 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1184 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
dd455cf5 L |
1185 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1186 | CPU_ENQCMD_FLAGS, 0 }, | |
142861df JB |
1187 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1188 | CPU_RDPRU_FLAGS, 0 }, | |
1189 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1190 | CPU_MCOMMIT_FLAGS, 0 }, | |
a847e322 JB |
1191 | { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN, |
1192 | CPU_SEV_ES_FLAGS, 0 }, | |
293f5f65 L |
1193 | }; |
1194 | ||
1195 | static const noarch_entry cpu_noarch[] = | |
1196 | { | |
1197 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1198 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1199 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1200 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1201 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1202 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1203 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1204 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1205 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1206 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
af5c13b0 | 1207 | { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS }, |
1848e567 L |
1208 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, |
1209 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1210 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
af5c13b0 | 1211 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, |
293f5f65 | 1212 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1213 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1214 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1215 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1216 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1217 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1218 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1219 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1220 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1221 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1222 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1223 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1224 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1225 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1226 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1227 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1228 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1229 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1230 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1231 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1232 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1233 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
9186c494 | 1234 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS }, |
dd455cf5 | 1235 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
e413e4e9 AM |
1236 | }; |
1237 | ||
704209c0 | 1238 | #ifdef I386COFF |
a6c24e68 NC |
1239 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1240 | is allowed to be optional. */ | |
1241 | ||
1242 | static symbolS * | |
1243 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1244 | { | |
1245 | addressT align = 0; | |
1246 | ||
1247 | SKIP_WHITESPACE (); | |
1248 | ||
7ab9ffdd | 1249 | if (needs_align |
a6c24e68 NC |
1250 | && *input_line_pointer == ',') |
1251 | { | |
1252 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1253 | |
a6c24e68 NC |
1254 | if (align == (addressT) -1) |
1255 | return NULL; | |
1256 | } | |
1257 | else | |
1258 | { | |
1259 | if (size >= 8) | |
1260 | align = 3; | |
1261 | else if (size >= 4) | |
1262 | align = 2; | |
1263 | else if (size >= 2) | |
1264 | align = 1; | |
1265 | else | |
1266 | align = 0; | |
1267 | } | |
1268 | ||
1269 | bss_alloc (symbolP, size, align); | |
1270 | return symbolP; | |
1271 | } | |
1272 | ||
704209c0 | 1273 | static void |
a6c24e68 NC |
1274 | pe_lcomm (int needs_align) |
1275 | { | |
1276 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1277 | } | |
704209c0 | 1278 | #endif |
a6c24e68 | 1279 | |
29b0f896 AM |
1280 | const pseudo_typeS md_pseudo_table[] = |
1281 | { | |
1282 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1283 | {"align", s_align_bytes, 0}, | |
1284 | #else | |
1285 | {"align", s_align_ptwo, 0}, | |
1286 | #endif | |
1287 | {"arch", set_cpu_arch, 0}, | |
1288 | #ifndef I386COFF | |
1289 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1290 | #else |
1291 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1292 | #endif |
1293 | {"ffloat", float_cons, 'f'}, | |
1294 | {"dfloat", float_cons, 'd'}, | |
1295 | {"tfloat", float_cons, 'x'}, | |
1296 | {"value", cons, 2}, | |
d182319b | 1297 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1298 | {"noopt", s_ignore, 0}, |
1299 | {"optim", s_ignore, 0}, | |
1300 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1301 | {"code16", set_code_flag, CODE_16BIT}, | |
1302 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1303 | #ifdef BFD64 |
29b0f896 | 1304 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1305 | #endif |
29b0f896 AM |
1306 | {"intel_syntax", set_intel_syntax, 1}, |
1307 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1308 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1309 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1310 | {"allow_index_reg", set_allow_index_reg, 1}, |
1311 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1312 | {"sse_check", set_check, 0}, |
1313 | {"operand_check", set_check, 1}, | |
3b22753a L |
1314 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1315 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1316 | #else |
68d20676 | 1317 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1318 | {"loc", dwarf2_directive_loc, 0}, |
1319 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1320 | #endif |
6482c264 NC |
1321 | #ifdef TE_PE |
1322 | {"secrel32", pe_directive_secrel, 0}, | |
1323 | #endif | |
29b0f896 AM |
1324 | {0, 0, 0} |
1325 | }; | |
1326 | ||
1327 | /* For interface with expression (). */ | |
1328 | extern char *input_line_pointer; | |
1329 | ||
1330 | /* Hash table for instruction mnemonic lookup. */ | |
1331 | static struct hash_control *op_hash; | |
1332 | ||
1333 | /* Hash table for register lookup. */ | |
1334 | static struct hash_control *reg_hash; | |
1335 | \f | |
ce8a8b2f AM |
1336 | /* Various efficient no-op patterns for aligning code labels. |
1337 | Note: Don't try to assemble the instructions in the comments. | |
1338 | 0L and 0w are not legal. */ | |
62a02d25 L |
1339 | static const unsigned char f32_1[] = |
1340 | {0x90}; /* nop */ | |
1341 | static const unsigned char f32_2[] = | |
1342 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1343 | static const unsigned char f32_3[] = | |
1344 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1345 | static const unsigned char f32_4[] = | |
1346 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1347 | static const unsigned char f32_6[] = |
1348 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1349 | static const unsigned char f32_7[] = | |
1350 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1351 | static const unsigned char f16_3[] = |
3ae729d5 | 1352 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1353 | static const unsigned char f16_4[] = |
3ae729d5 L |
1354 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1355 | static const unsigned char jump_disp8[] = | |
1356 | {0xeb}; /* jmp disp8 */ | |
1357 | static const unsigned char jump32_disp32[] = | |
1358 | {0xe9}; /* jmp disp32 */ | |
1359 | static const unsigned char jump16_disp32[] = | |
1360 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1361 | /* 32-bit NOPs patterns. */ |
1362 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1363 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1364 | }; |
1365 | /* 16-bit NOPs patterns. */ | |
1366 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1367 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1368 | }; |
1369 | /* nopl (%[re]ax) */ | |
1370 | static const unsigned char alt_3[] = | |
1371 | {0x0f,0x1f,0x00}; | |
1372 | /* nopl 0(%[re]ax) */ | |
1373 | static const unsigned char alt_4[] = | |
1374 | {0x0f,0x1f,0x40,0x00}; | |
1375 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1376 | static const unsigned char alt_5[] = | |
1377 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1378 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1379 | static const unsigned char alt_6[] = | |
1380 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1381 | /* nopl 0L(%[re]ax) */ | |
1382 | static const unsigned char alt_7[] = | |
1383 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1384 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1385 | static const unsigned char alt_8[] = | |
1386 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1387 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1388 | static const unsigned char alt_9[] = | |
1389 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1390 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1391 | static const unsigned char alt_10[] = | |
1392 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1393 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1394 | static const unsigned char alt_11[] = | |
1395 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1396 | /* 32-bit and 64-bit NOPs patterns. */ |
1397 | static const unsigned char *const alt_patt[] = { | |
1398 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1399 | alt_9, alt_10, alt_11 |
62a02d25 L |
1400 | }; |
1401 | ||
1402 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1403 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1404 | ||
1405 | static void | |
1406 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1407 | int count, int max_single_nop_size) | |
1408 | ||
1409 | { | |
3ae729d5 L |
1410 | /* Place the longer NOP first. */ |
1411 | int last; | |
1412 | int offset; | |
3076e594 NC |
1413 | const unsigned char *nops; |
1414 | ||
1415 | if (max_single_nop_size < 1) | |
1416 | { | |
1417 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1418 | max_single_nop_size); | |
1419 | return; | |
1420 | } | |
1421 | ||
1422 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1423 | |
1424 | /* Use the smaller one if the requsted one isn't available. */ | |
1425 | if (nops == NULL) | |
62a02d25 | 1426 | { |
3ae729d5 L |
1427 | max_single_nop_size--; |
1428 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1429 | } |
1430 | ||
3ae729d5 L |
1431 | last = count % max_single_nop_size; |
1432 | ||
1433 | count -= last; | |
1434 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1435 | memcpy (where + offset, nops, max_single_nop_size); | |
1436 | ||
1437 | if (last) | |
1438 | { | |
1439 | nops = patt[last - 1]; | |
1440 | if (nops == NULL) | |
1441 | { | |
1442 | /* Use the smaller one plus one-byte NOP if the needed one | |
1443 | isn't available. */ | |
1444 | last--; | |
1445 | nops = patt[last - 1]; | |
1446 | memcpy (where + offset, nops, last); | |
1447 | where[offset + last] = *patt[0]; | |
1448 | } | |
1449 | else | |
1450 | memcpy (where + offset, nops, last); | |
1451 | } | |
62a02d25 L |
1452 | } |
1453 | ||
3ae729d5 L |
1454 | static INLINE int |
1455 | fits_in_imm7 (offsetT num) | |
1456 | { | |
1457 | return (num & 0x7f) == num; | |
1458 | } | |
1459 | ||
1460 | static INLINE int | |
1461 | fits_in_imm31 (offsetT num) | |
1462 | { | |
1463 | return (num & 0x7fffffff) == num; | |
1464 | } | |
62a02d25 L |
1465 | |
1466 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1467 | single NOP instruction LIMIT. */ | |
1468 | ||
1469 | void | |
3ae729d5 | 1470 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1471 | { |
3ae729d5 | 1472 | const unsigned char *const *patt = NULL; |
62a02d25 | 1473 | int max_single_nop_size; |
3ae729d5 L |
1474 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1475 | int max_number_of_nops; | |
62a02d25 | 1476 | |
3ae729d5 | 1477 | switch (fragP->fr_type) |
62a02d25 | 1478 | { |
3ae729d5 L |
1479 | case rs_fill_nop: |
1480 | case rs_align_code: | |
1481 | break; | |
e379e5f3 L |
1482 | case rs_machine_dependent: |
1483 | /* Allow NOP padding for jumps and calls. */ | |
1484 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1485 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1486 | break; | |
1487 | /* Fall through. */ | |
3ae729d5 | 1488 | default: |
62a02d25 L |
1489 | return; |
1490 | } | |
1491 | ||
ccc9c027 L |
1492 | /* We need to decide which NOP sequence to use for 32bit and |
1493 | 64bit. When -mtune= is used: | |
4eed87de | 1494 | |
76bc74dc L |
1495 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1496 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1497 | 2. For the rest, alt_patt will be used. |
1498 | ||
1499 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1500 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1501 | be used. |
ccc9c027 L |
1502 | |
1503 | When -march= or .arch is used, we can't use anything beyond | |
1504 | cpu_arch_isa_flags. */ | |
1505 | ||
1506 | if (flag_code == CODE_16BIT) | |
1507 | { | |
3ae729d5 L |
1508 | patt = f16_patt; |
1509 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1510 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1511 | max_number_of_nops = 2; | |
252b5132 | 1512 | } |
33fef721 | 1513 | else |
ccc9c027 | 1514 | { |
fbf3f584 | 1515 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1516 | { |
1517 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1518 | switch (cpu_arch_tune) | |
1519 | { | |
1520 | case PROCESSOR_UNKNOWN: | |
1521 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1522 | optimize with nops. */ |
1523 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1524 | patt = alt_patt; |
ccc9c027 L |
1525 | else |
1526 | patt = f32_patt; | |
1527 | break; | |
ccc9c027 L |
1528 | case PROCESSOR_PENTIUM4: |
1529 | case PROCESSOR_NOCONA: | |
ef05d495 | 1530 | case PROCESSOR_CORE: |
76bc74dc | 1531 | case PROCESSOR_CORE2: |
bd5295b2 | 1532 | case PROCESSOR_COREI7: |
3632d14b | 1533 | case PROCESSOR_L1OM: |
7a9068fe | 1534 | case PROCESSOR_K1OM: |
76bc74dc | 1535 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1536 | case PROCESSOR_K6: |
1537 | case PROCESSOR_ATHLON: | |
1538 | case PROCESSOR_K8: | |
4eed87de | 1539 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1540 | case PROCESSOR_BD: |
029f3522 | 1541 | case PROCESSOR_ZNVER: |
7b458c12 | 1542 | case PROCESSOR_BT: |
80b8656c | 1543 | patt = alt_patt; |
ccc9c027 | 1544 | break; |
76bc74dc | 1545 | case PROCESSOR_I386: |
ccc9c027 L |
1546 | case PROCESSOR_I486: |
1547 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1548 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1549 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1550 | case PROCESSOR_GENERIC32: |
1551 | patt = f32_patt; | |
1552 | break; | |
4eed87de | 1553 | } |
ccc9c027 L |
1554 | } |
1555 | else | |
1556 | { | |
fbf3f584 | 1557 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1558 | { |
1559 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1560 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1561 | PROCESSOR_UNKNOWN. */ |
1562 | abort (); | |
1563 | break; | |
1564 | ||
76bc74dc | 1565 | case PROCESSOR_I386: |
ccc9c027 L |
1566 | case PROCESSOR_I486: |
1567 | case PROCESSOR_PENTIUM: | |
81486035 | 1568 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1569 | case PROCESSOR_K6: |
1570 | case PROCESSOR_ATHLON: | |
1571 | case PROCESSOR_K8: | |
4eed87de | 1572 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1573 | case PROCESSOR_BD: |
029f3522 | 1574 | case PROCESSOR_ZNVER: |
7b458c12 | 1575 | case PROCESSOR_BT: |
ccc9c027 L |
1576 | case PROCESSOR_GENERIC32: |
1577 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1578 | with nops. */ |
1579 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1580 | patt = alt_patt; |
ccc9c027 L |
1581 | else |
1582 | patt = f32_patt; | |
1583 | break; | |
76bc74dc L |
1584 | case PROCESSOR_PENTIUMPRO: |
1585 | case PROCESSOR_PENTIUM4: | |
1586 | case PROCESSOR_NOCONA: | |
1587 | case PROCESSOR_CORE: | |
ef05d495 | 1588 | case PROCESSOR_CORE2: |
bd5295b2 | 1589 | case PROCESSOR_COREI7: |
3632d14b | 1590 | case PROCESSOR_L1OM: |
7a9068fe | 1591 | case PROCESSOR_K1OM: |
22109423 | 1592 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1593 | patt = alt_patt; |
ccc9c027 L |
1594 | else |
1595 | patt = f32_patt; | |
1596 | break; | |
1597 | case PROCESSOR_GENERIC64: | |
80b8656c | 1598 | patt = alt_patt; |
ccc9c027 | 1599 | break; |
4eed87de | 1600 | } |
ccc9c027 L |
1601 | } |
1602 | ||
76bc74dc L |
1603 | if (patt == f32_patt) |
1604 | { | |
3ae729d5 L |
1605 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1606 | /* Limit number of NOPs to 2 for older processors. */ | |
1607 | max_number_of_nops = 2; | |
76bc74dc L |
1608 | } |
1609 | else | |
1610 | { | |
3ae729d5 L |
1611 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1612 | /* Limit number of NOPs to 7 for newer processors. */ | |
1613 | max_number_of_nops = 7; | |
1614 | } | |
1615 | } | |
1616 | ||
1617 | if (limit == 0) | |
1618 | limit = max_single_nop_size; | |
1619 | ||
1620 | if (fragP->fr_type == rs_fill_nop) | |
1621 | { | |
1622 | /* Output NOPs for .nop directive. */ | |
1623 | if (limit > max_single_nop_size) | |
1624 | { | |
1625 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1626 | _("invalid single nop size: %d " | |
1627 | "(expect within [0, %d])"), | |
1628 | limit, max_single_nop_size); | |
1629 | return; | |
1630 | } | |
1631 | } | |
e379e5f3 | 1632 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1633 | fragP->fr_var = count; |
1634 | ||
1635 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1636 | { | |
1637 | /* Generate jump over NOPs. */ | |
1638 | offsetT disp = count - 2; | |
1639 | if (fits_in_imm7 (disp)) | |
1640 | { | |
1641 | /* Use "jmp disp8" if possible. */ | |
1642 | count = disp; | |
1643 | where[0] = jump_disp8[0]; | |
1644 | where[1] = count; | |
1645 | where += 2; | |
1646 | } | |
1647 | else | |
1648 | { | |
1649 | unsigned int size_of_jump; | |
1650 | ||
1651 | if (flag_code == CODE_16BIT) | |
1652 | { | |
1653 | where[0] = jump16_disp32[0]; | |
1654 | where[1] = jump16_disp32[1]; | |
1655 | size_of_jump = 2; | |
1656 | } | |
1657 | else | |
1658 | { | |
1659 | where[0] = jump32_disp32[0]; | |
1660 | size_of_jump = 1; | |
1661 | } | |
1662 | ||
1663 | count -= size_of_jump + 4; | |
1664 | if (!fits_in_imm31 (count)) | |
1665 | { | |
1666 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1667 | _("jump over nop padding out of range")); | |
1668 | return; | |
1669 | } | |
1670 | ||
1671 | md_number_to_chars (where + size_of_jump, count, 4); | |
1672 | where += size_of_jump + 4; | |
76bc74dc | 1673 | } |
ccc9c027 | 1674 | } |
3ae729d5 L |
1675 | |
1676 | /* Generate multiple NOPs. */ | |
1677 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1678 | } |
1679 | ||
c6fb90c8 | 1680 | static INLINE int |
0dfbf9d7 | 1681 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1682 | { |
0dfbf9d7 | 1683 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1684 | { |
1685 | case 3: | |
0dfbf9d7 | 1686 | if (x->array[2]) |
c6fb90c8 | 1687 | return 0; |
1a0670f3 | 1688 | /* Fall through. */ |
c6fb90c8 | 1689 | case 2: |
0dfbf9d7 | 1690 | if (x->array[1]) |
c6fb90c8 | 1691 | return 0; |
1a0670f3 | 1692 | /* Fall through. */ |
c6fb90c8 | 1693 | case 1: |
0dfbf9d7 | 1694 | return !x->array[0]; |
c6fb90c8 L |
1695 | default: |
1696 | abort (); | |
1697 | } | |
40fb9820 L |
1698 | } |
1699 | ||
c6fb90c8 | 1700 | static INLINE void |
0dfbf9d7 | 1701 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1702 | { |
0dfbf9d7 | 1703 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1704 | { |
1705 | case 3: | |
0dfbf9d7 | 1706 | x->array[2] = v; |
1a0670f3 | 1707 | /* Fall through. */ |
c6fb90c8 | 1708 | case 2: |
0dfbf9d7 | 1709 | x->array[1] = v; |
1a0670f3 | 1710 | /* Fall through. */ |
c6fb90c8 | 1711 | case 1: |
0dfbf9d7 | 1712 | x->array[0] = v; |
1a0670f3 | 1713 | /* Fall through. */ |
c6fb90c8 L |
1714 | break; |
1715 | default: | |
1716 | abort (); | |
1717 | } | |
bab6aec1 JB |
1718 | |
1719 | x->bitfield.class = ClassNone; | |
75e5731b | 1720 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1721 | } |
40fb9820 | 1722 | |
c6fb90c8 | 1723 | static INLINE int |
0dfbf9d7 L |
1724 | operand_type_equal (const union i386_operand_type *x, |
1725 | const union i386_operand_type *y) | |
c6fb90c8 | 1726 | { |
0dfbf9d7 | 1727 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1728 | { |
1729 | case 3: | |
0dfbf9d7 | 1730 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1731 | return 0; |
1a0670f3 | 1732 | /* Fall through. */ |
c6fb90c8 | 1733 | case 2: |
0dfbf9d7 | 1734 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1735 | return 0; |
1a0670f3 | 1736 | /* Fall through. */ |
c6fb90c8 | 1737 | case 1: |
0dfbf9d7 | 1738 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1739 | break; |
1740 | default: | |
1741 | abort (); | |
1742 | } | |
1743 | } | |
40fb9820 | 1744 | |
0dfbf9d7 L |
1745 | static INLINE int |
1746 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1747 | { | |
1748 | switch (ARRAY_SIZE(x->array)) | |
1749 | { | |
53467f57 IT |
1750 | case 4: |
1751 | if (x->array[3]) | |
1752 | return 0; | |
1753 | /* Fall through. */ | |
0dfbf9d7 L |
1754 | case 3: |
1755 | if (x->array[2]) | |
1756 | return 0; | |
1a0670f3 | 1757 | /* Fall through. */ |
0dfbf9d7 L |
1758 | case 2: |
1759 | if (x->array[1]) | |
1760 | return 0; | |
1a0670f3 | 1761 | /* Fall through. */ |
0dfbf9d7 L |
1762 | case 1: |
1763 | return !x->array[0]; | |
1764 | default: | |
1765 | abort (); | |
1766 | } | |
1767 | } | |
1768 | ||
0dfbf9d7 L |
1769 | static INLINE int |
1770 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1771 | const union i386_cpu_flags *y) | |
1772 | { | |
1773 | switch (ARRAY_SIZE(x->array)) | |
1774 | { | |
53467f57 IT |
1775 | case 4: |
1776 | if (x->array[3] != y->array[3]) | |
1777 | return 0; | |
1778 | /* Fall through. */ | |
0dfbf9d7 L |
1779 | case 3: |
1780 | if (x->array[2] != y->array[2]) | |
1781 | return 0; | |
1a0670f3 | 1782 | /* Fall through. */ |
0dfbf9d7 L |
1783 | case 2: |
1784 | if (x->array[1] != y->array[1]) | |
1785 | return 0; | |
1a0670f3 | 1786 | /* Fall through. */ |
0dfbf9d7 L |
1787 | case 1: |
1788 | return x->array[0] == y->array[0]; | |
1789 | break; | |
1790 | default: | |
1791 | abort (); | |
1792 | } | |
1793 | } | |
c6fb90c8 L |
1794 | |
1795 | static INLINE int | |
1796 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1797 | { | |
1798 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1799 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1800 | } |
1801 | ||
c6fb90c8 L |
1802 | static INLINE i386_cpu_flags |
1803 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1804 | { |
c6fb90c8 L |
1805 | switch (ARRAY_SIZE (x.array)) |
1806 | { | |
53467f57 IT |
1807 | case 4: |
1808 | x.array [3] &= y.array [3]; | |
1809 | /* Fall through. */ | |
c6fb90c8 L |
1810 | case 3: |
1811 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1812 | /* Fall through. */ |
c6fb90c8 L |
1813 | case 2: |
1814 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1815 | /* Fall through. */ |
c6fb90c8 L |
1816 | case 1: |
1817 | x.array [0] &= y.array [0]; | |
1818 | break; | |
1819 | default: | |
1820 | abort (); | |
1821 | } | |
1822 | return x; | |
1823 | } | |
40fb9820 | 1824 | |
c6fb90c8 L |
1825 | static INLINE i386_cpu_flags |
1826 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1827 | { |
c6fb90c8 | 1828 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1829 | { |
53467f57 IT |
1830 | case 4: |
1831 | x.array [3] |= y.array [3]; | |
1832 | /* Fall through. */ | |
c6fb90c8 L |
1833 | case 3: |
1834 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1835 | /* Fall through. */ |
c6fb90c8 L |
1836 | case 2: |
1837 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1838 | /* Fall through. */ |
c6fb90c8 L |
1839 | case 1: |
1840 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1841 | break; |
1842 | default: | |
1843 | abort (); | |
1844 | } | |
40fb9820 L |
1845 | return x; |
1846 | } | |
1847 | ||
309d3373 JB |
1848 | static INLINE i386_cpu_flags |
1849 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1850 | { | |
1851 | switch (ARRAY_SIZE (x.array)) | |
1852 | { | |
53467f57 IT |
1853 | case 4: |
1854 | x.array [3] &= ~y.array [3]; | |
1855 | /* Fall through. */ | |
309d3373 JB |
1856 | case 3: |
1857 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1858 | /* Fall through. */ |
309d3373 JB |
1859 | case 2: |
1860 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1861 | /* Fall through. */ |
309d3373 JB |
1862 | case 1: |
1863 | x.array [0] &= ~y.array [0]; | |
1864 | break; | |
1865 | default: | |
1866 | abort (); | |
1867 | } | |
1868 | return x; | |
1869 | } | |
1870 | ||
6c0946d0 JB |
1871 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1872 | ||
c0f3af97 L |
1873 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1874 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1875 | ||
c0f3af97 | 1876 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1877 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1878 | |
1879 | /* Return CPU flags match bits. */ | |
3629bb00 | 1880 | |
40fb9820 | 1881 | static int |
d3ce72d0 | 1882 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1883 | { |
c0f3af97 L |
1884 | i386_cpu_flags x = t->cpu_flags; |
1885 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1886 | |
1887 | x.bitfield.cpu64 = 0; | |
1888 | x.bitfield.cpuno64 = 0; | |
1889 | ||
0dfbf9d7 | 1890 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1891 | { |
1892 | /* This instruction is available on all archs. */ | |
db12e14e | 1893 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1894 | } |
3629bb00 L |
1895 | else |
1896 | { | |
c0f3af97 | 1897 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1898 | i386_cpu_flags cpu = cpu_arch_flags; |
1899 | ||
ab592e75 JB |
1900 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1901 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1902 | return match; | |
1903 | x.bitfield.cpuavx512vl = 0; | |
1904 | ||
3629bb00 | 1905 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1906 | if (!cpu_flags_all_zero (&cpu)) |
1907 | { | |
a5ff0eb2 L |
1908 | if (x.bitfield.cpuavx) |
1909 | { | |
929f69fa | 1910 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1911 | if (cpu.bitfield.cpuavx |
1912 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1913 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1914 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1915 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1916 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1917 | } |
929f69fa JB |
1918 | else if (x.bitfield.cpuavx512f) |
1919 | { | |
1920 | /* We need to check a few extra flags with AVX512F. */ | |
1921 | if (cpu.bitfield.cpuavx512f | |
1922 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1923 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1924 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1925 | match |= CPU_FLAGS_ARCH_MATCH; | |
1926 | } | |
a5ff0eb2 | 1927 | else |
db12e14e | 1928 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1929 | } |
3629bb00 | 1930 | } |
c0f3af97 | 1931 | return match; |
40fb9820 L |
1932 | } |
1933 | ||
c6fb90c8 L |
1934 | static INLINE i386_operand_type |
1935 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1936 | { |
bab6aec1 JB |
1937 | if (x.bitfield.class != y.bitfield.class) |
1938 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1939 | if (x.bitfield.instance != y.bitfield.instance) |
1940 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1941 | |
c6fb90c8 L |
1942 | switch (ARRAY_SIZE (x.array)) |
1943 | { | |
1944 | case 3: | |
1945 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1946 | /* Fall through. */ |
c6fb90c8 L |
1947 | case 2: |
1948 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1949 | /* Fall through. */ |
c6fb90c8 L |
1950 | case 1: |
1951 | x.array [0] &= y.array [0]; | |
1952 | break; | |
1953 | default: | |
1954 | abort (); | |
1955 | } | |
1956 | return x; | |
40fb9820 L |
1957 | } |
1958 | ||
73053c1f JB |
1959 | static INLINE i386_operand_type |
1960 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1961 | { | |
bab6aec1 | 1962 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1963 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1964 | |
73053c1f JB |
1965 | switch (ARRAY_SIZE (x.array)) |
1966 | { | |
1967 | case 3: | |
1968 | x.array [2] &= ~y.array [2]; | |
1969 | /* Fall through. */ | |
1970 | case 2: | |
1971 | x.array [1] &= ~y.array [1]; | |
1972 | /* Fall through. */ | |
1973 | case 1: | |
1974 | x.array [0] &= ~y.array [0]; | |
1975 | break; | |
1976 | default: | |
1977 | abort (); | |
1978 | } | |
1979 | return x; | |
1980 | } | |
1981 | ||
c6fb90c8 L |
1982 | static INLINE i386_operand_type |
1983 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1984 | { |
bab6aec1 JB |
1985 | gas_assert (x.bitfield.class == ClassNone || |
1986 | y.bitfield.class == ClassNone || | |
1987 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
1988 | gas_assert (x.bitfield.instance == InstanceNone || |
1989 | y.bitfield.instance == InstanceNone || | |
1990 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 1991 | |
c6fb90c8 | 1992 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1993 | { |
c6fb90c8 L |
1994 | case 3: |
1995 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1996 | /* Fall through. */ |
c6fb90c8 L |
1997 | case 2: |
1998 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1999 | /* Fall through. */ |
c6fb90c8 L |
2000 | case 1: |
2001 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2002 | break; |
2003 | default: | |
2004 | abort (); | |
2005 | } | |
c6fb90c8 L |
2006 | return x; |
2007 | } | |
40fb9820 | 2008 | |
c6fb90c8 L |
2009 | static INLINE i386_operand_type |
2010 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2011 | { | |
bab6aec1 | 2012 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2013 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2014 | |
c6fb90c8 L |
2015 | switch (ARRAY_SIZE (x.array)) |
2016 | { | |
2017 | case 3: | |
2018 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2019 | /* Fall through. */ |
c6fb90c8 L |
2020 | case 2: |
2021 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2022 | /* Fall through. */ |
c6fb90c8 L |
2023 | case 1: |
2024 | x.array [0] ^= y.array [0]; | |
2025 | break; | |
2026 | default: | |
2027 | abort (); | |
2028 | } | |
40fb9820 L |
2029 | return x; |
2030 | } | |
2031 | ||
40fb9820 L |
2032 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
2033 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
2034 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
2035 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
2036 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
2037 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 2038 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 2039 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
2040 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
2041 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
2042 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
2043 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
2044 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
2045 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
2046 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
2047 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
2048 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
2049 | ||
2050 | enum operand_type | |
2051 | { | |
2052 | reg, | |
40fb9820 L |
2053 | imm, |
2054 | disp, | |
2055 | anymem | |
2056 | }; | |
2057 | ||
c6fb90c8 | 2058 | static INLINE int |
40fb9820 L |
2059 | operand_type_check (i386_operand_type t, enum operand_type c) |
2060 | { | |
2061 | switch (c) | |
2062 | { | |
2063 | case reg: | |
bab6aec1 | 2064 | return t.bitfield.class == Reg; |
40fb9820 | 2065 | |
40fb9820 L |
2066 | case imm: |
2067 | return (t.bitfield.imm8 | |
2068 | || t.bitfield.imm8s | |
2069 | || t.bitfield.imm16 | |
2070 | || t.bitfield.imm32 | |
2071 | || t.bitfield.imm32s | |
2072 | || t.bitfield.imm64); | |
2073 | ||
2074 | case disp: | |
2075 | return (t.bitfield.disp8 | |
2076 | || t.bitfield.disp16 | |
2077 | || t.bitfield.disp32 | |
2078 | || t.bitfield.disp32s | |
2079 | || t.bitfield.disp64); | |
2080 | ||
2081 | case anymem: | |
2082 | return (t.bitfield.disp8 | |
2083 | || t.bitfield.disp16 | |
2084 | || t.bitfield.disp32 | |
2085 | || t.bitfield.disp32s | |
2086 | || t.bitfield.disp64 | |
2087 | || t.bitfield.baseindex); | |
2088 | ||
2089 | default: | |
2090 | abort (); | |
2091 | } | |
2cfe26b6 AM |
2092 | |
2093 | return 0; | |
40fb9820 L |
2094 | } |
2095 | ||
7a54636a L |
2096 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2097 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2098 | |
2099 | static INLINE int | |
7a54636a L |
2100 | match_operand_size (const insn_template *t, unsigned int wanted, |
2101 | unsigned int given) | |
5c07affc | 2102 | { |
3ac21baa JB |
2103 | return !((i.types[given].bitfield.byte |
2104 | && !t->operand_types[wanted].bitfield.byte) | |
2105 | || (i.types[given].bitfield.word | |
2106 | && !t->operand_types[wanted].bitfield.word) | |
2107 | || (i.types[given].bitfield.dword | |
2108 | && !t->operand_types[wanted].bitfield.dword) | |
2109 | || (i.types[given].bitfield.qword | |
2110 | && !t->operand_types[wanted].bitfield.qword) | |
2111 | || (i.types[given].bitfield.tbyte | |
2112 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2113 | } |
2114 | ||
dd40ce22 L |
2115 | /* Return 1 if there is no conflict in SIMD register between operand |
2116 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2117 | |
2118 | static INLINE int | |
dd40ce22 L |
2119 | match_simd_size (const insn_template *t, unsigned int wanted, |
2120 | unsigned int given) | |
1b54b8d7 | 2121 | { |
3ac21baa JB |
2122 | return !((i.types[given].bitfield.xmmword |
2123 | && !t->operand_types[wanted].bitfield.xmmword) | |
2124 | || (i.types[given].bitfield.ymmword | |
2125 | && !t->operand_types[wanted].bitfield.ymmword) | |
2126 | || (i.types[given].bitfield.zmmword | |
2127 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
2128 | } |
2129 | ||
7a54636a L |
2130 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2131 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2132 | |
2133 | static INLINE int | |
dd40ce22 L |
2134 | match_mem_size (const insn_template *t, unsigned int wanted, |
2135 | unsigned int given) | |
5c07affc | 2136 | { |
7a54636a | 2137 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2138 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 2139 | && !i.broadcast |
3ac21baa JB |
2140 | && !t->operand_types[wanted].bitfield.unspecified) |
2141 | || (i.types[given].bitfield.fword | |
2142 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2143 | /* For scalar opcode templates to allow register and memory |
2144 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2145 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2146 | down-conversion vpmov*. */ | |
3528c362 | 2147 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
1b54b8d7 | 2148 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
2149 | && (t->operand_types[wanted].bitfield.byte |
2150 | || t->operand_types[wanted].bitfield.word | |
2151 | || t->operand_types[wanted].bitfield.dword | |
2152 | || t->operand_types[wanted].bitfield.qword)) | |
2153 | ? (i.types[given].bitfield.xmmword | |
2154 | || i.types[given].bitfield.ymmword | |
2155 | || i.types[given].bitfield.zmmword) | |
2156 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2157 | } |
2158 | ||
3ac21baa JB |
2159 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2160 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2161 | is no size conflict on any operands for the template with operands reversed | |
2162 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2163 | |
3ac21baa JB |
2164 | #define MATCH_STRAIGHT 1 |
2165 | #define MATCH_REVERSE 2 | |
2166 | ||
2167 | static INLINE unsigned int | |
d3ce72d0 | 2168 | operand_size_match (const insn_template *t) |
5c07affc | 2169 | { |
3ac21baa | 2170 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2171 | |
0cfa3eb3 | 2172 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2173 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2174 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2175 | return match; |
2176 | ||
2177 | /* Check memory and accumulator operand size. */ | |
2178 | for (j = 0; j < i.operands; j++) | |
2179 | { | |
3528c362 JB |
2180 | if (i.types[j].bitfield.class != Reg |
2181 | && i.types[j].bitfield.class != RegSIMD | |
601e8564 | 2182 | && t->opcode_modifier.anysize) |
5c07affc L |
2183 | continue; |
2184 | ||
bab6aec1 | 2185 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2186 | && !match_operand_size (t, j, j)) |
5c07affc L |
2187 | { |
2188 | match = 0; | |
2189 | break; | |
2190 | } | |
2191 | ||
3528c362 | 2192 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2193 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2194 | { |
2195 | match = 0; | |
2196 | break; | |
2197 | } | |
2198 | ||
75e5731b | 2199 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2200 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2201 | { |
2202 | match = 0; | |
2203 | break; | |
2204 | } | |
2205 | ||
c48dadc9 | 2206 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2207 | { |
2208 | match = 0; | |
2209 | break; | |
2210 | } | |
2211 | } | |
2212 | ||
3ac21baa | 2213 | if (!t->opcode_modifier.d) |
891edac4 | 2214 | { |
dc1e8a47 | 2215 | mismatch: |
3ac21baa JB |
2216 | if (!match) |
2217 | i.error = operand_size_mismatch; | |
2218 | return match; | |
891edac4 | 2219 | } |
5c07affc L |
2220 | |
2221 | /* Check reverse. */ | |
f5eb1d70 | 2222 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2223 | |
f5eb1d70 | 2224 | for (j = 0; j < i.operands; j++) |
5c07affc | 2225 | { |
f5eb1d70 JB |
2226 | unsigned int given = i.operands - j - 1; |
2227 | ||
bab6aec1 | 2228 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2229 | && !match_operand_size (t, j, given)) |
891edac4 | 2230 | goto mismatch; |
5c07affc | 2231 | |
3528c362 | 2232 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2233 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2234 | goto mismatch; |
2235 | ||
75e5731b | 2236 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2237 | && (!match_operand_size (t, j, given) |
2238 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2239 | goto mismatch; |
2240 | ||
f5eb1d70 | 2241 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2242 | goto mismatch; |
5c07affc L |
2243 | } |
2244 | ||
3ac21baa | 2245 | return match | MATCH_REVERSE; |
5c07affc L |
2246 | } |
2247 | ||
c6fb90c8 | 2248 | static INLINE int |
40fb9820 L |
2249 | operand_type_match (i386_operand_type overlap, |
2250 | i386_operand_type given) | |
2251 | { | |
2252 | i386_operand_type temp = overlap; | |
2253 | ||
7d5e4556 | 2254 | temp.bitfield.unspecified = 0; |
5c07affc L |
2255 | temp.bitfield.byte = 0; |
2256 | temp.bitfield.word = 0; | |
2257 | temp.bitfield.dword = 0; | |
2258 | temp.bitfield.fword = 0; | |
2259 | temp.bitfield.qword = 0; | |
2260 | temp.bitfield.tbyte = 0; | |
2261 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2262 | temp.bitfield.ymmword = 0; |
43234a1e | 2263 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2264 | if (operand_type_all_zero (&temp)) |
891edac4 | 2265 | goto mismatch; |
40fb9820 | 2266 | |
6f2f06be | 2267 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2268 | return 1; |
2269 | ||
dc1e8a47 | 2270 | mismatch: |
a65babc9 | 2271 | i.error = operand_type_mismatch; |
891edac4 | 2272 | return 0; |
40fb9820 L |
2273 | } |
2274 | ||
7d5e4556 | 2275 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2276 | unless the expected operand type register overlap is null. |
5de4d9ef | 2277 | Some Intel syntax memory operand size checking also happens here. */ |
40fb9820 | 2278 | |
c6fb90c8 | 2279 | static INLINE int |
dc821c5f | 2280 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2281 | i386_operand_type t0, |
40fb9820 L |
2282 | i386_operand_type g1, |
2283 | i386_operand_type t1) | |
2284 | { | |
bab6aec1 | 2285 | if (g0.bitfield.class != Reg |
3528c362 | 2286 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2287 | && (!operand_type_check (g0, anymem) |
2288 | || g0.bitfield.unspecified | |
5de4d9ef JB |
2289 | || (t0.bitfield.class != Reg |
2290 | && t0.bitfield.class != RegSIMD))) | |
40fb9820 L |
2291 | return 1; |
2292 | ||
bab6aec1 | 2293 | if (g1.bitfield.class != Reg |
3528c362 | 2294 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2295 | && (!operand_type_check (g1, anymem) |
2296 | || g1.bitfield.unspecified | |
5de4d9ef JB |
2297 | || (t1.bitfield.class != Reg |
2298 | && t1.bitfield.class != RegSIMD))) | |
40fb9820 L |
2299 | return 1; |
2300 | ||
dc821c5f JB |
2301 | if (g0.bitfield.byte == g1.bitfield.byte |
2302 | && g0.bitfield.word == g1.bitfield.word | |
2303 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2304 | && g0.bitfield.qword == g1.bitfield.qword |
2305 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2306 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2307 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2308 | return 1; |
2309 | ||
dc821c5f JB |
2310 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2311 | && !(t0.bitfield.word & t1.bitfield.word) | |
2312 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2313 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2314 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2315 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2316 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2317 | return 1; |
2318 | ||
a65babc9 | 2319 | i.error = register_type_mismatch; |
891edac4 L |
2320 | |
2321 | return 0; | |
40fb9820 L |
2322 | } |
2323 | ||
4c692bc7 JB |
2324 | static INLINE unsigned int |
2325 | register_number (const reg_entry *r) | |
2326 | { | |
2327 | unsigned int nr = r->reg_num; | |
2328 | ||
2329 | if (r->reg_flags & RegRex) | |
2330 | nr += 8; | |
2331 | ||
200cbe0f L |
2332 | if (r->reg_flags & RegVRex) |
2333 | nr += 16; | |
2334 | ||
4c692bc7 JB |
2335 | return nr; |
2336 | } | |
2337 | ||
252b5132 | 2338 | static INLINE unsigned int |
40fb9820 | 2339 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2340 | { |
b5014f7a | 2341 | if (t.bitfield.disp8) |
40fb9820 L |
2342 | return 1; |
2343 | else if (t.bitfield.disp16 | |
2344 | || t.bitfield.disp32 | |
2345 | || t.bitfield.disp32s) | |
2346 | return 2; | |
2347 | else | |
2348 | return 0; | |
252b5132 RH |
2349 | } |
2350 | ||
2351 | static INLINE int | |
65879393 | 2352 | fits_in_signed_byte (addressT num) |
252b5132 | 2353 | { |
65879393 | 2354 | return num + 0x80 <= 0xff; |
47926f60 | 2355 | } |
252b5132 RH |
2356 | |
2357 | static INLINE int | |
65879393 | 2358 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2359 | { |
65879393 | 2360 | return num <= 0xff; |
47926f60 | 2361 | } |
252b5132 RH |
2362 | |
2363 | static INLINE int | |
65879393 | 2364 | fits_in_unsigned_word (addressT num) |
252b5132 | 2365 | { |
65879393 | 2366 | return num <= 0xffff; |
47926f60 | 2367 | } |
252b5132 RH |
2368 | |
2369 | static INLINE int | |
65879393 | 2370 | fits_in_signed_word (addressT num) |
252b5132 | 2371 | { |
65879393 | 2372 | return num + 0x8000 <= 0xffff; |
47926f60 | 2373 | } |
2a962e6d | 2374 | |
3e73aa7c | 2375 | static INLINE int |
65879393 | 2376 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2377 | { |
2378 | #ifndef BFD64 | |
2379 | return 1; | |
2380 | #else | |
65879393 | 2381 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2382 | #endif |
2383 | } /* fits_in_signed_long() */ | |
2a962e6d | 2384 | |
3e73aa7c | 2385 | static INLINE int |
65879393 | 2386 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2387 | { |
2388 | #ifndef BFD64 | |
2389 | return 1; | |
2390 | #else | |
65879393 | 2391 | return num <= 0xffffffff; |
3e73aa7c JH |
2392 | #endif |
2393 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2394 | |
43234a1e | 2395 | static INLINE int |
b5014f7a | 2396 | fits_in_disp8 (offsetT num) |
43234a1e L |
2397 | { |
2398 | int shift = i.memshift; | |
2399 | unsigned int mask; | |
2400 | ||
2401 | if (shift == -1) | |
2402 | abort (); | |
2403 | ||
2404 | mask = (1 << shift) - 1; | |
2405 | ||
2406 | /* Return 0 if NUM isn't properly aligned. */ | |
2407 | if ((num & mask)) | |
2408 | return 0; | |
2409 | ||
2410 | /* Check if NUM will fit in 8bit after shift. */ | |
2411 | return fits_in_signed_byte (num >> shift); | |
2412 | } | |
2413 | ||
a683cc34 SP |
2414 | static INLINE int |
2415 | fits_in_imm4 (offsetT num) | |
2416 | { | |
2417 | return (num & 0xf) == num; | |
2418 | } | |
2419 | ||
40fb9820 | 2420 | static i386_operand_type |
e3bb37b5 | 2421 | smallest_imm_type (offsetT num) |
252b5132 | 2422 | { |
40fb9820 | 2423 | i386_operand_type t; |
7ab9ffdd | 2424 | |
0dfbf9d7 | 2425 | operand_type_set (&t, 0); |
40fb9820 L |
2426 | t.bitfield.imm64 = 1; |
2427 | ||
2428 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2429 | { |
2430 | /* This code is disabled on the 486 because all the Imm1 forms | |
2431 | in the opcode table are slower on the i486. They're the | |
2432 | versions with the implicitly specified single-position | |
2433 | displacement, which has another syntax if you really want to | |
2434 | use that form. */ | |
40fb9820 L |
2435 | t.bitfield.imm1 = 1; |
2436 | t.bitfield.imm8 = 1; | |
2437 | t.bitfield.imm8s = 1; | |
2438 | t.bitfield.imm16 = 1; | |
2439 | t.bitfield.imm32 = 1; | |
2440 | t.bitfield.imm32s = 1; | |
2441 | } | |
2442 | else if (fits_in_signed_byte (num)) | |
2443 | { | |
2444 | t.bitfield.imm8 = 1; | |
2445 | t.bitfield.imm8s = 1; | |
2446 | t.bitfield.imm16 = 1; | |
2447 | t.bitfield.imm32 = 1; | |
2448 | t.bitfield.imm32s = 1; | |
2449 | } | |
2450 | else if (fits_in_unsigned_byte (num)) | |
2451 | { | |
2452 | t.bitfield.imm8 = 1; | |
2453 | t.bitfield.imm16 = 1; | |
2454 | t.bitfield.imm32 = 1; | |
2455 | t.bitfield.imm32s = 1; | |
2456 | } | |
2457 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2458 | { | |
2459 | t.bitfield.imm16 = 1; | |
2460 | t.bitfield.imm32 = 1; | |
2461 | t.bitfield.imm32s = 1; | |
2462 | } | |
2463 | else if (fits_in_signed_long (num)) | |
2464 | { | |
2465 | t.bitfield.imm32 = 1; | |
2466 | t.bitfield.imm32s = 1; | |
2467 | } | |
2468 | else if (fits_in_unsigned_long (num)) | |
2469 | t.bitfield.imm32 = 1; | |
2470 | ||
2471 | return t; | |
47926f60 | 2472 | } |
252b5132 | 2473 | |
847f7ad4 | 2474 | static offsetT |
e3bb37b5 | 2475 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2476 | { |
508866be | 2477 | addressT mask; |
ba2adb93 | 2478 | |
847f7ad4 AM |
2479 | switch (size) |
2480 | { | |
508866be L |
2481 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2482 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2483 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2484 | #ifdef BFD64 |
2485 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2486 | #endif | |
47926f60 | 2487 | default: abort (); |
847f7ad4 AM |
2488 | } |
2489 | ||
9de868bf L |
2490 | #ifdef BFD64 |
2491 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2492 | if (flag_code != CODE_64BIT | |
2493 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2494 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2495 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2496 | #endif |
ba2adb93 | 2497 | |
47926f60 | 2498 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2499 | { |
2500 | char buf1[40], buf2[40]; | |
2501 | ||
2502 | sprint_value (buf1, val); | |
2503 | sprint_value (buf2, val & mask); | |
2504 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2505 | } | |
2506 | return val & mask; | |
2507 | } | |
2508 | ||
c32fa91d L |
2509 | enum PREFIX_GROUP |
2510 | { | |
2511 | PREFIX_EXIST = 0, | |
2512 | PREFIX_LOCK, | |
2513 | PREFIX_REP, | |
04ef582a | 2514 | PREFIX_DS, |
c32fa91d L |
2515 | PREFIX_OTHER |
2516 | }; | |
2517 | ||
2518 | /* Returns | |
2519 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2520 | same class already exists. | |
2521 | b. PREFIX_LOCK if lock prefix is added. | |
2522 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2523 | d. PREFIX_DS if ds prefix is added. |
2524 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2525 | */ |
2526 | ||
2527 | static enum PREFIX_GROUP | |
e3bb37b5 | 2528 | add_prefix (unsigned int prefix) |
252b5132 | 2529 | { |
c32fa91d | 2530 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2531 | unsigned int q; |
252b5132 | 2532 | |
29b0f896 AM |
2533 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2534 | && flag_code == CODE_64BIT) | |
b1905489 | 2535 | { |
161a04f6 | 2536 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2537 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2538 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2539 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2540 | ret = PREFIX_EXIST; |
b1905489 JB |
2541 | q = REX_PREFIX; |
2542 | } | |
3e73aa7c | 2543 | else |
b1905489 JB |
2544 | { |
2545 | switch (prefix) | |
2546 | { | |
2547 | default: | |
2548 | abort (); | |
2549 | ||
b1905489 | 2550 | case DS_PREFIX_OPCODE: |
04ef582a L |
2551 | ret = PREFIX_DS; |
2552 | /* Fall through. */ | |
2553 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2554 | case ES_PREFIX_OPCODE: |
2555 | case FS_PREFIX_OPCODE: | |
2556 | case GS_PREFIX_OPCODE: | |
2557 | case SS_PREFIX_OPCODE: | |
2558 | q = SEG_PREFIX; | |
2559 | break; | |
2560 | ||
2561 | case REPNE_PREFIX_OPCODE: | |
2562 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2563 | q = REP_PREFIX; |
2564 | ret = PREFIX_REP; | |
2565 | break; | |
2566 | ||
b1905489 | 2567 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2568 | q = LOCK_PREFIX; |
2569 | ret = PREFIX_LOCK; | |
b1905489 JB |
2570 | break; |
2571 | ||
2572 | case FWAIT_OPCODE: | |
2573 | q = WAIT_PREFIX; | |
2574 | break; | |
2575 | ||
2576 | case ADDR_PREFIX_OPCODE: | |
2577 | q = ADDR_PREFIX; | |
2578 | break; | |
2579 | ||
2580 | case DATA_PREFIX_OPCODE: | |
2581 | q = DATA_PREFIX; | |
2582 | break; | |
2583 | } | |
2584 | if (i.prefix[q] != 0) | |
c32fa91d | 2585 | ret = PREFIX_EXIST; |
b1905489 | 2586 | } |
252b5132 | 2587 | |
b1905489 | 2588 | if (ret) |
252b5132 | 2589 | { |
b1905489 JB |
2590 | if (!i.prefix[q]) |
2591 | ++i.prefixes; | |
2592 | i.prefix[q] |= prefix; | |
252b5132 | 2593 | } |
b1905489 JB |
2594 | else |
2595 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2596 | |
252b5132 RH |
2597 | return ret; |
2598 | } | |
2599 | ||
2600 | static void | |
78f12dd3 | 2601 | update_code_flag (int value, int check) |
eecb386c | 2602 | { |
78f12dd3 L |
2603 | PRINTF_LIKE ((*as_error)); |
2604 | ||
1e9cc1c2 | 2605 | flag_code = (enum flag_code) value; |
40fb9820 L |
2606 | if (flag_code == CODE_64BIT) |
2607 | { | |
2608 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2609 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2610 | } |
2611 | else | |
2612 | { | |
2613 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2614 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2615 | } |
2616 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2617 | { |
78f12dd3 L |
2618 | if (check) |
2619 | as_error = as_fatal; | |
2620 | else | |
2621 | as_error = as_bad; | |
2622 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2623 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2624 | } |
40fb9820 | 2625 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2626 | { |
78f12dd3 L |
2627 | if (check) |
2628 | as_error = as_fatal; | |
2629 | else | |
2630 | as_error = as_bad; | |
2631 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2632 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2633 | } |
eecb386c AM |
2634 | stackop_size = '\0'; |
2635 | } | |
2636 | ||
78f12dd3 L |
2637 | static void |
2638 | set_code_flag (int value) | |
2639 | { | |
2640 | update_code_flag (value, 0); | |
2641 | } | |
2642 | ||
eecb386c | 2643 | static void |
e3bb37b5 | 2644 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2645 | { |
1e9cc1c2 | 2646 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2647 | if (flag_code != CODE_16BIT) |
2648 | abort (); | |
2649 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2650 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2651 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2652 | } |
2653 | ||
2654 | static void | |
e3bb37b5 | 2655 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2656 | { |
2657 | /* Find out if register prefixing is specified. */ | |
2658 | int ask_naked_reg = 0; | |
2659 | ||
2660 | SKIP_WHITESPACE (); | |
29b0f896 | 2661 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2662 | { |
d02603dc NC |
2663 | char *string; |
2664 | int e = get_symbol_name (&string); | |
252b5132 | 2665 | |
47926f60 | 2666 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2667 | ask_naked_reg = 1; |
47926f60 | 2668 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2669 | ask_naked_reg = -1; |
2670 | else | |
d0b47220 | 2671 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2672 | (void) restore_line_pointer (e); |
252b5132 RH |
2673 | } |
2674 | demand_empty_rest_of_line (); | |
c3332e24 | 2675 | |
252b5132 RH |
2676 | intel_syntax = syntax_flag; |
2677 | ||
2678 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2679 | allow_naked_reg = (intel_syntax |
2680 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2681 | else |
2682 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2683 | |
ee86248c | 2684 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2685 | |
e4a3b5a4 | 2686 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2687 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2688 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2689 | } |
2690 | ||
1efbbeb4 L |
2691 | static void |
2692 | set_intel_mnemonic (int mnemonic_flag) | |
2693 | { | |
e1d4d893 | 2694 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2695 | } |
2696 | ||
db51cc60 L |
2697 | static void |
2698 | set_allow_index_reg (int flag) | |
2699 | { | |
2700 | allow_index_reg = flag; | |
2701 | } | |
2702 | ||
cb19c032 | 2703 | static void |
7bab8ab5 | 2704 | set_check (int what) |
cb19c032 | 2705 | { |
7bab8ab5 JB |
2706 | enum check_kind *kind; |
2707 | const char *str; | |
2708 | ||
2709 | if (what) | |
2710 | { | |
2711 | kind = &operand_check; | |
2712 | str = "operand"; | |
2713 | } | |
2714 | else | |
2715 | { | |
2716 | kind = &sse_check; | |
2717 | str = "sse"; | |
2718 | } | |
2719 | ||
cb19c032 L |
2720 | SKIP_WHITESPACE (); |
2721 | ||
2722 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2723 | { | |
d02603dc NC |
2724 | char *string; |
2725 | int e = get_symbol_name (&string); | |
cb19c032 L |
2726 | |
2727 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2728 | *kind = check_none; |
cb19c032 | 2729 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2730 | *kind = check_warning; |
cb19c032 | 2731 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2732 | *kind = check_error; |
cb19c032 | 2733 | else |
7bab8ab5 | 2734 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2735 | (void) restore_line_pointer (e); |
cb19c032 L |
2736 | } |
2737 | else | |
7bab8ab5 | 2738 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2739 | |
2740 | demand_empty_rest_of_line (); | |
2741 | } | |
2742 | ||
8a9036a4 L |
2743 | static void |
2744 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2745 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2746 | { |
2747 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2748 | static const char *arch; | |
2749 | ||
2750 | /* Intel LIOM is only supported on ELF. */ | |
2751 | if (!IS_ELF) | |
2752 | return; | |
2753 | ||
2754 | if (!arch) | |
2755 | { | |
2756 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2757 | use default_arch. */ | |
2758 | arch = cpu_arch_name; | |
2759 | if (!arch) | |
2760 | arch = default_arch; | |
2761 | } | |
2762 | ||
81486035 L |
2763 | /* If we are targeting Intel MCU, we must enable it. */ |
2764 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2765 | || new_flag.bitfield.cpuiamcu) | |
2766 | return; | |
2767 | ||
3632d14b | 2768 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2769 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2770 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2771 | return; |
76ba9986 | 2772 | |
7a9068fe L |
2773 | /* If we are targeting Intel K1OM, we must enable it. */ |
2774 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2775 | || new_flag.bitfield.cpuk1om) | |
2776 | return; | |
2777 | ||
8a9036a4 L |
2778 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2779 | #endif | |
2780 | } | |
2781 | ||
e413e4e9 | 2782 | static void |
e3bb37b5 | 2783 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2784 | { |
47926f60 | 2785 | SKIP_WHITESPACE (); |
e413e4e9 | 2786 | |
29b0f896 | 2787 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2788 | { |
d02603dc NC |
2789 | char *string; |
2790 | int e = get_symbol_name (&string); | |
91d6fa6a | 2791 | unsigned int j; |
40fb9820 | 2792 | i386_cpu_flags flags; |
e413e4e9 | 2793 | |
91d6fa6a | 2794 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2795 | { |
91d6fa6a | 2796 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2797 | { |
91d6fa6a | 2798 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2799 | |
5c6af06e JB |
2800 | if (*string != '.') |
2801 | { | |
91d6fa6a | 2802 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2803 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2804 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2805 | if (flag_code == CODE_64BIT) |
2806 | { | |
2807 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2808 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2809 | } | |
2810 | else | |
2811 | { | |
2812 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2813 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2814 | } | |
91d6fa6a NC |
2815 | cpu_arch_isa = cpu_arch[j].type; |
2816 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2817 | if (!cpu_arch_tune_set) |
2818 | { | |
2819 | cpu_arch_tune = cpu_arch_isa; | |
2820 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2821 | } | |
5c6af06e JB |
2822 | break; |
2823 | } | |
40fb9820 | 2824 | |
293f5f65 L |
2825 | flags = cpu_flags_or (cpu_arch_flags, |
2826 | cpu_arch[j].flags); | |
81486035 | 2827 | |
5b64d091 | 2828 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2829 | { |
6305a203 L |
2830 | if (cpu_sub_arch_name) |
2831 | { | |
2832 | char *name = cpu_sub_arch_name; | |
2833 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2834 | cpu_arch[j].name, |
1bf57e9f | 2835 | (const char *) NULL); |
6305a203 L |
2836 | free (name); |
2837 | } | |
2838 | else | |
91d6fa6a | 2839 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2840 | cpu_arch_flags = flags; |
a586129e | 2841 | cpu_arch_isa_flags = flags; |
5c6af06e | 2842 | } |
0089dace L |
2843 | else |
2844 | cpu_arch_isa_flags | |
2845 | = cpu_flags_or (cpu_arch_isa_flags, | |
2846 | cpu_arch[j].flags); | |
d02603dc | 2847 | (void) restore_line_pointer (e); |
5c6af06e JB |
2848 | demand_empty_rest_of_line (); |
2849 | return; | |
e413e4e9 AM |
2850 | } |
2851 | } | |
293f5f65 L |
2852 | |
2853 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2854 | { | |
33eaf5de | 2855 | /* Disable an ISA extension. */ |
293f5f65 L |
2856 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2857 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2858 | { | |
2859 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2860 | cpu_noarch[j].flags); | |
2861 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2862 | { | |
2863 | if (cpu_sub_arch_name) | |
2864 | { | |
2865 | char *name = cpu_sub_arch_name; | |
2866 | cpu_sub_arch_name = concat (name, string, | |
2867 | (const char *) NULL); | |
2868 | free (name); | |
2869 | } | |
2870 | else | |
2871 | cpu_sub_arch_name = xstrdup (string); | |
2872 | cpu_arch_flags = flags; | |
2873 | cpu_arch_isa_flags = flags; | |
2874 | } | |
2875 | (void) restore_line_pointer (e); | |
2876 | demand_empty_rest_of_line (); | |
2877 | return; | |
2878 | } | |
2879 | ||
2880 | j = ARRAY_SIZE (cpu_arch); | |
2881 | } | |
2882 | ||
91d6fa6a | 2883 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2884 | as_bad (_("no such architecture: `%s'"), string); |
2885 | ||
2886 | *input_line_pointer = e; | |
2887 | } | |
2888 | else | |
2889 | as_bad (_("missing cpu architecture")); | |
2890 | ||
fddf5b5b AM |
2891 | no_cond_jump_promotion = 0; |
2892 | if (*input_line_pointer == ',' | |
29b0f896 | 2893 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2894 | { |
d02603dc NC |
2895 | char *string; |
2896 | char e; | |
2897 | ||
2898 | ++input_line_pointer; | |
2899 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2900 | |
2901 | if (strcmp (string, "nojumps") == 0) | |
2902 | no_cond_jump_promotion = 1; | |
2903 | else if (strcmp (string, "jumps") == 0) | |
2904 | ; | |
2905 | else | |
2906 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2907 | ||
d02603dc | 2908 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2909 | } |
2910 | ||
e413e4e9 AM |
2911 | demand_empty_rest_of_line (); |
2912 | } | |
2913 | ||
8a9036a4 L |
2914 | enum bfd_architecture |
2915 | i386_arch (void) | |
2916 | { | |
3632d14b | 2917 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2918 | { |
2919 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2920 | || flag_code != CODE_64BIT) | |
2921 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2922 | return bfd_arch_l1om; | |
2923 | } | |
7a9068fe L |
2924 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2925 | { | |
2926 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2927 | || flag_code != CODE_64BIT) | |
2928 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2929 | return bfd_arch_k1om; | |
2930 | } | |
81486035 L |
2931 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2932 | { | |
2933 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2934 | || flag_code == CODE_64BIT) | |
2935 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2936 | return bfd_arch_iamcu; | |
2937 | } | |
8a9036a4 L |
2938 | else |
2939 | return bfd_arch_i386; | |
2940 | } | |
2941 | ||
b9d79e03 | 2942 | unsigned long |
7016a5d5 | 2943 | i386_mach (void) |
b9d79e03 | 2944 | { |
351f65ca | 2945 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2946 | { |
3632d14b | 2947 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2948 | { |
351f65ca L |
2949 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2950 | || default_arch[6] != '\0') | |
8a9036a4 L |
2951 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2952 | return bfd_mach_l1om; | |
2953 | } | |
7a9068fe L |
2954 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2955 | { | |
2956 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2957 | || default_arch[6] != '\0') | |
2958 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2959 | return bfd_mach_k1om; | |
2960 | } | |
351f65ca | 2961 | else if (default_arch[6] == '\0') |
8a9036a4 | 2962 | return bfd_mach_x86_64; |
351f65ca L |
2963 | else |
2964 | return bfd_mach_x64_32; | |
8a9036a4 | 2965 | } |
5197d474 L |
2966 | else if (!strcmp (default_arch, "i386") |
2967 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2968 | { |
2969 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2970 | { | |
2971 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2972 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2973 | return bfd_mach_i386_iamcu; | |
2974 | } | |
2975 | else | |
2976 | return bfd_mach_i386_i386; | |
2977 | } | |
b9d79e03 | 2978 | else |
2b5d6a91 | 2979 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2980 | } |
b9d79e03 | 2981 | \f |
252b5132 | 2982 | void |
7016a5d5 | 2983 | md_begin (void) |
252b5132 RH |
2984 | { |
2985 | const char *hash_err; | |
2986 | ||
86fa6981 L |
2987 | /* Support pseudo prefixes like {disp32}. */ |
2988 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2989 | ||
47926f60 | 2990 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2991 | op_hash = hash_new (); |
2992 | ||
2993 | { | |
d3ce72d0 | 2994 | const insn_template *optab; |
29b0f896 | 2995 | templates *core_optab; |
252b5132 | 2996 | |
47926f60 KH |
2997 | /* Setup for loop. */ |
2998 | optab = i386_optab; | |
add39d23 | 2999 | core_optab = XNEW (templates); |
252b5132 RH |
3000 | core_optab->start = optab; |
3001 | ||
3002 | while (1) | |
3003 | { | |
3004 | ++optab; | |
3005 | if (optab->name == NULL | |
3006 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
3007 | { | |
3008 | /* different name --> ship out current template list; | |
47926f60 | 3009 | add to hash table; & begin anew. */ |
252b5132 RH |
3010 | core_optab->end = optab; |
3011 | hash_err = hash_insert (op_hash, | |
3012 | (optab - 1)->name, | |
5a49b8ac | 3013 | (void *) core_optab); |
252b5132 RH |
3014 | if (hash_err) |
3015 | { | |
b37df7c4 | 3016 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
3017 | (optab - 1)->name, |
3018 | hash_err); | |
3019 | } | |
3020 | if (optab->name == NULL) | |
3021 | break; | |
add39d23 | 3022 | core_optab = XNEW (templates); |
252b5132 RH |
3023 | core_optab->start = optab; |
3024 | } | |
3025 | } | |
3026 | } | |
3027 | ||
47926f60 | 3028 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
3029 | reg_hash = hash_new (); |
3030 | { | |
29b0f896 | 3031 | const reg_entry *regtab; |
c3fe08fa | 3032 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3033 | |
c3fe08fa | 3034 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 3035 | { |
5a49b8ac | 3036 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 3037 | if (hash_err) |
b37df7c4 | 3038 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
3039 | regtab->reg_name, |
3040 | hash_err); | |
252b5132 RH |
3041 | } |
3042 | } | |
3043 | ||
47926f60 | 3044 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3045 | { |
29b0f896 AM |
3046 | int c; |
3047 | char *p; | |
252b5132 RH |
3048 | |
3049 | for (c = 0; c < 256; c++) | |
3050 | { | |
3882b010 | 3051 | if (ISDIGIT (c)) |
252b5132 RH |
3052 | { |
3053 | digit_chars[c] = c; | |
3054 | mnemonic_chars[c] = c; | |
3055 | register_chars[c] = c; | |
3056 | operand_chars[c] = c; | |
3057 | } | |
3882b010 | 3058 | else if (ISLOWER (c)) |
252b5132 RH |
3059 | { |
3060 | mnemonic_chars[c] = c; | |
3061 | register_chars[c] = c; | |
3062 | operand_chars[c] = c; | |
3063 | } | |
3882b010 | 3064 | else if (ISUPPER (c)) |
252b5132 | 3065 | { |
3882b010 | 3066 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3067 | register_chars[c] = mnemonic_chars[c]; |
3068 | operand_chars[c] = c; | |
3069 | } | |
43234a1e | 3070 | else if (c == '{' || c == '}') |
86fa6981 L |
3071 | { |
3072 | mnemonic_chars[c] = c; | |
3073 | operand_chars[c] = c; | |
3074 | } | |
252b5132 | 3075 | |
3882b010 | 3076 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3077 | identifier_chars[c] = c; |
3078 | else if (c >= 128) | |
3079 | { | |
3080 | identifier_chars[c] = c; | |
3081 | operand_chars[c] = c; | |
3082 | } | |
3083 | } | |
3084 | ||
3085 | #ifdef LEX_AT | |
3086 | identifier_chars['@'] = '@'; | |
32137342 NC |
3087 | #endif |
3088 | #ifdef LEX_QM | |
3089 | identifier_chars['?'] = '?'; | |
3090 | operand_chars['?'] = '?'; | |
252b5132 | 3091 | #endif |
252b5132 | 3092 | digit_chars['-'] = '-'; |
c0f3af97 | 3093 | mnemonic_chars['_'] = '_'; |
791fe849 | 3094 | mnemonic_chars['-'] = '-'; |
0003779b | 3095 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3096 | identifier_chars['_'] = '_'; |
3097 | identifier_chars['.'] = '.'; | |
3098 | ||
3099 | for (p = operand_special_chars; *p != '\0'; p++) | |
3100 | operand_chars[(unsigned char) *p] = *p; | |
3101 | } | |
3102 | ||
a4447b93 RH |
3103 | if (flag_code == CODE_64BIT) |
3104 | { | |
ca19b261 KT |
3105 | #if defined (OBJ_COFF) && defined (TE_PE) |
3106 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3107 | ? 32 : 16); | |
3108 | #else | |
a4447b93 | 3109 | x86_dwarf2_return_column = 16; |
ca19b261 | 3110 | #endif |
61ff971f | 3111 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3112 | } |
3113 | else | |
3114 | { | |
3115 | x86_dwarf2_return_column = 8; | |
3116 | x86_cie_data_alignment = -4; | |
3117 | } | |
e379e5f3 L |
3118 | |
3119 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3120 | can be turned into BRANCH_PREFIX frag. */ | |
3121 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3122 | abort (); | |
252b5132 RH |
3123 | } |
3124 | ||
3125 | void | |
e3bb37b5 | 3126 | i386_print_statistics (FILE *file) |
252b5132 RH |
3127 | { |
3128 | hash_print_statistics (file, "i386 opcode", op_hash); | |
3129 | hash_print_statistics (file, "i386 register", reg_hash); | |
3130 | } | |
3131 | \f | |
252b5132 RH |
3132 | #ifdef DEBUG386 |
3133 | ||
ce8a8b2f | 3134 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3135 | static void pte (insn_template *); |
40fb9820 | 3136 | static void pt (i386_operand_type); |
e3bb37b5 L |
3137 | static void pe (expressionS *); |
3138 | static void ps (symbolS *); | |
252b5132 RH |
3139 | |
3140 | static void | |
2c703856 | 3141 | pi (const char *line, i386_insn *x) |
252b5132 | 3142 | { |
09137c09 | 3143 | unsigned int j; |
252b5132 RH |
3144 | |
3145 | fprintf (stdout, "%s: template ", line); | |
3146 | pte (&x->tm); | |
09f131f2 JH |
3147 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3148 | x->base_reg ? x->base_reg->reg_name : "none", | |
3149 | x->index_reg ? x->index_reg->reg_name : "none", | |
3150 | x->log2_scale_factor); | |
3151 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3152 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3153 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3154 | x->sib.base, x->sib.index, x->sib.scale); | |
3155 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3156 | (x->rex & REX_W) != 0, |
3157 | (x->rex & REX_R) != 0, | |
3158 | (x->rex & REX_X) != 0, | |
3159 | (x->rex & REX_B) != 0); | |
09137c09 | 3160 | for (j = 0; j < x->operands; j++) |
252b5132 | 3161 | { |
09137c09 SP |
3162 | fprintf (stdout, " #%d: ", j + 1); |
3163 | pt (x->types[j]); | |
252b5132 | 3164 | fprintf (stdout, "\n"); |
bab6aec1 | 3165 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3166 | || x->types[j].bitfield.class == RegMMX |
3167 | || x->types[j].bitfield.class == RegSIMD | |
00cee14f | 3168 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3169 | || x->types[j].bitfield.class == RegCR |
3170 | || x->types[j].bitfield.class == RegDR | |
3171 | || x->types[j].bitfield.class == RegTR) | |
09137c09 SP |
3172 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3173 | if (operand_type_check (x->types[j], imm)) | |
3174 | pe (x->op[j].imms); | |
3175 | if (operand_type_check (x->types[j], disp)) | |
3176 | pe (x->op[j].disps); | |
252b5132 RH |
3177 | } |
3178 | } | |
3179 | ||
3180 | static void | |
d3ce72d0 | 3181 | pte (insn_template *t) |
252b5132 | 3182 | { |
09137c09 | 3183 | unsigned int j; |
252b5132 | 3184 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3185 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3186 | if (t->extension_opcode != None) |
3187 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3188 | if (t->opcode_modifier.d) |
252b5132 | 3189 | fprintf (stdout, "D"); |
40fb9820 | 3190 | if (t->opcode_modifier.w) |
252b5132 RH |
3191 | fprintf (stdout, "W"); |
3192 | fprintf (stdout, "\n"); | |
09137c09 | 3193 | for (j = 0; j < t->operands; j++) |
252b5132 | 3194 | { |
09137c09 SP |
3195 | fprintf (stdout, " #%d type ", j + 1); |
3196 | pt (t->operand_types[j]); | |
252b5132 RH |
3197 | fprintf (stdout, "\n"); |
3198 | } | |
3199 | } | |
3200 | ||
3201 | static void | |
e3bb37b5 | 3202 | pe (expressionS *e) |
252b5132 | 3203 | { |
24eab124 | 3204 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3205 | fprintf (stdout, " add_number %ld (%lx)\n", |
3206 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3207 | if (e->X_add_symbol) |
3208 | { | |
3209 | fprintf (stdout, " add_symbol "); | |
3210 | ps (e->X_add_symbol); | |
3211 | fprintf (stdout, "\n"); | |
3212 | } | |
3213 | if (e->X_op_symbol) | |
3214 | { | |
3215 | fprintf (stdout, " op_symbol "); | |
3216 | ps (e->X_op_symbol); | |
3217 | fprintf (stdout, "\n"); | |
3218 | } | |
3219 | } | |
3220 | ||
3221 | static void | |
e3bb37b5 | 3222 | ps (symbolS *s) |
252b5132 RH |
3223 | { |
3224 | fprintf (stdout, "%s type %s%s", | |
3225 | S_GET_NAME (s), | |
3226 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3227 | segment_name (S_GET_SEGMENT (s))); | |
3228 | } | |
3229 | ||
7b81dfbb | 3230 | static struct type_name |
252b5132 | 3231 | { |
40fb9820 L |
3232 | i386_operand_type mask; |
3233 | const char *name; | |
252b5132 | 3234 | } |
7b81dfbb | 3235 | const type_names[] = |
252b5132 | 3236 | { |
40fb9820 L |
3237 | { OPERAND_TYPE_REG8, "r8" }, |
3238 | { OPERAND_TYPE_REG16, "r16" }, | |
3239 | { OPERAND_TYPE_REG32, "r32" }, | |
3240 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3241 | { OPERAND_TYPE_ACC8, "acc8" }, |
3242 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3243 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3244 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3245 | { OPERAND_TYPE_IMM8, "i8" }, |
3246 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3247 | { OPERAND_TYPE_IMM16, "i16" }, | |
3248 | { OPERAND_TYPE_IMM32, "i32" }, | |
3249 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3250 | { OPERAND_TYPE_IMM64, "i64" }, | |
3251 | { OPERAND_TYPE_IMM1, "i1" }, | |
3252 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3253 | { OPERAND_TYPE_DISP8, "d8" }, | |
3254 | { OPERAND_TYPE_DISP16, "d16" }, | |
3255 | { OPERAND_TYPE_DISP32, "d32" }, | |
3256 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3257 | { OPERAND_TYPE_DISP64, "d64" }, | |
3258 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3259 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3260 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3261 | { OPERAND_TYPE_TEST, "test reg" }, | |
3262 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3263 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3264 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3265 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3266 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
3267 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3268 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3269 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3270 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
252b5132 RH |
3271 | }; |
3272 | ||
3273 | static void | |
40fb9820 | 3274 | pt (i386_operand_type t) |
252b5132 | 3275 | { |
40fb9820 | 3276 | unsigned int j; |
c6fb90c8 | 3277 | i386_operand_type a; |
252b5132 | 3278 | |
40fb9820 | 3279 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3280 | { |
3281 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3282 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3283 | fprintf (stdout, "%s, ", type_names[j].name); |
3284 | } | |
252b5132 RH |
3285 | fflush (stdout); |
3286 | } | |
3287 | ||
3288 | #endif /* DEBUG386 */ | |
3289 | \f | |
252b5132 | 3290 | static bfd_reloc_code_real_type |
3956db08 | 3291 | reloc (unsigned int size, |
64e74474 AM |
3292 | int pcrel, |
3293 | int sign, | |
3294 | bfd_reloc_code_real_type other) | |
252b5132 | 3295 | { |
47926f60 | 3296 | if (other != NO_RELOC) |
3956db08 | 3297 | { |
91d6fa6a | 3298 | reloc_howto_type *rel; |
3956db08 JB |
3299 | |
3300 | if (size == 8) | |
3301 | switch (other) | |
3302 | { | |
64e74474 AM |
3303 | case BFD_RELOC_X86_64_GOT32: |
3304 | return BFD_RELOC_X86_64_GOT64; | |
3305 | break; | |
553d1284 L |
3306 | case BFD_RELOC_X86_64_GOTPLT64: |
3307 | return BFD_RELOC_X86_64_GOTPLT64; | |
3308 | break; | |
64e74474 AM |
3309 | case BFD_RELOC_X86_64_PLTOFF64: |
3310 | return BFD_RELOC_X86_64_PLTOFF64; | |
3311 | break; | |
3312 | case BFD_RELOC_X86_64_GOTPC32: | |
3313 | other = BFD_RELOC_X86_64_GOTPC64; | |
3314 | break; | |
3315 | case BFD_RELOC_X86_64_GOTPCREL: | |
3316 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3317 | break; | |
3318 | case BFD_RELOC_X86_64_TPOFF32: | |
3319 | other = BFD_RELOC_X86_64_TPOFF64; | |
3320 | break; | |
3321 | case BFD_RELOC_X86_64_DTPOFF32: | |
3322 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3323 | break; | |
3324 | default: | |
3325 | break; | |
3956db08 | 3326 | } |
e05278af | 3327 | |
8ce3d284 | 3328 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3329 | if (other == BFD_RELOC_SIZE32) |
3330 | { | |
3331 | if (size == 8) | |
1ab668bf | 3332 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3333 | if (pcrel) |
1ab668bf AM |
3334 | { |
3335 | as_bad (_("there are no pc-relative size relocations")); | |
3336 | return NO_RELOC; | |
3337 | } | |
8fd4256d | 3338 | } |
8ce3d284 | 3339 | #endif |
8fd4256d | 3340 | |
e05278af | 3341 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3342 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3343 | sign = -1; |
3344 | ||
91d6fa6a NC |
3345 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3346 | if (!rel) | |
3956db08 | 3347 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3348 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3349 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3350 | bfd_get_reloc_size (rel), |
3956db08 | 3351 | size); |
91d6fa6a | 3352 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3353 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3354 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3355 | && !sign) |
91d6fa6a | 3356 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3357 | && sign > 0)) |
3956db08 JB |
3358 | as_bad (_("relocated field and relocation type differ in signedness")); |
3359 | else | |
3360 | return other; | |
3361 | return NO_RELOC; | |
3362 | } | |
252b5132 RH |
3363 | |
3364 | if (pcrel) | |
3365 | { | |
3e73aa7c | 3366 | if (!sign) |
3956db08 | 3367 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3368 | switch (size) |
3369 | { | |
3370 | case 1: return BFD_RELOC_8_PCREL; | |
3371 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3372 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3373 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3374 | } |
3956db08 | 3375 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3376 | } |
3377 | else | |
3378 | { | |
3956db08 | 3379 | if (sign > 0) |
e5cb08ac | 3380 | switch (size) |
3e73aa7c JH |
3381 | { |
3382 | case 4: return BFD_RELOC_X86_64_32S; | |
3383 | } | |
3384 | else | |
3385 | switch (size) | |
3386 | { | |
3387 | case 1: return BFD_RELOC_8; | |
3388 | case 2: return BFD_RELOC_16; | |
3389 | case 4: return BFD_RELOC_32; | |
3390 | case 8: return BFD_RELOC_64; | |
3391 | } | |
3956db08 JB |
3392 | as_bad (_("cannot do %s %u byte relocation"), |
3393 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3394 | } |
3395 | ||
0cc9e1d3 | 3396 | return NO_RELOC; |
252b5132 RH |
3397 | } |
3398 | ||
47926f60 KH |
3399 | /* Here we decide which fixups can be adjusted to make them relative to |
3400 | the beginning of the section instead of the symbol. Basically we need | |
3401 | to make sure that the dynamic relocations are done correctly, so in | |
3402 | some cases we force the original symbol to be used. */ | |
3403 | ||
252b5132 | 3404 | int |
e3bb37b5 | 3405 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3406 | { |
6d249963 | 3407 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3408 | if (!IS_ELF) |
31312f95 AM |
3409 | return 1; |
3410 | ||
a161fe53 AM |
3411 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3412 | mode. */ | |
3413 | if (use_rela_relocations | |
3414 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3415 | && fixP->fx_pcrel) | |
252b5132 | 3416 | return 0; |
31312f95 | 3417 | |
8d01d9a9 AJ |
3418 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3419 | and changed later by validate_fix. */ | |
3420 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3421 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3422 | return 0; | |
3423 | ||
8fd4256d L |
3424 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3425 | for size relocations. */ | |
3426 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3427 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3428 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3429 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3430 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3431 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3432 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3433 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3434 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3435 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3436 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3437 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3438 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3439 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3440 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3441 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3442 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3443 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3444 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3445 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3446 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3447 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3448 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3449 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3450 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3451 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3452 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3453 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3454 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3455 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3456 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3457 | return 0; | |
31312f95 | 3458 | #endif |
252b5132 RH |
3459 | return 1; |
3460 | } | |
252b5132 | 3461 | |
b4cac588 | 3462 | static int |
e3bb37b5 | 3463 | intel_float_operand (const char *mnemonic) |
252b5132 | 3464 | { |
9306ca4a JB |
3465 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3466 | operands, hence the code here is free to improperly handle opcodes that | |
3467 | have no operands (for better performance and smaller code). */ | |
3468 | ||
3469 | if (mnemonic[0] != 'f') | |
3470 | return 0; /* non-math */ | |
3471 | ||
3472 | switch (mnemonic[1]) | |
3473 | { | |
3474 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3475 | the fs segment override prefix not currently handled because no | |
3476 | call path can make opcodes without operands get here */ | |
3477 | case 'i': | |
3478 | return 2 /* integer op */; | |
3479 | case 'l': | |
3480 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3481 | return 3; /* fldcw/fldenv */ | |
3482 | break; | |
3483 | case 'n': | |
3484 | if (mnemonic[2] != 'o' /* fnop */) | |
3485 | return 3; /* non-waiting control op */ | |
3486 | break; | |
3487 | case 'r': | |
3488 | if (mnemonic[2] == 's') | |
3489 | return 3; /* frstor/frstpm */ | |
3490 | break; | |
3491 | case 's': | |
3492 | if (mnemonic[2] == 'a') | |
3493 | return 3; /* fsave */ | |
3494 | if (mnemonic[2] == 't') | |
3495 | { | |
3496 | switch (mnemonic[3]) | |
3497 | { | |
3498 | case 'c': /* fstcw */ | |
3499 | case 'd': /* fstdw */ | |
3500 | case 'e': /* fstenv */ | |
3501 | case 's': /* fsts[gw] */ | |
3502 | return 3; | |
3503 | } | |
3504 | } | |
3505 | break; | |
3506 | case 'x': | |
3507 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3508 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3509 | break; | |
3510 | } | |
252b5132 | 3511 | |
9306ca4a | 3512 | return 1; |
252b5132 RH |
3513 | } |
3514 | ||
c0f3af97 L |
3515 | /* Build the VEX prefix. */ |
3516 | ||
3517 | static void | |
d3ce72d0 | 3518 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3519 | { |
3520 | unsigned int register_specifier; | |
3521 | unsigned int implied_prefix; | |
3522 | unsigned int vector_length; | |
03751133 | 3523 | unsigned int w; |
c0f3af97 L |
3524 | |
3525 | /* Check register specifier. */ | |
3526 | if (i.vex.register_specifier) | |
43234a1e L |
3527 | { |
3528 | register_specifier = | |
3529 | ~register_number (i.vex.register_specifier) & 0xf; | |
3530 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3531 | } | |
c0f3af97 L |
3532 | else |
3533 | register_specifier = 0xf; | |
3534 | ||
79f0fa25 L |
3535 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3536 | if there are more than 1 register operand. */ | |
3537 | if (i.reg_operands > 1 | |
3538 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3539 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3540 | && i.operands == i.reg_operands |
dbbc8b7e | 3541 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3542 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3543 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3544 | && i.rex == REX_B) |
3545 | { | |
3546 | unsigned int xchg = i.operands - 1; | |
3547 | union i386_op temp_op; | |
3548 | i386_operand_type temp_type; | |
3549 | ||
3550 | temp_type = i.types[xchg]; | |
3551 | i.types[xchg] = i.types[0]; | |
3552 | i.types[0] = temp_type; | |
3553 | temp_op = i.op[xchg]; | |
3554 | i.op[xchg] = i.op[0]; | |
3555 | i.op[0] = temp_op; | |
3556 | ||
9c2799c2 | 3557 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3558 | |
3559 | i.rex = REX_R; | |
3560 | xchg = i.rm.regmem; | |
3561 | i.rm.regmem = i.rm.reg; | |
3562 | i.rm.reg = xchg; | |
3563 | ||
dbbc8b7e JB |
3564 | if (i.tm.opcode_modifier.d) |
3565 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3566 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3567 | else /* Use the next insn. */ | |
3568 | i.tm = t[1]; | |
fa99fab2 L |
3569 | } |
3570 | ||
79dec6b7 JB |
3571 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3572 | are no memory operands and at least 3 register ones. */ | |
3573 | if (i.reg_operands >= 3 | |
3574 | && i.vec_encoding != vex_encoding_vex3 | |
3575 | && i.reg_operands == i.operands - i.imm_operands | |
3576 | && i.tm.opcode_modifier.vex | |
3577 | && i.tm.opcode_modifier.commutative | |
3578 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3579 | && i.rex == REX_B | |
3580 | && i.vex.register_specifier | |
3581 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3582 | { | |
3583 | unsigned int xchg = i.operands - i.reg_operands; | |
3584 | union i386_op temp_op; | |
3585 | i386_operand_type temp_type; | |
3586 | ||
3587 | gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F); | |
3588 | gas_assert (!i.tm.opcode_modifier.sae); | |
3589 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3590 | &i.types[i.operands - 3])); | |
3591 | gas_assert (i.rm.mode == 3); | |
3592 | ||
3593 | temp_type = i.types[xchg]; | |
3594 | i.types[xchg] = i.types[xchg + 1]; | |
3595 | i.types[xchg + 1] = temp_type; | |
3596 | temp_op = i.op[xchg]; | |
3597 | i.op[xchg] = i.op[xchg + 1]; | |
3598 | i.op[xchg + 1] = temp_op; | |
3599 | ||
3600 | i.rex = 0; | |
3601 | xchg = i.rm.regmem | 8; | |
3602 | i.rm.regmem = ~register_specifier & 0xf; | |
3603 | gas_assert (!(i.rm.regmem & 8)); | |
3604 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3605 | register_specifier = ~xchg & 0xf; | |
3606 | } | |
3607 | ||
539f890d L |
3608 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3609 | vector_length = avxscalar; | |
10c17abd JB |
3610 | else if (i.tm.opcode_modifier.vex == VEX256) |
3611 | vector_length = 1; | |
539f890d | 3612 | else |
10c17abd | 3613 | { |
56522fc5 | 3614 | unsigned int op; |
10c17abd | 3615 | |
c7213af9 L |
3616 | /* Determine vector length from the last multi-length vector |
3617 | operand. */ | |
10c17abd | 3618 | vector_length = 0; |
56522fc5 | 3619 | for (op = t->operands; op--;) |
10c17abd JB |
3620 | if (t->operand_types[op].bitfield.xmmword |
3621 | && t->operand_types[op].bitfield.ymmword | |
3622 | && i.types[op].bitfield.ymmword) | |
3623 | { | |
3624 | vector_length = 1; | |
3625 | break; | |
3626 | } | |
3627 | } | |
c0f3af97 L |
3628 | |
3629 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3630 | { | |
3631 | case 0: | |
3632 | implied_prefix = 0; | |
3633 | break; | |
3634 | case DATA_PREFIX_OPCODE: | |
3635 | implied_prefix = 1; | |
3636 | break; | |
3637 | case REPE_PREFIX_OPCODE: | |
3638 | implied_prefix = 2; | |
3639 | break; | |
3640 | case REPNE_PREFIX_OPCODE: | |
3641 | implied_prefix = 3; | |
3642 | break; | |
3643 | default: | |
3644 | abort (); | |
3645 | } | |
3646 | ||
03751133 L |
3647 | /* Check the REX.W bit and VEXW. */ |
3648 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3649 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3650 | else if (i.tm.opcode_modifier.vexw) | |
3651 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3652 | else | |
931d03b7 | 3653 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3654 | |
c0f3af97 | 3655 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3656 | if (w == 0 |
3657 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3658 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3659 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3660 | { | |
3661 | /* 2-byte VEX prefix. */ | |
3662 | unsigned int r; | |
3663 | ||
3664 | i.vex.length = 2; | |
3665 | i.vex.bytes[0] = 0xc5; | |
3666 | ||
3667 | /* Check the REX.R bit. */ | |
3668 | r = (i.rex & REX_R) ? 0 : 1; | |
3669 | i.vex.bytes[1] = (r << 7 | |
3670 | | register_specifier << 3 | |
3671 | | vector_length << 2 | |
3672 | | implied_prefix); | |
3673 | } | |
3674 | else | |
3675 | { | |
3676 | /* 3-byte VEX prefix. */ | |
03751133 | 3677 | unsigned int m; |
c0f3af97 | 3678 | |
f88c9eb0 | 3679 | i.vex.length = 3; |
f88c9eb0 | 3680 | |
7f399153 | 3681 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3682 | { |
7f399153 L |
3683 | case VEX0F: |
3684 | m = 0x1; | |
80de6e00 | 3685 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3686 | break; |
3687 | case VEX0F38: | |
3688 | m = 0x2; | |
80de6e00 | 3689 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3690 | break; |
3691 | case VEX0F3A: | |
3692 | m = 0x3; | |
80de6e00 | 3693 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3694 | break; |
3695 | case XOP08: | |
5dd85c99 SP |
3696 | m = 0x8; |
3697 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3698 | break; |
3699 | case XOP09: | |
f88c9eb0 SP |
3700 | m = 0x9; |
3701 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3702 | break; |
3703 | case XOP0A: | |
f88c9eb0 SP |
3704 | m = 0xa; |
3705 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3706 | break; |
3707 | default: | |
3708 | abort (); | |
f88c9eb0 | 3709 | } |
c0f3af97 | 3710 | |
c0f3af97 L |
3711 | /* The high 3 bits of the second VEX byte are 1's compliment |
3712 | of RXB bits from REX. */ | |
3713 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3714 | ||
c0f3af97 L |
3715 | i.vex.bytes[2] = (w << 7 |
3716 | | register_specifier << 3 | |
3717 | | vector_length << 2 | |
3718 | | implied_prefix); | |
3719 | } | |
3720 | } | |
3721 | ||
e771e7c9 JB |
3722 | static INLINE bfd_boolean |
3723 | is_evex_encoding (const insn_template *t) | |
3724 | { | |
7091c612 | 3725 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3726 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3727 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3728 | } |
3729 | ||
7a8655d2 JB |
3730 | static INLINE bfd_boolean |
3731 | is_any_vex_encoding (const insn_template *t) | |
3732 | { | |
3733 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3734 | || is_evex_encoding (t); | |
3735 | } | |
3736 | ||
43234a1e L |
3737 | /* Build the EVEX prefix. */ |
3738 | ||
3739 | static void | |
3740 | build_evex_prefix (void) | |
3741 | { | |
3742 | unsigned int register_specifier; | |
3743 | unsigned int implied_prefix; | |
3744 | unsigned int m, w; | |
3745 | rex_byte vrex_used = 0; | |
3746 | ||
3747 | /* Check register specifier. */ | |
3748 | if (i.vex.register_specifier) | |
3749 | { | |
3750 | gas_assert ((i.vrex & REX_X) == 0); | |
3751 | ||
3752 | register_specifier = i.vex.register_specifier->reg_num; | |
3753 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3754 | register_specifier += 8; | |
3755 | /* The upper 16 registers are encoded in the fourth byte of the | |
3756 | EVEX prefix. */ | |
3757 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3758 | i.vex.bytes[3] = 0x8; | |
3759 | register_specifier = ~register_specifier & 0xf; | |
3760 | } | |
3761 | else | |
3762 | { | |
3763 | register_specifier = 0xf; | |
3764 | ||
3765 | /* Encode upper 16 vector index register in the fourth byte of | |
3766 | the EVEX prefix. */ | |
3767 | if (!(i.vrex & REX_X)) | |
3768 | i.vex.bytes[3] = 0x8; | |
3769 | else | |
3770 | vrex_used |= REX_X; | |
3771 | } | |
3772 | ||
3773 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3774 | { | |
3775 | case 0: | |
3776 | implied_prefix = 0; | |
3777 | break; | |
3778 | case DATA_PREFIX_OPCODE: | |
3779 | implied_prefix = 1; | |
3780 | break; | |
3781 | case REPE_PREFIX_OPCODE: | |
3782 | implied_prefix = 2; | |
3783 | break; | |
3784 | case REPNE_PREFIX_OPCODE: | |
3785 | implied_prefix = 3; | |
3786 | break; | |
3787 | default: | |
3788 | abort (); | |
3789 | } | |
3790 | ||
3791 | /* 4 byte EVEX prefix. */ | |
3792 | i.vex.length = 4; | |
3793 | i.vex.bytes[0] = 0x62; | |
3794 | ||
3795 | /* mmmm bits. */ | |
3796 | switch (i.tm.opcode_modifier.vexopcode) | |
3797 | { | |
3798 | case VEX0F: | |
3799 | m = 1; | |
3800 | break; | |
3801 | case VEX0F38: | |
3802 | m = 2; | |
3803 | break; | |
3804 | case VEX0F3A: | |
3805 | m = 3; | |
3806 | break; | |
3807 | default: | |
3808 | abort (); | |
3809 | break; | |
3810 | } | |
3811 | ||
3812 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3813 | bits from REX. */ | |
3814 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3815 | ||
3816 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3817 | REX_R bit in VREX. */ | |
3818 | if (!(i.vrex & REX_R)) | |
3819 | i.vex.bytes[1] |= 0x10; | |
3820 | else | |
3821 | vrex_used |= REX_R; | |
3822 | ||
3823 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3824 | { | |
3825 | /* When all operands are registers, the REX_X bit in REX is not | |
3826 | used. We reuse it to encode the upper 16 registers, which is | |
3827 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3828 | as 1's compliment. */ | |
3829 | if ((i.vrex & REX_B)) | |
3830 | { | |
3831 | vrex_used |= REX_B; | |
3832 | i.vex.bytes[1] &= ~0x40; | |
3833 | } | |
3834 | } | |
3835 | ||
3836 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3837 | i.vrex &= ~vrex_used; | |
3838 | gas_assert (i.vrex == 0); | |
3839 | ||
6865c043 L |
3840 | /* Check the REX.W bit and VEXW. */ |
3841 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3842 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3843 | else if (i.tm.opcode_modifier.vexw) | |
3844 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3845 | else | |
931d03b7 | 3846 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3847 | |
3848 | /* Encode the U bit. */ | |
3849 | implied_prefix |= 0x4; | |
3850 | ||
3851 | /* The third byte of the EVEX prefix. */ | |
3852 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3853 | ||
3854 | /* The fourth byte of the EVEX prefix. */ | |
3855 | /* The zeroing-masking bit. */ | |
3856 | if (i.mask && i.mask->zeroing) | |
3857 | i.vex.bytes[3] |= 0x80; | |
3858 | ||
3859 | /* Don't always set the broadcast bit if there is no RC. */ | |
3860 | if (!i.rounding) | |
3861 | { | |
3862 | /* Encode the vector length. */ | |
3863 | unsigned int vec_length; | |
3864 | ||
e771e7c9 JB |
3865 | if (!i.tm.opcode_modifier.evex |
3866 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3867 | { | |
56522fc5 | 3868 | unsigned int op; |
e771e7c9 | 3869 | |
c7213af9 L |
3870 | /* Determine vector length from the last multi-length vector |
3871 | operand. */ | |
e771e7c9 | 3872 | vec_length = 0; |
56522fc5 | 3873 | for (op = i.operands; op--;) |
e771e7c9 JB |
3874 | if (i.tm.operand_types[op].bitfield.xmmword |
3875 | + i.tm.operand_types[op].bitfield.ymmword | |
3876 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3877 | { | |
3878 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3879 | { |
3880 | i.tm.opcode_modifier.evex = EVEX512; | |
3881 | break; | |
3882 | } | |
e771e7c9 | 3883 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3884 | { |
3885 | i.tm.opcode_modifier.evex = EVEX256; | |
3886 | break; | |
3887 | } | |
e771e7c9 | 3888 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3889 | { |
3890 | i.tm.opcode_modifier.evex = EVEX128; | |
3891 | break; | |
3892 | } | |
625cbd7a JB |
3893 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3894 | { | |
4a1b91ea | 3895 | switch (i.broadcast->bytes) |
625cbd7a JB |
3896 | { |
3897 | case 64: | |
3898 | i.tm.opcode_modifier.evex = EVEX512; | |
3899 | break; | |
3900 | case 32: | |
3901 | i.tm.opcode_modifier.evex = EVEX256; | |
3902 | break; | |
3903 | case 16: | |
3904 | i.tm.opcode_modifier.evex = EVEX128; | |
3905 | break; | |
3906 | default: | |
c7213af9 | 3907 | abort (); |
625cbd7a | 3908 | } |
c7213af9 | 3909 | break; |
625cbd7a | 3910 | } |
e771e7c9 | 3911 | } |
c7213af9 | 3912 | |
56522fc5 | 3913 | if (op >= MAX_OPERANDS) |
c7213af9 | 3914 | abort (); |
e771e7c9 JB |
3915 | } |
3916 | ||
43234a1e L |
3917 | switch (i.tm.opcode_modifier.evex) |
3918 | { | |
3919 | case EVEXLIG: /* LL' is ignored */ | |
3920 | vec_length = evexlig << 5; | |
3921 | break; | |
3922 | case EVEX128: | |
3923 | vec_length = 0 << 5; | |
3924 | break; | |
3925 | case EVEX256: | |
3926 | vec_length = 1 << 5; | |
3927 | break; | |
3928 | case EVEX512: | |
3929 | vec_length = 2 << 5; | |
3930 | break; | |
3931 | default: | |
3932 | abort (); | |
3933 | break; | |
3934 | } | |
3935 | i.vex.bytes[3] |= vec_length; | |
3936 | /* Encode the broadcast bit. */ | |
3937 | if (i.broadcast) | |
3938 | i.vex.bytes[3] |= 0x10; | |
3939 | } | |
3940 | else | |
3941 | { | |
3942 | if (i.rounding->type != saeonly) | |
3943 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3944 | else | |
d3d3c6db | 3945 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3946 | } |
3947 | ||
3948 | if (i.mask && i.mask->mask) | |
3949 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3950 | } | |
3951 | ||
65da13b5 L |
3952 | static void |
3953 | process_immext (void) | |
3954 | { | |
3955 | expressionS *exp; | |
3956 | ||
c0f3af97 | 3957 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3958 | which is coded in the same place as an 8-bit immediate field |
3959 | would be. Here we fake an 8-bit immediate operand from the | |
3960 | opcode suffix stored in tm.extension_opcode. | |
3961 | ||
c1e679ec | 3962 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3963 | 3 argument instructions. */ |
65da13b5 | 3964 | |
43234a1e | 3965 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3966 | && (i.operands <= 2 |
7a8655d2 | 3967 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3968 | && i.operands <= 4))); |
65da13b5 L |
3969 | |
3970 | exp = &im_expressions[i.imm_operands++]; | |
3971 | i.op[i.operands].imms = exp; | |
3972 | i.types[i.operands] = imm8; | |
3973 | i.operands++; | |
3974 | exp->X_op = O_constant; | |
3975 | exp->X_add_number = i.tm.extension_opcode; | |
3976 | i.tm.extension_opcode = None; | |
3977 | } | |
3978 | ||
42164a71 L |
3979 | |
3980 | static int | |
3981 | check_hle (void) | |
3982 | { | |
3983 | switch (i.tm.opcode_modifier.hleprefixok) | |
3984 | { | |
3985 | default: | |
3986 | abort (); | |
82c2def5 | 3987 | case HLEPrefixNone: |
165de32a L |
3988 | as_bad (_("invalid instruction `%s' after `%s'"), |
3989 | i.tm.name, i.hle_prefix); | |
42164a71 | 3990 | return 0; |
82c2def5 | 3991 | case HLEPrefixLock: |
42164a71 L |
3992 | if (i.prefix[LOCK_PREFIX]) |
3993 | return 1; | |
165de32a | 3994 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3995 | return 0; |
82c2def5 | 3996 | case HLEPrefixAny: |
42164a71 | 3997 | return 1; |
82c2def5 | 3998 | case HLEPrefixRelease: |
42164a71 L |
3999 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4000 | { | |
4001 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
4002 | i.tm.name); | |
4003 | return 0; | |
4004 | } | |
8dc0818e | 4005 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4006 | { |
4007 | as_bad (_("memory destination needed for instruction `%s'" | |
4008 | " after `xrelease'"), i.tm.name); | |
4009 | return 0; | |
4010 | } | |
4011 | return 1; | |
4012 | } | |
4013 | } | |
4014 | ||
b6f8c7c4 L |
4015 | /* Try the shortest encoding by shortening operand size. */ |
4016 | ||
4017 | static void | |
4018 | optimize_encoding (void) | |
4019 | { | |
a0a1771e | 4020 | unsigned int j; |
b6f8c7c4 L |
4021 | |
4022 | if (optimize_for_space | |
72aea328 | 4023 | && !is_any_vex_encoding (&i.tm) |
b6f8c7c4 L |
4024 | && i.reg_operands == 1 |
4025 | && i.imm_operands == 1 | |
4026 | && !i.types[1].bitfield.byte | |
4027 | && i.op[0].imms->X_op == O_constant | |
4028 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
72aea328 | 4029 | && (i.tm.base_opcode == 0xa8 |
b6f8c7c4 L |
4030 | || (i.tm.base_opcode == 0xf6 |
4031 | && i.tm.extension_opcode == 0x0))) | |
4032 | { | |
4033 | /* Optimize: -Os: | |
4034 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4035 | */ | |
4036 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4037 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4038 | { | |
4039 | i.types[1].bitfield.byte = 1; | |
4040 | /* Ignore the suffix. */ | |
4041 | i.suffix = 0; | |
7697afb6 JB |
4042 | /* Convert to byte registers. */ |
4043 | if (i.types[1].bitfield.word) | |
4044 | j = 16; | |
4045 | else if (i.types[1].bitfield.dword) | |
4046 | j = 32; | |
4047 | else | |
4048 | j = 48; | |
4049 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4050 | j += 8; | |
4051 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4052 | } |
4053 | } | |
4054 | else if (flag_code == CODE_64BIT | |
72aea328 | 4055 | && !is_any_vex_encoding (&i.tm) |
d3d50934 L |
4056 | && ((i.types[1].bitfield.qword |
4057 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4058 | && i.imm_operands == 1 |
4059 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4060 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4061 | && i.tm.extension_opcode == None |
4062 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4063 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
72aea328 JB |
4064 | && ((i.tm.base_opcode == 0x24 |
4065 | || i.tm.base_opcode == 0xa8) | |
b6f8c7c4 L |
4066 | || (i.tm.base_opcode == 0x80 |
4067 | && i.tm.extension_opcode == 0x4) | |
4068 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4069 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4070 | && i.tm.extension_opcode == 0x0))) |
4071 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4072 | && i.tm.base_opcode == 0x83 | |
4073 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4074 | || (i.types[0].bitfield.qword |
4075 | && ((i.reg_operands == 2 | |
4076 | && i.op[0].regs == i.op[1].regs | |
72aea328 JB |
4077 | && (i.tm.base_opcode == 0x30 |
4078 | || i.tm.base_opcode == 0x28)) | |
d3d50934 L |
4079 | || (i.reg_operands == 1 |
4080 | && i.operands == 1 | |
72aea328 | 4081 | && i.tm.base_opcode == 0x30))))) |
b6f8c7c4 L |
4082 | { |
4083 | /* Optimize: -O: | |
4084 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4085 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4086 | testq $imm31, %r64 -> testl $imm31, %r32 |
4087 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4088 | subq %r64, %r64 -> subl %r32, %r32 | |
4089 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4090 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4091 | */ | |
4092 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4093 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4094 | { |
4095 | /* Handle | |
4096 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4097 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4098 | */ | |
4099 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4100 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4101 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4102 | i.types[0].bitfield.imm32 = 1; | |
4103 | i.types[0].bitfield.imm32s = 0; | |
4104 | i.types[0].bitfield.imm64 = 0; | |
4105 | i.types[1].bitfield.dword = 1; | |
4106 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4107 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4108 | { |
4109 | /* Handle | |
4110 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4111 | */ | |
507916b8 | 4112 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4113 | i.tm.extension_opcode = None; |
507916b8 | 4114 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4115 | i.tm.opcode_modifier.modrm = 0; |
4116 | } | |
4117 | } | |
4118 | } | |
5641ec01 JB |
4119 | else if (optimize > 1 |
4120 | && !optimize_for_space | |
72aea328 | 4121 | && !is_any_vex_encoding (&i.tm) |
5641ec01 JB |
4122 | && i.reg_operands == 2 |
4123 | && i.op[0].regs == i.op[1].regs | |
4124 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4125 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4126 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4127 | { | |
4128 | /* Optimize: -O2: | |
4129 | andb %rN, %rN -> testb %rN, %rN | |
4130 | andw %rN, %rN -> testw %rN, %rN | |
4131 | andq %rN, %rN -> testq %rN, %rN | |
4132 | orb %rN, %rN -> testb %rN, %rN | |
4133 | orw %rN, %rN -> testw %rN, %rN | |
4134 | orq %rN, %rN -> testq %rN, %rN | |
4135 | ||
4136 | and outside of 64-bit mode | |
4137 | ||
4138 | andl %rN, %rN -> testl %rN, %rN | |
4139 | orl %rN, %rN -> testl %rN, %rN | |
4140 | */ | |
4141 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4142 | } | |
99112332 | 4143 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4144 | && i.op[0].regs == i.op[1].regs |
4145 | && !i.types[2].bitfield.xmmword | |
4146 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 4147 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 4148 | && !i.rounding |
e771e7c9 | 4149 | && is_evex_encoding (&i.tm) |
80c34c38 | 4150 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4151 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4152 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4153 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4154 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
4155 | && ((i.tm.base_opcode == 0x55 |
4156 | || i.tm.base_opcode == 0x6655 | |
4157 | || i.tm.base_opcode == 0x66df | |
4158 | || i.tm.base_opcode == 0x57 | |
4159 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4160 | || i.tm.base_opcode == 0x66ef |
4161 | || i.tm.base_opcode == 0x66f8 | |
4162 | || i.tm.base_opcode == 0x66f9 | |
4163 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4164 | || i.tm.base_opcode == 0x66fb |
4165 | || i.tm.base_opcode == 0x42 | |
4166 | || i.tm.base_opcode == 0x6642 | |
4167 | || i.tm.base_opcode == 0x47 | |
4168 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4169 | && i.tm.extension_opcode == None)) |
4170 | { | |
99112332 | 4171 | /* Optimize: -O1: |
8305403a L |
4172 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4173 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4174 | EVEX VOP %zmmM, %zmmM, %zmmN |
4175 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4176 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4177 | EVEX VOP %ymmM, %ymmM, %ymmN |
4178 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4179 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4180 | VEX VOP %ymmM, %ymmM, %ymmN |
4181 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4182 | VOP, one of vpandn and vpxor: | |
4183 | VEX VOP %ymmM, %ymmM, %ymmN | |
4184 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4185 | VOP, one of vpandnd and vpandnq: | |
4186 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4187 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4188 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4189 | EVEX VOP %ymmM, %ymmM, %ymmN |
4190 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4191 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4192 | VOP, one of vpxord and vpxorq: |
4193 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4194 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4195 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4196 | EVEX VOP %ymmM, %ymmM, %ymmN |
4197 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4198 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4199 | VOP, one of kxord and kxorq: |
4200 | VEX VOP %kM, %kM, %kN | |
4201 | -> VEX kxorw %kM, %kM, %kN | |
4202 | VOP, one of kandnd and kandnq: | |
4203 | VEX VOP %kM, %kM, %kN | |
4204 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4205 | */ |
e771e7c9 | 4206 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4207 | { |
7b1d7ca1 | 4208 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4209 | { |
4210 | i.tm.opcode_modifier.vex = VEX128; | |
4211 | i.tm.opcode_modifier.vexw = VEXW0; | |
4212 | i.tm.opcode_modifier.evex = 0; | |
4213 | } | |
7b1d7ca1 | 4214 | else if (optimize > 1) |
dd22218c L |
4215 | i.tm.opcode_modifier.evex = EVEX128; |
4216 | else | |
4217 | return; | |
b6f8c7c4 | 4218 | } |
f74a6307 | 4219 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 JB |
4220 | { |
4221 | i.tm.base_opcode &= 0xff; | |
4222 | i.tm.opcode_modifier.vexw = VEXW0; | |
4223 | } | |
b6f8c7c4 L |
4224 | else |
4225 | i.tm.opcode_modifier.vex = VEX128; | |
4226 | ||
4227 | if (i.tm.opcode_modifier.vex) | |
4228 | for (j = 0; j < 3; j++) | |
4229 | { | |
4230 | i.types[j].bitfield.xmmword = 1; | |
4231 | i.types[j].bitfield.ymmword = 0; | |
4232 | } | |
4233 | } | |
392a5972 | 4234 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4235 | && !i.types[0].bitfield.zmmword |
392a5972 | 4236 | && !i.types[1].bitfield.zmmword |
97ed31ae | 4237 | && !i.mask |
a0a1771e | 4238 | && !i.broadcast |
97ed31ae | 4239 | && is_evex_encoding (&i.tm) |
392a5972 L |
4240 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4241 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
a0a1771e JB |
4242 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f |
4243 | || (i.tm.base_opcode & ~4) == 0x66db | |
4244 | || (i.tm.base_opcode & ~4) == 0x66eb) | |
97ed31ae L |
4245 | && i.tm.extension_opcode == None) |
4246 | { | |
4247 | /* Optimize: -O1: | |
4248 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4249 | vmovdqu32 and vmovdqu64: | |
4250 | EVEX VOP %xmmM, %xmmN | |
4251 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4252 | EVEX VOP %ymmM, %ymmN | |
4253 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4254 | EVEX VOP %xmmM, mem | |
4255 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4256 | EVEX VOP %ymmM, mem | |
4257 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4258 | EVEX VOP mem, %xmmN | |
4259 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4260 | EVEX VOP mem, %ymmN | |
4261 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4262 | VOP, one of vpand, vpandn, vpor, vpxor: |
4263 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4264 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4265 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4266 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4267 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4268 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4269 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4270 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4271 | */ |
a0a1771e | 4272 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4273 | if (operand_type_check (i.types[j], disp) |
4274 | && i.op[j].disps->X_op == O_constant) | |
4275 | { | |
4276 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4277 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4278 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4279 | int evex_disp8, vex_disp8; | |
4280 | unsigned int memshift = i.memshift; | |
4281 | offsetT n = i.op[j].disps->X_add_number; | |
4282 | ||
4283 | evex_disp8 = fits_in_disp8 (n); | |
4284 | i.memshift = 0; | |
4285 | vex_disp8 = fits_in_disp8 (n); | |
4286 | if (evex_disp8 != vex_disp8) | |
4287 | { | |
4288 | i.memshift = memshift; | |
4289 | return; | |
4290 | } | |
4291 | ||
4292 | i.types[j].bitfield.disp8 = vex_disp8; | |
4293 | break; | |
4294 | } | |
4295 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4296 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4297 | i.tm.opcode_modifier.vex |
4298 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4299 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 JB |
4300 | /* VPAND, VPOR, and VPXOR are commutative. */ |
4301 | if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df) | |
4302 | i.tm.opcode_modifier.commutative = 1; | |
97ed31ae L |
4303 | i.tm.opcode_modifier.evex = 0; |
4304 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4305 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4306 | i.tm.opcode_modifier.disp8memshift = 0; |
4307 | i.memshift = 0; | |
a0a1771e JB |
4308 | if (j < i.operands) |
4309 | i.types[j].bitfield.disp8 | |
4310 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4311 | } |
b6f8c7c4 L |
4312 | } |
4313 | ||
252b5132 RH |
4314 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4315 | machine dependent instruction. This function is supposed to emit | |
4316 | the frags/bytes it assembles to. */ | |
4317 | ||
4318 | void | |
65da13b5 | 4319 | md_assemble (char *line) |
252b5132 | 4320 | { |
40fb9820 | 4321 | unsigned int j; |
83b16ac6 | 4322 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4323 | const insn_template *t; |
252b5132 | 4324 | |
47926f60 | 4325 | /* Initialize globals. */ |
252b5132 RH |
4326 | memset (&i, '\0', sizeof (i)); |
4327 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4328 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4329 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4330 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4331 | save_stack_p = save_stack; |
252b5132 RH |
4332 | |
4333 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4334 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4335 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4336 | |
29b0f896 AM |
4337 | line = parse_insn (line, mnemonic); |
4338 | if (line == NULL) | |
4339 | return; | |
83b16ac6 | 4340 | mnem_suffix = i.suffix; |
252b5132 | 4341 | |
29b0f896 | 4342 | line = parse_operands (line, mnemonic); |
ee86248c | 4343 | this_operand = -1; |
8325cc63 JB |
4344 | xfree (i.memop1_string); |
4345 | i.memop1_string = NULL; | |
29b0f896 AM |
4346 | if (line == NULL) |
4347 | return; | |
252b5132 | 4348 | |
29b0f896 AM |
4349 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4350 | operands at hand. */ | |
4351 | ||
eedb0f2c JB |
4352 | /* All Intel opcodes have reversed operands except for "bound", "enter" |
4353 | "monitor*", and "mwait*". We also don't reverse intersegment "jmp" | |
4354 | and "call" instructions with 2 immediate operands so that the immediate | |
4355 | segment precedes the offset, as it does when in AT&T mode. */ | |
4d456e3d L |
4356 | if (intel_syntax |
4357 | && i.operands > 1 | |
29b0f896 | 4358 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4359 | && (strcmp (mnemonic, "invlpga") != 0) |
eedb0f2c JB |
4360 | && (strncmp (mnemonic, "monitor", 7) != 0) |
4361 | && (strncmp (mnemonic, "mwait", 5) != 0) | |
40fb9820 L |
4362 | && !(operand_type_check (i.types[0], imm) |
4363 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4364 | swap_operands (); |
4365 | ||
ec56d5c0 JB |
4366 | /* The order of the immediates should be reversed |
4367 | for 2 immediates extrq and insertq instructions */ | |
4368 | if (i.imm_operands == 2 | |
4369 | && (strcmp (mnemonic, "extrq") == 0 | |
4370 | || strcmp (mnemonic, "insertq") == 0)) | |
4371 | swap_2_operands (0, 1); | |
4372 | ||
29b0f896 AM |
4373 | if (i.imm_operands) |
4374 | optimize_imm (); | |
4375 | ||
b300c311 L |
4376 | /* Don't optimize displacement for movabs since it only takes 64bit |
4377 | displacement. */ | |
4378 | if (i.disp_operands | |
a501d77e | 4379 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4380 | && (flag_code != CODE_64BIT |
4381 | || strcmp (mnemonic, "movabs") != 0)) | |
4382 | optimize_disp (); | |
29b0f896 AM |
4383 | |
4384 | /* Next, we find a template that matches the given insn, | |
4385 | making sure the overlap of the given operands types is consistent | |
4386 | with the template operand types. */ | |
252b5132 | 4387 | |
83b16ac6 | 4388 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4389 | return; |
252b5132 | 4390 | |
7bab8ab5 | 4391 | if (sse_check != check_none |
81f8a913 | 4392 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4393 | && !i.tm.cpu_flags.bitfield.cpuavx |
569d50f1 | 4394 | && !i.tm.cpu_flags.bitfield.cpuavx512f |
daf50ae7 L |
4395 | && (i.tm.cpu_flags.bitfield.cpusse |
4396 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4397 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4398 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4399 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e | 4400 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
569d50f1 | 4401 | || i.tm.cpu_flags.bitfield.cpusse4a |
6e3e5c9e JB |
4402 | || i.tm.cpu_flags.bitfield.cpupclmul |
4403 | || i.tm.cpu_flags.bitfield.cpuaes | |
569d50f1 | 4404 | || i.tm.cpu_flags.bitfield.cpusha |
6e3e5c9e | 4405 | || i.tm.cpu_flags.bitfield.cpugfni)) |
daf50ae7 | 4406 | { |
7bab8ab5 | 4407 | (sse_check == check_warning |
daf50ae7 L |
4408 | ? as_warn |
4409 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4410 | } | |
4411 | ||
40fb9820 | 4412 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4413 | if (!add_prefix (FWAIT_OPCODE)) |
4414 | return; | |
252b5132 | 4415 | |
d5de92cf L |
4416 | /* Check if REP prefix is OK. */ |
4417 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4418 | { | |
4419 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4420 | i.tm.name, i.rep_prefix); | |
4421 | return; | |
4422 | } | |
4423 | ||
c1ba0266 L |
4424 | /* Check for lock without a lockable instruction. Destination operand |
4425 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4426 | if (i.prefix[LOCK_PREFIX] |
4427 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4428 | || i.mem_operands == 0 |
4429 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4430 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4431 | { |
4432 | as_bad (_("expecting lockable instruction after `lock'")); | |
4433 | return; | |
4434 | } | |
4435 | ||
7a8655d2 JB |
4436 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4437 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4438 | { | |
4439 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4440 | return; | |
4441 | } | |
4442 | ||
42164a71 | 4443 | /* Check if HLE prefix is OK. */ |
165de32a | 4444 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4445 | return; |
4446 | ||
7e8b059b L |
4447 | /* Check BND prefix. */ |
4448 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4449 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4450 | ||
04ef582a | 4451 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4452 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4453 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4454 | |
327e8c42 JB |
4455 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4456 | { | |
4457 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4458 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4459 | else if (flag_code != CODE_16BIT | |
4460 | ? i.prefix[ADDR_PREFIX] | |
4461 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4462 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4463 | } | |
7e8b059b L |
4464 | |
4465 | /* Insert BND prefix. */ | |
76d3a78a JB |
4466 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4467 | { | |
4468 | if (!i.prefix[BND_PREFIX]) | |
4469 | add_prefix (BND_PREFIX_OPCODE); | |
4470 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4471 | { | |
4472 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4473 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4474 | } | |
4475 | } | |
7e8b059b | 4476 | |
29b0f896 | 4477 | /* Check string instruction segment overrides. */ |
51c8edf6 | 4478 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 4479 | { |
51c8edf6 | 4480 | gas_assert (i.mem_operands); |
29b0f896 | 4481 | if (!check_string ()) |
5dd0794d | 4482 | return; |
fc0763e6 | 4483 | i.disp_operands = 0; |
29b0f896 | 4484 | } |
5dd0794d | 4485 | |
b6f8c7c4 L |
4486 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4487 | optimize_encoding (); | |
4488 | ||
29b0f896 AM |
4489 | if (!process_suffix ()) |
4490 | return; | |
e413e4e9 | 4491 | |
bc0844ae L |
4492 | /* Update operand types. */ |
4493 | for (j = 0; j < i.operands; j++) | |
4494 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4495 | ||
29b0f896 AM |
4496 | /* Make still unresolved immediate matches conform to size of immediate |
4497 | given in i.suffix. */ | |
4498 | if (!finalize_imm ()) | |
4499 | return; | |
252b5132 | 4500 | |
40fb9820 | 4501 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4502 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4503 | |
9afe6eb8 L |
4504 | /* We only need to check those implicit registers for instructions |
4505 | with 3 operands or less. */ | |
4506 | if (i.operands <= 3) | |
4507 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
4508 | if (i.types[j].bitfield.instance != InstanceNone |
4509 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 4510 | i.reg_operands--; |
40fb9820 | 4511 | |
c0f3af97 L |
4512 | /* ImmExt should be processed after SSE2AVX. */ |
4513 | if (!i.tm.opcode_modifier.sse2avx | |
4514 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4515 | process_immext (); |
252b5132 | 4516 | |
29b0f896 AM |
4517 | /* For insns with operands there are more diddles to do to the opcode. */ |
4518 | if (i.operands) | |
4519 | { | |
4520 | if (!process_operands ()) | |
4521 | return; | |
4522 | } | |
40fb9820 | 4523 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4524 | { |
4525 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4526 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4527 | } | |
252b5132 | 4528 | |
7a8655d2 | 4529 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 4530 | { |
c1dc7af5 | 4531 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 4532 | { |
c1dc7af5 | 4533 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
4534 | i.tm.name); |
4535 | return; | |
4536 | } | |
c0f3af97 | 4537 | |
9e5e5283 L |
4538 | if (i.tm.opcode_modifier.vex) |
4539 | build_vex_prefix (t); | |
4540 | else | |
4541 | build_evex_prefix (); | |
4542 | } | |
43234a1e | 4543 | |
5dd85c99 SP |
4544 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4545 | instructions may define INT_OPCODE as well, so avoid this corner | |
4546 | case for those instructions that use MODRM. */ | |
4547 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4548 | && !i.tm.opcode_modifier.modrm |
4549 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4550 | { |
4551 | i.tm.base_opcode = INT3_OPCODE; | |
4552 | i.imm_operands = 0; | |
4553 | } | |
252b5132 | 4554 | |
0cfa3eb3 JB |
4555 | if ((i.tm.opcode_modifier.jump == JUMP |
4556 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
4557 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
4558 | && i.op[0].disps->X_op == O_constant) |
4559 | { | |
4560 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4561 | the absolute address given by the constant. Since ix86 jumps and | |
4562 | calls are pc relative, we need to generate a reloc. */ | |
4563 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4564 | i.op[0].disps->X_op = O_symbol; | |
4565 | } | |
252b5132 | 4566 | |
40fb9820 | 4567 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4568 | i.rex |= REX_W; |
252b5132 | 4569 | |
29b0f896 AM |
4570 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4571 | instruction already has a prefix, we need to convert old | |
4572 | registers to new ones. */ | |
773f551c | 4573 | |
bab6aec1 | 4574 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 4575 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 4576 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 4577 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
4578 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
4579 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4580 | && i.rex != 0)) |
4581 | { | |
4582 | int x; | |
726c5dcd | 4583 | |
29b0f896 AM |
4584 | i.rex |= REX_OPCODE; |
4585 | for (x = 0; x < 2; x++) | |
4586 | { | |
4587 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 4588 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 4589 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4590 | { |
3f93af61 | 4591 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
4592 | /* In case it is "hi" register, give up. */ |
4593 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4594 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4595 | "instruction requiring REX prefix."), |
a540244d | 4596 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4597 | |
29b0f896 AM |
4598 | /* Otherwise it is equivalent to the extended register. |
4599 | Since the encoding doesn't change this is merely | |
4600 | cosmetic cleanup for debug output. */ | |
4601 | ||
4602 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4603 | } |
29b0f896 AM |
4604 | } |
4605 | } | |
773f551c | 4606 | |
6b6b6807 L |
4607 | if (i.rex == 0 && i.rex_encoding) |
4608 | { | |
4609 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 4610 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
4611 | the REX_OPCODE byte. */ |
4612 | int x; | |
4613 | for (x = 0; x < 2; x++) | |
bab6aec1 | 4614 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
4615 | && i.types[x].bitfield.byte |
4616 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4617 | && i.op[x].regs->reg_num > 3) | |
4618 | { | |
3f93af61 | 4619 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
6b6b6807 L |
4620 | i.rex_encoding = FALSE; |
4621 | break; | |
4622 | } | |
4623 | ||
4624 | if (i.rex_encoding) | |
4625 | i.rex = REX_OPCODE; | |
4626 | } | |
4627 | ||
7ab9ffdd | 4628 | if (i.rex != 0) |
29b0f896 AM |
4629 | add_prefix (REX_OPCODE | i.rex); |
4630 | ||
4631 | /* We are ready to output the insn. */ | |
4632 | output_insn (); | |
e379e5f3 L |
4633 | |
4634 | last_insn.seg = now_seg; | |
4635 | ||
4636 | if (i.tm.opcode_modifier.isprefix) | |
4637 | { | |
4638 | last_insn.kind = last_insn_prefix; | |
4639 | last_insn.name = i.tm.name; | |
4640 | last_insn.file = as_where (&last_insn.line); | |
4641 | } | |
4642 | else | |
4643 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
4644 | } |
4645 | ||
4646 | static char * | |
e3bb37b5 | 4647 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4648 | { |
4649 | char *l = line; | |
4650 | char *token_start = l; | |
4651 | char *mnem_p; | |
5c6af06e | 4652 | int supported; |
d3ce72d0 | 4653 | const insn_template *t; |
b6169b20 | 4654 | char *dot_p = NULL; |
29b0f896 | 4655 | |
29b0f896 AM |
4656 | while (1) |
4657 | { | |
4658 | mnem_p = mnemonic; | |
4659 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4660 | { | |
b6169b20 L |
4661 | if (*mnem_p == '.') |
4662 | dot_p = mnem_p; | |
29b0f896 AM |
4663 | mnem_p++; |
4664 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4665 | { |
29b0f896 AM |
4666 | as_bad (_("no such instruction: `%s'"), token_start); |
4667 | return NULL; | |
4668 | } | |
4669 | l++; | |
4670 | } | |
4671 | if (!is_space_char (*l) | |
4672 | && *l != END_OF_INSN | |
e44823cf JB |
4673 | && (intel_syntax |
4674 | || (*l != PREFIX_SEPARATOR | |
4675 | && *l != ','))) | |
29b0f896 AM |
4676 | { |
4677 | as_bad (_("invalid character %s in mnemonic"), | |
4678 | output_invalid (*l)); | |
4679 | return NULL; | |
4680 | } | |
4681 | if (token_start == l) | |
4682 | { | |
e44823cf | 4683 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4684 | as_bad (_("expecting prefix; got nothing")); |
4685 | else | |
4686 | as_bad (_("expecting mnemonic; got nothing")); | |
4687 | return NULL; | |
4688 | } | |
45288df1 | 4689 | |
29b0f896 | 4690 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4691 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4692 | |
29b0f896 AM |
4693 | if (*l != END_OF_INSN |
4694 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4695 | && current_templates | |
40fb9820 | 4696 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4697 | { |
c6fb90c8 | 4698 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4699 | { |
4700 | as_bad ((flag_code != CODE_64BIT | |
4701 | ? _("`%s' is only supported in 64-bit mode") | |
4702 | : _("`%s' is not supported in 64-bit mode")), | |
4703 | current_templates->start->name); | |
4704 | return NULL; | |
4705 | } | |
29b0f896 AM |
4706 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4707 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
4708 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
4709 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 4710 | && flag_code != CODE_64BIT |
673fe0f0 | 4711 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
4712 | ^ (flag_code == CODE_16BIT))) |
4713 | { | |
4714 | as_bad (_("redundant %s prefix"), | |
4715 | current_templates->start->name); | |
4716 | return NULL; | |
45288df1 | 4717 | } |
86fa6981 | 4718 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4719 | { |
86fa6981 L |
4720 | /* Handle pseudo prefixes. */ |
4721 | switch (current_templates->start->base_opcode) | |
4722 | { | |
4723 | case 0x0: | |
4724 | /* {disp8} */ | |
4725 | i.disp_encoding = disp_encoding_8bit; | |
4726 | break; | |
4727 | case 0x1: | |
4728 | /* {disp32} */ | |
4729 | i.disp_encoding = disp_encoding_32bit; | |
4730 | break; | |
4731 | case 0x2: | |
4732 | /* {load} */ | |
4733 | i.dir_encoding = dir_encoding_load; | |
4734 | break; | |
4735 | case 0x3: | |
4736 | /* {store} */ | |
4737 | i.dir_encoding = dir_encoding_store; | |
4738 | break; | |
4739 | case 0x4: | |
42e04b36 L |
4740 | /* {vex} */ |
4741 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 L |
4742 | break; |
4743 | case 0x5: | |
4744 | /* {vex3} */ | |
4745 | i.vec_encoding = vex_encoding_vex3; | |
4746 | break; | |
4747 | case 0x6: | |
4748 | /* {evex} */ | |
4749 | i.vec_encoding = vex_encoding_evex; | |
4750 | break; | |
6b6b6807 L |
4751 | case 0x7: |
4752 | /* {rex} */ | |
4753 | i.rex_encoding = TRUE; | |
4754 | break; | |
b6f8c7c4 L |
4755 | case 0x8: |
4756 | /* {nooptimize} */ | |
4757 | i.no_optimize = TRUE; | |
4758 | break; | |
86fa6981 L |
4759 | default: |
4760 | abort (); | |
4761 | } | |
4762 | } | |
4763 | else | |
4764 | { | |
4765 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4766 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4767 | { |
4e9ac44a L |
4768 | case PREFIX_EXIST: |
4769 | return NULL; | |
4770 | case PREFIX_DS: | |
d777820b | 4771 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4772 | i.notrack_prefix = current_templates->start->name; |
4773 | break; | |
4774 | case PREFIX_REP: | |
4775 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4776 | i.hle_prefix = current_templates->start->name; | |
4777 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4778 | i.bnd_prefix = current_templates->start->name; | |
4779 | else | |
4780 | i.rep_prefix = current_templates->start->name; | |
4781 | break; | |
4782 | default: | |
4783 | break; | |
86fa6981 | 4784 | } |
29b0f896 AM |
4785 | } |
4786 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4787 | token_start = ++l; | |
4788 | } | |
4789 | else | |
4790 | break; | |
4791 | } | |
45288df1 | 4792 | |
30a55f88 | 4793 | if (!current_templates) |
b6169b20 | 4794 | { |
07d5e953 JB |
4795 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4796 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4797 | encoding. */ |
30a55f88 | 4798 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4799 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4800 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4801 | && dot_p[1] == 'd' |
4802 | && dot_p[2] == '8') | |
4803 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4804 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4805 | && dot_p[1] == 'd' |
4806 | && dot_p[2] == '3' | |
4807 | && dot_p[3] == '2') | |
a501d77e | 4808 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4809 | else |
4810 | goto check_suffix; | |
4811 | mnem_p = dot_p; | |
4812 | *dot_p = '\0'; | |
d3ce72d0 | 4813 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4814 | } |
4815 | ||
29b0f896 AM |
4816 | if (!current_templates) |
4817 | { | |
dc1e8a47 | 4818 | check_suffix: |
1c529385 | 4819 | if (mnem_p > mnemonic) |
29b0f896 | 4820 | { |
1c529385 LH |
4821 | /* See if we can get a match by trimming off a suffix. */ |
4822 | switch (mnem_p[-1]) | |
29b0f896 | 4823 | { |
1c529385 LH |
4824 | case WORD_MNEM_SUFFIX: |
4825 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
4826 | i.suffix = SHORT_MNEM_SUFFIX; |
4827 | else | |
1c529385 LH |
4828 | /* Fall through. */ |
4829 | case BYTE_MNEM_SUFFIX: | |
4830 | case QWORD_MNEM_SUFFIX: | |
4831 | i.suffix = mnem_p[-1]; | |
29b0f896 | 4832 | mnem_p[-1] = '\0'; |
d3ce72d0 | 4833 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
4834 | mnemonic); |
4835 | break; | |
4836 | case SHORT_MNEM_SUFFIX: | |
4837 | case LONG_MNEM_SUFFIX: | |
4838 | if (!intel_syntax) | |
4839 | { | |
4840 | i.suffix = mnem_p[-1]; | |
4841 | mnem_p[-1] = '\0'; | |
4842 | current_templates = (const templates *) hash_find (op_hash, | |
4843 | mnemonic); | |
4844 | } | |
4845 | break; | |
4846 | ||
4847 | /* Intel Syntax. */ | |
4848 | case 'd': | |
4849 | if (intel_syntax) | |
4850 | { | |
4851 | if (intel_float_operand (mnemonic) == 1) | |
4852 | i.suffix = SHORT_MNEM_SUFFIX; | |
4853 | else | |
4854 | i.suffix = LONG_MNEM_SUFFIX; | |
4855 | mnem_p[-1] = '\0'; | |
4856 | current_templates = (const templates *) hash_find (op_hash, | |
4857 | mnemonic); | |
4858 | } | |
4859 | break; | |
29b0f896 | 4860 | } |
29b0f896 | 4861 | } |
1c529385 | 4862 | |
29b0f896 AM |
4863 | if (!current_templates) |
4864 | { | |
4865 | as_bad (_("no such instruction: `%s'"), token_start); | |
4866 | return NULL; | |
4867 | } | |
4868 | } | |
252b5132 | 4869 | |
0cfa3eb3 JB |
4870 | if (current_templates->start->opcode_modifier.jump == JUMP |
4871 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
4872 | { |
4873 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4874 | predict taken and predict not taken respectively. | |
4875 | I'm not sure that branch hints actually do anything on loop | |
4876 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4877 | may work in the future and it doesn't hurt to accept them | |
4878 | now. */ | |
4879 | if (l[0] == ',' && l[1] == 'p') | |
4880 | { | |
4881 | if (l[2] == 't') | |
4882 | { | |
4883 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4884 | return NULL; | |
4885 | l += 3; | |
4886 | } | |
4887 | else if (l[2] == 'n') | |
4888 | { | |
4889 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4890 | return NULL; | |
4891 | l += 3; | |
4892 | } | |
4893 | } | |
4894 | } | |
4895 | /* Any other comma loses. */ | |
4896 | if (*l == ',') | |
4897 | { | |
4898 | as_bad (_("invalid character %s in mnemonic"), | |
4899 | output_invalid (*l)); | |
4900 | return NULL; | |
4901 | } | |
252b5132 | 4902 | |
29b0f896 | 4903 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4904 | supported = 0; |
4905 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4906 | { | |
c0f3af97 L |
4907 | supported |= cpu_flags_match (t); |
4908 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4909 | { |
4910 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4911 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4912 | |
548d0ee6 JB |
4913 | return l; |
4914 | } | |
29b0f896 | 4915 | } |
3629bb00 | 4916 | |
548d0ee6 JB |
4917 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4918 | as_bad (flag_code == CODE_64BIT | |
4919 | ? _("`%s' is not supported in 64-bit mode") | |
4920 | : _("`%s' is only supported in 64-bit mode"), | |
4921 | current_templates->start->name); | |
4922 | else | |
4923 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4924 | current_templates->start->name, | |
4925 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4926 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4927 | |
548d0ee6 | 4928 | return NULL; |
29b0f896 | 4929 | } |
252b5132 | 4930 | |
29b0f896 | 4931 | static char * |
e3bb37b5 | 4932 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4933 | { |
4934 | char *token_start; | |
3138f287 | 4935 | |
29b0f896 AM |
4936 | /* 1 if operand is pending after ','. */ |
4937 | unsigned int expecting_operand = 0; | |
252b5132 | 4938 | |
29b0f896 AM |
4939 | /* Non-zero if operand parens not balanced. */ |
4940 | unsigned int paren_not_balanced; | |
4941 | ||
4942 | while (*l != END_OF_INSN) | |
4943 | { | |
4944 | /* Skip optional white space before operand. */ | |
4945 | if (is_space_char (*l)) | |
4946 | ++l; | |
d02603dc | 4947 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4948 | { |
4949 | as_bad (_("invalid character %s before operand %d"), | |
4950 | output_invalid (*l), | |
4951 | i.operands + 1); | |
4952 | return NULL; | |
4953 | } | |
d02603dc | 4954 | token_start = l; /* After white space. */ |
29b0f896 AM |
4955 | paren_not_balanced = 0; |
4956 | while (paren_not_balanced || *l != ',') | |
4957 | { | |
4958 | if (*l == END_OF_INSN) | |
4959 | { | |
4960 | if (paren_not_balanced) | |
4961 | { | |
4962 | if (!intel_syntax) | |
4963 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4964 | i.operands + 1); | |
4965 | else | |
4966 | as_bad (_("unbalanced brackets in operand %d."), | |
4967 | i.operands + 1); | |
4968 | return NULL; | |
4969 | } | |
4970 | else | |
4971 | break; /* we are done */ | |
4972 | } | |
d02603dc | 4973 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4974 | { |
4975 | as_bad (_("invalid character %s in operand %d"), | |
4976 | output_invalid (*l), | |
4977 | i.operands + 1); | |
4978 | return NULL; | |
4979 | } | |
4980 | if (!intel_syntax) | |
4981 | { | |
4982 | if (*l == '(') | |
4983 | ++paren_not_balanced; | |
4984 | if (*l == ')') | |
4985 | --paren_not_balanced; | |
4986 | } | |
4987 | else | |
4988 | { | |
4989 | if (*l == '[') | |
4990 | ++paren_not_balanced; | |
4991 | if (*l == ']') | |
4992 | --paren_not_balanced; | |
4993 | } | |
4994 | l++; | |
4995 | } | |
4996 | if (l != token_start) | |
4997 | { /* Yes, we've read in another operand. */ | |
4998 | unsigned int operand_ok; | |
4999 | this_operand = i.operands++; | |
5000 | if (i.operands > MAX_OPERANDS) | |
5001 | { | |
5002 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
5003 | MAX_OPERANDS); | |
5004 | return NULL; | |
5005 | } | |
9d46ce34 | 5006 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
5007 | /* Now parse operand adding info to 'i' as we go along. */ |
5008 | END_STRING_AND_SAVE (l); | |
5009 | ||
1286ab78 L |
5010 | if (i.mem_operands > 1) |
5011 | { | |
5012 | as_bad (_("too many memory references for `%s'"), | |
5013 | mnemonic); | |
5014 | return 0; | |
5015 | } | |
5016 | ||
29b0f896 AM |
5017 | if (intel_syntax) |
5018 | operand_ok = | |
5019 | i386_intel_operand (token_start, | |
5020 | intel_float_operand (mnemonic)); | |
5021 | else | |
a7619375 | 5022 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5023 | |
5024 | RESTORE_END_STRING (l); | |
5025 | if (!operand_ok) | |
5026 | return NULL; | |
5027 | } | |
5028 | else | |
5029 | { | |
5030 | if (expecting_operand) | |
5031 | { | |
5032 | expecting_operand_after_comma: | |
5033 | as_bad (_("expecting operand after ','; got nothing")); | |
5034 | return NULL; | |
5035 | } | |
5036 | if (*l == ',') | |
5037 | { | |
5038 | as_bad (_("expecting operand before ','; got nothing")); | |
5039 | return NULL; | |
5040 | } | |
5041 | } | |
7f3f1ea2 | 5042 | |
29b0f896 AM |
5043 | /* Now *l must be either ',' or END_OF_INSN. */ |
5044 | if (*l == ',') | |
5045 | { | |
5046 | if (*++l == END_OF_INSN) | |
5047 | { | |
5048 | /* Just skip it, if it's \n complain. */ | |
5049 | goto expecting_operand_after_comma; | |
5050 | } | |
5051 | expecting_operand = 1; | |
5052 | } | |
5053 | } | |
5054 | return l; | |
5055 | } | |
7f3f1ea2 | 5056 | |
050dfa73 | 5057 | static void |
4d456e3d | 5058 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
5059 | { |
5060 | union i386_op temp_op; | |
40fb9820 | 5061 | i386_operand_type temp_type; |
c48dadc9 | 5062 | unsigned int temp_flags; |
050dfa73 | 5063 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5064 | |
050dfa73 MM |
5065 | temp_type = i.types[xchg2]; |
5066 | i.types[xchg2] = i.types[xchg1]; | |
5067 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5068 | |
5069 | temp_flags = i.flags[xchg2]; | |
5070 | i.flags[xchg2] = i.flags[xchg1]; | |
5071 | i.flags[xchg1] = temp_flags; | |
5072 | ||
050dfa73 MM |
5073 | temp_op = i.op[xchg2]; |
5074 | i.op[xchg2] = i.op[xchg1]; | |
5075 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5076 | |
050dfa73 MM |
5077 | temp_reloc = i.reloc[xchg2]; |
5078 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5079 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
5080 | |
5081 | if (i.mask) | |
5082 | { | |
5083 | if (i.mask->operand == xchg1) | |
5084 | i.mask->operand = xchg2; | |
5085 | else if (i.mask->operand == xchg2) | |
5086 | i.mask->operand = xchg1; | |
5087 | } | |
5088 | if (i.broadcast) | |
5089 | { | |
5090 | if (i.broadcast->operand == xchg1) | |
5091 | i.broadcast->operand = xchg2; | |
5092 | else if (i.broadcast->operand == xchg2) | |
5093 | i.broadcast->operand = xchg1; | |
5094 | } | |
5095 | if (i.rounding) | |
5096 | { | |
5097 | if (i.rounding->operand == xchg1) | |
5098 | i.rounding->operand = xchg2; | |
5099 | else if (i.rounding->operand == xchg2) | |
5100 | i.rounding->operand = xchg1; | |
5101 | } | |
050dfa73 MM |
5102 | } |
5103 | ||
29b0f896 | 5104 | static void |
e3bb37b5 | 5105 | swap_operands (void) |
29b0f896 | 5106 | { |
b7c61d9a | 5107 | switch (i.operands) |
050dfa73 | 5108 | { |
c0f3af97 | 5109 | case 5: |
b7c61d9a | 5110 | case 4: |
4d456e3d | 5111 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5112 | /* Fall through. */ |
b7c61d9a L |
5113 | case 3: |
5114 | case 2: | |
4d456e3d | 5115 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5116 | break; |
5117 | default: | |
5118 | abort (); | |
29b0f896 | 5119 | } |
29b0f896 AM |
5120 | |
5121 | if (i.mem_operands == 2) | |
5122 | { | |
5123 | const seg_entry *temp_seg; | |
5124 | temp_seg = i.seg[0]; | |
5125 | i.seg[0] = i.seg[1]; | |
5126 | i.seg[1] = temp_seg; | |
5127 | } | |
5128 | } | |
252b5132 | 5129 | |
29b0f896 AM |
5130 | /* Try to ensure constant immediates are represented in the smallest |
5131 | opcode possible. */ | |
5132 | static void | |
e3bb37b5 | 5133 | optimize_imm (void) |
29b0f896 AM |
5134 | { |
5135 | char guess_suffix = 0; | |
5136 | int op; | |
252b5132 | 5137 | |
29b0f896 AM |
5138 | if (i.suffix) |
5139 | guess_suffix = i.suffix; | |
5140 | else if (i.reg_operands) | |
5141 | { | |
5142 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5143 | We can't do this properly yet, i.e. excluding special register |
5144 | instances, but the following works for instructions with | |
5145 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5146 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5147 | if (i.types[op].bitfield.class != Reg) |
5148 | continue; | |
5149 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5150 | { |
40fb9820 L |
5151 | guess_suffix = BYTE_MNEM_SUFFIX; |
5152 | break; | |
5153 | } | |
bab6aec1 | 5154 | else if (i.types[op].bitfield.word) |
252b5132 | 5155 | { |
40fb9820 L |
5156 | guess_suffix = WORD_MNEM_SUFFIX; |
5157 | break; | |
5158 | } | |
bab6aec1 | 5159 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5160 | { |
5161 | guess_suffix = LONG_MNEM_SUFFIX; | |
5162 | break; | |
5163 | } | |
bab6aec1 | 5164 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5165 | { |
5166 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5167 | break; |
252b5132 | 5168 | } |
29b0f896 AM |
5169 | } |
5170 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5171 | guess_suffix = WORD_MNEM_SUFFIX; | |
5172 | ||
5173 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5174 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5175 | { |
5176 | switch (i.op[op].imms->X_op) | |
252b5132 | 5177 | { |
29b0f896 AM |
5178 | case O_constant: |
5179 | /* If a suffix is given, this operand may be shortened. */ | |
5180 | switch (guess_suffix) | |
252b5132 | 5181 | { |
29b0f896 | 5182 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5183 | i.types[op].bitfield.imm32 = 1; |
5184 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5185 | break; |
5186 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5187 | i.types[op].bitfield.imm16 = 1; |
5188 | i.types[op].bitfield.imm32 = 1; | |
5189 | i.types[op].bitfield.imm32s = 1; | |
5190 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5191 | break; |
5192 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5193 | i.types[op].bitfield.imm8 = 1; |
5194 | i.types[op].bitfield.imm8s = 1; | |
5195 | i.types[op].bitfield.imm16 = 1; | |
5196 | i.types[op].bitfield.imm32 = 1; | |
5197 | i.types[op].bitfield.imm32s = 1; | |
5198 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5199 | break; |
252b5132 | 5200 | } |
252b5132 | 5201 | |
29b0f896 AM |
5202 | /* If this operand is at most 16 bits, convert it |
5203 | to a signed 16 bit number before trying to see | |
5204 | whether it will fit in an even smaller size. | |
5205 | This allows a 16-bit operand such as $0xffe0 to | |
5206 | be recognised as within Imm8S range. */ | |
40fb9820 | 5207 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5208 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5209 | { |
29b0f896 AM |
5210 | i.op[op].imms->X_add_number = |
5211 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5212 | } | |
a28def75 L |
5213 | #ifdef BFD64 |
5214 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5215 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5216 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5217 | == 0)) | |
5218 | { | |
5219 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5220 | ^ ((offsetT) 1 << 31)) | |
5221 | - ((offsetT) 1 << 31)); | |
5222 | } | |
a28def75 | 5223 | #endif |
40fb9820 | 5224 | i.types[op] |
c6fb90c8 L |
5225 | = operand_type_or (i.types[op], |
5226 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5227 | |
29b0f896 AM |
5228 | /* We must avoid matching of Imm32 templates when 64bit |
5229 | only immediate is available. */ | |
5230 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5231 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5232 | break; |
252b5132 | 5233 | |
29b0f896 AM |
5234 | case O_absent: |
5235 | case O_register: | |
5236 | abort (); | |
5237 | ||
5238 | /* Symbols and expressions. */ | |
5239 | default: | |
9cd96992 JB |
5240 | /* Convert symbolic operand to proper sizes for matching, but don't |
5241 | prevent matching a set of insns that only supports sizes other | |
5242 | than those matching the insn suffix. */ | |
5243 | { | |
40fb9820 | 5244 | i386_operand_type mask, allowed; |
d3ce72d0 | 5245 | const insn_template *t; |
9cd96992 | 5246 | |
0dfbf9d7 L |
5247 | operand_type_set (&mask, 0); |
5248 | operand_type_set (&allowed, 0); | |
40fb9820 | 5249 | |
4eed87de AM |
5250 | for (t = current_templates->start; |
5251 | t < current_templates->end; | |
5252 | ++t) | |
bab6aec1 JB |
5253 | { |
5254 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
5255 | allowed = operand_type_and (allowed, anyimm); | |
5256 | } | |
9cd96992 JB |
5257 | switch (guess_suffix) |
5258 | { | |
5259 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5260 | mask.bitfield.imm64 = 1; |
5261 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5262 | break; |
5263 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5264 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5265 | break; |
5266 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5267 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5268 | break; |
5269 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5270 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5271 | break; |
5272 | default: | |
9cd96992 JB |
5273 | break; |
5274 | } | |
c6fb90c8 | 5275 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5276 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5277 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5278 | } |
29b0f896 | 5279 | break; |
252b5132 | 5280 | } |
29b0f896 AM |
5281 | } |
5282 | } | |
47926f60 | 5283 | |
29b0f896 AM |
5284 | /* Try to use the smallest displacement type too. */ |
5285 | static void | |
e3bb37b5 | 5286 | optimize_disp (void) |
29b0f896 AM |
5287 | { |
5288 | int op; | |
3e73aa7c | 5289 | |
29b0f896 | 5290 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5291 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5292 | { |
b300c311 | 5293 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5294 | { |
91d6fa6a | 5295 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5296 | |
40fb9820 | 5297 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5298 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5299 | { |
5300 | /* If this operand is at most 16 bits, convert | |
5301 | to a signed 16 bit number and don't use 64bit | |
5302 | displacement. */ | |
91d6fa6a | 5303 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5304 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5305 | } |
a28def75 L |
5306 | #ifdef BFD64 |
5307 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5308 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5309 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5310 | { |
5311 | /* If this operand is at most 32 bits, convert | |
5312 | to a signed 32 bit number and don't use 64bit | |
5313 | displacement. */ | |
91d6fa6a NC |
5314 | op_disp &= (((offsetT) 2 << 31) - 1); |
5315 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5316 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5317 | } |
a28def75 | 5318 | #endif |
91d6fa6a | 5319 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5320 | { |
40fb9820 L |
5321 | i.types[op].bitfield.disp8 = 0; |
5322 | i.types[op].bitfield.disp16 = 0; | |
5323 | i.types[op].bitfield.disp32 = 0; | |
5324 | i.types[op].bitfield.disp32s = 0; | |
5325 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5326 | i.op[op].disps = 0; |
5327 | i.disp_operands--; | |
5328 | } | |
5329 | else if (flag_code == CODE_64BIT) | |
5330 | { | |
91d6fa6a | 5331 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5332 | { |
40fb9820 L |
5333 | i.types[op].bitfield.disp64 = 0; |
5334 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5335 | } |
0e1147d9 | 5336 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5337 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5338 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5339 | } |
40fb9820 L |
5340 | if ((i.types[op].bitfield.disp32 |
5341 | || i.types[op].bitfield.disp32s | |
5342 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5343 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5344 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5345 | } |
67a4f2b7 AO |
5346 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5347 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5348 | { | |
5349 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5350 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5351 | i.types[op].bitfield.disp8 = 0; |
5352 | i.types[op].bitfield.disp16 = 0; | |
5353 | i.types[op].bitfield.disp32 = 0; | |
5354 | i.types[op].bitfield.disp32s = 0; | |
5355 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5356 | } |
5357 | else | |
b300c311 | 5358 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5359 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5360 | } |
29b0f896 AM |
5361 | } |
5362 | ||
4a1b91ea L |
5363 | /* Return 1 if there is a match in broadcast bytes between operand |
5364 | GIVEN and instruction template T. */ | |
5365 | ||
5366 | static INLINE int | |
5367 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5368 | { | |
5369 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5370 | && i.types[given].bitfield.byte) | |
5371 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5372 | && i.types[given].bitfield.word) | |
5373 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5374 | && i.types[given].bitfield.dword) | |
5375 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5376 | && i.types[given].bitfield.qword)); | |
5377 | } | |
5378 | ||
6c30d220 L |
5379 | /* Check if operands are valid for the instruction. */ |
5380 | ||
5381 | static int | |
5382 | check_VecOperands (const insn_template *t) | |
5383 | { | |
43234a1e | 5384 | unsigned int op; |
e2195274 | 5385 | i386_cpu_flags cpu; |
e2195274 JB |
5386 | |
5387 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5388 | any one operand are implicity requiring AVX512VL support if the actual | |
5389 | operand size is YMMword or XMMword. Since this function runs after | |
5390 | template matching, there's no need to check for YMMword/XMMword in | |
5391 | the template. */ | |
5392 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5393 | if (!cpu_flags_all_zero (&cpu) | |
5394 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5395 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5396 | { | |
5397 | for (op = 0; op < t->operands; ++op) | |
5398 | { | |
5399 | if (t->operand_types[op].bitfield.zmmword | |
5400 | && (i.types[op].bitfield.ymmword | |
5401 | || i.types[op].bitfield.xmmword)) | |
5402 | { | |
5403 | i.error = unsupported; | |
5404 | return 1; | |
5405 | } | |
5406 | } | |
5407 | } | |
43234a1e | 5408 | |
6c30d220 L |
5409 | /* Without VSIB byte, we can't have a vector register for index. */ |
5410 | if (!t->opcode_modifier.vecsib | |
5411 | && i.index_reg | |
1b54b8d7 JB |
5412 | && (i.index_reg->reg_type.bitfield.xmmword |
5413 | || i.index_reg->reg_type.bitfield.ymmword | |
5414 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5415 | { |
5416 | i.error = unsupported_vector_index_register; | |
5417 | return 1; | |
5418 | } | |
5419 | ||
ad8ecc81 MZ |
5420 | /* Check if default mask is allowed. */ |
5421 | if (t->opcode_modifier.nodefmask | |
5422 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5423 | { | |
5424 | i.error = no_default_mask; | |
5425 | return 1; | |
5426 | } | |
5427 | ||
7bab8ab5 JB |
5428 | /* For VSIB byte, we need a vector register for index, and all vector |
5429 | registers must be distinct. */ | |
5430 | if (t->opcode_modifier.vecsib) | |
5431 | { | |
5432 | if (!i.index_reg | |
6c30d220 | 5433 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5434 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5435 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5436 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5437 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5438 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5439 | { |
5440 | i.error = invalid_vsib_address; | |
5441 | return 1; | |
5442 | } | |
5443 | ||
43234a1e L |
5444 | gas_assert (i.reg_operands == 2 || i.mask); |
5445 | if (i.reg_operands == 2 && !i.mask) | |
5446 | { | |
3528c362 | 5447 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5448 | gas_assert (i.types[0].bitfield.xmmword |
5449 | || i.types[0].bitfield.ymmword); | |
3528c362 | 5450 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5451 | gas_assert (i.types[2].bitfield.xmmword |
5452 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5453 | if (operand_check == check_none) |
5454 | return 0; | |
5455 | if (register_number (i.op[0].regs) | |
5456 | != register_number (i.index_reg) | |
5457 | && register_number (i.op[2].regs) | |
5458 | != register_number (i.index_reg) | |
5459 | && register_number (i.op[0].regs) | |
5460 | != register_number (i.op[2].regs)) | |
5461 | return 0; | |
5462 | if (operand_check == check_error) | |
5463 | { | |
5464 | i.error = invalid_vector_register_set; | |
5465 | return 1; | |
5466 | } | |
5467 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5468 | } | |
8444f82a MZ |
5469 | else if (i.reg_operands == 1 && i.mask) |
5470 | { | |
3528c362 | 5471 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
5472 | && (i.types[1].bitfield.xmmword |
5473 | || i.types[1].bitfield.ymmword | |
5474 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5475 | && (register_number (i.op[1].regs) |
5476 | == register_number (i.index_reg))) | |
5477 | { | |
5478 | if (operand_check == check_error) | |
5479 | { | |
5480 | i.error = invalid_vector_register_set; | |
5481 | return 1; | |
5482 | } | |
5483 | if (operand_check != check_none) | |
5484 | as_warn (_("index and destination registers should be distinct")); | |
5485 | } | |
5486 | } | |
43234a1e | 5487 | } |
7bab8ab5 | 5488 | |
43234a1e L |
5489 | /* Check if broadcast is supported by the instruction and is applied |
5490 | to the memory operand. */ | |
5491 | if (i.broadcast) | |
5492 | { | |
8e6e0792 | 5493 | i386_operand_type type, overlap; |
43234a1e L |
5494 | |
5495 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5496 | and its broadcast bytes match the memory operand. */ |
32546502 | 5497 | op = i.broadcast->operand; |
8e6e0792 | 5498 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5499 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5500 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5501 | && !match_broadcast_size (t, op))) |
43234a1e L |
5502 | { |
5503 | bad_broadcast: | |
5504 | i.error = unsupported_broadcast; | |
5505 | return 1; | |
5506 | } | |
8e6e0792 | 5507 | |
4a1b91ea L |
5508 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5509 | * i.broadcast->type); | |
8e6e0792 | 5510 | operand_type_set (&type, 0); |
4a1b91ea | 5511 | switch (i.broadcast->bytes) |
8e6e0792 | 5512 | { |
4a1b91ea L |
5513 | case 2: |
5514 | type.bitfield.word = 1; | |
5515 | break; | |
5516 | case 4: | |
5517 | type.bitfield.dword = 1; | |
5518 | break; | |
8e6e0792 JB |
5519 | case 8: |
5520 | type.bitfield.qword = 1; | |
5521 | break; | |
5522 | case 16: | |
5523 | type.bitfield.xmmword = 1; | |
5524 | break; | |
5525 | case 32: | |
5526 | type.bitfield.ymmword = 1; | |
5527 | break; | |
5528 | case 64: | |
5529 | type.bitfield.zmmword = 1; | |
5530 | break; | |
5531 | default: | |
5532 | goto bad_broadcast; | |
5533 | } | |
5534 | ||
5535 | overlap = operand_type_and (type, t->operand_types[op]); | |
5536 | if (operand_type_all_zero (&overlap)) | |
5537 | goto bad_broadcast; | |
5538 | ||
5539 | if (t->opcode_modifier.checkregsize) | |
5540 | { | |
5541 | unsigned int j; | |
5542 | ||
e2195274 | 5543 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5544 | for (j = 0; j < i.operands; ++j) |
5545 | { | |
5546 | if (j != op | |
5547 | && !operand_type_register_match(i.types[j], | |
5548 | t->operand_types[j], | |
5549 | type, | |
5550 | t->operand_types[op])) | |
5551 | goto bad_broadcast; | |
5552 | } | |
5553 | } | |
43234a1e L |
5554 | } |
5555 | /* If broadcast is supported in this instruction, we need to check if | |
5556 | operand of one-element size isn't specified without broadcast. */ | |
5557 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5558 | { | |
5559 | /* Find memory operand. */ | |
5560 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5561 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
5562 | break; |
5563 | gas_assert (op < i.operands); | |
5564 | /* Check size of the memory operand. */ | |
4a1b91ea | 5565 | if (match_broadcast_size (t, op)) |
43234a1e L |
5566 | { |
5567 | i.error = broadcast_needed; | |
5568 | return 1; | |
5569 | } | |
5570 | } | |
c39e5b26 JB |
5571 | else |
5572 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5573 | |
5574 | /* Check if requested masking is supported. */ | |
ae2387fe | 5575 | if (i.mask) |
43234a1e | 5576 | { |
ae2387fe JB |
5577 | switch (t->opcode_modifier.masking) |
5578 | { | |
5579 | case BOTH_MASKING: | |
5580 | break; | |
5581 | case MERGING_MASKING: | |
5582 | if (i.mask->zeroing) | |
5583 | { | |
5584 | case 0: | |
5585 | i.error = unsupported_masking; | |
5586 | return 1; | |
5587 | } | |
5588 | break; | |
5589 | case DYNAMIC_MASKING: | |
5590 | /* Memory destinations allow only merging masking. */ | |
5591 | if (i.mask->zeroing && i.mem_operands) | |
5592 | { | |
5593 | /* Find memory operand. */ | |
5594 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5595 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5596 | break; |
5597 | gas_assert (op < i.operands); | |
5598 | if (op == i.operands - 1) | |
5599 | { | |
5600 | i.error = unsupported_masking; | |
5601 | return 1; | |
5602 | } | |
5603 | } | |
5604 | break; | |
5605 | default: | |
5606 | abort (); | |
5607 | } | |
43234a1e L |
5608 | } |
5609 | ||
5610 | /* Check if masking is applied to dest operand. */ | |
5611 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5612 | { | |
5613 | i.error = mask_not_on_destination; | |
5614 | return 1; | |
5615 | } | |
5616 | ||
43234a1e L |
5617 | /* Check RC/SAE. */ |
5618 | if (i.rounding) | |
5619 | { | |
a80195f1 JB |
5620 | if (!t->opcode_modifier.sae |
5621 | || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding)) | |
43234a1e L |
5622 | { |
5623 | i.error = unsupported_rc_sae; | |
5624 | return 1; | |
5625 | } | |
5626 | /* If the instruction has several immediate operands and one of | |
5627 | them is rounding, the rounding operand should be the last | |
5628 | immediate operand. */ | |
5629 | if (i.imm_operands > 1 | |
5630 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5631 | { |
43234a1e | 5632 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5633 | return 1; |
5634 | } | |
6c30d220 L |
5635 | } |
5636 | ||
43234a1e | 5637 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5638 | if (t->opcode_modifier.disp8memshift |
5639 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5640 | { |
5641 | if (i.broadcast) | |
4a1b91ea | 5642 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5643 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5644 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5645 | else |
5646 | { | |
5647 | const i386_operand_type *type = NULL; | |
5648 | ||
5649 | i.memshift = 0; | |
5650 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5651 | if (i.flags[op] & Operand_Mem) |
7091c612 | 5652 | { |
4174bfff JB |
5653 | if (t->opcode_modifier.evex == EVEXLIG) |
5654 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5655 | else if (t->operand_types[op].bitfield.xmmword | |
5656 | + t->operand_types[op].bitfield.ymmword | |
5657 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5658 | type = &t->operand_types[op]; |
5659 | else if (!i.types[op].bitfield.unspecified) | |
5660 | type = &i.types[op]; | |
5661 | } | |
3528c362 | 5662 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 5663 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
5664 | { |
5665 | if (i.types[op].bitfield.zmmword) | |
5666 | i.memshift = 6; | |
5667 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5668 | i.memshift = 5; | |
5669 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5670 | i.memshift = 4; | |
5671 | } | |
5672 | ||
5673 | if (type) | |
5674 | { | |
5675 | if (type->bitfield.zmmword) | |
5676 | i.memshift = 6; | |
5677 | else if (type->bitfield.ymmword) | |
5678 | i.memshift = 5; | |
5679 | else if (type->bitfield.xmmword) | |
5680 | i.memshift = 4; | |
5681 | } | |
5682 | ||
5683 | /* For the check in fits_in_disp8(). */ | |
5684 | if (i.memshift == 0) | |
5685 | i.memshift = -1; | |
5686 | } | |
43234a1e L |
5687 | |
5688 | for (op = 0; op < i.operands; op++) | |
5689 | if (operand_type_check (i.types[op], disp) | |
5690 | && i.op[op].disps->X_op == O_constant) | |
5691 | { | |
b5014f7a | 5692 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5693 | { |
b5014f7a JB |
5694 | i.types[op].bitfield.disp8 = 1; |
5695 | return 0; | |
43234a1e | 5696 | } |
b5014f7a | 5697 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5698 | } |
5699 | } | |
b5014f7a JB |
5700 | |
5701 | i.memshift = 0; | |
43234a1e | 5702 | |
6c30d220 L |
5703 | return 0; |
5704 | } | |
5705 | ||
43f3e2ee | 5706 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5707 | operand types. */ |
5708 | ||
5709 | static int | |
5710 | VEX_check_operands (const insn_template *t) | |
5711 | { | |
86fa6981 | 5712 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5713 | { |
86fa6981 | 5714 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5715 | if (!is_evex_encoding (t)) |
86fa6981 L |
5716 | { |
5717 | i.error = unsupported; | |
5718 | return 1; | |
5719 | } | |
5720 | return 0; | |
43234a1e L |
5721 | } |
5722 | ||
a683cc34 | 5723 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5724 | { |
5725 | /* This instruction template doesn't have VEX prefix. */ | |
5726 | if (i.vec_encoding != vex_encoding_default) | |
5727 | { | |
5728 | i.error = unsupported; | |
5729 | return 1; | |
5730 | } | |
5731 | return 0; | |
5732 | } | |
a683cc34 | 5733 | |
9d3bf266 JB |
5734 | /* Check the special Imm4 cases; must be the first operand. */ |
5735 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
a683cc34 SP |
5736 | { |
5737 | if (i.op[0].imms->X_op != O_constant | |
5738 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5739 | { |
a65babc9 | 5740 | i.error = bad_imm4; |
891edac4 L |
5741 | return 1; |
5742 | } | |
a683cc34 | 5743 | |
9d3bf266 JB |
5744 | /* Turn off Imm<N> so that update_imm won't complain. */ |
5745 | operand_type_set (&i.types[0], 0); | |
a683cc34 SP |
5746 | } |
5747 | ||
5748 | return 0; | |
5749 | } | |
5750 | ||
d3ce72d0 | 5751 | static const insn_template * |
83b16ac6 | 5752 | match_template (char mnem_suffix) |
29b0f896 AM |
5753 | { |
5754 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5755 | const insn_template *t; |
40fb9820 | 5756 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5757 | i386_operand_type overlap4; |
29b0f896 | 5758 | unsigned int found_reverse_match; |
dc2be329 | 5759 | i386_opcode_modifier suffix_check; |
40fb9820 | 5760 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5761 | int addr_prefix_disp; |
45a4bb20 | 5762 | unsigned int j, size_match, check_register; |
5614d22c | 5763 | enum i386_error specific_error = 0; |
29b0f896 | 5764 | |
c0f3af97 L |
5765 | #if MAX_OPERANDS != 5 |
5766 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5767 | #endif |
5768 | ||
29b0f896 | 5769 | found_reverse_match = 0; |
539e75ad | 5770 | addr_prefix_disp = -1; |
40fb9820 | 5771 | |
dc2be329 | 5772 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 5773 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
5774 | switch (mnem_suffix) |
5775 | { | |
5776 | case BYTE_MNEM_SUFFIX: | |
5777 | suffix_check.no_bsuf = 1; | |
5778 | break; | |
5779 | case WORD_MNEM_SUFFIX: | |
5780 | suffix_check.no_wsuf = 1; | |
5781 | break; | |
5782 | case SHORT_MNEM_SUFFIX: | |
5783 | suffix_check.no_ssuf = 1; | |
5784 | break; | |
5785 | case LONG_MNEM_SUFFIX: | |
5786 | suffix_check.no_lsuf = 1; | |
5787 | break; | |
5788 | case QWORD_MNEM_SUFFIX: | |
5789 | suffix_check.no_qsuf = 1; | |
5790 | break; | |
5791 | default: | |
5792 | /* NB: In Intel syntax, normally we can check for memory operand | |
5793 | size when there is no mnemonic suffix. But jmp and call have | |
5794 | 2 different encodings with Dword memory operand size, one with | |
5795 | No_ldSuf and the other without. i.suffix is set to | |
5796 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
5797 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
5798 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
5799 | } |
5800 | ||
01559ecc L |
5801 | /* Must have right number of operands. */ |
5802 | i.error = number_of_operands_mismatch; | |
5803 | ||
45aa61fe | 5804 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5805 | { |
539e75ad | 5806 | addr_prefix_disp = -1; |
dbbc8b7e | 5807 | found_reverse_match = 0; |
539e75ad | 5808 | |
29b0f896 AM |
5809 | if (i.operands != t->operands) |
5810 | continue; | |
5811 | ||
50aecf8c | 5812 | /* Check processor support. */ |
a65babc9 | 5813 | i.error = unsupported; |
45a4bb20 | 5814 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
5815 | continue; |
5816 | ||
e1d4d893 | 5817 | /* Check AT&T mnemonic. */ |
a65babc9 | 5818 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5819 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5820 | continue; |
5821 | ||
4b5aaf5f | 5822 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 5823 | i.error = unsupported_syntax; |
5c07affc | 5824 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 5825 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
5826 | continue; |
5827 | ||
4b5aaf5f L |
5828 | /* Check Intel64/AMD64 ISA. */ |
5829 | switch (isa64) | |
5830 | { | |
5831 | default: | |
5832 | /* Default: Don't accept Intel64. */ | |
5833 | if (t->opcode_modifier.isa64 == INTEL64) | |
5834 | continue; | |
5835 | break; | |
5836 | case amd64: | |
5837 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
5838 | if (t->opcode_modifier.isa64 >= INTEL64) | |
5839 | continue; | |
5840 | break; | |
5841 | case intel64: | |
5842 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 5843 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
5844 | continue; |
5845 | break; | |
5846 | } | |
5847 | ||
dc2be329 | 5848 | /* Check the suffix. */ |
a65babc9 | 5849 | i.error = invalid_instruction_suffix; |
dc2be329 L |
5850 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
5851 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5852 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5853 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5854 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5855 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 5856 | continue; |
29b0f896 | 5857 | |
3ac21baa JB |
5858 | size_match = operand_size_match (t); |
5859 | if (!size_match) | |
7d5e4556 | 5860 | continue; |
539e75ad | 5861 | |
6f2f06be JB |
5862 | /* This is intentionally not |
5863 | ||
0cfa3eb3 | 5864 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
5865 | |
5866 | as the case of a missing * on the operand is accepted (perhaps with | |
5867 | a warning, issued further down). */ | |
0cfa3eb3 | 5868 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
6f2f06be JB |
5869 | { |
5870 | i.error = operand_type_mismatch; | |
5871 | continue; | |
5872 | } | |
5873 | ||
5c07affc L |
5874 | for (j = 0; j < MAX_OPERANDS; j++) |
5875 | operand_types[j] = t->operand_types[j]; | |
5876 | ||
45aa61fe AM |
5877 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5878 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5879 | && flag_code != CODE_64BIT | |
5880 | && (intel_syntax | |
3cd7f3e3 | 5881 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
625cbd7a | 5882 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5883 | && !intel_float_operand (t->name)) |
5884 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5885 | && ((operand_types[0].bitfield.class != RegMMX |
5886 | && operand_types[0].bitfield.class != RegSIMD) | |
5887 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5888 | && operand_types[t->operands > 1].bitfield.class != RegSIMD)) | |
45aa61fe AM |
5889 | && (t->base_opcode != 0x0fc7 |
5890 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5891 | continue; | |
5892 | ||
192dc9c6 JB |
5893 | /* In general, don't allow 32-bit operands on pre-386. */ |
5894 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5895 | && !cpu_arch_flags.bitfield.cpui386 | |
5896 | && (intel_syntax | |
3cd7f3e3 | 5897 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
192dc9c6 JB |
5898 | && !intel_float_operand (t->name)) |
5899 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5900 | && ((operand_types[0].bitfield.class != RegMMX |
5901 | && operand_types[0].bitfield.class != RegSIMD) | |
5902 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5903 | && operand_types[t->operands > 1].bitfield.class | |
5904 | != RegSIMD))) | |
192dc9c6 JB |
5905 | continue; |
5906 | ||
29b0f896 | 5907 | /* Do not verify operands when there are none. */ |
50aecf8c | 5908 | else |
29b0f896 | 5909 | { |
c6fb90c8 | 5910 | if (!t->operands) |
2dbab7d5 L |
5911 | /* We've found a match; break out of loop. */ |
5912 | break; | |
29b0f896 | 5913 | } |
252b5132 | 5914 | |
48bcea9f JB |
5915 | if (!t->opcode_modifier.jump |
5916 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
5917 | { | |
5918 | /* There should be only one Disp operand. */ | |
5919 | for (j = 0; j < MAX_OPERANDS; j++) | |
5920 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 5921 | break; |
48bcea9f JB |
5922 | if (j < MAX_OPERANDS) |
5923 | { | |
5924 | bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0); | |
5925 | ||
5926 | addr_prefix_disp = j; | |
5927 | ||
5928 | /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16 | |
5929 | operand into Disp32/Disp32/Disp16/Disp32 operand. */ | |
5930 | switch (flag_code) | |
40fb9820 | 5931 | { |
48bcea9f JB |
5932 | case CODE_16BIT: |
5933 | override = !override; | |
5934 | /* Fall through. */ | |
5935 | case CODE_32BIT: | |
5936 | if (operand_types[j].bitfield.disp32 | |
5937 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 5938 | { |
48bcea9f JB |
5939 | operand_types[j].bitfield.disp16 = override; |
5940 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 5941 | } |
48bcea9f JB |
5942 | operand_types[j].bitfield.disp32s = 0; |
5943 | operand_types[j].bitfield.disp64 = 0; | |
5944 | break; | |
5945 | ||
5946 | case CODE_64BIT: | |
5947 | if (operand_types[j].bitfield.disp32s | |
5948 | || operand_types[j].bitfield.disp64) | |
40fb9820 | 5949 | { |
48bcea9f JB |
5950 | operand_types[j].bitfield.disp64 &= !override; |
5951 | operand_types[j].bitfield.disp32s &= !override; | |
5952 | operand_types[j].bitfield.disp32 = override; | |
40fb9820 | 5953 | } |
48bcea9f JB |
5954 | operand_types[j].bitfield.disp16 = 0; |
5955 | break; | |
40fb9820 | 5956 | } |
539e75ad | 5957 | } |
48bcea9f | 5958 | } |
539e75ad | 5959 | |
02a86693 L |
5960 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5961 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5962 | continue; | |
5963 | ||
56ffb741 | 5964 | /* We check register size if needed. */ |
e2195274 JB |
5965 | if (t->opcode_modifier.checkregsize) |
5966 | { | |
5967 | check_register = (1 << t->operands) - 1; | |
5968 | if (i.broadcast) | |
5969 | check_register &= ~(1 << i.broadcast->operand); | |
5970 | } | |
5971 | else | |
5972 | check_register = 0; | |
5973 | ||
c6fb90c8 | 5974 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5975 | switch (t->operands) |
5976 | { | |
5977 | case 1: | |
40fb9820 | 5978 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5979 | continue; |
5980 | break; | |
5981 | case 2: | |
33eaf5de | 5982 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5983 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5984 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5985 | zero-extend %eax to %rax. */ | |
5986 | if (flag_code == CODE_64BIT | |
5987 | && t->base_opcode == 0x90 | |
75e5731b JB |
5988 | && i.types[0].bitfield.instance == Accum |
5989 | && i.types[0].bitfield.dword | |
5990 | && i.types[1].bitfield.instance == Accum | |
5991 | && i.types[1].bitfield.dword) | |
8b38ad71 | 5992 | continue; |
1212781b JB |
5993 | /* xrelease mov %eax, <disp> is another special case. It must not |
5994 | match the accumulator-only encoding of mov. */ | |
5995 | if (flag_code != CODE_64BIT | |
5996 | && i.hle_prefix | |
5997 | && t->base_opcode == 0xa0 | |
75e5731b | 5998 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 5999 | && (i.flags[1] & Operand_Mem)) |
1212781b | 6000 | continue; |
f5eb1d70 JB |
6001 | /* Fall through. */ |
6002 | ||
6003 | case 3: | |
3ac21baa JB |
6004 | if (!(size_match & MATCH_STRAIGHT)) |
6005 | goto check_reverse; | |
64c49ab3 JB |
6006 | /* Reverse direction of operands if swapping is possible in the first |
6007 | place (operands need to be symmetric) and | |
6008 | - the load form is requested, and the template is a store form, | |
6009 | - the store form is requested, and the template is a load form, | |
6010 | - the non-default (swapped) form is requested. */ | |
6011 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 6012 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
6013 | && !operand_type_all_zero (&overlap1)) |
6014 | switch (i.dir_encoding) | |
6015 | { | |
6016 | case dir_encoding_load: | |
6017 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6018 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
6019 | goto check_reverse; |
6020 | break; | |
6021 | ||
6022 | case dir_encoding_store: | |
6023 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6024 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
6025 | goto check_reverse; |
6026 | break; | |
6027 | ||
6028 | case dir_encoding_swap: | |
6029 | goto check_reverse; | |
6030 | ||
6031 | case dir_encoding_default: | |
6032 | break; | |
6033 | } | |
86fa6981 | 6034 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6035 | if ((i.dir_encoding == dir_encoding_store |
6036 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6037 | && i.mem_operands == 0 |
6038 | && t->opcode_modifier.load) | |
fa99fab2 | 6039 | continue; |
1a0670f3 | 6040 | /* Fall through. */ |
f48ff2ae | 6041 | case 4: |
c0f3af97 | 6042 | case 5: |
c6fb90c8 | 6043 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
6044 | if (!operand_type_match (overlap0, i.types[0]) |
6045 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 6046 | || ((check_register & 3) == 3 |
dc821c5f | 6047 | && !operand_type_register_match (i.types[0], |
40fb9820 | 6048 | operand_types[0], |
dc821c5f | 6049 | i.types[1], |
40fb9820 | 6050 | operand_types[1]))) |
29b0f896 AM |
6051 | { |
6052 | /* Check if other direction is valid ... */ | |
38e314eb | 6053 | if (!t->opcode_modifier.d) |
29b0f896 AM |
6054 | continue; |
6055 | ||
dc1e8a47 | 6056 | check_reverse: |
3ac21baa JB |
6057 | if (!(size_match & MATCH_REVERSE)) |
6058 | continue; | |
29b0f896 | 6059 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
6060 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
6061 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 6062 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 6063 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 6064 | || (check_register |
dc821c5f | 6065 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
6066 | operand_types[i.operands - 1], |
6067 | i.types[i.operands - 1], | |
45664ddb | 6068 | operand_types[0]))) |
29b0f896 AM |
6069 | { |
6070 | /* Does not match either direction. */ | |
6071 | continue; | |
6072 | } | |
38e314eb | 6073 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 6074 | we've found. */ |
38e314eb JB |
6075 | if (!t->opcode_modifier.d) |
6076 | found_reverse_match = 0; | |
6077 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 6078 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 6079 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 6080 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
6081 | || operand_types[0].bitfield.class == RegMMX |
6082 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
6083 | || is_any_vex_encoding(t)) |
6084 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
6085 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 6086 | else |
38e314eb | 6087 | found_reverse_match = Opcode_D; |
40fb9820 | 6088 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6089 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6090 | } |
f48ff2ae | 6091 | else |
29b0f896 | 6092 | { |
f48ff2ae | 6093 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
6094 | switch (t->operands) |
6095 | { | |
c0f3af97 L |
6096 | case 5: |
6097 | overlap4 = operand_type_and (i.types[4], | |
6098 | operand_types[4]); | |
1a0670f3 | 6099 | /* Fall through. */ |
d1cbb4db | 6100 | case 4: |
c6fb90c8 L |
6101 | overlap3 = operand_type_and (i.types[3], |
6102 | operand_types[3]); | |
1a0670f3 | 6103 | /* Fall through. */ |
d1cbb4db | 6104 | case 3: |
c6fb90c8 L |
6105 | overlap2 = operand_type_and (i.types[2], |
6106 | operand_types[2]); | |
d1cbb4db L |
6107 | break; |
6108 | } | |
29b0f896 | 6109 | |
f48ff2ae L |
6110 | switch (t->operands) |
6111 | { | |
c0f3af97 L |
6112 | case 5: |
6113 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 6114 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6115 | operand_types[3], |
c0f3af97 L |
6116 | i.types[4], |
6117 | operand_types[4])) | |
6118 | continue; | |
1a0670f3 | 6119 | /* Fall through. */ |
f48ff2ae | 6120 | case 4: |
40fb9820 | 6121 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6122 | || ((check_register & 0xa) == 0xa |
6123 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6124 | operand_types[1], |
6125 | i.types[3], | |
e2195274 JB |
6126 | operand_types[3])) |
6127 | || ((check_register & 0xc) == 0xc | |
6128 | && !operand_type_register_match (i.types[2], | |
6129 | operand_types[2], | |
6130 | i.types[3], | |
6131 | operand_types[3]))) | |
f48ff2ae | 6132 | continue; |
1a0670f3 | 6133 | /* Fall through. */ |
f48ff2ae L |
6134 | case 3: |
6135 | /* Here we make use of the fact that there are no | |
23e42951 | 6136 | reverse match 3 operand instructions. */ |
40fb9820 | 6137 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6138 | || ((check_register & 5) == 5 |
6139 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6140 | operand_types[0], |
6141 | i.types[2], | |
e2195274 JB |
6142 | operand_types[2])) |
6143 | || ((check_register & 6) == 6 | |
6144 | && !operand_type_register_match (i.types[1], | |
6145 | operand_types[1], | |
6146 | i.types[2], | |
6147 | operand_types[2]))) | |
f48ff2ae L |
6148 | continue; |
6149 | break; | |
6150 | } | |
29b0f896 | 6151 | } |
f48ff2ae | 6152 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6153 | slip through to break. */ |
6154 | } | |
c0f3af97 | 6155 | |
5614d22c JB |
6156 | /* Check if vector and VEX operands are valid. */ |
6157 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
6158 | { | |
6159 | specific_error = i.error; | |
6160 | continue; | |
6161 | } | |
a683cc34 | 6162 | |
29b0f896 AM |
6163 | /* We've found a match; break out of loop. */ |
6164 | break; | |
6165 | } | |
6166 | ||
6167 | if (t == current_templates->end) | |
6168 | { | |
6169 | /* We found no match. */ | |
a65babc9 | 6170 | const char *err_msg; |
5614d22c | 6171 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6172 | { |
6173 | default: | |
6174 | abort (); | |
86e026a4 | 6175 | case operand_size_mismatch: |
a65babc9 L |
6176 | err_msg = _("operand size mismatch"); |
6177 | break; | |
6178 | case operand_type_mismatch: | |
6179 | err_msg = _("operand type mismatch"); | |
6180 | break; | |
6181 | case register_type_mismatch: | |
6182 | err_msg = _("register type mismatch"); | |
6183 | break; | |
6184 | case number_of_operands_mismatch: | |
6185 | err_msg = _("number of operands mismatch"); | |
6186 | break; | |
6187 | case invalid_instruction_suffix: | |
6188 | err_msg = _("invalid instruction suffix"); | |
6189 | break; | |
6190 | case bad_imm4: | |
4a2608e3 | 6191 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6192 | break; |
a65babc9 L |
6193 | case unsupported_with_intel_mnemonic: |
6194 | err_msg = _("unsupported with Intel mnemonic"); | |
6195 | break; | |
6196 | case unsupported_syntax: | |
6197 | err_msg = _("unsupported syntax"); | |
6198 | break; | |
6199 | case unsupported: | |
35262a23 | 6200 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6201 | current_templates->start->name); |
6202 | return NULL; | |
6c30d220 L |
6203 | case invalid_vsib_address: |
6204 | err_msg = _("invalid VSIB address"); | |
6205 | break; | |
7bab8ab5 JB |
6206 | case invalid_vector_register_set: |
6207 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6208 | break; | |
6c30d220 L |
6209 | case unsupported_vector_index_register: |
6210 | err_msg = _("unsupported vector index register"); | |
6211 | break; | |
43234a1e L |
6212 | case unsupported_broadcast: |
6213 | err_msg = _("unsupported broadcast"); | |
6214 | break; | |
43234a1e L |
6215 | case broadcast_needed: |
6216 | err_msg = _("broadcast is needed for operand of such type"); | |
6217 | break; | |
6218 | case unsupported_masking: | |
6219 | err_msg = _("unsupported masking"); | |
6220 | break; | |
6221 | case mask_not_on_destination: | |
6222 | err_msg = _("mask not on destination operand"); | |
6223 | break; | |
6224 | case no_default_mask: | |
6225 | err_msg = _("default mask isn't allowed"); | |
6226 | break; | |
6227 | case unsupported_rc_sae: | |
6228 | err_msg = _("unsupported static rounding/sae"); | |
6229 | break; | |
6230 | case rc_sae_operand_not_last_imm: | |
6231 | if (intel_syntax) | |
6232 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6233 | else | |
6234 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6235 | break; | |
6236 | case invalid_register_operand: | |
6237 | err_msg = _("invalid register operand"); | |
6238 | break; | |
a65babc9 L |
6239 | } |
6240 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6241 | current_templates->start->name); |
fa99fab2 | 6242 | return NULL; |
29b0f896 | 6243 | } |
252b5132 | 6244 | |
29b0f896 AM |
6245 | if (!quiet_warnings) |
6246 | { | |
6247 | if (!intel_syntax | |
0cfa3eb3 | 6248 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
6f2f06be | 6249 | as_warn (_("indirect %s without `*'"), t->name); |
29b0f896 | 6250 | |
40fb9820 | 6251 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 6252 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
6253 | { |
6254 | /* Warn them that a data or address size prefix doesn't | |
6255 | affect assembly of the next line of code. */ | |
6256 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6257 | } | |
6258 | } | |
6259 | ||
6260 | /* Copy the template we found. */ | |
6261 | i.tm = *t; | |
539e75ad L |
6262 | |
6263 | if (addr_prefix_disp != -1) | |
6264 | i.tm.operand_types[addr_prefix_disp] | |
6265 | = operand_types[addr_prefix_disp]; | |
6266 | ||
29b0f896 AM |
6267 | if (found_reverse_match) |
6268 | { | |
dfd69174 JB |
6269 | /* If we found a reverse match we must alter the opcode direction |
6270 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6271 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6272 | |
6273 | i.tm.base_opcode ^= found_reverse_match; | |
6274 | ||
f5eb1d70 JB |
6275 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6276 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6277 | |
6278 | /* Certain SIMD insns have their load forms specified in the opcode | |
6279 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6280 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6281 | i.tm.opcode_modifier.regmem | |
6282 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6283 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6284 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6285 | } |
6286 | ||
fa99fab2 | 6287 | return t; |
29b0f896 AM |
6288 | } |
6289 | ||
6290 | static int | |
e3bb37b5 | 6291 | check_string (void) |
29b0f896 | 6292 | { |
51c8edf6 JB |
6293 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
6294 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 6295 | |
51c8edf6 | 6296 | if (i.seg[op] != NULL && i.seg[op] != &es) |
29b0f896 | 6297 | { |
51c8edf6 JB |
6298 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
6299 | i.tm.name, | |
6300 | intel_syntax ? i.tm.operands - es_op : es_op + 1, | |
6301 | register_prefix); | |
6302 | return 0; | |
29b0f896 | 6303 | } |
51c8edf6 JB |
6304 | |
6305 | /* There's only ever one segment override allowed per instruction. | |
6306 | This instruction possibly has a legal segment override on the | |
6307 | second operand, so copy the segment to where non-string | |
6308 | instructions store it, allowing common code. */ | |
6309 | i.seg[op] = i.seg[1]; | |
6310 | ||
29b0f896 AM |
6311 | return 1; |
6312 | } | |
6313 | ||
6314 | static int | |
543613e9 | 6315 | process_suffix (void) |
29b0f896 AM |
6316 | { |
6317 | /* If matched instruction specifies an explicit instruction mnemonic | |
6318 | suffix, use it. */ | |
673fe0f0 | 6319 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6320 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6321 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6322 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6323 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6324 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 6325 | else if (i.reg_operands |
c8f8eebc JB |
6326 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
6327 | && !i.tm.opcode_modifier.addrprefixopreg) | |
29b0f896 | 6328 | { |
65fca059 JB |
6329 | unsigned int numop = i.operands; |
6330 | ||
6331 | /* movsx/movzx want only their source operand considered here, for the | |
6332 | ambiguity checking below. The suffix will be replaced afterwards | |
6333 | to represent the destination (register). */ | |
6334 | if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w) | |
6335 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) | |
6336 | --i.operands; | |
6337 | ||
29b0f896 | 6338 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 6339 | based on GPR operands. */ |
29b0f896 AM |
6340 | if (!i.suffix) |
6341 | { | |
6342 | /* We take i.suffix from the last register operand specified, | |
6343 | Destination register type is more significant than source | |
381d071f L |
6344 | register type. crc32 in SSE4.2 prefers source register |
6345 | type. */ | |
1a035124 | 6346 | unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1; |
20592a94 | 6347 | |
1a035124 JB |
6348 | while (op--) |
6349 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
6350 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
6351 | { | |
6352 | if (i.types[op].bitfield.class != Reg) | |
6353 | continue; | |
6354 | if (i.types[op].bitfield.byte) | |
6355 | i.suffix = BYTE_MNEM_SUFFIX; | |
6356 | else if (i.types[op].bitfield.word) | |
6357 | i.suffix = WORD_MNEM_SUFFIX; | |
6358 | else if (i.types[op].bitfield.dword) | |
6359 | i.suffix = LONG_MNEM_SUFFIX; | |
6360 | else if (i.types[op].bitfield.qword) | |
6361 | i.suffix = QWORD_MNEM_SUFFIX; | |
6362 | else | |
6363 | continue; | |
6364 | break; | |
6365 | } | |
65fca059 JB |
6366 | |
6367 | /* As an exception, movsx/movzx silently default to a byte source | |
6368 | in AT&T mode. */ | |
6369 | if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w | |
6370 | && !i.suffix && !intel_syntax) | |
6371 | i.suffix = BYTE_MNEM_SUFFIX; | |
29b0f896 AM |
6372 | } |
6373 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6374 | { | |
2eb952a4 | 6375 | if (intel_syntax |
3cd7f3e3 | 6376 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
6377 | && i.tm.opcode_modifier.no_bsuf) |
6378 | i.suffix = 0; | |
6379 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6380 | return 0; |
6381 | } | |
6382 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6383 | { | |
2eb952a4 | 6384 | if (intel_syntax |
3cd7f3e3 | 6385 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
6386 | && i.tm.opcode_modifier.no_lsuf |
6387 | && !i.tm.opcode_modifier.todword | |
6388 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6389 | i.suffix = 0; |
6390 | else if (!check_long_reg ()) | |
29b0f896 AM |
6391 | return 0; |
6392 | } | |
6393 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6394 | { | |
955e1e6a | 6395 | if (intel_syntax |
3cd7f3e3 | 6396 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
6397 | && i.tm.opcode_modifier.no_qsuf |
6398 | && !i.tm.opcode_modifier.todword | |
6399 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6400 | i.suffix = 0; |
6401 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6402 | return 0; |
6403 | } | |
6404 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6405 | { | |
2eb952a4 | 6406 | if (intel_syntax |
3cd7f3e3 | 6407 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
6408 | && i.tm.opcode_modifier.no_wsuf) |
6409 | i.suffix = 0; | |
6410 | else if (!check_word_reg ()) | |
29b0f896 AM |
6411 | return 0; |
6412 | } | |
3cd7f3e3 L |
6413 | else if (intel_syntax |
6414 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
6415 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6416 | ; | |
6417 | else | |
6418 | abort (); | |
65fca059 JB |
6419 | |
6420 | /* Undo the movsx/movzx change done above. */ | |
6421 | i.operands = numop; | |
29b0f896 | 6422 | } |
3cd7f3e3 L |
6423 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
6424 | && !i.suffix) | |
29b0f896 | 6425 | { |
13e600d0 JB |
6426 | i.suffix = stackop_size; |
6427 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
6428 | { |
6429 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
6430 | .code16gcc directive to support 16-bit mode with | |
6431 | 32-bit address. For IRET without a suffix, generate | |
6432 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
6433 | handler. */ | |
13e600d0 JB |
6434 | if (i.tm.base_opcode == 0xcf) |
6435 | { | |
6436 | i.suffix = WORD_MNEM_SUFFIX; | |
6437 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
6438 | } | |
6439 | /* Warn about changed behavior for segment register push/pop. */ | |
6440 | else if ((i.tm.base_opcode | 1) == 0x07) | |
6441 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
6442 | i.tm.name); | |
06f74c5c | 6443 | } |
29b0f896 | 6444 | } |
c006a730 | 6445 | else if (!i.suffix |
0cfa3eb3 JB |
6446 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
6447 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
6448 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
64e74474 AM |
6449 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6450 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6451 | { |
6452 | switch (flag_code) | |
6453 | { | |
6454 | case CODE_64BIT: | |
40fb9820 | 6455 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6456 | { |
6457 | i.suffix = QWORD_MNEM_SUFFIX; | |
6458 | break; | |
6459 | } | |
1a0670f3 | 6460 | /* Fall through. */ |
9306ca4a | 6461 | case CODE_32BIT: |
40fb9820 | 6462 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6463 | i.suffix = LONG_MNEM_SUFFIX; |
6464 | break; | |
6465 | case CODE_16BIT: | |
40fb9820 | 6466 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6467 | i.suffix = WORD_MNEM_SUFFIX; |
6468 | break; | |
6469 | } | |
6470 | } | |
252b5132 | 6471 | |
c006a730 | 6472 | if (!i.suffix |
3cd7f3e3 | 6473 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
6474 | /* Also cover lret/retf/iret in 64-bit mode. */ |
6475 | || (flag_code == CODE_64BIT | |
6476 | && !i.tm.opcode_modifier.no_lsuf | |
6477 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 6478 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
62b3f548 JB |
6479 | /* Accept FLDENV et al without suffix. */ |
6480 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 6481 | { |
6c0946d0 | 6482 | unsigned int suffixes, evex = 0; |
c006a730 JB |
6483 | |
6484 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
6485 | if (!i.tm.opcode_modifier.no_wsuf) | |
6486 | suffixes |= 1 << 1; | |
6487 | if (!i.tm.opcode_modifier.no_lsuf) | |
6488 | suffixes |= 1 << 2; | |
6489 | if (!i.tm.opcode_modifier.no_ldsuf) | |
6490 | suffixes |= 1 << 3; | |
6491 | if (!i.tm.opcode_modifier.no_ssuf) | |
6492 | suffixes |= 1 << 4; | |
6493 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
6494 | suffixes |= 1 << 5; | |
6495 | ||
6c0946d0 JB |
6496 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
6497 | also suitable for AT&T syntax mode, it was requested that this be | |
6498 | restricted to just Intel syntax. */ | |
b9915cbc | 6499 | if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast) |
6c0946d0 | 6500 | { |
b9915cbc | 6501 | unsigned int op; |
6c0946d0 | 6502 | |
b9915cbc | 6503 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 6504 | { |
b9915cbc JB |
6505 | if (is_evex_encoding (&i.tm) |
6506 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6c0946d0 | 6507 | { |
b9915cbc JB |
6508 | if (i.tm.operand_types[op].bitfield.ymmword) |
6509 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
6510 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6511 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
6512 | if (!i.tm.opcode_modifier.evex | |
6513 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
6514 | i.tm.opcode_modifier.evex = EVEX512; | |
6515 | } | |
6c0946d0 | 6516 | |
b9915cbc JB |
6517 | if (i.tm.operand_types[op].bitfield.xmmword |
6518 | + i.tm.operand_types[op].bitfield.ymmword | |
6519 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
6520 | continue; | |
6c0946d0 | 6521 | |
b9915cbc JB |
6522 | /* Any properly sized operand disambiguates the insn. */ |
6523 | if (i.types[op].bitfield.xmmword | |
6524 | || i.types[op].bitfield.ymmword | |
6525 | || i.types[op].bitfield.zmmword) | |
6526 | { | |
6527 | suffixes &= ~(7 << 6); | |
6528 | evex = 0; | |
6529 | break; | |
6530 | } | |
6c0946d0 | 6531 | |
b9915cbc JB |
6532 | if ((i.flags[op] & Operand_Mem) |
6533 | && i.tm.operand_types[op].bitfield.unspecified) | |
6534 | { | |
6535 | if (i.tm.operand_types[op].bitfield.xmmword) | |
6536 | suffixes |= 1 << 6; | |
6537 | if (i.tm.operand_types[op].bitfield.ymmword) | |
6538 | suffixes |= 1 << 7; | |
6539 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6540 | suffixes |= 1 << 8; | |
6541 | if (is_evex_encoding (&i.tm)) | |
6542 | evex = EVEX512; | |
6c0946d0 JB |
6543 | } |
6544 | } | |
6545 | } | |
6546 | ||
6547 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 6548 | if (suffixes & (suffixes - 1)) |
9306ca4a | 6549 | { |
873494c8 | 6550 | if (intel_syntax |
3cd7f3e3 | 6551 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 6552 | || operand_check == check_error)) |
9306ca4a | 6553 | { |
c006a730 | 6554 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
9306ca4a JB |
6555 | return 0; |
6556 | } | |
c006a730 | 6557 | if (operand_check == check_error) |
9306ca4a | 6558 | { |
c006a730 JB |
6559 | as_bad (_("no instruction mnemonic suffix given and " |
6560 | "no register operands; can't size `%s'"), i.tm.name); | |
9306ca4a JB |
6561 | return 0; |
6562 | } | |
c006a730 | 6563 | if (operand_check == check_warning) |
873494c8 JB |
6564 | as_warn (_("%s; using default for `%s'"), |
6565 | intel_syntax | |
6566 | ? _("ambiguous operand size") | |
6567 | : _("no instruction mnemonic suffix given and " | |
6568 | "no register operands"), | |
6569 | i.tm.name); | |
c006a730 JB |
6570 | |
6571 | if (i.tm.opcode_modifier.floatmf) | |
6572 | i.suffix = SHORT_MNEM_SUFFIX; | |
65fca059 JB |
6573 | else if ((i.tm.base_opcode | 8) == 0xfbe |
6574 | || (i.tm.base_opcode == 0x63 | |
6575 | && i.tm.cpu_flags.bitfield.cpu64)) | |
6576 | /* handled below */; | |
6c0946d0 JB |
6577 | else if (evex) |
6578 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
6579 | else if (flag_code == CODE_16BIT) |
6580 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 6581 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 6582 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
6583 | else |
6584 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 6585 | } |
29b0f896 | 6586 | } |
252b5132 | 6587 | |
65fca059 JB |
6588 | if ((i.tm.base_opcode | 8) == 0xfbe |
6589 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) | |
6590 | { | |
6591 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
6592 | In AT&T syntax, if there is no suffix (warned about above), the default | |
6593 | will be byte extension. */ | |
6594 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
6595 | i.tm.base_opcode |= 1; | |
6596 | ||
6597 | /* For further processing, the suffix should represent the destination | |
6598 | (register). This is already the case when one was used with | |
6599 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
6600 | no suffix to begin with. */ | |
6601 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
6602 | { | |
6603 | if (i.types[1].bitfield.word) | |
6604 | i.suffix = WORD_MNEM_SUFFIX; | |
6605 | else if (i.types[1].bitfield.qword) | |
6606 | i.suffix = QWORD_MNEM_SUFFIX; | |
6607 | else | |
6608 | i.suffix = LONG_MNEM_SUFFIX; | |
6609 | ||
6610 | i.tm.opcode_modifier.w = 0; | |
6611 | } | |
6612 | } | |
6613 | ||
50128d0c JB |
6614 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
6615 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
6616 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
6617 | ||
d2224064 JB |
6618 | /* Change the opcode based on the operand size given by i.suffix. */ |
6619 | switch (i.suffix) | |
29b0f896 | 6620 | { |
d2224064 JB |
6621 | /* Size floating point instruction. */ |
6622 | case LONG_MNEM_SUFFIX: | |
6623 | if (i.tm.opcode_modifier.floatmf) | |
6624 | { | |
6625 | i.tm.base_opcode ^= 4; | |
6626 | break; | |
6627 | } | |
6628 | /* fall through */ | |
6629 | case WORD_MNEM_SUFFIX: | |
6630 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6631 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6632 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6633 | { |
50128d0c | 6634 | if (i.short_form) |
29b0f896 AM |
6635 | i.tm.base_opcode |= 8; |
6636 | else | |
6637 | i.tm.base_opcode |= 1; | |
6638 | } | |
d2224064 JB |
6639 | /* fall through */ |
6640 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6641 | /* Now select between word & dword operations via the operand |
6642 | size prefix, except for instructions that will ignore this | |
6643 | prefix anyway. */ | |
c8f8eebc | 6644 | if (i.suffix != QWORD_MNEM_SUFFIX |
3cd7f3e3 | 6645 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc JB |
6646 | && !i.tm.opcode_modifier.floatmf |
6647 | && !is_any_vex_encoding (&i.tm) | |
6648 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
6649 | || (flag_code == CODE_64BIT | |
6650 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
6651 | { |
6652 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6653 | |
0cfa3eb3 | 6654 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 6655 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6656 | |
29b0f896 AM |
6657 | if (!add_prefix (prefix)) |
6658 | return 0; | |
24eab124 | 6659 | } |
252b5132 | 6660 | |
29b0f896 AM |
6661 | /* Set mode64 for an operand. */ |
6662 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6663 | && flag_code == CODE_64BIT |
d2224064 | 6664 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6665 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6666 | need rex64. */ |
6667 | && ! (i.operands == 2 | |
6668 | && i.tm.base_opcode == 0x90 | |
6669 | && i.tm.extension_opcode == None | |
75e5731b JB |
6670 | && i.types[0].bitfield.instance == Accum |
6671 | && i.types[0].bitfield.qword | |
6672 | && i.types[1].bitfield.instance == Accum | |
6673 | && i.types[1].bitfield.qword)) | |
d2224064 | 6674 | i.rex |= REX_W; |
3e73aa7c | 6675 | |
d2224064 | 6676 | break; |
29b0f896 | 6677 | } |
7ecd2f8b | 6678 | |
c8f8eebc | 6679 | if (i.tm.opcode_modifier.addrprefixopreg) |
c0a30a9f | 6680 | { |
c8f8eebc JB |
6681 | gas_assert (!i.suffix); |
6682 | gas_assert (i.reg_operands); | |
c0a30a9f | 6683 | |
c8f8eebc JB |
6684 | if (i.tm.operand_types[0].bitfield.instance == Accum |
6685 | || i.operands == 1) | |
6686 | { | |
6687 | /* The address size override prefix changes the size of the | |
6688 | first operand. */ | |
6689 | if (flag_code == CODE_64BIT | |
6690 | && i.op[0].regs->reg_type.bitfield.word) | |
6691 | { | |
6692 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
6693 | i.tm.name); | |
6694 | return 0; | |
6695 | } | |
6696 | ||
6697 | if ((flag_code == CODE_32BIT | |
6698 | ? i.op[0].regs->reg_type.bitfield.word | |
6699 | : i.op[0].regs->reg_type.bitfield.dword) | |
6700 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
6701 | return 0; | |
6702 | } | |
c0a30a9f L |
6703 | else |
6704 | { | |
c8f8eebc JB |
6705 | /* Check invalid register operand when the address size override |
6706 | prefix changes the size of register operands. */ | |
6707 | unsigned int op; | |
6708 | enum { need_word, need_dword, need_qword } need; | |
6709 | ||
6710 | if (flag_code == CODE_32BIT) | |
6711 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6712 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
6713 | need = need_dword; |
6714 | else | |
6715 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 6716 | |
c8f8eebc JB |
6717 | for (op = 0; op < i.operands; op++) |
6718 | { | |
6719 | if (i.types[op].bitfield.class != Reg) | |
6720 | continue; | |
6721 | ||
6722 | switch (need) | |
6723 | { | |
6724 | case need_word: | |
6725 | if (i.op[op].regs->reg_type.bitfield.word) | |
6726 | continue; | |
6727 | break; | |
6728 | case need_dword: | |
6729 | if (i.op[op].regs->reg_type.bitfield.dword) | |
6730 | continue; | |
6731 | break; | |
6732 | case need_qword: | |
6733 | if (i.op[op].regs->reg_type.bitfield.qword) | |
6734 | continue; | |
6735 | break; | |
6736 | } | |
6737 | ||
6738 | as_bad (_("invalid register operand size for `%s'"), | |
6739 | i.tm.name); | |
6740 | return 0; | |
6741 | } | |
6742 | } | |
c0a30a9f L |
6743 | } |
6744 | ||
29b0f896 AM |
6745 | return 1; |
6746 | } | |
3e73aa7c | 6747 | |
29b0f896 | 6748 | static int |
543613e9 | 6749 | check_byte_reg (void) |
29b0f896 AM |
6750 | { |
6751 | int op; | |
543613e9 | 6752 | |
29b0f896 AM |
6753 | for (op = i.operands; --op >= 0;) |
6754 | { | |
dc821c5f | 6755 | /* Skip non-register operands. */ |
bab6aec1 | 6756 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
6757 | continue; |
6758 | ||
29b0f896 AM |
6759 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6760 | 32 bit version of an eight bit register, we will just use the | |
6761 | low portion, and that's OK too. */ | |
dc821c5f | 6762 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6763 | continue; |
6764 | ||
5a819eb9 | 6765 | /* I/O port address operands are OK too. */ |
75e5731b JB |
6766 | if (i.tm.operand_types[op].bitfield.instance == RegD |
6767 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
6768 | continue; |
6769 | ||
9706160a JB |
6770 | /* crc32 only wants its source operand checked here. */ |
6771 | if (i.tm.base_opcode == 0xf20f38f0 && op) | |
9344ff29 L |
6772 | continue; |
6773 | ||
29b0f896 | 6774 | /* Any other register is bad. */ |
bab6aec1 | 6775 | if (i.types[op].bitfield.class == Reg |
3528c362 JB |
6776 | || i.types[op].bitfield.class == RegMMX |
6777 | || i.types[op].bitfield.class == RegSIMD | |
00cee14f | 6778 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
6779 | || i.types[op].bitfield.class == RegCR |
6780 | || i.types[op].bitfield.class == RegDR | |
6781 | || i.types[op].bitfield.class == RegTR) | |
29b0f896 | 6782 | { |
a540244d L |
6783 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6784 | register_prefix, | |
29b0f896 AM |
6785 | i.op[op].regs->reg_name, |
6786 | i.tm.name, | |
6787 | i.suffix); | |
6788 | return 0; | |
6789 | } | |
6790 | } | |
6791 | return 1; | |
6792 | } | |
6793 | ||
6794 | static int | |
e3bb37b5 | 6795 | check_long_reg (void) |
29b0f896 AM |
6796 | { |
6797 | int op; | |
6798 | ||
6799 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6800 | /* Skip non-register operands. */ |
bab6aec1 | 6801 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6802 | continue; |
29b0f896 AM |
6803 | /* Reject eight bit registers, except where the template requires |
6804 | them. (eg. movzb) */ | |
dc821c5f | 6805 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6806 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6807 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6808 | && (i.tm.operand_types[op].bitfield.word |
6809 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6810 | { |
a540244d L |
6811 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6812 | register_prefix, | |
29b0f896 AM |
6813 | i.op[op].regs->reg_name, |
6814 | i.tm.name, | |
6815 | i.suffix); | |
6816 | return 0; | |
6817 | } | |
be4c5e58 L |
6818 | /* Error if the e prefix on a general reg is missing. */ |
6819 | else if (i.types[op].bitfield.word | |
bab6aec1 | 6820 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6821 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6822 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 6823 | { |
be4c5e58 L |
6824 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
6825 | register_prefix, i.op[op].regs->reg_name, | |
6826 | i.suffix); | |
6827 | return 0; | |
252b5132 | 6828 | } |
e4630f71 | 6829 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 6830 | else if (i.types[op].bitfield.qword |
bab6aec1 | 6831 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6832 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6833 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 6834 | { |
34828aad | 6835 | if (intel_syntax |
65fca059 | 6836 | && i.tm.opcode_modifier.toqword |
3528c362 | 6837 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6838 | { |
ca61edf2 | 6839 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6840 | i.suffix = QWORD_MNEM_SUFFIX; |
6841 | } | |
6842 | else | |
6843 | { | |
2b5d6a91 | 6844 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6845 | register_prefix, i.op[op].regs->reg_name, |
6846 | i.suffix); | |
6847 | return 0; | |
6848 | } | |
29b0f896 AM |
6849 | } |
6850 | return 1; | |
6851 | } | |
252b5132 | 6852 | |
29b0f896 | 6853 | static int |
e3bb37b5 | 6854 | check_qword_reg (void) |
29b0f896 AM |
6855 | { |
6856 | int op; | |
252b5132 | 6857 | |
29b0f896 | 6858 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 6859 | /* Skip non-register operands. */ |
bab6aec1 | 6860 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6861 | continue; |
29b0f896 AM |
6862 | /* Reject eight bit registers, except where the template requires |
6863 | them. (eg. movzb) */ | |
dc821c5f | 6864 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6865 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6866 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6867 | && (i.tm.operand_types[op].bitfield.word |
6868 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6869 | { |
a540244d L |
6870 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6871 | register_prefix, | |
29b0f896 AM |
6872 | i.op[op].regs->reg_name, |
6873 | i.tm.name, | |
6874 | i.suffix); | |
6875 | return 0; | |
6876 | } | |
e4630f71 | 6877 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6878 | else if ((i.types[op].bitfield.word |
6879 | || i.types[op].bitfield.dword) | |
bab6aec1 | 6880 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6881 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6882 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
6883 | { |
6884 | /* Prohibit these changes in the 64bit mode, since the | |
6885 | lowering is more complicated. */ | |
34828aad | 6886 | if (intel_syntax |
ca61edf2 | 6887 | && i.tm.opcode_modifier.todword |
3528c362 | 6888 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6889 | { |
ca61edf2 | 6890 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6891 | i.suffix = LONG_MNEM_SUFFIX; |
6892 | } | |
6893 | else | |
6894 | { | |
2b5d6a91 | 6895 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6896 | register_prefix, i.op[op].regs->reg_name, |
6897 | i.suffix); | |
6898 | return 0; | |
6899 | } | |
252b5132 | 6900 | } |
29b0f896 AM |
6901 | return 1; |
6902 | } | |
252b5132 | 6903 | |
29b0f896 | 6904 | static int |
e3bb37b5 | 6905 | check_word_reg (void) |
29b0f896 AM |
6906 | { |
6907 | int op; | |
6908 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6909 | /* Skip non-register operands. */ |
bab6aec1 | 6910 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6911 | continue; |
29b0f896 AM |
6912 | /* Reject eight bit registers, except where the template requires |
6913 | them. (eg. movzb) */ | |
dc821c5f | 6914 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6915 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6916 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6917 | && (i.tm.operand_types[op].bitfield.word |
6918 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6919 | { |
a540244d L |
6920 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6921 | register_prefix, | |
29b0f896 AM |
6922 | i.op[op].regs->reg_name, |
6923 | i.tm.name, | |
6924 | i.suffix); | |
6925 | return 0; | |
6926 | } | |
9706160a JB |
6927 | /* Error if the e or r prefix on a general reg is present. */ |
6928 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 6929 | || i.types[op].bitfield.qword) |
bab6aec1 | 6930 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6931 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6932 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 6933 | { |
9706160a JB |
6934 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
6935 | register_prefix, i.op[op].regs->reg_name, | |
6936 | i.suffix); | |
6937 | return 0; | |
29b0f896 AM |
6938 | } |
6939 | return 1; | |
6940 | } | |
252b5132 | 6941 | |
29b0f896 | 6942 | static int |
40fb9820 | 6943 | update_imm (unsigned int j) |
29b0f896 | 6944 | { |
bc0844ae | 6945 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6946 | if ((overlap.bitfield.imm8 |
6947 | || overlap.bitfield.imm8s | |
6948 | || overlap.bitfield.imm16 | |
6949 | || overlap.bitfield.imm32 | |
6950 | || overlap.bitfield.imm32s | |
6951 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6952 | && !operand_type_equal (&overlap, &imm8) |
6953 | && !operand_type_equal (&overlap, &imm8s) | |
6954 | && !operand_type_equal (&overlap, &imm16) | |
6955 | && !operand_type_equal (&overlap, &imm32) | |
6956 | && !operand_type_equal (&overlap, &imm32s) | |
6957 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6958 | { |
6959 | if (i.suffix) | |
6960 | { | |
40fb9820 L |
6961 | i386_operand_type temp; |
6962 | ||
0dfbf9d7 | 6963 | operand_type_set (&temp, 0); |
7ab9ffdd | 6964 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6965 | { |
6966 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6967 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6968 | } | |
6969 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6970 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6971 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6972 | { | |
6973 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6974 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6975 | } | |
6976 | else | |
6977 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6978 | overlap = temp; | |
29b0f896 | 6979 | } |
0dfbf9d7 L |
6980 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6981 | || operand_type_equal (&overlap, &imm16_32) | |
6982 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6983 | { |
40fb9820 | 6984 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6985 | overlap = imm16; |
40fb9820 | 6986 | else |
65da13b5 | 6987 | overlap = imm32s; |
29b0f896 | 6988 | } |
0dfbf9d7 L |
6989 | if (!operand_type_equal (&overlap, &imm8) |
6990 | && !operand_type_equal (&overlap, &imm8s) | |
6991 | && !operand_type_equal (&overlap, &imm16) | |
6992 | && !operand_type_equal (&overlap, &imm32) | |
6993 | && !operand_type_equal (&overlap, &imm32s) | |
6994 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6995 | { |
4eed87de AM |
6996 | as_bad (_("no instruction mnemonic suffix given; " |
6997 | "can't determine immediate size")); | |
29b0f896 AM |
6998 | return 0; |
6999 | } | |
7000 | } | |
40fb9820 | 7001 | i.types[j] = overlap; |
29b0f896 | 7002 | |
40fb9820 L |
7003 | return 1; |
7004 | } | |
7005 | ||
7006 | static int | |
7007 | finalize_imm (void) | |
7008 | { | |
bc0844ae | 7009 | unsigned int j, n; |
29b0f896 | 7010 | |
bc0844ae L |
7011 | /* Update the first 2 immediate operands. */ |
7012 | n = i.operands > 2 ? 2 : i.operands; | |
7013 | if (n) | |
7014 | { | |
7015 | for (j = 0; j < n; j++) | |
7016 | if (update_imm (j) == 0) | |
7017 | return 0; | |
40fb9820 | 7018 | |
bc0844ae L |
7019 | /* The 3rd operand can't be immediate operand. */ |
7020 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
7021 | } | |
29b0f896 AM |
7022 | |
7023 | return 1; | |
7024 | } | |
7025 | ||
7026 | static int | |
e3bb37b5 | 7027 | process_operands (void) |
29b0f896 AM |
7028 | { |
7029 | /* Default segment register this instruction will use for memory | |
7030 | accesses. 0 means unknown. This is only for optimizing out | |
7031 | unnecessary segment overrides. */ | |
7032 | const seg_entry *default_seg = 0; | |
7033 | ||
2426c15f | 7034 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 7035 | { |
91d6fa6a NC |
7036 | unsigned int dupl = i.operands; |
7037 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
7038 | unsigned int j; |
7039 | ||
c0f3af97 | 7040 | /* The destination must be an xmm register. */ |
9c2799c2 | 7041 | gas_assert (i.reg_operands |
91d6fa6a | 7042 | && MAX_OPERANDS > dupl |
7ab9ffdd | 7043 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 7044 | |
75e5731b | 7045 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7046 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 7047 | { |
8cd7925b | 7048 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
7049 | { |
7050 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
7051 | sources. */ | |
75e5731b | 7052 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 7053 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
7054 | goto duplicate; |
7055 | } | |
e2ec9d29 | 7056 | else |
c0f3af97 L |
7057 | { |
7058 | /* We remove the first xmm0 and keep the number of | |
7059 | operands unchanged, which in fact duplicates the | |
7060 | destination. */ | |
7061 | for (j = 1; j < i.operands; j++) | |
7062 | { | |
7063 | i.op[j - 1] = i.op[j]; | |
7064 | i.types[j - 1] = i.types[j]; | |
7065 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 7066 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
7067 | } |
7068 | } | |
7069 | } | |
7070 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 7071 | { |
91d6fa6a | 7072 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
7073 | && (i.tm.opcode_modifier.vexsources |
7074 | == VEX3SOURCES)); | |
c0f3af97 L |
7075 | |
7076 | /* Add the implicit xmm0 for instructions with VEX prefix | |
7077 | and 3 sources. */ | |
7078 | for (j = i.operands; j > 0; j--) | |
7079 | { | |
7080 | i.op[j] = i.op[j - 1]; | |
7081 | i.types[j] = i.types[j - 1]; | |
7082 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 7083 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
7084 | } |
7085 | i.op[0].regs | |
7086 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 7087 | i.types[0] = regxmm; |
c0f3af97 L |
7088 | i.tm.operand_types[0] = regxmm; |
7089 | ||
7090 | i.operands += 2; | |
7091 | i.reg_operands += 2; | |
7092 | i.tm.operands += 2; | |
7093 | ||
91d6fa6a | 7094 | dupl++; |
c0f3af97 | 7095 | dest++; |
91d6fa6a NC |
7096 | i.op[dupl] = i.op[dest]; |
7097 | i.types[dupl] = i.types[dest]; | |
7098 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7099 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 7100 | } |
c0f3af97 L |
7101 | else |
7102 | { | |
dc1e8a47 | 7103 | duplicate: |
c0f3af97 L |
7104 | i.operands++; |
7105 | i.reg_operands++; | |
7106 | i.tm.operands++; | |
7107 | ||
91d6fa6a NC |
7108 | i.op[dupl] = i.op[dest]; |
7109 | i.types[dupl] = i.types[dest]; | |
7110 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7111 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
7112 | } |
7113 | ||
7114 | if (i.tm.opcode_modifier.immext) | |
7115 | process_immext (); | |
7116 | } | |
75e5731b | 7117 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7118 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
7119 | { |
7120 | unsigned int j; | |
7121 | ||
9fcfb3d7 L |
7122 | for (j = 1; j < i.operands; j++) |
7123 | { | |
7124 | i.op[j - 1] = i.op[j]; | |
7125 | i.types[j - 1] = i.types[j]; | |
7126 | ||
7127 | /* We need to adjust fields in i.tm since they are used by | |
7128 | build_modrm_byte. */ | |
7129 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
7130 | |
7131 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
7132 | } |
7133 | ||
e2ec9d29 L |
7134 | i.operands--; |
7135 | i.reg_operands--; | |
e2ec9d29 L |
7136 | i.tm.operands--; |
7137 | } | |
920d2ddc IT |
7138 | else if (i.tm.opcode_modifier.implicitquadgroup) |
7139 | { | |
a477a8c4 JB |
7140 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
7141 | ||
920d2ddc | 7142 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 7143 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
7144 | regnum = register_number (i.op[1].regs); |
7145 | first_reg_in_group = regnum & ~3; | |
7146 | last_reg_in_group = first_reg_in_group + 3; | |
7147 | if (regnum != first_reg_in_group) | |
7148 | as_warn (_("source register `%s%s' implicitly denotes" | |
7149 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7150 | register_prefix, i.op[1].regs->reg_name, | |
7151 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7152 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7153 | i.tm.name); | |
7154 | } | |
e2ec9d29 L |
7155 | else if (i.tm.opcode_modifier.regkludge) |
7156 | { | |
7157 | /* The imul $imm, %reg instruction is converted into | |
7158 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7159 | is converted into xor %reg, %reg. */ | |
7160 | ||
7161 | unsigned int first_reg_op; | |
7162 | ||
7163 | if (operand_type_check (i.types[0], reg)) | |
7164 | first_reg_op = 0; | |
7165 | else | |
7166 | first_reg_op = 1; | |
7167 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7168 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7169 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7170 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7171 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7172 | i.operands++; | |
7173 | i.reg_operands++; | |
29b0f896 AM |
7174 | } |
7175 | ||
85b80b0f | 7176 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7177 | { |
7178 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7179 | must be put into the modrm byte). Now, we make the modrm and |
7180 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7181 | |
7182 | default_seg = build_modrm_byte (); | |
7183 | } | |
00cee14f | 7184 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7185 | { |
7186 | if (flag_code != CODE_64BIT | |
7187 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7188 | && i.op[0].regs->reg_num == 1 | |
7189 | : (i.tm.base_opcode | 1) == POP_SEG386_SHORT | |
7190 | && i.op[0].regs->reg_num < 4) | |
7191 | { | |
7192 | as_bad (_("you can't `%s %s%s'"), | |
7193 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7194 | return 0; | |
7195 | } | |
7196 | if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 ) | |
7197 | { | |
7198 | i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; | |
7199 | i.tm.opcode_length = 2; | |
7200 | } | |
7201 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7202 | } | |
8a2ed489 | 7203 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
7204 | { |
7205 | default_seg = &ds; | |
7206 | } | |
40fb9820 | 7207 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7208 | { |
7209 | /* For the string instructions that allow a segment override | |
7210 | on one of their operands, the default segment is ds. */ | |
7211 | default_seg = &ds; | |
7212 | } | |
50128d0c | 7213 | else if (i.short_form) |
85b80b0f JB |
7214 | { |
7215 | /* The register or float register operand is in operand | |
7216 | 0 or 1. */ | |
bab6aec1 | 7217 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7218 | |
7219 | /* Register goes in low 3 bits of opcode. */ | |
7220 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7221 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7222 | i.rex |= REX_B; | |
7223 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7224 | { | |
7225 | /* Warn about some common errors, but press on regardless. | |
7226 | The first case can be generated by gcc (<= 2.8.1). */ | |
7227 | if (i.operands == 2) | |
7228 | { | |
7229 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7230 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7231 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7232 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7233 | } | |
7234 | else | |
7235 | { | |
7236 | /* Extraneous `l' suffix on fp insn. */ | |
7237 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7238 | register_prefix, i.op[0].regs->reg_name); | |
7239 | } | |
7240 | } | |
7241 | } | |
29b0f896 | 7242 | |
514a8bb0 | 7243 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
514a8bb0 JB |
7244 | && i.tm.base_opcode == 0x8d /* lea */ |
7245 | && !is_any_vex_encoding(&i.tm)) | |
92334ad2 JB |
7246 | { |
7247 | if (!quiet_warnings) | |
7248 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); | |
7249 | if (optimize) | |
7250 | { | |
7251 | i.seg[0] = NULL; | |
7252 | i.prefix[SEG_PREFIX] = 0; | |
7253 | } | |
7254 | } | |
52271982 AM |
7255 | |
7256 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
7257 | is neither the default nor the one already recorded from a prefix, |
7258 | use an opcode prefix to select it. If we never figured out what | |
7259 | the default segment is, then default_seg will be zero at this | |
7260 | point, and the specified segment prefix will always be used. */ | |
7261 | if (i.seg[0] | |
7262 | && i.seg[0] != default_seg | |
7263 | && i.seg[0]->seg_prefix != i.prefix[SEG_PREFIX]) | |
29b0f896 AM |
7264 | { |
7265 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
7266 | return 0; | |
7267 | } | |
7268 | return 1; | |
7269 | } | |
7270 | ||
7271 | static const seg_entry * | |
e3bb37b5 | 7272 | build_modrm_byte (void) |
29b0f896 AM |
7273 | { |
7274 | const seg_entry *default_seg = 0; | |
c0f3af97 | 7275 | unsigned int source, dest; |
8cd7925b | 7276 | int vex_3_sources; |
c0f3af97 | 7277 | |
8cd7925b | 7278 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
7279 | if (vex_3_sources) |
7280 | { | |
91d6fa6a | 7281 | unsigned int nds, reg_slot; |
4c2c6516 | 7282 | expressionS *exp; |
c0f3af97 | 7283 | |
6b8d3588 | 7284 | dest = i.operands - 1; |
c0f3af97 | 7285 | nds = dest - 1; |
922d8de8 | 7286 | |
a683cc34 | 7287 | /* There are 2 kinds of instructions: |
bed3d976 | 7288 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 7289 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 7290 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 7291 | ZMM register. |
bed3d976 | 7292 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7293 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7294 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7295 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7296 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 7297 | && i.tm.opcode_modifier.vexw |
3528c362 | 7298 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 7299 | |
48db9223 JB |
7300 | /* If VexW1 is set, the first non-immediate operand is the source and |
7301 | the second non-immediate one is encoded in the immediate operand. */ | |
7302 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7303 | { | |
7304 | source = i.imm_operands; | |
7305 | reg_slot = i.imm_operands + 1; | |
7306 | } | |
7307 | else | |
7308 | { | |
7309 | source = i.imm_operands + 1; | |
7310 | reg_slot = i.imm_operands; | |
7311 | } | |
7312 | ||
a683cc34 | 7313 | if (i.imm_operands == 0) |
bed3d976 JB |
7314 | { |
7315 | /* When there is no immediate operand, generate an 8bit | |
7316 | immediate operand to encode the first operand. */ | |
7317 | exp = &im_expressions[i.imm_operands++]; | |
7318 | i.op[i.operands].imms = exp; | |
7319 | i.types[i.operands] = imm8; | |
7320 | i.operands++; | |
7321 | ||
3528c362 | 7322 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
7323 | exp->X_op = O_constant; |
7324 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7325 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7326 | } | |
922d8de8 | 7327 | else |
bed3d976 | 7328 | { |
9d3bf266 JB |
7329 | gas_assert (i.imm_operands == 1); |
7330 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
7331 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 7332 | |
9d3bf266 JB |
7333 | /* Turn on Imm8 again so that output_imm will generate it. */ |
7334 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 7335 | |
3528c362 | 7336 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 7337 | i.op[0].imms->X_add_number |
bed3d976 | 7338 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 7339 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7340 | } |
a683cc34 | 7341 | |
3528c362 | 7342 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 7343 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7344 | } |
7345 | else | |
7346 | source = dest = 0; | |
29b0f896 AM |
7347 | |
7348 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7349 | implicit registers do not count. If there are 3 register |
7350 | operands, it must be a instruction with VexNDS. For a | |
7351 | instruction with VexNDD, the destination register is encoded | |
7352 | in VEX prefix. If there are 4 register operands, it must be | |
7353 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7354 | if (i.mem_operands == 0 |
7355 | && ((i.reg_operands == 2 | |
2426c15f | 7356 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7357 | || (i.reg_operands == 3 |
2426c15f | 7358 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7359 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7360 | { |
cab737b9 L |
7361 | switch (i.operands) |
7362 | { | |
7363 | case 2: | |
7364 | source = 0; | |
7365 | break; | |
7366 | case 3: | |
c81128dc L |
7367 | /* When there are 3 operands, one of them may be immediate, |
7368 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7369 | the first operand must be shift count register (cl) or it |
7370 | is an instruction with VexNDS. */ | |
9c2799c2 | 7371 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7372 | || (i.imm_operands == 0 |
2426c15f | 7373 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
7374 | || (i.types[0].bitfield.instance == RegC |
7375 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 7376 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
7377 | || (i.types[0].bitfield.instance == RegC |
7378 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
7379 | source = 1; |
7380 | else | |
7381 | source = 0; | |
cab737b9 L |
7382 | break; |
7383 | case 4: | |
368d64cc L |
7384 | /* When there are 4 operands, the first two must be 8bit |
7385 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7386 | one. |
7387 | ||
7388 | For instructions with VexNDS, if the first operand | |
7389 | an imm8, the source operand is the 2nd one. If the last | |
7390 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7391 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7392 | && i.types[0].bitfield.imm8 |
7393 | && i.types[1].bitfield.imm8) | |
2426c15f | 7394 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7395 | && i.imm_operands == 1 |
7396 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7397 | || i.types[i.operands - 1].bitfield.imm8 |
7398 | || i.rounding))); | |
9f2670f2 L |
7399 | if (i.imm_operands == 2) |
7400 | source = 2; | |
7401 | else | |
c0f3af97 L |
7402 | { |
7403 | if (i.types[0].bitfield.imm8) | |
7404 | source = 1; | |
7405 | else | |
7406 | source = 0; | |
7407 | } | |
c0f3af97 L |
7408 | break; |
7409 | case 5: | |
e771e7c9 | 7410 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7411 | { |
7412 | /* For EVEX instructions, when there are 5 operands, the | |
7413 | first one must be immediate operand. If the second one | |
7414 | is immediate operand, the source operand is the 3th | |
7415 | one. If the last one is immediate operand, the source | |
7416 | operand is the 2nd one. */ | |
7417 | gas_assert (i.imm_operands == 2 | |
7418 | && i.tm.opcode_modifier.sae | |
7419 | && operand_type_check (i.types[0], imm)); | |
7420 | if (operand_type_check (i.types[1], imm)) | |
7421 | source = 2; | |
7422 | else if (operand_type_check (i.types[4], imm)) | |
7423 | source = 1; | |
7424 | else | |
7425 | abort (); | |
7426 | } | |
cab737b9 L |
7427 | break; |
7428 | default: | |
7429 | abort (); | |
7430 | } | |
7431 | ||
c0f3af97 L |
7432 | if (!vex_3_sources) |
7433 | { | |
7434 | dest = source + 1; | |
7435 | ||
43234a1e L |
7436 | /* RC/SAE operand could be between DEST and SRC. That happens |
7437 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7438 | register. */ | |
7439 | if (i.rounding && i.rounding->operand == (int) dest) | |
7440 | dest++; | |
7441 | ||
2426c15f | 7442 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7443 | { |
43234a1e | 7444 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7445 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 7446 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
7447 | |
7448 | i386_operand_type op; | |
7449 | unsigned int vvvv; | |
7450 | ||
7451 | /* Check register-only source operand when two source | |
7452 | operands are swapped. */ | |
7453 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7454 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7455 | { | |
7456 | vvvv = source; | |
7457 | source = dest; | |
7458 | } | |
7459 | else | |
7460 | vvvv = dest; | |
7461 | ||
7462 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 7463 | if ((dest + 1) >= i.operands |
bab6aec1 | 7464 | || ((op.bitfield.class != Reg |
dc821c5f | 7465 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 7466 | && op.bitfield.class != RegSIMD |
43234a1e | 7467 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7468 | abort (); |
f12dc422 | 7469 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7470 | dest++; |
7471 | } | |
7472 | } | |
29b0f896 AM |
7473 | |
7474 | i.rm.mode = 3; | |
dfd69174 JB |
7475 | /* One of the register operands will be encoded in the i.rm.reg |
7476 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
7477 | fields. If no form of this instruction supports a memory |
7478 | destination operand, then we assume the source operand may | |
7479 | sometimes be a memory operand and so we need to store the | |
7480 | destination in the i.rm.reg field. */ | |
dfd69174 | 7481 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 7482 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
7483 | { |
7484 | i.rm.reg = i.op[dest].regs->reg_num; | |
7485 | i.rm.regmem = i.op[source].regs->reg_num; | |
3528c362 JB |
7486 | if (i.op[dest].regs->reg_type.bitfield.class == RegMMX |
7487 | || i.op[source].regs->reg_type.bitfield.class == RegMMX) | |
b4a3a7b4 | 7488 | i.has_regmmx = TRUE; |
3528c362 JB |
7489 | else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD |
7490 | || i.op[source].regs->reg_type.bitfield.class == RegSIMD) | |
b4a3a7b4 L |
7491 | { |
7492 | if (i.types[dest].bitfield.zmmword | |
7493 | || i.types[source].bitfield.zmmword) | |
7494 | i.has_regzmm = TRUE; | |
7495 | else if (i.types[dest].bitfield.ymmword | |
7496 | || i.types[source].bitfield.ymmword) | |
7497 | i.has_regymm = TRUE; | |
7498 | else | |
7499 | i.has_regxmm = TRUE; | |
7500 | } | |
29b0f896 | 7501 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7502 | i.rex |= REX_R; |
43234a1e L |
7503 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7504 | i.vrex |= REX_R; | |
29b0f896 | 7505 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7506 | i.rex |= REX_B; |
43234a1e L |
7507 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7508 | i.vrex |= REX_B; | |
29b0f896 AM |
7509 | } |
7510 | else | |
7511 | { | |
7512 | i.rm.reg = i.op[source].regs->reg_num; | |
7513 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7514 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7515 | i.rex |= REX_B; |
43234a1e L |
7516 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7517 | i.vrex |= REX_B; | |
29b0f896 | 7518 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7519 | i.rex |= REX_R; |
43234a1e L |
7520 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7521 | i.vrex |= REX_R; | |
29b0f896 | 7522 | } |
e0c7f900 | 7523 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7524 | { |
4a5c67ed | 7525 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 7526 | abort (); |
e0c7f900 | 7527 | i.rex &= ~REX_R; |
c4a530c5 JB |
7528 | add_prefix (LOCK_PREFIX_OPCODE); |
7529 | } | |
29b0f896 AM |
7530 | } |
7531 | else | |
7532 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7533 | unsigned int mem; |
7534 | ||
29b0f896 AM |
7535 | if (i.mem_operands) |
7536 | { | |
7537 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7538 | unsigned int op; |
4eed87de | 7539 | |
7ab9ffdd | 7540 | for (op = 0; op < i.operands; op++) |
8dc0818e | 7541 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 7542 | break; |
7ab9ffdd | 7543 | gas_assert (op < i.operands); |
29b0f896 | 7544 | |
6c30d220 L |
7545 | if (i.tm.opcode_modifier.vecsib) |
7546 | { | |
e968fc9b | 7547 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7548 | abort (); |
7549 | ||
7550 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7551 | if (!i.base_reg) | |
7552 | { | |
7553 | i.sib.base = NO_BASE_REGISTER; | |
7554 | i.sib.scale = i.log2_scale_factor; | |
7555 | i.types[op].bitfield.disp8 = 0; | |
7556 | i.types[op].bitfield.disp16 = 0; | |
7557 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7558 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7559 | { |
7560 | /* Must be 32 bit */ | |
7561 | i.types[op].bitfield.disp32 = 1; | |
7562 | i.types[op].bitfield.disp32s = 0; | |
7563 | } | |
7564 | else | |
7565 | { | |
7566 | i.types[op].bitfield.disp32 = 0; | |
7567 | i.types[op].bitfield.disp32s = 1; | |
7568 | } | |
7569 | } | |
7570 | i.sib.index = i.index_reg->reg_num; | |
7571 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7572 | i.rex |= REX_X; | |
43234a1e L |
7573 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7574 | i.vrex |= REX_X; | |
6c30d220 L |
7575 | } |
7576 | ||
29b0f896 AM |
7577 | default_seg = &ds; |
7578 | ||
7579 | if (i.base_reg == 0) | |
7580 | { | |
7581 | i.rm.mode = 0; | |
7582 | if (!i.disp_operands) | |
9bb129e8 | 7583 | fake_zero_displacement = 1; |
29b0f896 AM |
7584 | if (i.index_reg == 0) |
7585 | { | |
73053c1f JB |
7586 | i386_operand_type newdisp; |
7587 | ||
6c30d220 | 7588 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7589 | /* Operand is just <disp> */ |
20f0a1fc | 7590 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7591 | { |
7592 | /* 64bit mode overwrites the 32bit absolute | |
7593 | addressing by RIP relative addressing and | |
7594 | absolute addressing is encoded by one of the | |
7595 | redundant SIB forms. */ | |
7596 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7597 | i.sib.base = NO_BASE_REGISTER; | |
7598 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7599 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7600 | } |
fc225355 L |
7601 | else if ((flag_code == CODE_16BIT) |
7602 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7603 | { |
7604 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7605 | newdisp = disp16; |
20f0a1fc NC |
7606 | } |
7607 | else | |
7608 | { | |
7609 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7610 | newdisp = disp32; |
29b0f896 | 7611 | } |
73053c1f JB |
7612 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7613 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7614 | } |
6c30d220 | 7615 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7616 | { |
6c30d220 | 7617 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7618 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7619 | i.sib.index = NO_INDEX_REGISTER; |
7620 | else | |
7621 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7622 | i.sib.base = NO_BASE_REGISTER; |
7623 | i.sib.scale = i.log2_scale_factor; | |
7624 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7625 | i.types[op].bitfield.disp8 = 0; |
7626 | i.types[op].bitfield.disp16 = 0; | |
7627 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7628 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7629 | { |
7630 | /* Must be 32 bit */ | |
7631 | i.types[op].bitfield.disp32 = 1; | |
7632 | i.types[op].bitfield.disp32s = 0; | |
7633 | } | |
29b0f896 | 7634 | else |
40fb9820 L |
7635 | { |
7636 | i.types[op].bitfield.disp32 = 0; | |
7637 | i.types[op].bitfield.disp32s = 1; | |
7638 | } | |
29b0f896 | 7639 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7640 | i.rex |= REX_X; |
29b0f896 AM |
7641 | } |
7642 | } | |
7643 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7644 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7645 | { |
6c30d220 | 7646 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7647 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7648 | i.types[op].bitfield.disp8 = 0; |
7649 | i.types[op].bitfield.disp16 = 0; | |
7650 | i.types[op].bitfield.disp32 = 0; | |
7651 | i.types[op].bitfield.disp32s = 1; | |
7652 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7653 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7654 | if (! i.disp_operands) |
7655 | fake_zero_displacement = 1; | |
29b0f896 | 7656 | } |
dc821c5f | 7657 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7658 | { |
6c30d220 | 7659 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7660 | switch (i.base_reg->reg_num) |
7661 | { | |
7662 | case 3: /* (%bx) */ | |
7663 | if (i.index_reg == 0) | |
7664 | i.rm.regmem = 7; | |
7665 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7666 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7667 | break; | |
7668 | case 5: /* (%bp) */ | |
7669 | default_seg = &ss; | |
7670 | if (i.index_reg == 0) | |
7671 | { | |
7672 | i.rm.regmem = 6; | |
40fb9820 | 7673 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7674 | { |
7675 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7676 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7677 | fake_zero_displacement = 1; |
29b0f896 AM |
7678 | } |
7679 | } | |
7680 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7681 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7682 | break; | |
7683 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7684 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7685 | } | |
7686 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7687 | } | |
7688 | else /* i.base_reg and 32/64 bit mode */ | |
7689 | { | |
7690 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7691 | && operand_type_check (i.types[op], disp)) |
7692 | { | |
73053c1f JB |
7693 | i.types[op].bitfield.disp16 = 0; |
7694 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7695 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7696 | { |
7697 | i.types[op].bitfield.disp32 = 0; | |
7698 | i.types[op].bitfield.disp32s = 1; | |
7699 | } | |
40fb9820 | 7700 | else |
73053c1f JB |
7701 | { |
7702 | i.types[op].bitfield.disp32 = 1; | |
7703 | i.types[op].bitfield.disp32s = 0; | |
7704 | } | |
40fb9820 | 7705 | } |
20f0a1fc | 7706 | |
6c30d220 L |
7707 | if (!i.tm.opcode_modifier.vecsib) |
7708 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7709 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7710 | i.rex |= REX_B; |
29b0f896 AM |
7711 | i.sib.base = i.base_reg->reg_num; |
7712 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7713 | complications. */ | |
848930b2 JB |
7714 | if (!(i.base_reg->reg_flags & RegRex) |
7715 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7716 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7717 | default_seg = &ss; |
848930b2 | 7718 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7719 | { |
848930b2 | 7720 | fake_zero_displacement = 1; |
b5014f7a | 7721 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7722 | } |
7723 | i.sib.scale = i.log2_scale_factor; | |
7724 | if (i.index_reg == 0) | |
7725 | { | |
6c30d220 | 7726 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7727 | /* <disp>(%esp) becomes two byte modrm with no index |
7728 | register. We've already stored the code for esp | |
7729 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7730 | Any base register besides %esp will not use the | |
7731 | extra modrm byte. */ | |
7732 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7733 | } |
6c30d220 | 7734 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7735 | { |
e968fc9b | 7736 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7737 | i.sib.index = NO_INDEX_REGISTER; |
7738 | else | |
7739 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7740 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7741 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7742 | i.rex |= REX_X; |
29b0f896 | 7743 | } |
67a4f2b7 AO |
7744 | |
7745 | if (i.disp_operands | |
7746 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7747 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7748 | i.rm.mode = 0; | |
7749 | else | |
a501d77e L |
7750 | { |
7751 | if (!fake_zero_displacement | |
7752 | && !i.disp_operands | |
7753 | && i.disp_encoding) | |
7754 | { | |
7755 | fake_zero_displacement = 1; | |
7756 | if (i.disp_encoding == disp_encoding_8bit) | |
7757 | i.types[op].bitfield.disp8 = 1; | |
7758 | else | |
7759 | i.types[op].bitfield.disp32 = 1; | |
7760 | } | |
7761 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7762 | } | |
29b0f896 | 7763 | } |
252b5132 | 7764 | |
29b0f896 AM |
7765 | if (fake_zero_displacement) |
7766 | { | |
7767 | /* Fakes a zero displacement assuming that i.types[op] | |
7768 | holds the correct displacement size. */ | |
7769 | expressionS *exp; | |
7770 | ||
9c2799c2 | 7771 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7772 | exp = &disp_expressions[i.disp_operands++]; |
7773 | i.op[op].disps = exp; | |
7774 | exp->X_op = O_constant; | |
7775 | exp->X_add_number = 0; | |
7776 | exp->X_add_symbol = (symbolS *) 0; | |
7777 | exp->X_op_symbol = (symbolS *) 0; | |
7778 | } | |
c0f3af97 L |
7779 | |
7780 | mem = op; | |
29b0f896 | 7781 | } |
c0f3af97 L |
7782 | else |
7783 | mem = ~0; | |
252b5132 | 7784 | |
8c43a48b | 7785 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7786 | { |
7787 | if (operand_type_check (i.types[0], imm)) | |
7788 | i.vex.register_specifier = NULL; | |
7789 | else | |
7790 | { | |
7791 | /* VEX.vvvv encodes one of the sources when the first | |
7792 | operand is not an immediate. */ | |
1ef99a7b | 7793 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7794 | i.vex.register_specifier = i.op[0].regs; |
7795 | else | |
7796 | i.vex.register_specifier = i.op[1].regs; | |
7797 | } | |
7798 | ||
7799 | /* Destination is a XMM register encoded in the ModRM.reg | |
7800 | and VEX.R bit. */ | |
7801 | i.rm.reg = i.op[2].regs->reg_num; | |
7802 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7803 | i.rex |= REX_R; | |
7804 | ||
7805 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7806 | if (!i.mem_operands) | |
7807 | { | |
7808 | i.rm.mode = 3; | |
7809 | ||
1ef99a7b | 7810 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7811 | i.rm.regmem = i.op[1].regs->reg_num; |
7812 | else | |
7813 | i.rm.regmem = i.op[0].regs->reg_num; | |
7814 | ||
7815 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7816 | i.rex |= REX_B; | |
7817 | } | |
7818 | } | |
2426c15f | 7819 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7820 | { |
7821 | i.vex.register_specifier = i.op[2].regs; | |
7822 | if (!i.mem_operands) | |
7823 | { | |
7824 | i.rm.mode = 3; | |
7825 | i.rm.regmem = i.op[1].regs->reg_num; | |
7826 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7827 | i.rex |= REX_B; | |
7828 | } | |
7829 | } | |
29b0f896 AM |
7830 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7831 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7832 | careful to make sure that segment/control/debug/test/MMX | |
7833 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7834 | else if (i.reg_operands) |
29b0f896 | 7835 | { |
99018f42 | 7836 | unsigned int op; |
7ab9ffdd L |
7837 | unsigned int vex_reg = ~0; |
7838 | ||
7839 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 | 7840 | { |
bab6aec1 | 7841 | if (i.types[op].bitfield.class == Reg |
f74a6307 JB |
7842 | || i.types[op].bitfield.class == RegBND |
7843 | || i.types[op].bitfield.class == RegMask | |
00cee14f | 7844 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
7845 | || i.types[op].bitfield.class == RegCR |
7846 | || i.types[op].bitfield.class == RegDR | |
7847 | || i.types[op].bitfield.class == RegTR) | |
b4a3a7b4 | 7848 | break; |
3528c362 | 7849 | if (i.types[op].bitfield.class == RegSIMD) |
b4a3a7b4 L |
7850 | { |
7851 | if (i.types[op].bitfield.zmmword) | |
7852 | i.has_regzmm = TRUE; | |
7853 | else if (i.types[op].bitfield.ymmword) | |
7854 | i.has_regymm = TRUE; | |
7855 | else | |
7856 | i.has_regxmm = TRUE; | |
7857 | break; | |
7858 | } | |
3528c362 | 7859 | if (i.types[op].bitfield.class == RegMMX) |
b4a3a7b4 L |
7860 | { |
7861 | i.has_regmmx = TRUE; | |
7862 | break; | |
7863 | } | |
7864 | } | |
c0209578 | 7865 | |
7ab9ffdd L |
7866 | if (vex_3_sources) |
7867 | op = dest; | |
2426c15f | 7868 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7869 | { |
7870 | /* For instructions with VexNDS, the register-only | |
7871 | source operand is encoded in VEX prefix. */ | |
7872 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7873 | |
7ab9ffdd | 7874 | if (op > mem) |
c0f3af97 | 7875 | { |
7ab9ffdd L |
7876 | vex_reg = op++; |
7877 | gas_assert (op < i.operands); | |
c0f3af97 L |
7878 | } |
7879 | else | |
c0f3af97 | 7880 | { |
f12dc422 L |
7881 | /* Check register-only source operand when two source |
7882 | operands are swapped. */ | |
7883 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7884 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7885 | { | |
7886 | vex_reg = op; | |
7887 | op += 2; | |
7888 | gas_assert (mem == (vex_reg + 1) | |
7889 | && op < i.operands); | |
7890 | } | |
7891 | else | |
7892 | { | |
7893 | vex_reg = op + 1; | |
7894 | gas_assert (vex_reg < i.operands); | |
7895 | } | |
c0f3af97 | 7896 | } |
7ab9ffdd | 7897 | } |
2426c15f | 7898 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7899 | { |
f12dc422 | 7900 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7901 | is encoded in VEX prefix. */ |
f12dc422 L |
7902 | if (i.mem_operands == 0) |
7903 | { | |
7904 | /* There is no memory operand. */ | |
7905 | gas_assert ((op + 2) == i.operands); | |
7906 | vex_reg = op + 1; | |
7907 | } | |
7908 | else | |
8d63c93e | 7909 | { |
ed438a93 JB |
7910 | /* There are only 2 non-immediate operands. */ |
7911 | gas_assert (op < i.imm_operands + 2 | |
7912 | && i.operands == i.imm_operands + 2); | |
7913 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7914 | } |
7ab9ffdd L |
7915 | } |
7916 | else | |
7917 | gas_assert (op < i.operands); | |
99018f42 | 7918 | |
7ab9ffdd L |
7919 | if (vex_reg != (unsigned int) ~0) |
7920 | { | |
f12dc422 | 7921 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7922 | |
bab6aec1 | 7923 | if ((type->bitfield.class != Reg |
dc821c5f | 7924 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 7925 | && type->bitfield.class != RegSIMD |
43234a1e | 7926 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7927 | abort (); |
f88c9eb0 | 7928 | |
7ab9ffdd L |
7929 | i.vex.register_specifier = i.op[vex_reg].regs; |
7930 | } | |
7931 | ||
1b9f0c97 L |
7932 | /* Don't set OP operand twice. */ |
7933 | if (vex_reg != op) | |
7ab9ffdd | 7934 | { |
1b9f0c97 L |
7935 | /* If there is an extension opcode to put here, the |
7936 | register number must be put into the regmem field. */ | |
7937 | if (i.tm.extension_opcode != None) | |
7938 | { | |
7939 | i.rm.regmem = i.op[op].regs->reg_num; | |
7940 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7941 | i.rex |= REX_B; | |
43234a1e L |
7942 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7943 | i.vrex |= REX_B; | |
1b9f0c97 L |
7944 | } |
7945 | else | |
7946 | { | |
7947 | i.rm.reg = i.op[op].regs->reg_num; | |
7948 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7949 | i.rex |= REX_R; | |
43234a1e L |
7950 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7951 | i.vrex |= REX_R; | |
1b9f0c97 | 7952 | } |
7ab9ffdd | 7953 | } |
252b5132 | 7954 | |
29b0f896 AM |
7955 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7956 | must set it to 3 to indicate this is a register operand | |
7957 | in the regmem field. */ | |
7958 | if (!i.mem_operands) | |
7959 | i.rm.mode = 3; | |
7960 | } | |
252b5132 | 7961 | |
29b0f896 | 7962 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7963 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7964 | i.rm.reg = i.tm.extension_opcode; |
7965 | } | |
7966 | return default_seg; | |
7967 | } | |
252b5132 | 7968 | |
376cd056 JB |
7969 | static unsigned int |
7970 | flip_code16 (unsigned int code16) | |
7971 | { | |
7972 | gas_assert (i.tm.operands == 1); | |
7973 | ||
7974 | return !(i.prefix[REX_PREFIX] & REX_W) | |
7975 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
7976 | || i.tm.operand_types[0].bitfield.disp32s | |
7977 | : i.tm.operand_types[0].bitfield.disp16) | |
7978 | ? CODE16 : 0; | |
7979 | } | |
7980 | ||
29b0f896 | 7981 | static void |
e3bb37b5 | 7982 | output_branch (void) |
29b0f896 AM |
7983 | { |
7984 | char *p; | |
f8a5c266 | 7985 | int size; |
29b0f896 AM |
7986 | int code16; |
7987 | int prefix; | |
7988 | relax_substateT subtype; | |
7989 | symbolS *sym; | |
7990 | offsetT off; | |
7991 | ||
f8a5c266 | 7992 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7993 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7994 | |
7995 | prefix = 0; | |
7996 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7997 | { |
29b0f896 AM |
7998 | prefix = 1; |
7999 | i.prefixes -= 1; | |
376cd056 | 8000 | code16 ^= flip_code16(code16); |
252b5132 | 8001 | } |
29b0f896 AM |
8002 | /* Pentium4 branch hints. */ |
8003 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8004 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 8005 | { |
29b0f896 AM |
8006 | prefix++; |
8007 | i.prefixes--; | |
8008 | } | |
8009 | if (i.prefix[REX_PREFIX] != 0) | |
8010 | { | |
8011 | prefix++; | |
8012 | i.prefixes--; | |
2f66722d AM |
8013 | } |
8014 | ||
7e8b059b L |
8015 | /* BND prefixed jump. */ |
8016 | if (i.prefix[BND_PREFIX] != 0) | |
8017 | { | |
6cb0a70e JB |
8018 | prefix++; |
8019 | i.prefixes--; | |
7e8b059b L |
8020 | } |
8021 | ||
f2810fe0 JB |
8022 | if (i.prefixes != 0) |
8023 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
29b0f896 AM |
8024 | |
8025 | /* It's always a symbol; End frag & setup for relax. | |
8026 | Make sure there is enough room in this frag for the largest | |
8027 | instruction we may generate in md_convert_frag. This is 2 | |
8028 | bytes for the opcode and room for the prefix and largest | |
8029 | displacement. */ | |
8030 | frag_grow (prefix + 2 + 4); | |
8031 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
8032 | p = frag_more (prefix + 1); | |
8033 | if (i.prefix[DATA_PREFIX] != 0) | |
8034 | *p++ = DATA_PREFIX_OPCODE; | |
8035 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
8036 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
8037 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
8038 | if (i.prefix[BND_PREFIX] != 0) |
8039 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
8040 | if (i.prefix[REX_PREFIX] != 0) |
8041 | *p++ = i.prefix[REX_PREFIX]; | |
8042 | *p = i.tm.base_opcode; | |
8043 | ||
8044 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 8045 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 8046 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 8047 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 8048 | else |
f8a5c266 | 8049 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 8050 | subtype |= code16; |
3e73aa7c | 8051 | |
29b0f896 AM |
8052 | sym = i.op[0].disps->X_add_symbol; |
8053 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 8054 | |
29b0f896 AM |
8055 | if (i.op[0].disps->X_op != O_constant |
8056 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 8057 | { |
29b0f896 AM |
8058 | /* Handle complex expressions. */ |
8059 | sym = make_expr_symbol (i.op[0].disps); | |
8060 | off = 0; | |
8061 | } | |
3e73aa7c | 8062 | |
29b0f896 AM |
8063 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
8064 | Pass reloc in fr_var. */ | |
d258b828 | 8065 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 8066 | } |
3e73aa7c | 8067 | |
bd7ab16b L |
8068 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8069 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
8070 | symbol S. */ | |
8071 | ||
8072 | static bfd_boolean | |
8073 | need_plt32_p (symbolS *s) | |
8074 | { | |
8075 | /* PLT32 relocation is ELF only. */ | |
8076 | if (!IS_ELF) | |
8077 | return FALSE; | |
8078 | ||
a5def729 RO |
8079 | #ifdef TE_SOLARIS |
8080 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
8081 | krtld support it. */ | |
8082 | return FALSE; | |
8083 | #endif | |
8084 | ||
bd7ab16b L |
8085 | /* Since there is no need to prepare for PLT branch on x86-64, we |
8086 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
8087 | be used as a marker for 32-bit PC-relative branches. */ | |
8088 | if (!object_64bit) | |
8089 | return FALSE; | |
8090 | ||
8091 | /* Weak or undefined symbol need PLT32 relocation. */ | |
8092 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
8093 | return TRUE; | |
8094 | ||
8095 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
8096 | if (! S_IS_EXTERNAL (s)) | |
8097 | return FALSE; | |
8098 | ||
8099 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
8100 | non-default visibilities are treated as normal global symbol | |
8101 | so that PLT32 relocation can be used as a marker for 32-bit | |
8102 | PC-relative branches. It is useful for linker relaxation. */ | |
8103 | return TRUE; | |
8104 | } | |
8105 | #endif | |
8106 | ||
29b0f896 | 8107 | static void |
e3bb37b5 | 8108 | output_jump (void) |
29b0f896 AM |
8109 | { |
8110 | char *p; | |
8111 | int size; | |
3e02c1cc | 8112 | fixS *fixP; |
bd7ab16b | 8113 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 8114 | |
0cfa3eb3 | 8115 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
8116 | { |
8117 | /* This is a loop or jecxz type instruction. */ | |
8118 | size = 1; | |
8119 | if (i.prefix[ADDR_PREFIX] != 0) | |
8120 | { | |
8121 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
8122 | i.prefixes -= 1; | |
8123 | } | |
8124 | /* Pentium4 branch hints. */ | |
8125 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8126 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
8127 | { | |
8128 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
8129 | i.prefixes--; | |
3e73aa7c JH |
8130 | } |
8131 | } | |
29b0f896 AM |
8132 | else |
8133 | { | |
8134 | int code16; | |
3e73aa7c | 8135 | |
29b0f896 AM |
8136 | code16 = 0; |
8137 | if (flag_code == CODE_16BIT) | |
8138 | code16 = CODE16; | |
3e73aa7c | 8139 | |
29b0f896 AM |
8140 | if (i.prefix[DATA_PREFIX] != 0) |
8141 | { | |
8142 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
8143 | i.prefixes -= 1; | |
376cd056 | 8144 | code16 ^= flip_code16(code16); |
29b0f896 | 8145 | } |
252b5132 | 8146 | |
29b0f896 AM |
8147 | size = 4; |
8148 | if (code16) | |
8149 | size = 2; | |
8150 | } | |
9fcc94b6 | 8151 | |
6cb0a70e JB |
8152 | /* BND prefixed jump. */ |
8153 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 8154 | { |
6cb0a70e | 8155 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); |
29b0f896 AM |
8156 | i.prefixes -= 1; |
8157 | } | |
252b5132 | 8158 | |
6cb0a70e | 8159 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 8160 | { |
6cb0a70e | 8161 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); |
7e8b059b L |
8162 | i.prefixes -= 1; |
8163 | } | |
8164 | ||
f2810fe0 JB |
8165 | if (i.prefixes != 0) |
8166 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
e0890092 | 8167 | |
42164a71 L |
8168 | p = frag_more (i.tm.opcode_length + size); |
8169 | switch (i.tm.opcode_length) | |
8170 | { | |
8171 | case 2: | |
8172 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8173 | /* Fall through. */ |
42164a71 L |
8174 | case 1: |
8175 | *p++ = i.tm.base_opcode; | |
8176 | break; | |
8177 | default: | |
8178 | abort (); | |
8179 | } | |
e0890092 | 8180 | |
bd7ab16b L |
8181 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8182 | if (size == 4 | |
8183 | && jump_reloc == NO_RELOC | |
8184 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
8185 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8186 | #endif | |
8187 | ||
8188 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8189 | ||
3e02c1cc | 8190 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8191 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
8192 | |
8193 | /* All jumps handled here are signed, but don't use a signed limit | |
8194 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
8195 | 4G and 64k respectively. */ | |
8196 | if (size == 1) | |
8197 | fixP->fx_signed = 1; | |
29b0f896 | 8198 | } |
e0890092 | 8199 | |
29b0f896 | 8200 | static void |
e3bb37b5 | 8201 | output_interseg_jump (void) |
29b0f896 AM |
8202 | { |
8203 | char *p; | |
8204 | int size; | |
8205 | int prefix; | |
8206 | int code16; | |
252b5132 | 8207 | |
29b0f896 AM |
8208 | code16 = 0; |
8209 | if (flag_code == CODE_16BIT) | |
8210 | code16 = CODE16; | |
a217f122 | 8211 | |
29b0f896 AM |
8212 | prefix = 0; |
8213 | if (i.prefix[DATA_PREFIX] != 0) | |
8214 | { | |
8215 | prefix = 1; | |
8216 | i.prefixes -= 1; | |
8217 | code16 ^= CODE16; | |
8218 | } | |
6cb0a70e JB |
8219 | |
8220 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 8221 | |
29b0f896 AM |
8222 | size = 4; |
8223 | if (code16) | |
8224 | size = 2; | |
252b5132 | 8225 | |
f2810fe0 JB |
8226 | if (i.prefixes != 0) |
8227 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
252b5132 | 8228 | |
29b0f896 AM |
8229 | /* 1 opcode; 2 segment; offset */ |
8230 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8231 | |
29b0f896 AM |
8232 | if (i.prefix[DATA_PREFIX] != 0) |
8233 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 8234 | |
29b0f896 AM |
8235 | if (i.prefix[REX_PREFIX] != 0) |
8236 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 8237 | |
29b0f896 AM |
8238 | *p++ = i.tm.base_opcode; |
8239 | if (i.op[1].imms->X_op == O_constant) | |
8240 | { | |
8241 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 8242 | |
29b0f896 AM |
8243 | if (size == 2 |
8244 | && !fits_in_unsigned_word (n) | |
8245 | && !fits_in_signed_word (n)) | |
8246 | { | |
8247 | as_bad (_("16-bit jump out of range")); | |
8248 | return; | |
8249 | } | |
8250 | md_number_to_chars (p, n, size); | |
8251 | } | |
8252 | else | |
8253 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 8254 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
8255 | if (i.op[0].imms->X_op != O_constant) |
8256 | as_bad (_("can't handle non absolute segment in `%s'"), | |
8257 | i.tm.name); | |
8258 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
8259 | } | |
a217f122 | 8260 | |
b4a3a7b4 L |
8261 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8262 | void | |
8263 | x86_cleanup (void) | |
8264 | { | |
8265 | char *p; | |
8266 | asection *seg = now_seg; | |
8267 | subsegT subseg = now_subseg; | |
8268 | asection *sec; | |
8269 | unsigned int alignment, align_size_1; | |
8270 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
8271 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
8272 | unsigned int padding; | |
8273 | ||
8274 | if (!IS_ELF || !x86_used_note) | |
8275 | return; | |
8276 | ||
b4a3a7b4 L |
8277 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
8278 | ||
8279 | /* The .note.gnu.property section layout: | |
8280 | ||
8281 | Field Length Contents | |
8282 | ---- ---- ---- | |
8283 | n_namsz 4 4 | |
8284 | n_descsz 4 The note descriptor size | |
8285 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
8286 | n_name 4 "GNU" | |
8287 | n_desc n_descsz The program property array | |
8288 | .... .... .... | |
8289 | */ | |
8290 | ||
8291 | /* Create the .note.gnu.property section. */ | |
8292 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 8293 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
8294 | (SEC_ALLOC |
8295 | | SEC_LOAD | |
8296 | | SEC_DATA | |
8297 | | SEC_HAS_CONTENTS | |
8298 | | SEC_READONLY)); | |
8299 | ||
8300 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8301 | { | |
8302 | align_size_1 = 7; | |
8303 | alignment = 3; | |
8304 | } | |
8305 | else | |
8306 | { | |
8307 | align_size_1 = 3; | |
8308 | alignment = 2; | |
8309 | } | |
8310 | ||
fd361982 | 8311 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
8312 | elf_section_type (sec) = SHT_NOTE; |
8313 | ||
8314 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8315 | + 4-byte data */ | |
8316 | isa_1_descsz_raw = 4 + 4 + 4; | |
8317 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8318 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8319 | ||
8320 | feature_2_descsz_raw = isa_1_descsz; | |
8321 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8322 | + 4-byte data */ | |
8323 | feature_2_descsz_raw += 4 + 4 + 4; | |
8324 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8325 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8326 | & ~align_size_1); | |
8327 | ||
8328 | descsz = feature_2_descsz; | |
8329 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8330 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8331 | ||
8332 | /* Write n_namsz. */ | |
8333 | md_number_to_chars (p, (valueT) 4, 4); | |
8334 | ||
8335 | /* Write n_descsz. */ | |
8336 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8337 | ||
8338 | /* Write n_type. */ | |
8339 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8340 | ||
8341 | /* Write n_name. */ | |
8342 | memcpy (p + 4 * 3, "GNU", 4); | |
8343 | ||
8344 | /* Write 4-byte type. */ | |
8345 | md_number_to_chars (p + 4 * 4, | |
8346 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8347 | ||
8348 | /* Write 4-byte data size. */ | |
8349 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8350 | ||
8351 | /* Write 4-byte data. */ | |
8352 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8353 | ||
8354 | /* Zero out paddings. */ | |
8355 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8356 | if (padding) | |
8357 | memset (p + 4 * 7, 0, padding); | |
8358 | ||
8359 | /* Write 4-byte type. */ | |
8360 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8361 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8362 | ||
8363 | /* Write 4-byte data size. */ | |
8364 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8365 | ||
8366 | /* Write 4-byte data. */ | |
8367 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8368 | (valueT) x86_feature_2_used, 4); | |
8369 | ||
8370 | /* Zero out paddings. */ | |
8371 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8372 | if (padding) | |
8373 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8374 | ||
8375 | /* We probably can't restore the current segment, for there likely | |
8376 | isn't one yet... */ | |
8377 | if (seg && subseg) | |
8378 | subseg_set (seg, subseg); | |
8379 | } | |
8380 | #endif | |
8381 | ||
9c33702b JB |
8382 | static unsigned int |
8383 | encoding_length (const fragS *start_frag, offsetT start_off, | |
8384 | const char *frag_now_ptr) | |
8385 | { | |
8386 | unsigned int len = 0; | |
8387 | ||
8388 | if (start_frag != frag_now) | |
8389 | { | |
8390 | const fragS *fr = start_frag; | |
8391 | ||
8392 | do { | |
8393 | len += fr->fr_fix; | |
8394 | fr = fr->fr_next; | |
8395 | } while (fr && fr != frag_now); | |
8396 | } | |
8397 | ||
8398 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
8399 | } | |
8400 | ||
e379e5f3 | 8401 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
8402 | be macro-fused with conditional jumps. |
8403 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
8404 | or is one of the following format: | |
8405 | ||
8406 | cmp m, imm | |
8407 | add m, imm | |
8408 | sub m, imm | |
8409 | test m, imm | |
8410 | and m, imm | |
8411 | inc m | |
8412 | dec m | |
8413 | ||
8414 | it is unfusible. */ | |
e379e5f3 L |
8415 | |
8416 | static int | |
79d72f45 | 8417 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
8418 | { |
8419 | /* No RIP address. */ | |
8420 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
8421 | return 0; | |
8422 | ||
8423 | /* No VEX/EVEX encoding. */ | |
8424 | if (is_any_vex_encoding (&i.tm)) | |
8425 | return 0; | |
8426 | ||
79d72f45 HL |
8427 | /* add, sub without add/sub m, imm. */ |
8428 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
8429 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
8430 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 8431 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 8432 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
8433 | { |
8434 | *mf_cmp_p = mf_cmp_alu_cmp; | |
8435 | return !(i.mem_operands && i.imm_operands); | |
8436 | } | |
e379e5f3 | 8437 | |
79d72f45 HL |
8438 | /* and without and m, imm. */ |
8439 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
8440 | || ((i.tm.base_opcode | 3) == 0x83 | |
8441 | && i.tm.extension_opcode == 0x4)) | |
8442 | { | |
8443 | *mf_cmp_p = mf_cmp_test_and; | |
8444 | return !(i.mem_operands && i.imm_operands); | |
8445 | } | |
8446 | ||
8447 | /* test without test m imm. */ | |
e379e5f3 L |
8448 | if ((i.tm.base_opcode | 1) == 0x85 |
8449 | || (i.tm.base_opcode | 1) == 0xa9 | |
8450 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
8451 | && i.tm.extension_opcode == 0)) |
8452 | { | |
8453 | *mf_cmp_p = mf_cmp_test_and; | |
8454 | return !(i.mem_operands && i.imm_operands); | |
8455 | } | |
8456 | ||
8457 | /* cmp without cmp m, imm. */ | |
8458 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
8459 | || ((i.tm.base_opcode | 3) == 0x83 |
8460 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
8461 | { |
8462 | *mf_cmp_p = mf_cmp_alu_cmp; | |
8463 | return !(i.mem_operands && i.imm_operands); | |
8464 | } | |
e379e5f3 | 8465 | |
79d72f45 | 8466 | /* inc, dec without inc/dec m. */ |
e379e5f3 L |
8467 | if ((i.tm.cpu_flags.bitfield.cpuno64 |
8468 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
8469 | || ((i.tm.base_opcode | 1) == 0xff | |
8470 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
8471 | { |
8472 | *mf_cmp_p = mf_cmp_incdec; | |
8473 | return !i.mem_operands; | |
8474 | } | |
e379e5f3 L |
8475 | |
8476 | return 0; | |
8477 | } | |
8478 | ||
8479 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
8480 | ||
8481 | static int | |
79d72f45 | 8482 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
8483 | { |
8484 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8485 | if (!align_branch_power | |
8486 | || now_seg == absolute_section | |
8487 | || !cpu_arch_flags.bitfield.cpui386 | |
8488 | || !(align_branch & align_branch_fused_bit)) | |
8489 | return 0; | |
8490 | ||
79d72f45 | 8491 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 L |
8492 | { |
8493 | if (last_insn.kind == last_insn_other | |
8494 | || last_insn.seg != now_seg) | |
8495 | return 1; | |
8496 | if (flag_debug) | |
8497 | as_warn_where (last_insn.file, last_insn.line, | |
8498 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8499 | last_insn.name, i.tm.name); | |
8500 | } | |
8501 | ||
8502 | return 0; | |
8503 | } | |
8504 | ||
8505 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
8506 | ||
8507 | static int | |
8508 | add_branch_prefix_frag_p (void) | |
8509 | { | |
8510 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
8511 | to PadLock instructions since they include prefixes in opcode. */ | |
8512 | if (!align_branch_power | |
8513 | || !align_branch_prefix_size | |
8514 | || now_seg == absolute_section | |
8515 | || i.tm.cpu_flags.bitfield.cpupadlock | |
8516 | || !cpu_arch_flags.bitfield.cpui386) | |
8517 | return 0; | |
8518 | ||
8519 | /* Don't add prefix if it is a prefix or there is no operand in case | |
8520 | that segment prefix is special. */ | |
8521 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
8522 | return 0; | |
8523 | ||
8524 | if (last_insn.kind == last_insn_other | |
8525 | || last_insn.seg != now_seg) | |
8526 | return 1; | |
8527 | ||
8528 | if (flag_debug) | |
8529 | as_warn_where (last_insn.file, last_insn.line, | |
8530 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8531 | last_insn.name, i.tm.name); | |
8532 | ||
8533 | return 0; | |
8534 | } | |
8535 | ||
8536 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
8537 | ||
8538 | static int | |
79d72f45 HL |
8539 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
8540 | enum mf_jcc_kind *mf_jcc_p) | |
e379e5f3 L |
8541 | { |
8542 | int add_padding; | |
8543 | ||
8544 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8545 | if (!align_branch_power | |
8546 | || now_seg == absolute_section | |
8547 | || !cpu_arch_flags.bitfield.cpui386) | |
8548 | return 0; | |
8549 | ||
8550 | add_padding = 0; | |
8551 | ||
8552 | /* Check for jcc and direct jmp. */ | |
8553 | if (i.tm.opcode_modifier.jump == JUMP) | |
8554 | { | |
8555 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
8556 | { | |
8557 | *branch_p = align_branch_jmp; | |
8558 | add_padding = align_branch & align_branch_jmp_bit; | |
8559 | } | |
8560 | else | |
8561 | { | |
79d72f45 HL |
8562 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
8563 | igore the lowest bit. */ | |
8564 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
8565 | *branch_p = align_branch_jcc; |
8566 | if ((align_branch & align_branch_jcc_bit)) | |
8567 | add_padding = 1; | |
8568 | } | |
8569 | } | |
8570 | else if (is_any_vex_encoding (&i.tm)) | |
8571 | return 0; | |
8572 | else if ((i.tm.base_opcode | 1) == 0xc3) | |
8573 | { | |
8574 | /* Near ret. */ | |
8575 | *branch_p = align_branch_ret; | |
8576 | if ((align_branch & align_branch_ret_bit)) | |
8577 | add_padding = 1; | |
8578 | } | |
8579 | else | |
8580 | { | |
8581 | /* Check for indirect jmp, direct and indirect calls. */ | |
8582 | if (i.tm.base_opcode == 0xe8) | |
8583 | { | |
8584 | /* Direct call. */ | |
8585 | *branch_p = align_branch_call; | |
8586 | if ((align_branch & align_branch_call_bit)) | |
8587 | add_padding = 1; | |
8588 | } | |
8589 | else if (i.tm.base_opcode == 0xff | |
8590 | && (i.tm.extension_opcode == 2 | |
8591 | || i.tm.extension_opcode == 4)) | |
8592 | { | |
8593 | /* Indirect call and jmp. */ | |
8594 | *branch_p = align_branch_indirect; | |
8595 | if ((align_branch & align_branch_indirect_bit)) | |
8596 | add_padding = 1; | |
8597 | } | |
8598 | ||
8599 | if (add_padding | |
8600 | && i.disp_operands | |
8601 | && tls_get_addr | |
8602 | && (i.op[0].disps->X_op == O_symbol | |
8603 | || (i.op[0].disps->X_op == O_subtract | |
8604 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
8605 | { | |
8606 | symbolS *s = i.op[0].disps->X_add_symbol; | |
8607 | /* No padding to call to global or undefined tls_get_addr. */ | |
8608 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
8609 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
8610 | return 0; | |
8611 | } | |
8612 | } | |
8613 | ||
8614 | if (add_padding | |
8615 | && last_insn.kind != last_insn_other | |
8616 | && last_insn.seg == now_seg) | |
8617 | { | |
8618 | if (flag_debug) | |
8619 | as_warn_where (last_insn.file, last_insn.line, | |
8620 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8621 | last_insn.name, i.tm.name); | |
8622 | return 0; | |
8623 | } | |
8624 | ||
8625 | return add_padding; | |
8626 | } | |
8627 | ||
29b0f896 | 8628 | static void |
e3bb37b5 | 8629 | output_insn (void) |
29b0f896 | 8630 | { |
2bbd9c25 JJ |
8631 | fragS *insn_start_frag; |
8632 | offsetT insn_start_off; | |
e379e5f3 L |
8633 | fragS *fragP = NULL; |
8634 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
8635 | /* The initializer is arbitrary just to avoid uninitialized error. |
8636 | it's actually either assigned in add_branch_padding_frag_p | |
8637 | or never be used. */ | |
8638 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 8639 | |
b4a3a7b4 L |
8640 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8641 | if (IS_ELF && x86_used_note) | |
8642 | { | |
8643 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8644 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8645 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8646 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8647 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8648 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8649 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8650 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8651 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8652 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8653 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8654 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8655 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8656 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8657 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8658 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8659 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8660 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8661 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8662 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8663 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8664 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8665 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8666 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8667 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8668 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8669 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8670 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8671 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8672 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8673 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8674 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8675 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8676 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8677 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8678 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8679 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8680 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8681 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8682 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8683 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8684 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8685 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8686 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8687 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8688 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8689 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8690 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
462cac58 L |
8691 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
8692 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; | |
b4a3a7b4 L |
8693 | |
8694 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8695 | || i.tm.cpu_flags.bitfield.cpu287 | |
8696 | || i.tm.cpu_flags.bitfield.cpu387 | |
8697 | || i.tm.cpu_flags.bitfield.cpu687 | |
8698 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8699 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
319ff62c JB |
8700 | if (i.has_regmmx |
8701 | || i.tm.base_opcode == 0xf77 /* emms */ | |
a7e12755 L |
8702 | || i.tm.base_opcode == 0xf0e /* femms */ |
8703 | || i.tm.base_opcode == 0xf2a /* cvtpi2ps */ | |
8704 | || i.tm.base_opcode == 0x660f2a /* cvtpi2pd */) | |
b4a3a7b4 L |
8705 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
8706 | if (i.has_regxmm) | |
8707 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8708 | if (i.has_regymm) | |
8709 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8710 | if (i.has_regzmm) | |
8711 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8712 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8713 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8714 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8715 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8716 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8717 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8718 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8719 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8720 | } | |
8721 | #endif | |
8722 | ||
29b0f896 AM |
8723 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8724 | We can't do this after the insn has been output as the current | |
8725 | frag may have been closed off. eg. by frag_var. */ | |
8726 | dwarf2_emit_insn (0); | |
8727 | ||
2bbd9c25 JJ |
8728 | insn_start_frag = frag_now; |
8729 | insn_start_off = frag_now_fix (); | |
8730 | ||
79d72f45 | 8731 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
e379e5f3 L |
8732 | { |
8733 | char *p; | |
8734 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
8735 | unsigned int max_branch_padding_size = 14; | |
8736 | ||
8737 | /* Align section to boundary. */ | |
8738 | record_alignment (now_seg, align_branch_power); | |
8739 | ||
8740 | /* Make room for padding. */ | |
8741 | frag_grow (max_branch_padding_size); | |
8742 | ||
8743 | /* Start of the padding. */ | |
8744 | p = frag_more (0); | |
8745 | ||
8746 | fragP = frag_now; | |
8747 | ||
8748 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
8749 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
8750 | NULL, 0, p); | |
8751 | ||
79d72f45 | 8752 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
8753 | fragP->tc_frag_data.branch_type = branch; |
8754 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
8755 | } | |
8756 | ||
29b0f896 | 8757 | /* Output jumps. */ |
0cfa3eb3 | 8758 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 8759 | output_branch (); |
0cfa3eb3 JB |
8760 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
8761 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 8762 | output_jump (); |
0cfa3eb3 | 8763 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
8764 | output_interseg_jump (); |
8765 | else | |
8766 | { | |
8767 | /* Output normal instructions here. */ | |
8768 | char *p; | |
8769 | unsigned char *q; | |
47465058 | 8770 | unsigned int j; |
331d2d0d | 8771 | unsigned int prefix; |
79d72f45 | 8772 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 8773 | |
e4e00185 | 8774 | if (avoid_fence |
c3949f43 JB |
8775 | && (i.tm.base_opcode == 0xfaee8 |
8776 | || i.tm.base_opcode == 0xfaef0 | |
8777 | || i.tm.base_opcode == 0xfaef8)) | |
e4e00185 AS |
8778 | { |
8779 | /* Encode lfence, mfence, and sfence as | |
8780 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8781 | offsetT val = 0x240483f0ULL; | |
8782 | p = frag_more (5); | |
8783 | md_number_to_chars (p, val, 5); | |
8784 | return; | |
8785 | } | |
8786 | ||
d022bddd IT |
8787 | /* Some processors fail on LOCK prefix. This options makes |
8788 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8789 | if (omit_lock_prefix) | |
8790 | { | |
8791 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8792 | return; | |
8793 | i.prefix[LOCK_PREFIX] = 0; | |
8794 | } | |
8795 | ||
e379e5f3 L |
8796 | if (branch) |
8797 | /* Skip if this is a branch. */ | |
8798 | ; | |
79d72f45 | 8799 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
e379e5f3 L |
8800 | { |
8801 | /* Make room for padding. */ | |
8802 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
8803 | p = frag_more (0); | |
8804 | ||
8805 | fragP = frag_now; | |
8806 | ||
8807 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
8808 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
8809 | NULL, 0, p); | |
8810 | ||
79d72f45 | 8811 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
8812 | fragP->tc_frag_data.branch_type = align_branch_fused; |
8813 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
8814 | } | |
8815 | else if (add_branch_prefix_frag_p ()) | |
8816 | { | |
8817 | unsigned int max_prefix_size = align_branch_prefix_size; | |
8818 | ||
8819 | /* Make room for padding. */ | |
8820 | frag_grow (max_prefix_size); | |
8821 | p = frag_more (0); | |
8822 | ||
8823 | fragP = frag_now; | |
8824 | ||
8825 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
8826 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
8827 | NULL, 0, p); | |
8828 | ||
8829 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
8830 | } | |
8831 | ||
43234a1e L |
8832 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8833 | don't need the explicit prefix. */ | |
8834 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8835 | { |
c0f3af97 | 8836 | switch (i.tm.opcode_length) |
bc4bd9ab | 8837 | { |
c0f3af97 L |
8838 | case 3: |
8839 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8840 | { |
c0f3af97 | 8841 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
c3949f43 JB |
8842 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8843 | || prefix != REPE_PREFIX_OPCODE | |
8844 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
8845 | add_prefix (prefix); | |
c0f3af97 L |
8846 | } |
8847 | break; | |
8848 | case 2: | |
8849 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8850 | { | |
8851 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
c3949f43 | 8852 | add_prefix (prefix); |
4dffcebc | 8853 | } |
c0f3af97 L |
8854 | break; |
8855 | case 1: | |
8856 | break; | |
390c91cf L |
8857 | case 0: |
8858 | /* Check for pseudo prefixes. */ | |
8859 | as_bad_where (insn_start_frag->fr_file, | |
8860 | insn_start_frag->fr_line, | |
8861 | _("pseudo prefix without instruction")); | |
8862 | return; | |
c0f3af97 L |
8863 | default: |
8864 | abort (); | |
bc4bd9ab | 8865 | } |
c0f3af97 | 8866 | |
6d19a37a | 8867 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8868 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8869 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
8870 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
8871 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
8872 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
8873 | if (x86_elf_abi == X86_64_X32_ABI |
8874 | && i.operands == 2 | |
14470f07 L |
8875 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
8876 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
8877 | && i.prefix[REX_PREFIX] == 0) |
8878 | add_prefix (REX_OPCODE); | |
6d19a37a | 8879 | #endif |
cf61b747 | 8880 | |
c0f3af97 L |
8881 | /* The prefix bytes. */ |
8882 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8883 | if (*q) | |
8884 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8885 | } |
ae5c1c7b | 8886 | else |
c0f3af97 L |
8887 | { |
8888 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8889 | if (*q) | |
8890 | switch (j) | |
8891 | { | |
8892 | case REX_PREFIX: | |
8893 | /* REX byte is encoded in VEX prefix. */ | |
8894 | break; | |
8895 | case SEG_PREFIX: | |
8896 | case ADDR_PREFIX: | |
8897 | FRAG_APPEND_1_CHAR (*q); | |
8898 | break; | |
8899 | default: | |
8900 | /* There should be no other prefixes for instructions | |
8901 | with VEX prefix. */ | |
8902 | abort (); | |
8903 | } | |
8904 | ||
43234a1e L |
8905 | /* For EVEX instructions i.vrex should become 0 after |
8906 | build_evex_prefix. For VEX instructions upper 16 registers | |
8907 | aren't available, so VREX should be 0. */ | |
8908 | if (i.vrex) | |
8909 | abort (); | |
c0f3af97 L |
8910 | /* Now the VEX prefix. */ |
8911 | p = frag_more (i.vex.length); | |
8912 | for (j = 0; j < i.vex.length; j++) | |
8913 | p[j] = i.vex.bytes[j]; | |
8914 | } | |
252b5132 | 8915 | |
29b0f896 | 8916 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8917 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8918 | { |
8919 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8920 | } | |
8921 | else | |
8922 | { | |
4dffcebc | 8923 | switch (i.tm.opcode_length) |
331d2d0d | 8924 | { |
43234a1e L |
8925 | case 4: |
8926 | p = frag_more (4); | |
8927 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8928 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8929 | break; | |
4dffcebc | 8930 | case 3: |
331d2d0d L |
8931 | p = frag_more (3); |
8932 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8933 | break; |
8934 | case 2: | |
8935 | p = frag_more (2); | |
8936 | break; | |
8937 | default: | |
8938 | abort (); | |
8939 | break; | |
331d2d0d | 8940 | } |
0f10071e | 8941 | |
29b0f896 AM |
8942 | /* Put out high byte first: can't use md_number_to_chars! */ |
8943 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8944 | *p = i.tm.base_opcode & 0xff; | |
8945 | } | |
3e73aa7c | 8946 | |
29b0f896 | 8947 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8948 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8949 | { |
4a3523fa L |
8950 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8951 | | i.rm.reg << 3 | |
8952 | | i.rm.mode << 6)); | |
29b0f896 AM |
8953 | /* If i.rm.regmem == ESP (4) |
8954 | && i.rm.mode != (Register mode) | |
8955 | && not 16 bit | |
8956 | ==> need second modrm byte. */ | |
8957 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8958 | && i.rm.mode != 3 | |
dc821c5f | 8959 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8960 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8961 | | i.sib.index << 3 | |
8962 | | i.sib.scale << 6)); | |
29b0f896 | 8963 | } |
3e73aa7c | 8964 | |
29b0f896 | 8965 | if (i.disp_operands) |
2bbd9c25 | 8966 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8967 | |
29b0f896 | 8968 | if (i.imm_operands) |
2bbd9c25 | 8969 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
8970 | |
8971 | /* | |
8972 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
8973 | * absolute section, and abs_section_offset not getting updated as data | |
8974 | * gets added to the frag breaks the logic below. | |
8975 | */ | |
8976 | if (now_seg != absolute_section) | |
8977 | { | |
8978 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
8979 | if (j > 15) | |
8980 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
8981 | j); | |
e379e5f3 L |
8982 | else if (fragP) |
8983 | { | |
8984 | /* NB: Don't add prefix with GOTPC relocation since | |
8985 | output_disp() above depends on the fixed encoding | |
8986 | length. Can't add prefix with TLS relocation since | |
8987 | it breaks TLS linker optimization. */ | |
8988 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
8989 | /* Prefix count on the current instruction. */ | |
8990 | unsigned int count = i.vex.length; | |
8991 | unsigned int k; | |
8992 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
8993 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
8994 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
8995 | count++; | |
8996 | ||
8997 | /* Count prefixes for extended opcode maps. */ | |
8998 | if (!i.vex.length) | |
8999 | switch (i.tm.opcode_length) | |
9000 | { | |
9001 | case 3: | |
9002 | if (((i.tm.base_opcode >> 16) & 0xff) == 0xf) | |
9003 | { | |
9004 | count++; | |
9005 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
9006 | { | |
9007 | case 0x38: | |
9008 | case 0x3a: | |
9009 | count++; | |
9010 | break; | |
9011 | default: | |
9012 | break; | |
9013 | } | |
9014 | } | |
9015 | break; | |
9016 | case 2: | |
9017 | if (((i.tm.base_opcode >> 8) & 0xff) == 0xf) | |
9018 | count++; | |
9019 | break; | |
9020 | case 1: | |
9021 | break; | |
9022 | default: | |
9023 | abort (); | |
9024 | } | |
9025 | ||
9026 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
9027 | == BRANCH_PREFIX) | |
9028 | { | |
9029 | /* Set the maximum prefix size in BRANCH_PREFIX | |
9030 | frag. */ | |
9031 | if (fragP->tc_frag_data.max_bytes > max) | |
9032 | fragP->tc_frag_data.max_bytes = max; | |
9033 | if (fragP->tc_frag_data.max_bytes > count) | |
9034 | fragP->tc_frag_data.max_bytes -= count; | |
9035 | else | |
9036 | fragP->tc_frag_data.max_bytes = 0; | |
9037 | } | |
9038 | else | |
9039 | { | |
9040 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
9041 | frag. */ | |
9042 | unsigned int max_prefix_size; | |
9043 | if (align_branch_prefix_size > max) | |
9044 | max_prefix_size = max; | |
9045 | else | |
9046 | max_prefix_size = align_branch_prefix_size; | |
9047 | if (max_prefix_size > count) | |
9048 | fragP->tc_frag_data.max_prefix_length | |
9049 | = max_prefix_size - count; | |
9050 | } | |
9051 | ||
9052 | /* Use existing segment prefix if possible. Use CS | |
9053 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
9054 | segment prefix with ESP/EBP base register and use DS | |
9055 | segment prefix without ESP/EBP base register. */ | |
9056 | if (i.prefix[SEG_PREFIX]) | |
9057 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
9058 | else if (flag_code == CODE_64BIT) | |
9059 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
9060 | else if (i.base_reg | |
9061 | && (i.base_reg->reg_num == 4 | |
9062 | || i.base_reg->reg_num == 5)) | |
9063 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
9064 | else | |
9065 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
9066 | } | |
9c33702b | 9067 | } |
29b0f896 | 9068 | } |
252b5132 | 9069 | |
e379e5f3 L |
9070 | /* NB: Don't work with COND_JUMP86 without i386. */ |
9071 | if (align_branch_power | |
9072 | && now_seg != absolute_section | |
9073 | && cpu_arch_flags.bitfield.cpui386) | |
9074 | { | |
9075 | /* Terminate each frag so that we can add prefix and check for | |
9076 | fused jcc. */ | |
9077 | frag_wane (frag_now); | |
9078 | frag_new (0); | |
9079 | } | |
9080 | ||
29b0f896 AM |
9081 | #ifdef DEBUG386 |
9082 | if (flag_debug) | |
9083 | { | |
7b81dfbb | 9084 | pi ("" /*line*/, &i); |
29b0f896 AM |
9085 | } |
9086 | #endif /* DEBUG386 */ | |
9087 | } | |
252b5132 | 9088 | |
e205caa7 L |
9089 | /* Return the size of the displacement operand N. */ |
9090 | ||
9091 | static int | |
9092 | disp_size (unsigned int n) | |
9093 | { | |
9094 | int size = 4; | |
43234a1e | 9095 | |
b5014f7a | 9096 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
9097 | size = 8; |
9098 | else if (i.types[n].bitfield.disp8) | |
9099 | size = 1; | |
9100 | else if (i.types[n].bitfield.disp16) | |
9101 | size = 2; | |
e205caa7 L |
9102 | return size; |
9103 | } | |
9104 | ||
9105 | /* Return the size of the immediate operand N. */ | |
9106 | ||
9107 | static int | |
9108 | imm_size (unsigned int n) | |
9109 | { | |
9110 | int size = 4; | |
40fb9820 L |
9111 | if (i.types[n].bitfield.imm64) |
9112 | size = 8; | |
9113 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
9114 | size = 1; | |
9115 | else if (i.types[n].bitfield.imm16) | |
9116 | size = 2; | |
e205caa7 L |
9117 | return size; |
9118 | } | |
9119 | ||
29b0f896 | 9120 | static void |
64e74474 | 9121 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9122 | { |
9123 | char *p; | |
9124 | unsigned int n; | |
252b5132 | 9125 | |
29b0f896 AM |
9126 | for (n = 0; n < i.operands; n++) |
9127 | { | |
b5014f7a | 9128 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
9129 | { |
9130 | if (i.op[n].disps->X_op == O_constant) | |
9131 | { | |
e205caa7 | 9132 | int size = disp_size (n); |
43234a1e | 9133 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 9134 | |
629cfaf1 JB |
9135 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
9136 | size); | |
29b0f896 AM |
9137 | p = frag_more (size); |
9138 | md_number_to_chars (p, val, size); | |
9139 | } | |
9140 | else | |
9141 | { | |
f86103b7 | 9142 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 9143 | int size = disp_size (n); |
40fb9820 | 9144 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 9145 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 9146 | fixS *fixP; |
29b0f896 | 9147 | |
e205caa7 | 9148 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 9149 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 9150 | |
29b0f896 AM |
9151 | /* The PC relative address is computed relative |
9152 | to the instruction boundary, so in case immediate | |
9153 | fields follows, we need to adjust the value. */ | |
9154 | if (pcrel && i.imm_operands) | |
9155 | { | |
29b0f896 | 9156 | unsigned int n1; |
e205caa7 | 9157 | int sz = 0; |
252b5132 | 9158 | |
29b0f896 | 9159 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 9160 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 9161 | { |
e205caa7 L |
9162 | /* Only one immediate is allowed for PC |
9163 | relative address. */ | |
9c2799c2 | 9164 | gas_assert (sz == 0); |
e205caa7 L |
9165 | sz = imm_size (n1); |
9166 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 9167 | } |
29b0f896 | 9168 | /* We should find the immediate. */ |
9c2799c2 | 9169 | gas_assert (sz != 0); |
29b0f896 | 9170 | } |
520dc8e8 | 9171 | |
29b0f896 | 9172 | p = frag_more (size); |
d258b828 | 9173 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 9174 | if (GOT_symbol |
2bbd9c25 | 9175 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 9176 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9177 | || reloc_type == BFD_RELOC_X86_64_32S |
9178 | || (reloc_type == BFD_RELOC_64 | |
9179 | && object_64bit)) | |
d6ab8113 JB |
9180 | && (i.op[n].disps->X_op == O_symbol |
9181 | || (i.op[n].disps->X_op == O_add | |
9182 | && ((symbol_get_value_expression | |
9183 | (i.op[n].disps->X_op_symbol)->X_op) | |
9184 | == O_subtract)))) | |
9185 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 9186 | { |
4fa24527 | 9187 | if (!object_64bit) |
7b81dfbb AJ |
9188 | { |
9189 | reloc_type = BFD_RELOC_386_GOTPC; | |
e379e5f3 | 9190 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9191 | i.op[n].imms->X_add_number += |
9192 | encoding_length (insn_start_frag, insn_start_off, p); | |
7b81dfbb AJ |
9193 | } |
9194 | else if (reloc_type == BFD_RELOC_64) | |
9195 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 9196 | else |
7b81dfbb AJ |
9197 | /* Don't do the adjustment for x86-64, as there |
9198 | the pcrel addressing is relative to the _next_ | |
9199 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 9200 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 9201 | } |
e379e5f3 L |
9202 | else if (align_branch_power) |
9203 | { | |
9204 | switch (reloc_type) | |
9205 | { | |
9206 | case BFD_RELOC_386_TLS_GD: | |
9207 | case BFD_RELOC_386_TLS_LDM: | |
9208 | case BFD_RELOC_386_TLS_IE: | |
9209 | case BFD_RELOC_386_TLS_IE_32: | |
9210 | case BFD_RELOC_386_TLS_GOTIE: | |
9211 | case BFD_RELOC_386_TLS_GOTDESC: | |
9212 | case BFD_RELOC_386_TLS_DESC_CALL: | |
9213 | case BFD_RELOC_X86_64_TLSGD: | |
9214 | case BFD_RELOC_X86_64_TLSLD: | |
9215 | case BFD_RELOC_X86_64_GOTTPOFF: | |
9216 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
9217 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9218 | i.has_gotpc_tls_reloc = TRUE; | |
9219 | default: | |
9220 | break; | |
9221 | } | |
9222 | } | |
02a86693 L |
9223 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
9224 | size, i.op[n].disps, pcrel, | |
9225 | reloc_type); | |
9226 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
9227 | "test %reg, mem" and "binop mem, %reg" where binop | |
9228 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
9229 | instructions without data prefix. Always generate |
9230 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
9231 | if (i.prefix[DATA_PREFIX] == 0 | |
9232 | && (generate_relax_relocations | |
9233 | || (!object_64bit | |
9234 | && i.rm.mode == 0 | |
9235 | && i.rm.regmem == 5)) | |
0cb4071e L |
9236 | && (i.rm.mode == 2 |
9237 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
2ae4c703 | 9238 | && !is_any_vex_encoding(&i.tm) |
02a86693 L |
9239 | && ((i.operands == 1 |
9240 | && i.tm.base_opcode == 0xff | |
9241 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
9242 | || (i.operands == 2 | |
9243 | && (i.tm.base_opcode == 0x8b | |
9244 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 9245 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
9246 | { |
9247 | if (object_64bit) | |
9248 | { | |
9249 | fixP->fx_tcbit = i.rex != 0; | |
9250 | if (i.base_reg | |
e968fc9b | 9251 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
9252 | fixP->fx_tcbit2 = 1; |
9253 | } | |
9254 | else | |
9255 | fixP->fx_tcbit2 = 1; | |
9256 | } | |
29b0f896 AM |
9257 | } |
9258 | } | |
9259 | } | |
9260 | } | |
252b5132 | 9261 | |
29b0f896 | 9262 | static void |
64e74474 | 9263 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9264 | { |
9265 | char *p; | |
9266 | unsigned int n; | |
252b5132 | 9267 | |
29b0f896 AM |
9268 | for (n = 0; n < i.operands; n++) |
9269 | { | |
43234a1e L |
9270 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
9271 | if (i.rounding && (int) n == i.rounding->operand) | |
9272 | continue; | |
9273 | ||
40fb9820 | 9274 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
9275 | { |
9276 | if (i.op[n].imms->X_op == O_constant) | |
9277 | { | |
e205caa7 | 9278 | int size = imm_size (n); |
29b0f896 | 9279 | offsetT val; |
b4cac588 | 9280 | |
29b0f896 AM |
9281 | val = offset_in_range (i.op[n].imms->X_add_number, |
9282 | size); | |
9283 | p = frag_more (size); | |
9284 | md_number_to_chars (p, val, size); | |
9285 | } | |
9286 | else | |
9287 | { | |
9288 | /* Not absolute_section. | |
9289 | Need a 32-bit fixup (don't support 8bit | |
9290 | non-absolute imms). Try to support other | |
9291 | sizes ... */ | |
f86103b7 | 9292 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
9293 | int size = imm_size (n); |
9294 | int sign; | |
29b0f896 | 9295 | |
40fb9820 | 9296 | if (i.types[n].bitfield.imm32s |
a7d61044 | 9297 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 9298 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 9299 | sign = 1; |
e205caa7 L |
9300 | else |
9301 | sign = 0; | |
520dc8e8 | 9302 | |
29b0f896 | 9303 | p = frag_more (size); |
d258b828 | 9304 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 9305 | |
2bbd9c25 JJ |
9306 | /* This is tough to explain. We end up with this one if we |
9307 | * have operands that look like | |
9308 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
9309 | * obtain the absolute address of the GOT, and it is strongly | |
9310 | * preferable from a performance point of view to avoid using | |
9311 | * a runtime relocation for this. The actual sequence of | |
9312 | * instructions often look something like: | |
9313 | * | |
9314 | * call .L66 | |
9315 | * .L66: | |
9316 | * popl %ebx | |
9317 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
9318 | * | |
9319 | * The call and pop essentially return the absolute address | |
9320 | * of the label .L66 and store it in %ebx. The linker itself | |
9321 | * will ultimately change the first operand of the addl so | |
9322 | * that %ebx points to the GOT, but to keep things simple, the | |
9323 | * .o file must have this operand set so that it generates not | |
9324 | * the absolute address of .L66, but the absolute address of | |
9325 | * itself. This allows the linker itself simply treat a GOTPC | |
9326 | * relocation as asking for a pcrel offset to the GOT to be | |
9327 | * added in, and the addend of the relocation is stored in the | |
9328 | * operand field for the instruction itself. | |
9329 | * | |
9330 | * Our job here is to fix the operand so that it would add | |
9331 | * the correct offset so that %ebx would point to itself. The | |
9332 | * thing that is tricky is that .-.L66 will point to the | |
9333 | * beginning of the instruction, so we need to further modify | |
9334 | * the operand so that it will point to itself. There are | |
9335 | * other cases where you have something like: | |
9336 | * | |
9337 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
9338 | * | |
9339 | * and here no correction would be required. Internally in | |
9340 | * the assembler we treat operands of this form as not being | |
9341 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
9342 | * whether it would simplify matters to do it this way. Who | |
9343 | * knows. In earlier versions of the PIC patches, the | |
9344 | * pcrel_adjust field was used to store the correction, but | |
9345 | * since the expression is not pcrel, I felt it would be | |
9346 | * confusing to do it this way. */ | |
9347 | ||
d6ab8113 | 9348 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9349 | || reloc_type == BFD_RELOC_X86_64_32S |
9350 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
9351 | && GOT_symbol |
9352 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
9353 | && (i.op[n].imms->X_op == O_symbol | |
9354 | || (i.op[n].imms->X_op == O_add | |
9355 | && ((symbol_get_value_expression | |
9356 | (i.op[n].imms->X_op_symbol)->X_op) | |
9357 | == O_subtract)))) | |
9358 | { | |
4fa24527 | 9359 | if (!object_64bit) |
d6ab8113 | 9360 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 9361 | else if (size == 4) |
d6ab8113 | 9362 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
9363 | else if (size == 8) |
9364 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
e379e5f3 | 9365 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9366 | i.op[n].imms->X_add_number += |
9367 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 9368 | } |
29b0f896 AM |
9369 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
9370 | i.op[n].imms, 0, reloc_type); | |
9371 | } | |
9372 | } | |
9373 | } | |
252b5132 RH |
9374 | } |
9375 | \f | |
d182319b JB |
9376 | /* x86_cons_fix_new is called via the expression parsing code when a |
9377 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
9378 | static int cons_sign = -1; |
9379 | ||
9380 | void | |
e3bb37b5 | 9381 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 9382 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 9383 | { |
d258b828 | 9384 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
9385 | |
9386 | #ifdef TE_PE | |
9387 | if (exp->X_op == O_secrel) | |
9388 | { | |
9389 | exp->X_op = O_symbol; | |
9390 | r = BFD_RELOC_32_SECREL; | |
9391 | } | |
9392 | #endif | |
9393 | ||
9394 | fix_new_exp (frag, off, len, exp, 0, r); | |
9395 | } | |
9396 | ||
357d1bd8 L |
9397 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
9398 | purpose of the `.dc.a' internal pseudo-op. */ | |
9399 | ||
9400 | int | |
9401 | x86_address_bytes (void) | |
9402 | { | |
9403 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
9404 | return 4; | |
9405 | return stdoutput->arch_info->bits_per_address / 8; | |
9406 | } | |
9407 | ||
d382c579 TG |
9408 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
9409 | || defined (LEX_AT) | |
d258b828 | 9410 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 9411 | #else |
f3c180ae AM |
9412 | /* Parse operands of the form |
9413 | <symbol>@GOTOFF+<nnn> | |
9414 | and similar .plt or .got references. | |
9415 | ||
9416 | If we find one, set up the correct relocation in RELOC and copy the | |
9417 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
9418 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9419 | is non-null set it to the length of the string we removed from the | |
9420 | input line. Otherwise return NULL. */ | |
9421 | static char * | |
91d6fa6a | 9422 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 9423 | int *adjust, |
d258b828 | 9424 | i386_operand_type *types) |
f3c180ae | 9425 | { |
7b81dfbb AJ |
9426 | /* Some of the relocations depend on the size of what field is to |
9427 | be relocated. But in our callers i386_immediate and i386_displacement | |
9428 | we don't yet know the operand size (this will be set by insn | |
9429 | matching). Hence we record the word32 relocation here, | |
9430 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
9431 | static const struct { |
9432 | const char *str; | |
cff8d58a | 9433 | int len; |
4fa24527 | 9434 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 9435 | const i386_operand_type types64; |
f3c180ae | 9436 | } gotrel[] = { |
8ce3d284 | 9437 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
9438 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
9439 | BFD_RELOC_SIZE32 }, | |
9440 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 9441 | #endif |
cff8d58a L |
9442 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
9443 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 9444 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
9445 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
9446 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 9447 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9448 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
9449 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 9450 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9451 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
9452 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 9453 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9454 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
9455 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 9456 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9457 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
9458 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 9459 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9460 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
9461 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9462 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9463 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
9464 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 9465 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9466 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
9467 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 9468 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9469 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
9470 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 9471 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9472 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
9473 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9474 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9475 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
9476 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 9477 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9478 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
9479 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9480 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9481 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
9482 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9483 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9484 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
9485 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 9486 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
9487 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
9488 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 9489 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9490 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
9491 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 9492 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
9493 | }; |
9494 | char *cp; | |
9495 | unsigned int j; | |
9496 | ||
d382c579 | 9497 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
9498 | if (!IS_ELF) |
9499 | return NULL; | |
d382c579 | 9500 | #endif |
718ddfc0 | 9501 | |
f3c180ae | 9502 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 9503 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
9504 | return NULL; |
9505 | ||
47465058 | 9506 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 9507 | { |
cff8d58a | 9508 | int len = gotrel[j].len; |
28f81592 | 9509 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 9510 | { |
4fa24527 | 9511 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 9512 | { |
28f81592 AM |
9513 | int first, second; |
9514 | char *tmpbuf, *past_reloc; | |
f3c180ae | 9515 | |
91d6fa6a | 9516 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 9517 | |
3956db08 JB |
9518 | if (types) |
9519 | { | |
9520 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
9521 | { |
9522 | types->bitfield.imm32 = 1; | |
9523 | types->bitfield.disp32 = 1; | |
9524 | } | |
3956db08 JB |
9525 | else |
9526 | *types = gotrel[j].types64; | |
9527 | } | |
9528 | ||
8fd4256d | 9529 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
9530 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
9531 | ||
28f81592 | 9532 | /* The length of the first part of our input line. */ |
f3c180ae | 9533 | first = cp - input_line_pointer; |
28f81592 AM |
9534 | |
9535 | /* The second part goes from after the reloc token until | |
67c11a9b | 9536 | (and including) an end_of_line char or comma. */ |
28f81592 | 9537 | past_reloc = cp + 1 + len; |
67c11a9b AM |
9538 | cp = past_reloc; |
9539 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9540 | ++cp; | |
9541 | second = cp + 1 - past_reloc; | |
28f81592 AM |
9542 | |
9543 | /* Allocate and copy string. The trailing NUL shouldn't | |
9544 | be necessary, but be safe. */ | |
add39d23 | 9545 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 9546 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
9547 | if (second != 0 && *past_reloc != ' ') |
9548 | /* Replace the relocation token with ' ', so that | |
9549 | errors like foo@GOTOFF1 will be detected. */ | |
9550 | tmpbuf[first++] = ' '; | |
af89796a L |
9551 | else |
9552 | /* Increment length by 1 if the relocation token is | |
9553 | removed. */ | |
9554 | len++; | |
9555 | if (adjust) | |
9556 | *adjust = len; | |
0787a12d AM |
9557 | memcpy (tmpbuf + first, past_reloc, second); |
9558 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
9559 | return tmpbuf; |
9560 | } | |
9561 | ||
4fa24527 JB |
9562 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
9563 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
9564 | return NULL; |
9565 | } | |
9566 | } | |
9567 | ||
9568 | /* Might be a symbol version string. Don't as_bad here. */ | |
9569 | return NULL; | |
9570 | } | |
4e4f7c87 | 9571 | #endif |
f3c180ae | 9572 | |
a988325c NC |
9573 | #ifdef TE_PE |
9574 | #ifdef lex_got | |
9575 | #undef lex_got | |
9576 | #endif | |
9577 | /* Parse operands of the form | |
9578 | <symbol>@SECREL32+<nnn> | |
9579 | ||
9580 | If we find one, set up the correct relocation in RELOC and copy the | |
9581 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
9582 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9583 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
9584 | input line. Otherwise return NULL. |
9585 | ||
a988325c NC |
9586 | This function is copied from the ELF version above adjusted for PE targets. */ |
9587 | ||
9588 | static char * | |
9589 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
9590 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 9591 | i386_operand_type *types) |
a988325c NC |
9592 | { |
9593 | static const struct | |
9594 | { | |
9595 | const char *str; | |
9596 | int len; | |
9597 | const enum bfd_reloc_code_real rel[2]; | |
9598 | const i386_operand_type types64; | |
9599 | } | |
9600 | gotrel[] = | |
9601 | { | |
9602 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
9603 | BFD_RELOC_32_SECREL }, | |
9604 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
9605 | }; | |
9606 | ||
9607 | char *cp; | |
9608 | unsigned j; | |
9609 | ||
9610 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
9611 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
9612 | return NULL; | |
9613 | ||
9614 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
9615 | { | |
9616 | int len = gotrel[j].len; | |
9617 | ||
9618 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
9619 | { | |
9620 | if (gotrel[j].rel[object_64bit] != 0) | |
9621 | { | |
9622 | int first, second; | |
9623 | char *tmpbuf, *past_reloc; | |
9624 | ||
9625 | *rel = gotrel[j].rel[object_64bit]; | |
9626 | if (adjust) | |
9627 | *adjust = len; | |
9628 | ||
9629 | if (types) | |
9630 | { | |
9631 | if (flag_code != CODE_64BIT) | |
9632 | { | |
9633 | types->bitfield.imm32 = 1; | |
9634 | types->bitfield.disp32 = 1; | |
9635 | } | |
9636 | else | |
9637 | *types = gotrel[j].types64; | |
9638 | } | |
9639 | ||
9640 | /* The length of the first part of our input line. */ | |
9641 | first = cp - input_line_pointer; | |
9642 | ||
9643 | /* The second part goes from after the reloc token until | |
9644 | (and including) an end_of_line char or comma. */ | |
9645 | past_reloc = cp + 1 + len; | |
9646 | cp = past_reloc; | |
9647 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9648 | ++cp; | |
9649 | second = cp + 1 - past_reloc; | |
9650 | ||
9651 | /* Allocate and copy string. The trailing NUL shouldn't | |
9652 | be necessary, but be safe. */ | |
add39d23 | 9653 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
9654 | memcpy (tmpbuf, input_line_pointer, first); |
9655 | if (second != 0 && *past_reloc != ' ') | |
9656 | /* Replace the relocation token with ' ', so that | |
9657 | errors like foo@SECLREL321 will be detected. */ | |
9658 | tmpbuf[first++] = ' '; | |
9659 | memcpy (tmpbuf + first, past_reloc, second); | |
9660 | tmpbuf[first + second] = '\0'; | |
9661 | return tmpbuf; | |
9662 | } | |
9663 | ||
9664 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
9665 | gotrel[j].str, 1 << (5 + object_64bit)); | |
9666 | return NULL; | |
9667 | } | |
9668 | } | |
9669 | ||
9670 | /* Might be a symbol version string. Don't as_bad here. */ | |
9671 | return NULL; | |
9672 | } | |
9673 | ||
9674 | #endif /* TE_PE */ | |
9675 | ||
62ebcb5c | 9676 | bfd_reloc_code_real_type |
e3bb37b5 | 9677 | x86_cons (expressionS *exp, int size) |
f3c180ae | 9678 | { |
62ebcb5c AM |
9679 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
9680 | ||
ee86248c JB |
9681 | intel_syntax = -intel_syntax; |
9682 | ||
3c7b9c2c | 9683 | exp->X_md = 0; |
4fa24527 | 9684 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
9685 | { |
9686 | /* Handle @GOTOFF and the like in an expression. */ | |
9687 | char *save; | |
9688 | char *gotfree_input_line; | |
4a57f2cf | 9689 | int adjust = 0; |
f3c180ae AM |
9690 | |
9691 | save = input_line_pointer; | |
d258b828 | 9692 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
9693 | if (gotfree_input_line) |
9694 | input_line_pointer = gotfree_input_line; | |
9695 | ||
9696 | expression (exp); | |
9697 | ||
9698 | if (gotfree_input_line) | |
9699 | { | |
9700 | /* expression () has merrily parsed up to the end of line, | |
9701 | or a comma - in the wrong buffer. Transfer how far | |
9702 | input_line_pointer has moved to the right buffer. */ | |
9703 | input_line_pointer = (save | |
9704 | + (input_line_pointer - gotfree_input_line) | |
9705 | + adjust); | |
9706 | free (gotfree_input_line); | |
3992d3b7 AM |
9707 | if (exp->X_op == O_constant |
9708 | || exp->X_op == O_absent | |
9709 | || exp->X_op == O_illegal | |
0398aac5 | 9710 | || exp->X_op == O_register |
3992d3b7 AM |
9711 | || exp->X_op == O_big) |
9712 | { | |
9713 | char c = *input_line_pointer; | |
9714 | *input_line_pointer = 0; | |
9715 | as_bad (_("missing or invalid expression `%s'"), save); | |
9716 | *input_line_pointer = c; | |
9717 | } | |
b9519cfe L |
9718 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
9719 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
9720 | && exp->X_op != O_symbol) | |
9721 | { | |
9722 | char c = *input_line_pointer; | |
9723 | *input_line_pointer = 0; | |
9724 | as_bad (_("invalid PLT expression `%s'"), save); | |
9725 | *input_line_pointer = c; | |
9726 | } | |
f3c180ae AM |
9727 | } |
9728 | } | |
9729 | else | |
9730 | expression (exp); | |
ee86248c JB |
9731 | |
9732 | intel_syntax = -intel_syntax; | |
9733 | ||
9734 | if (intel_syntax) | |
9735 | i386_intel_simplify (exp); | |
62ebcb5c AM |
9736 | |
9737 | return got_reloc; | |
f3c180ae | 9738 | } |
f3c180ae | 9739 | |
9f32dd5b L |
9740 | static void |
9741 | signed_cons (int size) | |
6482c264 | 9742 | { |
d182319b JB |
9743 | if (flag_code == CODE_64BIT) |
9744 | cons_sign = 1; | |
9745 | cons (size); | |
9746 | cons_sign = -1; | |
6482c264 NC |
9747 | } |
9748 | ||
d182319b | 9749 | #ifdef TE_PE |
6482c264 | 9750 | static void |
7016a5d5 | 9751 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
9752 | { |
9753 | expressionS exp; | |
9754 | ||
9755 | do | |
9756 | { | |
9757 | expression (&exp); | |
9758 | if (exp.X_op == O_symbol) | |
9759 | exp.X_op = O_secrel; | |
9760 | ||
9761 | emit_expr (&exp, 4); | |
9762 | } | |
9763 | while (*input_line_pointer++ == ','); | |
9764 | ||
9765 | input_line_pointer--; | |
9766 | demand_empty_rest_of_line (); | |
9767 | } | |
6482c264 NC |
9768 | #endif |
9769 | ||
43234a1e L |
9770 | /* Handle Vector operations. */ |
9771 | ||
9772 | static char * | |
9773 | check_VecOperations (char *op_string, char *op_end) | |
9774 | { | |
9775 | const reg_entry *mask; | |
9776 | const char *saved; | |
9777 | char *end_op; | |
9778 | ||
9779 | while (*op_string | |
9780 | && (op_end == NULL || op_string < op_end)) | |
9781 | { | |
9782 | saved = op_string; | |
9783 | if (*op_string == '{') | |
9784 | { | |
9785 | op_string++; | |
9786 | ||
9787 | /* Check broadcasts. */ | |
9788 | if (strncmp (op_string, "1to", 3) == 0) | |
9789 | { | |
9790 | int bcst_type; | |
9791 | ||
9792 | if (i.broadcast) | |
9793 | goto duplicated_vec_op; | |
9794 | ||
9795 | op_string += 3; | |
9796 | if (*op_string == '8') | |
8e6e0792 | 9797 | bcst_type = 8; |
b28d1bda | 9798 | else if (*op_string == '4') |
8e6e0792 | 9799 | bcst_type = 4; |
b28d1bda | 9800 | else if (*op_string == '2') |
8e6e0792 | 9801 | bcst_type = 2; |
43234a1e L |
9802 | else if (*op_string == '1' |
9803 | && *(op_string+1) == '6') | |
9804 | { | |
8e6e0792 | 9805 | bcst_type = 16; |
43234a1e L |
9806 | op_string++; |
9807 | } | |
9808 | else | |
9809 | { | |
9810 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9811 | return NULL; | |
9812 | } | |
9813 | op_string++; | |
9814 | ||
9815 | broadcast_op.type = bcst_type; | |
9816 | broadcast_op.operand = this_operand; | |
1f75763a | 9817 | broadcast_op.bytes = 0; |
43234a1e L |
9818 | i.broadcast = &broadcast_op; |
9819 | } | |
9820 | /* Check masking operation. */ | |
9821 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9822 | { | |
9823 | /* k0 can't be used for write mask. */ | |
f74a6307 | 9824 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 9825 | { |
6d2cd6b2 JB |
9826 | as_bad (_("`%s%s' can't be used for write mask"), |
9827 | register_prefix, mask->reg_name); | |
43234a1e L |
9828 | return NULL; |
9829 | } | |
9830 | ||
9831 | if (!i.mask) | |
9832 | { | |
9833 | mask_op.mask = mask; | |
9834 | mask_op.zeroing = 0; | |
9835 | mask_op.operand = this_operand; | |
9836 | i.mask = &mask_op; | |
9837 | } | |
9838 | else | |
9839 | { | |
9840 | if (i.mask->mask) | |
9841 | goto duplicated_vec_op; | |
9842 | ||
9843 | i.mask->mask = mask; | |
9844 | ||
9845 | /* Only "{z}" is allowed here. No need to check | |
9846 | zeroing mask explicitly. */ | |
9847 | if (i.mask->operand != this_operand) | |
9848 | { | |
9849 | as_bad (_("invalid write mask `%s'"), saved); | |
9850 | return NULL; | |
9851 | } | |
9852 | } | |
9853 | ||
9854 | op_string = end_op; | |
9855 | } | |
9856 | /* Check zeroing-flag for masking operation. */ | |
9857 | else if (*op_string == 'z') | |
9858 | { | |
9859 | if (!i.mask) | |
9860 | { | |
9861 | mask_op.mask = NULL; | |
9862 | mask_op.zeroing = 1; | |
9863 | mask_op.operand = this_operand; | |
9864 | i.mask = &mask_op; | |
9865 | } | |
9866 | else | |
9867 | { | |
9868 | if (i.mask->zeroing) | |
9869 | { | |
9870 | duplicated_vec_op: | |
9871 | as_bad (_("duplicated `%s'"), saved); | |
9872 | return NULL; | |
9873 | } | |
9874 | ||
9875 | i.mask->zeroing = 1; | |
9876 | ||
9877 | /* Only "{%k}" is allowed here. No need to check mask | |
9878 | register explicitly. */ | |
9879 | if (i.mask->operand != this_operand) | |
9880 | { | |
9881 | as_bad (_("invalid zeroing-masking `%s'"), | |
9882 | saved); | |
9883 | return NULL; | |
9884 | } | |
9885 | } | |
9886 | ||
9887 | op_string++; | |
9888 | } | |
9889 | else | |
9890 | goto unknown_vec_op; | |
9891 | ||
9892 | if (*op_string != '}') | |
9893 | { | |
9894 | as_bad (_("missing `}' in `%s'"), saved); | |
9895 | return NULL; | |
9896 | } | |
9897 | op_string++; | |
0ba3a731 L |
9898 | |
9899 | /* Strip whitespace since the addition of pseudo prefixes | |
9900 | changed how the scrubber treats '{'. */ | |
9901 | if (is_space_char (*op_string)) | |
9902 | ++op_string; | |
9903 | ||
43234a1e L |
9904 | continue; |
9905 | } | |
9906 | unknown_vec_op: | |
9907 | /* We don't know this one. */ | |
9908 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9909 | return NULL; | |
9910 | } | |
9911 | ||
6d2cd6b2 JB |
9912 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9913 | { | |
9914 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9915 | return NULL; | |
9916 | } | |
9917 | ||
43234a1e L |
9918 | return op_string; |
9919 | } | |
9920 | ||
252b5132 | 9921 | static int |
70e41ade | 9922 | i386_immediate (char *imm_start) |
252b5132 RH |
9923 | { |
9924 | char *save_input_line_pointer; | |
f3c180ae | 9925 | char *gotfree_input_line; |
252b5132 | 9926 | segT exp_seg = 0; |
47926f60 | 9927 | expressionS *exp; |
40fb9820 L |
9928 | i386_operand_type types; |
9929 | ||
0dfbf9d7 | 9930 | operand_type_set (&types, ~0); |
252b5132 RH |
9931 | |
9932 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9933 | { | |
31b2323c L |
9934 | as_bad (_("at most %d immediate operands are allowed"), |
9935 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9936 | return 0; |
9937 | } | |
9938 | ||
9939 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9940 | i.op[this_operand].imms = exp; |
252b5132 RH |
9941 | |
9942 | if (is_space_char (*imm_start)) | |
9943 | ++imm_start; | |
9944 | ||
9945 | save_input_line_pointer = input_line_pointer; | |
9946 | input_line_pointer = imm_start; | |
9947 | ||
d258b828 | 9948 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9949 | if (gotfree_input_line) |
9950 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9951 | |
9952 | exp_seg = expression (exp); | |
9953 | ||
83183c0c | 9954 | SKIP_WHITESPACE (); |
43234a1e L |
9955 | |
9956 | /* Handle vector operations. */ | |
9957 | if (*input_line_pointer == '{') | |
9958 | { | |
9959 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9960 | NULL); | |
9961 | if (input_line_pointer == NULL) | |
9962 | return 0; | |
9963 | } | |
9964 | ||
252b5132 | 9965 | if (*input_line_pointer) |
f3c180ae | 9966 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9967 | |
9968 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9969 | if (gotfree_input_line) |
ee86248c JB |
9970 | { |
9971 | free (gotfree_input_line); | |
9972 | ||
9973 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9974 | exp->X_op = O_illegal; | |
9975 | } | |
9976 | ||
9977 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9978 | } | |
252b5132 | 9979 | |
ee86248c JB |
9980 | static int |
9981 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9982 | i386_operand_type types, const char *imm_start) | |
9983 | { | |
9984 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9985 | { |
313c53d1 L |
9986 | if (imm_start) |
9987 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9988 | imm_start); | |
3992d3b7 | 9989 | return 0; |
252b5132 | 9990 | } |
3e73aa7c | 9991 | else if (exp->X_op == O_constant) |
252b5132 | 9992 | { |
47926f60 | 9993 | /* Size it properly later. */ |
40fb9820 | 9994 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9995 | /* If not 64bit, sign extend val. */ |
9996 | if (flag_code != CODE_64BIT | |
4eed87de AM |
9997 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
9998 | exp->X_add_number | |
9999 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 10000 | } |
4c63da97 | 10001 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 10002 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 10003 | && exp_seg != absolute_section |
47926f60 | 10004 | && exp_seg != text_section |
24eab124 AM |
10005 | && exp_seg != data_section |
10006 | && exp_seg != bss_section | |
10007 | && exp_seg != undefined_section | |
f86103b7 | 10008 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 10009 | { |
d0b47220 | 10010 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
10011 | return 0; |
10012 | } | |
10013 | #endif | |
a841bdf5 | 10014 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 10015 | { |
313c53d1 L |
10016 | if (imm_start) |
10017 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
10018 | return 0; |
10019 | } | |
252b5132 RH |
10020 | else |
10021 | { | |
10022 | /* This is an address. The size of the address will be | |
24eab124 | 10023 | determined later, depending on destination register, |
3e73aa7c | 10024 | suffix, or the default for the section. */ |
40fb9820 L |
10025 | i.types[this_operand].bitfield.imm8 = 1; |
10026 | i.types[this_operand].bitfield.imm16 = 1; | |
10027 | i.types[this_operand].bitfield.imm32 = 1; | |
10028 | i.types[this_operand].bitfield.imm32s = 1; | |
10029 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
10030 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10031 | types); | |
252b5132 RH |
10032 | } |
10033 | ||
10034 | return 1; | |
10035 | } | |
10036 | ||
551c1ca1 | 10037 | static char * |
e3bb37b5 | 10038 | i386_scale (char *scale) |
252b5132 | 10039 | { |
551c1ca1 AM |
10040 | offsetT val; |
10041 | char *save = input_line_pointer; | |
252b5132 | 10042 | |
551c1ca1 AM |
10043 | input_line_pointer = scale; |
10044 | val = get_absolute_expression (); | |
10045 | ||
10046 | switch (val) | |
252b5132 | 10047 | { |
551c1ca1 | 10048 | case 1: |
252b5132 RH |
10049 | i.log2_scale_factor = 0; |
10050 | break; | |
551c1ca1 | 10051 | case 2: |
252b5132 RH |
10052 | i.log2_scale_factor = 1; |
10053 | break; | |
551c1ca1 | 10054 | case 4: |
252b5132 RH |
10055 | i.log2_scale_factor = 2; |
10056 | break; | |
551c1ca1 | 10057 | case 8: |
252b5132 RH |
10058 | i.log2_scale_factor = 3; |
10059 | break; | |
10060 | default: | |
a724f0f4 JB |
10061 | { |
10062 | char sep = *input_line_pointer; | |
10063 | ||
10064 | *input_line_pointer = '\0'; | |
10065 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
10066 | scale); | |
10067 | *input_line_pointer = sep; | |
10068 | input_line_pointer = save; | |
10069 | return NULL; | |
10070 | } | |
252b5132 | 10071 | } |
29b0f896 | 10072 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
10073 | { |
10074 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 10075 | 1 << i.log2_scale_factor); |
252b5132 | 10076 | i.log2_scale_factor = 0; |
252b5132 | 10077 | } |
551c1ca1 AM |
10078 | scale = input_line_pointer; |
10079 | input_line_pointer = save; | |
10080 | return scale; | |
252b5132 RH |
10081 | } |
10082 | ||
252b5132 | 10083 | static int |
e3bb37b5 | 10084 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 10085 | { |
29b0f896 | 10086 | expressionS *exp; |
252b5132 RH |
10087 | segT exp_seg = 0; |
10088 | char *save_input_line_pointer; | |
f3c180ae | 10089 | char *gotfree_input_line; |
40fb9820 L |
10090 | int override; |
10091 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 10092 | int ret; |
252b5132 | 10093 | |
31b2323c L |
10094 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
10095 | { | |
10096 | as_bad (_("at most %d displacement operands are allowed"), | |
10097 | MAX_MEMORY_OPERANDS); | |
10098 | return 0; | |
10099 | } | |
10100 | ||
0dfbf9d7 | 10101 | operand_type_set (&bigdisp, 0); |
6f2f06be | 10102 | if (i.jumpabsolute |
48bcea9f | 10103 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
10104 | || (current_templates->start->opcode_modifier.jump != JUMP |
10105 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 10106 | { |
48bcea9f | 10107 | i386_addressing_mode (); |
e05278af | 10108 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
10109 | if (flag_code == CODE_64BIT) |
10110 | { | |
10111 | if (!override) | |
10112 | { | |
10113 | bigdisp.bitfield.disp32s = 1; | |
10114 | bigdisp.bitfield.disp64 = 1; | |
10115 | } | |
48bcea9f JB |
10116 | else |
10117 | bigdisp.bitfield.disp32 = 1; | |
40fb9820 L |
10118 | } |
10119 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 10120 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
10121 | else |
10122 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
10123 | } |
10124 | else | |
10125 | { | |
376cd056 JB |
10126 | /* For PC-relative branches, the width of the displacement may be |
10127 | dependent upon data size, but is never dependent upon address size. | |
10128 | Also make sure to not unintentionally match against a non-PC-relative | |
10129 | branch template. */ | |
10130 | static templates aux_templates; | |
10131 | const insn_template *t = current_templates->start; | |
10132 | bfd_boolean has_intel64 = FALSE; | |
10133 | ||
10134 | aux_templates.start = t; | |
10135 | while (++t < current_templates->end) | |
10136 | { | |
10137 | if (t->opcode_modifier.jump | |
10138 | != current_templates->start->opcode_modifier.jump) | |
10139 | break; | |
4b5aaf5f | 10140 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
376cd056 JB |
10141 | has_intel64 = TRUE; |
10142 | } | |
10143 | if (t < current_templates->end) | |
10144 | { | |
10145 | aux_templates.end = t; | |
10146 | current_templates = &aux_templates; | |
10147 | } | |
10148 | ||
e05278af | 10149 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
10150 | if (flag_code == CODE_64BIT) |
10151 | { | |
376cd056 JB |
10152 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
10153 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
10154 | bigdisp.bitfield.disp16 = 1; |
10155 | else | |
48bcea9f | 10156 | bigdisp.bitfield.disp32s = 1; |
40fb9820 L |
10157 | } |
10158 | else | |
e05278af JB |
10159 | { |
10160 | if (!override) | |
10161 | override = (i.suffix == (flag_code != CODE_16BIT | |
10162 | ? WORD_MNEM_SUFFIX | |
10163 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
10164 | bigdisp.bitfield.disp32 = 1; |
10165 | if ((flag_code == CODE_16BIT) ^ override) | |
10166 | { | |
10167 | bigdisp.bitfield.disp32 = 0; | |
10168 | bigdisp.bitfield.disp16 = 1; | |
10169 | } | |
e05278af | 10170 | } |
e05278af | 10171 | } |
c6fb90c8 L |
10172 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10173 | bigdisp); | |
252b5132 RH |
10174 | |
10175 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 10176 | i.op[this_operand].disps = exp; |
252b5132 RH |
10177 | i.disp_operands++; |
10178 | save_input_line_pointer = input_line_pointer; | |
10179 | input_line_pointer = disp_start; | |
10180 | END_STRING_AND_SAVE (disp_end); | |
10181 | ||
10182 | #ifndef GCC_ASM_O_HACK | |
10183 | #define GCC_ASM_O_HACK 0 | |
10184 | #endif | |
10185 | #if GCC_ASM_O_HACK | |
10186 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 10187 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 10188 | && displacement_string_end[-1] == '+') |
252b5132 RH |
10189 | { |
10190 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
10191 | constraint within gcc asm statements. |
10192 | For instance: | |
10193 | ||
10194 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
10195 | __asm__ __volatile__ ( \ | |
10196 | "movw %w2,%0\n\t" \ | |
10197 | "movw %w1,2+%0\n\t" \ | |
10198 | "rorl $16,%1\n\t" \ | |
10199 | "movb %b1,4+%0\n\t" \ | |
10200 | "movb %4,5+%0\n\t" \ | |
10201 | "movb $0,6+%0\n\t" \ | |
10202 | "movb %h1,7+%0\n\t" \ | |
10203 | "rorl $16,%1" \ | |
10204 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
10205 | ||
10206 | This works great except that the output assembler ends | |
10207 | up looking a bit weird if it turns out that there is | |
10208 | no offset. You end up producing code that looks like: | |
10209 | ||
10210 | #APP | |
10211 | movw $235,(%eax) | |
10212 | movw %dx,2+(%eax) | |
10213 | rorl $16,%edx | |
10214 | movb %dl,4+(%eax) | |
10215 | movb $137,5+(%eax) | |
10216 | movb $0,6+(%eax) | |
10217 | movb %dh,7+(%eax) | |
10218 | rorl $16,%edx | |
10219 | #NO_APP | |
10220 | ||
47926f60 | 10221 | So here we provide the missing zero. */ |
24eab124 AM |
10222 | |
10223 | *displacement_string_end = '0'; | |
252b5132 RH |
10224 | } |
10225 | #endif | |
d258b828 | 10226 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10227 | if (gotfree_input_line) |
10228 | input_line_pointer = gotfree_input_line; | |
252b5132 | 10229 | |
24eab124 | 10230 | exp_seg = expression (exp); |
252b5132 | 10231 | |
636c26b0 AM |
10232 | SKIP_WHITESPACE (); |
10233 | if (*input_line_pointer) | |
10234 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
10235 | #if GCC_ASM_O_HACK | |
10236 | RESTORE_END_STRING (disp_end + 1); | |
10237 | #endif | |
636c26b0 | 10238 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 10239 | if (gotfree_input_line) |
ee86248c JB |
10240 | { |
10241 | free (gotfree_input_line); | |
10242 | ||
10243 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10244 | exp->X_op = O_illegal; | |
10245 | } | |
10246 | ||
10247 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
10248 | ||
10249 | RESTORE_END_STRING (disp_end); | |
10250 | ||
10251 | return ret; | |
10252 | } | |
10253 | ||
10254 | static int | |
10255 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10256 | i386_operand_type types, const char *disp_start) | |
10257 | { | |
10258 | i386_operand_type bigdisp; | |
10259 | int ret = 1; | |
636c26b0 | 10260 | |
24eab124 AM |
10261 | /* We do this to make sure that the section symbol is in |
10262 | the symbol table. We will ultimately change the relocation | |
47926f60 | 10263 | to be relative to the beginning of the section. */ |
1ae12ab7 | 10264 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
10265 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
10266 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 10267 | { |
636c26b0 | 10268 | if (exp->X_op != O_symbol) |
3992d3b7 | 10269 | goto inv_disp; |
636c26b0 | 10270 | |
e5cb08ac | 10271 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
10272 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
10273 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 10274 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
10275 | exp->X_op = O_subtract; |
10276 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 10277 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 10278 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
10279 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
10280 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 10281 | else |
29b0f896 | 10282 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 10283 | } |
252b5132 | 10284 | |
3992d3b7 AM |
10285 | else if (exp->X_op == O_absent |
10286 | || exp->X_op == O_illegal | |
ee86248c | 10287 | || exp->X_op == O_big) |
2daf4fd8 | 10288 | { |
3992d3b7 AM |
10289 | inv_disp: |
10290 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 10291 | disp_start); |
3992d3b7 | 10292 | ret = 0; |
2daf4fd8 AM |
10293 | } |
10294 | ||
0e1147d9 L |
10295 | else if (flag_code == CODE_64BIT |
10296 | && !i.prefix[ADDR_PREFIX] | |
10297 | && exp->X_op == O_constant) | |
10298 | { | |
10299 | /* Since displacement is signed extended to 64bit, don't allow | |
10300 | disp32 and turn off disp32s if they are out of range. */ | |
10301 | i.types[this_operand].bitfield.disp32 = 0; | |
10302 | if (!fits_in_signed_long (exp->X_add_number)) | |
10303 | { | |
10304 | i.types[this_operand].bitfield.disp32s = 0; | |
10305 | if (i.types[this_operand].bitfield.baseindex) | |
10306 | { | |
10307 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
10308 | (long) exp->X_add_number); | |
10309 | ret = 0; | |
10310 | } | |
10311 | } | |
10312 | } | |
10313 | ||
4c63da97 | 10314 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
10315 | else if (exp->X_op != O_constant |
10316 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
10317 | && exp_seg != absolute_section | |
10318 | && exp_seg != text_section | |
10319 | && exp_seg != data_section | |
10320 | && exp_seg != bss_section | |
10321 | && exp_seg != undefined_section | |
10322 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 10323 | { |
d0b47220 | 10324 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 10325 | ret = 0; |
24eab124 | 10326 | } |
252b5132 | 10327 | #endif |
3956db08 | 10328 | |
48bcea9f JB |
10329 | if (current_templates->start->opcode_modifier.jump == JUMP_BYTE |
10330 | /* Constants get taken care of by optimize_disp(). */ | |
10331 | && exp->X_op != O_constant) | |
10332 | i.types[this_operand].bitfield.disp8 = 1; | |
10333 | ||
40fb9820 L |
10334 | /* Check if this is a displacement only operand. */ |
10335 | bigdisp = i.types[this_operand]; | |
10336 | bigdisp.bitfield.disp8 = 0; | |
10337 | bigdisp.bitfield.disp16 = 0; | |
10338 | bigdisp.bitfield.disp32 = 0; | |
10339 | bigdisp.bitfield.disp32s = 0; | |
10340 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 10341 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
10342 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10343 | types); | |
3956db08 | 10344 | |
3992d3b7 | 10345 | return ret; |
252b5132 RH |
10346 | } |
10347 | ||
2abc2bec JB |
10348 | /* Return the active addressing mode, taking address override and |
10349 | registers forming the address into consideration. Update the | |
10350 | address override prefix if necessary. */ | |
47926f60 | 10351 | |
2abc2bec JB |
10352 | static enum flag_code |
10353 | i386_addressing_mode (void) | |
252b5132 | 10354 | { |
be05d201 L |
10355 | enum flag_code addr_mode; |
10356 | ||
10357 | if (i.prefix[ADDR_PREFIX]) | |
10358 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
10359 | else | |
10360 | { | |
10361 | addr_mode = flag_code; | |
10362 | ||
24eab124 | 10363 | #if INFER_ADDR_PREFIX |
be05d201 L |
10364 | if (i.mem_operands == 0) |
10365 | { | |
10366 | /* Infer address prefix from the first memory operand. */ | |
10367 | const reg_entry *addr_reg = i.base_reg; | |
10368 | ||
10369 | if (addr_reg == NULL) | |
10370 | addr_reg = i.index_reg; | |
eecb386c | 10371 | |
be05d201 L |
10372 | if (addr_reg) |
10373 | { | |
e968fc9b | 10374 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
10375 | addr_mode = CODE_32BIT; |
10376 | else if (flag_code != CODE_64BIT | |
dc821c5f | 10377 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
10378 | addr_mode = CODE_16BIT; |
10379 | ||
10380 | if (addr_mode != flag_code) | |
10381 | { | |
10382 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
10383 | i.prefixes += 1; | |
10384 | /* Change the size of any displacement too. At most one | |
10385 | of Disp16 or Disp32 is set. | |
10386 | FIXME. There doesn't seem to be any real need for | |
10387 | separate Disp16 and Disp32 flags. The same goes for | |
10388 | Imm16 and Imm32. Removing them would probably clean | |
10389 | up the code quite a lot. */ | |
10390 | if (flag_code != CODE_64BIT | |
10391 | && (i.types[this_operand].bitfield.disp16 | |
10392 | || i.types[this_operand].bitfield.disp32)) | |
10393 | i.types[this_operand] | |
10394 | = operand_type_xor (i.types[this_operand], disp16_32); | |
10395 | } | |
10396 | } | |
10397 | } | |
24eab124 | 10398 | #endif |
be05d201 L |
10399 | } |
10400 | ||
2abc2bec JB |
10401 | return addr_mode; |
10402 | } | |
10403 | ||
10404 | /* Make sure the memory operand we've been dealt is valid. | |
10405 | Return 1 on success, 0 on a failure. */ | |
10406 | ||
10407 | static int | |
10408 | i386_index_check (const char *operand_string) | |
10409 | { | |
10410 | const char *kind = "base/index"; | |
10411 | enum flag_code addr_mode = i386_addressing_mode (); | |
10412 | ||
fc0763e6 | 10413 | if (current_templates->start->opcode_modifier.isstring |
c3949f43 | 10414 | && !current_templates->start->cpu_flags.bitfield.cpupadlock |
fc0763e6 JB |
10415 | && (current_templates->end[-1].opcode_modifier.isstring |
10416 | || i.mem_operands)) | |
10417 | { | |
10418 | /* Memory operands of string insns are special in that they only allow | |
10419 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
10420 | const reg_entry *expected_reg; |
10421 | static const char *di_si[][2] = | |
10422 | { | |
10423 | { "esi", "edi" }, | |
10424 | { "si", "di" }, | |
10425 | { "rsi", "rdi" } | |
10426 | }; | |
10427 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
10428 | |
10429 | kind = "string address"; | |
10430 | ||
8325cc63 | 10431 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 | 10432 | { |
51c8edf6 JB |
10433 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
10434 | - IS_STRING_ES_OP0; | |
10435 | int op = 0; | |
fc0763e6 | 10436 | |
51c8edf6 | 10437 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
fc0763e6 JB |
10438 | || ((!i.mem_operands != !intel_syntax) |
10439 | && current_templates->end[-1].operand_types[1] | |
10440 | .bitfield.baseindex)) | |
51c8edf6 JB |
10441 | op = 1; |
10442 | expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
10443 | } |
10444 | else | |
be05d201 | 10445 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 10446 | |
be05d201 L |
10447 | if (i.base_reg != expected_reg |
10448 | || i.index_reg | |
fc0763e6 | 10449 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 10450 | { |
be05d201 L |
10451 | /* The second memory operand must have the same size as |
10452 | the first one. */ | |
10453 | if (i.mem_operands | |
10454 | && i.base_reg | |
10455 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 10456 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 10457 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
10458 | ? i.base_reg->reg_type.bitfield.dword |
10459 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
10460 | goto bad_address; |
10461 | ||
fc0763e6 JB |
10462 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
10463 | operand_string, | |
10464 | intel_syntax ? '[' : '(', | |
10465 | register_prefix, | |
be05d201 | 10466 | expected_reg->reg_name, |
fc0763e6 | 10467 | intel_syntax ? ']' : ')'); |
be05d201 | 10468 | return 1; |
fc0763e6 | 10469 | } |
be05d201 L |
10470 | else |
10471 | return 1; | |
10472 | ||
dc1e8a47 | 10473 | bad_address: |
be05d201 L |
10474 | as_bad (_("`%s' is not a valid %s expression"), |
10475 | operand_string, kind); | |
10476 | return 0; | |
3e73aa7c JH |
10477 | } |
10478 | else | |
10479 | { | |
be05d201 L |
10480 | if (addr_mode != CODE_16BIT) |
10481 | { | |
10482 | /* 32-bit/64-bit checks. */ | |
10483 | if ((i.base_reg | |
e968fc9b JB |
10484 | && ((addr_mode == CODE_64BIT |
10485 | ? !i.base_reg->reg_type.bitfield.qword | |
10486 | : !i.base_reg->reg_type.bitfield.dword) | |
10487 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
10488 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 10489 | || (i.index_reg |
1b54b8d7 JB |
10490 | && !i.index_reg->reg_type.bitfield.xmmword |
10491 | && !i.index_reg->reg_type.bitfield.ymmword | |
10492 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 10493 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
10494 | ? !i.index_reg->reg_type.bitfield.qword |
10495 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
10496 | || !i.index_reg->reg_type.bitfield.baseindex))) |
10497 | goto bad_address; | |
8178be5b JB |
10498 | |
10499 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
10500 | if (current_templates->start->base_opcode == 0xf30f1b | |
10501 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
10502 | { | |
10503 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 10504 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
10505 | { |
10506 | as_bad (_("`%s' cannot be used here"), operand_string); | |
10507 | return 0; | |
10508 | } | |
10509 | ||
10510 | /* bndldx and bndstx ignore their scale factor. */ | |
10511 | if (current_templates->start->base_opcode != 0xf30f1b | |
10512 | && i.log2_scale_factor) | |
10513 | as_warn (_("register scaling is being ignored here")); | |
10514 | } | |
be05d201 L |
10515 | } |
10516 | else | |
3e73aa7c | 10517 | { |
be05d201 | 10518 | /* 16-bit checks. */ |
3e73aa7c | 10519 | if ((i.base_reg |
dc821c5f | 10520 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 10521 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 10522 | || (i.index_reg |
dc821c5f | 10523 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 10524 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
10525 | || !(i.base_reg |
10526 | && i.base_reg->reg_num < 6 | |
10527 | && i.index_reg->reg_num >= 6 | |
10528 | && i.log2_scale_factor == 0)))) | |
be05d201 | 10529 | goto bad_address; |
3e73aa7c JH |
10530 | } |
10531 | } | |
be05d201 | 10532 | return 1; |
24eab124 | 10533 | } |
252b5132 | 10534 | |
43234a1e L |
10535 | /* Handle vector immediates. */ |
10536 | ||
10537 | static int | |
10538 | RC_SAE_immediate (const char *imm_start) | |
10539 | { | |
10540 | unsigned int match_found, j; | |
10541 | const char *pstr = imm_start; | |
10542 | expressionS *exp; | |
10543 | ||
10544 | if (*pstr != '{') | |
10545 | return 0; | |
10546 | ||
10547 | pstr++; | |
10548 | match_found = 0; | |
10549 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
10550 | { | |
10551 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
10552 | { | |
10553 | if (!i.rounding) | |
10554 | { | |
10555 | rc_op.type = RC_NamesTable[j].type; | |
10556 | rc_op.operand = this_operand; | |
10557 | i.rounding = &rc_op; | |
10558 | } | |
10559 | else | |
10560 | { | |
10561 | as_bad (_("duplicated `%s'"), imm_start); | |
10562 | return 0; | |
10563 | } | |
10564 | pstr += RC_NamesTable[j].len; | |
10565 | match_found = 1; | |
10566 | break; | |
10567 | } | |
10568 | } | |
10569 | if (!match_found) | |
10570 | return 0; | |
10571 | ||
10572 | if (*pstr++ != '}') | |
10573 | { | |
10574 | as_bad (_("Missing '}': '%s'"), imm_start); | |
10575 | return 0; | |
10576 | } | |
10577 | /* RC/SAE immediate string should contain nothing more. */; | |
10578 | if (*pstr != 0) | |
10579 | { | |
10580 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
10581 | return 0; | |
10582 | } | |
10583 | ||
10584 | exp = &im_expressions[i.imm_operands++]; | |
10585 | i.op[this_operand].imms = exp; | |
10586 | ||
10587 | exp->X_op = O_constant; | |
10588 | exp->X_add_number = 0; | |
10589 | exp->X_add_symbol = (symbolS *) 0; | |
10590 | exp->X_op_symbol = (symbolS *) 0; | |
10591 | ||
10592 | i.types[this_operand].bitfield.imm8 = 1; | |
10593 | return 1; | |
10594 | } | |
10595 | ||
8325cc63 JB |
10596 | /* Only string instructions can have a second memory operand, so |
10597 | reduce current_templates to just those if it contains any. */ | |
10598 | static int | |
10599 | maybe_adjust_templates (void) | |
10600 | { | |
10601 | const insn_template *t; | |
10602 | ||
10603 | gas_assert (i.mem_operands == 1); | |
10604 | ||
10605 | for (t = current_templates->start; t < current_templates->end; ++t) | |
10606 | if (t->opcode_modifier.isstring) | |
10607 | break; | |
10608 | ||
10609 | if (t < current_templates->end) | |
10610 | { | |
10611 | static templates aux_templates; | |
10612 | bfd_boolean recheck; | |
10613 | ||
10614 | aux_templates.start = t; | |
10615 | for (; t < current_templates->end; ++t) | |
10616 | if (!t->opcode_modifier.isstring) | |
10617 | break; | |
10618 | aux_templates.end = t; | |
10619 | ||
10620 | /* Determine whether to re-check the first memory operand. */ | |
10621 | recheck = (aux_templates.start != current_templates->start | |
10622 | || t != current_templates->end); | |
10623 | ||
10624 | current_templates = &aux_templates; | |
10625 | ||
10626 | if (recheck) | |
10627 | { | |
10628 | i.mem_operands = 0; | |
10629 | if (i.memop1_string != NULL | |
10630 | && i386_index_check (i.memop1_string) == 0) | |
10631 | return 0; | |
10632 | i.mem_operands = 1; | |
10633 | } | |
10634 | } | |
10635 | ||
10636 | return 1; | |
10637 | } | |
10638 | ||
fc0763e6 | 10639 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 10640 | on error. */ |
252b5132 | 10641 | |
252b5132 | 10642 | static int |
a7619375 | 10643 | i386_att_operand (char *operand_string) |
252b5132 | 10644 | { |
af6bdddf AM |
10645 | const reg_entry *r; |
10646 | char *end_op; | |
24eab124 | 10647 | char *op_string = operand_string; |
252b5132 | 10648 | |
24eab124 | 10649 | if (is_space_char (*op_string)) |
252b5132 RH |
10650 | ++op_string; |
10651 | ||
24eab124 | 10652 | /* We check for an absolute prefix (differentiating, |
47926f60 | 10653 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
10654 | if (*op_string == ABSOLUTE_PREFIX) |
10655 | { | |
10656 | ++op_string; | |
10657 | if (is_space_char (*op_string)) | |
10658 | ++op_string; | |
6f2f06be | 10659 | i.jumpabsolute = TRUE; |
24eab124 | 10660 | } |
252b5132 | 10661 | |
47926f60 | 10662 | /* Check if operand is a register. */ |
4d1bb795 | 10663 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 10664 | { |
40fb9820 L |
10665 | i386_operand_type temp; |
10666 | ||
24eab124 AM |
10667 | /* Check for a segment override by searching for ':' after a |
10668 | segment register. */ | |
10669 | op_string = end_op; | |
10670 | if (is_space_char (*op_string)) | |
10671 | ++op_string; | |
00cee14f | 10672 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 AM |
10673 | { |
10674 | switch (r->reg_num) | |
10675 | { | |
10676 | case 0: | |
10677 | i.seg[i.mem_operands] = &es; | |
10678 | break; | |
10679 | case 1: | |
10680 | i.seg[i.mem_operands] = &cs; | |
10681 | break; | |
10682 | case 2: | |
10683 | i.seg[i.mem_operands] = &ss; | |
10684 | break; | |
10685 | case 3: | |
10686 | i.seg[i.mem_operands] = &ds; | |
10687 | break; | |
10688 | case 4: | |
10689 | i.seg[i.mem_operands] = &fs; | |
10690 | break; | |
10691 | case 5: | |
10692 | i.seg[i.mem_operands] = &gs; | |
10693 | break; | |
10694 | } | |
252b5132 | 10695 | |
24eab124 | 10696 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
10697 | ++op_string; |
10698 | if (is_space_char (*op_string)) | |
24eab124 | 10699 | ++op_string; |
252b5132 | 10700 | |
24eab124 AM |
10701 | if (!is_digit_char (*op_string) |
10702 | && !is_identifier_char (*op_string) | |
10703 | && *op_string != '(' | |
10704 | && *op_string != ABSOLUTE_PREFIX) | |
10705 | { | |
10706 | as_bad (_("bad memory operand `%s'"), op_string); | |
10707 | return 0; | |
10708 | } | |
47926f60 | 10709 | /* Handle case of %es:*foo. */ |
24eab124 AM |
10710 | if (*op_string == ABSOLUTE_PREFIX) |
10711 | { | |
10712 | ++op_string; | |
10713 | if (is_space_char (*op_string)) | |
10714 | ++op_string; | |
6f2f06be | 10715 | i.jumpabsolute = TRUE; |
24eab124 AM |
10716 | } |
10717 | goto do_memory_reference; | |
10718 | } | |
43234a1e L |
10719 | |
10720 | /* Handle vector operations. */ | |
10721 | if (*op_string == '{') | |
10722 | { | |
10723 | op_string = check_VecOperations (op_string, NULL); | |
10724 | if (op_string == NULL) | |
10725 | return 0; | |
10726 | } | |
10727 | ||
24eab124 AM |
10728 | if (*op_string) |
10729 | { | |
d0b47220 | 10730 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
10731 | return 0; |
10732 | } | |
40fb9820 L |
10733 | temp = r->reg_type; |
10734 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
10735 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10736 | temp); | |
7d5e4556 | 10737 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 10738 | i.op[this_operand].regs = r; |
24eab124 AM |
10739 | i.reg_operands++; |
10740 | } | |
af6bdddf AM |
10741 | else if (*op_string == REGISTER_PREFIX) |
10742 | { | |
10743 | as_bad (_("bad register name `%s'"), op_string); | |
10744 | return 0; | |
10745 | } | |
24eab124 | 10746 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 10747 | { |
24eab124 | 10748 | ++op_string; |
6f2f06be | 10749 | if (i.jumpabsolute) |
24eab124 | 10750 | { |
d0b47220 | 10751 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
10752 | return 0; |
10753 | } | |
10754 | if (!i386_immediate (op_string)) | |
10755 | return 0; | |
10756 | } | |
43234a1e L |
10757 | else if (RC_SAE_immediate (operand_string)) |
10758 | { | |
10759 | /* If it is a RC or SAE immediate, do nothing. */ | |
10760 | ; | |
10761 | } | |
24eab124 AM |
10762 | else if (is_digit_char (*op_string) |
10763 | || is_identifier_char (*op_string) | |
d02603dc | 10764 | || *op_string == '"' |
e5cb08ac | 10765 | || *op_string == '(') |
24eab124 | 10766 | { |
47926f60 | 10767 | /* This is a memory reference of some sort. */ |
af6bdddf | 10768 | char *base_string; |
252b5132 | 10769 | |
47926f60 | 10770 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
10771 | char *displacement_string_start; |
10772 | char *displacement_string_end; | |
43234a1e | 10773 | char *vop_start; |
252b5132 | 10774 | |
24eab124 | 10775 | do_memory_reference: |
8325cc63 JB |
10776 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
10777 | return 0; | |
24eab124 | 10778 | if ((i.mem_operands == 1 |
40fb9820 | 10779 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
10780 | || i.mem_operands == 2) |
10781 | { | |
10782 | as_bad (_("too many memory references for `%s'"), | |
10783 | current_templates->start->name); | |
10784 | return 0; | |
10785 | } | |
252b5132 | 10786 | |
24eab124 AM |
10787 | /* Check for base index form. We detect the base index form by |
10788 | looking for an ')' at the end of the operand, searching | |
10789 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
10790 | after the '('. */ | |
af6bdddf | 10791 | base_string = op_string + strlen (op_string); |
c3332e24 | 10792 | |
43234a1e L |
10793 | /* Handle vector operations. */ |
10794 | vop_start = strchr (op_string, '{'); | |
10795 | if (vop_start && vop_start < base_string) | |
10796 | { | |
10797 | if (check_VecOperations (vop_start, base_string) == NULL) | |
10798 | return 0; | |
10799 | base_string = vop_start; | |
10800 | } | |
10801 | ||
af6bdddf AM |
10802 | --base_string; |
10803 | if (is_space_char (*base_string)) | |
10804 | --base_string; | |
252b5132 | 10805 | |
47926f60 | 10806 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
10807 | displacement_string_start = op_string; |
10808 | displacement_string_end = base_string + 1; | |
252b5132 | 10809 | |
24eab124 AM |
10810 | if (*base_string == ')') |
10811 | { | |
af6bdddf | 10812 | char *temp_string; |
24eab124 AM |
10813 | unsigned int parens_balanced = 1; |
10814 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 10815 | equal, so this loop will not be infinite. */ |
24eab124 AM |
10816 | do |
10817 | { | |
10818 | base_string--; | |
10819 | if (*base_string == ')') | |
10820 | parens_balanced++; | |
10821 | if (*base_string == '(') | |
10822 | parens_balanced--; | |
10823 | } | |
10824 | while (parens_balanced); | |
c3332e24 | 10825 | |
af6bdddf | 10826 | temp_string = base_string; |
c3332e24 | 10827 | |
24eab124 | 10828 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
10829 | ++base_string; |
10830 | if (is_space_char (*base_string)) | |
24eab124 | 10831 | ++base_string; |
252b5132 | 10832 | |
af6bdddf | 10833 | if (*base_string == ',' |
4eed87de AM |
10834 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10835 | != NULL)) | |
252b5132 | 10836 | { |
af6bdddf | 10837 | displacement_string_end = temp_string; |
252b5132 | 10838 | |
40fb9820 | 10839 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10840 | |
af6bdddf | 10841 | if (i.base_reg) |
24eab124 | 10842 | { |
24eab124 AM |
10843 | base_string = end_op; |
10844 | if (is_space_char (*base_string)) | |
10845 | ++base_string; | |
af6bdddf AM |
10846 | } |
10847 | ||
10848 | /* There may be an index reg or scale factor here. */ | |
10849 | if (*base_string == ',') | |
10850 | { | |
10851 | ++base_string; | |
10852 | if (is_space_char (*base_string)) | |
10853 | ++base_string; | |
10854 | ||
4eed87de AM |
10855 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10856 | != NULL) | |
24eab124 | 10857 | { |
af6bdddf | 10858 | base_string = end_op; |
24eab124 AM |
10859 | if (is_space_char (*base_string)) |
10860 | ++base_string; | |
af6bdddf AM |
10861 | if (*base_string == ',') |
10862 | { | |
10863 | ++base_string; | |
10864 | if (is_space_char (*base_string)) | |
10865 | ++base_string; | |
10866 | } | |
e5cb08ac | 10867 | else if (*base_string != ')') |
af6bdddf | 10868 | { |
4eed87de AM |
10869 | as_bad (_("expecting `,' or `)' " |
10870 | "after index register in `%s'"), | |
af6bdddf AM |
10871 | operand_string); |
10872 | return 0; | |
10873 | } | |
24eab124 | 10874 | } |
af6bdddf | 10875 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10876 | { |
f76bf5e0 L |
10877 | end_op = strchr (base_string, ','); |
10878 | if (end_op) | |
10879 | *end_op = '\0'; | |
af6bdddf | 10880 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10881 | return 0; |
10882 | } | |
252b5132 | 10883 | |
47926f60 | 10884 | /* Check for scale factor. */ |
551c1ca1 | 10885 | if (*base_string != ')') |
af6bdddf | 10886 | { |
551c1ca1 AM |
10887 | char *end_scale = i386_scale (base_string); |
10888 | ||
10889 | if (!end_scale) | |
af6bdddf | 10890 | return 0; |
24eab124 | 10891 | |
551c1ca1 | 10892 | base_string = end_scale; |
af6bdddf AM |
10893 | if (is_space_char (*base_string)) |
10894 | ++base_string; | |
10895 | if (*base_string != ')') | |
10896 | { | |
4eed87de AM |
10897 | as_bad (_("expecting `)' " |
10898 | "after scale factor in `%s'"), | |
af6bdddf AM |
10899 | operand_string); |
10900 | return 0; | |
10901 | } | |
10902 | } | |
10903 | else if (!i.index_reg) | |
24eab124 | 10904 | { |
4eed87de AM |
10905 | as_bad (_("expecting index register or scale factor " |
10906 | "after `,'; got '%c'"), | |
af6bdddf | 10907 | *base_string); |
24eab124 AM |
10908 | return 0; |
10909 | } | |
10910 | } | |
af6bdddf | 10911 | else if (*base_string != ')') |
24eab124 | 10912 | { |
4eed87de AM |
10913 | as_bad (_("expecting `,' or `)' " |
10914 | "after base register in `%s'"), | |
af6bdddf | 10915 | operand_string); |
24eab124 AM |
10916 | return 0; |
10917 | } | |
c3332e24 | 10918 | } |
af6bdddf | 10919 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10920 | { |
f76bf5e0 L |
10921 | end_op = strchr (base_string, ','); |
10922 | if (end_op) | |
10923 | *end_op = '\0'; | |
af6bdddf | 10924 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10925 | return 0; |
c3332e24 | 10926 | } |
24eab124 AM |
10927 | } |
10928 | ||
10929 | /* If there's an expression beginning the operand, parse it, | |
10930 | assuming displacement_string_start and | |
10931 | displacement_string_end are meaningful. */ | |
10932 | if (displacement_string_start != displacement_string_end) | |
10933 | { | |
10934 | if (!i386_displacement (displacement_string_start, | |
10935 | displacement_string_end)) | |
10936 | return 0; | |
10937 | } | |
10938 | ||
10939 | /* Special case for (%dx) while doing input/output op. */ | |
10940 | if (i.base_reg | |
75e5731b JB |
10941 | && i.base_reg->reg_type.bitfield.instance == RegD |
10942 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
10943 | && i.index_reg == 0 |
10944 | && i.log2_scale_factor == 0 | |
10945 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10946 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10947 | { |
2fb5be8d | 10948 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10949 | return 1; |
10950 | } | |
10951 | ||
eecb386c AM |
10952 | if (i386_index_check (operand_string) == 0) |
10953 | return 0; | |
c48dadc9 | 10954 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10955 | if (i.mem_operands == 0) |
10956 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10957 | i.mem_operands++; |
10958 | } | |
10959 | else | |
ce8a8b2f AM |
10960 | { |
10961 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10962 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10963 | output_invalid (*op_string), | |
10964 | this_operand + 1, | |
10965 | op_string); | |
10966 | return 0; | |
10967 | } | |
47926f60 | 10968 | return 1; /* Normal return. */ |
252b5132 RH |
10969 | } |
10970 | \f | |
fa94de6b RM |
10971 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10972 | that an rs_machine_dependent frag may reach. */ | |
10973 | ||
10974 | unsigned int | |
10975 | i386_frag_max_var (fragS *frag) | |
10976 | { | |
10977 | /* The only relaxable frags are for jumps. | |
10978 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10979 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10980 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10981 | } | |
10982 | ||
b084df0b L |
10983 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10984 | static int | |
8dcea932 | 10985 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
10986 | { |
10987 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
10988 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
10989 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
10990 | return 0; | |
10991 | ||
10992 | if (!S_IS_EXTERNAL (fr_symbol)) | |
10993 | /* Symbol may be weak or local. */ | |
10994 | return !S_IS_WEAK (fr_symbol); | |
10995 | ||
8dcea932 L |
10996 | /* Global symbols with non-default visibility can't be preempted. */ |
10997 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
10998 | return 1; | |
10999 | ||
11000 | if (fr_var != NO_RELOC) | |
11001 | switch ((enum bfd_reloc_code_real) fr_var) | |
11002 | { | |
11003 | case BFD_RELOC_386_PLT32: | |
11004 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 11005 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
11006 | return 0; |
11007 | default: | |
11008 | abort (); | |
11009 | } | |
11010 | ||
b084df0b L |
11011 | /* Global symbols with default visibility in a shared library may be |
11012 | preempted by another definition. */ | |
8dcea932 | 11013 | return !shared; |
b084df0b L |
11014 | } |
11015 | #endif | |
11016 | ||
79d72f45 HL |
11017 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
11018 | Note also work for Skylake and Cascadelake. | |
11019 | --------------------------------------------------------------------- | |
11020 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
11021 | | ------ | ----------- | ------- | -------- | | |
11022 | | Jo | N | N | Y | | |
11023 | | Jno | N | N | Y | | |
11024 | | Jc/Jb | Y | N | Y | | |
11025 | | Jae/Jnb | Y | N | Y | | |
11026 | | Je/Jz | Y | Y | Y | | |
11027 | | Jne/Jnz | Y | Y | Y | | |
11028 | | Jna/Jbe | Y | N | Y | | |
11029 | | Ja/Jnbe | Y | N | Y | | |
11030 | | Js | N | N | Y | | |
11031 | | Jns | N | N | Y | | |
11032 | | Jp/Jpe | N | N | Y | | |
11033 | | Jnp/Jpo | N | N | Y | | |
11034 | | Jl/Jnge | Y | Y | Y | | |
11035 | | Jge/Jnl | Y | Y | Y | | |
11036 | | Jle/Jng | Y | Y | Y | | |
11037 | | Jg/Jnle | Y | Y | Y | | |
11038 | --------------------------------------------------------------------- */ | |
11039 | static int | |
11040 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
11041 | { | |
11042 | if (mf_cmp == mf_cmp_alu_cmp) | |
11043 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
11044 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
11045 | if (mf_cmp == mf_cmp_incdec) | |
11046 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
11047 | || mf_jcc == mf_jcc_jle); | |
11048 | if (mf_cmp == mf_cmp_test_and) | |
11049 | return 1; | |
11050 | return 0; | |
11051 | } | |
11052 | ||
e379e5f3 L |
11053 | /* Return the next non-empty frag. */ |
11054 | ||
11055 | static fragS * | |
11056 | i386_next_non_empty_frag (fragS *fragP) | |
11057 | { | |
11058 | /* There may be a frag with a ".fill 0" when there is no room in | |
11059 | the current frag for frag_grow in output_insn. */ | |
11060 | for (fragP = fragP->fr_next; | |
11061 | (fragP != NULL | |
11062 | && fragP->fr_type == rs_fill | |
11063 | && fragP->fr_fix == 0); | |
11064 | fragP = fragP->fr_next) | |
11065 | ; | |
11066 | return fragP; | |
11067 | } | |
11068 | ||
11069 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
11070 | ||
11071 | static fragS * | |
79d72f45 | 11072 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 11073 | { |
79d72f45 HL |
11074 | fragS *branch_fragP; |
11075 | if (!pad_fragP) | |
e379e5f3 L |
11076 | return NULL; |
11077 | ||
79d72f45 HL |
11078 | if (pad_fragP->fr_type == rs_machine_dependent |
11079 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
11080 | == BRANCH_PADDING)) |
11081 | { | |
79d72f45 HL |
11082 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
11083 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 11084 | return NULL; |
79d72f45 HL |
11085 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
11086 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
11087 | pad_fragP->tc_frag_data.mf_type)) | |
11088 | return branch_fragP; | |
e379e5f3 L |
11089 | } |
11090 | ||
11091 | return NULL; | |
11092 | } | |
11093 | ||
11094 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
11095 | ||
11096 | static void | |
11097 | i386_classify_machine_dependent_frag (fragS *fragP) | |
11098 | { | |
11099 | fragS *cmp_fragP; | |
11100 | fragS *pad_fragP; | |
11101 | fragS *branch_fragP; | |
11102 | fragS *next_fragP; | |
11103 | unsigned int max_prefix_length; | |
11104 | ||
11105 | if (fragP->tc_frag_data.classified) | |
11106 | return; | |
11107 | ||
11108 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
11109 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
11110 | for (next_fragP = fragP; | |
11111 | next_fragP != NULL; | |
11112 | next_fragP = next_fragP->fr_next) | |
11113 | { | |
11114 | next_fragP->tc_frag_data.classified = 1; | |
11115 | if (next_fragP->fr_type == rs_machine_dependent) | |
11116 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
11117 | { | |
11118 | case BRANCH_PADDING: | |
11119 | /* The BRANCH_PADDING frag must be followed by a branch | |
11120 | frag. */ | |
11121 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
11122 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11123 | break; | |
11124 | case FUSED_JCC_PADDING: | |
11125 | /* Check if this is a fused jcc: | |
11126 | FUSED_JCC_PADDING | |
11127 | CMP like instruction | |
11128 | BRANCH_PADDING | |
11129 | COND_JUMP | |
11130 | */ | |
11131 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
11132 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 11133 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
11134 | if (branch_fragP) |
11135 | { | |
11136 | /* The BRANCH_PADDING frag is merged with the | |
11137 | FUSED_JCC_PADDING frag. */ | |
11138 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11139 | /* CMP like instruction size. */ | |
11140 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
11141 | frag_wane (pad_fragP); | |
11142 | /* Skip to branch_fragP. */ | |
11143 | next_fragP = branch_fragP; | |
11144 | } | |
11145 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
11146 | { | |
11147 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
11148 | a fused jcc. */ | |
11149 | next_fragP->fr_subtype | |
11150 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
11151 | next_fragP->tc_frag_data.max_bytes | |
11152 | = next_fragP->tc_frag_data.max_prefix_length; | |
11153 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
11154 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
11155 | } | |
11156 | else | |
11157 | frag_wane (next_fragP); | |
11158 | break; | |
11159 | } | |
11160 | } | |
11161 | ||
11162 | /* Stop if there is no BRANCH_PREFIX. */ | |
11163 | if (!align_branch_prefix_size) | |
11164 | return; | |
11165 | ||
11166 | /* Scan for BRANCH_PREFIX. */ | |
11167 | for (; fragP != NULL; fragP = fragP->fr_next) | |
11168 | { | |
11169 | if (fragP->fr_type != rs_machine_dependent | |
11170 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11171 | != BRANCH_PREFIX)) | |
11172 | continue; | |
11173 | ||
11174 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
11175 | COND_JUMP_PREFIX. */ | |
11176 | max_prefix_length = 0; | |
11177 | for (next_fragP = fragP; | |
11178 | next_fragP != NULL; | |
11179 | next_fragP = next_fragP->fr_next) | |
11180 | { | |
11181 | if (next_fragP->fr_type == rs_fill) | |
11182 | /* Skip rs_fill frags. */ | |
11183 | continue; | |
11184 | else if (next_fragP->fr_type != rs_machine_dependent) | |
11185 | /* Stop for all other frags. */ | |
11186 | break; | |
11187 | ||
11188 | /* rs_machine_dependent frags. */ | |
11189 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11190 | == BRANCH_PREFIX) | |
11191 | { | |
11192 | /* Count BRANCH_PREFIX frags. */ | |
11193 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
11194 | { | |
11195 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
11196 | frag_wane (next_fragP); | |
11197 | } | |
11198 | else | |
11199 | max_prefix_length | |
11200 | += next_fragP->tc_frag_data.max_bytes; | |
11201 | } | |
11202 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11203 | == BRANCH_PADDING) | |
11204 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11205 | == FUSED_JCC_PADDING)) | |
11206 | { | |
11207 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
11208 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
11209 | break; | |
11210 | } | |
11211 | else | |
11212 | /* Stop for other rs_machine_dependent frags. */ | |
11213 | break; | |
11214 | } | |
11215 | ||
11216 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
11217 | ||
11218 | /* Skip to the next frag. */ | |
11219 | fragP = next_fragP; | |
11220 | } | |
11221 | } | |
11222 | ||
11223 | /* Compute padding size for | |
11224 | ||
11225 | FUSED_JCC_PADDING | |
11226 | CMP like instruction | |
11227 | BRANCH_PADDING | |
11228 | COND_JUMP/UNCOND_JUMP | |
11229 | ||
11230 | or | |
11231 | ||
11232 | BRANCH_PADDING | |
11233 | COND_JUMP/UNCOND_JUMP | |
11234 | */ | |
11235 | ||
11236 | static int | |
11237 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
11238 | { | |
11239 | unsigned int offset, size, padding_size; | |
11240 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
11241 | ||
11242 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
11243 | if (!address) | |
11244 | address = fragP->fr_address; | |
11245 | address += fragP->fr_fix; | |
11246 | ||
11247 | /* CMP like instrunction size. */ | |
11248 | size = fragP->tc_frag_data.cmp_size; | |
11249 | ||
11250 | /* The base size of the branch frag. */ | |
11251 | size += branch_fragP->fr_fix; | |
11252 | ||
11253 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
11254 | branch frag. */ | |
11255 | if (branch_fragP->fr_type == rs_machine_dependent) | |
11256 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
11257 | ||
11258 | /* Check if branch is within boundary and doesn't end at the last | |
11259 | byte. */ | |
11260 | offset = address & ((1U << align_branch_power) - 1); | |
11261 | if ((offset + size) >= (1U << align_branch_power)) | |
11262 | /* Padding needed to avoid crossing boundary. */ | |
11263 | padding_size = (1U << align_branch_power) - offset; | |
11264 | else | |
11265 | /* No padding needed. */ | |
11266 | padding_size = 0; | |
11267 | ||
11268 | /* The return value may be saved in tc_frag_data.length which is | |
11269 | unsigned byte. */ | |
11270 | if (!fits_in_unsigned_byte (padding_size)) | |
11271 | abort (); | |
11272 | ||
11273 | return padding_size; | |
11274 | } | |
11275 | ||
11276 | /* i386_generic_table_relax_frag() | |
11277 | ||
11278 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
11279 | grow/shrink padding to align branch frags. Hand others to | |
11280 | relax_frag(). */ | |
11281 | ||
11282 | long | |
11283 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
11284 | { | |
11285 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
11286 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11287 | { | |
11288 | long padding_size = i386_branch_padding_size (fragP, 0); | |
11289 | long grow = padding_size - fragP->tc_frag_data.length; | |
11290 | ||
11291 | /* When the BRANCH_PREFIX frag is used, the computed address | |
11292 | must match the actual address and there should be no padding. */ | |
11293 | if (fragP->tc_frag_data.padding_address | |
11294 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
11295 | || padding_size)) | |
11296 | abort (); | |
11297 | ||
11298 | /* Update the padding size. */ | |
11299 | if (grow) | |
11300 | fragP->tc_frag_data.length = padding_size; | |
11301 | ||
11302 | return grow; | |
11303 | } | |
11304 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11305 | { | |
11306 | fragS *padding_fragP, *next_fragP; | |
11307 | long padding_size, left_size, last_size; | |
11308 | ||
11309 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11310 | if (!padding_fragP) | |
11311 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
11312 | return (fragP->tc_frag_data.length | |
11313 | - fragP->tc_frag_data.last_length); | |
11314 | ||
11315 | /* Compute the relative address of the padding frag in the very | |
11316 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
11317 | if (!fragP->tc_frag_data.padding_address) | |
11318 | fragP->tc_frag_data.padding_address | |
11319 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
11320 | ||
11321 | /* First update the last length from the previous interation. */ | |
11322 | left_size = fragP->tc_frag_data.prefix_length; | |
11323 | for (next_fragP = fragP; | |
11324 | next_fragP != padding_fragP; | |
11325 | next_fragP = next_fragP->fr_next) | |
11326 | if (next_fragP->fr_type == rs_machine_dependent | |
11327 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11328 | == BRANCH_PREFIX)) | |
11329 | { | |
11330 | if (left_size) | |
11331 | { | |
11332 | int max = next_fragP->tc_frag_data.max_bytes; | |
11333 | if (max) | |
11334 | { | |
11335 | int size; | |
11336 | if (max > left_size) | |
11337 | size = left_size; | |
11338 | else | |
11339 | size = max; | |
11340 | left_size -= size; | |
11341 | next_fragP->tc_frag_data.last_length = size; | |
11342 | } | |
11343 | } | |
11344 | else | |
11345 | next_fragP->tc_frag_data.last_length = 0; | |
11346 | } | |
11347 | ||
11348 | /* Check the padding size for the padding frag. */ | |
11349 | padding_size = i386_branch_padding_size | |
11350 | (padding_fragP, (fragP->fr_address | |
11351 | + fragP->tc_frag_data.padding_address)); | |
11352 | ||
11353 | last_size = fragP->tc_frag_data.prefix_length; | |
11354 | /* Check if there is change from the last interation. */ | |
11355 | if (padding_size == last_size) | |
11356 | { | |
11357 | /* Update the expected address of the padding frag. */ | |
11358 | padding_fragP->tc_frag_data.padding_address | |
11359 | = (fragP->fr_address + padding_size | |
11360 | + fragP->tc_frag_data.padding_address); | |
11361 | return 0; | |
11362 | } | |
11363 | ||
11364 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
11365 | { | |
11366 | /* No padding if there is no sufficient room. Clear the | |
11367 | expected address of the padding frag. */ | |
11368 | padding_fragP->tc_frag_data.padding_address = 0; | |
11369 | padding_size = 0; | |
11370 | } | |
11371 | else | |
11372 | /* Store the expected address of the padding frag. */ | |
11373 | padding_fragP->tc_frag_data.padding_address | |
11374 | = (fragP->fr_address + padding_size | |
11375 | + fragP->tc_frag_data.padding_address); | |
11376 | ||
11377 | fragP->tc_frag_data.prefix_length = padding_size; | |
11378 | ||
11379 | /* Update the length for the current interation. */ | |
11380 | left_size = padding_size; | |
11381 | for (next_fragP = fragP; | |
11382 | next_fragP != padding_fragP; | |
11383 | next_fragP = next_fragP->fr_next) | |
11384 | if (next_fragP->fr_type == rs_machine_dependent | |
11385 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11386 | == BRANCH_PREFIX)) | |
11387 | { | |
11388 | if (left_size) | |
11389 | { | |
11390 | int max = next_fragP->tc_frag_data.max_bytes; | |
11391 | if (max) | |
11392 | { | |
11393 | int size; | |
11394 | if (max > left_size) | |
11395 | size = left_size; | |
11396 | else | |
11397 | size = max; | |
11398 | left_size -= size; | |
11399 | next_fragP->tc_frag_data.length = size; | |
11400 | } | |
11401 | } | |
11402 | else | |
11403 | next_fragP->tc_frag_data.length = 0; | |
11404 | } | |
11405 | ||
11406 | return (fragP->tc_frag_data.length | |
11407 | - fragP->tc_frag_data.last_length); | |
11408 | } | |
11409 | return relax_frag (segment, fragP, stretch); | |
11410 | } | |
11411 | ||
ee7fcc42 AM |
11412 | /* md_estimate_size_before_relax() |
11413 | ||
11414 | Called just before relax() for rs_machine_dependent frags. The x86 | |
11415 | assembler uses these frags to handle variable size jump | |
11416 | instructions. | |
11417 | ||
11418 | Any symbol that is now undefined will not become defined. | |
11419 | Return the correct fr_subtype in the frag. | |
11420 | Return the initial "guess for variable size of frag" to caller. | |
11421 | The guess is actually the growth beyond the fixed part. Whatever | |
11422 | we do to grow the fixed or variable part contributes to our | |
11423 | returned value. */ | |
11424 | ||
252b5132 | 11425 | int |
7016a5d5 | 11426 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 11427 | { |
e379e5f3 L |
11428 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11429 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
11430 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11431 | { | |
11432 | i386_classify_machine_dependent_frag (fragP); | |
11433 | return fragP->tc_frag_data.length; | |
11434 | } | |
11435 | ||
252b5132 | 11436 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
11437 | check for un-relaxable symbols. On an ELF system, we can't relax |
11438 | an externally visible symbol, because it may be overridden by a | |
11439 | shared library. */ | |
11440 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 11441 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11442 | || (IS_ELF |
8dcea932 L |
11443 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
11444 | fragP->fr_var)) | |
fbeb56a4 DK |
11445 | #endif |
11446 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 11447 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 11448 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
11449 | #endif |
11450 | ) | |
252b5132 | 11451 | { |
b98ef147 AM |
11452 | /* Symbol is undefined in this segment, or we need to keep a |
11453 | reloc so that weak symbols can be overridden. */ | |
11454 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 11455 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
11456 | unsigned char *opcode; |
11457 | int old_fr_fix; | |
f6af82bd | 11458 | |
ee7fcc42 | 11459 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 11460 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 11461 | else if (size == 2) |
f6af82bd | 11462 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
11463 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11464 | else if (need_plt32_p (fragP->fr_symbol)) | |
11465 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
11466 | #endif | |
f6af82bd AM |
11467 | else |
11468 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 11469 | |
ee7fcc42 AM |
11470 | old_fr_fix = fragP->fr_fix; |
11471 | opcode = (unsigned char *) fragP->fr_opcode; | |
11472 | ||
fddf5b5b | 11473 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 11474 | { |
fddf5b5b AM |
11475 | case UNCOND_JUMP: |
11476 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 11477 | opcode[0] = 0xe9; |
252b5132 | 11478 | fragP->fr_fix += size; |
062cd5e7 AS |
11479 | fix_new (fragP, old_fr_fix, size, |
11480 | fragP->fr_symbol, | |
11481 | fragP->fr_offset, 1, | |
11482 | reloc_type); | |
252b5132 RH |
11483 | break; |
11484 | ||
fddf5b5b | 11485 | case COND_JUMP86: |
412167cb AM |
11486 | if (size == 2 |
11487 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
11488 | { |
11489 | /* Negate the condition, and branch past an | |
11490 | unconditional jump. */ | |
11491 | opcode[0] ^= 1; | |
11492 | opcode[1] = 3; | |
11493 | /* Insert an unconditional jump. */ | |
11494 | opcode[2] = 0xe9; | |
11495 | /* We added two extra opcode bytes, and have a two byte | |
11496 | offset. */ | |
11497 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
11498 | fix_new (fragP, old_fr_fix + 2, 2, |
11499 | fragP->fr_symbol, | |
11500 | fragP->fr_offset, 1, | |
11501 | reloc_type); | |
fddf5b5b AM |
11502 | break; |
11503 | } | |
11504 | /* Fall through. */ | |
11505 | ||
11506 | case COND_JUMP: | |
412167cb AM |
11507 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
11508 | { | |
3e02c1cc AM |
11509 | fixS *fixP; |
11510 | ||
412167cb | 11511 | fragP->fr_fix += 1; |
3e02c1cc AM |
11512 | fixP = fix_new (fragP, old_fr_fix, 1, |
11513 | fragP->fr_symbol, | |
11514 | fragP->fr_offset, 1, | |
11515 | BFD_RELOC_8_PCREL); | |
11516 | fixP->fx_signed = 1; | |
412167cb AM |
11517 | break; |
11518 | } | |
93c2a809 | 11519 | |
24eab124 | 11520 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 11521 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 11522 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 11523 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
11524 | /* We've added an opcode byte. */ |
11525 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
11526 | fix_new (fragP, old_fr_fix + 1, size, |
11527 | fragP->fr_symbol, | |
11528 | fragP->fr_offset, 1, | |
11529 | reloc_type); | |
252b5132 | 11530 | break; |
fddf5b5b AM |
11531 | |
11532 | default: | |
11533 | BAD_CASE (fragP->fr_subtype); | |
11534 | break; | |
252b5132 RH |
11535 | } |
11536 | frag_wane (fragP); | |
ee7fcc42 | 11537 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 11538 | } |
93c2a809 | 11539 | |
93c2a809 AM |
11540 | /* Guess size depending on current relax state. Initially the relax |
11541 | state will correspond to a short jump and we return 1, because | |
11542 | the variable part of the frag (the branch offset) is one byte | |
11543 | long. However, we can relax a section more than once and in that | |
11544 | case we must either set fr_subtype back to the unrelaxed state, | |
11545 | or return the value for the appropriate branch. */ | |
11546 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
11547 | } |
11548 | ||
47926f60 KH |
11549 | /* Called after relax() is finished. |
11550 | ||
11551 | In: Address of frag. | |
11552 | fr_type == rs_machine_dependent. | |
11553 | fr_subtype is what the address relaxed to. | |
11554 | ||
11555 | Out: Any fixSs and constants are set up. | |
11556 | Caller will turn frag into a ".space 0". */ | |
11557 | ||
252b5132 | 11558 | void |
7016a5d5 TG |
11559 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
11560 | fragS *fragP) | |
252b5132 | 11561 | { |
29b0f896 | 11562 | unsigned char *opcode; |
252b5132 | 11563 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
11564 | offsetT target_address; |
11565 | offsetT opcode_address; | |
252b5132 | 11566 | unsigned int extension = 0; |
847f7ad4 | 11567 | offsetT displacement_from_opcode_start; |
252b5132 | 11568 | |
e379e5f3 L |
11569 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11570 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
11571 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11572 | { | |
11573 | /* Generate nop padding. */ | |
11574 | unsigned int size = fragP->tc_frag_data.length; | |
11575 | if (size) | |
11576 | { | |
11577 | if (size > fragP->tc_frag_data.max_bytes) | |
11578 | abort (); | |
11579 | ||
11580 | if (flag_debug) | |
11581 | { | |
11582 | const char *msg; | |
11583 | const char *branch = "branch"; | |
11584 | const char *prefix = ""; | |
11585 | fragS *padding_fragP; | |
11586 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11587 | == BRANCH_PREFIX) | |
11588 | { | |
11589 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11590 | switch (fragP->tc_frag_data.default_prefix) | |
11591 | { | |
11592 | default: | |
11593 | abort (); | |
11594 | break; | |
11595 | case CS_PREFIX_OPCODE: | |
11596 | prefix = " cs"; | |
11597 | break; | |
11598 | case DS_PREFIX_OPCODE: | |
11599 | prefix = " ds"; | |
11600 | break; | |
11601 | case ES_PREFIX_OPCODE: | |
11602 | prefix = " es"; | |
11603 | break; | |
11604 | case FS_PREFIX_OPCODE: | |
11605 | prefix = " fs"; | |
11606 | break; | |
11607 | case GS_PREFIX_OPCODE: | |
11608 | prefix = " gs"; | |
11609 | break; | |
11610 | case SS_PREFIX_OPCODE: | |
11611 | prefix = " ss"; | |
11612 | break; | |
11613 | } | |
11614 | if (padding_fragP) | |
11615 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
11616 | "%s within %d-byte boundary\n"); | |
11617 | else | |
11618 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
11619 | "align %s within %d-byte boundary\n"); | |
11620 | } | |
11621 | else | |
11622 | { | |
11623 | padding_fragP = fragP; | |
11624 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
11625 | "%s within %d-byte boundary\n"); | |
11626 | } | |
11627 | ||
11628 | if (padding_fragP) | |
11629 | switch (padding_fragP->tc_frag_data.branch_type) | |
11630 | { | |
11631 | case align_branch_jcc: | |
11632 | branch = "jcc"; | |
11633 | break; | |
11634 | case align_branch_fused: | |
11635 | branch = "fused jcc"; | |
11636 | break; | |
11637 | case align_branch_jmp: | |
11638 | branch = "jmp"; | |
11639 | break; | |
11640 | case align_branch_call: | |
11641 | branch = "call"; | |
11642 | break; | |
11643 | case align_branch_indirect: | |
11644 | branch = "indiret branch"; | |
11645 | break; | |
11646 | case align_branch_ret: | |
11647 | branch = "ret"; | |
11648 | break; | |
11649 | default: | |
11650 | break; | |
11651 | } | |
11652 | ||
11653 | fprintf (stdout, msg, | |
11654 | fragP->fr_file, fragP->fr_line, size, prefix, | |
11655 | (long long) fragP->fr_address, branch, | |
11656 | 1 << align_branch_power); | |
11657 | } | |
11658 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11659 | memset (fragP->fr_opcode, | |
11660 | fragP->tc_frag_data.default_prefix, size); | |
11661 | else | |
11662 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
11663 | size, 0); | |
11664 | fragP->fr_fix += size; | |
11665 | } | |
11666 | return; | |
11667 | } | |
11668 | ||
252b5132 RH |
11669 | opcode = (unsigned char *) fragP->fr_opcode; |
11670 | ||
47926f60 | 11671 | /* Address we want to reach in file space. */ |
252b5132 | 11672 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 11673 | |
47926f60 | 11674 | /* Address opcode resides at in file space. */ |
252b5132 RH |
11675 | opcode_address = fragP->fr_address + fragP->fr_fix; |
11676 | ||
47926f60 | 11677 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
11678 | displacement_from_opcode_start = target_address - opcode_address; |
11679 | ||
fddf5b5b | 11680 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 11681 | { |
47926f60 KH |
11682 | /* Don't have to change opcode. */ |
11683 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 11684 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
11685 | } |
11686 | else | |
11687 | { | |
11688 | if (no_cond_jump_promotion | |
11689 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
11690 | as_warn_where (fragP->fr_file, fragP->fr_line, |
11691 | _("long jump required")); | |
252b5132 | 11692 | |
fddf5b5b AM |
11693 | switch (fragP->fr_subtype) |
11694 | { | |
11695 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
11696 | extension = 4; /* 1 opcode + 4 displacement */ | |
11697 | opcode[0] = 0xe9; | |
11698 | where_to_put_displacement = &opcode[1]; | |
11699 | break; | |
252b5132 | 11700 | |
fddf5b5b AM |
11701 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
11702 | extension = 2; /* 1 opcode + 2 displacement */ | |
11703 | opcode[0] = 0xe9; | |
11704 | where_to_put_displacement = &opcode[1]; | |
11705 | break; | |
252b5132 | 11706 | |
fddf5b5b AM |
11707 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
11708 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
11709 | extension = 5; /* 2 opcode + 4 displacement */ | |
11710 | opcode[1] = opcode[0] + 0x10; | |
11711 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
11712 | where_to_put_displacement = &opcode[2]; | |
11713 | break; | |
252b5132 | 11714 | |
fddf5b5b AM |
11715 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
11716 | extension = 3; /* 2 opcode + 2 displacement */ | |
11717 | opcode[1] = opcode[0] + 0x10; | |
11718 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
11719 | where_to_put_displacement = &opcode[2]; | |
11720 | break; | |
252b5132 | 11721 | |
fddf5b5b AM |
11722 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
11723 | extension = 4; | |
11724 | opcode[0] ^= 1; | |
11725 | opcode[1] = 3; | |
11726 | opcode[2] = 0xe9; | |
11727 | where_to_put_displacement = &opcode[3]; | |
11728 | break; | |
11729 | ||
11730 | default: | |
11731 | BAD_CASE (fragP->fr_subtype); | |
11732 | break; | |
11733 | } | |
252b5132 | 11734 | } |
fddf5b5b | 11735 | |
7b81dfbb AJ |
11736 | /* If size if less then four we are sure that the operand fits, |
11737 | but if it's 4, then it could be that the displacement is larger | |
11738 | then -/+ 2GB. */ | |
11739 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
11740 | && object_64bit | |
11741 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
11742 | + ((addressT) 1 << 31)) |
11743 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
11744 | { |
11745 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
11746 | _("jump target out of range")); | |
11747 | /* Make us emit 0. */ | |
11748 | displacement_from_opcode_start = extension; | |
11749 | } | |
47926f60 | 11750 | /* Now put displacement after opcode. */ |
252b5132 RH |
11751 | md_number_to_chars ((char *) where_to_put_displacement, |
11752 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 11753 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
11754 | fragP->fr_fix += extension; |
11755 | } | |
11756 | \f | |
7016a5d5 | 11757 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
11758 | by our caller that we have all the info we need to fix it up. |
11759 | ||
7016a5d5 TG |
11760 | Parameter valP is the pointer to the value of the bits. |
11761 | ||
252b5132 RH |
11762 | On the 386, immediates, displacements, and data pointers are all in |
11763 | the same (little-endian) format, so we don't need to care about which | |
11764 | we are handling. */ | |
11765 | ||
94f592af | 11766 | void |
7016a5d5 | 11767 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11768 | { |
94f592af | 11769 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 11770 | valueT value = *valP; |
252b5132 | 11771 | |
f86103b7 | 11772 | #if !defined (TE_Mach) |
93382f6d AM |
11773 | if (fixP->fx_pcrel) |
11774 | { | |
11775 | switch (fixP->fx_r_type) | |
11776 | { | |
5865bb77 ILT |
11777 | default: |
11778 | break; | |
11779 | ||
d6ab8113 JB |
11780 | case BFD_RELOC_64: |
11781 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
11782 | break; | |
93382f6d | 11783 | case BFD_RELOC_32: |
ae8887b5 | 11784 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
11785 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
11786 | break; | |
11787 | case BFD_RELOC_16: | |
11788 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
11789 | break; | |
11790 | case BFD_RELOC_8: | |
11791 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
11792 | break; | |
11793 | } | |
11794 | } | |
252b5132 | 11795 | |
a161fe53 | 11796 | if (fixP->fx_addsy != NULL |
31312f95 | 11797 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 11798 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 11799 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 11800 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 11801 | && !use_rela_relocations) |
252b5132 | 11802 | { |
31312f95 AM |
11803 | /* This is a hack. There should be a better way to handle this. |
11804 | This covers for the fact that bfd_install_relocation will | |
11805 | subtract the current location (for partial_inplace, PC relative | |
11806 | relocations); see more below. */ | |
252b5132 | 11807 | #ifndef OBJ_AOUT |
718ddfc0 | 11808 | if (IS_ELF |
252b5132 RH |
11809 | #ifdef TE_PE |
11810 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
11811 | #endif | |
11812 | ) | |
11813 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
11814 | #endif | |
11815 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 11816 | if (IS_ELF) |
252b5132 | 11817 | { |
6539b54b | 11818 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 11819 | |
6539b54b | 11820 | if ((sym_seg == seg |
2f66722d | 11821 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 11822 | && sym_seg != absolute_section)) |
af65af87 | 11823 | && !generic_force_reloc (fixP)) |
2f66722d AM |
11824 | { |
11825 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
11826 | bfd_install_relocation subtracts them out again. I think |
11827 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
11828 | it. FIXME. */ |
11829 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
11830 | } | |
252b5132 RH |
11831 | } |
11832 | #endif | |
11833 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
11834 | /* For some reason, the PE format does not store a |
11835 | section address offset for a PC relative symbol. */ | |
11836 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 11837 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
11838 | value += md_pcrel_from (fixP); |
11839 | #endif | |
11840 | } | |
fbeb56a4 | 11841 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
11842 | if (fixP->fx_addsy != NULL |
11843 | && S_IS_WEAK (fixP->fx_addsy) | |
11844 | /* PR 16858: Do not modify weak function references. */ | |
11845 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 11846 | { |
296a8689 NC |
11847 | #if !defined (TE_PEP) |
11848 | /* For x86 PE weak function symbols are neither PC-relative | |
11849 | nor do they set S_IS_FUNCTION. So the only reliable way | |
11850 | to detect them is to check the flags of their containing | |
11851 | section. */ | |
11852 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
11853 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
11854 | ; | |
11855 | else | |
11856 | #endif | |
fbeb56a4 DK |
11857 | value -= S_GET_VALUE (fixP->fx_addsy); |
11858 | } | |
11859 | #endif | |
252b5132 RH |
11860 | |
11861 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 11862 | and we must not disappoint it. */ |
252b5132 | 11863 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11864 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
11865 | switch (fixP->fx_r_type) |
11866 | { | |
11867 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 11868 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
11869 | /* Make the jump instruction point to the address of the operand. |
11870 | At runtime we merely add the offset to the actual PLT entry. | |
11871 | NB: Subtract the offset size only for jump instructions. */ | |
11872 | if (fixP->fx_pcrel) | |
11873 | value = -4; | |
47926f60 | 11874 | break; |
31312f95 | 11875 | |
13ae64f3 JJ |
11876 | case BFD_RELOC_386_TLS_GD: |
11877 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 11878 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
11879 | case BFD_RELOC_386_TLS_IE: |
11880 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 11881 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
11882 | case BFD_RELOC_X86_64_TLSGD: |
11883 | case BFD_RELOC_X86_64_TLSLD: | |
11884 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 11885 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
11886 | value = 0; /* Fully resolved at runtime. No addend. */ |
11887 | /* Fallthrough */ | |
11888 | case BFD_RELOC_386_TLS_LE: | |
11889 | case BFD_RELOC_386_TLS_LDO_32: | |
11890 | case BFD_RELOC_386_TLS_LE_32: | |
11891 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11892 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 11893 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 11894 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
11895 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
11896 | break; | |
11897 | ||
67a4f2b7 AO |
11898 | case BFD_RELOC_386_TLS_DESC_CALL: |
11899 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
11900 | value = 0; /* Fully resolved at runtime. No addend. */ | |
11901 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11902 | fixP->fx_done = 0; | |
11903 | return; | |
11904 | ||
47926f60 KH |
11905 | case BFD_RELOC_VTABLE_INHERIT: |
11906 | case BFD_RELOC_VTABLE_ENTRY: | |
11907 | fixP->fx_done = 0; | |
94f592af | 11908 | return; |
47926f60 KH |
11909 | |
11910 | default: | |
11911 | break; | |
11912 | } | |
11913 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 11914 | *valP = value; |
f86103b7 | 11915 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 11916 | |
3e73aa7c | 11917 | /* Are we finished with this relocation now? */ |
c6682705 | 11918 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 11919 | fixP->fx_done = 1; |
fbeb56a4 DK |
11920 | #if defined (OBJ_COFF) && defined (TE_PE) |
11921 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
11922 | { | |
11923 | fixP->fx_done = 0; | |
11924 | /* Remember value for tc_gen_reloc. */ | |
11925 | fixP->fx_addnumber = value; | |
11926 | /* Clear out the frag for now. */ | |
11927 | value = 0; | |
11928 | } | |
11929 | #endif | |
3e73aa7c JH |
11930 | else if (use_rela_relocations) |
11931 | { | |
11932 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
11933 | /* Remember value for tc_gen_reloc. */ |
11934 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
11935 | value = 0; |
11936 | } | |
f86103b7 | 11937 | |
94f592af | 11938 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 11939 | } |
252b5132 | 11940 | \f |
6d4af3c2 | 11941 | const char * |
499ac353 | 11942 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11943 | { |
499ac353 NC |
11944 | /* This outputs the LITTLENUMs in REVERSE order; |
11945 | in accord with the bigendian 386. */ | |
11946 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
11947 | } |
11948 | \f | |
2d545b82 | 11949 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 11950 | |
252b5132 | 11951 | static char * |
e3bb37b5 | 11952 | output_invalid (int c) |
252b5132 | 11953 | { |
3882b010 | 11954 | if (ISPRINT (c)) |
f9f21a03 L |
11955 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
11956 | "'%c'", c); | |
252b5132 | 11957 | else |
f9f21a03 | 11958 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 11959 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
11960 | return output_invalid_buf; |
11961 | } | |
11962 | ||
af6bdddf | 11963 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
11964 | |
11965 | static const reg_entry * | |
4d1bb795 | 11966 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 11967 | { |
af6bdddf AM |
11968 | char *s = reg_string; |
11969 | char *p; | |
252b5132 RH |
11970 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
11971 | const reg_entry *r; | |
11972 | ||
11973 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
11974 | if (*s == REGISTER_PREFIX) | |
11975 | ++s; | |
11976 | ||
11977 | if (is_space_char (*s)) | |
11978 | ++s; | |
11979 | ||
11980 | p = reg_name_given; | |
af6bdddf | 11981 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
11982 | { |
11983 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
11984 | return (const reg_entry *) NULL; |
11985 | s++; | |
252b5132 RH |
11986 | } |
11987 | ||
6588847e DN |
11988 | /* For naked regs, make sure that we are not dealing with an identifier. |
11989 | This prevents confusing an identifier like `eax_var' with register | |
11990 | `eax'. */ | |
11991 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
11992 | return (const reg_entry *) NULL; | |
11993 | ||
af6bdddf | 11994 | *end_op = s; |
252b5132 RH |
11995 | |
11996 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
11997 | ||
5f47d35b | 11998 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 11999 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 12000 | { |
0e0eea78 JB |
12001 | if (!cpu_arch_flags.bitfield.cpu8087 |
12002 | && !cpu_arch_flags.bitfield.cpu287 | |
12003 | && !cpu_arch_flags.bitfield.cpu387) | |
12004 | return (const reg_entry *) NULL; | |
12005 | ||
5f47d35b AM |
12006 | if (is_space_char (*s)) |
12007 | ++s; | |
12008 | if (*s == '(') | |
12009 | { | |
af6bdddf | 12010 | ++s; |
5f47d35b AM |
12011 | if (is_space_char (*s)) |
12012 | ++s; | |
12013 | if (*s >= '0' && *s <= '7') | |
12014 | { | |
db557034 | 12015 | int fpr = *s - '0'; |
af6bdddf | 12016 | ++s; |
5f47d35b AM |
12017 | if (is_space_char (*s)) |
12018 | ++s; | |
12019 | if (*s == ')') | |
12020 | { | |
12021 | *end_op = s + 1; | |
1e9cc1c2 | 12022 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
12023 | know (r); |
12024 | return r + fpr; | |
5f47d35b | 12025 | } |
5f47d35b | 12026 | } |
47926f60 | 12027 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
12028 | return (const reg_entry *) NULL; |
12029 | } | |
12030 | } | |
12031 | ||
a60de03c JB |
12032 | if (r == NULL || allow_pseudo_reg) |
12033 | return r; | |
12034 | ||
0dfbf9d7 | 12035 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
12036 | return (const reg_entry *) NULL; |
12037 | ||
dc821c5f | 12038 | if ((r->reg_type.bitfield.dword |
00cee14f | 12039 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) |
4a5c67ed JB |
12040 | || r->reg_type.bitfield.class == RegCR |
12041 | || r->reg_type.bitfield.class == RegDR | |
12042 | || r->reg_type.bitfield.class == RegTR) | |
192dc9c6 JB |
12043 | && !cpu_arch_flags.bitfield.cpui386) |
12044 | return (const reg_entry *) NULL; | |
12045 | ||
3528c362 | 12046 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
12047 | return (const reg_entry *) NULL; |
12048 | ||
6e041cf4 JB |
12049 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
12050 | { | |
f74a6307 JB |
12051 | if (r->reg_type.bitfield.zmmword |
12052 | || r->reg_type.bitfield.class == RegMask) | |
6e041cf4 | 12053 | return (const reg_entry *) NULL; |
40f12533 | 12054 | |
6e041cf4 JB |
12055 | if (!cpu_arch_flags.bitfield.cpuavx) |
12056 | { | |
12057 | if (r->reg_type.bitfield.ymmword) | |
12058 | return (const reg_entry *) NULL; | |
1848e567 | 12059 | |
6e041cf4 JB |
12060 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
12061 | return (const reg_entry *) NULL; | |
12062 | } | |
12063 | } | |
43234a1e | 12064 | |
f74a6307 | 12065 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
1adf7f56 JB |
12066 | return (const reg_entry *) NULL; |
12067 | ||
db51cc60 | 12068 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 12069 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
12070 | return (const reg_entry *) NULL; |
12071 | ||
1d3f8286 JB |
12072 | /* Upper 16 vector registers are only available with VREX in 64bit |
12073 | mode, and require EVEX encoding. */ | |
12074 | if (r->reg_flags & RegVRex) | |
43234a1e | 12075 | { |
e951d5ca | 12076 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
12077 | || flag_code != CODE_64BIT) |
12078 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
12079 | |
12080 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
12081 | } |
12082 | ||
4787f4a5 | 12083 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
4a5c67ed | 12084 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) |
1ae00879 | 12085 | && flag_code != CODE_64BIT) |
20f0a1fc | 12086 | return (const reg_entry *) NULL; |
1ae00879 | 12087 | |
00cee14f JB |
12088 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat |
12089 | && !intel_syntax) | |
b7240065 JB |
12090 | return (const reg_entry *) NULL; |
12091 | ||
252b5132 RH |
12092 | return r; |
12093 | } | |
4d1bb795 JB |
12094 | |
12095 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
12096 | ||
12097 | static const reg_entry * | |
12098 | parse_register (char *reg_string, char **end_op) | |
12099 | { | |
12100 | const reg_entry *r; | |
12101 | ||
12102 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
12103 | r = parse_real_register (reg_string, end_op); | |
12104 | else | |
12105 | r = NULL; | |
12106 | if (!r) | |
12107 | { | |
12108 | char *save = input_line_pointer; | |
12109 | char c; | |
12110 | symbolS *symbolP; | |
12111 | ||
12112 | input_line_pointer = reg_string; | |
d02603dc | 12113 | c = get_symbol_name (®_string); |
4d1bb795 JB |
12114 | symbolP = symbol_find (reg_string); |
12115 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
12116 | { | |
12117 | const expressionS *e = symbol_get_value_expression (symbolP); | |
12118 | ||
0398aac5 | 12119 | know (e->X_op == O_register); |
4eed87de | 12120 | know (e->X_add_number >= 0 |
c3fe08fa | 12121 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 12122 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 12123 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 12124 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
12125 | *end_op = input_line_pointer; |
12126 | } | |
12127 | *input_line_pointer = c; | |
12128 | input_line_pointer = save; | |
12129 | } | |
12130 | return r; | |
12131 | } | |
12132 | ||
12133 | int | |
12134 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
12135 | { | |
12136 | const reg_entry *r; | |
12137 | char *end = input_line_pointer; | |
12138 | ||
12139 | *end = *nextcharP; | |
12140 | r = parse_register (name, &input_line_pointer); | |
12141 | if (r && end <= input_line_pointer) | |
12142 | { | |
12143 | *nextcharP = *input_line_pointer; | |
12144 | *input_line_pointer = 0; | |
12145 | e->X_op = O_register; | |
12146 | e->X_add_number = r - i386_regtab; | |
12147 | return 1; | |
12148 | } | |
12149 | input_line_pointer = end; | |
12150 | *end = 0; | |
ee86248c | 12151 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
12152 | } |
12153 | ||
12154 | void | |
12155 | md_operand (expressionS *e) | |
12156 | { | |
ee86248c JB |
12157 | char *end; |
12158 | const reg_entry *r; | |
4d1bb795 | 12159 | |
ee86248c JB |
12160 | switch (*input_line_pointer) |
12161 | { | |
12162 | case REGISTER_PREFIX: | |
12163 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
12164 | if (r) |
12165 | { | |
12166 | e->X_op = O_register; | |
12167 | e->X_add_number = r - i386_regtab; | |
12168 | input_line_pointer = end; | |
12169 | } | |
ee86248c JB |
12170 | break; |
12171 | ||
12172 | case '[': | |
9c2799c2 | 12173 | gas_assert (intel_syntax); |
ee86248c JB |
12174 | end = input_line_pointer++; |
12175 | expression (e); | |
12176 | if (*input_line_pointer == ']') | |
12177 | { | |
12178 | ++input_line_pointer; | |
12179 | e->X_op_symbol = make_expr_symbol (e); | |
12180 | e->X_add_symbol = NULL; | |
12181 | e->X_add_number = 0; | |
12182 | e->X_op = O_index; | |
12183 | } | |
12184 | else | |
12185 | { | |
12186 | e->X_op = O_absent; | |
12187 | input_line_pointer = end; | |
12188 | } | |
12189 | break; | |
4d1bb795 JB |
12190 | } |
12191 | } | |
12192 | ||
252b5132 | 12193 | \f |
4cc782b5 | 12194 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 12195 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 12196 | #else |
b6f8c7c4 | 12197 | const char *md_shortopts = "qnO::"; |
252b5132 | 12198 | #endif |
6e0b89ee | 12199 | |
3e73aa7c | 12200 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
12201 | #define OPTION_64 (OPTION_MD_BASE + 1) |
12202 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
12203 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
12204 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
12205 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
12206 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
12207 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
12208 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 12209 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 12210 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 12211 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
12212 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
12213 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
12214 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 12215 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
12216 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
12217 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 12218 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 12219 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 12220 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 12221 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
12222 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
12223 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 12224 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 12225 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 12226 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
12227 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
12228 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
12229 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 12230 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
b3b91714 | 12231 | |
99ad8390 NC |
12232 | struct option md_longopts[] = |
12233 | { | |
3e73aa7c | 12234 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 12235 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12236 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 12237 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
12238 | #endif |
12239 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 12240 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 12241 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 12242 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 12243 | #endif |
b3b91714 | 12244 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
12245 | {"march", required_argument, NULL, OPTION_MARCH}, |
12246 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
12247 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
12248 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
12249 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
12250 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 12251 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 12252 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 12253 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 12254 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 12255 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 12256 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
12257 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
12258 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
12259 | # if defined (TE_PE) || defined (TE_PEP) |
12260 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
12261 | #endif | |
d1982f93 | 12262 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 12263 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 12264 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 12265 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
12266 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
12267 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
12268 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 12269 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
5db04b09 L |
12270 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
12271 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
12272 | {NULL, no_argument, NULL, 0} |
12273 | }; | |
12274 | size_t md_longopts_size = sizeof (md_longopts); | |
12275 | ||
12276 | int | |
17b9d67d | 12277 | md_parse_option (int c, const char *arg) |
252b5132 | 12278 | { |
91d6fa6a | 12279 | unsigned int j; |
e379e5f3 | 12280 | char *arch, *next, *saved, *type; |
9103f4f4 | 12281 | |
252b5132 RH |
12282 | switch (c) |
12283 | { | |
12b55ccc L |
12284 | case 'n': |
12285 | optimize_align_code = 0; | |
12286 | break; | |
12287 | ||
a38cf1db AM |
12288 | case 'q': |
12289 | quiet_warnings = 1; | |
252b5132 RH |
12290 | break; |
12291 | ||
12292 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
12293 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
12294 | should be emitted or not. FIXME: Not implemented. */ | |
12295 | case 'Q': | |
d4693039 JB |
12296 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
12297 | return 0; | |
252b5132 RH |
12298 | break; |
12299 | ||
12300 | /* -V: SVR4 argument to print version ID. */ | |
12301 | case 'V': | |
12302 | print_version_id (); | |
12303 | break; | |
12304 | ||
a38cf1db AM |
12305 | /* -k: Ignore for FreeBSD compatibility. */ |
12306 | case 'k': | |
252b5132 | 12307 | break; |
4cc782b5 ILT |
12308 | |
12309 | case 's': | |
12310 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 12311 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 12312 | break; |
8dcea932 L |
12313 | |
12314 | case OPTION_MSHARED: | |
12315 | shared = 1; | |
12316 | break; | |
b4a3a7b4 L |
12317 | |
12318 | case OPTION_X86_USED_NOTE: | |
12319 | if (strcasecmp (arg, "yes") == 0) | |
12320 | x86_used_note = 1; | |
12321 | else if (strcasecmp (arg, "no") == 0) | |
12322 | x86_used_note = 0; | |
12323 | else | |
12324 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
12325 | break; | |
12326 | ||
12327 | ||
99ad8390 | 12328 | #endif |
321098a5 | 12329 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12330 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
12331 | case OPTION_64: |
12332 | { | |
12333 | const char **list, **l; | |
12334 | ||
3e73aa7c JH |
12335 | list = bfd_target_list (); |
12336 | for (l = list; *l != NULL; l++) | |
8620418b | 12337 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
12338 | || strcmp (*l, "coff-x86-64") == 0 |
12339 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
12340 | || strcmp (*l, "pei-x86-64") == 0 |
12341 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
12342 | { |
12343 | default_arch = "x86_64"; | |
12344 | break; | |
12345 | } | |
3e73aa7c | 12346 | if (*l == NULL) |
2b5d6a91 | 12347 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
12348 | free (list); |
12349 | } | |
12350 | break; | |
12351 | #endif | |
252b5132 | 12352 | |
351f65ca | 12353 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 12354 | case OPTION_X32: |
351f65ca L |
12355 | if (IS_ELF) |
12356 | { | |
12357 | const char **list, **l; | |
12358 | ||
12359 | list = bfd_target_list (); | |
12360 | for (l = list; *l != NULL; l++) | |
12361 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
12362 | { | |
12363 | default_arch = "x86_64:32"; | |
12364 | break; | |
12365 | } | |
12366 | if (*l == NULL) | |
2b5d6a91 | 12367 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
12368 | free (list); |
12369 | } | |
12370 | else | |
12371 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
12372 | break; | |
12373 | #endif | |
12374 | ||
6e0b89ee AM |
12375 | case OPTION_32: |
12376 | default_arch = "i386"; | |
12377 | break; | |
12378 | ||
b3b91714 AM |
12379 | case OPTION_DIVIDE: |
12380 | #ifdef SVR4_COMMENT_CHARS | |
12381 | { | |
12382 | char *n, *t; | |
12383 | const char *s; | |
12384 | ||
add39d23 | 12385 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
12386 | t = n; |
12387 | for (s = i386_comment_chars; *s != '\0'; s++) | |
12388 | if (*s != '/') | |
12389 | *t++ = *s; | |
12390 | *t = '\0'; | |
12391 | i386_comment_chars = n; | |
12392 | } | |
12393 | #endif | |
12394 | break; | |
12395 | ||
9103f4f4 | 12396 | case OPTION_MARCH: |
293f5f65 L |
12397 | saved = xstrdup (arg); |
12398 | arch = saved; | |
12399 | /* Allow -march=+nosse. */ | |
12400 | if (*arch == '+') | |
12401 | arch++; | |
6305a203 | 12402 | do |
9103f4f4 | 12403 | { |
6305a203 | 12404 | if (*arch == '.') |
2b5d6a91 | 12405 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12406 | next = strchr (arch, '+'); |
12407 | if (next) | |
12408 | *next++ = '\0'; | |
91d6fa6a | 12409 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12410 | { |
91d6fa6a | 12411 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 12412 | { |
6305a203 | 12413 | /* Processor. */ |
1ded5609 JB |
12414 | if (! cpu_arch[j].flags.bitfield.cpui386) |
12415 | continue; | |
12416 | ||
91d6fa6a | 12417 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 12418 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
12419 | cpu_arch_flags = cpu_arch[j].flags; |
12420 | cpu_arch_isa = cpu_arch[j].type; | |
12421 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
12422 | if (!cpu_arch_tune_set) |
12423 | { | |
12424 | cpu_arch_tune = cpu_arch_isa; | |
12425 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
12426 | } | |
12427 | break; | |
12428 | } | |
91d6fa6a NC |
12429 | else if (*cpu_arch [j].name == '.' |
12430 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 12431 | { |
33eaf5de | 12432 | /* ISA extension. */ |
6305a203 | 12433 | i386_cpu_flags flags; |
309d3373 | 12434 | |
293f5f65 L |
12435 | flags = cpu_flags_or (cpu_arch_flags, |
12436 | cpu_arch[j].flags); | |
81486035 | 12437 | |
5b64d091 | 12438 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
12439 | { |
12440 | if (cpu_sub_arch_name) | |
12441 | { | |
12442 | char *name = cpu_sub_arch_name; | |
12443 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 12444 | cpu_arch[j].name, |
1bf57e9f | 12445 | (const char *) NULL); |
6305a203 L |
12446 | free (name); |
12447 | } | |
12448 | else | |
91d6fa6a | 12449 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 12450 | cpu_arch_flags = flags; |
a586129e | 12451 | cpu_arch_isa_flags = flags; |
6305a203 | 12452 | } |
0089dace L |
12453 | else |
12454 | cpu_arch_isa_flags | |
12455 | = cpu_flags_or (cpu_arch_isa_flags, | |
12456 | cpu_arch[j].flags); | |
6305a203 | 12457 | break; |
ccc9c027 | 12458 | } |
9103f4f4 | 12459 | } |
6305a203 | 12460 | |
293f5f65 L |
12461 | if (j >= ARRAY_SIZE (cpu_arch)) |
12462 | { | |
33eaf5de | 12463 | /* Disable an ISA extension. */ |
293f5f65 L |
12464 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
12465 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
12466 | { | |
12467 | i386_cpu_flags flags; | |
12468 | ||
12469 | flags = cpu_flags_and_not (cpu_arch_flags, | |
12470 | cpu_noarch[j].flags); | |
12471 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
12472 | { | |
12473 | if (cpu_sub_arch_name) | |
12474 | { | |
12475 | char *name = cpu_sub_arch_name; | |
12476 | cpu_sub_arch_name = concat (arch, | |
12477 | (const char *) NULL); | |
12478 | free (name); | |
12479 | } | |
12480 | else | |
12481 | cpu_sub_arch_name = xstrdup (arch); | |
12482 | cpu_arch_flags = flags; | |
12483 | cpu_arch_isa_flags = flags; | |
12484 | } | |
12485 | break; | |
12486 | } | |
12487 | ||
12488 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
12489 | j = ARRAY_SIZE (cpu_arch); | |
12490 | } | |
12491 | ||
91d6fa6a | 12492 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12493 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12494 | |
12495 | arch = next; | |
9103f4f4 | 12496 | } |
293f5f65 L |
12497 | while (next != NULL); |
12498 | free (saved); | |
9103f4f4 L |
12499 | break; |
12500 | ||
12501 | case OPTION_MTUNE: | |
12502 | if (*arg == '.') | |
2b5d6a91 | 12503 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 12504 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12505 | { |
91d6fa6a | 12506 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 12507 | { |
ccc9c027 | 12508 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
12509 | cpu_arch_tune = cpu_arch [j].type; |
12510 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
12511 | break; |
12512 | } | |
12513 | } | |
91d6fa6a | 12514 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12515 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
12516 | break; |
12517 | ||
1efbbeb4 L |
12518 | case OPTION_MMNEMONIC: |
12519 | if (strcasecmp (arg, "att") == 0) | |
12520 | intel_mnemonic = 0; | |
12521 | else if (strcasecmp (arg, "intel") == 0) | |
12522 | intel_mnemonic = 1; | |
12523 | else | |
2b5d6a91 | 12524 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
12525 | break; |
12526 | ||
12527 | case OPTION_MSYNTAX: | |
12528 | if (strcasecmp (arg, "att") == 0) | |
12529 | intel_syntax = 0; | |
12530 | else if (strcasecmp (arg, "intel") == 0) | |
12531 | intel_syntax = 1; | |
12532 | else | |
2b5d6a91 | 12533 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
12534 | break; |
12535 | ||
12536 | case OPTION_MINDEX_REG: | |
12537 | allow_index_reg = 1; | |
12538 | break; | |
12539 | ||
12540 | case OPTION_MNAKED_REG: | |
12541 | allow_naked_reg = 1; | |
12542 | break; | |
12543 | ||
c0f3af97 L |
12544 | case OPTION_MSSE2AVX: |
12545 | sse2avx = 1; | |
12546 | break; | |
12547 | ||
daf50ae7 L |
12548 | case OPTION_MSSE_CHECK: |
12549 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 12550 | sse_check = check_error; |
daf50ae7 | 12551 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 12552 | sse_check = check_warning; |
daf50ae7 | 12553 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 12554 | sse_check = check_none; |
daf50ae7 | 12555 | else |
2b5d6a91 | 12556 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
12557 | break; |
12558 | ||
7bab8ab5 JB |
12559 | case OPTION_MOPERAND_CHECK: |
12560 | if (strcasecmp (arg, "error") == 0) | |
12561 | operand_check = check_error; | |
12562 | else if (strcasecmp (arg, "warning") == 0) | |
12563 | operand_check = check_warning; | |
12564 | else if (strcasecmp (arg, "none") == 0) | |
12565 | operand_check = check_none; | |
12566 | else | |
12567 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
12568 | break; | |
12569 | ||
539f890d L |
12570 | case OPTION_MAVXSCALAR: |
12571 | if (strcasecmp (arg, "128") == 0) | |
12572 | avxscalar = vex128; | |
12573 | else if (strcasecmp (arg, "256") == 0) | |
12574 | avxscalar = vex256; | |
12575 | else | |
2b5d6a91 | 12576 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
12577 | break; |
12578 | ||
03751133 L |
12579 | case OPTION_MVEXWIG: |
12580 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 12581 | vexwig = vexw0; |
03751133 | 12582 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 12583 | vexwig = vexw1; |
03751133 L |
12584 | else |
12585 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
12586 | break; | |
12587 | ||
7e8b059b L |
12588 | case OPTION_MADD_BND_PREFIX: |
12589 | add_bnd_prefix = 1; | |
12590 | break; | |
12591 | ||
43234a1e L |
12592 | case OPTION_MEVEXLIG: |
12593 | if (strcmp (arg, "128") == 0) | |
12594 | evexlig = evexl128; | |
12595 | else if (strcmp (arg, "256") == 0) | |
12596 | evexlig = evexl256; | |
12597 | else if (strcmp (arg, "512") == 0) | |
12598 | evexlig = evexl512; | |
12599 | else | |
12600 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
12601 | break; | |
12602 | ||
d3d3c6db IT |
12603 | case OPTION_MEVEXRCIG: |
12604 | if (strcmp (arg, "rne") == 0) | |
12605 | evexrcig = rne; | |
12606 | else if (strcmp (arg, "rd") == 0) | |
12607 | evexrcig = rd; | |
12608 | else if (strcmp (arg, "ru") == 0) | |
12609 | evexrcig = ru; | |
12610 | else if (strcmp (arg, "rz") == 0) | |
12611 | evexrcig = rz; | |
12612 | else | |
12613 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
12614 | break; | |
12615 | ||
43234a1e L |
12616 | case OPTION_MEVEXWIG: |
12617 | if (strcmp (arg, "0") == 0) | |
12618 | evexwig = evexw0; | |
12619 | else if (strcmp (arg, "1") == 0) | |
12620 | evexwig = evexw1; | |
12621 | else | |
12622 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
12623 | break; | |
12624 | ||
167ad85b TG |
12625 | # if defined (TE_PE) || defined (TE_PEP) |
12626 | case OPTION_MBIG_OBJ: | |
12627 | use_big_obj = 1; | |
12628 | break; | |
12629 | #endif | |
12630 | ||
d1982f93 | 12631 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
12632 | if (strcasecmp (arg, "yes") == 0) |
12633 | omit_lock_prefix = 1; | |
12634 | else if (strcasecmp (arg, "no") == 0) | |
12635 | omit_lock_prefix = 0; | |
12636 | else | |
12637 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
12638 | break; | |
12639 | ||
e4e00185 AS |
12640 | case OPTION_MFENCE_AS_LOCK_ADD: |
12641 | if (strcasecmp (arg, "yes") == 0) | |
12642 | avoid_fence = 1; | |
12643 | else if (strcasecmp (arg, "no") == 0) | |
12644 | avoid_fence = 0; | |
12645 | else | |
12646 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
12647 | break; | |
12648 | ||
0cb4071e L |
12649 | case OPTION_MRELAX_RELOCATIONS: |
12650 | if (strcasecmp (arg, "yes") == 0) | |
12651 | generate_relax_relocations = 1; | |
12652 | else if (strcasecmp (arg, "no") == 0) | |
12653 | generate_relax_relocations = 0; | |
12654 | else | |
12655 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
12656 | break; | |
12657 | ||
e379e5f3 L |
12658 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
12659 | { | |
12660 | char *end; | |
12661 | long int align = strtoul (arg, &end, 0); | |
12662 | if (*end == '\0') | |
12663 | { | |
12664 | if (align == 0) | |
12665 | { | |
12666 | align_branch_power = 0; | |
12667 | break; | |
12668 | } | |
12669 | else if (align >= 16) | |
12670 | { | |
12671 | int align_power; | |
12672 | for (align_power = 0; | |
12673 | (align & 1) == 0; | |
12674 | align >>= 1, align_power++) | |
12675 | continue; | |
12676 | /* Limit alignment power to 31. */ | |
12677 | if (align == 1 && align_power < 32) | |
12678 | { | |
12679 | align_branch_power = align_power; | |
12680 | break; | |
12681 | } | |
12682 | } | |
12683 | } | |
12684 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
12685 | } | |
12686 | break; | |
12687 | ||
12688 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
12689 | { | |
12690 | char *end; | |
12691 | int align = strtoul (arg, &end, 0); | |
12692 | /* Some processors only support 5 prefixes. */ | |
12693 | if (*end == '\0' && align >= 0 && align < 6) | |
12694 | { | |
12695 | align_branch_prefix_size = align; | |
12696 | break; | |
12697 | } | |
12698 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
12699 | arg); | |
12700 | } | |
12701 | break; | |
12702 | ||
12703 | case OPTION_MALIGN_BRANCH: | |
12704 | align_branch = 0; | |
12705 | saved = xstrdup (arg); | |
12706 | type = saved; | |
12707 | do | |
12708 | { | |
12709 | next = strchr (type, '+'); | |
12710 | if (next) | |
12711 | *next++ = '\0'; | |
12712 | if (strcasecmp (type, "jcc") == 0) | |
12713 | align_branch |= align_branch_jcc_bit; | |
12714 | else if (strcasecmp (type, "fused") == 0) | |
12715 | align_branch |= align_branch_fused_bit; | |
12716 | else if (strcasecmp (type, "jmp") == 0) | |
12717 | align_branch |= align_branch_jmp_bit; | |
12718 | else if (strcasecmp (type, "call") == 0) | |
12719 | align_branch |= align_branch_call_bit; | |
12720 | else if (strcasecmp (type, "ret") == 0) | |
12721 | align_branch |= align_branch_ret_bit; | |
12722 | else if (strcasecmp (type, "indirect") == 0) | |
12723 | align_branch |= align_branch_indirect_bit; | |
12724 | else | |
12725 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
12726 | type = next; | |
12727 | } | |
12728 | while (next != NULL); | |
12729 | free (saved); | |
12730 | break; | |
12731 | ||
76cf450b L |
12732 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
12733 | align_branch_power = 5; | |
12734 | align_branch_prefix_size = 5; | |
12735 | align_branch = (align_branch_jcc_bit | |
12736 | | align_branch_fused_bit | |
12737 | | align_branch_jmp_bit); | |
12738 | break; | |
12739 | ||
5db04b09 | 12740 | case OPTION_MAMD64: |
4b5aaf5f | 12741 | isa64 = amd64; |
5db04b09 L |
12742 | break; |
12743 | ||
12744 | case OPTION_MINTEL64: | |
4b5aaf5f | 12745 | isa64 = intel64; |
5db04b09 L |
12746 | break; |
12747 | ||
b6f8c7c4 L |
12748 | case 'O': |
12749 | if (arg == NULL) | |
12750 | { | |
12751 | optimize = 1; | |
12752 | /* Turn off -Os. */ | |
12753 | optimize_for_space = 0; | |
12754 | } | |
12755 | else if (*arg == 's') | |
12756 | { | |
12757 | optimize_for_space = 1; | |
12758 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 12759 | optimize = INT_MAX; |
b6f8c7c4 L |
12760 | } |
12761 | else | |
12762 | { | |
12763 | optimize = atoi (arg); | |
12764 | /* Turn off -Os. */ | |
12765 | optimize_for_space = 0; | |
12766 | } | |
12767 | break; | |
12768 | ||
252b5132 RH |
12769 | default: |
12770 | return 0; | |
12771 | } | |
12772 | return 1; | |
12773 | } | |
12774 | ||
8a2c8fef L |
12775 | #define MESSAGE_TEMPLATE \ |
12776 | " " | |
12777 | ||
293f5f65 L |
12778 | static char * |
12779 | output_message (FILE *stream, char *p, char *message, char *start, | |
12780 | int *left_p, const char *name, int len) | |
12781 | { | |
12782 | int size = sizeof (MESSAGE_TEMPLATE); | |
12783 | int left = *left_p; | |
12784 | ||
12785 | /* Reserve 2 spaces for ", " or ",\0" */ | |
12786 | left -= len + 2; | |
12787 | ||
12788 | /* Check if there is any room. */ | |
12789 | if (left >= 0) | |
12790 | { | |
12791 | if (p != start) | |
12792 | { | |
12793 | *p++ = ','; | |
12794 | *p++ = ' '; | |
12795 | } | |
12796 | p = mempcpy (p, name, len); | |
12797 | } | |
12798 | else | |
12799 | { | |
12800 | /* Output the current message now and start a new one. */ | |
12801 | *p++ = ','; | |
12802 | *p = '\0'; | |
12803 | fprintf (stream, "%s\n", message); | |
12804 | p = start; | |
12805 | left = size - (start - message) - len - 2; | |
12806 | ||
12807 | gas_assert (left >= 0); | |
12808 | ||
12809 | p = mempcpy (p, name, len); | |
12810 | } | |
12811 | ||
12812 | *left_p = left; | |
12813 | return p; | |
12814 | } | |
12815 | ||
8a2c8fef | 12816 | static void |
1ded5609 | 12817 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
12818 | { |
12819 | static char message[] = MESSAGE_TEMPLATE; | |
12820 | char *start = message + 27; | |
12821 | char *p; | |
12822 | int size = sizeof (MESSAGE_TEMPLATE); | |
12823 | int left; | |
12824 | const char *name; | |
12825 | int len; | |
12826 | unsigned int j; | |
12827 | ||
12828 | p = start; | |
12829 | left = size - (start - message); | |
12830 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
12831 | { | |
12832 | /* Should it be skipped? */ | |
12833 | if (cpu_arch [j].skip) | |
12834 | continue; | |
12835 | ||
12836 | name = cpu_arch [j].name; | |
12837 | len = cpu_arch [j].len; | |
12838 | if (*name == '.') | |
12839 | { | |
12840 | /* It is an extension. Skip if we aren't asked to show it. */ | |
12841 | if (ext) | |
12842 | { | |
12843 | name++; | |
12844 | len--; | |
12845 | } | |
12846 | else | |
12847 | continue; | |
12848 | } | |
12849 | else if (ext) | |
12850 | { | |
12851 | /* It is an processor. Skip if we show only extension. */ | |
12852 | continue; | |
12853 | } | |
1ded5609 JB |
12854 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
12855 | { | |
12856 | /* It is an impossible processor - skip. */ | |
12857 | continue; | |
12858 | } | |
8a2c8fef | 12859 | |
293f5f65 | 12860 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
12861 | } |
12862 | ||
293f5f65 L |
12863 | /* Display disabled extensions. */ |
12864 | if (ext) | |
12865 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
12866 | { | |
12867 | name = cpu_noarch [j].name; | |
12868 | len = cpu_noarch [j].len; | |
12869 | p = output_message (stream, p, message, start, &left, name, | |
12870 | len); | |
12871 | } | |
12872 | ||
8a2c8fef L |
12873 | *p = '\0'; |
12874 | fprintf (stream, "%s\n", message); | |
12875 | } | |
12876 | ||
252b5132 | 12877 | void |
8a2c8fef | 12878 | md_show_usage (FILE *stream) |
252b5132 | 12879 | { |
4cc782b5 ILT |
12880 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12881 | fprintf (stream, _("\ | |
d4693039 | 12882 | -Qy, -Qn ignored\n\ |
a38cf1db | 12883 | -V print assembler version number\n\ |
b3b91714 AM |
12884 | -k ignored\n")); |
12885 | #endif | |
12886 | fprintf (stream, _("\ | |
12b55ccc | 12887 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
12888 | -q quieten some warnings\n")); |
12889 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12890 | fprintf (stream, _("\ | |
a38cf1db | 12891 | -s ignored\n")); |
b3b91714 | 12892 | #endif |
d7f449c0 L |
12893 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
12894 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 12895 | fprintf (stream, _("\ |
570561f7 | 12896 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 12897 | #endif |
b3b91714 AM |
12898 | #ifdef SVR4_COMMENT_CHARS |
12899 | fprintf (stream, _("\ | |
12900 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
12901 | #else |
12902 | fprintf (stream, _("\ | |
b3b91714 | 12903 | --divide ignored\n")); |
4cc782b5 | 12904 | #endif |
9103f4f4 | 12905 | fprintf (stream, _("\ |
6305a203 | 12906 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 12907 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 12908 | show_arch (stream, 0, 1); |
8a2c8fef L |
12909 | fprintf (stream, _("\ |
12910 | EXTENSION is combination of:\n")); | |
1ded5609 | 12911 | show_arch (stream, 1, 0); |
6305a203 | 12912 | fprintf (stream, _("\ |
8a2c8fef | 12913 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 12914 | show_arch (stream, 0, 0); |
ba104c83 | 12915 | fprintf (stream, _("\ |
c0f3af97 L |
12916 | -msse2avx encode SSE instructions with VEX prefix\n")); |
12917 | fprintf (stream, _("\ | |
7c5c05ef | 12918 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
12919 | check SSE instructions\n")); |
12920 | fprintf (stream, _("\ | |
7c5c05ef | 12921 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
12922 | check operand combinations for validity\n")); |
12923 | fprintf (stream, _("\ | |
7c5c05ef L |
12924 | -mavxscalar=[128|256] (default: 128)\n\ |
12925 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
12926 | length\n")); |
12927 | fprintf (stream, _("\ | |
03751133 L |
12928 | -mvexwig=[0|1] (default: 0)\n\ |
12929 | encode VEX instructions with specific VEX.W value\n\ | |
12930 | for VEX.W bit ignored instructions\n")); | |
12931 | fprintf (stream, _("\ | |
7c5c05ef L |
12932 | -mevexlig=[128|256|512] (default: 128)\n\ |
12933 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
12934 | length\n")); |
12935 | fprintf (stream, _("\ | |
7c5c05ef L |
12936 | -mevexwig=[0|1] (default: 0)\n\ |
12937 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
12938 | for EVEX.W bit ignored instructions\n")); |
12939 | fprintf (stream, _("\ | |
7c5c05ef | 12940 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
12941 | encode EVEX instructions with specific EVEX.RC value\n\ |
12942 | for SAE-only ignored instructions\n")); | |
12943 | fprintf (stream, _("\ | |
7c5c05ef L |
12944 | -mmnemonic=[att|intel] ")); |
12945 | if (SYSV386_COMPAT) | |
12946 | fprintf (stream, _("(default: att)\n")); | |
12947 | else | |
12948 | fprintf (stream, _("(default: intel)\n")); | |
12949 | fprintf (stream, _("\ | |
12950 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 12951 | fprintf (stream, _("\ |
7c5c05ef L |
12952 | -msyntax=[att|intel] (default: att)\n\ |
12953 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
12954 | fprintf (stream, _("\ |
12955 | -mindex-reg support pseudo index registers\n")); | |
12956 | fprintf (stream, _("\ | |
12957 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
12958 | fprintf (stream, _("\ | |
7e8b059b | 12959 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 12960 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
12961 | fprintf (stream, _("\ |
12962 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
12963 | fprintf (stream, _("\ |
12964 | -mx86-used-note=[no|yes] ")); | |
12965 | if (DEFAULT_X86_USED_NOTE) | |
12966 | fprintf (stream, _("(default: yes)\n")); | |
12967 | else | |
12968 | fprintf (stream, _("(default: no)\n")); | |
12969 | fprintf (stream, _("\ | |
12970 | generate x86 used ISA and feature properties\n")); | |
12971 | #endif | |
12972 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
12973 | fprintf (stream, _("\ |
12974 | -mbig-obj generate big object files\n")); | |
12975 | #endif | |
d022bddd | 12976 | fprintf (stream, _("\ |
7c5c05ef | 12977 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 12978 | strip all lock prefixes\n")); |
5db04b09 | 12979 | fprintf (stream, _("\ |
7c5c05ef | 12980 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
12981 | encode lfence, mfence and sfence as\n\ |
12982 | lock addl $0x0, (%%{re}sp)\n")); | |
12983 | fprintf (stream, _("\ | |
7c5c05ef L |
12984 | -mrelax-relocations=[no|yes] ")); |
12985 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
12986 | fprintf (stream, _("(default: yes)\n")); | |
12987 | else | |
12988 | fprintf (stream, _("(default: no)\n")); | |
12989 | fprintf (stream, _("\ | |
0cb4071e L |
12990 | generate relax relocations\n")); |
12991 | fprintf (stream, _("\ | |
e379e5f3 L |
12992 | -malign-branch-boundary=NUM (default: 0)\n\ |
12993 | align branches within NUM byte boundary\n")); | |
12994 | fprintf (stream, _("\ | |
12995 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
12996 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
12997 | indirect\n\ | |
12998 | specify types of branches to align\n")); | |
12999 | fprintf (stream, _("\ | |
13000 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
13001 | align branches with NUM prefixes per instruction\n")); | |
13002 | fprintf (stream, _("\ | |
76cf450b L |
13003 | -mbranches-within-32B-boundaries\n\ |
13004 | align branches within 32 byte boundary\n")); | |
13005 | fprintf (stream, _("\ | |
7c5c05ef | 13006 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
13007 | fprintf (stream, _("\ |
13008 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
13009 | } |
13010 | ||
3e73aa7c | 13011 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 13012 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 13013 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
13014 | |
13015 | /* Pick the target format to use. */ | |
13016 | ||
47926f60 | 13017 | const char * |
e3bb37b5 | 13018 | i386_target_format (void) |
252b5132 | 13019 | { |
351f65ca L |
13020 | if (!strncmp (default_arch, "x86_64", 6)) |
13021 | { | |
13022 | update_code_flag (CODE_64BIT, 1); | |
13023 | if (default_arch[6] == '\0') | |
7f56bc95 | 13024 | x86_elf_abi = X86_64_ABI; |
351f65ca | 13025 | else |
7f56bc95 | 13026 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 13027 | } |
3e73aa7c | 13028 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 13029 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
13030 | else if (!strcmp (default_arch, "iamcu")) |
13031 | { | |
13032 | update_code_flag (CODE_32BIT, 1); | |
13033 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
13034 | { | |
13035 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
13036 | cpu_arch_name = "iamcu"; | |
13037 | cpu_sub_arch_name = NULL; | |
13038 | cpu_arch_flags = iamcu_flags; | |
13039 | cpu_arch_isa = PROCESSOR_IAMCU; | |
13040 | cpu_arch_isa_flags = iamcu_flags; | |
13041 | if (!cpu_arch_tune_set) | |
13042 | { | |
13043 | cpu_arch_tune = cpu_arch_isa; | |
13044 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13045 | } | |
13046 | } | |
8d471ec1 | 13047 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
13048 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
13049 | cpu_arch_name); | |
13050 | } | |
3e73aa7c | 13051 | else |
2b5d6a91 | 13052 | as_fatal (_("unknown architecture")); |
89507696 JB |
13053 | |
13054 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
13055 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13056 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
13057 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13058 | ||
252b5132 RH |
13059 | switch (OUTPUT_FLAVOR) |
13060 | { | |
9384f2ff | 13061 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 13062 | case bfd_target_aout_flavour: |
47926f60 | 13063 | return AOUT_TARGET_FORMAT; |
4c63da97 | 13064 | #endif |
9384f2ff AM |
13065 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
13066 | # if defined (TE_PE) || defined (TE_PEP) | |
13067 | case bfd_target_coff_flavour: | |
167ad85b TG |
13068 | if (flag_code == CODE_64BIT) |
13069 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
13070 | else | |
13071 | return "pe-i386"; | |
9384f2ff | 13072 | # elif defined (TE_GO32) |
0561d57c JK |
13073 | case bfd_target_coff_flavour: |
13074 | return "coff-go32"; | |
9384f2ff | 13075 | # else |
252b5132 RH |
13076 | case bfd_target_coff_flavour: |
13077 | return "coff-i386"; | |
9384f2ff | 13078 | # endif |
4c63da97 | 13079 | #endif |
3e73aa7c | 13080 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 13081 | case bfd_target_elf_flavour: |
3e73aa7c | 13082 | { |
351f65ca L |
13083 | const char *format; |
13084 | ||
13085 | switch (x86_elf_abi) | |
4fa24527 | 13086 | { |
351f65ca L |
13087 | default: |
13088 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
13089 | #ifndef TE_SOLARIS |
13090 | tls_get_addr = "___tls_get_addr"; | |
13091 | #endif | |
351f65ca | 13092 | break; |
7f56bc95 | 13093 | case X86_64_ABI: |
351f65ca | 13094 | use_rela_relocations = 1; |
4fa24527 | 13095 | object_64bit = 1; |
e379e5f3 L |
13096 | #ifndef TE_SOLARIS |
13097 | tls_get_addr = "__tls_get_addr"; | |
13098 | #endif | |
351f65ca L |
13099 | format = ELF_TARGET_FORMAT64; |
13100 | break; | |
7f56bc95 | 13101 | case X86_64_X32_ABI: |
4fa24527 | 13102 | use_rela_relocations = 1; |
351f65ca | 13103 | object_64bit = 1; |
e379e5f3 L |
13104 | #ifndef TE_SOLARIS |
13105 | tls_get_addr = "__tls_get_addr"; | |
13106 | #endif | |
862be3fb | 13107 | disallow_64bit_reloc = 1; |
351f65ca L |
13108 | format = ELF_TARGET_FORMAT32; |
13109 | break; | |
4fa24527 | 13110 | } |
3632d14b | 13111 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 13112 | { |
7f56bc95 | 13113 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
13114 | as_fatal (_("Intel L1OM is 64bit only")); |
13115 | return ELF_TARGET_L1OM_FORMAT; | |
13116 | } | |
b49f93f6 | 13117 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
13118 | { |
13119 | if (x86_elf_abi != X86_64_ABI) | |
13120 | as_fatal (_("Intel K1OM is 64bit only")); | |
13121 | return ELF_TARGET_K1OM_FORMAT; | |
13122 | } | |
81486035 L |
13123 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
13124 | { | |
13125 | if (x86_elf_abi != I386_ABI) | |
13126 | as_fatal (_("Intel MCU is 32bit only")); | |
13127 | return ELF_TARGET_IAMCU_FORMAT; | |
13128 | } | |
8a9036a4 | 13129 | else |
351f65ca | 13130 | return format; |
3e73aa7c | 13131 | } |
e57f8c65 TG |
13132 | #endif |
13133 | #if defined (OBJ_MACH_O) | |
13134 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
13135 | if (flag_code == CODE_64BIT) |
13136 | { | |
13137 | use_rela_relocations = 1; | |
13138 | object_64bit = 1; | |
13139 | return "mach-o-x86-64"; | |
13140 | } | |
13141 | else | |
13142 | return "mach-o-i386"; | |
4c63da97 | 13143 | #endif |
252b5132 RH |
13144 | default: |
13145 | abort (); | |
13146 | return NULL; | |
13147 | } | |
13148 | } | |
13149 | ||
47926f60 | 13150 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 13151 | \f |
252b5132 | 13152 | symbolS * |
7016a5d5 | 13153 | md_undefined_symbol (char *name) |
252b5132 | 13154 | { |
18dc2407 ILT |
13155 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
13156 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
13157 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
13158 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
13159 | { |
13160 | if (!GOT_symbol) | |
13161 | { | |
13162 | if (symbol_find (name)) | |
13163 | as_bad (_("GOT already in symbol table")); | |
13164 | GOT_symbol = symbol_new (name, undefined_section, | |
13165 | (valueT) 0, &zero_address_frag); | |
13166 | }; | |
13167 | return GOT_symbol; | |
13168 | } | |
252b5132 RH |
13169 | return 0; |
13170 | } | |
13171 | ||
13172 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 13173 | |
252b5132 | 13174 | valueT |
7016a5d5 | 13175 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 13176 | { |
4c63da97 AM |
13177 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
13178 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
13179 | { | |
13180 | /* For a.out, force the section size to be aligned. If we don't do | |
13181 | this, BFD will align it for us, but it will not write out the | |
13182 | final bytes of the section. This may be a bug in BFD, but it is | |
13183 | easier to fix it here since that is how the other a.out targets | |
13184 | work. */ | |
13185 | int align; | |
13186 | ||
fd361982 | 13187 | align = bfd_section_alignment (segment); |
8d3842cd | 13188 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 13189 | } |
252b5132 RH |
13190 | #endif |
13191 | ||
13192 | return size; | |
13193 | } | |
13194 | ||
13195 | /* On the i386, PC-relative offsets are relative to the start of the | |
13196 | next instruction. That is, the address of the offset, plus its | |
13197 | size, since the offset is always the last part of the insn. */ | |
13198 | ||
13199 | long | |
e3bb37b5 | 13200 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
13201 | { |
13202 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
13203 | } | |
13204 | ||
13205 | #ifndef I386COFF | |
13206 | ||
13207 | static void | |
e3bb37b5 | 13208 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13209 | { |
29b0f896 | 13210 | int temp; |
252b5132 | 13211 | |
8a75718c JB |
13212 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13213 | if (IS_ELF) | |
13214 | obj_elf_section_change_hook (); | |
13215 | #endif | |
252b5132 RH |
13216 | temp = get_absolute_expression (); |
13217 | subseg_set (bss_section, (subsegT) temp); | |
13218 | demand_empty_rest_of_line (); | |
13219 | } | |
13220 | ||
13221 | #endif | |
13222 | ||
e379e5f3 L |
13223 | /* Remember constant directive. */ |
13224 | ||
13225 | void | |
13226 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
13227 | { | |
13228 | if (last_insn.kind != last_insn_directive | |
13229 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
13230 | { | |
13231 | last_insn.seg = now_seg; | |
13232 | last_insn.kind = last_insn_directive; | |
13233 | last_insn.name = "constant directive"; | |
13234 | last_insn.file = as_where (&last_insn.line); | |
13235 | } | |
13236 | } | |
13237 | ||
252b5132 | 13238 | void |
e3bb37b5 | 13239 | i386_validate_fix (fixS *fixp) |
252b5132 | 13240 | { |
02a86693 | 13241 | if (fixp->fx_subsy) |
252b5132 | 13242 | { |
02a86693 | 13243 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 13244 | { |
02a86693 L |
13245 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
13246 | { | |
13247 | if (!object_64bit) | |
13248 | abort (); | |
13249 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13250 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
13251 | fixp->fx_r_type = (fixp->fx_tcbit |
13252 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
13253 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
13254 | else |
13255 | #endif | |
13256 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
13257 | } | |
d6ab8113 | 13258 | else |
02a86693 L |
13259 | { |
13260 | if (!object_64bit) | |
13261 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
13262 | else | |
13263 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
13264 | } | |
13265 | fixp->fx_subsy = 0; | |
23df1078 | 13266 | } |
252b5132 | 13267 | } |
02a86693 L |
13268 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13269 | else if (!object_64bit) | |
13270 | { | |
13271 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
13272 | && fixp->fx_tcbit2) | |
13273 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
13274 | } | |
13275 | #endif | |
252b5132 RH |
13276 | } |
13277 | ||
252b5132 | 13278 | arelent * |
7016a5d5 | 13279 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13280 | { |
13281 | arelent *rel; | |
13282 | bfd_reloc_code_real_type code; | |
13283 | ||
13284 | switch (fixp->fx_r_type) | |
13285 | { | |
8ce3d284 | 13286 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
13287 | case BFD_RELOC_SIZE32: |
13288 | case BFD_RELOC_SIZE64: | |
13289 | if (S_IS_DEFINED (fixp->fx_addsy) | |
13290 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
13291 | { | |
13292 | /* Resolve size relocation against local symbol to size of | |
13293 | the symbol plus addend. */ | |
13294 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
13295 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
13296 | && !fits_in_unsigned_long (value)) | |
13297 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13298 | _("symbol size computation overflow")); | |
13299 | fixp->fx_addsy = NULL; | |
13300 | fixp->fx_subsy = NULL; | |
13301 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
13302 | return NULL; | |
13303 | } | |
8ce3d284 | 13304 | #endif |
1a0670f3 | 13305 | /* Fall through. */ |
8fd4256d | 13306 | |
3e73aa7c JH |
13307 | case BFD_RELOC_X86_64_PLT32: |
13308 | case BFD_RELOC_X86_64_GOT32: | |
13309 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13310 | case BFD_RELOC_X86_64_GOTPCRELX: |
13311 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
13312 | case BFD_RELOC_386_PLT32: |
13313 | case BFD_RELOC_386_GOT32: | |
02a86693 | 13314 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
13315 | case BFD_RELOC_386_GOTOFF: |
13316 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
13317 | case BFD_RELOC_386_TLS_GD: |
13318 | case BFD_RELOC_386_TLS_LDM: | |
13319 | case BFD_RELOC_386_TLS_LDO_32: | |
13320 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
13321 | case BFD_RELOC_386_TLS_IE: |
13322 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
13323 | case BFD_RELOC_386_TLS_LE_32: |
13324 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
13325 | case BFD_RELOC_386_TLS_GOTDESC: |
13326 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
13327 | case BFD_RELOC_X86_64_TLSGD: |
13328 | case BFD_RELOC_X86_64_TLSLD: | |
13329 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 13330 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
13331 | case BFD_RELOC_X86_64_GOTTPOFF: |
13332 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
13333 | case BFD_RELOC_X86_64_TPOFF64: |
13334 | case BFD_RELOC_X86_64_GOTOFF64: | |
13335 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
13336 | case BFD_RELOC_X86_64_GOT64: |
13337 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13338 | case BFD_RELOC_X86_64_GOTPC64: | |
13339 | case BFD_RELOC_X86_64_GOTPLT64: | |
13340 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
13341 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13342 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
13343 | case BFD_RELOC_RVA: |
13344 | case BFD_RELOC_VTABLE_ENTRY: | |
13345 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
13346 | #ifdef TE_PE |
13347 | case BFD_RELOC_32_SECREL: | |
13348 | #endif | |
252b5132 RH |
13349 | code = fixp->fx_r_type; |
13350 | break; | |
dbbaec26 L |
13351 | case BFD_RELOC_X86_64_32S: |
13352 | if (!fixp->fx_pcrel) | |
13353 | { | |
13354 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
13355 | code = fixp->fx_r_type; | |
13356 | break; | |
13357 | } | |
1a0670f3 | 13358 | /* Fall through. */ |
252b5132 | 13359 | default: |
93382f6d | 13360 | if (fixp->fx_pcrel) |
252b5132 | 13361 | { |
93382f6d AM |
13362 | switch (fixp->fx_size) |
13363 | { | |
13364 | default: | |
b091f402 AM |
13365 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13366 | _("can not do %d byte pc-relative relocation"), | |
13367 | fixp->fx_size); | |
93382f6d AM |
13368 | code = BFD_RELOC_32_PCREL; |
13369 | break; | |
13370 | case 1: code = BFD_RELOC_8_PCREL; break; | |
13371 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 13372 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
13373 | #ifdef BFD64 |
13374 | case 8: code = BFD_RELOC_64_PCREL; break; | |
13375 | #endif | |
93382f6d AM |
13376 | } |
13377 | } | |
13378 | else | |
13379 | { | |
13380 | switch (fixp->fx_size) | |
13381 | { | |
13382 | default: | |
b091f402 AM |
13383 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13384 | _("can not do %d byte relocation"), | |
13385 | fixp->fx_size); | |
93382f6d AM |
13386 | code = BFD_RELOC_32; |
13387 | break; | |
13388 | case 1: code = BFD_RELOC_8; break; | |
13389 | case 2: code = BFD_RELOC_16; break; | |
13390 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 13391 | #ifdef BFD64 |
3e73aa7c | 13392 | case 8: code = BFD_RELOC_64; break; |
937149dd | 13393 | #endif |
93382f6d | 13394 | } |
252b5132 RH |
13395 | } |
13396 | break; | |
13397 | } | |
252b5132 | 13398 | |
d182319b JB |
13399 | if ((code == BFD_RELOC_32 |
13400 | || code == BFD_RELOC_32_PCREL | |
13401 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
13402 | && GOT_symbol |
13403 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 13404 | { |
4fa24527 | 13405 | if (!object_64bit) |
d6ab8113 JB |
13406 | code = BFD_RELOC_386_GOTPC; |
13407 | else | |
13408 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 13409 | } |
7b81dfbb AJ |
13410 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
13411 | && GOT_symbol | |
13412 | && fixp->fx_addsy == GOT_symbol) | |
13413 | { | |
13414 | code = BFD_RELOC_X86_64_GOTPC64; | |
13415 | } | |
252b5132 | 13416 | |
add39d23 TS |
13417 | rel = XNEW (arelent); |
13418 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 13419 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
13420 | |
13421 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 13422 | |
3e73aa7c JH |
13423 | if (!use_rela_relocations) |
13424 | { | |
13425 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
13426 | vtable entry to be used in the relocation's section offset. */ | |
13427 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13428 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
13429 | #if defined (OBJ_COFF) && defined (TE_PE) |
13430 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
13431 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
13432 | else | |
13433 | #endif | |
c6682705 | 13434 | rel->addend = 0; |
3e73aa7c JH |
13435 | } |
13436 | /* Use the rela in 64bit mode. */ | |
252b5132 | 13437 | else |
3e73aa7c | 13438 | { |
862be3fb L |
13439 | if (disallow_64bit_reloc) |
13440 | switch (code) | |
13441 | { | |
862be3fb L |
13442 | case BFD_RELOC_X86_64_DTPOFF64: |
13443 | case BFD_RELOC_X86_64_TPOFF64: | |
13444 | case BFD_RELOC_64_PCREL: | |
13445 | case BFD_RELOC_X86_64_GOTOFF64: | |
13446 | case BFD_RELOC_X86_64_GOT64: | |
13447 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13448 | case BFD_RELOC_X86_64_GOTPC64: | |
13449 | case BFD_RELOC_X86_64_GOTPLT64: | |
13450 | case BFD_RELOC_X86_64_PLTOFF64: | |
13451 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13452 | _("cannot represent relocation type %s in x32 mode"), | |
13453 | bfd_get_reloc_code_name (code)); | |
13454 | break; | |
13455 | default: | |
13456 | break; | |
13457 | } | |
13458 | ||
062cd5e7 AS |
13459 | if (!fixp->fx_pcrel) |
13460 | rel->addend = fixp->fx_offset; | |
13461 | else | |
13462 | switch (code) | |
13463 | { | |
13464 | case BFD_RELOC_X86_64_PLT32: | |
13465 | case BFD_RELOC_X86_64_GOT32: | |
13466 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13467 | case BFD_RELOC_X86_64_GOTPCRELX: |
13468 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
13469 | case BFD_RELOC_X86_64_TLSGD: |
13470 | case BFD_RELOC_X86_64_TLSLD: | |
13471 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
13472 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13473 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
13474 | rel->addend = fixp->fx_offset - fixp->fx_size; |
13475 | break; | |
13476 | default: | |
13477 | rel->addend = (section->vma | |
13478 | - fixp->fx_size | |
13479 | + fixp->fx_addnumber | |
13480 | + md_pcrel_from (fixp)); | |
13481 | break; | |
13482 | } | |
3e73aa7c JH |
13483 | } |
13484 | ||
252b5132 RH |
13485 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
13486 | if (rel->howto == NULL) | |
13487 | { | |
13488 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 13489 | _("cannot represent relocation type %s"), |
252b5132 RH |
13490 | bfd_get_reloc_code_name (code)); |
13491 | /* Set howto to a garbage value so that we can keep going. */ | |
13492 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 13493 | gas_assert (rel->howto != NULL); |
252b5132 RH |
13494 | } |
13495 | ||
13496 | return rel; | |
13497 | } | |
13498 | ||
ee86248c | 13499 | #include "tc-i386-intel.c" |
54cfded0 | 13500 | |
a60de03c JB |
13501 | void |
13502 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 13503 | { |
a60de03c JB |
13504 | int saved_naked_reg; |
13505 | char saved_register_dot; | |
54cfded0 | 13506 | |
a60de03c JB |
13507 | saved_naked_reg = allow_naked_reg; |
13508 | allow_naked_reg = 1; | |
13509 | saved_register_dot = register_chars['.']; | |
13510 | register_chars['.'] = '.'; | |
13511 | allow_pseudo_reg = 1; | |
13512 | expression_and_evaluate (exp); | |
13513 | allow_pseudo_reg = 0; | |
13514 | register_chars['.'] = saved_register_dot; | |
13515 | allow_naked_reg = saved_naked_reg; | |
13516 | ||
e96d56a1 | 13517 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 13518 | { |
a60de03c JB |
13519 | if ((addressT) exp->X_add_number < i386_regtab_size) |
13520 | { | |
13521 | exp->X_op = O_constant; | |
13522 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
13523 | .dw2_regnum[flag_code >> 1]; | |
13524 | } | |
13525 | else | |
13526 | exp->X_op = O_illegal; | |
54cfded0 | 13527 | } |
54cfded0 AM |
13528 | } |
13529 | ||
13530 | void | |
13531 | tc_x86_frame_initial_instructions (void) | |
13532 | { | |
a60de03c JB |
13533 | static unsigned int sp_regno[2]; |
13534 | ||
13535 | if (!sp_regno[flag_code >> 1]) | |
13536 | { | |
13537 | char *saved_input = input_line_pointer; | |
13538 | char sp[][4] = {"esp", "rsp"}; | |
13539 | expressionS exp; | |
a4447b93 | 13540 | |
a60de03c JB |
13541 | input_line_pointer = sp[flag_code >> 1]; |
13542 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 13543 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
13544 | sp_regno[flag_code >> 1] = exp.X_add_number; |
13545 | input_line_pointer = saved_input; | |
13546 | } | |
a4447b93 | 13547 | |
61ff971f L |
13548 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
13549 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 13550 | } |
d2b2c203 | 13551 | |
d7921315 L |
13552 | int |
13553 | x86_dwarf2_addr_size (void) | |
13554 | { | |
13555 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
13556 | if (x86_elf_abi == X86_64_X32_ABI) | |
13557 | return 4; | |
13558 | #endif | |
13559 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
13560 | } | |
13561 | ||
d2b2c203 DJ |
13562 | int |
13563 | i386_elf_section_type (const char *str, size_t len) | |
13564 | { | |
13565 | if (flag_code == CODE_64BIT | |
13566 | && len == sizeof ("unwind") - 1 | |
13567 | && strncmp (str, "unwind", 6) == 0) | |
13568 | return SHT_X86_64_UNWIND; | |
13569 | ||
13570 | return -1; | |
13571 | } | |
bb41ade5 | 13572 | |
ad5fec3b EB |
13573 | #ifdef TE_SOLARIS |
13574 | void | |
13575 | i386_solaris_fix_up_eh_frame (segT sec) | |
13576 | { | |
13577 | if (flag_code == CODE_64BIT) | |
13578 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
13579 | } | |
13580 | #endif | |
13581 | ||
bb41ade5 AM |
13582 | #ifdef TE_PE |
13583 | void | |
13584 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
13585 | { | |
91d6fa6a | 13586 | expressionS exp; |
bb41ade5 | 13587 | |
91d6fa6a NC |
13588 | exp.X_op = O_secrel; |
13589 | exp.X_add_symbol = symbol; | |
13590 | exp.X_add_number = 0; | |
13591 | emit_expr (&exp, size); | |
bb41ade5 AM |
13592 | } |
13593 | #endif | |
3b22753a L |
13594 | |
13595 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13596 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
13597 | ||
01e1a5bc | 13598 | bfd_vma |
6d4af3c2 | 13599 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
13600 | { |
13601 | if (flag_code == CODE_64BIT) | |
13602 | { | |
13603 | if (letter == 'l') | |
13604 | return SHF_X86_64_LARGE; | |
13605 | ||
8f3bae45 | 13606 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 13607 | } |
3b22753a | 13608 | else |
8f3bae45 | 13609 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
13610 | return -1; |
13611 | } | |
13612 | ||
01e1a5bc | 13613 | bfd_vma |
3b22753a L |
13614 | x86_64_section_word (char *str, size_t len) |
13615 | { | |
8620418b | 13616 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
13617 | return SHF_X86_64_LARGE; |
13618 | ||
13619 | return -1; | |
13620 | } | |
13621 | ||
13622 | static void | |
13623 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
13624 | { | |
13625 | if (flag_code != CODE_64BIT) | |
13626 | { | |
13627 | s_comm_internal (0, elf_common_parse); | |
13628 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
13629 | } | |
13630 | else | |
13631 | { | |
13632 | static segT lbss_section; | |
13633 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
13634 | asection *saved_bss_section = bss_section; | |
13635 | ||
13636 | if (lbss_section == NULL) | |
13637 | { | |
13638 | flagword applicable; | |
13639 | segT seg = now_seg; | |
13640 | subsegT subseg = now_subseg; | |
13641 | ||
13642 | /* The .lbss section is for local .largecomm symbols. */ | |
13643 | lbss_section = subseg_new (".lbss", 0); | |
13644 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 13645 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
13646 | seg_info (lbss_section)->bss = 1; |
13647 | ||
13648 | subseg_set (seg, subseg); | |
13649 | } | |
13650 | ||
13651 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
13652 | bss_section = lbss_section; | |
13653 | ||
13654 | s_comm_internal (0, elf_common_parse); | |
13655 | ||
13656 | elf_com_section_ptr = saved_com_section_ptr; | |
13657 | bss_section = saved_bss_section; | |
13658 | } | |
13659 | } | |
13660 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |