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* config/tc-mips.c (macro) <M_S_DOB>: Fix the placement of code.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
22109423 135 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 136}
137arch_entry;
138
78f12dd3 139static void update_code_flag (int, int);
e3bb37b5
L		 140static void set_code_flag (int);
141static void set_16bit_gcc_code_flag (int);
142static void set_intel_syntax (int);
1efbbeb4 143static void set_intel_mnemonic (int);
db51cc60 144static void set_allow_index_reg (int);
cb19c032 145static void set_sse_check (int);
e3bb37b5 146static void set_cpu_arch (int);
6482c264 147#ifdef TE_PE
e3bb37b5 148static void pe_directive_secrel (int);
6482c264 149#endif
e3bb37b5
L		 150static void signed_cons (int);
151static char *output_invalid (int c);
ee86248c
JB		 152static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
a7619375 156static int i386_att_operand (char *);
e3bb37b5 157static int i386_intel_operand (char *, int);
ee86248c
JB		 158static int i386_intel_simplify (expressionS *);
159static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 160static const reg_entry *parse_register (char *, char **);
161static char *parse_insn (char *, char *);
162static char *parse_operands (char *, const char *);
163static void swap_operands (void);
4d456e3d 164static void swap_2_operands (int, int);
e3bb37b5
L		 165static void optimize_imm (void);
166static void optimize_disp (void);
d3ce72d0 167static const insn_template *match_template (void);
e3bb37b5
L		 168static int check_string (void);
169static int process_suffix (void);
170static int check_byte_reg (void);
171static int check_long_reg (void);
172static int check_qword_reg (void);
173static int check_word_reg (void);
174static int finalize_imm (void);
175static int process_operands (void);
176static const seg_entry *build_modrm_byte (void);
177static void output_insn (void);
178static void output_imm (fragS *, offsetT);
179static void output_disp (fragS *, offsetT);
29b0f896 180#ifndef I386COFF
e3bb37b5 181static void s_bss (int);
252b5132 182#endif
17d4e2a2
L		 183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184static void handle_large_common (int small ATTRIBUTE_UNUSED);
185#endif
252b5132 186
a847613f 187static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 188
c0f3af97
L		 189/* VEX prefix. */
190typedef struct
191{
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes[3];
194 unsigned int length;
195 /* Destination or source register specifier. */
196 const reg_entry *register_specifier;
197} vex_prefix;
198
252b5132 199/* 'md_assemble ()' gathers together information and puts it into a
47926f60 200 i386_insn. */
252b5132 201
520dc8e8
AM		 202union i386_op
203 {
204 expressionS *disps;
205 expressionS *imms;
206 const reg_entry *regs;
207 };
208
a65babc9
L		 209enum i386_error
210 {
86e026a4 211 operand_size_mismatch,
a65babc9
L		 212 operand_type_mismatch,
213 register_type_mismatch,
214 number_of_operands_mismatch,
215 invalid_instruction_suffix,
216 bad_imm4,
217 old_gcc_only,
218 unsupported_with_intel_mnemonic,
219 unsupported_syntax,
220 unsupported
221 };
222
252b5132
RH		 223struct _i386_insn
224 {
47926f60 225 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 226 insn_template tm;
252b5132 227
7d5e4556
L		 228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
252b5132
RH		 230 char suffix;
231
47926f60 232 /* OPERANDS gives the number of given operands. */
252b5132
RH		 233 unsigned int operands;
234
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
47926f60 237 operands. */
252b5132
RH		 238 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
239
240 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 241 use OP[i] for the corresponding operand. */
40fb9820 242 i386_operand_type types[MAX_OPERANDS];
252b5132 243
520dc8e8
AM		 244 /* Displacement expression, immediate expression, or register for each
245 operand. */
246 union i386_op op[MAX_OPERANDS];
252b5132 247
3e73aa7c
JH		 248 /* Flags for operands. */
249 unsigned int flags[MAX_OPERANDS];
250#define Operand_PCrel 1
251
252b5132 252 /* Relocation type for operand */
f86103b7 253 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 254
252b5132
RH		 255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry *base_reg;
258 const reg_entry *index_reg;
259 unsigned int log2_scale_factor;
260
261 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 262 explicit segment overrides are given. */
ce8a8b2f 263 const seg_entry *seg[2];
252b5132
RH		 264
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes;
268 unsigned char prefix[MAX_PREFIXES];
269
270 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 271 addressing modes of this insn are encoded. */
252b5132 272 modrm_byte rm;
3e73aa7c 273 rex_byte rex;
252b5132 274 sib_byte sib;
c0f3af97 275 vex_prefix vex;
b6169b20
L		 276
277 /* Swap operand in encoding. */
4473e004 278 unsigned int swap_operand;
891edac4 279
f8a5c266
L		 280 /* Force 32bit displacement in encoding. */
281 unsigned int disp32_encoding;
282
891edac4 283 /* Error message. */
a65babc9 284 enum i386_error error;
252b5132
RH		 285 };
286
287typedef struct _i386_insn i386_insn;
288
289/* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
32137342 291const char extra_symbol_chars[] = "*%-(["
252b5132 292#ifdef LEX_AT
32137342
NC		 293 "@"
294#endif
295#ifdef LEX_QM
296 "?"
252b5132 297#endif
32137342 298 ;
252b5132 299
29b0f896
AM		 300#if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 302 && !defined (TE_GNU) \
29b0f896 303 && !defined (TE_LINUX) \
32137342 304 && !defined (TE_NETWARE) \
29b0f896
AM		 305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
252b5132 307/* This array holds the chars that always start a comment. If the
b3b91714
AM		 308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310const char *i386_comment_chars = "#/";
311#define SVR4_COMMENT_CHARS 1
252b5132 312#define PREFIX_SEPARATOR '\\'
252b5132 313
b3b91714
AM		 314#else
315const char *i386_comment_chars = "#";
316#define PREFIX_SEPARATOR '/'
317#endif
318
252b5132
RH		 319/* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 323 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
252b5132 326 '/' isn't otherwise defined. */
b3b91714 327const char line_comment_chars[] = "#/";
252b5132 328
63a0b638 329const char line_separator_chars[] = ";";
252b5132 330
ce8a8b2f
AM		 331/* Chars that can be used to separate mant from exp in floating point
332 nums. */
252b5132
RH		 333const char EXP_CHARS[] = "eE";
334
ce8a8b2f
AM		 335/* Chars that mean this number is a floating point constant
336 As in 0f12.456
337 or 0d1.2345e12. */
252b5132
RH		 338const char FLT_CHARS[] = "fFdDxX";
339
ce8a8b2f 340/* Tables for lexical analysis. */
252b5132
RH		 341static char mnemonic_chars[256];
342static char register_chars[256];
343static char operand_chars[256];
344static char identifier_chars[256];
345static char digit_chars[256];
346
ce8a8b2f 347/* Lexical macros. */
252b5132
RH		 348#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349#define is_operand_char(x) (operand_chars[(unsigned char) x])
350#define is_register_char(x) (register_chars[(unsigned char) x])
351#define is_space_char(x) ((x) == ' ')
352#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353#define is_digit_char(x) (digit_chars[(unsigned char) x])
354
0234cb7c 355/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 356static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
357
358/* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
47926f60 361 assembler instruction). */
252b5132 362static char save_stack[32];
ce8a8b2f 363static char *save_stack_p;
252b5132
RH		 364#define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366#define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
368
47926f60 369/* The instruction we're assembling. */
252b5132
RH		 370static i386_insn i;
371
372/* Possible templates for current insn. */
373static const templates *current_templates;
374
31b2323c
L		 375/* Per instruction expressionS buffers: max displacements & immediates. */
376static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
377static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 378
47926f60 379/* Current operand we are working on. */
ee86248c 380static int this_operand = -1;
252b5132 381
3e73aa7c
JH		 382/* We support four different modes. FLAG_CODE variable is used to distinguish
383 these. */
384
385enum flag_code {
386 CODE_32BIT,
387 CODE_16BIT,
388 CODE_64BIT };
389
390static enum flag_code flag_code;
4fa24527 391static unsigned int object_64bit;
3e73aa7c
JH		 392static int use_rela_relocations = 0;
393
394/* The names used to print error messages. */
b77a7acd 395static const char *flag_code_names[] =
3e73aa7c
JH		 396 {
397 "32",
398 "16",
399 "64"
400 };
252b5132 401
47926f60
KH		 402/* 1 for intel syntax,
403 0 if att syntax. */
404static int intel_syntax = 0;
252b5132 405
1efbbeb4
L		 406/* 1 for intel mnemonic,
407 0 if att mnemonic. */
408static int intel_mnemonic = !SYSV386_COMPAT;
409
5209009a 410/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 411static int old_gcc = OLDGCC_COMPAT;
412
a60de03c
JB		 413/* 1 if pseudo registers are permitted. */
414static int allow_pseudo_reg = 0;
415
47926f60
KH		 416/* 1 if register prefix % not required. */
417static int allow_naked_reg = 0;
252b5132 418
ba104c83 419/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 420static int allow_index_reg = 0;
421
daf50ae7
L		 422static enum
423 {
424 sse_check_none = 0,
425 sse_check_warning,
426 sse_check_error
427 }
428sse_check;
429
2ca3ace5
L		 430/* Register prefix used for error message. */
431static const char *register_prefix = "%";
432
47926f60
KH		 433/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436static char stackop_size = '\0';
eecb386c 437
12b55ccc
L		 438/* Non-zero to optimize code alignment. */
439int optimize_align_code = 1;
440
47926f60
KH		 441/* Non-zero to quieten some warnings. */
442static int quiet_warnings = 0;
a38cf1db 443
47926f60
KH		 444/* CPU name. */
445static const char *cpu_arch_name = NULL;
6305a203 446static char *cpu_sub_arch_name = NULL;
a38cf1db 447
47926f60 448/* CPU feature flags. */
40fb9820
L		 449static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
450
ccc9c027
L		 451/* If we have selected a cpu we are generating instructions for. */
452static int cpu_arch_tune_set = 0;
453
9103f4f4 454/* Cpu we are generating instructions for. */
fbf3f584 455enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 456
457/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 458static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 459
ccc9c027 460/* CPU instruction set architecture used. */
fbf3f584 461enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 462
9103f4f4 463/* CPU feature flags of instruction set architecture used. */
fbf3f584 464i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 465
fddf5b5b
AM		 466/* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468static unsigned int no_cond_jump_promotion = 0;
469
c0f3af97
L		 470/* Encode SSE instructions with VEX prefix. */
471static unsigned int sse2avx;
472
539f890d
L		 473/* Encode scalar AVX instructions with specific vector length. */
474static enum
475 {
476 vex128 = 0,
477 vex256
478 } avxscalar;
479
29b0f896 480/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 481static symbolS *GOT_symbol;
29b0f896 482
a4447b93
RH		 483/* The dwarf2 return column, adjusted for 32 or 64 bit. */
484unsigned int x86_dwarf2_return_column;
485
486/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
487int x86_cie_data_alignment;
488
252b5132 489/* Interface to relax_segment.
fddf5b5b
AM		 490 There are 3 major relax states for 386 jump insns because the
491 different types of jumps add different sizes to frags when we're
492 figuring out what sort of jump to choose to reach a given label. */
252b5132 493
47926f60 494/* Types. */
93c2a809
AM		 495#define UNCOND_JUMP 0
496#define COND_JUMP 1
497#define COND_JUMP86 2
fddf5b5b 498
47926f60 499/* Sizes. */
252b5132
RH		 500#define CODE16 1
501#define SMALL 0
29b0f896 502#define SMALL16 (SMALL | CODE16)
252b5132 503#define BIG 2
29b0f896 504#define BIG16 (BIG | CODE16)
252b5132
RH		 505
506#ifndef INLINE
507#ifdef __GNUC__
508#define INLINE __inline__
509#else
510#define INLINE
511#endif
512#endif
513
fddf5b5b
AM		 514#define ENCODE_RELAX_STATE(type, size) \
515 ((relax_substateT) (((type) << 2) | (size)))
516#define TYPE_FROM_RELAX_STATE(s) \
517 ((s) >> 2)
518#define DISP_SIZE_FROM_RELAX_STATE(s) \
519 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 520
521/* This table is used by relax_frag to promote short jumps to long
522 ones where necessary. SMALL (short) jumps may be promoted to BIG
523 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
524 don't allow a short jump in a 32 bit code segment to be promoted to
525 a 16 bit offset jump because it's slower (requires data size
526 prefix), and doesn't work, unless the destination is in the bottom
527 64k of the code segment (The top 16 bits of eip are zeroed). */
528
529const relax_typeS md_relax_table[] =
530{
24eab124
AM		 531 /* The fields are:
532 1) most positive reach of this state,
533 2) most negative reach of this state,
93c2a809 534 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 535 4) which index into the table to try if we can't fit into this one. */
252b5132 536
fddf5b5b 537 /* UNCOND_JUMP states. */
93c2a809
AM		 538 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
539 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
540 /* dword jmp adds 4 bytes to frag:
541 0 extra opcode bytes, 4 displacement bytes. */
252b5132 542 {0, 0, 4, 0},
93c2a809
AM		 543 /* word jmp adds 2 byte2 to frag:
544 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 545 {0, 0, 2, 0},
546
93c2a809
AM		 547 /* COND_JUMP states. */
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
549 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
550 /* dword conditionals adds 5 bytes to frag:
551 1 extra opcode byte, 4 displacement bytes. */
552 {0, 0, 5, 0},
fddf5b5b 553 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 554 1 extra opcode byte, 2 displacement bytes. */
555 {0, 0, 3, 0},
556
557 /* COND_JUMP86 states. */
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
559 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
560 /* dword conditionals adds 5 bytes to frag:
561 1 extra opcode byte, 4 displacement bytes. */
562 {0, 0, 5, 0},
563 /* word conditionals add 4 bytes to frag:
564 1 displacement byte and a 3 byte long branch insn. */
565 {0, 0, 4, 0}
252b5132
RH		 566};
567
9103f4f4
L		 568static const arch_entry cpu_arch[] =
569{
89507696
JB		 570 /* Do not replace the first two entries - i386_target_format()
571 relies on them being there in this order. */
8a2c8fef 572 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 573 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 574 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 575 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 576 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 577 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 578 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 579 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 580 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 581 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 582 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 583 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 584 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 585 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 586 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 587 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 588 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 589 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 590 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 591 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 592 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 593 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 594 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 595 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 596 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 597 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 598 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 599 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 600 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 601 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 602 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 603 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 604 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 605 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 606 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 607 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 609 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 611 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 613 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 615 CPU_L1OM_FLAGS, 0, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 617 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 619 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 621 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 623 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 625 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 627 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 629 CPU_AMDFAM10_FLAGS, 0, 0 },
68339fdf 630 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
22109423 631 CPU_BDVER1_FLAGS, 0, 0 },
8a2c8fef 632 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 633 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 634 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 635 CPU_287_FLAGS, 0, 0 },
8a2c8fef 636 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 637 CPU_387_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 639 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 640 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 641 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 642 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 643 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 644 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 645 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 646 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 647 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 648 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 649 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 650 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 651 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 652 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 653 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 654 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 655 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 656 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 657 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 658 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 659 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 660 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 661 CPU_AVX_FLAGS, 0, 0 },
8a2c8fef 662 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 663 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 664 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 665 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 666 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 667 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 668 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 669 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 670 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 671 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 672 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 673 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 674 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 675 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 676 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 677 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 678 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 679 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 680 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 681 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 682 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 683 CPU_F16C_FLAGS, 0, 0 },
8a2c8fef 684 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 685 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 686 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 687 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 688 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 689 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 690 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 691 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 692 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 693 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 694 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 695 CPU_EPT_FLAGS, 0, 0 },
8a2c8fef 696 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 697 CPU_CLFLUSH_FLAGS, 0, 0 },
698 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
699 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 700 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 701 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 702 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 703 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 704 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 705 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 706 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 707 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 708 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 709 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 710 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 711 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 712 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 713 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 715 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 716 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 717 CPU_ABM_FLAGS, 0, 0 },
e413e4e9
AM		 718};
719
704209c0 720#ifdef I386COFF
a6c24e68
NC		 721/* Like s_lcomm_internal in gas/read.c but the alignment string
722 is allowed to be optional. */
723
724static symbolS *
725pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
726{
727 addressT align = 0;
728
729 SKIP_WHITESPACE ();
730
7ab9ffdd 731 if (needs_align
a6c24e68
NC		 732 && *input_line_pointer == ',')
733 {
734 align = parse_align (needs_align - 1);
7ab9ffdd 735
a6c24e68
NC		 736 if (align == (addressT) -1)
737 return NULL;
738 }
739 else
740 {
741 if (size >= 8)
742 align = 3;
743 else if (size >= 4)
744 align = 2;
745 else if (size >= 2)
746 align = 1;
747 else
748 align = 0;
749 }
750
751 bss_alloc (symbolP, size, align);
752 return symbolP;
753}
754
704209c0 755static void
a6c24e68
NC		 756pe_lcomm (int needs_align)
757{
758 s_comm_internal (needs_align * 2, pe_lcomm_internal);
759}
704209c0 760#endif
a6c24e68 761
29b0f896
AM		 762const pseudo_typeS md_pseudo_table[] =
763{
764#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
765 {"align", s_align_bytes, 0},
766#else
767 {"align", s_align_ptwo, 0},
768#endif
769 {"arch", set_cpu_arch, 0},
770#ifndef I386COFF
771 {"bss", s_bss, 0},
a6c24e68
NC		 772#else
773 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 774#endif
775 {"ffloat", float_cons, 'f'},
776 {"dfloat", float_cons, 'd'},
777 {"tfloat", float_cons, 'x'},
778 {"value", cons, 2},
d182319b 779 {"slong", signed_cons, 4},
29b0f896
AM		 780 {"noopt", s_ignore, 0},
781 {"optim", s_ignore, 0},
782 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
783 {"code16", set_code_flag, CODE_16BIT},
784 {"code32", set_code_flag, CODE_32BIT},
785 {"code64", set_code_flag, CODE_64BIT},
786 {"intel_syntax", set_intel_syntax, 1},
787 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 788 {"intel_mnemonic", set_intel_mnemonic, 1},
789 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 790 {"allow_index_reg", set_allow_index_reg, 1},
791 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 792 {"sse_check", set_sse_check, 0},
3b22753a
L		 793#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
794 {"largecomm", handle_large_common, 0},
07a53e5c 795#else
e3bb37b5 796 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 797 {"loc", dwarf2_directive_loc, 0},
798 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 799#endif
6482c264
NC		 800#ifdef TE_PE
801 {"secrel32", pe_directive_secrel, 0},
802#endif
29b0f896
AM		 803 {0, 0, 0}
804};
805
806/* For interface with expression (). */
807extern char *input_line_pointer;
808
809/* Hash table for instruction mnemonic lookup. */
810static struct hash_control *op_hash;
811
812/* Hash table for register lookup. */
813static struct hash_control *reg_hash;
814\f
252b5132 815void
e3bb37b5 816i386_align_code (fragS *fragP, int count)
252b5132 817{
ce8a8b2f
AM		 818 /* Various efficient no-op patterns for aligning code labels.
819 Note: Don't try to assemble the instructions in the comments.
820 0L and 0w are not legal. */
252b5132
RH		 821 static const char f32_1[] =
822 {0x90}; /* nop */
823 static const char f32_2[] =
ccc9c027 824 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 825 static const char f32_3[] =
826 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
827 static const char f32_4[] =
828 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
829 static const char f32_5[] =
830 {0x90, /* nop */
831 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
832 static const char f32_6[] =
833 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
834 static const char f32_7[] =
835 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
836 static const char f32_8[] =
837 {0x90, /* nop */
838 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
839 static const char f32_9[] =
840 {0x89,0xf6, /* movl %esi,%esi */
841 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
842 static const char f32_10[] =
843 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
844 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
845 static const char f32_11[] =
846 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
847 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
848 static const char f32_12[] =
849 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
850 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
851 static const char f32_13[] =
852 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
853 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
854 static const char f32_14[] =
855 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
856 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 857 static const char f16_3[] =
858 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 859 static const char f16_4[] =
860 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
861 static const char f16_5[] =
862 {0x90, /* nop */
863 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
864 static const char f16_6[] =
865 {0x89,0xf6, /* mov %si,%si */
866 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
867 static const char f16_7[] =
868 {0x8d,0x74,0x00, /* lea 0(%si),%si */
869 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
870 static const char f16_8[] =
871 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
872 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 873 static const char jump_31[] =
874 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
875 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
876 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
877 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 878 static const char *const f32_patt[] = {
879 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 880 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 881 };
882 static const char *const f16_patt[] = {
76bc74dc 883 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 884 };
ccc9c027
L		 885 /* nopl (%[re]ax) */
886 static const char alt_3[] =
887 {0x0f,0x1f,0x00};
888 /* nopl 0(%[re]ax) */
889 static const char alt_4[] =
890 {0x0f,0x1f,0x40,0x00};
891 /* nopl 0(%[re]ax,%[re]ax,1) */
892 static const char alt_5[] =
893 {0x0f,0x1f,0x44,0x00,0x00};
894 /* nopw 0(%[re]ax,%[re]ax,1) */
895 static const char alt_6[] =
896 {0x66,0x0f,0x1f,0x44,0x00,0x00};
897 /* nopl 0L(%[re]ax) */
898 static const char alt_7[] =
899 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
900 /* nopl 0L(%[re]ax,%[re]ax,1) */
901 static const char alt_8[] =
902 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
903 /* nopw 0L(%[re]ax,%[re]ax,1) */
904 static const char alt_9[] =
905 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
906 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
907 static const char alt_10[] =
908 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
909 /* data16
910 nopw %cs:0L(%[re]ax,%[re]ax,1) */
911 static const char alt_long_11[] =
912 {0x66,
913 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
914 /* data16
915 data16
916 nopw %cs:0L(%[re]ax,%[re]ax,1) */
917 static const char alt_long_12[] =
918 {0x66,
919 0x66,
920 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
921 /* data16
922 data16
923 data16
924 nopw %cs:0L(%[re]ax,%[re]ax,1) */
925 static const char alt_long_13[] =
926 {0x66,
927 0x66,
928 0x66,
929 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
930 /* data16
931 data16
932 data16
933 data16
934 nopw %cs:0L(%[re]ax,%[re]ax,1) */
935 static const char alt_long_14[] =
936 {0x66,
937 0x66,
938 0x66,
939 0x66,
940 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
941 /* data16
942 data16
943 data16
944 data16
945 data16
946 nopw %cs:0L(%[re]ax,%[re]ax,1) */
947 static const char alt_long_15[] =
948 {0x66,
949 0x66,
950 0x66,
951 0x66,
952 0x66,
953 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
954 /* nopl 0(%[re]ax,%[re]ax,1)
955 nopw 0(%[re]ax,%[re]ax,1) */
956 static const char alt_short_11[] =
957 {0x0f,0x1f,0x44,0x00,0x00,
958 0x66,0x0f,0x1f,0x44,0x00,0x00};
959 /* nopw 0(%[re]ax,%[re]ax,1)
960 nopw 0(%[re]ax,%[re]ax,1) */
961 static const char alt_short_12[] =
962 {0x66,0x0f,0x1f,0x44,0x00,0x00,
963 0x66,0x0f,0x1f,0x44,0x00,0x00};
964 /* nopw 0(%[re]ax,%[re]ax,1)
965 nopl 0L(%[re]ax) */
966 static const char alt_short_13[] =
967 {0x66,0x0f,0x1f,0x44,0x00,0x00,
968 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
969 /* nopl 0L(%[re]ax)
970 nopl 0L(%[re]ax) */
971 static const char alt_short_14[] =
972 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
973 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
974 /* nopl 0L(%[re]ax)
975 nopl 0L(%[re]ax,%[re]ax,1) */
976 static const char alt_short_15[] =
977 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
978 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
979 static const char *const alt_short_patt[] = {
980 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
981 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
982 alt_short_14, alt_short_15
983 };
984 static const char *const alt_long_patt[] = {
985 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
986 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
987 alt_long_14, alt_long_15
988 };
252b5132 989
76bc74dc
L		 990 /* Only align for at least a positive non-zero boundary. */
991 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 992 return;
3e73aa7c 993
ccc9c027
L		 994 /* We need to decide which NOP sequence to use for 32bit and
995 64bit. When -mtune= is used:
4eed87de 996
76bc74dc
L		 997 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
998 PROCESSOR_GENERIC32, f32_patt will be used.
999 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1000 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1001 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1002 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 1003 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 1004 will be used.
ccc9c027 1005
76bc74dc 1006 When -mtune= isn't used, alt_long_patt will be used if
22109423 1007 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1008 be used.
ccc9c027
L		 1009
1010 When -march= or .arch is used, we can't use anything beyond
1011 cpu_arch_isa_flags. */
1012
1013 if (flag_code == CODE_16BIT)
1014 {
ccc9c027 1015 if (count > 8)
33fef721 1016 {
76bc74dc
L		 1017 memcpy (fragP->fr_literal + fragP->fr_fix,
1018 jump_31, count);
1019 /* Adjust jump offset. */
1020 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1021 }
76bc74dc
L		 1022 else
1023 memcpy (fragP->fr_literal + fragP->fr_fix,
1024 f16_patt[count - 1], count);
252b5132 1025 }
33fef721 1026 else
ccc9c027
L		 1027 {
1028 const char *const *patt = NULL;
1029
fbf3f584 1030 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1031 {
1032 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1033 switch (cpu_arch_tune)
1034 {
1035 case PROCESSOR_UNKNOWN:
1036 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1037 optimize with nops. */
1038 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1039 patt = alt_long_patt;
ccc9c027
L		 1040 else
1041 patt = f32_patt;
1042 break;
ccc9c027
L		 1043 case PROCESSOR_PENTIUMPRO:
1044 case PROCESSOR_PENTIUM4:
1045 case PROCESSOR_NOCONA:
ef05d495 1046 case PROCESSOR_CORE:
76bc74dc 1047 case PROCESSOR_CORE2:
bd5295b2 1048 case PROCESSOR_COREI7:
3632d14b 1049 case PROCESSOR_L1OM:
76bc74dc
L		 1050 case PROCESSOR_GENERIC64:
1051 patt = alt_long_patt;
1052 break;
ccc9c027
L		 1053 case PROCESSOR_K6:
1054 case PROCESSOR_ATHLON:
1055 case PROCESSOR_K8:
4eed87de 1056 case PROCESSOR_AMDFAM10:
68339fdf 1057 case PROCESSOR_BDVER1:
ccc9c027
L		 1058 patt = alt_short_patt;
1059 break;
76bc74dc 1060 case PROCESSOR_I386:
ccc9c027
L		 1061 case PROCESSOR_I486:
1062 case PROCESSOR_PENTIUM:
1063 case PROCESSOR_GENERIC32:
1064 patt = f32_patt;
1065 break;
4eed87de 1066 }
ccc9c027
L		 1067 }
1068 else
1069 {
fbf3f584 1070 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1071 {
1072 case PROCESSOR_UNKNOWN:
e6a14101 1073 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1074 PROCESSOR_UNKNOWN. */
1075 abort ();
1076 break;
1077
76bc74dc 1078 case PROCESSOR_I386:
ccc9c027
L		 1079 case PROCESSOR_I486:
1080 case PROCESSOR_PENTIUM:
ccc9c027
L		 1081 case PROCESSOR_K6:
1082 case PROCESSOR_ATHLON:
1083 case PROCESSOR_K8:
4eed87de 1084 case PROCESSOR_AMDFAM10:
68339fdf 1085 case PROCESSOR_BDVER1:
ccc9c027
L		 1086 case PROCESSOR_GENERIC32:
1087 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1088 with nops. */
1089 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1090 patt = alt_short_patt;
1091 else
1092 patt = f32_patt;
1093 break;
76bc74dc
L		 1094 case PROCESSOR_PENTIUMPRO:
1095 case PROCESSOR_PENTIUM4:
1096 case PROCESSOR_NOCONA:
1097 case PROCESSOR_CORE:
ef05d495 1098 case PROCESSOR_CORE2:
bd5295b2 1099 case PROCESSOR_COREI7:
3632d14b 1100 case PROCESSOR_L1OM:
22109423 1101 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1102 patt = alt_long_patt;
1103 else
1104 patt = f32_patt;
1105 break;
1106 case PROCESSOR_GENERIC64:
76bc74dc 1107 patt = alt_long_patt;
ccc9c027 1108 break;
4eed87de 1109 }
ccc9c027
L		 1110 }
1111
76bc74dc
L		 1112 if (patt == f32_patt)
1113 {
1114 /* If the padding is less than 15 bytes, we use the normal
1115 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1116 its offset. */
1117 int limit;
76ba9986 1118
711eedef
L		 1119 /* For 64bit, the limit is 3 bytes. */
1120 if (flag_code == CODE_64BIT
1121 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1122 limit = 3;
1123 else
1124 limit = 15;
1125 if (count < limit)
76bc74dc
L		 1126 memcpy (fragP->fr_literal + fragP->fr_fix,
1127 patt[count - 1], count);
1128 else
1129 {
1130 memcpy (fragP->fr_literal + fragP->fr_fix,
1131 jump_31, count);
1132 /* Adjust jump offset. */
1133 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1134 }
1135 }
1136 else
1137 {
1138 /* Maximum length of an instruction is 15 byte. If the
1139 padding is greater than 15 bytes and we don't use jump,
1140 we have to break it into smaller pieces. */
1141 int padding = count;
1142 while (padding > 15)
1143 {
1144 padding -= 15;
1145 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1146 patt [14], 15);
1147 }
1148
1149 if (padding)
1150 memcpy (fragP->fr_literal + fragP->fr_fix,
1151 patt [padding - 1], padding);
1152 }
ccc9c027 1153 }
33fef721 1154 fragP->fr_var = count;
252b5132
RH		 1155}
1156
c6fb90c8 1157static INLINE int
0dfbf9d7 1158operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1159{
0dfbf9d7 1160 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1161 {
1162 case 3:
0dfbf9d7 1163 if (x->array[2])
c6fb90c8
L		 1164 return 0;
1165 case 2:
0dfbf9d7 1166 if (x->array[1])
c6fb90c8
L		 1167 return 0;
1168 case 1:
0dfbf9d7 1169 return !x->array[0];
c6fb90c8
L		 1170 default:
1171 abort ();
1172 }
40fb9820
L		 1173}
1174
c6fb90c8 1175static INLINE void
0dfbf9d7 1176operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1177{
0dfbf9d7 1178 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1179 {
1180 case 3:
0dfbf9d7 1181 x->array[2] = v;
c6fb90c8 1182 case 2:
0dfbf9d7 1183 x->array[1] = v;
c6fb90c8 1184 case 1:
0dfbf9d7 1185 x->array[0] = v;
c6fb90c8
L		 1186 break;
1187 default:
1188 abort ();
1189 }
1190}
40fb9820 1191
c6fb90c8 1192static INLINE int
0dfbf9d7
L		 1193operand_type_equal (const union i386_operand_type *x,
1194 const union i386_operand_type *y)
c6fb90c8 1195{
0dfbf9d7 1196 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1197 {
1198 case 3:
0dfbf9d7 1199 if (x->array[2] != y->array[2])
c6fb90c8
L		 1200 return 0;
1201 case 2:
0dfbf9d7 1202 if (x->array[1] != y->array[1])
c6fb90c8
L		 1203 return 0;
1204 case 1:
0dfbf9d7 1205 return x->array[0] == y->array[0];
c6fb90c8
L		 1206 break;
1207 default:
1208 abort ();
1209 }
1210}
40fb9820 1211
0dfbf9d7
L		 1212static INLINE int
1213cpu_flags_all_zero (const union i386_cpu_flags *x)
1214{
1215 switch (ARRAY_SIZE(x->array))
1216 {
1217 case 3:
1218 if (x->array[2])
1219 return 0;
1220 case 2:
1221 if (x->array[1])
1222 return 0;
1223 case 1:
1224 return !x->array[0];
1225 default:
1226 abort ();
1227 }
1228}
1229
1230static INLINE void
1231cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1232{
1233 switch (ARRAY_SIZE(x->array))
1234 {
1235 case 3:
1236 x->array[2] = v;
1237 case 2:
1238 x->array[1] = v;
1239 case 1:
1240 x->array[0] = v;
1241 break;
1242 default:
1243 abort ();
1244 }
1245}
1246
1247static INLINE int
1248cpu_flags_equal (const union i386_cpu_flags *x,
1249 const union i386_cpu_flags *y)
1250{
1251 switch (ARRAY_SIZE(x->array))
1252 {
1253 case 3:
1254 if (x->array[2] != y->array[2])
1255 return 0;
1256 case 2:
1257 if (x->array[1] != y->array[1])
1258 return 0;
1259 case 1:
1260 return x->array[0] == y->array[0];
1261 break;
1262 default:
1263 abort ();
1264 }
1265}
c6fb90c8
L		 1266
1267static INLINE int
1268cpu_flags_check_cpu64 (i386_cpu_flags f)
1269{
1270 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1271 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1272}
1273
c6fb90c8
L		 1274static INLINE i386_cpu_flags
1275cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1276{
c6fb90c8
L		 1277 switch (ARRAY_SIZE (x.array))
1278 {
1279 case 3:
1280 x.array [2] &= y.array [2];
1281 case 2:
1282 x.array [1] &= y.array [1];
1283 case 1:
1284 x.array [0] &= y.array [0];
1285 break;
1286 default:
1287 abort ();
1288 }
1289 return x;
1290}
40fb9820 1291
c6fb90c8
L		 1292static INLINE i386_cpu_flags
1293cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1294{
c6fb90c8 1295 switch (ARRAY_SIZE (x.array))
40fb9820 1296 {
c6fb90c8
L		 1297 case 3:
1298 x.array [2] |= y.array [2];
1299 case 2:
1300 x.array [1] |= y.array [1];
1301 case 1:
1302 x.array [0] |= y.array [0];
40fb9820
L		 1303 break;
1304 default:
1305 abort ();
1306 }
40fb9820
L		 1307 return x;
1308}
1309
309d3373
JB		 1310static INLINE i386_cpu_flags
1311cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1312{
1313 switch (ARRAY_SIZE (x.array))
1314 {
1315 case 3:
1316 x.array [2] &= ~y.array [2];
1317 case 2:
1318 x.array [1] &= ~y.array [1];
1319 case 1:
1320 x.array [0] &= ~y.array [0];
1321 break;
1322 default:
1323 abort ();
1324 }
1325 return x;
1326}
1327
c0f3af97
L		 1328#define CPU_FLAGS_ARCH_MATCH 0x1
1329#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1330#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1331#define CPU_FLAGS_PCLMUL_MATCH 0x8
1332#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1333
a5ff0eb2 1334#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1335 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1336 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1337#define CPU_FLAGS_PERFECT_MATCH \
1338 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1339
1340/* Return CPU flags match bits. */
3629bb00 1341
40fb9820 1342static int
d3ce72d0 1343cpu_flags_match (const insn_template *t)
40fb9820 1344{
c0f3af97
L		 1345 i386_cpu_flags x = t->cpu_flags;
1346 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1347
1348 x.bitfield.cpu64 = 0;
1349 x.bitfield.cpuno64 = 0;
1350
0dfbf9d7 1351 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1352 {
1353 /* This instruction is available on all archs. */
1354 match |= CPU_FLAGS_32BIT_MATCH;
1355 }
3629bb00
L		 1356 else
1357 {
c0f3af97 1358 /* This instruction is available only on some archs. */
3629bb00
L		 1359 i386_cpu_flags cpu = cpu_arch_flags;
1360
1361 cpu.bitfield.cpu64 = 0;
1362 cpu.bitfield.cpuno64 = 0;
1363 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1364 if (!cpu_flags_all_zero (&cpu))
1365 {
a5ff0eb2
L		 1366 if (x.bitfield.cpuavx)
1367 {
ce2f5b3c 1368 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1369 if (cpu.bitfield.cpuavx)
1370 {
1371 /* Check SSE2AVX. */
1372 if (!t->opcode_modifier.sse2avx|| sse2avx)
1373 {
1374 match |= (CPU_FLAGS_ARCH_MATCH
1375 | CPU_FLAGS_AVX_MATCH);
1376 /* Check AES. */
1377 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1378 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1379 /* Check PCLMUL. */
1380 if (!x.bitfield.cpupclmul
1381 || cpu.bitfield.cpupclmul)
1382 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1383 }
1384 }
1385 else
1386 match |= CPU_FLAGS_ARCH_MATCH;
1387 }
1388 else
c0f3af97
L		 1389 match |= CPU_FLAGS_32BIT_MATCH;
1390 }
3629bb00 1391 }
c0f3af97 1392 return match;
40fb9820
L		 1393}
1394
c6fb90c8
L		 1395static INLINE i386_operand_type
1396operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1397{
c6fb90c8
L		 1398 switch (ARRAY_SIZE (x.array))
1399 {
1400 case 3:
1401 x.array [2] &= y.array [2];
1402 case 2:
1403 x.array [1] &= y.array [1];
1404 case 1:
1405 x.array [0] &= y.array [0];
1406 break;
1407 default:
1408 abort ();
1409 }
1410 return x;
40fb9820
L		 1411}
1412
c6fb90c8
L		 1413static INLINE i386_operand_type
1414operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1415{
c6fb90c8 1416 switch (ARRAY_SIZE (x.array))
40fb9820 1417 {
c6fb90c8
L		 1418 case 3:
1419 x.array [2] |= y.array [2];
1420 case 2:
1421 x.array [1] |= y.array [1];
1422 case 1:
1423 x.array [0] |= y.array [0];
40fb9820
L		 1424 break;
1425 default:
1426 abort ();
1427 }
c6fb90c8
L		 1428 return x;
1429}
40fb9820 1430
c6fb90c8
L		 1431static INLINE i386_operand_type
1432operand_type_xor (i386_operand_type x, i386_operand_type y)
1433{
1434 switch (ARRAY_SIZE (x.array))
1435 {
1436 case 3:
1437 x.array [2] ^= y.array [2];
1438 case 2:
1439 x.array [1] ^= y.array [1];
1440 case 1:
1441 x.array [0] ^= y.array [0];
1442 break;
1443 default:
1444 abort ();
1445 }
40fb9820
L		 1446 return x;
1447}
1448
1449static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1450static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1451static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1452static const i386_operand_type inoutportreg
1453 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1454static const i386_operand_type reg16_inoutportreg
1455 = OPERAND_TYPE_REG16_INOUTPORTREG;
1456static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1457static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1458static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1459static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1460static const i386_operand_type anydisp
1461 = OPERAND_TYPE_ANYDISP;
40fb9820 1462static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1463static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1464static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1465static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1466static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1467static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1468static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1469static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1470static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1471static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1472static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1473static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1474
1475enum operand_type
1476{
1477 reg,
40fb9820
L		 1478 imm,
1479 disp,
1480 anymem
1481};
1482
c6fb90c8 1483static INLINE int
40fb9820
L		 1484operand_type_check (i386_operand_type t, enum operand_type c)
1485{
1486 switch (c)
1487 {
1488 case reg:
1489 return (t.bitfield.reg8
1490 || t.bitfield.reg16
1491 || t.bitfield.reg32
1492 || t.bitfield.reg64);
1493
40fb9820
L		 1494 case imm:
1495 return (t.bitfield.imm8
1496 || t.bitfield.imm8s
1497 || t.bitfield.imm16
1498 || t.bitfield.imm32
1499 || t.bitfield.imm32s
1500 || t.bitfield.imm64);
1501
1502 case disp:
1503 return (t.bitfield.disp8
1504 || t.bitfield.disp16
1505 || t.bitfield.disp32
1506 || t.bitfield.disp32s
1507 || t.bitfield.disp64);
1508
1509 case anymem:
1510 return (t.bitfield.disp8
1511 || t.bitfield.disp16
1512 || t.bitfield.disp32
1513 || t.bitfield.disp32s
1514 || t.bitfield.disp64
1515 || t.bitfield.baseindex);
1516
1517 default:
1518 abort ();
1519 }
2cfe26b6
AM		 1520
1521 return 0;
40fb9820
L		 1522}
1523
5c07affc
L		 1524/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1525 operand J for instruction template T. */
1526
1527static INLINE int
d3ce72d0 1528match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1529{
1530 return !((i.types[j].bitfield.byte
1531 && !t->operand_types[j].bitfield.byte)
1532 || (i.types[j].bitfield.word
1533 && !t->operand_types[j].bitfield.word)
1534 || (i.types[j].bitfield.dword
1535 && !t->operand_types[j].bitfield.dword)
1536 || (i.types[j].bitfield.qword
1537 && !t->operand_types[j].bitfield.qword));
1538}
1539
1540/* Return 1 if there is no conflict in any size on operand J for
1541 instruction template T. */
1542
1543static INLINE int
d3ce72d0 1544match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1545{
1546 return (match_reg_size (t, j)
1547 && !((i.types[j].bitfield.unspecified
1548 && !t->operand_types[j].bitfield.unspecified)
1549 || (i.types[j].bitfield.fword
1550 && !t->operand_types[j].bitfield.fword)
1551 || (i.types[j].bitfield.tbyte
1552 && !t->operand_types[j].bitfield.tbyte)
1553 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1554 && !t->operand_types[j].bitfield.xmmword)
1555 || (i.types[j].bitfield.ymmword
1556 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1557}
1558
1559/* Return 1 if there is no size conflict on any operands for
1560 instruction template T. */
1561
1562static INLINE int
d3ce72d0 1563operand_size_match (const insn_template *t)
5c07affc
L		 1564{
1565 unsigned int j;
1566 int match = 1;
1567
1568 /* Don't check jump instructions. */
1569 if (t->opcode_modifier.jump
1570 || t->opcode_modifier.jumpbyte
1571 || t->opcode_modifier.jumpdword
1572 || t->opcode_modifier.jumpintersegment)
1573 return match;
1574
1575 /* Check memory and accumulator operand size. */
1576 for (j = 0; j < i.operands; j++)
1577 {
1578 if (t->operand_types[j].bitfield.anysize)
1579 continue;
1580
1581 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1582 {
1583 match = 0;
1584 break;
1585 }
1586
1587 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1588 {
1589 match = 0;
1590 break;
1591 }
1592 }
1593
891edac4 1594 if (match)
5c07affc 1595 return match;
891edac4
L		 1596 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1597 {
1598mismatch:
86e026a4 1599 i.error = operand_size_mismatch;
891edac4
L		 1600 return 0;
1601 }
5c07affc
L		 1602
1603 /* Check reverse. */
9c2799c2 1604 gas_assert (i.operands == 2);
5c07affc
L		 1605
1606 match = 1;
1607 for (j = 0; j < 2; j++)
1608 {
1609 if (t->operand_types[j].bitfield.acc
1610 && !match_reg_size (t, j ? 0 : 1))
891edac4 1611 goto mismatch;
5c07affc
L		 1612
1613 if (i.types[j].bitfield.mem
1614 && !match_mem_size (t, j ? 0 : 1))
891edac4 1615 goto mismatch;
5c07affc
L		 1616 }
1617
1618 return match;
1619}
1620
c6fb90c8 1621static INLINE int
40fb9820
L		 1622operand_type_match (i386_operand_type overlap,
1623 i386_operand_type given)
1624{
1625 i386_operand_type temp = overlap;
1626
1627 temp.bitfield.jumpabsolute = 0;
7d5e4556 1628 temp.bitfield.unspecified = 0;
5c07affc
L		 1629 temp.bitfield.byte = 0;
1630 temp.bitfield.word = 0;
1631 temp.bitfield.dword = 0;
1632 temp.bitfield.fword = 0;
1633 temp.bitfield.qword = 0;
1634 temp.bitfield.tbyte = 0;
1635 temp.bitfield.xmmword = 0;
c0f3af97 1636 temp.bitfield.ymmword = 0;
0dfbf9d7 1637 if (operand_type_all_zero (&temp))
891edac4 1638 goto mismatch;
40fb9820 1639
891edac4
L		 1640 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1641 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1642 return 1;
1643
1644mismatch:
a65babc9 1645 i.error = operand_type_mismatch;
891edac4 1646 return 0;
40fb9820
L		 1647}
1648
7d5e4556 1649/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1650 unless the expected operand type register overlap is null.
1651 Note that Acc in a template matches every size of reg. */
1652
c6fb90c8 1653static INLINE int
40fb9820
L		 1654operand_type_register_match (i386_operand_type m0,
1655 i386_operand_type g0,
1656 i386_operand_type t0,
1657 i386_operand_type m1,
1658 i386_operand_type g1,
1659 i386_operand_type t1)
1660{
1661 if (!operand_type_check (g0, reg))
1662 return 1;
1663
1664 if (!operand_type_check (g1, reg))
1665 return 1;
1666
1667 if (g0.bitfield.reg8 == g1.bitfield.reg8
1668 && g0.bitfield.reg16 == g1.bitfield.reg16
1669 && g0.bitfield.reg32 == g1.bitfield.reg32
1670 && g0.bitfield.reg64 == g1.bitfield.reg64)
1671 return 1;
1672
1673 if (m0.bitfield.acc)
1674 {
1675 t0.bitfield.reg8 = 1;
1676 t0.bitfield.reg16 = 1;
1677 t0.bitfield.reg32 = 1;
1678 t0.bitfield.reg64 = 1;
1679 }
1680
1681 if (m1.bitfield.acc)
1682 {
1683 t1.bitfield.reg8 = 1;
1684 t1.bitfield.reg16 = 1;
1685 t1.bitfield.reg32 = 1;
1686 t1.bitfield.reg64 = 1;
1687 }
1688
891edac4
L		 1689 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1690 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1691 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1692 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1693 return 1;
1694
a65babc9 1695 i.error = register_type_mismatch;
891edac4
L		 1696
1697 return 0;
40fb9820
L		 1698}
1699
252b5132 1700static INLINE unsigned int
40fb9820 1701mode_from_disp_size (i386_operand_type t)
252b5132 1702{
40fb9820
L		 1703 if (t.bitfield.disp8)
1704 return 1;
1705 else if (t.bitfield.disp16
1706 || t.bitfield.disp32
1707 || t.bitfield.disp32s)
1708 return 2;
1709 else
1710 return 0;
252b5132
RH		 1711}
1712
1713static INLINE int
e3bb37b5 1714fits_in_signed_byte (offsetT num)
252b5132
RH		 1715{
1716 return (num >= -128) && (num <= 127);
47926f60 1717}
252b5132
RH		 1718
1719static INLINE int
e3bb37b5 1720fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1721{
1722 return (num & 0xff) == num;
47926f60 1723}
252b5132
RH		 1724
1725static INLINE int
e3bb37b5 1726fits_in_unsigned_word (offsetT num)
252b5132
RH		 1727{
1728 return (num & 0xffff) == num;
47926f60 1729}
252b5132
RH		 1730
1731static INLINE int
e3bb37b5 1732fits_in_signed_word (offsetT num)
252b5132
RH		 1733{
1734 return (-32768 <= num) && (num <= 32767);
47926f60 1735}
2a962e6d 1736
3e73aa7c 1737static INLINE int
e3bb37b5 1738fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1739{
1740#ifndef BFD64
1741 return 1;
1742#else
1743 return (!(((offsetT) -1 << 31) & num)
1744 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1745#endif
1746} /* fits_in_signed_long() */
2a962e6d 1747
3e73aa7c 1748static INLINE int
e3bb37b5 1749fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1750{
1751#ifndef BFD64
1752 return 1;
1753#else
1754 return (num & (((offsetT) 2 << 31) - 1)) == num;
1755#endif
1756} /* fits_in_unsigned_long() */
252b5132 1757
a683cc34
SP		 1758static INLINE int
1759fits_in_imm4 (offsetT num)
1760{
1761 return (num & 0xf) == num;
1762}
1763
40fb9820 1764static i386_operand_type
e3bb37b5 1765smallest_imm_type (offsetT num)
252b5132 1766{
40fb9820 1767 i386_operand_type t;
7ab9ffdd 1768
0dfbf9d7 1769 operand_type_set (&t, 0);
40fb9820
L		 1770 t.bitfield.imm64 = 1;
1771
1772 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1773 {
1774 /* This code is disabled on the 486 because all the Imm1 forms
1775 in the opcode table are slower on the i486. They're the
1776 versions with the implicitly specified single-position
1777 displacement, which has another syntax if you really want to
1778 use that form. */
40fb9820
L		 1779 t.bitfield.imm1 = 1;
1780 t.bitfield.imm8 = 1;
1781 t.bitfield.imm8s = 1;
1782 t.bitfield.imm16 = 1;
1783 t.bitfield.imm32 = 1;
1784 t.bitfield.imm32s = 1;
1785 }
1786 else if (fits_in_signed_byte (num))
1787 {
1788 t.bitfield.imm8 = 1;
1789 t.bitfield.imm8s = 1;
1790 t.bitfield.imm16 = 1;
1791 t.bitfield.imm32 = 1;
1792 t.bitfield.imm32s = 1;
1793 }
1794 else if (fits_in_unsigned_byte (num))
1795 {
1796 t.bitfield.imm8 = 1;
1797 t.bitfield.imm16 = 1;
1798 t.bitfield.imm32 = 1;
1799 t.bitfield.imm32s = 1;
1800 }
1801 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1802 {
1803 t.bitfield.imm16 = 1;
1804 t.bitfield.imm32 = 1;
1805 t.bitfield.imm32s = 1;
1806 }
1807 else if (fits_in_signed_long (num))
1808 {
1809 t.bitfield.imm32 = 1;
1810 t.bitfield.imm32s = 1;
1811 }
1812 else if (fits_in_unsigned_long (num))
1813 t.bitfield.imm32 = 1;
1814
1815 return t;
47926f60 1816}
252b5132 1817
847f7ad4 1818static offsetT
e3bb37b5 1819offset_in_range (offsetT val, int size)
847f7ad4 1820{
508866be 1821 addressT mask;
ba2adb93 1822
847f7ad4
AM		 1823 switch (size)
1824 {
508866be
L		 1825 case 1: mask = ((addressT) 1 << 8) - 1; break;
1826 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1827 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1828#ifdef BFD64
1829 case 8: mask = ((addressT) 2 << 63) - 1; break;
1830#endif
47926f60 1831 default: abort ();
847f7ad4
AM		 1832 }
1833
9de868bf
L		 1834#ifdef BFD64
1835 /* If BFD64, sign extend val for 32bit address mode. */
1836 if (flag_code != CODE_64BIT
1837 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1838 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1839 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1840#endif
ba2adb93 1841
47926f60 1842 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1843 {
1844 char buf1[40], buf2[40];
1845
1846 sprint_value (buf1, val);
1847 sprint_value (buf2, val & mask);
1848 as_warn (_("%s shortened to %s"), buf1, buf2);
1849 }
1850 return val & mask;
1851}
1852
c32fa91d
L		 1853enum PREFIX_GROUP
1854{
1855 PREFIX_EXIST = 0,
1856 PREFIX_LOCK,
1857 PREFIX_REP,
1858 PREFIX_OTHER
1859};
1860
1861/* Returns
1862 a. PREFIX_EXIST if attempting to add a prefix where one from the
1863 same class already exists.
1864 b. PREFIX_LOCK if lock prefix is added.
1865 c. PREFIX_REP if rep/repne prefix is added.
1866 d. PREFIX_OTHER if other prefix is added.
1867 */
1868
1869static enum PREFIX_GROUP
e3bb37b5 1870add_prefix (unsigned int prefix)
252b5132 1871{
c32fa91d 1872 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1873 unsigned int q;
252b5132 1874
29b0f896
AM		 1875 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1876 && flag_code == CODE_64BIT)
b1905489 1877 {
161a04f6
L		 1878 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1879 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1880 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1881 ret = PREFIX_EXIST;
b1905489
JB		 1882 q = REX_PREFIX;
1883 }
3e73aa7c 1884 else
b1905489
JB		 1885 {
1886 switch (prefix)
1887 {
1888 default:
1889 abort ();
1890
1891 case CS_PREFIX_OPCODE:
1892 case DS_PREFIX_OPCODE:
1893 case ES_PREFIX_OPCODE:
1894 case FS_PREFIX_OPCODE:
1895 case GS_PREFIX_OPCODE:
1896 case SS_PREFIX_OPCODE:
1897 q = SEG_PREFIX;
1898 break;
1899
1900 case REPNE_PREFIX_OPCODE:
1901 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1902 q = REP_PREFIX;
1903 ret = PREFIX_REP;
1904 break;
1905
b1905489 1906 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1907 q = LOCK_PREFIX;
1908 ret = PREFIX_LOCK;
b1905489
JB		 1909 break;
1910
1911 case FWAIT_OPCODE:
1912 q = WAIT_PREFIX;
1913 break;
1914
1915 case ADDR_PREFIX_OPCODE:
1916 q = ADDR_PREFIX;
1917 break;
1918
1919 case DATA_PREFIX_OPCODE:
1920 q = DATA_PREFIX;
1921 break;
1922 }
1923 if (i.prefix[q] != 0)
c32fa91d 1924 ret = PREFIX_EXIST;
b1905489 1925 }
252b5132 1926
b1905489 1927 if (ret)
252b5132 1928 {
b1905489
JB		 1929 if (!i.prefix[q])
1930 ++i.prefixes;
1931 i.prefix[q] |= prefix;
252b5132 1932 }
b1905489
JB		 1933 else
1934 as_bad (_("same type of prefix used twice"));
252b5132 1935
252b5132
RH		 1936 return ret;
1937}
1938
1939static void
78f12dd3 1940update_code_flag (int value, int check)
eecb386c 1941{
78f12dd3
L		 1942 PRINTF_LIKE ((*as_error));
1943
1e9cc1c2 1944 flag_code = (enum flag_code) value;
40fb9820
L		 1945 if (flag_code == CODE_64BIT)
1946 {
1947 cpu_arch_flags.bitfield.cpu64 = 1;
1948 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1949 }
1950 else
1951 {
1952 cpu_arch_flags.bitfield.cpu64 = 0;
1953 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1954 }
1955 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1956 {
78f12dd3
L		 1957 if (check)
1958 as_error = as_fatal;
1959 else
1960 as_error = as_bad;
1961 (*as_error) (_("64bit mode not supported on `%s'."),
1962 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1963 }
40fb9820 1964 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 1965 {
78f12dd3
L		 1966 if (check)
1967 as_error = as_fatal;
1968 else
1969 as_error = as_bad;
1970 (*as_error) (_("32bit mode not supported on `%s'."),
1971 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1972 }
eecb386c
AM		 1973 stackop_size = '\0';
1974}
1975
78f12dd3
L		 1976static void
1977set_code_flag (int value)
1978{
1979 update_code_flag (value, 0);
1980}
1981
eecb386c 1982static void
e3bb37b5 1983set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1984{
1e9cc1c2 1985 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1986 if (flag_code != CODE_16BIT)
1987 abort ();
1988 cpu_arch_flags.bitfield.cpu64 = 0;
1989 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1990 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1991}
1992
1993static void
e3bb37b5 1994set_intel_syntax (int syntax_flag)
252b5132
RH		 1995{
1996 /* Find out if register prefixing is specified. */
1997 int ask_naked_reg = 0;
1998
1999 SKIP_WHITESPACE ();
29b0f896 2000 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2001 {
2002 char *string = input_line_pointer;
2003 int e = get_symbol_end ();
2004
47926f60 2005 if (strcmp (string, "prefix") == 0)
252b5132 2006 ask_naked_reg = 1;
47926f60 2007 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2008 ask_naked_reg = -1;
2009 else
d0b47220 2010 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2011 *input_line_pointer = e;
2012 }
2013 demand_empty_rest_of_line ();
c3332e24 2014
252b5132
RH		 2015 intel_syntax = syntax_flag;
2016
2017 if (ask_naked_reg == 0)
f86103b7
AM		 2018 allow_naked_reg = (intel_syntax
2019 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2020 else
2021 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2022
ee86248c 2023 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2024
e4a3b5a4 2025 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2026 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2027 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2028}
2029
1efbbeb4
L		 2030static void
2031set_intel_mnemonic (int mnemonic_flag)
2032{
e1d4d893 2033 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2034}
2035
db51cc60
L		 2036static void
2037set_allow_index_reg (int flag)
2038{
2039 allow_index_reg = flag;
2040}
2041
cb19c032
L		 2042static void
2043set_sse_check (int dummy ATTRIBUTE_UNUSED)
2044{
2045 SKIP_WHITESPACE ();
2046
2047 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2048 {
2049 char *string = input_line_pointer;
2050 int e = get_symbol_end ();
2051
2052 if (strcmp (string, "none") == 0)
2053 sse_check = sse_check_none;
2054 else if (strcmp (string, "warning") == 0)
2055 sse_check = sse_check_warning;
2056 else if (strcmp (string, "error") == 0)
2057 sse_check = sse_check_error;
2058 else
2059 as_bad (_("bad argument to sse_check directive."));
2060 *input_line_pointer = e;
2061 }
2062 else
2063 as_bad (_("missing argument for sse_check directive"));
2064
2065 demand_empty_rest_of_line ();
2066}
2067
8a9036a4
L		 2068static void
2069check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2070 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2071{
2072#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2073 static const char *arch;
2074
2075 /* Intel LIOM is only supported on ELF. */
2076 if (!IS_ELF)
2077 return;
2078
2079 if (!arch)
2080 {
2081 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2082 use default_arch. */
2083 arch = cpu_arch_name;
2084 if (!arch)
2085 arch = default_arch;
2086 }
2087
3632d14b 2088 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2089 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2090 || new_flag.bitfield.cpul1om)
8a9036a4 2091 return;
76ba9986 2092
8a9036a4
L		 2093 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2094#endif
2095}
2096
e413e4e9 2097static void
e3bb37b5 2098set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2099{
47926f60 2100 SKIP_WHITESPACE ();
e413e4e9 2101
29b0f896 2102 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2103 {
2104 char *string = input_line_pointer;
2105 int e = get_symbol_end ();
91d6fa6a 2106 unsigned int j;
40fb9820 2107 i386_cpu_flags flags;
e413e4e9 2108
91d6fa6a 2109 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2110 {
91d6fa6a 2111 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2112 {
91d6fa6a 2113 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2114
5c6af06e
JB		 2115 if (*string != '.')
2116 {
91d6fa6a 2117 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2118 cpu_sub_arch_name = NULL;
91d6fa6a 2119 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2120 if (flag_code == CODE_64BIT)
2121 {
2122 cpu_arch_flags.bitfield.cpu64 = 1;
2123 cpu_arch_flags.bitfield.cpuno64 = 0;
2124 }
2125 else
2126 {
2127 cpu_arch_flags.bitfield.cpu64 = 0;
2128 cpu_arch_flags.bitfield.cpuno64 = 1;
2129 }
91d6fa6a
NC		 2130 cpu_arch_isa = cpu_arch[j].type;
2131 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2132 if (!cpu_arch_tune_set)
2133 {
2134 cpu_arch_tune = cpu_arch_isa;
2135 cpu_arch_tune_flags = cpu_arch_isa_flags;
2136 }
5c6af06e
JB		 2137 break;
2138 }
40fb9820 2139
22109423 2140 if (!cpu_arch[j].negated)
309d3373 2141 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2142 cpu_arch[j].flags);
309d3373
JB		 2143 else
2144 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2145 cpu_arch[j].flags);
0dfbf9d7 2146 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2147 {
6305a203
L		 2148 if (cpu_sub_arch_name)
2149 {
2150 char *name = cpu_sub_arch_name;
2151 cpu_sub_arch_name = concat (name,
91d6fa6a 2152 cpu_arch[j].name,
1bf57e9f 2153 (const char *) NULL);
6305a203
L		 2154 free (name);
2155 }
2156 else
91d6fa6a 2157 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2158 cpu_arch_flags = flags;
5c6af06e
JB		 2159 }
2160 *input_line_pointer = e;
2161 demand_empty_rest_of_line ();
2162 return;
e413e4e9
AM		 2163 }
2164 }
91d6fa6a 2165 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2166 as_bad (_("no such architecture: `%s'"), string);
2167
2168 *input_line_pointer = e;
2169 }
2170 else
2171 as_bad (_("missing cpu architecture"));
2172
fddf5b5b
AM		 2173 no_cond_jump_promotion = 0;
2174 if (*input_line_pointer == ','
29b0f896 2175 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2176 {
2177 char *string = ++input_line_pointer;
2178 int e = get_symbol_end ();
2179
2180 if (strcmp (string, "nojumps") == 0)
2181 no_cond_jump_promotion = 1;
2182 else if (strcmp (string, "jumps") == 0)
2183 ;
2184 else
2185 as_bad (_("no such architecture modifier: `%s'"), string);
2186
2187 *input_line_pointer = e;
2188 }
2189
e413e4e9
AM		 2190 demand_empty_rest_of_line ();
2191}
2192
8a9036a4
L		 2193enum bfd_architecture
2194i386_arch (void)
2195{
3632d14b 2196 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2197 {
2198 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2199 || flag_code != CODE_64BIT)
2200 as_fatal (_("Intel L1OM is 64bit ELF only"));
2201 return bfd_arch_l1om;
2202 }
2203 else
2204 return bfd_arch_i386;
2205}
2206
b9d79e03
JH		 2207unsigned long
2208i386_mach ()
2209{
2210 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2211 {
3632d14b 2212 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2213 {
2214 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2215 as_fatal (_("Intel L1OM is 64bit ELF only"));
2216 return bfd_mach_l1om;
2217 }
2218 else
2219 return bfd_mach_x86_64;
2220 }
b9d79e03
JH		 2221 else if (!strcmp (default_arch, "i386"))
2222 return bfd_mach_i386_i386;
2223 else
2224 as_fatal (_("Unknown architecture"));
2225}
b9d79e03 2226\f
252b5132
RH		 2227void
2228md_begin ()
2229{
2230 const char *hash_err;
2231
47926f60 2232 /* Initialize op_hash hash table. */
252b5132
RH		 2233 op_hash = hash_new ();
2234
2235 {
d3ce72d0 2236 const insn_template *optab;
29b0f896 2237 templates *core_optab;
252b5132 2238
47926f60
KH		 2239 /* Setup for loop. */
2240 optab = i386_optab;
252b5132
RH		 2241 core_optab = (templates *) xmalloc (sizeof (templates));
2242 core_optab->start = optab;
2243
2244 while (1)
2245 {
2246 ++optab;
2247 if (optab->name == NULL
2248 || strcmp (optab->name, (optab - 1)->name) != 0)
2249 {
2250 /* different name --> ship out current template list;
47926f60 2251 add to hash table; & begin anew. */
252b5132
RH		 2252 core_optab->end = optab;
2253 hash_err = hash_insert (op_hash,
2254 (optab - 1)->name,
5a49b8ac 2255 (void *) core_optab);
252b5132
RH		 2256 if (hash_err)
2257 {
252b5132
RH		 2258 as_fatal (_("Internal Error: Can't hash %s: %s"),
2259 (optab - 1)->name,
2260 hash_err);
2261 }
2262 if (optab->name == NULL)
2263 break;
2264 core_optab = (templates *) xmalloc (sizeof (templates));
2265 core_optab->start = optab;
2266 }
2267 }
2268 }
2269
47926f60 2270 /* Initialize reg_hash hash table. */
252b5132
RH		 2271 reg_hash = hash_new ();
2272 {
29b0f896 2273 const reg_entry *regtab;
c3fe08fa 2274 unsigned int regtab_size = i386_regtab_size;
252b5132 2275
c3fe08fa 2276 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2277 {
5a49b8ac 2278 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2279 if (hash_err)
3e73aa7c
JH		 2280 as_fatal (_("Internal Error: Can't hash %s: %s"),
2281 regtab->reg_name,
2282 hash_err);
252b5132
RH		 2283 }
2284 }
2285
47926f60 2286 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2287 {
29b0f896
AM		 2288 int c;
2289 char *p;
252b5132
RH		 2290
2291 for (c = 0; c < 256; c++)
2292 {
3882b010 2293 if (ISDIGIT (c))
252b5132
RH		 2294 {
2295 digit_chars[c] = c;
2296 mnemonic_chars[c] = c;
2297 register_chars[c] = c;
2298 operand_chars[c] = c;
2299 }
3882b010 2300 else if (ISLOWER (c))
252b5132
RH		 2301 {
2302 mnemonic_chars[c] = c;
2303 register_chars[c] = c;
2304 operand_chars[c] = c;
2305 }
3882b010 2306 else if (ISUPPER (c))
252b5132 2307 {
3882b010 2308 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2309 register_chars[c] = mnemonic_chars[c];
2310 operand_chars[c] = c;
2311 }
2312
3882b010 2313 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2314 identifier_chars[c] = c;
2315 else if (c >= 128)
2316 {
2317 identifier_chars[c] = c;
2318 operand_chars[c] = c;
2319 }
2320 }
2321
2322#ifdef LEX_AT
2323 identifier_chars['@'] = '@';
32137342
NC		 2324#endif
2325#ifdef LEX_QM
2326 identifier_chars['?'] = '?';
2327 operand_chars['?'] = '?';
252b5132 2328#endif
252b5132 2329 digit_chars['-'] = '-';
c0f3af97 2330 mnemonic_chars['_'] = '_';
791fe849 2331 mnemonic_chars['-'] = '-';
0003779b 2332 mnemonic_chars['.'] = '.';
252b5132
RH		 2333 identifier_chars['_'] = '_';
2334 identifier_chars['.'] = '.';
2335
2336 for (p = operand_special_chars; *p != '\0'; p++)
2337 operand_chars[(unsigned char) *p] = *p;
2338 }
2339
2340#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2341 if (IS_ELF)
252b5132
RH		 2342 {
2343 record_alignment (text_section, 2);
2344 record_alignment (data_section, 2);
2345 record_alignment (bss_section, 2);
2346 }
2347#endif
a4447b93
RH		 2348
2349 if (flag_code == CODE_64BIT)
2350 {
2351 x86_dwarf2_return_column = 16;
2352 x86_cie_data_alignment = -8;
2353 }
2354 else
2355 {
2356 x86_dwarf2_return_column = 8;
2357 x86_cie_data_alignment = -4;
2358 }
252b5132
RH		 2359}
2360
2361void
e3bb37b5 2362i386_print_statistics (FILE *file)
252b5132
RH		 2363{
2364 hash_print_statistics (file, "i386 opcode", op_hash);
2365 hash_print_statistics (file, "i386 register", reg_hash);
2366}
2367\f
252b5132
RH		 2368#ifdef DEBUG386
2369
ce8a8b2f 2370/* Debugging routines for md_assemble. */
d3ce72d0 2371static void pte (insn_template *);
40fb9820 2372static void pt (i386_operand_type);
e3bb37b5
L		 2373static void pe (expressionS *);
2374static void ps (symbolS *);
252b5132
RH		 2375
2376static void
e3bb37b5 2377pi (char *line, i386_insn *x)
252b5132 2378{
09137c09 2379 unsigned int j;
252b5132
RH		 2380
2381 fprintf (stdout, "%s: template ", line);
2382 pte (&x->tm);
09f131f2
JH		 2383 fprintf (stdout, " address: base %s index %s scale %x\n",
2384 x->base_reg ? x->base_reg->reg_name : "none",
2385 x->index_reg ? x->index_reg->reg_name : "none",
2386 x->log2_scale_factor);
2387 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2388 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2389 fprintf (stdout, " sib: base %x index %x scale %x\n",
2390 x->sib.base, x->sib.index, x->sib.scale);
2391 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2392 (x->rex & REX_W) != 0,
2393 (x->rex & REX_R) != 0,
2394 (x->rex & REX_X) != 0,
2395 (x->rex & REX_B) != 0);
09137c09 2396 for (j = 0; j < x->operands; j++)
252b5132 2397 {
09137c09
SP		 2398 fprintf (stdout, " #%d: ", j + 1);
2399 pt (x->types[j]);
252b5132 2400 fprintf (stdout, "\n");
09137c09
SP		 2401 if (x->types[j].bitfield.reg8
2402 || x->types[j].bitfield.reg16
2403 || x->types[j].bitfield.reg32
2404 || x->types[j].bitfield.reg64
2405 || x->types[j].bitfield.regmmx
2406 || x->types[j].bitfield.regxmm
2407 || x->types[j].bitfield.regymm
2408 || x->types[j].bitfield.sreg2
2409 || x->types[j].bitfield.sreg3
2410 || x->types[j].bitfield.control
2411 || x->types[j].bitfield.debug
2412 || x->types[j].bitfield.test)
2413 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2414 if (operand_type_check (x->types[j], imm))
2415 pe (x->op[j].imms);
2416 if (operand_type_check (x->types[j], disp))
2417 pe (x->op[j].disps);
252b5132
RH		 2418 }
2419}
2420
2421static void
d3ce72d0 2422pte (insn_template *t)
252b5132 2423{
09137c09 2424 unsigned int j;
252b5132 2425 fprintf (stdout, " %d operands ", t->operands);
47926f60 2426 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2427 if (t->extension_opcode != None)
2428 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2429 if (t->opcode_modifier.d)
252b5132 2430 fprintf (stdout, "D");
40fb9820 2431 if (t->opcode_modifier.w)
252b5132
RH		 2432 fprintf (stdout, "W");
2433 fprintf (stdout, "\n");
09137c09 2434 for (j = 0; j < t->operands; j++)
252b5132 2435 {
09137c09
SP		 2436 fprintf (stdout, " #%d type ", j + 1);
2437 pt (t->operand_types[j]);
252b5132
RH		 2438 fprintf (stdout, "\n");
2439 }
2440}
2441
2442static void
e3bb37b5 2443pe (expressionS *e)
252b5132 2444{
24eab124 2445 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2446 fprintf (stdout, " add_number %ld (%lx)\n",
2447 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2448 if (e->X_add_symbol)
2449 {
2450 fprintf (stdout, " add_symbol ");
2451 ps (e->X_add_symbol);
2452 fprintf (stdout, "\n");
2453 }
2454 if (e->X_op_symbol)
2455 {
2456 fprintf (stdout, " op_symbol ");
2457 ps (e->X_op_symbol);
2458 fprintf (stdout, "\n");
2459 }
2460}
2461
2462static void
e3bb37b5 2463ps (symbolS *s)
252b5132
RH		 2464{
2465 fprintf (stdout, "%s type %s%s",
2466 S_GET_NAME (s),
2467 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2468 segment_name (S_GET_SEGMENT (s)));
2469}
2470
7b81dfbb 2471static struct type_name
252b5132 2472 {
40fb9820
L		 2473 i386_operand_type mask;
2474 const char *name;
252b5132 2475 }
7b81dfbb 2476const type_names[] =
252b5132 2477{
40fb9820
L		 2478 { OPERAND_TYPE_REG8, "r8" },
2479 { OPERAND_TYPE_REG16, "r16" },
2480 { OPERAND_TYPE_REG32, "r32" },
2481 { OPERAND_TYPE_REG64, "r64" },
2482 { OPERAND_TYPE_IMM8, "i8" },
2483 { OPERAND_TYPE_IMM8, "i8s" },
2484 { OPERAND_TYPE_IMM16, "i16" },
2485 { OPERAND_TYPE_IMM32, "i32" },
2486 { OPERAND_TYPE_IMM32S, "i32s" },
2487 { OPERAND_TYPE_IMM64, "i64" },
2488 { OPERAND_TYPE_IMM1, "i1" },
2489 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2490 { OPERAND_TYPE_DISP8, "d8" },
2491 { OPERAND_TYPE_DISP16, "d16" },
2492 { OPERAND_TYPE_DISP32, "d32" },
2493 { OPERAND_TYPE_DISP32S, "d32s" },
2494 { OPERAND_TYPE_DISP64, "d64" },
2495 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2496 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2497 { OPERAND_TYPE_CONTROL, "control reg" },
2498 { OPERAND_TYPE_TEST, "test reg" },
2499 { OPERAND_TYPE_DEBUG, "debug reg" },
2500 { OPERAND_TYPE_FLOATREG, "FReg" },
2501 { OPERAND_TYPE_FLOATACC, "FAcc" },
2502 { OPERAND_TYPE_SREG2, "SReg2" },
2503 { OPERAND_TYPE_SREG3, "SReg3" },
2504 { OPERAND_TYPE_ACC, "Acc" },
2505 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2506 { OPERAND_TYPE_REGMMX, "rMMX" },
2507 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2508 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2509 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2510};
2511
2512static void
40fb9820 2513pt (i386_operand_type t)
252b5132 2514{
40fb9820 2515 unsigned int j;
c6fb90c8 2516 i386_operand_type a;
252b5132 2517
40fb9820 2518 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2519 {
2520 a = operand_type_and (t, type_names[j].mask);
0349dc08 2521 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2522 fprintf (stdout, "%s, ", type_names[j].name);
2523 }
252b5132
RH		 2524 fflush (stdout);
2525}
2526
2527#endif /* DEBUG386 */
2528\f
252b5132 2529static bfd_reloc_code_real_type
3956db08 2530reloc (unsigned int size,
64e74474
AM		 2531 int pcrel,
2532 int sign,
2533 bfd_reloc_code_real_type other)
252b5132 2534{
47926f60 2535 if (other != NO_RELOC)
3956db08 2536 {
91d6fa6a 2537 reloc_howto_type *rel;
3956db08
JB		 2538
2539 if (size == 8)
2540 switch (other)
2541 {
64e74474
AM		 2542 case BFD_RELOC_X86_64_GOT32:
2543 return BFD_RELOC_X86_64_GOT64;
2544 break;
2545 case BFD_RELOC_X86_64_PLTOFF64:
2546 return BFD_RELOC_X86_64_PLTOFF64;
2547 break;
2548 case BFD_RELOC_X86_64_GOTPC32:
2549 other = BFD_RELOC_X86_64_GOTPC64;
2550 break;
2551 case BFD_RELOC_X86_64_GOTPCREL:
2552 other = BFD_RELOC_X86_64_GOTPCREL64;
2553 break;
2554 case BFD_RELOC_X86_64_TPOFF32:
2555 other = BFD_RELOC_X86_64_TPOFF64;
2556 break;
2557 case BFD_RELOC_X86_64_DTPOFF32:
2558 other = BFD_RELOC_X86_64_DTPOFF64;
2559 break;
2560 default:
2561 break;
3956db08 2562 }
e05278af
JB		 2563
2564 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2565 if (size == 4 && flag_code != CODE_64BIT)
2566 sign = -1;
2567
91d6fa6a
NC		 2568 rel = bfd_reloc_type_lookup (stdoutput, other);
2569 if (!rel)
3956db08 2570 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2571 else if (size != bfd_get_reloc_size (rel))
3956db08 2572 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2573 bfd_get_reloc_size (rel),
3956db08 2574 size);
91d6fa6a 2575 else if (pcrel && !rel->pc_relative)
3956db08 2576 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2577 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2578 && !sign)
91d6fa6a 2579 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2580 && sign > 0))
3956db08
JB		 2581 as_bad (_("relocated field and relocation type differ in signedness"));
2582 else
2583 return other;
2584 return NO_RELOC;
2585 }
252b5132
RH		 2586
2587 if (pcrel)
2588 {
3e73aa7c 2589 if (!sign)
3956db08 2590 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2591 switch (size)
2592 {
2593 case 1: return BFD_RELOC_8_PCREL;
2594 case 2: return BFD_RELOC_16_PCREL;
2595 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2596 case 8: return BFD_RELOC_64_PCREL;
252b5132 2597 }
3956db08 2598 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2599 }
2600 else
2601 {
3956db08 2602 if (sign > 0)
e5cb08ac 2603 switch (size)
3e73aa7c
JH		 2604 {
2605 case 4: return BFD_RELOC_X86_64_32S;
2606 }
2607 else
2608 switch (size)
2609 {
2610 case 1: return BFD_RELOC_8;
2611 case 2: return BFD_RELOC_16;
2612 case 4: return BFD_RELOC_32;
2613 case 8: return BFD_RELOC_64;
2614 }
3956db08
JB		 2615 as_bad (_("cannot do %s %u byte relocation"),
2616 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2617 }
2618
0cc9e1d3 2619 return NO_RELOC;
252b5132
RH		 2620}
2621
47926f60
KH		 2622/* Here we decide which fixups can be adjusted to make them relative to
2623 the beginning of the section instead of the symbol. Basically we need
2624 to make sure that the dynamic relocations are done correctly, so in
2625 some cases we force the original symbol to be used. */
2626
252b5132 2627int
e3bb37b5 2628tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2629{
6d249963 2630#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2631 if (!IS_ELF)
31312f95
AM		 2632 return 1;
2633
a161fe53
AM		 2634 /* Don't adjust pc-relative references to merge sections in 64-bit
2635 mode. */
2636 if (use_rela_relocations
2637 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2638 && fixP->fx_pcrel)
252b5132 2639 return 0;
31312f95 2640
8d01d9a9
AJ		 2641 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2642 and changed later by validate_fix. */
2643 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2644 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2645 return 0;
2646
ce8a8b2f 2647 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2648 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2649 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2650 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2651 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2652 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2653 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2654 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2655 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2656 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2657 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2658 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2659 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2660 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2661 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2662 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2663 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2664 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2665 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2666 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2667 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2668 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2669 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2670 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2671 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2672 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2673 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2674 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2675 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2676 return 0;
31312f95 2677#endif
252b5132
RH		 2678 return 1;
2679}
252b5132 2680
b4cac588 2681static int
e3bb37b5 2682intel_float_operand (const char *mnemonic)
252b5132 2683{
9306ca4a
JB		 2684 /* Note that the value returned is meaningful only for opcodes with (memory)
2685 operands, hence the code here is free to improperly handle opcodes that
2686 have no operands (for better performance and smaller code). */
2687
2688 if (mnemonic[0] != 'f')
2689 return 0; /* non-math */
2690
2691 switch (mnemonic[1])
2692 {
2693 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2694 the fs segment override prefix not currently handled because no
2695 call path can make opcodes without operands get here */
2696 case 'i':
2697 return 2 /* integer op */;
2698 case 'l':
2699 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2700 return 3; /* fldcw/fldenv */
2701 break;
2702 case 'n':
2703 if (mnemonic[2] != 'o' /* fnop */)
2704 return 3; /* non-waiting control op */
2705 break;
2706 case 'r':
2707 if (mnemonic[2] == 's')
2708 return 3; /* frstor/frstpm */
2709 break;
2710 case 's':
2711 if (mnemonic[2] == 'a')
2712 return 3; /* fsave */
2713 if (mnemonic[2] == 't')
2714 {
2715 switch (mnemonic[3])
2716 {
2717 case 'c': /* fstcw */
2718 case 'd': /* fstdw */
2719 case 'e': /* fstenv */
2720 case 's': /* fsts[gw] */
2721 return 3;
2722 }
2723 }
2724 break;
2725 case 'x':
2726 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2727 return 0; /* fxsave/fxrstor are not really math ops */
2728 break;
2729 }
252b5132 2730
9306ca4a 2731 return 1;
252b5132
RH		 2732}
2733
c0f3af97
L		 2734/* Build the VEX prefix. */
2735
2736static void
d3ce72d0 2737build_vex_prefix (const insn_template *t)
c0f3af97
L		 2738{
2739 unsigned int register_specifier;
2740 unsigned int implied_prefix;
2741 unsigned int vector_length;
2742
2743 /* Check register specifier. */
2744 if (i.vex.register_specifier)
2745 {
2746 register_specifier = i.vex.register_specifier->reg_num;
2747 if ((i.vex.register_specifier->reg_flags & RegRex))
2748 register_specifier += 8;
2749 register_specifier = ~register_specifier & 0xf;
2750 }
2751 else
2752 register_specifier = 0xf;
2753
fa99fab2
L		 2754 /* Use 2-byte VEX prefix by swappping destination and source
2755 operand. */
2756 if (!i.swap_operand
2757 && i.operands == i.reg_operands
7f399153 2758 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2759 && i.tm.opcode_modifier.s
2760 && i.rex == REX_B)
2761 {
2762 unsigned int xchg = i.operands - 1;
2763 union i386_op temp_op;
2764 i386_operand_type temp_type;
2765
2766 temp_type = i.types[xchg];
2767 i.types[xchg] = i.types[0];
2768 i.types[0] = temp_type;
2769 temp_op = i.op[xchg];
2770 i.op[xchg] = i.op[0];
2771 i.op[0] = temp_op;
2772
9c2799c2 2773 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2774
2775 i.rex = REX_R;
2776 xchg = i.rm.regmem;
2777 i.rm.regmem = i.rm.reg;
2778 i.rm.reg = xchg;
2779
2780 /* Use the next insn. */
2781 i.tm = t[1];
2782 }
2783
539f890d
L		 2784 if (i.tm.opcode_modifier.vex == VEXScalar)
2785 vector_length = avxscalar;
2786 else
2787 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2788
2789 switch ((i.tm.base_opcode >> 8) & 0xff)
2790 {
2791 case 0:
2792 implied_prefix = 0;
2793 break;
2794 case DATA_PREFIX_OPCODE:
2795 implied_prefix = 1;
2796 break;
2797 case REPE_PREFIX_OPCODE:
2798 implied_prefix = 2;
2799 break;
2800 case REPNE_PREFIX_OPCODE:
2801 implied_prefix = 3;
2802 break;
2803 default:
2804 abort ();
2805 }
2806
2807 /* Use 2-byte VEX prefix if possible. */
7f399153 2808 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2809 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2810 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2811 {
2812 /* 2-byte VEX prefix. */
2813 unsigned int r;
2814
2815 i.vex.length = 2;
2816 i.vex.bytes[0] = 0xc5;
2817
2818 /* Check the REX.R bit. */
2819 r = (i.rex & REX_R) ? 0 : 1;
2820 i.vex.bytes[1] = (r << 7
2821 | register_specifier << 3
2822 | vector_length << 2
2823 | implied_prefix);
2824 }
2825 else
2826 {
2827 /* 3-byte VEX prefix. */
2828 unsigned int m, w;
2829
f88c9eb0 2830 i.vex.length = 3;
f88c9eb0 2831
7f399153 2832 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2833 {
7f399153
L		 2834 case VEX0F:
2835 m = 0x1;
80de6e00 2836 i.vex.bytes[0] = 0xc4;
7f399153
L		 2837 break;
2838 case VEX0F38:
2839 m = 0x2;
80de6e00 2840 i.vex.bytes[0] = 0xc4;
7f399153
L		 2841 break;
2842 case VEX0F3A:
2843 m = 0x3;
80de6e00 2844 i.vex.bytes[0] = 0xc4;
7f399153
L		 2845 break;
2846 case XOP08:
5dd85c99
SP		 2847 m = 0x8;
2848 i.vex.bytes[0] = 0x8f;
7f399153
L		 2849 break;
2850 case XOP09:
f88c9eb0
SP		 2851 m = 0x9;
2852 i.vex.bytes[0] = 0x8f;
7f399153
L		 2853 break;
2854 case XOP0A:
f88c9eb0
SP		 2855 m = 0xa;
2856 i.vex.bytes[0] = 0x8f;
7f399153
L		 2857 break;
2858 default:
2859 abort ();
f88c9eb0 2860 }
c0f3af97 2861
c0f3af97
L		 2862 /* The high 3 bits of the second VEX byte are 1's compliment
2863 of RXB bits from REX. */
2864 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2865
2866 /* Check the REX.W bit. */
2867 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2868 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2869 {
2870 if (w)
2871 abort ();
2872
1ef99a7b 2873 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2874 w = 1;
2875 }
2876
2877 i.vex.bytes[2] = (w << 7
2878 | register_specifier << 3
2879 | vector_length << 2
2880 | implied_prefix);
2881 }
2882}
2883
65da13b5
L		 2884static void
2885process_immext (void)
2886{
2887 expressionS *exp;
2888
2889 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2890 {
1fed0ba1
L		 2891 /* SSE3 Instructions have the fixed operands with an opcode
2892 suffix which is coded in the same place as an 8-bit immediate
2893 field would be. Here we check those operands and remove them
2894 afterwards. */
65da13b5
L		 2895 unsigned int x;
2896
2897 for (x = 0; x < i.operands; x++)
2898 if (i.op[x].regs->reg_num != x)
2899 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2900 register_prefix, i.op[x].regs->reg_name, x + 1,
2901 i.tm.name);
2902
2903 i.operands = 0;
65da13b5
L		 2904 }
2905
c0f3af97 2906 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2907 which is coded in the same place as an 8-bit immediate field
2908 would be. Here we fake an 8-bit immediate operand from the
2909 opcode suffix stored in tm.extension_opcode.
2910
c1e679ec 2911 AVX instructions also use this encoding, for some of
c0f3af97 2912 3 argument instructions. */
65da13b5 2913
9c2799c2 2914 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2915 && (i.operands <= 2
2916 || (i.tm.opcode_modifier.vex
2917 && i.operands <= 4)));
65da13b5
L		 2918
2919 exp = &im_expressions[i.imm_operands++];
2920 i.op[i.operands].imms = exp;
2921 i.types[i.operands] = imm8;
2922 i.operands++;
2923 exp->X_op = O_constant;
2924 exp->X_add_number = i.tm.extension_opcode;
2925 i.tm.extension_opcode = None;
2926}
2927
252b5132
RH		 2928/* This is the guts of the machine-dependent assembler. LINE points to a
2929 machine dependent instruction. This function is supposed to emit
2930 the frags/bytes it assembles to. */
2931
2932void
65da13b5 2933md_assemble (char *line)
252b5132 2934{
40fb9820 2935 unsigned int j;
252b5132 2936 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2937 const insn_template *t;
252b5132 2938
47926f60 2939 /* Initialize globals. */
252b5132
RH		 2940 memset (&i, '\0', sizeof (i));
2941 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2942 i.reloc[j] = NO_RELOC;
252b5132
RH		 2943 memset (disp_expressions, '\0', sizeof (disp_expressions));
2944 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2945 save_stack_p = save_stack;
252b5132
RH		 2946
2947 /* First parse an instruction mnemonic & call i386_operand for the operands.
2948 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2949 start of a (possibly prefixed) mnemonic. */
252b5132 2950
29b0f896
AM		 2951 line = parse_insn (line, mnemonic);
2952 if (line == NULL)
2953 return;
252b5132 2954
29b0f896 2955 line = parse_operands (line, mnemonic);
ee86248c 2956 this_operand = -1;
29b0f896
AM		 2957 if (line == NULL)
2958 return;
252b5132 2959
29b0f896
AM		 2960 /* Now we've parsed the mnemonic into a set of templates, and have the
2961 operands at hand. */
2962
2963 /* All intel opcodes have reversed operands except for "bound" and
2964 "enter". We also don't reverse intersegment "jmp" and "call"
2965 instructions with 2 immediate operands so that the immediate segment
050dfa73 2966 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2967 if (intel_syntax
2968 && i.operands > 1
29b0f896 2969 && (strcmp (mnemonic, "bound") != 0)
30123838 2970 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2971 && !(operand_type_check (i.types[0], imm)
2972 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2973 swap_operands ();
2974
ec56d5c0
JB		 2975 /* The order of the immediates should be reversed
2976 for 2 immediates extrq and insertq instructions */
2977 if (i.imm_operands == 2
2978 && (strcmp (mnemonic, "extrq") == 0
2979 || strcmp (mnemonic, "insertq") == 0))
2980 swap_2_operands (0, 1);
2981
29b0f896
AM		 2982 if (i.imm_operands)
2983 optimize_imm ();
2984
b300c311
L		 2985 /* Don't optimize displacement for movabs since it only takes 64bit
2986 displacement. */
2987 if (i.disp_operands
f8a5c266 2988 && !i.disp32_encoding
b300c311
L		 2989 && (flag_code != CODE_64BIT
2990 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2991 optimize_disp ();
2992
2993 /* Next, we find a template that matches the given insn,
2994 making sure the overlap of the given operands types is consistent
2995 with the template operand types. */
252b5132 2996
fa99fab2 2997 if (!(t = match_template ()))
29b0f896 2998 return;
252b5132 2999
daf50ae7 3000 if (sse_check != sse_check_none
81f8a913 3001 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3002 && (i.tm.cpu_flags.bitfield.cpusse
3003 || i.tm.cpu_flags.bitfield.cpusse2
3004 || i.tm.cpu_flags.bitfield.cpusse3
3005 || i.tm.cpu_flags.bitfield.cpussse3
3006 || i.tm.cpu_flags.bitfield.cpusse4_1
3007 || i.tm.cpu_flags.bitfield.cpusse4_2))
3008 {
3009 (sse_check == sse_check_warning
3010 ? as_warn
3011 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3012 }
3013
321fd21e
L		 3014 /* Zap movzx and movsx suffix. The suffix has been set from
3015 "word ptr" or "byte ptr" on the source operand in Intel syntax
3016 or extracted from mnemonic in AT&T syntax. But we'll use
3017 the destination register to choose the suffix for encoding. */
3018 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3019 {
321fd21e
L		 3020 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3021 there is no suffix, the default will be byte extension. */
3022 if (i.reg_operands != 2
3023 && !i.suffix
7ab9ffdd 3024 && intel_syntax)
321fd21e
L		 3025 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3026
3027 i.suffix = 0;
cd61ebfe 3028 }
24eab124 3029
40fb9820 3030 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3031 if (!add_prefix (FWAIT_OPCODE))
3032 return;
252b5132 3033
c1ba0266
L		 3034 /* Check for lock without a lockable instruction. Destination operand
3035 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3036 if (i.prefix[LOCK_PREFIX]
3037 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3038 || i.mem_operands == 0
3039 || (i.tm.base_opcode != 0x86
3040 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3041 {
3042 as_bad (_("expecting lockable instruction after `lock'"));
3043 return;
3044 }
3045
29b0f896 3046 /* Check string instruction segment overrides. */
40fb9820 3047 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3048 {
3049 if (!check_string ())
5dd0794d 3050 return;
fc0763e6 3051 i.disp_operands = 0;
29b0f896 3052 }
5dd0794d 3053
29b0f896
AM		 3054 if (!process_suffix ())
3055 return;
e413e4e9 3056
bc0844ae
L		 3057 /* Update operand types. */
3058 for (j = 0; j < i.operands; j++)
3059 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3060
29b0f896
AM		 3061 /* Make still unresolved immediate matches conform to size of immediate
3062 given in i.suffix. */
3063 if (!finalize_imm ())
3064 return;
252b5132 3065
40fb9820 3066 if (i.types[0].bitfield.imm1)
29b0f896 3067 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3068
9afe6eb8
L		 3069 /* We only need to check those implicit registers for instructions
3070 with 3 operands or less. */
3071 if (i.operands <= 3)
3072 for (j = 0; j < i.operands; j++)
3073 if (i.types[j].bitfield.inoutportreg
3074 || i.types[j].bitfield.shiftcount
3075 || i.types[j].bitfield.acc
3076 || i.types[j].bitfield.floatacc)
3077 i.reg_operands--;
40fb9820 3078
c0f3af97
L		 3079 /* ImmExt should be processed after SSE2AVX. */
3080 if (!i.tm.opcode_modifier.sse2avx
3081 && i.tm.opcode_modifier.immext)
65da13b5 3082 process_immext ();
252b5132 3083
29b0f896
AM		 3084 /* For insns with operands there are more diddles to do to the opcode. */
3085 if (i.operands)
3086 {
3087 if (!process_operands ())
3088 return;
3089 }
40fb9820 3090 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3091 {
3092 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3093 as_warn (_("translating to `%sp'"), i.tm.name);
3094 }
252b5132 3095
c0f3af97 3096 if (i.tm.opcode_modifier.vex)
fa99fab2 3097 build_vex_prefix (t);
c0f3af97 3098
5dd85c99
SP		 3099 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3100 instructions may define INT_OPCODE as well, so avoid this corner
3101 case for those instructions that use MODRM. */
3102 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3103 && !i.tm.opcode_modifier.modrm
3104 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3105 {
3106 i.tm.base_opcode = INT3_OPCODE;
3107 i.imm_operands = 0;
3108 }
252b5132 3109
40fb9820
L		 3110 if ((i.tm.opcode_modifier.jump
3111 || i.tm.opcode_modifier.jumpbyte
3112 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3113 && i.op[0].disps->X_op == O_constant)
3114 {
3115 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3116 the absolute address given by the constant. Since ix86 jumps and
3117 calls are pc relative, we need to generate a reloc. */
3118 i.op[0].disps->X_add_symbol = &abs_symbol;
3119 i.op[0].disps->X_op = O_symbol;
3120 }
252b5132 3121
40fb9820 3122 if (i.tm.opcode_modifier.rex64)
161a04f6 3123 i.rex |= REX_W;
252b5132 3124
29b0f896
AM		 3125 /* For 8 bit registers we need an empty rex prefix. Also if the
3126 instruction already has a prefix, we need to convert old
3127 registers to new ones. */
773f551c 3128
40fb9820 3129 if ((i.types[0].bitfield.reg8
29b0f896 3130 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3131 || (i.types[1].bitfield.reg8
29b0f896 3132 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3133 || ((i.types[0].bitfield.reg8
3134 || i.types[1].bitfield.reg8)
29b0f896
AM		 3135 && i.rex != 0))
3136 {
3137 int x;
726c5dcd 3138
29b0f896
AM		 3139 i.rex |= REX_OPCODE;
3140 for (x = 0; x < 2; x++)
3141 {
3142 /* Look for 8 bit operand that uses old registers. */
40fb9820 3143 if (i.types[x].bitfield.reg8
29b0f896 3144 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3145 {
29b0f896
AM		 3146 /* In case it is "hi" register, give up. */
3147 if (i.op[x].regs->reg_num > 3)
a540244d 3148 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3149 "instruction requiring REX prefix."),
a540244d 3150 register_prefix, i.op[x].regs->reg_name);
773f551c 3151
29b0f896
AM		 3152 /* Otherwise it is equivalent to the extended register.
3153 Since the encoding doesn't change this is merely
3154 cosmetic cleanup for debug output. */
3155
3156 i.op[x].regs = i.op[x].regs + 8;
773f551c 3157 }
29b0f896
AM		 3158 }
3159 }
773f551c 3160
7ab9ffdd 3161 if (i.rex != 0)
29b0f896
AM		 3162 add_prefix (REX_OPCODE | i.rex);
3163
3164 /* We are ready to output the insn. */
3165 output_insn ();
3166}
3167
3168static char *
e3bb37b5 3169parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3170{
3171 char *l = line;
3172 char *token_start = l;
3173 char *mnem_p;
5c6af06e 3174 int supported;
d3ce72d0 3175 const insn_template *t;
b6169b20 3176 char *dot_p = NULL;
29b0f896
AM		 3177
3178 /* Non-zero if we found a prefix only acceptable with string insns. */
3179 const char *expecting_string_instruction = NULL;
45288df1 3180
29b0f896
AM		 3181 while (1)
3182 {
3183 mnem_p = mnemonic;
3184 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3185 {
b6169b20
L		 3186 if (*mnem_p == '.')
3187 dot_p = mnem_p;
29b0f896
AM		 3188 mnem_p++;
3189 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3190 {
29b0f896
AM		 3191 as_bad (_("no such instruction: `%s'"), token_start);
3192 return NULL;
3193 }
3194 l++;
3195 }
3196 if (!is_space_char (*l)
3197 && *l != END_OF_INSN
e44823cf
JB		 3198 && (intel_syntax
3199 || (*l != PREFIX_SEPARATOR
3200 && *l != ',')))
29b0f896
AM		 3201 {
3202 as_bad (_("invalid character %s in mnemonic"),
3203 output_invalid (*l));
3204 return NULL;
3205 }
3206 if (token_start == l)
3207 {
e44823cf 3208 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3209 as_bad (_("expecting prefix; got nothing"));
3210 else
3211 as_bad (_("expecting mnemonic; got nothing"));
3212 return NULL;
3213 }
45288df1 3214
29b0f896 3215 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3216 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3217
29b0f896
AM		 3218 if (*l != END_OF_INSN
3219 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3220 && current_templates
40fb9820 3221 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3222 {
c6fb90c8 3223 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3224 {
3225 as_bad ((flag_code != CODE_64BIT
3226 ? _("`%s' is only supported in 64-bit mode")
3227 : _("`%s' is not supported in 64-bit mode")),
3228 current_templates->start->name);
3229 return NULL;
3230 }
29b0f896
AM		 3231 /* If we are in 16-bit mode, do not allow addr16 or data16.
3232 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3233 if ((current_templates->start->opcode_modifier.size16
3234 || current_templates->start->opcode_modifier.size32)
29b0f896 3235 && flag_code != CODE_64BIT
40fb9820 3236 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3237 ^ (flag_code == CODE_16BIT)))
3238 {
3239 as_bad (_("redundant %s prefix"),
3240 current_templates->start->name);
3241 return NULL;
45288df1 3242 }
29b0f896
AM		 3243 /* Add prefix, checking for repeated prefixes. */
3244 switch (add_prefix (current_templates->start->base_opcode))
3245 {
c32fa91d 3246 case PREFIX_EXIST:
29b0f896 3247 return NULL;
c32fa91d 3248 case PREFIX_REP:
29b0f896
AM		 3249 expecting_string_instruction = current_templates->start->name;
3250 break;
c32fa91d
L		 3251 default:
3252 break;
29b0f896
AM		 3253 }
3254 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3255 token_start = ++l;
3256 }
3257 else
3258 break;
3259 }
45288df1 3260
30a55f88 3261 if (!current_templates)
b6169b20 3262 {
f8a5c266
L		 3263 /* Check if we should swap operand or force 32bit displacement in
3264 encoding. */
30a55f88
L		 3265 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3266 i.swap_operand = 1;
f8a5c266
L		 3267 else if (mnem_p - 4 == dot_p
3268 && dot_p[1] == 'd'
3269 && dot_p[2] == '3'
3270 && dot_p[3] == '2')
3271 i.disp32_encoding = 1;
30a55f88
L		 3272 else
3273 goto check_suffix;
3274 mnem_p = dot_p;
3275 *dot_p = '\0';
d3ce72d0 3276 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3277 }
3278
29b0f896
AM		 3279 if (!current_templates)
3280 {
b6169b20 3281check_suffix:
29b0f896
AM		 3282 /* See if we can get a match by trimming off a suffix. */
3283 switch (mnem_p[-1])
3284 {
3285 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3286 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3287 i.suffix = SHORT_MNEM_SUFFIX;
3288 else
29b0f896
AM		 3289 case BYTE_MNEM_SUFFIX:
3290 case QWORD_MNEM_SUFFIX:
3291 i.suffix = mnem_p[-1];
3292 mnem_p[-1] = '\0';
d3ce72d0
NC		 3293 current_templates = (const templates *) hash_find (op_hash,
3294 mnemonic);
29b0f896
AM		 3295 break;
3296 case SHORT_MNEM_SUFFIX:
3297 case LONG_MNEM_SUFFIX:
3298 if (!intel_syntax)
3299 {
3300 i.suffix = mnem_p[-1];
3301 mnem_p[-1] = '\0';
d3ce72d0
NC		 3302 current_templates = (const templates *) hash_find (op_hash,
3303 mnemonic);
29b0f896
AM		 3304 }
3305 break;
252b5132 3306
29b0f896
AM		 3307 /* Intel Syntax. */
3308 case 'd':
3309 if (intel_syntax)
3310 {
9306ca4a 3311 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3312 i.suffix = SHORT_MNEM_SUFFIX;
3313 else
3314 i.suffix = LONG_MNEM_SUFFIX;
3315 mnem_p[-1] = '\0';
d3ce72d0
NC		 3316 current_templates = (const templates *) hash_find (op_hash,
3317 mnemonic);
29b0f896
AM		 3318 }
3319 break;
3320 }
3321 if (!current_templates)
3322 {
3323 as_bad (_("no such instruction: `%s'"), token_start);
3324 return NULL;
3325 }
3326 }
252b5132 3327
40fb9820
L		 3328 if (current_templates->start->opcode_modifier.jump
3329 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3330 {
3331 /* Check for a branch hint. We allow ",pt" and ",pn" for
3332 predict taken and predict not taken respectively.
3333 I'm not sure that branch hints actually do anything on loop
3334 and jcxz insns (JumpByte) for current Pentium4 chips. They
3335 may work in the future and it doesn't hurt to accept them
3336 now. */
3337 if (l[0] == ',' && l[1] == 'p')
3338 {
3339 if (l[2] == 't')
3340 {
3341 if (!add_prefix (DS_PREFIX_OPCODE))
3342 return NULL;
3343 l += 3;
3344 }
3345 else if (l[2] == 'n')
3346 {
3347 if (!add_prefix (CS_PREFIX_OPCODE))
3348 return NULL;
3349 l += 3;
3350 }
3351 }
3352 }
3353 /* Any other comma loses. */
3354 if (*l == ',')
3355 {
3356 as_bad (_("invalid character %s in mnemonic"),
3357 output_invalid (*l));
3358 return NULL;
3359 }
252b5132 3360
29b0f896 3361 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3362 supported = 0;
3363 for (t = current_templates->start; t < current_templates->end; ++t)
3364 {
c0f3af97
L		 3365 supported |= cpu_flags_match (t);
3366 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3367 goto skip;
5c6af06e 3368 }
3629bb00 3369
c0f3af97 3370 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3371 {
3372 as_bad (flag_code == CODE_64BIT
3373 ? _("`%s' is not supported in 64-bit mode")
3374 : _("`%s' is only supported in 64-bit mode"),
3375 current_templates->start->name);
3376 return NULL;
3377 }
c0f3af97 3378 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3379 {
3629bb00 3380 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3381 current_templates->start->name,
41aacd83 3382 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3383 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3384 return NULL;
29b0f896 3385 }
3629bb00
L		 3386
3387skip:
3388 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3389 && (flag_code != CODE_16BIT))
29b0f896
AM		 3390 {
3391 as_warn (_("use .code16 to ensure correct addressing mode"));
3392 }
252b5132 3393
29b0f896 3394 /* Check for rep/repne without a string instruction. */
f41bbced 3395 if (expecting_string_instruction)
29b0f896 3396 {
f41bbced
JB		 3397 static templates override;
3398
3399 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3400 if (t->opcode_modifier.isstring)
f41bbced
JB		 3401 break;
3402 if (t >= current_templates->end)
3403 {
3404 as_bad (_("expecting string instruction after `%s'"),
64e74474 3405 expecting_string_instruction);
f41bbced
JB		 3406 return NULL;
3407 }
3408 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3409 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3410 break;
3411 override.end = t;
3412 current_templates = &override;
29b0f896 3413 }
252b5132 3414
29b0f896
AM		 3415 return l;
3416}
252b5132 3417
29b0f896 3418static char *
e3bb37b5 3419parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3420{
3421 char *token_start;
3138f287 3422
29b0f896
AM		 3423 /* 1 if operand is pending after ','. */
3424 unsigned int expecting_operand = 0;
252b5132 3425
29b0f896
AM		 3426 /* Non-zero if operand parens not balanced. */
3427 unsigned int paren_not_balanced;
3428
3429 while (*l != END_OF_INSN)
3430 {
3431 /* Skip optional white space before operand. */
3432 if (is_space_char (*l))
3433 ++l;
3434 if (!is_operand_char (*l) && *l != END_OF_INSN)
3435 {
3436 as_bad (_("invalid character %s before operand %d"),
3437 output_invalid (*l),
3438 i.operands + 1);
3439 return NULL;
3440 }
3441 token_start = l; /* after white space */
3442 paren_not_balanced = 0;
3443 while (paren_not_balanced || *l != ',')
3444 {
3445 if (*l == END_OF_INSN)
3446 {
3447 if (paren_not_balanced)
3448 {
3449 if (!intel_syntax)
3450 as_bad (_("unbalanced parenthesis in operand %d."),
3451 i.operands + 1);
3452 else
3453 as_bad (_("unbalanced brackets in operand %d."),
3454 i.operands + 1);
3455 return NULL;
3456 }
3457 else
3458 break; /* we are done */
3459 }
3460 else if (!is_operand_char (*l) && !is_space_char (*l))
3461 {
3462 as_bad (_("invalid character %s in operand %d"),
3463 output_invalid (*l),
3464 i.operands + 1);
3465 return NULL;
3466 }
3467 if (!intel_syntax)
3468 {
3469 if (*l == '(')
3470 ++paren_not_balanced;
3471 if (*l == ')')
3472 --paren_not_balanced;
3473 }
3474 else
3475 {
3476 if (*l == '[')
3477 ++paren_not_balanced;
3478 if (*l == ']')
3479 --paren_not_balanced;
3480 }
3481 l++;
3482 }
3483 if (l != token_start)
3484 { /* Yes, we've read in another operand. */
3485 unsigned int operand_ok;
3486 this_operand = i.operands++;
7d5e4556 3487 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3488 if (i.operands > MAX_OPERANDS)
3489 {
3490 as_bad (_("spurious operands; (%d operands/instruction max)"),
3491 MAX_OPERANDS);
3492 return NULL;
3493 }
3494 /* Now parse operand adding info to 'i' as we go along. */
3495 END_STRING_AND_SAVE (l);
3496
3497 if (intel_syntax)
3498 operand_ok =
3499 i386_intel_operand (token_start,
3500 intel_float_operand (mnemonic));
3501 else
a7619375 3502 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3503
3504 RESTORE_END_STRING (l);
3505 if (!operand_ok)
3506 return NULL;
3507 }
3508 else
3509 {
3510 if (expecting_operand)
3511 {
3512 expecting_operand_after_comma:
3513 as_bad (_("expecting operand after ','; got nothing"));
3514 return NULL;
3515 }
3516 if (*l == ',')
3517 {
3518 as_bad (_("expecting operand before ','; got nothing"));
3519 return NULL;
3520 }
3521 }
7f3f1ea2 3522
29b0f896
AM		 3523 /* Now *l must be either ',' or END_OF_INSN. */
3524 if (*l == ',')
3525 {
3526 if (*++l == END_OF_INSN)
3527 {
3528 /* Just skip it, if it's \n complain. */
3529 goto expecting_operand_after_comma;
3530 }
3531 expecting_operand = 1;
3532 }
3533 }
3534 return l;
3535}
7f3f1ea2 3536
050dfa73 3537static void
4d456e3d 3538swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3539{
3540 union i386_op temp_op;
40fb9820 3541 i386_operand_type temp_type;
050dfa73 3542 enum bfd_reloc_code_real temp_reloc;
4eed87de 3543
050dfa73
MM		 3544 temp_type = i.types[xchg2];
3545 i.types[xchg2] = i.types[xchg1];
3546 i.types[xchg1] = temp_type;
3547 temp_op = i.op[xchg2];
3548 i.op[xchg2] = i.op[xchg1];
3549 i.op[xchg1] = temp_op;
3550 temp_reloc = i.reloc[xchg2];
3551 i.reloc[xchg2] = i.reloc[xchg1];
3552 i.reloc[xchg1] = temp_reloc;
3553}
3554
29b0f896 3555static void
e3bb37b5 3556swap_operands (void)
29b0f896 3557{
b7c61d9a 3558 switch (i.operands)
050dfa73 3559 {
c0f3af97 3560 case 5:
b7c61d9a 3561 case 4:
4d456e3d 3562 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3563 case 3:
3564 case 2:
4d456e3d 3565 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3566 break;
3567 default:
3568 abort ();
29b0f896 3569 }
29b0f896
AM		 3570
3571 if (i.mem_operands == 2)
3572 {
3573 const seg_entry *temp_seg;
3574 temp_seg = i.seg[0];
3575 i.seg[0] = i.seg[1];
3576 i.seg[1] = temp_seg;
3577 }
3578}
252b5132 3579
29b0f896
AM		 3580/* Try to ensure constant immediates are represented in the smallest
3581 opcode possible. */
3582static void
e3bb37b5 3583optimize_imm (void)
29b0f896
AM		 3584{
3585 char guess_suffix = 0;
3586 int op;
252b5132 3587
29b0f896
AM		 3588 if (i.suffix)
3589 guess_suffix = i.suffix;
3590 else if (i.reg_operands)
3591 {
3592 /* Figure out a suffix from the last register operand specified.
3593 We can't do this properly yet, ie. excluding InOutPortReg,
3594 but the following works for instructions with immediates.
3595 In any case, we can't set i.suffix yet. */
3596 for (op = i.operands; --op >= 0;)
40fb9820 3597 if (i.types[op].bitfield.reg8)
7ab9ffdd 3598 {
40fb9820
L		 3599 guess_suffix = BYTE_MNEM_SUFFIX;
3600 break;
3601 }
3602 else if (i.types[op].bitfield.reg16)
252b5132 3603 {
40fb9820
L		 3604 guess_suffix = WORD_MNEM_SUFFIX;
3605 break;
3606 }
3607 else if (i.types[op].bitfield.reg32)
3608 {
3609 guess_suffix = LONG_MNEM_SUFFIX;
3610 break;
3611 }
3612 else if (i.types[op].bitfield.reg64)
3613 {
3614 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3615 break;
252b5132 3616 }
29b0f896
AM		 3617 }
3618 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3619 guess_suffix = WORD_MNEM_SUFFIX;
3620
3621 for (op = i.operands; --op >= 0;)
40fb9820 3622 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3623 {
3624 switch (i.op[op].imms->X_op)
252b5132 3625 {
29b0f896
AM		 3626 case O_constant:
3627 /* If a suffix is given, this operand may be shortened. */
3628 switch (guess_suffix)
252b5132 3629 {
29b0f896 3630 case LONG_MNEM_SUFFIX:
40fb9820
L		 3631 i.types[op].bitfield.imm32 = 1;
3632 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3633 break;
3634 case WORD_MNEM_SUFFIX:
40fb9820
L		 3635 i.types[op].bitfield.imm16 = 1;
3636 i.types[op].bitfield.imm32 = 1;
3637 i.types[op].bitfield.imm32s = 1;
3638 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3639 break;
3640 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3641 i.types[op].bitfield.imm8 = 1;
3642 i.types[op].bitfield.imm8s = 1;
3643 i.types[op].bitfield.imm16 = 1;
3644 i.types[op].bitfield.imm32 = 1;
3645 i.types[op].bitfield.imm32s = 1;
3646 i.types[op].bitfield.imm64 = 1;
29b0f896 3647 break;
252b5132 3648 }
252b5132 3649
29b0f896
AM		 3650 /* If this operand is at most 16 bits, convert it
3651 to a signed 16 bit number before trying to see
3652 whether it will fit in an even smaller size.
3653 This allows a 16-bit operand such as $0xffe0 to
3654 be recognised as within Imm8S range. */
40fb9820 3655 if ((i.types[op].bitfield.imm16)
29b0f896 3656 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3657 {
29b0f896
AM		 3658 i.op[op].imms->X_add_number =
3659 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3660 }
40fb9820 3661 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3662 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3663 == 0))
3664 {
3665 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3666 ^ ((offsetT) 1 << 31))
3667 - ((offsetT) 1 << 31));
3668 }
40fb9820 3669 i.types[op]
c6fb90c8
L		 3670 = operand_type_or (i.types[op],
3671 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3672
29b0f896
AM		 3673 /* We must avoid matching of Imm32 templates when 64bit
3674 only immediate is available. */
3675 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3676 i.types[op].bitfield.imm32 = 0;
29b0f896 3677 break;
252b5132 3678
29b0f896
AM		 3679 case O_absent:
3680 case O_register:
3681 abort ();
3682
3683 /* Symbols and expressions. */
3684 default:
9cd96992
JB		 3685 /* Convert symbolic operand to proper sizes for matching, but don't
3686 prevent matching a set of insns that only supports sizes other
3687 than those matching the insn suffix. */
3688 {
40fb9820 3689 i386_operand_type mask, allowed;
d3ce72d0 3690 const insn_template *t;
9cd96992 3691
0dfbf9d7
L		 3692 operand_type_set (&mask, 0);
3693 operand_type_set (&allowed, 0);
40fb9820 3694
4eed87de
AM		 3695 for (t = current_templates->start;
3696 t < current_templates->end;
3697 ++t)
c6fb90c8
L		 3698 allowed = operand_type_or (allowed,
3699 t->operand_types[op]);
9cd96992
JB		 3700 switch (guess_suffix)
3701 {
3702 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3703 mask.bitfield.imm64 = 1;
3704 mask.bitfield.imm32s = 1;
9cd96992
JB		 3705 break;
3706 case LONG_MNEM_SUFFIX:
40fb9820 3707 mask.bitfield.imm32 = 1;
9cd96992
JB		 3708 break;
3709 case WORD_MNEM_SUFFIX:
40fb9820 3710 mask.bitfield.imm16 = 1;
9cd96992
JB		 3711 break;
3712 case BYTE_MNEM_SUFFIX:
40fb9820 3713 mask.bitfield.imm8 = 1;
9cd96992
JB		 3714 break;
3715 default:
9cd96992
JB		 3716 break;
3717 }
c6fb90c8 3718 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3719 if (!operand_type_all_zero (&allowed))
c6fb90c8 3720 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3721 }
29b0f896 3722 break;
252b5132 3723 }
29b0f896
AM		 3724 }
3725}
47926f60 3726
29b0f896
AM		 3727/* Try to use the smallest displacement type too. */
3728static void
e3bb37b5 3729optimize_disp (void)
29b0f896
AM		 3730{
3731 int op;
3e73aa7c 3732
29b0f896 3733 for (op = i.operands; --op >= 0;)
40fb9820 3734 if (operand_type_check (i.types[op], disp))
252b5132 3735 {
b300c311 3736 if (i.op[op].disps->X_op == O_constant)
252b5132 3737 {
91d6fa6a 3738 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3739
40fb9820 3740 if (i.types[op].bitfield.disp16
91d6fa6a 3741 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3742 {
3743 /* If this operand is at most 16 bits, convert
3744 to a signed 16 bit number and don't use 64bit
3745 displacement. */
91d6fa6a 3746 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3747 i.types[op].bitfield.disp64 = 0;
b300c311 3748 }
40fb9820 3749 if (i.types[op].bitfield.disp32
91d6fa6a 3750 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3751 {
3752 /* If this operand is at most 32 bits, convert
3753 to a signed 32 bit number and don't use 64bit
3754 displacement. */
91d6fa6a
NC		 3755 op_disp &= (((offsetT) 2 << 31) - 1);
3756 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3757 i.types[op].bitfield.disp64 = 0;
b300c311 3758 }
91d6fa6a 3759 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3760 {
40fb9820
L		 3761 i.types[op].bitfield.disp8 = 0;
3762 i.types[op].bitfield.disp16 = 0;
3763 i.types[op].bitfield.disp32 = 0;
3764 i.types[op].bitfield.disp32s = 0;
3765 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3766 i.op[op].disps = 0;
3767 i.disp_operands--;
3768 }
3769 else if (flag_code == CODE_64BIT)
3770 {
91d6fa6a 3771 if (fits_in_signed_long (op_disp))
28a9d8f5 3772 {
40fb9820
L		 3773 i.types[op].bitfield.disp64 = 0;
3774 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3775 }
0e1147d9 3776 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3777 && fits_in_unsigned_long (op_disp))
40fb9820 3778 i.types[op].bitfield.disp32 = 1;
b300c311 3779 }
40fb9820
L		 3780 if ((i.types[op].bitfield.disp32
3781 || i.types[op].bitfield.disp32s
3782 || i.types[op].bitfield.disp16)
91d6fa6a 3783 && fits_in_signed_byte (op_disp))
40fb9820 3784 i.types[op].bitfield.disp8 = 1;
252b5132 3785 }
67a4f2b7
AO		 3786 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3787 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3788 {
3789 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3790 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3791 i.types[op].bitfield.disp8 = 0;
3792 i.types[op].bitfield.disp16 = 0;
3793 i.types[op].bitfield.disp32 = 0;
3794 i.types[op].bitfield.disp32s = 0;
3795 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3796 }
3797 else
b300c311 3798 /* We only support 64bit displacement on constants. */
40fb9820 3799 i.types[op].bitfield.disp64 = 0;
252b5132 3800 }
29b0f896
AM		 3801}
3802
43f3e2ee 3803/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3804 operand types. */
3805
3806static int
3807VEX_check_operands (const insn_template *t)
3808{
3809 if (!t->opcode_modifier.vex)
3810 return 0;
3811
3812 /* Only check VEX_Imm4, which must be the first operand. */
3813 if (t->operand_types[0].bitfield.vec_imm4)
3814 {
3815 if (i.op[0].imms->X_op != O_constant
3816 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3817 {
a65babc9 3818 i.error = bad_imm4;
891edac4
L		 3819 return 1;
3820 }
a683cc34
SP		 3821
3822 /* Turn off Imm8 so that update_imm won't complain. */
3823 i.types[0] = vec_imm4;
3824 }
3825
3826 return 0;
3827}
3828
d3ce72d0 3829static const insn_template *
e3bb37b5 3830match_template (void)
29b0f896
AM		 3831{
3832 /* Points to template once we've found it. */
d3ce72d0 3833 const insn_template *t;
40fb9820 3834 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3835 i386_operand_type overlap4;
29b0f896 3836 unsigned int found_reverse_match;
40fb9820
L		 3837 i386_opcode_modifier suffix_check;
3838 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3839 int addr_prefix_disp;
a5c311ca 3840 unsigned int j;
3629bb00 3841 unsigned int found_cpu_match;
45664ddb 3842 unsigned int check_register;
29b0f896 3843
c0f3af97
L		 3844#if MAX_OPERANDS != 5
3845# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3846#endif
3847
29b0f896 3848 found_reverse_match = 0;
539e75ad 3849 addr_prefix_disp = -1;
40fb9820
L		 3850
3851 memset (&suffix_check, 0, sizeof (suffix_check));
3852 if (i.suffix == BYTE_MNEM_SUFFIX)
3853 suffix_check.no_bsuf = 1;
3854 else if (i.suffix == WORD_MNEM_SUFFIX)
3855 suffix_check.no_wsuf = 1;
3856 else if (i.suffix == SHORT_MNEM_SUFFIX)
3857 suffix_check.no_ssuf = 1;
3858 else if (i.suffix == LONG_MNEM_SUFFIX)
3859 suffix_check.no_lsuf = 1;
3860 else if (i.suffix == QWORD_MNEM_SUFFIX)
3861 suffix_check.no_qsuf = 1;
3862 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3863 suffix_check.no_ldsuf = 1;
29b0f896 3864
01559ecc
L		 3865 /* Must have right number of operands. */
3866 i.error = number_of_operands_mismatch;
3867
45aa61fe 3868 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3869 {
539e75ad
L		 3870 addr_prefix_disp = -1;
3871
29b0f896
AM		 3872 if (i.operands != t->operands)
3873 continue;
3874
50aecf8c 3875 /* Check processor support. */
a65babc9 3876 i.error = unsupported;
c0f3af97
L		 3877 found_cpu_match = (cpu_flags_match (t)
3878 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3879 if (!found_cpu_match)
3880 continue;
3881
e1d4d893 3882 /* Check old gcc support. */
a65babc9 3883 i.error = old_gcc_only;
e1d4d893
L		 3884 if (!old_gcc && t->opcode_modifier.oldgcc)
3885 continue;
3886
3887 /* Check AT&T mnemonic. */
a65babc9 3888 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3889 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3890 continue;
3891
891edac4 3892 /* Check AT&T/Intel syntax. */
a65babc9 3893 i.error = unsupported_syntax;
5c07affc
L		 3894 if ((intel_syntax && t->opcode_modifier.attsyntax)
3895 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3896 continue;
3897
20592a94 3898 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3899 i.error = invalid_instruction_suffix;
567e4e96
L		 3900 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3901 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3902 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3903 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3904 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3905 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3906 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3907 continue;
3908
5c07affc 3909 if (!operand_size_match (t))
7d5e4556 3910 continue;
539e75ad 3911
5c07affc
L		 3912 for (j = 0; j < MAX_OPERANDS; j++)
3913 operand_types[j] = t->operand_types[j];
3914
45aa61fe
AM		 3915 /* In general, don't allow 64-bit operands in 32-bit mode. */
3916 if (i.suffix == QWORD_MNEM_SUFFIX
3917 && flag_code != CODE_64BIT
3918 && (intel_syntax
40fb9820 3919 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3920 && !intel_float_operand (t->name))
3921 : intel_float_operand (t->name) != 2)
40fb9820 3922 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3923 && !operand_types[0].bitfield.regxmm
3924 && !operand_types[0].bitfield.regymm)
40fb9820 3925 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3926 && !!operand_types[t->operands > 1].bitfield.regxmm
3927 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3928 && (t->base_opcode != 0x0fc7
3929 || t->extension_opcode != 1 /* cmpxchg8b */))
3930 continue;
3931
192dc9c6
JB		 3932 /* In general, don't allow 32-bit operands on pre-386. */
3933 else if (i.suffix == LONG_MNEM_SUFFIX
3934 && !cpu_arch_flags.bitfield.cpui386
3935 && (intel_syntax
3936 ? (!t->opcode_modifier.ignoresize
3937 && !intel_float_operand (t->name))
3938 : intel_float_operand (t->name) != 2)
3939 && ((!operand_types[0].bitfield.regmmx
3940 && !operand_types[0].bitfield.regxmm)
3941 || (!operand_types[t->operands > 1].bitfield.regmmx
3942 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3943 continue;
3944
29b0f896 3945 /* Do not verify operands when there are none. */
50aecf8c 3946 else
29b0f896 3947 {
c6fb90c8 3948 if (!t->operands)
2dbab7d5
L		 3949 /* We've found a match; break out of loop. */
3950 break;
29b0f896 3951 }
252b5132 3952
539e75ad
L		 3953 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3954 into Disp32/Disp16/Disp32 operand. */
3955 if (i.prefix[ADDR_PREFIX] != 0)
3956 {
40fb9820 3957 /* There should be only one Disp operand. */
539e75ad
L		 3958 switch (flag_code)
3959 {
3960 case CODE_16BIT:
40fb9820
L		 3961 for (j = 0; j < MAX_OPERANDS; j++)
3962 {
3963 if (operand_types[j].bitfield.disp16)
3964 {
3965 addr_prefix_disp = j;
3966 operand_types[j].bitfield.disp32 = 1;
3967 operand_types[j].bitfield.disp16 = 0;
3968 break;
3969 }
3970 }
539e75ad
L		 3971 break;
3972 case CODE_32BIT:
40fb9820
L		 3973 for (j = 0; j < MAX_OPERANDS; j++)
3974 {
3975 if (operand_types[j].bitfield.disp32)
3976 {
3977 addr_prefix_disp = j;
3978 operand_types[j].bitfield.disp32 = 0;
3979 operand_types[j].bitfield.disp16 = 1;
3980 break;
3981 }
3982 }
539e75ad
L		 3983 break;
3984 case CODE_64BIT:
40fb9820
L		 3985 for (j = 0; j < MAX_OPERANDS; j++)
3986 {
3987 if (operand_types[j].bitfield.disp64)
3988 {
3989 addr_prefix_disp = j;
3990 operand_types[j].bitfield.disp64 = 0;
3991 operand_types[j].bitfield.disp32 = 1;
3992 break;
3993 }
3994 }
539e75ad
L		 3995 break;
3996 }
539e75ad
L		 3997 }
3998
56ffb741
L		 3999 /* We check register size if needed. */
4000 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4001 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4002 switch (t->operands)
4003 {
4004 case 1:
40fb9820 4005 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4006 continue;
4007 break;
4008 case 2:
8b38ad71
L		 4009 /* xchg %eax, %eax is a special case. It is an aliase for nop
4010 only in 32bit mode and we can use opcode 0x90. In 64bit
4011 mode, we can't use 0x90 for xchg %eax, %eax since it should
4012 zero-extend %eax to %rax. */
4013 if (flag_code == CODE_64BIT
4014 && t->base_opcode == 0x90
0dfbf9d7
L		 4015 && operand_type_equal (&i.types [0], &acc32)
4016 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4017 continue;
b6169b20
L		 4018 if (i.swap_operand)
4019 {
4020 /* If we swap operand in encoding, we either match
4021 the next one or reverse direction of operands. */
4022 if (t->opcode_modifier.s)
4023 continue;
4024 else if (t->opcode_modifier.d)
4025 goto check_reverse;
4026 }
4027
29b0f896 4028 case 3:
fa99fab2
L		 4029 /* If we swap operand in encoding, we match the next one. */
4030 if (i.swap_operand && t->opcode_modifier.s)
4031 continue;
f48ff2ae 4032 case 4:
c0f3af97 4033 case 5:
c6fb90c8 4034 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4035 if (!operand_type_match (overlap0, i.types[0])
4036 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4037 || (check_register
4038 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4039 operand_types[0],
4040 overlap1, i.types[1],
4041 operand_types[1])))
29b0f896
AM		 4042 {
4043 /* Check if other direction is valid ... */
40fb9820 4044 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4045 continue;
4046
b6169b20 4047check_reverse:
29b0f896 4048 /* Try reversing direction of operands. */
c6fb90c8
L		 4049 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4050 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4051 if (!operand_type_match (overlap0, i.types[0])
4052 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4053 || (check_register
4054 && !operand_type_register_match (overlap0,
4055 i.types[0],
4056 operand_types[1],
4057 overlap1,
4058 i.types[1],
4059 operand_types[0])))
29b0f896
AM		 4060 {
4061 /* Does not match either direction. */
4062 continue;
4063 }
4064 /* found_reverse_match holds which of D or FloatDR
4065 we've found. */
40fb9820 4066 if (t->opcode_modifier.d)
8a2ed489 4067 found_reverse_match = Opcode_D;
40fb9820 4068 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4069 found_reverse_match = Opcode_FloatD;
4070 else
4071 found_reverse_match = 0;
40fb9820 4072 if (t->opcode_modifier.floatr)
8a2ed489 4073 found_reverse_match |= Opcode_FloatR;
29b0f896 4074 }
f48ff2ae 4075 else
29b0f896 4076 {
f48ff2ae 4077 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4078 switch (t->operands)
4079 {
c0f3af97
L		 4080 case 5:
4081 overlap4 = operand_type_and (i.types[4],
4082 operand_types[4]);
d1cbb4db 4083 case 4:
c6fb90c8
L		 4084 overlap3 = operand_type_and (i.types[3],
4085 operand_types[3]);
d1cbb4db 4086 case 3:
c6fb90c8
L		 4087 overlap2 = operand_type_and (i.types[2],
4088 operand_types[2]);
d1cbb4db
L		 4089 break;
4090 }
29b0f896 4091
f48ff2ae
L		 4092 switch (t->operands)
4093 {
c0f3af97
L		 4094 case 5:
4095 if (!operand_type_match (overlap4, i.types[4])
4096 || !operand_type_register_match (overlap3,
4097 i.types[3],
4098 operand_types[3],
4099 overlap4,
4100 i.types[4],
4101 operand_types[4]))
4102 continue;
f48ff2ae 4103 case 4:
40fb9820 4104 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4105 || (check_register
4106 && !operand_type_register_match (overlap2,
4107 i.types[2],
4108 operand_types[2],
4109 overlap3,
4110 i.types[3],
4111 operand_types[3])))
f48ff2ae
L		 4112 continue;
4113 case 3:
4114 /* Here we make use of the fact that there are no
4115 reverse match 3 operand instructions, and all 3
4116 operand instructions only need to be checked for
4117 register consistency between operands 2 and 3. */
40fb9820 4118 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4119 || (check_register
4120 && !operand_type_register_match (overlap1,
4121 i.types[1],
4122 operand_types[1],
4123 overlap2,
4124 i.types[2],
4125 operand_types[2])))
f48ff2ae
L		 4126 continue;
4127 break;
4128 }
29b0f896 4129 }
f48ff2ae 4130 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4131 slip through to break. */
4132 }
3629bb00 4133 if (!found_cpu_match)
29b0f896
AM		 4134 {
4135 found_reverse_match = 0;
4136 continue;
4137 }
c0f3af97 4138
a683cc34
SP		 4139 /* Check if VEX operands are valid. */
4140 if (VEX_check_operands (t))
4141 continue;
4142
29b0f896
AM		 4143 /* We've found a match; break out of loop. */
4144 break;
4145 }
4146
4147 if (t == current_templates->end)
4148 {
4149 /* We found no match. */
a65babc9
L		 4150 const char *err_msg;
4151 switch (i.error)
4152 {
4153 default:
4154 abort ();
86e026a4 4155 case operand_size_mismatch:
a65babc9
L		 4156 err_msg = _("operand size mismatch");
4157 break;
4158 case operand_type_mismatch:
4159 err_msg = _("operand type mismatch");
4160 break;
4161 case register_type_mismatch:
4162 err_msg = _("register type mismatch");
4163 break;
4164 case number_of_operands_mismatch:
4165 err_msg = _("number of operands mismatch");
4166 break;
4167 case invalid_instruction_suffix:
4168 err_msg = _("invalid instruction suffix");
4169 break;
4170 case bad_imm4:
4171 err_msg = _("Imm4 isn't the first operand");
4172 break;
4173 case old_gcc_only:
4174 err_msg = _("only supported with old gcc");
4175 break;
4176 case unsupported_with_intel_mnemonic:
4177 err_msg = _("unsupported with Intel mnemonic");
4178 break;
4179 case unsupported_syntax:
4180 err_msg = _("unsupported syntax");
4181 break;
4182 case unsupported:
4183 err_msg = _("unsupported");
4184 break;
4185 }
4186 as_bad (_("%s for `%s'"), err_msg,
891edac4 4187 current_templates->start->name);
fa99fab2 4188 return NULL;
29b0f896 4189 }
252b5132 4190
29b0f896
AM		 4191 if (!quiet_warnings)
4192 {
4193 if (!intel_syntax
40fb9820
L		 4194 && (i.types[0].bitfield.jumpabsolute
4195 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4196 {
4197 as_warn (_("indirect %s without `*'"), t->name);
4198 }
4199
40fb9820
L		 4200 if (t->opcode_modifier.isprefix
4201 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4202 {
4203 /* Warn them that a data or address size prefix doesn't
4204 affect assembly of the next line of code. */
4205 as_warn (_("stand-alone `%s' prefix"), t->name);
4206 }
4207 }
4208
4209 /* Copy the template we found. */
4210 i.tm = *t;
539e75ad
L		 4211
4212 if (addr_prefix_disp != -1)
4213 i.tm.operand_types[addr_prefix_disp]
4214 = operand_types[addr_prefix_disp];
4215
29b0f896
AM		 4216 if (found_reverse_match)
4217 {
4218 /* If we found a reverse match we must alter the opcode
4219 direction bit. found_reverse_match holds bits to change
4220 (different for int & float insns). */
4221
4222 i.tm.base_opcode ^= found_reverse_match;
4223
539e75ad
L		 4224 i.tm.operand_types[0] = operand_types[1];
4225 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4226 }
4227
fa99fab2 4228 return t;
29b0f896
AM		 4229}
4230
4231static int
e3bb37b5 4232check_string (void)
29b0f896 4233{
40fb9820
L		 4234 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4235 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4236 {
4237 if (i.seg[0] != NULL && i.seg[0] != &es)
4238 {
a87af027 4239 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4240 i.tm.name,
a87af027
JB		 4241 mem_op + 1,
4242 register_prefix);
29b0f896
AM		 4243 return 0;
4244 }
4245 /* There's only ever one segment override allowed per instruction.
4246 This instruction possibly has a legal segment override on the
4247 second operand, so copy the segment to where non-string
4248 instructions store it, allowing common code. */
4249 i.seg[0] = i.seg[1];
4250 }
40fb9820 4251 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4252 {
4253 if (i.seg[1] != NULL && i.seg[1] != &es)
4254 {
a87af027 4255 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4256 i.tm.name,
a87af027
JB		 4257 mem_op + 2,
4258 register_prefix);
29b0f896
AM		 4259 return 0;
4260 }
4261 }
4262 return 1;
4263}
4264
4265static int
543613e9 4266process_suffix (void)
29b0f896
AM		 4267{
4268 /* If matched instruction specifies an explicit instruction mnemonic
4269 suffix, use it. */
40fb9820
L		 4270 if (i.tm.opcode_modifier.size16)
4271 i.suffix = WORD_MNEM_SUFFIX;
4272 else if (i.tm.opcode_modifier.size32)
4273 i.suffix = LONG_MNEM_SUFFIX;
4274 else if (i.tm.opcode_modifier.size64)
4275 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4276 else if (i.reg_operands)
4277 {
4278 /* If there's no instruction mnemonic suffix we try to invent one
4279 based on register operands. */
4280 if (!i.suffix)
4281 {
4282 /* We take i.suffix from the last register operand specified,
4283 Destination register type is more significant than source
381d071f
L		 4284 register type. crc32 in SSE4.2 prefers source register
4285 type. */
4286 if (i.tm.base_opcode == 0xf20f38f1)
4287 {
40fb9820
L		 4288 if (i.types[0].bitfield.reg16)
4289 i.suffix = WORD_MNEM_SUFFIX;
4290 else if (i.types[0].bitfield.reg32)
4291 i.suffix = LONG_MNEM_SUFFIX;
4292 else if (i.types[0].bitfield.reg64)
4293 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4294 }
9344ff29 4295 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4296 {
40fb9820 4297 if (i.types[0].bitfield.reg8)
20592a94
L		 4298 i.suffix = BYTE_MNEM_SUFFIX;
4299 }
381d071f
L		 4300
4301 if (!i.suffix)
4302 {
4303 int op;
4304
20592a94
L		 4305 if (i.tm.base_opcode == 0xf20f38f1
4306 || i.tm.base_opcode == 0xf20f38f0)
4307 {
4308 /* We have to know the operand size for crc32. */
4309 as_bad (_("ambiguous memory operand size for `%s`"),
4310 i.tm.name);
4311 return 0;
4312 }
4313
381d071f 4314 for (op = i.operands; --op >= 0;)
40fb9820 4315 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4316 {
40fb9820
L		 4317 if (i.types[op].bitfield.reg8)
4318 {
4319 i.suffix = BYTE_MNEM_SUFFIX;
4320 break;
4321 }
4322 else if (i.types[op].bitfield.reg16)
4323 {
4324 i.suffix = WORD_MNEM_SUFFIX;
4325 break;
4326 }
4327 else if (i.types[op].bitfield.reg32)
4328 {
4329 i.suffix = LONG_MNEM_SUFFIX;
4330 break;
4331 }
4332 else if (i.types[op].bitfield.reg64)
4333 {
4334 i.suffix = QWORD_MNEM_SUFFIX;
4335 break;
4336 }
381d071f
L		 4337 }
4338 }
29b0f896
AM		 4339 }
4340 else if (i.suffix == BYTE_MNEM_SUFFIX)
4341 {
2eb952a4
L		 4342 if (intel_syntax
4343 && i.tm.opcode_modifier.ignoresize
4344 && i.tm.opcode_modifier.no_bsuf)
4345 i.suffix = 0;
4346 else if (!check_byte_reg ())
29b0f896
AM		 4347 return 0;
4348 }
4349 else if (i.suffix == LONG_MNEM_SUFFIX)
4350 {
2eb952a4
L		 4351 if (intel_syntax
4352 && i.tm.opcode_modifier.ignoresize
4353 && i.tm.opcode_modifier.no_lsuf)
4354 i.suffix = 0;
4355 else if (!check_long_reg ())
29b0f896
AM		 4356 return 0;
4357 }
4358 else if (i.suffix == QWORD_MNEM_SUFFIX)
4359 {
955e1e6a
L		 4360 if (intel_syntax
4361 && i.tm.opcode_modifier.ignoresize
4362 && i.tm.opcode_modifier.no_qsuf)
4363 i.suffix = 0;
4364 else if (!check_qword_reg ())
29b0f896
AM		 4365 return 0;
4366 }
4367 else if (i.suffix == WORD_MNEM_SUFFIX)
4368 {
2eb952a4
L		 4369 if (intel_syntax
4370 && i.tm.opcode_modifier.ignoresize
4371 && i.tm.opcode_modifier.no_wsuf)
4372 i.suffix = 0;
4373 else if (!check_word_reg ())
29b0f896
AM		 4374 return 0;
4375 }
c0f3af97
L		 4376 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4377 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4378 {
c0f3af97 4379 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4380 should check if it is a valid suffix. */
4381 }
40fb9820 4382 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4383 /* Do nothing if the instruction is going to ignore the prefix. */
4384 ;
4385 else
4386 abort ();
4387 }
40fb9820 4388 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4389 && !i.suffix
4390 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4391 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4392 {
4393 i.suffix = stackop_size;
4394 }
9306ca4a
JB		 4395 else if (intel_syntax
4396 && !i.suffix
40fb9820
L		 4397 && (i.tm.operand_types[0].bitfield.jumpabsolute
4398 || i.tm.opcode_modifier.jumpbyte
4399 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4400 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4401 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4402 {
4403 switch (flag_code)
4404 {
4405 case CODE_64BIT:
40fb9820 4406 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4407 {
4408 i.suffix = QWORD_MNEM_SUFFIX;
4409 break;
4410 }
4411 case CODE_32BIT:
40fb9820 4412 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4413 i.suffix = LONG_MNEM_SUFFIX;
4414 break;
4415 case CODE_16BIT:
40fb9820 4416 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4417 i.suffix = WORD_MNEM_SUFFIX;
4418 break;
4419 }
4420 }
252b5132 4421
9306ca4a 4422 if (!i.suffix)
29b0f896 4423 {
9306ca4a
JB		 4424 if (!intel_syntax)
4425 {
40fb9820 4426 if (i.tm.opcode_modifier.w)
9306ca4a 4427 {
4eed87de
AM		 4428 as_bad (_("no instruction mnemonic suffix given and "
4429 "no register operands; can't size instruction"));
9306ca4a
JB		 4430 return 0;
4431 }
4432 }
4433 else
4434 {
40fb9820 4435 unsigned int suffixes;
7ab9ffdd 4436
40fb9820
L		 4437 suffixes = !i.tm.opcode_modifier.no_bsuf;
4438 if (!i.tm.opcode_modifier.no_wsuf)
4439 suffixes |= 1 << 1;
4440 if (!i.tm.opcode_modifier.no_lsuf)
4441 suffixes |= 1 << 2;
fc4adea1 4442 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4443 suffixes |= 1 << 3;
4444 if (!i.tm.opcode_modifier.no_ssuf)
4445 suffixes |= 1 << 4;
4446 if (!i.tm.opcode_modifier.no_qsuf)
4447 suffixes |= 1 << 5;
4448
4449 /* There are more than suffix matches. */
4450 if (i.tm.opcode_modifier.w
9306ca4a 4451 || ((suffixes & (suffixes - 1))
40fb9820
L		 4452 && !i.tm.opcode_modifier.defaultsize
4453 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4454 {
4455 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4456 return 0;
4457 }
4458 }
29b0f896 4459 }
252b5132 4460
9306ca4a
JB		 4461 /* Change the opcode based on the operand size given by i.suffix;
4462 We don't need to change things for byte insns. */
4463
582d5edd
L		 4464 if (i.suffix
4465 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4466 && i.suffix != XMMWORD_MNEM_SUFFIX
4467 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4468 {
4469 /* It's not a byte, select word/dword operation. */
40fb9820 4470 if (i.tm.opcode_modifier.w)
29b0f896 4471 {
40fb9820 4472 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4473 i.tm.base_opcode |= 8;
4474 else
4475 i.tm.base_opcode |= 1;
4476 }
0f3f3d8b 4477
29b0f896
AM		 4478 /* Now select between word & dword operations via the operand
4479 size prefix, except for instructions that will ignore this
4480 prefix anyway. */
ca61edf2 4481 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4482 {
ca61edf2
L		 4483 /* The address size override prefix changes the size of the
4484 first operand. */
40fb9820
L		 4485 if ((flag_code == CODE_32BIT
4486 && i.op->regs[0].reg_type.bitfield.reg16)
4487 || (flag_code != CODE_32BIT
4488 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4489 if (!add_prefix (ADDR_PREFIX_OPCODE))
4490 return 0;
4491 }
4492 else if (i.suffix != QWORD_MNEM_SUFFIX
4493 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4494 && !i.tm.opcode_modifier.ignoresize
4495 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4496 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4497 || (flag_code == CODE_64BIT
40fb9820 4498 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4499 {
4500 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4501
40fb9820 4502 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4503 prefix = ADDR_PREFIX_OPCODE;
252b5132 4504
29b0f896
AM		 4505 if (!add_prefix (prefix))
4506 return 0;
24eab124 4507 }
252b5132 4508
29b0f896
AM		 4509 /* Set mode64 for an operand. */
4510 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4511 && flag_code == CODE_64BIT
40fb9820 4512 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4513 {
4514 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4515 need rex64. cmpxchg8b is also a special case. */
4516 if (! (i.operands == 2
4517 && i.tm.base_opcode == 0x90
4518 && i.tm.extension_opcode == None
0dfbf9d7
L		 4519 && operand_type_equal (&i.types [0], &acc64)
4520 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4521 && ! (i.operands == 1
4522 && i.tm.base_opcode == 0xfc7
4523 && i.tm.extension_opcode == 1
40fb9820
L		 4524 && !operand_type_check (i.types [0], reg)
4525 && operand_type_check (i.types [0], anymem)))
f6bee062 4526 i.rex |= REX_W;
46e883c5 4527 }
3e73aa7c 4528
29b0f896
AM		 4529 /* Size floating point instruction. */
4530 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4531 if (i.tm.opcode_modifier.floatmf)
543613e9 4532 i.tm.base_opcode ^= 4;
29b0f896 4533 }
7ecd2f8b 4534
29b0f896
AM		 4535 return 1;
4536}
3e73aa7c 4537
29b0f896 4538static int
543613e9 4539check_byte_reg (void)
29b0f896
AM		 4540{
4541 int op;
543613e9 4542
29b0f896
AM		 4543 for (op = i.operands; --op >= 0;)
4544 {
4545 /* If this is an eight bit register, it's OK. If it's the 16 or
4546 32 bit version of an eight bit register, we will just use the
4547 low portion, and that's OK too. */
40fb9820 4548 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4549 continue;
4550
9344ff29
L		 4551 /* crc32 doesn't generate this warning. */
4552 if (i.tm.base_opcode == 0xf20f38f0)
4553 continue;
4554
40fb9820
L		 4555 if ((i.types[op].bitfield.reg16
4556 || i.types[op].bitfield.reg32
4557 || i.types[op].bitfield.reg64)
4558 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4559 {
4560 /* Prohibit these changes in the 64bit mode, since the
4561 lowering is more complicated. */
4562 if (flag_code == CODE_64BIT
40fb9820 4563 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4564 {
2ca3ace5
L		 4565 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4566 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4567 i.suffix);
4568 return 0;
4569 }
4570#if REGISTER_WARNINGS
4571 if (!quiet_warnings
40fb9820 4572 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4573 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4574 register_prefix,
40fb9820 4575 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4576 ? REGNAM_AL - REGNAM_AX
4577 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4578 register_prefix,
29b0f896
AM		 4579 i.op[op].regs->reg_name,
4580 i.suffix);
4581#endif
4582 continue;
4583 }
4584 /* Any other register is bad. */
40fb9820
L		 4585 if (i.types[op].bitfield.reg16
4586 || i.types[op].bitfield.reg32
4587 || i.types[op].bitfield.reg64
4588 || i.types[op].bitfield.regmmx
4589 || i.types[op].bitfield.regxmm
c0f3af97 4590 || i.types[op].bitfield.regymm
40fb9820
L		 4591 || i.types[op].bitfield.sreg2
4592 || i.types[op].bitfield.sreg3
4593 || i.types[op].bitfield.control
4594 || i.types[op].bitfield.debug
4595 || i.types[op].bitfield.test
4596 || i.types[op].bitfield.floatreg
4597 || i.types[op].bitfield.floatacc)
29b0f896 4598 {
a540244d
L		 4599 as_bad (_("`%s%s' not allowed with `%s%c'"),
4600 register_prefix,
29b0f896
AM		 4601 i.op[op].regs->reg_name,
4602 i.tm.name,
4603 i.suffix);
4604 return 0;
4605 }
4606 }
4607 return 1;
4608}
4609
4610static int
e3bb37b5 4611check_long_reg (void)
29b0f896
AM		 4612{
4613 int op;
4614
4615 for (op = i.operands; --op >= 0;)
4616 /* Reject eight bit registers, except where the template requires
4617 them. (eg. movzb) */
40fb9820
L		 4618 if (i.types[op].bitfield.reg8
4619 && (i.tm.operand_types[op].bitfield.reg16
4620 || i.tm.operand_types[op].bitfield.reg32
4621 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4622 {
a540244d
L		 4623 as_bad (_("`%s%s' not allowed with `%s%c'"),
4624 register_prefix,
29b0f896
AM		 4625 i.op[op].regs->reg_name,
4626 i.tm.name,
4627 i.suffix);
4628 return 0;
4629 }
4630 /* Warn if the e prefix on a general reg is missing. */
4631 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4632 && i.types[op].bitfield.reg16
4633 && (i.tm.operand_types[op].bitfield.reg32
4634 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4635 {
4636 /* Prohibit these changes in the 64bit mode, since the
4637 lowering is more complicated. */
4638 if (flag_code == CODE_64BIT)
252b5132 4639 {
2ca3ace5
L		 4640 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4641 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4642 i.suffix);
4643 return 0;
252b5132 4644 }
29b0f896
AM		 4645#if REGISTER_WARNINGS
4646 else
a540244d
L		 4647 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4648 register_prefix,
29b0f896 4649 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4650 register_prefix,
29b0f896
AM		 4651 i.op[op].regs->reg_name,
4652 i.suffix);
4653#endif
252b5132 4654 }
29b0f896 4655 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4656 else if (i.types[op].bitfield.reg64
4657 && (i.tm.operand_types[op].bitfield.reg32
4658 || i.tm.operand_types[op].bitfield.acc))
252b5132 4659 {
34828aad 4660 if (intel_syntax
ca61edf2 4661 && i.tm.opcode_modifier.toqword
40fb9820 4662 && !i.types[0].bitfield.regxmm)
34828aad 4663 {
ca61edf2 4664 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4665 i.suffix = QWORD_MNEM_SUFFIX;
4666 }
4667 else
4668 {
4669 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4670 register_prefix, i.op[op].regs->reg_name,
4671 i.suffix);
4672 return 0;
4673 }
29b0f896
AM		 4674 }
4675 return 1;
4676}
252b5132 4677
29b0f896 4678static int
e3bb37b5 4679check_qword_reg (void)
29b0f896
AM		 4680{
4681 int op;
252b5132 4682
29b0f896
AM		 4683 for (op = i.operands; --op >= 0; )
4684 /* Reject eight bit registers, except where the template requires
4685 them. (eg. movzb) */
40fb9820
L		 4686 if (i.types[op].bitfield.reg8
4687 && (i.tm.operand_types[op].bitfield.reg16
4688 || i.tm.operand_types[op].bitfield.reg32
4689 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4690 {
a540244d
L		 4691 as_bad (_("`%s%s' not allowed with `%s%c'"),
4692 register_prefix,
29b0f896
AM		 4693 i.op[op].regs->reg_name,
4694 i.tm.name,
4695 i.suffix);
4696 return 0;
4697 }
4698 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4699 else if ((i.types[op].bitfield.reg16
4700 || i.types[op].bitfield.reg32)
4701 && (i.tm.operand_types[op].bitfield.reg32
4702 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4703 {
4704 /* Prohibit these changes in the 64bit mode, since the
4705 lowering is more complicated. */
34828aad 4706 if (intel_syntax
ca61edf2 4707 && i.tm.opcode_modifier.todword
40fb9820 4708 && !i.types[0].bitfield.regxmm)
34828aad 4709 {
ca61edf2 4710 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4711 i.suffix = LONG_MNEM_SUFFIX;
4712 }
4713 else
4714 {
4715 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4716 register_prefix, i.op[op].regs->reg_name,
4717 i.suffix);
4718 return 0;
4719 }
252b5132 4720 }
29b0f896
AM		 4721 return 1;
4722}
252b5132 4723
29b0f896 4724static int
e3bb37b5 4725check_word_reg (void)
29b0f896
AM		 4726{
4727 int op;
4728 for (op = i.operands; --op >= 0;)
4729 /* Reject eight bit registers, except where the template requires
4730 them. (eg. movzb) */
40fb9820
L		 4731 if (i.types[op].bitfield.reg8
4732 && (i.tm.operand_types[op].bitfield.reg16
4733 || i.tm.operand_types[op].bitfield.reg32
4734 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4735 {
a540244d
L		 4736 as_bad (_("`%s%s' not allowed with `%s%c'"),
4737 register_prefix,
29b0f896
AM		 4738 i.op[op].regs->reg_name,
4739 i.tm.name,
4740 i.suffix);
4741 return 0;
4742 }
4743 /* Warn if the e prefix on a general reg is present. */
4744 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4745 && i.types[op].bitfield.reg32
4746 && (i.tm.operand_types[op].bitfield.reg16
4747 || i.tm.operand_types[op].bitfield.acc))
252b5132 4748 {
29b0f896
AM		 4749 /* Prohibit these changes in the 64bit mode, since the
4750 lowering is more complicated. */
4751 if (flag_code == CODE_64BIT)
252b5132 4752 {
2ca3ace5
L		 4753 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4754 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4755 i.suffix);
4756 return 0;
252b5132 4757 }
29b0f896
AM		 4758 else
4759#if REGISTER_WARNINGS
a540244d
L		 4760 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4761 register_prefix,
29b0f896 4762 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4763 register_prefix,
29b0f896
AM		 4764 i.op[op].regs->reg_name,
4765 i.suffix);
4766#endif
4767 }
4768 return 1;
4769}
252b5132 4770
29b0f896 4771static int
40fb9820 4772update_imm (unsigned int j)
29b0f896 4773{
bc0844ae 4774 i386_operand_type overlap = i.types[j];
40fb9820
L		 4775 if ((overlap.bitfield.imm8
4776 || overlap.bitfield.imm8s
4777 || overlap.bitfield.imm16
4778 || overlap.bitfield.imm32
4779 || overlap.bitfield.imm32s
4780 || overlap.bitfield.imm64)
0dfbf9d7
L		 4781 && !operand_type_equal (&overlap, &imm8)
4782 && !operand_type_equal (&overlap, &imm8s)
4783 && !operand_type_equal (&overlap, &imm16)
4784 && !operand_type_equal (&overlap, &imm32)
4785 && !operand_type_equal (&overlap, &imm32s)
4786 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4787 {
4788 if (i.suffix)
4789 {
40fb9820
L		 4790 i386_operand_type temp;
4791
0dfbf9d7 4792 operand_type_set (&temp, 0);
7ab9ffdd 4793 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4794 {
4795 temp.bitfield.imm8 = overlap.bitfield.imm8;
4796 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4797 }
4798 else if (i.suffix == WORD_MNEM_SUFFIX)
4799 temp.bitfield.imm16 = overlap.bitfield.imm16;
4800 else if (i.suffix == QWORD_MNEM_SUFFIX)
4801 {
4802 temp.bitfield.imm64 = overlap.bitfield.imm64;
4803 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4804 }
4805 else
4806 temp.bitfield.imm32 = overlap.bitfield.imm32;
4807 overlap = temp;
29b0f896 4808 }
0dfbf9d7
L		 4809 else if (operand_type_equal (&overlap, &imm16_32_32s)
4810 || operand_type_equal (&overlap, &imm16_32)
4811 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4812 {
40fb9820 4813 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4814 overlap = imm16;
40fb9820 4815 else
65da13b5 4816 overlap = imm32s;
29b0f896 4817 }
0dfbf9d7
L		 4818 if (!operand_type_equal (&overlap, &imm8)
4819 && !operand_type_equal (&overlap, &imm8s)
4820 && !operand_type_equal (&overlap, &imm16)
4821 && !operand_type_equal (&overlap, &imm32)
4822 && !operand_type_equal (&overlap, &imm32s)
4823 && !operand_type_equal (&overlap, &imm64))
29b0f896 4824 {
4eed87de
AM		 4825 as_bad (_("no instruction mnemonic suffix given; "
4826 "can't determine immediate size"));
29b0f896
AM		 4827 return 0;
4828 }
4829 }
40fb9820 4830 i.types[j] = overlap;
29b0f896 4831
40fb9820
L		 4832 return 1;
4833}
4834
4835static int
4836finalize_imm (void)
4837{
bc0844ae 4838 unsigned int j, n;
29b0f896 4839
bc0844ae
L		 4840 /* Update the first 2 immediate operands. */
4841 n = i.operands > 2 ? 2 : i.operands;
4842 if (n)
4843 {
4844 for (j = 0; j < n; j++)
4845 if (update_imm (j) == 0)
4846 return 0;
40fb9820 4847
bc0844ae
L		 4848 /* The 3rd operand can't be immediate operand. */
4849 gas_assert (operand_type_check (i.types[2], imm) == 0);
4850 }
29b0f896
AM		 4851
4852 return 1;
4853}
4854
c0f3af97
L		 4855static int
4856bad_implicit_operand (int xmm)
4857{
91d6fa6a
NC		 4858 const char *ireg = xmm ? "xmm0" : "ymm0";
4859
c0f3af97
L		 4860 if (intel_syntax)
4861 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4862 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4863 else
4864 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4865 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4866 return 0;
4867}
4868
29b0f896 4869static int
e3bb37b5 4870process_operands (void)
29b0f896
AM		 4871{
4872 /* Default segment register this instruction will use for memory
4873 accesses. 0 means unknown. This is only for optimizing out
4874 unnecessary segment overrides. */
4875 const seg_entry *default_seg = 0;
4876
2426c15f 4877 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4878 {
91d6fa6a
NC		 4879 unsigned int dupl = i.operands;
4880 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4881 unsigned int j;
4882
c0f3af97 4883 /* The destination must be an xmm register. */
9c2799c2 4884 gas_assert (i.reg_operands
91d6fa6a 4885 && MAX_OPERANDS > dupl
7ab9ffdd 4886 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4887
4888 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4889 {
c0f3af97 4890 /* The first operand is implicit and must be xmm0. */
9c2799c2 4891 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4892 if (i.op[0].regs->reg_num != 0)
4893 return bad_implicit_operand (1);
4894
8cd7925b 4895 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4896 {
4897 /* Keep xmm0 for instructions with VEX prefix and 3
4898 sources. */
4899 goto duplicate;
4900 }
e2ec9d29 4901 else
c0f3af97
L		 4902 {
4903 /* We remove the first xmm0 and keep the number of
4904 operands unchanged, which in fact duplicates the
4905 destination. */
4906 for (j = 1; j < i.operands; j++)
4907 {
4908 i.op[j - 1] = i.op[j];
4909 i.types[j - 1] = i.types[j];
4910 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4911 }
4912 }
4913 }
4914 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4915 {
91d6fa6a 4916 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4917 && (i.tm.opcode_modifier.vexsources
4918 == VEX3SOURCES));
c0f3af97
L		 4919
4920 /* Add the implicit xmm0 for instructions with VEX prefix
4921 and 3 sources. */
4922 for (j = i.operands; j > 0; j--)
4923 {
4924 i.op[j] = i.op[j - 1];
4925 i.types[j] = i.types[j - 1];
4926 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4927 }
4928 i.op[0].regs
4929 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4930 i.types[0] = regxmm;
c0f3af97
L		 4931 i.tm.operand_types[0] = regxmm;
4932
4933 i.operands += 2;
4934 i.reg_operands += 2;
4935 i.tm.operands += 2;
4936
91d6fa6a 4937 dupl++;
c0f3af97 4938 dest++;
91d6fa6a
NC		 4939 i.op[dupl] = i.op[dest];
4940 i.types[dupl] = i.types[dest];
4941 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4942 }
c0f3af97
L		 4943 else
4944 {
4945duplicate:
4946 i.operands++;
4947 i.reg_operands++;
4948 i.tm.operands++;
4949
91d6fa6a
NC		 4950 i.op[dupl] = i.op[dest];
4951 i.types[dupl] = i.types[dest];
4952 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4953 }
4954
4955 if (i.tm.opcode_modifier.immext)
4956 process_immext ();
4957 }
4958 else if (i.tm.opcode_modifier.firstxmm0)
4959 {
4960 unsigned int j;
4961
4962 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4963 gas_assert (i.reg_operands
7ab9ffdd
L		 4964 && (operand_type_equal (&i.types[0], &regxmm)
4965 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4966 if (i.op[0].regs->reg_num != 0)
4967 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4968
4969 for (j = 1; j < i.operands; j++)
4970 {
4971 i.op[j - 1] = i.op[j];
4972 i.types[j - 1] = i.types[j];
4973
4974 /* We need to adjust fields in i.tm since they are used by
4975 build_modrm_byte. */
4976 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4977 }
4978
e2ec9d29
L		 4979 i.operands--;
4980 i.reg_operands--;
e2ec9d29
L		 4981 i.tm.operands--;
4982 }
4983 else if (i.tm.opcode_modifier.regkludge)
4984 {
4985 /* The imul $imm, %reg instruction is converted into
4986 imul $imm, %reg, %reg, and the clr %reg instruction
4987 is converted into xor %reg, %reg. */
4988
4989 unsigned int first_reg_op;
4990
4991 if (operand_type_check (i.types[0], reg))
4992 first_reg_op = 0;
4993 else
4994 first_reg_op = 1;
4995 /* Pretend we saw the extra register operand. */
9c2799c2 4996 gas_assert (i.reg_operands == 1
7ab9ffdd 4997 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4998 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4999 i.types[first_reg_op + 1] = i.types[first_reg_op];
5000 i.operands++;
5001 i.reg_operands++;
29b0f896
AM		 5002 }
5003
40fb9820 5004 if (i.tm.opcode_modifier.shortform)
29b0f896 5005 {
40fb9820
L		 5006 if (i.types[0].bitfield.sreg2
5007 || i.types[0].bitfield.sreg3)
29b0f896 5008 {
4eed87de
AM		 5009 if (i.tm.base_opcode == POP_SEG_SHORT
5010 && i.op[0].regs->reg_num == 1)
29b0f896 5011 {
a87af027 5012 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5013 return 0;
29b0f896 5014 }
4eed87de
AM		 5015 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5016 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5017 i.rex |= REX_B;
4eed87de
AM		 5018 }
5019 else
5020 {
7ab9ffdd 5021 /* The register or float register operand is in operand
85f10a01 5022 0 or 1. */
40fb9820 5023 unsigned int op;
7ab9ffdd
L		 5024
5025 if (i.types[0].bitfield.floatreg
5026 || operand_type_check (i.types[0], reg))
5027 op = 0;
5028 else
5029 op = 1;
4eed87de
AM		 5030 /* Register goes in low 3 bits of opcode. */
5031 i.tm.base_opcode |= i.op[op].regs->reg_num;
5032 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5033 i.rex |= REX_B;
40fb9820 5034 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5035 {
4eed87de
AM		 5036 /* Warn about some common errors, but press on regardless.
5037 The first case can be generated by gcc (<= 2.8.1). */
5038 if (i.operands == 2)
5039 {
5040 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5041 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5042 register_prefix, i.op[!intel_syntax].regs->reg_name,
5043 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5044 }
5045 else
5046 {
5047 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5048 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5049 register_prefix, i.op[0].regs->reg_name);
4eed87de 5050 }
29b0f896
AM		 5051 }
5052 }
5053 }
40fb9820 5054 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5055 {
5056 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5057 must be put into the modrm byte). Now, we make the modrm and
5058 index base bytes based on all the info we've collected. */
29b0f896
AM		 5059
5060 default_seg = build_modrm_byte ();
5061 }
8a2ed489 5062 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5063 {
5064 default_seg = &ds;
5065 }
40fb9820 5066 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5067 {
5068 /* For the string instructions that allow a segment override
5069 on one of their operands, the default segment is ds. */
5070 default_seg = &ds;
5071 }
5072
75178d9d
L		 5073 if (i.tm.base_opcode == 0x8d /* lea */
5074 && i.seg[0]
5075 && !quiet_warnings)
30123838 5076 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5077
5078 /* If a segment was explicitly specified, and the specified segment
5079 is not the default, use an opcode prefix to select it. If we
5080 never figured out what the default segment is, then default_seg
5081 will be zero at this point, and the specified segment prefix will
5082 always be used. */
29b0f896
AM		 5083 if ((i.seg[0]) && (i.seg[0] != default_seg))
5084 {
5085 if (!add_prefix (i.seg[0]->seg_prefix))
5086 return 0;
5087 }
5088 return 1;
5089}
5090
5091static const seg_entry *
e3bb37b5 5092build_modrm_byte (void)
29b0f896
AM		 5093{
5094 const seg_entry *default_seg = 0;
c0f3af97 5095 unsigned int source, dest;
8cd7925b 5096 int vex_3_sources;
c0f3af97
L		 5097
5098 /* The first operand of instructions with VEX prefix and 3 sources
5099 must be VEX_Imm4. */
8cd7925b 5100 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5101 if (vex_3_sources)
5102 {
91d6fa6a 5103 unsigned int nds, reg_slot;
4c2c6516 5104 expressionS *exp;
c0f3af97 5105
922d8de8 5106 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5107 && i.tm.opcode_modifier.immext)
5108 {
5109 dest = i.operands - 2;
5110 gas_assert (dest == 3);
5111 }
922d8de8 5112 else
a683cc34 5113 dest = i.operands - 1;
c0f3af97 5114 nds = dest - 1;
922d8de8 5115
a683cc34
SP		 5116 /* There are 2 kinds of instructions:
5117 1. 5 operands: 4 register operands or 3 register operands
5118 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5119 VexW0 or VexW1. The destination must be either XMM or YMM
5120 register.
5121 2. 4 operands: 4 register operands or 3 register operands
5122 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5123 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5124 || (i.reg_operands == 3 && i.mem_operands == 1))
5125 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5126 && (i.tm.opcode_modifier.veximmext
5127 || (i.imm_operands == 1
5128 && i.types[0].bitfield.vec_imm4
5129 && (i.tm.opcode_modifier.vexw == VEXW0
5130 || i.tm.opcode_modifier.vexw == VEXW1)
5131 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5132 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5133
5134 if (i.imm_operands == 0)
5135 {
5136 /* When there is no immediate operand, generate an 8bit
5137 immediate operand to encode the first operand. */
5138 exp = &im_expressions[i.imm_operands++];
5139 i.op[i.operands].imms = exp;
5140 i.types[i.operands] = imm8;
5141 i.operands++;
5142 /* If VexW1 is set, the first operand is the source and
5143 the second operand is encoded in the immediate operand. */
5144 if (i.tm.opcode_modifier.vexw == VEXW1)
5145 {
5146 source = 0;
5147 reg_slot = 1;
5148 }
5149 else
5150 {
5151 source = 1;
5152 reg_slot = 0;
5153 }
5154
5155 /* FMA swaps REG and NDS. */
5156 if (i.tm.cpu_flags.bitfield.cpufma)
5157 {
5158 unsigned int tmp;
5159 tmp = reg_slot;
5160 reg_slot = nds;
5161 nds = tmp;
5162 }
5163
24981e7b
L		 5164 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5165 &regxmm)
a683cc34
SP		 5166 || operand_type_equal (&i.tm.operand_types[reg_slot],
5167 &regymm));
5168 exp->X_op = O_constant;
5169 exp->X_add_number
5170 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5171 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5172 << 4);
a683cc34 5173 }
922d8de8 5174 else
a683cc34
SP		 5175 {
5176 unsigned int imm_slot;
5177
5178 if (i.tm.opcode_modifier.vexw == VEXW0)
5179 {
5180 /* If VexW0 is set, the third operand is the source and
5181 the second operand is encoded in the immediate
5182 operand. */
5183 source = 2;
5184 reg_slot = 1;
5185 }
5186 else
5187 {
5188 /* VexW1 is set, the second operand is the source and
5189 the third operand is encoded in the immediate
5190 operand. */
5191 source = 1;
5192 reg_slot = 2;
5193 }
5194
5195 if (i.tm.opcode_modifier.immext)
5196 {
5197 /* When ImmExt is set, the immdiate byte is the last
5198 operand. */
5199 imm_slot = i.operands - 1;
5200 source--;
5201 reg_slot--;
5202 }
5203 else
5204 {
5205 imm_slot = 0;
5206
5207 /* Turn on Imm8 so that output_imm will generate it. */
5208 i.types[imm_slot].bitfield.imm8 = 1;
5209 }
5210
24981e7b
L		 5211 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5212 &regxmm)
5213 || operand_type_equal (&i.tm.operand_types[reg_slot],
5214 &regymm));
a683cc34
SP		 5215 i.op[imm_slot].imms->X_add_number
5216 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5217 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5218 << 4);
a683cc34
SP		 5219 }
5220
5221 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5222 || operand_type_equal (&i.tm.operand_types[nds],
5223 &regymm));
dae39acc 5224 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5225 }
5226 else
5227 source = dest = 0;
29b0f896
AM		 5228
5229 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5230 implicit registers do not count. If there are 3 register
5231 operands, it must be a instruction with VexNDS. For a
5232 instruction with VexNDD, the destination register is encoded
5233 in VEX prefix. If there are 4 register operands, it must be
5234 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5235 if (i.mem_operands == 0
5236 && ((i.reg_operands == 2
2426c15f 5237 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5238 || (i.reg_operands == 3
2426c15f 5239 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5240 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5241 {
cab737b9
L		 5242 switch (i.operands)
5243 {
5244 case 2:
5245 source = 0;
5246 break;
5247 case 3:
c81128dc
L		 5248 /* When there are 3 operands, one of them may be immediate,
5249 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5250 the first operand must be shift count register (cl) or it
5251 is an instruction with VexNDS. */
9c2799c2 5252 gas_assert (i.imm_operands == 1
7ab9ffdd 5253 || (i.imm_operands == 0
2426c15f 5254 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5255 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5256 if (operand_type_check (i.types[0], imm)
5257 || i.types[0].bitfield.shiftcount)
5258 source = 1;
5259 else
5260 source = 0;
cab737b9
L		 5261 break;
5262 case 4:
368d64cc
L		 5263 /* When there are 4 operands, the first two must be 8bit
5264 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5265 one.
5266
5267 For instructions with VexNDS, if the first operand
5268 an imm8, the source operand is the 2nd one. If the last
5269 operand is imm8, the source operand is the first one. */
9c2799c2 5270 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5271 && i.types[0].bitfield.imm8
5272 && i.types[1].bitfield.imm8)
2426c15f 5273 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5274 && i.imm_operands == 1
5275 && (i.types[0].bitfield.imm8
5276 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5277 if (i.imm_operands == 2)
5278 source = 2;
5279 else
c0f3af97
L		 5280 {
5281 if (i.types[0].bitfield.imm8)
5282 source = 1;
5283 else
5284 source = 0;
5285 }
c0f3af97
L		 5286 break;
5287 case 5:
cab737b9
L		 5288 break;
5289 default:
5290 abort ();
5291 }
5292
c0f3af97
L		 5293 if (!vex_3_sources)
5294 {
5295 dest = source + 1;
5296
2426c15f 5297 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5298 {
5299 /* For instructions with VexNDS, the register-only
5300 source operand must be XMM or YMM register. It is
fa99fab2
L		 5301 encoded in VEX prefix. We need to clear RegMem bit
5302 before calling operand_type_equal. */
5303 i386_operand_type op = i.tm.operand_types[dest];
5304 op.bitfield.regmem = 0;
c0f3af97 5305 if ((dest + 1) >= i.operands
fa99fab2
L		 5306 || (!operand_type_equal (&op, &regxmm)
5307 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5308 abort ();
5309 i.vex.register_specifier = i.op[dest].regs;
5310 dest++;
5311 }
5312 }
29b0f896
AM		 5313
5314 i.rm.mode = 3;
5315 /* One of the register operands will be encoded in the i.tm.reg
5316 field, the other in the combined i.tm.mode and i.tm.regmem
5317 fields. If no form of this instruction supports a memory
5318 destination operand, then we assume the source operand may
5319 sometimes be a memory operand and so we need to store the
5320 destination in the i.rm.reg field. */
40fb9820
L		 5321 if (!i.tm.operand_types[dest].bitfield.regmem
5322 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5323 {
5324 i.rm.reg = i.op[dest].regs->reg_num;
5325 i.rm.regmem = i.op[source].regs->reg_num;
5326 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5327 i.rex |= REX_R;
29b0f896 5328 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5329 i.rex |= REX_B;
29b0f896
AM		 5330 }
5331 else
5332 {
5333 i.rm.reg = i.op[source].regs->reg_num;
5334 i.rm.regmem = i.op[dest].regs->reg_num;
5335 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5336 i.rex |= REX_B;
29b0f896 5337 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5338 i.rex |= REX_R;
29b0f896 5339 }
161a04f6 5340 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5341 {
40fb9820
L		 5342 if (!i.types[0].bitfield.control
5343 && !i.types[1].bitfield.control)
c4a530c5 5344 abort ();
161a04f6 5345 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5346 add_prefix (LOCK_PREFIX_OPCODE);
5347 }
29b0f896
AM		 5348 }
5349 else
5350 { /* If it's not 2 reg operands... */
c0f3af97
L		 5351 unsigned int mem;
5352
29b0f896
AM		 5353 if (i.mem_operands)
5354 {
5355 unsigned int fake_zero_displacement = 0;
99018f42 5356 unsigned int op;
4eed87de 5357
7ab9ffdd
L		 5358 for (op = 0; op < i.operands; op++)
5359 if (operand_type_check (i.types[op], anymem))
5360 break;
7ab9ffdd 5361 gas_assert (op < i.operands);
29b0f896
AM		 5362
5363 default_seg = &ds;
5364
5365 if (i.base_reg == 0)
5366 {
5367 i.rm.mode = 0;
5368 if (!i.disp_operands)
5369 fake_zero_displacement = 1;
5370 if (i.index_reg == 0)
5371 {
5372 /* Operand is just <disp> */
20f0a1fc 5373 if (flag_code == CODE_64BIT)
29b0f896
AM		 5374 {
5375 /* 64bit mode overwrites the 32bit absolute
5376 addressing by RIP relative addressing and
5377 absolute addressing is encoded by one of the
5378 redundant SIB forms. */
5379 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5380 i.sib.base = NO_BASE_REGISTER;
5381 i.sib.index = NO_INDEX_REGISTER;
fc225355 5382 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5383 ? disp32s : disp32);
20f0a1fc 5384 }
fc225355
L		 5385 else if ((flag_code == CODE_16BIT)
5386 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5387 {
5388 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5389 i.types[op] = disp16;
20f0a1fc
NC		 5390 }
5391 else
5392 {
5393 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5394 i.types[op] = disp32;
29b0f896
AM		 5395 }
5396 }
5397 else /* !i.base_reg && i.index_reg */
5398 {
db51cc60
L		 5399 if (i.index_reg->reg_num == RegEiz
5400 || i.index_reg->reg_num == RegRiz)
5401 i.sib.index = NO_INDEX_REGISTER;
5402 else
5403 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5404 i.sib.base = NO_BASE_REGISTER;
5405 i.sib.scale = i.log2_scale_factor;
5406 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5407 i.types[op].bitfield.disp8 = 0;
5408 i.types[op].bitfield.disp16 = 0;
5409 i.types[op].bitfield.disp64 = 0;
29b0f896 5410 if (flag_code != CODE_64BIT)
40fb9820
L		 5411 {
5412 /* Must be 32 bit */
5413 i.types[op].bitfield.disp32 = 1;
5414 i.types[op].bitfield.disp32s = 0;
5415 }
29b0f896 5416 else
40fb9820
L		 5417 {
5418 i.types[op].bitfield.disp32 = 0;
5419 i.types[op].bitfield.disp32s = 1;
5420 }
29b0f896 5421 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5422 i.rex |= REX_X;
29b0f896
AM		 5423 }
5424 }
5425 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5426 else if (i.base_reg->reg_num == RegRip ||
5427 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5428 {
5429 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5430 i.types[op].bitfield.disp8 = 0;
5431 i.types[op].bitfield.disp16 = 0;
5432 i.types[op].bitfield.disp32 = 0;
5433 i.types[op].bitfield.disp32s = 1;
5434 i.types[op].bitfield.disp64 = 0;
71903a11 5435 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5436 if (! i.disp_operands)
5437 fake_zero_displacement = 1;
29b0f896 5438 }
40fb9820 5439 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5440 {
5441 switch (i.base_reg->reg_num)
5442 {
5443 case 3: /* (%bx) */
5444 if (i.index_reg == 0)
5445 i.rm.regmem = 7;
5446 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5447 i.rm.regmem = i.index_reg->reg_num - 6;
5448 break;
5449 case 5: /* (%bp) */
5450 default_seg = &ss;
5451 if (i.index_reg == 0)
5452 {
5453 i.rm.regmem = 6;
40fb9820 5454 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5455 {
5456 /* fake (%bp) into 0(%bp) */
40fb9820 5457 i.types[op].bitfield.disp8 = 1;
252b5132 5458 fake_zero_displacement = 1;
29b0f896
AM		 5459 }
5460 }
5461 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5462 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5463 break;
5464 default: /* (%si) -> 4 or (%di) -> 5 */
5465 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5466 }
5467 i.rm.mode = mode_from_disp_size (i.types[op]);
5468 }
5469 else /* i.base_reg and 32/64 bit mode */
5470 {
5471 if (flag_code == CODE_64BIT
40fb9820
L		 5472 && operand_type_check (i.types[op], disp))
5473 {
5474 i386_operand_type temp;
0dfbf9d7 5475 operand_type_set (&temp, 0);
40fb9820
L		 5476 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5477 i.types[op] = temp;
5478 if (i.prefix[ADDR_PREFIX] == 0)
5479 i.types[op].bitfield.disp32s = 1;
5480 else
5481 i.types[op].bitfield.disp32 = 1;
5482 }
20f0a1fc 5483
29b0f896
AM		 5484 i.rm.regmem = i.base_reg->reg_num;
5485 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5486 i.rex |= REX_B;
29b0f896
AM		 5487 i.sib.base = i.base_reg->reg_num;
5488 /* x86-64 ignores REX prefix bit here to avoid decoder
5489 complications. */
5490 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5491 {
5492 default_seg = &ss;
5493 if (i.disp_operands == 0)
5494 {
5495 fake_zero_displacement = 1;
40fb9820 5496 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5497 }
5498 }
5499 else if (i.base_reg->reg_num == ESP_REG_NUM)
5500 {
5501 default_seg = &ss;
5502 }
5503 i.sib.scale = i.log2_scale_factor;
5504 if (i.index_reg == 0)
5505 {
5506 /* <disp>(%esp) becomes two byte modrm with no index
5507 register. We've already stored the code for esp
5508 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5509 Any base register besides %esp will not use the
5510 extra modrm byte. */
5511 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5512 }
5513 else
5514 {
db51cc60
L		 5515 if (i.index_reg->reg_num == RegEiz
5516 || i.index_reg->reg_num == RegRiz)
5517 i.sib.index = NO_INDEX_REGISTER;
5518 else
5519 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5520 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5521 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5522 i.rex |= REX_X;
29b0f896 5523 }
67a4f2b7
AO		 5524
5525 if (i.disp_operands
5526 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5527 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5528 i.rm.mode = 0;
5529 else
5530 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5531 }
252b5132 5532
29b0f896
AM		 5533 if (fake_zero_displacement)
5534 {
5535 /* Fakes a zero displacement assuming that i.types[op]
5536 holds the correct displacement size. */
5537 expressionS *exp;
5538
9c2799c2 5539 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5540 exp = &disp_expressions[i.disp_operands++];
5541 i.op[op].disps = exp;
5542 exp->X_op = O_constant;
5543 exp->X_add_number = 0;
5544 exp->X_add_symbol = (symbolS *) 0;
5545 exp->X_op_symbol = (symbolS *) 0;
5546 }
c0f3af97
L		 5547
5548 mem = op;
29b0f896 5549 }
c0f3af97
L		 5550 else
5551 mem = ~0;
252b5132 5552
8c43a48b 5553 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5554 {
5555 if (operand_type_check (i.types[0], imm))
5556 i.vex.register_specifier = NULL;
5557 else
5558 {
5559 /* VEX.vvvv encodes one of the sources when the first
5560 operand is not an immediate. */
1ef99a7b 5561 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5562 i.vex.register_specifier = i.op[0].regs;
5563 else
5564 i.vex.register_specifier = i.op[1].regs;
5565 }
5566
5567 /* Destination is a XMM register encoded in the ModRM.reg
5568 and VEX.R bit. */
5569 i.rm.reg = i.op[2].regs->reg_num;
5570 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5571 i.rex |= REX_R;
5572
5573 /* ModRM.rm and VEX.B encodes the other source. */
5574 if (!i.mem_operands)
5575 {
5576 i.rm.mode = 3;
5577
1ef99a7b 5578 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5579 i.rm.regmem = i.op[1].regs->reg_num;
5580 else
5581 i.rm.regmem = i.op[0].regs->reg_num;
5582
5583 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5584 i.rex |= REX_B;
5585 }
5586 }
2426c15f 5587 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5588 {
5589 i.vex.register_specifier = i.op[2].regs;
5590 if (!i.mem_operands)
5591 {
5592 i.rm.mode = 3;
5593 i.rm.regmem = i.op[1].regs->reg_num;
5594 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5595 i.rex |= REX_B;
5596 }
5597 }
29b0f896
AM		 5598 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5599 (if any) based on i.tm.extension_opcode. Again, we must be
5600 careful to make sure that segment/control/debug/test/MMX
5601 registers are coded into the i.rm.reg field. */
f88c9eb0 5602 else if (i.reg_operands)
29b0f896 5603 {
99018f42 5604 unsigned int op;
7ab9ffdd
L		 5605 unsigned int vex_reg = ~0;
5606
5607 for (op = 0; op < i.operands; op++)
5608 if (i.types[op].bitfield.reg8
5609 || i.types[op].bitfield.reg16
5610 || i.types[op].bitfield.reg32
5611 || i.types[op].bitfield.reg64
5612 || i.types[op].bitfield.regmmx
5613 || i.types[op].bitfield.regxmm
5614 || i.types[op].bitfield.regymm
5615 || i.types[op].bitfield.sreg2
5616 || i.types[op].bitfield.sreg3
5617 || i.types[op].bitfield.control
5618 || i.types[op].bitfield.debug
5619 || i.types[op].bitfield.test)
5620 break;
c0209578 5621
7ab9ffdd
L		 5622 if (vex_3_sources)
5623 op = dest;
2426c15f 5624 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5625 {
5626 /* For instructions with VexNDS, the register-only
5627 source operand is encoded in VEX prefix. */
5628 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5629
7ab9ffdd 5630 if (op > mem)
c0f3af97 5631 {
7ab9ffdd
L		 5632 vex_reg = op++;
5633 gas_assert (op < i.operands);
c0f3af97
L		 5634 }
5635 else
c0f3af97 5636 {
7ab9ffdd
L		 5637 vex_reg = op + 1;
5638 gas_assert (vex_reg < i.operands);
c0f3af97 5639 }
7ab9ffdd 5640 }
2426c15f 5641 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5642 {
5643 /* For instructions with VexNDD, there should be
5644 no memory operand and the register destination
5645 is encoded in VEX prefix. */
5646 gas_assert (i.mem_operands == 0
5647 && (op + 2) == i.operands);
5648 vex_reg = op + 1;
5649 }
5650 else
5651 gas_assert (op < i.operands);
99018f42 5652
7ab9ffdd
L		 5653 if (vex_reg != (unsigned int) ~0)
5654 {
5655 gas_assert (i.reg_operands == 2);
5656
5657 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5658 &regxmm)
7ab9ffdd
L		 5659 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5660 &regymm))
5661 abort ();
f88c9eb0 5662
7ab9ffdd
L		 5663 i.vex.register_specifier = i.op[vex_reg].regs;
5664 }
5665
1b9f0c97
L		 5666 /* Don't set OP operand twice. */
5667 if (vex_reg != op)
7ab9ffdd 5668 {
1b9f0c97
L		 5669 /* If there is an extension opcode to put here, the
5670 register number must be put into the regmem field. */
5671 if (i.tm.extension_opcode != None)
5672 {
5673 i.rm.regmem = i.op[op].regs->reg_num;
5674 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5675 i.rex |= REX_B;
5676 }
5677 else
5678 {
5679 i.rm.reg = i.op[op].regs->reg_num;
5680 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5681 i.rex |= REX_R;
5682 }
7ab9ffdd 5683 }
252b5132 5684
29b0f896
AM		 5685 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5686 must set it to 3 to indicate this is a register operand
5687 in the regmem field. */
5688 if (!i.mem_operands)
5689 i.rm.mode = 3;
5690 }
252b5132 5691
29b0f896 5692 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5693 if (i.tm.extension_opcode != None)
29b0f896
AM		 5694 i.rm.reg = i.tm.extension_opcode;
5695 }
5696 return default_seg;
5697}
252b5132 5698
29b0f896 5699static void
e3bb37b5 5700output_branch (void)
29b0f896
AM		 5701{
5702 char *p;
f8a5c266 5703 int size;
29b0f896
AM		 5704 int code16;
5705 int prefix;
5706 relax_substateT subtype;
5707 symbolS *sym;
5708 offsetT off;
5709
f8a5c266
L		 5710 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
5711 size = i.disp32_encoding ? BIG : SMALL;
29b0f896
AM		 5712
5713 prefix = 0;
5714 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5715 {
29b0f896
AM		 5716 prefix = 1;
5717 i.prefixes -= 1;
5718 code16 ^= CODE16;
252b5132 5719 }
29b0f896
AM		 5720 /* Pentium4 branch hints. */
5721 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5722 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5723 {
29b0f896
AM		 5724 prefix++;
5725 i.prefixes--;
5726 }
5727 if (i.prefix[REX_PREFIX] != 0)
5728 {
5729 prefix++;
5730 i.prefixes--;
2f66722d
AM		 5731 }
5732
29b0f896
AM		 5733 if (i.prefixes != 0 && !intel_syntax)
5734 as_warn (_("skipping prefixes on this instruction"));
5735
5736 /* It's always a symbol; End frag & setup for relax.
5737 Make sure there is enough room in this frag for the largest
5738 instruction we may generate in md_convert_frag. This is 2
5739 bytes for the opcode and room for the prefix and largest
5740 displacement. */
5741 frag_grow (prefix + 2 + 4);
5742 /* Prefix and 1 opcode byte go in fr_fix. */
5743 p = frag_more (prefix + 1);
5744 if (i.prefix[DATA_PREFIX] != 0)
5745 *p++ = DATA_PREFIX_OPCODE;
5746 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5747 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5748 *p++ = i.prefix[SEG_PREFIX];
5749 if (i.prefix[REX_PREFIX] != 0)
5750 *p++ = i.prefix[REX_PREFIX];
5751 *p = i.tm.base_opcode;
5752
5753 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 5754 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 5755 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 5756 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 5757 else
f8a5c266 5758 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 5759 subtype |= code16;
3e73aa7c 5760
29b0f896
AM		 5761 sym = i.op[0].disps->X_add_symbol;
5762 off = i.op[0].disps->X_add_number;
3e73aa7c 5763
29b0f896
AM		 5764 if (i.op[0].disps->X_op != O_constant
5765 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5766 {
29b0f896
AM		 5767 /* Handle complex expressions. */
5768 sym = make_expr_symbol (i.op[0].disps);
5769 off = 0;
5770 }
3e73aa7c 5771
29b0f896
AM		 5772 /* 1 possible extra opcode + 4 byte displacement go in var part.
5773 Pass reloc in fr_var. */
5774 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5775}
3e73aa7c 5776
29b0f896 5777static void
e3bb37b5 5778output_jump (void)
29b0f896
AM		 5779{
5780 char *p;
5781 int size;
3e02c1cc 5782 fixS *fixP;
29b0f896 5783
40fb9820 5784 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5785 {
5786 /* This is a loop or jecxz type instruction. */
5787 size = 1;
5788 if (i.prefix[ADDR_PREFIX] != 0)
5789 {
5790 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5791 i.prefixes -= 1;
5792 }
5793 /* Pentium4 branch hints. */
5794 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5795 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5796 {
5797 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5798 i.prefixes--;
3e73aa7c
JH		 5799 }
5800 }
29b0f896
AM		 5801 else
5802 {
5803 int code16;
3e73aa7c 5804
29b0f896
AM		 5805 code16 = 0;
5806 if (flag_code == CODE_16BIT)
5807 code16 = CODE16;
3e73aa7c 5808
29b0f896
AM		 5809 if (i.prefix[DATA_PREFIX] != 0)
5810 {
5811 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5812 i.prefixes -= 1;
5813 code16 ^= CODE16;
5814 }
252b5132 5815
29b0f896
AM		 5816 size = 4;
5817 if (code16)
5818 size = 2;
5819 }
9fcc94b6 5820
29b0f896
AM		 5821 if (i.prefix[REX_PREFIX] != 0)
5822 {
5823 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5824 i.prefixes -= 1;
5825 }
252b5132 5826
29b0f896
AM		 5827 if (i.prefixes != 0 && !intel_syntax)
5828 as_warn (_("skipping prefixes on this instruction"));
e0890092 5829
29b0f896
AM		 5830 p = frag_more (1 + size);
5831 *p++ = i.tm.base_opcode;
e0890092 5832
3e02c1cc
AM		 5833 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5834 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5835
5836 /* All jumps handled here are signed, but don't use a signed limit
5837 check for 32 and 16 bit jumps as we want to allow wrap around at
5838 4G and 64k respectively. */
5839 if (size == 1)
5840 fixP->fx_signed = 1;
29b0f896 5841}
e0890092 5842
29b0f896 5843static void
e3bb37b5 5844output_interseg_jump (void)
29b0f896
AM		 5845{
5846 char *p;
5847 int size;
5848 int prefix;
5849 int code16;
252b5132 5850
29b0f896
AM		 5851 code16 = 0;
5852 if (flag_code == CODE_16BIT)
5853 code16 = CODE16;
a217f122 5854
29b0f896
AM		 5855 prefix = 0;
5856 if (i.prefix[DATA_PREFIX] != 0)
5857 {
5858 prefix = 1;
5859 i.prefixes -= 1;
5860 code16 ^= CODE16;
5861 }
5862 if (i.prefix[REX_PREFIX] != 0)
5863 {
5864 prefix++;
5865 i.prefixes -= 1;
5866 }
252b5132 5867
29b0f896
AM		 5868 size = 4;
5869 if (code16)
5870 size = 2;
252b5132 5871
29b0f896
AM		 5872 if (i.prefixes != 0 && !intel_syntax)
5873 as_warn (_("skipping prefixes on this instruction"));
252b5132 5874
29b0f896
AM		 5875 /* 1 opcode; 2 segment; offset */
5876 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5877
29b0f896
AM		 5878 if (i.prefix[DATA_PREFIX] != 0)
5879 *p++ = DATA_PREFIX_OPCODE;
252b5132 5880
29b0f896
AM		 5881 if (i.prefix[REX_PREFIX] != 0)
5882 *p++ = i.prefix[REX_PREFIX];
252b5132 5883
29b0f896
AM		 5884 *p++ = i.tm.base_opcode;
5885 if (i.op[1].imms->X_op == O_constant)
5886 {
5887 offsetT n = i.op[1].imms->X_add_number;
252b5132 5888
29b0f896
AM		 5889 if (size == 2
5890 && !fits_in_unsigned_word (n)
5891 && !fits_in_signed_word (n))
5892 {
5893 as_bad (_("16-bit jump out of range"));
5894 return;
5895 }
5896 md_number_to_chars (p, n, size);
5897 }
5898 else
5899 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5900 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5901 if (i.op[0].imms->X_op != O_constant)
5902 as_bad (_("can't handle non absolute segment in `%s'"),
5903 i.tm.name);
5904 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5905}
a217f122 5906
29b0f896 5907static void
e3bb37b5 5908output_insn (void)
29b0f896 5909{
2bbd9c25
JJ		 5910 fragS *insn_start_frag;
5911 offsetT insn_start_off;
5912
29b0f896
AM		 5913 /* Tie dwarf2 debug info to the address at the start of the insn.
5914 We can't do this after the insn has been output as the current
5915 frag may have been closed off. eg. by frag_var. */
5916 dwarf2_emit_insn (0);
5917
2bbd9c25
JJ		 5918 insn_start_frag = frag_now;
5919 insn_start_off = frag_now_fix ();
5920
29b0f896 5921 /* Output jumps. */
40fb9820 5922 if (i.tm.opcode_modifier.jump)
29b0f896 5923 output_branch ();
40fb9820
L		 5924 else if (i.tm.opcode_modifier.jumpbyte
5925 || i.tm.opcode_modifier.jumpdword)
29b0f896 5926 output_jump ();
40fb9820 5927 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5928 output_interseg_jump ();
5929 else
5930 {
5931 /* Output normal instructions here. */
5932 char *p;
5933 unsigned char *q;
47465058 5934 unsigned int j;
331d2d0d 5935 unsigned int prefix;
4dffcebc 5936
c0f3af97
L		 5937 /* Since the VEX prefix contains the implicit prefix, we don't
5938 need the explicit prefix. */
5939 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5940 {
c0f3af97 5941 switch (i.tm.opcode_length)
bc4bd9ab 5942 {
c0f3af97
L		 5943 case 3:
5944 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5945 {
c0f3af97
L		 5946 prefix = (i.tm.base_opcode >> 24) & 0xff;
5947 goto check_prefix;
5948 }
5949 break;
5950 case 2:
5951 if ((i.tm.base_opcode & 0xff0000) != 0)
5952 {
5953 prefix = (i.tm.base_opcode >> 16) & 0xff;
5954 if (i.tm.cpu_flags.bitfield.cpupadlock)
5955 {
4dffcebc 5956check_prefix:
c0f3af97 5957 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5958 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5959 != REPE_PREFIX_OPCODE))
5960 add_prefix (prefix);
5961 }
5962 else
4dffcebc
L		 5963 add_prefix (prefix);
5964 }
c0f3af97
L		 5965 break;
5966 case 1:
5967 break;
5968 default:
5969 abort ();
bc4bd9ab 5970 }
c0f3af97
L		 5971
5972 /* The prefix bytes. */
5973 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5974 if (*q)
5975 FRAG_APPEND_1_CHAR (*q);
0f10071e 5976 }
252b5132 5977
c0f3af97
L		 5978 if (i.tm.opcode_modifier.vex)
5979 {
5980 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5981 if (*q)
5982 switch (j)
5983 {
5984 case REX_PREFIX:
5985 /* REX byte is encoded in VEX prefix. */
5986 break;
5987 case SEG_PREFIX:
5988 case ADDR_PREFIX:
5989 FRAG_APPEND_1_CHAR (*q);
5990 break;
5991 default:
5992 /* There should be no other prefixes for instructions
5993 with VEX prefix. */
5994 abort ();
5995 }
5996
5997 /* Now the VEX prefix. */
5998 p = frag_more (i.vex.length);
5999 for (j = 0; j < i.vex.length; j++)
6000 p[j] = i.vex.bytes[j];
6001 }
252b5132 6002
29b0f896 6003 /* Now the opcode; be careful about word order here! */
4dffcebc 6004 if (i.tm.opcode_length == 1)
29b0f896
AM		 6005 {
6006 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6007 }
6008 else
6009 {
4dffcebc 6010 switch (i.tm.opcode_length)
331d2d0d 6011 {
4dffcebc 6012 case 3:
331d2d0d
L		 6013 p = frag_more (3);
6014 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6015 break;
6016 case 2:
6017 p = frag_more (2);
6018 break;
6019 default:
6020 abort ();
6021 break;
331d2d0d 6022 }
0f10071e 6023
29b0f896
AM		 6024 /* Put out high byte first: can't use md_number_to_chars! */
6025 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6026 *p = i.tm.base_opcode & 0xff;
6027 }
3e73aa7c 6028
29b0f896 6029 /* Now the modrm byte and sib byte (if present). */
40fb9820 6030 if (i.tm.opcode_modifier.modrm)
29b0f896 6031 {
4a3523fa
L		 6032 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6033 | i.rm.reg << 3
6034 | i.rm.mode << 6));
29b0f896
AM		 6035 /* If i.rm.regmem == ESP (4)
6036 && i.rm.mode != (Register mode)
6037 && not 16 bit
6038 ==> need second modrm byte. */
6039 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6040 && i.rm.mode != 3
40fb9820 6041 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6042 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6043 | i.sib.index << 3
6044 | i.sib.scale << 6));
29b0f896 6045 }
3e73aa7c 6046
29b0f896 6047 if (i.disp_operands)
2bbd9c25 6048 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6049
29b0f896 6050 if (i.imm_operands)
2bbd9c25 6051 output_imm (insn_start_frag, insn_start_off);
29b0f896 6052 }
252b5132 6053
29b0f896
AM		 6054#ifdef DEBUG386
6055 if (flag_debug)
6056 {
7b81dfbb 6057 pi ("" /*line*/, &i);
29b0f896
AM		 6058 }
6059#endif /* DEBUG386 */
6060}
252b5132 6061
e205caa7
L		 6062/* Return the size of the displacement operand N. */
6063
6064static int
6065disp_size (unsigned int n)
6066{
6067 int size = 4;
40fb9820
L		 6068 if (i.types[n].bitfield.disp64)
6069 size = 8;
6070 else if (i.types[n].bitfield.disp8)
6071 size = 1;
6072 else if (i.types[n].bitfield.disp16)
6073 size = 2;
e205caa7
L		 6074 return size;
6075}
6076
6077/* Return the size of the immediate operand N. */
6078
6079static int
6080imm_size (unsigned int n)
6081{
6082 int size = 4;
40fb9820
L		 6083 if (i.types[n].bitfield.imm64)
6084 size = 8;
6085 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6086 size = 1;
6087 else if (i.types[n].bitfield.imm16)
6088 size = 2;
e205caa7
L		 6089 return size;
6090}
6091
29b0f896 6092static void
64e74474 6093output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6094{
6095 char *p;
6096 unsigned int n;
252b5132 6097
29b0f896
AM		 6098 for (n = 0; n < i.operands; n++)
6099 {
40fb9820 6100 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6101 {
6102 if (i.op[n].disps->X_op == O_constant)
6103 {
e205caa7 6104 int size = disp_size (n);
29b0f896 6105 offsetT val;
252b5132 6106
29b0f896
AM		 6107 val = offset_in_range (i.op[n].disps->X_add_number,
6108 size);
6109 p = frag_more (size);
6110 md_number_to_chars (p, val, size);
6111 }
6112 else
6113 {
f86103b7 6114 enum bfd_reloc_code_real reloc_type;
e205caa7 6115 int size = disp_size (n);
40fb9820 6116 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6117 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6118
e205caa7 6119 /* We can't have 8 bit displacement here. */
9c2799c2 6120 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6121
29b0f896
AM		 6122 /* The PC relative address is computed relative
6123 to the instruction boundary, so in case immediate
6124 fields follows, we need to adjust the value. */
6125 if (pcrel && i.imm_operands)
6126 {
29b0f896 6127 unsigned int n1;
e205caa7 6128 int sz = 0;
252b5132 6129
29b0f896 6130 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6131 if (operand_type_check (i.types[n1], imm))
252b5132 6132 {
e205caa7
L		 6133 /* Only one immediate is allowed for PC
6134 relative address. */
9c2799c2 6135 gas_assert (sz == 0);
e205caa7
L		 6136 sz = imm_size (n1);
6137 i.op[n].disps->X_add_number -= sz;
252b5132 6138 }
29b0f896 6139 /* We should find the immediate. */
9c2799c2 6140 gas_assert (sz != 0);
29b0f896 6141 }
520dc8e8 6142
29b0f896 6143 p = frag_more (size);
2bbd9c25 6144 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6145 if (GOT_symbol
2bbd9c25 6146 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6147 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6148 || reloc_type == BFD_RELOC_X86_64_32S
6149 || (reloc_type == BFD_RELOC_64
6150 && object_64bit))
d6ab8113
JB		 6151 && (i.op[n].disps->X_op == O_symbol
6152 || (i.op[n].disps->X_op == O_add
6153 && ((symbol_get_value_expression
6154 (i.op[n].disps->X_op_symbol)->X_op)
6155 == O_subtract))))
6156 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6157 {
6158 offsetT add;
6159
6160 if (insn_start_frag == frag_now)
6161 add = (p - frag_now->fr_literal) - insn_start_off;
6162 else
6163 {
6164 fragS *fr;
6165
6166 add = insn_start_frag->fr_fix - insn_start_off;
6167 for (fr = insn_start_frag->fr_next;
6168 fr && fr != frag_now; fr = fr->fr_next)
6169 add += fr->fr_fix;
6170 add += p - frag_now->fr_literal;
6171 }
6172
4fa24527 6173 if (!object_64bit)
7b81dfbb
AJ		 6174 {
6175 reloc_type = BFD_RELOC_386_GOTPC;
6176 i.op[n].imms->X_add_number += add;
6177 }
6178 else if (reloc_type == BFD_RELOC_64)
6179 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6180 else
7b81dfbb
AJ		 6181 /* Don't do the adjustment for x86-64, as there
6182 the pcrel addressing is relative to the _next_
6183 insn, and that is taken care of in other code. */
d6ab8113 6184 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6185 }
062cd5e7 6186 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6187 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6188 }
6189 }
6190 }
6191}
252b5132 6192
29b0f896 6193static void
64e74474 6194output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6195{
6196 char *p;
6197 unsigned int n;
252b5132 6198
29b0f896
AM		 6199 for (n = 0; n < i.operands; n++)
6200 {
40fb9820 6201 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6202 {
6203 if (i.op[n].imms->X_op == O_constant)
6204 {
e205caa7 6205 int size = imm_size (n);
29b0f896 6206 offsetT val;
b4cac588 6207
29b0f896
AM		 6208 val = offset_in_range (i.op[n].imms->X_add_number,
6209 size);
6210 p = frag_more (size);
6211 md_number_to_chars (p, val, size);
6212 }
6213 else
6214 {
6215 /* Not absolute_section.
6216 Need a 32-bit fixup (don't support 8bit
6217 non-absolute imms). Try to support other
6218 sizes ... */
f86103b7 6219 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6220 int size = imm_size (n);
6221 int sign;
29b0f896 6222
40fb9820 6223 if (i.types[n].bitfield.imm32s
a7d61044 6224 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6225 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6226 sign = 1;
e205caa7
L		 6227 else
6228 sign = 0;
520dc8e8 6229
29b0f896
AM		 6230 p = frag_more (size);
6231 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6232
2bbd9c25
JJ		 6233 /* This is tough to explain. We end up with this one if we
6234 * have operands that look like
6235 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6236 * obtain the absolute address of the GOT, and it is strongly
6237 * preferable from a performance point of view to avoid using
6238 * a runtime relocation for this. The actual sequence of
6239 * instructions often look something like:
6240 *
6241 * call .L66
6242 * .L66:
6243 * popl %ebx
6244 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6245 *
6246 * The call and pop essentially return the absolute address
6247 * of the label .L66 and store it in %ebx. The linker itself
6248 * will ultimately change the first operand of the addl so
6249 * that %ebx points to the GOT, but to keep things simple, the
6250 * .o file must have this operand set so that it generates not
6251 * the absolute address of .L66, but the absolute address of
6252 * itself. This allows the linker itself simply treat a GOTPC
6253 * relocation as asking for a pcrel offset to the GOT to be
6254 * added in, and the addend of the relocation is stored in the
6255 * operand field for the instruction itself.
6256 *
6257 * Our job here is to fix the operand so that it would add
6258 * the correct offset so that %ebx would point to itself. The
6259 * thing that is tricky is that .-.L66 will point to the
6260 * beginning of the instruction, so we need to further modify
6261 * the operand so that it will point to itself. There are
6262 * other cases where you have something like:
6263 *
6264 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6265 *
6266 * and here no correction would be required. Internally in
6267 * the assembler we treat operands of this form as not being
6268 * pcrel since the '.' is explicitly mentioned, and I wonder
6269 * whether it would simplify matters to do it this way. Who
6270 * knows. In earlier versions of the PIC patches, the
6271 * pcrel_adjust field was used to store the correction, but
6272 * since the expression is not pcrel, I felt it would be
6273 * confusing to do it this way. */
6274
d6ab8113 6275 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6276 || reloc_type == BFD_RELOC_X86_64_32S
6277 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6278 && GOT_symbol
6279 && GOT_symbol == i.op[n].imms->X_add_symbol
6280 && (i.op[n].imms->X_op == O_symbol
6281 || (i.op[n].imms->X_op == O_add
6282 && ((symbol_get_value_expression
6283 (i.op[n].imms->X_op_symbol)->X_op)
6284 == O_subtract))))
6285 {
2bbd9c25
JJ		 6286 offsetT add;
6287
6288 if (insn_start_frag == frag_now)
6289 add = (p - frag_now->fr_literal) - insn_start_off;
6290 else
6291 {
6292 fragS *fr;
6293
6294 add = insn_start_frag->fr_fix - insn_start_off;
6295 for (fr = insn_start_frag->fr_next;
6296 fr && fr != frag_now; fr = fr->fr_next)
6297 add += fr->fr_fix;
6298 add += p - frag_now->fr_literal;
6299 }
6300
4fa24527 6301 if (!object_64bit)
d6ab8113 6302 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6303 else if (size == 4)
d6ab8113 6304 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6305 else if (size == 8)
6306 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6307 i.op[n].imms->X_add_number += add;
29b0f896 6308 }
29b0f896
AM		 6309 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6310 i.op[n].imms, 0, reloc_type);
6311 }
6312 }
6313 }
252b5132
RH		 6314}
6315\f
d182319b
JB		 6316/* x86_cons_fix_new is called via the expression parsing code when a
6317 reloc is needed. We use this hook to get the correct .got reloc. */
6318static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6319static int cons_sign = -1;
6320
6321void
e3bb37b5 6322x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6323 expressionS *exp)
d182319b
JB		 6324{
6325 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6326
6327 got_reloc = NO_RELOC;
6328
6329#ifdef TE_PE
6330 if (exp->X_op == O_secrel)
6331 {
6332 exp->X_op = O_symbol;
6333 r = BFD_RELOC_32_SECREL;
6334 }
6335#endif
6336
6337 fix_new_exp (frag, off, len, exp, 0, r);
6338}
6339
718ddfc0
JB		 6340#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6341# define lex_got(reloc, adjust, types) NULL
6342#else
f3c180ae
AM		 6343/* Parse operands of the form
6344 <symbol>@GOTOFF+<nnn>
6345 and similar .plt or .got references.
6346
6347 If we find one, set up the correct relocation in RELOC and copy the
6348 input string, minus the `@GOTOFF' into a malloc'd buffer for
6349 parsing by the calling routine. Return this buffer, and if ADJUST
6350 is non-null set it to the length of the string we removed from the
6351 input line. Otherwise return NULL. */
6352static char *
91d6fa6a 6353lex_got (enum bfd_reloc_code_real *rel,
64e74474 6354 int *adjust,
40fb9820 6355 i386_operand_type *types)
f3c180ae 6356{
7b81dfbb
AJ		 6357 /* Some of the relocations depend on the size of what field is to
6358 be relocated. But in our callers i386_immediate and i386_displacement
6359 we don't yet know the operand size (this will be set by insn
6360 matching). Hence we record the word32 relocation here,
6361 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6362 static const struct {
6363 const char *str;
cff8d58a 6364 int len;
4fa24527 6365 const enum bfd_reloc_code_real rel[2];
40fb9820 6366 const i386_operand_type types64;
f3c180ae 6367 } gotrel[] = {
cff8d58a
L		 6368 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6369 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6370 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6371 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6372 BFD_RELOC_X86_64_PLT32 },
40fb9820 6373 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6374 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6375 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6376 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6377 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6378 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6379 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6380 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6381 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6382 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6383 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6384 BFD_RELOC_X86_64_TLSGD },
40fb9820 6385 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6386 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6387 _dummy_first_bfd_reloc_code_real },
40fb9820 6388 OPERAND_TYPE_NONE },
cff8d58a
L		 6389 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6390 BFD_RELOC_X86_64_TLSLD },
40fb9820 6391 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6392 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6393 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6394 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6395 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6396 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6397 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6398 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6399 _dummy_first_bfd_reloc_code_real },
40fb9820 6400 OPERAND_TYPE_NONE },
cff8d58a
L		 6401 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6402 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6403 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6404 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6405 _dummy_first_bfd_reloc_code_real },
40fb9820 6406 OPERAND_TYPE_NONE },
cff8d58a
L		 6407 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6408 _dummy_first_bfd_reloc_code_real },
40fb9820 6409 OPERAND_TYPE_NONE },
cff8d58a
L		 6410 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6411 BFD_RELOC_X86_64_GOT32 },
40fb9820 6412 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6413 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6414 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6415 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6416 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6417 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6418 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6419 };
6420 char *cp;
6421 unsigned int j;
6422
718ddfc0
JB		 6423 if (!IS_ELF)
6424 return NULL;
6425
f3c180ae 6426 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6427 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6428 return NULL;
6429
47465058 6430 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6431 {
cff8d58a 6432 int len = gotrel[j].len;
28f81592 6433 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6434 {
4fa24527 6435 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6436 {
28f81592
AM		 6437 int first, second;
6438 char *tmpbuf, *past_reloc;
f3c180ae 6439
91d6fa6a 6440 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6441 if (adjust)
6442 *adjust = len;
f3c180ae 6443
3956db08
JB		 6444 if (types)
6445 {
6446 if (flag_code != CODE_64BIT)
40fb9820
L		 6447 {
6448 types->bitfield.imm32 = 1;
6449 types->bitfield.disp32 = 1;
6450 }
3956db08
JB		 6451 else
6452 *types = gotrel[j].types64;
6453 }
6454
f3c180ae
AM		 6455 if (GOT_symbol == NULL)
6456 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6457
28f81592 6458 /* The length of the first part of our input line. */
f3c180ae 6459 first = cp - input_line_pointer;
28f81592
AM		 6460
6461 /* The second part goes from after the reloc token until
67c11a9b 6462 (and including) an end_of_line char or comma. */
28f81592 6463 past_reloc = cp + 1 + len;
67c11a9b
AM		 6464 cp = past_reloc;
6465 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6466 ++cp;
6467 second = cp + 1 - past_reloc;
28f81592
AM		 6468
6469 /* Allocate and copy string. The trailing NUL shouldn't
6470 be necessary, but be safe. */
1e9cc1c2 6471 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6472 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6473 if (second != 0 && *past_reloc != ' ')
6474 /* Replace the relocation token with ' ', so that
6475 errors like foo@GOTOFF1 will be detected. */
6476 tmpbuf[first++] = ' ';
6477 memcpy (tmpbuf + first, past_reloc, second);
6478 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6479 return tmpbuf;
6480 }
6481
4fa24527
JB		 6482 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6483 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6484 return NULL;
6485 }
6486 }
6487
6488 /* Might be a symbol version string. Don't as_bad here. */
6489 return NULL;
6490}
6491
f3c180ae 6492void
e3bb37b5 6493x86_cons (expressionS *exp, int size)
f3c180ae 6494{
ee86248c
JB		 6495 intel_syntax = -intel_syntax;
6496
3c7b9c2c 6497 exp->X_md = 0;
4fa24527 6498 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6499 {
6500 /* Handle @GOTOFF and the like in an expression. */
6501 char *save;
6502 char *gotfree_input_line;
6503 int adjust;
6504
6505 save = input_line_pointer;
3956db08 6506 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6507 if (gotfree_input_line)
6508 input_line_pointer = gotfree_input_line;
6509
6510 expression (exp);
6511
6512 if (gotfree_input_line)
6513 {
6514 /* expression () has merrily parsed up to the end of line,
6515 or a comma - in the wrong buffer. Transfer how far
6516 input_line_pointer has moved to the right buffer. */
6517 input_line_pointer = (save
6518 + (input_line_pointer - gotfree_input_line)
6519 + adjust);
6520 free (gotfree_input_line);
3992d3b7
AM		 6521 if (exp->X_op == O_constant
6522 || exp->X_op == O_absent
6523 || exp->X_op == O_illegal
0398aac5 6524 || exp->X_op == O_register
3992d3b7
AM		 6525 || exp->X_op == O_big)
6526 {
6527 char c = *input_line_pointer;
6528 *input_line_pointer = 0;
6529 as_bad (_("missing or invalid expression `%s'"), save);
6530 *input_line_pointer = c;
6531 }
f3c180ae
AM		 6532 }
6533 }
6534 else
6535 expression (exp);
ee86248c
JB		 6536
6537 intel_syntax = -intel_syntax;
6538
6539 if (intel_syntax)
6540 i386_intel_simplify (exp);
f3c180ae
AM		 6541}
6542#endif
6543
9f32dd5b
L		 6544static void
6545signed_cons (int size)
6482c264 6546{
d182319b
JB		 6547 if (flag_code == CODE_64BIT)
6548 cons_sign = 1;
6549 cons (size);
6550 cons_sign = -1;
6482c264
NC		 6551}
6552
d182319b 6553#ifdef TE_PE
6482c264
NC		 6554static void
6555pe_directive_secrel (dummy)
6556 int dummy ATTRIBUTE_UNUSED;
6557{
6558 expressionS exp;
6559
6560 do
6561 {
6562 expression (&exp);
6563 if (exp.X_op == O_symbol)
6564 exp.X_op = O_secrel;
6565
6566 emit_expr (&exp, 4);
6567 }
6568 while (*input_line_pointer++ == ',');
6569
6570 input_line_pointer--;
6571 demand_empty_rest_of_line ();
6572}
6482c264
NC		 6573#endif
6574
252b5132 6575static int
70e41ade 6576i386_immediate (char *imm_start)
252b5132
RH		 6577{
6578 char *save_input_line_pointer;
f3c180ae 6579 char *gotfree_input_line;
252b5132 6580 segT exp_seg = 0;
47926f60 6581 expressionS *exp;
40fb9820
L		 6582 i386_operand_type types;
6583
0dfbf9d7 6584 operand_type_set (&types, ~0);
252b5132
RH		 6585
6586 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6587 {
31b2323c
L		 6588 as_bad (_("at most %d immediate operands are allowed"),
6589 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6590 return 0;
6591 }
6592
6593 exp = &im_expressions[i.imm_operands++];
520dc8e8 6594 i.op[this_operand].imms = exp;
252b5132
RH		 6595
6596 if (is_space_char (*imm_start))
6597 ++imm_start;
6598
6599 save_input_line_pointer = input_line_pointer;
6600 input_line_pointer = imm_start;
6601
3956db08 6602 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6603 if (gotfree_input_line)
6604 input_line_pointer = gotfree_input_line;
252b5132
RH		 6605
6606 exp_seg = expression (exp);
6607
83183c0c 6608 SKIP_WHITESPACE ();
252b5132 6609 if (*input_line_pointer)
f3c180ae 6610 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6611
6612 input_line_pointer = save_input_line_pointer;
f3c180ae 6613 if (gotfree_input_line)
ee86248c
JB		 6614 {
6615 free (gotfree_input_line);
6616
6617 if (exp->X_op == O_constant || exp->X_op == O_register)
6618 exp->X_op = O_illegal;
6619 }
6620
6621 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6622}
252b5132 6623
ee86248c
JB		 6624static int
6625i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6626 i386_operand_type types, const char *imm_start)
6627{
6628 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6629 {
313c53d1
L		 6630 if (imm_start)
6631 as_bad (_("missing or invalid immediate expression `%s'"),
6632 imm_start);
3992d3b7 6633 return 0;
252b5132 6634 }
3e73aa7c 6635 else if (exp->X_op == O_constant)
252b5132 6636 {
47926f60 6637 /* Size it properly later. */
40fb9820 6638 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6639 /* If not 64bit, sign extend val. */
6640 if (flag_code != CODE_64BIT
4eed87de
AM		 6641 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6642 exp->X_add_number
6643 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6644 }
4c63da97 6645#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6646 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6647 && exp_seg != absolute_section
47926f60 6648 && exp_seg != text_section
24eab124
AM		 6649 && exp_seg != data_section
6650 && exp_seg != bss_section
6651 && exp_seg != undefined_section
f86103b7 6652 && !bfd_is_com_section (exp_seg))
252b5132 6653 {
d0b47220 6654 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6655 return 0;
6656 }
6657#endif
bb8f5920
L		 6658 else if (!intel_syntax && exp->X_op == O_register)
6659 {
313c53d1
L		 6660 if (imm_start)
6661 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6662 return 0;
6663 }
252b5132
RH		 6664 else
6665 {
6666 /* This is an address. The size of the address will be
24eab124 6667 determined later, depending on destination register,
3e73aa7c 6668 suffix, or the default for the section. */
40fb9820
L		 6669 i.types[this_operand].bitfield.imm8 = 1;
6670 i.types[this_operand].bitfield.imm16 = 1;
6671 i.types[this_operand].bitfield.imm32 = 1;
6672 i.types[this_operand].bitfield.imm32s = 1;
6673 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6674 i.types[this_operand] = operand_type_and (i.types[this_operand],
6675 types);
252b5132
RH		 6676 }
6677
6678 return 1;
6679}
6680
551c1ca1 6681static char *
e3bb37b5 6682i386_scale (char *scale)
252b5132 6683{
551c1ca1
AM		 6684 offsetT val;
6685 char *save = input_line_pointer;
252b5132 6686
551c1ca1
AM		 6687 input_line_pointer = scale;
6688 val = get_absolute_expression ();
6689
6690 switch (val)
252b5132 6691 {
551c1ca1 6692 case 1:
252b5132
RH		 6693 i.log2_scale_factor = 0;
6694 break;
551c1ca1 6695 case 2:
252b5132
RH		 6696 i.log2_scale_factor = 1;
6697 break;
551c1ca1 6698 case 4:
252b5132
RH		 6699 i.log2_scale_factor = 2;
6700 break;
551c1ca1 6701 case 8:
252b5132
RH		 6702 i.log2_scale_factor = 3;
6703 break;
6704 default:
a724f0f4
JB		 6705 {
6706 char sep = *input_line_pointer;
6707
6708 *input_line_pointer = '\0';
6709 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6710 scale);
6711 *input_line_pointer = sep;
6712 input_line_pointer = save;
6713 return NULL;
6714 }
252b5132 6715 }
29b0f896 6716 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6717 {
6718 as_warn (_("scale factor of %d without an index register"),
24eab124 6719 1 << i.log2_scale_factor);
252b5132 6720 i.log2_scale_factor = 0;
252b5132 6721 }
551c1ca1
AM		 6722 scale = input_line_pointer;
6723 input_line_pointer = save;
6724 return scale;
252b5132
RH		 6725}
6726
252b5132 6727static int
e3bb37b5 6728i386_displacement (char *disp_start, char *disp_end)
252b5132 6729{
29b0f896 6730 expressionS *exp;
252b5132
RH		 6731 segT exp_seg = 0;
6732 char *save_input_line_pointer;
f3c180ae 6733 char *gotfree_input_line;
40fb9820
L		 6734 int override;
6735 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6736 int ret;
252b5132 6737
31b2323c
L		 6738 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6739 {
6740 as_bad (_("at most %d displacement operands are allowed"),
6741 MAX_MEMORY_OPERANDS);
6742 return 0;
6743 }
6744
0dfbf9d7 6745 operand_type_set (&bigdisp, 0);
40fb9820
L		 6746 if ((i.types[this_operand].bitfield.jumpabsolute)
6747 || (!current_templates->start->opcode_modifier.jump
6748 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6749 {
40fb9820 6750 bigdisp.bitfield.disp32 = 1;
e05278af 6751 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6752 if (flag_code == CODE_64BIT)
6753 {
6754 if (!override)
6755 {
6756 bigdisp.bitfield.disp32s = 1;
6757 bigdisp.bitfield.disp64 = 1;
6758 }
6759 }
6760 else if ((flag_code == CODE_16BIT) ^ override)
6761 {
6762 bigdisp.bitfield.disp32 = 0;
6763 bigdisp.bitfield.disp16 = 1;
6764 }
e05278af
JB		 6765 }
6766 else
6767 {
6768 /* For PC-relative branches, the width of the displacement
6769 is dependent upon data size, not address size. */
e05278af 6770 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6771 if (flag_code == CODE_64BIT)
6772 {
6773 if (override || i.suffix == WORD_MNEM_SUFFIX)
6774 bigdisp.bitfield.disp16 = 1;
6775 else
6776 {
6777 bigdisp.bitfield.disp32 = 1;
6778 bigdisp.bitfield.disp32s = 1;
6779 }
6780 }
6781 else
e05278af
JB		 6782 {
6783 if (!override)
6784 override = (i.suffix == (flag_code != CODE_16BIT
6785 ? WORD_MNEM_SUFFIX
6786 : LONG_MNEM_SUFFIX));
40fb9820
L		 6787 bigdisp.bitfield.disp32 = 1;
6788 if ((flag_code == CODE_16BIT) ^ override)
6789 {
6790 bigdisp.bitfield.disp32 = 0;
6791 bigdisp.bitfield.disp16 = 1;
6792 }
e05278af 6793 }
e05278af 6794 }
c6fb90c8
L		 6795 i.types[this_operand] = operand_type_or (i.types[this_operand],
6796 bigdisp);
252b5132
RH		 6797
6798 exp = &disp_expressions[i.disp_operands];
520dc8e8 6799 i.op[this_operand].disps = exp;
252b5132
RH		 6800 i.disp_operands++;
6801 save_input_line_pointer = input_line_pointer;
6802 input_line_pointer = disp_start;
6803 END_STRING_AND_SAVE (disp_end);
6804
6805#ifndef GCC_ASM_O_HACK
6806#define GCC_ASM_O_HACK 0
6807#endif
6808#if GCC_ASM_O_HACK
6809 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6810 if (i.types[this_operand].bitfield.baseIndex
24eab124 6811 && displacement_string_end[-1] == '+')
252b5132
RH		 6812 {
6813 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6814 constraint within gcc asm statements.
6815 For instance:
6816
6817 #define _set_tssldt_desc(n,addr,limit,type) \
6818 __asm__ __volatile__ ( \
6819 "movw %w2,%0\n\t" \
6820 "movw %w1,2+%0\n\t" \
6821 "rorl $16,%1\n\t" \
6822 "movb %b1,4+%0\n\t" \
6823 "movb %4,5+%0\n\t" \
6824 "movb $0,6+%0\n\t" \
6825 "movb %h1,7+%0\n\t" \
6826 "rorl $16,%1" \
6827 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6828
6829 This works great except that the output assembler ends
6830 up looking a bit weird if it turns out that there is
6831 no offset. You end up producing code that looks like:
6832
6833 #APP
6834 movw $235,(%eax)
6835 movw %dx,2+(%eax)
6836 rorl $16,%edx
6837 movb %dl,4+(%eax)
6838 movb $137,5+(%eax)
6839 movb $0,6+(%eax)
6840 movb %dh,7+(%eax)
6841 rorl $16,%edx
6842 #NO_APP
6843
47926f60 6844 So here we provide the missing zero. */
24eab124
AM		 6845
6846 *displacement_string_end = '0';
252b5132
RH		 6847 }
6848#endif
3956db08 6849 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6850 if (gotfree_input_line)
6851 input_line_pointer = gotfree_input_line;
252b5132 6852
24eab124 6853 exp_seg = expression (exp);
252b5132 6854
636c26b0
AM		 6855 SKIP_WHITESPACE ();
6856 if (*input_line_pointer)
6857 as_bad (_("junk `%s' after expression"), input_line_pointer);
6858#if GCC_ASM_O_HACK
6859 RESTORE_END_STRING (disp_end + 1);
6860#endif
636c26b0 6861 input_line_pointer = save_input_line_pointer;
636c26b0 6862 if (gotfree_input_line)
ee86248c
JB		 6863 {
6864 free (gotfree_input_line);
6865
6866 if (exp->X_op == O_constant || exp->X_op == O_register)
6867 exp->X_op = O_illegal;
6868 }
6869
6870 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6871
6872 RESTORE_END_STRING (disp_end);
6873
6874 return ret;
6875}
6876
6877static int
6878i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6879 i386_operand_type types, const char *disp_start)
6880{
6881 i386_operand_type bigdisp;
6882 int ret = 1;
636c26b0 6883
24eab124
AM		 6884 /* We do this to make sure that the section symbol is in
6885 the symbol table. We will ultimately change the relocation
47926f60 6886 to be relative to the beginning of the section. */
1ae12ab7 6887 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6888 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6889 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6890 {
636c26b0 6891 if (exp->X_op != O_symbol)
3992d3b7 6892 goto inv_disp;
636c26b0 6893
e5cb08ac 6894 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 6895 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
6896 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 6897 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6898 exp->X_op = O_subtract;
6899 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6900 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6901 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6902 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6903 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6904 else
29b0f896 6905 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6906 }
252b5132 6907
3992d3b7
AM		 6908 else if (exp->X_op == O_absent
6909 || exp->X_op == O_illegal
ee86248c 6910 || exp->X_op == O_big)
2daf4fd8 6911 {
3992d3b7
AM		 6912 inv_disp:
6913 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6914 disp_start);
3992d3b7 6915 ret = 0;
2daf4fd8
AM		 6916 }
6917
0e1147d9
L		 6918 else if (flag_code == CODE_64BIT
6919 && !i.prefix[ADDR_PREFIX]
6920 && exp->X_op == O_constant)
6921 {
6922 /* Since displacement is signed extended to 64bit, don't allow
6923 disp32 and turn off disp32s if they are out of range. */
6924 i.types[this_operand].bitfield.disp32 = 0;
6925 if (!fits_in_signed_long (exp->X_add_number))
6926 {
6927 i.types[this_operand].bitfield.disp32s = 0;
6928 if (i.types[this_operand].bitfield.baseindex)
6929 {
6930 as_bad (_("0x%lx out range of signed 32bit displacement"),
6931 (long) exp->X_add_number);
6932 ret = 0;
6933 }
6934 }
6935 }
6936
4c63da97 6937#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6938 else if (exp->X_op != O_constant
6939 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6940 && exp_seg != absolute_section
6941 && exp_seg != text_section
6942 && exp_seg != data_section
6943 && exp_seg != bss_section
6944 && exp_seg != undefined_section
6945 && !bfd_is_com_section (exp_seg))
24eab124 6946 {
d0b47220 6947 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6948 ret = 0;
24eab124 6949 }
252b5132 6950#endif
3956db08 6951
40fb9820
L		 6952 /* Check if this is a displacement only operand. */
6953 bigdisp = i.types[this_operand];
6954 bigdisp.bitfield.disp8 = 0;
6955 bigdisp.bitfield.disp16 = 0;
6956 bigdisp.bitfield.disp32 = 0;
6957 bigdisp.bitfield.disp32s = 0;
6958 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6959 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6960 i.types[this_operand] = operand_type_and (i.types[this_operand],
6961 types);
3956db08 6962
3992d3b7 6963 return ret;
252b5132
RH		 6964}
6965
eecb386c 6966/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6967 Return 1 on success, 0 on a failure. */
6968
252b5132 6969static int
e3bb37b5 6970i386_index_check (const char *operand_string)
252b5132 6971{
3e73aa7c 6972 int ok;
fc0763e6 6973 const char *kind = "base/index";
24eab124 6974#if INFER_ADDR_PREFIX
eecb386c
AM		 6975 int fudged = 0;
6976
24eab124
AM		 6977 tryprefix:
6978#endif
3e73aa7c 6979 ok = 1;
fc0763e6
JB		 6980 if (current_templates->start->opcode_modifier.isstring
6981 && !current_templates->start->opcode_modifier.immext
6982 && (current_templates->end[-1].opcode_modifier.isstring
6983 || i.mem_operands))
6984 {
6985 /* Memory operands of string insns are special in that they only allow
6986 a single register (rDI, rSI, or rBX) as their memory address. */
6987 unsigned int expected;
6988
6989 kind = "string address";
6990
6991 if (current_templates->start->opcode_modifier.w)
6992 {
6993 i386_operand_type type = current_templates->end[-1].operand_types[0];
6994
6995 if (!type.bitfield.baseindex
6996 || ((!i.mem_operands != !intel_syntax)
6997 && current_templates->end[-1].operand_types[1]
6998 .bitfield.baseindex))
6999 type = current_templates->end[-1].operand_types[1];
7000 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7001 }
7002 else
7003 expected = 3 /* rBX */;
7004
7005 if (!i.base_reg || i.index_reg
7006 || operand_type_check (i.types[this_operand], disp))
7007 ok = -1;
7008 else if (!(flag_code == CODE_64BIT
7009 ? i.prefix[ADDR_PREFIX]
7010 ? i.base_reg->reg_type.bitfield.reg32
7011 : i.base_reg->reg_type.bitfield.reg64
7012 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7013 ? i.base_reg->reg_type.bitfield.reg32
7014 : i.base_reg->reg_type.bitfield.reg16))
7015 ok = 0;
7016 else if (i.base_reg->reg_num != expected)
7017 ok = -1;
7018
7019 if (ok < 0)
7020 {
7021 unsigned int j;
7022
7023 for (j = 0; j < i386_regtab_size; ++j)
7024 if ((flag_code == CODE_64BIT
7025 ? i.prefix[ADDR_PREFIX]
7026 ? i386_regtab[j].reg_type.bitfield.reg32
7027 : i386_regtab[j].reg_type.bitfield.reg64
7028 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7029 ? i386_regtab[j].reg_type.bitfield.reg32
7030 : i386_regtab[j].reg_type.bitfield.reg16)
7031 && i386_regtab[j].reg_num == expected)
7032 break;
9c2799c2 7033 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7034 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7035 operand_string,
7036 intel_syntax ? '[' : '(',
7037 register_prefix,
7038 i386_regtab[j].reg_name,
7039 intel_syntax ? ']' : ')');
7040 ok = 1;
7041 }
7042 }
7043 else if (flag_code == CODE_64BIT)
64e74474 7044 {
64e74474 7045 if ((i.base_reg
40fb9820
L		 7046 && ((i.prefix[ADDR_PREFIX] == 0
7047 && !i.base_reg->reg_type.bitfield.reg64)
7048 || (i.prefix[ADDR_PREFIX]
7049 && !i.base_reg->reg_type.bitfield.reg32))
7050 && (i.index_reg
9a04903e
JB		 7051 || i.base_reg->reg_num !=
7052 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7053 || (i.index_reg
40fb9820
L		 7054 && (!i.index_reg->reg_type.bitfield.baseindex
7055 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7056 && i.index_reg->reg_num != RegRiz
7057 && !i.index_reg->reg_type.bitfield.reg64
7058 )
40fb9820 7059 || (i.prefix[ADDR_PREFIX]
db51cc60 7060 && i.index_reg->reg_num != RegEiz
40fb9820 7061 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7062 ok = 0;
3e73aa7c
JH		 7063 }
7064 else
7065 {
7066 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7067 {
7068 /* 16bit checks. */
7069 if ((i.base_reg
40fb9820
L		 7070 && (!i.base_reg->reg_type.bitfield.reg16
7071 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7072 || (i.index_reg
40fb9820
L		 7073 && (!i.index_reg->reg_type.bitfield.reg16
7074 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7075 || !(i.base_reg
7076 && i.base_reg->reg_num < 6
7077 && i.index_reg->reg_num >= 6
7078 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7079 ok = 0;
7080 }
7081 else
e5cb08ac 7082 {
3e73aa7c
JH		 7083 /* 32bit checks. */
7084 if ((i.base_reg
40fb9820 7085 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7086 || (i.index_reg
db51cc60
L		 7087 && ((!i.index_reg->reg_type.bitfield.reg32
7088 && i.index_reg->reg_num != RegEiz)
40fb9820 7089 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7090 ok = 0;
3e73aa7c
JH		 7091 }
7092 }
7093 if (!ok)
24eab124
AM		 7094 {
7095#if INFER_ADDR_PREFIX
fc0763e6 7096 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7097 {
7098 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7099 i.prefixes += 1;
b23bac36
AM		 7100 /* Change the size of any displacement too. At most one of
7101 Disp16 or Disp32 is set.
7102 FIXME. There doesn't seem to be any real need for separate
7103 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7104 Removing them would probably clean up the code quite a lot. */
4eed87de 7105 if (flag_code != CODE_64BIT
40fb9820
L		 7106 && (i.types[this_operand].bitfield.disp16
7107 || i.types[this_operand].bitfield.disp32))
7108 i.types[this_operand]
c6fb90c8 7109 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7110 fudged = 1;
24eab124
AM		 7111 goto tryprefix;
7112 }
eecb386c 7113 if (fudged)
fc0763e6
JB		 7114 as_bad (_("`%s' is not a valid %s expression"),
7115 operand_string,
7116 kind);
eecb386c 7117 else
c388dee8 7118#endif
fc0763e6 7119 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7120 operand_string,
fc0763e6
JB		 7121 flag_code_names[i.prefix[ADDR_PREFIX]
7122 ? flag_code == CODE_32BIT
7123 ? CODE_16BIT
7124 : CODE_32BIT
7125 : flag_code],
7126 kind);
24eab124 7127 }
20f0a1fc 7128 return ok;
24eab124 7129}
252b5132 7130
fc0763e6 7131/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7132 on error. */
252b5132 7133
252b5132 7134static int
a7619375 7135i386_att_operand (char *operand_string)
252b5132 7136{
af6bdddf
AM		 7137 const reg_entry *r;
7138 char *end_op;
24eab124 7139 char *op_string = operand_string;
252b5132 7140
24eab124 7141 if (is_space_char (*op_string))
252b5132
RH		 7142 ++op_string;
7143
24eab124 7144 /* We check for an absolute prefix (differentiating,
47926f60 7145 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7146 if (*op_string == ABSOLUTE_PREFIX)
7147 {
7148 ++op_string;
7149 if (is_space_char (*op_string))
7150 ++op_string;
40fb9820 7151 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7152 }
252b5132 7153
47926f60 7154 /* Check if operand is a register. */
4d1bb795 7155 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7156 {
40fb9820
L		 7157 i386_operand_type temp;
7158
24eab124
AM		 7159 /* Check for a segment override by searching for ':' after a
7160 segment register. */
7161 op_string = end_op;
7162 if (is_space_char (*op_string))
7163 ++op_string;
40fb9820
L		 7164 if (*op_string == ':'
7165 && (r->reg_type.bitfield.sreg2
7166 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7167 {
7168 switch (r->reg_num)
7169 {
7170 case 0:
7171 i.seg[i.mem_operands] = &es;
7172 break;
7173 case 1:
7174 i.seg[i.mem_operands] = &cs;
7175 break;
7176 case 2:
7177 i.seg[i.mem_operands] = &ss;
7178 break;
7179 case 3:
7180 i.seg[i.mem_operands] = &ds;
7181 break;
7182 case 4:
7183 i.seg[i.mem_operands] = &fs;
7184 break;
7185 case 5:
7186 i.seg[i.mem_operands] = &gs;
7187 break;
7188 }
252b5132 7189
24eab124 7190 /* Skip the ':' and whitespace. */
252b5132
RH		 7191 ++op_string;
7192 if (is_space_char (*op_string))
24eab124 7193 ++op_string;
252b5132 7194
24eab124
AM		 7195 if (!is_digit_char (*op_string)
7196 && !is_identifier_char (*op_string)
7197 && *op_string != '('
7198 && *op_string != ABSOLUTE_PREFIX)
7199 {
7200 as_bad (_("bad memory operand `%s'"), op_string);
7201 return 0;
7202 }
47926f60 7203 /* Handle case of %es:*foo. */
24eab124
AM		 7204 if (*op_string == ABSOLUTE_PREFIX)
7205 {
7206 ++op_string;
7207 if (is_space_char (*op_string))
7208 ++op_string;
40fb9820 7209 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7210 }
7211 goto do_memory_reference;
7212 }
7213 if (*op_string)
7214 {
d0b47220 7215 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7216 return 0;
7217 }
40fb9820
L		 7218 temp = r->reg_type;
7219 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7220 i.types[this_operand] = operand_type_or (i.types[this_operand],
7221 temp);
7d5e4556 7222 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7223 i.op[this_operand].regs = r;
24eab124
AM		 7224 i.reg_operands++;
7225 }
af6bdddf
AM		 7226 else if (*op_string == REGISTER_PREFIX)
7227 {
7228 as_bad (_("bad register name `%s'"), op_string);
7229 return 0;
7230 }
24eab124 7231 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7232 {
24eab124 7233 ++op_string;
40fb9820 7234 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7235 {
d0b47220 7236 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7237 return 0;
7238 }
7239 if (!i386_immediate (op_string))
7240 return 0;
7241 }
7242 else if (is_digit_char (*op_string)
7243 || is_identifier_char (*op_string)
e5cb08ac 7244 || *op_string == '(')
24eab124 7245 {
47926f60 7246 /* This is a memory reference of some sort. */
af6bdddf 7247 char *base_string;
252b5132 7248
47926f60 7249 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7250 char *displacement_string_start;
7251 char *displacement_string_end;
252b5132 7252
24eab124 7253 do_memory_reference:
24eab124 7254 if ((i.mem_operands == 1
40fb9820 7255 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7256 || i.mem_operands == 2)
7257 {
7258 as_bad (_("too many memory references for `%s'"),
7259 current_templates->start->name);
7260 return 0;
7261 }
252b5132 7262
24eab124
AM		 7263 /* Check for base index form. We detect the base index form by
7264 looking for an ')' at the end of the operand, searching
7265 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7266 after the '('. */
af6bdddf 7267 base_string = op_string + strlen (op_string);
c3332e24 7268
af6bdddf
AM		 7269 --base_string;
7270 if (is_space_char (*base_string))
7271 --base_string;
252b5132 7272
47926f60 7273 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7274 displacement_string_start = op_string;
7275 displacement_string_end = base_string + 1;
252b5132 7276
24eab124
AM		 7277 if (*base_string == ')')
7278 {
af6bdddf 7279 char *temp_string;
24eab124
AM		 7280 unsigned int parens_balanced = 1;
7281 /* We've already checked that the number of left & right ()'s are
47926f60 7282 equal, so this loop will not be infinite. */
24eab124
AM		 7283 do
7284 {
7285 base_string--;
7286 if (*base_string == ')')
7287 parens_balanced++;
7288 if (*base_string == '(')
7289 parens_balanced--;
7290 }
7291 while (parens_balanced);
c3332e24 7292
af6bdddf 7293 temp_string = base_string;
c3332e24 7294
24eab124 7295 /* Skip past '(' and whitespace. */
252b5132
RH		 7296 ++base_string;
7297 if (is_space_char (*base_string))
24eab124 7298 ++base_string;
252b5132 7299
af6bdddf 7300 if (*base_string == ','
4eed87de
AM		 7301 || ((i.base_reg = parse_register (base_string, &end_op))
7302 != NULL))
252b5132 7303 {
af6bdddf 7304 displacement_string_end = temp_string;
252b5132 7305
40fb9820 7306 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7307
af6bdddf 7308 if (i.base_reg)
24eab124 7309 {
24eab124
AM		 7310 base_string = end_op;
7311 if (is_space_char (*base_string))
7312 ++base_string;
af6bdddf
AM		 7313 }
7314
7315 /* There may be an index reg or scale factor here. */
7316 if (*base_string == ',')
7317 {
7318 ++base_string;
7319 if (is_space_char (*base_string))
7320 ++base_string;
7321
4eed87de
AM		 7322 if ((i.index_reg = parse_register (base_string, &end_op))
7323 != NULL)
24eab124 7324 {
af6bdddf 7325 base_string = end_op;
24eab124
AM		 7326 if (is_space_char (*base_string))
7327 ++base_string;
af6bdddf
AM		 7328 if (*base_string == ',')
7329 {
7330 ++base_string;
7331 if (is_space_char (*base_string))
7332 ++base_string;
7333 }
e5cb08ac 7334 else if (*base_string != ')')
af6bdddf 7335 {
4eed87de
AM		 7336 as_bad (_("expecting `,' or `)' "
7337 "after index register in `%s'"),
af6bdddf
AM		 7338 operand_string);
7339 return 0;
7340 }
24eab124 7341 }
af6bdddf 7342 else if (*base_string == REGISTER_PREFIX)
24eab124 7343 {
af6bdddf 7344 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7345 return 0;
7346 }
252b5132 7347
47926f60 7348 /* Check for scale factor. */
551c1ca1 7349 if (*base_string != ')')
af6bdddf 7350 {
551c1ca1
AM		 7351 char *end_scale = i386_scale (base_string);
7352
7353 if (!end_scale)
af6bdddf 7354 return 0;
24eab124 7355
551c1ca1 7356 base_string = end_scale;
af6bdddf
AM		 7357 if (is_space_char (*base_string))
7358 ++base_string;
7359 if (*base_string != ')')
7360 {
4eed87de
AM		 7361 as_bad (_("expecting `)' "
7362 "after scale factor in `%s'"),
af6bdddf
AM		 7363 operand_string);
7364 return 0;
7365 }
7366 }
7367 else if (!i.index_reg)
24eab124 7368 {
4eed87de
AM		 7369 as_bad (_("expecting index register or scale factor "
7370 "after `,'; got '%c'"),
af6bdddf 7371 *base_string);
24eab124
AM		 7372 return 0;
7373 }
7374 }
af6bdddf 7375 else if (*base_string != ')')
24eab124 7376 {
4eed87de
AM		 7377 as_bad (_("expecting `,' or `)' "
7378 "after base register in `%s'"),
af6bdddf 7379 operand_string);
24eab124
AM		 7380 return 0;
7381 }
c3332e24 7382 }
af6bdddf 7383 else if (*base_string == REGISTER_PREFIX)
c3332e24 7384 {
af6bdddf 7385 as_bad (_("bad register name `%s'"), base_string);
24eab124 7386 return 0;
c3332e24 7387 }
24eab124
AM		 7388 }
7389
7390 /* If there's an expression beginning the operand, parse it,
7391 assuming displacement_string_start and
7392 displacement_string_end are meaningful. */
7393 if (displacement_string_start != displacement_string_end)
7394 {
7395 if (!i386_displacement (displacement_string_start,
7396 displacement_string_end))
7397 return 0;
7398 }
7399
7400 /* Special case for (%dx) while doing input/output op. */
7401 if (i.base_reg
0dfbf9d7
L		 7402 && operand_type_equal (&i.base_reg->reg_type,
7403 &reg16_inoutportreg)
24eab124
AM		 7404 && i.index_reg == 0
7405 && i.log2_scale_factor == 0
7406 && i.seg[i.mem_operands] == 0
40fb9820 7407 && !operand_type_check (i.types[this_operand], disp))
24eab124 7408 {
65da13b5 7409 i.types[this_operand] = inoutportreg;
24eab124
AM		 7410 return 1;
7411 }
7412
eecb386c
AM		 7413 if (i386_index_check (operand_string) == 0)
7414 return 0;
5c07affc 7415 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7416 i.mem_operands++;
7417 }
7418 else
ce8a8b2f
AM		 7419 {
7420 /* It's not a memory operand; argh! */
24eab124
AM		 7421 as_bad (_("invalid char %s beginning operand %d `%s'"),
7422 output_invalid (*op_string),
7423 this_operand + 1,
7424 op_string);
7425 return 0;
7426 }
47926f60 7427 return 1; /* Normal return. */
252b5132
RH		 7428}
7429\f
ee7fcc42
AM		 7430/* md_estimate_size_before_relax()
7431
7432 Called just before relax() for rs_machine_dependent frags. The x86
7433 assembler uses these frags to handle variable size jump
7434 instructions.
7435
7436 Any symbol that is now undefined will not become defined.
7437 Return the correct fr_subtype in the frag.
7438 Return the initial "guess for variable size of frag" to caller.
7439 The guess is actually the growth beyond the fixed part. Whatever
7440 we do to grow the fixed or variable part contributes to our
7441 returned value. */
7442
252b5132
RH		 7443int
7444md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7445 fragS *fragP;
7446 segT segment;
252b5132 7447{
252b5132 7448 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7449 check for un-relaxable symbols. On an ELF system, we can't relax
7450 an externally visible symbol, because it may be overridden by a
7451 shared library. */
7452 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7453#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7454 || (IS_ELF
31312f95 7455 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7456 || S_IS_WEAK (fragP->fr_symbol)
7457 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7458 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7459#endif
7460#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7461 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7462 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7463#endif
7464 )
252b5132 7465 {
b98ef147
AM		 7466 /* Symbol is undefined in this segment, or we need to keep a
7467 reloc so that weak symbols can be overridden. */
7468 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7469 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7470 unsigned char *opcode;
7471 int old_fr_fix;
f6af82bd 7472
ee7fcc42 7473 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7474 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7475 else if (size == 2)
f6af82bd
AM		 7476 reloc_type = BFD_RELOC_16_PCREL;
7477 else
7478 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7479
ee7fcc42
AM		 7480 old_fr_fix = fragP->fr_fix;
7481 opcode = (unsigned char *) fragP->fr_opcode;
7482
fddf5b5b 7483 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7484 {
fddf5b5b
AM		 7485 case UNCOND_JUMP:
7486 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7487 opcode[0] = 0xe9;
252b5132 7488 fragP->fr_fix += size;
062cd5e7
AS		 7489 fix_new (fragP, old_fr_fix, size,
7490 fragP->fr_symbol,
7491 fragP->fr_offset, 1,
7492 reloc_type);
252b5132
RH		 7493 break;
7494
fddf5b5b 7495 case COND_JUMP86:
412167cb
AM		 7496 if (size == 2
7497 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7498 {
7499 /* Negate the condition, and branch past an
7500 unconditional jump. */
7501 opcode[0] ^= 1;
7502 opcode[1] = 3;
7503 /* Insert an unconditional jump. */
7504 opcode[2] = 0xe9;
7505 /* We added two extra opcode bytes, and have a two byte
7506 offset. */
7507 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7508 fix_new (fragP, old_fr_fix + 2, 2,
7509 fragP->fr_symbol,
7510 fragP->fr_offset, 1,
7511 reloc_type);
fddf5b5b
AM		 7512 break;
7513 }
7514 /* Fall through. */
7515
7516 case COND_JUMP:
412167cb
AM		 7517 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7518 {
3e02c1cc
AM		 7519 fixS *fixP;
7520
412167cb 7521 fragP->fr_fix += 1;
3e02c1cc
AM		 7522 fixP = fix_new (fragP, old_fr_fix, 1,
7523 fragP->fr_symbol,
7524 fragP->fr_offset, 1,
7525 BFD_RELOC_8_PCREL);
7526 fixP->fx_signed = 1;
412167cb
AM		 7527 break;
7528 }
93c2a809 7529
24eab124 7530 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7531 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7532 opcode[1] = opcode[0] + 0x10;
f6af82bd 7533 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7534 /* We've added an opcode byte. */
7535 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7536 fix_new (fragP, old_fr_fix + 1, size,
7537 fragP->fr_symbol,
7538 fragP->fr_offset, 1,
7539 reloc_type);
252b5132 7540 break;
fddf5b5b
AM		 7541
7542 default:
7543 BAD_CASE (fragP->fr_subtype);
7544 break;
252b5132
RH		 7545 }
7546 frag_wane (fragP);
ee7fcc42 7547 return fragP->fr_fix - old_fr_fix;
252b5132 7548 }
93c2a809 7549
93c2a809
AM		 7550 /* Guess size depending on current relax state. Initially the relax
7551 state will correspond to a short jump and we return 1, because
7552 the variable part of the frag (the branch offset) is one byte
7553 long. However, we can relax a section more than once and in that
7554 case we must either set fr_subtype back to the unrelaxed state,
7555 or return the value for the appropriate branch. */
7556 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7557}
7558
47926f60
KH		 7559/* Called after relax() is finished.
7560
7561 In: Address of frag.
7562 fr_type == rs_machine_dependent.
7563 fr_subtype is what the address relaxed to.
7564
7565 Out: Any fixSs and constants are set up.
7566 Caller will turn frag into a ".space 0". */
7567
252b5132
RH		 7568void
7569md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7570 bfd *abfd ATTRIBUTE_UNUSED;
7571 segT sec ATTRIBUTE_UNUSED;
29b0f896 7572 fragS *fragP;
252b5132 7573{
29b0f896 7574 unsigned char *opcode;
252b5132 7575 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7576 offsetT target_address;
7577 offsetT opcode_address;
252b5132 7578 unsigned int extension = 0;
847f7ad4 7579 offsetT displacement_from_opcode_start;
252b5132
RH		 7580
7581 opcode = (unsigned char *) fragP->fr_opcode;
7582
47926f60 7583 /* Address we want to reach in file space. */
252b5132 7584 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7585
47926f60 7586 /* Address opcode resides at in file space. */
252b5132
RH		 7587 opcode_address = fragP->fr_address + fragP->fr_fix;
7588
47926f60 7589 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7590 displacement_from_opcode_start = target_address - opcode_address;
7591
fddf5b5b 7592 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7593 {
47926f60
KH		 7594 /* Don't have to change opcode. */
7595 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7596 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7597 }
7598 else
7599 {
7600 if (no_cond_jump_promotion
7601 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7602 as_warn_where (fragP->fr_file, fragP->fr_line,
7603 _("long jump required"));
252b5132 7604
fddf5b5b
AM		 7605 switch (fragP->fr_subtype)
7606 {
7607 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7608 extension = 4; /* 1 opcode + 4 displacement */
7609 opcode[0] = 0xe9;
7610 where_to_put_displacement = &opcode[1];
7611 break;
252b5132 7612
fddf5b5b
AM		 7613 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7614 extension = 2; /* 1 opcode + 2 displacement */
7615 opcode[0] = 0xe9;
7616 where_to_put_displacement = &opcode[1];
7617 break;
252b5132 7618
fddf5b5b
AM		 7619 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7620 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7621 extension = 5; /* 2 opcode + 4 displacement */
7622 opcode[1] = opcode[0] + 0x10;
7623 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7624 where_to_put_displacement = &opcode[2];
7625 break;
252b5132 7626
fddf5b5b
AM		 7627 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7628 extension = 3; /* 2 opcode + 2 displacement */
7629 opcode[1] = opcode[0] + 0x10;
7630 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7631 where_to_put_displacement = &opcode[2];
7632 break;
252b5132 7633
fddf5b5b
AM		 7634 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7635 extension = 4;
7636 opcode[0] ^= 1;
7637 opcode[1] = 3;
7638 opcode[2] = 0xe9;
7639 where_to_put_displacement = &opcode[3];
7640 break;
7641
7642 default:
7643 BAD_CASE (fragP->fr_subtype);
7644 break;
7645 }
252b5132 7646 }
fddf5b5b 7647
7b81dfbb
AJ		 7648 /* If size if less then four we are sure that the operand fits,
7649 but if it's 4, then it could be that the displacement is larger
7650 then -/+ 2GB. */
7651 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7652 && object_64bit
7653 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7654 + ((addressT) 1 << 31))
7655 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7656 {
7657 as_bad_where (fragP->fr_file, fragP->fr_line,
7658 _("jump target out of range"));
7659 /* Make us emit 0. */
7660 displacement_from_opcode_start = extension;
7661 }
47926f60 7662 /* Now put displacement after opcode. */
252b5132
RH		 7663 md_number_to_chars ((char *) where_to_put_displacement,
7664 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7665 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7666 fragP->fr_fix += extension;
7667}
7668\f
252b5132
RH		 7669/* Apply a fixup (fixS) to segment data, once it has been determined
7670 by our caller that we have all the info we need to fix it up.
7671
7672 On the 386, immediates, displacements, and data pointers are all in
7673 the same (little-endian) format, so we don't need to care about which
7674 we are handling. */
7675
94f592af 7676void
55cf6793 7677md_apply_fix (fixP, valP, seg)
47926f60
KH		 7678 /* The fix we're to put in. */
7679 fixS *fixP;
47926f60 7680 /* Pointer to the value of the bits. */
c6682705 7681 valueT *valP;
47926f60
KH		 7682 /* Segment fix is from. */
7683 segT seg ATTRIBUTE_UNUSED;
252b5132 7684{
94f592af 7685 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7686 valueT value = *valP;
252b5132 7687
f86103b7 7688#if !defined (TE_Mach)
93382f6d
AM		 7689 if (fixP->fx_pcrel)
7690 {
7691 switch (fixP->fx_r_type)
7692 {
5865bb77
ILT		 7693 default:
7694 break;
7695
d6ab8113
JB		 7696 case BFD_RELOC_64:
7697 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7698 break;
93382f6d 7699 case BFD_RELOC_32:
ae8887b5 7700 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7701 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7702 break;
7703 case BFD_RELOC_16:
7704 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7705 break;
7706 case BFD_RELOC_8:
7707 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7708 break;
7709 }
7710 }
252b5132 7711
a161fe53 7712 if (fixP->fx_addsy != NULL
31312f95 7713 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7714 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7715 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7716 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7717 && !use_rela_relocations)
252b5132 7718 {
31312f95
AM		 7719 /* This is a hack. There should be a better way to handle this.
7720 This covers for the fact that bfd_install_relocation will
7721 subtract the current location (for partial_inplace, PC relative
7722 relocations); see more below. */
252b5132 7723#ifndef OBJ_AOUT
718ddfc0 7724 if (IS_ELF
252b5132
RH		 7725#ifdef TE_PE
7726 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7727#endif
7728 )
7729 value += fixP->fx_where + fixP->fx_frag->fr_address;
7730#endif
7731#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7732 if (IS_ELF)
252b5132 7733 {
6539b54b 7734 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7735
6539b54b 7736 if ((sym_seg == seg
2f66722d 7737 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7738 && sym_seg != absolute_section))
af65af87 7739 && !generic_force_reloc (fixP))
2f66722d
AM		 7740 {
7741 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7742 bfd_install_relocation subtracts them out again. I think
7743 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7744 it. FIXME. */
7745 value += fixP->fx_where + fixP->fx_frag->fr_address;
7746 }
252b5132
RH		 7747 }
7748#endif
7749#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7750 /* For some reason, the PE format does not store a
7751 section address offset for a PC relative symbol. */
7752 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7753 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7754 value += md_pcrel_from (fixP);
7755#endif
7756 }
fbeb56a4
DK		 7757#if defined (OBJ_COFF) && defined (TE_PE)
7758 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7759 {
7760 value -= S_GET_VALUE (fixP->fx_addsy);
7761 }
7762#endif
252b5132
RH		 7763
7764 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7765 and we must not disappoint it. */
252b5132 7766#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7767 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7768 switch (fixP->fx_r_type)
7769 {
7770 case BFD_RELOC_386_PLT32:
3e73aa7c 7771 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7772 /* Make the jump instruction point to the address of the operand. At
7773 runtime we merely add the offset to the actual PLT entry. */
7774 value = -4;
7775 break;
31312f95 7776
13ae64f3
JJ		 7777 case BFD_RELOC_386_TLS_GD:
7778 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7779 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7780 case BFD_RELOC_386_TLS_IE:
7781 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7782 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7783 case BFD_RELOC_X86_64_TLSGD:
7784 case BFD_RELOC_X86_64_TLSLD:
7785 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7786 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7787 value = 0; /* Fully resolved at runtime. No addend. */
7788 /* Fallthrough */
7789 case BFD_RELOC_386_TLS_LE:
7790 case BFD_RELOC_386_TLS_LDO_32:
7791 case BFD_RELOC_386_TLS_LE_32:
7792 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7793 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7794 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7795 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7796 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7797 break;
7798
67a4f2b7
AO		 7799 case BFD_RELOC_386_TLS_DESC_CALL:
7800 case BFD_RELOC_X86_64_TLSDESC_CALL:
7801 value = 0; /* Fully resolved at runtime. No addend. */
7802 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7803 fixP->fx_done = 0;
7804 return;
7805
00f7efb6
JJ		 7806 case BFD_RELOC_386_GOT32:
7807 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7808 value = 0; /* Fully resolved at runtime. No addend. */
7809 break;
47926f60
KH		 7810
7811 case BFD_RELOC_VTABLE_INHERIT:
7812 case BFD_RELOC_VTABLE_ENTRY:
7813 fixP->fx_done = 0;
94f592af 7814 return;
47926f60
KH		 7815
7816 default:
7817 break;
7818 }
7819#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7820 *valP = value;
f86103b7 7821#endif /* !defined (TE_Mach) */
3e73aa7c 7822
3e73aa7c 7823 /* Are we finished with this relocation now? */
c6682705 7824 if (fixP->fx_addsy == NULL)
3e73aa7c 7825 fixP->fx_done = 1;
fbeb56a4
DK		 7826#if defined (OBJ_COFF) && defined (TE_PE)
7827 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7828 {
7829 fixP->fx_done = 0;
7830 /* Remember value for tc_gen_reloc. */
7831 fixP->fx_addnumber = value;
7832 /* Clear out the frag for now. */
7833 value = 0;
7834 }
7835#endif
3e73aa7c
JH		 7836 else if (use_rela_relocations)
7837 {
7838 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7839 /* Remember value for tc_gen_reloc. */
7840 fixP->fx_addnumber = value;
3e73aa7c
JH		 7841 value = 0;
7842 }
f86103b7 7843
94f592af 7844 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7845}
252b5132 7846\f
252b5132 7847char *
499ac353 7848md_atof (int type, char *litP, int *sizeP)
252b5132 7849{
499ac353
NC		 7850 /* This outputs the LITTLENUMs in REVERSE order;
7851 in accord with the bigendian 386. */
7852 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7853}
7854\f
2d545b82 7855static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7856
252b5132 7857static char *
e3bb37b5 7858output_invalid (int c)
252b5132 7859{
3882b010 7860 if (ISPRINT (c))
f9f21a03
L		 7861 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7862 "'%c'", c);
252b5132 7863 else
f9f21a03 7864 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7865 "(0x%x)", (unsigned char) c);
252b5132
RH		 7866 return output_invalid_buf;
7867}
7868
af6bdddf 7869/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7870
7871static const reg_entry *
4d1bb795 7872parse_real_register (char *reg_string, char **end_op)
252b5132 7873{
af6bdddf
AM		 7874 char *s = reg_string;
7875 char *p;
252b5132
RH		 7876 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7877 const reg_entry *r;
7878
7879 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7880 if (*s == REGISTER_PREFIX)
7881 ++s;
7882
7883 if (is_space_char (*s))
7884 ++s;
7885
7886 p = reg_name_given;
af6bdddf 7887 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7888 {
7889 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7890 return (const reg_entry *) NULL;
7891 s++;
252b5132
RH		 7892 }
7893
6588847e
DN		 7894 /* For naked regs, make sure that we are not dealing with an identifier.
7895 This prevents confusing an identifier like `eax_var' with register
7896 `eax'. */
7897 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7898 return (const reg_entry *) NULL;
7899
af6bdddf 7900 *end_op = s;
252b5132
RH		 7901
7902 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7903
5f47d35b 7904 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7905 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7906 {
5f47d35b
AM		 7907 if (is_space_char (*s))
7908 ++s;
7909 if (*s == '(')
7910 {
af6bdddf 7911 ++s;
5f47d35b
AM		 7912 if (is_space_char (*s))
7913 ++s;
7914 if (*s >= '0' && *s <= '7')
7915 {
db557034 7916 int fpr = *s - '0';
af6bdddf 7917 ++s;
5f47d35b
AM		 7918 if (is_space_char (*s))
7919 ++s;
7920 if (*s == ')')
7921 {
7922 *end_op = s + 1;
1e9cc1c2 7923 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7924 know (r);
7925 return r + fpr;
5f47d35b 7926 }
5f47d35b 7927 }
47926f60 7928 /* We have "%st(" then garbage. */
5f47d35b
AM		 7929 return (const reg_entry *) NULL;
7930 }
7931 }
7932
a60de03c
JB		 7933 if (r == NULL || allow_pseudo_reg)
7934 return r;
7935
0dfbf9d7 7936 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7937 return (const reg_entry *) NULL;
7938
192dc9c6
JB		 7939 if ((r->reg_type.bitfield.reg32
7940 || r->reg_type.bitfield.sreg3
7941 || r->reg_type.bitfield.control
7942 || r->reg_type.bitfield.debug
7943 || r->reg_type.bitfield.test)
7944 && !cpu_arch_flags.bitfield.cpui386)
7945 return (const reg_entry *) NULL;
7946
309d3373
JB		 7947 if (r->reg_type.bitfield.floatreg
7948 && !cpu_arch_flags.bitfield.cpu8087
7949 && !cpu_arch_flags.bitfield.cpu287
7950 && !cpu_arch_flags.bitfield.cpu387)
7951 return (const reg_entry *) NULL;
7952
192dc9c6
JB		 7953 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7954 return (const reg_entry *) NULL;
7955
7956 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7957 return (const reg_entry *) NULL;
7958
40f12533
L		 7959 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7960 return (const reg_entry *) NULL;
7961
db51cc60 7962 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7963 if (!allow_index_reg
db51cc60
L		 7964 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7965 return (const reg_entry *) NULL;
7966
a60de03c
JB		 7967 if (((r->reg_flags & (RegRex64 | RegRex))
7968 || r->reg_type.bitfield.reg64)
40fb9820 7969 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7970 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7971 && flag_code != CODE_64BIT)
20f0a1fc 7972 return (const reg_entry *) NULL;
1ae00879 7973
b7240065
JB		 7974 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7975 return (const reg_entry *) NULL;
7976
252b5132
RH		 7977 return r;
7978}
4d1bb795
JB		 7979
7980/* REG_STRING starts *before* REGISTER_PREFIX. */
7981
7982static const reg_entry *
7983parse_register (char *reg_string, char **end_op)
7984{
7985 const reg_entry *r;
7986
7987 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7988 r = parse_real_register (reg_string, end_op);
7989 else
7990 r = NULL;
7991 if (!r)
7992 {
7993 char *save = input_line_pointer;
7994 char c;
7995 symbolS *symbolP;
7996
7997 input_line_pointer = reg_string;
7998 c = get_symbol_end ();
7999 symbolP = symbol_find (reg_string);
8000 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8001 {
8002 const expressionS *e = symbol_get_value_expression (symbolP);
8003
0398aac5 8004 know (e->X_op == O_register);
4eed87de 8005 know (e->X_add_number >= 0
c3fe08fa 8006 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8007 r = i386_regtab + e->X_add_number;
8008 *end_op = input_line_pointer;
8009 }
8010 *input_line_pointer = c;
8011 input_line_pointer = save;
8012 }
8013 return r;
8014}
8015
8016int
8017i386_parse_name (char *name, expressionS *e, char *nextcharP)
8018{
8019 const reg_entry *r;
8020 char *end = input_line_pointer;
8021
8022 *end = *nextcharP;
8023 r = parse_register (name, &input_line_pointer);
8024 if (r && end <= input_line_pointer)
8025 {
8026 *nextcharP = *input_line_pointer;
8027 *input_line_pointer = 0;
8028 e->X_op = O_register;
8029 e->X_add_number = r - i386_regtab;
8030 return 1;
8031 }
8032 input_line_pointer = end;
8033 *end = 0;
ee86248c 8034 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8035}
8036
8037void
8038md_operand (expressionS *e)
8039{
ee86248c
JB		 8040 char *end;
8041 const reg_entry *r;
4d1bb795 8042
ee86248c
JB		 8043 switch (*input_line_pointer)
8044 {
8045 case REGISTER_PREFIX:
8046 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8047 if (r)
8048 {
8049 e->X_op = O_register;
8050 e->X_add_number = r - i386_regtab;
8051 input_line_pointer = end;
8052 }
ee86248c
JB		 8053 break;
8054
8055 case '[':
9c2799c2 8056 gas_assert (intel_syntax);
ee86248c
JB		 8057 end = input_line_pointer++;
8058 expression (e);
8059 if (*input_line_pointer == ']')
8060 {
8061 ++input_line_pointer;
8062 e->X_op_symbol = make_expr_symbol (e);
8063 e->X_add_symbol = NULL;
8064 e->X_add_number = 0;
8065 e->X_op = O_index;
8066 }
8067 else
8068 {
8069 e->X_op = O_absent;
8070 input_line_pointer = end;
8071 }
8072 break;
4d1bb795
JB		 8073 }
8074}
8075
252b5132 8076\f
4cc782b5 8077#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8078const char *md_shortopts = "kVQ:sqn";
252b5132 8079#else
12b55ccc 8080const char *md_shortopts = "qn";
252b5132 8081#endif
6e0b89ee 8082
3e73aa7c 8083#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8084#define OPTION_64 (OPTION_MD_BASE + 1)
8085#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8086#define OPTION_MARCH (OPTION_MD_BASE + 3)
8087#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8088#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8089#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8090#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8091#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8092#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8093#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8094#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8095#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
b3b91714 8096
99ad8390
NC		 8097struct option md_longopts[] =
8098{
3e73aa7c 8099 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8100#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8101 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8102 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 8103#endif
b3b91714 8104 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8105 {"march", required_argument, NULL, OPTION_MARCH},
8106 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8107 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8108 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8109 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8110 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8111 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8112 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8113 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8114 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8115 {NULL, no_argument, NULL, 0}
8116};
8117size_t md_longopts_size = sizeof (md_longopts);
8118
8119int
9103f4f4 8120md_parse_option (int c, char *arg)
252b5132 8121{
91d6fa6a 8122 unsigned int j;
6305a203 8123 char *arch, *next;
9103f4f4 8124
252b5132
RH		 8125 switch (c)
8126 {
12b55ccc
L		 8127 case 'n':
8128 optimize_align_code = 0;
8129 break;
8130
a38cf1db
AM		 8131 case 'q':
8132 quiet_warnings = 1;
252b5132
RH		 8133 break;
8134
8135#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8136 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8137 should be emitted or not. FIXME: Not implemented. */
8138 case 'Q':
252b5132
RH		 8139 break;
8140
8141 /* -V: SVR4 argument to print version ID. */
8142 case 'V':
8143 print_version_id ();
8144 break;
8145
a38cf1db
AM		 8146 /* -k: Ignore for FreeBSD compatibility. */
8147 case 'k':
252b5132 8148 break;
4cc782b5
ILT		 8149
8150 case 's':
8151 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8152 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8153 break;
99ad8390 8154#endif
321098a5
L		 8155#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8156 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8157 case OPTION_64:
8158 {
8159 const char **list, **l;
8160
3e73aa7c
JH		 8161 list = bfd_target_list ();
8162 for (l = list; *l != NULL; l++)
8620418b 8163 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8164 || strcmp (*l, "coff-x86-64") == 0
8165 || strcmp (*l, "pe-x86-64") == 0
8166 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8167 {
8168 default_arch = "x86_64";
8169 break;
8170 }
3e73aa7c 8171 if (*l == NULL)
6e0b89ee 8172 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8173 free (list);
8174 }
8175 break;
8176#endif
252b5132 8177
6e0b89ee
AM		 8178 case OPTION_32:
8179 default_arch = "i386";
8180 break;
8181
b3b91714
AM		 8182 case OPTION_DIVIDE:
8183#ifdef SVR4_COMMENT_CHARS
8184 {
8185 char *n, *t;
8186 const char *s;
8187
8188 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8189 t = n;
8190 for (s = i386_comment_chars; *s != '\0'; s++)
8191 if (*s != '/')
8192 *t++ = *s;
8193 *t = '\0';
8194 i386_comment_chars = n;
8195 }
8196#endif
8197 break;
8198
9103f4f4 8199 case OPTION_MARCH:
6305a203
L		 8200 arch = xstrdup (arg);
8201 do
9103f4f4 8202 {
6305a203
L		 8203 if (*arch == '.')
8204 as_fatal (_("Invalid -march= option: `%s'"), arg);
8205 next = strchr (arch, '+');
8206 if (next)
8207 *next++ = '\0';
91d6fa6a 8208 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8209 {
91d6fa6a 8210 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8211 {
6305a203 8212 /* Processor. */
1ded5609
JB		 8213 if (! cpu_arch[j].flags.bitfield.cpui386)
8214 continue;
8215
91d6fa6a 8216 cpu_arch_name = cpu_arch[j].name;
6305a203 8217 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8218 cpu_arch_flags = cpu_arch[j].flags;
8219 cpu_arch_isa = cpu_arch[j].type;
8220 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8221 if (!cpu_arch_tune_set)
8222 {
8223 cpu_arch_tune = cpu_arch_isa;
8224 cpu_arch_tune_flags = cpu_arch_isa_flags;
8225 }
8226 break;
8227 }
91d6fa6a
NC		 8228 else if (*cpu_arch [j].name == '.'
8229 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8230 {
8231 /* ISA entension. */
8232 i386_cpu_flags flags;
309d3373 8233
49021df2 8234 if (!cpu_arch[j].negated)
309d3373 8235 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8236 cpu_arch[j].flags);
309d3373
JB		 8237 else
8238 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8239 cpu_arch[j].flags);
0dfbf9d7 8240 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8241 {
8242 if (cpu_sub_arch_name)
8243 {
8244 char *name = cpu_sub_arch_name;
8245 cpu_sub_arch_name = concat (name,
91d6fa6a 8246 cpu_arch[j].name,
1bf57e9f 8247 (const char *) NULL);
6305a203
L		 8248 free (name);
8249 }
8250 else
91d6fa6a 8251 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8252 cpu_arch_flags = flags;
8253 }
8254 break;
ccc9c027 8255 }
9103f4f4 8256 }
6305a203 8257
91d6fa6a 8258 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8259 as_fatal (_("Invalid -march= option: `%s'"), arg);
8260
8261 arch = next;
9103f4f4 8262 }
6305a203 8263 while (next != NULL );
9103f4f4
L		 8264 break;
8265
8266 case OPTION_MTUNE:
8267 if (*arg == '.')
8268 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8269 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8270 {
91d6fa6a 8271 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8272 {
ccc9c027 8273 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8274 cpu_arch_tune = cpu_arch [j].type;
8275 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8276 break;
8277 }
8278 }
91d6fa6a 8279 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8280 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8281 break;
8282
1efbbeb4
L		 8283 case OPTION_MMNEMONIC:
8284 if (strcasecmp (arg, "att") == 0)
8285 intel_mnemonic = 0;
8286 else if (strcasecmp (arg, "intel") == 0)
8287 intel_mnemonic = 1;
8288 else
8289 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8290 break;
8291
8292 case OPTION_MSYNTAX:
8293 if (strcasecmp (arg, "att") == 0)
8294 intel_syntax = 0;
8295 else if (strcasecmp (arg, "intel") == 0)
8296 intel_syntax = 1;
8297 else
8298 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8299 break;
8300
8301 case OPTION_MINDEX_REG:
8302 allow_index_reg = 1;
8303 break;
8304
8305 case OPTION_MNAKED_REG:
8306 allow_naked_reg = 1;
8307 break;
8308
8309 case OPTION_MOLD_GCC:
8310 old_gcc = 1;
1efbbeb4
L		 8311 break;
8312
c0f3af97
L		 8313 case OPTION_MSSE2AVX:
8314 sse2avx = 1;
8315 break;
8316
daf50ae7
L		 8317 case OPTION_MSSE_CHECK:
8318 if (strcasecmp (arg, "error") == 0)
8319 sse_check = sse_check_error;
8320 else if (strcasecmp (arg, "warning") == 0)
8321 sse_check = sse_check_warning;
8322 else if (strcasecmp (arg, "none") == 0)
8323 sse_check = sse_check_none;
8324 else
8325 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8326 break;
8327
539f890d
L		 8328 case OPTION_MAVXSCALAR:
8329 if (strcasecmp (arg, "128") == 0)
8330 avxscalar = vex128;
8331 else if (strcasecmp (arg, "256") == 0)
8332 avxscalar = vex256;
8333 else
8334 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8335 break;
8336
252b5132
RH		 8337 default:
8338 return 0;
8339 }
8340 return 1;
8341}
8342
8a2c8fef
L		 8343#define MESSAGE_TEMPLATE \
8344" "
8345
8346static void
1ded5609 8347show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8348{
8349 static char message[] = MESSAGE_TEMPLATE;
8350 char *start = message + 27;
8351 char *p;
8352 int size = sizeof (MESSAGE_TEMPLATE);
8353 int left;
8354 const char *name;
8355 int len;
8356 unsigned int j;
8357
8358 p = start;
8359 left = size - (start - message);
8360 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8361 {
8362 /* Should it be skipped? */
8363 if (cpu_arch [j].skip)
8364 continue;
8365
8366 name = cpu_arch [j].name;
8367 len = cpu_arch [j].len;
8368 if (*name == '.')
8369 {
8370 /* It is an extension. Skip if we aren't asked to show it. */
8371 if (ext)
8372 {
8373 name++;
8374 len--;
8375 }
8376 else
8377 continue;
8378 }
8379 else if (ext)
8380 {
8381 /* It is an processor. Skip if we show only extension. */
8382 continue;
8383 }
1ded5609
JB		 8384 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8385 {
8386 /* It is an impossible processor - skip. */
8387 continue;
8388 }
8a2c8fef
L		 8389
8390 /* Reserve 2 spaces for ", " or ",\0" */
8391 left -= len + 2;
8392
8393 /* Check if there is any room. */
8394 if (left >= 0)
8395 {
8396 if (p != start)
8397 {
8398 *p++ = ',';
8399 *p++ = ' ';
8400 }
8401 p = mempcpy (p, name, len);
8402 }
8403 else
8404 {
8405 /* Output the current message now and start a new one. */
8406 *p++ = ',';
8407 *p = '\0';
8408 fprintf (stream, "%s\n", message);
8409 p = start;
8410 left = size - (start - message) - len - 2;
8411
8412 gas_assert (left >= 0);
8413
8414 p = mempcpy (p, name, len);
8415 }
8416 }
8417
8418 *p = '\0';
8419 fprintf (stream, "%s\n", message);
8420}
8421
252b5132 8422void
8a2c8fef 8423md_show_usage (FILE *stream)
252b5132 8424{
4cc782b5
ILT		 8425#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8426 fprintf (stream, _("\
a38cf1db
AM		 8427 -Q ignored\n\
8428 -V print assembler version number\n\
b3b91714
AM		 8429 -k ignored\n"));
8430#endif
8431 fprintf (stream, _("\
12b55ccc 8432 -n Do not optimize code alignment\n\
b3b91714
AM		 8433 -q quieten some warnings\n"));
8434#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8435 fprintf (stream, _("\
a38cf1db 8436 -s ignored\n"));
b3b91714 8437#endif
321098a5
L		 8438#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8439 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8440 fprintf (stream, _("\
8441 --32/--64 generate 32bit/64bit code\n"));
8442#endif
b3b91714
AM		 8443#ifdef SVR4_COMMENT_CHARS
8444 fprintf (stream, _("\
8445 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8446#else
8447 fprintf (stream, _("\
b3b91714 8448 --divide ignored\n"));
4cc782b5 8449#endif
9103f4f4 8450 fprintf (stream, _("\
6305a203 8451 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8452 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8453 show_arch (stream, 0, 1);
8a2c8fef
L		 8454 fprintf (stream, _("\
8455 EXTENSION is combination of:\n"));
1ded5609 8456 show_arch (stream, 1, 0);
6305a203 8457 fprintf (stream, _("\
8a2c8fef 8458 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8459 show_arch (stream, 0, 0);
ba104c83 8460 fprintf (stream, _("\
c0f3af97
L		 8461 -msse2avx encode SSE instructions with VEX prefix\n"));
8462 fprintf (stream, _("\
daf50ae7
L		 8463 -msse-check=[none|error|warning]\n\
8464 check SSE instructions\n"));
8465 fprintf (stream, _("\
539f890d
L		 8466 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8467 length\n"));
8468 fprintf (stream, _("\
ba104c83
L		 8469 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8470 fprintf (stream, _("\
8471 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8472 fprintf (stream, _("\
8473 -mindex-reg support pseudo index registers\n"));
8474 fprintf (stream, _("\
8475 -mnaked-reg don't require `%%' prefix for registers\n"));
8476 fprintf (stream, _("\
8477 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8478}
8479
3e73aa7c 8480#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8481 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8482 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8483
8484/* Pick the target format to use. */
8485
47926f60 8486const char *
e3bb37b5 8487i386_target_format (void)
252b5132 8488{
3e73aa7c 8489 if (!strcmp (default_arch, "x86_64"))
78f12dd3 8490 update_code_flag (CODE_64BIT, 1);
3e73aa7c 8491 else if (!strcmp (default_arch, "i386"))
78f12dd3 8492 update_code_flag (CODE_32BIT, 1);
3e73aa7c
JH		 8493 else
8494 as_fatal (_("Unknown architecture"));
89507696
JB		 8495
8496 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8497 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8498 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8499 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8500
252b5132
RH		 8501 switch (OUTPUT_FLAVOR)
8502 {
9384f2ff 8503#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8504 case bfd_target_aout_flavour:
47926f60 8505 return AOUT_TARGET_FORMAT;
4c63da97 8506#endif
9384f2ff
AM		 8507#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8508# if defined (TE_PE) || defined (TE_PEP)
8509 case bfd_target_coff_flavour:
8510 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8511# elif defined (TE_GO32)
0561d57c
JK		 8512 case bfd_target_coff_flavour:
8513 return "coff-go32";
9384f2ff 8514# else
252b5132
RH		 8515 case bfd_target_coff_flavour:
8516 return "coff-i386";
9384f2ff 8517# endif
4c63da97 8518#endif
3e73aa7c 8519#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8520 case bfd_target_elf_flavour:
3e73aa7c 8521 {
e5cb08ac 8522 if (flag_code == CODE_64BIT)
4fa24527
JB		 8523 {
8524 object_64bit = 1;
8525 use_rela_relocations = 1;
8526 }
3632d14b 8527 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8528 {
8529 if (flag_code != CODE_64BIT)
8530 as_fatal (_("Intel L1OM is 64bit only"));
8531 return ELF_TARGET_L1OM_FORMAT;
8532 }
8533 else
8534 return (flag_code == CODE_64BIT
8535 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8536 }
e57f8c65
TG		 8537#endif
8538#if defined (OBJ_MACH_O)
8539 case bfd_target_mach_o_flavour:
8540 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8541#endif
252b5132
RH		 8542 default:
8543 abort ();
8544 return NULL;
8545 }
8546}
8547
47926f60 8548#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8549
8550#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8551void
8552i386_elf_emit_arch_note (void)
a847613f 8553{
718ddfc0 8554 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8555 {
8556 char *p;
8557 asection *seg = now_seg;
8558 subsegT subseg = now_subseg;
8559 Elf_Internal_Note i_note;
8560 Elf_External_Note e_note;
8561 asection *note_secp;
8562 int len;
8563
8564 /* Create the .note section. */
8565 note_secp = subseg_new (".note", 0);
8566 bfd_set_section_flags (stdoutput,
8567 note_secp,
8568 SEC_HAS_CONTENTS | SEC_READONLY);
8569
8570 /* Process the arch string. */
8571 len = strlen (cpu_arch_name);
8572
8573 i_note.namesz = len + 1;
8574 i_note.descsz = 0;
8575 i_note.type = NT_ARCH;
8576 p = frag_more (sizeof (e_note.namesz));
8577 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8578 p = frag_more (sizeof (e_note.descsz));
8579 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8580 p = frag_more (sizeof (e_note.type));
8581 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8582 p = frag_more (len + 1);
8583 strcpy (p, cpu_arch_name);
8584
8585 frag_align (2, 0, 0);
8586
8587 subseg_set (seg, subseg);
8588 }
8589}
8590#endif
252b5132 8591\f
252b5132
RH		 8592symbolS *
8593md_undefined_symbol (name)
8594 char *name;
8595{
18dc2407
ILT		 8596 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8597 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8598 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8599 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8600 {
8601 if (!GOT_symbol)
8602 {
8603 if (symbol_find (name))
8604 as_bad (_("GOT already in symbol table"));
8605 GOT_symbol = symbol_new (name, undefined_section,
8606 (valueT) 0, &zero_address_frag);
8607 };
8608 return GOT_symbol;
8609 }
252b5132
RH		 8610 return 0;
8611}
8612
8613/* Round up a section size to the appropriate boundary. */
47926f60 8614
252b5132
RH		 8615valueT
8616md_section_align (segment, size)
ab9da554 8617 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8618 valueT size;
8619{
4c63da97
AM		 8620#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8621 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8622 {
8623 /* For a.out, force the section size to be aligned. If we don't do
8624 this, BFD will align it for us, but it will not write out the
8625 final bytes of the section. This may be a bug in BFD, but it is
8626 easier to fix it here since that is how the other a.out targets
8627 work. */
8628 int align;
8629
8630 align = bfd_get_section_alignment (stdoutput, segment);
8631 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8632 }
252b5132
RH		 8633#endif
8634
8635 return size;
8636}
8637
8638/* On the i386, PC-relative offsets are relative to the start of the
8639 next instruction. That is, the address of the offset, plus its
8640 size, since the offset is always the last part of the insn. */
8641
8642long
e3bb37b5 8643md_pcrel_from (fixS *fixP)
252b5132
RH		 8644{
8645 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8646}
8647
8648#ifndef I386COFF
8649
8650static void
e3bb37b5 8651s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8652{
29b0f896 8653 int temp;
252b5132 8654
8a75718c
JB		 8655#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8656 if (IS_ELF)
8657 obj_elf_section_change_hook ();
8658#endif
252b5132
RH		 8659 temp = get_absolute_expression ();
8660 subseg_set (bss_section, (subsegT) temp);
8661 demand_empty_rest_of_line ();
8662}
8663
8664#endif
8665
252b5132 8666void
e3bb37b5 8667i386_validate_fix (fixS *fixp)
252b5132
RH		 8668{
8669 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8670 {
23df1078
JH		 8671 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8672 {
4fa24527 8673 if (!object_64bit)
23df1078
JH		 8674 abort ();
8675 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8676 }
8677 else
8678 {
4fa24527 8679 if (!object_64bit)
d6ab8113
JB		 8680 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8681 else
8682 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8683 }
252b5132
RH		 8684 fixp->fx_subsy = 0;
8685 }
8686}
8687
252b5132
RH		 8688arelent *
8689tc_gen_reloc (section, fixp)
ab9da554 8690 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8691 fixS *fixp;
8692{
8693 arelent *rel;
8694 bfd_reloc_code_real_type code;
8695
8696 switch (fixp->fx_r_type)
8697 {
3e73aa7c
JH		 8698 case BFD_RELOC_X86_64_PLT32:
8699 case BFD_RELOC_X86_64_GOT32:
8700 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8701 case BFD_RELOC_386_PLT32:
8702 case BFD_RELOC_386_GOT32:
8703 case BFD_RELOC_386_GOTOFF:
8704 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8705 case BFD_RELOC_386_TLS_GD:
8706 case BFD_RELOC_386_TLS_LDM:
8707 case BFD_RELOC_386_TLS_LDO_32:
8708 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8709 case BFD_RELOC_386_TLS_IE:
8710 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8711 case BFD_RELOC_386_TLS_LE_32:
8712 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8713 case BFD_RELOC_386_TLS_GOTDESC:
8714 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8715 case BFD_RELOC_X86_64_TLSGD:
8716 case BFD_RELOC_X86_64_TLSLD:
8717 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8718 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8719 case BFD_RELOC_X86_64_GOTTPOFF:
8720 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8721 case BFD_RELOC_X86_64_TPOFF64:
8722 case BFD_RELOC_X86_64_GOTOFF64:
8723 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8724 case BFD_RELOC_X86_64_GOT64:
8725 case BFD_RELOC_X86_64_GOTPCREL64:
8726 case BFD_RELOC_X86_64_GOTPC64:
8727 case BFD_RELOC_X86_64_GOTPLT64:
8728 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8729 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8730 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8731 case BFD_RELOC_RVA:
8732 case BFD_RELOC_VTABLE_ENTRY:
8733 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8734#ifdef TE_PE
8735 case BFD_RELOC_32_SECREL:
8736#endif
252b5132
RH		 8737 code = fixp->fx_r_type;
8738 break;
dbbaec26
L		 8739 case BFD_RELOC_X86_64_32S:
8740 if (!fixp->fx_pcrel)
8741 {
8742 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8743 code = fixp->fx_r_type;
8744 break;
8745 }
252b5132 8746 default:
93382f6d 8747 if (fixp->fx_pcrel)
252b5132 8748 {
93382f6d
AM		 8749 switch (fixp->fx_size)
8750 {
8751 default:
b091f402
AM		 8752 as_bad_where (fixp->fx_file, fixp->fx_line,
8753 _("can not do %d byte pc-relative relocation"),
8754 fixp->fx_size);
93382f6d
AM		 8755 code = BFD_RELOC_32_PCREL;
8756 break;
8757 case 1: code = BFD_RELOC_8_PCREL; break;
8758 case 2: code = BFD_RELOC_16_PCREL; break;
8759 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8760#ifdef BFD64
8761 case 8: code = BFD_RELOC_64_PCREL; break;
8762#endif
93382f6d
AM		 8763 }
8764 }
8765 else
8766 {
8767 switch (fixp->fx_size)
8768 {
8769 default:
b091f402
AM		 8770 as_bad_where (fixp->fx_file, fixp->fx_line,
8771 _("can not do %d byte relocation"),
8772 fixp->fx_size);
93382f6d
AM		 8773 code = BFD_RELOC_32;
8774 break;
8775 case 1: code = BFD_RELOC_8; break;
8776 case 2: code = BFD_RELOC_16; break;
8777 case 4: code = BFD_RELOC_32; break;
937149dd 8778#ifdef BFD64
3e73aa7c 8779 case 8: code = BFD_RELOC_64; break;
937149dd 8780#endif
93382f6d 8781 }
252b5132
RH		 8782 }
8783 break;
8784 }
252b5132 8785
d182319b
JB		 8786 if ((code == BFD_RELOC_32
8787 || code == BFD_RELOC_32_PCREL
8788 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8789 && GOT_symbol
8790 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8791 {
4fa24527 8792 if (!object_64bit)
d6ab8113
JB		 8793 code = BFD_RELOC_386_GOTPC;
8794 else
8795 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8796 }
7b81dfbb
AJ		 8797 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8798 && GOT_symbol
8799 && fixp->fx_addsy == GOT_symbol)
8800 {
8801 code = BFD_RELOC_X86_64_GOTPC64;
8802 }
252b5132
RH		 8803
8804 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8805 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8806 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8807
8808 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8809
3e73aa7c
JH		 8810 if (!use_rela_relocations)
8811 {
8812 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8813 vtable entry to be used in the relocation's section offset. */
8814 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8815 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8816#if defined (OBJ_COFF) && defined (TE_PE)
8817 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8818 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8819 else
8820#endif
c6682705 8821 rel->addend = 0;
3e73aa7c
JH		 8822 }
8823 /* Use the rela in 64bit mode. */
252b5132 8824 else
3e73aa7c 8825 {
062cd5e7
AS		 8826 if (!fixp->fx_pcrel)
8827 rel->addend = fixp->fx_offset;
8828 else
8829 switch (code)
8830 {
8831 case BFD_RELOC_X86_64_PLT32:
8832 case BFD_RELOC_X86_64_GOT32:
8833 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8834 case BFD_RELOC_X86_64_TLSGD:
8835 case BFD_RELOC_X86_64_TLSLD:
8836 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8837 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8838 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8839 rel->addend = fixp->fx_offset - fixp->fx_size;
8840 break;
8841 default:
8842 rel->addend = (section->vma
8843 - fixp->fx_size
8844 + fixp->fx_addnumber
8845 + md_pcrel_from (fixp));
8846 break;
8847 }
3e73aa7c
JH		 8848 }
8849
252b5132
RH		 8850 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8851 if (rel->howto == NULL)
8852 {
8853 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8854 _("cannot represent relocation type %s"),
252b5132
RH		 8855 bfd_get_reloc_code_name (code));
8856 /* Set howto to a garbage value so that we can keep going. */
8857 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8858 gas_assert (rel->howto != NULL);
252b5132
RH		 8859 }
8860
8861 return rel;
8862}
8863
ee86248c 8864#include "tc-i386-intel.c"
54cfded0 8865
a60de03c
JB		 8866void
8867tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8868{
a60de03c
JB		 8869 int saved_naked_reg;
8870 char saved_register_dot;
54cfded0 8871
a60de03c
JB		 8872 saved_naked_reg = allow_naked_reg;
8873 allow_naked_reg = 1;
8874 saved_register_dot = register_chars['.'];
8875 register_chars['.'] = '.';
8876 allow_pseudo_reg = 1;
8877 expression_and_evaluate (exp);
8878 allow_pseudo_reg = 0;
8879 register_chars['.'] = saved_register_dot;
8880 allow_naked_reg = saved_naked_reg;
8881
e96d56a1 8882 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8883 {
a60de03c
JB		 8884 if ((addressT) exp->X_add_number < i386_regtab_size)
8885 {
8886 exp->X_op = O_constant;
8887 exp->X_add_number = i386_regtab[exp->X_add_number]
8888 .dw2_regnum[flag_code >> 1];
8889 }
8890 else
8891 exp->X_op = O_illegal;
54cfded0 8892 }
54cfded0
AM		 8893}
8894
8895void
8896tc_x86_frame_initial_instructions (void)
8897{
a60de03c
JB		 8898 static unsigned int sp_regno[2];
8899
8900 if (!sp_regno[flag_code >> 1])
8901 {
8902 char *saved_input = input_line_pointer;
8903 char sp[][4] = {"esp", "rsp"};
8904 expressionS exp;
a4447b93 8905
a60de03c
JB		 8906 input_line_pointer = sp[flag_code >> 1];
8907 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8908 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8909 sp_regno[flag_code >> 1] = exp.X_add_number;
8910 input_line_pointer = saved_input;
8911 }
a4447b93 8912
a60de03c 8913 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8914 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8915}
d2b2c203
DJ		 8916
8917int
8918i386_elf_section_type (const char *str, size_t len)
8919{
8920 if (flag_code == CODE_64BIT
8921 && len == sizeof ("unwind") - 1
8922 && strncmp (str, "unwind", 6) == 0)
8923 return SHT_X86_64_UNWIND;
8924
8925 return -1;
8926}
bb41ade5 8927
ad5fec3b
EB		 8928#ifdef TE_SOLARIS
8929void
8930i386_solaris_fix_up_eh_frame (segT sec)
8931{
8932 if (flag_code == CODE_64BIT)
8933 elf_section_type (sec) = SHT_X86_64_UNWIND;
8934}
8935#endif
8936
bb41ade5
AM		 8937#ifdef TE_PE
8938void
8939tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8940{
91d6fa6a 8941 expressionS exp;
bb41ade5 8942
91d6fa6a
NC		 8943 exp.X_op = O_secrel;
8944 exp.X_add_symbol = symbol;
8945 exp.X_add_number = 0;
8946 emit_expr (&exp, size);
bb41ade5
AM		 8947}
8948#endif
3b22753a
L		 8949
8950#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8951/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8952
01e1a5bc 8953bfd_vma
3b22753a
L		 8954x86_64_section_letter (int letter, char **ptr_msg)
8955{
8956 if (flag_code == CODE_64BIT)
8957 {
8958 if (letter == 'l')
8959 return SHF_X86_64_LARGE;
8960
8f3bae45 8961 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8962 }
3b22753a 8963 else
8f3bae45 8964 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8965 return -1;
8966}
8967
01e1a5bc 8968bfd_vma
3b22753a
L		 8969x86_64_section_word (char *str, size_t len)
8970{
8620418b 8971 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8972 return SHF_X86_64_LARGE;
8973
8974 return -1;
8975}
8976
8977static void
8978handle_large_common (int small ATTRIBUTE_UNUSED)
8979{
8980 if (flag_code != CODE_64BIT)
8981 {
8982 s_comm_internal (0, elf_common_parse);
8983 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8984 }
8985 else
8986 {
8987 static segT lbss_section;
8988 asection *saved_com_section_ptr = elf_com_section_ptr;
8989 asection *saved_bss_section = bss_section;
8990
8991 if (lbss_section == NULL)
8992 {
8993 flagword applicable;
8994 segT seg = now_seg;
8995 subsegT subseg = now_subseg;
8996
8997 /* The .lbss section is for local .largecomm symbols. */
8998 lbss_section = subseg_new (".lbss", 0);
8999 applicable = bfd_applicable_section_flags (stdoutput);
9000 bfd_set_section_flags (stdoutput, lbss_section,
9001 applicable & SEC_ALLOC);
9002 seg_info (lbss_section)->bss = 1;
9003
9004 subseg_set (seg, subseg);
9005 }
9006
9007 elf_com_section_ptr = &_bfd_elf_large_com_section;
9008 bss_section = lbss_section;
9009
9010 s_comm_internal (0, elf_common_parse);
9011
9012 elf_com_section_ptr = saved_com_section_ptr;
9013 bss_section = saved_bss_section;
9014 }
9015}
9016#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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