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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
b3adc24a | 2 | Copyright (C) 1989-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
c3332e24 | 47 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 48 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
49 | #endif |
50 | ||
29b0f896 AM |
51 | #ifndef DEFAULT_ARCH |
52 | #define DEFAULT_ARCH "i386" | |
246fcdee | 53 | #endif |
252b5132 | 54 | |
edde18a5 AM |
55 | #ifndef INLINE |
56 | #if __GNUC__ >= 2 | |
57 | #define INLINE __inline__ | |
58 | #else | |
59 | #define INLINE | |
60 | #endif | |
61 | #endif | |
62 | ||
6305a203 L |
63 | /* Prefixes will be emitted in the order defined below. |
64 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
65 | instruction, and so must come before any prefixes. | |
66 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 67 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
68 | #define WAIT_PREFIX 0 |
69 | #define SEG_PREFIX 1 | |
70 | #define ADDR_PREFIX 2 | |
71 | #define DATA_PREFIX 3 | |
c32fa91d | 72 | #define REP_PREFIX 4 |
42164a71 | 73 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 74 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 75 | #define LOCK_PREFIX 5 |
4e9ac44a L |
76 | #define REX_PREFIX 6 /* must come last. */ |
77 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
78 | |
79 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
80 | #define REGISTER_PREFIX '%' | |
81 | #define IMMEDIATE_PREFIX '$' | |
82 | #define ABSOLUTE_PREFIX '*' | |
83 | ||
84 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
85 | memory operand size in Intel syntax. */ | |
86 | #define WORD_MNEM_SUFFIX 'w' | |
87 | #define BYTE_MNEM_SUFFIX 'b' | |
88 | #define SHORT_MNEM_SUFFIX 's' | |
89 | #define LONG_MNEM_SUFFIX 'l' | |
90 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
91 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
92 | in instructions. */ | |
93 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
94 | ||
95 | #define END_OF_INSN '\0' | |
96 | ||
79dec6b7 JB |
97 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
98 | #define commutative staticrounding | |
99 | ||
6305a203 L |
100 | /* |
101 | 'templates' is for grouping together 'template' structures for opcodes | |
102 | of the same name. This is only used for storing the insns in the grand | |
103 | ole hash table of insns. | |
104 | The templates themselves start at START and range up to (but not including) | |
105 | END. | |
106 | */ | |
107 | typedef struct | |
108 | { | |
d3ce72d0 NC |
109 | const insn_template *start; |
110 | const insn_template *end; | |
6305a203 L |
111 | } |
112 | templates; | |
113 | ||
114 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
115 | typedef struct | |
116 | { | |
117 | unsigned int regmem; /* codes register or memory operand */ | |
118 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
119 | unsigned int mode; /* how to interpret regmem & reg */ | |
120 | } | |
121 | modrm_byte; | |
122 | ||
123 | /* x86-64 extension prefix. */ | |
124 | typedef int rex_byte; | |
125 | ||
6305a203 L |
126 | /* 386 opcode byte to code indirect addressing. */ |
127 | typedef struct | |
128 | { | |
129 | unsigned base; | |
130 | unsigned index; | |
131 | unsigned scale; | |
132 | } | |
133 | sib_byte; | |
134 | ||
6305a203 L |
135 | /* x86 arch names, types and features */ |
136 | typedef struct | |
137 | { | |
138 | const char *name; /* arch name */ | |
8a2c8fef | 139 | unsigned int len; /* arch string length */ |
6305a203 L |
140 | enum processor_type type; /* arch type */ |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 142 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
143 | } |
144 | arch_entry; | |
145 | ||
293f5f65 L |
146 | /* Used to turn off indicated flags. */ |
147 | typedef struct | |
148 | { | |
149 | const char *name; /* arch name */ | |
150 | unsigned int len; /* arch string length */ | |
151 | i386_cpu_flags flags; /* cpu feature flags */ | |
152 | } | |
153 | noarch_entry; | |
154 | ||
78f12dd3 | 155 | static void update_code_flag (int, int); |
e3bb37b5 L |
156 | static void set_code_flag (int); |
157 | static void set_16bit_gcc_code_flag (int); | |
158 | static void set_intel_syntax (int); | |
1efbbeb4 | 159 | static void set_intel_mnemonic (int); |
db51cc60 | 160 | static void set_allow_index_reg (int); |
7bab8ab5 | 161 | static void set_check (int); |
e3bb37b5 | 162 | static void set_cpu_arch (int); |
6482c264 | 163 | #ifdef TE_PE |
e3bb37b5 | 164 | static void pe_directive_secrel (int); |
6482c264 | 165 | #endif |
e3bb37b5 L |
166 | static void signed_cons (int); |
167 | static char *output_invalid (int c); | |
ee86248c JB |
168 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
169 | const char *); | |
170 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
171 | const char *); | |
a7619375 | 172 | static int i386_att_operand (char *); |
e3bb37b5 | 173 | static int i386_intel_operand (char *, int); |
ee86248c JB |
174 | static int i386_intel_simplify (expressionS *); |
175 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
176 | static const reg_entry *parse_register (char *, char **); |
177 | static char *parse_insn (char *, char *); | |
178 | static char *parse_operands (char *, const char *); | |
179 | static void swap_operands (void); | |
4d456e3d | 180 | static void swap_2_operands (int, int); |
48bcea9f | 181 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
182 | static void optimize_imm (void); |
183 | static void optimize_disp (void); | |
83b16ac6 | 184 | static const insn_template *match_template (char); |
e3bb37b5 L |
185 | static int check_string (void); |
186 | static int process_suffix (void); | |
187 | static int check_byte_reg (void); | |
188 | static int check_long_reg (void); | |
189 | static int check_qword_reg (void); | |
190 | static int check_word_reg (void); | |
191 | static int finalize_imm (void); | |
192 | static int process_operands (void); | |
193 | static const seg_entry *build_modrm_byte (void); | |
194 | static void output_insn (void); | |
195 | static void output_imm (fragS *, offsetT); | |
196 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 197 | #ifndef I386COFF |
e3bb37b5 | 198 | static void s_bss (int); |
252b5132 | 199 | #endif |
17d4e2a2 L |
200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
201 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
202 | |
203 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
204 | static unsigned int x86_isa_1_used; | |
205 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
206 | static unsigned int x86_feature_2_used; | |
207 | /* Generate x86 used ISA and feature properties. */ | |
208 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 209 | #endif |
252b5132 | 210 | |
a847613f | 211 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 212 | |
43234a1e L |
213 | /* This struct describes rounding control and SAE in the instruction. */ |
214 | struct RC_Operation | |
215 | { | |
216 | enum rc_type | |
217 | { | |
218 | rne = 0, | |
219 | rd, | |
220 | ru, | |
221 | rz, | |
222 | saeonly | |
223 | } type; | |
224 | int operand; | |
225 | }; | |
226 | ||
227 | static struct RC_Operation rc_op; | |
228 | ||
229 | /* The struct describes masking, applied to OPERAND in the instruction. | |
230 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
231 | whether merging or zeroing mask is used. */ | |
232 | struct Mask_Operation | |
233 | { | |
234 | const reg_entry *mask; | |
235 | unsigned int zeroing; | |
236 | /* The operand where this operation is associated. */ | |
237 | int operand; | |
238 | }; | |
239 | ||
240 | static struct Mask_Operation mask_op; | |
241 | ||
242 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
243 | broadcast factor. */ | |
244 | struct Broadcast_Operation | |
245 | { | |
8e6e0792 | 246 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
247 | int type; |
248 | ||
249 | /* Index of broadcasted operand. */ | |
250 | int operand; | |
4a1b91ea L |
251 | |
252 | /* Number of bytes to broadcast. */ | |
253 | int bytes; | |
43234a1e L |
254 | }; |
255 | ||
256 | static struct Broadcast_Operation broadcast_op; | |
257 | ||
c0f3af97 L |
258 | /* VEX prefix. */ |
259 | typedef struct | |
260 | { | |
43234a1e L |
261 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
262 | unsigned char bytes[4]; | |
c0f3af97 L |
263 | unsigned int length; |
264 | /* Destination or source register specifier. */ | |
265 | const reg_entry *register_specifier; | |
266 | } vex_prefix; | |
267 | ||
252b5132 | 268 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 269 | i386_insn. */ |
252b5132 | 270 | |
520dc8e8 AM |
271 | union i386_op |
272 | { | |
273 | expressionS *disps; | |
274 | expressionS *imms; | |
275 | const reg_entry *regs; | |
276 | }; | |
277 | ||
a65babc9 L |
278 | enum i386_error |
279 | { | |
86e026a4 | 280 | operand_size_mismatch, |
a65babc9 L |
281 | operand_type_mismatch, |
282 | register_type_mismatch, | |
283 | number_of_operands_mismatch, | |
284 | invalid_instruction_suffix, | |
285 | bad_imm4, | |
a65babc9 L |
286 | unsupported_with_intel_mnemonic, |
287 | unsupported_syntax, | |
6c30d220 L |
288 | unsupported, |
289 | invalid_vsib_address, | |
7bab8ab5 | 290 | invalid_vector_register_set, |
43234a1e L |
291 | unsupported_vector_index_register, |
292 | unsupported_broadcast, | |
43234a1e L |
293 | broadcast_needed, |
294 | unsupported_masking, | |
295 | mask_not_on_destination, | |
296 | no_default_mask, | |
297 | unsupported_rc_sae, | |
298 | rc_sae_operand_not_last_imm, | |
299 | invalid_register_operand, | |
a65babc9 L |
300 | }; |
301 | ||
252b5132 RH |
302 | struct _i386_insn |
303 | { | |
47926f60 | 304 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 305 | insn_template tm; |
252b5132 | 306 | |
7d5e4556 L |
307 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
308 | or qword, if given. */ | |
252b5132 RH |
309 | char suffix; |
310 | ||
47926f60 | 311 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
312 | unsigned int operands; |
313 | ||
314 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
315 | of given register, displacement, memory operands and immediate | |
47926f60 | 316 | operands. */ |
252b5132 RH |
317 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
318 | ||
319 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 320 | use OP[i] for the corresponding operand. */ |
40fb9820 | 321 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 322 | |
520dc8e8 AM |
323 | /* Displacement expression, immediate expression, or register for each |
324 | operand. */ | |
325 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 326 | |
3e73aa7c JH |
327 | /* Flags for operands. */ |
328 | unsigned int flags[MAX_OPERANDS]; | |
329 | #define Operand_PCrel 1 | |
c48dadc9 | 330 | #define Operand_Mem 2 |
3e73aa7c | 331 | |
252b5132 | 332 | /* Relocation type for operand */ |
f86103b7 | 333 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 334 | |
252b5132 RH |
335 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
336 | the base index byte below. */ | |
337 | const reg_entry *base_reg; | |
338 | const reg_entry *index_reg; | |
339 | unsigned int log2_scale_factor; | |
340 | ||
341 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 342 | explicit segment overrides are given. */ |
ce8a8b2f | 343 | const seg_entry *seg[2]; |
252b5132 | 344 | |
8325cc63 JB |
345 | /* Copied first memory operand string, for re-checking. */ |
346 | char *memop1_string; | |
347 | ||
252b5132 RH |
348 | /* PREFIX holds all the given prefix opcodes (usually null). |
349 | PREFIXES is the number of prefix opcodes. */ | |
350 | unsigned int prefixes; | |
351 | unsigned char prefix[MAX_PREFIXES]; | |
352 | ||
50128d0c JB |
353 | /* Register is in low 3 bits of opcode. */ |
354 | bfd_boolean short_form; | |
355 | ||
6f2f06be JB |
356 | /* The operand to a branch insn indicates an absolute branch. */ |
357 | bfd_boolean jumpabsolute; | |
358 | ||
b4a3a7b4 L |
359 | /* Has MMX register operands. */ |
360 | bfd_boolean has_regmmx; | |
361 | ||
362 | /* Has XMM register operands. */ | |
363 | bfd_boolean has_regxmm; | |
364 | ||
365 | /* Has YMM register operands. */ | |
366 | bfd_boolean has_regymm; | |
367 | ||
368 | /* Has ZMM register operands. */ | |
369 | bfd_boolean has_regzmm; | |
370 | ||
e379e5f3 L |
371 | /* Has GOTPC or TLS relocation. */ |
372 | bfd_boolean has_gotpc_tls_reloc; | |
373 | ||
252b5132 | 374 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 375 | addressing modes of this insn are encoded. */ |
252b5132 | 376 | modrm_byte rm; |
3e73aa7c | 377 | rex_byte rex; |
43234a1e | 378 | rex_byte vrex; |
252b5132 | 379 | sib_byte sib; |
c0f3af97 | 380 | vex_prefix vex; |
b6169b20 | 381 | |
43234a1e L |
382 | /* Masking attributes. */ |
383 | struct Mask_Operation *mask; | |
384 | ||
385 | /* Rounding control and SAE attributes. */ | |
386 | struct RC_Operation *rounding; | |
387 | ||
388 | /* Broadcasting attributes. */ | |
389 | struct Broadcast_Operation *broadcast; | |
390 | ||
391 | /* Compressed disp8*N attribute. */ | |
392 | unsigned int memshift; | |
393 | ||
86fa6981 L |
394 | /* Prefer load or store in encoding. */ |
395 | enum | |
396 | { | |
397 | dir_encoding_default = 0, | |
398 | dir_encoding_load, | |
64c49ab3 JB |
399 | dir_encoding_store, |
400 | dir_encoding_swap | |
86fa6981 | 401 | } dir_encoding; |
891edac4 | 402 | |
a501d77e L |
403 | /* Prefer 8bit or 32bit displacement in encoding. */ |
404 | enum | |
405 | { | |
406 | disp_encoding_default = 0, | |
407 | disp_encoding_8bit, | |
408 | disp_encoding_32bit | |
409 | } disp_encoding; | |
f8a5c266 | 410 | |
6b6b6807 L |
411 | /* Prefer the REX byte in encoding. */ |
412 | bfd_boolean rex_encoding; | |
413 | ||
b6f8c7c4 L |
414 | /* Disable instruction size optimization. */ |
415 | bfd_boolean no_optimize; | |
416 | ||
86fa6981 L |
417 | /* How to encode vector instructions. */ |
418 | enum | |
419 | { | |
420 | vex_encoding_default = 0, | |
42e04b36 | 421 | vex_encoding_vex, |
86fa6981 L |
422 | vex_encoding_vex3, |
423 | vex_encoding_evex | |
424 | } vec_encoding; | |
425 | ||
d5de92cf L |
426 | /* REP prefix. */ |
427 | const char *rep_prefix; | |
428 | ||
165de32a L |
429 | /* HLE prefix. */ |
430 | const char *hle_prefix; | |
42164a71 | 431 | |
7e8b059b L |
432 | /* Have BND prefix. */ |
433 | const char *bnd_prefix; | |
434 | ||
04ef582a L |
435 | /* Have NOTRACK prefix. */ |
436 | const char *notrack_prefix; | |
437 | ||
891edac4 | 438 | /* Error message. */ |
a65babc9 | 439 | enum i386_error error; |
252b5132 RH |
440 | }; |
441 | ||
442 | typedef struct _i386_insn i386_insn; | |
443 | ||
43234a1e L |
444 | /* Link RC type with corresponding string, that'll be looked for in |
445 | asm. */ | |
446 | struct RC_name | |
447 | { | |
448 | enum rc_type type; | |
449 | const char *name; | |
450 | unsigned int len; | |
451 | }; | |
452 | ||
453 | static const struct RC_name RC_NamesTable[] = | |
454 | { | |
455 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
456 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
457 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
458 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
459 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
460 | }; | |
461 | ||
252b5132 RH |
462 | /* List of chars besides those in app.c:symbol_chars that can start an |
463 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 464 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 465 | #ifdef LEX_AT |
32137342 NC |
466 | "@" |
467 | #endif | |
468 | #ifdef LEX_QM | |
469 | "?" | |
252b5132 | 470 | #endif |
32137342 | 471 | ; |
252b5132 | 472 | |
29b0f896 AM |
473 | #if (defined (TE_I386AIX) \ |
474 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 475 | && !defined (TE_GNU) \ |
29b0f896 | 476 | && !defined (TE_LINUX) \ |
8d63c93e | 477 | && !defined (TE_NACL) \ |
29b0f896 | 478 | && !defined (TE_FreeBSD) \ |
5b806d27 | 479 | && !defined (TE_DragonFly) \ |
29b0f896 | 480 | && !defined (TE_NetBSD))) |
252b5132 | 481 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
482 | pre-processor is disabled, these aren't very useful. The option |
483 | --divide will remove '/' from this list. */ | |
484 | const char *i386_comment_chars = "#/"; | |
485 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 486 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 487 | |
b3b91714 AM |
488 | #else |
489 | const char *i386_comment_chars = "#"; | |
490 | #define PREFIX_SEPARATOR '/' | |
491 | #endif | |
492 | ||
252b5132 RH |
493 | /* This array holds the chars that only start a comment at the beginning of |
494 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
495 | .line and .file directives will appear in the pre-processed output. |
496 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 497 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
498 | #NO_APP at the beginning of its output. |
499 | Also note that comments started like this one will always work if | |
252b5132 | 500 | '/' isn't otherwise defined. */ |
b3b91714 | 501 | const char line_comment_chars[] = "#/"; |
252b5132 | 502 | |
63a0b638 | 503 | const char line_separator_chars[] = ";"; |
252b5132 | 504 | |
ce8a8b2f AM |
505 | /* Chars that can be used to separate mant from exp in floating point |
506 | nums. */ | |
252b5132 RH |
507 | const char EXP_CHARS[] = "eE"; |
508 | ||
ce8a8b2f AM |
509 | /* Chars that mean this number is a floating point constant |
510 | As in 0f12.456 | |
511 | or 0d1.2345e12. */ | |
252b5132 RH |
512 | const char FLT_CHARS[] = "fFdDxX"; |
513 | ||
ce8a8b2f | 514 | /* Tables for lexical analysis. */ |
252b5132 RH |
515 | static char mnemonic_chars[256]; |
516 | static char register_chars[256]; | |
517 | static char operand_chars[256]; | |
518 | static char identifier_chars[256]; | |
519 | static char digit_chars[256]; | |
520 | ||
ce8a8b2f | 521 | /* Lexical macros. */ |
252b5132 RH |
522 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
523 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
524 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
525 | #define is_space_char(x) ((x) == ' ') | |
526 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
527 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
528 | ||
0234cb7c | 529 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
530 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
531 | ||
532 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
533 | effect this we maintain a stack of saved characters that we've smashed | |
534 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 535 | assembler instruction). */ |
252b5132 | 536 | static char save_stack[32]; |
ce8a8b2f | 537 | static char *save_stack_p; |
252b5132 RH |
538 | #define END_STRING_AND_SAVE(s) \ |
539 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
540 | #define RESTORE_END_STRING(s) \ | |
541 | do { *(s) = *--save_stack_p; } while (0) | |
542 | ||
47926f60 | 543 | /* The instruction we're assembling. */ |
252b5132 RH |
544 | static i386_insn i; |
545 | ||
546 | /* Possible templates for current insn. */ | |
547 | static const templates *current_templates; | |
548 | ||
31b2323c L |
549 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
550 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
551 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 552 | |
47926f60 | 553 | /* Current operand we are working on. */ |
ee86248c | 554 | static int this_operand = -1; |
252b5132 | 555 | |
3e73aa7c JH |
556 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
557 | these. */ | |
558 | ||
559 | enum flag_code { | |
560 | CODE_32BIT, | |
561 | CODE_16BIT, | |
562 | CODE_64BIT }; | |
563 | ||
564 | static enum flag_code flag_code; | |
4fa24527 | 565 | static unsigned int object_64bit; |
862be3fb | 566 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 567 | static int use_rela_relocations = 0; |
e379e5f3 L |
568 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
569 | static const char *tls_get_addr; | |
3e73aa7c | 570 | |
7af8ed2d NC |
571 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
572 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
573 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
574 | ||
351f65ca L |
575 | /* The ELF ABI to use. */ |
576 | enum x86_elf_abi | |
577 | { | |
578 | I386_ABI, | |
7f56bc95 L |
579 | X86_64_ABI, |
580 | X86_64_X32_ABI | |
351f65ca L |
581 | }; |
582 | ||
583 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 584 | #endif |
351f65ca | 585 | |
167ad85b TG |
586 | #if defined (TE_PE) || defined (TE_PEP) |
587 | /* Use big object file format. */ | |
588 | static int use_big_obj = 0; | |
589 | #endif | |
590 | ||
8dcea932 L |
591 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
592 | /* 1 if generating code for a shared library. */ | |
593 | static int shared = 0; | |
594 | #endif | |
595 | ||
47926f60 KH |
596 | /* 1 for intel syntax, |
597 | 0 if att syntax. */ | |
598 | static int intel_syntax = 0; | |
252b5132 | 599 | |
4b5aaf5f L |
600 | static enum x86_64_isa |
601 | { | |
602 | amd64 = 1, /* AMD64 ISA. */ | |
603 | intel64 /* Intel64 ISA. */ | |
604 | } isa64; | |
e89c5eaa | 605 | |
1efbbeb4 L |
606 | /* 1 for intel mnemonic, |
607 | 0 if att mnemonic. */ | |
608 | static int intel_mnemonic = !SYSV386_COMPAT; | |
609 | ||
a60de03c JB |
610 | /* 1 if pseudo registers are permitted. */ |
611 | static int allow_pseudo_reg = 0; | |
612 | ||
47926f60 KH |
613 | /* 1 if register prefix % not required. */ |
614 | static int allow_naked_reg = 0; | |
252b5132 | 615 | |
33eaf5de | 616 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
617 | instructions supporting it, even if this prefix wasn't specified |
618 | explicitly. */ | |
619 | static int add_bnd_prefix = 0; | |
620 | ||
ba104c83 | 621 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
622 | static int allow_index_reg = 0; |
623 | ||
d022bddd IT |
624 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
625 | specified explicitly. */ | |
626 | static int omit_lock_prefix = 0; | |
627 | ||
e4e00185 AS |
628 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
629 | "lock addl $0, (%{re}sp)". */ | |
630 | static int avoid_fence = 0; | |
631 | ||
ae531041 L |
632 | /* 1 if lfence should be inserted after every load. */ |
633 | static int lfence_after_load = 0; | |
634 | ||
635 | /* Non-zero if lfence should be inserted before indirect branch. */ | |
636 | static enum lfence_before_indirect_branch_kind | |
637 | { | |
638 | lfence_branch_none = 0, | |
639 | lfence_branch_register, | |
640 | lfence_branch_memory, | |
641 | lfence_branch_all | |
642 | } | |
643 | lfence_before_indirect_branch; | |
644 | ||
645 | /* Non-zero if lfence should be inserted before ret. */ | |
646 | static enum lfence_before_ret_kind | |
647 | { | |
648 | lfence_before_ret_none = 0, | |
649 | lfence_before_ret_not, | |
a09f656b | 650 | lfence_before_ret_or, |
651 | lfence_before_ret_shl | |
ae531041 L |
652 | } |
653 | lfence_before_ret; | |
654 | ||
655 | /* Types of previous instruction is .byte or prefix. */ | |
e379e5f3 L |
656 | static struct |
657 | { | |
658 | segT seg; | |
659 | const char *file; | |
660 | const char *name; | |
661 | unsigned int line; | |
662 | enum last_insn_kind | |
663 | { | |
664 | last_insn_other = 0, | |
665 | last_insn_directive, | |
666 | last_insn_prefix | |
667 | } kind; | |
668 | } last_insn; | |
669 | ||
0cb4071e L |
670 | /* 1 if the assembler should generate relax relocations. */ |
671 | ||
672 | static int generate_relax_relocations | |
673 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
674 | ||
7bab8ab5 | 675 | static enum check_kind |
daf50ae7 | 676 | { |
7bab8ab5 JB |
677 | check_none = 0, |
678 | check_warning, | |
679 | check_error | |
daf50ae7 | 680 | } |
7bab8ab5 | 681 | sse_check, operand_check = check_warning; |
daf50ae7 | 682 | |
e379e5f3 L |
683 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
684 | static int align_branch_power = 0; | |
685 | ||
686 | /* Types of branches to align. */ | |
687 | enum align_branch_kind | |
688 | { | |
689 | align_branch_none = 0, | |
690 | align_branch_jcc = 1, | |
691 | align_branch_fused = 2, | |
692 | align_branch_jmp = 3, | |
693 | align_branch_call = 4, | |
694 | align_branch_indirect = 5, | |
695 | align_branch_ret = 6 | |
696 | }; | |
697 | ||
698 | /* Type bits of branches to align. */ | |
699 | enum align_branch_bit | |
700 | { | |
701 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
702 | align_branch_fused_bit = 1 << align_branch_fused, | |
703 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
704 | align_branch_call_bit = 1 << align_branch_call, | |
705 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
706 | align_branch_ret_bit = 1 << align_branch_ret | |
707 | }; | |
708 | ||
709 | static unsigned int align_branch = (align_branch_jcc_bit | |
710 | | align_branch_fused_bit | |
711 | | align_branch_jmp_bit); | |
712 | ||
79d72f45 HL |
713 | /* Types of condition jump used by macro-fusion. */ |
714 | enum mf_jcc_kind | |
715 | { | |
716 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
717 | mf_jcc_jc, /* base opcode 0x72 */ | |
718 | mf_jcc_je, /* base opcode 0x74 */ | |
719 | mf_jcc_jna, /* base opcode 0x76 */ | |
720 | mf_jcc_js, /* base opcode 0x78 */ | |
721 | mf_jcc_jp, /* base opcode 0x7a */ | |
722 | mf_jcc_jl, /* base opcode 0x7c */ | |
723 | mf_jcc_jle, /* base opcode 0x7e */ | |
724 | }; | |
725 | ||
726 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
727 | enum mf_cmp_kind | |
728 | { | |
729 | mf_cmp_test_and, /* test/cmp */ | |
730 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
731 | mf_cmp_incdec /* inc/dec */ | |
732 | }; | |
733 | ||
e379e5f3 L |
734 | /* The maximum padding size for fused jcc. CMP like instruction can |
735 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
736 | prefixes. */ | |
737 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
738 | ||
739 | /* The maximum number of prefixes added for an instruction. */ | |
740 | static unsigned int align_branch_prefix_size = 5; | |
741 | ||
b6f8c7c4 L |
742 | /* Optimization: |
743 | 1. Clear the REX_W bit with register operand if possible. | |
744 | 2. Above plus use 128bit vector instruction to clear the full vector | |
745 | register. | |
746 | */ | |
747 | static int optimize = 0; | |
748 | ||
749 | /* Optimization: | |
750 | 1. Clear the REX_W bit with register operand if possible. | |
751 | 2. Above plus use 128bit vector instruction to clear the full vector | |
752 | register. | |
753 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
754 | "testb $imm7,%r8". | |
755 | */ | |
756 | static int optimize_for_space = 0; | |
757 | ||
2ca3ace5 L |
758 | /* Register prefix used for error message. */ |
759 | static const char *register_prefix = "%"; | |
760 | ||
47926f60 KH |
761 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
762 | leave, push, and pop instructions so that gcc has the same stack | |
763 | frame as in 32 bit mode. */ | |
764 | static char stackop_size = '\0'; | |
eecb386c | 765 | |
12b55ccc L |
766 | /* Non-zero to optimize code alignment. */ |
767 | int optimize_align_code = 1; | |
768 | ||
47926f60 KH |
769 | /* Non-zero to quieten some warnings. */ |
770 | static int quiet_warnings = 0; | |
a38cf1db | 771 | |
47926f60 KH |
772 | /* CPU name. */ |
773 | static const char *cpu_arch_name = NULL; | |
6305a203 | 774 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 775 | |
47926f60 | 776 | /* CPU feature flags. */ |
40fb9820 L |
777 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
778 | ||
ccc9c027 L |
779 | /* If we have selected a cpu we are generating instructions for. */ |
780 | static int cpu_arch_tune_set = 0; | |
781 | ||
9103f4f4 | 782 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 783 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
784 | |
785 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 786 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 787 | |
ccc9c027 | 788 | /* CPU instruction set architecture used. */ |
fbf3f584 | 789 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 790 | |
9103f4f4 | 791 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 792 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 793 | |
fddf5b5b AM |
794 | /* If set, conditional jumps are not automatically promoted to handle |
795 | larger than a byte offset. */ | |
796 | static unsigned int no_cond_jump_promotion = 0; | |
797 | ||
c0f3af97 L |
798 | /* Encode SSE instructions with VEX prefix. */ |
799 | static unsigned int sse2avx; | |
800 | ||
539f890d L |
801 | /* Encode scalar AVX instructions with specific vector length. */ |
802 | static enum | |
803 | { | |
804 | vex128 = 0, | |
805 | vex256 | |
806 | } avxscalar; | |
807 | ||
03751133 L |
808 | /* Encode VEX WIG instructions with specific vex.w. */ |
809 | static enum | |
810 | { | |
811 | vexw0 = 0, | |
812 | vexw1 | |
813 | } vexwig; | |
814 | ||
43234a1e L |
815 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
816 | static enum | |
817 | { | |
818 | evexl128 = 0, | |
819 | evexl256, | |
820 | evexl512 | |
821 | } evexlig; | |
822 | ||
823 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
824 | static enum | |
825 | { | |
826 | evexw0 = 0, | |
827 | evexw1 | |
828 | } evexwig; | |
829 | ||
d3d3c6db IT |
830 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
831 | static enum rc_type evexrcig = rne; | |
832 | ||
29b0f896 | 833 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 834 | static symbolS *GOT_symbol; |
29b0f896 | 835 | |
a4447b93 RH |
836 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
837 | unsigned int x86_dwarf2_return_column; | |
838 | ||
839 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
840 | int x86_cie_data_alignment; | |
841 | ||
252b5132 | 842 | /* Interface to relax_segment. |
fddf5b5b AM |
843 | There are 3 major relax states for 386 jump insns because the |
844 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
845 | figuring out what sort of jump to choose to reach a given label. |
846 | ||
847 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
848 | branches which are handled by md_estimate_size_before_relax() and | |
849 | i386_generic_table_relax_frag(). */ | |
252b5132 | 850 | |
47926f60 | 851 | /* Types. */ |
93c2a809 AM |
852 | #define UNCOND_JUMP 0 |
853 | #define COND_JUMP 1 | |
854 | #define COND_JUMP86 2 | |
e379e5f3 L |
855 | #define BRANCH_PADDING 3 |
856 | #define BRANCH_PREFIX 4 | |
857 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 858 | |
47926f60 | 859 | /* Sizes. */ |
252b5132 RH |
860 | #define CODE16 1 |
861 | #define SMALL 0 | |
29b0f896 | 862 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 863 | #define BIG 2 |
29b0f896 | 864 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
865 | |
866 | #ifndef INLINE | |
867 | #ifdef __GNUC__ | |
868 | #define INLINE __inline__ | |
869 | #else | |
870 | #define INLINE | |
871 | #endif | |
872 | #endif | |
873 | ||
fddf5b5b AM |
874 | #define ENCODE_RELAX_STATE(type, size) \ |
875 | ((relax_substateT) (((type) << 2) | (size))) | |
876 | #define TYPE_FROM_RELAX_STATE(s) \ | |
877 | ((s) >> 2) | |
878 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
879 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
880 | |
881 | /* This table is used by relax_frag to promote short jumps to long | |
882 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
883 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
884 | don't allow a short jump in a 32 bit code segment to be promoted to | |
885 | a 16 bit offset jump because it's slower (requires data size | |
886 | prefix), and doesn't work, unless the destination is in the bottom | |
887 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
888 | ||
889 | const relax_typeS md_relax_table[] = | |
890 | { | |
24eab124 AM |
891 | /* The fields are: |
892 | 1) most positive reach of this state, | |
893 | 2) most negative reach of this state, | |
93c2a809 | 894 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 895 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 896 | |
fddf5b5b | 897 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
898 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
899 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
900 | /* dword jmp adds 4 bytes to frag: | |
901 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 902 | {0, 0, 4, 0}, |
93c2a809 AM |
903 | /* word jmp adds 2 byte2 to frag: |
904 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
905 | {0, 0, 2, 0}, |
906 | ||
93c2a809 AM |
907 | /* COND_JUMP states. */ |
908 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
909 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
910 | /* dword conditionals adds 5 bytes to frag: | |
911 | 1 extra opcode byte, 4 displacement bytes. */ | |
912 | {0, 0, 5, 0}, | |
fddf5b5b | 913 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
914 | 1 extra opcode byte, 2 displacement bytes. */ |
915 | {0, 0, 3, 0}, | |
916 | ||
917 | /* COND_JUMP86 states. */ | |
918 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
919 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
920 | /* dword conditionals adds 5 bytes to frag: | |
921 | 1 extra opcode byte, 4 displacement bytes. */ | |
922 | {0, 0, 5, 0}, | |
923 | /* word conditionals add 4 bytes to frag: | |
924 | 1 displacement byte and a 3 byte long branch insn. */ | |
925 | {0, 0, 4, 0} | |
252b5132 RH |
926 | }; |
927 | ||
9103f4f4 L |
928 | static const arch_entry cpu_arch[] = |
929 | { | |
89507696 JB |
930 | /* Do not replace the first two entries - i386_target_format() |
931 | relies on them being there in this order. */ | |
8a2c8fef | 932 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 933 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 934 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 935 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 936 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 937 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 938 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 939 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 940 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 941 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 942 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 943 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 944 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 945 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 946 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 947 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 948 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 949 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 950 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 951 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 952 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 953 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 954 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 955 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 956 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 957 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 958 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 959 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 960 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 961 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 962 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 963 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 964 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 965 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 966 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 967 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 968 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 969 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 970 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 971 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 972 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 973 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 974 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 975 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 976 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 977 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 978 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 979 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 980 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 981 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 982 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 983 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 984 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 985 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 986 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 987 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 988 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 989 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 990 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 991 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 992 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 993 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 994 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 995 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 996 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 997 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 998 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 999 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 1000 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 1001 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 1002 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 1003 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
1004 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
1005 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 1006 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 1007 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 1008 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 1009 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 1010 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 1011 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 1012 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 1013 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 1014 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 1015 | CPU_387_FLAGS, 0 }, |
1848e567 L |
1016 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
1017 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
1018 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
1019 | CPU_CMOV_FLAGS, 0 }, | |
1020 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
1021 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 1022 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1023 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 1024 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 1025 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 1026 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1027 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 1028 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1029 | CPU_SSE3_FLAGS, 0 }, |
af5c13b0 L |
1030 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
1031 | CPU_SSE4A_FLAGS, 0 }, | |
8a2c8fef | 1032 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1033 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 1034 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1035 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 1036 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1037 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1038 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1039 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1040 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1041 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 1042 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1043 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 1044 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 1045 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 1046 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1047 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 1048 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 1049 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 1050 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 1051 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 1052 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 1053 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 1054 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1055 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 1056 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 1057 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 1058 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1059 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 1060 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 1061 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 1062 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1063 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 1064 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 1065 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 1066 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1067 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 1068 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 1069 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 1070 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 1071 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 1072 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 1073 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 1074 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1075 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 1076 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1077 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 1078 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 1079 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 1080 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1081 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 1082 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 1083 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 1084 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1085 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 1086 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1087 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 1088 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1089 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 1090 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1091 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 1092 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1093 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 1094 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 1095 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 1096 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 1097 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 1098 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 1099 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 1100 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1101 | CPU_LZCNT_FLAGS, 0 }, |
272a84b1 L |
1102 | { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN, |
1103 | CPU_POPCNT_FLAGS, 0 }, | |
42164a71 | 1104 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 1105 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 1106 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1107 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 1108 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1109 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 1110 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 1111 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 1112 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1113 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 1114 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 1115 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 1116 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1117 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1118 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1119 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1120 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1121 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1122 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1123 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1124 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1125 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1126 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1127 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1128 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1129 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1130 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1131 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1132 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1133 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1134 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1135 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1136 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1137 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1138 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1139 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1140 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1141 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1142 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1143 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1144 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1145 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1146 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1147 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1148 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1149 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1150 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1151 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1152 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1153 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1154 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1155 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1156 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1157 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1158 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1159 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1160 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1161 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1162 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1163 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1164 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1165 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1166 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1167 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1168 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1169 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1170 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1171 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1172 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1173 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1174 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1175 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1176 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1177 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1178 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1179 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1180 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1181 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1182 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1183 | CPU_IBT_FLAGS, 0 }, | |
1184 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1185 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1186 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1187 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1188 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1189 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1190 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1191 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1192 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1193 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1194 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1195 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1196 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1197 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1198 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1199 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1200 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1201 | CPU_MOVDIRI_FLAGS, 0 }, | |
1202 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1203 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1204 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1205 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1206 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1207 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
dd455cf5 L |
1208 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1209 | CPU_ENQCMD_FLAGS, 0 }, | |
4b27d27c L |
1210 | { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN, |
1211 | CPU_SERIALIZE_FLAGS, 0 }, | |
142861df JB |
1212 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1213 | CPU_RDPRU_FLAGS, 0 }, | |
1214 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1215 | CPU_MCOMMIT_FLAGS, 0 }, | |
a847e322 JB |
1216 | { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN, |
1217 | CPU_SEV_ES_FLAGS, 0 }, | |
bb651e8b CL |
1218 | { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN, |
1219 | CPU_TSXLDTRK_FLAGS, 0 }, | |
293f5f65 L |
1220 | }; |
1221 | ||
1222 | static const noarch_entry cpu_noarch[] = | |
1223 | { | |
1224 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1225 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1226 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1227 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1228 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1229 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1230 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1231 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1232 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1233 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
af5c13b0 | 1234 | { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS }, |
1848e567 L |
1235 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, |
1236 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1237 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
af5c13b0 | 1238 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, |
293f5f65 | 1239 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1240 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1241 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1242 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1243 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1244 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1245 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1246 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1247 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1248 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1249 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1250 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1251 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1252 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1253 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1254 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1255 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1256 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1257 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1258 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1259 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1260 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
9186c494 | 1261 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS }, |
dd455cf5 | 1262 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
4b27d27c | 1263 | { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS }, |
bb651e8b | 1264 | { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS }, |
e413e4e9 AM |
1265 | }; |
1266 | ||
704209c0 | 1267 | #ifdef I386COFF |
a6c24e68 NC |
1268 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1269 | is allowed to be optional. */ | |
1270 | ||
1271 | static symbolS * | |
1272 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1273 | { | |
1274 | addressT align = 0; | |
1275 | ||
1276 | SKIP_WHITESPACE (); | |
1277 | ||
7ab9ffdd | 1278 | if (needs_align |
a6c24e68 NC |
1279 | && *input_line_pointer == ',') |
1280 | { | |
1281 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1282 | |
a6c24e68 NC |
1283 | if (align == (addressT) -1) |
1284 | return NULL; | |
1285 | } | |
1286 | else | |
1287 | { | |
1288 | if (size >= 8) | |
1289 | align = 3; | |
1290 | else if (size >= 4) | |
1291 | align = 2; | |
1292 | else if (size >= 2) | |
1293 | align = 1; | |
1294 | else | |
1295 | align = 0; | |
1296 | } | |
1297 | ||
1298 | bss_alloc (symbolP, size, align); | |
1299 | return symbolP; | |
1300 | } | |
1301 | ||
704209c0 | 1302 | static void |
a6c24e68 NC |
1303 | pe_lcomm (int needs_align) |
1304 | { | |
1305 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1306 | } | |
704209c0 | 1307 | #endif |
a6c24e68 | 1308 | |
29b0f896 AM |
1309 | const pseudo_typeS md_pseudo_table[] = |
1310 | { | |
1311 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1312 | {"align", s_align_bytes, 0}, | |
1313 | #else | |
1314 | {"align", s_align_ptwo, 0}, | |
1315 | #endif | |
1316 | {"arch", set_cpu_arch, 0}, | |
1317 | #ifndef I386COFF | |
1318 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1319 | #else |
1320 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1321 | #endif |
1322 | {"ffloat", float_cons, 'f'}, | |
1323 | {"dfloat", float_cons, 'd'}, | |
1324 | {"tfloat", float_cons, 'x'}, | |
1325 | {"value", cons, 2}, | |
d182319b | 1326 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1327 | {"noopt", s_ignore, 0}, |
1328 | {"optim", s_ignore, 0}, | |
1329 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1330 | {"code16", set_code_flag, CODE_16BIT}, | |
1331 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1332 | #ifdef BFD64 |
29b0f896 | 1333 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1334 | #endif |
29b0f896 AM |
1335 | {"intel_syntax", set_intel_syntax, 1}, |
1336 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1337 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1338 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1339 | {"allow_index_reg", set_allow_index_reg, 1}, |
1340 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1341 | {"sse_check", set_check, 0}, |
1342 | {"operand_check", set_check, 1}, | |
3b22753a L |
1343 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1344 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1345 | #else |
68d20676 | 1346 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1347 | {"loc", dwarf2_directive_loc, 0}, |
1348 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1349 | #endif |
6482c264 NC |
1350 | #ifdef TE_PE |
1351 | {"secrel32", pe_directive_secrel, 0}, | |
1352 | #endif | |
29b0f896 AM |
1353 | {0, 0, 0} |
1354 | }; | |
1355 | ||
1356 | /* For interface with expression (). */ | |
1357 | extern char *input_line_pointer; | |
1358 | ||
1359 | /* Hash table for instruction mnemonic lookup. */ | |
1360 | static struct hash_control *op_hash; | |
1361 | ||
1362 | /* Hash table for register lookup. */ | |
1363 | static struct hash_control *reg_hash; | |
1364 | \f | |
ce8a8b2f AM |
1365 | /* Various efficient no-op patterns for aligning code labels. |
1366 | Note: Don't try to assemble the instructions in the comments. | |
1367 | 0L and 0w are not legal. */ | |
62a02d25 L |
1368 | static const unsigned char f32_1[] = |
1369 | {0x90}; /* nop */ | |
1370 | static const unsigned char f32_2[] = | |
1371 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1372 | static const unsigned char f32_3[] = | |
1373 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1374 | static const unsigned char f32_4[] = | |
1375 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1376 | static const unsigned char f32_6[] = |
1377 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1378 | static const unsigned char f32_7[] = | |
1379 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1380 | static const unsigned char f16_3[] = |
3ae729d5 | 1381 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1382 | static const unsigned char f16_4[] = |
3ae729d5 L |
1383 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1384 | static const unsigned char jump_disp8[] = | |
1385 | {0xeb}; /* jmp disp8 */ | |
1386 | static const unsigned char jump32_disp32[] = | |
1387 | {0xe9}; /* jmp disp32 */ | |
1388 | static const unsigned char jump16_disp32[] = | |
1389 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1390 | /* 32-bit NOPs patterns. */ |
1391 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1392 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1393 | }; |
1394 | /* 16-bit NOPs patterns. */ | |
1395 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1396 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1397 | }; |
1398 | /* nopl (%[re]ax) */ | |
1399 | static const unsigned char alt_3[] = | |
1400 | {0x0f,0x1f,0x00}; | |
1401 | /* nopl 0(%[re]ax) */ | |
1402 | static const unsigned char alt_4[] = | |
1403 | {0x0f,0x1f,0x40,0x00}; | |
1404 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1405 | static const unsigned char alt_5[] = | |
1406 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1407 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1408 | static const unsigned char alt_6[] = | |
1409 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1410 | /* nopl 0L(%[re]ax) */ | |
1411 | static const unsigned char alt_7[] = | |
1412 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1413 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1414 | static const unsigned char alt_8[] = | |
1415 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1416 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1417 | static const unsigned char alt_9[] = | |
1418 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1419 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1420 | static const unsigned char alt_10[] = | |
1421 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1422 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1423 | static const unsigned char alt_11[] = | |
1424 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1425 | /* 32-bit and 64-bit NOPs patterns. */ |
1426 | static const unsigned char *const alt_patt[] = { | |
1427 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1428 | alt_9, alt_10, alt_11 |
62a02d25 L |
1429 | }; |
1430 | ||
1431 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1432 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1433 | ||
1434 | static void | |
1435 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1436 | int count, int max_single_nop_size) | |
1437 | ||
1438 | { | |
3ae729d5 L |
1439 | /* Place the longer NOP first. */ |
1440 | int last; | |
1441 | int offset; | |
3076e594 NC |
1442 | const unsigned char *nops; |
1443 | ||
1444 | if (max_single_nop_size < 1) | |
1445 | { | |
1446 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1447 | max_single_nop_size); | |
1448 | return; | |
1449 | } | |
1450 | ||
1451 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1452 | |
1453 | /* Use the smaller one if the requsted one isn't available. */ | |
1454 | if (nops == NULL) | |
62a02d25 | 1455 | { |
3ae729d5 L |
1456 | max_single_nop_size--; |
1457 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1458 | } |
1459 | ||
3ae729d5 L |
1460 | last = count % max_single_nop_size; |
1461 | ||
1462 | count -= last; | |
1463 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1464 | memcpy (where + offset, nops, max_single_nop_size); | |
1465 | ||
1466 | if (last) | |
1467 | { | |
1468 | nops = patt[last - 1]; | |
1469 | if (nops == NULL) | |
1470 | { | |
1471 | /* Use the smaller one plus one-byte NOP if the needed one | |
1472 | isn't available. */ | |
1473 | last--; | |
1474 | nops = patt[last - 1]; | |
1475 | memcpy (where + offset, nops, last); | |
1476 | where[offset + last] = *patt[0]; | |
1477 | } | |
1478 | else | |
1479 | memcpy (where + offset, nops, last); | |
1480 | } | |
62a02d25 L |
1481 | } |
1482 | ||
3ae729d5 L |
1483 | static INLINE int |
1484 | fits_in_imm7 (offsetT num) | |
1485 | { | |
1486 | return (num & 0x7f) == num; | |
1487 | } | |
1488 | ||
1489 | static INLINE int | |
1490 | fits_in_imm31 (offsetT num) | |
1491 | { | |
1492 | return (num & 0x7fffffff) == num; | |
1493 | } | |
62a02d25 L |
1494 | |
1495 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1496 | single NOP instruction LIMIT. */ | |
1497 | ||
1498 | void | |
3ae729d5 | 1499 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1500 | { |
3ae729d5 | 1501 | const unsigned char *const *patt = NULL; |
62a02d25 | 1502 | int max_single_nop_size; |
3ae729d5 L |
1503 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1504 | int max_number_of_nops; | |
62a02d25 | 1505 | |
3ae729d5 | 1506 | switch (fragP->fr_type) |
62a02d25 | 1507 | { |
3ae729d5 L |
1508 | case rs_fill_nop: |
1509 | case rs_align_code: | |
1510 | break; | |
e379e5f3 L |
1511 | case rs_machine_dependent: |
1512 | /* Allow NOP padding for jumps and calls. */ | |
1513 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1514 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1515 | break; | |
1516 | /* Fall through. */ | |
3ae729d5 | 1517 | default: |
62a02d25 L |
1518 | return; |
1519 | } | |
1520 | ||
ccc9c027 L |
1521 | /* We need to decide which NOP sequence to use for 32bit and |
1522 | 64bit. When -mtune= is used: | |
4eed87de | 1523 | |
76bc74dc L |
1524 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1525 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1526 | 2. For the rest, alt_patt will be used. |
1527 | ||
1528 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1529 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1530 | be used. |
ccc9c027 L |
1531 | |
1532 | When -march= or .arch is used, we can't use anything beyond | |
1533 | cpu_arch_isa_flags. */ | |
1534 | ||
1535 | if (flag_code == CODE_16BIT) | |
1536 | { | |
3ae729d5 L |
1537 | patt = f16_patt; |
1538 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1539 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1540 | max_number_of_nops = 2; | |
252b5132 | 1541 | } |
33fef721 | 1542 | else |
ccc9c027 | 1543 | { |
fbf3f584 | 1544 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1545 | { |
1546 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1547 | switch (cpu_arch_tune) | |
1548 | { | |
1549 | case PROCESSOR_UNKNOWN: | |
1550 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1551 | optimize with nops. */ |
1552 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1553 | patt = alt_patt; |
ccc9c027 L |
1554 | else |
1555 | patt = f32_patt; | |
1556 | break; | |
ccc9c027 L |
1557 | case PROCESSOR_PENTIUM4: |
1558 | case PROCESSOR_NOCONA: | |
ef05d495 | 1559 | case PROCESSOR_CORE: |
76bc74dc | 1560 | case PROCESSOR_CORE2: |
bd5295b2 | 1561 | case PROCESSOR_COREI7: |
3632d14b | 1562 | case PROCESSOR_L1OM: |
7a9068fe | 1563 | case PROCESSOR_K1OM: |
76bc74dc | 1564 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1565 | case PROCESSOR_K6: |
1566 | case PROCESSOR_ATHLON: | |
1567 | case PROCESSOR_K8: | |
4eed87de | 1568 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1569 | case PROCESSOR_BD: |
029f3522 | 1570 | case PROCESSOR_ZNVER: |
7b458c12 | 1571 | case PROCESSOR_BT: |
80b8656c | 1572 | patt = alt_patt; |
ccc9c027 | 1573 | break; |
76bc74dc | 1574 | case PROCESSOR_I386: |
ccc9c027 L |
1575 | case PROCESSOR_I486: |
1576 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1577 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1578 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1579 | case PROCESSOR_GENERIC32: |
1580 | patt = f32_patt; | |
1581 | break; | |
4eed87de | 1582 | } |
ccc9c027 L |
1583 | } |
1584 | else | |
1585 | { | |
fbf3f584 | 1586 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1587 | { |
1588 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1589 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1590 | PROCESSOR_UNKNOWN. */ |
1591 | abort (); | |
1592 | break; | |
1593 | ||
76bc74dc | 1594 | case PROCESSOR_I386: |
ccc9c027 L |
1595 | case PROCESSOR_I486: |
1596 | case PROCESSOR_PENTIUM: | |
81486035 | 1597 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1598 | case PROCESSOR_K6: |
1599 | case PROCESSOR_ATHLON: | |
1600 | case PROCESSOR_K8: | |
4eed87de | 1601 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1602 | case PROCESSOR_BD: |
029f3522 | 1603 | case PROCESSOR_ZNVER: |
7b458c12 | 1604 | case PROCESSOR_BT: |
ccc9c027 L |
1605 | case PROCESSOR_GENERIC32: |
1606 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1607 | with nops. */ |
1608 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1609 | patt = alt_patt; |
ccc9c027 L |
1610 | else |
1611 | patt = f32_patt; | |
1612 | break; | |
76bc74dc L |
1613 | case PROCESSOR_PENTIUMPRO: |
1614 | case PROCESSOR_PENTIUM4: | |
1615 | case PROCESSOR_NOCONA: | |
1616 | case PROCESSOR_CORE: | |
ef05d495 | 1617 | case PROCESSOR_CORE2: |
bd5295b2 | 1618 | case PROCESSOR_COREI7: |
3632d14b | 1619 | case PROCESSOR_L1OM: |
7a9068fe | 1620 | case PROCESSOR_K1OM: |
22109423 | 1621 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1622 | patt = alt_patt; |
ccc9c027 L |
1623 | else |
1624 | patt = f32_patt; | |
1625 | break; | |
1626 | case PROCESSOR_GENERIC64: | |
80b8656c | 1627 | patt = alt_patt; |
ccc9c027 | 1628 | break; |
4eed87de | 1629 | } |
ccc9c027 L |
1630 | } |
1631 | ||
76bc74dc L |
1632 | if (patt == f32_patt) |
1633 | { | |
3ae729d5 L |
1634 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1635 | /* Limit number of NOPs to 2 for older processors. */ | |
1636 | max_number_of_nops = 2; | |
76bc74dc L |
1637 | } |
1638 | else | |
1639 | { | |
3ae729d5 L |
1640 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1641 | /* Limit number of NOPs to 7 for newer processors. */ | |
1642 | max_number_of_nops = 7; | |
1643 | } | |
1644 | } | |
1645 | ||
1646 | if (limit == 0) | |
1647 | limit = max_single_nop_size; | |
1648 | ||
1649 | if (fragP->fr_type == rs_fill_nop) | |
1650 | { | |
1651 | /* Output NOPs for .nop directive. */ | |
1652 | if (limit > max_single_nop_size) | |
1653 | { | |
1654 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1655 | _("invalid single nop size: %d " | |
1656 | "(expect within [0, %d])"), | |
1657 | limit, max_single_nop_size); | |
1658 | return; | |
1659 | } | |
1660 | } | |
e379e5f3 | 1661 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1662 | fragP->fr_var = count; |
1663 | ||
1664 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1665 | { | |
1666 | /* Generate jump over NOPs. */ | |
1667 | offsetT disp = count - 2; | |
1668 | if (fits_in_imm7 (disp)) | |
1669 | { | |
1670 | /* Use "jmp disp8" if possible. */ | |
1671 | count = disp; | |
1672 | where[0] = jump_disp8[0]; | |
1673 | where[1] = count; | |
1674 | where += 2; | |
1675 | } | |
1676 | else | |
1677 | { | |
1678 | unsigned int size_of_jump; | |
1679 | ||
1680 | if (flag_code == CODE_16BIT) | |
1681 | { | |
1682 | where[0] = jump16_disp32[0]; | |
1683 | where[1] = jump16_disp32[1]; | |
1684 | size_of_jump = 2; | |
1685 | } | |
1686 | else | |
1687 | { | |
1688 | where[0] = jump32_disp32[0]; | |
1689 | size_of_jump = 1; | |
1690 | } | |
1691 | ||
1692 | count -= size_of_jump + 4; | |
1693 | if (!fits_in_imm31 (count)) | |
1694 | { | |
1695 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1696 | _("jump over nop padding out of range")); | |
1697 | return; | |
1698 | } | |
1699 | ||
1700 | md_number_to_chars (where + size_of_jump, count, 4); | |
1701 | where += size_of_jump + 4; | |
76bc74dc | 1702 | } |
ccc9c027 | 1703 | } |
3ae729d5 L |
1704 | |
1705 | /* Generate multiple NOPs. */ | |
1706 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1707 | } |
1708 | ||
c6fb90c8 | 1709 | static INLINE int |
0dfbf9d7 | 1710 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1711 | { |
0dfbf9d7 | 1712 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1713 | { |
1714 | case 3: | |
0dfbf9d7 | 1715 | if (x->array[2]) |
c6fb90c8 | 1716 | return 0; |
1a0670f3 | 1717 | /* Fall through. */ |
c6fb90c8 | 1718 | case 2: |
0dfbf9d7 | 1719 | if (x->array[1]) |
c6fb90c8 | 1720 | return 0; |
1a0670f3 | 1721 | /* Fall through. */ |
c6fb90c8 | 1722 | case 1: |
0dfbf9d7 | 1723 | return !x->array[0]; |
c6fb90c8 L |
1724 | default: |
1725 | abort (); | |
1726 | } | |
40fb9820 L |
1727 | } |
1728 | ||
c6fb90c8 | 1729 | static INLINE void |
0dfbf9d7 | 1730 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1731 | { |
0dfbf9d7 | 1732 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1733 | { |
1734 | case 3: | |
0dfbf9d7 | 1735 | x->array[2] = v; |
1a0670f3 | 1736 | /* Fall through. */ |
c6fb90c8 | 1737 | case 2: |
0dfbf9d7 | 1738 | x->array[1] = v; |
1a0670f3 | 1739 | /* Fall through. */ |
c6fb90c8 | 1740 | case 1: |
0dfbf9d7 | 1741 | x->array[0] = v; |
1a0670f3 | 1742 | /* Fall through. */ |
c6fb90c8 L |
1743 | break; |
1744 | default: | |
1745 | abort (); | |
1746 | } | |
bab6aec1 JB |
1747 | |
1748 | x->bitfield.class = ClassNone; | |
75e5731b | 1749 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1750 | } |
40fb9820 | 1751 | |
c6fb90c8 | 1752 | static INLINE int |
0dfbf9d7 L |
1753 | operand_type_equal (const union i386_operand_type *x, |
1754 | const union i386_operand_type *y) | |
c6fb90c8 | 1755 | { |
0dfbf9d7 | 1756 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1757 | { |
1758 | case 3: | |
0dfbf9d7 | 1759 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1760 | return 0; |
1a0670f3 | 1761 | /* Fall through. */ |
c6fb90c8 | 1762 | case 2: |
0dfbf9d7 | 1763 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1764 | return 0; |
1a0670f3 | 1765 | /* Fall through. */ |
c6fb90c8 | 1766 | case 1: |
0dfbf9d7 | 1767 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1768 | break; |
1769 | default: | |
1770 | abort (); | |
1771 | } | |
1772 | } | |
40fb9820 | 1773 | |
0dfbf9d7 L |
1774 | static INLINE int |
1775 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1776 | { | |
1777 | switch (ARRAY_SIZE(x->array)) | |
1778 | { | |
53467f57 IT |
1779 | case 4: |
1780 | if (x->array[3]) | |
1781 | return 0; | |
1782 | /* Fall through. */ | |
0dfbf9d7 L |
1783 | case 3: |
1784 | if (x->array[2]) | |
1785 | return 0; | |
1a0670f3 | 1786 | /* Fall through. */ |
0dfbf9d7 L |
1787 | case 2: |
1788 | if (x->array[1]) | |
1789 | return 0; | |
1a0670f3 | 1790 | /* Fall through. */ |
0dfbf9d7 L |
1791 | case 1: |
1792 | return !x->array[0]; | |
1793 | default: | |
1794 | abort (); | |
1795 | } | |
1796 | } | |
1797 | ||
0dfbf9d7 L |
1798 | static INLINE int |
1799 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1800 | const union i386_cpu_flags *y) | |
1801 | { | |
1802 | switch (ARRAY_SIZE(x->array)) | |
1803 | { | |
53467f57 IT |
1804 | case 4: |
1805 | if (x->array[3] != y->array[3]) | |
1806 | return 0; | |
1807 | /* Fall through. */ | |
0dfbf9d7 L |
1808 | case 3: |
1809 | if (x->array[2] != y->array[2]) | |
1810 | return 0; | |
1a0670f3 | 1811 | /* Fall through. */ |
0dfbf9d7 L |
1812 | case 2: |
1813 | if (x->array[1] != y->array[1]) | |
1814 | return 0; | |
1a0670f3 | 1815 | /* Fall through. */ |
0dfbf9d7 L |
1816 | case 1: |
1817 | return x->array[0] == y->array[0]; | |
1818 | break; | |
1819 | default: | |
1820 | abort (); | |
1821 | } | |
1822 | } | |
c6fb90c8 L |
1823 | |
1824 | static INLINE int | |
1825 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1826 | { | |
1827 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1828 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1829 | } |
1830 | ||
c6fb90c8 L |
1831 | static INLINE i386_cpu_flags |
1832 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1833 | { |
c6fb90c8 L |
1834 | switch (ARRAY_SIZE (x.array)) |
1835 | { | |
53467f57 IT |
1836 | case 4: |
1837 | x.array [3] &= y.array [3]; | |
1838 | /* Fall through. */ | |
c6fb90c8 L |
1839 | case 3: |
1840 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1841 | /* Fall through. */ |
c6fb90c8 L |
1842 | case 2: |
1843 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1844 | /* Fall through. */ |
c6fb90c8 L |
1845 | case 1: |
1846 | x.array [0] &= y.array [0]; | |
1847 | break; | |
1848 | default: | |
1849 | abort (); | |
1850 | } | |
1851 | return x; | |
1852 | } | |
40fb9820 | 1853 | |
c6fb90c8 L |
1854 | static INLINE i386_cpu_flags |
1855 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1856 | { |
c6fb90c8 | 1857 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1858 | { |
53467f57 IT |
1859 | case 4: |
1860 | x.array [3] |= y.array [3]; | |
1861 | /* Fall through. */ | |
c6fb90c8 L |
1862 | case 3: |
1863 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1864 | /* Fall through. */ |
c6fb90c8 L |
1865 | case 2: |
1866 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1867 | /* Fall through. */ |
c6fb90c8 L |
1868 | case 1: |
1869 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1870 | break; |
1871 | default: | |
1872 | abort (); | |
1873 | } | |
40fb9820 L |
1874 | return x; |
1875 | } | |
1876 | ||
309d3373 JB |
1877 | static INLINE i386_cpu_flags |
1878 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1879 | { | |
1880 | switch (ARRAY_SIZE (x.array)) | |
1881 | { | |
53467f57 IT |
1882 | case 4: |
1883 | x.array [3] &= ~y.array [3]; | |
1884 | /* Fall through. */ | |
309d3373 JB |
1885 | case 3: |
1886 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1887 | /* Fall through. */ |
309d3373 JB |
1888 | case 2: |
1889 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1890 | /* Fall through. */ |
309d3373 JB |
1891 | case 1: |
1892 | x.array [0] &= ~y.array [0]; | |
1893 | break; | |
1894 | default: | |
1895 | abort (); | |
1896 | } | |
1897 | return x; | |
1898 | } | |
1899 | ||
6c0946d0 JB |
1900 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1901 | ||
c0f3af97 L |
1902 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1903 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1904 | ||
c0f3af97 | 1905 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1906 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1907 | |
1908 | /* Return CPU flags match bits. */ | |
3629bb00 | 1909 | |
40fb9820 | 1910 | static int |
d3ce72d0 | 1911 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1912 | { |
c0f3af97 L |
1913 | i386_cpu_flags x = t->cpu_flags; |
1914 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1915 | |
1916 | x.bitfield.cpu64 = 0; | |
1917 | x.bitfield.cpuno64 = 0; | |
1918 | ||
0dfbf9d7 | 1919 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1920 | { |
1921 | /* This instruction is available on all archs. */ | |
db12e14e | 1922 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1923 | } |
3629bb00 L |
1924 | else |
1925 | { | |
c0f3af97 | 1926 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1927 | i386_cpu_flags cpu = cpu_arch_flags; |
1928 | ||
ab592e75 JB |
1929 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1930 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1931 | return match; | |
1932 | x.bitfield.cpuavx512vl = 0; | |
1933 | ||
3629bb00 | 1934 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1935 | if (!cpu_flags_all_zero (&cpu)) |
1936 | { | |
a5ff0eb2 L |
1937 | if (x.bitfield.cpuavx) |
1938 | { | |
929f69fa | 1939 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1940 | if (cpu.bitfield.cpuavx |
1941 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1942 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1943 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1944 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1945 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1946 | } |
929f69fa JB |
1947 | else if (x.bitfield.cpuavx512f) |
1948 | { | |
1949 | /* We need to check a few extra flags with AVX512F. */ | |
1950 | if (cpu.bitfield.cpuavx512f | |
1951 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1952 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1953 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1954 | match |= CPU_FLAGS_ARCH_MATCH; | |
1955 | } | |
a5ff0eb2 | 1956 | else |
db12e14e | 1957 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1958 | } |
3629bb00 | 1959 | } |
c0f3af97 | 1960 | return match; |
40fb9820 L |
1961 | } |
1962 | ||
c6fb90c8 L |
1963 | static INLINE i386_operand_type |
1964 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1965 | { |
bab6aec1 JB |
1966 | if (x.bitfield.class != y.bitfield.class) |
1967 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1968 | if (x.bitfield.instance != y.bitfield.instance) |
1969 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1970 | |
c6fb90c8 L |
1971 | switch (ARRAY_SIZE (x.array)) |
1972 | { | |
1973 | case 3: | |
1974 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1975 | /* Fall through. */ |
c6fb90c8 L |
1976 | case 2: |
1977 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1978 | /* Fall through. */ |
c6fb90c8 L |
1979 | case 1: |
1980 | x.array [0] &= y.array [0]; | |
1981 | break; | |
1982 | default: | |
1983 | abort (); | |
1984 | } | |
1985 | return x; | |
40fb9820 L |
1986 | } |
1987 | ||
73053c1f JB |
1988 | static INLINE i386_operand_type |
1989 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1990 | { | |
bab6aec1 | 1991 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1992 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1993 | |
73053c1f JB |
1994 | switch (ARRAY_SIZE (x.array)) |
1995 | { | |
1996 | case 3: | |
1997 | x.array [2] &= ~y.array [2]; | |
1998 | /* Fall through. */ | |
1999 | case 2: | |
2000 | x.array [1] &= ~y.array [1]; | |
2001 | /* Fall through. */ | |
2002 | case 1: | |
2003 | x.array [0] &= ~y.array [0]; | |
2004 | break; | |
2005 | default: | |
2006 | abort (); | |
2007 | } | |
2008 | return x; | |
2009 | } | |
2010 | ||
c6fb90c8 L |
2011 | static INLINE i386_operand_type |
2012 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 2013 | { |
bab6aec1 JB |
2014 | gas_assert (x.bitfield.class == ClassNone || |
2015 | y.bitfield.class == ClassNone || | |
2016 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
2017 | gas_assert (x.bitfield.instance == InstanceNone || |
2018 | y.bitfield.instance == InstanceNone || | |
2019 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 2020 | |
c6fb90c8 | 2021 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 2022 | { |
c6fb90c8 L |
2023 | case 3: |
2024 | x.array [2] |= y.array [2]; | |
1a0670f3 | 2025 | /* Fall through. */ |
c6fb90c8 L |
2026 | case 2: |
2027 | x.array [1] |= y.array [1]; | |
1a0670f3 | 2028 | /* Fall through. */ |
c6fb90c8 L |
2029 | case 1: |
2030 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2031 | break; |
2032 | default: | |
2033 | abort (); | |
2034 | } | |
c6fb90c8 L |
2035 | return x; |
2036 | } | |
40fb9820 | 2037 | |
c6fb90c8 L |
2038 | static INLINE i386_operand_type |
2039 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2040 | { | |
bab6aec1 | 2041 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2042 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2043 | |
c6fb90c8 L |
2044 | switch (ARRAY_SIZE (x.array)) |
2045 | { | |
2046 | case 3: | |
2047 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2048 | /* Fall through. */ |
c6fb90c8 L |
2049 | case 2: |
2050 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2051 | /* Fall through. */ |
c6fb90c8 L |
2052 | case 1: |
2053 | x.array [0] ^= y.array [0]; | |
2054 | break; | |
2055 | default: | |
2056 | abort (); | |
2057 | } | |
40fb9820 L |
2058 | return x; |
2059 | } | |
2060 | ||
40fb9820 L |
2061 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
2062 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
2063 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
2064 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
2065 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
2066 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 2067 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 2068 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
2069 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
2070 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
2071 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
2072 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
2073 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
2074 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
2075 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
2076 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
2077 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
2078 | ||
2079 | enum operand_type | |
2080 | { | |
2081 | reg, | |
40fb9820 L |
2082 | imm, |
2083 | disp, | |
2084 | anymem | |
2085 | }; | |
2086 | ||
c6fb90c8 | 2087 | static INLINE int |
40fb9820 L |
2088 | operand_type_check (i386_operand_type t, enum operand_type c) |
2089 | { | |
2090 | switch (c) | |
2091 | { | |
2092 | case reg: | |
bab6aec1 | 2093 | return t.bitfield.class == Reg; |
40fb9820 | 2094 | |
40fb9820 L |
2095 | case imm: |
2096 | return (t.bitfield.imm8 | |
2097 | || t.bitfield.imm8s | |
2098 | || t.bitfield.imm16 | |
2099 | || t.bitfield.imm32 | |
2100 | || t.bitfield.imm32s | |
2101 | || t.bitfield.imm64); | |
2102 | ||
2103 | case disp: | |
2104 | return (t.bitfield.disp8 | |
2105 | || t.bitfield.disp16 | |
2106 | || t.bitfield.disp32 | |
2107 | || t.bitfield.disp32s | |
2108 | || t.bitfield.disp64); | |
2109 | ||
2110 | case anymem: | |
2111 | return (t.bitfield.disp8 | |
2112 | || t.bitfield.disp16 | |
2113 | || t.bitfield.disp32 | |
2114 | || t.bitfield.disp32s | |
2115 | || t.bitfield.disp64 | |
2116 | || t.bitfield.baseindex); | |
2117 | ||
2118 | default: | |
2119 | abort (); | |
2120 | } | |
2cfe26b6 AM |
2121 | |
2122 | return 0; | |
40fb9820 L |
2123 | } |
2124 | ||
7a54636a L |
2125 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2126 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2127 | |
2128 | static INLINE int | |
7a54636a L |
2129 | match_operand_size (const insn_template *t, unsigned int wanted, |
2130 | unsigned int given) | |
5c07affc | 2131 | { |
3ac21baa JB |
2132 | return !((i.types[given].bitfield.byte |
2133 | && !t->operand_types[wanted].bitfield.byte) | |
2134 | || (i.types[given].bitfield.word | |
2135 | && !t->operand_types[wanted].bitfield.word) | |
2136 | || (i.types[given].bitfield.dword | |
2137 | && !t->operand_types[wanted].bitfield.dword) | |
2138 | || (i.types[given].bitfield.qword | |
2139 | && !t->operand_types[wanted].bitfield.qword) | |
2140 | || (i.types[given].bitfield.tbyte | |
2141 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2142 | } |
2143 | ||
dd40ce22 L |
2144 | /* Return 1 if there is no conflict in SIMD register between operand |
2145 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2146 | |
2147 | static INLINE int | |
dd40ce22 L |
2148 | match_simd_size (const insn_template *t, unsigned int wanted, |
2149 | unsigned int given) | |
1b54b8d7 | 2150 | { |
3ac21baa JB |
2151 | return !((i.types[given].bitfield.xmmword |
2152 | && !t->operand_types[wanted].bitfield.xmmword) | |
2153 | || (i.types[given].bitfield.ymmword | |
2154 | && !t->operand_types[wanted].bitfield.ymmword) | |
2155 | || (i.types[given].bitfield.zmmword | |
2156 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
2157 | } |
2158 | ||
7a54636a L |
2159 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2160 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2161 | |
2162 | static INLINE int | |
dd40ce22 L |
2163 | match_mem_size (const insn_template *t, unsigned int wanted, |
2164 | unsigned int given) | |
5c07affc | 2165 | { |
7a54636a | 2166 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2167 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 2168 | && !i.broadcast |
3ac21baa JB |
2169 | && !t->operand_types[wanted].bitfield.unspecified) |
2170 | || (i.types[given].bitfield.fword | |
2171 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2172 | /* For scalar opcode templates to allow register and memory |
2173 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2174 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2175 | down-conversion vpmov*. */ | |
3528c362 | 2176 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
bc49bfd8 JB |
2177 | && t->operand_types[wanted].bitfield.byte |
2178 | + t->operand_types[wanted].bitfield.word | |
2179 | + t->operand_types[wanted].bitfield.dword | |
2180 | + t->operand_types[wanted].bitfield.qword | |
2181 | > !!t->opcode_modifier.broadcast) | |
3ac21baa JB |
2182 | ? (i.types[given].bitfield.xmmword |
2183 | || i.types[given].bitfield.ymmword | |
2184 | || i.types[given].bitfield.zmmword) | |
2185 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2186 | } |
2187 | ||
3ac21baa JB |
2188 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2189 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2190 | is no size conflict on any operands for the template with operands reversed | |
2191 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2192 | |
3ac21baa JB |
2193 | #define MATCH_STRAIGHT 1 |
2194 | #define MATCH_REVERSE 2 | |
2195 | ||
2196 | static INLINE unsigned int | |
d3ce72d0 | 2197 | operand_size_match (const insn_template *t) |
5c07affc | 2198 | { |
3ac21baa | 2199 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2200 | |
0cfa3eb3 | 2201 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2202 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2203 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2204 | return match; |
2205 | ||
2206 | /* Check memory and accumulator operand size. */ | |
2207 | for (j = 0; j < i.operands; j++) | |
2208 | { | |
3528c362 JB |
2209 | if (i.types[j].bitfield.class != Reg |
2210 | && i.types[j].bitfield.class != RegSIMD | |
601e8564 | 2211 | && t->opcode_modifier.anysize) |
5c07affc L |
2212 | continue; |
2213 | ||
bab6aec1 | 2214 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2215 | && !match_operand_size (t, j, j)) |
5c07affc L |
2216 | { |
2217 | match = 0; | |
2218 | break; | |
2219 | } | |
2220 | ||
3528c362 | 2221 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2222 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2223 | { |
2224 | match = 0; | |
2225 | break; | |
2226 | } | |
2227 | ||
75e5731b | 2228 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2229 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2230 | { |
2231 | match = 0; | |
2232 | break; | |
2233 | } | |
2234 | ||
c48dadc9 | 2235 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2236 | { |
2237 | match = 0; | |
2238 | break; | |
2239 | } | |
2240 | } | |
2241 | ||
3ac21baa | 2242 | if (!t->opcode_modifier.d) |
891edac4 | 2243 | { |
dc1e8a47 | 2244 | mismatch: |
3ac21baa JB |
2245 | if (!match) |
2246 | i.error = operand_size_mismatch; | |
2247 | return match; | |
891edac4 | 2248 | } |
5c07affc L |
2249 | |
2250 | /* Check reverse. */ | |
f5eb1d70 | 2251 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2252 | |
f5eb1d70 | 2253 | for (j = 0; j < i.operands; j++) |
5c07affc | 2254 | { |
f5eb1d70 JB |
2255 | unsigned int given = i.operands - j - 1; |
2256 | ||
bab6aec1 | 2257 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2258 | && !match_operand_size (t, j, given)) |
891edac4 | 2259 | goto mismatch; |
5c07affc | 2260 | |
3528c362 | 2261 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2262 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2263 | goto mismatch; |
2264 | ||
75e5731b | 2265 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2266 | && (!match_operand_size (t, j, given) |
2267 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2268 | goto mismatch; |
2269 | ||
f5eb1d70 | 2270 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2271 | goto mismatch; |
5c07affc L |
2272 | } |
2273 | ||
3ac21baa | 2274 | return match | MATCH_REVERSE; |
5c07affc L |
2275 | } |
2276 | ||
c6fb90c8 | 2277 | static INLINE int |
40fb9820 L |
2278 | operand_type_match (i386_operand_type overlap, |
2279 | i386_operand_type given) | |
2280 | { | |
2281 | i386_operand_type temp = overlap; | |
2282 | ||
7d5e4556 | 2283 | temp.bitfield.unspecified = 0; |
5c07affc L |
2284 | temp.bitfield.byte = 0; |
2285 | temp.bitfield.word = 0; | |
2286 | temp.bitfield.dword = 0; | |
2287 | temp.bitfield.fword = 0; | |
2288 | temp.bitfield.qword = 0; | |
2289 | temp.bitfield.tbyte = 0; | |
2290 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2291 | temp.bitfield.ymmword = 0; |
43234a1e | 2292 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2293 | if (operand_type_all_zero (&temp)) |
891edac4 | 2294 | goto mismatch; |
40fb9820 | 2295 | |
6f2f06be | 2296 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2297 | return 1; |
2298 | ||
dc1e8a47 | 2299 | mismatch: |
a65babc9 | 2300 | i.error = operand_type_mismatch; |
891edac4 | 2301 | return 0; |
40fb9820 L |
2302 | } |
2303 | ||
7d5e4556 | 2304 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2305 | unless the expected operand type register overlap is null. |
5de4d9ef | 2306 | Some Intel syntax memory operand size checking also happens here. */ |
40fb9820 | 2307 | |
c6fb90c8 | 2308 | static INLINE int |
dc821c5f | 2309 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2310 | i386_operand_type t0, |
40fb9820 L |
2311 | i386_operand_type g1, |
2312 | i386_operand_type t1) | |
2313 | { | |
bab6aec1 | 2314 | if (g0.bitfield.class != Reg |
3528c362 | 2315 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2316 | && (!operand_type_check (g0, anymem) |
2317 | || g0.bitfield.unspecified | |
5de4d9ef JB |
2318 | || (t0.bitfield.class != Reg |
2319 | && t0.bitfield.class != RegSIMD))) | |
40fb9820 L |
2320 | return 1; |
2321 | ||
bab6aec1 | 2322 | if (g1.bitfield.class != Reg |
3528c362 | 2323 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2324 | && (!operand_type_check (g1, anymem) |
2325 | || g1.bitfield.unspecified | |
5de4d9ef JB |
2326 | || (t1.bitfield.class != Reg |
2327 | && t1.bitfield.class != RegSIMD))) | |
40fb9820 L |
2328 | return 1; |
2329 | ||
dc821c5f JB |
2330 | if (g0.bitfield.byte == g1.bitfield.byte |
2331 | && g0.bitfield.word == g1.bitfield.word | |
2332 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2333 | && g0.bitfield.qword == g1.bitfield.qword |
2334 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2335 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2336 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2337 | return 1; |
2338 | ||
dc821c5f JB |
2339 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2340 | && !(t0.bitfield.word & t1.bitfield.word) | |
2341 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2342 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2343 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2344 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2345 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2346 | return 1; |
2347 | ||
a65babc9 | 2348 | i.error = register_type_mismatch; |
891edac4 L |
2349 | |
2350 | return 0; | |
40fb9820 L |
2351 | } |
2352 | ||
4c692bc7 JB |
2353 | static INLINE unsigned int |
2354 | register_number (const reg_entry *r) | |
2355 | { | |
2356 | unsigned int nr = r->reg_num; | |
2357 | ||
2358 | if (r->reg_flags & RegRex) | |
2359 | nr += 8; | |
2360 | ||
200cbe0f L |
2361 | if (r->reg_flags & RegVRex) |
2362 | nr += 16; | |
2363 | ||
4c692bc7 JB |
2364 | return nr; |
2365 | } | |
2366 | ||
252b5132 | 2367 | static INLINE unsigned int |
40fb9820 | 2368 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2369 | { |
b5014f7a | 2370 | if (t.bitfield.disp8) |
40fb9820 L |
2371 | return 1; |
2372 | else if (t.bitfield.disp16 | |
2373 | || t.bitfield.disp32 | |
2374 | || t.bitfield.disp32s) | |
2375 | return 2; | |
2376 | else | |
2377 | return 0; | |
252b5132 RH |
2378 | } |
2379 | ||
2380 | static INLINE int | |
65879393 | 2381 | fits_in_signed_byte (addressT num) |
252b5132 | 2382 | { |
65879393 | 2383 | return num + 0x80 <= 0xff; |
47926f60 | 2384 | } |
252b5132 RH |
2385 | |
2386 | static INLINE int | |
65879393 | 2387 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2388 | { |
65879393 | 2389 | return num <= 0xff; |
47926f60 | 2390 | } |
252b5132 RH |
2391 | |
2392 | static INLINE int | |
65879393 | 2393 | fits_in_unsigned_word (addressT num) |
252b5132 | 2394 | { |
65879393 | 2395 | return num <= 0xffff; |
47926f60 | 2396 | } |
252b5132 RH |
2397 | |
2398 | static INLINE int | |
65879393 | 2399 | fits_in_signed_word (addressT num) |
252b5132 | 2400 | { |
65879393 | 2401 | return num + 0x8000 <= 0xffff; |
47926f60 | 2402 | } |
2a962e6d | 2403 | |
3e73aa7c | 2404 | static INLINE int |
65879393 | 2405 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2406 | { |
2407 | #ifndef BFD64 | |
2408 | return 1; | |
2409 | #else | |
65879393 | 2410 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2411 | #endif |
2412 | } /* fits_in_signed_long() */ | |
2a962e6d | 2413 | |
3e73aa7c | 2414 | static INLINE int |
65879393 | 2415 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2416 | { |
2417 | #ifndef BFD64 | |
2418 | return 1; | |
2419 | #else | |
65879393 | 2420 | return num <= 0xffffffff; |
3e73aa7c JH |
2421 | #endif |
2422 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2423 | |
43234a1e | 2424 | static INLINE int |
b5014f7a | 2425 | fits_in_disp8 (offsetT num) |
43234a1e L |
2426 | { |
2427 | int shift = i.memshift; | |
2428 | unsigned int mask; | |
2429 | ||
2430 | if (shift == -1) | |
2431 | abort (); | |
2432 | ||
2433 | mask = (1 << shift) - 1; | |
2434 | ||
2435 | /* Return 0 if NUM isn't properly aligned. */ | |
2436 | if ((num & mask)) | |
2437 | return 0; | |
2438 | ||
2439 | /* Check if NUM will fit in 8bit after shift. */ | |
2440 | return fits_in_signed_byte (num >> shift); | |
2441 | } | |
2442 | ||
a683cc34 SP |
2443 | static INLINE int |
2444 | fits_in_imm4 (offsetT num) | |
2445 | { | |
2446 | return (num & 0xf) == num; | |
2447 | } | |
2448 | ||
40fb9820 | 2449 | static i386_operand_type |
e3bb37b5 | 2450 | smallest_imm_type (offsetT num) |
252b5132 | 2451 | { |
40fb9820 | 2452 | i386_operand_type t; |
7ab9ffdd | 2453 | |
0dfbf9d7 | 2454 | operand_type_set (&t, 0); |
40fb9820 L |
2455 | t.bitfield.imm64 = 1; |
2456 | ||
2457 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2458 | { |
2459 | /* This code is disabled on the 486 because all the Imm1 forms | |
2460 | in the opcode table are slower on the i486. They're the | |
2461 | versions with the implicitly specified single-position | |
2462 | displacement, which has another syntax if you really want to | |
2463 | use that form. */ | |
40fb9820 L |
2464 | t.bitfield.imm1 = 1; |
2465 | t.bitfield.imm8 = 1; | |
2466 | t.bitfield.imm8s = 1; | |
2467 | t.bitfield.imm16 = 1; | |
2468 | t.bitfield.imm32 = 1; | |
2469 | t.bitfield.imm32s = 1; | |
2470 | } | |
2471 | else if (fits_in_signed_byte (num)) | |
2472 | { | |
2473 | t.bitfield.imm8 = 1; | |
2474 | t.bitfield.imm8s = 1; | |
2475 | t.bitfield.imm16 = 1; | |
2476 | t.bitfield.imm32 = 1; | |
2477 | t.bitfield.imm32s = 1; | |
2478 | } | |
2479 | else if (fits_in_unsigned_byte (num)) | |
2480 | { | |
2481 | t.bitfield.imm8 = 1; | |
2482 | t.bitfield.imm16 = 1; | |
2483 | t.bitfield.imm32 = 1; | |
2484 | t.bitfield.imm32s = 1; | |
2485 | } | |
2486 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2487 | { | |
2488 | t.bitfield.imm16 = 1; | |
2489 | t.bitfield.imm32 = 1; | |
2490 | t.bitfield.imm32s = 1; | |
2491 | } | |
2492 | else if (fits_in_signed_long (num)) | |
2493 | { | |
2494 | t.bitfield.imm32 = 1; | |
2495 | t.bitfield.imm32s = 1; | |
2496 | } | |
2497 | else if (fits_in_unsigned_long (num)) | |
2498 | t.bitfield.imm32 = 1; | |
2499 | ||
2500 | return t; | |
47926f60 | 2501 | } |
252b5132 | 2502 | |
847f7ad4 | 2503 | static offsetT |
e3bb37b5 | 2504 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2505 | { |
508866be | 2506 | addressT mask; |
ba2adb93 | 2507 | |
847f7ad4 AM |
2508 | switch (size) |
2509 | { | |
508866be L |
2510 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2511 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2512 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2513 | #ifdef BFD64 |
2514 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2515 | #endif | |
47926f60 | 2516 | default: abort (); |
847f7ad4 AM |
2517 | } |
2518 | ||
9de868bf L |
2519 | #ifdef BFD64 |
2520 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2521 | if (flag_code != CODE_64BIT | |
2522 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2523 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2524 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2525 | #endif |
ba2adb93 | 2526 | |
47926f60 | 2527 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2528 | { |
2529 | char buf1[40], buf2[40]; | |
2530 | ||
2531 | sprint_value (buf1, val); | |
2532 | sprint_value (buf2, val & mask); | |
2533 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2534 | } | |
2535 | return val & mask; | |
2536 | } | |
2537 | ||
c32fa91d L |
2538 | enum PREFIX_GROUP |
2539 | { | |
2540 | PREFIX_EXIST = 0, | |
2541 | PREFIX_LOCK, | |
2542 | PREFIX_REP, | |
04ef582a | 2543 | PREFIX_DS, |
c32fa91d L |
2544 | PREFIX_OTHER |
2545 | }; | |
2546 | ||
2547 | /* Returns | |
2548 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2549 | same class already exists. | |
2550 | b. PREFIX_LOCK if lock prefix is added. | |
2551 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2552 | d. PREFIX_DS if ds prefix is added. |
2553 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2554 | */ |
2555 | ||
2556 | static enum PREFIX_GROUP | |
e3bb37b5 | 2557 | add_prefix (unsigned int prefix) |
252b5132 | 2558 | { |
c32fa91d | 2559 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2560 | unsigned int q; |
252b5132 | 2561 | |
29b0f896 AM |
2562 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2563 | && flag_code == CODE_64BIT) | |
b1905489 | 2564 | { |
161a04f6 | 2565 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2566 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2567 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2568 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2569 | ret = PREFIX_EXIST; |
b1905489 JB |
2570 | q = REX_PREFIX; |
2571 | } | |
3e73aa7c | 2572 | else |
b1905489 JB |
2573 | { |
2574 | switch (prefix) | |
2575 | { | |
2576 | default: | |
2577 | abort (); | |
2578 | ||
b1905489 | 2579 | case DS_PREFIX_OPCODE: |
04ef582a L |
2580 | ret = PREFIX_DS; |
2581 | /* Fall through. */ | |
2582 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2583 | case ES_PREFIX_OPCODE: |
2584 | case FS_PREFIX_OPCODE: | |
2585 | case GS_PREFIX_OPCODE: | |
2586 | case SS_PREFIX_OPCODE: | |
2587 | q = SEG_PREFIX; | |
2588 | break; | |
2589 | ||
2590 | case REPNE_PREFIX_OPCODE: | |
2591 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2592 | q = REP_PREFIX; |
2593 | ret = PREFIX_REP; | |
2594 | break; | |
2595 | ||
b1905489 | 2596 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2597 | q = LOCK_PREFIX; |
2598 | ret = PREFIX_LOCK; | |
b1905489 JB |
2599 | break; |
2600 | ||
2601 | case FWAIT_OPCODE: | |
2602 | q = WAIT_PREFIX; | |
2603 | break; | |
2604 | ||
2605 | case ADDR_PREFIX_OPCODE: | |
2606 | q = ADDR_PREFIX; | |
2607 | break; | |
2608 | ||
2609 | case DATA_PREFIX_OPCODE: | |
2610 | q = DATA_PREFIX; | |
2611 | break; | |
2612 | } | |
2613 | if (i.prefix[q] != 0) | |
c32fa91d | 2614 | ret = PREFIX_EXIST; |
b1905489 | 2615 | } |
252b5132 | 2616 | |
b1905489 | 2617 | if (ret) |
252b5132 | 2618 | { |
b1905489 JB |
2619 | if (!i.prefix[q]) |
2620 | ++i.prefixes; | |
2621 | i.prefix[q] |= prefix; | |
252b5132 | 2622 | } |
b1905489 JB |
2623 | else |
2624 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2625 | |
252b5132 RH |
2626 | return ret; |
2627 | } | |
2628 | ||
2629 | static void | |
78f12dd3 | 2630 | update_code_flag (int value, int check) |
eecb386c | 2631 | { |
78f12dd3 L |
2632 | PRINTF_LIKE ((*as_error)); |
2633 | ||
1e9cc1c2 | 2634 | flag_code = (enum flag_code) value; |
40fb9820 L |
2635 | if (flag_code == CODE_64BIT) |
2636 | { | |
2637 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2638 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2639 | } |
2640 | else | |
2641 | { | |
2642 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2643 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2644 | } |
2645 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2646 | { |
78f12dd3 L |
2647 | if (check) |
2648 | as_error = as_fatal; | |
2649 | else | |
2650 | as_error = as_bad; | |
2651 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2652 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2653 | } |
40fb9820 | 2654 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2655 | { |
78f12dd3 L |
2656 | if (check) |
2657 | as_error = as_fatal; | |
2658 | else | |
2659 | as_error = as_bad; | |
2660 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2661 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2662 | } |
eecb386c AM |
2663 | stackop_size = '\0'; |
2664 | } | |
2665 | ||
78f12dd3 L |
2666 | static void |
2667 | set_code_flag (int value) | |
2668 | { | |
2669 | update_code_flag (value, 0); | |
2670 | } | |
2671 | ||
eecb386c | 2672 | static void |
e3bb37b5 | 2673 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2674 | { |
1e9cc1c2 | 2675 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2676 | if (flag_code != CODE_16BIT) |
2677 | abort (); | |
2678 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2679 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2680 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2681 | } |
2682 | ||
2683 | static void | |
e3bb37b5 | 2684 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2685 | { |
2686 | /* Find out if register prefixing is specified. */ | |
2687 | int ask_naked_reg = 0; | |
2688 | ||
2689 | SKIP_WHITESPACE (); | |
29b0f896 | 2690 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2691 | { |
d02603dc NC |
2692 | char *string; |
2693 | int e = get_symbol_name (&string); | |
252b5132 | 2694 | |
47926f60 | 2695 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2696 | ask_naked_reg = 1; |
47926f60 | 2697 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2698 | ask_naked_reg = -1; |
2699 | else | |
d0b47220 | 2700 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2701 | (void) restore_line_pointer (e); |
252b5132 RH |
2702 | } |
2703 | demand_empty_rest_of_line (); | |
c3332e24 | 2704 | |
252b5132 RH |
2705 | intel_syntax = syntax_flag; |
2706 | ||
2707 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2708 | allow_naked_reg = (intel_syntax |
2709 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2710 | else |
2711 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2712 | |
ee86248c | 2713 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2714 | |
e4a3b5a4 | 2715 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2716 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2717 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2718 | } |
2719 | ||
1efbbeb4 L |
2720 | static void |
2721 | set_intel_mnemonic (int mnemonic_flag) | |
2722 | { | |
e1d4d893 | 2723 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2724 | } |
2725 | ||
db51cc60 L |
2726 | static void |
2727 | set_allow_index_reg (int flag) | |
2728 | { | |
2729 | allow_index_reg = flag; | |
2730 | } | |
2731 | ||
cb19c032 | 2732 | static void |
7bab8ab5 | 2733 | set_check (int what) |
cb19c032 | 2734 | { |
7bab8ab5 JB |
2735 | enum check_kind *kind; |
2736 | const char *str; | |
2737 | ||
2738 | if (what) | |
2739 | { | |
2740 | kind = &operand_check; | |
2741 | str = "operand"; | |
2742 | } | |
2743 | else | |
2744 | { | |
2745 | kind = &sse_check; | |
2746 | str = "sse"; | |
2747 | } | |
2748 | ||
cb19c032 L |
2749 | SKIP_WHITESPACE (); |
2750 | ||
2751 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2752 | { | |
d02603dc NC |
2753 | char *string; |
2754 | int e = get_symbol_name (&string); | |
cb19c032 L |
2755 | |
2756 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2757 | *kind = check_none; |
cb19c032 | 2758 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2759 | *kind = check_warning; |
cb19c032 | 2760 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2761 | *kind = check_error; |
cb19c032 | 2762 | else |
7bab8ab5 | 2763 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2764 | (void) restore_line_pointer (e); |
cb19c032 L |
2765 | } |
2766 | else | |
7bab8ab5 | 2767 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2768 | |
2769 | demand_empty_rest_of_line (); | |
2770 | } | |
2771 | ||
8a9036a4 L |
2772 | static void |
2773 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2774 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2775 | { |
2776 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2777 | static const char *arch; | |
2778 | ||
2779 | /* Intel LIOM is only supported on ELF. */ | |
2780 | if (!IS_ELF) | |
2781 | return; | |
2782 | ||
2783 | if (!arch) | |
2784 | { | |
2785 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2786 | use default_arch. */ | |
2787 | arch = cpu_arch_name; | |
2788 | if (!arch) | |
2789 | arch = default_arch; | |
2790 | } | |
2791 | ||
81486035 L |
2792 | /* If we are targeting Intel MCU, we must enable it. */ |
2793 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2794 | || new_flag.bitfield.cpuiamcu) | |
2795 | return; | |
2796 | ||
3632d14b | 2797 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2798 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2799 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2800 | return; |
76ba9986 | 2801 | |
7a9068fe L |
2802 | /* If we are targeting Intel K1OM, we must enable it. */ |
2803 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2804 | || new_flag.bitfield.cpuk1om) | |
2805 | return; | |
2806 | ||
8a9036a4 L |
2807 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2808 | #endif | |
2809 | } | |
2810 | ||
e413e4e9 | 2811 | static void |
e3bb37b5 | 2812 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2813 | { |
47926f60 | 2814 | SKIP_WHITESPACE (); |
e413e4e9 | 2815 | |
29b0f896 | 2816 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2817 | { |
d02603dc NC |
2818 | char *string; |
2819 | int e = get_symbol_name (&string); | |
91d6fa6a | 2820 | unsigned int j; |
40fb9820 | 2821 | i386_cpu_flags flags; |
e413e4e9 | 2822 | |
91d6fa6a | 2823 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2824 | { |
91d6fa6a | 2825 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2826 | { |
91d6fa6a | 2827 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2828 | |
5c6af06e JB |
2829 | if (*string != '.') |
2830 | { | |
91d6fa6a | 2831 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2832 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2833 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2834 | if (flag_code == CODE_64BIT) |
2835 | { | |
2836 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2837 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2838 | } | |
2839 | else | |
2840 | { | |
2841 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2842 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2843 | } | |
91d6fa6a NC |
2844 | cpu_arch_isa = cpu_arch[j].type; |
2845 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2846 | if (!cpu_arch_tune_set) |
2847 | { | |
2848 | cpu_arch_tune = cpu_arch_isa; | |
2849 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2850 | } | |
5c6af06e JB |
2851 | break; |
2852 | } | |
40fb9820 | 2853 | |
293f5f65 L |
2854 | flags = cpu_flags_or (cpu_arch_flags, |
2855 | cpu_arch[j].flags); | |
81486035 | 2856 | |
5b64d091 | 2857 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2858 | { |
6305a203 L |
2859 | if (cpu_sub_arch_name) |
2860 | { | |
2861 | char *name = cpu_sub_arch_name; | |
2862 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2863 | cpu_arch[j].name, |
1bf57e9f | 2864 | (const char *) NULL); |
6305a203 L |
2865 | free (name); |
2866 | } | |
2867 | else | |
91d6fa6a | 2868 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2869 | cpu_arch_flags = flags; |
a586129e | 2870 | cpu_arch_isa_flags = flags; |
5c6af06e | 2871 | } |
0089dace L |
2872 | else |
2873 | cpu_arch_isa_flags | |
2874 | = cpu_flags_or (cpu_arch_isa_flags, | |
2875 | cpu_arch[j].flags); | |
d02603dc | 2876 | (void) restore_line_pointer (e); |
5c6af06e JB |
2877 | demand_empty_rest_of_line (); |
2878 | return; | |
e413e4e9 AM |
2879 | } |
2880 | } | |
293f5f65 L |
2881 | |
2882 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2883 | { | |
33eaf5de | 2884 | /* Disable an ISA extension. */ |
293f5f65 L |
2885 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2886 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2887 | { | |
2888 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2889 | cpu_noarch[j].flags); | |
2890 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2891 | { | |
2892 | if (cpu_sub_arch_name) | |
2893 | { | |
2894 | char *name = cpu_sub_arch_name; | |
2895 | cpu_sub_arch_name = concat (name, string, | |
2896 | (const char *) NULL); | |
2897 | free (name); | |
2898 | } | |
2899 | else | |
2900 | cpu_sub_arch_name = xstrdup (string); | |
2901 | cpu_arch_flags = flags; | |
2902 | cpu_arch_isa_flags = flags; | |
2903 | } | |
2904 | (void) restore_line_pointer (e); | |
2905 | demand_empty_rest_of_line (); | |
2906 | return; | |
2907 | } | |
2908 | ||
2909 | j = ARRAY_SIZE (cpu_arch); | |
2910 | } | |
2911 | ||
91d6fa6a | 2912 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2913 | as_bad (_("no such architecture: `%s'"), string); |
2914 | ||
2915 | *input_line_pointer = e; | |
2916 | } | |
2917 | else | |
2918 | as_bad (_("missing cpu architecture")); | |
2919 | ||
fddf5b5b AM |
2920 | no_cond_jump_promotion = 0; |
2921 | if (*input_line_pointer == ',' | |
29b0f896 | 2922 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2923 | { |
d02603dc NC |
2924 | char *string; |
2925 | char e; | |
2926 | ||
2927 | ++input_line_pointer; | |
2928 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2929 | |
2930 | if (strcmp (string, "nojumps") == 0) | |
2931 | no_cond_jump_promotion = 1; | |
2932 | else if (strcmp (string, "jumps") == 0) | |
2933 | ; | |
2934 | else | |
2935 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2936 | ||
d02603dc | 2937 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2938 | } |
2939 | ||
e413e4e9 AM |
2940 | demand_empty_rest_of_line (); |
2941 | } | |
2942 | ||
8a9036a4 L |
2943 | enum bfd_architecture |
2944 | i386_arch (void) | |
2945 | { | |
3632d14b | 2946 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2947 | { |
2948 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2949 | || flag_code != CODE_64BIT) | |
2950 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2951 | return bfd_arch_l1om; | |
2952 | } | |
7a9068fe L |
2953 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2954 | { | |
2955 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2956 | || flag_code != CODE_64BIT) | |
2957 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2958 | return bfd_arch_k1om; | |
2959 | } | |
81486035 L |
2960 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2961 | { | |
2962 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2963 | || flag_code == CODE_64BIT) | |
2964 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2965 | return bfd_arch_iamcu; | |
2966 | } | |
8a9036a4 L |
2967 | else |
2968 | return bfd_arch_i386; | |
2969 | } | |
2970 | ||
b9d79e03 | 2971 | unsigned long |
7016a5d5 | 2972 | i386_mach (void) |
b9d79e03 | 2973 | { |
351f65ca | 2974 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2975 | { |
3632d14b | 2976 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2977 | { |
351f65ca L |
2978 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2979 | || default_arch[6] != '\0') | |
8a9036a4 L |
2980 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2981 | return bfd_mach_l1om; | |
2982 | } | |
7a9068fe L |
2983 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2984 | { | |
2985 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2986 | || default_arch[6] != '\0') | |
2987 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2988 | return bfd_mach_k1om; | |
2989 | } | |
351f65ca | 2990 | else if (default_arch[6] == '\0') |
8a9036a4 | 2991 | return bfd_mach_x86_64; |
351f65ca L |
2992 | else |
2993 | return bfd_mach_x64_32; | |
8a9036a4 | 2994 | } |
5197d474 L |
2995 | else if (!strcmp (default_arch, "i386") |
2996 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2997 | { |
2998 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2999 | { | |
3000 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
3001 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
3002 | return bfd_mach_i386_iamcu; | |
3003 | } | |
3004 | else | |
3005 | return bfd_mach_i386_i386; | |
3006 | } | |
b9d79e03 | 3007 | else |
2b5d6a91 | 3008 | as_fatal (_("unknown architecture")); |
b9d79e03 | 3009 | } |
b9d79e03 | 3010 | \f |
252b5132 | 3011 | void |
7016a5d5 | 3012 | md_begin (void) |
252b5132 RH |
3013 | { |
3014 | const char *hash_err; | |
3015 | ||
86fa6981 L |
3016 | /* Support pseudo prefixes like {disp32}. */ |
3017 | lex_type ['{'] = LEX_BEGIN_NAME; | |
3018 | ||
47926f60 | 3019 | /* Initialize op_hash hash table. */ |
252b5132 RH |
3020 | op_hash = hash_new (); |
3021 | ||
3022 | { | |
d3ce72d0 | 3023 | const insn_template *optab; |
29b0f896 | 3024 | templates *core_optab; |
252b5132 | 3025 | |
47926f60 KH |
3026 | /* Setup for loop. */ |
3027 | optab = i386_optab; | |
add39d23 | 3028 | core_optab = XNEW (templates); |
252b5132 RH |
3029 | core_optab->start = optab; |
3030 | ||
3031 | while (1) | |
3032 | { | |
3033 | ++optab; | |
3034 | if (optab->name == NULL | |
3035 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
3036 | { | |
3037 | /* different name --> ship out current template list; | |
47926f60 | 3038 | add to hash table; & begin anew. */ |
252b5132 RH |
3039 | core_optab->end = optab; |
3040 | hash_err = hash_insert (op_hash, | |
3041 | (optab - 1)->name, | |
5a49b8ac | 3042 | (void *) core_optab); |
252b5132 RH |
3043 | if (hash_err) |
3044 | { | |
b37df7c4 | 3045 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
3046 | (optab - 1)->name, |
3047 | hash_err); | |
3048 | } | |
3049 | if (optab->name == NULL) | |
3050 | break; | |
add39d23 | 3051 | core_optab = XNEW (templates); |
252b5132 RH |
3052 | core_optab->start = optab; |
3053 | } | |
3054 | } | |
3055 | } | |
3056 | ||
47926f60 | 3057 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
3058 | reg_hash = hash_new (); |
3059 | { | |
29b0f896 | 3060 | const reg_entry *regtab; |
c3fe08fa | 3061 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3062 | |
c3fe08fa | 3063 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 3064 | { |
5a49b8ac | 3065 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 3066 | if (hash_err) |
b37df7c4 | 3067 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
3068 | regtab->reg_name, |
3069 | hash_err); | |
252b5132 RH |
3070 | } |
3071 | } | |
3072 | ||
47926f60 | 3073 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3074 | { |
29b0f896 AM |
3075 | int c; |
3076 | char *p; | |
252b5132 RH |
3077 | |
3078 | for (c = 0; c < 256; c++) | |
3079 | { | |
3882b010 | 3080 | if (ISDIGIT (c)) |
252b5132 RH |
3081 | { |
3082 | digit_chars[c] = c; | |
3083 | mnemonic_chars[c] = c; | |
3084 | register_chars[c] = c; | |
3085 | operand_chars[c] = c; | |
3086 | } | |
3882b010 | 3087 | else if (ISLOWER (c)) |
252b5132 RH |
3088 | { |
3089 | mnemonic_chars[c] = c; | |
3090 | register_chars[c] = c; | |
3091 | operand_chars[c] = c; | |
3092 | } | |
3882b010 | 3093 | else if (ISUPPER (c)) |
252b5132 | 3094 | { |
3882b010 | 3095 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3096 | register_chars[c] = mnemonic_chars[c]; |
3097 | operand_chars[c] = c; | |
3098 | } | |
43234a1e | 3099 | else if (c == '{' || c == '}') |
86fa6981 L |
3100 | { |
3101 | mnemonic_chars[c] = c; | |
3102 | operand_chars[c] = c; | |
3103 | } | |
252b5132 | 3104 | |
3882b010 | 3105 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3106 | identifier_chars[c] = c; |
3107 | else if (c >= 128) | |
3108 | { | |
3109 | identifier_chars[c] = c; | |
3110 | operand_chars[c] = c; | |
3111 | } | |
3112 | } | |
3113 | ||
3114 | #ifdef LEX_AT | |
3115 | identifier_chars['@'] = '@'; | |
32137342 NC |
3116 | #endif |
3117 | #ifdef LEX_QM | |
3118 | identifier_chars['?'] = '?'; | |
3119 | operand_chars['?'] = '?'; | |
252b5132 | 3120 | #endif |
252b5132 | 3121 | digit_chars['-'] = '-'; |
c0f3af97 | 3122 | mnemonic_chars['_'] = '_'; |
791fe849 | 3123 | mnemonic_chars['-'] = '-'; |
0003779b | 3124 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3125 | identifier_chars['_'] = '_'; |
3126 | identifier_chars['.'] = '.'; | |
3127 | ||
3128 | for (p = operand_special_chars; *p != '\0'; p++) | |
3129 | operand_chars[(unsigned char) *p] = *p; | |
3130 | } | |
3131 | ||
a4447b93 RH |
3132 | if (flag_code == CODE_64BIT) |
3133 | { | |
ca19b261 KT |
3134 | #if defined (OBJ_COFF) && defined (TE_PE) |
3135 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3136 | ? 32 : 16); | |
3137 | #else | |
a4447b93 | 3138 | x86_dwarf2_return_column = 16; |
ca19b261 | 3139 | #endif |
61ff971f | 3140 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3141 | } |
3142 | else | |
3143 | { | |
3144 | x86_dwarf2_return_column = 8; | |
3145 | x86_cie_data_alignment = -4; | |
3146 | } | |
e379e5f3 L |
3147 | |
3148 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3149 | can be turned into BRANCH_PREFIX frag. */ | |
3150 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3151 | abort (); | |
252b5132 RH |
3152 | } |
3153 | ||
3154 | void | |
e3bb37b5 | 3155 | i386_print_statistics (FILE *file) |
252b5132 RH |
3156 | { |
3157 | hash_print_statistics (file, "i386 opcode", op_hash); | |
3158 | hash_print_statistics (file, "i386 register", reg_hash); | |
3159 | } | |
3160 | \f | |
252b5132 RH |
3161 | #ifdef DEBUG386 |
3162 | ||
ce8a8b2f | 3163 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3164 | static void pte (insn_template *); |
40fb9820 | 3165 | static void pt (i386_operand_type); |
e3bb37b5 L |
3166 | static void pe (expressionS *); |
3167 | static void ps (symbolS *); | |
252b5132 RH |
3168 | |
3169 | static void | |
2c703856 | 3170 | pi (const char *line, i386_insn *x) |
252b5132 | 3171 | { |
09137c09 | 3172 | unsigned int j; |
252b5132 RH |
3173 | |
3174 | fprintf (stdout, "%s: template ", line); | |
3175 | pte (&x->tm); | |
09f131f2 JH |
3176 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3177 | x->base_reg ? x->base_reg->reg_name : "none", | |
3178 | x->index_reg ? x->index_reg->reg_name : "none", | |
3179 | x->log2_scale_factor); | |
3180 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3181 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3182 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3183 | x->sib.base, x->sib.index, x->sib.scale); | |
3184 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3185 | (x->rex & REX_W) != 0, |
3186 | (x->rex & REX_R) != 0, | |
3187 | (x->rex & REX_X) != 0, | |
3188 | (x->rex & REX_B) != 0); | |
09137c09 | 3189 | for (j = 0; j < x->operands; j++) |
252b5132 | 3190 | { |
09137c09 SP |
3191 | fprintf (stdout, " #%d: ", j + 1); |
3192 | pt (x->types[j]); | |
252b5132 | 3193 | fprintf (stdout, "\n"); |
bab6aec1 | 3194 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3195 | || x->types[j].bitfield.class == RegMMX |
3196 | || x->types[j].bitfield.class == RegSIMD | |
00cee14f | 3197 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3198 | || x->types[j].bitfield.class == RegCR |
3199 | || x->types[j].bitfield.class == RegDR | |
3200 | || x->types[j].bitfield.class == RegTR) | |
09137c09 SP |
3201 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3202 | if (operand_type_check (x->types[j], imm)) | |
3203 | pe (x->op[j].imms); | |
3204 | if (operand_type_check (x->types[j], disp)) | |
3205 | pe (x->op[j].disps); | |
252b5132 RH |
3206 | } |
3207 | } | |
3208 | ||
3209 | static void | |
d3ce72d0 | 3210 | pte (insn_template *t) |
252b5132 | 3211 | { |
09137c09 | 3212 | unsigned int j; |
252b5132 | 3213 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3214 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3215 | if (t->extension_opcode != None) |
3216 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3217 | if (t->opcode_modifier.d) |
252b5132 | 3218 | fprintf (stdout, "D"); |
40fb9820 | 3219 | if (t->opcode_modifier.w) |
252b5132 RH |
3220 | fprintf (stdout, "W"); |
3221 | fprintf (stdout, "\n"); | |
09137c09 | 3222 | for (j = 0; j < t->operands; j++) |
252b5132 | 3223 | { |
09137c09 SP |
3224 | fprintf (stdout, " #%d type ", j + 1); |
3225 | pt (t->operand_types[j]); | |
252b5132 RH |
3226 | fprintf (stdout, "\n"); |
3227 | } | |
3228 | } | |
3229 | ||
3230 | static void | |
e3bb37b5 | 3231 | pe (expressionS *e) |
252b5132 | 3232 | { |
24eab124 | 3233 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3234 | fprintf (stdout, " add_number %ld (%lx)\n", |
3235 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3236 | if (e->X_add_symbol) |
3237 | { | |
3238 | fprintf (stdout, " add_symbol "); | |
3239 | ps (e->X_add_symbol); | |
3240 | fprintf (stdout, "\n"); | |
3241 | } | |
3242 | if (e->X_op_symbol) | |
3243 | { | |
3244 | fprintf (stdout, " op_symbol "); | |
3245 | ps (e->X_op_symbol); | |
3246 | fprintf (stdout, "\n"); | |
3247 | } | |
3248 | } | |
3249 | ||
3250 | static void | |
e3bb37b5 | 3251 | ps (symbolS *s) |
252b5132 RH |
3252 | { |
3253 | fprintf (stdout, "%s type %s%s", | |
3254 | S_GET_NAME (s), | |
3255 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3256 | segment_name (S_GET_SEGMENT (s))); | |
3257 | } | |
3258 | ||
7b81dfbb | 3259 | static struct type_name |
252b5132 | 3260 | { |
40fb9820 L |
3261 | i386_operand_type mask; |
3262 | const char *name; | |
252b5132 | 3263 | } |
7b81dfbb | 3264 | const type_names[] = |
252b5132 | 3265 | { |
40fb9820 L |
3266 | { OPERAND_TYPE_REG8, "r8" }, |
3267 | { OPERAND_TYPE_REG16, "r16" }, | |
3268 | { OPERAND_TYPE_REG32, "r32" }, | |
3269 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3270 | { OPERAND_TYPE_ACC8, "acc8" }, |
3271 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3272 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3273 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3274 | { OPERAND_TYPE_IMM8, "i8" }, |
3275 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3276 | { OPERAND_TYPE_IMM16, "i16" }, | |
3277 | { OPERAND_TYPE_IMM32, "i32" }, | |
3278 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3279 | { OPERAND_TYPE_IMM64, "i64" }, | |
3280 | { OPERAND_TYPE_IMM1, "i1" }, | |
3281 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3282 | { OPERAND_TYPE_DISP8, "d8" }, | |
3283 | { OPERAND_TYPE_DISP16, "d16" }, | |
3284 | { OPERAND_TYPE_DISP32, "d32" }, | |
3285 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3286 | { OPERAND_TYPE_DISP64, "d64" }, | |
3287 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3288 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3289 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3290 | { OPERAND_TYPE_TEST, "test reg" }, | |
3291 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3292 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3293 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3294 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3295 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
3296 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3297 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3298 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3299 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
252b5132 RH |
3300 | }; |
3301 | ||
3302 | static void | |
40fb9820 | 3303 | pt (i386_operand_type t) |
252b5132 | 3304 | { |
40fb9820 | 3305 | unsigned int j; |
c6fb90c8 | 3306 | i386_operand_type a; |
252b5132 | 3307 | |
40fb9820 | 3308 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3309 | { |
3310 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3311 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3312 | fprintf (stdout, "%s, ", type_names[j].name); |
3313 | } | |
252b5132 RH |
3314 | fflush (stdout); |
3315 | } | |
3316 | ||
3317 | #endif /* DEBUG386 */ | |
3318 | \f | |
252b5132 | 3319 | static bfd_reloc_code_real_type |
3956db08 | 3320 | reloc (unsigned int size, |
64e74474 AM |
3321 | int pcrel, |
3322 | int sign, | |
3323 | bfd_reloc_code_real_type other) | |
252b5132 | 3324 | { |
47926f60 | 3325 | if (other != NO_RELOC) |
3956db08 | 3326 | { |
91d6fa6a | 3327 | reloc_howto_type *rel; |
3956db08 JB |
3328 | |
3329 | if (size == 8) | |
3330 | switch (other) | |
3331 | { | |
64e74474 AM |
3332 | case BFD_RELOC_X86_64_GOT32: |
3333 | return BFD_RELOC_X86_64_GOT64; | |
3334 | break; | |
553d1284 L |
3335 | case BFD_RELOC_X86_64_GOTPLT64: |
3336 | return BFD_RELOC_X86_64_GOTPLT64; | |
3337 | break; | |
64e74474 AM |
3338 | case BFD_RELOC_X86_64_PLTOFF64: |
3339 | return BFD_RELOC_X86_64_PLTOFF64; | |
3340 | break; | |
3341 | case BFD_RELOC_X86_64_GOTPC32: | |
3342 | other = BFD_RELOC_X86_64_GOTPC64; | |
3343 | break; | |
3344 | case BFD_RELOC_X86_64_GOTPCREL: | |
3345 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3346 | break; | |
3347 | case BFD_RELOC_X86_64_TPOFF32: | |
3348 | other = BFD_RELOC_X86_64_TPOFF64; | |
3349 | break; | |
3350 | case BFD_RELOC_X86_64_DTPOFF32: | |
3351 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3352 | break; | |
3353 | default: | |
3354 | break; | |
3956db08 | 3355 | } |
e05278af | 3356 | |
8ce3d284 | 3357 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3358 | if (other == BFD_RELOC_SIZE32) |
3359 | { | |
3360 | if (size == 8) | |
1ab668bf | 3361 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3362 | if (pcrel) |
1ab668bf AM |
3363 | { |
3364 | as_bad (_("there are no pc-relative size relocations")); | |
3365 | return NO_RELOC; | |
3366 | } | |
8fd4256d | 3367 | } |
8ce3d284 | 3368 | #endif |
8fd4256d | 3369 | |
e05278af | 3370 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3371 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3372 | sign = -1; |
3373 | ||
91d6fa6a NC |
3374 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3375 | if (!rel) | |
3956db08 | 3376 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3377 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3378 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3379 | bfd_get_reloc_size (rel), |
3956db08 | 3380 | size); |
91d6fa6a | 3381 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3382 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3383 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3384 | && !sign) |
91d6fa6a | 3385 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3386 | && sign > 0)) |
3956db08 JB |
3387 | as_bad (_("relocated field and relocation type differ in signedness")); |
3388 | else | |
3389 | return other; | |
3390 | return NO_RELOC; | |
3391 | } | |
252b5132 RH |
3392 | |
3393 | if (pcrel) | |
3394 | { | |
3e73aa7c | 3395 | if (!sign) |
3956db08 | 3396 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3397 | switch (size) |
3398 | { | |
3399 | case 1: return BFD_RELOC_8_PCREL; | |
3400 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3401 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3402 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3403 | } |
3956db08 | 3404 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3405 | } |
3406 | else | |
3407 | { | |
3956db08 | 3408 | if (sign > 0) |
e5cb08ac | 3409 | switch (size) |
3e73aa7c JH |
3410 | { |
3411 | case 4: return BFD_RELOC_X86_64_32S; | |
3412 | } | |
3413 | else | |
3414 | switch (size) | |
3415 | { | |
3416 | case 1: return BFD_RELOC_8; | |
3417 | case 2: return BFD_RELOC_16; | |
3418 | case 4: return BFD_RELOC_32; | |
3419 | case 8: return BFD_RELOC_64; | |
3420 | } | |
3956db08 JB |
3421 | as_bad (_("cannot do %s %u byte relocation"), |
3422 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3423 | } |
3424 | ||
0cc9e1d3 | 3425 | return NO_RELOC; |
252b5132 RH |
3426 | } |
3427 | ||
47926f60 KH |
3428 | /* Here we decide which fixups can be adjusted to make them relative to |
3429 | the beginning of the section instead of the symbol. Basically we need | |
3430 | to make sure that the dynamic relocations are done correctly, so in | |
3431 | some cases we force the original symbol to be used. */ | |
3432 | ||
252b5132 | 3433 | int |
e3bb37b5 | 3434 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3435 | { |
6d249963 | 3436 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3437 | if (!IS_ELF) |
31312f95 AM |
3438 | return 1; |
3439 | ||
a161fe53 AM |
3440 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3441 | mode. */ | |
3442 | if (use_rela_relocations | |
3443 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3444 | && fixP->fx_pcrel) | |
252b5132 | 3445 | return 0; |
31312f95 | 3446 | |
8d01d9a9 AJ |
3447 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3448 | and changed later by validate_fix. */ | |
3449 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3450 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3451 | return 0; | |
3452 | ||
8fd4256d L |
3453 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3454 | for size relocations. */ | |
3455 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3456 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3457 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3458 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3459 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3460 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3461 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3462 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3463 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3464 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3465 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3466 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3467 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3468 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3469 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3470 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3471 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3472 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3473 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3474 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3475 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3476 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3477 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3478 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3479 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3480 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3481 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3482 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3483 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3484 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3485 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3486 | return 0; | |
31312f95 | 3487 | #endif |
252b5132 RH |
3488 | return 1; |
3489 | } | |
252b5132 | 3490 | |
b4cac588 | 3491 | static int |
e3bb37b5 | 3492 | intel_float_operand (const char *mnemonic) |
252b5132 | 3493 | { |
9306ca4a JB |
3494 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3495 | operands, hence the code here is free to improperly handle opcodes that | |
3496 | have no operands (for better performance and smaller code). */ | |
3497 | ||
3498 | if (mnemonic[0] != 'f') | |
3499 | return 0; /* non-math */ | |
3500 | ||
3501 | switch (mnemonic[1]) | |
3502 | { | |
3503 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3504 | the fs segment override prefix not currently handled because no | |
3505 | call path can make opcodes without operands get here */ | |
3506 | case 'i': | |
3507 | return 2 /* integer op */; | |
3508 | case 'l': | |
3509 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3510 | return 3; /* fldcw/fldenv */ | |
3511 | break; | |
3512 | case 'n': | |
3513 | if (mnemonic[2] != 'o' /* fnop */) | |
3514 | return 3; /* non-waiting control op */ | |
3515 | break; | |
3516 | case 'r': | |
3517 | if (mnemonic[2] == 's') | |
3518 | return 3; /* frstor/frstpm */ | |
3519 | break; | |
3520 | case 's': | |
3521 | if (mnemonic[2] == 'a') | |
3522 | return 3; /* fsave */ | |
3523 | if (mnemonic[2] == 't') | |
3524 | { | |
3525 | switch (mnemonic[3]) | |
3526 | { | |
3527 | case 'c': /* fstcw */ | |
3528 | case 'd': /* fstdw */ | |
3529 | case 'e': /* fstenv */ | |
3530 | case 's': /* fsts[gw] */ | |
3531 | return 3; | |
3532 | } | |
3533 | } | |
3534 | break; | |
3535 | case 'x': | |
3536 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3537 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3538 | break; | |
3539 | } | |
252b5132 | 3540 | |
9306ca4a | 3541 | return 1; |
252b5132 RH |
3542 | } |
3543 | ||
c0f3af97 L |
3544 | /* Build the VEX prefix. */ |
3545 | ||
3546 | static void | |
d3ce72d0 | 3547 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3548 | { |
3549 | unsigned int register_specifier; | |
3550 | unsigned int implied_prefix; | |
3551 | unsigned int vector_length; | |
03751133 | 3552 | unsigned int w; |
c0f3af97 L |
3553 | |
3554 | /* Check register specifier. */ | |
3555 | if (i.vex.register_specifier) | |
43234a1e L |
3556 | { |
3557 | register_specifier = | |
3558 | ~register_number (i.vex.register_specifier) & 0xf; | |
3559 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3560 | } | |
c0f3af97 L |
3561 | else |
3562 | register_specifier = 0xf; | |
3563 | ||
79f0fa25 L |
3564 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3565 | if there are more than 1 register operand. */ | |
3566 | if (i.reg_operands > 1 | |
3567 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3568 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3569 | && i.operands == i.reg_operands |
dbbc8b7e | 3570 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3571 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3572 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3573 | && i.rex == REX_B) |
3574 | { | |
3575 | unsigned int xchg = i.operands - 1; | |
3576 | union i386_op temp_op; | |
3577 | i386_operand_type temp_type; | |
3578 | ||
3579 | temp_type = i.types[xchg]; | |
3580 | i.types[xchg] = i.types[0]; | |
3581 | i.types[0] = temp_type; | |
3582 | temp_op = i.op[xchg]; | |
3583 | i.op[xchg] = i.op[0]; | |
3584 | i.op[0] = temp_op; | |
3585 | ||
9c2799c2 | 3586 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3587 | |
3588 | i.rex = REX_R; | |
3589 | xchg = i.rm.regmem; | |
3590 | i.rm.regmem = i.rm.reg; | |
3591 | i.rm.reg = xchg; | |
3592 | ||
dbbc8b7e JB |
3593 | if (i.tm.opcode_modifier.d) |
3594 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3595 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3596 | else /* Use the next insn. */ | |
3597 | i.tm = t[1]; | |
fa99fab2 L |
3598 | } |
3599 | ||
79dec6b7 JB |
3600 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3601 | are no memory operands and at least 3 register ones. */ | |
3602 | if (i.reg_operands >= 3 | |
3603 | && i.vec_encoding != vex_encoding_vex3 | |
3604 | && i.reg_operands == i.operands - i.imm_operands | |
3605 | && i.tm.opcode_modifier.vex | |
3606 | && i.tm.opcode_modifier.commutative | |
3607 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3608 | && i.rex == REX_B | |
3609 | && i.vex.register_specifier | |
3610 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3611 | { | |
3612 | unsigned int xchg = i.operands - i.reg_operands; | |
3613 | union i386_op temp_op; | |
3614 | i386_operand_type temp_type; | |
3615 | ||
3616 | gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F); | |
3617 | gas_assert (!i.tm.opcode_modifier.sae); | |
3618 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3619 | &i.types[i.operands - 3])); | |
3620 | gas_assert (i.rm.mode == 3); | |
3621 | ||
3622 | temp_type = i.types[xchg]; | |
3623 | i.types[xchg] = i.types[xchg + 1]; | |
3624 | i.types[xchg + 1] = temp_type; | |
3625 | temp_op = i.op[xchg]; | |
3626 | i.op[xchg] = i.op[xchg + 1]; | |
3627 | i.op[xchg + 1] = temp_op; | |
3628 | ||
3629 | i.rex = 0; | |
3630 | xchg = i.rm.regmem | 8; | |
3631 | i.rm.regmem = ~register_specifier & 0xf; | |
3632 | gas_assert (!(i.rm.regmem & 8)); | |
3633 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3634 | register_specifier = ~xchg & 0xf; | |
3635 | } | |
3636 | ||
539f890d L |
3637 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3638 | vector_length = avxscalar; | |
10c17abd JB |
3639 | else if (i.tm.opcode_modifier.vex == VEX256) |
3640 | vector_length = 1; | |
539f890d | 3641 | else |
10c17abd | 3642 | { |
56522fc5 | 3643 | unsigned int op; |
10c17abd | 3644 | |
c7213af9 L |
3645 | /* Determine vector length from the last multi-length vector |
3646 | operand. */ | |
10c17abd | 3647 | vector_length = 0; |
56522fc5 | 3648 | for (op = t->operands; op--;) |
10c17abd JB |
3649 | if (t->operand_types[op].bitfield.xmmword |
3650 | && t->operand_types[op].bitfield.ymmword | |
3651 | && i.types[op].bitfield.ymmword) | |
3652 | { | |
3653 | vector_length = 1; | |
3654 | break; | |
3655 | } | |
3656 | } | |
c0f3af97 L |
3657 | |
3658 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3659 | { | |
3660 | case 0: | |
3661 | implied_prefix = 0; | |
3662 | break; | |
3663 | case DATA_PREFIX_OPCODE: | |
3664 | implied_prefix = 1; | |
3665 | break; | |
3666 | case REPE_PREFIX_OPCODE: | |
3667 | implied_prefix = 2; | |
3668 | break; | |
3669 | case REPNE_PREFIX_OPCODE: | |
3670 | implied_prefix = 3; | |
3671 | break; | |
3672 | default: | |
3673 | abort (); | |
3674 | } | |
3675 | ||
03751133 L |
3676 | /* Check the REX.W bit and VEXW. */ |
3677 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3678 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3679 | else if (i.tm.opcode_modifier.vexw) | |
3680 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3681 | else | |
931d03b7 | 3682 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3683 | |
c0f3af97 | 3684 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3685 | if (w == 0 |
3686 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3687 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3688 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3689 | { | |
3690 | /* 2-byte VEX prefix. */ | |
3691 | unsigned int r; | |
3692 | ||
3693 | i.vex.length = 2; | |
3694 | i.vex.bytes[0] = 0xc5; | |
3695 | ||
3696 | /* Check the REX.R bit. */ | |
3697 | r = (i.rex & REX_R) ? 0 : 1; | |
3698 | i.vex.bytes[1] = (r << 7 | |
3699 | | register_specifier << 3 | |
3700 | | vector_length << 2 | |
3701 | | implied_prefix); | |
3702 | } | |
3703 | else | |
3704 | { | |
3705 | /* 3-byte VEX prefix. */ | |
03751133 | 3706 | unsigned int m; |
c0f3af97 | 3707 | |
f88c9eb0 | 3708 | i.vex.length = 3; |
f88c9eb0 | 3709 | |
7f399153 | 3710 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3711 | { |
7f399153 L |
3712 | case VEX0F: |
3713 | m = 0x1; | |
80de6e00 | 3714 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3715 | break; |
3716 | case VEX0F38: | |
3717 | m = 0x2; | |
80de6e00 | 3718 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3719 | break; |
3720 | case VEX0F3A: | |
3721 | m = 0x3; | |
80de6e00 | 3722 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3723 | break; |
3724 | case XOP08: | |
5dd85c99 SP |
3725 | m = 0x8; |
3726 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3727 | break; |
3728 | case XOP09: | |
f88c9eb0 SP |
3729 | m = 0x9; |
3730 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3731 | break; |
3732 | case XOP0A: | |
f88c9eb0 SP |
3733 | m = 0xa; |
3734 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3735 | break; |
3736 | default: | |
3737 | abort (); | |
f88c9eb0 | 3738 | } |
c0f3af97 | 3739 | |
c0f3af97 L |
3740 | /* The high 3 bits of the second VEX byte are 1's compliment |
3741 | of RXB bits from REX. */ | |
3742 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3743 | ||
c0f3af97 L |
3744 | i.vex.bytes[2] = (w << 7 |
3745 | | register_specifier << 3 | |
3746 | | vector_length << 2 | |
3747 | | implied_prefix); | |
3748 | } | |
3749 | } | |
3750 | ||
e771e7c9 JB |
3751 | static INLINE bfd_boolean |
3752 | is_evex_encoding (const insn_template *t) | |
3753 | { | |
7091c612 | 3754 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3755 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3756 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3757 | } |
3758 | ||
7a8655d2 JB |
3759 | static INLINE bfd_boolean |
3760 | is_any_vex_encoding (const insn_template *t) | |
3761 | { | |
3762 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3763 | || is_evex_encoding (t); | |
3764 | } | |
3765 | ||
43234a1e L |
3766 | /* Build the EVEX prefix. */ |
3767 | ||
3768 | static void | |
3769 | build_evex_prefix (void) | |
3770 | { | |
3771 | unsigned int register_specifier; | |
3772 | unsigned int implied_prefix; | |
3773 | unsigned int m, w; | |
3774 | rex_byte vrex_used = 0; | |
3775 | ||
3776 | /* Check register specifier. */ | |
3777 | if (i.vex.register_specifier) | |
3778 | { | |
3779 | gas_assert ((i.vrex & REX_X) == 0); | |
3780 | ||
3781 | register_specifier = i.vex.register_specifier->reg_num; | |
3782 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3783 | register_specifier += 8; | |
3784 | /* The upper 16 registers are encoded in the fourth byte of the | |
3785 | EVEX prefix. */ | |
3786 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3787 | i.vex.bytes[3] = 0x8; | |
3788 | register_specifier = ~register_specifier & 0xf; | |
3789 | } | |
3790 | else | |
3791 | { | |
3792 | register_specifier = 0xf; | |
3793 | ||
3794 | /* Encode upper 16 vector index register in the fourth byte of | |
3795 | the EVEX prefix. */ | |
3796 | if (!(i.vrex & REX_X)) | |
3797 | i.vex.bytes[3] = 0x8; | |
3798 | else | |
3799 | vrex_used |= REX_X; | |
3800 | } | |
3801 | ||
3802 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3803 | { | |
3804 | case 0: | |
3805 | implied_prefix = 0; | |
3806 | break; | |
3807 | case DATA_PREFIX_OPCODE: | |
3808 | implied_prefix = 1; | |
3809 | break; | |
3810 | case REPE_PREFIX_OPCODE: | |
3811 | implied_prefix = 2; | |
3812 | break; | |
3813 | case REPNE_PREFIX_OPCODE: | |
3814 | implied_prefix = 3; | |
3815 | break; | |
3816 | default: | |
3817 | abort (); | |
3818 | } | |
3819 | ||
3820 | /* 4 byte EVEX prefix. */ | |
3821 | i.vex.length = 4; | |
3822 | i.vex.bytes[0] = 0x62; | |
3823 | ||
3824 | /* mmmm bits. */ | |
3825 | switch (i.tm.opcode_modifier.vexopcode) | |
3826 | { | |
3827 | case VEX0F: | |
3828 | m = 1; | |
3829 | break; | |
3830 | case VEX0F38: | |
3831 | m = 2; | |
3832 | break; | |
3833 | case VEX0F3A: | |
3834 | m = 3; | |
3835 | break; | |
3836 | default: | |
3837 | abort (); | |
3838 | break; | |
3839 | } | |
3840 | ||
3841 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3842 | bits from REX. */ | |
3843 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3844 | ||
3845 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3846 | REX_R bit in VREX. */ | |
3847 | if (!(i.vrex & REX_R)) | |
3848 | i.vex.bytes[1] |= 0x10; | |
3849 | else | |
3850 | vrex_used |= REX_R; | |
3851 | ||
3852 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3853 | { | |
3854 | /* When all operands are registers, the REX_X bit in REX is not | |
3855 | used. We reuse it to encode the upper 16 registers, which is | |
3856 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3857 | as 1's compliment. */ | |
3858 | if ((i.vrex & REX_B)) | |
3859 | { | |
3860 | vrex_used |= REX_B; | |
3861 | i.vex.bytes[1] &= ~0x40; | |
3862 | } | |
3863 | } | |
3864 | ||
3865 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3866 | i.vrex &= ~vrex_used; | |
3867 | gas_assert (i.vrex == 0); | |
3868 | ||
6865c043 L |
3869 | /* Check the REX.W bit and VEXW. */ |
3870 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3871 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3872 | else if (i.tm.opcode_modifier.vexw) | |
3873 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3874 | else | |
931d03b7 | 3875 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3876 | |
3877 | /* Encode the U bit. */ | |
3878 | implied_prefix |= 0x4; | |
3879 | ||
3880 | /* The third byte of the EVEX prefix. */ | |
3881 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3882 | ||
3883 | /* The fourth byte of the EVEX prefix. */ | |
3884 | /* The zeroing-masking bit. */ | |
3885 | if (i.mask && i.mask->zeroing) | |
3886 | i.vex.bytes[3] |= 0x80; | |
3887 | ||
3888 | /* Don't always set the broadcast bit if there is no RC. */ | |
3889 | if (!i.rounding) | |
3890 | { | |
3891 | /* Encode the vector length. */ | |
3892 | unsigned int vec_length; | |
3893 | ||
e771e7c9 JB |
3894 | if (!i.tm.opcode_modifier.evex |
3895 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3896 | { | |
56522fc5 | 3897 | unsigned int op; |
e771e7c9 | 3898 | |
c7213af9 L |
3899 | /* Determine vector length from the last multi-length vector |
3900 | operand. */ | |
e771e7c9 | 3901 | vec_length = 0; |
56522fc5 | 3902 | for (op = i.operands; op--;) |
e771e7c9 JB |
3903 | if (i.tm.operand_types[op].bitfield.xmmword |
3904 | + i.tm.operand_types[op].bitfield.ymmword | |
3905 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3906 | { | |
3907 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3908 | { |
3909 | i.tm.opcode_modifier.evex = EVEX512; | |
3910 | break; | |
3911 | } | |
e771e7c9 | 3912 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3913 | { |
3914 | i.tm.opcode_modifier.evex = EVEX256; | |
3915 | break; | |
3916 | } | |
e771e7c9 | 3917 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3918 | { |
3919 | i.tm.opcode_modifier.evex = EVEX128; | |
3920 | break; | |
3921 | } | |
625cbd7a JB |
3922 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3923 | { | |
4a1b91ea | 3924 | switch (i.broadcast->bytes) |
625cbd7a JB |
3925 | { |
3926 | case 64: | |
3927 | i.tm.opcode_modifier.evex = EVEX512; | |
3928 | break; | |
3929 | case 32: | |
3930 | i.tm.opcode_modifier.evex = EVEX256; | |
3931 | break; | |
3932 | case 16: | |
3933 | i.tm.opcode_modifier.evex = EVEX128; | |
3934 | break; | |
3935 | default: | |
c7213af9 | 3936 | abort (); |
625cbd7a | 3937 | } |
c7213af9 | 3938 | break; |
625cbd7a | 3939 | } |
e771e7c9 | 3940 | } |
c7213af9 | 3941 | |
56522fc5 | 3942 | if (op >= MAX_OPERANDS) |
c7213af9 | 3943 | abort (); |
e771e7c9 JB |
3944 | } |
3945 | ||
43234a1e L |
3946 | switch (i.tm.opcode_modifier.evex) |
3947 | { | |
3948 | case EVEXLIG: /* LL' is ignored */ | |
3949 | vec_length = evexlig << 5; | |
3950 | break; | |
3951 | case EVEX128: | |
3952 | vec_length = 0 << 5; | |
3953 | break; | |
3954 | case EVEX256: | |
3955 | vec_length = 1 << 5; | |
3956 | break; | |
3957 | case EVEX512: | |
3958 | vec_length = 2 << 5; | |
3959 | break; | |
3960 | default: | |
3961 | abort (); | |
3962 | break; | |
3963 | } | |
3964 | i.vex.bytes[3] |= vec_length; | |
3965 | /* Encode the broadcast bit. */ | |
3966 | if (i.broadcast) | |
3967 | i.vex.bytes[3] |= 0x10; | |
3968 | } | |
3969 | else | |
3970 | { | |
3971 | if (i.rounding->type != saeonly) | |
3972 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3973 | else | |
d3d3c6db | 3974 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3975 | } |
3976 | ||
3977 | if (i.mask && i.mask->mask) | |
3978 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3979 | } | |
3980 | ||
65da13b5 L |
3981 | static void |
3982 | process_immext (void) | |
3983 | { | |
3984 | expressionS *exp; | |
3985 | ||
c0f3af97 | 3986 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3987 | which is coded in the same place as an 8-bit immediate field |
3988 | would be. Here we fake an 8-bit immediate operand from the | |
3989 | opcode suffix stored in tm.extension_opcode. | |
3990 | ||
c1e679ec | 3991 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3992 | 3 argument instructions. */ |
65da13b5 | 3993 | |
43234a1e | 3994 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3995 | && (i.operands <= 2 |
7a8655d2 | 3996 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3997 | && i.operands <= 4))); |
65da13b5 L |
3998 | |
3999 | exp = &im_expressions[i.imm_operands++]; | |
4000 | i.op[i.operands].imms = exp; | |
4001 | i.types[i.operands] = imm8; | |
4002 | i.operands++; | |
4003 | exp->X_op = O_constant; | |
4004 | exp->X_add_number = i.tm.extension_opcode; | |
4005 | i.tm.extension_opcode = None; | |
4006 | } | |
4007 | ||
42164a71 L |
4008 | |
4009 | static int | |
4010 | check_hle (void) | |
4011 | { | |
4012 | switch (i.tm.opcode_modifier.hleprefixok) | |
4013 | { | |
4014 | default: | |
4015 | abort (); | |
82c2def5 | 4016 | case HLEPrefixNone: |
165de32a L |
4017 | as_bad (_("invalid instruction `%s' after `%s'"), |
4018 | i.tm.name, i.hle_prefix); | |
42164a71 | 4019 | return 0; |
82c2def5 | 4020 | case HLEPrefixLock: |
42164a71 L |
4021 | if (i.prefix[LOCK_PREFIX]) |
4022 | return 1; | |
165de32a | 4023 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 4024 | return 0; |
82c2def5 | 4025 | case HLEPrefixAny: |
42164a71 | 4026 | return 1; |
82c2def5 | 4027 | case HLEPrefixRelease: |
42164a71 L |
4028 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4029 | { | |
4030 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
4031 | i.tm.name); | |
4032 | return 0; | |
4033 | } | |
8dc0818e | 4034 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4035 | { |
4036 | as_bad (_("memory destination needed for instruction `%s'" | |
4037 | " after `xrelease'"), i.tm.name); | |
4038 | return 0; | |
4039 | } | |
4040 | return 1; | |
4041 | } | |
4042 | } | |
4043 | ||
b6f8c7c4 L |
4044 | /* Try the shortest encoding by shortening operand size. */ |
4045 | ||
4046 | static void | |
4047 | optimize_encoding (void) | |
4048 | { | |
a0a1771e | 4049 | unsigned int j; |
b6f8c7c4 L |
4050 | |
4051 | if (optimize_for_space | |
72aea328 | 4052 | && !is_any_vex_encoding (&i.tm) |
b6f8c7c4 L |
4053 | && i.reg_operands == 1 |
4054 | && i.imm_operands == 1 | |
4055 | && !i.types[1].bitfield.byte | |
4056 | && i.op[0].imms->X_op == O_constant | |
4057 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
72aea328 | 4058 | && (i.tm.base_opcode == 0xa8 |
b6f8c7c4 L |
4059 | || (i.tm.base_opcode == 0xf6 |
4060 | && i.tm.extension_opcode == 0x0))) | |
4061 | { | |
4062 | /* Optimize: -Os: | |
4063 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4064 | */ | |
4065 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4066 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4067 | { | |
4068 | i.types[1].bitfield.byte = 1; | |
4069 | /* Ignore the suffix. */ | |
4070 | i.suffix = 0; | |
7697afb6 JB |
4071 | /* Convert to byte registers. */ |
4072 | if (i.types[1].bitfield.word) | |
4073 | j = 16; | |
4074 | else if (i.types[1].bitfield.dword) | |
4075 | j = 32; | |
4076 | else | |
4077 | j = 48; | |
4078 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4079 | j += 8; | |
4080 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4081 | } |
4082 | } | |
4083 | else if (flag_code == CODE_64BIT | |
72aea328 | 4084 | && !is_any_vex_encoding (&i.tm) |
d3d50934 L |
4085 | && ((i.types[1].bitfield.qword |
4086 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4087 | && i.imm_operands == 1 |
4088 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4089 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4090 | && i.tm.extension_opcode == None |
4091 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4092 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
72aea328 JB |
4093 | && ((i.tm.base_opcode == 0x24 |
4094 | || i.tm.base_opcode == 0xa8) | |
b6f8c7c4 L |
4095 | || (i.tm.base_opcode == 0x80 |
4096 | && i.tm.extension_opcode == 0x4) | |
4097 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4098 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4099 | && i.tm.extension_opcode == 0x0))) |
4100 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4101 | && i.tm.base_opcode == 0x83 | |
4102 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4103 | || (i.types[0].bitfield.qword |
4104 | && ((i.reg_operands == 2 | |
4105 | && i.op[0].regs == i.op[1].regs | |
72aea328 JB |
4106 | && (i.tm.base_opcode == 0x30 |
4107 | || i.tm.base_opcode == 0x28)) | |
d3d50934 L |
4108 | || (i.reg_operands == 1 |
4109 | && i.operands == 1 | |
72aea328 | 4110 | && i.tm.base_opcode == 0x30))))) |
b6f8c7c4 L |
4111 | { |
4112 | /* Optimize: -O: | |
4113 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4114 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4115 | testq $imm31, %r64 -> testl $imm31, %r32 |
4116 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4117 | subq %r64, %r64 -> subl %r32, %r32 | |
4118 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4119 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4120 | */ | |
4121 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4122 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4123 | { |
4124 | /* Handle | |
4125 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4126 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4127 | */ | |
4128 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4129 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4130 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4131 | i.types[0].bitfield.imm32 = 1; | |
4132 | i.types[0].bitfield.imm32s = 0; | |
4133 | i.types[0].bitfield.imm64 = 0; | |
4134 | i.types[1].bitfield.dword = 1; | |
4135 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4136 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4137 | { |
4138 | /* Handle | |
4139 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4140 | */ | |
507916b8 | 4141 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4142 | i.tm.extension_opcode = None; |
507916b8 | 4143 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4144 | i.tm.opcode_modifier.modrm = 0; |
4145 | } | |
4146 | } | |
4147 | } | |
5641ec01 JB |
4148 | else if (optimize > 1 |
4149 | && !optimize_for_space | |
72aea328 | 4150 | && !is_any_vex_encoding (&i.tm) |
5641ec01 JB |
4151 | && i.reg_operands == 2 |
4152 | && i.op[0].regs == i.op[1].regs | |
4153 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4154 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4155 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4156 | { | |
4157 | /* Optimize: -O2: | |
4158 | andb %rN, %rN -> testb %rN, %rN | |
4159 | andw %rN, %rN -> testw %rN, %rN | |
4160 | andq %rN, %rN -> testq %rN, %rN | |
4161 | orb %rN, %rN -> testb %rN, %rN | |
4162 | orw %rN, %rN -> testw %rN, %rN | |
4163 | orq %rN, %rN -> testq %rN, %rN | |
4164 | ||
4165 | and outside of 64-bit mode | |
4166 | ||
4167 | andl %rN, %rN -> testl %rN, %rN | |
4168 | orl %rN, %rN -> testl %rN, %rN | |
4169 | */ | |
4170 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4171 | } | |
99112332 | 4172 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4173 | && i.op[0].regs == i.op[1].regs |
4174 | && !i.types[2].bitfield.xmmword | |
4175 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 4176 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 4177 | && !i.rounding |
e771e7c9 | 4178 | && is_evex_encoding (&i.tm) |
80c34c38 | 4179 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4180 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4181 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4182 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4183 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
4184 | && ((i.tm.base_opcode == 0x55 |
4185 | || i.tm.base_opcode == 0x6655 | |
4186 | || i.tm.base_opcode == 0x66df | |
4187 | || i.tm.base_opcode == 0x57 | |
4188 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4189 | || i.tm.base_opcode == 0x66ef |
4190 | || i.tm.base_opcode == 0x66f8 | |
4191 | || i.tm.base_opcode == 0x66f9 | |
4192 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4193 | || i.tm.base_opcode == 0x66fb |
4194 | || i.tm.base_opcode == 0x42 | |
4195 | || i.tm.base_opcode == 0x6642 | |
4196 | || i.tm.base_opcode == 0x47 | |
4197 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4198 | && i.tm.extension_opcode == None)) |
4199 | { | |
99112332 | 4200 | /* Optimize: -O1: |
8305403a L |
4201 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4202 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4203 | EVEX VOP %zmmM, %zmmM, %zmmN |
4204 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4205 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4206 | EVEX VOP %ymmM, %ymmM, %ymmN |
4207 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4208 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4209 | VEX VOP %ymmM, %ymmM, %ymmN |
4210 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4211 | VOP, one of vpandn and vpxor: | |
4212 | VEX VOP %ymmM, %ymmM, %ymmN | |
4213 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4214 | VOP, one of vpandnd and vpandnq: | |
4215 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4216 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4217 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4218 | EVEX VOP %ymmM, %ymmM, %ymmN |
4219 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4220 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4221 | VOP, one of vpxord and vpxorq: |
4222 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4223 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4224 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4225 | EVEX VOP %ymmM, %ymmM, %ymmN |
4226 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4227 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4228 | VOP, one of kxord and kxorq: |
4229 | VEX VOP %kM, %kM, %kN | |
4230 | -> VEX kxorw %kM, %kM, %kN | |
4231 | VOP, one of kandnd and kandnq: | |
4232 | VEX VOP %kM, %kM, %kN | |
4233 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4234 | */ |
e771e7c9 | 4235 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4236 | { |
7b1d7ca1 | 4237 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4238 | { |
4239 | i.tm.opcode_modifier.vex = VEX128; | |
4240 | i.tm.opcode_modifier.vexw = VEXW0; | |
4241 | i.tm.opcode_modifier.evex = 0; | |
4242 | } | |
7b1d7ca1 | 4243 | else if (optimize > 1) |
dd22218c L |
4244 | i.tm.opcode_modifier.evex = EVEX128; |
4245 | else | |
4246 | return; | |
b6f8c7c4 | 4247 | } |
f74a6307 | 4248 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 JB |
4249 | { |
4250 | i.tm.base_opcode &= 0xff; | |
4251 | i.tm.opcode_modifier.vexw = VEXW0; | |
4252 | } | |
b6f8c7c4 L |
4253 | else |
4254 | i.tm.opcode_modifier.vex = VEX128; | |
4255 | ||
4256 | if (i.tm.opcode_modifier.vex) | |
4257 | for (j = 0; j < 3; j++) | |
4258 | { | |
4259 | i.types[j].bitfield.xmmword = 1; | |
4260 | i.types[j].bitfield.ymmword = 0; | |
4261 | } | |
4262 | } | |
392a5972 | 4263 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4264 | && !i.types[0].bitfield.zmmword |
392a5972 | 4265 | && !i.types[1].bitfield.zmmword |
97ed31ae | 4266 | && !i.mask |
a0a1771e | 4267 | && !i.broadcast |
97ed31ae | 4268 | && is_evex_encoding (&i.tm) |
392a5972 L |
4269 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4270 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
a0a1771e JB |
4271 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f |
4272 | || (i.tm.base_opcode & ~4) == 0x66db | |
4273 | || (i.tm.base_opcode & ~4) == 0x66eb) | |
97ed31ae L |
4274 | && i.tm.extension_opcode == None) |
4275 | { | |
4276 | /* Optimize: -O1: | |
4277 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4278 | vmovdqu32 and vmovdqu64: | |
4279 | EVEX VOP %xmmM, %xmmN | |
4280 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4281 | EVEX VOP %ymmM, %ymmN | |
4282 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4283 | EVEX VOP %xmmM, mem | |
4284 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4285 | EVEX VOP %ymmM, mem | |
4286 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4287 | EVEX VOP mem, %xmmN | |
4288 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4289 | EVEX VOP mem, %ymmN | |
4290 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4291 | VOP, one of vpand, vpandn, vpor, vpxor: |
4292 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4293 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4294 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4295 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4296 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4297 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4298 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4299 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4300 | */ |
a0a1771e | 4301 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4302 | if (operand_type_check (i.types[j], disp) |
4303 | && i.op[j].disps->X_op == O_constant) | |
4304 | { | |
4305 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4306 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4307 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4308 | int evex_disp8, vex_disp8; | |
4309 | unsigned int memshift = i.memshift; | |
4310 | offsetT n = i.op[j].disps->X_add_number; | |
4311 | ||
4312 | evex_disp8 = fits_in_disp8 (n); | |
4313 | i.memshift = 0; | |
4314 | vex_disp8 = fits_in_disp8 (n); | |
4315 | if (evex_disp8 != vex_disp8) | |
4316 | { | |
4317 | i.memshift = memshift; | |
4318 | return; | |
4319 | } | |
4320 | ||
4321 | i.types[j].bitfield.disp8 = vex_disp8; | |
4322 | break; | |
4323 | } | |
4324 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4325 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4326 | i.tm.opcode_modifier.vex |
4327 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4328 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 JB |
4329 | /* VPAND, VPOR, and VPXOR are commutative. */ |
4330 | if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df) | |
4331 | i.tm.opcode_modifier.commutative = 1; | |
97ed31ae L |
4332 | i.tm.opcode_modifier.evex = 0; |
4333 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4334 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4335 | i.tm.opcode_modifier.disp8memshift = 0; |
4336 | i.memshift = 0; | |
a0a1771e JB |
4337 | if (j < i.operands) |
4338 | i.types[j].bitfield.disp8 | |
4339 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4340 | } |
b6f8c7c4 L |
4341 | } |
4342 | ||
ae531041 L |
4343 | /* Return non-zero for load instruction. */ |
4344 | ||
4345 | static int | |
4346 | load_insn_p (void) | |
4347 | { | |
4348 | unsigned int dest; | |
4349 | int any_vex_p = is_any_vex_encoding (&i.tm); | |
4350 | unsigned int base_opcode = i.tm.base_opcode | 1; | |
4351 | ||
4352 | if (!any_vex_p) | |
4353 | { | |
a09f656b | 4354 | /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0, |
4355 | prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn, | |
4356 | bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */ | |
4357 | if (i.tm.opcode_modifier.anysize) | |
ae531041 L |
4358 | return 0; |
4359 | ||
a09f656b | 4360 | /* pop, popf, popa. */ |
4361 | if (strcmp (i.tm.name, "pop") == 0 | |
4362 | || i.tm.base_opcode == 0x9d | |
4363 | || i.tm.base_opcode == 0x61) | |
ae531041 L |
4364 | return 1; |
4365 | ||
4366 | /* movs, cmps, lods, scas. */ | |
4367 | if ((i.tm.base_opcode | 0xb) == 0xaf) | |
4368 | return 1; | |
4369 | ||
a09f656b | 4370 | /* outs, xlatb. */ |
4371 | if (base_opcode == 0x6f | |
4372 | || i.tm.base_opcode == 0xd7) | |
ae531041 | 4373 | return 1; |
a09f656b | 4374 | /* NB: For AMD-specific insns with implicit memory operands, |
4375 | they're intentionally not covered. */ | |
ae531041 L |
4376 | } |
4377 | ||
4378 | /* No memory operand. */ | |
4379 | if (!i.mem_operands) | |
4380 | return 0; | |
4381 | ||
4382 | if (any_vex_p) | |
4383 | { | |
4384 | /* vldmxcsr. */ | |
4385 | if (i.tm.base_opcode == 0xae | |
4386 | && i.tm.opcode_modifier.vex | |
4387 | && i.tm.opcode_modifier.vexopcode == VEX0F | |
4388 | && i.tm.extension_opcode == 2) | |
4389 | return 1; | |
4390 | } | |
4391 | else | |
4392 | { | |
4393 | /* test, not, neg, mul, imul, div, idiv. */ | |
4394 | if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7) | |
4395 | && i.tm.extension_opcode != 1) | |
4396 | return 1; | |
4397 | ||
4398 | /* inc, dec. */ | |
4399 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) | |
4400 | return 1; | |
4401 | ||
4402 | /* add, or, adc, sbb, and, sub, xor, cmp. */ | |
4403 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) | |
4404 | return 1; | |
4405 | ||
4406 | /* bt, bts, btr, btc. */ | |
4407 | if (i.tm.base_opcode == 0xfba | |
4408 | && (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7)) | |
4409 | return 1; | |
4410 | ||
4411 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ | |
4412 | if ((base_opcode == 0xc1 | |
4413 | || (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3)) | |
4414 | && i.tm.extension_opcode != 6) | |
4415 | return 1; | |
4416 | ||
4417 | /* cmpxchg8b, cmpxchg16b, xrstors. */ | |
4418 | if (i.tm.base_opcode == 0xfc7 | |
4419 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3)) | |
4420 | return 1; | |
4421 | ||
4422 | /* fxrstor, ldmxcsr, xrstor. */ | |
4423 | if (i.tm.base_opcode == 0xfae | |
4424 | && (i.tm.extension_opcode == 1 | |
4425 | || i.tm.extension_opcode == 2 | |
4426 | || i.tm.extension_opcode == 5)) | |
4427 | return 1; | |
4428 | ||
4429 | /* lgdt, lidt, lmsw. */ | |
4430 | if (i.tm.base_opcode == 0xf01 | |
4431 | && (i.tm.extension_opcode == 2 | |
4432 | || i.tm.extension_opcode == 3 | |
4433 | || i.tm.extension_opcode == 6)) | |
4434 | return 1; | |
4435 | ||
4436 | /* vmptrld */ | |
4437 | if (i.tm.base_opcode == 0xfc7 | |
4438 | && i.tm.extension_opcode == 6) | |
4439 | return 1; | |
4440 | ||
4441 | /* Check for x87 instructions. */ | |
4442 | if (i.tm.base_opcode >= 0xd8 && i.tm.base_opcode <= 0xdf) | |
4443 | { | |
4444 | /* Skip fst, fstp, fstenv, fstcw. */ | |
4445 | if (i.tm.base_opcode == 0xd9 | |
4446 | && (i.tm.extension_opcode == 2 | |
4447 | || i.tm.extension_opcode == 3 | |
4448 | || i.tm.extension_opcode == 6 | |
4449 | || i.tm.extension_opcode == 7)) | |
4450 | return 0; | |
4451 | ||
4452 | /* Skip fisttp, fist, fistp, fstp. */ | |
4453 | if (i.tm.base_opcode == 0xdb | |
4454 | && (i.tm.extension_opcode == 1 | |
4455 | || i.tm.extension_opcode == 2 | |
4456 | || i.tm.extension_opcode == 3 | |
4457 | || i.tm.extension_opcode == 7)) | |
4458 | return 0; | |
4459 | ||
4460 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ | |
4461 | if (i.tm.base_opcode == 0xdd | |
4462 | && (i.tm.extension_opcode == 1 | |
4463 | || i.tm.extension_opcode == 2 | |
4464 | || i.tm.extension_opcode == 3 | |
4465 | || i.tm.extension_opcode == 6 | |
4466 | || i.tm.extension_opcode == 7)) | |
4467 | return 0; | |
4468 | ||
4469 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ | |
4470 | if (i.tm.base_opcode == 0xdf | |
4471 | && (i.tm.extension_opcode == 1 | |
4472 | || i.tm.extension_opcode == 2 | |
4473 | || i.tm.extension_opcode == 3 | |
4474 | || i.tm.extension_opcode == 6 | |
4475 | || i.tm.extension_opcode == 7)) | |
4476 | return 0; | |
4477 | ||
4478 | return 1; | |
4479 | } | |
4480 | } | |
4481 | ||
4482 | dest = i.operands - 1; | |
4483 | ||
4484 | /* Check fake imm8 operand and 3 source operands. */ | |
4485 | if ((i.tm.opcode_modifier.immext | |
4486 | || i.tm.opcode_modifier.vexsources == VEX3SOURCES) | |
4487 | && i.types[dest].bitfield.imm8) | |
4488 | dest--; | |
4489 | ||
4490 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */ | |
4491 | if (!any_vex_p | |
4492 | && (base_opcode == 0x1 | |
4493 | || base_opcode == 0x9 | |
4494 | || base_opcode == 0x11 | |
4495 | || base_opcode == 0x19 | |
4496 | || base_opcode == 0x21 | |
4497 | || base_opcode == 0x29 | |
4498 | || base_opcode == 0x31 | |
4499 | || base_opcode == 0x39 | |
4500 | || (i.tm.base_opcode >= 0x84 && i.tm.base_opcode <= 0x87) | |
4501 | || base_opcode == 0xfc1)) | |
4502 | return 1; | |
4503 | ||
4504 | /* Check for load instruction. */ | |
4505 | return (i.types[dest].bitfield.class != ClassNone | |
4506 | || i.types[dest].bitfield.instance == Accum); | |
4507 | } | |
4508 | ||
4509 | /* Output lfence, 0xfaee8, after instruction. */ | |
4510 | ||
4511 | static void | |
4512 | insert_lfence_after (void) | |
4513 | { | |
4514 | if (lfence_after_load && load_insn_p ()) | |
4515 | { | |
a09f656b | 4516 | /* There are also two REP string instructions that require |
4517 | special treatment. Specifically, the compare string (CMPS) | |
4518 | and scan string (SCAS) instructions set EFLAGS in a manner | |
4519 | that depends on the data being compared/scanned. When used | |
4520 | with a REP prefix, the number of iterations may therefore | |
4521 | vary depending on this data. If the data is a program secret | |
4522 | chosen by the adversary using an LVI method, | |
4523 | then this data-dependent behavior may leak some aspect | |
4524 | of the secret. */ | |
4525 | if (((i.tm.base_opcode | 0x1) == 0xa7 | |
4526 | || (i.tm.base_opcode | 0x1) == 0xaf) | |
4527 | && i.prefix[REP_PREFIX]) | |
4528 | { | |
4529 | as_warn (_("`%s` changes flags which would affect control flow behavior"), | |
4530 | i.tm.name); | |
4531 | } | |
ae531041 L |
4532 | char *p = frag_more (3); |
4533 | *p++ = 0xf; | |
4534 | *p++ = 0xae; | |
4535 | *p = 0xe8; | |
4536 | } | |
4537 | } | |
4538 | ||
4539 | /* Output lfence, 0xfaee8, before instruction. */ | |
4540 | ||
4541 | static void | |
4542 | insert_lfence_before (void) | |
4543 | { | |
4544 | char *p; | |
4545 | ||
4546 | if (is_any_vex_encoding (&i.tm)) | |
4547 | return; | |
4548 | ||
4549 | if (i.tm.base_opcode == 0xff | |
4550 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) | |
4551 | { | |
4552 | /* Insert lfence before indirect branch if needed. */ | |
4553 | ||
4554 | if (lfence_before_indirect_branch == lfence_branch_none) | |
4555 | return; | |
4556 | ||
4557 | if (i.operands != 1) | |
4558 | abort (); | |
4559 | ||
4560 | if (i.reg_operands == 1) | |
4561 | { | |
4562 | /* Indirect branch via register. Don't insert lfence with | |
4563 | -mlfence-after-load=yes. */ | |
4564 | if (lfence_after_load | |
4565 | || lfence_before_indirect_branch == lfence_branch_memory) | |
4566 | return; | |
4567 | } | |
4568 | else if (i.mem_operands == 1 | |
4569 | && lfence_before_indirect_branch != lfence_branch_register) | |
4570 | { | |
4571 | as_warn (_("indirect `%s` with memory operand should be avoided"), | |
4572 | i.tm.name); | |
4573 | return; | |
4574 | } | |
4575 | else | |
4576 | return; | |
4577 | ||
4578 | if (last_insn.kind != last_insn_other | |
4579 | && last_insn.seg == now_seg) | |
4580 | { | |
4581 | as_warn_where (last_insn.file, last_insn.line, | |
4582 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), | |
4583 | last_insn.name, i.tm.name); | |
4584 | return; | |
4585 | } | |
4586 | ||
4587 | p = frag_more (3); | |
4588 | *p++ = 0xf; | |
4589 | *p++ = 0xae; | |
4590 | *p = 0xe8; | |
4591 | return; | |
4592 | } | |
4593 | ||
503648e4 | 4594 | /* Output or/not/shl and lfence before near ret. */ |
ae531041 L |
4595 | if (lfence_before_ret != lfence_before_ret_none |
4596 | && (i.tm.base_opcode == 0xc2 | |
503648e4 | 4597 | || i.tm.base_opcode == 0xc3)) |
ae531041 L |
4598 | { |
4599 | if (last_insn.kind != last_insn_other | |
4600 | && last_insn.seg == now_seg) | |
4601 | { | |
4602 | as_warn_where (last_insn.file, last_insn.line, | |
4603 | _("`%s` skips -mlfence-before-ret on `%s`"), | |
4604 | last_insn.name, i.tm.name); | |
4605 | return; | |
4606 | } | |
a09f656b | 4607 | |
a09f656b | 4608 | /* Near ret ingore operand size override under CPU64. */ |
503648e4 | 4609 | char prefix = flag_code == CODE_64BIT |
4610 | ? 0x48 | |
4611 | : i.prefix[DATA_PREFIX] ? 0x66 : 0x0; | |
a09f656b | 4612 | |
4613 | if (lfence_before_ret == lfence_before_ret_not) | |
4614 | { | |
4615 | /* not: 0xf71424, may add prefix | |
4616 | for operand size override or 64-bit code. */ | |
4617 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); | |
4618 | if (prefix) | |
4619 | *p++ = prefix; | |
ae531041 L |
4620 | *p++ = 0xf7; |
4621 | *p++ = 0x14; | |
4622 | *p++ = 0x24; | |
a09f656b | 4623 | if (prefix) |
4624 | *p++ = prefix; | |
ae531041 L |
4625 | *p++ = 0xf7; |
4626 | *p++ = 0x14; | |
4627 | *p++ = 0x24; | |
4628 | } | |
a09f656b | 4629 | else |
4630 | { | |
4631 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); | |
4632 | if (prefix) | |
4633 | *p++ = prefix; | |
4634 | if (lfence_before_ret == lfence_before_ret_or) | |
4635 | { | |
4636 | /* or: 0x830c2400, may add prefix | |
4637 | for operand size override or 64-bit code. */ | |
4638 | *p++ = 0x83; | |
4639 | *p++ = 0x0c; | |
4640 | } | |
4641 | else | |
4642 | { | |
4643 | /* shl: 0xc1242400, may add prefix | |
4644 | for operand size override or 64-bit code. */ | |
4645 | *p++ = 0xc1; | |
4646 | *p++ = 0x24; | |
4647 | } | |
4648 | ||
4649 | *p++ = 0x24; | |
4650 | *p++ = 0x0; | |
4651 | } | |
4652 | ||
ae531041 L |
4653 | *p++ = 0xf; |
4654 | *p++ = 0xae; | |
4655 | *p = 0xe8; | |
4656 | } | |
4657 | } | |
4658 | ||
252b5132 RH |
4659 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4660 | machine dependent instruction. This function is supposed to emit | |
4661 | the frags/bytes it assembles to. */ | |
4662 | ||
4663 | void | |
65da13b5 | 4664 | md_assemble (char *line) |
252b5132 | 4665 | { |
40fb9820 | 4666 | unsigned int j; |
83b16ac6 | 4667 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4668 | const insn_template *t; |
252b5132 | 4669 | |
47926f60 | 4670 | /* Initialize globals. */ |
252b5132 RH |
4671 | memset (&i, '\0', sizeof (i)); |
4672 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4673 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4674 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4675 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4676 | save_stack_p = save_stack; |
252b5132 RH |
4677 | |
4678 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4679 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4680 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4681 | |
29b0f896 AM |
4682 | line = parse_insn (line, mnemonic); |
4683 | if (line == NULL) | |
4684 | return; | |
83b16ac6 | 4685 | mnem_suffix = i.suffix; |
252b5132 | 4686 | |
29b0f896 | 4687 | line = parse_operands (line, mnemonic); |
ee86248c | 4688 | this_operand = -1; |
8325cc63 JB |
4689 | xfree (i.memop1_string); |
4690 | i.memop1_string = NULL; | |
29b0f896 AM |
4691 | if (line == NULL) |
4692 | return; | |
252b5132 | 4693 | |
29b0f896 AM |
4694 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4695 | operands at hand. */ | |
4696 | ||
b630c145 JB |
4697 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
4698 | "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse | |
4699 | intersegment "jmp" and "call" instructions with 2 immediate operands so | |
4700 | that the immediate segment precedes the offset, as it does when in AT&T | |
4701 | mode. */ | |
4d456e3d L |
4702 | if (intel_syntax |
4703 | && i.operands > 1 | |
29b0f896 | 4704 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4705 | && (strcmp (mnemonic, "invlpga") != 0) |
eedb0f2c JB |
4706 | && (strncmp (mnemonic, "monitor", 7) != 0) |
4707 | && (strncmp (mnemonic, "mwait", 5) != 0) | |
b630c145 JB |
4708 | && (strcmp (mnemonic, "tpause") != 0) |
4709 | && (strcmp (mnemonic, "umwait") != 0) | |
40fb9820 L |
4710 | && !(operand_type_check (i.types[0], imm) |
4711 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4712 | swap_operands (); |
4713 | ||
ec56d5c0 JB |
4714 | /* The order of the immediates should be reversed |
4715 | for 2 immediates extrq and insertq instructions */ | |
4716 | if (i.imm_operands == 2 | |
4717 | && (strcmp (mnemonic, "extrq") == 0 | |
4718 | || strcmp (mnemonic, "insertq") == 0)) | |
4719 | swap_2_operands (0, 1); | |
4720 | ||
29b0f896 AM |
4721 | if (i.imm_operands) |
4722 | optimize_imm (); | |
4723 | ||
b300c311 L |
4724 | /* Don't optimize displacement for movabs since it only takes 64bit |
4725 | displacement. */ | |
4726 | if (i.disp_operands | |
a501d77e | 4727 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4728 | && (flag_code != CODE_64BIT |
4729 | || strcmp (mnemonic, "movabs") != 0)) | |
4730 | optimize_disp (); | |
29b0f896 AM |
4731 | |
4732 | /* Next, we find a template that matches the given insn, | |
4733 | making sure the overlap of the given operands types is consistent | |
4734 | with the template operand types. */ | |
252b5132 | 4735 | |
83b16ac6 | 4736 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4737 | return; |
252b5132 | 4738 | |
7bab8ab5 | 4739 | if (sse_check != check_none |
81f8a913 | 4740 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4741 | && !i.tm.cpu_flags.bitfield.cpuavx |
569d50f1 | 4742 | && !i.tm.cpu_flags.bitfield.cpuavx512f |
daf50ae7 L |
4743 | && (i.tm.cpu_flags.bitfield.cpusse |
4744 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4745 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4746 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4747 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e | 4748 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
569d50f1 | 4749 | || i.tm.cpu_flags.bitfield.cpusse4a |
6e3e5c9e JB |
4750 | || i.tm.cpu_flags.bitfield.cpupclmul |
4751 | || i.tm.cpu_flags.bitfield.cpuaes | |
569d50f1 | 4752 | || i.tm.cpu_flags.bitfield.cpusha |
6e3e5c9e | 4753 | || i.tm.cpu_flags.bitfield.cpugfni)) |
daf50ae7 | 4754 | { |
7bab8ab5 | 4755 | (sse_check == check_warning |
daf50ae7 L |
4756 | ? as_warn |
4757 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4758 | } | |
4759 | ||
40fb9820 | 4760 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4761 | if (!add_prefix (FWAIT_OPCODE)) |
4762 | return; | |
252b5132 | 4763 | |
d5de92cf L |
4764 | /* Check if REP prefix is OK. */ |
4765 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4766 | { | |
4767 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4768 | i.tm.name, i.rep_prefix); | |
4769 | return; | |
4770 | } | |
4771 | ||
c1ba0266 L |
4772 | /* Check for lock without a lockable instruction. Destination operand |
4773 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4774 | if (i.prefix[LOCK_PREFIX] |
4775 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4776 | || i.mem_operands == 0 |
4777 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4778 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4779 | { |
4780 | as_bad (_("expecting lockable instruction after `lock'")); | |
4781 | return; | |
4782 | } | |
4783 | ||
7a8655d2 JB |
4784 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4785 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4786 | { | |
4787 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4788 | return; | |
4789 | } | |
4790 | ||
42164a71 | 4791 | /* Check if HLE prefix is OK. */ |
165de32a | 4792 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4793 | return; |
4794 | ||
7e8b059b L |
4795 | /* Check BND prefix. */ |
4796 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4797 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4798 | ||
04ef582a | 4799 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4800 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4801 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4802 | |
327e8c42 JB |
4803 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4804 | { | |
4805 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4806 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4807 | else if (flag_code != CODE_16BIT | |
4808 | ? i.prefix[ADDR_PREFIX] | |
4809 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4810 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4811 | } | |
7e8b059b L |
4812 | |
4813 | /* Insert BND prefix. */ | |
76d3a78a JB |
4814 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4815 | { | |
4816 | if (!i.prefix[BND_PREFIX]) | |
4817 | add_prefix (BND_PREFIX_OPCODE); | |
4818 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4819 | { | |
4820 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4821 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4822 | } | |
4823 | } | |
7e8b059b | 4824 | |
29b0f896 | 4825 | /* Check string instruction segment overrides. */ |
51c8edf6 | 4826 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 4827 | { |
51c8edf6 | 4828 | gas_assert (i.mem_operands); |
29b0f896 | 4829 | if (!check_string ()) |
5dd0794d | 4830 | return; |
fc0763e6 | 4831 | i.disp_operands = 0; |
29b0f896 | 4832 | } |
5dd0794d | 4833 | |
b6f8c7c4 L |
4834 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4835 | optimize_encoding (); | |
4836 | ||
29b0f896 AM |
4837 | if (!process_suffix ()) |
4838 | return; | |
e413e4e9 | 4839 | |
bc0844ae L |
4840 | /* Update operand types. */ |
4841 | for (j = 0; j < i.operands; j++) | |
4842 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4843 | ||
29b0f896 AM |
4844 | /* Make still unresolved immediate matches conform to size of immediate |
4845 | given in i.suffix. */ | |
4846 | if (!finalize_imm ()) | |
4847 | return; | |
252b5132 | 4848 | |
40fb9820 | 4849 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4850 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4851 | |
9afe6eb8 L |
4852 | /* We only need to check those implicit registers for instructions |
4853 | with 3 operands or less. */ | |
4854 | if (i.operands <= 3) | |
4855 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
4856 | if (i.types[j].bitfield.instance != InstanceNone |
4857 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 4858 | i.reg_operands--; |
40fb9820 | 4859 | |
c0f3af97 L |
4860 | /* ImmExt should be processed after SSE2AVX. */ |
4861 | if (!i.tm.opcode_modifier.sse2avx | |
4862 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4863 | process_immext (); |
252b5132 | 4864 | |
29b0f896 AM |
4865 | /* For insns with operands there are more diddles to do to the opcode. */ |
4866 | if (i.operands) | |
4867 | { | |
4868 | if (!process_operands ()) | |
4869 | return; | |
4870 | } | |
40fb9820 | 4871 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4872 | { |
4873 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4874 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4875 | } | |
252b5132 | 4876 | |
7a8655d2 | 4877 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 4878 | { |
c1dc7af5 | 4879 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 4880 | { |
c1dc7af5 | 4881 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
4882 | i.tm.name); |
4883 | return; | |
4884 | } | |
c0f3af97 | 4885 | |
9e5e5283 L |
4886 | if (i.tm.opcode_modifier.vex) |
4887 | build_vex_prefix (t); | |
4888 | else | |
4889 | build_evex_prefix (); | |
4890 | } | |
43234a1e | 4891 | |
5dd85c99 SP |
4892 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4893 | instructions may define INT_OPCODE as well, so avoid this corner | |
4894 | case for those instructions that use MODRM. */ | |
4895 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4896 | && !i.tm.opcode_modifier.modrm |
4897 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4898 | { |
4899 | i.tm.base_opcode = INT3_OPCODE; | |
4900 | i.imm_operands = 0; | |
4901 | } | |
252b5132 | 4902 | |
0cfa3eb3 JB |
4903 | if ((i.tm.opcode_modifier.jump == JUMP |
4904 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
4905 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
4906 | && i.op[0].disps->X_op == O_constant) |
4907 | { | |
4908 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4909 | the absolute address given by the constant. Since ix86 jumps and | |
4910 | calls are pc relative, we need to generate a reloc. */ | |
4911 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4912 | i.op[0].disps->X_op = O_symbol; | |
4913 | } | |
252b5132 | 4914 | |
29b0f896 AM |
4915 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4916 | instruction already has a prefix, we need to convert old | |
4917 | registers to new ones. */ | |
773f551c | 4918 | |
bab6aec1 | 4919 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 4920 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 4921 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 4922 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
4923 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
4924 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4925 | && i.rex != 0)) |
4926 | { | |
4927 | int x; | |
726c5dcd | 4928 | |
29b0f896 AM |
4929 | i.rex |= REX_OPCODE; |
4930 | for (x = 0; x < 2; x++) | |
4931 | { | |
4932 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 4933 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 4934 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4935 | { |
3f93af61 | 4936 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
4937 | /* In case it is "hi" register, give up. */ |
4938 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4939 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4940 | "instruction requiring REX prefix."), |
a540244d | 4941 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4942 | |
29b0f896 AM |
4943 | /* Otherwise it is equivalent to the extended register. |
4944 | Since the encoding doesn't change this is merely | |
4945 | cosmetic cleanup for debug output. */ | |
4946 | ||
4947 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4948 | } |
29b0f896 AM |
4949 | } |
4950 | } | |
773f551c | 4951 | |
6b6b6807 L |
4952 | if (i.rex == 0 && i.rex_encoding) |
4953 | { | |
4954 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 4955 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
4956 | the REX_OPCODE byte. */ |
4957 | int x; | |
4958 | for (x = 0; x < 2; x++) | |
bab6aec1 | 4959 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
4960 | && i.types[x].bitfield.byte |
4961 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4962 | && i.op[x].regs->reg_num > 3) | |
4963 | { | |
3f93af61 | 4964 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
6b6b6807 L |
4965 | i.rex_encoding = FALSE; |
4966 | break; | |
4967 | } | |
4968 | ||
4969 | if (i.rex_encoding) | |
4970 | i.rex = REX_OPCODE; | |
4971 | } | |
4972 | ||
7ab9ffdd | 4973 | if (i.rex != 0) |
29b0f896 AM |
4974 | add_prefix (REX_OPCODE | i.rex); |
4975 | ||
ae531041 L |
4976 | insert_lfence_before (); |
4977 | ||
29b0f896 AM |
4978 | /* We are ready to output the insn. */ |
4979 | output_insn (); | |
e379e5f3 | 4980 | |
ae531041 L |
4981 | insert_lfence_after (); |
4982 | ||
e379e5f3 L |
4983 | last_insn.seg = now_seg; |
4984 | ||
4985 | if (i.tm.opcode_modifier.isprefix) | |
4986 | { | |
4987 | last_insn.kind = last_insn_prefix; | |
4988 | last_insn.name = i.tm.name; | |
4989 | last_insn.file = as_where (&last_insn.line); | |
4990 | } | |
4991 | else | |
4992 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
4993 | } |
4994 | ||
4995 | static char * | |
e3bb37b5 | 4996 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4997 | { |
4998 | char *l = line; | |
4999 | char *token_start = l; | |
5000 | char *mnem_p; | |
5c6af06e | 5001 | int supported; |
d3ce72d0 | 5002 | const insn_template *t; |
b6169b20 | 5003 | char *dot_p = NULL; |
29b0f896 | 5004 | |
29b0f896 AM |
5005 | while (1) |
5006 | { | |
5007 | mnem_p = mnemonic; | |
5008 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
5009 | { | |
b6169b20 L |
5010 | if (*mnem_p == '.') |
5011 | dot_p = mnem_p; | |
29b0f896 AM |
5012 | mnem_p++; |
5013 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 5014 | { |
29b0f896 AM |
5015 | as_bad (_("no such instruction: `%s'"), token_start); |
5016 | return NULL; | |
5017 | } | |
5018 | l++; | |
5019 | } | |
5020 | if (!is_space_char (*l) | |
5021 | && *l != END_OF_INSN | |
e44823cf JB |
5022 | && (intel_syntax |
5023 | || (*l != PREFIX_SEPARATOR | |
5024 | && *l != ','))) | |
29b0f896 AM |
5025 | { |
5026 | as_bad (_("invalid character %s in mnemonic"), | |
5027 | output_invalid (*l)); | |
5028 | return NULL; | |
5029 | } | |
5030 | if (token_start == l) | |
5031 | { | |
e44823cf | 5032 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
5033 | as_bad (_("expecting prefix; got nothing")); |
5034 | else | |
5035 | as_bad (_("expecting mnemonic; got nothing")); | |
5036 | return NULL; | |
5037 | } | |
45288df1 | 5038 | |
29b0f896 | 5039 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 5040 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 5041 | |
29b0f896 AM |
5042 | if (*l != END_OF_INSN |
5043 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
5044 | && current_templates | |
40fb9820 | 5045 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 5046 | { |
c6fb90c8 | 5047 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
5048 | { |
5049 | as_bad ((flag_code != CODE_64BIT | |
5050 | ? _("`%s' is only supported in 64-bit mode") | |
5051 | : _("`%s' is not supported in 64-bit mode")), | |
5052 | current_templates->start->name); | |
5053 | return NULL; | |
5054 | } | |
29b0f896 AM |
5055 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
5056 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
5057 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
5058 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 5059 | && flag_code != CODE_64BIT |
673fe0f0 | 5060 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
5061 | ^ (flag_code == CODE_16BIT))) |
5062 | { | |
5063 | as_bad (_("redundant %s prefix"), | |
5064 | current_templates->start->name); | |
5065 | return NULL; | |
45288df1 | 5066 | } |
86fa6981 | 5067 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 5068 | { |
86fa6981 L |
5069 | /* Handle pseudo prefixes. */ |
5070 | switch (current_templates->start->base_opcode) | |
5071 | { | |
5072 | case 0x0: | |
5073 | /* {disp8} */ | |
5074 | i.disp_encoding = disp_encoding_8bit; | |
5075 | break; | |
5076 | case 0x1: | |
5077 | /* {disp32} */ | |
5078 | i.disp_encoding = disp_encoding_32bit; | |
5079 | break; | |
5080 | case 0x2: | |
5081 | /* {load} */ | |
5082 | i.dir_encoding = dir_encoding_load; | |
5083 | break; | |
5084 | case 0x3: | |
5085 | /* {store} */ | |
5086 | i.dir_encoding = dir_encoding_store; | |
5087 | break; | |
5088 | case 0x4: | |
42e04b36 L |
5089 | /* {vex} */ |
5090 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 L |
5091 | break; |
5092 | case 0x5: | |
5093 | /* {vex3} */ | |
5094 | i.vec_encoding = vex_encoding_vex3; | |
5095 | break; | |
5096 | case 0x6: | |
5097 | /* {evex} */ | |
5098 | i.vec_encoding = vex_encoding_evex; | |
5099 | break; | |
6b6b6807 L |
5100 | case 0x7: |
5101 | /* {rex} */ | |
5102 | i.rex_encoding = TRUE; | |
5103 | break; | |
b6f8c7c4 L |
5104 | case 0x8: |
5105 | /* {nooptimize} */ | |
5106 | i.no_optimize = TRUE; | |
5107 | break; | |
86fa6981 L |
5108 | default: |
5109 | abort (); | |
5110 | } | |
5111 | } | |
5112 | else | |
5113 | { | |
5114 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 5115 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 5116 | { |
4e9ac44a L |
5117 | case PREFIX_EXIST: |
5118 | return NULL; | |
5119 | case PREFIX_DS: | |
d777820b | 5120 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
5121 | i.notrack_prefix = current_templates->start->name; |
5122 | break; | |
5123 | case PREFIX_REP: | |
5124 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
5125 | i.hle_prefix = current_templates->start->name; | |
5126 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
5127 | i.bnd_prefix = current_templates->start->name; | |
5128 | else | |
5129 | i.rep_prefix = current_templates->start->name; | |
5130 | break; | |
5131 | default: | |
5132 | break; | |
86fa6981 | 5133 | } |
29b0f896 AM |
5134 | } |
5135 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
5136 | token_start = ++l; | |
5137 | } | |
5138 | else | |
5139 | break; | |
5140 | } | |
45288df1 | 5141 | |
30a55f88 | 5142 | if (!current_templates) |
b6169b20 | 5143 | { |
07d5e953 JB |
5144 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
5145 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 5146 | encoding. */ |
30a55f88 | 5147 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 5148 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 5149 | else if (mnem_p - 3 == dot_p |
a501d77e L |
5150 | && dot_p[1] == 'd' |
5151 | && dot_p[2] == '8') | |
5152 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 5153 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
5154 | && dot_p[1] == 'd' |
5155 | && dot_p[2] == '3' | |
5156 | && dot_p[3] == '2') | |
a501d77e | 5157 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
5158 | else |
5159 | goto check_suffix; | |
5160 | mnem_p = dot_p; | |
5161 | *dot_p = '\0'; | |
d3ce72d0 | 5162 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
5163 | } |
5164 | ||
29b0f896 AM |
5165 | if (!current_templates) |
5166 | { | |
dc1e8a47 | 5167 | check_suffix: |
1c529385 | 5168 | if (mnem_p > mnemonic) |
29b0f896 | 5169 | { |
1c529385 LH |
5170 | /* See if we can get a match by trimming off a suffix. */ |
5171 | switch (mnem_p[-1]) | |
29b0f896 | 5172 | { |
1c529385 LH |
5173 | case WORD_MNEM_SUFFIX: |
5174 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
5175 | i.suffix = SHORT_MNEM_SUFFIX; |
5176 | else | |
1c529385 LH |
5177 | /* Fall through. */ |
5178 | case BYTE_MNEM_SUFFIX: | |
5179 | case QWORD_MNEM_SUFFIX: | |
5180 | i.suffix = mnem_p[-1]; | |
29b0f896 | 5181 | mnem_p[-1] = '\0'; |
d3ce72d0 | 5182 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
5183 | mnemonic); |
5184 | break; | |
5185 | case SHORT_MNEM_SUFFIX: | |
5186 | case LONG_MNEM_SUFFIX: | |
5187 | if (!intel_syntax) | |
5188 | { | |
5189 | i.suffix = mnem_p[-1]; | |
5190 | mnem_p[-1] = '\0'; | |
5191 | current_templates = (const templates *) hash_find (op_hash, | |
5192 | mnemonic); | |
5193 | } | |
5194 | break; | |
5195 | ||
5196 | /* Intel Syntax. */ | |
5197 | case 'd': | |
5198 | if (intel_syntax) | |
5199 | { | |
5200 | if (intel_float_operand (mnemonic) == 1) | |
5201 | i.suffix = SHORT_MNEM_SUFFIX; | |
5202 | else | |
5203 | i.suffix = LONG_MNEM_SUFFIX; | |
5204 | mnem_p[-1] = '\0'; | |
5205 | current_templates = (const templates *) hash_find (op_hash, | |
5206 | mnemonic); | |
5207 | } | |
5208 | break; | |
29b0f896 | 5209 | } |
29b0f896 | 5210 | } |
1c529385 | 5211 | |
29b0f896 AM |
5212 | if (!current_templates) |
5213 | { | |
5214 | as_bad (_("no such instruction: `%s'"), token_start); | |
5215 | return NULL; | |
5216 | } | |
5217 | } | |
252b5132 | 5218 | |
0cfa3eb3 JB |
5219 | if (current_templates->start->opcode_modifier.jump == JUMP |
5220 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
5221 | { |
5222 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
5223 | predict taken and predict not taken respectively. | |
5224 | I'm not sure that branch hints actually do anything on loop | |
5225 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
5226 | may work in the future and it doesn't hurt to accept them | |
5227 | now. */ | |
5228 | if (l[0] == ',' && l[1] == 'p') | |
5229 | { | |
5230 | if (l[2] == 't') | |
5231 | { | |
5232 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
5233 | return NULL; | |
5234 | l += 3; | |
5235 | } | |
5236 | else if (l[2] == 'n') | |
5237 | { | |
5238 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
5239 | return NULL; | |
5240 | l += 3; | |
5241 | } | |
5242 | } | |
5243 | } | |
5244 | /* Any other comma loses. */ | |
5245 | if (*l == ',') | |
5246 | { | |
5247 | as_bad (_("invalid character %s in mnemonic"), | |
5248 | output_invalid (*l)); | |
5249 | return NULL; | |
5250 | } | |
252b5132 | 5251 | |
29b0f896 | 5252 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
5253 | supported = 0; |
5254 | for (t = current_templates->start; t < current_templates->end; ++t) | |
5255 | { | |
c0f3af97 L |
5256 | supported |= cpu_flags_match (t); |
5257 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
5258 | { |
5259 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
5260 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 5261 | |
548d0ee6 JB |
5262 | return l; |
5263 | } | |
29b0f896 | 5264 | } |
3629bb00 | 5265 | |
548d0ee6 JB |
5266 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5267 | as_bad (flag_code == CODE_64BIT | |
5268 | ? _("`%s' is not supported in 64-bit mode") | |
5269 | : _("`%s' is only supported in 64-bit mode"), | |
5270 | current_templates->start->name); | |
5271 | else | |
5272 | as_bad (_("`%s' is not supported on `%s%s'"), | |
5273 | current_templates->start->name, | |
5274 | cpu_arch_name ? cpu_arch_name : default_arch, | |
5275 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 5276 | |
548d0ee6 | 5277 | return NULL; |
29b0f896 | 5278 | } |
252b5132 | 5279 | |
29b0f896 | 5280 | static char * |
e3bb37b5 | 5281 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
5282 | { |
5283 | char *token_start; | |
3138f287 | 5284 | |
29b0f896 AM |
5285 | /* 1 if operand is pending after ','. */ |
5286 | unsigned int expecting_operand = 0; | |
252b5132 | 5287 | |
29b0f896 AM |
5288 | /* Non-zero if operand parens not balanced. */ |
5289 | unsigned int paren_not_balanced; | |
5290 | ||
5291 | while (*l != END_OF_INSN) | |
5292 | { | |
5293 | /* Skip optional white space before operand. */ | |
5294 | if (is_space_char (*l)) | |
5295 | ++l; | |
d02603dc | 5296 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
5297 | { |
5298 | as_bad (_("invalid character %s before operand %d"), | |
5299 | output_invalid (*l), | |
5300 | i.operands + 1); | |
5301 | return NULL; | |
5302 | } | |
d02603dc | 5303 | token_start = l; /* After white space. */ |
29b0f896 AM |
5304 | paren_not_balanced = 0; |
5305 | while (paren_not_balanced || *l != ',') | |
5306 | { | |
5307 | if (*l == END_OF_INSN) | |
5308 | { | |
5309 | if (paren_not_balanced) | |
5310 | { | |
5311 | if (!intel_syntax) | |
5312 | as_bad (_("unbalanced parenthesis in operand %d."), | |
5313 | i.operands + 1); | |
5314 | else | |
5315 | as_bad (_("unbalanced brackets in operand %d."), | |
5316 | i.operands + 1); | |
5317 | return NULL; | |
5318 | } | |
5319 | else | |
5320 | break; /* we are done */ | |
5321 | } | |
d02603dc | 5322 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
5323 | { |
5324 | as_bad (_("invalid character %s in operand %d"), | |
5325 | output_invalid (*l), | |
5326 | i.operands + 1); | |
5327 | return NULL; | |
5328 | } | |
5329 | if (!intel_syntax) | |
5330 | { | |
5331 | if (*l == '(') | |
5332 | ++paren_not_balanced; | |
5333 | if (*l == ')') | |
5334 | --paren_not_balanced; | |
5335 | } | |
5336 | else | |
5337 | { | |
5338 | if (*l == '[') | |
5339 | ++paren_not_balanced; | |
5340 | if (*l == ']') | |
5341 | --paren_not_balanced; | |
5342 | } | |
5343 | l++; | |
5344 | } | |
5345 | if (l != token_start) | |
5346 | { /* Yes, we've read in another operand. */ | |
5347 | unsigned int operand_ok; | |
5348 | this_operand = i.operands++; | |
5349 | if (i.operands > MAX_OPERANDS) | |
5350 | { | |
5351 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
5352 | MAX_OPERANDS); | |
5353 | return NULL; | |
5354 | } | |
9d46ce34 | 5355 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
5356 | /* Now parse operand adding info to 'i' as we go along. */ |
5357 | END_STRING_AND_SAVE (l); | |
5358 | ||
1286ab78 L |
5359 | if (i.mem_operands > 1) |
5360 | { | |
5361 | as_bad (_("too many memory references for `%s'"), | |
5362 | mnemonic); | |
5363 | return 0; | |
5364 | } | |
5365 | ||
29b0f896 AM |
5366 | if (intel_syntax) |
5367 | operand_ok = | |
5368 | i386_intel_operand (token_start, | |
5369 | intel_float_operand (mnemonic)); | |
5370 | else | |
a7619375 | 5371 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5372 | |
5373 | RESTORE_END_STRING (l); | |
5374 | if (!operand_ok) | |
5375 | return NULL; | |
5376 | } | |
5377 | else | |
5378 | { | |
5379 | if (expecting_operand) | |
5380 | { | |
5381 | expecting_operand_after_comma: | |
5382 | as_bad (_("expecting operand after ','; got nothing")); | |
5383 | return NULL; | |
5384 | } | |
5385 | if (*l == ',') | |
5386 | { | |
5387 | as_bad (_("expecting operand before ','; got nothing")); | |
5388 | return NULL; | |
5389 | } | |
5390 | } | |
7f3f1ea2 | 5391 | |
29b0f896 AM |
5392 | /* Now *l must be either ',' or END_OF_INSN. */ |
5393 | if (*l == ',') | |
5394 | { | |
5395 | if (*++l == END_OF_INSN) | |
5396 | { | |
5397 | /* Just skip it, if it's \n complain. */ | |
5398 | goto expecting_operand_after_comma; | |
5399 | } | |
5400 | expecting_operand = 1; | |
5401 | } | |
5402 | } | |
5403 | return l; | |
5404 | } | |
7f3f1ea2 | 5405 | |
050dfa73 | 5406 | static void |
4d456e3d | 5407 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
5408 | { |
5409 | union i386_op temp_op; | |
40fb9820 | 5410 | i386_operand_type temp_type; |
c48dadc9 | 5411 | unsigned int temp_flags; |
050dfa73 | 5412 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5413 | |
050dfa73 MM |
5414 | temp_type = i.types[xchg2]; |
5415 | i.types[xchg2] = i.types[xchg1]; | |
5416 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5417 | |
5418 | temp_flags = i.flags[xchg2]; | |
5419 | i.flags[xchg2] = i.flags[xchg1]; | |
5420 | i.flags[xchg1] = temp_flags; | |
5421 | ||
050dfa73 MM |
5422 | temp_op = i.op[xchg2]; |
5423 | i.op[xchg2] = i.op[xchg1]; | |
5424 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5425 | |
050dfa73 MM |
5426 | temp_reloc = i.reloc[xchg2]; |
5427 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5428 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
5429 | |
5430 | if (i.mask) | |
5431 | { | |
5432 | if (i.mask->operand == xchg1) | |
5433 | i.mask->operand = xchg2; | |
5434 | else if (i.mask->operand == xchg2) | |
5435 | i.mask->operand = xchg1; | |
5436 | } | |
5437 | if (i.broadcast) | |
5438 | { | |
5439 | if (i.broadcast->operand == xchg1) | |
5440 | i.broadcast->operand = xchg2; | |
5441 | else if (i.broadcast->operand == xchg2) | |
5442 | i.broadcast->operand = xchg1; | |
5443 | } | |
5444 | if (i.rounding) | |
5445 | { | |
5446 | if (i.rounding->operand == xchg1) | |
5447 | i.rounding->operand = xchg2; | |
5448 | else if (i.rounding->operand == xchg2) | |
5449 | i.rounding->operand = xchg1; | |
5450 | } | |
050dfa73 MM |
5451 | } |
5452 | ||
29b0f896 | 5453 | static void |
e3bb37b5 | 5454 | swap_operands (void) |
29b0f896 | 5455 | { |
b7c61d9a | 5456 | switch (i.operands) |
050dfa73 | 5457 | { |
c0f3af97 | 5458 | case 5: |
b7c61d9a | 5459 | case 4: |
4d456e3d | 5460 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5461 | /* Fall through. */ |
b7c61d9a L |
5462 | case 3: |
5463 | case 2: | |
4d456e3d | 5464 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5465 | break; |
5466 | default: | |
5467 | abort (); | |
29b0f896 | 5468 | } |
29b0f896 AM |
5469 | |
5470 | if (i.mem_operands == 2) | |
5471 | { | |
5472 | const seg_entry *temp_seg; | |
5473 | temp_seg = i.seg[0]; | |
5474 | i.seg[0] = i.seg[1]; | |
5475 | i.seg[1] = temp_seg; | |
5476 | } | |
5477 | } | |
252b5132 | 5478 | |
29b0f896 AM |
5479 | /* Try to ensure constant immediates are represented in the smallest |
5480 | opcode possible. */ | |
5481 | static void | |
e3bb37b5 | 5482 | optimize_imm (void) |
29b0f896 AM |
5483 | { |
5484 | char guess_suffix = 0; | |
5485 | int op; | |
252b5132 | 5486 | |
29b0f896 AM |
5487 | if (i.suffix) |
5488 | guess_suffix = i.suffix; | |
5489 | else if (i.reg_operands) | |
5490 | { | |
5491 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5492 | We can't do this properly yet, i.e. excluding special register |
5493 | instances, but the following works for instructions with | |
5494 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5495 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5496 | if (i.types[op].bitfield.class != Reg) |
5497 | continue; | |
5498 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5499 | { |
40fb9820 L |
5500 | guess_suffix = BYTE_MNEM_SUFFIX; |
5501 | break; | |
5502 | } | |
bab6aec1 | 5503 | else if (i.types[op].bitfield.word) |
252b5132 | 5504 | { |
40fb9820 L |
5505 | guess_suffix = WORD_MNEM_SUFFIX; |
5506 | break; | |
5507 | } | |
bab6aec1 | 5508 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5509 | { |
5510 | guess_suffix = LONG_MNEM_SUFFIX; | |
5511 | break; | |
5512 | } | |
bab6aec1 | 5513 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5514 | { |
5515 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5516 | break; |
252b5132 | 5517 | } |
29b0f896 AM |
5518 | } |
5519 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5520 | guess_suffix = WORD_MNEM_SUFFIX; | |
5521 | ||
5522 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5523 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5524 | { |
5525 | switch (i.op[op].imms->X_op) | |
252b5132 | 5526 | { |
29b0f896 AM |
5527 | case O_constant: |
5528 | /* If a suffix is given, this operand may be shortened. */ | |
5529 | switch (guess_suffix) | |
252b5132 | 5530 | { |
29b0f896 | 5531 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5532 | i.types[op].bitfield.imm32 = 1; |
5533 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5534 | break; |
5535 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5536 | i.types[op].bitfield.imm16 = 1; |
5537 | i.types[op].bitfield.imm32 = 1; | |
5538 | i.types[op].bitfield.imm32s = 1; | |
5539 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5540 | break; |
5541 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5542 | i.types[op].bitfield.imm8 = 1; |
5543 | i.types[op].bitfield.imm8s = 1; | |
5544 | i.types[op].bitfield.imm16 = 1; | |
5545 | i.types[op].bitfield.imm32 = 1; | |
5546 | i.types[op].bitfield.imm32s = 1; | |
5547 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5548 | break; |
252b5132 | 5549 | } |
252b5132 | 5550 | |
29b0f896 AM |
5551 | /* If this operand is at most 16 bits, convert it |
5552 | to a signed 16 bit number before trying to see | |
5553 | whether it will fit in an even smaller size. | |
5554 | This allows a 16-bit operand such as $0xffe0 to | |
5555 | be recognised as within Imm8S range. */ | |
40fb9820 | 5556 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5557 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5558 | { |
29b0f896 AM |
5559 | i.op[op].imms->X_add_number = |
5560 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5561 | } | |
a28def75 L |
5562 | #ifdef BFD64 |
5563 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5564 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5565 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5566 | == 0)) | |
5567 | { | |
5568 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5569 | ^ ((offsetT) 1 << 31)) | |
5570 | - ((offsetT) 1 << 31)); | |
5571 | } | |
a28def75 | 5572 | #endif |
40fb9820 | 5573 | i.types[op] |
c6fb90c8 L |
5574 | = operand_type_or (i.types[op], |
5575 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5576 | |
29b0f896 AM |
5577 | /* We must avoid matching of Imm32 templates when 64bit |
5578 | only immediate is available. */ | |
5579 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5580 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5581 | break; |
252b5132 | 5582 | |
29b0f896 AM |
5583 | case O_absent: |
5584 | case O_register: | |
5585 | abort (); | |
5586 | ||
5587 | /* Symbols and expressions. */ | |
5588 | default: | |
9cd96992 JB |
5589 | /* Convert symbolic operand to proper sizes for matching, but don't |
5590 | prevent matching a set of insns that only supports sizes other | |
5591 | than those matching the insn suffix. */ | |
5592 | { | |
40fb9820 | 5593 | i386_operand_type mask, allowed; |
d3ce72d0 | 5594 | const insn_template *t; |
9cd96992 | 5595 | |
0dfbf9d7 L |
5596 | operand_type_set (&mask, 0); |
5597 | operand_type_set (&allowed, 0); | |
40fb9820 | 5598 | |
4eed87de AM |
5599 | for (t = current_templates->start; |
5600 | t < current_templates->end; | |
5601 | ++t) | |
bab6aec1 JB |
5602 | { |
5603 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
5604 | allowed = operand_type_and (allowed, anyimm); | |
5605 | } | |
9cd96992 JB |
5606 | switch (guess_suffix) |
5607 | { | |
5608 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5609 | mask.bitfield.imm64 = 1; |
5610 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5611 | break; |
5612 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5613 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5614 | break; |
5615 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5616 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5617 | break; |
5618 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5619 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5620 | break; |
5621 | default: | |
9cd96992 JB |
5622 | break; |
5623 | } | |
c6fb90c8 | 5624 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5625 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5626 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5627 | } |
29b0f896 | 5628 | break; |
252b5132 | 5629 | } |
29b0f896 AM |
5630 | } |
5631 | } | |
47926f60 | 5632 | |
29b0f896 AM |
5633 | /* Try to use the smallest displacement type too. */ |
5634 | static void | |
e3bb37b5 | 5635 | optimize_disp (void) |
29b0f896 AM |
5636 | { |
5637 | int op; | |
3e73aa7c | 5638 | |
29b0f896 | 5639 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5640 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5641 | { |
b300c311 | 5642 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5643 | { |
91d6fa6a | 5644 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5645 | |
40fb9820 | 5646 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5647 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5648 | { |
5649 | /* If this operand is at most 16 bits, convert | |
5650 | to a signed 16 bit number and don't use 64bit | |
5651 | displacement. */ | |
91d6fa6a | 5652 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5653 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5654 | } |
a28def75 L |
5655 | #ifdef BFD64 |
5656 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5657 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5658 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5659 | { |
5660 | /* If this operand is at most 32 bits, convert | |
5661 | to a signed 32 bit number and don't use 64bit | |
5662 | displacement. */ | |
91d6fa6a NC |
5663 | op_disp &= (((offsetT) 2 << 31) - 1); |
5664 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5665 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5666 | } |
a28def75 | 5667 | #endif |
91d6fa6a | 5668 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5669 | { |
40fb9820 L |
5670 | i.types[op].bitfield.disp8 = 0; |
5671 | i.types[op].bitfield.disp16 = 0; | |
5672 | i.types[op].bitfield.disp32 = 0; | |
5673 | i.types[op].bitfield.disp32s = 0; | |
5674 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5675 | i.op[op].disps = 0; |
5676 | i.disp_operands--; | |
5677 | } | |
5678 | else if (flag_code == CODE_64BIT) | |
5679 | { | |
91d6fa6a | 5680 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5681 | { |
40fb9820 L |
5682 | i.types[op].bitfield.disp64 = 0; |
5683 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5684 | } |
0e1147d9 | 5685 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5686 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5687 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5688 | } |
40fb9820 L |
5689 | if ((i.types[op].bitfield.disp32 |
5690 | || i.types[op].bitfield.disp32s | |
5691 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5692 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5693 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5694 | } |
67a4f2b7 AO |
5695 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5696 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5697 | { | |
5698 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5699 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5700 | i.types[op].bitfield.disp8 = 0; |
5701 | i.types[op].bitfield.disp16 = 0; | |
5702 | i.types[op].bitfield.disp32 = 0; | |
5703 | i.types[op].bitfield.disp32s = 0; | |
5704 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5705 | } |
5706 | else | |
b300c311 | 5707 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5708 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5709 | } |
29b0f896 AM |
5710 | } |
5711 | ||
4a1b91ea L |
5712 | /* Return 1 if there is a match in broadcast bytes between operand |
5713 | GIVEN and instruction template T. */ | |
5714 | ||
5715 | static INLINE int | |
5716 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5717 | { | |
5718 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5719 | && i.types[given].bitfield.byte) | |
5720 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5721 | && i.types[given].bitfield.word) | |
5722 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5723 | && i.types[given].bitfield.dword) | |
5724 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5725 | && i.types[given].bitfield.qword)); | |
5726 | } | |
5727 | ||
6c30d220 L |
5728 | /* Check if operands are valid for the instruction. */ |
5729 | ||
5730 | static int | |
5731 | check_VecOperands (const insn_template *t) | |
5732 | { | |
43234a1e | 5733 | unsigned int op; |
e2195274 | 5734 | i386_cpu_flags cpu; |
e2195274 JB |
5735 | |
5736 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5737 | any one operand are implicity requiring AVX512VL support if the actual | |
5738 | operand size is YMMword or XMMword. Since this function runs after | |
5739 | template matching, there's no need to check for YMMword/XMMword in | |
5740 | the template. */ | |
5741 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5742 | if (!cpu_flags_all_zero (&cpu) | |
5743 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5744 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5745 | { | |
5746 | for (op = 0; op < t->operands; ++op) | |
5747 | { | |
5748 | if (t->operand_types[op].bitfield.zmmword | |
5749 | && (i.types[op].bitfield.ymmword | |
5750 | || i.types[op].bitfield.xmmword)) | |
5751 | { | |
5752 | i.error = unsupported; | |
5753 | return 1; | |
5754 | } | |
5755 | } | |
5756 | } | |
43234a1e | 5757 | |
6c30d220 L |
5758 | /* Without VSIB byte, we can't have a vector register for index. */ |
5759 | if (!t->opcode_modifier.vecsib | |
5760 | && i.index_reg | |
1b54b8d7 JB |
5761 | && (i.index_reg->reg_type.bitfield.xmmword |
5762 | || i.index_reg->reg_type.bitfield.ymmword | |
5763 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5764 | { |
5765 | i.error = unsupported_vector_index_register; | |
5766 | return 1; | |
5767 | } | |
5768 | ||
ad8ecc81 MZ |
5769 | /* Check if default mask is allowed. */ |
5770 | if (t->opcode_modifier.nodefmask | |
5771 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5772 | { | |
5773 | i.error = no_default_mask; | |
5774 | return 1; | |
5775 | } | |
5776 | ||
7bab8ab5 JB |
5777 | /* For VSIB byte, we need a vector register for index, and all vector |
5778 | registers must be distinct. */ | |
5779 | if (t->opcode_modifier.vecsib) | |
5780 | { | |
5781 | if (!i.index_reg | |
6c30d220 | 5782 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5783 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5784 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5785 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5786 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5787 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5788 | { |
5789 | i.error = invalid_vsib_address; | |
5790 | return 1; | |
5791 | } | |
5792 | ||
43234a1e L |
5793 | gas_assert (i.reg_operands == 2 || i.mask); |
5794 | if (i.reg_operands == 2 && !i.mask) | |
5795 | { | |
3528c362 | 5796 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5797 | gas_assert (i.types[0].bitfield.xmmword |
5798 | || i.types[0].bitfield.ymmword); | |
3528c362 | 5799 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5800 | gas_assert (i.types[2].bitfield.xmmword |
5801 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5802 | if (operand_check == check_none) |
5803 | return 0; | |
5804 | if (register_number (i.op[0].regs) | |
5805 | != register_number (i.index_reg) | |
5806 | && register_number (i.op[2].regs) | |
5807 | != register_number (i.index_reg) | |
5808 | && register_number (i.op[0].regs) | |
5809 | != register_number (i.op[2].regs)) | |
5810 | return 0; | |
5811 | if (operand_check == check_error) | |
5812 | { | |
5813 | i.error = invalid_vector_register_set; | |
5814 | return 1; | |
5815 | } | |
5816 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5817 | } | |
8444f82a MZ |
5818 | else if (i.reg_operands == 1 && i.mask) |
5819 | { | |
3528c362 | 5820 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
5821 | && (i.types[1].bitfield.xmmword |
5822 | || i.types[1].bitfield.ymmword | |
5823 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5824 | && (register_number (i.op[1].regs) |
5825 | == register_number (i.index_reg))) | |
5826 | { | |
5827 | if (operand_check == check_error) | |
5828 | { | |
5829 | i.error = invalid_vector_register_set; | |
5830 | return 1; | |
5831 | } | |
5832 | if (operand_check != check_none) | |
5833 | as_warn (_("index and destination registers should be distinct")); | |
5834 | } | |
5835 | } | |
43234a1e | 5836 | } |
7bab8ab5 | 5837 | |
43234a1e L |
5838 | /* Check if broadcast is supported by the instruction and is applied |
5839 | to the memory operand. */ | |
5840 | if (i.broadcast) | |
5841 | { | |
8e6e0792 | 5842 | i386_operand_type type, overlap; |
43234a1e L |
5843 | |
5844 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5845 | and its broadcast bytes match the memory operand. */ |
32546502 | 5846 | op = i.broadcast->operand; |
8e6e0792 | 5847 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5848 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5849 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5850 | && !match_broadcast_size (t, op))) |
43234a1e L |
5851 | { |
5852 | bad_broadcast: | |
5853 | i.error = unsupported_broadcast; | |
5854 | return 1; | |
5855 | } | |
8e6e0792 | 5856 | |
4a1b91ea L |
5857 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5858 | * i.broadcast->type); | |
8e6e0792 | 5859 | operand_type_set (&type, 0); |
4a1b91ea | 5860 | switch (i.broadcast->bytes) |
8e6e0792 | 5861 | { |
4a1b91ea L |
5862 | case 2: |
5863 | type.bitfield.word = 1; | |
5864 | break; | |
5865 | case 4: | |
5866 | type.bitfield.dword = 1; | |
5867 | break; | |
8e6e0792 JB |
5868 | case 8: |
5869 | type.bitfield.qword = 1; | |
5870 | break; | |
5871 | case 16: | |
5872 | type.bitfield.xmmword = 1; | |
5873 | break; | |
5874 | case 32: | |
5875 | type.bitfield.ymmword = 1; | |
5876 | break; | |
5877 | case 64: | |
5878 | type.bitfield.zmmword = 1; | |
5879 | break; | |
5880 | default: | |
5881 | goto bad_broadcast; | |
5882 | } | |
5883 | ||
5884 | overlap = operand_type_and (type, t->operand_types[op]); | |
bc49bfd8 JB |
5885 | if (t->operand_types[op].bitfield.class == RegSIMD |
5886 | && t->operand_types[op].bitfield.byte | |
5887 | + t->operand_types[op].bitfield.word | |
5888 | + t->operand_types[op].bitfield.dword | |
5889 | + t->operand_types[op].bitfield.qword > 1) | |
5890 | { | |
5891 | overlap.bitfield.xmmword = 0; | |
5892 | overlap.bitfield.ymmword = 0; | |
5893 | overlap.bitfield.zmmword = 0; | |
5894 | } | |
8e6e0792 JB |
5895 | if (operand_type_all_zero (&overlap)) |
5896 | goto bad_broadcast; | |
5897 | ||
5898 | if (t->opcode_modifier.checkregsize) | |
5899 | { | |
5900 | unsigned int j; | |
5901 | ||
e2195274 | 5902 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5903 | for (j = 0; j < i.operands; ++j) |
5904 | { | |
5905 | if (j != op | |
5906 | && !operand_type_register_match(i.types[j], | |
5907 | t->operand_types[j], | |
5908 | type, | |
5909 | t->operand_types[op])) | |
5910 | goto bad_broadcast; | |
5911 | } | |
5912 | } | |
43234a1e L |
5913 | } |
5914 | /* If broadcast is supported in this instruction, we need to check if | |
5915 | operand of one-element size isn't specified without broadcast. */ | |
5916 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5917 | { | |
5918 | /* Find memory operand. */ | |
5919 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5920 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
5921 | break; |
5922 | gas_assert (op < i.operands); | |
5923 | /* Check size of the memory operand. */ | |
4a1b91ea | 5924 | if (match_broadcast_size (t, op)) |
43234a1e L |
5925 | { |
5926 | i.error = broadcast_needed; | |
5927 | return 1; | |
5928 | } | |
5929 | } | |
c39e5b26 JB |
5930 | else |
5931 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5932 | |
5933 | /* Check if requested masking is supported. */ | |
ae2387fe | 5934 | if (i.mask) |
43234a1e | 5935 | { |
ae2387fe JB |
5936 | switch (t->opcode_modifier.masking) |
5937 | { | |
5938 | case BOTH_MASKING: | |
5939 | break; | |
5940 | case MERGING_MASKING: | |
5941 | if (i.mask->zeroing) | |
5942 | { | |
5943 | case 0: | |
5944 | i.error = unsupported_masking; | |
5945 | return 1; | |
5946 | } | |
5947 | break; | |
5948 | case DYNAMIC_MASKING: | |
5949 | /* Memory destinations allow only merging masking. */ | |
5950 | if (i.mask->zeroing && i.mem_operands) | |
5951 | { | |
5952 | /* Find memory operand. */ | |
5953 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5954 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5955 | break; |
5956 | gas_assert (op < i.operands); | |
5957 | if (op == i.operands - 1) | |
5958 | { | |
5959 | i.error = unsupported_masking; | |
5960 | return 1; | |
5961 | } | |
5962 | } | |
5963 | break; | |
5964 | default: | |
5965 | abort (); | |
5966 | } | |
43234a1e L |
5967 | } |
5968 | ||
5969 | /* Check if masking is applied to dest operand. */ | |
5970 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5971 | { | |
5972 | i.error = mask_not_on_destination; | |
5973 | return 1; | |
5974 | } | |
5975 | ||
43234a1e L |
5976 | /* Check RC/SAE. */ |
5977 | if (i.rounding) | |
5978 | { | |
a80195f1 JB |
5979 | if (!t->opcode_modifier.sae |
5980 | || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding)) | |
43234a1e L |
5981 | { |
5982 | i.error = unsupported_rc_sae; | |
5983 | return 1; | |
5984 | } | |
5985 | /* If the instruction has several immediate operands and one of | |
5986 | them is rounding, the rounding operand should be the last | |
5987 | immediate operand. */ | |
5988 | if (i.imm_operands > 1 | |
5989 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5990 | { |
43234a1e | 5991 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5992 | return 1; |
5993 | } | |
6c30d220 L |
5994 | } |
5995 | ||
43234a1e | 5996 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5997 | if (t->opcode_modifier.disp8memshift |
5998 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5999 | { |
6000 | if (i.broadcast) | |
4a1b91ea | 6001 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 6002 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 6003 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
6004 | else |
6005 | { | |
6006 | const i386_operand_type *type = NULL; | |
6007 | ||
6008 | i.memshift = 0; | |
6009 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6010 | if (i.flags[op] & Operand_Mem) |
7091c612 | 6011 | { |
4174bfff JB |
6012 | if (t->opcode_modifier.evex == EVEXLIG) |
6013 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
6014 | else if (t->operand_types[op].bitfield.xmmword | |
6015 | + t->operand_types[op].bitfield.ymmword | |
6016 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
6017 | type = &t->operand_types[op]; |
6018 | else if (!i.types[op].bitfield.unspecified) | |
6019 | type = &i.types[op]; | |
6020 | } | |
3528c362 | 6021 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 6022 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
6023 | { |
6024 | if (i.types[op].bitfield.zmmword) | |
6025 | i.memshift = 6; | |
6026 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
6027 | i.memshift = 5; | |
6028 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
6029 | i.memshift = 4; | |
6030 | } | |
6031 | ||
6032 | if (type) | |
6033 | { | |
6034 | if (type->bitfield.zmmword) | |
6035 | i.memshift = 6; | |
6036 | else if (type->bitfield.ymmword) | |
6037 | i.memshift = 5; | |
6038 | else if (type->bitfield.xmmword) | |
6039 | i.memshift = 4; | |
6040 | } | |
6041 | ||
6042 | /* For the check in fits_in_disp8(). */ | |
6043 | if (i.memshift == 0) | |
6044 | i.memshift = -1; | |
6045 | } | |
43234a1e L |
6046 | |
6047 | for (op = 0; op < i.operands; op++) | |
6048 | if (operand_type_check (i.types[op], disp) | |
6049 | && i.op[op].disps->X_op == O_constant) | |
6050 | { | |
b5014f7a | 6051 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 6052 | { |
b5014f7a JB |
6053 | i.types[op].bitfield.disp8 = 1; |
6054 | return 0; | |
43234a1e | 6055 | } |
b5014f7a | 6056 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
6057 | } |
6058 | } | |
b5014f7a JB |
6059 | |
6060 | i.memshift = 0; | |
43234a1e | 6061 | |
6c30d220 L |
6062 | return 0; |
6063 | } | |
6064 | ||
43f3e2ee | 6065 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
6066 | operand types. */ |
6067 | ||
6068 | static int | |
6069 | VEX_check_operands (const insn_template *t) | |
6070 | { | |
86fa6981 | 6071 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 6072 | { |
86fa6981 | 6073 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 6074 | if (!is_evex_encoding (t)) |
86fa6981 L |
6075 | { |
6076 | i.error = unsupported; | |
6077 | return 1; | |
6078 | } | |
6079 | return 0; | |
43234a1e L |
6080 | } |
6081 | ||
a683cc34 | 6082 | if (!t->opcode_modifier.vex) |
86fa6981 L |
6083 | { |
6084 | /* This instruction template doesn't have VEX prefix. */ | |
6085 | if (i.vec_encoding != vex_encoding_default) | |
6086 | { | |
6087 | i.error = unsupported; | |
6088 | return 1; | |
6089 | } | |
6090 | return 0; | |
6091 | } | |
a683cc34 | 6092 | |
9d3bf266 JB |
6093 | /* Check the special Imm4 cases; must be the first operand. */ |
6094 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
a683cc34 SP |
6095 | { |
6096 | if (i.op[0].imms->X_op != O_constant | |
6097 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 6098 | { |
a65babc9 | 6099 | i.error = bad_imm4; |
891edac4 L |
6100 | return 1; |
6101 | } | |
a683cc34 | 6102 | |
9d3bf266 JB |
6103 | /* Turn off Imm<N> so that update_imm won't complain. */ |
6104 | operand_type_set (&i.types[0], 0); | |
a683cc34 SP |
6105 | } |
6106 | ||
6107 | return 0; | |
6108 | } | |
6109 | ||
d3ce72d0 | 6110 | static const insn_template * |
83b16ac6 | 6111 | match_template (char mnem_suffix) |
29b0f896 AM |
6112 | { |
6113 | /* Points to template once we've found it. */ | |
d3ce72d0 | 6114 | const insn_template *t; |
40fb9820 | 6115 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 6116 | i386_operand_type overlap4; |
29b0f896 | 6117 | unsigned int found_reverse_match; |
dc2be329 | 6118 | i386_opcode_modifier suffix_check; |
40fb9820 | 6119 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 6120 | int addr_prefix_disp; |
45a4bb20 | 6121 | unsigned int j, size_match, check_register; |
5614d22c | 6122 | enum i386_error specific_error = 0; |
29b0f896 | 6123 | |
c0f3af97 L |
6124 | #if MAX_OPERANDS != 5 |
6125 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
6126 | #endif |
6127 | ||
29b0f896 | 6128 | found_reverse_match = 0; |
539e75ad | 6129 | addr_prefix_disp = -1; |
40fb9820 | 6130 | |
dc2be329 | 6131 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 6132 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
6133 | switch (mnem_suffix) |
6134 | { | |
6135 | case BYTE_MNEM_SUFFIX: | |
6136 | suffix_check.no_bsuf = 1; | |
6137 | break; | |
6138 | case WORD_MNEM_SUFFIX: | |
6139 | suffix_check.no_wsuf = 1; | |
6140 | break; | |
6141 | case SHORT_MNEM_SUFFIX: | |
6142 | suffix_check.no_ssuf = 1; | |
6143 | break; | |
6144 | case LONG_MNEM_SUFFIX: | |
6145 | suffix_check.no_lsuf = 1; | |
6146 | break; | |
6147 | case QWORD_MNEM_SUFFIX: | |
6148 | suffix_check.no_qsuf = 1; | |
6149 | break; | |
6150 | default: | |
6151 | /* NB: In Intel syntax, normally we can check for memory operand | |
6152 | size when there is no mnemonic suffix. But jmp and call have | |
6153 | 2 different encodings with Dword memory operand size, one with | |
6154 | No_ldSuf and the other without. i.suffix is set to | |
6155 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
6156 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
6157 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
6158 | } |
6159 | ||
01559ecc L |
6160 | /* Must have right number of operands. */ |
6161 | i.error = number_of_operands_mismatch; | |
6162 | ||
45aa61fe | 6163 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 6164 | { |
539e75ad | 6165 | addr_prefix_disp = -1; |
dbbc8b7e | 6166 | found_reverse_match = 0; |
539e75ad | 6167 | |
29b0f896 AM |
6168 | if (i.operands != t->operands) |
6169 | continue; | |
6170 | ||
50aecf8c | 6171 | /* Check processor support. */ |
a65babc9 | 6172 | i.error = unsupported; |
45a4bb20 | 6173 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
6174 | continue; |
6175 | ||
e1d4d893 | 6176 | /* Check AT&T mnemonic. */ |
a65babc9 | 6177 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 6178 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
6179 | continue; |
6180 | ||
4b5aaf5f | 6181 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 6182 | i.error = unsupported_syntax; |
5c07affc | 6183 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 6184 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
6185 | continue; |
6186 | ||
4b5aaf5f L |
6187 | /* Check Intel64/AMD64 ISA. */ |
6188 | switch (isa64) | |
6189 | { | |
6190 | default: | |
6191 | /* Default: Don't accept Intel64. */ | |
6192 | if (t->opcode_modifier.isa64 == INTEL64) | |
6193 | continue; | |
6194 | break; | |
6195 | case amd64: | |
6196 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
6197 | if (t->opcode_modifier.isa64 >= INTEL64) | |
6198 | continue; | |
6199 | break; | |
6200 | case intel64: | |
6201 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 6202 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
6203 | continue; |
6204 | break; | |
6205 | } | |
6206 | ||
dc2be329 | 6207 | /* Check the suffix. */ |
a65babc9 | 6208 | i.error = invalid_instruction_suffix; |
dc2be329 L |
6209 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
6210 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
6211 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
6212 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
6213 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
6214 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 6215 | continue; |
29b0f896 | 6216 | |
3ac21baa JB |
6217 | size_match = operand_size_match (t); |
6218 | if (!size_match) | |
7d5e4556 | 6219 | continue; |
539e75ad | 6220 | |
6f2f06be JB |
6221 | /* This is intentionally not |
6222 | ||
0cfa3eb3 | 6223 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
6224 | |
6225 | as the case of a missing * on the operand is accepted (perhaps with | |
6226 | a warning, issued further down). */ | |
0cfa3eb3 | 6227 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
6f2f06be JB |
6228 | { |
6229 | i.error = operand_type_mismatch; | |
6230 | continue; | |
6231 | } | |
6232 | ||
5c07affc L |
6233 | for (j = 0; j < MAX_OPERANDS; j++) |
6234 | operand_types[j] = t->operand_types[j]; | |
6235 | ||
e365e234 JB |
6236 | /* In general, don't allow |
6237 | - 64-bit operands outside of 64-bit mode, | |
6238 | - 32-bit operands on pre-386. */ | |
4873e243 | 6239 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
e365e234 JB |
6240 | if (((i.suffix == QWORD_MNEM_SUFFIX |
6241 | && flag_code != CODE_64BIT | |
6242 | && (t->base_opcode != 0x0fc7 | |
6243 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
6244 | || (i.suffix == LONG_MNEM_SUFFIX | |
6245 | && !cpu_arch_flags.bitfield.cpui386)) | |
45aa61fe | 6246 | && (intel_syntax |
3cd7f3e3 | 6247 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
45aa61fe AM |
6248 | && !intel_float_operand (t->name)) |
6249 | : intel_float_operand (t->name) != 2) | |
4873e243 JB |
6250 | && (t->operands == i.imm_operands |
6251 | || (operand_types[i.imm_operands].bitfield.class != RegMMX | |
6252 | && operand_types[i.imm_operands].bitfield.class != RegSIMD | |
6253 | && operand_types[i.imm_operands].bitfield.class != RegMask) | |
6254 | || (operand_types[j].bitfield.class != RegMMX | |
6255 | && operand_types[j].bitfield.class != RegSIMD | |
6256 | && operand_types[j].bitfield.class != RegMask)) | |
6257 | && !t->opcode_modifier.vecsib) | |
192dc9c6 JB |
6258 | continue; |
6259 | ||
29b0f896 | 6260 | /* Do not verify operands when there are none. */ |
e365e234 JB |
6261 | if (!t->operands) |
6262 | /* We've found a match; break out of loop. */ | |
6263 | break; | |
252b5132 | 6264 | |
48bcea9f JB |
6265 | if (!t->opcode_modifier.jump |
6266 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
6267 | { | |
6268 | /* There should be only one Disp operand. */ | |
6269 | for (j = 0; j < MAX_OPERANDS; j++) | |
6270 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 6271 | break; |
48bcea9f JB |
6272 | if (j < MAX_OPERANDS) |
6273 | { | |
6274 | bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0); | |
6275 | ||
6276 | addr_prefix_disp = j; | |
6277 | ||
6278 | /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16 | |
6279 | operand into Disp32/Disp32/Disp16/Disp32 operand. */ | |
6280 | switch (flag_code) | |
40fb9820 | 6281 | { |
48bcea9f JB |
6282 | case CODE_16BIT: |
6283 | override = !override; | |
6284 | /* Fall through. */ | |
6285 | case CODE_32BIT: | |
6286 | if (operand_types[j].bitfield.disp32 | |
6287 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 6288 | { |
48bcea9f JB |
6289 | operand_types[j].bitfield.disp16 = override; |
6290 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 6291 | } |
48bcea9f JB |
6292 | operand_types[j].bitfield.disp32s = 0; |
6293 | operand_types[j].bitfield.disp64 = 0; | |
6294 | break; | |
6295 | ||
6296 | case CODE_64BIT: | |
6297 | if (operand_types[j].bitfield.disp32s | |
6298 | || operand_types[j].bitfield.disp64) | |
40fb9820 | 6299 | { |
48bcea9f JB |
6300 | operand_types[j].bitfield.disp64 &= !override; |
6301 | operand_types[j].bitfield.disp32s &= !override; | |
6302 | operand_types[j].bitfield.disp32 = override; | |
40fb9820 | 6303 | } |
48bcea9f JB |
6304 | operand_types[j].bitfield.disp16 = 0; |
6305 | break; | |
40fb9820 | 6306 | } |
539e75ad | 6307 | } |
48bcea9f | 6308 | } |
539e75ad | 6309 | |
02a86693 L |
6310 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
6311 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
6312 | continue; | |
6313 | ||
56ffb741 | 6314 | /* We check register size if needed. */ |
e2195274 JB |
6315 | if (t->opcode_modifier.checkregsize) |
6316 | { | |
6317 | check_register = (1 << t->operands) - 1; | |
6318 | if (i.broadcast) | |
6319 | check_register &= ~(1 << i.broadcast->operand); | |
6320 | } | |
6321 | else | |
6322 | check_register = 0; | |
6323 | ||
c6fb90c8 | 6324 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
6325 | switch (t->operands) |
6326 | { | |
6327 | case 1: | |
40fb9820 | 6328 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
6329 | continue; |
6330 | break; | |
6331 | case 2: | |
33eaf5de | 6332 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
6333 | only in 32bit mode and we can use opcode 0x90. In 64bit |
6334 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
6335 | zero-extend %eax to %rax. */ | |
6336 | if (flag_code == CODE_64BIT | |
6337 | && t->base_opcode == 0x90 | |
75e5731b JB |
6338 | && i.types[0].bitfield.instance == Accum |
6339 | && i.types[0].bitfield.dword | |
6340 | && i.types[1].bitfield.instance == Accum | |
6341 | && i.types[1].bitfield.dword) | |
8b38ad71 | 6342 | continue; |
1212781b JB |
6343 | /* xrelease mov %eax, <disp> is another special case. It must not |
6344 | match the accumulator-only encoding of mov. */ | |
6345 | if (flag_code != CODE_64BIT | |
6346 | && i.hle_prefix | |
6347 | && t->base_opcode == 0xa0 | |
75e5731b | 6348 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 6349 | && (i.flags[1] & Operand_Mem)) |
1212781b | 6350 | continue; |
f5eb1d70 JB |
6351 | /* Fall through. */ |
6352 | ||
6353 | case 3: | |
3ac21baa JB |
6354 | if (!(size_match & MATCH_STRAIGHT)) |
6355 | goto check_reverse; | |
64c49ab3 JB |
6356 | /* Reverse direction of operands if swapping is possible in the first |
6357 | place (operands need to be symmetric) and | |
6358 | - the load form is requested, and the template is a store form, | |
6359 | - the store form is requested, and the template is a load form, | |
6360 | - the non-default (swapped) form is requested. */ | |
6361 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 6362 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
6363 | && !operand_type_all_zero (&overlap1)) |
6364 | switch (i.dir_encoding) | |
6365 | { | |
6366 | case dir_encoding_load: | |
6367 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6368 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
6369 | goto check_reverse; |
6370 | break; | |
6371 | ||
6372 | case dir_encoding_store: | |
6373 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6374 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
6375 | goto check_reverse; |
6376 | break; | |
6377 | ||
6378 | case dir_encoding_swap: | |
6379 | goto check_reverse; | |
6380 | ||
6381 | case dir_encoding_default: | |
6382 | break; | |
6383 | } | |
86fa6981 | 6384 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6385 | if ((i.dir_encoding == dir_encoding_store |
6386 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6387 | && i.mem_operands == 0 |
6388 | && t->opcode_modifier.load) | |
fa99fab2 | 6389 | continue; |
1a0670f3 | 6390 | /* Fall through. */ |
f48ff2ae | 6391 | case 4: |
c0f3af97 | 6392 | case 5: |
c6fb90c8 | 6393 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
6394 | if (!operand_type_match (overlap0, i.types[0]) |
6395 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 6396 | || ((check_register & 3) == 3 |
dc821c5f | 6397 | && !operand_type_register_match (i.types[0], |
40fb9820 | 6398 | operand_types[0], |
dc821c5f | 6399 | i.types[1], |
40fb9820 | 6400 | operand_types[1]))) |
29b0f896 AM |
6401 | { |
6402 | /* Check if other direction is valid ... */ | |
38e314eb | 6403 | if (!t->opcode_modifier.d) |
29b0f896 AM |
6404 | continue; |
6405 | ||
dc1e8a47 | 6406 | check_reverse: |
3ac21baa JB |
6407 | if (!(size_match & MATCH_REVERSE)) |
6408 | continue; | |
29b0f896 | 6409 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
6410 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
6411 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 6412 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 6413 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 6414 | || (check_register |
dc821c5f | 6415 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
6416 | operand_types[i.operands - 1], |
6417 | i.types[i.operands - 1], | |
45664ddb | 6418 | operand_types[0]))) |
29b0f896 AM |
6419 | { |
6420 | /* Does not match either direction. */ | |
6421 | continue; | |
6422 | } | |
38e314eb | 6423 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 6424 | we've found. */ |
38e314eb JB |
6425 | if (!t->opcode_modifier.d) |
6426 | found_reverse_match = 0; | |
6427 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 6428 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 6429 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 6430 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
6431 | || operand_types[0].bitfield.class == RegMMX |
6432 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
6433 | || is_any_vex_encoding(t)) |
6434 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
6435 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 6436 | else |
38e314eb | 6437 | found_reverse_match = Opcode_D; |
40fb9820 | 6438 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6439 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6440 | } |
f48ff2ae | 6441 | else |
29b0f896 | 6442 | { |
f48ff2ae | 6443 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
6444 | switch (t->operands) |
6445 | { | |
c0f3af97 L |
6446 | case 5: |
6447 | overlap4 = operand_type_and (i.types[4], | |
6448 | operand_types[4]); | |
1a0670f3 | 6449 | /* Fall through. */ |
d1cbb4db | 6450 | case 4: |
c6fb90c8 L |
6451 | overlap3 = operand_type_and (i.types[3], |
6452 | operand_types[3]); | |
1a0670f3 | 6453 | /* Fall through. */ |
d1cbb4db | 6454 | case 3: |
c6fb90c8 L |
6455 | overlap2 = operand_type_and (i.types[2], |
6456 | operand_types[2]); | |
d1cbb4db L |
6457 | break; |
6458 | } | |
29b0f896 | 6459 | |
f48ff2ae L |
6460 | switch (t->operands) |
6461 | { | |
c0f3af97 L |
6462 | case 5: |
6463 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 6464 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6465 | operand_types[3], |
c0f3af97 L |
6466 | i.types[4], |
6467 | operand_types[4])) | |
6468 | continue; | |
1a0670f3 | 6469 | /* Fall through. */ |
f48ff2ae | 6470 | case 4: |
40fb9820 | 6471 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6472 | || ((check_register & 0xa) == 0xa |
6473 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6474 | operand_types[1], |
6475 | i.types[3], | |
e2195274 JB |
6476 | operand_types[3])) |
6477 | || ((check_register & 0xc) == 0xc | |
6478 | && !operand_type_register_match (i.types[2], | |
6479 | operand_types[2], | |
6480 | i.types[3], | |
6481 | operand_types[3]))) | |
f48ff2ae | 6482 | continue; |
1a0670f3 | 6483 | /* Fall through. */ |
f48ff2ae L |
6484 | case 3: |
6485 | /* Here we make use of the fact that there are no | |
23e42951 | 6486 | reverse match 3 operand instructions. */ |
40fb9820 | 6487 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6488 | || ((check_register & 5) == 5 |
6489 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6490 | operand_types[0], |
6491 | i.types[2], | |
e2195274 JB |
6492 | operand_types[2])) |
6493 | || ((check_register & 6) == 6 | |
6494 | && !operand_type_register_match (i.types[1], | |
6495 | operand_types[1], | |
6496 | i.types[2], | |
6497 | operand_types[2]))) | |
f48ff2ae L |
6498 | continue; |
6499 | break; | |
6500 | } | |
29b0f896 | 6501 | } |
f48ff2ae | 6502 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6503 | slip through to break. */ |
6504 | } | |
c0f3af97 | 6505 | |
5614d22c JB |
6506 | /* Check if vector and VEX operands are valid. */ |
6507 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
6508 | { | |
6509 | specific_error = i.error; | |
6510 | continue; | |
6511 | } | |
a683cc34 | 6512 | |
29b0f896 AM |
6513 | /* We've found a match; break out of loop. */ |
6514 | break; | |
6515 | } | |
6516 | ||
6517 | if (t == current_templates->end) | |
6518 | { | |
6519 | /* We found no match. */ | |
a65babc9 | 6520 | const char *err_msg; |
5614d22c | 6521 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6522 | { |
6523 | default: | |
6524 | abort (); | |
86e026a4 | 6525 | case operand_size_mismatch: |
a65babc9 L |
6526 | err_msg = _("operand size mismatch"); |
6527 | break; | |
6528 | case operand_type_mismatch: | |
6529 | err_msg = _("operand type mismatch"); | |
6530 | break; | |
6531 | case register_type_mismatch: | |
6532 | err_msg = _("register type mismatch"); | |
6533 | break; | |
6534 | case number_of_operands_mismatch: | |
6535 | err_msg = _("number of operands mismatch"); | |
6536 | break; | |
6537 | case invalid_instruction_suffix: | |
6538 | err_msg = _("invalid instruction suffix"); | |
6539 | break; | |
6540 | case bad_imm4: | |
4a2608e3 | 6541 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6542 | break; |
a65babc9 L |
6543 | case unsupported_with_intel_mnemonic: |
6544 | err_msg = _("unsupported with Intel mnemonic"); | |
6545 | break; | |
6546 | case unsupported_syntax: | |
6547 | err_msg = _("unsupported syntax"); | |
6548 | break; | |
6549 | case unsupported: | |
35262a23 | 6550 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6551 | current_templates->start->name); |
6552 | return NULL; | |
6c30d220 L |
6553 | case invalid_vsib_address: |
6554 | err_msg = _("invalid VSIB address"); | |
6555 | break; | |
7bab8ab5 JB |
6556 | case invalid_vector_register_set: |
6557 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6558 | break; | |
6c30d220 L |
6559 | case unsupported_vector_index_register: |
6560 | err_msg = _("unsupported vector index register"); | |
6561 | break; | |
43234a1e L |
6562 | case unsupported_broadcast: |
6563 | err_msg = _("unsupported broadcast"); | |
6564 | break; | |
43234a1e L |
6565 | case broadcast_needed: |
6566 | err_msg = _("broadcast is needed for operand of such type"); | |
6567 | break; | |
6568 | case unsupported_masking: | |
6569 | err_msg = _("unsupported masking"); | |
6570 | break; | |
6571 | case mask_not_on_destination: | |
6572 | err_msg = _("mask not on destination operand"); | |
6573 | break; | |
6574 | case no_default_mask: | |
6575 | err_msg = _("default mask isn't allowed"); | |
6576 | break; | |
6577 | case unsupported_rc_sae: | |
6578 | err_msg = _("unsupported static rounding/sae"); | |
6579 | break; | |
6580 | case rc_sae_operand_not_last_imm: | |
6581 | if (intel_syntax) | |
6582 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6583 | else | |
6584 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6585 | break; | |
6586 | case invalid_register_operand: | |
6587 | err_msg = _("invalid register operand"); | |
6588 | break; | |
a65babc9 L |
6589 | } |
6590 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6591 | current_templates->start->name); |
fa99fab2 | 6592 | return NULL; |
29b0f896 | 6593 | } |
252b5132 | 6594 | |
29b0f896 AM |
6595 | if (!quiet_warnings) |
6596 | { | |
6597 | if (!intel_syntax | |
0cfa3eb3 | 6598 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
6f2f06be | 6599 | as_warn (_("indirect %s without `*'"), t->name); |
29b0f896 | 6600 | |
40fb9820 | 6601 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 6602 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
6603 | { |
6604 | /* Warn them that a data or address size prefix doesn't | |
6605 | affect assembly of the next line of code. */ | |
6606 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6607 | } | |
6608 | } | |
6609 | ||
6610 | /* Copy the template we found. */ | |
6611 | i.tm = *t; | |
539e75ad L |
6612 | |
6613 | if (addr_prefix_disp != -1) | |
6614 | i.tm.operand_types[addr_prefix_disp] | |
6615 | = operand_types[addr_prefix_disp]; | |
6616 | ||
29b0f896 AM |
6617 | if (found_reverse_match) |
6618 | { | |
dfd69174 JB |
6619 | /* If we found a reverse match we must alter the opcode direction |
6620 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6621 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6622 | |
6623 | i.tm.base_opcode ^= found_reverse_match; | |
6624 | ||
f5eb1d70 JB |
6625 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6626 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6627 | |
6628 | /* Certain SIMD insns have their load forms specified in the opcode | |
6629 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6630 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6631 | i.tm.opcode_modifier.regmem | |
6632 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6633 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6634 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6635 | } |
6636 | ||
fa99fab2 | 6637 | return t; |
29b0f896 AM |
6638 | } |
6639 | ||
6640 | static int | |
e3bb37b5 | 6641 | check_string (void) |
29b0f896 | 6642 | { |
51c8edf6 JB |
6643 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
6644 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 6645 | |
51c8edf6 | 6646 | if (i.seg[op] != NULL && i.seg[op] != &es) |
29b0f896 | 6647 | { |
51c8edf6 JB |
6648 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
6649 | i.tm.name, | |
6650 | intel_syntax ? i.tm.operands - es_op : es_op + 1, | |
6651 | register_prefix); | |
6652 | return 0; | |
29b0f896 | 6653 | } |
51c8edf6 JB |
6654 | |
6655 | /* There's only ever one segment override allowed per instruction. | |
6656 | This instruction possibly has a legal segment override on the | |
6657 | second operand, so copy the segment to where non-string | |
6658 | instructions store it, allowing common code. */ | |
6659 | i.seg[op] = i.seg[1]; | |
6660 | ||
29b0f896 AM |
6661 | return 1; |
6662 | } | |
6663 | ||
6664 | static int | |
543613e9 | 6665 | process_suffix (void) |
29b0f896 AM |
6666 | { |
6667 | /* If matched instruction specifies an explicit instruction mnemonic | |
6668 | suffix, use it. */ | |
673fe0f0 | 6669 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6670 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6671 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6672 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6673 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6674 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 6675 | else if (i.reg_operands |
c8f8eebc JB |
6676 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
6677 | && !i.tm.opcode_modifier.addrprefixopreg) | |
29b0f896 | 6678 | { |
65fca059 JB |
6679 | unsigned int numop = i.operands; |
6680 | ||
6681 | /* movsx/movzx want only their source operand considered here, for the | |
6682 | ambiguity checking below. The suffix will be replaced afterwards | |
6683 | to represent the destination (register). */ | |
6684 | if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w) | |
6685 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) | |
6686 | --i.operands; | |
6687 | ||
643bb870 JB |
6688 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
6689 | if (i.tm.base_opcode == 0xf20f38f0 | |
6690 | && i.tm.operand_types[1].bitfield.qword) | |
6691 | i.rex |= REX_W; | |
6692 | ||
29b0f896 | 6693 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 6694 | based on GPR operands. */ |
29b0f896 AM |
6695 | if (!i.suffix) |
6696 | { | |
6697 | /* We take i.suffix from the last register operand specified, | |
6698 | Destination register type is more significant than source | |
381d071f L |
6699 | register type. crc32 in SSE4.2 prefers source register |
6700 | type. */ | |
1a035124 | 6701 | unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1; |
20592a94 | 6702 | |
1a035124 JB |
6703 | while (op--) |
6704 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
6705 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
6706 | { | |
6707 | if (i.types[op].bitfield.class != Reg) | |
6708 | continue; | |
6709 | if (i.types[op].bitfield.byte) | |
6710 | i.suffix = BYTE_MNEM_SUFFIX; | |
6711 | else if (i.types[op].bitfield.word) | |
6712 | i.suffix = WORD_MNEM_SUFFIX; | |
6713 | else if (i.types[op].bitfield.dword) | |
6714 | i.suffix = LONG_MNEM_SUFFIX; | |
6715 | else if (i.types[op].bitfield.qword) | |
6716 | i.suffix = QWORD_MNEM_SUFFIX; | |
6717 | else | |
6718 | continue; | |
6719 | break; | |
6720 | } | |
65fca059 JB |
6721 | |
6722 | /* As an exception, movsx/movzx silently default to a byte source | |
6723 | in AT&T mode. */ | |
6724 | if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w | |
6725 | && !i.suffix && !intel_syntax) | |
6726 | i.suffix = BYTE_MNEM_SUFFIX; | |
29b0f896 AM |
6727 | } |
6728 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6729 | { | |
2eb952a4 | 6730 | if (intel_syntax |
3cd7f3e3 | 6731 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
6732 | && i.tm.opcode_modifier.no_bsuf) |
6733 | i.suffix = 0; | |
6734 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6735 | return 0; |
6736 | } | |
6737 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6738 | { | |
2eb952a4 | 6739 | if (intel_syntax |
3cd7f3e3 | 6740 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
6741 | && i.tm.opcode_modifier.no_lsuf |
6742 | && !i.tm.opcode_modifier.todword | |
6743 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6744 | i.suffix = 0; |
6745 | else if (!check_long_reg ()) | |
29b0f896 AM |
6746 | return 0; |
6747 | } | |
6748 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6749 | { | |
955e1e6a | 6750 | if (intel_syntax |
3cd7f3e3 | 6751 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
6752 | && i.tm.opcode_modifier.no_qsuf |
6753 | && !i.tm.opcode_modifier.todword | |
6754 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6755 | i.suffix = 0; |
6756 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6757 | return 0; |
6758 | } | |
6759 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6760 | { | |
2eb952a4 | 6761 | if (intel_syntax |
3cd7f3e3 | 6762 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
6763 | && i.tm.opcode_modifier.no_wsuf) |
6764 | i.suffix = 0; | |
6765 | else if (!check_word_reg ()) | |
29b0f896 AM |
6766 | return 0; |
6767 | } | |
3cd7f3e3 L |
6768 | else if (intel_syntax |
6769 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
6770 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6771 | ; | |
6772 | else | |
6773 | abort (); | |
65fca059 JB |
6774 | |
6775 | /* Undo the movsx/movzx change done above. */ | |
6776 | i.operands = numop; | |
29b0f896 | 6777 | } |
3cd7f3e3 L |
6778 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
6779 | && !i.suffix) | |
29b0f896 | 6780 | { |
13e600d0 JB |
6781 | i.suffix = stackop_size; |
6782 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
6783 | { |
6784 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
6785 | .code16gcc directive to support 16-bit mode with | |
6786 | 32-bit address. For IRET without a suffix, generate | |
6787 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
6788 | handler. */ | |
13e600d0 JB |
6789 | if (i.tm.base_opcode == 0xcf) |
6790 | { | |
6791 | i.suffix = WORD_MNEM_SUFFIX; | |
6792 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
6793 | } | |
6794 | /* Warn about changed behavior for segment register push/pop. */ | |
6795 | else if ((i.tm.base_opcode | 1) == 0x07) | |
6796 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
6797 | i.tm.name); | |
06f74c5c | 6798 | } |
29b0f896 | 6799 | } |
c006a730 | 6800 | else if (!i.suffix |
0cfa3eb3 JB |
6801 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
6802 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
6803 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
64e74474 AM |
6804 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6805 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6806 | { |
6807 | switch (flag_code) | |
6808 | { | |
6809 | case CODE_64BIT: | |
40fb9820 | 6810 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6811 | { |
6812 | i.suffix = QWORD_MNEM_SUFFIX; | |
6813 | break; | |
6814 | } | |
1a0670f3 | 6815 | /* Fall through. */ |
9306ca4a | 6816 | case CODE_32BIT: |
40fb9820 | 6817 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6818 | i.suffix = LONG_MNEM_SUFFIX; |
6819 | break; | |
6820 | case CODE_16BIT: | |
40fb9820 | 6821 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6822 | i.suffix = WORD_MNEM_SUFFIX; |
6823 | break; | |
6824 | } | |
6825 | } | |
252b5132 | 6826 | |
c006a730 | 6827 | if (!i.suffix |
3cd7f3e3 | 6828 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
6829 | /* Also cover lret/retf/iret in 64-bit mode. */ |
6830 | || (flag_code == CODE_64BIT | |
6831 | && !i.tm.opcode_modifier.no_lsuf | |
6832 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 6833 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
62b3f548 JB |
6834 | /* Accept FLDENV et al without suffix. */ |
6835 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 6836 | { |
6c0946d0 | 6837 | unsigned int suffixes, evex = 0; |
c006a730 JB |
6838 | |
6839 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
6840 | if (!i.tm.opcode_modifier.no_wsuf) | |
6841 | suffixes |= 1 << 1; | |
6842 | if (!i.tm.opcode_modifier.no_lsuf) | |
6843 | suffixes |= 1 << 2; | |
6844 | if (!i.tm.opcode_modifier.no_ldsuf) | |
6845 | suffixes |= 1 << 3; | |
6846 | if (!i.tm.opcode_modifier.no_ssuf) | |
6847 | suffixes |= 1 << 4; | |
6848 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
6849 | suffixes |= 1 << 5; | |
6850 | ||
6c0946d0 JB |
6851 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
6852 | also suitable for AT&T syntax mode, it was requested that this be | |
6853 | restricted to just Intel syntax. */ | |
b9915cbc | 6854 | if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast) |
6c0946d0 | 6855 | { |
b9915cbc | 6856 | unsigned int op; |
6c0946d0 | 6857 | |
b9915cbc | 6858 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 6859 | { |
b9915cbc JB |
6860 | if (is_evex_encoding (&i.tm) |
6861 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6c0946d0 | 6862 | { |
b9915cbc JB |
6863 | if (i.tm.operand_types[op].bitfield.ymmword) |
6864 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
6865 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6866 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
6867 | if (!i.tm.opcode_modifier.evex | |
6868 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
6869 | i.tm.opcode_modifier.evex = EVEX512; | |
6870 | } | |
6c0946d0 | 6871 | |
b9915cbc JB |
6872 | if (i.tm.operand_types[op].bitfield.xmmword |
6873 | + i.tm.operand_types[op].bitfield.ymmword | |
6874 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
6875 | continue; | |
6c0946d0 | 6876 | |
b9915cbc JB |
6877 | /* Any properly sized operand disambiguates the insn. */ |
6878 | if (i.types[op].bitfield.xmmword | |
6879 | || i.types[op].bitfield.ymmword | |
6880 | || i.types[op].bitfield.zmmword) | |
6881 | { | |
6882 | suffixes &= ~(7 << 6); | |
6883 | evex = 0; | |
6884 | break; | |
6885 | } | |
6c0946d0 | 6886 | |
b9915cbc JB |
6887 | if ((i.flags[op] & Operand_Mem) |
6888 | && i.tm.operand_types[op].bitfield.unspecified) | |
6889 | { | |
6890 | if (i.tm.operand_types[op].bitfield.xmmword) | |
6891 | suffixes |= 1 << 6; | |
6892 | if (i.tm.operand_types[op].bitfield.ymmword) | |
6893 | suffixes |= 1 << 7; | |
6894 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6895 | suffixes |= 1 << 8; | |
6896 | if (is_evex_encoding (&i.tm)) | |
6897 | evex = EVEX512; | |
6c0946d0 JB |
6898 | } |
6899 | } | |
6900 | } | |
6901 | ||
6902 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 6903 | if (suffixes & (suffixes - 1)) |
9306ca4a | 6904 | { |
873494c8 | 6905 | if (intel_syntax |
3cd7f3e3 | 6906 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 6907 | || operand_check == check_error)) |
9306ca4a | 6908 | { |
c006a730 | 6909 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
9306ca4a JB |
6910 | return 0; |
6911 | } | |
c006a730 | 6912 | if (operand_check == check_error) |
9306ca4a | 6913 | { |
c006a730 JB |
6914 | as_bad (_("no instruction mnemonic suffix given and " |
6915 | "no register operands; can't size `%s'"), i.tm.name); | |
9306ca4a JB |
6916 | return 0; |
6917 | } | |
c006a730 | 6918 | if (operand_check == check_warning) |
873494c8 JB |
6919 | as_warn (_("%s; using default for `%s'"), |
6920 | intel_syntax | |
6921 | ? _("ambiguous operand size") | |
6922 | : _("no instruction mnemonic suffix given and " | |
6923 | "no register operands"), | |
6924 | i.tm.name); | |
c006a730 JB |
6925 | |
6926 | if (i.tm.opcode_modifier.floatmf) | |
6927 | i.suffix = SHORT_MNEM_SUFFIX; | |
65fca059 JB |
6928 | else if ((i.tm.base_opcode | 8) == 0xfbe |
6929 | || (i.tm.base_opcode == 0x63 | |
6930 | && i.tm.cpu_flags.bitfield.cpu64)) | |
6931 | /* handled below */; | |
6c0946d0 JB |
6932 | else if (evex) |
6933 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
6934 | else if (flag_code == CODE_16BIT) |
6935 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 6936 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 6937 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
6938 | else |
6939 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 6940 | } |
29b0f896 | 6941 | } |
252b5132 | 6942 | |
65fca059 JB |
6943 | if ((i.tm.base_opcode | 8) == 0xfbe |
6944 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) | |
6945 | { | |
6946 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
6947 | In AT&T syntax, if there is no suffix (warned about above), the default | |
6948 | will be byte extension. */ | |
6949 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
6950 | i.tm.base_opcode |= 1; | |
6951 | ||
6952 | /* For further processing, the suffix should represent the destination | |
6953 | (register). This is already the case when one was used with | |
6954 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
6955 | no suffix to begin with. */ | |
6956 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
6957 | { | |
6958 | if (i.types[1].bitfield.word) | |
6959 | i.suffix = WORD_MNEM_SUFFIX; | |
6960 | else if (i.types[1].bitfield.qword) | |
6961 | i.suffix = QWORD_MNEM_SUFFIX; | |
6962 | else | |
6963 | i.suffix = LONG_MNEM_SUFFIX; | |
6964 | ||
6965 | i.tm.opcode_modifier.w = 0; | |
6966 | } | |
6967 | } | |
6968 | ||
50128d0c JB |
6969 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
6970 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
6971 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
6972 | ||
d2224064 JB |
6973 | /* Change the opcode based on the operand size given by i.suffix. */ |
6974 | switch (i.suffix) | |
29b0f896 | 6975 | { |
d2224064 JB |
6976 | /* Size floating point instruction. */ |
6977 | case LONG_MNEM_SUFFIX: | |
6978 | if (i.tm.opcode_modifier.floatmf) | |
6979 | { | |
6980 | i.tm.base_opcode ^= 4; | |
6981 | break; | |
6982 | } | |
6983 | /* fall through */ | |
6984 | case WORD_MNEM_SUFFIX: | |
6985 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6986 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6987 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6988 | { |
50128d0c | 6989 | if (i.short_form) |
29b0f896 AM |
6990 | i.tm.base_opcode |= 8; |
6991 | else | |
6992 | i.tm.base_opcode |= 1; | |
6993 | } | |
d2224064 JB |
6994 | /* fall through */ |
6995 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6996 | /* Now select between word & dword operations via the operand |
6997 | size prefix, except for instructions that will ignore this | |
6998 | prefix anyway. */ | |
c8f8eebc | 6999 | if (i.suffix != QWORD_MNEM_SUFFIX |
3cd7f3e3 | 7000 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc JB |
7001 | && !i.tm.opcode_modifier.floatmf |
7002 | && !is_any_vex_encoding (&i.tm) | |
7003 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
7004 | || (flag_code == CODE_64BIT | |
7005 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
7006 | { |
7007 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 7008 | |
0cfa3eb3 | 7009 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 7010 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 7011 | |
29b0f896 AM |
7012 | if (!add_prefix (prefix)) |
7013 | return 0; | |
24eab124 | 7014 | } |
252b5132 | 7015 | |
29b0f896 AM |
7016 | /* Set mode64 for an operand. */ |
7017 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 7018 | && flag_code == CODE_64BIT |
d2224064 | 7019 | && !i.tm.opcode_modifier.norex64 |
4ed21b58 | 7020 | && !i.tm.opcode_modifier.vexw |
46e883c5 | 7021 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
7022 | need rex64. */ |
7023 | && ! (i.operands == 2 | |
7024 | && i.tm.base_opcode == 0x90 | |
7025 | && i.tm.extension_opcode == None | |
75e5731b JB |
7026 | && i.types[0].bitfield.instance == Accum |
7027 | && i.types[0].bitfield.qword | |
7028 | && i.types[1].bitfield.instance == Accum | |
7029 | && i.types[1].bitfield.qword)) | |
d2224064 | 7030 | i.rex |= REX_W; |
3e73aa7c | 7031 | |
d2224064 | 7032 | break; |
29b0f896 | 7033 | } |
7ecd2f8b | 7034 | |
c8f8eebc | 7035 | if (i.tm.opcode_modifier.addrprefixopreg) |
c0a30a9f | 7036 | { |
c8f8eebc JB |
7037 | gas_assert (!i.suffix); |
7038 | gas_assert (i.reg_operands); | |
c0a30a9f | 7039 | |
c8f8eebc JB |
7040 | if (i.tm.operand_types[0].bitfield.instance == Accum |
7041 | || i.operands == 1) | |
7042 | { | |
7043 | /* The address size override prefix changes the size of the | |
7044 | first operand. */ | |
7045 | if (flag_code == CODE_64BIT | |
7046 | && i.op[0].regs->reg_type.bitfield.word) | |
7047 | { | |
7048 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
7049 | i.tm.name); | |
7050 | return 0; | |
7051 | } | |
7052 | ||
7053 | if ((flag_code == CODE_32BIT | |
7054 | ? i.op[0].regs->reg_type.bitfield.word | |
7055 | : i.op[0].regs->reg_type.bitfield.dword) | |
7056 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
7057 | return 0; | |
7058 | } | |
c0a30a9f L |
7059 | else |
7060 | { | |
c8f8eebc JB |
7061 | /* Check invalid register operand when the address size override |
7062 | prefix changes the size of register operands. */ | |
7063 | unsigned int op; | |
7064 | enum { need_word, need_dword, need_qword } need; | |
7065 | ||
7066 | if (flag_code == CODE_32BIT) | |
7067 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
7068 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
7069 | need = need_dword; |
7070 | else | |
7071 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 7072 | |
c8f8eebc JB |
7073 | for (op = 0; op < i.operands; op++) |
7074 | { | |
7075 | if (i.types[op].bitfield.class != Reg) | |
7076 | continue; | |
7077 | ||
7078 | switch (need) | |
7079 | { | |
7080 | case need_word: | |
7081 | if (i.op[op].regs->reg_type.bitfield.word) | |
7082 | continue; | |
7083 | break; | |
7084 | case need_dword: | |
7085 | if (i.op[op].regs->reg_type.bitfield.dword) | |
7086 | continue; | |
7087 | break; | |
7088 | case need_qword: | |
7089 | if (i.op[op].regs->reg_type.bitfield.qword) | |
7090 | continue; | |
7091 | break; | |
7092 | } | |
7093 | ||
7094 | as_bad (_("invalid register operand size for `%s'"), | |
7095 | i.tm.name); | |
7096 | return 0; | |
7097 | } | |
7098 | } | |
c0a30a9f L |
7099 | } |
7100 | ||
29b0f896 AM |
7101 | return 1; |
7102 | } | |
3e73aa7c | 7103 | |
29b0f896 | 7104 | static int |
543613e9 | 7105 | check_byte_reg (void) |
29b0f896 AM |
7106 | { |
7107 | int op; | |
543613e9 | 7108 | |
29b0f896 AM |
7109 | for (op = i.operands; --op >= 0;) |
7110 | { | |
dc821c5f | 7111 | /* Skip non-register operands. */ |
bab6aec1 | 7112 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
7113 | continue; |
7114 | ||
29b0f896 AM |
7115 | /* If this is an eight bit register, it's OK. If it's the 16 or |
7116 | 32 bit version of an eight bit register, we will just use the | |
7117 | low portion, and that's OK too. */ | |
dc821c5f | 7118 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
7119 | continue; |
7120 | ||
5a819eb9 | 7121 | /* I/O port address operands are OK too. */ |
75e5731b JB |
7122 | if (i.tm.operand_types[op].bitfield.instance == RegD |
7123 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
7124 | continue; |
7125 | ||
9706160a JB |
7126 | /* crc32 only wants its source operand checked here. */ |
7127 | if (i.tm.base_opcode == 0xf20f38f0 && op) | |
9344ff29 L |
7128 | continue; |
7129 | ||
29b0f896 | 7130 | /* Any other register is bad. */ |
bab6aec1 | 7131 | if (i.types[op].bitfield.class == Reg |
3528c362 JB |
7132 | || i.types[op].bitfield.class == RegMMX |
7133 | || i.types[op].bitfield.class == RegSIMD | |
00cee14f | 7134 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
7135 | || i.types[op].bitfield.class == RegCR |
7136 | || i.types[op].bitfield.class == RegDR | |
7137 | || i.types[op].bitfield.class == RegTR) | |
29b0f896 | 7138 | { |
a540244d L |
7139 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7140 | register_prefix, | |
29b0f896 AM |
7141 | i.op[op].regs->reg_name, |
7142 | i.tm.name, | |
7143 | i.suffix); | |
7144 | return 0; | |
7145 | } | |
7146 | } | |
7147 | return 1; | |
7148 | } | |
7149 | ||
7150 | static int | |
e3bb37b5 | 7151 | check_long_reg (void) |
29b0f896 AM |
7152 | { |
7153 | int op; | |
7154 | ||
7155 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7156 | /* Skip non-register operands. */ |
bab6aec1 | 7157 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7158 | continue; |
29b0f896 AM |
7159 | /* Reject eight bit registers, except where the template requires |
7160 | them. (eg. movzb) */ | |
dc821c5f | 7161 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7162 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7163 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7164 | && (i.tm.operand_types[op].bitfield.word |
7165 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7166 | { |
a540244d L |
7167 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7168 | register_prefix, | |
29b0f896 AM |
7169 | i.op[op].regs->reg_name, |
7170 | i.tm.name, | |
7171 | i.suffix); | |
7172 | return 0; | |
7173 | } | |
be4c5e58 L |
7174 | /* Error if the e prefix on a general reg is missing. */ |
7175 | else if (i.types[op].bitfield.word | |
bab6aec1 | 7176 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7177 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7178 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 7179 | { |
be4c5e58 L |
7180 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7181 | register_prefix, i.op[op].regs->reg_name, | |
7182 | i.suffix); | |
7183 | return 0; | |
252b5132 | 7184 | } |
e4630f71 | 7185 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 7186 | else if (i.types[op].bitfield.qword |
bab6aec1 | 7187 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7188 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7189 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 7190 | { |
34828aad | 7191 | if (intel_syntax |
65fca059 | 7192 | && i.tm.opcode_modifier.toqword |
3528c362 | 7193 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 7194 | { |
ca61edf2 | 7195 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
7196 | i.suffix = QWORD_MNEM_SUFFIX; |
7197 | } | |
7198 | else | |
7199 | { | |
2b5d6a91 | 7200 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
7201 | register_prefix, i.op[op].regs->reg_name, |
7202 | i.suffix); | |
7203 | return 0; | |
7204 | } | |
29b0f896 AM |
7205 | } |
7206 | return 1; | |
7207 | } | |
252b5132 | 7208 | |
29b0f896 | 7209 | static int |
e3bb37b5 | 7210 | check_qword_reg (void) |
29b0f896 AM |
7211 | { |
7212 | int op; | |
252b5132 | 7213 | |
29b0f896 | 7214 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 7215 | /* Skip non-register operands. */ |
bab6aec1 | 7216 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7217 | continue; |
29b0f896 AM |
7218 | /* Reject eight bit registers, except where the template requires |
7219 | them. (eg. movzb) */ | |
dc821c5f | 7220 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7221 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7222 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7223 | && (i.tm.operand_types[op].bitfield.word |
7224 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7225 | { |
a540244d L |
7226 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7227 | register_prefix, | |
29b0f896 AM |
7228 | i.op[op].regs->reg_name, |
7229 | i.tm.name, | |
7230 | i.suffix); | |
7231 | return 0; | |
7232 | } | |
e4630f71 | 7233 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
7234 | else if ((i.types[op].bitfield.word |
7235 | || i.types[op].bitfield.dword) | |
bab6aec1 | 7236 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7237 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7238 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
7239 | { |
7240 | /* Prohibit these changes in the 64bit mode, since the | |
7241 | lowering is more complicated. */ | |
34828aad | 7242 | if (intel_syntax |
ca61edf2 | 7243 | && i.tm.opcode_modifier.todword |
3528c362 | 7244 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 7245 | { |
ca61edf2 | 7246 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
7247 | i.suffix = LONG_MNEM_SUFFIX; |
7248 | } | |
7249 | else | |
7250 | { | |
2b5d6a91 | 7251 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
7252 | register_prefix, i.op[op].regs->reg_name, |
7253 | i.suffix); | |
7254 | return 0; | |
7255 | } | |
252b5132 | 7256 | } |
29b0f896 AM |
7257 | return 1; |
7258 | } | |
252b5132 | 7259 | |
29b0f896 | 7260 | static int |
e3bb37b5 | 7261 | check_word_reg (void) |
29b0f896 AM |
7262 | { |
7263 | int op; | |
7264 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7265 | /* Skip non-register operands. */ |
bab6aec1 | 7266 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7267 | continue; |
29b0f896 AM |
7268 | /* Reject eight bit registers, except where the template requires |
7269 | them. (eg. movzb) */ | |
dc821c5f | 7270 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7271 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7272 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7273 | && (i.tm.operand_types[op].bitfield.word |
7274 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7275 | { |
a540244d L |
7276 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7277 | register_prefix, | |
29b0f896 AM |
7278 | i.op[op].regs->reg_name, |
7279 | i.tm.name, | |
7280 | i.suffix); | |
7281 | return 0; | |
7282 | } | |
9706160a JB |
7283 | /* Error if the e or r prefix on a general reg is present. */ |
7284 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 7285 | || i.types[op].bitfield.qword) |
bab6aec1 | 7286 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7287 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7288 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 7289 | { |
9706160a JB |
7290 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7291 | register_prefix, i.op[op].regs->reg_name, | |
7292 | i.suffix); | |
7293 | return 0; | |
29b0f896 AM |
7294 | } |
7295 | return 1; | |
7296 | } | |
252b5132 | 7297 | |
29b0f896 | 7298 | static int |
40fb9820 | 7299 | update_imm (unsigned int j) |
29b0f896 | 7300 | { |
bc0844ae | 7301 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
7302 | if ((overlap.bitfield.imm8 |
7303 | || overlap.bitfield.imm8s | |
7304 | || overlap.bitfield.imm16 | |
7305 | || overlap.bitfield.imm32 | |
7306 | || overlap.bitfield.imm32s | |
7307 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
7308 | && !operand_type_equal (&overlap, &imm8) |
7309 | && !operand_type_equal (&overlap, &imm8s) | |
7310 | && !operand_type_equal (&overlap, &imm16) | |
7311 | && !operand_type_equal (&overlap, &imm32) | |
7312 | && !operand_type_equal (&overlap, &imm32s) | |
7313 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
7314 | { |
7315 | if (i.suffix) | |
7316 | { | |
40fb9820 L |
7317 | i386_operand_type temp; |
7318 | ||
0dfbf9d7 | 7319 | operand_type_set (&temp, 0); |
7ab9ffdd | 7320 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
7321 | { |
7322 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
7323 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
7324 | } | |
7325 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7326 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
7327 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7328 | { | |
7329 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
7330 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
7331 | } | |
7332 | else | |
7333 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
7334 | overlap = temp; | |
29b0f896 | 7335 | } |
0dfbf9d7 L |
7336 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
7337 | || operand_type_equal (&overlap, &imm16_32) | |
7338 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 7339 | { |
40fb9820 | 7340 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 7341 | overlap = imm16; |
40fb9820 | 7342 | else |
65da13b5 | 7343 | overlap = imm32s; |
29b0f896 | 7344 | } |
0dfbf9d7 L |
7345 | if (!operand_type_equal (&overlap, &imm8) |
7346 | && !operand_type_equal (&overlap, &imm8s) | |
7347 | && !operand_type_equal (&overlap, &imm16) | |
7348 | && !operand_type_equal (&overlap, &imm32) | |
7349 | && !operand_type_equal (&overlap, &imm32s) | |
7350 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 7351 | { |
4eed87de AM |
7352 | as_bad (_("no instruction mnemonic suffix given; " |
7353 | "can't determine immediate size")); | |
29b0f896 AM |
7354 | return 0; |
7355 | } | |
7356 | } | |
40fb9820 | 7357 | i.types[j] = overlap; |
29b0f896 | 7358 | |
40fb9820 L |
7359 | return 1; |
7360 | } | |
7361 | ||
7362 | static int | |
7363 | finalize_imm (void) | |
7364 | { | |
bc0844ae | 7365 | unsigned int j, n; |
29b0f896 | 7366 | |
bc0844ae L |
7367 | /* Update the first 2 immediate operands. */ |
7368 | n = i.operands > 2 ? 2 : i.operands; | |
7369 | if (n) | |
7370 | { | |
7371 | for (j = 0; j < n; j++) | |
7372 | if (update_imm (j) == 0) | |
7373 | return 0; | |
40fb9820 | 7374 | |
bc0844ae L |
7375 | /* The 3rd operand can't be immediate operand. */ |
7376 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
7377 | } | |
29b0f896 AM |
7378 | |
7379 | return 1; | |
7380 | } | |
7381 | ||
7382 | static int | |
e3bb37b5 | 7383 | process_operands (void) |
29b0f896 AM |
7384 | { |
7385 | /* Default segment register this instruction will use for memory | |
7386 | accesses. 0 means unknown. This is only for optimizing out | |
7387 | unnecessary segment overrides. */ | |
7388 | const seg_entry *default_seg = 0; | |
7389 | ||
2426c15f | 7390 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 7391 | { |
91d6fa6a NC |
7392 | unsigned int dupl = i.operands; |
7393 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
7394 | unsigned int j; |
7395 | ||
c0f3af97 | 7396 | /* The destination must be an xmm register. */ |
9c2799c2 | 7397 | gas_assert (i.reg_operands |
91d6fa6a | 7398 | && MAX_OPERANDS > dupl |
7ab9ffdd | 7399 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 7400 | |
75e5731b | 7401 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7402 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 7403 | { |
8cd7925b | 7404 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
7405 | { |
7406 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
7407 | sources. */ | |
75e5731b | 7408 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 7409 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
7410 | goto duplicate; |
7411 | } | |
e2ec9d29 | 7412 | else |
c0f3af97 L |
7413 | { |
7414 | /* We remove the first xmm0 and keep the number of | |
7415 | operands unchanged, which in fact duplicates the | |
7416 | destination. */ | |
7417 | for (j = 1; j < i.operands; j++) | |
7418 | { | |
7419 | i.op[j - 1] = i.op[j]; | |
7420 | i.types[j - 1] = i.types[j]; | |
7421 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 7422 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
7423 | } |
7424 | } | |
7425 | } | |
7426 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 7427 | { |
91d6fa6a | 7428 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
7429 | && (i.tm.opcode_modifier.vexsources |
7430 | == VEX3SOURCES)); | |
c0f3af97 L |
7431 | |
7432 | /* Add the implicit xmm0 for instructions with VEX prefix | |
7433 | and 3 sources. */ | |
7434 | for (j = i.operands; j > 0; j--) | |
7435 | { | |
7436 | i.op[j] = i.op[j - 1]; | |
7437 | i.types[j] = i.types[j - 1]; | |
7438 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 7439 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
7440 | } |
7441 | i.op[0].regs | |
7442 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 7443 | i.types[0] = regxmm; |
c0f3af97 L |
7444 | i.tm.operand_types[0] = regxmm; |
7445 | ||
7446 | i.operands += 2; | |
7447 | i.reg_operands += 2; | |
7448 | i.tm.operands += 2; | |
7449 | ||
91d6fa6a | 7450 | dupl++; |
c0f3af97 | 7451 | dest++; |
91d6fa6a NC |
7452 | i.op[dupl] = i.op[dest]; |
7453 | i.types[dupl] = i.types[dest]; | |
7454 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7455 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 7456 | } |
c0f3af97 L |
7457 | else |
7458 | { | |
dc1e8a47 | 7459 | duplicate: |
c0f3af97 L |
7460 | i.operands++; |
7461 | i.reg_operands++; | |
7462 | i.tm.operands++; | |
7463 | ||
91d6fa6a NC |
7464 | i.op[dupl] = i.op[dest]; |
7465 | i.types[dupl] = i.types[dest]; | |
7466 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7467 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
7468 | } |
7469 | ||
7470 | if (i.tm.opcode_modifier.immext) | |
7471 | process_immext (); | |
7472 | } | |
75e5731b | 7473 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7474 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
7475 | { |
7476 | unsigned int j; | |
7477 | ||
9fcfb3d7 L |
7478 | for (j = 1; j < i.operands; j++) |
7479 | { | |
7480 | i.op[j - 1] = i.op[j]; | |
7481 | i.types[j - 1] = i.types[j]; | |
7482 | ||
7483 | /* We need to adjust fields in i.tm since they are used by | |
7484 | build_modrm_byte. */ | |
7485 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
7486 | |
7487 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
7488 | } |
7489 | ||
e2ec9d29 L |
7490 | i.operands--; |
7491 | i.reg_operands--; | |
e2ec9d29 L |
7492 | i.tm.operands--; |
7493 | } | |
920d2ddc IT |
7494 | else if (i.tm.opcode_modifier.implicitquadgroup) |
7495 | { | |
a477a8c4 JB |
7496 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
7497 | ||
920d2ddc | 7498 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 7499 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
7500 | regnum = register_number (i.op[1].regs); |
7501 | first_reg_in_group = regnum & ~3; | |
7502 | last_reg_in_group = first_reg_in_group + 3; | |
7503 | if (regnum != first_reg_in_group) | |
7504 | as_warn (_("source register `%s%s' implicitly denotes" | |
7505 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7506 | register_prefix, i.op[1].regs->reg_name, | |
7507 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7508 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7509 | i.tm.name); | |
7510 | } | |
e2ec9d29 L |
7511 | else if (i.tm.opcode_modifier.regkludge) |
7512 | { | |
7513 | /* The imul $imm, %reg instruction is converted into | |
7514 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7515 | is converted into xor %reg, %reg. */ | |
7516 | ||
7517 | unsigned int first_reg_op; | |
7518 | ||
7519 | if (operand_type_check (i.types[0], reg)) | |
7520 | first_reg_op = 0; | |
7521 | else | |
7522 | first_reg_op = 1; | |
7523 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7524 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7525 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7526 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7527 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7528 | i.operands++; | |
7529 | i.reg_operands++; | |
29b0f896 AM |
7530 | } |
7531 | ||
85b80b0f | 7532 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7533 | { |
7534 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7535 | must be put into the modrm byte). Now, we make the modrm and |
7536 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7537 | |
7538 | default_seg = build_modrm_byte (); | |
7539 | } | |
00cee14f | 7540 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7541 | { |
7542 | if (flag_code != CODE_64BIT | |
7543 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7544 | && i.op[0].regs->reg_num == 1 | |
7545 | : (i.tm.base_opcode | 1) == POP_SEG386_SHORT | |
7546 | && i.op[0].regs->reg_num < 4) | |
7547 | { | |
7548 | as_bad (_("you can't `%s %s%s'"), | |
7549 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7550 | return 0; | |
7551 | } | |
7552 | if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 ) | |
7553 | { | |
7554 | i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; | |
7555 | i.tm.opcode_length = 2; | |
7556 | } | |
7557 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7558 | } | |
8a2ed489 | 7559 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
7560 | { |
7561 | default_seg = &ds; | |
7562 | } | |
40fb9820 | 7563 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7564 | { |
7565 | /* For the string instructions that allow a segment override | |
7566 | on one of their operands, the default segment is ds. */ | |
7567 | default_seg = &ds; | |
7568 | } | |
50128d0c | 7569 | else if (i.short_form) |
85b80b0f JB |
7570 | { |
7571 | /* The register or float register operand is in operand | |
7572 | 0 or 1. */ | |
bab6aec1 | 7573 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7574 | |
7575 | /* Register goes in low 3 bits of opcode. */ | |
7576 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7577 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7578 | i.rex |= REX_B; | |
7579 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7580 | { | |
7581 | /* Warn about some common errors, but press on regardless. | |
7582 | The first case can be generated by gcc (<= 2.8.1). */ | |
7583 | if (i.operands == 2) | |
7584 | { | |
7585 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7586 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7587 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7588 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7589 | } | |
7590 | else | |
7591 | { | |
7592 | /* Extraneous `l' suffix on fp insn. */ | |
7593 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7594 | register_prefix, i.op[0].regs->reg_name); | |
7595 | } | |
7596 | } | |
7597 | } | |
29b0f896 | 7598 | |
514a8bb0 | 7599 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
514a8bb0 JB |
7600 | && i.tm.base_opcode == 0x8d /* lea */ |
7601 | && !is_any_vex_encoding(&i.tm)) | |
92334ad2 JB |
7602 | { |
7603 | if (!quiet_warnings) | |
7604 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); | |
7605 | if (optimize) | |
7606 | { | |
7607 | i.seg[0] = NULL; | |
7608 | i.prefix[SEG_PREFIX] = 0; | |
7609 | } | |
7610 | } | |
52271982 AM |
7611 | |
7612 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
7613 | is neither the default nor the one already recorded from a prefix, |
7614 | use an opcode prefix to select it. If we never figured out what | |
7615 | the default segment is, then default_seg will be zero at this | |
7616 | point, and the specified segment prefix will always be used. */ | |
7617 | if (i.seg[0] | |
7618 | && i.seg[0] != default_seg | |
7619 | && i.seg[0]->seg_prefix != i.prefix[SEG_PREFIX]) | |
29b0f896 AM |
7620 | { |
7621 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
7622 | return 0; | |
7623 | } | |
7624 | return 1; | |
7625 | } | |
7626 | ||
7627 | static const seg_entry * | |
e3bb37b5 | 7628 | build_modrm_byte (void) |
29b0f896 AM |
7629 | { |
7630 | const seg_entry *default_seg = 0; | |
c0f3af97 | 7631 | unsigned int source, dest; |
8cd7925b | 7632 | int vex_3_sources; |
c0f3af97 | 7633 | |
8cd7925b | 7634 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
7635 | if (vex_3_sources) |
7636 | { | |
91d6fa6a | 7637 | unsigned int nds, reg_slot; |
4c2c6516 | 7638 | expressionS *exp; |
c0f3af97 | 7639 | |
6b8d3588 | 7640 | dest = i.operands - 1; |
c0f3af97 | 7641 | nds = dest - 1; |
922d8de8 | 7642 | |
a683cc34 | 7643 | /* There are 2 kinds of instructions: |
bed3d976 | 7644 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 7645 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 7646 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 7647 | ZMM register. |
bed3d976 | 7648 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7649 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7650 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7651 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7652 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 7653 | && i.tm.opcode_modifier.vexw |
3528c362 | 7654 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 7655 | |
48db9223 JB |
7656 | /* If VexW1 is set, the first non-immediate operand is the source and |
7657 | the second non-immediate one is encoded in the immediate operand. */ | |
7658 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7659 | { | |
7660 | source = i.imm_operands; | |
7661 | reg_slot = i.imm_operands + 1; | |
7662 | } | |
7663 | else | |
7664 | { | |
7665 | source = i.imm_operands + 1; | |
7666 | reg_slot = i.imm_operands; | |
7667 | } | |
7668 | ||
a683cc34 | 7669 | if (i.imm_operands == 0) |
bed3d976 JB |
7670 | { |
7671 | /* When there is no immediate operand, generate an 8bit | |
7672 | immediate operand to encode the first operand. */ | |
7673 | exp = &im_expressions[i.imm_operands++]; | |
7674 | i.op[i.operands].imms = exp; | |
7675 | i.types[i.operands] = imm8; | |
7676 | i.operands++; | |
7677 | ||
3528c362 | 7678 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
7679 | exp->X_op = O_constant; |
7680 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7681 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7682 | } | |
922d8de8 | 7683 | else |
bed3d976 | 7684 | { |
9d3bf266 JB |
7685 | gas_assert (i.imm_operands == 1); |
7686 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
7687 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 7688 | |
9d3bf266 JB |
7689 | /* Turn on Imm8 again so that output_imm will generate it. */ |
7690 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 7691 | |
3528c362 | 7692 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 7693 | i.op[0].imms->X_add_number |
bed3d976 | 7694 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 7695 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7696 | } |
a683cc34 | 7697 | |
3528c362 | 7698 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 7699 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7700 | } |
7701 | else | |
7702 | source = dest = 0; | |
29b0f896 AM |
7703 | |
7704 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7705 | implicit registers do not count. If there are 3 register |
7706 | operands, it must be a instruction with VexNDS. For a | |
7707 | instruction with VexNDD, the destination register is encoded | |
7708 | in VEX prefix. If there are 4 register operands, it must be | |
7709 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7710 | if (i.mem_operands == 0 |
7711 | && ((i.reg_operands == 2 | |
2426c15f | 7712 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7713 | || (i.reg_operands == 3 |
2426c15f | 7714 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7715 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7716 | { |
cab737b9 L |
7717 | switch (i.operands) |
7718 | { | |
7719 | case 2: | |
7720 | source = 0; | |
7721 | break; | |
7722 | case 3: | |
c81128dc L |
7723 | /* When there are 3 operands, one of them may be immediate, |
7724 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7725 | the first operand must be shift count register (cl) or it |
7726 | is an instruction with VexNDS. */ | |
9c2799c2 | 7727 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7728 | || (i.imm_operands == 0 |
2426c15f | 7729 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
7730 | || (i.types[0].bitfield.instance == RegC |
7731 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 7732 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
7733 | || (i.types[0].bitfield.instance == RegC |
7734 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
7735 | source = 1; |
7736 | else | |
7737 | source = 0; | |
cab737b9 L |
7738 | break; |
7739 | case 4: | |
368d64cc L |
7740 | /* When there are 4 operands, the first two must be 8bit |
7741 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7742 | one. |
7743 | ||
7744 | For instructions with VexNDS, if the first operand | |
7745 | an imm8, the source operand is the 2nd one. If the last | |
7746 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7747 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7748 | && i.types[0].bitfield.imm8 |
7749 | && i.types[1].bitfield.imm8) | |
2426c15f | 7750 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7751 | && i.imm_operands == 1 |
7752 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7753 | || i.types[i.operands - 1].bitfield.imm8 |
7754 | || i.rounding))); | |
9f2670f2 L |
7755 | if (i.imm_operands == 2) |
7756 | source = 2; | |
7757 | else | |
c0f3af97 L |
7758 | { |
7759 | if (i.types[0].bitfield.imm8) | |
7760 | source = 1; | |
7761 | else | |
7762 | source = 0; | |
7763 | } | |
c0f3af97 L |
7764 | break; |
7765 | case 5: | |
e771e7c9 | 7766 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7767 | { |
7768 | /* For EVEX instructions, when there are 5 operands, the | |
7769 | first one must be immediate operand. If the second one | |
7770 | is immediate operand, the source operand is the 3th | |
7771 | one. If the last one is immediate operand, the source | |
7772 | operand is the 2nd one. */ | |
7773 | gas_assert (i.imm_operands == 2 | |
7774 | && i.tm.opcode_modifier.sae | |
7775 | && operand_type_check (i.types[0], imm)); | |
7776 | if (operand_type_check (i.types[1], imm)) | |
7777 | source = 2; | |
7778 | else if (operand_type_check (i.types[4], imm)) | |
7779 | source = 1; | |
7780 | else | |
7781 | abort (); | |
7782 | } | |
cab737b9 L |
7783 | break; |
7784 | default: | |
7785 | abort (); | |
7786 | } | |
7787 | ||
c0f3af97 L |
7788 | if (!vex_3_sources) |
7789 | { | |
7790 | dest = source + 1; | |
7791 | ||
43234a1e L |
7792 | /* RC/SAE operand could be between DEST and SRC. That happens |
7793 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7794 | register. */ | |
7795 | if (i.rounding && i.rounding->operand == (int) dest) | |
7796 | dest++; | |
7797 | ||
2426c15f | 7798 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7799 | { |
43234a1e | 7800 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7801 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 7802 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
7803 | |
7804 | i386_operand_type op; | |
7805 | unsigned int vvvv; | |
7806 | ||
7807 | /* Check register-only source operand when two source | |
7808 | operands are swapped. */ | |
7809 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7810 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7811 | { | |
7812 | vvvv = source; | |
7813 | source = dest; | |
7814 | } | |
7815 | else | |
7816 | vvvv = dest; | |
7817 | ||
7818 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 7819 | if ((dest + 1) >= i.operands |
bab6aec1 | 7820 | || ((op.bitfield.class != Reg |
dc821c5f | 7821 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 7822 | && op.bitfield.class != RegSIMD |
43234a1e | 7823 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7824 | abort (); |
f12dc422 | 7825 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7826 | dest++; |
7827 | } | |
7828 | } | |
29b0f896 AM |
7829 | |
7830 | i.rm.mode = 3; | |
dfd69174 JB |
7831 | /* One of the register operands will be encoded in the i.rm.reg |
7832 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
7833 | fields. If no form of this instruction supports a memory |
7834 | destination operand, then we assume the source operand may | |
7835 | sometimes be a memory operand and so we need to store the | |
7836 | destination in the i.rm.reg field. */ | |
dfd69174 | 7837 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 7838 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
7839 | { |
7840 | i.rm.reg = i.op[dest].regs->reg_num; | |
7841 | i.rm.regmem = i.op[source].regs->reg_num; | |
3528c362 JB |
7842 | if (i.op[dest].regs->reg_type.bitfield.class == RegMMX |
7843 | || i.op[source].regs->reg_type.bitfield.class == RegMMX) | |
b4a3a7b4 | 7844 | i.has_regmmx = TRUE; |
3528c362 JB |
7845 | else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD |
7846 | || i.op[source].regs->reg_type.bitfield.class == RegSIMD) | |
b4a3a7b4 L |
7847 | { |
7848 | if (i.types[dest].bitfield.zmmword | |
7849 | || i.types[source].bitfield.zmmword) | |
7850 | i.has_regzmm = TRUE; | |
7851 | else if (i.types[dest].bitfield.ymmword | |
7852 | || i.types[source].bitfield.ymmword) | |
7853 | i.has_regymm = TRUE; | |
7854 | else | |
7855 | i.has_regxmm = TRUE; | |
7856 | } | |
29b0f896 | 7857 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7858 | i.rex |= REX_R; |
43234a1e L |
7859 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7860 | i.vrex |= REX_R; | |
29b0f896 | 7861 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7862 | i.rex |= REX_B; |
43234a1e L |
7863 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7864 | i.vrex |= REX_B; | |
29b0f896 AM |
7865 | } |
7866 | else | |
7867 | { | |
7868 | i.rm.reg = i.op[source].regs->reg_num; | |
7869 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7870 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7871 | i.rex |= REX_B; |
43234a1e L |
7872 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7873 | i.vrex |= REX_B; | |
29b0f896 | 7874 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7875 | i.rex |= REX_R; |
43234a1e L |
7876 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7877 | i.vrex |= REX_R; | |
29b0f896 | 7878 | } |
e0c7f900 | 7879 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7880 | { |
4a5c67ed | 7881 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 7882 | abort (); |
e0c7f900 | 7883 | i.rex &= ~REX_R; |
c4a530c5 JB |
7884 | add_prefix (LOCK_PREFIX_OPCODE); |
7885 | } | |
29b0f896 AM |
7886 | } |
7887 | else | |
7888 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7889 | unsigned int mem; |
7890 | ||
29b0f896 AM |
7891 | if (i.mem_operands) |
7892 | { | |
7893 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7894 | unsigned int op; |
4eed87de | 7895 | |
7ab9ffdd | 7896 | for (op = 0; op < i.operands; op++) |
8dc0818e | 7897 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 7898 | break; |
7ab9ffdd | 7899 | gas_assert (op < i.operands); |
29b0f896 | 7900 | |
6c30d220 L |
7901 | if (i.tm.opcode_modifier.vecsib) |
7902 | { | |
e968fc9b | 7903 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7904 | abort (); |
7905 | ||
7906 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7907 | if (!i.base_reg) | |
7908 | { | |
7909 | i.sib.base = NO_BASE_REGISTER; | |
7910 | i.sib.scale = i.log2_scale_factor; | |
7911 | i.types[op].bitfield.disp8 = 0; | |
7912 | i.types[op].bitfield.disp16 = 0; | |
7913 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7914 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7915 | { |
7916 | /* Must be 32 bit */ | |
7917 | i.types[op].bitfield.disp32 = 1; | |
7918 | i.types[op].bitfield.disp32s = 0; | |
7919 | } | |
7920 | else | |
7921 | { | |
7922 | i.types[op].bitfield.disp32 = 0; | |
7923 | i.types[op].bitfield.disp32s = 1; | |
7924 | } | |
7925 | } | |
7926 | i.sib.index = i.index_reg->reg_num; | |
7927 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7928 | i.rex |= REX_X; | |
43234a1e L |
7929 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7930 | i.vrex |= REX_X; | |
6c30d220 L |
7931 | } |
7932 | ||
29b0f896 AM |
7933 | default_seg = &ds; |
7934 | ||
7935 | if (i.base_reg == 0) | |
7936 | { | |
7937 | i.rm.mode = 0; | |
7938 | if (!i.disp_operands) | |
9bb129e8 | 7939 | fake_zero_displacement = 1; |
29b0f896 AM |
7940 | if (i.index_reg == 0) |
7941 | { | |
73053c1f JB |
7942 | i386_operand_type newdisp; |
7943 | ||
6c30d220 | 7944 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7945 | /* Operand is just <disp> */ |
20f0a1fc | 7946 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7947 | { |
7948 | /* 64bit mode overwrites the 32bit absolute | |
7949 | addressing by RIP relative addressing and | |
7950 | absolute addressing is encoded by one of the | |
7951 | redundant SIB forms. */ | |
7952 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7953 | i.sib.base = NO_BASE_REGISTER; | |
7954 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7955 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7956 | } |
fc225355 L |
7957 | else if ((flag_code == CODE_16BIT) |
7958 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7959 | { |
7960 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7961 | newdisp = disp16; |
20f0a1fc NC |
7962 | } |
7963 | else | |
7964 | { | |
7965 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7966 | newdisp = disp32; |
29b0f896 | 7967 | } |
73053c1f JB |
7968 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7969 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7970 | } |
6c30d220 | 7971 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7972 | { |
6c30d220 | 7973 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7974 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7975 | i.sib.index = NO_INDEX_REGISTER; |
7976 | else | |
7977 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7978 | i.sib.base = NO_BASE_REGISTER; |
7979 | i.sib.scale = i.log2_scale_factor; | |
7980 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7981 | i.types[op].bitfield.disp8 = 0; |
7982 | i.types[op].bitfield.disp16 = 0; | |
7983 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7984 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7985 | { |
7986 | /* Must be 32 bit */ | |
7987 | i.types[op].bitfield.disp32 = 1; | |
7988 | i.types[op].bitfield.disp32s = 0; | |
7989 | } | |
29b0f896 | 7990 | else |
40fb9820 L |
7991 | { |
7992 | i.types[op].bitfield.disp32 = 0; | |
7993 | i.types[op].bitfield.disp32s = 1; | |
7994 | } | |
29b0f896 | 7995 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7996 | i.rex |= REX_X; |
29b0f896 AM |
7997 | } |
7998 | } | |
7999 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 8000 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 8001 | { |
6c30d220 | 8002 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 8003 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
8004 | i.types[op].bitfield.disp8 = 0; |
8005 | i.types[op].bitfield.disp16 = 0; | |
8006 | i.types[op].bitfield.disp32 = 0; | |
8007 | i.types[op].bitfield.disp32s = 1; | |
8008 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 8009 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
8010 | if (! i.disp_operands) |
8011 | fake_zero_displacement = 1; | |
29b0f896 | 8012 | } |
dc821c5f | 8013 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 8014 | { |
6c30d220 | 8015 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
8016 | switch (i.base_reg->reg_num) |
8017 | { | |
8018 | case 3: /* (%bx) */ | |
8019 | if (i.index_reg == 0) | |
8020 | i.rm.regmem = 7; | |
8021 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
8022 | i.rm.regmem = i.index_reg->reg_num - 6; | |
8023 | break; | |
8024 | case 5: /* (%bp) */ | |
8025 | default_seg = &ss; | |
8026 | if (i.index_reg == 0) | |
8027 | { | |
8028 | i.rm.regmem = 6; | |
40fb9820 | 8029 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
8030 | { |
8031 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 8032 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 8033 | fake_zero_displacement = 1; |
29b0f896 AM |
8034 | } |
8035 | } | |
8036 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
8037 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
8038 | break; | |
8039 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
8040 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
8041 | } | |
8042 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
8043 | } | |
8044 | else /* i.base_reg and 32/64 bit mode */ | |
8045 | { | |
8046 | if (flag_code == CODE_64BIT | |
40fb9820 L |
8047 | && operand_type_check (i.types[op], disp)) |
8048 | { | |
73053c1f JB |
8049 | i.types[op].bitfield.disp16 = 0; |
8050 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 8051 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
8052 | { |
8053 | i.types[op].bitfield.disp32 = 0; | |
8054 | i.types[op].bitfield.disp32s = 1; | |
8055 | } | |
40fb9820 | 8056 | else |
73053c1f JB |
8057 | { |
8058 | i.types[op].bitfield.disp32 = 1; | |
8059 | i.types[op].bitfield.disp32s = 0; | |
8060 | } | |
40fb9820 | 8061 | } |
20f0a1fc | 8062 | |
6c30d220 L |
8063 | if (!i.tm.opcode_modifier.vecsib) |
8064 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 8065 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8066 | i.rex |= REX_B; |
29b0f896 AM |
8067 | i.sib.base = i.base_reg->reg_num; |
8068 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
8069 | complications. */ | |
848930b2 JB |
8070 | if (!(i.base_reg->reg_flags & RegRex) |
8071 | && (i.base_reg->reg_num == EBP_REG_NUM | |
8072 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 8073 | default_seg = &ss; |
848930b2 | 8074 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 8075 | { |
848930b2 | 8076 | fake_zero_displacement = 1; |
b5014f7a | 8077 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
8078 | } |
8079 | i.sib.scale = i.log2_scale_factor; | |
8080 | if (i.index_reg == 0) | |
8081 | { | |
6c30d220 | 8082 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
8083 | /* <disp>(%esp) becomes two byte modrm with no index |
8084 | register. We've already stored the code for esp | |
8085 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
8086 | Any base register besides %esp will not use the | |
8087 | extra modrm byte. */ | |
8088 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 8089 | } |
6c30d220 | 8090 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 8091 | { |
e968fc9b | 8092 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8093 | i.sib.index = NO_INDEX_REGISTER; |
8094 | else | |
8095 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8096 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
8097 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 8098 | i.rex |= REX_X; |
29b0f896 | 8099 | } |
67a4f2b7 AO |
8100 | |
8101 | if (i.disp_operands | |
8102 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
8103 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
8104 | i.rm.mode = 0; | |
8105 | else | |
a501d77e L |
8106 | { |
8107 | if (!fake_zero_displacement | |
8108 | && !i.disp_operands | |
8109 | && i.disp_encoding) | |
8110 | { | |
8111 | fake_zero_displacement = 1; | |
8112 | if (i.disp_encoding == disp_encoding_8bit) | |
8113 | i.types[op].bitfield.disp8 = 1; | |
8114 | else | |
8115 | i.types[op].bitfield.disp32 = 1; | |
8116 | } | |
8117 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
8118 | } | |
29b0f896 | 8119 | } |
252b5132 | 8120 | |
29b0f896 AM |
8121 | if (fake_zero_displacement) |
8122 | { | |
8123 | /* Fakes a zero displacement assuming that i.types[op] | |
8124 | holds the correct displacement size. */ | |
8125 | expressionS *exp; | |
8126 | ||
9c2799c2 | 8127 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
8128 | exp = &disp_expressions[i.disp_operands++]; |
8129 | i.op[op].disps = exp; | |
8130 | exp->X_op = O_constant; | |
8131 | exp->X_add_number = 0; | |
8132 | exp->X_add_symbol = (symbolS *) 0; | |
8133 | exp->X_op_symbol = (symbolS *) 0; | |
8134 | } | |
c0f3af97 L |
8135 | |
8136 | mem = op; | |
29b0f896 | 8137 | } |
c0f3af97 L |
8138 | else |
8139 | mem = ~0; | |
252b5132 | 8140 | |
8c43a48b | 8141 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
8142 | { |
8143 | if (operand_type_check (i.types[0], imm)) | |
8144 | i.vex.register_specifier = NULL; | |
8145 | else | |
8146 | { | |
8147 | /* VEX.vvvv encodes one of the sources when the first | |
8148 | operand is not an immediate. */ | |
1ef99a7b | 8149 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
8150 | i.vex.register_specifier = i.op[0].regs; |
8151 | else | |
8152 | i.vex.register_specifier = i.op[1].regs; | |
8153 | } | |
8154 | ||
8155 | /* Destination is a XMM register encoded in the ModRM.reg | |
8156 | and VEX.R bit. */ | |
8157 | i.rm.reg = i.op[2].regs->reg_num; | |
8158 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
8159 | i.rex |= REX_R; | |
8160 | ||
8161 | /* ModRM.rm and VEX.B encodes the other source. */ | |
8162 | if (!i.mem_operands) | |
8163 | { | |
8164 | i.rm.mode = 3; | |
8165 | ||
1ef99a7b | 8166 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
8167 | i.rm.regmem = i.op[1].regs->reg_num; |
8168 | else | |
8169 | i.rm.regmem = i.op[0].regs->reg_num; | |
8170 | ||
8171 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8172 | i.rex |= REX_B; | |
8173 | } | |
8174 | } | |
2426c15f | 8175 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
8176 | { |
8177 | i.vex.register_specifier = i.op[2].regs; | |
8178 | if (!i.mem_operands) | |
8179 | { | |
8180 | i.rm.mode = 3; | |
8181 | i.rm.regmem = i.op[1].regs->reg_num; | |
8182 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8183 | i.rex |= REX_B; | |
8184 | } | |
8185 | } | |
29b0f896 AM |
8186 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
8187 | (if any) based on i.tm.extension_opcode. Again, we must be | |
8188 | careful to make sure that segment/control/debug/test/MMX | |
8189 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 8190 | else if (i.reg_operands) |
29b0f896 | 8191 | { |
99018f42 | 8192 | unsigned int op; |
7ab9ffdd L |
8193 | unsigned int vex_reg = ~0; |
8194 | ||
8195 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 | 8196 | { |
bab6aec1 | 8197 | if (i.types[op].bitfield.class == Reg |
f74a6307 JB |
8198 | || i.types[op].bitfield.class == RegBND |
8199 | || i.types[op].bitfield.class == RegMask | |
00cee14f | 8200 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
8201 | || i.types[op].bitfield.class == RegCR |
8202 | || i.types[op].bitfield.class == RegDR | |
8203 | || i.types[op].bitfield.class == RegTR) | |
b4a3a7b4 | 8204 | break; |
3528c362 | 8205 | if (i.types[op].bitfield.class == RegSIMD) |
b4a3a7b4 L |
8206 | { |
8207 | if (i.types[op].bitfield.zmmword) | |
8208 | i.has_regzmm = TRUE; | |
8209 | else if (i.types[op].bitfield.ymmword) | |
8210 | i.has_regymm = TRUE; | |
8211 | else | |
8212 | i.has_regxmm = TRUE; | |
8213 | break; | |
8214 | } | |
3528c362 | 8215 | if (i.types[op].bitfield.class == RegMMX) |
b4a3a7b4 L |
8216 | { |
8217 | i.has_regmmx = TRUE; | |
8218 | break; | |
8219 | } | |
8220 | } | |
c0209578 | 8221 | |
7ab9ffdd L |
8222 | if (vex_3_sources) |
8223 | op = dest; | |
2426c15f | 8224 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
8225 | { |
8226 | /* For instructions with VexNDS, the register-only | |
8227 | source operand is encoded in VEX prefix. */ | |
8228 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 8229 | |
7ab9ffdd | 8230 | if (op > mem) |
c0f3af97 | 8231 | { |
7ab9ffdd L |
8232 | vex_reg = op++; |
8233 | gas_assert (op < i.operands); | |
c0f3af97 L |
8234 | } |
8235 | else | |
c0f3af97 | 8236 | { |
f12dc422 L |
8237 | /* Check register-only source operand when two source |
8238 | operands are swapped. */ | |
8239 | if (!i.tm.operand_types[op].bitfield.baseindex | |
8240 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
8241 | { | |
8242 | vex_reg = op; | |
8243 | op += 2; | |
8244 | gas_assert (mem == (vex_reg + 1) | |
8245 | && op < i.operands); | |
8246 | } | |
8247 | else | |
8248 | { | |
8249 | vex_reg = op + 1; | |
8250 | gas_assert (vex_reg < i.operands); | |
8251 | } | |
c0f3af97 | 8252 | } |
7ab9ffdd | 8253 | } |
2426c15f | 8254 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 8255 | { |
f12dc422 | 8256 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 8257 | is encoded in VEX prefix. */ |
f12dc422 L |
8258 | if (i.mem_operands == 0) |
8259 | { | |
8260 | /* There is no memory operand. */ | |
8261 | gas_assert ((op + 2) == i.operands); | |
8262 | vex_reg = op + 1; | |
8263 | } | |
8264 | else | |
8d63c93e | 8265 | { |
ed438a93 JB |
8266 | /* There are only 2 non-immediate operands. */ |
8267 | gas_assert (op < i.imm_operands + 2 | |
8268 | && i.operands == i.imm_operands + 2); | |
8269 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 8270 | } |
7ab9ffdd L |
8271 | } |
8272 | else | |
8273 | gas_assert (op < i.operands); | |
99018f42 | 8274 | |
7ab9ffdd L |
8275 | if (vex_reg != (unsigned int) ~0) |
8276 | { | |
f12dc422 | 8277 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 8278 | |
bab6aec1 | 8279 | if ((type->bitfield.class != Reg |
dc821c5f | 8280 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 8281 | && type->bitfield.class != RegSIMD |
43234a1e | 8282 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 8283 | abort (); |
f88c9eb0 | 8284 | |
7ab9ffdd L |
8285 | i.vex.register_specifier = i.op[vex_reg].regs; |
8286 | } | |
8287 | ||
1b9f0c97 L |
8288 | /* Don't set OP operand twice. */ |
8289 | if (vex_reg != op) | |
7ab9ffdd | 8290 | { |
1b9f0c97 L |
8291 | /* If there is an extension opcode to put here, the |
8292 | register number must be put into the regmem field. */ | |
8293 | if (i.tm.extension_opcode != None) | |
8294 | { | |
8295 | i.rm.regmem = i.op[op].regs->reg_num; | |
8296 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
8297 | i.rex |= REX_B; | |
43234a1e L |
8298 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
8299 | i.vrex |= REX_B; | |
1b9f0c97 L |
8300 | } |
8301 | else | |
8302 | { | |
8303 | i.rm.reg = i.op[op].regs->reg_num; | |
8304 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
8305 | i.rex |= REX_R; | |
43234a1e L |
8306 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
8307 | i.vrex |= REX_R; | |
1b9f0c97 | 8308 | } |
7ab9ffdd | 8309 | } |
252b5132 | 8310 | |
29b0f896 AM |
8311 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
8312 | must set it to 3 to indicate this is a register operand | |
8313 | in the regmem field. */ | |
8314 | if (!i.mem_operands) | |
8315 | i.rm.mode = 3; | |
8316 | } | |
252b5132 | 8317 | |
29b0f896 | 8318 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 8319 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
8320 | i.rm.reg = i.tm.extension_opcode; |
8321 | } | |
8322 | return default_seg; | |
8323 | } | |
252b5132 | 8324 | |
376cd056 JB |
8325 | static unsigned int |
8326 | flip_code16 (unsigned int code16) | |
8327 | { | |
8328 | gas_assert (i.tm.operands == 1); | |
8329 | ||
8330 | return !(i.prefix[REX_PREFIX] & REX_W) | |
8331 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
8332 | || i.tm.operand_types[0].bitfield.disp32s | |
8333 | : i.tm.operand_types[0].bitfield.disp16) | |
8334 | ? CODE16 : 0; | |
8335 | } | |
8336 | ||
29b0f896 | 8337 | static void |
e3bb37b5 | 8338 | output_branch (void) |
29b0f896 AM |
8339 | { |
8340 | char *p; | |
f8a5c266 | 8341 | int size; |
29b0f896 AM |
8342 | int code16; |
8343 | int prefix; | |
8344 | relax_substateT subtype; | |
8345 | symbolS *sym; | |
8346 | offsetT off; | |
8347 | ||
f8a5c266 | 8348 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 8349 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
8350 | |
8351 | prefix = 0; | |
8352 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 8353 | { |
29b0f896 AM |
8354 | prefix = 1; |
8355 | i.prefixes -= 1; | |
376cd056 | 8356 | code16 ^= flip_code16(code16); |
252b5132 | 8357 | } |
29b0f896 AM |
8358 | /* Pentium4 branch hints. */ |
8359 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8360 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 8361 | { |
29b0f896 AM |
8362 | prefix++; |
8363 | i.prefixes--; | |
8364 | } | |
8365 | if (i.prefix[REX_PREFIX] != 0) | |
8366 | { | |
8367 | prefix++; | |
8368 | i.prefixes--; | |
2f66722d AM |
8369 | } |
8370 | ||
7e8b059b L |
8371 | /* BND prefixed jump. */ |
8372 | if (i.prefix[BND_PREFIX] != 0) | |
8373 | { | |
6cb0a70e JB |
8374 | prefix++; |
8375 | i.prefixes--; | |
7e8b059b L |
8376 | } |
8377 | ||
f2810fe0 JB |
8378 | if (i.prefixes != 0) |
8379 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
29b0f896 AM |
8380 | |
8381 | /* It's always a symbol; End frag & setup for relax. | |
8382 | Make sure there is enough room in this frag for the largest | |
8383 | instruction we may generate in md_convert_frag. This is 2 | |
8384 | bytes for the opcode and room for the prefix and largest | |
8385 | displacement. */ | |
8386 | frag_grow (prefix + 2 + 4); | |
8387 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
8388 | p = frag_more (prefix + 1); | |
8389 | if (i.prefix[DATA_PREFIX] != 0) | |
8390 | *p++ = DATA_PREFIX_OPCODE; | |
8391 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
8392 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
8393 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
8394 | if (i.prefix[BND_PREFIX] != 0) |
8395 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
8396 | if (i.prefix[REX_PREFIX] != 0) |
8397 | *p++ = i.prefix[REX_PREFIX]; | |
8398 | *p = i.tm.base_opcode; | |
8399 | ||
8400 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 8401 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 8402 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 8403 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 8404 | else |
f8a5c266 | 8405 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 8406 | subtype |= code16; |
3e73aa7c | 8407 | |
29b0f896 AM |
8408 | sym = i.op[0].disps->X_add_symbol; |
8409 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 8410 | |
29b0f896 AM |
8411 | if (i.op[0].disps->X_op != O_constant |
8412 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 8413 | { |
29b0f896 AM |
8414 | /* Handle complex expressions. */ |
8415 | sym = make_expr_symbol (i.op[0].disps); | |
8416 | off = 0; | |
8417 | } | |
3e73aa7c | 8418 | |
29b0f896 AM |
8419 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
8420 | Pass reloc in fr_var. */ | |
d258b828 | 8421 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 8422 | } |
3e73aa7c | 8423 | |
bd7ab16b L |
8424 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8425 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
8426 | symbol S. */ | |
8427 | ||
8428 | static bfd_boolean | |
8429 | need_plt32_p (symbolS *s) | |
8430 | { | |
8431 | /* PLT32 relocation is ELF only. */ | |
8432 | if (!IS_ELF) | |
8433 | return FALSE; | |
8434 | ||
a5def729 RO |
8435 | #ifdef TE_SOLARIS |
8436 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
8437 | krtld support it. */ | |
8438 | return FALSE; | |
8439 | #endif | |
8440 | ||
bd7ab16b L |
8441 | /* Since there is no need to prepare for PLT branch on x86-64, we |
8442 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
8443 | be used as a marker for 32-bit PC-relative branches. */ | |
8444 | if (!object_64bit) | |
8445 | return FALSE; | |
8446 | ||
8447 | /* Weak or undefined symbol need PLT32 relocation. */ | |
8448 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
8449 | return TRUE; | |
8450 | ||
8451 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
8452 | if (! S_IS_EXTERNAL (s)) | |
8453 | return FALSE; | |
8454 | ||
8455 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
8456 | non-default visibilities are treated as normal global symbol | |
8457 | so that PLT32 relocation can be used as a marker for 32-bit | |
8458 | PC-relative branches. It is useful for linker relaxation. */ | |
8459 | return TRUE; | |
8460 | } | |
8461 | #endif | |
8462 | ||
29b0f896 | 8463 | static void |
e3bb37b5 | 8464 | output_jump (void) |
29b0f896 AM |
8465 | { |
8466 | char *p; | |
8467 | int size; | |
3e02c1cc | 8468 | fixS *fixP; |
bd7ab16b | 8469 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 8470 | |
0cfa3eb3 | 8471 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
8472 | { |
8473 | /* This is a loop or jecxz type instruction. */ | |
8474 | size = 1; | |
8475 | if (i.prefix[ADDR_PREFIX] != 0) | |
8476 | { | |
8477 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
8478 | i.prefixes -= 1; | |
8479 | } | |
8480 | /* Pentium4 branch hints. */ | |
8481 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8482 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
8483 | { | |
8484 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
8485 | i.prefixes--; | |
3e73aa7c JH |
8486 | } |
8487 | } | |
29b0f896 AM |
8488 | else |
8489 | { | |
8490 | int code16; | |
3e73aa7c | 8491 | |
29b0f896 AM |
8492 | code16 = 0; |
8493 | if (flag_code == CODE_16BIT) | |
8494 | code16 = CODE16; | |
3e73aa7c | 8495 | |
29b0f896 AM |
8496 | if (i.prefix[DATA_PREFIX] != 0) |
8497 | { | |
8498 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
8499 | i.prefixes -= 1; | |
376cd056 | 8500 | code16 ^= flip_code16(code16); |
29b0f896 | 8501 | } |
252b5132 | 8502 | |
29b0f896 AM |
8503 | size = 4; |
8504 | if (code16) | |
8505 | size = 2; | |
8506 | } | |
9fcc94b6 | 8507 | |
6cb0a70e JB |
8508 | /* BND prefixed jump. */ |
8509 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 8510 | { |
6cb0a70e | 8511 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); |
29b0f896 AM |
8512 | i.prefixes -= 1; |
8513 | } | |
252b5132 | 8514 | |
6cb0a70e | 8515 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 8516 | { |
6cb0a70e | 8517 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); |
7e8b059b L |
8518 | i.prefixes -= 1; |
8519 | } | |
8520 | ||
f2810fe0 JB |
8521 | if (i.prefixes != 0) |
8522 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
e0890092 | 8523 | |
42164a71 L |
8524 | p = frag_more (i.tm.opcode_length + size); |
8525 | switch (i.tm.opcode_length) | |
8526 | { | |
8527 | case 2: | |
8528 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8529 | /* Fall through. */ |
42164a71 L |
8530 | case 1: |
8531 | *p++ = i.tm.base_opcode; | |
8532 | break; | |
8533 | default: | |
8534 | abort (); | |
8535 | } | |
e0890092 | 8536 | |
bd7ab16b L |
8537 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8538 | if (size == 4 | |
8539 | && jump_reloc == NO_RELOC | |
8540 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
8541 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8542 | #endif | |
8543 | ||
8544 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8545 | ||
3e02c1cc | 8546 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8547 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
8548 | |
8549 | /* All jumps handled here are signed, but don't use a signed limit | |
8550 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
8551 | 4G and 64k respectively. */ | |
8552 | if (size == 1) | |
8553 | fixP->fx_signed = 1; | |
29b0f896 | 8554 | } |
e0890092 | 8555 | |
29b0f896 | 8556 | static void |
e3bb37b5 | 8557 | output_interseg_jump (void) |
29b0f896 AM |
8558 | { |
8559 | char *p; | |
8560 | int size; | |
8561 | int prefix; | |
8562 | int code16; | |
252b5132 | 8563 | |
29b0f896 AM |
8564 | code16 = 0; |
8565 | if (flag_code == CODE_16BIT) | |
8566 | code16 = CODE16; | |
a217f122 | 8567 | |
29b0f896 AM |
8568 | prefix = 0; |
8569 | if (i.prefix[DATA_PREFIX] != 0) | |
8570 | { | |
8571 | prefix = 1; | |
8572 | i.prefixes -= 1; | |
8573 | code16 ^= CODE16; | |
8574 | } | |
6cb0a70e JB |
8575 | |
8576 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 8577 | |
29b0f896 AM |
8578 | size = 4; |
8579 | if (code16) | |
8580 | size = 2; | |
252b5132 | 8581 | |
f2810fe0 JB |
8582 | if (i.prefixes != 0) |
8583 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
252b5132 | 8584 | |
29b0f896 AM |
8585 | /* 1 opcode; 2 segment; offset */ |
8586 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8587 | |
29b0f896 AM |
8588 | if (i.prefix[DATA_PREFIX] != 0) |
8589 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 8590 | |
29b0f896 AM |
8591 | if (i.prefix[REX_PREFIX] != 0) |
8592 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 8593 | |
29b0f896 AM |
8594 | *p++ = i.tm.base_opcode; |
8595 | if (i.op[1].imms->X_op == O_constant) | |
8596 | { | |
8597 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 8598 | |
29b0f896 AM |
8599 | if (size == 2 |
8600 | && !fits_in_unsigned_word (n) | |
8601 | && !fits_in_signed_word (n)) | |
8602 | { | |
8603 | as_bad (_("16-bit jump out of range")); | |
8604 | return; | |
8605 | } | |
8606 | md_number_to_chars (p, n, size); | |
8607 | } | |
8608 | else | |
8609 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 8610 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
8611 | if (i.op[0].imms->X_op != O_constant) |
8612 | as_bad (_("can't handle non absolute segment in `%s'"), | |
8613 | i.tm.name); | |
8614 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
8615 | } | |
a217f122 | 8616 | |
b4a3a7b4 L |
8617 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8618 | void | |
8619 | x86_cleanup (void) | |
8620 | { | |
8621 | char *p; | |
8622 | asection *seg = now_seg; | |
8623 | subsegT subseg = now_subseg; | |
8624 | asection *sec; | |
8625 | unsigned int alignment, align_size_1; | |
8626 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
8627 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
8628 | unsigned int padding; | |
8629 | ||
8630 | if (!IS_ELF || !x86_used_note) | |
8631 | return; | |
8632 | ||
b4a3a7b4 L |
8633 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
8634 | ||
8635 | /* The .note.gnu.property section layout: | |
8636 | ||
8637 | Field Length Contents | |
8638 | ---- ---- ---- | |
8639 | n_namsz 4 4 | |
8640 | n_descsz 4 The note descriptor size | |
8641 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
8642 | n_name 4 "GNU" | |
8643 | n_desc n_descsz The program property array | |
8644 | .... .... .... | |
8645 | */ | |
8646 | ||
8647 | /* Create the .note.gnu.property section. */ | |
8648 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 8649 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
8650 | (SEC_ALLOC |
8651 | | SEC_LOAD | |
8652 | | SEC_DATA | |
8653 | | SEC_HAS_CONTENTS | |
8654 | | SEC_READONLY)); | |
8655 | ||
8656 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8657 | { | |
8658 | align_size_1 = 7; | |
8659 | alignment = 3; | |
8660 | } | |
8661 | else | |
8662 | { | |
8663 | align_size_1 = 3; | |
8664 | alignment = 2; | |
8665 | } | |
8666 | ||
fd361982 | 8667 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
8668 | elf_section_type (sec) = SHT_NOTE; |
8669 | ||
8670 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8671 | + 4-byte data */ | |
8672 | isa_1_descsz_raw = 4 + 4 + 4; | |
8673 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8674 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8675 | ||
8676 | feature_2_descsz_raw = isa_1_descsz; | |
8677 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8678 | + 4-byte data */ | |
8679 | feature_2_descsz_raw += 4 + 4 + 4; | |
8680 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8681 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8682 | & ~align_size_1); | |
8683 | ||
8684 | descsz = feature_2_descsz; | |
8685 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8686 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8687 | ||
8688 | /* Write n_namsz. */ | |
8689 | md_number_to_chars (p, (valueT) 4, 4); | |
8690 | ||
8691 | /* Write n_descsz. */ | |
8692 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8693 | ||
8694 | /* Write n_type. */ | |
8695 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8696 | ||
8697 | /* Write n_name. */ | |
8698 | memcpy (p + 4 * 3, "GNU", 4); | |
8699 | ||
8700 | /* Write 4-byte type. */ | |
8701 | md_number_to_chars (p + 4 * 4, | |
8702 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8703 | ||
8704 | /* Write 4-byte data size. */ | |
8705 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8706 | ||
8707 | /* Write 4-byte data. */ | |
8708 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8709 | ||
8710 | /* Zero out paddings. */ | |
8711 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8712 | if (padding) | |
8713 | memset (p + 4 * 7, 0, padding); | |
8714 | ||
8715 | /* Write 4-byte type. */ | |
8716 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8717 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8718 | ||
8719 | /* Write 4-byte data size. */ | |
8720 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8721 | ||
8722 | /* Write 4-byte data. */ | |
8723 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8724 | (valueT) x86_feature_2_used, 4); | |
8725 | ||
8726 | /* Zero out paddings. */ | |
8727 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8728 | if (padding) | |
8729 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8730 | ||
8731 | /* We probably can't restore the current segment, for there likely | |
8732 | isn't one yet... */ | |
8733 | if (seg && subseg) | |
8734 | subseg_set (seg, subseg); | |
8735 | } | |
8736 | #endif | |
8737 | ||
9c33702b JB |
8738 | static unsigned int |
8739 | encoding_length (const fragS *start_frag, offsetT start_off, | |
8740 | const char *frag_now_ptr) | |
8741 | { | |
8742 | unsigned int len = 0; | |
8743 | ||
8744 | if (start_frag != frag_now) | |
8745 | { | |
8746 | const fragS *fr = start_frag; | |
8747 | ||
8748 | do { | |
8749 | len += fr->fr_fix; | |
8750 | fr = fr->fr_next; | |
8751 | } while (fr && fr != frag_now); | |
8752 | } | |
8753 | ||
8754 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
8755 | } | |
8756 | ||
e379e5f3 | 8757 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
8758 | be macro-fused with conditional jumps. |
8759 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
8760 | or is one of the following format: | |
8761 | ||
8762 | cmp m, imm | |
8763 | add m, imm | |
8764 | sub m, imm | |
8765 | test m, imm | |
8766 | and m, imm | |
8767 | inc m | |
8768 | dec m | |
8769 | ||
8770 | it is unfusible. */ | |
e379e5f3 L |
8771 | |
8772 | static int | |
79d72f45 | 8773 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
8774 | { |
8775 | /* No RIP address. */ | |
8776 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
8777 | return 0; | |
8778 | ||
8779 | /* No VEX/EVEX encoding. */ | |
8780 | if (is_any_vex_encoding (&i.tm)) | |
8781 | return 0; | |
8782 | ||
79d72f45 HL |
8783 | /* add, sub without add/sub m, imm. */ |
8784 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
8785 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
8786 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 8787 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 8788 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
8789 | { |
8790 | *mf_cmp_p = mf_cmp_alu_cmp; | |
8791 | return !(i.mem_operands && i.imm_operands); | |
8792 | } | |
e379e5f3 | 8793 | |
79d72f45 HL |
8794 | /* and without and m, imm. */ |
8795 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
8796 | || ((i.tm.base_opcode | 3) == 0x83 | |
8797 | && i.tm.extension_opcode == 0x4)) | |
8798 | { | |
8799 | *mf_cmp_p = mf_cmp_test_and; | |
8800 | return !(i.mem_operands && i.imm_operands); | |
8801 | } | |
8802 | ||
8803 | /* test without test m imm. */ | |
e379e5f3 L |
8804 | if ((i.tm.base_opcode | 1) == 0x85 |
8805 | || (i.tm.base_opcode | 1) == 0xa9 | |
8806 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
8807 | && i.tm.extension_opcode == 0)) |
8808 | { | |
8809 | *mf_cmp_p = mf_cmp_test_and; | |
8810 | return !(i.mem_operands && i.imm_operands); | |
8811 | } | |
8812 | ||
8813 | /* cmp without cmp m, imm. */ | |
8814 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
8815 | || ((i.tm.base_opcode | 3) == 0x83 |
8816 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
8817 | { |
8818 | *mf_cmp_p = mf_cmp_alu_cmp; | |
8819 | return !(i.mem_operands && i.imm_operands); | |
8820 | } | |
e379e5f3 | 8821 | |
79d72f45 | 8822 | /* inc, dec without inc/dec m. */ |
e379e5f3 L |
8823 | if ((i.tm.cpu_flags.bitfield.cpuno64 |
8824 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
8825 | || ((i.tm.base_opcode | 1) == 0xff | |
8826 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
8827 | { |
8828 | *mf_cmp_p = mf_cmp_incdec; | |
8829 | return !i.mem_operands; | |
8830 | } | |
e379e5f3 L |
8831 | |
8832 | return 0; | |
8833 | } | |
8834 | ||
8835 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
8836 | ||
8837 | static int | |
79d72f45 | 8838 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
8839 | { |
8840 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8841 | if (!align_branch_power | |
8842 | || now_seg == absolute_section | |
8843 | || !cpu_arch_flags.bitfield.cpui386 | |
8844 | || !(align_branch & align_branch_fused_bit)) | |
8845 | return 0; | |
8846 | ||
79d72f45 | 8847 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 L |
8848 | { |
8849 | if (last_insn.kind == last_insn_other | |
8850 | || last_insn.seg != now_seg) | |
8851 | return 1; | |
8852 | if (flag_debug) | |
8853 | as_warn_where (last_insn.file, last_insn.line, | |
8854 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8855 | last_insn.name, i.tm.name); | |
8856 | } | |
8857 | ||
8858 | return 0; | |
8859 | } | |
8860 | ||
8861 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
8862 | ||
8863 | static int | |
8864 | add_branch_prefix_frag_p (void) | |
8865 | { | |
8866 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
8867 | to PadLock instructions since they include prefixes in opcode. */ | |
8868 | if (!align_branch_power | |
8869 | || !align_branch_prefix_size | |
8870 | || now_seg == absolute_section | |
8871 | || i.tm.cpu_flags.bitfield.cpupadlock | |
8872 | || !cpu_arch_flags.bitfield.cpui386) | |
8873 | return 0; | |
8874 | ||
8875 | /* Don't add prefix if it is a prefix or there is no operand in case | |
8876 | that segment prefix is special. */ | |
8877 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
8878 | return 0; | |
8879 | ||
8880 | if (last_insn.kind == last_insn_other | |
8881 | || last_insn.seg != now_seg) | |
8882 | return 1; | |
8883 | ||
8884 | if (flag_debug) | |
8885 | as_warn_where (last_insn.file, last_insn.line, | |
8886 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8887 | last_insn.name, i.tm.name); | |
8888 | ||
8889 | return 0; | |
8890 | } | |
8891 | ||
8892 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
8893 | ||
8894 | static int | |
79d72f45 HL |
8895 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
8896 | enum mf_jcc_kind *mf_jcc_p) | |
e379e5f3 L |
8897 | { |
8898 | int add_padding; | |
8899 | ||
8900 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8901 | if (!align_branch_power | |
8902 | || now_seg == absolute_section | |
8903 | || !cpu_arch_flags.bitfield.cpui386) | |
8904 | return 0; | |
8905 | ||
8906 | add_padding = 0; | |
8907 | ||
8908 | /* Check for jcc and direct jmp. */ | |
8909 | if (i.tm.opcode_modifier.jump == JUMP) | |
8910 | { | |
8911 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
8912 | { | |
8913 | *branch_p = align_branch_jmp; | |
8914 | add_padding = align_branch & align_branch_jmp_bit; | |
8915 | } | |
8916 | else | |
8917 | { | |
79d72f45 HL |
8918 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
8919 | igore the lowest bit. */ | |
8920 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
8921 | *branch_p = align_branch_jcc; |
8922 | if ((align_branch & align_branch_jcc_bit)) | |
8923 | add_padding = 1; | |
8924 | } | |
8925 | } | |
8926 | else if (is_any_vex_encoding (&i.tm)) | |
8927 | return 0; | |
8928 | else if ((i.tm.base_opcode | 1) == 0xc3) | |
8929 | { | |
8930 | /* Near ret. */ | |
8931 | *branch_p = align_branch_ret; | |
8932 | if ((align_branch & align_branch_ret_bit)) | |
8933 | add_padding = 1; | |
8934 | } | |
8935 | else | |
8936 | { | |
8937 | /* Check for indirect jmp, direct and indirect calls. */ | |
8938 | if (i.tm.base_opcode == 0xe8) | |
8939 | { | |
8940 | /* Direct call. */ | |
8941 | *branch_p = align_branch_call; | |
8942 | if ((align_branch & align_branch_call_bit)) | |
8943 | add_padding = 1; | |
8944 | } | |
8945 | else if (i.tm.base_opcode == 0xff | |
8946 | && (i.tm.extension_opcode == 2 | |
8947 | || i.tm.extension_opcode == 4)) | |
8948 | { | |
8949 | /* Indirect call and jmp. */ | |
8950 | *branch_p = align_branch_indirect; | |
8951 | if ((align_branch & align_branch_indirect_bit)) | |
8952 | add_padding = 1; | |
8953 | } | |
8954 | ||
8955 | if (add_padding | |
8956 | && i.disp_operands | |
8957 | && tls_get_addr | |
8958 | && (i.op[0].disps->X_op == O_symbol | |
8959 | || (i.op[0].disps->X_op == O_subtract | |
8960 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
8961 | { | |
8962 | symbolS *s = i.op[0].disps->X_add_symbol; | |
8963 | /* No padding to call to global or undefined tls_get_addr. */ | |
8964 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
8965 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
8966 | return 0; | |
8967 | } | |
8968 | } | |
8969 | ||
8970 | if (add_padding | |
8971 | && last_insn.kind != last_insn_other | |
8972 | && last_insn.seg == now_seg) | |
8973 | { | |
8974 | if (flag_debug) | |
8975 | as_warn_where (last_insn.file, last_insn.line, | |
8976 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8977 | last_insn.name, i.tm.name); | |
8978 | return 0; | |
8979 | } | |
8980 | ||
8981 | return add_padding; | |
8982 | } | |
8983 | ||
29b0f896 | 8984 | static void |
e3bb37b5 | 8985 | output_insn (void) |
29b0f896 | 8986 | { |
2bbd9c25 JJ |
8987 | fragS *insn_start_frag; |
8988 | offsetT insn_start_off; | |
e379e5f3 L |
8989 | fragS *fragP = NULL; |
8990 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
8991 | /* The initializer is arbitrary just to avoid uninitialized error. |
8992 | it's actually either assigned in add_branch_padding_frag_p | |
8993 | or never be used. */ | |
8994 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 8995 | |
b4a3a7b4 L |
8996 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8997 | if (IS_ELF && x86_used_note) | |
8998 | { | |
8999 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
9000 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
9001 | if (i.tm.cpu_flags.bitfield.cpusse) | |
9002 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
9003 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
9004 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
9005 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
9006 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
9007 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
9008 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
9009 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
9010 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
9011 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
9012 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
9013 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
9014 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
9015 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
9016 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
9017 | if (i.tm.cpu_flags.bitfield.cpufma) | |
9018 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
9019 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
9020 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
9021 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
9022 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
9023 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
9024 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
9025 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
9026 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
9027 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
9028 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
9029 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
9030 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
9031 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
9032 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
9033 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
9034 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
9035 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
9036 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
9037 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
9038 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
9039 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
9040 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
9041 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
9042 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
9043 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
9044 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
9045 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
9046 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
462cac58 L |
9047 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
9048 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; | |
b4a3a7b4 L |
9049 | |
9050 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
9051 | || i.tm.cpu_flags.bitfield.cpu287 | |
9052 | || i.tm.cpu_flags.bitfield.cpu387 | |
9053 | || i.tm.cpu_flags.bitfield.cpu687 | |
9054 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
9055 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
319ff62c JB |
9056 | if (i.has_regmmx |
9057 | || i.tm.base_opcode == 0xf77 /* emms */ | |
a7e12755 L |
9058 | || i.tm.base_opcode == 0xf0e /* femms */ |
9059 | || i.tm.base_opcode == 0xf2a /* cvtpi2ps */ | |
9060 | || i.tm.base_opcode == 0x660f2a /* cvtpi2pd */) | |
b4a3a7b4 L |
9061 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
9062 | if (i.has_regxmm) | |
9063 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
9064 | if (i.has_regymm) | |
9065 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
9066 | if (i.has_regzmm) | |
9067 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
9068 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
9069 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
9070 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
9071 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
9072 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
9073 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
9074 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
9075 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
9076 | } | |
9077 | #endif | |
9078 | ||
29b0f896 AM |
9079 | /* Tie dwarf2 debug info to the address at the start of the insn. |
9080 | We can't do this after the insn has been output as the current | |
9081 | frag may have been closed off. eg. by frag_var. */ | |
9082 | dwarf2_emit_insn (0); | |
9083 | ||
2bbd9c25 JJ |
9084 | insn_start_frag = frag_now; |
9085 | insn_start_off = frag_now_fix (); | |
9086 | ||
79d72f45 | 9087 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
e379e5f3 L |
9088 | { |
9089 | char *p; | |
9090 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
9091 | unsigned int max_branch_padding_size = 14; | |
9092 | ||
9093 | /* Align section to boundary. */ | |
9094 | record_alignment (now_seg, align_branch_power); | |
9095 | ||
9096 | /* Make room for padding. */ | |
9097 | frag_grow (max_branch_padding_size); | |
9098 | ||
9099 | /* Start of the padding. */ | |
9100 | p = frag_more (0); | |
9101 | ||
9102 | fragP = frag_now; | |
9103 | ||
9104 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
9105 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
9106 | NULL, 0, p); | |
9107 | ||
79d72f45 | 9108 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
9109 | fragP->tc_frag_data.branch_type = branch; |
9110 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
9111 | } | |
9112 | ||
29b0f896 | 9113 | /* Output jumps. */ |
0cfa3eb3 | 9114 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 9115 | output_branch (); |
0cfa3eb3 JB |
9116 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
9117 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 9118 | output_jump (); |
0cfa3eb3 | 9119 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
9120 | output_interseg_jump (); |
9121 | else | |
9122 | { | |
9123 | /* Output normal instructions here. */ | |
9124 | char *p; | |
9125 | unsigned char *q; | |
47465058 | 9126 | unsigned int j; |
331d2d0d | 9127 | unsigned int prefix; |
79d72f45 | 9128 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 9129 | |
e4e00185 | 9130 | if (avoid_fence |
c3949f43 JB |
9131 | && (i.tm.base_opcode == 0xfaee8 |
9132 | || i.tm.base_opcode == 0xfaef0 | |
9133 | || i.tm.base_opcode == 0xfaef8)) | |
e4e00185 AS |
9134 | { |
9135 | /* Encode lfence, mfence, and sfence as | |
9136 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
9137 | offsetT val = 0x240483f0ULL; | |
9138 | p = frag_more (5); | |
9139 | md_number_to_chars (p, val, 5); | |
9140 | return; | |
9141 | } | |
9142 | ||
d022bddd IT |
9143 | /* Some processors fail on LOCK prefix. This options makes |
9144 | assembler ignore LOCK prefix and serves as a workaround. */ | |
9145 | if (omit_lock_prefix) | |
9146 | { | |
9147 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
9148 | return; | |
9149 | i.prefix[LOCK_PREFIX] = 0; | |
9150 | } | |
9151 | ||
e379e5f3 L |
9152 | if (branch) |
9153 | /* Skip if this is a branch. */ | |
9154 | ; | |
79d72f45 | 9155 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
e379e5f3 L |
9156 | { |
9157 | /* Make room for padding. */ | |
9158 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
9159 | p = frag_more (0); | |
9160 | ||
9161 | fragP = frag_now; | |
9162 | ||
9163 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
9164 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
9165 | NULL, 0, p); | |
9166 | ||
79d72f45 | 9167 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
9168 | fragP->tc_frag_data.branch_type = align_branch_fused; |
9169 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
9170 | } | |
9171 | else if (add_branch_prefix_frag_p ()) | |
9172 | { | |
9173 | unsigned int max_prefix_size = align_branch_prefix_size; | |
9174 | ||
9175 | /* Make room for padding. */ | |
9176 | frag_grow (max_prefix_size); | |
9177 | p = frag_more (0); | |
9178 | ||
9179 | fragP = frag_now; | |
9180 | ||
9181 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
9182 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
9183 | NULL, 0, p); | |
9184 | ||
9185 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
9186 | } | |
9187 | ||
43234a1e L |
9188 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
9189 | don't need the explicit prefix. */ | |
9190 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 9191 | { |
c0f3af97 | 9192 | switch (i.tm.opcode_length) |
bc4bd9ab | 9193 | { |
c0f3af97 L |
9194 | case 3: |
9195 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 9196 | { |
c0f3af97 | 9197 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
c3949f43 JB |
9198 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
9199 | || prefix != REPE_PREFIX_OPCODE | |
9200 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
9201 | add_prefix (prefix); | |
c0f3af97 L |
9202 | } |
9203 | break; | |
9204 | case 2: | |
9205 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
9206 | { | |
9207 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
c3949f43 | 9208 | add_prefix (prefix); |
4dffcebc | 9209 | } |
c0f3af97 L |
9210 | break; |
9211 | case 1: | |
9212 | break; | |
390c91cf L |
9213 | case 0: |
9214 | /* Check for pseudo prefixes. */ | |
9215 | as_bad_where (insn_start_frag->fr_file, | |
9216 | insn_start_frag->fr_line, | |
9217 | _("pseudo prefix without instruction")); | |
9218 | return; | |
c0f3af97 L |
9219 | default: |
9220 | abort (); | |
bc4bd9ab | 9221 | } |
c0f3af97 | 9222 | |
6d19a37a | 9223 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
9224 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
9225 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
9226 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
9227 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
9228 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
9229 | if (x86_elf_abi == X86_64_X32_ABI |
9230 | && i.operands == 2 | |
14470f07 L |
9231 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
9232 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
9233 | && i.prefix[REX_PREFIX] == 0) |
9234 | add_prefix (REX_OPCODE); | |
6d19a37a | 9235 | #endif |
cf61b747 | 9236 | |
c0f3af97 L |
9237 | /* The prefix bytes. */ |
9238 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
9239 | if (*q) | |
9240 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 9241 | } |
ae5c1c7b | 9242 | else |
c0f3af97 L |
9243 | { |
9244 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
9245 | if (*q) | |
9246 | switch (j) | |
9247 | { | |
9248 | case REX_PREFIX: | |
9249 | /* REX byte is encoded in VEX prefix. */ | |
9250 | break; | |
9251 | case SEG_PREFIX: | |
9252 | case ADDR_PREFIX: | |
9253 | FRAG_APPEND_1_CHAR (*q); | |
9254 | break; | |
9255 | default: | |
9256 | /* There should be no other prefixes for instructions | |
9257 | with VEX prefix. */ | |
9258 | abort (); | |
9259 | } | |
9260 | ||
43234a1e L |
9261 | /* For EVEX instructions i.vrex should become 0 after |
9262 | build_evex_prefix. For VEX instructions upper 16 registers | |
9263 | aren't available, so VREX should be 0. */ | |
9264 | if (i.vrex) | |
9265 | abort (); | |
c0f3af97 L |
9266 | /* Now the VEX prefix. */ |
9267 | p = frag_more (i.vex.length); | |
9268 | for (j = 0; j < i.vex.length; j++) | |
9269 | p[j] = i.vex.bytes[j]; | |
9270 | } | |
252b5132 | 9271 | |
29b0f896 | 9272 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 9273 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
9274 | { |
9275 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
9276 | } | |
9277 | else | |
9278 | { | |
4dffcebc | 9279 | switch (i.tm.opcode_length) |
331d2d0d | 9280 | { |
43234a1e L |
9281 | case 4: |
9282 | p = frag_more (4); | |
9283 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
9284 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
9285 | break; | |
4dffcebc | 9286 | case 3: |
331d2d0d L |
9287 | p = frag_more (3); |
9288 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
9289 | break; |
9290 | case 2: | |
9291 | p = frag_more (2); | |
9292 | break; | |
9293 | default: | |
9294 | abort (); | |
9295 | break; | |
331d2d0d | 9296 | } |
0f10071e | 9297 | |
29b0f896 AM |
9298 | /* Put out high byte first: can't use md_number_to_chars! */ |
9299 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
9300 | *p = i.tm.base_opcode & 0xff; | |
9301 | } | |
3e73aa7c | 9302 | |
29b0f896 | 9303 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 9304 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 9305 | { |
4a3523fa L |
9306 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
9307 | | i.rm.reg << 3 | |
9308 | | i.rm.mode << 6)); | |
29b0f896 AM |
9309 | /* If i.rm.regmem == ESP (4) |
9310 | && i.rm.mode != (Register mode) | |
9311 | && not 16 bit | |
9312 | ==> need second modrm byte. */ | |
9313 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
9314 | && i.rm.mode != 3 | |
dc821c5f | 9315 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
9316 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
9317 | | i.sib.index << 3 | |
9318 | | i.sib.scale << 6)); | |
29b0f896 | 9319 | } |
3e73aa7c | 9320 | |
29b0f896 | 9321 | if (i.disp_operands) |
2bbd9c25 | 9322 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 9323 | |
29b0f896 | 9324 | if (i.imm_operands) |
2bbd9c25 | 9325 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
9326 | |
9327 | /* | |
9328 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
9329 | * absolute section, and abs_section_offset not getting updated as data | |
9330 | * gets added to the frag breaks the logic below. | |
9331 | */ | |
9332 | if (now_seg != absolute_section) | |
9333 | { | |
9334 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
9335 | if (j > 15) | |
9336 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
9337 | j); | |
e379e5f3 L |
9338 | else if (fragP) |
9339 | { | |
9340 | /* NB: Don't add prefix with GOTPC relocation since | |
9341 | output_disp() above depends on the fixed encoding | |
9342 | length. Can't add prefix with TLS relocation since | |
9343 | it breaks TLS linker optimization. */ | |
9344 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
9345 | /* Prefix count on the current instruction. */ | |
9346 | unsigned int count = i.vex.length; | |
9347 | unsigned int k; | |
9348 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
9349 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
9350 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
9351 | count++; | |
9352 | ||
9353 | /* Count prefixes for extended opcode maps. */ | |
9354 | if (!i.vex.length) | |
9355 | switch (i.tm.opcode_length) | |
9356 | { | |
9357 | case 3: | |
9358 | if (((i.tm.base_opcode >> 16) & 0xff) == 0xf) | |
9359 | { | |
9360 | count++; | |
9361 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
9362 | { | |
9363 | case 0x38: | |
9364 | case 0x3a: | |
9365 | count++; | |
9366 | break; | |
9367 | default: | |
9368 | break; | |
9369 | } | |
9370 | } | |
9371 | break; | |
9372 | case 2: | |
9373 | if (((i.tm.base_opcode >> 8) & 0xff) == 0xf) | |
9374 | count++; | |
9375 | break; | |
9376 | case 1: | |
9377 | break; | |
9378 | default: | |
9379 | abort (); | |
9380 | } | |
9381 | ||
9382 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
9383 | == BRANCH_PREFIX) | |
9384 | { | |
9385 | /* Set the maximum prefix size in BRANCH_PREFIX | |
9386 | frag. */ | |
9387 | if (fragP->tc_frag_data.max_bytes > max) | |
9388 | fragP->tc_frag_data.max_bytes = max; | |
9389 | if (fragP->tc_frag_data.max_bytes > count) | |
9390 | fragP->tc_frag_data.max_bytes -= count; | |
9391 | else | |
9392 | fragP->tc_frag_data.max_bytes = 0; | |
9393 | } | |
9394 | else | |
9395 | { | |
9396 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
9397 | frag. */ | |
9398 | unsigned int max_prefix_size; | |
9399 | if (align_branch_prefix_size > max) | |
9400 | max_prefix_size = max; | |
9401 | else | |
9402 | max_prefix_size = align_branch_prefix_size; | |
9403 | if (max_prefix_size > count) | |
9404 | fragP->tc_frag_data.max_prefix_length | |
9405 | = max_prefix_size - count; | |
9406 | } | |
9407 | ||
9408 | /* Use existing segment prefix if possible. Use CS | |
9409 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
9410 | segment prefix with ESP/EBP base register and use DS | |
9411 | segment prefix without ESP/EBP base register. */ | |
9412 | if (i.prefix[SEG_PREFIX]) | |
9413 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
9414 | else if (flag_code == CODE_64BIT) | |
9415 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
9416 | else if (i.base_reg | |
9417 | && (i.base_reg->reg_num == 4 | |
9418 | || i.base_reg->reg_num == 5)) | |
9419 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
9420 | else | |
9421 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
9422 | } | |
9c33702b | 9423 | } |
29b0f896 | 9424 | } |
252b5132 | 9425 | |
e379e5f3 L |
9426 | /* NB: Don't work with COND_JUMP86 without i386. */ |
9427 | if (align_branch_power | |
9428 | && now_seg != absolute_section | |
9429 | && cpu_arch_flags.bitfield.cpui386) | |
9430 | { | |
9431 | /* Terminate each frag so that we can add prefix and check for | |
9432 | fused jcc. */ | |
9433 | frag_wane (frag_now); | |
9434 | frag_new (0); | |
9435 | } | |
9436 | ||
29b0f896 AM |
9437 | #ifdef DEBUG386 |
9438 | if (flag_debug) | |
9439 | { | |
7b81dfbb | 9440 | pi ("" /*line*/, &i); |
29b0f896 AM |
9441 | } |
9442 | #endif /* DEBUG386 */ | |
9443 | } | |
252b5132 | 9444 | |
e205caa7 L |
9445 | /* Return the size of the displacement operand N. */ |
9446 | ||
9447 | static int | |
9448 | disp_size (unsigned int n) | |
9449 | { | |
9450 | int size = 4; | |
43234a1e | 9451 | |
b5014f7a | 9452 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
9453 | size = 8; |
9454 | else if (i.types[n].bitfield.disp8) | |
9455 | size = 1; | |
9456 | else if (i.types[n].bitfield.disp16) | |
9457 | size = 2; | |
e205caa7 L |
9458 | return size; |
9459 | } | |
9460 | ||
9461 | /* Return the size of the immediate operand N. */ | |
9462 | ||
9463 | static int | |
9464 | imm_size (unsigned int n) | |
9465 | { | |
9466 | int size = 4; | |
40fb9820 L |
9467 | if (i.types[n].bitfield.imm64) |
9468 | size = 8; | |
9469 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
9470 | size = 1; | |
9471 | else if (i.types[n].bitfield.imm16) | |
9472 | size = 2; | |
e205caa7 L |
9473 | return size; |
9474 | } | |
9475 | ||
29b0f896 | 9476 | static void |
64e74474 | 9477 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9478 | { |
9479 | char *p; | |
9480 | unsigned int n; | |
252b5132 | 9481 | |
29b0f896 AM |
9482 | for (n = 0; n < i.operands; n++) |
9483 | { | |
b5014f7a | 9484 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
9485 | { |
9486 | if (i.op[n].disps->X_op == O_constant) | |
9487 | { | |
e205caa7 | 9488 | int size = disp_size (n); |
43234a1e | 9489 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 9490 | |
629cfaf1 JB |
9491 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
9492 | size); | |
29b0f896 AM |
9493 | p = frag_more (size); |
9494 | md_number_to_chars (p, val, size); | |
9495 | } | |
9496 | else | |
9497 | { | |
f86103b7 | 9498 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 9499 | int size = disp_size (n); |
40fb9820 | 9500 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 9501 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 9502 | fixS *fixP; |
29b0f896 | 9503 | |
e205caa7 | 9504 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 9505 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 9506 | |
29b0f896 AM |
9507 | /* The PC relative address is computed relative |
9508 | to the instruction boundary, so in case immediate | |
9509 | fields follows, we need to adjust the value. */ | |
9510 | if (pcrel && i.imm_operands) | |
9511 | { | |
29b0f896 | 9512 | unsigned int n1; |
e205caa7 | 9513 | int sz = 0; |
252b5132 | 9514 | |
29b0f896 | 9515 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 9516 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 9517 | { |
e205caa7 L |
9518 | /* Only one immediate is allowed for PC |
9519 | relative address. */ | |
9c2799c2 | 9520 | gas_assert (sz == 0); |
e205caa7 L |
9521 | sz = imm_size (n1); |
9522 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 9523 | } |
29b0f896 | 9524 | /* We should find the immediate. */ |
9c2799c2 | 9525 | gas_assert (sz != 0); |
29b0f896 | 9526 | } |
520dc8e8 | 9527 | |
29b0f896 | 9528 | p = frag_more (size); |
d258b828 | 9529 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 9530 | if (GOT_symbol |
2bbd9c25 | 9531 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 9532 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9533 | || reloc_type == BFD_RELOC_X86_64_32S |
9534 | || (reloc_type == BFD_RELOC_64 | |
9535 | && object_64bit)) | |
d6ab8113 JB |
9536 | && (i.op[n].disps->X_op == O_symbol |
9537 | || (i.op[n].disps->X_op == O_add | |
9538 | && ((symbol_get_value_expression | |
9539 | (i.op[n].disps->X_op_symbol)->X_op) | |
9540 | == O_subtract)))) | |
9541 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 9542 | { |
4fa24527 | 9543 | if (!object_64bit) |
7b81dfbb AJ |
9544 | { |
9545 | reloc_type = BFD_RELOC_386_GOTPC; | |
e379e5f3 | 9546 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9547 | i.op[n].imms->X_add_number += |
9548 | encoding_length (insn_start_frag, insn_start_off, p); | |
7b81dfbb AJ |
9549 | } |
9550 | else if (reloc_type == BFD_RELOC_64) | |
9551 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 9552 | else |
7b81dfbb AJ |
9553 | /* Don't do the adjustment for x86-64, as there |
9554 | the pcrel addressing is relative to the _next_ | |
9555 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 9556 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 9557 | } |
e379e5f3 L |
9558 | else if (align_branch_power) |
9559 | { | |
9560 | switch (reloc_type) | |
9561 | { | |
9562 | case BFD_RELOC_386_TLS_GD: | |
9563 | case BFD_RELOC_386_TLS_LDM: | |
9564 | case BFD_RELOC_386_TLS_IE: | |
9565 | case BFD_RELOC_386_TLS_IE_32: | |
9566 | case BFD_RELOC_386_TLS_GOTIE: | |
9567 | case BFD_RELOC_386_TLS_GOTDESC: | |
9568 | case BFD_RELOC_386_TLS_DESC_CALL: | |
9569 | case BFD_RELOC_X86_64_TLSGD: | |
9570 | case BFD_RELOC_X86_64_TLSLD: | |
9571 | case BFD_RELOC_X86_64_GOTTPOFF: | |
9572 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
9573 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9574 | i.has_gotpc_tls_reloc = TRUE; | |
9575 | default: | |
9576 | break; | |
9577 | } | |
9578 | } | |
02a86693 L |
9579 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
9580 | size, i.op[n].disps, pcrel, | |
9581 | reloc_type); | |
9582 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
9583 | "test %reg, mem" and "binop mem, %reg" where binop | |
9584 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
9585 | instructions without data prefix. Always generate |
9586 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
9587 | if (i.prefix[DATA_PREFIX] == 0 | |
9588 | && (generate_relax_relocations | |
9589 | || (!object_64bit | |
9590 | && i.rm.mode == 0 | |
9591 | && i.rm.regmem == 5)) | |
0cb4071e L |
9592 | && (i.rm.mode == 2 |
9593 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
2ae4c703 | 9594 | && !is_any_vex_encoding(&i.tm) |
02a86693 L |
9595 | && ((i.operands == 1 |
9596 | && i.tm.base_opcode == 0xff | |
9597 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
9598 | || (i.operands == 2 | |
9599 | && (i.tm.base_opcode == 0x8b | |
9600 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 9601 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
9602 | { |
9603 | if (object_64bit) | |
9604 | { | |
9605 | fixP->fx_tcbit = i.rex != 0; | |
9606 | if (i.base_reg | |
e968fc9b | 9607 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
9608 | fixP->fx_tcbit2 = 1; |
9609 | } | |
9610 | else | |
9611 | fixP->fx_tcbit2 = 1; | |
9612 | } | |
29b0f896 AM |
9613 | } |
9614 | } | |
9615 | } | |
9616 | } | |
252b5132 | 9617 | |
29b0f896 | 9618 | static void |
64e74474 | 9619 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9620 | { |
9621 | char *p; | |
9622 | unsigned int n; | |
252b5132 | 9623 | |
29b0f896 AM |
9624 | for (n = 0; n < i.operands; n++) |
9625 | { | |
43234a1e L |
9626 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
9627 | if (i.rounding && (int) n == i.rounding->operand) | |
9628 | continue; | |
9629 | ||
40fb9820 | 9630 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
9631 | { |
9632 | if (i.op[n].imms->X_op == O_constant) | |
9633 | { | |
e205caa7 | 9634 | int size = imm_size (n); |
29b0f896 | 9635 | offsetT val; |
b4cac588 | 9636 | |
29b0f896 AM |
9637 | val = offset_in_range (i.op[n].imms->X_add_number, |
9638 | size); | |
9639 | p = frag_more (size); | |
9640 | md_number_to_chars (p, val, size); | |
9641 | } | |
9642 | else | |
9643 | { | |
9644 | /* Not absolute_section. | |
9645 | Need a 32-bit fixup (don't support 8bit | |
9646 | non-absolute imms). Try to support other | |
9647 | sizes ... */ | |
f86103b7 | 9648 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
9649 | int size = imm_size (n); |
9650 | int sign; | |
29b0f896 | 9651 | |
40fb9820 | 9652 | if (i.types[n].bitfield.imm32s |
a7d61044 | 9653 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 9654 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 9655 | sign = 1; |
e205caa7 L |
9656 | else |
9657 | sign = 0; | |
520dc8e8 | 9658 | |
29b0f896 | 9659 | p = frag_more (size); |
d258b828 | 9660 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 9661 | |
2bbd9c25 JJ |
9662 | /* This is tough to explain. We end up with this one if we |
9663 | * have operands that look like | |
9664 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
9665 | * obtain the absolute address of the GOT, and it is strongly | |
9666 | * preferable from a performance point of view to avoid using | |
9667 | * a runtime relocation for this. The actual sequence of | |
9668 | * instructions often look something like: | |
9669 | * | |
9670 | * call .L66 | |
9671 | * .L66: | |
9672 | * popl %ebx | |
9673 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
9674 | * | |
9675 | * The call and pop essentially return the absolute address | |
9676 | * of the label .L66 and store it in %ebx. The linker itself | |
9677 | * will ultimately change the first operand of the addl so | |
9678 | * that %ebx points to the GOT, but to keep things simple, the | |
9679 | * .o file must have this operand set so that it generates not | |
9680 | * the absolute address of .L66, but the absolute address of | |
9681 | * itself. This allows the linker itself simply treat a GOTPC | |
9682 | * relocation as asking for a pcrel offset to the GOT to be | |
9683 | * added in, and the addend of the relocation is stored in the | |
9684 | * operand field for the instruction itself. | |
9685 | * | |
9686 | * Our job here is to fix the operand so that it would add | |
9687 | * the correct offset so that %ebx would point to itself. The | |
9688 | * thing that is tricky is that .-.L66 will point to the | |
9689 | * beginning of the instruction, so we need to further modify | |
9690 | * the operand so that it will point to itself. There are | |
9691 | * other cases where you have something like: | |
9692 | * | |
9693 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
9694 | * | |
9695 | * and here no correction would be required. Internally in | |
9696 | * the assembler we treat operands of this form as not being | |
9697 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
9698 | * whether it would simplify matters to do it this way. Who | |
9699 | * knows. In earlier versions of the PIC patches, the | |
9700 | * pcrel_adjust field was used to store the correction, but | |
9701 | * since the expression is not pcrel, I felt it would be | |
9702 | * confusing to do it this way. */ | |
9703 | ||
d6ab8113 | 9704 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9705 | || reloc_type == BFD_RELOC_X86_64_32S |
9706 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
9707 | && GOT_symbol |
9708 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
9709 | && (i.op[n].imms->X_op == O_symbol | |
9710 | || (i.op[n].imms->X_op == O_add | |
9711 | && ((symbol_get_value_expression | |
9712 | (i.op[n].imms->X_op_symbol)->X_op) | |
9713 | == O_subtract)))) | |
9714 | { | |
4fa24527 | 9715 | if (!object_64bit) |
d6ab8113 | 9716 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 9717 | else if (size == 4) |
d6ab8113 | 9718 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
9719 | else if (size == 8) |
9720 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
e379e5f3 | 9721 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9722 | i.op[n].imms->X_add_number += |
9723 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 9724 | } |
29b0f896 AM |
9725 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
9726 | i.op[n].imms, 0, reloc_type); | |
9727 | } | |
9728 | } | |
9729 | } | |
252b5132 RH |
9730 | } |
9731 | \f | |
d182319b JB |
9732 | /* x86_cons_fix_new is called via the expression parsing code when a |
9733 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
9734 | static int cons_sign = -1; |
9735 | ||
9736 | void | |
e3bb37b5 | 9737 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 9738 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 9739 | { |
d258b828 | 9740 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
9741 | |
9742 | #ifdef TE_PE | |
9743 | if (exp->X_op == O_secrel) | |
9744 | { | |
9745 | exp->X_op = O_symbol; | |
9746 | r = BFD_RELOC_32_SECREL; | |
9747 | } | |
9748 | #endif | |
9749 | ||
9750 | fix_new_exp (frag, off, len, exp, 0, r); | |
9751 | } | |
9752 | ||
357d1bd8 L |
9753 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
9754 | purpose of the `.dc.a' internal pseudo-op. */ | |
9755 | ||
9756 | int | |
9757 | x86_address_bytes (void) | |
9758 | { | |
9759 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
9760 | return 4; | |
9761 | return stdoutput->arch_info->bits_per_address / 8; | |
9762 | } | |
9763 | ||
d382c579 TG |
9764 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
9765 | || defined (LEX_AT) | |
d258b828 | 9766 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 9767 | #else |
f3c180ae AM |
9768 | /* Parse operands of the form |
9769 | <symbol>@GOTOFF+<nnn> | |
9770 | and similar .plt or .got references. | |
9771 | ||
9772 | If we find one, set up the correct relocation in RELOC and copy the | |
9773 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
9774 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9775 | is non-null set it to the length of the string we removed from the | |
9776 | input line. Otherwise return NULL. */ | |
9777 | static char * | |
91d6fa6a | 9778 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 9779 | int *adjust, |
d258b828 | 9780 | i386_operand_type *types) |
f3c180ae | 9781 | { |
7b81dfbb AJ |
9782 | /* Some of the relocations depend on the size of what field is to |
9783 | be relocated. But in our callers i386_immediate and i386_displacement | |
9784 | we don't yet know the operand size (this will be set by insn | |
9785 | matching). Hence we record the word32 relocation here, | |
9786 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
9787 | static const struct { |
9788 | const char *str; | |
cff8d58a | 9789 | int len; |
4fa24527 | 9790 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 9791 | const i386_operand_type types64; |
f3c180ae | 9792 | } gotrel[] = { |
8ce3d284 | 9793 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
9794 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
9795 | BFD_RELOC_SIZE32 }, | |
9796 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 9797 | #endif |
cff8d58a L |
9798 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
9799 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 9800 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
9801 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
9802 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 9803 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9804 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
9805 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 9806 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9807 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
9808 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 9809 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9810 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
9811 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 9812 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9813 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
9814 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 9815 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9816 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
9817 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9818 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9819 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
9820 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 9821 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9822 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
9823 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 9824 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9825 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
9826 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 9827 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9828 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
9829 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9830 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9831 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
9832 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 9833 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9834 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
9835 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9836 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9837 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
9838 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9839 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9840 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
9841 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 9842 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
9843 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
9844 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 9845 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9846 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
9847 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 9848 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
9849 | }; |
9850 | char *cp; | |
9851 | unsigned int j; | |
9852 | ||
d382c579 | 9853 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
9854 | if (!IS_ELF) |
9855 | return NULL; | |
d382c579 | 9856 | #endif |
718ddfc0 | 9857 | |
f3c180ae | 9858 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 9859 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
9860 | return NULL; |
9861 | ||
47465058 | 9862 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 9863 | { |
cff8d58a | 9864 | int len = gotrel[j].len; |
28f81592 | 9865 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 9866 | { |
4fa24527 | 9867 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 9868 | { |
28f81592 AM |
9869 | int first, second; |
9870 | char *tmpbuf, *past_reloc; | |
f3c180ae | 9871 | |
91d6fa6a | 9872 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 9873 | |
3956db08 JB |
9874 | if (types) |
9875 | { | |
9876 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
9877 | { |
9878 | types->bitfield.imm32 = 1; | |
9879 | types->bitfield.disp32 = 1; | |
9880 | } | |
3956db08 JB |
9881 | else |
9882 | *types = gotrel[j].types64; | |
9883 | } | |
9884 | ||
8fd4256d | 9885 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
9886 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
9887 | ||
28f81592 | 9888 | /* The length of the first part of our input line. */ |
f3c180ae | 9889 | first = cp - input_line_pointer; |
28f81592 AM |
9890 | |
9891 | /* The second part goes from after the reloc token until | |
67c11a9b | 9892 | (and including) an end_of_line char or comma. */ |
28f81592 | 9893 | past_reloc = cp + 1 + len; |
67c11a9b AM |
9894 | cp = past_reloc; |
9895 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9896 | ++cp; | |
9897 | second = cp + 1 - past_reloc; | |
28f81592 AM |
9898 | |
9899 | /* Allocate and copy string. The trailing NUL shouldn't | |
9900 | be necessary, but be safe. */ | |
add39d23 | 9901 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 9902 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
9903 | if (second != 0 && *past_reloc != ' ') |
9904 | /* Replace the relocation token with ' ', so that | |
9905 | errors like foo@GOTOFF1 will be detected. */ | |
9906 | tmpbuf[first++] = ' '; | |
af89796a L |
9907 | else |
9908 | /* Increment length by 1 if the relocation token is | |
9909 | removed. */ | |
9910 | len++; | |
9911 | if (adjust) | |
9912 | *adjust = len; | |
0787a12d AM |
9913 | memcpy (tmpbuf + first, past_reloc, second); |
9914 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
9915 | return tmpbuf; |
9916 | } | |
9917 | ||
4fa24527 JB |
9918 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
9919 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
9920 | return NULL; |
9921 | } | |
9922 | } | |
9923 | ||
9924 | /* Might be a symbol version string. Don't as_bad here. */ | |
9925 | return NULL; | |
9926 | } | |
4e4f7c87 | 9927 | #endif |
f3c180ae | 9928 | |
a988325c NC |
9929 | #ifdef TE_PE |
9930 | #ifdef lex_got | |
9931 | #undef lex_got | |
9932 | #endif | |
9933 | /* Parse operands of the form | |
9934 | <symbol>@SECREL32+<nnn> | |
9935 | ||
9936 | If we find one, set up the correct relocation in RELOC and copy the | |
9937 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
9938 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9939 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
9940 | input line. Otherwise return NULL. |
9941 | ||
a988325c NC |
9942 | This function is copied from the ELF version above adjusted for PE targets. */ |
9943 | ||
9944 | static char * | |
9945 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
9946 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 9947 | i386_operand_type *types) |
a988325c NC |
9948 | { |
9949 | static const struct | |
9950 | { | |
9951 | const char *str; | |
9952 | int len; | |
9953 | const enum bfd_reloc_code_real rel[2]; | |
9954 | const i386_operand_type types64; | |
9955 | } | |
9956 | gotrel[] = | |
9957 | { | |
9958 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
9959 | BFD_RELOC_32_SECREL }, | |
9960 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
9961 | }; | |
9962 | ||
9963 | char *cp; | |
9964 | unsigned j; | |
9965 | ||
9966 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
9967 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
9968 | return NULL; | |
9969 | ||
9970 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
9971 | { | |
9972 | int len = gotrel[j].len; | |
9973 | ||
9974 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
9975 | { | |
9976 | if (gotrel[j].rel[object_64bit] != 0) | |
9977 | { | |
9978 | int first, second; | |
9979 | char *tmpbuf, *past_reloc; | |
9980 | ||
9981 | *rel = gotrel[j].rel[object_64bit]; | |
9982 | if (adjust) | |
9983 | *adjust = len; | |
9984 | ||
9985 | if (types) | |
9986 | { | |
9987 | if (flag_code != CODE_64BIT) | |
9988 | { | |
9989 | types->bitfield.imm32 = 1; | |
9990 | types->bitfield.disp32 = 1; | |
9991 | } | |
9992 | else | |
9993 | *types = gotrel[j].types64; | |
9994 | } | |
9995 | ||
9996 | /* The length of the first part of our input line. */ | |
9997 | first = cp - input_line_pointer; | |
9998 | ||
9999 | /* The second part goes from after the reloc token until | |
10000 | (and including) an end_of_line char or comma. */ | |
10001 | past_reloc = cp + 1 + len; | |
10002 | cp = past_reloc; | |
10003 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
10004 | ++cp; | |
10005 | second = cp + 1 - past_reloc; | |
10006 | ||
10007 | /* Allocate and copy string. The trailing NUL shouldn't | |
10008 | be necessary, but be safe. */ | |
add39d23 | 10009 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
10010 | memcpy (tmpbuf, input_line_pointer, first); |
10011 | if (second != 0 && *past_reloc != ' ') | |
10012 | /* Replace the relocation token with ' ', so that | |
10013 | errors like foo@SECLREL321 will be detected. */ | |
10014 | tmpbuf[first++] = ' '; | |
10015 | memcpy (tmpbuf + first, past_reloc, second); | |
10016 | tmpbuf[first + second] = '\0'; | |
10017 | return tmpbuf; | |
10018 | } | |
10019 | ||
10020 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
10021 | gotrel[j].str, 1 << (5 + object_64bit)); | |
10022 | return NULL; | |
10023 | } | |
10024 | } | |
10025 | ||
10026 | /* Might be a symbol version string. Don't as_bad here. */ | |
10027 | return NULL; | |
10028 | } | |
10029 | ||
10030 | #endif /* TE_PE */ | |
10031 | ||
62ebcb5c | 10032 | bfd_reloc_code_real_type |
e3bb37b5 | 10033 | x86_cons (expressionS *exp, int size) |
f3c180ae | 10034 | { |
62ebcb5c AM |
10035 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
10036 | ||
ee86248c JB |
10037 | intel_syntax = -intel_syntax; |
10038 | ||
3c7b9c2c | 10039 | exp->X_md = 0; |
4fa24527 | 10040 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
10041 | { |
10042 | /* Handle @GOTOFF and the like in an expression. */ | |
10043 | char *save; | |
10044 | char *gotfree_input_line; | |
4a57f2cf | 10045 | int adjust = 0; |
f3c180ae AM |
10046 | |
10047 | save = input_line_pointer; | |
d258b828 | 10048 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
10049 | if (gotfree_input_line) |
10050 | input_line_pointer = gotfree_input_line; | |
10051 | ||
10052 | expression (exp); | |
10053 | ||
10054 | if (gotfree_input_line) | |
10055 | { | |
10056 | /* expression () has merrily parsed up to the end of line, | |
10057 | or a comma - in the wrong buffer. Transfer how far | |
10058 | input_line_pointer has moved to the right buffer. */ | |
10059 | input_line_pointer = (save | |
10060 | + (input_line_pointer - gotfree_input_line) | |
10061 | + adjust); | |
10062 | free (gotfree_input_line); | |
3992d3b7 AM |
10063 | if (exp->X_op == O_constant |
10064 | || exp->X_op == O_absent | |
10065 | || exp->X_op == O_illegal | |
0398aac5 | 10066 | || exp->X_op == O_register |
3992d3b7 AM |
10067 | || exp->X_op == O_big) |
10068 | { | |
10069 | char c = *input_line_pointer; | |
10070 | *input_line_pointer = 0; | |
10071 | as_bad (_("missing or invalid expression `%s'"), save); | |
10072 | *input_line_pointer = c; | |
10073 | } | |
b9519cfe L |
10074 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
10075 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
10076 | && exp->X_op != O_symbol) | |
10077 | { | |
10078 | char c = *input_line_pointer; | |
10079 | *input_line_pointer = 0; | |
10080 | as_bad (_("invalid PLT expression `%s'"), save); | |
10081 | *input_line_pointer = c; | |
10082 | } | |
f3c180ae AM |
10083 | } |
10084 | } | |
10085 | else | |
10086 | expression (exp); | |
ee86248c JB |
10087 | |
10088 | intel_syntax = -intel_syntax; | |
10089 | ||
10090 | if (intel_syntax) | |
10091 | i386_intel_simplify (exp); | |
62ebcb5c AM |
10092 | |
10093 | return got_reloc; | |
f3c180ae | 10094 | } |
f3c180ae | 10095 | |
9f32dd5b L |
10096 | static void |
10097 | signed_cons (int size) | |
6482c264 | 10098 | { |
d182319b JB |
10099 | if (flag_code == CODE_64BIT) |
10100 | cons_sign = 1; | |
10101 | cons (size); | |
10102 | cons_sign = -1; | |
6482c264 NC |
10103 | } |
10104 | ||
d182319b | 10105 | #ifdef TE_PE |
6482c264 | 10106 | static void |
7016a5d5 | 10107 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
10108 | { |
10109 | expressionS exp; | |
10110 | ||
10111 | do | |
10112 | { | |
10113 | expression (&exp); | |
10114 | if (exp.X_op == O_symbol) | |
10115 | exp.X_op = O_secrel; | |
10116 | ||
10117 | emit_expr (&exp, 4); | |
10118 | } | |
10119 | while (*input_line_pointer++ == ','); | |
10120 | ||
10121 | input_line_pointer--; | |
10122 | demand_empty_rest_of_line (); | |
10123 | } | |
6482c264 NC |
10124 | #endif |
10125 | ||
43234a1e L |
10126 | /* Handle Vector operations. */ |
10127 | ||
10128 | static char * | |
10129 | check_VecOperations (char *op_string, char *op_end) | |
10130 | { | |
10131 | const reg_entry *mask; | |
10132 | const char *saved; | |
10133 | char *end_op; | |
10134 | ||
10135 | while (*op_string | |
10136 | && (op_end == NULL || op_string < op_end)) | |
10137 | { | |
10138 | saved = op_string; | |
10139 | if (*op_string == '{') | |
10140 | { | |
10141 | op_string++; | |
10142 | ||
10143 | /* Check broadcasts. */ | |
10144 | if (strncmp (op_string, "1to", 3) == 0) | |
10145 | { | |
10146 | int bcst_type; | |
10147 | ||
10148 | if (i.broadcast) | |
10149 | goto duplicated_vec_op; | |
10150 | ||
10151 | op_string += 3; | |
10152 | if (*op_string == '8') | |
8e6e0792 | 10153 | bcst_type = 8; |
b28d1bda | 10154 | else if (*op_string == '4') |
8e6e0792 | 10155 | bcst_type = 4; |
b28d1bda | 10156 | else if (*op_string == '2') |
8e6e0792 | 10157 | bcst_type = 2; |
43234a1e L |
10158 | else if (*op_string == '1' |
10159 | && *(op_string+1) == '6') | |
10160 | { | |
8e6e0792 | 10161 | bcst_type = 16; |
43234a1e L |
10162 | op_string++; |
10163 | } | |
10164 | else | |
10165 | { | |
10166 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
10167 | return NULL; | |
10168 | } | |
10169 | op_string++; | |
10170 | ||
10171 | broadcast_op.type = bcst_type; | |
10172 | broadcast_op.operand = this_operand; | |
1f75763a | 10173 | broadcast_op.bytes = 0; |
43234a1e L |
10174 | i.broadcast = &broadcast_op; |
10175 | } | |
10176 | /* Check masking operation. */ | |
10177 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
10178 | { | |
10179 | /* k0 can't be used for write mask. */ | |
f74a6307 | 10180 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 10181 | { |
6d2cd6b2 JB |
10182 | as_bad (_("`%s%s' can't be used for write mask"), |
10183 | register_prefix, mask->reg_name); | |
43234a1e L |
10184 | return NULL; |
10185 | } | |
10186 | ||
10187 | if (!i.mask) | |
10188 | { | |
10189 | mask_op.mask = mask; | |
10190 | mask_op.zeroing = 0; | |
10191 | mask_op.operand = this_operand; | |
10192 | i.mask = &mask_op; | |
10193 | } | |
10194 | else | |
10195 | { | |
10196 | if (i.mask->mask) | |
10197 | goto duplicated_vec_op; | |
10198 | ||
10199 | i.mask->mask = mask; | |
10200 | ||
10201 | /* Only "{z}" is allowed here. No need to check | |
10202 | zeroing mask explicitly. */ | |
10203 | if (i.mask->operand != this_operand) | |
10204 | { | |
10205 | as_bad (_("invalid write mask `%s'"), saved); | |
10206 | return NULL; | |
10207 | } | |
10208 | } | |
10209 | ||
10210 | op_string = end_op; | |
10211 | } | |
10212 | /* Check zeroing-flag for masking operation. */ | |
10213 | else if (*op_string == 'z') | |
10214 | { | |
10215 | if (!i.mask) | |
10216 | { | |
10217 | mask_op.mask = NULL; | |
10218 | mask_op.zeroing = 1; | |
10219 | mask_op.operand = this_operand; | |
10220 | i.mask = &mask_op; | |
10221 | } | |
10222 | else | |
10223 | { | |
10224 | if (i.mask->zeroing) | |
10225 | { | |
10226 | duplicated_vec_op: | |
10227 | as_bad (_("duplicated `%s'"), saved); | |
10228 | return NULL; | |
10229 | } | |
10230 | ||
10231 | i.mask->zeroing = 1; | |
10232 | ||
10233 | /* Only "{%k}" is allowed here. No need to check mask | |
10234 | register explicitly. */ | |
10235 | if (i.mask->operand != this_operand) | |
10236 | { | |
10237 | as_bad (_("invalid zeroing-masking `%s'"), | |
10238 | saved); | |
10239 | return NULL; | |
10240 | } | |
10241 | } | |
10242 | ||
10243 | op_string++; | |
10244 | } | |
10245 | else | |
10246 | goto unknown_vec_op; | |
10247 | ||
10248 | if (*op_string != '}') | |
10249 | { | |
10250 | as_bad (_("missing `}' in `%s'"), saved); | |
10251 | return NULL; | |
10252 | } | |
10253 | op_string++; | |
0ba3a731 L |
10254 | |
10255 | /* Strip whitespace since the addition of pseudo prefixes | |
10256 | changed how the scrubber treats '{'. */ | |
10257 | if (is_space_char (*op_string)) | |
10258 | ++op_string; | |
10259 | ||
43234a1e L |
10260 | continue; |
10261 | } | |
10262 | unknown_vec_op: | |
10263 | /* We don't know this one. */ | |
10264 | as_bad (_("unknown vector operation: `%s'"), saved); | |
10265 | return NULL; | |
10266 | } | |
10267 | ||
6d2cd6b2 JB |
10268 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
10269 | { | |
10270 | as_bad (_("zeroing-masking only allowed with write mask")); | |
10271 | return NULL; | |
10272 | } | |
10273 | ||
43234a1e L |
10274 | return op_string; |
10275 | } | |
10276 | ||
252b5132 | 10277 | static int |
70e41ade | 10278 | i386_immediate (char *imm_start) |
252b5132 RH |
10279 | { |
10280 | char *save_input_line_pointer; | |
f3c180ae | 10281 | char *gotfree_input_line; |
252b5132 | 10282 | segT exp_seg = 0; |
47926f60 | 10283 | expressionS *exp; |
40fb9820 L |
10284 | i386_operand_type types; |
10285 | ||
0dfbf9d7 | 10286 | operand_type_set (&types, ~0); |
252b5132 RH |
10287 | |
10288 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
10289 | { | |
31b2323c L |
10290 | as_bad (_("at most %d immediate operands are allowed"), |
10291 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
10292 | return 0; |
10293 | } | |
10294 | ||
10295 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 10296 | i.op[this_operand].imms = exp; |
252b5132 RH |
10297 | |
10298 | if (is_space_char (*imm_start)) | |
10299 | ++imm_start; | |
10300 | ||
10301 | save_input_line_pointer = input_line_pointer; | |
10302 | input_line_pointer = imm_start; | |
10303 | ||
d258b828 | 10304 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10305 | if (gotfree_input_line) |
10306 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
10307 | |
10308 | exp_seg = expression (exp); | |
10309 | ||
83183c0c | 10310 | SKIP_WHITESPACE (); |
43234a1e L |
10311 | |
10312 | /* Handle vector operations. */ | |
10313 | if (*input_line_pointer == '{') | |
10314 | { | |
10315 | input_line_pointer = check_VecOperations (input_line_pointer, | |
10316 | NULL); | |
10317 | if (input_line_pointer == NULL) | |
10318 | return 0; | |
10319 | } | |
10320 | ||
252b5132 | 10321 | if (*input_line_pointer) |
f3c180ae | 10322 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
10323 | |
10324 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 10325 | if (gotfree_input_line) |
ee86248c JB |
10326 | { |
10327 | free (gotfree_input_line); | |
10328 | ||
10329 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10330 | exp->X_op = O_illegal; | |
10331 | } | |
10332 | ||
10333 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
10334 | } | |
252b5132 | 10335 | |
ee86248c JB |
10336 | static int |
10337 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10338 | i386_operand_type types, const char *imm_start) | |
10339 | { | |
10340 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 10341 | { |
313c53d1 L |
10342 | if (imm_start) |
10343 | as_bad (_("missing or invalid immediate expression `%s'"), | |
10344 | imm_start); | |
3992d3b7 | 10345 | return 0; |
252b5132 | 10346 | } |
3e73aa7c | 10347 | else if (exp->X_op == O_constant) |
252b5132 | 10348 | { |
47926f60 | 10349 | /* Size it properly later. */ |
40fb9820 | 10350 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
10351 | /* If not 64bit, sign extend val. */ |
10352 | if (flag_code != CODE_64BIT | |
4eed87de AM |
10353 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
10354 | exp->X_add_number | |
10355 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 10356 | } |
4c63da97 | 10357 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 10358 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 10359 | && exp_seg != absolute_section |
47926f60 | 10360 | && exp_seg != text_section |
24eab124 AM |
10361 | && exp_seg != data_section |
10362 | && exp_seg != bss_section | |
10363 | && exp_seg != undefined_section | |
f86103b7 | 10364 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 10365 | { |
d0b47220 | 10366 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
10367 | return 0; |
10368 | } | |
10369 | #endif | |
a841bdf5 | 10370 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 10371 | { |
313c53d1 L |
10372 | if (imm_start) |
10373 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
10374 | return 0; |
10375 | } | |
252b5132 RH |
10376 | else |
10377 | { | |
10378 | /* This is an address. The size of the address will be | |
24eab124 | 10379 | determined later, depending on destination register, |
3e73aa7c | 10380 | suffix, or the default for the section. */ |
40fb9820 L |
10381 | i.types[this_operand].bitfield.imm8 = 1; |
10382 | i.types[this_operand].bitfield.imm16 = 1; | |
10383 | i.types[this_operand].bitfield.imm32 = 1; | |
10384 | i.types[this_operand].bitfield.imm32s = 1; | |
10385 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
10386 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10387 | types); | |
252b5132 RH |
10388 | } |
10389 | ||
10390 | return 1; | |
10391 | } | |
10392 | ||
551c1ca1 | 10393 | static char * |
e3bb37b5 | 10394 | i386_scale (char *scale) |
252b5132 | 10395 | { |
551c1ca1 AM |
10396 | offsetT val; |
10397 | char *save = input_line_pointer; | |
252b5132 | 10398 | |
551c1ca1 AM |
10399 | input_line_pointer = scale; |
10400 | val = get_absolute_expression (); | |
10401 | ||
10402 | switch (val) | |
252b5132 | 10403 | { |
551c1ca1 | 10404 | case 1: |
252b5132 RH |
10405 | i.log2_scale_factor = 0; |
10406 | break; | |
551c1ca1 | 10407 | case 2: |
252b5132 RH |
10408 | i.log2_scale_factor = 1; |
10409 | break; | |
551c1ca1 | 10410 | case 4: |
252b5132 RH |
10411 | i.log2_scale_factor = 2; |
10412 | break; | |
551c1ca1 | 10413 | case 8: |
252b5132 RH |
10414 | i.log2_scale_factor = 3; |
10415 | break; | |
10416 | default: | |
a724f0f4 JB |
10417 | { |
10418 | char sep = *input_line_pointer; | |
10419 | ||
10420 | *input_line_pointer = '\0'; | |
10421 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
10422 | scale); | |
10423 | *input_line_pointer = sep; | |
10424 | input_line_pointer = save; | |
10425 | return NULL; | |
10426 | } | |
252b5132 | 10427 | } |
29b0f896 | 10428 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
10429 | { |
10430 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 10431 | 1 << i.log2_scale_factor); |
252b5132 | 10432 | i.log2_scale_factor = 0; |
252b5132 | 10433 | } |
551c1ca1 AM |
10434 | scale = input_line_pointer; |
10435 | input_line_pointer = save; | |
10436 | return scale; | |
252b5132 RH |
10437 | } |
10438 | ||
252b5132 | 10439 | static int |
e3bb37b5 | 10440 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 10441 | { |
29b0f896 | 10442 | expressionS *exp; |
252b5132 RH |
10443 | segT exp_seg = 0; |
10444 | char *save_input_line_pointer; | |
f3c180ae | 10445 | char *gotfree_input_line; |
40fb9820 L |
10446 | int override; |
10447 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 10448 | int ret; |
252b5132 | 10449 | |
31b2323c L |
10450 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
10451 | { | |
10452 | as_bad (_("at most %d displacement operands are allowed"), | |
10453 | MAX_MEMORY_OPERANDS); | |
10454 | return 0; | |
10455 | } | |
10456 | ||
0dfbf9d7 | 10457 | operand_type_set (&bigdisp, 0); |
6f2f06be | 10458 | if (i.jumpabsolute |
48bcea9f | 10459 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
10460 | || (current_templates->start->opcode_modifier.jump != JUMP |
10461 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 10462 | { |
48bcea9f | 10463 | i386_addressing_mode (); |
e05278af | 10464 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
10465 | if (flag_code == CODE_64BIT) |
10466 | { | |
10467 | if (!override) | |
10468 | { | |
10469 | bigdisp.bitfield.disp32s = 1; | |
10470 | bigdisp.bitfield.disp64 = 1; | |
10471 | } | |
48bcea9f JB |
10472 | else |
10473 | bigdisp.bitfield.disp32 = 1; | |
40fb9820 L |
10474 | } |
10475 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 10476 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
10477 | else |
10478 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
10479 | } |
10480 | else | |
10481 | { | |
376cd056 JB |
10482 | /* For PC-relative branches, the width of the displacement may be |
10483 | dependent upon data size, but is never dependent upon address size. | |
10484 | Also make sure to not unintentionally match against a non-PC-relative | |
10485 | branch template. */ | |
10486 | static templates aux_templates; | |
10487 | const insn_template *t = current_templates->start; | |
10488 | bfd_boolean has_intel64 = FALSE; | |
10489 | ||
10490 | aux_templates.start = t; | |
10491 | while (++t < current_templates->end) | |
10492 | { | |
10493 | if (t->opcode_modifier.jump | |
10494 | != current_templates->start->opcode_modifier.jump) | |
10495 | break; | |
4b5aaf5f | 10496 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
376cd056 JB |
10497 | has_intel64 = TRUE; |
10498 | } | |
10499 | if (t < current_templates->end) | |
10500 | { | |
10501 | aux_templates.end = t; | |
10502 | current_templates = &aux_templates; | |
10503 | } | |
10504 | ||
e05278af | 10505 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
10506 | if (flag_code == CODE_64BIT) |
10507 | { | |
376cd056 JB |
10508 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
10509 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
10510 | bigdisp.bitfield.disp16 = 1; |
10511 | else | |
48bcea9f | 10512 | bigdisp.bitfield.disp32s = 1; |
40fb9820 L |
10513 | } |
10514 | else | |
e05278af JB |
10515 | { |
10516 | if (!override) | |
10517 | override = (i.suffix == (flag_code != CODE_16BIT | |
10518 | ? WORD_MNEM_SUFFIX | |
10519 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
10520 | bigdisp.bitfield.disp32 = 1; |
10521 | if ((flag_code == CODE_16BIT) ^ override) | |
10522 | { | |
10523 | bigdisp.bitfield.disp32 = 0; | |
10524 | bigdisp.bitfield.disp16 = 1; | |
10525 | } | |
e05278af | 10526 | } |
e05278af | 10527 | } |
c6fb90c8 L |
10528 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10529 | bigdisp); | |
252b5132 RH |
10530 | |
10531 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 10532 | i.op[this_operand].disps = exp; |
252b5132 RH |
10533 | i.disp_operands++; |
10534 | save_input_line_pointer = input_line_pointer; | |
10535 | input_line_pointer = disp_start; | |
10536 | END_STRING_AND_SAVE (disp_end); | |
10537 | ||
10538 | #ifndef GCC_ASM_O_HACK | |
10539 | #define GCC_ASM_O_HACK 0 | |
10540 | #endif | |
10541 | #if GCC_ASM_O_HACK | |
10542 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 10543 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 10544 | && displacement_string_end[-1] == '+') |
252b5132 RH |
10545 | { |
10546 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
10547 | constraint within gcc asm statements. |
10548 | For instance: | |
10549 | ||
10550 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
10551 | __asm__ __volatile__ ( \ | |
10552 | "movw %w2,%0\n\t" \ | |
10553 | "movw %w1,2+%0\n\t" \ | |
10554 | "rorl $16,%1\n\t" \ | |
10555 | "movb %b1,4+%0\n\t" \ | |
10556 | "movb %4,5+%0\n\t" \ | |
10557 | "movb $0,6+%0\n\t" \ | |
10558 | "movb %h1,7+%0\n\t" \ | |
10559 | "rorl $16,%1" \ | |
10560 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
10561 | ||
10562 | This works great except that the output assembler ends | |
10563 | up looking a bit weird if it turns out that there is | |
10564 | no offset. You end up producing code that looks like: | |
10565 | ||
10566 | #APP | |
10567 | movw $235,(%eax) | |
10568 | movw %dx,2+(%eax) | |
10569 | rorl $16,%edx | |
10570 | movb %dl,4+(%eax) | |
10571 | movb $137,5+(%eax) | |
10572 | movb $0,6+(%eax) | |
10573 | movb %dh,7+(%eax) | |
10574 | rorl $16,%edx | |
10575 | #NO_APP | |
10576 | ||
47926f60 | 10577 | So here we provide the missing zero. */ |
24eab124 AM |
10578 | |
10579 | *displacement_string_end = '0'; | |
252b5132 RH |
10580 | } |
10581 | #endif | |
d258b828 | 10582 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10583 | if (gotfree_input_line) |
10584 | input_line_pointer = gotfree_input_line; | |
252b5132 | 10585 | |
24eab124 | 10586 | exp_seg = expression (exp); |
252b5132 | 10587 | |
636c26b0 AM |
10588 | SKIP_WHITESPACE (); |
10589 | if (*input_line_pointer) | |
10590 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
10591 | #if GCC_ASM_O_HACK | |
10592 | RESTORE_END_STRING (disp_end + 1); | |
10593 | #endif | |
636c26b0 | 10594 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 10595 | if (gotfree_input_line) |
ee86248c JB |
10596 | { |
10597 | free (gotfree_input_line); | |
10598 | ||
10599 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10600 | exp->X_op = O_illegal; | |
10601 | } | |
10602 | ||
10603 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
10604 | ||
10605 | RESTORE_END_STRING (disp_end); | |
10606 | ||
10607 | return ret; | |
10608 | } | |
10609 | ||
10610 | static int | |
10611 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10612 | i386_operand_type types, const char *disp_start) | |
10613 | { | |
10614 | i386_operand_type bigdisp; | |
10615 | int ret = 1; | |
636c26b0 | 10616 | |
24eab124 AM |
10617 | /* We do this to make sure that the section symbol is in |
10618 | the symbol table. We will ultimately change the relocation | |
47926f60 | 10619 | to be relative to the beginning of the section. */ |
1ae12ab7 | 10620 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
10621 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
10622 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 10623 | { |
636c26b0 | 10624 | if (exp->X_op != O_symbol) |
3992d3b7 | 10625 | goto inv_disp; |
636c26b0 | 10626 | |
e5cb08ac | 10627 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
10628 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
10629 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 10630 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
10631 | exp->X_op = O_subtract; |
10632 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 10633 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 10634 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
10635 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
10636 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 10637 | else |
29b0f896 | 10638 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 10639 | } |
252b5132 | 10640 | |
3992d3b7 AM |
10641 | else if (exp->X_op == O_absent |
10642 | || exp->X_op == O_illegal | |
ee86248c | 10643 | || exp->X_op == O_big) |
2daf4fd8 | 10644 | { |
3992d3b7 AM |
10645 | inv_disp: |
10646 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 10647 | disp_start); |
3992d3b7 | 10648 | ret = 0; |
2daf4fd8 AM |
10649 | } |
10650 | ||
0e1147d9 L |
10651 | else if (flag_code == CODE_64BIT |
10652 | && !i.prefix[ADDR_PREFIX] | |
10653 | && exp->X_op == O_constant) | |
10654 | { | |
10655 | /* Since displacement is signed extended to 64bit, don't allow | |
10656 | disp32 and turn off disp32s if they are out of range. */ | |
10657 | i.types[this_operand].bitfield.disp32 = 0; | |
10658 | if (!fits_in_signed_long (exp->X_add_number)) | |
10659 | { | |
10660 | i.types[this_operand].bitfield.disp32s = 0; | |
10661 | if (i.types[this_operand].bitfield.baseindex) | |
10662 | { | |
10663 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
10664 | (long) exp->X_add_number); | |
10665 | ret = 0; | |
10666 | } | |
10667 | } | |
10668 | } | |
10669 | ||
4c63da97 | 10670 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
10671 | else if (exp->X_op != O_constant |
10672 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
10673 | && exp_seg != absolute_section | |
10674 | && exp_seg != text_section | |
10675 | && exp_seg != data_section | |
10676 | && exp_seg != bss_section | |
10677 | && exp_seg != undefined_section | |
10678 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 10679 | { |
d0b47220 | 10680 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 10681 | ret = 0; |
24eab124 | 10682 | } |
252b5132 | 10683 | #endif |
3956db08 | 10684 | |
48bcea9f JB |
10685 | if (current_templates->start->opcode_modifier.jump == JUMP_BYTE |
10686 | /* Constants get taken care of by optimize_disp(). */ | |
10687 | && exp->X_op != O_constant) | |
10688 | i.types[this_operand].bitfield.disp8 = 1; | |
10689 | ||
40fb9820 L |
10690 | /* Check if this is a displacement only operand. */ |
10691 | bigdisp = i.types[this_operand]; | |
10692 | bigdisp.bitfield.disp8 = 0; | |
10693 | bigdisp.bitfield.disp16 = 0; | |
10694 | bigdisp.bitfield.disp32 = 0; | |
10695 | bigdisp.bitfield.disp32s = 0; | |
10696 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 10697 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
10698 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10699 | types); | |
3956db08 | 10700 | |
3992d3b7 | 10701 | return ret; |
252b5132 RH |
10702 | } |
10703 | ||
2abc2bec JB |
10704 | /* Return the active addressing mode, taking address override and |
10705 | registers forming the address into consideration. Update the | |
10706 | address override prefix if necessary. */ | |
47926f60 | 10707 | |
2abc2bec JB |
10708 | static enum flag_code |
10709 | i386_addressing_mode (void) | |
252b5132 | 10710 | { |
be05d201 L |
10711 | enum flag_code addr_mode; |
10712 | ||
10713 | if (i.prefix[ADDR_PREFIX]) | |
10714 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 JB |
10715 | else if (flag_code == CODE_16BIT |
10716 | && current_templates->start->cpu_flags.bitfield.cpumpx | |
10717 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic | |
10718 | from md_assemble() by "is not a valid base/index expression" | |
10719 | when there is a base and/or index. */ | |
10720 | && !i.types[this_operand].bitfield.baseindex) | |
10721 | { | |
10722 | /* MPX insn memory operands with neither base nor index must be forced | |
10723 | to use 32-bit addressing in 16-bit mode. */ | |
10724 | addr_mode = CODE_32BIT; | |
10725 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
10726 | ++i.prefixes; | |
10727 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
10728 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
10729 | } | |
be05d201 L |
10730 | else |
10731 | { | |
10732 | addr_mode = flag_code; | |
10733 | ||
24eab124 | 10734 | #if INFER_ADDR_PREFIX |
be05d201 L |
10735 | if (i.mem_operands == 0) |
10736 | { | |
10737 | /* Infer address prefix from the first memory operand. */ | |
10738 | const reg_entry *addr_reg = i.base_reg; | |
10739 | ||
10740 | if (addr_reg == NULL) | |
10741 | addr_reg = i.index_reg; | |
eecb386c | 10742 | |
be05d201 L |
10743 | if (addr_reg) |
10744 | { | |
e968fc9b | 10745 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
10746 | addr_mode = CODE_32BIT; |
10747 | else if (flag_code != CODE_64BIT | |
dc821c5f | 10748 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
10749 | addr_mode = CODE_16BIT; |
10750 | ||
10751 | if (addr_mode != flag_code) | |
10752 | { | |
10753 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
10754 | i.prefixes += 1; | |
10755 | /* Change the size of any displacement too. At most one | |
10756 | of Disp16 or Disp32 is set. | |
10757 | FIXME. There doesn't seem to be any real need for | |
10758 | separate Disp16 and Disp32 flags. The same goes for | |
10759 | Imm16 and Imm32. Removing them would probably clean | |
10760 | up the code quite a lot. */ | |
10761 | if (flag_code != CODE_64BIT | |
10762 | && (i.types[this_operand].bitfield.disp16 | |
10763 | || i.types[this_operand].bitfield.disp32)) | |
10764 | i.types[this_operand] | |
10765 | = operand_type_xor (i.types[this_operand], disp16_32); | |
10766 | } | |
10767 | } | |
10768 | } | |
24eab124 | 10769 | #endif |
be05d201 L |
10770 | } |
10771 | ||
2abc2bec JB |
10772 | return addr_mode; |
10773 | } | |
10774 | ||
10775 | /* Make sure the memory operand we've been dealt is valid. | |
10776 | Return 1 on success, 0 on a failure. */ | |
10777 | ||
10778 | static int | |
10779 | i386_index_check (const char *operand_string) | |
10780 | { | |
10781 | const char *kind = "base/index"; | |
10782 | enum flag_code addr_mode = i386_addressing_mode (); | |
10783 | ||
fc0763e6 | 10784 | if (current_templates->start->opcode_modifier.isstring |
c3949f43 | 10785 | && !current_templates->start->cpu_flags.bitfield.cpupadlock |
fc0763e6 JB |
10786 | && (current_templates->end[-1].opcode_modifier.isstring |
10787 | || i.mem_operands)) | |
10788 | { | |
10789 | /* Memory operands of string insns are special in that they only allow | |
10790 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
10791 | const reg_entry *expected_reg; |
10792 | static const char *di_si[][2] = | |
10793 | { | |
10794 | { "esi", "edi" }, | |
10795 | { "si", "di" }, | |
10796 | { "rsi", "rdi" } | |
10797 | }; | |
10798 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
10799 | |
10800 | kind = "string address"; | |
10801 | ||
8325cc63 | 10802 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 | 10803 | { |
51c8edf6 JB |
10804 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
10805 | - IS_STRING_ES_OP0; | |
10806 | int op = 0; | |
fc0763e6 | 10807 | |
51c8edf6 | 10808 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
fc0763e6 JB |
10809 | || ((!i.mem_operands != !intel_syntax) |
10810 | && current_templates->end[-1].operand_types[1] | |
10811 | .bitfield.baseindex)) | |
51c8edf6 JB |
10812 | op = 1; |
10813 | expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
10814 | } |
10815 | else | |
be05d201 | 10816 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 10817 | |
be05d201 L |
10818 | if (i.base_reg != expected_reg |
10819 | || i.index_reg | |
fc0763e6 | 10820 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 10821 | { |
be05d201 L |
10822 | /* The second memory operand must have the same size as |
10823 | the first one. */ | |
10824 | if (i.mem_operands | |
10825 | && i.base_reg | |
10826 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 10827 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 10828 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
10829 | ? i.base_reg->reg_type.bitfield.dword |
10830 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
10831 | goto bad_address; |
10832 | ||
fc0763e6 JB |
10833 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
10834 | operand_string, | |
10835 | intel_syntax ? '[' : '(', | |
10836 | register_prefix, | |
be05d201 | 10837 | expected_reg->reg_name, |
fc0763e6 | 10838 | intel_syntax ? ']' : ')'); |
be05d201 | 10839 | return 1; |
fc0763e6 | 10840 | } |
be05d201 L |
10841 | else |
10842 | return 1; | |
10843 | ||
dc1e8a47 | 10844 | bad_address: |
be05d201 L |
10845 | as_bad (_("`%s' is not a valid %s expression"), |
10846 | operand_string, kind); | |
10847 | return 0; | |
3e73aa7c JH |
10848 | } |
10849 | else | |
10850 | { | |
be05d201 L |
10851 | if (addr_mode != CODE_16BIT) |
10852 | { | |
10853 | /* 32-bit/64-bit checks. */ | |
10854 | if ((i.base_reg | |
e968fc9b JB |
10855 | && ((addr_mode == CODE_64BIT |
10856 | ? !i.base_reg->reg_type.bitfield.qword | |
10857 | : !i.base_reg->reg_type.bitfield.dword) | |
10858 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
10859 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 10860 | || (i.index_reg |
1b54b8d7 JB |
10861 | && !i.index_reg->reg_type.bitfield.xmmword |
10862 | && !i.index_reg->reg_type.bitfield.ymmword | |
10863 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 10864 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
10865 | ? !i.index_reg->reg_type.bitfield.qword |
10866 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
10867 | || !i.index_reg->reg_type.bitfield.baseindex))) |
10868 | goto bad_address; | |
8178be5b JB |
10869 | |
10870 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
10871 | if (current_templates->start->base_opcode == 0xf30f1b | |
10872 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
10873 | { | |
10874 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 10875 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
10876 | { |
10877 | as_bad (_("`%s' cannot be used here"), operand_string); | |
10878 | return 0; | |
10879 | } | |
10880 | ||
10881 | /* bndldx and bndstx ignore their scale factor. */ | |
10882 | if (current_templates->start->base_opcode != 0xf30f1b | |
10883 | && i.log2_scale_factor) | |
10884 | as_warn (_("register scaling is being ignored here")); | |
10885 | } | |
be05d201 L |
10886 | } |
10887 | else | |
3e73aa7c | 10888 | { |
be05d201 | 10889 | /* 16-bit checks. */ |
3e73aa7c | 10890 | if ((i.base_reg |
dc821c5f | 10891 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 10892 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 10893 | || (i.index_reg |
dc821c5f | 10894 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 10895 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
10896 | || !(i.base_reg |
10897 | && i.base_reg->reg_num < 6 | |
10898 | && i.index_reg->reg_num >= 6 | |
10899 | && i.log2_scale_factor == 0)))) | |
be05d201 | 10900 | goto bad_address; |
3e73aa7c JH |
10901 | } |
10902 | } | |
be05d201 | 10903 | return 1; |
24eab124 | 10904 | } |
252b5132 | 10905 | |
43234a1e L |
10906 | /* Handle vector immediates. */ |
10907 | ||
10908 | static int | |
10909 | RC_SAE_immediate (const char *imm_start) | |
10910 | { | |
10911 | unsigned int match_found, j; | |
10912 | const char *pstr = imm_start; | |
10913 | expressionS *exp; | |
10914 | ||
10915 | if (*pstr != '{') | |
10916 | return 0; | |
10917 | ||
10918 | pstr++; | |
10919 | match_found = 0; | |
10920 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
10921 | { | |
10922 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
10923 | { | |
10924 | if (!i.rounding) | |
10925 | { | |
10926 | rc_op.type = RC_NamesTable[j].type; | |
10927 | rc_op.operand = this_operand; | |
10928 | i.rounding = &rc_op; | |
10929 | } | |
10930 | else | |
10931 | { | |
10932 | as_bad (_("duplicated `%s'"), imm_start); | |
10933 | return 0; | |
10934 | } | |
10935 | pstr += RC_NamesTable[j].len; | |
10936 | match_found = 1; | |
10937 | break; | |
10938 | } | |
10939 | } | |
10940 | if (!match_found) | |
10941 | return 0; | |
10942 | ||
10943 | if (*pstr++ != '}') | |
10944 | { | |
10945 | as_bad (_("Missing '}': '%s'"), imm_start); | |
10946 | return 0; | |
10947 | } | |
10948 | /* RC/SAE immediate string should contain nothing more. */; | |
10949 | if (*pstr != 0) | |
10950 | { | |
10951 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
10952 | return 0; | |
10953 | } | |
10954 | ||
10955 | exp = &im_expressions[i.imm_operands++]; | |
10956 | i.op[this_operand].imms = exp; | |
10957 | ||
10958 | exp->X_op = O_constant; | |
10959 | exp->X_add_number = 0; | |
10960 | exp->X_add_symbol = (symbolS *) 0; | |
10961 | exp->X_op_symbol = (symbolS *) 0; | |
10962 | ||
10963 | i.types[this_operand].bitfield.imm8 = 1; | |
10964 | return 1; | |
10965 | } | |
10966 | ||
8325cc63 JB |
10967 | /* Only string instructions can have a second memory operand, so |
10968 | reduce current_templates to just those if it contains any. */ | |
10969 | static int | |
10970 | maybe_adjust_templates (void) | |
10971 | { | |
10972 | const insn_template *t; | |
10973 | ||
10974 | gas_assert (i.mem_operands == 1); | |
10975 | ||
10976 | for (t = current_templates->start; t < current_templates->end; ++t) | |
10977 | if (t->opcode_modifier.isstring) | |
10978 | break; | |
10979 | ||
10980 | if (t < current_templates->end) | |
10981 | { | |
10982 | static templates aux_templates; | |
10983 | bfd_boolean recheck; | |
10984 | ||
10985 | aux_templates.start = t; | |
10986 | for (; t < current_templates->end; ++t) | |
10987 | if (!t->opcode_modifier.isstring) | |
10988 | break; | |
10989 | aux_templates.end = t; | |
10990 | ||
10991 | /* Determine whether to re-check the first memory operand. */ | |
10992 | recheck = (aux_templates.start != current_templates->start | |
10993 | || t != current_templates->end); | |
10994 | ||
10995 | current_templates = &aux_templates; | |
10996 | ||
10997 | if (recheck) | |
10998 | { | |
10999 | i.mem_operands = 0; | |
11000 | if (i.memop1_string != NULL | |
11001 | && i386_index_check (i.memop1_string) == 0) | |
11002 | return 0; | |
11003 | i.mem_operands = 1; | |
11004 | } | |
11005 | } | |
11006 | ||
11007 | return 1; | |
11008 | } | |
11009 | ||
fc0763e6 | 11010 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 11011 | on error. */ |
252b5132 | 11012 | |
252b5132 | 11013 | static int |
a7619375 | 11014 | i386_att_operand (char *operand_string) |
252b5132 | 11015 | { |
af6bdddf AM |
11016 | const reg_entry *r; |
11017 | char *end_op; | |
24eab124 | 11018 | char *op_string = operand_string; |
252b5132 | 11019 | |
24eab124 | 11020 | if (is_space_char (*op_string)) |
252b5132 RH |
11021 | ++op_string; |
11022 | ||
24eab124 | 11023 | /* We check for an absolute prefix (differentiating, |
47926f60 | 11024 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
11025 | if (*op_string == ABSOLUTE_PREFIX) |
11026 | { | |
11027 | ++op_string; | |
11028 | if (is_space_char (*op_string)) | |
11029 | ++op_string; | |
6f2f06be | 11030 | i.jumpabsolute = TRUE; |
24eab124 | 11031 | } |
252b5132 | 11032 | |
47926f60 | 11033 | /* Check if operand is a register. */ |
4d1bb795 | 11034 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 11035 | { |
40fb9820 L |
11036 | i386_operand_type temp; |
11037 | ||
24eab124 AM |
11038 | /* Check for a segment override by searching for ':' after a |
11039 | segment register. */ | |
11040 | op_string = end_op; | |
11041 | if (is_space_char (*op_string)) | |
11042 | ++op_string; | |
00cee14f | 11043 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 AM |
11044 | { |
11045 | switch (r->reg_num) | |
11046 | { | |
11047 | case 0: | |
11048 | i.seg[i.mem_operands] = &es; | |
11049 | break; | |
11050 | case 1: | |
11051 | i.seg[i.mem_operands] = &cs; | |
11052 | break; | |
11053 | case 2: | |
11054 | i.seg[i.mem_operands] = &ss; | |
11055 | break; | |
11056 | case 3: | |
11057 | i.seg[i.mem_operands] = &ds; | |
11058 | break; | |
11059 | case 4: | |
11060 | i.seg[i.mem_operands] = &fs; | |
11061 | break; | |
11062 | case 5: | |
11063 | i.seg[i.mem_operands] = &gs; | |
11064 | break; | |
11065 | } | |
252b5132 | 11066 | |
24eab124 | 11067 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
11068 | ++op_string; |
11069 | if (is_space_char (*op_string)) | |
24eab124 | 11070 | ++op_string; |
252b5132 | 11071 | |
24eab124 AM |
11072 | if (!is_digit_char (*op_string) |
11073 | && !is_identifier_char (*op_string) | |
11074 | && *op_string != '(' | |
11075 | && *op_string != ABSOLUTE_PREFIX) | |
11076 | { | |
11077 | as_bad (_("bad memory operand `%s'"), op_string); | |
11078 | return 0; | |
11079 | } | |
47926f60 | 11080 | /* Handle case of %es:*foo. */ |
24eab124 AM |
11081 | if (*op_string == ABSOLUTE_PREFIX) |
11082 | { | |
11083 | ++op_string; | |
11084 | if (is_space_char (*op_string)) | |
11085 | ++op_string; | |
6f2f06be | 11086 | i.jumpabsolute = TRUE; |
24eab124 AM |
11087 | } |
11088 | goto do_memory_reference; | |
11089 | } | |
43234a1e L |
11090 | |
11091 | /* Handle vector operations. */ | |
11092 | if (*op_string == '{') | |
11093 | { | |
11094 | op_string = check_VecOperations (op_string, NULL); | |
11095 | if (op_string == NULL) | |
11096 | return 0; | |
11097 | } | |
11098 | ||
24eab124 AM |
11099 | if (*op_string) |
11100 | { | |
d0b47220 | 11101 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
11102 | return 0; |
11103 | } | |
40fb9820 L |
11104 | temp = r->reg_type; |
11105 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
11106 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
11107 | temp); | |
7d5e4556 | 11108 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 11109 | i.op[this_operand].regs = r; |
24eab124 AM |
11110 | i.reg_operands++; |
11111 | } | |
af6bdddf AM |
11112 | else if (*op_string == REGISTER_PREFIX) |
11113 | { | |
11114 | as_bad (_("bad register name `%s'"), op_string); | |
11115 | return 0; | |
11116 | } | |
24eab124 | 11117 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 11118 | { |
24eab124 | 11119 | ++op_string; |
6f2f06be | 11120 | if (i.jumpabsolute) |
24eab124 | 11121 | { |
d0b47220 | 11122 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
11123 | return 0; |
11124 | } | |
11125 | if (!i386_immediate (op_string)) | |
11126 | return 0; | |
11127 | } | |
43234a1e L |
11128 | else if (RC_SAE_immediate (operand_string)) |
11129 | { | |
11130 | /* If it is a RC or SAE immediate, do nothing. */ | |
11131 | ; | |
11132 | } | |
24eab124 AM |
11133 | else if (is_digit_char (*op_string) |
11134 | || is_identifier_char (*op_string) | |
d02603dc | 11135 | || *op_string == '"' |
e5cb08ac | 11136 | || *op_string == '(') |
24eab124 | 11137 | { |
47926f60 | 11138 | /* This is a memory reference of some sort. */ |
af6bdddf | 11139 | char *base_string; |
252b5132 | 11140 | |
47926f60 | 11141 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
11142 | char *displacement_string_start; |
11143 | char *displacement_string_end; | |
43234a1e | 11144 | char *vop_start; |
252b5132 | 11145 | |
24eab124 | 11146 | do_memory_reference: |
8325cc63 JB |
11147 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
11148 | return 0; | |
24eab124 | 11149 | if ((i.mem_operands == 1 |
40fb9820 | 11150 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
11151 | || i.mem_operands == 2) |
11152 | { | |
11153 | as_bad (_("too many memory references for `%s'"), | |
11154 | current_templates->start->name); | |
11155 | return 0; | |
11156 | } | |
252b5132 | 11157 | |
24eab124 AM |
11158 | /* Check for base index form. We detect the base index form by |
11159 | looking for an ')' at the end of the operand, searching | |
11160 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
11161 | after the '('. */ | |
af6bdddf | 11162 | base_string = op_string + strlen (op_string); |
c3332e24 | 11163 | |
43234a1e L |
11164 | /* Handle vector operations. */ |
11165 | vop_start = strchr (op_string, '{'); | |
11166 | if (vop_start && vop_start < base_string) | |
11167 | { | |
11168 | if (check_VecOperations (vop_start, base_string) == NULL) | |
11169 | return 0; | |
11170 | base_string = vop_start; | |
11171 | } | |
11172 | ||
af6bdddf AM |
11173 | --base_string; |
11174 | if (is_space_char (*base_string)) | |
11175 | --base_string; | |
252b5132 | 11176 | |
47926f60 | 11177 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
11178 | displacement_string_start = op_string; |
11179 | displacement_string_end = base_string + 1; | |
252b5132 | 11180 | |
24eab124 AM |
11181 | if (*base_string == ')') |
11182 | { | |
af6bdddf | 11183 | char *temp_string; |
24eab124 AM |
11184 | unsigned int parens_balanced = 1; |
11185 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 11186 | equal, so this loop will not be infinite. */ |
24eab124 AM |
11187 | do |
11188 | { | |
11189 | base_string--; | |
11190 | if (*base_string == ')') | |
11191 | parens_balanced++; | |
11192 | if (*base_string == '(') | |
11193 | parens_balanced--; | |
11194 | } | |
11195 | while (parens_balanced); | |
c3332e24 | 11196 | |
af6bdddf | 11197 | temp_string = base_string; |
c3332e24 | 11198 | |
24eab124 | 11199 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
11200 | ++base_string; |
11201 | if (is_space_char (*base_string)) | |
24eab124 | 11202 | ++base_string; |
252b5132 | 11203 | |
af6bdddf | 11204 | if (*base_string == ',' |
4eed87de AM |
11205 | || ((i.base_reg = parse_register (base_string, &end_op)) |
11206 | != NULL)) | |
252b5132 | 11207 | { |
af6bdddf | 11208 | displacement_string_end = temp_string; |
252b5132 | 11209 | |
40fb9820 | 11210 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 11211 | |
af6bdddf | 11212 | if (i.base_reg) |
24eab124 | 11213 | { |
24eab124 AM |
11214 | base_string = end_op; |
11215 | if (is_space_char (*base_string)) | |
11216 | ++base_string; | |
af6bdddf AM |
11217 | } |
11218 | ||
11219 | /* There may be an index reg or scale factor here. */ | |
11220 | if (*base_string == ',') | |
11221 | { | |
11222 | ++base_string; | |
11223 | if (is_space_char (*base_string)) | |
11224 | ++base_string; | |
11225 | ||
4eed87de AM |
11226 | if ((i.index_reg = parse_register (base_string, &end_op)) |
11227 | != NULL) | |
24eab124 | 11228 | { |
af6bdddf | 11229 | base_string = end_op; |
24eab124 AM |
11230 | if (is_space_char (*base_string)) |
11231 | ++base_string; | |
af6bdddf AM |
11232 | if (*base_string == ',') |
11233 | { | |
11234 | ++base_string; | |
11235 | if (is_space_char (*base_string)) | |
11236 | ++base_string; | |
11237 | } | |
e5cb08ac | 11238 | else if (*base_string != ')') |
af6bdddf | 11239 | { |
4eed87de AM |
11240 | as_bad (_("expecting `,' or `)' " |
11241 | "after index register in `%s'"), | |
af6bdddf AM |
11242 | operand_string); |
11243 | return 0; | |
11244 | } | |
24eab124 | 11245 | } |
af6bdddf | 11246 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 11247 | { |
f76bf5e0 L |
11248 | end_op = strchr (base_string, ','); |
11249 | if (end_op) | |
11250 | *end_op = '\0'; | |
af6bdddf | 11251 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
11252 | return 0; |
11253 | } | |
252b5132 | 11254 | |
47926f60 | 11255 | /* Check for scale factor. */ |
551c1ca1 | 11256 | if (*base_string != ')') |
af6bdddf | 11257 | { |
551c1ca1 AM |
11258 | char *end_scale = i386_scale (base_string); |
11259 | ||
11260 | if (!end_scale) | |
af6bdddf | 11261 | return 0; |
24eab124 | 11262 | |
551c1ca1 | 11263 | base_string = end_scale; |
af6bdddf AM |
11264 | if (is_space_char (*base_string)) |
11265 | ++base_string; | |
11266 | if (*base_string != ')') | |
11267 | { | |
4eed87de AM |
11268 | as_bad (_("expecting `)' " |
11269 | "after scale factor in `%s'"), | |
af6bdddf AM |
11270 | operand_string); |
11271 | return 0; | |
11272 | } | |
11273 | } | |
11274 | else if (!i.index_reg) | |
24eab124 | 11275 | { |
4eed87de AM |
11276 | as_bad (_("expecting index register or scale factor " |
11277 | "after `,'; got '%c'"), | |
af6bdddf | 11278 | *base_string); |
24eab124 AM |
11279 | return 0; |
11280 | } | |
11281 | } | |
af6bdddf | 11282 | else if (*base_string != ')') |
24eab124 | 11283 | { |
4eed87de AM |
11284 | as_bad (_("expecting `,' or `)' " |
11285 | "after base register in `%s'"), | |
af6bdddf | 11286 | operand_string); |
24eab124 AM |
11287 | return 0; |
11288 | } | |
c3332e24 | 11289 | } |
af6bdddf | 11290 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 11291 | { |
f76bf5e0 L |
11292 | end_op = strchr (base_string, ','); |
11293 | if (end_op) | |
11294 | *end_op = '\0'; | |
af6bdddf | 11295 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 11296 | return 0; |
c3332e24 | 11297 | } |
24eab124 AM |
11298 | } |
11299 | ||
11300 | /* If there's an expression beginning the operand, parse it, | |
11301 | assuming displacement_string_start and | |
11302 | displacement_string_end are meaningful. */ | |
11303 | if (displacement_string_start != displacement_string_end) | |
11304 | { | |
11305 | if (!i386_displacement (displacement_string_start, | |
11306 | displacement_string_end)) | |
11307 | return 0; | |
11308 | } | |
11309 | ||
11310 | /* Special case for (%dx) while doing input/output op. */ | |
11311 | if (i.base_reg | |
75e5731b JB |
11312 | && i.base_reg->reg_type.bitfield.instance == RegD |
11313 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
11314 | && i.index_reg == 0 |
11315 | && i.log2_scale_factor == 0 | |
11316 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 11317 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 11318 | { |
2fb5be8d | 11319 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
11320 | return 1; |
11321 | } | |
11322 | ||
eecb386c AM |
11323 | if (i386_index_check (operand_string) == 0) |
11324 | return 0; | |
c48dadc9 | 11325 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
11326 | if (i.mem_operands == 0) |
11327 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
11328 | i.mem_operands++; |
11329 | } | |
11330 | else | |
ce8a8b2f AM |
11331 | { |
11332 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
11333 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
11334 | output_invalid (*op_string), | |
11335 | this_operand + 1, | |
11336 | op_string); | |
11337 | return 0; | |
11338 | } | |
47926f60 | 11339 | return 1; /* Normal return. */ |
252b5132 RH |
11340 | } |
11341 | \f | |
fa94de6b RM |
11342 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
11343 | that an rs_machine_dependent frag may reach. */ | |
11344 | ||
11345 | unsigned int | |
11346 | i386_frag_max_var (fragS *frag) | |
11347 | { | |
11348 | /* The only relaxable frags are for jumps. | |
11349 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
11350 | gas_assert (frag->fr_type == rs_machine_dependent); | |
11351 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
11352 | } | |
11353 | ||
b084df0b L |
11354 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11355 | static int | |
8dcea932 | 11356 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
11357 | { |
11358 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
11359 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
11360 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
11361 | return 0; | |
11362 | ||
11363 | if (!S_IS_EXTERNAL (fr_symbol)) | |
11364 | /* Symbol may be weak or local. */ | |
11365 | return !S_IS_WEAK (fr_symbol); | |
11366 | ||
8dcea932 L |
11367 | /* Global symbols with non-default visibility can't be preempted. */ |
11368 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
11369 | return 1; | |
11370 | ||
11371 | if (fr_var != NO_RELOC) | |
11372 | switch ((enum bfd_reloc_code_real) fr_var) | |
11373 | { | |
11374 | case BFD_RELOC_386_PLT32: | |
11375 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 11376 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
11377 | return 0; |
11378 | default: | |
11379 | abort (); | |
11380 | } | |
11381 | ||
b084df0b L |
11382 | /* Global symbols with default visibility in a shared library may be |
11383 | preempted by another definition. */ | |
8dcea932 | 11384 | return !shared; |
b084df0b L |
11385 | } |
11386 | #endif | |
11387 | ||
79d72f45 HL |
11388 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
11389 | Note also work for Skylake and Cascadelake. | |
11390 | --------------------------------------------------------------------- | |
11391 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
11392 | | ------ | ----------- | ------- | -------- | | |
11393 | | Jo | N | N | Y | | |
11394 | | Jno | N | N | Y | | |
11395 | | Jc/Jb | Y | N | Y | | |
11396 | | Jae/Jnb | Y | N | Y | | |
11397 | | Je/Jz | Y | Y | Y | | |
11398 | | Jne/Jnz | Y | Y | Y | | |
11399 | | Jna/Jbe | Y | N | Y | | |
11400 | | Ja/Jnbe | Y | N | Y | | |
11401 | | Js | N | N | Y | | |
11402 | | Jns | N | N | Y | | |
11403 | | Jp/Jpe | N | N | Y | | |
11404 | | Jnp/Jpo | N | N | Y | | |
11405 | | Jl/Jnge | Y | Y | Y | | |
11406 | | Jge/Jnl | Y | Y | Y | | |
11407 | | Jle/Jng | Y | Y | Y | | |
11408 | | Jg/Jnle | Y | Y | Y | | |
11409 | --------------------------------------------------------------------- */ | |
11410 | static int | |
11411 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
11412 | { | |
11413 | if (mf_cmp == mf_cmp_alu_cmp) | |
11414 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
11415 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
11416 | if (mf_cmp == mf_cmp_incdec) | |
11417 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
11418 | || mf_jcc == mf_jcc_jle); | |
11419 | if (mf_cmp == mf_cmp_test_and) | |
11420 | return 1; | |
11421 | return 0; | |
11422 | } | |
11423 | ||
e379e5f3 L |
11424 | /* Return the next non-empty frag. */ |
11425 | ||
11426 | static fragS * | |
11427 | i386_next_non_empty_frag (fragS *fragP) | |
11428 | { | |
11429 | /* There may be a frag with a ".fill 0" when there is no room in | |
11430 | the current frag for frag_grow in output_insn. */ | |
11431 | for (fragP = fragP->fr_next; | |
11432 | (fragP != NULL | |
11433 | && fragP->fr_type == rs_fill | |
11434 | && fragP->fr_fix == 0); | |
11435 | fragP = fragP->fr_next) | |
11436 | ; | |
11437 | return fragP; | |
11438 | } | |
11439 | ||
11440 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
11441 | ||
11442 | static fragS * | |
79d72f45 | 11443 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 11444 | { |
79d72f45 HL |
11445 | fragS *branch_fragP; |
11446 | if (!pad_fragP) | |
e379e5f3 L |
11447 | return NULL; |
11448 | ||
79d72f45 HL |
11449 | if (pad_fragP->fr_type == rs_machine_dependent |
11450 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
11451 | == BRANCH_PADDING)) |
11452 | { | |
79d72f45 HL |
11453 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
11454 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 11455 | return NULL; |
79d72f45 HL |
11456 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
11457 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
11458 | pad_fragP->tc_frag_data.mf_type)) | |
11459 | return branch_fragP; | |
e379e5f3 L |
11460 | } |
11461 | ||
11462 | return NULL; | |
11463 | } | |
11464 | ||
11465 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
11466 | ||
11467 | static void | |
11468 | i386_classify_machine_dependent_frag (fragS *fragP) | |
11469 | { | |
11470 | fragS *cmp_fragP; | |
11471 | fragS *pad_fragP; | |
11472 | fragS *branch_fragP; | |
11473 | fragS *next_fragP; | |
11474 | unsigned int max_prefix_length; | |
11475 | ||
11476 | if (fragP->tc_frag_data.classified) | |
11477 | return; | |
11478 | ||
11479 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
11480 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
11481 | for (next_fragP = fragP; | |
11482 | next_fragP != NULL; | |
11483 | next_fragP = next_fragP->fr_next) | |
11484 | { | |
11485 | next_fragP->tc_frag_data.classified = 1; | |
11486 | if (next_fragP->fr_type == rs_machine_dependent) | |
11487 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
11488 | { | |
11489 | case BRANCH_PADDING: | |
11490 | /* The BRANCH_PADDING frag must be followed by a branch | |
11491 | frag. */ | |
11492 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
11493 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11494 | break; | |
11495 | case FUSED_JCC_PADDING: | |
11496 | /* Check if this is a fused jcc: | |
11497 | FUSED_JCC_PADDING | |
11498 | CMP like instruction | |
11499 | BRANCH_PADDING | |
11500 | COND_JUMP | |
11501 | */ | |
11502 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
11503 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 11504 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
11505 | if (branch_fragP) |
11506 | { | |
11507 | /* The BRANCH_PADDING frag is merged with the | |
11508 | FUSED_JCC_PADDING frag. */ | |
11509 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11510 | /* CMP like instruction size. */ | |
11511 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
11512 | frag_wane (pad_fragP); | |
11513 | /* Skip to branch_fragP. */ | |
11514 | next_fragP = branch_fragP; | |
11515 | } | |
11516 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
11517 | { | |
11518 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
11519 | a fused jcc. */ | |
11520 | next_fragP->fr_subtype | |
11521 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
11522 | next_fragP->tc_frag_data.max_bytes | |
11523 | = next_fragP->tc_frag_data.max_prefix_length; | |
11524 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
11525 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
11526 | } | |
11527 | else | |
11528 | frag_wane (next_fragP); | |
11529 | break; | |
11530 | } | |
11531 | } | |
11532 | ||
11533 | /* Stop if there is no BRANCH_PREFIX. */ | |
11534 | if (!align_branch_prefix_size) | |
11535 | return; | |
11536 | ||
11537 | /* Scan for BRANCH_PREFIX. */ | |
11538 | for (; fragP != NULL; fragP = fragP->fr_next) | |
11539 | { | |
11540 | if (fragP->fr_type != rs_machine_dependent | |
11541 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11542 | != BRANCH_PREFIX)) | |
11543 | continue; | |
11544 | ||
11545 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
11546 | COND_JUMP_PREFIX. */ | |
11547 | max_prefix_length = 0; | |
11548 | for (next_fragP = fragP; | |
11549 | next_fragP != NULL; | |
11550 | next_fragP = next_fragP->fr_next) | |
11551 | { | |
11552 | if (next_fragP->fr_type == rs_fill) | |
11553 | /* Skip rs_fill frags. */ | |
11554 | continue; | |
11555 | else if (next_fragP->fr_type != rs_machine_dependent) | |
11556 | /* Stop for all other frags. */ | |
11557 | break; | |
11558 | ||
11559 | /* rs_machine_dependent frags. */ | |
11560 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11561 | == BRANCH_PREFIX) | |
11562 | { | |
11563 | /* Count BRANCH_PREFIX frags. */ | |
11564 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
11565 | { | |
11566 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
11567 | frag_wane (next_fragP); | |
11568 | } | |
11569 | else | |
11570 | max_prefix_length | |
11571 | += next_fragP->tc_frag_data.max_bytes; | |
11572 | } | |
11573 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11574 | == BRANCH_PADDING) | |
11575 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11576 | == FUSED_JCC_PADDING)) | |
11577 | { | |
11578 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
11579 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
11580 | break; | |
11581 | } | |
11582 | else | |
11583 | /* Stop for other rs_machine_dependent frags. */ | |
11584 | break; | |
11585 | } | |
11586 | ||
11587 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
11588 | ||
11589 | /* Skip to the next frag. */ | |
11590 | fragP = next_fragP; | |
11591 | } | |
11592 | } | |
11593 | ||
11594 | /* Compute padding size for | |
11595 | ||
11596 | FUSED_JCC_PADDING | |
11597 | CMP like instruction | |
11598 | BRANCH_PADDING | |
11599 | COND_JUMP/UNCOND_JUMP | |
11600 | ||
11601 | or | |
11602 | ||
11603 | BRANCH_PADDING | |
11604 | COND_JUMP/UNCOND_JUMP | |
11605 | */ | |
11606 | ||
11607 | static int | |
11608 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
11609 | { | |
11610 | unsigned int offset, size, padding_size; | |
11611 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
11612 | ||
11613 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
11614 | if (!address) | |
11615 | address = fragP->fr_address; | |
11616 | address += fragP->fr_fix; | |
11617 | ||
11618 | /* CMP like instrunction size. */ | |
11619 | size = fragP->tc_frag_data.cmp_size; | |
11620 | ||
11621 | /* The base size of the branch frag. */ | |
11622 | size += branch_fragP->fr_fix; | |
11623 | ||
11624 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
11625 | branch frag. */ | |
11626 | if (branch_fragP->fr_type == rs_machine_dependent) | |
11627 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
11628 | ||
11629 | /* Check if branch is within boundary and doesn't end at the last | |
11630 | byte. */ | |
11631 | offset = address & ((1U << align_branch_power) - 1); | |
11632 | if ((offset + size) >= (1U << align_branch_power)) | |
11633 | /* Padding needed to avoid crossing boundary. */ | |
11634 | padding_size = (1U << align_branch_power) - offset; | |
11635 | else | |
11636 | /* No padding needed. */ | |
11637 | padding_size = 0; | |
11638 | ||
11639 | /* The return value may be saved in tc_frag_data.length which is | |
11640 | unsigned byte. */ | |
11641 | if (!fits_in_unsigned_byte (padding_size)) | |
11642 | abort (); | |
11643 | ||
11644 | return padding_size; | |
11645 | } | |
11646 | ||
11647 | /* i386_generic_table_relax_frag() | |
11648 | ||
11649 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
11650 | grow/shrink padding to align branch frags. Hand others to | |
11651 | relax_frag(). */ | |
11652 | ||
11653 | long | |
11654 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
11655 | { | |
11656 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
11657 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11658 | { | |
11659 | long padding_size = i386_branch_padding_size (fragP, 0); | |
11660 | long grow = padding_size - fragP->tc_frag_data.length; | |
11661 | ||
11662 | /* When the BRANCH_PREFIX frag is used, the computed address | |
11663 | must match the actual address and there should be no padding. */ | |
11664 | if (fragP->tc_frag_data.padding_address | |
11665 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
11666 | || padding_size)) | |
11667 | abort (); | |
11668 | ||
11669 | /* Update the padding size. */ | |
11670 | if (grow) | |
11671 | fragP->tc_frag_data.length = padding_size; | |
11672 | ||
11673 | return grow; | |
11674 | } | |
11675 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11676 | { | |
11677 | fragS *padding_fragP, *next_fragP; | |
11678 | long padding_size, left_size, last_size; | |
11679 | ||
11680 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11681 | if (!padding_fragP) | |
11682 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
11683 | return (fragP->tc_frag_data.length | |
11684 | - fragP->tc_frag_data.last_length); | |
11685 | ||
11686 | /* Compute the relative address of the padding frag in the very | |
11687 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
11688 | if (!fragP->tc_frag_data.padding_address) | |
11689 | fragP->tc_frag_data.padding_address | |
11690 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
11691 | ||
11692 | /* First update the last length from the previous interation. */ | |
11693 | left_size = fragP->tc_frag_data.prefix_length; | |
11694 | for (next_fragP = fragP; | |
11695 | next_fragP != padding_fragP; | |
11696 | next_fragP = next_fragP->fr_next) | |
11697 | if (next_fragP->fr_type == rs_machine_dependent | |
11698 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11699 | == BRANCH_PREFIX)) | |
11700 | { | |
11701 | if (left_size) | |
11702 | { | |
11703 | int max = next_fragP->tc_frag_data.max_bytes; | |
11704 | if (max) | |
11705 | { | |
11706 | int size; | |
11707 | if (max > left_size) | |
11708 | size = left_size; | |
11709 | else | |
11710 | size = max; | |
11711 | left_size -= size; | |
11712 | next_fragP->tc_frag_data.last_length = size; | |
11713 | } | |
11714 | } | |
11715 | else | |
11716 | next_fragP->tc_frag_data.last_length = 0; | |
11717 | } | |
11718 | ||
11719 | /* Check the padding size for the padding frag. */ | |
11720 | padding_size = i386_branch_padding_size | |
11721 | (padding_fragP, (fragP->fr_address | |
11722 | + fragP->tc_frag_data.padding_address)); | |
11723 | ||
11724 | last_size = fragP->tc_frag_data.prefix_length; | |
11725 | /* Check if there is change from the last interation. */ | |
11726 | if (padding_size == last_size) | |
11727 | { | |
11728 | /* Update the expected address of the padding frag. */ | |
11729 | padding_fragP->tc_frag_data.padding_address | |
11730 | = (fragP->fr_address + padding_size | |
11731 | + fragP->tc_frag_data.padding_address); | |
11732 | return 0; | |
11733 | } | |
11734 | ||
11735 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
11736 | { | |
11737 | /* No padding if there is no sufficient room. Clear the | |
11738 | expected address of the padding frag. */ | |
11739 | padding_fragP->tc_frag_data.padding_address = 0; | |
11740 | padding_size = 0; | |
11741 | } | |
11742 | else | |
11743 | /* Store the expected address of the padding frag. */ | |
11744 | padding_fragP->tc_frag_data.padding_address | |
11745 | = (fragP->fr_address + padding_size | |
11746 | + fragP->tc_frag_data.padding_address); | |
11747 | ||
11748 | fragP->tc_frag_data.prefix_length = padding_size; | |
11749 | ||
11750 | /* Update the length for the current interation. */ | |
11751 | left_size = padding_size; | |
11752 | for (next_fragP = fragP; | |
11753 | next_fragP != padding_fragP; | |
11754 | next_fragP = next_fragP->fr_next) | |
11755 | if (next_fragP->fr_type == rs_machine_dependent | |
11756 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11757 | == BRANCH_PREFIX)) | |
11758 | { | |
11759 | if (left_size) | |
11760 | { | |
11761 | int max = next_fragP->tc_frag_data.max_bytes; | |
11762 | if (max) | |
11763 | { | |
11764 | int size; | |
11765 | if (max > left_size) | |
11766 | size = left_size; | |
11767 | else | |
11768 | size = max; | |
11769 | left_size -= size; | |
11770 | next_fragP->tc_frag_data.length = size; | |
11771 | } | |
11772 | } | |
11773 | else | |
11774 | next_fragP->tc_frag_data.length = 0; | |
11775 | } | |
11776 | ||
11777 | return (fragP->tc_frag_data.length | |
11778 | - fragP->tc_frag_data.last_length); | |
11779 | } | |
11780 | return relax_frag (segment, fragP, stretch); | |
11781 | } | |
11782 | ||
ee7fcc42 AM |
11783 | /* md_estimate_size_before_relax() |
11784 | ||
11785 | Called just before relax() for rs_machine_dependent frags. The x86 | |
11786 | assembler uses these frags to handle variable size jump | |
11787 | instructions. | |
11788 | ||
11789 | Any symbol that is now undefined will not become defined. | |
11790 | Return the correct fr_subtype in the frag. | |
11791 | Return the initial "guess for variable size of frag" to caller. | |
11792 | The guess is actually the growth beyond the fixed part. Whatever | |
11793 | we do to grow the fixed or variable part contributes to our | |
11794 | returned value. */ | |
11795 | ||
252b5132 | 11796 | int |
7016a5d5 | 11797 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 11798 | { |
e379e5f3 L |
11799 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11800 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
11801 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11802 | { | |
11803 | i386_classify_machine_dependent_frag (fragP); | |
11804 | return fragP->tc_frag_data.length; | |
11805 | } | |
11806 | ||
252b5132 | 11807 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
11808 | check for un-relaxable symbols. On an ELF system, we can't relax |
11809 | an externally visible symbol, because it may be overridden by a | |
11810 | shared library. */ | |
11811 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 11812 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11813 | || (IS_ELF |
8dcea932 L |
11814 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
11815 | fragP->fr_var)) | |
fbeb56a4 DK |
11816 | #endif |
11817 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 11818 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 11819 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
11820 | #endif |
11821 | ) | |
252b5132 | 11822 | { |
b98ef147 AM |
11823 | /* Symbol is undefined in this segment, or we need to keep a |
11824 | reloc so that weak symbols can be overridden. */ | |
11825 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 11826 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
11827 | unsigned char *opcode; |
11828 | int old_fr_fix; | |
f6af82bd | 11829 | |
ee7fcc42 | 11830 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 11831 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 11832 | else if (size == 2) |
f6af82bd | 11833 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
11834 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11835 | else if (need_plt32_p (fragP->fr_symbol)) | |
11836 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
11837 | #endif | |
f6af82bd AM |
11838 | else |
11839 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 11840 | |
ee7fcc42 AM |
11841 | old_fr_fix = fragP->fr_fix; |
11842 | opcode = (unsigned char *) fragP->fr_opcode; | |
11843 | ||
fddf5b5b | 11844 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 11845 | { |
fddf5b5b AM |
11846 | case UNCOND_JUMP: |
11847 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 11848 | opcode[0] = 0xe9; |
252b5132 | 11849 | fragP->fr_fix += size; |
062cd5e7 AS |
11850 | fix_new (fragP, old_fr_fix, size, |
11851 | fragP->fr_symbol, | |
11852 | fragP->fr_offset, 1, | |
11853 | reloc_type); | |
252b5132 RH |
11854 | break; |
11855 | ||
fddf5b5b | 11856 | case COND_JUMP86: |
412167cb AM |
11857 | if (size == 2 |
11858 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
11859 | { |
11860 | /* Negate the condition, and branch past an | |
11861 | unconditional jump. */ | |
11862 | opcode[0] ^= 1; | |
11863 | opcode[1] = 3; | |
11864 | /* Insert an unconditional jump. */ | |
11865 | opcode[2] = 0xe9; | |
11866 | /* We added two extra opcode bytes, and have a two byte | |
11867 | offset. */ | |
11868 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
11869 | fix_new (fragP, old_fr_fix + 2, 2, |
11870 | fragP->fr_symbol, | |
11871 | fragP->fr_offset, 1, | |
11872 | reloc_type); | |
fddf5b5b AM |
11873 | break; |
11874 | } | |
11875 | /* Fall through. */ | |
11876 | ||
11877 | case COND_JUMP: | |
412167cb AM |
11878 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
11879 | { | |
3e02c1cc AM |
11880 | fixS *fixP; |
11881 | ||
412167cb | 11882 | fragP->fr_fix += 1; |
3e02c1cc AM |
11883 | fixP = fix_new (fragP, old_fr_fix, 1, |
11884 | fragP->fr_symbol, | |
11885 | fragP->fr_offset, 1, | |
11886 | BFD_RELOC_8_PCREL); | |
11887 | fixP->fx_signed = 1; | |
412167cb AM |
11888 | break; |
11889 | } | |
93c2a809 | 11890 | |
24eab124 | 11891 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 11892 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 11893 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 11894 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
11895 | /* We've added an opcode byte. */ |
11896 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
11897 | fix_new (fragP, old_fr_fix + 1, size, |
11898 | fragP->fr_symbol, | |
11899 | fragP->fr_offset, 1, | |
11900 | reloc_type); | |
252b5132 | 11901 | break; |
fddf5b5b AM |
11902 | |
11903 | default: | |
11904 | BAD_CASE (fragP->fr_subtype); | |
11905 | break; | |
252b5132 RH |
11906 | } |
11907 | frag_wane (fragP); | |
ee7fcc42 | 11908 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 11909 | } |
93c2a809 | 11910 | |
93c2a809 AM |
11911 | /* Guess size depending on current relax state. Initially the relax |
11912 | state will correspond to a short jump and we return 1, because | |
11913 | the variable part of the frag (the branch offset) is one byte | |
11914 | long. However, we can relax a section more than once and in that | |
11915 | case we must either set fr_subtype back to the unrelaxed state, | |
11916 | or return the value for the appropriate branch. */ | |
11917 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
11918 | } |
11919 | ||
47926f60 KH |
11920 | /* Called after relax() is finished. |
11921 | ||
11922 | In: Address of frag. | |
11923 | fr_type == rs_machine_dependent. | |
11924 | fr_subtype is what the address relaxed to. | |
11925 | ||
11926 | Out: Any fixSs and constants are set up. | |
11927 | Caller will turn frag into a ".space 0". */ | |
11928 | ||
252b5132 | 11929 | void |
7016a5d5 TG |
11930 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
11931 | fragS *fragP) | |
252b5132 | 11932 | { |
29b0f896 | 11933 | unsigned char *opcode; |
252b5132 | 11934 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
11935 | offsetT target_address; |
11936 | offsetT opcode_address; | |
252b5132 | 11937 | unsigned int extension = 0; |
847f7ad4 | 11938 | offsetT displacement_from_opcode_start; |
252b5132 | 11939 | |
e379e5f3 L |
11940 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11941 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
11942 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11943 | { | |
11944 | /* Generate nop padding. */ | |
11945 | unsigned int size = fragP->tc_frag_data.length; | |
11946 | if (size) | |
11947 | { | |
11948 | if (size > fragP->tc_frag_data.max_bytes) | |
11949 | abort (); | |
11950 | ||
11951 | if (flag_debug) | |
11952 | { | |
11953 | const char *msg; | |
11954 | const char *branch = "branch"; | |
11955 | const char *prefix = ""; | |
11956 | fragS *padding_fragP; | |
11957 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11958 | == BRANCH_PREFIX) | |
11959 | { | |
11960 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11961 | switch (fragP->tc_frag_data.default_prefix) | |
11962 | { | |
11963 | default: | |
11964 | abort (); | |
11965 | break; | |
11966 | case CS_PREFIX_OPCODE: | |
11967 | prefix = " cs"; | |
11968 | break; | |
11969 | case DS_PREFIX_OPCODE: | |
11970 | prefix = " ds"; | |
11971 | break; | |
11972 | case ES_PREFIX_OPCODE: | |
11973 | prefix = " es"; | |
11974 | break; | |
11975 | case FS_PREFIX_OPCODE: | |
11976 | prefix = " fs"; | |
11977 | break; | |
11978 | case GS_PREFIX_OPCODE: | |
11979 | prefix = " gs"; | |
11980 | break; | |
11981 | case SS_PREFIX_OPCODE: | |
11982 | prefix = " ss"; | |
11983 | break; | |
11984 | } | |
11985 | if (padding_fragP) | |
11986 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
11987 | "%s within %d-byte boundary\n"); | |
11988 | else | |
11989 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
11990 | "align %s within %d-byte boundary\n"); | |
11991 | } | |
11992 | else | |
11993 | { | |
11994 | padding_fragP = fragP; | |
11995 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
11996 | "%s within %d-byte boundary\n"); | |
11997 | } | |
11998 | ||
11999 | if (padding_fragP) | |
12000 | switch (padding_fragP->tc_frag_data.branch_type) | |
12001 | { | |
12002 | case align_branch_jcc: | |
12003 | branch = "jcc"; | |
12004 | break; | |
12005 | case align_branch_fused: | |
12006 | branch = "fused jcc"; | |
12007 | break; | |
12008 | case align_branch_jmp: | |
12009 | branch = "jmp"; | |
12010 | break; | |
12011 | case align_branch_call: | |
12012 | branch = "call"; | |
12013 | break; | |
12014 | case align_branch_indirect: | |
12015 | branch = "indiret branch"; | |
12016 | break; | |
12017 | case align_branch_ret: | |
12018 | branch = "ret"; | |
12019 | break; | |
12020 | default: | |
12021 | break; | |
12022 | } | |
12023 | ||
12024 | fprintf (stdout, msg, | |
12025 | fragP->fr_file, fragP->fr_line, size, prefix, | |
12026 | (long long) fragP->fr_address, branch, | |
12027 | 1 << align_branch_power); | |
12028 | } | |
12029 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12030 | memset (fragP->fr_opcode, | |
12031 | fragP->tc_frag_data.default_prefix, size); | |
12032 | else | |
12033 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
12034 | size, 0); | |
12035 | fragP->fr_fix += size; | |
12036 | } | |
12037 | return; | |
12038 | } | |
12039 | ||
252b5132 RH |
12040 | opcode = (unsigned char *) fragP->fr_opcode; |
12041 | ||
47926f60 | 12042 | /* Address we want to reach in file space. */ |
252b5132 | 12043 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 12044 | |
47926f60 | 12045 | /* Address opcode resides at in file space. */ |
252b5132 RH |
12046 | opcode_address = fragP->fr_address + fragP->fr_fix; |
12047 | ||
47926f60 | 12048 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
12049 | displacement_from_opcode_start = target_address - opcode_address; |
12050 | ||
fddf5b5b | 12051 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 12052 | { |
47926f60 KH |
12053 | /* Don't have to change opcode. */ |
12054 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 12055 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
12056 | } |
12057 | else | |
12058 | { | |
12059 | if (no_cond_jump_promotion | |
12060 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
12061 | as_warn_where (fragP->fr_file, fragP->fr_line, |
12062 | _("long jump required")); | |
252b5132 | 12063 | |
fddf5b5b AM |
12064 | switch (fragP->fr_subtype) |
12065 | { | |
12066 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
12067 | extension = 4; /* 1 opcode + 4 displacement */ | |
12068 | opcode[0] = 0xe9; | |
12069 | where_to_put_displacement = &opcode[1]; | |
12070 | break; | |
252b5132 | 12071 | |
fddf5b5b AM |
12072 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
12073 | extension = 2; /* 1 opcode + 2 displacement */ | |
12074 | opcode[0] = 0xe9; | |
12075 | where_to_put_displacement = &opcode[1]; | |
12076 | break; | |
252b5132 | 12077 | |
fddf5b5b AM |
12078 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
12079 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
12080 | extension = 5; /* 2 opcode + 4 displacement */ | |
12081 | opcode[1] = opcode[0] + 0x10; | |
12082 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12083 | where_to_put_displacement = &opcode[2]; | |
12084 | break; | |
252b5132 | 12085 | |
fddf5b5b AM |
12086 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
12087 | extension = 3; /* 2 opcode + 2 displacement */ | |
12088 | opcode[1] = opcode[0] + 0x10; | |
12089 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12090 | where_to_put_displacement = &opcode[2]; | |
12091 | break; | |
252b5132 | 12092 | |
fddf5b5b AM |
12093 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
12094 | extension = 4; | |
12095 | opcode[0] ^= 1; | |
12096 | opcode[1] = 3; | |
12097 | opcode[2] = 0xe9; | |
12098 | where_to_put_displacement = &opcode[3]; | |
12099 | break; | |
12100 | ||
12101 | default: | |
12102 | BAD_CASE (fragP->fr_subtype); | |
12103 | break; | |
12104 | } | |
252b5132 | 12105 | } |
fddf5b5b | 12106 | |
7b81dfbb AJ |
12107 | /* If size if less then four we are sure that the operand fits, |
12108 | but if it's 4, then it could be that the displacement is larger | |
12109 | then -/+ 2GB. */ | |
12110 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
12111 | && object_64bit | |
12112 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
12113 | + ((addressT) 1 << 31)) |
12114 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
12115 | { |
12116 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
12117 | _("jump target out of range")); | |
12118 | /* Make us emit 0. */ | |
12119 | displacement_from_opcode_start = extension; | |
12120 | } | |
47926f60 | 12121 | /* Now put displacement after opcode. */ |
252b5132 RH |
12122 | md_number_to_chars ((char *) where_to_put_displacement, |
12123 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 12124 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
12125 | fragP->fr_fix += extension; |
12126 | } | |
12127 | \f | |
7016a5d5 | 12128 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
12129 | by our caller that we have all the info we need to fix it up. |
12130 | ||
7016a5d5 TG |
12131 | Parameter valP is the pointer to the value of the bits. |
12132 | ||
252b5132 RH |
12133 | On the 386, immediates, displacements, and data pointers are all in |
12134 | the same (little-endian) format, so we don't need to care about which | |
12135 | we are handling. */ | |
12136 | ||
94f592af | 12137 | void |
7016a5d5 | 12138 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12139 | { |
94f592af | 12140 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 12141 | valueT value = *valP; |
252b5132 | 12142 | |
f86103b7 | 12143 | #if !defined (TE_Mach) |
93382f6d AM |
12144 | if (fixP->fx_pcrel) |
12145 | { | |
12146 | switch (fixP->fx_r_type) | |
12147 | { | |
5865bb77 ILT |
12148 | default: |
12149 | break; | |
12150 | ||
d6ab8113 JB |
12151 | case BFD_RELOC_64: |
12152 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
12153 | break; | |
93382f6d | 12154 | case BFD_RELOC_32: |
ae8887b5 | 12155 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
12156 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
12157 | break; | |
12158 | case BFD_RELOC_16: | |
12159 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
12160 | break; | |
12161 | case BFD_RELOC_8: | |
12162 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
12163 | break; | |
12164 | } | |
12165 | } | |
252b5132 | 12166 | |
a161fe53 | 12167 | if (fixP->fx_addsy != NULL |
31312f95 | 12168 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 12169 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 12170 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 12171 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 12172 | && !use_rela_relocations) |
252b5132 | 12173 | { |
31312f95 AM |
12174 | /* This is a hack. There should be a better way to handle this. |
12175 | This covers for the fact that bfd_install_relocation will | |
12176 | subtract the current location (for partial_inplace, PC relative | |
12177 | relocations); see more below. */ | |
252b5132 | 12178 | #ifndef OBJ_AOUT |
718ddfc0 | 12179 | if (IS_ELF |
252b5132 RH |
12180 | #ifdef TE_PE |
12181 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
12182 | #endif | |
12183 | ) | |
12184 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12185 | #endif | |
12186 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 12187 | if (IS_ELF) |
252b5132 | 12188 | { |
6539b54b | 12189 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 12190 | |
6539b54b | 12191 | if ((sym_seg == seg |
2f66722d | 12192 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 12193 | && sym_seg != absolute_section)) |
af65af87 | 12194 | && !generic_force_reloc (fixP)) |
2f66722d AM |
12195 | { |
12196 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
12197 | bfd_install_relocation subtracts them out again. I think |
12198 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
12199 | it. FIXME. */ |
12200 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12201 | } | |
252b5132 RH |
12202 | } |
12203 | #endif | |
12204 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
12205 | /* For some reason, the PE format does not store a |
12206 | section address offset for a PC relative symbol. */ | |
12207 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 12208 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
12209 | value += md_pcrel_from (fixP); |
12210 | #endif | |
12211 | } | |
fbeb56a4 | 12212 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
12213 | if (fixP->fx_addsy != NULL |
12214 | && S_IS_WEAK (fixP->fx_addsy) | |
12215 | /* PR 16858: Do not modify weak function references. */ | |
12216 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 12217 | { |
296a8689 NC |
12218 | #if !defined (TE_PEP) |
12219 | /* For x86 PE weak function symbols are neither PC-relative | |
12220 | nor do they set S_IS_FUNCTION. So the only reliable way | |
12221 | to detect them is to check the flags of their containing | |
12222 | section. */ | |
12223 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
12224 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
12225 | ; | |
12226 | else | |
12227 | #endif | |
fbeb56a4 DK |
12228 | value -= S_GET_VALUE (fixP->fx_addsy); |
12229 | } | |
12230 | #endif | |
252b5132 RH |
12231 | |
12232 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 12233 | and we must not disappoint it. */ |
252b5132 | 12234 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12235 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
12236 | switch (fixP->fx_r_type) |
12237 | { | |
12238 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 12239 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
12240 | /* Make the jump instruction point to the address of the operand. |
12241 | At runtime we merely add the offset to the actual PLT entry. | |
12242 | NB: Subtract the offset size only for jump instructions. */ | |
12243 | if (fixP->fx_pcrel) | |
12244 | value = -4; | |
47926f60 | 12245 | break; |
31312f95 | 12246 | |
13ae64f3 JJ |
12247 | case BFD_RELOC_386_TLS_GD: |
12248 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 12249 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
12250 | case BFD_RELOC_386_TLS_IE: |
12251 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 12252 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
12253 | case BFD_RELOC_X86_64_TLSGD: |
12254 | case BFD_RELOC_X86_64_TLSLD: | |
12255 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 12256 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
12257 | value = 0; /* Fully resolved at runtime. No addend. */ |
12258 | /* Fallthrough */ | |
12259 | case BFD_RELOC_386_TLS_LE: | |
12260 | case BFD_RELOC_386_TLS_LDO_32: | |
12261 | case BFD_RELOC_386_TLS_LE_32: | |
12262 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 12263 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 12264 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 12265 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
12266 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
12267 | break; | |
12268 | ||
67a4f2b7 AO |
12269 | case BFD_RELOC_386_TLS_DESC_CALL: |
12270 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
12271 | value = 0; /* Fully resolved at runtime. No addend. */ | |
12272 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12273 | fixP->fx_done = 0; | |
12274 | return; | |
12275 | ||
47926f60 KH |
12276 | case BFD_RELOC_VTABLE_INHERIT: |
12277 | case BFD_RELOC_VTABLE_ENTRY: | |
12278 | fixP->fx_done = 0; | |
94f592af | 12279 | return; |
47926f60 KH |
12280 | |
12281 | default: | |
12282 | break; | |
12283 | } | |
12284 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 12285 | *valP = value; |
f86103b7 | 12286 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 12287 | |
3e73aa7c | 12288 | /* Are we finished with this relocation now? */ |
c6682705 | 12289 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 12290 | fixP->fx_done = 1; |
fbeb56a4 DK |
12291 | #if defined (OBJ_COFF) && defined (TE_PE) |
12292 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
12293 | { | |
12294 | fixP->fx_done = 0; | |
12295 | /* Remember value for tc_gen_reloc. */ | |
12296 | fixP->fx_addnumber = value; | |
12297 | /* Clear out the frag for now. */ | |
12298 | value = 0; | |
12299 | } | |
12300 | #endif | |
3e73aa7c JH |
12301 | else if (use_rela_relocations) |
12302 | { | |
12303 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
12304 | /* Remember value for tc_gen_reloc. */ |
12305 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
12306 | value = 0; |
12307 | } | |
f86103b7 | 12308 | |
94f592af | 12309 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 12310 | } |
252b5132 | 12311 | \f |
6d4af3c2 | 12312 | const char * |
499ac353 | 12313 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 12314 | { |
499ac353 NC |
12315 | /* This outputs the LITTLENUMs in REVERSE order; |
12316 | in accord with the bigendian 386. */ | |
12317 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
12318 | } |
12319 | \f | |
2d545b82 | 12320 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 12321 | |
252b5132 | 12322 | static char * |
e3bb37b5 | 12323 | output_invalid (int c) |
252b5132 | 12324 | { |
3882b010 | 12325 | if (ISPRINT (c)) |
f9f21a03 L |
12326 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
12327 | "'%c'", c); | |
252b5132 | 12328 | else |
f9f21a03 | 12329 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 12330 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
12331 | return output_invalid_buf; |
12332 | } | |
12333 | ||
af6bdddf | 12334 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
12335 | |
12336 | static const reg_entry * | |
4d1bb795 | 12337 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 12338 | { |
af6bdddf AM |
12339 | char *s = reg_string; |
12340 | char *p; | |
252b5132 RH |
12341 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
12342 | const reg_entry *r; | |
12343 | ||
12344 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
12345 | if (*s == REGISTER_PREFIX) | |
12346 | ++s; | |
12347 | ||
12348 | if (is_space_char (*s)) | |
12349 | ++s; | |
12350 | ||
12351 | p = reg_name_given; | |
af6bdddf | 12352 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
12353 | { |
12354 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
12355 | return (const reg_entry *) NULL; |
12356 | s++; | |
252b5132 RH |
12357 | } |
12358 | ||
6588847e DN |
12359 | /* For naked regs, make sure that we are not dealing with an identifier. |
12360 | This prevents confusing an identifier like `eax_var' with register | |
12361 | `eax'. */ | |
12362 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
12363 | return (const reg_entry *) NULL; | |
12364 | ||
af6bdddf | 12365 | *end_op = s; |
252b5132 RH |
12366 | |
12367 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
12368 | ||
5f47d35b | 12369 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 12370 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 12371 | { |
0e0eea78 JB |
12372 | if (!cpu_arch_flags.bitfield.cpu8087 |
12373 | && !cpu_arch_flags.bitfield.cpu287 | |
12374 | && !cpu_arch_flags.bitfield.cpu387) | |
12375 | return (const reg_entry *) NULL; | |
12376 | ||
5f47d35b AM |
12377 | if (is_space_char (*s)) |
12378 | ++s; | |
12379 | if (*s == '(') | |
12380 | { | |
af6bdddf | 12381 | ++s; |
5f47d35b AM |
12382 | if (is_space_char (*s)) |
12383 | ++s; | |
12384 | if (*s >= '0' && *s <= '7') | |
12385 | { | |
db557034 | 12386 | int fpr = *s - '0'; |
af6bdddf | 12387 | ++s; |
5f47d35b AM |
12388 | if (is_space_char (*s)) |
12389 | ++s; | |
12390 | if (*s == ')') | |
12391 | { | |
12392 | *end_op = s + 1; | |
1e9cc1c2 | 12393 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
12394 | know (r); |
12395 | return r + fpr; | |
5f47d35b | 12396 | } |
5f47d35b | 12397 | } |
47926f60 | 12398 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
12399 | return (const reg_entry *) NULL; |
12400 | } | |
12401 | } | |
12402 | ||
a60de03c JB |
12403 | if (r == NULL || allow_pseudo_reg) |
12404 | return r; | |
12405 | ||
0dfbf9d7 | 12406 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
12407 | return (const reg_entry *) NULL; |
12408 | ||
dc821c5f | 12409 | if ((r->reg_type.bitfield.dword |
00cee14f | 12410 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) |
4a5c67ed JB |
12411 | || r->reg_type.bitfield.class == RegCR |
12412 | || r->reg_type.bitfield.class == RegDR | |
12413 | || r->reg_type.bitfield.class == RegTR) | |
192dc9c6 JB |
12414 | && !cpu_arch_flags.bitfield.cpui386) |
12415 | return (const reg_entry *) NULL; | |
12416 | ||
3528c362 | 12417 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
12418 | return (const reg_entry *) NULL; |
12419 | ||
6e041cf4 JB |
12420 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
12421 | { | |
f74a6307 JB |
12422 | if (r->reg_type.bitfield.zmmword |
12423 | || r->reg_type.bitfield.class == RegMask) | |
6e041cf4 | 12424 | return (const reg_entry *) NULL; |
40f12533 | 12425 | |
6e041cf4 JB |
12426 | if (!cpu_arch_flags.bitfield.cpuavx) |
12427 | { | |
12428 | if (r->reg_type.bitfield.ymmword) | |
12429 | return (const reg_entry *) NULL; | |
1848e567 | 12430 | |
6e041cf4 JB |
12431 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
12432 | return (const reg_entry *) NULL; | |
12433 | } | |
12434 | } | |
43234a1e | 12435 | |
f74a6307 | 12436 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
1adf7f56 JB |
12437 | return (const reg_entry *) NULL; |
12438 | ||
db51cc60 | 12439 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 12440 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
12441 | return (const reg_entry *) NULL; |
12442 | ||
1d3f8286 JB |
12443 | /* Upper 16 vector registers are only available with VREX in 64bit |
12444 | mode, and require EVEX encoding. */ | |
12445 | if (r->reg_flags & RegVRex) | |
43234a1e | 12446 | { |
e951d5ca | 12447 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
12448 | || flag_code != CODE_64BIT) |
12449 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
12450 | |
12451 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
12452 | } |
12453 | ||
4787f4a5 | 12454 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
4a5c67ed | 12455 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) |
1ae00879 | 12456 | && flag_code != CODE_64BIT) |
20f0a1fc | 12457 | return (const reg_entry *) NULL; |
1ae00879 | 12458 | |
00cee14f JB |
12459 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat |
12460 | && !intel_syntax) | |
b7240065 JB |
12461 | return (const reg_entry *) NULL; |
12462 | ||
252b5132 RH |
12463 | return r; |
12464 | } | |
4d1bb795 JB |
12465 | |
12466 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
12467 | ||
12468 | static const reg_entry * | |
12469 | parse_register (char *reg_string, char **end_op) | |
12470 | { | |
12471 | const reg_entry *r; | |
12472 | ||
12473 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
12474 | r = parse_real_register (reg_string, end_op); | |
12475 | else | |
12476 | r = NULL; | |
12477 | if (!r) | |
12478 | { | |
12479 | char *save = input_line_pointer; | |
12480 | char c; | |
12481 | symbolS *symbolP; | |
12482 | ||
12483 | input_line_pointer = reg_string; | |
d02603dc | 12484 | c = get_symbol_name (®_string); |
4d1bb795 JB |
12485 | symbolP = symbol_find (reg_string); |
12486 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
12487 | { | |
12488 | const expressionS *e = symbol_get_value_expression (symbolP); | |
12489 | ||
0398aac5 | 12490 | know (e->X_op == O_register); |
4eed87de | 12491 | know (e->X_add_number >= 0 |
c3fe08fa | 12492 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 12493 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 12494 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 12495 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
12496 | *end_op = input_line_pointer; |
12497 | } | |
12498 | *input_line_pointer = c; | |
12499 | input_line_pointer = save; | |
12500 | } | |
12501 | return r; | |
12502 | } | |
12503 | ||
12504 | int | |
12505 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
12506 | { | |
12507 | const reg_entry *r; | |
12508 | char *end = input_line_pointer; | |
12509 | ||
12510 | *end = *nextcharP; | |
12511 | r = parse_register (name, &input_line_pointer); | |
12512 | if (r && end <= input_line_pointer) | |
12513 | { | |
12514 | *nextcharP = *input_line_pointer; | |
12515 | *input_line_pointer = 0; | |
12516 | e->X_op = O_register; | |
12517 | e->X_add_number = r - i386_regtab; | |
12518 | return 1; | |
12519 | } | |
12520 | input_line_pointer = end; | |
12521 | *end = 0; | |
ee86248c | 12522 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
12523 | } |
12524 | ||
12525 | void | |
12526 | md_operand (expressionS *e) | |
12527 | { | |
ee86248c JB |
12528 | char *end; |
12529 | const reg_entry *r; | |
4d1bb795 | 12530 | |
ee86248c JB |
12531 | switch (*input_line_pointer) |
12532 | { | |
12533 | case REGISTER_PREFIX: | |
12534 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
12535 | if (r) |
12536 | { | |
12537 | e->X_op = O_register; | |
12538 | e->X_add_number = r - i386_regtab; | |
12539 | input_line_pointer = end; | |
12540 | } | |
ee86248c JB |
12541 | break; |
12542 | ||
12543 | case '[': | |
9c2799c2 | 12544 | gas_assert (intel_syntax); |
ee86248c JB |
12545 | end = input_line_pointer++; |
12546 | expression (e); | |
12547 | if (*input_line_pointer == ']') | |
12548 | { | |
12549 | ++input_line_pointer; | |
12550 | e->X_op_symbol = make_expr_symbol (e); | |
12551 | e->X_add_symbol = NULL; | |
12552 | e->X_add_number = 0; | |
12553 | e->X_op = O_index; | |
12554 | } | |
12555 | else | |
12556 | { | |
12557 | e->X_op = O_absent; | |
12558 | input_line_pointer = end; | |
12559 | } | |
12560 | break; | |
4d1bb795 JB |
12561 | } |
12562 | } | |
12563 | ||
252b5132 | 12564 | \f |
4cc782b5 | 12565 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 12566 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 12567 | #else |
b6f8c7c4 | 12568 | const char *md_shortopts = "qnO::"; |
252b5132 | 12569 | #endif |
6e0b89ee | 12570 | |
3e73aa7c | 12571 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
12572 | #define OPTION_64 (OPTION_MD_BASE + 1) |
12573 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
12574 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
12575 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
12576 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
12577 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
12578 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
12579 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 12580 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 12581 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 12582 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
12583 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
12584 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
12585 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 12586 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
12587 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
12588 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 12589 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 12590 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 12591 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 12592 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
12593 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
12594 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 12595 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 12596 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 12597 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
12598 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
12599 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
12600 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 12601 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
ae531041 L |
12602 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
12603 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) | |
12604 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) | |
b3b91714 | 12605 | |
99ad8390 NC |
12606 | struct option md_longopts[] = |
12607 | { | |
3e73aa7c | 12608 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 12609 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12610 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 12611 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
12612 | #endif |
12613 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 12614 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 12615 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 12616 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 12617 | #endif |
b3b91714 | 12618 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
12619 | {"march", required_argument, NULL, OPTION_MARCH}, |
12620 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
12621 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
12622 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
12623 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
12624 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 12625 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 12626 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 12627 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 12628 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 12629 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 12630 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
12631 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
12632 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
12633 | # if defined (TE_PE) || defined (TE_PEP) |
12634 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
12635 | #endif | |
d1982f93 | 12636 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 12637 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 12638 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 12639 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
12640 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
12641 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
12642 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 12643 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
ae531041 L |
12644 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
12645 | {"mlfence-before-indirect-branch", required_argument, NULL, | |
12646 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, | |
12647 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, | |
5db04b09 L |
12648 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
12649 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
12650 | {NULL, no_argument, NULL, 0} |
12651 | }; | |
12652 | size_t md_longopts_size = sizeof (md_longopts); | |
12653 | ||
12654 | int | |
17b9d67d | 12655 | md_parse_option (int c, const char *arg) |
252b5132 | 12656 | { |
91d6fa6a | 12657 | unsigned int j; |
e379e5f3 | 12658 | char *arch, *next, *saved, *type; |
9103f4f4 | 12659 | |
252b5132 RH |
12660 | switch (c) |
12661 | { | |
12b55ccc L |
12662 | case 'n': |
12663 | optimize_align_code = 0; | |
12664 | break; | |
12665 | ||
a38cf1db AM |
12666 | case 'q': |
12667 | quiet_warnings = 1; | |
252b5132 RH |
12668 | break; |
12669 | ||
12670 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
12671 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
12672 | should be emitted or not. FIXME: Not implemented. */ | |
12673 | case 'Q': | |
d4693039 JB |
12674 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
12675 | return 0; | |
252b5132 RH |
12676 | break; |
12677 | ||
12678 | /* -V: SVR4 argument to print version ID. */ | |
12679 | case 'V': | |
12680 | print_version_id (); | |
12681 | break; | |
12682 | ||
a38cf1db AM |
12683 | /* -k: Ignore for FreeBSD compatibility. */ |
12684 | case 'k': | |
252b5132 | 12685 | break; |
4cc782b5 ILT |
12686 | |
12687 | case 's': | |
12688 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 12689 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 12690 | break; |
8dcea932 L |
12691 | |
12692 | case OPTION_MSHARED: | |
12693 | shared = 1; | |
12694 | break; | |
b4a3a7b4 L |
12695 | |
12696 | case OPTION_X86_USED_NOTE: | |
12697 | if (strcasecmp (arg, "yes") == 0) | |
12698 | x86_used_note = 1; | |
12699 | else if (strcasecmp (arg, "no") == 0) | |
12700 | x86_used_note = 0; | |
12701 | else | |
12702 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
12703 | break; | |
12704 | ||
12705 | ||
99ad8390 | 12706 | #endif |
321098a5 | 12707 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12708 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
12709 | case OPTION_64: |
12710 | { | |
12711 | const char **list, **l; | |
12712 | ||
3e73aa7c JH |
12713 | list = bfd_target_list (); |
12714 | for (l = list; *l != NULL; l++) | |
8620418b | 12715 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
12716 | || strcmp (*l, "coff-x86-64") == 0 |
12717 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
12718 | || strcmp (*l, "pei-x86-64") == 0 |
12719 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
12720 | { |
12721 | default_arch = "x86_64"; | |
12722 | break; | |
12723 | } | |
3e73aa7c | 12724 | if (*l == NULL) |
2b5d6a91 | 12725 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
12726 | free (list); |
12727 | } | |
12728 | break; | |
12729 | #endif | |
252b5132 | 12730 | |
351f65ca | 12731 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 12732 | case OPTION_X32: |
351f65ca L |
12733 | if (IS_ELF) |
12734 | { | |
12735 | const char **list, **l; | |
12736 | ||
12737 | list = bfd_target_list (); | |
12738 | for (l = list; *l != NULL; l++) | |
12739 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
12740 | { | |
12741 | default_arch = "x86_64:32"; | |
12742 | break; | |
12743 | } | |
12744 | if (*l == NULL) | |
2b5d6a91 | 12745 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
12746 | free (list); |
12747 | } | |
12748 | else | |
12749 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
12750 | break; | |
12751 | #endif | |
12752 | ||
6e0b89ee AM |
12753 | case OPTION_32: |
12754 | default_arch = "i386"; | |
12755 | break; | |
12756 | ||
b3b91714 AM |
12757 | case OPTION_DIVIDE: |
12758 | #ifdef SVR4_COMMENT_CHARS | |
12759 | { | |
12760 | char *n, *t; | |
12761 | const char *s; | |
12762 | ||
add39d23 | 12763 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
12764 | t = n; |
12765 | for (s = i386_comment_chars; *s != '\0'; s++) | |
12766 | if (*s != '/') | |
12767 | *t++ = *s; | |
12768 | *t = '\0'; | |
12769 | i386_comment_chars = n; | |
12770 | } | |
12771 | #endif | |
12772 | break; | |
12773 | ||
9103f4f4 | 12774 | case OPTION_MARCH: |
293f5f65 L |
12775 | saved = xstrdup (arg); |
12776 | arch = saved; | |
12777 | /* Allow -march=+nosse. */ | |
12778 | if (*arch == '+') | |
12779 | arch++; | |
6305a203 | 12780 | do |
9103f4f4 | 12781 | { |
6305a203 | 12782 | if (*arch == '.') |
2b5d6a91 | 12783 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12784 | next = strchr (arch, '+'); |
12785 | if (next) | |
12786 | *next++ = '\0'; | |
91d6fa6a | 12787 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12788 | { |
91d6fa6a | 12789 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 12790 | { |
6305a203 | 12791 | /* Processor. */ |
1ded5609 JB |
12792 | if (! cpu_arch[j].flags.bitfield.cpui386) |
12793 | continue; | |
12794 | ||
91d6fa6a | 12795 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 12796 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
12797 | cpu_arch_flags = cpu_arch[j].flags; |
12798 | cpu_arch_isa = cpu_arch[j].type; | |
12799 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
12800 | if (!cpu_arch_tune_set) |
12801 | { | |
12802 | cpu_arch_tune = cpu_arch_isa; | |
12803 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
12804 | } | |
12805 | break; | |
12806 | } | |
91d6fa6a NC |
12807 | else if (*cpu_arch [j].name == '.' |
12808 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 12809 | { |
33eaf5de | 12810 | /* ISA extension. */ |
6305a203 | 12811 | i386_cpu_flags flags; |
309d3373 | 12812 | |
293f5f65 L |
12813 | flags = cpu_flags_or (cpu_arch_flags, |
12814 | cpu_arch[j].flags); | |
81486035 | 12815 | |
5b64d091 | 12816 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
12817 | { |
12818 | if (cpu_sub_arch_name) | |
12819 | { | |
12820 | char *name = cpu_sub_arch_name; | |
12821 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 12822 | cpu_arch[j].name, |
1bf57e9f | 12823 | (const char *) NULL); |
6305a203 L |
12824 | free (name); |
12825 | } | |
12826 | else | |
91d6fa6a | 12827 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 12828 | cpu_arch_flags = flags; |
a586129e | 12829 | cpu_arch_isa_flags = flags; |
6305a203 | 12830 | } |
0089dace L |
12831 | else |
12832 | cpu_arch_isa_flags | |
12833 | = cpu_flags_or (cpu_arch_isa_flags, | |
12834 | cpu_arch[j].flags); | |
6305a203 | 12835 | break; |
ccc9c027 | 12836 | } |
9103f4f4 | 12837 | } |
6305a203 | 12838 | |
293f5f65 L |
12839 | if (j >= ARRAY_SIZE (cpu_arch)) |
12840 | { | |
33eaf5de | 12841 | /* Disable an ISA extension. */ |
293f5f65 L |
12842 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
12843 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
12844 | { | |
12845 | i386_cpu_flags flags; | |
12846 | ||
12847 | flags = cpu_flags_and_not (cpu_arch_flags, | |
12848 | cpu_noarch[j].flags); | |
12849 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
12850 | { | |
12851 | if (cpu_sub_arch_name) | |
12852 | { | |
12853 | char *name = cpu_sub_arch_name; | |
12854 | cpu_sub_arch_name = concat (arch, | |
12855 | (const char *) NULL); | |
12856 | free (name); | |
12857 | } | |
12858 | else | |
12859 | cpu_sub_arch_name = xstrdup (arch); | |
12860 | cpu_arch_flags = flags; | |
12861 | cpu_arch_isa_flags = flags; | |
12862 | } | |
12863 | break; | |
12864 | } | |
12865 | ||
12866 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
12867 | j = ARRAY_SIZE (cpu_arch); | |
12868 | } | |
12869 | ||
91d6fa6a | 12870 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12871 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12872 | |
12873 | arch = next; | |
9103f4f4 | 12874 | } |
293f5f65 L |
12875 | while (next != NULL); |
12876 | free (saved); | |
9103f4f4 L |
12877 | break; |
12878 | ||
12879 | case OPTION_MTUNE: | |
12880 | if (*arg == '.') | |
2b5d6a91 | 12881 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 12882 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12883 | { |
91d6fa6a | 12884 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 12885 | { |
ccc9c027 | 12886 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
12887 | cpu_arch_tune = cpu_arch [j].type; |
12888 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
12889 | break; |
12890 | } | |
12891 | } | |
91d6fa6a | 12892 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12893 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
12894 | break; |
12895 | ||
1efbbeb4 L |
12896 | case OPTION_MMNEMONIC: |
12897 | if (strcasecmp (arg, "att") == 0) | |
12898 | intel_mnemonic = 0; | |
12899 | else if (strcasecmp (arg, "intel") == 0) | |
12900 | intel_mnemonic = 1; | |
12901 | else | |
2b5d6a91 | 12902 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
12903 | break; |
12904 | ||
12905 | case OPTION_MSYNTAX: | |
12906 | if (strcasecmp (arg, "att") == 0) | |
12907 | intel_syntax = 0; | |
12908 | else if (strcasecmp (arg, "intel") == 0) | |
12909 | intel_syntax = 1; | |
12910 | else | |
2b5d6a91 | 12911 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
12912 | break; |
12913 | ||
12914 | case OPTION_MINDEX_REG: | |
12915 | allow_index_reg = 1; | |
12916 | break; | |
12917 | ||
12918 | case OPTION_MNAKED_REG: | |
12919 | allow_naked_reg = 1; | |
12920 | break; | |
12921 | ||
c0f3af97 L |
12922 | case OPTION_MSSE2AVX: |
12923 | sse2avx = 1; | |
12924 | break; | |
12925 | ||
daf50ae7 L |
12926 | case OPTION_MSSE_CHECK: |
12927 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 12928 | sse_check = check_error; |
daf50ae7 | 12929 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 12930 | sse_check = check_warning; |
daf50ae7 | 12931 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 12932 | sse_check = check_none; |
daf50ae7 | 12933 | else |
2b5d6a91 | 12934 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
12935 | break; |
12936 | ||
7bab8ab5 JB |
12937 | case OPTION_MOPERAND_CHECK: |
12938 | if (strcasecmp (arg, "error") == 0) | |
12939 | operand_check = check_error; | |
12940 | else if (strcasecmp (arg, "warning") == 0) | |
12941 | operand_check = check_warning; | |
12942 | else if (strcasecmp (arg, "none") == 0) | |
12943 | operand_check = check_none; | |
12944 | else | |
12945 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
12946 | break; | |
12947 | ||
539f890d L |
12948 | case OPTION_MAVXSCALAR: |
12949 | if (strcasecmp (arg, "128") == 0) | |
12950 | avxscalar = vex128; | |
12951 | else if (strcasecmp (arg, "256") == 0) | |
12952 | avxscalar = vex256; | |
12953 | else | |
2b5d6a91 | 12954 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
12955 | break; |
12956 | ||
03751133 L |
12957 | case OPTION_MVEXWIG: |
12958 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 12959 | vexwig = vexw0; |
03751133 | 12960 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 12961 | vexwig = vexw1; |
03751133 L |
12962 | else |
12963 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
12964 | break; | |
12965 | ||
7e8b059b L |
12966 | case OPTION_MADD_BND_PREFIX: |
12967 | add_bnd_prefix = 1; | |
12968 | break; | |
12969 | ||
43234a1e L |
12970 | case OPTION_MEVEXLIG: |
12971 | if (strcmp (arg, "128") == 0) | |
12972 | evexlig = evexl128; | |
12973 | else if (strcmp (arg, "256") == 0) | |
12974 | evexlig = evexl256; | |
12975 | else if (strcmp (arg, "512") == 0) | |
12976 | evexlig = evexl512; | |
12977 | else | |
12978 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
12979 | break; | |
12980 | ||
d3d3c6db IT |
12981 | case OPTION_MEVEXRCIG: |
12982 | if (strcmp (arg, "rne") == 0) | |
12983 | evexrcig = rne; | |
12984 | else if (strcmp (arg, "rd") == 0) | |
12985 | evexrcig = rd; | |
12986 | else if (strcmp (arg, "ru") == 0) | |
12987 | evexrcig = ru; | |
12988 | else if (strcmp (arg, "rz") == 0) | |
12989 | evexrcig = rz; | |
12990 | else | |
12991 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
12992 | break; | |
12993 | ||
43234a1e L |
12994 | case OPTION_MEVEXWIG: |
12995 | if (strcmp (arg, "0") == 0) | |
12996 | evexwig = evexw0; | |
12997 | else if (strcmp (arg, "1") == 0) | |
12998 | evexwig = evexw1; | |
12999 | else | |
13000 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
13001 | break; | |
13002 | ||
167ad85b TG |
13003 | # if defined (TE_PE) || defined (TE_PEP) |
13004 | case OPTION_MBIG_OBJ: | |
13005 | use_big_obj = 1; | |
13006 | break; | |
13007 | #endif | |
13008 | ||
d1982f93 | 13009 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
13010 | if (strcasecmp (arg, "yes") == 0) |
13011 | omit_lock_prefix = 1; | |
13012 | else if (strcasecmp (arg, "no") == 0) | |
13013 | omit_lock_prefix = 0; | |
13014 | else | |
13015 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
13016 | break; | |
13017 | ||
e4e00185 AS |
13018 | case OPTION_MFENCE_AS_LOCK_ADD: |
13019 | if (strcasecmp (arg, "yes") == 0) | |
13020 | avoid_fence = 1; | |
13021 | else if (strcasecmp (arg, "no") == 0) | |
13022 | avoid_fence = 0; | |
13023 | else | |
13024 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
13025 | break; | |
13026 | ||
ae531041 L |
13027 | case OPTION_MLFENCE_AFTER_LOAD: |
13028 | if (strcasecmp (arg, "yes") == 0) | |
13029 | lfence_after_load = 1; | |
13030 | else if (strcasecmp (arg, "no") == 0) | |
13031 | lfence_after_load = 0; | |
13032 | else | |
13033 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); | |
13034 | break; | |
13035 | ||
13036 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: | |
13037 | if (strcasecmp (arg, "all") == 0) | |
a09f656b | 13038 | { |
13039 | lfence_before_indirect_branch = lfence_branch_all; | |
13040 | if (lfence_before_ret == lfence_before_ret_none) | |
13041 | lfence_before_ret = lfence_before_ret_shl; | |
13042 | } | |
ae531041 L |
13043 | else if (strcasecmp (arg, "memory") == 0) |
13044 | lfence_before_indirect_branch = lfence_branch_memory; | |
13045 | else if (strcasecmp (arg, "register") == 0) | |
13046 | lfence_before_indirect_branch = lfence_branch_register; | |
13047 | else if (strcasecmp (arg, "none") == 0) | |
13048 | lfence_before_indirect_branch = lfence_branch_none; | |
13049 | else | |
13050 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), | |
13051 | arg); | |
13052 | break; | |
13053 | ||
13054 | case OPTION_MLFENCE_BEFORE_RET: | |
13055 | if (strcasecmp (arg, "or") == 0) | |
13056 | lfence_before_ret = lfence_before_ret_or; | |
13057 | else if (strcasecmp (arg, "not") == 0) | |
13058 | lfence_before_ret = lfence_before_ret_not; | |
a09f656b | 13059 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
13060 | lfence_before_ret = lfence_before_ret_shl; | |
ae531041 L |
13061 | else if (strcasecmp (arg, "none") == 0) |
13062 | lfence_before_ret = lfence_before_ret_none; | |
13063 | else | |
13064 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), | |
13065 | arg); | |
13066 | break; | |
13067 | ||
0cb4071e L |
13068 | case OPTION_MRELAX_RELOCATIONS: |
13069 | if (strcasecmp (arg, "yes") == 0) | |
13070 | generate_relax_relocations = 1; | |
13071 | else if (strcasecmp (arg, "no") == 0) | |
13072 | generate_relax_relocations = 0; | |
13073 | else | |
13074 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
13075 | break; | |
13076 | ||
e379e5f3 L |
13077 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
13078 | { | |
13079 | char *end; | |
13080 | long int align = strtoul (arg, &end, 0); | |
13081 | if (*end == '\0') | |
13082 | { | |
13083 | if (align == 0) | |
13084 | { | |
13085 | align_branch_power = 0; | |
13086 | break; | |
13087 | } | |
13088 | else if (align >= 16) | |
13089 | { | |
13090 | int align_power; | |
13091 | for (align_power = 0; | |
13092 | (align & 1) == 0; | |
13093 | align >>= 1, align_power++) | |
13094 | continue; | |
13095 | /* Limit alignment power to 31. */ | |
13096 | if (align == 1 && align_power < 32) | |
13097 | { | |
13098 | align_branch_power = align_power; | |
13099 | break; | |
13100 | } | |
13101 | } | |
13102 | } | |
13103 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
13104 | } | |
13105 | break; | |
13106 | ||
13107 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
13108 | { | |
13109 | char *end; | |
13110 | int align = strtoul (arg, &end, 0); | |
13111 | /* Some processors only support 5 prefixes. */ | |
13112 | if (*end == '\0' && align >= 0 && align < 6) | |
13113 | { | |
13114 | align_branch_prefix_size = align; | |
13115 | break; | |
13116 | } | |
13117 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
13118 | arg); | |
13119 | } | |
13120 | break; | |
13121 | ||
13122 | case OPTION_MALIGN_BRANCH: | |
13123 | align_branch = 0; | |
13124 | saved = xstrdup (arg); | |
13125 | type = saved; | |
13126 | do | |
13127 | { | |
13128 | next = strchr (type, '+'); | |
13129 | if (next) | |
13130 | *next++ = '\0'; | |
13131 | if (strcasecmp (type, "jcc") == 0) | |
13132 | align_branch |= align_branch_jcc_bit; | |
13133 | else if (strcasecmp (type, "fused") == 0) | |
13134 | align_branch |= align_branch_fused_bit; | |
13135 | else if (strcasecmp (type, "jmp") == 0) | |
13136 | align_branch |= align_branch_jmp_bit; | |
13137 | else if (strcasecmp (type, "call") == 0) | |
13138 | align_branch |= align_branch_call_bit; | |
13139 | else if (strcasecmp (type, "ret") == 0) | |
13140 | align_branch |= align_branch_ret_bit; | |
13141 | else if (strcasecmp (type, "indirect") == 0) | |
13142 | align_branch |= align_branch_indirect_bit; | |
13143 | else | |
13144 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
13145 | type = next; | |
13146 | } | |
13147 | while (next != NULL); | |
13148 | free (saved); | |
13149 | break; | |
13150 | ||
76cf450b L |
13151 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
13152 | align_branch_power = 5; | |
13153 | align_branch_prefix_size = 5; | |
13154 | align_branch = (align_branch_jcc_bit | |
13155 | | align_branch_fused_bit | |
13156 | | align_branch_jmp_bit); | |
13157 | break; | |
13158 | ||
5db04b09 | 13159 | case OPTION_MAMD64: |
4b5aaf5f | 13160 | isa64 = amd64; |
5db04b09 L |
13161 | break; |
13162 | ||
13163 | case OPTION_MINTEL64: | |
4b5aaf5f | 13164 | isa64 = intel64; |
5db04b09 L |
13165 | break; |
13166 | ||
b6f8c7c4 L |
13167 | case 'O': |
13168 | if (arg == NULL) | |
13169 | { | |
13170 | optimize = 1; | |
13171 | /* Turn off -Os. */ | |
13172 | optimize_for_space = 0; | |
13173 | } | |
13174 | else if (*arg == 's') | |
13175 | { | |
13176 | optimize_for_space = 1; | |
13177 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 13178 | optimize = INT_MAX; |
b6f8c7c4 L |
13179 | } |
13180 | else | |
13181 | { | |
13182 | optimize = atoi (arg); | |
13183 | /* Turn off -Os. */ | |
13184 | optimize_for_space = 0; | |
13185 | } | |
13186 | break; | |
13187 | ||
252b5132 RH |
13188 | default: |
13189 | return 0; | |
13190 | } | |
13191 | return 1; | |
13192 | } | |
13193 | ||
8a2c8fef L |
13194 | #define MESSAGE_TEMPLATE \ |
13195 | " " | |
13196 | ||
293f5f65 L |
13197 | static char * |
13198 | output_message (FILE *stream, char *p, char *message, char *start, | |
13199 | int *left_p, const char *name, int len) | |
13200 | { | |
13201 | int size = sizeof (MESSAGE_TEMPLATE); | |
13202 | int left = *left_p; | |
13203 | ||
13204 | /* Reserve 2 spaces for ", " or ",\0" */ | |
13205 | left -= len + 2; | |
13206 | ||
13207 | /* Check if there is any room. */ | |
13208 | if (left >= 0) | |
13209 | { | |
13210 | if (p != start) | |
13211 | { | |
13212 | *p++ = ','; | |
13213 | *p++ = ' '; | |
13214 | } | |
13215 | p = mempcpy (p, name, len); | |
13216 | } | |
13217 | else | |
13218 | { | |
13219 | /* Output the current message now and start a new one. */ | |
13220 | *p++ = ','; | |
13221 | *p = '\0'; | |
13222 | fprintf (stream, "%s\n", message); | |
13223 | p = start; | |
13224 | left = size - (start - message) - len - 2; | |
13225 | ||
13226 | gas_assert (left >= 0); | |
13227 | ||
13228 | p = mempcpy (p, name, len); | |
13229 | } | |
13230 | ||
13231 | *left_p = left; | |
13232 | return p; | |
13233 | } | |
13234 | ||
8a2c8fef | 13235 | static void |
1ded5609 | 13236 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
13237 | { |
13238 | static char message[] = MESSAGE_TEMPLATE; | |
13239 | char *start = message + 27; | |
13240 | char *p; | |
13241 | int size = sizeof (MESSAGE_TEMPLATE); | |
13242 | int left; | |
13243 | const char *name; | |
13244 | int len; | |
13245 | unsigned int j; | |
13246 | ||
13247 | p = start; | |
13248 | left = size - (start - message); | |
13249 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
13250 | { | |
13251 | /* Should it be skipped? */ | |
13252 | if (cpu_arch [j].skip) | |
13253 | continue; | |
13254 | ||
13255 | name = cpu_arch [j].name; | |
13256 | len = cpu_arch [j].len; | |
13257 | if (*name == '.') | |
13258 | { | |
13259 | /* It is an extension. Skip if we aren't asked to show it. */ | |
13260 | if (ext) | |
13261 | { | |
13262 | name++; | |
13263 | len--; | |
13264 | } | |
13265 | else | |
13266 | continue; | |
13267 | } | |
13268 | else if (ext) | |
13269 | { | |
13270 | /* It is an processor. Skip if we show only extension. */ | |
13271 | continue; | |
13272 | } | |
1ded5609 JB |
13273 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
13274 | { | |
13275 | /* It is an impossible processor - skip. */ | |
13276 | continue; | |
13277 | } | |
8a2c8fef | 13278 | |
293f5f65 | 13279 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
13280 | } |
13281 | ||
293f5f65 L |
13282 | /* Display disabled extensions. */ |
13283 | if (ext) | |
13284 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
13285 | { | |
13286 | name = cpu_noarch [j].name; | |
13287 | len = cpu_noarch [j].len; | |
13288 | p = output_message (stream, p, message, start, &left, name, | |
13289 | len); | |
13290 | } | |
13291 | ||
8a2c8fef L |
13292 | *p = '\0'; |
13293 | fprintf (stream, "%s\n", message); | |
13294 | } | |
13295 | ||
252b5132 | 13296 | void |
8a2c8fef | 13297 | md_show_usage (FILE *stream) |
252b5132 | 13298 | { |
4cc782b5 ILT |
13299 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13300 | fprintf (stream, _("\ | |
d4693039 | 13301 | -Qy, -Qn ignored\n\ |
a38cf1db | 13302 | -V print assembler version number\n\ |
b3b91714 AM |
13303 | -k ignored\n")); |
13304 | #endif | |
13305 | fprintf (stream, _("\ | |
12b55ccc | 13306 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
13307 | -q quieten some warnings\n")); |
13308 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13309 | fprintf (stream, _("\ | |
a38cf1db | 13310 | -s ignored\n")); |
b3b91714 | 13311 | #endif |
d7f449c0 L |
13312 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
13313 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 13314 | fprintf (stream, _("\ |
570561f7 | 13315 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 13316 | #endif |
b3b91714 AM |
13317 | #ifdef SVR4_COMMENT_CHARS |
13318 | fprintf (stream, _("\ | |
13319 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
13320 | #else |
13321 | fprintf (stream, _("\ | |
b3b91714 | 13322 | --divide ignored\n")); |
4cc782b5 | 13323 | #endif |
9103f4f4 | 13324 | fprintf (stream, _("\ |
6305a203 | 13325 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 13326 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 13327 | show_arch (stream, 0, 1); |
8a2c8fef L |
13328 | fprintf (stream, _("\ |
13329 | EXTENSION is combination of:\n")); | |
1ded5609 | 13330 | show_arch (stream, 1, 0); |
6305a203 | 13331 | fprintf (stream, _("\ |
8a2c8fef | 13332 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 13333 | show_arch (stream, 0, 0); |
ba104c83 | 13334 | fprintf (stream, _("\ |
c0f3af97 L |
13335 | -msse2avx encode SSE instructions with VEX prefix\n")); |
13336 | fprintf (stream, _("\ | |
7c5c05ef | 13337 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
13338 | check SSE instructions\n")); |
13339 | fprintf (stream, _("\ | |
7c5c05ef | 13340 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
13341 | check operand combinations for validity\n")); |
13342 | fprintf (stream, _("\ | |
7c5c05ef L |
13343 | -mavxscalar=[128|256] (default: 128)\n\ |
13344 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
13345 | length\n")); |
13346 | fprintf (stream, _("\ | |
03751133 L |
13347 | -mvexwig=[0|1] (default: 0)\n\ |
13348 | encode VEX instructions with specific VEX.W value\n\ | |
13349 | for VEX.W bit ignored instructions\n")); | |
13350 | fprintf (stream, _("\ | |
7c5c05ef L |
13351 | -mevexlig=[128|256|512] (default: 128)\n\ |
13352 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
13353 | length\n")); |
13354 | fprintf (stream, _("\ | |
7c5c05ef L |
13355 | -mevexwig=[0|1] (default: 0)\n\ |
13356 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
13357 | for EVEX.W bit ignored instructions\n")); |
13358 | fprintf (stream, _("\ | |
7c5c05ef | 13359 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
13360 | encode EVEX instructions with specific EVEX.RC value\n\ |
13361 | for SAE-only ignored instructions\n")); | |
13362 | fprintf (stream, _("\ | |
7c5c05ef L |
13363 | -mmnemonic=[att|intel] ")); |
13364 | if (SYSV386_COMPAT) | |
13365 | fprintf (stream, _("(default: att)\n")); | |
13366 | else | |
13367 | fprintf (stream, _("(default: intel)\n")); | |
13368 | fprintf (stream, _("\ | |
13369 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 13370 | fprintf (stream, _("\ |
7c5c05ef L |
13371 | -msyntax=[att|intel] (default: att)\n\ |
13372 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
13373 | fprintf (stream, _("\ |
13374 | -mindex-reg support pseudo index registers\n")); | |
13375 | fprintf (stream, _("\ | |
13376 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
13377 | fprintf (stream, _("\ | |
7e8b059b | 13378 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 13379 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
13380 | fprintf (stream, _("\ |
13381 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
13382 | fprintf (stream, _("\ |
13383 | -mx86-used-note=[no|yes] ")); | |
13384 | if (DEFAULT_X86_USED_NOTE) | |
13385 | fprintf (stream, _("(default: yes)\n")); | |
13386 | else | |
13387 | fprintf (stream, _("(default: no)\n")); | |
13388 | fprintf (stream, _("\ | |
13389 | generate x86 used ISA and feature properties\n")); | |
13390 | #endif | |
13391 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
13392 | fprintf (stream, _("\ |
13393 | -mbig-obj generate big object files\n")); | |
13394 | #endif | |
d022bddd | 13395 | fprintf (stream, _("\ |
7c5c05ef | 13396 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 13397 | strip all lock prefixes\n")); |
5db04b09 | 13398 | fprintf (stream, _("\ |
7c5c05ef | 13399 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
13400 | encode lfence, mfence and sfence as\n\ |
13401 | lock addl $0x0, (%%{re}sp)\n")); | |
13402 | fprintf (stream, _("\ | |
7c5c05ef L |
13403 | -mrelax-relocations=[no|yes] ")); |
13404 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
13405 | fprintf (stream, _("(default: yes)\n")); | |
13406 | else | |
13407 | fprintf (stream, _("(default: no)\n")); | |
13408 | fprintf (stream, _("\ | |
0cb4071e L |
13409 | generate relax relocations\n")); |
13410 | fprintf (stream, _("\ | |
e379e5f3 L |
13411 | -malign-branch-boundary=NUM (default: 0)\n\ |
13412 | align branches within NUM byte boundary\n")); | |
13413 | fprintf (stream, _("\ | |
13414 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
13415 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
13416 | indirect\n\ | |
13417 | specify types of branches to align\n")); | |
13418 | fprintf (stream, _("\ | |
13419 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
13420 | align branches with NUM prefixes per instruction\n")); | |
13421 | fprintf (stream, _("\ | |
76cf450b L |
13422 | -mbranches-within-32B-boundaries\n\ |
13423 | align branches within 32 byte boundary\n")); | |
13424 | fprintf (stream, _("\ | |
ae531041 L |
13425 | -mlfence-after-load=[no|yes] (default: no)\n\ |
13426 | generate lfence after load\n")); | |
13427 | fprintf (stream, _("\ | |
13428 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ | |
13429 | generate lfence before indirect near branch\n")); | |
13430 | fprintf (stream, _("\ | |
a09f656b | 13431 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
ae531041 L |
13432 | generate lfence before ret\n")); |
13433 | fprintf (stream, _("\ | |
7c5c05ef | 13434 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
13435 | fprintf (stream, _("\ |
13436 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
13437 | } |
13438 | ||
3e73aa7c | 13439 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 13440 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 13441 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
13442 | |
13443 | /* Pick the target format to use. */ | |
13444 | ||
47926f60 | 13445 | const char * |
e3bb37b5 | 13446 | i386_target_format (void) |
252b5132 | 13447 | { |
351f65ca L |
13448 | if (!strncmp (default_arch, "x86_64", 6)) |
13449 | { | |
13450 | update_code_flag (CODE_64BIT, 1); | |
13451 | if (default_arch[6] == '\0') | |
7f56bc95 | 13452 | x86_elf_abi = X86_64_ABI; |
351f65ca | 13453 | else |
7f56bc95 | 13454 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 13455 | } |
3e73aa7c | 13456 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 13457 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
13458 | else if (!strcmp (default_arch, "iamcu")) |
13459 | { | |
13460 | update_code_flag (CODE_32BIT, 1); | |
13461 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
13462 | { | |
13463 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
13464 | cpu_arch_name = "iamcu"; | |
13465 | cpu_sub_arch_name = NULL; | |
13466 | cpu_arch_flags = iamcu_flags; | |
13467 | cpu_arch_isa = PROCESSOR_IAMCU; | |
13468 | cpu_arch_isa_flags = iamcu_flags; | |
13469 | if (!cpu_arch_tune_set) | |
13470 | { | |
13471 | cpu_arch_tune = cpu_arch_isa; | |
13472 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13473 | } | |
13474 | } | |
8d471ec1 | 13475 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
13476 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
13477 | cpu_arch_name); | |
13478 | } | |
3e73aa7c | 13479 | else |
2b5d6a91 | 13480 | as_fatal (_("unknown architecture")); |
89507696 JB |
13481 | |
13482 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
13483 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13484 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
13485 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13486 | ||
252b5132 RH |
13487 | switch (OUTPUT_FLAVOR) |
13488 | { | |
9384f2ff | 13489 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 13490 | case bfd_target_aout_flavour: |
47926f60 | 13491 | return AOUT_TARGET_FORMAT; |
4c63da97 | 13492 | #endif |
9384f2ff AM |
13493 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
13494 | # if defined (TE_PE) || defined (TE_PEP) | |
13495 | case bfd_target_coff_flavour: | |
167ad85b TG |
13496 | if (flag_code == CODE_64BIT) |
13497 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
13498 | else | |
251dae91 | 13499 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; |
9384f2ff | 13500 | # elif defined (TE_GO32) |
0561d57c JK |
13501 | case bfd_target_coff_flavour: |
13502 | return "coff-go32"; | |
9384f2ff | 13503 | # else |
252b5132 RH |
13504 | case bfd_target_coff_flavour: |
13505 | return "coff-i386"; | |
9384f2ff | 13506 | # endif |
4c63da97 | 13507 | #endif |
3e73aa7c | 13508 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 13509 | case bfd_target_elf_flavour: |
3e73aa7c | 13510 | { |
351f65ca L |
13511 | const char *format; |
13512 | ||
13513 | switch (x86_elf_abi) | |
4fa24527 | 13514 | { |
351f65ca L |
13515 | default: |
13516 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
13517 | #ifndef TE_SOLARIS |
13518 | tls_get_addr = "___tls_get_addr"; | |
13519 | #endif | |
351f65ca | 13520 | break; |
7f56bc95 | 13521 | case X86_64_ABI: |
351f65ca | 13522 | use_rela_relocations = 1; |
4fa24527 | 13523 | object_64bit = 1; |
e379e5f3 L |
13524 | #ifndef TE_SOLARIS |
13525 | tls_get_addr = "__tls_get_addr"; | |
13526 | #endif | |
351f65ca L |
13527 | format = ELF_TARGET_FORMAT64; |
13528 | break; | |
7f56bc95 | 13529 | case X86_64_X32_ABI: |
4fa24527 | 13530 | use_rela_relocations = 1; |
351f65ca | 13531 | object_64bit = 1; |
e379e5f3 L |
13532 | #ifndef TE_SOLARIS |
13533 | tls_get_addr = "__tls_get_addr"; | |
13534 | #endif | |
862be3fb | 13535 | disallow_64bit_reloc = 1; |
351f65ca L |
13536 | format = ELF_TARGET_FORMAT32; |
13537 | break; | |
4fa24527 | 13538 | } |
3632d14b | 13539 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 13540 | { |
7f56bc95 | 13541 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
13542 | as_fatal (_("Intel L1OM is 64bit only")); |
13543 | return ELF_TARGET_L1OM_FORMAT; | |
13544 | } | |
b49f93f6 | 13545 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
13546 | { |
13547 | if (x86_elf_abi != X86_64_ABI) | |
13548 | as_fatal (_("Intel K1OM is 64bit only")); | |
13549 | return ELF_TARGET_K1OM_FORMAT; | |
13550 | } | |
81486035 L |
13551 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
13552 | { | |
13553 | if (x86_elf_abi != I386_ABI) | |
13554 | as_fatal (_("Intel MCU is 32bit only")); | |
13555 | return ELF_TARGET_IAMCU_FORMAT; | |
13556 | } | |
8a9036a4 | 13557 | else |
351f65ca | 13558 | return format; |
3e73aa7c | 13559 | } |
e57f8c65 TG |
13560 | #endif |
13561 | #if defined (OBJ_MACH_O) | |
13562 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
13563 | if (flag_code == CODE_64BIT) |
13564 | { | |
13565 | use_rela_relocations = 1; | |
13566 | object_64bit = 1; | |
13567 | return "mach-o-x86-64"; | |
13568 | } | |
13569 | else | |
13570 | return "mach-o-i386"; | |
4c63da97 | 13571 | #endif |
252b5132 RH |
13572 | default: |
13573 | abort (); | |
13574 | return NULL; | |
13575 | } | |
13576 | } | |
13577 | ||
47926f60 | 13578 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 13579 | \f |
252b5132 | 13580 | symbolS * |
7016a5d5 | 13581 | md_undefined_symbol (char *name) |
252b5132 | 13582 | { |
18dc2407 ILT |
13583 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
13584 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
13585 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
13586 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
13587 | { |
13588 | if (!GOT_symbol) | |
13589 | { | |
13590 | if (symbol_find (name)) | |
13591 | as_bad (_("GOT already in symbol table")); | |
13592 | GOT_symbol = symbol_new (name, undefined_section, | |
13593 | (valueT) 0, &zero_address_frag); | |
13594 | }; | |
13595 | return GOT_symbol; | |
13596 | } | |
252b5132 RH |
13597 | return 0; |
13598 | } | |
13599 | ||
13600 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 13601 | |
252b5132 | 13602 | valueT |
7016a5d5 | 13603 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 13604 | { |
4c63da97 AM |
13605 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
13606 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
13607 | { | |
13608 | /* For a.out, force the section size to be aligned. If we don't do | |
13609 | this, BFD will align it for us, but it will not write out the | |
13610 | final bytes of the section. This may be a bug in BFD, but it is | |
13611 | easier to fix it here since that is how the other a.out targets | |
13612 | work. */ | |
13613 | int align; | |
13614 | ||
fd361982 | 13615 | align = bfd_section_alignment (segment); |
8d3842cd | 13616 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 13617 | } |
252b5132 RH |
13618 | #endif |
13619 | ||
13620 | return size; | |
13621 | } | |
13622 | ||
13623 | /* On the i386, PC-relative offsets are relative to the start of the | |
13624 | next instruction. That is, the address of the offset, plus its | |
13625 | size, since the offset is always the last part of the insn. */ | |
13626 | ||
13627 | long | |
e3bb37b5 | 13628 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
13629 | { |
13630 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
13631 | } | |
13632 | ||
13633 | #ifndef I386COFF | |
13634 | ||
13635 | static void | |
e3bb37b5 | 13636 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13637 | { |
29b0f896 | 13638 | int temp; |
252b5132 | 13639 | |
8a75718c JB |
13640 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13641 | if (IS_ELF) | |
13642 | obj_elf_section_change_hook (); | |
13643 | #endif | |
252b5132 RH |
13644 | temp = get_absolute_expression (); |
13645 | subseg_set (bss_section, (subsegT) temp); | |
13646 | demand_empty_rest_of_line (); | |
13647 | } | |
13648 | ||
13649 | #endif | |
13650 | ||
e379e5f3 L |
13651 | /* Remember constant directive. */ |
13652 | ||
13653 | void | |
13654 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
13655 | { | |
13656 | if (last_insn.kind != last_insn_directive | |
13657 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
13658 | { | |
13659 | last_insn.seg = now_seg; | |
13660 | last_insn.kind = last_insn_directive; | |
13661 | last_insn.name = "constant directive"; | |
13662 | last_insn.file = as_where (&last_insn.line); | |
ae531041 L |
13663 | if (lfence_before_ret != lfence_before_ret_none) |
13664 | { | |
13665 | if (lfence_before_indirect_branch != lfence_branch_none) | |
13666 | as_warn (_("constant directive skips -mlfence-before-ret " | |
13667 | "and -mlfence-before-indirect-branch")); | |
13668 | else | |
13669 | as_warn (_("constant directive skips -mlfence-before-ret")); | |
13670 | } | |
13671 | else if (lfence_before_indirect_branch != lfence_branch_none) | |
13672 | as_warn (_("constant directive skips -mlfence-before-indirect-branch")); | |
e379e5f3 L |
13673 | } |
13674 | } | |
13675 | ||
252b5132 | 13676 | void |
e3bb37b5 | 13677 | i386_validate_fix (fixS *fixp) |
252b5132 | 13678 | { |
02a86693 | 13679 | if (fixp->fx_subsy) |
252b5132 | 13680 | { |
02a86693 | 13681 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 13682 | { |
02a86693 L |
13683 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
13684 | { | |
13685 | if (!object_64bit) | |
13686 | abort (); | |
13687 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13688 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
13689 | fixp->fx_r_type = (fixp->fx_tcbit |
13690 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
13691 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
13692 | else |
13693 | #endif | |
13694 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
13695 | } | |
d6ab8113 | 13696 | else |
02a86693 L |
13697 | { |
13698 | if (!object_64bit) | |
13699 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
13700 | else | |
13701 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
13702 | } | |
13703 | fixp->fx_subsy = 0; | |
23df1078 | 13704 | } |
252b5132 | 13705 | } |
02a86693 L |
13706 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13707 | else if (!object_64bit) | |
13708 | { | |
13709 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
13710 | && fixp->fx_tcbit2) | |
13711 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
13712 | } | |
13713 | #endif | |
252b5132 RH |
13714 | } |
13715 | ||
252b5132 | 13716 | arelent * |
7016a5d5 | 13717 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13718 | { |
13719 | arelent *rel; | |
13720 | bfd_reloc_code_real_type code; | |
13721 | ||
13722 | switch (fixp->fx_r_type) | |
13723 | { | |
8ce3d284 | 13724 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
13725 | case BFD_RELOC_SIZE32: |
13726 | case BFD_RELOC_SIZE64: | |
13727 | if (S_IS_DEFINED (fixp->fx_addsy) | |
13728 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
13729 | { | |
13730 | /* Resolve size relocation against local symbol to size of | |
13731 | the symbol plus addend. */ | |
13732 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
13733 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
13734 | && !fits_in_unsigned_long (value)) | |
13735 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13736 | _("symbol size computation overflow")); | |
13737 | fixp->fx_addsy = NULL; | |
13738 | fixp->fx_subsy = NULL; | |
13739 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
13740 | return NULL; | |
13741 | } | |
8ce3d284 | 13742 | #endif |
1a0670f3 | 13743 | /* Fall through. */ |
8fd4256d | 13744 | |
3e73aa7c JH |
13745 | case BFD_RELOC_X86_64_PLT32: |
13746 | case BFD_RELOC_X86_64_GOT32: | |
13747 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13748 | case BFD_RELOC_X86_64_GOTPCRELX: |
13749 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
13750 | case BFD_RELOC_386_PLT32: |
13751 | case BFD_RELOC_386_GOT32: | |
02a86693 | 13752 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
13753 | case BFD_RELOC_386_GOTOFF: |
13754 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
13755 | case BFD_RELOC_386_TLS_GD: |
13756 | case BFD_RELOC_386_TLS_LDM: | |
13757 | case BFD_RELOC_386_TLS_LDO_32: | |
13758 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
13759 | case BFD_RELOC_386_TLS_IE: |
13760 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
13761 | case BFD_RELOC_386_TLS_LE_32: |
13762 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
13763 | case BFD_RELOC_386_TLS_GOTDESC: |
13764 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
13765 | case BFD_RELOC_X86_64_TLSGD: |
13766 | case BFD_RELOC_X86_64_TLSLD: | |
13767 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 13768 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
13769 | case BFD_RELOC_X86_64_GOTTPOFF: |
13770 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
13771 | case BFD_RELOC_X86_64_TPOFF64: |
13772 | case BFD_RELOC_X86_64_GOTOFF64: | |
13773 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
13774 | case BFD_RELOC_X86_64_GOT64: |
13775 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13776 | case BFD_RELOC_X86_64_GOTPC64: | |
13777 | case BFD_RELOC_X86_64_GOTPLT64: | |
13778 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
13779 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13780 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
13781 | case BFD_RELOC_RVA: |
13782 | case BFD_RELOC_VTABLE_ENTRY: | |
13783 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
13784 | #ifdef TE_PE |
13785 | case BFD_RELOC_32_SECREL: | |
13786 | #endif | |
252b5132 RH |
13787 | code = fixp->fx_r_type; |
13788 | break; | |
dbbaec26 L |
13789 | case BFD_RELOC_X86_64_32S: |
13790 | if (!fixp->fx_pcrel) | |
13791 | { | |
13792 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
13793 | code = fixp->fx_r_type; | |
13794 | break; | |
13795 | } | |
1a0670f3 | 13796 | /* Fall through. */ |
252b5132 | 13797 | default: |
93382f6d | 13798 | if (fixp->fx_pcrel) |
252b5132 | 13799 | { |
93382f6d AM |
13800 | switch (fixp->fx_size) |
13801 | { | |
13802 | default: | |
b091f402 AM |
13803 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13804 | _("can not do %d byte pc-relative relocation"), | |
13805 | fixp->fx_size); | |
93382f6d AM |
13806 | code = BFD_RELOC_32_PCREL; |
13807 | break; | |
13808 | case 1: code = BFD_RELOC_8_PCREL; break; | |
13809 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 13810 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
13811 | #ifdef BFD64 |
13812 | case 8: code = BFD_RELOC_64_PCREL; break; | |
13813 | #endif | |
93382f6d AM |
13814 | } |
13815 | } | |
13816 | else | |
13817 | { | |
13818 | switch (fixp->fx_size) | |
13819 | { | |
13820 | default: | |
b091f402 AM |
13821 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13822 | _("can not do %d byte relocation"), | |
13823 | fixp->fx_size); | |
93382f6d AM |
13824 | code = BFD_RELOC_32; |
13825 | break; | |
13826 | case 1: code = BFD_RELOC_8; break; | |
13827 | case 2: code = BFD_RELOC_16; break; | |
13828 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 13829 | #ifdef BFD64 |
3e73aa7c | 13830 | case 8: code = BFD_RELOC_64; break; |
937149dd | 13831 | #endif |
93382f6d | 13832 | } |
252b5132 RH |
13833 | } |
13834 | break; | |
13835 | } | |
252b5132 | 13836 | |
d182319b JB |
13837 | if ((code == BFD_RELOC_32 |
13838 | || code == BFD_RELOC_32_PCREL | |
13839 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
13840 | && GOT_symbol |
13841 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 13842 | { |
4fa24527 | 13843 | if (!object_64bit) |
d6ab8113 JB |
13844 | code = BFD_RELOC_386_GOTPC; |
13845 | else | |
13846 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 13847 | } |
7b81dfbb AJ |
13848 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
13849 | && GOT_symbol | |
13850 | && fixp->fx_addsy == GOT_symbol) | |
13851 | { | |
13852 | code = BFD_RELOC_X86_64_GOTPC64; | |
13853 | } | |
252b5132 | 13854 | |
add39d23 TS |
13855 | rel = XNEW (arelent); |
13856 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 13857 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
13858 | |
13859 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 13860 | |
3e73aa7c JH |
13861 | if (!use_rela_relocations) |
13862 | { | |
13863 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
13864 | vtable entry to be used in the relocation's section offset. */ | |
13865 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13866 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
13867 | #if defined (OBJ_COFF) && defined (TE_PE) |
13868 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
13869 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
13870 | else | |
13871 | #endif | |
c6682705 | 13872 | rel->addend = 0; |
3e73aa7c JH |
13873 | } |
13874 | /* Use the rela in 64bit mode. */ | |
252b5132 | 13875 | else |
3e73aa7c | 13876 | { |
862be3fb L |
13877 | if (disallow_64bit_reloc) |
13878 | switch (code) | |
13879 | { | |
862be3fb L |
13880 | case BFD_RELOC_X86_64_DTPOFF64: |
13881 | case BFD_RELOC_X86_64_TPOFF64: | |
13882 | case BFD_RELOC_64_PCREL: | |
13883 | case BFD_RELOC_X86_64_GOTOFF64: | |
13884 | case BFD_RELOC_X86_64_GOT64: | |
13885 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13886 | case BFD_RELOC_X86_64_GOTPC64: | |
13887 | case BFD_RELOC_X86_64_GOTPLT64: | |
13888 | case BFD_RELOC_X86_64_PLTOFF64: | |
13889 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13890 | _("cannot represent relocation type %s in x32 mode"), | |
13891 | bfd_get_reloc_code_name (code)); | |
13892 | break; | |
13893 | default: | |
13894 | break; | |
13895 | } | |
13896 | ||
062cd5e7 AS |
13897 | if (!fixp->fx_pcrel) |
13898 | rel->addend = fixp->fx_offset; | |
13899 | else | |
13900 | switch (code) | |
13901 | { | |
13902 | case BFD_RELOC_X86_64_PLT32: | |
13903 | case BFD_RELOC_X86_64_GOT32: | |
13904 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13905 | case BFD_RELOC_X86_64_GOTPCRELX: |
13906 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
13907 | case BFD_RELOC_X86_64_TLSGD: |
13908 | case BFD_RELOC_X86_64_TLSLD: | |
13909 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
13910 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13911 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
13912 | rel->addend = fixp->fx_offset - fixp->fx_size; |
13913 | break; | |
13914 | default: | |
13915 | rel->addend = (section->vma | |
13916 | - fixp->fx_size | |
13917 | + fixp->fx_addnumber | |
13918 | + md_pcrel_from (fixp)); | |
13919 | break; | |
13920 | } | |
3e73aa7c JH |
13921 | } |
13922 | ||
252b5132 RH |
13923 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
13924 | if (rel->howto == NULL) | |
13925 | { | |
13926 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 13927 | _("cannot represent relocation type %s"), |
252b5132 RH |
13928 | bfd_get_reloc_code_name (code)); |
13929 | /* Set howto to a garbage value so that we can keep going. */ | |
13930 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 13931 | gas_assert (rel->howto != NULL); |
252b5132 RH |
13932 | } |
13933 | ||
13934 | return rel; | |
13935 | } | |
13936 | ||
ee86248c | 13937 | #include "tc-i386-intel.c" |
54cfded0 | 13938 | |
a60de03c JB |
13939 | void |
13940 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 13941 | { |
a60de03c JB |
13942 | int saved_naked_reg; |
13943 | char saved_register_dot; | |
54cfded0 | 13944 | |
a60de03c JB |
13945 | saved_naked_reg = allow_naked_reg; |
13946 | allow_naked_reg = 1; | |
13947 | saved_register_dot = register_chars['.']; | |
13948 | register_chars['.'] = '.'; | |
13949 | allow_pseudo_reg = 1; | |
13950 | expression_and_evaluate (exp); | |
13951 | allow_pseudo_reg = 0; | |
13952 | register_chars['.'] = saved_register_dot; | |
13953 | allow_naked_reg = saved_naked_reg; | |
13954 | ||
e96d56a1 | 13955 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 13956 | { |
a60de03c JB |
13957 | if ((addressT) exp->X_add_number < i386_regtab_size) |
13958 | { | |
13959 | exp->X_op = O_constant; | |
13960 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
13961 | .dw2_regnum[flag_code >> 1]; | |
13962 | } | |
13963 | else | |
13964 | exp->X_op = O_illegal; | |
54cfded0 | 13965 | } |
54cfded0 AM |
13966 | } |
13967 | ||
13968 | void | |
13969 | tc_x86_frame_initial_instructions (void) | |
13970 | { | |
a60de03c JB |
13971 | static unsigned int sp_regno[2]; |
13972 | ||
13973 | if (!sp_regno[flag_code >> 1]) | |
13974 | { | |
13975 | char *saved_input = input_line_pointer; | |
13976 | char sp[][4] = {"esp", "rsp"}; | |
13977 | expressionS exp; | |
a4447b93 | 13978 | |
a60de03c JB |
13979 | input_line_pointer = sp[flag_code >> 1]; |
13980 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 13981 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
13982 | sp_regno[flag_code >> 1] = exp.X_add_number; |
13983 | input_line_pointer = saved_input; | |
13984 | } | |
a4447b93 | 13985 | |
61ff971f L |
13986 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
13987 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 13988 | } |
d2b2c203 | 13989 | |
d7921315 L |
13990 | int |
13991 | x86_dwarf2_addr_size (void) | |
13992 | { | |
13993 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
13994 | if (x86_elf_abi == X86_64_X32_ABI) | |
13995 | return 4; | |
13996 | #endif | |
13997 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
13998 | } | |
13999 | ||
d2b2c203 DJ |
14000 | int |
14001 | i386_elf_section_type (const char *str, size_t len) | |
14002 | { | |
14003 | if (flag_code == CODE_64BIT | |
14004 | && len == sizeof ("unwind") - 1 | |
14005 | && strncmp (str, "unwind", 6) == 0) | |
14006 | return SHT_X86_64_UNWIND; | |
14007 | ||
14008 | return -1; | |
14009 | } | |
bb41ade5 | 14010 | |
ad5fec3b EB |
14011 | #ifdef TE_SOLARIS |
14012 | void | |
14013 | i386_solaris_fix_up_eh_frame (segT sec) | |
14014 | { | |
14015 | if (flag_code == CODE_64BIT) | |
14016 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
14017 | } | |
14018 | #endif | |
14019 | ||
bb41ade5 AM |
14020 | #ifdef TE_PE |
14021 | void | |
14022 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
14023 | { | |
91d6fa6a | 14024 | expressionS exp; |
bb41ade5 | 14025 | |
91d6fa6a NC |
14026 | exp.X_op = O_secrel; |
14027 | exp.X_add_symbol = symbol; | |
14028 | exp.X_add_number = 0; | |
14029 | emit_expr (&exp, size); | |
bb41ade5 AM |
14030 | } |
14031 | #endif | |
3b22753a L |
14032 | |
14033 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14034 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
14035 | ||
01e1a5bc | 14036 | bfd_vma |
6d4af3c2 | 14037 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
14038 | { |
14039 | if (flag_code == CODE_64BIT) | |
14040 | { | |
14041 | if (letter == 'l') | |
14042 | return SHF_X86_64_LARGE; | |
14043 | ||
8f3bae45 | 14044 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 14045 | } |
3b22753a | 14046 | else |
8f3bae45 | 14047 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
14048 | return -1; |
14049 | } | |
14050 | ||
01e1a5bc | 14051 | bfd_vma |
3b22753a L |
14052 | x86_64_section_word (char *str, size_t len) |
14053 | { | |
8620418b | 14054 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
14055 | return SHF_X86_64_LARGE; |
14056 | ||
14057 | return -1; | |
14058 | } | |
14059 | ||
14060 | static void | |
14061 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
14062 | { | |
14063 | if (flag_code != CODE_64BIT) | |
14064 | { | |
14065 | s_comm_internal (0, elf_common_parse); | |
14066 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
14067 | } | |
14068 | else | |
14069 | { | |
14070 | static segT lbss_section; | |
14071 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
14072 | asection *saved_bss_section = bss_section; | |
14073 | ||
14074 | if (lbss_section == NULL) | |
14075 | { | |
14076 | flagword applicable; | |
14077 | segT seg = now_seg; | |
14078 | subsegT subseg = now_subseg; | |
14079 | ||
14080 | /* The .lbss section is for local .largecomm symbols. */ | |
14081 | lbss_section = subseg_new (".lbss", 0); | |
14082 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 14083 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
14084 | seg_info (lbss_section)->bss = 1; |
14085 | ||
14086 | subseg_set (seg, subseg); | |
14087 | } | |
14088 | ||
14089 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
14090 | bss_section = lbss_section; | |
14091 | ||
14092 | s_comm_internal (0, elf_common_parse); | |
14093 | ||
14094 | elf_com_section_ptr = saved_com_section_ptr; | |
14095 | bss_section = saved_bss_section; | |
14096 | } | |
14097 | } | |
14098 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |