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Add dependencies to configure rule
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
d3ce72d0 176static const insn_template *match_template (void);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132
RH		 328
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes;
332 unsigned char prefix[MAX_PREFIXES];
333
334 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 335 addressing modes of this insn are encoded. */
252b5132 336 modrm_byte rm;
3e73aa7c 337 rex_byte rex;
43234a1e 338 rex_byte vrex;
252b5132 339 sib_byte sib;
c0f3af97 340 vex_prefix vex;
b6169b20 341
43234a1e
L		 342 /* Masking attributes. */
343 struct Mask_Operation *mask;
344
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation *rounding;
347
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation *broadcast;
350
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift;
353
b6169b20 354 /* Swap operand in encoding. */
4473e004 355 unsigned int swap_operand;
891edac4 356
a501d77e
L		 357 /* Prefer 8bit or 32bit displacement in encoding. */
358 enum
359 {
360 disp_encoding_default = 0,
361 disp_encoding_8bit,
362 disp_encoding_32bit
363 } disp_encoding;
f8a5c266 364
d5de92cf
L		 365 /* REP prefix. */
366 const char *rep_prefix;
367
165de32a
L		 368 /* HLE prefix. */
369 const char *hle_prefix;
42164a71 370
7e8b059b
L		 371 /* Have BND prefix. */
372 const char *bnd_prefix;
373
43234a1e
L		 374 /* Need VREX to support upper 16 registers. */
375 int need_vrex;
376
891edac4 377 /* Error message. */
a65babc9 378 enum i386_error error;
252b5132
RH		 379 };
380
381typedef struct _i386_insn i386_insn;
382
43234a1e
L		 383/* Link RC type with corresponding string, that'll be looked for in
384 asm. */
385struct RC_name
386{
387 enum rc_type type;
388 const char *name;
389 unsigned int len;
390};
391
392static const struct RC_name RC_NamesTable[] =
393{
394 { rne, STRING_COMMA_LEN ("rn-sae") },
395 { rd, STRING_COMMA_LEN ("rd-sae") },
396 { ru, STRING_COMMA_LEN ("ru-sae") },
397 { rz, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly, STRING_COMMA_LEN ("sae") },
399};
400
252b5132
RH		 401/* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 403const char extra_symbol_chars[] = "*%-([{"
252b5132 404#ifdef LEX_AT
32137342
NC		 405 "@"
406#endif
407#ifdef LEX_QM
408 "?"
252b5132 409#endif
32137342 410 ;
252b5132 411
29b0f896
AM		 412#if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 414 && !defined (TE_GNU) \
29b0f896 415 && !defined (TE_LINUX) \
8d63c93e
RM		 416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
29b0f896 418 && !defined (TE_FreeBSD) \
5b806d27 419 && !defined (TE_DragonFly) \
29b0f896 420 && !defined (TE_NetBSD)))
252b5132 421/* This array holds the chars that always start a comment. If the
b3b91714
AM		 422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424const char *i386_comment_chars = "#/";
425#define SVR4_COMMENT_CHARS 1
252b5132 426#define PREFIX_SEPARATOR '\\'
252b5132 427
b3b91714
AM		 428#else
429const char *i386_comment_chars = "#";
430#define PREFIX_SEPARATOR '/'
431#endif
432
252b5132
RH		 433/* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 437 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
252b5132 440 '/' isn't otherwise defined. */
b3b91714 441const char line_comment_chars[] = "#/";
252b5132 442
63a0b638 443const char line_separator_chars[] = ";";
252b5132 444
ce8a8b2f
AM		 445/* Chars that can be used to separate mant from exp in floating point
446 nums. */
252b5132
RH		 447const char EXP_CHARS[] = "eE";
448
ce8a8b2f
AM		 449/* Chars that mean this number is a floating point constant
450 As in 0f12.456
451 or 0d1.2345e12. */
252b5132
RH		 452const char FLT_CHARS[] = "fFdDxX";
453
ce8a8b2f 454/* Tables for lexical analysis. */
252b5132
RH		 455static char mnemonic_chars[256];
456static char register_chars[256];
457static char operand_chars[256];
458static char identifier_chars[256];
459static char digit_chars[256];
460
ce8a8b2f 461/* Lexical macros. */
252b5132
RH		 462#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463#define is_operand_char(x) (operand_chars[(unsigned char) x])
464#define is_register_char(x) (register_chars[(unsigned char) x])
465#define is_space_char(x) ((x) == ' ')
466#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467#define is_digit_char(x) (digit_chars[(unsigned char) x])
468
0234cb7c 469/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 470static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
471
472/* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
47926f60 475 assembler instruction). */
252b5132 476static char save_stack[32];
ce8a8b2f 477static char *save_stack_p;
252b5132
RH		 478#define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480#define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
482
47926f60 483/* The instruction we're assembling. */
252b5132
RH		 484static i386_insn i;
485
486/* Possible templates for current insn. */
487static const templates *current_templates;
488
31b2323c
L		 489/* Per instruction expressionS buffers: max displacements & immediates. */
490static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
491static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 492
47926f60 493/* Current operand we are working on. */
ee86248c 494static int this_operand = -1;
252b5132 495
3e73aa7c
JH		 496/* We support four different modes. FLAG_CODE variable is used to distinguish
497 these. */
498
499enum flag_code {
500 CODE_32BIT,
501 CODE_16BIT,
502 CODE_64BIT };
503
504static enum flag_code flag_code;
4fa24527 505static unsigned int object_64bit;
862be3fb 506static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 507static int use_rela_relocations = 0;
508
7af8ed2d
NC		 509#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
512
351f65ca
L		 513/* The ELF ABI to use. */
514enum x86_elf_abi
515{
516 I386_ABI,
7f56bc95
L		 517 X86_64_ABI,
518 X86_64_X32_ABI
351f65ca
L		 519};
520
521static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 522#endif
351f65ca 523
167ad85b
TG		 524#if defined (TE_PE) || defined (TE_PEP)
525/* Use big object file format. */
526static int use_big_obj = 0;
527#endif
528
8dcea932
L		 529#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530/* 1 if generating code for a shared library. */
531static int shared = 0;
532#endif
533
47926f60
KH		 534/* 1 for intel syntax,
535 0 if att syntax. */
536static int intel_syntax = 0;
252b5132 537
e89c5eaa
L		 538/* 1 for Intel64 ISA,
539 0 if AMD64 ISA. */
540static int intel64;
541
1efbbeb4
L		 542/* 1 for intel mnemonic,
543 0 if att mnemonic. */
544static int intel_mnemonic = !SYSV386_COMPAT;
545
5209009a 546/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 547static int old_gcc = OLDGCC_COMPAT;
548
a60de03c
JB		 549/* 1 if pseudo registers are permitted. */
550static int allow_pseudo_reg = 0;
551
47926f60
KH		 552/* 1 if register prefix % not required. */
553static int allow_naked_reg = 0;
252b5132 554
7e8b059b
L		 555/* 1 if the assembler should add BND prefix for all control-tranferring
556 instructions supporting it, even if this prefix wasn't specified
557 explicitly. */
558static int add_bnd_prefix = 0;
559
ba104c83 560/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 561static int allow_index_reg = 0;
562
d022bddd
IT		 563/* 1 if the assembler should ignore LOCK prefix, even if it was
564 specified explicitly. */
565static int omit_lock_prefix = 0;
566
e4e00185
AS		 567/* 1 if the assembler should encode lfence, mfence, and sfence as
568 "lock addl $0, (%{re}sp)". */
569static int avoid_fence = 0;
570
0cb4071e
L		 571/* 1 if the assembler should generate relax relocations. */
572
573static int generate_relax_relocations
574 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
575
7bab8ab5 576static enum check_kind
daf50ae7 577 {
7bab8ab5
JB		 578 check_none = 0,
579 check_warning,
580 check_error
daf50ae7 581 }
7bab8ab5 582sse_check, operand_check = check_warning;
daf50ae7 583
2ca3ace5
L		 584/* Register prefix used for error message. */
585static const char *register_prefix = "%";
586
47926f60
KH		 587/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
588 leave, push, and pop instructions so that gcc has the same stack
589 frame as in 32 bit mode. */
590static char stackop_size = '\0';
eecb386c 591
12b55ccc
L		 592/* Non-zero to optimize code alignment. */
593int optimize_align_code = 1;
594
47926f60
KH		 595/* Non-zero to quieten some warnings. */
596static int quiet_warnings = 0;
a38cf1db 597
47926f60
KH		 598/* CPU name. */
599static const char *cpu_arch_name = NULL;
6305a203 600static char *cpu_sub_arch_name = NULL;
a38cf1db 601
47926f60 602/* CPU feature flags. */
40fb9820
L		 603static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
604
ccc9c027
L		 605/* If we have selected a cpu we are generating instructions for. */
606static int cpu_arch_tune_set = 0;
607
9103f4f4 608/* Cpu we are generating instructions for. */
fbf3f584 609enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 610
611/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 612static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 613
ccc9c027 614/* CPU instruction set architecture used. */
fbf3f584 615enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 616
9103f4f4 617/* CPU feature flags of instruction set architecture used. */
fbf3f584 618i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 619
fddf5b5b
AM		 620/* If set, conditional jumps are not automatically promoted to handle
621 larger than a byte offset. */
622static unsigned int no_cond_jump_promotion = 0;
623
c0f3af97
L		 624/* Encode SSE instructions with VEX prefix. */
625static unsigned int sse2avx;
626
539f890d
L		 627/* Encode scalar AVX instructions with specific vector length. */
628static enum
629 {
630 vex128 = 0,
631 vex256
632 } avxscalar;
633
43234a1e
L		 634/* Encode scalar EVEX LIG instructions with specific vector length. */
635static enum
636 {
637 evexl128 = 0,
638 evexl256,
639 evexl512
640 } evexlig;
641
642/* Encode EVEX WIG instructions with specific evex.w. */
643static enum
644 {
645 evexw0 = 0,
646 evexw1
647 } evexwig;
648
d3d3c6db
IT		 649/* Value to encode in EVEX RC bits, for SAE-only instructions. */
650static enum rc_type evexrcig = rne;
651
29b0f896 652/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 653static symbolS *GOT_symbol;
29b0f896 654
a4447b93
RH		 655/* The dwarf2 return column, adjusted for 32 or 64 bit. */
656unsigned int x86_dwarf2_return_column;
657
658/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
659int x86_cie_data_alignment;
660
252b5132 661/* Interface to relax_segment.
fddf5b5b
AM		 662 There are 3 major relax states for 386 jump insns because the
663 different types of jumps add different sizes to frags when we're
664 figuring out what sort of jump to choose to reach a given label. */
252b5132 665
47926f60 666/* Types. */
93c2a809
AM		 667#define UNCOND_JUMP 0
668#define COND_JUMP 1
669#define COND_JUMP86 2
fddf5b5b 670
47926f60 671/* Sizes. */
252b5132
RH		 672#define CODE16 1
673#define SMALL 0
29b0f896 674#define SMALL16 (SMALL | CODE16)
252b5132 675#define BIG 2
29b0f896 676#define BIG16 (BIG | CODE16)
252b5132
RH		 677
678#ifndef INLINE
679#ifdef __GNUC__
680#define INLINE __inline__
681#else
682#define INLINE
683#endif
684#endif
685
fddf5b5b
AM		 686#define ENCODE_RELAX_STATE(type, size) \
687 ((relax_substateT) (((type) << 2) | (size)))
688#define TYPE_FROM_RELAX_STATE(s) \
689 ((s) >> 2)
690#define DISP_SIZE_FROM_RELAX_STATE(s) \
691 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 692
693/* This table is used by relax_frag to promote short jumps to long
694 ones where necessary. SMALL (short) jumps may be promoted to BIG
695 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
696 don't allow a short jump in a 32 bit code segment to be promoted to
697 a 16 bit offset jump because it's slower (requires data size
698 prefix), and doesn't work, unless the destination is in the bottom
699 64k of the code segment (The top 16 bits of eip are zeroed). */
700
701const relax_typeS md_relax_table[] =
702{
24eab124
AM		 703 /* The fields are:
704 1) most positive reach of this state,
705 2) most negative reach of this state,
93c2a809 706 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 707 4) which index into the table to try if we can't fit into this one. */
252b5132 708
fddf5b5b 709 /* UNCOND_JUMP states. */
93c2a809
AM		 710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
712 /* dword jmp adds 4 bytes to frag:
713 0 extra opcode bytes, 4 displacement bytes. */
252b5132 714 {0, 0, 4, 0},
93c2a809
AM		 715 /* word jmp adds 2 byte2 to frag:
716 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 717 {0, 0, 2, 0},
718
93c2a809
AM		 719 /* COND_JUMP states. */
720 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
721 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
722 /* dword conditionals adds 5 bytes to frag:
723 1 extra opcode byte, 4 displacement bytes. */
724 {0, 0, 5, 0},
fddf5b5b 725 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 726 1 extra opcode byte, 2 displacement bytes. */
727 {0, 0, 3, 0},
728
729 /* COND_JUMP86 states. */
730 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
731 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
732 /* dword conditionals adds 5 bytes to frag:
733 1 extra opcode byte, 4 displacement bytes. */
734 {0, 0, 5, 0},
735 /* word conditionals add 4 bytes to frag:
736 1 displacement byte and a 3 byte long branch insn. */
737 {0, 0, 4, 0}
252b5132
RH		 738};
739
9103f4f4
L		 740static const arch_entry cpu_arch[] =
741{
89507696
JB		 742 /* Do not replace the first two entries - i386_target_format()
743 relies on them being there in this order. */
8a2c8fef 744 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 745 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 747 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 749 CPU_NONE_FLAGS, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 751 CPU_I186_FLAGS, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 753 CPU_I286_FLAGS, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 755 CPU_I386_FLAGS, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 757 CPU_I486_FLAGS, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 759 CPU_I586_FLAGS, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 761 CPU_I686_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 763 CPU_I586_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 765 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 767 CPU_P2_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 769 CPU_P3_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 771 CPU_P4_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 773 CPU_CORE_FLAGS, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 775 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 777 CPU_CORE_FLAGS, 1 },
8a2c8fef 778 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 779 CPU_CORE_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 781 CPU_CORE2_FLAGS, 1 },
8a2c8fef 782 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 783 CPU_CORE2_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 785 CPU_COREI7_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 787 CPU_L1OM_FLAGS, 0 },
7a9068fe 788 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 789 CPU_K1OM_FLAGS, 0 },
81486035 790 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 791 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 793 CPU_K6_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 795 CPU_K6_2_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 797 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 799 CPU_K8_FLAGS, 1 },
8a2c8fef 800 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 801 CPU_K8_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 803 CPU_K8_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 805 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 806 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 807 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 808 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 809 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 810 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 811 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 812 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 813 CPU_BDVER4_FLAGS, 0 },
029f3522 814 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 815 CPU_ZNVER1_FLAGS, 0 },
7b458c12 816 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 817 CPU_BTVER1_FLAGS, 0 },
7b458c12 818 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 819 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 821 CPU_8087_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 823 CPU_287_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 825 CPU_387_FLAGS, 0 },
1848e567
L		 826 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
827 CPU_687_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 829 CPU_MMX_FLAGS, 0 },
8a2c8fef 830 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 831 CPU_SSE_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 833 CPU_SSE2_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 835 CPU_SSE3_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 840 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 841 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 842 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 843 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_AVX_FLAGS, 0 },
6c30d220 846 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_AVX2_FLAGS, 0 },
43234a1e 848 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_AVX512F_FLAGS, 0 },
43234a1e 850 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_AVX512CD_FLAGS, 0 },
43234a1e 852 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_AVX512ER_FLAGS, 0 },
43234a1e 854 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 856 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 858 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 860 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_VMX_FLAGS, 0 },
8729a6f6 864 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_SMX_FLAGS, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 870 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 872 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 874 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AES_FLAGS, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 880 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 882 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 884 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 886 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_F16C_FLAGS, 0 },
6c30d220 888 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_BMI2_FLAGS, 0 },
8a2c8fef 890 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_FMA_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_FMA4_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_XOP_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_LWP_FLAGS, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_MOVBE_FLAGS, 0 },
60aa667e 900 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_CX16_FLAGS, 0 },
8a2c8fef 902 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_EPT_FLAGS, 0 },
6c30d220 904 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_LZCNT_FLAGS, 0 },
42164a71 906 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_HLE_FLAGS, 0 },
42164a71 908 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_RTM_FLAGS, 0 },
6c30d220 910 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_CLFLUSH_FLAGS, 0 },
22109423 914 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_NOP_FLAGS, 0 },
8a2c8fef 916 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 920 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_SVME_FLAGS, 1 },
8a2c8fef 928 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_SVME_FLAGS, 0 },
8a2c8fef 930 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_ABM_FLAGS, 0 },
87973e9f 934 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_BMI_FLAGS, 0 },
2a2a0f38 936 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_TBM_FLAGS, 0 },
e2e1fcde 938 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_ADX_FLAGS, 0 },
e2e1fcde 940 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 942 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_PRFCHW_FLAGS, 0 },
5c111e37 944 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_SMAP_FLAGS, 0 },
7e8b059b 946 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_MPX_FLAGS, 0 },
a0046408 948 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_SHA_FLAGS, 0 },
963f3586 950 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 952 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 954 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_SE1_FLAGS, 0 },
c5e7287a 956 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_CLWB_FLAGS, 0 },
9d8596f0 958 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_PCOMMIT_FLAGS, 0 },
2cc1b5aa 960 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 962 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_AVX512VBMI_FLAGS, 0 },
029f3522 964 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_CLZERO_FLAGS, 0 },
9916071f 966 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_MWAITX_FLAGS, 0 },
8eab4136 968 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_OSPKE_FLAGS, 0 },
8bc52696 970 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65
L		 971 CPU_RDPID_FLAGS, 0 },
972};
973
974static const noarch_entry cpu_noarch[] =
975{
976 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 977 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
978 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
979 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 980 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
981 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 982 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
983 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
984 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
985 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
986 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
987 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 988 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 989 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
e413e4e9
AM		 990};
991
704209c0 992#ifdef I386COFF
a6c24e68
NC		 993/* Like s_lcomm_internal in gas/read.c but the alignment string
994 is allowed to be optional. */
995
996static symbolS *
997pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
998{
999 addressT align = 0;
1000
1001 SKIP_WHITESPACE ();
1002
7ab9ffdd 1003 if (needs_align
a6c24e68
NC		 1004 && *input_line_pointer == ',')
1005 {
1006 align = parse_align (needs_align - 1);
7ab9ffdd 1007
a6c24e68
NC		 1008 if (align == (addressT) -1)
1009 return NULL;
1010 }
1011 else
1012 {
1013 if (size >= 8)
1014 align = 3;
1015 else if (size >= 4)
1016 align = 2;
1017 else if (size >= 2)
1018 align = 1;
1019 else
1020 align = 0;
1021 }
1022
1023 bss_alloc (symbolP, size, align);
1024 return symbolP;
1025}
1026
704209c0 1027static void
a6c24e68
NC		 1028pe_lcomm (int needs_align)
1029{
1030 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1031}
704209c0 1032#endif
a6c24e68 1033
29b0f896
AM		 1034const pseudo_typeS md_pseudo_table[] =
1035{
1036#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1037 {"align", s_align_bytes, 0},
1038#else
1039 {"align", s_align_ptwo, 0},
1040#endif
1041 {"arch", set_cpu_arch, 0},
1042#ifndef I386COFF
1043 {"bss", s_bss, 0},
a6c24e68
NC		 1044#else
1045 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1046#endif
1047 {"ffloat", float_cons, 'f'},
1048 {"dfloat", float_cons, 'd'},
1049 {"tfloat", float_cons, 'x'},
1050 {"value", cons, 2},
d182319b 1051 {"slong", signed_cons, 4},
29b0f896
AM		 1052 {"noopt", s_ignore, 0},
1053 {"optim", s_ignore, 0},
1054 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1055 {"code16", set_code_flag, CODE_16BIT},
1056 {"code32", set_code_flag, CODE_32BIT},
1057 {"code64", set_code_flag, CODE_64BIT},
1058 {"intel_syntax", set_intel_syntax, 1},
1059 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1060 {"intel_mnemonic", set_intel_mnemonic, 1},
1061 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1062 {"allow_index_reg", set_allow_index_reg, 1},
1063 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1064 {"sse_check", set_check, 0},
1065 {"operand_check", set_check, 1},
3b22753a
L		 1066#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1067 {"largecomm", handle_large_common, 0},
07a53e5c 1068#else
e3bb37b5 1069 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1070 {"loc", dwarf2_directive_loc, 0},
1071 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1072#endif
6482c264
NC		 1073#ifdef TE_PE
1074 {"secrel32", pe_directive_secrel, 0},
1075#endif
29b0f896
AM		 1076 {0, 0, 0}
1077};
1078
1079/* For interface with expression (). */
1080extern char *input_line_pointer;
1081
1082/* Hash table for instruction mnemonic lookup. */
1083static struct hash_control *op_hash;
1084
1085/* Hash table for register lookup. */
1086static struct hash_control *reg_hash;
1087\f
252b5132 1088void
e3bb37b5 1089i386_align_code (fragS *fragP, int count)
252b5132 1090{
ce8a8b2f
AM		 1091 /* Various efficient no-op patterns for aligning code labels.
1092 Note: Don't try to assemble the instructions in the comments.
1093 0L and 0w are not legal. */
bad6e36d 1094 static const unsigned char f32_1[] =
252b5132 1095 {0x90}; /* nop */
bad6e36d 1096 static const unsigned char f32_2[] =
ccc9c027 1097 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1098 static const unsigned char f32_3[] =
252b5132 1099 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1100 static const unsigned char f32_4[] =
252b5132 1101 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1102 static const unsigned char f32_5[] =
252b5132
RH		 1103 {0x90, /* nop */
1104 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1105 static const unsigned char f32_6[] =
252b5132 1106 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1107 static const unsigned char f32_7[] =
252b5132 1108 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1109 static const unsigned char f32_8[] =
252b5132
RH		 1110 {0x90, /* nop */
1111 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1112 static const unsigned char f32_9[] =
252b5132
RH		 1113 {0x89,0xf6, /* movl %esi,%esi */
1114 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1115 static const unsigned char f32_10[] =
252b5132
RH		 1116 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1117 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1118 static const unsigned char f32_11[] =
252b5132
RH		 1119 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1120 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1121 static const unsigned char f32_12[] =
252b5132
RH		 1122 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1123 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1124 static const unsigned char f32_13[] =
252b5132
RH		 1125 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1126 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1127 static const unsigned char f32_14[] =
252b5132
RH		 1128 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1129 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1130 static const unsigned char f16_3[] =
c3332e24 1131 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1132 static const unsigned char f16_4[] =
252b5132 1133 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1134 static const unsigned char f16_5[] =
252b5132
RH		 1135 {0x90, /* nop */
1136 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1137 static const unsigned char f16_6[] =
252b5132
RH		 1138 {0x89,0xf6, /* mov %si,%si */
1139 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1140 static const unsigned char f16_7[] =
252b5132
RH		 1141 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1142 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1143 static const unsigned char f16_8[] =
252b5132
RH		 1144 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1145 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1146 static const unsigned char jump_31[] =
76bc74dc
L		 1147 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1148 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1149 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1150 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1151 static const unsigned char *const f32_patt[] = {
252b5132 1152 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1153 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1154 };
bad6e36d 1155 static const unsigned char *const f16_patt[] = {
76bc74dc 1156 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1157 };
ccc9c027 1158 /* nopl (%[re]ax) */
bad6e36d 1159 static const unsigned char alt_3[] =
ccc9c027
L		 1160 {0x0f,0x1f,0x00};
1161 /* nopl 0(%[re]ax) */
bad6e36d 1162 static const unsigned char alt_4[] =
ccc9c027
L		 1163 {0x0f,0x1f,0x40,0x00};
1164 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1165 static const unsigned char alt_5[] =
ccc9c027
L		 1166 {0x0f,0x1f,0x44,0x00,0x00};
1167 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1168 static const unsigned char alt_6[] =
ccc9c027
L		 1169 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1170 /* nopl 0L(%[re]ax) */
bad6e36d 1171 static const unsigned char alt_7[] =
ccc9c027
L		 1172 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1173 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1174 static const unsigned char alt_8[] =
ccc9c027
L		 1175 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1176 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1177 static const unsigned char alt_9[] =
ccc9c027
L		 1178 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1179 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1180 static const unsigned char alt_10[] =
ccc9c027 1181 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1182 static const unsigned char *const alt_patt[] = {
ccc9c027 1183 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1184 alt_9, alt_10
ccc9c027 1185 };
252b5132 1186
76bc74dc
L		 1187 /* Only align for at least a positive non-zero boundary. */
1188 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1189 return;
3e73aa7c 1190
ccc9c027
L		 1191 /* We need to decide which NOP sequence to use for 32bit and
1192 64bit. When -mtune= is used:
4eed87de 1193
76bc74dc
L		 1194 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1195 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1196 2. For the rest, alt_patt will be used.
1197
1198 When -mtune= isn't used, alt_patt will be used if
22109423 1199 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1200 be used.
ccc9c027
L		 1201
1202 When -march= or .arch is used, we can't use anything beyond
1203 cpu_arch_isa_flags. */
1204
1205 if (flag_code == CODE_16BIT)
1206 {
ccc9c027 1207 if (count > 8)
33fef721 1208 {
76bc74dc
L		 1209 memcpy (fragP->fr_literal + fragP->fr_fix,
1210 jump_31, count);
1211 /* Adjust jump offset. */
1212 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1213 }
76bc74dc
L		 1214 else
1215 memcpy (fragP->fr_literal + fragP->fr_fix,
1216 f16_patt[count - 1], count);
252b5132 1217 }
33fef721 1218 else
ccc9c027 1219 {
bad6e36d 1220 const unsigned char *const *patt = NULL;
ccc9c027 1221
fbf3f584 1222 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1223 {
1224 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1225 switch (cpu_arch_tune)
1226 {
1227 case PROCESSOR_UNKNOWN:
1228 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1229 optimize with nops. */
1230 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1231 patt = alt_patt;
ccc9c027
L		 1232 else
1233 patt = f32_patt;
1234 break;
ccc9c027
L		 1235 case PROCESSOR_PENTIUM4:
1236 case PROCESSOR_NOCONA:
ef05d495 1237 case PROCESSOR_CORE:
76bc74dc 1238 case PROCESSOR_CORE2:
bd5295b2 1239 case PROCESSOR_COREI7:
3632d14b 1240 case PROCESSOR_L1OM:
7a9068fe 1241 case PROCESSOR_K1OM:
76bc74dc 1242 case PROCESSOR_GENERIC64:
ccc9c027
L		 1243 case PROCESSOR_K6:
1244 case PROCESSOR_ATHLON:
1245 case PROCESSOR_K8:
4eed87de 1246 case PROCESSOR_AMDFAM10:
8aedb9fe 1247 case PROCESSOR_BD:
029f3522 1248 case PROCESSOR_ZNVER:
7b458c12 1249 case PROCESSOR_BT:
80b8656c 1250 patt = alt_patt;
ccc9c027 1251 break;
76bc74dc 1252 case PROCESSOR_I386:
ccc9c027
L		 1253 case PROCESSOR_I486:
1254 case PROCESSOR_PENTIUM:
2dde1948 1255 case PROCESSOR_PENTIUMPRO:
81486035 1256 case PROCESSOR_IAMCU:
ccc9c027
L		 1257 case PROCESSOR_GENERIC32:
1258 patt = f32_patt;
1259 break;
4eed87de 1260 }
ccc9c027
L		 1261 }
1262 else
1263 {
fbf3f584 1264 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1265 {
1266 case PROCESSOR_UNKNOWN:
e6a14101 1267 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1268 PROCESSOR_UNKNOWN. */
1269 abort ();
1270 break;
1271
76bc74dc 1272 case PROCESSOR_I386:
ccc9c027
L		 1273 case PROCESSOR_I486:
1274 case PROCESSOR_PENTIUM:
81486035 1275 case PROCESSOR_IAMCU:
ccc9c027
L		 1276 case PROCESSOR_K6:
1277 case PROCESSOR_ATHLON:
1278 case PROCESSOR_K8:
4eed87de 1279 case PROCESSOR_AMDFAM10:
8aedb9fe 1280 case PROCESSOR_BD:
029f3522 1281 case PROCESSOR_ZNVER:
7b458c12 1282 case PROCESSOR_BT:
ccc9c027
L		 1283 case PROCESSOR_GENERIC32:
1284 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1285 with nops. */
1286 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1287 patt = alt_patt;
ccc9c027
L		 1288 else
1289 patt = f32_patt;
1290 break;
76bc74dc
L		 1291 case PROCESSOR_PENTIUMPRO:
1292 case PROCESSOR_PENTIUM4:
1293 case PROCESSOR_NOCONA:
1294 case PROCESSOR_CORE:
ef05d495 1295 case PROCESSOR_CORE2:
bd5295b2 1296 case PROCESSOR_COREI7:
3632d14b 1297 case PROCESSOR_L1OM:
7a9068fe 1298 case PROCESSOR_K1OM:
22109423 1299 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1300 patt = alt_patt;
ccc9c027
L		 1301 else
1302 patt = f32_patt;
1303 break;
1304 case PROCESSOR_GENERIC64:
80b8656c 1305 patt = alt_patt;
ccc9c027 1306 break;
4eed87de 1307 }
ccc9c027
L		 1308 }
1309
76bc74dc
L		 1310 if (patt == f32_patt)
1311 {
1312 /* If the padding is less than 15 bytes, we use the normal
1313 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1314 its offset. */
1315 int limit;
76ba9986 1316
711eedef
L		 1317 /* For 64bit, the limit is 3 bytes. */
1318 if (flag_code == CODE_64BIT
1319 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1320 limit = 3;
1321 else
1322 limit = 15;
1323 if (count < limit)
76bc74dc
L		 1324 memcpy (fragP->fr_literal + fragP->fr_fix,
1325 patt[count - 1], count);
1326 else
1327 {
1328 memcpy (fragP->fr_literal + fragP->fr_fix,
1329 jump_31, count);
1330 /* Adjust jump offset. */
1331 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1332 }
1333 }
1334 else
1335 {
80b8656c
L		 1336 /* Maximum length of an instruction is 10 byte. If the
1337 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1338 we have to break it into smaller pieces. */
1339 int padding = count;
80b8656c 1340 while (padding > 10)
76bc74dc 1341 {
80b8656c 1342 padding -= 10;
76bc74dc 1343 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1344 patt [9], 10);
76bc74dc
L		 1345 }
1346
1347 if (padding)
1348 memcpy (fragP->fr_literal + fragP->fr_fix,
1349 patt [padding - 1], padding);
1350 }
ccc9c027 1351 }
33fef721 1352 fragP->fr_var = count;
252b5132
RH		 1353}
1354
c6fb90c8 1355static INLINE int
0dfbf9d7 1356operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1357{
0dfbf9d7 1358 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1359 {
1360 case 3:
0dfbf9d7 1361 if (x->array[2])
c6fb90c8
L		 1362 return 0;
1363 case 2:
0dfbf9d7 1364 if (x->array[1])
c6fb90c8
L		 1365 return 0;
1366 case 1:
0dfbf9d7 1367 return !x->array[0];
c6fb90c8
L		 1368 default:
1369 abort ();
1370 }
40fb9820
L		 1371}
1372
c6fb90c8 1373static INLINE void
0dfbf9d7 1374operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1375{
0dfbf9d7 1376 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1377 {
1378 case 3:
0dfbf9d7 1379 x->array[2] = v;
c6fb90c8 1380 case 2:
0dfbf9d7 1381 x->array[1] = v;
c6fb90c8 1382 case 1:
0dfbf9d7 1383 x->array[0] = v;
c6fb90c8
L		 1384 break;
1385 default:
1386 abort ();
1387 }
1388}
40fb9820 1389
c6fb90c8 1390static INLINE int
0dfbf9d7
L		 1391operand_type_equal (const union i386_operand_type *x,
1392 const union i386_operand_type *y)
c6fb90c8 1393{
0dfbf9d7 1394 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1395 {
1396 case 3:
0dfbf9d7 1397 if (x->array[2] != y->array[2])
c6fb90c8
L		 1398 return 0;
1399 case 2:
0dfbf9d7 1400 if (x->array[1] != y->array[1])
c6fb90c8
L		 1401 return 0;
1402 case 1:
0dfbf9d7 1403 return x->array[0] == y->array[0];
c6fb90c8
L		 1404 break;
1405 default:
1406 abort ();
1407 }
1408}
40fb9820 1409
0dfbf9d7
L		 1410static INLINE int
1411cpu_flags_all_zero (const union i386_cpu_flags *x)
1412{
1413 switch (ARRAY_SIZE(x->array))
1414 {
1415 case 3:
1416 if (x->array[2])
1417 return 0;
1418 case 2:
1419 if (x->array[1])
1420 return 0;
1421 case 1:
1422 return !x->array[0];
1423 default:
1424 abort ();
1425 }
1426}
1427
0dfbf9d7
L		 1428static INLINE int
1429cpu_flags_equal (const union i386_cpu_flags *x,
1430 const union i386_cpu_flags *y)
1431{
1432 switch (ARRAY_SIZE(x->array))
1433 {
1434 case 3:
1435 if (x->array[2] != y->array[2])
1436 return 0;
1437 case 2:
1438 if (x->array[1] != y->array[1])
1439 return 0;
1440 case 1:
1441 return x->array[0] == y->array[0];
1442 break;
1443 default:
1444 abort ();
1445 }
1446}
c6fb90c8
L		 1447
1448static INLINE int
1449cpu_flags_check_cpu64 (i386_cpu_flags f)
1450{
1451 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1452 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1453}
1454
c6fb90c8
L		 1455static INLINE i386_cpu_flags
1456cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1457{
c6fb90c8
L		 1458 switch (ARRAY_SIZE (x.array))
1459 {
1460 case 3:
1461 x.array [2] &= y.array [2];
1462 case 2:
1463 x.array [1] &= y.array [1];
1464 case 1:
1465 x.array [0] &= y.array [0];
1466 break;
1467 default:
1468 abort ();
1469 }
1470 return x;
1471}
40fb9820 1472
c6fb90c8
L		 1473static INLINE i386_cpu_flags
1474cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1475{
c6fb90c8 1476 switch (ARRAY_SIZE (x.array))
40fb9820 1477 {
c6fb90c8
L		 1478 case 3:
1479 x.array [2] |= y.array [2];
1480 case 2:
1481 x.array [1] |= y.array [1];
1482 case 1:
1483 x.array [0] |= y.array [0];
40fb9820
L		 1484 break;
1485 default:
1486 abort ();
1487 }
40fb9820
L		 1488 return x;
1489}
1490
309d3373
JB		 1491static INLINE i386_cpu_flags
1492cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1493{
1494 switch (ARRAY_SIZE (x.array))
1495 {
1496 case 3:
1497 x.array [2] &= ~y.array [2];
1498 case 2:
1499 x.array [1] &= ~y.array [1];
1500 case 1:
1501 x.array [0] &= ~y.array [0];
1502 break;
1503 default:
1504 abort ();
1505 }
1506 return x;
1507}
1508
81486035
L		 1509static int
1510valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1511{
1512 if (cpu_arch_isa == PROCESSOR_IAMCU)
1513 {
1514 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1515 i386_cpu_flags compat_flags;
1516 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1517 return cpu_flags_all_zero (&compat_flags);
1518 }
1519 else
1520 return 1;
1521}
1522
c0f3af97
L		 1523#define CPU_FLAGS_ARCH_MATCH 0x1
1524#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1525#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1526#define CPU_FLAGS_PCLMUL_MATCH 0x8
1527#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1528
a5ff0eb2 1529#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1530 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1531 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1532#define CPU_FLAGS_PERFECT_MATCH \
1533 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1534
1535/* Return CPU flags match bits. */
3629bb00 1536
40fb9820 1537static int
d3ce72d0 1538cpu_flags_match (const insn_template *t)
40fb9820 1539{
c0f3af97
L		 1540 i386_cpu_flags x = t->cpu_flags;
1541 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1542
1543 x.bitfield.cpu64 = 0;
1544 x.bitfield.cpuno64 = 0;
1545
0dfbf9d7 1546 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1547 {
1548 /* This instruction is available on all archs. */
1549 match |= CPU_FLAGS_32BIT_MATCH;
1550 }
3629bb00
L		 1551 else
1552 {
c0f3af97 1553 /* This instruction is available only on some archs. */
3629bb00
L		 1554 i386_cpu_flags cpu = cpu_arch_flags;
1555
3629bb00 1556 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1557 if (!cpu_flags_all_zero (&cpu))
1558 {
a5ff0eb2
L		 1559 if (x.bitfield.cpuavx)
1560 {
ce2f5b3c 1561 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1562 if (cpu.bitfield.cpuavx)
1563 {
1564 /* Check SSE2AVX. */
1565 if (!t->opcode_modifier.sse2avx|| sse2avx)
1566 {
1567 match |= (CPU_FLAGS_ARCH_MATCH
1568 | CPU_FLAGS_AVX_MATCH);
1569 /* Check AES. */
1570 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1571 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1572 /* Check PCLMUL. */
1573 if (!x.bitfield.cpupclmul
1574 || cpu.bitfield.cpupclmul)
1575 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1576 }
1577 }
1578 else
1579 match |= CPU_FLAGS_ARCH_MATCH;
1580 }
73b090a9
L		 1581 else if (x.bitfield.cpuavx512vl)
1582 {
1583 /* Match AVX512VL. */
1584 if (cpu.bitfield.cpuavx512vl)
1585 {
1586 /* Need another match. */
1587 cpu.bitfield.cpuavx512vl = 0;
1588 if (!cpu_flags_all_zero (&cpu))
1589 match |= CPU_FLAGS_32BIT_MATCH;
1590 else
1591 match |= CPU_FLAGS_ARCH_MATCH;
1592 }
1593 else
1594 match |= CPU_FLAGS_ARCH_MATCH;
1595 }
a5ff0eb2 1596 else
c0f3af97
L		 1597 match |= CPU_FLAGS_32BIT_MATCH;
1598 }
3629bb00 1599 }
c0f3af97 1600 return match;
40fb9820
L		 1601}
1602
c6fb90c8
L		 1603static INLINE i386_operand_type
1604operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1605{
c6fb90c8
L		 1606 switch (ARRAY_SIZE (x.array))
1607 {
1608 case 3:
1609 x.array [2] &= y.array [2];
1610 case 2:
1611 x.array [1] &= y.array [1];
1612 case 1:
1613 x.array [0] &= y.array [0];
1614 break;
1615 default:
1616 abort ();
1617 }
1618 return x;
40fb9820
L		 1619}
1620
c6fb90c8
L		 1621static INLINE i386_operand_type
1622operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1623{
c6fb90c8 1624 switch (ARRAY_SIZE (x.array))
40fb9820 1625 {
c6fb90c8
L		 1626 case 3:
1627 x.array [2] |= y.array [2];
1628 case 2:
1629 x.array [1] |= y.array [1];
1630 case 1:
1631 x.array [0] |= y.array [0];
40fb9820
L		 1632 break;
1633 default:
1634 abort ();
1635 }
c6fb90c8
L		 1636 return x;
1637}
40fb9820 1638
c6fb90c8
L		 1639static INLINE i386_operand_type
1640operand_type_xor (i386_operand_type x, i386_operand_type y)
1641{
1642 switch (ARRAY_SIZE (x.array))
1643 {
1644 case 3:
1645 x.array [2] ^= y.array [2];
1646 case 2:
1647 x.array [1] ^= y.array [1];
1648 case 1:
1649 x.array [0] ^= y.array [0];
1650 break;
1651 default:
1652 abort ();
1653 }
40fb9820
L		 1654 return x;
1655}
1656
1657static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1658static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1659static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1660static const i386_operand_type inoutportreg
1661 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1662static const i386_operand_type reg16_inoutportreg
1663 = OPERAND_TYPE_REG16_INOUTPORTREG;
1664static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1665static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1666static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1667static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1668static const i386_operand_type anydisp
1669 = OPERAND_TYPE_ANYDISP;
40fb9820 1670static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1671static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1672static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1673static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1674static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1675static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1676static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1677static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1678static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1679static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1680static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1681static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1682static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1683static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1684
1685enum operand_type
1686{
1687 reg,
40fb9820
L		 1688 imm,
1689 disp,
1690 anymem
1691};
1692
c6fb90c8 1693static INLINE int
40fb9820
L		 1694operand_type_check (i386_operand_type t, enum operand_type c)
1695{
1696 switch (c)
1697 {
1698 case reg:
1699 return (t.bitfield.reg8
1700 || t.bitfield.reg16
1701 || t.bitfield.reg32
1702 || t.bitfield.reg64);
1703
40fb9820
L		 1704 case imm:
1705 return (t.bitfield.imm8
1706 || t.bitfield.imm8s
1707 || t.bitfield.imm16
1708 || t.bitfield.imm32
1709 || t.bitfield.imm32s
1710 || t.bitfield.imm64);
1711
1712 case disp:
1713 return (t.bitfield.disp8
1714 || t.bitfield.disp16
1715 || t.bitfield.disp32
1716 || t.bitfield.disp32s
1717 || t.bitfield.disp64);
1718
1719 case anymem:
1720 return (t.bitfield.disp8
1721 || t.bitfield.disp16
1722 || t.bitfield.disp32
1723 || t.bitfield.disp32s
1724 || t.bitfield.disp64
1725 || t.bitfield.baseindex);
1726
1727 default:
1728 abort ();
1729 }
2cfe26b6
AM		 1730
1731 return 0;
40fb9820
L		 1732}
1733
5c07affc
L		 1734/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1735 operand J for instruction template T. */
1736
1737static INLINE int
d3ce72d0 1738match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1739{
1740 return !((i.types[j].bitfield.byte
1741 && !t->operand_types[j].bitfield.byte)
1742 || (i.types[j].bitfield.word
1743 && !t->operand_types[j].bitfield.word)
1744 || (i.types[j].bitfield.dword
1745 && !t->operand_types[j].bitfield.dword)
1746 || (i.types[j].bitfield.qword
1747 && !t->operand_types[j].bitfield.qword));
1748}
1749
1750/* Return 1 if there is no conflict in any size on operand J for
1751 instruction template T. */
1752
1753static INLINE int
d3ce72d0 1754match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1755{
1756 return (match_reg_size (t, j)
1757 && !((i.types[j].bitfield.unspecified
af508cb9 1758 && !i.broadcast
5c07affc
L		 1759 && !t->operand_types[j].bitfield.unspecified)
1760 || (i.types[j].bitfield.fword
1761 && !t->operand_types[j].bitfield.fword)
1762 || (i.types[j].bitfield.tbyte
1763 && !t->operand_types[j].bitfield.tbyte)
1764 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1765 && !t->operand_types[j].bitfield.xmmword)
1766 || (i.types[j].bitfield.ymmword
43234a1e
L		 1767 && !t->operand_types[j].bitfield.ymmword)
1768 || (i.types[j].bitfield.zmmword
1769 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1770}
1771
1772/* Return 1 if there is no size conflict on any operands for
1773 instruction template T. */
1774
1775static INLINE int
d3ce72d0 1776operand_size_match (const insn_template *t)
5c07affc
L		 1777{
1778 unsigned int j;
1779 int match = 1;
1780
1781 /* Don't check jump instructions. */
1782 if (t->opcode_modifier.jump
1783 || t->opcode_modifier.jumpbyte
1784 || t->opcode_modifier.jumpdword
1785 || t->opcode_modifier.jumpintersegment)
1786 return match;
1787
1788 /* Check memory and accumulator operand size. */
1789 for (j = 0; j < i.operands; j++)
1790 {
1791 if (t->operand_types[j].bitfield.anysize)
1792 continue;
1793
1794 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1795 {
1796 match = 0;
1797 break;
1798 }
1799
1800 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1801 {
1802 match = 0;
1803 break;
1804 }
1805 }
1806
891edac4 1807 if (match)
5c07affc 1808 return match;
891edac4
L		 1809 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1810 {
1811mismatch:
86e026a4 1812 i.error = operand_size_mismatch;
891edac4
L		 1813 return 0;
1814 }
5c07affc
L		 1815
1816 /* Check reverse. */
9c2799c2 1817 gas_assert (i.operands == 2);
5c07affc
L		 1818
1819 match = 1;
1820 for (j = 0; j < 2; j++)
1821 {
1822 if (t->operand_types[j].bitfield.acc
1823 && !match_reg_size (t, j ? 0 : 1))
891edac4 1824 goto mismatch;
5c07affc
L		 1825
1826 if (i.types[j].bitfield.mem
1827 && !match_mem_size (t, j ? 0 : 1))
891edac4 1828 goto mismatch;
5c07affc
L		 1829 }
1830
1831 return match;
1832}
1833
c6fb90c8 1834static INLINE int
40fb9820
L		 1835operand_type_match (i386_operand_type overlap,
1836 i386_operand_type given)
1837{
1838 i386_operand_type temp = overlap;
1839
1840 temp.bitfield.jumpabsolute = 0;
7d5e4556 1841 temp.bitfield.unspecified = 0;
5c07affc
L		 1842 temp.bitfield.byte = 0;
1843 temp.bitfield.word = 0;
1844 temp.bitfield.dword = 0;
1845 temp.bitfield.fword = 0;
1846 temp.bitfield.qword = 0;
1847 temp.bitfield.tbyte = 0;
1848 temp.bitfield.xmmword = 0;
c0f3af97 1849 temp.bitfield.ymmword = 0;
43234a1e 1850 temp.bitfield.zmmword = 0;
0dfbf9d7 1851 if (operand_type_all_zero (&temp))
891edac4 1852 goto mismatch;
40fb9820 1853
891edac4
L		 1854 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1855 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1856 return 1;
1857
1858mismatch:
a65babc9 1859 i.error = operand_type_mismatch;
891edac4 1860 return 0;
40fb9820
L		 1861}
1862
7d5e4556 1863/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1864 unless the expected operand type register overlap is null.
1865 Note that Acc in a template matches every size of reg. */
1866
c6fb90c8 1867static INLINE int
40fb9820
L		 1868operand_type_register_match (i386_operand_type m0,
1869 i386_operand_type g0,
1870 i386_operand_type t0,
1871 i386_operand_type m1,
1872 i386_operand_type g1,
1873 i386_operand_type t1)
1874{
1875 if (!operand_type_check (g0, reg))
1876 return 1;
1877
1878 if (!operand_type_check (g1, reg))
1879 return 1;
1880
1881 if (g0.bitfield.reg8 == g1.bitfield.reg8
1882 && g0.bitfield.reg16 == g1.bitfield.reg16
1883 && g0.bitfield.reg32 == g1.bitfield.reg32
1884 && g0.bitfield.reg64 == g1.bitfield.reg64)
1885 return 1;
1886
1887 if (m0.bitfield.acc)
1888 {
1889 t0.bitfield.reg8 = 1;
1890 t0.bitfield.reg16 = 1;
1891 t0.bitfield.reg32 = 1;
1892 t0.bitfield.reg64 = 1;
1893 }
1894
1895 if (m1.bitfield.acc)
1896 {
1897 t1.bitfield.reg8 = 1;
1898 t1.bitfield.reg16 = 1;
1899 t1.bitfield.reg32 = 1;
1900 t1.bitfield.reg64 = 1;
1901 }
1902
891edac4
L		 1903 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1904 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1905 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1906 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1907 return 1;
1908
a65babc9 1909 i.error = register_type_mismatch;
891edac4
L		 1910
1911 return 0;
40fb9820
L		 1912}
1913
4c692bc7
JB		 1914static INLINE unsigned int
1915register_number (const reg_entry *r)
1916{
1917 unsigned int nr = r->reg_num;
1918
1919 if (r->reg_flags & RegRex)
1920 nr += 8;
1921
200cbe0f
L		 1922 if (r->reg_flags & RegVRex)
1923 nr += 16;
1924
4c692bc7
JB		 1925 return nr;
1926}
1927
252b5132 1928static INLINE unsigned int
40fb9820 1929mode_from_disp_size (i386_operand_type t)
252b5132 1930{
43234a1e 1931 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1932 return 1;
1933 else if (t.bitfield.disp16
1934 || t.bitfield.disp32
1935 || t.bitfield.disp32s)
1936 return 2;
1937 else
1938 return 0;
252b5132
RH		 1939}
1940
1941static INLINE int
65879393 1942fits_in_signed_byte (addressT num)
252b5132 1943{
65879393 1944 return num + 0x80 <= 0xff;
47926f60 1945}
252b5132
RH		 1946
1947static INLINE int
65879393 1948fits_in_unsigned_byte (addressT num)
252b5132 1949{
65879393 1950 return num <= 0xff;
47926f60 1951}
252b5132
RH		 1952
1953static INLINE int
65879393 1954fits_in_unsigned_word (addressT num)
252b5132 1955{
65879393 1956 return num <= 0xffff;
47926f60 1957}
252b5132
RH		 1958
1959static INLINE int
65879393 1960fits_in_signed_word (addressT num)
252b5132 1961{
65879393 1962 return num + 0x8000 <= 0xffff;
47926f60 1963}
2a962e6d 1964
3e73aa7c 1965static INLINE int
65879393 1966fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1967{
1968#ifndef BFD64
1969 return 1;
1970#else
65879393 1971 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1972#endif
1973} /* fits_in_signed_long() */
2a962e6d 1974
3e73aa7c 1975static INLINE int
65879393 1976fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1977{
1978#ifndef BFD64
1979 return 1;
1980#else
65879393 1981 return num <= 0xffffffff;
3e73aa7c
JH		 1982#endif
1983} /* fits_in_unsigned_long() */
252b5132 1984
43234a1e
L		 1985static INLINE int
1986fits_in_vec_disp8 (offsetT num)
1987{
1988 int shift = i.memshift;
1989 unsigned int mask;
1990
1991 if (shift == -1)
1992 abort ();
1993
1994 mask = (1 << shift) - 1;
1995
1996 /* Return 0 if NUM isn't properly aligned. */
1997 if ((num & mask))
1998 return 0;
1999
2000 /* Check if NUM will fit in 8bit after shift. */
2001 return fits_in_signed_byte (num >> shift);
2002}
2003
a683cc34
SP		 2004static INLINE int
2005fits_in_imm4 (offsetT num)
2006{
2007 return (num & 0xf) == num;
2008}
2009
40fb9820 2010static i386_operand_type
e3bb37b5 2011smallest_imm_type (offsetT num)
252b5132 2012{
40fb9820 2013 i386_operand_type t;
7ab9ffdd 2014
0dfbf9d7 2015 operand_type_set (&t, 0);
40fb9820
L		 2016 t.bitfield.imm64 = 1;
2017
2018 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2019 {
2020 /* This code is disabled on the 486 because all the Imm1 forms
2021 in the opcode table are slower on the i486. They're the
2022 versions with the implicitly specified single-position
2023 displacement, which has another syntax if you really want to
2024 use that form. */
40fb9820
L		 2025 t.bitfield.imm1 = 1;
2026 t.bitfield.imm8 = 1;
2027 t.bitfield.imm8s = 1;
2028 t.bitfield.imm16 = 1;
2029 t.bitfield.imm32 = 1;
2030 t.bitfield.imm32s = 1;
2031 }
2032 else if (fits_in_signed_byte (num))
2033 {
2034 t.bitfield.imm8 = 1;
2035 t.bitfield.imm8s = 1;
2036 t.bitfield.imm16 = 1;
2037 t.bitfield.imm32 = 1;
2038 t.bitfield.imm32s = 1;
2039 }
2040 else if (fits_in_unsigned_byte (num))
2041 {
2042 t.bitfield.imm8 = 1;
2043 t.bitfield.imm16 = 1;
2044 t.bitfield.imm32 = 1;
2045 t.bitfield.imm32s = 1;
2046 }
2047 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2048 {
2049 t.bitfield.imm16 = 1;
2050 t.bitfield.imm32 = 1;
2051 t.bitfield.imm32s = 1;
2052 }
2053 else if (fits_in_signed_long (num))
2054 {
2055 t.bitfield.imm32 = 1;
2056 t.bitfield.imm32s = 1;
2057 }
2058 else if (fits_in_unsigned_long (num))
2059 t.bitfield.imm32 = 1;
2060
2061 return t;
47926f60 2062}
252b5132 2063
847f7ad4 2064static offsetT
e3bb37b5 2065offset_in_range (offsetT val, int size)
847f7ad4 2066{
508866be 2067 addressT mask;
ba2adb93 2068
847f7ad4
AM		 2069 switch (size)
2070 {
508866be
L		 2071 case 1: mask = ((addressT) 1 << 8) - 1; break;
2072 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2073 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2074#ifdef BFD64
2075 case 8: mask = ((addressT) 2 << 63) - 1; break;
2076#endif
47926f60 2077 default: abort ();
847f7ad4
AM		 2078 }
2079
9de868bf
L		 2080#ifdef BFD64
2081 /* If BFD64, sign extend val for 32bit address mode. */
2082 if (flag_code != CODE_64BIT
2083 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2084 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2085 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2086#endif
ba2adb93 2087
47926f60 2088 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2089 {
2090 char buf1[40], buf2[40];
2091
2092 sprint_value (buf1, val);
2093 sprint_value (buf2, val & mask);
2094 as_warn (_("%s shortened to %s"), buf1, buf2);
2095 }
2096 return val & mask;
2097}
2098
c32fa91d
L		 2099enum PREFIX_GROUP
2100{
2101 PREFIX_EXIST = 0,
2102 PREFIX_LOCK,
2103 PREFIX_REP,
2104 PREFIX_OTHER
2105};
2106
2107/* Returns
2108 a. PREFIX_EXIST if attempting to add a prefix where one from the
2109 same class already exists.
2110 b. PREFIX_LOCK if lock prefix is added.
2111 c. PREFIX_REP if rep/repne prefix is added.
2112 d. PREFIX_OTHER if other prefix is added.
2113 */
2114
2115static enum PREFIX_GROUP
e3bb37b5 2116add_prefix (unsigned int prefix)
252b5132 2117{
c32fa91d 2118 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2119 unsigned int q;
252b5132 2120
29b0f896
AM		 2121 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2122 && flag_code == CODE_64BIT)
b1905489 2123 {
161a04f6
L		 2124 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2125 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2126 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2127 ret = PREFIX_EXIST;
b1905489
JB		 2128 q = REX_PREFIX;
2129 }
3e73aa7c 2130 else
b1905489
JB		 2131 {
2132 switch (prefix)
2133 {
2134 default:
2135 abort ();
2136
2137 case CS_PREFIX_OPCODE:
2138 case DS_PREFIX_OPCODE:
2139 case ES_PREFIX_OPCODE:
2140 case FS_PREFIX_OPCODE:
2141 case GS_PREFIX_OPCODE:
2142 case SS_PREFIX_OPCODE:
2143 q = SEG_PREFIX;
2144 break;
2145
2146 case REPNE_PREFIX_OPCODE:
2147 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2148 q = REP_PREFIX;
2149 ret = PREFIX_REP;
2150 break;
2151
b1905489 2152 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2153 q = LOCK_PREFIX;
2154 ret = PREFIX_LOCK;
b1905489
JB		 2155 break;
2156
2157 case FWAIT_OPCODE:
2158 q = WAIT_PREFIX;
2159 break;
2160
2161 case ADDR_PREFIX_OPCODE:
2162 q = ADDR_PREFIX;
2163 break;
2164
2165 case DATA_PREFIX_OPCODE:
2166 q = DATA_PREFIX;
2167 break;
2168 }
2169 if (i.prefix[q] != 0)
c32fa91d 2170 ret = PREFIX_EXIST;
b1905489 2171 }
252b5132 2172
b1905489 2173 if (ret)
252b5132 2174 {
b1905489
JB		 2175 if (!i.prefix[q])
2176 ++i.prefixes;
2177 i.prefix[q] |= prefix;
252b5132 2178 }
b1905489
JB		 2179 else
2180 as_bad (_("same type of prefix used twice"));
252b5132 2181
252b5132
RH		 2182 return ret;
2183}
2184
2185static void
78f12dd3 2186update_code_flag (int value, int check)
eecb386c 2187{
78f12dd3
L		 2188 PRINTF_LIKE ((*as_error));
2189
1e9cc1c2 2190 flag_code = (enum flag_code) value;
40fb9820
L		 2191 if (flag_code == CODE_64BIT)
2192 {
2193 cpu_arch_flags.bitfield.cpu64 = 1;
2194 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2195 }
2196 else
2197 {
2198 cpu_arch_flags.bitfield.cpu64 = 0;
2199 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2200 }
2201 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2202 {
78f12dd3
L		 2203 if (check)
2204 as_error = as_fatal;
2205 else
2206 as_error = as_bad;
2207 (*as_error) (_("64bit mode not supported on `%s'."),
2208 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2209 }
40fb9820 2210 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2211 {
78f12dd3
L		 2212 if (check)
2213 as_error = as_fatal;
2214 else
2215 as_error = as_bad;
2216 (*as_error) (_("32bit mode not supported on `%s'."),
2217 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2218 }
eecb386c
AM		 2219 stackop_size = '\0';
2220}
2221
78f12dd3
L		 2222static void
2223set_code_flag (int value)
2224{
2225 update_code_flag (value, 0);
2226}
2227
eecb386c 2228static void
e3bb37b5 2229set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2230{
1e9cc1c2 2231 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2232 if (flag_code != CODE_16BIT)
2233 abort ();
2234 cpu_arch_flags.bitfield.cpu64 = 0;
2235 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2236 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2237}
2238
2239static void
e3bb37b5 2240set_intel_syntax (int syntax_flag)
252b5132
RH		 2241{
2242 /* Find out if register prefixing is specified. */
2243 int ask_naked_reg = 0;
2244
2245 SKIP_WHITESPACE ();
29b0f896 2246 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2247 {
d02603dc
NC		 2248 char *string;
2249 int e = get_symbol_name (&string);
252b5132 2250
47926f60 2251 if (strcmp (string, "prefix") == 0)
252b5132 2252 ask_naked_reg = 1;
47926f60 2253 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2254 ask_naked_reg = -1;
2255 else
d0b47220 2256 as_bad (_("bad argument to syntax directive."));
d02603dc 2257 (void) restore_line_pointer (e);
252b5132
RH		 2258 }
2259 demand_empty_rest_of_line ();
c3332e24 2260
252b5132
RH		 2261 intel_syntax = syntax_flag;
2262
2263 if (ask_naked_reg == 0)
f86103b7
AM		 2264 allow_naked_reg = (intel_syntax
2265 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2266 else
2267 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2268
ee86248c 2269 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2270
e4a3b5a4 2271 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2272 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2273 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2274}
2275
1efbbeb4
L		 2276static void
2277set_intel_mnemonic (int mnemonic_flag)
2278{
e1d4d893 2279 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2280}
2281
db51cc60
L		 2282static void
2283set_allow_index_reg (int flag)
2284{
2285 allow_index_reg = flag;
2286}
2287
cb19c032 2288static void
7bab8ab5 2289set_check (int what)
cb19c032 2290{
7bab8ab5
JB		 2291 enum check_kind *kind;
2292 const char *str;
2293
2294 if (what)
2295 {
2296 kind = &operand_check;
2297 str = "operand";
2298 }
2299 else
2300 {
2301 kind = &sse_check;
2302 str = "sse";
2303 }
2304
cb19c032
L		 2305 SKIP_WHITESPACE ();
2306
2307 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2308 {
d02603dc
NC		 2309 char *string;
2310 int e = get_symbol_name (&string);
cb19c032
L		 2311
2312 if (strcmp (string, "none") == 0)
7bab8ab5 2313 *kind = check_none;
cb19c032 2314 else if (strcmp (string, "warning") == 0)
7bab8ab5 2315 *kind = check_warning;
cb19c032 2316 else if (strcmp (string, "error") == 0)
7bab8ab5 2317 *kind = check_error;
cb19c032 2318 else
7bab8ab5 2319 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2320 (void) restore_line_pointer (e);
cb19c032
L		 2321 }
2322 else
7bab8ab5 2323 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2324
2325 demand_empty_rest_of_line ();
2326}
2327
8a9036a4
L		 2328static void
2329check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2330 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2331{
2332#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2333 static const char *arch;
2334
2335 /* Intel LIOM is only supported on ELF. */
2336 if (!IS_ELF)
2337 return;
2338
2339 if (!arch)
2340 {
2341 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2342 use default_arch. */
2343 arch = cpu_arch_name;
2344 if (!arch)
2345 arch = default_arch;
2346 }
2347
81486035
L		 2348 /* If we are targeting Intel MCU, we must enable it. */
2349 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2350 || new_flag.bitfield.cpuiamcu)
2351 return;
2352
3632d14b 2353 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2354 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2355 || new_flag.bitfield.cpul1om)
8a9036a4 2356 return;
76ba9986 2357
7a9068fe
L		 2358 /* If we are targeting Intel K1OM, we must enable it. */
2359 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2360 || new_flag.bitfield.cpuk1om)
2361 return;
2362
8a9036a4
L		 2363 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2364#endif
2365}
2366
e413e4e9 2367static void
e3bb37b5 2368set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2369{
47926f60 2370 SKIP_WHITESPACE ();
e413e4e9 2371
29b0f896 2372 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2373 {
d02603dc
NC		 2374 char *string;
2375 int e = get_symbol_name (&string);
91d6fa6a 2376 unsigned int j;
40fb9820 2377 i386_cpu_flags flags;
e413e4e9 2378
91d6fa6a 2379 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2380 {
91d6fa6a 2381 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2382 {
91d6fa6a 2383 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2384
5c6af06e
JB		 2385 if (*string != '.')
2386 {
91d6fa6a 2387 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2388 cpu_sub_arch_name = NULL;
91d6fa6a 2389 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2390 if (flag_code == CODE_64BIT)
2391 {
2392 cpu_arch_flags.bitfield.cpu64 = 1;
2393 cpu_arch_flags.bitfield.cpuno64 = 0;
2394 }
2395 else
2396 {
2397 cpu_arch_flags.bitfield.cpu64 = 0;
2398 cpu_arch_flags.bitfield.cpuno64 = 1;
2399 }
91d6fa6a
NC		 2400 cpu_arch_isa = cpu_arch[j].type;
2401 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2402 if (!cpu_arch_tune_set)
2403 {
2404 cpu_arch_tune = cpu_arch_isa;
2405 cpu_arch_tune_flags = cpu_arch_isa_flags;
2406 }
5c6af06e
JB		 2407 break;
2408 }
40fb9820 2409
293f5f65
L		 2410 flags = cpu_flags_or (cpu_arch_flags,
2411 cpu_arch[j].flags);
81486035
L		 2412
2413 if (!valid_iamcu_cpu_flags (&flags))
2414 as_fatal (_("`%s' isn't valid for Intel MCU"),
2415 cpu_arch[j].name);
2416 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2417 {
6305a203
L		 2418 if (cpu_sub_arch_name)
2419 {
2420 char *name = cpu_sub_arch_name;
2421 cpu_sub_arch_name = concat (name,
91d6fa6a 2422 cpu_arch[j].name,
1bf57e9f 2423 (const char *) NULL);
6305a203
L		 2424 free (name);
2425 }
2426 else
91d6fa6a 2427 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2428 cpu_arch_flags = flags;
a586129e 2429 cpu_arch_isa_flags = flags;
5c6af06e 2430 }
d02603dc 2431 (void) restore_line_pointer (e);
5c6af06e
JB		 2432 demand_empty_rest_of_line ();
2433 return;
e413e4e9
AM		 2434 }
2435 }
293f5f65
L		 2436
2437 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2438 {
2439 /* Disable an ISA entension. */
2440 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2441 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2442 {
2443 flags = cpu_flags_and_not (cpu_arch_flags,
2444 cpu_noarch[j].flags);
2445 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2446 {
2447 if (cpu_sub_arch_name)
2448 {
2449 char *name = cpu_sub_arch_name;
2450 cpu_sub_arch_name = concat (name, string,
2451 (const char *) NULL);
2452 free (name);
2453 }
2454 else
2455 cpu_sub_arch_name = xstrdup (string);
2456 cpu_arch_flags = flags;
2457 cpu_arch_isa_flags = flags;
2458 }
2459 (void) restore_line_pointer (e);
2460 demand_empty_rest_of_line ();
2461 return;
2462 }
2463
2464 j = ARRAY_SIZE (cpu_arch);
2465 }
2466
91d6fa6a 2467 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2468 as_bad (_("no such architecture: `%s'"), string);
2469
2470 *input_line_pointer = e;
2471 }
2472 else
2473 as_bad (_("missing cpu architecture"));
2474
fddf5b5b
AM		 2475 no_cond_jump_promotion = 0;
2476 if (*input_line_pointer == ','
29b0f896 2477 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2478 {
d02603dc
NC		 2479 char *string;
2480 char e;
2481
2482 ++input_line_pointer;
2483 e = get_symbol_name (&string);
fddf5b5b
AM		 2484
2485 if (strcmp (string, "nojumps") == 0)
2486 no_cond_jump_promotion = 1;
2487 else if (strcmp (string, "jumps") == 0)
2488 ;
2489 else
2490 as_bad (_("no such architecture modifier: `%s'"), string);
2491
d02603dc 2492 (void) restore_line_pointer (e);
fddf5b5b
AM		 2493 }
2494
e413e4e9
AM		 2495 demand_empty_rest_of_line ();
2496}
2497
8a9036a4
L		 2498enum bfd_architecture
2499i386_arch (void)
2500{
3632d14b 2501 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2502 {
2503 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2504 || flag_code != CODE_64BIT)
2505 as_fatal (_("Intel L1OM is 64bit ELF only"));
2506 return bfd_arch_l1om;
2507 }
7a9068fe
L		 2508 else if (cpu_arch_isa == PROCESSOR_K1OM)
2509 {
2510 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2511 || flag_code != CODE_64BIT)
2512 as_fatal (_("Intel K1OM is 64bit ELF only"));
2513 return bfd_arch_k1om;
2514 }
81486035
L		 2515 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2516 {
2517 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2518 || flag_code == CODE_64BIT)
2519 as_fatal (_("Intel MCU is 32bit ELF only"));
2520 return bfd_arch_iamcu;
2521 }
8a9036a4
L		 2522 else
2523 return bfd_arch_i386;
2524}
2525
b9d79e03 2526unsigned long
7016a5d5 2527i386_mach (void)
b9d79e03 2528{
351f65ca 2529 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2530 {
3632d14b 2531 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2532 {
351f65ca
L		 2533 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2534 || default_arch[6] != '\0')
8a9036a4
L		 2535 as_fatal (_("Intel L1OM is 64bit ELF only"));
2536 return bfd_mach_l1om;
2537 }
7a9068fe
L		 2538 else if (cpu_arch_isa == PROCESSOR_K1OM)
2539 {
2540 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2541 || default_arch[6] != '\0')
2542 as_fatal (_("Intel K1OM is 64bit ELF only"));
2543 return bfd_mach_k1om;
2544 }
351f65ca 2545 else if (default_arch[6] == '\0')
8a9036a4 2546 return bfd_mach_x86_64;
351f65ca
L		 2547 else
2548 return bfd_mach_x64_32;
8a9036a4 2549 }
5197d474
L		 2550 else if (!strcmp (default_arch, "i386")
2551 || !strcmp (default_arch, "iamcu"))
81486035
L		 2552 {
2553 if (cpu_arch_isa == PROCESSOR_IAMCU)
2554 {
2555 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2556 as_fatal (_("Intel MCU is 32bit ELF only"));
2557 return bfd_mach_i386_iamcu;
2558 }
2559 else
2560 return bfd_mach_i386_i386;
2561 }
b9d79e03 2562 else
2b5d6a91 2563 as_fatal (_("unknown architecture"));
b9d79e03 2564}
b9d79e03 2565\f
252b5132 2566void
7016a5d5 2567md_begin (void)
252b5132
RH		 2568{
2569 const char *hash_err;
2570
47926f60 2571 /* Initialize op_hash hash table. */
252b5132
RH		 2572 op_hash = hash_new ();
2573
2574 {
d3ce72d0 2575 const insn_template *optab;
29b0f896 2576 templates *core_optab;
252b5132 2577
47926f60
KH		 2578 /* Setup for loop. */
2579 optab = i386_optab;
add39d23 2580 core_optab = XNEW (templates);
252b5132
RH		 2581 core_optab->start = optab;
2582
2583 while (1)
2584 {
2585 ++optab;
2586 if (optab->name == NULL
2587 || strcmp (optab->name, (optab - 1)->name) != 0)
2588 {
2589 /* different name --> ship out current template list;
47926f60 2590 add to hash table; & begin anew. */
252b5132
RH		 2591 core_optab->end = optab;
2592 hash_err = hash_insert (op_hash,
2593 (optab - 1)->name,
5a49b8ac 2594 (void *) core_optab);
252b5132
RH		 2595 if (hash_err)
2596 {
b37df7c4 2597 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2598 (optab - 1)->name,
2599 hash_err);
2600 }
2601 if (optab->name == NULL)
2602 break;
add39d23 2603 core_optab = XNEW (templates);
252b5132
RH		 2604 core_optab->start = optab;
2605 }
2606 }
2607 }
2608
47926f60 2609 /* Initialize reg_hash hash table. */
252b5132
RH		 2610 reg_hash = hash_new ();
2611 {
29b0f896 2612 const reg_entry *regtab;
c3fe08fa 2613 unsigned int regtab_size = i386_regtab_size;
252b5132 2614
c3fe08fa 2615 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2616 {
5a49b8ac 2617 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2618 if (hash_err)
b37df7c4 2619 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2620 regtab->reg_name,
2621 hash_err);
252b5132
RH		 2622 }
2623 }
2624
47926f60 2625 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2626 {
29b0f896
AM		 2627 int c;
2628 char *p;
252b5132
RH		 2629
2630 for (c = 0; c < 256; c++)
2631 {
3882b010 2632 if (ISDIGIT (c))
252b5132
RH		 2633 {
2634 digit_chars[c] = c;
2635 mnemonic_chars[c] = c;
2636 register_chars[c] = c;
2637 operand_chars[c] = c;
2638 }
3882b010 2639 else if (ISLOWER (c))
252b5132
RH		 2640 {
2641 mnemonic_chars[c] = c;
2642 register_chars[c] = c;
2643 operand_chars[c] = c;
2644 }
3882b010 2645 else if (ISUPPER (c))
252b5132 2646 {
3882b010 2647 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2648 register_chars[c] = mnemonic_chars[c];
2649 operand_chars[c] = c;
2650 }
43234a1e
L		 2651 else if (c == '{' || c == '}')
2652 operand_chars[c] = c;
252b5132 2653
3882b010 2654 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2655 identifier_chars[c] = c;
2656 else if (c >= 128)
2657 {
2658 identifier_chars[c] = c;
2659 operand_chars[c] = c;
2660 }
2661 }
2662
2663#ifdef LEX_AT
2664 identifier_chars['@'] = '@';
32137342
NC		 2665#endif
2666#ifdef LEX_QM
2667 identifier_chars['?'] = '?';
2668 operand_chars['?'] = '?';
252b5132 2669#endif
252b5132 2670 digit_chars['-'] = '-';
c0f3af97 2671 mnemonic_chars['_'] = '_';
791fe849 2672 mnemonic_chars['-'] = '-';
0003779b 2673 mnemonic_chars['.'] = '.';
252b5132
RH		 2674 identifier_chars['_'] = '_';
2675 identifier_chars['.'] = '.';
2676
2677 for (p = operand_special_chars; *p != '\0'; p++)
2678 operand_chars[(unsigned char) *p] = *p;
2679 }
2680
a4447b93
RH		 2681 if (flag_code == CODE_64BIT)
2682 {
ca19b261
KT		 2683#if defined (OBJ_COFF) && defined (TE_PE)
2684 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2685 ? 32 : 16);
2686#else
a4447b93 2687 x86_dwarf2_return_column = 16;
ca19b261 2688#endif
61ff971f 2689 x86_cie_data_alignment = -8;
a4447b93
RH		 2690 }
2691 else
2692 {
2693 x86_dwarf2_return_column = 8;
2694 x86_cie_data_alignment = -4;
2695 }
252b5132
RH		 2696}
2697
2698void
e3bb37b5 2699i386_print_statistics (FILE *file)
252b5132
RH		 2700{
2701 hash_print_statistics (file, "i386 opcode", op_hash);
2702 hash_print_statistics (file, "i386 register", reg_hash);
2703}
2704\f
252b5132
RH		 2705#ifdef DEBUG386
2706
ce8a8b2f 2707/* Debugging routines for md_assemble. */
d3ce72d0 2708static void pte (insn_template *);
40fb9820 2709static void pt (i386_operand_type);
e3bb37b5
L		 2710static void pe (expressionS *);
2711static void ps (symbolS *);
252b5132
RH		 2712
2713static void
e3bb37b5 2714pi (char *line, i386_insn *x)
252b5132 2715{
09137c09 2716 unsigned int j;
252b5132
RH		 2717
2718 fprintf (stdout, "%s: template ", line);
2719 pte (&x->tm);
09f131f2
JH		 2720 fprintf (stdout, " address: base %s index %s scale %x\n",
2721 x->base_reg ? x->base_reg->reg_name : "none",
2722 x->index_reg ? x->index_reg->reg_name : "none",
2723 x->log2_scale_factor);
2724 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2725 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2726 fprintf (stdout, " sib: base %x index %x scale %x\n",
2727 x->sib.base, x->sib.index, x->sib.scale);
2728 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2729 (x->rex & REX_W) != 0,
2730 (x->rex & REX_R) != 0,
2731 (x->rex & REX_X) != 0,
2732 (x->rex & REX_B) != 0);
09137c09 2733 for (j = 0; j < x->operands; j++)
252b5132 2734 {
09137c09
SP		 2735 fprintf (stdout, " #%d: ", j + 1);
2736 pt (x->types[j]);
252b5132 2737 fprintf (stdout, "\n");
09137c09
SP		 2738 if (x->types[j].bitfield.reg8
2739 || x->types[j].bitfield.reg16
2740 || x->types[j].bitfield.reg32
2741 || x->types[j].bitfield.reg64
2742 || x->types[j].bitfield.regmmx
2743 || x->types[j].bitfield.regxmm
2744 || x->types[j].bitfield.regymm
43234a1e 2745 || x->types[j].bitfield.regzmm
09137c09
SP		 2746 || x->types[j].bitfield.sreg2
2747 || x->types[j].bitfield.sreg3
2748 || x->types[j].bitfield.control
2749 || x->types[j].bitfield.debug
2750 || x->types[j].bitfield.test)
2751 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2752 if (operand_type_check (x->types[j], imm))
2753 pe (x->op[j].imms);
2754 if (operand_type_check (x->types[j], disp))
2755 pe (x->op[j].disps);
252b5132
RH		 2756 }
2757}
2758
2759static void
d3ce72d0 2760pte (insn_template *t)
252b5132 2761{
09137c09 2762 unsigned int j;
252b5132 2763 fprintf (stdout, " %d operands ", t->operands);
47926f60 2764 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2765 if (t->extension_opcode != None)
2766 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2767 if (t->opcode_modifier.d)
252b5132 2768 fprintf (stdout, "D");
40fb9820 2769 if (t->opcode_modifier.w)
252b5132
RH		 2770 fprintf (stdout, "W");
2771 fprintf (stdout, "\n");
09137c09 2772 for (j = 0; j < t->operands; j++)
252b5132 2773 {
09137c09
SP		 2774 fprintf (stdout, " #%d type ", j + 1);
2775 pt (t->operand_types[j]);
252b5132
RH		 2776 fprintf (stdout, "\n");
2777 }
2778}
2779
2780static void
e3bb37b5 2781pe (expressionS *e)
252b5132 2782{
24eab124 2783 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2784 fprintf (stdout, " add_number %ld (%lx)\n",
2785 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2786 if (e->X_add_symbol)
2787 {
2788 fprintf (stdout, " add_symbol ");
2789 ps (e->X_add_symbol);
2790 fprintf (stdout, "\n");
2791 }
2792 if (e->X_op_symbol)
2793 {
2794 fprintf (stdout, " op_symbol ");
2795 ps (e->X_op_symbol);
2796 fprintf (stdout, "\n");
2797 }
2798}
2799
2800static void
e3bb37b5 2801ps (symbolS *s)
252b5132
RH		 2802{
2803 fprintf (stdout, "%s type %s%s",
2804 S_GET_NAME (s),
2805 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2806 segment_name (S_GET_SEGMENT (s)));
2807}
2808
7b81dfbb 2809static struct type_name
252b5132 2810 {
40fb9820
L		 2811 i386_operand_type mask;
2812 const char *name;
252b5132 2813 }
7b81dfbb 2814const type_names[] =
252b5132 2815{
40fb9820
L		 2816 { OPERAND_TYPE_REG8, "r8" },
2817 { OPERAND_TYPE_REG16, "r16" },
2818 { OPERAND_TYPE_REG32, "r32" },
2819 { OPERAND_TYPE_REG64, "r64" },
2820 { OPERAND_TYPE_IMM8, "i8" },
2821 { OPERAND_TYPE_IMM8, "i8s" },
2822 { OPERAND_TYPE_IMM16, "i16" },
2823 { OPERAND_TYPE_IMM32, "i32" },
2824 { OPERAND_TYPE_IMM32S, "i32s" },
2825 { OPERAND_TYPE_IMM64, "i64" },
2826 { OPERAND_TYPE_IMM1, "i1" },
2827 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2828 { OPERAND_TYPE_DISP8, "d8" },
2829 { OPERAND_TYPE_DISP16, "d16" },
2830 { OPERAND_TYPE_DISP32, "d32" },
2831 { OPERAND_TYPE_DISP32S, "d32s" },
2832 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2833 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2834 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2835 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2836 { OPERAND_TYPE_CONTROL, "control reg" },
2837 { OPERAND_TYPE_TEST, "test reg" },
2838 { OPERAND_TYPE_DEBUG, "debug reg" },
2839 { OPERAND_TYPE_FLOATREG, "FReg" },
2840 { OPERAND_TYPE_FLOATACC, "FAcc" },
2841 { OPERAND_TYPE_SREG2, "SReg2" },
2842 { OPERAND_TYPE_SREG3, "SReg3" },
2843 { OPERAND_TYPE_ACC, "Acc" },
2844 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2845 { OPERAND_TYPE_REGMMX, "rMMX" },
2846 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2847 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2848 { OPERAND_TYPE_REGZMM, "rZMM" },
2849 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2850 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2851};
2852
2853static void
40fb9820 2854pt (i386_operand_type t)
252b5132 2855{
40fb9820 2856 unsigned int j;
c6fb90c8 2857 i386_operand_type a;
252b5132 2858
40fb9820 2859 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2860 {
2861 a = operand_type_and (t, type_names[j].mask);
0349dc08 2862 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2863 fprintf (stdout, "%s, ", type_names[j].name);
2864 }
252b5132
RH		 2865 fflush (stdout);
2866}
2867
2868#endif /* DEBUG386 */
2869\f
252b5132 2870static bfd_reloc_code_real_type
3956db08 2871reloc (unsigned int size,
64e74474
AM		 2872 int pcrel,
2873 int sign,
2874 bfd_reloc_code_real_type other)
252b5132 2875{
47926f60 2876 if (other != NO_RELOC)
3956db08 2877 {
91d6fa6a 2878 reloc_howto_type *rel;
3956db08
JB		 2879
2880 if (size == 8)
2881 switch (other)
2882 {
64e74474
AM		 2883 case BFD_RELOC_X86_64_GOT32:
2884 return BFD_RELOC_X86_64_GOT64;
2885 break;
553d1284
L		 2886 case BFD_RELOC_X86_64_GOTPLT64:
2887 return BFD_RELOC_X86_64_GOTPLT64;
2888 break;
64e74474
AM		 2889 case BFD_RELOC_X86_64_PLTOFF64:
2890 return BFD_RELOC_X86_64_PLTOFF64;
2891 break;
2892 case BFD_RELOC_X86_64_GOTPC32:
2893 other = BFD_RELOC_X86_64_GOTPC64;
2894 break;
2895 case BFD_RELOC_X86_64_GOTPCREL:
2896 other = BFD_RELOC_X86_64_GOTPCREL64;
2897 break;
2898 case BFD_RELOC_X86_64_TPOFF32:
2899 other = BFD_RELOC_X86_64_TPOFF64;
2900 break;
2901 case BFD_RELOC_X86_64_DTPOFF32:
2902 other = BFD_RELOC_X86_64_DTPOFF64;
2903 break;
2904 default:
2905 break;
3956db08 2906 }
e05278af 2907
8ce3d284 2908#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2909 if (other == BFD_RELOC_SIZE32)
2910 {
2911 if (size == 8)
1ab668bf 2912 other = BFD_RELOC_SIZE64;
8fd4256d 2913 if (pcrel)
1ab668bf
AM		 2914 {
2915 as_bad (_("there are no pc-relative size relocations"));
2916 return NO_RELOC;
2917 }
8fd4256d 2918 }
8ce3d284 2919#endif
8fd4256d 2920
e05278af 2921 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2922 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2923 sign = -1;
2924
91d6fa6a
NC		 2925 rel = bfd_reloc_type_lookup (stdoutput, other);
2926 if (!rel)
3956db08 2927 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2928 else if (size != bfd_get_reloc_size (rel))
3956db08 2929 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2930 bfd_get_reloc_size (rel),
3956db08 2931 size);
91d6fa6a 2932 else if (pcrel && !rel->pc_relative)
3956db08 2933 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2934 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2935 && !sign)
91d6fa6a 2936 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2937 && sign > 0))
3956db08
JB		 2938 as_bad (_("relocated field and relocation type differ in signedness"));
2939 else
2940 return other;
2941 return NO_RELOC;
2942 }
252b5132
RH		 2943
2944 if (pcrel)
2945 {
3e73aa7c 2946 if (!sign)
3956db08 2947 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2948 switch (size)
2949 {
2950 case 1: return BFD_RELOC_8_PCREL;
2951 case 2: return BFD_RELOC_16_PCREL;
d258b828 2952 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2953 case 8: return BFD_RELOC_64_PCREL;
252b5132 2954 }
3956db08 2955 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2956 }
2957 else
2958 {
3956db08 2959 if (sign > 0)
e5cb08ac 2960 switch (size)
3e73aa7c
JH		 2961 {
2962 case 4: return BFD_RELOC_X86_64_32S;
2963 }
2964 else
2965 switch (size)
2966 {
2967 case 1: return BFD_RELOC_8;
2968 case 2: return BFD_RELOC_16;
2969 case 4: return BFD_RELOC_32;
2970 case 8: return BFD_RELOC_64;
2971 }
3956db08
JB		 2972 as_bad (_("cannot do %s %u byte relocation"),
2973 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2974 }
2975
0cc9e1d3 2976 return NO_RELOC;
252b5132
RH		 2977}
2978
47926f60
KH		 2979/* Here we decide which fixups can be adjusted to make them relative to
2980 the beginning of the section instead of the symbol. Basically we need
2981 to make sure that the dynamic relocations are done correctly, so in
2982 some cases we force the original symbol to be used. */
2983
252b5132 2984int
e3bb37b5 2985tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2986{
6d249963 2987#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2988 if (!IS_ELF)
31312f95
AM		 2989 return 1;
2990
a161fe53
AM		 2991 /* Don't adjust pc-relative references to merge sections in 64-bit
2992 mode. */
2993 if (use_rela_relocations
2994 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2995 && fixP->fx_pcrel)
252b5132 2996 return 0;
31312f95 2997
8d01d9a9
AJ		 2998 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2999 and changed later by validate_fix. */
3000 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3001 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3002 return 0;
3003
8fd4256d
L		 3004 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3005 for size relocations. */
3006 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3007 || fixP->fx_r_type == BFD_RELOC_SIZE64
3008 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3009 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3010 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3011 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3012 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3013 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3014 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3015 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3016 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3017 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3018 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3019 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3020 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3021 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3022 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3023 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3024 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3025 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3026 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3027 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3028 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3029 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3030 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3031 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3032 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3033 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3034 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3035 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3036 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3037 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3038 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3039 return 0;
31312f95 3040#endif
252b5132
RH		 3041 return 1;
3042}
252b5132 3043
b4cac588 3044static int
e3bb37b5 3045intel_float_operand (const char *mnemonic)
252b5132 3046{
9306ca4a
JB		 3047 /* Note that the value returned is meaningful only for opcodes with (memory)
3048 operands, hence the code here is free to improperly handle opcodes that
3049 have no operands (for better performance and smaller code). */
3050
3051 if (mnemonic[0] != 'f')
3052 return 0; /* non-math */
3053
3054 switch (mnemonic[1])
3055 {
3056 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3057 the fs segment override prefix not currently handled because no
3058 call path can make opcodes without operands get here */
3059 case 'i':
3060 return 2 /* integer op */;
3061 case 'l':
3062 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3063 return 3; /* fldcw/fldenv */
3064 break;
3065 case 'n':
3066 if (mnemonic[2] != 'o' /* fnop */)
3067 return 3; /* non-waiting control op */
3068 break;
3069 case 'r':
3070 if (mnemonic[2] == 's')
3071 return 3; /* frstor/frstpm */
3072 break;
3073 case 's':
3074 if (mnemonic[2] == 'a')
3075 return 3; /* fsave */
3076 if (mnemonic[2] == 't')
3077 {
3078 switch (mnemonic[3])
3079 {
3080 case 'c': /* fstcw */
3081 case 'd': /* fstdw */
3082 case 'e': /* fstenv */
3083 case 's': /* fsts[gw] */
3084 return 3;
3085 }
3086 }
3087 break;
3088 case 'x':
3089 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3090 return 0; /* fxsave/fxrstor are not really math ops */
3091 break;
3092 }
252b5132 3093
9306ca4a 3094 return 1;
252b5132
RH		 3095}
3096
c0f3af97
L		 3097/* Build the VEX prefix. */
3098
3099static void
d3ce72d0 3100build_vex_prefix (const insn_template *t)
c0f3af97
L		 3101{
3102 unsigned int register_specifier;
3103 unsigned int implied_prefix;
3104 unsigned int vector_length;
3105
3106 /* Check register specifier. */
3107 if (i.vex.register_specifier)
43234a1e
L		 3108 {
3109 register_specifier =
3110 ~register_number (i.vex.register_specifier) & 0xf;
3111 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3112 }
c0f3af97
L		 3113 else
3114 register_specifier = 0xf;
3115
fa99fab2
L		 3116 /* Use 2-byte VEX prefix by swappping destination and source
3117 operand. */
3118 if (!i.swap_operand
3119 && i.operands == i.reg_operands
7f399153 3120 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3121 && i.tm.opcode_modifier.s
3122 && i.rex == REX_B)
3123 {
3124 unsigned int xchg = i.operands - 1;
3125 union i386_op temp_op;
3126 i386_operand_type temp_type;
3127
3128 temp_type = i.types[xchg];
3129 i.types[xchg] = i.types[0];
3130 i.types[0] = temp_type;
3131 temp_op = i.op[xchg];
3132 i.op[xchg] = i.op[0];
3133 i.op[0] = temp_op;
3134
9c2799c2 3135 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3136
3137 i.rex = REX_R;
3138 xchg = i.rm.regmem;
3139 i.rm.regmem = i.rm.reg;
3140 i.rm.reg = xchg;
3141
3142 /* Use the next insn. */
3143 i.tm = t[1];
3144 }
3145
539f890d
L		 3146 if (i.tm.opcode_modifier.vex == VEXScalar)
3147 vector_length = avxscalar;
3148 else
3149 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3150
3151 switch ((i.tm.base_opcode >> 8) & 0xff)
3152 {
3153 case 0:
3154 implied_prefix = 0;
3155 break;
3156 case DATA_PREFIX_OPCODE:
3157 implied_prefix = 1;
3158 break;
3159 case REPE_PREFIX_OPCODE:
3160 implied_prefix = 2;
3161 break;
3162 case REPNE_PREFIX_OPCODE:
3163 implied_prefix = 3;
3164 break;
3165 default:
3166 abort ();
3167 }
3168
3169 /* Use 2-byte VEX prefix if possible. */
7f399153 3170 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3171 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3172 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3173 {
3174 /* 2-byte VEX prefix. */
3175 unsigned int r;
3176
3177 i.vex.length = 2;
3178 i.vex.bytes[0] = 0xc5;
3179
3180 /* Check the REX.R bit. */
3181 r = (i.rex & REX_R) ? 0 : 1;
3182 i.vex.bytes[1] = (r << 7
3183 | register_specifier << 3
3184 | vector_length << 2
3185 | implied_prefix);
3186 }
3187 else
3188 {
3189 /* 3-byte VEX prefix. */
3190 unsigned int m, w;
3191
f88c9eb0 3192 i.vex.length = 3;
f88c9eb0 3193
7f399153 3194 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3195 {
7f399153
L		 3196 case VEX0F:
3197 m = 0x1;
80de6e00 3198 i.vex.bytes[0] = 0xc4;
7f399153
L		 3199 break;
3200 case VEX0F38:
3201 m = 0x2;
80de6e00 3202 i.vex.bytes[0] = 0xc4;
7f399153
L		 3203 break;
3204 case VEX0F3A:
3205 m = 0x3;
80de6e00 3206 i.vex.bytes[0] = 0xc4;
7f399153
L		 3207 break;
3208 case XOP08:
5dd85c99
SP		 3209 m = 0x8;
3210 i.vex.bytes[0] = 0x8f;
7f399153
L		 3211 break;
3212 case XOP09:
f88c9eb0
SP		 3213 m = 0x9;
3214 i.vex.bytes[0] = 0x8f;
7f399153
L		 3215 break;
3216 case XOP0A:
f88c9eb0
SP		 3217 m = 0xa;
3218 i.vex.bytes[0] = 0x8f;
7f399153
L		 3219 break;
3220 default:
3221 abort ();
f88c9eb0 3222 }
c0f3af97 3223
c0f3af97
L		 3224 /* The high 3 bits of the second VEX byte are 1's compliment
3225 of RXB bits from REX. */
3226 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3227
3228 /* Check the REX.W bit. */
3229 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3230 if (i.tm.opcode_modifier.vexw == VEXW1)
3231 w = 1;
c0f3af97
L		 3232
3233 i.vex.bytes[2] = (w << 7
3234 | register_specifier << 3
3235 | vector_length << 2
3236 | implied_prefix);
3237 }
3238}
3239
43234a1e
L		 3240/* Build the EVEX prefix. */
3241
3242static void
3243build_evex_prefix (void)
3244{
3245 unsigned int register_specifier;
3246 unsigned int implied_prefix;
3247 unsigned int m, w;
3248 rex_byte vrex_used = 0;
3249
3250 /* Check register specifier. */
3251 if (i.vex.register_specifier)
3252 {
3253 gas_assert ((i.vrex & REX_X) == 0);
3254
3255 register_specifier = i.vex.register_specifier->reg_num;
3256 if ((i.vex.register_specifier->reg_flags & RegRex))
3257 register_specifier += 8;
3258 /* The upper 16 registers are encoded in the fourth byte of the
3259 EVEX prefix. */
3260 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3261 i.vex.bytes[3] = 0x8;
3262 register_specifier = ~register_specifier & 0xf;
3263 }
3264 else
3265 {
3266 register_specifier = 0xf;
3267
3268 /* Encode upper 16 vector index register in the fourth byte of
3269 the EVEX prefix. */
3270 if (!(i.vrex & REX_X))
3271 i.vex.bytes[3] = 0x8;
3272 else
3273 vrex_used |= REX_X;
3274 }
3275
3276 switch ((i.tm.base_opcode >> 8) & 0xff)
3277 {
3278 case 0:
3279 implied_prefix = 0;
3280 break;
3281 case DATA_PREFIX_OPCODE:
3282 implied_prefix = 1;
3283 break;
3284 case REPE_PREFIX_OPCODE:
3285 implied_prefix = 2;
3286 break;
3287 case REPNE_PREFIX_OPCODE:
3288 implied_prefix = 3;
3289 break;
3290 default:
3291 abort ();
3292 }
3293
3294 /* 4 byte EVEX prefix. */
3295 i.vex.length = 4;
3296 i.vex.bytes[0] = 0x62;
3297
3298 /* mmmm bits. */
3299 switch (i.tm.opcode_modifier.vexopcode)
3300 {
3301 case VEX0F:
3302 m = 1;
3303 break;
3304 case VEX0F38:
3305 m = 2;
3306 break;
3307 case VEX0F3A:
3308 m = 3;
3309 break;
3310 default:
3311 abort ();
3312 break;
3313 }
3314
3315 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3316 bits from REX. */
3317 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3318
3319 /* The fifth bit of the second EVEX byte is 1's compliment of the
3320 REX_R bit in VREX. */
3321 if (!(i.vrex & REX_R))
3322 i.vex.bytes[1] |= 0x10;
3323 else
3324 vrex_used |= REX_R;
3325
3326 if ((i.reg_operands + i.imm_operands) == i.operands)
3327 {
3328 /* When all operands are registers, the REX_X bit in REX is not
3329 used. We reuse it to encode the upper 16 registers, which is
3330 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3331 as 1's compliment. */
3332 if ((i.vrex & REX_B))
3333 {
3334 vrex_used |= REX_B;
3335 i.vex.bytes[1] &= ~0x40;
3336 }
3337 }
3338
3339 /* EVEX instructions shouldn't need the REX prefix. */
3340 i.vrex &= ~vrex_used;
3341 gas_assert (i.vrex == 0);
3342
3343 /* Check the REX.W bit. */
3344 w = (i.rex & REX_W) ? 1 : 0;
3345 if (i.tm.opcode_modifier.vexw)
3346 {
3347 if (i.tm.opcode_modifier.vexw == VEXW1)
3348 w = 1;
3349 }
3350 /* If w is not set it means we are dealing with WIG instruction. */
3351 else if (!w)
3352 {
3353 if (evexwig == evexw1)
3354 w = 1;
3355 }
3356
3357 /* Encode the U bit. */
3358 implied_prefix |= 0x4;
3359
3360 /* The third byte of the EVEX prefix. */
3361 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3362
3363 /* The fourth byte of the EVEX prefix. */
3364 /* The zeroing-masking bit. */
3365 if (i.mask && i.mask->zeroing)
3366 i.vex.bytes[3] |= 0x80;
3367
3368 /* Don't always set the broadcast bit if there is no RC. */
3369 if (!i.rounding)
3370 {
3371 /* Encode the vector length. */
3372 unsigned int vec_length;
3373
3374 switch (i.tm.opcode_modifier.evex)
3375 {
3376 case EVEXLIG: /* LL' is ignored */
3377 vec_length = evexlig << 5;
3378 break;
3379 case EVEX128:
3380 vec_length = 0 << 5;
3381 break;
3382 case EVEX256:
3383 vec_length = 1 << 5;
3384 break;
3385 case EVEX512:
3386 vec_length = 2 << 5;
3387 break;
3388 default:
3389 abort ();
3390 break;
3391 }
3392 i.vex.bytes[3] |= vec_length;
3393 /* Encode the broadcast bit. */
3394 if (i.broadcast)
3395 i.vex.bytes[3] |= 0x10;
3396 }
3397 else
3398 {
3399 if (i.rounding->type != saeonly)
3400 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3401 else
d3d3c6db 3402 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3403 }
3404
3405 if (i.mask && i.mask->mask)
3406 i.vex.bytes[3] |= i.mask->mask->reg_num;
3407}
3408
65da13b5
L		 3409static void
3410process_immext (void)
3411{
3412 expressionS *exp;
3413
4c692bc7
JB		 3414 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3415 && i.operands > 0)
65da13b5 3416 {
4c692bc7
JB		 3417 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3418 with an opcode suffix which is coded in the same place as an
3419 8-bit immediate field would be.
3420 Here we check those operands and remove them afterwards. */
65da13b5
L		 3421 unsigned int x;
3422
3423 for (x = 0; x < i.operands; x++)
4c692bc7 3424 if (register_number (i.op[x].regs) != x)
65da13b5 3425 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3426 register_prefix, i.op[x].regs->reg_name, x + 1,
3427 i.tm.name);
3428
3429 i.operands = 0;
65da13b5
L		 3430 }
3431
9916071f
AP		 3432 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3433 {
3434 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3435 suffix which is coded in the same place as an 8-bit immediate
3436 field would be.
3437 Here we check those operands and remove them afterwards. */
3438 unsigned int x;
3439
3440 if (i.operands != 3)
3441 abort();
3442
3443 for (x = 0; x < 2; x++)
3444 if (register_number (i.op[x].regs) != x)
3445 goto bad_register_operand;
3446
3447 /* Check for third operand for mwaitx/monitorx insn. */
3448 if (register_number (i.op[x].regs)
3449 != (x + (i.tm.extension_opcode == 0xfb)))
3450 {
3451bad_register_operand:
3452 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3453 register_prefix, i.op[x].regs->reg_name, x+1,
3454 i.tm.name);
3455 }
3456
3457 i.operands = 0;
3458 }
3459
c0f3af97 3460 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3461 which is coded in the same place as an 8-bit immediate field
3462 would be. Here we fake an 8-bit immediate operand from the
3463 opcode suffix stored in tm.extension_opcode.
3464
c1e679ec 3465 AVX instructions also use this encoding, for some of
c0f3af97 3466 3 argument instructions. */
65da13b5 3467
43234a1e 3468 gas_assert (i.imm_operands <= 1
7ab9ffdd 3469 && (i.operands <= 2
43234a1e
L		 3470 || ((i.tm.opcode_modifier.vex
3471 || i.tm.opcode_modifier.evex)
7ab9ffdd 3472 && i.operands <= 4)));
65da13b5
L		 3473
3474 exp = &im_expressions[i.imm_operands++];
3475 i.op[i.operands].imms = exp;
3476 i.types[i.operands] = imm8;
3477 i.operands++;
3478 exp->X_op = O_constant;
3479 exp->X_add_number = i.tm.extension_opcode;
3480 i.tm.extension_opcode = None;
3481}
3482
42164a71
L		 3483
3484static int
3485check_hle (void)
3486{
3487 switch (i.tm.opcode_modifier.hleprefixok)
3488 {
3489 default:
3490 abort ();
82c2def5 3491 case HLEPrefixNone:
165de32a
L		 3492 as_bad (_("invalid instruction `%s' after `%s'"),
3493 i.tm.name, i.hle_prefix);
42164a71 3494 return 0;
82c2def5 3495 case HLEPrefixLock:
42164a71
L		 3496 if (i.prefix[LOCK_PREFIX])
3497 return 1;
165de32a 3498 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3499 return 0;
82c2def5 3500 case HLEPrefixAny:
42164a71 3501 return 1;
82c2def5 3502 case HLEPrefixRelease:
42164a71
L		 3503 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3504 {
3505 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3506 i.tm.name);
3507 return 0;
3508 }
3509 if (i.mem_operands == 0
3510 || !operand_type_check (i.types[i.operands - 1], anymem))
3511 {
3512 as_bad (_("memory destination needed for instruction `%s'"
3513 " after `xrelease'"), i.tm.name);
3514 return 0;
3515 }
3516 return 1;
3517 }
3518}
3519
252b5132
RH		 3520/* This is the guts of the machine-dependent assembler. LINE points to a
3521 machine dependent instruction. This function is supposed to emit
3522 the frags/bytes it assembles to. */
3523
3524void
65da13b5 3525md_assemble (char *line)
252b5132 3526{
40fb9820 3527 unsigned int j;
252b5132 3528 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3529 const insn_template *t;
252b5132 3530
47926f60 3531 /* Initialize globals. */
252b5132
RH		 3532 memset (&i, '\0', sizeof (i));
3533 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3534 i.reloc[j] = NO_RELOC;
252b5132
RH		 3535 memset (disp_expressions, '\0', sizeof (disp_expressions));
3536 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3537 save_stack_p = save_stack;
252b5132
RH		 3538
3539 /* First parse an instruction mnemonic & call i386_operand for the operands.
3540 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3541 start of a (possibly prefixed) mnemonic. */
252b5132 3542
29b0f896
AM		 3543 line = parse_insn (line, mnemonic);
3544 if (line == NULL)
3545 return;
252b5132 3546
29b0f896 3547 line = parse_operands (line, mnemonic);
ee86248c 3548 this_operand = -1;
29b0f896
AM		 3549 if (line == NULL)
3550 return;
252b5132 3551
29b0f896
AM		 3552 /* Now we've parsed the mnemonic into a set of templates, and have the
3553 operands at hand. */
3554
3555 /* All intel opcodes have reversed operands except for "bound" and
3556 "enter". We also don't reverse intersegment "jmp" and "call"
3557 instructions with 2 immediate operands so that the immediate segment
050dfa73 3558 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3559 if (intel_syntax
3560 && i.operands > 1
29b0f896 3561 && (strcmp (mnemonic, "bound") != 0)
30123838 3562 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3563 && !(operand_type_check (i.types[0], imm)
3564 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3565 swap_operands ();
3566
ec56d5c0
JB		 3567 /* The order of the immediates should be reversed
3568 for 2 immediates extrq and insertq instructions */
3569 if (i.imm_operands == 2
3570 && (strcmp (mnemonic, "extrq") == 0
3571 || strcmp (mnemonic, "insertq") == 0))
3572 swap_2_operands (0, 1);
3573
29b0f896
AM		 3574 if (i.imm_operands)
3575 optimize_imm ();
3576
b300c311
L		 3577 /* Don't optimize displacement for movabs since it only takes 64bit
3578 displacement. */
3579 if (i.disp_operands
a501d77e 3580 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3581 && (flag_code != CODE_64BIT
3582 || strcmp (mnemonic, "movabs") != 0))
3583 optimize_disp ();
29b0f896
AM		 3584
3585 /* Next, we find a template that matches the given insn,
3586 making sure the overlap of the given operands types is consistent
3587 with the template operand types. */
252b5132 3588
fa99fab2 3589 if (!(t = match_template ()))
29b0f896 3590 return;
252b5132 3591
7bab8ab5 3592 if (sse_check != check_none
81f8a913 3593 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3594 && (i.tm.cpu_flags.bitfield.cpusse
3595 || i.tm.cpu_flags.bitfield.cpusse2
3596 || i.tm.cpu_flags.bitfield.cpusse3
3597 || i.tm.cpu_flags.bitfield.cpussse3
3598 || i.tm.cpu_flags.bitfield.cpusse4_1
3599 || i.tm.cpu_flags.bitfield.cpusse4_2))
3600 {
7bab8ab5 3601 (sse_check == check_warning
daf50ae7
L		 3602 ? as_warn
3603 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3604 }
3605
321fd21e
L		 3606 /* Zap movzx and movsx suffix. The suffix has been set from
3607 "word ptr" or "byte ptr" on the source operand in Intel syntax
3608 or extracted from mnemonic in AT&T syntax. But we'll use
3609 the destination register to choose the suffix for encoding. */
3610 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3611 {
321fd21e
L		 3612 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3613 there is no suffix, the default will be byte extension. */
3614 if (i.reg_operands != 2
3615 && !i.suffix
7ab9ffdd 3616 && intel_syntax)
321fd21e
L		 3617 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3618
3619 i.suffix = 0;
cd61ebfe 3620 }
24eab124 3621
40fb9820 3622 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3623 if (!add_prefix (FWAIT_OPCODE))
3624 return;
252b5132 3625
d5de92cf
L		 3626 /* Check if REP prefix is OK. */
3627 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3628 {
3629 as_bad (_("invalid instruction `%s' after `%s'"),
3630 i.tm.name, i.rep_prefix);
3631 return;
3632 }
3633
c1ba0266
L		 3634 /* Check for lock without a lockable instruction. Destination operand
3635 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3636 if (i.prefix[LOCK_PREFIX]
3637 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3638 || i.mem_operands == 0
3639 || (i.tm.base_opcode != 0x86
3640 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3641 {
3642 as_bad (_("expecting lockable instruction after `lock'"));
3643 return;
3644 }
3645
42164a71 3646 /* Check if HLE prefix is OK. */
165de32a 3647 if (i.hle_prefix && !check_hle ())
42164a71
L		 3648 return;
3649
7e8b059b
L		 3650 /* Check BND prefix. */
3651 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3652 as_bad (_("expecting valid branch instruction after `bnd'"));
3653
3654 if (i.tm.cpu_flags.bitfield.cpumpx
3655 && flag_code == CODE_64BIT
3656 && i.prefix[ADDR_PREFIX])
3657 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3658
3659 /* Insert BND prefix. */
3660 if (add_bnd_prefix
3661 && i.tm.opcode_modifier.bndprefixok
3662 && !i.prefix[BND_PREFIX])
3663 add_prefix (BND_PREFIX_OPCODE);
3664
29b0f896 3665 /* Check string instruction segment overrides. */
40fb9820 3666 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3667 {
3668 if (!check_string ())
5dd0794d 3669 return;
fc0763e6 3670 i.disp_operands = 0;
29b0f896 3671 }
5dd0794d 3672
29b0f896
AM		 3673 if (!process_suffix ())
3674 return;
e413e4e9 3675
bc0844ae
L		 3676 /* Update operand types. */
3677 for (j = 0; j < i.operands; j++)
3678 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3679
29b0f896
AM		 3680 /* Make still unresolved immediate matches conform to size of immediate
3681 given in i.suffix. */
3682 if (!finalize_imm ())
3683 return;
252b5132 3684
40fb9820 3685 if (i.types[0].bitfield.imm1)
29b0f896 3686 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3687
9afe6eb8
L		 3688 /* We only need to check those implicit registers for instructions
3689 with 3 operands or less. */
3690 if (i.operands <= 3)
3691 for (j = 0; j < i.operands; j++)
3692 if (i.types[j].bitfield.inoutportreg
3693 || i.types[j].bitfield.shiftcount
3694 || i.types[j].bitfield.acc
3695 || i.types[j].bitfield.floatacc)
3696 i.reg_operands--;
40fb9820 3697
c0f3af97
L		 3698 /* ImmExt should be processed after SSE2AVX. */
3699 if (!i.tm.opcode_modifier.sse2avx
3700 && i.tm.opcode_modifier.immext)
65da13b5 3701 process_immext ();
252b5132 3702
29b0f896
AM		 3703 /* For insns with operands there are more diddles to do to the opcode. */
3704 if (i.operands)
3705 {
3706 if (!process_operands ())
3707 return;
3708 }
40fb9820 3709 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3710 {
3711 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3712 as_warn (_("translating to `%sp'"), i.tm.name);
3713 }
252b5132 3714
9e5e5283
L		 3715 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3716 {
3717 if (flag_code == CODE_16BIT)
3718 {
3719 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3720 i.tm.name);
3721 return;
3722 }
c0f3af97 3723
9e5e5283
L		 3724 if (i.tm.opcode_modifier.vex)
3725 build_vex_prefix (t);
3726 else
3727 build_evex_prefix ();
3728 }
43234a1e 3729
5dd85c99
SP		 3730 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3731 instructions may define INT_OPCODE as well, so avoid this corner
3732 case for those instructions that use MODRM. */
3733 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3734 && !i.tm.opcode_modifier.modrm
3735 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3736 {
3737 i.tm.base_opcode = INT3_OPCODE;
3738 i.imm_operands = 0;
3739 }
252b5132 3740
40fb9820
L		 3741 if ((i.tm.opcode_modifier.jump
3742 || i.tm.opcode_modifier.jumpbyte
3743 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3744 && i.op[0].disps->X_op == O_constant)
3745 {
3746 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3747 the absolute address given by the constant. Since ix86 jumps and
3748 calls are pc relative, we need to generate a reloc. */
3749 i.op[0].disps->X_add_symbol = &abs_symbol;
3750 i.op[0].disps->X_op = O_symbol;
3751 }
252b5132 3752
40fb9820 3753 if (i.tm.opcode_modifier.rex64)
161a04f6 3754 i.rex |= REX_W;
252b5132 3755
29b0f896
AM		 3756 /* For 8 bit registers we need an empty rex prefix. Also if the
3757 instruction already has a prefix, we need to convert old
3758 registers to new ones. */
773f551c 3759
40fb9820 3760 if ((i.types[0].bitfield.reg8
29b0f896 3761 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3762 || (i.types[1].bitfield.reg8
29b0f896 3763 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3764 || ((i.types[0].bitfield.reg8
3765 || i.types[1].bitfield.reg8)
29b0f896
AM		 3766 && i.rex != 0))
3767 {
3768 int x;
726c5dcd 3769
29b0f896
AM		 3770 i.rex |= REX_OPCODE;
3771 for (x = 0; x < 2; x++)
3772 {
3773 /* Look for 8 bit operand that uses old registers. */
40fb9820 3774 if (i.types[x].bitfield.reg8
29b0f896 3775 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3776 {
29b0f896
AM		 3777 /* In case it is "hi" register, give up. */
3778 if (i.op[x].regs->reg_num > 3)
a540244d 3779 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3780 "instruction requiring REX prefix."),
a540244d 3781 register_prefix, i.op[x].regs->reg_name);
773f551c 3782
29b0f896
AM		 3783 /* Otherwise it is equivalent to the extended register.
3784 Since the encoding doesn't change this is merely
3785 cosmetic cleanup for debug output. */
3786
3787 i.op[x].regs = i.op[x].regs + 8;
773f551c 3788 }
29b0f896
AM		 3789 }
3790 }
773f551c 3791
7ab9ffdd 3792 if (i.rex != 0)
29b0f896
AM		 3793 add_prefix (REX_OPCODE | i.rex);
3794
3795 /* We are ready to output the insn. */
3796 output_insn ();
3797}
3798
3799static char *
e3bb37b5 3800parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3801{
3802 char *l = line;
3803 char *token_start = l;
3804 char *mnem_p;
5c6af06e 3805 int supported;
d3ce72d0 3806 const insn_template *t;
b6169b20 3807 char *dot_p = NULL;
29b0f896 3808
29b0f896
AM		 3809 while (1)
3810 {
3811 mnem_p = mnemonic;
3812 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3813 {
b6169b20
L		 3814 if (*mnem_p == '.')
3815 dot_p = mnem_p;
29b0f896
AM		 3816 mnem_p++;
3817 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3818 {
29b0f896
AM		 3819 as_bad (_("no such instruction: `%s'"), token_start);
3820 return NULL;
3821 }
3822 l++;
3823 }
3824 if (!is_space_char (*l)
3825 && *l != END_OF_INSN
e44823cf
JB		 3826 && (intel_syntax
3827 || (*l != PREFIX_SEPARATOR
3828 && *l != ',')))
29b0f896
AM		 3829 {
3830 as_bad (_("invalid character %s in mnemonic"),
3831 output_invalid (*l));
3832 return NULL;
3833 }
3834 if (token_start == l)
3835 {
e44823cf 3836 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3837 as_bad (_("expecting prefix; got nothing"));
3838 else
3839 as_bad (_("expecting mnemonic; got nothing"));
3840 return NULL;
3841 }
45288df1 3842
29b0f896 3843 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3844 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3845
29b0f896
AM		 3846 if (*l != END_OF_INSN
3847 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3848 && current_templates
40fb9820 3849 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3850 {
c6fb90c8 3851 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3852 {
3853 as_bad ((flag_code != CODE_64BIT
3854 ? _("`%s' is only supported in 64-bit mode")
3855 : _("`%s' is not supported in 64-bit mode")),
3856 current_templates->start->name);
3857 return NULL;
3858 }
29b0f896
AM		 3859 /* If we are in 16-bit mode, do not allow addr16 or data16.
3860 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3861 if ((current_templates->start->opcode_modifier.size16
3862 || current_templates->start->opcode_modifier.size32)
29b0f896 3863 && flag_code != CODE_64BIT
40fb9820 3864 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3865 ^ (flag_code == CODE_16BIT)))
3866 {
3867 as_bad (_("redundant %s prefix"),
3868 current_templates->start->name);
3869 return NULL;
45288df1 3870 }
29b0f896
AM		 3871 /* Add prefix, checking for repeated prefixes. */
3872 switch (add_prefix (current_templates->start->base_opcode))
3873 {
c32fa91d 3874 case PREFIX_EXIST:
29b0f896 3875 return NULL;
c32fa91d 3876 case PREFIX_REP:
42164a71 3877 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3878 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3879 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3880 i.bnd_prefix = current_templates->start->name;
42164a71 3881 else
d5de92cf 3882 i.rep_prefix = current_templates->start->name;
29b0f896 3883 break;
c32fa91d
L		 3884 default:
3885 break;
29b0f896
AM		 3886 }
3887 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3888 token_start = ++l;
3889 }
3890 else
3891 break;
3892 }
45288df1 3893
30a55f88 3894 if (!current_templates)
b6169b20 3895 {
f8a5c266
L		 3896 /* Check if we should swap operand or force 32bit displacement in
3897 encoding. */
30a55f88
L		 3898 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3899 i.swap_operand = 1;
8d63c93e 3900 else if (mnem_p - 3 == dot_p
a501d77e
L		 3901 && dot_p[1] == 'd'
3902 && dot_p[2] == '8')
3903 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3904 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3905 && dot_p[1] == 'd'
3906 && dot_p[2] == '3'
3907 && dot_p[3] == '2')
a501d77e 3908 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3909 else
3910 goto check_suffix;
3911 mnem_p = dot_p;
3912 *dot_p = '\0';
d3ce72d0 3913 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3914 }
3915
29b0f896
AM		 3916 if (!current_templates)
3917 {
b6169b20 3918check_suffix:
29b0f896
AM		 3919 /* See if we can get a match by trimming off a suffix. */
3920 switch (mnem_p[-1])
3921 {
3922 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3923 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3924 i.suffix = SHORT_MNEM_SUFFIX;
3925 else
29b0f896
AM		 3926 case BYTE_MNEM_SUFFIX:
3927 case QWORD_MNEM_SUFFIX:
3928 i.suffix = mnem_p[-1];
3929 mnem_p[-1] = '\0';
d3ce72d0
NC		 3930 current_templates = (const templates *) hash_find (op_hash,
3931 mnemonic);
29b0f896
AM		 3932 break;
3933 case SHORT_MNEM_SUFFIX:
3934 case LONG_MNEM_SUFFIX:
3935 if (!intel_syntax)
3936 {
3937 i.suffix = mnem_p[-1];
3938 mnem_p[-1] = '\0';
d3ce72d0
NC		 3939 current_templates = (const templates *) hash_find (op_hash,
3940 mnemonic);
29b0f896
AM		 3941 }
3942 break;
252b5132 3943
29b0f896
AM		 3944 /* Intel Syntax. */
3945 case 'd':
3946 if (intel_syntax)
3947 {
9306ca4a 3948 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3949 i.suffix = SHORT_MNEM_SUFFIX;
3950 else
3951 i.suffix = LONG_MNEM_SUFFIX;
3952 mnem_p[-1] = '\0';
d3ce72d0
NC		 3953 current_templates = (const templates *) hash_find (op_hash,
3954 mnemonic);
29b0f896
AM		 3955 }
3956 break;
3957 }
3958 if (!current_templates)
3959 {
3960 as_bad (_("no such instruction: `%s'"), token_start);
3961 return NULL;
3962 }
3963 }
252b5132 3964
40fb9820
L		 3965 if (current_templates->start->opcode_modifier.jump
3966 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3967 {
3968 /* Check for a branch hint. We allow ",pt" and ",pn" for
3969 predict taken and predict not taken respectively.
3970 I'm not sure that branch hints actually do anything on loop
3971 and jcxz insns (JumpByte) for current Pentium4 chips. They
3972 may work in the future and it doesn't hurt to accept them
3973 now. */
3974 if (l[0] == ',' && l[1] == 'p')
3975 {
3976 if (l[2] == 't')
3977 {
3978 if (!add_prefix (DS_PREFIX_OPCODE))
3979 return NULL;
3980 l += 3;
3981 }
3982 else if (l[2] == 'n')
3983 {
3984 if (!add_prefix (CS_PREFIX_OPCODE))
3985 return NULL;
3986 l += 3;
3987 }
3988 }
3989 }
3990 /* Any other comma loses. */
3991 if (*l == ',')
3992 {
3993 as_bad (_("invalid character %s in mnemonic"),
3994 output_invalid (*l));
3995 return NULL;
3996 }
252b5132 3997
29b0f896 3998 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3999 supported = 0;
4000 for (t = current_templates->start; t < current_templates->end; ++t)
4001 {
c0f3af97
L		 4002 supported |= cpu_flags_match (t);
4003 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4004 goto skip;
5c6af06e 4005 }
3629bb00 4006
c0f3af97 4007 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4008 {
4009 as_bad (flag_code == CODE_64BIT
4010 ? _("`%s' is not supported in 64-bit mode")
4011 : _("`%s' is only supported in 64-bit mode"),
4012 current_templates->start->name);
4013 return NULL;
4014 }
c0f3af97 4015 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4016 {
3629bb00 4017 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4018 current_templates->start->name,
41aacd83 4019 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4020 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4021 return NULL;
29b0f896 4022 }
3629bb00
L		 4023
4024skip:
4025 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4026 && (flag_code != CODE_16BIT))
29b0f896
AM		 4027 {
4028 as_warn (_("use .code16 to ensure correct addressing mode"));
4029 }
252b5132 4030
29b0f896
AM		 4031 return l;
4032}
252b5132 4033
29b0f896 4034static char *
e3bb37b5 4035parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4036{
4037 char *token_start;
3138f287 4038
29b0f896
AM		 4039 /* 1 if operand is pending after ','. */
4040 unsigned int expecting_operand = 0;
252b5132 4041
29b0f896
AM		 4042 /* Non-zero if operand parens not balanced. */
4043 unsigned int paren_not_balanced;
4044
4045 while (*l != END_OF_INSN)
4046 {
4047 /* Skip optional white space before operand. */
4048 if (is_space_char (*l))
4049 ++l;
d02603dc 4050 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4051 {
4052 as_bad (_("invalid character %s before operand %d"),
4053 output_invalid (*l),
4054 i.operands + 1);
4055 return NULL;
4056 }
d02603dc 4057 token_start = l; /* After white space. */
29b0f896
AM		 4058 paren_not_balanced = 0;
4059 while (paren_not_balanced || *l != ',')
4060 {
4061 if (*l == END_OF_INSN)
4062 {
4063 if (paren_not_balanced)
4064 {
4065 if (!intel_syntax)
4066 as_bad (_("unbalanced parenthesis in operand %d."),
4067 i.operands + 1);
4068 else
4069 as_bad (_("unbalanced brackets in operand %d."),
4070 i.operands + 1);
4071 return NULL;
4072 }
4073 else
4074 break; /* we are done */
4075 }
d02603dc 4076 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4077 {
4078 as_bad (_("invalid character %s in operand %d"),
4079 output_invalid (*l),
4080 i.operands + 1);
4081 return NULL;
4082 }
4083 if (!intel_syntax)
4084 {
4085 if (*l == '(')
4086 ++paren_not_balanced;
4087 if (*l == ')')
4088 --paren_not_balanced;
4089 }
4090 else
4091 {
4092 if (*l == '[')
4093 ++paren_not_balanced;
4094 if (*l == ']')
4095 --paren_not_balanced;
4096 }
4097 l++;
4098 }
4099 if (l != token_start)
4100 { /* Yes, we've read in another operand. */
4101 unsigned int operand_ok;
4102 this_operand = i.operands++;
7d5e4556 4103 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4104 if (i.operands > MAX_OPERANDS)
4105 {
4106 as_bad (_("spurious operands; (%d operands/instruction max)"),
4107 MAX_OPERANDS);
4108 return NULL;
4109 }
4110 /* Now parse operand adding info to 'i' as we go along. */
4111 END_STRING_AND_SAVE (l);
4112
4113 if (intel_syntax)
4114 operand_ok =
4115 i386_intel_operand (token_start,
4116 intel_float_operand (mnemonic));
4117 else
a7619375 4118 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4119
4120 RESTORE_END_STRING (l);
4121 if (!operand_ok)
4122 return NULL;
4123 }
4124 else
4125 {
4126 if (expecting_operand)
4127 {
4128 expecting_operand_after_comma:
4129 as_bad (_("expecting operand after ','; got nothing"));
4130 return NULL;
4131 }
4132 if (*l == ',')
4133 {
4134 as_bad (_("expecting operand before ','; got nothing"));
4135 return NULL;
4136 }
4137 }
7f3f1ea2 4138
29b0f896
AM		 4139 /* Now *l must be either ',' or END_OF_INSN. */
4140 if (*l == ',')
4141 {
4142 if (*++l == END_OF_INSN)
4143 {
4144 /* Just skip it, if it's \n complain. */
4145 goto expecting_operand_after_comma;
4146 }
4147 expecting_operand = 1;
4148 }
4149 }
4150 return l;
4151}
7f3f1ea2 4152
050dfa73 4153static void
4d456e3d 4154swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4155{
4156 union i386_op temp_op;
40fb9820 4157 i386_operand_type temp_type;
050dfa73 4158 enum bfd_reloc_code_real temp_reloc;
4eed87de 4159
050dfa73
MM		 4160 temp_type = i.types[xchg2];
4161 i.types[xchg2] = i.types[xchg1];
4162 i.types[xchg1] = temp_type;
4163 temp_op = i.op[xchg2];
4164 i.op[xchg2] = i.op[xchg1];
4165 i.op[xchg1] = temp_op;
4166 temp_reloc = i.reloc[xchg2];
4167 i.reloc[xchg2] = i.reloc[xchg1];
4168 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4169
4170 if (i.mask)
4171 {
4172 if (i.mask->operand == xchg1)
4173 i.mask->operand = xchg2;
4174 else if (i.mask->operand == xchg2)
4175 i.mask->operand = xchg1;
4176 }
4177 if (i.broadcast)
4178 {
4179 if (i.broadcast->operand == xchg1)
4180 i.broadcast->operand = xchg2;
4181 else if (i.broadcast->operand == xchg2)
4182 i.broadcast->operand = xchg1;
4183 }
4184 if (i.rounding)
4185 {
4186 if (i.rounding->operand == xchg1)
4187 i.rounding->operand = xchg2;
4188 else if (i.rounding->operand == xchg2)
4189 i.rounding->operand = xchg1;
4190 }
050dfa73
MM		 4191}
4192
29b0f896 4193static void
e3bb37b5 4194swap_operands (void)
29b0f896 4195{
b7c61d9a 4196 switch (i.operands)
050dfa73 4197 {
c0f3af97 4198 case 5:
b7c61d9a 4199 case 4:
4d456e3d 4200 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4201 case 3:
4202 case 2:
4d456e3d 4203 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4204 break;
4205 default:
4206 abort ();
29b0f896 4207 }
29b0f896
AM		 4208
4209 if (i.mem_operands == 2)
4210 {
4211 const seg_entry *temp_seg;
4212 temp_seg = i.seg[0];
4213 i.seg[0] = i.seg[1];
4214 i.seg[1] = temp_seg;
4215 }
4216}
252b5132 4217
29b0f896
AM		 4218/* Try to ensure constant immediates are represented in the smallest
4219 opcode possible. */
4220static void
e3bb37b5 4221optimize_imm (void)
29b0f896
AM		 4222{
4223 char guess_suffix = 0;
4224 int op;
252b5132 4225
29b0f896
AM		 4226 if (i.suffix)
4227 guess_suffix = i.suffix;
4228 else if (i.reg_operands)
4229 {
4230 /* Figure out a suffix from the last register operand specified.
4231 We can't do this properly yet, ie. excluding InOutPortReg,
4232 but the following works for instructions with immediates.
4233 In any case, we can't set i.suffix yet. */
4234 for (op = i.operands; --op >= 0;)
40fb9820 4235 if (i.types[op].bitfield.reg8)
7ab9ffdd 4236 {
40fb9820
L		 4237 guess_suffix = BYTE_MNEM_SUFFIX;
4238 break;
4239 }
4240 else if (i.types[op].bitfield.reg16)
252b5132 4241 {
40fb9820
L		 4242 guess_suffix = WORD_MNEM_SUFFIX;
4243 break;
4244 }
4245 else if (i.types[op].bitfield.reg32)
4246 {
4247 guess_suffix = LONG_MNEM_SUFFIX;
4248 break;
4249 }
4250 else if (i.types[op].bitfield.reg64)
4251 {
4252 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4253 break;
252b5132 4254 }
29b0f896
AM		 4255 }
4256 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4257 guess_suffix = WORD_MNEM_SUFFIX;
4258
4259 for (op = i.operands; --op >= 0;)
40fb9820 4260 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4261 {
4262 switch (i.op[op].imms->X_op)
252b5132 4263 {
29b0f896
AM		 4264 case O_constant:
4265 /* If a suffix is given, this operand may be shortened. */
4266 switch (guess_suffix)
252b5132 4267 {
29b0f896 4268 case LONG_MNEM_SUFFIX:
40fb9820
L		 4269 i.types[op].bitfield.imm32 = 1;
4270 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4271 break;
4272 case WORD_MNEM_SUFFIX:
40fb9820
L		 4273 i.types[op].bitfield.imm16 = 1;
4274 i.types[op].bitfield.imm32 = 1;
4275 i.types[op].bitfield.imm32s = 1;
4276 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4277 break;
4278 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4279 i.types[op].bitfield.imm8 = 1;
4280 i.types[op].bitfield.imm8s = 1;
4281 i.types[op].bitfield.imm16 = 1;
4282 i.types[op].bitfield.imm32 = 1;
4283 i.types[op].bitfield.imm32s = 1;
4284 i.types[op].bitfield.imm64 = 1;
29b0f896 4285 break;
252b5132 4286 }
252b5132 4287
29b0f896
AM		 4288 /* If this operand is at most 16 bits, convert it
4289 to a signed 16 bit number before trying to see
4290 whether it will fit in an even smaller size.
4291 This allows a 16-bit operand such as $0xffe0 to
4292 be recognised as within Imm8S range. */
40fb9820 4293 if ((i.types[op].bitfield.imm16)
29b0f896 4294 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4295 {
29b0f896
AM		 4296 i.op[op].imms->X_add_number =
4297 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4298 }
a28def75
L		 4299#ifdef BFD64
4300 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4301 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4302 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4303 == 0))
4304 {
4305 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4306 ^ ((offsetT) 1 << 31))
4307 - ((offsetT) 1 << 31));
4308 }
a28def75 4309#endif
40fb9820 4310 i.types[op]
c6fb90c8
L		 4311 = operand_type_or (i.types[op],
4312 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4313
29b0f896
AM		 4314 /* We must avoid matching of Imm32 templates when 64bit
4315 only immediate is available. */
4316 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4317 i.types[op].bitfield.imm32 = 0;
29b0f896 4318 break;
252b5132 4319
29b0f896
AM		 4320 case O_absent:
4321 case O_register:
4322 abort ();
4323
4324 /* Symbols and expressions. */
4325 default:
9cd96992
JB		 4326 /* Convert symbolic operand to proper sizes for matching, but don't
4327 prevent matching a set of insns that only supports sizes other
4328 than those matching the insn suffix. */
4329 {
40fb9820 4330 i386_operand_type mask, allowed;
d3ce72d0 4331 const insn_template *t;
9cd96992 4332
0dfbf9d7
L		 4333 operand_type_set (&mask, 0);
4334 operand_type_set (&allowed, 0);
40fb9820 4335
4eed87de
AM		 4336 for (t = current_templates->start;
4337 t < current_templates->end;
4338 ++t)
c6fb90c8
L		 4339 allowed = operand_type_or (allowed,
4340 t->operand_types[op]);
9cd96992
JB		 4341 switch (guess_suffix)
4342 {
4343 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4344 mask.bitfield.imm64 = 1;
4345 mask.bitfield.imm32s = 1;
9cd96992
JB		 4346 break;
4347 case LONG_MNEM_SUFFIX:
40fb9820 4348 mask.bitfield.imm32 = 1;
9cd96992
JB		 4349 break;
4350 case WORD_MNEM_SUFFIX:
40fb9820 4351 mask.bitfield.imm16 = 1;
9cd96992
JB		 4352 break;
4353 case BYTE_MNEM_SUFFIX:
40fb9820 4354 mask.bitfield.imm8 = 1;
9cd96992
JB		 4355 break;
4356 default:
9cd96992
JB		 4357 break;
4358 }
c6fb90c8 4359 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4360 if (!operand_type_all_zero (&allowed))
c6fb90c8 4361 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4362 }
29b0f896 4363 break;
252b5132 4364 }
29b0f896
AM		 4365 }
4366}
47926f60 4367
29b0f896
AM		 4368/* Try to use the smallest displacement type too. */
4369static void
e3bb37b5 4370optimize_disp (void)
29b0f896
AM		 4371{
4372 int op;
3e73aa7c 4373
29b0f896 4374 for (op = i.operands; --op >= 0;)
40fb9820 4375 if (operand_type_check (i.types[op], disp))
252b5132 4376 {
b300c311 4377 if (i.op[op].disps->X_op == O_constant)
252b5132 4378 {
91d6fa6a 4379 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4380
40fb9820 4381 if (i.types[op].bitfield.disp16
91d6fa6a 4382 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4383 {
4384 /* If this operand is at most 16 bits, convert
4385 to a signed 16 bit number and don't use 64bit
4386 displacement. */
91d6fa6a 4387 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4388 i.types[op].bitfield.disp64 = 0;
b300c311 4389 }
a28def75
L		 4390#ifdef BFD64
4391 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4392 if (i.types[op].bitfield.disp32
91d6fa6a 4393 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4394 {
4395 /* If this operand is at most 32 bits, convert
4396 to a signed 32 bit number and don't use 64bit
4397 displacement. */
91d6fa6a
NC		 4398 op_disp &= (((offsetT) 2 << 31) - 1);
4399 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4400 i.types[op].bitfield.disp64 = 0;
b300c311 4401 }
a28def75 4402#endif
91d6fa6a 4403 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4404 {
40fb9820
L		 4405 i.types[op].bitfield.disp8 = 0;
4406 i.types[op].bitfield.disp16 = 0;
4407 i.types[op].bitfield.disp32 = 0;
4408 i.types[op].bitfield.disp32s = 0;
4409 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4410 i.op[op].disps = 0;
4411 i.disp_operands--;
4412 }
4413 else if (flag_code == CODE_64BIT)
4414 {
91d6fa6a 4415 if (fits_in_signed_long (op_disp))
28a9d8f5 4416 {
40fb9820
L		 4417 i.types[op].bitfield.disp64 = 0;
4418 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4419 }
0e1147d9 4420 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4421 && fits_in_unsigned_long (op_disp))
40fb9820 4422 i.types[op].bitfield.disp32 = 1;
b300c311 4423 }
40fb9820
L		 4424 if ((i.types[op].bitfield.disp32
4425 || i.types[op].bitfield.disp32s
4426 || i.types[op].bitfield.disp16)
91d6fa6a 4427 && fits_in_signed_byte (op_disp))
40fb9820 4428 i.types[op].bitfield.disp8 = 1;
252b5132 4429 }
67a4f2b7
AO		 4430 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4431 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4432 {
4433 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4434 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4435 i.types[op].bitfield.disp8 = 0;
4436 i.types[op].bitfield.disp16 = 0;
4437 i.types[op].bitfield.disp32 = 0;
4438 i.types[op].bitfield.disp32s = 0;
4439 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4440 }
4441 else
b300c311 4442 /* We only support 64bit displacement on constants. */
40fb9820 4443 i.types[op].bitfield.disp64 = 0;
252b5132 4444 }
29b0f896
AM		 4445}
4446
6c30d220
L		 4447/* Check if operands are valid for the instruction. */
4448
4449static int
4450check_VecOperands (const insn_template *t)
4451{
43234a1e
L		 4452 unsigned int op;
4453
6c30d220
L		 4454 /* Without VSIB byte, we can't have a vector register for index. */
4455 if (!t->opcode_modifier.vecsib
4456 && i.index_reg
4457 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4458 || i.index_reg->reg_type.bitfield.regymm
4459 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4460 {
4461 i.error = unsupported_vector_index_register;
4462 return 1;
4463 }
4464
ad8ecc81
MZ		 4465 /* Check if default mask is allowed. */
4466 if (t->opcode_modifier.nodefmask
4467 && (!i.mask || i.mask->mask->reg_num == 0))
4468 {
4469 i.error = no_default_mask;
4470 return 1;
4471 }
4472
7bab8ab5
JB		 4473 /* For VSIB byte, we need a vector register for index, and all vector
4474 registers must be distinct. */
4475 if (t->opcode_modifier.vecsib)
4476 {
4477 if (!i.index_reg
6c30d220
L		 4478 || !((t->opcode_modifier.vecsib == VecSIB128
4479 && i.index_reg->reg_type.bitfield.regxmm)
4480 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4481 && i.index_reg->reg_type.bitfield.regymm)
4482 || (t->opcode_modifier.vecsib == VecSIB512
4483 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4484 {
4485 i.error = invalid_vsib_address;
4486 return 1;
4487 }
4488
43234a1e
L		 4489 gas_assert (i.reg_operands == 2 || i.mask);
4490 if (i.reg_operands == 2 && !i.mask)
4491 {
4492 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4493 || i.types[0].bitfield.regymm);
43234a1e 4494 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4495 || i.types[2].bitfield.regymm);
43234a1e
L		 4496 if (operand_check == check_none)
4497 return 0;
4498 if (register_number (i.op[0].regs)
4499 != register_number (i.index_reg)
4500 && register_number (i.op[2].regs)
4501 != register_number (i.index_reg)
4502 && register_number (i.op[0].regs)
4503 != register_number (i.op[2].regs))
4504 return 0;
4505 if (operand_check == check_error)
4506 {
4507 i.error = invalid_vector_register_set;
4508 return 1;
4509 }
4510 as_warn (_("mask, index, and destination registers should be distinct"));
4511 }
8444f82a
MZ		 4512 else if (i.reg_operands == 1 && i.mask)
4513 {
4514 if ((i.types[1].bitfield.regymm
4515 || i.types[1].bitfield.regzmm)
4516 && (register_number (i.op[1].regs)
4517 == register_number (i.index_reg)))
4518 {
4519 if (operand_check == check_error)
4520 {
4521 i.error = invalid_vector_register_set;
4522 return 1;
4523 }
4524 if (operand_check != check_none)
4525 as_warn (_("index and destination registers should be distinct"));
4526 }
4527 }
43234a1e 4528 }
7bab8ab5 4529
43234a1e
L		 4530 /* Check if broadcast is supported by the instruction and is applied
4531 to the memory operand. */
4532 if (i.broadcast)
4533 {
4534 int broadcasted_opnd_size;
4535
4536 /* Check if specified broadcast is supported in this instruction,
4537 and it's applied to memory operand of DWORD or QWORD type,
4538 depending on VecESize. */
4539 if (i.broadcast->type != t->opcode_modifier.broadcast
4540 || !i.types[i.broadcast->operand].bitfield.mem
4541 || (t->opcode_modifier.vecesize == 0
4542 && !i.types[i.broadcast->operand].bitfield.dword
4543 && !i.types[i.broadcast->operand].bitfield.unspecified)
4544 || (t->opcode_modifier.vecesize == 1
4545 && !i.types[i.broadcast->operand].bitfield.qword
4546 && !i.types[i.broadcast->operand].bitfield.unspecified))
4547 goto bad_broadcast;
4548
4549 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4550 if (i.broadcast->type == BROADCAST_1TO16)
4551 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4552 else if (i.broadcast->type == BROADCAST_1TO8)
4553 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4554 else if (i.broadcast->type == BROADCAST_1TO4)
4555 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4556 else if (i.broadcast->type == BROADCAST_1TO2)
4557 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4558 else
4559 goto bad_broadcast;
4560
4561 if ((broadcasted_opnd_size == 256
4562 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4563 || (broadcasted_opnd_size == 512
4564 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4565 {
4566 bad_broadcast:
4567 i.error = unsupported_broadcast;
4568 return 1;
4569 }
4570 }
4571 /* If broadcast is supported in this instruction, we need to check if
4572 operand of one-element size isn't specified without broadcast. */
4573 else if (t->opcode_modifier.broadcast && i.mem_operands)
4574 {
4575 /* Find memory operand. */
4576 for (op = 0; op < i.operands; op++)
4577 if (operand_type_check (i.types[op], anymem))
4578 break;
4579 gas_assert (op < i.operands);
4580 /* Check size of the memory operand. */
4581 if ((t->opcode_modifier.vecesize == 0
4582 && i.types[op].bitfield.dword)
4583 || (t->opcode_modifier.vecesize == 1
4584 && i.types[op].bitfield.qword))
4585 {
4586 i.error = broadcast_needed;
4587 return 1;
4588 }
4589 }
4590
4591 /* Check if requested masking is supported. */
4592 if (i.mask
4593 && (!t->opcode_modifier.masking
4594 || (i.mask->zeroing
4595 && t->opcode_modifier.masking == MERGING_MASKING)))
4596 {
4597 i.error = unsupported_masking;
4598 return 1;
4599 }
4600
4601 /* Check if masking is applied to dest operand. */
4602 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4603 {
4604 i.error = mask_not_on_destination;
4605 return 1;
4606 }
4607
43234a1e
L		 4608 /* Check RC/SAE. */
4609 if (i.rounding)
4610 {
4611 if ((i.rounding->type != saeonly
4612 && !t->opcode_modifier.staticrounding)
4613 || (i.rounding->type == saeonly
4614 && (t->opcode_modifier.staticrounding
4615 || !t->opcode_modifier.sae)))
4616 {
4617 i.error = unsupported_rc_sae;
4618 return 1;
4619 }
4620 /* If the instruction has several immediate operands and one of
4621 them is rounding, the rounding operand should be the last
4622 immediate operand. */
4623 if (i.imm_operands > 1
4624 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4625 {
43234a1e 4626 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4627 return 1;
4628 }
6c30d220
L		 4629 }
4630
43234a1e
L		 4631 /* Check vector Disp8 operand. */
4632 if (t->opcode_modifier.disp8memshift)
4633 {
4634 if (i.broadcast)
4635 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4636 else
4637 i.memshift = t->opcode_modifier.disp8memshift;
4638
4639 for (op = 0; op < i.operands; op++)
4640 if (operand_type_check (i.types[op], disp)
4641 && i.op[op].disps->X_op == O_constant)
4642 {
4643 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4644 int vec_disp8_ok
4645 = (i.disp_encoding != disp_encoding_32bit
4646 && fits_in_vec_disp8 (value));
43234a1e
L		 4647 if (t->operand_types [op].bitfield.vec_disp8)
4648 {
4649 if (vec_disp8_ok)
4650 i.types[op].bitfield.vec_disp8 = 1;
4651 else
4652 {
4653 /* Vector insn can only have Vec_Disp8/Disp32 in
4654 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4655 mode. */
4656 i.types[op].bitfield.disp8 = 0;
4657 if (flag_code != CODE_16BIT)
4658 i.types[op].bitfield.disp16 = 0;
4659 }
4660 }
4661 else if (flag_code != CODE_16BIT)
4662 {
4663 /* One form of this instruction supports vector Disp8.
4664 Try vector Disp8 if we need to use Disp32. */
4665 if (vec_disp8_ok && !fits_in_signed_byte (value))
4666 {
4667 i.error = try_vector_disp8;
4668 return 1;
4669 }
4670 }
4671 }
4672 }
4673 else
4674 i.memshift = -1;
4675
6c30d220
L		 4676 return 0;
4677}
4678
43f3e2ee 4679/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4680 operand types. */
4681
4682static int
4683VEX_check_operands (const insn_template *t)
4684{
43234a1e
L		 4685 /* VREX is only valid with EVEX prefix. */
4686 if (i.need_vrex && !t->opcode_modifier.evex)
4687 {
4688 i.error = invalid_register_operand;
4689 return 1;
4690 }
4691
a683cc34
SP		 4692 if (!t->opcode_modifier.vex)
4693 return 0;
4694
4695 /* Only check VEX_Imm4, which must be the first operand. */
4696 if (t->operand_types[0].bitfield.vec_imm4)
4697 {
4698 if (i.op[0].imms->X_op != O_constant
4699 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4700 {
a65babc9 4701 i.error = bad_imm4;
891edac4
L		 4702 return 1;
4703 }
a683cc34
SP		 4704
4705 /* Turn off Imm8 so that update_imm won't complain. */
4706 i.types[0] = vec_imm4;
4707 }
4708
4709 return 0;
4710}
4711
d3ce72d0 4712static const insn_template *
e3bb37b5 4713match_template (void)
29b0f896
AM		 4714{
4715 /* Points to template once we've found it. */
d3ce72d0 4716 const insn_template *t;
40fb9820 4717 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4718 i386_operand_type overlap4;
29b0f896 4719 unsigned int found_reverse_match;
40fb9820
L		 4720 i386_opcode_modifier suffix_check;
4721 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4722 int addr_prefix_disp;
a5c311ca 4723 unsigned int j;
3629bb00 4724 unsigned int found_cpu_match;
45664ddb 4725 unsigned int check_register;
5614d22c 4726 enum i386_error specific_error = 0;
29b0f896 4727
c0f3af97
L		 4728#if MAX_OPERANDS != 5
4729# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4730#endif
4731
29b0f896 4732 found_reverse_match = 0;
539e75ad 4733 addr_prefix_disp = -1;
40fb9820
L		 4734
4735 memset (&suffix_check, 0, sizeof (suffix_check));
4736 if (i.suffix == BYTE_MNEM_SUFFIX)
4737 suffix_check.no_bsuf = 1;
4738 else if (i.suffix == WORD_MNEM_SUFFIX)
4739 suffix_check.no_wsuf = 1;
4740 else if (i.suffix == SHORT_MNEM_SUFFIX)
4741 suffix_check.no_ssuf = 1;
4742 else if (i.suffix == LONG_MNEM_SUFFIX)
4743 suffix_check.no_lsuf = 1;
4744 else if (i.suffix == QWORD_MNEM_SUFFIX)
4745 suffix_check.no_qsuf = 1;
4746 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4747 suffix_check.no_ldsuf = 1;
29b0f896 4748
01559ecc
L		 4749 /* Must have right number of operands. */
4750 i.error = number_of_operands_mismatch;
4751
45aa61fe 4752 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4753 {
539e75ad
L		 4754 addr_prefix_disp = -1;
4755
29b0f896
AM		 4756 if (i.operands != t->operands)
4757 continue;
4758
50aecf8c 4759 /* Check processor support. */
a65babc9 4760 i.error = unsupported;
c0f3af97
L		 4761 found_cpu_match = (cpu_flags_match (t)
4762 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4763 if (!found_cpu_match)
4764 continue;
4765
e1d4d893 4766 /* Check old gcc support. */
a65babc9 4767 i.error = old_gcc_only;
e1d4d893
L		 4768 if (!old_gcc && t->opcode_modifier.oldgcc)
4769 continue;
4770
4771 /* Check AT&T mnemonic. */
a65babc9 4772 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4773 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4774 continue;
4775
e92bae62 4776 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4777 i.error = unsupported_syntax;
5c07affc 4778 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4779 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4780 || (intel64 && t->opcode_modifier.amd64)
4781 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4782 continue;
4783
20592a94 4784 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4785 i.error = invalid_instruction_suffix;
567e4e96
L		 4786 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4787 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4788 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4789 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4790 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4791 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4792 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4793 continue;
4794
5c07affc 4795 if (!operand_size_match (t))
7d5e4556 4796 continue;
539e75ad 4797
5c07affc
L		 4798 for (j = 0; j < MAX_OPERANDS; j++)
4799 operand_types[j] = t->operand_types[j];
4800
45aa61fe
AM		 4801 /* In general, don't allow 64-bit operands in 32-bit mode. */
4802 if (i.suffix == QWORD_MNEM_SUFFIX
4803 && flag_code != CODE_64BIT
4804 && (intel_syntax
40fb9820 4805 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4806 && !intel_float_operand (t->name))
4807 : intel_float_operand (t->name) != 2)
40fb9820 4808 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4809 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4810 && !operand_types[0].bitfield.regymm
4811 && !operand_types[0].bitfield.regzmm)
40fb9820 4812 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4813 && operand_types[t->operands > 1].bitfield.regxmm
4814 && operand_types[t->operands > 1].bitfield.regymm
4815 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4816 && (t->base_opcode != 0x0fc7
4817 || t->extension_opcode != 1 /* cmpxchg8b */))
4818 continue;
4819
192dc9c6
JB		 4820 /* In general, don't allow 32-bit operands on pre-386. */
4821 else if (i.suffix == LONG_MNEM_SUFFIX
4822 && !cpu_arch_flags.bitfield.cpui386
4823 && (intel_syntax
4824 ? (!t->opcode_modifier.ignoresize
4825 && !intel_float_operand (t->name))
4826 : intel_float_operand (t->name) != 2)
4827 && ((!operand_types[0].bitfield.regmmx
4828 && !operand_types[0].bitfield.regxmm)
4829 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4830 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4831 continue;
4832
29b0f896 4833 /* Do not verify operands when there are none. */
50aecf8c 4834 else
29b0f896 4835 {
c6fb90c8 4836 if (!t->operands)
2dbab7d5
L		 4837 /* We've found a match; break out of loop. */
4838 break;
29b0f896 4839 }
252b5132 4840
539e75ad
L		 4841 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4842 into Disp32/Disp16/Disp32 operand. */
4843 if (i.prefix[ADDR_PREFIX] != 0)
4844 {
40fb9820 4845 /* There should be only one Disp operand. */
539e75ad
L		 4846 switch (flag_code)
4847 {
4848 case CODE_16BIT:
40fb9820
L		 4849 for (j = 0; j < MAX_OPERANDS; j++)
4850 {
4851 if (operand_types[j].bitfield.disp16)
4852 {
4853 addr_prefix_disp = j;
4854 operand_types[j].bitfield.disp32 = 1;
4855 operand_types[j].bitfield.disp16 = 0;
4856 break;
4857 }
4858 }
539e75ad
L		 4859 break;
4860 case CODE_32BIT:
40fb9820
L		 4861 for (j = 0; j < MAX_OPERANDS; j++)
4862 {
4863 if (operand_types[j].bitfield.disp32)
4864 {
4865 addr_prefix_disp = j;
4866 operand_types[j].bitfield.disp32 = 0;
4867 operand_types[j].bitfield.disp16 = 1;
4868 break;
4869 }
4870 }
539e75ad
L		 4871 break;
4872 case CODE_64BIT:
40fb9820
L		 4873 for (j = 0; j < MAX_OPERANDS; j++)
4874 {
4875 if (operand_types[j].bitfield.disp64)
4876 {
4877 addr_prefix_disp = j;
4878 operand_types[j].bitfield.disp64 = 0;
4879 operand_types[j].bitfield.disp32 = 1;
4880 break;
4881 }
4882 }
539e75ad
L		 4883 break;
4884 }
539e75ad
L		 4885 }
4886
02a86693
L		 4887 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4888 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4889 continue;
4890
56ffb741
L		 4891 /* We check register size if needed. */
4892 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4893 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4894 switch (t->operands)
4895 {
4896 case 1:
40fb9820 4897 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4898 continue;
4899 break;
4900 case 2:
8b38ad71
L		 4901 /* xchg %eax, %eax is a special case. It is an aliase for nop
4902 only in 32bit mode and we can use opcode 0x90. In 64bit
4903 mode, we can't use 0x90 for xchg %eax, %eax since it should
4904 zero-extend %eax to %rax. */
4905 if (flag_code == CODE_64BIT
4906 && t->base_opcode == 0x90
0dfbf9d7
L		 4907 && operand_type_equal (&i.types [0], &acc32)
4908 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4909 continue;
b6169b20
L		 4910 if (i.swap_operand)
4911 {
4912 /* If we swap operand in encoding, we either match
4913 the next one or reverse direction of operands. */
4914 if (t->opcode_modifier.s)
4915 continue;
4916 else if (t->opcode_modifier.d)
4917 goto check_reverse;
4918 }
4919
29b0f896 4920 case 3:
fa99fab2
L		 4921 /* If we swap operand in encoding, we match the next one. */
4922 if (i.swap_operand && t->opcode_modifier.s)
4923 continue;
f48ff2ae 4924 case 4:
c0f3af97 4925 case 5:
c6fb90c8 4926 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4927 if (!operand_type_match (overlap0, i.types[0])
4928 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4929 || (check_register
4930 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4931 operand_types[0],
4932 overlap1, i.types[1],
4933 operand_types[1])))
29b0f896
AM		 4934 {
4935 /* Check if other direction is valid ... */
40fb9820 4936 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4937 continue;
4938
b6169b20 4939check_reverse:
29b0f896 4940 /* Try reversing direction of operands. */
c6fb90c8
L		 4941 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4942 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4943 if (!operand_type_match (overlap0, i.types[0])
4944 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4945 || (check_register
4946 && !operand_type_register_match (overlap0,
4947 i.types[0],
4948 operand_types[1],
4949 overlap1,
4950 i.types[1],
4951 operand_types[0])))
29b0f896
AM		 4952 {
4953 /* Does not match either direction. */
4954 continue;
4955 }
4956 /* found_reverse_match holds which of D or FloatDR
4957 we've found. */
40fb9820 4958 if (t->opcode_modifier.d)
8a2ed489 4959 found_reverse_match = Opcode_D;
40fb9820 4960 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4961 found_reverse_match = Opcode_FloatD;
4962 else
4963 found_reverse_match = 0;
40fb9820 4964 if (t->opcode_modifier.floatr)
8a2ed489 4965 found_reverse_match |= Opcode_FloatR;
29b0f896 4966 }
f48ff2ae 4967 else
29b0f896 4968 {
f48ff2ae 4969 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4970 switch (t->operands)
4971 {
c0f3af97
L		 4972 case 5:
4973 overlap4 = operand_type_and (i.types[4],
4974 operand_types[4]);
d1cbb4db 4975 case 4:
c6fb90c8
L		 4976 overlap3 = operand_type_and (i.types[3],
4977 operand_types[3]);
d1cbb4db 4978 case 3:
c6fb90c8
L		 4979 overlap2 = operand_type_and (i.types[2],
4980 operand_types[2]);
d1cbb4db
L		 4981 break;
4982 }
29b0f896 4983
f48ff2ae
L		 4984 switch (t->operands)
4985 {
c0f3af97
L		 4986 case 5:
4987 if (!operand_type_match (overlap4, i.types[4])
4988 || !operand_type_register_match (overlap3,
4989 i.types[3],
4990 operand_types[3],
4991 overlap4,
4992 i.types[4],
4993 operand_types[4]))
4994 continue;
f48ff2ae 4995 case 4:
40fb9820 4996 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4997 || (check_register
4998 && !operand_type_register_match (overlap2,
4999 i.types[2],
5000 operand_types[2],
5001 overlap3,
5002 i.types[3],
5003 operand_types[3])))
f48ff2ae
L		 5004 continue;
5005 case 3:
5006 /* Here we make use of the fact that there are no
5007 reverse match 3 operand instructions, and all 3
5008 operand instructions only need to be checked for
5009 register consistency between operands 2 and 3. */
40fb9820 5010 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5011 || (check_register
5012 && !operand_type_register_match (overlap1,
5013 i.types[1],
5014 operand_types[1],
5015 overlap2,
5016 i.types[2],
5017 operand_types[2])))
f48ff2ae
L		 5018 continue;
5019 break;
5020 }
29b0f896 5021 }
f48ff2ae 5022 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5023 slip through to break. */
5024 }
3629bb00 5025 if (!found_cpu_match)
29b0f896
AM		 5026 {
5027 found_reverse_match = 0;
5028 continue;
5029 }
c0f3af97 5030
5614d22c
JB		 5031 /* Check if vector and VEX operands are valid. */
5032 if (check_VecOperands (t) || VEX_check_operands (t))
5033 {
5034 specific_error = i.error;
5035 continue;
5036 }
a683cc34 5037
29b0f896
AM		 5038 /* We've found a match; break out of loop. */
5039 break;
5040 }
5041
5042 if (t == current_templates->end)
5043 {
5044 /* We found no match. */
a65babc9 5045 const char *err_msg;
5614d22c 5046 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5047 {
5048 default:
5049 abort ();
86e026a4 5050 case operand_size_mismatch:
a65babc9
L		 5051 err_msg = _("operand size mismatch");
5052 break;
5053 case operand_type_mismatch:
5054 err_msg = _("operand type mismatch");
5055 break;
5056 case register_type_mismatch:
5057 err_msg = _("register type mismatch");
5058 break;
5059 case number_of_operands_mismatch:
5060 err_msg = _("number of operands mismatch");
5061 break;
5062 case invalid_instruction_suffix:
5063 err_msg = _("invalid instruction suffix");
5064 break;
5065 case bad_imm4:
4a2608e3 5066 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5067 break;
5068 case old_gcc_only:
5069 err_msg = _("only supported with old gcc");
5070 break;
5071 case unsupported_with_intel_mnemonic:
5072 err_msg = _("unsupported with Intel mnemonic");
5073 break;
5074 case unsupported_syntax:
5075 err_msg = _("unsupported syntax");
5076 break;
5077 case unsupported:
35262a23 5078 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5079 current_templates->start->name);
5080 return NULL;
6c30d220
L		 5081 case invalid_vsib_address:
5082 err_msg = _("invalid VSIB address");
5083 break;
7bab8ab5
JB		 5084 case invalid_vector_register_set:
5085 err_msg = _("mask, index, and destination registers must be distinct");
5086 break;
6c30d220
L		 5087 case unsupported_vector_index_register:
5088 err_msg = _("unsupported vector index register");
5089 break;
43234a1e
L		 5090 case unsupported_broadcast:
5091 err_msg = _("unsupported broadcast");
5092 break;
5093 case broadcast_not_on_src_operand:
5094 err_msg = _("broadcast not on source memory operand");
5095 break;
5096 case broadcast_needed:
5097 err_msg = _("broadcast is needed for operand of such type");
5098 break;
5099 case unsupported_masking:
5100 err_msg = _("unsupported masking");
5101 break;
5102 case mask_not_on_destination:
5103 err_msg = _("mask not on destination operand");
5104 break;
5105 case no_default_mask:
5106 err_msg = _("default mask isn't allowed");
5107 break;
5108 case unsupported_rc_sae:
5109 err_msg = _("unsupported static rounding/sae");
5110 break;
5111 case rc_sae_operand_not_last_imm:
5112 if (intel_syntax)
5113 err_msg = _("RC/SAE operand must precede immediate operands");
5114 else
5115 err_msg = _("RC/SAE operand must follow immediate operands");
5116 break;
5117 case invalid_register_operand:
5118 err_msg = _("invalid register operand");
5119 break;
a65babc9
L		 5120 }
5121 as_bad (_("%s for `%s'"), err_msg,
891edac4 5122 current_templates->start->name);
fa99fab2 5123 return NULL;
29b0f896 5124 }
252b5132 5125
29b0f896
AM		 5126 if (!quiet_warnings)
5127 {
5128 if (!intel_syntax
40fb9820
L		 5129 && (i.types[0].bitfield.jumpabsolute
5130 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5131 {
5132 as_warn (_("indirect %s without `*'"), t->name);
5133 }
5134
40fb9820
L		 5135 if (t->opcode_modifier.isprefix
5136 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5137 {
5138 /* Warn them that a data or address size prefix doesn't
5139 affect assembly of the next line of code. */
5140 as_warn (_("stand-alone `%s' prefix"), t->name);
5141 }
5142 }
5143
5144 /* Copy the template we found. */
5145 i.tm = *t;
539e75ad
L		 5146
5147 if (addr_prefix_disp != -1)
5148 i.tm.operand_types[addr_prefix_disp]
5149 = operand_types[addr_prefix_disp];
5150
29b0f896
AM		 5151 if (found_reverse_match)
5152 {
5153 /* If we found a reverse match we must alter the opcode
5154 direction bit. found_reverse_match holds bits to change
5155 (different for int & float insns). */
5156
5157 i.tm.base_opcode ^= found_reverse_match;
5158
539e75ad
L		 5159 i.tm.operand_types[0] = operand_types[1];
5160 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5161 }
5162
fa99fab2 5163 return t;
29b0f896
AM		 5164}
5165
5166static int
e3bb37b5 5167check_string (void)
29b0f896 5168{
40fb9820
L		 5169 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5170 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5171 {
5172 if (i.seg[0] != NULL && i.seg[0] != &es)
5173 {
a87af027 5174 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5175 i.tm.name,
a87af027
JB		 5176 mem_op + 1,
5177 register_prefix);
29b0f896
AM		 5178 return 0;
5179 }
5180 /* There's only ever one segment override allowed per instruction.
5181 This instruction possibly has a legal segment override on the
5182 second operand, so copy the segment to where non-string
5183 instructions store it, allowing common code. */
5184 i.seg[0] = i.seg[1];
5185 }
40fb9820 5186 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5187 {
5188 if (i.seg[1] != NULL && i.seg[1] != &es)
5189 {
a87af027 5190 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5191 i.tm.name,
a87af027
JB		 5192 mem_op + 2,
5193 register_prefix);
29b0f896
AM		 5194 return 0;
5195 }
5196 }
5197 return 1;
5198}
5199
5200static int
543613e9 5201process_suffix (void)
29b0f896
AM		 5202{
5203 /* If matched instruction specifies an explicit instruction mnemonic
5204 suffix, use it. */
40fb9820
L		 5205 if (i.tm.opcode_modifier.size16)
5206 i.suffix = WORD_MNEM_SUFFIX;
5207 else if (i.tm.opcode_modifier.size32)
5208 i.suffix = LONG_MNEM_SUFFIX;
5209 else if (i.tm.opcode_modifier.size64)
5210 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5211 else if (i.reg_operands)
5212 {
5213 /* If there's no instruction mnemonic suffix we try to invent one
5214 based on register operands. */
5215 if (!i.suffix)
5216 {
5217 /* We take i.suffix from the last register operand specified,
5218 Destination register type is more significant than source
381d071f
L		 5219 register type. crc32 in SSE4.2 prefers source register
5220 type. */
5221 if (i.tm.base_opcode == 0xf20f38f1)
5222 {
40fb9820
L		 5223 if (i.types[0].bitfield.reg16)
5224 i.suffix = WORD_MNEM_SUFFIX;
5225 else if (i.types[0].bitfield.reg32)
5226 i.suffix = LONG_MNEM_SUFFIX;
5227 else if (i.types[0].bitfield.reg64)
5228 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5229 }
9344ff29 5230 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5231 {
40fb9820 5232 if (i.types[0].bitfield.reg8)
20592a94
L		 5233 i.suffix = BYTE_MNEM_SUFFIX;
5234 }
381d071f
L		 5235
5236 if (!i.suffix)
5237 {
5238 int op;
5239
20592a94
L		 5240 if (i.tm.base_opcode == 0xf20f38f1
5241 || i.tm.base_opcode == 0xf20f38f0)
5242 {
5243 /* We have to know the operand size for crc32. */
5244 as_bad (_("ambiguous memory operand size for `%s`"),
5245 i.tm.name);
5246 return 0;
5247 }
5248
381d071f 5249 for (op = i.operands; --op >= 0;)
40fb9820 5250 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5251 {
40fb9820
L		 5252 if (i.types[op].bitfield.reg8)
5253 {
5254 i.suffix = BYTE_MNEM_SUFFIX;
5255 break;
5256 }
5257 else if (i.types[op].bitfield.reg16)
5258 {
5259 i.suffix = WORD_MNEM_SUFFIX;
5260 break;
5261 }
5262 else if (i.types[op].bitfield.reg32)
5263 {
5264 i.suffix = LONG_MNEM_SUFFIX;
5265 break;
5266 }
5267 else if (i.types[op].bitfield.reg64)
5268 {
5269 i.suffix = QWORD_MNEM_SUFFIX;
5270 break;
5271 }
381d071f
L		 5272 }
5273 }
29b0f896
AM		 5274 }
5275 else if (i.suffix == BYTE_MNEM_SUFFIX)
5276 {
2eb952a4
L		 5277 if (intel_syntax
5278 && i.tm.opcode_modifier.ignoresize
5279 && i.tm.opcode_modifier.no_bsuf)
5280 i.suffix = 0;
5281 else if (!check_byte_reg ())
29b0f896
AM		 5282 return 0;
5283 }
5284 else if (i.suffix == LONG_MNEM_SUFFIX)
5285 {
2eb952a4
L		 5286 if (intel_syntax
5287 && i.tm.opcode_modifier.ignoresize
5288 && i.tm.opcode_modifier.no_lsuf)
5289 i.suffix = 0;
5290 else if (!check_long_reg ())
29b0f896
AM		 5291 return 0;
5292 }
5293 else if (i.suffix == QWORD_MNEM_SUFFIX)
5294 {
955e1e6a
L		 5295 if (intel_syntax
5296 && i.tm.opcode_modifier.ignoresize
5297 && i.tm.opcode_modifier.no_qsuf)
5298 i.suffix = 0;
5299 else if (!check_qword_reg ())
29b0f896
AM		 5300 return 0;
5301 }
5302 else if (i.suffix == WORD_MNEM_SUFFIX)
5303 {
2eb952a4
L		 5304 if (intel_syntax
5305 && i.tm.opcode_modifier.ignoresize
5306 && i.tm.opcode_modifier.no_wsuf)
5307 i.suffix = 0;
5308 else if (!check_word_reg ())
29b0f896
AM		 5309 return 0;
5310 }
c0f3af97 5311 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5312 || i.suffix == YMMWORD_MNEM_SUFFIX
5313 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5314 {
43234a1e 5315 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5316 should check if it is a valid suffix. */
5317 }
40fb9820 5318 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5319 /* Do nothing if the instruction is going to ignore the prefix. */
5320 ;
5321 else
5322 abort ();
5323 }
40fb9820 5324 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5325 && !i.suffix
5326 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5327 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5328 {
5329 i.suffix = stackop_size;
5330 }
9306ca4a
JB		 5331 else if (intel_syntax
5332 && !i.suffix
40fb9820
L		 5333 && (i.tm.operand_types[0].bitfield.jumpabsolute
5334 || i.tm.opcode_modifier.jumpbyte
5335 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5336 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5337 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5338 {
5339 switch (flag_code)
5340 {
5341 case CODE_64BIT:
40fb9820 5342 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5343 {
5344 i.suffix = QWORD_MNEM_SUFFIX;
5345 break;
5346 }
5347 case CODE_32BIT:
40fb9820 5348 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5349 i.suffix = LONG_MNEM_SUFFIX;
5350 break;
5351 case CODE_16BIT:
40fb9820 5352 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5353 i.suffix = WORD_MNEM_SUFFIX;
5354 break;
5355 }
5356 }
252b5132 5357
9306ca4a 5358 if (!i.suffix)
29b0f896 5359 {
9306ca4a
JB		 5360 if (!intel_syntax)
5361 {
40fb9820 5362 if (i.tm.opcode_modifier.w)
9306ca4a 5363 {
4eed87de
AM		 5364 as_bad (_("no instruction mnemonic suffix given and "
5365 "no register operands; can't size instruction"));
9306ca4a
JB		 5366 return 0;
5367 }
5368 }
5369 else
5370 {
40fb9820 5371 unsigned int suffixes;
7ab9ffdd 5372
40fb9820
L		 5373 suffixes = !i.tm.opcode_modifier.no_bsuf;
5374 if (!i.tm.opcode_modifier.no_wsuf)
5375 suffixes |= 1 << 1;
5376 if (!i.tm.opcode_modifier.no_lsuf)
5377 suffixes |= 1 << 2;
fc4adea1 5378 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5379 suffixes |= 1 << 3;
5380 if (!i.tm.opcode_modifier.no_ssuf)
5381 suffixes |= 1 << 4;
5382 if (!i.tm.opcode_modifier.no_qsuf)
5383 suffixes |= 1 << 5;
5384
5385 /* There are more than suffix matches. */
5386 if (i.tm.opcode_modifier.w
9306ca4a 5387 || ((suffixes & (suffixes - 1))
40fb9820
L		 5388 && !i.tm.opcode_modifier.defaultsize
5389 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5390 {
5391 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5392 return 0;
5393 }
5394 }
29b0f896 5395 }
252b5132 5396
9306ca4a
JB		 5397 /* Change the opcode based on the operand size given by i.suffix;
5398 We don't need to change things for byte insns. */
5399
582d5edd
L		 5400 if (i.suffix
5401 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5402 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5403 && i.suffix != YMMWORD_MNEM_SUFFIX
5404 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5405 {
5406 /* It's not a byte, select word/dword operation. */
40fb9820 5407 if (i.tm.opcode_modifier.w)
29b0f896 5408 {
40fb9820 5409 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5410 i.tm.base_opcode |= 8;
5411 else
5412 i.tm.base_opcode |= 1;
5413 }
0f3f3d8b 5414
29b0f896
AM		 5415 /* Now select between word & dword operations via the operand
5416 size prefix, except for instructions that will ignore this
5417 prefix anyway. */
ca61edf2 5418 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5419 {
ca61edf2
L		 5420 /* The address size override prefix changes the size of the
5421 first operand. */
40fb9820
L		 5422 if ((flag_code == CODE_32BIT
5423 && i.op->regs[0].reg_type.bitfield.reg16)
5424 || (flag_code != CODE_32BIT
5425 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5426 if (!add_prefix (ADDR_PREFIX_OPCODE))
5427 return 0;
5428 }
5429 else if (i.suffix != QWORD_MNEM_SUFFIX
5430 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5431 && !i.tm.opcode_modifier.ignoresize
5432 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5433 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5434 || (flag_code == CODE_64BIT
40fb9820 5435 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5436 {
5437 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5438
40fb9820 5439 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5440 prefix = ADDR_PREFIX_OPCODE;
252b5132 5441
29b0f896
AM		 5442 if (!add_prefix (prefix))
5443 return 0;
24eab124 5444 }
252b5132 5445
29b0f896
AM		 5446 /* Set mode64 for an operand. */
5447 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5448 && flag_code == CODE_64BIT
40fb9820 5449 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5450 {
5451 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5452 need rex64. cmpxchg8b is also a special case. */
5453 if (! (i.operands == 2
5454 && i.tm.base_opcode == 0x90
5455 && i.tm.extension_opcode == None
0dfbf9d7
L		 5456 && operand_type_equal (&i.types [0], &acc64)
5457 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5458 && ! (i.operands == 1
5459 && i.tm.base_opcode == 0xfc7
5460 && i.tm.extension_opcode == 1
40fb9820
L		 5461 && !operand_type_check (i.types [0], reg)
5462 && operand_type_check (i.types [0], anymem)))
f6bee062 5463 i.rex |= REX_W;
46e883c5 5464 }
3e73aa7c 5465
29b0f896
AM		 5466 /* Size floating point instruction. */
5467 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5468 if (i.tm.opcode_modifier.floatmf)
543613e9 5469 i.tm.base_opcode ^= 4;
29b0f896 5470 }
7ecd2f8b 5471
29b0f896
AM		 5472 return 1;
5473}
3e73aa7c 5474
29b0f896 5475static int
543613e9 5476check_byte_reg (void)
29b0f896
AM		 5477{
5478 int op;
543613e9 5479
29b0f896
AM		 5480 for (op = i.operands; --op >= 0;)
5481 {
5482 /* If this is an eight bit register, it's OK. If it's the 16 or
5483 32 bit version of an eight bit register, we will just use the
5484 low portion, and that's OK too. */
40fb9820 5485 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5486 continue;
5487
5a819eb9
JB		 5488 /* I/O port address operands are OK too. */
5489 if (i.tm.operand_types[op].bitfield.inoutportreg)
5490 continue;
5491
9344ff29
L		 5492 /* crc32 doesn't generate this warning. */
5493 if (i.tm.base_opcode == 0xf20f38f0)
5494 continue;
5495
40fb9820
L		 5496 if ((i.types[op].bitfield.reg16
5497 || i.types[op].bitfield.reg32
5498 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5499 && i.op[op].regs->reg_num < 4
5500 /* Prohibit these changes in 64bit mode, since the lowering
5501 would be more complicated. */
5502 && flag_code != CODE_64BIT)
29b0f896 5503 {
29b0f896 5504#if REGISTER_WARNINGS
5a819eb9 5505 if (!quiet_warnings)
a540244d
L		 5506 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5507 register_prefix,
40fb9820 5508 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5509 ? REGNAM_AL - REGNAM_AX
5510 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5511 register_prefix,
29b0f896
AM		 5512 i.op[op].regs->reg_name,
5513 i.suffix);
5514#endif
5515 continue;
5516 }
5517 /* Any other register is bad. */
40fb9820
L		 5518 if (i.types[op].bitfield.reg16
5519 || i.types[op].bitfield.reg32
5520 || i.types[op].bitfield.reg64
5521 || i.types[op].bitfield.regmmx
5522 || i.types[op].bitfield.regxmm
c0f3af97 5523 || i.types[op].bitfield.regymm
43234a1e 5524 || i.types[op].bitfield.regzmm
40fb9820
L		 5525 || i.types[op].bitfield.sreg2
5526 || i.types[op].bitfield.sreg3
5527 || i.types[op].bitfield.control
5528 || i.types[op].bitfield.debug
5529 || i.types[op].bitfield.test
5530 || i.types[op].bitfield.floatreg
5531 || i.types[op].bitfield.floatacc)
29b0f896 5532 {
a540244d
L		 5533 as_bad (_("`%s%s' not allowed with `%s%c'"),
5534 register_prefix,
29b0f896
AM		 5535 i.op[op].regs->reg_name,
5536 i.tm.name,
5537 i.suffix);
5538 return 0;
5539 }
5540 }
5541 return 1;
5542}
5543
5544static int
e3bb37b5 5545check_long_reg (void)
29b0f896
AM		 5546{
5547 int op;
5548
5549 for (op = i.operands; --op >= 0;)
5550 /* Reject eight bit registers, except where the template requires
5551 them. (eg. movzb) */
40fb9820
L		 5552 if (i.types[op].bitfield.reg8
5553 && (i.tm.operand_types[op].bitfield.reg16
5554 || i.tm.operand_types[op].bitfield.reg32
5555 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5556 {
a540244d
L		 5557 as_bad (_("`%s%s' not allowed with `%s%c'"),
5558 register_prefix,
29b0f896
AM		 5559 i.op[op].regs->reg_name,
5560 i.tm.name,
5561 i.suffix);
5562 return 0;
5563 }
e4630f71 5564 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5565 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5566 && i.types[op].bitfield.reg16
5567 && (i.tm.operand_types[op].bitfield.reg32
5568 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5569 {
5570 /* Prohibit these changes in the 64bit mode, since the
5571 lowering is more complicated. */
5572 if (flag_code == CODE_64BIT)
252b5132 5573 {
2b5d6a91 5574 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5575 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5576 i.suffix);
5577 return 0;
252b5132 5578 }
29b0f896 5579#if REGISTER_WARNINGS
cecf1424
JB		 5580 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5581 register_prefix,
5582 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5583 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5584#endif
252b5132 5585 }
e4630f71 5586 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5587 else if (i.types[op].bitfield.reg64
5588 && (i.tm.operand_types[op].bitfield.reg32
5589 || i.tm.operand_types[op].bitfield.acc))
252b5132 5590 {
34828aad 5591 if (intel_syntax
ca61edf2 5592 && i.tm.opcode_modifier.toqword
40fb9820 5593 && !i.types[0].bitfield.regxmm)
34828aad 5594 {
ca61edf2 5595 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5596 i.suffix = QWORD_MNEM_SUFFIX;
5597 }
5598 else
5599 {
2b5d6a91 5600 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5601 register_prefix, i.op[op].regs->reg_name,
5602 i.suffix);
5603 return 0;
5604 }
29b0f896
AM		 5605 }
5606 return 1;
5607}
252b5132 5608
29b0f896 5609static int
e3bb37b5 5610check_qword_reg (void)
29b0f896
AM		 5611{
5612 int op;
252b5132 5613
29b0f896
AM		 5614 for (op = i.operands; --op >= 0; )
5615 /* Reject eight bit registers, except where the template requires
5616 them. (eg. movzb) */
40fb9820
L		 5617 if (i.types[op].bitfield.reg8
5618 && (i.tm.operand_types[op].bitfield.reg16
5619 || i.tm.operand_types[op].bitfield.reg32
5620 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5621 {
a540244d
L		 5622 as_bad (_("`%s%s' not allowed with `%s%c'"),
5623 register_prefix,
29b0f896
AM		 5624 i.op[op].regs->reg_name,
5625 i.tm.name,
5626 i.suffix);
5627 return 0;
5628 }
e4630f71 5629 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5630 else if ((i.types[op].bitfield.reg16
5631 || i.types[op].bitfield.reg32)
5632 && (i.tm.operand_types[op].bitfield.reg32
5633 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5634 {
5635 /* Prohibit these changes in the 64bit mode, since the
5636 lowering is more complicated. */
34828aad 5637 if (intel_syntax
ca61edf2 5638 && i.tm.opcode_modifier.todword
40fb9820 5639 && !i.types[0].bitfield.regxmm)
34828aad 5640 {
ca61edf2 5641 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5642 i.suffix = LONG_MNEM_SUFFIX;
5643 }
5644 else
5645 {
2b5d6a91 5646 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5647 register_prefix, i.op[op].regs->reg_name,
5648 i.suffix);
5649 return 0;
5650 }
252b5132 5651 }
29b0f896
AM		 5652 return 1;
5653}
252b5132 5654
29b0f896 5655static int
e3bb37b5 5656check_word_reg (void)
29b0f896
AM		 5657{
5658 int op;
5659 for (op = i.operands; --op >= 0;)
5660 /* Reject eight bit registers, except where the template requires
5661 them. (eg. movzb) */
40fb9820
L		 5662 if (i.types[op].bitfield.reg8
5663 && (i.tm.operand_types[op].bitfield.reg16
5664 || i.tm.operand_types[op].bitfield.reg32
5665 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5666 {
a540244d
L		 5667 as_bad (_("`%s%s' not allowed with `%s%c'"),
5668 register_prefix,
29b0f896
AM		 5669 i.op[op].regs->reg_name,
5670 i.tm.name,
5671 i.suffix);
5672 return 0;
5673 }
e4630f71 5674 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5675 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5676 && (i.types[op].bitfield.reg32
5677 || i.types[op].bitfield.reg64)
40fb9820
L		 5678 && (i.tm.operand_types[op].bitfield.reg16
5679 || i.tm.operand_types[op].bitfield.acc))
252b5132 5680 {
29b0f896
AM		 5681 /* Prohibit these changes in the 64bit mode, since the
5682 lowering is more complicated. */
5683 if (flag_code == CODE_64BIT)
252b5132 5684 {
2b5d6a91 5685 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5686 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5687 i.suffix);
5688 return 0;
252b5132 5689 }
29b0f896 5690#if REGISTER_WARNINGS
cecf1424
JB		 5691 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5692 register_prefix,
5693 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5694 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5695#endif
5696 }
5697 return 1;
5698}
252b5132 5699
29b0f896 5700static int
40fb9820 5701update_imm (unsigned int j)
29b0f896 5702{
bc0844ae 5703 i386_operand_type overlap = i.types[j];
40fb9820
L		 5704 if ((overlap.bitfield.imm8
5705 || overlap.bitfield.imm8s
5706 || overlap.bitfield.imm16
5707 || overlap.bitfield.imm32
5708 || overlap.bitfield.imm32s
5709 || overlap.bitfield.imm64)
0dfbf9d7
L		 5710 && !operand_type_equal (&overlap, &imm8)
5711 && !operand_type_equal (&overlap, &imm8s)
5712 && !operand_type_equal (&overlap, &imm16)
5713 && !operand_type_equal (&overlap, &imm32)
5714 && !operand_type_equal (&overlap, &imm32s)
5715 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5716 {
5717 if (i.suffix)
5718 {
40fb9820
L		 5719 i386_operand_type temp;
5720
0dfbf9d7 5721 operand_type_set (&temp, 0);
7ab9ffdd 5722 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5723 {
5724 temp.bitfield.imm8 = overlap.bitfield.imm8;
5725 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5726 }
5727 else if (i.suffix == WORD_MNEM_SUFFIX)
5728 temp.bitfield.imm16 = overlap.bitfield.imm16;
5729 else if (i.suffix == QWORD_MNEM_SUFFIX)
5730 {
5731 temp.bitfield.imm64 = overlap.bitfield.imm64;
5732 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5733 }
5734 else
5735 temp.bitfield.imm32 = overlap.bitfield.imm32;
5736 overlap = temp;
29b0f896 5737 }
0dfbf9d7
L		 5738 else if (operand_type_equal (&overlap, &imm16_32_32s)
5739 || operand_type_equal (&overlap, &imm16_32)
5740 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5741 {
40fb9820 5742 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5743 overlap = imm16;
40fb9820 5744 else
65da13b5 5745 overlap = imm32s;
29b0f896 5746 }
0dfbf9d7
L		 5747 if (!operand_type_equal (&overlap, &imm8)
5748 && !operand_type_equal (&overlap, &imm8s)
5749 && !operand_type_equal (&overlap, &imm16)
5750 && !operand_type_equal (&overlap, &imm32)
5751 && !operand_type_equal (&overlap, &imm32s)
5752 && !operand_type_equal (&overlap, &imm64))
29b0f896 5753 {
4eed87de
AM		 5754 as_bad (_("no instruction mnemonic suffix given; "
5755 "can't determine immediate size"));
29b0f896
AM		 5756 return 0;
5757 }
5758 }
40fb9820 5759 i.types[j] = overlap;
29b0f896 5760
40fb9820
L		 5761 return 1;
5762}
5763
5764static int
5765finalize_imm (void)
5766{
bc0844ae 5767 unsigned int j, n;
29b0f896 5768
bc0844ae
L		 5769 /* Update the first 2 immediate operands. */
5770 n = i.operands > 2 ? 2 : i.operands;
5771 if (n)
5772 {
5773 for (j = 0; j < n; j++)
5774 if (update_imm (j) == 0)
5775 return 0;
40fb9820 5776
bc0844ae
L		 5777 /* The 3rd operand can't be immediate operand. */
5778 gas_assert (operand_type_check (i.types[2], imm) == 0);
5779 }
29b0f896
AM		 5780
5781 return 1;
5782}
5783
c0f3af97
L		 5784static int
5785bad_implicit_operand (int xmm)
5786{
91d6fa6a
NC		 5787 const char *ireg = xmm ? "xmm0" : "ymm0";
5788
c0f3af97
L		 5789 if (intel_syntax)
5790 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5791 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5792 else
5793 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5794 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5795 return 0;
5796}
5797
29b0f896 5798static int
e3bb37b5 5799process_operands (void)
29b0f896
AM		 5800{
5801 /* Default segment register this instruction will use for memory
5802 accesses. 0 means unknown. This is only for optimizing out
5803 unnecessary segment overrides. */
5804 const seg_entry *default_seg = 0;
5805
2426c15f 5806 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5807 {
91d6fa6a
NC		 5808 unsigned int dupl = i.operands;
5809 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5810 unsigned int j;
5811
c0f3af97 5812 /* The destination must be an xmm register. */
9c2799c2 5813 gas_assert (i.reg_operands
91d6fa6a 5814 && MAX_OPERANDS > dupl
7ab9ffdd 5815 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5816
5817 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5818 {
c0f3af97 5819 /* The first operand is implicit and must be xmm0. */
9c2799c2 5820 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5821 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5822 return bad_implicit_operand (1);
5823
8cd7925b 5824 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5825 {
5826 /* Keep xmm0 for instructions with VEX prefix and 3
5827 sources. */
5828 goto duplicate;
5829 }
e2ec9d29 5830 else
c0f3af97
L		 5831 {
5832 /* We remove the first xmm0 and keep the number of
5833 operands unchanged, which in fact duplicates the
5834 destination. */
5835 for (j = 1; j < i.operands; j++)
5836 {
5837 i.op[j - 1] = i.op[j];
5838 i.types[j - 1] = i.types[j];
5839 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5840 }
5841 }
5842 }
5843 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5844 {
91d6fa6a 5845 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5846 && (i.tm.opcode_modifier.vexsources
5847 == VEX3SOURCES));
c0f3af97
L		 5848
5849 /* Add the implicit xmm0 for instructions with VEX prefix
5850 and 3 sources. */
5851 for (j = i.operands; j > 0; j--)
5852 {
5853 i.op[j] = i.op[j - 1];
5854 i.types[j] = i.types[j - 1];
5855 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5856 }
5857 i.op[0].regs
5858 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5859 i.types[0] = regxmm;
c0f3af97
L		 5860 i.tm.operand_types[0] = regxmm;
5861
5862 i.operands += 2;
5863 i.reg_operands += 2;
5864 i.tm.operands += 2;
5865
91d6fa6a 5866 dupl++;
c0f3af97 5867 dest++;
91d6fa6a
NC		 5868 i.op[dupl] = i.op[dest];
5869 i.types[dupl] = i.types[dest];
5870 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5871 }
c0f3af97
L		 5872 else
5873 {
5874duplicate:
5875 i.operands++;
5876 i.reg_operands++;
5877 i.tm.operands++;
5878
91d6fa6a
NC		 5879 i.op[dupl] = i.op[dest];
5880 i.types[dupl] = i.types[dest];
5881 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5882 }
5883
5884 if (i.tm.opcode_modifier.immext)
5885 process_immext ();
5886 }
5887 else if (i.tm.opcode_modifier.firstxmm0)
5888 {
5889 unsigned int j;
5890
43234a1e 5891 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5892 gas_assert (i.reg_operands
7ab9ffdd 5893 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5894 || operand_type_equal (&i.types[0], &regymm)
5895 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5896 if (register_number (i.op[0].regs) != 0)
c0f3af97 5897 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5898
5899 for (j = 1; j < i.operands; j++)
5900 {
5901 i.op[j - 1] = i.op[j];
5902 i.types[j - 1] = i.types[j];
5903
5904 /* We need to adjust fields in i.tm since they are used by
5905 build_modrm_byte. */
5906 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5907 }
5908
e2ec9d29
L		 5909 i.operands--;
5910 i.reg_operands--;
e2ec9d29
L		 5911 i.tm.operands--;
5912 }
5913 else if (i.tm.opcode_modifier.regkludge)
5914 {
5915 /* The imul $imm, %reg instruction is converted into
5916 imul $imm, %reg, %reg, and the clr %reg instruction
5917 is converted into xor %reg, %reg. */
5918
5919 unsigned int first_reg_op;
5920
5921 if (operand_type_check (i.types[0], reg))
5922 first_reg_op = 0;
5923 else
5924 first_reg_op = 1;
5925 /* Pretend we saw the extra register operand. */
9c2799c2 5926 gas_assert (i.reg_operands == 1
7ab9ffdd 5927 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5928 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5929 i.types[first_reg_op + 1] = i.types[first_reg_op];
5930 i.operands++;
5931 i.reg_operands++;
29b0f896
AM		 5932 }
5933
40fb9820 5934 if (i.tm.opcode_modifier.shortform)
29b0f896 5935 {
40fb9820
L		 5936 if (i.types[0].bitfield.sreg2
5937 || i.types[0].bitfield.sreg3)
29b0f896 5938 {
4eed87de
AM		 5939 if (i.tm.base_opcode == POP_SEG_SHORT
5940 && i.op[0].regs->reg_num == 1)
29b0f896 5941 {
a87af027 5942 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5943 return 0;
29b0f896 5944 }
4eed87de
AM		 5945 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5946 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5947 i.rex |= REX_B;
4eed87de
AM		 5948 }
5949 else
5950 {
7ab9ffdd 5951 /* The register or float register operand is in operand
85f10a01 5952 0 or 1. */
40fb9820 5953 unsigned int op;
7ab9ffdd
L		 5954
5955 if (i.types[0].bitfield.floatreg
5956 || operand_type_check (i.types[0], reg))
5957 op = 0;
5958 else
5959 op = 1;
4eed87de
AM		 5960 /* Register goes in low 3 bits of opcode. */
5961 i.tm.base_opcode |= i.op[op].regs->reg_num;
5962 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5963 i.rex |= REX_B;
40fb9820 5964 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5965 {
4eed87de
AM		 5966 /* Warn about some common errors, but press on regardless.
5967 The first case can be generated by gcc (<= 2.8.1). */
5968 if (i.operands == 2)
5969 {
5970 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5971 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5972 register_prefix, i.op[!intel_syntax].regs->reg_name,
5973 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5974 }
5975 else
5976 {
5977 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5978 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5979 register_prefix, i.op[0].regs->reg_name);
4eed87de 5980 }
29b0f896
AM		 5981 }
5982 }
5983 }
40fb9820 5984 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5985 {
5986 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5987 must be put into the modrm byte). Now, we make the modrm and
5988 index base bytes based on all the info we've collected. */
29b0f896
AM		 5989
5990 default_seg = build_modrm_byte ();
5991 }
8a2ed489 5992 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5993 {
5994 default_seg = &ds;
5995 }
40fb9820 5996 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5997 {
5998 /* For the string instructions that allow a segment override
5999 on one of their operands, the default segment is ds. */
6000 default_seg = &ds;
6001 }
6002
75178d9d
L		 6003 if (i.tm.base_opcode == 0x8d /* lea */
6004 && i.seg[0]
6005 && !quiet_warnings)
30123838 6006 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6007
6008 /* If a segment was explicitly specified, and the specified segment
6009 is not the default, use an opcode prefix to select it. If we
6010 never figured out what the default segment is, then default_seg
6011 will be zero at this point, and the specified segment prefix will
6012 always be used. */
29b0f896
AM		 6013 if ((i.seg[0]) && (i.seg[0] != default_seg))
6014 {
6015 if (!add_prefix (i.seg[0]->seg_prefix))
6016 return 0;
6017 }
6018 return 1;
6019}
6020
6021static const seg_entry *
e3bb37b5 6022build_modrm_byte (void)
29b0f896
AM		 6023{
6024 const seg_entry *default_seg = 0;
c0f3af97 6025 unsigned int source, dest;
8cd7925b 6026 int vex_3_sources;
c0f3af97
L		 6027
6028 /* The first operand of instructions with VEX prefix and 3 sources
6029 must be VEX_Imm4. */
8cd7925b 6030 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6031 if (vex_3_sources)
6032 {
91d6fa6a 6033 unsigned int nds, reg_slot;
4c2c6516 6034 expressionS *exp;
c0f3af97 6035
922d8de8 6036 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6037 && i.tm.opcode_modifier.immext)
6038 {
6039 dest = i.operands - 2;
6040 gas_assert (dest == 3);
6041 }
922d8de8 6042 else
a683cc34 6043 dest = i.operands - 1;
c0f3af97 6044 nds = dest - 1;
922d8de8 6045
a683cc34
SP		 6046 /* There are 2 kinds of instructions:
6047 1. 5 operands: 4 register operands or 3 register operands
6048 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6049 VexW0 or VexW1. The destination must be either XMM, YMM or
6050 ZMM register.
a683cc34
SP		 6051 2. 4 operands: 4 register operands or 3 register operands
6052 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6053 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6054 || (i.reg_operands == 3 && i.mem_operands == 1))
6055 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6056 && (i.tm.opcode_modifier.veximmext
6057 || (i.imm_operands == 1
6058 && i.types[0].bitfield.vec_imm4
6059 && (i.tm.opcode_modifier.vexw == VEXW0
6060 || i.tm.opcode_modifier.vexw == VEXW1)
6061 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6062 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6063 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6064
6065 if (i.imm_operands == 0)
6066 {
6067 /* When there is no immediate operand, generate an 8bit
6068 immediate operand to encode the first operand. */
6069 exp = &im_expressions[i.imm_operands++];
6070 i.op[i.operands].imms = exp;
6071 i.types[i.operands] = imm8;
6072 i.operands++;
6073 /* If VexW1 is set, the first operand is the source and
6074 the second operand is encoded in the immediate operand. */
6075 if (i.tm.opcode_modifier.vexw == VEXW1)
6076 {
6077 source = 0;
6078 reg_slot = 1;
6079 }
6080 else
6081 {
6082 source = 1;
6083 reg_slot = 0;
6084 }
6085
6086 /* FMA swaps REG and NDS. */
6087 if (i.tm.cpu_flags.bitfield.cpufma)
6088 {
6089 unsigned int tmp;
6090 tmp = reg_slot;
6091 reg_slot = nds;
6092 nds = tmp;
6093 }
6094
24981e7b
L		 6095 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6096 &regxmm)
a683cc34 6097 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6098 &regymm)
6099 || operand_type_equal (&i.tm.operand_types[reg_slot],
6100 &regzmm));
a683cc34 6101 exp->X_op = O_constant;
4c692bc7 6102 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6103 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6104 }
922d8de8 6105 else
a683cc34
SP		 6106 {
6107 unsigned int imm_slot;
6108
6109 if (i.tm.opcode_modifier.vexw == VEXW0)
6110 {
6111 /* If VexW0 is set, the third operand is the source and
6112 the second operand is encoded in the immediate
6113 operand. */
6114 source = 2;
6115 reg_slot = 1;
6116 }
6117 else
6118 {
6119 /* VexW1 is set, the second operand is the source and
6120 the third operand is encoded in the immediate
6121 operand. */
6122 source = 1;
6123 reg_slot = 2;
6124 }
6125
6126 if (i.tm.opcode_modifier.immext)
6127 {
6128 /* When ImmExt is set, the immdiate byte is the last
6129 operand. */
6130 imm_slot = i.operands - 1;
6131 source--;
6132 reg_slot--;
6133 }
6134 else
6135 {
6136 imm_slot = 0;
6137
6138 /* Turn on Imm8 so that output_imm will generate it. */
6139 i.types[imm_slot].bitfield.imm8 = 1;
6140 }
6141
24981e7b
L		 6142 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6143 &regxmm)
6144 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6145 &regymm)
6146 || operand_type_equal (&i.tm.operand_types[reg_slot],
6147 &regzmm));
a683cc34 6148 i.op[imm_slot].imms->X_add_number
4c692bc7 6149 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6150 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6151 }
6152
6153 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6154 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6155 &regymm)
6156 || operand_type_equal (&i.tm.operand_types[nds],
6157 &regzmm));
dae39acc 6158 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6159 }
6160 else
6161 source = dest = 0;
29b0f896
AM		 6162
6163 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6164 implicit registers do not count. If there are 3 register
6165 operands, it must be a instruction with VexNDS. For a
6166 instruction with VexNDD, the destination register is encoded
6167 in VEX prefix. If there are 4 register operands, it must be
6168 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6169 if (i.mem_operands == 0
6170 && ((i.reg_operands == 2
2426c15f 6171 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6172 || (i.reg_operands == 3
2426c15f 6173 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6174 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6175 {
cab737b9
L		 6176 switch (i.operands)
6177 {
6178 case 2:
6179 source = 0;
6180 break;
6181 case 3:
c81128dc
L		 6182 /* When there are 3 operands, one of them may be immediate,
6183 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6184 the first operand must be shift count register (cl) or it
6185 is an instruction with VexNDS. */
9c2799c2 6186 gas_assert (i.imm_operands == 1
7ab9ffdd 6187 || (i.imm_operands == 0
2426c15f 6188 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6189 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6190 if (operand_type_check (i.types[0], imm)
6191 || i.types[0].bitfield.shiftcount)
6192 source = 1;
6193 else
6194 source = 0;
cab737b9
L		 6195 break;
6196 case 4:
368d64cc
L		 6197 /* When there are 4 operands, the first two must be 8bit
6198 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6199 one.
6200
6201 For instructions with VexNDS, if the first operand
6202 an imm8, the source operand is the 2nd one. If the last
6203 operand is imm8, the source operand is the first one. */
9c2799c2 6204 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6205 && i.types[0].bitfield.imm8
6206 && i.types[1].bitfield.imm8)
2426c15f 6207 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6208 && i.imm_operands == 1
6209 && (i.types[0].bitfield.imm8
43234a1e
L		 6210 || i.types[i.operands - 1].bitfield.imm8
6211 || i.rounding)));
9f2670f2
L		 6212 if (i.imm_operands == 2)
6213 source = 2;
6214 else
c0f3af97
L		 6215 {
6216 if (i.types[0].bitfield.imm8)
6217 source = 1;
6218 else
6219 source = 0;
6220 }
c0f3af97
L		 6221 break;
6222 case 5:
43234a1e
L		 6223 if (i.tm.opcode_modifier.evex)
6224 {
6225 /* For EVEX instructions, when there are 5 operands, the
6226 first one must be immediate operand. If the second one
6227 is immediate operand, the source operand is the 3th
6228 one. If the last one is immediate operand, the source
6229 operand is the 2nd one. */
6230 gas_assert (i.imm_operands == 2
6231 && i.tm.opcode_modifier.sae
6232 && operand_type_check (i.types[0], imm));
6233 if (operand_type_check (i.types[1], imm))
6234 source = 2;
6235 else if (operand_type_check (i.types[4], imm))
6236 source = 1;
6237 else
6238 abort ();
6239 }
cab737b9
L		 6240 break;
6241 default:
6242 abort ();
6243 }
6244
c0f3af97
L		 6245 if (!vex_3_sources)
6246 {
6247 dest = source + 1;
6248
43234a1e
L		 6249 /* RC/SAE operand could be between DEST and SRC. That happens
6250 when one operand is GPR and the other one is XMM/YMM/ZMM
6251 register. */
6252 if (i.rounding && i.rounding->operand == (int) dest)
6253 dest++;
6254
2426c15f 6255 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6256 {
43234a1e
L		 6257 /* For instructions with VexNDS, the register-only source
6258 operand must be 32/64bit integer, XMM, YMM or ZMM
6259 register. It is encoded in VEX prefix. We need to
6260 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6261
6262 i386_operand_type op;
6263 unsigned int vvvv;
6264
6265 /* Check register-only source operand when two source
6266 operands are swapped. */
6267 if (!i.tm.operand_types[source].bitfield.baseindex
6268 && i.tm.operand_types[dest].bitfield.baseindex)
6269 {
6270 vvvv = source;
6271 source = dest;
6272 }
6273 else
6274 vvvv = dest;
6275
6276 op = i.tm.operand_types[vvvv];
fa99fab2 6277 op.bitfield.regmem = 0;
c0f3af97 6278 if ((dest + 1) >= i.operands
ac4eb736
AM		 6279 || (!op.bitfield.reg32
6280 && op.bitfield.reg64
f12dc422 6281 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6282 && !operand_type_equal (&op, &regymm)
6283 && !operand_type_equal (&op, &regzmm)
6284 && !operand_type_equal (&op, &regmask)))
c0f3af97 6285 abort ();
f12dc422 6286 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6287 dest++;
6288 }
6289 }
29b0f896
AM		 6290
6291 i.rm.mode = 3;
6292 /* One of the register operands will be encoded in the i.tm.reg
6293 field, the other in the combined i.tm.mode and i.tm.regmem
6294 fields. If no form of this instruction supports a memory
6295 destination operand, then we assume the source operand may
6296 sometimes be a memory operand and so we need to store the
6297 destination in the i.rm.reg field. */
40fb9820
L		 6298 if (!i.tm.operand_types[dest].bitfield.regmem
6299 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6300 {
6301 i.rm.reg = i.op[dest].regs->reg_num;
6302 i.rm.regmem = i.op[source].regs->reg_num;
6303 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6304 i.rex |= REX_R;
43234a1e
L		 6305 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6306 i.vrex |= REX_R;
29b0f896 6307 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6308 i.rex |= REX_B;
43234a1e
L		 6309 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6310 i.vrex |= REX_B;
29b0f896
AM		 6311 }
6312 else
6313 {
6314 i.rm.reg = i.op[source].regs->reg_num;
6315 i.rm.regmem = i.op[dest].regs->reg_num;
6316 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6317 i.rex |= REX_B;
43234a1e
L		 6318 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6319 i.vrex |= REX_B;
29b0f896 6320 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6321 i.rex |= REX_R;
43234a1e
L		 6322 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6323 i.vrex |= REX_R;
29b0f896 6324 }
161a04f6 6325 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6326 {
40fb9820
L		 6327 if (!i.types[0].bitfield.control
6328 && !i.types[1].bitfield.control)
c4a530c5 6329 abort ();
161a04f6 6330 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6331 add_prefix (LOCK_PREFIX_OPCODE);
6332 }
29b0f896
AM		 6333 }
6334 else
6335 { /* If it's not 2 reg operands... */
c0f3af97
L		 6336 unsigned int mem;
6337
29b0f896
AM		 6338 if (i.mem_operands)
6339 {
6340 unsigned int fake_zero_displacement = 0;
99018f42 6341 unsigned int op;
4eed87de 6342
7ab9ffdd
L		 6343 for (op = 0; op < i.operands; op++)
6344 if (operand_type_check (i.types[op], anymem))
6345 break;
7ab9ffdd 6346 gas_assert (op < i.operands);
29b0f896 6347
6c30d220
L		 6348 if (i.tm.opcode_modifier.vecsib)
6349 {
6350 if (i.index_reg->reg_num == RegEiz
6351 || i.index_reg->reg_num == RegRiz)
6352 abort ();
6353
6354 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6355 if (!i.base_reg)
6356 {
6357 i.sib.base = NO_BASE_REGISTER;
6358 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6359 /* No Vec_Disp8 if there is no base. */
6360 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6361 i.types[op].bitfield.disp8 = 0;
6362 i.types[op].bitfield.disp16 = 0;
6363 i.types[op].bitfield.disp64 = 0;
6364 if (flag_code != CODE_64BIT)
6365 {
6366 /* Must be 32 bit */
6367 i.types[op].bitfield.disp32 = 1;
6368 i.types[op].bitfield.disp32s = 0;
6369 }
6370 else
6371 {
6372 i.types[op].bitfield.disp32 = 0;
6373 i.types[op].bitfield.disp32s = 1;
6374 }
6375 }
6376 i.sib.index = i.index_reg->reg_num;
6377 if ((i.index_reg->reg_flags & RegRex) != 0)
6378 i.rex |= REX_X;
43234a1e
L		 6379 if ((i.index_reg->reg_flags & RegVRex) != 0)
6380 i.vrex |= REX_X;
6c30d220
L		 6381 }
6382
29b0f896
AM		 6383 default_seg = &ds;
6384
6385 if (i.base_reg == 0)
6386 {
6387 i.rm.mode = 0;
6388 if (!i.disp_operands)
6c30d220
L		 6389 {
6390 fake_zero_displacement = 1;
6391 /* Instructions with VSIB byte need 32bit displacement
6392 if there is no base register. */
6393 if (i.tm.opcode_modifier.vecsib)
6394 i.types[op].bitfield.disp32 = 1;
6395 }
29b0f896
AM		 6396 if (i.index_reg == 0)
6397 {
6c30d220 6398 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6399 /* Operand is just <disp> */
20f0a1fc 6400 if (flag_code == CODE_64BIT)
29b0f896
AM		 6401 {
6402 /* 64bit mode overwrites the 32bit absolute
6403 addressing by RIP relative addressing and
6404 absolute addressing is encoded by one of the
6405 redundant SIB forms. */
6406 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6407 i.sib.base = NO_BASE_REGISTER;
6408 i.sib.index = NO_INDEX_REGISTER;
fc225355 6409 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6410 ? disp32s : disp32);
20f0a1fc 6411 }
fc225355
L		 6412 else if ((flag_code == CODE_16BIT)
6413 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6414 {
6415 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6416 i.types[op] = disp16;
20f0a1fc
NC		 6417 }
6418 else
6419 {
6420 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6421 i.types[op] = disp32;
29b0f896
AM		 6422 }
6423 }
6c30d220 6424 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6425 {
6c30d220 6426 /* !i.base_reg && i.index_reg */
db51cc60
L		 6427 if (i.index_reg->reg_num == RegEiz
6428 || i.index_reg->reg_num == RegRiz)
6429 i.sib.index = NO_INDEX_REGISTER;
6430 else
6431 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6432 i.sib.base = NO_BASE_REGISTER;
6433 i.sib.scale = i.log2_scale_factor;
6434 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6435 /* No Vec_Disp8 if there is no base. */
6436 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6437 i.types[op].bitfield.disp8 = 0;
6438 i.types[op].bitfield.disp16 = 0;
6439 i.types[op].bitfield.disp64 = 0;
29b0f896 6440 if (flag_code != CODE_64BIT)
40fb9820
L		 6441 {
6442 /* Must be 32 bit */
6443 i.types[op].bitfield.disp32 = 1;
6444 i.types[op].bitfield.disp32s = 0;
6445 }
29b0f896 6446 else
40fb9820
L		 6447 {
6448 i.types[op].bitfield.disp32 = 0;
6449 i.types[op].bitfield.disp32s = 1;
6450 }
29b0f896 6451 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6452 i.rex |= REX_X;
29b0f896
AM		 6453 }
6454 }
6455 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6456 else if (i.base_reg->reg_num == RegRip ||
6457 i.base_reg->reg_num == RegEip)
29b0f896 6458 {
6c30d220 6459 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6460 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6461 i.types[op].bitfield.disp8 = 0;
6462 i.types[op].bitfield.disp16 = 0;
6463 i.types[op].bitfield.disp32 = 0;
6464 i.types[op].bitfield.disp32s = 1;
6465 i.types[op].bitfield.disp64 = 0;
43234a1e 6466 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6467 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6468 if (! i.disp_operands)
6469 fake_zero_displacement = 1;
29b0f896 6470 }
40fb9820 6471 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6472 {
6c30d220 6473 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6474 switch (i.base_reg->reg_num)
6475 {
6476 case 3: /* (%bx) */
6477 if (i.index_reg == 0)
6478 i.rm.regmem = 7;
6479 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6480 i.rm.regmem = i.index_reg->reg_num - 6;
6481 break;
6482 case 5: /* (%bp) */
6483 default_seg = &ss;
6484 if (i.index_reg == 0)
6485 {
6486 i.rm.regmem = 6;
40fb9820 6487 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6488 {
6489 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6490 if (i.tm.operand_types[op].bitfield.vec_disp8)
6491 i.types[op].bitfield.vec_disp8 = 1;
6492 else
6493 i.types[op].bitfield.disp8 = 1;
252b5132 6494 fake_zero_displacement = 1;
29b0f896
AM		 6495 }
6496 }
6497 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6498 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6499 break;
6500 default: /* (%si) -> 4 or (%di) -> 5 */
6501 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6502 }
6503 i.rm.mode = mode_from_disp_size (i.types[op]);
6504 }
6505 else /* i.base_reg and 32/64 bit mode */
6506 {
6507 if (flag_code == CODE_64BIT
40fb9820
L		 6508 && operand_type_check (i.types[op], disp))
6509 {
6510 i386_operand_type temp;
0dfbf9d7 6511 operand_type_set (&temp, 0);
40fb9820 6512 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6513 temp.bitfield.vec_disp8
6514 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6515 i.types[op] = temp;
6516 if (i.prefix[ADDR_PREFIX] == 0)
6517 i.types[op].bitfield.disp32s = 1;
6518 else
6519 i.types[op].bitfield.disp32 = 1;
6520 }
20f0a1fc 6521
6c30d220
L		 6522 if (!i.tm.opcode_modifier.vecsib)
6523 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6524 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6525 i.rex |= REX_B;
29b0f896
AM		 6526 i.sib.base = i.base_reg->reg_num;
6527 /* x86-64 ignores REX prefix bit here to avoid decoder
6528 complications. */
848930b2
JB		 6529 if (!(i.base_reg->reg_flags & RegRex)
6530 && (i.base_reg->reg_num == EBP_REG_NUM
6531 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6532 default_seg = &ss;
848930b2 6533 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6534 {
848930b2 6535 fake_zero_displacement = 1;
43234a1e
L		 6536 if (i.tm.operand_types [op].bitfield.vec_disp8)
6537 i.types[op].bitfield.vec_disp8 = 1;
6538 else
6539 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6540 }
6541 i.sib.scale = i.log2_scale_factor;
6542 if (i.index_reg == 0)
6543 {
6c30d220 6544 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6545 /* <disp>(%esp) becomes two byte modrm with no index
6546 register. We've already stored the code for esp
6547 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6548 Any base register besides %esp will not use the
6549 extra modrm byte. */
6550 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6551 }
6c30d220 6552 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6553 {
db51cc60
L		 6554 if (i.index_reg->reg_num == RegEiz
6555 || i.index_reg->reg_num == RegRiz)
6556 i.sib.index = NO_INDEX_REGISTER;
6557 else
6558 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6559 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6560 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6561 i.rex |= REX_X;
29b0f896 6562 }
67a4f2b7
AO		 6563
6564 if (i.disp_operands
6565 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6566 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6567 i.rm.mode = 0;
6568 else
a501d77e
L		 6569 {
6570 if (!fake_zero_displacement
6571 && !i.disp_operands
6572 && i.disp_encoding)
6573 {
6574 fake_zero_displacement = 1;
6575 if (i.disp_encoding == disp_encoding_8bit)
6576 i.types[op].bitfield.disp8 = 1;
6577 else
6578 i.types[op].bitfield.disp32 = 1;
6579 }
6580 i.rm.mode = mode_from_disp_size (i.types[op]);
6581 }
29b0f896 6582 }
252b5132 6583
29b0f896
AM		 6584 if (fake_zero_displacement)
6585 {
6586 /* Fakes a zero displacement assuming that i.types[op]
6587 holds the correct displacement size. */
6588 expressionS *exp;
6589
9c2799c2 6590 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6591 exp = &disp_expressions[i.disp_operands++];
6592 i.op[op].disps = exp;
6593 exp->X_op = O_constant;
6594 exp->X_add_number = 0;
6595 exp->X_add_symbol = (symbolS *) 0;
6596 exp->X_op_symbol = (symbolS *) 0;
6597 }
c0f3af97
L		 6598
6599 mem = op;
29b0f896 6600 }
c0f3af97
L		 6601 else
6602 mem = ~0;
252b5132 6603
8c43a48b 6604 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6605 {
6606 if (operand_type_check (i.types[0], imm))
6607 i.vex.register_specifier = NULL;
6608 else
6609 {
6610 /* VEX.vvvv encodes one of the sources when the first
6611 operand is not an immediate. */
1ef99a7b 6612 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6613 i.vex.register_specifier = i.op[0].regs;
6614 else
6615 i.vex.register_specifier = i.op[1].regs;
6616 }
6617
6618 /* Destination is a XMM register encoded in the ModRM.reg
6619 and VEX.R bit. */
6620 i.rm.reg = i.op[2].regs->reg_num;
6621 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6622 i.rex |= REX_R;
6623
6624 /* ModRM.rm and VEX.B encodes the other source. */
6625 if (!i.mem_operands)
6626 {
6627 i.rm.mode = 3;
6628
1ef99a7b 6629 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6630 i.rm.regmem = i.op[1].regs->reg_num;
6631 else
6632 i.rm.regmem = i.op[0].regs->reg_num;
6633
6634 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6635 i.rex |= REX_B;
6636 }
6637 }
2426c15f 6638 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6639 {
6640 i.vex.register_specifier = i.op[2].regs;
6641 if (!i.mem_operands)
6642 {
6643 i.rm.mode = 3;
6644 i.rm.regmem = i.op[1].regs->reg_num;
6645 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6646 i.rex |= REX_B;
6647 }
6648 }
29b0f896
AM		 6649 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6650 (if any) based on i.tm.extension_opcode. Again, we must be
6651 careful to make sure that segment/control/debug/test/MMX
6652 registers are coded into the i.rm.reg field. */
f88c9eb0 6653 else if (i.reg_operands)
29b0f896 6654 {
99018f42 6655 unsigned int op;
7ab9ffdd
L		 6656 unsigned int vex_reg = ~0;
6657
6658 for (op = 0; op < i.operands; op++)
6659 if (i.types[op].bitfield.reg8
6660 || i.types[op].bitfield.reg16
6661 || i.types[op].bitfield.reg32
6662 || i.types[op].bitfield.reg64
6663 || i.types[op].bitfield.regmmx
6664 || i.types[op].bitfield.regxmm
6665 || i.types[op].bitfield.regymm
7e8b059b 6666 || i.types[op].bitfield.regbnd
43234a1e
L		 6667 || i.types[op].bitfield.regzmm
6668 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6669 || i.types[op].bitfield.sreg2
6670 || i.types[op].bitfield.sreg3
6671 || i.types[op].bitfield.control
6672 || i.types[op].bitfield.debug
6673 || i.types[op].bitfield.test)
6674 break;
c0209578 6675
7ab9ffdd
L		 6676 if (vex_3_sources)
6677 op = dest;
2426c15f 6678 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6679 {
6680 /* For instructions with VexNDS, the register-only
6681 source operand is encoded in VEX prefix. */
6682 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6683
7ab9ffdd 6684 if (op > mem)
c0f3af97 6685 {
7ab9ffdd
L		 6686 vex_reg = op++;
6687 gas_assert (op < i.operands);
c0f3af97
L		 6688 }
6689 else
c0f3af97 6690 {
f12dc422
L		 6691 /* Check register-only source operand when two source
6692 operands are swapped. */
6693 if (!i.tm.operand_types[op].bitfield.baseindex
6694 && i.tm.operand_types[op + 1].bitfield.baseindex)
6695 {
6696 vex_reg = op;
6697 op += 2;
6698 gas_assert (mem == (vex_reg + 1)
6699 && op < i.operands);
6700 }
6701 else
6702 {
6703 vex_reg = op + 1;
6704 gas_assert (vex_reg < i.operands);
6705 }
c0f3af97 6706 }
7ab9ffdd 6707 }
2426c15f 6708 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6709 {
f12dc422 6710 /* For instructions with VexNDD, the register destination
7ab9ffdd 6711 is encoded in VEX prefix. */
f12dc422
L		 6712 if (i.mem_operands == 0)
6713 {
6714 /* There is no memory operand. */
6715 gas_assert ((op + 2) == i.operands);
6716 vex_reg = op + 1;
6717 }
6718 else
8d63c93e 6719 {
f12dc422
L		 6720 /* There are only 2 operands. */
6721 gas_assert (op < 2 && i.operands == 2);
6722 vex_reg = 1;
6723 }
7ab9ffdd
L		 6724 }
6725 else
6726 gas_assert (op < i.operands);
99018f42 6727
7ab9ffdd
L		 6728 if (vex_reg != (unsigned int) ~0)
6729 {
f12dc422 6730 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6731
f12dc422
L		 6732 if (type->bitfield.reg32 != 1
6733 && type->bitfield.reg64 != 1
6734 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6735 && !operand_type_equal (type, &regymm)
6736 && !operand_type_equal (type, &regzmm)
6737 && !operand_type_equal (type, &regmask))
7ab9ffdd 6738 abort ();
f88c9eb0 6739
7ab9ffdd
L		 6740 i.vex.register_specifier = i.op[vex_reg].regs;
6741 }
6742
1b9f0c97
L		 6743 /* Don't set OP operand twice. */
6744 if (vex_reg != op)
7ab9ffdd 6745 {
1b9f0c97
L		 6746 /* If there is an extension opcode to put here, the
6747 register number must be put into the regmem field. */
6748 if (i.tm.extension_opcode != None)
6749 {
6750 i.rm.regmem = i.op[op].regs->reg_num;
6751 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6752 i.rex |= REX_B;
43234a1e
L		 6753 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6754 i.vrex |= REX_B;
1b9f0c97
L		 6755 }
6756 else
6757 {
6758 i.rm.reg = i.op[op].regs->reg_num;
6759 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6760 i.rex |= REX_R;
43234a1e
L		 6761 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6762 i.vrex |= REX_R;
1b9f0c97 6763 }
7ab9ffdd 6764 }
252b5132 6765
29b0f896
AM		 6766 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6767 must set it to 3 to indicate this is a register operand
6768 in the regmem field. */
6769 if (!i.mem_operands)
6770 i.rm.mode = 3;
6771 }
252b5132 6772
29b0f896 6773 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6774 if (i.tm.extension_opcode != None)
29b0f896
AM		 6775 i.rm.reg = i.tm.extension_opcode;
6776 }
6777 return default_seg;
6778}
252b5132 6779
29b0f896 6780static void
e3bb37b5 6781output_branch (void)
29b0f896
AM		 6782{
6783 char *p;
f8a5c266 6784 int size;
29b0f896
AM		 6785 int code16;
6786 int prefix;
6787 relax_substateT subtype;
6788 symbolS *sym;
6789 offsetT off;
6790
f8a5c266 6791 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6792 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6793
6794 prefix = 0;
6795 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6796 {
29b0f896
AM		 6797 prefix = 1;
6798 i.prefixes -= 1;
6799 code16 ^= CODE16;
252b5132 6800 }
29b0f896
AM		 6801 /* Pentium4 branch hints. */
6802 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6803 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6804 {
29b0f896
AM		 6805 prefix++;
6806 i.prefixes--;
6807 }
6808 if (i.prefix[REX_PREFIX] != 0)
6809 {
6810 prefix++;
6811 i.prefixes--;
2f66722d
AM		 6812 }
6813
7e8b059b
L		 6814 /* BND prefixed jump. */
6815 if (i.prefix[BND_PREFIX] != 0)
6816 {
6817 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6818 i.prefixes -= 1;
6819 }
6820
29b0f896
AM		 6821 if (i.prefixes != 0 && !intel_syntax)
6822 as_warn (_("skipping prefixes on this instruction"));
6823
6824 /* It's always a symbol; End frag & setup for relax.
6825 Make sure there is enough room in this frag for the largest
6826 instruction we may generate in md_convert_frag. This is 2
6827 bytes for the opcode and room for the prefix and largest
6828 displacement. */
6829 frag_grow (prefix + 2 + 4);
6830 /* Prefix and 1 opcode byte go in fr_fix. */
6831 p = frag_more (prefix + 1);
6832 if (i.prefix[DATA_PREFIX] != 0)
6833 *p++ = DATA_PREFIX_OPCODE;
6834 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6835 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6836 *p++ = i.prefix[SEG_PREFIX];
6837 if (i.prefix[REX_PREFIX] != 0)
6838 *p++ = i.prefix[REX_PREFIX];
6839 *p = i.tm.base_opcode;
6840
6841 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6842 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6843 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6844 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6845 else
f8a5c266 6846 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6847 subtype |= code16;
3e73aa7c 6848
29b0f896
AM		 6849 sym = i.op[0].disps->X_add_symbol;
6850 off = i.op[0].disps->X_add_number;
3e73aa7c 6851
29b0f896
AM		 6852 if (i.op[0].disps->X_op != O_constant
6853 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6854 {
29b0f896
AM		 6855 /* Handle complex expressions. */
6856 sym = make_expr_symbol (i.op[0].disps);
6857 off = 0;
6858 }
3e73aa7c 6859
29b0f896
AM		 6860 /* 1 possible extra opcode + 4 byte displacement go in var part.
6861 Pass reloc in fr_var. */
d258b828 6862 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6863}
3e73aa7c 6864
29b0f896 6865static void
e3bb37b5 6866output_jump (void)
29b0f896
AM		 6867{
6868 char *p;
6869 int size;
3e02c1cc 6870 fixS *fixP;
29b0f896 6871
40fb9820 6872 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6873 {
6874 /* This is a loop or jecxz type instruction. */
6875 size = 1;
6876 if (i.prefix[ADDR_PREFIX] != 0)
6877 {
6878 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6879 i.prefixes -= 1;
6880 }
6881 /* Pentium4 branch hints. */
6882 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6883 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6884 {
6885 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6886 i.prefixes--;
3e73aa7c
JH		 6887 }
6888 }
29b0f896
AM		 6889 else
6890 {
6891 int code16;
3e73aa7c 6892
29b0f896
AM		 6893 code16 = 0;
6894 if (flag_code == CODE_16BIT)
6895 code16 = CODE16;
3e73aa7c 6896
29b0f896
AM		 6897 if (i.prefix[DATA_PREFIX] != 0)
6898 {
6899 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6900 i.prefixes -= 1;
6901 code16 ^= CODE16;
6902 }
252b5132 6903
29b0f896
AM		 6904 size = 4;
6905 if (code16)
6906 size = 2;
6907 }
9fcc94b6 6908
29b0f896
AM		 6909 if (i.prefix[REX_PREFIX] != 0)
6910 {
6911 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6912 i.prefixes -= 1;
6913 }
252b5132 6914
7e8b059b
L		 6915 /* BND prefixed jump. */
6916 if (i.prefix[BND_PREFIX] != 0)
6917 {
6918 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6919 i.prefixes -= 1;
6920 }
6921
29b0f896
AM		 6922 if (i.prefixes != 0 && !intel_syntax)
6923 as_warn (_("skipping prefixes on this instruction"));
e0890092 6924
42164a71
L		 6925 p = frag_more (i.tm.opcode_length + size);
6926 switch (i.tm.opcode_length)
6927 {
6928 case 2:
6929 *p++ = i.tm.base_opcode >> 8;
6930 case 1:
6931 *p++ = i.tm.base_opcode;
6932 break;
6933 default:
6934 abort ();
6935 }
e0890092 6936
3e02c1cc 6937 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6938 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6939
6940 /* All jumps handled here are signed, but don't use a signed limit
6941 check for 32 and 16 bit jumps as we want to allow wrap around at
6942 4G and 64k respectively. */
6943 if (size == 1)
6944 fixP->fx_signed = 1;
29b0f896 6945}
e0890092 6946
29b0f896 6947static void
e3bb37b5 6948output_interseg_jump (void)
29b0f896
AM		 6949{
6950 char *p;
6951 int size;
6952 int prefix;
6953 int code16;
252b5132 6954
29b0f896
AM		 6955 code16 = 0;
6956 if (flag_code == CODE_16BIT)
6957 code16 = CODE16;
a217f122 6958
29b0f896
AM		 6959 prefix = 0;
6960 if (i.prefix[DATA_PREFIX] != 0)
6961 {
6962 prefix = 1;
6963 i.prefixes -= 1;
6964 code16 ^= CODE16;
6965 }
6966 if (i.prefix[REX_PREFIX] != 0)
6967 {
6968 prefix++;
6969 i.prefixes -= 1;
6970 }
252b5132 6971
29b0f896
AM		 6972 size = 4;
6973 if (code16)
6974 size = 2;
252b5132 6975
29b0f896
AM		 6976 if (i.prefixes != 0 && !intel_syntax)
6977 as_warn (_("skipping prefixes on this instruction"));
252b5132 6978
29b0f896
AM		 6979 /* 1 opcode; 2 segment; offset */
6980 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6981
29b0f896
AM		 6982 if (i.prefix[DATA_PREFIX] != 0)
6983 *p++ = DATA_PREFIX_OPCODE;
252b5132 6984
29b0f896
AM		 6985 if (i.prefix[REX_PREFIX] != 0)
6986 *p++ = i.prefix[REX_PREFIX];
252b5132 6987
29b0f896
AM		 6988 *p++ = i.tm.base_opcode;
6989 if (i.op[1].imms->X_op == O_constant)
6990 {
6991 offsetT n = i.op[1].imms->X_add_number;
252b5132 6992
29b0f896
AM		 6993 if (size == 2
6994 && !fits_in_unsigned_word (n)
6995 && !fits_in_signed_word (n))
6996 {
6997 as_bad (_("16-bit jump out of range"));
6998 return;
6999 }
7000 md_number_to_chars (p, n, size);
7001 }
7002 else
7003 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7004 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7005 if (i.op[0].imms->X_op != O_constant)
7006 as_bad (_("can't handle non absolute segment in `%s'"),
7007 i.tm.name);
7008 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7009}
a217f122 7010
29b0f896 7011static void
e3bb37b5 7012output_insn (void)
29b0f896 7013{
2bbd9c25
JJ		 7014 fragS *insn_start_frag;
7015 offsetT insn_start_off;
7016
29b0f896
AM		 7017 /* Tie dwarf2 debug info to the address at the start of the insn.
7018 We can't do this after the insn has been output as the current
7019 frag may have been closed off. eg. by frag_var. */
7020 dwarf2_emit_insn (0);
7021
2bbd9c25
JJ		 7022 insn_start_frag = frag_now;
7023 insn_start_off = frag_now_fix ();
7024
29b0f896 7025 /* Output jumps. */
40fb9820 7026 if (i.tm.opcode_modifier.jump)
29b0f896 7027 output_branch ();
40fb9820
L		 7028 else if (i.tm.opcode_modifier.jumpbyte
7029 || i.tm.opcode_modifier.jumpdword)
29b0f896 7030 output_jump ();
40fb9820 7031 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7032 output_interseg_jump ();
7033 else
7034 {
7035 /* Output normal instructions here. */
7036 char *p;
7037 unsigned char *q;
47465058 7038 unsigned int j;
331d2d0d 7039 unsigned int prefix;
4dffcebc 7040
e4e00185
AS		 7041 if (avoid_fence
7042 && i.tm.base_opcode == 0xfae
7043 && i.operands == 1
7044 && i.imm_operands == 1
7045 && (i.op[0].imms->X_add_number == 0xe8
7046 || i.op[0].imms->X_add_number == 0xf0
7047 || i.op[0].imms->X_add_number == 0xf8))
7048 {
7049 /* Encode lfence, mfence, and sfence as
7050 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7051 offsetT val = 0x240483f0ULL;
7052 p = frag_more (5);
7053 md_number_to_chars (p, val, 5);
7054 return;
7055 }
7056
d022bddd
IT		 7057 /* Some processors fail on LOCK prefix. This options makes
7058 assembler ignore LOCK prefix and serves as a workaround. */
7059 if (omit_lock_prefix)
7060 {
7061 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7062 return;
7063 i.prefix[LOCK_PREFIX] = 0;
7064 }
7065
43234a1e
L		 7066 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7067 don't need the explicit prefix. */
7068 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7069 {
c0f3af97 7070 switch (i.tm.opcode_length)
bc4bd9ab 7071 {
c0f3af97
L		 7072 case 3:
7073 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7074 {
c0f3af97
L		 7075 prefix = (i.tm.base_opcode >> 24) & 0xff;
7076 goto check_prefix;
7077 }
7078 break;
7079 case 2:
7080 if ((i.tm.base_opcode & 0xff0000) != 0)
7081 {
7082 prefix = (i.tm.base_opcode >> 16) & 0xff;
7083 if (i.tm.cpu_flags.bitfield.cpupadlock)
7084 {
4dffcebc 7085check_prefix:
c0f3af97 7086 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7087 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7088 != REPE_PREFIX_OPCODE))
7089 add_prefix (prefix);
7090 }
7091 else
4dffcebc
L		 7092 add_prefix (prefix);
7093 }
c0f3af97
L		 7094 break;
7095 case 1:
7096 break;
7097 default:
7098 abort ();
bc4bd9ab 7099 }
c0f3af97 7100
6d19a37a 7101#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7102 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7103 R_X86_64_GOTTPOFF relocation so that linker can safely
7104 perform IE->LE optimization. */
7105 if (x86_elf_abi == X86_64_X32_ABI
7106 && i.operands == 2
7107 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7108 && i.prefix[REX_PREFIX] == 0)
7109 add_prefix (REX_OPCODE);
6d19a37a 7110#endif
cf61b747 7111
c0f3af97
L		 7112 /* The prefix bytes. */
7113 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7114 if (*q)
7115 FRAG_APPEND_1_CHAR (*q);
0f10071e 7116 }
ae5c1c7b 7117 else
c0f3af97
L		 7118 {
7119 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7120 if (*q)
7121 switch (j)
7122 {
7123 case REX_PREFIX:
7124 /* REX byte is encoded in VEX prefix. */
7125 break;
7126 case SEG_PREFIX:
7127 case ADDR_PREFIX:
7128 FRAG_APPEND_1_CHAR (*q);
7129 break;
7130 default:
7131 /* There should be no other prefixes for instructions
7132 with VEX prefix. */
7133 abort ();
7134 }
7135
43234a1e
L		 7136 /* For EVEX instructions i.vrex should become 0 after
7137 build_evex_prefix. For VEX instructions upper 16 registers
7138 aren't available, so VREX should be 0. */
7139 if (i.vrex)
7140 abort ();
c0f3af97
L		 7141 /* Now the VEX prefix. */
7142 p = frag_more (i.vex.length);
7143 for (j = 0; j < i.vex.length; j++)
7144 p[j] = i.vex.bytes[j];
7145 }
252b5132 7146
29b0f896 7147 /* Now the opcode; be careful about word order here! */
4dffcebc 7148 if (i.tm.opcode_length == 1)
29b0f896
AM		 7149 {
7150 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7151 }
7152 else
7153 {
4dffcebc 7154 switch (i.tm.opcode_length)
331d2d0d 7155 {
43234a1e
L		 7156 case 4:
7157 p = frag_more (4);
7158 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7159 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7160 break;
4dffcebc 7161 case 3:
331d2d0d
L		 7162 p = frag_more (3);
7163 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7164 break;
7165 case 2:
7166 p = frag_more (2);
7167 break;
7168 default:
7169 abort ();
7170 break;
331d2d0d 7171 }
0f10071e 7172
29b0f896
AM		 7173 /* Put out high byte first: can't use md_number_to_chars! */
7174 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7175 *p = i.tm.base_opcode & 0xff;
7176 }
3e73aa7c 7177
29b0f896 7178 /* Now the modrm byte and sib byte (if present). */
40fb9820 7179 if (i.tm.opcode_modifier.modrm)
29b0f896 7180 {
4a3523fa
L		 7181 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7182 | i.rm.reg << 3
7183 | i.rm.mode << 6));
29b0f896
AM		 7184 /* If i.rm.regmem == ESP (4)
7185 && i.rm.mode != (Register mode)
7186 && not 16 bit
7187 ==> need second modrm byte. */
7188 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7189 && i.rm.mode != 3
40fb9820 7190 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7191 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7192 | i.sib.index << 3
7193 | i.sib.scale << 6));
29b0f896 7194 }
3e73aa7c 7195
29b0f896 7196 if (i.disp_operands)
2bbd9c25 7197 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7198
29b0f896 7199 if (i.imm_operands)
2bbd9c25 7200 output_imm (insn_start_frag, insn_start_off);
29b0f896 7201 }
252b5132 7202
29b0f896
AM		 7203#ifdef DEBUG386
7204 if (flag_debug)
7205 {
7b81dfbb 7206 pi ("" /*line*/, &i);
29b0f896
AM		 7207 }
7208#endif /* DEBUG386 */
7209}
252b5132 7210
e205caa7
L		 7211/* Return the size of the displacement operand N. */
7212
7213static int
7214disp_size (unsigned int n)
7215{
7216 int size = 4;
43234a1e
L		 7217
7218 /* Vec_Disp8 has to be 8bit. */
7219 if (i.types[n].bitfield.vec_disp8)
7220 size = 1;
7221 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7222 size = 8;
7223 else if (i.types[n].bitfield.disp8)
7224 size = 1;
7225 else if (i.types[n].bitfield.disp16)
7226 size = 2;
e205caa7
L		 7227 return size;
7228}
7229
7230/* Return the size of the immediate operand N. */
7231
7232static int
7233imm_size (unsigned int n)
7234{
7235 int size = 4;
40fb9820
L		 7236 if (i.types[n].bitfield.imm64)
7237 size = 8;
7238 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7239 size = 1;
7240 else if (i.types[n].bitfield.imm16)
7241 size = 2;
e205caa7
L		 7242 return size;
7243}
7244
29b0f896 7245static void
64e74474 7246output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7247{
7248 char *p;
7249 unsigned int n;
252b5132 7250
29b0f896
AM		 7251 for (n = 0; n < i.operands; n++)
7252 {
43234a1e
L		 7253 if (i.types[n].bitfield.vec_disp8
7254 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7255 {
7256 if (i.op[n].disps->X_op == O_constant)
7257 {
e205caa7 7258 int size = disp_size (n);
43234a1e 7259 offsetT val = i.op[n].disps->X_add_number;
252b5132 7260
43234a1e
L		 7261 if (i.types[n].bitfield.vec_disp8)
7262 val >>= i.memshift;
7263 val = offset_in_range (val, size);
29b0f896
AM		 7264 p = frag_more (size);
7265 md_number_to_chars (p, val, size);
7266 }
7267 else
7268 {
f86103b7 7269 enum bfd_reloc_code_real reloc_type;
e205caa7 7270 int size = disp_size (n);
40fb9820 7271 int sign = i.types[n].bitfield.disp32s;
29b0f896 7272 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7273 fixS *fixP;
29b0f896 7274
e205caa7 7275 /* We can't have 8 bit displacement here. */
9c2799c2 7276 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7277
29b0f896
AM		 7278 /* The PC relative address is computed relative
7279 to the instruction boundary, so in case immediate
7280 fields follows, we need to adjust the value. */
7281 if (pcrel && i.imm_operands)
7282 {
29b0f896 7283 unsigned int n1;
e205caa7 7284 int sz = 0;
252b5132 7285
29b0f896 7286 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7287 if (operand_type_check (i.types[n1], imm))
252b5132 7288 {
e205caa7
L		 7289 /* Only one immediate is allowed for PC
7290 relative address. */
9c2799c2 7291 gas_assert (sz == 0);
e205caa7
L		 7292 sz = imm_size (n1);
7293 i.op[n].disps->X_add_number -= sz;
252b5132 7294 }
29b0f896 7295 /* We should find the immediate. */
9c2799c2 7296 gas_assert (sz != 0);
29b0f896 7297 }
520dc8e8 7298
29b0f896 7299 p = frag_more (size);
d258b828 7300 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7301 if (GOT_symbol
2bbd9c25 7302 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7303 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7304 || reloc_type == BFD_RELOC_X86_64_32S
7305 || (reloc_type == BFD_RELOC_64
7306 && object_64bit))
d6ab8113
JB		 7307 && (i.op[n].disps->X_op == O_symbol
7308 || (i.op[n].disps->X_op == O_add
7309 && ((symbol_get_value_expression
7310 (i.op[n].disps->X_op_symbol)->X_op)
7311 == O_subtract))))
7312 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7313 {
7314 offsetT add;
7315
7316 if (insn_start_frag == frag_now)
7317 add = (p - frag_now->fr_literal) - insn_start_off;
7318 else
7319 {
7320 fragS *fr;
7321
7322 add = insn_start_frag->fr_fix - insn_start_off;
7323 for (fr = insn_start_frag->fr_next;
7324 fr && fr != frag_now; fr = fr->fr_next)
7325 add += fr->fr_fix;
7326 add += p - frag_now->fr_literal;
7327 }
7328
4fa24527 7329 if (!object_64bit)
7b81dfbb
AJ		 7330 {
7331 reloc_type = BFD_RELOC_386_GOTPC;
7332 i.op[n].imms->X_add_number += add;
7333 }
7334 else if (reloc_type == BFD_RELOC_64)
7335 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7336 else
7b81dfbb
AJ		 7337 /* Don't do the adjustment for x86-64, as there
7338 the pcrel addressing is relative to the _next_
7339 insn, and that is taken care of in other code. */
d6ab8113 7340 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7341 }
02a86693
L		 7342 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7343 size, i.op[n].disps, pcrel,
7344 reloc_type);
7345 /* Check for "call/jmp *mem", "mov mem, %reg",
7346 "test %reg, mem" and "binop mem, %reg" where binop
7347 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7348 instructions. Always generate R_386_GOT32X for
7349 "sym*GOT" operand in 32-bit mode. */
7350 if ((generate_relax_relocations
7351 || (!object_64bit
7352 && i.rm.mode == 0
7353 && i.rm.regmem == 5))
7354 && (i.rm.mode == 2
7355 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7356 && ((i.operands == 1
7357 && i.tm.base_opcode == 0xff
7358 && (i.rm.reg == 2 || i.rm.reg == 4))
7359 || (i.operands == 2
7360 && (i.tm.base_opcode == 0x8b
7361 || i.tm.base_opcode == 0x85
7362 || (i.tm.base_opcode & 0xc7) == 0x03))))
7363 {
7364 if (object_64bit)
7365 {
7366 fixP->fx_tcbit = i.rex != 0;
7367 if (i.base_reg
7368 && (i.base_reg->reg_num == RegRip
7369 || i.base_reg->reg_num == RegEip))
7370 fixP->fx_tcbit2 = 1;
7371 }
7372 else
7373 fixP->fx_tcbit2 = 1;
7374 }
29b0f896
AM		 7375 }
7376 }
7377 }
7378}
252b5132 7379
29b0f896 7380static void
64e74474 7381output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7382{
7383 char *p;
7384 unsigned int n;
252b5132 7385
29b0f896
AM		 7386 for (n = 0; n < i.operands; n++)
7387 {
43234a1e
L		 7388 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7389 if (i.rounding && (int) n == i.rounding->operand)
7390 continue;
7391
40fb9820 7392 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7393 {
7394 if (i.op[n].imms->X_op == O_constant)
7395 {
e205caa7 7396 int size = imm_size (n);
29b0f896 7397 offsetT val;
b4cac588 7398
29b0f896
AM		 7399 val = offset_in_range (i.op[n].imms->X_add_number,
7400 size);
7401 p = frag_more (size);
7402 md_number_to_chars (p, val, size);
7403 }
7404 else
7405 {
7406 /* Not absolute_section.
7407 Need a 32-bit fixup (don't support 8bit
7408 non-absolute imms). Try to support other
7409 sizes ... */
f86103b7 7410 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7411 int size = imm_size (n);
7412 int sign;
29b0f896 7413
40fb9820 7414 if (i.types[n].bitfield.imm32s
a7d61044 7415 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7416 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7417 sign = 1;
e205caa7
L		 7418 else
7419 sign = 0;
520dc8e8 7420
29b0f896 7421 p = frag_more (size);
d258b828 7422 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7423
2bbd9c25
JJ		 7424 /* This is tough to explain. We end up with this one if we
7425 * have operands that look like
7426 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7427 * obtain the absolute address of the GOT, and it is strongly
7428 * preferable from a performance point of view to avoid using
7429 * a runtime relocation for this. The actual sequence of
7430 * instructions often look something like:
7431 *
7432 * call .L66
7433 * .L66:
7434 * popl %ebx
7435 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7436 *
7437 * The call and pop essentially return the absolute address
7438 * of the label .L66 and store it in %ebx. The linker itself
7439 * will ultimately change the first operand of the addl so
7440 * that %ebx points to the GOT, but to keep things simple, the
7441 * .o file must have this operand set so that it generates not
7442 * the absolute address of .L66, but the absolute address of
7443 * itself. This allows the linker itself simply treat a GOTPC
7444 * relocation as asking for a pcrel offset to the GOT to be
7445 * added in, and the addend of the relocation is stored in the
7446 * operand field for the instruction itself.
7447 *
7448 * Our job here is to fix the operand so that it would add
7449 * the correct offset so that %ebx would point to itself. The
7450 * thing that is tricky is that .-.L66 will point to the
7451 * beginning of the instruction, so we need to further modify
7452 * the operand so that it will point to itself. There are
7453 * other cases where you have something like:
7454 *
7455 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7456 *
7457 * and here no correction would be required. Internally in
7458 * the assembler we treat operands of this form as not being
7459 * pcrel since the '.' is explicitly mentioned, and I wonder
7460 * whether it would simplify matters to do it this way. Who
7461 * knows. In earlier versions of the PIC patches, the
7462 * pcrel_adjust field was used to store the correction, but
7463 * since the expression is not pcrel, I felt it would be
7464 * confusing to do it this way. */
7465
d6ab8113 7466 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7467 || reloc_type == BFD_RELOC_X86_64_32S
7468 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7469 && GOT_symbol
7470 && GOT_symbol == i.op[n].imms->X_add_symbol
7471 && (i.op[n].imms->X_op == O_symbol
7472 || (i.op[n].imms->X_op == O_add
7473 && ((symbol_get_value_expression
7474 (i.op[n].imms->X_op_symbol)->X_op)
7475 == O_subtract))))
7476 {
2bbd9c25
JJ		 7477 offsetT add;
7478
7479 if (insn_start_frag == frag_now)
7480 add = (p - frag_now->fr_literal) - insn_start_off;
7481 else
7482 {
7483 fragS *fr;
7484
7485 add = insn_start_frag->fr_fix - insn_start_off;
7486 for (fr = insn_start_frag->fr_next;
7487 fr && fr != frag_now; fr = fr->fr_next)
7488 add += fr->fr_fix;
7489 add += p - frag_now->fr_literal;
7490 }
7491
4fa24527 7492 if (!object_64bit)
d6ab8113 7493 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7494 else if (size == 4)
d6ab8113 7495 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7496 else if (size == 8)
7497 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7498 i.op[n].imms->X_add_number += add;
29b0f896 7499 }
29b0f896
AM		 7500 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7501 i.op[n].imms, 0, reloc_type);
7502 }
7503 }
7504 }
252b5132
RH		 7505}
7506\f
d182319b
JB		 7507/* x86_cons_fix_new is called via the expression parsing code when a
7508 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7509static int cons_sign = -1;
7510
7511void
e3bb37b5 7512x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7513 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7514{
d258b828 7515 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7516
7517#ifdef TE_PE
7518 if (exp->X_op == O_secrel)
7519 {
7520 exp->X_op = O_symbol;
7521 r = BFD_RELOC_32_SECREL;
7522 }
7523#endif
7524
7525 fix_new_exp (frag, off, len, exp, 0, r);
7526}
7527
357d1bd8
L		 7528/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7529 purpose of the `.dc.a' internal pseudo-op. */
7530
7531int
7532x86_address_bytes (void)
7533{
7534 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7535 return 4;
7536 return stdoutput->arch_info->bits_per_address / 8;
7537}
7538
d382c579
TG		 7539#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7540 || defined (LEX_AT)
d258b828 7541# define lex_got(reloc, adjust, types) NULL
718ddfc0 7542#else
f3c180ae
AM		 7543/* Parse operands of the form
7544 <symbol>@GOTOFF+<nnn>
7545 and similar .plt or .got references.
7546
7547 If we find one, set up the correct relocation in RELOC and copy the
7548 input string, minus the `@GOTOFF' into a malloc'd buffer for
7549 parsing by the calling routine. Return this buffer, and if ADJUST
7550 is non-null set it to the length of the string we removed from the
7551 input line. Otherwise return NULL. */
7552static char *
91d6fa6a 7553lex_got (enum bfd_reloc_code_real *rel,
64e74474 7554 int *adjust,
d258b828 7555 i386_operand_type *types)
f3c180ae 7556{
7b81dfbb
AJ		 7557 /* Some of the relocations depend on the size of what field is to
7558 be relocated. But in our callers i386_immediate and i386_displacement
7559 we don't yet know the operand size (this will be set by insn
7560 matching). Hence we record the word32 relocation here,
7561 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7562 static const struct {
7563 const char *str;
cff8d58a 7564 int len;
4fa24527 7565 const enum bfd_reloc_code_real rel[2];
40fb9820 7566 const i386_operand_type types64;
f3c180ae 7567 } gotrel[] = {
8ce3d284 7568#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7569 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7570 BFD_RELOC_SIZE32 },
7571 OPERAND_TYPE_IMM32_64 },
8ce3d284 7572#endif
cff8d58a
L		 7573 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7574 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7575 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7576 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7577 BFD_RELOC_X86_64_PLT32 },
40fb9820 7578 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7579 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7580 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7581 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7582 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7583 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7584 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7585 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7586 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7587 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7588 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7589 BFD_RELOC_X86_64_TLSGD },
40fb9820 7590 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7591 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7592 _dummy_first_bfd_reloc_code_real },
40fb9820 7593 OPERAND_TYPE_NONE },
cff8d58a
L		 7594 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7595 BFD_RELOC_X86_64_TLSLD },
40fb9820 7596 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7597 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7598 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7599 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7600 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7601 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7602 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7603 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7604 _dummy_first_bfd_reloc_code_real },
40fb9820 7605 OPERAND_TYPE_NONE },
cff8d58a
L		 7606 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7607 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7608 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7609 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7610 _dummy_first_bfd_reloc_code_real },
40fb9820 7611 OPERAND_TYPE_NONE },
cff8d58a
L		 7612 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7613 _dummy_first_bfd_reloc_code_real },
40fb9820 7614 OPERAND_TYPE_NONE },
cff8d58a
L		 7615 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7616 BFD_RELOC_X86_64_GOT32 },
40fb9820 7617 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7618 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7619 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7620 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7621 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7622 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7623 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7624 };
7625 char *cp;
7626 unsigned int j;
7627
d382c579 7628#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7629 if (!IS_ELF)
7630 return NULL;
d382c579 7631#endif
718ddfc0 7632
f3c180ae 7633 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7634 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7635 return NULL;
7636
47465058 7637 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7638 {
cff8d58a 7639 int len = gotrel[j].len;
28f81592 7640 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7641 {
4fa24527 7642 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7643 {
28f81592
AM		 7644 int first, second;
7645 char *tmpbuf, *past_reloc;
f3c180ae 7646
91d6fa6a 7647 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7648
3956db08
JB		 7649 if (types)
7650 {
7651 if (flag_code != CODE_64BIT)
40fb9820
L		 7652 {
7653 types->bitfield.imm32 = 1;
7654 types->bitfield.disp32 = 1;
7655 }
3956db08
JB		 7656 else
7657 *types = gotrel[j].types64;
7658 }
7659
8fd4256d 7660 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7661 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7662
28f81592 7663 /* The length of the first part of our input line. */
f3c180ae 7664 first = cp - input_line_pointer;
28f81592
AM		 7665
7666 /* The second part goes from after the reloc token until
67c11a9b 7667 (and including) an end_of_line char or comma. */
28f81592 7668 past_reloc = cp + 1 + len;
67c11a9b
AM		 7669 cp = past_reloc;
7670 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7671 ++cp;
7672 second = cp + 1 - past_reloc;
28f81592
AM		 7673
7674 /* Allocate and copy string. The trailing NUL shouldn't
7675 be necessary, but be safe. */
add39d23 7676 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7677 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7678 if (second != 0 && *past_reloc != ' ')
7679 /* Replace the relocation token with ' ', so that
7680 errors like foo@GOTOFF1 will be detected. */
7681 tmpbuf[first++] = ' ';
af89796a
L		 7682 else
7683 /* Increment length by 1 if the relocation token is
7684 removed. */
7685 len++;
7686 if (adjust)
7687 *adjust = len;
0787a12d
AM		 7688 memcpy (tmpbuf + first, past_reloc, second);
7689 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7690 return tmpbuf;
7691 }
7692
4fa24527
JB		 7693 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7694 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7695 return NULL;
7696 }
7697 }
7698
7699 /* Might be a symbol version string. Don't as_bad here. */
7700 return NULL;
7701}
4e4f7c87 7702#endif
f3c180ae 7703
a988325c
NC		 7704#ifdef TE_PE
7705#ifdef lex_got
7706#undef lex_got
7707#endif
7708/* Parse operands of the form
7709 <symbol>@SECREL32+<nnn>
7710
7711 If we find one, set up the correct relocation in RELOC and copy the
7712 input string, minus the `@SECREL32' into a malloc'd buffer for
7713 parsing by the calling routine. Return this buffer, and if ADJUST
7714 is non-null set it to the length of the string we removed from the
34bca508
L		 7715 input line. Otherwise return NULL.
7716
a988325c
NC		 7717 This function is copied from the ELF version above adjusted for PE targets. */
7718
7719static char *
7720lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7721 int *adjust ATTRIBUTE_UNUSED,
d258b828 7722 i386_operand_type *types)
a988325c
NC		 7723{
7724 static const struct
7725 {
7726 const char *str;
7727 int len;
7728 const enum bfd_reloc_code_real rel[2];
7729 const i386_operand_type types64;
7730 }
7731 gotrel[] =
7732 {
7733 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7734 BFD_RELOC_32_SECREL },
7735 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7736 };
7737
7738 char *cp;
7739 unsigned j;
7740
7741 for (cp = input_line_pointer; *cp != '@'; cp++)
7742 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7743 return NULL;
7744
7745 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7746 {
7747 int len = gotrel[j].len;
7748
7749 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7750 {
7751 if (gotrel[j].rel[object_64bit] != 0)
7752 {
7753 int first, second;
7754 char *tmpbuf, *past_reloc;
7755
7756 *rel = gotrel[j].rel[object_64bit];
7757 if (adjust)
7758 *adjust = len;
7759
7760 if (types)
7761 {
7762 if (flag_code != CODE_64BIT)
7763 {
7764 types->bitfield.imm32 = 1;
7765 types->bitfield.disp32 = 1;
7766 }
7767 else
7768 *types = gotrel[j].types64;
7769 }
7770
7771 /* The length of the first part of our input line. */
7772 first = cp - input_line_pointer;
7773
7774 /* The second part goes from after the reloc token until
7775 (and including) an end_of_line char or comma. */
7776 past_reloc = cp + 1 + len;
7777 cp = past_reloc;
7778 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7779 ++cp;
7780 second = cp + 1 - past_reloc;
7781
7782 /* Allocate and copy string. The trailing NUL shouldn't
7783 be necessary, but be safe. */
add39d23 7784 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7785 memcpy (tmpbuf, input_line_pointer, first);
7786 if (second != 0 && *past_reloc != ' ')
7787 /* Replace the relocation token with ' ', so that
7788 errors like foo@SECLREL321 will be detected. */
7789 tmpbuf[first++] = ' ';
7790 memcpy (tmpbuf + first, past_reloc, second);
7791 tmpbuf[first + second] = '\0';
7792 return tmpbuf;
7793 }
7794
7795 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7796 gotrel[j].str, 1 << (5 + object_64bit));
7797 return NULL;
7798 }
7799 }
7800
7801 /* Might be a symbol version string. Don't as_bad here. */
7802 return NULL;
7803}
7804
7805#endif /* TE_PE */
7806
62ebcb5c 7807bfd_reloc_code_real_type
e3bb37b5 7808x86_cons (expressionS *exp, int size)
f3c180ae 7809{
62ebcb5c
AM		 7810 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7811
ee86248c
JB		 7812 intel_syntax = -intel_syntax;
7813
3c7b9c2c 7814 exp->X_md = 0;
4fa24527 7815 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7816 {
7817 /* Handle @GOTOFF and the like in an expression. */
7818 char *save;
7819 char *gotfree_input_line;
4a57f2cf 7820 int adjust = 0;
f3c180ae
AM		 7821
7822 save = input_line_pointer;
d258b828 7823 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7824 if (gotfree_input_line)
7825 input_line_pointer = gotfree_input_line;
7826
7827 expression (exp);
7828
7829 if (gotfree_input_line)
7830 {
7831 /* expression () has merrily parsed up to the end of line,
7832 or a comma - in the wrong buffer. Transfer how far
7833 input_line_pointer has moved to the right buffer. */
7834 input_line_pointer = (save
7835 + (input_line_pointer - gotfree_input_line)
7836 + adjust);
7837 free (gotfree_input_line);
3992d3b7
AM		 7838 if (exp->X_op == O_constant
7839 || exp->X_op == O_absent
7840 || exp->X_op == O_illegal
0398aac5 7841 || exp->X_op == O_register
3992d3b7
AM		 7842 || exp->X_op == O_big)
7843 {
7844 char c = *input_line_pointer;
7845 *input_line_pointer = 0;
7846 as_bad (_("missing or invalid expression `%s'"), save);
7847 *input_line_pointer = c;
7848 }
f3c180ae
AM		 7849 }
7850 }
7851 else
7852 expression (exp);
ee86248c
JB		 7853
7854 intel_syntax = -intel_syntax;
7855
7856 if (intel_syntax)
7857 i386_intel_simplify (exp);
62ebcb5c
AM		 7858
7859 return got_reloc;
f3c180ae 7860}
f3c180ae 7861
9f32dd5b
L		 7862static void
7863signed_cons (int size)
6482c264 7864{
d182319b
JB		 7865 if (flag_code == CODE_64BIT)
7866 cons_sign = 1;
7867 cons (size);
7868 cons_sign = -1;
6482c264
NC		 7869}
7870
d182319b 7871#ifdef TE_PE
6482c264 7872static void
7016a5d5 7873pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7874{
7875 expressionS exp;
7876
7877 do
7878 {
7879 expression (&exp);
7880 if (exp.X_op == O_symbol)
7881 exp.X_op = O_secrel;
7882
7883 emit_expr (&exp, 4);
7884 }
7885 while (*input_line_pointer++ == ',');
7886
7887 input_line_pointer--;
7888 demand_empty_rest_of_line ();
7889}
6482c264
NC		 7890#endif
7891
43234a1e
L		 7892/* Handle Vector operations. */
7893
7894static char *
7895check_VecOperations (char *op_string, char *op_end)
7896{
7897 const reg_entry *mask;
7898 const char *saved;
7899 char *end_op;
7900
7901 while (*op_string
7902 && (op_end == NULL || op_string < op_end))
7903 {
7904 saved = op_string;
7905 if (*op_string == '{')
7906 {
7907 op_string++;
7908
7909 /* Check broadcasts. */
7910 if (strncmp (op_string, "1to", 3) == 0)
7911 {
7912 int bcst_type;
7913
7914 if (i.broadcast)
7915 goto duplicated_vec_op;
7916
7917 op_string += 3;
7918 if (*op_string == '8')
7919 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7920 else if (*op_string == '4')
7921 bcst_type = BROADCAST_1TO4;
7922 else if (*op_string == '2')
7923 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7924 else if (*op_string == '1'
7925 && *(op_string+1) == '6')
7926 {
7927 bcst_type = BROADCAST_1TO16;
7928 op_string++;
7929 }
7930 else
7931 {
7932 as_bad (_("Unsupported broadcast: `%s'"), saved);
7933 return NULL;
7934 }
7935 op_string++;
7936
7937 broadcast_op.type = bcst_type;
7938 broadcast_op.operand = this_operand;
7939 i.broadcast = &broadcast_op;
7940 }
7941 /* Check masking operation. */
7942 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7943 {
7944 /* k0 can't be used for write mask. */
7945 if (mask->reg_num == 0)
7946 {
7947 as_bad (_("`%s' can't be used for write mask"),
7948 op_string);
7949 return NULL;
7950 }
7951
7952 if (!i.mask)
7953 {
7954 mask_op.mask = mask;
7955 mask_op.zeroing = 0;
7956 mask_op.operand = this_operand;
7957 i.mask = &mask_op;
7958 }
7959 else
7960 {
7961 if (i.mask->mask)
7962 goto duplicated_vec_op;
7963
7964 i.mask->mask = mask;
7965
7966 /* Only "{z}" is allowed here. No need to check
7967 zeroing mask explicitly. */
7968 if (i.mask->operand != this_operand)
7969 {
7970 as_bad (_("invalid write mask `%s'"), saved);
7971 return NULL;
7972 }
7973 }
7974
7975 op_string = end_op;
7976 }
7977 /* Check zeroing-flag for masking operation. */
7978 else if (*op_string == 'z')
7979 {
7980 if (!i.mask)
7981 {
7982 mask_op.mask = NULL;
7983 mask_op.zeroing = 1;
7984 mask_op.operand = this_operand;
7985 i.mask = &mask_op;
7986 }
7987 else
7988 {
7989 if (i.mask->zeroing)
7990 {
7991 duplicated_vec_op:
7992 as_bad (_("duplicated `%s'"), saved);
7993 return NULL;
7994 }
7995
7996 i.mask->zeroing = 1;
7997
7998 /* Only "{%k}" is allowed here. No need to check mask
7999 register explicitly. */
8000 if (i.mask->operand != this_operand)
8001 {
8002 as_bad (_("invalid zeroing-masking `%s'"),
8003 saved);
8004 return NULL;
8005 }
8006 }
8007
8008 op_string++;
8009 }
8010 else
8011 goto unknown_vec_op;
8012
8013 if (*op_string != '}')
8014 {
8015 as_bad (_("missing `}' in `%s'"), saved);
8016 return NULL;
8017 }
8018 op_string++;
8019 continue;
8020 }
8021 unknown_vec_op:
8022 /* We don't know this one. */
8023 as_bad (_("unknown vector operation: `%s'"), saved);
8024 return NULL;
8025 }
8026
8027 return op_string;
8028}
8029
252b5132 8030static int
70e41ade 8031i386_immediate (char *imm_start)
252b5132
RH		 8032{
8033 char *save_input_line_pointer;
f3c180ae 8034 char *gotfree_input_line;
252b5132 8035 segT exp_seg = 0;
47926f60 8036 expressionS *exp;
40fb9820
L		 8037 i386_operand_type types;
8038
0dfbf9d7 8039 operand_type_set (&types, ~0);
252b5132
RH		 8040
8041 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8042 {
31b2323c
L		 8043 as_bad (_("at most %d immediate operands are allowed"),
8044 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8045 return 0;
8046 }
8047
8048 exp = &im_expressions[i.imm_operands++];
520dc8e8 8049 i.op[this_operand].imms = exp;
252b5132
RH		 8050
8051 if (is_space_char (*imm_start))
8052 ++imm_start;
8053
8054 save_input_line_pointer = input_line_pointer;
8055 input_line_pointer = imm_start;
8056
d258b828 8057 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8058 if (gotfree_input_line)
8059 input_line_pointer = gotfree_input_line;
252b5132
RH		 8060
8061 exp_seg = expression (exp);
8062
83183c0c 8063 SKIP_WHITESPACE ();
43234a1e
L		 8064
8065 /* Handle vector operations. */
8066 if (*input_line_pointer == '{')
8067 {
8068 input_line_pointer = check_VecOperations (input_line_pointer,
8069 NULL);
8070 if (input_line_pointer == NULL)
8071 return 0;
8072 }
8073
252b5132 8074 if (*input_line_pointer)
f3c180ae 8075 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8076
8077 input_line_pointer = save_input_line_pointer;
f3c180ae 8078 if (gotfree_input_line)
ee86248c
JB		 8079 {
8080 free (gotfree_input_line);
8081
8082 if (exp->X_op == O_constant || exp->X_op == O_register)
8083 exp->X_op = O_illegal;
8084 }
8085
8086 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8087}
252b5132 8088
ee86248c
JB		 8089static int
8090i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8091 i386_operand_type types, const char *imm_start)
8092{
8093 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8094 {
313c53d1
L		 8095 if (imm_start)
8096 as_bad (_("missing or invalid immediate expression `%s'"),
8097 imm_start);
3992d3b7 8098 return 0;
252b5132 8099 }
3e73aa7c 8100 else if (exp->X_op == O_constant)
252b5132 8101 {
47926f60 8102 /* Size it properly later. */
40fb9820 8103 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8104 /* If not 64bit, sign extend val. */
8105 if (flag_code != CODE_64BIT
4eed87de
AM		 8106 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8107 exp->X_add_number
8108 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8109 }
4c63da97 8110#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8111 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8112 && exp_seg != absolute_section
47926f60 8113 && exp_seg != text_section
24eab124
AM		 8114 && exp_seg != data_section
8115 && exp_seg != bss_section
8116 && exp_seg != undefined_section
f86103b7 8117 && !bfd_is_com_section (exp_seg))
252b5132 8118 {
d0b47220 8119 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8120 return 0;
8121 }
8122#endif
a841bdf5 8123 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8124 {
313c53d1
L		 8125 if (imm_start)
8126 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8127 return 0;
8128 }
252b5132
RH		 8129 else
8130 {
8131 /* This is an address. The size of the address will be
24eab124 8132 determined later, depending on destination register,
3e73aa7c 8133 suffix, or the default for the section. */
40fb9820
L		 8134 i.types[this_operand].bitfield.imm8 = 1;
8135 i.types[this_operand].bitfield.imm16 = 1;
8136 i.types[this_operand].bitfield.imm32 = 1;
8137 i.types[this_operand].bitfield.imm32s = 1;
8138 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8139 i.types[this_operand] = operand_type_and (i.types[this_operand],
8140 types);
252b5132
RH		 8141 }
8142
8143 return 1;
8144}
8145
551c1ca1 8146static char *
e3bb37b5 8147i386_scale (char *scale)
252b5132 8148{
551c1ca1
AM		 8149 offsetT val;
8150 char *save = input_line_pointer;
252b5132 8151
551c1ca1
AM		 8152 input_line_pointer = scale;
8153 val = get_absolute_expression ();
8154
8155 switch (val)
252b5132 8156 {
551c1ca1 8157 case 1:
252b5132
RH		 8158 i.log2_scale_factor = 0;
8159 break;
551c1ca1 8160 case 2:
252b5132
RH		 8161 i.log2_scale_factor = 1;
8162 break;
551c1ca1 8163 case 4:
252b5132
RH		 8164 i.log2_scale_factor = 2;
8165 break;
551c1ca1 8166 case 8:
252b5132
RH		 8167 i.log2_scale_factor = 3;
8168 break;
8169 default:
a724f0f4
JB		 8170 {
8171 char sep = *input_line_pointer;
8172
8173 *input_line_pointer = '\0';
8174 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8175 scale);
8176 *input_line_pointer = sep;
8177 input_line_pointer = save;
8178 return NULL;
8179 }
252b5132 8180 }
29b0f896 8181 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8182 {
8183 as_warn (_("scale factor of %d without an index register"),
24eab124 8184 1 << i.log2_scale_factor);
252b5132 8185 i.log2_scale_factor = 0;
252b5132 8186 }
551c1ca1
AM		 8187 scale = input_line_pointer;
8188 input_line_pointer = save;
8189 return scale;
252b5132
RH		 8190}
8191
252b5132 8192static int
e3bb37b5 8193i386_displacement (char *disp_start, char *disp_end)
252b5132 8194{
29b0f896 8195 expressionS *exp;
252b5132
RH		 8196 segT exp_seg = 0;
8197 char *save_input_line_pointer;
f3c180ae 8198 char *gotfree_input_line;
40fb9820
L		 8199 int override;
8200 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8201 int ret;
252b5132 8202
31b2323c
L		 8203 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8204 {
8205 as_bad (_("at most %d displacement operands are allowed"),
8206 MAX_MEMORY_OPERANDS);
8207 return 0;
8208 }
8209
0dfbf9d7 8210 operand_type_set (&bigdisp, 0);
40fb9820
L		 8211 if ((i.types[this_operand].bitfield.jumpabsolute)
8212 || (!current_templates->start->opcode_modifier.jump
8213 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8214 {
40fb9820 8215 bigdisp.bitfield.disp32 = 1;
e05278af 8216 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8217 if (flag_code == CODE_64BIT)
8218 {
8219 if (!override)
8220 {
8221 bigdisp.bitfield.disp32s = 1;
8222 bigdisp.bitfield.disp64 = 1;
8223 }
8224 }
8225 else if ((flag_code == CODE_16BIT) ^ override)
8226 {
8227 bigdisp.bitfield.disp32 = 0;
8228 bigdisp.bitfield.disp16 = 1;
8229 }
e05278af
JB		 8230 }
8231 else
8232 {
8233 /* For PC-relative branches, the width of the displacement
8234 is dependent upon data size, not address size. */
e05278af 8235 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8236 if (flag_code == CODE_64BIT)
8237 {
8238 if (override || i.suffix == WORD_MNEM_SUFFIX)
8239 bigdisp.bitfield.disp16 = 1;
8240 else
8241 {
8242 bigdisp.bitfield.disp32 = 1;
8243 bigdisp.bitfield.disp32s = 1;
8244 }
8245 }
8246 else
e05278af
JB		 8247 {
8248 if (!override)
8249 override = (i.suffix == (flag_code != CODE_16BIT
8250 ? WORD_MNEM_SUFFIX
8251 : LONG_MNEM_SUFFIX));
40fb9820
L		 8252 bigdisp.bitfield.disp32 = 1;
8253 if ((flag_code == CODE_16BIT) ^ override)
8254 {
8255 bigdisp.bitfield.disp32 = 0;
8256 bigdisp.bitfield.disp16 = 1;
8257 }
e05278af 8258 }
e05278af 8259 }
c6fb90c8
L		 8260 i.types[this_operand] = operand_type_or (i.types[this_operand],
8261 bigdisp);
252b5132
RH		 8262
8263 exp = &disp_expressions[i.disp_operands];
520dc8e8 8264 i.op[this_operand].disps = exp;
252b5132
RH		 8265 i.disp_operands++;
8266 save_input_line_pointer = input_line_pointer;
8267 input_line_pointer = disp_start;
8268 END_STRING_AND_SAVE (disp_end);
8269
8270#ifndef GCC_ASM_O_HACK
8271#define GCC_ASM_O_HACK 0
8272#endif
8273#if GCC_ASM_O_HACK
8274 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8275 if (i.types[this_operand].bitfield.baseIndex
24eab124 8276 && displacement_string_end[-1] == '+')
252b5132
RH		 8277 {
8278 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8279 constraint within gcc asm statements.
8280 For instance:
8281
8282 #define _set_tssldt_desc(n,addr,limit,type) \
8283 __asm__ __volatile__ ( \
8284 "movw %w2,%0\n\t" \
8285 "movw %w1,2+%0\n\t" \
8286 "rorl $16,%1\n\t" \
8287 "movb %b1,4+%0\n\t" \
8288 "movb %4,5+%0\n\t" \
8289 "movb $0,6+%0\n\t" \
8290 "movb %h1,7+%0\n\t" \
8291 "rorl $16,%1" \
8292 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8293
8294 This works great except that the output assembler ends
8295 up looking a bit weird if it turns out that there is
8296 no offset. You end up producing code that looks like:
8297
8298 #APP
8299 movw $235,(%eax)
8300 movw %dx,2+(%eax)
8301 rorl $16,%edx
8302 movb %dl,4+(%eax)
8303 movb $137,5+(%eax)
8304 movb $0,6+(%eax)
8305 movb %dh,7+(%eax)
8306 rorl $16,%edx
8307 #NO_APP
8308
47926f60 8309 So here we provide the missing zero. */
24eab124
AM		 8310
8311 *displacement_string_end = '0';
252b5132
RH		 8312 }
8313#endif
d258b828 8314 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8315 if (gotfree_input_line)
8316 input_line_pointer = gotfree_input_line;
252b5132 8317
24eab124 8318 exp_seg = expression (exp);
252b5132 8319
636c26b0
AM		 8320 SKIP_WHITESPACE ();
8321 if (*input_line_pointer)
8322 as_bad (_("junk `%s' after expression"), input_line_pointer);
8323#if GCC_ASM_O_HACK
8324 RESTORE_END_STRING (disp_end + 1);
8325#endif
636c26b0 8326 input_line_pointer = save_input_line_pointer;
636c26b0 8327 if (gotfree_input_line)
ee86248c
JB		 8328 {
8329 free (gotfree_input_line);
8330
8331 if (exp->X_op == O_constant || exp->X_op == O_register)
8332 exp->X_op = O_illegal;
8333 }
8334
8335 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8336
8337 RESTORE_END_STRING (disp_end);
8338
8339 return ret;
8340}
8341
8342static int
8343i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8344 i386_operand_type types, const char *disp_start)
8345{
8346 i386_operand_type bigdisp;
8347 int ret = 1;
636c26b0 8348
24eab124
AM		 8349 /* We do this to make sure that the section symbol is in
8350 the symbol table. We will ultimately change the relocation
47926f60 8351 to be relative to the beginning of the section. */
1ae12ab7 8352 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8353 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8354 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8355 {
636c26b0 8356 if (exp->X_op != O_symbol)
3992d3b7 8357 goto inv_disp;
636c26b0 8358
e5cb08ac 8359 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8360 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8361 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8362 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8363 exp->X_op = O_subtract;
8364 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8365 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8366 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8367 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8368 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8369 else
29b0f896 8370 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8371 }
252b5132 8372
3992d3b7
AM		 8373 else if (exp->X_op == O_absent
8374 || exp->X_op == O_illegal
ee86248c 8375 || exp->X_op == O_big)
2daf4fd8 8376 {
3992d3b7
AM		 8377 inv_disp:
8378 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8379 disp_start);
3992d3b7 8380 ret = 0;
2daf4fd8
AM		 8381 }
8382
0e1147d9
L		 8383 else if (flag_code == CODE_64BIT
8384 && !i.prefix[ADDR_PREFIX]
8385 && exp->X_op == O_constant)
8386 {
8387 /* Since displacement is signed extended to 64bit, don't allow
8388 disp32 and turn off disp32s if they are out of range. */
8389 i.types[this_operand].bitfield.disp32 = 0;
8390 if (!fits_in_signed_long (exp->X_add_number))
8391 {
8392 i.types[this_operand].bitfield.disp32s = 0;
8393 if (i.types[this_operand].bitfield.baseindex)
8394 {
8395 as_bad (_("0x%lx out range of signed 32bit displacement"),
8396 (long) exp->X_add_number);
8397 ret = 0;
8398 }
8399 }
8400 }
8401
4c63da97 8402#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8403 else if (exp->X_op != O_constant
8404 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8405 && exp_seg != absolute_section
8406 && exp_seg != text_section
8407 && exp_seg != data_section
8408 && exp_seg != bss_section
8409 && exp_seg != undefined_section
8410 && !bfd_is_com_section (exp_seg))
24eab124 8411 {
d0b47220 8412 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8413 ret = 0;
24eab124 8414 }
252b5132 8415#endif
3956db08 8416
40fb9820
L		 8417 /* Check if this is a displacement only operand. */
8418 bigdisp = i.types[this_operand];
8419 bigdisp.bitfield.disp8 = 0;
8420 bigdisp.bitfield.disp16 = 0;
8421 bigdisp.bitfield.disp32 = 0;
8422 bigdisp.bitfield.disp32s = 0;
8423 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8424 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8425 i.types[this_operand] = operand_type_and (i.types[this_operand],
8426 types);
3956db08 8427
3992d3b7 8428 return ret;
252b5132
RH		 8429}
8430
eecb386c 8431/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8432 Return 1 on success, 0 on a failure. */
8433
252b5132 8434static int
e3bb37b5 8435i386_index_check (const char *operand_string)
252b5132 8436{
fc0763e6 8437 const char *kind = "base/index";
be05d201
L		 8438 enum flag_code addr_mode;
8439
8440 if (i.prefix[ADDR_PREFIX])
8441 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8442 else
8443 {
8444 addr_mode = flag_code;
8445
24eab124 8446#if INFER_ADDR_PREFIX
be05d201
L		 8447 if (i.mem_operands == 0)
8448 {
8449 /* Infer address prefix from the first memory operand. */
8450 const reg_entry *addr_reg = i.base_reg;
8451
8452 if (addr_reg == NULL)
8453 addr_reg = i.index_reg;
eecb386c 8454
be05d201
L		 8455 if (addr_reg)
8456 {
8457 if (addr_reg->reg_num == RegEip
8458 || addr_reg->reg_num == RegEiz
8459 || addr_reg->reg_type.bitfield.reg32)
8460 addr_mode = CODE_32BIT;
8461 else if (flag_code != CODE_64BIT
8462 && addr_reg->reg_type.bitfield.reg16)
8463 addr_mode = CODE_16BIT;
8464
8465 if (addr_mode != flag_code)
8466 {
8467 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8468 i.prefixes += 1;
8469 /* Change the size of any displacement too. At most one
8470 of Disp16 or Disp32 is set.
8471 FIXME. There doesn't seem to be any real need for
8472 separate Disp16 and Disp32 flags. The same goes for
8473 Imm16 and Imm32. Removing them would probably clean
8474 up the code quite a lot. */
8475 if (flag_code != CODE_64BIT
8476 && (i.types[this_operand].bitfield.disp16
8477 || i.types[this_operand].bitfield.disp32))
8478 i.types[this_operand]
8479 = operand_type_xor (i.types[this_operand], disp16_32);
8480 }
8481 }
8482 }
24eab124 8483#endif
be05d201
L		 8484 }
8485
fc0763e6
JB		 8486 if (current_templates->start->opcode_modifier.isstring
8487 && !current_templates->start->opcode_modifier.immext
8488 && (current_templates->end[-1].opcode_modifier.isstring
8489 || i.mem_operands))
8490 {
8491 /* Memory operands of string insns are special in that they only allow
8492 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8493 const reg_entry *expected_reg;
8494 static const char *di_si[][2] =
8495 {
8496 { "esi", "edi" },
8497 { "si", "di" },
8498 { "rsi", "rdi" }
8499 };
8500 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8501
8502 kind = "string address";
8503
8504 if (current_templates->start->opcode_modifier.w)
8505 {
8506 i386_operand_type type = current_templates->end[-1].operand_types[0];
8507
8508 if (!type.bitfield.baseindex
8509 || ((!i.mem_operands != !intel_syntax)
8510 && current_templates->end[-1].operand_types[1]
8511 .bitfield.baseindex))
8512 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8513 expected_reg = hash_find (reg_hash,
8514 di_si[addr_mode][type.bitfield.esseg]);
8515
fc0763e6
JB		 8516 }
8517 else
be05d201 8518 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8519
be05d201
L		 8520 if (i.base_reg != expected_reg
8521 || i.index_reg
fc0763e6 8522 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8523 {
be05d201
L		 8524 /* The second memory operand must have the same size as
8525 the first one. */
8526 if (i.mem_operands
8527 && i.base_reg
8528 && !((addr_mode == CODE_64BIT
8529 && i.base_reg->reg_type.bitfield.reg64)
8530 || (addr_mode == CODE_32BIT
8531 ? i.base_reg->reg_type.bitfield.reg32
8532 : i.base_reg->reg_type.bitfield.reg16)))
8533 goto bad_address;
8534
fc0763e6
JB		 8535 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8536 operand_string,
8537 intel_syntax ? '[' : '(',
8538 register_prefix,
be05d201 8539 expected_reg->reg_name,
fc0763e6 8540 intel_syntax ? ']' : ')');
be05d201 8541 return 1;
fc0763e6 8542 }
be05d201
L		 8543 else
8544 return 1;
8545
8546bad_address:
8547 as_bad (_("`%s' is not a valid %s expression"),
8548 operand_string, kind);
8549 return 0;
3e73aa7c
JH		 8550 }
8551 else
8552 {
be05d201
L		 8553 if (addr_mode != CODE_16BIT)
8554 {
8555 /* 32-bit/64-bit checks. */
8556 if ((i.base_reg
8557 && (addr_mode == CODE_64BIT
8558 ? !i.base_reg->reg_type.bitfield.reg64
8559 : !i.base_reg->reg_type.bitfield.reg32)
8560 && (i.index_reg
8561 || (i.base_reg->reg_num
8562 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8563 || (i.index_reg
8564 && !i.index_reg->reg_type.bitfield.regxmm
8565 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8566 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8567 && ((addr_mode == CODE_64BIT
8568 ? !(i.index_reg->reg_type.bitfield.reg64
8569 || i.index_reg->reg_num == RegRiz)
8570 : !(i.index_reg->reg_type.bitfield.reg32
8571 || i.index_reg->reg_num == RegEiz))
8572 || !i.index_reg->reg_type.bitfield.baseindex)))
8573 goto bad_address;
8574 }
8575 else
3e73aa7c 8576 {
be05d201 8577 /* 16-bit checks. */
3e73aa7c 8578 if ((i.base_reg
40fb9820
L		 8579 && (!i.base_reg->reg_type.bitfield.reg16
8580 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8581 || (i.index_reg
40fb9820
L		 8582 && (!i.index_reg->reg_type.bitfield.reg16
8583 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8584 || !(i.base_reg
8585 && i.base_reg->reg_num < 6
8586 && i.index_reg->reg_num >= 6
8587 && i.log2_scale_factor == 0))))
be05d201 8588 goto bad_address;
3e73aa7c
JH		 8589 }
8590 }
be05d201 8591 return 1;
24eab124 8592}
252b5132 8593
43234a1e
L		 8594/* Handle vector immediates. */
8595
8596static int
8597RC_SAE_immediate (const char *imm_start)
8598{
8599 unsigned int match_found, j;
8600 const char *pstr = imm_start;
8601 expressionS *exp;
8602
8603 if (*pstr != '{')
8604 return 0;
8605
8606 pstr++;
8607 match_found = 0;
8608 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8609 {
8610 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8611 {
8612 if (!i.rounding)
8613 {
8614 rc_op.type = RC_NamesTable[j].type;
8615 rc_op.operand = this_operand;
8616 i.rounding = &rc_op;
8617 }
8618 else
8619 {
8620 as_bad (_("duplicated `%s'"), imm_start);
8621 return 0;
8622 }
8623 pstr += RC_NamesTable[j].len;
8624 match_found = 1;
8625 break;
8626 }
8627 }
8628 if (!match_found)
8629 return 0;
8630
8631 if (*pstr++ != '}')
8632 {
8633 as_bad (_("Missing '}': '%s'"), imm_start);
8634 return 0;
8635 }
8636 /* RC/SAE immediate string should contain nothing more. */;
8637 if (*pstr != 0)
8638 {
8639 as_bad (_("Junk after '}': '%s'"), imm_start);
8640 return 0;
8641 }
8642
8643 exp = &im_expressions[i.imm_operands++];
8644 i.op[this_operand].imms = exp;
8645
8646 exp->X_op = O_constant;
8647 exp->X_add_number = 0;
8648 exp->X_add_symbol = (symbolS *) 0;
8649 exp->X_op_symbol = (symbolS *) 0;
8650
8651 i.types[this_operand].bitfield.imm8 = 1;
8652 return 1;
8653}
8654
fc0763e6 8655/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8656 on error. */
252b5132 8657
252b5132 8658static int
a7619375 8659i386_att_operand (char *operand_string)
252b5132 8660{
af6bdddf
AM		 8661 const reg_entry *r;
8662 char *end_op;
24eab124 8663 char *op_string = operand_string;
252b5132 8664
24eab124 8665 if (is_space_char (*op_string))
252b5132
RH		 8666 ++op_string;
8667
24eab124 8668 /* We check for an absolute prefix (differentiating,
47926f60 8669 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8670 if (*op_string == ABSOLUTE_PREFIX)
8671 {
8672 ++op_string;
8673 if (is_space_char (*op_string))
8674 ++op_string;
40fb9820 8675 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8676 }
252b5132 8677
47926f60 8678 /* Check if operand is a register. */
4d1bb795 8679 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8680 {
40fb9820
L		 8681 i386_operand_type temp;
8682
24eab124
AM		 8683 /* Check for a segment override by searching for ':' after a
8684 segment register. */
8685 op_string = end_op;
8686 if (is_space_char (*op_string))
8687 ++op_string;
40fb9820
L		 8688 if (*op_string == ':'
8689 && (r->reg_type.bitfield.sreg2
8690 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8691 {
8692 switch (r->reg_num)
8693 {
8694 case 0:
8695 i.seg[i.mem_operands] = &es;
8696 break;
8697 case 1:
8698 i.seg[i.mem_operands] = &cs;
8699 break;
8700 case 2:
8701 i.seg[i.mem_operands] = &ss;
8702 break;
8703 case 3:
8704 i.seg[i.mem_operands] = &ds;
8705 break;
8706 case 4:
8707 i.seg[i.mem_operands] = &fs;
8708 break;
8709 case 5:
8710 i.seg[i.mem_operands] = &gs;
8711 break;
8712 }
252b5132 8713
24eab124 8714 /* Skip the ':' and whitespace. */
252b5132
RH		 8715 ++op_string;
8716 if (is_space_char (*op_string))
24eab124 8717 ++op_string;
252b5132 8718
24eab124
AM		 8719 if (!is_digit_char (*op_string)
8720 && !is_identifier_char (*op_string)
8721 && *op_string != '('
8722 && *op_string != ABSOLUTE_PREFIX)
8723 {
8724 as_bad (_("bad memory operand `%s'"), op_string);
8725 return 0;
8726 }
47926f60 8727 /* Handle case of %es:*foo. */
24eab124
AM		 8728 if (*op_string == ABSOLUTE_PREFIX)
8729 {
8730 ++op_string;
8731 if (is_space_char (*op_string))
8732 ++op_string;
40fb9820 8733 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8734 }
8735 goto do_memory_reference;
8736 }
43234a1e
L		 8737
8738 /* Handle vector operations. */
8739 if (*op_string == '{')
8740 {
8741 op_string = check_VecOperations (op_string, NULL);
8742 if (op_string == NULL)
8743 return 0;
8744 }
8745
24eab124
AM		 8746 if (*op_string)
8747 {
d0b47220 8748 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8749 return 0;
8750 }
40fb9820
L		 8751 temp = r->reg_type;
8752 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8753 i.types[this_operand] = operand_type_or (i.types[this_operand],
8754 temp);
7d5e4556 8755 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8756 i.op[this_operand].regs = r;
24eab124
AM		 8757 i.reg_operands++;
8758 }
af6bdddf
AM		 8759 else if (*op_string == REGISTER_PREFIX)
8760 {
8761 as_bad (_("bad register name `%s'"), op_string);
8762 return 0;
8763 }
24eab124 8764 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8765 {
24eab124 8766 ++op_string;
40fb9820 8767 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8768 {
d0b47220 8769 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8770 return 0;
8771 }
8772 if (!i386_immediate (op_string))
8773 return 0;
8774 }
43234a1e
L		 8775 else if (RC_SAE_immediate (operand_string))
8776 {
8777 /* If it is a RC or SAE immediate, do nothing. */
8778 ;
8779 }
24eab124
AM		 8780 else if (is_digit_char (*op_string)
8781 || is_identifier_char (*op_string)
d02603dc 8782 || *op_string == '"'
e5cb08ac 8783 || *op_string == '(')
24eab124 8784 {
47926f60 8785 /* This is a memory reference of some sort. */
af6bdddf 8786 char *base_string;
252b5132 8787
47926f60 8788 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8789 char *displacement_string_start;
8790 char *displacement_string_end;
43234a1e 8791 char *vop_start;
252b5132 8792
24eab124 8793 do_memory_reference:
24eab124 8794 if ((i.mem_operands == 1
40fb9820 8795 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8796 || i.mem_operands == 2)
8797 {
8798 as_bad (_("too many memory references for `%s'"),
8799 current_templates->start->name);
8800 return 0;
8801 }
252b5132 8802
24eab124
AM		 8803 /* Check for base index form. We detect the base index form by
8804 looking for an ')' at the end of the operand, searching
8805 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8806 after the '('. */
af6bdddf 8807 base_string = op_string + strlen (op_string);
c3332e24 8808
43234a1e
L		 8809 /* Handle vector operations. */
8810 vop_start = strchr (op_string, '{');
8811 if (vop_start && vop_start < base_string)
8812 {
8813 if (check_VecOperations (vop_start, base_string) == NULL)
8814 return 0;
8815 base_string = vop_start;
8816 }
8817
af6bdddf
AM		 8818 --base_string;
8819 if (is_space_char (*base_string))
8820 --base_string;
252b5132 8821
47926f60 8822 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8823 displacement_string_start = op_string;
8824 displacement_string_end = base_string + 1;
252b5132 8825
24eab124
AM		 8826 if (*base_string == ')')
8827 {
af6bdddf 8828 char *temp_string;
24eab124
AM		 8829 unsigned int parens_balanced = 1;
8830 /* We've already checked that the number of left & right ()'s are
47926f60 8831 equal, so this loop will not be infinite. */
24eab124
AM		 8832 do
8833 {
8834 base_string--;
8835 if (*base_string == ')')
8836 parens_balanced++;
8837 if (*base_string == '(')
8838 parens_balanced--;
8839 }
8840 while (parens_balanced);
c3332e24 8841
af6bdddf 8842 temp_string = base_string;
c3332e24 8843
24eab124 8844 /* Skip past '(' and whitespace. */
252b5132
RH		 8845 ++base_string;
8846 if (is_space_char (*base_string))
24eab124 8847 ++base_string;
252b5132 8848
af6bdddf 8849 if (*base_string == ','
4eed87de
AM		 8850 || ((i.base_reg = parse_register (base_string, &end_op))
8851 != NULL))
252b5132 8852 {
af6bdddf 8853 displacement_string_end = temp_string;
252b5132 8854
40fb9820 8855 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8856
af6bdddf 8857 if (i.base_reg)
24eab124 8858 {
24eab124
AM		 8859 base_string = end_op;
8860 if (is_space_char (*base_string))
8861 ++base_string;
af6bdddf
AM		 8862 }
8863
8864 /* There may be an index reg or scale factor here. */
8865 if (*base_string == ',')
8866 {
8867 ++base_string;
8868 if (is_space_char (*base_string))
8869 ++base_string;
8870
4eed87de
AM		 8871 if ((i.index_reg = parse_register (base_string, &end_op))
8872 != NULL)
24eab124 8873 {
af6bdddf 8874 base_string = end_op;
24eab124
AM		 8875 if (is_space_char (*base_string))
8876 ++base_string;
af6bdddf
AM		 8877 if (*base_string == ',')
8878 {
8879 ++base_string;
8880 if (is_space_char (*base_string))
8881 ++base_string;
8882 }
e5cb08ac 8883 else if (*base_string != ')')
af6bdddf 8884 {
4eed87de
AM		 8885 as_bad (_("expecting `,' or `)' "
8886 "after index register in `%s'"),
af6bdddf
AM		 8887 operand_string);
8888 return 0;
8889 }
24eab124 8890 }
af6bdddf 8891 else if (*base_string == REGISTER_PREFIX)
24eab124 8892 {
f76bf5e0
L		 8893 end_op = strchr (base_string, ',');
8894 if (end_op)
8895 *end_op = '\0';
af6bdddf 8896 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8897 return 0;
8898 }
252b5132 8899
47926f60 8900 /* Check for scale factor. */
551c1ca1 8901 if (*base_string != ')')
af6bdddf 8902 {
551c1ca1
AM		 8903 char *end_scale = i386_scale (base_string);
8904
8905 if (!end_scale)
af6bdddf 8906 return 0;
24eab124 8907
551c1ca1 8908 base_string = end_scale;
af6bdddf
AM		 8909 if (is_space_char (*base_string))
8910 ++base_string;
8911 if (*base_string != ')')
8912 {
4eed87de
AM		 8913 as_bad (_("expecting `)' "
8914 "after scale factor in `%s'"),
af6bdddf
AM		 8915 operand_string);
8916 return 0;
8917 }
8918 }
8919 else if (!i.index_reg)
24eab124 8920 {
4eed87de
AM		 8921 as_bad (_("expecting index register or scale factor "
8922 "after `,'; got '%c'"),
af6bdddf 8923 *base_string);
24eab124
AM		 8924 return 0;
8925 }
8926 }
af6bdddf 8927 else if (*base_string != ')')
24eab124 8928 {
4eed87de
AM		 8929 as_bad (_("expecting `,' or `)' "
8930 "after base register in `%s'"),
af6bdddf 8931 operand_string);
24eab124
AM		 8932 return 0;
8933 }
c3332e24 8934 }
af6bdddf 8935 else if (*base_string == REGISTER_PREFIX)
c3332e24 8936 {
f76bf5e0
L		 8937 end_op = strchr (base_string, ',');
8938 if (end_op)
8939 *end_op = '\0';
af6bdddf 8940 as_bad (_("bad register name `%s'"), base_string);
24eab124 8941 return 0;
c3332e24 8942 }
24eab124
AM		 8943 }
8944
8945 /* If there's an expression beginning the operand, parse it,
8946 assuming displacement_string_start and
8947 displacement_string_end are meaningful. */
8948 if (displacement_string_start != displacement_string_end)
8949 {
8950 if (!i386_displacement (displacement_string_start,
8951 displacement_string_end))
8952 return 0;
8953 }
8954
8955 /* Special case for (%dx) while doing input/output op. */
8956 if (i.base_reg
0dfbf9d7
L		 8957 && operand_type_equal (&i.base_reg->reg_type,
8958 &reg16_inoutportreg)
24eab124
AM		 8959 && i.index_reg == 0
8960 && i.log2_scale_factor == 0
8961 && i.seg[i.mem_operands] == 0
40fb9820 8962 && !operand_type_check (i.types[this_operand], disp))
24eab124 8963 {
65da13b5 8964 i.types[this_operand] = inoutportreg;
24eab124
AM		 8965 return 1;
8966 }
8967
eecb386c
AM		 8968 if (i386_index_check (operand_string) == 0)
8969 return 0;
5c07affc 8970 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8971 i.mem_operands++;
8972 }
8973 else
ce8a8b2f
AM		 8974 {
8975 /* It's not a memory operand; argh! */
24eab124
AM		 8976 as_bad (_("invalid char %s beginning operand %d `%s'"),
8977 output_invalid (*op_string),
8978 this_operand + 1,
8979 op_string);
8980 return 0;
8981 }
47926f60 8982 return 1; /* Normal return. */
252b5132
RH		 8983}
8984\f
fa94de6b
RM		 8985/* Calculate the maximum variable size (i.e., excluding fr_fix)
8986 that an rs_machine_dependent frag may reach. */
8987
8988unsigned int
8989i386_frag_max_var (fragS *frag)
8990{
8991 /* The only relaxable frags are for jumps.
8992 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8993 gas_assert (frag->fr_type == rs_machine_dependent);
8994 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8995}
8996
b084df0b
L		 8997#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8998static int
8dcea932 8999elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9000{
9001 /* STT_GNU_IFUNC symbol must go through PLT. */
9002 if ((symbol_get_bfdsym (fr_symbol)->flags
9003 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9004 return 0;
9005
9006 if (!S_IS_EXTERNAL (fr_symbol))
9007 /* Symbol may be weak or local. */
9008 return !S_IS_WEAK (fr_symbol);
9009
8dcea932
L		 9010 /* Global symbols with non-default visibility can't be preempted. */
9011 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9012 return 1;
9013
9014 if (fr_var != NO_RELOC)
9015 switch ((enum bfd_reloc_code_real) fr_var)
9016 {
9017 case BFD_RELOC_386_PLT32:
9018 case BFD_RELOC_X86_64_PLT32:
9019 /* Symbol with PLT relocatin may be preempted. */
9020 return 0;
9021 default:
9022 abort ();
9023 }
9024
b084df0b
L		 9025 /* Global symbols with default visibility in a shared library may be
9026 preempted by another definition. */
8dcea932 9027 return !shared;
b084df0b
L		 9028}
9029#endif
9030
ee7fcc42
AM		 9031/* md_estimate_size_before_relax()
9032
9033 Called just before relax() for rs_machine_dependent frags. The x86
9034 assembler uses these frags to handle variable size jump
9035 instructions.
9036
9037 Any symbol that is now undefined will not become defined.
9038 Return the correct fr_subtype in the frag.
9039 Return the initial "guess for variable size of frag" to caller.
9040 The guess is actually the growth beyond the fixed part. Whatever
9041 we do to grow the fixed or variable part contributes to our
9042 returned value. */
9043
252b5132 9044int
7016a5d5 9045md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9046{
252b5132 9047 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9048 check for un-relaxable symbols. On an ELF system, we can't relax
9049 an externally visible symbol, because it may be overridden by a
9050 shared library. */
9051 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9052#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9053 || (IS_ELF
8dcea932
L		 9054 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9055 fragP->fr_var))
fbeb56a4
DK		 9056#endif
9057#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9058 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9059 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9060#endif
9061 )
252b5132 9062 {
b98ef147
AM		 9063 /* Symbol is undefined in this segment, or we need to keep a
9064 reloc so that weak symbols can be overridden. */
9065 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9066 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9067 unsigned char *opcode;
9068 int old_fr_fix;
f6af82bd 9069
ee7fcc42 9070 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9071 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9072 else if (size == 2)
f6af82bd
AM		 9073 reloc_type = BFD_RELOC_16_PCREL;
9074 else
9075 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9076
ee7fcc42
AM		 9077 old_fr_fix = fragP->fr_fix;
9078 opcode = (unsigned char *) fragP->fr_opcode;
9079
fddf5b5b 9080 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9081 {
fddf5b5b
AM		 9082 case UNCOND_JUMP:
9083 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9084 opcode[0] = 0xe9;
252b5132 9085 fragP->fr_fix += size;
062cd5e7
AS		 9086 fix_new (fragP, old_fr_fix, size,
9087 fragP->fr_symbol,
9088 fragP->fr_offset, 1,
9089 reloc_type);
252b5132
RH		 9090 break;
9091
fddf5b5b 9092 case COND_JUMP86:
412167cb
AM		 9093 if (size == 2
9094 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9095 {
9096 /* Negate the condition, and branch past an
9097 unconditional jump. */
9098 opcode[0] ^= 1;
9099 opcode[1] = 3;
9100 /* Insert an unconditional jump. */
9101 opcode[2] = 0xe9;
9102 /* We added two extra opcode bytes, and have a two byte
9103 offset. */
9104 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9105 fix_new (fragP, old_fr_fix + 2, 2,
9106 fragP->fr_symbol,
9107 fragP->fr_offset, 1,
9108 reloc_type);
fddf5b5b
AM		 9109 break;
9110 }
9111 /* Fall through. */
9112
9113 case COND_JUMP:
412167cb
AM		 9114 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9115 {
3e02c1cc
AM		 9116 fixS *fixP;
9117
412167cb 9118 fragP->fr_fix += 1;
3e02c1cc
AM		 9119 fixP = fix_new (fragP, old_fr_fix, 1,
9120 fragP->fr_symbol,
9121 fragP->fr_offset, 1,
9122 BFD_RELOC_8_PCREL);
9123 fixP->fx_signed = 1;
412167cb
AM		 9124 break;
9125 }
93c2a809 9126
24eab124 9127 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9128 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9129 opcode[1] = opcode[0] + 0x10;
f6af82bd 9130 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9131 /* We've added an opcode byte. */
9132 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9133 fix_new (fragP, old_fr_fix + 1, size,
9134 fragP->fr_symbol,
9135 fragP->fr_offset, 1,
9136 reloc_type);
252b5132 9137 break;
fddf5b5b
AM		 9138
9139 default:
9140 BAD_CASE (fragP->fr_subtype);
9141 break;
252b5132
RH		 9142 }
9143 frag_wane (fragP);
ee7fcc42 9144 return fragP->fr_fix - old_fr_fix;
252b5132 9145 }
93c2a809 9146
93c2a809
AM		 9147 /* Guess size depending on current relax state. Initially the relax
9148 state will correspond to a short jump and we return 1, because
9149 the variable part of the frag (the branch offset) is one byte
9150 long. However, we can relax a section more than once and in that
9151 case we must either set fr_subtype back to the unrelaxed state,
9152 or return the value for the appropriate branch. */
9153 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9154}
9155
47926f60
KH		 9156/* Called after relax() is finished.
9157
9158 In: Address of frag.
9159 fr_type == rs_machine_dependent.
9160 fr_subtype is what the address relaxed to.
9161
9162 Out: Any fixSs and constants are set up.
9163 Caller will turn frag into a ".space 0". */
9164
252b5132 9165void
7016a5d5
TG		 9166md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9167 fragS *fragP)
252b5132 9168{
29b0f896 9169 unsigned char *opcode;
252b5132 9170 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9171 offsetT target_address;
9172 offsetT opcode_address;
252b5132 9173 unsigned int extension = 0;
847f7ad4 9174 offsetT displacement_from_opcode_start;
252b5132
RH		 9175
9176 opcode = (unsigned char *) fragP->fr_opcode;
9177
47926f60 9178 /* Address we want to reach in file space. */
252b5132 9179 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9180
47926f60 9181 /* Address opcode resides at in file space. */
252b5132
RH		 9182 opcode_address = fragP->fr_address + fragP->fr_fix;
9183
47926f60 9184 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9185 displacement_from_opcode_start = target_address - opcode_address;
9186
fddf5b5b 9187 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9188 {
47926f60
KH		 9189 /* Don't have to change opcode. */
9190 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9191 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9192 }
9193 else
9194 {
9195 if (no_cond_jump_promotion
9196 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9197 as_warn_where (fragP->fr_file, fragP->fr_line,
9198 _("long jump required"));
252b5132 9199
fddf5b5b
AM		 9200 switch (fragP->fr_subtype)
9201 {
9202 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9203 extension = 4; /* 1 opcode + 4 displacement */
9204 opcode[0] = 0xe9;
9205 where_to_put_displacement = &opcode[1];
9206 break;
252b5132 9207
fddf5b5b
AM		 9208 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9209 extension = 2; /* 1 opcode + 2 displacement */
9210 opcode[0] = 0xe9;
9211 where_to_put_displacement = &opcode[1];
9212 break;
252b5132 9213
fddf5b5b
AM		 9214 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9215 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9216 extension = 5; /* 2 opcode + 4 displacement */
9217 opcode[1] = opcode[0] + 0x10;
9218 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9219 where_to_put_displacement = &opcode[2];
9220 break;
252b5132 9221
fddf5b5b
AM		 9222 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9223 extension = 3; /* 2 opcode + 2 displacement */
9224 opcode[1] = opcode[0] + 0x10;
9225 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9226 where_to_put_displacement = &opcode[2];
9227 break;
252b5132 9228
fddf5b5b
AM		 9229 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9230 extension = 4;
9231 opcode[0] ^= 1;
9232 opcode[1] = 3;
9233 opcode[2] = 0xe9;
9234 where_to_put_displacement = &opcode[3];
9235 break;
9236
9237 default:
9238 BAD_CASE (fragP->fr_subtype);
9239 break;
9240 }
252b5132 9241 }
fddf5b5b 9242
7b81dfbb
AJ		 9243 /* If size if less then four we are sure that the operand fits,
9244 but if it's 4, then it could be that the displacement is larger
9245 then -/+ 2GB. */
9246 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9247 && object_64bit
9248 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9249 + ((addressT) 1 << 31))
9250 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9251 {
9252 as_bad_where (fragP->fr_file, fragP->fr_line,
9253 _("jump target out of range"));
9254 /* Make us emit 0. */
9255 displacement_from_opcode_start = extension;
9256 }
47926f60 9257 /* Now put displacement after opcode. */
252b5132
RH		 9258 md_number_to_chars ((char *) where_to_put_displacement,
9259 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9260 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9261 fragP->fr_fix += extension;
9262}
9263\f
7016a5d5 9264/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9265 by our caller that we have all the info we need to fix it up.
9266
7016a5d5
TG		 9267 Parameter valP is the pointer to the value of the bits.
9268
252b5132
RH		 9269 On the 386, immediates, displacements, and data pointers are all in
9270 the same (little-endian) format, so we don't need to care about which
9271 we are handling. */
9272
94f592af 9273void
7016a5d5 9274md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9275{
94f592af 9276 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9277 valueT value = *valP;
252b5132 9278
f86103b7 9279#if !defined (TE_Mach)
93382f6d
AM		 9280 if (fixP->fx_pcrel)
9281 {
9282 switch (fixP->fx_r_type)
9283 {
5865bb77
ILT		 9284 default:
9285 break;
9286
d6ab8113
JB		 9287 case BFD_RELOC_64:
9288 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9289 break;
93382f6d 9290 case BFD_RELOC_32:
ae8887b5 9291 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9292 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9293 break;
9294 case BFD_RELOC_16:
9295 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9296 break;
9297 case BFD_RELOC_8:
9298 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9299 break;
9300 }
9301 }
252b5132 9302
a161fe53 9303 if (fixP->fx_addsy != NULL
31312f95 9304 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9305 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9306 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9307 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9308 && !use_rela_relocations)
252b5132 9309 {
31312f95
AM		 9310 /* This is a hack. There should be a better way to handle this.
9311 This covers for the fact that bfd_install_relocation will
9312 subtract the current location (for partial_inplace, PC relative
9313 relocations); see more below. */
252b5132 9314#ifndef OBJ_AOUT
718ddfc0 9315 if (IS_ELF
252b5132
RH		 9316#ifdef TE_PE
9317 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9318#endif
9319 )
9320 value += fixP->fx_where + fixP->fx_frag->fr_address;
9321#endif
9322#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9323 if (IS_ELF)
252b5132 9324 {
6539b54b 9325 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9326
6539b54b 9327 if ((sym_seg == seg
2f66722d 9328 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9329 && sym_seg != absolute_section))
af65af87 9330 && !generic_force_reloc (fixP))
2f66722d
AM		 9331 {
9332 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9333 bfd_install_relocation subtracts them out again. I think
9334 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9335 it. FIXME. */
9336 value += fixP->fx_where + fixP->fx_frag->fr_address;
9337 }
252b5132
RH		 9338 }
9339#endif
9340#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9341 /* For some reason, the PE format does not store a
9342 section address offset for a PC relative symbol. */
9343 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9344 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9345 value += md_pcrel_from (fixP);
9346#endif
9347 }
fbeb56a4 9348#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9349 if (fixP->fx_addsy != NULL
9350 && S_IS_WEAK (fixP->fx_addsy)
9351 /* PR 16858: Do not modify weak function references. */
9352 && ! fixP->fx_pcrel)
fbeb56a4 9353 {
296a8689
NC		 9354#if !defined (TE_PEP)
9355 /* For x86 PE weak function symbols are neither PC-relative
9356 nor do they set S_IS_FUNCTION. So the only reliable way
9357 to detect them is to check the flags of their containing
9358 section. */
9359 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9360 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9361 ;
9362 else
9363#endif
fbeb56a4
DK		 9364 value -= S_GET_VALUE (fixP->fx_addsy);
9365 }
9366#endif
252b5132
RH		 9367
9368 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9369 and we must not disappoint it. */
252b5132 9370#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9371 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9372 switch (fixP->fx_r_type)
9373 {
9374 case BFD_RELOC_386_PLT32:
3e73aa7c 9375 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9376 /* Make the jump instruction point to the address of the operand. At
9377 runtime we merely add the offset to the actual PLT entry. */
9378 value = -4;
9379 break;
31312f95 9380
13ae64f3
JJ		 9381 case BFD_RELOC_386_TLS_GD:
9382 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9383 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9384 case BFD_RELOC_386_TLS_IE:
9385 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9386 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9387 case BFD_RELOC_X86_64_TLSGD:
9388 case BFD_RELOC_X86_64_TLSLD:
9389 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9390 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9391 value = 0; /* Fully resolved at runtime. No addend. */
9392 /* Fallthrough */
9393 case BFD_RELOC_386_TLS_LE:
9394 case BFD_RELOC_386_TLS_LDO_32:
9395 case BFD_RELOC_386_TLS_LE_32:
9396 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9397 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9398 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9399 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9400 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9401 break;
9402
67a4f2b7
AO		 9403 case BFD_RELOC_386_TLS_DESC_CALL:
9404 case BFD_RELOC_X86_64_TLSDESC_CALL:
9405 value = 0; /* Fully resolved at runtime. No addend. */
9406 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9407 fixP->fx_done = 0;
9408 return;
9409
47926f60
KH		 9410 case BFD_RELOC_VTABLE_INHERIT:
9411 case BFD_RELOC_VTABLE_ENTRY:
9412 fixP->fx_done = 0;
94f592af 9413 return;
47926f60
KH		 9414
9415 default:
9416 break;
9417 }
9418#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9419 *valP = value;
f86103b7 9420#endif /* !defined (TE_Mach) */
3e73aa7c 9421
3e73aa7c 9422 /* Are we finished with this relocation now? */
c6682705 9423 if (fixP->fx_addsy == NULL)
3e73aa7c 9424 fixP->fx_done = 1;
fbeb56a4
DK		 9425#if defined (OBJ_COFF) && defined (TE_PE)
9426 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9427 {
9428 fixP->fx_done = 0;
9429 /* Remember value for tc_gen_reloc. */
9430 fixP->fx_addnumber = value;
9431 /* Clear out the frag for now. */
9432 value = 0;
9433 }
9434#endif
3e73aa7c
JH		 9435 else if (use_rela_relocations)
9436 {
9437 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9438 /* Remember value for tc_gen_reloc. */
9439 fixP->fx_addnumber = value;
3e73aa7c
JH		 9440 value = 0;
9441 }
f86103b7 9442
94f592af 9443 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9444}
252b5132 9445\f
6d4af3c2 9446const char *
499ac353 9447md_atof (int type, char *litP, int *sizeP)
252b5132 9448{
499ac353
NC		 9449 /* This outputs the LITTLENUMs in REVERSE order;
9450 in accord with the bigendian 386. */
9451 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9452}
9453\f
2d545b82 9454static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9455
252b5132 9456static char *
e3bb37b5 9457output_invalid (int c)
252b5132 9458{
3882b010 9459 if (ISPRINT (c))
f9f21a03
L		 9460 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9461 "'%c'", c);
252b5132 9462 else
f9f21a03 9463 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9464 "(0x%x)", (unsigned char) c);
252b5132
RH		 9465 return output_invalid_buf;
9466}
9467
af6bdddf 9468/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9469
9470static const reg_entry *
4d1bb795 9471parse_real_register (char *reg_string, char **end_op)
252b5132 9472{
af6bdddf
AM		 9473 char *s = reg_string;
9474 char *p;
252b5132
RH		 9475 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9476 const reg_entry *r;
9477
9478 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9479 if (*s == REGISTER_PREFIX)
9480 ++s;
9481
9482 if (is_space_char (*s))
9483 ++s;
9484
9485 p = reg_name_given;
af6bdddf 9486 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9487 {
9488 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9489 return (const reg_entry *) NULL;
9490 s++;
252b5132
RH		 9491 }
9492
6588847e
DN		 9493 /* For naked regs, make sure that we are not dealing with an identifier.
9494 This prevents confusing an identifier like `eax_var' with register
9495 `eax'. */
9496 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9497 return (const reg_entry *) NULL;
9498
af6bdddf 9499 *end_op = s;
252b5132
RH		 9500
9501 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9502
5f47d35b 9503 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9504 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9505 {
5f47d35b
AM		 9506 if (is_space_char (*s))
9507 ++s;
9508 if (*s == '(')
9509 {
af6bdddf 9510 ++s;
5f47d35b
AM		 9511 if (is_space_char (*s))
9512 ++s;
9513 if (*s >= '0' && *s <= '7')
9514 {
db557034 9515 int fpr = *s - '0';
af6bdddf 9516 ++s;
5f47d35b
AM		 9517 if (is_space_char (*s))
9518 ++s;
9519 if (*s == ')')
9520 {
9521 *end_op = s + 1;
1e9cc1c2 9522 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9523 know (r);
9524 return r + fpr;
5f47d35b 9525 }
5f47d35b 9526 }
47926f60 9527 /* We have "%st(" then garbage. */
5f47d35b
AM		 9528 return (const reg_entry *) NULL;
9529 }
9530 }
9531
a60de03c
JB		 9532 if (r == NULL || allow_pseudo_reg)
9533 return r;
9534
0dfbf9d7 9535 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9536 return (const reg_entry *) NULL;
9537
192dc9c6
JB		 9538 if ((r->reg_type.bitfield.reg32
9539 || r->reg_type.bitfield.sreg3
9540 || r->reg_type.bitfield.control
9541 || r->reg_type.bitfield.debug
9542 || r->reg_type.bitfield.test)
9543 && !cpu_arch_flags.bitfield.cpui386)
9544 return (const reg_entry *) NULL;
9545
309d3373
JB		 9546 if (r->reg_type.bitfield.floatreg
9547 && !cpu_arch_flags.bitfield.cpu8087
9548 && !cpu_arch_flags.bitfield.cpu287
9549 && !cpu_arch_flags.bitfield.cpu387)
9550 return (const reg_entry *) NULL;
9551
1848e567 9552 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9553 return (const reg_entry *) NULL;
9554
1848e567 9555 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9556 return (const reg_entry *) NULL;
9557
1848e567 9558 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9559 return (const reg_entry *) NULL;
9560
1848e567
L		 9561 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9562 return (const reg_entry *) NULL;
9563
9564 if (r->reg_type.bitfield.regmask
9565 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9566 return (const reg_entry *) NULL;
9567
db51cc60 9568 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9569 if (!allow_index_reg
db51cc60
L		 9570 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9571 return (const reg_entry *) NULL;
9572
43234a1e
L		 9573 /* Upper 16 vector register is only available with VREX in 64bit
9574 mode. */
9575 if ((r->reg_flags & RegVRex))
9576 {
9577 if (!cpu_arch_flags.bitfield.cpuvrex
9578 || flag_code != CODE_64BIT)
9579 return (const reg_entry *) NULL;
9580
9581 i.need_vrex = 1;
9582 }
9583
a60de03c
JB		 9584 if (((r->reg_flags & (RegRex64 | RegRex))
9585 || r->reg_type.bitfield.reg64)
40fb9820 9586 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9587 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9588 && flag_code != CODE_64BIT)
20f0a1fc 9589 return (const reg_entry *) NULL;
1ae00879 9590
b7240065
JB		 9591 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9592 return (const reg_entry *) NULL;
9593
252b5132
RH		 9594 return r;
9595}
4d1bb795
JB		 9596
9597/* REG_STRING starts *before* REGISTER_PREFIX. */
9598
9599static const reg_entry *
9600parse_register (char *reg_string, char **end_op)
9601{
9602 const reg_entry *r;
9603
9604 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9605 r = parse_real_register (reg_string, end_op);
9606 else
9607 r = NULL;
9608 if (!r)
9609 {
9610 char *save = input_line_pointer;
9611 char c;
9612 symbolS *symbolP;
9613
9614 input_line_pointer = reg_string;
d02603dc 9615 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9616 symbolP = symbol_find (reg_string);
9617 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9618 {
9619 const expressionS *e = symbol_get_value_expression (symbolP);
9620
0398aac5 9621 know (e->X_op == O_register);
4eed87de 9622 know (e->X_add_number >= 0
c3fe08fa 9623 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9624 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9625 if ((r->reg_flags & RegVRex))
9626 i.need_vrex = 1;
4d1bb795
JB		 9627 *end_op = input_line_pointer;
9628 }
9629 *input_line_pointer = c;
9630 input_line_pointer = save;
9631 }
9632 return r;
9633}
9634
9635int
9636i386_parse_name (char *name, expressionS *e, char *nextcharP)
9637{
9638 const reg_entry *r;
9639 char *end = input_line_pointer;
9640
9641 *end = *nextcharP;
9642 r = parse_register (name, &input_line_pointer);
9643 if (r && end <= input_line_pointer)
9644 {
9645 *nextcharP = *input_line_pointer;
9646 *input_line_pointer = 0;
9647 e->X_op = O_register;
9648 e->X_add_number = r - i386_regtab;
9649 return 1;
9650 }
9651 input_line_pointer = end;
9652 *end = 0;
ee86248c 9653 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9654}
9655
9656void
9657md_operand (expressionS *e)
9658{
ee86248c
JB		 9659 char *end;
9660 const reg_entry *r;
4d1bb795 9661
ee86248c
JB		 9662 switch (*input_line_pointer)
9663 {
9664 case REGISTER_PREFIX:
9665 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9666 if (r)
9667 {
9668 e->X_op = O_register;
9669 e->X_add_number = r - i386_regtab;
9670 input_line_pointer = end;
9671 }
ee86248c
JB		 9672 break;
9673
9674 case '[':
9c2799c2 9675 gas_assert (intel_syntax);
ee86248c
JB		 9676 end = input_line_pointer++;
9677 expression (e);
9678 if (*input_line_pointer == ']')
9679 {
9680 ++input_line_pointer;
9681 e->X_op_symbol = make_expr_symbol (e);
9682 e->X_add_symbol = NULL;
9683 e->X_add_number = 0;
9684 e->X_op = O_index;
9685 }
9686 else
9687 {
9688 e->X_op = O_absent;
9689 input_line_pointer = end;
9690 }
9691 break;
4d1bb795
JB		 9692 }
9693}
9694
252b5132 9695\f
4cc782b5 9696#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9697const char *md_shortopts = "kVQ:sqn";
252b5132 9698#else
12b55ccc 9699const char *md_shortopts = "qn";
252b5132 9700#endif
6e0b89ee 9701
3e73aa7c 9702#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9703#define OPTION_64 (OPTION_MD_BASE + 1)
9704#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9705#define OPTION_MARCH (OPTION_MD_BASE + 3)
9706#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9707#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9708#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9709#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9710#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9711#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9712#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9713#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9714#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9715#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9716#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9717#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9718#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9719#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9720#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9721#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9722#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9723#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9724#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9725#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9726#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9727#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9728
99ad8390
NC		 9729struct option md_longopts[] =
9730{
3e73aa7c 9731 {"32", no_argument, NULL, OPTION_32},
321098a5 9732#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9733 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9734 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9735#endif
9736#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9737 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9738 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9739#endif
b3b91714 9740 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9741 {"march", required_argument, NULL, OPTION_MARCH},
9742 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9743 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9744 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9745 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9746 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9747 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9748 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9749 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9750 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9751 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9752 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9753 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9754 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9755# if defined (TE_PE) || defined (TE_PEP)
9756 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9757#endif
d1982f93 9758 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9759 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9760 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9761 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9762 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9763 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9764 {NULL, no_argument, NULL, 0}
9765};
9766size_t md_longopts_size = sizeof (md_longopts);
9767
9768int
17b9d67d 9769md_parse_option (int c, const char *arg)
252b5132 9770{
91d6fa6a 9771 unsigned int j;
293f5f65 9772 char *arch, *next, *saved;
9103f4f4 9773
252b5132
RH		 9774 switch (c)
9775 {
12b55ccc
L		 9776 case 'n':
9777 optimize_align_code = 0;
9778 break;
9779
a38cf1db
AM		 9780 case 'q':
9781 quiet_warnings = 1;
252b5132
RH		 9782 break;
9783
9784#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9785 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9786 should be emitted or not. FIXME: Not implemented. */
9787 case 'Q':
252b5132
RH		 9788 break;
9789
9790 /* -V: SVR4 argument to print version ID. */
9791 case 'V':
9792 print_version_id ();
9793 break;
9794
a38cf1db
AM		 9795 /* -k: Ignore for FreeBSD compatibility. */
9796 case 'k':
252b5132 9797 break;
4cc782b5
ILT		 9798
9799 case 's':
9800 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9801 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9802 break;
8dcea932
L		 9803
9804 case OPTION_MSHARED:
9805 shared = 1;
9806 break;
99ad8390 9807#endif
321098a5 9808#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9809 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9810 case OPTION_64:
9811 {
9812 const char **list, **l;
9813
3e73aa7c
JH		 9814 list = bfd_target_list ();
9815 for (l = list; *l != NULL; l++)
8620418b 9816 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9817 || strcmp (*l, "coff-x86-64") == 0
9818 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9819 || strcmp (*l, "pei-x86-64") == 0
9820 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9821 {
9822 default_arch = "x86_64";
9823 break;
9824 }
3e73aa7c 9825 if (*l == NULL)
2b5d6a91 9826 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9827 free (list);
9828 }
9829 break;
9830#endif
252b5132 9831
351f65ca 9832#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9833 case OPTION_X32:
351f65ca
L		 9834 if (IS_ELF)
9835 {
9836 const char **list, **l;
9837
9838 list = bfd_target_list ();
9839 for (l = list; *l != NULL; l++)
9840 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9841 {
9842 default_arch = "x86_64:32";
9843 break;
9844 }
9845 if (*l == NULL)
2b5d6a91 9846 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9847 free (list);
9848 }
9849 else
9850 as_fatal (_("32bit x86_64 is only supported for ELF"));
9851 break;
9852#endif
9853
6e0b89ee
AM		 9854 case OPTION_32:
9855 default_arch = "i386";
9856 break;
9857
b3b91714
AM		 9858 case OPTION_DIVIDE:
9859#ifdef SVR4_COMMENT_CHARS
9860 {
9861 char *n, *t;
9862 const char *s;
9863
add39d23 9864 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 9865 t = n;
9866 for (s = i386_comment_chars; *s != '\0'; s++)
9867 if (*s != '/')
9868 *t++ = *s;
9869 *t = '\0';
9870 i386_comment_chars = n;
9871 }
9872#endif
9873 break;
9874
9103f4f4 9875 case OPTION_MARCH:
293f5f65
L		 9876 saved = xstrdup (arg);
9877 arch = saved;
9878 /* Allow -march=+nosse. */
9879 if (*arch == '+')
9880 arch++;
6305a203 9881 do
9103f4f4 9882 {
6305a203 9883 if (*arch == '.')
2b5d6a91 9884 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9885 next = strchr (arch, '+');
9886 if (next)
9887 *next++ = '\0';
91d6fa6a 9888 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9889 {
91d6fa6a 9890 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9891 {
6305a203 9892 /* Processor. */
1ded5609
JB		 9893 if (! cpu_arch[j].flags.bitfield.cpui386)
9894 continue;
9895
91d6fa6a 9896 cpu_arch_name = cpu_arch[j].name;
6305a203 9897 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9898 cpu_arch_flags = cpu_arch[j].flags;
9899 cpu_arch_isa = cpu_arch[j].type;
9900 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9901 if (!cpu_arch_tune_set)
9902 {
9903 cpu_arch_tune = cpu_arch_isa;
9904 cpu_arch_tune_flags = cpu_arch_isa_flags;
9905 }
9906 break;
9907 }
91d6fa6a
NC		 9908 else if (*cpu_arch [j].name == '.'
9909 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9910 {
9911 /* ISA entension. */
9912 i386_cpu_flags flags;
309d3373 9913
293f5f65
L		 9914 flags = cpu_flags_or (cpu_arch_flags,
9915 cpu_arch[j].flags);
81486035
L		 9916
9917 if (!valid_iamcu_cpu_flags (&flags))
9918 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9919 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9920 {
9921 if (cpu_sub_arch_name)
9922 {
9923 char *name = cpu_sub_arch_name;
9924 cpu_sub_arch_name = concat (name,
91d6fa6a 9925 cpu_arch[j].name,
1bf57e9f 9926 (const char *) NULL);
6305a203
L		 9927 free (name);
9928 }
9929 else
91d6fa6a 9930 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9931 cpu_arch_flags = flags;
a586129e 9932 cpu_arch_isa_flags = flags;
6305a203
L		 9933 }
9934 break;
ccc9c027 9935 }
9103f4f4 9936 }
6305a203 9937
293f5f65
L		 9938 if (j >= ARRAY_SIZE (cpu_arch))
9939 {
9940 /* Disable an ISA entension. */
9941 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
9942 if (strcmp (arch, cpu_noarch [j].name) == 0)
9943 {
9944 i386_cpu_flags flags;
9945
9946 flags = cpu_flags_and_not (cpu_arch_flags,
9947 cpu_noarch[j].flags);
9948 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9949 {
9950 if (cpu_sub_arch_name)
9951 {
9952 char *name = cpu_sub_arch_name;
9953 cpu_sub_arch_name = concat (arch,
9954 (const char *) NULL);
9955 free (name);
9956 }
9957 else
9958 cpu_sub_arch_name = xstrdup (arch);
9959 cpu_arch_flags = flags;
9960 cpu_arch_isa_flags = flags;
9961 }
9962 break;
9963 }
9964
9965 if (j >= ARRAY_SIZE (cpu_noarch))
9966 j = ARRAY_SIZE (cpu_arch);
9967 }
9968
91d6fa6a 9969 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9970 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9971
9972 arch = next;
9103f4f4 9973 }
293f5f65
L		 9974 while (next != NULL);
9975 free (saved);
9103f4f4
L		 9976 break;
9977
9978 case OPTION_MTUNE:
9979 if (*arg == '.')
2b5d6a91 9980 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9981 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9982 {
91d6fa6a 9983 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9984 {
ccc9c027 9985 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9986 cpu_arch_tune = cpu_arch [j].type;
9987 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9988 break;
9989 }
9990 }
91d6fa6a 9991 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9992 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9993 break;
9994
1efbbeb4
L		 9995 case OPTION_MMNEMONIC:
9996 if (strcasecmp (arg, "att") == 0)
9997 intel_mnemonic = 0;
9998 else if (strcasecmp (arg, "intel") == 0)
9999 intel_mnemonic = 1;
10000 else
2b5d6a91 10001 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10002 break;
10003
10004 case OPTION_MSYNTAX:
10005 if (strcasecmp (arg, "att") == 0)
10006 intel_syntax = 0;
10007 else if (strcasecmp (arg, "intel") == 0)
10008 intel_syntax = 1;
10009 else
2b5d6a91 10010 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10011 break;
10012
10013 case OPTION_MINDEX_REG:
10014 allow_index_reg = 1;
10015 break;
10016
10017 case OPTION_MNAKED_REG:
10018 allow_naked_reg = 1;
10019 break;
10020
10021 case OPTION_MOLD_GCC:
10022 old_gcc = 1;
1efbbeb4
L		 10023 break;
10024
c0f3af97
L		 10025 case OPTION_MSSE2AVX:
10026 sse2avx = 1;
10027 break;
10028
daf50ae7
L		 10029 case OPTION_MSSE_CHECK:
10030 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10031 sse_check = check_error;
daf50ae7 10032 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10033 sse_check = check_warning;
daf50ae7 10034 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10035 sse_check = check_none;
daf50ae7 10036 else
2b5d6a91 10037 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10038 break;
10039
7bab8ab5
JB		 10040 case OPTION_MOPERAND_CHECK:
10041 if (strcasecmp (arg, "error") == 0)
10042 operand_check = check_error;
10043 else if (strcasecmp (arg, "warning") == 0)
10044 operand_check = check_warning;
10045 else if (strcasecmp (arg, "none") == 0)
10046 operand_check = check_none;
10047 else
10048 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10049 break;
10050
539f890d
L		 10051 case OPTION_MAVXSCALAR:
10052 if (strcasecmp (arg, "128") == 0)
10053 avxscalar = vex128;
10054 else if (strcasecmp (arg, "256") == 0)
10055 avxscalar = vex256;
10056 else
2b5d6a91 10057 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10058 break;
10059
7e8b059b
L		 10060 case OPTION_MADD_BND_PREFIX:
10061 add_bnd_prefix = 1;
10062 break;
10063
43234a1e
L		 10064 case OPTION_MEVEXLIG:
10065 if (strcmp (arg, "128") == 0)
10066 evexlig = evexl128;
10067 else if (strcmp (arg, "256") == 0)
10068 evexlig = evexl256;
10069 else if (strcmp (arg, "512") == 0)
10070 evexlig = evexl512;
10071 else
10072 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10073 break;
10074
d3d3c6db
IT		 10075 case OPTION_MEVEXRCIG:
10076 if (strcmp (arg, "rne") == 0)
10077 evexrcig = rne;
10078 else if (strcmp (arg, "rd") == 0)
10079 evexrcig = rd;
10080 else if (strcmp (arg, "ru") == 0)
10081 evexrcig = ru;
10082 else if (strcmp (arg, "rz") == 0)
10083 evexrcig = rz;
10084 else
10085 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10086 break;
10087
43234a1e
L		 10088 case OPTION_MEVEXWIG:
10089 if (strcmp (arg, "0") == 0)
10090 evexwig = evexw0;
10091 else if (strcmp (arg, "1") == 0)
10092 evexwig = evexw1;
10093 else
10094 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10095 break;
10096
167ad85b
TG		 10097# if defined (TE_PE) || defined (TE_PEP)
10098 case OPTION_MBIG_OBJ:
10099 use_big_obj = 1;
10100 break;
10101#endif
10102
d1982f93 10103 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10104 if (strcasecmp (arg, "yes") == 0)
10105 omit_lock_prefix = 1;
10106 else if (strcasecmp (arg, "no") == 0)
10107 omit_lock_prefix = 0;
10108 else
10109 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10110 break;
10111
e4e00185
AS		 10112 case OPTION_MFENCE_AS_LOCK_ADD:
10113 if (strcasecmp (arg, "yes") == 0)
10114 avoid_fence = 1;
10115 else if (strcasecmp (arg, "no") == 0)
10116 avoid_fence = 0;
10117 else
10118 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10119 break;
10120
0cb4071e
L		 10121 case OPTION_MRELAX_RELOCATIONS:
10122 if (strcasecmp (arg, "yes") == 0)
10123 generate_relax_relocations = 1;
10124 else if (strcasecmp (arg, "no") == 0)
10125 generate_relax_relocations = 0;
10126 else
10127 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10128 break;
10129
5db04b09 10130 case OPTION_MAMD64:
e89c5eaa 10131 intel64 = 0;
5db04b09
L		 10132 break;
10133
10134 case OPTION_MINTEL64:
e89c5eaa 10135 intel64 = 1;
5db04b09
L		 10136 break;
10137
252b5132
RH		 10138 default:
10139 return 0;
10140 }
10141 return 1;
10142}
10143
8a2c8fef
L		 10144#define MESSAGE_TEMPLATE \
10145" "
10146
293f5f65
L		 10147static char *
10148output_message (FILE *stream, char *p, char *message, char *start,
10149 int *left_p, const char *name, int len)
10150{
10151 int size = sizeof (MESSAGE_TEMPLATE);
10152 int left = *left_p;
10153
10154 /* Reserve 2 spaces for ", " or ",\0" */
10155 left -= len + 2;
10156
10157 /* Check if there is any room. */
10158 if (left >= 0)
10159 {
10160 if (p != start)
10161 {
10162 *p++ = ',';
10163 *p++ = ' ';
10164 }
10165 p = mempcpy (p, name, len);
10166 }
10167 else
10168 {
10169 /* Output the current message now and start a new one. */
10170 *p++ = ',';
10171 *p = '\0';
10172 fprintf (stream, "%s\n", message);
10173 p = start;
10174 left = size - (start - message) - len - 2;
10175
10176 gas_assert (left >= 0);
10177
10178 p = mempcpy (p, name, len);
10179 }
10180
10181 *left_p = left;
10182 return p;
10183}
10184
8a2c8fef 10185static void
1ded5609 10186show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10187{
10188 static char message[] = MESSAGE_TEMPLATE;
10189 char *start = message + 27;
10190 char *p;
10191 int size = sizeof (MESSAGE_TEMPLATE);
10192 int left;
10193 const char *name;
10194 int len;
10195 unsigned int j;
10196
10197 p = start;
10198 left = size - (start - message);
10199 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10200 {
10201 /* Should it be skipped? */
10202 if (cpu_arch [j].skip)
10203 continue;
10204
10205 name = cpu_arch [j].name;
10206 len = cpu_arch [j].len;
10207 if (*name == '.')
10208 {
10209 /* It is an extension. Skip if we aren't asked to show it. */
10210 if (ext)
10211 {
10212 name++;
10213 len--;
10214 }
10215 else
10216 continue;
10217 }
10218 else if (ext)
10219 {
10220 /* It is an processor. Skip if we show only extension. */
10221 continue;
10222 }
1ded5609
JB		 10223 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10224 {
10225 /* It is an impossible processor - skip. */
10226 continue;
10227 }
8a2c8fef 10228
293f5f65 10229 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10230 }
10231
293f5f65
L		 10232 /* Display disabled extensions. */
10233 if (ext)
10234 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10235 {
10236 name = cpu_noarch [j].name;
10237 len = cpu_noarch [j].len;
10238 p = output_message (stream, p, message, start, &left, name,
10239 len);
10240 }
10241
8a2c8fef
L		 10242 *p = '\0';
10243 fprintf (stream, "%s\n", message);
10244}
10245
252b5132 10246void
8a2c8fef 10247md_show_usage (FILE *stream)
252b5132 10248{
4cc782b5
ILT		 10249#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10250 fprintf (stream, _("\
a38cf1db
AM		 10251 -Q ignored\n\
10252 -V print assembler version number\n\
b3b91714
AM		 10253 -k ignored\n"));
10254#endif
10255 fprintf (stream, _("\
12b55ccc 10256 -n Do not optimize code alignment\n\
b3b91714
AM		 10257 -q quieten some warnings\n"));
10258#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10259 fprintf (stream, _("\
a38cf1db 10260 -s ignored\n"));
b3b91714 10261#endif
321098a5
L		 10262#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10263 || defined (TE_PE) || defined (TE_PEP))
751d281c 10264 fprintf (stream, _("\
570561f7 10265 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10266#endif
b3b91714
AM		 10267#ifdef SVR4_COMMENT_CHARS
10268 fprintf (stream, _("\
10269 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10270#else
10271 fprintf (stream, _("\
b3b91714 10272 --divide ignored\n"));
4cc782b5 10273#endif
9103f4f4 10274 fprintf (stream, _("\
6305a203 10275 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10276 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10277 show_arch (stream, 0, 1);
8a2c8fef
L		 10278 fprintf (stream, _("\
10279 EXTENSION is combination of:\n"));
1ded5609 10280 show_arch (stream, 1, 0);
6305a203 10281 fprintf (stream, _("\
8a2c8fef 10282 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10283 show_arch (stream, 0, 0);
ba104c83 10284 fprintf (stream, _("\
c0f3af97
L		 10285 -msse2avx encode SSE instructions with VEX prefix\n"));
10286 fprintf (stream, _("\
daf50ae7
L		 10287 -msse-check=[none|error|warning]\n\
10288 check SSE instructions\n"));
10289 fprintf (stream, _("\
7bab8ab5
JB		 10290 -moperand-check=[none|error|warning]\n\
10291 check operand combinations for validity\n"));
10292 fprintf (stream, _("\
539f890d
L		 10293 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10294 length\n"));
10295 fprintf (stream, _("\
43234a1e
L		 10296 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10297 length\n"));
10298 fprintf (stream, _("\
10299 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10300 for EVEX.W bit ignored instructions\n"));
10301 fprintf (stream, _("\
d3d3c6db
IT		 10302 -mevexrcig=[rne|rd|ru|rz]\n\
10303 encode EVEX instructions with specific EVEX.RC value\n\
10304 for SAE-only ignored instructions\n"));
10305 fprintf (stream, _("\
ba104c83
L		 10306 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10307 fprintf (stream, _("\
10308 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10309 fprintf (stream, _("\
10310 -mindex-reg support pseudo index registers\n"));
10311 fprintf (stream, _("\
10312 -mnaked-reg don't require `%%' prefix for registers\n"));
10313 fprintf (stream, _("\
10314 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10315 fprintf (stream, _("\
10316 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10317 fprintf (stream, _("\
10318 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10319# if defined (TE_PE) || defined (TE_PEP)
10320 fprintf (stream, _("\
10321 -mbig-obj generate big object files\n"));
10322#endif
d022bddd
IT		 10323 fprintf (stream, _("\
10324 -momit-lock-prefix=[no|yes]\n\
10325 strip all lock prefixes\n"));
5db04b09 10326 fprintf (stream, _("\
e4e00185
AS		 10327 -mfence-as-lock-add=[no|yes]\n\
10328 encode lfence, mfence and sfence as\n\
10329 lock addl $0x0, (%%{re}sp)\n"));
10330 fprintf (stream, _("\
0cb4071e
L		 10331 -mrelax-relocations=[no|yes]\n\
10332 generate relax relocations\n"));
10333 fprintf (stream, _("\
5db04b09
L		 10334 -mamd64 accept only AMD64 ISA\n"));
10335 fprintf (stream, _("\
10336 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10337}
10338
3e73aa7c 10339#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10340 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10341 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10342
10343/* Pick the target format to use. */
10344
47926f60 10345const char *
e3bb37b5 10346i386_target_format (void)
252b5132 10347{
351f65ca
L		 10348 if (!strncmp (default_arch, "x86_64", 6))
10349 {
10350 update_code_flag (CODE_64BIT, 1);
10351 if (default_arch[6] == '\0')
7f56bc95 10352 x86_elf_abi = X86_64_ABI;
351f65ca 10353 else
7f56bc95 10354 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10355 }
3e73aa7c 10356 else if (!strcmp (default_arch, "i386"))
78f12dd3 10357 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10358 else if (!strcmp (default_arch, "iamcu"))
10359 {
10360 update_code_flag (CODE_32BIT, 1);
10361 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10362 {
10363 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10364 cpu_arch_name = "iamcu";
10365 cpu_sub_arch_name = NULL;
10366 cpu_arch_flags = iamcu_flags;
10367 cpu_arch_isa = PROCESSOR_IAMCU;
10368 cpu_arch_isa_flags = iamcu_flags;
10369 if (!cpu_arch_tune_set)
10370 {
10371 cpu_arch_tune = cpu_arch_isa;
10372 cpu_arch_tune_flags = cpu_arch_isa_flags;
10373 }
10374 }
10375 else
10376 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10377 cpu_arch_name);
10378 }
3e73aa7c 10379 else
2b5d6a91 10380 as_fatal (_("unknown architecture"));
89507696
JB		 10381
10382 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10383 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10384 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10385 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10386
252b5132
RH		 10387 switch (OUTPUT_FLAVOR)
10388 {
9384f2ff 10389#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10390 case bfd_target_aout_flavour:
47926f60 10391 return AOUT_TARGET_FORMAT;
4c63da97 10392#endif
9384f2ff
AM		 10393#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10394# if defined (TE_PE) || defined (TE_PEP)
10395 case bfd_target_coff_flavour:
167ad85b
TG		 10396 if (flag_code == CODE_64BIT)
10397 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10398 else
10399 return "pe-i386";
9384f2ff 10400# elif defined (TE_GO32)
0561d57c
JK		 10401 case bfd_target_coff_flavour:
10402 return "coff-go32";
9384f2ff 10403# else
252b5132
RH		 10404 case bfd_target_coff_flavour:
10405 return "coff-i386";
9384f2ff 10406# endif
4c63da97 10407#endif
3e73aa7c 10408#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10409 case bfd_target_elf_flavour:
3e73aa7c 10410 {
351f65ca
L		 10411 const char *format;
10412
10413 switch (x86_elf_abi)
4fa24527 10414 {
351f65ca
L		 10415 default:
10416 format = ELF_TARGET_FORMAT;
10417 break;
7f56bc95 10418 case X86_64_ABI:
351f65ca 10419 use_rela_relocations = 1;
4fa24527 10420 object_64bit = 1;
351f65ca
L		 10421 format = ELF_TARGET_FORMAT64;
10422 break;
7f56bc95 10423 case X86_64_X32_ABI:
4fa24527 10424 use_rela_relocations = 1;
351f65ca 10425 object_64bit = 1;
862be3fb 10426 disallow_64bit_reloc = 1;
351f65ca
L		 10427 format = ELF_TARGET_FORMAT32;
10428 break;
4fa24527 10429 }
3632d14b 10430 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10431 {
7f56bc95 10432 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10433 as_fatal (_("Intel L1OM is 64bit only"));
10434 return ELF_TARGET_L1OM_FORMAT;
10435 }
b49f93f6 10436 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10437 {
10438 if (x86_elf_abi != X86_64_ABI)
10439 as_fatal (_("Intel K1OM is 64bit only"));
10440 return ELF_TARGET_K1OM_FORMAT;
10441 }
81486035
L		 10442 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10443 {
10444 if (x86_elf_abi != I386_ABI)
10445 as_fatal (_("Intel MCU is 32bit only"));
10446 return ELF_TARGET_IAMCU_FORMAT;
10447 }
8a9036a4 10448 else
351f65ca 10449 return format;
3e73aa7c 10450 }
e57f8c65
TG		 10451#endif
10452#if defined (OBJ_MACH_O)
10453 case bfd_target_mach_o_flavour:
d382c579
TG		 10454 if (flag_code == CODE_64BIT)
10455 {
10456 use_rela_relocations = 1;
10457 object_64bit = 1;
10458 return "mach-o-x86-64";
10459 }
10460 else
10461 return "mach-o-i386";
4c63da97 10462#endif
252b5132
RH		 10463 default:
10464 abort ();
10465 return NULL;
10466 }
10467}
10468
47926f60 10469#endif /* OBJ_MAYBE_ more than one */
252b5132 10470\f
252b5132 10471symbolS *
7016a5d5 10472md_undefined_symbol (char *name)
252b5132 10473{
18dc2407
ILT		 10474 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10475 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10476 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10477 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10478 {
10479 if (!GOT_symbol)
10480 {
10481 if (symbol_find (name))
10482 as_bad (_("GOT already in symbol table"));
10483 GOT_symbol = symbol_new (name, undefined_section,
10484 (valueT) 0, &zero_address_frag);
10485 };
10486 return GOT_symbol;
10487 }
252b5132
RH		 10488 return 0;
10489}
10490
10491/* Round up a section size to the appropriate boundary. */
47926f60 10492
252b5132 10493valueT
7016a5d5 10494md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10495{
4c63da97
AM		 10496#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10497 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10498 {
10499 /* For a.out, force the section size to be aligned. If we don't do
10500 this, BFD will align it for us, but it will not write out the
10501 final bytes of the section. This may be a bug in BFD, but it is
10502 easier to fix it here since that is how the other a.out targets
10503 work. */
10504 int align;
10505
10506 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10507 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10508 }
252b5132
RH		 10509#endif
10510
10511 return size;
10512}
10513
10514/* On the i386, PC-relative offsets are relative to the start of the
10515 next instruction. That is, the address of the offset, plus its
10516 size, since the offset is always the last part of the insn. */
10517
10518long
e3bb37b5 10519md_pcrel_from (fixS *fixP)
252b5132
RH		 10520{
10521 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10522}
10523
10524#ifndef I386COFF
10525
10526static void
e3bb37b5 10527s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10528{
29b0f896 10529 int temp;
252b5132 10530
8a75718c
JB		 10531#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10532 if (IS_ELF)
10533 obj_elf_section_change_hook ();
10534#endif
252b5132
RH		 10535 temp = get_absolute_expression ();
10536 subseg_set (bss_section, (subsegT) temp);
10537 demand_empty_rest_of_line ();
10538}
10539
10540#endif
10541
252b5132 10542void
e3bb37b5 10543i386_validate_fix (fixS *fixp)
252b5132 10544{
02a86693 10545 if (fixp->fx_subsy)
252b5132 10546 {
02a86693 10547 if (fixp->fx_subsy == GOT_symbol)
23df1078 10548 {
02a86693
L		 10549 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10550 {
10551 if (!object_64bit)
10552 abort ();
10553#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10554 if (fixp->fx_tcbit2)
56ceb5b5
L		 10555 fixp->fx_r_type = (fixp->fx_tcbit
10556 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10557 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10558 else
10559#endif
10560 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10561 }
d6ab8113 10562 else
02a86693
L		 10563 {
10564 if (!object_64bit)
10565 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10566 else
10567 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10568 }
10569 fixp->fx_subsy = 0;
23df1078 10570 }
252b5132 10571 }
02a86693
L		 10572#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10573 else if (!object_64bit)
10574 {
10575 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10576 && fixp->fx_tcbit2)
10577 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10578 }
10579#endif
252b5132
RH		 10580}
10581
252b5132 10582arelent *
7016a5d5 10583tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10584{
10585 arelent *rel;
10586 bfd_reloc_code_real_type code;
10587
10588 switch (fixp->fx_r_type)
10589 {
8ce3d284 10590#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10591 case BFD_RELOC_SIZE32:
10592 case BFD_RELOC_SIZE64:
10593 if (S_IS_DEFINED (fixp->fx_addsy)
10594 && !S_IS_EXTERNAL (fixp->fx_addsy))
10595 {
10596 /* Resolve size relocation against local symbol to size of
10597 the symbol plus addend. */
10598 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10599 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10600 && !fits_in_unsigned_long (value))
10601 as_bad_where (fixp->fx_file, fixp->fx_line,
10602 _("symbol size computation overflow"));
10603 fixp->fx_addsy = NULL;
10604 fixp->fx_subsy = NULL;
10605 md_apply_fix (fixp, (valueT *) &value, NULL);
10606 return NULL;
10607 }
8ce3d284 10608#endif
8fd4256d 10609
3e73aa7c
JH		 10610 case BFD_RELOC_X86_64_PLT32:
10611 case BFD_RELOC_X86_64_GOT32:
10612 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10613 case BFD_RELOC_X86_64_GOTPCRELX:
10614 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10615 case BFD_RELOC_386_PLT32:
10616 case BFD_RELOC_386_GOT32:
02a86693 10617 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10618 case BFD_RELOC_386_GOTOFF:
10619 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10620 case BFD_RELOC_386_TLS_GD:
10621 case BFD_RELOC_386_TLS_LDM:
10622 case BFD_RELOC_386_TLS_LDO_32:
10623 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10624 case BFD_RELOC_386_TLS_IE:
10625 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10626 case BFD_RELOC_386_TLS_LE_32:
10627 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10628 case BFD_RELOC_386_TLS_GOTDESC:
10629 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10630 case BFD_RELOC_X86_64_TLSGD:
10631 case BFD_RELOC_X86_64_TLSLD:
10632 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10633 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10634 case BFD_RELOC_X86_64_GOTTPOFF:
10635 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10636 case BFD_RELOC_X86_64_TPOFF64:
10637 case BFD_RELOC_X86_64_GOTOFF64:
10638 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10639 case BFD_RELOC_X86_64_GOT64:
10640 case BFD_RELOC_X86_64_GOTPCREL64:
10641 case BFD_RELOC_X86_64_GOTPC64:
10642 case BFD_RELOC_X86_64_GOTPLT64:
10643 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10644 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10645 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10646 case BFD_RELOC_RVA:
10647 case BFD_RELOC_VTABLE_ENTRY:
10648 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10649#ifdef TE_PE
10650 case BFD_RELOC_32_SECREL:
10651#endif
252b5132
RH		 10652 code = fixp->fx_r_type;
10653 break;
dbbaec26
L		 10654 case BFD_RELOC_X86_64_32S:
10655 if (!fixp->fx_pcrel)
10656 {
10657 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10658 code = fixp->fx_r_type;
10659 break;
10660 }
252b5132 10661 default:
93382f6d 10662 if (fixp->fx_pcrel)
252b5132 10663 {
93382f6d
AM		 10664 switch (fixp->fx_size)
10665 {
10666 default:
b091f402
AM		 10667 as_bad_where (fixp->fx_file, fixp->fx_line,
10668 _("can not do %d byte pc-relative relocation"),
10669 fixp->fx_size);
93382f6d
AM		 10670 code = BFD_RELOC_32_PCREL;
10671 break;
10672 case 1: code = BFD_RELOC_8_PCREL; break;
10673 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10674 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10675#ifdef BFD64
10676 case 8: code = BFD_RELOC_64_PCREL; break;
10677#endif
93382f6d
AM		 10678 }
10679 }
10680 else
10681 {
10682 switch (fixp->fx_size)
10683 {
10684 default:
b091f402
AM		 10685 as_bad_where (fixp->fx_file, fixp->fx_line,
10686 _("can not do %d byte relocation"),
10687 fixp->fx_size);
93382f6d
AM		 10688 code = BFD_RELOC_32;
10689 break;
10690 case 1: code = BFD_RELOC_8; break;
10691 case 2: code = BFD_RELOC_16; break;
10692 case 4: code = BFD_RELOC_32; break;
937149dd 10693#ifdef BFD64
3e73aa7c 10694 case 8: code = BFD_RELOC_64; break;
937149dd 10695#endif
93382f6d 10696 }
252b5132
RH		 10697 }
10698 break;
10699 }
252b5132 10700
d182319b
JB		 10701 if ((code == BFD_RELOC_32
10702 || code == BFD_RELOC_32_PCREL
10703 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10704 && GOT_symbol
10705 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10706 {
4fa24527 10707 if (!object_64bit)
d6ab8113
JB		 10708 code = BFD_RELOC_386_GOTPC;
10709 else
10710 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10711 }
7b81dfbb
AJ		 10712 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10713 && GOT_symbol
10714 && fixp->fx_addsy == GOT_symbol)
10715 {
10716 code = BFD_RELOC_X86_64_GOTPC64;
10717 }
252b5132 10718
add39d23
TS		 10719 rel = XNEW (arelent);
10720 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10721 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10722
10723 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10724
3e73aa7c
JH		 10725 if (!use_rela_relocations)
10726 {
10727 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10728 vtable entry to be used in the relocation's section offset. */
10729 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10730 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10731#if defined (OBJ_COFF) && defined (TE_PE)
10732 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10733 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10734 else
10735#endif
c6682705 10736 rel->addend = 0;
3e73aa7c
JH		 10737 }
10738 /* Use the rela in 64bit mode. */
252b5132 10739 else
3e73aa7c 10740 {
862be3fb
L		 10741 if (disallow_64bit_reloc)
10742 switch (code)
10743 {
862be3fb
L		 10744 case BFD_RELOC_X86_64_DTPOFF64:
10745 case BFD_RELOC_X86_64_TPOFF64:
10746 case BFD_RELOC_64_PCREL:
10747 case BFD_RELOC_X86_64_GOTOFF64:
10748 case BFD_RELOC_X86_64_GOT64:
10749 case BFD_RELOC_X86_64_GOTPCREL64:
10750 case BFD_RELOC_X86_64_GOTPC64:
10751 case BFD_RELOC_X86_64_GOTPLT64:
10752 case BFD_RELOC_X86_64_PLTOFF64:
10753 as_bad_where (fixp->fx_file, fixp->fx_line,
10754 _("cannot represent relocation type %s in x32 mode"),
10755 bfd_get_reloc_code_name (code));
10756 break;
10757 default:
10758 break;
10759 }
10760
062cd5e7
AS		 10761 if (!fixp->fx_pcrel)
10762 rel->addend = fixp->fx_offset;
10763 else
10764 switch (code)
10765 {
10766 case BFD_RELOC_X86_64_PLT32:
10767 case BFD_RELOC_X86_64_GOT32:
10768 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10769 case BFD_RELOC_X86_64_GOTPCRELX:
10770 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10771 case BFD_RELOC_X86_64_TLSGD:
10772 case BFD_RELOC_X86_64_TLSLD:
10773 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10774 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10775 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10776 rel->addend = fixp->fx_offset - fixp->fx_size;
10777 break;
10778 default:
10779 rel->addend = (section->vma
10780 - fixp->fx_size
10781 + fixp->fx_addnumber
10782 + md_pcrel_from (fixp));
10783 break;
10784 }
3e73aa7c
JH		 10785 }
10786
252b5132
RH		 10787 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10788 if (rel->howto == NULL)
10789 {
10790 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10791 _("cannot represent relocation type %s"),
252b5132
RH		 10792 bfd_get_reloc_code_name (code));
10793 /* Set howto to a garbage value so that we can keep going. */
10794 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10795 gas_assert (rel->howto != NULL);
252b5132
RH		 10796 }
10797
10798 return rel;
10799}
10800
ee86248c 10801#include "tc-i386-intel.c"
54cfded0 10802
a60de03c
JB		 10803void
10804tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10805{
a60de03c
JB		 10806 int saved_naked_reg;
10807 char saved_register_dot;
54cfded0 10808
a60de03c
JB		 10809 saved_naked_reg = allow_naked_reg;
10810 allow_naked_reg = 1;
10811 saved_register_dot = register_chars['.'];
10812 register_chars['.'] = '.';
10813 allow_pseudo_reg = 1;
10814 expression_and_evaluate (exp);
10815 allow_pseudo_reg = 0;
10816 register_chars['.'] = saved_register_dot;
10817 allow_naked_reg = saved_naked_reg;
10818
e96d56a1 10819 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10820 {
a60de03c
JB		 10821 if ((addressT) exp->X_add_number < i386_regtab_size)
10822 {
10823 exp->X_op = O_constant;
10824 exp->X_add_number = i386_regtab[exp->X_add_number]
10825 .dw2_regnum[flag_code >> 1];
10826 }
10827 else
10828 exp->X_op = O_illegal;
54cfded0 10829 }
54cfded0
AM		 10830}
10831
10832void
10833tc_x86_frame_initial_instructions (void)
10834{
a60de03c
JB		 10835 static unsigned int sp_regno[2];
10836
10837 if (!sp_regno[flag_code >> 1])
10838 {
10839 char *saved_input = input_line_pointer;
10840 char sp[][4] = {"esp", "rsp"};
10841 expressionS exp;
a4447b93 10842
a60de03c
JB		 10843 input_line_pointer = sp[flag_code >> 1];
10844 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10845 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10846 sp_regno[flag_code >> 1] = exp.X_add_number;
10847 input_line_pointer = saved_input;
10848 }
a4447b93 10849
61ff971f
L		 10850 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10851 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10852}
d2b2c203 10853
d7921315
L		 10854int
10855x86_dwarf2_addr_size (void)
10856{
10857#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10858 if (x86_elf_abi == X86_64_X32_ABI)
10859 return 4;
10860#endif
10861 return bfd_arch_bits_per_address (stdoutput) / 8;
10862}
10863
d2b2c203
DJ		 10864int
10865i386_elf_section_type (const char *str, size_t len)
10866{
10867 if (flag_code == CODE_64BIT
10868 && len == sizeof ("unwind") - 1
10869 && strncmp (str, "unwind", 6) == 0)
10870 return SHT_X86_64_UNWIND;
10871
10872 return -1;
10873}
bb41ade5 10874
ad5fec3b
EB		 10875#ifdef TE_SOLARIS
10876void
10877i386_solaris_fix_up_eh_frame (segT sec)
10878{
10879 if (flag_code == CODE_64BIT)
10880 elf_section_type (sec) = SHT_X86_64_UNWIND;
10881}
10882#endif
10883
bb41ade5
AM		 10884#ifdef TE_PE
10885void
10886tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10887{
91d6fa6a 10888 expressionS exp;
bb41ade5 10889
91d6fa6a
NC		 10890 exp.X_op = O_secrel;
10891 exp.X_add_symbol = symbol;
10892 exp.X_add_number = 0;
10893 emit_expr (&exp, size);
bb41ade5
AM		 10894}
10895#endif
3b22753a
L		 10896
10897#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10898/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10899
01e1a5bc 10900bfd_vma
6d4af3c2 10901x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 10902{
10903 if (flag_code == CODE_64BIT)
10904 {
10905 if (letter == 'l')
10906 return SHF_X86_64_LARGE;
10907
8f3bae45 10908 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10909 }
3b22753a 10910 else
8f3bae45 10911 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10912 return -1;
10913}
10914
01e1a5bc 10915bfd_vma
3b22753a
L		 10916x86_64_section_word (char *str, size_t len)
10917{
8620418b 10918 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10919 return SHF_X86_64_LARGE;
10920
10921 return -1;
10922}
10923
10924static void
10925handle_large_common (int small ATTRIBUTE_UNUSED)
10926{
10927 if (flag_code != CODE_64BIT)
10928 {
10929 s_comm_internal (0, elf_common_parse);
10930 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10931 }
10932 else
10933 {
10934 static segT lbss_section;
10935 asection *saved_com_section_ptr = elf_com_section_ptr;
10936 asection *saved_bss_section = bss_section;
10937
10938 if (lbss_section == NULL)
10939 {
10940 flagword applicable;
10941 segT seg = now_seg;
10942 subsegT subseg = now_subseg;
10943
10944 /* The .lbss section is for local .largecomm symbols. */
10945 lbss_section = subseg_new (".lbss", 0);
10946 applicable = bfd_applicable_section_flags (stdoutput);
10947 bfd_set_section_flags (stdoutput, lbss_section,
10948 applicable & SEC_ALLOC);
10949 seg_info (lbss_section)->bss = 1;
10950
10951 subseg_set (seg, subseg);
10952 }
10953
10954 elf_com_section_ptr = &_bfd_elf_large_com_section;
10955 bss_section = lbss_section;
10956
10957 s_comm_internal (0, elf_common_parse);
10958
10959 elf_com_section_ptr = saved_com_section_ptr;
10960 bss_section = saved_bss_section;
10961 }
10962}
10963#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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