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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579
TG		 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
4 2012
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d 68#define REP_PREFIX 4
42164a71 69#define HLE_PREFIX REP_PREFIX
c32fa91d
L		 70#define LOCK_PREFIX 5
71#define REX_PREFIX 6 /* must come last. */
72#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 73
74/* we define the syntax here (modulo base,index,scale syntax) */
75#define REGISTER_PREFIX '%'
76#define IMMEDIATE_PREFIX '$'
77#define ABSOLUTE_PREFIX '*'
78
79/* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81#define WORD_MNEM_SUFFIX 'w'
82#define BYTE_MNEM_SUFFIX 'b'
83#define SHORT_MNEM_SUFFIX 's'
84#define LONG_MNEM_SUFFIX 'l'
85#define QWORD_MNEM_SUFFIX 'q'
86#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 87#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 88/* Intel Syntax. Use a non-ascii letter since since it never appears
89 in instructions. */
90#define LONG_DOUBLE_MNEM_SUFFIX '\1'
91
92#define END_OF_INSN '\0'
93
94/*
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
99 END.
100 */
101typedef struct
102{
d3ce72d0
NC		 103 const insn_template *start;
104 const insn_template *end;
6305a203
L		 105}
106templates;
107
108/* 386 operand encoding bytes: see 386 book for details of this. */
109typedef struct
110{
111 unsigned int regmem; /* codes register or memory operand */
112 unsigned int reg; /* codes register operand (or extended opcode) */
113 unsigned int mode; /* how to interpret regmem & reg */
114}
115modrm_byte;
116
117/* x86-64 extension prefix. */
118typedef int rex_byte;
119
6305a203
L		 120/* 386 opcode byte to code indirect addressing. */
121typedef struct
122{
123 unsigned base;
124 unsigned index;
125 unsigned scale;
126}
127sib_byte;
128
6305a203
L		 129/* x86 arch names, types and features */
130typedef struct
131{
132 const char *name; /* arch name */
8a2c8fef 133 unsigned int len; /* arch string length */
6305a203
L		 134 enum processor_type type; /* arch type */
135 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 136 unsigned int skip; /* show_arch should skip this. */
22109423 137 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 138}
139arch_entry;
140
78f12dd3 141static void update_code_flag (int, int);
e3bb37b5
L		 142static void set_code_flag (int);
143static void set_16bit_gcc_code_flag (int);
144static void set_intel_syntax (int);
1efbbeb4 145static void set_intel_mnemonic (int);
db51cc60 146static void set_allow_index_reg (int);
7bab8ab5 147static void set_check (int);
e3bb37b5 148static void set_cpu_arch (int);
6482c264 149#ifdef TE_PE
e3bb37b5 150static void pe_directive_secrel (int);
6482c264 151#endif
e3bb37b5
L		 152static void signed_cons (int);
153static char *output_invalid (int c);
ee86248c
JB		 154static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
155 const char *);
156static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
157 const char *);
a7619375 158static int i386_att_operand (char *);
e3bb37b5 159static int i386_intel_operand (char *, int);
ee86248c
JB		 160static int i386_intel_simplify (expressionS *);
161static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 162static const reg_entry *parse_register (char *, char **);
163static char *parse_insn (char *, char *);
164static char *parse_operands (char *, const char *);
165static void swap_operands (void);
4d456e3d 166static void swap_2_operands (int, int);
e3bb37b5
L		 167static void optimize_imm (void);
168static void optimize_disp (void);
d3ce72d0 169static const insn_template *match_template (void);
e3bb37b5
L		 170static int check_string (void);
171static int process_suffix (void);
172static int check_byte_reg (void);
173static int check_long_reg (void);
174static int check_qword_reg (void);
175static int check_word_reg (void);
176static int finalize_imm (void);
177static int process_operands (void);
178static const seg_entry *build_modrm_byte (void);
179static void output_insn (void);
180static void output_imm (fragS *, offsetT);
181static void output_disp (fragS *, offsetT);
29b0f896 182#ifndef I386COFF
e3bb37b5 183static void s_bss (int);
252b5132 184#endif
17d4e2a2
L		 185#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186static void handle_large_common (int small ATTRIBUTE_UNUSED);
187#endif
252b5132 188
a847613f 189static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 190
c0f3af97
L		 191/* VEX prefix. */
192typedef struct
193{
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes[3];
196 unsigned int length;
197 /* Destination or source register specifier. */
198 const reg_entry *register_specifier;
199} vex_prefix;
200
252b5132 201/* 'md_assemble ()' gathers together information and puts it into a
47926f60 202 i386_insn. */
252b5132 203
520dc8e8
AM		 204union i386_op
205 {
206 expressionS *disps;
207 expressionS *imms;
208 const reg_entry *regs;
209 };
210
a65babc9
L		 211enum i386_error
212 {
86e026a4 213 operand_size_mismatch,
a65babc9
L		 214 operand_type_mismatch,
215 register_type_mismatch,
216 number_of_operands_mismatch,
217 invalid_instruction_suffix,
218 bad_imm4,
219 old_gcc_only,
220 unsupported_with_intel_mnemonic,
221 unsupported_syntax,
6c30d220
L		 222 unsupported,
223 invalid_vsib_address,
7bab8ab5 224 invalid_vector_register_set,
6c30d220 225 unsupported_vector_index_register
a65babc9
L		 226 };
227
252b5132
RH		 228struct _i386_insn
229 {
47926f60 230 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 231 insn_template tm;
252b5132 232
7d5e4556
L		 233 /* SUFFIX holds the instruction size suffix for byte, word, dword
234 or qword, if given. */
252b5132
RH		 235 char suffix;
236
47926f60 237 /* OPERANDS gives the number of given operands. */
252b5132
RH		 238 unsigned int operands;
239
240 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
241 of given register, displacement, memory operands and immediate
47926f60 242 operands. */
252b5132
RH		 243 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
244
245 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 246 use OP[i] for the corresponding operand. */
40fb9820 247 i386_operand_type types[MAX_OPERANDS];
252b5132 248
520dc8e8
AM		 249 /* Displacement expression, immediate expression, or register for each
250 operand. */
251 union i386_op op[MAX_OPERANDS];
252b5132 252
3e73aa7c
JH		 253 /* Flags for operands. */
254 unsigned int flags[MAX_OPERANDS];
255#define Operand_PCrel 1
256
252b5132 257 /* Relocation type for operand */
f86103b7 258 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 259
252b5132
RH		 260 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
261 the base index byte below. */
262 const reg_entry *base_reg;
263 const reg_entry *index_reg;
264 unsigned int log2_scale_factor;
265
266 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 267 explicit segment overrides are given. */
ce8a8b2f 268 const seg_entry *seg[2];
252b5132
RH		 269
270 /* PREFIX holds all the given prefix opcodes (usually null).
271 PREFIXES is the number of prefix opcodes. */
272 unsigned int prefixes;
273 unsigned char prefix[MAX_PREFIXES];
274
275 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 276 addressing modes of this insn are encoded. */
252b5132 277 modrm_byte rm;
3e73aa7c 278 rex_byte rex;
252b5132 279 sib_byte sib;
c0f3af97 280 vex_prefix vex;
b6169b20
L		 281
282 /* Swap operand in encoding. */
4473e004 283 unsigned int swap_operand;
891edac4 284
a501d77e
L		 285 /* Prefer 8bit or 32bit displacement in encoding. */
286 enum
287 {
288 disp_encoding_default = 0,
289 disp_encoding_8bit,
290 disp_encoding_32bit
291 } disp_encoding;
f8a5c266 292
42164a71
L		 293 /* Have HLE prefix. */
294 unsigned int have_hle;
295
891edac4 296 /* Error message. */
a65babc9 297 enum i386_error error;
252b5132
RH		 298 };
299
300typedef struct _i386_insn i386_insn;
301
302/* List of chars besides those in app.c:symbol_chars that can start an
303 operand. Used to prevent the scrubber eating vital white-space. */
32137342 304const char extra_symbol_chars[] = "*%-(["
252b5132 305#ifdef LEX_AT
32137342
NC		 306 "@"
307#endif
308#ifdef LEX_QM
309 "?"
252b5132 310#endif
32137342 311 ;
252b5132 312
29b0f896
AM		 313#if (defined (TE_I386AIX) \
314 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 315 && !defined (TE_GNU) \
29b0f896 316 && !defined (TE_LINUX) \
8d63c93e
RM		 317 && !defined (TE_NACL) \
318 && !defined (TE_NETWARE) \
29b0f896 319 && !defined (TE_FreeBSD) \
5b806d27 320 && !defined (TE_DragonFly) \
29b0f896 321 && !defined (TE_NetBSD)))
252b5132 322/* This array holds the chars that always start a comment. If the
b3b91714
AM		 323 pre-processor is disabled, these aren't very useful. The option
324 --divide will remove '/' from this list. */
325const char *i386_comment_chars = "#/";
326#define SVR4_COMMENT_CHARS 1
252b5132 327#define PREFIX_SEPARATOR '\\'
252b5132 328
b3b91714
AM		 329#else
330const char *i386_comment_chars = "#";
331#define PREFIX_SEPARATOR '/'
332#endif
333
252b5132
RH		 334/* This array holds the chars that only start a comment at the beginning of
335 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 336 .line and .file directives will appear in the pre-processed output.
337 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 338 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 339 #NO_APP at the beginning of its output.
340 Also note that comments started like this one will always work if
252b5132 341 '/' isn't otherwise defined. */
b3b91714 342const char line_comment_chars[] = "#/";
252b5132 343
63a0b638 344const char line_separator_chars[] = ";";
252b5132 345
ce8a8b2f
AM		 346/* Chars that can be used to separate mant from exp in floating point
347 nums. */
252b5132
RH		 348const char EXP_CHARS[] = "eE";
349
ce8a8b2f
AM		 350/* Chars that mean this number is a floating point constant
351 As in 0f12.456
352 or 0d1.2345e12. */
252b5132
RH		 353const char FLT_CHARS[] = "fFdDxX";
354
ce8a8b2f 355/* Tables for lexical analysis. */
252b5132
RH		 356static char mnemonic_chars[256];
357static char register_chars[256];
358static char operand_chars[256];
359static char identifier_chars[256];
360static char digit_chars[256];
361
ce8a8b2f 362/* Lexical macros. */
252b5132
RH		 363#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
364#define is_operand_char(x) (operand_chars[(unsigned char) x])
365#define is_register_char(x) (register_chars[(unsigned char) x])
366#define is_space_char(x) ((x) == ' ')
367#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
368#define is_digit_char(x) (digit_chars[(unsigned char) x])
369
0234cb7c 370/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 371static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
372
373/* md_assemble() always leaves the strings it's passed unaltered. To
374 effect this we maintain a stack of saved characters that we've smashed
375 with '\0's (indicating end of strings for various sub-fields of the
47926f60 376 assembler instruction). */
252b5132 377static char save_stack[32];
ce8a8b2f 378static char *save_stack_p;
252b5132
RH		 379#define END_STRING_AND_SAVE(s) \
380 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
381#define RESTORE_END_STRING(s) \
382 do { *(s) = *--save_stack_p; } while (0)
383
47926f60 384/* The instruction we're assembling. */
252b5132
RH		 385static i386_insn i;
386
387/* Possible templates for current insn. */
388static const templates *current_templates;
389
31b2323c
L		 390/* Per instruction expressionS buffers: max displacements & immediates. */
391static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
392static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 393
47926f60 394/* Current operand we are working on. */
ee86248c 395static int this_operand = -1;
252b5132 396
3e73aa7c
JH		 397/* We support four different modes. FLAG_CODE variable is used to distinguish
398 these. */
399
400enum flag_code {
401 CODE_32BIT,
402 CODE_16BIT,
403 CODE_64BIT };
404
405static enum flag_code flag_code;
4fa24527 406static unsigned int object_64bit;
862be3fb 407static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 408static int use_rela_relocations = 0;
409
7af8ed2d
NC		 410#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
411 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
412 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
413
351f65ca
L		 414/* The ELF ABI to use. */
415enum x86_elf_abi
416{
417 I386_ABI,
7f56bc95
L		 418 X86_64_ABI,
419 X86_64_X32_ABI
351f65ca
L		 420};
421
422static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 423#endif
351f65ca 424
3e73aa7c 425/* The names used to print error messages. */
b77a7acd 426static const char *flag_code_names[] =
3e73aa7c
JH		 427 {
428 "32",
429 "16",
430 "64"
431 };
252b5132 432
47926f60
KH		 433/* 1 for intel syntax,
434 0 if att syntax. */
435static int intel_syntax = 0;
252b5132 436
1efbbeb4
L		 437/* 1 for intel mnemonic,
438 0 if att mnemonic. */
439static int intel_mnemonic = !SYSV386_COMPAT;
440
5209009a 441/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 442static int old_gcc = OLDGCC_COMPAT;
443
a60de03c
JB		 444/* 1 if pseudo registers are permitted. */
445static int allow_pseudo_reg = 0;
446
47926f60
KH		 447/* 1 if register prefix % not required. */
448static int allow_naked_reg = 0;
252b5132 449
ba104c83 450/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 451static int allow_index_reg = 0;
452
7bab8ab5 453static enum check_kind
daf50ae7 454 {
7bab8ab5
JB		 455 check_none = 0,
456 check_warning,
457 check_error
daf50ae7 458 }
7bab8ab5 459sse_check, operand_check = check_warning;
daf50ae7 460
2ca3ace5
L		 461/* Register prefix used for error message. */
462static const char *register_prefix = "%";
463
47926f60
KH		 464/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
465 leave, push, and pop instructions so that gcc has the same stack
466 frame as in 32 bit mode. */
467static char stackop_size = '\0';
eecb386c 468
12b55ccc
L		 469/* Non-zero to optimize code alignment. */
470int optimize_align_code = 1;
471
47926f60
KH		 472/* Non-zero to quieten some warnings. */
473static int quiet_warnings = 0;
a38cf1db 474
47926f60
KH		 475/* CPU name. */
476static const char *cpu_arch_name = NULL;
6305a203 477static char *cpu_sub_arch_name = NULL;
a38cf1db 478
47926f60 479/* CPU feature flags. */
40fb9820
L		 480static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
481
ccc9c027
L		 482/* If we have selected a cpu we are generating instructions for. */
483static int cpu_arch_tune_set = 0;
484
9103f4f4 485/* Cpu we are generating instructions for. */
fbf3f584 486enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 487
488/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 489static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 490
ccc9c027 491/* CPU instruction set architecture used. */
fbf3f584 492enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 493
9103f4f4 494/* CPU feature flags of instruction set architecture used. */
fbf3f584 495i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 496
fddf5b5b
AM		 497/* If set, conditional jumps are not automatically promoted to handle
498 larger than a byte offset. */
499static unsigned int no_cond_jump_promotion = 0;
500
c0f3af97
L		 501/* Encode SSE instructions with VEX prefix. */
502static unsigned int sse2avx;
503
539f890d
L		 504/* Encode scalar AVX instructions with specific vector length. */
505static enum
506 {
507 vex128 = 0,
508 vex256
509 } avxscalar;
510
29b0f896 511/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 512static symbolS *GOT_symbol;
29b0f896 513
a4447b93
RH		 514/* The dwarf2 return column, adjusted for 32 or 64 bit. */
515unsigned int x86_dwarf2_return_column;
516
517/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
518int x86_cie_data_alignment;
519
252b5132 520/* Interface to relax_segment.
fddf5b5b
AM		 521 There are 3 major relax states for 386 jump insns because the
522 different types of jumps add different sizes to frags when we're
523 figuring out what sort of jump to choose to reach a given label. */
252b5132 524
47926f60 525/* Types. */
93c2a809
AM		 526#define UNCOND_JUMP 0
527#define COND_JUMP 1
528#define COND_JUMP86 2
fddf5b5b 529
47926f60 530/* Sizes. */
252b5132
RH		 531#define CODE16 1
532#define SMALL 0
29b0f896 533#define SMALL16 (SMALL | CODE16)
252b5132 534#define BIG 2
29b0f896 535#define BIG16 (BIG | CODE16)
252b5132
RH		 536
537#ifndef INLINE
538#ifdef __GNUC__
539#define INLINE __inline__
540#else
541#define INLINE
542#endif
543#endif
544
fddf5b5b
AM		 545#define ENCODE_RELAX_STATE(type, size) \
546 ((relax_substateT) (((type) << 2) | (size)))
547#define TYPE_FROM_RELAX_STATE(s) \
548 ((s) >> 2)
549#define DISP_SIZE_FROM_RELAX_STATE(s) \
550 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 551
552/* This table is used by relax_frag to promote short jumps to long
553 ones where necessary. SMALL (short) jumps may be promoted to BIG
554 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
555 don't allow a short jump in a 32 bit code segment to be promoted to
556 a 16 bit offset jump because it's slower (requires data size
557 prefix), and doesn't work, unless the destination is in the bottom
558 64k of the code segment (The top 16 bits of eip are zeroed). */
559
560const relax_typeS md_relax_table[] =
561{
24eab124
AM		 562 /* The fields are:
563 1) most positive reach of this state,
564 2) most negative reach of this state,
93c2a809 565 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 566 4) which index into the table to try if we can't fit into this one. */
252b5132 567
fddf5b5b 568 /* UNCOND_JUMP states. */
93c2a809
AM		 569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
570 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
571 /* dword jmp adds 4 bytes to frag:
572 0 extra opcode bytes, 4 displacement bytes. */
252b5132 573 {0, 0, 4, 0},
93c2a809
AM		 574 /* word jmp adds 2 byte2 to frag:
575 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 576 {0, 0, 2, 0},
577
93c2a809
AM		 578 /* COND_JUMP states. */
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
580 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
581 /* dword conditionals adds 5 bytes to frag:
582 1 extra opcode byte, 4 displacement bytes. */
583 {0, 0, 5, 0},
fddf5b5b 584 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 585 1 extra opcode byte, 2 displacement bytes. */
586 {0, 0, 3, 0},
587
588 /* COND_JUMP86 states. */
589 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
590 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
591 /* dword conditionals adds 5 bytes to frag:
592 1 extra opcode byte, 4 displacement bytes. */
593 {0, 0, 5, 0},
594 /* word conditionals add 4 bytes to frag:
595 1 displacement byte and a 3 byte long branch insn. */
596 {0, 0, 4, 0}
252b5132
RH		 597};
598
9103f4f4
L		 599static const arch_entry cpu_arch[] =
600{
89507696
JB		 601 /* Do not replace the first two entries - i386_target_format()
602 relies on them being there in this order. */
8a2c8fef 603 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 604 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 605 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 606 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 607 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 608 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 609 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 610 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 611 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 612 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 613 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 614 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 615 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 616 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 617 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 618 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 619 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 620 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 621 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 622 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 623 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 624 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 625 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 626 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 627 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 628 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 629 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 630 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 631 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 632 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 633 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 634 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 635 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 636 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 637 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 638 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 639 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 640 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 641 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 642 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 643 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 644 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 645 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 646 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 647 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
648 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 649 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 650 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 651 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 652 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 653 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 654 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 655 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 656 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 657 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 658 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 659 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 660 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 661 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 662 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 663 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 664 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 665 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 666 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 667 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
668 CPU_BDVER3_FLAGS, 0, 0 },
7b458c12
L		 669 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
670 CPU_BTVER1_FLAGS, 0, 0 },
671 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
672 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 673 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 674 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 675 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 676 CPU_287_FLAGS, 0, 0 },
8a2c8fef 677 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 678 CPU_387_FLAGS, 0, 0 },
8a2c8fef 679 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 680 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 681 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 682 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 683 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 684 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 685 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 686 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 687 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 688 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 689 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 690 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 691 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 692 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 693 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 694 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 695 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 696 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 697 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 698 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 699 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 700 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 701 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 702 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 703 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
704 CPU_AVX2_FLAGS, 0, 0 },
8a2c8fef 705 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 706 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 707 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 708 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 709 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
710 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 711 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 712 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 714 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 715 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 716 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 718 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 720 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 722 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 723 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 724 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 725 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 726 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 727 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 728 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 729 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
730 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 732 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 734 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 736 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 738 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 740 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 741 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
742 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 744 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 745 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
746 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 747 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
748 CPU_HLE_FLAGS, 0, 0 },
749 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
750 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 751 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
752 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 754 CPU_CLFLUSH_FLAGS, 0, 0 },
755 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
756 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 758 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 760 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 762 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 764 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 766 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 767 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 768 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 769 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 770 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 772 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 773 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 774 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 775 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
776 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 777 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
778 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 779 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
780 CPU_ADX_FLAGS, 0, 0 },
781 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
782 CPU_RDSEED_FLAGS, 0, 0 },
783 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
784 CPU_PRFCHW_FLAGS, 0, 0 },
e413e4e9
AM		 785};
786
704209c0 787#ifdef I386COFF
a6c24e68
NC		 788/* Like s_lcomm_internal in gas/read.c but the alignment string
789 is allowed to be optional. */
790
791static symbolS *
792pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
793{
794 addressT align = 0;
795
796 SKIP_WHITESPACE ();
797
7ab9ffdd 798 if (needs_align
a6c24e68
NC		 799 && *input_line_pointer == ',')
800 {
801 align = parse_align (needs_align - 1);
7ab9ffdd 802
a6c24e68
NC		 803 if (align == (addressT) -1)
804 return NULL;
805 }
806 else
807 {
808 if (size >= 8)
809 align = 3;
810 else if (size >= 4)
811 align = 2;
812 else if (size >= 2)
813 align = 1;
814 else
815 align = 0;
816 }
817
818 bss_alloc (symbolP, size, align);
819 return symbolP;
820}
821
704209c0 822static void
a6c24e68
NC		 823pe_lcomm (int needs_align)
824{
825 s_comm_internal (needs_align * 2, pe_lcomm_internal);
826}
704209c0 827#endif
a6c24e68 828
29b0f896
AM		 829const pseudo_typeS md_pseudo_table[] =
830{
831#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
832 {"align", s_align_bytes, 0},
833#else
834 {"align", s_align_ptwo, 0},
835#endif
836 {"arch", set_cpu_arch, 0},
837#ifndef I386COFF
838 {"bss", s_bss, 0},
a6c24e68
NC		 839#else
840 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 841#endif
842 {"ffloat", float_cons, 'f'},
843 {"dfloat", float_cons, 'd'},
844 {"tfloat", float_cons, 'x'},
845 {"value", cons, 2},
d182319b 846 {"slong", signed_cons, 4},
29b0f896
AM		 847 {"noopt", s_ignore, 0},
848 {"optim", s_ignore, 0},
849 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
850 {"code16", set_code_flag, CODE_16BIT},
851 {"code32", set_code_flag, CODE_32BIT},
852 {"code64", set_code_flag, CODE_64BIT},
853 {"intel_syntax", set_intel_syntax, 1},
854 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 855 {"intel_mnemonic", set_intel_mnemonic, 1},
856 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 857 {"allow_index_reg", set_allow_index_reg, 1},
858 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 859 {"sse_check", set_check, 0},
860 {"operand_check", set_check, 1},
3b22753a
L		 861#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
862 {"largecomm", handle_large_common, 0},
07a53e5c 863#else
e3bb37b5 864 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 865 {"loc", dwarf2_directive_loc, 0},
866 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 867#endif
6482c264
NC		 868#ifdef TE_PE
869 {"secrel32", pe_directive_secrel, 0},
870#endif
29b0f896
AM		 871 {0, 0, 0}
872};
873
874/* For interface with expression (). */
875extern char *input_line_pointer;
876
877/* Hash table for instruction mnemonic lookup. */
878static struct hash_control *op_hash;
879
880/* Hash table for register lookup. */
881static struct hash_control *reg_hash;
882\f
252b5132 883void
e3bb37b5 884i386_align_code (fragS *fragP, int count)
252b5132 885{
ce8a8b2f
AM		 886 /* Various efficient no-op patterns for aligning code labels.
887 Note: Don't try to assemble the instructions in the comments.
888 0L and 0w are not legal. */
252b5132
RH		 889 static const char f32_1[] =
890 {0x90}; /* nop */
891 static const char f32_2[] =
ccc9c027 892 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 893 static const char f32_3[] =
894 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
895 static const char f32_4[] =
896 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
897 static const char f32_5[] =
898 {0x90, /* nop */
899 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
900 static const char f32_6[] =
901 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
902 static const char f32_7[] =
903 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
904 static const char f32_8[] =
905 {0x90, /* nop */
906 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
907 static const char f32_9[] =
908 {0x89,0xf6, /* movl %esi,%esi */
909 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
910 static const char f32_10[] =
911 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
912 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
913 static const char f32_11[] =
914 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
915 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
916 static const char f32_12[] =
917 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
918 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
919 static const char f32_13[] =
920 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
921 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
922 static const char f32_14[] =
923 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
924 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 925 static const char f16_3[] =
926 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 927 static const char f16_4[] =
928 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
929 static const char f16_5[] =
930 {0x90, /* nop */
931 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
932 static const char f16_6[] =
933 {0x89,0xf6, /* mov %si,%si */
934 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
935 static const char f16_7[] =
936 {0x8d,0x74,0x00, /* lea 0(%si),%si */
937 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
938 static const char f16_8[] =
939 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
940 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 941 static const char jump_31[] =
942 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
943 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
944 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
945 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 946 static const char *const f32_patt[] = {
947 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 948 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 949 };
950 static const char *const f16_patt[] = {
76bc74dc 951 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 952 };
ccc9c027
L		 953 /* nopl (%[re]ax) */
954 static const char alt_3[] =
955 {0x0f,0x1f,0x00};
956 /* nopl 0(%[re]ax) */
957 static const char alt_4[] =
958 {0x0f,0x1f,0x40,0x00};
959 /* nopl 0(%[re]ax,%[re]ax,1) */
960 static const char alt_5[] =
961 {0x0f,0x1f,0x44,0x00,0x00};
962 /* nopw 0(%[re]ax,%[re]ax,1) */
963 static const char alt_6[] =
964 {0x66,0x0f,0x1f,0x44,0x00,0x00};
965 /* nopl 0L(%[re]ax) */
966 static const char alt_7[] =
967 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
968 /* nopl 0L(%[re]ax,%[re]ax,1) */
969 static const char alt_8[] =
970 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
971 /* nopw 0L(%[re]ax,%[re]ax,1) */
972 static const char alt_9[] =
973 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
974 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
975 static const char alt_10[] =
976 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
977 /* data16
978 nopw %cs:0L(%[re]ax,%[re]ax,1) */
979 static const char alt_long_11[] =
980 {0x66,
981 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
982 /* data16
983 data16
984 nopw %cs:0L(%[re]ax,%[re]ax,1) */
985 static const char alt_long_12[] =
986 {0x66,
987 0x66,
988 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
989 /* data16
990 data16
991 data16
992 nopw %cs:0L(%[re]ax,%[re]ax,1) */
993 static const char alt_long_13[] =
994 {0x66,
995 0x66,
996 0x66,
997 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
998 /* data16
999 data16
1000 data16
1001 data16
1002 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1003 static const char alt_long_14[] =
1004 {0x66,
1005 0x66,
1006 0x66,
1007 0x66,
1008 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1009 /* data16
1010 data16
1011 data16
1012 data16
1013 data16
1014 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1015 static const char alt_long_15[] =
1016 {0x66,
1017 0x66,
1018 0x66,
1019 0x66,
1020 0x66,
1021 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1022 /* nopl 0(%[re]ax,%[re]ax,1)
1023 nopw 0(%[re]ax,%[re]ax,1) */
1024 static const char alt_short_11[] =
1025 {0x0f,0x1f,0x44,0x00,0x00,
1026 0x66,0x0f,0x1f,0x44,0x00,0x00};
1027 /* nopw 0(%[re]ax,%[re]ax,1)
1028 nopw 0(%[re]ax,%[re]ax,1) */
1029 static const char alt_short_12[] =
1030 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1031 0x66,0x0f,0x1f,0x44,0x00,0x00};
1032 /* nopw 0(%[re]ax,%[re]ax,1)
1033 nopl 0L(%[re]ax) */
1034 static const char alt_short_13[] =
1035 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1036 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1037 /* nopl 0L(%[re]ax)
1038 nopl 0L(%[re]ax) */
1039 static const char alt_short_14[] =
1040 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1041 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1042 /* nopl 0L(%[re]ax)
1043 nopl 0L(%[re]ax,%[re]ax,1) */
1044 static const char alt_short_15[] =
1045 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1046 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1047 static const char *const alt_short_patt[] = {
1048 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1049 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1050 alt_short_14, alt_short_15
1051 };
1052 static const char *const alt_long_patt[] = {
1053 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1054 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1055 alt_long_14, alt_long_15
1056 };
252b5132 1057
76bc74dc
L		 1058 /* Only align for at least a positive non-zero boundary. */
1059 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1060 return;
3e73aa7c 1061
ccc9c027
L		 1062 /* We need to decide which NOP sequence to use for 32bit and
1063 64bit. When -mtune= is used:
4eed87de 1064
76bc74dc
L		 1065 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1066 PROCESSOR_GENERIC32, f32_patt will be used.
1067 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1068 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1069 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1070 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1071 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1072 will be used.
ccc9c027 1073
76bc74dc 1074 When -mtune= isn't used, alt_long_patt will be used if
22109423 1075 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1076 be used.
ccc9c027
L		 1077
1078 When -march= or .arch is used, we can't use anything beyond
1079 cpu_arch_isa_flags. */
1080
1081 if (flag_code == CODE_16BIT)
1082 {
ccc9c027 1083 if (count > 8)
33fef721 1084 {
76bc74dc
L		 1085 memcpy (fragP->fr_literal + fragP->fr_fix,
1086 jump_31, count);
1087 /* Adjust jump offset. */
1088 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1089 }
76bc74dc
L		 1090 else
1091 memcpy (fragP->fr_literal + fragP->fr_fix,
1092 f16_patt[count - 1], count);
252b5132 1093 }
33fef721 1094 else
ccc9c027
L		 1095 {
1096 const char *const *patt = NULL;
1097
fbf3f584 1098 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1099 {
1100 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1101 switch (cpu_arch_tune)
1102 {
1103 case PROCESSOR_UNKNOWN:
1104 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1105 optimize with nops. */
1106 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1107 patt = alt_long_patt;
ccc9c027
L		 1108 else
1109 patt = f32_patt;
1110 break;
ccc9c027
L		 1111 case PROCESSOR_PENTIUM4:
1112 case PROCESSOR_NOCONA:
ef05d495 1113 case PROCESSOR_CORE:
76bc74dc 1114 case PROCESSOR_CORE2:
bd5295b2 1115 case PROCESSOR_COREI7:
3632d14b 1116 case PROCESSOR_L1OM:
7a9068fe 1117 case PROCESSOR_K1OM:
76bc74dc
L		 1118 case PROCESSOR_GENERIC64:
1119 patt = alt_long_patt;
1120 break;
ccc9c027
L		 1121 case PROCESSOR_K6:
1122 case PROCESSOR_ATHLON:
1123 case PROCESSOR_K8:
4eed87de 1124 case PROCESSOR_AMDFAM10:
8aedb9fe 1125 case PROCESSOR_BD:
7b458c12 1126 case PROCESSOR_BT:
ccc9c027
L		 1127 patt = alt_short_patt;
1128 break;
76bc74dc 1129 case PROCESSOR_I386:
ccc9c027
L		 1130 case PROCESSOR_I486:
1131 case PROCESSOR_PENTIUM:
2dde1948 1132 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1133 case PROCESSOR_GENERIC32:
1134 patt = f32_patt;
1135 break;
4eed87de 1136 }
ccc9c027
L		 1137 }
1138 else
1139 {
fbf3f584 1140 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1141 {
1142 case PROCESSOR_UNKNOWN:
e6a14101 1143 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1144 PROCESSOR_UNKNOWN. */
1145 abort ();
1146 break;
1147
76bc74dc 1148 case PROCESSOR_I386:
ccc9c027
L		 1149 case PROCESSOR_I486:
1150 case PROCESSOR_PENTIUM:
ccc9c027
L		 1151 case PROCESSOR_K6:
1152 case PROCESSOR_ATHLON:
1153 case PROCESSOR_K8:
4eed87de 1154 case PROCESSOR_AMDFAM10:
8aedb9fe 1155 case PROCESSOR_BD:
7b458c12 1156 case PROCESSOR_BT:
ccc9c027
L		 1157 case PROCESSOR_GENERIC32:
1158 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1159 with nops. */
1160 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1161 patt = alt_short_patt;
1162 else
1163 patt = f32_patt;
1164 break;
76bc74dc
L		 1165 case PROCESSOR_PENTIUMPRO:
1166 case PROCESSOR_PENTIUM4:
1167 case PROCESSOR_NOCONA:
1168 case PROCESSOR_CORE:
ef05d495 1169 case PROCESSOR_CORE2:
bd5295b2 1170 case PROCESSOR_COREI7:
3632d14b 1171 case PROCESSOR_L1OM:
7a9068fe 1172 case PROCESSOR_K1OM:
22109423 1173 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1174 patt = alt_long_patt;
1175 else
1176 patt = f32_patt;
1177 break;
1178 case PROCESSOR_GENERIC64:
76bc74dc 1179 patt = alt_long_patt;
ccc9c027 1180 break;
4eed87de 1181 }
ccc9c027
L		 1182 }
1183
76bc74dc
L		 1184 if (patt == f32_patt)
1185 {
1186 /* If the padding is less than 15 bytes, we use the normal
1187 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1188 its offset. */
1189 int limit;
76ba9986 1190
711eedef
L		 1191 /* For 64bit, the limit is 3 bytes. */
1192 if (flag_code == CODE_64BIT
1193 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1194 limit = 3;
1195 else
1196 limit = 15;
1197 if (count < limit)
76bc74dc
L		 1198 memcpy (fragP->fr_literal + fragP->fr_fix,
1199 patt[count - 1], count);
1200 else
1201 {
1202 memcpy (fragP->fr_literal + fragP->fr_fix,
1203 jump_31, count);
1204 /* Adjust jump offset. */
1205 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1206 }
1207 }
1208 else
1209 {
1210 /* Maximum length of an instruction is 15 byte. If the
1211 padding is greater than 15 bytes and we don't use jump,
1212 we have to break it into smaller pieces. */
1213 int padding = count;
1214 while (padding > 15)
1215 {
1216 padding -= 15;
1217 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1218 patt [14], 15);
1219 }
1220
1221 if (padding)
1222 memcpy (fragP->fr_literal + fragP->fr_fix,
1223 patt [padding - 1], padding);
1224 }
ccc9c027 1225 }
33fef721 1226 fragP->fr_var = count;
252b5132
RH		 1227}
1228
c6fb90c8 1229static INLINE int
0dfbf9d7 1230operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1231{
0dfbf9d7 1232 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1233 {
1234 case 3:
0dfbf9d7 1235 if (x->array[2])
c6fb90c8
L		 1236 return 0;
1237 case 2:
0dfbf9d7 1238 if (x->array[1])
c6fb90c8
L		 1239 return 0;
1240 case 1:
0dfbf9d7 1241 return !x->array[0];
c6fb90c8
L		 1242 default:
1243 abort ();
1244 }
40fb9820
L		 1245}
1246
c6fb90c8 1247static INLINE void
0dfbf9d7 1248operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1249{
0dfbf9d7 1250 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1251 {
1252 case 3:
0dfbf9d7 1253 x->array[2] = v;
c6fb90c8 1254 case 2:
0dfbf9d7 1255 x->array[1] = v;
c6fb90c8 1256 case 1:
0dfbf9d7 1257 x->array[0] = v;
c6fb90c8
L		 1258 break;
1259 default:
1260 abort ();
1261 }
1262}
40fb9820 1263
c6fb90c8 1264static INLINE int
0dfbf9d7
L		 1265operand_type_equal (const union i386_operand_type *x,
1266 const union i386_operand_type *y)
c6fb90c8 1267{
0dfbf9d7 1268 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1269 {
1270 case 3:
0dfbf9d7 1271 if (x->array[2] != y->array[2])
c6fb90c8
L		 1272 return 0;
1273 case 2:
0dfbf9d7 1274 if (x->array[1] != y->array[1])
c6fb90c8
L		 1275 return 0;
1276 case 1:
0dfbf9d7 1277 return x->array[0] == y->array[0];
c6fb90c8
L		 1278 break;
1279 default:
1280 abort ();
1281 }
1282}
40fb9820 1283
0dfbf9d7
L		 1284static INLINE int
1285cpu_flags_all_zero (const union i386_cpu_flags *x)
1286{
1287 switch (ARRAY_SIZE(x->array))
1288 {
1289 case 3:
1290 if (x->array[2])
1291 return 0;
1292 case 2:
1293 if (x->array[1])
1294 return 0;
1295 case 1:
1296 return !x->array[0];
1297 default:
1298 abort ();
1299 }
1300}
1301
1302static INLINE void
1303cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1304{
1305 switch (ARRAY_SIZE(x->array))
1306 {
1307 case 3:
1308 x->array[2] = v;
1309 case 2:
1310 x->array[1] = v;
1311 case 1:
1312 x->array[0] = v;
1313 break;
1314 default:
1315 abort ();
1316 }
1317}
1318
1319static INLINE int
1320cpu_flags_equal (const union i386_cpu_flags *x,
1321 const union i386_cpu_flags *y)
1322{
1323 switch (ARRAY_SIZE(x->array))
1324 {
1325 case 3:
1326 if (x->array[2] != y->array[2])
1327 return 0;
1328 case 2:
1329 if (x->array[1] != y->array[1])
1330 return 0;
1331 case 1:
1332 return x->array[0] == y->array[0];
1333 break;
1334 default:
1335 abort ();
1336 }
1337}
c6fb90c8
L		 1338
1339static INLINE int
1340cpu_flags_check_cpu64 (i386_cpu_flags f)
1341{
1342 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1343 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1344}
1345
c6fb90c8
L		 1346static INLINE i386_cpu_flags
1347cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1348{
c6fb90c8
L		 1349 switch (ARRAY_SIZE (x.array))
1350 {
1351 case 3:
1352 x.array [2] &= y.array [2];
1353 case 2:
1354 x.array [1] &= y.array [1];
1355 case 1:
1356 x.array [0] &= y.array [0];
1357 break;
1358 default:
1359 abort ();
1360 }
1361 return x;
1362}
40fb9820 1363
c6fb90c8
L		 1364static INLINE i386_cpu_flags
1365cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1366{
c6fb90c8 1367 switch (ARRAY_SIZE (x.array))
40fb9820 1368 {
c6fb90c8
L		 1369 case 3:
1370 x.array [2] |= y.array [2];
1371 case 2:
1372 x.array [1] |= y.array [1];
1373 case 1:
1374 x.array [0] |= y.array [0];
40fb9820
L		 1375 break;
1376 default:
1377 abort ();
1378 }
40fb9820
L		 1379 return x;
1380}
1381
309d3373
JB		 1382static INLINE i386_cpu_flags
1383cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1384{
1385 switch (ARRAY_SIZE (x.array))
1386 {
1387 case 3:
1388 x.array [2] &= ~y.array [2];
1389 case 2:
1390 x.array [1] &= ~y.array [1];
1391 case 1:
1392 x.array [0] &= ~y.array [0];
1393 break;
1394 default:
1395 abort ();
1396 }
1397 return x;
1398}
1399
c0f3af97
L		 1400#define CPU_FLAGS_ARCH_MATCH 0x1
1401#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1402#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1403#define CPU_FLAGS_PCLMUL_MATCH 0x8
1404#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1405
a5ff0eb2 1406#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1407 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1408 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1409#define CPU_FLAGS_PERFECT_MATCH \
1410 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1411
1412/* Return CPU flags match bits. */
3629bb00 1413
40fb9820 1414static int
d3ce72d0 1415cpu_flags_match (const insn_template *t)
40fb9820 1416{
c0f3af97
L		 1417 i386_cpu_flags x = t->cpu_flags;
1418 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1419
1420 x.bitfield.cpu64 = 0;
1421 x.bitfield.cpuno64 = 0;
1422
0dfbf9d7 1423 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1424 {
1425 /* This instruction is available on all archs. */
1426 match |= CPU_FLAGS_32BIT_MATCH;
1427 }
3629bb00
L		 1428 else
1429 {
c0f3af97 1430 /* This instruction is available only on some archs. */
3629bb00
L		 1431 i386_cpu_flags cpu = cpu_arch_flags;
1432
1433 cpu.bitfield.cpu64 = 0;
1434 cpu.bitfield.cpuno64 = 0;
1435 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1436 if (!cpu_flags_all_zero (&cpu))
1437 {
a5ff0eb2
L		 1438 if (x.bitfield.cpuavx)
1439 {
ce2f5b3c 1440 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1441 if (cpu.bitfield.cpuavx)
1442 {
1443 /* Check SSE2AVX. */
1444 if (!t->opcode_modifier.sse2avx|| sse2avx)
1445 {
1446 match |= (CPU_FLAGS_ARCH_MATCH
1447 | CPU_FLAGS_AVX_MATCH);
1448 /* Check AES. */
1449 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1450 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1451 /* Check PCLMUL. */
1452 if (!x.bitfield.cpupclmul
1453 || cpu.bitfield.cpupclmul)
1454 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1455 }
1456 }
1457 else
1458 match |= CPU_FLAGS_ARCH_MATCH;
1459 }
1460 else
c0f3af97
L		 1461 match |= CPU_FLAGS_32BIT_MATCH;
1462 }
3629bb00 1463 }
c0f3af97 1464 return match;
40fb9820
L		 1465}
1466
c6fb90c8
L		 1467static INLINE i386_operand_type
1468operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1469{
c6fb90c8
L		 1470 switch (ARRAY_SIZE (x.array))
1471 {
1472 case 3:
1473 x.array [2] &= y.array [2];
1474 case 2:
1475 x.array [1] &= y.array [1];
1476 case 1:
1477 x.array [0] &= y.array [0];
1478 break;
1479 default:
1480 abort ();
1481 }
1482 return x;
40fb9820
L		 1483}
1484
c6fb90c8
L		 1485static INLINE i386_operand_type
1486operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1487{
c6fb90c8 1488 switch (ARRAY_SIZE (x.array))
40fb9820 1489 {
c6fb90c8
L		 1490 case 3:
1491 x.array [2] |= y.array [2];
1492 case 2:
1493 x.array [1] |= y.array [1];
1494 case 1:
1495 x.array [0] |= y.array [0];
40fb9820
L		 1496 break;
1497 default:
1498 abort ();
1499 }
c6fb90c8
L		 1500 return x;
1501}
40fb9820 1502
c6fb90c8
L		 1503static INLINE i386_operand_type
1504operand_type_xor (i386_operand_type x, i386_operand_type y)
1505{
1506 switch (ARRAY_SIZE (x.array))
1507 {
1508 case 3:
1509 x.array [2] ^= y.array [2];
1510 case 2:
1511 x.array [1] ^= y.array [1];
1512 case 1:
1513 x.array [0] ^= y.array [0];
1514 break;
1515 default:
1516 abort ();
1517 }
40fb9820
L		 1518 return x;
1519}
1520
1521static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1522static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1523static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1524static const i386_operand_type inoutportreg
1525 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1526static const i386_operand_type reg16_inoutportreg
1527 = OPERAND_TYPE_REG16_INOUTPORTREG;
1528static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1529static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1530static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1531static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1532static const i386_operand_type anydisp
1533 = OPERAND_TYPE_ANYDISP;
40fb9820 1534static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1535static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1536static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1537static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1538static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1539static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1540static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1541static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1542static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1543static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1544static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1545static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1546
1547enum operand_type
1548{
1549 reg,
40fb9820
L		 1550 imm,
1551 disp,
1552 anymem
1553};
1554
c6fb90c8 1555static INLINE int
40fb9820
L		 1556operand_type_check (i386_operand_type t, enum operand_type c)
1557{
1558 switch (c)
1559 {
1560 case reg:
1561 return (t.bitfield.reg8
1562 || t.bitfield.reg16
1563 || t.bitfield.reg32
1564 || t.bitfield.reg64);
1565
40fb9820
L		 1566 case imm:
1567 return (t.bitfield.imm8
1568 || t.bitfield.imm8s
1569 || t.bitfield.imm16
1570 || t.bitfield.imm32
1571 || t.bitfield.imm32s
1572 || t.bitfield.imm64);
1573
1574 case disp:
1575 return (t.bitfield.disp8
1576 || t.bitfield.disp16
1577 || t.bitfield.disp32
1578 || t.bitfield.disp32s
1579 || t.bitfield.disp64);
1580
1581 case anymem:
1582 return (t.bitfield.disp8
1583 || t.bitfield.disp16
1584 || t.bitfield.disp32
1585 || t.bitfield.disp32s
1586 || t.bitfield.disp64
1587 || t.bitfield.baseindex);
1588
1589 default:
1590 abort ();
1591 }
2cfe26b6
AM		 1592
1593 return 0;
40fb9820
L		 1594}
1595
5c07affc
L		 1596/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1597 operand J for instruction template T. */
1598
1599static INLINE int
d3ce72d0 1600match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1601{
1602 return !((i.types[j].bitfield.byte
1603 && !t->operand_types[j].bitfield.byte)
1604 || (i.types[j].bitfield.word
1605 && !t->operand_types[j].bitfield.word)
1606 || (i.types[j].bitfield.dword
1607 && !t->operand_types[j].bitfield.dword)
1608 || (i.types[j].bitfield.qword
1609 && !t->operand_types[j].bitfield.qword));
1610}
1611
1612/* Return 1 if there is no conflict in any size on operand J for
1613 instruction template T. */
1614
1615static INLINE int
d3ce72d0 1616match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1617{
1618 return (match_reg_size (t, j)
1619 && !((i.types[j].bitfield.unspecified
1620 && !t->operand_types[j].bitfield.unspecified)
1621 || (i.types[j].bitfield.fword
1622 && !t->operand_types[j].bitfield.fword)
1623 || (i.types[j].bitfield.tbyte
1624 && !t->operand_types[j].bitfield.tbyte)
1625 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1626 && !t->operand_types[j].bitfield.xmmword)
1627 || (i.types[j].bitfield.ymmword
1628 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1629}
1630
1631/* Return 1 if there is no size conflict on any operands for
1632 instruction template T. */
1633
1634static INLINE int
d3ce72d0 1635operand_size_match (const insn_template *t)
5c07affc
L		 1636{
1637 unsigned int j;
1638 int match = 1;
1639
1640 /* Don't check jump instructions. */
1641 if (t->opcode_modifier.jump
1642 || t->opcode_modifier.jumpbyte
1643 || t->opcode_modifier.jumpdword
1644 || t->opcode_modifier.jumpintersegment)
1645 return match;
1646
1647 /* Check memory and accumulator operand size. */
1648 for (j = 0; j < i.operands; j++)
1649 {
1650 if (t->operand_types[j].bitfield.anysize)
1651 continue;
1652
1653 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1654 {
1655 match = 0;
1656 break;
1657 }
1658
1659 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1660 {
1661 match = 0;
1662 break;
1663 }
1664 }
1665
891edac4 1666 if (match)
5c07affc 1667 return match;
891edac4
L		 1668 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1669 {
1670mismatch:
86e026a4 1671 i.error = operand_size_mismatch;
891edac4
L		 1672 return 0;
1673 }
5c07affc
L		 1674
1675 /* Check reverse. */
9c2799c2 1676 gas_assert (i.operands == 2);
5c07affc
L		 1677
1678 match = 1;
1679 for (j = 0; j < 2; j++)
1680 {
1681 if (t->operand_types[j].bitfield.acc
1682 && !match_reg_size (t, j ? 0 : 1))
891edac4 1683 goto mismatch;
5c07affc
L		 1684
1685 if (i.types[j].bitfield.mem
1686 && !match_mem_size (t, j ? 0 : 1))
891edac4 1687 goto mismatch;
5c07affc
L		 1688 }
1689
1690 return match;
1691}
1692
c6fb90c8 1693static INLINE int
40fb9820
L		 1694operand_type_match (i386_operand_type overlap,
1695 i386_operand_type given)
1696{
1697 i386_operand_type temp = overlap;
1698
1699 temp.bitfield.jumpabsolute = 0;
7d5e4556 1700 temp.bitfield.unspecified = 0;
5c07affc
L		 1701 temp.bitfield.byte = 0;
1702 temp.bitfield.word = 0;
1703 temp.bitfield.dword = 0;
1704 temp.bitfield.fword = 0;
1705 temp.bitfield.qword = 0;
1706 temp.bitfield.tbyte = 0;
1707 temp.bitfield.xmmword = 0;
c0f3af97 1708 temp.bitfield.ymmword = 0;
0dfbf9d7 1709 if (operand_type_all_zero (&temp))
891edac4 1710 goto mismatch;
40fb9820 1711
891edac4
L		 1712 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1713 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1714 return 1;
1715
1716mismatch:
a65babc9 1717 i.error = operand_type_mismatch;
891edac4 1718 return 0;
40fb9820
L		 1719}
1720
7d5e4556 1721/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1722 unless the expected operand type register overlap is null.
1723 Note that Acc in a template matches every size of reg. */
1724
c6fb90c8 1725static INLINE int
40fb9820
L		 1726operand_type_register_match (i386_operand_type m0,
1727 i386_operand_type g0,
1728 i386_operand_type t0,
1729 i386_operand_type m1,
1730 i386_operand_type g1,
1731 i386_operand_type t1)
1732{
1733 if (!operand_type_check (g0, reg))
1734 return 1;
1735
1736 if (!operand_type_check (g1, reg))
1737 return 1;
1738
1739 if (g0.bitfield.reg8 == g1.bitfield.reg8
1740 && g0.bitfield.reg16 == g1.bitfield.reg16
1741 && g0.bitfield.reg32 == g1.bitfield.reg32
1742 && g0.bitfield.reg64 == g1.bitfield.reg64)
1743 return 1;
1744
1745 if (m0.bitfield.acc)
1746 {
1747 t0.bitfield.reg8 = 1;
1748 t0.bitfield.reg16 = 1;
1749 t0.bitfield.reg32 = 1;
1750 t0.bitfield.reg64 = 1;
1751 }
1752
1753 if (m1.bitfield.acc)
1754 {
1755 t1.bitfield.reg8 = 1;
1756 t1.bitfield.reg16 = 1;
1757 t1.bitfield.reg32 = 1;
1758 t1.bitfield.reg64 = 1;
1759 }
1760
891edac4
L		 1761 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1762 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1763 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1764 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1765 return 1;
1766
a65babc9 1767 i.error = register_type_mismatch;
891edac4
L		 1768
1769 return 0;
40fb9820
L		 1770}
1771
4c692bc7
JB		 1772static INLINE unsigned int
1773register_number (const reg_entry *r)
1774{
1775 unsigned int nr = r->reg_num;
1776
1777 if (r->reg_flags & RegRex)
1778 nr += 8;
1779
1780 return nr;
1781}
1782
252b5132 1783static INLINE unsigned int
40fb9820 1784mode_from_disp_size (i386_operand_type t)
252b5132 1785{
40fb9820
L		 1786 if (t.bitfield.disp8)
1787 return 1;
1788 else if (t.bitfield.disp16
1789 || t.bitfield.disp32
1790 || t.bitfield.disp32s)
1791 return 2;
1792 else
1793 return 0;
252b5132
RH		 1794}
1795
1796static INLINE int
e3bb37b5 1797fits_in_signed_byte (offsetT num)
252b5132
RH		 1798{
1799 return (num >= -128) && (num <= 127);
47926f60 1800}
252b5132
RH		 1801
1802static INLINE int
e3bb37b5 1803fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1804{
1805 return (num & 0xff) == num;
47926f60 1806}
252b5132
RH		 1807
1808static INLINE int
e3bb37b5 1809fits_in_unsigned_word (offsetT num)
252b5132
RH		 1810{
1811 return (num & 0xffff) == num;
47926f60 1812}
252b5132
RH		 1813
1814static INLINE int
e3bb37b5 1815fits_in_signed_word (offsetT num)
252b5132
RH		 1816{
1817 return (-32768 <= num) && (num <= 32767);
47926f60 1818}
2a962e6d 1819
3e73aa7c 1820static INLINE int
e3bb37b5 1821fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1822{
1823#ifndef BFD64
1824 return 1;
1825#else
1826 return (!(((offsetT) -1 << 31) & num)
1827 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1828#endif
1829} /* fits_in_signed_long() */
2a962e6d 1830
3e73aa7c 1831static INLINE int
e3bb37b5 1832fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1833{
1834#ifndef BFD64
1835 return 1;
1836#else
1837 return (num & (((offsetT) 2 << 31) - 1)) == num;
1838#endif
1839} /* fits_in_unsigned_long() */
252b5132 1840
a683cc34
SP		 1841static INLINE int
1842fits_in_imm4 (offsetT num)
1843{
1844 return (num & 0xf) == num;
1845}
1846
40fb9820 1847static i386_operand_type
e3bb37b5 1848smallest_imm_type (offsetT num)
252b5132 1849{
40fb9820 1850 i386_operand_type t;
7ab9ffdd 1851
0dfbf9d7 1852 operand_type_set (&t, 0);
40fb9820
L		 1853 t.bitfield.imm64 = 1;
1854
1855 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1856 {
1857 /* This code is disabled on the 486 because all the Imm1 forms
1858 in the opcode table are slower on the i486. They're the
1859 versions with the implicitly specified single-position
1860 displacement, which has another syntax if you really want to
1861 use that form. */
40fb9820
L		 1862 t.bitfield.imm1 = 1;
1863 t.bitfield.imm8 = 1;
1864 t.bitfield.imm8s = 1;
1865 t.bitfield.imm16 = 1;
1866 t.bitfield.imm32 = 1;
1867 t.bitfield.imm32s = 1;
1868 }
1869 else if (fits_in_signed_byte (num))
1870 {
1871 t.bitfield.imm8 = 1;
1872 t.bitfield.imm8s = 1;
1873 t.bitfield.imm16 = 1;
1874 t.bitfield.imm32 = 1;
1875 t.bitfield.imm32s = 1;
1876 }
1877 else if (fits_in_unsigned_byte (num))
1878 {
1879 t.bitfield.imm8 = 1;
1880 t.bitfield.imm16 = 1;
1881 t.bitfield.imm32 = 1;
1882 t.bitfield.imm32s = 1;
1883 }
1884 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1885 {
1886 t.bitfield.imm16 = 1;
1887 t.bitfield.imm32 = 1;
1888 t.bitfield.imm32s = 1;
1889 }
1890 else if (fits_in_signed_long (num))
1891 {
1892 t.bitfield.imm32 = 1;
1893 t.bitfield.imm32s = 1;
1894 }
1895 else if (fits_in_unsigned_long (num))
1896 t.bitfield.imm32 = 1;
1897
1898 return t;
47926f60 1899}
252b5132 1900
847f7ad4 1901static offsetT
e3bb37b5 1902offset_in_range (offsetT val, int size)
847f7ad4 1903{
508866be 1904 addressT mask;
ba2adb93 1905
847f7ad4
AM		 1906 switch (size)
1907 {
508866be
L		 1908 case 1: mask = ((addressT) 1 << 8) - 1; break;
1909 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1910 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1911#ifdef BFD64
1912 case 8: mask = ((addressT) 2 << 63) - 1; break;
1913#endif
47926f60 1914 default: abort ();
847f7ad4
AM		 1915 }
1916
9de868bf
L		 1917#ifdef BFD64
1918 /* If BFD64, sign extend val for 32bit address mode. */
1919 if (flag_code != CODE_64BIT
1920 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1921 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1922 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1923#endif
ba2adb93 1924
47926f60 1925 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1926 {
1927 char buf1[40], buf2[40];
1928
1929 sprint_value (buf1, val);
1930 sprint_value (buf2, val & mask);
1931 as_warn (_("%s shortened to %s"), buf1, buf2);
1932 }
1933 return val & mask;
1934}
1935
c32fa91d
L		 1936enum PREFIX_GROUP
1937{
1938 PREFIX_EXIST = 0,
1939 PREFIX_LOCK,
1940 PREFIX_REP,
1941 PREFIX_OTHER
1942};
1943
1944/* Returns
1945 a. PREFIX_EXIST if attempting to add a prefix where one from the
1946 same class already exists.
1947 b. PREFIX_LOCK if lock prefix is added.
1948 c. PREFIX_REP if rep/repne prefix is added.
1949 d. PREFIX_OTHER if other prefix is added.
1950 */
1951
1952static enum PREFIX_GROUP
e3bb37b5 1953add_prefix (unsigned int prefix)
252b5132 1954{
c32fa91d 1955 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1956 unsigned int q;
252b5132 1957
29b0f896
AM		 1958 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1959 && flag_code == CODE_64BIT)
b1905489 1960 {
161a04f6
L		 1961 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1962 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1963 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1964 ret = PREFIX_EXIST;
b1905489
JB		 1965 q = REX_PREFIX;
1966 }
3e73aa7c 1967 else
b1905489
JB		 1968 {
1969 switch (prefix)
1970 {
1971 default:
1972 abort ();
1973
1974 case CS_PREFIX_OPCODE:
1975 case DS_PREFIX_OPCODE:
1976 case ES_PREFIX_OPCODE:
1977 case FS_PREFIX_OPCODE:
1978 case GS_PREFIX_OPCODE:
1979 case SS_PREFIX_OPCODE:
1980 q = SEG_PREFIX;
1981 break;
1982
1983 case REPNE_PREFIX_OPCODE:
1984 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1985 q = REP_PREFIX;
1986 ret = PREFIX_REP;
1987 break;
1988
b1905489 1989 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1990 q = LOCK_PREFIX;
1991 ret = PREFIX_LOCK;
b1905489
JB		 1992 break;
1993
1994 case FWAIT_OPCODE:
1995 q = WAIT_PREFIX;
1996 break;
1997
1998 case ADDR_PREFIX_OPCODE:
1999 q = ADDR_PREFIX;
2000 break;
2001
2002 case DATA_PREFIX_OPCODE:
2003 q = DATA_PREFIX;
2004 break;
2005 }
2006 if (i.prefix[q] != 0)
c32fa91d 2007 ret = PREFIX_EXIST;
b1905489 2008 }
252b5132 2009
b1905489 2010 if (ret)
252b5132 2011 {
b1905489
JB		 2012 if (!i.prefix[q])
2013 ++i.prefixes;
2014 i.prefix[q] |= prefix;
252b5132 2015 }
b1905489
JB		 2016 else
2017 as_bad (_("same type of prefix used twice"));
252b5132 2018
252b5132
RH		 2019 return ret;
2020}
2021
2022static void
78f12dd3 2023update_code_flag (int value, int check)
eecb386c 2024{
78f12dd3
L		 2025 PRINTF_LIKE ((*as_error));
2026
1e9cc1c2 2027 flag_code = (enum flag_code) value;
40fb9820
L		 2028 if (flag_code == CODE_64BIT)
2029 {
2030 cpu_arch_flags.bitfield.cpu64 = 1;
2031 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2032 }
2033 else
2034 {
2035 cpu_arch_flags.bitfield.cpu64 = 0;
2036 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2037 }
2038 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2039 {
78f12dd3
L		 2040 if (check)
2041 as_error = as_fatal;
2042 else
2043 as_error = as_bad;
2044 (*as_error) (_("64bit mode not supported on `%s'."),
2045 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2046 }
40fb9820 2047 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2048 {
78f12dd3
L		 2049 if (check)
2050 as_error = as_fatal;
2051 else
2052 as_error = as_bad;
2053 (*as_error) (_("32bit mode not supported on `%s'."),
2054 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2055 }
eecb386c
AM		 2056 stackop_size = '\0';
2057}
2058
78f12dd3
L		 2059static void
2060set_code_flag (int value)
2061{
2062 update_code_flag (value, 0);
2063}
2064
eecb386c 2065static void
e3bb37b5 2066set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2067{
1e9cc1c2 2068 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2069 if (flag_code != CODE_16BIT)
2070 abort ();
2071 cpu_arch_flags.bitfield.cpu64 = 0;
2072 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2073 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2074}
2075
2076static void
e3bb37b5 2077set_intel_syntax (int syntax_flag)
252b5132
RH		 2078{
2079 /* Find out if register prefixing is specified. */
2080 int ask_naked_reg = 0;
2081
2082 SKIP_WHITESPACE ();
29b0f896 2083 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2084 {
2085 char *string = input_line_pointer;
2086 int e = get_symbol_end ();
2087
47926f60 2088 if (strcmp (string, "prefix") == 0)
252b5132 2089 ask_naked_reg = 1;
47926f60 2090 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2091 ask_naked_reg = -1;
2092 else
d0b47220 2093 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2094 *input_line_pointer = e;
2095 }
2096 demand_empty_rest_of_line ();
c3332e24 2097
252b5132
RH		 2098 intel_syntax = syntax_flag;
2099
2100 if (ask_naked_reg == 0)
f86103b7
AM		 2101 allow_naked_reg = (intel_syntax
2102 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2103 else
2104 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2105
ee86248c 2106 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2107
e4a3b5a4 2108 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2109 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2110 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2111}
2112
1efbbeb4
L		 2113static void
2114set_intel_mnemonic (int mnemonic_flag)
2115{
e1d4d893 2116 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2117}
2118
db51cc60
L		 2119static void
2120set_allow_index_reg (int flag)
2121{
2122 allow_index_reg = flag;
2123}
2124
cb19c032 2125static void
7bab8ab5 2126set_check (int what)
cb19c032 2127{
7bab8ab5
JB		 2128 enum check_kind *kind;
2129 const char *str;
2130
2131 if (what)
2132 {
2133 kind = &operand_check;
2134 str = "operand";
2135 }
2136 else
2137 {
2138 kind = &sse_check;
2139 str = "sse";
2140 }
2141
cb19c032
L		 2142 SKIP_WHITESPACE ();
2143
2144 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2145 {
2146 char *string = input_line_pointer;
2147 int e = get_symbol_end ();
2148
2149 if (strcmp (string, "none") == 0)
7bab8ab5 2150 *kind = check_none;
cb19c032 2151 else if (strcmp (string, "warning") == 0)
7bab8ab5 2152 *kind = check_warning;
cb19c032 2153 else if (strcmp (string, "error") == 0)
7bab8ab5 2154 *kind = check_error;
cb19c032 2155 else
7bab8ab5 2156 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2157 *input_line_pointer = e;
2158 }
2159 else
7bab8ab5 2160 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2161
2162 demand_empty_rest_of_line ();
2163}
2164
8a9036a4
L		 2165static void
2166check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2167 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2168{
2169#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2170 static const char *arch;
2171
2172 /* Intel LIOM is only supported on ELF. */
2173 if (!IS_ELF)
2174 return;
2175
2176 if (!arch)
2177 {
2178 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2179 use default_arch. */
2180 arch = cpu_arch_name;
2181 if (!arch)
2182 arch = default_arch;
2183 }
2184
3632d14b 2185 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2186 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2187 || new_flag.bitfield.cpul1om)
8a9036a4 2188 return;
76ba9986 2189
7a9068fe
L		 2190 /* If we are targeting Intel K1OM, we must enable it. */
2191 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2192 || new_flag.bitfield.cpuk1om)
2193 return;
2194
8a9036a4
L		 2195 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2196#endif
2197}
2198
e413e4e9 2199static void
e3bb37b5 2200set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2201{
47926f60 2202 SKIP_WHITESPACE ();
e413e4e9 2203
29b0f896 2204 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2205 {
2206 char *string = input_line_pointer;
2207 int e = get_symbol_end ();
91d6fa6a 2208 unsigned int j;
40fb9820 2209 i386_cpu_flags flags;
e413e4e9 2210
91d6fa6a 2211 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2212 {
91d6fa6a 2213 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2214 {
91d6fa6a 2215 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2216
5c6af06e
JB		 2217 if (*string != '.')
2218 {
91d6fa6a 2219 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2220 cpu_sub_arch_name = NULL;
91d6fa6a 2221 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2222 if (flag_code == CODE_64BIT)
2223 {
2224 cpu_arch_flags.bitfield.cpu64 = 1;
2225 cpu_arch_flags.bitfield.cpuno64 = 0;
2226 }
2227 else
2228 {
2229 cpu_arch_flags.bitfield.cpu64 = 0;
2230 cpu_arch_flags.bitfield.cpuno64 = 1;
2231 }
91d6fa6a
NC		 2232 cpu_arch_isa = cpu_arch[j].type;
2233 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2234 if (!cpu_arch_tune_set)
2235 {
2236 cpu_arch_tune = cpu_arch_isa;
2237 cpu_arch_tune_flags = cpu_arch_isa_flags;
2238 }
5c6af06e
JB		 2239 break;
2240 }
40fb9820 2241
22109423 2242 if (!cpu_arch[j].negated)
309d3373 2243 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2244 cpu_arch[j].flags);
309d3373
JB		 2245 else
2246 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2247 cpu_arch[j].flags);
0dfbf9d7 2248 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2249 {
6305a203
L		 2250 if (cpu_sub_arch_name)
2251 {
2252 char *name = cpu_sub_arch_name;
2253 cpu_sub_arch_name = concat (name,
91d6fa6a 2254 cpu_arch[j].name,
1bf57e9f 2255 (const char *) NULL);
6305a203
L		 2256 free (name);
2257 }
2258 else
91d6fa6a 2259 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2260 cpu_arch_flags = flags;
a586129e 2261 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2262 }
2263 *input_line_pointer = e;
2264 demand_empty_rest_of_line ();
2265 return;
e413e4e9
AM		 2266 }
2267 }
91d6fa6a 2268 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2269 as_bad (_("no such architecture: `%s'"), string);
2270
2271 *input_line_pointer = e;
2272 }
2273 else
2274 as_bad (_("missing cpu architecture"));
2275
fddf5b5b
AM		 2276 no_cond_jump_promotion = 0;
2277 if (*input_line_pointer == ','
29b0f896 2278 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2279 {
2280 char *string = ++input_line_pointer;
2281 int e = get_symbol_end ();
2282
2283 if (strcmp (string, "nojumps") == 0)
2284 no_cond_jump_promotion = 1;
2285 else if (strcmp (string, "jumps") == 0)
2286 ;
2287 else
2288 as_bad (_("no such architecture modifier: `%s'"), string);
2289
2290 *input_line_pointer = e;
2291 }
2292
e413e4e9
AM		 2293 demand_empty_rest_of_line ();
2294}
2295
8a9036a4
L		 2296enum bfd_architecture
2297i386_arch (void)
2298{
3632d14b 2299 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2300 {
2301 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2302 || flag_code != CODE_64BIT)
2303 as_fatal (_("Intel L1OM is 64bit ELF only"));
2304 return bfd_arch_l1om;
2305 }
7a9068fe
L		 2306 else if (cpu_arch_isa == PROCESSOR_K1OM)
2307 {
2308 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2309 || flag_code != CODE_64BIT)
2310 as_fatal (_("Intel K1OM is 64bit ELF only"));
2311 return bfd_arch_k1om;
2312 }
8a9036a4
L		 2313 else
2314 return bfd_arch_i386;
2315}
2316
b9d79e03 2317unsigned long
7016a5d5 2318i386_mach (void)
b9d79e03 2319{
351f65ca 2320 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2321 {
3632d14b 2322 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2323 {
351f65ca
L		 2324 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2325 || default_arch[6] != '\0')
8a9036a4
L		 2326 as_fatal (_("Intel L1OM is 64bit ELF only"));
2327 return bfd_mach_l1om;
2328 }
7a9068fe
L		 2329 else if (cpu_arch_isa == PROCESSOR_K1OM)
2330 {
2331 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2332 || default_arch[6] != '\0')
2333 as_fatal (_("Intel K1OM is 64bit ELF only"));
2334 return bfd_mach_k1om;
2335 }
351f65ca 2336 else if (default_arch[6] == '\0')
8a9036a4 2337 return bfd_mach_x86_64;
351f65ca
L		 2338 else
2339 return bfd_mach_x64_32;
8a9036a4 2340 }
b9d79e03
JH		 2341 else if (!strcmp (default_arch, "i386"))
2342 return bfd_mach_i386_i386;
2343 else
2b5d6a91 2344 as_fatal (_("unknown architecture"));
b9d79e03 2345}
b9d79e03 2346\f
252b5132 2347void
7016a5d5 2348md_begin (void)
252b5132
RH		 2349{
2350 const char *hash_err;
2351
47926f60 2352 /* Initialize op_hash hash table. */
252b5132
RH		 2353 op_hash = hash_new ();
2354
2355 {
d3ce72d0 2356 const insn_template *optab;
29b0f896 2357 templates *core_optab;
252b5132 2358
47926f60
KH		 2359 /* Setup for loop. */
2360 optab = i386_optab;
252b5132
RH		 2361 core_optab = (templates *) xmalloc (sizeof (templates));
2362 core_optab->start = optab;
2363
2364 while (1)
2365 {
2366 ++optab;
2367 if (optab->name == NULL
2368 || strcmp (optab->name, (optab - 1)->name) != 0)
2369 {
2370 /* different name --> ship out current template list;
47926f60 2371 add to hash table; & begin anew. */
252b5132
RH		 2372 core_optab->end = optab;
2373 hash_err = hash_insert (op_hash,
2374 (optab - 1)->name,
5a49b8ac 2375 (void *) core_optab);
252b5132
RH		 2376 if (hash_err)
2377 {
b37df7c4 2378 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2379 (optab - 1)->name,
2380 hash_err);
2381 }
2382 if (optab->name == NULL)
2383 break;
2384 core_optab = (templates *) xmalloc (sizeof (templates));
2385 core_optab->start = optab;
2386 }
2387 }
2388 }
2389
47926f60 2390 /* Initialize reg_hash hash table. */
252b5132
RH		 2391 reg_hash = hash_new ();
2392 {
29b0f896 2393 const reg_entry *regtab;
c3fe08fa 2394 unsigned int regtab_size = i386_regtab_size;
252b5132 2395
c3fe08fa 2396 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2397 {
5a49b8ac 2398 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2399 if (hash_err)
b37df7c4 2400 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2401 regtab->reg_name,
2402 hash_err);
252b5132
RH		 2403 }
2404 }
2405
47926f60 2406 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2407 {
29b0f896
AM		 2408 int c;
2409 char *p;
252b5132
RH		 2410
2411 for (c = 0; c < 256; c++)
2412 {
3882b010 2413 if (ISDIGIT (c))
252b5132
RH		 2414 {
2415 digit_chars[c] = c;
2416 mnemonic_chars[c] = c;
2417 register_chars[c] = c;
2418 operand_chars[c] = c;
2419 }
3882b010 2420 else if (ISLOWER (c))
252b5132
RH		 2421 {
2422 mnemonic_chars[c] = c;
2423 register_chars[c] = c;
2424 operand_chars[c] = c;
2425 }
3882b010 2426 else if (ISUPPER (c))
252b5132 2427 {
3882b010 2428 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2429 register_chars[c] = mnemonic_chars[c];
2430 operand_chars[c] = c;
2431 }
2432
3882b010 2433 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2434 identifier_chars[c] = c;
2435 else if (c >= 128)
2436 {
2437 identifier_chars[c] = c;
2438 operand_chars[c] = c;
2439 }
2440 }
2441
2442#ifdef LEX_AT
2443 identifier_chars['@'] = '@';
32137342
NC		 2444#endif
2445#ifdef LEX_QM
2446 identifier_chars['?'] = '?';
2447 operand_chars['?'] = '?';
252b5132 2448#endif
252b5132 2449 digit_chars['-'] = '-';
c0f3af97 2450 mnemonic_chars['_'] = '_';
791fe849 2451 mnemonic_chars['-'] = '-';
0003779b 2452 mnemonic_chars['.'] = '.';
252b5132
RH		 2453 identifier_chars['_'] = '_';
2454 identifier_chars['.'] = '.';
2455
2456 for (p = operand_special_chars; *p != '\0'; p++)
2457 operand_chars[(unsigned char) *p] = *p;
2458 }
2459
2460#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2461 if (IS_ELF)
252b5132
RH		 2462 {
2463 record_alignment (text_section, 2);
2464 record_alignment (data_section, 2);
2465 record_alignment (bss_section, 2);
2466 }
2467#endif
a4447b93
RH		 2468
2469 if (flag_code == CODE_64BIT)
2470 {
ca19b261
KT		 2471#if defined (OBJ_COFF) && defined (TE_PE)
2472 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2473 ? 32 : 16);
2474#else
a4447b93 2475 x86_dwarf2_return_column = 16;
ca19b261 2476#endif
61ff971f 2477 x86_cie_data_alignment = -8;
a4447b93
RH		 2478 }
2479 else
2480 {
2481 x86_dwarf2_return_column = 8;
2482 x86_cie_data_alignment = -4;
2483 }
252b5132
RH		 2484}
2485
2486void
e3bb37b5 2487i386_print_statistics (FILE *file)
252b5132
RH		 2488{
2489 hash_print_statistics (file, "i386 opcode", op_hash);
2490 hash_print_statistics (file, "i386 register", reg_hash);
2491}
2492\f
252b5132
RH		 2493#ifdef DEBUG386
2494
ce8a8b2f 2495/* Debugging routines for md_assemble. */
d3ce72d0 2496static void pte (insn_template *);
40fb9820 2497static void pt (i386_operand_type);
e3bb37b5
L		 2498static void pe (expressionS *);
2499static void ps (symbolS *);
252b5132
RH		 2500
2501static void
e3bb37b5 2502pi (char *line, i386_insn *x)
252b5132 2503{
09137c09 2504 unsigned int j;
252b5132
RH		 2505
2506 fprintf (stdout, "%s: template ", line);
2507 pte (&x->tm);
09f131f2
JH		 2508 fprintf (stdout, " address: base %s index %s scale %x\n",
2509 x->base_reg ? x->base_reg->reg_name : "none",
2510 x->index_reg ? x->index_reg->reg_name : "none",
2511 x->log2_scale_factor);
2512 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2513 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2514 fprintf (stdout, " sib: base %x index %x scale %x\n",
2515 x->sib.base, x->sib.index, x->sib.scale);
2516 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2517 (x->rex & REX_W) != 0,
2518 (x->rex & REX_R) != 0,
2519 (x->rex & REX_X) != 0,
2520 (x->rex & REX_B) != 0);
09137c09 2521 for (j = 0; j < x->operands; j++)
252b5132 2522 {
09137c09
SP		 2523 fprintf (stdout, " #%d: ", j + 1);
2524 pt (x->types[j]);
252b5132 2525 fprintf (stdout, "\n");
09137c09
SP		 2526 if (x->types[j].bitfield.reg8
2527 || x->types[j].bitfield.reg16
2528 || x->types[j].bitfield.reg32
2529 || x->types[j].bitfield.reg64
2530 || x->types[j].bitfield.regmmx
2531 || x->types[j].bitfield.regxmm
2532 || x->types[j].bitfield.regymm
2533 || x->types[j].bitfield.sreg2
2534 || x->types[j].bitfield.sreg3
2535 || x->types[j].bitfield.control
2536 || x->types[j].bitfield.debug
2537 || x->types[j].bitfield.test)
2538 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2539 if (operand_type_check (x->types[j], imm))
2540 pe (x->op[j].imms);
2541 if (operand_type_check (x->types[j], disp))
2542 pe (x->op[j].disps);
252b5132
RH		 2543 }
2544}
2545
2546static void
d3ce72d0 2547pte (insn_template *t)
252b5132 2548{
09137c09 2549 unsigned int j;
252b5132 2550 fprintf (stdout, " %d operands ", t->operands);
47926f60 2551 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2552 if (t->extension_opcode != None)
2553 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2554 if (t->opcode_modifier.d)
252b5132 2555 fprintf (stdout, "D");
40fb9820 2556 if (t->opcode_modifier.w)
252b5132
RH		 2557 fprintf (stdout, "W");
2558 fprintf (stdout, "\n");
09137c09 2559 for (j = 0; j < t->operands; j++)
252b5132 2560 {
09137c09
SP		 2561 fprintf (stdout, " #%d type ", j + 1);
2562 pt (t->operand_types[j]);
252b5132
RH		 2563 fprintf (stdout, "\n");
2564 }
2565}
2566
2567static void
e3bb37b5 2568pe (expressionS *e)
252b5132 2569{
24eab124 2570 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2571 fprintf (stdout, " add_number %ld (%lx)\n",
2572 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2573 if (e->X_add_symbol)
2574 {
2575 fprintf (stdout, " add_symbol ");
2576 ps (e->X_add_symbol);
2577 fprintf (stdout, "\n");
2578 }
2579 if (e->X_op_symbol)
2580 {
2581 fprintf (stdout, " op_symbol ");
2582 ps (e->X_op_symbol);
2583 fprintf (stdout, "\n");
2584 }
2585}
2586
2587static void
e3bb37b5 2588ps (symbolS *s)
252b5132
RH		 2589{
2590 fprintf (stdout, "%s type %s%s",
2591 S_GET_NAME (s),
2592 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2593 segment_name (S_GET_SEGMENT (s)));
2594}
2595
7b81dfbb 2596static struct type_name
252b5132 2597 {
40fb9820
L		 2598 i386_operand_type mask;
2599 const char *name;
252b5132 2600 }
7b81dfbb 2601const type_names[] =
252b5132 2602{
40fb9820
L		 2603 { OPERAND_TYPE_REG8, "r8" },
2604 { OPERAND_TYPE_REG16, "r16" },
2605 { OPERAND_TYPE_REG32, "r32" },
2606 { OPERAND_TYPE_REG64, "r64" },
2607 { OPERAND_TYPE_IMM8, "i8" },
2608 { OPERAND_TYPE_IMM8, "i8s" },
2609 { OPERAND_TYPE_IMM16, "i16" },
2610 { OPERAND_TYPE_IMM32, "i32" },
2611 { OPERAND_TYPE_IMM32S, "i32s" },
2612 { OPERAND_TYPE_IMM64, "i64" },
2613 { OPERAND_TYPE_IMM1, "i1" },
2614 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2615 { OPERAND_TYPE_DISP8, "d8" },
2616 { OPERAND_TYPE_DISP16, "d16" },
2617 { OPERAND_TYPE_DISP32, "d32" },
2618 { OPERAND_TYPE_DISP32S, "d32s" },
2619 { OPERAND_TYPE_DISP64, "d64" },
2620 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2621 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2622 { OPERAND_TYPE_CONTROL, "control reg" },
2623 { OPERAND_TYPE_TEST, "test reg" },
2624 { OPERAND_TYPE_DEBUG, "debug reg" },
2625 { OPERAND_TYPE_FLOATREG, "FReg" },
2626 { OPERAND_TYPE_FLOATACC, "FAcc" },
2627 { OPERAND_TYPE_SREG2, "SReg2" },
2628 { OPERAND_TYPE_SREG3, "SReg3" },
2629 { OPERAND_TYPE_ACC, "Acc" },
2630 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2631 { OPERAND_TYPE_REGMMX, "rMMX" },
2632 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2633 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2634 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2635};
2636
2637static void
40fb9820 2638pt (i386_operand_type t)
252b5132 2639{
40fb9820 2640 unsigned int j;
c6fb90c8 2641 i386_operand_type a;
252b5132 2642
40fb9820 2643 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2644 {
2645 a = operand_type_and (t, type_names[j].mask);
0349dc08 2646 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2647 fprintf (stdout, "%s, ", type_names[j].name);
2648 }
252b5132
RH		 2649 fflush (stdout);
2650}
2651
2652#endif /* DEBUG386 */
2653\f
252b5132 2654static bfd_reloc_code_real_type
3956db08 2655reloc (unsigned int size,
64e74474
AM		 2656 int pcrel,
2657 int sign,
2658 bfd_reloc_code_real_type other)
252b5132 2659{
47926f60 2660 if (other != NO_RELOC)
3956db08 2661 {
91d6fa6a 2662 reloc_howto_type *rel;
3956db08
JB		 2663
2664 if (size == 8)
2665 switch (other)
2666 {
64e74474
AM		 2667 case BFD_RELOC_X86_64_GOT32:
2668 return BFD_RELOC_X86_64_GOT64;
2669 break;
2670 case BFD_RELOC_X86_64_PLTOFF64:
2671 return BFD_RELOC_X86_64_PLTOFF64;
2672 break;
2673 case BFD_RELOC_X86_64_GOTPC32:
2674 other = BFD_RELOC_X86_64_GOTPC64;
2675 break;
2676 case BFD_RELOC_X86_64_GOTPCREL:
2677 other = BFD_RELOC_X86_64_GOTPCREL64;
2678 break;
2679 case BFD_RELOC_X86_64_TPOFF32:
2680 other = BFD_RELOC_X86_64_TPOFF64;
2681 break;
2682 case BFD_RELOC_X86_64_DTPOFF32:
2683 other = BFD_RELOC_X86_64_DTPOFF64;
2684 break;
2685 default:
2686 break;
3956db08 2687 }
e05278af 2688
8ce3d284 2689#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2690 if (other == BFD_RELOC_SIZE32)
2691 {
2692 if (size == 8)
2693 return BFD_RELOC_SIZE64;
2694 if (pcrel)
2695 as_bad (_("there are no pc-relative size relocations"));
2696 }
8ce3d284 2697#endif
8fd4256d 2698
e05278af 2699 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2700 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2701 sign = -1;
2702
91d6fa6a
NC		 2703 rel = bfd_reloc_type_lookup (stdoutput, other);
2704 if (!rel)
3956db08 2705 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2706 else if (size != bfd_get_reloc_size (rel))
3956db08 2707 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2708 bfd_get_reloc_size (rel),
3956db08 2709 size);
91d6fa6a 2710 else if (pcrel && !rel->pc_relative)
3956db08 2711 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2712 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2713 && !sign)
91d6fa6a 2714 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2715 && sign > 0))
3956db08
JB		 2716 as_bad (_("relocated field and relocation type differ in signedness"));
2717 else
2718 return other;
2719 return NO_RELOC;
2720 }
252b5132
RH		 2721
2722 if (pcrel)
2723 {
3e73aa7c 2724 if (!sign)
3956db08 2725 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2726 switch (size)
2727 {
2728 case 1: return BFD_RELOC_8_PCREL;
2729 case 2: return BFD_RELOC_16_PCREL;
2730 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2731 case 8: return BFD_RELOC_64_PCREL;
252b5132 2732 }
3956db08 2733 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2734 }
2735 else
2736 {
3956db08 2737 if (sign > 0)
e5cb08ac 2738 switch (size)
3e73aa7c
JH		 2739 {
2740 case 4: return BFD_RELOC_X86_64_32S;
2741 }
2742 else
2743 switch (size)
2744 {
2745 case 1: return BFD_RELOC_8;
2746 case 2: return BFD_RELOC_16;
2747 case 4: return BFD_RELOC_32;
2748 case 8: return BFD_RELOC_64;
2749 }
3956db08
JB		 2750 as_bad (_("cannot do %s %u byte relocation"),
2751 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2752 }
2753
0cc9e1d3 2754 return NO_RELOC;
252b5132
RH		 2755}
2756
47926f60
KH		 2757/* Here we decide which fixups can be adjusted to make them relative to
2758 the beginning of the section instead of the symbol. Basically we need
2759 to make sure that the dynamic relocations are done correctly, so in
2760 some cases we force the original symbol to be used. */
2761
252b5132 2762int
e3bb37b5 2763tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2764{
6d249963 2765#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2766 if (!IS_ELF)
31312f95
AM		 2767 return 1;
2768
a161fe53
AM		 2769 /* Don't adjust pc-relative references to merge sections in 64-bit
2770 mode. */
2771 if (use_rela_relocations
2772 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2773 && fixP->fx_pcrel)
252b5132 2774 return 0;
31312f95 2775
8d01d9a9
AJ		 2776 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2777 and changed later by validate_fix. */
2778 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2779 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2780 return 0;
2781
8fd4256d
L		 2782 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2783 for size relocations. */
2784 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2785 || fixP->fx_r_type == BFD_RELOC_SIZE64
2786 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2787 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2788 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2789 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2790 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2791 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2792 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2793 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2794 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2795 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2796 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2797 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2798 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2799 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2800 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2801 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2802 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2803 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2804 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2805 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2806 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2807 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2808 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2809 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2810 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2811 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2812 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2813 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2814 return 0;
31312f95 2815#endif
252b5132
RH		 2816 return 1;
2817}
252b5132 2818
b4cac588 2819static int
e3bb37b5 2820intel_float_operand (const char *mnemonic)
252b5132 2821{
9306ca4a
JB		 2822 /* Note that the value returned is meaningful only for opcodes with (memory)
2823 operands, hence the code here is free to improperly handle opcodes that
2824 have no operands (for better performance and smaller code). */
2825
2826 if (mnemonic[0] != 'f')
2827 return 0; /* non-math */
2828
2829 switch (mnemonic[1])
2830 {
2831 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2832 the fs segment override prefix not currently handled because no
2833 call path can make opcodes without operands get here */
2834 case 'i':
2835 return 2 /* integer op */;
2836 case 'l':
2837 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2838 return 3; /* fldcw/fldenv */
2839 break;
2840 case 'n':
2841 if (mnemonic[2] != 'o' /* fnop */)
2842 return 3; /* non-waiting control op */
2843 break;
2844 case 'r':
2845 if (mnemonic[2] == 's')
2846 return 3; /* frstor/frstpm */
2847 break;
2848 case 's':
2849 if (mnemonic[2] == 'a')
2850 return 3; /* fsave */
2851 if (mnemonic[2] == 't')
2852 {
2853 switch (mnemonic[3])
2854 {
2855 case 'c': /* fstcw */
2856 case 'd': /* fstdw */
2857 case 'e': /* fstenv */
2858 case 's': /* fsts[gw] */
2859 return 3;
2860 }
2861 }
2862 break;
2863 case 'x':
2864 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2865 return 0; /* fxsave/fxrstor are not really math ops */
2866 break;
2867 }
252b5132 2868
9306ca4a 2869 return 1;
252b5132
RH		 2870}
2871
c0f3af97
L		 2872/* Build the VEX prefix. */
2873
2874static void
d3ce72d0 2875build_vex_prefix (const insn_template *t)
c0f3af97
L		 2876{
2877 unsigned int register_specifier;
2878 unsigned int implied_prefix;
2879 unsigned int vector_length;
2880
2881 /* Check register specifier. */
2882 if (i.vex.register_specifier)
4c692bc7 2883 register_specifier = ~register_number (i.vex.register_specifier) & 0xf;
c0f3af97
L		 2884 else
2885 register_specifier = 0xf;
2886
fa99fab2
L		 2887 /* Use 2-byte VEX prefix by swappping destination and source
2888 operand. */
2889 if (!i.swap_operand
2890 && i.operands == i.reg_operands
7f399153 2891 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2892 && i.tm.opcode_modifier.s
2893 && i.rex == REX_B)
2894 {
2895 unsigned int xchg = i.operands - 1;
2896 union i386_op temp_op;
2897 i386_operand_type temp_type;
2898
2899 temp_type = i.types[xchg];
2900 i.types[xchg] = i.types[0];
2901 i.types[0] = temp_type;
2902 temp_op = i.op[xchg];
2903 i.op[xchg] = i.op[0];
2904 i.op[0] = temp_op;
2905
9c2799c2 2906 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2907
2908 i.rex = REX_R;
2909 xchg = i.rm.regmem;
2910 i.rm.regmem = i.rm.reg;
2911 i.rm.reg = xchg;
2912
2913 /* Use the next insn. */
2914 i.tm = t[1];
2915 }
2916
539f890d
L		 2917 if (i.tm.opcode_modifier.vex == VEXScalar)
2918 vector_length = avxscalar;
2919 else
2920 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2921
2922 switch ((i.tm.base_opcode >> 8) & 0xff)
2923 {
2924 case 0:
2925 implied_prefix = 0;
2926 break;
2927 case DATA_PREFIX_OPCODE:
2928 implied_prefix = 1;
2929 break;
2930 case REPE_PREFIX_OPCODE:
2931 implied_prefix = 2;
2932 break;
2933 case REPNE_PREFIX_OPCODE:
2934 implied_prefix = 3;
2935 break;
2936 default:
2937 abort ();
2938 }
2939
2940 /* Use 2-byte VEX prefix if possible. */
7f399153 2941 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2942 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2943 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2944 {
2945 /* 2-byte VEX prefix. */
2946 unsigned int r;
2947
2948 i.vex.length = 2;
2949 i.vex.bytes[0] = 0xc5;
2950
2951 /* Check the REX.R bit. */
2952 r = (i.rex & REX_R) ? 0 : 1;
2953 i.vex.bytes[1] = (r << 7
2954 | register_specifier << 3
2955 | vector_length << 2
2956 | implied_prefix);
2957 }
2958 else
2959 {
2960 /* 3-byte VEX prefix. */
2961 unsigned int m, w;
2962
f88c9eb0 2963 i.vex.length = 3;
f88c9eb0 2964
7f399153 2965 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2966 {
7f399153
L		 2967 case VEX0F:
2968 m = 0x1;
80de6e00 2969 i.vex.bytes[0] = 0xc4;
7f399153
L		 2970 break;
2971 case VEX0F38:
2972 m = 0x2;
80de6e00 2973 i.vex.bytes[0] = 0xc4;
7f399153
L		 2974 break;
2975 case VEX0F3A:
2976 m = 0x3;
80de6e00 2977 i.vex.bytes[0] = 0xc4;
7f399153
L		 2978 break;
2979 case XOP08:
5dd85c99
SP		 2980 m = 0x8;
2981 i.vex.bytes[0] = 0x8f;
7f399153
L		 2982 break;
2983 case XOP09:
f88c9eb0
SP		 2984 m = 0x9;
2985 i.vex.bytes[0] = 0x8f;
7f399153
L		 2986 break;
2987 case XOP0A:
f88c9eb0
SP		 2988 m = 0xa;
2989 i.vex.bytes[0] = 0x8f;
7f399153
L		 2990 break;
2991 default:
2992 abort ();
f88c9eb0 2993 }
c0f3af97 2994
c0f3af97
L		 2995 /* The high 3 bits of the second VEX byte are 1's compliment
2996 of RXB bits from REX. */
2997 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2998
2999 /* Check the REX.W bit. */
3000 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 3001 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3002 {
3003 if (w)
3004 abort ();
3005
1ef99a7b 3006 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3007 w = 1;
3008 }
3009
3010 i.vex.bytes[2] = (w << 7
3011 | register_specifier << 3
3012 | vector_length << 2
3013 | implied_prefix);
3014 }
3015}
3016
65da13b5
L		 3017static void
3018process_immext (void)
3019{
3020 expressionS *exp;
3021
4c692bc7
JB		 3022 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3023 && i.operands > 0)
65da13b5 3024 {
4c692bc7
JB		 3025 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3026 with an opcode suffix which is coded in the same place as an
3027 8-bit immediate field would be.
3028 Here we check those operands and remove them afterwards. */
65da13b5
L		 3029 unsigned int x;
3030
3031 for (x = 0; x < i.operands; x++)
4c692bc7 3032 if (register_number (i.op[x].regs) != x)
65da13b5 3033 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3034 register_prefix, i.op[x].regs->reg_name, x + 1,
3035 i.tm.name);
3036
3037 i.operands = 0;
65da13b5
L		 3038 }
3039
c0f3af97 3040 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3041 which is coded in the same place as an 8-bit immediate field
3042 would be. Here we fake an 8-bit immediate operand from the
3043 opcode suffix stored in tm.extension_opcode.
3044
c1e679ec 3045 AVX instructions also use this encoding, for some of
c0f3af97 3046 3 argument instructions. */
65da13b5 3047
9c2799c2 3048 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 3049 && (i.operands <= 2
3050 || (i.tm.opcode_modifier.vex
3051 && i.operands <= 4)));
65da13b5
L		 3052
3053 exp = &im_expressions[i.imm_operands++];
3054 i.op[i.operands].imms = exp;
3055 i.types[i.operands] = imm8;
3056 i.operands++;
3057 exp->X_op = O_constant;
3058 exp->X_add_number = i.tm.extension_opcode;
3059 i.tm.extension_opcode = None;
3060}
3061
42164a71
L		 3062
3063static int
3064check_hle (void)
3065{
3066 switch (i.tm.opcode_modifier.hleprefixok)
3067 {
3068 default:
3069 abort ();
82c2def5 3070 case HLEPrefixNone:
42164a71
L		 3071 if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE)
3072 as_bad (_("invalid instruction `%s' after `xacquire'"),
3073 i.tm.name);
3074 else
3075 as_bad (_("invalid instruction `%s' after `xrelease'"),
3076 i.tm.name);
3077 return 0;
82c2def5 3078 case HLEPrefixLock:
42164a71
L		 3079 if (i.prefix[LOCK_PREFIX])
3080 return 1;
3081 if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE)
3082 as_bad (_("missing `lock' with `xacquire'"));
3083 else
3084 as_bad (_("missing `lock' with `xrelease'"));
3085 return 0;
82c2def5 3086 case HLEPrefixAny:
42164a71 3087 return 1;
82c2def5 3088 case HLEPrefixRelease:
42164a71
L		 3089 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3090 {
3091 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3092 i.tm.name);
3093 return 0;
3094 }
3095 if (i.mem_operands == 0
3096 || !operand_type_check (i.types[i.operands - 1], anymem))
3097 {
3098 as_bad (_("memory destination needed for instruction `%s'"
3099 " after `xrelease'"), i.tm.name);
3100 return 0;
3101 }
3102 return 1;
3103 }
3104}
3105
252b5132
RH		 3106/* This is the guts of the machine-dependent assembler. LINE points to a
3107 machine dependent instruction. This function is supposed to emit
3108 the frags/bytes it assembles to. */
3109
3110void
65da13b5 3111md_assemble (char *line)
252b5132 3112{
40fb9820 3113 unsigned int j;
252b5132 3114 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3115 const insn_template *t;
252b5132 3116
47926f60 3117 /* Initialize globals. */
252b5132
RH		 3118 memset (&i, '\0', sizeof (i));
3119 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3120 i.reloc[j] = NO_RELOC;
252b5132
RH		 3121 memset (disp_expressions, '\0', sizeof (disp_expressions));
3122 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3123 save_stack_p = save_stack;
252b5132
RH		 3124
3125 /* First parse an instruction mnemonic & call i386_operand for the operands.
3126 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3127 start of a (possibly prefixed) mnemonic. */
252b5132 3128
29b0f896
AM		 3129 line = parse_insn (line, mnemonic);
3130 if (line == NULL)
3131 return;
252b5132 3132
29b0f896 3133 line = parse_operands (line, mnemonic);
ee86248c 3134 this_operand = -1;
29b0f896
AM		 3135 if (line == NULL)
3136 return;
252b5132 3137
29b0f896
AM		 3138 /* Now we've parsed the mnemonic into a set of templates, and have the
3139 operands at hand. */
3140
3141 /* All intel opcodes have reversed operands except for "bound" and
3142 "enter". We also don't reverse intersegment "jmp" and "call"
3143 instructions with 2 immediate operands so that the immediate segment
050dfa73 3144 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3145 if (intel_syntax
3146 && i.operands > 1
29b0f896 3147 && (strcmp (mnemonic, "bound") != 0)
30123838 3148 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3149 && !(operand_type_check (i.types[0], imm)
3150 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3151 swap_operands ();
3152
ec56d5c0
JB		 3153 /* The order of the immediates should be reversed
3154 for 2 immediates extrq and insertq instructions */
3155 if (i.imm_operands == 2
3156 && (strcmp (mnemonic, "extrq") == 0
3157 || strcmp (mnemonic, "insertq") == 0))
3158 swap_2_operands (0, 1);
3159
29b0f896
AM		 3160 if (i.imm_operands)
3161 optimize_imm ();
3162
b300c311
L		 3163 /* Don't optimize displacement for movabs since it only takes 64bit
3164 displacement. */
3165 if (i.disp_operands
a501d77e 3166 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3167 && (flag_code != CODE_64BIT
3168 || strcmp (mnemonic, "movabs") != 0))
3169 optimize_disp ();
29b0f896
AM		 3170
3171 /* Next, we find a template that matches the given insn,
3172 making sure the overlap of the given operands types is consistent
3173 with the template operand types. */
252b5132 3174
fa99fab2 3175 if (!(t = match_template ()))
29b0f896 3176 return;
252b5132 3177
7bab8ab5 3178 if (sse_check != check_none
81f8a913 3179 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3180 && (i.tm.cpu_flags.bitfield.cpusse
3181 || i.tm.cpu_flags.bitfield.cpusse2
3182 || i.tm.cpu_flags.bitfield.cpusse3
3183 || i.tm.cpu_flags.bitfield.cpussse3
3184 || i.tm.cpu_flags.bitfield.cpusse4_1
3185 || i.tm.cpu_flags.bitfield.cpusse4_2))
3186 {
7bab8ab5 3187 (sse_check == check_warning
daf50ae7
L		 3188 ? as_warn
3189 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3190 }
3191
321fd21e
L		 3192 /* Zap movzx and movsx suffix. The suffix has been set from
3193 "word ptr" or "byte ptr" on the source operand in Intel syntax
3194 or extracted from mnemonic in AT&T syntax. But we'll use
3195 the destination register to choose the suffix for encoding. */
3196 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3197 {
321fd21e
L		 3198 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3199 there is no suffix, the default will be byte extension. */
3200 if (i.reg_operands != 2
3201 && !i.suffix
7ab9ffdd 3202 && intel_syntax)
321fd21e
L		 3203 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3204
3205 i.suffix = 0;
cd61ebfe 3206 }
24eab124 3207
40fb9820 3208 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3209 if (!add_prefix (FWAIT_OPCODE))
3210 return;
252b5132 3211
c1ba0266
L		 3212 /* Check for lock without a lockable instruction. Destination operand
3213 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3214 if (i.prefix[LOCK_PREFIX]
3215 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3216 || i.mem_operands == 0
3217 || (i.tm.base_opcode != 0x86
3218 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3219 {
3220 as_bad (_("expecting lockable instruction after `lock'"));
3221 return;
3222 }
3223
42164a71
L		 3224 /* Check if HLE prefix is OK. */
3225 if (i.have_hle && !check_hle ())
3226 return;
3227
29b0f896 3228 /* Check string instruction segment overrides. */
40fb9820 3229 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3230 {
3231 if (!check_string ())
5dd0794d 3232 return;
fc0763e6 3233 i.disp_operands = 0;
29b0f896 3234 }
5dd0794d 3235
29b0f896
AM		 3236 if (!process_suffix ())
3237 return;
e413e4e9 3238
bc0844ae
L		 3239 /* Update operand types. */
3240 for (j = 0; j < i.operands; j++)
3241 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3242
29b0f896
AM		 3243 /* Make still unresolved immediate matches conform to size of immediate
3244 given in i.suffix. */
3245 if (!finalize_imm ())
3246 return;
252b5132 3247
40fb9820 3248 if (i.types[0].bitfield.imm1)
29b0f896 3249 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3250
9afe6eb8
L		 3251 /* We only need to check those implicit registers for instructions
3252 with 3 operands or less. */
3253 if (i.operands <= 3)
3254 for (j = 0; j < i.operands; j++)
3255 if (i.types[j].bitfield.inoutportreg
3256 || i.types[j].bitfield.shiftcount
3257 || i.types[j].bitfield.acc
3258 || i.types[j].bitfield.floatacc)
3259 i.reg_operands--;
40fb9820 3260
c0f3af97
L		 3261 /* ImmExt should be processed after SSE2AVX. */
3262 if (!i.tm.opcode_modifier.sse2avx
3263 && i.tm.opcode_modifier.immext)
65da13b5 3264 process_immext ();
252b5132 3265
29b0f896
AM		 3266 /* For insns with operands there are more diddles to do to the opcode. */
3267 if (i.operands)
3268 {
3269 if (!process_operands ())
3270 return;
3271 }
40fb9820 3272 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3273 {
3274 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3275 as_warn (_("translating to `%sp'"), i.tm.name);
3276 }
252b5132 3277
c0f3af97 3278 if (i.tm.opcode_modifier.vex)
fa99fab2 3279 build_vex_prefix (t);
c0f3af97 3280
5dd85c99
SP		 3281 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3282 instructions may define INT_OPCODE as well, so avoid this corner
3283 case for those instructions that use MODRM. */
3284 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3285 && !i.tm.opcode_modifier.modrm
3286 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3287 {
3288 i.tm.base_opcode = INT3_OPCODE;
3289 i.imm_operands = 0;
3290 }
252b5132 3291
40fb9820
L		 3292 if ((i.tm.opcode_modifier.jump
3293 || i.tm.opcode_modifier.jumpbyte
3294 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3295 && i.op[0].disps->X_op == O_constant)
3296 {
3297 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3298 the absolute address given by the constant. Since ix86 jumps and
3299 calls are pc relative, we need to generate a reloc. */
3300 i.op[0].disps->X_add_symbol = &abs_symbol;
3301 i.op[0].disps->X_op = O_symbol;
3302 }
252b5132 3303
40fb9820 3304 if (i.tm.opcode_modifier.rex64)
161a04f6 3305 i.rex |= REX_W;
252b5132 3306
29b0f896
AM		 3307 /* For 8 bit registers we need an empty rex prefix. Also if the
3308 instruction already has a prefix, we need to convert old
3309 registers to new ones. */
773f551c 3310
40fb9820 3311 if ((i.types[0].bitfield.reg8
29b0f896 3312 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3313 || (i.types[1].bitfield.reg8
29b0f896 3314 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3315 || ((i.types[0].bitfield.reg8
3316 || i.types[1].bitfield.reg8)
29b0f896
AM		 3317 && i.rex != 0))
3318 {
3319 int x;
726c5dcd 3320
29b0f896
AM		 3321 i.rex |= REX_OPCODE;
3322 for (x = 0; x < 2; x++)
3323 {
3324 /* Look for 8 bit operand that uses old registers. */
40fb9820 3325 if (i.types[x].bitfield.reg8
29b0f896 3326 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3327 {
29b0f896
AM		 3328 /* In case it is "hi" register, give up. */
3329 if (i.op[x].regs->reg_num > 3)
a540244d 3330 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3331 "instruction requiring REX prefix."),
a540244d 3332 register_prefix, i.op[x].regs->reg_name);
773f551c 3333
29b0f896
AM		 3334 /* Otherwise it is equivalent to the extended register.
3335 Since the encoding doesn't change this is merely
3336 cosmetic cleanup for debug output. */
3337
3338 i.op[x].regs = i.op[x].regs + 8;
773f551c 3339 }
29b0f896
AM		 3340 }
3341 }
773f551c 3342
7ab9ffdd 3343 if (i.rex != 0)
29b0f896
AM		 3344 add_prefix (REX_OPCODE | i.rex);
3345
3346 /* We are ready to output the insn. */
3347 output_insn ();
3348}
3349
3350static char *
e3bb37b5 3351parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3352{
3353 char *l = line;
3354 char *token_start = l;
3355 char *mnem_p;
5c6af06e 3356 int supported;
d3ce72d0 3357 const insn_template *t;
b6169b20 3358 char *dot_p = NULL;
29b0f896
AM		 3359
3360 /* Non-zero if we found a prefix only acceptable with string insns. */
3361 const char *expecting_string_instruction = NULL;
45288df1 3362
29b0f896
AM		 3363 while (1)
3364 {
3365 mnem_p = mnemonic;
3366 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3367 {
b6169b20
L		 3368 if (*mnem_p == '.')
3369 dot_p = mnem_p;
29b0f896
AM		 3370 mnem_p++;
3371 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3372 {
29b0f896
AM		 3373 as_bad (_("no such instruction: `%s'"), token_start);
3374 return NULL;
3375 }
3376 l++;
3377 }
3378 if (!is_space_char (*l)
3379 && *l != END_OF_INSN
e44823cf
JB		 3380 && (intel_syntax
3381 || (*l != PREFIX_SEPARATOR
3382 && *l != ',')))
29b0f896
AM		 3383 {
3384 as_bad (_("invalid character %s in mnemonic"),
3385 output_invalid (*l));
3386 return NULL;
3387 }
3388 if (token_start == l)
3389 {
e44823cf 3390 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3391 as_bad (_("expecting prefix; got nothing"));
3392 else
3393 as_bad (_("expecting mnemonic; got nothing"));
3394 return NULL;
3395 }
45288df1 3396
29b0f896 3397 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3398 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3399
29b0f896
AM		 3400 if (*l != END_OF_INSN
3401 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3402 && current_templates
40fb9820 3403 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3404 {
c6fb90c8 3405 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3406 {
3407 as_bad ((flag_code != CODE_64BIT
3408 ? _("`%s' is only supported in 64-bit mode")
3409 : _("`%s' is not supported in 64-bit mode")),
3410 current_templates->start->name);
3411 return NULL;
3412 }
29b0f896
AM		 3413 /* If we are in 16-bit mode, do not allow addr16 or data16.
3414 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3415 if ((current_templates->start->opcode_modifier.size16
3416 || current_templates->start->opcode_modifier.size32)
29b0f896 3417 && flag_code != CODE_64BIT
40fb9820 3418 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3419 ^ (flag_code == CODE_16BIT)))
3420 {
3421 as_bad (_("redundant %s prefix"),
3422 current_templates->start->name);
3423 return NULL;
45288df1 3424 }
29b0f896
AM		 3425 /* Add prefix, checking for repeated prefixes. */
3426 switch (add_prefix (current_templates->start->base_opcode))
3427 {
c32fa91d 3428 case PREFIX_EXIST:
29b0f896 3429 return NULL;
c32fa91d 3430 case PREFIX_REP:
42164a71
L		 3431 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3432 i.have_hle = 1;
3433 else
3434 expecting_string_instruction = current_templates->start->name;
29b0f896 3435 break;
c32fa91d
L		 3436 default:
3437 break;
29b0f896
AM		 3438 }
3439 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3440 token_start = ++l;
3441 }
3442 else
3443 break;
3444 }
45288df1 3445
30a55f88 3446 if (!current_templates)
b6169b20 3447 {
f8a5c266
L		 3448 /* Check if we should swap operand or force 32bit displacement in
3449 encoding. */
30a55f88
L		 3450 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3451 i.swap_operand = 1;
8d63c93e 3452 else if (mnem_p - 3 == dot_p
a501d77e
L		 3453 && dot_p[1] == 'd'
3454 && dot_p[2] == '8')
3455 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3456 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3457 && dot_p[1] == 'd'
3458 && dot_p[2] == '3'
3459 && dot_p[3] == '2')
a501d77e 3460 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3461 else
3462 goto check_suffix;
3463 mnem_p = dot_p;
3464 *dot_p = '\0';
d3ce72d0 3465 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3466 }
3467
29b0f896
AM		 3468 if (!current_templates)
3469 {
b6169b20 3470check_suffix:
29b0f896
AM		 3471 /* See if we can get a match by trimming off a suffix. */
3472 switch (mnem_p[-1])
3473 {
3474 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3475 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3476 i.suffix = SHORT_MNEM_SUFFIX;
3477 else
29b0f896
AM		 3478 case BYTE_MNEM_SUFFIX:
3479 case QWORD_MNEM_SUFFIX:
3480 i.suffix = mnem_p[-1];
3481 mnem_p[-1] = '\0';
d3ce72d0
NC		 3482 current_templates = (const templates *) hash_find (op_hash,
3483 mnemonic);
29b0f896
AM		 3484 break;
3485 case SHORT_MNEM_SUFFIX:
3486 case LONG_MNEM_SUFFIX:
3487 if (!intel_syntax)
3488 {
3489 i.suffix = mnem_p[-1];
3490 mnem_p[-1] = '\0';
d3ce72d0
NC		 3491 current_templates = (const templates *) hash_find (op_hash,
3492 mnemonic);
29b0f896
AM		 3493 }
3494 break;
252b5132 3495
29b0f896
AM		 3496 /* Intel Syntax. */
3497 case 'd':
3498 if (intel_syntax)
3499 {
9306ca4a 3500 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3501 i.suffix = SHORT_MNEM_SUFFIX;
3502 else
3503 i.suffix = LONG_MNEM_SUFFIX;
3504 mnem_p[-1] = '\0';
d3ce72d0
NC		 3505 current_templates = (const templates *) hash_find (op_hash,
3506 mnemonic);
29b0f896
AM		 3507 }
3508 break;
3509 }
3510 if (!current_templates)
3511 {
3512 as_bad (_("no such instruction: `%s'"), token_start);
3513 return NULL;
3514 }
3515 }
252b5132 3516
40fb9820
L		 3517 if (current_templates->start->opcode_modifier.jump
3518 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3519 {
3520 /* Check for a branch hint. We allow ",pt" and ",pn" for
3521 predict taken and predict not taken respectively.
3522 I'm not sure that branch hints actually do anything on loop
3523 and jcxz insns (JumpByte) for current Pentium4 chips. They
3524 may work in the future and it doesn't hurt to accept them
3525 now. */
3526 if (l[0] == ',' && l[1] == 'p')
3527 {
3528 if (l[2] == 't')
3529 {
3530 if (!add_prefix (DS_PREFIX_OPCODE))
3531 return NULL;
3532 l += 3;
3533 }
3534 else if (l[2] == 'n')
3535 {
3536 if (!add_prefix (CS_PREFIX_OPCODE))
3537 return NULL;
3538 l += 3;
3539 }
3540 }
3541 }
3542 /* Any other comma loses. */
3543 if (*l == ',')
3544 {
3545 as_bad (_("invalid character %s in mnemonic"),
3546 output_invalid (*l));
3547 return NULL;
3548 }
252b5132 3549
29b0f896 3550 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3551 supported = 0;
3552 for (t = current_templates->start; t < current_templates->end; ++t)
3553 {
c0f3af97
L		 3554 supported |= cpu_flags_match (t);
3555 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3556 goto skip;
5c6af06e 3557 }
3629bb00 3558
c0f3af97 3559 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3560 {
3561 as_bad (flag_code == CODE_64BIT
3562 ? _("`%s' is not supported in 64-bit mode")
3563 : _("`%s' is only supported in 64-bit mode"),
3564 current_templates->start->name);
3565 return NULL;
3566 }
c0f3af97 3567 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3568 {
3629bb00 3569 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3570 current_templates->start->name,
41aacd83 3571 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3572 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3573 return NULL;
29b0f896 3574 }
3629bb00
L		 3575
3576skip:
3577 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3578 && (flag_code != CODE_16BIT))
29b0f896
AM		 3579 {
3580 as_warn (_("use .code16 to ensure correct addressing mode"));
3581 }
252b5132 3582
29c048b6 3583 /* Check for rep/repne without a string (or other allowed) instruction. */
f41bbced 3584 if (expecting_string_instruction)
29b0f896 3585 {
f41bbced
JB		 3586 static templates override;
3587
3588 for (t = current_templates->start; t < current_templates->end; ++t)
29c048b6 3589 if (t->opcode_modifier.repprefixok)
f41bbced
JB		 3590 break;
3591 if (t >= current_templates->end)
3592 {
3593 as_bad (_("expecting string instruction after `%s'"),
64e74474 3594 expecting_string_instruction);
f41bbced
JB		 3595 return NULL;
3596 }
3597 for (override.start = t; t < current_templates->end; ++t)
29c048b6 3598 if (!t->opcode_modifier.repprefixok)
f41bbced
JB		 3599 break;
3600 override.end = t;
3601 current_templates = &override;
29b0f896 3602 }
252b5132 3603
29b0f896
AM		 3604 return l;
3605}
252b5132 3606
29b0f896 3607static char *
e3bb37b5 3608parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3609{
3610 char *token_start;
3138f287 3611
29b0f896
AM		 3612 /* 1 if operand is pending after ','. */
3613 unsigned int expecting_operand = 0;
252b5132 3614
29b0f896
AM		 3615 /* Non-zero if operand parens not balanced. */
3616 unsigned int paren_not_balanced;
3617
3618 while (*l != END_OF_INSN)
3619 {
3620 /* Skip optional white space before operand. */
3621 if (is_space_char (*l))
3622 ++l;
3623 if (!is_operand_char (*l) && *l != END_OF_INSN)
3624 {
3625 as_bad (_("invalid character %s before operand %d"),
3626 output_invalid (*l),
3627 i.operands + 1);
3628 return NULL;
3629 }
3630 token_start = l; /* after white space */
3631 paren_not_balanced = 0;
3632 while (paren_not_balanced || *l != ',')
3633 {
3634 if (*l == END_OF_INSN)
3635 {
3636 if (paren_not_balanced)
3637 {
3638 if (!intel_syntax)
3639 as_bad (_("unbalanced parenthesis in operand %d."),
3640 i.operands + 1);
3641 else
3642 as_bad (_("unbalanced brackets in operand %d."),
3643 i.operands + 1);
3644 return NULL;
3645 }
3646 else
3647 break; /* we are done */
3648 }
3649 else if (!is_operand_char (*l) && !is_space_char (*l))
3650 {
3651 as_bad (_("invalid character %s in operand %d"),
3652 output_invalid (*l),
3653 i.operands + 1);
3654 return NULL;
3655 }
3656 if (!intel_syntax)
3657 {
3658 if (*l == '(')
3659 ++paren_not_balanced;
3660 if (*l == ')')
3661 --paren_not_balanced;
3662 }
3663 else
3664 {
3665 if (*l == '[')
3666 ++paren_not_balanced;
3667 if (*l == ']')
3668 --paren_not_balanced;
3669 }
3670 l++;
3671 }
3672 if (l != token_start)
3673 { /* Yes, we've read in another operand. */
3674 unsigned int operand_ok;
3675 this_operand = i.operands++;
7d5e4556 3676 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3677 if (i.operands > MAX_OPERANDS)
3678 {
3679 as_bad (_("spurious operands; (%d operands/instruction max)"),
3680 MAX_OPERANDS);
3681 return NULL;
3682 }
3683 /* Now parse operand adding info to 'i' as we go along. */
3684 END_STRING_AND_SAVE (l);
3685
3686 if (intel_syntax)
3687 operand_ok =
3688 i386_intel_operand (token_start,
3689 intel_float_operand (mnemonic));
3690 else
a7619375 3691 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3692
3693 RESTORE_END_STRING (l);
3694 if (!operand_ok)
3695 return NULL;
3696 }
3697 else
3698 {
3699 if (expecting_operand)
3700 {
3701 expecting_operand_after_comma:
3702 as_bad (_("expecting operand after ','; got nothing"));
3703 return NULL;
3704 }
3705 if (*l == ',')
3706 {
3707 as_bad (_("expecting operand before ','; got nothing"));
3708 return NULL;
3709 }
3710 }
7f3f1ea2 3711
29b0f896
AM		 3712 /* Now *l must be either ',' or END_OF_INSN. */
3713 if (*l == ',')
3714 {
3715 if (*++l == END_OF_INSN)
3716 {
3717 /* Just skip it, if it's \n complain. */
3718 goto expecting_operand_after_comma;
3719 }
3720 expecting_operand = 1;
3721 }
3722 }
3723 return l;
3724}
7f3f1ea2 3725
050dfa73 3726static void
4d456e3d 3727swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3728{
3729 union i386_op temp_op;
40fb9820 3730 i386_operand_type temp_type;
050dfa73 3731 enum bfd_reloc_code_real temp_reloc;
4eed87de 3732
050dfa73
MM		 3733 temp_type = i.types[xchg2];
3734 i.types[xchg2] = i.types[xchg1];
3735 i.types[xchg1] = temp_type;
3736 temp_op = i.op[xchg2];
3737 i.op[xchg2] = i.op[xchg1];
3738 i.op[xchg1] = temp_op;
3739 temp_reloc = i.reloc[xchg2];
3740 i.reloc[xchg2] = i.reloc[xchg1];
3741 i.reloc[xchg1] = temp_reloc;
3742}
3743
29b0f896 3744static void
e3bb37b5 3745swap_operands (void)
29b0f896 3746{
b7c61d9a 3747 switch (i.operands)
050dfa73 3748 {
c0f3af97 3749 case 5:
b7c61d9a 3750 case 4:
4d456e3d 3751 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3752 case 3:
3753 case 2:
4d456e3d 3754 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3755 break;
3756 default:
3757 abort ();
29b0f896 3758 }
29b0f896
AM		 3759
3760 if (i.mem_operands == 2)
3761 {
3762 const seg_entry *temp_seg;
3763 temp_seg = i.seg[0];
3764 i.seg[0] = i.seg[1];
3765 i.seg[1] = temp_seg;
3766 }
3767}
252b5132 3768
29b0f896
AM		 3769/* Try to ensure constant immediates are represented in the smallest
3770 opcode possible. */
3771static void
e3bb37b5 3772optimize_imm (void)
29b0f896
AM		 3773{
3774 char guess_suffix = 0;
3775 int op;
252b5132 3776
29b0f896
AM		 3777 if (i.suffix)
3778 guess_suffix = i.suffix;
3779 else if (i.reg_operands)
3780 {
3781 /* Figure out a suffix from the last register operand specified.
3782 We can't do this properly yet, ie. excluding InOutPortReg,
3783 but the following works for instructions with immediates.
3784 In any case, we can't set i.suffix yet. */
3785 for (op = i.operands; --op >= 0;)
40fb9820 3786 if (i.types[op].bitfield.reg8)
7ab9ffdd 3787 {
40fb9820
L		 3788 guess_suffix = BYTE_MNEM_SUFFIX;
3789 break;
3790 }
3791 else if (i.types[op].bitfield.reg16)
252b5132 3792 {
40fb9820
L		 3793 guess_suffix = WORD_MNEM_SUFFIX;
3794 break;
3795 }
3796 else if (i.types[op].bitfield.reg32)
3797 {
3798 guess_suffix = LONG_MNEM_SUFFIX;
3799 break;
3800 }
3801 else if (i.types[op].bitfield.reg64)
3802 {
3803 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3804 break;
252b5132 3805 }
29b0f896
AM		 3806 }
3807 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3808 guess_suffix = WORD_MNEM_SUFFIX;
3809
3810 for (op = i.operands; --op >= 0;)
40fb9820 3811 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3812 {
3813 switch (i.op[op].imms->X_op)
252b5132 3814 {
29b0f896
AM		 3815 case O_constant:
3816 /* If a suffix is given, this operand may be shortened. */
3817 switch (guess_suffix)
252b5132 3818 {
29b0f896 3819 case LONG_MNEM_SUFFIX:
40fb9820
L		 3820 i.types[op].bitfield.imm32 = 1;
3821 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3822 break;
3823 case WORD_MNEM_SUFFIX:
40fb9820
L		 3824 i.types[op].bitfield.imm16 = 1;
3825 i.types[op].bitfield.imm32 = 1;
3826 i.types[op].bitfield.imm32s = 1;
3827 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3828 break;
3829 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3830 i.types[op].bitfield.imm8 = 1;
3831 i.types[op].bitfield.imm8s = 1;
3832 i.types[op].bitfield.imm16 = 1;
3833 i.types[op].bitfield.imm32 = 1;
3834 i.types[op].bitfield.imm32s = 1;
3835 i.types[op].bitfield.imm64 = 1;
29b0f896 3836 break;
252b5132 3837 }
252b5132 3838
29b0f896
AM		 3839 /* If this operand is at most 16 bits, convert it
3840 to a signed 16 bit number before trying to see
3841 whether it will fit in an even smaller size.
3842 This allows a 16-bit operand such as $0xffe0 to
3843 be recognised as within Imm8S range. */
40fb9820 3844 if ((i.types[op].bitfield.imm16)
29b0f896 3845 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3846 {
29b0f896
AM		 3847 i.op[op].imms->X_add_number =
3848 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3849 }
40fb9820 3850 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3851 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3852 == 0))
3853 {
3854 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3855 ^ ((offsetT) 1 << 31))
3856 - ((offsetT) 1 << 31));
3857 }
40fb9820 3858 i.types[op]
c6fb90c8
L		 3859 = operand_type_or (i.types[op],
3860 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3861
29b0f896
AM		 3862 /* We must avoid matching of Imm32 templates when 64bit
3863 only immediate is available. */
3864 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3865 i.types[op].bitfield.imm32 = 0;
29b0f896 3866 break;
252b5132 3867
29b0f896
AM		 3868 case O_absent:
3869 case O_register:
3870 abort ();
3871
3872 /* Symbols and expressions. */
3873 default:
9cd96992
JB		 3874 /* Convert symbolic operand to proper sizes for matching, but don't
3875 prevent matching a set of insns that only supports sizes other
3876 than those matching the insn suffix. */
3877 {
40fb9820 3878 i386_operand_type mask, allowed;
d3ce72d0 3879 const insn_template *t;
9cd96992 3880
0dfbf9d7
L		 3881 operand_type_set (&mask, 0);
3882 operand_type_set (&allowed, 0);
40fb9820 3883
4eed87de
AM		 3884 for (t = current_templates->start;
3885 t < current_templates->end;
3886 ++t)
c6fb90c8
L		 3887 allowed = operand_type_or (allowed,
3888 t->operand_types[op]);
9cd96992
JB		 3889 switch (guess_suffix)
3890 {
3891 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3892 mask.bitfield.imm64 = 1;
3893 mask.bitfield.imm32s = 1;
9cd96992
JB		 3894 break;
3895 case LONG_MNEM_SUFFIX:
40fb9820 3896 mask.bitfield.imm32 = 1;
9cd96992
JB		 3897 break;
3898 case WORD_MNEM_SUFFIX:
40fb9820 3899 mask.bitfield.imm16 = 1;
9cd96992
JB		 3900 break;
3901 case BYTE_MNEM_SUFFIX:
40fb9820 3902 mask.bitfield.imm8 = 1;
9cd96992
JB		 3903 break;
3904 default:
9cd96992
JB		 3905 break;
3906 }
c6fb90c8 3907 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3908 if (!operand_type_all_zero (&allowed))
c6fb90c8 3909 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3910 }
29b0f896 3911 break;
252b5132 3912 }
29b0f896
AM		 3913 }
3914}
47926f60 3915
29b0f896
AM		 3916/* Try to use the smallest displacement type too. */
3917static void
e3bb37b5 3918optimize_disp (void)
29b0f896
AM		 3919{
3920 int op;
3e73aa7c 3921
29b0f896 3922 for (op = i.operands; --op >= 0;)
40fb9820 3923 if (operand_type_check (i.types[op], disp))
252b5132 3924 {
b300c311 3925 if (i.op[op].disps->X_op == O_constant)
252b5132 3926 {
91d6fa6a 3927 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3928
40fb9820 3929 if (i.types[op].bitfield.disp16
91d6fa6a 3930 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3931 {
3932 /* If this operand is at most 16 bits, convert
3933 to a signed 16 bit number and don't use 64bit
3934 displacement. */
91d6fa6a 3935 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3936 i.types[op].bitfield.disp64 = 0;
b300c311 3937 }
40fb9820 3938 if (i.types[op].bitfield.disp32
91d6fa6a 3939 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3940 {
3941 /* If this operand is at most 32 bits, convert
3942 to a signed 32 bit number and don't use 64bit
3943 displacement. */
91d6fa6a
NC		 3944 op_disp &= (((offsetT) 2 << 31) - 1);
3945 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3946 i.types[op].bitfield.disp64 = 0;
b300c311 3947 }
91d6fa6a 3948 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3949 {
40fb9820
L		 3950 i.types[op].bitfield.disp8 = 0;
3951 i.types[op].bitfield.disp16 = 0;
3952 i.types[op].bitfield.disp32 = 0;
3953 i.types[op].bitfield.disp32s = 0;
3954 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3955 i.op[op].disps = 0;
3956 i.disp_operands--;
3957 }
3958 else if (flag_code == CODE_64BIT)
3959 {
91d6fa6a 3960 if (fits_in_signed_long (op_disp))
28a9d8f5 3961 {
40fb9820
L		 3962 i.types[op].bitfield.disp64 = 0;
3963 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3964 }
0e1147d9 3965 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3966 && fits_in_unsigned_long (op_disp))
40fb9820 3967 i.types[op].bitfield.disp32 = 1;
b300c311 3968 }
40fb9820
L		 3969 if ((i.types[op].bitfield.disp32
3970 || i.types[op].bitfield.disp32s
3971 || i.types[op].bitfield.disp16)
91d6fa6a 3972 && fits_in_signed_byte (op_disp))
40fb9820 3973 i.types[op].bitfield.disp8 = 1;
252b5132 3974 }
67a4f2b7
AO		 3975 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3976 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3977 {
3978 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3979 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3980 i.types[op].bitfield.disp8 = 0;
3981 i.types[op].bitfield.disp16 = 0;
3982 i.types[op].bitfield.disp32 = 0;
3983 i.types[op].bitfield.disp32s = 0;
3984 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3985 }
3986 else
b300c311 3987 /* We only support 64bit displacement on constants. */
40fb9820 3988 i.types[op].bitfield.disp64 = 0;
252b5132 3989 }
29b0f896
AM		 3990}
3991
6c30d220
L		 3992/* Check if operands are valid for the instruction. */
3993
3994static int
3995check_VecOperands (const insn_template *t)
3996{
3997 /* Without VSIB byte, we can't have a vector register for index. */
3998 if (!t->opcode_modifier.vecsib
3999 && i.index_reg
4000 && (i.index_reg->reg_type.bitfield.regxmm
4001 || i.index_reg->reg_type.bitfield.regymm))
4002 {
4003 i.error = unsupported_vector_index_register;
4004 return 1;
4005 }
4006
7bab8ab5
JB		 4007 /* For VSIB byte, we need a vector register for index, and all vector
4008 registers must be distinct. */
4009 if (t->opcode_modifier.vecsib)
4010 {
4011 if (!i.index_reg
6c30d220
L		 4012 || !((t->opcode_modifier.vecsib == VecSIB128
4013 && i.index_reg->reg_type.bitfield.regxmm)
4014 || (t->opcode_modifier.vecsib == VecSIB256
7bab8ab5
JB		 4015 && i.index_reg->reg_type.bitfield.regymm)))
4016 {
4017 i.error = invalid_vsib_address;
4018 return 1;
4019 }
4020
4021 gas_assert (i.reg_operands == 2);
4022 gas_assert (i.types[0].bitfield.regxmm
4023 || i.types[0].bitfield.regymm);
4024 gas_assert (i.types[2].bitfield.regxmm
4025 || i.types[2].bitfield.regymm);
4026
4027 if (operand_check == check_none)
4028 return 0;
4029 if (register_number (i.op[0].regs) != register_number (i.index_reg)
4030 && register_number (i.op[2].regs) != register_number (i.index_reg)
4031 && register_number (i.op[0].regs) != register_number (i.op[2].regs))
4032 return 0;
4033 if (operand_check == check_error)
4034 {
4035 i.error = invalid_vector_register_set;
4036 return 1;
4037 }
4038 as_warn (_("mask, index, and destination registers should be distinct"));
6c30d220
L		 4039 }
4040
4041 return 0;
4042}
4043
43f3e2ee 4044/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4045 operand types. */
4046
4047static int
4048VEX_check_operands (const insn_template *t)
4049{
4050 if (!t->opcode_modifier.vex)
4051 return 0;
4052
4053 /* Only check VEX_Imm4, which must be the first operand. */
4054 if (t->operand_types[0].bitfield.vec_imm4)
4055 {
4056 if (i.op[0].imms->X_op != O_constant
4057 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4058 {
a65babc9 4059 i.error = bad_imm4;
891edac4
L		 4060 return 1;
4061 }
a683cc34
SP		 4062
4063 /* Turn off Imm8 so that update_imm won't complain. */
4064 i.types[0] = vec_imm4;
4065 }
4066
4067 return 0;
4068}
4069
d3ce72d0 4070static const insn_template *
e3bb37b5 4071match_template (void)
29b0f896
AM		 4072{
4073 /* Points to template once we've found it. */
d3ce72d0 4074 const insn_template *t;
40fb9820 4075 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4076 i386_operand_type overlap4;
29b0f896 4077 unsigned int found_reverse_match;
40fb9820
L		 4078 i386_opcode_modifier suffix_check;
4079 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4080 int addr_prefix_disp;
a5c311ca 4081 unsigned int j;
3629bb00 4082 unsigned int found_cpu_match;
45664ddb 4083 unsigned int check_register;
5614d22c 4084 enum i386_error specific_error = 0;
29b0f896 4085
c0f3af97
L		 4086#if MAX_OPERANDS != 5
4087# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4088#endif
4089
29b0f896 4090 found_reverse_match = 0;
539e75ad 4091 addr_prefix_disp = -1;
40fb9820
L		 4092
4093 memset (&suffix_check, 0, sizeof (suffix_check));
4094 if (i.suffix == BYTE_MNEM_SUFFIX)
4095 suffix_check.no_bsuf = 1;
4096 else if (i.suffix == WORD_MNEM_SUFFIX)
4097 suffix_check.no_wsuf = 1;
4098 else if (i.suffix == SHORT_MNEM_SUFFIX)
4099 suffix_check.no_ssuf = 1;
4100 else if (i.suffix == LONG_MNEM_SUFFIX)
4101 suffix_check.no_lsuf = 1;
4102 else if (i.suffix == QWORD_MNEM_SUFFIX)
4103 suffix_check.no_qsuf = 1;
4104 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4105 suffix_check.no_ldsuf = 1;
29b0f896 4106
01559ecc
L		 4107 /* Must have right number of operands. */
4108 i.error = number_of_operands_mismatch;
4109
45aa61fe 4110 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4111 {
539e75ad
L		 4112 addr_prefix_disp = -1;
4113
29b0f896
AM		 4114 if (i.operands != t->operands)
4115 continue;
4116
50aecf8c 4117 /* Check processor support. */
a65babc9 4118 i.error = unsupported;
c0f3af97
L		 4119 found_cpu_match = (cpu_flags_match (t)
4120 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4121 if (!found_cpu_match)
4122 continue;
4123
e1d4d893 4124 /* Check old gcc support. */
a65babc9 4125 i.error = old_gcc_only;
e1d4d893
L		 4126 if (!old_gcc && t->opcode_modifier.oldgcc)
4127 continue;
4128
4129 /* Check AT&T mnemonic. */
a65babc9 4130 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4131 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4132 continue;
4133
891edac4 4134 /* Check AT&T/Intel syntax. */
a65babc9 4135 i.error = unsupported_syntax;
5c07affc
L		 4136 if ((intel_syntax && t->opcode_modifier.attsyntax)
4137 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4138 continue;
4139
20592a94 4140 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4141 i.error = invalid_instruction_suffix;
567e4e96
L		 4142 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4143 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4144 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4145 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4146 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4147 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4148 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4149 continue;
4150
5c07affc 4151 if (!operand_size_match (t))
7d5e4556 4152 continue;
539e75ad 4153
5c07affc
L		 4154 for (j = 0; j < MAX_OPERANDS; j++)
4155 operand_types[j] = t->operand_types[j];
4156
45aa61fe
AM		 4157 /* In general, don't allow 64-bit operands in 32-bit mode. */
4158 if (i.suffix == QWORD_MNEM_SUFFIX
4159 && flag_code != CODE_64BIT
4160 && (intel_syntax
40fb9820 4161 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4162 && !intel_float_operand (t->name))
4163 : intel_float_operand (t->name) != 2)
40fb9820 4164 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 4165 && !operand_types[0].bitfield.regxmm
4166 && !operand_types[0].bitfield.regymm)
40fb9820 4167 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 4168 && !!operand_types[t->operands > 1].bitfield.regxmm
4169 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 4170 && (t->base_opcode != 0x0fc7
4171 || t->extension_opcode != 1 /* cmpxchg8b */))
4172 continue;
4173
192dc9c6
JB		 4174 /* In general, don't allow 32-bit operands on pre-386. */
4175 else if (i.suffix == LONG_MNEM_SUFFIX
4176 && !cpu_arch_flags.bitfield.cpui386
4177 && (intel_syntax
4178 ? (!t->opcode_modifier.ignoresize
4179 && !intel_float_operand (t->name))
4180 : intel_float_operand (t->name) != 2)
4181 && ((!operand_types[0].bitfield.regmmx
4182 && !operand_types[0].bitfield.regxmm)
4183 || (!operand_types[t->operands > 1].bitfield.regmmx
4184 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4185 continue;
4186
29b0f896 4187 /* Do not verify operands when there are none. */
50aecf8c 4188 else
29b0f896 4189 {
c6fb90c8 4190 if (!t->operands)
2dbab7d5
L		 4191 /* We've found a match; break out of loop. */
4192 break;
29b0f896 4193 }
252b5132 4194
539e75ad
L		 4195 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4196 into Disp32/Disp16/Disp32 operand. */
4197 if (i.prefix[ADDR_PREFIX] != 0)
4198 {
40fb9820 4199 /* There should be only one Disp operand. */
539e75ad
L		 4200 switch (flag_code)
4201 {
4202 case CODE_16BIT:
40fb9820
L		 4203 for (j = 0; j < MAX_OPERANDS; j++)
4204 {
4205 if (operand_types[j].bitfield.disp16)
4206 {
4207 addr_prefix_disp = j;
4208 operand_types[j].bitfield.disp32 = 1;
4209 operand_types[j].bitfield.disp16 = 0;
4210 break;
4211 }
4212 }
539e75ad
L		 4213 break;
4214 case CODE_32BIT:
40fb9820
L		 4215 for (j = 0; j < MAX_OPERANDS; j++)
4216 {
4217 if (operand_types[j].bitfield.disp32)
4218 {
4219 addr_prefix_disp = j;
4220 operand_types[j].bitfield.disp32 = 0;
4221 operand_types[j].bitfield.disp16 = 1;
4222 break;
4223 }
4224 }
539e75ad
L		 4225 break;
4226 case CODE_64BIT:
40fb9820
L		 4227 for (j = 0; j < MAX_OPERANDS; j++)
4228 {
4229 if (operand_types[j].bitfield.disp64)
4230 {
4231 addr_prefix_disp = j;
4232 operand_types[j].bitfield.disp64 = 0;
4233 operand_types[j].bitfield.disp32 = 1;
4234 break;
4235 }
4236 }
539e75ad
L		 4237 break;
4238 }
539e75ad
L		 4239 }
4240
56ffb741
L		 4241 /* We check register size if needed. */
4242 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4243 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4244 switch (t->operands)
4245 {
4246 case 1:
40fb9820 4247 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4248 continue;
4249 break;
4250 case 2:
8b38ad71
L		 4251 /* xchg %eax, %eax is a special case. It is an aliase for nop
4252 only in 32bit mode and we can use opcode 0x90. In 64bit
4253 mode, we can't use 0x90 for xchg %eax, %eax since it should
4254 zero-extend %eax to %rax. */
4255 if (flag_code == CODE_64BIT
4256 && t->base_opcode == 0x90
0dfbf9d7
L		 4257 && operand_type_equal (&i.types [0], &acc32)
4258 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4259 continue;
b6169b20
L		 4260 if (i.swap_operand)
4261 {
4262 /* If we swap operand in encoding, we either match
4263 the next one or reverse direction of operands. */
4264 if (t->opcode_modifier.s)
4265 continue;
4266 else if (t->opcode_modifier.d)
4267 goto check_reverse;
4268 }
4269
29b0f896 4270 case 3:
fa99fab2
L		 4271 /* If we swap operand in encoding, we match the next one. */
4272 if (i.swap_operand && t->opcode_modifier.s)
4273 continue;
f48ff2ae 4274 case 4:
c0f3af97 4275 case 5:
c6fb90c8 4276 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4277 if (!operand_type_match (overlap0, i.types[0])
4278 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4279 || (check_register
4280 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4281 operand_types[0],
4282 overlap1, i.types[1],
4283 operand_types[1])))
29b0f896
AM		 4284 {
4285 /* Check if other direction is valid ... */
40fb9820 4286 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4287 continue;
4288
b6169b20 4289check_reverse:
29b0f896 4290 /* Try reversing direction of operands. */
c6fb90c8
L		 4291 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4292 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4293 if (!operand_type_match (overlap0, i.types[0])
4294 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4295 || (check_register
4296 && !operand_type_register_match (overlap0,
4297 i.types[0],
4298 operand_types[1],
4299 overlap1,
4300 i.types[1],
4301 operand_types[0])))
29b0f896
AM		 4302 {
4303 /* Does not match either direction. */
4304 continue;
4305 }
4306 /* found_reverse_match holds which of D or FloatDR
4307 we've found. */
40fb9820 4308 if (t->opcode_modifier.d)
8a2ed489 4309 found_reverse_match = Opcode_D;
40fb9820 4310 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4311 found_reverse_match = Opcode_FloatD;
4312 else
4313 found_reverse_match = 0;
40fb9820 4314 if (t->opcode_modifier.floatr)
8a2ed489 4315 found_reverse_match |= Opcode_FloatR;
29b0f896 4316 }
f48ff2ae 4317 else
29b0f896 4318 {
f48ff2ae 4319 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4320 switch (t->operands)
4321 {
c0f3af97
L		 4322 case 5:
4323 overlap4 = operand_type_and (i.types[4],
4324 operand_types[4]);
d1cbb4db 4325 case 4:
c6fb90c8
L		 4326 overlap3 = operand_type_and (i.types[3],
4327 operand_types[3]);
d1cbb4db 4328 case 3:
c6fb90c8
L		 4329 overlap2 = operand_type_and (i.types[2],
4330 operand_types[2]);
d1cbb4db
L		 4331 break;
4332 }
29b0f896 4333
f48ff2ae
L		 4334 switch (t->operands)
4335 {
c0f3af97
L		 4336 case 5:
4337 if (!operand_type_match (overlap4, i.types[4])
4338 || !operand_type_register_match (overlap3,
4339 i.types[3],
4340 operand_types[3],
4341 overlap4,
4342 i.types[4],
4343 operand_types[4]))
4344 continue;
f48ff2ae 4345 case 4:
40fb9820 4346 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4347 || (check_register
4348 && !operand_type_register_match (overlap2,
4349 i.types[2],
4350 operand_types[2],
4351 overlap3,
4352 i.types[3],
4353 operand_types[3])))
f48ff2ae
L		 4354 continue;
4355 case 3:
4356 /* Here we make use of the fact that there are no
4357 reverse match 3 operand instructions, and all 3
4358 operand instructions only need to be checked for
4359 register consistency between operands 2 and 3. */
40fb9820 4360 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4361 || (check_register
4362 && !operand_type_register_match (overlap1,
4363 i.types[1],
4364 operand_types[1],
4365 overlap2,
4366 i.types[2],
4367 operand_types[2])))
f48ff2ae
L		 4368 continue;
4369 break;
4370 }
29b0f896 4371 }
f48ff2ae 4372 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4373 slip through to break. */
4374 }
3629bb00 4375 if (!found_cpu_match)
29b0f896
AM		 4376 {
4377 found_reverse_match = 0;
4378 continue;
4379 }
c0f3af97 4380
5614d22c
JB		 4381 /* Check if vector and VEX operands are valid. */
4382 if (check_VecOperands (t) || VEX_check_operands (t))
4383 {
4384 specific_error = i.error;
4385 continue;
4386 }
a683cc34 4387
29b0f896
AM		 4388 /* We've found a match; break out of loop. */
4389 break;
4390 }
4391
4392 if (t == current_templates->end)
4393 {
4394 /* We found no match. */
a65babc9 4395 const char *err_msg;
5614d22c 4396 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4397 {
4398 default:
4399 abort ();
86e026a4 4400 case operand_size_mismatch:
a65babc9
L		 4401 err_msg = _("operand size mismatch");
4402 break;
4403 case operand_type_mismatch:
4404 err_msg = _("operand type mismatch");
4405 break;
4406 case register_type_mismatch:
4407 err_msg = _("register type mismatch");
4408 break;
4409 case number_of_operands_mismatch:
4410 err_msg = _("number of operands mismatch");
4411 break;
4412 case invalid_instruction_suffix:
4413 err_msg = _("invalid instruction suffix");
4414 break;
4415 case bad_imm4:
4a2608e3 4416 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4417 break;
4418 case old_gcc_only:
4419 err_msg = _("only supported with old gcc");
4420 break;
4421 case unsupported_with_intel_mnemonic:
4422 err_msg = _("unsupported with Intel mnemonic");
4423 break;
4424 case unsupported_syntax:
4425 err_msg = _("unsupported syntax");
4426 break;
4427 case unsupported:
35262a23 4428 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4429 current_templates->start->name);
4430 return NULL;
6c30d220
L		 4431 case invalid_vsib_address:
4432 err_msg = _("invalid VSIB address");
4433 break;
7bab8ab5
JB		 4434 case invalid_vector_register_set:
4435 err_msg = _("mask, index, and destination registers must be distinct");
4436 break;
6c30d220
L		 4437 case unsupported_vector_index_register:
4438 err_msg = _("unsupported vector index register");
4439 break;
a65babc9
L		 4440 }
4441 as_bad (_("%s for `%s'"), err_msg,
891edac4 4442 current_templates->start->name);
fa99fab2 4443 return NULL;
29b0f896 4444 }
252b5132 4445
29b0f896
AM		 4446 if (!quiet_warnings)
4447 {
4448 if (!intel_syntax
40fb9820
L		 4449 && (i.types[0].bitfield.jumpabsolute
4450 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4451 {
4452 as_warn (_("indirect %s without `*'"), t->name);
4453 }
4454
40fb9820
L		 4455 if (t->opcode_modifier.isprefix
4456 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4457 {
4458 /* Warn them that a data or address size prefix doesn't
4459 affect assembly of the next line of code. */
4460 as_warn (_("stand-alone `%s' prefix"), t->name);
4461 }
4462 }
4463
4464 /* Copy the template we found. */
4465 i.tm = *t;
539e75ad
L		 4466
4467 if (addr_prefix_disp != -1)
4468 i.tm.operand_types[addr_prefix_disp]
4469 = operand_types[addr_prefix_disp];
4470
29b0f896
AM		 4471 if (found_reverse_match)
4472 {
4473 /* If we found a reverse match we must alter the opcode
4474 direction bit. found_reverse_match holds bits to change
4475 (different for int & float insns). */
4476
4477 i.tm.base_opcode ^= found_reverse_match;
4478
539e75ad
L		 4479 i.tm.operand_types[0] = operand_types[1];
4480 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4481 }
4482
fa99fab2 4483 return t;
29b0f896
AM		 4484}
4485
4486static int
e3bb37b5 4487check_string (void)
29b0f896 4488{
40fb9820
L		 4489 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4490 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4491 {
4492 if (i.seg[0] != NULL && i.seg[0] != &es)
4493 {
a87af027 4494 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4495 i.tm.name,
a87af027
JB		 4496 mem_op + 1,
4497 register_prefix);
29b0f896
AM		 4498 return 0;
4499 }
4500 /* There's only ever one segment override allowed per instruction.
4501 This instruction possibly has a legal segment override on the
4502 second operand, so copy the segment to where non-string
4503 instructions store it, allowing common code. */
4504 i.seg[0] = i.seg[1];
4505 }
40fb9820 4506 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4507 {
4508 if (i.seg[1] != NULL && i.seg[1] != &es)
4509 {
a87af027 4510 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4511 i.tm.name,
a87af027
JB		 4512 mem_op + 2,
4513 register_prefix);
29b0f896
AM		 4514 return 0;
4515 }
4516 }
4517 return 1;
4518}
4519
4520static int
543613e9 4521process_suffix (void)
29b0f896
AM		 4522{
4523 /* If matched instruction specifies an explicit instruction mnemonic
4524 suffix, use it. */
40fb9820
L		 4525 if (i.tm.opcode_modifier.size16)
4526 i.suffix = WORD_MNEM_SUFFIX;
4527 else if (i.tm.opcode_modifier.size32)
4528 i.suffix = LONG_MNEM_SUFFIX;
4529 else if (i.tm.opcode_modifier.size64)
4530 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4531 else if (i.reg_operands)
4532 {
4533 /* If there's no instruction mnemonic suffix we try to invent one
4534 based on register operands. */
4535 if (!i.suffix)
4536 {
4537 /* We take i.suffix from the last register operand specified,
4538 Destination register type is more significant than source
381d071f
L		 4539 register type. crc32 in SSE4.2 prefers source register
4540 type. */
4541 if (i.tm.base_opcode == 0xf20f38f1)
4542 {
40fb9820
L		 4543 if (i.types[0].bitfield.reg16)
4544 i.suffix = WORD_MNEM_SUFFIX;
4545 else if (i.types[0].bitfield.reg32)
4546 i.suffix = LONG_MNEM_SUFFIX;
4547 else if (i.types[0].bitfield.reg64)
4548 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4549 }
9344ff29 4550 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4551 {
40fb9820 4552 if (i.types[0].bitfield.reg8)
20592a94
L		 4553 i.suffix = BYTE_MNEM_SUFFIX;
4554 }
381d071f
L		 4555
4556 if (!i.suffix)
4557 {
4558 int op;
4559
20592a94
L		 4560 if (i.tm.base_opcode == 0xf20f38f1
4561 || i.tm.base_opcode == 0xf20f38f0)
4562 {
4563 /* We have to know the operand size for crc32. */
4564 as_bad (_("ambiguous memory operand size for `%s`"),
4565 i.tm.name);
4566 return 0;
4567 }
4568
381d071f 4569 for (op = i.operands; --op >= 0;)
40fb9820 4570 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4571 {
40fb9820
L		 4572 if (i.types[op].bitfield.reg8)
4573 {
4574 i.suffix = BYTE_MNEM_SUFFIX;
4575 break;
4576 }
4577 else if (i.types[op].bitfield.reg16)
4578 {
4579 i.suffix = WORD_MNEM_SUFFIX;
4580 break;
4581 }
4582 else if (i.types[op].bitfield.reg32)
4583 {
4584 i.suffix = LONG_MNEM_SUFFIX;
4585 break;
4586 }
4587 else if (i.types[op].bitfield.reg64)
4588 {
4589 i.suffix = QWORD_MNEM_SUFFIX;
4590 break;
4591 }
381d071f
L		 4592 }
4593 }
29b0f896
AM		 4594 }
4595 else if (i.suffix == BYTE_MNEM_SUFFIX)
4596 {
2eb952a4
L		 4597 if (intel_syntax
4598 && i.tm.opcode_modifier.ignoresize
4599 && i.tm.opcode_modifier.no_bsuf)
4600 i.suffix = 0;
4601 else if (!check_byte_reg ())
29b0f896
AM		 4602 return 0;
4603 }
4604 else if (i.suffix == LONG_MNEM_SUFFIX)
4605 {
2eb952a4
L		 4606 if (intel_syntax
4607 && i.tm.opcode_modifier.ignoresize
4608 && i.tm.opcode_modifier.no_lsuf)
4609 i.suffix = 0;
4610 else if (!check_long_reg ())
29b0f896
AM		 4611 return 0;
4612 }
4613 else if (i.suffix == QWORD_MNEM_SUFFIX)
4614 {
955e1e6a
L		 4615 if (intel_syntax
4616 && i.tm.opcode_modifier.ignoresize
4617 && i.tm.opcode_modifier.no_qsuf)
4618 i.suffix = 0;
4619 else if (!check_qword_reg ())
29b0f896
AM		 4620 return 0;
4621 }
4622 else if (i.suffix == WORD_MNEM_SUFFIX)
4623 {
2eb952a4
L		 4624 if (intel_syntax
4625 && i.tm.opcode_modifier.ignoresize
4626 && i.tm.opcode_modifier.no_wsuf)
4627 i.suffix = 0;
4628 else if (!check_word_reg ())
29b0f896
AM		 4629 return 0;
4630 }
c0f3af97
L		 4631 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4632 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4633 {
c0f3af97 4634 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4635 should check if it is a valid suffix. */
4636 }
40fb9820 4637 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4638 /* Do nothing if the instruction is going to ignore the prefix. */
4639 ;
4640 else
4641 abort ();
4642 }
40fb9820 4643 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4644 && !i.suffix
4645 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4646 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4647 {
4648 i.suffix = stackop_size;
4649 }
9306ca4a
JB		 4650 else if (intel_syntax
4651 && !i.suffix
40fb9820
L		 4652 && (i.tm.operand_types[0].bitfield.jumpabsolute
4653 || i.tm.opcode_modifier.jumpbyte
4654 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4655 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4656 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4657 {
4658 switch (flag_code)
4659 {
4660 case CODE_64BIT:
40fb9820 4661 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4662 {
4663 i.suffix = QWORD_MNEM_SUFFIX;
4664 break;
4665 }
4666 case CODE_32BIT:
40fb9820 4667 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4668 i.suffix = LONG_MNEM_SUFFIX;
4669 break;
4670 case CODE_16BIT:
40fb9820 4671 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4672 i.suffix = WORD_MNEM_SUFFIX;
4673 break;
4674 }
4675 }
252b5132 4676
9306ca4a 4677 if (!i.suffix)
29b0f896 4678 {
9306ca4a
JB		 4679 if (!intel_syntax)
4680 {
40fb9820 4681 if (i.tm.opcode_modifier.w)
9306ca4a 4682 {
4eed87de
AM		 4683 as_bad (_("no instruction mnemonic suffix given and "
4684 "no register operands; can't size instruction"));
9306ca4a
JB		 4685 return 0;
4686 }
4687 }
4688 else
4689 {
40fb9820 4690 unsigned int suffixes;
7ab9ffdd 4691
40fb9820
L		 4692 suffixes = !i.tm.opcode_modifier.no_bsuf;
4693 if (!i.tm.opcode_modifier.no_wsuf)
4694 suffixes |= 1 << 1;
4695 if (!i.tm.opcode_modifier.no_lsuf)
4696 suffixes |= 1 << 2;
fc4adea1 4697 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4698 suffixes |= 1 << 3;
4699 if (!i.tm.opcode_modifier.no_ssuf)
4700 suffixes |= 1 << 4;
4701 if (!i.tm.opcode_modifier.no_qsuf)
4702 suffixes |= 1 << 5;
4703
4704 /* There are more than suffix matches. */
4705 if (i.tm.opcode_modifier.w
9306ca4a 4706 || ((suffixes & (suffixes - 1))
40fb9820
L		 4707 && !i.tm.opcode_modifier.defaultsize
4708 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4709 {
4710 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4711 return 0;
4712 }
4713 }
29b0f896 4714 }
252b5132 4715
9306ca4a
JB		 4716 /* Change the opcode based on the operand size given by i.suffix;
4717 We don't need to change things for byte insns. */
4718
582d5edd
L		 4719 if (i.suffix
4720 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4721 && i.suffix != XMMWORD_MNEM_SUFFIX
4722 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4723 {
4724 /* It's not a byte, select word/dword operation. */
40fb9820 4725 if (i.tm.opcode_modifier.w)
29b0f896 4726 {
40fb9820 4727 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4728 i.tm.base_opcode |= 8;
4729 else
4730 i.tm.base_opcode |= 1;
4731 }
0f3f3d8b 4732
29b0f896
AM		 4733 /* Now select between word & dword operations via the operand
4734 size prefix, except for instructions that will ignore this
4735 prefix anyway. */
ca61edf2 4736 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4737 {
ca61edf2
L		 4738 /* The address size override prefix changes the size of the
4739 first operand. */
40fb9820
L		 4740 if ((flag_code == CODE_32BIT
4741 && i.op->regs[0].reg_type.bitfield.reg16)
4742 || (flag_code != CODE_32BIT
4743 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4744 if (!add_prefix (ADDR_PREFIX_OPCODE))
4745 return 0;
4746 }
4747 else if (i.suffix != QWORD_MNEM_SUFFIX
4748 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4749 && !i.tm.opcode_modifier.ignoresize
4750 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4751 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4752 || (flag_code == CODE_64BIT
40fb9820 4753 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4754 {
4755 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4756
40fb9820 4757 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4758 prefix = ADDR_PREFIX_OPCODE;
252b5132 4759
29b0f896
AM		 4760 if (!add_prefix (prefix))
4761 return 0;
24eab124 4762 }
252b5132 4763
29b0f896
AM		 4764 /* Set mode64 for an operand. */
4765 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4766 && flag_code == CODE_64BIT
40fb9820 4767 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4768 {
4769 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4770 need rex64. cmpxchg8b is also a special case. */
4771 if (! (i.operands == 2
4772 && i.tm.base_opcode == 0x90
4773 && i.tm.extension_opcode == None
0dfbf9d7
L		 4774 && operand_type_equal (&i.types [0], &acc64)
4775 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4776 && ! (i.operands == 1
4777 && i.tm.base_opcode == 0xfc7
4778 && i.tm.extension_opcode == 1
40fb9820
L		 4779 && !operand_type_check (i.types [0], reg)
4780 && operand_type_check (i.types [0], anymem)))
f6bee062 4781 i.rex |= REX_W;
46e883c5 4782 }
3e73aa7c 4783
29b0f896
AM		 4784 /* Size floating point instruction. */
4785 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4786 if (i.tm.opcode_modifier.floatmf)
543613e9 4787 i.tm.base_opcode ^= 4;
29b0f896 4788 }
7ecd2f8b 4789
29b0f896
AM		 4790 return 1;
4791}
3e73aa7c 4792
29b0f896 4793static int
543613e9 4794check_byte_reg (void)
29b0f896
AM		 4795{
4796 int op;
543613e9 4797
29b0f896
AM		 4798 for (op = i.operands; --op >= 0;)
4799 {
4800 /* If this is an eight bit register, it's OK. If it's the 16 or
4801 32 bit version of an eight bit register, we will just use the
4802 low portion, and that's OK too. */
40fb9820 4803 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4804 continue;
4805
5a819eb9
JB		 4806 /* I/O port address operands are OK too. */
4807 if (i.tm.operand_types[op].bitfield.inoutportreg)
4808 continue;
4809
9344ff29
L		 4810 /* crc32 doesn't generate this warning. */
4811 if (i.tm.base_opcode == 0xf20f38f0)
4812 continue;
4813
40fb9820
L		 4814 if ((i.types[op].bitfield.reg16
4815 || i.types[op].bitfield.reg32
4816 || i.types[op].bitfield.reg64)
5a819eb9
JB		 4817 && i.op[op].regs->reg_num < 4
4818 /* Prohibit these changes in 64bit mode, since the lowering
4819 would be more complicated. */
4820 && flag_code != CODE_64BIT)
29b0f896 4821 {
29b0f896 4822#if REGISTER_WARNINGS
5a819eb9 4823 if (!quiet_warnings)
a540244d
L		 4824 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4825 register_prefix,
40fb9820 4826 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4827 ? REGNAM_AL - REGNAM_AX
4828 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4829 register_prefix,
29b0f896
AM		 4830 i.op[op].regs->reg_name,
4831 i.suffix);
4832#endif
4833 continue;
4834 }
4835 /* Any other register is bad. */
40fb9820
L		 4836 if (i.types[op].bitfield.reg16
4837 || i.types[op].bitfield.reg32
4838 || i.types[op].bitfield.reg64
4839 || i.types[op].bitfield.regmmx
4840 || i.types[op].bitfield.regxmm
c0f3af97 4841 || i.types[op].bitfield.regymm
40fb9820
L		 4842 || i.types[op].bitfield.sreg2
4843 || i.types[op].bitfield.sreg3
4844 || i.types[op].bitfield.control
4845 || i.types[op].bitfield.debug
4846 || i.types[op].bitfield.test
4847 || i.types[op].bitfield.floatreg
4848 || i.types[op].bitfield.floatacc)
29b0f896 4849 {
a540244d
L		 4850 as_bad (_("`%s%s' not allowed with `%s%c'"),
4851 register_prefix,
29b0f896
AM		 4852 i.op[op].regs->reg_name,
4853 i.tm.name,
4854 i.suffix);
4855 return 0;
4856 }
4857 }
4858 return 1;
4859}
4860
4861static int
e3bb37b5 4862check_long_reg (void)
29b0f896
AM		 4863{
4864 int op;
4865
4866 for (op = i.operands; --op >= 0;)
4867 /* Reject eight bit registers, except where the template requires
4868 them. (eg. movzb) */
40fb9820
L		 4869 if (i.types[op].bitfield.reg8
4870 && (i.tm.operand_types[op].bitfield.reg16
4871 || i.tm.operand_types[op].bitfield.reg32
4872 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4873 {
a540244d
L		 4874 as_bad (_("`%s%s' not allowed with `%s%c'"),
4875 register_prefix,
29b0f896
AM		 4876 i.op[op].regs->reg_name,
4877 i.tm.name,
4878 i.suffix);
4879 return 0;
4880 }
4881 /* Warn if the e prefix on a general reg is missing. */
4882 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4883 && i.types[op].bitfield.reg16
4884 && (i.tm.operand_types[op].bitfield.reg32
4885 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4886 {
4887 /* Prohibit these changes in the 64bit mode, since the
4888 lowering is more complicated. */
4889 if (flag_code == CODE_64BIT)
252b5132 4890 {
2b5d6a91 4891 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4892 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4893 i.suffix);
4894 return 0;
252b5132 4895 }
29b0f896
AM		 4896#if REGISTER_WARNINGS
4897 else
a540244d
L		 4898 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4899 register_prefix,
29b0f896 4900 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4901 register_prefix,
29b0f896
AM		 4902 i.op[op].regs->reg_name,
4903 i.suffix);
4904#endif
252b5132 4905 }
29b0f896 4906 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4907 else if (i.types[op].bitfield.reg64
4908 && (i.tm.operand_types[op].bitfield.reg32
4909 || i.tm.operand_types[op].bitfield.acc))
252b5132 4910 {
34828aad 4911 if (intel_syntax
ca61edf2 4912 && i.tm.opcode_modifier.toqword
40fb9820 4913 && !i.types[0].bitfield.regxmm)
34828aad 4914 {
ca61edf2 4915 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4916 i.suffix = QWORD_MNEM_SUFFIX;
4917 }
4918 else
4919 {
2b5d6a91 4920 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4921 register_prefix, i.op[op].regs->reg_name,
4922 i.suffix);
4923 return 0;
4924 }
29b0f896
AM		 4925 }
4926 return 1;
4927}
252b5132 4928
29b0f896 4929static int
e3bb37b5 4930check_qword_reg (void)
29b0f896
AM		 4931{
4932 int op;
252b5132 4933
29b0f896
AM		 4934 for (op = i.operands; --op >= 0; )
4935 /* Reject eight bit registers, except where the template requires
4936 them. (eg. movzb) */
40fb9820
L		 4937 if (i.types[op].bitfield.reg8
4938 && (i.tm.operand_types[op].bitfield.reg16
4939 || i.tm.operand_types[op].bitfield.reg32
4940 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4941 {
a540244d
L		 4942 as_bad (_("`%s%s' not allowed with `%s%c'"),
4943 register_prefix,
29b0f896
AM		 4944 i.op[op].regs->reg_name,
4945 i.tm.name,
4946 i.suffix);
4947 return 0;
4948 }
4949 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4950 else if ((i.types[op].bitfield.reg16
4951 || i.types[op].bitfield.reg32)
4952 && (i.tm.operand_types[op].bitfield.reg32
4953 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4954 {
4955 /* Prohibit these changes in the 64bit mode, since the
4956 lowering is more complicated. */
34828aad 4957 if (intel_syntax
ca61edf2 4958 && i.tm.opcode_modifier.todword
40fb9820 4959 && !i.types[0].bitfield.regxmm)
34828aad 4960 {
ca61edf2 4961 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4962 i.suffix = LONG_MNEM_SUFFIX;
4963 }
4964 else
4965 {
2b5d6a91 4966 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4967 register_prefix, i.op[op].regs->reg_name,
4968 i.suffix);
4969 return 0;
4970 }
252b5132 4971 }
29b0f896
AM		 4972 return 1;
4973}
252b5132 4974
29b0f896 4975static int
e3bb37b5 4976check_word_reg (void)
29b0f896
AM		 4977{
4978 int op;
4979 for (op = i.operands; --op >= 0;)
4980 /* Reject eight bit registers, except where the template requires
4981 them. (eg. movzb) */
40fb9820
L		 4982 if (i.types[op].bitfield.reg8
4983 && (i.tm.operand_types[op].bitfield.reg16
4984 || i.tm.operand_types[op].bitfield.reg32
4985 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4986 {
a540244d
L		 4987 as_bad (_("`%s%s' not allowed with `%s%c'"),
4988 register_prefix,
29b0f896
AM		 4989 i.op[op].regs->reg_name,
4990 i.tm.name,
4991 i.suffix);
4992 return 0;
4993 }
4994 /* Warn if the e prefix on a general reg is present. */
4995 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4996 && i.types[op].bitfield.reg32
4997 && (i.tm.operand_types[op].bitfield.reg16
4998 || i.tm.operand_types[op].bitfield.acc))
252b5132 4999 {
29b0f896
AM		 5000 /* Prohibit these changes in the 64bit mode, since the
5001 lowering is more complicated. */
5002 if (flag_code == CODE_64BIT)
252b5132 5003 {
2b5d6a91 5004 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5005 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5006 i.suffix);
5007 return 0;
252b5132 5008 }
29b0f896
AM		 5009 else
5010#if REGISTER_WARNINGS
a540244d
L		 5011 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5012 register_prefix,
29b0f896 5013 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 5014 register_prefix,
29b0f896
AM		 5015 i.op[op].regs->reg_name,
5016 i.suffix);
5017#endif
5018 }
5019 return 1;
5020}
252b5132 5021
29b0f896 5022static int
40fb9820 5023update_imm (unsigned int j)
29b0f896 5024{
bc0844ae 5025 i386_operand_type overlap = i.types[j];
40fb9820
L		 5026 if ((overlap.bitfield.imm8
5027 || overlap.bitfield.imm8s
5028 || overlap.bitfield.imm16
5029 || overlap.bitfield.imm32
5030 || overlap.bitfield.imm32s
5031 || overlap.bitfield.imm64)
0dfbf9d7
L		 5032 && !operand_type_equal (&overlap, &imm8)
5033 && !operand_type_equal (&overlap, &imm8s)
5034 && !operand_type_equal (&overlap, &imm16)
5035 && !operand_type_equal (&overlap, &imm32)
5036 && !operand_type_equal (&overlap, &imm32s)
5037 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5038 {
5039 if (i.suffix)
5040 {
40fb9820
L		 5041 i386_operand_type temp;
5042
0dfbf9d7 5043 operand_type_set (&temp, 0);
7ab9ffdd 5044 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5045 {
5046 temp.bitfield.imm8 = overlap.bitfield.imm8;
5047 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5048 }
5049 else if (i.suffix == WORD_MNEM_SUFFIX)
5050 temp.bitfield.imm16 = overlap.bitfield.imm16;
5051 else if (i.suffix == QWORD_MNEM_SUFFIX)
5052 {
5053 temp.bitfield.imm64 = overlap.bitfield.imm64;
5054 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5055 }
5056 else
5057 temp.bitfield.imm32 = overlap.bitfield.imm32;
5058 overlap = temp;
29b0f896 5059 }
0dfbf9d7
L		 5060 else if (operand_type_equal (&overlap, &imm16_32_32s)
5061 || operand_type_equal (&overlap, &imm16_32)
5062 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5063 {
40fb9820 5064 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5065 overlap = imm16;
40fb9820 5066 else
65da13b5 5067 overlap = imm32s;
29b0f896 5068 }
0dfbf9d7
L		 5069 if (!operand_type_equal (&overlap, &imm8)
5070 && !operand_type_equal (&overlap, &imm8s)
5071 && !operand_type_equal (&overlap, &imm16)
5072 && !operand_type_equal (&overlap, &imm32)
5073 && !operand_type_equal (&overlap, &imm32s)
5074 && !operand_type_equal (&overlap, &imm64))
29b0f896 5075 {
4eed87de
AM		 5076 as_bad (_("no instruction mnemonic suffix given; "
5077 "can't determine immediate size"));
29b0f896
AM		 5078 return 0;
5079 }
5080 }
40fb9820 5081 i.types[j] = overlap;
29b0f896 5082
40fb9820
L		 5083 return 1;
5084}
5085
5086static int
5087finalize_imm (void)
5088{
bc0844ae 5089 unsigned int j, n;
29b0f896 5090
bc0844ae
L		 5091 /* Update the first 2 immediate operands. */
5092 n = i.operands > 2 ? 2 : i.operands;
5093 if (n)
5094 {
5095 for (j = 0; j < n; j++)
5096 if (update_imm (j) == 0)
5097 return 0;
40fb9820 5098
bc0844ae
L		 5099 /* The 3rd operand can't be immediate operand. */
5100 gas_assert (operand_type_check (i.types[2], imm) == 0);
5101 }
29b0f896
AM		 5102
5103 return 1;
5104}
5105
c0f3af97
L		 5106static int
5107bad_implicit_operand (int xmm)
5108{
91d6fa6a
NC		 5109 const char *ireg = xmm ? "xmm0" : "ymm0";
5110
c0f3af97
L		 5111 if (intel_syntax)
5112 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5113 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5114 else
5115 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5116 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5117 return 0;
5118}
5119
29b0f896 5120static int
e3bb37b5 5121process_operands (void)
29b0f896
AM		 5122{
5123 /* Default segment register this instruction will use for memory
5124 accesses. 0 means unknown. This is only for optimizing out
5125 unnecessary segment overrides. */
5126 const seg_entry *default_seg = 0;
5127
2426c15f 5128 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5129 {
91d6fa6a
NC		 5130 unsigned int dupl = i.operands;
5131 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5132 unsigned int j;
5133
c0f3af97 5134 /* The destination must be an xmm register. */
9c2799c2 5135 gas_assert (i.reg_operands
91d6fa6a 5136 && MAX_OPERANDS > dupl
7ab9ffdd 5137 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5138
5139 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5140 {
c0f3af97 5141 /* The first operand is implicit and must be xmm0. */
9c2799c2 5142 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5143 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5144 return bad_implicit_operand (1);
5145
8cd7925b 5146 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5147 {
5148 /* Keep xmm0 for instructions with VEX prefix and 3
5149 sources. */
5150 goto duplicate;
5151 }
e2ec9d29 5152 else
c0f3af97
L		 5153 {
5154 /* We remove the first xmm0 and keep the number of
5155 operands unchanged, which in fact duplicates the
5156 destination. */
5157 for (j = 1; j < i.operands; j++)
5158 {
5159 i.op[j - 1] = i.op[j];
5160 i.types[j - 1] = i.types[j];
5161 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5162 }
5163 }
5164 }
5165 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5166 {
91d6fa6a 5167 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5168 && (i.tm.opcode_modifier.vexsources
5169 == VEX3SOURCES));
c0f3af97
L		 5170
5171 /* Add the implicit xmm0 for instructions with VEX prefix
5172 and 3 sources. */
5173 for (j = i.operands; j > 0; j--)
5174 {
5175 i.op[j] = i.op[j - 1];
5176 i.types[j] = i.types[j - 1];
5177 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5178 }
5179 i.op[0].regs
5180 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5181 i.types[0] = regxmm;
c0f3af97
L		 5182 i.tm.operand_types[0] = regxmm;
5183
5184 i.operands += 2;
5185 i.reg_operands += 2;
5186 i.tm.operands += 2;
5187
91d6fa6a 5188 dupl++;
c0f3af97 5189 dest++;
91d6fa6a
NC		 5190 i.op[dupl] = i.op[dest];
5191 i.types[dupl] = i.types[dest];
5192 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5193 }
c0f3af97
L		 5194 else
5195 {
5196duplicate:
5197 i.operands++;
5198 i.reg_operands++;
5199 i.tm.operands++;
5200
91d6fa6a
NC		 5201 i.op[dupl] = i.op[dest];
5202 i.types[dupl] = i.types[dest];
5203 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5204 }
5205
5206 if (i.tm.opcode_modifier.immext)
5207 process_immext ();
5208 }
5209 else if (i.tm.opcode_modifier.firstxmm0)
5210 {
5211 unsigned int j;
5212
5213 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 5214 gas_assert (i.reg_operands
7ab9ffdd
L		 5215 && (operand_type_equal (&i.types[0], &regxmm)
5216 || operand_type_equal (&i.types[0], &regymm)));
4c692bc7 5217 if (register_number (i.op[0].regs) != 0)
c0f3af97 5218 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5219
5220 for (j = 1; j < i.operands; j++)
5221 {
5222 i.op[j - 1] = i.op[j];
5223 i.types[j - 1] = i.types[j];
5224
5225 /* We need to adjust fields in i.tm since they are used by
5226 build_modrm_byte. */
5227 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5228 }
5229
e2ec9d29
L		 5230 i.operands--;
5231 i.reg_operands--;
e2ec9d29
L		 5232 i.tm.operands--;
5233 }
5234 else if (i.tm.opcode_modifier.regkludge)
5235 {
5236 /* The imul $imm, %reg instruction is converted into
5237 imul $imm, %reg, %reg, and the clr %reg instruction
5238 is converted into xor %reg, %reg. */
5239
5240 unsigned int first_reg_op;
5241
5242 if (operand_type_check (i.types[0], reg))
5243 first_reg_op = 0;
5244 else
5245 first_reg_op = 1;
5246 /* Pretend we saw the extra register operand. */
9c2799c2 5247 gas_assert (i.reg_operands == 1
7ab9ffdd 5248 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5249 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5250 i.types[first_reg_op + 1] = i.types[first_reg_op];
5251 i.operands++;
5252 i.reg_operands++;
29b0f896
AM		 5253 }
5254
40fb9820 5255 if (i.tm.opcode_modifier.shortform)
29b0f896 5256 {
40fb9820
L		 5257 if (i.types[0].bitfield.sreg2
5258 || i.types[0].bitfield.sreg3)
29b0f896 5259 {
4eed87de
AM		 5260 if (i.tm.base_opcode == POP_SEG_SHORT
5261 && i.op[0].regs->reg_num == 1)
29b0f896 5262 {
a87af027 5263 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5264 return 0;
29b0f896 5265 }
4eed87de
AM		 5266 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5267 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5268 i.rex |= REX_B;
4eed87de
AM		 5269 }
5270 else
5271 {
7ab9ffdd 5272 /* The register or float register operand is in operand
85f10a01 5273 0 or 1. */
40fb9820 5274 unsigned int op;
7ab9ffdd
L		 5275
5276 if (i.types[0].bitfield.floatreg
5277 || operand_type_check (i.types[0], reg))
5278 op = 0;
5279 else
5280 op = 1;
4eed87de
AM		 5281 /* Register goes in low 3 bits of opcode. */
5282 i.tm.base_opcode |= i.op[op].regs->reg_num;
5283 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5284 i.rex |= REX_B;
40fb9820 5285 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5286 {
4eed87de
AM		 5287 /* Warn about some common errors, but press on regardless.
5288 The first case can be generated by gcc (<= 2.8.1). */
5289 if (i.operands == 2)
5290 {
5291 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5292 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5293 register_prefix, i.op[!intel_syntax].regs->reg_name,
5294 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5295 }
5296 else
5297 {
5298 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5299 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5300 register_prefix, i.op[0].regs->reg_name);
4eed87de 5301 }
29b0f896
AM		 5302 }
5303 }
5304 }
40fb9820 5305 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5306 {
5307 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5308 must be put into the modrm byte). Now, we make the modrm and
5309 index base bytes based on all the info we've collected. */
29b0f896
AM		 5310
5311 default_seg = build_modrm_byte ();
5312 }
8a2ed489 5313 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5314 {
5315 default_seg = &ds;
5316 }
40fb9820 5317 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5318 {
5319 /* For the string instructions that allow a segment override
5320 on one of their operands, the default segment is ds. */
5321 default_seg = &ds;
5322 }
5323
75178d9d
L		 5324 if (i.tm.base_opcode == 0x8d /* lea */
5325 && i.seg[0]
5326 && !quiet_warnings)
30123838 5327 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5328
5329 /* If a segment was explicitly specified, and the specified segment
5330 is not the default, use an opcode prefix to select it. If we
5331 never figured out what the default segment is, then default_seg
5332 will be zero at this point, and the specified segment prefix will
5333 always be used. */
29b0f896
AM		 5334 if ((i.seg[0]) && (i.seg[0] != default_seg))
5335 {
5336 if (!add_prefix (i.seg[0]->seg_prefix))
5337 return 0;
5338 }
5339 return 1;
5340}
5341
5342static const seg_entry *
e3bb37b5 5343build_modrm_byte (void)
29b0f896
AM		 5344{
5345 const seg_entry *default_seg = 0;
c0f3af97 5346 unsigned int source, dest;
8cd7925b 5347 int vex_3_sources;
c0f3af97
L		 5348
5349 /* The first operand of instructions with VEX prefix and 3 sources
5350 must be VEX_Imm4. */
8cd7925b 5351 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5352 if (vex_3_sources)
5353 {
91d6fa6a 5354 unsigned int nds, reg_slot;
4c2c6516 5355 expressionS *exp;
c0f3af97 5356
922d8de8 5357 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5358 && i.tm.opcode_modifier.immext)
5359 {
5360 dest = i.operands - 2;
5361 gas_assert (dest == 3);
5362 }
922d8de8 5363 else
a683cc34 5364 dest = i.operands - 1;
c0f3af97 5365 nds = dest - 1;
922d8de8 5366
a683cc34
SP		 5367 /* There are 2 kinds of instructions:
5368 1. 5 operands: 4 register operands or 3 register operands
5369 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5370 VexW0 or VexW1. The destination must be either XMM or YMM
5371 register.
5372 2. 4 operands: 4 register operands or 3 register operands
5373 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5374 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5375 || (i.reg_operands == 3 && i.mem_operands == 1))
5376 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5377 && (i.tm.opcode_modifier.veximmext
5378 || (i.imm_operands == 1
5379 && i.types[0].bitfield.vec_imm4
5380 && (i.tm.opcode_modifier.vexw == VEXW0
5381 || i.tm.opcode_modifier.vexw == VEXW1)
5382 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5383 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5384
5385 if (i.imm_operands == 0)
5386 {
5387 /* When there is no immediate operand, generate an 8bit
5388 immediate operand to encode the first operand. */
5389 exp = &im_expressions[i.imm_operands++];
5390 i.op[i.operands].imms = exp;
5391 i.types[i.operands] = imm8;
5392 i.operands++;
5393 /* If VexW1 is set, the first operand is the source and
5394 the second operand is encoded in the immediate operand. */
5395 if (i.tm.opcode_modifier.vexw == VEXW1)
5396 {
5397 source = 0;
5398 reg_slot = 1;
5399 }
5400 else
5401 {
5402 source = 1;
5403 reg_slot = 0;
5404 }
5405
5406 /* FMA swaps REG and NDS. */
5407 if (i.tm.cpu_flags.bitfield.cpufma)
5408 {
5409 unsigned int tmp;
5410 tmp = reg_slot;
5411 reg_slot = nds;
5412 nds = tmp;
5413 }
5414
24981e7b
L		 5415 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5416 &regxmm)
a683cc34
SP		 5417 || operand_type_equal (&i.tm.operand_types[reg_slot],
5418 &regymm));
5419 exp->X_op = O_constant;
4c692bc7 5420 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
a683cc34 5421 }
922d8de8 5422 else
a683cc34
SP		 5423 {
5424 unsigned int imm_slot;
5425
5426 if (i.tm.opcode_modifier.vexw == VEXW0)
5427 {
5428 /* If VexW0 is set, the third operand is the source and
5429 the second operand is encoded in the immediate
5430 operand. */
5431 source = 2;
5432 reg_slot = 1;
5433 }
5434 else
5435 {
5436 /* VexW1 is set, the second operand is the source and
5437 the third operand is encoded in the immediate
5438 operand. */
5439 source = 1;
5440 reg_slot = 2;
5441 }
5442
5443 if (i.tm.opcode_modifier.immext)
5444 {
5445 /* When ImmExt is set, the immdiate byte is the last
5446 operand. */
5447 imm_slot = i.operands - 1;
5448 source--;
5449 reg_slot--;
5450 }
5451 else
5452 {
5453 imm_slot = 0;
5454
5455 /* Turn on Imm8 so that output_imm will generate it. */
5456 i.types[imm_slot].bitfield.imm8 = 1;
5457 }
5458
24981e7b
L		 5459 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5460 &regxmm)
5461 || operand_type_equal (&i.tm.operand_types[reg_slot],
5462 &regymm));
a683cc34 5463 i.op[imm_slot].imms->X_add_number
4c692bc7 5464 |= register_number (i.op[reg_slot].regs) << 4;
a683cc34
SP		 5465 }
5466
5467 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5468 || operand_type_equal (&i.tm.operand_types[nds],
5469 &regymm));
dae39acc 5470 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5471 }
5472 else
5473 source = dest = 0;
29b0f896
AM		 5474
5475 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5476 implicit registers do not count. If there are 3 register
5477 operands, it must be a instruction with VexNDS. For a
5478 instruction with VexNDD, the destination register is encoded
5479 in VEX prefix. If there are 4 register operands, it must be
5480 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5481 if (i.mem_operands == 0
5482 && ((i.reg_operands == 2
2426c15f 5483 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5484 || (i.reg_operands == 3
2426c15f 5485 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5486 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5487 {
cab737b9
L		 5488 switch (i.operands)
5489 {
5490 case 2:
5491 source = 0;
5492 break;
5493 case 3:
c81128dc
L		 5494 /* When there are 3 operands, one of them may be immediate,
5495 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5496 the first operand must be shift count register (cl) or it
5497 is an instruction with VexNDS. */
9c2799c2 5498 gas_assert (i.imm_operands == 1
7ab9ffdd 5499 || (i.imm_operands == 0
2426c15f 5500 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5501 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5502 if (operand_type_check (i.types[0], imm)
5503 || i.types[0].bitfield.shiftcount)
5504 source = 1;
5505 else
5506 source = 0;
cab737b9
L		 5507 break;
5508 case 4:
368d64cc
L		 5509 /* When there are 4 operands, the first two must be 8bit
5510 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5511 one.
5512
5513 For instructions with VexNDS, if the first operand
5514 an imm8, the source operand is the 2nd one. If the last
5515 operand is imm8, the source operand is the first one. */
9c2799c2 5516 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5517 && i.types[0].bitfield.imm8
5518 && i.types[1].bitfield.imm8)
2426c15f 5519 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5520 && i.imm_operands == 1
5521 && (i.types[0].bitfield.imm8
5522 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5523 if (i.imm_operands == 2)
5524 source = 2;
5525 else
c0f3af97
L		 5526 {
5527 if (i.types[0].bitfield.imm8)
5528 source = 1;
5529 else
5530 source = 0;
5531 }
c0f3af97
L		 5532 break;
5533 case 5:
cab737b9
L		 5534 break;
5535 default:
5536 abort ();
5537 }
5538
c0f3af97
L		 5539 if (!vex_3_sources)
5540 {
5541 dest = source + 1;
5542
2426c15f 5543 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5544 {
5545 /* For instructions with VexNDS, the register-only
f12dc422
L		 5546 source operand must be 32/64bit integer, XMM or
5547 YMM register. It is encoded in VEX prefix. We
5548 need to clear RegMem bit before calling
5549 operand_type_equal. */
5550
5551 i386_operand_type op;
5552 unsigned int vvvv;
5553
5554 /* Check register-only source operand when two source
5555 operands are swapped. */
5556 if (!i.tm.operand_types[source].bitfield.baseindex
5557 && i.tm.operand_types[dest].bitfield.baseindex)
5558 {
5559 vvvv = source;
5560 source = dest;
5561 }
5562 else
5563 vvvv = dest;
5564
5565 op = i.tm.operand_types[vvvv];
fa99fab2 5566 op.bitfield.regmem = 0;
c0f3af97 5567 if ((dest + 1) >= i.operands
f12dc422
L		 5568 || (op.bitfield.reg32 != 1
5569 && !op.bitfield.reg64 != 1
5570 && !operand_type_equal (&op, &regxmm)
fa99fab2 5571 && !operand_type_equal (&op, &regymm)))
c0f3af97 5572 abort ();
f12dc422 5573 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5574 dest++;
5575 }
5576 }
29b0f896
AM		 5577
5578 i.rm.mode = 3;
5579 /* One of the register operands will be encoded in the i.tm.reg
5580 field, the other in the combined i.tm.mode and i.tm.regmem
5581 fields. If no form of this instruction supports a memory
5582 destination operand, then we assume the source operand may
5583 sometimes be a memory operand and so we need to store the
5584 destination in the i.rm.reg field. */
40fb9820
L		 5585 if (!i.tm.operand_types[dest].bitfield.regmem
5586 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5587 {
5588 i.rm.reg = i.op[dest].regs->reg_num;
5589 i.rm.regmem = i.op[source].regs->reg_num;
5590 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5591 i.rex |= REX_R;
29b0f896 5592 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5593 i.rex |= REX_B;
29b0f896
AM		 5594 }
5595 else
5596 {
5597 i.rm.reg = i.op[source].regs->reg_num;
5598 i.rm.regmem = i.op[dest].regs->reg_num;
5599 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5600 i.rex |= REX_B;
29b0f896 5601 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5602 i.rex |= REX_R;
29b0f896 5603 }
161a04f6 5604 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5605 {
40fb9820
L		 5606 if (!i.types[0].bitfield.control
5607 && !i.types[1].bitfield.control)
c4a530c5 5608 abort ();
161a04f6 5609 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5610 add_prefix (LOCK_PREFIX_OPCODE);
5611 }
29b0f896
AM		 5612 }
5613 else
5614 { /* If it's not 2 reg operands... */
c0f3af97
L		 5615 unsigned int mem;
5616
29b0f896
AM		 5617 if (i.mem_operands)
5618 {
5619 unsigned int fake_zero_displacement = 0;
99018f42 5620 unsigned int op;
4eed87de 5621
7ab9ffdd
L		 5622 for (op = 0; op < i.operands; op++)
5623 if (operand_type_check (i.types[op], anymem))
5624 break;
7ab9ffdd 5625 gas_assert (op < i.operands);
29b0f896 5626
6c30d220
L		 5627 if (i.tm.opcode_modifier.vecsib)
5628 {
5629 if (i.index_reg->reg_num == RegEiz
5630 || i.index_reg->reg_num == RegRiz)
5631 abort ();
5632
5633 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5634 if (!i.base_reg)
5635 {
5636 i.sib.base = NO_BASE_REGISTER;
5637 i.sib.scale = i.log2_scale_factor;
5638 i.types[op].bitfield.disp8 = 0;
5639 i.types[op].bitfield.disp16 = 0;
5640 i.types[op].bitfield.disp64 = 0;
5641 if (flag_code != CODE_64BIT)
5642 {
5643 /* Must be 32 bit */
5644 i.types[op].bitfield.disp32 = 1;
5645 i.types[op].bitfield.disp32s = 0;
5646 }
5647 else
5648 {
5649 i.types[op].bitfield.disp32 = 0;
5650 i.types[op].bitfield.disp32s = 1;
5651 }
5652 }
5653 i.sib.index = i.index_reg->reg_num;
5654 if ((i.index_reg->reg_flags & RegRex) != 0)
5655 i.rex |= REX_X;
5656 }
5657
29b0f896
AM		 5658 default_seg = &ds;
5659
5660 if (i.base_reg == 0)
5661 {
5662 i.rm.mode = 0;
5663 if (!i.disp_operands)
6c30d220
L		 5664 {
5665 fake_zero_displacement = 1;
5666 /* Instructions with VSIB byte need 32bit displacement
5667 if there is no base register. */
5668 if (i.tm.opcode_modifier.vecsib)
5669 i.types[op].bitfield.disp32 = 1;
5670 }
29b0f896
AM		 5671 if (i.index_reg == 0)
5672 {
6c30d220 5673 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5674 /* Operand is just <disp> */
20f0a1fc 5675 if (flag_code == CODE_64BIT)
29b0f896
AM		 5676 {
5677 /* 64bit mode overwrites the 32bit absolute
5678 addressing by RIP relative addressing and
5679 absolute addressing is encoded by one of the
5680 redundant SIB forms. */
5681 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5682 i.sib.base = NO_BASE_REGISTER;
5683 i.sib.index = NO_INDEX_REGISTER;
fc225355 5684 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5685 ? disp32s : disp32);
20f0a1fc 5686 }
fc225355
L		 5687 else if ((flag_code == CODE_16BIT)
5688 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5689 {
5690 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5691 i.types[op] = disp16;
20f0a1fc
NC		 5692 }
5693 else
5694 {
5695 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5696 i.types[op] = disp32;
29b0f896
AM		 5697 }
5698 }
6c30d220 5699 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5700 {
6c30d220 5701 /* !i.base_reg && i.index_reg */
db51cc60
L		 5702 if (i.index_reg->reg_num == RegEiz
5703 || i.index_reg->reg_num == RegRiz)
5704 i.sib.index = NO_INDEX_REGISTER;
5705 else
5706 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5707 i.sib.base = NO_BASE_REGISTER;
5708 i.sib.scale = i.log2_scale_factor;
5709 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5710 i.types[op].bitfield.disp8 = 0;
5711 i.types[op].bitfield.disp16 = 0;
5712 i.types[op].bitfield.disp64 = 0;
29b0f896 5713 if (flag_code != CODE_64BIT)
40fb9820
L		 5714 {
5715 /* Must be 32 bit */
5716 i.types[op].bitfield.disp32 = 1;
5717 i.types[op].bitfield.disp32s = 0;
5718 }
29b0f896 5719 else
40fb9820
L		 5720 {
5721 i.types[op].bitfield.disp32 = 0;
5722 i.types[op].bitfield.disp32s = 1;
5723 }
29b0f896 5724 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5725 i.rex |= REX_X;
29b0f896
AM		 5726 }
5727 }
5728 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5729 else if (i.base_reg->reg_num == RegRip ||
5730 i.base_reg->reg_num == RegEip)
29b0f896 5731 {
6c30d220 5732 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5733 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5734 i.types[op].bitfield.disp8 = 0;
5735 i.types[op].bitfield.disp16 = 0;
5736 i.types[op].bitfield.disp32 = 0;
5737 i.types[op].bitfield.disp32s = 1;
5738 i.types[op].bitfield.disp64 = 0;
71903a11 5739 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5740 if (! i.disp_operands)
5741 fake_zero_displacement = 1;
29b0f896 5742 }
40fb9820 5743 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 5744 {
6c30d220 5745 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5746 switch (i.base_reg->reg_num)
5747 {
5748 case 3: /* (%bx) */
5749 if (i.index_reg == 0)
5750 i.rm.regmem = 7;
5751 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5752 i.rm.regmem = i.index_reg->reg_num - 6;
5753 break;
5754 case 5: /* (%bp) */
5755 default_seg = &ss;
5756 if (i.index_reg == 0)
5757 {
5758 i.rm.regmem = 6;
40fb9820 5759 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5760 {
5761 /* fake (%bp) into 0(%bp) */
40fb9820 5762 i.types[op].bitfield.disp8 = 1;
252b5132 5763 fake_zero_displacement = 1;
29b0f896
AM		 5764 }
5765 }
5766 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5767 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5768 break;
5769 default: /* (%si) -> 4 or (%di) -> 5 */
5770 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5771 }
5772 i.rm.mode = mode_from_disp_size (i.types[op]);
5773 }
5774 else /* i.base_reg and 32/64 bit mode */
5775 {
5776 if (flag_code == CODE_64BIT
40fb9820
L		 5777 && operand_type_check (i.types[op], disp))
5778 {
5779 i386_operand_type temp;
0dfbf9d7 5780 operand_type_set (&temp, 0);
40fb9820
L		 5781 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5782 i.types[op] = temp;
5783 if (i.prefix[ADDR_PREFIX] == 0)
5784 i.types[op].bitfield.disp32s = 1;
5785 else
5786 i.types[op].bitfield.disp32 = 1;
5787 }
20f0a1fc 5788
6c30d220
L		 5789 if (!i.tm.opcode_modifier.vecsib)
5790 i.rm.regmem = i.base_reg->reg_num;
29b0f896 5791 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5792 i.rex |= REX_B;
29b0f896
AM		 5793 i.sib.base = i.base_reg->reg_num;
5794 /* x86-64 ignores REX prefix bit here to avoid decoder
5795 complications. */
848930b2
JB		 5796 if (!(i.base_reg->reg_flags & RegRex)
5797 && (i.base_reg->reg_num == EBP_REG_NUM
5798 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 5799 default_seg = &ss;
848930b2 5800 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 5801 {
848930b2
JB		 5802 fake_zero_displacement = 1;
5803 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5804 }
5805 i.sib.scale = i.log2_scale_factor;
5806 if (i.index_reg == 0)
5807 {
6c30d220 5808 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5809 /* <disp>(%esp) becomes two byte modrm with no index
5810 register. We've already stored the code for esp
5811 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5812 Any base register besides %esp will not use the
5813 extra modrm byte. */
5814 i.sib.index = NO_INDEX_REGISTER;
29b0f896 5815 }
6c30d220 5816 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5817 {
db51cc60
L		 5818 if (i.index_reg->reg_num == RegEiz
5819 || i.index_reg->reg_num == RegRiz)
5820 i.sib.index = NO_INDEX_REGISTER;
5821 else
5822 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5823 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5824 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5825 i.rex |= REX_X;
29b0f896 5826 }
67a4f2b7
AO		 5827
5828 if (i.disp_operands
5829 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5830 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5831 i.rm.mode = 0;
5832 else
a501d77e
L		 5833 {
5834 if (!fake_zero_displacement
5835 && !i.disp_operands
5836 && i.disp_encoding)
5837 {
5838 fake_zero_displacement = 1;
5839 if (i.disp_encoding == disp_encoding_8bit)
5840 i.types[op].bitfield.disp8 = 1;
5841 else
5842 i.types[op].bitfield.disp32 = 1;
5843 }
5844 i.rm.mode = mode_from_disp_size (i.types[op]);
5845 }
29b0f896 5846 }
252b5132 5847
29b0f896
AM		 5848 if (fake_zero_displacement)
5849 {
5850 /* Fakes a zero displacement assuming that i.types[op]
5851 holds the correct displacement size. */
5852 expressionS *exp;
5853
9c2799c2 5854 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5855 exp = &disp_expressions[i.disp_operands++];
5856 i.op[op].disps = exp;
5857 exp->X_op = O_constant;
5858 exp->X_add_number = 0;
5859 exp->X_add_symbol = (symbolS *) 0;
5860 exp->X_op_symbol = (symbolS *) 0;
5861 }
c0f3af97
L		 5862
5863 mem = op;
29b0f896 5864 }
c0f3af97
L		 5865 else
5866 mem = ~0;
252b5132 5867
8c43a48b 5868 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5869 {
5870 if (operand_type_check (i.types[0], imm))
5871 i.vex.register_specifier = NULL;
5872 else
5873 {
5874 /* VEX.vvvv encodes one of the sources when the first
5875 operand is not an immediate. */
1ef99a7b 5876 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5877 i.vex.register_specifier = i.op[0].regs;
5878 else
5879 i.vex.register_specifier = i.op[1].regs;
5880 }
5881
5882 /* Destination is a XMM register encoded in the ModRM.reg
5883 and VEX.R bit. */
5884 i.rm.reg = i.op[2].regs->reg_num;
5885 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5886 i.rex |= REX_R;
5887
5888 /* ModRM.rm and VEX.B encodes the other source. */
5889 if (!i.mem_operands)
5890 {
5891 i.rm.mode = 3;
5892
1ef99a7b 5893 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5894 i.rm.regmem = i.op[1].regs->reg_num;
5895 else
5896 i.rm.regmem = i.op[0].regs->reg_num;
5897
5898 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5899 i.rex |= REX_B;
5900 }
5901 }
2426c15f 5902 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5903 {
5904 i.vex.register_specifier = i.op[2].regs;
5905 if (!i.mem_operands)
5906 {
5907 i.rm.mode = 3;
5908 i.rm.regmem = i.op[1].regs->reg_num;
5909 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5910 i.rex |= REX_B;
5911 }
5912 }
29b0f896
AM		 5913 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5914 (if any) based on i.tm.extension_opcode. Again, we must be
5915 careful to make sure that segment/control/debug/test/MMX
5916 registers are coded into the i.rm.reg field. */
f88c9eb0 5917 else if (i.reg_operands)
29b0f896 5918 {
99018f42 5919 unsigned int op;
7ab9ffdd
L		 5920 unsigned int vex_reg = ~0;
5921
5922 for (op = 0; op < i.operands; op++)
5923 if (i.types[op].bitfield.reg8
5924 || i.types[op].bitfield.reg16
5925 || i.types[op].bitfield.reg32
5926 || i.types[op].bitfield.reg64
5927 || i.types[op].bitfield.regmmx
5928 || i.types[op].bitfield.regxmm
5929 || i.types[op].bitfield.regymm
5930 || i.types[op].bitfield.sreg2
5931 || i.types[op].bitfield.sreg3
5932 || i.types[op].bitfield.control
5933 || i.types[op].bitfield.debug
5934 || i.types[op].bitfield.test)
5935 break;
c0209578 5936
7ab9ffdd
L		 5937 if (vex_3_sources)
5938 op = dest;
2426c15f 5939 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5940 {
5941 /* For instructions with VexNDS, the register-only
5942 source operand is encoded in VEX prefix. */
5943 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5944
7ab9ffdd 5945 if (op > mem)
c0f3af97 5946 {
7ab9ffdd
L		 5947 vex_reg = op++;
5948 gas_assert (op < i.operands);
c0f3af97
L		 5949 }
5950 else
c0f3af97 5951 {
f12dc422
L		 5952 /* Check register-only source operand when two source
5953 operands are swapped. */
5954 if (!i.tm.operand_types[op].bitfield.baseindex
5955 && i.tm.operand_types[op + 1].bitfield.baseindex)
5956 {
5957 vex_reg = op;
5958 op += 2;
5959 gas_assert (mem == (vex_reg + 1)
5960 && op < i.operands);
5961 }
5962 else
5963 {
5964 vex_reg = op + 1;
5965 gas_assert (vex_reg < i.operands);
5966 }
c0f3af97 5967 }
7ab9ffdd 5968 }
2426c15f 5969 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5970 {
f12dc422 5971 /* For instructions with VexNDD, the register destination
7ab9ffdd 5972 is encoded in VEX prefix. */
f12dc422
L		 5973 if (i.mem_operands == 0)
5974 {
5975 /* There is no memory operand. */
5976 gas_assert ((op + 2) == i.operands);
5977 vex_reg = op + 1;
5978 }
5979 else
8d63c93e 5980 {
f12dc422
L		 5981 /* There are only 2 operands. */
5982 gas_assert (op < 2 && i.operands == 2);
5983 vex_reg = 1;
5984 }
7ab9ffdd
L		 5985 }
5986 else
5987 gas_assert (op < i.operands);
99018f42 5988
7ab9ffdd
L		 5989 if (vex_reg != (unsigned int) ~0)
5990 {
f12dc422 5991 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5992
f12dc422
L		 5993 if (type->bitfield.reg32 != 1
5994 && type->bitfield.reg64 != 1
5995 && !operand_type_equal (type, &regxmm)
5996 && !operand_type_equal (type, &regymm))
7ab9ffdd 5997 abort ();
f88c9eb0 5998
7ab9ffdd
L		 5999 i.vex.register_specifier = i.op[vex_reg].regs;
6000 }
6001
1b9f0c97
L		 6002 /* Don't set OP operand twice. */
6003 if (vex_reg != op)
7ab9ffdd 6004 {
1b9f0c97
L		 6005 /* If there is an extension opcode to put here, the
6006 register number must be put into the regmem field. */
6007 if (i.tm.extension_opcode != None)
6008 {
6009 i.rm.regmem = i.op[op].regs->reg_num;
6010 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6011 i.rex |= REX_B;
6012 }
6013 else
6014 {
6015 i.rm.reg = i.op[op].regs->reg_num;
6016 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6017 i.rex |= REX_R;
6018 }
7ab9ffdd 6019 }
252b5132 6020
29b0f896
AM		 6021 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6022 must set it to 3 to indicate this is a register operand
6023 in the regmem field. */
6024 if (!i.mem_operands)
6025 i.rm.mode = 3;
6026 }
252b5132 6027
29b0f896 6028 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6029 if (i.tm.extension_opcode != None)
29b0f896
AM		 6030 i.rm.reg = i.tm.extension_opcode;
6031 }
6032 return default_seg;
6033}
252b5132 6034
29b0f896 6035static void
e3bb37b5 6036output_branch (void)
29b0f896
AM		 6037{
6038 char *p;
f8a5c266 6039 int size;
29b0f896
AM		 6040 int code16;
6041 int prefix;
6042 relax_substateT subtype;
6043 symbolS *sym;
6044 offsetT off;
6045
f8a5c266 6046 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6047 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6048
6049 prefix = 0;
6050 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6051 {
29b0f896
AM		 6052 prefix = 1;
6053 i.prefixes -= 1;
6054 code16 ^= CODE16;
252b5132 6055 }
29b0f896
AM		 6056 /* Pentium4 branch hints. */
6057 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6058 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6059 {
29b0f896
AM		 6060 prefix++;
6061 i.prefixes--;
6062 }
6063 if (i.prefix[REX_PREFIX] != 0)
6064 {
6065 prefix++;
6066 i.prefixes--;
2f66722d
AM		 6067 }
6068
29b0f896
AM		 6069 if (i.prefixes != 0 && !intel_syntax)
6070 as_warn (_("skipping prefixes on this instruction"));
6071
6072 /* It's always a symbol; End frag & setup for relax.
6073 Make sure there is enough room in this frag for the largest
6074 instruction we may generate in md_convert_frag. This is 2
6075 bytes for the opcode and room for the prefix and largest
6076 displacement. */
6077 frag_grow (prefix + 2 + 4);
6078 /* Prefix and 1 opcode byte go in fr_fix. */
6079 p = frag_more (prefix + 1);
6080 if (i.prefix[DATA_PREFIX] != 0)
6081 *p++ = DATA_PREFIX_OPCODE;
6082 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6083 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6084 *p++ = i.prefix[SEG_PREFIX];
6085 if (i.prefix[REX_PREFIX] != 0)
6086 *p++ = i.prefix[REX_PREFIX];
6087 *p = i.tm.base_opcode;
6088
6089 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6090 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6091 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6092 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6093 else
f8a5c266 6094 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6095 subtype |= code16;
3e73aa7c 6096
29b0f896
AM		 6097 sym = i.op[0].disps->X_add_symbol;
6098 off = i.op[0].disps->X_add_number;
3e73aa7c 6099
29b0f896
AM		 6100 if (i.op[0].disps->X_op != O_constant
6101 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6102 {
29b0f896
AM		 6103 /* Handle complex expressions. */
6104 sym = make_expr_symbol (i.op[0].disps);
6105 off = 0;
6106 }
3e73aa7c 6107
29b0f896
AM		 6108 /* 1 possible extra opcode + 4 byte displacement go in var part.
6109 Pass reloc in fr_var. */
6110 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
6111}
3e73aa7c 6112
29b0f896 6113static void
e3bb37b5 6114output_jump (void)
29b0f896
AM		 6115{
6116 char *p;
6117 int size;
3e02c1cc 6118 fixS *fixP;
29b0f896 6119
40fb9820 6120 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6121 {
6122 /* This is a loop or jecxz type instruction. */
6123 size = 1;
6124 if (i.prefix[ADDR_PREFIX] != 0)
6125 {
6126 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6127 i.prefixes -= 1;
6128 }
6129 /* Pentium4 branch hints. */
6130 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6131 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6132 {
6133 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6134 i.prefixes--;
3e73aa7c
JH		 6135 }
6136 }
29b0f896
AM		 6137 else
6138 {
6139 int code16;
3e73aa7c 6140
29b0f896
AM		 6141 code16 = 0;
6142 if (flag_code == CODE_16BIT)
6143 code16 = CODE16;
3e73aa7c 6144
29b0f896
AM		 6145 if (i.prefix[DATA_PREFIX] != 0)
6146 {
6147 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6148 i.prefixes -= 1;
6149 code16 ^= CODE16;
6150 }
252b5132 6151
29b0f896
AM		 6152 size = 4;
6153 if (code16)
6154 size = 2;
6155 }
9fcc94b6 6156
29b0f896
AM		 6157 if (i.prefix[REX_PREFIX] != 0)
6158 {
6159 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6160 i.prefixes -= 1;
6161 }
252b5132 6162
29b0f896
AM		 6163 if (i.prefixes != 0 && !intel_syntax)
6164 as_warn (_("skipping prefixes on this instruction"));
e0890092 6165
42164a71
L		 6166 p = frag_more (i.tm.opcode_length + size);
6167 switch (i.tm.opcode_length)
6168 {
6169 case 2:
6170 *p++ = i.tm.base_opcode >> 8;
6171 case 1:
6172 *p++ = i.tm.base_opcode;
6173 break;
6174 default:
6175 abort ();
6176 }
e0890092 6177
3e02c1cc
AM		 6178 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6179 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6180
6181 /* All jumps handled here are signed, but don't use a signed limit
6182 check for 32 and 16 bit jumps as we want to allow wrap around at
6183 4G and 64k respectively. */
6184 if (size == 1)
6185 fixP->fx_signed = 1;
29b0f896 6186}
e0890092 6187
29b0f896 6188static void
e3bb37b5 6189output_interseg_jump (void)
29b0f896
AM		 6190{
6191 char *p;
6192 int size;
6193 int prefix;
6194 int code16;
252b5132 6195
29b0f896
AM		 6196 code16 = 0;
6197 if (flag_code == CODE_16BIT)
6198 code16 = CODE16;
a217f122 6199
29b0f896
AM		 6200 prefix = 0;
6201 if (i.prefix[DATA_PREFIX] != 0)
6202 {
6203 prefix = 1;
6204 i.prefixes -= 1;
6205 code16 ^= CODE16;
6206 }
6207 if (i.prefix[REX_PREFIX] != 0)
6208 {
6209 prefix++;
6210 i.prefixes -= 1;
6211 }
252b5132 6212
29b0f896
AM		 6213 size = 4;
6214 if (code16)
6215 size = 2;
252b5132 6216
29b0f896
AM		 6217 if (i.prefixes != 0 && !intel_syntax)
6218 as_warn (_("skipping prefixes on this instruction"));
252b5132 6219
29b0f896
AM		 6220 /* 1 opcode; 2 segment; offset */
6221 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6222
29b0f896
AM		 6223 if (i.prefix[DATA_PREFIX] != 0)
6224 *p++ = DATA_PREFIX_OPCODE;
252b5132 6225
29b0f896
AM		 6226 if (i.prefix[REX_PREFIX] != 0)
6227 *p++ = i.prefix[REX_PREFIX];
252b5132 6228
29b0f896
AM		 6229 *p++ = i.tm.base_opcode;
6230 if (i.op[1].imms->X_op == O_constant)
6231 {
6232 offsetT n = i.op[1].imms->X_add_number;
252b5132 6233
29b0f896
AM		 6234 if (size == 2
6235 && !fits_in_unsigned_word (n)
6236 && !fits_in_signed_word (n))
6237 {
6238 as_bad (_("16-bit jump out of range"));
6239 return;
6240 }
6241 md_number_to_chars (p, n, size);
6242 }
6243 else
6244 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6245 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6246 if (i.op[0].imms->X_op != O_constant)
6247 as_bad (_("can't handle non absolute segment in `%s'"),
6248 i.tm.name);
6249 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6250}
a217f122 6251
29b0f896 6252static void
e3bb37b5 6253output_insn (void)
29b0f896 6254{
2bbd9c25
JJ		 6255 fragS *insn_start_frag;
6256 offsetT insn_start_off;
6257
29b0f896
AM		 6258 /* Tie dwarf2 debug info to the address at the start of the insn.
6259 We can't do this after the insn has been output as the current
6260 frag may have been closed off. eg. by frag_var. */
6261 dwarf2_emit_insn (0);
6262
2bbd9c25
JJ		 6263 insn_start_frag = frag_now;
6264 insn_start_off = frag_now_fix ();
6265
29b0f896 6266 /* Output jumps. */
40fb9820 6267 if (i.tm.opcode_modifier.jump)
29b0f896 6268 output_branch ();
40fb9820
L		 6269 else if (i.tm.opcode_modifier.jumpbyte
6270 || i.tm.opcode_modifier.jumpdword)
29b0f896 6271 output_jump ();
40fb9820 6272 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6273 output_interseg_jump ();
6274 else
6275 {
6276 /* Output normal instructions here. */
6277 char *p;
6278 unsigned char *q;
47465058 6279 unsigned int j;
331d2d0d 6280 unsigned int prefix;
4dffcebc 6281
c0f3af97 6282 /* Since the VEX prefix contains the implicit prefix, we don't
89e71f5c 6283 need the explicit prefix. */
c0f3af97 6284 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6285 {
c0f3af97 6286 switch (i.tm.opcode_length)
bc4bd9ab 6287 {
c0f3af97
L		 6288 case 3:
6289 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6290 {
c0f3af97
L		 6291 prefix = (i.tm.base_opcode >> 24) & 0xff;
6292 goto check_prefix;
6293 }
6294 break;
6295 case 2:
6296 if ((i.tm.base_opcode & 0xff0000) != 0)
6297 {
6298 prefix = (i.tm.base_opcode >> 16) & 0xff;
6299 if (i.tm.cpu_flags.bitfield.cpupadlock)
6300 {
4dffcebc 6301check_prefix:
c0f3af97 6302 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6303 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6304 != REPE_PREFIX_OPCODE))
6305 add_prefix (prefix);
6306 }
6307 else
4dffcebc
L		 6308 add_prefix (prefix);
6309 }
c0f3af97
L		 6310 break;
6311 case 1:
6312 break;
6313 default:
6314 abort ();
bc4bd9ab 6315 }
c0f3af97
L		 6316
6317 /* The prefix bytes. */
6318 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6319 if (*q)
6320 FRAG_APPEND_1_CHAR (*q);
0f10071e 6321 }
ae5c1c7b 6322 else
c0f3af97
L		 6323 {
6324 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6325 if (*q)
6326 switch (j)
6327 {
6328 case REX_PREFIX:
6329 /* REX byte is encoded in VEX prefix. */
6330 break;
6331 case SEG_PREFIX:
6332 case ADDR_PREFIX:
6333 FRAG_APPEND_1_CHAR (*q);
6334 break;
6335 default:
6336 /* There should be no other prefixes for instructions
6337 with VEX prefix. */
6338 abort ();
6339 }
6340
6341 /* Now the VEX prefix. */
6342 p = frag_more (i.vex.length);
6343 for (j = 0; j < i.vex.length; j++)
6344 p[j] = i.vex.bytes[j];
6345 }
252b5132 6346
29b0f896 6347 /* Now the opcode; be careful about word order here! */
4dffcebc 6348 if (i.tm.opcode_length == 1)
29b0f896
AM		 6349 {
6350 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6351 }
6352 else
6353 {
4dffcebc 6354 switch (i.tm.opcode_length)
331d2d0d 6355 {
4dffcebc 6356 case 3:
331d2d0d
L		 6357 p = frag_more (3);
6358 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6359 break;
6360 case 2:
6361 p = frag_more (2);
6362 break;
6363 default:
6364 abort ();
6365 break;
331d2d0d 6366 }
0f10071e 6367
29b0f896
AM		 6368 /* Put out high byte first: can't use md_number_to_chars! */
6369 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6370 *p = i.tm.base_opcode & 0xff;
6371 }
3e73aa7c 6372
29b0f896 6373 /* Now the modrm byte and sib byte (if present). */
40fb9820 6374 if (i.tm.opcode_modifier.modrm)
29b0f896 6375 {
4a3523fa
L		 6376 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6377 | i.rm.reg << 3
6378 | i.rm.mode << 6));
29b0f896
AM		 6379 /* If i.rm.regmem == ESP (4)
6380 && i.rm.mode != (Register mode)
6381 && not 16 bit
6382 ==> need second modrm byte. */
6383 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6384 && i.rm.mode != 3
40fb9820 6385 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6386 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6387 | i.sib.index << 3
6388 | i.sib.scale << 6));
29b0f896 6389 }
3e73aa7c 6390
29b0f896 6391 if (i.disp_operands)
2bbd9c25 6392 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6393
29b0f896 6394 if (i.imm_operands)
2bbd9c25 6395 output_imm (insn_start_frag, insn_start_off);
29b0f896 6396 }
252b5132 6397
29b0f896
AM		 6398#ifdef DEBUG386
6399 if (flag_debug)
6400 {
7b81dfbb 6401 pi ("" /*line*/, &i);
29b0f896
AM		 6402 }
6403#endif /* DEBUG386 */
6404}
252b5132 6405
e205caa7
L		 6406/* Return the size of the displacement operand N. */
6407
6408static int
6409disp_size (unsigned int n)
6410{
6411 int size = 4;
40fb9820
L		 6412 if (i.types[n].bitfield.disp64)
6413 size = 8;
6414 else if (i.types[n].bitfield.disp8)
6415 size = 1;
6416 else if (i.types[n].bitfield.disp16)
6417 size = 2;
e205caa7
L		 6418 return size;
6419}
6420
6421/* Return the size of the immediate operand N. */
6422
6423static int
6424imm_size (unsigned int n)
6425{
6426 int size = 4;
40fb9820
L		 6427 if (i.types[n].bitfield.imm64)
6428 size = 8;
6429 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6430 size = 1;
6431 else if (i.types[n].bitfield.imm16)
6432 size = 2;
e205caa7
L		 6433 return size;
6434}
6435
29b0f896 6436static void
64e74474 6437output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6438{
6439 char *p;
6440 unsigned int n;
252b5132 6441
29b0f896
AM		 6442 for (n = 0; n < i.operands; n++)
6443 {
40fb9820 6444 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6445 {
6446 if (i.op[n].disps->X_op == O_constant)
6447 {
e205caa7 6448 int size = disp_size (n);
29b0f896 6449 offsetT val;
252b5132 6450
29b0f896
AM		 6451 val = offset_in_range (i.op[n].disps->X_add_number,
6452 size);
6453 p = frag_more (size);
6454 md_number_to_chars (p, val, size);
6455 }
6456 else
6457 {
f86103b7 6458 enum bfd_reloc_code_real reloc_type;
e205caa7 6459 int size = disp_size (n);
40fb9820 6460 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6461 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6462
e205caa7 6463 /* We can't have 8 bit displacement here. */
9c2799c2 6464 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6465
29b0f896
AM		 6466 /* The PC relative address is computed relative
6467 to the instruction boundary, so in case immediate
6468 fields follows, we need to adjust the value. */
6469 if (pcrel && i.imm_operands)
6470 {
29b0f896 6471 unsigned int n1;
e205caa7 6472 int sz = 0;
252b5132 6473
29b0f896 6474 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6475 if (operand_type_check (i.types[n1], imm))
252b5132 6476 {
e205caa7
L		 6477 /* Only one immediate is allowed for PC
6478 relative address. */
9c2799c2 6479 gas_assert (sz == 0);
e205caa7
L		 6480 sz = imm_size (n1);
6481 i.op[n].disps->X_add_number -= sz;
252b5132 6482 }
29b0f896 6483 /* We should find the immediate. */
9c2799c2 6484 gas_assert (sz != 0);
29b0f896 6485 }
520dc8e8 6486
29b0f896 6487 p = frag_more (size);
2bbd9c25 6488 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6489 if (GOT_symbol
2bbd9c25 6490 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6491 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6492 || reloc_type == BFD_RELOC_X86_64_32S
6493 || (reloc_type == BFD_RELOC_64
6494 && object_64bit))
d6ab8113
JB		 6495 && (i.op[n].disps->X_op == O_symbol
6496 || (i.op[n].disps->X_op == O_add
6497 && ((symbol_get_value_expression
6498 (i.op[n].disps->X_op_symbol)->X_op)
6499 == O_subtract))))
6500 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6501 {
6502 offsetT add;
6503
6504 if (insn_start_frag == frag_now)
6505 add = (p - frag_now->fr_literal) - insn_start_off;
6506 else
6507 {
6508 fragS *fr;
6509
6510 add = insn_start_frag->fr_fix - insn_start_off;
6511 for (fr = insn_start_frag->fr_next;
6512 fr && fr != frag_now; fr = fr->fr_next)
6513 add += fr->fr_fix;
6514 add += p - frag_now->fr_literal;
6515 }
6516
4fa24527 6517 if (!object_64bit)
7b81dfbb
AJ		 6518 {
6519 reloc_type = BFD_RELOC_386_GOTPC;
6520 i.op[n].imms->X_add_number += add;
6521 }
6522 else if (reloc_type == BFD_RELOC_64)
6523 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6524 else
7b81dfbb
AJ		 6525 /* Don't do the adjustment for x86-64, as there
6526 the pcrel addressing is relative to the _next_
6527 insn, and that is taken care of in other code. */
d6ab8113 6528 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6529 }
062cd5e7 6530 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6531 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6532 }
6533 }
6534 }
6535}
252b5132 6536
29b0f896 6537static void
64e74474 6538output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6539{
6540 char *p;
6541 unsigned int n;
252b5132 6542
29b0f896
AM		 6543 for (n = 0; n < i.operands; n++)
6544 {
40fb9820 6545 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6546 {
6547 if (i.op[n].imms->X_op == O_constant)
6548 {
e205caa7 6549 int size = imm_size (n);
29b0f896 6550 offsetT val;
b4cac588 6551
29b0f896
AM		 6552 val = offset_in_range (i.op[n].imms->X_add_number,
6553 size);
6554 p = frag_more (size);
6555 md_number_to_chars (p, val, size);
6556 }
6557 else
6558 {
6559 /* Not absolute_section.
6560 Need a 32-bit fixup (don't support 8bit
6561 non-absolute imms). Try to support other
6562 sizes ... */
f86103b7 6563 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6564 int size = imm_size (n);
6565 int sign;
29b0f896 6566
40fb9820 6567 if (i.types[n].bitfield.imm32s
a7d61044 6568 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6569 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6570 sign = 1;
e205caa7
L		 6571 else
6572 sign = 0;
520dc8e8 6573
29b0f896
AM		 6574 p = frag_more (size);
6575 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6576
2bbd9c25
JJ		 6577 /* This is tough to explain. We end up with this one if we
6578 * have operands that look like
6579 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6580 * obtain the absolute address of the GOT, and it is strongly
6581 * preferable from a performance point of view to avoid using
6582 * a runtime relocation for this. The actual sequence of
6583 * instructions often look something like:
6584 *
6585 * call .L66
6586 * .L66:
6587 * popl %ebx
6588 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6589 *
6590 * The call and pop essentially return the absolute address
6591 * of the label .L66 and store it in %ebx. The linker itself
6592 * will ultimately change the first operand of the addl so
6593 * that %ebx points to the GOT, but to keep things simple, the
6594 * .o file must have this operand set so that it generates not
6595 * the absolute address of .L66, but the absolute address of
6596 * itself. This allows the linker itself simply treat a GOTPC
6597 * relocation as asking for a pcrel offset to the GOT to be
6598 * added in, and the addend of the relocation is stored in the
6599 * operand field for the instruction itself.
6600 *
6601 * Our job here is to fix the operand so that it would add
6602 * the correct offset so that %ebx would point to itself. The
6603 * thing that is tricky is that .-.L66 will point to the
6604 * beginning of the instruction, so we need to further modify
6605 * the operand so that it will point to itself. There are
6606 * other cases where you have something like:
6607 *
6608 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6609 *
6610 * and here no correction would be required. Internally in
6611 * the assembler we treat operands of this form as not being
6612 * pcrel since the '.' is explicitly mentioned, and I wonder
6613 * whether it would simplify matters to do it this way. Who
6614 * knows. In earlier versions of the PIC patches, the
6615 * pcrel_adjust field was used to store the correction, but
6616 * since the expression is not pcrel, I felt it would be
6617 * confusing to do it this way. */
6618
d6ab8113 6619 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6620 || reloc_type == BFD_RELOC_X86_64_32S
6621 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6622 && GOT_symbol
6623 && GOT_symbol == i.op[n].imms->X_add_symbol
6624 && (i.op[n].imms->X_op == O_symbol
6625 || (i.op[n].imms->X_op == O_add
6626 && ((symbol_get_value_expression
6627 (i.op[n].imms->X_op_symbol)->X_op)
6628 == O_subtract))))
6629 {
2bbd9c25
JJ		 6630 offsetT add;
6631
6632 if (insn_start_frag == frag_now)
6633 add = (p - frag_now->fr_literal) - insn_start_off;
6634 else
6635 {
6636 fragS *fr;
6637
6638 add = insn_start_frag->fr_fix - insn_start_off;
6639 for (fr = insn_start_frag->fr_next;
6640 fr && fr != frag_now; fr = fr->fr_next)
6641 add += fr->fr_fix;
6642 add += p - frag_now->fr_literal;
6643 }
6644
4fa24527 6645 if (!object_64bit)
d6ab8113 6646 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6647 else if (size == 4)
d6ab8113 6648 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6649 else if (size == 8)
6650 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6651 i.op[n].imms->X_add_number += add;
29b0f896 6652 }
29b0f896
AM		 6653 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6654 i.op[n].imms, 0, reloc_type);
6655 }
6656 }
6657 }
252b5132
RH		 6658}
6659\f
d182319b
JB		 6660/* x86_cons_fix_new is called via the expression parsing code when a
6661 reloc is needed. We use this hook to get the correct .got reloc. */
6662static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6663static int cons_sign = -1;
6664
6665void
e3bb37b5 6666x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6667 expressionS *exp)
d182319b
JB		 6668{
6669 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6670
6671 got_reloc = NO_RELOC;
6672
6673#ifdef TE_PE
6674 if (exp->X_op == O_secrel)
6675 {
6676 exp->X_op = O_symbol;
6677 r = BFD_RELOC_32_SECREL;
6678 }
6679#endif
6680
6681 fix_new_exp (frag, off, len, exp, 0, r);
6682}
6683
357d1bd8
L		 6684/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6685 purpose of the `.dc.a' internal pseudo-op. */
6686
6687int
6688x86_address_bytes (void)
6689{
6690 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
6691 return 4;
6692 return stdoutput->arch_info->bits_per_address / 8;
6693}
6694
d382c579
TG		 6695#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6696 || defined (LEX_AT)
718ddfc0
JB		 6697# define lex_got(reloc, adjust, types) NULL
6698#else
f3c180ae
AM		 6699/* Parse operands of the form
6700 <symbol>@GOTOFF+<nnn>
6701 and similar .plt or .got references.
6702
6703 If we find one, set up the correct relocation in RELOC and copy the
6704 input string, minus the `@GOTOFF' into a malloc'd buffer for
6705 parsing by the calling routine. Return this buffer, and if ADJUST
6706 is non-null set it to the length of the string we removed from the
6707 input line. Otherwise return NULL. */
6708static char *
91d6fa6a 6709lex_got (enum bfd_reloc_code_real *rel,
64e74474 6710 int *adjust,
40fb9820 6711 i386_operand_type *types)
f3c180ae 6712{
7b81dfbb
AJ		 6713 /* Some of the relocations depend on the size of what field is to
6714 be relocated. But in our callers i386_immediate and i386_displacement
6715 we don't yet know the operand size (this will be set by insn
6716 matching). Hence we record the word32 relocation here,
6717 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6718 static const struct {
6719 const char *str;
cff8d58a 6720 int len;
4fa24527 6721 const enum bfd_reloc_code_real rel[2];
40fb9820 6722 const i386_operand_type types64;
f3c180ae 6723 } gotrel[] = {
8ce3d284 6724#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 6725 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
6726 BFD_RELOC_SIZE32 },
6727 OPERAND_TYPE_IMM32_64 },
8ce3d284 6728#endif
cff8d58a
L		 6729 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6730 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6731 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6732 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6733 BFD_RELOC_X86_64_PLT32 },
40fb9820 6734 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6735 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6736 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6737 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6738 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6739 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6740 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6741 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6742 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6743 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6744 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6745 BFD_RELOC_X86_64_TLSGD },
40fb9820 6746 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6747 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6748 _dummy_first_bfd_reloc_code_real },
40fb9820 6749 OPERAND_TYPE_NONE },
cff8d58a
L		 6750 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6751 BFD_RELOC_X86_64_TLSLD },
40fb9820 6752 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6753 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6754 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6755 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6756 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6757 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6758 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6759 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6760 _dummy_first_bfd_reloc_code_real },
40fb9820 6761 OPERAND_TYPE_NONE },
cff8d58a
L		 6762 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6763 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6764 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6765 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6766 _dummy_first_bfd_reloc_code_real },
40fb9820 6767 OPERAND_TYPE_NONE },
cff8d58a
L		 6768 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6769 _dummy_first_bfd_reloc_code_real },
40fb9820 6770 OPERAND_TYPE_NONE },
cff8d58a
L		 6771 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6772 BFD_RELOC_X86_64_GOT32 },
40fb9820 6773 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6774 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6775 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6776 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6777 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6778 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6779 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6780 };
6781 char *cp;
6782 unsigned int j;
6783
d382c579 6784#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 6785 if (!IS_ELF)
6786 return NULL;
d382c579 6787#endif
718ddfc0 6788
f3c180ae 6789 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6790 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6791 return NULL;
6792
47465058 6793 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6794 {
cff8d58a 6795 int len = gotrel[j].len;
28f81592 6796 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6797 {
4fa24527 6798 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6799 {
28f81592
AM		 6800 int first, second;
6801 char *tmpbuf, *past_reloc;
f3c180ae 6802
91d6fa6a 6803 *rel = gotrel[j].rel[object_64bit];
f3c180ae 6804
3956db08
JB		 6805 if (types)
6806 {
6807 if (flag_code != CODE_64BIT)
40fb9820
L		 6808 {
6809 types->bitfield.imm32 = 1;
6810 types->bitfield.disp32 = 1;
6811 }
3956db08
JB		 6812 else
6813 *types = gotrel[j].types64;
6814 }
6815
8fd4256d 6816 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 6817 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6818
28f81592 6819 /* The length of the first part of our input line. */
f3c180ae 6820 first = cp - input_line_pointer;
28f81592
AM		 6821
6822 /* The second part goes from after the reloc token until
67c11a9b 6823 (and including) an end_of_line char or comma. */
28f81592 6824 past_reloc = cp + 1 + len;
67c11a9b
AM		 6825 cp = past_reloc;
6826 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6827 ++cp;
6828 second = cp + 1 - past_reloc;
28f81592
AM		 6829
6830 /* Allocate and copy string. The trailing NUL shouldn't
6831 be necessary, but be safe. */
1e9cc1c2 6832 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6833 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6834 if (second != 0 && *past_reloc != ' ')
6835 /* Replace the relocation token with ' ', so that
6836 errors like foo@GOTOFF1 will be detected. */
6837 tmpbuf[first++] = ' ';
af89796a
L		 6838 else
6839 /* Increment length by 1 if the relocation token is
6840 removed. */
6841 len++;
6842 if (adjust)
6843 *adjust = len;
0787a12d
AM		 6844 memcpy (tmpbuf + first, past_reloc, second);
6845 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6846 return tmpbuf;
6847 }
6848
4fa24527
JB		 6849 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6850 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6851 return NULL;
6852 }
6853 }
6854
6855 /* Might be a symbol version string. Don't as_bad here. */
6856 return NULL;
6857}
4e4f7c87 6858#endif
f3c180ae 6859
a988325c
NC		 6860#ifdef TE_PE
6861#ifdef lex_got
6862#undef lex_got
6863#endif
6864/* Parse operands of the form
6865 <symbol>@SECREL32+<nnn>
6866
6867 If we find one, set up the correct relocation in RELOC and copy the
6868 input string, minus the `@SECREL32' into a malloc'd buffer for
6869 parsing by the calling routine. Return this buffer, and if ADJUST
6870 is non-null set it to the length of the string we removed from the
34bca508
L		 6871 input line. Otherwise return NULL.
6872
a988325c
NC		 6873 This function is copied from the ELF version above adjusted for PE targets. */
6874
6875static char *
6876lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
6877 int *adjust ATTRIBUTE_UNUSED,
6878 i386_operand_type *types ATTRIBUTE_UNUSED)
6879{
6880 static const struct
6881 {
6882 const char *str;
6883 int len;
6884 const enum bfd_reloc_code_real rel[2];
6885 const i386_operand_type types64;
6886 }
6887 gotrel[] =
6888 {
6889 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
6890 BFD_RELOC_32_SECREL },
6891 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6892 };
6893
6894 char *cp;
6895 unsigned j;
6896
6897 for (cp = input_line_pointer; *cp != '@'; cp++)
6898 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
6899 return NULL;
6900
6901 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
6902 {
6903 int len = gotrel[j].len;
6904
6905 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
6906 {
6907 if (gotrel[j].rel[object_64bit] != 0)
6908 {
6909 int first, second;
6910 char *tmpbuf, *past_reloc;
6911
6912 *rel = gotrel[j].rel[object_64bit];
6913 if (adjust)
6914 *adjust = len;
6915
6916 if (types)
6917 {
6918 if (flag_code != CODE_64BIT)
6919 {
6920 types->bitfield.imm32 = 1;
6921 types->bitfield.disp32 = 1;
6922 }
6923 else
6924 *types = gotrel[j].types64;
6925 }
6926
6927 /* The length of the first part of our input line. */
6928 first = cp - input_line_pointer;
6929
6930 /* The second part goes from after the reloc token until
6931 (and including) an end_of_line char or comma. */
6932 past_reloc = cp + 1 + len;
6933 cp = past_reloc;
6934 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6935 ++cp;
6936 second = cp + 1 - past_reloc;
6937
6938 /* Allocate and copy string. The trailing NUL shouldn't
6939 be necessary, but be safe. */
6940 tmpbuf = (char *) xmalloc (first + second + 2);
6941 memcpy (tmpbuf, input_line_pointer, first);
6942 if (second != 0 && *past_reloc != ' ')
6943 /* Replace the relocation token with ' ', so that
6944 errors like foo@SECLREL321 will be detected. */
6945 tmpbuf[first++] = ' ';
6946 memcpy (tmpbuf + first, past_reloc, second);
6947 tmpbuf[first + second] = '\0';
6948 return tmpbuf;
6949 }
6950
6951 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6952 gotrel[j].str, 1 << (5 + object_64bit));
6953 return NULL;
6954 }
6955 }
6956
6957 /* Might be a symbol version string. Don't as_bad here. */
6958 return NULL;
6959}
6960
6961#endif /* TE_PE */
6962
f3c180ae 6963void
e3bb37b5 6964x86_cons (expressionS *exp, int size)
f3c180ae 6965{
ee86248c
JB		 6966 intel_syntax = -intel_syntax;
6967
3c7b9c2c 6968 exp->X_md = 0;
4fa24527 6969 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6970 {
6971 /* Handle @GOTOFF and the like in an expression. */
6972 char *save;
6973 char *gotfree_input_line;
4a57f2cf 6974 int adjust = 0;
f3c180ae
AM		 6975
6976 save = input_line_pointer;
3956db08 6977 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6978 if (gotfree_input_line)
6979 input_line_pointer = gotfree_input_line;
6980
6981 expression (exp);
6982
6983 if (gotfree_input_line)
6984 {
6985 /* expression () has merrily parsed up to the end of line,
6986 or a comma - in the wrong buffer. Transfer how far
6987 input_line_pointer has moved to the right buffer. */
6988 input_line_pointer = (save
6989 + (input_line_pointer - gotfree_input_line)
6990 + adjust);
6991 free (gotfree_input_line);
3992d3b7
AM		 6992 if (exp->X_op == O_constant
6993 || exp->X_op == O_absent
6994 || exp->X_op == O_illegal
0398aac5 6995 || exp->X_op == O_register
3992d3b7
AM		 6996 || exp->X_op == O_big)
6997 {
6998 char c = *input_line_pointer;
6999 *input_line_pointer = 0;
7000 as_bad (_("missing or invalid expression `%s'"), save);
7001 *input_line_pointer = c;
7002 }
f3c180ae
AM		 7003 }
7004 }
7005 else
7006 expression (exp);
ee86248c
JB		 7007
7008 intel_syntax = -intel_syntax;
7009
7010 if (intel_syntax)
7011 i386_intel_simplify (exp);
f3c180ae 7012}
f3c180ae 7013
9f32dd5b
L		 7014static void
7015signed_cons (int size)
6482c264 7016{
d182319b
JB		 7017 if (flag_code == CODE_64BIT)
7018 cons_sign = 1;
7019 cons (size);
7020 cons_sign = -1;
6482c264
NC		 7021}
7022
d182319b 7023#ifdef TE_PE
6482c264 7024static void
7016a5d5 7025pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7026{
7027 expressionS exp;
7028
7029 do
7030 {
7031 expression (&exp);
7032 if (exp.X_op == O_symbol)
7033 exp.X_op = O_secrel;
7034
7035 emit_expr (&exp, 4);
7036 }
7037 while (*input_line_pointer++ == ',');
7038
7039 input_line_pointer--;
7040 demand_empty_rest_of_line ();
7041}
6482c264
NC		 7042#endif
7043
252b5132 7044static int
70e41ade 7045i386_immediate (char *imm_start)
252b5132
RH		 7046{
7047 char *save_input_line_pointer;
f3c180ae 7048 char *gotfree_input_line;
252b5132 7049 segT exp_seg = 0;
47926f60 7050 expressionS *exp;
40fb9820
L		 7051 i386_operand_type types;
7052
0dfbf9d7 7053 operand_type_set (&types, ~0);
252b5132
RH		 7054
7055 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7056 {
31b2323c
L		 7057 as_bad (_("at most %d immediate operands are allowed"),
7058 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7059 return 0;
7060 }
7061
7062 exp = &im_expressions[i.imm_operands++];
520dc8e8 7063 i.op[this_operand].imms = exp;
252b5132
RH		 7064
7065 if (is_space_char (*imm_start))
7066 ++imm_start;
7067
7068 save_input_line_pointer = input_line_pointer;
7069 input_line_pointer = imm_start;
7070
3956db08 7071 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7072 if (gotfree_input_line)
7073 input_line_pointer = gotfree_input_line;
252b5132
RH		 7074
7075 exp_seg = expression (exp);
7076
83183c0c 7077 SKIP_WHITESPACE ();
252b5132 7078 if (*input_line_pointer)
f3c180ae 7079 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7080
7081 input_line_pointer = save_input_line_pointer;
f3c180ae 7082 if (gotfree_input_line)
ee86248c
JB		 7083 {
7084 free (gotfree_input_line);
7085
7086 if (exp->X_op == O_constant || exp->X_op == O_register)
7087 exp->X_op = O_illegal;
7088 }
7089
7090 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7091}
252b5132 7092
ee86248c
JB		 7093static int
7094i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7095 i386_operand_type types, const char *imm_start)
7096{
7097 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7098 {
313c53d1
L		 7099 if (imm_start)
7100 as_bad (_("missing or invalid immediate expression `%s'"),
7101 imm_start);
3992d3b7 7102 return 0;
252b5132 7103 }
3e73aa7c 7104 else if (exp->X_op == O_constant)
252b5132 7105 {
47926f60 7106 /* Size it properly later. */
40fb9820 7107 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7108 /* If not 64bit, sign extend val. */
7109 if (flag_code != CODE_64BIT
4eed87de
AM		 7110 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7111 exp->X_add_number
7112 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7113 }
4c63da97 7114#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7115 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7116 && exp_seg != absolute_section
47926f60 7117 && exp_seg != text_section
24eab124
AM		 7118 && exp_seg != data_section
7119 && exp_seg != bss_section
7120 && exp_seg != undefined_section
f86103b7 7121 && !bfd_is_com_section (exp_seg))
252b5132 7122 {
d0b47220 7123 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7124 return 0;
7125 }
7126#endif
bb8f5920
L		 7127 else if (!intel_syntax && exp->X_op == O_register)
7128 {
313c53d1
L		 7129 if (imm_start)
7130 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7131 return 0;
7132 }
252b5132
RH		 7133 else
7134 {
7135 /* This is an address. The size of the address will be
24eab124 7136 determined later, depending on destination register,
3e73aa7c 7137 suffix, or the default for the section. */
40fb9820
L		 7138 i.types[this_operand].bitfield.imm8 = 1;
7139 i.types[this_operand].bitfield.imm16 = 1;
7140 i.types[this_operand].bitfield.imm32 = 1;
7141 i.types[this_operand].bitfield.imm32s = 1;
7142 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7143 i.types[this_operand] = operand_type_and (i.types[this_operand],
7144 types);
252b5132
RH		 7145 }
7146
7147 return 1;
7148}
7149
551c1ca1 7150static char *
e3bb37b5 7151i386_scale (char *scale)
252b5132 7152{
551c1ca1
AM		 7153 offsetT val;
7154 char *save = input_line_pointer;
252b5132 7155
551c1ca1
AM		 7156 input_line_pointer = scale;
7157 val = get_absolute_expression ();
7158
7159 switch (val)
252b5132 7160 {
551c1ca1 7161 case 1:
252b5132
RH		 7162 i.log2_scale_factor = 0;
7163 break;
551c1ca1 7164 case 2:
252b5132
RH		 7165 i.log2_scale_factor = 1;
7166 break;
551c1ca1 7167 case 4:
252b5132
RH		 7168 i.log2_scale_factor = 2;
7169 break;
551c1ca1 7170 case 8:
252b5132
RH		 7171 i.log2_scale_factor = 3;
7172 break;
7173 default:
a724f0f4
JB		 7174 {
7175 char sep = *input_line_pointer;
7176
7177 *input_line_pointer = '\0';
7178 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7179 scale);
7180 *input_line_pointer = sep;
7181 input_line_pointer = save;
7182 return NULL;
7183 }
252b5132 7184 }
29b0f896 7185 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7186 {
7187 as_warn (_("scale factor of %d without an index register"),
24eab124 7188 1 << i.log2_scale_factor);
252b5132 7189 i.log2_scale_factor = 0;
252b5132 7190 }
551c1ca1
AM		 7191 scale = input_line_pointer;
7192 input_line_pointer = save;
7193 return scale;
252b5132
RH		 7194}
7195
252b5132 7196static int
e3bb37b5 7197i386_displacement (char *disp_start, char *disp_end)
252b5132 7198{
29b0f896 7199 expressionS *exp;
252b5132
RH		 7200 segT exp_seg = 0;
7201 char *save_input_line_pointer;
f3c180ae 7202 char *gotfree_input_line;
40fb9820
L		 7203 int override;
7204 i386_operand_type bigdisp, types = anydisp;
3992d3b7 7205 int ret;
252b5132 7206
31b2323c
L		 7207 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7208 {
7209 as_bad (_("at most %d displacement operands are allowed"),
7210 MAX_MEMORY_OPERANDS);
7211 return 0;
7212 }
7213
0dfbf9d7 7214 operand_type_set (&bigdisp, 0);
40fb9820
L		 7215 if ((i.types[this_operand].bitfield.jumpabsolute)
7216 || (!current_templates->start->opcode_modifier.jump
7217 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 7218 {
40fb9820 7219 bigdisp.bitfield.disp32 = 1;
e05278af 7220 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 7221 if (flag_code == CODE_64BIT)
7222 {
7223 if (!override)
7224 {
7225 bigdisp.bitfield.disp32s = 1;
7226 bigdisp.bitfield.disp64 = 1;
7227 }
7228 }
7229 else if ((flag_code == CODE_16BIT) ^ override)
7230 {
7231 bigdisp.bitfield.disp32 = 0;
7232 bigdisp.bitfield.disp16 = 1;
7233 }
e05278af
JB		 7234 }
7235 else
7236 {
7237 /* For PC-relative branches, the width of the displacement
7238 is dependent upon data size, not address size. */
e05278af 7239 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 7240 if (flag_code == CODE_64BIT)
7241 {
7242 if (override || i.suffix == WORD_MNEM_SUFFIX)
7243 bigdisp.bitfield.disp16 = 1;
7244 else
7245 {
7246 bigdisp.bitfield.disp32 = 1;
7247 bigdisp.bitfield.disp32s = 1;
7248 }
7249 }
7250 else
e05278af
JB		 7251 {
7252 if (!override)
7253 override = (i.suffix == (flag_code != CODE_16BIT
7254 ? WORD_MNEM_SUFFIX
7255 : LONG_MNEM_SUFFIX));
40fb9820
L		 7256 bigdisp.bitfield.disp32 = 1;
7257 if ((flag_code == CODE_16BIT) ^ override)
7258 {
7259 bigdisp.bitfield.disp32 = 0;
7260 bigdisp.bitfield.disp16 = 1;
7261 }
e05278af 7262 }
e05278af 7263 }
c6fb90c8
L		 7264 i.types[this_operand] = operand_type_or (i.types[this_operand],
7265 bigdisp);
252b5132
RH		 7266
7267 exp = &disp_expressions[i.disp_operands];
520dc8e8 7268 i.op[this_operand].disps = exp;
252b5132
RH		 7269 i.disp_operands++;
7270 save_input_line_pointer = input_line_pointer;
7271 input_line_pointer = disp_start;
7272 END_STRING_AND_SAVE (disp_end);
7273
7274#ifndef GCC_ASM_O_HACK
7275#define GCC_ASM_O_HACK 0
7276#endif
7277#if GCC_ASM_O_HACK
7278 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 7279 if (i.types[this_operand].bitfield.baseIndex
24eab124 7280 && displacement_string_end[-1] == '+')
252b5132
RH		 7281 {
7282 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 7283 constraint within gcc asm statements.
7284 For instance:
7285
7286 #define _set_tssldt_desc(n,addr,limit,type) \
7287 __asm__ __volatile__ ( \
7288 "movw %w2,%0\n\t" \
7289 "movw %w1,2+%0\n\t" \
7290 "rorl $16,%1\n\t" \
7291 "movb %b1,4+%0\n\t" \
7292 "movb %4,5+%0\n\t" \
7293 "movb $0,6+%0\n\t" \
7294 "movb %h1,7+%0\n\t" \
7295 "rorl $16,%1" \
7296 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7297
7298 This works great except that the output assembler ends
7299 up looking a bit weird if it turns out that there is
7300 no offset. You end up producing code that looks like:
7301
7302 #APP
7303 movw $235,(%eax)
7304 movw %dx,2+(%eax)
7305 rorl $16,%edx
7306 movb %dl,4+(%eax)
7307 movb $137,5+(%eax)
7308 movb $0,6+(%eax)
7309 movb %dh,7+(%eax)
7310 rorl $16,%edx
7311 #NO_APP
7312
47926f60 7313 So here we provide the missing zero. */
24eab124
AM		 7314
7315 *displacement_string_end = '0';
252b5132
RH		 7316 }
7317#endif
3956db08 7318 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7319 if (gotfree_input_line)
7320 input_line_pointer = gotfree_input_line;
252b5132 7321
24eab124 7322 exp_seg = expression (exp);
252b5132 7323
636c26b0
AM		 7324 SKIP_WHITESPACE ();
7325 if (*input_line_pointer)
7326 as_bad (_("junk `%s' after expression"), input_line_pointer);
7327#if GCC_ASM_O_HACK
7328 RESTORE_END_STRING (disp_end + 1);
7329#endif
636c26b0 7330 input_line_pointer = save_input_line_pointer;
636c26b0 7331 if (gotfree_input_line)
ee86248c
JB		 7332 {
7333 free (gotfree_input_line);
7334
7335 if (exp->X_op == O_constant || exp->X_op == O_register)
7336 exp->X_op = O_illegal;
7337 }
7338
7339 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
7340
7341 RESTORE_END_STRING (disp_end);
7342
7343 return ret;
7344}
7345
7346static int
7347i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7348 i386_operand_type types, const char *disp_start)
7349{
7350 i386_operand_type bigdisp;
7351 int ret = 1;
636c26b0 7352
24eab124
AM		 7353 /* We do this to make sure that the section symbol is in
7354 the symbol table. We will ultimately change the relocation
47926f60 7355 to be relative to the beginning of the section. */
1ae12ab7 7356 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 7357 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
7358 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 7359 {
636c26b0 7360 if (exp->X_op != O_symbol)
3992d3b7 7361 goto inv_disp;
636c26b0 7362
e5cb08ac 7363 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 7364 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
7365 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 7366 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 7367 exp->X_op = O_subtract;
7368 exp->X_op_symbol = GOT_symbol;
1ae12ab7 7369 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 7370 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 7371 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
7372 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 7373 else
29b0f896 7374 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 7375 }
252b5132 7376
3992d3b7
AM		 7377 else if (exp->X_op == O_absent
7378 || exp->X_op == O_illegal
ee86248c 7379 || exp->X_op == O_big)
2daf4fd8 7380 {
3992d3b7
AM		 7381 inv_disp:
7382 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 7383 disp_start);
3992d3b7 7384 ret = 0;
2daf4fd8
AM		 7385 }
7386
0e1147d9
L		 7387 else if (flag_code == CODE_64BIT
7388 && !i.prefix[ADDR_PREFIX]
7389 && exp->X_op == O_constant)
7390 {
7391 /* Since displacement is signed extended to 64bit, don't allow
7392 disp32 and turn off disp32s if they are out of range. */
7393 i.types[this_operand].bitfield.disp32 = 0;
7394 if (!fits_in_signed_long (exp->X_add_number))
7395 {
7396 i.types[this_operand].bitfield.disp32s = 0;
7397 if (i.types[this_operand].bitfield.baseindex)
7398 {
7399 as_bad (_("0x%lx out range of signed 32bit displacement"),
7400 (long) exp->X_add_number);
7401 ret = 0;
7402 }
7403 }
7404 }
7405
4c63da97 7406#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7407 else if (exp->X_op != O_constant
7408 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7409 && exp_seg != absolute_section
7410 && exp_seg != text_section
7411 && exp_seg != data_section
7412 && exp_seg != bss_section
7413 && exp_seg != undefined_section
7414 && !bfd_is_com_section (exp_seg))
24eab124 7415 {
d0b47220 7416 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7417 ret = 0;
24eab124 7418 }
252b5132 7419#endif
3956db08 7420
40fb9820
L		 7421 /* Check if this is a displacement only operand. */
7422 bigdisp = i.types[this_operand];
7423 bigdisp.bitfield.disp8 = 0;
7424 bigdisp.bitfield.disp16 = 0;
7425 bigdisp.bitfield.disp32 = 0;
7426 bigdisp.bitfield.disp32s = 0;
7427 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7428 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7429 i.types[this_operand] = operand_type_and (i.types[this_operand],
7430 types);
3956db08 7431
3992d3b7 7432 return ret;
252b5132
RH		 7433}
7434
eecb386c 7435/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7436 Return 1 on success, 0 on a failure. */
7437
252b5132 7438static int
e3bb37b5 7439i386_index_check (const char *operand_string)
252b5132 7440{
3e73aa7c 7441 int ok;
fc0763e6 7442 const char *kind = "base/index";
24eab124 7443#if INFER_ADDR_PREFIX
eecb386c
AM		 7444 int fudged = 0;
7445
24eab124
AM		 7446 tryprefix:
7447#endif
3e73aa7c 7448 ok = 1;
fc0763e6
JB		 7449 if (current_templates->start->opcode_modifier.isstring
7450 && !current_templates->start->opcode_modifier.immext
7451 && (current_templates->end[-1].opcode_modifier.isstring
7452 || i.mem_operands))
7453 {
7454 /* Memory operands of string insns are special in that they only allow
7455 a single register (rDI, rSI, or rBX) as their memory address. */
7456 unsigned int expected;
7457
7458 kind = "string address";
7459
7460 if (current_templates->start->opcode_modifier.w)
7461 {
7462 i386_operand_type type = current_templates->end[-1].operand_types[0];
7463
7464 if (!type.bitfield.baseindex
7465 || ((!i.mem_operands != !intel_syntax)
7466 && current_templates->end[-1].operand_types[1]
7467 .bitfield.baseindex))
7468 type = current_templates->end[-1].operand_types[1];
7469 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7470 }
7471 else
7472 expected = 3 /* rBX */;
7473
7474 if (!i.base_reg || i.index_reg
7475 || operand_type_check (i.types[this_operand], disp))
7476 ok = -1;
7477 else if (!(flag_code == CODE_64BIT
7478 ? i.prefix[ADDR_PREFIX]
7479 ? i.base_reg->reg_type.bitfield.reg32
7480 : i.base_reg->reg_type.bitfield.reg64
7481 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7482 ? i.base_reg->reg_type.bitfield.reg32
7483 : i.base_reg->reg_type.bitfield.reg16))
7484 ok = 0;
4c692bc7 7485 else if (register_number (i.base_reg) != expected)
fc0763e6
JB		 7486 ok = -1;
7487
7488 if (ok < 0)
7489 {
7490 unsigned int j;
7491
7492 for (j = 0; j < i386_regtab_size; ++j)
7493 if ((flag_code == CODE_64BIT
7494 ? i.prefix[ADDR_PREFIX]
7495 ? i386_regtab[j].reg_type.bitfield.reg32
7496 : i386_regtab[j].reg_type.bitfield.reg64
7497 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7498 ? i386_regtab[j].reg_type.bitfield.reg32
7499 : i386_regtab[j].reg_type.bitfield.reg16)
4c692bc7 7500 && register_number(i386_regtab + j) == expected)
fc0763e6 7501 break;
9c2799c2 7502 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7503 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7504 operand_string,
7505 intel_syntax ? '[' : '(',
7506 register_prefix,
7507 i386_regtab[j].reg_name,
7508 intel_syntax ? ']' : ')');
7509 ok = 1;
7510 }
7511 }
7512 else if (flag_code == CODE_64BIT)
64e74474 7513 {
64e74474 7514 if ((i.base_reg
40fb9820
L		 7515 && ((i.prefix[ADDR_PREFIX] == 0
7516 && !i.base_reg->reg_type.bitfield.reg64)
7517 || (i.prefix[ADDR_PREFIX]
7518 && !i.base_reg->reg_type.bitfield.reg32))
7519 && (i.index_reg
9a04903e
JB		 7520 || i.base_reg->reg_num !=
7521 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7522 || (i.index_reg
6c30d220
L		 7523 && !(i.index_reg->reg_type.bitfield.regxmm
7524 || i.index_reg->reg_type.bitfield.regymm)
40fb9820
L		 7525 && (!i.index_reg->reg_type.bitfield.baseindex
7526 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7527 && i.index_reg->reg_num != RegRiz
7528 && !i.index_reg->reg_type.bitfield.reg64
7529 )
40fb9820 7530 || (i.prefix[ADDR_PREFIX]
db51cc60 7531 && i.index_reg->reg_num != RegEiz
40fb9820 7532 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7533 ok = 0;
3e73aa7c
JH		 7534 }
7535 else
7536 {
7537 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7538 {
7539 /* 16bit checks. */
7540 if ((i.base_reg
40fb9820
L		 7541 && (!i.base_reg->reg_type.bitfield.reg16
7542 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7543 || (i.index_reg
40fb9820
L		 7544 && (!i.index_reg->reg_type.bitfield.reg16
7545 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7546 || !(i.base_reg
7547 && i.base_reg->reg_num < 6
7548 && i.index_reg->reg_num >= 6
7549 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7550 ok = 0;
7551 }
7552 else
e5cb08ac 7553 {
3e73aa7c
JH		 7554 /* 32bit checks. */
7555 if ((i.base_reg
40fb9820 7556 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7557 || (i.index_reg
6c30d220
L		 7558 && !i.index_reg->reg_type.bitfield.regxmm
7559 && !i.index_reg->reg_type.bitfield.regymm
db51cc60
L		 7560 && ((!i.index_reg->reg_type.bitfield.reg32
7561 && i.index_reg->reg_num != RegEiz)
40fb9820 7562 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7563 ok = 0;
3e73aa7c
JH		 7564 }
7565 }
7566 if (!ok)
24eab124
AM		 7567 {
7568#if INFER_ADDR_PREFIX
fc0763e6 7569 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7570 {
7571 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7572 i.prefixes += 1;
b23bac36
AM		 7573 /* Change the size of any displacement too. At most one of
7574 Disp16 or Disp32 is set.
7575 FIXME. There doesn't seem to be any real need for separate
7576 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7577 Removing them would probably clean up the code quite a lot. */
4eed87de 7578 if (flag_code != CODE_64BIT
40fb9820
L		 7579 && (i.types[this_operand].bitfield.disp16
7580 || i.types[this_operand].bitfield.disp32))
7581 i.types[this_operand]
c6fb90c8 7582 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7583 fudged = 1;
24eab124
AM		 7584 goto tryprefix;
7585 }
eecb386c 7586 if (fudged)
fc0763e6
JB		 7587 as_bad (_("`%s' is not a valid %s expression"),
7588 operand_string,
7589 kind);
eecb386c 7590 else
c388dee8 7591#endif
fc0763e6 7592 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7593 operand_string,
fc0763e6
JB		 7594 flag_code_names[i.prefix[ADDR_PREFIX]
7595 ? flag_code == CODE_32BIT
7596 ? CODE_16BIT
7597 : CODE_32BIT
7598 : flag_code],
7599 kind);
24eab124 7600 }
20f0a1fc 7601 return ok;
24eab124 7602}
252b5132 7603
fc0763e6 7604/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7605 on error. */
252b5132 7606
252b5132 7607static int
a7619375 7608i386_att_operand (char *operand_string)
252b5132 7609{
af6bdddf
AM		 7610 const reg_entry *r;
7611 char *end_op;
24eab124 7612 char *op_string = operand_string;
252b5132 7613
24eab124 7614 if (is_space_char (*op_string))
252b5132
RH		 7615 ++op_string;
7616
24eab124 7617 /* We check for an absolute prefix (differentiating,
47926f60 7618 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7619 if (*op_string == ABSOLUTE_PREFIX)
7620 {
7621 ++op_string;
7622 if (is_space_char (*op_string))
7623 ++op_string;
40fb9820 7624 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7625 }
252b5132 7626
47926f60 7627 /* Check if operand is a register. */
4d1bb795 7628 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7629 {
40fb9820
L		 7630 i386_operand_type temp;
7631
24eab124
AM		 7632 /* Check for a segment override by searching for ':' after a
7633 segment register. */
7634 op_string = end_op;
7635 if (is_space_char (*op_string))
7636 ++op_string;
40fb9820
L		 7637 if (*op_string == ':'
7638 && (r->reg_type.bitfield.sreg2
7639 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7640 {
7641 switch (r->reg_num)
7642 {
7643 case 0:
7644 i.seg[i.mem_operands] = &es;
7645 break;
7646 case 1:
7647 i.seg[i.mem_operands] = &cs;
7648 break;
7649 case 2:
7650 i.seg[i.mem_operands] = &ss;
7651 break;
7652 case 3:
7653 i.seg[i.mem_operands] = &ds;
7654 break;
7655 case 4:
7656 i.seg[i.mem_operands] = &fs;
7657 break;
7658 case 5:
7659 i.seg[i.mem_operands] = &gs;
7660 break;
7661 }
252b5132 7662
24eab124 7663 /* Skip the ':' and whitespace. */
252b5132
RH		 7664 ++op_string;
7665 if (is_space_char (*op_string))
24eab124 7666 ++op_string;
252b5132 7667
24eab124
AM		 7668 if (!is_digit_char (*op_string)
7669 && !is_identifier_char (*op_string)
7670 && *op_string != '('
7671 && *op_string != ABSOLUTE_PREFIX)
7672 {
7673 as_bad (_("bad memory operand `%s'"), op_string);
7674 return 0;
7675 }
47926f60 7676 /* Handle case of %es:*foo. */
24eab124
AM		 7677 if (*op_string == ABSOLUTE_PREFIX)
7678 {
7679 ++op_string;
7680 if (is_space_char (*op_string))
7681 ++op_string;
40fb9820 7682 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7683 }
7684 goto do_memory_reference;
7685 }
7686 if (*op_string)
7687 {
d0b47220 7688 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7689 return 0;
7690 }
40fb9820
L		 7691 temp = r->reg_type;
7692 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7693 i.types[this_operand] = operand_type_or (i.types[this_operand],
7694 temp);
7d5e4556 7695 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7696 i.op[this_operand].regs = r;
24eab124
AM		 7697 i.reg_operands++;
7698 }
af6bdddf
AM		 7699 else if (*op_string == REGISTER_PREFIX)
7700 {
7701 as_bad (_("bad register name `%s'"), op_string);
7702 return 0;
7703 }
24eab124 7704 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7705 {
24eab124 7706 ++op_string;
40fb9820 7707 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7708 {
d0b47220 7709 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7710 return 0;
7711 }
7712 if (!i386_immediate (op_string))
7713 return 0;
7714 }
7715 else if (is_digit_char (*op_string)
7716 || is_identifier_char (*op_string)
e5cb08ac 7717 || *op_string == '(')
24eab124 7718 {
47926f60 7719 /* This is a memory reference of some sort. */
af6bdddf 7720 char *base_string;
252b5132 7721
47926f60 7722 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7723 char *displacement_string_start;
7724 char *displacement_string_end;
252b5132 7725
24eab124 7726 do_memory_reference:
24eab124 7727 if ((i.mem_operands == 1
40fb9820 7728 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7729 || i.mem_operands == 2)
7730 {
7731 as_bad (_("too many memory references for `%s'"),
7732 current_templates->start->name);
7733 return 0;
7734 }
252b5132 7735
24eab124
AM		 7736 /* Check for base index form. We detect the base index form by
7737 looking for an ')' at the end of the operand, searching
7738 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7739 after the '('. */
af6bdddf 7740 base_string = op_string + strlen (op_string);
c3332e24 7741
af6bdddf
AM		 7742 --base_string;
7743 if (is_space_char (*base_string))
7744 --base_string;
252b5132 7745
47926f60 7746 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7747 displacement_string_start = op_string;
7748 displacement_string_end = base_string + 1;
252b5132 7749
24eab124
AM		 7750 if (*base_string == ')')
7751 {
af6bdddf 7752 char *temp_string;
24eab124
AM		 7753 unsigned int parens_balanced = 1;
7754 /* We've already checked that the number of left & right ()'s are
47926f60 7755 equal, so this loop will not be infinite. */
24eab124
AM		 7756 do
7757 {
7758 base_string--;
7759 if (*base_string == ')')
7760 parens_balanced++;
7761 if (*base_string == '(')
7762 parens_balanced--;
7763 }
7764 while (parens_balanced);
c3332e24 7765
af6bdddf 7766 temp_string = base_string;
c3332e24 7767
24eab124 7768 /* Skip past '(' and whitespace. */
252b5132
RH		 7769 ++base_string;
7770 if (is_space_char (*base_string))
24eab124 7771 ++base_string;
252b5132 7772
af6bdddf 7773 if (*base_string == ','
4eed87de
AM		 7774 || ((i.base_reg = parse_register (base_string, &end_op))
7775 != NULL))
252b5132 7776 {
af6bdddf 7777 displacement_string_end = temp_string;
252b5132 7778
40fb9820 7779 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7780
af6bdddf 7781 if (i.base_reg)
24eab124 7782 {
24eab124
AM		 7783 base_string = end_op;
7784 if (is_space_char (*base_string))
7785 ++base_string;
af6bdddf
AM		 7786 }
7787
7788 /* There may be an index reg or scale factor here. */
7789 if (*base_string == ',')
7790 {
7791 ++base_string;
7792 if (is_space_char (*base_string))
7793 ++base_string;
7794
4eed87de
AM		 7795 if ((i.index_reg = parse_register (base_string, &end_op))
7796 != NULL)
24eab124 7797 {
af6bdddf 7798 base_string = end_op;
24eab124
AM		 7799 if (is_space_char (*base_string))
7800 ++base_string;
af6bdddf
AM		 7801 if (*base_string == ',')
7802 {
7803 ++base_string;
7804 if (is_space_char (*base_string))
7805 ++base_string;
7806 }
e5cb08ac 7807 else if (*base_string != ')')
af6bdddf 7808 {
4eed87de
AM		 7809 as_bad (_("expecting `,' or `)' "
7810 "after index register in `%s'"),
af6bdddf
AM		 7811 operand_string);
7812 return 0;
7813 }
24eab124 7814 }
af6bdddf 7815 else if (*base_string == REGISTER_PREFIX)
24eab124 7816 {
f76bf5e0
L		 7817 end_op = strchr (base_string, ',');
7818 if (end_op)
7819 *end_op = '\0';
af6bdddf 7820 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7821 return 0;
7822 }
252b5132 7823
47926f60 7824 /* Check for scale factor. */
551c1ca1 7825 if (*base_string != ')')
af6bdddf 7826 {
551c1ca1
AM		 7827 char *end_scale = i386_scale (base_string);
7828
7829 if (!end_scale)
af6bdddf 7830 return 0;
24eab124 7831
551c1ca1 7832 base_string = end_scale;
af6bdddf
AM		 7833 if (is_space_char (*base_string))
7834 ++base_string;
7835 if (*base_string != ')')
7836 {
4eed87de
AM		 7837 as_bad (_("expecting `)' "
7838 "after scale factor in `%s'"),
af6bdddf
AM		 7839 operand_string);
7840 return 0;
7841 }
7842 }
7843 else if (!i.index_reg)
24eab124 7844 {
4eed87de
AM		 7845 as_bad (_("expecting index register or scale factor "
7846 "after `,'; got '%c'"),
af6bdddf 7847 *base_string);
24eab124
AM		 7848 return 0;
7849 }
7850 }
af6bdddf 7851 else if (*base_string != ')')
24eab124 7852 {
4eed87de
AM		 7853 as_bad (_("expecting `,' or `)' "
7854 "after base register in `%s'"),
af6bdddf 7855 operand_string);
24eab124
AM		 7856 return 0;
7857 }
c3332e24 7858 }
af6bdddf 7859 else if (*base_string == REGISTER_PREFIX)
c3332e24 7860 {
f76bf5e0
L		 7861 end_op = strchr (base_string, ',');
7862 if (end_op)
7863 *end_op = '\0';
af6bdddf 7864 as_bad (_("bad register name `%s'"), base_string);
24eab124 7865 return 0;
c3332e24 7866 }
24eab124
AM		 7867 }
7868
7869 /* If there's an expression beginning the operand, parse it,
7870 assuming displacement_string_start and
7871 displacement_string_end are meaningful. */
7872 if (displacement_string_start != displacement_string_end)
7873 {
7874 if (!i386_displacement (displacement_string_start,
7875 displacement_string_end))
7876 return 0;
7877 }
7878
7879 /* Special case for (%dx) while doing input/output op. */
7880 if (i.base_reg
0dfbf9d7
L		 7881 && operand_type_equal (&i.base_reg->reg_type,
7882 &reg16_inoutportreg)
24eab124
AM		 7883 && i.index_reg == 0
7884 && i.log2_scale_factor == 0
7885 && i.seg[i.mem_operands] == 0
40fb9820 7886 && !operand_type_check (i.types[this_operand], disp))
24eab124 7887 {
65da13b5 7888 i.types[this_operand] = inoutportreg;
24eab124
AM		 7889 return 1;
7890 }
7891
eecb386c
AM		 7892 if (i386_index_check (operand_string) == 0)
7893 return 0;
5c07affc 7894 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7895 i.mem_operands++;
7896 }
7897 else
ce8a8b2f
AM		 7898 {
7899 /* It's not a memory operand; argh! */
24eab124
AM		 7900 as_bad (_("invalid char %s beginning operand %d `%s'"),
7901 output_invalid (*op_string),
7902 this_operand + 1,
7903 op_string);
7904 return 0;
7905 }
47926f60 7906 return 1; /* Normal return. */
252b5132
RH		 7907}
7908\f
fa94de6b
RM		 7909/* Calculate the maximum variable size (i.e., excluding fr_fix)
7910 that an rs_machine_dependent frag may reach. */
7911
7912unsigned int
7913i386_frag_max_var (fragS *frag)
7914{
7915 /* The only relaxable frags are for jumps.
7916 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7917 gas_assert (frag->fr_type == rs_machine_dependent);
7918 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
7919}
7920
ee7fcc42
AM		 7921/* md_estimate_size_before_relax()
7922
7923 Called just before relax() for rs_machine_dependent frags. The x86
7924 assembler uses these frags to handle variable size jump
7925 instructions.
7926
7927 Any symbol that is now undefined will not become defined.
7928 Return the correct fr_subtype in the frag.
7929 Return the initial "guess for variable size of frag" to caller.
7930 The guess is actually the growth beyond the fixed part. Whatever
7931 we do to grow the fixed or variable part contributes to our
7932 returned value. */
7933
252b5132 7934int
7016a5d5 7935md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 7936{
252b5132 7937 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7938 check for un-relaxable symbols. On an ELF system, we can't relax
7939 an externally visible symbol, because it may be overridden by a
7940 shared library. */
7941 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7942#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7943 || (IS_ELF
31312f95 7944 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7945 || S_IS_WEAK (fragP->fr_symbol)
7946 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7947 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7948#endif
7949#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7950 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7951 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7952#endif
7953 )
252b5132 7954 {
b98ef147
AM		 7955 /* Symbol is undefined in this segment, or we need to keep a
7956 reloc so that weak symbols can be overridden. */
7957 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7958 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7959 unsigned char *opcode;
7960 int old_fr_fix;
f6af82bd 7961
ee7fcc42 7962 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7963 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7964 else if (size == 2)
f6af82bd
AM		 7965 reloc_type = BFD_RELOC_16_PCREL;
7966 else
7967 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7968
ee7fcc42
AM		 7969 old_fr_fix = fragP->fr_fix;
7970 opcode = (unsigned char *) fragP->fr_opcode;
7971
fddf5b5b 7972 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7973 {
fddf5b5b
AM		 7974 case UNCOND_JUMP:
7975 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7976 opcode[0] = 0xe9;
252b5132 7977 fragP->fr_fix += size;
062cd5e7
AS		 7978 fix_new (fragP, old_fr_fix, size,
7979 fragP->fr_symbol,
7980 fragP->fr_offset, 1,
7981 reloc_type);
252b5132
RH		 7982 break;
7983
fddf5b5b 7984 case COND_JUMP86:
412167cb
AM		 7985 if (size == 2
7986 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7987 {
7988 /* Negate the condition, and branch past an
7989 unconditional jump. */
7990 opcode[0] ^= 1;
7991 opcode[1] = 3;
7992 /* Insert an unconditional jump. */
7993 opcode[2] = 0xe9;
7994 /* We added two extra opcode bytes, and have a two byte
7995 offset. */
7996 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7997 fix_new (fragP, old_fr_fix + 2, 2,
7998 fragP->fr_symbol,
7999 fragP->fr_offset, 1,
8000 reloc_type);
fddf5b5b
AM		 8001 break;
8002 }
8003 /* Fall through. */
8004
8005 case COND_JUMP:
412167cb
AM		 8006 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8007 {
3e02c1cc
AM		 8008 fixS *fixP;
8009
412167cb 8010 fragP->fr_fix += 1;
3e02c1cc
AM		 8011 fixP = fix_new (fragP, old_fr_fix, 1,
8012 fragP->fr_symbol,
8013 fragP->fr_offset, 1,
8014 BFD_RELOC_8_PCREL);
8015 fixP->fx_signed = 1;
412167cb
AM		 8016 break;
8017 }
93c2a809 8018
24eab124 8019 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8020 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8021 opcode[1] = opcode[0] + 0x10;
f6af82bd 8022 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8023 /* We've added an opcode byte. */
8024 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8025 fix_new (fragP, old_fr_fix + 1, size,
8026 fragP->fr_symbol,
8027 fragP->fr_offset, 1,
8028 reloc_type);
252b5132 8029 break;
fddf5b5b
AM		 8030
8031 default:
8032 BAD_CASE (fragP->fr_subtype);
8033 break;
252b5132
RH		 8034 }
8035 frag_wane (fragP);
ee7fcc42 8036 return fragP->fr_fix - old_fr_fix;
252b5132 8037 }
93c2a809 8038
93c2a809
AM		 8039 /* Guess size depending on current relax state. Initially the relax
8040 state will correspond to a short jump and we return 1, because
8041 the variable part of the frag (the branch offset) is one byte
8042 long. However, we can relax a section more than once and in that
8043 case we must either set fr_subtype back to the unrelaxed state,
8044 or return the value for the appropriate branch. */
8045 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8046}
8047
47926f60
KH		 8048/* Called after relax() is finished.
8049
8050 In: Address of frag.
8051 fr_type == rs_machine_dependent.
8052 fr_subtype is what the address relaxed to.
8053
8054 Out: Any fixSs and constants are set up.
8055 Caller will turn frag into a ".space 0". */
8056
252b5132 8057void
7016a5d5
TG		 8058md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8059 fragS *fragP)
252b5132 8060{
29b0f896 8061 unsigned char *opcode;
252b5132 8062 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8063 offsetT target_address;
8064 offsetT opcode_address;
252b5132 8065 unsigned int extension = 0;
847f7ad4 8066 offsetT displacement_from_opcode_start;
252b5132
RH		 8067
8068 opcode = (unsigned char *) fragP->fr_opcode;
8069
47926f60 8070 /* Address we want to reach in file space. */
252b5132 8071 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8072
47926f60 8073 /* Address opcode resides at in file space. */
252b5132
RH		 8074 opcode_address = fragP->fr_address + fragP->fr_fix;
8075
47926f60 8076 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8077 displacement_from_opcode_start = target_address - opcode_address;
8078
fddf5b5b 8079 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8080 {
47926f60
KH		 8081 /* Don't have to change opcode. */
8082 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8083 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8084 }
8085 else
8086 {
8087 if (no_cond_jump_promotion
8088 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8089 as_warn_where (fragP->fr_file, fragP->fr_line,
8090 _("long jump required"));
252b5132 8091
fddf5b5b
AM		 8092 switch (fragP->fr_subtype)
8093 {
8094 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8095 extension = 4; /* 1 opcode + 4 displacement */
8096 opcode[0] = 0xe9;
8097 where_to_put_displacement = &opcode[1];
8098 break;
252b5132 8099
fddf5b5b
AM		 8100 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8101 extension = 2; /* 1 opcode + 2 displacement */
8102 opcode[0] = 0xe9;
8103 where_to_put_displacement = &opcode[1];
8104 break;
252b5132 8105
fddf5b5b
AM		 8106 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8107 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8108 extension = 5; /* 2 opcode + 4 displacement */
8109 opcode[1] = opcode[0] + 0x10;
8110 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8111 where_to_put_displacement = &opcode[2];
8112 break;
252b5132 8113
fddf5b5b
AM		 8114 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8115 extension = 3; /* 2 opcode + 2 displacement */
8116 opcode[1] = opcode[0] + 0x10;
8117 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8118 where_to_put_displacement = &opcode[2];
8119 break;
252b5132 8120
fddf5b5b
AM		 8121 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
8122 extension = 4;
8123 opcode[0] ^= 1;
8124 opcode[1] = 3;
8125 opcode[2] = 0xe9;
8126 where_to_put_displacement = &opcode[3];
8127 break;
8128
8129 default:
8130 BAD_CASE (fragP->fr_subtype);
8131 break;
8132 }
252b5132 8133 }
fddf5b5b 8134
7b81dfbb
AJ		 8135 /* If size if less then four we are sure that the operand fits,
8136 but if it's 4, then it could be that the displacement is larger
8137 then -/+ 2GB. */
8138 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
8139 && object_64bit
8140 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 8141 + ((addressT) 1 << 31))
8142 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 8143 {
8144 as_bad_where (fragP->fr_file, fragP->fr_line,
8145 _("jump target out of range"));
8146 /* Make us emit 0. */
8147 displacement_from_opcode_start = extension;
8148 }
47926f60 8149 /* Now put displacement after opcode. */
252b5132
RH		 8150 md_number_to_chars ((char *) where_to_put_displacement,
8151 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 8152 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 8153 fragP->fr_fix += extension;
8154}
8155\f
7016a5d5 8156/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 8157 by our caller that we have all the info we need to fix it up.
8158
7016a5d5
TG		 8159 Parameter valP is the pointer to the value of the bits.
8160
252b5132
RH		 8161 On the 386, immediates, displacements, and data pointers are all in
8162 the same (little-endian) format, so we don't need to care about which
8163 we are handling. */
8164
94f592af 8165void
7016a5d5 8166md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 8167{
94f592af 8168 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 8169 valueT value = *valP;
252b5132 8170
f86103b7 8171#if !defined (TE_Mach)
93382f6d
AM		 8172 if (fixP->fx_pcrel)
8173 {
8174 switch (fixP->fx_r_type)
8175 {
5865bb77
ILT		 8176 default:
8177 break;
8178
d6ab8113
JB		 8179 case BFD_RELOC_64:
8180 fixP->fx_r_type = BFD_RELOC_64_PCREL;
8181 break;
93382f6d 8182 case BFD_RELOC_32:
ae8887b5 8183 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 8184 fixP->fx_r_type = BFD_RELOC_32_PCREL;
8185 break;
8186 case BFD_RELOC_16:
8187 fixP->fx_r_type = BFD_RELOC_16_PCREL;
8188 break;
8189 case BFD_RELOC_8:
8190 fixP->fx_r_type = BFD_RELOC_8_PCREL;
8191 break;
8192 }
8193 }
252b5132 8194
a161fe53 8195 if (fixP->fx_addsy != NULL
31312f95 8196 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 8197 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 8198 || fixP->fx_r_type == BFD_RELOC_16_PCREL
8199 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
8200 && !use_rela_relocations)
252b5132 8201 {
31312f95
AM		 8202 /* This is a hack. There should be a better way to handle this.
8203 This covers for the fact that bfd_install_relocation will
8204 subtract the current location (for partial_inplace, PC relative
8205 relocations); see more below. */
252b5132 8206#ifndef OBJ_AOUT
718ddfc0 8207 if (IS_ELF
252b5132
RH		 8208#ifdef TE_PE
8209 || OUTPUT_FLAVOR == bfd_target_coff_flavour
8210#endif
8211 )
8212 value += fixP->fx_where + fixP->fx_frag->fr_address;
8213#endif
8214#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8215 if (IS_ELF)
252b5132 8216 {
6539b54b 8217 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 8218
6539b54b 8219 if ((sym_seg == seg
2f66722d 8220 || (symbol_section_p (fixP->fx_addsy)
6539b54b 8221 && sym_seg != absolute_section))
af65af87 8222 && !generic_force_reloc (fixP))
2f66722d
AM		 8223 {
8224 /* Yes, we add the values in twice. This is because
6539b54b
AM		 8225 bfd_install_relocation subtracts them out again. I think
8226 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 8227 it. FIXME. */
8228 value += fixP->fx_where + fixP->fx_frag->fr_address;
8229 }
252b5132
RH		 8230 }
8231#endif
8232#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 8233 /* For some reason, the PE format does not store a
8234 section address offset for a PC relative symbol. */
8235 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 8236 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 8237 value += md_pcrel_from (fixP);
8238#endif
8239 }
fbeb56a4
DK		 8240#if defined (OBJ_COFF) && defined (TE_PE)
8241 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8242 {
8243 value -= S_GET_VALUE (fixP->fx_addsy);
8244 }
8245#endif
252b5132
RH		 8246
8247 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 8248 and we must not disappoint it. */
252b5132 8249#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8250 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 8251 switch (fixP->fx_r_type)
8252 {
8253 case BFD_RELOC_386_PLT32:
3e73aa7c 8254 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 8255 /* Make the jump instruction point to the address of the operand. At
8256 runtime we merely add the offset to the actual PLT entry. */
8257 value = -4;
8258 break;
31312f95 8259
13ae64f3
JJ		 8260 case BFD_RELOC_386_TLS_GD:
8261 case BFD_RELOC_386_TLS_LDM:
13ae64f3 8262 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8263 case BFD_RELOC_386_TLS_IE:
8264 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 8265 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 8266 case BFD_RELOC_X86_64_TLSGD:
8267 case BFD_RELOC_X86_64_TLSLD:
8268 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 8269 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 8270 value = 0; /* Fully resolved at runtime. No addend. */
8271 /* Fallthrough */
8272 case BFD_RELOC_386_TLS_LE:
8273 case BFD_RELOC_386_TLS_LDO_32:
8274 case BFD_RELOC_386_TLS_LE_32:
8275 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8276 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 8277 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 8278 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 8279 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8280 break;
8281
67a4f2b7
AO		 8282 case BFD_RELOC_386_TLS_DESC_CALL:
8283 case BFD_RELOC_X86_64_TLSDESC_CALL:
8284 value = 0; /* Fully resolved at runtime. No addend. */
8285 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8286 fixP->fx_done = 0;
8287 return;
8288
00f7efb6
JJ		 8289 case BFD_RELOC_386_GOT32:
8290 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 8291 value = 0; /* Fully resolved at runtime. No addend. */
8292 break;
47926f60
KH		 8293
8294 case BFD_RELOC_VTABLE_INHERIT:
8295 case BFD_RELOC_VTABLE_ENTRY:
8296 fixP->fx_done = 0;
94f592af 8297 return;
47926f60
KH		 8298
8299 default:
8300 break;
8301 }
8302#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 8303 *valP = value;
f86103b7 8304#endif /* !defined (TE_Mach) */
3e73aa7c 8305
3e73aa7c 8306 /* Are we finished with this relocation now? */
c6682705 8307 if (fixP->fx_addsy == NULL)
3e73aa7c 8308 fixP->fx_done = 1;
fbeb56a4
DK		 8309#if defined (OBJ_COFF) && defined (TE_PE)
8310 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8311 {
8312 fixP->fx_done = 0;
8313 /* Remember value for tc_gen_reloc. */
8314 fixP->fx_addnumber = value;
8315 /* Clear out the frag for now. */
8316 value = 0;
8317 }
8318#endif
3e73aa7c
JH		 8319 else if (use_rela_relocations)
8320 {
8321 fixP->fx_no_overflow = 1;
062cd5e7
AS		 8322 /* Remember value for tc_gen_reloc. */
8323 fixP->fx_addnumber = value;
3e73aa7c
JH		 8324 value = 0;
8325 }
f86103b7 8326
94f592af 8327 md_number_to_chars (p, value, fixP->fx_size);
252b5132 8328}
252b5132 8329\f
252b5132 8330char *
499ac353 8331md_atof (int type, char *litP, int *sizeP)
252b5132 8332{
499ac353
NC		 8333 /* This outputs the LITTLENUMs in REVERSE order;
8334 in accord with the bigendian 386. */
8335 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 8336}
8337\f
2d545b82 8338static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 8339
252b5132 8340static char *
e3bb37b5 8341output_invalid (int c)
252b5132 8342{
3882b010 8343 if (ISPRINT (c))
f9f21a03
L		 8344 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
8345 "'%c'", c);
252b5132 8346 else
f9f21a03 8347 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 8348 "(0x%x)", (unsigned char) c);
252b5132
RH		 8349 return output_invalid_buf;
8350}
8351
af6bdddf 8352/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 8353
8354static const reg_entry *
4d1bb795 8355parse_real_register (char *reg_string, char **end_op)
252b5132 8356{
af6bdddf
AM		 8357 char *s = reg_string;
8358 char *p;
252b5132
RH		 8359 char reg_name_given[MAX_REG_NAME_SIZE + 1];
8360 const reg_entry *r;
8361
8362 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8363 if (*s == REGISTER_PREFIX)
8364 ++s;
8365
8366 if (is_space_char (*s))
8367 ++s;
8368
8369 p = reg_name_given;
af6bdddf 8370 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 8371 {
8372 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 8373 return (const reg_entry *) NULL;
8374 s++;
252b5132
RH		 8375 }
8376
6588847e
DN		 8377 /* For naked regs, make sure that we are not dealing with an identifier.
8378 This prevents confusing an identifier like `eax_var' with register
8379 `eax'. */
8380 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
8381 return (const reg_entry *) NULL;
8382
af6bdddf 8383 *end_op = s;
252b5132
RH		 8384
8385 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
8386
5f47d35b 8387 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 8388 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 8389 {
5f47d35b
AM		 8390 if (is_space_char (*s))
8391 ++s;
8392 if (*s == '(')
8393 {
af6bdddf 8394 ++s;
5f47d35b
AM		 8395 if (is_space_char (*s))
8396 ++s;
8397 if (*s >= '0' && *s <= '7')
8398 {
db557034 8399 int fpr = *s - '0';
af6bdddf 8400 ++s;
5f47d35b
AM		 8401 if (is_space_char (*s))
8402 ++s;
8403 if (*s == ')')
8404 {
8405 *end_op = s + 1;
1e9cc1c2 8406 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 8407 know (r);
8408 return r + fpr;
5f47d35b 8409 }
5f47d35b 8410 }
47926f60 8411 /* We have "%st(" then garbage. */
5f47d35b
AM		 8412 return (const reg_entry *) NULL;
8413 }
8414 }
8415
a60de03c
JB		 8416 if (r == NULL || allow_pseudo_reg)
8417 return r;
8418
0dfbf9d7 8419 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8420 return (const reg_entry *) NULL;
8421
192dc9c6
JB		 8422 if ((r->reg_type.bitfield.reg32
8423 || r->reg_type.bitfield.sreg3
8424 || r->reg_type.bitfield.control
8425 || r->reg_type.bitfield.debug
8426 || r->reg_type.bitfield.test)
8427 && !cpu_arch_flags.bitfield.cpui386)
8428 return (const reg_entry *) NULL;
8429
309d3373
JB		 8430 if (r->reg_type.bitfield.floatreg
8431 && !cpu_arch_flags.bitfield.cpu8087
8432 && !cpu_arch_flags.bitfield.cpu287
8433 && !cpu_arch_flags.bitfield.cpu387)
8434 return (const reg_entry *) NULL;
8435
192dc9c6
JB		 8436 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8437 return (const reg_entry *) NULL;
8438
8439 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8440 return (const reg_entry *) NULL;
8441
40f12533
L		 8442 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8443 return (const reg_entry *) NULL;
8444
db51cc60 8445 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8446 if (!allow_index_reg
db51cc60
L		 8447 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8448 return (const reg_entry *) NULL;
8449
a60de03c
JB		 8450 if (((r->reg_flags & (RegRex64 | RegRex))
8451 || r->reg_type.bitfield.reg64)
40fb9820 8452 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8453 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8454 && flag_code != CODE_64BIT)
20f0a1fc 8455 return (const reg_entry *) NULL;
1ae00879 8456
b7240065
JB		 8457 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8458 return (const reg_entry *) NULL;
8459
252b5132
RH		 8460 return r;
8461}
4d1bb795
JB		 8462
8463/* REG_STRING starts *before* REGISTER_PREFIX. */
8464
8465static const reg_entry *
8466parse_register (char *reg_string, char **end_op)
8467{
8468 const reg_entry *r;
8469
8470 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8471 r = parse_real_register (reg_string, end_op);
8472 else
8473 r = NULL;
8474 if (!r)
8475 {
8476 char *save = input_line_pointer;
8477 char c;
8478 symbolS *symbolP;
8479
8480 input_line_pointer = reg_string;
8481 c = get_symbol_end ();
8482 symbolP = symbol_find (reg_string);
8483 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8484 {
8485 const expressionS *e = symbol_get_value_expression (symbolP);
8486
0398aac5 8487 know (e->X_op == O_register);
4eed87de 8488 know (e->X_add_number >= 0
c3fe08fa 8489 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8490 r = i386_regtab + e->X_add_number;
8491 *end_op = input_line_pointer;
8492 }
8493 *input_line_pointer = c;
8494 input_line_pointer = save;
8495 }
8496 return r;
8497}
8498
8499int
8500i386_parse_name (char *name, expressionS *e, char *nextcharP)
8501{
8502 const reg_entry *r;
8503 char *end = input_line_pointer;
8504
8505 *end = *nextcharP;
8506 r = parse_register (name, &input_line_pointer);
8507 if (r && end <= input_line_pointer)
8508 {
8509 *nextcharP = *input_line_pointer;
8510 *input_line_pointer = 0;
8511 e->X_op = O_register;
8512 e->X_add_number = r - i386_regtab;
8513 return 1;
8514 }
8515 input_line_pointer = end;
8516 *end = 0;
ee86248c 8517 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8518}
8519
8520void
8521md_operand (expressionS *e)
8522{
ee86248c
JB		 8523 char *end;
8524 const reg_entry *r;
4d1bb795 8525
ee86248c
JB		 8526 switch (*input_line_pointer)
8527 {
8528 case REGISTER_PREFIX:
8529 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8530 if (r)
8531 {
8532 e->X_op = O_register;
8533 e->X_add_number = r - i386_regtab;
8534 input_line_pointer = end;
8535 }
ee86248c
JB		 8536 break;
8537
8538 case '[':
9c2799c2 8539 gas_assert (intel_syntax);
ee86248c
JB		 8540 end = input_line_pointer++;
8541 expression (e);
8542 if (*input_line_pointer == ']')
8543 {
8544 ++input_line_pointer;
8545 e->X_op_symbol = make_expr_symbol (e);
8546 e->X_add_symbol = NULL;
8547 e->X_add_number = 0;
8548 e->X_op = O_index;
8549 }
8550 else
8551 {
8552 e->X_op = O_absent;
8553 input_line_pointer = end;
8554 }
8555 break;
4d1bb795
JB		 8556 }
8557}
8558
252b5132 8559\f
4cc782b5 8560#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8561const char *md_shortopts = "kVQ:sqn";
252b5132 8562#else
12b55ccc 8563const char *md_shortopts = "qn";
252b5132 8564#endif
6e0b89ee 8565
3e73aa7c 8566#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8567#define OPTION_64 (OPTION_MD_BASE + 1)
8568#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8569#define OPTION_MARCH (OPTION_MD_BASE + 3)
8570#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8571#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8572#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8573#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8574#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8575#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8576#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8577#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 8578#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8579#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8580#define OPTION_X32 (OPTION_MD_BASE + 14)
b3b91714 8581
99ad8390
NC		 8582struct option md_longopts[] =
8583{
3e73aa7c 8584 {"32", no_argument, NULL, OPTION_32},
321098a5 8585#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8586 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 8587 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8588#endif
8589#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8590 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8591#endif
b3b91714 8592 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8593 {"march", required_argument, NULL, OPTION_MARCH},
8594 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8595 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8596 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8597 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8598 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8599 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8600 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8601 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 8602 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 8603 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8604 {NULL, no_argument, NULL, 0}
8605};
8606size_t md_longopts_size = sizeof (md_longopts);
8607
8608int
9103f4f4 8609md_parse_option (int c, char *arg)
252b5132 8610{
91d6fa6a 8611 unsigned int j;
6305a203 8612 char *arch, *next;
9103f4f4 8613
252b5132
RH		 8614 switch (c)
8615 {
12b55ccc
L		 8616 case 'n':
8617 optimize_align_code = 0;
8618 break;
8619
a38cf1db
AM		 8620 case 'q':
8621 quiet_warnings = 1;
252b5132
RH		 8622 break;
8623
8624#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8625 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8626 should be emitted or not. FIXME: Not implemented. */
8627 case 'Q':
252b5132
RH		 8628 break;
8629
8630 /* -V: SVR4 argument to print version ID. */
8631 case 'V':
8632 print_version_id ();
8633 break;
8634
a38cf1db
AM		 8635 /* -k: Ignore for FreeBSD compatibility. */
8636 case 'k':
252b5132 8637 break;
4cc782b5
ILT		 8638
8639 case 's':
8640 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8641 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8642 break;
99ad8390 8643#endif
321098a5 8644#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8645 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 8646 case OPTION_64:
8647 {
8648 const char **list, **l;
8649
3e73aa7c
JH		 8650 list = bfd_target_list ();
8651 for (l = list; *l != NULL; l++)
8620418b 8652 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8653 || strcmp (*l, "coff-x86-64") == 0
8654 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 8655 || strcmp (*l, "pei-x86-64") == 0
8656 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 8657 {
8658 default_arch = "x86_64";
8659 break;
8660 }
3e73aa7c 8661 if (*l == NULL)
2b5d6a91 8662 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 8663 free (list);
8664 }
8665 break;
8666#endif
252b5132 8667
351f65ca 8668#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8669 case OPTION_X32:
351f65ca
L		 8670 if (IS_ELF)
8671 {
8672 const char **list, **l;
8673
8674 list = bfd_target_list ();
8675 for (l = list; *l != NULL; l++)
8676 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8677 {
8678 default_arch = "x86_64:32";
8679 break;
8680 }
8681 if (*l == NULL)
2b5d6a91 8682 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 8683 free (list);
8684 }
8685 else
8686 as_fatal (_("32bit x86_64 is only supported for ELF"));
8687 break;
8688#endif
8689
6e0b89ee
AM		 8690 case OPTION_32:
8691 default_arch = "i386";
8692 break;
8693
b3b91714
AM		 8694 case OPTION_DIVIDE:
8695#ifdef SVR4_COMMENT_CHARS
8696 {
8697 char *n, *t;
8698 const char *s;
8699
8700 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8701 t = n;
8702 for (s = i386_comment_chars; *s != '\0'; s++)
8703 if (*s != '/')
8704 *t++ = *s;
8705 *t = '\0';
8706 i386_comment_chars = n;
8707 }
8708#endif
8709 break;
8710
9103f4f4 8711 case OPTION_MARCH:
6305a203
L		 8712 arch = xstrdup (arg);
8713 do
9103f4f4 8714 {
6305a203 8715 if (*arch == '.')
2b5d6a91 8716 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8717 next = strchr (arch, '+');
8718 if (next)
8719 *next++ = '\0';
91d6fa6a 8720 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8721 {
91d6fa6a 8722 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8723 {
6305a203 8724 /* Processor. */
1ded5609
JB		 8725 if (! cpu_arch[j].flags.bitfield.cpui386)
8726 continue;
8727
91d6fa6a 8728 cpu_arch_name = cpu_arch[j].name;
6305a203 8729 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8730 cpu_arch_flags = cpu_arch[j].flags;
8731 cpu_arch_isa = cpu_arch[j].type;
8732 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8733 if (!cpu_arch_tune_set)
8734 {
8735 cpu_arch_tune = cpu_arch_isa;
8736 cpu_arch_tune_flags = cpu_arch_isa_flags;
8737 }
8738 break;
8739 }
91d6fa6a
NC		 8740 else if (*cpu_arch [j].name == '.'
8741 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8742 {
8743 /* ISA entension. */
8744 i386_cpu_flags flags;
309d3373 8745
49021df2 8746 if (!cpu_arch[j].negated)
309d3373 8747 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8748 cpu_arch[j].flags);
309d3373
JB		 8749 else
8750 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8751 cpu_arch[j].flags);
0dfbf9d7 8752 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8753 {
8754 if (cpu_sub_arch_name)
8755 {
8756 char *name = cpu_sub_arch_name;
8757 cpu_sub_arch_name = concat (name,
91d6fa6a 8758 cpu_arch[j].name,
1bf57e9f 8759 (const char *) NULL);
6305a203
L		 8760 free (name);
8761 }
8762 else
91d6fa6a 8763 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8764 cpu_arch_flags = flags;
a586129e 8765 cpu_arch_isa_flags = flags;
6305a203
L		 8766 }
8767 break;
ccc9c027 8768 }
9103f4f4 8769 }
6305a203 8770
91d6fa6a 8771 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8772 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8773
8774 arch = next;
9103f4f4 8775 }
6305a203 8776 while (next != NULL );
9103f4f4
L		 8777 break;
8778
8779 case OPTION_MTUNE:
8780 if (*arg == '.')
2b5d6a91 8781 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 8782 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8783 {
91d6fa6a 8784 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8785 {
ccc9c027 8786 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8787 cpu_arch_tune = cpu_arch [j].type;
8788 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8789 break;
8790 }
8791 }
91d6fa6a 8792 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8793 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 8794 break;
8795
1efbbeb4
L		 8796 case OPTION_MMNEMONIC:
8797 if (strcasecmp (arg, "att") == 0)
8798 intel_mnemonic = 0;
8799 else if (strcasecmp (arg, "intel") == 0)
8800 intel_mnemonic = 1;
8801 else
2b5d6a91 8802 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 8803 break;
8804
8805 case OPTION_MSYNTAX:
8806 if (strcasecmp (arg, "att") == 0)
8807 intel_syntax = 0;
8808 else if (strcasecmp (arg, "intel") == 0)
8809 intel_syntax = 1;
8810 else
2b5d6a91 8811 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 8812 break;
8813
8814 case OPTION_MINDEX_REG:
8815 allow_index_reg = 1;
8816 break;
8817
8818 case OPTION_MNAKED_REG:
8819 allow_naked_reg = 1;
8820 break;
8821
8822 case OPTION_MOLD_GCC:
8823 old_gcc = 1;
1efbbeb4
L		 8824 break;
8825
c0f3af97
L		 8826 case OPTION_MSSE2AVX:
8827 sse2avx = 1;
8828 break;
8829
daf50ae7
L		 8830 case OPTION_MSSE_CHECK:
8831 if (strcasecmp (arg, "error") == 0)
7bab8ab5 8832 sse_check = check_error;
daf50ae7 8833 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 8834 sse_check = check_warning;
daf50ae7 8835 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 8836 sse_check = check_none;
daf50ae7 8837 else
2b5d6a91 8838 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 8839 break;
8840
7bab8ab5
JB		 8841 case OPTION_MOPERAND_CHECK:
8842 if (strcasecmp (arg, "error") == 0)
8843 operand_check = check_error;
8844 else if (strcasecmp (arg, "warning") == 0)
8845 operand_check = check_warning;
8846 else if (strcasecmp (arg, "none") == 0)
8847 operand_check = check_none;
8848 else
8849 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
8850 break;
8851
539f890d
L		 8852 case OPTION_MAVXSCALAR:
8853 if (strcasecmp (arg, "128") == 0)
8854 avxscalar = vex128;
8855 else if (strcasecmp (arg, "256") == 0)
8856 avxscalar = vex256;
8857 else
2b5d6a91 8858 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 8859 break;
8860
252b5132
RH		 8861 default:
8862 return 0;
8863 }
8864 return 1;
8865}
8866
8a2c8fef
L		 8867#define MESSAGE_TEMPLATE \
8868" "
8869
8870static void
1ded5609 8871show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8872{
8873 static char message[] = MESSAGE_TEMPLATE;
8874 char *start = message + 27;
8875 char *p;
8876 int size = sizeof (MESSAGE_TEMPLATE);
8877 int left;
8878 const char *name;
8879 int len;
8880 unsigned int j;
8881
8882 p = start;
8883 left = size - (start - message);
8884 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8885 {
8886 /* Should it be skipped? */
8887 if (cpu_arch [j].skip)
8888 continue;
8889
8890 name = cpu_arch [j].name;
8891 len = cpu_arch [j].len;
8892 if (*name == '.')
8893 {
8894 /* It is an extension. Skip if we aren't asked to show it. */
8895 if (ext)
8896 {
8897 name++;
8898 len--;
8899 }
8900 else
8901 continue;
8902 }
8903 else if (ext)
8904 {
8905 /* It is an processor. Skip if we show only extension. */
8906 continue;
8907 }
1ded5609
JB		 8908 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8909 {
8910 /* It is an impossible processor - skip. */
8911 continue;
8912 }
8a2c8fef
L		 8913
8914 /* Reserve 2 spaces for ", " or ",\0" */
8915 left -= len + 2;
8916
8917 /* Check if there is any room. */
8918 if (left >= 0)
8919 {
8920 if (p != start)
8921 {
8922 *p++ = ',';
8923 *p++ = ' ';
8924 }
8925 p = mempcpy (p, name, len);
8926 }
8927 else
8928 {
8929 /* Output the current message now and start a new one. */
8930 *p++ = ',';
8931 *p = '\0';
8932 fprintf (stream, "%s\n", message);
8933 p = start;
8934 left = size - (start - message) - len - 2;
8d63c93e 8935
8a2c8fef
L		 8936 gas_assert (left >= 0);
8937
8938 p = mempcpy (p, name, len);
8939 }
8940 }
8941
8942 *p = '\0';
8943 fprintf (stream, "%s\n", message);
8944}
8945
252b5132 8946void
8a2c8fef 8947md_show_usage (FILE *stream)
252b5132 8948{
4cc782b5
ILT		 8949#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8950 fprintf (stream, _("\
a38cf1db
AM		 8951 -Q ignored\n\
8952 -V print assembler version number\n\
b3b91714
AM		 8953 -k ignored\n"));
8954#endif
8955 fprintf (stream, _("\
12b55ccc 8956 -n Do not optimize code alignment\n\
b3b91714
AM		 8957 -q quieten some warnings\n"));
8958#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8959 fprintf (stream, _("\
a38cf1db 8960 -s ignored\n"));
b3b91714 8961#endif
321098a5
L		 8962#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8963 || defined (TE_PE) || defined (TE_PEP))
751d281c 8964 fprintf (stream, _("\
570561f7 8965 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8966#endif
b3b91714
AM		 8967#ifdef SVR4_COMMENT_CHARS
8968 fprintf (stream, _("\
8969 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8970#else
8971 fprintf (stream, _("\
b3b91714 8972 --divide ignored\n"));
4cc782b5 8973#endif
9103f4f4 8974 fprintf (stream, _("\
6305a203 8975 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8976 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8977 show_arch (stream, 0, 1);
8a2c8fef
L		 8978 fprintf (stream, _("\
8979 EXTENSION is combination of:\n"));
1ded5609 8980 show_arch (stream, 1, 0);
6305a203 8981 fprintf (stream, _("\
8a2c8fef 8982 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8983 show_arch (stream, 0, 0);
ba104c83 8984 fprintf (stream, _("\
c0f3af97
L		 8985 -msse2avx encode SSE instructions with VEX prefix\n"));
8986 fprintf (stream, _("\
daf50ae7
L		 8987 -msse-check=[none|error|warning]\n\
8988 check SSE instructions\n"));
8989 fprintf (stream, _("\
7bab8ab5
JB		 8990 -moperand-check=[none|error|warning]\n\
8991 check operand combinations for validity\n"));
8992 fprintf (stream, _("\
539f890d
L		 8993 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8994 length\n"));
8995 fprintf (stream, _("\
ba104c83
L		 8996 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8997 fprintf (stream, _("\
8998 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8999 fprintf (stream, _("\
9000 -mindex-reg support pseudo index registers\n"));
9001 fprintf (stream, _("\
9002 -mnaked-reg don't require `%%' prefix for registers\n"));
9003 fprintf (stream, _("\
9004 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 9005}
9006
3e73aa7c 9007#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9008 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9009 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9010
9011/* Pick the target format to use. */
9012
47926f60 9013const char *
e3bb37b5 9014i386_target_format (void)
252b5132 9015{
351f65ca
L		 9016 if (!strncmp (default_arch, "x86_64", 6))
9017 {
9018 update_code_flag (CODE_64BIT, 1);
9019 if (default_arch[6] == '\0')
7f56bc95 9020 x86_elf_abi = X86_64_ABI;
351f65ca 9021 else
7f56bc95 9022 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9023 }
3e73aa7c 9024 else if (!strcmp (default_arch, "i386"))
78f12dd3 9025 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9026 else
2b5d6a91 9027 as_fatal (_("unknown architecture"));
89507696
JB		 9028
9029 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9030 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9031 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9032 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9033
252b5132
RH		 9034 switch (OUTPUT_FLAVOR)
9035 {
9384f2ff 9036#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 9037 case bfd_target_aout_flavour:
47926f60 9038 return AOUT_TARGET_FORMAT;
4c63da97 9039#endif
9384f2ff
AM		 9040#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9041# if defined (TE_PE) || defined (TE_PEP)
9042 case bfd_target_coff_flavour:
9043 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9044# elif defined (TE_GO32)
0561d57c
JK		 9045 case bfd_target_coff_flavour:
9046 return "coff-go32";
9384f2ff 9047# else
252b5132
RH		 9048 case bfd_target_coff_flavour:
9049 return "coff-i386";
9384f2ff 9050# endif
4c63da97 9051#endif
3e73aa7c 9052#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 9053 case bfd_target_elf_flavour:
3e73aa7c 9054 {
351f65ca
L		 9055 const char *format;
9056
9057 switch (x86_elf_abi)
4fa24527 9058 {
351f65ca
L		 9059 default:
9060 format = ELF_TARGET_FORMAT;
9061 break;
7f56bc95 9062 case X86_64_ABI:
351f65ca 9063 use_rela_relocations = 1;
4fa24527 9064 object_64bit = 1;
351f65ca
L		 9065 format = ELF_TARGET_FORMAT64;
9066 break;
7f56bc95 9067 case X86_64_X32_ABI:
4fa24527 9068 use_rela_relocations = 1;
351f65ca 9069 object_64bit = 1;
862be3fb 9070 disallow_64bit_reloc = 1;
351f65ca
L		 9071 format = ELF_TARGET_FORMAT32;
9072 break;
4fa24527 9073 }
3632d14b 9074 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 9075 {
7f56bc95 9076 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 9077 as_fatal (_("Intel L1OM is 64bit only"));
9078 return ELF_TARGET_L1OM_FORMAT;
9079 }
7a9068fe
L		 9080 if (cpu_arch_isa == PROCESSOR_K1OM)
9081 {
9082 if (x86_elf_abi != X86_64_ABI)
9083 as_fatal (_("Intel K1OM is 64bit only"));
9084 return ELF_TARGET_K1OM_FORMAT;
9085 }
8a9036a4 9086 else
351f65ca 9087 return format;
3e73aa7c 9088 }
e57f8c65
TG		 9089#endif
9090#if defined (OBJ_MACH_O)
9091 case bfd_target_mach_o_flavour:
d382c579
TG		 9092 if (flag_code == CODE_64BIT)
9093 {
9094 use_rela_relocations = 1;
9095 object_64bit = 1;
9096 return "mach-o-x86-64";
9097 }
9098 else
9099 return "mach-o-i386";
4c63da97 9100#endif
252b5132
RH		 9101 default:
9102 abort ();
9103 return NULL;
9104 }
9105}
9106
47926f60 9107#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 9108
9109#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 9110void
9111i386_elf_emit_arch_note (void)
a847613f 9112{
718ddfc0 9113 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 9114 {
9115 char *p;
9116 asection *seg = now_seg;
9117 subsegT subseg = now_subseg;
9118 Elf_Internal_Note i_note;
9119 Elf_External_Note e_note;
9120 asection *note_secp;
9121 int len;
9122
9123 /* Create the .note section. */
9124 note_secp = subseg_new (".note", 0);
9125 bfd_set_section_flags (stdoutput,
9126 note_secp,
9127 SEC_HAS_CONTENTS | SEC_READONLY);
9128
9129 /* Process the arch string. */
9130 len = strlen (cpu_arch_name);
9131
9132 i_note.namesz = len + 1;
9133 i_note.descsz = 0;
9134 i_note.type = NT_ARCH;
9135 p = frag_more (sizeof (e_note.namesz));
9136 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
9137 p = frag_more (sizeof (e_note.descsz));
9138 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
9139 p = frag_more (sizeof (e_note.type));
9140 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
9141 p = frag_more (len + 1);
9142 strcpy (p, cpu_arch_name);
9143
9144 frag_align (2, 0, 0);
9145
9146 subseg_set (seg, subseg);
9147 }
9148}
9149#endif
252b5132 9150\f
252b5132 9151symbolS *
7016a5d5 9152md_undefined_symbol (char *name)
252b5132 9153{
18dc2407
ILT		 9154 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
9155 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
9156 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
9157 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 9158 {
9159 if (!GOT_symbol)
9160 {
9161 if (symbol_find (name))
9162 as_bad (_("GOT already in symbol table"));
9163 GOT_symbol = symbol_new (name, undefined_section,
9164 (valueT) 0, &zero_address_frag);
9165 };
9166 return GOT_symbol;
9167 }
252b5132
RH		 9168 return 0;
9169}
9170
9171/* Round up a section size to the appropriate boundary. */
47926f60 9172
252b5132 9173valueT
7016a5d5 9174md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 9175{
4c63da97
AM		 9176#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9177 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
9178 {
9179 /* For a.out, force the section size to be aligned. If we don't do
9180 this, BFD will align it for us, but it will not write out the
9181 final bytes of the section. This may be a bug in BFD, but it is
9182 easier to fix it here since that is how the other a.out targets
9183 work. */
9184 int align;
9185
9186 align = bfd_get_section_alignment (stdoutput, segment);
9187 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
9188 }
252b5132
RH		 9189#endif
9190
9191 return size;
9192}
9193
9194/* On the i386, PC-relative offsets are relative to the start of the
9195 next instruction. That is, the address of the offset, plus its
9196 size, since the offset is always the last part of the insn. */
9197
9198long
e3bb37b5 9199md_pcrel_from (fixS *fixP)
252b5132
RH		 9200{
9201 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
9202}
9203
9204#ifndef I386COFF
9205
9206static void
e3bb37b5 9207s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 9208{
29b0f896 9209 int temp;
252b5132 9210
8a75718c
JB		 9211#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9212 if (IS_ELF)
9213 obj_elf_section_change_hook ();
9214#endif
252b5132
RH		 9215 temp = get_absolute_expression ();
9216 subseg_set (bss_section, (subsegT) temp);
9217 demand_empty_rest_of_line ();
9218}
9219
9220#endif
9221
252b5132 9222void
e3bb37b5 9223i386_validate_fix (fixS *fixp)
252b5132
RH		 9224{
9225 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
9226 {
23df1078
JH		 9227 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
9228 {
4fa24527 9229 if (!object_64bit)
23df1078
JH		 9230 abort ();
9231 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
9232 }
9233 else
9234 {
4fa24527 9235 if (!object_64bit)
d6ab8113
JB		 9236 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
9237 else
9238 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 9239 }
252b5132
RH		 9240 fixp->fx_subsy = 0;
9241 }
9242}
9243
252b5132 9244arelent *
7016a5d5 9245tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 9246{
9247 arelent *rel;
9248 bfd_reloc_code_real_type code;
9249
9250 switch (fixp->fx_r_type)
9251 {
8ce3d284 9252#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 9253 case BFD_RELOC_SIZE32:
9254 case BFD_RELOC_SIZE64:
9255 if (S_IS_DEFINED (fixp->fx_addsy)
9256 && !S_IS_EXTERNAL (fixp->fx_addsy))
9257 {
9258 /* Resolve size relocation against local symbol to size of
9259 the symbol plus addend. */
9260 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
9261 if (fixp->fx_r_type == BFD_RELOC_SIZE32
9262 && !fits_in_unsigned_long (value))
9263 as_bad_where (fixp->fx_file, fixp->fx_line,
9264 _("symbol size computation overflow"));
9265 fixp->fx_addsy = NULL;
9266 fixp->fx_subsy = NULL;
9267 md_apply_fix (fixp, (valueT *) &value, NULL);
9268 return NULL;
9269 }
8ce3d284 9270#endif
8fd4256d 9271
3e73aa7c
JH		 9272 case BFD_RELOC_X86_64_PLT32:
9273 case BFD_RELOC_X86_64_GOT32:
9274 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 9275 case BFD_RELOC_386_PLT32:
9276 case BFD_RELOC_386_GOT32:
9277 case BFD_RELOC_386_GOTOFF:
9278 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 9279 case BFD_RELOC_386_TLS_GD:
9280 case BFD_RELOC_386_TLS_LDM:
9281 case BFD_RELOC_386_TLS_LDO_32:
9282 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9283 case BFD_RELOC_386_TLS_IE:
9284 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 9285 case BFD_RELOC_386_TLS_LE_32:
9286 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 9287 case BFD_RELOC_386_TLS_GOTDESC:
9288 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 9289 case BFD_RELOC_X86_64_TLSGD:
9290 case BFD_RELOC_X86_64_TLSLD:
9291 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9292 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 9293 case BFD_RELOC_X86_64_GOTTPOFF:
9294 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 9295 case BFD_RELOC_X86_64_TPOFF64:
9296 case BFD_RELOC_X86_64_GOTOFF64:
9297 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 9298 case BFD_RELOC_X86_64_GOT64:
9299 case BFD_RELOC_X86_64_GOTPCREL64:
9300 case BFD_RELOC_X86_64_GOTPC64:
9301 case BFD_RELOC_X86_64_GOTPLT64:
9302 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 9303 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9304 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 9305 case BFD_RELOC_RVA:
9306 case BFD_RELOC_VTABLE_ENTRY:
9307 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 9308#ifdef TE_PE
9309 case BFD_RELOC_32_SECREL:
9310#endif
252b5132
RH		 9311 code = fixp->fx_r_type;
9312 break;
dbbaec26
L		 9313 case BFD_RELOC_X86_64_32S:
9314 if (!fixp->fx_pcrel)
9315 {
9316 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9317 code = fixp->fx_r_type;
9318 break;
9319 }
252b5132 9320 default:
93382f6d 9321 if (fixp->fx_pcrel)
252b5132 9322 {
93382f6d
AM		 9323 switch (fixp->fx_size)
9324 {
9325 default:
b091f402
AM		 9326 as_bad_where (fixp->fx_file, fixp->fx_line,
9327 _("can not do %d byte pc-relative relocation"),
9328 fixp->fx_size);
93382f6d
AM		 9329 code = BFD_RELOC_32_PCREL;
9330 break;
9331 case 1: code = BFD_RELOC_8_PCREL; break;
9332 case 2: code = BFD_RELOC_16_PCREL; break;
9333 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 9334#ifdef BFD64
9335 case 8: code = BFD_RELOC_64_PCREL; break;
9336#endif
93382f6d
AM		 9337 }
9338 }
9339 else
9340 {
9341 switch (fixp->fx_size)
9342 {
9343 default:
b091f402
AM		 9344 as_bad_where (fixp->fx_file, fixp->fx_line,
9345 _("can not do %d byte relocation"),
9346 fixp->fx_size);
93382f6d
AM		 9347 code = BFD_RELOC_32;
9348 break;
9349 case 1: code = BFD_RELOC_8; break;
9350 case 2: code = BFD_RELOC_16; break;
9351 case 4: code = BFD_RELOC_32; break;
937149dd 9352#ifdef BFD64
3e73aa7c 9353 case 8: code = BFD_RELOC_64; break;
937149dd 9354#endif
93382f6d 9355 }
252b5132
RH		 9356 }
9357 break;
9358 }
252b5132 9359
d182319b
JB		 9360 if ((code == BFD_RELOC_32
9361 || code == BFD_RELOC_32_PCREL
9362 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 9363 && GOT_symbol
9364 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 9365 {
4fa24527 9366 if (!object_64bit)
d6ab8113
JB		 9367 code = BFD_RELOC_386_GOTPC;
9368 else
9369 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 9370 }
7b81dfbb
AJ		 9371 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
9372 && GOT_symbol
9373 && fixp->fx_addsy == GOT_symbol)
9374 {
9375 code = BFD_RELOC_X86_64_GOTPC64;
9376 }
252b5132
RH		 9377
9378 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 9379 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9380 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 9381
9382 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 9383
3e73aa7c
JH		 9384 if (!use_rela_relocations)
9385 {
9386 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9387 vtable entry to be used in the relocation's section offset. */
9388 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
9389 rel->address = fixp->fx_offset;
fbeb56a4
DK		 9390#if defined (OBJ_COFF) && defined (TE_PE)
9391 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
9392 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
9393 else
9394#endif
c6682705 9395 rel->addend = 0;
3e73aa7c
JH		 9396 }
9397 /* Use the rela in 64bit mode. */
252b5132 9398 else
3e73aa7c 9399 {
862be3fb
L		 9400 if (disallow_64bit_reloc)
9401 switch (code)
9402 {
862be3fb
L		 9403 case BFD_RELOC_X86_64_DTPOFF64:
9404 case BFD_RELOC_X86_64_TPOFF64:
9405 case BFD_RELOC_64_PCREL:
9406 case BFD_RELOC_X86_64_GOTOFF64:
9407 case BFD_RELOC_X86_64_GOT64:
9408 case BFD_RELOC_X86_64_GOTPCREL64:
9409 case BFD_RELOC_X86_64_GOTPC64:
9410 case BFD_RELOC_X86_64_GOTPLT64:
9411 case BFD_RELOC_X86_64_PLTOFF64:
9412 as_bad_where (fixp->fx_file, fixp->fx_line,
9413 _("cannot represent relocation type %s in x32 mode"),
9414 bfd_get_reloc_code_name (code));
9415 break;
9416 default:
9417 break;
9418 }
9419
062cd5e7
AS		 9420 if (!fixp->fx_pcrel)
9421 rel->addend = fixp->fx_offset;
9422 else
9423 switch (code)
9424 {
9425 case BFD_RELOC_X86_64_PLT32:
9426 case BFD_RELOC_X86_64_GOT32:
9427 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 9428 case BFD_RELOC_X86_64_TLSGD:
9429 case BFD_RELOC_X86_64_TLSLD:
9430 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 9431 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9432 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 9433 rel->addend = fixp->fx_offset - fixp->fx_size;
9434 break;
9435 default:
9436 rel->addend = (section->vma
9437 - fixp->fx_size
9438 + fixp->fx_addnumber
9439 + md_pcrel_from (fixp));
9440 break;
9441 }
3e73aa7c
JH		 9442 }
9443
252b5132
RH		 9444 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
9445 if (rel->howto == NULL)
9446 {
9447 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 9448 _("cannot represent relocation type %s"),
252b5132
RH		 9449 bfd_get_reloc_code_name (code));
9450 /* Set howto to a garbage value so that we can keep going. */
9451 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 9452 gas_assert (rel->howto != NULL);
252b5132
RH		 9453 }
9454
9455 return rel;
9456}
9457
ee86248c 9458#include "tc-i386-intel.c"
54cfded0 9459
a60de03c
JB		 9460void
9461tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9462{
a60de03c
JB		 9463 int saved_naked_reg;
9464 char saved_register_dot;
54cfded0 9465
a60de03c
JB		 9466 saved_naked_reg = allow_naked_reg;
9467 allow_naked_reg = 1;
9468 saved_register_dot = register_chars['.'];
9469 register_chars['.'] = '.';
9470 allow_pseudo_reg = 1;
9471 expression_and_evaluate (exp);
9472 allow_pseudo_reg = 0;
9473 register_chars['.'] = saved_register_dot;
9474 allow_naked_reg = saved_naked_reg;
9475
e96d56a1 9476 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9477 {
a60de03c
JB		 9478 if ((addressT) exp->X_add_number < i386_regtab_size)
9479 {
9480 exp->X_op = O_constant;
9481 exp->X_add_number = i386_regtab[exp->X_add_number]
9482 .dw2_regnum[flag_code >> 1];
9483 }
9484 else
9485 exp->X_op = O_illegal;
54cfded0 9486 }
54cfded0
AM		 9487}
9488
9489void
9490tc_x86_frame_initial_instructions (void)
9491{
a60de03c
JB		 9492 static unsigned int sp_regno[2];
9493
9494 if (!sp_regno[flag_code >> 1])
9495 {
9496 char *saved_input = input_line_pointer;
9497 char sp[][4] = {"esp", "rsp"};
9498 expressionS exp;
a4447b93 9499
a60de03c
JB		 9500 input_line_pointer = sp[flag_code >> 1];
9501 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9502 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9503 sp_regno[flag_code >> 1] = exp.X_add_number;
9504 input_line_pointer = saved_input;
9505 }
a4447b93 9506
61ff971f
L		 9507 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9508 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9509}
d2b2c203 9510
d7921315
L		 9511int
9512x86_dwarf2_addr_size (void)
9513{
9514#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9515 if (x86_elf_abi == X86_64_X32_ABI)
9516 return 4;
9517#endif
9518 return bfd_arch_bits_per_address (stdoutput) / 8;
9519}
9520
d2b2c203
DJ		 9521int
9522i386_elf_section_type (const char *str, size_t len)
9523{
9524 if (flag_code == CODE_64BIT
9525 && len == sizeof ("unwind") - 1
9526 && strncmp (str, "unwind", 6) == 0)
9527 return SHT_X86_64_UNWIND;
9528
9529 return -1;
9530}
bb41ade5 9531
ad5fec3b
EB		 9532#ifdef TE_SOLARIS
9533void
9534i386_solaris_fix_up_eh_frame (segT sec)
9535{
9536 if (flag_code == CODE_64BIT)
9537 elf_section_type (sec) = SHT_X86_64_UNWIND;
9538}
9539#endif
9540
bb41ade5
AM		 9541#ifdef TE_PE
9542void
9543tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9544{
91d6fa6a 9545 expressionS exp;
bb41ade5 9546
91d6fa6a
NC		 9547 exp.X_op = O_secrel;
9548 exp.X_add_symbol = symbol;
9549 exp.X_add_number = 0;
9550 emit_expr (&exp, size);
bb41ade5
AM		 9551}
9552#endif
3b22753a
L		 9553
9554#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9555/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9556
01e1a5bc 9557bfd_vma
3b22753a
L		 9558x86_64_section_letter (int letter, char **ptr_msg)
9559{
9560 if (flag_code == CODE_64BIT)
9561 {
9562 if (letter == 'l')
9563 return SHF_X86_64_LARGE;
9564
8f3bae45 9565 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9566 }
3b22753a 9567 else
8f3bae45 9568 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9569 return -1;
9570}
9571
01e1a5bc 9572bfd_vma
3b22753a
L		 9573x86_64_section_word (char *str, size_t len)
9574{
8620418b 9575 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9576 return SHF_X86_64_LARGE;
9577
9578 return -1;
9579}
9580
9581static void
9582handle_large_common (int small ATTRIBUTE_UNUSED)
9583{
9584 if (flag_code != CODE_64BIT)
9585 {
9586 s_comm_internal (0, elf_common_parse);
9587 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9588 }
9589 else
9590 {
9591 static segT lbss_section;
9592 asection *saved_com_section_ptr = elf_com_section_ptr;
9593 asection *saved_bss_section = bss_section;
9594
9595 if (lbss_section == NULL)
9596 {
9597 flagword applicable;
9598 segT seg = now_seg;
9599 subsegT subseg = now_subseg;
9600
9601 /* The .lbss section is for local .largecomm symbols. */
9602 lbss_section = subseg_new (".lbss", 0);
9603 applicable = bfd_applicable_section_flags (stdoutput);
9604 bfd_set_section_flags (stdoutput, lbss_section,
9605 applicable & SEC_ALLOC);
9606 seg_info (lbss_section)->bss = 1;
9607
9608 subseg_set (seg, subseg);
9609 }
9610
9611 elf_com_section_ptr = &_bfd_elf_large_com_section;
9612 bss_section = lbss_section;
9613
9614 s_comm_internal (0, elf_common_parse);
9615
9616 elf_com_section_ptr = saved_com_section_ptr;
9617 bss_section = saved_bss_section;
9618 }
9619}
9620#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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