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[PATCH, COMMITTED] [AArch64] Replace the :got_prel19: address modifier with :got:
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579
TG		 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
4 2012
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d 68#define REP_PREFIX 4
42164a71 69#define HLE_PREFIX REP_PREFIX
c32fa91d
L		 70#define LOCK_PREFIX 5
71#define REX_PREFIX 6 /* must come last. */
72#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 73
74/* we define the syntax here (modulo base,index,scale syntax) */
75#define REGISTER_PREFIX '%'
76#define IMMEDIATE_PREFIX '$'
77#define ABSOLUTE_PREFIX '*'
78
79/* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81#define WORD_MNEM_SUFFIX 'w'
82#define BYTE_MNEM_SUFFIX 'b'
83#define SHORT_MNEM_SUFFIX 's'
84#define LONG_MNEM_SUFFIX 'l'
85#define QWORD_MNEM_SUFFIX 'q'
86#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 87#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 88/* Intel Syntax. Use a non-ascii letter since since it never appears
89 in instructions. */
90#define LONG_DOUBLE_MNEM_SUFFIX '\1'
91
92#define END_OF_INSN '\0'
93
94/*
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
99 END.
100 */
101typedef struct
102{
d3ce72d0
NC		 103 const insn_template *start;
104 const insn_template *end;
6305a203
L		 105}
106templates;
107
108/* 386 operand encoding bytes: see 386 book for details of this. */
109typedef struct
110{
111 unsigned int regmem; /* codes register or memory operand */
112 unsigned int reg; /* codes register operand (or extended opcode) */
113 unsigned int mode; /* how to interpret regmem & reg */
114}
115modrm_byte;
116
117/* x86-64 extension prefix. */
118typedef int rex_byte;
119
6305a203
L		 120/* 386 opcode byte to code indirect addressing. */
121typedef struct
122{
123 unsigned base;
124 unsigned index;
125 unsigned scale;
126}
127sib_byte;
128
6305a203
L		 129/* x86 arch names, types and features */
130typedef struct
131{
132 const char *name; /* arch name */
8a2c8fef 133 unsigned int len; /* arch string length */
6305a203
L		 134 enum processor_type type; /* arch type */
135 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 136 unsigned int skip; /* show_arch should skip this. */
22109423 137 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 138}
139arch_entry;
140
78f12dd3 141static void update_code_flag (int, int);
e3bb37b5
L		 142static void set_code_flag (int);
143static void set_16bit_gcc_code_flag (int);
144static void set_intel_syntax (int);
1efbbeb4 145static void set_intel_mnemonic (int);
db51cc60 146static void set_allow_index_reg (int);
7bab8ab5 147static void set_check (int);
e3bb37b5 148static void set_cpu_arch (int);
6482c264 149#ifdef TE_PE
e3bb37b5 150static void pe_directive_secrel (int);
6482c264 151#endif
e3bb37b5
L		 152static void signed_cons (int);
153static char *output_invalid (int c);
ee86248c
JB		 154static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
155 const char *);
156static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
157 const char *);
a7619375 158static int i386_att_operand (char *);
e3bb37b5 159static int i386_intel_operand (char *, int);
ee86248c
JB		 160static int i386_intel_simplify (expressionS *);
161static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 162static const reg_entry *parse_register (char *, char **);
163static char *parse_insn (char *, char *);
164static char *parse_operands (char *, const char *);
165static void swap_operands (void);
4d456e3d 166static void swap_2_operands (int, int);
e3bb37b5
L		 167static void optimize_imm (void);
168static void optimize_disp (void);
d3ce72d0 169static const insn_template *match_template (void);
e3bb37b5
L		 170static int check_string (void);
171static int process_suffix (void);
172static int check_byte_reg (void);
173static int check_long_reg (void);
174static int check_qword_reg (void);
175static int check_word_reg (void);
176static int finalize_imm (void);
177static int process_operands (void);
178static const seg_entry *build_modrm_byte (void);
179static void output_insn (void);
180static void output_imm (fragS *, offsetT);
181static void output_disp (fragS *, offsetT);
29b0f896 182#ifndef I386COFF
e3bb37b5 183static void s_bss (int);
252b5132 184#endif
17d4e2a2
L		 185#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186static void handle_large_common (int small ATTRIBUTE_UNUSED);
187#endif
252b5132 188
a847613f 189static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 190
c0f3af97
L		 191/* VEX prefix. */
192typedef struct
193{
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes[3];
196 unsigned int length;
197 /* Destination or source register specifier. */
198 const reg_entry *register_specifier;
199} vex_prefix;
200
252b5132 201/* 'md_assemble ()' gathers together information and puts it into a
47926f60 202 i386_insn. */
252b5132 203
520dc8e8
AM		 204union i386_op
205 {
206 expressionS *disps;
207 expressionS *imms;
208 const reg_entry *regs;
209 };
210
a65babc9
L		 211enum i386_error
212 {
86e026a4 213 operand_size_mismatch,
a65babc9
L		 214 operand_type_mismatch,
215 register_type_mismatch,
216 number_of_operands_mismatch,
217 invalid_instruction_suffix,
218 bad_imm4,
219 old_gcc_only,
220 unsupported_with_intel_mnemonic,
221 unsupported_syntax,
6c30d220
L		 222 unsupported,
223 invalid_vsib_address,
7bab8ab5 224 invalid_vector_register_set,
6c30d220 225 unsupported_vector_index_register
a65babc9
L		 226 };
227
252b5132
RH		 228struct _i386_insn
229 {
47926f60 230 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 231 insn_template tm;
252b5132 232
7d5e4556
L		 233 /* SUFFIX holds the instruction size suffix for byte, word, dword
234 or qword, if given. */
252b5132
RH		 235 char suffix;
236
47926f60 237 /* OPERANDS gives the number of given operands. */
252b5132
RH		 238 unsigned int operands;
239
240 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
241 of given register, displacement, memory operands and immediate
47926f60 242 operands. */
252b5132
RH		 243 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
244
245 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 246 use OP[i] for the corresponding operand. */
40fb9820 247 i386_operand_type types[MAX_OPERANDS];
252b5132 248
520dc8e8
AM		 249 /* Displacement expression, immediate expression, or register for each
250 operand. */
251 union i386_op op[MAX_OPERANDS];
252b5132 252
3e73aa7c
JH		 253 /* Flags for operands. */
254 unsigned int flags[MAX_OPERANDS];
255#define Operand_PCrel 1
256
252b5132 257 /* Relocation type for operand */
f86103b7 258 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 259
252b5132
RH		 260 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
261 the base index byte below. */
262 const reg_entry *base_reg;
263 const reg_entry *index_reg;
264 unsigned int log2_scale_factor;
265
266 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 267 explicit segment overrides are given. */
ce8a8b2f 268 const seg_entry *seg[2];
252b5132
RH		 269
270 /* PREFIX holds all the given prefix opcodes (usually null).
271 PREFIXES is the number of prefix opcodes. */
272 unsigned int prefixes;
273 unsigned char prefix[MAX_PREFIXES];
274
275 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 276 addressing modes of this insn are encoded. */
252b5132 277 modrm_byte rm;
3e73aa7c 278 rex_byte rex;
252b5132 279 sib_byte sib;
c0f3af97 280 vex_prefix vex;
b6169b20
L		 281
282 /* Swap operand in encoding. */
4473e004 283 unsigned int swap_operand;
891edac4 284
a501d77e
L		 285 /* Prefer 8bit or 32bit displacement in encoding. */
286 enum
287 {
288 disp_encoding_default = 0,
289 disp_encoding_8bit,
290 disp_encoding_32bit
291 } disp_encoding;
f8a5c266 292
d5de92cf
L		 293 /* REP prefix. */
294 const char *rep_prefix;
295
165de32a
L		 296 /* HLE prefix. */
297 const char *hle_prefix;
42164a71 298
891edac4 299 /* Error message. */
a65babc9 300 enum i386_error error;
252b5132
RH		 301 };
302
303typedef struct _i386_insn i386_insn;
304
305/* List of chars besides those in app.c:symbol_chars that can start an
306 operand. Used to prevent the scrubber eating vital white-space. */
32137342 307const char extra_symbol_chars[] = "*%-(["
252b5132 308#ifdef LEX_AT
32137342
NC		 309 "@"
310#endif
311#ifdef LEX_QM
312 "?"
252b5132 313#endif
32137342 314 ;
252b5132 315
29b0f896
AM		 316#if (defined (TE_I386AIX) \
317 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 318 && !defined (TE_GNU) \
29b0f896 319 && !defined (TE_LINUX) \
8d63c93e
RM		 320 && !defined (TE_NACL) \
321 && !defined (TE_NETWARE) \
29b0f896 322 && !defined (TE_FreeBSD) \
5b806d27 323 && !defined (TE_DragonFly) \
29b0f896 324 && !defined (TE_NetBSD)))
252b5132 325/* This array holds the chars that always start a comment. If the
b3b91714
AM		 326 pre-processor is disabled, these aren't very useful. The option
327 --divide will remove '/' from this list. */
328const char *i386_comment_chars = "#/";
329#define SVR4_COMMENT_CHARS 1
252b5132 330#define PREFIX_SEPARATOR '\\'
252b5132 331
b3b91714
AM		 332#else
333const char *i386_comment_chars = "#";
334#define PREFIX_SEPARATOR '/'
335#endif
336
252b5132
RH		 337/* This array holds the chars that only start a comment at the beginning of
338 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 339 .line and .file directives will appear in the pre-processed output.
340 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 341 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 342 #NO_APP at the beginning of its output.
343 Also note that comments started like this one will always work if
252b5132 344 '/' isn't otherwise defined. */
b3b91714 345const char line_comment_chars[] = "#/";
252b5132 346
63a0b638 347const char line_separator_chars[] = ";";
252b5132 348
ce8a8b2f
AM		 349/* Chars that can be used to separate mant from exp in floating point
350 nums. */
252b5132
RH		 351const char EXP_CHARS[] = "eE";
352
ce8a8b2f
AM		 353/* Chars that mean this number is a floating point constant
354 As in 0f12.456
355 or 0d1.2345e12. */
252b5132
RH		 356const char FLT_CHARS[] = "fFdDxX";
357
ce8a8b2f 358/* Tables for lexical analysis. */
252b5132
RH		 359static char mnemonic_chars[256];
360static char register_chars[256];
361static char operand_chars[256];
362static char identifier_chars[256];
363static char digit_chars[256];
364
ce8a8b2f 365/* Lexical macros. */
252b5132
RH		 366#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
367#define is_operand_char(x) (operand_chars[(unsigned char) x])
368#define is_register_char(x) (register_chars[(unsigned char) x])
369#define is_space_char(x) ((x) == ' ')
370#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
371#define is_digit_char(x) (digit_chars[(unsigned char) x])
372
0234cb7c 373/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 374static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
375
376/* md_assemble() always leaves the strings it's passed unaltered. To
377 effect this we maintain a stack of saved characters that we've smashed
378 with '\0's (indicating end of strings for various sub-fields of the
47926f60 379 assembler instruction). */
252b5132 380static char save_stack[32];
ce8a8b2f 381static char *save_stack_p;
252b5132
RH		 382#define END_STRING_AND_SAVE(s) \
383 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
384#define RESTORE_END_STRING(s) \
385 do { *(s) = *--save_stack_p; } while (0)
386
47926f60 387/* The instruction we're assembling. */
252b5132
RH		 388static i386_insn i;
389
390/* Possible templates for current insn. */
391static const templates *current_templates;
392
31b2323c
L		 393/* Per instruction expressionS buffers: max displacements & immediates. */
394static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
395static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 396
47926f60 397/* Current operand we are working on. */
ee86248c 398static int this_operand = -1;
252b5132 399
3e73aa7c
JH		 400/* We support four different modes. FLAG_CODE variable is used to distinguish
401 these. */
402
403enum flag_code {
404 CODE_32BIT,
405 CODE_16BIT,
406 CODE_64BIT };
407
408static enum flag_code flag_code;
4fa24527 409static unsigned int object_64bit;
862be3fb 410static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 411static int use_rela_relocations = 0;
412
7af8ed2d
NC		 413#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
414 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
415 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
416
351f65ca
L		 417/* The ELF ABI to use. */
418enum x86_elf_abi
419{
420 I386_ABI,
7f56bc95
L		 421 X86_64_ABI,
422 X86_64_X32_ABI
351f65ca
L		 423};
424
425static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 426#endif
351f65ca 427
47926f60
KH		 428/* 1 for intel syntax,
429 0 if att syntax. */
430static int intel_syntax = 0;
252b5132 431
1efbbeb4
L		 432/* 1 for intel mnemonic,
433 0 if att mnemonic. */
434static int intel_mnemonic = !SYSV386_COMPAT;
435
5209009a 436/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 437static int old_gcc = OLDGCC_COMPAT;
438
a60de03c
JB		 439/* 1 if pseudo registers are permitted. */
440static int allow_pseudo_reg = 0;
441
47926f60
KH		 442/* 1 if register prefix % not required. */
443static int allow_naked_reg = 0;
252b5132 444
ba104c83 445/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 446static int allow_index_reg = 0;
447
7bab8ab5 448static enum check_kind
daf50ae7 449 {
7bab8ab5
JB		 450 check_none = 0,
451 check_warning,
452 check_error
daf50ae7 453 }
7bab8ab5 454sse_check, operand_check = check_warning;
daf50ae7 455
2ca3ace5
L		 456/* Register prefix used for error message. */
457static const char *register_prefix = "%";
458
47926f60
KH		 459/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
460 leave, push, and pop instructions so that gcc has the same stack
461 frame as in 32 bit mode. */
462static char stackop_size = '\0';
eecb386c 463
12b55ccc
L		 464/* Non-zero to optimize code alignment. */
465int optimize_align_code = 1;
466
47926f60
KH		 467/* Non-zero to quieten some warnings. */
468static int quiet_warnings = 0;
a38cf1db 469
47926f60
KH		 470/* CPU name. */
471static const char *cpu_arch_name = NULL;
6305a203 472static char *cpu_sub_arch_name = NULL;
a38cf1db 473
47926f60 474/* CPU feature flags. */
40fb9820
L		 475static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
476
ccc9c027
L		 477/* If we have selected a cpu we are generating instructions for. */
478static int cpu_arch_tune_set = 0;
479
9103f4f4 480/* Cpu we are generating instructions for. */
fbf3f584 481enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 482
483/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 484static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 485
ccc9c027 486/* CPU instruction set architecture used. */
fbf3f584 487enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 488
9103f4f4 489/* CPU feature flags of instruction set architecture used. */
fbf3f584 490i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 491
fddf5b5b
AM		 492/* If set, conditional jumps are not automatically promoted to handle
493 larger than a byte offset. */
494static unsigned int no_cond_jump_promotion = 0;
495
c0f3af97
L		 496/* Encode SSE instructions with VEX prefix. */
497static unsigned int sse2avx;
498
539f890d
L		 499/* Encode scalar AVX instructions with specific vector length. */
500static enum
501 {
502 vex128 = 0,
503 vex256
504 } avxscalar;
505
29b0f896 506/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 507static symbolS *GOT_symbol;
29b0f896 508
a4447b93
RH		 509/* The dwarf2 return column, adjusted for 32 or 64 bit. */
510unsigned int x86_dwarf2_return_column;
511
512/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
513int x86_cie_data_alignment;
514
252b5132 515/* Interface to relax_segment.
fddf5b5b
AM		 516 There are 3 major relax states for 386 jump insns because the
517 different types of jumps add different sizes to frags when we're
518 figuring out what sort of jump to choose to reach a given label. */
252b5132 519
47926f60 520/* Types. */
93c2a809
AM		 521#define UNCOND_JUMP 0
522#define COND_JUMP 1
523#define COND_JUMP86 2
fddf5b5b 524
47926f60 525/* Sizes. */
252b5132
RH		 526#define CODE16 1
527#define SMALL 0
29b0f896 528#define SMALL16 (SMALL | CODE16)
252b5132 529#define BIG 2
29b0f896 530#define BIG16 (BIG | CODE16)
252b5132
RH		 531
532#ifndef INLINE
533#ifdef __GNUC__
534#define INLINE __inline__
535#else
536#define INLINE
537#endif
538#endif
539
fddf5b5b
AM		 540#define ENCODE_RELAX_STATE(type, size) \
541 ((relax_substateT) (((type) << 2) | (size)))
542#define TYPE_FROM_RELAX_STATE(s) \
543 ((s) >> 2)
544#define DISP_SIZE_FROM_RELAX_STATE(s) \
545 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 546
547/* This table is used by relax_frag to promote short jumps to long
548 ones where necessary. SMALL (short) jumps may be promoted to BIG
549 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
550 don't allow a short jump in a 32 bit code segment to be promoted to
551 a 16 bit offset jump because it's slower (requires data size
552 prefix), and doesn't work, unless the destination is in the bottom
553 64k of the code segment (The top 16 bits of eip are zeroed). */
554
555const relax_typeS md_relax_table[] =
556{
24eab124
AM		 557 /* The fields are:
558 1) most positive reach of this state,
559 2) most negative reach of this state,
93c2a809 560 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 561 4) which index into the table to try if we can't fit into this one. */
252b5132 562
fddf5b5b 563 /* UNCOND_JUMP states. */
93c2a809
AM		 564 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
565 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
566 /* dword jmp adds 4 bytes to frag:
567 0 extra opcode bytes, 4 displacement bytes. */
252b5132 568 {0, 0, 4, 0},
93c2a809
AM		 569 /* word jmp adds 2 byte2 to frag:
570 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 571 {0, 0, 2, 0},
572
93c2a809
AM		 573 /* COND_JUMP states. */
574 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
575 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
576 /* dword conditionals adds 5 bytes to frag:
577 1 extra opcode byte, 4 displacement bytes. */
578 {0, 0, 5, 0},
fddf5b5b 579 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 580 1 extra opcode byte, 2 displacement bytes. */
581 {0, 0, 3, 0},
582
583 /* COND_JUMP86 states. */
584 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
585 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
586 /* dword conditionals adds 5 bytes to frag:
587 1 extra opcode byte, 4 displacement bytes. */
588 {0, 0, 5, 0},
589 /* word conditionals add 4 bytes to frag:
590 1 displacement byte and a 3 byte long branch insn. */
591 {0, 0, 4, 0}
252b5132
RH		 592};
593
9103f4f4
L		 594static const arch_entry cpu_arch[] =
595{
89507696
JB		 596 /* Do not replace the first two entries - i386_target_format()
597 relies on them being there in this order. */
8a2c8fef 598 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 599 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 600 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 601 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 602 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 603 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 604 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 605 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 606 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 607 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 609 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 611 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 613 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 615 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 617 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 619 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 621 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 623 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 625 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 627 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 629 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 630 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 631 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 632 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 633 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 634 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 635 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 636 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 637 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 639 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 640 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 641 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 642 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
643 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 644 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 645 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 646 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 647 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 648 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 649 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 650 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 651 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 652 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 653 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 654 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 655 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 656 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 657 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 658 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 659 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 660 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 661 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 662 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
663 CPU_BDVER3_FLAGS, 0, 0 },
7b458c12
L		 664 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
665 CPU_BTVER1_FLAGS, 0, 0 },
666 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
667 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 668 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 669 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 670 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 671 CPU_287_FLAGS, 0, 0 },
8a2c8fef 672 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 673 CPU_387_FLAGS, 0, 0 },
8a2c8fef 674 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 675 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 676 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 677 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 678 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 679 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 680 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 681 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 682 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 683 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 684 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 685 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 686 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 687 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 688 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 689 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 690 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 691 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 692 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 693 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 694 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 695 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 696 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 697 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 698 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
699 CPU_AVX2_FLAGS, 0, 0 },
8a2c8fef 700 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 701 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 702 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 703 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 704 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
705 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 706 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 707 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 708 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 709 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 710 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 711 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 712 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 713 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 715 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 716 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 717 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 718 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 719 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 720 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 721 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 722 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 723 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 724 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
725 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 727 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 729 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 731 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 733 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 735 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 736 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
737 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 739 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 740 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
741 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 742 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
743 CPU_HLE_FLAGS, 0, 0 },
744 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
745 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 746 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
747 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 749 CPU_CLFLUSH_FLAGS, 0, 0 },
750 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
751 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 752 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 753 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 755 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 756 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 757 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 758 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 759 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 760 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 761 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 762 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 763 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 764 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 765 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 766 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 767 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 768 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 769 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 770 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
771 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 772 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
773 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 774 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
775 CPU_ADX_FLAGS, 0, 0 },
776 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
777 CPU_RDSEED_FLAGS, 0, 0 },
778 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
779 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 780 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
781 CPU_SMAP_FLAGS, 0, 0 },
e413e4e9
AM		 782};
783
704209c0 784#ifdef I386COFF
a6c24e68
NC		 785/* Like s_lcomm_internal in gas/read.c but the alignment string
786 is allowed to be optional. */
787
788static symbolS *
789pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
790{
791 addressT align = 0;
792
793 SKIP_WHITESPACE ();
794
7ab9ffdd 795 if (needs_align
a6c24e68
NC		 796 && *input_line_pointer == ',')
797 {
798 align = parse_align (needs_align - 1);
7ab9ffdd 799
a6c24e68
NC		 800 if (align == (addressT) -1)
801 return NULL;
802 }
803 else
804 {
805 if (size >= 8)
806 align = 3;
807 else if (size >= 4)
808 align = 2;
809 else if (size >= 2)
810 align = 1;
811 else
812 align = 0;
813 }
814
815 bss_alloc (symbolP, size, align);
816 return symbolP;
817}
818
704209c0 819static void
a6c24e68
NC		 820pe_lcomm (int needs_align)
821{
822 s_comm_internal (needs_align * 2, pe_lcomm_internal);
823}
704209c0 824#endif
a6c24e68 825
29b0f896
AM		 826const pseudo_typeS md_pseudo_table[] =
827{
828#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
829 {"align", s_align_bytes, 0},
830#else
831 {"align", s_align_ptwo, 0},
832#endif
833 {"arch", set_cpu_arch, 0},
834#ifndef I386COFF
835 {"bss", s_bss, 0},
a6c24e68
NC		 836#else
837 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 838#endif
839 {"ffloat", float_cons, 'f'},
840 {"dfloat", float_cons, 'd'},
841 {"tfloat", float_cons, 'x'},
842 {"value", cons, 2},
d182319b 843 {"slong", signed_cons, 4},
29b0f896
AM		 844 {"noopt", s_ignore, 0},
845 {"optim", s_ignore, 0},
846 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
847 {"code16", set_code_flag, CODE_16BIT},
848 {"code32", set_code_flag, CODE_32BIT},
849 {"code64", set_code_flag, CODE_64BIT},
850 {"intel_syntax", set_intel_syntax, 1},
851 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 852 {"intel_mnemonic", set_intel_mnemonic, 1},
853 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 854 {"allow_index_reg", set_allow_index_reg, 1},
855 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 856 {"sse_check", set_check, 0},
857 {"operand_check", set_check, 1},
3b22753a
L		 858#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
859 {"largecomm", handle_large_common, 0},
07a53e5c 860#else
e3bb37b5 861 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 862 {"loc", dwarf2_directive_loc, 0},
863 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 864#endif
6482c264
NC		 865#ifdef TE_PE
866 {"secrel32", pe_directive_secrel, 0},
867#endif
29b0f896
AM		 868 {0, 0, 0}
869};
870
871/* For interface with expression (). */
872extern char *input_line_pointer;
873
874/* Hash table for instruction mnemonic lookup. */
875static struct hash_control *op_hash;
876
877/* Hash table for register lookup. */
878static struct hash_control *reg_hash;
879\f
252b5132 880void
e3bb37b5 881i386_align_code (fragS *fragP, int count)
252b5132 882{
ce8a8b2f
AM		 883 /* Various efficient no-op patterns for aligning code labels.
884 Note: Don't try to assemble the instructions in the comments.
885 0L and 0w are not legal. */
252b5132
RH		 886 static const char f32_1[] =
887 {0x90}; /* nop */
888 static const char f32_2[] =
ccc9c027 889 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 890 static const char f32_3[] =
891 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
892 static const char f32_4[] =
893 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
894 static const char f32_5[] =
895 {0x90, /* nop */
896 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
897 static const char f32_6[] =
898 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
899 static const char f32_7[] =
900 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
901 static const char f32_8[] =
902 {0x90, /* nop */
903 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
904 static const char f32_9[] =
905 {0x89,0xf6, /* movl %esi,%esi */
906 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
907 static const char f32_10[] =
908 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
909 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
910 static const char f32_11[] =
911 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
912 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
913 static const char f32_12[] =
914 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
915 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
916 static const char f32_13[] =
917 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
918 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
919 static const char f32_14[] =
920 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
921 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 922 static const char f16_3[] =
923 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 924 static const char f16_4[] =
925 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
926 static const char f16_5[] =
927 {0x90, /* nop */
928 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
929 static const char f16_6[] =
930 {0x89,0xf6, /* mov %si,%si */
931 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
932 static const char f16_7[] =
933 {0x8d,0x74,0x00, /* lea 0(%si),%si */
934 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
935 static const char f16_8[] =
936 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
937 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 938 static const char jump_31[] =
939 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
940 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
941 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
942 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 943 static const char *const f32_patt[] = {
944 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 945 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 946 };
947 static const char *const f16_patt[] = {
76bc74dc 948 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 949 };
ccc9c027
L		 950 /* nopl (%[re]ax) */
951 static const char alt_3[] =
952 {0x0f,0x1f,0x00};
953 /* nopl 0(%[re]ax) */
954 static const char alt_4[] =
955 {0x0f,0x1f,0x40,0x00};
956 /* nopl 0(%[re]ax,%[re]ax,1) */
957 static const char alt_5[] =
958 {0x0f,0x1f,0x44,0x00,0x00};
959 /* nopw 0(%[re]ax,%[re]ax,1) */
960 static const char alt_6[] =
961 {0x66,0x0f,0x1f,0x44,0x00,0x00};
962 /* nopl 0L(%[re]ax) */
963 static const char alt_7[] =
964 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
965 /* nopl 0L(%[re]ax,%[re]ax,1) */
966 static const char alt_8[] =
967 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
968 /* nopw 0L(%[re]ax,%[re]ax,1) */
969 static const char alt_9[] =
970 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
971 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
972 static const char alt_10[] =
973 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
974 /* data16
975 nopw %cs:0L(%[re]ax,%[re]ax,1) */
976 static const char alt_long_11[] =
977 {0x66,
978 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
979 /* data16
980 data16
981 nopw %cs:0L(%[re]ax,%[re]ax,1) */
982 static const char alt_long_12[] =
983 {0x66,
984 0x66,
985 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
986 /* data16
987 data16
988 data16
989 nopw %cs:0L(%[re]ax,%[re]ax,1) */
990 static const char alt_long_13[] =
991 {0x66,
992 0x66,
993 0x66,
994 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
995 /* data16
996 data16
997 data16
998 data16
999 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1000 static const char alt_long_14[] =
1001 {0x66,
1002 0x66,
1003 0x66,
1004 0x66,
1005 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1006 /* data16
1007 data16
1008 data16
1009 data16
1010 data16
1011 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1012 static const char alt_long_15[] =
1013 {0x66,
1014 0x66,
1015 0x66,
1016 0x66,
1017 0x66,
1018 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1019 /* nopl 0(%[re]ax,%[re]ax,1)
1020 nopw 0(%[re]ax,%[re]ax,1) */
1021 static const char alt_short_11[] =
1022 {0x0f,0x1f,0x44,0x00,0x00,
1023 0x66,0x0f,0x1f,0x44,0x00,0x00};
1024 /* nopw 0(%[re]ax,%[re]ax,1)
1025 nopw 0(%[re]ax,%[re]ax,1) */
1026 static const char alt_short_12[] =
1027 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1028 0x66,0x0f,0x1f,0x44,0x00,0x00};
1029 /* nopw 0(%[re]ax,%[re]ax,1)
1030 nopl 0L(%[re]ax) */
1031 static const char alt_short_13[] =
1032 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1033 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1034 /* nopl 0L(%[re]ax)
1035 nopl 0L(%[re]ax) */
1036 static const char alt_short_14[] =
1037 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1038 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1039 /* nopl 0L(%[re]ax)
1040 nopl 0L(%[re]ax,%[re]ax,1) */
1041 static const char alt_short_15[] =
1042 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1043 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1044 static const char *const alt_short_patt[] = {
1045 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1046 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1047 alt_short_14, alt_short_15
1048 };
1049 static const char *const alt_long_patt[] = {
1050 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1051 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1052 alt_long_14, alt_long_15
1053 };
252b5132 1054
76bc74dc
L		 1055 /* Only align for at least a positive non-zero boundary. */
1056 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1057 return;
3e73aa7c 1058
ccc9c027
L		 1059 /* We need to decide which NOP sequence to use for 32bit and
1060 64bit. When -mtune= is used:
4eed87de 1061
76bc74dc
L		 1062 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1063 PROCESSOR_GENERIC32, f32_patt will be used.
1064 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1065 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1066 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1067 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1068 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1069 will be used.
ccc9c027 1070
76bc74dc 1071 When -mtune= isn't used, alt_long_patt will be used if
22109423 1072 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1073 be used.
ccc9c027
L		 1074
1075 When -march= or .arch is used, we can't use anything beyond
1076 cpu_arch_isa_flags. */
1077
1078 if (flag_code == CODE_16BIT)
1079 {
ccc9c027 1080 if (count > 8)
33fef721 1081 {
76bc74dc
L		 1082 memcpy (fragP->fr_literal + fragP->fr_fix,
1083 jump_31, count);
1084 /* Adjust jump offset. */
1085 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1086 }
76bc74dc
L		 1087 else
1088 memcpy (fragP->fr_literal + fragP->fr_fix,
1089 f16_patt[count - 1], count);
252b5132 1090 }
33fef721 1091 else
ccc9c027
L		 1092 {
1093 const char *const *patt = NULL;
1094
fbf3f584 1095 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1096 {
1097 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1098 switch (cpu_arch_tune)
1099 {
1100 case PROCESSOR_UNKNOWN:
1101 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1102 optimize with nops. */
1103 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1104 patt = alt_long_patt;
ccc9c027
L		 1105 else
1106 patt = f32_patt;
1107 break;
ccc9c027
L		 1108 case PROCESSOR_PENTIUM4:
1109 case PROCESSOR_NOCONA:
ef05d495 1110 case PROCESSOR_CORE:
76bc74dc 1111 case PROCESSOR_CORE2:
bd5295b2 1112 case PROCESSOR_COREI7:
3632d14b 1113 case PROCESSOR_L1OM:
7a9068fe 1114 case PROCESSOR_K1OM:
76bc74dc
L		 1115 case PROCESSOR_GENERIC64:
1116 patt = alt_long_patt;
1117 break;
ccc9c027
L		 1118 case PROCESSOR_K6:
1119 case PROCESSOR_ATHLON:
1120 case PROCESSOR_K8:
4eed87de 1121 case PROCESSOR_AMDFAM10:
8aedb9fe 1122 case PROCESSOR_BD:
7b458c12 1123 case PROCESSOR_BT:
ccc9c027
L		 1124 patt = alt_short_patt;
1125 break;
76bc74dc 1126 case PROCESSOR_I386:
ccc9c027
L		 1127 case PROCESSOR_I486:
1128 case PROCESSOR_PENTIUM:
2dde1948 1129 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1130 case PROCESSOR_GENERIC32:
1131 patt = f32_patt;
1132 break;
4eed87de 1133 }
ccc9c027
L		 1134 }
1135 else
1136 {
fbf3f584 1137 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1138 {
1139 case PROCESSOR_UNKNOWN:
e6a14101 1140 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1141 PROCESSOR_UNKNOWN. */
1142 abort ();
1143 break;
1144
76bc74dc 1145 case PROCESSOR_I386:
ccc9c027
L		 1146 case PROCESSOR_I486:
1147 case PROCESSOR_PENTIUM:
ccc9c027
L		 1148 case PROCESSOR_K6:
1149 case PROCESSOR_ATHLON:
1150 case PROCESSOR_K8:
4eed87de 1151 case PROCESSOR_AMDFAM10:
8aedb9fe 1152 case PROCESSOR_BD:
7b458c12 1153 case PROCESSOR_BT:
ccc9c027
L		 1154 case PROCESSOR_GENERIC32:
1155 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1156 with nops. */
1157 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1158 patt = alt_short_patt;
1159 else
1160 patt = f32_patt;
1161 break;
76bc74dc
L		 1162 case PROCESSOR_PENTIUMPRO:
1163 case PROCESSOR_PENTIUM4:
1164 case PROCESSOR_NOCONA:
1165 case PROCESSOR_CORE:
ef05d495 1166 case PROCESSOR_CORE2:
bd5295b2 1167 case PROCESSOR_COREI7:
3632d14b 1168 case PROCESSOR_L1OM:
7a9068fe 1169 case PROCESSOR_K1OM:
22109423 1170 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1171 patt = alt_long_patt;
1172 else
1173 patt = f32_patt;
1174 break;
1175 case PROCESSOR_GENERIC64:
76bc74dc 1176 patt = alt_long_patt;
ccc9c027 1177 break;
4eed87de 1178 }
ccc9c027
L		 1179 }
1180
76bc74dc
L		 1181 if (patt == f32_patt)
1182 {
1183 /* If the padding is less than 15 bytes, we use the normal
1184 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1185 its offset. */
1186 int limit;
76ba9986 1187
711eedef
L		 1188 /* For 64bit, the limit is 3 bytes. */
1189 if (flag_code == CODE_64BIT
1190 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1191 limit = 3;
1192 else
1193 limit = 15;
1194 if (count < limit)
76bc74dc
L		 1195 memcpy (fragP->fr_literal + fragP->fr_fix,
1196 patt[count - 1], count);
1197 else
1198 {
1199 memcpy (fragP->fr_literal + fragP->fr_fix,
1200 jump_31, count);
1201 /* Adjust jump offset. */
1202 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1203 }
1204 }
1205 else
1206 {
1207 /* Maximum length of an instruction is 15 byte. If the
1208 padding is greater than 15 bytes and we don't use jump,
1209 we have to break it into smaller pieces. */
1210 int padding = count;
1211 while (padding > 15)
1212 {
1213 padding -= 15;
1214 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1215 patt [14], 15);
1216 }
1217
1218 if (padding)
1219 memcpy (fragP->fr_literal + fragP->fr_fix,
1220 patt [padding - 1], padding);
1221 }
ccc9c027 1222 }
33fef721 1223 fragP->fr_var = count;
252b5132
RH		 1224}
1225
c6fb90c8 1226static INLINE int
0dfbf9d7 1227operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1228{
0dfbf9d7 1229 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1230 {
1231 case 3:
0dfbf9d7 1232 if (x->array[2])
c6fb90c8
L		 1233 return 0;
1234 case 2:
0dfbf9d7 1235 if (x->array[1])
c6fb90c8
L		 1236 return 0;
1237 case 1:
0dfbf9d7 1238 return !x->array[0];
c6fb90c8
L		 1239 default:
1240 abort ();
1241 }
40fb9820
L		 1242}
1243
c6fb90c8 1244static INLINE void
0dfbf9d7 1245operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1246{
0dfbf9d7 1247 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1248 {
1249 case 3:
0dfbf9d7 1250 x->array[2] = v;
c6fb90c8 1251 case 2:
0dfbf9d7 1252 x->array[1] = v;
c6fb90c8 1253 case 1:
0dfbf9d7 1254 x->array[0] = v;
c6fb90c8
L		 1255 break;
1256 default:
1257 abort ();
1258 }
1259}
40fb9820 1260
c6fb90c8 1261static INLINE int
0dfbf9d7
L		 1262operand_type_equal (const union i386_operand_type *x,
1263 const union i386_operand_type *y)
c6fb90c8 1264{
0dfbf9d7 1265 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1266 {
1267 case 3:
0dfbf9d7 1268 if (x->array[2] != y->array[2])
c6fb90c8
L		 1269 return 0;
1270 case 2:
0dfbf9d7 1271 if (x->array[1] != y->array[1])
c6fb90c8
L		 1272 return 0;
1273 case 1:
0dfbf9d7 1274 return x->array[0] == y->array[0];
c6fb90c8
L		 1275 break;
1276 default:
1277 abort ();
1278 }
1279}
40fb9820 1280
0dfbf9d7
L		 1281static INLINE int
1282cpu_flags_all_zero (const union i386_cpu_flags *x)
1283{
1284 switch (ARRAY_SIZE(x->array))
1285 {
1286 case 3:
1287 if (x->array[2])
1288 return 0;
1289 case 2:
1290 if (x->array[1])
1291 return 0;
1292 case 1:
1293 return !x->array[0];
1294 default:
1295 abort ();
1296 }
1297}
1298
1299static INLINE void
1300cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1301{
1302 switch (ARRAY_SIZE(x->array))
1303 {
1304 case 3:
1305 x->array[2] = v;
1306 case 2:
1307 x->array[1] = v;
1308 case 1:
1309 x->array[0] = v;
1310 break;
1311 default:
1312 abort ();
1313 }
1314}
1315
1316static INLINE int
1317cpu_flags_equal (const union i386_cpu_flags *x,
1318 const union i386_cpu_flags *y)
1319{
1320 switch (ARRAY_SIZE(x->array))
1321 {
1322 case 3:
1323 if (x->array[2] != y->array[2])
1324 return 0;
1325 case 2:
1326 if (x->array[1] != y->array[1])
1327 return 0;
1328 case 1:
1329 return x->array[0] == y->array[0];
1330 break;
1331 default:
1332 abort ();
1333 }
1334}
c6fb90c8
L		 1335
1336static INLINE int
1337cpu_flags_check_cpu64 (i386_cpu_flags f)
1338{
1339 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1340 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1341}
1342
c6fb90c8
L		 1343static INLINE i386_cpu_flags
1344cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1345{
c6fb90c8
L		 1346 switch (ARRAY_SIZE (x.array))
1347 {
1348 case 3:
1349 x.array [2] &= y.array [2];
1350 case 2:
1351 x.array [1] &= y.array [1];
1352 case 1:
1353 x.array [0] &= y.array [0];
1354 break;
1355 default:
1356 abort ();
1357 }
1358 return x;
1359}
40fb9820 1360
c6fb90c8
L		 1361static INLINE i386_cpu_flags
1362cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1363{
c6fb90c8 1364 switch (ARRAY_SIZE (x.array))
40fb9820 1365 {
c6fb90c8
L		 1366 case 3:
1367 x.array [2] |= y.array [2];
1368 case 2:
1369 x.array [1] |= y.array [1];
1370 case 1:
1371 x.array [0] |= y.array [0];
40fb9820
L		 1372 break;
1373 default:
1374 abort ();
1375 }
40fb9820
L		 1376 return x;
1377}
1378
309d3373
JB		 1379static INLINE i386_cpu_flags
1380cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1381{
1382 switch (ARRAY_SIZE (x.array))
1383 {
1384 case 3:
1385 x.array [2] &= ~y.array [2];
1386 case 2:
1387 x.array [1] &= ~y.array [1];
1388 case 1:
1389 x.array [0] &= ~y.array [0];
1390 break;
1391 default:
1392 abort ();
1393 }
1394 return x;
1395}
1396
c0f3af97
L		 1397#define CPU_FLAGS_ARCH_MATCH 0x1
1398#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1399#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1400#define CPU_FLAGS_PCLMUL_MATCH 0x8
1401#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1402
a5ff0eb2 1403#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1404 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1405 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1406#define CPU_FLAGS_PERFECT_MATCH \
1407 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1408
1409/* Return CPU flags match bits. */
3629bb00 1410
40fb9820 1411static int
d3ce72d0 1412cpu_flags_match (const insn_template *t)
40fb9820 1413{
c0f3af97
L		 1414 i386_cpu_flags x = t->cpu_flags;
1415 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1416
1417 x.bitfield.cpu64 = 0;
1418 x.bitfield.cpuno64 = 0;
1419
0dfbf9d7 1420 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1421 {
1422 /* This instruction is available on all archs. */
1423 match |= CPU_FLAGS_32BIT_MATCH;
1424 }
3629bb00
L		 1425 else
1426 {
c0f3af97 1427 /* This instruction is available only on some archs. */
3629bb00
L		 1428 i386_cpu_flags cpu = cpu_arch_flags;
1429
1430 cpu.bitfield.cpu64 = 0;
1431 cpu.bitfield.cpuno64 = 0;
1432 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1433 if (!cpu_flags_all_zero (&cpu))
1434 {
a5ff0eb2
L		 1435 if (x.bitfield.cpuavx)
1436 {
ce2f5b3c 1437 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1438 if (cpu.bitfield.cpuavx)
1439 {
1440 /* Check SSE2AVX. */
1441 if (!t->opcode_modifier.sse2avx|| sse2avx)
1442 {
1443 match |= (CPU_FLAGS_ARCH_MATCH
1444 | CPU_FLAGS_AVX_MATCH);
1445 /* Check AES. */
1446 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1447 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1448 /* Check PCLMUL. */
1449 if (!x.bitfield.cpupclmul
1450 || cpu.bitfield.cpupclmul)
1451 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1452 }
1453 }
1454 else
1455 match |= CPU_FLAGS_ARCH_MATCH;
1456 }
1457 else
c0f3af97
L		 1458 match |= CPU_FLAGS_32BIT_MATCH;
1459 }
3629bb00 1460 }
c0f3af97 1461 return match;
40fb9820
L		 1462}
1463
c6fb90c8
L		 1464static INLINE i386_operand_type
1465operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1466{
c6fb90c8
L		 1467 switch (ARRAY_SIZE (x.array))
1468 {
1469 case 3:
1470 x.array [2] &= y.array [2];
1471 case 2:
1472 x.array [1] &= y.array [1];
1473 case 1:
1474 x.array [0] &= y.array [0];
1475 break;
1476 default:
1477 abort ();
1478 }
1479 return x;
40fb9820
L		 1480}
1481
c6fb90c8
L		 1482static INLINE i386_operand_type
1483operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1484{
c6fb90c8 1485 switch (ARRAY_SIZE (x.array))
40fb9820 1486 {
c6fb90c8
L		 1487 case 3:
1488 x.array [2] |= y.array [2];
1489 case 2:
1490 x.array [1] |= y.array [1];
1491 case 1:
1492 x.array [0] |= y.array [0];
40fb9820
L		 1493 break;
1494 default:
1495 abort ();
1496 }
c6fb90c8
L		 1497 return x;
1498}
40fb9820 1499
c6fb90c8
L		 1500static INLINE i386_operand_type
1501operand_type_xor (i386_operand_type x, i386_operand_type y)
1502{
1503 switch (ARRAY_SIZE (x.array))
1504 {
1505 case 3:
1506 x.array [2] ^= y.array [2];
1507 case 2:
1508 x.array [1] ^= y.array [1];
1509 case 1:
1510 x.array [0] ^= y.array [0];
1511 break;
1512 default:
1513 abort ();
1514 }
40fb9820
L		 1515 return x;
1516}
1517
1518static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1519static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1520static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1521static const i386_operand_type inoutportreg
1522 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1523static const i386_operand_type reg16_inoutportreg
1524 = OPERAND_TYPE_REG16_INOUTPORTREG;
1525static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1526static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1527static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1528static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1529static const i386_operand_type anydisp
1530 = OPERAND_TYPE_ANYDISP;
40fb9820 1531static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1532static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1533static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1534static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1535static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1536static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1537static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1538static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1539static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1540static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1541static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1542static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1543
1544enum operand_type
1545{
1546 reg,
40fb9820
L		 1547 imm,
1548 disp,
1549 anymem
1550};
1551
c6fb90c8 1552static INLINE int
40fb9820
L		 1553operand_type_check (i386_operand_type t, enum operand_type c)
1554{
1555 switch (c)
1556 {
1557 case reg:
1558 return (t.bitfield.reg8
1559 || t.bitfield.reg16
1560 || t.bitfield.reg32
1561 || t.bitfield.reg64);
1562
40fb9820
L		 1563 case imm:
1564 return (t.bitfield.imm8
1565 || t.bitfield.imm8s
1566 || t.bitfield.imm16
1567 || t.bitfield.imm32
1568 || t.bitfield.imm32s
1569 || t.bitfield.imm64);
1570
1571 case disp:
1572 return (t.bitfield.disp8
1573 || t.bitfield.disp16
1574 || t.bitfield.disp32
1575 || t.bitfield.disp32s
1576 || t.bitfield.disp64);
1577
1578 case anymem:
1579 return (t.bitfield.disp8
1580 || t.bitfield.disp16
1581 || t.bitfield.disp32
1582 || t.bitfield.disp32s
1583 || t.bitfield.disp64
1584 || t.bitfield.baseindex);
1585
1586 default:
1587 abort ();
1588 }
2cfe26b6
AM		 1589
1590 return 0;
40fb9820
L		 1591}
1592
5c07affc
L		 1593/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1594 operand J for instruction template T. */
1595
1596static INLINE int
d3ce72d0 1597match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1598{
1599 return !((i.types[j].bitfield.byte
1600 && !t->operand_types[j].bitfield.byte)
1601 || (i.types[j].bitfield.word
1602 && !t->operand_types[j].bitfield.word)
1603 || (i.types[j].bitfield.dword
1604 && !t->operand_types[j].bitfield.dword)
1605 || (i.types[j].bitfield.qword
1606 && !t->operand_types[j].bitfield.qword));
1607}
1608
1609/* Return 1 if there is no conflict in any size on operand J for
1610 instruction template T. */
1611
1612static INLINE int
d3ce72d0 1613match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1614{
1615 return (match_reg_size (t, j)
1616 && !((i.types[j].bitfield.unspecified
1617 && !t->operand_types[j].bitfield.unspecified)
1618 || (i.types[j].bitfield.fword
1619 && !t->operand_types[j].bitfield.fword)
1620 || (i.types[j].bitfield.tbyte
1621 && !t->operand_types[j].bitfield.tbyte)
1622 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1623 && !t->operand_types[j].bitfield.xmmword)
1624 || (i.types[j].bitfield.ymmword
1625 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1626}
1627
1628/* Return 1 if there is no size conflict on any operands for
1629 instruction template T. */
1630
1631static INLINE int
d3ce72d0 1632operand_size_match (const insn_template *t)
5c07affc
L		 1633{
1634 unsigned int j;
1635 int match = 1;
1636
1637 /* Don't check jump instructions. */
1638 if (t->opcode_modifier.jump
1639 || t->opcode_modifier.jumpbyte
1640 || t->opcode_modifier.jumpdword
1641 || t->opcode_modifier.jumpintersegment)
1642 return match;
1643
1644 /* Check memory and accumulator operand size. */
1645 for (j = 0; j < i.operands; j++)
1646 {
1647 if (t->operand_types[j].bitfield.anysize)
1648 continue;
1649
1650 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1651 {
1652 match = 0;
1653 break;
1654 }
1655
1656 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1657 {
1658 match = 0;
1659 break;
1660 }
1661 }
1662
891edac4 1663 if (match)
5c07affc 1664 return match;
891edac4
L		 1665 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1666 {
1667mismatch:
86e026a4 1668 i.error = operand_size_mismatch;
891edac4
L		 1669 return 0;
1670 }
5c07affc
L		 1671
1672 /* Check reverse. */
9c2799c2 1673 gas_assert (i.operands == 2);
5c07affc
L		 1674
1675 match = 1;
1676 for (j = 0; j < 2; j++)
1677 {
1678 if (t->operand_types[j].bitfield.acc
1679 && !match_reg_size (t, j ? 0 : 1))
891edac4 1680 goto mismatch;
5c07affc
L		 1681
1682 if (i.types[j].bitfield.mem
1683 && !match_mem_size (t, j ? 0 : 1))
891edac4 1684 goto mismatch;
5c07affc
L		 1685 }
1686
1687 return match;
1688}
1689
c6fb90c8 1690static INLINE int
40fb9820
L		 1691operand_type_match (i386_operand_type overlap,
1692 i386_operand_type given)
1693{
1694 i386_operand_type temp = overlap;
1695
1696 temp.bitfield.jumpabsolute = 0;
7d5e4556 1697 temp.bitfield.unspecified = 0;
5c07affc
L		 1698 temp.bitfield.byte = 0;
1699 temp.bitfield.word = 0;
1700 temp.bitfield.dword = 0;
1701 temp.bitfield.fword = 0;
1702 temp.bitfield.qword = 0;
1703 temp.bitfield.tbyte = 0;
1704 temp.bitfield.xmmword = 0;
c0f3af97 1705 temp.bitfield.ymmword = 0;
0dfbf9d7 1706 if (operand_type_all_zero (&temp))
891edac4 1707 goto mismatch;
40fb9820 1708
891edac4
L		 1709 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1710 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1711 return 1;
1712
1713mismatch:
a65babc9 1714 i.error = operand_type_mismatch;
891edac4 1715 return 0;
40fb9820
L		 1716}
1717
7d5e4556 1718/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1719 unless the expected operand type register overlap is null.
1720 Note that Acc in a template matches every size of reg. */
1721
c6fb90c8 1722static INLINE int
40fb9820
L		 1723operand_type_register_match (i386_operand_type m0,
1724 i386_operand_type g0,
1725 i386_operand_type t0,
1726 i386_operand_type m1,
1727 i386_operand_type g1,
1728 i386_operand_type t1)
1729{
1730 if (!operand_type_check (g0, reg))
1731 return 1;
1732
1733 if (!operand_type_check (g1, reg))
1734 return 1;
1735
1736 if (g0.bitfield.reg8 == g1.bitfield.reg8
1737 && g0.bitfield.reg16 == g1.bitfield.reg16
1738 && g0.bitfield.reg32 == g1.bitfield.reg32
1739 && g0.bitfield.reg64 == g1.bitfield.reg64)
1740 return 1;
1741
1742 if (m0.bitfield.acc)
1743 {
1744 t0.bitfield.reg8 = 1;
1745 t0.bitfield.reg16 = 1;
1746 t0.bitfield.reg32 = 1;
1747 t0.bitfield.reg64 = 1;
1748 }
1749
1750 if (m1.bitfield.acc)
1751 {
1752 t1.bitfield.reg8 = 1;
1753 t1.bitfield.reg16 = 1;
1754 t1.bitfield.reg32 = 1;
1755 t1.bitfield.reg64 = 1;
1756 }
1757
891edac4
L		 1758 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1759 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1760 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1761 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1762 return 1;
1763
a65babc9 1764 i.error = register_type_mismatch;
891edac4
L		 1765
1766 return 0;
40fb9820
L		 1767}
1768
4c692bc7
JB		 1769static INLINE unsigned int
1770register_number (const reg_entry *r)
1771{
1772 unsigned int nr = r->reg_num;
1773
1774 if (r->reg_flags & RegRex)
1775 nr += 8;
1776
1777 return nr;
1778}
1779
252b5132 1780static INLINE unsigned int
40fb9820 1781mode_from_disp_size (i386_operand_type t)
252b5132 1782{
40fb9820
L		 1783 if (t.bitfield.disp8)
1784 return 1;
1785 else if (t.bitfield.disp16
1786 || t.bitfield.disp32
1787 || t.bitfield.disp32s)
1788 return 2;
1789 else
1790 return 0;
252b5132
RH		 1791}
1792
1793static INLINE int
e3bb37b5 1794fits_in_signed_byte (offsetT num)
252b5132
RH		 1795{
1796 return (num >= -128) && (num <= 127);
47926f60 1797}
252b5132
RH		 1798
1799static INLINE int
e3bb37b5 1800fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1801{
1802 return (num & 0xff) == num;
47926f60 1803}
252b5132
RH		 1804
1805static INLINE int
e3bb37b5 1806fits_in_unsigned_word (offsetT num)
252b5132
RH		 1807{
1808 return (num & 0xffff) == num;
47926f60 1809}
252b5132
RH		 1810
1811static INLINE int
e3bb37b5 1812fits_in_signed_word (offsetT num)
252b5132
RH		 1813{
1814 return (-32768 <= num) && (num <= 32767);
47926f60 1815}
2a962e6d 1816
3e73aa7c 1817static INLINE int
e3bb37b5 1818fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1819{
1820#ifndef BFD64
1821 return 1;
1822#else
1823 return (!(((offsetT) -1 << 31) & num)
1824 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1825#endif
1826} /* fits_in_signed_long() */
2a962e6d 1827
3e73aa7c 1828static INLINE int
e3bb37b5 1829fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1830{
1831#ifndef BFD64
1832 return 1;
1833#else
1834 return (num & (((offsetT) 2 << 31) - 1)) == num;
1835#endif
1836} /* fits_in_unsigned_long() */
252b5132 1837
a683cc34
SP		 1838static INLINE int
1839fits_in_imm4 (offsetT num)
1840{
1841 return (num & 0xf) == num;
1842}
1843
40fb9820 1844static i386_operand_type
e3bb37b5 1845smallest_imm_type (offsetT num)
252b5132 1846{
40fb9820 1847 i386_operand_type t;
7ab9ffdd 1848
0dfbf9d7 1849 operand_type_set (&t, 0);
40fb9820
L		 1850 t.bitfield.imm64 = 1;
1851
1852 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1853 {
1854 /* This code is disabled on the 486 because all the Imm1 forms
1855 in the opcode table are slower on the i486. They're the
1856 versions with the implicitly specified single-position
1857 displacement, which has another syntax if you really want to
1858 use that form. */
40fb9820
L		 1859 t.bitfield.imm1 = 1;
1860 t.bitfield.imm8 = 1;
1861 t.bitfield.imm8s = 1;
1862 t.bitfield.imm16 = 1;
1863 t.bitfield.imm32 = 1;
1864 t.bitfield.imm32s = 1;
1865 }
1866 else if (fits_in_signed_byte (num))
1867 {
1868 t.bitfield.imm8 = 1;
1869 t.bitfield.imm8s = 1;
1870 t.bitfield.imm16 = 1;
1871 t.bitfield.imm32 = 1;
1872 t.bitfield.imm32s = 1;
1873 }
1874 else if (fits_in_unsigned_byte (num))
1875 {
1876 t.bitfield.imm8 = 1;
1877 t.bitfield.imm16 = 1;
1878 t.bitfield.imm32 = 1;
1879 t.bitfield.imm32s = 1;
1880 }
1881 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1882 {
1883 t.bitfield.imm16 = 1;
1884 t.bitfield.imm32 = 1;
1885 t.bitfield.imm32s = 1;
1886 }
1887 else if (fits_in_signed_long (num))
1888 {
1889 t.bitfield.imm32 = 1;
1890 t.bitfield.imm32s = 1;
1891 }
1892 else if (fits_in_unsigned_long (num))
1893 t.bitfield.imm32 = 1;
1894
1895 return t;
47926f60 1896}
252b5132 1897
847f7ad4 1898static offsetT
e3bb37b5 1899offset_in_range (offsetT val, int size)
847f7ad4 1900{
508866be 1901 addressT mask;
ba2adb93 1902
847f7ad4
AM		 1903 switch (size)
1904 {
508866be
L		 1905 case 1: mask = ((addressT) 1 << 8) - 1; break;
1906 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1907 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1908#ifdef BFD64
1909 case 8: mask = ((addressT) 2 << 63) - 1; break;
1910#endif
47926f60 1911 default: abort ();
847f7ad4
AM		 1912 }
1913
9de868bf
L		 1914#ifdef BFD64
1915 /* If BFD64, sign extend val for 32bit address mode. */
1916 if (flag_code != CODE_64BIT
1917 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1918 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1919 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1920#endif
ba2adb93 1921
47926f60 1922 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1923 {
1924 char buf1[40], buf2[40];
1925
1926 sprint_value (buf1, val);
1927 sprint_value (buf2, val & mask);
1928 as_warn (_("%s shortened to %s"), buf1, buf2);
1929 }
1930 return val & mask;
1931}
1932
c32fa91d
L		 1933enum PREFIX_GROUP
1934{
1935 PREFIX_EXIST = 0,
1936 PREFIX_LOCK,
1937 PREFIX_REP,
1938 PREFIX_OTHER
1939};
1940
1941/* Returns
1942 a. PREFIX_EXIST if attempting to add a prefix where one from the
1943 same class already exists.
1944 b. PREFIX_LOCK if lock prefix is added.
1945 c. PREFIX_REP if rep/repne prefix is added.
1946 d. PREFIX_OTHER if other prefix is added.
1947 */
1948
1949static enum PREFIX_GROUP
e3bb37b5 1950add_prefix (unsigned int prefix)
252b5132 1951{
c32fa91d 1952 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1953 unsigned int q;
252b5132 1954
29b0f896
AM		 1955 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1956 && flag_code == CODE_64BIT)
b1905489 1957 {
161a04f6
L		 1958 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1959 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1960 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1961 ret = PREFIX_EXIST;
b1905489
JB		 1962 q = REX_PREFIX;
1963 }
3e73aa7c 1964 else
b1905489
JB		 1965 {
1966 switch (prefix)
1967 {
1968 default:
1969 abort ();
1970
1971 case CS_PREFIX_OPCODE:
1972 case DS_PREFIX_OPCODE:
1973 case ES_PREFIX_OPCODE:
1974 case FS_PREFIX_OPCODE:
1975 case GS_PREFIX_OPCODE:
1976 case SS_PREFIX_OPCODE:
1977 q = SEG_PREFIX;
1978 break;
1979
1980 case REPNE_PREFIX_OPCODE:
1981 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1982 q = REP_PREFIX;
1983 ret = PREFIX_REP;
1984 break;
1985
b1905489 1986 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1987 q = LOCK_PREFIX;
1988 ret = PREFIX_LOCK;
b1905489
JB		 1989 break;
1990
1991 case FWAIT_OPCODE:
1992 q = WAIT_PREFIX;
1993 break;
1994
1995 case ADDR_PREFIX_OPCODE:
1996 q = ADDR_PREFIX;
1997 break;
1998
1999 case DATA_PREFIX_OPCODE:
2000 q = DATA_PREFIX;
2001 break;
2002 }
2003 if (i.prefix[q] != 0)
c32fa91d 2004 ret = PREFIX_EXIST;
b1905489 2005 }
252b5132 2006
b1905489 2007 if (ret)
252b5132 2008 {
b1905489
JB		 2009 if (!i.prefix[q])
2010 ++i.prefixes;
2011 i.prefix[q] |= prefix;
252b5132 2012 }
b1905489
JB		 2013 else
2014 as_bad (_("same type of prefix used twice"));
252b5132 2015
252b5132
RH		 2016 return ret;
2017}
2018
2019static void
78f12dd3 2020update_code_flag (int value, int check)
eecb386c 2021{
78f12dd3
L		 2022 PRINTF_LIKE ((*as_error));
2023
1e9cc1c2 2024 flag_code = (enum flag_code) value;
40fb9820
L		 2025 if (flag_code == CODE_64BIT)
2026 {
2027 cpu_arch_flags.bitfield.cpu64 = 1;
2028 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2029 }
2030 else
2031 {
2032 cpu_arch_flags.bitfield.cpu64 = 0;
2033 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2034 }
2035 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2036 {
78f12dd3
L		 2037 if (check)
2038 as_error = as_fatal;
2039 else
2040 as_error = as_bad;
2041 (*as_error) (_("64bit mode not supported on `%s'."),
2042 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2043 }
40fb9820 2044 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2045 {
78f12dd3
L		 2046 if (check)
2047 as_error = as_fatal;
2048 else
2049 as_error = as_bad;
2050 (*as_error) (_("32bit mode not supported on `%s'."),
2051 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2052 }
eecb386c
AM		 2053 stackop_size = '\0';
2054}
2055
78f12dd3
L		 2056static void
2057set_code_flag (int value)
2058{
2059 update_code_flag (value, 0);
2060}
2061
eecb386c 2062static void
e3bb37b5 2063set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2064{
1e9cc1c2 2065 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2066 if (flag_code != CODE_16BIT)
2067 abort ();
2068 cpu_arch_flags.bitfield.cpu64 = 0;
2069 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2070 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2071}
2072
2073static void
e3bb37b5 2074set_intel_syntax (int syntax_flag)
252b5132
RH		 2075{
2076 /* Find out if register prefixing is specified. */
2077 int ask_naked_reg = 0;
2078
2079 SKIP_WHITESPACE ();
29b0f896 2080 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2081 {
2082 char *string = input_line_pointer;
2083 int e = get_symbol_end ();
2084
47926f60 2085 if (strcmp (string, "prefix") == 0)
252b5132 2086 ask_naked_reg = 1;
47926f60 2087 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2088 ask_naked_reg = -1;
2089 else
d0b47220 2090 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2091 *input_line_pointer = e;
2092 }
2093 demand_empty_rest_of_line ();
c3332e24 2094
252b5132
RH		 2095 intel_syntax = syntax_flag;
2096
2097 if (ask_naked_reg == 0)
f86103b7
AM		 2098 allow_naked_reg = (intel_syntax
2099 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2100 else
2101 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2102
ee86248c 2103 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2104
e4a3b5a4 2105 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2106 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2107 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2108}
2109
1efbbeb4
L		 2110static void
2111set_intel_mnemonic (int mnemonic_flag)
2112{
e1d4d893 2113 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2114}
2115
db51cc60
L		 2116static void
2117set_allow_index_reg (int flag)
2118{
2119 allow_index_reg = flag;
2120}
2121
cb19c032 2122static void
7bab8ab5 2123set_check (int what)
cb19c032 2124{
7bab8ab5
JB		 2125 enum check_kind *kind;
2126 const char *str;
2127
2128 if (what)
2129 {
2130 kind = &operand_check;
2131 str = "operand";
2132 }
2133 else
2134 {
2135 kind = &sse_check;
2136 str = "sse";
2137 }
2138
cb19c032
L		 2139 SKIP_WHITESPACE ();
2140
2141 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2142 {
2143 char *string = input_line_pointer;
2144 int e = get_symbol_end ();
2145
2146 if (strcmp (string, "none") == 0)
7bab8ab5 2147 *kind = check_none;
cb19c032 2148 else if (strcmp (string, "warning") == 0)
7bab8ab5 2149 *kind = check_warning;
cb19c032 2150 else if (strcmp (string, "error") == 0)
7bab8ab5 2151 *kind = check_error;
cb19c032 2152 else
7bab8ab5 2153 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2154 *input_line_pointer = e;
2155 }
2156 else
7bab8ab5 2157 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2158
2159 demand_empty_rest_of_line ();
2160}
2161
8a9036a4
L		 2162static void
2163check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2164 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2165{
2166#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2167 static const char *arch;
2168
2169 /* Intel LIOM is only supported on ELF. */
2170 if (!IS_ELF)
2171 return;
2172
2173 if (!arch)
2174 {
2175 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2176 use default_arch. */
2177 arch = cpu_arch_name;
2178 if (!arch)
2179 arch = default_arch;
2180 }
2181
3632d14b 2182 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2183 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2184 || new_flag.bitfield.cpul1om)
8a9036a4 2185 return;
76ba9986 2186
7a9068fe
L		 2187 /* If we are targeting Intel K1OM, we must enable it. */
2188 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2189 || new_flag.bitfield.cpuk1om)
2190 return;
2191
8a9036a4
L		 2192 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2193#endif
2194}
2195
e413e4e9 2196static void
e3bb37b5 2197set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2198{
47926f60 2199 SKIP_WHITESPACE ();
e413e4e9 2200
29b0f896 2201 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2202 {
2203 char *string = input_line_pointer;
2204 int e = get_symbol_end ();
91d6fa6a 2205 unsigned int j;
40fb9820 2206 i386_cpu_flags flags;
e413e4e9 2207
91d6fa6a 2208 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2209 {
91d6fa6a 2210 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2211 {
91d6fa6a 2212 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2213
5c6af06e
JB		 2214 if (*string != '.')
2215 {
91d6fa6a 2216 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2217 cpu_sub_arch_name = NULL;
91d6fa6a 2218 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2219 if (flag_code == CODE_64BIT)
2220 {
2221 cpu_arch_flags.bitfield.cpu64 = 1;
2222 cpu_arch_flags.bitfield.cpuno64 = 0;
2223 }
2224 else
2225 {
2226 cpu_arch_flags.bitfield.cpu64 = 0;
2227 cpu_arch_flags.bitfield.cpuno64 = 1;
2228 }
91d6fa6a
NC		 2229 cpu_arch_isa = cpu_arch[j].type;
2230 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2231 if (!cpu_arch_tune_set)
2232 {
2233 cpu_arch_tune = cpu_arch_isa;
2234 cpu_arch_tune_flags = cpu_arch_isa_flags;
2235 }
5c6af06e
JB		 2236 break;
2237 }
40fb9820 2238
22109423 2239 if (!cpu_arch[j].negated)
309d3373 2240 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2241 cpu_arch[j].flags);
309d3373
JB		 2242 else
2243 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2244 cpu_arch[j].flags);
0dfbf9d7 2245 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2246 {
6305a203
L		 2247 if (cpu_sub_arch_name)
2248 {
2249 char *name = cpu_sub_arch_name;
2250 cpu_sub_arch_name = concat (name,
91d6fa6a 2251 cpu_arch[j].name,
1bf57e9f 2252 (const char *) NULL);
6305a203
L		 2253 free (name);
2254 }
2255 else
91d6fa6a 2256 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2257 cpu_arch_flags = flags;
a586129e 2258 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2259 }
2260 *input_line_pointer = e;
2261 demand_empty_rest_of_line ();
2262 return;
e413e4e9
AM		 2263 }
2264 }
91d6fa6a 2265 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2266 as_bad (_("no such architecture: `%s'"), string);
2267
2268 *input_line_pointer = e;
2269 }
2270 else
2271 as_bad (_("missing cpu architecture"));
2272
fddf5b5b
AM		 2273 no_cond_jump_promotion = 0;
2274 if (*input_line_pointer == ','
29b0f896 2275 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2276 {
2277 char *string = ++input_line_pointer;
2278 int e = get_symbol_end ();
2279
2280 if (strcmp (string, "nojumps") == 0)
2281 no_cond_jump_promotion = 1;
2282 else if (strcmp (string, "jumps") == 0)
2283 ;
2284 else
2285 as_bad (_("no such architecture modifier: `%s'"), string);
2286
2287 *input_line_pointer = e;
2288 }
2289
e413e4e9
AM		 2290 demand_empty_rest_of_line ();
2291}
2292
8a9036a4
L		 2293enum bfd_architecture
2294i386_arch (void)
2295{
3632d14b 2296 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2297 {
2298 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2299 || flag_code != CODE_64BIT)
2300 as_fatal (_("Intel L1OM is 64bit ELF only"));
2301 return bfd_arch_l1om;
2302 }
7a9068fe
L		 2303 else if (cpu_arch_isa == PROCESSOR_K1OM)
2304 {
2305 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2306 || flag_code != CODE_64BIT)
2307 as_fatal (_("Intel K1OM is 64bit ELF only"));
2308 return bfd_arch_k1om;
2309 }
8a9036a4
L		 2310 else
2311 return bfd_arch_i386;
2312}
2313
b9d79e03 2314unsigned long
7016a5d5 2315i386_mach (void)
b9d79e03 2316{
351f65ca 2317 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2318 {
3632d14b 2319 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2320 {
351f65ca
L		 2321 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2322 || default_arch[6] != '\0')
8a9036a4
L		 2323 as_fatal (_("Intel L1OM is 64bit ELF only"));
2324 return bfd_mach_l1om;
2325 }
7a9068fe
L		 2326 else if (cpu_arch_isa == PROCESSOR_K1OM)
2327 {
2328 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2329 || default_arch[6] != '\0')
2330 as_fatal (_("Intel K1OM is 64bit ELF only"));
2331 return bfd_mach_k1om;
2332 }
351f65ca 2333 else if (default_arch[6] == '\0')
8a9036a4 2334 return bfd_mach_x86_64;
351f65ca
L		 2335 else
2336 return bfd_mach_x64_32;
8a9036a4 2337 }
b9d79e03
JH		 2338 else if (!strcmp (default_arch, "i386"))
2339 return bfd_mach_i386_i386;
2340 else
2b5d6a91 2341 as_fatal (_("unknown architecture"));
b9d79e03 2342}
b9d79e03 2343\f
252b5132 2344void
7016a5d5 2345md_begin (void)
252b5132
RH		 2346{
2347 const char *hash_err;
2348
47926f60 2349 /* Initialize op_hash hash table. */
252b5132
RH		 2350 op_hash = hash_new ();
2351
2352 {
d3ce72d0 2353 const insn_template *optab;
29b0f896 2354 templates *core_optab;
252b5132 2355
47926f60
KH		 2356 /* Setup for loop. */
2357 optab = i386_optab;
252b5132
RH		 2358 core_optab = (templates *) xmalloc (sizeof (templates));
2359 core_optab->start = optab;
2360
2361 while (1)
2362 {
2363 ++optab;
2364 if (optab->name == NULL
2365 || strcmp (optab->name, (optab - 1)->name) != 0)
2366 {
2367 /* different name --> ship out current template list;
47926f60 2368 add to hash table; & begin anew. */
252b5132
RH		 2369 core_optab->end = optab;
2370 hash_err = hash_insert (op_hash,
2371 (optab - 1)->name,
5a49b8ac 2372 (void *) core_optab);
252b5132
RH		 2373 if (hash_err)
2374 {
b37df7c4 2375 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2376 (optab - 1)->name,
2377 hash_err);
2378 }
2379 if (optab->name == NULL)
2380 break;
2381 core_optab = (templates *) xmalloc (sizeof (templates));
2382 core_optab->start = optab;
2383 }
2384 }
2385 }
2386
47926f60 2387 /* Initialize reg_hash hash table. */
252b5132
RH		 2388 reg_hash = hash_new ();
2389 {
29b0f896 2390 const reg_entry *regtab;
c3fe08fa 2391 unsigned int regtab_size = i386_regtab_size;
252b5132 2392
c3fe08fa 2393 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2394 {
5a49b8ac 2395 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2396 if (hash_err)
b37df7c4 2397 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2398 regtab->reg_name,
2399 hash_err);
252b5132
RH		 2400 }
2401 }
2402
47926f60 2403 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2404 {
29b0f896
AM		 2405 int c;
2406 char *p;
252b5132
RH		 2407
2408 for (c = 0; c < 256; c++)
2409 {
3882b010 2410 if (ISDIGIT (c))
252b5132
RH		 2411 {
2412 digit_chars[c] = c;
2413 mnemonic_chars[c] = c;
2414 register_chars[c] = c;
2415 operand_chars[c] = c;
2416 }
3882b010 2417 else if (ISLOWER (c))
252b5132
RH		 2418 {
2419 mnemonic_chars[c] = c;
2420 register_chars[c] = c;
2421 operand_chars[c] = c;
2422 }
3882b010 2423 else if (ISUPPER (c))
252b5132 2424 {
3882b010 2425 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2426 register_chars[c] = mnemonic_chars[c];
2427 operand_chars[c] = c;
2428 }
2429
3882b010 2430 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2431 identifier_chars[c] = c;
2432 else if (c >= 128)
2433 {
2434 identifier_chars[c] = c;
2435 operand_chars[c] = c;
2436 }
2437 }
2438
2439#ifdef LEX_AT
2440 identifier_chars['@'] = '@';
32137342
NC		 2441#endif
2442#ifdef LEX_QM
2443 identifier_chars['?'] = '?';
2444 operand_chars['?'] = '?';
252b5132 2445#endif
252b5132 2446 digit_chars['-'] = '-';
c0f3af97 2447 mnemonic_chars['_'] = '_';
791fe849 2448 mnemonic_chars['-'] = '-';
0003779b 2449 mnemonic_chars['.'] = '.';
252b5132
RH		 2450 identifier_chars['_'] = '_';
2451 identifier_chars['.'] = '.';
2452
2453 for (p = operand_special_chars; *p != '\0'; p++)
2454 operand_chars[(unsigned char) *p] = *p;
2455 }
2456
a4447b93
RH		 2457 if (flag_code == CODE_64BIT)
2458 {
ca19b261
KT		 2459#if defined (OBJ_COFF) && defined (TE_PE)
2460 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2461 ? 32 : 16);
2462#else
a4447b93 2463 x86_dwarf2_return_column = 16;
ca19b261 2464#endif
61ff971f 2465 x86_cie_data_alignment = -8;
a4447b93
RH		 2466 }
2467 else
2468 {
2469 x86_dwarf2_return_column = 8;
2470 x86_cie_data_alignment = -4;
2471 }
252b5132
RH		 2472}
2473
2474void
e3bb37b5 2475i386_print_statistics (FILE *file)
252b5132
RH		 2476{
2477 hash_print_statistics (file, "i386 opcode", op_hash);
2478 hash_print_statistics (file, "i386 register", reg_hash);
2479}
2480\f
252b5132
RH		 2481#ifdef DEBUG386
2482
ce8a8b2f 2483/* Debugging routines for md_assemble. */
d3ce72d0 2484static void pte (insn_template *);
40fb9820 2485static void pt (i386_operand_type);
e3bb37b5
L		 2486static void pe (expressionS *);
2487static void ps (symbolS *);
252b5132
RH		 2488
2489static void
e3bb37b5 2490pi (char *line, i386_insn *x)
252b5132 2491{
09137c09 2492 unsigned int j;
252b5132
RH		 2493
2494 fprintf (stdout, "%s: template ", line);
2495 pte (&x->tm);
09f131f2
JH		 2496 fprintf (stdout, " address: base %s index %s scale %x\n",
2497 x->base_reg ? x->base_reg->reg_name : "none",
2498 x->index_reg ? x->index_reg->reg_name : "none",
2499 x->log2_scale_factor);
2500 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2501 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2502 fprintf (stdout, " sib: base %x index %x scale %x\n",
2503 x->sib.base, x->sib.index, x->sib.scale);
2504 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2505 (x->rex & REX_W) != 0,
2506 (x->rex & REX_R) != 0,
2507 (x->rex & REX_X) != 0,
2508 (x->rex & REX_B) != 0);
09137c09 2509 for (j = 0; j < x->operands; j++)
252b5132 2510 {
09137c09
SP		 2511 fprintf (stdout, " #%d: ", j + 1);
2512 pt (x->types[j]);
252b5132 2513 fprintf (stdout, "\n");
09137c09
SP		 2514 if (x->types[j].bitfield.reg8
2515 || x->types[j].bitfield.reg16
2516 || x->types[j].bitfield.reg32
2517 || x->types[j].bitfield.reg64
2518 || x->types[j].bitfield.regmmx
2519 || x->types[j].bitfield.regxmm
2520 || x->types[j].bitfield.regymm
2521 || x->types[j].bitfield.sreg2
2522 || x->types[j].bitfield.sreg3
2523 || x->types[j].bitfield.control
2524 || x->types[j].bitfield.debug
2525 || x->types[j].bitfield.test)
2526 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2527 if (operand_type_check (x->types[j], imm))
2528 pe (x->op[j].imms);
2529 if (operand_type_check (x->types[j], disp))
2530 pe (x->op[j].disps);
252b5132
RH		 2531 }
2532}
2533
2534static void
d3ce72d0 2535pte (insn_template *t)
252b5132 2536{
09137c09 2537 unsigned int j;
252b5132 2538 fprintf (stdout, " %d operands ", t->operands);
47926f60 2539 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2540 if (t->extension_opcode != None)
2541 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2542 if (t->opcode_modifier.d)
252b5132 2543 fprintf (stdout, "D");
40fb9820 2544 if (t->opcode_modifier.w)
252b5132
RH		 2545 fprintf (stdout, "W");
2546 fprintf (stdout, "\n");
09137c09 2547 for (j = 0; j < t->operands; j++)
252b5132 2548 {
09137c09
SP		 2549 fprintf (stdout, " #%d type ", j + 1);
2550 pt (t->operand_types[j]);
252b5132
RH		 2551 fprintf (stdout, "\n");
2552 }
2553}
2554
2555static void
e3bb37b5 2556pe (expressionS *e)
252b5132 2557{
24eab124 2558 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2559 fprintf (stdout, " add_number %ld (%lx)\n",
2560 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2561 if (e->X_add_symbol)
2562 {
2563 fprintf (stdout, " add_symbol ");
2564 ps (e->X_add_symbol);
2565 fprintf (stdout, "\n");
2566 }
2567 if (e->X_op_symbol)
2568 {
2569 fprintf (stdout, " op_symbol ");
2570 ps (e->X_op_symbol);
2571 fprintf (stdout, "\n");
2572 }
2573}
2574
2575static void
e3bb37b5 2576ps (symbolS *s)
252b5132
RH		 2577{
2578 fprintf (stdout, "%s type %s%s",
2579 S_GET_NAME (s),
2580 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2581 segment_name (S_GET_SEGMENT (s)));
2582}
2583
7b81dfbb 2584static struct type_name
252b5132 2585 {
40fb9820
L		 2586 i386_operand_type mask;
2587 const char *name;
252b5132 2588 }
7b81dfbb 2589const type_names[] =
252b5132 2590{
40fb9820
L		 2591 { OPERAND_TYPE_REG8, "r8" },
2592 { OPERAND_TYPE_REG16, "r16" },
2593 { OPERAND_TYPE_REG32, "r32" },
2594 { OPERAND_TYPE_REG64, "r64" },
2595 { OPERAND_TYPE_IMM8, "i8" },
2596 { OPERAND_TYPE_IMM8, "i8s" },
2597 { OPERAND_TYPE_IMM16, "i16" },
2598 { OPERAND_TYPE_IMM32, "i32" },
2599 { OPERAND_TYPE_IMM32S, "i32s" },
2600 { OPERAND_TYPE_IMM64, "i64" },
2601 { OPERAND_TYPE_IMM1, "i1" },
2602 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2603 { OPERAND_TYPE_DISP8, "d8" },
2604 { OPERAND_TYPE_DISP16, "d16" },
2605 { OPERAND_TYPE_DISP32, "d32" },
2606 { OPERAND_TYPE_DISP32S, "d32s" },
2607 { OPERAND_TYPE_DISP64, "d64" },
2608 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2609 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2610 { OPERAND_TYPE_CONTROL, "control reg" },
2611 { OPERAND_TYPE_TEST, "test reg" },
2612 { OPERAND_TYPE_DEBUG, "debug reg" },
2613 { OPERAND_TYPE_FLOATREG, "FReg" },
2614 { OPERAND_TYPE_FLOATACC, "FAcc" },
2615 { OPERAND_TYPE_SREG2, "SReg2" },
2616 { OPERAND_TYPE_SREG3, "SReg3" },
2617 { OPERAND_TYPE_ACC, "Acc" },
2618 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2619 { OPERAND_TYPE_REGMMX, "rMMX" },
2620 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2621 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2622 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2623};
2624
2625static void
40fb9820 2626pt (i386_operand_type t)
252b5132 2627{
40fb9820 2628 unsigned int j;
c6fb90c8 2629 i386_operand_type a;
252b5132 2630
40fb9820 2631 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2632 {
2633 a = operand_type_and (t, type_names[j].mask);
0349dc08 2634 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2635 fprintf (stdout, "%s, ", type_names[j].name);
2636 }
252b5132
RH		 2637 fflush (stdout);
2638}
2639
2640#endif /* DEBUG386 */
2641\f
252b5132 2642static bfd_reloc_code_real_type
3956db08 2643reloc (unsigned int size,
64e74474
AM		 2644 int pcrel,
2645 int sign,
2646 bfd_reloc_code_real_type other)
252b5132 2647{
47926f60 2648 if (other != NO_RELOC)
3956db08 2649 {
91d6fa6a 2650 reloc_howto_type *rel;
3956db08
JB		 2651
2652 if (size == 8)
2653 switch (other)
2654 {
64e74474
AM		 2655 case BFD_RELOC_X86_64_GOT32:
2656 return BFD_RELOC_X86_64_GOT64;
2657 break;
2658 case BFD_RELOC_X86_64_PLTOFF64:
2659 return BFD_RELOC_X86_64_PLTOFF64;
2660 break;
2661 case BFD_RELOC_X86_64_GOTPC32:
2662 other = BFD_RELOC_X86_64_GOTPC64;
2663 break;
2664 case BFD_RELOC_X86_64_GOTPCREL:
2665 other = BFD_RELOC_X86_64_GOTPCREL64;
2666 break;
2667 case BFD_RELOC_X86_64_TPOFF32:
2668 other = BFD_RELOC_X86_64_TPOFF64;
2669 break;
2670 case BFD_RELOC_X86_64_DTPOFF32:
2671 other = BFD_RELOC_X86_64_DTPOFF64;
2672 break;
2673 default:
2674 break;
3956db08 2675 }
e05278af 2676
8ce3d284 2677#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2678 if (other == BFD_RELOC_SIZE32)
2679 {
2680 if (size == 8)
2681 return BFD_RELOC_SIZE64;
2682 if (pcrel)
2683 as_bad (_("there are no pc-relative size relocations"));
2684 }
8ce3d284 2685#endif
8fd4256d 2686
e05278af 2687 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2688 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2689 sign = -1;
2690
91d6fa6a
NC		 2691 rel = bfd_reloc_type_lookup (stdoutput, other);
2692 if (!rel)
3956db08 2693 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2694 else if (size != bfd_get_reloc_size (rel))
3956db08 2695 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2696 bfd_get_reloc_size (rel),
3956db08 2697 size);
91d6fa6a 2698 else if (pcrel && !rel->pc_relative)
3956db08 2699 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2700 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2701 && !sign)
91d6fa6a 2702 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2703 && sign > 0))
3956db08
JB		 2704 as_bad (_("relocated field and relocation type differ in signedness"));
2705 else
2706 return other;
2707 return NO_RELOC;
2708 }
252b5132
RH		 2709
2710 if (pcrel)
2711 {
3e73aa7c 2712 if (!sign)
3956db08 2713 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2714 switch (size)
2715 {
2716 case 1: return BFD_RELOC_8_PCREL;
2717 case 2: return BFD_RELOC_16_PCREL;
2718 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2719 case 8: return BFD_RELOC_64_PCREL;
252b5132 2720 }
3956db08 2721 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2722 }
2723 else
2724 {
3956db08 2725 if (sign > 0)
e5cb08ac 2726 switch (size)
3e73aa7c
JH		 2727 {
2728 case 4: return BFD_RELOC_X86_64_32S;
2729 }
2730 else
2731 switch (size)
2732 {
2733 case 1: return BFD_RELOC_8;
2734 case 2: return BFD_RELOC_16;
2735 case 4: return BFD_RELOC_32;
2736 case 8: return BFD_RELOC_64;
2737 }
3956db08
JB		 2738 as_bad (_("cannot do %s %u byte relocation"),
2739 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2740 }
2741
0cc9e1d3 2742 return NO_RELOC;
252b5132
RH		 2743}
2744
47926f60
KH		 2745/* Here we decide which fixups can be adjusted to make them relative to
2746 the beginning of the section instead of the symbol. Basically we need
2747 to make sure that the dynamic relocations are done correctly, so in
2748 some cases we force the original symbol to be used. */
2749
252b5132 2750int
e3bb37b5 2751tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2752{
6d249963 2753#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2754 if (!IS_ELF)
31312f95
AM		 2755 return 1;
2756
a161fe53
AM		 2757 /* Don't adjust pc-relative references to merge sections in 64-bit
2758 mode. */
2759 if (use_rela_relocations
2760 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2761 && fixP->fx_pcrel)
252b5132 2762 return 0;
31312f95 2763
8d01d9a9
AJ		 2764 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2765 and changed later by validate_fix. */
2766 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2767 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2768 return 0;
2769
8fd4256d
L		 2770 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2771 for size relocations. */
2772 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2773 || fixP->fx_r_type == BFD_RELOC_SIZE64
2774 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2775 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2776 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2777 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2778 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2779 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2780 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2781 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2782 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2783 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2784 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2785 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2786 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2787 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2788 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2789 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2790 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2791 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2792 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2793 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2794 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2795 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2796 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2797 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2798 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2799 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2800 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2801 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2802 return 0;
31312f95 2803#endif
252b5132
RH		 2804 return 1;
2805}
252b5132 2806
b4cac588 2807static int
e3bb37b5 2808intel_float_operand (const char *mnemonic)
252b5132 2809{
9306ca4a
JB		 2810 /* Note that the value returned is meaningful only for opcodes with (memory)
2811 operands, hence the code here is free to improperly handle opcodes that
2812 have no operands (for better performance and smaller code). */
2813
2814 if (mnemonic[0] != 'f')
2815 return 0; /* non-math */
2816
2817 switch (mnemonic[1])
2818 {
2819 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2820 the fs segment override prefix not currently handled because no
2821 call path can make opcodes without operands get here */
2822 case 'i':
2823 return 2 /* integer op */;
2824 case 'l':
2825 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2826 return 3; /* fldcw/fldenv */
2827 break;
2828 case 'n':
2829 if (mnemonic[2] != 'o' /* fnop */)
2830 return 3; /* non-waiting control op */
2831 break;
2832 case 'r':
2833 if (mnemonic[2] == 's')
2834 return 3; /* frstor/frstpm */
2835 break;
2836 case 's':
2837 if (mnemonic[2] == 'a')
2838 return 3; /* fsave */
2839 if (mnemonic[2] == 't')
2840 {
2841 switch (mnemonic[3])
2842 {
2843 case 'c': /* fstcw */
2844 case 'd': /* fstdw */
2845 case 'e': /* fstenv */
2846 case 's': /* fsts[gw] */
2847 return 3;
2848 }
2849 }
2850 break;
2851 case 'x':
2852 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2853 return 0; /* fxsave/fxrstor are not really math ops */
2854 break;
2855 }
252b5132 2856
9306ca4a 2857 return 1;
252b5132
RH		 2858}
2859
c0f3af97
L		 2860/* Build the VEX prefix. */
2861
2862static void
d3ce72d0 2863build_vex_prefix (const insn_template *t)
c0f3af97
L		 2864{
2865 unsigned int register_specifier;
2866 unsigned int implied_prefix;
2867 unsigned int vector_length;
2868
2869 /* Check register specifier. */
2870 if (i.vex.register_specifier)
4c692bc7 2871 register_specifier = ~register_number (i.vex.register_specifier) & 0xf;
c0f3af97
L		 2872 else
2873 register_specifier = 0xf;
2874
fa99fab2
L		 2875 /* Use 2-byte VEX prefix by swappping destination and source
2876 operand. */
2877 if (!i.swap_operand
2878 && i.operands == i.reg_operands
7f399153 2879 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2880 && i.tm.opcode_modifier.s
2881 && i.rex == REX_B)
2882 {
2883 unsigned int xchg = i.operands - 1;
2884 union i386_op temp_op;
2885 i386_operand_type temp_type;
2886
2887 temp_type = i.types[xchg];
2888 i.types[xchg] = i.types[0];
2889 i.types[0] = temp_type;
2890 temp_op = i.op[xchg];
2891 i.op[xchg] = i.op[0];
2892 i.op[0] = temp_op;
2893
9c2799c2 2894 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2895
2896 i.rex = REX_R;
2897 xchg = i.rm.regmem;
2898 i.rm.regmem = i.rm.reg;
2899 i.rm.reg = xchg;
2900
2901 /* Use the next insn. */
2902 i.tm = t[1];
2903 }
2904
539f890d
L		 2905 if (i.tm.opcode_modifier.vex == VEXScalar)
2906 vector_length = avxscalar;
2907 else
2908 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2909
2910 switch ((i.tm.base_opcode >> 8) & 0xff)
2911 {
2912 case 0:
2913 implied_prefix = 0;
2914 break;
2915 case DATA_PREFIX_OPCODE:
2916 implied_prefix = 1;
2917 break;
2918 case REPE_PREFIX_OPCODE:
2919 implied_prefix = 2;
2920 break;
2921 case REPNE_PREFIX_OPCODE:
2922 implied_prefix = 3;
2923 break;
2924 default:
2925 abort ();
2926 }
2927
2928 /* Use 2-byte VEX prefix if possible. */
7f399153 2929 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2930 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2931 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2932 {
2933 /* 2-byte VEX prefix. */
2934 unsigned int r;
2935
2936 i.vex.length = 2;
2937 i.vex.bytes[0] = 0xc5;
2938
2939 /* Check the REX.R bit. */
2940 r = (i.rex & REX_R) ? 0 : 1;
2941 i.vex.bytes[1] = (r << 7
2942 | register_specifier << 3
2943 | vector_length << 2
2944 | implied_prefix);
2945 }
2946 else
2947 {
2948 /* 3-byte VEX prefix. */
2949 unsigned int m, w;
2950
f88c9eb0 2951 i.vex.length = 3;
f88c9eb0 2952
7f399153 2953 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2954 {
7f399153
L		 2955 case VEX0F:
2956 m = 0x1;
80de6e00 2957 i.vex.bytes[0] = 0xc4;
7f399153
L		 2958 break;
2959 case VEX0F38:
2960 m = 0x2;
80de6e00 2961 i.vex.bytes[0] = 0xc4;
7f399153
L		 2962 break;
2963 case VEX0F3A:
2964 m = 0x3;
80de6e00 2965 i.vex.bytes[0] = 0xc4;
7f399153
L		 2966 break;
2967 case XOP08:
5dd85c99
SP		 2968 m = 0x8;
2969 i.vex.bytes[0] = 0x8f;
7f399153
L		 2970 break;
2971 case XOP09:
f88c9eb0
SP		 2972 m = 0x9;
2973 i.vex.bytes[0] = 0x8f;
7f399153
L		 2974 break;
2975 case XOP0A:
f88c9eb0
SP		 2976 m = 0xa;
2977 i.vex.bytes[0] = 0x8f;
7f399153
L		 2978 break;
2979 default:
2980 abort ();
f88c9eb0 2981 }
c0f3af97 2982
c0f3af97
L		 2983 /* The high 3 bits of the second VEX byte are 1's compliment
2984 of RXB bits from REX. */
2985 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2986
2987 /* Check the REX.W bit. */
2988 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2989 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2990 {
2991 if (w)
2992 abort ();
2993
1ef99a7b 2994 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2995 w = 1;
2996 }
2997
2998 i.vex.bytes[2] = (w << 7
2999 | register_specifier << 3
3000 | vector_length << 2
3001 | implied_prefix);
3002 }
3003}
3004
65da13b5
L		 3005static void
3006process_immext (void)
3007{
3008 expressionS *exp;
3009
4c692bc7
JB		 3010 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3011 && i.operands > 0)
65da13b5 3012 {
4c692bc7
JB		 3013 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3014 with an opcode suffix which is coded in the same place as an
3015 8-bit immediate field would be.
3016 Here we check those operands and remove them afterwards. */
65da13b5
L		 3017 unsigned int x;
3018
3019 for (x = 0; x < i.operands; x++)
4c692bc7 3020 if (register_number (i.op[x].regs) != x)
65da13b5 3021 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3022 register_prefix, i.op[x].regs->reg_name, x + 1,
3023 i.tm.name);
3024
3025 i.operands = 0;
65da13b5
L		 3026 }
3027
c0f3af97 3028 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3029 which is coded in the same place as an 8-bit immediate field
3030 would be. Here we fake an 8-bit immediate operand from the
3031 opcode suffix stored in tm.extension_opcode.
3032
c1e679ec 3033 AVX instructions also use this encoding, for some of
c0f3af97 3034 3 argument instructions. */
65da13b5 3035
9c2799c2 3036 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 3037 && (i.operands <= 2
3038 || (i.tm.opcode_modifier.vex
3039 && i.operands <= 4)));
65da13b5
L		 3040
3041 exp = &im_expressions[i.imm_operands++];
3042 i.op[i.operands].imms = exp;
3043 i.types[i.operands] = imm8;
3044 i.operands++;
3045 exp->X_op = O_constant;
3046 exp->X_add_number = i.tm.extension_opcode;
3047 i.tm.extension_opcode = None;
3048}
3049
42164a71
L		 3050
3051static int
3052check_hle (void)
3053{
3054 switch (i.tm.opcode_modifier.hleprefixok)
3055 {
3056 default:
3057 abort ();
82c2def5 3058 case HLEPrefixNone:
165de32a
L		 3059 as_bad (_("invalid instruction `%s' after `%s'"),
3060 i.tm.name, i.hle_prefix);
42164a71 3061 return 0;
82c2def5 3062 case HLEPrefixLock:
42164a71
L		 3063 if (i.prefix[LOCK_PREFIX])
3064 return 1;
165de32a 3065 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3066 return 0;
82c2def5 3067 case HLEPrefixAny:
42164a71 3068 return 1;
82c2def5 3069 case HLEPrefixRelease:
42164a71
L		 3070 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3071 {
3072 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3073 i.tm.name);
3074 return 0;
3075 }
3076 if (i.mem_operands == 0
3077 || !operand_type_check (i.types[i.operands - 1], anymem))
3078 {
3079 as_bad (_("memory destination needed for instruction `%s'"
3080 " after `xrelease'"), i.tm.name);
3081 return 0;
3082 }
3083 return 1;
3084 }
3085}
3086
252b5132
RH		 3087/* This is the guts of the machine-dependent assembler. LINE points to a
3088 machine dependent instruction. This function is supposed to emit
3089 the frags/bytes it assembles to. */
3090
3091void
65da13b5 3092md_assemble (char *line)
252b5132 3093{
40fb9820 3094 unsigned int j;
252b5132 3095 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3096 const insn_template *t;
252b5132 3097
47926f60 3098 /* Initialize globals. */
252b5132
RH		 3099 memset (&i, '\0', sizeof (i));
3100 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3101 i.reloc[j] = NO_RELOC;
252b5132
RH		 3102 memset (disp_expressions, '\0', sizeof (disp_expressions));
3103 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3104 save_stack_p = save_stack;
252b5132
RH		 3105
3106 /* First parse an instruction mnemonic & call i386_operand for the operands.
3107 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3108 start of a (possibly prefixed) mnemonic. */
252b5132 3109
29b0f896
AM		 3110 line = parse_insn (line, mnemonic);
3111 if (line == NULL)
3112 return;
252b5132 3113
29b0f896 3114 line = parse_operands (line, mnemonic);
ee86248c 3115 this_operand = -1;
29b0f896
AM		 3116 if (line == NULL)
3117 return;
252b5132 3118
29b0f896
AM		 3119 /* Now we've parsed the mnemonic into a set of templates, and have the
3120 operands at hand. */
3121
3122 /* All intel opcodes have reversed operands except for "bound" and
3123 "enter". We also don't reverse intersegment "jmp" and "call"
3124 instructions with 2 immediate operands so that the immediate segment
050dfa73 3125 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3126 if (intel_syntax
3127 && i.operands > 1
29b0f896 3128 && (strcmp (mnemonic, "bound") != 0)
30123838 3129 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3130 && !(operand_type_check (i.types[0], imm)
3131 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3132 swap_operands ();
3133
ec56d5c0
JB		 3134 /* The order of the immediates should be reversed
3135 for 2 immediates extrq and insertq instructions */
3136 if (i.imm_operands == 2
3137 && (strcmp (mnemonic, "extrq") == 0
3138 || strcmp (mnemonic, "insertq") == 0))
3139 swap_2_operands (0, 1);
3140
29b0f896
AM		 3141 if (i.imm_operands)
3142 optimize_imm ();
3143
b300c311
L		 3144 /* Don't optimize displacement for movabs since it only takes 64bit
3145 displacement. */
3146 if (i.disp_operands
a501d77e 3147 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3148 && (flag_code != CODE_64BIT
3149 || strcmp (mnemonic, "movabs") != 0))
3150 optimize_disp ();
29b0f896
AM		 3151
3152 /* Next, we find a template that matches the given insn,
3153 making sure the overlap of the given operands types is consistent
3154 with the template operand types. */
252b5132 3155
fa99fab2 3156 if (!(t = match_template ()))
29b0f896 3157 return;
252b5132 3158
7bab8ab5 3159 if (sse_check != check_none
81f8a913 3160 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3161 && (i.tm.cpu_flags.bitfield.cpusse
3162 || i.tm.cpu_flags.bitfield.cpusse2
3163 || i.tm.cpu_flags.bitfield.cpusse3
3164 || i.tm.cpu_flags.bitfield.cpussse3
3165 || i.tm.cpu_flags.bitfield.cpusse4_1
3166 || i.tm.cpu_flags.bitfield.cpusse4_2))
3167 {
7bab8ab5 3168 (sse_check == check_warning
daf50ae7
L		 3169 ? as_warn
3170 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3171 }
3172
321fd21e
L		 3173 /* Zap movzx and movsx suffix. The suffix has been set from
3174 "word ptr" or "byte ptr" on the source operand in Intel syntax
3175 or extracted from mnemonic in AT&T syntax. But we'll use
3176 the destination register to choose the suffix for encoding. */
3177 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3178 {
321fd21e
L		 3179 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3180 there is no suffix, the default will be byte extension. */
3181 if (i.reg_operands != 2
3182 && !i.suffix
7ab9ffdd 3183 && intel_syntax)
321fd21e
L		 3184 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3185
3186 i.suffix = 0;
cd61ebfe 3187 }
24eab124 3188
40fb9820 3189 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3190 if (!add_prefix (FWAIT_OPCODE))
3191 return;
252b5132 3192
d5de92cf
L		 3193 /* Check if REP prefix is OK. */
3194 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3195 {
3196 as_bad (_("invalid instruction `%s' after `%s'"),
3197 i.tm.name, i.rep_prefix);
3198 return;
3199 }
3200
c1ba0266
L		 3201 /* Check for lock without a lockable instruction. Destination operand
3202 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3203 if (i.prefix[LOCK_PREFIX]
3204 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3205 || i.mem_operands == 0
3206 || (i.tm.base_opcode != 0x86
3207 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3208 {
3209 as_bad (_("expecting lockable instruction after `lock'"));
3210 return;
3211 }
3212
42164a71 3213 /* Check if HLE prefix is OK. */
165de32a 3214 if (i.hle_prefix && !check_hle ())
42164a71
L		 3215 return;
3216
29b0f896 3217 /* Check string instruction segment overrides. */
40fb9820 3218 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3219 {
3220 if (!check_string ())
5dd0794d 3221 return;
fc0763e6 3222 i.disp_operands = 0;
29b0f896 3223 }
5dd0794d 3224
29b0f896
AM		 3225 if (!process_suffix ())
3226 return;
e413e4e9 3227
bc0844ae
L		 3228 /* Update operand types. */
3229 for (j = 0; j < i.operands; j++)
3230 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3231
29b0f896
AM		 3232 /* Make still unresolved immediate matches conform to size of immediate
3233 given in i.suffix. */
3234 if (!finalize_imm ())
3235 return;
252b5132 3236
40fb9820 3237 if (i.types[0].bitfield.imm1)
29b0f896 3238 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3239
9afe6eb8
L		 3240 /* We only need to check those implicit registers for instructions
3241 with 3 operands or less. */
3242 if (i.operands <= 3)
3243 for (j = 0; j < i.operands; j++)
3244 if (i.types[j].bitfield.inoutportreg
3245 || i.types[j].bitfield.shiftcount
3246 || i.types[j].bitfield.acc
3247 || i.types[j].bitfield.floatacc)
3248 i.reg_operands--;
40fb9820 3249
c0f3af97
L		 3250 /* ImmExt should be processed after SSE2AVX. */
3251 if (!i.tm.opcode_modifier.sse2avx
3252 && i.tm.opcode_modifier.immext)
65da13b5 3253 process_immext ();
252b5132 3254
29b0f896
AM		 3255 /* For insns with operands there are more diddles to do to the opcode. */
3256 if (i.operands)
3257 {
3258 if (!process_operands ())
3259 return;
3260 }
40fb9820 3261 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3262 {
3263 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3264 as_warn (_("translating to `%sp'"), i.tm.name);
3265 }
252b5132 3266
c0f3af97 3267 if (i.tm.opcode_modifier.vex)
fa99fab2 3268 build_vex_prefix (t);
c0f3af97 3269
5dd85c99
SP		 3270 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3271 instructions may define INT_OPCODE as well, so avoid this corner
3272 case for those instructions that use MODRM. */
3273 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3274 && !i.tm.opcode_modifier.modrm
3275 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3276 {
3277 i.tm.base_opcode = INT3_OPCODE;
3278 i.imm_operands = 0;
3279 }
252b5132 3280
40fb9820
L		 3281 if ((i.tm.opcode_modifier.jump
3282 || i.tm.opcode_modifier.jumpbyte
3283 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3284 && i.op[0].disps->X_op == O_constant)
3285 {
3286 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3287 the absolute address given by the constant. Since ix86 jumps and
3288 calls are pc relative, we need to generate a reloc. */
3289 i.op[0].disps->X_add_symbol = &abs_symbol;
3290 i.op[0].disps->X_op = O_symbol;
3291 }
252b5132 3292
40fb9820 3293 if (i.tm.opcode_modifier.rex64)
161a04f6 3294 i.rex |= REX_W;
252b5132 3295
29b0f896
AM		 3296 /* For 8 bit registers we need an empty rex prefix. Also if the
3297 instruction already has a prefix, we need to convert old
3298 registers to new ones. */
773f551c 3299
40fb9820 3300 if ((i.types[0].bitfield.reg8
29b0f896 3301 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3302 || (i.types[1].bitfield.reg8
29b0f896 3303 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3304 || ((i.types[0].bitfield.reg8
3305 || i.types[1].bitfield.reg8)
29b0f896
AM		 3306 && i.rex != 0))
3307 {
3308 int x;
726c5dcd 3309
29b0f896
AM		 3310 i.rex |= REX_OPCODE;
3311 for (x = 0; x < 2; x++)
3312 {
3313 /* Look for 8 bit operand that uses old registers. */
40fb9820 3314 if (i.types[x].bitfield.reg8
29b0f896 3315 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3316 {
29b0f896
AM		 3317 /* In case it is "hi" register, give up. */
3318 if (i.op[x].regs->reg_num > 3)
a540244d 3319 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3320 "instruction requiring REX prefix."),
a540244d 3321 register_prefix, i.op[x].regs->reg_name);
773f551c 3322
29b0f896
AM		 3323 /* Otherwise it is equivalent to the extended register.
3324 Since the encoding doesn't change this is merely
3325 cosmetic cleanup for debug output. */
3326
3327 i.op[x].regs = i.op[x].regs + 8;
773f551c 3328 }
29b0f896
AM		 3329 }
3330 }
773f551c 3331
7ab9ffdd 3332 if (i.rex != 0)
29b0f896
AM		 3333 add_prefix (REX_OPCODE | i.rex);
3334
3335 /* We are ready to output the insn. */
3336 output_insn ();
3337}
3338
3339static char *
e3bb37b5 3340parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3341{
3342 char *l = line;
3343 char *token_start = l;
3344 char *mnem_p;
5c6af06e 3345 int supported;
d3ce72d0 3346 const insn_template *t;
b6169b20 3347 char *dot_p = NULL;
29b0f896 3348
29b0f896
AM		 3349 while (1)
3350 {
3351 mnem_p = mnemonic;
3352 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3353 {
b6169b20
L		 3354 if (*mnem_p == '.')
3355 dot_p = mnem_p;
29b0f896
AM		 3356 mnem_p++;
3357 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3358 {
29b0f896
AM		 3359 as_bad (_("no such instruction: `%s'"), token_start);
3360 return NULL;
3361 }
3362 l++;
3363 }
3364 if (!is_space_char (*l)
3365 && *l != END_OF_INSN
e44823cf
JB		 3366 && (intel_syntax
3367 || (*l != PREFIX_SEPARATOR
3368 && *l != ',')))
29b0f896
AM		 3369 {
3370 as_bad (_("invalid character %s in mnemonic"),
3371 output_invalid (*l));
3372 return NULL;
3373 }
3374 if (token_start == l)
3375 {
e44823cf 3376 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3377 as_bad (_("expecting prefix; got nothing"));
3378 else
3379 as_bad (_("expecting mnemonic; got nothing"));
3380 return NULL;
3381 }
45288df1 3382
29b0f896 3383 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3384 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3385
29b0f896
AM		 3386 if (*l != END_OF_INSN
3387 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3388 && current_templates
40fb9820 3389 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3390 {
c6fb90c8 3391 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3392 {
3393 as_bad ((flag_code != CODE_64BIT
3394 ? _("`%s' is only supported in 64-bit mode")
3395 : _("`%s' is not supported in 64-bit mode")),
3396 current_templates->start->name);
3397 return NULL;
3398 }
29b0f896
AM		 3399 /* If we are in 16-bit mode, do not allow addr16 or data16.
3400 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3401 if ((current_templates->start->opcode_modifier.size16
3402 || current_templates->start->opcode_modifier.size32)
29b0f896 3403 && flag_code != CODE_64BIT
40fb9820 3404 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3405 ^ (flag_code == CODE_16BIT)))
3406 {
3407 as_bad (_("redundant %s prefix"),
3408 current_templates->start->name);
3409 return NULL;
45288df1 3410 }
29b0f896
AM		 3411 /* Add prefix, checking for repeated prefixes. */
3412 switch (add_prefix (current_templates->start->base_opcode))
3413 {
c32fa91d 3414 case PREFIX_EXIST:
29b0f896 3415 return NULL;
c32fa91d 3416 case PREFIX_REP:
42164a71 3417 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3418 i.hle_prefix = current_templates->start->name;
42164a71 3419 else
d5de92cf 3420 i.rep_prefix = current_templates->start->name;
29b0f896 3421 break;
c32fa91d
L		 3422 default:
3423 break;
29b0f896
AM		 3424 }
3425 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3426 token_start = ++l;
3427 }
3428 else
3429 break;
3430 }
45288df1 3431
30a55f88 3432 if (!current_templates)
b6169b20 3433 {
f8a5c266
L		 3434 /* Check if we should swap operand or force 32bit displacement in
3435 encoding. */
30a55f88
L		 3436 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3437 i.swap_operand = 1;
8d63c93e 3438 else if (mnem_p - 3 == dot_p
a501d77e
L		 3439 && dot_p[1] == 'd'
3440 && dot_p[2] == '8')
3441 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3442 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3443 && dot_p[1] == 'd'
3444 && dot_p[2] == '3'
3445 && dot_p[3] == '2')
a501d77e 3446 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3447 else
3448 goto check_suffix;
3449 mnem_p = dot_p;
3450 *dot_p = '\0';
d3ce72d0 3451 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3452 }
3453
29b0f896
AM		 3454 if (!current_templates)
3455 {
b6169b20 3456check_suffix:
29b0f896
AM		 3457 /* See if we can get a match by trimming off a suffix. */
3458 switch (mnem_p[-1])
3459 {
3460 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3461 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3462 i.suffix = SHORT_MNEM_SUFFIX;
3463 else
29b0f896
AM		 3464 case BYTE_MNEM_SUFFIX:
3465 case QWORD_MNEM_SUFFIX:
3466 i.suffix = mnem_p[-1];
3467 mnem_p[-1] = '\0';
d3ce72d0
NC		 3468 current_templates = (const templates *) hash_find (op_hash,
3469 mnemonic);
29b0f896
AM		 3470 break;
3471 case SHORT_MNEM_SUFFIX:
3472 case LONG_MNEM_SUFFIX:
3473 if (!intel_syntax)
3474 {
3475 i.suffix = mnem_p[-1];
3476 mnem_p[-1] = '\0';
d3ce72d0
NC		 3477 current_templates = (const templates *) hash_find (op_hash,
3478 mnemonic);
29b0f896
AM		 3479 }
3480 break;
252b5132 3481
29b0f896
AM		 3482 /* Intel Syntax. */
3483 case 'd':
3484 if (intel_syntax)
3485 {
9306ca4a 3486 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3487 i.suffix = SHORT_MNEM_SUFFIX;
3488 else
3489 i.suffix = LONG_MNEM_SUFFIX;
3490 mnem_p[-1] = '\0';
d3ce72d0
NC		 3491 current_templates = (const templates *) hash_find (op_hash,
3492 mnemonic);
29b0f896
AM		 3493 }
3494 break;
3495 }
3496 if (!current_templates)
3497 {
3498 as_bad (_("no such instruction: `%s'"), token_start);
3499 return NULL;
3500 }
3501 }
252b5132 3502
40fb9820
L		 3503 if (current_templates->start->opcode_modifier.jump
3504 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3505 {
3506 /* Check for a branch hint. We allow ",pt" and ",pn" for
3507 predict taken and predict not taken respectively.
3508 I'm not sure that branch hints actually do anything on loop
3509 and jcxz insns (JumpByte) for current Pentium4 chips. They
3510 may work in the future and it doesn't hurt to accept them
3511 now. */
3512 if (l[0] == ',' && l[1] == 'p')
3513 {
3514 if (l[2] == 't')
3515 {
3516 if (!add_prefix (DS_PREFIX_OPCODE))
3517 return NULL;
3518 l += 3;
3519 }
3520 else if (l[2] == 'n')
3521 {
3522 if (!add_prefix (CS_PREFIX_OPCODE))
3523 return NULL;
3524 l += 3;
3525 }
3526 }
3527 }
3528 /* Any other comma loses. */
3529 if (*l == ',')
3530 {
3531 as_bad (_("invalid character %s in mnemonic"),
3532 output_invalid (*l));
3533 return NULL;
3534 }
252b5132 3535
29b0f896 3536 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3537 supported = 0;
3538 for (t = current_templates->start; t < current_templates->end; ++t)
3539 {
c0f3af97
L		 3540 supported |= cpu_flags_match (t);
3541 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3542 goto skip;
5c6af06e 3543 }
3629bb00 3544
c0f3af97 3545 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3546 {
3547 as_bad (flag_code == CODE_64BIT
3548 ? _("`%s' is not supported in 64-bit mode")
3549 : _("`%s' is only supported in 64-bit mode"),
3550 current_templates->start->name);
3551 return NULL;
3552 }
c0f3af97 3553 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3554 {
3629bb00 3555 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3556 current_templates->start->name,
41aacd83 3557 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3558 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3559 return NULL;
29b0f896 3560 }
3629bb00
L		 3561
3562skip:
3563 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3564 && (flag_code != CODE_16BIT))
29b0f896
AM		 3565 {
3566 as_warn (_("use .code16 to ensure correct addressing mode"));
3567 }
252b5132 3568
29b0f896
AM		 3569 return l;
3570}
252b5132 3571
29b0f896 3572static char *
e3bb37b5 3573parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3574{
3575 char *token_start;
3138f287 3576
29b0f896
AM		 3577 /* 1 if operand is pending after ','. */
3578 unsigned int expecting_operand = 0;
252b5132 3579
29b0f896
AM		 3580 /* Non-zero if operand parens not balanced. */
3581 unsigned int paren_not_balanced;
3582
3583 while (*l != END_OF_INSN)
3584 {
3585 /* Skip optional white space before operand. */
3586 if (is_space_char (*l))
3587 ++l;
3588 if (!is_operand_char (*l) && *l != END_OF_INSN)
3589 {
3590 as_bad (_("invalid character %s before operand %d"),
3591 output_invalid (*l),
3592 i.operands + 1);
3593 return NULL;
3594 }
3595 token_start = l; /* after white space */
3596 paren_not_balanced = 0;
3597 while (paren_not_balanced || *l != ',')
3598 {
3599 if (*l == END_OF_INSN)
3600 {
3601 if (paren_not_balanced)
3602 {
3603 if (!intel_syntax)
3604 as_bad (_("unbalanced parenthesis in operand %d."),
3605 i.operands + 1);
3606 else
3607 as_bad (_("unbalanced brackets in operand %d."),
3608 i.operands + 1);
3609 return NULL;
3610 }
3611 else
3612 break; /* we are done */
3613 }
3614 else if (!is_operand_char (*l) && !is_space_char (*l))
3615 {
3616 as_bad (_("invalid character %s in operand %d"),
3617 output_invalid (*l),
3618 i.operands + 1);
3619 return NULL;
3620 }
3621 if (!intel_syntax)
3622 {
3623 if (*l == '(')
3624 ++paren_not_balanced;
3625 if (*l == ')')
3626 --paren_not_balanced;
3627 }
3628 else
3629 {
3630 if (*l == '[')
3631 ++paren_not_balanced;
3632 if (*l == ']')
3633 --paren_not_balanced;
3634 }
3635 l++;
3636 }
3637 if (l != token_start)
3638 { /* Yes, we've read in another operand. */
3639 unsigned int operand_ok;
3640 this_operand = i.operands++;
7d5e4556 3641 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3642 if (i.operands > MAX_OPERANDS)
3643 {
3644 as_bad (_("spurious operands; (%d operands/instruction max)"),
3645 MAX_OPERANDS);
3646 return NULL;
3647 }
3648 /* Now parse operand adding info to 'i' as we go along. */
3649 END_STRING_AND_SAVE (l);
3650
3651 if (intel_syntax)
3652 operand_ok =
3653 i386_intel_operand (token_start,
3654 intel_float_operand (mnemonic));
3655 else
a7619375 3656 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3657
3658 RESTORE_END_STRING (l);
3659 if (!operand_ok)
3660 return NULL;
3661 }
3662 else
3663 {
3664 if (expecting_operand)
3665 {
3666 expecting_operand_after_comma:
3667 as_bad (_("expecting operand after ','; got nothing"));
3668 return NULL;
3669 }
3670 if (*l == ',')
3671 {
3672 as_bad (_("expecting operand before ','; got nothing"));
3673 return NULL;
3674 }
3675 }
7f3f1ea2 3676
29b0f896
AM		 3677 /* Now *l must be either ',' or END_OF_INSN. */
3678 if (*l == ',')
3679 {
3680 if (*++l == END_OF_INSN)
3681 {
3682 /* Just skip it, if it's \n complain. */
3683 goto expecting_operand_after_comma;
3684 }
3685 expecting_operand = 1;
3686 }
3687 }
3688 return l;
3689}
7f3f1ea2 3690
050dfa73 3691static void
4d456e3d 3692swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3693{
3694 union i386_op temp_op;
40fb9820 3695 i386_operand_type temp_type;
050dfa73 3696 enum bfd_reloc_code_real temp_reloc;
4eed87de 3697
050dfa73
MM		 3698 temp_type = i.types[xchg2];
3699 i.types[xchg2] = i.types[xchg1];
3700 i.types[xchg1] = temp_type;
3701 temp_op = i.op[xchg2];
3702 i.op[xchg2] = i.op[xchg1];
3703 i.op[xchg1] = temp_op;
3704 temp_reloc = i.reloc[xchg2];
3705 i.reloc[xchg2] = i.reloc[xchg1];
3706 i.reloc[xchg1] = temp_reloc;
3707}
3708
29b0f896 3709static void
e3bb37b5 3710swap_operands (void)
29b0f896 3711{
b7c61d9a 3712 switch (i.operands)
050dfa73 3713 {
c0f3af97 3714 case 5:
b7c61d9a 3715 case 4:
4d456e3d 3716 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3717 case 3:
3718 case 2:
4d456e3d 3719 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3720 break;
3721 default:
3722 abort ();
29b0f896 3723 }
29b0f896
AM		 3724
3725 if (i.mem_operands == 2)
3726 {
3727 const seg_entry *temp_seg;
3728 temp_seg = i.seg[0];
3729 i.seg[0] = i.seg[1];
3730 i.seg[1] = temp_seg;
3731 }
3732}
252b5132 3733
29b0f896
AM		 3734/* Try to ensure constant immediates are represented in the smallest
3735 opcode possible. */
3736static void
e3bb37b5 3737optimize_imm (void)
29b0f896
AM		 3738{
3739 char guess_suffix = 0;
3740 int op;
252b5132 3741
29b0f896
AM		 3742 if (i.suffix)
3743 guess_suffix = i.suffix;
3744 else if (i.reg_operands)
3745 {
3746 /* Figure out a suffix from the last register operand specified.
3747 We can't do this properly yet, ie. excluding InOutPortReg,
3748 but the following works for instructions with immediates.
3749 In any case, we can't set i.suffix yet. */
3750 for (op = i.operands; --op >= 0;)
40fb9820 3751 if (i.types[op].bitfield.reg8)
7ab9ffdd 3752 {
40fb9820
L		 3753 guess_suffix = BYTE_MNEM_SUFFIX;
3754 break;
3755 }
3756 else if (i.types[op].bitfield.reg16)
252b5132 3757 {
40fb9820
L		 3758 guess_suffix = WORD_MNEM_SUFFIX;
3759 break;
3760 }
3761 else if (i.types[op].bitfield.reg32)
3762 {
3763 guess_suffix = LONG_MNEM_SUFFIX;
3764 break;
3765 }
3766 else if (i.types[op].bitfield.reg64)
3767 {
3768 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3769 break;
252b5132 3770 }
29b0f896
AM		 3771 }
3772 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3773 guess_suffix = WORD_MNEM_SUFFIX;
3774
3775 for (op = i.operands; --op >= 0;)
40fb9820 3776 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3777 {
3778 switch (i.op[op].imms->X_op)
252b5132 3779 {
29b0f896
AM		 3780 case O_constant:
3781 /* If a suffix is given, this operand may be shortened. */
3782 switch (guess_suffix)
252b5132 3783 {
29b0f896 3784 case LONG_MNEM_SUFFIX:
40fb9820
L		 3785 i.types[op].bitfield.imm32 = 1;
3786 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3787 break;
3788 case WORD_MNEM_SUFFIX:
40fb9820
L		 3789 i.types[op].bitfield.imm16 = 1;
3790 i.types[op].bitfield.imm32 = 1;
3791 i.types[op].bitfield.imm32s = 1;
3792 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3793 break;
3794 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3795 i.types[op].bitfield.imm8 = 1;
3796 i.types[op].bitfield.imm8s = 1;
3797 i.types[op].bitfield.imm16 = 1;
3798 i.types[op].bitfield.imm32 = 1;
3799 i.types[op].bitfield.imm32s = 1;
3800 i.types[op].bitfield.imm64 = 1;
29b0f896 3801 break;
252b5132 3802 }
252b5132 3803
29b0f896
AM		 3804 /* If this operand is at most 16 bits, convert it
3805 to a signed 16 bit number before trying to see
3806 whether it will fit in an even smaller size.
3807 This allows a 16-bit operand such as $0xffe0 to
3808 be recognised as within Imm8S range. */
40fb9820 3809 if ((i.types[op].bitfield.imm16)
29b0f896 3810 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3811 {
29b0f896
AM		 3812 i.op[op].imms->X_add_number =
3813 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3814 }
40fb9820 3815 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3816 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3817 == 0))
3818 {
3819 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3820 ^ ((offsetT) 1 << 31))
3821 - ((offsetT) 1 << 31));
3822 }
40fb9820 3823 i.types[op]
c6fb90c8
L		 3824 = operand_type_or (i.types[op],
3825 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3826
29b0f896
AM		 3827 /* We must avoid matching of Imm32 templates when 64bit
3828 only immediate is available. */
3829 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3830 i.types[op].bitfield.imm32 = 0;
29b0f896 3831 break;
252b5132 3832
29b0f896
AM		 3833 case O_absent:
3834 case O_register:
3835 abort ();
3836
3837 /* Symbols and expressions. */
3838 default:
9cd96992
JB		 3839 /* Convert symbolic operand to proper sizes for matching, but don't
3840 prevent matching a set of insns that only supports sizes other
3841 than those matching the insn suffix. */
3842 {
40fb9820 3843 i386_operand_type mask, allowed;
d3ce72d0 3844 const insn_template *t;
9cd96992 3845
0dfbf9d7
L		 3846 operand_type_set (&mask, 0);
3847 operand_type_set (&allowed, 0);
40fb9820 3848
4eed87de
AM		 3849 for (t = current_templates->start;
3850 t < current_templates->end;
3851 ++t)
c6fb90c8
L		 3852 allowed = operand_type_or (allowed,
3853 t->operand_types[op]);
9cd96992
JB		 3854 switch (guess_suffix)
3855 {
3856 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3857 mask.bitfield.imm64 = 1;
3858 mask.bitfield.imm32s = 1;
9cd96992
JB		 3859 break;
3860 case LONG_MNEM_SUFFIX:
40fb9820 3861 mask.bitfield.imm32 = 1;
9cd96992
JB		 3862 break;
3863 case WORD_MNEM_SUFFIX:
40fb9820 3864 mask.bitfield.imm16 = 1;
9cd96992
JB		 3865 break;
3866 case BYTE_MNEM_SUFFIX:
40fb9820 3867 mask.bitfield.imm8 = 1;
9cd96992
JB		 3868 break;
3869 default:
9cd96992
JB		 3870 break;
3871 }
c6fb90c8 3872 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3873 if (!operand_type_all_zero (&allowed))
c6fb90c8 3874 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3875 }
29b0f896 3876 break;
252b5132 3877 }
29b0f896
AM		 3878 }
3879}
47926f60 3880
29b0f896
AM		 3881/* Try to use the smallest displacement type too. */
3882static void
e3bb37b5 3883optimize_disp (void)
29b0f896
AM		 3884{
3885 int op;
3e73aa7c 3886
29b0f896 3887 for (op = i.operands; --op >= 0;)
40fb9820 3888 if (operand_type_check (i.types[op], disp))
252b5132 3889 {
b300c311 3890 if (i.op[op].disps->X_op == O_constant)
252b5132 3891 {
91d6fa6a 3892 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3893
40fb9820 3894 if (i.types[op].bitfield.disp16
91d6fa6a 3895 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3896 {
3897 /* If this operand is at most 16 bits, convert
3898 to a signed 16 bit number and don't use 64bit
3899 displacement. */
91d6fa6a 3900 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3901 i.types[op].bitfield.disp64 = 0;
b300c311 3902 }
40fb9820 3903 if (i.types[op].bitfield.disp32
91d6fa6a 3904 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3905 {
3906 /* If this operand is at most 32 bits, convert
3907 to a signed 32 bit number and don't use 64bit
3908 displacement. */
91d6fa6a
NC		 3909 op_disp &= (((offsetT) 2 << 31) - 1);
3910 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3911 i.types[op].bitfield.disp64 = 0;
b300c311 3912 }
91d6fa6a 3913 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3914 {
40fb9820
L		 3915 i.types[op].bitfield.disp8 = 0;
3916 i.types[op].bitfield.disp16 = 0;
3917 i.types[op].bitfield.disp32 = 0;
3918 i.types[op].bitfield.disp32s = 0;
3919 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3920 i.op[op].disps = 0;
3921 i.disp_operands--;
3922 }
3923 else if (flag_code == CODE_64BIT)
3924 {
91d6fa6a 3925 if (fits_in_signed_long (op_disp))
28a9d8f5 3926 {
40fb9820
L		 3927 i.types[op].bitfield.disp64 = 0;
3928 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3929 }
0e1147d9 3930 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3931 && fits_in_unsigned_long (op_disp))
40fb9820 3932 i.types[op].bitfield.disp32 = 1;
b300c311 3933 }
40fb9820
L		 3934 if ((i.types[op].bitfield.disp32
3935 || i.types[op].bitfield.disp32s
3936 || i.types[op].bitfield.disp16)
91d6fa6a 3937 && fits_in_signed_byte (op_disp))
40fb9820 3938 i.types[op].bitfield.disp8 = 1;
252b5132 3939 }
67a4f2b7
AO		 3940 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3941 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3942 {
3943 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3944 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3945 i.types[op].bitfield.disp8 = 0;
3946 i.types[op].bitfield.disp16 = 0;
3947 i.types[op].bitfield.disp32 = 0;
3948 i.types[op].bitfield.disp32s = 0;
3949 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3950 }
3951 else
b300c311 3952 /* We only support 64bit displacement on constants. */
40fb9820 3953 i.types[op].bitfield.disp64 = 0;
252b5132 3954 }
29b0f896
AM		 3955}
3956
6c30d220
L		 3957/* Check if operands are valid for the instruction. */
3958
3959static int
3960check_VecOperands (const insn_template *t)
3961{
3962 /* Without VSIB byte, we can't have a vector register for index. */
3963 if (!t->opcode_modifier.vecsib
3964 && i.index_reg
3965 && (i.index_reg->reg_type.bitfield.regxmm
3966 || i.index_reg->reg_type.bitfield.regymm))
3967 {
3968 i.error = unsupported_vector_index_register;
3969 return 1;
3970 }
3971
7bab8ab5
JB		 3972 /* For VSIB byte, we need a vector register for index, and all vector
3973 registers must be distinct. */
3974 if (t->opcode_modifier.vecsib)
3975 {
3976 if (!i.index_reg
6c30d220
L		 3977 || !((t->opcode_modifier.vecsib == VecSIB128
3978 && i.index_reg->reg_type.bitfield.regxmm)
3979 || (t->opcode_modifier.vecsib == VecSIB256
7bab8ab5
JB		 3980 && i.index_reg->reg_type.bitfield.regymm)))
3981 {
3982 i.error = invalid_vsib_address;
3983 return 1;
3984 }
3985
3986 gas_assert (i.reg_operands == 2);
3987 gas_assert (i.types[0].bitfield.regxmm
3988 || i.types[0].bitfield.regymm);
3989 gas_assert (i.types[2].bitfield.regxmm
3990 || i.types[2].bitfield.regymm);
3991
3992 if (operand_check == check_none)
3993 return 0;
3994 if (register_number (i.op[0].regs) != register_number (i.index_reg)
3995 && register_number (i.op[2].regs) != register_number (i.index_reg)
3996 && register_number (i.op[0].regs) != register_number (i.op[2].regs))
3997 return 0;
3998 if (operand_check == check_error)
3999 {
4000 i.error = invalid_vector_register_set;
4001 return 1;
4002 }
4003 as_warn (_("mask, index, and destination registers should be distinct"));
6c30d220
L		 4004 }
4005
4006 return 0;
4007}
4008
43f3e2ee 4009/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4010 operand types. */
4011
4012static int
4013VEX_check_operands (const insn_template *t)
4014{
4015 if (!t->opcode_modifier.vex)
4016 return 0;
4017
4018 /* Only check VEX_Imm4, which must be the first operand. */
4019 if (t->operand_types[0].bitfield.vec_imm4)
4020 {
4021 if (i.op[0].imms->X_op != O_constant
4022 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4023 {
a65babc9 4024 i.error = bad_imm4;
891edac4
L		 4025 return 1;
4026 }
a683cc34
SP		 4027
4028 /* Turn off Imm8 so that update_imm won't complain. */
4029 i.types[0] = vec_imm4;
4030 }
4031
4032 return 0;
4033}
4034
d3ce72d0 4035static const insn_template *
e3bb37b5 4036match_template (void)
29b0f896
AM		 4037{
4038 /* Points to template once we've found it. */
d3ce72d0 4039 const insn_template *t;
40fb9820 4040 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4041 i386_operand_type overlap4;
29b0f896 4042 unsigned int found_reverse_match;
40fb9820
L		 4043 i386_opcode_modifier suffix_check;
4044 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4045 int addr_prefix_disp;
a5c311ca 4046 unsigned int j;
3629bb00 4047 unsigned int found_cpu_match;
45664ddb 4048 unsigned int check_register;
5614d22c 4049 enum i386_error specific_error = 0;
29b0f896 4050
c0f3af97
L		 4051#if MAX_OPERANDS != 5
4052# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4053#endif
4054
29b0f896 4055 found_reverse_match = 0;
539e75ad 4056 addr_prefix_disp = -1;
40fb9820
L		 4057
4058 memset (&suffix_check, 0, sizeof (suffix_check));
4059 if (i.suffix == BYTE_MNEM_SUFFIX)
4060 suffix_check.no_bsuf = 1;
4061 else if (i.suffix == WORD_MNEM_SUFFIX)
4062 suffix_check.no_wsuf = 1;
4063 else if (i.suffix == SHORT_MNEM_SUFFIX)
4064 suffix_check.no_ssuf = 1;
4065 else if (i.suffix == LONG_MNEM_SUFFIX)
4066 suffix_check.no_lsuf = 1;
4067 else if (i.suffix == QWORD_MNEM_SUFFIX)
4068 suffix_check.no_qsuf = 1;
4069 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4070 suffix_check.no_ldsuf = 1;
29b0f896 4071
01559ecc
L		 4072 /* Must have right number of operands. */
4073 i.error = number_of_operands_mismatch;
4074
45aa61fe 4075 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4076 {
539e75ad
L		 4077 addr_prefix_disp = -1;
4078
29b0f896
AM		 4079 if (i.operands != t->operands)
4080 continue;
4081
50aecf8c 4082 /* Check processor support. */
a65babc9 4083 i.error = unsupported;
c0f3af97
L		 4084 found_cpu_match = (cpu_flags_match (t)
4085 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4086 if (!found_cpu_match)
4087 continue;
4088
e1d4d893 4089 /* Check old gcc support. */
a65babc9 4090 i.error = old_gcc_only;
e1d4d893
L		 4091 if (!old_gcc && t->opcode_modifier.oldgcc)
4092 continue;
4093
4094 /* Check AT&T mnemonic. */
a65babc9 4095 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4096 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4097 continue;
4098
891edac4 4099 /* Check AT&T/Intel syntax. */
a65babc9 4100 i.error = unsupported_syntax;
5c07affc
L		 4101 if ((intel_syntax && t->opcode_modifier.attsyntax)
4102 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4103 continue;
4104
20592a94 4105 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4106 i.error = invalid_instruction_suffix;
567e4e96
L		 4107 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4108 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4109 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4110 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4111 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4112 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4113 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4114 continue;
4115
5c07affc 4116 if (!operand_size_match (t))
7d5e4556 4117 continue;
539e75ad 4118
5c07affc
L		 4119 for (j = 0; j < MAX_OPERANDS; j++)
4120 operand_types[j] = t->operand_types[j];
4121
45aa61fe
AM		 4122 /* In general, don't allow 64-bit operands in 32-bit mode. */
4123 if (i.suffix == QWORD_MNEM_SUFFIX
4124 && flag_code != CODE_64BIT
4125 && (intel_syntax
40fb9820 4126 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4127 && !intel_float_operand (t->name))
4128 : intel_float_operand (t->name) != 2)
40fb9820 4129 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 4130 && !operand_types[0].bitfield.regxmm
4131 && !operand_types[0].bitfield.regymm)
40fb9820 4132 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 4133 && !!operand_types[t->operands > 1].bitfield.regxmm
4134 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 4135 && (t->base_opcode != 0x0fc7
4136 || t->extension_opcode != 1 /* cmpxchg8b */))
4137 continue;
4138
192dc9c6
JB		 4139 /* In general, don't allow 32-bit operands on pre-386. */
4140 else if (i.suffix == LONG_MNEM_SUFFIX
4141 && !cpu_arch_flags.bitfield.cpui386
4142 && (intel_syntax
4143 ? (!t->opcode_modifier.ignoresize
4144 && !intel_float_operand (t->name))
4145 : intel_float_operand (t->name) != 2)
4146 && ((!operand_types[0].bitfield.regmmx
4147 && !operand_types[0].bitfield.regxmm)
4148 || (!operand_types[t->operands > 1].bitfield.regmmx
4149 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4150 continue;
4151
29b0f896 4152 /* Do not verify operands when there are none. */
50aecf8c 4153 else
29b0f896 4154 {
c6fb90c8 4155 if (!t->operands)
2dbab7d5
L		 4156 /* We've found a match; break out of loop. */
4157 break;
29b0f896 4158 }
252b5132 4159
539e75ad
L		 4160 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4161 into Disp32/Disp16/Disp32 operand. */
4162 if (i.prefix[ADDR_PREFIX] != 0)
4163 {
40fb9820 4164 /* There should be only one Disp operand. */
539e75ad
L		 4165 switch (flag_code)
4166 {
4167 case CODE_16BIT:
40fb9820
L		 4168 for (j = 0; j < MAX_OPERANDS; j++)
4169 {
4170 if (operand_types[j].bitfield.disp16)
4171 {
4172 addr_prefix_disp = j;
4173 operand_types[j].bitfield.disp32 = 1;
4174 operand_types[j].bitfield.disp16 = 0;
4175 break;
4176 }
4177 }
539e75ad
L		 4178 break;
4179 case CODE_32BIT:
40fb9820
L		 4180 for (j = 0; j < MAX_OPERANDS; j++)
4181 {
4182 if (operand_types[j].bitfield.disp32)
4183 {
4184 addr_prefix_disp = j;
4185 operand_types[j].bitfield.disp32 = 0;
4186 operand_types[j].bitfield.disp16 = 1;
4187 break;
4188 }
4189 }
539e75ad
L		 4190 break;
4191 case CODE_64BIT:
40fb9820
L		 4192 for (j = 0; j < MAX_OPERANDS; j++)
4193 {
4194 if (operand_types[j].bitfield.disp64)
4195 {
4196 addr_prefix_disp = j;
4197 operand_types[j].bitfield.disp64 = 0;
4198 operand_types[j].bitfield.disp32 = 1;
4199 break;
4200 }
4201 }
539e75ad
L		 4202 break;
4203 }
539e75ad
L		 4204 }
4205
56ffb741
L		 4206 /* We check register size if needed. */
4207 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4208 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4209 switch (t->operands)
4210 {
4211 case 1:
40fb9820 4212 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4213 continue;
4214 break;
4215 case 2:
8b38ad71
L		 4216 /* xchg %eax, %eax is a special case. It is an aliase for nop
4217 only in 32bit mode and we can use opcode 0x90. In 64bit
4218 mode, we can't use 0x90 for xchg %eax, %eax since it should
4219 zero-extend %eax to %rax. */
4220 if (flag_code == CODE_64BIT
4221 && t->base_opcode == 0x90
0dfbf9d7
L		 4222 && operand_type_equal (&i.types [0], &acc32)
4223 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4224 continue;
b6169b20
L		 4225 if (i.swap_operand)
4226 {
4227 /* If we swap operand in encoding, we either match
4228 the next one or reverse direction of operands. */
4229 if (t->opcode_modifier.s)
4230 continue;
4231 else if (t->opcode_modifier.d)
4232 goto check_reverse;
4233 }
4234
29b0f896 4235 case 3:
fa99fab2
L		 4236 /* If we swap operand in encoding, we match the next one. */
4237 if (i.swap_operand && t->opcode_modifier.s)
4238 continue;
f48ff2ae 4239 case 4:
c0f3af97 4240 case 5:
c6fb90c8 4241 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4242 if (!operand_type_match (overlap0, i.types[0])
4243 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4244 || (check_register
4245 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4246 operand_types[0],
4247 overlap1, i.types[1],
4248 operand_types[1])))
29b0f896
AM		 4249 {
4250 /* Check if other direction is valid ... */
40fb9820 4251 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4252 continue;
4253
b6169b20 4254check_reverse:
29b0f896 4255 /* Try reversing direction of operands. */
c6fb90c8
L		 4256 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4257 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4258 if (!operand_type_match (overlap0, i.types[0])
4259 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4260 || (check_register
4261 && !operand_type_register_match (overlap0,
4262 i.types[0],
4263 operand_types[1],
4264 overlap1,
4265 i.types[1],
4266 operand_types[0])))
29b0f896
AM		 4267 {
4268 /* Does not match either direction. */
4269 continue;
4270 }
4271 /* found_reverse_match holds which of D or FloatDR
4272 we've found. */
40fb9820 4273 if (t->opcode_modifier.d)
8a2ed489 4274 found_reverse_match = Opcode_D;
40fb9820 4275 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4276 found_reverse_match = Opcode_FloatD;
4277 else
4278 found_reverse_match = 0;
40fb9820 4279 if (t->opcode_modifier.floatr)
8a2ed489 4280 found_reverse_match |= Opcode_FloatR;
29b0f896 4281 }
f48ff2ae 4282 else
29b0f896 4283 {
f48ff2ae 4284 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4285 switch (t->operands)
4286 {
c0f3af97
L		 4287 case 5:
4288 overlap4 = operand_type_and (i.types[4],
4289 operand_types[4]);
d1cbb4db 4290 case 4:
c6fb90c8
L		 4291 overlap3 = operand_type_and (i.types[3],
4292 operand_types[3]);
d1cbb4db 4293 case 3:
c6fb90c8
L		 4294 overlap2 = operand_type_and (i.types[2],
4295 operand_types[2]);
d1cbb4db
L		 4296 break;
4297 }
29b0f896 4298
f48ff2ae
L		 4299 switch (t->operands)
4300 {
c0f3af97
L		 4301 case 5:
4302 if (!operand_type_match (overlap4, i.types[4])
4303 || !operand_type_register_match (overlap3,
4304 i.types[3],
4305 operand_types[3],
4306 overlap4,
4307 i.types[4],
4308 operand_types[4]))
4309 continue;
f48ff2ae 4310 case 4:
40fb9820 4311 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4312 || (check_register
4313 && !operand_type_register_match (overlap2,
4314 i.types[2],
4315 operand_types[2],
4316 overlap3,
4317 i.types[3],
4318 operand_types[3])))
f48ff2ae
L		 4319 continue;
4320 case 3:
4321 /* Here we make use of the fact that there are no
4322 reverse match 3 operand instructions, and all 3
4323 operand instructions only need to be checked for
4324 register consistency between operands 2 and 3. */
40fb9820 4325 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4326 || (check_register
4327 && !operand_type_register_match (overlap1,
4328 i.types[1],
4329 operand_types[1],
4330 overlap2,
4331 i.types[2],
4332 operand_types[2])))
f48ff2ae
L		 4333 continue;
4334 break;
4335 }
29b0f896 4336 }
f48ff2ae 4337 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4338 slip through to break. */
4339 }
3629bb00 4340 if (!found_cpu_match)
29b0f896
AM		 4341 {
4342 found_reverse_match = 0;
4343 continue;
4344 }
c0f3af97 4345
5614d22c
JB		 4346 /* Check if vector and VEX operands are valid. */
4347 if (check_VecOperands (t) || VEX_check_operands (t))
4348 {
4349 specific_error = i.error;
4350 continue;
4351 }
a683cc34 4352
29b0f896
AM		 4353 /* We've found a match; break out of loop. */
4354 break;
4355 }
4356
4357 if (t == current_templates->end)
4358 {
4359 /* We found no match. */
a65babc9 4360 const char *err_msg;
5614d22c 4361 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4362 {
4363 default:
4364 abort ();
86e026a4 4365 case operand_size_mismatch:
a65babc9
L		 4366 err_msg = _("operand size mismatch");
4367 break;
4368 case operand_type_mismatch:
4369 err_msg = _("operand type mismatch");
4370 break;
4371 case register_type_mismatch:
4372 err_msg = _("register type mismatch");
4373 break;
4374 case number_of_operands_mismatch:
4375 err_msg = _("number of operands mismatch");
4376 break;
4377 case invalid_instruction_suffix:
4378 err_msg = _("invalid instruction suffix");
4379 break;
4380 case bad_imm4:
4a2608e3 4381 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4382 break;
4383 case old_gcc_only:
4384 err_msg = _("only supported with old gcc");
4385 break;
4386 case unsupported_with_intel_mnemonic:
4387 err_msg = _("unsupported with Intel mnemonic");
4388 break;
4389 case unsupported_syntax:
4390 err_msg = _("unsupported syntax");
4391 break;
4392 case unsupported:
35262a23 4393 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4394 current_templates->start->name);
4395 return NULL;
6c30d220
L		 4396 case invalid_vsib_address:
4397 err_msg = _("invalid VSIB address");
4398 break;
7bab8ab5
JB		 4399 case invalid_vector_register_set:
4400 err_msg = _("mask, index, and destination registers must be distinct");
4401 break;
6c30d220
L		 4402 case unsupported_vector_index_register:
4403 err_msg = _("unsupported vector index register");
4404 break;
a65babc9
L		 4405 }
4406 as_bad (_("%s for `%s'"), err_msg,
891edac4 4407 current_templates->start->name);
fa99fab2 4408 return NULL;
29b0f896 4409 }
252b5132 4410
29b0f896
AM		 4411 if (!quiet_warnings)
4412 {
4413 if (!intel_syntax
40fb9820
L		 4414 && (i.types[0].bitfield.jumpabsolute
4415 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4416 {
4417 as_warn (_("indirect %s without `*'"), t->name);
4418 }
4419
40fb9820
L		 4420 if (t->opcode_modifier.isprefix
4421 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4422 {
4423 /* Warn them that a data or address size prefix doesn't
4424 affect assembly of the next line of code. */
4425 as_warn (_("stand-alone `%s' prefix"), t->name);
4426 }
4427 }
4428
4429 /* Copy the template we found. */
4430 i.tm = *t;
539e75ad
L		 4431
4432 if (addr_prefix_disp != -1)
4433 i.tm.operand_types[addr_prefix_disp]
4434 = operand_types[addr_prefix_disp];
4435
29b0f896
AM		 4436 if (found_reverse_match)
4437 {
4438 /* If we found a reverse match we must alter the opcode
4439 direction bit. found_reverse_match holds bits to change
4440 (different for int & float insns). */
4441
4442 i.tm.base_opcode ^= found_reverse_match;
4443
539e75ad
L		 4444 i.tm.operand_types[0] = operand_types[1];
4445 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4446 }
4447
fa99fab2 4448 return t;
29b0f896
AM		 4449}
4450
4451static int
e3bb37b5 4452check_string (void)
29b0f896 4453{
40fb9820
L		 4454 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4455 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4456 {
4457 if (i.seg[0] != NULL && i.seg[0] != &es)
4458 {
a87af027 4459 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4460 i.tm.name,
a87af027
JB		 4461 mem_op + 1,
4462 register_prefix);
29b0f896
AM		 4463 return 0;
4464 }
4465 /* There's only ever one segment override allowed per instruction.
4466 This instruction possibly has a legal segment override on the
4467 second operand, so copy the segment to where non-string
4468 instructions store it, allowing common code. */
4469 i.seg[0] = i.seg[1];
4470 }
40fb9820 4471 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4472 {
4473 if (i.seg[1] != NULL && i.seg[1] != &es)
4474 {
a87af027 4475 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4476 i.tm.name,
a87af027
JB		 4477 mem_op + 2,
4478 register_prefix);
29b0f896
AM		 4479 return 0;
4480 }
4481 }
4482 return 1;
4483}
4484
4485static int
543613e9 4486process_suffix (void)
29b0f896
AM		 4487{
4488 /* If matched instruction specifies an explicit instruction mnemonic
4489 suffix, use it. */
40fb9820
L		 4490 if (i.tm.opcode_modifier.size16)
4491 i.suffix = WORD_MNEM_SUFFIX;
4492 else if (i.tm.opcode_modifier.size32)
4493 i.suffix = LONG_MNEM_SUFFIX;
4494 else if (i.tm.opcode_modifier.size64)
4495 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4496 else if (i.reg_operands)
4497 {
4498 /* If there's no instruction mnemonic suffix we try to invent one
4499 based on register operands. */
4500 if (!i.suffix)
4501 {
4502 /* We take i.suffix from the last register operand specified,
4503 Destination register type is more significant than source
381d071f
L		 4504 register type. crc32 in SSE4.2 prefers source register
4505 type. */
4506 if (i.tm.base_opcode == 0xf20f38f1)
4507 {
40fb9820
L		 4508 if (i.types[0].bitfield.reg16)
4509 i.suffix = WORD_MNEM_SUFFIX;
4510 else if (i.types[0].bitfield.reg32)
4511 i.suffix = LONG_MNEM_SUFFIX;
4512 else if (i.types[0].bitfield.reg64)
4513 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4514 }
9344ff29 4515 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4516 {
40fb9820 4517 if (i.types[0].bitfield.reg8)
20592a94
L		 4518 i.suffix = BYTE_MNEM_SUFFIX;
4519 }
381d071f
L		 4520
4521 if (!i.suffix)
4522 {
4523 int op;
4524
20592a94
L		 4525 if (i.tm.base_opcode == 0xf20f38f1
4526 || i.tm.base_opcode == 0xf20f38f0)
4527 {
4528 /* We have to know the operand size for crc32. */
4529 as_bad (_("ambiguous memory operand size for `%s`"),
4530 i.tm.name);
4531 return 0;
4532 }
4533
381d071f 4534 for (op = i.operands; --op >= 0;)
40fb9820 4535 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4536 {
40fb9820
L		 4537 if (i.types[op].bitfield.reg8)
4538 {
4539 i.suffix = BYTE_MNEM_SUFFIX;
4540 break;
4541 }
4542 else if (i.types[op].bitfield.reg16)
4543 {
4544 i.suffix = WORD_MNEM_SUFFIX;
4545 break;
4546 }
4547 else if (i.types[op].bitfield.reg32)
4548 {
4549 i.suffix = LONG_MNEM_SUFFIX;
4550 break;
4551 }
4552 else if (i.types[op].bitfield.reg64)
4553 {
4554 i.suffix = QWORD_MNEM_SUFFIX;
4555 break;
4556 }
381d071f
L		 4557 }
4558 }
29b0f896
AM		 4559 }
4560 else if (i.suffix == BYTE_MNEM_SUFFIX)
4561 {
2eb952a4
L		 4562 if (intel_syntax
4563 && i.tm.opcode_modifier.ignoresize
4564 && i.tm.opcode_modifier.no_bsuf)
4565 i.suffix = 0;
4566 else if (!check_byte_reg ())
29b0f896
AM		 4567 return 0;
4568 }
4569 else if (i.suffix == LONG_MNEM_SUFFIX)
4570 {
2eb952a4
L		 4571 if (intel_syntax
4572 && i.tm.opcode_modifier.ignoresize
4573 && i.tm.opcode_modifier.no_lsuf)
4574 i.suffix = 0;
4575 else if (!check_long_reg ())
29b0f896
AM		 4576 return 0;
4577 }
4578 else if (i.suffix == QWORD_MNEM_SUFFIX)
4579 {
955e1e6a
L		 4580 if (intel_syntax
4581 && i.tm.opcode_modifier.ignoresize
4582 && i.tm.opcode_modifier.no_qsuf)
4583 i.suffix = 0;
4584 else if (!check_qword_reg ())
29b0f896
AM		 4585 return 0;
4586 }
4587 else if (i.suffix == WORD_MNEM_SUFFIX)
4588 {
2eb952a4
L		 4589 if (intel_syntax
4590 && i.tm.opcode_modifier.ignoresize
4591 && i.tm.opcode_modifier.no_wsuf)
4592 i.suffix = 0;
4593 else if (!check_word_reg ())
29b0f896
AM		 4594 return 0;
4595 }
c0f3af97
L		 4596 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4597 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4598 {
c0f3af97 4599 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4600 should check if it is a valid suffix. */
4601 }
40fb9820 4602 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4603 /* Do nothing if the instruction is going to ignore the prefix. */
4604 ;
4605 else
4606 abort ();
4607 }
40fb9820 4608 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4609 && !i.suffix
4610 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4611 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4612 {
4613 i.suffix = stackop_size;
4614 }
9306ca4a
JB		 4615 else if (intel_syntax
4616 && !i.suffix
40fb9820
L		 4617 && (i.tm.operand_types[0].bitfield.jumpabsolute
4618 || i.tm.opcode_modifier.jumpbyte
4619 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4620 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4621 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4622 {
4623 switch (flag_code)
4624 {
4625 case CODE_64BIT:
40fb9820 4626 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4627 {
4628 i.suffix = QWORD_MNEM_SUFFIX;
4629 break;
4630 }
4631 case CODE_32BIT:
40fb9820 4632 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4633 i.suffix = LONG_MNEM_SUFFIX;
4634 break;
4635 case CODE_16BIT:
40fb9820 4636 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4637 i.suffix = WORD_MNEM_SUFFIX;
4638 break;
4639 }
4640 }
252b5132 4641
9306ca4a 4642 if (!i.suffix)
29b0f896 4643 {
9306ca4a
JB		 4644 if (!intel_syntax)
4645 {
40fb9820 4646 if (i.tm.opcode_modifier.w)
9306ca4a 4647 {
4eed87de
AM		 4648 as_bad (_("no instruction mnemonic suffix given and "
4649 "no register operands; can't size instruction"));
9306ca4a
JB		 4650 return 0;
4651 }
4652 }
4653 else
4654 {
40fb9820 4655 unsigned int suffixes;
7ab9ffdd 4656
40fb9820
L		 4657 suffixes = !i.tm.opcode_modifier.no_bsuf;
4658 if (!i.tm.opcode_modifier.no_wsuf)
4659 suffixes |= 1 << 1;
4660 if (!i.tm.opcode_modifier.no_lsuf)
4661 suffixes |= 1 << 2;
fc4adea1 4662 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4663 suffixes |= 1 << 3;
4664 if (!i.tm.opcode_modifier.no_ssuf)
4665 suffixes |= 1 << 4;
4666 if (!i.tm.opcode_modifier.no_qsuf)
4667 suffixes |= 1 << 5;
4668
4669 /* There are more than suffix matches. */
4670 if (i.tm.opcode_modifier.w
9306ca4a 4671 || ((suffixes & (suffixes - 1))
40fb9820
L		 4672 && !i.tm.opcode_modifier.defaultsize
4673 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4674 {
4675 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4676 return 0;
4677 }
4678 }
29b0f896 4679 }
252b5132 4680
9306ca4a
JB		 4681 /* Change the opcode based on the operand size given by i.suffix;
4682 We don't need to change things for byte insns. */
4683
582d5edd
L		 4684 if (i.suffix
4685 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4686 && i.suffix != XMMWORD_MNEM_SUFFIX
4687 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4688 {
4689 /* It's not a byte, select word/dword operation. */
40fb9820 4690 if (i.tm.opcode_modifier.w)
29b0f896 4691 {
40fb9820 4692 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4693 i.tm.base_opcode |= 8;
4694 else
4695 i.tm.base_opcode |= 1;
4696 }
0f3f3d8b 4697
29b0f896
AM		 4698 /* Now select between word & dword operations via the operand
4699 size prefix, except for instructions that will ignore this
4700 prefix anyway. */
ca61edf2 4701 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4702 {
ca61edf2
L		 4703 /* The address size override prefix changes the size of the
4704 first operand. */
40fb9820
L		 4705 if ((flag_code == CODE_32BIT
4706 && i.op->regs[0].reg_type.bitfield.reg16)
4707 || (flag_code != CODE_32BIT
4708 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4709 if (!add_prefix (ADDR_PREFIX_OPCODE))
4710 return 0;
4711 }
4712 else if (i.suffix != QWORD_MNEM_SUFFIX
4713 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4714 && !i.tm.opcode_modifier.ignoresize
4715 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4716 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4717 || (flag_code == CODE_64BIT
40fb9820 4718 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4719 {
4720 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4721
40fb9820 4722 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4723 prefix = ADDR_PREFIX_OPCODE;
252b5132 4724
29b0f896
AM		 4725 if (!add_prefix (prefix))
4726 return 0;
24eab124 4727 }
252b5132 4728
29b0f896
AM		 4729 /* Set mode64 for an operand. */
4730 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4731 && flag_code == CODE_64BIT
40fb9820 4732 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4733 {
4734 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4735 need rex64. cmpxchg8b is also a special case. */
4736 if (! (i.operands == 2
4737 && i.tm.base_opcode == 0x90
4738 && i.tm.extension_opcode == None
0dfbf9d7
L		 4739 && operand_type_equal (&i.types [0], &acc64)
4740 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4741 && ! (i.operands == 1
4742 && i.tm.base_opcode == 0xfc7
4743 && i.tm.extension_opcode == 1
40fb9820
L		 4744 && !operand_type_check (i.types [0], reg)
4745 && operand_type_check (i.types [0], anymem)))
f6bee062 4746 i.rex |= REX_W;
46e883c5 4747 }
3e73aa7c 4748
29b0f896
AM		 4749 /* Size floating point instruction. */
4750 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4751 if (i.tm.opcode_modifier.floatmf)
543613e9 4752 i.tm.base_opcode ^= 4;
29b0f896 4753 }
7ecd2f8b 4754
29b0f896
AM		 4755 return 1;
4756}
3e73aa7c 4757
29b0f896 4758static int
543613e9 4759check_byte_reg (void)
29b0f896
AM		 4760{
4761 int op;
543613e9 4762
29b0f896
AM		 4763 for (op = i.operands; --op >= 0;)
4764 {
4765 /* If this is an eight bit register, it's OK. If it's the 16 or
4766 32 bit version of an eight bit register, we will just use the
4767 low portion, and that's OK too. */
40fb9820 4768 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4769 continue;
4770
5a819eb9
JB		 4771 /* I/O port address operands are OK too. */
4772 if (i.tm.operand_types[op].bitfield.inoutportreg)
4773 continue;
4774
9344ff29
L		 4775 /* crc32 doesn't generate this warning. */
4776 if (i.tm.base_opcode == 0xf20f38f0)
4777 continue;
4778
40fb9820
L		 4779 if ((i.types[op].bitfield.reg16
4780 || i.types[op].bitfield.reg32
4781 || i.types[op].bitfield.reg64)
5a819eb9
JB		 4782 && i.op[op].regs->reg_num < 4
4783 /* Prohibit these changes in 64bit mode, since the lowering
4784 would be more complicated. */
4785 && flag_code != CODE_64BIT)
29b0f896 4786 {
29b0f896 4787#if REGISTER_WARNINGS
5a819eb9 4788 if (!quiet_warnings)
a540244d
L		 4789 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4790 register_prefix,
40fb9820 4791 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4792 ? REGNAM_AL - REGNAM_AX
4793 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4794 register_prefix,
29b0f896
AM		 4795 i.op[op].regs->reg_name,
4796 i.suffix);
4797#endif
4798 continue;
4799 }
4800 /* Any other register is bad. */
40fb9820
L		 4801 if (i.types[op].bitfield.reg16
4802 || i.types[op].bitfield.reg32
4803 || i.types[op].bitfield.reg64
4804 || i.types[op].bitfield.regmmx
4805 || i.types[op].bitfield.regxmm
c0f3af97 4806 || i.types[op].bitfield.regymm
40fb9820
L		 4807 || i.types[op].bitfield.sreg2
4808 || i.types[op].bitfield.sreg3
4809 || i.types[op].bitfield.control
4810 || i.types[op].bitfield.debug
4811 || i.types[op].bitfield.test
4812 || i.types[op].bitfield.floatreg
4813 || i.types[op].bitfield.floatacc)
29b0f896 4814 {
a540244d
L		 4815 as_bad (_("`%s%s' not allowed with `%s%c'"),
4816 register_prefix,
29b0f896
AM		 4817 i.op[op].regs->reg_name,
4818 i.tm.name,
4819 i.suffix);
4820 return 0;
4821 }
4822 }
4823 return 1;
4824}
4825
4826static int
e3bb37b5 4827check_long_reg (void)
29b0f896
AM		 4828{
4829 int op;
4830
4831 for (op = i.operands; --op >= 0;)
4832 /* Reject eight bit registers, except where the template requires
4833 them. (eg. movzb) */
40fb9820
L		 4834 if (i.types[op].bitfield.reg8
4835 && (i.tm.operand_types[op].bitfield.reg16
4836 || i.tm.operand_types[op].bitfield.reg32
4837 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4838 {
a540244d
L		 4839 as_bad (_("`%s%s' not allowed with `%s%c'"),
4840 register_prefix,
29b0f896
AM		 4841 i.op[op].regs->reg_name,
4842 i.tm.name,
4843 i.suffix);
4844 return 0;
4845 }
4846 /* Warn if the e prefix on a general reg is missing. */
4847 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4848 && i.types[op].bitfield.reg16
4849 && (i.tm.operand_types[op].bitfield.reg32
4850 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4851 {
4852 /* Prohibit these changes in the 64bit mode, since the
4853 lowering is more complicated. */
4854 if (flag_code == CODE_64BIT)
252b5132 4855 {
2b5d6a91 4856 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4857 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4858 i.suffix);
4859 return 0;
252b5132 4860 }
29b0f896
AM		 4861#if REGISTER_WARNINGS
4862 else
a540244d
L		 4863 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4864 register_prefix,
29b0f896 4865 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4866 register_prefix,
29b0f896
AM		 4867 i.op[op].regs->reg_name,
4868 i.suffix);
4869#endif
252b5132 4870 }
29b0f896 4871 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4872 else if (i.types[op].bitfield.reg64
4873 && (i.tm.operand_types[op].bitfield.reg32
4874 || i.tm.operand_types[op].bitfield.acc))
252b5132 4875 {
34828aad 4876 if (intel_syntax
ca61edf2 4877 && i.tm.opcode_modifier.toqword
40fb9820 4878 && !i.types[0].bitfield.regxmm)
34828aad 4879 {
ca61edf2 4880 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4881 i.suffix = QWORD_MNEM_SUFFIX;
4882 }
4883 else
4884 {
2b5d6a91 4885 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4886 register_prefix, i.op[op].regs->reg_name,
4887 i.suffix);
4888 return 0;
4889 }
29b0f896
AM		 4890 }
4891 return 1;
4892}
252b5132 4893
29b0f896 4894static int
e3bb37b5 4895check_qword_reg (void)
29b0f896
AM		 4896{
4897 int op;
252b5132 4898
29b0f896
AM		 4899 for (op = i.operands; --op >= 0; )
4900 /* Reject eight bit registers, except where the template requires
4901 them. (eg. movzb) */
40fb9820
L		 4902 if (i.types[op].bitfield.reg8
4903 && (i.tm.operand_types[op].bitfield.reg16
4904 || i.tm.operand_types[op].bitfield.reg32
4905 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4906 {
a540244d
L		 4907 as_bad (_("`%s%s' not allowed with `%s%c'"),
4908 register_prefix,
29b0f896
AM		 4909 i.op[op].regs->reg_name,
4910 i.tm.name,
4911 i.suffix);
4912 return 0;
4913 }
4914 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4915 else if ((i.types[op].bitfield.reg16
4916 || i.types[op].bitfield.reg32)
4917 && (i.tm.operand_types[op].bitfield.reg32
4918 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4919 {
4920 /* Prohibit these changes in the 64bit mode, since the
4921 lowering is more complicated. */
34828aad 4922 if (intel_syntax
ca61edf2 4923 && i.tm.opcode_modifier.todword
40fb9820 4924 && !i.types[0].bitfield.regxmm)
34828aad 4925 {
ca61edf2 4926 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4927 i.suffix = LONG_MNEM_SUFFIX;
4928 }
4929 else
4930 {
2b5d6a91 4931 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4932 register_prefix, i.op[op].regs->reg_name,
4933 i.suffix);
4934 return 0;
4935 }
252b5132 4936 }
29b0f896
AM		 4937 return 1;
4938}
252b5132 4939
29b0f896 4940static int
e3bb37b5 4941check_word_reg (void)
29b0f896
AM		 4942{
4943 int op;
4944 for (op = i.operands; --op >= 0;)
4945 /* Reject eight bit registers, except where the template requires
4946 them. (eg. movzb) */
40fb9820
L		 4947 if (i.types[op].bitfield.reg8
4948 && (i.tm.operand_types[op].bitfield.reg16
4949 || i.tm.operand_types[op].bitfield.reg32
4950 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4951 {
a540244d
L		 4952 as_bad (_("`%s%s' not allowed with `%s%c'"),
4953 register_prefix,
29b0f896
AM		 4954 i.op[op].regs->reg_name,
4955 i.tm.name,
4956 i.suffix);
4957 return 0;
4958 }
4959 /* Warn if the e prefix on a general reg is present. */
4960 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4961 && i.types[op].bitfield.reg32
4962 && (i.tm.operand_types[op].bitfield.reg16
4963 || i.tm.operand_types[op].bitfield.acc))
252b5132 4964 {
29b0f896
AM		 4965 /* Prohibit these changes in the 64bit mode, since the
4966 lowering is more complicated. */
4967 if (flag_code == CODE_64BIT)
252b5132 4968 {
2b5d6a91 4969 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4970 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4971 i.suffix);
4972 return 0;
252b5132 4973 }
29b0f896
AM		 4974 else
4975#if REGISTER_WARNINGS
a540244d
L		 4976 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4977 register_prefix,
29b0f896 4978 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4979 register_prefix,
29b0f896
AM		 4980 i.op[op].regs->reg_name,
4981 i.suffix);
4982#endif
4983 }
4984 return 1;
4985}
252b5132 4986
29b0f896 4987static int
40fb9820 4988update_imm (unsigned int j)
29b0f896 4989{
bc0844ae 4990 i386_operand_type overlap = i.types[j];
40fb9820
L		 4991 if ((overlap.bitfield.imm8
4992 || overlap.bitfield.imm8s
4993 || overlap.bitfield.imm16
4994 || overlap.bitfield.imm32
4995 || overlap.bitfield.imm32s
4996 || overlap.bitfield.imm64)
0dfbf9d7
L		 4997 && !operand_type_equal (&overlap, &imm8)
4998 && !operand_type_equal (&overlap, &imm8s)
4999 && !operand_type_equal (&overlap, &imm16)
5000 && !operand_type_equal (&overlap, &imm32)
5001 && !operand_type_equal (&overlap, &imm32s)
5002 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5003 {
5004 if (i.suffix)
5005 {
40fb9820
L		 5006 i386_operand_type temp;
5007
0dfbf9d7 5008 operand_type_set (&temp, 0);
7ab9ffdd 5009 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5010 {
5011 temp.bitfield.imm8 = overlap.bitfield.imm8;
5012 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5013 }
5014 else if (i.suffix == WORD_MNEM_SUFFIX)
5015 temp.bitfield.imm16 = overlap.bitfield.imm16;
5016 else if (i.suffix == QWORD_MNEM_SUFFIX)
5017 {
5018 temp.bitfield.imm64 = overlap.bitfield.imm64;
5019 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5020 }
5021 else
5022 temp.bitfield.imm32 = overlap.bitfield.imm32;
5023 overlap = temp;
29b0f896 5024 }
0dfbf9d7
L		 5025 else if (operand_type_equal (&overlap, &imm16_32_32s)
5026 || operand_type_equal (&overlap, &imm16_32)
5027 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5028 {
40fb9820 5029 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5030 overlap = imm16;
40fb9820 5031 else
65da13b5 5032 overlap = imm32s;
29b0f896 5033 }
0dfbf9d7
L		 5034 if (!operand_type_equal (&overlap, &imm8)
5035 && !operand_type_equal (&overlap, &imm8s)
5036 && !operand_type_equal (&overlap, &imm16)
5037 && !operand_type_equal (&overlap, &imm32)
5038 && !operand_type_equal (&overlap, &imm32s)
5039 && !operand_type_equal (&overlap, &imm64))
29b0f896 5040 {
4eed87de
AM		 5041 as_bad (_("no instruction mnemonic suffix given; "
5042 "can't determine immediate size"));
29b0f896
AM		 5043 return 0;
5044 }
5045 }
40fb9820 5046 i.types[j] = overlap;
29b0f896 5047
40fb9820
L		 5048 return 1;
5049}
5050
5051static int
5052finalize_imm (void)
5053{
bc0844ae 5054 unsigned int j, n;
29b0f896 5055
bc0844ae
L		 5056 /* Update the first 2 immediate operands. */
5057 n = i.operands > 2 ? 2 : i.operands;
5058 if (n)
5059 {
5060 for (j = 0; j < n; j++)
5061 if (update_imm (j) == 0)
5062 return 0;
40fb9820 5063
bc0844ae
L		 5064 /* The 3rd operand can't be immediate operand. */
5065 gas_assert (operand_type_check (i.types[2], imm) == 0);
5066 }
29b0f896
AM		 5067
5068 return 1;
5069}
5070
c0f3af97
L		 5071static int
5072bad_implicit_operand (int xmm)
5073{
91d6fa6a
NC		 5074 const char *ireg = xmm ? "xmm0" : "ymm0";
5075
c0f3af97
L		 5076 if (intel_syntax)
5077 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5078 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5079 else
5080 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5081 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5082 return 0;
5083}
5084
29b0f896 5085static int
e3bb37b5 5086process_operands (void)
29b0f896
AM		 5087{
5088 /* Default segment register this instruction will use for memory
5089 accesses. 0 means unknown. This is only for optimizing out
5090 unnecessary segment overrides. */
5091 const seg_entry *default_seg = 0;
5092
2426c15f 5093 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5094 {
91d6fa6a
NC		 5095 unsigned int dupl = i.operands;
5096 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5097 unsigned int j;
5098
c0f3af97 5099 /* The destination must be an xmm register. */
9c2799c2 5100 gas_assert (i.reg_operands
91d6fa6a 5101 && MAX_OPERANDS > dupl
7ab9ffdd 5102 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5103
5104 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5105 {
c0f3af97 5106 /* The first operand is implicit and must be xmm0. */
9c2799c2 5107 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5108 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5109 return bad_implicit_operand (1);
5110
8cd7925b 5111 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5112 {
5113 /* Keep xmm0 for instructions with VEX prefix and 3
5114 sources. */
5115 goto duplicate;
5116 }
e2ec9d29 5117 else
c0f3af97
L		 5118 {
5119 /* We remove the first xmm0 and keep the number of
5120 operands unchanged, which in fact duplicates the
5121 destination. */
5122 for (j = 1; j < i.operands; j++)
5123 {
5124 i.op[j - 1] = i.op[j];
5125 i.types[j - 1] = i.types[j];
5126 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5127 }
5128 }
5129 }
5130 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5131 {
91d6fa6a 5132 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5133 && (i.tm.opcode_modifier.vexsources
5134 == VEX3SOURCES));
c0f3af97
L		 5135
5136 /* Add the implicit xmm0 for instructions with VEX prefix
5137 and 3 sources. */
5138 for (j = i.operands; j > 0; j--)
5139 {
5140 i.op[j] = i.op[j - 1];
5141 i.types[j] = i.types[j - 1];
5142 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5143 }
5144 i.op[0].regs
5145 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5146 i.types[0] = regxmm;
c0f3af97
L		 5147 i.tm.operand_types[0] = regxmm;
5148
5149 i.operands += 2;
5150 i.reg_operands += 2;
5151 i.tm.operands += 2;
5152
91d6fa6a 5153 dupl++;
c0f3af97 5154 dest++;
91d6fa6a
NC		 5155 i.op[dupl] = i.op[dest];
5156 i.types[dupl] = i.types[dest];
5157 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5158 }
c0f3af97
L		 5159 else
5160 {
5161duplicate:
5162 i.operands++;
5163 i.reg_operands++;
5164 i.tm.operands++;
5165
91d6fa6a
NC		 5166 i.op[dupl] = i.op[dest];
5167 i.types[dupl] = i.types[dest];
5168 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5169 }
5170
5171 if (i.tm.opcode_modifier.immext)
5172 process_immext ();
5173 }
5174 else if (i.tm.opcode_modifier.firstxmm0)
5175 {
5176 unsigned int j;
5177
5178 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 5179 gas_assert (i.reg_operands
7ab9ffdd
L		 5180 && (operand_type_equal (&i.types[0], &regxmm)
5181 || operand_type_equal (&i.types[0], &regymm)));
4c692bc7 5182 if (register_number (i.op[0].regs) != 0)
c0f3af97 5183 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5184
5185 for (j = 1; j < i.operands; j++)
5186 {
5187 i.op[j - 1] = i.op[j];
5188 i.types[j - 1] = i.types[j];
5189
5190 /* We need to adjust fields in i.tm since they are used by
5191 build_modrm_byte. */
5192 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5193 }
5194
e2ec9d29
L		 5195 i.operands--;
5196 i.reg_operands--;
e2ec9d29
L		 5197 i.tm.operands--;
5198 }
5199 else if (i.tm.opcode_modifier.regkludge)
5200 {
5201 /* The imul $imm, %reg instruction is converted into
5202 imul $imm, %reg, %reg, and the clr %reg instruction
5203 is converted into xor %reg, %reg. */
5204
5205 unsigned int first_reg_op;
5206
5207 if (operand_type_check (i.types[0], reg))
5208 first_reg_op = 0;
5209 else
5210 first_reg_op = 1;
5211 /* Pretend we saw the extra register operand. */
9c2799c2 5212 gas_assert (i.reg_operands == 1
7ab9ffdd 5213 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5214 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5215 i.types[first_reg_op + 1] = i.types[first_reg_op];
5216 i.operands++;
5217 i.reg_operands++;
29b0f896
AM		 5218 }
5219
40fb9820 5220 if (i.tm.opcode_modifier.shortform)
29b0f896 5221 {
40fb9820
L		 5222 if (i.types[0].bitfield.sreg2
5223 || i.types[0].bitfield.sreg3)
29b0f896 5224 {
4eed87de
AM		 5225 if (i.tm.base_opcode == POP_SEG_SHORT
5226 && i.op[0].regs->reg_num == 1)
29b0f896 5227 {
a87af027 5228 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5229 return 0;
29b0f896 5230 }
4eed87de
AM		 5231 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5232 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5233 i.rex |= REX_B;
4eed87de
AM		 5234 }
5235 else
5236 {
7ab9ffdd 5237 /* The register or float register operand is in operand
85f10a01 5238 0 or 1. */
40fb9820 5239 unsigned int op;
7ab9ffdd
L		 5240
5241 if (i.types[0].bitfield.floatreg
5242 || operand_type_check (i.types[0], reg))
5243 op = 0;
5244 else
5245 op = 1;
4eed87de
AM		 5246 /* Register goes in low 3 bits of opcode. */
5247 i.tm.base_opcode |= i.op[op].regs->reg_num;
5248 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5249 i.rex |= REX_B;
40fb9820 5250 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5251 {
4eed87de
AM		 5252 /* Warn about some common errors, but press on regardless.
5253 The first case can be generated by gcc (<= 2.8.1). */
5254 if (i.operands == 2)
5255 {
5256 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5257 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5258 register_prefix, i.op[!intel_syntax].regs->reg_name,
5259 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5260 }
5261 else
5262 {
5263 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5264 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5265 register_prefix, i.op[0].regs->reg_name);
4eed87de 5266 }
29b0f896
AM		 5267 }
5268 }
5269 }
40fb9820 5270 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5271 {
5272 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5273 must be put into the modrm byte). Now, we make the modrm and
5274 index base bytes based on all the info we've collected. */
29b0f896
AM		 5275
5276 default_seg = build_modrm_byte ();
5277 }
8a2ed489 5278 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5279 {
5280 default_seg = &ds;
5281 }
40fb9820 5282 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5283 {
5284 /* For the string instructions that allow a segment override
5285 on one of their operands, the default segment is ds. */
5286 default_seg = &ds;
5287 }
5288
75178d9d
L		 5289 if (i.tm.base_opcode == 0x8d /* lea */
5290 && i.seg[0]
5291 && !quiet_warnings)
30123838 5292 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5293
5294 /* If a segment was explicitly specified, and the specified segment
5295 is not the default, use an opcode prefix to select it. If we
5296 never figured out what the default segment is, then default_seg
5297 will be zero at this point, and the specified segment prefix will
5298 always be used. */
29b0f896
AM		 5299 if ((i.seg[0]) && (i.seg[0] != default_seg))
5300 {
5301 if (!add_prefix (i.seg[0]->seg_prefix))
5302 return 0;
5303 }
5304 return 1;
5305}
5306
5307static const seg_entry *
e3bb37b5 5308build_modrm_byte (void)
29b0f896
AM		 5309{
5310 const seg_entry *default_seg = 0;
c0f3af97 5311 unsigned int source, dest;
8cd7925b 5312 int vex_3_sources;
c0f3af97
L		 5313
5314 /* The first operand of instructions with VEX prefix and 3 sources
5315 must be VEX_Imm4. */
8cd7925b 5316 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5317 if (vex_3_sources)
5318 {
91d6fa6a 5319 unsigned int nds, reg_slot;
4c2c6516 5320 expressionS *exp;
c0f3af97 5321
922d8de8 5322 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5323 && i.tm.opcode_modifier.immext)
5324 {
5325 dest = i.operands - 2;
5326 gas_assert (dest == 3);
5327 }
922d8de8 5328 else
a683cc34 5329 dest = i.operands - 1;
c0f3af97 5330 nds = dest - 1;
922d8de8 5331
a683cc34
SP		 5332 /* There are 2 kinds of instructions:
5333 1. 5 operands: 4 register operands or 3 register operands
5334 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5335 VexW0 or VexW1. The destination must be either XMM or YMM
5336 register.
5337 2. 4 operands: 4 register operands or 3 register operands
5338 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5339 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5340 || (i.reg_operands == 3 && i.mem_operands == 1))
5341 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5342 && (i.tm.opcode_modifier.veximmext
5343 || (i.imm_operands == 1
5344 && i.types[0].bitfield.vec_imm4
5345 && (i.tm.opcode_modifier.vexw == VEXW0
5346 || i.tm.opcode_modifier.vexw == VEXW1)
5347 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5348 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5349
5350 if (i.imm_operands == 0)
5351 {
5352 /* When there is no immediate operand, generate an 8bit
5353 immediate operand to encode the first operand. */
5354 exp = &im_expressions[i.imm_operands++];
5355 i.op[i.operands].imms = exp;
5356 i.types[i.operands] = imm8;
5357 i.operands++;
5358 /* If VexW1 is set, the first operand is the source and
5359 the second operand is encoded in the immediate operand. */
5360 if (i.tm.opcode_modifier.vexw == VEXW1)
5361 {
5362 source = 0;
5363 reg_slot = 1;
5364 }
5365 else
5366 {
5367 source = 1;
5368 reg_slot = 0;
5369 }
5370
5371 /* FMA swaps REG and NDS. */
5372 if (i.tm.cpu_flags.bitfield.cpufma)
5373 {
5374 unsigned int tmp;
5375 tmp = reg_slot;
5376 reg_slot = nds;
5377 nds = tmp;
5378 }
5379
24981e7b
L		 5380 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5381 &regxmm)
a683cc34
SP		 5382 || operand_type_equal (&i.tm.operand_types[reg_slot],
5383 &regymm));
5384 exp->X_op = O_constant;
4c692bc7 5385 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
a683cc34 5386 }
922d8de8 5387 else
a683cc34
SP		 5388 {
5389 unsigned int imm_slot;
5390
5391 if (i.tm.opcode_modifier.vexw == VEXW0)
5392 {
5393 /* If VexW0 is set, the third operand is the source and
5394 the second operand is encoded in the immediate
5395 operand. */
5396 source = 2;
5397 reg_slot = 1;
5398 }
5399 else
5400 {
5401 /* VexW1 is set, the second operand is the source and
5402 the third operand is encoded in the immediate
5403 operand. */
5404 source = 1;
5405 reg_slot = 2;
5406 }
5407
5408 if (i.tm.opcode_modifier.immext)
5409 {
5410 /* When ImmExt is set, the immdiate byte is the last
5411 operand. */
5412 imm_slot = i.operands - 1;
5413 source--;
5414 reg_slot--;
5415 }
5416 else
5417 {
5418 imm_slot = 0;
5419
5420 /* Turn on Imm8 so that output_imm will generate it. */
5421 i.types[imm_slot].bitfield.imm8 = 1;
5422 }
5423
24981e7b
L		 5424 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5425 &regxmm)
5426 || operand_type_equal (&i.tm.operand_types[reg_slot],
5427 &regymm));
a683cc34 5428 i.op[imm_slot].imms->X_add_number
4c692bc7 5429 |= register_number (i.op[reg_slot].regs) << 4;
a683cc34
SP		 5430 }
5431
5432 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5433 || operand_type_equal (&i.tm.operand_types[nds],
5434 &regymm));
dae39acc 5435 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5436 }
5437 else
5438 source = dest = 0;
29b0f896
AM		 5439
5440 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5441 implicit registers do not count. If there are 3 register
5442 operands, it must be a instruction with VexNDS. For a
5443 instruction with VexNDD, the destination register is encoded
5444 in VEX prefix. If there are 4 register operands, it must be
5445 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5446 if (i.mem_operands == 0
5447 && ((i.reg_operands == 2
2426c15f 5448 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5449 || (i.reg_operands == 3
2426c15f 5450 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5451 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5452 {
cab737b9
L		 5453 switch (i.operands)
5454 {
5455 case 2:
5456 source = 0;
5457 break;
5458 case 3:
c81128dc
L		 5459 /* When there are 3 operands, one of them may be immediate,
5460 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5461 the first operand must be shift count register (cl) or it
5462 is an instruction with VexNDS. */
9c2799c2 5463 gas_assert (i.imm_operands == 1
7ab9ffdd 5464 || (i.imm_operands == 0
2426c15f 5465 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5466 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5467 if (operand_type_check (i.types[0], imm)
5468 || i.types[0].bitfield.shiftcount)
5469 source = 1;
5470 else
5471 source = 0;
cab737b9
L		 5472 break;
5473 case 4:
368d64cc
L		 5474 /* When there are 4 operands, the first two must be 8bit
5475 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5476 one.
5477
5478 For instructions with VexNDS, if the first operand
5479 an imm8, the source operand is the 2nd one. If the last
5480 operand is imm8, the source operand is the first one. */
9c2799c2 5481 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5482 && i.types[0].bitfield.imm8
5483 && i.types[1].bitfield.imm8)
2426c15f 5484 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5485 && i.imm_operands == 1
5486 && (i.types[0].bitfield.imm8
5487 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5488 if (i.imm_operands == 2)
5489 source = 2;
5490 else
c0f3af97
L		 5491 {
5492 if (i.types[0].bitfield.imm8)
5493 source = 1;
5494 else
5495 source = 0;
5496 }
c0f3af97
L		 5497 break;
5498 case 5:
cab737b9
L		 5499 break;
5500 default:
5501 abort ();
5502 }
5503
c0f3af97
L		 5504 if (!vex_3_sources)
5505 {
5506 dest = source + 1;
5507
2426c15f 5508 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5509 {
5510 /* For instructions with VexNDS, the register-only
f12dc422
L		 5511 source operand must be 32/64bit integer, XMM or
5512 YMM register. It is encoded in VEX prefix. We
5513 need to clear RegMem bit before calling
5514 operand_type_equal. */
5515
5516 i386_operand_type op;
5517 unsigned int vvvv;
5518
5519 /* Check register-only source operand when two source
5520 operands are swapped. */
5521 if (!i.tm.operand_types[source].bitfield.baseindex
5522 && i.tm.operand_types[dest].bitfield.baseindex)
5523 {
5524 vvvv = source;
5525 source = dest;
5526 }
5527 else
5528 vvvv = dest;
5529
5530 op = i.tm.operand_types[vvvv];
fa99fab2 5531 op.bitfield.regmem = 0;
c0f3af97 5532 if ((dest + 1) >= i.operands
f12dc422
L		 5533 || (op.bitfield.reg32 != 1
5534 && !op.bitfield.reg64 != 1
5535 && !operand_type_equal (&op, &regxmm)
fa99fab2 5536 && !operand_type_equal (&op, &regymm)))
c0f3af97 5537 abort ();
f12dc422 5538 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5539 dest++;
5540 }
5541 }
29b0f896
AM		 5542
5543 i.rm.mode = 3;
5544 /* One of the register operands will be encoded in the i.tm.reg
5545 field, the other in the combined i.tm.mode and i.tm.regmem
5546 fields. If no form of this instruction supports a memory
5547 destination operand, then we assume the source operand may
5548 sometimes be a memory operand and so we need to store the
5549 destination in the i.rm.reg field. */
40fb9820
L		 5550 if (!i.tm.operand_types[dest].bitfield.regmem
5551 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5552 {
5553 i.rm.reg = i.op[dest].regs->reg_num;
5554 i.rm.regmem = i.op[source].regs->reg_num;
5555 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5556 i.rex |= REX_R;
29b0f896 5557 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5558 i.rex |= REX_B;
29b0f896
AM		 5559 }
5560 else
5561 {
5562 i.rm.reg = i.op[source].regs->reg_num;
5563 i.rm.regmem = i.op[dest].regs->reg_num;
5564 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5565 i.rex |= REX_B;
29b0f896 5566 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5567 i.rex |= REX_R;
29b0f896 5568 }
161a04f6 5569 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5570 {
40fb9820
L		 5571 if (!i.types[0].bitfield.control
5572 && !i.types[1].bitfield.control)
c4a530c5 5573 abort ();
161a04f6 5574 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5575 add_prefix (LOCK_PREFIX_OPCODE);
5576 }
29b0f896
AM		 5577 }
5578 else
5579 { /* If it's not 2 reg operands... */
c0f3af97
L		 5580 unsigned int mem;
5581
29b0f896
AM		 5582 if (i.mem_operands)
5583 {
5584 unsigned int fake_zero_displacement = 0;
99018f42 5585 unsigned int op;
4eed87de 5586
7ab9ffdd
L		 5587 for (op = 0; op < i.operands; op++)
5588 if (operand_type_check (i.types[op], anymem))
5589 break;
7ab9ffdd 5590 gas_assert (op < i.operands);
29b0f896 5591
6c30d220
L		 5592 if (i.tm.opcode_modifier.vecsib)
5593 {
5594 if (i.index_reg->reg_num == RegEiz
5595 || i.index_reg->reg_num == RegRiz)
5596 abort ();
5597
5598 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5599 if (!i.base_reg)
5600 {
5601 i.sib.base = NO_BASE_REGISTER;
5602 i.sib.scale = i.log2_scale_factor;
5603 i.types[op].bitfield.disp8 = 0;
5604 i.types[op].bitfield.disp16 = 0;
5605 i.types[op].bitfield.disp64 = 0;
5606 if (flag_code != CODE_64BIT)
5607 {
5608 /* Must be 32 bit */
5609 i.types[op].bitfield.disp32 = 1;
5610 i.types[op].bitfield.disp32s = 0;
5611 }
5612 else
5613 {
5614 i.types[op].bitfield.disp32 = 0;
5615 i.types[op].bitfield.disp32s = 1;
5616 }
5617 }
5618 i.sib.index = i.index_reg->reg_num;
5619 if ((i.index_reg->reg_flags & RegRex) != 0)
5620 i.rex |= REX_X;
5621 }
5622
29b0f896
AM		 5623 default_seg = &ds;
5624
5625 if (i.base_reg == 0)
5626 {
5627 i.rm.mode = 0;
5628 if (!i.disp_operands)
6c30d220
L		 5629 {
5630 fake_zero_displacement = 1;
5631 /* Instructions with VSIB byte need 32bit displacement
5632 if there is no base register. */
5633 if (i.tm.opcode_modifier.vecsib)
5634 i.types[op].bitfield.disp32 = 1;
5635 }
29b0f896
AM		 5636 if (i.index_reg == 0)
5637 {
6c30d220 5638 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5639 /* Operand is just <disp> */
20f0a1fc 5640 if (flag_code == CODE_64BIT)
29b0f896
AM		 5641 {
5642 /* 64bit mode overwrites the 32bit absolute
5643 addressing by RIP relative addressing and
5644 absolute addressing is encoded by one of the
5645 redundant SIB forms. */
5646 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5647 i.sib.base = NO_BASE_REGISTER;
5648 i.sib.index = NO_INDEX_REGISTER;
fc225355 5649 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5650 ? disp32s : disp32);
20f0a1fc 5651 }
fc225355
L		 5652 else if ((flag_code == CODE_16BIT)
5653 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5654 {
5655 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5656 i.types[op] = disp16;
20f0a1fc
NC		 5657 }
5658 else
5659 {
5660 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5661 i.types[op] = disp32;
29b0f896
AM		 5662 }
5663 }
6c30d220 5664 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5665 {
6c30d220 5666 /* !i.base_reg && i.index_reg */
db51cc60
L		 5667 if (i.index_reg->reg_num == RegEiz
5668 || i.index_reg->reg_num == RegRiz)
5669 i.sib.index = NO_INDEX_REGISTER;
5670 else
5671 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5672 i.sib.base = NO_BASE_REGISTER;
5673 i.sib.scale = i.log2_scale_factor;
5674 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5675 i.types[op].bitfield.disp8 = 0;
5676 i.types[op].bitfield.disp16 = 0;
5677 i.types[op].bitfield.disp64 = 0;
29b0f896 5678 if (flag_code != CODE_64BIT)
40fb9820
L		 5679 {
5680 /* Must be 32 bit */
5681 i.types[op].bitfield.disp32 = 1;
5682 i.types[op].bitfield.disp32s = 0;
5683 }
29b0f896 5684 else
40fb9820
L		 5685 {
5686 i.types[op].bitfield.disp32 = 0;
5687 i.types[op].bitfield.disp32s = 1;
5688 }
29b0f896 5689 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5690 i.rex |= REX_X;
29b0f896
AM		 5691 }
5692 }
5693 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5694 else if (i.base_reg->reg_num == RegRip ||
5695 i.base_reg->reg_num == RegEip)
29b0f896 5696 {
6c30d220 5697 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5698 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5699 i.types[op].bitfield.disp8 = 0;
5700 i.types[op].bitfield.disp16 = 0;
5701 i.types[op].bitfield.disp32 = 0;
5702 i.types[op].bitfield.disp32s = 1;
5703 i.types[op].bitfield.disp64 = 0;
71903a11 5704 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5705 if (! i.disp_operands)
5706 fake_zero_displacement = 1;
29b0f896 5707 }
40fb9820 5708 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 5709 {
6c30d220 5710 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5711 switch (i.base_reg->reg_num)
5712 {
5713 case 3: /* (%bx) */
5714 if (i.index_reg == 0)
5715 i.rm.regmem = 7;
5716 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5717 i.rm.regmem = i.index_reg->reg_num - 6;
5718 break;
5719 case 5: /* (%bp) */
5720 default_seg = &ss;
5721 if (i.index_reg == 0)
5722 {
5723 i.rm.regmem = 6;
40fb9820 5724 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5725 {
5726 /* fake (%bp) into 0(%bp) */
40fb9820 5727 i.types[op].bitfield.disp8 = 1;
252b5132 5728 fake_zero_displacement = 1;
29b0f896
AM		 5729 }
5730 }
5731 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5732 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5733 break;
5734 default: /* (%si) -> 4 or (%di) -> 5 */
5735 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5736 }
5737 i.rm.mode = mode_from_disp_size (i.types[op]);
5738 }
5739 else /* i.base_reg and 32/64 bit mode */
5740 {
5741 if (flag_code == CODE_64BIT
40fb9820
L		 5742 && operand_type_check (i.types[op], disp))
5743 {
5744 i386_operand_type temp;
0dfbf9d7 5745 operand_type_set (&temp, 0);
40fb9820
L		 5746 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5747 i.types[op] = temp;
5748 if (i.prefix[ADDR_PREFIX] == 0)
5749 i.types[op].bitfield.disp32s = 1;
5750 else
5751 i.types[op].bitfield.disp32 = 1;
5752 }
20f0a1fc 5753
6c30d220
L		 5754 if (!i.tm.opcode_modifier.vecsib)
5755 i.rm.regmem = i.base_reg->reg_num;
29b0f896 5756 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5757 i.rex |= REX_B;
29b0f896
AM		 5758 i.sib.base = i.base_reg->reg_num;
5759 /* x86-64 ignores REX prefix bit here to avoid decoder
5760 complications. */
848930b2
JB		 5761 if (!(i.base_reg->reg_flags & RegRex)
5762 && (i.base_reg->reg_num == EBP_REG_NUM
5763 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 5764 default_seg = &ss;
848930b2 5765 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 5766 {
848930b2
JB		 5767 fake_zero_displacement = 1;
5768 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5769 }
5770 i.sib.scale = i.log2_scale_factor;
5771 if (i.index_reg == 0)
5772 {
6c30d220 5773 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5774 /* <disp>(%esp) becomes two byte modrm with no index
5775 register. We've already stored the code for esp
5776 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5777 Any base register besides %esp will not use the
5778 extra modrm byte. */
5779 i.sib.index = NO_INDEX_REGISTER;
29b0f896 5780 }
6c30d220 5781 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5782 {
db51cc60
L		 5783 if (i.index_reg->reg_num == RegEiz
5784 || i.index_reg->reg_num == RegRiz)
5785 i.sib.index = NO_INDEX_REGISTER;
5786 else
5787 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5788 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5789 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5790 i.rex |= REX_X;
29b0f896 5791 }
67a4f2b7
AO		 5792
5793 if (i.disp_operands
5794 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5795 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5796 i.rm.mode = 0;
5797 else
a501d77e
L		 5798 {
5799 if (!fake_zero_displacement
5800 && !i.disp_operands
5801 && i.disp_encoding)
5802 {
5803 fake_zero_displacement = 1;
5804 if (i.disp_encoding == disp_encoding_8bit)
5805 i.types[op].bitfield.disp8 = 1;
5806 else
5807 i.types[op].bitfield.disp32 = 1;
5808 }
5809 i.rm.mode = mode_from_disp_size (i.types[op]);
5810 }
29b0f896 5811 }
252b5132 5812
29b0f896
AM		 5813 if (fake_zero_displacement)
5814 {
5815 /* Fakes a zero displacement assuming that i.types[op]
5816 holds the correct displacement size. */
5817 expressionS *exp;
5818
9c2799c2 5819 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5820 exp = &disp_expressions[i.disp_operands++];
5821 i.op[op].disps = exp;
5822 exp->X_op = O_constant;
5823 exp->X_add_number = 0;
5824 exp->X_add_symbol = (symbolS *) 0;
5825 exp->X_op_symbol = (symbolS *) 0;
5826 }
c0f3af97
L		 5827
5828 mem = op;
29b0f896 5829 }
c0f3af97
L		 5830 else
5831 mem = ~0;
252b5132 5832
8c43a48b 5833 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5834 {
5835 if (operand_type_check (i.types[0], imm))
5836 i.vex.register_specifier = NULL;
5837 else
5838 {
5839 /* VEX.vvvv encodes one of the sources when the first
5840 operand is not an immediate. */
1ef99a7b 5841 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5842 i.vex.register_specifier = i.op[0].regs;
5843 else
5844 i.vex.register_specifier = i.op[1].regs;
5845 }
5846
5847 /* Destination is a XMM register encoded in the ModRM.reg
5848 and VEX.R bit. */
5849 i.rm.reg = i.op[2].regs->reg_num;
5850 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5851 i.rex |= REX_R;
5852
5853 /* ModRM.rm and VEX.B encodes the other source. */
5854 if (!i.mem_operands)
5855 {
5856 i.rm.mode = 3;
5857
1ef99a7b 5858 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5859 i.rm.regmem = i.op[1].regs->reg_num;
5860 else
5861 i.rm.regmem = i.op[0].regs->reg_num;
5862
5863 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5864 i.rex |= REX_B;
5865 }
5866 }
2426c15f 5867 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5868 {
5869 i.vex.register_specifier = i.op[2].regs;
5870 if (!i.mem_operands)
5871 {
5872 i.rm.mode = 3;
5873 i.rm.regmem = i.op[1].regs->reg_num;
5874 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5875 i.rex |= REX_B;
5876 }
5877 }
29b0f896
AM		 5878 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5879 (if any) based on i.tm.extension_opcode. Again, we must be
5880 careful to make sure that segment/control/debug/test/MMX
5881 registers are coded into the i.rm.reg field. */
f88c9eb0 5882 else if (i.reg_operands)
29b0f896 5883 {
99018f42 5884 unsigned int op;
7ab9ffdd
L		 5885 unsigned int vex_reg = ~0;
5886
5887 for (op = 0; op < i.operands; op++)
5888 if (i.types[op].bitfield.reg8
5889 || i.types[op].bitfield.reg16
5890 || i.types[op].bitfield.reg32
5891 || i.types[op].bitfield.reg64
5892 || i.types[op].bitfield.regmmx
5893 || i.types[op].bitfield.regxmm
5894 || i.types[op].bitfield.regymm
5895 || i.types[op].bitfield.sreg2
5896 || i.types[op].bitfield.sreg3
5897 || i.types[op].bitfield.control
5898 || i.types[op].bitfield.debug
5899 || i.types[op].bitfield.test)
5900 break;
c0209578 5901
7ab9ffdd
L		 5902 if (vex_3_sources)
5903 op = dest;
2426c15f 5904 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5905 {
5906 /* For instructions with VexNDS, the register-only
5907 source operand is encoded in VEX prefix. */
5908 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5909
7ab9ffdd 5910 if (op > mem)
c0f3af97 5911 {
7ab9ffdd
L		 5912 vex_reg = op++;
5913 gas_assert (op < i.operands);
c0f3af97
L		 5914 }
5915 else
c0f3af97 5916 {
f12dc422
L		 5917 /* Check register-only source operand when two source
5918 operands are swapped. */
5919 if (!i.tm.operand_types[op].bitfield.baseindex
5920 && i.tm.operand_types[op + 1].bitfield.baseindex)
5921 {
5922 vex_reg = op;
5923 op += 2;
5924 gas_assert (mem == (vex_reg + 1)
5925 && op < i.operands);
5926 }
5927 else
5928 {
5929 vex_reg = op + 1;
5930 gas_assert (vex_reg < i.operands);
5931 }
c0f3af97 5932 }
7ab9ffdd 5933 }
2426c15f 5934 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5935 {
f12dc422 5936 /* For instructions with VexNDD, the register destination
7ab9ffdd 5937 is encoded in VEX prefix. */
f12dc422
L		 5938 if (i.mem_operands == 0)
5939 {
5940 /* There is no memory operand. */
5941 gas_assert ((op + 2) == i.operands);
5942 vex_reg = op + 1;
5943 }
5944 else
8d63c93e 5945 {
f12dc422
L		 5946 /* There are only 2 operands. */
5947 gas_assert (op < 2 && i.operands == 2);
5948 vex_reg = 1;
5949 }
7ab9ffdd
L		 5950 }
5951 else
5952 gas_assert (op < i.operands);
99018f42 5953
7ab9ffdd
L		 5954 if (vex_reg != (unsigned int) ~0)
5955 {
f12dc422 5956 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5957
f12dc422
L		 5958 if (type->bitfield.reg32 != 1
5959 && type->bitfield.reg64 != 1
5960 && !operand_type_equal (type, &regxmm)
5961 && !operand_type_equal (type, &regymm))
7ab9ffdd 5962 abort ();
f88c9eb0 5963
7ab9ffdd
L		 5964 i.vex.register_specifier = i.op[vex_reg].regs;
5965 }
5966
1b9f0c97
L		 5967 /* Don't set OP operand twice. */
5968 if (vex_reg != op)
7ab9ffdd 5969 {
1b9f0c97
L		 5970 /* If there is an extension opcode to put here, the
5971 register number must be put into the regmem field. */
5972 if (i.tm.extension_opcode != None)
5973 {
5974 i.rm.regmem = i.op[op].regs->reg_num;
5975 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5976 i.rex |= REX_B;
5977 }
5978 else
5979 {
5980 i.rm.reg = i.op[op].regs->reg_num;
5981 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5982 i.rex |= REX_R;
5983 }
7ab9ffdd 5984 }
252b5132 5985
29b0f896
AM		 5986 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5987 must set it to 3 to indicate this is a register operand
5988 in the regmem field. */
5989 if (!i.mem_operands)
5990 i.rm.mode = 3;
5991 }
252b5132 5992
29b0f896 5993 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5994 if (i.tm.extension_opcode != None)
29b0f896
AM		 5995 i.rm.reg = i.tm.extension_opcode;
5996 }
5997 return default_seg;
5998}
252b5132 5999
29b0f896 6000static void
e3bb37b5 6001output_branch (void)
29b0f896
AM		 6002{
6003 char *p;
f8a5c266 6004 int size;
29b0f896
AM		 6005 int code16;
6006 int prefix;
6007 relax_substateT subtype;
6008 symbolS *sym;
6009 offsetT off;
6010
f8a5c266 6011 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6012 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6013
6014 prefix = 0;
6015 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6016 {
29b0f896
AM		 6017 prefix = 1;
6018 i.prefixes -= 1;
6019 code16 ^= CODE16;
252b5132 6020 }
29b0f896
AM		 6021 /* Pentium4 branch hints. */
6022 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6023 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6024 {
29b0f896
AM		 6025 prefix++;
6026 i.prefixes--;
6027 }
6028 if (i.prefix[REX_PREFIX] != 0)
6029 {
6030 prefix++;
6031 i.prefixes--;
2f66722d
AM		 6032 }
6033
29b0f896
AM		 6034 if (i.prefixes != 0 && !intel_syntax)
6035 as_warn (_("skipping prefixes on this instruction"));
6036
6037 /* It's always a symbol; End frag & setup for relax.
6038 Make sure there is enough room in this frag for the largest
6039 instruction we may generate in md_convert_frag. This is 2
6040 bytes for the opcode and room for the prefix and largest
6041 displacement. */
6042 frag_grow (prefix + 2 + 4);
6043 /* Prefix and 1 opcode byte go in fr_fix. */
6044 p = frag_more (prefix + 1);
6045 if (i.prefix[DATA_PREFIX] != 0)
6046 *p++ = DATA_PREFIX_OPCODE;
6047 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6048 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6049 *p++ = i.prefix[SEG_PREFIX];
6050 if (i.prefix[REX_PREFIX] != 0)
6051 *p++ = i.prefix[REX_PREFIX];
6052 *p = i.tm.base_opcode;
6053
6054 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6055 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6056 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6057 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6058 else
f8a5c266 6059 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6060 subtype |= code16;
3e73aa7c 6061
29b0f896
AM		 6062 sym = i.op[0].disps->X_add_symbol;
6063 off = i.op[0].disps->X_add_number;
3e73aa7c 6064
29b0f896
AM		 6065 if (i.op[0].disps->X_op != O_constant
6066 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6067 {
29b0f896
AM		 6068 /* Handle complex expressions. */
6069 sym = make_expr_symbol (i.op[0].disps);
6070 off = 0;
6071 }
3e73aa7c 6072
29b0f896
AM		 6073 /* 1 possible extra opcode + 4 byte displacement go in var part.
6074 Pass reloc in fr_var. */
6075 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
6076}
3e73aa7c 6077
29b0f896 6078static void
e3bb37b5 6079output_jump (void)
29b0f896
AM		 6080{
6081 char *p;
6082 int size;
3e02c1cc 6083 fixS *fixP;
29b0f896 6084
40fb9820 6085 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6086 {
6087 /* This is a loop or jecxz type instruction. */
6088 size = 1;
6089 if (i.prefix[ADDR_PREFIX] != 0)
6090 {
6091 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6092 i.prefixes -= 1;
6093 }
6094 /* Pentium4 branch hints. */
6095 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6096 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6097 {
6098 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6099 i.prefixes--;
3e73aa7c
JH		 6100 }
6101 }
29b0f896
AM		 6102 else
6103 {
6104 int code16;
3e73aa7c 6105
29b0f896
AM		 6106 code16 = 0;
6107 if (flag_code == CODE_16BIT)
6108 code16 = CODE16;
3e73aa7c 6109
29b0f896
AM		 6110 if (i.prefix[DATA_PREFIX] != 0)
6111 {
6112 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6113 i.prefixes -= 1;
6114 code16 ^= CODE16;
6115 }
252b5132 6116
29b0f896
AM		 6117 size = 4;
6118 if (code16)
6119 size = 2;
6120 }
9fcc94b6 6121
29b0f896
AM		 6122 if (i.prefix[REX_PREFIX] != 0)
6123 {
6124 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6125 i.prefixes -= 1;
6126 }
252b5132 6127
29b0f896
AM		 6128 if (i.prefixes != 0 && !intel_syntax)
6129 as_warn (_("skipping prefixes on this instruction"));
e0890092 6130
42164a71
L		 6131 p = frag_more (i.tm.opcode_length + size);
6132 switch (i.tm.opcode_length)
6133 {
6134 case 2:
6135 *p++ = i.tm.base_opcode >> 8;
6136 case 1:
6137 *p++ = i.tm.base_opcode;
6138 break;
6139 default:
6140 abort ();
6141 }
e0890092 6142
3e02c1cc
AM		 6143 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6144 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6145
6146 /* All jumps handled here are signed, but don't use a signed limit
6147 check for 32 and 16 bit jumps as we want to allow wrap around at
6148 4G and 64k respectively. */
6149 if (size == 1)
6150 fixP->fx_signed = 1;
29b0f896 6151}
e0890092 6152
29b0f896 6153static void
e3bb37b5 6154output_interseg_jump (void)
29b0f896
AM		 6155{
6156 char *p;
6157 int size;
6158 int prefix;
6159 int code16;
252b5132 6160
29b0f896
AM		 6161 code16 = 0;
6162 if (flag_code == CODE_16BIT)
6163 code16 = CODE16;
a217f122 6164
29b0f896
AM		 6165 prefix = 0;
6166 if (i.prefix[DATA_PREFIX] != 0)
6167 {
6168 prefix = 1;
6169 i.prefixes -= 1;
6170 code16 ^= CODE16;
6171 }
6172 if (i.prefix[REX_PREFIX] != 0)
6173 {
6174 prefix++;
6175 i.prefixes -= 1;
6176 }
252b5132 6177
29b0f896
AM		 6178 size = 4;
6179 if (code16)
6180 size = 2;
252b5132 6181
29b0f896
AM		 6182 if (i.prefixes != 0 && !intel_syntax)
6183 as_warn (_("skipping prefixes on this instruction"));
252b5132 6184
29b0f896
AM		 6185 /* 1 opcode; 2 segment; offset */
6186 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6187
29b0f896
AM		 6188 if (i.prefix[DATA_PREFIX] != 0)
6189 *p++ = DATA_PREFIX_OPCODE;
252b5132 6190
29b0f896
AM		 6191 if (i.prefix[REX_PREFIX] != 0)
6192 *p++ = i.prefix[REX_PREFIX];
252b5132 6193
29b0f896
AM		 6194 *p++ = i.tm.base_opcode;
6195 if (i.op[1].imms->X_op == O_constant)
6196 {
6197 offsetT n = i.op[1].imms->X_add_number;
252b5132 6198
29b0f896
AM		 6199 if (size == 2
6200 && !fits_in_unsigned_word (n)
6201 && !fits_in_signed_word (n))
6202 {
6203 as_bad (_("16-bit jump out of range"));
6204 return;
6205 }
6206 md_number_to_chars (p, n, size);
6207 }
6208 else
6209 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6210 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6211 if (i.op[0].imms->X_op != O_constant)
6212 as_bad (_("can't handle non absolute segment in `%s'"),
6213 i.tm.name);
6214 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6215}
a217f122 6216
29b0f896 6217static void
e3bb37b5 6218output_insn (void)
29b0f896 6219{
2bbd9c25
JJ		 6220 fragS *insn_start_frag;
6221 offsetT insn_start_off;
6222
29b0f896
AM		 6223 /* Tie dwarf2 debug info to the address at the start of the insn.
6224 We can't do this after the insn has been output as the current
6225 frag may have been closed off. eg. by frag_var. */
6226 dwarf2_emit_insn (0);
6227
2bbd9c25
JJ		 6228 insn_start_frag = frag_now;
6229 insn_start_off = frag_now_fix ();
6230
29b0f896 6231 /* Output jumps. */
40fb9820 6232 if (i.tm.opcode_modifier.jump)
29b0f896 6233 output_branch ();
40fb9820
L		 6234 else if (i.tm.opcode_modifier.jumpbyte
6235 || i.tm.opcode_modifier.jumpdword)
29b0f896 6236 output_jump ();
40fb9820 6237 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6238 output_interseg_jump ();
6239 else
6240 {
6241 /* Output normal instructions here. */
6242 char *p;
6243 unsigned char *q;
47465058 6244 unsigned int j;
331d2d0d 6245 unsigned int prefix;
4dffcebc 6246
c0f3af97 6247 /* Since the VEX prefix contains the implicit prefix, we don't
89e71f5c 6248 need the explicit prefix. */
c0f3af97 6249 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6250 {
c0f3af97 6251 switch (i.tm.opcode_length)
bc4bd9ab 6252 {
c0f3af97
L		 6253 case 3:
6254 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6255 {
c0f3af97
L		 6256 prefix = (i.tm.base_opcode >> 24) & 0xff;
6257 goto check_prefix;
6258 }
6259 break;
6260 case 2:
6261 if ((i.tm.base_opcode & 0xff0000) != 0)
6262 {
6263 prefix = (i.tm.base_opcode >> 16) & 0xff;
6264 if (i.tm.cpu_flags.bitfield.cpupadlock)
6265 {
4dffcebc 6266check_prefix:
c0f3af97 6267 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6268 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6269 != REPE_PREFIX_OPCODE))
6270 add_prefix (prefix);
6271 }
6272 else
4dffcebc
L		 6273 add_prefix (prefix);
6274 }
c0f3af97
L		 6275 break;
6276 case 1:
6277 break;
6278 default:
6279 abort ();
bc4bd9ab 6280 }
c0f3af97
L		 6281
6282 /* The prefix bytes. */
6283 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6284 if (*q)
6285 FRAG_APPEND_1_CHAR (*q);
0f10071e 6286 }
ae5c1c7b 6287 else
c0f3af97
L		 6288 {
6289 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6290 if (*q)
6291 switch (j)
6292 {
6293 case REX_PREFIX:
6294 /* REX byte is encoded in VEX prefix. */
6295 break;
6296 case SEG_PREFIX:
6297 case ADDR_PREFIX:
6298 FRAG_APPEND_1_CHAR (*q);
6299 break;
6300 default:
6301 /* There should be no other prefixes for instructions
6302 with VEX prefix. */
6303 abort ();
6304 }
6305
6306 /* Now the VEX prefix. */
6307 p = frag_more (i.vex.length);
6308 for (j = 0; j < i.vex.length; j++)
6309 p[j] = i.vex.bytes[j];
6310 }
252b5132 6311
29b0f896 6312 /* Now the opcode; be careful about word order here! */
4dffcebc 6313 if (i.tm.opcode_length == 1)
29b0f896
AM		 6314 {
6315 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6316 }
6317 else
6318 {
4dffcebc 6319 switch (i.tm.opcode_length)
331d2d0d 6320 {
4dffcebc 6321 case 3:
331d2d0d
L		 6322 p = frag_more (3);
6323 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6324 break;
6325 case 2:
6326 p = frag_more (2);
6327 break;
6328 default:
6329 abort ();
6330 break;
331d2d0d 6331 }
0f10071e 6332
29b0f896
AM		 6333 /* Put out high byte first: can't use md_number_to_chars! */
6334 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6335 *p = i.tm.base_opcode & 0xff;
6336 }
3e73aa7c 6337
29b0f896 6338 /* Now the modrm byte and sib byte (if present). */
40fb9820 6339 if (i.tm.opcode_modifier.modrm)
29b0f896 6340 {
4a3523fa
L		 6341 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6342 | i.rm.reg << 3
6343 | i.rm.mode << 6));
29b0f896
AM		 6344 /* If i.rm.regmem == ESP (4)
6345 && i.rm.mode != (Register mode)
6346 && not 16 bit
6347 ==> need second modrm byte. */
6348 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6349 && i.rm.mode != 3
40fb9820 6350 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6351 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6352 | i.sib.index << 3
6353 | i.sib.scale << 6));
29b0f896 6354 }
3e73aa7c 6355
29b0f896 6356 if (i.disp_operands)
2bbd9c25 6357 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6358
29b0f896 6359 if (i.imm_operands)
2bbd9c25 6360 output_imm (insn_start_frag, insn_start_off);
29b0f896 6361 }
252b5132 6362
29b0f896
AM		 6363#ifdef DEBUG386
6364 if (flag_debug)
6365 {
7b81dfbb 6366 pi ("" /*line*/, &i);
29b0f896
AM		 6367 }
6368#endif /* DEBUG386 */
6369}
252b5132 6370
e205caa7
L		 6371/* Return the size of the displacement operand N. */
6372
6373static int
6374disp_size (unsigned int n)
6375{
6376 int size = 4;
40fb9820
L		 6377 if (i.types[n].bitfield.disp64)
6378 size = 8;
6379 else if (i.types[n].bitfield.disp8)
6380 size = 1;
6381 else if (i.types[n].bitfield.disp16)
6382 size = 2;
e205caa7
L		 6383 return size;
6384}
6385
6386/* Return the size of the immediate operand N. */
6387
6388static int
6389imm_size (unsigned int n)
6390{
6391 int size = 4;
40fb9820
L		 6392 if (i.types[n].bitfield.imm64)
6393 size = 8;
6394 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6395 size = 1;
6396 else if (i.types[n].bitfield.imm16)
6397 size = 2;
e205caa7
L		 6398 return size;
6399}
6400
29b0f896 6401static void
64e74474 6402output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6403{
6404 char *p;
6405 unsigned int n;
252b5132 6406
29b0f896
AM		 6407 for (n = 0; n < i.operands; n++)
6408 {
40fb9820 6409 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6410 {
6411 if (i.op[n].disps->X_op == O_constant)
6412 {
e205caa7 6413 int size = disp_size (n);
29b0f896 6414 offsetT val;
252b5132 6415
29b0f896
AM		 6416 val = offset_in_range (i.op[n].disps->X_add_number,
6417 size);
6418 p = frag_more (size);
6419 md_number_to_chars (p, val, size);
6420 }
6421 else
6422 {
f86103b7 6423 enum bfd_reloc_code_real reloc_type;
e205caa7 6424 int size = disp_size (n);
40fb9820 6425 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6426 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6427
e205caa7 6428 /* We can't have 8 bit displacement here. */
9c2799c2 6429 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6430
29b0f896
AM		 6431 /* The PC relative address is computed relative
6432 to the instruction boundary, so in case immediate
6433 fields follows, we need to adjust the value. */
6434 if (pcrel && i.imm_operands)
6435 {
29b0f896 6436 unsigned int n1;
e205caa7 6437 int sz = 0;
252b5132 6438
29b0f896 6439 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6440 if (operand_type_check (i.types[n1], imm))
252b5132 6441 {
e205caa7
L		 6442 /* Only one immediate is allowed for PC
6443 relative address. */
9c2799c2 6444 gas_assert (sz == 0);
e205caa7
L		 6445 sz = imm_size (n1);
6446 i.op[n].disps->X_add_number -= sz;
252b5132 6447 }
29b0f896 6448 /* We should find the immediate. */
9c2799c2 6449 gas_assert (sz != 0);
29b0f896 6450 }
520dc8e8 6451
29b0f896 6452 p = frag_more (size);
2bbd9c25 6453 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6454 if (GOT_symbol
2bbd9c25 6455 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6456 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6457 || reloc_type == BFD_RELOC_X86_64_32S
6458 || (reloc_type == BFD_RELOC_64
6459 && object_64bit))
d6ab8113
JB		 6460 && (i.op[n].disps->X_op == O_symbol
6461 || (i.op[n].disps->X_op == O_add
6462 && ((symbol_get_value_expression
6463 (i.op[n].disps->X_op_symbol)->X_op)
6464 == O_subtract))))
6465 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6466 {
6467 offsetT add;
6468
6469 if (insn_start_frag == frag_now)
6470 add = (p - frag_now->fr_literal) - insn_start_off;
6471 else
6472 {
6473 fragS *fr;
6474
6475 add = insn_start_frag->fr_fix - insn_start_off;
6476 for (fr = insn_start_frag->fr_next;
6477 fr && fr != frag_now; fr = fr->fr_next)
6478 add += fr->fr_fix;
6479 add += p - frag_now->fr_literal;
6480 }
6481
4fa24527 6482 if (!object_64bit)
7b81dfbb
AJ		 6483 {
6484 reloc_type = BFD_RELOC_386_GOTPC;
6485 i.op[n].imms->X_add_number += add;
6486 }
6487 else if (reloc_type == BFD_RELOC_64)
6488 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6489 else
7b81dfbb
AJ		 6490 /* Don't do the adjustment for x86-64, as there
6491 the pcrel addressing is relative to the _next_
6492 insn, and that is taken care of in other code. */
d6ab8113 6493 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6494 }
062cd5e7 6495 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6496 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6497 }
6498 }
6499 }
6500}
252b5132 6501
29b0f896 6502static void
64e74474 6503output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6504{
6505 char *p;
6506 unsigned int n;
252b5132 6507
29b0f896
AM		 6508 for (n = 0; n < i.operands; n++)
6509 {
40fb9820 6510 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6511 {
6512 if (i.op[n].imms->X_op == O_constant)
6513 {
e205caa7 6514 int size = imm_size (n);
29b0f896 6515 offsetT val;
b4cac588 6516
29b0f896
AM		 6517 val = offset_in_range (i.op[n].imms->X_add_number,
6518 size);
6519 p = frag_more (size);
6520 md_number_to_chars (p, val, size);
6521 }
6522 else
6523 {
6524 /* Not absolute_section.
6525 Need a 32-bit fixup (don't support 8bit
6526 non-absolute imms). Try to support other
6527 sizes ... */
f86103b7 6528 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6529 int size = imm_size (n);
6530 int sign;
29b0f896 6531
40fb9820 6532 if (i.types[n].bitfield.imm32s
a7d61044 6533 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6534 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6535 sign = 1;
e205caa7
L		 6536 else
6537 sign = 0;
520dc8e8 6538
29b0f896
AM		 6539 p = frag_more (size);
6540 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6541
2bbd9c25
JJ		 6542 /* This is tough to explain. We end up with this one if we
6543 * have operands that look like
6544 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6545 * obtain the absolute address of the GOT, and it is strongly
6546 * preferable from a performance point of view to avoid using
6547 * a runtime relocation for this. The actual sequence of
6548 * instructions often look something like:
6549 *
6550 * call .L66
6551 * .L66:
6552 * popl %ebx
6553 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6554 *
6555 * The call and pop essentially return the absolute address
6556 * of the label .L66 and store it in %ebx. The linker itself
6557 * will ultimately change the first operand of the addl so
6558 * that %ebx points to the GOT, but to keep things simple, the
6559 * .o file must have this operand set so that it generates not
6560 * the absolute address of .L66, but the absolute address of
6561 * itself. This allows the linker itself simply treat a GOTPC
6562 * relocation as asking for a pcrel offset to the GOT to be
6563 * added in, and the addend of the relocation is stored in the
6564 * operand field for the instruction itself.
6565 *
6566 * Our job here is to fix the operand so that it would add
6567 * the correct offset so that %ebx would point to itself. The
6568 * thing that is tricky is that .-.L66 will point to the
6569 * beginning of the instruction, so we need to further modify
6570 * the operand so that it will point to itself. There are
6571 * other cases where you have something like:
6572 *
6573 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6574 *
6575 * and here no correction would be required. Internally in
6576 * the assembler we treat operands of this form as not being
6577 * pcrel since the '.' is explicitly mentioned, and I wonder
6578 * whether it would simplify matters to do it this way. Who
6579 * knows. In earlier versions of the PIC patches, the
6580 * pcrel_adjust field was used to store the correction, but
6581 * since the expression is not pcrel, I felt it would be
6582 * confusing to do it this way. */
6583
d6ab8113 6584 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6585 || reloc_type == BFD_RELOC_X86_64_32S
6586 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6587 && GOT_symbol
6588 && GOT_symbol == i.op[n].imms->X_add_symbol
6589 && (i.op[n].imms->X_op == O_symbol
6590 || (i.op[n].imms->X_op == O_add
6591 && ((symbol_get_value_expression
6592 (i.op[n].imms->X_op_symbol)->X_op)
6593 == O_subtract))))
6594 {
2bbd9c25
JJ		 6595 offsetT add;
6596
6597 if (insn_start_frag == frag_now)
6598 add = (p - frag_now->fr_literal) - insn_start_off;
6599 else
6600 {
6601 fragS *fr;
6602
6603 add = insn_start_frag->fr_fix - insn_start_off;
6604 for (fr = insn_start_frag->fr_next;
6605 fr && fr != frag_now; fr = fr->fr_next)
6606 add += fr->fr_fix;
6607 add += p - frag_now->fr_literal;
6608 }
6609
4fa24527 6610 if (!object_64bit)
d6ab8113 6611 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6612 else if (size == 4)
d6ab8113 6613 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6614 else if (size == 8)
6615 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6616 i.op[n].imms->X_add_number += add;
29b0f896 6617 }
29b0f896
AM		 6618 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6619 i.op[n].imms, 0, reloc_type);
6620 }
6621 }
6622 }
252b5132
RH		 6623}
6624\f
d182319b
JB		 6625/* x86_cons_fix_new is called via the expression parsing code when a
6626 reloc is needed. We use this hook to get the correct .got reloc. */
6627static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6628static int cons_sign = -1;
6629
6630void
e3bb37b5 6631x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6632 expressionS *exp)
d182319b
JB		 6633{
6634 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6635
6636 got_reloc = NO_RELOC;
6637
6638#ifdef TE_PE
6639 if (exp->X_op == O_secrel)
6640 {
6641 exp->X_op = O_symbol;
6642 r = BFD_RELOC_32_SECREL;
6643 }
6644#endif
6645
6646 fix_new_exp (frag, off, len, exp, 0, r);
6647}
6648
357d1bd8
L		 6649/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6650 purpose of the `.dc.a' internal pseudo-op. */
6651
6652int
6653x86_address_bytes (void)
6654{
6655 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
6656 return 4;
6657 return stdoutput->arch_info->bits_per_address / 8;
6658}
6659
d382c579
TG		 6660#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6661 || defined (LEX_AT)
718ddfc0
JB		 6662# define lex_got(reloc, adjust, types) NULL
6663#else
f3c180ae
AM		 6664/* Parse operands of the form
6665 <symbol>@GOTOFF+<nnn>
6666 and similar .plt or .got references.
6667
6668 If we find one, set up the correct relocation in RELOC and copy the
6669 input string, minus the `@GOTOFF' into a malloc'd buffer for
6670 parsing by the calling routine. Return this buffer, and if ADJUST
6671 is non-null set it to the length of the string we removed from the
6672 input line. Otherwise return NULL. */
6673static char *
91d6fa6a 6674lex_got (enum bfd_reloc_code_real *rel,
64e74474 6675 int *adjust,
40fb9820 6676 i386_operand_type *types)
f3c180ae 6677{
7b81dfbb
AJ		 6678 /* Some of the relocations depend on the size of what field is to
6679 be relocated. But in our callers i386_immediate and i386_displacement
6680 we don't yet know the operand size (this will be set by insn
6681 matching). Hence we record the word32 relocation here,
6682 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6683 static const struct {
6684 const char *str;
cff8d58a 6685 int len;
4fa24527 6686 const enum bfd_reloc_code_real rel[2];
40fb9820 6687 const i386_operand_type types64;
f3c180ae 6688 } gotrel[] = {
8ce3d284 6689#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 6690 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
6691 BFD_RELOC_SIZE32 },
6692 OPERAND_TYPE_IMM32_64 },
8ce3d284 6693#endif
cff8d58a
L		 6694 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6695 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6696 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6697 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6698 BFD_RELOC_X86_64_PLT32 },
40fb9820 6699 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6700 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6701 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6702 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6703 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6704 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6705 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6706 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6707 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6708 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6709 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6710 BFD_RELOC_X86_64_TLSGD },
40fb9820 6711 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6712 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6713 _dummy_first_bfd_reloc_code_real },
40fb9820 6714 OPERAND_TYPE_NONE },
cff8d58a
L		 6715 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6716 BFD_RELOC_X86_64_TLSLD },
40fb9820 6717 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6718 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6719 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6720 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6721 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6722 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6723 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6724 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6725 _dummy_first_bfd_reloc_code_real },
40fb9820 6726 OPERAND_TYPE_NONE },
cff8d58a
L		 6727 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6728 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6729 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6730 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6731 _dummy_first_bfd_reloc_code_real },
40fb9820 6732 OPERAND_TYPE_NONE },
cff8d58a
L		 6733 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6734 _dummy_first_bfd_reloc_code_real },
40fb9820 6735 OPERAND_TYPE_NONE },
cff8d58a
L		 6736 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6737 BFD_RELOC_X86_64_GOT32 },
40fb9820 6738 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6739 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6740 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6741 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6742 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6743 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6744 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6745 };
6746 char *cp;
6747 unsigned int j;
6748
d382c579 6749#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 6750 if (!IS_ELF)
6751 return NULL;
d382c579 6752#endif
718ddfc0 6753
f3c180ae 6754 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6755 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6756 return NULL;
6757
47465058 6758 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6759 {
cff8d58a 6760 int len = gotrel[j].len;
28f81592 6761 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6762 {
4fa24527 6763 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6764 {
28f81592
AM		 6765 int first, second;
6766 char *tmpbuf, *past_reloc;
f3c180ae 6767
91d6fa6a 6768 *rel = gotrel[j].rel[object_64bit];
f3c180ae 6769
3956db08
JB		 6770 if (types)
6771 {
6772 if (flag_code != CODE_64BIT)
40fb9820
L		 6773 {
6774 types->bitfield.imm32 = 1;
6775 types->bitfield.disp32 = 1;
6776 }
3956db08
JB		 6777 else
6778 *types = gotrel[j].types64;
6779 }
6780
8fd4256d 6781 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 6782 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6783
28f81592 6784 /* The length of the first part of our input line. */
f3c180ae 6785 first = cp - input_line_pointer;
28f81592
AM		 6786
6787 /* The second part goes from after the reloc token until
67c11a9b 6788 (and including) an end_of_line char or comma. */
28f81592 6789 past_reloc = cp + 1 + len;
67c11a9b
AM		 6790 cp = past_reloc;
6791 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6792 ++cp;
6793 second = cp + 1 - past_reloc;
28f81592
AM		 6794
6795 /* Allocate and copy string. The trailing NUL shouldn't
6796 be necessary, but be safe. */
1e9cc1c2 6797 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6798 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6799 if (second != 0 && *past_reloc != ' ')
6800 /* Replace the relocation token with ' ', so that
6801 errors like foo@GOTOFF1 will be detected. */
6802 tmpbuf[first++] = ' ';
af89796a
L		 6803 else
6804 /* Increment length by 1 if the relocation token is
6805 removed. */
6806 len++;
6807 if (adjust)
6808 *adjust = len;
0787a12d
AM		 6809 memcpy (tmpbuf + first, past_reloc, second);
6810 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6811 return tmpbuf;
6812 }
6813
4fa24527
JB		 6814 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6815 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6816 return NULL;
6817 }
6818 }
6819
6820 /* Might be a symbol version string. Don't as_bad here. */
6821 return NULL;
6822}
4e4f7c87 6823#endif
f3c180ae 6824
a988325c
NC		 6825#ifdef TE_PE
6826#ifdef lex_got
6827#undef lex_got
6828#endif
6829/* Parse operands of the form
6830 <symbol>@SECREL32+<nnn>
6831
6832 If we find one, set up the correct relocation in RELOC and copy the
6833 input string, minus the `@SECREL32' into a malloc'd buffer for
6834 parsing by the calling routine. Return this buffer, and if ADJUST
6835 is non-null set it to the length of the string we removed from the
34bca508
L		 6836 input line. Otherwise return NULL.
6837
a988325c
NC		 6838 This function is copied from the ELF version above adjusted for PE targets. */
6839
6840static char *
6841lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
6842 int *adjust ATTRIBUTE_UNUSED,
6843 i386_operand_type *types ATTRIBUTE_UNUSED)
6844{
6845 static const struct
6846 {
6847 const char *str;
6848 int len;
6849 const enum bfd_reloc_code_real rel[2];
6850 const i386_operand_type types64;
6851 }
6852 gotrel[] =
6853 {
6854 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
6855 BFD_RELOC_32_SECREL },
6856 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6857 };
6858
6859 char *cp;
6860 unsigned j;
6861
6862 for (cp = input_line_pointer; *cp != '@'; cp++)
6863 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
6864 return NULL;
6865
6866 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
6867 {
6868 int len = gotrel[j].len;
6869
6870 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
6871 {
6872 if (gotrel[j].rel[object_64bit] != 0)
6873 {
6874 int first, second;
6875 char *tmpbuf, *past_reloc;
6876
6877 *rel = gotrel[j].rel[object_64bit];
6878 if (adjust)
6879 *adjust = len;
6880
6881 if (types)
6882 {
6883 if (flag_code != CODE_64BIT)
6884 {
6885 types->bitfield.imm32 = 1;
6886 types->bitfield.disp32 = 1;
6887 }
6888 else
6889 *types = gotrel[j].types64;
6890 }
6891
6892 /* The length of the first part of our input line. */
6893 first = cp - input_line_pointer;
6894
6895 /* The second part goes from after the reloc token until
6896 (and including) an end_of_line char or comma. */
6897 past_reloc = cp + 1 + len;
6898 cp = past_reloc;
6899 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6900 ++cp;
6901 second = cp + 1 - past_reloc;
6902
6903 /* Allocate and copy string. The trailing NUL shouldn't
6904 be necessary, but be safe. */
6905 tmpbuf = (char *) xmalloc (first + second + 2);
6906 memcpy (tmpbuf, input_line_pointer, first);
6907 if (second != 0 && *past_reloc != ' ')
6908 /* Replace the relocation token with ' ', so that
6909 errors like foo@SECLREL321 will be detected. */
6910 tmpbuf[first++] = ' ';
6911 memcpy (tmpbuf + first, past_reloc, second);
6912 tmpbuf[first + second] = '\0';
6913 return tmpbuf;
6914 }
6915
6916 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6917 gotrel[j].str, 1 << (5 + object_64bit));
6918 return NULL;
6919 }
6920 }
6921
6922 /* Might be a symbol version string. Don't as_bad here. */
6923 return NULL;
6924}
6925
6926#endif /* TE_PE */
6927
f3c180ae 6928void
e3bb37b5 6929x86_cons (expressionS *exp, int size)
f3c180ae 6930{
ee86248c
JB		 6931 intel_syntax = -intel_syntax;
6932
3c7b9c2c 6933 exp->X_md = 0;
4fa24527 6934 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6935 {
6936 /* Handle @GOTOFF and the like in an expression. */
6937 char *save;
6938 char *gotfree_input_line;
4a57f2cf 6939 int adjust = 0;
f3c180ae
AM		 6940
6941 save = input_line_pointer;
3956db08 6942 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6943 if (gotfree_input_line)
6944 input_line_pointer = gotfree_input_line;
6945
6946 expression (exp);
6947
6948 if (gotfree_input_line)
6949 {
6950 /* expression () has merrily parsed up to the end of line,
6951 or a comma - in the wrong buffer. Transfer how far
6952 input_line_pointer has moved to the right buffer. */
6953 input_line_pointer = (save
6954 + (input_line_pointer - gotfree_input_line)
6955 + adjust);
6956 free (gotfree_input_line);
3992d3b7
AM		 6957 if (exp->X_op == O_constant
6958 || exp->X_op == O_absent
6959 || exp->X_op == O_illegal
0398aac5 6960 || exp->X_op == O_register
3992d3b7
AM		 6961 || exp->X_op == O_big)
6962 {
6963 char c = *input_line_pointer;
6964 *input_line_pointer = 0;
6965 as_bad (_("missing or invalid expression `%s'"), save);
6966 *input_line_pointer = c;
6967 }
f3c180ae
AM		 6968 }
6969 }
6970 else
6971 expression (exp);
ee86248c
JB		 6972
6973 intel_syntax = -intel_syntax;
6974
6975 if (intel_syntax)
6976 i386_intel_simplify (exp);
f3c180ae 6977}
f3c180ae 6978
9f32dd5b
L		 6979static void
6980signed_cons (int size)
6482c264 6981{
d182319b
JB		 6982 if (flag_code == CODE_64BIT)
6983 cons_sign = 1;
6984 cons (size);
6985 cons_sign = -1;
6482c264
NC		 6986}
6987
d182319b 6988#ifdef TE_PE
6482c264 6989static void
7016a5d5 6990pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 6991{
6992 expressionS exp;
6993
6994 do
6995 {
6996 expression (&exp);
6997 if (exp.X_op == O_symbol)
6998 exp.X_op = O_secrel;
6999
7000 emit_expr (&exp, 4);
7001 }
7002 while (*input_line_pointer++ == ',');
7003
7004 input_line_pointer--;
7005 demand_empty_rest_of_line ();
7006}
6482c264
NC		 7007#endif
7008
252b5132 7009static int
70e41ade 7010i386_immediate (char *imm_start)
252b5132
RH		 7011{
7012 char *save_input_line_pointer;
f3c180ae 7013 char *gotfree_input_line;
252b5132 7014 segT exp_seg = 0;
47926f60 7015 expressionS *exp;
40fb9820
L		 7016 i386_operand_type types;
7017
0dfbf9d7 7018 operand_type_set (&types, ~0);
252b5132
RH		 7019
7020 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7021 {
31b2323c
L		 7022 as_bad (_("at most %d immediate operands are allowed"),
7023 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7024 return 0;
7025 }
7026
7027 exp = &im_expressions[i.imm_operands++];
520dc8e8 7028 i.op[this_operand].imms = exp;
252b5132
RH		 7029
7030 if (is_space_char (*imm_start))
7031 ++imm_start;
7032
7033 save_input_line_pointer = input_line_pointer;
7034 input_line_pointer = imm_start;
7035
3956db08 7036 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7037 if (gotfree_input_line)
7038 input_line_pointer = gotfree_input_line;
252b5132
RH		 7039
7040 exp_seg = expression (exp);
7041
83183c0c 7042 SKIP_WHITESPACE ();
252b5132 7043 if (*input_line_pointer)
f3c180ae 7044 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7045
7046 input_line_pointer = save_input_line_pointer;
f3c180ae 7047 if (gotfree_input_line)
ee86248c
JB		 7048 {
7049 free (gotfree_input_line);
7050
7051 if (exp->X_op == O_constant || exp->X_op == O_register)
7052 exp->X_op = O_illegal;
7053 }
7054
7055 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7056}
252b5132 7057
ee86248c
JB		 7058static int
7059i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7060 i386_operand_type types, const char *imm_start)
7061{
7062 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7063 {
313c53d1
L		 7064 if (imm_start)
7065 as_bad (_("missing or invalid immediate expression `%s'"),
7066 imm_start);
3992d3b7 7067 return 0;
252b5132 7068 }
3e73aa7c 7069 else if (exp->X_op == O_constant)
252b5132 7070 {
47926f60 7071 /* Size it properly later. */
40fb9820 7072 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7073 /* If not 64bit, sign extend val. */
7074 if (flag_code != CODE_64BIT
4eed87de
AM		 7075 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7076 exp->X_add_number
7077 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7078 }
4c63da97 7079#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7080 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7081 && exp_seg != absolute_section
47926f60 7082 && exp_seg != text_section
24eab124
AM		 7083 && exp_seg != data_section
7084 && exp_seg != bss_section
7085 && exp_seg != undefined_section
f86103b7 7086 && !bfd_is_com_section (exp_seg))
252b5132 7087 {
d0b47220 7088 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7089 return 0;
7090 }
7091#endif
bb8f5920
L		 7092 else if (!intel_syntax && exp->X_op == O_register)
7093 {
313c53d1
L		 7094 if (imm_start)
7095 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7096 return 0;
7097 }
252b5132
RH		 7098 else
7099 {
7100 /* This is an address. The size of the address will be
24eab124 7101 determined later, depending on destination register,
3e73aa7c 7102 suffix, or the default for the section. */
40fb9820
L		 7103 i.types[this_operand].bitfield.imm8 = 1;
7104 i.types[this_operand].bitfield.imm16 = 1;
7105 i.types[this_operand].bitfield.imm32 = 1;
7106 i.types[this_operand].bitfield.imm32s = 1;
7107 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7108 i.types[this_operand] = operand_type_and (i.types[this_operand],
7109 types);
252b5132
RH		 7110 }
7111
7112 return 1;
7113}
7114
551c1ca1 7115static char *
e3bb37b5 7116i386_scale (char *scale)
252b5132 7117{
551c1ca1
AM		 7118 offsetT val;
7119 char *save = input_line_pointer;
252b5132 7120
551c1ca1
AM		 7121 input_line_pointer = scale;
7122 val = get_absolute_expression ();
7123
7124 switch (val)
252b5132 7125 {
551c1ca1 7126 case 1:
252b5132
RH		 7127 i.log2_scale_factor = 0;
7128 break;
551c1ca1 7129 case 2:
252b5132
RH		 7130 i.log2_scale_factor = 1;
7131 break;
551c1ca1 7132 case 4:
252b5132
RH		 7133 i.log2_scale_factor = 2;
7134 break;
551c1ca1 7135 case 8:
252b5132
RH		 7136 i.log2_scale_factor = 3;
7137 break;
7138 default:
a724f0f4
JB		 7139 {
7140 char sep = *input_line_pointer;
7141
7142 *input_line_pointer = '\0';
7143 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7144 scale);
7145 *input_line_pointer = sep;
7146 input_line_pointer = save;
7147 return NULL;
7148 }
252b5132 7149 }
29b0f896 7150 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7151 {
7152 as_warn (_("scale factor of %d without an index register"),
24eab124 7153 1 << i.log2_scale_factor);
252b5132 7154 i.log2_scale_factor = 0;
252b5132 7155 }
551c1ca1
AM		 7156 scale = input_line_pointer;
7157 input_line_pointer = save;
7158 return scale;
252b5132
RH		 7159}
7160
252b5132 7161static int
e3bb37b5 7162i386_displacement (char *disp_start, char *disp_end)
252b5132 7163{
29b0f896 7164 expressionS *exp;
252b5132
RH		 7165 segT exp_seg = 0;
7166 char *save_input_line_pointer;
f3c180ae 7167 char *gotfree_input_line;
40fb9820
L		 7168 int override;
7169 i386_operand_type bigdisp, types = anydisp;
3992d3b7 7170 int ret;
252b5132 7171
31b2323c
L		 7172 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7173 {
7174 as_bad (_("at most %d displacement operands are allowed"),
7175 MAX_MEMORY_OPERANDS);
7176 return 0;
7177 }
7178
0dfbf9d7 7179 operand_type_set (&bigdisp, 0);
40fb9820
L		 7180 if ((i.types[this_operand].bitfield.jumpabsolute)
7181 || (!current_templates->start->opcode_modifier.jump
7182 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 7183 {
40fb9820 7184 bigdisp.bitfield.disp32 = 1;
e05278af 7185 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 7186 if (flag_code == CODE_64BIT)
7187 {
7188 if (!override)
7189 {
7190 bigdisp.bitfield.disp32s = 1;
7191 bigdisp.bitfield.disp64 = 1;
7192 }
7193 }
7194 else if ((flag_code == CODE_16BIT) ^ override)
7195 {
7196 bigdisp.bitfield.disp32 = 0;
7197 bigdisp.bitfield.disp16 = 1;
7198 }
e05278af
JB		 7199 }
7200 else
7201 {
7202 /* For PC-relative branches, the width of the displacement
7203 is dependent upon data size, not address size. */
e05278af 7204 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 7205 if (flag_code == CODE_64BIT)
7206 {
7207 if (override || i.suffix == WORD_MNEM_SUFFIX)
7208 bigdisp.bitfield.disp16 = 1;
7209 else
7210 {
7211 bigdisp.bitfield.disp32 = 1;
7212 bigdisp.bitfield.disp32s = 1;
7213 }
7214 }
7215 else
e05278af
JB		 7216 {
7217 if (!override)
7218 override = (i.suffix == (flag_code != CODE_16BIT
7219 ? WORD_MNEM_SUFFIX
7220 : LONG_MNEM_SUFFIX));
40fb9820
L		 7221 bigdisp.bitfield.disp32 = 1;
7222 if ((flag_code == CODE_16BIT) ^ override)
7223 {
7224 bigdisp.bitfield.disp32 = 0;
7225 bigdisp.bitfield.disp16 = 1;
7226 }
e05278af 7227 }
e05278af 7228 }
c6fb90c8
L		 7229 i.types[this_operand] = operand_type_or (i.types[this_operand],
7230 bigdisp);
252b5132
RH		 7231
7232 exp = &disp_expressions[i.disp_operands];
520dc8e8 7233 i.op[this_operand].disps = exp;
252b5132
RH		 7234 i.disp_operands++;
7235 save_input_line_pointer = input_line_pointer;
7236 input_line_pointer = disp_start;
7237 END_STRING_AND_SAVE (disp_end);
7238
7239#ifndef GCC_ASM_O_HACK
7240#define GCC_ASM_O_HACK 0
7241#endif
7242#if GCC_ASM_O_HACK
7243 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 7244 if (i.types[this_operand].bitfield.baseIndex
24eab124 7245 && displacement_string_end[-1] == '+')
252b5132
RH		 7246 {
7247 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 7248 constraint within gcc asm statements.
7249 For instance:
7250
7251 #define _set_tssldt_desc(n,addr,limit,type) \
7252 __asm__ __volatile__ ( \
7253 "movw %w2,%0\n\t" \
7254 "movw %w1,2+%0\n\t" \
7255 "rorl $16,%1\n\t" \
7256 "movb %b1,4+%0\n\t" \
7257 "movb %4,5+%0\n\t" \
7258 "movb $0,6+%0\n\t" \
7259 "movb %h1,7+%0\n\t" \
7260 "rorl $16,%1" \
7261 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7262
7263 This works great except that the output assembler ends
7264 up looking a bit weird if it turns out that there is
7265 no offset. You end up producing code that looks like:
7266
7267 #APP
7268 movw $235,(%eax)
7269 movw %dx,2+(%eax)
7270 rorl $16,%edx
7271 movb %dl,4+(%eax)
7272 movb $137,5+(%eax)
7273 movb $0,6+(%eax)
7274 movb %dh,7+(%eax)
7275 rorl $16,%edx
7276 #NO_APP
7277
47926f60 7278 So here we provide the missing zero. */
24eab124
AM		 7279
7280 *displacement_string_end = '0';
252b5132
RH		 7281 }
7282#endif
3956db08 7283 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7284 if (gotfree_input_line)
7285 input_line_pointer = gotfree_input_line;
252b5132 7286
24eab124 7287 exp_seg = expression (exp);
252b5132 7288
636c26b0
AM		 7289 SKIP_WHITESPACE ();
7290 if (*input_line_pointer)
7291 as_bad (_("junk `%s' after expression"), input_line_pointer);
7292#if GCC_ASM_O_HACK
7293 RESTORE_END_STRING (disp_end + 1);
7294#endif
636c26b0 7295 input_line_pointer = save_input_line_pointer;
636c26b0 7296 if (gotfree_input_line)
ee86248c
JB		 7297 {
7298 free (gotfree_input_line);
7299
7300 if (exp->X_op == O_constant || exp->X_op == O_register)
7301 exp->X_op = O_illegal;
7302 }
7303
7304 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
7305
7306 RESTORE_END_STRING (disp_end);
7307
7308 return ret;
7309}
7310
7311static int
7312i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7313 i386_operand_type types, const char *disp_start)
7314{
7315 i386_operand_type bigdisp;
7316 int ret = 1;
636c26b0 7317
24eab124
AM		 7318 /* We do this to make sure that the section symbol is in
7319 the symbol table. We will ultimately change the relocation
47926f60 7320 to be relative to the beginning of the section. */
1ae12ab7 7321 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 7322 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
7323 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 7324 {
636c26b0 7325 if (exp->X_op != O_symbol)
3992d3b7 7326 goto inv_disp;
636c26b0 7327
e5cb08ac 7328 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 7329 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
7330 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 7331 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 7332 exp->X_op = O_subtract;
7333 exp->X_op_symbol = GOT_symbol;
1ae12ab7 7334 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 7335 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 7336 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
7337 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 7338 else
29b0f896 7339 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 7340 }
252b5132 7341
3992d3b7
AM		 7342 else if (exp->X_op == O_absent
7343 || exp->X_op == O_illegal
ee86248c 7344 || exp->X_op == O_big)
2daf4fd8 7345 {
3992d3b7
AM		 7346 inv_disp:
7347 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 7348 disp_start);
3992d3b7 7349 ret = 0;
2daf4fd8
AM		 7350 }
7351
0e1147d9
L		 7352 else if (flag_code == CODE_64BIT
7353 && !i.prefix[ADDR_PREFIX]
7354 && exp->X_op == O_constant)
7355 {
7356 /* Since displacement is signed extended to 64bit, don't allow
7357 disp32 and turn off disp32s if they are out of range. */
7358 i.types[this_operand].bitfield.disp32 = 0;
7359 if (!fits_in_signed_long (exp->X_add_number))
7360 {
7361 i.types[this_operand].bitfield.disp32s = 0;
7362 if (i.types[this_operand].bitfield.baseindex)
7363 {
7364 as_bad (_("0x%lx out range of signed 32bit displacement"),
7365 (long) exp->X_add_number);
7366 ret = 0;
7367 }
7368 }
7369 }
7370
4c63da97 7371#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7372 else if (exp->X_op != O_constant
7373 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7374 && exp_seg != absolute_section
7375 && exp_seg != text_section
7376 && exp_seg != data_section
7377 && exp_seg != bss_section
7378 && exp_seg != undefined_section
7379 && !bfd_is_com_section (exp_seg))
24eab124 7380 {
d0b47220 7381 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7382 ret = 0;
24eab124 7383 }
252b5132 7384#endif
3956db08 7385
40fb9820
L		 7386 /* Check if this is a displacement only operand. */
7387 bigdisp = i.types[this_operand];
7388 bigdisp.bitfield.disp8 = 0;
7389 bigdisp.bitfield.disp16 = 0;
7390 bigdisp.bitfield.disp32 = 0;
7391 bigdisp.bitfield.disp32s = 0;
7392 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7393 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7394 i.types[this_operand] = operand_type_and (i.types[this_operand],
7395 types);
3956db08 7396
3992d3b7 7397 return ret;
252b5132
RH		 7398}
7399
eecb386c 7400/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7401 Return 1 on success, 0 on a failure. */
7402
252b5132 7403static int
e3bb37b5 7404i386_index_check (const char *operand_string)
252b5132 7405{
fc0763e6 7406 const char *kind = "base/index";
be05d201
L		 7407 enum flag_code addr_mode;
7408
7409 if (i.prefix[ADDR_PREFIX])
7410 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
7411 else
7412 {
7413 addr_mode = flag_code;
7414
24eab124 7415#if INFER_ADDR_PREFIX
be05d201
L		 7416 if (i.mem_operands == 0)
7417 {
7418 /* Infer address prefix from the first memory operand. */
7419 const reg_entry *addr_reg = i.base_reg;
7420
7421 if (addr_reg == NULL)
7422 addr_reg = i.index_reg;
eecb386c 7423
be05d201
L		 7424 if (addr_reg)
7425 {
7426 if (addr_reg->reg_num == RegEip
7427 || addr_reg->reg_num == RegEiz
7428 || addr_reg->reg_type.bitfield.reg32)
7429 addr_mode = CODE_32BIT;
7430 else if (flag_code != CODE_64BIT
7431 && addr_reg->reg_type.bitfield.reg16)
7432 addr_mode = CODE_16BIT;
7433
7434 if (addr_mode != flag_code)
7435 {
7436 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7437 i.prefixes += 1;
7438 /* Change the size of any displacement too. At most one
7439 of Disp16 or Disp32 is set.
7440 FIXME. There doesn't seem to be any real need for
7441 separate Disp16 and Disp32 flags. The same goes for
7442 Imm16 and Imm32. Removing them would probably clean
7443 up the code quite a lot. */
7444 if (flag_code != CODE_64BIT
7445 && (i.types[this_operand].bitfield.disp16
7446 || i.types[this_operand].bitfield.disp32))
7447 i.types[this_operand]
7448 = operand_type_xor (i.types[this_operand], disp16_32);
7449 }
7450 }
7451 }
24eab124 7452#endif
be05d201
L		 7453 }
7454
fc0763e6
JB		 7455 if (current_templates->start->opcode_modifier.isstring
7456 && !current_templates->start->opcode_modifier.immext
7457 && (current_templates->end[-1].opcode_modifier.isstring
7458 || i.mem_operands))
7459 {
7460 /* Memory operands of string insns are special in that they only allow
7461 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 7462 const reg_entry *expected_reg;
7463 static const char *di_si[][2] =
7464 {
7465 { "esi", "edi" },
7466 { "si", "di" },
7467 { "rsi", "rdi" }
7468 };
7469 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 7470
7471 kind = "string address";
7472
7473 if (current_templates->start->opcode_modifier.w)
7474 {
7475 i386_operand_type type = current_templates->end[-1].operand_types[0];
7476
7477 if (!type.bitfield.baseindex
7478 || ((!i.mem_operands != !intel_syntax)
7479 && current_templates->end[-1].operand_types[1]
7480 .bitfield.baseindex))
7481 type = current_templates->end[-1].operand_types[1];
be05d201
L		 7482 expected_reg = hash_find (reg_hash,
7483 di_si[addr_mode][type.bitfield.esseg]);
7484
fc0763e6
JB		 7485 }
7486 else
be05d201 7487 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 7488
be05d201
L		 7489 if (i.base_reg != expected_reg
7490 || i.index_reg
fc0763e6 7491 || operand_type_check (i.types[this_operand], disp))
fc0763e6 7492 {
be05d201
L		 7493 /* The second memory operand must have the same size as
7494 the first one. */
7495 if (i.mem_operands
7496 && i.base_reg
7497 && !((addr_mode == CODE_64BIT
7498 && i.base_reg->reg_type.bitfield.reg64)
7499 || (addr_mode == CODE_32BIT
7500 ? i.base_reg->reg_type.bitfield.reg32
7501 : i.base_reg->reg_type.bitfield.reg16)))
7502 goto bad_address;
7503
fc0763e6
JB		 7504 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7505 operand_string,
7506 intel_syntax ? '[' : '(',
7507 register_prefix,
be05d201 7508 expected_reg->reg_name,
fc0763e6 7509 intel_syntax ? ']' : ')');
be05d201 7510 return 1;
fc0763e6 7511 }
be05d201
L		 7512 else
7513 return 1;
7514
7515bad_address:
7516 as_bad (_("`%s' is not a valid %s expression"),
7517 operand_string, kind);
7518 return 0;
3e73aa7c
JH		 7519 }
7520 else
7521 {
be05d201
L		 7522 if (addr_mode != CODE_16BIT)
7523 {
7524 /* 32-bit/64-bit checks. */
7525 if ((i.base_reg
7526 && (addr_mode == CODE_64BIT
7527 ? !i.base_reg->reg_type.bitfield.reg64
7528 : !i.base_reg->reg_type.bitfield.reg32)
7529 && (i.index_reg
7530 || (i.base_reg->reg_num
7531 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
7532 || (i.index_reg
7533 && !i.index_reg->reg_type.bitfield.regxmm
7534 && !i.index_reg->reg_type.bitfield.regymm
7535 && ((addr_mode == CODE_64BIT
7536 ? !(i.index_reg->reg_type.bitfield.reg64
7537 || i.index_reg->reg_num == RegRiz)
7538 : !(i.index_reg->reg_type.bitfield.reg32
7539 || i.index_reg->reg_num == RegEiz))
7540 || !i.index_reg->reg_type.bitfield.baseindex)))
7541 goto bad_address;
7542 }
7543 else
3e73aa7c 7544 {
be05d201 7545 /* 16-bit checks. */
3e73aa7c 7546 if ((i.base_reg
40fb9820
L		 7547 && (!i.base_reg->reg_type.bitfield.reg16
7548 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7549 || (i.index_reg
40fb9820
L		 7550 && (!i.index_reg->reg_type.bitfield.reg16
7551 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7552 || !(i.base_reg
7553 && i.base_reg->reg_num < 6
7554 && i.index_reg->reg_num >= 6
7555 && i.log2_scale_factor == 0))))
be05d201 7556 goto bad_address;
3e73aa7c
JH		 7557 }
7558 }
be05d201 7559 return 1;
24eab124 7560}
252b5132 7561
fc0763e6 7562/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7563 on error. */
252b5132 7564
252b5132 7565static int
a7619375 7566i386_att_operand (char *operand_string)
252b5132 7567{
af6bdddf
AM		 7568 const reg_entry *r;
7569 char *end_op;
24eab124 7570 char *op_string = operand_string;
252b5132 7571
24eab124 7572 if (is_space_char (*op_string))
252b5132
RH		 7573 ++op_string;
7574
24eab124 7575 /* We check for an absolute prefix (differentiating,
47926f60 7576 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7577 if (*op_string == ABSOLUTE_PREFIX)
7578 {
7579 ++op_string;
7580 if (is_space_char (*op_string))
7581 ++op_string;
40fb9820 7582 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7583 }
252b5132 7584
47926f60 7585 /* Check if operand is a register. */
4d1bb795 7586 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7587 {
40fb9820
L		 7588 i386_operand_type temp;
7589
24eab124
AM		 7590 /* Check for a segment override by searching for ':' after a
7591 segment register. */
7592 op_string = end_op;
7593 if (is_space_char (*op_string))
7594 ++op_string;
40fb9820
L		 7595 if (*op_string == ':'
7596 && (r->reg_type.bitfield.sreg2
7597 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7598 {
7599 switch (r->reg_num)
7600 {
7601 case 0:
7602 i.seg[i.mem_operands] = &es;
7603 break;
7604 case 1:
7605 i.seg[i.mem_operands] = &cs;
7606 break;
7607 case 2:
7608 i.seg[i.mem_operands] = &ss;
7609 break;
7610 case 3:
7611 i.seg[i.mem_operands] = &ds;
7612 break;
7613 case 4:
7614 i.seg[i.mem_operands] = &fs;
7615 break;
7616 case 5:
7617 i.seg[i.mem_operands] = &gs;
7618 break;
7619 }
252b5132 7620
24eab124 7621 /* Skip the ':' and whitespace. */
252b5132
RH		 7622 ++op_string;
7623 if (is_space_char (*op_string))
24eab124 7624 ++op_string;
252b5132 7625
24eab124
AM		 7626 if (!is_digit_char (*op_string)
7627 && !is_identifier_char (*op_string)
7628 && *op_string != '('
7629 && *op_string != ABSOLUTE_PREFIX)
7630 {
7631 as_bad (_("bad memory operand `%s'"), op_string);
7632 return 0;
7633 }
47926f60 7634 /* Handle case of %es:*foo. */
24eab124
AM		 7635 if (*op_string == ABSOLUTE_PREFIX)
7636 {
7637 ++op_string;
7638 if (is_space_char (*op_string))
7639 ++op_string;
40fb9820 7640 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7641 }
7642 goto do_memory_reference;
7643 }
7644 if (*op_string)
7645 {
d0b47220 7646 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7647 return 0;
7648 }
40fb9820
L		 7649 temp = r->reg_type;
7650 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7651 i.types[this_operand] = operand_type_or (i.types[this_operand],
7652 temp);
7d5e4556 7653 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7654 i.op[this_operand].regs = r;
24eab124
AM		 7655 i.reg_operands++;
7656 }
af6bdddf
AM		 7657 else if (*op_string == REGISTER_PREFIX)
7658 {
7659 as_bad (_("bad register name `%s'"), op_string);
7660 return 0;
7661 }
24eab124 7662 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7663 {
24eab124 7664 ++op_string;
40fb9820 7665 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7666 {
d0b47220 7667 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7668 return 0;
7669 }
7670 if (!i386_immediate (op_string))
7671 return 0;
7672 }
7673 else if (is_digit_char (*op_string)
7674 || is_identifier_char (*op_string)
e5cb08ac 7675 || *op_string == '(')
24eab124 7676 {
47926f60 7677 /* This is a memory reference of some sort. */
af6bdddf 7678 char *base_string;
252b5132 7679
47926f60 7680 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7681 char *displacement_string_start;
7682 char *displacement_string_end;
252b5132 7683
24eab124 7684 do_memory_reference:
24eab124 7685 if ((i.mem_operands == 1
40fb9820 7686 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7687 || i.mem_operands == 2)
7688 {
7689 as_bad (_("too many memory references for `%s'"),
7690 current_templates->start->name);
7691 return 0;
7692 }
252b5132 7693
24eab124
AM		 7694 /* Check for base index form. We detect the base index form by
7695 looking for an ')' at the end of the operand, searching
7696 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7697 after the '('. */
af6bdddf 7698 base_string = op_string + strlen (op_string);
c3332e24 7699
af6bdddf
AM		 7700 --base_string;
7701 if (is_space_char (*base_string))
7702 --base_string;
252b5132 7703
47926f60 7704 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7705 displacement_string_start = op_string;
7706 displacement_string_end = base_string + 1;
252b5132 7707
24eab124
AM		 7708 if (*base_string == ')')
7709 {
af6bdddf 7710 char *temp_string;
24eab124
AM		 7711 unsigned int parens_balanced = 1;
7712 /* We've already checked that the number of left & right ()'s are
47926f60 7713 equal, so this loop will not be infinite. */
24eab124
AM		 7714 do
7715 {
7716 base_string--;
7717 if (*base_string == ')')
7718 parens_balanced++;
7719 if (*base_string == '(')
7720 parens_balanced--;
7721 }
7722 while (parens_balanced);
c3332e24 7723
af6bdddf 7724 temp_string = base_string;
c3332e24 7725
24eab124 7726 /* Skip past '(' and whitespace. */
252b5132
RH		 7727 ++base_string;
7728 if (is_space_char (*base_string))
24eab124 7729 ++base_string;
252b5132 7730
af6bdddf 7731 if (*base_string == ','
4eed87de
AM		 7732 || ((i.base_reg = parse_register (base_string, &end_op))
7733 != NULL))
252b5132 7734 {
af6bdddf 7735 displacement_string_end = temp_string;
252b5132 7736
40fb9820 7737 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7738
af6bdddf 7739 if (i.base_reg)
24eab124 7740 {
24eab124
AM		 7741 base_string = end_op;
7742 if (is_space_char (*base_string))
7743 ++base_string;
af6bdddf
AM		 7744 }
7745
7746 /* There may be an index reg or scale factor here. */
7747 if (*base_string == ',')
7748 {
7749 ++base_string;
7750 if (is_space_char (*base_string))
7751 ++base_string;
7752
4eed87de
AM		 7753 if ((i.index_reg = parse_register (base_string, &end_op))
7754 != NULL)
24eab124 7755 {
af6bdddf 7756 base_string = end_op;
24eab124
AM		 7757 if (is_space_char (*base_string))
7758 ++base_string;
af6bdddf
AM		 7759 if (*base_string == ',')
7760 {
7761 ++base_string;
7762 if (is_space_char (*base_string))
7763 ++base_string;
7764 }
e5cb08ac 7765 else if (*base_string != ')')
af6bdddf 7766 {
4eed87de
AM		 7767 as_bad (_("expecting `,' or `)' "
7768 "after index register in `%s'"),
af6bdddf
AM		 7769 operand_string);
7770 return 0;
7771 }
24eab124 7772 }
af6bdddf 7773 else if (*base_string == REGISTER_PREFIX)
24eab124 7774 {
f76bf5e0
L		 7775 end_op = strchr (base_string, ',');
7776 if (end_op)
7777 *end_op = '\0';
af6bdddf 7778 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7779 return 0;
7780 }
252b5132 7781
47926f60 7782 /* Check for scale factor. */
551c1ca1 7783 if (*base_string != ')')
af6bdddf 7784 {
551c1ca1
AM		 7785 char *end_scale = i386_scale (base_string);
7786
7787 if (!end_scale)
af6bdddf 7788 return 0;
24eab124 7789
551c1ca1 7790 base_string = end_scale;
af6bdddf
AM		 7791 if (is_space_char (*base_string))
7792 ++base_string;
7793 if (*base_string != ')')
7794 {
4eed87de
AM		 7795 as_bad (_("expecting `)' "
7796 "after scale factor in `%s'"),
af6bdddf
AM		 7797 operand_string);
7798 return 0;
7799 }
7800 }
7801 else if (!i.index_reg)
24eab124 7802 {
4eed87de
AM		 7803 as_bad (_("expecting index register or scale factor "
7804 "after `,'; got '%c'"),
af6bdddf 7805 *base_string);
24eab124
AM		 7806 return 0;
7807 }
7808 }
af6bdddf 7809 else if (*base_string != ')')
24eab124 7810 {
4eed87de
AM		 7811 as_bad (_("expecting `,' or `)' "
7812 "after base register in `%s'"),
af6bdddf 7813 operand_string);
24eab124
AM		 7814 return 0;
7815 }
c3332e24 7816 }
af6bdddf 7817 else if (*base_string == REGISTER_PREFIX)
c3332e24 7818 {
f76bf5e0
L		 7819 end_op = strchr (base_string, ',');
7820 if (end_op)
7821 *end_op = '\0';
af6bdddf 7822 as_bad (_("bad register name `%s'"), base_string);
24eab124 7823 return 0;
c3332e24 7824 }
24eab124
AM		 7825 }
7826
7827 /* If there's an expression beginning the operand, parse it,
7828 assuming displacement_string_start and
7829 displacement_string_end are meaningful. */
7830 if (displacement_string_start != displacement_string_end)
7831 {
7832 if (!i386_displacement (displacement_string_start,
7833 displacement_string_end))
7834 return 0;
7835 }
7836
7837 /* Special case for (%dx) while doing input/output op. */
7838 if (i.base_reg
0dfbf9d7
L		 7839 && operand_type_equal (&i.base_reg->reg_type,
7840 &reg16_inoutportreg)
24eab124
AM		 7841 && i.index_reg == 0
7842 && i.log2_scale_factor == 0
7843 && i.seg[i.mem_operands] == 0
40fb9820 7844 && !operand_type_check (i.types[this_operand], disp))
24eab124 7845 {
65da13b5 7846 i.types[this_operand] = inoutportreg;
24eab124
AM		 7847 return 1;
7848 }
7849
eecb386c
AM		 7850 if (i386_index_check (operand_string) == 0)
7851 return 0;
5c07affc 7852 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7853 i.mem_operands++;
7854 }
7855 else
ce8a8b2f
AM		 7856 {
7857 /* It's not a memory operand; argh! */
24eab124
AM		 7858 as_bad (_("invalid char %s beginning operand %d `%s'"),
7859 output_invalid (*op_string),
7860 this_operand + 1,
7861 op_string);
7862 return 0;
7863 }
47926f60 7864 return 1; /* Normal return. */
252b5132
RH		 7865}
7866\f
fa94de6b
RM		 7867/* Calculate the maximum variable size (i.e., excluding fr_fix)
7868 that an rs_machine_dependent frag may reach. */
7869
7870unsigned int
7871i386_frag_max_var (fragS *frag)
7872{
7873 /* The only relaxable frags are for jumps.
7874 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7875 gas_assert (frag->fr_type == rs_machine_dependent);
7876 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
7877}
7878
ee7fcc42
AM		 7879/* md_estimate_size_before_relax()
7880
7881 Called just before relax() for rs_machine_dependent frags. The x86
7882 assembler uses these frags to handle variable size jump
7883 instructions.
7884
7885 Any symbol that is now undefined will not become defined.
7886 Return the correct fr_subtype in the frag.
7887 Return the initial "guess for variable size of frag" to caller.
7888 The guess is actually the growth beyond the fixed part. Whatever
7889 we do to grow the fixed or variable part contributes to our
7890 returned value. */
7891
252b5132 7892int
7016a5d5 7893md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 7894{
252b5132 7895 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7896 check for un-relaxable symbols. On an ELF system, we can't relax
7897 an externally visible symbol, because it may be overridden by a
7898 shared library. */
7899 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7900#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7901 || (IS_ELF
31312f95 7902 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7903 || S_IS_WEAK (fragP->fr_symbol)
7904 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7905 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7906#endif
7907#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7908 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7909 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7910#endif
7911 )
252b5132 7912 {
b98ef147
AM		 7913 /* Symbol is undefined in this segment, or we need to keep a
7914 reloc so that weak symbols can be overridden. */
7915 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7916 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7917 unsigned char *opcode;
7918 int old_fr_fix;
f6af82bd 7919
ee7fcc42 7920 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7921 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7922 else if (size == 2)
f6af82bd
AM		 7923 reloc_type = BFD_RELOC_16_PCREL;
7924 else
7925 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7926
ee7fcc42
AM		 7927 old_fr_fix = fragP->fr_fix;
7928 opcode = (unsigned char *) fragP->fr_opcode;
7929
fddf5b5b 7930 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7931 {
fddf5b5b
AM		 7932 case UNCOND_JUMP:
7933 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7934 opcode[0] = 0xe9;
252b5132 7935 fragP->fr_fix += size;
062cd5e7
AS		 7936 fix_new (fragP, old_fr_fix, size,
7937 fragP->fr_symbol,
7938 fragP->fr_offset, 1,
7939 reloc_type);
252b5132
RH		 7940 break;
7941
fddf5b5b 7942 case COND_JUMP86:
412167cb
AM		 7943 if (size == 2
7944 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7945 {
7946 /* Negate the condition, and branch past an
7947 unconditional jump. */
7948 opcode[0] ^= 1;
7949 opcode[1] = 3;
7950 /* Insert an unconditional jump. */
7951 opcode[2] = 0xe9;
7952 /* We added two extra opcode bytes, and have a two byte
7953 offset. */
7954 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7955 fix_new (fragP, old_fr_fix + 2, 2,
7956 fragP->fr_symbol,
7957 fragP->fr_offset, 1,
7958 reloc_type);
fddf5b5b
AM		 7959 break;
7960 }
7961 /* Fall through. */
7962
7963 case COND_JUMP:
412167cb
AM		 7964 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7965 {
3e02c1cc
AM		 7966 fixS *fixP;
7967
412167cb 7968 fragP->fr_fix += 1;
3e02c1cc
AM		 7969 fixP = fix_new (fragP, old_fr_fix, 1,
7970 fragP->fr_symbol,
7971 fragP->fr_offset, 1,
7972 BFD_RELOC_8_PCREL);
7973 fixP->fx_signed = 1;
412167cb
AM		 7974 break;
7975 }
93c2a809 7976
24eab124 7977 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7978 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7979 opcode[1] = opcode[0] + 0x10;
f6af82bd 7980 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7981 /* We've added an opcode byte. */
7982 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7983 fix_new (fragP, old_fr_fix + 1, size,
7984 fragP->fr_symbol,
7985 fragP->fr_offset, 1,
7986 reloc_type);
252b5132 7987 break;
fddf5b5b
AM		 7988
7989 default:
7990 BAD_CASE (fragP->fr_subtype);
7991 break;
252b5132
RH		 7992 }
7993 frag_wane (fragP);
ee7fcc42 7994 return fragP->fr_fix - old_fr_fix;
252b5132 7995 }
93c2a809 7996
93c2a809
AM		 7997 /* Guess size depending on current relax state. Initially the relax
7998 state will correspond to a short jump and we return 1, because
7999 the variable part of the frag (the branch offset) is one byte
8000 long. However, we can relax a section more than once and in that
8001 case we must either set fr_subtype back to the unrelaxed state,
8002 or return the value for the appropriate branch. */
8003 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8004}
8005
47926f60
KH		 8006/* Called after relax() is finished.
8007
8008 In: Address of frag.
8009 fr_type == rs_machine_dependent.
8010 fr_subtype is what the address relaxed to.
8011
8012 Out: Any fixSs and constants are set up.
8013 Caller will turn frag into a ".space 0". */
8014
252b5132 8015void
7016a5d5
TG		 8016md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8017 fragS *fragP)
252b5132 8018{
29b0f896 8019 unsigned char *opcode;
252b5132 8020 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8021 offsetT target_address;
8022 offsetT opcode_address;
252b5132 8023 unsigned int extension = 0;
847f7ad4 8024 offsetT displacement_from_opcode_start;
252b5132
RH		 8025
8026 opcode = (unsigned char *) fragP->fr_opcode;
8027
47926f60 8028 /* Address we want to reach in file space. */
252b5132 8029 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8030
47926f60 8031 /* Address opcode resides at in file space. */
252b5132
RH		 8032 opcode_address = fragP->fr_address + fragP->fr_fix;
8033
47926f60 8034 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8035 displacement_from_opcode_start = target_address - opcode_address;
8036
fddf5b5b 8037 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8038 {
47926f60
KH		 8039 /* Don't have to change opcode. */
8040 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8041 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8042 }
8043 else
8044 {
8045 if (no_cond_jump_promotion
8046 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8047 as_warn_where (fragP->fr_file, fragP->fr_line,
8048 _("long jump required"));
252b5132 8049
fddf5b5b
AM		 8050 switch (fragP->fr_subtype)
8051 {
8052 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8053 extension = 4; /* 1 opcode + 4 displacement */
8054 opcode[0] = 0xe9;
8055 where_to_put_displacement = &opcode[1];
8056 break;
252b5132 8057
fddf5b5b
AM		 8058 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8059 extension = 2; /* 1 opcode + 2 displacement */
8060 opcode[0] = 0xe9;
8061 where_to_put_displacement = &opcode[1];
8062 break;
252b5132 8063
fddf5b5b
AM		 8064 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8065 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8066 extension = 5; /* 2 opcode + 4 displacement */
8067 opcode[1] = opcode[0] + 0x10;
8068 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8069 where_to_put_displacement = &opcode[2];
8070 break;
252b5132 8071
fddf5b5b
AM		 8072 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8073 extension = 3; /* 2 opcode + 2 displacement */
8074 opcode[1] = opcode[0] + 0x10;
8075 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8076 where_to_put_displacement = &opcode[2];
8077 break;
252b5132 8078
fddf5b5b
AM		 8079 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
8080 extension = 4;
8081 opcode[0] ^= 1;
8082 opcode[1] = 3;
8083 opcode[2] = 0xe9;
8084 where_to_put_displacement = &opcode[3];
8085 break;
8086
8087 default:
8088 BAD_CASE (fragP->fr_subtype);
8089 break;
8090 }
252b5132 8091 }
fddf5b5b 8092
7b81dfbb
AJ		 8093 /* If size if less then four we are sure that the operand fits,
8094 but if it's 4, then it could be that the displacement is larger
8095 then -/+ 2GB. */
8096 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
8097 && object_64bit
8098 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 8099 + ((addressT) 1 << 31))
8100 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 8101 {
8102 as_bad_where (fragP->fr_file, fragP->fr_line,
8103 _("jump target out of range"));
8104 /* Make us emit 0. */
8105 displacement_from_opcode_start = extension;
8106 }
47926f60 8107 /* Now put displacement after opcode. */
252b5132
RH		 8108 md_number_to_chars ((char *) where_to_put_displacement,
8109 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 8110 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 8111 fragP->fr_fix += extension;
8112}
8113\f
7016a5d5 8114/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 8115 by our caller that we have all the info we need to fix it up.
8116
7016a5d5
TG		 8117 Parameter valP is the pointer to the value of the bits.
8118
252b5132
RH		 8119 On the 386, immediates, displacements, and data pointers are all in
8120 the same (little-endian) format, so we don't need to care about which
8121 we are handling. */
8122
94f592af 8123void
7016a5d5 8124md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 8125{
94f592af 8126 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 8127 valueT value = *valP;
252b5132 8128
f86103b7 8129#if !defined (TE_Mach)
93382f6d
AM		 8130 if (fixP->fx_pcrel)
8131 {
8132 switch (fixP->fx_r_type)
8133 {
5865bb77
ILT		 8134 default:
8135 break;
8136
d6ab8113
JB		 8137 case BFD_RELOC_64:
8138 fixP->fx_r_type = BFD_RELOC_64_PCREL;
8139 break;
93382f6d 8140 case BFD_RELOC_32:
ae8887b5 8141 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 8142 fixP->fx_r_type = BFD_RELOC_32_PCREL;
8143 break;
8144 case BFD_RELOC_16:
8145 fixP->fx_r_type = BFD_RELOC_16_PCREL;
8146 break;
8147 case BFD_RELOC_8:
8148 fixP->fx_r_type = BFD_RELOC_8_PCREL;
8149 break;
8150 }
8151 }
252b5132 8152
a161fe53 8153 if (fixP->fx_addsy != NULL
31312f95 8154 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 8155 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 8156 || fixP->fx_r_type == BFD_RELOC_16_PCREL
8157 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
8158 && !use_rela_relocations)
252b5132 8159 {
31312f95
AM		 8160 /* This is a hack. There should be a better way to handle this.
8161 This covers for the fact that bfd_install_relocation will
8162 subtract the current location (for partial_inplace, PC relative
8163 relocations); see more below. */
252b5132 8164#ifndef OBJ_AOUT
718ddfc0 8165 if (IS_ELF
252b5132
RH		 8166#ifdef TE_PE
8167 || OUTPUT_FLAVOR == bfd_target_coff_flavour
8168#endif
8169 )
8170 value += fixP->fx_where + fixP->fx_frag->fr_address;
8171#endif
8172#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8173 if (IS_ELF)
252b5132 8174 {
6539b54b 8175 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 8176
6539b54b 8177 if ((sym_seg == seg
2f66722d 8178 || (symbol_section_p (fixP->fx_addsy)
6539b54b 8179 && sym_seg != absolute_section))
af65af87 8180 && !generic_force_reloc (fixP))
2f66722d
AM		 8181 {
8182 /* Yes, we add the values in twice. This is because
6539b54b
AM		 8183 bfd_install_relocation subtracts them out again. I think
8184 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 8185 it. FIXME. */
8186 value += fixP->fx_where + fixP->fx_frag->fr_address;
8187 }
252b5132
RH		 8188 }
8189#endif
8190#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 8191 /* For some reason, the PE format does not store a
8192 section address offset for a PC relative symbol. */
8193 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 8194 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 8195 value += md_pcrel_from (fixP);
8196#endif
8197 }
fbeb56a4
DK		 8198#if defined (OBJ_COFF) && defined (TE_PE)
8199 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8200 {
8201 value -= S_GET_VALUE (fixP->fx_addsy);
8202 }
8203#endif
252b5132
RH		 8204
8205 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 8206 and we must not disappoint it. */
252b5132 8207#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8208 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 8209 switch (fixP->fx_r_type)
8210 {
8211 case BFD_RELOC_386_PLT32:
3e73aa7c 8212 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 8213 /* Make the jump instruction point to the address of the operand. At
8214 runtime we merely add the offset to the actual PLT entry. */
8215 value = -4;
8216 break;
31312f95 8217
13ae64f3
JJ		 8218 case BFD_RELOC_386_TLS_GD:
8219 case BFD_RELOC_386_TLS_LDM:
13ae64f3 8220 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8221 case BFD_RELOC_386_TLS_IE:
8222 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 8223 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 8224 case BFD_RELOC_X86_64_TLSGD:
8225 case BFD_RELOC_X86_64_TLSLD:
8226 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 8227 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 8228 value = 0; /* Fully resolved at runtime. No addend. */
8229 /* Fallthrough */
8230 case BFD_RELOC_386_TLS_LE:
8231 case BFD_RELOC_386_TLS_LDO_32:
8232 case BFD_RELOC_386_TLS_LE_32:
8233 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8234 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 8235 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 8236 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 8237 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8238 break;
8239
67a4f2b7
AO		 8240 case BFD_RELOC_386_TLS_DESC_CALL:
8241 case BFD_RELOC_X86_64_TLSDESC_CALL:
8242 value = 0; /* Fully resolved at runtime. No addend. */
8243 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8244 fixP->fx_done = 0;
8245 return;
8246
00f7efb6
JJ		 8247 case BFD_RELOC_386_GOT32:
8248 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 8249 value = 0; /* Fully resolved at runtime. No addend. */
8250 break;
47926f60
KH		 8251
8252 case BFD_RELOC_VTABLE_INHERIT:
8253 case BFD_RELOC_VTABLE_ENTRY:
8254 fixP->fx_done = 0;
94f592af 8255 return;
47926f60
KH		 8256
8257 default:
8258 break;
8259 }
8260#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 8261 *valP = value;
f86103b7 8262#endif /* !defined (TE_Mach) */
3e73aa7c 8263
3e73aa7c 8264 /* Are we finished with this relocation now? */
c6682705 8265 if (fixP->fx_addsy == NULL)
3e73aa7c 8266 fixP->fx_done = 1;
fbeb56a4
DK		 8267#if defined (OBJ_COFF) && defined (TE_PE)
8268 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8269 {
8270 fixP->fx_done = 0;
8271 /* Remember value for tc_gen_reloc. */
8272 fixP->fx_addnumber = value;
8273 /* Clear out the frag for now. */
8274 value = 0;
8275 }
8276#endif
3e73aa7c
JH		 8277 else if (use_rela_relocations)
8278 {
8279 fixP->fx_no_overflow = 1;
062cd5e7
AS		 8280 /* Remember value for tc_gen_reloc. */
8281 fixP->fx_addnumber = value;
3e73aa7c
JH		 8282 value = 0;
8283 }
f86103b7 8284
94f592af 8285 md_number_to_chars (p, value, fixP->fx_size);
252b5132 8286}
252b5132 8287\f
252b5132 8288char *
499ac353 8289md_atof (int type, char *litP, int *sizeP)
252b5132 8290{
499ac353
NC		 8291 /* This outputs the LITTLENUMs in REVERSE order;
8292 in accord with the bigendian 386. */
8293 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 8294}
8295\f
2d545b82 8296static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 8297
252b5132 8298static char *
e3bb37b5 8299output_invalid (int c)
252b5132 8300{
3882b010 8301 if (ISPRINT (c))
f9f21a03
L		 8302 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
8303 "'%c'", c);
252b5132 8304 else
f9f21a03 8305 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 8306 "(0x%x)", (unsigned char) c);
252b5132
RH		 8307 return output_invalid_buf;
8308}
8309
af6bdddf 8310/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 8311
8312static const reg_entry *
4d1bb795 8313parse_real_register (char *reg_string, char **end_op)
252b5132 8314{
af6bdddf
AM		 8315 char *s = reg_string;
8316 char *p;
252b5132
RH		 8317 char reg_name_given[MAX_REG_NAME_SIZE + 1];
8318 const reg_entry *r;
8319
8320 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8321 if (*s == REGISTER_PREFIX)
8322 ++s;
8323
8324 if (is_space_char (*s))
8325 ++s;
8326
8327 p = reg_name_given;
af6bdddf 8328 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 8329 {
8330 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 8331 return (const reg_entry *) NULL;
8332 s++;
252b5132
RH		 8333 }
8334
6588847e
DN		 8335 /* For naked regs, make sure that we are not dealing with an identifier.
8336 This prevents confusing an identifier like `eax_var' with register
8337 `eax'. */
8338 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
8339 return (const reg_entry *) NULL;
8340
af6bdddf 8341 *end_op = s;
252b5132
RH		 8342
8343 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
8344
5f47d35b 8345 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 8346 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 8347 {
5f47d35b
AM		 8348 if (is_space_char (*s))
8349 ++s;
8350 if (*s == '(')
8351 {
af6bdddf 8352 ++s;
5f47d35b
AM		 8353 if (is_space_char (*s))
8354 ++s;
8355 if (*s >= '0' && *s <= '7')
8356 {
db557034 8357 int fpr = *s - '0';
af6bdddf 8358 ++s;
5f47d35b
AM		 8359 if (is_space_char (*s))
8360 ++s;
8361 if (*s == ')')
8362 {
8363 *end_op = s + 1;
1e9cc1c2 8364 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 8365 know (r);
8366 return r + fpr;
5f47d35b 8367 }
5f47d35b 8368 }
47926f60 8369 /* We have "%st(" then garbage. */
5f47d35b
AM		 8370 return (const reg_entry *) NULL;
8371 }
8372 }
8373
a60de03c
JB		 8374 if (r == NULL || allow_pseudo_reg)
8375 return r;
8376
0dfbf9d7 8377 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8378 return (const reg_entry *) NULL;
8379
192dc9c6
JB		 8380 if ((r->reg_type.bitfield.reg32
8381 || r->reg_type.bitfield.sreg3
8382 || r->reg_type.bitfield.control
8383 || r->reg_type.bitfield.debug
8384 || r->reg_type.bitfield.test)
8385 && !cpu_arch_flags.bitfield.cpui386)
8386 return (const reg_entry *) NULL;
8387
309d3373
JB		 8388 if (r->reg_type.bitfield.floatreg
8389 && !cpu_arch_flags.bitfield.cpu8087
8390 && !cpu_arch_flags.bitfield.cpu287
8391 && !cpu_arch_flags.bitfield.cpu387)
8392 return (const reg_entry *) NULL;
8393
192dc9c6
JB		 8394 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8395 return (const reg_entry *) NULL;
8396
8397 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8398 return (const reg_entry *) NULL;
8399
40f12533
L		 8400 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8401 return (const reg_entry *) NULL;
8402
db51cc60 8403 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8404 if (!allow_index_reg
db51cc60
L		 8405 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8406 return (const reg_entry *) NULL;
8407
a60de03c
JB		 8408 if (((r->reg_flags & (RegRex64 | RegRex))
8409 || r->reg_type.bitfield.reg64)
40fb9820 8410 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8411 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8412 && flag_code != CODE_64BIT)
20f0a1fc 8413 return (const reg_entry *) NULL;
1ae00879 8414
b7240065
JB		 8415 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8416 return (const reg_entry *) NULL;
8417
252b5132
RH		 8418 return r;
8419}
4d1bb795
JB		 8420
8421/* REG_STRING starts *before* REGISTER_PREFIX. */
8422
8423static const reg_entry *
8424parse_register (char *reg_string, char **end_op)
8425{
8426 const reg_entry *r;
8427
8428 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8429 r = parse_real_register (reg_string, end_op);
8430 else
8431 r = NULL;
8432 if (!r)
8433 {
8434 char *save = input_line_pointer;
8435 char c;
8436 symbolS *symbolP;
8437
8438 input_line_pointer = reg_string;
8439 c = get_symbol_end ();
8440 symbolP = symbol_find (reg_string);
8441 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8442 {
8443 const expressionS *e = symbol_get_value_expression (symbolP);
8444
0398aac5 8445 know (e->X_op == O_register);
4eed87de 8446 know (e->X_add_number >= 0
c3fe08fa 8447 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8448 r = i386_regtab + e->X_add_number;
8449 *end_op = input_line_pointer;
8450 }
8451 *input_line_pointer = c;
8452 input_line_pointer = save;
8453 }
8454 return r;
8455}
8456
8457int
8458i386_parse_name (char *name, expressionS *e, char *nextcharP)
8459{
8460 const reg_entry *r;
8461 char *end = input_line_pointer;
8462
8463 *end = *nextcharP;
8464 r = parse_register (name, &input_line_pointer);
8465 if (r && end <= input_line_pointer)
8466 {
8467 *nextcharP = *input_line_pointer;
8468 *input_line_pointer = 0;
8469 e->X_op = O_register;
8470 e->X_add_number = r - i386_regtab;
8471 return 1;
8472 }
8473 input_line_pointer = end;
8474 *end = 0;
ee86248c 8475 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8476}
8477
8478void
8479md_operand (expressionS *e)
8480{
ee86248c
JB		 8481 char *end;
8482 const reg_entry *r;
4d1bb795 8483
ee86248c
JB		 8484 switch (*input_line_pointer)
8485 {
8486 case REGISTER_PREFIX:
8487 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8488 if (r)
8489 {
8490 e->X_op = O_register;
8491 e->X_add_number = r - i386_regtab;
8492 input_line_pointer = end;
8493 }
ee86248c
JB		 8494 break;
8495
8496 case '[':
9c2799c2 8497 gas_assert (intel_syntax);
ee86248c
JB		 8498 end = input_line_pointer++;
8499 expression (e);
8500 if (*input_line_pointer == ']')
8501 {
8502 ++input_line_pointer;
8503 e->X_op_symbol = make_expr_symbol (e);
8504 e->X_add_symbol = NULL;
8505 e->X_add_number = 0;
8506 e->X_op = O_index;
8507 }
8508 else
8509 {
8510 e->X_op = O_absent;
8511 input_line_pointer = end;
8512 }
8513 break;
4d1bb795
JB		 8514 }
8515}
8516
252b5132 8517\f
4cc782b5 8518#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8519const char *md_shortopts = "kVQ:sqn";
252b5132 8520#else
12b55ccc 8521const char *md_shortopts = "qn";
252b5132 8522#endif
6e0b89ee 8523
3e73aa7c 8524#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8525#define OPTION_64 (OPTION_MD_BASE + 1)
8526#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8527#define OPTION_MARCH (OPTION_MD_BASE + 3)
8528#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8529#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8530#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8531#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8532#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8533#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8534#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8535#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 8536#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8537#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8538#define OPTION_X32 (OPTION_MD_BASE + 14)
b3b91714 8539
99ad8390
NC		 8540struct option md_longopts[] =
8541{
3e73aa7c 8542 {"32", no_argument, NULL, OPTION_32},
321098a5 8543#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8544 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 8545 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8546#endif
8547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8548 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8549#endif
b3b91714 8550 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8551 {"march", required_argument, NULL, OPTION_MARCH},
8552 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8553 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8554 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8555 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8556 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8557 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8558 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8559 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 8560 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 8561 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8562 {NULL, no_argument, NULL, 0}
8563};
8564size_t md_longopts_size = sizeof (md_longopts);
8565
8566int
9103f4f4 8567md_parse_option (int c, char *arg)
252b5132 8568{
91d6fa6a 8569 unsigned int j;
6305a203 8570 char *arch, *next;
9103f4f4 8571
252b5132
RH		 8572 switch (c)
8573 {
12b55ccc
L		 8574 case 'n':
8575 optimize_align_code = 0;
8576 break;
8577
a38cf1db
AM		 8578 case 'q':
8579 quiet_warnings = 1;
252b5132
RH		 8580 break;
8581
8582#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8583 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8584 should be emitted or not. FIXME: Not implemented. */
8585 case 'Q':
252b5132
RH		 8586 break;
8587
8588 /* -V: SVR4 argument to print version ID. */
8589 case 'V':
8590 print_version_id ();
8591 break;
8592
a38cf1db
AM		 8593 /* -k: Ignore for FreeBSD compatibility. */
8594 case 'k':
252b5132 8595 break;
4cc782b5
ILT		 8596
8597 case 's':
8598 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8599 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8600 break;
99ad8390 8601#endif
321098a5 8602#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8603 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 8604 case OPTION_64:
8605 {
8606 const char **list, **l;
8607
3e73aa7c
JH		 8608 list = bfd_target_list ();
8609 for (l = list; *l != NULL; l++)
8620418b 8610 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8611 || strcmp (*l, "coff-x86-64") == 0
8612 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 8613 || strcmp (*l, "pei-x86-64") == 0
8614 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 8615 {
8616 default_arch = "x86_64";
8617 break;
8618 }
3e73aa7c 8619 if (*l == NULL)
2b5d6a91 8620 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 8621 free (list);
8622 }
8623 break;
8624#endif
252b5132 8625
351f65ca 8626#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8627 case OPTION_X32:
351f65ca
L		 8628 if (IS_ELF)
8629 {
8630 const char **list, **l;
8631
8632 list = bfd_target_list ();
8633 for (l = list; *l != NULL; l++)
8634 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8635 {
8636 default_arch = "x86_64:32";
8637 break;
8638 }
8639 if (*l == NULL)
2b5d6a91 8640 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 8641 free (list);
8642 }
8643 else
8644 as_fatal (_("32bit x86_64 is only supported for ELF"));
8645 break;
8646#endif
8647
6e0b89ee
AM		 8648 case OPTION_32:
8649 default_arch = "i386";
8650 break;
8651
b3b91714
AM		 8652 case OPTION_DIVIDE:
8653#ifdef SVR4_COMMENT_CHARS
8654 {
8655 char *n, *t;
8656 const char *s;
8657
8658 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8659 t = n;
8660 for (s = i386_comment_chars; *s != '\0'; s++)
8661 if (*s != '/')
8662 *t++ = *s;
8663 *t = '\0';
8664 i386_comment_chars = n;
8665 }
8666#endif
8667 break;
8668
9103f4f4 8669 case OPTION_MARCH:
6305a203
L		 8670 arch = xstrdup (arg);
8671 do
9103f4f4 8672 {
6305a203 8673 if (*arch == '.')
2b5d6a91 8674 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8675 next = strchr (arch, '+');
8676 if (next)
8677 *next++ = '\0';
91d6fa6a 8678 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8679 {
91d6fa6a 8680 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8681 {
6305a203 8682 /* Processor. */
1ded5609
JB		 8683 if (! cpu_arch[j].flags.bitfield.cpui386)
8684 continue;
8685
91d6fa6a 8686 cpu_arch_name = cpu_arch[j].name;
6305a203 8687 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8688 cpu_arch_flags = cpu_arch[j].flags;
8689 cpu_arch_isa = cpu_arch[j].type;
8690 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8691 if (!cpu_arch_tune_set)
8692 {
8693 cpu_arch_tune = cpu_arch_isa;
8694 cpu_arch_tune_flags = cpu_arch_isa_flags;
8695 }
8696 break;
8697 }
91d6fa6a
NC		 8698 else if (*cpu_arch [j].name == '.'
8699 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8700 {
8701 /* ISA entension. */
8702 i386_cpu_flags flags;
309d3373 8703
49021df2 8704 if (!cpu_arch[j].negated)
309d3373 8705 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8706 cpu_arch[j].flags);
309d3373
JB		 8707 else
8708 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8709 cpu_arch[j].flags);
0dfbf9d7 8710 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8711 {
8712 if (cpu_sub_arch_name)
8713 {
8714 char *name = cpu_sub_arch_name;
8715 cpu_sub_arch_name = concat (name,
91d6fa6a 8716 cpu_arch[j].name,
1bf57e9f 8717 (const char *) NULL);
6305a203
L		 8718 free (name);
8719 }
8720 else
91d6fa6a 8721 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8722 cpu_arch_flags = flags;
a586129e 8723 cpu_arch_isa_flags = flags;
6305a203
L		 8724 }
8725 break;
ccc9c027 8726 }
9103f4f4 8727 }
6305a203 8728
91d6fa6a 8729 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8730 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8731
8732 arch = next;
9103f4f4 8733 }
6305a203 8734 while (next != NULL );
9103f4f4
L		 8735 break;
8736
8737 case OPTION_MTUNE:
8738 if (*arg == '.')
2b5d6a91 8739 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 8740 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8741 {
91d6fa6a 8742 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8743 {
ccc9c027 8744 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8745 cpu_arch_tune = cpu_arch [j].type;
8746 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8747 break;
8748 }
8749 }
91d6fa6a 8750 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8751 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 8752 break;
8753
1efbbeb4
L		 8754 case OPTION_MMNEMONIC:
8755 if (strcasecmp (arg, "att") == 0)
8756 intel_mnemonic = 0;
8757 else if (strcasecmp (arg, "intel") == 0)
8758 intel_mnemonic = 1;
8759 else
2b5d6a91 8760 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 8761 break;
8762
8763 case OPTION_MSYNTAX:
8764 if (strcasecmp (arg, "att") == 0)
8765 intel_syntax = 0;
8766 else if (strcasecmp (arg, "intel") == 0)
8767 intel_syntax = 1;
8768 else
2b5d6a91 8769 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 8770 break;
8771
8772 case OPTION_MINDEX_REG:
8773 allow_index_reg = 1;
8774 break;
8775
8776 case OPTION_MNAKED_REG:
8777 allow_naked_reg = 1;
8778 break;
8779
8780 case OPTION_MOLD_GCC:
8781 old_gcc = 1;
1efbbeb4
L		 8782 break;
8783
c0f3af97
L		 8784 case OPTION_MSSE2AVX:
8785 sse2avx = 1;
8786 break;
8787
daf50ae7
L		 8788 case OPTION_MSSE_CHECK:
8789 if (strcasecmp (arg, "error") == 0)
7bab8ab5 8790 sse_check = check_error;
daf50ae7 8791 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 8792 sse_check = check_warning;
daf50ae7 8793 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 8794 sse_check = check_none;
daf50ae7 8795 else
2b5d6a91 8796 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 8797 break;
8798
7bab8ab5
JB		 8799 case OPTION_MOPERAND_CHECK:
8800 if (strcasecmp (arg, "error") == 0)
8801 operand_check = check_error;
8802 else if (strcasecmp (arg, "warning") == 0)
8803 operand_check = check_warning;
8804 else if (strcasecmp (arg, "none") == 0)
8805 operand_check = check_none;
8806 else
8807 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
8808 break;
8809
539f890d
L		 8810 case OPTION_MAVXSCALAR:
8811 if (strcasecmp (arg, "128") == 0)
8812 avxscalar = vex128;
8813 else if (strcasecmp (arg, "256") == 0)
8814 avxscalar = vex256;
8815 else
2b5d6a91 8816 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 8817 break;
8818
252b5132
RH		 8819 default:
8820 return 0;
8821 }
8822 return 1;
8823}
8824
8a2c8fef
L		 8825#define MESSAGE_TEMPLATE \
8826" "
8827
8828static void
1ded5609 8829show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8830{
8831 static char message[] = MESSAGE_TEMPLATE;
8832 char *start = message + 27;
8833 char *p;
8834 int size = sizeof (MESSAGE_TEMPLATE);
8835 int left;
8836 const char *name;
8837 int len;
8838 unsigned int j;
8839
8840 p = start;
8841 left = size - (start - message);
8842 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8843 {
8844 /* Should it be skipped? */
8845 if (cpu_arch [j].skip)
8846 continue;
8847
8848 name = cpu_arch [j].name;
8849 len = cpu_arch [j].len;
8850 if (*name == '.')
8851 {
8852 /* It is an extension. Skip if we aren't asked to show it. */
8853 if (ext)
8854 {
8855 name++;
8856 len--;
8857 }
8858 else
8859 continue;
8860 }
8861 else if (ext)
8862 {
8863 /* It is an processor. Skip if we show only extension. */
8864 continue;
8865 }
1ded5609
JB		 8866 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8867 {
8868 /* It is an impossible processor - skip. */
8869 continue;
8870 }
8a2c8fef
L		 8871
8872 /* Reserve 2 spaces for ", " or ",\0" */
8873 left -= len + 2;
8874
8875 /* Check if there is any room. */
8876 if (left >= 0)
8877 {
8878 if (p != start)
8879 {
8880 *p++ = ',';
8881 *p++ = ' ';
8882 }
8883 p = mempcpy (p, name, len);
8884 }
8885 else
8886 {
8887 /* Output the current message now and start a new one. */
8888 *p++ = ',';
8889 *p = '\0';
8890 fprintf (stream, "%s\n", message);
8891 p = start;
8892 left = size - (start - message) - len - 2;
8d63c93e 8893
8a2c8fef
L		 8894 gas_assert (left >= 0);
8895
8896 p = mempcpy (p, name, len);
8897 }
8898 }
8899
8900 *p = '\0';
8901 fprintf (stream, "%s\n", message);
8902}
8903
252b5132 8904void
8a2c8fef 8905md_show_usage (FILE *stream)
252b5132 8906{
4cc782b5
ILT		 8907#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8908 fprintf (stream, _("\
a38cf1db
AM		 8909 -Q ignored\n\
8910 -V print assembler version number\n\
b3b91714
AM		 8911 -k ignored\n"));
8912#endif
8913 fprintf (stream, _("\
12b55ccc 8914 -n Do not optimize code alignment\n\
b3b91714
AM		 8915 -q quieten some warnings\n"));
8916#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8917 fprintf (stream, _("\
a38cf1db 8918 -s ignored\n"));
b3b91714 8919#endif
321098a5
L		 8920#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8921 || defined (TE_PE) || defined (TE_PEP))
751d281c 8922 fprintf (stream, _("\
570561f7 8923 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8924#endif
b3b91714
AM		 8925#ifdef SVR4_COMMENT_CHARS
8926 fprintf (stream, _("\
8927 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8928#else
8929 fprintf (stream, _("\
b3b91714 8930 --divide ignored\n"));
4cc782b5 8931#endif
9103f4f4 8932 fprintf (stream, _("\
6305a203 8933 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8934 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8935 show_arch (stream, 0, 1);
8a2c8fef
L		 8936 fprintf (stream, _("\
8937 EXTENSION is combination of:\n"));
1ded5609 8938 show_arch (stream, 1, 0);
6305a203 8939 fprintf (stream, _("\
8a2c8fef 8940 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8941 show_arch (stream, 0, 0);
ba104c83 8942 fprintf (stream, _("\
c0f3af97
L		 8943 -msse2avx encode SSE instructions with VEX prefix\n"));
8944 fprintf (stream, _("\
daf50ae7
L		 8945 -msse-check=[none|error|warning]\n\
8946 check SSE instructions\n"));
8947 fprintf (stream, _("\
7bab8ab5
JB		 8948 -moperand-check=[none|error|warning]\n\
8949 check operand combinations for validity\n"));
8950 fprintf (stream, _("\
539f890d
L		 8951 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8952 length\n"));
8953 fprintf (stream, _("\
ba104c83
L		 8954 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8955 fprintf (stream, _("\
8956 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8957 fprintf (stream, _("\
8958 -mindex-reg support pseudo index registers\n"));
8959 fprintf (stream, _("\
8960 -mnaked-reg don't require `%%' prefix for registers\n"));
8961 fprintf (stream, _("\
8962 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8963}
8964
3e73aa7c 8965#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8966 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8967 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8968
8969/* Pick the target format to use. */
8970
47926f60 8971const char *
e3bb37b5 8972i386_target_format (void)
252b5132 8973{
351f65ca
L		 8974 if (!strncmp (default_arch, "x86_64", 6))
8975 {
8976 update_code_flag (CODE_64BIT, 1);
8977 if (default_arch[6] == '\0')
7f56bc95 8978 x86_elf_abi = X86_64_ABI;
351f65ca 8979 else
7f56bc95 8980 x86_elf_abi = X86_64_X32_ABI;
351f65ca 8981 }
3e73aa7c 8982 else if (!strcmp (default_arch, "i386"))
78f12dd3 8983 update_code_flag (CODE_32BIT, 1);
3e73aa7c 8984 else
2b5d6a91 8985 as_fatal (_("unknown architecture"));
89507696
JB		 8986
8987 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8988 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8989 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8990 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8991
252b5132
RH		 8992 switch (OUTPUT_FLAVOR)
8993 {
9384f2ff 8994#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8995 case bfd_target_aout_flavour:
47926f60 8996 return AOUT_TARGET_FORMAT;
4c63da97 8997#endif
9384f2ff
AM		 8998#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8999# if defined (TE_PE) || defined (TE_PEP)
9000 case bfd_target_coff_flavour:
9001 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9002# elif defined (TE_GO32)
0561d57c
JK		 9003 case bfd_target_coff_flavour:
9004 return "coff-go32";
9384f2ff 9005# else
252b5132
RH		 9006 case bfd_target_coff_flavour:
9007 return "coff-i386";
9384f2ff 9008# endif
4c63da97 9009#endif
3e73aa7c 9010#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 9011 case bfd_target_elf_flavour:
3e73aa7c 9012 {
351f65ca
L		 9013 const char *format;
9014
9015 switch (x86_elf_abi)
4fa24527 9016 {
351f65ca
L		 9017 default:
9018 format = ELF_TARGET_FORMAT;
9019 break;
7f56bc95 9020 case X86_64_ABI:
351f65ca 9021 use_rela_relocations = 1;
4fa24527 9022 object_64bit = 1;
351f65ca
L		 9023 format = ELF_TARGET_FORMAT64;
9024 break;
7f56bc95 9025 case X86_64_X32_ABI:
4fa24527 9026 use_rela_relocations = 1;
351f65ca 9027 object_64bit = 1;
862be3fb 9028 disallow_64bit_reloc = 1;
351f65ca
L		 9029 format = ELF_TARGET_FORMAT32;
9030 break;
4fa24527 9031 }
3632d14b 9032 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 9033 {
7f56bc95 9034 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 9035 as_fatal (_("Intel L1OM is 64bit only"));
9036 return ELF_TARGET_L1OM_FORMAT;
9037 }
7a9068fe
L		 9038 if (cpu_arch_isa == PROCESSOR_K1OM)
9039 {
9040 if (x86_elf_abi != X86_64_ABI)
9041 as_fatal (_("Intel K1OM is 64bit only"));
9042 return ELF_TARGET_K1OM_FORMAT;
9043 }
8a9036a4 9044 else
351f65ca 9045 return format;
3e73aa7c 9046 }
e57f8c65
TG		 9047#endif
9048#if defined (OBJ_MACH_O)
9049 case bfd_target_mach_o_flavour:
d382c579
TG		 9050 if (flag_code == CODE_64BIT)
9051 {
9052 use_rela_relocations = 1;
9053 object_64bit = 1;
9054 return "mach-o-x86-64";
9055 }
9056 else
9057 return "mach-o-i386";
4c63da97 9058#endif
252b5132
RH		 9059 default:
9060 abort ();
9061 return NULL;
9062 }
9063}
9064
47926f60 9065#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 9066
9067#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 9068void
9069i386_elf_emit_arch_note (void)
a847613f 9070{
718ddfc0 9071 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 9072 {
9073 char *p;
9074 asection *seg = now_seg;
9075 subsegT subseg = now_subseg;
9076 Elf_Internal_Note i_note;
9077 Elf_External_Note e_note;
9078 asection *note_secp;
9079 int len;
9080
9081 /* Create the .note section. */
9082 note_secp = subseg_new (".note", 0);
9083 bfd_set_section_flags (stdoutput,
9084 note_secp,
9085 SEC_HAS_CONTENTS | SEC_READONLY);
9086
9087 /* Process the arch string. */
9088 len = strlen (cpu_arch_name);
9089
9090 i_note.namesz = len + 1;
9091 i_note.descsz = 0;
9092 i_note.type = NT_ARCH;
9093 p = frag_more (sizeof (e_note.namesz));
9094 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
9095 p = frag_more (sizeof (e_note.descsz));
9096 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
9097 p = frag_more (sizeof (e_note.type));
9098 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
9099 p = frag_more (len + 1);
9100 strcpy (p, cpu_arch_name);
9101
9102 frag_align (2, 0, 0);
9103
9104 subseg_set (seg, subseg);
9105 }
9106}
9107#endif
252b5132 9108\f
252b5132 9109symbolS *
7016a5d5 9110md_undefined_symbol (char *name)
252b5132 9111{
18dc2407
ILT		 9112 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
9113 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
9114 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
9115 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 9116 {
9117 if (!GOT_symbol)
9118 {
9119 if (symbol_find (name))
9120 as_bad (_("GOT already in symbol table"));
9121 GOT_symbol = symbol_new (name, undefined_section,
9122 (valueT) 0, &zero_address_frag);
9123 };
9124 return GOT_symbol;
9125 }
252b5132
RH		 9126 return 0;
9127}
9128
9129/* Round up a section size to the appropriate boundary. */
47926f60 9130
252b5132 9131valueT
7016a5d5 9132md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 9133{
4c63da97
AM		 9134#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9135 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
9136 {
9137 /* For a.out, force the section size to be aligned. If we don't do
9138 this, BFD will align it for us, but it will not write out the
9139 final bytes of the section. This may be a bug in BFD, but it is
9140 easier to fix it here since that is how the other a.out targets
9141 work. */
9142 int align;
9143
9144 align = bfd_get_section_alignment (stdoutput, segment);
9145 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
9146 }
252b5132
RH		 9147#endif
9148
9149 return size;
9150}
9151
9152/* On the i386, PC-relative offsets are relative to the start of the
9153 next instruction. That is, the address of the offset, plus its
9154 size, since the offset is always the last part of the insn. */
9155
9156long
e3bb37b5 9157md_pcrel_from (fixS *fixP)
252b5132
RH		 9158{
9159 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
9160}
9161
9162#ifndef I386COFF
9163
9164static void
e3bb37b5 9165s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 9166{
29b0f896 9167 int temp;
252b5132 9168
8a75718c
JB		 9169#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9170 if (IS_ELF)
9171 obj_elf_section_change_hook ();
9172#endif
252b5132
RH		 9173 temp = get_absolute_expression ();
9174 subseg_set (bss_section, (subsegT) temp);
9175 demand_empty_rest_of_line ();
9176}
9177
9178#endif
9179
252b5132 9180void
e3bb37b5 9181i386_validate_fix (fixS *fixp)
252b5132
RH		 9182{
9183 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
9184 {
23df1078
JH		 9185 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
9186 {
4fa24527 9187 if (!object_64bit)
23df1078
JH		 9188 abort ();
9189 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
9190 }
9191 else
9192 {
4fa24527 9193 if (!object_64bit)
d6ab8113
JB		 9194 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
9195 else
9196 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 9197 }
252b5132
RH		 9198 fixp->fx_subsy = 0;
9199 }
9200}
9201
252b5132 9202arelent *
7016a5d5 9203tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 9204{
9205 arelent *rel;
9206 bfd_reloc_code_real_type code;
9207
9208 switch (fixp->fx_r_type)
9209 {
8ce3d284 9210#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 9211 case BFD_RELOC_SIZE32:
9212 case BFD_RELOC_SIZE64:
9213 if (S_IS_DEFINED (fixp->fx_addsy)
9214 && !S_IS_EXTERNAL (fixp->fx_addsy))
9215 {
9216 /* Resolve size relocation against local symbol to size of
9217 the symbol plus addend. */
9218 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
9219 if (fixp->fx_r_type == BFD_RELOC_SIZE32
9220 && !fits_in_unsigned_long (value))
9221 as_bad_where (fixp->fx_file, fixp->fx_line,
9222 _("symbol size computation overflow"));
9223 fixp->fx_addsy = NULL;
9224 fixp->fx_subsy = NULL;
9225 md_apply_fix (fixp, (valueT *) &value, NULL);
9226 return NULL;
9227 }
8ce3d284 9228#endif
8fd4256d 9229
3e73aa7c
JH		 9230 case BFD_RELOC_X86_64_PLT32:
9231 case BFD_RELOC_X86_64_GOT32:
9232 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 9233 case BFD_RELOC_386_PLT32:
9234 case BFD_RELOC_386_GOT32:
9235 case BFD_RELOC_386_GOTOFF:
9236 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 9237 case BFD_RELOC_386_TLS_GD:
9238 case BFD_RELOC_386_TLS_LDM:
9239 case BFD_RELOC_386_TLS_LDO_32:
9240 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9241 case BFD_RELOC_386_TLS_IE:
9242 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 9243 case BFD_RELOC_386_TLS_LE_32:
9244 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 9245 case BFD_RELOC_386_TLS_GOTDESC:
9246 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 9247 case BFD_RELOC_X86_64_TLSGD:
9248 case BFD_RELOC_X86_64_TLSLD:
9249 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9250 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 9251 case BFD_RELOC_X86_64_GOTTPOFF:
9252 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 9253 case BFD_RELOC_X86_64_TPOFF64:
9254 case BFD_RELOC_X86_64_GOTOFF64:
9255 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 9256 case BFD_RELOC_X86_64_GOT64:
9257 case BFD_RELOC_X86_64_GOTPCREL64:
9258 case BFD_RELOC_X86_64_GOTPC64:
9259 case BFD_RELOC_X86_64_GOTPLT64:
9260 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 9261 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9262 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 9263 case BFD_RELOC_RVA:
9264 case BFD_RELOC_VTABLE_ENTRY:
9265 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 9266#ifdef TE_PE
9267 case BFD_RELOC_32_SECREL:
9268#endif
252b5132
RH		 9269 code = fixp->fx_r_type;
9270 break;
dbbaec26
L		 9271 case BFD_RELOC_X86_64_32S:
9272 if (!fixp->fx_pcrel)
9273 {
9274 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9275 code = fixp->fx_r_type;
9276 break;
9277 }
252b5132 9278 default:
93382f6d 9279 if (fixp->fx_pcrel)
252b5132 9280 {
93382f6d
AM		 9281 switch (fixp->fx_size)
9282 {
9283 default:
b091f402
AM		 9284 as_bad_where (fixp->fx_file, fixp->fx_line,
9285 _("can not do %d byte pc-relative relocation"),
9286 fixp->fx_size);
93382f6d
AM		 9287 code = BFD_RELOC_32_PCREL;
9288 break;
9289 case 1: code = BFD_RELOC_8_PCREL; break;
9290 case 2: code = BFD_RELOC_16_PCREL; break;
9291 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 9292#ifdef BFD64
9293 case 8: code = BFD_RELOC_64_PCREL; break;
9294#endif
93382f6d
AM		 9295 }
9296 }
9297 else
9298 {
9299 switch (fixp->fx_size)
9300 {
9301 default:
b091f402
AM		 9302 as_bad_where (fixp->fx_file, fixp->fx_line,
9303 _("can not do %d byte relocation"),
9304 fixp->fx_size);
93382f6d
AM		 9305 code = BFD_RELOC_32;
9306 break;
9307 case 1: code = BFD_RELOC_8; break;
9308 case 2: code = BFD_RELOC_16; break;
9309 case 4: code = BFD_RELOC_32; break;
937149dd 9310#ifdef BFD64
3e73aa7c 9311 case 8: code = BFD_RELOC_64; break;
937149dd 9312#endif
93382f6d 9313 }
252b5132
RH		 9314 }
9315 break;
9316 }
252b5132 9317
d182319b
JB		 9318 if ((code == BFD_RELOC_32
9319 || code == BFD_RELOC_32_PCREL
9320 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 9321 && GOT_symbol
9322 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 9323 {
4fa24527 9324 if (!object_64bit)
d6ab8113
JB		 9325 code = BFD_RELOC_386_GOTPC;
9326 else
9327 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 9328 }
7b81dfbb
AJ		 9329 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
9330 && GOT_symbol
9331 && fixp->fx_addsy == GOT_symbol)
9332 {
9333 code = BFD_RELOC_X86_64_GOTPC64;
9334 }
252b5132
RH		 9335
9336 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 9337 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9338 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 9339
9340 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 9341
3e73aa7c
JH		 9342 if (!use_rela_relocations)
9343 {
9344 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9345 vtable entry to be used in the relocation's section offset. */
9346 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
9347 rel->address = fixp->fx_offset;
fbeb56a4
DK		 9348#if defined (OBJ_COFF) && defined (TE_PE)
9349 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
9350 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
9351 else
9352#endif
c6682705 9353 rel->addend = 0;
3e73aa7c
JH		 9354 }
9355 /* Use the rela in 64bit mode. */
252b5132 9356 else
3e73aa7c 9357 {
862be3fb
L		 9358 if (disallow_64bit_reloc)
9359 switch (code)
9360 {
862be3fb
L		 9361 case BFD_RELOC_X86_64_DTPOFF64:
9362 case BFD_RELOC_X86_64_TPOFF64:
9363 case BFD_RELOC_64_PCREL:
9364 case BFD_RELOC_X86_64_GOTOFF64:
9365 case BFD_RELOC_X86_64_GOT64:
9366 case BFD_RELOC_X86_64_GOTPCREL64:
9367 case BFD_RELOC_X86_64_GOTPC64:
9368 case BFD_RELOC_X86_64_GOTPLT64:
9369 case BFD_RELOC_X86_64_PLTOFF64:
9370 as_bad_where (fixp->fx_file, fixp->fx_line,
9371 _("cannot represent relocation type %s in x32 mode"),
9372 bfd_get_reloc_code_name (code));
9373 break;
9374 default:
9375 break;
9376 }
9377
062cd5e7
AS		 9378 if (!fixp->fx_pcrel)
9379 rel->addend = fixp->fx_offset;
9380 else
9381 switch (code)
9382 {
9383 case BFD_RELOC_X86_64_PLT32:
9384 case BFD_RELOC_X86_64_GOT32:
9385 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 9386 case BFD_RELOC_X86_64_TLSGD:
9387 case BFD_RELOC_X86_64_TLSLD:
9388 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 9389 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9390 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 9391 rel->addend = fixp->fx_offset - fixp->fx_size;
9392 break;
9393 default:
9394 rel->addend = (section->vma
9395 - fixp->fx_size
9396 + fixp->fx_addnumber
9397 + md_pcrel_from (fixp));
9398 break;
9399 }
3e73aa7c
JH		 9400 }
9401
252b5132
RH		 9402 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
9403 if (rel->howto == NULL)
9404 {
9405 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 9406 _("cannot represent relocation type %s"),
252b5132
RH		 9407 bfd_get_reloc_code_name (code));
9408 /* Set howto to a garbage value so that we can keep going. */
9409 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 9410 gas_assert (rel->howto != NULL);
252b5132
RH		 9411 }
9412
9413 return rel;
9414}
9415
ee86248c 9416#include "tc-i386-intel.c"
54cfded0 9417
a60de03c
JB		 9418void
9419tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9420{
a60de03c
JB		 9421 int saved_naked_reg;
9422 char saved_register_dot;
54cfded0 9423
a60de03c
JB		 9424 saved_naked_reg = allow_naked_reg;
9425 allow_naked_reg = 1;
9426 saved_register_dot = register_chars['.'];
9427 register_chars['.'] = '.';
9428 allow_pseudo_reg = 1;
9429 expression_and_evaluate (exp);
9430 allow_pseudo_reg = 0;
9431 register_chars['.'] = saved_register_dot;
9432 allow_naked_reg = saved_naked_reg;
9433
e96d56a1 9434 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9435 {
a60de03c
JB		 9436 if ((addressT) exp->X_add_number < i386_regtab_size)
9437 {
9438 exp->X_op = O_constant;
9439 exp->X_add_number = i386_regtab[exp->X_add_number]
9440 .dw2_regnum[flag_code >> 1];
9441 }
9442 else
9443 exp->X_op = O_illegal;
54cfded0 9444 }
54cfded0
AM		 9445}
9446
9447void
9448tc_x86_frame_initial_instructions (void)
9449{
a60de03c
JB		 9450 static unsigned int sp_regno[2];
9451
9452 if (!sp_regno[flag_code >> 1])
9453 {
9454 char *saved_input = input_line_pointer;
9455 char sp[][4] = {"esp", "rsp"};
9456 expressionS exp;
a4447b93 9457
a60de03c
JB		 9458 input_line_pointer = sp[flag_code >> 1];
9459 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9460 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9461 sp_regno[flag_code >> 1] = exp.X_add_number;
9462 input_line_pointer = saved_input;
9463 }
a4447b93 9464
61ff971f
L		 9465 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9466 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9467}
d2b2c203 9468
d7921315
L		 9469int
9470x86_dwarf2_addr_size (void)
9471{
9472#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9473 if (x86_elf_abi == X86_64_X32_ABI)
9474 return 4;
9475#endif
9476 return bfd_arch_bits_per_address (stdoutput) / 8;
9477}
9478
d2b2c203
DJ		 9479int
9480i386_elf_section_type (const char *str, size_t len)
9481{
9482 if (flag_code == CODE_64BIT
9483 && len == sizeof ("unwind") - 1
9484 && strncmp (str, "unwind", 6) == 0)
9485 return SHT_X86_64_UNWIND;
9486
9487 return -1;
9488}
bb41ade5 9489
ad5fec3b
EB		 9490#ifdef TE_SOLARIS
9491void
9492i386_solaris_fix_up_eh_frame (segT sec)
9493{
9494 if (flag_code == CODE_64BIT)
9495 elf_section_type (sec) = SHT_X86_64_UNWIND;
9496}
9497#endif
9498
bb41ade5
AM		 9499#ifdef TE_PE
9500void
9501tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9502{
91d6fa6a 9503 expressionS exp;
bb41ade5 9504
91d6fa6a
NC		 9505 exp.X_op = O_secrel;
9506 exp.X_add_symbol = symbol;
9507 exp.X_add_number = 0;
9508 emit_expr (&exp, size);
bb41ade5
AM		 9509}
9510#endif
3b22753a
L		 9511
9512#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9513/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9514
01e1a5bc 9515bfd_vma
3b22753a
L		 9516x86_64_section_letter (int letter, char **ptr_msg)
9517{
9518 if (flag_code == CODE_64BIT)
9519 {
9520 if (letter == 'l')
9521 return SHF_X86_64_LARGE;
9522
8f3bae45 9523 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9524 }
3b22753a 9525 else
8f3bae45 9526 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9527 return -1;
9528}
9529
01e1a5bc 9530bfd_vma
3b22753a
L		 9531x86_64_section_word (char *str, size_t len)
9532{
8620418b 9533 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9534 return SHF_X86_64_LARGE;
9535
9536 return -1;
9537}
9538
9539static void
9540handle_large_common (int small ATTRIBUTE_UNUSED)
9541{
9542 if (flag_code != CODE_64BIT)
9543 {
9544 s_comm_internal (0, elf_common_parse);
9545 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9546 }
9547 else
9548 {
9549 static segT lbss_section;
9550 asection *saved_com_section_ptr = elf_com_section_ptr;
9551 asection *saved_bss_section = bss_section;
9552
9553 if (lbss_section == NULL)
9554 {
9555 flagword applicable;
9556 segT seg = now_seg;
9557 subsegT subseg = now_subseg;
9558
9559 /* The .lbss section is for local .largecomm symbols. */
9560 lbss_section = subseg_new (".lbss", 0);
9561 applicable = bfd_applicable_section_flags (stdoutput);
9562 bfd_set_section_flags (stdoutput, lbss_section,
9563 applicable & SEC_ALLOC);
9564 seg_info (lbss_section)->bss = 1;
9565
9566 subseg_set (seg, subseg);
9567 }
9568
9569 elf_com_section_ptr = &_bfd_elf_large_com_section;
9570 bss_section = lbss_section;
9571
9572 s_comm_internal (0, elf_common_parse);
9573
9574 elf_com_section_ptr = saved_com_section_ptr;
9575 bss_section = saved_bss_section;
9576 }
9577}
9578#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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