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* elflink.c (_bfd_elf_gc_mark_hook): New function.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
050dfa73 92static void swap_imm_operands PARAMS ((void));
29b0f896
AM		 93static void optimize_imm PARAMS ((void));
94static void optimize_disp PARAMS ((void));
95static int match_template PARAMS ((void));
96static int check_string PARAMS ((void));
97static int process_suffix PARAMS ((void));
98static int check_byte_reg PARAMS ((void));
99static int check_long_reg PARAMS ((void));
100static int check_qword_reg PARAMS ((void));
101static int check_word_reg PARAMS ((void));
102static int finalize_imm PARAMS ((void));
103static int process_operands PARAMS ((void));
104static const seg_entry *build_modrm_byte PARAMS ((void));
105static void output_insn PARAMS ((void));
106static void output_branch PARAMS ((void));
107static void output_jump PARAMS ((void));
108static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 109static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
29b0f896
AM		 113#ifndef I386COFF
114static void s_bss PARAMS ((int));
252b5132 115#endif
17d4e2a2
L		 116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117static void handle_large_common (int small ATTRIBUTE_UNUSED);
118#endif
252b5132 119
a847613f 120static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 121
252b5132 122/* 'md_assemble ()' gathers together information and puts it into a
47926f60 123 i386_insn. */
252b5132 124
520dc8e8
AM		 125union i386_op
126 {
127 expressionS *disps;
128 expressionS *imms;
129 const reg_entry *regs;
130 };
131
252b5132
RH		 132struct _i386_insn
133 {
47926f60 134 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 135 template tm;
136
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
139 char suffix;
140
47926f60 141 /* OPERANDS gives the number of given operands. */
252b5132
RH		 142 unsigned int operands;
143
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
47926f60 146 operands. */
252b5132
RH		 147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148
149 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 150 use OP[i] for the corresponding operand. */
252b5132
RH		 151 unsigned int types[MAX_OPERANDS];
152
520dc8e8
AM		 153 /* Displacement expression, immediate expression, or register for each
154 operand. */
155 union i386_op op[MAX_OPERANDS];
252b5132 156
3e73aa7c
JH		 157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159#define Operand_PCrel 1
160
252b5132 161 /* Relocation type for operand */
f86103b7 162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 163
252b5132
RH		 164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
169
170 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 171 explicit segment overrides are given. */
ce8a8b2f 172 const seg_entry *seg[2];
252b5132
RH		 173
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
178
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
181
182 modrm_byte rm;
3e73aa7c 183 rex_byte rex;
252b5132
RH		 184 sib_byte sib;
185 };
186
187typedef struct _i386_insn i386_insn;
188
189/* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
32137342 191const char extra_symbol_chars[] = "*%-(["
252b5132 192#ifdef LEX_AT
32137342
NC		 193 "@"
194#endif
195#ifdef LEX_QM
196 "?"
252b5132 197#endif
32137342 198 ;
252b5132 199
29b0f896
AM		 200#if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 202 && !defined (TE_GNU) \
29b0f896 203 && !defined (TE_LINUX) \
32137342 204 && !defined (TE_NETWARE) \
29b0f896
AM		 205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
252b5132 207/* This array holds the chars that always start a comment. If the
b3b91714
AM		 208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210const char *i386_comment_chars = "#/";
211#define SVR4_COMMENT_CHARS 1
252b5132 212#define PREFIX_SEPARATOR '\\'
252b5132 213
b3b91714
AM		 214#else
215const char *i386_comment_chars = "#";
216#define PREFIX_SEPARATOR '/'
217#endif
218
252b5132
RH		 219/* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 223 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
252b5132 226 '/' isn't otherwise defined. */
b3b91714 227const char line_comment_chars[] = "#/";
252b5132 228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
47926f60 275/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 276static expressionS disp_expressions[2], im_expressions[2];
277
47926f60
KH		 278/* Current operand we are working on. */
279static int this_operand;
252b5132 280
3e73aa7c
JH		 281/* We support four different modes. FLAG_CODE variable is used to distinguish
282 these. */
283
284enum flag_code {
285 CODE_32BIT,
286 CODE_16BIT,
287 CODE_64BIT };
f3c180ae 288#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 289
290static enum flag_code flag_code;
4fa24527 291static unsigned int object_64bit;
3e73aa7c
JH		 292static int use_rela_relocations = 0;
293
294/* The names used to print error messages. */
b77a7acd 295static const char *flag_code_names[] =
3e73aa7c
JH		 296 {
297 "32",
298 "16",
299 "64"
300 };
252b5132 301
47926f60
KH		 302/* 1 for intel syntax,
303 0 if att syntax. */
304static int intel_syntax = 0;
252b5132 305
47926f60
KH		 306/* 1 if register prefix % not required. */
307static int allow_naked_reg = 0;
252b5132 308
47926f60
KH		 309/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312static char stackop_size = '\0';
eecb386c 313
12b55ccc
L		 314/* Non-zero to optimize code alignment. */
315int optimize_align_code = 1;
316
47926f60
KH		 317/* Non-zero to quieten some warnings. */
318static int quiet_warnings = 0;
a38cf1db 319
47926f60
KH		 320/* CPU name. */
321static const char *cpu_arch_name = NULL;
5c6af06e 322static const char *cpu_sub_arch_name = NULL;
a38cf1db 323
47926f60 324/* CPU feature flags. */
29b0f896 325static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 326
ccc9c027
L		 327/* If we have selected a cpu we are generating instructions for. */
328static int cpu_arch_tune_set = 0;
329
9103f4f4
L		 330/* Cpu we are generating instructions for. */
331static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
332
333/* CPU feature flags of cpu we are generating instructions for. */
334static unsigned int cpu_arch_tune_flags = 0;
335
ccc9c027
L		 336/* CPU instruction set architecture used. */
337static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
338
9103f4f4
L		 339/* CPU feature flags of instruction set architecture used. */
340static unsigned int cpu_arch_isa_flags = 0;
341
fddf5b5b
AM		 342/* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344static unsigned int no_cond_jump_promotion = 0;
345
29b0f896 346/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 347static symbolS *GOT_symbol;
29b0f896 348
a4447b93
RH		 349/* The dwarf2 return column, adjusted for 32 or 64 bit. */
350unsigned int x86_dwarf2_return_column;
351
352/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353int x86_cie_data_alignment;
354
252b5132 355/* Interface to relax_segment.
fddf5b5b
AM		 356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
252b5132 359
47926f60 360/* Types. */
93c2a809
AM		 361#define UNCOND_JUMP 0
362#define COND_JUMP 1
363#define COND_JUMP86 2
fddf5b5b 364
47926f60 365/* Sizes. */
252b5132
RH		 366#define CODE16 1
367#define SMALL 0
29b0f896 368#define SMALL16 (SMALL | CODE16)
252b5132 369#define BIG 2
29b0f896 370#define BIG16 (BIG | CODE16)
252b5132
RH		 371
372#ifndef INLINE
373#ifdef __GNUC__
374#define INLINE __inline__
375#else
376#define INLINE
377#endif
378#endif
379
fddf5b5b
AM		 380#define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382#define TYPE_FROM_RELAX_STATE(s) \
383 ((s) >> 2)
384#define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 386
387/* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
394
395const relax_typeS md_relax_table[] =
396{
24eab124
AM		 397 /* The fields are:
398 1) most positive reach of this state,
399 2) most negative reach of this state,
93c2a809 400 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 401 4) which index into the table to try if we can't fit into this one. */
252b5132 402
fddf5b5b 403 /* UNCOND_JUMP states. */
93c2a809
AM		 404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
252b5132 408 {0, 0, 4, 0},
93c2a809
AM		 409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 411 {0, 0, 2, 0},
412
93c2a809
AM		 413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
418 {0, 0, 5, 0},
fddf5b5b 419 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 420 1 extra opcode byte, 2 displacement bytes. */
421 {0, 0, 3, 0},
422
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
428 {0, 0, 5, 0},
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
431 {0, 0, 4, 0}
252b5132
RH		 432};
433
9103f4f4
L		 434static const arch_entry cpu_arch[] =
435{
436 {"generic32", PROCESSOR_GENERIC32,
d32cad65 437 Cpu186|Cpu286|Cpu386},
9103f4f4 438 {"generic64", PROCESSOR_GENERIC64,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 440 |CpuMMX2|CpuSSE|CpuSSE2},
441 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 442 0},
9103f4f4 443 {"i186", PROCESSOR_UNKNOWN,
d32cad65 444 Cpu186},
9103f4f4 445 {"i286", PROCESSOR_UNKNOWN,
d32cad65 446 Cpu186|Cpu286},
9103f4f4 447 {"i386", PROCESSOR_GENERIC32,
d32cad65 448 Cpu186|Cpu286|Cpu386},
9103f4f4 449 {"i486", PROCESSOR_I486,
d32cad65 450 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 451 {"i586", PROCESSOR_PENTIUM,
d32cad65 452 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 453 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 455 {"pentium", PROCESSOR_PENTIUM,
d32cad65 456 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 457 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 458 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 459 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 461 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 462 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 463 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 464 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 465 |CpuMMX2|CpuSSE|CpuSSE2},
466 {"prescott", PROCESSOR_NOCONA,
d32cad65 467 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
469 {"nocona", PROCESSOR_NOCONA,
d32cad65 470 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
472 {"yonah", PROCESSOR_YONAH,
d32cad65 473 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 474 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
475 {"merom", PROCESSOR_MEROM,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 477 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuMNI},
478 {"k6", PROCESSOR_K6,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 480 {"k6_2", PROCESSOR_K6,
d32cad65 481 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 482 {"athlon", PROCESSOR_ATHLON,
d32cad65 483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 484 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
485 {"sledgehammer", PROCESSOR_K8,
d32cad65 486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
488 {"opteron", PROCESSOR_K8,
d32cad65 489 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 490 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
491 {"k8", PROCESSOR_K8,
d32cad65 492 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 493 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 494 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 495 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
496 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
497 |CpuABM},
9103f4f4
L		 498 {".mmx", PROCESSOR_UNKNOWN,
499 CpuMMX},
500 {".sse", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE},
502 {".sse2", PROCESSOR_UNKNOWN,
503 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
504 {".sse3", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
506 {".3dnow", PROCESSOR_UNKNOWN,
507 CpuMMX|Cpu3dnow},
508 {".3dnowa", PROCESSOR_UNKNOWN,
509 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
510 {".padlock", PROCESSOR_UNKNOWN,
511 CpuPadLock},
512 {".pacifica", PROCESSOR_UNKNOWN,
513 CpuSVME},
514 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 515 CpuSVME},
516 {".sse4a", PROCESSOR_UNKNOWN,
517 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
518 {".abm", PROCESSOR_UNKNOWN,
519 CpuABM}
e413e4e9
AM		 520};
521
29b0f896
AM		 522const pseudo_typeS md_pseudo_table[] =
523{
524#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
525 {"align", s_align_bytes, 0},
526#else
527 {"align", s_align_ptwo, 0},
528#endif
529 {"arch", set_cpu_arch, 0},
530#ifndef I386COFF
531 {"bss", s_bss, 0},
532#endif
533 {"ffloat", float_cons, 'f'},
534 {"dfloat", float_cons, 'd'},
535 {"tfloat", float_cons, 'x'},
536 {"value", cons, 2},
d182319b 537 {"slong", signed_cons, 4},
29b0f896
AM		 538 {"noopt", s_ignore, 0},
539 {"optim", s_ignore, 0},
540 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
541 {"code16", set_code_flag, CODE_16BIT},
542 {"code32", set_code_flag, CODE_32BIT},
543 {"code64", set_code_flag, CODE_64BIT},
544 {"intel_syntax", set_intel_syntax, 1},
545 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 548#else
549 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 552#endif
6482c264
NC		 553#ifdef TE_PE
554 {"secrel32", pe_directive_secrel, 0},
555#endif
29b0f896
AM		 556 {0, 0, 0}
557};
558
559/* For interface with expression (). */
560extern char *input_line_pointer;
561
562/* Hash table for instruction mnemonic lookup. */
563static struct hash_control *op_hash;
564
565/* Hash table for register lookup. */
566static struct hash_control *reg_hash;
567\f
252b5132
RH		 568void
569i386_align_code (fragP, count)
570 fragS *fragP;
571 int count;
572{
ce8a8b2f
AM		 573 /* Various efficient no-op patterns for aligning code labels.
574 Note: Don't try to assemble the instructions in the comments.
575 0L and 0w are not legal. */
252b5132
RH		 576 static const char f32_1[] =
577 {0x90}; /* nop */
578 static const char f32_2[] =
ccc9c027 579 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 580 static const char f32_3[] =
581 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
582 static const char f32_4[] =
583 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
584 static const char f32_5[] =
585 {0x90, /* nop */
586 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
587 static const char f32_6[] =
588 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
589 static const char f32_7[] =
590 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
591 static const char f32_8[] =
592 {0x90, /* nop */
593 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
594 static const char f32_9[] =
595 {0x89,0xf6, /* movl %esi,%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_10[] =
598 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_11[] =
601 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_12[] =
604 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
605 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
606 static const char f32_13[] =
607 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
608 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
609 static const char f32_14[] =
610 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
611 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
612 static const char f32_15[] =
613 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
614 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 615 static const char f16_3[] =
616 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 617 static const char f16_4[] =
618 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
619 static const char f16_5[] =
620 {0x90, /* nop */
621 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
622 static const char f16_6[] =
623 {0x89,0xf6, /* mov %si,%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char f16_7[] =
626 {0x8d,0x74,0x00, /* lea 0(%si),%si */
627 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
628 static const char f16_8[] =
629 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
630 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
634 };
635 static const char *const f16_patt[] = {
c3332e24 636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 637 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
638 };
ccc9c027
L		 639 /* nopl (%[re]ax) */
640 static const char alt_3[] =
641 {0x0f,0x1f,0x00};
642 /* nopl 0(%[re]ax) */
643 static const char alt_4[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 /* data16
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11[] =
666 {0x66,
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* data16
669 data16
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12[] =
672 {0x66,
673 0x66,
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
675 /* data16
676 data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13[] =
680 {0x66,
681 0x66,
682 0x66,
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
684 /* data16
685 data16
686 data16
687 data16
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14[] =
690 {0x66,
691 0x66,
692 0x66,
693 0x66,
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
695 /* data16
696 data16
697 data16
698 data16
699 data16
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15[] =
702 {0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
719 nopl 0L(%[re]ax) */
720 static const char alt_short_13[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 /* nopl 0L(%[re]ax)
724 nopl 0L(%[re]ax) */
725 static const char alt_short_14[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 /* nopl 0L(%[re]ax)
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
736 alt_short_14, alt_short_15
737 };
738 static const char *const alt_long_patt[] = {
739 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
740 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
741 alt_long_14, alt_long_15
742 };
252b5132 743
33fef721
JH		 744 if (count <= 0 || count > 15)
745 return;
3e73aa7c 746
ccc9c027
L		 747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
749
750 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
751 f32_patt will be used.
050dfa73 752 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ccc9c027
L		 753 3. For PROCESSOR_MEROM, alt_long_patt will be used.
754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
755 PROCESSOR_YONAH, PROCESSOR_MEROM, PROCESSOR_K6, PROCESSOR_ATHLON
756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
757
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
760
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
763
764 if (flag_code == CODE_16BIT)
765 {
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
768 if (count > 8)
769 /* Adjust jump offset. */
770 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
771 }
772 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 773 {
33fef721
JH		 774 int i;
775 int nnops = (count + 3) / 4;
776 int len = count / nnops;
777 int remains = count - nnops * len;
778 int pos = 0;
779
ccc9c027
L		 780 /* The recommended way to pad 64bit code is to use NOPs preceded
781 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 782 for (i = 0; i < remains; i++)
252b5132 783 {
33fef721
JH		 784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
785 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
786 pos += len + 1;
787 }
788 for (; i < nnops; i++)
789 {
790 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
791 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
792 pos += len;
252b5132 793 }
252b5132 794 }
33fef721 795 else
ccc9c027
L		 796 {
797 const char *const *patt = NULL;
798
799 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
800 {
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune)
803 {
804 case PROCESSOR_UNKNOWN:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags & Cpu686) != 0)
808 patt = alt_short_patt;
809 else
810 patt = f32_patt;
811 break;
812 case PROCESSOR_MEROM:
813 patt = alt_long_patt;
814 break;
815 case PROCESSOR_PENTIUMPRO:
816 case PROCESSOR_PENTIUM4:
817 case PROCESSOR_NOCONA:
818 case PROCESSOR_YONAH:
819 case PROCESSOR_K6:
820 case PROCESSOR_ATHLON:
821 case PROCESSOR_K8:
822 case PROCESSOR_GENERIC64:
050dfa73 823 case PROCESSOR_AMDFAM10:
ccc9c027
L		 824 patt = alt_short_patt;
825 break;
826 case PROCESSOR_I486:
827 case PROCESSOR_PENTIUM:
828 case PROCESSOR_GENERIC32:
829 patt = f32_patt;
830 break;
831 }
832 }
833 else
834 {
835 switch (cpu_arch_tune)
836 {
837 case PROCESSOR_UNKNOWN:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
840 abort ();
841 break;
842
843 case PROCESSOR_I486:
844 case PROCESSOR_PENTIUM:
845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
848 case PROCESSOR_YONAH:
849 case PROCESSOR_K6:
850 case PROCESSOR_ATHLON:
851 case PROCESSOR_K8:
050dfa73 852 case PROCESSOR_AMDFAM10:
ccc9c027
L		 853 case PROCESSOR_GENERIC32:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
855 for Cpu686. */
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_short_patt;
858 else
859 patt = f32_patt;
860 break;
861 case PROCESSOR_MEROM:
862 if ((cpu_arch_isa_flags & Cpu686) != 0)
863 patt = alt_long_patt;
864 else
865 patt = f32_patt;
866 break;
867 case PROCESSOR_GENERIC64:
868 patt = alt_short_patt;
869 break;
870 }
871 }
872
33fef721 873 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 874 patt[count - 1], count);
875 }
33fef721 876 fragP->fr_var = count;
252b5132
RH		 877}
878
252b5132
RH		 879static INLINE unsigned int
880mode_from_disp_size (t)
881 unsigned int t;
882{
3e73aa7c 883 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 884}
885
886static INLINE int
887fits_in_signed_byte (num)
847f7ad4 888 offsetT num;
252b5132
RH		 889{
890 return (num >= -128) && (num <= 127);
47926f60 891}
252b5132
RH		 892
893static INLINE int
894fits_in_unsigned_byte (num)
847f7ad4 895 offsetT num;
252b5132
RH		 896{
897 return (num & 0xff) == num;
47926f60 898}
252b5132
RH		 899
900static INLINE int
901fits_in_unsigned_word (num)
847f7ad4 902 offsetT num;
252b5132
RH		 903{
904 return (num & 0xffff) == num;
47926f60 905}
252b5132
RH		 906
907static INLINE int
908fits_in_signed_word (num)
847f7ad4 909 offsetT num;
252b5132
RH		 910{
911 return (-32768 <= num) && (num <= 32767);
47926f60 912}
3e73aa7c
JH		 913static INLINE int
914fits_in_signed_long (num)
915 offsetT num ATTRIBUTE_UNUSED;
916{
917#ifndef BFD64
918 return 1;
919#else
920 return (!(((offsetT) -1 << 31) & num)
921 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
922#endif
923} /* fits_in_signed_long() */
924static INLINE int
925fits_in_unsigned_long (num)
926 offsetT num ATTRIBUTE_UNUSED;
927{
928#ifndef BFD64
929 return 1;
930#else
931 return (num & (((offsetT) 2 << 31) - 1)) == num;
932#endif
933} /* fits_in_unsigned_long() */
252b5132
RH		 934
935static int
936smallest_imm_type (num)
847f7ad4 937 offsetT num;
252b5132 938{
d32cad65 939 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 940 {
941 /* This code is disabled on the 486 because all the Imm1 forms
942 in the opcode table are slower on the i486. They're the
943 versions with the implicitly specified single-position
944 displacement, which has another syntax if you really want to
945 use that form. */
946 if (num == 1)
3e73aa7c 947 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 948 }
252b5132 949 return (fits_in_signed_byte (num)
3e73aa7c 950 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 951 : fits_in_unsigned_byte (num)
3e73aa7c 952 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 953 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 954 ? (Imm16 | Imm32 | Imm32S | Imm64)
955 : fits_in_signed_long (num)
956 ? (Imm32 | Imm32S | Imm64)
957 : fits_in_unsigned_long (num)
958 ? (Imm32 | Imm64)
959 : Imm64);
47926f60 960}
252b5132 961
847f7ad4
AM		 962static offsetT
963offset_in_range (val, size)
964 offsetT val;
965 int size;
966{
508866be 967 addressT mask;
ba2adb93 968
847f7ad4
AM		 969 switch (size)
970 {
508866be
L		 971 case 1: mask = ((addressT) 1 << 8) - 1; break;
972 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 973 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 974#ifdef BFD64
975 case 8: mask = ((addressT) 2 << 63) - 1; break;
976#endif
47926f60 977 default: abort ();
847f7ad4
AM		 978 }
979
ba2adb93 980 /* If BFD64, sign extend val. */
3e73aa7c
JH		 981 if (!use_rela_relocations)
982 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
983 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 984
47926f60 985 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 986 {
987 char buf1[40], buf2[40];
988
989 sprint_value (buf1, val);
990 sprint_value (buf2, val & mask);
991 as_warn (_("%s shortened to %s"), buf1, buf2);
992 }
993 return val & mask;
994}
995
252b5132
RH		 996/* Returns 0 if attempting to add a prefix where one from the same
997 class already exists, 1 if non rep/repne added, 2 if rep/repne
998 added. */
999static int
1000add_prefix (prefix)
1001 unsigned int prefix;
1002{
1003 int ret = 1;
b1905489 1004 unsigned int q;
252b5132 1005
29b0f896
AM		 1006 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1007 && flag_code == CODE_64BIT)
b1905489
JB		 1008 {
1009 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1010 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1011 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1012 ret = 0;
1013 q = REX_PREFIX;
1014 }
3e73aa7c 1015 else
b1905489
JB		 1016 {
1017 switch (prefix)
1018 {
1019 default:
1020 abort ();
1021
1022 case CS_PREFIX_OPCODE:
1023 case DS_PREFIX_OPCODE:
1024 case ES_PREFIX_OPCODE:
1025 case FS_PREFIX_OPCODE:
1026 case GS_PREFIX_OPCODE:
1027 case SS_PREFIX_OPCODE:
1028 q = SEG_PREFIX;
1029 break;
1030
1031 case REPNE_PREFIX_OPCODE:
1032 case REPE_PREFIX_OPCODE:
1033 ret = 2;
1034 /* fall thru */
1035 case LOCK_PREFIX_OPCODE:
1036 q = LOCKREP_PREFIX;
1037 break;
1038
1039 case FWAIT_OPCODE:
1040 q = WAIT_PREFIX;
1041 break;
1042
1043 case ADDR_PREFIX_OPCODE:
1044 q = ADDR_PREFIX;
1045 break;
1046
1047 case DATA_PREFIX_OPCODE:
1048 q = DATA_PREFIX;
1049 break;
1050 }
1051 if (i.prefix[q] != 0)
1052 ret = 0;
1053 }
252b5132 1054
b1905489 1055 if (ret)
252b5132 1056 {
b1905489
JB		 1057 if (!i.prefix[q])
1058 ++i.prefixes;
1059 i.prefix[q] |= prefix;
252b5132 1060 }
b1905489
JB		 1061 else
1062 as_bad (_("same type of prefix used twice"));
252b5132 1063
252b5132
RH		 1064 return ret;
1065}
1066
1067static void
3e73aa7c 1068set_code_flag (value)
e5cb08ac 1069 int value;
eecb386c 1070{
3e73aa7c
JH		 1071 flag_code = value;
1072 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1073 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1074 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1075 {
1076 as_bad (_("64bit mode not supported on this CPU."));
1077 }
1078 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1079 {
1080 as_bad (_("32bit mode not supported on this CPU."));
1081 }
eecb386c
AM		 1082 stackop_size = '\0';
1083}
1084
1085static void
3e73aa7c
JH		 1086set_16bit_gcc_code_flag (new_code_flag)
1087 int new_code_flag;
252b5132 1088{
3e73aa7c
JH		 1089 flag_code = new_code_flag;
1090 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1091 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1092 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1093}
1094
1095static void
1096set_intel_syntax (syntax_flag)
eecb386c 1097 int syntax_flag;
252b5132
RH		 1098{
1099 /* Find out if register prefixing is specified. */
1100 int ask_naked_reg = 0;
1101
1102 SKIP_WHITESPACE ();
29b0f896 1103 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1104 {
1105 char *string = input_line_pointer;
1106 int e = get_symbol_end ();
1107
47926f60 1108 if (strcmp (string, "prefix") == 0)
252b5132 1109 ask_naked_reg = 1;
47926f60 1110 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1111 ask_naked_reg = -1;
1112 else
d0b47220 1113 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1114 *input_line_pointer = e;
1115 }
1116 demand_empty_rest_of_line ();
c3332e24 1117
252b5132
RH		 1118 intel_syntax = syntax_flag;
1119
1120 if (ask_naked_reg == 0)
f86103b7
AM		 1121 allow_naked_reg = (intel_syntax
1122 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1123 else
1124 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 1125
1126 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1127 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 1128}
1129
e413e4e9
AM		 1130static void
1131set_cpu_arch (dummy)
47926f60 1132 int dummy ATTRIBUTE_UNUSED;
e413e4e9 1133{
47926f60 1134 SKIP_WHITESPACE ();
e413e4e9 1135
29b0f896 1136 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1137 {
1138 char *string = input_line_pointer;
1139 int e = get_symbol_end ();
9103f4f4 1140 unsigned int i;
e413e4e9 1141
9103f4f4 1142 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1143 {
1144 if (strcmp (string, cpu_arch[i].name) == 0)
1145 {
5c6af06e
JB		 1146 if (*string != '.')
1147 {
1148 cpu_arch_name = cpu_arch[i].name;
1149 cpu_sub_arch_name = NULL;
1150 cpu_arch_flags = (cpu_arch[i].flags
1151 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1152 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1153 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1154 if (!cpu_arch_tune_set)
1155 {
1156 cpu_arch_tune = cpu_arch_isa;
1157 cpu_arch_tune_flags = cpu_arch_isa_flags;
1158 }
5c6af06e
JB		 1159 break;
1160 }
1161 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1162 {
1163 cpu_sub_arch_name = cpu_arch[i].name;
1164 cpu_arch_flags |= cpu_arch[i].flags;
1165 }
1166 *input_line_pointer = e;
1167 demand_empty_rest_of_line ();
1168 return;
e413e4e9
AM		 1169 }
1170 }
9103f4f4 1171 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1172 as_bad (_("no such architecture: `%s'"), string);
1173
1174 *input_line_pointer = e;
1175 }
1176 else
1177 as_bad (_("missing cpu architecture"));
1178
fddf5b5b
AM		 1179 no_cond_jump_promotion = 0;
1180 if (*input_line_pointer == ','
29b0f896 1181 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1182 {
1183 char *string = ++input_line_pointer;
1184 int e = get_symbol_end ();
1185
1186 if (strcmp (string, "nojumps") == 0)
1187 no_cond_jump_promotion = 1;
1188 else if (strcmp (string, "jumps") == 0)
1189 ;
1190 else
1191 as_bad (_("no such architecture modifier: `%s'"), string);
1192
1193 *input_line_pointer = e;
1194 }
1195
e413e4e9
AM		 1196 demand_empty_rest_of_line ();
1197}
1198
b9d79e03
JH		 1199unsigned long
1200i386_mach ()
1201{
1202 if (!strcmp (default_arch, "x86_64"))
1203 return bfd_mach_x86_64;
1204 else if (!strcmp (default_arch, "i386"))
1205 return bfd_mach_i386_i386;
1206 else
1207 as_fatal (_("Unknown architecture"));
1208}
b9d79e03 1209\f
252b5132
RH		 1210void
1211md_begin ()
1212{
1213 const char *hash_err;
1214
47926f60 1215 /* Initialize op_hash hash table. */
252b5132
RH		 1216 op_hash = hash_new ();
1217
1218 {
29b0f896
AM		 1219 const template *optab;
1220 templates *core_optab;
252b5132 1221
47926f60
KH		 1222 /* Setup for loop. */
1223 optab = i386_optab;
252b5132
RH		 1224 core_optab = (templates *) xmalloc (sizeof (templates));
1225 core_optab->start = optab;
1226
1227 while (1)
1228 {
1229 ++optab;
1230 if (optab->name == NULL
1231 || strcmp (optab->name, (optab - 1)->name) != 0)
1232 {
1233 /* different name --> ship out current template list;
47926f60 1234 add to hash table; & begin anew. */
252b5132
RH		 1235 core_optab->end = optab;
1236 hash_err = hash_insert (op_hash,
1237 (optab - 1)->name,
1238 (PTR) core_optab);
1239 if (hash_err)
1240 {
252b5132
RH		 1241 as_fatal (_("Internal Error: Can't hash %s: %s"),
1242 (optab - 1)->name,
1243 hash_err);
1244 }
1245 if (optab->name == NULL)
1246 break;
1247 core_optab = (templates *) xmalloc (sizeof (templates));
1248 core_optab->start = optab;
1249 }
1250 }
1251 }
1252
47926f60 1253 /* Initialize reg_hash hash table. */
252b5132
RH		 1254 reg_hash = hash_new ();
1255 {
29b0f896 1256 const reg_entry *regtab;
252b5132
RH		 1257
1258 for (regtab = i386_regtab;
1259 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1260 regtab++)
1261 {
1262 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1263 if (hash_err)
3e73aa7c
JH		 1264 as_fatal (_("Internal Error: Can't hash %s: %s"),
1265 regtab->reg_name,
1266 hash_err);
252b5132
RH		 1267 }
1268 }
1269
47926f60 1270 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1271 {
29b0f896
AM		 1272 int c;
1273 char *p;
252b5132
RH		 1274
1275 for (c = 0; c < 256; c++)
1276 {
3882b010 1277 if (ISDIGIT (c))
252b5132
RH		 1278 {
1279 digit_chars[c] = c;
1280 mnemonic_chars[c] = c;
1281 register_chars[c] = c;
1282 operand_chars[c] = c;
1283 }
3882b010 1284 else if (ISLOWER (c))
252b5132
RH		 1285 {
1286 mnemonic_chars[c] = c;
1287 register_chars[c] = c;
1288 operand_chars[c] = c;
1289 }
3882b010 1290 else if (ISUPPER (c))
252b5132 1291 {
3882b010 1292 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1293 register_chars[c] = mnemonic_chars[c];
1294 operand_chars[c] = c;
1295 }
1296
3882b010 1297 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1298 identifier_chars[c] = c;
1299 else if (c >= 128)
1300 {
1301 identifier_chars[c] = c;
1302 operand_chars[c] = c;
1303 }
1304 }
1305
1306#ifdef LEX_AT
1307 identifier_chars['@'] = '@';
32137342
NC		 1308#endif
1309#ifdef LEX_QM
1310 identifier_chars['?'] = '?';
1311 operand_chars['?'] = '?';
252b5132 1312#endif
252b5132 1313 digit_chars['-'] = '-';
791fe849 1314 mnemonic_chars['-'] = '-';
252b5132
RH		 1315 identifier_chars['_'] = '_';
1316 identifier_chars['.'] = '.';
1317
1318 for (p = operand_special_chars; *p != '\0'; p++)
1319 operand_chars[(unsigned char) *p] = *p;
1320 }
1321
1322#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1323 if (IS_ELF)
252b5132
RH		 1324 {
1325 record_alignment (text_section, 2);
1326 record_alignment (data_section, 2);
1327 record_alignment (bss_section, 2);
1328 }
1329#endif
a4447b93
RH		 1330
1331 if (flag_code == CODE_64BIT)
1332 {
1333 x86_dwarf2_return_column = 16;
1334 x86_cie_data_alignment = -8;
1335 }
1336 else
1337 {
1338 x86_dwarf2_return_column = 8;
1339 x86_cie_data_alignment = -4;
1340 }
252b5132
RH		 1341}
1342
1343void
1344i386_print_statistics (file)
1345 FILE *file;
1346{
1347 hash_print_statistics (file, "i386 opcode", op_hash);
1348 hash_print_statistics (file, "i386 register", reg_hash);
1349}
1350\f
252b5132
RH		 1351#ifdef DEBUG386
1352
ce8a8b2f 1353/* Debugging routines for md_assemble. */
252b5132
RH		 1354static void pi PARAMS ((char *, i386_insn *));
1355static void pte PARAMS ((template *));
1356static void pt PARAMS ((unsigned int));
1357static void pe PARAMS ((expressionS *));
1358static void ps PARAMS ((symbolS *));
1359
1360static void
1361pi (line, x)
1362 char *line;
1363 i386_insn *x;
1364{
09f131f2 1365 unsigned int i;
252b5132
RH		 1366
1367 fprintf (stdout, "%s: template ", line);
1368 pte (&x->tm);
09f131f2
JH		 1369 fprintf (stdout, " address: base %s index %s scale %x\n",
1370 x->base_reg ? x->base_reg->reg_name : "none",
1371 x->index_reg ? x->index_reg->reg_name : "none",
1372 x->log2_scale_factor);
1373 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1374 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1375 fprintf (stdout, " sib: base %x index %x scale %x\n",
1376 x->sib.base, x->sib.index, x->sib.scale);
1377 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1378 (x->rex & REX_MODE64) != 0,
1379 (x->rex & REX_EXTX) != 0,
1380 (x->rex & REX_EXTY) != 0,
1381 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1382 for (i = 0; i < x->operands; i++)
1383 {
1384 fprintf (stdout, " #%d: ", i + 1);
1385 pt (x->types[i]);
1386 fprintf (stdout, "\n");
1387 if (x->types[i]
3f4438ab 1388 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1389 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1390 if (x->types[i] & Imm)
520dc8e8 1391 pe (x->op[i].imms);
252b5132 1392 if (x->types[i] & Disp)
520dc8e8 1393 pe (x->op[i].disps);
252b5132
RH		 1394 }
1395}
1396
1397static void
1398pte (t)
1399 template *t;
1400{
09f131f2 1401 unsigned int i;
252b5132 1402 fprintf (stdout, " %d operands ", t->operands);
47926f60 1403 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1404 if (t->extension_opcode != None)
1405 fprintf (stdout, "ext %x ", t->extension_opcode);
1406 if (t->opcode_modifier & D)
1407 fprintf (stdout, "D");
1408 if (t->opcode_modifier & W)
1409 fprintf (stdout, "W");
1410 fprintf (stdout, "\n");
1411 for (i = 0; i < t->operands; i++)
1412 {
1413 fprintf (stdout, " #%d type ", i + 1);
1414 pt (t->operand_types[i]);
1415 fprintf (stdout, "\n");
1416 }
1417}
1418
1419static void
1420pe (e)
1421 expressionS *e;
1422{
24eab124 1423 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1424 fprintf (stdout, " add_number %ld (%lx)\n",
1425 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1426 if (e->X_add_symbol)
1427 {
1428 fprintf (stdout, " add_symbol ");
1429 ps (e->X_add_symbol);
1430 fprintf (stdout, "\n");
1431 }
1432 if (e->X_op_symbol)
1433 {
1434 fprintf (stdout, " op_symbol ");
1435 ps (e->X_op_symbol);
1436 fprintf (stdout, "\n");
1437 }
1438}
1439
1440static void
1441ps (s)
1442 symbolS *s;
1443{
1444 fprintf (stdout, "%s type %s%s",
1445 S_GET_NAME (s),
1446 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1447 segment_name (S_GET_SEGMENT (s)));
1448}
1449
7b81dfbb 1450static struct type_name
252b5132
RH		 1451 {
1452 unsigned int mask;
1453 char *tname;
1454 }
7b81dfbb 1455const type_names[] =
252b5132
RH		 1456{
1457 { Reg8, "r8" },
1458 { Reg16, "r16" },
1459 { Reg32, "r32" },
09f131f2 1460 { Reg64, "r64" },
252b5132
RH		 1461 { Imm8, "i8" },
1462 { Imm8S, "i8s" },
1463 { Imm16, "i16" },
1464 { Imm32, "i32" },
09f131f2
JH		 1465 { Imm32S, "i32s" },
1466 { Imm64, "i64" },
252b5132
RH		 1467 { Imm1, "i1" },
1468 { BaseIndex, "BaseIndex" },
1469 { Disp8, "d8" },
1470 { Disp16, "d16" },
1471 { Disp32, "d32" },
09f131f2
JH		 1472 { Disp32S, "d32s" },
1473 { Disp64, "d64" },
252b5132
RH		 1474 { InOutPortReg, "InOutPortReg" },
1475 { ShiftCount, "ShiftCount" },
1476 { Control, "control reg" },
1477 { Test, "test reg" },
1478 { Debug, "debug reg" },
1479 { FloatReg, "FReg" },
1480 { FloatAcc, "FAcc" },
1481 { SReg2, "SReg2" },
1482 { SReg3, "SReg3" },
1483 { Acc, "Acc" },
1484 { JumpAbsolute, "Jump Absolute" },
1485 { RegMMX, "rMMX" },
3f4438ab 1486 { RegXMM, "rXMM" },
252b5132
RH		 1487 { EsSeg, "es" },
1488 { 0, "" }
1489};
1490
1491static void
1492pt (t)
1493 unsigned int t;
1494{
29b0f896 1495 const struct type_name *ty;
252b5132 1496
09f131f2
JH		 1497 for (ty = type_names; ty->mask; ty++)
1498 if (t & ty->mask)
1499 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1500 fflush (stdout);
1501}
1502
1503#endif /* DEBUG386 */
1504\f
252b5132 1505static bfd_reloc_code_real_type
3956db08 1506reloc (unsigned int size,
64e74474
AM		 1507 int pcrel,
1508 int sign,
1509 bfd_reloc_code_real_type other)
252b5132 1510{
47926f60 1511 if (other != NO_RELOC)
3956db08
JB		 1512 {
1513 reloc_howto_type *reloc;
1514
1515 if (size == 8)
1516 switch (other)
1517 {
64e74474
AM		 1518 case BFD_RELOC_X86_64_GOT32:
1519 return BFD_RELOC_X86_64_GOT64;
1520 break;
1521 case BFD_RELOC_X86_64_PLTOFF64:
1522 return BFD_RELOC_X86_64_PLTOFF64;
1523 break;
1524 case BFD_RELOC_X86_64_GOTPC32:
1525 other = BFD_RELOC_X86_64_GOTPC64;
1526 break;
1527 case BFD_RELOC_X86_64_GOTPCREL:
1528 other = BFD_RELOC_X86_64_GOTPCREL64;
1529 break;
1530 case BFD_RELOC_X86_64_TPOFF32:
1531 other = BFD_RELOC_X86_64_TPOFF64;
1532 break;
1533 case BFD_RELOC_X86_64_DTPOFF32:
1534 other = BFD_RELOC_X86_64_DTPOFF64;
1535 break;
1536 default:
1537 break;
3956db08 1538 }
e05278af
JB		 1539
1540 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1541 if (size == 4 && flag_code != CODE_64BIT)
1542 sign = -1;
1543
3956db08
JB		 1544 reloc = bfd_reloc_type_lookup (stdoutput, other);
1545 if (!reloc)
1546 as_bad (_("unknown relocation (%u)"), other);
1547 else if (size != bfd_get_reloc_size (reloc))
1548 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1549 bfd_get_reloc_size (reloc),
1550 size);
1551 else if (pcrel && !reloc->pc_relative)
1552 as_bad (_("non-pc-relative relocation for pc-relative field"));
1553 else if ((reloc->complain_on_overflow == complain_overflow_signed
1554 && !sign)
1555 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1556 && sign > 0))
3956db08
JB		 1557 as_bad (_("relocated field and relocation type differ in signedness"));
1558 else
1559 return other;
1560 return NO_RELOC;
1561 }
252b5132
RH		 1562
1563 if (pcrel)
1564 {
3e73aa7c 1565 if (!sign)
3956db08 1566 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1567 switch (size)
1568 {
1569 case 1: return BFD_RELOC_8_PCREL;
1570 case 2: return BFD_RELOC_16_PCREL;
1571 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1572 case 8: return BFD_RELOC_64_PCREL;
252b5132 1573 }
3956db08 1574 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1575 }
1576 else
1577 {
3956db08 1578 if (sign > 0)
e5cb08ac 1579 switch (size)
3e73aa7c
JH		 1580 {
1581 case 4: return BFD_RELOC_X86_64_32S;
1582 }
1583 else
1584 switch (size)
1585 {
1586 case 1: return BFD_RELOC_8;
1587 case 2: return BFD_RELOC_16;
1588 case 4: return BFD_RELOC_32;
1589 case 8: return BFD_RELOC_64;
1590 }
3956db08
JB		 1591 as_bad (_("cannot do %s %u byte relocation"),
1592 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1593 }
1594
bfb32b52 1595 abort ();
252b5132
RH		 1596 return BFD_RELOC_NONE;
1597}
1598
47926f60
KH		 1599/* Here we decide which fixups can be adjusted to make them relative to
1600 the beginning of the section instead of the symbol. Basically we need
1601 to make sure that the dynamic relocations are done correctly, so in
1602 some cases we force the original symbol to be used. */
1603
252b5132 1604int
c0c949c7 1605tc_i386_fix_adjustable (fixP)
31312f95 1606 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1607{
6d249963 1608#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1609 if (!IS_ELF)
31312f95
AM		 1610 return 1;
1611
a161fe53
AM		 1612 /* Don't adjust pc-relative references to merge sections in 64-bit
1613 mode. */
1614 if (use_rela_relocations
1615 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1616 && fixP->fx_pcrel)
252b5132 1617 return 0;
31312f95 1618
8d01d9a9
AJ		 1619 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1620 and changed later by validate_fix. */
1621 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1622 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1623 return 0;
1624
ce8a8b2f 1625 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1626 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1627 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1628 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1629 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1630 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1631 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1632 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1633 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1634 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1635 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1636 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1637 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1638 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1639 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1640 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1641 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1642 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1643 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1644 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1645 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1646 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1647 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1648 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1649 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1650 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1652 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1653 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1654 return 0;
31312f95 1655#endif
252b5132
RH		 1656 return 1;
1657}
252b5132 1658
29b0f896 1659static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1660
1661static int
252b5132 1662intel_float_operand (mnemonic)
29b0f896 1663 const char *mnemonic;
252b5132 1664{
9306ca4a
JB		 1665 /* Note that the value returned is meaningful only for opcodes with (memory)
1666 operands, hence the code here is free to improperly handle opcodes that
1667 have no operands (for better performance and smaller code). */
1668
1669 if (mnemonic[0] != 'f')
1670 return 0; /* non-math */
1671
1672 switch (mnemonic[1])
1673 {
1674 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1675 the fs segment override prefix not currently handled because no
1676 call path can make opcodes without operands get here */
1677 case 'i':
1678 return 2 /* integer op */;
1679 case 'l':
1680 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1681 return 3; /* fldcw/fldenv */
1682 break;
1683 case 'n':
1684 if (mnemonic[2] != 'o' /* fnop */)
1685 return 3; /* non-waiting control op */
1686 break;
1687 case 'r':
1688 if (mnemonic[2] == 's')
1689 return 3; /* frstor/frstpm */
1690 break;
1691 case 's':
1692 if (mnemonic[2] == 'a')
1693 return 3; /* fsave */
1694 if (mnemonic[2] == 't')
1695 {
1696 switch (mnemonic[3])
1697 {
1698 case 'c': /* fstcw */
1699 case 'd': /* fstdw */
1700 case 'e': /* fstenv */
1701 case 's': /* fsts[gw] */
1702 return 3;
1703 }
1704 }
1705 break;
1706 case 'x':
1707 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1708 return 0; /* fxsave/fxrstor are not really math ops */
1709 break;
1710 }
252b5132 1711
9306ca4a 1712 return 1;
252b5132
RH		 1713}
1714
1715/* This is the guts of the machine-dependent assembler. LINE points to a
1716 machine dependent instruction. This function is supposed to emit
1717 the frags/bytes it assembles to. */
1718
1719void
1720md_assemble (line)
1721 char *line;
1722{
252b5132 1723 int j;
252b5132
RH		 1724 char mnemonic[MAX_MNEM_SIZE];
1725
47926f60 1726 /* Initialize globals. */
252b5132
RH		 1727 memset (&i, '\0', sizeof (i));
1728 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1729 i.reloc[j] = NO_RELOC;
252b5132
RH		 1730 memset (disp_expressions, '\0', sizeof (disp_expressions));
1731 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1732 save_stack_p = save_stack;
252b5132
RH		 1733
1734 /* First parse an instruction mnemonic & call i386_operand for the operands.
1735 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1736 start of a (possibly prefixed) mnemonic. */
252b5132 1737
29b0f896
AM		 1738 line = parse_insn (line, mnemonic);
1739 if (line == NULL)
1740 return;
252b5132 1741
29b0f896
AM		 1742 line = parse_operands (line, mnemonic);
1743 if (line == NULL)
1744 return;
252b5132 1745
050dfa73
MM		 1746 /* The order of the immediates should be reversed
1747 for 2 immediates extrq and insertq instructions */
1748 if ((i.imm_operands == 2) &&
1749 ((strcmp (mnemonic, "extrq") == 0)
1750 || (strcmp (mnemonic, "insertq") == 0)))
1751 {
1752 swap_imm_operands ();
1753 /* "extrq" and insertq" are the only two instructions whose operands
1754 have to be reversed even though they have two immediate operands.
1755 */
1756 if (intel_syntax)
1757 swap_operands ();
1758 }
1759
29b0f896
AM		 1760 /* Now we've parsed the mnemonic into a set of templates, and have the
1761 operands at hand. */
1762
1763 /* All intel opcodes have reversed operands except for "bound" and
1764 "enter". We also don't reverse intersegment "jmp" and "call"
1765 instructions with 2 immediate operands so that the immediate segment
050dfa73 1766 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1767 if (intel_syntax && i.operands > 1
1768 && (strcmp (mnemonic, "bound") != 0)
30123838 1769 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1770 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1771 swap_operands ();
1772
1773 if (i.imm_operands)
1774 optimize_imm ();
1775
b300c311
L		 1776 /* Don't optimize displacement for movabs since it only takes 64bit
1777 displacement. */
1778 if (i.disp_operands
1779 && (flag_code != CODE_64BIT
1780 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1781 optimize_disp ();
1782
1783 /* Next, we find a template that matches the given insn,
1784 making sure the overlap of the given operands types is consistent
1785 with the template operand types. */
252b5132 1786
29b0f896
AM		 1787 if (!match_template ())
1788 return;
252b5132 1789
cd61ebfe
AM		 1790 if (intel_syntax)
1791 {
1792 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1793 if (SYSV386_COMPAT
1794 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1795 i.tm.base_opcode ^= FloatR;
1796
1797 /* Zap movzx and movsx suffix. The suffix may have been set from
1798 "word ptr" or "byte ptr" on the source operand, but we'll use
1799 the suffix later to choose the destination register. */
1800 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1801 {
1802 if (i.reg_operands < 2
1803 && !i.suffix
1804 && (~i.tm.opcode_modifier
1805 & (No_bSuf
1806 | No_wSuf
1807 | No_lSuf
1808 | No_sSuf
1809 | No_xSuf
1810 | No_qSuf)))
1811 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1812
1813 i.suffix = 0;
1814 }
cd61ebfe 1815 }
24eab124 1816
29b0f896
AM		 1817 if (i.tm.opcode_modifier & FWait)
1818 if (!add_prefix (FWAIT_OPCODE))
1819 return;
252b5132 1820
29b0f896
AM		 1821 /* Check string instruction segment overrides. */
1822 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1823 {
1824 if (!check_string ())
5dd0794d 1825 return;
29b0f896 1826 }
5dd0794d 1827
29b0f896
AM		 1828 if (!process_suffix ())
1829 return;
e413e4e9 1830
29b0f896
AM		 1831 /* Make still unresolved immediate matches conform to size of immediate
1832 given in i.suffix. */
1833 if (!finalize_imm ())
1834 return;
252b5132 1835
29b0f896
AM		 1836 if (i.types[0] & Imm1)
1837 i.imm_operands = 0; /* kludge for shift insns. */
1838 if (i.types[0] & ImplicitRegister)
1839 i.reg_operands--;
1840 if (i.types[1] & ImplicitRegister)
1841 i.reg_operands--;
1842 if (i.types[2] & ImplicitRegister)
1843 i.reg_operands--;
252b5132 1844
29b0f896
AM		 1845 if (i.tm.opcode_modifier & ImmExt)
1846 {
02fc3089
L		 1847 expressionS *exp;
1848
ca164297
L		 1849 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1850 {
67c1ffbe 1851 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1852 operands with an opcode suffix which is coded in the same
1853 place as an 8-bit immediate field would be. Here we check
1854 those operands and remove them afterwards. */
1855 unsigned int x;
1856
a4622f40 1857 for (x = 0; x < i.operands; x++)
ca164297
L		 1858 if (i.op[x].regs->reg_num != x)
1859 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1860 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1861 i.operands = 0;
1862 }
1863
29b0f896
AM		 1864 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1865 opcode suffix which is coded in the same place as an 8-bit
1866 immediate field would be. Here we fake an 8-bit immediate
1867 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1868
29b0f896 1869 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1870
29b0f896
AM		 1871 exp = &im_expressions[i.imm_operands++];
1872 i.op[i.operands].imms = exp;
1873 i.types[i.operands++] = Imm8;
1874 exp->X_op = O_constant;
1875 exp->X_add_number = i.tm.extension_opcode;
1876 i.tm.extension_opcode = None;
1877 }
252b5132 1878
29b0f896
AM		 1879 /* For insns with operands there are more diddles to do to the opcode. */
1880 if (i.operands)
1881 {
1882 if (!process_operands ())
1883 return;
1884 }
1885 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1886 {
1887 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1888 as_warn (_("translating to `%sp'"), i.tm.name);
1889 }
252b5132 1890
29b0f896
AM		 1891 /* Handle conversion of 'int $3' --> special int3 insn. */
1892 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1893 {
1894 i.tm.base_opcode = INT3_OPCODE;
1895 i.imm_operands = 0;
1896 }
252b5132 1897
29b0f896
AM		 1898 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1899 && i.op[0].disps->X_op == O_constant)
1900 {
1901 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1902 the absolute address given by the constant. Since ix86 jumps and
1903 calls are pc relative, we need to generate a reloc. */
1904 i.op[0].disps->X_add_symbol = &abs_symbol;
1905 i.op[0].disps->X_op = O_symbol;
1906 }
252b5132 1907
29b0f896
AM		 1908 if ((i.tm.opcode_modifier & Rex64) != 0)
1909 i.rex |= REX_MODE64;
252b5132 1910
29b0f896
AM		 1911 /* For 8 bit registers we need an empty rex prefix. Also if the
1912 instruction already has a prefix, we need to convert old
1913 registers to new ones. */
773f551c 1914
29b0f896
AM		 1915 if (((i.types[0] & Reg8) != 0
1916 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1917 || ((i.types[1] & Reg8) != 0
1918 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1919 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1920 && i.rex != 0))
1921 {
1922 int x;
726c5dcd 1923
29b0f896
AM		 1924 i.rex |= REX_OPCODE;
1925 for (x = 0; x < 2; x++)
1926 {
1927 /* Look for 8 bit operand that uses old registers. */
1928 if ((i.types[x] & Reg8) != 0
1929 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1930 {
29b0f896
AM		 1931 /* In case it is "hi" register, give up. */
1932 if (i.op[x].regs->reg_num > 3)
0477af35 1933 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1934 i.op[x].regs->reg_name);
773f551c 1935
29b0f896
AM		 1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1939
1940 i.op[x].regs = i.op[x].regs + 8;
773f551c 1941 }
29b0f896
AM		 1942 }
1943 }
773f551c 1944
29b0f896
AM		 1945 if (i.rex != 0)
1946 add_prefix (REX_OPCODE | i.rex);
1947
1948 /* We are ready to output the insn. */
1949 output_insn ();
1950}
1951
1952static char *
1953parse_insn (line, mnemonic)
1954 char *line;
1955 char *mnemonic;
1956{
1957 char *l = line;
1958 char *token_start = l;
1959 char *mnem_p;
5c6af06e
JB		 1960 int supported;
1961 const template *t;
29b0f896
AM		 1962
1963 /* Non-zero if we found a prefix only acceptable with string insns. */
1964 const char *expecting_string_instruction = NULL;
45288df1 1965
29b0f896
AM		 1966 while (1)
1967 {
1968 mnem_p = mnemonic;
1969 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1970 {
1971 mnem_p++;
1972 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1973 {
29b0f896
AM		 1974 as_bad (_("no such instruction: `%s'"), token_start);
1975 return NULL;
1976 }
1977 l++;
1978 }
1979 if (!is_space_char (*l)
1980 && *l != END_OF_INSN
e44823cf
JB		 1981 && (intel_syntax
1982 || (*l != PREFIX_SEPARATOR
1983 && *l != ',')))
29b0f896
AM		 1984 {
1985 as_bad (_("invalid character %s in mnemonic"),
1986 output_invalid (*l));
1987 return NULL;
1988 }
1989 if (token_start == l)
1990 {
e44823cf 1991 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1992 as_bad (_("expecting prefix; got nothing"));
1993 else
1994 as_bad (_("expecting mnemonic; got nothing"));
1995 return NULL;
1996 }
45288df1 1997
29b0f896
AM		 1998 /* Look up instruction (or prefix) via hash table. */
1999 current_templates = hash_find (op_hash, mnemonic);
47926f60 2000
29b0f896
AM		 2001 if (*l != END_OF_INSN
2002 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2003 && current_templates
2004 && (current_templates->start->opcode_modifier & IsPrefix))
2005 {
2dd88dca
JB		 2006 if (current_templates->start->cpu_flags
2007 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2008 {
2009 as_bad ((flag_code != CODE_64BIT
2010 ? _("`%s' is only supported in 64-bit mode")
2011 : _("`%s' is not supported in 64-bit mode")),
2012 current_templates->start->name);
2013 return NULL;
2014 }
29b0f896
AM		 2015 /* If we are in 16-bit mode, do not allow addr16 or data16.
2016 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2017 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2018 && flag_code != CODE_64BIT
2019 && (((current_templates->start->opcode_modifier & Size32) != 0)
2020 ^ (flag_code == CODE_16BIT)))
2021 {
2022 as_bad (_("redundant %s prefix"),
2023 current_templates->start->name);
2024 return NULL;
45288df1 2025 }
29b0f896
AM		 2026 /* Add prefix, checking for repeated prefixes. */
2027 switch (add_prefix (current_templates->start->base_opcode))
2028 {
2029 case 0:
2030 return NULL;
2031 case 2:
2032 expecting_string_instruction = current_templates->start->name;
2033 break;
2034 }
2035 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2036 token_start = ++l;
2037 }
2038 else
2039 break;
2040 }
45288df1 2041
29b0f896
AM		 2042 if (!current_templates)
2043 {
2044 /* See if we can get a match by trimming off a suffix. */
2045 switch (mnem_p[-1])
2046 {
2047 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2048 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2049 i.suffix = SHORT_MNEM_SUFFIX;
2050 else
29b0f896
AM		 2051 case BYTE_MNEM_SUFFIX:
2052 case QWORD_MNEM_SUFFIX:
2053 i.suffix = mnem_p[-1];
2054 mnem_p[-1] = '\0';
2055 current_templates = hash_find (op_hash, mnemonic);
2056 break;
2057 case SHORT_MNEM_SUFFIX:
2058 case LONG_MNEM_SUFFIX:
2059 if (!intel_syntax)
2060 {
2061 i.suffix = mnem_p[-1];
2062 mnem_p[-1] = '\0';
2063 current_templates = hash_find (op_hash, mnemonic);
2064 }
2065 break;
252b5132 2066
29b0f896
AM		 2067 /* Intel Syntax. */
2068 case 'd':
2069 if (intel_syntax)
2070 {
9306ca4a 2071 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2072 i.suffix = SHORT_MNEM_SUFFIX;
2073 else
2074 i.suffix = LONG_MNEM_SUFFIX;
2075 mnem_p[-1] = '\0';
2076 current_templates = hash_find (op_hash, mnemonic);
2077 }
2078 break;
2079 }
2080 if (!current_templates)
2081 {
2082 as_bad (_("no such instruction: `%s'"), token_start);
2083 return NULL;
2084 }
2085 }
252b5132 2086
29b0f896
AM		 2087 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2088 {
2089 /* Check for a branch hint. We allow ",pt" and ",pn" for
2090 predict taken and predict not taken respectively.
2091 I'm not sure that branch hints actually do anything on loop
2092 and jcxz insns (JumpByte) for current Pentium4 chips. They
2093 may work in the future and it doesn't hurt to accept them
2094 now. */
2095 if (l[0] == ',' && l[1] == 'p')
2096 {
2097 if (l[2] == 't')
2098 {
2099 if (!add_prefix (DS_PREFIX_OPCODE))
2100 return NULL;
2101 l += 3;
2102 }
2103 else if (l[2] == 'n')
2104 {
2105 if (!add_prefix (CS_PREFIX_OPCODE))
2106 return NULL;
2107 l += 3;
2108 }
2109 }
2110 }
2111 /* Any other comma loses. */
2112 if (*l == ',')
2113 {
2114 as_bad (_("invalid character %s in mnemonic"),
2115 output_invalid (*l));
2116 return NULL;
2117 }
252b5132 2118
29b0f896 2119 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2120 supported = 0;
2121 for (t = current_templates->start; t < current_templates->end; ++t)
2122 {
2123 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2124 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2125 supported |= 1;
5c6af06e 2126 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2127 supported |= 2;
5c6af06e
JB		 2128 }
2129 if (!(supported & 2))
2130 {
2131 as_bad (flag_code == CODE_64BIT
2132 ? _("`%s' is not supported in 64-bit mode")
2133 : _("`%s' is only supported in 64-bit mode"),
2134 current_templates->start->name);
2135 return NULL;
2136 }
2137 if (!(supported & 1))
29b0f896 2138 {
5c6af06e
JB		 2139 as_warn (_("`%s' is not supported on `%s%s'"),
2140 current_templates->start->name,
2141 cpu_arch_name,
2142 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2143 }
2144 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2145 {
2146 as_warn (_("use .code16 to ensure correct addressing mode"));
2147 }
252b5132 2148
29b0f896 2149 /* Check for rep/repne without a string instruction. */
f41bbced 2150 if (expecting_string_instruction)
29b0f896 2151 {
f41bbced
JB		 2152 static templates override;
2153
2154 for (t = current_templates->start; t < current_templates->end; ++t)
2155 if (t->opcode_modifier & IsString)
2156 break;
2157 if (t >= current_templates->end)
2158 {
2159 as_bad (_("expecting string instruction after `%s'"),
64e74474 2160 expecting_string_instruction);
f41bbced
JB		 2161 return NULL;
2162 }
2163 for (override.start = t; t < current_templates->end; ++t)
2164 if (!(t->opcode_modifier & IsString))
2165 break;
2166 override.end = t;
2167 current_templates = &override;
29b0f896 2168 }
252b5132 2169
29b0f896
AM		 2170 return l;
2171}
252b5132 2172
29b0f896
AM		 2173static char *
2174parse_operands (l, mnemonic)
2175 char *l;
2176 const char *mnemonic;
2177{
2178 char *token_start;
3138f287 2179
29b0f896
AM		 2180 /* 1 if operand is pending after ','. */
2181 unsigned int expecting_operand = 0;
252b5132 2182
29b0f896
AM		 2183 /* Non-zero if operand parens not balanced. */
2184 unsigned int paren_not_balanced;
2185
2186 while (*l != END_OF_INSN)
2187 {
2188 /* Skip optional white space before operand. */
2189 if (is_space_char (*l))
2190 ++l;
2191 if (!is_operand_char (*l) && *l != END_OF_INSN)
2192 {
2193 as_bad (_("invalid character %s before operand %d"),
2194 output_invalid (*l),
2195 i.operands + 1);
2196 return NULL;
2197 }
2198 token_start = l; /* after white space */
2199 paren_not_balanced = 0;
2200 while (paren_not_balanced || *l != ',')
2201 {
2202 if (*l == END_OF_INSN)
2203 {
2204 if (paren_not_balanced)
2205 {
2206 if (!intel_syntax)
2207 as_bad (_("unbalanced parenthesis in operand %d."),
2208 i.operands + 1);
2209 else
2210 as_bad (_("unbalanced brackets in operand %d."),
2211 i.operands + 1);
2212 return NULL;
2213 }
2214 else
2215 break; /* we are done */
2216 }
2217 else if (!is_operand_char (*l) && !is_space_char (*l))
2218 {
2219 as_bad (_("invalid character %s in operand %d"),
2220 output_invalid (*l),
2221 i.operands + 1);
2222 return NULL;
2223 }
2224 if (!intel_syntax)
2225 {
2226 if (*l == '(')
2227 ++paren_not_balanced;
2228 if (*l == ')')
2229 --paren_not_balanced;
2230 }
2231 else
2232 {
2233 if (*l == '[')
2234 ++paren_not_balanced;
2235 if (*l == ']')
2236 --paren_not_balanced;
2237 }
2238 l++;
2239 }
2240 if (l != token_start)
2241 { /* Yes, we've read in another operand. */
2242 unsigned int operand_ok;
2243 this_operand = i.operands++;
2244 if (i.operands > MAX_OPERANDS)
2245 {
2246 as_bad (_("spurious operands; (%d operands/instruction max)"),
2247 MAX_OPERANDS);
2248 return NULL;
2249 }
2250 /* Now parse operand adding info to 'i' as we go along. */
2251 END_STRING_AND_SAVE (l);
2252
2253 if (intel_syntax)
2254 operand_ok =
2255 i386_intel_operand (token_start,
2256 intel_float_operand (mnemonic));
2257 else
2258 operand_ok = i386_operand (token_start);
2259
2260 RESTORE_END_STRING (l);
2261 if (!operand_ok)
2262 return NULL;
2263 }
2264 else
2265 {
2266 if (expecting_operand)
2267 {
2268 expecting_operand_after_comma:
2269 as_bad (_("expecting operand after ','; got nothing"));
2270 return NULL;
2271 }
2272 if (*l == ',')
2273 {
2274 as_bad (_("expecting operand before ','; got nothing"));
2275 return NULL;
2276 }
2277 }
7f3f1ea2 2278
29b0f896
AM		 2279 /* Now *l must be either ',' or END_OF_INSN. */
2280 if (*l == ',')
2281 {
2282 if (*++l == END_OF_INSN)
2283 {
2284 /* Just skip it, if it's \n complain. */
2285 goto expecting_operand_after_comma;
2286 }
2287 expecting_operand = 1;
2288 }
2289 }
2290 return l;
2291}
7f3f1ea2 2292
050dfa73
MM		 2293static void
2294swap_imm_operands ()
2295{
2296 union i386_op temp_op;
2297 unsigned int temp_type;
2298 enum bfd_reloc_code_real temp_reloc;
2299 int xchg1 = 0;
2300 int xchg2 = 1;
2301
2302 temp_type = i.types[xchg2];
2303 i.types[xchg2] = i.types[xchg1];
2304 i.types[xchg1] = temp_type;
2305 temp_op = i.op[xchg2];
2306 i.op[xchg2] = i.op[xchg1];
2307 i.op[xchg1] = temp_op;
2308 temp_reloc = i.reloc[xchg2];
2309 i.reloc[xchg2] = i.reloc[xchg1];
2310 i.reloc[xchg1] = temp_reloc;
2311}
2312
2313
29b0f896
AM		 2314static void
2315swap_operands ()
2316{
2317 union i386_op temp_op;
2318 unsigned int temp_type;
f86103b7 2319 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2320 int xchg1 = 0;
2321 int xchg2 = 0;
252b5132 2322
050dfa73
MM		 2323 if (i.operands == 4)
2324 /* There will be two exchanges in a 4 operand instruction.
2325 First exchange is the done inside this block.(1st and 4rth operand)
2326 The next exchange is done outside this block.(2nd and 3rd operand) */
2327 {
2328 xchg1 = 0;
2329 xchg2 = 3;
2330 temp_type = i.types[xchg2];
2331 i.types[xchg2] = i.types[xchg1];
2332 i.types[xchg1] = temp_type;
2333 temp_op = i.op[xchg2];
2334 i.op[xchg2] = i.op[xchg1];
2335 i.op[xchg1] = temp_op;
2336 temp_reloc = i.reloc[xchg2];
2337 i.reloc[xchg2] = i.reloc[xchg1];
2338 i.reloc[xchg1] = temp_reloc;
2339 xchg1 = 1;
2340 xchg2 = 2;
2341 }
2342
29b0f896
AM		 2343 if (i.operands == 2)
2344 {
2345 xchg1 = 0;
2346 xchg2 = 1;
2347 }
2348 else if (i.operands == 3)
2349 {
2350 xchg1 = 0;
2351 xchg2 = 2;
2352 }
2353 temp_type = i.types[xchg2];
2354 i.types[xchg2] = i.types[xchg1];
2355 i.types[xchg1] = temp_type;
2356 temp_op = i.op[xchg2];
2357 i.op[xchg2] = i.op[xchg1];
2358 i.op[xchg1] = temp_op;
2359 temp_reloc = i.reloc[xchg2];
2360 i.reloc[xchg2] = i.reloc[xchg1];
2361 i.reloc[xchg1] = temp_reloc;
2362
2363 if (i.mem_operands == 2)
2364 {
2365 const seg_entry *temp_seg;
2366 temp_seg = i.seg[0];
2367 i.seg[0] = i.seg[1];
2368 i.seg[1] = temp_seg;
2369 }
2370}
252b5132 2371
29b0f896
AM		 2372/* Try to ensure constant immediates are represented in the smallest
2373 opcode possible. */
2374static void
2375optimize_imm ()
2376{
2377 char guess_suffix = 0;
2378 int op;
252b5132 2379
29b0f896
AM		 2380 if (i.suffix)
2381 guess_suffix = i.suffix;
2382 else if (i.reg_operands)
2383 {
2384 /* Figure out a suffix from the last register operand specified.
2385 We can't do this properly yet, ie. excluding InOutPortReg,
2386 but the following works for instructions with immediates.
2387 In any case, we can't set i.suffix yet. */
2388 for (op = i.operands; --op >= 0;)
2389 if (i.types[op] & Reg)
252b5132 2390 {
29b0f896
AM		 2391 if (i.types[op] & Reg8)
2392 guess_suffix = BYTE_MNEM_SUFFIX;
2393 else if (i.types[op] & Reg16)
2394 guess_suffix = WORD_MNEM_SUFFIX;
2395 else if (i.types[op] & Reg32)
2396 guess_suffix = LONG_MNEM_SUFFIX;
2397 else if (i.types[op] & Reg64)
2398 guess_suffix = QWORD_MNEM_SUFFIX;
2399 break;
252b5132 2400 }
29b0f896
AM		 2401 }
2402 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2403 guess_suffix = WORD_MNEM_SUFFIX;
2404
2405 for (op = i.operands; --op >= 0;)
2406 if (i.types[op] & Imm)
2407 {
2408 switch (i.op[op].imms->X_op)
252b5132 2409 {
29b0f896
AM		 2410 case O_constant:
2411 /* If a suffix is given, this operand may be shortened. */
2412 switch (guess_suffix)
252b5132 2413 {
29b0f896
AM		 2414 case LONG_MNEM_SUFFIX:
2415 i.types[op] |= Imm32 | Imm64;
2416 break;
2417 case WORD_MNEM_SUFFIX:
2418 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2419 break;
2420 case BYTE_MNEM_SUFFIX:
2421 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2422 break;
252b5132 2423 }
252b5132 2424
29b0f896
AM		 2425 /* If this operand is at most 16 bits, convert it
2426 to a signed 16 bit number before trying to see
2427 whether it will fit in an even smaller size.
2428 This allows a 16-bit operand such as $0xffe0 to
2429 be recognised as within Imm8S range. */
2430 if ((i.types[op] & Imm16)
2431 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2432 {
29b0f896
AM		 2433 i.op[op].imms->X_add_number =
2434 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2435 }
2436 if ((i.types[op] & Imm32)
2437 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2438 == 0))
2439 {
2440 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2441 ^ ((offsetT) 1 << 31))
2442 - ((offsetT) 1 << 31));
2443 }
2444 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2445
29b0f896
AM		 2446 /* We must avoid matching of Imm32 templates when 64bit
2447 only immediate is available. */
2448 if (guess_suffix == QWORD_MNEM_SUFFIX)
2449 i.types[op] &= ~Imm32;
2450 break;
252b5132 2451
29b0f896
AM		 2452 case O_absent:
2453 case O_register:
2454 abort ();
2455
2456 /* Symbols and expressions. */
2457 default:
9cd96992
JB		 2458 /* Convert symbolic operand to proper sizes for matching, but don't
2459 prevent matching a set of insns that only supports sizes other
2460 than those matching the insn suffix. */
2461 {
2462 unsigned int mask, allowed = 0;
2463 const template *t;
2464
2465 for (t = current_templates->start; t < current_templates->end; ++t)
2466 allowed |= t->operand_types[op];
2467 switch (guess_suffix)
2468 {
2469 case QWORD_MNEM_SUFFIX:
2470 mask = Imm64 | Imm32S;
2471 break;
2472 case LONG_MNEM_SUFFIX:
2473 mask = Imm32;
2474 break;
2475 case WORD_MNEM_SUFFIX:
2476 mask = Imm16;
2477 break;
2478 case BYTE_MNEM_SUFFIX:
2479 mask = Imm8;
2480 break;
2481 default:
2482 mask = 0;
2483 break;
2484 }
64e74474
AM		 2485 if (mask & allowed)
2486 i.types[op] &= mask;
9cd96992 2487 }
29b0f896 2488 break;
252b5132 2489 }
29b0f896
AM		 2490 }
2491}
47926f60 2492
29b0f896
AM		 2493/* Try to use the smallest displacement type too. */
2494static void
2495optimize_disp ()
2496{
2497 int op;
3e73aa7c 2498
29b0f896 2499 for (op = i.operands; --op >= 0;)
b300c311 2500 if (i.types[op] & Disp)
252b5132 2501 {
b300c311 2502 if (i.op[op].disps->X_op == O_constant)
252b5132 2503 {
b300c311 2504 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2505
b300c311
L		 2506 if ((i.types[op] & Disp16)
2507 && (disp & ~(offsetT) 0xffff) == 0)
2508 {
2509 /* If this operand is at most 16 bits, convert
2510 to a signed 16 bit number and don't use 64bit
2511 displacement. */
2512 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2513 i.types[op] &= ~Disp64;
2514 }
2515 if ((i.types[op] & Disp32)
2516 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2517 {
2518 /* If this operand is at most 32 bits, convert
2519 to a signed 32 bit number and don't use 64bit
2520 displacement. */
2521 disp &= (((offsetT) 2 << 31) - 1);
2522 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2523 i.types[op] &= ~Disp64;
2524 }
2525 if (!disp && (i.types[op] & BaseIndex))
2526 {
2527 i.types[op] &= ~Disp;
2528 i.op[op].disps = 0;
2529 i.disp_operands--;
2530 }
2531 else if (flag_code == CODE_64BIT)
2532 {
2533 if (fits_in_signed_long (disp))
28a9d8f5
L		 2534 {
2535 i.types[op] &= ~Disp64;
2536 i.types[op] |= Disp32S;
2537 }
b300c311
L		 2538 if (fits_in_unsigned_long (disp))
2539 i.types[op] |= Disp32;
2540 }
2541 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2542 && fits_in_signed_byte (disp))
2543 i.types[op] |= Disp8;
252b5132 2544 }
67a4f2b7
AO		 2545 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2546 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2547 {
2548 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2549 i.op[op].disps, 0, i.reloc[op]);
2550 i.types[op] &= ~Disp;
2551 }
2552 else
b300c311
L		 2553 /* We only support 64bit displacement on constants. */
2554 i.types[op] &= ~Disp64;
252b5132 2555 }
29b0f896
AM		 2556}
2557
2558static int
2559match_template ()
2560{
2561 /* Points to template once we've found it. */
2562 const template *t;
2563 unsigned int overlap0, overlap1, overlap2;
2564 unsigned int found_reverse_match;
2565 int suffix_check;
539e75ad
L		 2566 unsigned int operand_types [3];
2567 int addr_prefix_disp;
29b0f896
AM		 2568
2569#define MATCH(overlap, given, template) \
2570 ((overlap & ~JumpAbsolute) \
2571 && (((given) & (BaseIndex | JumpAbsolute)) \
2572 == ((overlap) & (BaseIndex | JumpAbsolute))))
2573
2574 /* If given types r0 and r1 are registers they must be of the same type
2575 unless the expected operand type register overlap is null.
2576 Note that Acc in a template matches every size of reg. */
2577#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2578 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2579 || ((g0) & Reg) == ((g1) & Reg) \
2580 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2581
2582 overlap0 = 0;
2583 overlap1 = 0;
2584 overlap2 = 0;
2585 found_reverse_match = 0;
539e75ad
L		 2586 operand_types [0] = 0;
2587 operand_types [1] = 0;
2588 operand_types [2] = 0;
2589 addr_prefix_disp = -1;
29b0f896
AM		 2590 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2591 ? No_bSuf
2592 : (i.suffix == WORD_MNEM_SUFFIX
2593 ? No_wSuf
2594 : (i.suffix == SHORT_MNEM_SUFFIX
2595 ? No_sSuf
2596 : (i.suffix == LONG_MNEM_SUFFIX
2597 ? No_lSuf
2598 : (i.suffix == QWORD_MNEM_SUFFIX
2599 ? No_qSuf
2600 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2601 ? No_xSuf : 0))))));
2602
45aa61fe 2603 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2604 {
539e75ad
L		 2605 addr_prefix_disp = -1;
2606
29b0f896
AM		 2607 /* Must have right number of operands. */
2608 if (i.operands != t->operands)
2609 continue;
2610
2611 /* Check the suffix, except for some instructions in intel mode. */
2612 if ((t->opcode_modifier & suffix_check)
2613 && !(intel_syntax
9306ca4a 2614 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2615 continue;
2616
539e75ad
L		 2617 operand_types [0] = t->operand_types [0];
2618 operand_types [1] = t->operand_types [1];
2619 operand_types [2] = t->operand_types [2];
2620
45aa61fe
AM		 2621 /* In general, don't allow 64-bit operands in 32-bit mode. */
2622 if (i.suffix == QWORD_MNEM_SUFFIX
2623 && flag_code != CODE_64BIT
2624 && (intel_syntax
2625 ? (!(t->opcode_modifier & IgnoreSize)
2626 && !intel_float_operand (t->name))
2627 : intel_float_operand (t->name) != 2)
539e75ad
L		 2628 && (!(operand_types[0] & (RegMMX | RegXMM))
2629 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2630 && (t->base_opcode != 0x0fc7
2631 || t->extension_opcode != 1 /* cmpxchg8b */))
2632 continue;
2633
29b0f896
AM		 2634 /* Do not verify operands when there are none. */
2635 else if (!t->operands)
2636 {
2637 if (t->cpu_flags & ~cpu_arch_flags)
2638 continue;
2639 /* We've found a match; break out of loop. */
2640 break;
2641 }
252b5132 2642
539e75ad
L		 2643 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2644 into Disp32/Disp16/Disp32 operand. */
2645 if (i.prefix[ADDR_PREFIX] != 0)
2646 {
2647 unsigned int j, DispOn = 0, DispOff = 0;
2648
2649 switch (flag_code)
2650 {
2651 case CODE_16BIT:
2652 DispOn = Disp32;
2653 DispOff = Disp16;
2654 break;
2655 case CODE_32BIT:
2656 DispOn = Disp16;
2657 DispOff = Disp32;
2658 break;
2659 case CODE_64BIT:
2660 DispOn = Disp32;
2661 DispOff = Disp64;
2662 break;
2663 }
2664
2665 for (j = 0; j < 3; j++)
2666 {
2667 /* There should be only one Disp operand. */
2668 if ((operand_types[j] & DispOff))
2669 {
2670 addr_prefix_disp = j;
2671 operand_types[j] |= DispOn;
2672 operand_types[j] &= ~DispOff;
2673 break;
2674 }
2675 }
2676 }
2677
2678 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2679 switch (t->operands)
2680 {
2681 case 1:
539e75ad 2682 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2683 continue;
2684 break;
2685 case 2:
2686 case 3:
539e75ad
L		 2687 overlap1 = i.types[1] & operand_types[1];
2688 if (!MATCH (overlap0, i.types[0], operand_types[0])
2689 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2690 /* monitor in SSE3 is a very special case. The first
708587a4 2691 register and the second register may have different
cb712a9e
L		 2692 sizes. */
2693 || !((t->base_opcode == 0x0f01
2694 && t->extension_opcode == 0xc8)
2695 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2696 operand_types[0],
cb712a9e 2697 overlap1, i.types[1],
539e75ad 2698 operand_types[1])))
29b0f896
AM		 2699 {
2700 /* Check if other direction is valid ... */
2701 if ((t->opcode_modifier & (D | FloatD)) == 0)
2702 continue;
2703
2704 /* Try reversing direction of operands. */
539e75ad
L		 2705 overlap0 = i.types[0] & operand_types[1];
2706 overlap1 = i.types[1] & operand_types[0];
2707 if (!MATCH (overlap0, i.types[0], operand_types[1])
2708 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2709 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2710 operand_types[1],
29b0f896 2711 overlap1, i.types[1],
539e75ad 2712 operand_types[0]))
29b0f896
AM		 2713 {
2714 /* Does not match either direction. */
2715 continue;
2716 }
2717 /* found_reverse_match holds which of D or FloatDR
2718 we've found. */
2719 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2720 }
2721 /* Found a forward 2 operand match here. */
2722 else if (t->operands == 3)
2723 {
2724 /* Here we make use of the fact that there are no
2725 reverse match 3 operand instructions, and all 3
2726 operand instructions only need to be checked for
2727 register consistency between operands 2 and 3. */
539e75ad
L		 2728 overlap2 = i.types[2] & operand_types[2];
2729 if (!MATCH (overlap2, i.types[2], operand_types[2])
29b0f896 2730 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
539e75ad 2731 operand_types[1],
29b0f896 2732 overlap2, i.types[2],
539e75ad 2733 operand_types[2]))
29b0f896
AM		 2734
2735 continue;
2736 }
2737 /* Found either forward/reverse 2 or 3 operand match here:
2738 slip through to break. */
2739 }
2740 if (t->cpu_flags & ~cpu_arch_flags)
2741 {
2742 found_reverse_match = 0;
2743 continue;
2744 }
2745 /* We've found a match; break out of loop. */
2746 break;
2747 }
2748
2749 if (t == current_templates->end)
2750 {
2751 /* We found no match. */
2752 as_bad (_("suffix or operands invalid for `%s'"),
2753 current_templates->start->name);
2754 return 0;
2755 }
252b5132 2756
29b0f896
AM		 2757 if (!quiet_warnings)
2758 {
2759 if (!intel_syntax
2760 && ((i.types[0] & JumpAbsolute)
539e75ad 2761 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2762 {
2763 as_warn (_("indirect %s without `*'"), t->name);
2764 }
2765
2766 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2767 == (IsPrefix | IgnoreSize))
2768 {
2769 /* Warn them that a data or address size prefix doesn't
2770 affect assembly of the next line of code. */
2771 as_warn (_("stand-alone `%s' prefix"), t->name);
2772 }
2773 }
2774
2775 /* Copy the template we found. */
2776 i.tm = *t;
539e75ad
L		 2777
2778 if (addr_prefix_disp != -1)
2779 i.tm.operand_types[addr_prefix_disp]
2780 = operand_types[addr_prefix_disp];
2781
29b0f896
AM		 2782 if (found_reverse_match)
2783 {
2784 /* If we found a reverse match we must alter the opcode
2785 direction bit. found_reverse_match holds bits to change
2786 (different for int & float insns). */
2787
2788 i.tm.base_opcode ^= found_reverse_match;
2789
539e75ad
L		 2790 i.tm.operand_types[0] = operand_types[1];
2791 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2792 }
2793
2794 return 1;
2795}
2796
2797static int
2798check_string ()
2799{
2800 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2801 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2802 {
2803 if (i.seg[0] != NULL && i.seg[0] != &es)
2804 {
2805 as_bad (_("`%s' operand %d must use `%%es' segment"),
2806 i.tm.name,
2807 mem_op + 1);
2808 return 0;
2809 }
2810 /* There's only ever one segment override allowed per instruction.
2811 This instruction possibly has a legal segment override on the
2812 second operand, so copy the segment to where non-string
2813 instructions store it, allowing common code. */
2814 i.seg[0] = i.seg[1];
2815 }
2816 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2817 {
2818 if (i.seg[1] != NULL && i.seg[1] != &es)
2819 {
2820 as_bad (_("`%s' operand %d must use `%%es' segment"),
2821 i.tm.name,
2822 mem_op + 2);
2823 return 0;
2824 }
2825 }
2826 return 1;
2827}
2828
2829static int
543613e9 2830process_suffix (void)
29b0f896
AM		 2831{
2832 /* If matched instruction specifies an explicit instruction mnemonic
2833 suffix, use it. */
2834 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2835 {
2836 if (i.tm.opcode_modifier & Size16)
2837 i.suffix = WORD_MNEM_SUFFIX;
2838 else if (i.tm.opcode_modifier & Size64)
2839 i.suffix = QWORD_MNEM_SUFFIX;
2840 else
2841 i.suffix = LONG_MNEM_SUFFIX;
2842 }
2843 else if (i.reg_operands)
2844 {
2845 /* If there's no instruction mnemonic suffix we try to invent one
2846 based on register operands. */
2847 if (!i.suffix)
2848 {
2849 /* We take i.suffix from the last register operand specified,
2850 Destination register type is more significant than source
2851 register type. */
2852 int op;
543613e9 2853
29b0f896
AM		 2854 for (op = i.operands; --op >= 0;)
2855 if ((i.types[op] & Reg)
2856 && !(i.tm.operand_types[op] & InOutPortReg))
2857 {
2858 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2859 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2860 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2861 LONG_MNEM_SUFFIX);
2862 break;
2863 }
2864 }
2865 else if (i.suffix == BYTE_MNEM_SUFFIX)
2866 {
2867 if (!check_byte_reg ())
2868 return 0;
2869 }
2870 else if (i.suffix == LONG_MNEM_SUFFIX)
2871 {
2872 if (!check_long_reg ())
2873 return 0;
2874 }
2875 else if (i.suffix == QWORD_MNEM_SUFFIX)
2876 {
2877 if (!check_qword_reg ())
2878 return 0;
2879 }
2880 else if (i.suffix == WORD_MNEM_SUFFIX)
2881 {
2882 if (!check_word_reg ())
2883 return 0;
2884 }
2885 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2886 /* Do nothing if the instruction is going to ignore the prefix. */
2887 ;
2888 else
2889 abort ();
2890 }
9306ca4a
JB		 2891 else if ((i.tm.opcode_modifier & DefaultSize)
2892 && !i.suffix
2893 /* exclude fldenv/frstor/fsave/fstenv */
2894 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2895 {
2896 i.suffix = stackop_size;
2897 }
9306ca4a
JB		 2898 else if (intel_syntax
2899 && !i.suffix
2900 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2901 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2902 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2903 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2904 {
2905 switch (flag_code)
2906 {
2907 case CODE_64BIT:
2908 if (!(i.tm.opcode_modifier & No_qSuf))
2909 {
2910 i.suffix = QWORD_MNEM_SUFFIX;
2911 break;
2912 }
2913 case CODE_32BIT:
2914 if (!(i.tm.opcode_modifier & No_lSuf))
2915 i.suffix = LONG_MNEM_SUFFIX;
2916 break;
2917 case CODE_16BIT:
2918 if (!(i.tm.opcode_modifier & No_wSuf))
2919 i.suffix = WORD_MNEM_SUFFIX;
2920 break;
2921 }
2922 }
252b5132 2923
9306ca4a 2924 if (!i.suffix)
29b0f896 2925 {
9306ca4a
JB		 2926 if (!intel_syntax)
2927 {
2928 if (i.tm.opcode_modifier & W)
2929 {
2930 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2931 return 0;
2932 }
2933 }
2934 else
2935 {
64e74474
AM		 2936 unsigned int suffixes = (~i.tm.opcode_modifier
2937 & (No_bSuf
2938 | No_wSuf
2939 | No_lSuf
2940 | No_sSuf
2941 | No_xSuf
2942 | No_qSuf));
9306ca4a
JB		 2943
2944 if ((i.tm.opcode_modifier & W)
2945 || ((suffixes & (suffixes - 1))
2946 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2947 {
2948 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2949 return 0;
2950 }
2951 }
29b0f896 2952 }
252b5132 2953
9306ca4a
JB		 2954 /* Change the opcode based on the operand size given by i.suffix;
2955 We don't need to change things for byte insns. */
2956
29b0f896
AM		 2957 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2958 {
2959 /* It's not a byte, select word/dword operation. */
2960 if (i.tm.opcode_modifier & W)
2961 {
2962 if (i.tm.opcode_modifier & ShortForm)
2963 i.tm.base_opcode |= 8;
2964 else
2965 i.tm.base_opcode |= 1;
2966 }
0f3f3d8b 2967
29b0f896
AM		 2968 /* Now select between word & dword operations via the operand
2969 size prefix, except for instructions that will ignore this
2970 prefix anyway. */
cb712a9e
L		 2971 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2972 {
2973 /* monitor in SSE3 is a very special case. The default size
2974 of AX is the size of mode. The address size override
2975 prefix will change the size of AX. */
2976 if (i.op->regs[0].reg_type &
2977 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2978 if (!add_prefix (ADDR_PREFIX_OPCODE))
2979 return 0;
2980 }
2981 else if (i.suffix != QWORD_MNEM_SUFFIX
2982 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2983 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2984 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2985 || (flag_code == CODE_64BIT
2986 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2987 {
2988 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2989
29b0f896
AM		 2990 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2991 prefix = ADDR_PREFIX_OPCODE;
252b5132 2992
29b0f896
AM		 2993 if (!add_prefix (prefix))
2994 return 0;
24eab124 2995 }
252b5132 2996
29b0f896
AM		 2997 /* Set mode64 for an operand. */
2998 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2999 && flag_code == CODE_64BIT
29b0f896 3000 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3001 {
3002 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3003 need rex64. */
3004 if (i.operands != 2
3005 || i.types [0] != (Acc | Reg64)
3006 || i.types [1] != (Acc | Reg64)
3007 || strcmp (i.tm.name, "xchg") != 0)
3008 i.rex |= REX_MODE64;
3009 }
3e73aa7c 3010
29b0f896
AM		 3011 /* Size floating point instruction. */
3012 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3013 if (i.tm.opcode_modifier & FloatMF)
3014 i.tm.base_opcode ^= 4;
29b0f896 3015 }
7ecd2f8b 3016
29b0f896
AM		 3017 return 1;
3018}
3e73aa7c 3019
29b0f896 3020static int
543613e9 3021check_byte_reg (void)
29b0f896
AM		 3022{
3023 int op;
543613e9 3024
29b0f896
AM		 3025 for (op = i.operands; --op >= 0;)
3026 {
3027 /* If this is an eight bit register, it's OK. If it's the 16 or
3028 32 bit version of an eight bit register, we will just use the
3029 low portion, and that's OK too. */
3030 if (i.types[op] & Reg8)
3031 continue;
3032
3033 /* movzx and movsx should not generate this warning. */
3034 if (intel_syntax
3035 && (i.tm.base_opcode == 0xfb7
3036 || i.tm.base_opcode == 0xfb6
3037 || i.tm.base_opcode == 0x63
3038 || i.tm.base_opcode == 0xfbe
3039 || i.tm.base_opcode == 0xfbf))
3040 continue;
3041
65ec77d2 3042 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3043 {
3044 /* Prohibit these changes in the 64bit mode, since the
3045 lowering is more complicated. */
3046 if (flag_code == CODE_64BIT
3047 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3048 {
0f3f3d8b 3049 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3050 i.op[op].regs->reg_name,
3051 i.suffix);
3052 return 0;
3053 }
3054#if REGISTER_WARNINGS
3055 if (!quiet_warnings
3056 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3057 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3058 (i.op[op].regs + (i.types[op] & Reg16
3059 ? REGNAM_AL - REGNAM_AX
3060 : REGNAM_AL - REGNAM_EAX))->reg_name,
3061 i.op[op].regs->reg_name,
3062 i.suffix);
3063#endif
3064 continue;
3065 }
3066 /* Any other register is bad. */
3067 if (i.types[op] & (Reg | RegMMX | RegXMM
3068 | SReg2 | SReg3
3069 | Control | Debug | Test
3070 | FloatReg | FloatAcc))
3071 {
3072 as_bad (_("`%%%s' not allowed with `%s%c'"),
3073 i.op[op].regs->reg_name,
3074 i.tm.name,
3075 i.suffix);
3076 return 0;
3077 }
3078 }
3079 return 1;
3080}
3081
3082static int
3083check_long_reg ()
3084{
3085 int op;
3086
3087 for (op = i.operands; --op >= 0;)
3088 /* Reject eight bit registers, except where the template requires
3089 them. (eg. movzb) */
3090 if ((i.types[op] & Reg8) != 0
3091 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3092 {
3093 as_bad (_("`%%%s' not allowed with `%s%c'"),
3094 i.op[op].regs->reg_name,
3095 i.tm.name,
3096 i.suffix);
3097 return 0;
3098 }
3099 /* Warn if the e prefix on a general reg is missing. */
3100 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3101 && (i.types[op] & Reg16) != 0
3102 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3103 {
3104 /* Prohibit these changes in the 64bit mode, since the
3105 lowering is more complicated. */
3106 if (flag_code == CODE_64BIT)
252b5132 3107 {
0f3f3d8b 3108 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3109 i.op[op].regs->reg_name,
3110 i.suffix);
3111 return 0;
252b5132 3112 }
29b0f896
AM		 3113#if REGISTER_WARNINGS
3114 else
3115 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3116 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3117 i.op[op].regs->reg_name,
3118 i.suffix);
3119#endif
252b5132 3120 }
29b0f896
AM		 3121 /* Warn if the r prefix on a general reg is missing. */
3122 else if ((i.types[op] & Reg64) != 0
3123 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3124 {
0f3f3d8b 3125 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3126 i.op[op].regs->reg_name,
3127 i.suffix);
3128 return 0;
3129 }
3130 return 1;
3131}
252b5132 3132
29b0f896
AM		 3133static int
3134check_qword_reg ()
3135{
3136 int op;
252b5132 3137
29b0f896
AM		 3138 for (op = i.operands; --op >= 0; )
3139 /* Reject eight bit registers, except where the template requires
3140 them. (eg. movzb) */
3141 if ((i.types[op] & Reg8) != 0
3142 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3143 {
3144 as_bad (_("`%%%s' not allowed with `%s%c'"),
3145 i.op[op].regs->reg_name,
3146 i.tm.name,
3147 i.suffix);
3148 return 0;
3149 }
3150 /* Warn if the e prefix on a general reg is missing. */
3151 else if (((i.types[op] & Reg16) != 0
3152 || (i.types[op] & Reg32) != 0)
3153 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3154 {
3155 /* Prohibit these changes in the 64bit mode, since the
3156 lowering is more complicated. */
0f3f3d8b 3157 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3158 i.op[op].regs->reg_name,
3159 i.suffix);
3160 return 0;
252b5132 3161 }
29b0f896
AM		 3162 return 1;
3163}
252b5132 3164
29b0f896
AM		 3165static int
3166check_word_reg ()
3167{
3168 int op;
3169 for (op = i.operands; --op >= 0;)
3170 /* Reject eight bit registers, except where the template requires
3171 them. (eg. movzb) */
3172 if ((i.types[op] & Reg8) != 0
3173 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3174 {
3175 as_bad (_("`%%%s' not allowed with `%s%c'"),
3176 i.op[op].regs->reg_name,
3177 i.tm.name,
3178 i.suffix);
3179 return 0;
3180 }
3181 /* Warn if the e prefix on a general reg is present. */
3182 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3183 && (i.types[op] & Reg32) != 0
3184 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3185 {
29b0f896
AM		 3186 /* Prohibit these changes in the 64bit mode, since the
3187 lowering is more complicated. */
3188 if (flag_code == CODE_64BIT)
252b5132 3189 {
0f3f3d8b 3190 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3191 i.op[op].regs->reg_name,
3192 i.suffix);
3193 return 0;
252b5132 3194 }
29b0f896
AM		 3195 else
3196#if REGISTER_WARNINGS
3197 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3198 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3199 i.op[op].regs->reg_name,
3200 i.suffix);
3201#endif
3202 }
3203 return 1;
3204}
252b5132 3205
29b0f896
AM		 3206static int
3207finalize_imm ()
3208{
3209 unsigned int overlap0, overlap1, overlap2;
3210
3211 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3212 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3213 && overlap0 != Imm8 && overlap0 != Imm8S
3214 && overlap0 != Imm16 && overlap0 != Imm32S
3215 && overlap0 != Imm32 && overlap0 != Imm64)
3216 {
3217 if (i.suffix)
3218 {
3219 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3220 ? Imm8 | Imm8S
3221 : (i.suffix == WORD_MNEM_SUFFIX
3222 ? Imm16
3223 : (i.suffix == QWORD_MNEM_SUFFIX
3224 ? Imm64 | Imm32S
3225 : Imm32)));
3226 }
3227 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3228 || overlap0 == (Imm16 | Imm32)
3229 || overlap0 == (Imm16 | Imm32S))
3230 {
3231 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3232 ? Imm16 : Imm32S);
3233 }
3234 if (overlap0 != Imm8 && overlap0 != Imm8S
3235 && overlap0 != Imm16 && overlap0 != Imm32S
3236 && overlap0 != Imm32 && overlap0 != Imm64)
3237 {
3238 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3239 return 0;
3240 }
3241 }
3242 i.types[0] = overlap0;
3243
3244 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3245 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3246 && overlap1 != Imm8 && overlap1 != Imm8S
3247 && overlap1 != Imm16 && overlap1 != Imm32S
3248 && overlap1 != Imm32 && overlap1 != Imm64)
3249 {
3250 if (i.suffix)
3251 {
3252 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3253 ? Imm8 | Imm8S
3254 : (i.suffix == WORD_MNEM_SUFFIX
3255 ? Imm16
3256 : (i.suffix == QWORD_MNEM_SUFFIX
3257 ? Imm64 | Imm32S
3258 : Imm32)));
3259 }
3260 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3261 || overlap1 == (Imm16 | Imm32)
3262 || overlap1 == (Imm16 | Imm32S))
3263 {
3264 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3265 ? Imm16 : Imm32S);
3266 }
3267 if (overlap1 != Imm8 && overlap1 != Imm8S
3268 && overlap1 != Imm16 && overlap1 != Imm32S
3269 && overlap1 != Imm32 && overlap1 != Imm64)
3270 {
3271 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3272 return 0;
3273 }
3274 }
3275 i.types[1] = overlap1;
3276
3277 overlap2 = i.types[2] & i.tm.operand_types[2];
3278 assert ((overlap2 & Imm) == 0);
3279 i.types[2] = overlap2;
3280
3281 return 1;
3282}
3283
3284static int
3285process_operands ()
3286{
3287 /* Default segment register this instruction will use for memory
3288 accesses. 0 means unknown. This is only for optimizing out
3289 unnecessary segment overrides. */
3290 const seg_entry *default_seg = 0;
3291
3292 /* The imul $imm, %reg instruction is converted into
3293 imul $imm, %reg, %reg, and the clr %reg instruction
3294 is converted into xor %reg, %reg. */
3295 if (i.tm.opcode_modifier & regKludge)
3296 {
3297 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3298 /* Pretend we saw the extra register operand. */
3299 assert (i.op[first_reg_op + 1].regs == 0);
3300 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3301 i.types[first_reg_op + 1] = i.types[first_reg_op];
3302 i.reg_operands = 2;
3303 }
3304
3305 if (i.tm.opcode_modifier & ShortForm)
3306 {
3307 /* The register or float register operand is in operand 0 or 1. */
3308 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3309 /* Register goes in low 3 bits of opcode. */
3310 i.tm.base_opcode |= i.op[op].regs->reg_num;
3311 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3312 i.rex |= REX_EXTZ;
3313 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3314 {
3315 /* Warn about some common errors, but press on regardless.
3316 The first case can be generated by gcc (<= 2.8.1). */
3317 if (i.operands == 2)
3318 {
3319 /* Reversed arguments on faddp, fsubp, etc. */
3320 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3321 i.op[1].regs->reg_name,
3322 i.op[0].regs->reg_name);
3323 }
3324 else
3325 {
3326 /* Extraneous `l' suffix on fp insn. */
3327 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3328 i.op[0].regs->reg_name);
3329 }
3330 }
3331 }
3332 else if (i.tm.opcode_modifier & Modrm)
3333 {
3334 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3335 must be put into the modrm byte). Now, we make the modrm and
3336 index base bytes based on all the info we've collected. */
29b0f896
AM		 3337
3338 default_seg = build_modrm_byte ();
3339 }
3340 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3341 {
3342 if (i.tm.base_opcode == POP_SEG_SHORT
3343 && i.op[0].regs->reg_num == 1)
3344 {
3345 as_bad (_("you can't `pop %%cs'"));
3346 return 0;
3347 }
3348 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3349 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3350 i.rex |= REX_EXTZ;
3351 }
3352 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3353 {
3354 default_seg = &ds;
3355 }
3356 else if ((i.tm.opcode_modifier & IsString) != 0)
3357 {
3358 /* For the string instructions that allow a segment override
3359 on one of their operands, the default segment is ds. */
3360 default_seg = &ds;
3361 }
3362
30123838
JB		 3363 if ((i.tm.base_opcode == 0x8d /* lea */
3364 || (i.tm.cpu_flags & CpuSVME))
3365 && i.seg[0] && !quiet_warnings)
3366 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3367
3368 /* If a segment was explicitly specified, and the specified segment
3369 is not the default, use an opcode prefix to select it. If we
3370 never figured out what the default segment is, then default_seg
3371 will be zero at this point, and the specified segment prefix will
3372 always be used. */
29b0f896
AM		 3373 if ((i.seg[0]) && (i.seg[0] != default_seg))
3374 {
3375 if (!add_prefix (i.seg[0]->seg_prefix))
3376 return 0;
3377 }
3378 return 1;
3379}
3380
3381static const seg_entry *
3382build_modrm_byte ()
3383{
3384 const seg_entry *default_seg = 0;
3385
3386 /* i.reg_operands MUST be the number of real register operands;
3387 implicit registers do not count. */
3388 if (i.reg_operands == 2)
3389 {
3390 unsigned int source, dest;
3391 source = ((i.types[0]
3392 & (Reg | RegMMX | RegXMM
3393 | SReg2 | SReg3
3394 | Control | Debug | Test))
3395 ? 0 : 1);
050dfa73
MM		 3396
3397 /* In 4 operands instructions with 2 immediate operands, the first two are immediate
3398 bytes and hence source operand will be in the next byte after the immediates */
3399 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
29b0f896
AM		 3400 dest = source + 1;
3401
3402 i.rm.mode = 3;
3403 /* One of the register operands will be encoded in the i.tm.reg
3404 field, the other in the combined i.tm.mode and i.tm.regmem
3405 fields. If no form of this instruction supports a memory
3406 destination operand, then we assume the source operand may
3407 sometimes be a memory operand and so we need to store the
3408 destination in the i.rm.reg field. */
3409 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3410 {
3411 i.rm.reg = i.op[dest].regs->reg_num;
3412 i.rm.regmem = i.op[source].regs->reg_num;
3413 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3414 i.rex |= REX_EXTX;
3415 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3416 i.rex |= REX_EXTZ;
3417 }
3418 else
3419 {
3420 i.rm.reg = i.op[source].regs->reg_num;
3421 i.rm.regmem = i.op[dest].regs->reg_num;
3422 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3423 i.rex |= REX_EXTZ;
3424 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3425 i.rex |= REX_EXTX;
3426 }
c4a530c5
JB		 3427 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3428 {
3429 if (!((i.types[0] | i.types[1]) & Control))
3430 abort ();
3431 i.rex &= ~(REX_EXTX | REX_EXTZ);
3432 add_prefix (LOCK_PREFIX_OPCODE);
3433 }
29b0f896
AM		 3434 }
3435 else
3436 { /* If it's not 2 reg operands... */
3437 if (i.mem_operands)
3438 {
3439 unsigned int fake_zero_displacement = 0;
3440 unsigned int op = ((i.types[0] & AnyMem)
3441 ? 0
3442 : (i.types[1] & AnyMem) ? 1 : 2);
3443
3444 default_seg = &ds;
3445
3446 if (i.base_reg == 0)
3447 {
3448 i.rm.mode = 0;
3449 if (!i.disp_operands)
3450 fake_zero_displacement = 1;
3451 if (i.index_reg == 0)
3452 {
3453 /* Operand is just <disp> */
20f0a1fc 3454 if (flag_code == CODE_64BIT)
29b0f896
AM		 3455 {
3456 /* 64bit mode overwrites the 32bit absolute
3457 addressing by RIP relative addressing and
3458 absolute addressing is encoded by one of the
3459 redundant SIB forms. */
3460 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3461 i.sib.base = NO_BASE_REGISTER;
3462 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3463 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3464 }
3465 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3466 {
3467 i.rm.regmem = NO_BASE_REGISTER_16;
3468 i.types[op] = Disp16;
3469 }
3470 else
3471 {
3472 i.rm.regmem = NO_BASE_REGISTER;
3473 i.types[op] = Disp32;
29b0f896
AM		 3474 }
3475 }
3476 else /* !i.base_reg && i.index_reg */
3477 {
3478 i.sib.index = i.index_reg->reg_num;
3479 i.sib.base = NO_BASE_REGISTER;
3480 i.sib.scale = i.log2_scale_factor;
3481 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3482 i.types[op] &= ~Disp;
3483 if (flag_code != CODE_64BIT)
3484 i.types[op] |= Disp32; /* Must be 32 bit */
3485 else
3486 i.types[op] |= Disp32S;
3487 if ((i.index_reg->reg_flags & RegRex) != 0)
3488 i.rex |= REX_EXTY;
3489 }
3490 }
3491 /* RIP addressing for 64bit mode. */
3492 else if (i.base_reg->reg_type == BaseIndex)
3493 {
3494 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3495 i.types[op] &= ~ Disp;
29b0f896
AM		 3496 i.types[op] |= Disp32S;
3497 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3498 if (! i.disp_operands)
3499 fake_zero_displacement = 1;
29b0f896
AM		 3500 }
3501 else if (i.base_reg->reg_type & Reg16)
3502 {
3503 switch (i.base_reg->reg_num)
3504 {
3505 case 3: /* (%bx) */
3506 if (i.index_reg == 0)
3507 i.rm.regmem = 7;
3508 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3509 i.rm.regmem = i.index_reg->reg_num - 6;
3510 break;
3511 case 5: /* (%bp) */
3512 default_seg = &ss;
3513 if (i.index_reg == 0)
3514 {
3515 i.rm.regmem = 6;
3516 if ((i.types[op] & Disp) == 0)
3517 {
3518 /* fake (%bp) into 0(%bp) */
3519 i.types[op] |= Disp8;
252b5132 3520 fake_zero_displacement = 1;
29b0f896
AM		 3521 }
3522 }
3523 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3524 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3525 break;
3526 default: /* (%si) -> 4 or (%di) -> 5 */
3527 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3528 }
3529 i.rm.mode = mode_from_disp_size (i.types[op]);
3530 }
3531 else /* i.base_reg and 32/64 bit mode */
3532 {
3533 if (flag_code == CODE_64BIT
3534 && (i.types[op] & Disp))
20f0a1fc
NC		 3535 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3536
29b0f896
AM		 3537 i.rm.regmem = i.base_reg->reg_num;
3538 if ((i.base_reg->reg_flags & RegRex) != 0)
3539 i.rex |= REX_EXTZ;
3540 i.sib.base = i.base_reg->reg_num;
3541 /* x86-64 ignores REX prefix bit here to avoid decoder
3542 complications. */
3543 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3544 {
3545 default_seg = &ss;
3546 if (i.disp_operands == 0)
3547 {
3548 fake_zero_displacement = 1;
3549 i.types[op] |= Disp8;
3550 }
3551 }
3552 else if (i.base_reg->reg_num == ESP_REG_NUM)
3553 {
3554 default_seg = &ss;
3555 }
3556 i.sib.scale = i.log2_scale_factor;
3557 if (i.index_reg == 0)
3558 {
3559 /* <disp>(%esp) becomes two byte modrm with no index
3560 register. We've already stored the code for esp
3561 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3562 Any base register besides %esp will not use the
3563 extra modrm byte. */
3564 i.sib.index = NO_INDEX_REGISTER;
3565#if !SCALE1_WHEN_NO_INDEX
3566 /* Another case where we force the second modrm byte. */
3567 if (i.log2_scale_factor)
3568 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3569#endif
29b0f896
AM		 3570 }
3571 else
3572 {
3573 i.sib.index = i.index_reg->reg_num;
3574 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3575 if ((i.index_reg->reg_flags & RegRex) != 0)
3576 i.rex |= REX_EXTY;
3577 }
67a4f2b7
AO		 3578
3579 if (i.disp_operands
3580 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3581 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3582 i.rm.mode = 0;
3583 else
3584 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3585 }
252b5132 3586
29b0f896
AM		 3587 if (fake_zero_displacement)
3588 {
3589 /* Fakes a zero displacement assuming that i.types[op]
3590 holds the correct displacement size. */
3591 expressionS *exp;
3592
3593 assert (i.op[op].disps == 0);
3594 exp = &disp_expressions[i.disp_operands++];
3595 i.op[op].disps = exp;
3596 exp->X_op = O_constant;
3597 exp->X_add_number = 0;
3598 exp->X_add_symbol = (symbolS *) 0;
3599 exp->X_op_symbol = (symbolS *) 0;
3600 }
3601 }
252b5132 3602
29b0f896
AM		 3603 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3604 (if any) based on i.tm.extension_opcode. Again, we must be
3605 careful to make sure that segment/control/debug/test/MMX
3606 registers are coded into the i.rm.reg field. */
3607 if (i.reg_operands)
3608 {
3609 unsigned int op =
3610 ((i.types[0]
3611 & (Reg | RegMMX | RegXMM
3612 | SReg2 | SReg3
3613 | Control | Debug | Test))
3614 ? 0
3615 : ((i.types[1]
3616 & (Reg | RegMMX | RegXMM
3617 | SReg2 | SReg3
3618 | Control | Debug | Test))
3619 ? 1
3620 : 2));
3621 /* If there is an extension opcode to put here, the register
3622 number must be put into the regmem field. */
3623 if (i.tm.extension_opcode != None)
3624 {
3625 i.rm.regmem = i.op[op].regs->reg_num;
3626 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3627 i.rex |= REX_EXTZ;
3628 }
3629 else
3630 {
3631 i.rm.reg = i.op[op].regs->reg_num;
3632 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3633 i.rex |= REX_EXTX;
3634 }
252b5132 3635
29b0f896
AM		 3636 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3637 must set it to 3 to indicate this is a register operand
3638 in the regmem field. */
3639 if (!i.mem_operands)
3640 i.rm.mode = 3;
3641 }
252b5132 3642
29b0f896
AM		 3643 /* Fill in i.rm.reg field with extension opcode (if any). */
3644 if (i.tm.extension_opcode != None)
3645 i.rm.reg = i.tm.extension_opcode;
3646 }
3647 return default_seg;
3648}
252b5132 3649
29b0f896
AM		 3650static void
3651output_branch ()
3652{
3653 char *p;
3654 int code16;
3655 int prefix;
3656 relax_substateT subtype;
3657 symbolS *sym;
3658 offsetT off;
3659
3660 code16 = 0;
3661 if (flag_code == CODE_16BIT)
3662 code16 = CODE16;
3663
3664 prefix = 0;
3665 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3666 {
29b0f896
AM		 3667 prefix = 1;
3668 i.prefixes -= 1;
3669 code16 ^= CODE16;
252b5132 3670 }
29b0f896
AM		 3671 /* Pentium4 branch hints. */
3672 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3673 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3674 {
29b0f896
AM		 3675 prefix++;
3676 i.prefixes--;
3677 }
3678 if (i.prefix[REX_PREFIX] != 0)
3679 {
3680 prefix++;
3681 i.prefixes--;
2f66722d
AM		 3682 }
3683
29b0f896
AM		 3684 if (i.prefixes != 0 && !intel_syntax)
3685 as_warn (_("skipping prefixes on this instruction"));
3686
3687 /* It's always a symbol; End frag & setup for relax.
3688 Make sure there is enough room in this frag for the largest
3689 instruction we may generate in md_convert_frag. This is 2
3690 bytes for the opcode and room for the prefix and largest
3691 displacement. */
3692 frag_grow (prefix + 2 + 4);
3693 /* Prefix and 1 opcode byte go in fr_fix. */
3694 p = frag_more (prefix + 1);
3695 if (i.prefix[DATA_PREFIX] != 0)
3696 *p++ = DATA_PREFIX_OPCODE;
3697 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3698 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3699 *p++ = i.prefix[SEG_PREFIX];
3700 if (i.prefix[REX_PREFIX] != 0)
3701 *p++ = i.prefix[REX_PREFIX];
3702 *p = i.tm.base_opcode;
3703
3704 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3705 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3706 else if ((cpu_arch_flags & Cpu386) != 0)
3707 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3708 else
3709 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3710 subtype |= code16;
3e73aa7c 3711
29b0f896
AM		 3712 sym = i.op[0].disps->X_add_symbol;
3713 off = i.op[0].disps->X_add_number;
3e73aa7c 3714
29b0f896
AM		 3715 if (i.op[0].disps->X_op != O_constant
3716 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3717 {
29b0f896
AM		 3718 /* Handle complex expressions. */
3719 sym = make_expr_symbol (i.op[0].disps);
3720 off = 0;
3721 }
3e73aa7c 3722
29b0f896
AM		 3723 /* 1 possible extra opcode + 4 byte displacement go in var part.
3724 Pass reloc in fr_var. */
3725 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3726}
3e73aa7c 3727
29b0f896
AM		 3728static void
3729output_jump ()
3730{
3731 char *p;
3732 int size;
3e02c1cc 3733 fixS *fixP;
29b0f896
AM		 3734
3735 if (i.tm.opcode_modifier & JumpByte)
3736 {
3737 /* This is a loop or jecxz type instruction. */
3738 size = 1;
3739 if (i.prefix[ADDR_PREFIX] != 0)
3740 {
3741 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3742 i.prefixes -= 1;
3743 }
3744 /* Pentium4 branch hints. */
3745 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3746 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3747 {
3748 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3749 i.prefixes--;
3e73aa7c
JH		 3750 }
3751 }
29b0f896
AM		 3752 else
3753 {
3754 int code16;
3e73aa7c 3755
29b0f896
AM		 3756 code16 = 0;
3757 if (flag_code == CODE_16BIT)
3758 code16 = CODE16;
3e73aa7c 3759
29b0f896
AM		 3760 if (i.prefix[DATA_PREFIX] != 0)
3761 {
3762 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3763 i.prefixes -= 1;
3764 code16 ^= CODE16;
3765 }
252b5132 3766
29b0f896
AM		 3767 size = 4;
3768 if (code16)
3769 size = 2;
3770 }
9fcc94b6 3771
29b0f896
AM		 3772 if (i.prefix[REX_PREFIX] != 0)
3773 {
3774 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3775 i.prefixes -= 1;
3776 }
252b5132 3777
29b0f896
AM		 3778 if (i.prefixes != 0 && !intel_syntax)
3779 as_warn (_("skipping prefixes on this instruction"));
e0890092 3780
29b0f896
AM		 3781 p = frag_more (1 + size);
3782 *p++ = i.tm.base_opcode;
e0890092 3783
3e02c1cc
AM		 3784 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3785 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3786
3787 /* All jumps handled here are signed, but don't use a signed limit
3788 check for 32 and 16 bit jumps as we want to allow wrap around at
3789 4G and 64k respectively. */
3790 if (size == 1)
3791 fixP->fx_signed = 1;
29b0f896 3792}
e0890092 3793
29b0f896
AM		 3794static void
3795output_interseg_jump ()
3796{
3797 char *p;
3798 int size;
3799 int prefix;
3800 int code16;
252b5132 3801
29b0f896
AM		 3802 code16 = 0;
3803 if (flag_code == CODE_16BIT)
3804 code16 = CODE16;
a217f122 3805
29b0f896
AM		 3806 prefix = 0;
3807 if (i.prefix[DATA_PREFIX] != 0)
3808 {
3809 prefix = 1;
3810 i.prefixes -= 1;
3811 code16 ^= CODE16;
3812 }
3813 if (i.prefix[REX_PREFIX] != 0)
3814 {
3815 prefix++;
3816 i.prefixes -= 1;
3817 }
252b5132 3818
29b0f896
AM		 3819 size = 4;
3820 if (code16)
3821 size = 2;
252b5132 3822
29b0f896
AM		 3823 if (i.prefixes != 0 && !intel_syntax)
3824 as_warn (_("skipping prefixes on this instruction"));
252b5132 3825
29b0f896
AM		 3826 /* 1 opcode; 2 segment; offset */
3827 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3828
29b0f896
AM		 3829 if (i.prefix[DATA_PREFIX] != 0)
3830 *p++ = DATA_PREFIX_OPCODE;
252b5132 3831
29b0f896
AM		 3832 if (i.prefix[REX_PREFIX] != 0)
3833 *p++ = i.prefix[REX_PREFIX];
252b5132 3834
29b0f896
AM		 3835 *p++ = i.tm.base_opcode;
3836 if (i.op[1].imms->X_op == O_constant)
3837 {
3838 offsetT n = i.op[1].imms->X_add_number;
252b5132 3839
29b0f896
AM		 3840 if (size == 2
3841 && !fits_in_unsigned_word (n)
3842 && !fits_in_signed_word (n))
3843 {
3844 as_bad (_("16-bit jump out of range"));
3845 return;
3846 }
3847 md_number_to_chars (p, n, size);
3848 }
3849 else
3850 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3851 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3852 if (i.op[0].imms->X_op != O_constant)
3853 as_bad (_("can't handle non absolute segment in `%s'"),
3854 i.tm.name);
3855 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3856}
a217f122 3857
29b0f896
AM		 3858static void
3859output_insn ()
3860{
2bbd9c25
JJ		 3861 fragS *insn_start_frag;
3862 offsetT insn_start_off;
3863
29b0f896
AM		 3864 /* Tie dwarf2 debug info to the address at the start of the insn.
3865 We can't do this after the insn has been output as the current
3866 frag may have been closed off. eg. by frag_var. */
3867 dwarf2_emit_insn (0);
3868
2bbd9c25
JJ		 3869 insn_start_frag = frag_now;
3870 insn_start_off = frag_now_fix ();
3871
29b0f896
AM		 3872 /* Output jumps. */
3873 if (i.tm.opcode_modifier & Jump)
3874 output_branch ();
3875 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3876 output_jump ();
3877 else if (i.tm.opcode_modifier & JumpInterSegment)
3878 output_interseg_jump ();
3879 else
3880 {
3881 /* Output normal instructions here. */
3882 char *p;
3883 unsigned char *q;
331d2d0d 3884 unsigned int prefix;
252b5132 3885
331d2d0d
L		 3886 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3887 Instructions have 3 bytes. We may use one more higher byte
3888 to specify a prefix the instruction requires. */
3889 if ((i.tm.cpu_flags & CpuMNI) != 0)
bc4bd9ab 3890 {
331d2d0d
L		 3891 if (i.tm.base_opcode & 0xff000000)
3892 {
3893 prefix = (i.tm.base_opcode >> 24) & 0xff;
3894 goto check_prefix;
3895 }
3896 }
3897 else if ((i.tm.base_opcode & 0xff0000) != 0)
3898 {
3899 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3900 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3901 {
64e74474 3902 check_prefix:
bc4bd9ab
MK		 3903 if (prefix != REPE_PREFIX_OPCODE
3904 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3905 add_prefix (prefix);
3906 }
3907 else
331d2d0d 3908 add_prefix (prefix);
0f10071e 3909 }
252b5132 3910
29b0f896
AM		 3911 /* The prefix bytes. */
3912 for (q = i.prefix;
3913 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3914 q++)
3915 {
3916 if (*q)
3917 {
3918 p = frag_more (1);
3919 md_number_to_chars (p, (valueT) *q, 1);
3920 }
3921 }
252b5132 3922
29b0f896
AM		 3923 /* Now the opcode; be careful about word order here! */
3924 if (fits_in_unsigned_byte (i.tm.base_opcode))
3925 {
3926 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3927 }
3928 else
3929 {
331d2d0d
L		 3930 if ((i.tm.cpu_flags & CpuMNI) != 0)
3931 {
3932 p = frag_more (3);
3933 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3934 }
3935 else
3936 p = frag_more (2);
0f10071e 3937
29b0f896
AM		 3938 /* Put out high byte first: can't use md_number_to_chars! */
3939 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3940 *p = i.tm.base_opcode & 0xff;
3941 }
3e73aa7c 3942
29b0f896
AM		 3943 /* Now the modrm byte and sib byte (if present). */
3944 if (i.tm.opcode_modifier & Modrm)
3945 {
3946 p = frag_more (1);
3947 md_number_to_chars (p,
3948 (valueT) (i.rm.regmem << 0
3949 | i.rm.reg << 3
3950 | i.rm.mode << 6),
3951 1);
3952 /* If i.rm.regmem == ESP (4)
3953 && i.rm.mode != (Register mode)
3954 && not 16 bit
3955 ==> need second modrm byte. */
3956 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3957 && i.rm.mode != 3
3958 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3959 {
3960 p = frag_more (1);
3961 md_number_to_chars (p,
3962 (valueT) (i.sib.base << 0
3963 | i.sib.index << 3
3964 | i.sib.scale << 6),
3965 1);
3966 }
3967 }
3e73aa7c 3968
29b0f896 3969 if (i.disp_operands)
2bbd9c25 3970 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3971
29b0f896 3972 if (i.imm_operands)
2bbd9c25 3973 output_imm (insn_start_frag, insn_start_off);
29b0f896 3974 }
252b5132 3975
29b0f896
AM		 3976#ifdef DEBUG386
3977 if (flag_debug)
3978 {
7b81dfbb 3979 pi ("" /*line*/, &i);
29b0f896
AM		 3980 }
3981#endif /* DEBUG386 */
3982}
252b5132 3983
29b0f896 3984static void
64e74474 3985output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3986{
3987 char *p;
3988 unsigned int n;
252b5132 3989
29b0f896
AM		 3990 for (n = 0; n < i.operands; n++)
3991 {
3992 if (i.types[n] & Disp)
3993 {
3994 if (i.op[n].disps->X_op == O_constant)
3995 {
3996 int size;
3997 offsetT val;
252b5132 3998
29b0f896
AM		 3999 size = 4;
4000 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4001 {
4002 size = 2;
4003 if (i.types[n] & Disp8)
4004 size = 1;
4005 if (i.types[n] & Disp64)
4006 size = 8;
4007 }
4008 val = offset_in_range (i.op[n].disps->X_add_number,
4009 size);
4010 p = frag_more (size);
4011 md_number_to_chars (p, val, size);
4012 }
4013 else
4014 {
f86103b7 4015 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4016 int size = 4;
4017 int sign = 0;
4018 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4019
4020 /* The PC relative address is computed relative
4021 to the instruction boundary, so in case immediate
4022 fields follows, we need to adjust the value. */
4023 if (pcrel && i.imm_operands)
4024 {
4025 int imm_size = 4;
4026 unsigned int n1;
252b5132 4027
29b0f896
AM		 4028 for (n1 = 0; n1 < i.operands; n1++)
4029 if (i.types[n1] & Imm)
252b5132 4030 {
29b0f896 4031 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4032 {
29b0f896
AM		 4033 imm_size = 2;
4034 if (i.types[n1] & (Imm8 | Imm8S))
4035 imm_size = 1;
4036 if (i.types[n1] & Imm64)
4037 imm_size = 8;
252b5132 4038 }
29b0f896 4039 break;
252b5132 4040 }
29b0f896
AM		 4041 /* We should find the immediate. */
4042 if (n1 == i.operands)
4043 abort ();
4044 i.op[n].disps->X_add_number -= imm_size;
4045 }
520dc8e8 4046
29b0f896
AM		 4047 if (i.types[n] & Disp32S)
4048 sign = 1;
3e73aa7c 4049
29b0f896
AM		 4050 if (i.types[n] & (Disp16 | Disp64))
4051 {
4052 size = 2;
4053 if (i.types[n] & Disp64)
4054 size = 8;
4055 }
520dc8e8 4056
29b0f896 4057 p = frag_more (size);
2bbd9c25 4058 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4059 if (GOT_symbol
2bbd9c25 4060 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4061 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4062 || reloc_type == BFD_RELOC_X86_64_32S
4063 || (reloc_type == BFD_RELOC_64
4064 && object_64bit))
d6ab8113
JB		 4065 && (i.op[n].disps->X_op == O_symbol
4066 || (i.op[n].disps->X_op == O_add
4067 && ((symbol_get_value_expression
4068 (i.op[n].disps->X_op_symbol)->X_op)
4069 == O_subtract))))
4070 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4071 {
4072 offsetT add;
4073
4074 if (insn_start_frag == frag_now)
4075 add = (p - frag_now->fr_literal) - insn_start_off;
4076 else
4077 {
4078 fragS *fr;
4079
4080 add = insn_start_frag->fr_fix - insn_start_off;
4081 for (fr = insn_start_frag->fr_next;
4082 fr && fr != frag_now; fr = fr->fr_next)
4083 add += fr->fr_fix;
4084 add += p - frag_now->fr_literal;
4085 }
4086
4fa24527 4087 if (!object_64bit)
7b81dfbb
AJ		 4088 {
4089 reloc_type = BFD_RELOC_386_GOTPC;
4090 i.op[n].imms->X_add_number += add;
4091 }
4092 else if (reloc_type == BFD_RELOC_64)
4093 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4094 else
7b81dfbb
AJ		 4095 /* Don't do the adjustment for x86-64, as there
4096 the pcrel addressing is relative to the _next_
4097 insn, and that is taken care of in other code. */
d6ab8113 4098 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4099 }
062cd5e7 4100 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4101 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4102 }
4103 }
4104 }
4105}
252b5132 4106
29b0f896 4107static void
64e74474 4108output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4109{
4110 char *p;
4111 unsigned int n;
252b5132 4112
29b0f896
AM		 4113 for (n = 0; n < i.operands; n++)
4114 {
4115 if (i.types[n] & Imm)
4116 {
4117 if (i.op[n].imms->X_op == O_constant)
4118 {
4119 int size;
4120 offsetT val;
b4cac588 4121
29b0f896
AM		 4122 size = 4;
4123 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4124 {
4125 size = 2;
4126 if (i.types[n] & (Imm8 | Imm8S))
4127 size = 1;
4128 else if (i.types[n] & Imm64)
4129 size = 8;
4130 }
4131 val = offset_in_range (i.op[n].imms->X_add_number,
4132 size);
4133 p = frag_more (size);
4134 md_number_to_chars (p, val, size);
4135 }
4136 else
4137 {
4138 /* Not absolute_section.
4139 Need a 32-bit fixup (don't support 8bit
4140 non-absolute imms). Try to support other
4141 sizes ... */
f86103b7 4142 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4143 int size = 4;
4144 int sign = 0;
4145
4146 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4147 && (i.suffix == QWORD_MNEM_SUFFIX
4148 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4149 sign = 1;
4150 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4151 {
4152 size = 2;
4153 if (i.types[n] & (Imm8 | Imm8S))
4154 size = 1;
4155 if (i.types[n] & Imm64)
4156 size = 8;
4157 }
520dc8e8 4158
29b0f896
AM		 4159 p = frag_more (size);
4160 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4161
2bbd9c25
JJ		 4162 /* This is tough to explain. We end up with this one if we
4163 * have operands that look like
4164 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4165 * obtain the absolute address of the GOT, and it is strongly
4166 * preferable from a performance point of view to avoid using
4167 * a runtime relocation for this. The actual sequence of
4168 * instructions often look something like:
4169 *
4170 * call .L66
4171 * .L66:
4172 * popl %ebx
4173 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4174 *
4175 * The call and pop essentially return the absolute address
4176 * of the label .L66 and store it in %ebx. The linker itself
4177 * will ultimately change the first operand of the addl so
4178 * that %ebx points to the GOT, but to keep things simple, the
4179 * .o file must have this operand set so that it generates not
4180 * the absolute address of .L66, but the absolute address of
4181 * itself. This allows the linker itself simply treat a GOTPC
4182 * relocation as asking for a pcrel offset to the GOT to be
4183 * added in, and the addend of the relocation is stored in the
4184 * operand field for the instruction itself.
4185 *
4186 * Our job here is to fix the operand so that it would add
4187 * the correct offset so that %ebx would point to itself. The
4188 * thing that is tricky is that .-.L66 will point to the
4189 * beginning of the instruction, so we need to further modify
4190 * the operand so that it will point to itself. There are
4191 * other cases where you have something like:
4192 *
4193 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4194 *
4195 * and here no correction would be required. Internally in
4196 * the assembler we treat operands of this form as not being
4197 * pcrel since the '.' is explicitly mentioned, and I wonder
4198 * whether it would simplify matters to do it this way. Who
4199 * knows. In earlier versions of the PIC patches, the
4200 * pcrel_adjust field was used to store the correction, but
4201 * since the expression is not pcrel, I felt it would be
4202 * confusing to do it this way. */
4203
d6ab8113 4204 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4205 || reloc_type == BFD_RELOC_X86_64_32S
4206 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4207 && GOT_symbol
4208 && GOT_symbol == i.op[n].imms->X_add_symbol
4209 && (i.op[n].imms->X_op == O_symbol
4210 || (i.op[n].imms->X_op == O_add
4211 && ((symbol_get_value_expression
4212 (i.op[n].imms->X_op_symbol)->X_op)
4213 == O_subtract))))
4214 {
2bbd9c25
JJ		 4215 offsetT add;
4216
4217 if (insn_start_frag == frag_now)
4218 add = (p - frag_now->fr_literal) - insn_start_off;
4219 else
4220 {
4221 fragS *fr;
4222
4223 add = insn_start_frag->fr_fix - insn_start_off;
4224 for (fr = insn_start_frag->fr_next;
4225 fr && fr != frag_now; fr = fr->fr_next)
4226 add += fr->fr_fix;
4227 add += p - frag_now->fr_literal;
4228 }
4229
4fa24527 4230 if (!object_64bit)
d6ab8113 4231 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4232 else if (size == 4)
d6ab8113 4233 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4234 else if (size == 8)
4235 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4236 i.op[n].imms->X_add_number += add;
29b0f896 4237 }
29b0f896
AM		 4238 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4239 i.op[n].imms, 0, reloc_type);
4240 }
4241 }
4242 }
252b5132
RH		 4243}
4244\f
d182319b
JB		 4245/* x86_cons_fix_new is called via the expression parsing code when a
4246 reloc is needed. We use this hook to get the correct .got reloc. */
4247static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4248static int cons_sign = -1;
4249
4250void
4251x86_cons_fix_new (fragS *frag,
64e74474
AM		 4252 unsigned int off,
4253 unsigned int len,
4254 expressionS *exp)
d182319b
JB		 4255{
4256 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4257
4258 got_reloc = NO_RELOC;
4259
4260#ifdef TE_PE
4261 if (exp->X_op == O_secrel)
4262 {
4263 exp->X_op = O_symbol;
4264 r = BFD_RELOC_32_SECREL;
4265 }
4266#endif
4267
4268 fix_new_exp (frag, off, len, exp, 0, r);
4269}
4270
718ddfc0
JB		 4271#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4272# define lex_got(reloc, adjust, types) NULL
4273#else
f3c180ae
AM		 4274/* Parse operands of the form
4275 <symbol>@GOTOFF+<nnn>
4276 and similar .plt or .got references.
4277
4278 If we find one, set up the correct relocation in RELOC and copy the
4279 input string, minus the `@GOTOFF' into a malloc'd buffer for
4280 parsing by the calling routine. Return this buffer, and if ADJUST
4281 is non-null set it to the length of the string we removed from the
4282 input line. Otherwise return NULL. */
4283static char *
3956db08 4284lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4285 int *adjust,
4286 unsigned int *types)
f3c180ae 4287{
7b81dfbb
AJ		 4288 /* Some of the relocations depend on the size of what field is to
4289 be relocated. But in our callers i386_immediate and i386_displacement
4290 we don't yet know the operand size (this will be set by insn
4291 matching). Hence we record the word32 relocation here,
4292 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4293 static const struct {
4294 const char *str;
4fa24527 4295 const enum bfd_reloc_code_real rel[2];
3956db08 4296 const unsigned int types64;
f3c180ae 4297 } gotrel[] = {
7b81dfbb 4298 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4299 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4300 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4301 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4302 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4303 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4304 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4305 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4306 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4307 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4308 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4309 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4310 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4311 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4312 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4313 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4314 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4315 };
4316 char *cp;
4317 unsigned int j;
4318
718ddfc0
JB		 4319 if (!IS_ELF)
4320 return NULL;
4321
f3c180ae
AM		 4322 for (cp = input_line_pointer; *cp != '@'; cp++)
4323 if (is_end_of_line[(unsigned char) *cp])
4324 return NULL;
4325
4326 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4327 {
4328 int len;
4329
4330 len = strlen (gotrel[j].str);
28f81592 4331 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4332 {
4fa24527 4333 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4334 {
28f81592
AM		 4335 int first, second;
4336 char *tmpbuf, *past_reloc;
f3c180ae 4337
4fa24527 4338 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4339 if (adjust)
4340 *adjust = len;
f3c180ae 4341
3956db08
JB		 4342 if (types)
4343 {
4344 if (flag_code != CODE_64BIT)
4345 *types = Imm32|Disp32;
4346 else
4347 *types = gotrel[j].types64;
4348 }
4349
f3c180ae
AM		 4350 if (GOT_symbol == NULL)
4351 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4352
4353 /* Replace the relocation token with ' ', so that
4354 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4355
4356 /* The length of the first part of our input line. */
f3c180ae 4357 first = cp - input_line_pointer;
28f81592
AM		 4358
4359 /* The second part goes from after the reloc token until
4360 (and including) an end_of_line char. Don't use strlen
4361 here as the end_of_line char may not be a NUL. */
4362 past_reloc = cp + 1 + len;
4363 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4364 ;
4365 second = cp - past_reloc;
4366
4367 /* Allocate and copy string. The trailing NUL shouldn't
4368 be necessary, but be safe. */
4369 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4370 memcpy (tmpbuf, input_line_pointer, first);
4371 tmpbuf[first] = ' ';
28f81592
AM		 4372 memcpy (tmpbuf + first + 1, past_reloc, second);
4373 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4374 return tmpbuf;
4375 }
4376
4fa24527
JB		 4377 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4378 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4379 return NULL;
4380 }
4381 }
4382
4383 /* Might be a symbol version string. Don't as_bad here. */
4384 return NULL;
4385}
4386
f3c180ae
AM		 4387void
4388x86_cons (exp, size)
4389 expressionS *exp;
4390 int size;
4391{
4fa24527 4392 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4393 {
4394 /* Handle @GOTOFF and the like in an expression. */
4395 char *save;
4396 char *gotfree_input_line;
4397 int adjust;
4398
4399 save = input_line_pointer;
3956db08 4400 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4401 if (gotfree_input_line)
4402 input_line_pointer = gotfree_input_line;
4403
4404 expression (exp);
4405
4406 if (gotfree_input_line)
4407 {
4408 /* expression () has merrily parsed up to the end of line,
4409 or a comma - in the wrong buffer. Transfer how far
4410 input_line_pointer has moved to the right buffer. */
4411 input_line_pointer = (save
4412 + (input_line_pointer - gotfree_input_line)
4413 + adjust);
4414 free (gotfree_input_line);
4415 }
4416 }
4417 else
4418 expression (exp);
4419}
4420#endif
4421
d182319b 4422static void signed_cons (int size)
6482c264 4423{
d182319b
JB		 4424 if (flag_code == CODE_64BIT)
4425 cons_sign = 1;
4426 cons (size);
4427 cons_sign = -1;
6482c264
NC		 4428}
4429
d182319b 4430#ifdef TE_PE
6482c264
NC		 4431static void
4432pe_directive_secrel (dummy)
4433 int dummy ATTRIBUTE_UNUSED;
4434{
4435 expressionS exp;
4436
4437 do
4438 {
4439 expression (&exp);
4440 if (exp.X_op == O_symbol)
4441 exp.X_op = O_secrel;
4442
4443 emit_expr (&exp, 4);
4444 }
4445 while (*input_line_pointer++ == ',');
4446
4447 input_line_pointer--;
4448 demand_empty_rest_of_line ();
4449}
6482c264
NC		 4450#endif
4451
252b5132
RH		 4452static int i386_immediate PARAMS ((char *));
4453
4454static int
4455i386_immediate (imm_start)
4456 char *imm_start;
4457{
4458 char *save_input_line_pointer;
f3c180ae 4459 char *gotfree_input_line;
252b5132 4460 segT exp_seg = 0;
47926f60 4461 expressionS *exp;
3956db08 4462 unsigned int types = ~0U;
252b5132
RH		 4463
4464 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4465 {
d0b47220 4466 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4467 return 0;
4468 }
4469
4470 exp = &im_expressions[i.imm_operands++];
520dc8e8 4471 i.op[this_operand].imms = exp;
252b5132
RH		 4472
4473 if (is_space_char (*imm_start))
4474 ++imm_start;
4475
4476 save_input_line_pointer = input_line_pointer;
4477 input_line_pointer = imm_start;
4478
3956db08 4479 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4480 if (gotfree_input_line)
4481 input_line_pointer = gotfree_input_line;
252b5132
RH		 4482
4483 exp_seg = expression (exp);
4484
83183c0c 4485 SKIP_WHITESPACE ();
252b5132 4486 if (*input_line_pointer)
f3c180ae 4487 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4488
4489 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4490 if (gotfree_input_line)
4491 free (gotfree_input_line);
252b5132 4492
2daf4fd8 4493 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4494 {
47926f60 4495 /* Missing or bad expr becomes absolute 0. */
d0b47220 4496 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4497 imm_start);
252b5132
RH		 4498 exp->X_op = O_constant;
4499 exp->X_add_number = 0;
4500 exp->X_add_symbol = (symbolS *) 0;
4501 exp->X_op_symbol = (symbolS *) 0;
252b5132 4502 }
3e73aa7c 4503 else if (exp->X_op == O_constant)
252b5132 4504 {
47926f60 4505 /* Size it properly later. */
3e73aa7c
JH		 4506 i.types[this_operand] |= Imm64;
4507 /* If BFD64, sign extend val. */
4508 if (!use_rela_relocations)
4509 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4510 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4511 }
4c63da97 4512#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4513 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4514 && exp_seg != absolute_section
47926f60 4515 && exp_seg != text_section
24eab124
AM		 4516 && exp_seg != data_section
4517 && exp_seg != bss_section
4518 && exp_seg != undefined_section
f86103b7 4519 && !bfd_is_com_section (exp_seg))
252b5132 4520 {
d0b47220 4521 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4522 return 0;
4523 }
4524#endif
bb8f5920
L		 4525 else if (!intel_syntax && exp->X_op == O_register)
4526 {
4527 as_bad (_("illegal immediate register operand %s"), imm_start);
4528 return 0;
4529 }
252b5132
RH		 4530 else
4531 {
4532 /* This is an address. The size of the address will be
24eab124 4533 determined later, depending on destination register,
3e73aa7c
JH		 4534 suffix, or the default for the section. */
4535 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4536 i.types[this_operand] &= types;
252b5132
RH		 4537 }
4538
4539 return 1;
4540}
4541
551c1ca1 4542static char *i386_scale PARAMS ((char *));
252b5132 4543
551c1ca1 4544static char *
252b5132
RH		 4545i386_scale (scale)
4546 char *scale;
4547{
551c1ca1
AM		 4548 offsetT val;
4549 char *save = input_line_pointer;
252b5132 4550
551c1ca1
AM		 4551 input_line_pointer = scale;
4552 val = get_absolute_expression ();
4553
4554 switch (val)
252b5132 4555 {
551c1ca1 4556 case 1:
252b5132
RH		 4557 i.log2_scale_factor = 0;
4558 break;
551c1ca1 4559 case 2:
252b5132
RH		 4560 i.log2_scale_factor = 1;
4561 break;
551c1ca1 4562 case 4:
252b5132
RH		 4563 i.log2_scale_factor = 2;
4564 break;
551c1ca1 4565 case 8:
252b5132
RH		 4566 i.log2_scale_factor = 3;
4567 break;
4568 default:
a724f0f4
JB		 4569 {
4570 char sep = *input_line_pointer;
4571
4572 *input_line_pointer = '\0';
4573 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4574 scale);
4575 *input_line_pointer = sep;
4576 input_line_pointer = save;
4577 return NULL;
4578 }
252b5132 4579 }
29b0f896 4580 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4581 {
4582 as_warn (_("scale factor of %d without an index register"),
24eab124 4583 1 << i.log2_scale_factor);
252b5132
RH		 4584#if SCALE1_WHEN_NO_INDEX
4585 i.log2_scale_factor = 0;
4586#endif
4587 }
551c1ca1
AM		 4588 scale = input_line_pointer;
4589 input_line_pointer = save;
4590 return scale;
252b5132
RH		 4591}
4592
4593static int i386_displacement PARAMS ((char *, char *));
4594
4595static int
4596i386_displacement (disp_start, disp_end)
4597 char *disp_start;
4598 char *disp_end;
4599{
29b0f896 4600 expressionS *exp;
252b5132
RH		 4601 segT exp_seg = 0;
4602 char *save_input_line_pointer;
f3c180ae 4603 char *gotfree_input_line;
e05278af 4604 int bigdisp, override;
3956db08 4605 unsigned int types = Disp;
252b5132 4606
e05278af
JB		 4607 if ((i.types[this_operand] & JumpAbsolute)
4608 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4609 {
4610 bigdisp = Disp32;
4611 override = (i.prefix[ADDR_PREFIX] != 0);
4612 }
4613 else
4614 {
4615 /* For PC-relative branches, the width of the displacement
4616 is dependent upon data size, not address size. */
4617 bigdisp = 0;
4618 override = (i.prefix[DATA_PREFIX] != 0);
4619 }
3e73aa7c 4620 if (flag_code == CODE_64BIT)
7ecd2f8b 4621 {
e05278af 4622 if (!bigdisp)
64e74474
AM		 4623 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4624 ? Disp16
4625 : Disp32S | Disp32);
e05278af 4626 else if (!override)
3956db08 4627 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4628 }
e05278af
JB		 4629 else
4630 {
4631 if (!bigdisp)
4632 {
4633 if (!override)
4634 override = (i.suffix == (flag_code != CODE_16BIT
4635 ? WORD_MNEM_SUFFIX
4636 : LONG_MNEM_SUFFIX));
4637 bigdisp = Disp32;
4638 }
4639 if ((flag_code == CODE_16BIT) ^ override)
4640 bigdisp = Disp16;
4641 }
252b5132
RH		 4642 i.types[this_operand] |= bigdisp;
4643
4644 exp = &disp_expressions[i.disp_operands];
520dc8e8 4645 i.op[this_operand].disps = exp;
252b5132
RH		 4646 i.disp_operands++;
4647 save_input_line_pointer = input_line_pointer;
4648 input_line_pointer = disp_start;
4649 END_STRING_AND_SAVE (disp_end);
4650
4651#ifndef GCC_ASM_O_HACK
4652#define GCC_ASM_O_HACK 0
4653#endif
4654#if GCC_ASM_O_HACK
4655 END_STRING_AND_SAVE (disp_end + 1);
4656 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4657 && displacement_string_end[-1] == '+')
252b5132
RH		 4658 {
4659 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4660 constraint within gcc asm statements.
4661 For instance:
4662
4663 #define _set_tssldt_desc(n,addr,limit,type) \
4664 __asm__ __volatile__ ( \
4665 "movw %w2,%0\n\t" \
4666 "movw %w1,2+%0\n\t" \
4667 "rorl $16,%1\n\t" \
4668 "movb %b1,4+%0\n\t" \
4669 "movb %4,5+%0\n\t" \
4670 "movb $0,6+%0\n\t" \
4671 "movb %h1,7+%0\n\t" \
4672 "rorl $16,%1" \
4673 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4674
4675 This works great except that the output assembler ends
4676 up looking a bit weird if it turns out that there is
4677 no offset. You end up producing code that looks like:
4678
4679 #APP
4680 movw $235,(%eax)
4681 movw %dx,2+(%eax)
4682 rorl $16,%edx
4683 movb %dl,4+(%eax)
4684 movb $137,5+(%eax)
4685 movb $0,6+(%eax)
4686 movb %dh,7+(%eax)
4687 rorl $16,%edx
4688 #NO_APP
4689
47926f60 4690 So here we provide the missing zero. */
24eab124
AM		 4691
4692 *displacement_string_end = '0';
252b5132
RH		 4693 }
4694#endif
3956db08 4695 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4696 if (gotfree_input_line)
4697 input_line_pointer = gotfree_input_line;
252b5132 4698
24eab124 4699 exp_seg = expression (exp);
252b5132 4700
636c26b0
AM		 4701 SKIP_WHITESPACE ();
4702 if (*input_line_pointer)
4703 as_bad (_("junk `%s' after expression"), input_line_pointer);
4704#if GCC_ASM_O_HACK
4705 RESTORE_END_STRING (disp_end + 1);
4706#endif
4707 RESTORE_END_STRING (disp_end);
4708 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4709 if (gotfree_input_line)
4710 free (gotfree_input_line);
636c26b0 4711
24eab124
AM		 4712 /* We do this to make sure that the section symbol is in
4713 the symbol table. We will ultimately change the relocation
47926f60 4714 to be relative to the beginning of the section. */
1ae12ab7 4715 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4716 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4717 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4718 {
636c26b0
AM		 4719 if (exp->X_op != O_symbol)
4720 {
4721 as_bad (_("bad expression used with @%s"),
4722 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4723 ? "GOTPCREL"
4724 : "GOTOFF"));
4725 return 0;
4726 }
4727
e5cb08ac 4728 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4729 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4730 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4731 exp->X_op = O_subtract;
4732 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4733 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4734 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4735 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4736 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4737 else
29b0f896 4738 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4739 }
252b5132 4740
2daf4fd8
AM		 4741 if (exp->X_op == O_absent || exp->X_op == O_big)
4742 {
47926f60 4743 /* Missing or bad expr becomes absolute 0. */
d0b47220 4744 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4745 disp_start);
4746 exp->X_op = O_constant;
4747 exp->X_add_number = 0;
4748 exp->X_add_symbol = (symbolS *) 0;
4749 exp->X_op_symbol = (symbolS *) 0;
4750 }
4751
4c63da97 4752#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4753 if (exp->X_op != O_constant
45288df1 4754 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4755 && exp_seg != absolute_section
45288df1
AM		 4756 && exp_seg != text_section
4757 && exp_seg != data_section
4758 && exp_seg != bss_section
31312f95 4759 && exp_seg != undefined_section
f86103b7 4760 && !bfd_is_com_section (exp_seg))
24eab124 4761 {
d0b47220 4762 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4763 return 0;
4764 }
252b5132 4765#endif
3956db08
JB		 4766
4767 if (!(i.types[this_operand] & ~Disp))
4768 i.types[this_operand] &= types;
4769
252b5132
RH		 4770 return 1;
4771}
4772
e5cb08ac 4773static int i386_index_check PARAMS ((const char *));
252b5132 4774
eecb386c 4775/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4776 Return 1 on success, 0 on a failure. */
4777
252b5132 4778static int
eecb386c
AM		 4779i386_index_check (operand_string)
4780 const char *operand_string;
252b5132 4781{
3e73aa7c 4782 int ok;
24eab124 4783#if INFER_ADDR_PREFIX
eecb386c
AM		 4784 int fudged = 0;
4785
24eab124
AM		 4786 tryprefix:
4787#endif
3e73aa7c 4788 ok = 1;
30123838
JB		 4789 if ((current_templates->start->cpu_flags & CpuSVME)
4790 && current_templates->end[-1].operand_types[0] == AnyMem)
4791 {
4792 /* Memory operands of SVME insns are special in that they only allow
4793 rAX as their memory address and ignore any segment override. */
4794 unsigned RegXX;
4795
4796 /* SKINIT is even more restrictive: it always requires EAX. */
4797 if (strcmp (current_templates->start->name, "skinit") == 0)
4798 RegXX = Reg32;
4799 else if (flag_code == CODE_64BIT)
4800 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4801 else
64e74474
AM		 4802 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4803 ? Reg16
4804 : Reg32);
30123838
JB		 4805 if (!i.base_reg
4806 || !(i.base_reg->reg_type & Acc)
4807 || !(i.base_reg->reg_type & RegXX)
4808 || i.index_reg
4809 || (i.types[0] & Disp))
4810 ok = 0;
4811 }
4812 else if (flag_code == CODE_64BIT)
64e74474
AM		 4813 {
4814 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4815
4816 if ((i.base_reg
4817 && ((i.base_reg->reg_type & RegXX) == 0)
4818 && (i.base_reg->reg_type != BaseIndex
4819 || i.index_reg))
4820 || (i.index_reg
4821 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4822 != (RegXX | BaseIndex))))
4823 ok = 0;
3e73aa7c
JH		 4824 }
4825 else
4826 {
4827 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4828 {
4829 /* 16bit checks. */
4830 if ((i.base_reg
29b0f896
AM		 4831 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4832 != (Reg16 | BaseIndex)))
3e73aa7c 4833 || (i.index_reg
29b0f896
AM		 4834 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4835 != (Reg16 | BaseIndex))
4836 || !(i.base_reg
4837 && i.base_reg->reg_num < 6
4838 && i.index_reg->reg_num >= 6
4839 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4840 ok = 0;
4841 }
4842 else
e5cb08ac 4843 {
3e73aa7c
JH		 4844 /* 32bit checks. */
4845 if ((i.base_reg
4846 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4847 || (i.index_reg
29b0f896
AM		 4848 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4849 != (Reg32 | BaseIndex))))
e5cb08ac 4850 ok = 0;
3e73aa7c
JH		 4851 }
4852 }
4853 if (!ok)
24eab124
AM		 4854 {
4855#if INFER_ADDR_PREFIX
20f0a1fc 4856 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4857 {
4858 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4859 i.prefixes += 1;
b23bac36
AM		 4860 /* Change the size of any displacement too. At most one of
4861 Disp16 or Disp32 is set.
4862 FIXME. There doesn't seem to be any real need for separate
4863 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4864 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4865 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4866 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4867 fudged = 1;
24eab124
AM		 4868 goto tryprefix;
4869 }
eecb386c
AM		 4870 if (fudged)
4871 as_bad (_("`%s' is not a valid base/index expression"),
4872 operand_string);
4873 else
c388dee8 4874#endif
eecb386c
AM		 4875 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4876 operand_string,
3e73aa7c 4877 flag_code_names[flag_code]);
24eab124 4878 }
20f0a1fc 4879 return ok;
24eab124 4880}
252b5132 4881
252b5132 4882/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4883 on error. */
252b5132 4884
252b5132
RH		 4885static int
4886i386_operand (operand_string)
4887 char *operand_string;
4888{
af6bdddf
AM		 4889 const reg_entry *r;
4890 char *end_op;
24eab124 4891 char *op_string = operand_string;
252b5132 4892
24eab124 4893 if (is_space_char (*op_string))
252b5132
RH		 4894 ++op_string;
4895
24eab124 4896 /* We check for an absolute prefix (differentiating,
47926f60 4897 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4898 if (*op_string == ABSOLUTE_PREFIX)
4899 {
4900 ++op_string;
4901 if (is_space_char (*op_string))
4902 ++op_string;
4903 i.types[this_operand] |= JumpAbsolute;
4904 }
252b5132 4905
47926f60 4906 /* Check if operand is a register. */
4d1bb795 4907 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4908 {
24eab124
AM		 4909 /* Check for a segment override by searching for ':' after a
4910 segment register. */
4911 op_string = end_op;
4912 if (is_space_char (*op_string))
4913 ++op_string;
4914 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4915 {
4916 switch (r->reg_num)
4917 {
4918 case 0:
4919 i.seg[i.mem_operands] = &es;
4920 break;
4921 case 1:
4922 i.seg[i.mem_operands] = &cs;
4923 break;
4924 case 2:
4925 i.seg[i.mem_operands] = &ss;
4926 break;
4927 case 3:
4928 i.seg[i.mem_operands] = &ds;
4929 break;
4930 case 4:
4931 i.seg[i.mem_operands] = &fs;
4932 break;
4933 case 5:
4934 i.seg[i.mem_operands] = &gs;
4935 break;
4936 }
252b5132 4937
24eab124 4938 /* Skip the ':' and whitespace. */
252b5132
RH		 4939 ++op_string;
4940 if (is_space_char (*op_string))
24eab124 4941 ++op_string;
252b5132 4942
24eab124
AM		 4943 if (!is_digit_char (*op_string)
4944 && !is_identifier_char (*op_string)
4945 && *op_string != '('
4946 && *op_string != ABSOLUTE_PREFIX)
4947 {
4948 as_bad (_("bad memory operand `%s'"), op_string);
4949 return 0;
4950 }
47926f60 4951 /* Handle case of %es:*foo. */
24eab124
AM		 4952 if (*op_string == ABSOLUTE_PREFIX)
4953 {
4954 ++op_string;
4955 if (is_space_char (*op_string))
4956 ++op_string;
4957 i.types[this_operand] |= JumpAbsolute;
4958 }
4959 goto do_memory_reference;
4960 }
4961 if (*op_string)
4962 {
d0b47220 4963 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4964 return 0;
4965 }
4966 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4967 i.op[this_operand].regs = r;
24eab124
AM		 4968 i.reg_operands++;
4969 }
af6bdddf
AM		 4970 else if (*op_string == REGISTER_PREFIX)
4971 {
4972 as_bad (_("bad register name `%s'"), op_string);
4973 return 0;
4974 }
24eab124 4975 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4976 {
24eab124
AM		 4977 ++op_string;
4978 if (i.types[this_operand] & JumpAbsolute)
4979 {
d0b47220 4980 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4981 return 0;
4982 }
4983 if (!i386_immediate (op_string))
4984 return 0;
4985 }
4986 else if (is_digit_char (*op_string)
4987 || is_identifier_char (*op_string)
e5cb08ac 4988 || *op_string == '(')
24eab124 4989 {
47926f60 4990 /* This is a memory reference of some sort. */
af6bdddf 4991 char *base_string;
252b5132 4992
47926f60 4993 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4994 char *displacement_string_start;
4995 char *displacement_string_end;
252b5132 4996
24eab124 4997 do_memory_reference:
24eab124
AM		 4998 if ((i.mem_operands == 1
4999 && (current_templates->start->opcode_modifier & IsString) == 0)
5000 || i.mem_operands == 2)
5001 {
5002 as_bad (_("too many memory references for `%s'"),
5003 current_templates->start->name);
5004 return 0;
5005 }
252b5132 5006
24eab124
AM		 5007 /* Check for base index form. We detect the base index form by
5008 looking for an ')' at the end of the operand, searching
5009 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5010 after the '('. */
af6bdddf 5011 base_string = op_string + strlen (op_string);
c3332e24 5012
af6bdddf
AM		 5013 --base_string;
5014 if (is_space_char (*base_string))
5015 --base_string;
252b5132 5016
47926f60 5017 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5018 displacement_string_start = op_string;
5019 displacement_string_end = base_string + 1;
252b5132 5020
24eab124
AM		 5021 if (*base_string == ')')
5022 {
af6bdddf 5023 char *temp_string;
24eab124
AM		 5024 unsigned int parens_balanced = 1;
5025 /* We've already checked that the number of left & right ()'s are
47926f60 5026 equal, so this loop will not be infinite. */
24eab124
AM		 5027 do
5028 {
5029 base_string--;
5030 if (*base_string == ')')
5031 parens_balanced++;
5032 if (*base_string == '(')
5033 parens_balanced--;
5034 }
5035 while (parens_balanced);
c3332e24 5036
af6bdddf 5037 temp_string = base_string;
c3332e24 5038
24eab124 5039 /* Skip past '(' and whitespace. */
252b5132
RH		 5040 ++base_string;
5041 if (is_space_char (*base_string))
24eab124 5042 ++base_string;
252b5132 5043
af6bdddf 5044 if (*base_string == ','
4d1bb795 5045 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 5046 {
af6bdddf 5047 displacement_string_end = temp_string;
252b5132 5048
af6bdddf 5049 i.types[this_operand] |= BaseIndex;
252b5132 5050
af6bdddf 5051 if (i.base_reg)
24eab124 5052 {
24eab124
AM		 5053 base_string = end_op;
5054 if (is_space_char (*base_string))
5055 ++base_string;
af6bdddf
AM		 5056 }
5057
5058 /* There may be an index reg or scale factor here. */
5059 if (*base_string == ',')
5060 {
5061 ++base_string;
5062 if (is_space_char (*base_string))
5063 ++base_string;
5064
4d1bb795 5065 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5066 {
af6bdddf 5067 base_string = end_op;
24eab124
AM		 5068 if (is_space_char (*base_string))
5069 ++base_string;
af6bdddf
AM		 5070 if (*base_string == ',')
5071 {
5072 ++base_string;
5073 if (is_space_char (*base_string))
5074 ++base_string;
5075 }
e5cb08ac 5076 else if (*base_string != ')')
af6bdddf
AM		 5077 {
5078 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5079 operand_string);
5080 return 0;
5081 }
24eab124 5082 }
af6bdddf 5083 else if (*base_string == REGISTER_PREFIX)
24eab124 5084 {
af6bdddf 5085 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5086 return 0;
5087 }
252b5132 5088
47926f60 5089 /* Check for scale factor. */
551c1ca1 5090 if (*base_string != ')')
af6bdddf 5091 {
551c1ca1
AM		 5092 char *end_scale = i386_scale (base_string);
5093
5094 if (!end_scale)
af6bdddf 5095 return 0;
24eab124 5096
551c1ca1 5097 base_string = end_scale;
af6bdddf
AM		 5098 if (is_space_char (*base_string))
5099 ++base_string;
5100 if (*base_string != ')')
5101 {
5102 as_bad (_("expecting `)' after scale factor in `%s'"),
5103 operand_string);
5104 return 0;
5105 }
5106 }
5107 else if (!i.index_reg)
24eab124 5108 {
af6bdddf
AM		 5109 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5110 *base_string);
24eab124
AM		 5111 return 0;
5112 }
5113 }
af6bdddf 5114 else if (*base_string != ')')
24eab124 5115 {
af6bdddf
AM		 5116 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5117 operand_string);
24eab124
AM		 5118 return 0;
5119 }
c3332e24 5120 }
af6bdddf 5121 else if (*base_string == REGISTER_PREFIX)
c3332e24 5122 {
af6bdddf 5123 as_bad (_("bad register name `%s'"), base_string);
24eab124 5124 return 0;
c3332e24 5125 }
24eab124
AM		 5126 }
5127
5128 /* If there's an expression beginning the operand, parse it,
5129 assuming displacement_string_start and
5130 displacement_string_end are meaningful. */
5131 if (displacement_string_start != displacement_string_end)
5132 {
5133 if (!i386_displacement (displacement_string_start,
5134 displacement_string_end))
5135 return 0;
5136 }
5137
5138 /* Special case for (%dx) while doing input/output op. */
5139 if (i.base_reg
5140 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5141 && i.index_reg == 0
5142 && i.log2_scale_factor == 0
5143 && i.seg[i.mem_operands] == 0
5144 && (i.types[this_operand] & Disp) == 0)
5145 {
5146 i.types[this_operand] = InOutPortReg;
5147 return 1;
5148 }
5149
eecb386c
AM		 5150 if (i386_index_check (operand_string) == 0)
5151 return 0;
24eab124
AM		 5152 i.mem_operands++;
5153 }
5154 else
ce8a8b2f
AM		 5155 {
5156 /* It's not a memory operand; argh! */
24eab124
AM		 5157 as_bad (_("invalid char %s beginning operand %d `%s'"),
5158 output_invalid (*op_string),
5159 this_operand + 1,
5160 op_string);
5161 return 0;
5162 }
47926f60 5163 return 1; /* Normal return. */
252b5132
RH		 5164}
5165\f
ee7fcc42
AM		 5166/* md_estimate_size_before_relax()
5167
5168 Called just before relax() for rs_machine_dependent frags. The x86
5169 assembler uses these frags to handle variable size jump
5170 instructions.
5171
5172 Any symbol that is now undefined will not become defined.
5173 Return the correct fr_subtype in the frag.
5174 Return the initial "guess for variable size of frag" to caller.
5175 The guess is actually the growth beyond the fixed part. Whatever
5176 we do to grow the fixed or variable part contributes to our
5177 returned value. */
5178
252b5132
RH		 5179int
5180md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5181 fragS *fragP;
5182 segT segment;
252b5132 5183{
252b5132 5184 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5185 check for un-relaxable symbols. On an ELF system, we can't relax
5186 an externally visible symbol, because it may be overridden by a
5187 shared library. */
5188 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5190 || (IS_ELF
31312f95
AM		 5191 && (S_IS_EXTERNAL (fragP->fr_symbol)
5192 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5193#endif
5194 )
252b5132 5195 {
b98ef147
AM		 5196 /* Symbol is undefined in this segment, or we need to keep a
5197 reloc so that weak symbols can be overridden. */
5198 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5199 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5200 unsigned char *opcode;
5201 int old_fr_fix;
f6af82bd 5202
ee7fcc42
AM		 5203 if (fragP->fr_var != NO_RELOC)
5204 reloc_type = fragP->fr_var;
b98ef147 5205 else if (size == 2)
f6af82bd
AM		 5206 reloc_type = BFD_RELOC_16_PCREL;
5207 else
5208 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5209
ee7fcc42
AM		 5210 old_fr_fix = fragP->fr_fix;
5211 opcode = (unsigned char *) fragP->fr_opcode;
5212
fddf5b5b 5213 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5214 {
fddf5b5b
AM		 5215 case UNCOND_JUMP:
5216 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5217 opcode[0] = 0xe9;
252b5132 5218 fragP->fr_fix += size;
062cd5e7
AS		 5219 fix_new (fragP, old_fr_fix, size,
5220 fragP->fr_symbol,
5221 fragP->fr_offset, 1,
5222 reloc_type);
252b5132
RH		 5223 break;
5224
fddf5b5b 5225 case COND_JUMP86:
412167cb
AM		 5226 if (size == 2
5227 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5228 {
5229 /* Negate the condition, and branch past an
5230 unconditional jump. */
5231 opcode[0] ^= 1;
5232 opcode[1] = 3;
5233 /* Insert an unconditional jump. */
5234 opcode[2] = 0xe9;
5235 /* We added two extra opcode bytes, and have a two byte
5236 offset. */
5237 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5238 fix_new (fragP, old_fr_fix + 2, 2,
5239 fragP->fr_symbol,
5240 fragP->fr_offset, 1,
5241 reloc_type);
fddf5b5b
AM		 5242 break;
5243 }
5244 /* Fall through. */
5245
5246 case COND_JUMP:
412167cb
AM		 5247 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5248 {
3e02c1cc
AM		 5249 fixS *fixP;
5250
412167cb 5251 fragP->fr_fix += 1;
3e02c1cc
AM		 5252 fixP = fix_new (fragP, old_fr_fix, 1,
5253 fragP->fr_symbol,
5254 fragP->fr_offset, 1,
5255 BFD_RELOC_8_PCREL);
5256 fixP->fx_signed = 1;
412167cb
AM		 5257 break;
5258 }
93c2a809 5259
24eab124 5260 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5261 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5262 opcode[1] = opcode[0] + 0x10;
f6af82bd 5263 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5264 /* We've added an opcode byte. */
5265 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5266 fix_new (fragP, old_fr_fix + 1, size,
5267 fragP->fr_symbol,
5268 fragP->fr_offset, 1,
5269 reloc_type);
252b5132 5270 break;
fddf5b5b
AM		 5271
5272 default:
5273 BAD_CASE (fragP->fr_subtype);
5274 break;
252b5132
RH		 5275 }
5276 frag_wane (fragP);
ee7fcc42 5277 return fragP->fr_fix - old_fr_fix;
252b5132 5278 }
93c2a809 5279
93c2a809
AM		 5280 /* Guess size depending on current relax state. Initially the relax
5281 state will correspond to a short jump and we return 1, because
5282 the variable part of the frag (the branch offset) is one byte
5283 long. However, we can relax a section more than once and in that
5284 case we must either set fr_subtype back to the unrelaxed state,
5285 or return the value for the appropriate branch. */
5286 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5287}
5288
47926f60
KH		 5289/* Called after relax() is finished.
5290
5291 In: Address of frag.
5292 fr_type == rs_machine_dependent.
5293 fr_subtype is what the address relaxed to.
5294
5295 Out: Any fixSs and constants are set up.
5296 Caller will turn frag into a ".space 0". */
5297
252b5132
RH		 5298void
5299md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5300 bfd *abfd ATTRIBUTE_UNUSED;
5301 segT sec ATTRIBUTE_UNUSED;
29b0f896 5302 fragS *fragP;
252b5132 5303{
29b0f896 5304 unsigned char *opcode;
252b5132 5305 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5306 offsetT target_address;
5307 offsetT opcode_address;
252b5132 5308 unsigned int extension = 0;
847f7ad4 5309 offsetT displacement_from_opcode_start;
252b5132
RH		 5310
5311 opcode = (unsigned char *) fragP->fr_opcode;
5312
47926f60 5313 /* Address we want to reach in file space. */
252b5132 5314 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5315
47926f60 5316 /* Address opcode resides at in file space. */
252b5132
RH		 5317 opcode_address = fragP->fr_address + fragP->fr_fix;
5318
47926f60 5319 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5320 displacement_from_opcode_start = target_address - opcode_address;
5321
fddf5b5b 5322 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5323 {
47926f60
KH		 5324 /* Don't have to change opcode. */
5325 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5326 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5327 }
5328 else
5329 {
5330 if (no_cond_jump_promotion
5331 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5332 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5333
fddf5b5b
AM		 5334 switch (fragP->fr_subtype)
5335 {
5336 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5337 extension = 4; /* 1 opcode + 4 displacement */
5338 opcode[0] = 0xe9;
5339 where_to_put_displacement = &opcode[1];
5340 break;
252b5132 5341
fddf5b5b
AM		 5342 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5343 extension = 2; /* 1 opcode + 2 displacement */
5344 opcode[0] = 0xe9;
5345 where_to_put_displacement = &opcode[1];
5346 break;
252b5132 5347
fddf5b5b
AM		 5348 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5349 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5350 extension = 5; /* 2 opcode + 4 displacement */
5351 opcode[1] = opcode[0] + 0x10;
5352 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5353 where_to_put_displacement = &opcode[2];
5354 break;
252b5132 5355
fddf5b5b
AM		 5356 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5357 extension = 3; /* 2 opcode + 2 displacement */
5358 opcode[1] = opcode[0] + 0x10;
5359 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5360 where_to_put_displacement = &opcode[2];
5361 break;
252b5132 5362
fddf5b5b
AM		 5363 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5364 extension = 4;
5365 opcode[0] ^= 1;
5366 opcode[1] = 3;
5367 opcode[2] = 0xe9;
5368 where_to_put_displacement = &opcode[3];
5369 break;
5370
5371 default:
5372 BAD_CASE (fragP->fr_subtype);
5373 break;
5374 }
252b5132 5375 }
fddf5b5b 5376
7b81dfbb
AJ		 5377 /* If size if less then four we are sure that the operand fits,
5378 but if it's 4, then it could be that the displacement is larger
5379 then -/+ 2GB. */
5380 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5381 && object_64bit
5382 && ((addressT) (displacement_from_opcode_start - extension
5383 + ((addressT) 1 << 31))
5384 > (((addressT) 2 << 31) - 1)))
5385 {
5386 as_bad_where (fragP->fr_file, fragP->fr_line,
5387 _("jump target out of range"));
5388 /* Make us emit 0. */
5389 displacement_from_opcode_start = extension;
5390 }
47926f60 5391 /* Now put displacement after opcode. */
252b5132
RH		 5392 md_number_to_chars ((char *) where_to_put_displacement,
5393 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5394 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5395 fragP->fr_fix += extension;
5396}
5397\f
47926f60
KH		 5398/* Size of byte displacement jmp. */
5399int md_short_jump_size = 2;
5400
5401/* Size of dword displacement jmp. */
5402int md_long_jump_size = 5;
252b5132 5403
252b5132
RH		 5404void
5405md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5406 char *ptr;
5407 addressT from_addr, to_addr;
ab9da554
ILT		 5408 fragS *frag ATTRIBUTE_UNUSED;
5409 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5410{
847f7ad4 5411 offsetT offset;
252b5132
RH		 5412
5413 offset = to_addr - (from_addr + 2);
47926f60
KH		 5414 /* Opcode for byte-disp jump. */
5415 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5416 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5417}
5418
5419void
5420md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5421 char *ptr;
5422 addressT from_addr, to_addr;
a38cf1db
AM		 5423 fragS *frag ATTRIBUTE_UNUSED;
5424 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5425{
847f7ad4 5426 offsetT offset;
252b5132 5427
a38cf1db
AM		 5428 offset = to_addr - (from_addr + 5);
5429 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5430 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5431}
5432\f
5433/* Apply a fixup (fixS) to segment data, once it has been determined
5434 by our caller that we have all the info we need to fix it up.
5435
5436 On the 386, immediates, displacements, and data pointers are all in
5437 the same (little-endian) format, so we don't need to care about which
5438 we are handling. */
5439
94f592af 5440void
55cf6793 5441md_apply_fix (fixP, valP, seg)
47926f60
KH		 5442 /* The fix we're to put in. */
5443 fixS *fixP;
47926f60 5444 /* Pointer to the value of the bits. */
c6682705 5445 valueT *valP;
47926f60
KH		 5446 /* Segment fix is from. */
5447 segT seg ATTRIBUTE_UNUSED;
252b5132 5448{
94f592af 5449 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5450 valueT value = *valP;
252b5132 5451
f86103b7 5452#if !defined (TE_Mach)
93382f6d
AM		 5453 if (fixP->fx_pcrel)
5454 {
5455 switch (fixP->fx_r_type)
5456 {
5865bb77
ILT		 5457 default:
5458 break;
5459
d6ab8113
JB		 5460 case BFD_RELOC_64:
5461 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5462 break;
93382f6d 5463 case BFD_RELOC_32:
ae8887b5 5464 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5465 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5466 break;
5467 case BFD_RELOC_16:
5468 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5469 break;
5470 case BFD_RELOC_8:
5471 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5472 break;
5473 }
5474 }
252b5132 5475
a161fe53 5476 if (fixP->fx_addsy != NULL
31312f95 5477 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5478 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5479 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5480 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5481 && !use_rela_relocations)
252b5132 5482 {
31312f95
AM		 5483 /* This is a hack. There should be a better way to handle this.
5484 This covers for the fact that bfd_install_relocation will
5485 subtract the current location (for partial_inplace, PC relative
5486 relocations); see more below. */
252b5132 5487#ifndef OBJ_AOUT
718ddfc0 5488 if (IS_ELF
252b5132
RH		 5489#ifdef TE_PE
5490 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5491#endif
5492 )
5493 value += fixP->fx_where + fixP->fx_frag->fr_address;
5494#endif
5495#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5496 if (IS_ELF)
252b5132 5497 {
6539b54b 5498 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5499
6539b54b 5500 if ((sym_seg == seg
2f66722d 5501 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5502 && sym_seg != absolute_section))
ae6063d4 5503 && !generic_force_reloc (fixP))
2f66722d
AM		 5504 {
5505 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5506 bfd_install_relocation subtracts them out again. I think
5507 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5508 it. FIXME. */
5509 value += fixP->fx_where + fixP->fx_frag->fr_address;
5510 }
252b5132
RH		 5511 }
5512#endif
5513#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5514 /* For some reason, the PE format does not store a
5515 section address offset for a PC relative symbol. */
5516 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5517 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5518 value += md_pcrel_from (fixP);
5519#endif
5520 }
5521
5522 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5523 and we must not disappoint it. */
252b5132 5524#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5525 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5526 switch (fixP->fx_r_type)
5527 {
5528 case BFD_RELOC_386_PLT32:
3e73aa7c 5529 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5530 /* Make the jump instruction point to the address of the operand. At
5531 runtime we merely add the offset to the actual PLT entry. */
5532 value = -4;
5533 break;
31312f95 5534
13ae64f3
JJ		 5535 case BFD_RELOC_386_TLS_GD:
5536 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5537 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5538 case BFD_RELOC_386_TLS_IE:
5539 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5540 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5541 case BFD_RELOC_X86_64_TLSGD:
5542 case BFD_RELOC_X86_64_TLSLD:
5543 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5544 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5545 value = 0; /* Fully resolved at runtime. No addend. */
5546 /* Fallthrough */
5547 case BFD_RELOC_386_TLS_LE:
5548 case BFD_RELOC_386_TLS_LDO_32:
5549 case BFD_RELOC_386_TLS_LE_32:
5550 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5551 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5552 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5553 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5554 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5555 break;
5556
67a4f2b7
AO		 5557 case BFD_RELOC_386_TLS_DESC_CALL:
5558 case BFD_RELOC_X86_64_TLSDESC_CALL:
5559 value = 0; /* Fully resolved at runtime. No addend. */
5560 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5561 fixP->fx_done = 0;
5562 return;
5563
00f7efb6
JJ		 5564 case BFD_RELOC_386_GOT32:
5565 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5566 value = 0; /* Fully resolved at runtime. No addend. */
5567 break;
47926f60
KH		 5568
5569 case BFD_RELOC_VTABLE_INHERIT:
5570 case BFD_RELOC_VTABLE_ENTRY:
5571 fixP->fx_done = 0;
94f592af 5572 return;
47926f60
KH		 5573
5574 default:
5575 break;
5576 }
5577#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5578 *valP = value;
f86103b7 5579#endif /* !defined (TE_Mach) */
3e73aa7c 5580
3e73aa7c 5581 /* Are we finished with this relocation now? */
c6682705 5582 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5583 fixP->fx_done = 1;
5584 else if (use_rela_relocations)
5585 {
5586 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5587 /* Remember value for tc_gen_reloc. */
5588 fixP->fx_addnumber = value;
3e73aa7c
JH		 5589 value = 0;
5590 }
f86103b7 5591
94f592af 5592 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5593}
252b5132 5594\f
252b5132
RH		 5595#define MAX_LITTLENUMS 6
5596
47926f60
KH		 5597/* Turn the string pointed to by litP into a floating point constant
5598 of type TYPE, and emit the appropriate bytes. The number of
5599 LITTLENUMS emitted is stored in *SIZEP. An error message is
5600 returned, or NULL on OK. */
5601
252b5132
RH		 5602char *
5603md_atof (type, litP, sizeP)
2ab9b79e 5604 int type;
252b5132
RH		 5605 char *litP;
5606 int *sizeP;
5607{
5608 int prec;
5609 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5610 LITTLENUM_TYPE *wordP;
5611 char *t;
5612
5613 switch (type)
5614 {
5615 case 'f':
5616 case 'F':
5617 prec = 2;
5618 break;
5619
5620 case 'd':
5621 case 'D':
5622 prec = 4;
5623 break;
5624
5625 case 'x':
5626 case 'X':
5627 prec = 5;
5628 break;
5629
5630 default:
5631 *sizeP = 0;
5632 return _("Bad call to md_atof ()");
5633 }
5634 t = atof_ieee (input_line_pointer, type, words);
5635 if (t)
5636 input_line_pointer = t;
5637
5638 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5639 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5640 the bigendian 386. */
5641 for (wordP = words + prec - 1; prec--;)
5642 {
5643 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5644 litP += sizeof (LITTLENUM_TYPE);
5645 }
5646 return 0;
5647}
5648\f
2d545b82 5649static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5650
252b5132
RH		 5651static char *
5652output_invalid (c)
5653 int c;
5654{
3882b010 5655 if (ISPRINT (c))
f9f21a03
L		 5656 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5657 "'%c'", c);
252b5132 5658 else
f9f21a03 5659 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5660 "(0x%x)", (unsigned char) c);
252b5132
RH		 5661 return output_invalid_buf;
5662}
5663
af6bdddf 5664/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5665
5666static const reg_entry *
4d1bb795 5667parse_real_register (char *reg_string, char **end_op)
252b5132 5668{
af6bdddf
AM		 5669 char *s = reg_string;
5670 char *p;
252b5132
RH		 5671 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5672 const reg_entry *r;
5673
5674 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5675 if (*s == REGISTER_PREFIX)
5676 ++s;
5677
5678 if (is_space_char (*s))
5679 ++s;
5680
5681 p = reg_name_given;
af6bdddf 5682 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5683 {
5684 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5685 return (const reg_entry *) NULL;
5686 s++;
252b5132
RH		 5687 }
5688
6588847e
DN		 5689 /* For naked regs, make sure that we are not dealing with an identifier.
5690 This prevents confusing an identifier like `eax_var' with register
5691 `eax'. */
5692 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5693 return (const reg_entry *) NULL;
5694
af6bdddf 5695 *end_op = s;
252b5132
RH		 5696
5697 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5698
5f47d35b 5699 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5700 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5701 {
5f47d35b
AM		 5702 if (is_space_char (*s))
5703 ++s;
5704 if (*s == '(')
5705 {
af6bdddf 5706 ++s;
5f47d35b
AM		 5707 if (is_space_char (*s))
5708 ++s;
5709 if (*s >= '0' && *s <= '7')
5710 {
5711 r = &i386_float_regtab[*s - '0'];
af6bdddf 5712 ++s;
5f47d35b
AM		 5713 if (is_space_char (*s))
5714 ++s;
5715 if (*s == ')')
5716 {
5717 *end_op = s + 1;
5718 return r;
5719 }
5f47d35b 5720 }
47926f60 5721 /* We have "%st(" then garbage. */
5f47d35b
AM		 5722 return (const reg_entry *) NULL;
5723 }
5724 }
5725
1ae00879 5726 if (r != NULL
20f0a1fc 5727 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5728 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5729 && flag_code != CODE_64BIT)
20f0a1fc 5730 return (const reg_entry *) NULL;
1ae00879 5731
252b5132
RH		 5732 return r;
5733}
4d1bb795
JB		 5734
5735/* REG_STRING starts *before* REGISTER_PREFIX. */
5736
5737static const reg_entry *
5738parse_register (char *reg_string, char **end_op)
5739{
5740 const reg_entry *r;
5741
5742 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5743 r = parse_real_register (reg_string, end_op);
5744 else
5745 r = NULL;
5746 if (!r)
5747 {
5748 char *save = input_line_pointer;
5749 char c;
5750 symbolS *symbolP;
5751
5752 input_line_pointer = reg_string;
5753 c = get_symbol_end ();
5754 symbolP = symbol_find (reg_string);
5755 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5756 {
5757 const expressionS *e = symbol_get_value_expression (symbolP);
5758
5759 know (e->X_op == O_register);
5760 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5761 r = i386_regtab + e->X_add_number;
5762 *end_op = input_line_pointer;
5763 }
5764 *input_line_pointer = c;
5765 input_line_pointer = save;
5766 }
5767 return r;
5768}
5769
5770int
5771i386_parse_name (char *name, expressionS *e, char *nextcharP)
5772{
5773 const reg_entry *r;
5774 char *end = input_line_pointer;
5775
5776 *end = *nextcharP;
5777 r = parse_register (name, &input_line_pointer);
5778 if (r && end <= input_line_pointer)
5779 {
5780 *nextcharP = *input_line_pointer;
5781 *input_line_pointer = 0;
5782 e->X_op = O_register;
5783 e->X_add_number = r - i386_regtab;
5784 return 1;
5785 }
5786 input_line_pointer = end;
5787 *end = 0;
5788 return 0;
5789}
5790
5791void
5792md_operand (expressionS *e)
5793{
5794 if (*input_line_pointer == REGISTER_PREFIX)
5795 {
5796 char *end;
5797 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5798
5799 if (r)
5800 {
5801 e->X_op = O_register;
5802 e->X_add_number = r - i386_regtab;
5803 input_line_pointer = end;
5804 }
5805 }
5806}
5807
252b5132 5808\f
4cc782b5 5809#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5810const char *md_shortopts = "kVQ:sqn";
252b5132 5811#else
12b55ccc 5812const char *md_shortopts = "qn";
252b5132 5813#endif
6e0b89ee 5814
3e73aa7c 5815#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5816#define OPTION_64 (OPTION_MD_BASE + 1)
5817#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5818#define OPTION_MARCH (OPTION_MD_BASE + 3)
5819#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5820
99ad8390
NC		 5821struct option md_longopts[] =
5822{
3e73aa7c 5823 {"32", no_argument, NULL, OPTION_32},
99ad8390 5824#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5825 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5826#endif
b3b91714 5827 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5828 {"march", required_argument, NULL, OPTION_MARCH},
5829 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5830 {NULL, no_argument, NULL, 0}
5831};
5832size_t md_longopts_size = sizeof (md_longopts);
5833
5834int
9103f4f4 5835md_parse_option (int c, char *arg)
252b5132 5836{
9103f4f4
L		 5837 unsigned int i;
5838
252b5132
RH		 5839 switch (c)
5840 {
12b55ccc
L		 5841 case 'n':
5842 optimize_align_code = 0;
5843 break;
5844
a38cf1db
AM		 5845 case 'q':
5846 quiet_warnings = 1;
252b5132
RH		 5847 break;
5848
5849#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5850 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5851 should be emitted or not. FIXME: Not implemented. */
5852 case 'Q':
252b5132
RH		 5853 break;
5854
5855 /* -V: SVR4 argument to print version ID. */
5856 case 'V':
5857 print_version_id ();
5858 break;
5859
a38cf1db
AM		 5860 /* -k: Ignore for FreeBSD compatibility. */
5861 case 'k':
252b5132 5862 break;
4cc782b5
ILT		 5863
5864 case 's':
5865 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5866 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5867 break;
99ad8390
NC		 5868#endif
5869#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5870 case OPTION_64:
5871 {
5872 const char **list, **l;
5873
3e73aa7c
JH		 5874 list = bfd_target_list ();
5875 for (l = list; *l != NULL; l++)
99ad8390
NC		 5876 if ( strncmp (*l, "elf64-x86-64", 12) == 0
5877 || strcmp (*l, "coff-x86-64") == 0
5878 || strcmp (*l, "pe-x86-64") == 0
5879 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5880 {
5881 default_arch = "x86_64";
5882 break;
5883 }
3e73aa7c 5884 if (*l == NULL)
6e0b89ee 5885 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5886 free (list);
5887 }
5888 break;
5889#endif
252b5132 5890
6e0b89ee
AM		 5891 case OPTION_32:
5892 default_arch = "i386";
5893 break;
5894
b3b91714
AM		 5895 case OPTION_DIVIDE:
5896#ifdef SVR4_COMMENT_CHARS
5897 {
5898 char *n, *t;
5899 const char *s;
5900
5901 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5902 t = n;
5903 for (s = i386_comment_chars; *s != '\0'; s++)
5904 if (*s != '/')
5905 *t++ = *s;
5906 *t = '\0';
5907 i386_comment_chars = n;
5908 }
5909#endif
5910 break;
5911
9103f4f4
L		 5912 case OPTION_MARCH:
5913 if (*arg == '.')
5914 as_fatal (_("Invalid -march= option: `%s'"), arg);
5915 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5916 {
5917 if (strcmp (arg, cpu_arch [i].name) == 0)
5918 {
ccc9c027 5919 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5920 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5921 if (!cpu_arch_tune_set)
5922 {
5923 cpu_arch_tune = cpu_arch_isa;
5924 cpu_arch_tune_flags = cpu_arch_isa_flags;
5925 }
9103f4f4
L		 5926 break;
5927 }
5928 }
5929 if (i >= ARRAY_SIZE (cpu_arch))
5930 as_fatal (_("Invalid -march= option: `%s'"), arg);
5931 break;
5932
5933 case OPTION_MTUNE:
5934 if (*arg == '.')
5935 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5936 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5937 {
5938 if (strcmp (arg, cpu_arch [i].name) == 0)
5939 {
ccc9c027 5940 cpu_arch_tune_set = 1;
9103f4f4
L		 5941 cpu_arch_tune = cpu_arch [i].type;
5942 cpu_arch_tune_flags = cpu_arch[i].flags;
5943 break;
5944 }
5945 }
5946 if (i >= ARRAY_SIZE (cpu_arch))
5947 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5948 break;
5949
252b5132
RH		 5950 default:
5951 return 0;
5952 }
5953 return 1;
5954}
5955
5956void
5957md_show_usage (stream)
5958 FILE *stream;
5959{
4cc782b5
ILT		 5960#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5961 fprintf (stream, _("\
a38cf1db
AM		 5962 -Q ignored\n\
5963 -V print assembler version number\n\
b3b91714
AM		 5964 -k ignored\n"));
5965#endif
5966 fprintf (stream, _("\
12b55ccc 5967 -n Do not optimize code alignment\n\
b3b91714
AM		 5968 -q quieten some warnings\n"));
5969#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5970 fprintf (stream, _("\
a38cf1db 5971 -s ignored\n"));
b3b91714
AM		 5972#endif
5973#ifdef SVR4_COMMENT_CHARS
5974 fprintf (stream, _("\
5975 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5976#else
5977 fprintf (stream, _("\
b3b91714 5978 --divide ignored\n"));
4cc782b5 5979#endif
9103f4f4
L		 5980 fprintf (stream, _("\
5981 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5982 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5983 yonah, merom, k6, athlon, k8, generic32, generic64\n"));
5984
252b5132
RH		 5985}
5986
99ad8390
NC		 5987#if defined(TE_PEP)
5988const char *
5989x86_64_target_format (void)
5990{
5991 if (strcmp (default_arch, "x86_64") == 0)
5992 {
5993 set_code_flag (CODE_64BIT);
5994 return COFF_TARGET_FORMAT;
5995 }
5996 else if (strcmp (default_arch, "i386") == 0)
5997 {
5998 set_code_flag (CODE_32BIT);
5999 return "coff-i386";
6000 }
6001
6002 as_fatal (_("Unknown architecture"));
6003 return NULL;
6004}
6005#endif
6006
3e73aa7c
JH		 6007#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6008 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6009
6010/* Pick the target format to use. */
6011
47926f60 6012const char *
252b5132
RH		 6013i386_target_format ()
6014{
3e73aa7c 6015 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6016 {
6017 set_code_flag (CODE_64BIT);
6018 if (cpu_arch_isa_flags == 0)
d32cad65 6019 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6020 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6021 |CpuSSE|CpuSSE2;
ccc9c027 6022 if (cpu_arch_tune_flags == 0)
d32cad65 6023 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6024 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6025 |CpuSSE|CpuSSE2;
9103f4f4 6026 }
3e73aa7c 6027 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6028 {
6029 set_code_flag (CODE_32BIT);
6030 if (cpu_arch_isa_flags == 0)
d32cad65 6031 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6032 if (cpu_arch_tune_flags == 0)
d32cad65 6033 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6034 }
3e73aa7c
JH		 6035 else
6036 as_fatal (_("Unknown architecture"));
252b5132
RH		 6037 switch (OUTPUT_FLAVOR)
6038 {
4c63da97
AM		 6039#ifdef OBJ_MAYBE_AOUT
6040 case bfd_target_aout_flavour:
47926f60 6041 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6042#endif
6043#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6044 case bfd_target_coff_flavour:
6045 return "coff-i386";
4c63da97 6046#endif
3e73aa7c 6047#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6048 case bfd_target_elf_flavour:
3e73aa7c 6049 {
e5cb08ac 6050 if (flag_code == CODE_64BIT)
4fa24527
JB		 6051 {
6052 object_64bit = 1;
6053 use_rela_relocations = 1;
6054 }
9d7cbccd 6055 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6056 }
4c63da97 6057#endif
252b5132
RH		 6058 default:
6059 abort ();
6060 return NULL;
6061 }
6062}
6063
47926f60 6064#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6065
6066#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6067void i386_elf_emit_arch_note ()
6068{
718ddfc0 6069 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6070 {
6071 char *p;
6072 asection *seg = now_seg;
6073 subsegT subseg = now_subseg;
6074 Elf_Internal_Note i_note;
6075 Elf_External_Note e_note;
6076 asection *note_secp;
6077 int len;
6078
6079 /* Create the .note section. */
6080 note_secp = subseg_new (".note", 0);
6081 bfd_set_section_flags (stdoutput,
6082 note_secp,
6083 SEC_HAS_CONTENTS | SEC_READONLY);
6084
6085 /* Process the arch string. */
6086 len = strlen (cpu_arch_name);
6087
6088 i_note.namesz = len + 1;
6089 i_note.descsz = 0;
6090 i_note.type = NT_ARCH;
6091 p = frag_more (sizeof (e_note.namesz));
6092 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6093 p = frag_more (sizeof (e_note.descsz));
6094 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6095 p = frag_more (sizeof (e_note.type));
6096 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6097 p = frag_more (len + 1);
6098 strcpy (p, cpu_arch_name);
6099
6100 frag_align (2, 0, 0);
6101
6102 subseg_set (seg, subseg);
6103 }
6104}
6105#endif
252b5132 6106\f
252b5132
RH		 6107symbolS *
6108md_undefined_symbol (name)
6109 char *name;
6110{
18dc2407
ILT		 6111 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6112 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6113 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6114 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6115 {
6116 if (!GOT_symbol)
6117 {
6118 if (symbol_find (name))
6119 as_bad (_("GOT already in symbol table"));
6120 GOT_symbol = symbol_new (name, undefined_section,
6121 (valueT) 0, &zero_address_frag);
6122 };
6123 return GOT_symbol;
6124 }
252b5132
RH		 6125 return 0;
6126}
6127
6128/* Round up a section size to the appropriate boundary. */
47926f60 6129
252b5132
RH		 6130valueT
6131md_section_align (segment, size)
ab9da554 6132 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6133 valueT size;
6134{
4c63da97
AM		 6135#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6136 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6137 {
6138 /* For a.out, force the section size to be aligned. If we don't do
6139 this, BFD will align it for us, but it will not write out the
6140 final bytes of the section. This may be a bug in BFD, but it is
6141 easier to fix it here since that is how the other a.out targets
6142 work. */
6143 int align;
6144
6145 align = bfd_get_section_alignment (stdoutput, segment);
6146 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6147 }
252b5132
RH		 6148#endif
6149
6150 return size;
6151}
6152
6153/* On the i386, PC-relative offsets are relative to the start of the
6154 next instruction. That is, the address of the offset, plus its
6155 size, since the offset is always the last part of the insn. */
6156
6157long
6158md_pcrel_from (fixP)
6159 fixS *fixP;
6160{
6161 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6162}
6163
6164#ifndef I386COFF
6165
6166static void
6167s_bss (ignore)
ab9da554 6168 int ignore ATTRIBUTE_UNUSED;
252b5132 6169{
29b0f896 6170 int temp;
252b5132 6171
8a75718c
JB		 6172#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6173 if (IS_ELF)
6174 obj_elf_section_change_hook ();
6175#endif
252b5132
RH		 6176 temp = get_absolute_expression ();
6177 subseg_set (bss_section, (subsegT) temp);
6178 demand_empty_rest_of_line ();
6179}
6180
6181#endif
6182
252b5132
RH		 6183void
6184i386_validate_fix (fixp)
6185 fixS *fixp;
6186{
6187 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6188 {
23df1078
JH		 6189 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6190 {
4fa24527 6191 if (!object_64bit)
23df1078
JH		 6192 abort ();
6193 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6194 }
6195 else
6196 {
4fa24527 6197 if (!object_64bit)
d6ab8113
JB		 6198 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6199 else
6200 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6201 }
252b5132
RH		 6202 fixp->fx_subsy = 0;
6203 }
6204}
6205
252b5132
RH		 6206arelent *
6207tc_gen_reloc (section, fixp)
ab9da554 6208 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6209 fixS *fixp;
6210{
6211 arelent *rel;
6212 bfd_reloc_code_real_type code;
6213
6214 switch (fixp->fx_r_type)
6215 {
3e73aa7c
JH		 6216 case BFD_RELOC_X86_64_PLT32:
6217 case BFD_RELOC_X86_64_GOT32:
6218 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6219 case BFD_RELOC_386_PLT32:
6220 case BFD_RELOC_386_GOT32:
6221 case BFD_RELOC_386_GOTOFF:
6222 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6223 case BFD_RELOC_386_TLS_GD:
6224 case BFD_RELOC_386_TLS_LDM:
6225 case BFD_RELOC_386_TLS_LDO_32:
6226 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6227 case BFD_RELOC_386_TLS_IE:
6228 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6229 case BFD_RELOC_386_TLS_LE_32:
6230 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6231 case BFD_RELOC_386_TLS_GOTDESC:
6232 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6233 case BFD_RELOC_X86_64_TLSGD:
6234 case BFD_RELOC_X86_64_TLSLD:
6235 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6236 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6237 case BFD_RELOC_X86_64_GOTTPOFF:
6238 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6239 case BFD_RELOC_X86_64_TPOFF64:
6240 case BFD_RELOC_X86_64_GOTOFF64:
6241 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6242 case BFD_RELOC_X86_64_GOT64:
6243 case BFD_RELOC_X86_64_GOTPCREL64:
6244 case BFD_RELOC_X86_64_GOTPC64:
6245 case BFD_RELOC_X86_64_GOTPLT64:
6246 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6247 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6248 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6249 case BFD_RELOC_RVA:
6250 case BFD_RELOC_VTABLE_ENTRY:
6251 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6252#ifdef TE_PE
6253 case BFD_RELOC_32_SECREL:
6254#endif
252b5132
RH		 6255 code = fixp->fx_r_type;
6256 break;
dbbaec26
L		 6257 case BFD_RELOC_X86_64_32S:
6258 if (!fixp->fx_pcrel)
6259 {
6260 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6261 code = fixp->fx_r_type;
6262 break;
6263 }
252b5132 6264 default:
93382f6d 6265 if (fixp->fx_pcrel)
252b5132 6266 {
93382f6d
AM		 6267 switch (fixp->fx_size)
6268 {
6269 default:
b091f402
AM		 6270 as_bad_where (fixp->fx_file, fixp->fx_line,
6271 _("can not do %d byte pc-relative relocation"),
6272 fixp->fx_size);
93382f6d
AM		 6273 code = BFD_RELOC_32_PCREL;
6274 break;
6275 case 1: code = BFD_RELOC_8_PCREL; break;
6276 case 2: code = BFD_RELOC_16_PCREL; break;
6277 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6278#ifdef BFD64
6279 case 8: code = BFD_RELOC_64_PCREL; break;
6280#endif
93382f6d
AM		 6281 }
6282 }
6283 else
6284 {
6285 switch (fixp->fx_size)
6286 {
6287 default:
b091f402
AM		 6288 as_bad_where (fixp->fx_file, fixp->fx_line,
6289 _("can not do %d byte relocation"),
6290 fixp->fx_size);
93382f6d
AM		 6291 code = BFD_RELOC_32;
6292 break;
6293 case 1: code = BFD_RELOC_8; break;
6294 case 2: code = BFD_RELOC_16; break;
6295 case 4: code = BFD_RELOC_32; break;
937149dd 6296#ifdef BFD64
3e73aa7c 6297 case 8: code = BFD_RELOC_64; break;
937149dd 6298#endif
93382f6d 6299 }
252b5132
RH		 6300 }
6301 break;
6302 }
252b5132 6303
d182319b
JB		 6304 if ((code == BFD_RELOC_32
6305 || code == BFD_RELOC_32_PCREL
6306 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6307 && GOT_symbol
6308 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6309 {
4fa24527 6310 if (!object_64bit)
d6ab8113
JB		 6311 code = BFD_RELOC_386_GOTPC;
6312 else
6313 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6314 }
7b81dfbb
AJ		 6315 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6316 && GOT_symbol
6317 && fixp->fx_addsy == GOT_symbol)
6318 {
6319 code = BFD_RELOC_X86_64_GOTPC64;
6320 }
252b5132
RH		 6321
6322 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6323 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6324 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6325
6326 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6327
3e73aa7c
JH		 6328 if (!use_rela_relocations)
6329 {
6330 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6331 vtable entry to be used in the relocation's section offset. */
6332 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6333 rel->address = fixp->fx_offset;
252b5132 6334
c6682705 6335 rel->addend = 0;
3e73aa7c
JH		 6336 }
6337 /* Use the rela in 64bit mode. */
252b5132 6338 else
3e73aa7c 6339 {
062cd5e7
AS		 6340 if (!fixp->fx_pcrel)
6341 rel->addend = fixp->fx_offset;
6342 else
6343 switch (code)
6344 {
6345 case BFD_RELOC_X86_64_PLT32:
6346 case BFD_RELOC_X86_64_GOT32:
6347 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6348 case BFD_RELOC_X86_64_TLSGD:
6349 case BFD_RELOC_X86_64_TLSLD:
6350 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6351 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6352 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6353 rel->addend = fixp->fx_offset - fixp->fx_size;
6354 break;
6355 default:
6356 rel->addend = (section->vma
6357 - fixp->fx_size
6358 + fixp->fx_addnumber
6359 + md_pcrel_from (fixp));
6360 break;
6361 }
3e73aa7c
JH		 6362 }
6363
252b5132
RH		 6364 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6365 if (rel->howto == NULL)
6366 {
6367 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6368 _("cannot represent relocation type %s"),
252b5132
RH		 6369 bfd_get_reloc_code_name (code));
6370 /* Set howto to a garbage value so that we can keep going. */
6371 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6372 assert (rel->howto != NULL);
6373 }
6374
6375 return rel;
6376}
6377
64a0c779
DN		 6378\f
6379/* Parse operands using Intel syntax. This implements a recursive descent
6380 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6381 Programmer's Guide.
6382
6383 FIXME: We do not recognize the full operand grammar defined in the MASM
6384 documentation. In particular, all the structure/union and
6385 high-level macro operands are missing.
6386
6387 Uppercase words are terminals, lower case words are non-terminals.
6388 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6389 bars '|' denote choices. Most grammar productions are implemented in
6390 functions called 'intel_<production>'.
6391
6392 Initial production is 'expr'.
6393
9306ca4a 6394 addOp + | -
64a0c779
DN		 6395
6396 alpha [a-zA-Z]
6397
9306ca4a
JB		 6398 binOp & | AND | \| | OR | ^ | XOR
6399
64a0c779
DN		 6400 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6401
6402 constant digits [[ radixOverride ]]
6403
9306ca4a 6404 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6405
6406 digits decdigit
b77a7acd
AJ		 6407 | digits decdigit
6408 | digits hexdigit
64a0c779
DN		 6409
6410 decdigit [0-9]
6411
9306ca4a
JB		 6412 e04 e04 addOp e05
6413 | e05
6414
6415 e05 e05 binOp e06
b77a7acd 6416 | e06
64a0c779
DN		 6417
6418 e06 e06 mulOp e09
b77a7acd 6419 | e09
64a0c779
DN		 6420
6421 e09 OFFSET e10
a724f0f4
JB		 6422 | SHORT e10
6423 | + e10
6424 | - e10
9306ca4a
JB		 6425 | ~ e10
6426 | NOT e10
64a0c779
DN		 6427 | e09 PTR e10
6428 | e09 : e10
6429 | e10
6430
6431 e10 e10 [ expr ]
b77a7acd 6432 | e11
64a0c779
DN		 6433
6434 e11 ( expr )
b77a7acd 6435 | [ expr ]
64a0c779
DN		 6436 | constant
6437 | dataType
6438 | id
6439 | $
6440 | register
6441
a724f0f4 6442 => expr expr cmpOp e04
9306ca4a 6443 | e04
64a0c779
DN		 6444
6445 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6446 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6447
6448 hexdigit a | b | c | d | e | f
b77a7acd 6449 | A | B | C | D | E | F
64a0c779
DN		 6450
6451 id alpha
b77a7acd 6452 | id alpha
64a0c779
DN		 6453 | id decdigit
6454
9306ca4a 6455 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6456
6457 quote " | '
6458
6459 register specialRegister
b77a7acd 6460 | gpRegister
64a0c779
DN		 6461 | byteRegister
6462
6463 segmentRegister CS | DS | ES | FS | GS | SS
6464
9306ca4a 6465 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6466 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6467 | TR3 | TR4 | TR5 | TR6 | TR7
6468
64a0c779
DN		 6469 We simplify the grammar in obvious places (e.g., register parsing is
6470 done by calling parse_register) and eliminate immediate left recursion
6471 to implement a recursive-descent parser.
6472
a724f0f4
JB		 6473 expr e04 expr'
6474
6475 expr' cmpOp e04 expr'
6476 | Empty
9306ca4a
JB		 6477
6478 e04 e05 e04'
6479
6480 e04' addOp e05 e04'
6481 | Empty
64a0c779
DN		 6482
6483 e05 e06 e05'
6484
9306ca4a 6485 e05' binOp e06 e05'
b77a7acd 6486 | Empty
64a0c779
DN		 6487
6488 e06 e09 e06'
6489
6490 e06' mulOp e09 e06'
b77a7acd 6491 | Empty
64a0c779
DN		 6492
6493 e09 OFFSET e10 e09'
a724f0f4
JB		 6494 | SHORT e10'
6495 | + e10'
6496 | - e10'
6497 | ~ e10'
6498 | NOT e10'
b77a7acd 6499 | e10 e09'
64a0c779
DN		 6500
6501 e09' PTR e10 e09'
b77a7acd 6502 | : e10 e09'
64a0c779
DN		 6503 | Empty
6504
6505 e10 e11 e10'
6506
6507 e10' [ expr ] e10'
b77a7acd 6508 | Empty
64a0c779
DN		 6509
6510 e11 ( expr )
b77a7acd 6511 | [ expr ]
64a0c779
DN		 6512 | BYTE
6513 | WORD
6514 | DWORD
9306ca4a 6515 | FWORD
64a0c779 6516 | QWORD
9306ca4a
JB		 6517 | TBYTE
6518 | OWORD
6519 | XMMWORD
64a0c779
DN		 6520 | .
6521 | $
6522 | register
6523 | id
6524 | constant */
6525
6526/* Parsing structure for the intel syntax parser. Used to implement the
6527 semantic actions for the operand grammar. */
6528struct intel_parser_s
6529 {
6530 char *op_string; /* The string being parsed. */
6531 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6532 int op_modifier; /* Operand modifier. */
64a0c779 6533 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6534 int in_offset; /* >=1 if parsing operand of offset. */
6535 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6536 const reg_entry *reg; /* Last register reference found. */
6537 char *disp; /* Displacement string being built. */
a724f0f4 6538 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6539 };
6540
6541static struct intel_parser_s intel_parser;
6542
6543/* Token structure for parsing intel syntax. */
6544struct intel_token
6545 {
6546 int code; /* Token code. */
6547 const reg_entry *reg; /* Register entry for register tokens. */
6548 char *str; /* String representation. */
6549 };
6550
6551static struct intel_token cur_token, prev_token;
6552
50705ef4
AM		 6553/* Token codes for the intel parser. Since T_SHORT is already used
6554 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6555#define T_NIL -1
6556#define T_CONST 1
6557#define T_REG 2
6558#define T_BYTE 3
6559#define T_WORD 4
9306ca4a
JB		 6560#define T_DWORD 5
6561#define T_FWORD 6
6562#define T_QWORD 7
6563#define T_TBYTE 8
6564#define T_XMMWORD 9
50705ef4 6565#undef T_SHORT
9306ca4a
JB		 6566#define T_SHORT 10
6567#define T_OFFSET 11
6568#define T_PTR 12
6569#define T_ID 13
6570#define T_SHL 14
6571#define T_SHR 15
64a0c779
DN		 6572
6573/* Prototypes for intel parser functions. */
6574static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6575static void intel_get_token PARAMS ((void));
6576static void intel_putback_token PARAMS ((void));
6577static int intel_expr PARAMS ((void));
9306ca4a 6578static int intel_e04 PARAMS ((void));
cce0cbdc 6579static int intel_e05 PARAMS ((void));
cce0cbdc 6580static int intel_e06 PARAMS ((void));
cce0cbdc 6581static int intel_e09 PARAMS ((void));
a724f0f4 6582static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6583static int intel_e10 PARAMS ((void));
cce0cbdc 6584static int intel_e11 PARAMS ((void));
64a0c779 6585
64a0c779
DN		 6586static int
6587i386_intel_operand (operand_string, got_a_float)
6588 char *operand_string;
6589 int got_a_float;
6590{
6591 int ret;
6592 char *p;
6593
a724f0f4
JB		 6594 p = intel_parser.op_string = xstrdup (operand_string);
6595 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6596
6597 for (;;)
64a0c779 6598 {
a724f0f4
JB		 6599 /* Initialize token holders. */
6600 cur_token.code = prev_token.code = T_NIL;
6601 cur_token.reg = prev_token.reg = NULL;
6602 cur_token.str = prev_token.str = NULL;
6603
6604 /* Initialize parser structure. */
6605 intel_parser.got_a_float = got_a_float;
6606 intel_parser.op_modifier = 0;
6607 intel_parser.is_mem = 0;
6608 intel_parser.in_offset = 0;
6609 intel_parser.in_bracket = 0;
6610 intel_parser.reg = NULL;
6611 intel_parser.disp[0] = '\0';
6612 intel_parser.next_operand = NULL;
6613
6614 /* Read the first token and start the parser. */
6615 intel_get_token ();
6616 ret = intel_expr ();
6617
6618 if (!ret)
6619 break;
6620
9306ca4a
JB		 6621 if (cur_token.code != T_NIL)
6622 {
6623 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6624 current_templates->start->name, cur_token.str);
6625 ret = 0;
6626 }
64a0c779
DN		 6627 /* If we found a memory reference, hand it over to i386_displacement
6628 to fill in the rest of the operand fields. */
9306ca4a 6629 else if (intel_parser.is_mem)
64a0c779
DN		 6630 {
6631 if ((i.mem_operands == 1
6632 && (current_templates->start->opcode_modifier & IsString) == 0)
6633 || i.mem_operands == 2)
6634 {
6635 as_bad (_("too many memory references for '%s'"),
6636 current_templates->start->name);
6637 ret = 0;
6638 }
6639 else
6640 {
6641 char *s = intel_parser.disp;
6642 i.mem_operands++;
6643
a724f0f4
JB		 6644 if (!quiet_warnings && intel_parser.is_mem < 0)
6645 /* See the comments in intel_bracket_expr. */
6646 as_warn (_("Treating `%s' as memory reference"), operand_string);
6647
64a0c779
DN		 6648 /* Add the displacement expression. */
6649 if (*s != '\0')
a4622f40
AM		 6650 ret = i386_displacement (s, s + strlen (s));
6651 if (ret)
a724f0f4
JB		 6652 {
6653 /* Swap base and index in 16-bit memory operands like
6654 [si+bx]. Since i386_index_check is also used in AT&T
6655 mode we have to do that here. */
6656 if (i.base_reg
6657 && i.index_reg
6658 && (i.base_reg->reg_type & Reg16)
6659 && (i.index_reg->reg_type & Reg16)
6660 && i.base_reg->reg_num >= 6
6661 && i.index_reg->reg_num < 6)
6662 {
6663 const reg_entry *base = i.index_reg;
6664
6665 i.index_reg = i.base_reg;
6666 i.base_reg = base;
6667 }
6668 ret = i386_index_check (operand_string);
6669 }
64a0c779
DN		 6670 }
6671 }
6672
6673 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6674 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6675 || intel_parser.reg == NULL)
6676 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6677
6678 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6679 ret = 0;
6680 if (!ret || !intel_parser.next_operand)
6681 break;
6682 intel_parser.op_string = intel_parser.next_operand;
6683 this_operand = i.operands++;
64a0c779
DN		 6684 }
6685
6686 free (p);
6687 free (intel_parser.disp);
6688
6689 return ret;
6690}
6691
a724f0f4
JB		 6692#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6693
6694/* expr e04 expr'
6695
6696 expr' cmpOp e04 expr'
6697 | Empty */
64a0c779
DN		 6698static int
6699intel_expr ()
6700{
a724f0f4
JB		 6701 /* XXX Implement the comparison operators. */
6702 return intel_e04 ();
9306ca4a
JB		 6703}
6704
a724f0f4 6705/* e04 e05 e04'
9306ca4a 6706
a724f0f4 6707 e04' addOp e05 e04'
9306ca4a
JB		 6708 | Empty */
6709static int
6710intel_e04 ()
6711{
a724f0f4 6712 int nregs = -1;
9306ca4a 6713
a724f0f4 6714 for (;;)
9306ca4a 6715 {
a724f0f4
JB		 6716 if (!intel_e05())
6717 return 0;
9306ca4a 6718
a724f0f4
JB		 6719 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6720 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6721
a724f0f4
JB		 6722 if (cur_token.code == '+')
6723 nregs = -1;
6724 else if (cur_token.code == '-')
6725 nregs = NUM_ADDRESS_REGS;
6726 else
6727 return 1;
64a0c779 6728
a724f0f4
JB		 6729 strcat (intel_parser.disp, cur_token.str);
6730 intel_match_token (cur_token.code);
6731 }
64a0c779
DN		 6732}
6733
64a0c779
DN		 6734/* e05 e06 e05'
6735
9306ca4a 6736 e05' binOp e06 e05'
64a0c779
DN		 6737 | Empty */
6738static int
6739intel_e05 ()
6740{
a724f0f4 6741 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6742
a724f0f4 6743 for (;;)
64a0c779 6744 {
a724f0f4
JB		 6745 if (!intel_e06())
6746 return 0;
6747
6748 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6749 {
6750 char str[2];
6751
6752 str[0] = cur_token.code;
6753 str[1] = 0;
6754 strcat (intel_parser.disp, str);
6755 }
6756 else
6757 break;
9306ca4a 6758
64a0c779
DN		 6759 intel_match_token (cur_token.code);
6760
a724f0f4
JB		 6761 if (nregs < 0)
6762 nregs = ~nregs;
64a0c779 6763 }
a724f0f4
JB		 6764 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6765 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6766 return 1;
4a1805b1 6767}
64a0c779
DN		 6768
6769/* e06 e09 e06'
6770
6771 e06' mulOp e09 e06'
b77a7acd 6772 | Empty */
64a0c779
DN		 6773static int
6774intel_e06 ()
6775{
a724f0f4 6776 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6777
a724f0f4 6778 for (;;)
64a0c779 6779 {
a724f0f4
JB		 6780 if (!intel_e09())
6781 return 0;
9306ca4a 6782
a724f0f4
JB		 6783 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6784 {
6785 char str[2];
9306ca4a 6786
a724f0f4
JB		 6787 str[0] = cur_token.code;
6788 str[1] = 0;
6789 strcat (intel_parser.disp, str);
6790 }
6791 else if (cur_token.code == T_SHL)
6792 strcat (intel_parser.disp, "<<");
6793 else if (cur_token.code == T_SHR)
6794 strcat (intel_parser.disp, ">>");
6795 else
6796 break;
9306ca4a 6797
64e74474 6798 intel_match_token (cur_token.code);
64a0c779 6799
a724f0f4
JB		 6800 if (nregs < 0)
6801 nregs = ~nregs;
64a0c779 6802 }
a724f0f4
JB		 6803 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6804 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6805 return 1;
64a0c779
DN		 6806}
6807
a724f0f4
JB		 6808/* e09 OFFSET e09
6809 | SHORT e09
6810 | + e09
6811 | - e09
6812 | ~ e09
6813 | NOT e09
9306ca4a
JB		 6814 | e10 e09'
6815
64a0c779 6816 e09' PTR e10 e09'
b77a7acd 6817 | : e10 e09'
64a0c779
DN		 6818 | Empty */
6819static int
6820intel_e09 ()
6821{
a724f0f4
JB		 6822 int nregs = ~NUM_ADDRESS_REGS;
6823 int in_offset = 0;
6824
6825 for (;;)
64a0c779 6826 {
a724f0f4
JB		 6827 /* Don't consume constants here. */
6828 if (cur_token.code == '+' || cur_token.code == '-')
6829 {
6830 /* Need to look one token ahead - if the next token
6831 is a constant, the current token is its sign. */
6832 int next_code;
6833
6834 intel_match_token (cur_token.code);
6835 next_code = cur_token.code;
6836 intel_putback_token ();
6837 if (next_code == T_CONST)
6838 break;
6839 }
6840
6841 /* e09 OFFSET e09 */
6842 if (cur_token.code == T_OFFSET)
6843 {
6844 if (!in_offset++)
6845 ++intel_parser.in_offset;
6846 }
6847
6848 /* e09 SHORT e09 */
6849 else if (cur_token.code == T_SHORT)
6850 intel_parser.op_modifier |= 1 << T_SHORT;
6851
6852 /* e09 + e09 */
6853 else if (cur_token.code == '+')
6854 strcat (intel_parser.disp, "+");
6855
6856 /* e09 - e09
6857 | ~ e09
6858 | NOT e09 */
6859 else if (cur_token.code == '-' || cur_token.code == '~')
6860 {
6861 char str[2];
64a0c779 6862
a724f0f4
JB		 6863 if (nregs < 0)
6864 nregs = ~nregs;
6865 str[0] = cur_token.code;
6866 str[1] = 0;
6867 strcat (intel_parser.disp, str);
6868 }
6869
6870 /* e09 e10 e09' */
6871 else
6872 break;
6873
6874 intel_match_token (cur_token.code);
64a0c779
DN		 6875 }
6876
a724f0f4 6877 for (;;)
9306ca4a 6878 {
a724f0f4
JB		 6879 if (!intel_e10 ())
6880 return 0;
9306ca4a 6881
a724f0f4
JB		 6882 /* e09' PTR e10 e09' */
6883 if (cur_token.code == T_PTR)
6884 {
6885 char suffix;
9306ca4a 6886
a724f0f4
JB		 6887 if (prev_token.code == T_BYTE)
6888 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6889
a724f0f4
JB		 6890 else if (prev_token.code == T_WORD)
6891 {
6892 if (current_templates->start->name[0] == 'l'
6893 && current_templates->start->name[2] == 's'
6894 && current_templates->start->name[3] == 0)
6895 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6896 else if (intel_parser.got_a_float == 2) /* "fi..." */
6897 suffix = SHORT_MNEM_SUFFIX;
6898 else
6899 suffix = WORD_MNEM_SUFFIX;
6900 }
64a0c779 6901
a724f0f4
JB		 6902 else if (prev_token.code == T_DWORD)
6903 {
6904 if (current_templates->start->name[0] == 'l'
6905 && current_templates->start->name[2] == 's'
6906 && current_templates->start->name[3] == 0)
6907 suffix = WORD_MNEM_SUFFIX;
6908 else if (flag_code == CODE_16BIT
6909 && (current_templates->start->opcode_modifier
435acd52 6910 & (Jump | JumpDword)))
a724f0f4
JB		 6911 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6912 else if (intel_parser.got_a_float == 1) /* "f..." */
6913 suffix = SHORT_MNEM_SUFFIX;
6914 else
6915 suffix = LONG_MNEM_SUFFIX;
6916 }
9306ca4a 6917
a724f0f4
JB		 6918 else if (prev_token.code == T_FWORD)
6919 {
6920 if (current_templates->start->name[0] == 'l'
6921 && current_templates->start->name[2] == 's'
6922 && current_templates->start->name[3] == 0)
6923 suffix = LONG_MNEM_SUFFIX;
6924 else if (!intel_parser.got_a_float)
6925 {
6926 if (flag_code == CODE_16BIT)
6927 add_prefix (DATA_PREFIX_OPCODE);
6928 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6929 }
6930 else
6931 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6932 }
64a0c779 6933
a724f0f4
JB		 6934 else if (prev_token.code == T_QWORD)
6935 {
6936 if (intel_parser.got_a_float == 1) /* "f..." */
6937 suffix = LONG_MNEM_SUFFIX;
6938 else
6939 suffix = QWORD_MNEM_SUFFIX;
6940 }
64a0c779 6941
a724f0f4
JB		 6942 else if (prev_token.code == T_TBYTE)
6943 {
6944 if (intel_parser.got_a_float == 1)
6945 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6946 else
6947 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6948 }
9306ca4a 6949
a724f0f4 6950 else if (prev_token.code == T_XMMWORD)
9306ca4a 6951 {
a724f0f4
JB		 6952 /* XXX ignored for now, but accepted since gcc uses it */
6953 suffix = 0;
9306ca4a 6954 }
64a0c779 6955
f16b83df 6956 else
a724f0f4
JB		 6957 {
6958 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6959 return 0;
6960 }
6961
435acd52
JB		 6962 /* Operands for jump/call using 'ptr' notation denote absolute
6963 addresses. */
6964 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6965 i.types[this_operand] |= JumpAbsolute;
6966
a724f0f4
JB		 6967 if (current_templates->start->base_opcode == 0x8d /* lea */)
6968 ;
6969 else if (!i.suffix)
6970 i.suffix = suffix;
6971 else if (i.suffix != suffix)
6972 {
6973 as_bad (_("Conflicting operand modifiers"));
6974 return 0;
6975 }
64a0c779 6976
9306ca4a
JB		 6977 }
6978
a724f0f4
JB		 6979 /* e09' : e10 e09' */
6980 else if (cur_token.code == ':')
9306ca4a 6981 {
a724f0f4
JB		 6982 if (prev_token.code != T_REG)
6983 {
6984 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6985 segment/group identifier (which we don't have), using comma
6986 as the operand separator there is even less consistent, since
6987 there all branches only have a single operand. */
6988 if (this_operand != 0
6989 || intel_parser.in_offset
6990 || intel_parser.in_bracket
6991 || (!(current_templates->start->opcode_modifier
6992 & (Jump|JumpDword|JumpInterSegment))
6993 && !(current_templates->start->operand_types[0]
6994 & JumpAbsolute)))
6995 return intel_match_token (T_NIL);
6996 /* Remember the start of the 2nd operand and terminate 1st
6997 operand here.
6998 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6999 another expression), but it gets at least the simplest case
7000 (a plain number or symbol on the left side) right. */
7001 intel_parser.next_operand = intel_parser.op_string;
7002 *--intel_parser.op_string = '\0';
7003 return intel_match_token (':');
7004 }
9306ca4a 7005 }
64a0c779 7006
a724f0f4 7007 /* e09' Empty */
64a0c779 7008 else
a724f0f4 7009 break;
64a0c779 7010
a724f0f4
JB		 7011 intel_match_token (cur_token.code);
7012
7013 }
7014
7015 if (in_offset)
7016 {
7017 --intel_parser.in_offset;
7018 if (nregs < 0)
7019 nregs = ~nregs;
7020 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7021 {
a724f0f4 7022 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7023 return 0;
7024 }
a724f0f4
JB		 7025 intel_parser.op_modifier |= 1 << T_OFFSET;
7026 }
9306ca4a 7027
a724f0f4
JB		 7028 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7029 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7030 return 1;
7031}
64a0c779 7032
a724f0f4
JB		 7033static int
7034intel_bracket_expr ()
7035{
7036 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7037 const char *start = intel_parser.op_string;
7038 int len;
7039
7040 if (i.op[this_operand].regs)
7041 return intel_match_token (T_NIL);
7042
7043 intel_match_token ('[');
7044
7045 /* Mark as a memory operand only if it's not already known to be an
7046 offset expression. If it's an offset expression, we need to keep
7047 the brace in. */
7048 if (!intel_parser.in_offset)
7049 {
7050 ++intel_parser.in_bracket;
435acd52
JB		 7051
7052 /* Operands for jump/call inside brackets denote absolute addresses. */
7053 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7054 i.types[this_operand] |= JumpAbsolute;
7055
a724f0f4
JB		 7056 /* Unfortunately gas always diverged from MASM in a respect that can't
7057 be easily fixed without risking to break code sequences likely to be
7058 encountered (the testsuite even check for this): MASM doesn't consider
7059 an expression inside brackets unconditionally as a memory reference.
7060 When that is e.g. a constant, an offset expression, or the sum of the
7061 two, this is still taken as a constant load. gas, however, always
7062 treated these as memory references. As a compromise, we'll try to make
7063 offset expressions inside brackets work the MASM way (since that's
7064 less likely to be found in real world code), but make constants alone
7065 continue to work the traditional gas way. In either case, issue a
7066 warning. */
7067 intel_parser.op_modifier &= ~was_offset;
64a0c779 7068 }
a724f0f4 7069 else
64e74474 7070 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7071
7072 /* Add a '+' to the displacement string if necessary. */
7073 if (*intel_parser.disp != '\0'
7074 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7075 strcat (intel_parser.disp, "+");
64a0c779 7076
a724f0f4
JB		 7077 if (intel_expr ()
7078 && (len = intel_parser.op_string - start - 1,
7079 intel_match_token (']')))
64a0c779 7080 {
a724f0f4
JB		 7081 /* Preserve brackets when the operand is an offset expression. */
7082 if (intel_parser.in_offset)
7083 strcat (intel_parser.disp, "]");
7084 else
7085 {
7086 --intel_parser.in_bracket;
7087 if (i.base_reg || i.index_reg)
7088 intel_parser.is_mem = 1;
7089 if (!intel_parser.is_mem)
7090 {
7091 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7092 /* Defer the warning until all of the operand was parsed. */
7093 intel_parser.is_mem = -1;
7094 else if (!quiet_warnings)
7095 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7096 }
7097 }
7098 intel_parser.op_modifier |= was_offset;
64a0c779 7099
a724f0f4 7100 return 1;
64a0c779 7101 }
a724f0f4 7102 return 0;
64a0c779
DN		 7103}
7104
7105/* e10 e11 e10'
7106
7107 e10' [ expr ] e10'
b77a7acd 7108 | Empty */
64a0c779
DN		 7109static int
7110intel_e10 ()
7111{
a724f0f4
JB		 7112 if (!intel_e11 ())
7113 return 0;
64a0c779 7114
a724f0f4 7115 while (cur_token.code == '[')
64a0c779 7116 {
a724f0f4 7117 if (!intel_bracket_expr ())
21d6c4af 7118 return 0;
64a0c779
DN		 7119 }
7120
a724f0f4 7121 return 1;
64a0c779
DN		 7122}
7123
64a0c779 7124/* e11 ( expr )
b77a7acd 7125 | [ expr ]
64a0c779
DN		 7126 | BYTE
7127 | WORD
7128 | DWORD
9306ca4a 7129 | FWORD
64a0c779 7130 | QWORD
9306ca4a
JB		 7131 | TBYTE
7132 | OWORD
7133 | XMMWORD
4a1805b1 7134 | $
64a0c779
DN		 7135 | .
7136 | register
7137 | id
7138 | constant */
7139static int
7140intel_e11 ()
7141{
a724f0f4 7142 switch (cur_token.code)
64a0c779 7143 {
a724f0f4
JB		 7144 /* e11 ( expr ) */
7145 case '(':
64a0c779
DN		 7146 intel_match_token ('(');
7147 strcat (intel_parser.disp, "(");
7148
7149 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7150 {
7151 strcat (intel_parser.disp, ")");
7152 return 1;
7153 }
a724f0f4 7154 return 0;
4a1805b1 7155
a724f0f4
JB		 7156 /* e11 [ expr ] */
7157 case '[':
a724f0f4 7158 return intel_bracket_expr ();
64a0c779 7159
a724f0f4
JB		 7160 /* e11 $
7161 | . */
7162 case '.':
64a0c779
DN		 7163 strcat (intel_parser.disp, cur_token.str);
7164 intel_match_token (cur_token.code);
21d6c4af
DN		 7165
7166 /* Mark as a memory operand only if it's not already known to be an
7167 offset expression. */
a724f0f4 7168 if (!intel_parser.in_offset)
21d6c4af 7169 intel_parser.is_mem = 1;
64a0c779
DN		 7170
7171 return 1;
64a0c779 7172
a724f0f4
JB		 7173 /* e11 register */
7174 case T_REG:
7175 {
7176 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7177
a724f0f4 7178 intel_match_token (T_REG);
64a0c779 7179
a724f0f4
JB		 7180 /* Check for segment change. */
7181 if (cur_token.code == ':')
7182 {
7183 if (!(reg->reg_type & (SReg2 | SReg3)))
7184 {
7185 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7186 return 0;
7187 }
7188 else if (i.seg[i.mem_operands])
7189 as_warn (_("Extra segment override ignored"));
7190 else
7191 {
7192 if (!intel_parser.in_offset)
7193 intel_parser.is_mem = 1;
7194 switch (reg->reg_num)
7195 {
7196 case 0:
7197 i.seg[i.mem_operands] = &es;
7198 break;
7199 case 1:
7200 i.seg[i.mem_operands] = &cs;
7201 break;
7202 case 2:
7203 i.seg[i.mem_operands] = &ss;
7204 break;
7205 case 3:
7206 i.seg[i.mem_operands] = &ds;
7207 break;
7208 case 4:
7209 i.seg[i.mem_operands] = &fs;
7210 break;
7211 case 5:
7212 i.seg[i.mem_operands] = &gs;
7213 break;
7214 }
7215 }
7216 }
64a0c779 7217
a724f0f4
JB		 7218 /* Not a segment register. Check for register scaling. */
7219 else if (cur_token.code == '*')
7220 {
7221 if (!intel_parser.in_bracket)
7222 {
7223 as_bad (_("Register scaling only allowed in memory operands"));
7224 return 0;
7225 }
64a0c779 7226
a724f0f4
JB		 7227 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7228 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7229 else if (i.index_reg)
7230 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7231
a724f0f4
JB		 7232 /* What follows must be a valid scale. */
7233 intel_match_token ('*');
7234 i.index_reg = reg;
7235 i.types[this_operand] |= BaseIndex;
64a0c779 7236
a724f0f4
JB		 7237 /* Set the scale after setting the register (otherwise,
7238 i386_scale will complain) */
7239 if (cur_token.code == '+' || cur_token.code == '-')
7240 {
7241 char *str, sign = cur_token.code;
7242 intel_match_token (cur_token.code);
7243 if (cur_token.code != T_CONST)
7244 {
7245 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7246 cur_token.str);
7247 return 0;
7248 }
7249 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7250 strcpy (str + 1, cur_token.str);
7251 *str = sign;
7252 if (!i386_scale (str))
7253 return 0;
7254 free (str);
7255 }
7256 else if (!i386_scale (cur_token.str))
64a0c779 7257 return 0;
a724f0f4
JB		 7258 intel_match_token (cur_token.code);
7259 }
64a0c779 7260
a724f0f4
JB		 7261 /* No scaling. If this is a memory operand, the register is either a
7262 base register (first occurrence) or an index register (second
7263 occurrence). */
7b0441f6 7264 else if (intel_parser.in_bracket)
a724f0f4 7265 {
64a0c779 7266
a724f0f4
JB		 7267 if (!i.base_reg)
7268 i.base_reg = reg;
7269 else if (!i.index_reg)
7270 i.index_reg = reg;
7271 else
7272 {
7273 as_bad (_("Too many register references in memory operand"));
7274 return 0;
7275 }
64a0c779 7276
a724f0f4
JB		 7277 i.types[this_operand] |= BaseIndex;
7278 }
4a1805b1 7279
4d1bb795
JB		 7280 /* It's neither base nor index. */
7281 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7282 {
7283 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7284 i.op[this_operand].regs = reg;
7285 i.reg_operands++;
7286 }
7287 else
7288 {
7289 as_bad (_("Invalid use of register"));
7290 return 0;
7291 }
64a0c779 7292
a724f0f4
JB		 7293 /* Since registers are not part of the displacement string (except
7294 when we're parsing offset operands), we may need to remove any
7295 preceding '+' from the displacement string. */
7296 if (*intel_parser.disp != '\0'
7297 && !intel_parser.in_offset)
7298 {
7299 char *s = intel_parser.disp;
7300 s += strlen (s) - 1;
7301 if (*s == '+')
7302 *s = '\0';
7303 }
4a1805b1 7304
a724f0f4
JB		 7305 return 1;
7306 }
7307
7308 /* e11 BYTE
7309 | WORD
7310 | DWORD
7311 | FWORD
7312 | QWORD
7313 | TBYTE
7314 | OWORD
7315 | XMMWORD */
7316 case T_BYTE:
7317 case T_WORD:
7318 case T_DWORD:
7319 case T_FWORD:
7320 case T_QWORD:
7321 case T_TBYTE:
7322 case T_XMMWORD:
7323 intel_match_token (cur_token.code);
64a0c779 7324
a724f0f4
JB		 7325 if (cur_token.code == T_PTR)
7326 return 1;
7327
7328 /* It must have been an identifier. */
7329 intel_putback_token ();
7330 cur_token.code = T_ID;
7331 /* FALLTHRU */
7332
7333 /* e11 id
7334 | constant */
7335 case T_ID:
7336 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7337 {
7338 symbolS *symbolP;
7339
a724f0f4
JB		 7340 /* The identifier represents a memory reference only if it's not
7341 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7342 symbolP = symbol_find(cur_token.str);
7343 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7344 intel_parser.is_mem = 1;
7345 }
a724f0f4 7346 /* FALLTHRU */
64a0c779 7347
a724f0f4
JB		 7348 case T_CONST:
7349 case '-':
7350 case '+':
7351 {
7352 char *save_str, sign = 0;
64a0c779 7353
a724f0f4
JB		 7354 /* Allow constants that start with `+' or `-'. */
7355 if (cur_token.code == '-' || cur_token.code == '+')
7356 {
7357 sign = cur_token.code;
7358 intel_match_token (cur_token.code);
7359 if (cur_token.code != T_CONST)
7360 {
7361 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7362 cur_token.str);
7363 return 0;
7364 }
7365 }
64a0c779 7366
a724f0f4
JB		 7367 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7368 strcpy (save_str + !!sign, cur_token.str);
7369 if (sign)
7370 *save_str = sign;
64a0c779 7371
a724f0f4
JB		 7372 /* Get the next token to check for register scaling. */
7373 intel_match_token (cur_token.code);
64a0c779 7374
a724f0f4
JB		 7375 /* Check if this constant is a scaling factor for an index register. */
7376 if (cur_token.code == '*')
7377 {
7378 if (intel_match_token ('*') && cur_token.code == T_REG)
7379 {
7380 const reg_entry *reg = cur_token.reg;
7381
7382 if (!intel_parser.in_bracket)
7383 {
7384 as_bad (_("Register scaling only allowed in memory operands"));
7385 return 0;
7386 }
7387
7388 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7389 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7390 else if (i.index_reg)
7391 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7392
7393 /* The constant is followed by `* reg', so it must be
7394 a valid scale. */
7395 i.index_reg = reg;
7396 i.types[this_operand] |= BaseIndex;
7397
7398 /* Set the scale after setting the register (otherwise,
7399 i386_scale will complain) */
7400 if (!i386_scale (save_str))
64a0c779 7401 return 0;
a724f0f4
JB		 7402 intel_match_token (T_REG);
7403
7404 /* Since registers are not part of the displacement
7405 string, we may need to remove any preceding '+' from
7406 the displacement string. */
7407 if (*intel_parser.disp != '\0')
7408 {
7409 char *s = intel_parser.disp;
7410 s += strlen (s) - 1;
7411 if (*s == '+')
7412 *s = '\0';
7413 }
7414
7415 free (save_str);
7416
7417 return 1;
7418 }
64a0c779 7419
a724f0f4
JB		 7420 /* The constant was not used for register scaling. Since we have
7421 already consumed the token following `*' we now need to put it
7422 back in the stream. */
64a0c779 7423 intel_putback_token ();
a724f0f4 7424 }
64a0c779 7425
a724f0f4
JB		 7426 /* Add the constant to the displacement string. */
7427 strcat (intel_parser.disp, save_str);
7428 free (save_str);
64a0c779 7429
a724f0f4
JB		 7430 return 1;
7431 }
64a0c779
DN		 7432 }
7433
64a0c779
DN		 7434 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7435 return 0;
7436}
7437
64a0c779
DN		 7438/* Match the given token against cur_token. If they match, read the next
7439 token from the operand string. */
7440static int
7441intel_match_token (code)
e5cb08ac 7442 int code;
64a0c779
DN		 7443{
7444 if (cur_token.code == code)
7445 {
7446 intel_get_token ();
7447 return 1;
7448 }
7449 else
7450 {
0477af35 7451 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7452 return 0;
7453 }
7454}
7455
64a0c779
DN		 7456/* Read a new token from intel_parser.op_string and store it in cur_token. */
7457static void
7458intel_get_token ()
7459{
7460 char *end_op;
7461 const reg_entry *reg;
7462 struct intel_token new_token;
7463
7464 new_token.code = T_NIL;
7465 new_token.reg = NULL;
7466 new_token.str = NULL;
7467
4a1805b1 7468 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7469 cur_token to prev_token. */
7470 if (prev_token.str)
7471 free (prev_token.str);
7472
7473 prev_token = cur_token;
7474
7475 /* Skip whitespace. */
7476 while (is_space_char (*intel_parser.op_string))
7477 intel_parser.op_string++;
7478
7479 /* Return an empty token if we find nothing else on the line. */
7480 if (*intel_parser.op_string == '\0')
7481 {
7482 cur_token = new_token;
7483 return;
7484 }
7485
7486 /* The new token cannot be larger than the remainder of the operand
7487 string. */
a724f0f4 7488 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7489 new_token.str[0] = '\0';
7490
7491 if (strchr ("0123456789", *intel_parser.op_string))
7492 {
7493 char *p = new_token.str;
7494 char *q = intel_parser.op_string;
7495 new_token.code = T_CONST;
7496
7497 /* Allow any kind of identifier char to encompass floating point and
7498 hexadecimal numbers. */
7499 while (is_identifier_char (*q))
7500 *p++ = *q++;
7501 *p = '\0';
7502
7503 /* Recognize special symbol names [0-9][bf]. */
7504 if (strlen (intel_parser.op_string) == 2
4a1805b1 7505 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7506 || intel_parser.op_string[1] == 'f'))
7507 new_token.code = T_ID;
7508 }
7509
4d1bb795 7510 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7511 {
4d1bb795
JB		 7512 size_t len = end_op - intel_parser.op_string;
7513
64a0c779
DN		 7514 new_token.code = T_REG;
7515 new_token.reg = reg;
7516
4d1bb795
JB		 7517 memcpy (new_token.str, intel_parser.op_string, len);
7518 new_token.str[len] = '\0';
64a0c779
DN		 7519 }
7520
7521 else if (is_identifier_char (*intel_parser.op_string))
7522 {
7523 char *p = new_token.str;
7524 char *q = intel_parser.op_string;
7525
7526 /* A '.' or '$' followed by an identifier char is an identifier.
7527 Otherwise, it's operator '.' followed by an expression. */
7528 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7529 {
9306ca4a
JB		 7530 new_token.code = '.';
7531 new_token.str[0] = '.';
64a0c779
DN		 7532 new_token.str[1] = '\0';
7533 }
7534 else
7535 {
7536 while (is_identifier_char (*q) || *q == '@')
7537 *p++ = *q++;
7538 *p = '\0';
7539
9306ca4a
JB		 7540 if (strcasecmp (new_token.str, "NOT") == 0)
7541 new_token.code = '~';
7542
7543 else if (strcasecmp (new_token.str, "MOD") == 0)
7544 new_token.code = '%';
7545
7546 else if (strcasecmp (new_token.str, "AND") == 0)
7547 new_token.code = '&';
7548
7549 else if (strcasecmp (new_token.str, "OR") == 0)
7550 new_token.code = '|';
7551
7552 else if (strcasecmp (new_token.str, "XOR") == 0)
7553 new_token.code = '^';
7554
7555 else if (strcasecmp (new_token.str, "SHL") == 0)
7556 new_token.code = T_SHL;
7557
7558 else if (strcasecmp (new_token.str, "SHR") == 0)
7559 new_token.code = T_SHR;
7560
7561 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7562 new_token.code = T_BYTE;
7563
7564 else if (strcasecmp (new_token.str, "WORD") == 0)
7565 new_token.code = T_WORD;
7566
7567 else if (strcasecmp (new_token.str, "DWORD") == 0)
7568 new_token.code = T_DWORD;
7569
9306ca4a
JB		 7570 else if (strcasecmp (new_token.str, "FWORD") == 0)
7571 new_token.code = T_FWORD;
7572
64a0c779
DN		 7573 else if (strcasecmp (new_token.str, "QWORD") == 0)
7574 new_token.code = T_QWORD;
7575
9306ca4a
JB		 7576 else if (strcasecmp (new_token.str, "TBYTE") == 0
7577 /* XXX remove (gcc still uses it) */
7578 || strcasecmp (new_token.str, "XWORD") == 0)
7579 new_token.code = T_TBYTE;
7580
7581 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7582 || strcasecmp (new_token.str, "OWORD") == 0)
7583 new_token.code = T_XMMWORD;
64a0c779
DN		 7584
7585 else if (strcasecmp (new_token.str, "PTR") == 0)
7586 new_token.code = T_PTR;
7587
7588 else if (strcasecmp (new_token.str, "SHORT") == 0)
7589 new_token.code = T_SHORT;
7590
7591 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7592 {
7593 new_token.code = T_OFFSET;
7594
7595 /* ??? This is not mentioned in the MASM grammar but gcc
7596 makes use of it with -mintel-syntax. OFFSET may be
7597 followed by FLAT: */
7598 if (strncasecmp (q, " FLAT:", 6) == 0)
7599 strcat (new_token.str, " FLAT:");
7600 }
7601
7602 /* ??? This is not mentioned in the MASM grammar. */
7603 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7604 {
7605 new_token.code = T_OFFSET;
7606 if (*q == ':')
7607 strcat (new_token.str, ":");
7608 else
7609 as_bad (_("`:' expected"));
7610 }
64a0c779
DN		 7611
7612 else
7613 new_token.code = T_ID;
7614 }
7615 }
7616
9306ca4a
JB		 7617 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7618 {
7619 new_token.code = *intel_parser.op_string;
7620 new_token.str[0] = *intel_parser.op_string;
7621 new_token.str[1] = '\0';
7622 }
7623
7624 else if (strchr ("<>", *intel_parser.op_string)
7625 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7626 {
7627 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7628 new_token.str[0] = *intel_parser.op_string;
7629 new_token.str[1] = *intel_parser.op_string;
7630 new_token.str[2] = '\0';
7631 }
7632
64a0c779 7633 else
0477af35 7634 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7635
7636 intel_parser.op_string += strlen (new_token.str);
7637 cur_token = new_token;
7638}
7639
64a0c779
DN		 7640/* Put cur_token back into the token stream and make cur_token point to
7641 prev_token. */
7642static void
7643intel_putback_token ()
7644{
a724f0f4
JB		 7645 if (cur_token.code != T_NIL)
7646 {
7647 intel_parser.op_string -= strlen (cur_token.str);
7648 free (cur_token.str);
7649 }
64a0c779 7650 cur_token = prev_token;
4a1805b1 7651
64a0c779
DN		 7652 /* Forget prev_token. */
7653 prev_token.code = T_NIL;
7654 prev_token.reg = NULL;
7655 prev_token.str = NULL;
7656}
54cfded0 7657
a4447b93 7658int
1df69f4f 7659tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7660{
7661 unsigned int regnum;
7662 unsigned int regnames_count;
089dfecd 7663 static const char *const regnames_32[] =
54cfded0 7664 {
a4447b93
RH		 7665 "eax", "ecx", "edx", "ebx",
7666 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7667 "eip", "eflags", NULL,
7668 "st0", "st1", "st2", "st3",
7669 "st4", "st5", "st6", "st7",
7670 NULL, NULL,
7671 "xmm0", "xmm1", "xmm2", "xmm3",
7672 "xmm4", "xmm5", "xmm6", "xmm7",
7673 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7674 "mm4", "mm5", "mm6", "mm7",
7675 "fcw", "fsw", "mxcsr",
7676 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7677 "tr", "ldtr"
54cfded0 7678 };
089dfecd 7679 static const char *const regnames_64[] =
54cfded0 7680 {
089dfecd
JB		 7681 "rax", "rdx", "rcx", "rbx",
7682 "rsi", "rdi", "rbp", "rsp",
7683 "r8", "r9", "r10", "r11",
54cfded0 7684 "r12", "r13", "r14", "r15",
089dfecd
JB		 7685 "rip",
7686 "xmm0", "xmm1", "xmm2", "xmm3",
7687 "xmm4", "xmm5", "xmm6", "xmm7",
7688 "xmm8", "xmm9", "xmm10", "xmm11",
7689 "xmm12", "xmm13", "xmm14", "xmm15",
7690 "st0", "st1", "st2", "st3",
7691 "st4", "st5", "st6", "st7",
7692 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7693 "mm4", "mm5", "mm6", "mm7",
7694 "rflags",
7695 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7696 "fs.base", "gs.base", NULL, NULL,
7697 "tr", "ldtr",
7698 "mxcsr", "fcw", "fsw"
54cfded0 7699 };
089dfecd 7700 const char *const *regnames;
54cfded0
AM		 7701
7702 if (flag_code == CODE_64BIT)
7703 {
7704 regnames = regnames_64;
0cea6190 7705 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7706 }
7707 else
7708 {
7709 regnames = regnames_32;
0cea6190 7710 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7711 }
7712
7713 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7714 if (regnames[regnum] != NULL
7715 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7716 return regnum;
7717
54cfded0
AM		 7718 return -1;
7719}
7720
7721void
7722tc_x86_frame_initial_instructions (void)
7723{
a4447b93
RH		 7724 static unsigned int sp_regno;
7725
7726 if (!sp_regno)
7727 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7728 ? "rsp" : "esp");
7729
7730 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7731 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7732}
d2b2c203
DJ		 7733
7734int
7735i386_elf_section_type (const char *str, size_t len)
7736{
7737 if (flag_code == CODE_64BIT
7738 && len == sizeof ("unwind") - 1
7739 && strncmp (str, "unwind", 6) == 0)
7740 return SHT_X86_64_UNWIND;
7741
7742 return -1;
7743}
bb41ade5
AM		 7744
7745#ifdef TE_PE
7746void
7747tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7748{
7749 expressionS expr;
7750
7751 expr.X_op = O_secrel;
7752 expr.X_add_symbol = symbol;
7753 expr.X_add_number = 0;
7754 emit_expr (&expr, size);
7755}
7756#endif
3b22753a
L		 7757
7758#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7759/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7760
7761int
7762x86_64_section_letter (int letter, char **ptr_msg)
7763{
7764 if (flag_code == CODE_64BIT)
7765 {
7766 if (letter == 'l')
7767 return SHF_X86_64_LARGE;
7768
7769 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7770 }
3b22753a 7771 else
64e74474 7772 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7773 return -1;
7774}
7775
7776int
7777x86_64_section_word (char *str, size_t len)
7778{
7779 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7780 return SHF_X86_64_LARGE;
7781
7782 return -1;
7783}
7784
7785static void
7786handle_large_common (int small ATTRIBUTE_UNUSED)
7787{
7788 if (flag_code != CODE_64BIT)
7789 {
7790 s_comm_internal (0, elf_common_parse);
7791 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7792 }
7793 else
7794 {
7795 static segT lbss_section;
7796 asection *saved_com_section_ptr = elf_com_section_ptr;
7797 asection *saved_bss_section = bss_section;
7798
7799 if (lbss_section == NULL)
7800 {
7801 flagword applicable;
7802 segT seg = now_seg;
7803 subsegT subseg = now_subseg;
7804
7805 /* The .lbss section is for local .largecomm symbols. */
7806 lbss_section = subseg_new (".lbss", 0);
7807 applicable = bfd_applicable_section_flags (stdoutput);
7808 bfd_set_section_flags (stdoutput, lbss_section,
7809 applicable & SEC_ALLOC);
7810 seg_info (lbss_section)->bss = 1;
7811
7812 subseg_set (seg, subseg);
7813 }
7814
7815 elf_com_section_ptr = &_bfd_elf_large_com_section;
7816 bss_section = lbss_section;
7817
7818 s_comm_internal (0, elf_common_parse);
7819
7820 elf_com_section_ptr = saved_com_section_ptr;
7821 bss_section = saved_bss_section;
7822 }
7823}
7824#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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