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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 135}
136arch_entry;
137
78f12dd3 138static void update_code_flag (int, int);
e3bb37b5
L		 139static void set_code_flag (int);
140static void set_16bit_gcc_code_flag (int);
141static void set_intel_syntax (int);
1efbbeb4 142static void set_intel_mnemonic (int);
db51cc60 143static void set_allow_index_reg (int);
cb19c032 144static void set_sse_check (int);
e3bb37b5 145static void set_cpu_arch (int);
6482c264 146#ifdef TE_PE
e3bb37b5 147static void pe_directive_secrel (int);
6482c264 148#endif
e3bb37b5
L		 149static void signed_cons (int);
150static char *output_invalid (int c);
ee86248c
JB		 151static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
152 const char *);
153static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
154 const char *);
a7619375 155static int i386_att_operand (char *);
e3bb37b5 156static int i386_intel_operand (char *, int);
ee86248c
JB		 157static int i386_intel_simplify (expressionS *);
158static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 159static const reg_entry *parse_register (char *, char **);
160static char *parse_insn (char *, char *);
161static char *parse_operands (char *, const char *);
162static void swap_operands (void);
4d456e3d 163static void swap_2_operands (int, int);
e3bb37b5
L		 164static void optimize_imm (void);
165static void optimize_disp (void);
d3ce72d0 166static const insn_template *match_template (void);
e3bb37b5
L		 167static int check_string (void);
168static int process_suffix (void);
169static int check_byte_reg (void);
170static int check_long_reg (void);
171static int check_qword_reg (void);
172static int check_word_reg (void);
173static int finalize_imm (void);
174static int process_operands (void);
175static const seg_entry *build_modrm_byte (void);
176static void output_insn (void);
177static void output_imm (fragS *, offsetT);
178static void output_disp (fragS *, offsetT);
29b0f896 179#ifndef I386COFF
e3bb37b5 180static void s_bss (int);
252b5132 181#endif
17d4e2a2
L		 182#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
183static void handle_large_common (int small ATTRIBUTE_UNUSED);
184#endif
252b5132 185
a847613f 186static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 187
c0f3af97
L		 188/* VEX prefix. */
189typedef struct
190{
191 /* VEX prefix is either 2 byte or 3 byte. */
192 unsigned char bytes[3];
193 unsigned int length;
194 /* Destination or source register specifier. */
195 const reg_entry *register_specifier;
196} vex_prefix;
197
252b5132 198/* 'md_assemble ()' gathers together information and puts it into a
47926f60 199 i386_insn. */
252b5132 200
520dc8e8
AM		 201union i386_op
202 {
203 expressionS *disps;
204 expressionS *imms;
205 const reg_entry *regs;
206 };
207
a65babc9
L		 208enum i386_error
209 {
86e026a4 210 operand_size_mismatch,
a65babc9
L		 211 operand_type_mismatch,
212 register_type_mismatch,
213 number_of_operands_mismatch,
214 invalid_instruction_suffix,
215 bad_imm4,
216 old_gcc_only,
217 unsupported_with_intel_mnemonic,
218 unsupported_syntax,
219 unsupported
220 };
221
252b5132
RH		 222struct _i386_insn
223 {
47926f60 224 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 225 insn_template tm;
252b5132 226
7d5e4556
L		 227 /* SUFFIX holds the instruction size suffix for byte, word, dword
228 or qword, if given. */
252b5132
RH		 229 char suffix;
230
47926f60 231 /* OPERANDS gives the number of given operands. */
252b5132
RH		 232 unsigned int operands;
233
234 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
235 of given register, displacement, memory operands and immediate
47926f60 236 operands. */
252b5132
RH		 237 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
238
239 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 240 use OP[i] for the corresponding operand. */
40fb9820 241 i386_operand_type types[MAX_OPERANDS];
252b5132 242
520dc8e8
AM		 243 /* Displacement expression, immediate expression, or register for each
244 operand. */
245 union i386_op op[MAX_OPERANDS];
252b5132 246
3e73aa7c
JH		 247 /* Flags for operands. */
248 unsigned int flags[MAX_OPERANDS];
249#define Operand_PCrel 1
250
252b5132 251 /* Relocation type for operand */
f86103b7 252 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 253
252b5132
RH		 254 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
255 the base index byte below. */
256 const reg_entry *base_reg;
257 const reg_entry *index_reg;
258 unsigned int log2_scale_factor;
259
260 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 261 explicit segment overrides are given. */
ce8a8b2f 262 const seg_entry *seg[2];
252b5132
RH		 263
264 /* PREFIX holds all the given prefix opcodes (usually null).
265 PREFIXES is the number of prefix opcodes. */
266 unsigned int prefixes;
267 unsigned char prefix[MAX_PREFIXES];
268
269 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 270 addressing modes of this insn are encoded. */
252b5132 271 modrm_byte rm;
3e73aa7c 272 rex_byte rex;
252b5132 273 sib_byte sib;
c0f3af97 274 vex_prefix vex;
b6169b20
L		 275
276 /* Swap operand in encoding. */
4473e004 277 unsigned int swap_operand;
891edac4
L		 278
279 /* Error message. */
a65babc9 280 enum i386_error error;
252b5132
RH		 281 };
282
283typedef struct _i386_insn i386_insn;
284
285/* List of chars besides those in app.c:symbol_chars that can start an
286 operand. Used to prevent the scrubber eating vital white-space. */
32137342 287const char extra_symbol_chars[] = "*%-(["
252b5132 288#ifdef LEX_AT
32137342
NC		 289 "@"
290#endif
291#ifdef LEX_QM
292 "?"
252b5132 293#endif
32137342 294 ;
252b5132 295
29b0f896
AM		 296#if (defined (TE_I386AIX) \
297 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 298 && !defined (TE_GNU) \
29b0f896 299 && !defined (TE_LINUX) \
32137342 300 && !defined (TE_NETWARE) \
29b0f896
AM		 301 && !defined (TE_FreeBSD) \
302 && !defined (TE_NetBSD)))
252b5132 303/* This array holds the chars that always start a comment. If the
b3b91714
AM		 304 pre-processor is disabled, these aren't very useful. The option
305 --divide will remove '/' from this list. */
306const char *i386_comment_chars = "#/";
307#define SVR4_COMMENT_CHARS 1
252b5132 308#define PREFIX_SEPARATOR '\\'
252b5132 309
b3b91714
AM		 310#else
311const char *i386_comment_chars = "#";
312#define PREFIX_SEPARATOR '/'
313#endif
314
252b5132
RH		 315/* This array holds the chars that only start a comment at the beginning of
316 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 317 .line and .file directives will appear in the pre-processed output.
318 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 319 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 320 #NO_APP at the beginning of its output.
321 Also note that comments started like this one will always work if
252b5132 322 '/' isn't otherwise defined. */
b3b91714 323const char line_comment_chars[] = "#/";
252b5132 324
63a0b638 325const char line_separator_chars[] = ";";
252b5132 326
ce8a8b2f
AM		 327/* Chars that can be used to separate mant from exp in floating point
328 nums. */
252b5132
RH		 329const char EXP_CHARS[] = "eE";
330
ce8a8b2f
AM		 331/* Chars that mean this number is a floating point constant
332 As in 0f12.456
333 or 0d1.2345e12. */
252b5132
RH		 334const char FLT_CHARS[] = "fFdDxX";
335
ce8a8b2f 336/* Tables for lexical analysis. */
252b5132
RH		 337static char mnemonic_chars[256];
338static char register_chars[256];
339static char operand_chars[256];
340static char identifier_chars[256];
341static char digit_chars[256];
342
ce8a8b2f 343/* Lexical macros. */
252b5132
RH		 344#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
345#define is_operand_char(x) (operand_chars[(unsigned char) x])
346#define is_register_char(x) (register_chars[(unsigned char) x])
347#define is_space_char(x) ((x) == ' ')
348#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
349#define is_digit_char(x) (digit_chars[(unsigned char) x])
350
0234cb7c 351/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 352static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
353
354/* md_assemble() always leaves the strings it's passed unaltered. To
355 effect this we maintain a stack of saved characters that we've smashed
356 with '\0's (indicating end of strings for various sub-fields of the
47926f60 357 assembler instruction). */
252b5132 358static char save_stack[32];
ce8a8b2f 359static char *save_stack_p;
252b5132
RH		 360#define END_STRING_AND_SAVE(s) \
361 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
362#define RESTORE_END_STRING(s) \
363 do { *(s) = *--save_stack_p; } while (0)
364
47926f60 365/* The instruction we're assembling. */
252b5132
RH		 366static i386_insn i;
367
368/* Possible templates for current insn. */
369static const templates *current_templates;
370
31b2323c
L		 371/* Per instruction expressionS buffers: max displacements & immediates. */
372static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
373static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 374
47926f60 375/* Current operand we are working on. */
ee86248c 376static int this_operand = -1;
252b5132 377
3e73aa7c
JH		 378/* We support four different modes. FLAG_CODE variable is used to distinguish
379 these. */
380
381enum flag_code {
382 CODE_32BIT,
383 CODE_16BIT,
384 CODE_64BIT };
385
386static enum flag_code flag_code;
4fa24527 387static unsigned int object_64bit;
3e73aa7c
JH		 388static int use_rela_relocations = 0;
389
390/* The names used to print error messages. */
b77a7acd 391static const char *flag_code_names[] =
3e73aa7c
JH		 392 {
393 "32",
394 "16",
395 "64"
396 };
252b5132 397
47926f60
KH		 398/* 1 for intel syntax,
399 0 if att syntax. */
400static int intel_syntax = 0;
252b5132 401
1efbbeb4
L		 402/* 1 for intel mnemonic,
403 0 if att mnemonic. */
404static int intel_mnemonic = !SYSV386_COMPAT;
405
5209009a 406/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 407static int old_gcc = OLDGCC_COMPAT;
408
a60de03c
JB		 409/* 1 if pseudo registers are permitted. */
410static int allow_pseudo_reg = 0;
411
47926f60
KH		 412/* 1 if register prefix % not required. */
413static int allow_naked_reg = 0;
252b5132 414
ba104c83 415/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 416static int allow_index_reg = 0;
417
daf50ae7
L		 418static enum
419 {
420 sse_check_none = 0,
421 sse_check_warning,
422 sse_check_error
423 }
424sse_check;
425
2ca3ace5
L		 426/* Register prefix used for error message. */
427static const char *register_prefix = "%";
428
47926f60
KH		 429/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
430 leave, push, and pop instructions so that gcc has the same stack
431 frame as in 32 bit mode. */
432static char stackop_size = '\0';
eecb386c 433
12b55ccc
L		 434/* Non-zero to optimize code alignment. */
435int optimize_align_code = 1;
436
47926f60
KH		 437/* Non-zero to quieten some warnings. */
438static int quiet_warnings = 0;
a38cf1db 439
47926f60
KH		 440/* CPU name. */
441static const char *cpu_arch_name = NULL;
6305a203 442static char *cpu_sub_arch_name = NULL;
a38cf1db 443
47926f60 444/* CPU feature flags. */
40fb9820
L		 445static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
446
ccc9c027
L		 447/* If we have selected a cpu we are generating instructions for. */
448static int cpu_arch_tune_set = 0;
449
9103f4f4 450/* Cpu we are generating instructions for. */
fbf3f584 451enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 452
453/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 454static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 455
ccc9c027 456/* CPU instruction set architecture used. */
fbf3f584 457enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 458
9103f4f4 459/* CPU feature flags of instruction set architecture used. */
fbf3f584 460i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 461
fddf5b5b
AM		 462/* If set, conditional jumps are not automatically promoted to handle
463 larger than a byte offset. */
464static unsigned int no_cond_jump_promotion = 0;
465
c0f3af97
L		 466/* Encode SSE instructions with VEX prefix. */
467static unsigned int sse2avx;
468
539f890d
L		 469/* Encode scalar AVX instructions with specific vector length. */
470static enum
471 {
472 vex128 = 0,
473 vex256
474 } avxscalar;
475
29b0f896 476/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 477static symbolS *GOT_symbol;
29b0f896 478
a4447b93
RH		 479/* The dwarf2 return column, adjusted for 32 or 64 bit. */
480unsigned int x86_dwarf2_return_column;
481
482/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
483int x86_cie_data_alignment;
484
252b5132 485/* Interface to relax_segment.
fddf5b5b
AM		 486 There are 3 major relax states for 386 jump insns because the
487 different types of jumps add different sizes to frags when we're
488 figuring out what sort of jump to choose to reach a given label. */
252b5132 489
47926f60 490/* Types. */
93c2a809
AM		 491#define UNCOND_JUMP 0
492#define COND_JUMP 1
493#define COND_JUMP86 2
fddf5b5b 494
47926f60 495/* Sizes. */
252b5132
RH		 496#define CODE16 1
497#define SMALL 0
29b0f896 498#define SMALL16 (SMALL | CODE16)
252b5132 499#define BIG 2
29b0f896 500#define BIG16 (BIG | CODE16)
252b5132
RH		 501
502#ifndef INLINE
503#ifdef __GNUC__
504#define INLINE __inline__
505#else
506#define INLINE
507#endif
508#endif
509
fddf5b5b
AM		 510#define ENCODE_RELAX_STATE(type, size) \
511 ((relax_substateT) (((type) << 2) | (size)))
512#define TYPE_FROM_RELAX_STATE(s) \
513 ((s) >> 2)
514#define DISP_SIZE_FROM_RELAX_STATE(s) \
515 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 516
517/* This table is used by relax_frag to promote short jumps to long
518 ones where necessary. SMALL (short) jumps may be promoted to BIG
519 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
520 don't allow a short jump in a 32 bit code segment to be promoted to
521 a 16 bit offset jump because it's slower (requires data size
522 prefix), and doesn't work, unless the destination is in the bottom
523 64k of the code segment (The top 16 bits of eip are zeroed). */
524
525const relax_typeS md_relax_table[] =
526{
24eab124
AM		 527 /* The fields are:
528 1) most positive reach of this state,
529 2) most negative reach of this state,
93c2a809 530 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 531 4) which index into the table to try if we can't fit into this one. */
252b5132 532
fddf5b5b 533 /* UNCOND_JUMP states. */
93c2a809
AM		 534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
535 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
536 /* dword jmp adds 4 bytes to frag:
537 0 extra opcode bytes, 4 displacement bytes. */
252b5132 538 {0, 0, 4, 0},
93c2a809
AM		 539 /* word jmp adds 2 byte2 to frag:
540 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 541 {0, 0, 2, 0},
542
93c2a809
AM		 543 /* COND_JUMP states. */
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
545 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
546 /* dword conditionals adds 5 bytes to frag:
547 1 extra opcode byte, 4 displacement bytes. */
548 {0, 0, 5, 0},
fddf5b5b 549 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 550 1 extra opcode byte, 2 displacement bytes. */
551 {0, 0, 3, 0},
552
553 /* COND_JUMP86 states. */
554 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
555 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
556 /* dword conditionals adds 5 bytes to frag:
557 1 extra opcode byte, 4 displacement bytes. */
558 {0, 0, 5, 0},
559 /* word conditionals add 4 bytes to frag:
560 1 displacement byte and a 3 byte long branch insn. */
561 {0, 0, 4, 0}
252b5132
RH		 562};
563
9103f4f4
L		 564static const arch_entry cpu_arch[] =
565{
89507696
JB		 566 /* Do not replace the first two entries - i386_target_format()
567 relies on them being there in this order. */
8a2c8fef
L		 568 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
569 CPU_GENERIC32_FLAGS, 0 },
570 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
571 CPU_GENERIC64_FLAGS, 0 },
572 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
573 CPU_NONE_FLAGS, 0 },
574 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
575 CPU_I186_FLAGS, 0 },
576 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
577 CPU_I286_FLAGS, 0 },
578 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
579 CPU_I386_FLAGS, 0 },
580 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
581 CPU_I486_FLAGS, 0 },
582 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
583 CPU_I586_FLAGS, 0 },
584 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
585 CPU_I686_FLAGS, 0 },
586 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
587 CPU_I586_FLAGS, 0 },
588 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
589 CPU_I686_FLAGS, 0 },
590 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
591 CPU_P2_FLAGS, 0 },
592 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
593 CPU_P3_FLAGS, 0 },
594 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
595 CPU_P4_FLAGS, 0 },
596 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
597 CPU_CORE_FLAGS, 0 },
598 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
599 CPU_NOCONA_FLAGS, 0 },
600 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
601 CPU_CORE_FLAGS, 1 },
602 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
603 CPU_CORE_FLAGS, 0 },
604 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
605 CPU_CORE2_FLAGS, 1 },
606 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
607 CPU_CORE2_FLAGS, 0 },
608 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
609 CPU_COREI7_FLAGS, 0 },
610 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
611 CPU_L1OM_FLAGS, 0 },
612 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
613 CPU_K6_FLAGS, 0 },
614 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
615 CPU_K6_2_FLAGS, 0 },
616 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
617 CPU_ATHLON_FLAGS, 0 },
618 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
619 CPU_K8_FLAGS, 1 },
620 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
621 CPU_K8_FLAGS, 0 },
622 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
623 CPU_K8_FLAGS, 0 },
624 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
625 CPU_AMDFAM10_FLAGS, 0 },
68339fdf
SP		 626 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
627 CPU_BDVER1_FLAGS, 0 },
8a2c8fef
L		 628 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
629 CPU_8087_FLAGS, 0 },
630 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
631 CPU_287_FLAGS, 0 },
632 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
633 CPU_387_FLAGS, 0 },
634 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
635 CPU_ANY87_FLAGS, 0 },
636 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
637 CPU_MMX_FLAGS, 0 },
638 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
639 CPU_3DNOWA_FLAGS, 0 },
640 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
641 CPU_SSE_FLAGS, 0 },
642 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
643 CPU_SSE2_FLAGS, 0 },
644 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
645 CPU_SSE3_FLAGS, 0 },
646 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
647 CPU_SSSE3_FLAGS, 0 },
648 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
649 CPU_SSE4_1_FLAGS, 0 },
650 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
651 CPU_SSE4_2_FLAGS, 0 },
652 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
653 CPU_SSE4_2_FLAGS, 0 },
654 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
655 CPU_ANY_SSE_FLAGS, 0 },
656 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
657 CPU_AVX_FLAGS, 0 },
658 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
659 CPU_ANY_AVX_FLAGS, 0 },
660 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
661 CPU_VMX_FLAGS, 0 },
662 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
663 CPU_SMX_FLAGS, 0 },
664 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
665 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a
L		 666 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
667 CPU_XSAVEOPT_FLAGS, 0 },
8a2c8fef
L		 668 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
669 CPU_AES_FLAGS, 0 },
670 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
671 CPU_PCLMUL_FLAGS, 0 },
672 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
673 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a
L		 674 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
675 CPU_FSGSBASE_FLAGS, 0 },
676 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
677 CPU_RDRND_FLAGS, 0 },
678 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
679 CPU_F16C_FLAGS, 0 },
8a2c8fef
L		 680 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
681 CPU_FMA_FLAGS, 0 },
682 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
683 CPU_FMA4_FLAGS, 0 },
684 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
685 CPU_XOP_FLAGS, 0 },
686 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
687 CPU_LWP_FLAGS, 0 },
688 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
689 CPU_MOVBE_FLAGS, 0 },
690 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
691 CPU_EPT_FLAGS, 0 },
692 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
693 CPU_CLFLUSH_FLAGS, 0 },
694 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
695 CPU_SYSCALL_FLAGS, 0 },
696 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
697 CPU_RDTSCP_FLAGS, 0 },
698 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
699 CPU_3DNOW_FLAGS, 0 },
700 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
701 CPU_3DNOWA_FLAGS, 0 },
702 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
703 CPU_PADLOCK_FLAGS, 0 },
704 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
705 CPU_SVME_FLAGS, 1 },
706 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
707 CPU_SVME_FLAGS, 0 },
708 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
709 CPU_SSE4A_FLAGS, 0 },
710 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
711 CPU_ABM_FLAGS, 0 },
e413e4e9
AM		 712};
713
704209c0 714#ifdef I386COFF
a6c24e68
NC		 715/* Like s_lcomm_internal in gas/read.c but the alignment string
716 is allowed to be optional. */
717
718static symbolS *
719pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
720{
721 addressT align = 0;
722
723 SKIP_WHITESPACE ();
724
7ab9ffdd 725 if (needs_align
a6c24e68
NC		 726 && *input_line_pointer == ',')
727 {
728 align = parse_align (needs_align - 1);
7ab9ffdd 729
a6c24e68
NC		 730 if (align == (addressT) -1)
731 return NULL;
732 }
733 else
734 {
735 if (size >= 8)
736 align = 3;
737 else if (size >= 4)
738 align = 2;
739 else if (size >= 2)
740 align = 1;
741 else
742 align = 0;
743 }
744
745 bss_alloc (symbolP, size, align);
746 return symbolP;
747}
748
704209c0 749static void
a6c24e68
NC		 750pe_lcomm (int needs_align)
751{
752 s_comm_internal (needs_align * 2, pe_lcomm_internal);
753}
704209c0 754#endif
a6c24e68 755
29b0f896
AM		 756const pseudo_typeS md_pseudo_table[] =
757{
758#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
759 {"align", s_align_bytes, 0},
760#else
761 {"align", s_align_ptwo, 0},
762#endif
763 {"arch", set_cpu_arch, 0},
764#ifndef I386COFF
765 {"bss", s_bss, 0},
a6c24e68
NC		 766#else
767 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 768#endif
769 {"ffloat", float_cons, 'f'},
770 {"dfloat", float_cons, 'd'},
771 {"tfloat", float_cons, 'x'},
772 {"value", cons, 2},
d182319b 773 {"slong", signed_cons, 4},
29b0f896
AM		 774 {"noopt", s_ignore, 0},
775 {"optim", s_ignore, 0},
776 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
777 {"code16", set_code_flag, CODE_16BIT},
778 {"code32", set_code_flag, CODE_32BIT},
779 {"code64", set_code_flag, CODE_64BIT},
780 {"intel_syntax", set_intel_syntax, 1},
781 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 782 {"intel_mnemonic", set_intel_mnemonic, 1},
783 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 784 {"allow_index_reg", set_allow_index_reg, 1},
785 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 786 {"sse_check", set_sse_check, 0},
3b22753a
L		 787#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
788 {"largecomm", handle_large_common, 0},
07a53e5c 789#else
e3bb37b5 790 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 791 {"loc", dwarf2_directive_loc, 0},
792 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 793#endif
6482c264
NC		 794#ifdef TE_PE
795 {"secrel32", pe_directive_secrel, 0},
796#endif
29b0f896
AM		 797 {0, 0, 0}
798};
799
800/* For interface with expression (). */
801extern char *input_line_pointer;
802
803/* Hash table for instruction mnemonic lookup. */
804static struct hash_control *op_hash;
805
806/* Hash table for register lookup. */
807static struct hash_control *reg_hash;
808\f
252b5132 809void
e3bb37b5 810i386_align_code (fragS *fragP, int count)
252b5132 811{
ce8a8b2f
AM		 812 /* Various efficient no-op patterns for aligning code labels.
813 Note: Don't try to assemble the instructions in the comments.
814 0L and 0w are not legal. */
252b5132
RH		 815 static const char f32_1[] =
816 {0x90}; /* nop */
817 static const char f32_2[] =
ccc9c027 818 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 819 static const char f32_3[] =
820 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
821 static const char f32_4[] =
822 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
823 static const char f32_5[] =
824 {0x90, /* nop */
825 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
826 static const char f32_6[] =
827 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
828 static const char f32_7[] =
829 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
830 static const char f32_8[] =
831 {0x90, /* nop */
832 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
833 static const char f32_9[] =
834 {0x89,0xf6, /* movl %esi,%esi */
835 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
836 static const char f32_10[] =
837 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
838 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
839 static const char f32_11[] =
840 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
841 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
842 static const char f32_12[] =
843 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
844 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
845 static const char f32_13[] =
846 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
847 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
848 static const char f32_14[] =
849 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
850 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 851 static const char f16_3[] =
852 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 853 static const char f16_4[] =
854 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
855 static const char f16_5[] =
856 {0x90, /* nop */
857 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
858 static const char f16_6[] =
859 {0x89,0xf6, /* mov %si,%si */
860 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
861 static const char f16_7[] =
862 {0x8d,0x74,0x00, /* lea 0(%si),%si */
863 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
864 static const char f16_8[] =
865 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
866 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 867 static const char jump_31[] =
868 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
869 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
870 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
871 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 872 static const char *const f32_patt[] = {
873 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 874 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 875 };
876 static const char *const f16_patt[] = {
76bc74dc 877 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 878 };
ccc9c027
L		 879 /* nopl (%[re]ax) */
880 static const char alt_3[] =
881 {0x0f,0x1f,0x00};
882 /* nopl 0(%[re]ax) */
883 static const char alt_4[] =
884 {0x0f,0x1f,0x40,0x00};
885 /* nopl 0(%[re]ax,%[re]ax,1) */
886 static const char alt_5[] =
887 {0x0f,0x1f,0x44,0x00,0x00};
888 /* nopw 0(%[re]ax,%[re]ax,1) */
889 static const char alt_6[] =
890 {0x66,0x0f,0x1f,0x44,0x00,0x00};
891 /* nopl 0L(%[re]ax) */
892 static const char alt_7[] =
893 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
894 /* nopl 0L(%[re]ax,%[re]ax,1) */
895 static const char alt_8[] =
896 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
897 /* nopw 0L(%[re]ax,%[re]ax,1) */
898 static const char alt_9[] =
899 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
901 static const char alt_10[] =
902 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
903 /* data16
904 nopw %cs:0L(%[re]ax,%[re]ax,1) */
905 static const char alt_long_11[] =
906 {0x66,
907 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
908 /* data16
909 data16
910 nopw %cs:0L(%[re]ax,%[re]ax,1) */
911 static const char alt_long_12[] =
912 {0x66,
913 0x66,
914 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
915 /* data16
916 data16
917 data16
918 nopw %cs:0L(%[re]ax,%[re]ax,1) */
919 static const char alt_long_13[] =
920 {0x66,
921 0x66,
922 0x66,
923 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
924 /* data16
925 data16
926 data16
927 data16
928 nopw %cs:0L(%[re]ax,%[re]ax,1) */
929 static const char alt_long_14[] =
930 {0x66,
931 0x66,
932 0x66,
933 0x66,
934 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
935 /* data16
936 data16
937 data16
938 data16
939 data16
940 nopw %cs:0L(%[re]ax,%[re]ax,1) */
941 static const char alt_long_15[] =
942 {0x66,
943 0x66,
944 0x66,
945 0x66,
946 0x66,
947 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
948 /* nopl 0(%[re]ax,%[re]ax,1)
949 nopw 0(%[re]ax,%[re]ax,1) */
950 static const char alt_short_11[] =
951 {0x0f,0x1f,0x44,0x00,0x00,
952 0x66,0x0f,0x1f,0x44,0x00,0x00};
953 /* nopw 0(%[re]ax,%[re]ax,1)
954 nopw 0(%[re]ax,%[re]ax,1) */
955 static const char alt_short_12[] =
956 {0x66,0x0f,0x1f,0x44,0x00,0x00,
957 0x66,0x0f,0x1f,0x44,0x00,0x00};
958 /* nopw 0(%[re]ax,%[re]ax,1)
959 nopl 0L(%[re]ax) */
960 static const char alt_short_13[] =
961 {0x66,0x0f,0x1f,0x44,0x00,0x00,
962 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
963 /* nopl 0L(%[re]ax)
964 nopl 0L(%[re]ax) */
965 static const char alt_short_14[] =
966 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
967 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
968 /* nopl 0L(%[re]ax)
969 nopl 0L(%[re]ax,%[re]ax,1) */
970 static const char alt_short_15[] =
971 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
972 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
973 static const char *const alt_short_patt[] = {
974 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
975 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
976 alt_short_14, alt_short_15
977 };
978 static const char *const alt_long_patt[] = {
979 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
980 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
981 alt_long_14, alt_long_15
982 };
252b5132 983
76bc74dc
L		 984 /* Only align for at least a positive non-zero boundary. */
985 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 986 return;
3e73aa7c 987
ccc9c027
L		 988 /* We need to decide which NOP sequence to use for 32bit and
989 64bit. When -mtune= is used:
4eed87de 990
76bc74dc
L		 991 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
992 PROCESSOR_GENERIC32, f32_patt will be used.
993 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 994 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
995 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 996 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 997 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 998 will be used.
ccc9c027 999
76bc74dc
L		 1000 When -mtune= isn't used, alt_long_patt will be used if
1001 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
1002 be used.
ccc9c027
L		 1003
1004 When -march= or .arch is used, we can't use anything beyond
1005 cpu_arch_isa_flags. */
1006
1007 if (flag_code == CODE_16BIT)
1008 {
ccc9c027 1009 if (count > 8)
33fef721 1010 {
76bc74dc
L		 1011 memcpy (fragP->fr_literal + fragP->fr_fix,
1012 jump_31, count);
1013 /* Adjust jump offset. */
1014 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1015 }
76bc74dc
L		 1016 else
1017 memcpy (fragP->fr_literal + fragP->fr_fix,
1018 f16_patt[count - 1], count);
252b5132 1019 }
33fef721 1020 else
ccc9c027
L		 1021 {
1022 const char *const *patt = NULL;
1023
fbf3f584 1024 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1025 {
1026 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1027 switch (cpu_arch_tune)
1028 {
1029 case PROCESSOR_UNKNOWN:
1030 /* We use cpu_arch_isa_flags to check if we SHOULD
1031 optimize for Cpu686. */
fbf3f584 1032 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 1033 patt = alt_long_patt;
ccc9c027
L		 1034 else
1035 patt = f32_patt;
1036 break;
ccc9c027
L		 1037 case PROCESSOR_PENTIUMPRO:
1038 case PROCESSOR_PENTIUM4:
1039 case PROCESSOR_NOCONA:
ef05d495 1040 case PROCESSOR_CORE:
76bc74dc 1041 case PROCESSOR_CORE2:
bd5295b2 1042 case PROCESSOR_COREI7:
3632d14b 1043 case PROCESSOR_L1OM:
76bc74dc
L		 1044 case PROCESSOR_GENERIC64:
1045 patt = alt_long_patt;
1046 break;
ccc9c027
L		 1047 case PROCESSOR_K6:
1048 case PROCESSOR_ATHLON:
1049 case PROCESSOR_K8:
4eed87de 1050 case PROCESSOR_AMDFAM10:
68339fdf 1051 case PROCESSOR_BDVER1:
ccc9c027
L		 1052 patt = alt_short_patt;
1053 break;
76bc74dc 1054 case PROCESSOR_I386:
ccc9c027
L		 1055 case PROCESSOR_I486:
1056 case PROCESSOR_PENTIUM:
1057 case PROCESSOR_GENERIC32:
1058 patt = f32_patt;
1059 break;
4eed87de 1060 }
ccc9c027
L		 1061 }
1062 else
1063 {
fbf3f584 1064 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1065 {
1066 case PROCESSOR_UNKNOWN:
e6a14101 1067 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1068 PROCESSOR_UNKNOWN. */
1069 abort ();
1070 break;
1071
76bc74dc 1072 case PROCESSOR_I386:
ccc9c027
L		 1073 case PROCESSOR_I486:
1074 case PROCESSOR_PENTIUM:
ccc9c027
L		 1075 case PROCESSOR_K6:
1076 case PROCESSOR_ATHLON:
1077 case PROCESSOR_K8:
4eed87de 1078 case PROCESSOR_AMDFAM10:
68339fdf 1079 case PROCESSOR_BDVER1:
ccc9c027
L		 1080 case PROCESSOR_GENERIC32:
1081 /* We use cpu_arch_isa_flags to check if we CAN optimize
1082 for Cpu686. */
fbf3f584 1083 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1084 patt = alt_short_patt;
1085 else
1086 patt = f32_patt;
1087 break;
76bc74dc
L		 1088 case PROCESSOR_PENTIUMPRO:
1089 case PROCESSOR_PENTIUM4:
1090 case PROCESSOR_NOCONA:
1091 case PROCESSOR_CORE:
ef05d495 1092 case PROCESSOR_CORE2:
bd5295b2 1093 case PROCESSOR_COREI7:
3632d14b 1094 case PROCESSOR_L1OM:
fbf3f584 1095 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1096 patt = alt_long_patt;
1097 else
1098 patt = f32_patt;
1099 break;
1100 case PROCESSOR_GENERIC64:
76bc74dc 1101 patt = alt_long_patt;
ccc9c027 1102 break;
4eed87de 1103 }
ccc9c027
L		 1104 }
1105
76bc74dc
L		 1106 if (patt == f32_patt)
1107 {
1108 /* If the padding is less than 15 bytes, we use the normal
1109 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1110 its offset. */
1111 int limit;
76ba9986 1112
711eedef
L		 1113 /* For 64bit, the limit is 3 bytes. */
1114 if (flag_code == CODE_64BIT
1115 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1116 limit = 3;
1117 else
1118 limit = 15;
1119 if (count < limit)
76bc74dc
L		 1120 memcpy (fragP->fr_literal + fragP->fr_fix,
1121 patt[count - 1], count);
1122 else
1123 {
1124 memcpy (fragP->fr_literal + fragP->fr_fix,
1125 jump_31, count);
1126 /* Adjust jump offset. */
1127 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1128 }
1129 }
1130 else
1131 {
1132 /* Maximum length of an instruction is 15 byte. If the
1133 padding is greater than 15 bytes and we don't use jump,
1134 we have to break it into smaller pieces. */
1135 int padding = count;
1136 while (padding > 15)
1137 {
1138 padding -= 15;
1139 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1140 patt [14], 15);
1141 }
1142
1143 if (padding)
1144 memcpy (fragP->fr_literal + fragP->fr_fix,
1145 patt [padding - 1], padding);
1146 }
ccc9c027 1147 }
33fef721 1148 fragP->fr_var = count;
252b5132
RH		 1149}
1150
c6fb90c8 1151static INLINE int
0dfbf9d7 1152operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1153{
0dfbf9d7 1154 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1155 {
1156 case 3:
0dfbf9d7 1157 if (x->array[2])
c6fb90c8
L		 1158 return 0;
1159 case 2:
0dfbf9d7 1160 if (x->array[1])
c6fb90c8
L		 1161 return 0;
1162 case 1:
0dfbf9d7 1163 return !x->array[0];
c6fb90c8
L		 1164 default:
1165 abort ();
1166 }
40fb9820
L		 1167}
1168
c6fb90c8 1169static INLINE void
0dfbf9d7 1170operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1171{
0dfbf9d7 1172 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1173 {
1174 case 3:
0dfbf9d7 1175 x->array[2] = v;
c6fb90c8 1176 case 2:
0dfbf9d7 1177 x->array[1] = v;
c6fb90c8 1178 case 1:
0dfbf9d7 1179 x->array[0] = v;
c6fb90c8
L		 1180 break;
1181 default:
1182 abort ();
1183 }
1184}
40fb9820 1185
c6fb90c8 1186static INLINE int
0dfbf9d7
L		 1187operand_type_equal (const union i386_operand_type *x,
1188 const union i386_operand_type *y)
c6fb90c8 1189{
0dfbf9d7 1190 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1191 {
1192 case 3:
0dfbf9d7 1193 if (x->array[2] != y->array[2])
c6fb90c8
L		 1194 return 0;
1195 case 2:
0dfbf9d7 1196 if (x->array[1] != y->array[1])
c6fb90c8
L		 1197 return 0;
1198 case 1:
0dfbf9d7 1199 return x->array[0] == y->array[0];
c6fb90c8
L		 1200 break;
1201 default:
1202 abort ();
1203 }
1204}
40fb9820 1205
0dfbf9d7
L		 1206static INLINE int
1207cpu_flags_all_zero (const union i386_cpu_flags *x)
1208{
1209 switch (ARRAY_SIZE(x->array))
1210 {
1211 case 3:
1212 if (x->array[2])
1213 return 0;
1214 case 2:
1215 if (x->array[1])
1216 return 0;
1217 case 1:
1218 return !x->array[0];
1219 default:
1220 abort ();
1221 }
1222}
1223
1224static INLINE void
1225cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1226{
1227 switch (ARRAY_SIZE(x->array))
1228 {
1229 case 3:
1230 x->array[2] = v;
1231 case 2:
1232 x->array[1] = v;
1233 case 1:
1234 x->array[0] = v;
1235 break;
1236 default:
1237 abort ();
1238 }
1239}
1240
1241static INLINE int
1242cpu_flags_equal (const union i386_cpu_flags *x,
1243 const union i386_cpu_flags *y)
1244{
1245 switch (ARRAY_SIZE(x->array))
1246 {
1247 case 3:
1248 if (x->array[2] != y->array[2])
1249 return 0;
1250 case 2:
1251 if (x->array[1] != y->array[1])
1252 return 0;
1253 case 1:
1254 return x->array[0] == y->array[0];
1255 break;
1256 default:
1257 abort ();
1258 }
1259}
c6fb90c8
L		 1260
1261static INLINE int
1262cpu_flags_check_cpu64 (i386_cpu_flags f)
1263{
1264 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1265 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1266}
1267
c6fb90c8
L		 1268static INLINE i386_cpu_flags
1269cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1270{
c6fb90c8
L		 1271 switch (ARRAY_SIZE (x.array))
1272 {
1273 case 3:
1274 x.array [2] &= y.array [2];
1275 case 2:
1276 x.array [1] &= y.array [1];
1277 case 1:
1278 x.array [0] &= y.array [0];
1279 break;
1280 default:
1281 abort ();
1282 }
1283 return x;
1284}
40fb9820 1285
c6fb90c8
L		 1286static INLINE i386_cpu_flags
1287cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1288{
c6fb90c8 1289 switch (ARRAY_SIZE (x.array))
40fb9820 1290 {
c6fb90c8
L		 1291 case 3:
1292 x.array [2] |= y.array [2];
1293 case 2:
1294 x.array [1] |= y.array [1];
1295 case 1:
1296 x.array [0] |= y.array [0];
40fb9820
L		 1297 break;
1298 default:
1299 abort ();
1300 }
40fb9820
L		 1301 return x;
1302}
1303
309d3373
JB		 1304static INLINE i386_cpu_flags
1305cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1306{
1307 switch (ARRAY_SIZE (x.array))
1308 {
1309 case 3:
1310 x.array [2] &= ~y.array [2];
1311 case 2:
1312 x.array [1] &= ~y.array [1];
1313 case 1:
1314 x.array [0] &= ~y.array [0];
1315 break;
1316 default:
1317 abort ();
1318 }
1319 return x;
1320}
1321
c0f3af97
L		 1322#define CPU_FLAGS_ARCH_MATCH 0x1
1323#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1324#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1325#define CPU_FLAGS_PCLMUL_MATCH 0x8
1326#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1327
a5ff0eb2 1328#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1329 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1330 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1331#define CPU_FLAGS_PERFECT_MATCH \
1332 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1333
1334/* Return CPU flags match bits. */
3629bb00 1335
40fb9820 1336static int
d3ce72d0 1337cpu_flags_match (const insn_template *t)
40fb9820 1338{
c0f3af97
L		 1339 i386_cpu_flags x = t->cpu_flags;
1340 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1341
1342 x.bitfield.cpu64 = 0;
1343 x.bitfield.cpuno64 = 0;
1344
0dfbf9d7 1345 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1346 {
1347 /* This instruction is available on all archs. */
1348 match |= CPU_FLAGS_32BIT_MATCH;
1349 }
3629bb00
L		 1350 else
1351 {
c0f3af97 1352 /* This instruction is available only on some archs. */
3629bb00
L		 1353 i386_cpu_flags cpu = cpu_arch_flags;
1354
1355 cpu.bitfield.cpu64 = 0;
1356 cpu.bitfield.cpuno64 = 0;
1357 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1358 if (!cpu_flags_all_zero (&cpu))
1359 {
a5ff0eb2
L		 1360 if (x.bitfield.cpuavx)
1361 {
ce2f5b3c 1362 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1363 if (cpu.bitfield.cpuavx)
1364 {
1365 /* Check SSE2AVX. */
1366 if (!t->opcode_modifier.sse2avx|| sse2avx)
1367 {
1368 match |= (CPU_FLAGS_ARCH_MATCH
1369 | CPU_FLAGS_AVX_MATCH);
1370 /* Check AES. */
1371 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1372 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1373 /* Check PCLMUL. */
1374 if (!x.bitfield.cpupclmul
1375 || cpu.bitfield.cpupclmul)
1376 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1377 }
1378 }
1379 else
1380 match |= CPU_FLAGS_ARCH_MATCH;
1381 }
1382 else
c0f3af97
L		 1383 match |= CPU_FLAGS_32BIT_MATCH;
1384 }
3629bb00 1385 }
c0f3af97 1386 return match;
40fb9820
L		 1387}
1388
c6fb90c8
L		 1389static INLINE i386_operand_type
1390operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1391{
c6fb90c8
L		 1392 switch (ARRAY_SIZE (x.array))
1393 {
1394 case 3:
1395 x.array [2] &= y.array [2];
1396 case 2:
1397 x.array [1] &= y.array [1];
1398 case 1:
1399 x.array [0] &= y.array [0];
1400 break;
1401 default:
1402 abort ();
1403 }
1404 return x;
40fb9820
L		 1405}
1406
c6fb90c8
L		 1407static INLINE i386_operand_type
1408operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1409{
c6fb90c8 1410 switch (ARRAY_SIZE (x.array))
40fb9820 1411 {
c6fb90c8
L		 1412 case 3:
1413 x.array [2] |= y.array [2];
1414 case 2:
1415 x.array [1] |= y.array [1];
1416 case 1:
1417 x.array [0] |= y.array [0];
40fb9820
L		 1418 break;
1419 default:
1420 abort ();
1421 }
c6fb90c8
L		 1422 return x;
1423}
40fb9820 1424
c6fb90c8
L		 1425static INLINE i386_operand_type
1426operand_type_xor (i386_operand_type x, i386_operand_type y)
1427{
1428 switch (ARRAY_SIZE (x.array))
1429 {
1430 case 3:
1431 x.array [2] ^= y.array [2];
1432 case 2:
1433 x.array [1] ^= y.array [1];
1434 case 1:
1435 x.array [0] ^= y.array [0];
1436 break;
1437 default:
1438 abort ();
1439 }
40fb9820
L		 1440 return x;
1441}
1442
1443static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1444static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1445static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1446static const i386_operand_type inoutportreg
1447 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1448static const i386_operand_type reg16_inoutportreg
1449 = OPERAND_TYPE_REG16_INOUTPORTREG;
1450static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1451static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1452static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1453static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1454static const i386_operand_type anydisp
1455 = OPERAND_TYPE_ANYDISP;
40fb9820 1456static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1457static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1458static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1459static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1460static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1461static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1462static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1463static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1464static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1465static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1466static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1467static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1468
1469enum operand_type
1470{
1471 reg,
40fb9820
L		 1472 imm,
1473 disp,
1474 anymem
1475};
1476
c6fb90c8 1477static INLINE int
40fb9820
L		 1478operand_type_check (i386_operand_type t, enum operand_type c)
1479{
1480 switch (c)
1481 {
1482 case reg:
1483 return (t.bitfield.reg8
1484 || t.bitfield.reg16
1485 || t.bitfield.reg32
1486 || t.bitfield.reg64);
1487
40fb9820
L		 1488 case imm:
1489 return (t.bitfield.imm8
1490 || t.bitfield.imm8s
1491 || t.bitfield.imm16
1492 || t.bitfield.imm32
1493 || t.bitfield.imm32s
1494 || t.bitfield.imm64);
1495
1496 case disp:
1497 return (t.bitfield.disp8
1498 || t.bitfield.disp16
1499 || t.bitfield.disp32
1500 || t.bitfield.disp32s
1501 || t.bitfield.disp64);
1502
1503 case anymem:
1504 return (t.bitfield.disp8
1505 || t.bitfield.disp16
1506 || t.bitfield.disp32
1507 || t.bitfield.disp32s
1508 || t.bitfield.disp64
1509 || t.bitfield.baseindex);
1510
1511 default:
1512 abort ();
1513 }
2cfe26b6
AM		 1514
1515 return 0;
40fb9820
L		 1516}
1517
5c07affc
L		 1518/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1519 operand J for instruction template T. */
1520
1521static INLINE int
d3ce72d0 1522match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1523{
1524 return !((i.types[j].bitfield.byte
1525 && !t->operand_types[j].bitfield.byte)
1526 || (i.types[j].bitfield.word
1527 && !t->operand_types[j].bitfield.word)
1528 || (i.types[j].bitfield.dword
1529 && !t->operand_types[j].bitfield.dword)
1530 || (i.types[j].bitfield.qword
1531 && !t->operand_types[j].bitfield.qword));
1532}
1533
1534/* Return 1 if there is no conflict in any size on operand J for
1535 instruction template T. */
1536
1537static INLINE int
d3ce72d0 1538match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1539{
1540 return (match_reg_size (t, j)
1541 && !((i.types[j].bitfield.unspecified
1542 && !t->operand_types[j].bitfield.unspecified)
1543 || (i.types[j].bitfield.fword
1544 && !t->operand_types[j].bitfield.fword)
1545 || (i.types[j].bitfield.tbyte
1546 && !t->operand_types[j].bitfield.tbyte)
1547 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1548 && !t->operand_types[j].bitfield.xmmword)
1549 || (i.types[j].bitfield.ymmword
1550 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1551}
1552
1553/* Return 1 if there is no size conflict on any operands for
1554 instruction template T. */
1555
1556static INLINE int
d3ce72d0 1557operand_size_match (const insn_template *t)
5c07affc
L		 1558{
1559 unsigned int j;
1560 int match = 1;
1561
1562 /* Don't check jump instructions. */
1563 if (t->opcode_modifier.jump
1564 || t->opcode_modifier.jumpbyte
1565 || t->opcode_modifier.jumpdword
1566 || t->opcode_modifier.jumpintersegment)
1567 return match;
1568
1569 /* Check memory and accumulator operand size. */
1570 for (j = 0; j < i.operands; j++)
1571 {
1572 if (t->operand_types[j].bitfield.anysize)
1573 continue;
1574
1575 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1576 {
1577 match = 0;
1578 break;
1579 }
1580
1581 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1582 {
1583 match = 0;
1584 break;
1585 }
1586 }
1587
891edac4 1588 if (match)
5c07affc 1589 return match;
891edac4
L		 1590 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1591 {
1592mismatch:
86e026a4 1593 i.error = operand_size_mismatch;
891edac4
L		 1594 return 0;
1595 }
5c07affc
L		 1596
1597 /* Check reverse. */
9c2799c2 1598 gas_assert (i.operands == 2);
5c07affc
L		 1599
1600 match = 1;
1601 for (j = 0; j < 2; j++)
1602 {
1603 if (t->operand_types[j].bitfield.acc
1604 && !match_reg_size (t, j ? 0 : 1))
891edac4 1605 goto mismatch;
5c07affc
L		 1606
1607 if (i.types[j].bitfield.mem
1608 && !match_mem_size (t, j ? 0 : 1))
891edac4 1609 goto mismatch;
5c07affc
L		 1610 }
1611
1612 return match;
1613}
1614
c6fb90c8 1615static INLINE int
40fb9820
L		 1616operand_type_match (i386_operand_type overlap,
1617 i386_operand_type given)
1618{
1619 i386_operand_type temp = overlap;
1620
1621 temp.bitfield.jumpabsolute = 0;
7d5e4556 1622 temp.bitfield.unspecified = 0;
5c07affc
L		 1623 temp.bitfield.byte = 0;
1624 temp.bitfield.word = 0;
1625 temp.bitfield.dword = 0;
1626 temp.bitfield.fword = 0;
1627 temp.bitfield.qword = 0;
1628 temp.bitfield.tbyte = 0;
1629 temp.bitfield.xmmword = 0;
c0f3af97 1630 temp.bitfield.ymmword = 0;
0dfbf9d7 1631 if (operand_type_all_zero (&temp))
891edac4 1632 goto mismatch;
40fb9820 1633
891edac4
L		 1634 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1635 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1636 return 1;
1637
1638mismatch:
a65babc9 1639 i.error = operand_type_mismatch;
891edac4 1640 return 0;
40fb9820
L		 1641}
1642
7d5e4556 1643/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1644 unless the expected operand type register overlap is null.
1645 Note that Acc in a template matches every size of reg. */
1646
c6fb90c8 1647static INLINE int
40fb9820
L		 1648operand_type_register_match (i386_operand_type m0,
1649 i386_operand_type g0,
1650 i386_operand_type t0,
1651 i386_operand_type m1,
1652 i386_operand_type g1,
1653 i386_operand_type t1)
1654{
1655 if (!operand_type_check (g0, reg))
1656 return 1;
1657
1658 if (!operand_type_check (g1, reg))
1659 return 1;
1660
1661 if (g0.bitfield.reg8 == g1.bitfield.reg8
1662 && g0.bitfield.reg16 == g1.bitfield.reg16
1663 && g0.bitfield.reg32 == g1.bitfield.reg32
1664 && g0.bitfield.reg64 == g1.bitfield.reg64)
1665 return 1;
1666
1667 if (m0.bitfield.acc)
1668 {
1669 t0.bitfield.reg8 = 1;
1670 t0.bitfield.reg16 = 1;
1671 t0.bitfield.reg32 = 1;
1672 t0.bitfield.reg64 = 1;
1673 }
1674
1675 if (m1.bitfield.acc)
1676 {
1677 t1.bitfield.reg8 = 1;
1678 t1.bitfield.reg16 = 1;
1679 t1.bitfield.reg32 = 1;
1680 t1.bitfield.reg64 = 1;
1681 }
1682
891edac4
L		 1683 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1684 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1685 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1686 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1687 return 1;
1688
a65babc9 1689 i.error = register_type_mismatch;
891edac4
L		 1690
1691 return 0;
40fb9820
L		 1692}
1693
252b5132 1694static INLINE unsigned int
40fb9820 1695mode_from_disp_size (i386_operand_type t)
252b5132 1696{
40fb9820
L		 1697 if (t.bitfield.disp8)
1698 return 1;
1699 else if (t.bitfield.disp16
1700 || t.bitfield.disp32
1701 || t.bitfield.disp32s)
1702 return 2;
1703 else
1704 return 0;
252b5132
RH		 1705}
1706
1707static INLINE int
e3bb37b5 1708fits_in_signed_byte (offsetT num)
252b5132
RH		 1709{
1710 return (num >= -128) && (num <= 127);
47926f60 1711}
252b5132
RH		 1712
1713static INLINE int
e3bb37b5 1714fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1715{
1716 return (num & 0xff) == num;
47926f60 1717}
252b5132
RH		 1718
1719static INLINE int
e3bb37b5 1720fits_in_unsigned_word (offsetT num)
252b5132
RH		 1721{
1722 return (num & 0xffff) == num;
47926f60 1723}
252b5132
RH		 1724
1725static INLINE int
e3bb37b5 1726fits_in_signed_word (offsetT num)
252b5132
RH		 1727{
1728 return (-32768 <= num) && (num <= 32767);
47926f60 1729}
2a962e6d 1730
3e73aa7c 1731static INLINE int
e3bb37b5 1732fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1733{
1734#ifndef BFD64
1735 return 1;
1736#else
1737 return (!(((offsetT) -1 << 31) & num)
1738 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1739#endif
1740} /* fits_in_signed_long() */
2a962e6d 1741
3e73aa7c 1742static INLINE int
e3bb37b5 1743fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1744{
1745#ifndef BFD64
1746 return 1;
1747#else
1748 return (num & (((offsetT) 2 << 31) - 1)) == num;
1749#endif
1750} /* fits_in_unsigned_long() */
252b5132 1751
a683cc34
SP		 1752static INLINE int
1753fits_in_imm4 (offsetT num)
1754{
1755 return (num & 0xf) == num;
1756}
1757
40fb9820 1758static i386_operand_type
e3bb37b5 1759smallest_imm_type (offsetT num)
252b5132 1760{
40fb9820 1761 i386_operand_type t;
7ab9ffdd 1762
0dfbf9d7 1763 operand_type_set (&t, 0);
40fb9820
L		 1764 t.bitfield.imm64 = 1;
1765
1766 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1767 {
1768 /* This code is disabled on the 486 because all the Imm1 forms
1769 in the opcode table are slower on the i486. They're the
1770 versions with the implicitly specified single-position
1771 displacement, which has another syntax if you really want to
1772 use that form. */
40fb9820
L		 1773 t.bitfield.imm1 = 1;
1774 t.bitfield.imm8 = 1;
1775 t.bitfield.imm8s = 1;
1776 t.bitfield.imm16 = 1;
1777 t.bitfield.imm32 = 1;
1778 t.bitfield.imm32s = 1;
1779 }
1780 else if (fits_in_signed_byte (num))
1781 {
1782 t.bitfield.imm8 = 1;
1783 t.bitfield.imm8s = 1;
1784 t.bitfield.imm16 = 1;
1785 t.bitfield.imm32 = 1;
1786 t.bitfield.imm32s = 1;
1787 }
1788 else if (fits_in_unsigned_byte (num))
1789 {
1790 t.bitfield.imm8 = 1;
1791 t.bitfield.imm16 = 1;
1792 t.bitfield.imm32 = 1;
1793 t.bitfield.imm32s = 1;
1794 }
1795 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1796 {
1797 t.bitfield.imm16 = 1;
1798 t.bitfield.imm32 = 1;
1799 t.bitfield.imm32s = 1;
1800 }
1801 else if (fits_in_signed_long (num))
1802 {
1803 t.bitfield.imm32 = 1;
1804 t.bitfield.imm32s = 1;
1805 }
1806 else if (fits_in_unsigned_long (num))
1807 t.bitfield.imm32 = 1;
1808
1809 return t;
47926f60 1810}
252b5132 1811
847f7ad4 1812static offsetT
e3bb37b5 1813offset_in_range (offsetT val, int size)
847f7ad4 1814{
508866be 1815 addressT mask;
ba2adb93 1816
847f7ad4
AM		 1817 switch (size)
1818 {
508866be
L		 1819 case 1: mask = ((addressT) 1 << 8) - 1; break;
1820 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1821 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1822#ifdef BFD64
1823 case 8: mask = ((addressT) 2 << 63) - 1; break;
1824#endif
47926f60 1825 default: abort ();
847f7ad4
AM		 1826 }
1827
9de868bf
L		 1828#ifdef BFD64
1829 /* If BFD64, sign extend val for 32bit address mode. */
1830 if (flag_code != CODE_64BIT
1831 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1832 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1833 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1834#endif
ba2adb93 1835
47926f60 1836 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1837 {
1838 char buf1[40], buf2[40];
1839
1840 sprint_value (buf1, val);
1841 sprint_value (buf2, val & mask);
1842 as_warn (_("%s shortened to %s"), buf1, buf2);
1843 }
1844 return val & mask;
1845}
1846
c32fa91d
L		 1847enum PREFIX_GROUP
1848{
1849 PREFIX_EXIST = 0,
1850 PREFIX_LOCK,
1851 PREFIX_REP,
1852 PREFIX_OTHER
1853};
1854
1855/* Returns
1856 a. PREFIX_EXIST if attempting to add a prefix where one from the
1857 same class already exists.
1858 b. PREFIX_LOCK if lock prefix is added.
1859 c. PREFIX_REP if rep/repne prefix is added.
1860 d. PREFIX_OTHER if other prefix is added.
1861 */
1862
1863static enum PREFIX_GROUP
e3bb37b5 1864add_prefix (unsigned int prefix)
252b5132 1865{
c32fa91d 1866 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1867 unsigned int q;
252b5132 1868
29b0f896
AM		 1869 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1870 && flag_code == CODE_64BIT)
b1905489 1871 {
161a04f6
L		 1872 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1873 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1874 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1875 ret = PREFIX_EXIST;
b1905489
JB		 1876 q = REX_PREFIX;
1877 }
3e73aa7c 1878 else
b1905489
JB		 1879 {
1880 switch (prefix)
1881 {
1882 default:
1883 abort ();
1884
1885 case CS_PREFIX_OPCODE:
1886 case DS_PREFIX_OPCODE:
1887 case ES_PREFIX_OPCODE:
1888 case FS_PREFIX_OPCODE:
1889 case GS_PREFIX_OPCODE:
1890 case SS_PREFIX_OPCODE:
1891 q = SEG_PREFIX;
1892 break;
1893
1894 case REPNE_PREFIX_OPCODE:
1895 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1896 q = REP_PREFIX;
1897 ret = PREFIX_REP;
1898 break;
1899
b1905489 1900 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1901 q = LOCK_PREFIX;
1902 ret = PREFIX_LOCK;
b1905489
JB		 1903 break;
1904
1905 case FWAIT_OPCODE:
1906 q = WAIT_PREFIX;
1907 break;
1908
1909 case ADDR_PREFIX_OPCODE:
1910 q = ADDR_PREFIX;
1911 break;
1912
1913 case DATA_PREFIX_OPCODE:
1914 q = DATA_PREFIX;
1915 break;
1916 }
1917 if (i.prefix[q] != 0)
c32fa91d 1918 ret = PREFIX_EXIST;
b1905489 1919 }
252b5132 1920
b1905489 1921 if (ret)
252b5132 1922 {
b1905489
JB		 1923 if (!i.prefix[q])
1924 ++i.prefixes;
1925 i.prefix[q] |= prefix;
252b5132 1926 }
b1905489
JB		 1927 else
1928 as_bad (_("same type of prefix used twice"));
252b5132 1929
252b5132
RH		 1930 return ret;
1931}
1932
1933static void
78f12dd3 1934update_code_flag (int value, int check)
eecb386c 1935{
78f12dd3
L		 1936 PRINTF_LIKE ((*as_error));
1937
1e9cc1c2 1938 flag_code = (enum flag_code) value;
40fb9820
L		 1939 if (flag_code == CODE_64BIT)
1940 {
1941 cpu_arch_flags.bitfield.cpu64 = 1;
1942 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1943 }
1944 else
1945 {
1946 cpu_arch_flags.bitfield.cpu64 = 0;
1947 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1948 }
1949 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1950 {
78f12dd3
L		 1951 if (check)
1952 as_error = as_fatal;
1953 else
1954 as_error = as_bad;
1955 (*as_error) (_("64bit mode not supported on `%s'."),
1956 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1957 }
40fb9820 1958 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 1959 {
78f12dd3
L		 1960 if (check)
1961 as_error = as_fatal;
1962 else
1963 as_error = as_bad;
1964 (*as_error) (_("32bit mode not supported on `%s'."),
1965 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1966 }
eecb386c
AM		 1967 stackop_size = '\0';
1968}
1969
78f12dd3
L		 1970static void
1971set_code_flag (int value)
1972{
1973 update_code_flag (value, 0);
1974}
1975
eecb386c 1976static void
e3bb37b5 1977set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1978{
1e9cc1c2 1979 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1980 if (flag_code != CODE_16BIT)
1981 abort ();
1982 cpu_arch_flags.bitfield.cpu64 = 0;
1983 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1984 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1985}
1986
1987static void
e3bb37b5 1988set_intel_syntax (int syntax_flag)
252b5132
RH		 1989{
1990 /* Find out if register prefixing is specified. */
1991 int ask_naked_reg = 0;
1992
1993 SKIP_WHITESPACE ();
29b0f896 1994 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1995 {
1996 char *string = input_line_pointer;
1997 int e = get_symbol_end ();
1998
47926f60 1999 if (strcmp (string, "prefix") == 0)
252b5132 2000 ask_naked_reg = 1;
47926f60 2001 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2002 ask_naked_reg = -1;
2003 else
d0b47220 2004 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2005 *input_line_pointer = e;
2006 }
2007 demand_empty_rest_of_line ();
c3332e24 2008
252b5132
RH		 2009 intel_syntax = syntax_flag;
2010
2011 if (ask_naked_reg == 0)
f86103b7
AM		 2012 allow_naked_reg = (intel_syntax
2013 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2014 else
2015 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2016
ee86248c 2017 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2018
e4a3b5a4 2019 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2020 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2021 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2022}
2023
1efbbeb4
L		 2024static void
2025set_intel_mnemonic (int mnemonic_flag)
2026{
e1d4d893 2027 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2028}
2029
db51cc60
L		 2030static void
2031set_allow_index_reg (int flag)
2032{
2033 allow_index_reg = flag;
2034}
2035
cb19c032
L		 2036static void
2037set_sse_check (int dummy ATTRIBUTE_UNUSED)
2038{
2039 SKIP_WHITESPACE ();
2040
2041 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2042 {
2043 char *string = input_line_pointer;
2044 int e = get_symbol_end ();
2045
2046 if (strcmp (string, "none") == 0)
2047 sse_check = sse_check_none;
2048 else if (strcmp (string, "warning") == 0)
2049 sse_check = sse_check_warning;
2050 else if (strcmp (string, "error") == 0)
2051 sse_check = sse_check_error;
2052 else
2053 as_bad (_("bad argument to sse_check directive."));
2054 *input_line_pointer = e;
2055 }
2056 else
2057 as_bad (_("missing argument for sse_check directive"));
2058
2059 demand_empty_rest_of_line ();
2060}
2061
8a9036a4
L		 2062static void
2063check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2064 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2065{
2066#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2067 static const char *arch;
2068
2069 /* Intel LIOM is only supported on ELF. */
2070 if (!IS_ELF)
2071 return;
2072
2073 if (!arch)
2074 {
2075 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2076 use default_arch. */
2077 arch = cpu_arch_name;
2078 if (!arch)
2079 arch = default_arch;
2080 }
2081
3632d14b 2082 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2083 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2084 || new_flag.bitfield.cpul1om)
8a9036a4 2085 return;
76ba9986 2086
8a9036a4
L		 2087 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2088#endif
2089}
2090
e413e4e9 2091static void
e3bb37b5 2092set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2093{
47926f60 2094 SKIP_WHITESPACE ();
e413e4e9 2095
29b0f896 2096 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2097 {
2098 char *string = input_line_pointer;
2099 int e = get_symbol_end ();
91d6fa6a 2100 unsigned int j;
40fb9820 2101 i386_cpu_flags flags;
e413e4e9 2102
91d6fa6a 2103 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2104 {
91d6fa6a 2105 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2106 {
91d6fa6a 2107 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2108
5c6af06e
JB		 2109 if (*string != '.')
2110 {
91d6fa6a 2111 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2112 cpu_sub_arch_name = NULL;
91d6fa6a 2113 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2114 if (flag_code == CODE_64BIT)
2115 {
2116 cpu_arch_flags.bitfield.cpu64 = 1;
2117 cpu_arch_flags.bitfield.cpuno64 = 0;
2118 }
2119 else
2120 {
2121 cpu_arch_flags.bitfield.cpu64 = 0;
2122 cpu_arch_flags.bitfield.cpuno64 = 1;
2123 }
91d6fa6a
NC		 2124 cpu_arch_isa = cpu_arch[j].type;
2125 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2126 if (!cpu_arch_tune_set)
2127 {
2128 cpu_arch_tune = cpu_arch_isa;
2129 cpu_arch_tune_flags = cpu_arch_isa_flags;
2130 }
5c6af06e
JB		 2131 break;
2132 }
40fb9820 2133
309d3373
JB		 2134 if (strncmp (string + 1, "no", 2))
2135 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2136 cpu_arch[j].flags);
309d3373
JB		 2137 else
2138 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 2139 cpu_arch[j].flags);
0dfbf9d7 2140 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2141 {
6305a203
L		 2142 if (cpu_sub_arch_name)
2143 {
2144 char *name = cpu_sub_arch_name;
2145 cpu_sub_arch_name = concat (name,
91d6fa6a 2146 cpu_arch[j].name,
1bf57e9f 2147 (const char *) NULL);
6305a203
L		 2148 free (name);
2149 }
2150 else
91d6fa6a 2151 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2152 cpu_arch_flags = flags;
5c6af06e
JB		 2153 }
2154 *input_line_pointer = e;
2155 demand_empty_rest_of_line ();
2156 return;
e413e4e9
AM		 2157 }
2158 }
91d6fa6a 2159 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2160 as_bad (_("no such architecture: `%s'"), string);
2161
2162 *input_line_pointer = e;
2163 }
2164 else
2165 as_bad (_("missing cpu architecture"));
2166
fddf5b5b
AM		 2167 no_cond_jump_promotion = 0;
2168 if (*input_line_pointer == ','
29b0f896 2169 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2170 {
2171 char *string = ++input_line_pointer;
2172 int e = get_symbol_end ();
2173
2174 if (strcmp (string, "nojumps") == 0)
2175 no_cond_jump_promotion = 1;
2176 else if (strcmp (string, "jumps") == 0)
2177 ;
2178 else
2179 as_bad (_("no such architecture modifier: `%s'"), string);
2180
2181 *input_line_pointer = e;
2182 }
2183
e413e4e9
AM		 2184 demand_empty_rest_of_line ();
2185}
2186
8a9036a4
L		 2187enum bfd_architecture
2188i386_arch (void)
2189{
3632d14b 2190 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2191 {
2192 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2193 || flag_code != CODE_64BIT)
2194 as_fatal (_("Intel L1OM is 64bit ELF only"));
2195 return bfd_arch_l1om;
2196 }
2197 else
2198 return bfd_arch_i386;
2199}
2200
b9d79e03
JH		 2201unsigned long
2202i386_mach ()
2203{
2204 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2205 {
3632d14b 2206 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2207 {
2208 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2209 as_fatal (_("Intel L1OM is 64bit ELF only"));
2210 return bfd_mach_l1om;
2211 }
2212 else
2213 return bfd_mach_x86_64;
2214 }
b9d79e03
JH		 2215 else if (!strcmp (default_arch, "i386"))
2216 return bfd_mach_i386_i386;
2217 else
2218 as_fatal (_("Unknown architecture"));
2219}
b9d79e03 2220\f
252b5132
RH		 2221void
2222md_begin ()
2223{
2224 const char *hash_err;
2225
47926f60 2226 /* Initialize op_hash hash table. */
252b5132
RH		 2227 op_hash = hash_new ();
2228
2229 {
d3ce72d0 2230 const insn_template *optab;
29b0f896 2231 templates *core_optab;
252b5132 2232
47926f60
KH		 2233 /* Setup for loop. */
2234 optab = i386_optab;
252b5132
RH		 2235 core_optab = (templates *) xmalloc (sizeof (templates));
2236 core_optab->start = optab;
2237
2238 while (1)
2239 {
2240 ++optab;
2241 if (optab->name == NULL
2242 || strcmp (optab->name, (optab - 1)->name) != 0)
2243 {
2244 /* different name --> ship out current template list;
47926f60 2245 add to hash table; & begin anew. */
252b5132
RH		 2246 core_optab->end = optab;
2247 hash_err = hash_insert (op_hash,
2248 (optab - 1)->name,
5a49b8ac 2249 (void *) core_optab);
252b5132
RH		 2250 if (hash_err)
2251 {
252b5132
RH		 2252 as_fatal (_("Internal Error: Can't hash %s: %s"),
2253 (optab - 1)->name,
2254 hash_err);
2255 }
2256 if (optab->name == NULL)
2257 break;
2258 core_optab = (templates *) xmalloc (sizeof (templates));
2259 core_optab->start = optab;
2260 }
2261 }
2262 }
2263
47926f60 2264 /* Initialize reg_hash hash table. */
252b5132
RH		 2265 reg_hash = hash_new ();
2266 {
29b0f896 2267 const reg_entry *regtab;
c3fe08fa 2268 unsigned int regtab_size = i386_regtab_size;
252b5132 2269
c3fe08fa 2270 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2271 {
5a49b8ac 2272 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2273 if (hash_err)
3e73aa7c
JH		 2274 as_fatal (_("Internal Error: Can't hash %s: %s"),
2275 regtab->reg_name,
2276 hash_err);
252b5132
RH		 2277 }
2278 }
2279
47926f60 2280 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2281 {
29b0f896
AM		 2282 int c;
2283 char *p;
252b5132
RH		 2284
2285 for (c = 0; c < 256; c++)
2286 {
3882b010 2287 if (ISDIGIT (c))
252b5132
RH		 2288 {
2289 digit_chars[c] = c;
2290 mnemonic_chars[c] = c;
2291 register_chars[c] = c;
2292 operand_chars[c] = c;
2293 }
3882b010 2294 else if (ISLOWER (c))
252b5132
RH		 2295 {
2296 mnemonic_chars[c] = c;
2297 register_chars[c] = c;
2298 operand_chars[c] = c;
2299 }
3882b010 2300 else if (ISUPPER (c))
252b5132 2301 {
3882b010 2302 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2303 register_chars[c] = mnemonic_chars[c];
2304 operand_chars[c] = c;
2305 }
2306
3882b010 2307 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2308 identifier_chars[c] = c;
2309 else if (c >= 128)
2310 {
2311 identifier_chars[c] = c;
2312 operand_chars[c] = c;
2313 }
2314 }
2315
2316#ifdef LEX_AT
2317 identifier_chars['@'] = '@';
32137342
NC		 2318#endif
2319#ifdef LEX_QM
2320 identifier_chars['?'] = '?';
2321 operand_chars['?'] = '?';
252b5132 2322#endif
252b5132 2323 digit_chars['-'] = '-';
c0f3af97 2324 mnemonic_chars['_'] = '_';
791fe849 2325 mnemonic_chars['-'] = '-';
0003779b 2326 mnemonic_chars['.'] = '.';
252b5132
RH		 2327 identifier_chars['_'] = '_';
2328 identifier_chars['.'] = '.';
2329
2330 for (p = operand_special_chars; *p != '\0'; p++)
2331 operand_chars[(unsigned char) *p] = *p;
2332 }
2333
2334#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2335 if (IS_ELF)
252b5132
RH		 2336 {
2337 record_alignment (text_section, 2);
2338 record_alignment (data_section, 2);
2339 record_alignment (bss_section, 2);
2340 }
2341#endif
a4447b93
RH		 2342
2343 if (flag_code == CODE_64BIT)
2344 {
2345 x86_dwarf2_return_column = 16;
2346 x86_cie_data_alignment = -8;
2347 }
2348 else
2349 {
2350 x86_dwarf2_return_column = 8;
2351 x86_cie_data_alignment = -4;
2352 }
252b5132
RH		 2353}
2354
2355void
e3bb37b5 2356i386_print_statistics (FILE *file)
252b5132
RH		 2357{
2358 hash_print_statistics (file, "i386 opcode", op_hash);
2359 hash_print_statistics (file, "i386 register", reg_hash);
2360}
2361\f
252b5132
RH		 2362#ifdef DEBUG386
2363
ce8a8b2f 2364/* Debugging routines for md_assemble. */
d3ce72d0 2365static void pte (insn_template *);
40fb9820 2366static void pt (i386_operand_type);
e3bb37b5
L		 2367static void pe (expressionS *);
2368static void ps (symbolS *);
252b5132
RH		 2369
2370static void
e3bb37b5 2371pi (char *line, i386_insn *x)
252b5132 2372{
09137c09 2373 unsigned int j;
252b5132
RH		 2374
2375 fprintf (stdout, "%s: template ", line);
2376 pte (&x->tm);
09f131f2
JH		 2377 fprintf (stdout, " address: base %s index %s scale %x\n",
2378 x->base_reg ? x->base_reg->reg_name : "none",
2379 x->index_reg ? x->index_reg->reg_name : "none",
2380 x->log2_scale_factor);
2381 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2382 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2383 fprintf (stdout, " sib: base %x index %x scale %x\n",
2384 x->sib.base, x->sib.index, x->sib.scale);
2385 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2386 (x->rex & REX_W) != 0,
2387 (x->rex & REX_R) != 0,
2388 (x->rex & REX_X) != 0,
2389 (x->rex & REX_B) != 0);
09137c09 2390 for (j = 0; j < x->operands; j++)
252b5132 2391 {
09137c09
SP		 2392 fprintf (stdout, " #%d: ", j + 1);
2393 pt (x->types[j]);
252b5132 2394 fprintf (stdout, "\n");
09137c09
SP		 2395 if (x->types[j].bitfield.reg8
2396 || x->types[j].bitfield.reg16
2397 || x->types[j].bitfield.reg32
2398 || x->types[j].bitfield.reg64
2399 || x->types[j].bitfield.regmmx
2400 || x->types[j].bitfield.regxmm
2401 || x->types[j].bitfield.regymm
2402 || x->types[j].bitfield.sreg2
2403 || x->types[j].bitfield.sreg3
2404 || x->types[j].bitfield.control
2405 || x->types[j].bitfield.debug
2406 || x->types[j].bitfield.test)
2407 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2408 if (operand_type_check (x->types[j], imm))
2409 pe (x->op[j].imms);
2410 if (operand_type_check (x->types[j], disp))
2411 pe (x->op[j].disps);
252b5132
RH		 2412 }
2413}
2414
2415static void
d3ce72d0 2416pte (insn_template *t)
252b5132 2417{
09137c09 2418 unsigned int j;
252b5132 2419 fprintf (stdout, " %d operands ", t->operands);
47926f60 2420 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2421 if (t->extension_opcode != None)
2422 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2423 if (t->opcode_modifier.d)
252b5132 2424 fprintf (stdout, "D");
40fb9820 2425 if (t->opcode_modifier.w)
252b5132
RH		 2426 fprintf (stdout, "W");
2427 fprintf (stdout, "\n");
09137c09 2428 for (j = 0; j < t->operands; j++)
252b5132 2429 {
09137c09
SP		 2430 fprintf (stdout, " #%d type ", j + 1);
2431 pt (t->operand_types[j]);
252b5132
RH		 2432 fprintf (stdout, "\n");
2433 }
2434}
2435
2436static void
e3bb37b5 2437pe (expressionS *e)
252b5132 2438{
24eab124 2439 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2440 fprintf (stdout, " add_number %ld (%lx)\n",
2441 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2442 if (e->X_add_symbol)
2443 {
2444 fprintf (stdout, " add_symbol ");
2445 ps (e->X_add_symbol);
2446 fprintf (stdout, "\n");
2447 }
2448 if (e->X_op_symbol)
2449 {
2450 fprintf (stdout, " op_symbol ");
2451 ps (e->X_op_symbol);
2452 fprintf (stdout, "\n");
2453 }
2454}
2455
2456static void
e3bb37b5 2457ps (symbolS *s)
252b5132
RH		 2458{
2459 fprintf (stdout, "%s type %s%s",
2460 S_GET_NAME (s),
2461 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2462 segment_name (S_GET_SEGMENT (s)));
2463}
2464
7b81dfbb 2465static struct type_name
252b5132 2466 {
40fb9820
L		 2467 i386_operand_type mask;
2468 const char *name;
252b5132 2469 }
7b81dfbb 2470const type_names[] =
252b5132 2471{
40fb9820
L		 2472 { OPERAND_TYPE_REG8, "r8" },
2473 { OPERAND_TYPE_REG16, "r16" },
2474 { OPERAND_TYPE_REG32, "r32" },
2475 { OPERAND_TYPE_REG64, "r64" },
2476 { OPERAND_TYPE_IMM8, "i8" },
2477 { OPERAND_TYPE_IMM8, "i8s" },
2478 { OPERAND_TYPE_IMM16, "i16" },
2479 { OPERAND_TYPE_IMM32, "i32" },
2480 { OPERAND_TYPE_IMM32S, "i32s" },
2481 { OPERAND_TYPE_IMM64, "i64" },
2482 { OPERAND_TYPE_IMM1, "i1" },
2483 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2484 { OPERAND_TYPE_DISP8, "d8" },
2485 { OPERAND_TYPE_DISP16, "d16" },
2486 { OPERAND_TYPE_DISP32, "d32" },
2487 { OPERAND_TYPE_DISP32S, "d32s" },
2488 { OPERAND_TYPE_DISP64, "d64" },
2489 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2490 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2491 { OPERAND_TYPE_CONTROL, "control reg" },
2492 { OPERAND_TYPE_TEST, "test reg" },
2493 { OPERAND_TYPE_DEBUG, "debug reg" },
2494 { OPERAND_TYPE_FLOATREG, "FReg" },
2495 { OPERAND_TYPE_FLOATACC, "FAcc" },
2496 { OPERAND_TYPE_SREG2, "SReg2" },
2497 { OPERAND_TYPE_SREG3, "SReg3" },
2498 { OPERAND_TYPE_ACC, "Acc" },
2499 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2500 { OPERAND_TYPE_REGMMX, "rMMX" },
2501 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2502 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2503 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2504};
2505
2506static void
40fb9820 2507pt (i386_operand_type t)
252b5132 2508{
40fb9820 2509 unsigned int j;
c6fb90c8 2510 i386_operand_type a;
252b5132 2511
40fb9820 2512 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2513 {
2514 a = operand_type_and (t, type_names[j].mask);
0349dc08 2515 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2516 fprintf (stdout, "%s, ", type_names[j].name);
2517 }
252b5132
RH		 2518 fflush (stdout);
2519}
2520
2521#endif /* DEBUG386 */
2522\f
252b5132 2523static bfd_reloc_code_real_type
3956db08 2524reloc (unsigned int size,
64e74474
AM		 2525 int pcrel,
2526 int sign,
2527 bfd_reloc_code_real_type other)
252b5132 2528{
47926f60 2529 if (other != NO_RELOC)
3956db08 2530 {
91d6fa6a 2531 reloc_howto_type *rel;
3956db08
JB		 2532
2533 if (size == 8)
2534 switch (other)
2535 {
64e74474
AM		 2536 case BFD_RELOC_X86_64_GOT32:
2537 return BFD_RELOC_X86_64_GOT64;
2538 break;
2539 case BFD_RELOC_X86_64_PLTOFF64:
2540 return BFD_RELOC_X86_64_PLTOFF64;
2541 break;
2542 case BFD_RELOC_X86_64_GOTPC32:
2543 other = BFD_RELOC_X86_64_GOTPC64;
2544 break;
2545 case BFD_RELOC_X86_64_GOTPCREL:
2546 other = BFD_RELOC_X86_64_GOTPCREL64;
2547 break;
2548 case BFD_RELOC_X86_64_TPOFF32:
2549 other = BFD_RELOC_X86_64_TPOFF64;
2550 break;
2551 case BFD_RELOC_X86_64_DTPOFF32:
2552 other = BFD_RELOC_X86_64_DTPOFF64;
2553 break;
2554 default:
2555 break;
3956db08 2556 }
e05278af
JB		 2557
2558 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2559 if (size == 4 && flag_code != CODE_64BIT)
2560 sign = -1;
2561
91d6fa6a
NC		 2562 rel = bfd_reloc_type_lookup (stdoutput, other);
2563 if (!rel)
3956db08 2564 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2565 else if (size != bfd_get_reloc_size (rel))
3956db08 2566 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2567 bfd_get_reloc_size (rel),
3956db08 2568 size);
91d6fa6a 2569 else if (pcrel && !rel->pc_relative)
3956db08 2570 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2571 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2572 && !sign)
91d6fa6a 2573 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2574 && sign > 0))
3956db08
JB		 2575 as_bad (_("relocated field and relocation type differ in signedness"));
2576 else
2577 return other;
2578 return NO_RELOC;
2579 }
252b5132
RH		 2580
2581 if (pcrel)
2582 {
3e73aa7c 2583 if (!sign)
3956db08 2584 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2585 switch (size)
2586 {
2587 case 1: return BFD_RELOC_8_PCREL;
2588 case 2: return BFD_RELOC_16_PCREL;
2589 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2590 case 8: return BFD_RELOC_64_PCREL;
252b5132 2591 }
3956db08 2592 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2593 }
2594 else
2595 {
3956db08 2596 if (sign > 0)
e5cb08ac 2597 switch (size)
3e73aa7c
JH		 2598 {
2599 case 4: return BFD_RELOC_X86_64_32S;
2600 }
2601 else
2602 switch (size)
2603 {
2604 case 1: return BFD_RELOC_8;
2605 case 2: return BFD_RELOC_16;
2606 case 4: return BFD_RELOC_32;
2607 case 8: return BFD_RELOC_64;
2608 }
3956db08
JB		 2609 as_bad (_("cannot do %s %u byte relocation"),
2610 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2611 }
2612
0cc9e1d3 2613 return NO_RELOC;
252b5132
RH		 2614}
2615
47926f60
KH		 2616/* Here we decide which fixups can be adjusted to make them relative to
2617 the beginning of the section instead of the symbol. Basically we need
2618 to make sure that the dynamic relocations are done correctly, so in
2619 some cases we force the original symbol to be used. */
2620
252b5132 2621int
e3bb37b5 2622tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2623{
6d249963 2624#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2625 if (!IS_ELF)
31312f95
AM		 2626 return 1;
2627
a161fe53
AM		 2628 /* Don't adjust pc-relative references to merge sections in 64-bit
2629 mode. */
2630 if (use_rela_relocations
2631 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2632 && fixP->fx_pcrel)
252b5132 2633 return 0;
31312f95 2634
8d01d9a9
AJ		 2635 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2636 and changed later by validate_fix. */
2637 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2638 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2639 return 0;
2640
ce8a8b2f 2641 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2642 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2643 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2644 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2645 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2646 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2647 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2648 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2649 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2650 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2651 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2652 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2653 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2654 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2655 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2656 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2657 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2658 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2659 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2660 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2661 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2662 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2663 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2664 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2665 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2666 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2667 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2668 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2669 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2670 return 0;
31312f95 2671#endif
252b5132
RH		 2672 return 1;
2673}
252b5132 2674
b4cac588 2675static int
e3bb37b5 2676intel_float_operand (const char *mnemonic)
252b5132 2677{
9306ca4a
JB		 2678 /* Note that the value returned is meaningful only for opcodes with (memory)
2679 operands, hence the code here is free to improperly handle opcodes that
2680 have no operands (for better performance and smaller code). */
2681
2682 if (mnemonic[0] != 'f')
2683 return 0; /* non-math */
2684
2685 switch (mnemonic[1])
2686 {
2687 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2688 the fs segment override prefix not currently handled because no
2689 call path can make opcodes without operands get here */
2690 case 'i':
2691 return 2 /* integer op */;
2692 case 'l':
2693 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2694 return 3; /* fldcw/fldenv */
2695 break;
2696 case 'n':
2697 if (mnemonic[2] != 'o' /* fnop */)
2698 return 3; /* non-waiting control op */
2699 break;
2700 case 'r':
2701 if (mnemonic[2] == 's')
2702 return 3; /* frstor/frstpm */
2703 break;
2704 case 's':
2705 if (mnemonic[2] == 'a')
2706 return 3; /* fsave */
2707 if (mnemonic[2] == 't')
2708 {
2709 switch (mnemonic[3])
2710 {
2711 case 'c': /* fstcw */
2712 case 'd': /* fstdw */
2713 case 'e': /* fstenv */
2714 case 's': /* fsts[gw] */
2715 return 3;
2716 }
2717 }
2718 break;
2719 case 'x':
2720 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2721 return 0; /* fxsave/fxrstor are not really math ops */
2722 break;
2723 }
252b5132 2724
9306ca4a 2725 return 1;
252b5132
RH		 2726}
2727
c0f3af97
L		 2728/* Build the VEX prefix. */
2729
2730static void
d3ce72d0 2731build_vex_prefix (const insn_template *t)
c0f3af97
L		 2732{
2733 unsigned int register_specifier;
2734 unsigned int implied_prefix;
2735 unsigned int vector_length;
2736
2737 /* Check register specifier. */
2738 if (i.vex.register_specifier)
2739 {
2740 register_specifier = i.vex.register_specifier->reg_num;
2741 if ((i.vex.register_specifier->reg_flags & RegRex))
2742 register_specifier += 8;
2743 register_specifier = ~register_specifier & 0xf;
2744 }
2745 else
2746 register_specifier = 0xf;
2747
fa99fab2
L		 2748 /* Use 2-byte VEX prefix by swappping destination and source
2749 operand. */
2750 if (!i.swap_operand
2751 && i.operands == i.reg_operands
7f399153 2752 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2753 && i.tm.opcode_modifier.s
2754 && i.rex == REX_B)
2755 {
2756 unsigned int xchg = i.operands - 1;
2757 union i386_op temp_op;
2758 i386_operand_type temp_type;
2759
2760 temp_type = i.types[xchg];
2761 i.types[xchg] = i.types[0];
2762 i.types[0] = temp_type;
2763 temp_op = i.op[xchg];
2764 i.op[xchg] = i.op[0];
2765 i.op[0] = temp_op;
2766
9c2799c2 2767 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2768
2769 i.rex = REX_R;
2770 xchg = i.rm.regmem;
2771 i.rm.regmem = i.rm.reg;
2772 i.rm.reg = xchg;
2773
2774 /* Use the next insn. */
2775 i.tm = t[1];
2776 }
2777
539f890d
L		 2778 if (i.tm.opcode_modifier.vex == VEXScalar)
2779 vector_length = avxscalar;
2780 else
2781 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2782
2783 switch ((i.tm.base_opcode >> 8) & 0xff)
2784 {
2785 case 0:
2786 implied_prefix = 0;
2787 break;
2788 case DATA_PREFIX_OPCODE:
2789 implied_prefix = 1;
2790 break;
2791 case REPE_PREFIX_OPCODE:
2792 implied_prefix = 2;
2793 break;
2794 case REPNE_PREFIX_OPCODE:
2795 implied_prefix = 3;
2796 break;
2797 default:
2798 abort ();
2799 }
2800
2801 /* Use 2-byte VEX prefix if possible. */
7f399153 2802 if (i.tm.opcode_modifier.vexopcode == VEX0F
c0f3af97
L		 2803 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2804 {
2805 /* 2-byte VEX prefix. */
2806 unsigned int r;
2807
2808 i.vex.length = 2;
2809 i.vex.bytes[0] = 0xc5;
2810
2811 /* Check the REX.R bit. */
2812 r = (i.rex & REX_R) ? 0 : 1;
2813 i.vex.bytes[1] = (r << 7
2814 | register_specifier << 3
2815 | vector_length << 2
2816 | implied_prefix);
2817 }
2818 else
2819 {
2820 /* 3-byte VEX prefix. */
2821 unsigned int m, w;
2822
f88c9eb0 2823 i.vex.length = 3;
f88c9eb0 2824
7f399153 2825 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2826 {
7f399153
L		 2827 case VEX0F:
2828 m = 0x1;
80de6e00 2829 i.vex.bytes[0] = 0xc4;
7f399153
L		 2830 break;
2831 case VEX0F38:
2832 m = 0x2;
80de6e00 2833 i.vex.bytes[0] = 0xc4;
7f399153
L		 2834 break;
2835 case VEX0F3A:
2836 m = 0x3;
80de6e00 2837 i.vex.bytes[0] = 0xc4;
7f399153
L		 2838 break;
2839 case XOP08:
5dd85c99
SP		 2840 m = 0x8;
2841 i.vex.bytes[0] = 0x8f;
7f399153
L		 2842 break;
2843 case XOP09:
f88c9eb0
SP		 2844 m = 0x9;
2845 i.vex.bytes[0] = 0x8f;
7f399153
L		 2846 break;
2847 case XOP0A:
f88c9eb0
SP		 2848 m = 0xa;
2849 i.vex.bytes[0] = 0x8f;
7f399153
L		 2850 break;
2851 default:
2852 abort ();
f88c9eb0 2853 }
c0f3af97 2854
c0f3af97
L		 2855 /* The high 3 bits of the second VEX byte are 1's compliment
2856 of RXB bits from REX. */
2857 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2858
2859 /* Check the REX.W bit. */
2860 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2861 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2862 {
2863 if (w)
2864 abort ();
2865
1ef99a7b 2866 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2867 w = 1;
2868 }
2869
2870 i.vex.bytes[2] = (w << 7
2871 | register_specifier << 3
2872 | vector_length << 2
2873 | implied_prefix);
2874 }
2875}
2876
65da13b5
L		 2877static void
2878process_immext (void)
2879{
2880 expressionS *exp;
2881
2882 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2883 {
1fed0ba1
L		 2884 /* SSE3 Instructions have the fixed operands with an opcode
2885 suffix which is coded in the same place as an 8-bit immediate
2886 field would be. Here we check those operands and remove them
2887 afterwards. */
65da13b5
L		 2888 unsigned int x;
2889
2890 for (x = 0; x < i.operands; x++)
2891 if (i.op[x].regs->reg_num != x)
2892 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2893 register_prefix, i.op[x].regs->reg_name, x + 1,
2894 i.tm.name);
2895
2896 i.operands = 0;
65da13b5
L		 2897 }
2898
c0f3af97 2899 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2900 which is coded in the same place as an 8-bit immediate field
2901 would be. Here we fake an 8-bit immediate operand from the
2902 opcode suffix stored in tm.extension_opcode.
2903
c1e679ec 2904 AVX instructions also use this encoding, for some of
c0f3af97 2905 3 argument instructions. */
65da13b5 2906
9c2799c2 2907 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2908 && (i.operands <= 2
2909 || (i.tm.opcode_modifier.vex
2910 && i.operands <= 4)));
65da13b5
L		 2911
2912 exp = &im_expressions[i.imm_operands++];
2913 i.op[i.operands].imms = exp;
2914 i.types[i.operands] = imm8;
2915 i.operands++;
2916 exp->X_op = O_constant;
2917 exp->X_add_number = i.tm.extension_opcode;
2918 i.tm.extension_opcode = None;
2919}
2920
252b5132
RH		 2921/* This is the guts of the machine-dependent assembler. LINE points to a
2922 machine dependent instruction. This function is supposed to emit
2923 the frags/bytes it assembles to. */
2924
2925void
65da13b5 2926md_assemble (char *line)
252b5132 2927{
40fb9820 2928 unsigned int j;
252b5132 2929 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2930 const insn_template *t;
252b5132 2931
47926f60 2932 /* Initialize globals. */
252b5132
RH		 2933 memset (&i, '\0', sizeof (i));
2934 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2935 i.reloc[j] = NO_RELOC;
252b5132
RH		 2936 memset (disp_expressions, '\0', sizeof (disp_expressions));
2937 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2938 save_stack_p = save_stack;
252b5132
RH		 2939
2940 /* First parse an instruction mnemonic & call i386_operand for the operands.
2941 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2942 start of a (possibly prefixed) mnemonic. */
252b5132 2943
29b0f896
AM		 2944 line = parse_insn (line, mnemonic);
2945 if (line == NULL)
2946 return;
252b5132 2947
29b0f896 2948 line = parse_operands (line, mnemonic);
ee86248c 2949 this_operand = -1;
29b0f896
AM		 2950 if (line == NULL)
2951 return;
252b5132 2952
29b0f896
AM		 2953 /* Now we've parsed the mnemonic into a set of templates, and have the
2954 operands at hand. */
2955
2956 /* All intel opcodes have reversed operands except for "bound" and
2957 "enter". We also don't reverse intersegment "jmp" and "call"
2958 instructions with 2 immediate operands so that the immediate segment
050dfa73 2959 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2960 if (intel_syntax
2961 && i.operands > 1
29b0f896 2962 && (strcmp (mnemonic, "bound") != 0)
30123838 2963 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2964 && !(operand_type_check (i.types[0], imm)
2965 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2966 swap_operands ();
2967
ec56d5c0
JB		 2968 /* The order of the immediates should be reversed
2969 for 2 immediates extrq and insertq instructions */
2970 if (i.imm_operands == 2
2971 && (strcmp (mnemonic, "extrq") == 0
2972 || strcmp (mnemonic, "insertq") == 0))
2973 swap_2_operands (0, 1);
2974
29b0f896
AM		 2975 if (i.imm_operands)
2976 optimize_imm ();
2977
b300c311
L		 2978 /* Don't optimize displacement for movabs since it only takes 64bit
2979 displacement. */
2980 if (i.disp_operands
2981 && (flag_code != CODE_64BIT
2982 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2983 optimize_disp ();
2984
2985 /* Next, we find a template that matches the given insn,
2986 making sure the overlap of the given operands types is consistent
2987 with the template operand types. */
252b5132 2988
fa99fab2 2989 if (!(t = match_template ()))
29b0f896 2990 return;
252b5132 2991
daf50ae7 2992 if (sse_check != sse_check_none
81f8a913 2993 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2994 && (i.tm.cpu_flags.bitfield.cpusse
2995 || i.tm.cpu_flags.bitfield.cpusse2
2996 || i.tm.cpu_flags.bitfield.cpusse3
2997 || i.tm.cpu_flags.bitfield.cpussse3
2998 || i.tm.cpu_flags.bitfield.cpusse4_1
2999 || i.tm.cpu_flags.bitfield.cpusse4_2))
3000 {
3001 (sse_check == sse_check_warning
3002 ? as_warn
3003 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3004 }
3005
321fd21e
L		 3006 /* Zap movzx and movsx suffix. The suffix has been set from
3007 "word ptr" or "byte ptr" on the source operand in Intel syntax
3008 or extracted from mnemonic in AT&T syntax. But we'll use
3009 the destination register to choose the suffix for encoding. */
3010 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3011 {
321fd21e
L		 3012 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3013 there is no suffix, the default will be byte extension. */
3014 if (i.reg_operands != 2
3015 && !i.suffix
7ab9ffdd 3016 && intel_syntax)
321fd21e
L		 3017 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3018
3019 i.suffix = 0;
cd61ebfe 3020 }
24eab124 3021
40fb9820 3022 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3023 if (!add_prefix (FWAIT_OPCODE))
3024 return;
252b5132 3025
c1ba0266
L		 3026 /* Check for lock without a lockable instruction. Destination operand
3027 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3028 if (i.prefix[LOCK_PREFIX]
3029 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3030 || i.mem_operands == 0
3031 || (i.tm.base_opcode != 0x86
3032 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3033 {
3034 as_bad (_("expecting lockable instruction after `lock'"));
3035 return;
3036 }
3037
29b0f896 3038 /* Check string instruction segment overrides. */
40fb9820 3039 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3040 {
3041 if (!check_string ())
5dd0794d 3042 return;
fc0763e6 3043 i.disp_operands = 0;
29b0f896 3044 }
5dd0794d 3045
29b0f896
AM		 3046 if (!process_suffix ())
3047 return;
e413e4e9 3048
bc0844ae
L		 3049 /* Update operand types. */
3050 for (j = 0; j < i.operands; j++)
3051 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3052
29b0f896
AM		 3053 /* Make still unresolved immediate matches conform to size of immediate
3054 given in i.suffix. */
3055 if (!finalize_imm ())
3056 return;
252b5132 3057
40fb9820 3058 if (i.types[0].bitfield.imm1)
29b0f896 3059 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3060
9afe6eb8
L		 3061 /* We only need to check those implicit registers for instructions
3062 with 3 operands or less. */
3063 if (i.operands <= 3)
3064 for (j = 0; j < i.operands; j++)
3065 if (i.types[j].bitfield.inoutportreg
3066 || i.types[j].bitfield.shiftcount
3067 || i.types[j].bitfield.acc
3068 || i.types[j].bitfield.floatacc)
3069 i.reg_operands--;
40fb9820 3070
c0f3af97
L		 3071 /* ImmExt should be processed after SSE2AVX. */
3072 if (!i.tm.opcode_modifier.sse2avx
3073 && i.tm.opcode_modifier.immext)
65da13b5 3074 process_immext ();
252b5132 3075
29b0f896
AM		 3076 /* For insns with operands there are more diddles to do to the opcode. */
3077 if (i.operands)
3078 {
3079 if (!process_operands ())
3080 return;
3081 }
40fb9820 3082 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3083 {
3084 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3085 as_warn (_("translating to `%sp'"), i.tm.name);
3086 }
252b5132 3087
c0f3af97 3088 if (i.tm.opcode_modifier.vex)
fa99fab2 3089 build_vex_prefix (t);
c0f3af97 3090
5dd85c99
SP		 3091 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3092 instructions may define INT_OPCODE as well, so avoid this corner
3093 case for those instructions that use MODRM. */
3094 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3095 && !i.tm.opcode_modifier.modrm
3096 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3097 {
3098 i.tm.base_opcode = INT3_OPCODE;
3099 i.imm_operands = 0;
3100 }
252b5132 3101
40fb9820
L		 3102 if ((i.tm.opcode_modifier.jump
3103 || i.tm.opcode_modifier.jumpbyte
3104 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3105 && i.op[0].disps->X_op == O_constant)
3106 {
3107 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3108 the absolute address given by the constant. Since ix86 jumps and
3109 calls are pc relative, we need to generate a reloc. */
3110 i.op[0].disps->X_add_symbol = &abs_symbol;
3111 i.op[0].disps->X_op = O_symbol;
3112 }
252b5132 3113
40fb9820 3114 if (i.tm.opcode_modifier.rex64)
161a04f6 3115 i.rex |= REX_W;
252b5132 3116
29b0f896
AM		 3117 /* For 8 bit registers we need an empty rex prefix. Also if the
3118 instruction already has a prefix, we need to convert old
3119 registers to new ones. */
773f551c 3120
40fb9820 3121 if ((i.types[0].bitfield.reg8
29b0f896 3122 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3123 || (i.types[1].bitfield.reg8
29b0f896 3124 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3125 || ((i.types[0].bitfield.reg8
3126 || i.types[1].bitfield.reg8)
29b0f896
AM		 3127 && i.rex != 0))
3128 {
3129 int x;
726c5dcd 3130
29b0f896
AM		 3131 i.rex |= REX_OPCODE;
3132 for (x = 0; x < 2; x++)
3133 {
3134 /* Look for 8 bit operand that uses old registers. */
40fb9820 3135 if (i.types[x].bitfield.reg8
29b0f896 3136 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3137 {
29b0f896
AM		 3138 /* In case it is "hi" register, give up. */
3139 if (i.op[x].regs->reg_num > 3)
a540244d 3140 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3141 "instruction requiring REX prefix."),
a540244d 3142 register_prefix, i.op[x].regs->reg_name);
773f551c 3143
29b0f896
AM		 3144 /* Otherwise it is equivalent to the extended register.
3145 Since the encoding doesn't change this is merely
3146 cosmetic cleanup for debug output. */
3147
3148 i.op[x].regs = i.op[x].regs + 8;
773f551c 3149 }
29b0f896
AM		 3150 }
3151 }
773f551c 3152
7ab9ffdd 3153 if (i.rex != 0)
29b0f896
AM		 3154 add_prefix (REX_OPCODE | i.rex);
3155
3156 /* We are ready to output the insn. */
3157 output_insn ();
3158}
3159
3160static char *
e3bb37b5 3161parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3162{
3163 char *l = line;
3164 char *token_start = l;
3165 char *mnem_p;
5c6af06e 3166 int supported;
d3ce72d0 3167 const insn_template *t;
b6169b20 3168 char *dot_p = NULL;
29b0f896
AM		 3169
3170 /* Non-zero if we found a prefix only acceptable with string insns. */
3171 const char *expecting_string_instruction = NULL;
45288df1 3172
29b0f896
AM		 3173 while (1)
3174 {
3175 mnem_p = mnemonic;
3176 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3177 {
b6169b20
L		 3178 if (*mnem_p == '.')
3179 dot_p = mnem_p;
29b0f896
AM		 3180 mnem_p++;
3181 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3182 {
29b0f896
AM		 3183 as_bad (_("no such instruction: `%s'"), token_start);
3184 return NULL;
3185 }
3186 l++;
3187 }
3188 if (!is_space_char (*l)
3189 && *l != END_OF_INSN
e44823cf
JB		 3190 && (intel_syntax
3191 || (*l != PREFIX_SEPARATOR
3192 && *l != ',')))
29b0f896
AM		 3193 {
3194 as_bad (_("invalid character %s in mnemonic"),
3195 output_invalid (*l));
3196 return NULL;
3197 }
3198 if (token_start == l)
3199 {
e44823cf 3200 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3201 as_bad (_("expecting prefix; got nothing"));
3202 else
3203 as_bad (_("expecting mnemonic; got nothing"));
3204 return NULL;
3205 }
45288df1 3206
29b0f896 3207 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3208 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3209
29b0f896
AM		 3210 if (*l != END_OF_INSN
3211 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3212 && current_templates
40fb9820 3213 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3214 {
c6fb90c8 3215 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3216 {
3217 as_bad ((flag_code != CODE_64BIT
3218 ? _("`%s' is only supported in 64-bit mode")
3219 : _("`%s' is not supported in 64-bit mode")),
3220 current_templates->start->name);
3221 return NULL;
3222 }
29b0f896
AM		 3223 /* If we are in 16-bit mode, do not allow addr16 or data16.
3224 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3225 if ((current_templates->start->opcode_modifier.size16
3226 || current_templates->start->opcode_modifier.size32)
29b0f896 3227 && flag_code != CODE_64BIT
40fb9820 3228 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3229 ^ (flag_code == CODE_16BIT)))
3230 {
3231 as_bad (_("redundant %s prefix"),
3232 current_templates->start->name);
3233 return NULL;
45288df1 3234 }
29b0f896
AM		 3235 /* Add prefix, checking for repeated prefixes. */
3236 switch (add_prefix (current_templates->start->base_opcode))
3237 {
c32fa91d 3238 case PREFIX_EXIST:
29b0f896 3239 return NULL;
c32fa91d 3240 case PREFIX_REP:
29b0f896
AM		 3241 expecting_string_instruction = current_templates->start->name;
3242 break;
c32fa91d
L		 3243 default:
3244 break;
29b0f896
AM		 3245 }
3246 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3247 token_start = ++l;
3248 }
3249 else
3250 break;
3251 }
45288df1 3252
30a55f88 3253 if (!current_templates)
b6169b20 3254 {
30a55f88
L		 3255 /* Check if we should swap operand in encoding. */
3256 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3257 i.swap_operand = 1;
3258 else
3259 goto check_suffix;
3260 mnem_p = dot_p;
3261 *dot_p = '\0';
d3ce72d0 3262 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3263 }
3264
29b0f896
AM		 3265 if (!current_templates)
3266 {
b6169b20 3267check_suffix:
29b0f896
AM		 3268 /* See if we can get a match by trimming off a suffix. */
3269 switch (mnem_p[-1])
3270 {
3271 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3272 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3273 i.suffix = SHORT_MNEM_SUFFIX;
3274 else
29b0f896
AM		 3275 case BYTE_MNEM_SUFFIX:
3276 case QWORD_MNEM_SUFFIX:
3277 i.suffix = mnem_p[-1];
3278 mnem_p[-1] = '\0';
d3ce72d0
NC		 3279 current_templates = (const templates *) hash_find (op_hash,
3280 mnemonic);
29b0f896
AM		 3281 break;
3282 case SHORT_MNEM_SUFFIX:
3283 case LONG_MNEM_SUFFIX:
3284 if (!intel_syntax)
3285 {
3286 i.suffix = mnem_p[-1];
3287 mnem_p[-1] = '\0';
d3ce72d0
NC		 3288 current_templates = (const templates *) hash_find (op_hash,
3289 mnemonic);
29b0f896
AM		 3290 }
3291 break;
252b5132 3292
29b0f896
AM		 3293 /* Intel Syntax. */
3294 case 'd':
3295 if (intel_syntax)
3296 {
9306ca4a 3297 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3298 i.suffix = SHORT_MNEM_SUFFIX;
3299 else
3300 i.suffix = LONG_MNEM_SUFFIX;
3301 mnem_p[-1] = '\0';
d3ce72d0
NC		 3302 current_templates = (const templates *) hash_find (op_hash,
3303 mnemonic);
29b0f896
AM		 3304 }
3305 break;
3306 }
3307 if (!current_templates)
3308 {
3309 as_bad (_("no such instruction: `%s'"), token_start);
3310 return NULL;
3311 }
3312 }
252b5132 3313
40fb9820
L		 3314 if (current_templates->start->opcode_modifier.jump
3315 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3316 {
3317 /* Check for a branch hint. We allow ",pt" and ",pn" for
3318 predict taken and predict not taken respectively.
3319 I'm not sure that branch hints actually do anything on loop
3320 and jcxz insns (JumpByte) for current Pentium4 chips. They
3321 may work in the future and it doesn't hurt to accept them
3322 now. */
3323 if (l[0] == ',' && l[1] == 'p')
3324 {
3325 if (l[2] == 't')
3326 {
3327 if (!add_prefix (DS_PREFIX_OPCODE))
3328 return NULL;
3329 l += 3;
3330 }
3331 else if (l[2] == 'n')
3332 {
3333 if (!add_prefix (CS_PREFIX_OPCODE))
3334 return NULL;
3335 l += 3;
3336 }
3337 }
3338 }
3339 /* Any other comma loses. */
3340 if (*l == ',')
3341 {
3342 as_bad (_("invalid character %s in mnemonic"),
3343 output_invalid (*l));
3344 return NULL;
3345 }
252b5132 3346
29b0f896 3347 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3348 supported = 0;
3349 for (t = current_templates->start; t < current_templates->end; ++t)
3350 {
c0f3af97
L		 3351 supported |= cpu_flags_match (t);
3352 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3353 goto skip;
5c6af06e 3354 }
3629bb00 3355
c0f3af97 3356 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3357 {
3358 as_bad (flag_code == CODE_64BIT
3359 ? _("`%s' is not supported in 64-bit mode")
3360 : _("`%s' is only supported in 64-bit mode"),
3361 current_templates->start->name);
3362 return NULL;
3363 }
c0f3af97 3364 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3365 {
3629bb00 3366 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3367 current_templates->start->name,
41aacd83 3368 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3369 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3370 return NULL;
29b0f896 3371 }
3629bb00
L		 3372
3373skip:
3374 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3375 && (flag_code != CODE_16BIT))
29b0f896
AM		 3376 {
3377 as_warn (_("use .code16 to ensure correct addressing mode"));
3378 }
252b5132 3379
29b0f896 3380 /* Check for rep/repne without a string instruction. */
f41bbced 3381 if (expecting_string_instruction)
29b0f896 3382 {
f41bbced
JB		 3383 static templates override;
3384
3385 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3386 if (t->opcode_modifier.isstring)
f41bbced
JB		 3387 break;
3388 if (t >= current_templates->end)
3389 {
3390 as_bad (_("expecting string instruction after `%s'"),
64e74474 3391 expecting_string_instruction);
f41bbced
JB		 3392 return NULL;
3393 }
3394 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3395 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3396 break;
3397 override.end = t;
3398 current_templates = &override;
29b0f896 3399 }
252b5132 3400
29b0f896
AM		 3401 return l;
3402}
252b5132 3403
29b0f896 3404static char *
e3bb37b5 3405parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3406{
3407 char *token_start;
3138f287 3408
29b0f896
AM		 3409 /* 1 if operand is pending after ','. */
3410 unsigned int expecting_operand = 0;
252b5132 3411
29b0f896
AM		 3412 /* Non-zero if operand parens not balanced. */
3413 unsigned int paren_not_balanced;
3414
3415 while (*l != END_OF_INSN)
3416 {
3417 /* Skip optional white space before operand. */
3418 if (is_space_char (*l))
3419 ++l;
3420 if (!is_operand_char (*l) && *l != END_OF_INSN)
3421 {
3422 as_bad (_("invalid character %s before operand %d"),
3423 output_invalid (*l),
3424 i.operands + 1);
3425 return NULL;
3426 }
3427 token_start = l; /* after white space */
3428 paren_not_balanced = 0;
3429 while (paren_not_balanced || *l != ',')
3430 {
3431 if (*l == END_OF_INSN)
3432 {
3433 if (paren_not_balanced)
3434 {
3435 if (!intel_syntax)
3436 as_bad (_("unbalanced parenthesis in operand %d."),
3437 i.operands + 1);
3438 else
3439 as_bad (_("unbalanced brackets in operand %d."),
3440 i.operands + 1);
3441 return NULL;
3442 }
3443 else
3444 break; /* we are done */
3445 }
3446 else if (!is_operand_char (*l) && !is_space_char (*l))
3447 {
3448 as_bad (_("invalid character %s in operand %d"),
3449 output_invalid (*l),
3450 i.operands + 1);
3451 return NULL;
3452 }
3453 if (!intel_syntax)
3454 {
3455 if (*l == '(')
3456 ++paren_not_balanced;
3457 if (*l == ')')
3458 --paren_not_balanced;
3459 }
3460 else
3461 {
3462 if (*l == '[')
3463 ++paren_not_balanced;
3464 if (*l == ']')
3465 --paren_not_balanced;
3466 }
3467 l++;
3468 }
3469 if (l != token_start)
3470 { /* Yes, we've read in another operand. */
3471 unsigned int operand_ok;
3472 this_operand = i.operands++;
7d5e4556 3473 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3474 if (i.operands > MAX_OPERANDS)
3475 {
3476 as_bad (_("spurious operands; (%d operands/instruction max)"),
3477 MAX_OPERANDS);
3478 return NULL;
3479 }
3480 /* Now parse operand adding info to 'i' as we go along. */
3481 END_STRING_AND_SAVE (l);
3482
3483 if (intel_syntax)
3484 operand_ok =
3485 i386_intel_operand (token_start,
3486 intel_float_operand (mnemonic));
3487 else
a7619375 3488 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3489
3490 RESTORE_END_STRING (l);
3491 if (!operand_ok)
3492 return NULL;
3493 }
3494 else
3495 {
3496 if (expecting_operand)
3497 {
3498 expecting_operand_after_comma:
3499 as_bad (_("expecting operand after ','; got nothing"));
3500 return NULL;
3501 }
3502 if (*l == ',')
3503 {
3504 as_bad (_("expecting operand before ','; got nothing"));
3505 return NULL;
3506 }
3507 }
7f3f1ea2 3508
29b0f896
AM		 3509 /* Now *l must be either ',' or END_OF_INSN. */
3510 if (*l == ',')
3511 {
3512 if (*++l == END_OF_INSN)
3513 {
3514 /* Just skip it, if it's \n complain. */
3515 goto expecting_operand_after_comma;
3516 }
3517 expecting_operand = 1;
3518 }
3519 }
3520 return l;
3521}
7f3f1ea2 3522
050dfa73 3523static void
4d456e3d 3524swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3525{
3526 union i386_op temp_op;
40fb9820 3527 i386_operand_type temp_type;
050dfa73 3528 enum bfd_reloc_code_real temp_reloc;
4eed87de 3529
050dfa73
MM		 3530 temp_type = i.types[xchg2];
3531 i.types[xchg2] = i.types[xchg1];
3532 i.types[xchg1] = temp_type;
3533 temp_op = i.op[xchg2];
3534 i.op[xchg2] = i.op[xchg1];
3535 i.op[xchg1] = temp_op;
3536 temp_reloc = i.reloc[xchg2];
3537 i.reloc[xchg2] = i.reloc[xchg1];
3538 i.reloc[xchg1] = temp_reloc;
3539}
3540
29b0f896 3541static void
e3bb37b5 3542swap_operands (void)
29b0f896 3543{
b7c61d9a 3544 switch (i.operands)
050dfa73 3545 {
c0f3af97 3546 case 5:
b7c61d9a 3547 case 4:
4d456e3d 3548 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3549 case 3:
3550 case 2:
4d456e3d 3551 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3552 break;
3553 default:
3554 abort ();
29b0f896 3555 }
29b0f896
AM		 3556
3557 if (i.mem_operands == 2)
3558 {
3559 const seg_entry *temp_seg;
3560 temp_seg = i.seg[0];
3561 i.seg[0] = i.seg[1];
3562 i.seg[1] = temp_seg;
3563 }
3564}
252b5132 3565
29b0f896
AM		 3566/* Try to ensure constant immediates are represented in the smallest
3567 opcode possible. */
3568static void
e3bb37b5 3569optimize_imm (void)
29b0f896
AM		 3570{
3571 char guess_suffix = 0;
3572 int op;
252b5132 3573
29b0f896
AM		 3574 if (i.suffix)
3575 guess_suffix = i.suffix;
3576 else if (i.reg_operands)
3577 {
3578 /* Figure out a suffix from the last register operand specified.
3579 We can't do this properly yet, ie. excluding InOutPortReg,
3580 but the following works for instructions with immediates.
3581 In any case, we can't set i.suffix yet. */
3582 for (op = i.operands; --op >= 0;)
40fb9820 3583 if (i.types[op].bitfield.reg8)
7ab9ffdd 3584 {
40fb9820
L		 3585 guess_suffix = BYTE_MNEM_SUFFIX;
3586 break;
3587 }
3588 else if (i.types[op].bitfield.reg16)
252b5132 3589 {
40fb9820
L		 3590 guess_suffix = WORD_MNEM_SUFFIX;
3591 break;
3592 }
3593 else if (i.types[op].bitfield.reg32)
3594 {
3595 guess_suffix = LONG_MNEM_SUFFIX;
3596 break;
3597 }
3598 else if (i.types[op].bitfield.reg64)
3599 {
3600 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3601 break;
252b5132 3602 }
29b0f896
AM		 3603 }
3604 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3605 guess_suffix = WORD_MNEM_SUFFIX;
3606
3607 for (op = i.operands; --op >= 0;)
40fb9820 3608 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3609 {
3610 switch (i.op[op].imms->X_op)
252b5132 3611 {
29b0f896
AM		 3612 case O_constant:
3613 /* If a suffix is given, this operand may be shortened. */
3614 switch (guess_suffix)
252b5132 3615 {
29b0f896 3616 case LONG_MNEM_SUFFIX:
40fb9820
L		 3617 i.types[op].bitfield.imm32 = 1;
3618 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3619 break;
3620 case WORD_MNEM_SUFFIX:
40fb9820
L		 3621 i.types[op].bitfield.imm16 = 1;
3622 i.types[op].bitfield.imm32 = 1;
3623 i.types[op].bitfield.imm32s = 1;
3624 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3625 break;
3626 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3627 i.types[op].bitfield.imm8 = 1;
3628 i.types[op].bitfield.imm8s = 1;
3629 i.types[op].bitfield.imm16 = 1;
3630 i.types[op].bitfield.imm32 = 1;
3631 i.types[op].bitfield.imm32s = 1;
3632 i.types[op].bitfield.imm64 = 1;
29b0f896 3633 break;
252b5132 3634 }
252b5132 3635
29b0f896
AM		 3636 /* If this operand is at most 16 bits, convert it
3637 to a signed 16 bit number before trying to see
3638 whether it will fit in an even smaller size.
3639 This allows a 16-bit operand such as $0xffe0 to
3640 be recognised as within Imm8S range. */
40fb9820 3641 if ((i.types[op].bitfield.imm16)
29b0f896 3642 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3643 {
29b0f896
AM		 3644 i.op[op].imms->X_add_number =
3645 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3646 }
40fb9820 3647 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3648 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3649 == 0))
3650 {
3651 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3652 ^ ((offsetT) 1 << 31))
3653 - ((offsetT) 1 << 31));
3654 }
40fb9820 3655 i.types[op]
c6fb90c8
L		 3656 = operand_type_or (i.types[op],
3657 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3658
29b0f896
AM		 3659 /* We must avoid matching of Imm32 templates when 64bit
3660 only immediate is available. */
3661 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3662 i.types[op].bitfield.imm32 = 0;
29b0f896 3663 break;
252b5132 3664
29b0f896
AM		 3665 case O_absent:
3666 case O_register:
3667 abort ();
3668
3669 /* Symbols and expressions. */
3670 default:
9cd96992
JB		 3671 /* Convert symbolic operand to proper sizes for matching, but don't
3672 prevent matching a set of insns that only supports sizes other
3673 than those matching the insn suffix. */
3674 {
40fb9820 3675 i386_operand_type mask, allowed;
d3ce72d0 3676 const insn_template *t;
9cd96992 3677
0dfbf9d7
L		 3678 operand_type_set (&mask, 0);
3679 operand_type_set (&allowed, 0);
40fb9820 3680
4eed87de
AM		 3681 for (t = current_templates->start;
3682 t < current_templates->end;
3683 ++t)
c6fb90c8
L		 3684 allowed = operand_type_or (allowed,
3685 t->operand_types[op]);
9cd96992
JB		 3686 switch (guess_suffix)
3687 {
3688 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3689 mask.bitfield.imm64 = 1;
3690 mask.bitfield.imm32s = 1;
9cd96992
JB		 3691 break;
3692 case LONG_MNEM_SUFFIX:
40fb9820 3693 mask.bitfield.imm32 = 1;
9cd96992
JB		 3694 break;
3695 case WORD_MNEM_SUFFIX:
40fb9820 3696 mask.bitfield.imm16 = 1;
9cd96992
JB		 3697 break;
3698 case BYTE_MNEM_SUFFIX:
40fb9820 3699 mask.bitfield.imm8 = 1;
9cd96992
JB		 3700 break;
3701 default:
9cd96992
JB		 3702 break;
3703 }
c6fb90c8 3704 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3705 if (!operand_type_all_zero (&allowed))
c6fb90c8 3706 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3707 }
29b0f896 3708 break;
252b5132 3709 }
29b0f896
AM		 3710 }
3711}
47926f60 3712
29b0f896
AM		 3713/* Try to use the smallest displacement type too. */
3714static void
e3bb37b5 3715optimize_disp (void)
29b0f896
AM		 3716{
3717 int op;
3e73aa7c 3718
29b0f896 3719 for (op = i.operands; --op >= 0;)
40fb9820 3720 if (operand_type_check (i.types[op], disp))
252b5132 3721 {
b300c311 3722 if (i.op[op].disps->X_op == O_constant)
252b5132 3723 {
91d6fa6a 3724 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3725
40fb9820 3726 if (i.types[op].bitfield.disp16
91d6fa6a 3727 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3728 {
3729 /* If this operand is at most 16 bits, convert
3730 to a signed 16 bit number and don't use 64bit
3731 displacement. */
91d6fa6a 3732 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3733 i.types[op].bitfield.disp64 = 0;
b300c311 3734 }
40fb9820 3735 if (i.types[op].bitfield.disp32
91d6fa6a 3736 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3737 {
3738 /* If this operand is at most 32 bits, convert
3739 to a signed 32 bit number and don't use 64bit
3740 displacement. */
91d6fa6a
NC		 3741 op_disp &= (((offsetT) 2 << 31) - 1);
3742 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3743 i.types[op].bitfield.disp64 = 0;
b300c311 3744 }
91d6fa6a 3745 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3746 {
40fb9820
L		 3747 i.types[op].bitfield.disp8 = 0;
3748 i.types[op].bitfield.disp16 = 0;
3749 i.types[op].bitfield.disp32 = 0;
3750 i.types[op].bitfield.disp32s = 0;
3751 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3752 i.op[op].disps = 0;
3753 i.disp_operands--;
3754 }
3755 else if (flag_code == CODE_64BIT)
3756 {
91d6fa6a 3757 if (fits_in_signed_long (op_disp))
28a9d8f5 3758 {
40fb9820
L		 3759 i.types[op].bitfield.disp64 = 0;
3760 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3761 }
0e1147d9 3762 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3763 && fits_in_unsigned_long (op_disp))
40fb9820 3764 i.types[op].bitfield.disp32 = 1;
b300c311 3765 }
40fb9820
L		 3766 if ((i.types[op].bitfield.disp32
3767 || i.types[op].bitfield.disp32s
3768 || i.types[op].bitfield.disp16)
91d6fa6a 3769 && fits_in_signed_byte (op_disp))
40fb9820 3770 i.types[op].bitfield.disp8 = 1;
252b5132 3771 }
67a4f2b7
AO		 3772 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3773 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3774 {
3775 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3776 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3777 i.types[op].bitfield.disp8 = 0;
3778 i.types[op].bitfield.disp16 = 0;
3779 i.types[op].bitfield.disp32 = 0;
3780 i.types[op].bitfield.disp32s = 0;
3781 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3782 }
3783 else
b300c311 3784 /* We only support 64bit displacement on constants. */
40fb9820 3785 i.types[op].bitfield.disp64 = 0;
252b5132 3786 }
29b0f896
AM		 3787}
3788
a683cc34
SP		 3789/* Check if operands are valid for the instrucrtion. Update VEX
3790 operand types. */
3791
3792static int
3793VEX_check_operands (const insn_template *t)
3794{
3795 if (!t->opcode_modifier.vex)
3796 return 0;
3797
3798 /* Only check VEX_Imm4, which must be the first operand. */
3799 if (t->operand_types[0].bitfield.vec_imm4)
3800 {
3801 if (i.op[0].imms->X_op != O_constant
3802 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3803 {
a65babc9 3804 i.error = bad_imm4;
891edac4
L		 3805 return 1;
3806 }
a683cc34
SP		 3807
3808 /* Turn off Imm8 so that update_imm won't complain. */
3809 i.types[0] = vec_imm4;
3810 }
3811
3812 return 0;
3813}
3814
d3ce72d0 3815static const insn_template *
e3bb37b5 3816match_template (void)
29b0f896
AM		 3817{
3818 /* Points to template once we've found it. */
d3ce72d0 3819 const insn_template *t;
40fb9820 3820 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3821 i386_operand_type overlap4;
29b0f896 3822 unsigned int found_reverse_match;
40fb9820
L		 3823 i386_opcode_modifier suffix_check;
3824 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3825 int addr_prefix_disp;
a5c311ca 3826 unsigned int j;
3629bb00 3827 unsigned int found_cpu_match;
45664ddb 3828 unsigned int check_register;
29b0f896 3829
c0f3af97
L		 3830#if MAX_OPERANDS != 5
3831# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3832#endif
3833
29b0f896 3834 found_reverse_match = 0;
539e75ad 3835 addr_prefix_disp = -1;
40fb9820
L		 3836
3837 memset (&suffix_check, 0, sizeof (suffix_check));
3838 if (i.suffix == BYTE_MNEM_SUFFIX)
3839 suffix_check.no_bsuf = 1;
3840 else if (i.suffix == WORD_MNEM_SUFFIX)
3841 suffix_check.no_wsuf = 1;
3842 else if (i.suffix == SHORT_MNEM_SUFFIX)
3843 suffix_check.no_ssuf = 1;
3844 else if (i.suffix == LONG_MNEM_SUFFIX)
3845 suffix_check.no_lsuf = 1;
3846 else if (i.suffix == QWORD_MNEM_SUFFIX)
3847 suffix_check.no_qsuf = 1;
3848 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3849 suffix_check.no_ldsuf = 1;
29b0f896 3850
45aa61fe 3851 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3852 {
539e75ad
L		 3853 addr_prefix_disp = -1;
3854
29b0f896 3855 /* Must have right number of operands. */
a65babc9 3856 i.error = number_of_operands_mismatch;
29b0f896
AM		 3857 if (i.operands != t->operands)
3858 continue;
3859
50aecf8c 3860 /* Check processor support. */
a65babc9 3861 i.error = unsupported;
c0f3af97
L		 3862 found_cpu_match = (cpu_flags_match (t)
3863 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3864 if (!found_cpu_match)
3865 continue;
3866
e1d4d893 3867 /* Check old gcc support. */
a65babc9 3868 i.error = old_gcc_only;
e1d4d893
L		 3869 if (!old_gcc && t->opcode_modifier.oldgcc)
3870 continue;
3871
3872 /* Check AT&T mnemonic. */
a65babc9 3873 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3874 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3875 continue;
3876
891edac4 3877 /* Check AT&T/Intel syntax. */
a65babc9 3878 i.error = unsupported_syntax;
5c07affc
L		 3879 if ((intel_syntax && t->opcode_modifier.attsyntax)
3880 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3881 continue;
3882
20592a94 3883 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3884 i.error = invalid_instruction_suffix;
567e4e96
L		 3885 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3886 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3887 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3888 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3889 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3890 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3891 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3892 continue;
3893
5c07affc 3894 if (!operand_size_match (t))
7d5e4556 3895 continue;
539e75ad 3896
5c07affc
L		 3897 for (j = 0; j < MAX_OPERANDS; j++)
3898 operand_types[j] = t->operand_types[j];
3899
45aa61fe
AM		 3900 /* In general, don't allow 64-bit operands in 32-bit mode. */
3901 if (i.suffix == QWORD_MNEM_SUFFIX
3902 && flag_code != CODE_64BIT
3903 && (intel_syntax
40fb9820 3904 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3905 && !intel_float_operand (t->name))
3906 : intel_float_operand (t->name) != 2)
40fb9820 3907 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3908 && !operand_types[0].bitfield.regxmm
3909 && !operand_types[0].bitfield.regymm)
40fb9820 3910 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3911 && !!operand_types[t->operands > 1].bitfield.regxmm
3912 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3913 && (t->base_opcode != 0x0fc7
3914 || t->extension_opcode != 1 /* cmpxchg8b */))
3915 continue;
3916
192dc9c6
JB		 3917 /* In general, don't allow 32-bit operands on pre-386. */
3918 else if (i.suffix == LONG_MNEM_SUFFIX
3919 && !cpu_arch_flags.bitfield.cpui386
3920 && (intel_syntax
3921 ? (!t->opcode_modifier.ignoresize
3922 && !intel_float_operand (t->name))
3923 : intel_float_operand (t->name) != 2)
3924 && ((!operand_types[0].bitfield.regmmx
3925 && !operand_types[0].bitfield.regxmm)
3926 || (!operand_types[t->operands > 1].bitfield.regmmx
3927 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3928 continue;
3929
29b0f896 3930 /* Do not verify operands when there are none. */
50aecf8c 3931 else
29b0f896 3932 {
c6fb90c8 3933 if (!t->operands)
2dbab7d5
L		 3934 /* We've found a match; break out of loop. */
3935 break;
29b0f896 3936 }
252b5132 3937
539e75ad
L		 3938 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3939 into Disp32/Disp16/Disp32 operand. */
3940 if (i.prefix[ADDR_PREFIX] != 0)
3941 {
40fb9820 3942 /* There should be only one Disp operand. */
539e75ad
L		 3943 switch (flag_code)
3944 {
3945 case CODE_16BIT:
40fb9820
L		 3946 for (j = 0; j < MAX_OPERANDS; j++)
3947 {
3948 if (operand_types[j].bitfield.disp16)
3949 {
3950 addr_prefix_disp = j;
3951 operand_types[j].bitfield.disp32 = 1;
3952 operand_types[j].bitfield.disp16 = 0;
3953 break;
3954 }
3955 }
539e75ad
L		 3956 break;
3957 case CODE_32BIT:
40fb9820
L		 3958 for (j = 0; j < MAX_OPERANDS; j++)
3959 {
3960 if (operand_types[j].bitfield.disp32)
3961 {
3962 addr_prefix_disp = j;
3963 operand_types[j].bitfield.disp32 = 0;
3964 operand_types[j].bitfield.disp16 = 1;
3965 break;
3966 }
3967 }
539e75ad
L		 3968 break;
3969 case CODE_64BIT:
40fb9820
L		 3970 for (j = 0; j < MAX_OPERANDS; j++)
3971 {
3972 if (operand_types[j].bitfield.disp64)
3973 {
3974 addr_prefix_disp = j;
3975 operand_types[j].bitfield.disp64 = 0;
3976 operand_types[j].bitfield.disp32 = 1;
3977 break;
3978 }
3979 }
539e75ad
L		 3980 break;
3981 }
539e75ad
L		 3982 }
3983
45664ddb
L		 3984 /* We check register size only if size of operands can be
3985 encoded the canonical way. */
3986 check_register = t->opcode_modifier.w;
c6fb90c8 3987 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3988 switch (t->operands)
3989 {
3990 case 1:
40fb9820 3991 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3992 continue;
3993 break;
3994 case 2:
8b38ad71
L		 3995 /* xchg %eax, %eax is a special case. It is an aliase for nop
3996 only in 32bit mode and we can use opcode 0x90. In 64bit
3997 mode, we can't use 0x90 for xchg %eax, %eax since it should
3998 zero-extend %eax to %rax. */
3999 if (flag_code == CODE_64BIT
4000 && t->base_opcode == 0x90
0dfbf9d7
L		 4001 && operand_type_equal (&i.types [0], &acc32)
4002 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4003 continue;
b6169b20
L		 4004 if (i.swap_operand)
4005 {
4006 /* If we swap operand in encoding, we either match
4007 the next one or reverse direction of operands. */
4008 if (t->opcode_modifier.s)
4009 continue;
4010 else if (t->opcode_modifier.d)
4011 goto check_reverse;
4012 }
4013
29b0f896 4014 case 3:
fa99fab2
L		 4015 /* If we swap operand in encoding, we match the next one. */
4016 if (i.swap_operand && t->opcode_modifier.s)
4017 continue;
f48ff2ae 4018 case 4:
c0f3af97 4019 case 5:
c6fb90c8 4020 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4021 if (!operand_type_match (overlap0, i.types[0])
4022 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4023 || (check_register
4024 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4025 operand_types[0],
4026 overlap1, i.types[1],
4027 operand_types[1])))
29b0f896
AM		 4028 {
4029 /* Check if other direction is valid ... */
40fb9820 4030 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4031 continue;
4032
b6169b20 4033check_reverse:
29b0f896 4034 /* Try reversing direction of operands. */
c6fb90c8
L		 4035 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4036 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4037 if (!operand_type_match (overlap0, i.types[0])
4038 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4039 || (check_register
4040 && !operand_type_register_match (overlap0,
4041 i.types[0],
4042 operand_types[1],
4043 overlap1,
4044 i.types[1],
4045 operand_types[0])))
29b0f896
AM		 4046 {
4047 /* Does not match either direction. */
4048 continue;
4049 }
4050 /* found_reverse_match holds which of D or FloatDR
4051 we've found. */
40fb9820 4052 if (t->opcode_modifier.d)
8a2ed489 4053 found_reverse_match = Opcode_D;
40fb9820 4054 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4055 found_reverse_match = Opcode_FloatD;
4056 else
4057 found_reverse_match = 0;
40fb9820 4058 if (t->opcode_modifier.floatr)
8a2ed489 4059 found_reverse_match |= Opcode_FloatR;
29b0f896 4060 }
f48ff2ae 4061 else
29b0f896 4062 {
f48ff2ae 4063 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4064 switch (t->operands)
4065 {
c0f3af97
L		 4066 case 5:
4067 overlap4 = operand_type_and (i.types[4],
4068 operand_types[4]);
d1cbb4db 4069 case 4:
c6fb90c8
L		 4070 overlap3 = operand_type_and (i.types[3],
4071 operand_types[3]);
d1cbb4db 4072 case 3:
c6fb90c8
L		 4073 overlap2 = operand_type_and (i.types[2],
4074 operand_types[2]);
d1cbb4db
L		 4075 break;
4076 }
29b0f896 4077
f48ff2ae
L		 4078 switch (t->operands)
4079 {
c0f3af97
L		 4080 case 5:
4081 if (!operand_type_match (overlap4, i.types[4])
4082 || !operand_type_register_match (overlap3,
4083 i.types[3],
4084 operand_types[3],
4085 overlap4,
4086 i.types[4],
4087 operand_types[4]))
4088 continue;
f48ff2ae 4089 case 4:
40fb9820 4090 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4091 || (check_register
4092 && !operand_type_register_match (overlap2,
4093 i.types[2],
4094 operand_types[2],
4095 overlap3,
4096 i.types[3],
4097 operand_types[3])))
f48ff2ae
L		 4098 continue;
4099 case 3:
4100 /* Here we make use of the fact that there are no
4101 reverse match 3 operand instructions, and all 3
4102 operand instructions only need to be checked for
4103 register consistency between operands 2 and 3. */
40fb9820 4104 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4105 || (check_register
4106 && !operand_type_register_match (overlap1,
4107 i.types[1],
4108 operand_types[1],
4109 overlap2,
4110 i.types[2],
4111 operand_types[2])))
f48ff2ae
L		 4112 continue;
4113 break;
4114 }
29b0f896 4115 }
f48ff2ae 4116 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4117 slip through to break. */
4118 }
3629bb00 4119 if (!found_cpu_match)
29b0f896
AM		 4120 {
4121 found_reverse_match = 0;
4122 continue;
4123 }
c0f3af97 4124
a683cc34
SP		 4125 /* Check if VEX operands are valid. */
4126 if (VEX_check_operands (t))
4127 continue;
4128
29b0f896
AM		 4129 /* We've found a match; break out of loop. */
4130 break;
4131 }
4132
4133 if (t == current_templates->end)
4134 {
4135 /* We found no match. */
a65babc9
L		 4136 const char *err_msg;
4137 switch (i.error)
4138 {
4139 default:
4140 abort ();
86e026a4 4141 case operand_size_mismatch:
a65babc9
L		 4142 err_msg = _("operand size mismatch");
4143 break;
4144 case operand_type_mismatch:
4145 err_msg = _("operand type mismatch");
4146 break;
4147 case register_type_mismatch:
4148 err_msg = _("register type mismatch");
4149 break;
4150 case number_of_operands_mismatch:
4151 err_msg = _("number of operands mismatch");
4152 break;
4153 case invalid_instruction_suffix:
4154 err_msg = _("invalid instruction suffix");
4155 break;
4156 case bad_imm4:
4157 err_msg = _("Imm4 isn't the first operand");
4158 break;
4159 case old_gcc_only:
4160 err_msg = _("only supported with old gcc");
4161 break;
4162 case unsupported_with_intel_mnemonic:
4163 err_msg = _("unsupported with Intel mnemonic");
4164 break;
4165 case unsupported_syntax:
4166 err_msg = _("unsupported syntax");
4167 break;
4168 case unsupported:
4169 err_msg = _("unsupported");
4170 break;
4171 }
4172 as_bad (_("%s for `%s'"), err_msg,
891edac4 4173 current_templates->start->name);
fa99fab2 4174 return NULL;
29b0f896 4175 }
252b5132 4176
29b0f896
AM		 4177 if (!quiet_warnings)
4178 {
4179 if (!intel_syntax
40fb9820
L		 4180 && (i.types[0].bitfield.jumpabsolute
4181 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4182 {
4183 as_warn (_("indirect %s without `*'"), t->name);
4184 }
4185
40fb9820
L		 4186 if (t->opcode_modifier.isprefix
4187 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4188 {
4189 /* Warn them that a data or address size prefix doesn't
4190 affect assembly of the next line of code. */
4191 as_warn (_("stand-alone `%s' prefix"), t->name);
4192 }
4193 }
4194
4195 /* Copy the template we found. */
4196 i.tm = *t;
539e75ad
L		 4197
4198 if (addr_prefix_disp != -1)
4199 i.tm.operand_types[addr_prefix_disp]
4200 = operand_types[addr_prefix_disp];
4201
29b0f896
AM		 4202 if (found_reverse_match)
4203 {
4204 /* If we found a reverse match we must alter the opcode
4205 direction bit. found_reverse_match holds bits to change
4206 (different for int & float insns). */
4207
4208 i.tm.base_opcode ^= found_reverse_match;
4209
539e75ad
L		 4210 i.tm.operand_types[0] = operand_types[1];
4211 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4212 }
4213
fa99fab2 4214 return t;
29b0f896
AM		 4215}
4216
4217static int
e3bb37b5 4218check_string (void)
29b0f896 4219{
40fb9820
L		 4220 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4221 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4222 {
4223 if (i.seg[0] != NULL && i.seg[0] != &es)
4224 {
a87af027 4225 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4226 i.tm.name,
a87af027
JB		 4227 mem_op + 1,
4228 register_prefix);
29b0f896
AM		 4229 return 0;
4230 }
4231 /* There's only ever one segment override allowed per instruction.
4232 This instruction possibly has a legal segment override on the
4233 second operand, so copy the segment to where non-string
4234 instructions store it, allowing common code. */
4235 i.seg[0] = i.seg[1];
4236 }
40fb9820 4237 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4238 {
4239 if (i.seg[1] != NULL && i.seg[1] != &es)
4240 {
a87af027 4241 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4242 i.tm.name,
a87af027
JB		 4243 mem_op + 2,
4244 register_prefix);
29b0f896
AM		 4245 return 0;
4246 }
4247 }
4248 return 1;
4249}
4250
4251static int
543613e9 4252process_suffix (void)
29b0f896
AM		 4253{
4254 /* If matched instruction specifies an explicit instruction mnemonic
4255 suffix, use it. */
40fb9820
L		 4256 if (i.tm.opcode_modifier.size16)
4257 i.suffix = WORD_MNEM_SUFFIX;
4258 else if (i.tm.opcode_modifier.size32)
4259 i.suffix = LONG_MNEM_SUFFIX;
4260 else if (i.tm.opcode_modifier.size64)
4261 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4262 else if (i.reg_operands)
4263 {
4264 /* If there's no instruction mnemonic suffix we try to invent one
4265 based on register operands. */
4266 if (!i.suffix)
4267 {
4268 /* We take i.suffix from the last register operand specified,
4269 Destination register type is more significant than source
381d071f
L		 4270 register type. crc32 in SSE4.2 prefers source register
4271 type. */
4272 if (i.tm.base_opcode == 0xf20f38f1)
4273 {
40fb9820
L		 4274 if (i.types[0].bitfield.reg16)
4275 i.suffix = WORD_MNEM_SUFFIX;
4276 else if (i.types[0].bitfield.reg32)
4277 i.suffix = LONG_MNEM_SUFFIX;
4278 else if (i.types[0].bitfield.reg64)
4279 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4280 }
9344ff29 4281 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4282 {
40fb9820 4283 if (i.types[0].bitfield.reg8)
20592a94
L		 4284 i.suffix = BYTE_MNEM_SUFFIX;
4285 }
381d071f
L		 4286
4287 if (!i.suffix)
4288 {
4289 int op;
4290
20592a94
L		 4291 if (i.tm.base_opcode == 0xf20f38f1
4292 || i.tm.base_opcode == 0xf20f38f0)
4293 {
4294 /* We have to know the operand size for crc32. */
4295 as_bad (_("ambiguous memory operand size for `%s`"),
4296 i.tm.name);
4297 return 0;
4298 }
4299
381d071f 4300 for (op = i.operands; --op >= 0;)
40fb9820 4301 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4302 {
40fb9820
L		 4303 if (i.types[op].bitfield.reg8)
4304 {
4305 i.suffix = BYTE_MNEM_SUFFIX;
4306 break;
4307 }
4308 else if (i.types[op].bitfield.reg16)
4309 {
4310 i.suffix = WORD_MNEM_SUFFIX;
4311 break;
4312 }
4313 else if (i.types[op].bitfield.reg32)
4314 {
4315 i.suffix = LONG_MNEM_SUFFIX;
4316 break;
4317 }
4318 else if (i.types[op].bitfield.reg64)
4319 {
4320 i.suffix = QWORD_MNEM_SUFFIX;
4321 break;
4322 }
381d071f
L		 4323 }
4324 }
29b0f896
AM		 4325 }
4326 else if (i.suffix == BYTE_MNEM_SUFFIX)
4327 {
2eb952a4
L		 4328 if (intel_syntax
4329 && i.tm.opcode_modifier.ignoresize
4330 && i.tm.opcode_modifier.no_bsuf)
4331 i.suffix = 0;
4332 else if (!check_byte_reg ())
29b0f896
AM		 4333 return 0;
4334 }
4335 else if (i.suffix == LONG_MNEM_SUFFIX)
4336 {
2eb952a4
L		 4337 if (intel_syntax
4338 && i.tm.opcode_modifier.ignoresize
4339 && i.tm.opcode_modifier.no_lsuf)
4340 i.suffix = 0;
4341 else if (!check_long_reg ())
29b0f896
AM		 4342 return 0;
4343 }
4344 else if (i.suffix == QWORD_MNEM_SUFFIX)
4345 {
955e1e6a
L		 4346 if (intel_syntax
4347 && i.tm.opcode_modifier.ignoresize
4348 && i.tm.opcode_modifier.no_qsuf)
4349 i.suffix = 0;
4350 else if (!check_qword_reg ())
29b0f896
AM		 4351 return 0;
4352 }
4353 else if (i.suffix == WORD_MNEM_SUFFIX)
4354 {
2eb952a4
L		 4355 if (intel_syntax
4356 && i.tm.opcode_modifier.ignoresize
4357 && i.tm.opcode_modifier.no_wsuf)
4358 i.suffix = 0;
4359 else if (!check_word_reg ())
29b0f896
AM		 4360 return 0;
4361 }
c0f3af97
L		 4362 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4363 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4364 {
c0f3af97 4365 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4366 should check if it is a valid suffix. */
4367 }
40fb9820 4368 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4369 /* Do nothing if the instruction is going to ignore the prefix. */
4370 ;
4371 else
4372 abort ();
4373 }
40fb9820 4374 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4375 && !i.suffix
4376 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4377 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4378 {
4379 i.suffix = stackop_size;
4380 }
9306ca4a
JB		 4381 else if (intel_syntax
4382 && !i.suffix
40fb9820
L		 4383 && (i.tm.operand_types[0].bitfield.jumpabsolute
4384 || i.tm.opcode_modifier.jumpbyte
4385 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4386 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4387 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4388 {
4389 switch (flag_code)
4390 {
4391 case CODE_64BIT:
40fb9820 4392 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4393 {
4394 i.suffix = QWORD_MNEM_SUFFIX;
4395 break;
4396 }
4397 case CODE_32BIT:
40fb9820 4398 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4399 i.suffix = LONG_MNEM_SUFFIX;
4400 break;
4401 case CODE_16BIT:
40fb9820 4402 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4403 i.suffix = WORD_MNEM_SUFFIX;
4404 break;
4405 }
4406 }
252b5132 4407
9306ca4a 4408 if (!i.suffix)
29b0f896 4409 {
9306ca4a
JB		 4410 if (!intel_syntax)
4411 {
40fb9820 4412 if (i.tm.opcode_modifier.w)
9306ca4a 4413 {
4eed87de
AM		 4414 as_bad (_("no instruction mnemonic suffix given and "
4415 "no register operands; can't size instruction"));
9306ca4a
JB		 4416 return 0;
4417 }
4418 }
4419 else
4420 {
40fb9820 4421 unsigned int suffixes;
7ab9ffdd 4422
40fb9820
L		 4423 suffixes = !i.tm.opcode_modifier.no_bsuf;
4424 if (!i.tm.opcode_modifier.no_wsuf)
4425 suffixes |= 1 << 1;
4426 if (!i.tm.opcode_modifier.no_lsuf)
4427 suffixes |= 1 << 2;
fc4adea1 4428 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4429 suffixes |= 1 << 3;
4430 if (!i.tm.opcode_modifier.no_ssuf)
4431 suffixes |= 1 << 4;
4432 if (!i.tm.opcode_modifier.no_qsuf)
4433 suffixes |= 1 << 5;
4434
4435 /* There are more than suffix matches. */
4436 if (i.tm.opcode_modifier.w
9306ca4a 4437 || ((suffixes & (suffixes - 1))
40fb9820
L		 4438 && !i.tm.opcode_modifier.defaultsize
4439 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4440 {
4441 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4442 return 0;
4443 }
4444 }
29b0f896 4445 }
252b5132 4446
9306ca4a
JB		 4447 /* Change the opcode based on the operand size given by i.suffix;
4448 We don't need to change things for byte insns. */
4449
582d5edd
L		 4450 if (i.suffix
4451 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4452 && i.suffix != XMMWORD_MNEM_SUFFIX
4453 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4454 {
4455 /* It's not a byte, select word/dword operation. */
40fb9820 4456 if (i.tm.opcode_modifier.w)
29b0f896 4457 {
40fb9820 4458 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4459 i.tm.base_opcode |= 8;
4460 else
4461 i.tm.base_opcode |= 1;
4462 }
0f3f3d8b 4463
29b0f896
AM		 4464 /* Now select between word & dword operations via the operand
4465 size prefix, except for instructions that will ignore this
4466 prefix anyway. */
ca61edf2 4467 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4468 {
ca61edf2
L		 4469 /* The address size override prefix changes the size of the
4470 first operand. */
40fb9820
L		 4471 if ((flag_code == CODE_32BIT
4472 && i.op->regs[0].reg_type.bitfield.reg16)
4473 || (flag_code != CODE_32BIT
4474 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4475 if (!add_prefix (ADDR_PREFIX_OPCODE))
4476 return 0;
4477 }
4478 else if (i.suffix != QWORD_MNEM_SUFFIX
4479 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4480 && !i.tm.opcode_modifier.ignoresize
4481 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4482 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4483 || (flag_code == CODE_64BIT
40fb9820 4484 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4485 {
4486 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4487
40fb9820 4488 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4489 prefix = ADDR_PREFIX_OPCODE;
252b5132 4490
29b0f896
AM		 4491 if (!add_prefix (prefix))
4492 return 0;
24eab124 4493 }
252b5132 4494
29b0f896
AM		 4495 /* Set mode64 for an operand. */
4496 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4497 && flag_code == CODE_64BIT
40fb9820 4498 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4499 {
4500 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4501 need rex64. cmpxchg8b is also a special case. */
4502 if (! (i.operands == 2
4503 && i.tm.base_opcode == 0x90
4504 && i.tm.extension_opcode == None
0dfbf9d7
L		 4505 && operand_type_equal (&i.types [0], &acc64)
4506 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4507 && ! (i.operands == 1
4508 && i.tm.base_opcode == 0xfc7
4509 && i.tm.extension_opcode == 1
40fb9820
L		 4510 && !operand_type_check (i.types [0], reg)
4511 && operand_type_check (i.types [0], anymem)))
f6bee062 4512 i.rex |= REX_W;
46e883c5 4513 }
3e73aa7c 4514
29b0f896
AM		 4515 /* Size floating point instruction. */
4516 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4517 if (i.tm.opcode_modifier.floatmf)
543613e9 4518 i.tm.base_opcode ^= 4;
29b0f896 4519 }
7ecd2f8b 4520
29b0f896
AM		 4521 return 1;
4522}
3e73aa7c 4523
29b0f896 4524static int
543613e9 4525check_byte_reg (void)
29b0f896
AM		 4526{
4527 int op;
543613e9 4528
29b0f896
AM		 4529 for (op = i.operands; --op >= 0;)
4530 {
4531 /* If this is an eight bit register, it's OK. If it's the 16 or
4532 32 bit version of an eight bit register, we will just use the
4533 low portion, and that's OK too. */
40fb9820 4534 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4535 continue;
4536
9344ff29
L		 4537 /* crc32 doesn't generate this warning. */
4538 if (i.tm.base_opcode == 0xf20f38f0)
4539 continue;
4540
40fb9820
L		 4541 if ((i.types[op].bitfield.reg16
4542 || i.types[op].bitfield.reg32
4543 || i.types[op].bitfield.reg64)
4544 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4545 {
4546 /* Prohibit these changes in the 64bit mode, since the
4547 lowering is more complicated. */
4548 if (flag_code == CODE_64BIT
40fb9820 4549 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4550 {
2ca3ace5
L		 4551 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4552 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4553 i.suffix);
4554 return 0;
4555 }
4556#if REGISTER_WARNINGS
4557 if (!quiet_warnings
40fb9820 4558 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4559 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4560 register_prefix,
40fb9820 4561 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4562 ? REGNAM_AL - REGNAM_AX
4563 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4564 register_prefix,
29b0f896
AM		 4565 i.op[op].regs->reg_name,
4566 i.suffix);
4567#endif
4568 continue;
4569 }
4570 /* Any other register is bad. */
40fb9820
L		 4571 if (i.types[op].bitfield.reg16
4572 || i.types[op].bitfield.reg32
4573 || i.types[op].bitfield.reg64
4574 || i.types[op].bitfield.regmmx
4575 || i.types[op].bitfield.regxmm
c0f3af97 4576 || i.types[op].bitfield.regymm
40fb9820
L		 4577 || i.types[op].bitfield.sreg2
4578 || i.types[op].bitfield.sreg3
4579 || i.types[op].bitfield.control
4580 || i.types[op].bitfield.debug
4581 || i.types[op].bitfield.test
4582 || i.types[op].bitfield.floatreg
4583 || i.types[op].bitfield.floatacc)
29b0f896 4584 {
a540244d
L		 4585 as_bad (_("`%s%s' not allowed with `%s%c'"),
4586 register_prefix,
29b0f896
AM		 4587 i.op[op].regs->reg_name,
4588 i.tm.name,
4589 i.suffix);
4590 return 0;
4591 }
4592 }
4593 return 1;
4594}
4595
4596static int
e3bb37b5 4597check_long_reg (void)
29b0f896
AM		 4598{
4599 int op;
4600
4601 for (op = i.operands; --op >= 0;)
4602 /* Reject eight bit registers, except where the template requires
4603 them. (eg. movzb) */
40fb9820
L		 4604 if (i.types[op].bitfield.reg8
4605 && (i.tm.operand_types[op].bitfield.reg16
4606 || i.tm.operand_types[op].bitfield.reg32
4607 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4608 {
a540244d
L		 4609 as_bad (_("`%s%s' not allowed with `%s%c'"),
4610 register_prefix,
29b0f896
AM		 4611 i.op[op].regs->reg_name,
4612 i.tm.name,
4613 i.suffix);
4614 return 0;
4615 }
4616 /* Warn if the e prefix on a general reg is missing. */
4617 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4618 && i.types[op].bitfield.reg16
4619 && (i.tm.operand_types[op].bitfield.reg32
4620 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4621 {
4622 /* Prohibit these changes in the 64bit mode, since the
4623 lowering is more complicated. */
4624 if (flag_code == CODE_64BIT)
252b5132 4625 {
2ca3ace5
L		 4626 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4627 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4628 i.suffix);
4629 return 0;
252b5132 4630 }
29b0f896
AM		 4631#if REGISTER_WARNINGS
4632 else
a540244d
L		 4633 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4634 register_prefix,
29b0f896 4635 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4636 register_prefix,
29b0f896
AM		 4637 i.op[op].regs->reg_name,
4638 i.suffix);
4639#endif
252b5132 4640 }
29b0f896 4641 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4642 else if (i.types[op].bitfield.reg64
4643 && (i.tm.operand_types[op].bitfield.reg32
4644 || i.tm.operand_types[op].bitfield.acc))
252b5132 4645 {
34828aad 4646 if (intel_syntax
ca61edf2 4647 && i.tm.opcode_modifier.toqword
40fb9820 4648 && !i.types[0].bitfield.regxmm)
34828aad 4649 {
ca61edf2 4650 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4651 i.suffix = QWORD_MNEM_SUFFIX;
4652 }
4653 else
4654 {
4655 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4656 register_prefix, i.op[op].regs->reg_name,
4657 i.suffix);
4658 return 0;
4659 }
29b0f896
AM		 4660 }
4661 return 1;
4662}
252b5132 4663
29b0f896 4664static int
e3bb37b5 4665check_qword_reg (void)
29b0f896
AM		 4666{
4667 int op;
252b5132 4668
29b0f896
AM		 4669 for (op = i.operands; --op >= 0; )
4670 /* Reject eight bit registers, except where the template requires
4671 them. (eg. movzb) */
40fb9820
L		 4672 if (i.types[op].bitfield.reg8
4673 && (i.tm.operand_types[op].bitfield.reg16
4674 || i.tm.operand_types[op].bitfield.reg32
4675 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4676 {
a540244d
L		 4677 as_bad (_("`%s%s' not allowed with `%s%c'"),
4678 register_prefix,
29b0f896
AM		 4679 i.op[op].regs->reg_name,
4680 i.tm.name,
4681 i.suffix);
4682 return 0;
4683 }
4684 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4685 else if ((i.types[op].bitfield.reg16
4686 || i.types[op].bitfield.reg32)
4687 && (i.tm.operand_types[op].bitfield.reg32
4688 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4689 {
4690 /* Prohibit these changes in the 64bit mode, since the
4691 lowering is more complicated. */
34828aad 4692 if (intel_syntax
ca61edf2 4693 && i.tm.opcode_modifier.todword
40fb9820 4694 && !i.types[0].bitfield.regxmm)
34828aad 4695 {
ca61edf2 4696 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4697 i.suffix = LONG_MNEM_SUFFIX;
4698 }
4699 else
4700 {
4701 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4702 register_prefix, i.op[op].regs->reg_name,
4703 i.suffix);
4704 return 0;
4705 }
252b5132 4706 }
29b0f896
AM		 4707 return 1;
4708}
252b5132 4709
29b0f896 4710static int
e3bb37b5 4711check_word_reg (void)
29b0f896
AM		 4712{
4713 int op;
4714 for (op = i.operands; --op >= 0;)
4715 /* Reject eight bit registers, except where the template requires
4716 them. (eg. movzb) */
40fb9820
L		 4717 if (i.types[op].bitfield.reg8
4718 && (i.tm.operand_types[op].bitfield.reg16
4719 || i.tm.operand_types[op].bitfield.reg32
4720 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4721 {
a540244d
L		 4722 as_bad (_("`%s%s' not allowed with `%s%c'"),
4723 register_prefix,
29b0f896
AM		 4724 i.op[op].regs->reg_name,
4725 i.tm.name,
4726 i.suffix);
4727 return 0;
4728 }
4729 /* Warn if the e prefix on a general reg is present. */
4730 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4731 && i.types[op].bitfield.reg32
4732 && (i.tm.operand_types[op].bitfield.reg16
4733 || i.tm.operand_types[op].bitfield.acc))
252b5132 4734 {
29b0f896
AM		 4735 /* Prohibit these changes in the 64bit mode, since the
4736 lowering is more complicated. */
4737 if (flag_code == CODE_64BIT)
252b5132 4738 {
2ca3ace5
L		 4739 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4740 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4741 i.suffix);
4742 return 0;
252b5132 4743 }
29b0f896
AM		 4744 else
4745#if REGISTER_WARNINGS
a540244d
L		 4746 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4747 register_prefix,
29b0f896 4748 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4749 register_prefix,
29b0f896
AM		 4750 i.op[op].regs->reg_name,
4751 i.suffix);
4752#endif
4753 }
4754 return 1;
4755}
252b5132 4756
29b0f896 4757static int
40fb9820 4758update_imm (unsigned int j)
29b0f896 4759{
bc0844ae 4760 i386_operand_type overlap = i.types[j];
40fb9820
L		 4761 if ((overlap.bitfield.imm8
4762 || overlap.bitfield.imm8s
4763 || overlap.bitfield.imm16
4764 || overlap.bitfield.imm32
4765 || overlap.bitfield.imm32s
4766 || overlap.bitfield.imm64)
0dfbf9d7
L		 4767 && !operand_type_equal (&overlap, &imm8)
4768 && !operand_type_equal (&overlap, &imm8s)
4769 && !operand_type_equal (&overlap, &imm16)
4770 && !operand_type_equal (&overlap, &imm32)
4771 && !operand_type_equal (&overlap, &imm32s)
4772 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4773 {
4774 if (i.suffix)
4775 {
40fb9820
L		 4776 i386_operand_type temp;
4777
0dfbf9d7 4778 operand_type_set (&temp, 0);
7ab9ffdd 4779 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4780 {
4781 temp.bitfield.imm8 = overlap.bitfield.imm8;
4782 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4783 }
4784 else if (i.suffix == WORD_MNEM_SUFFIX)
4785 temp.bitfield.imm16 = overlap.bitfield.imm16;
4786 else if (i.suffix == QWORD_MNEM_SUFFIX)
4787 {
4788 temp.bitfield.imm64 = overlap.bitfield.imm64;
4789 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4790 }
4791 else
4792 temp.bitfield.imm32 = overlap.bitfield.imm32;
4793 overlap = temp;
29b0f896 4794 }
0dfbf9d7
L		 4795 else if (operand_type_equal (&overlap, &imm16_32_32s)
4796 || operand_type_equal (&overlap, &imm16_32)
4797 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4798 {
40fb9820 4799 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4800 overlap = imm16;
40fb9820 4801 else
65da13b5 4802 overlap = imm32s;
29b0f896 4803 }
0dfbf9d7
L		 4804 if (!operand_type_equal (&overlap, &imm8)
4805 && !operand_type_equal (&overlap, &imm8s)
4806 && !operand_type_equal (&overlap, &imm16)
4807 && !operand_type_equal (&overlap, &imm32)
4808 && !operand_type_equal (&overlap, &imm32s)
4809 && !operand_type_equal (&overlap, &imm64))
29b0f896 4810 {
4eed87de
AM		 4811 as_bad (_("no instruction mnemonic suffix given; "
4812 "can't determine immediate size"));
29b0f896
AM		 4813 return 0;
4814 }
4815 }
40fb9820 4816 i.types[j] = overlap;
29b0f896 4817
40fb9820
L		 4818 return 1;
4819}
4820
4821static int
4822finalize_imm (void)
4823{
bc0844ae 4824 unsigned int j, n;
29b0f896 4825
bc0844ae
L		 4826 /* Update the first 2 immediate operands. */
4827 n = i.operands > 2 ? 2 : i.operands;
4828 if (n)
4829 {
4830 for (j = 0; j < n; j++)
4831 if (update_imm (j) == 0)
4832 return 0;
40fb9820 4833
bc0844ae
L		 4834 /* The 3rd operand can't be immediate operand. */
4835 gas_assert (operand_type_check (i.types[2], imm) == 0);
4836 }
29b0f896
AM		 4837
4838 return 1;
4839}
4840
c0f3af97
L		 4841static int
4842bad_implicit_operand (int xmm)
4843{
91d6fa6a
NC		 4844 const char *ireg = xmm ? "xmm0" : "ymm0";
4845
c0f3af97
L		 4846 if (intel_syntax)
4847 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4848 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4849 else
4850 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4851 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4852 return 0;
4853}
4854
29b0f896 4855static int
e3bb37b5 4856process_operands (void)
29b0f896
AM		 4857{
4858 /* Default segment register this instruction will use for memory
4859 accesses. 0 means unknown. This is only for optimizing out
4860 unnecessary segment overrides. */
4861 const seg_entry *default_seg = 0;
4862
2426c15f 4863 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4864 {
91d6fa6a
NC		 4865 unsigned int dupl = i.operands;
4866 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4867 unsigned int j;
4868
c0f3af97 4869 /* The destination must be an xmm register. */
9c2799c2 4870 gas_assert (i.reg_operands
91d6fa6a 4871 && MAX_OPERANDS > dupl
7ab9ffdd 4872 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4873
4874 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4875 {
c0f3af97 4876 /* The first operand is implicit and must be xmm0. */
9c2799c2 4877 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4878 if (i.op[0].regs->reg_num != 0)
4879 return bad_implicit_operand (1);
4880
8cd7925b 4881 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4882 {
4883 /* Keep xmm0 for instructions with VEX prefix and 3
4884 sources. */
4885 goto duplicate;
4886 }
e2ec9d29 4887 else
c0f3af97
L		 4888 {
4889 /* We remove the first xmm0 and keep the number of
4890 operands unchanged, which in fact duplicates the
4891 destination. */
4892 for (j = 1; j < i.operands; j++)
4893 {
4894 i.op[j - 1] = i.op[j];
4895 i.types[j - 1] = i.types[j];
4896 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4897 }
4898 }
4899 }
4900 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4901 {
91d6fa6a 4902 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4903 && (i.tm.opcode_modifier.vexsources
4904 == VEX3SOURCES));
c0f3af97
L		 4905
4906 /* Add the implicit xmm0 for instructions with VEX prefix
4907 and 3 sources. */
4908 for (j = i.operands; j > 0; j--)
4909 {
4910 i.op[j] = i.op[j - 1];
4911 i.types[j] = i.types[j - 1];
4912 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4913 }
4914 i.op[0].regs
4915 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4916 i.types[0] = regxmm;
c0f3af97
L		 4917 i.tm.operand_types[0] = regxmm;
4918
4919 i.operands += 2;
4920 i.reg_operands += 2;
4921 i.tm.operands += 2;
4922
91d6fa6a 4923 dupl++;
c0f3af97 4924 dest++;
91d6fa6a
NC		 4925 i.op[dupl] = i.op[dest];
4926 i.types[dupl] = i.types[dest];
4927 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4928 }
c0f3af97
L		 4929 else
4930 {
4931duplicate:
4932 i.operands++;
4933 i.reg_operands++;
4934 i.tm.operands++;
4935
91d6fa6a
NC		 4936 i.op[dupl] = i.op[dest];
4937 i.types[dupl] = i.types[dest];
4938 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4939 }
4940
4941 if (i.tm.opcode_modifier.immext)
4942 process_immext ();
4943 }
4944 else if (i.tm.opcode_modifier.firstxmm0)
4945 {
4946 unsigned int j;
4947
4948 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4949 gas_assert (i.reg_operands
7ab9ffdd
L		 4950 && (operand_type_equal (&i.types[0], &regxmm)
4951 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4952 if (i.op[0].regs->reg_num != 0)
4953 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4954
4955 for (j = 1; j < i.operands; j++)
4956 {
4957 i.op[j - 1] = i.op[j];
4958 i.types[j - 1] = i.types[j];
4959
4960 /* We need to adjust fields in i.tm since they are used by
4961 build_modrm_byte. */
4962 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4963 }
4964
e2ec9d29
L		 4965 i.operands--;
4966 i.reg_operands--;
e2ec9d29
L		 4967 i.tm.operands--;
4968 }
4969 else if (i.tm.opcode_modifier.regkludge)
4970 {
4971 /* The imul $imm, %reg instruction is converted into
4972 imul $imm, %reg, %reg, and the clr %reg instruction
4973 is converted into xor %reg, %reg. */
4974
4975 unsigned int first_reg_op;
4976
4977 if (operand_type_check (i.types[0], reg))
4978 first_reg_op = 0;
4979 else
4980 first_reg_op = 1;
4981 /* Pretend we saw the extra register operand. */
9c2799c2 4982 gas_assert (i.reg_operands == 1
7ab9ffdd 4983 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4984 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4985 i.types[first_reg_op + 1] = i.types[first_reg_op];
4986 i.operands++;
4987 i.reg_operands++;
29b0f896
AM		 4988 }
4989
40fb9820 4990 if (i.tm.opcode_modifier.shortform)
29b0f896 4991 {
40fb9820
L		 4992 if (i.types[0].bitfield.sreg2
4993 || i.types[0].bitfield.sreg3)
29b0f896 4994 {
4eed87de
AM		 4995 if (i.tm.base_opcode == POP_SEG_SHORT
4996 && i.op[0].regs->reg_num == 1)
29b0f896 4997 {
a87af027 4998 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4999 return 0;
29b0f896 5000 }
4eed87de
AM		 5001 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5002 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5003 i.rex |= REX_B;
4eed87de
AM		 5004 }
5005 else
5006 {
7ab9ffdd 5007 /* The register or float register operand is in operand
85f10a01 5008 0 or 1. */
40fb9820 5009 unsigned int op;
7ab9ffdd
L		 5010
5011 if (i.types[0].bitfield.floatreg
5012 || operand_type_check (i.types[0], reg))
5013 op = 0;
5014 else
5015 op = 1;
4eed87de
AM		 5016 /* Register goes in low 3 bits of opcode. */
5017 i.tm.base_opcode |= i.op[op].regs->reg_num;
5018 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5019 i.rex |= REX_B;
40fb9820 5020 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5021 {
4eed87de
AM		 5022 /* Warn about some common errors, but press on regardless.
5023 The first case can be generated by gcc (<= 2.8.1). */
5024 if (i.operands == 2)
5025 {
5026 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5027 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5028 register_prefix, i.op[!intel_syntax].regs->reg_name,
5029 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5030 }
5031 else
5032 {
5033 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5034 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5035 register_prefix, i.op[0].regs->reg_name);
4eed87de 5036 }
29b0f896
AM		 5037 }
5038 }
5039 }
40fb9820 5040 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5041 {
5042 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5043 must be put into the modrm byte). Now, we make the modrm and
5044 index base bytes based on all the info we've collected. */
29b0f896
AM		 5045
5046 default_seg = build_modrm_byte ();
5047 }
8a2ed489 5048 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5049 {
5050 default_seg = &ds;
5051 }
40fb9820 5052 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5053 {
5054 /* For the string instructions that allow a segment override
5055 on one of their operands, the default segment is ds. */
5056 default_seg = &ds;
5057 }
5058
75178d9d
L		 5059 if (i.tm.base_opcode == 0x8d /* lea */
5060 && i.seg[0]
5061 && !quiet_warnings)
30123838 5062 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5063
5064 /* If a segment was explicitly specified, and the specified segment
5065 is not the default, use an opcode prefix to select it. If we
5066 never figured out what the default segment is, then default_seg
5067 will be zero at this point, and the specified segment prefix will
5068 always be used. */
29b0f896
AM		 5069 if ((i.seg[0]) && (i.seg[0] != default_seg))
5070 {
5071 if (!add_prefix (i.seg[0]->seg_prefix))
5072 return 0;
5073 }
5074 return 1;
5075}
5076
5077static const seg_entry *
e3bb37b5 5078build_modrm_byte (void)
29b0f896
AM		 5079{
5080 const seg_entry *default_seg = 0;
c0f3af97 5081 unsigned int source, dest;
8cd7925b 5082 int vex_3_sources;
c0f3af97
L		 5083
5084 /* The first operand of instructions with VEX prefix and 3 sources
5085 must be VEX_Imm4. */
8cd7925b 5086 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5087 if (vex_3_sources)
5088 {
91d6fa6a 5089 unsigned int nds, reg_slot;
4c2c6516 5090 expressionS *exp;
c0f3af97 5091
922d8de8 5092 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5093 && i.tm.opcode_modifier.immext)
5094 {
5095 dest = i.operands - 2;
5096 gas_assert (dest == 3);
5097 }
922d8de8 5098 else
a683cc34 5099 dest = i.operands - 1;
c0f3af97 5100 nds = dest - 1;
922d8de8 5101
a683cc34
SP		 5102 /* There are 2 kinds of instructions:
5103 1. 5 operands: 4 register operands or 3 register operands
5104 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5105 VexW0 or VexW1. The destination must be either XMM or YMM
5106 register.
5107 2. 4 operands: 4 register operands or 3 register operands
5108 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5109 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5110 || (i.reg_operands == 3 && i.mem_operands == 1))
5111 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5112 && (i.tm.opcode_modifier.veximmext
5113 || (i.imm_operands == 1
5114 && i.types[0].bitfield.vec_imm4
5115 && (i.tm.opcode_modifier.vexw == VEXW0
5116 || i.tm.opcode_modifier.vexw == VEXW1)
5117 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5118 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5119
5120 if (i.imm_operands == 0)
5121 {
5122 /* When there is no immediate operand, generate an 8bit
5123 immediate operand to encode the first operand. */
5124 exp = &im_expressions[i.imm_operands++];
5125 i.op[i.operands].imms = exp;
5126 i.types[i.operands] = imm8;
5127 i.operands++;
5128 /* If VexW1 is set, the first operand is the source and
5129 the second operand is encoded in the immediate operand. */
5130 if (i.tm.opcode_modifier.vexw == VEXW1)
5131 {
5132 source = 0;
5133 reg_slot = 1;
5134 }
5135 else
5136 {
5137 source = 1;
5138 reg_slot = 0;
5139 }
5140
5141 /* FMA swaps REG and NDS. */
5142 if (i.tm.cpu_flags.bitfield.cpufma)
5143 {
5144 unsigned int tmp;
5145 tmp = reg_slot;
5146 reg_slot = nds;
5147 nds = tmp;
5148 }
5149
24981e7b
L		 5150 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5151 &regxmm)
a683cc34
SP		 5152 || operand_type_equal (&i.tm.operand_types[reg_slot],
5153 &regymm));
5154 exp->X_op = O_constant;
5155 exp->X_add_number
5156 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5157 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5158 << 4);
a683cc34 5159 }
922d8de8 5160 else
a683cc34
SP		 5161 {
5162 unsigned int imm_slot;
5163
5164 if (i.tm.opcode_modifier.vexw == VEXW0)
5165 {
5166 /* If VexW0 is set, the third operand is the source and
5167 the second operand is encoded in the immediate
5168 operand. */
5169 source = 2;
5170 reg_slot = 1;
5171 }
5172 else
5173 {
5174 /* VexW1 is set, the second operand is the source and
5175 the third operand is encoded in the immediate
5176 operand. */
5177 source = 1;
5178 reg_slot = 2;
5179 }
5180
5181 if (i.tm.opcode_modifier.immext)
5182 {
5183 /* When ImmExt is set, the immdiate byte is the last
5184 operand. */
5185 imm_slot = i.operands - 1;
5186 source--;
5187 reg_slot--;
5188 }
5189 else
5190 {
5191 imm_slot = 0;
5192
5193 /* Turn on Imm8 so that output_imm will generate it. */
5194 i.types[imm_slot].bitfield.imm8 = 1;
5195 }
5196
24981e7b
L		 5197 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5198 &regxmm)
5199 || operand_type_equal (&i.tm.operand_types[reg_slot],
5200 &regymm));
a683cc34
SP		 5201 i.op[imm_slot].imms->X_add_number
5202 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5203 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5204 << 4);
a683cc34
SP		 5205 }
5206
5207 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5208 || operand_type_equal (&i.tm.operand_types[nds],
5209 &regymm));
dae39acc 5210 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5211 }
5212 else
5213 source = dest = 0;
29b0f896
AM		 5214
5215 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5216 implicit registers do not count. If there are 3 register
5217 operands, it must be a instruction with VexNDS. For a
5218 instruction with VexNDD, the destination register is encoded
5219 in VEX prefix. If there are 4 register operands, it must be
5220 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5221 if (i.mem_operands == 0
5222 && ((i.reg_operands == 2
2426c15f 5223 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5224 || (i.reg_operands == 3
2426c15f 5225 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5226 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5227 {
cab737b9
L		 5228 switch (i.operands)
5229 {
5230 case 2:
5231 source = 0;
5232 break;
5233 case 3:
c81128dc
L		 5234 /* When there are 3 operands, one of them may be immediate,
5235 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5236 the first operand must be shift count register (cl) or it
5237 is an instruction with VexNDS. */
9c2799c2 5238 gas_assert (i.imm_operands == 1
7ab9ffdd 5239 || (i.imm_operands == 0
2426c15f 5240 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5241 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5242 if (operand_type_check (i.types[0], imm)
5243 || i.types[0].bitfield.shiftcount)
5244 source = 1;
5245 else
5246 source = 0;
cab737b9
L		 5247 break;
5248 case 4:
368d64cc
L		 5249 /* When there are 4 operands, the first two must be 8bit
5250 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5251 one.
5252
5253 For instructions with VexNDS, if the first operand
5254 an imm8, the source operand is the 2nd one. If the last
5255 operand is imm8, the source operand is the first one. */
9c2799c2 5256 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5257 && i.types[0].bitfield.imm8
5258 && i.types[1].bitfield.imm8)
2426c15f 5259 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5260 && i.imm_operands == 1
5261 && (i.types[0].bitfield.imm8
5262 || i.types[i.operands - 1].bitfield.imm8)));
2426c15f 5263 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5264 {
5265 if (i.types[0].bitfield.imm8)
5266 source = 1;
5267 else
5268 source = 0;
5269 }
5270 else
5271 source = 2;
5272 break;
5273 case 5:
cab737b9
L		 5274 break;
5275 default:
5276 abort ();
5277 }
5278
c0f3af97
L		 5279 if (!vex_3_sources)
5280 {
5281 dest = source + 1;
5282
2426c15f 5283 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5284 {
5285 /* For instructions with VexNDS, the register-only
5286 source operand must be XMM or YMM register. It is
fa99fab2
L		 5287 encoded in VEX prefix. We need to clear RegMem bit
5288 before calling operand_type_equal. */
5289 i386_operand_type op = i.tm.operand_types[dest];
5290 op.bitfield.regmem = 0;
c0f3af97 5291 if ((dest + 1) >= i.operands
fa99fab2
L		 5292 || (!operand_type_equal (&op, &regxmm)
5293 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5294 abort ();
5295 i.vex.register_specifier = i.op[dest].regs;
5296 dest++;
5297 }
5298 }
29b0f896
AM		 5299
5300 i.rm.mode = 3;
5301 /* One of the register operands will be encoded in the i.tm.reg
5302 field, the other in the combined i.tm.mode and i.tm.regmem
5303 fields. If no form of this instruction supports a memory
5304 destination operand, then we assume the source operand may
5305 sometimes be a memory operand and so we need to store the
5306 destination in the i.rm.reg field. */
40fb9820
L		 5307 if (!i.tm.operand_types[dest].bitfield.regmem
5308 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5309 {
5310 i.rm.reg = i.op[dest].regs->reg_num;
5311 i.rm.regmem = i.op[source].regs->reg_num;
5312 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5313 i.rex |= REX_R;
29b0f896 5314 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5315 i.rex |= REX_B;
29b0f896
AM		 5316 }
5317 else
5318 {
5319 i.rm.reg = i.op[source].regs->reg_num;
5320 i.rm.regmem = i.op[dest].regs->reg_num;
5321 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5322 i.rex |= REX_B;
29b0f896 5323 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5324 i.rex |= REX_R;
29b0f896 5325 }
161a04f6 5326 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5327 {
40fb9820
L		 5328 if (!i.types[0].bitfield.control
5329 && !i.types[1].bitfield.control)
c4a530c5 5330 abort ();
161a04f6 5331 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5332 add_prefix (LOCK_PREFIX_OPCODE);
5333 }
29b0f896
AM		 5334 }
5335 else
5336 { /* If it's not 2 reg operands... */
c0f3af97
L		 5337 unsigned int mem;
5338
29b0f896
AM		 5339 if (i.mem_operands)
5340 {
5341 unsigned int fake_zero_displacement = 0;
99018f42 5342 unsigned int op;
4eed87de 5343
7ab9ffdd
L		 5344 for (op = 0; op < i.operands; op++)
5345 if (operand_type_check (i.types[op], anymem))
5346 break;
7ab9ffdd 5347 gas_assert (op < i.operands);
29b0f896
AM		 5348
5349 default_seg = &ds;
5350
5351 if (i.base_reg == 0)
5352 {
5353 i.rm.mode = 0;
5354 if (!i.disp_operands)
5355 fake_zero_displacement = 1;
5356 if (i.index_reg == 0)
5357 {
5358 /* Operand is just <disp> */
20f0a1fc 5359 if (flag_code == CODE_64BIT)
29b0f896
AM		 5360 {
5361 /* 64bit mode overwrites the 32bit absolute
5362 addressing by RIP relative addressing and
5363 absolute addressing is encoded by one of the
5364 redundant SIB forms. */
5365 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5366 i.sib.base = NO_BASE_REGISTER;
5367 i.sib.index = NO_INDEX_REGISTER;
fc225355 5368 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5369 ? disp32s : disp32);
20f0a1fc 5370 }
fc225355
L		 5371 else if ((flag_code == CODE_16BIT)
5372 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5373 {
5374 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5375 i.types[op] = disp16;
20f0a1fc
NC		 5376 }
5377 else
5378 {
5379 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5380 i.types[op] = disp32;
29b0f896
AM		 5381 }
5382 }
5383 else /* !i.base_reg && i.index_reg */
5384 {
db51cc60
L		 5385 if (i.index_reg->reg_num == RegEiz
5386 || i.index_reg->reg_num == RegRiz)
5387 i.sib.index = NO_INDEX_REGISTER;
5388 else
5389 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5390 i.sib.base = NO_BASE_REGISTER;
5391 i.sib.scale = i.log2_scale_factor;
5392 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5393 i.types[op].bitfield.disp8 = 0;
5394 i.types[op].bitfield.disp16 = 0;
5395 i.types[op].bitfield.disp64 = 0;
29b0f896 5396 if (flag_code != CODE_64BIT)
40fb9820
L		 5397 {
5398 /* Must be 32 bit */
5399 i.types[op].bitfield.disp32 = 1;
5400 i.types[op].bitfield.disp32s = 0;
5401 }
29b0f896 5402 else
40fb9820
L		 5403 {
5404 i.types[op].bitfield.disp32 = 0;
5405 i.types[op].bitfield.disp32s = 1;
5406 }
29b0f896 5407 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5408 i.rex |= REX_X;
29b0f896
AM		 5409 }
5410 }
5411 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5412 else if (i.base_reg->reg_num == RegRip ||
5413 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5414 {
5415 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5416 i.types[op].bitfield.disp8 = 0;
5417 i.types[op].bitfield.disp16 = 0;
5418 i.types[op].bitfield.disp32 = 0;
5419 i.types[op].bitfield.disp32s = 1;
5420 i.types[op].bitfield.disp64 = 0;
71903a11 5421 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5422 if (! i.disp_operands)
5423 fake_zero_displacement = 1;
29b0f896 5424 }
40fb9820 5425 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5426 {
5427 switch (i.base_reg->reg_num)
5428 {
5429 case 3: /* (%bx) */
5430 if (i.index_reg == 0)
5431 i.rm.regmem = 7;
5432 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5433 i.rm.regmem = i.index_reg->reg_num - 6;
5434 break;
5435 case 5: /* (%bp) */
5436 default_seg = &ss;
5437 if (i.index_reg == 0)
5438 {
5439 i.rm.regmem = 6;
40fb9820 5440 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5441 {
5442 /* fake (%bp) into 0(%bp) */
40fb9820 5443 i.types[op].bitfield.disp8 = 1;
252b5132 5444 fake_zero_displacement = 1;
29b0f896
AM		 5445 }
5446 }
5447 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5448 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5449 break;
5450 default: /* (%si) -> 4 or (%di) -> 5 */
5451 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5452 }
5453 i.rm.mode = mode_from_disp_size (i.types[op]);
5454 }
5455 else /* i.base_reg and 32/64 bit mode */
5456 {
5457 if (flag_code == CODE_64BIT
40fb9820
L		 5458 && operand_type_check (i.types[op], disp))
5459 {
5460 i386_operand_type temp;
0dfbf9d7 5461 operand_type_set (&temp, 0);
40fb9820
L		 5462 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5463 i.types[op] = temp;
5464 if (i.prefix[ADDR_PREFIX] == 0)
5465 i.types[op].bitfield.disp32s = 1;
5466 else
5467 i.types[op].bitfield.disp32 = 1;
5468 }
20f0a1fc 5469
29b0f896
AM		 5470 i.rm.regmem = i.base_reg->reg_num;
5471 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5472 i.rex |= REX_B;
29b0f896
AM		 5473 i.sib.base = i.base_reg->reg_num;
5474 /* x86-64 ignores REX prefix bit here to avoid decoder
5475 complications. */
5476 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5477 {
5478 default_seg = &ss;
5479 if (i.disp_operands == 0)
5480 {
5481 fake_zero_displacement = 1;
40fb9820 5482 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5483 }
5484 }
5485 else if (i.base_reg->reg_num == ESP_REG_NUM)
5486 {
5487 default_seg = &ss;
5488 }
5489 i.sib.scale = i.log2_scale_factor;
5490 if (i.index_reg == 0)
5491 {
5492 /* <disp>(%esp) becomes two byte modrm with no index
5493 register. We've already stored the code for esp
5494 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5495 Any base register besides %esp will not use the
5496 extra modrm byte. */
5497 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5498 }
5499 else
5500 {
db51cc60
L		 5501 if (i.index_reg->reg_num == RegEiz
5502 || i.index_reg->reg_num == RegRiz)
5503 i.sib.index = NO_INDEX_REGISTER;
5504 else
5505 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5506 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5507 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5508 i.rex |= REX_X;
29b0f896 5509 }
67a4f2b7
AO		 5510
5511 if (i.disp_operands
5512 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5513 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5514 i.rm.mode = 0;
5515 else
5516 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5517 }
252b5132 5518
29b0f896
AM		 5519 if (fake_zero_displacement)
5520 {
5521 /* Fakes a zero displacement assuming that i.types[op]
5522 holds the correct displacement size. */
5523 expressionS *exp;
5524
9c2799c2 5525 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5526 exp = &disp_expressions[i.disp_operands++];
5527 i.op[op].disps = exp;
5528 exp->X_op = O_constant;
5529 exp->X_add_number = 0;
5530 exp->X_add_symbol = (symbolS *) 0;
5531 exp->X_op_symbol = (symbolS *) 0;
5532 }
c0f3af97
L		 5533
5534 mem = op;
29b0f896 5535 }
c0f3af97
L		 5536 else
5537 mem = ~0;
252b5132 5538
8c43a48b 5539 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5540 {
5541 if (operand_type_check (i.types[0], imm))
5542 i.vex.register_specifier = NULL;
5543 else
5544 {
5545 /* VEX.vvvv encodes one of the sources when the first
5546 operand is not an immediate. */
1ef99a7b 5547 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5548 i.vex.register_specifier = i.op[0].regs;
5549 else
5550 i.vex.register_specifier = i.op[1].regs;
5551 }
5552
5553 /* Destination is a XMM register encoded in the ModRM.reg
5554 and VEX.R bit. */
5555 i.rm.reg = i.op[2].regs->reg_num;
5556 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5557 i.rex |= REX_R;
5558
5559 /* ModRM.rm and VEX.B encodes the other source. */
5560 if (!i.mem_operands)
5561 {
5562 i.rm.mode = 3;
5563
1ef99a7b 5564 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5565 i.rm.regmem = i.op[1].regs->reg_num;
5566 else
5567 i.rm.regmem = i.op[0].regs->reg_num;
5568
5569 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5570 i.rex |= REX_B;
5571 }
5572 }
2426c15f 5573 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5574 {
5575 i.vex.register_specifier = i.op[2].regs;
5576 if (!i.mem_operands)
5577 {
5578 i.rm.mode = 3;
5579 i.rm.regmem = i.op[1].regs->reg_num;
5580 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5581 i.rex |= REX_B;
5582 }
5583 }
29b0f896
AM		 5584 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5585 (if any) based on i.tm.extension_opcode. Again, we must be
5586 careful to make sure that segment/control/debug/test/MMX
5587 registers are coded into the i.rm.reg field. */
f88c9eb0 5588 else if (i.reg_operands)
29b0f896 5589 {
99018f42 5590 unsigned int op;
7ab9ffdd
L		 5591 unsigned int vex_reg = ~0;
5592
5593 for (op = 0; op < i.operands; op++)
5594 if (i.types[op].bitfield.reg8
5595 || i.types[op].bitfield.reg16
5596 || i.types[op].bitfield.reg32
5597 || i.types[op].bitfield.reg64
5598 || i.types[op].bitfield.regmmx
5599 || i.types[op].bitfield.regxmm
5600 || i.types[op].bitfield.regymm
5601 || i.types[op].bitfield.sreg2
5602 || i.types[op].bitfield.sreg3
5603 || i.types[op].bitfield.control
5604 || i.types[op].bitfield.debug
5605 || i.types[op].bitfield.test)
5606 break;
c0209578 5607
7ab9ffdd
L		 5608 if (vex_3_sources)
5609 op = dest;
2426c15f 5610 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5611 {
5612 /* For instructions with VexNDS, the register-only
5613 source operand is encoded in VEX prefix. */
5614 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5615
7ab9ffdd 5616 if (op > mem)
c0f3af97 5617 {
7ab9ffdd
L		 5618 vex_reg = op++;
5619 gas_assert (op < i.operands);
c0f3af97
L		 5620 }
5621 else
c0f3af97 5622 {
7ab9ffdd
L		 5623 vex_reg = op + 1;
5624 gas_assert (vex_reg < i.operands);
c0f3af97 5625 }
7ab9ffdd 5626 }
2426c15f 5627 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5628 {
5629 /* For instructions with VexNDD, there should be
5630 no memory operand and the register destination
5631 is encoded in VEX prefix. */
5632 gas_assert (i.mem_operands == 0
5633 && (op + 2) == i.operands);
5634 vex_reg = op + 1;
5635 }
5636 else
5637 gas_assert (op < i.operands);
99018f42 5638
7ab9ffdd
L		 5639 if (vex_reg != (unsigned int) ~0)
5640 {
5641 gas_assert (i.reg_operands == 2);
5642
5643 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5644 &regxmm)
7ab9ffdd
L		 5645 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5646 &regymm))
5647 abort ();
f88c9eb0 5648
7ab9ffdd
L		 5649 i.vex.register_specifier = i.op[vex_reg].regs;
5650 }
5651
1b9f0c97
L		 5652 /* Don't set OP operand twice. */
5653 if (vex_reg != op)
7ab9ffdd 5654 {
1b9f0c97
L		 5655 /* If there is an extension opcode to put here, the
5656 register number must be put into the regmem field. */
5657 if (i.tm.extension_opcode != None)
5658 {
5659 i.rm.regmem = i.op[op].regs->reg_num;
5660 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5661 i.rex |= REX_B;
5662 }
5663 else
5664 {
5665 i.rm.reg = i.op[op].regs->reg_num;
5666 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5667 i.rex |= REX_R;
5668 }
7ab9ffdd 5669 }
252b5132 5670
29b0f896
AM		 5671 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5672 must set it to 3 to indicate this is a register operand
5673 in the regmem field. */
5674 if (!i.mem_operands)
5675 i.rm.mode = 3;
5676 }
252b5132 5677
29b0f896 5678 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5679 if (i.tm.extension_opcode != None)
29b0f896
AM		 5680 i.rm.reg = i.tm.extension_opcode;
5681 }
5682 return default_seg;
5683}
252b5132 5684
29b0f896 5685static void
e3bb37b5 5686output_branch (void)
29b0f896
AM		 5687{
5688 char *p;
5689 int code16;
5690 int prefix;
5691 relax_substateT subtype;
5692 symbolS *sym;
5693 offsetT off;
5694
5695 code16 = 0;
5696 if (flag_code == CODE_16BIT)
5697 code16 = CODE16;
5698
5699 prefix = 0;
5700 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5701 {
29b0f896
AM		 5702 prefix = 1;
5703 i.prefixes -= 1;
5704 code16 ^= CODE16;
252b5132 5705 }
29b0f896
AM		 5706 /* Pentium4 branch hints. */
5707 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5708 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5709 {
29b0f896
AM		 5710 prefix++;
5711 i.prefixes--;
5712 }
5713 if (i.prefix[REX_PREFIX] != 0)
5714 {
5715 prefix++;
5716 i.prefixes--;
2f66722d
AM		 5717 }
5718
29b0f896
AM		 5719 if (i.prefixes != 0 && !intel_syntax)
5720 as_warn (_("skipping prefixes on this instruction"));
5721
5722 /* It's always a symbol; End frag & setup for relax.
5723 Make sure there is enough room in this frag for the largest
5724 instruction we may generate in md_convert_frag. This is 2
5725 bytes for the opcode and room for the prefix and largest
5726 displacement. */
5727 frag_grow (prefix + 2 + 4);
5728 /* Prefix and 1 opcode byte go in fr_fix. */
5729 p = frag_more (prefix + 1);
5730 if (i.prefix[DATA_PREFIX] != 0)
5731 *p++ = DATA_PREFIX_OPCODE;
5732 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5733 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5734 *p++ = i.prefix[SEG_PREFIX];
5735 if (i.prefix[REX_PREFIX] != 0)
5736 *p++ = i.prefix[REX_PREFIX];
5737 *p = i.tm.base_opcode;
5738
5739 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5740 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5741 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5742 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5743 else
5744 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5745 subtype |= code16;
3e73aa7c 5746
29b0f896
AM		 5747 sym = i.op[0].disps->X_add_symbol;
5748 off = i.op[0].disps->X_add_number;
3e73aa7c 5749
29b0f896
AM		 5750 if (i.op[0].disps->X_op != O_constant
5751 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5752 {
29b0f896
AM		 5753 /* Handle complex expressions. */
5754 sym = make_expr_symbol (i.op[0].disps);
5755 off = 0;
5756 }
3e73aa7c 5757
29b0f896
AM		 5758 /* 1 possible extra opcode + 4 byte displacement go in var part.
5759 Pass reloc in fr_var. */
5760 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5761}
3e73aa7c 5762
29b0f896 5763static void
e3bb37b5 5764output_jump (void)
29b0f896
AM		 5765{
5766 char *p;
5767 int size;
3e02c1cc 5768 fixS *fixP;
29b0f896 5769
40fb9820 5770 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5771 {
5772 /* This is a loop or jecxz type instruction. */
5773 size = 1;
5774 if (i.prefix[ADDR_PREFIX] != 0)
5775 {
5776 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5777 i.prefixes -= 1;
5778 }
5779 /* Pentium4 branch hints. */
5780 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5781 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5782 {
5783 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5784 i.prefixes--;
3e73aa7c
JH		 5785 }
5786 }
29b0f896
AM		 5787 else
5788 {
5789 int code16;
3e73aa7c 5790
29b0f896
AM		 5791 code16 = 0;
5792 if (flag_code == CODE_16BIT)
5793 code16 = CODE16;
3e73aa7c 5794
29b0f896
AM		 5795 if (i.prefix[DATA_PREFIX] != 0)
5796 {
5797 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5798 i.prefixes -= 1;
5799 code16 ^= CODE16;
5800 }
252b5132 5801
29b0f896
AM		 5802 size = 4;
5803 if (code16)
5804 size = 2;
5805 }
9fcc94b6 5806
29b0f896
AM		 5807 if (i.prefix[REX_PREFIX] != 0)
5808 {
5809 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5810 i.prefixes -= 1;
5811 }
252b5132 5812
29b0f896
AM		 5813 if (i.prefixes != 0 && !intel_syntax)
5814 as_warn (_("skipping prefixes on this instruction"));
e0890092 5815
29b0f896
AM		 5816 p = frag_more (1 + size);
5817 *p++ = i.tm.base_opcode;
e0890092 5818
3e02c1cc
AM		 5819 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5820 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5821
5822 /* All jumps handled here are signed, but don't use a signed limit
5823 check for 32 and 16 bit jumps as we want to allow wrap around at
5824 4G and 64k respectively. */
5825 if (size == 1)
5826 fixP->fx_signed = 1;
29b0f896 5827}
e0890092 5828
29b0f896 5829static void
e3bb37b5 5830output_interseg_jump (void)
29b0f896
AM		 5831{
5832 char *p;
5833 int size;
5834 int prefix;
5835 int code16;
252b5132 5836
29b0f896
AM		 5837 code16 = 0;
5838 if (flag_code == CODE_16BIT)
5839 code16 = CODE16;
a217f122 5840
29b0f896
AM		 5841 prefix = 0;
5842 if (i.prefix[DATA_PREFIX] != 0)
5843 {
5844 prefix = 1;
5845 i.prefixes -= 1;
5846 code16 ^= CODE16;
5847 }
5848 if (i.prefix[REX_PREFIX] != 0)
5849 {
5850 prefix++;
5851 i.prefixes -= 1;
5852 }
252b5132 5853
29b0f896
AM		 5854 size = 4;
5855 if (code16)
5856 size = 2;
252b5132 5857
29b0f896
AM		 5858 if (i.prefixes != 0 && !intel_syntax)
5859 as_warn (_("skipping prefixes on this instruction"));
252b5132 5860
29b0f896
AM		 5861 /* 1 opcode; 2 segment; offset */
5862 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5863
29b0f896
AM		 5864 if (i.prefix[DATA_PREFIX] != 0)
5865 *p++ = DATA_PREFIX_OPCODE;
252b5132 5866
29b0f896
AM		 5867 if (i.prefix[REX_PREFIX] != 0)
5868 *p++ = i.prefix[REX_PREFIX];
252b5132 5869
29b0f896
AM		 5870 *p++ = i.tm.base_opcode;
5871 if (i.op[1].imms->X_op == O_constant)
5872 {
5873 offsetT n = i.op[1].imms->X_add_number;
252b5132 5874
29b0f896
AM		 5875 if (size == 2
5876 && !fits_in_unsigned_word (n)
5877 && !fits_in_signed_word (n))
5878 {
5879 as_bad (_("16-bit jump out of range"));
5880 return;
5881 }
5882 md_number_to_chars (p, n, size);
5883 }
5884 else
5885 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5886 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5887 if (i.op[0].imms->X_op != O_constant)
5888 as_bad (_("can't handle non absolute segment in `%s'"),
5889 i.tm.name);
5890 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5891}
a217f122 5892
29b0f896 5893static void
e3bb37b5 5894output_insn (void)
29b0f896 5895{
2bbd9c25
JJ		 5896 fragS *insn_start_frag;
5897 offsetT insn_start_off;
5898
29b0f896
AM		 5899 /* Tie dwarf2 debug info to the address at the start of the insn.
5900 We can't do this after the insn has been output as the current
5901 frag may have been closed off. eg. by frag_var. */
5902 dwarf2_emit_insn (0);
5903
2bbd9c25
JJ		 5904 insn_start_frag = frag_now;
5905 insn_start_off = frag_now_fix ();
5906
29b0f896 5907 /* Output jumps. */
40fb9820 5908 if (i.tm.opcode_modifier.jump)
29b0f896 5909 output_branch ();
40fb9820
L		 5910 else if (i.tm.opcode_modifier.jumpbyte
5911 || i.tm.opcode_modifier.jumpdword)
29b0f896 5912 output_jump ();
40fb9820 5913 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5914 output_interseg_jump ();
5915 else
5916 {
5917 /* Output normal instructions here. */
5918 char *p;
5919 unsigned char *q;
47465058 5920 unsigned int j;
331d2d0d 5921 unsigned int prefix;
4dffcebc 5922
c0f3af97
L		 5923 /* Since the VEX prefix contains the implicit prefix, we don't
5924 need the explicit prefix. */
5925 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5926 {
c0f3af97 5927 switch (i.tm.opcode_length)
bc4bd9ab 5928 {
c0f3af97
L		 5929 case 3:
5930 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5931 {
c0f3af97
L		 5932 prefix = (i.tm.base_opcode >> 24) & 0xff;
5933 goto check_prefix;
5934 }
5935 break;
5936 case 2:
5937 if ((i.tm.base_opcode & 0xff0000) != 0)
5938 {
5939 prefix = (i.tm.base_opcode >> 16) & 0xff;
5940 if (i.tm.cpu_flags.bitfield.cpupadlock)
5941 {
4dffcebc 5942check_prefix:
c0f3af97 5943 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5944 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5945 != REPE_PREFIX_OPCODE))
5946 add_prefix (prefix);
5947 }
5948 else
4dffcebc
L		 5949 add_prefix (prefix);
5950 }
c0f3af97
L		 5951 break;
5952 case 1:
5953 break;
5954 default:
5955 abort ();
bc4bd9ab 5956 }
c0f3af97
L		 5957
5958 /* The prefix bytes. */
5959 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5960 if (*q)
5961 FRAG_APPEND_1_CHAR (*q);
0f10071e 5962 }
252b5132 5963
c0f3af97
L		 5964 if (i.tm.opcode_modifier.vex)
5965 {
5966 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5967 if (*q)
5968 switch (j)
5969 {
5970 case REX_PREFIX:
5971 /* REX byte is encoded in VEX prefix. */
5972 break;
5973 case SEG_PREFIX:
5974 case ADDR_PREFIX:
5975 FRAG_APPEND_1_CHAR (*q);
5976 break;
5977 default:
5978 /* There should be no other prefixes for instructions
5979 with VEX prefix. */
5980 abort ();
5981 }
5982
5983 /* Now the VEX prefix. */
5984 p = frag_more (i.vex.length);
5985 for (j = 0; j < i.vex.length; j++)
5986 p[j] = i.vex.bytes[j];
5987 }
252b5132 5988
29b0f896 5989 /* Now the opcode; be careful about word order here! */
4dffcebc 5990 if (i.tm.opcode_length == 1)
29b0f896
AM		 5991 {
5992 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5993 }
5994 else
5995 {
4dffcebc 5996 switch (i.tm.opcode_length)
331d2d0d 5997 {
4dffcebc 5998 case 3:
331d2d0d
L		 5999 p = frag_more (3);
6000 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6001 break;
6002 case 2:
6003 p = frag_more (2);
6004 break;
6005 default:
6006 abort ();
6007 break;
331d2d0d 6008 }
0f10071e 6009
29b0f896
AM		 6010 /* Put out high byte first: can't use md_number_to_chars! */
6011 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6012 *p = i.tm.base_opcode & 0xff;
6013 }
3e73aa7c 6014
29b0f896 6015 /* Now the modrm byte and sib byte (if present). */
40fb9820 6016 if (i.tm.opcode_modifier.modrm)
29b0f896 6017 {
4a3523fa
L		 6018 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6019 | i.rm.reg << 3
6020 | i.rm.mode << 6));
29b0f896
AM		 6021 /* If i.rm.regmem == ESP (4)
6022 && i.rm.mode != (Register mode)
6023 && not 16 bit
6024 ==> need second modrm byte. */
6025 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6026 && i.rm.mode != 3
40fb9820 6027 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6028 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6029 | i.sib.index << 3
6030 | i.sib.scale << 6));
29b0f896 6031 }
3e73aa7c 6032
29b0f896 6033 if (i.disp_operands)
2bbd9c25 6034 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6035
29b0f896 6036 if (i.imm_operands)
2bbd9c25 6037 output_imm (insn_start_frag, insn_start_off);
29b0f896 6038 }
252b5132 6039
29b0f896
AM		 6040#ifdef DEBUG386
6041 if (flag_debug)
6042 {
7b81dfbb 6043 pi ("" /*line*/, &i);
29b0f896
AM		 6044 }
6045#endif /* DEBUG386 */
6046}
252b5132 6047
e205caa7
L		 6048/* Return the size of the displacement operand N. */
6049
6050static int
6051disp_size (unsigned int n)
6052{
6053 int size = 4;
40fb9820
L		 6054 if (i.types[n].bitfield.disp64)
6055 size = 8;
6056 else if (i.types[n].bitfield.disp8)
6057 size = 1;
6058 else if (i.types[n].bitfield.disp16)
6059 size = 2;
e205caa7
L		 6060 return size;
6061}
6062
6063/* Return the size of the immediate operand N. */
6064
6065static int
6066imm_size (unsigned int n)
6067{
6068 int size = 4;
40fb9820
L		 6069 if (i.types[n].bitfield.imm64)
6070 size = 8;
6071 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6072 size = 1;
6073 else if (i.types[n].bitfield.imm16)
6074 size = 2;
e205caa7
L		 6075 return size;
6076}
6077
29b0f896 6078static void
64e74474 6079output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6080{
6081 char *p;
6082 unsigned int n;
252b5132 6083
29b0f896
AM		 6084 for (n = 0; n < i.operands; n++)
6085 {
40fb9820 6086 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6087 {
6088 if (i.op[n].disps->X_op == O_constant)
6089 {
e205caa7 6090 int size = disp_size (n);
29b0f896 6091 offsetT val;
252b5132 6092
29b0f896
AM		 6093 val = offset_in_range (i.op[n].disps->X_add_number,
6094 size);
6095 p = frag_more (size);
6096 md_number_to_chars (p, val, size);
6097 }
6098 else
6099 {
f86103b7 6100 enum bfd_reloc_code_real reloc_type;
e205caa7 6101 int size = disp_size (n);
40fb9820 6102 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6103 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6104
e205caa7 6105 /* We can't have 8 bit displacement here. */
9c2799c2 6106 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6107
29b0f896
AM		 6108 /* The PC relative address is computed relative
6109 to the instruction boundary, so in case immediate
6110 fields follows, we need to adjust the value. */
6111 if (pcrel && i.imm_operands)
6112 {
29b0f896 6113 unsigned int n1;
e205caa7 6114 int sz = 0;
252b5132 6115
29b0f896 6116 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6117 if (operand_type_check (i.types[n1], imm))
252b5132 6118 {
e205caa7
L		 6119 /* Only one immediate is allowed for PC
6120 relative address. */
9c2799c2 6121 gas_assert (sz == 0);
e205caa7
L		 6122 sz = imm_size (n1);
6123 i.op[n].disps->X_add_number -= sz;
252b5132 6124 }
29b0f896 6125 /* We should find the immediate. */
9c2799c2 6126 gas_assert (sz != 0);
29b0f896 6127 }
520dc8e8 6128
29b0f896 6129 p = frag_more (size);
2bbd9c25 6130 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6131 if (GOT_symbol
2bbd9c25 6132 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6133 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6134 || reloc_type == BFD_RELOC_X86_64_32S
6135 || (reloc_type == BFD_RELOC_64
6136 && object_64bit))
d6ab8113
JB		 6137 && (i.op[n].disps->X_op == O_symbol
6138 || (i.op[n].disps->X_op == O_add
6139 && ((symbol_get_value_expression
6140 (i.op[n].disps->X_op_symbol)->X_op)
6141 == O_subtract))))
6142 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6143 {
6144 offsetT add;
6145
6146 if (insn_start_frag == frag_now)
6147 add = (p - frag_now->fr_literal) - insn_start_off;
6148 else
6149 {
6150 fragS *fr;
6151
6152 add = insn_start_frag->fr_fix - insn_start_off;
6153 for (fr = insn_start_frag->fr_next;
6154 fr && fr != frag_now; fr = fr->fr_next)
6155 add += fr->fr_fix;
6156 add += p - frag_now->fr_literal;
6157 }
6158
4fa24527 6159 if (!object_64bit)
7b81dfbb
AJ		 6160 {
6161 reloc_type = BFD_RELOC_386_GOTPC;
6162 i.op[n].imms->X_add_number += add;
6163 }
6164 else if (reloc_type == BFD_RELOC_64)
6165 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6166 else
7b81dfbb
AJ		 6167 /* Don't do the adjustment for x86-64, as there
6168 the pcrel addressing is relative to the _next_
6169 insn, and that is taken care of in other code. */
d6ab8113 6170 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6171 }
062cd5e7 6172 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6173 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6174 }
6175 }
6176 }
6177}
252b5132 6178
29b0f896 6179static void
64e74474 6180output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6181{
6182 char *p;
6183 unsigned int n;
252b5132 6184
29b0f896
AM		 6185 for (n = 0; n < i.operands; n++)
6186 {
40fb9820 6187 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6188 {
6189 if (i.op[n].imms->X_op == O_constant)
6190 {
e205caa7 6191 int size = imm_size (n);
29b0f896 6192 offsetT val;
b4cac588 6193
29b0f896
AM		 6194 val = offset_in_range (i.op[n].imms->X_add_number,
6195 size);
6196 p = frag_more (size);
6197 md_number_to_chars (p, val, size);
6198 }
6199 else
6200 {
6201 /* Not absolute_section.
6202 Need a 32-bit fixup (don't support 8bit
6203 non-absolute imms). Try to support other
6204 sizes ... */
f86103b7 6205 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6206 int size = imm_size (n);
6207 int sign;
29b0f896 6208
40fb9820 6209 if (i.types[n].bitfield.imm32s
a7d61044 6210 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6211 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6212 sign = 1;
e205caa7
L		 6213 else
6214 sign = 0;
520dc8e8 6215
29b0f896
AM		 6216 p = frag_more (size);
6217 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6218
2bbd9c25
JJ		 6219 /* This is tough to explain. We end up with this one if we
6220 * have operands that look like
6221 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6222 * obtain the absolute address of the GOT, and it is strongly
6223 * preferable from a performance point of view to avoid using
6224 * a runtime relocation for this. The actual sequence of
6225 * instructions often look something like:
6226 *
6227 * call .L66
6228 * .L66:
6229 * popl %ebx
6230 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6231 *
6232 * The call and pop essentially return the absolute address
6233 * of the label .L66 and store it in %ebx. The linker itself
6234 * will ultimately change the first operand of the addl so
6235 * that %ebx points to the GOT, but to keep things simple, the
6236 * .o file must have this operand set so that it generates not
6237 * the absolute address of .L66, but the absolute address of
6238 * itself. This allows the linker itself simply treat a GOTPC
6239 * relocation as asking for a pcrel offset to the GOT to be
6240 * added in, and the addend of the relocation is stored in the
6241 * operand field for the instruction itself.
6242 *
6243 * Our job here is to fix the operand so that it would add
6244 * the correct offset so that %ebx would point to itself. The
6245 * thing that is tricky is that .-.L66 will point to the
6246 * beginning of the instruction, so we need to further modify
6247 * the operand so that it will point to itself. There are
6248 * other cases where you have something like:
6249 *
6250 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6251 *
6252 * and here no correction would be required. Internally in
6253 * the assembler we treat operands of this form as not being
6254 * pcrel since the '.' is explicitly mentioned, and I wonder
6255 * whether it would simplify matters to do it this way. Who
6256 * knows. In earlier versions of the PIC patches, the
6257 * pcrel_adjust field was used to store the correction, but
6258 * since the expression is not pcrel, I felt it would be
6259 * confusing to do it this way. */
6260
d6ab8113 6261 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6262 || reloc_type == BFD_RELOC_X86_64_32S
6263 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6264 && GOT_symbol
6265 && GOT_symbol == i.op[n].imms->X_add_symbol
6266 && (i.op[n].imms->X_op == O_symbol
6267 || (i.op[n].imms->X_op == O_add
6268 && ((symbol_get_value_expression
6269 (i.op[n].imms->X_op_symbol)->X_op)
6270 == O_subtract))))
6271 {
2bbd9c25
JJ		 6272 offsetT add;
6273
6274 if (insn_start_frag == frag_now)
6275 add = (p - frag_now->fr_literal) - insn_start_off;
6276 else
6277 {
6278 fragS *fr;
6279
6280 add = insn_start_frag->fr_fix - insn_start_off;
6281 for (fr = insn_start_frag->fr_next;
6282 fr && fr != frag_now; fr = fr->fr_next)
6283 add += fr->fr_fix;
6284 add += p - frag_now->fr_literal;
6285 }
6286
4fa24527 6287 if (!object_64bit)
d6ab8113 6288 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6289 else if (size == 4)
d6ab8113 6290 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6291 else if (size == 8)
6292 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6293 i.op[n].imms->X_add_number += add;
29b0f896 6294 }
29b0f896
AM		 6295 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6296 i.op[n].imms, 0, reloc_type);
6297 }
6298 }
6299 }
252b5132
RH		 6300}
6301\f
d182319b
JB		 6302/* x86_cons_fix_new is called via the expression parsing code when a
6303 reloc is needed. We use this hook to get the correct .got reloc. */
6304static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6305static int cons_sign = -1;
6306
6307void
e3bb37b5 6308x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6309 expressionS *exp)
d182319b
JB		 6310{
6311 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6312
6313 got_reloc = NO_RELOC;
6314
6315#ifdef TE_PE
6316 if (exp->X_op == O_secrel)
6317 {
6318 exp->X_op = O_symbol;
6319 r = BFD_RELOC_32_SECREL;
6320 }
6321#endif
6322
6323 fix_new_exp (frag, off, len, exp, 0, r);
6324}
6325
718ddfc0
JB		 6326#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6327# define lex_got(reloc, adjust, types) NULL
6328#else
f3c180ae
AM		 6329/* Parse operands of the form
6330 <symbol>@GOTOFF+<nnn>
6331 and similar .plt or .got references.
6332
6333 If we find one, set up the correct relocation in RELOC and copy the
6334 input string, minus the `@GOTOFF' into a malloc'd buffer for
6335 parsing by the calling routine. Return this buffer, and if ADJUST
6336 is non-null set it to the length of the string we removed from the
6337 input line. Otherwise return NULL. */
6338static char *
91d6fa6a 6339lex_got (enum bfd_reloc_code_real *rel,
64e74474 6340 int *adjust,
40fb9820 6341 i386_operand_type *types)
f3c180ae 6342{
7b81dfbb
AJ		 6343 /* Some of the relocations depend on the size of what field is to
6344 be relocated. But in our callers i386_immediate and i386_displacement
6345 we don't yet know the operand size (this will be set by insn
6346 matching). Hence we record the word32 relocation here,
6347 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6348 static const struct {
6349 const char *str;
cff8d58a 6350 int len;
4fa24527 6351 const enum bfd_reloc_code_real rel[2];
40fb9820 6352 const i386_operand_type types64;
f3c180ae 6353 } gotrel[] = {
cff8d58a
L		 6354 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6355 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6356 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6357 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6358 BFD_RELOC_X86_64_PLT32 },
40fb9820 6359 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6360 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6361 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6362 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6363 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6364 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6365 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6366 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6367 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6368 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6369 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6370 BFD_RELOC_X86_64_TLSGD },
40fb9820 6371 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6372 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6373 _dummy_first_bfd_reloc_code_real },
40fb9820 6374 OPERAND_TYPE_NONE },
cff8d58a
L		 6375 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6376 BFD_RELOC_X86_64_TLSLD },
40fb9820 6377 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6378 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6379 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6380 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6381 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6382 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6383 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6384 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6385 _dummy_first_bfd_reloc_code_real },
40fb9820 6386 OPERAND_TYPE_NONE },
cff8d58a
L		 6387 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6388 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6389 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6390 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6391 _dummy_first_bfd_reloc_code_real },
40fb9820 6392 OPERAND_TYPE_NONE },
cff8d58a
L		 6393 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6394 _dummy_first_bfd_reloc_code_real },
40fb9820 6395 OPERAND_TYPE_NONE },
cff8d58a
L		 6396 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6397 BFD_RELOC_X86_64_GOT32 },
40fb9820 6398 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6399 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6400 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6401 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6402 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6403 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6404 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6405 };
6406 char *cp;
6407 unsigned int j;
6408
718ddfc0
JB		 6409 if (!IS_ELF)
6410 return NULL;
6411
f3c180ae 6412 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6413 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6414 return NULL;
6415
47465058 6416 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6417 {
cff8d58a 6418 int len = gotrel[j].len;
28f81592 6419 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6420 {
4fa24527 6421 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6422 {
28f81592
AM		 6423 int first, second;
6424 char *tmpbuf, *past_reloc;
f3c180ae 6425
91d6fa6a 6426 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6427 if (adjust)
6428 *adjust = len;
f3c180ae 6429
3956db08
JB		 6430 if (types)
6431 {
6432 if (flag_code != CODE_64BIT)
40fb9820
L		 6433 {
6434 types->bitfield.imm32 = 1;
6435 types->bitfield.disp32 = 1;
6436 }
3956db08
JB		 6437 else
6438 *types = gotrel[j].types64;
6439 }
6440
f3c180ae
AM		 6441 if (GOT_symbol == NULL)
6442 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6443
28f81592 6444 /* The length of the first part of our input line. */
f3c180ae 6445 first = cp - input_line_pointer;
28f81592
AM		 6446
6447 /* The second part goes from after the reloc token until
67c11a9b 6448 (and including) an end_of_line char or comma. */
28f81592 6449 past_reloc = cp + 1 + len;
67c11a9b
AM		 6450 cp = past_reloc;
6451 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6452 ++cp;
6453 second = cp + 1 - past_reloc;
28f81592
AM		 6454
6455 /* Allocate and copy string. The trailing NUL shouldn't
6456 be necessary, but be safe. */
1e9cc1c2 6457 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6458 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6459 if (second != 0 && *past_reloc != ' ')
6460 /* Replace the relocation token with ' ', so that
6461 errors like foo@GOTOFF1 will be detected. */
6462 tmpbuf[first++] = ' ';
6463 memcpy (tmpbuf + first, past_reloc, second);
6464 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6465 return tmpbuf;
6466 }
6467
4fa24527
JB		 6468 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6469 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6470 return NULL;
6471 }
6472 }
6473
6474 /* Might be a symbol version string. Don't as_bad here. */
6475 return NULL;
6476}
6477
f3c180ae 6478void
e3bb37b5 6479x86_cons (expressionS *exp, int size)
f3c180ae 6480{
ee86248c
JB		 6481 intel_syntax = -intel_syntax;
6482
3c7b9c2c 6483 exp->X_md = 0;
4fa24527 6484 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6485 {
6486 /* Handle @GOTOFF and the like in an expression. */
6487 char *save;
6488 char *gotfree_input_line;
6489 int adjust;
6490
6491 save = input_line_pointer;
3956db08 6492 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6493 if (gotfree_input_line)
6494 input_line_pointer = gotfree_input_line;
6495
6496 expression (exp);
6497
6498 if (gotfree_input_line)
6499 {
6500 /* expression () has merrily parsed up to the end of line,
6501 or a comma - in the wrong buffer. Transfer how far
6502 input_line_pointer has moved to the right buffer. */
6503 input_line_pointer = (save
6504 + (input_line_pointer - gotfree_input_line)
6505 + adjust);
6506 free (gotfree_input_line);
3992d3b7
AM		 6507 if (exp->X_op == O_constant
6508 || exp->X_op == O_absent
6509 || exp->X_op == O_illegal
0398aac5 6510 || exp->X_op == O_register
3992d3b7
AM		 6511 || exp->X_op == O_big)
6512 {
6513 char c = *input_line_pointer;
6514 *input_line_pointer = 0;
6515 as_bad (_("missing or invalid expression `%s'"), save);
6516 *input_line_pointer = c;
6517 }
f3c180ae
AM		 6518 }
6519 }
6520 else
6521 expression (exp);
ee86248c
JB		 6522
6523 intel_syntax = -intel_syntax;
6524
6525 if (intel_syntax)
6526 i386_intel_simplify (exp);
f3c180ae
AM		 6527}
6528#endif
6529
9f32dd5b
L		 6530static void
6531signed_cons (int size)
6482c264 6532{
d182319b
JB		 6533 if (flag_code == CODE_64BIT)
6534 cons_sign = 1;
6535 cons (size);
6536 cons_sign = -1;
6482c264
NC		 6537}
6538
d182319b 6539#ifdef TE_PE
6482c264
NC		 6540static void
6541pe_directive_secrel (dummy)
6542 int dummy ATTRIBUTE_UNUSED;
6543{
6544 expressionS exp;
6545
6546 do
6547 {
6548 expression (&exp);
6549 if (exp.X_op == O_symbol)
6550 exp.X_op = O_secrel;
6551
6552 emit_expr (&exp, 4);
6553 }
6554 while (*input_line_pointer++ == ',');
6555
6556 input_line_pointer--;
6557 demand_empty_rest_of_line ();
6558}
6482c264
NC		 6559#endif
6560
252b5132 6561static int
70e41ade 6562i386_immediate (char *imm_start)
252b5132
RH		 6563{
6564 char *save_input_line_pointer;
f3c180ae 6565 char *gotfree_input_line;
252b5132 6566 segT exp_seg = 0;
47926f60 6567 expressionS *exp;
40fb9820
L		 6568 i386_operand_type types;
6569
0dfbf9d7 6570 operand_type_set (&types, ~0);
252b5132
RH		 6571
6572 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6573 {
31b2323c
L		 6574 as_bad (_("at most %d immediate operands are allowed"),
6575 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6576 return 0;
6577 }
6578
6579 exp = &im_expressions[i.imm_operands++];
520dc8e8 6580 i.op[this_operand].imms = exp;
252b5132
RH		 6581
6582 if (is_space_char (*imm_start))
6583 ++imm_start;
6584
6585 save_input_line_pointer = input_line_pointer;
6586 input_line_pointer = imm_start;
6587
3956db08 6588 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6589 if (gotfree_input_line)
6590 input_line_pointer = gotfree_input_line;
252b5132
RH		 6591
6592 exp_seg = expression (exp);
6593
83183c0c 6594 SKIP_WHITESPACE ();
252b5132 6595 if (*input_line_pointer)
f3c180ae 6596 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6597
6598 input_line_pointer = save_input_line_pointer;
f3c180ae 6599 if (gotfree_input_line)
ee86248c
JB		 6600 {
6601 free (gotfree_input_line);
6602
6603 if (exp->X_op == O_constant || exp->X_op == O_register)
6604 exp->X_op = O_illegal;
6605 }
6606
6607 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6608}
252b5132 6609
ee86248c
JB		 6610static int
6611i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6612 i386_operand_type types, const char *imm_start)
6613{
6614 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6615 {
313c53d1
L		 6616 if (imm_start)
6617 as_bad (_("missing or invalid immediate expression `%s'"),
6618 imm_start);
3992d3b7 6619 return 0;
252b5132 6620 }
3e73aa7c 6621 else if (exp->X_op == O_constant)
252b5132 6622 {
47926f60 6623 /* Size it properly later. */
40fb9820 6624 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6625 /* If BFD64, sign extend val. */
4eed87de
AM		 6626 if (!use_rela_relocations
6627 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6628 exp->X_add_number
6629 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6630 }
4c63da97 6631#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6632 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6633 && exp_seg != absolute_section
47926f60 6634 && exp_seg != text_section
24eab124
AM		 6635 && exp_seg != data_section
6636 && exp_seg != bss_section
6637 && exp_seg != undefined_section
f86103b7 6638 && !bfd_is_com_section (exp_seg))
252b5132 6639 {
d0b47220 6640 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6641 return 0;
6642 }
6643#endif
bb8f5920
L		 6644 else if (!intel_syntax && exp->X_op == O_register)
6645 {
313c53d1
L		 6646 if (imm_start)
6647 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6648 return 0;
6649 }
252b5132
RH		 6650 else
6651 {
6652 /* This is an address. The size of the address will be
24eab124 6653 determined later, depending on destination register,
3e73aa7c 6654 suffix, or the default for the section. */
40fb9820
L		 6655 i.types[this_operand].bitfield.imm8 = 1;
6656 i.types[this_operand].bitfield.imm16 = 1;
6657 i.types[this_operand].bitfield.imm32 = 1;
6658 i.types[this_operand].bitfield.imm32s = 1;
6659 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6660 i.types[this_operand] = operand_type_and (i.types[this_operand],
6661 types);
252b5132
RH		 6662 }
6663
6664 return 1;
6665}
6666
551c1ca1 6667static char *
e3bb37b5 6668i386_scale (char *scale)
252b5132 6669{
551c1ca1
AM		 6670 offsetT val;
6671 char *save = input_line_pointer;
252b5132 6672
551c1ca1
AM		 6673 input_line_pointer = scale;
6674 val = get_absolute_expression ();
6675
6676 switch (val)
252b5132 6677 {
551c1ca1 6678 case 1:
252b5132
RH		 6679 i.log2_scale_factor = 0;
6680 break;
551c1ca1 6681 case 2:
252b5132
RH		 6682 i.log2_scale_factor = 1;
6683 break;
551c1ca1 6684 case 4:
252b5132
RH		 6685 i.log2_scale_factor = 2;
6686 break;
551c1ca1 6687 case 8:
252b5132
RH		 6688 i.log2_scale_factor = 3;
6689 break;
6690 default:
a724f0f4
JB		 6691 {
6692 char sep = *input_line_pointer;
6693
6694 *input_line_pointer = '\0';
6695 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6696 scale);
6697 *input_line_pointer = sep;
6698 input_line_pointer = save;
6699 return NULL;
6700 }
252b5132 6701 }
29b0f896 6702 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6703 {
6704 as_warn (_("scale factor of %d without an index register"),
24eab124 6705 1 << i.log2_scale_factor);
252b5132 6706 i.log2_scale_factor = 0;
252b5132 6707 }
551c1ca1
AM		 6708 scale = input_line_pointer;
6709 input_line_pointer = save;
6710 return scale;
252b5132
RH		 6711}
6712
252b5132 6713static int
e3bb37b5 6714i386_displacement (char *disp_start, char *disp_end)
252b5132 6715{
29b0f896 6716 expressionS *exp;
252b5132
RH		 6717 segT exp_seg = 0;
6718 char *save_input_line_pointer;
f3c180ae 6719 char *gotfree_input_line;
40fb9820
L		 6720 int override;
6721 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6722 int ret;
252b5132 6723
31b2323c
L		 6724 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6725 {
6726 as_bad (_("at most %d displacement operands are allowed"),
6727 MAX_MEMORY_OPERANDS);
6728 return 0;
6729 }
6730
0dfbf9d7 6731 operand_type_set (&bigdisp, 0);
40fb9820
L		 6732 if ((i.types[this_operand].bitfield.jumpabsolute)
6733 || (!current_templates->start->opcode_modifier.jump
6734 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6735 {
40fb9820 6736 bigdisp.bitfield.disp32 = 1;
e05278af 6737 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6738 if (flag_code == CODE_64BIT)
6739 {
6740 if (!override)
6741 {
6742 bigdisp.bitfield.disp32s = 1;
6743 bigdisp.bitfield.disp64 = 1;
6744 }
6745 }
6746 else if ((flag_code == CODE_16BIT) ^ override)
6747 {
6748 bigdisp.bitfield.disp32 = 0;
6749 bigdisp.bitfield.disp16 = 1;
6750 }
e05278af
JB		 6751 }
6752 else
6753 {
6754 /* For PC-relative branches, the width of the displacement
6755 is dependent upon data size, not address size. */
e05278af 6756 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6757 if (flag_code == CODE_64BIT)
6758 {
6759 if (override || i.suffix == WORD_MNEM_SUFFIX)
6760 bigdisp.bitfield.disp16 = 1;
6761 else
6762 {
6763 bigdisp.bitfield.disp32 = 1;
6764 bigdisp.bitfield.disp32s = 1;
6765 }
6766 }
6767 else
e05278af
JB		 6768 {
6769 if (!override)
6770 override = (i.suffix == (flag_code != CODE_16BIT
6771 ? WORD_MNEM_SUFFIX
6772 : LONG_MNEM_SUFFIX));
40fb9820
L		 6773 bigdisp.bitfield.disp32 = 1;
6774 if ((flag_code == CODE_16BIT) ^ override)
6775 {
6776 bigdisp.bitfield.disp32 = 0;
6777 bigdisp.bitfield.disp16 = 1;
6778 }
e05278af 6779 }
e05278af 6780 }
c6fb90c8
L		 6781 i.types[this_operand] = operand_type_or (i.types[this_operand],
6782 bigdisp);
252b5132
RH		 6783
6784 exp = &disp_expressions[i.disp_operands];
520dc8e8 6785 i.op[this_operand].disps = exp;
252b5132
RH		 6786 i.disp_operands++;
6787 save_input_line_pointer = input_line_pointer;
6788 input_line_pointer = disp_start;
6789 END_STRING_AND_SAVE (disp_end);
6790
6791#ifndef GCC_ASM_O_HACK
6792#define GCC_ASM_O_HACK 0
6793#endif
6794#if GCC_ASM_O_HACK
6795 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6796 if (i.types[this_operand].bitfield.baseIndex
24eab124 6797 && displacement_string_end[-1] == '+')
252b5132
RH		 6798 {
6799 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6800 constraint within gcc asm statements.
6801 For instance:
6802
6803 #define _set_tssldt_desc(n,addr,limit,type) \
6804 __asm__ __volatile__ ( \
6805 "movw %w2,%0\n\t" \
6806 "movw %w1,2+%0\n\t" \
6807 "rorl $16,%1\n\t" \
6808 "movb %b1,4+%0\n\t" \
6809 "movb %4,5+%0\n\t" \
6810 "movb $0,6+%0\n\t" \
6811 "movb %h1,7+%0\n\t" \
6812 "rorl $16,%1" \
6813 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6814
6815 This works great except that the output assembler ends
6816 up looking a bit weird if it turns out that there is
6817 no offset. You end up producing code that looks like:
6818
6819 #APP
6820 movw $235,(%eax)
6821 movw %dx,2+(%eax)
6822 rorl $16,%edx
6823 movb %dl,4+(%eax)
6824 movb $137,5+(%eax)
6825 movb $0,6+(%eax)
6826 movb %dh,7+(%eax)
6827 rorl $16,%edx
6828 #NO_APP
6829
47926f60 6830 So here we provide the missing zero. */
24eab124
AM		 6831
6832 *displacement_string_end = '0';
252b5132
RH		 6833 }
6834#endif
3956db08 6835 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6836 if (gotfree_input_line)
6837 input_line_pointer = gotfree_input_line;
252b5132 6838
24eab124 6839 exp_seg = expression (exp);
252b5132 6840
636c26b0
AM		 6841 SKIP_WHITESPACE ();
6842 if (*input_line_pointer)
6843 as_bad (_("junk `%s' after expression"), input_line_pointer);
6844#if GCC_ASM_O_HACK
6845 RESTORE_END_STRING (disp_end + 1);
6846#endif
636c26b0 6847 input_line_pointer = save_input_line_pointer;
636c26b0 6848 if (gotfree_input_line)
ee86248c
JB		 6849 {
6850 free (gotfree_input_line);
6851
6852 if (exp->X_op == O_constant || exp->X_op == O_register)
6853 exp->X_op = O_illegal;
6854 }
6855
6856 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6857
6858 RESTORE_END_STRING (disp_end);
6859
6860 return ret;
6861}
6862
6863static int
6864i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6865 i386_operand_type types, const char *disp_start)
6866{
6867 i386_operand_type bigdisp;
6868 int ret = 1;
636c26b0 6869
24eab124
AM		 6870 /* We do this to make sure that the section symbol is in
6871 the symbol table. We will ultimately change the relocation
47926f60 6872 to be relative to the beginning of the section. */
1ae12ab7 6873 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6874 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6875 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6876 {
636c26b0 6877 if (exp->X_op != O_symbol)
3992d3b7 6878 goto inv_disp;
636c26b0 6879
e5cb08ac 6880 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6881 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6882 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6883 exp->X_op = O_subtract;
6884 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6885 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6886 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6887 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6888 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6889 else
29b0f896 6890 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6891 }
252b5132 6892
3992d3b7
AM		 6893 else if (exp->X_op == O_absent
6894 || exp->X_op == O_illegal
ee86248c 6895 || exp->X_op == O_big)
2daf4fd8 6896 {
3992d3b7
AM		 6897 inv_disp:
6898 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6899 disp_start);
3992d3b7 6900 ret = 0;
2daf4fd8
AM		 6901 }
6902
0e1147d9
L		 6903 else if (flag_code == CODE_64BIT
6904 && !i.prefix[ADDR_PREFIX]
6905 && exp->X_op == O_constant)
6906 {
6907 /* Since displacement is signed extended to 64bit, don't allow
6908 disp32 and turn off disp32s if they are out of range. */
6909 i.types[this_operand].bitfield.disp32 = 0;
6910 if (!fits_in_signed_long (exp->X_add_number))
6911 {
6912 i.types[this_operand].bitfield.disp32s = 0;
6913 if (i.types[this_operand].bitfield.baseindex)
6914 {
6915 as_bad (_("0x%lx out range of signed 32bit displacement"),
6916 (long) exp->X_add_number);
6917 ret = 0;
6918 }
6919 }
6920 }
6921
4c63da97 6922#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6923 else if (exp->X_op != O_constant
6924 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6925 && exp_seg != absolute_section
6926 && exp_seg != text_section
6927 && exp_seg != data_section
6928 && exp_seg != bss_section
6929 && exp_seg != undefined_section
6930 && !bfd_is_com_section (exp_seg))
24eab124 6931 {
d0b47220 6932 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6933 ret = 0;
24eab124 6934 }
252b5132 6935#endif
3956db08 6936
40fb9820
L		 6937 /* Check if this is a displacement only operand. */
6938 bigdisp = i.types[this_operand];
6939 bigdisp.bitfield.disp8 = 0;
6940 bigdisp.bitfield.disp16 = 0;
6941 bigdisp.bitfield.disp32 = 0;
6942 bigdisp.bitfield.disp32s = 0;
6943 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6944 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6945 i.types[this_operand] = operand_type_and (i.types[this_operand],
6946 types);
3956db08 6947
3992d3b7 6948 return ret;
252b5132
RH		 6949}
6950
eecb386c 6951/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6952 Return 1 on success, 0 on a failure. */
6953
252b5132 6954static int
e3bb37b5 6955i386_index_check (const char *operand_string)
252b5132 6956{
3e73aa7c 6957 int ok;
fc0763e6 6958 const char *kind = "base/index";
24eab124 6959#if INFER_ADDR_PREFIX
eecb386c
AM		 6960 int fudged = 0;
6961
24eab124
AM		 6962 tryprefix:
6963#endif
3e73aa7c 6964 ok = 1;
fc0763e6
JB		 6965 if (current_templates->start->opcode_modifier.isstring
6966 && !current_templates->start->opcode_modifier.immext
6967 && (current_templates->end[-1].opcode_modifier.isstring
6968 || i.mem_operands))
6969 {
6970 /* Memory operands of string insns are special in that they only allow
6971 a single register (rDI, rSI, or rBX) as their memory address. */
6972 unsigned int expected;
6973
6974 kind = "string address";
6975
6976 if (current_templates->start->opcode_modifier.w)
6977 {
6978 i386_operand_type type = current_templates->end[-1].operand_types[0];
6979
6980 if (!type.bitfield.baseindex
6981 || ((!i.mem_operands != !intel_syntax)
6982 && current_templates->end[-1].operand_types[1]
6983 .bitfield.baseindex))
6984 type = current_templates->end[-1].operand_types[1];
6985 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6986 }
6987 else
6988 expected = 3 /* rBX */;
6989
6990 if (!i.base_reg || i.index_reg
6991 || operand_type_check (i.types[this_operand], disp))
6992 ok = -1;
6993 else if (!(flag_code == CODE_64BIT
6994 ? i.prefix[ADDR_PREFIX]
6995 ? i.base_reg->reg_type.bitfield.reg32
6996 : i.base_reg->reg_type.bitfield.reg64
6997 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6998 ? i.base_reg->reg_type.bitfield.reg32
6999 : i.base_reg->reg_type.bitfield.reg16))
7000 ok = 0;
7001 else if (i.base_reg->reg_num != expected)
7002 ok = -1;
7003
7004 if (ok < 0)
7005 {
7006 unsigned int j;
7007
7008 for (j = 0; j < i386_regtab_size; ++j)
7009 if ((flag_code == CODE_64BIT
7010 ? i.prefix[ADDR_PREFIX]
7011 ? i386_regtab[j].reg_type.bitfield.reg32
7012 : i386_regtab[j].reg_type.bitfield.reg64
7013 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7014 ? i386_regtab[j].reg_type.bitfield.reg32
7015 : i386_regtab[j].reg_type.bitfield.reg16)
7016 && i386_regtab[j].reg_num == expected)
7017 break;
9c2799c2 7018 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7019 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7020 operand_string,
7021 intel_syntax ? '[' : '(',
7022 register_prefix,
7023 i386_regtab[j].reg_name,
7024 intel_syntax ? ']' : ')');
7025 ok = 1;
7026 }
7027 }
7028 else if (flag_code == CODE_64BIT)
64e74474 7029 {
64e74474 7030 if ((i.base_reg
40fb9820
L		 7031 && ((i.prefix[ADDR_PREFIX] == 0
7032 && !i.base_reg->reg_type.bitfield.reg64)
7033 || (i.prefix[ADDR_PREFIX]
7034 && !i.base_reg->reg_type.bitfield.reg32))
7035 && (i.index_reg
9a04903e
JB		 7036 || i.base_reg->reg_num !=
7037 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7038 || (i.index_reg
40fb9820
L		 7039 && (!i.index_reg->reg_type.bitfield.baseindex
7040 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7041 && i.index_reg->reg_num != RegRiz
7042 && !i.index_reg->reg_type.bitfield.reg64
7043 )
40fb9820 7044 || (i.prefix[ADDR_PREFIX]
db51cc60 7045 && i.index_reg->reg_num != RegEiz
40fb9820 7046 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7047 ok = 0;
3e73aa7c
JH		 7048 }
7049 else
7050 {
7051 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7052 {
7053 /* 16bit checks. */
7054 if ((i.base_reg
40fb9820
L		 7055 && (!i.base_reg->reg_type.bitfield.reg16
7056 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7057 || (i.index_reg
40fb9820
L		 7058 && (!i.index_reg->reg_type.bitfield.reg16
7059 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7060 || !(i.base_reg
7061 && i.base_reg->reg_num < 6
7062 && i.index_reg->reg_num >= 6
7063 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7064 ok = 0;
7065 }
7066 else
e5cb08ac 7067 {
3e73aa7c
JH		 7068 /* 32bit checks. */
7069 if ((i.base_reg
40fb9820 7070 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7071 || (i.index_reg
db51cc60
L		 7072 && ((!i.index_reg->reg_type.bitfield.reg32
7073 && i.index_reg->reg_num != RegEiz)
40fb9820 7074 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7075 ok = 0;
3e73aa7c
JH		 7076 }
7077 }
7078 if (!ok)
24eab124
AM		 7079 {
7080#if INFER_ADDR_PREFIX
fc0763e6 7081 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7082 {
7083 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7084 i.prefixes += 1;
b23bac36
AM		 7085 /* Change the size of any displacement too. At most one of
7086 Disp16 or Disp32 is set.
7087 FIXME. There doesn't seem to be any real need for separate
7088 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7089 Removing them would probably clean up the code quite a lot. */
4eed87de 7090 if (flag_code != CODE_64BIT
40fb9820
L		 7091 && (i.types[this_operand].bitfield.disp16
7092 || i.types[this_operand].bitfield.disp32))
7093 i.types[this_operand]
c6fb90c8 7094 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7095 fudged = 1;
24eab124
AM		 7096 goto tryprefix;
7097 }
eecb386c 7098 if (fudged)
fc0763e6
JB		 7099 as_bad (_("`%s' is not a valid %s expression"),
7100 operand_string,
7101 kind);
eecb386c 7102 else
c388dee8 7103#endif
fc0763e6 7104 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7105 operand_string,
fc0763e6
JB		 7106 flag_code_names[i.prefix[ADDR_PREFIX]
7107 ? flag_code == CODE_32BIT
7108 ? CODE_16BIT
7109 : CODE_32BIT
7110 : flag_code],
7111 kind);
24eab124 7112 }
20f0a1fc 7113 return ok;
24eab124 7114}
252b5132 7115
fc0763e6 7116/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7117 on error. */
252b5132 7118
252b5132 7119static int
a7619375 7120i386_att_operand (char *operand_string)
252b5132 7121{
af6bdddf
AM		 7122 const reg_entry *r;
7123 char *end_op;
24eab124 7124 char *op_string = operand_string;
252b5132 7125
24eab124 7126 if (is_space_char (*op_string))
252b5132
RH		 7127 ++op_string;
7128
24eab124 7129 /* We check for an absolute prefix (differentiating,
47926f60 7130 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7131 if (*op_string == ABSOLUTE_PREFIX)
7132 {
7133 ++op_string;
7134 if (is_space_char (*op_string))
7135 ++op_string;
40fb9820 7136 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7137 }
252b5132 7138
47926f60 7139 /* Check if operand is a register. */
4d1bb795 7140 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7141 {
40fb9820
L		 7142 i386_operand_type temp;
7143
24eab124
AM		 7144 /* Check for a segment override by searching for ':' after a
7145 segment register. */
7146 op_string = end_op;
7147 if (is_space_char (*op_string))
7148 ++op_string;
40fb9820
L		 7149 if (*op_string == ':'
7150 && (r->reg_type.bitfield.sreg2
7151 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7152 {
7153 switch (r->reg_num)
7154 {
7155 case 0:
7156 i.seg[i.mem_operands] = &es;
7157 break;
7158 case 1:
7159 i.seg[i.mem_operands] = &cs;
7160 break;
7161 case 2:
7162 i.seg[i.mem_operands] = &ss;
7163 break;
7164 case 3:
7165 i.seg[i.mem_operands] = &ds;
7166 break;
7167 case 4:
7168 i.seg[i.mem_operands] = &fs;
7169 break;
7170 case 5:
7171 i.seg[i.mem_operands] = &gs;
7172 break;
7173 }
252b5132 7174
24eab124 7175 /* Skip the ':' and whitespace. */
252b5132
RH		 7176 ++op_string;
7177 if (is_space_char (*op_string))
24eab124 7178 ++op_string;
252b5132 7179
24eab124
AM		 7180 if (!is_digit_char (*op_string)
7181 && !is_identifier_char (*op_string)
7182 && *op_string != '('
7183 && *op_string != ABSOLUTE_PREFIX)
7184 {
7185 as_bad (_("bad memory operand `%s'"), op_string);
7186 return 0;
7187 }
47926f60 7188 /* Handle case of %es:*foo. */
24eab124
AM		 7189 if (*op_string == ABSOLUTE_PREFIX)
7190 {
7191 ++op_string;
7192 if (is_space_char (*op_string))
7193 ++op_string;
40fb9820 7194 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7195 }
7196 goto do_memory_reference;
7197 }
7198 if (*op_string)
7199 {
d0b47220 7200 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7201 return 0;
7202 }
40fb9820
L		 7203 temp = r->reg_type;
7204 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7205 i.types[this_operand] = operand_type_or (i.types[this_operand],
7206 temp);
7d5e4556 7207 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7208 i.op[this_operand].regs = r;
24eab124
AM		 7209 i.reg_operands++;
7210 }
af6bdddf
AM		 7211 else if (*op_string == REGISTER_PREFIX)
7212 {
7213 as_bad (_("bad register name `%s'"), op_string);
7214 return 0;
7215 }
24eab124 7216 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7217 {
24eab124 7218 ++op_string;
40fb9820 7219 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7220 {
d0b47220 7221 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7222 return 0;
7223 }
7224 if (!i386_immediate (op_string))
7225 return 0;
7226 }
7227 else if (is_digit_char (*op_string)
7228 || is_identifier_char (*op_string)
e5cb08ac 7229 || *op_string == '(')
24eab124 7230 {
47926f60 7231 /* This is a memory reference of some sort. */
af6bdddf 7232 char *base_string;
252b5132 7233
47926f60 7234 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7235 char *displacement_string_start;
7236 char *displacement_string_end;
252b5132 7237
24eab124 7238 do_memory_reference:
24eab124 7239 if ((i.mem_operands == 1
40fb9820 7240 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7241 || i.mem_operands == 2)
7242 {
7243 as_bad (_("too many memory references for `%s'"),
7244 current_templates->start->name);
7245 return 0;
7246 }
252b5132 7247
24eab124
AM		 7248 /* Check for base index form. We detect the base index form by
7249 looking for an ')' at the end of the operand, searching
7250 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7251 after the '('. */
af6bdddf 7252 base_string = op_string + strlen (op_string);
c3332e24 7253
af6bdddf
AM		 7254 --base_string;
7255 if (is_space_char (*base_string))
7256 --base_string;
252b5132 7257
47926f60 7258 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7259 displacement_string_start = op_string;
7260 displacement_string_end = base_string + 1;
252b5132 7261
24eab124
AM		 7262 if (*base_string == ')')
7263 {
af6bdddf 7264 char *temp_string;
24eab124
AM		 7265 unsigned int parens_balanced = 1;
7266 /* We've already checked that the number of left & right ()'s are
47926f60 7267 equal, so this loop will not be infinite. */
24eab124
AM		 7268 do
7269 {
7270 base_string--;
7271 if (*base_string == ')')
7272 parens_balanced++;
7273 if (*base_string == '(')
7274 parens_balanced--;
7275 }
7276 while (parens_balanced);
c3332e24 7277
af6bdddf 7278 temp_string = base_string;
c3332e24 7279
24eab124 7280 /* Skip past '(' and whitespace. */
252b5132
RH		 7281 ++base_string;
7282 if (is_space_char (*base_string))
24eab124 7283 ++base_string;
252b5132 7284
af6bdddf 7285 if (*base_string == ','
4eed87de
AM		 7286 || ((i.base_reg = parse_register (base_string, &end_op))
7287 != NULL))
252b5132 7288 {
af6bdddf 7289 displacement_string_end = temp_string;
252b5132 7290
40fb9820 7291 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7292
af6bdddf 7293 if (i.base_reg)
24eab124 7294 {
24eab124
AM		 7295 base_string = end_op;
7296 if (is_space_char (*base_string))
7297 ++base_string;
af6bdddf
AM		 7298 }
7299
7300 /* There may be an index reg or scale factor here. */
7301 if (*base_string == ',')
7302 {
7303 ++base_string;
7304 if (is_space_char (*base_string))
7305 ++base_string;
7306
4eed87de
AM		 7307 if ((i.index_reg = parse_register (base_string, &end_op))
7308 != NULL)
24eab124 7309 {
af6bdddf 7310 base_string = end_op;
24eab124
AM		 7311 if (is_space_char (*base_string))
7312 ++base_string;
af6bdddf
AM		 7313 if (*base_string == ',')
7314 {
7315 ++base_string;
7316 if (is_space_char (*base_string))
7317 ++base_string;
7318 }
e5cb08ac 7319 else if (*base_string != ')')
af6bdddf 7320 {
4eed87de
AM		 7321 as_bad (_("expecting `,' or `)' "
7322 "after index register in `%s'"),
af6bdddf
AM		 7323 operand_string);
7324 return 0;
7325 }
24eab124 7326 }
af6bdddf 7327 else if (*base_string == REGISTER_PREFIX)
24eab124 7328 {
af6bdddf 7329 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7330 return 0;
7331 }
252b5132 7332
47926f60 7333 /* Check for scale factor. */
551c1ca1 7334 if (*base_string != ')')
af6bdddf 7335 {
551c1ca1
AM		 7336 char *end_scale = i386_scale (base_string);
7337
7338 if (!end_scale)
af6bdddf 7339 return 0;
24eab124 7340
551c1ca1 7341 base_string = end_scale;
af6bdddf
AM		 7342 if (is_space_char (*base_string))
7343 ++base_string;
7344 if (*base_string != ')')
7345 {
4eed87de
AM		 7346 as_bad (_("expecting `)' "
7347 "after scale factor in `%s'"),
af6bdddf
AM		 7348 operand_string);
7349 return 0;
7350 }
7351 }
7352 else if (!i.index_reg)
24eab124 7353 {
4eed87de
AM		 7354 as_bad (_("expecting index register or scale factor "
7355 "after `,'; got '%c'"),
af6bdddf 7356 *base_string);
24eab124
AM		 7357 return 0;
7358 }
7359 }
af6bdddf 7360 else if (*base_string != ')')
24eab124 7361 {
4eed87de
AM		 7362 as_bad (_("expecting `,' or `)' "
7363 "after base register in `%s'"),
af6bdddf 7364 operand_string);
24eab124
AM		 7365 return 0;
7366 }
c3332e24 7367 }
af6bdddf 7368 else if (*base_string == REGISTER_PREFIX)
c3332e24 7369 {
af6bdddf 7370 as_bad (_("bad register name `%s'"), base_string);
24eab124 7371 return 0;
c3332e24 7372 }
24eab124
AM		 7373 }
7374
7375 /* If there's an expression beginning the operand, parse it,
7376 assuming displacement_string_start and
7377 displacement_string_end are meaningful. */
7378 if (displacement_string_start != displacement_string_end)
7379 {
7380 if (!i386_displacement (displacement_string_start,
7381 displacement_string_end))
7382 return 0;
7383 }
7384
7385 /* Special case for (%dx) while doing input/output op. */
7386 if (i.base_reg
0dfbf9d7
L		 7387 && operand_type_equal (&i.base_reg->reg_type,
7388 &reg16_inoutportreg)
24eab124
AM		 7389 && i.index_reg == 0
7390 && i.log2_scale_factor == 0
7391 && i.seg[i.mem_operands] == 0
40fb9820 7392 && !operand_type_check (i.types[this_operand], disp))
24eab124 7393 {
65da13b5 7394 i.types[this_operand] = inoutportreg;
24eab124
AM		 7395 return 1;
7396 }
7397
eecb386c
AM		 7398 if (i386_index_check (operand_string) == 0)
7399 return 0;
5c07affc 7400 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7401 i.mem_operands++;
7402 }
7403 else
ce8a8b2f
AM		 7404 {
7405 /* It's not a memory operand; argh! */
24eab124
AM		 7406 as_bad (_("invalid char %s beginning operand %d `%s'"),
7407 output_invalid (*op_string),
7408 this_operand + 1,
7409 op_string);
7410 return 0;
7411 }
47926f60 7412 return 1; /* Normal return. */
252b5132
RH		 7413}
7414\f
ee7fcc42
AM		 7415/* md_estimate_size_before_relax()
7416
7417 Called just before relax() for rs_machine_dependent frags. The x86
7418 assembler uses these frags to handle variable size jump
7419 instructions.
7420
7421 Any symbol that is now undefined will not become defined.
7422 Return the correct fr_subtype in the frag.
7423 Return the initial "guess for variable size of frag" to caller.
7424 The guess is actually the growth beyond the fixed part. Whatever
7425 we do to grow the fixed or variable part contributes to our
7426 returned value. */
7427
252b5132
RH		 7428int
7429md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7430 fragS *fragP;
7431 segT segment;
252b5132 7432{
252b5132 7433 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7434 check for un-relaxable symbols. On an ELF system, we can't relax
7435 an externally visible symbol, because it may be overridden by a
7436 shared library. */
7437 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7438#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7439 || (IS_ELF
31312f95 7440 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7441 || S_IS_WEAK (fragP->fr_symbol)
7442 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7443 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7444#endif
7445#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7446 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7447 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7448#endif
7449 )
252b5132 7450 {
b98ef147
AM		 7451 /* Symbol is undefined in this segment, or we need to keep a
7452 reloc so that weak symbols can be overridden. */
7453 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7454 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7455 unsigned char *opcode;
7456 int old_fr_fix;
f6af82bd 7457
ee7fcc42 7458 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7459 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7460 else if (size == 2)
f6af82bd
AM		 7461 reloc_type = BFD_RELOC_16_PCREL;
7462 else
7463 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7464
ee7fcc42
AM		 7465 old_fr_fix = fragP->fr_fix;
7466 opcode = (unsigned char *) fragP->fr_opcode;
7467
fddf5b5b 7468 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7469 {
fddf5b5b
AM		 7470 case UNCOND_JUMP:
7471 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7472 opcode[0] = 0xe9;
252b5132 7473 fragP->fr_fix += size;
062cd5e7
AS		 7474 fix_new (fragP, old_fr_fix, size,
7475 fragP->fr_symbol,
7476 fragP->fr_offset, 1,
7477 reloc_type);
252b5132
RH		 7478 break;
7479
fddf5b5b 7480 case COND_JUMP86:
412167cb
AM		 7481 if (size == 2
7482 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7483 {
7484 /* Negate the condition, and branch past an
7485 unconditional jump. */
7486 opcode[0] ^= 1;
7487 opcode[1] = 3;
7488 /* Insert an unconditional jump. */
7489 opcode[2] = 0xe9;
7490 /* We added two extra opcode bytes, and have a two byte
7491 offset. */
7492 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7493 fix_new (fragP, old_fr_fix + 2, 2,
7494 fragP->fr_symbol,
7495 fragP->fr_offset, 1,
7496 reloc_type);
fddf5b5b
AM		 7497 break;
7498 }
7499 /* Fall through. */
7500
7501 case COND_JUMP:
412167cb
AM		 7502 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7503 {
3e02c1cc
AM		 7504 fixS *fixP;
7505
412167cb 7506 fragP->fr_fix += 1;
3e02c1cc
AM		 7507 fixP = fix_new (fragP, old_fr_fix, 1,
7508 fragP->fr_symbol,
7509 fragP->fr_offset, 1,
7510 BFD_RELOC_8_PCREL);
7511 fixP->fx_signed = 1;
412167cb
AM		 7512 break;
7513 }
93c2a809 7514
24eab124 7515 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7516 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7517 opcode[1] = opcode[0] + 0x10;
f6af82bd 7518 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7519 /* We've added an opcode byte. */
7520 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7521 fix_new (fragP, old_fr_fix + 1, size,
7522 fragP->fr_symbol,
7523 fragP->fr_offset, 1,
7524 reloc_type);
252b5132 7525 break;
fddf5b5b
AM		 7526
7527 default:
7528 BAD_CASE (fragP->fr_subtype);
7529 break;
252b5132
RH		 7530 }
7531 frag_wane (fragP);
ee7fcc42 7532 return fragP->fr_fix - old_fr_fix;
252b5132 7533 }
93c2a809 7534
93c2a809
AM		 7535 /* Guess size depending on current relax state. Initially the relax
7536 state will correspond to a short jump and we return 1, because
7537 the variable part of the frag (the branch offset) is one byte
7538 long. However, we can relax a section more than once and in that
7539 case we must either set fr_subtype back to the unrelaxed state,
7540 or return the value for the appropriate branch. */
7541 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7542}
7543
47926f60
KH		 7544/* Called after relax() is finished.
7545
7546 In: Address of frag.
7547 fr_type == rs_machine_dependent.
7548 fr_subtype is what the address relaxed to.
7549
7550 Out: Any fixSs and constants are set up.
7551 Caller will turn frag into a ".space 0". */
7552
252b5132
RH		 7553void
7554md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7555 bfd *abfd ATTRIBUTE_UNUSED;
7556 segT sec ATTRIBUTE_UNUSED;
29b0f896 7557 fragS *fragP;
252b5132 7558{
29b0f896 7559 unsigned char *opcode;
252b5132 7560 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7561 offsetT target_address;
7562 offsetT opcode_address;
252b5132 7563 unsigned int extension = 0;
847f7ad4 7564 offsetT displacement_from_opcode_start;
252b5132
RH		 7565
7566 opcode = (unsigned char *) fragP->fr_opcode;
7567
47926f60 7568 /* Address we want to reach in file space. */
252b5132 7569 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7570
47926f60 7571 /* Address opcode resides at in file space. */
252b5132
RH		 7572 opcode_address = fragP->fr_address + fragP->fr_fix;
7573
47926f60 7574 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7575 displacement_from_opcode_start = target_address - opcode_address;
7576
fddf5b5b 7577 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7578 {
47926f60
KH		 7579 /* Don't have to change opcode. */
7580 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7581 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7582 }
7583 else
7584 {
7585 if (no_cond_jump_promotion
7586 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7587 as_warn_where (fragP->fr_file, fragP->fr_line,
7588 _("long jump required"));
252b5132 7589
fddf5b5b
AM		 7590 switch (fragP->fr_subtype)
7591 {
7592 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7593 extension = 4; /* 1 opcode + 4 displacement */
7594 opcode[0] = 0xe9;
7595 where_to_put_displacement = &opcode[1];
7596 break;
252b5132 7597
fddf5b5b
AM		 7598 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7599 extension = 2; /* 1 opcode + 2 displacement */
7600 opcode[0] = 0xe9;
7601 where_to_put_displacement = &opcode[1];
7602 break;
252b5132 7603
fddf5b5b
AM		 7604 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7605 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7606 extension = 5; /* 2 opcode + 4 displacement */
7607 opcode[1] = opcode[0] + 0x10;
7608 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7609 where_to_put_displacement = &opcode[2];
7610 break;
252b5132 7611
fddf5b5b
AM		 7612 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7613 extension = 3; /* 2 opcode + 2 displacement */
7614 opcode[1] = opcode[0] + 0x10;
7615 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7616 where_to_put_displacement = &opcode[2];
7617 break;
252b5132 7618
fddf5b5b
AM		 7619 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7620 extension = 4;
7621 opcode[0] ^= 1;
7622 opcode[1] = 3;
7623 opcode[2] = 0xe9;
7624 where_to_put_displacement = &opcode[3];
7625 break;
7626
7627 default:
7628 BAD_CASE (fragP->fr_subtype);
7629 break;
7630 }
252b5132 7631 }
fddf5b5b 7632
7b81dfbb
AJ		 7633 /* If size if less then four we are sure that the operand fits,
7634 but if it's 4, then it could be that the displacement is larger
7635 then -/+ 2GB. */
7636 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7637 && object_64bit
7638 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7639 + ((addressT) 1 << 31))
7640 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7641 {
7642 as_bad_where (fragP->fr_file, fragP->fr_line,
7643 _("jump target out of range"));
7644 /* Make us emit 0. */
7645 displacement_from_opcode_start = extension;
7646 }
47926f60 7647 /* Now put displacement after opcode. */
252b5132
RH		 7648 md_number_to_chars ((char *) where_to_put_displacement,
7649 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7650 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7651 fragP->fr_fix += extension;
7652}
7653\f
252b5132
RH		 7654/* Apply a fixup (fixS) to segment data, once it has been determined
7655 by our caller that we have all the info we need to fix it up.
7656
7657 On the 386, immediates, displacements, and data pointers are all in
7658 the same (little-endian) format, so we don't need to care about which
7659 we are handling. */
7660
94f592af 7661void
55cf6793 7662md_apply_fix (fixP, valP, seg)
47926f60
KH		 7663 /* The fix we're to put in. */
7664 fixS *fixP;
47926f60 7665 /* Pointer to the value of the bits. */
c6682705 7666 valueT *valP;
47926f60
KH		 7667 /* Segment fix is from. */
7668 segT seg ATTRIBUTE_UNUSED;
252b5132 7669{
94f592af 7670 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7671 valueT value = *valP;
252b5132 7672
f86103b7 7673#if !defined (TE_Mach)
93382f6d
AM		 7674 if (fixP->fx_pcrel)
7675 {
7676 switch (fixP->fx_r_type)
7677 {
5865bb77
ILT		 7678 default:
7679 break;
7680
d6ab8113
JB		 7681 case BFD_RELOC_64:
7682 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7683 break;
93382f6d 7684 case BFD_RELOC_32:
ae8887b5 7685 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7686 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7687 break;
7688 case BFD_RELOC_16:
7689 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7690 break;
7691 case BFD_RELOC_8:
7692 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7693 break;
7694 }
7695 }
252b5132 7696
a161fe53 7697 if (fixP->fx_addsy != NULL
31312f95 7698 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7699 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7700 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7701 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7702 && !use_rela_relocations)
252b5132 7703 {
31312f95
AM		 7704 /* This is a hack. There should be a better way to handle this.
7705 This covers for the fact that bfd_install_relocation will
7706 subtract the current location (for partial_inplace, PC relative
7707 relocations); see more below. */
252b5132 7708#ifndef OBJ_AOUT
718ddfc0 7709 if (IS_ELF
252b5132
RH		 7710#ifdef TE_PE
7711 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7712#endif
7713 )
7714 value += fixP->fx_where + fixP->fx_frag->fr_address;
7715#endif
7716#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7717 if (IS_ELF)
252b5132 7718 {
6539b54b 7719 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7720
6539b54b 7721 if ((sym_seg == seg
2f66722d 7722 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7723 && sym_seg != absolute_section))
af65af87 7724 && !generic_force_reloc (fixP))
2f66722d
AM		 7725 {
7726 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7727 bfd_install_relocation subtracts them out again. I think
7728 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7729 it. FIXME. */
7730 value += fixP->fx_where + fixP->fx_frag->fr_address;
7731 }
252b5132
RH		 7732 }
7733#endif
7734#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7735 /* For some reason, the PE format does not store a
7736 section address offset for a PC relative symbol. */
7737 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7738 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7739 value += md_pcrel_from (fixP);
7740#endif
7741 }
fbeb56a4
DK		 7742#if defined (OBJ_COFF) && defined (TE_PE)
7743 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7744 {
7745 value -= S_GET_VALUE (fixP->fx_addsy);
7746 }
7747#endif
252b5132
RH		 7748
7749 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7750 and we must not disappoint it. */
252b5132 7751#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7752 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7753 switch (fixP->fx_r_type)
7754 {
7755 case BFD_RELOC_386_PLT32:
3e73aa7c 7756 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7757 /* Make the jump instruction point to the address of the operand. At
7758 runtime we merely add the offset to the actual PLT entry. */
7759 value = -4;
7760 break;
31312f95 7761
13ae64f3
JJ		 7762 case BFD_RELOC_386_TLS_GD:
7763 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7764 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7765 case BFD_RELOC_386_TLS_IE:
7766 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7767 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7768 case BFD_RELOC_X86_64_TLSGD:
7769 case BFD_RELOC_X86_64_TLSLD:
7770 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7771 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7772 value = 0; /* Fully resolved at runtime. No addend. */
7773 /* Fallthrough */
7774 case BFD_RELOC_386_TLS_LE:
7775 case BFD_RELOC_386_TLS_LDO_32:
7776 case BFD_RELOC_386_TLS_LE_32:
7777 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7778 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7779 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7780 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7781 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7782 break;
7783
67a4f2b7
AO		 7784 case BFD_RELOC_386_TLS_DESC_CALL:
7785 case BFD_RELOC_X86_64_TLSDESC_CALL:
7786 value = 0; /* Fully resolved at runtime. No addend. */
7787 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7788 fixP->fx_done = 0;
7789 return;
7790
00f7efb6
JJ		 7791 case BFD_RELOC_386_GOT32:
7792 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7793 value = 0; /* Fully resolved at runtime. No addend. */
7794 break;
47926f60
KH		 7795
7796 case BFD_RELOC_VTABLE_INHERIT:
7797 case BFD_RELOC_VTABLE_ENTRY:
7798 fixP->fx_done = 0;
94f592af 7799 return;
47926f60
KH		 7800
7801 default:
7802 break;
7803 }
7804#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7805 *valP = value;
f86103b7 7806#endif /* !defined (TE_Mach) */
3e73aa7c 7807
3e73aa7c 7808 /* Are we finished with this relocation now? */
c6682705 7809 if (fixP->fx_addsy == NULL)
3e73aa7c 7810 fixP->fx_done = 1;
fbeb56a4
DK		 7811#if defined (OBJ_COFF) && defined (TE_PE)
7812 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7813 {
7814 fixP->fx_done = 0;
7815 /* Remember value for tc_gen_reloc. */
7816 fixP->fx_addnumber = value;
7817 /* Clear out the frag for now. */
7818 value = 0;
7819 }
7820#endif
3e73aa7c
JH		 7821 else if (use_rela_relocations)
7822 {
7823 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7824 /* Remember value for tc_gen_reloc. */
7825 fixP->fx_addnumber = value;
3e73aa7c
JH		 7826 value = 0;
7827 }
f86103b7 7828
94f592af 7829 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7830}
252b5132 7831\f
252b5132 7832char *
499ac353 7833md_atof (int type, char *litP, int *sizeP)
252b5132 7834{
499ac353
NC		 7835 /* This outputs the LITTLENUMs in REVERSE order;
7836 in accord with the bigendian 386. */
7837 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7838}
7839\f
2d545b82 7840static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7841
252b5132 7842static char *
e3bb37b5 7843output_invalid (int c)
252b5132 7844{
3882b010 7845 if (ISPRINT (c))
f9f21a03
L		 7846 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7847 "'%c'", c);
252b5132 7848 else
f9f21a03 7849 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7850 "(0x%x)", (unsigned char) c);
252b5132
RH		 7851 return output_invalid_buf;
7852}
7853
af6bdddf 7854/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7855
7856static const reg_entry *
4d1bb795 7857parse_real_register (char *reg_string, char **end_op)
252b5132 7858{
af6bdddf
AM		 7859 char *s = reg_string;
7860 char *p;
252b5132
RH		 7861 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7862 const reg_entry *r;
7863
7864 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7865 if (*s == REGISTER_PREFIX)
7866 ++s;
7867
7868 if (is_space_char (*s))
7869 ++s;
7870
7871 p = reg_name_given;
af6bdddf 7872 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7873 {
7874 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7875 return (const reg_entry *) NULL;
7876 s++;
252b5132
RH		 7877 }
7878
6588847e
DN		 7879 /* For naked regs, make sure that we are not dealing with an identifier.
7880 This prevents confusing an identifier like `eax_var' with register
7881 `eax'. */
7882 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7883 return (const reg_entry *) NULL;
7884
af6bdddf 7885 *end_op = s;
252b5132
RH		 7886
7887 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7888
5f47d35b 7889 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7890 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7891 {
5f47d35b
AM		 7892 if (is_space_char (*s))
7893 ++s;
7894 if (*s == '(')
7895 {
af6bdddf 7896 ++s;
5f47d35b
AM		 7897 if (is_space_char (*s))
7898 ++s;
7899 if (*s >= '0' && *s <= '7')
7900 {
db557034 7901 int fpr = *s - '0';
af6bdddf 7902 ++s;
5f47d35b
AM		 7903 if (is_space_char (*s))
7904 ++s;
7905 if (*s == ')')
7906 {
7907 *end_op = s + 1;
1e9cc1c2 7908 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7909 know (r);
7910 return r + fpr;
5f47d35b 7911 }
5f47d35b 7912 }
47926f60 7913 /* We have "%st(" then garbage. */
5f47d35b
AM		 7914 return (const reg_entry *) NULL;
7915 }
7916 }
7917
a60de03c
JB		 7918 if (r == NULL || allow_pseudo_reg)
7919 return r;
7920
0dfbf9d7 7921 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7922 return (const reg_entry *) NULL;
7923
192dc9c6
JB		 7924 if ((r->reg_type.bitfield.reg32
7925 || r->reg_type.bitfield.sreg3
7926 || r->reg_type.bitfield.control
7927 || r->reg_type.bitfield.debug
7928 || r->reg_type.bitfield.test)
7929 && !cpu_arch_flags.bitfield.cpui386)
7930 return (const reg_entry *) NULL;
7931
309d3373
JB		 7932 if (r->reg_type.bitfield.floatreg
7933 && !cpu_arch_flags.bitfield.cpu8087
7934 && !cpu_arch_flags.bitfield.cpu287
7935 && !cpu_arch_flags.bitfield.cpu387)
7936 return (const reg_entry *) NULL;
7937
192dc9c6
JB		 7938 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7939 return (const reg_entry *) NULL;
7940
7941 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7942 return (const reg_entry *) NULL;
7943
40f12533
L		 7944 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7945 return (const reg_entry *) NULL;
7946
db51cc60 7947 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7948 if (!allow_index_reg
db51cc60
L		 7949 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7950 return (const reg_entry *) NULL;
7951
a60de03c
JB		 7952 if (((r->reg_flags & (RegRex64 | RegRex))
7953 || r->reg_type.bitfield.reg64)
40fb9820 7954 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7955 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7956 && flag_code != CODE_64BIT)
20f0a1fc 7957 return (const reg_entry *) NULL;
1ae00879 7958
b7240065
JB		 7959 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7960 return (const reg_entry *) NULL;
7961
252b5132
RH		 7962 return r;
7963}
4d1bb795
JB		 7964
7965/* REG_STRING starts *before* REGISTER_PREFIX. */
7966
7967static const reg_entry *
7968parse_register (char *reg_string, char **end_op)
7969{
7970 const reg_entry *r;
7971
7972 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7973 r = parse_real_register (reg_string, end_op);
7974 else
7975 r = NULL;
7976 if (!r)
7977 {
7978 char *save = input_line_pointer;
7979 char c;
7980 symbolS *symbolP;
7981
7982 input_line_pointer = reg_string;
7983 c = get_symbol_end ();
7984 symbolP = symbol_find (reg_string);
7985 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7986 {
7987 const expressionS *e = symbol_get_value_expression (symbolP);
7988
0398aac5 7989 know (e->X_op == O_register);
4eed87de 7990 know (e->X_add_number >= 0
c3fe08fa 7991 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7992 r = i386_regtab + e->X_add_number;
7993 *end_op = input_line_pointer;
7994 }
7995 *input_line_pointer = c;
7996 input_line_pointer = save;
7997 }
7998 return r;
7999}
8000
8001int
8002i386_parse_name (char *name, expressionS *e, char *nextcharP)
8003{
8004 const reg_entry *r;
8005 char *end = input_line_pointer;
8006
8007 *end = *nextcharP;
8008 r = parse_register (name, &input_line_pointer);
8009 if (r && end <= input_line_pointer)
8010 {
8011 *nextcharP = *input_line_pointer;
8012 *input_line_pointer = 0;
8013 e->X_op = O_register;
8014 e->X_add_number = r - i386_regtab;
8015 return 1;
8016 }
8017 input_line_pointer = end;
8018 *end = 0;
ee86248c 8019 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8020}
8021
8022void
8023md_operand (expressionS *e)
8024{
ee86248c
JB		 8025 char *end;
8026 const reg_entry *r;
4d1bb795 8027
ee86248c
JB		 8028 switch (*input_line_pointer)
8029 {
8030 case REGISTER_PREFIX:
8031 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8032 if (r)
8033 {
8034 e->X_op = O_register;
8035 e->X_add_number = r - i386_regtab;
8036 input_line_pointer = end;
8037 }
ee86248c
JB		 8038 break;
8039
8040 case '[':
9c2799c2 8041 gas_assert (intel_syntax);
ee86248c
JB		 8042 end = input_line_pointer++;
8043 expression (e);
8044 if (*input_line_pointer == ']')
8045 {
8046 ++input_line_pointer;
8047 e->X_op_symbol = make_expr_symbol (e);
8048 e->X_add_symbol = NULL;
8049 e->X_add_number = 0;
8050 e->X_op = O_index;
8051 }
8052 else
8053 {
8054 e->X_op = O_absent;
8055 input_line_pointer = end;
8056 }
8057 break;
4d1bb795
JB		 8058 }
8059}
8060
252b5132 8061\f
4cc782b5 8062#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8063const char *md_shortopts = "kVQ:sqn";
252b5132 8064#else
12b55ccc 8065const char *md_shortopts = "qn";
252b5132 8066#endif
6e0b89ee 8067
3e73aa7c 8068#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8069#define OPTION_64 (OPTION_MD_BASE + 1)
8070#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8071#define OPTION_MARCH (OPTION_MD_BASE + 3)
8072#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8073#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8074#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8075#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8076#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8077#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8078#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8079#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8080#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
b3b91714 8081
99ad8390
NC		 8082struct option md_longopts[] =
8083{
3e73aa7c 8084 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8085#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8086 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8087 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 8088#endif
b3b91714 8089 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8090 {"march", required_argument, NULL, OPTION_MARCH},
8091 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8092 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8093 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8094 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8095 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8096 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8097 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8098 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8099 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8100 {NULL, no_argument, NULL, 0}
8101};
8102size_t md_longopts_size = sizeof (md_longopts);
8103
8104int
9103f4f4 8105md_parse_option (int c, char *arg)
252b5132 8106{
91d6fa6a 8107 unsigned int j;
6305a203 8108 char *arch, *next;
9103f4f4 8109
252b5132
RH		 8110 switch (c)
8111 {
12b55ccc
L		 8112 case 'n':
8113 optimize_align_code = 0;
8114 break;
8115
a38cf1db
AM		 8116 case 'q':
8117 quiet_warnings = 1;
252b5132
RH		 8118 break;
8119
8120#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8121 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8122 should be emitted or not. FIXME: Not implemented. */
8123 case 'Q':
252b5132
RH		 8124 break;
8125
8126 /* -V: SVR4 argument to print version ID. */
8127 case 'V':
8128 print_version_id ();
8129 break;
8130
a38cf1db
AM		 8131 /* -k: Ignore for FreeBSD compatibility. */
8132 case 'k':
252b5132 8133 break;
4cc782b5
ILT		 8134
8135 case 's':
8136 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8137 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8138 break;
99ad8390 8139#endif
321098a5
L		 8140#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8141 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8142 case OPTION_64:
8143 {
8144 const char **list, **l;
8145
3e73aa7c
JH		 8146 list = bfd_target_list ();
8147 for (l = list; *l != NULL; l++)
8620418b 8148 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8149 || strcmp (*l, "coff-x86-64") == 0
8150 || strcmp (*l, "pe-x86-64") == 0
8151 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8152 {
8153 default_arch = "x86_64";
8154 break;
8155 }
3e73aa7c 8156 if (*l == NULL)
6e0b89ee 8157 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8158 free (list);
8159 }
8160 break;
8161#endif
252b5132 8162
6e0b89ee
AM		 8163 case OPTION_32:
8164 default_arch = "i386";
8165 break;
8166
b3b91714
AM		 8167 case OPTION_DIVIDE:
8168#ifdef SVR4_COMMENT_CHARS
8169 {
8170 char *n, *t;
8171 const char *s;
8172
8173 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8174 t = n;
8175 for (s = i386_comment_chars; *s != '\0'; s++)
8176 if (*s != '/')
8177 *t++ = *s;
8178 *t = '\0';
8179 i386_comment_chars = n;
8180 }
8181#endif
8182 break;
8183
9103f4f4 8184 case OPTION_MARCH:
6305a203
L		 8185 arch = xstrdup (arg);
8186 do
9103f4f4 8187 {
6305a203
L		 8188 if (*arch == '.')
8189 as_fatal (_("Invalid -march= option: `%s'"), arg);
8190 next = strchr (arch, '+');
8191 if (next)
8192 *next++ = '\0';
91d6fa6a 8193 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8194 {
91d6fa6a 8195 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8196 {
6305a203 8197 /* Processor. */
1ded5609
JB		 8198 if (! cpu_arch[j].flags.bitfield.cpui386)
8199 continue;
8200
91d6fa6a 8201 cpu_arch_name = cpu_arch[j].name;
6305a203 8202 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8203 cpu_arch_flags = cpu_arch[j].flags;
8204 cpu_arch_isa = cpu_arch[j].type;
8205 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8206 if (!cpu_arch_tune_set)
8207 {
8208 cpu_arch_tune = cpu_arch_isa;
8209 cpu_arch_tune_flags = cpu_arch_isa_flags;
8210 }
8211 break;
8212 }
91d6fa6a
NC		 8213 else if (*cpu_arch [j].name == '.'
8214 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8215 {
8216 /* ISA entension. */
8217 i386_cpu_flags flags;
309d3373
JB		 8218
8219 if (strncmp (arch, "no", 2))
8220 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8221 cpu_arch[j].flags);
309d3373
JB		 8222 else
8223 flags = cpu_flags_and_not (cpu_arch_flags,
91d6fa6a 8224 cpu_arch[j].flags);
0dfbf9d7 8225 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8226 {
8227 if (cpu_sub_arch_name)
8228 {
8229 char *name = cpu_sub_arch_name;
8230 cpu_sub_arch_name = concat (name,
91d6fa6a 8231 cpu_arch[j].name,
1bf57e9f 8232 (const char *) NULL);
6305a203
L		 8233 free (name);
8234 }
8235 else
91d6fa6a 8236 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8237 cpu_arch_flags = flags;
8238 }
8239 break;
ccc9c027 8240 }
9103f4f4 8241 }
6305a203 8242
91d6fa6a 8243 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8244 as_fatal (_("Invalid -march= option: `%s'"), arg);
8245
8246 arch = next;
9103f4f4 8247 }
6305a203 8248 while (next != NULL );
9103f4f4
L		 8249 break;
8250
8251 case OPTION_MTUNE:
8252 if (*arg == '.')
8253 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8254 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8255 {
91d6fa6a 8256 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8257 {
ccc9c027 8258 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8259 cpu_arch_tune = cpu_arch [j].type;
8260 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8261 break;
8262 }
8263 }
91d6fa6a 8264 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8265 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8266 break;
8267
1efbbeb4
L		 8268 case OPTION_MMNEMONIC:
8269 if (strcasecmp (arg, "att") == 0)
8270 intel_mnemonic = 0;
8271 else if (strcasecmp (arg, "intel") == 0)
8272 intel_mnemonic = 1;
8273 else
8274 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8275 break;
8276
8277 case OPTION_MSYNTAX:
8278 if (strcasecmp (arg, "att") == 0)
8279 intel_syntax = 0;
8280 else if (strcasecmp (arg, "intel") == 0)
8281 intel_syntax = 1;
8282 else
8283 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8284 break;
8285
8286 case OPTION_MINDEX_REG:
8287 allow_index_reg = 1;
8288 break;
8289
8290 case OPTION_MNAKED_REG:
8291 allow_naked_reg = 1;
8292 break;
8293
8294 case OPTION_MOLD_GCC:
8295 old_gcc = 1;
1efbbeb4
L		 8296 break;
8297
c0f3af97
L		 8298 case OPTION_MSSE2AVX:
8299 sse2avx = 1;
8300 break;
8301
daf50ae7
L		 8302 case OPTION_MSSE_CHECK:
8303 if (strcasecmp (arg, "error") == 0)
8304 sse_check = sse_check_error;
8305 else if (strcasecmp (arg, "warning") == 0)
8306 sse_check = sse_check_warning;
8307 else if (strcasecmp (arg, "none") == 0)
8308 sse_check = sse_check_none;
8309 else
8310 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8311 break;
8312
539f890d
L		 8313 case OPTION_MAVXSCALAR:
8314 if (strcasecmp (arg, "128") == 0)
8315 avxscalar = vex128;
8316 else if (strcasecmp (arg, "256") == 0)
8317 avxscalar = vex256;
8318 else
8319 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8320 break;
8321
252b5132
RH		 8322 default:
8323 return 0;
8324 }
8325 return 1;
8326}
8327
8a2c8fef
L		 8328#define MESSAGE_TEMPLATE \
8329" "
8330
8331static void
1ded5609 8332show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8333{
8334 static char message[] = MESSAGE_TEMPLATE;
8335 char *start = message + 27;
8336 char *p;
8337 int size = sizeof (MESSAGE_TEMPLATE);
8338 int left;
8339 const char *name;
8340 int len;
8341 unsigned int j;
8342
8343 p = start;
8344 left = size - (start - message);
8345 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8346 {
8347 /* Should it be skipped? */
8348 if (cpu_arch [j].skip)
8349 continue;
8350
8351 name = cpu_arch [j].name;
8352 len = cpu_arch [j].len;
8353 if (*name == '.')
8354 {
8355 /* It is an extension. Skip if we aren't asked to show it. */
8356 if (ext)
8357 {
8358 name++;
8359 len--;
8360 }
8361 else
8362 continue;
8363 }
8364 else if (ext)
8365 {
8366 /* It is an processor. Skip if we show only extension. */
8367 continue;
8368 }
1ded5609
JB		 8369 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8370 {
8371 /* It is an impossible processor - skip. */
8372 continue;
8373 }
8a2c8fef
L		 8374
8375 /* Reserve 2 spaces for ", " or ",\0" */
8376 left -= len + 2;
8377
8378 /* Check if there is any room. */
8379 if (left >= 0)
8380 {
8381 if (p != start)
8382 {
8383 *p++ = ',';
8384 *p++ = ' ';
8385 }
8386 p = mempcpy (p, name, len);
8387 }
8388 else
8389 {
8390 /* Output the current message now and start a new one. */
8391 *p++ = ',';
8392 *p = '\0';
8393 fprintf (stream, "%s\n", message);
8394 p = start;
8395 left = size - (start - message) - len - 2;
8396
8397 gas_assert (left >= 0);
8398
8399 p = mempcpy (p, name, len);
8400 }
8401 }
8402
8403 *p = '\0';
8404 fprintf (stream, "%s\n", message);
8405}
8406
252b5132 8407void
8a2c8fef 8408md_show_usage (FILE *stream)
252b5132 8409{
4cc782b5
ILT		 8410#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8411 fprintf (stream, _("\
a38cf1db
AM		 8412 -Q ignored\n\
8413 -V print assembler version number\n\
b3b91714
AM		 8414 -k ignored\n"));
8415#endif
8416 fprintf (stream, _("\
12b55ccc 8417 -n Do not optimize code alignment\n\
b3b91714
AM		 8418 -q quieten some warnings\n"));
8419#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8420 fprintf (stream, _("\
a38cf1db 8421 -s ignored\n"));
b3b91714 8422#endif
321098a5
L		 8423#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8424 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8425 fprintf (stream, _("\
8426 --32/--64 generate 32bit/64bit code\n"));
8427#endif
b3b91714
AM		 8428#ifdef SVR4_COMMENT_CHARS
8429 fprintf (stream, _("\
8430 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8431#else
8432 fprintf (stream, _("\
b3b91714 8433 --divide ignored\n"));
4cc782b5 8434#endif
9103f4f4 8435 fprintf (stream, _("\
6305a203 8436 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8437 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8438 show_arch (stream, 0, 1);
8a2c8fef
L		 8439 fprintf (stream, _("\
8440 EXTENSION is combination of:\n"));
1ded5609 8441 show_arch (stream, 1, 0);
6305a203 8442 fprintf (stream, _("\
8a2c8fef 8443 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8444 show_arch (stream, 0, 0);
ba104c83 8445 fprintf (stream, _("\
c0f3af97
L		 8446 -msse2avx encode SSE instructions with VEX prefix\n"));
8447 fprintf (stream, _("\
daf50ae7
L		 8448 -msse-check=[none|error|warning]\n\
8449 check SSE instructions\n"));
8450 fprintf (stream, _("\
539f890d
L		 8451 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8452 length\n"));
8453 fprintf (stream, _("\
ba104c83
L		 8454 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8455 fprintf (stream, _("\
8456 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8457 fprintf (stream, _("\
8458 -mindex-reg support pseudo index registers\n"));
8459 fprintf (stream, _("\
8460 -mnaked-reg don't require `%%' prefix for registers\n"));
8461 fprintf (stream, _("\
8462 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8463}
8464
3e73aa7c 8465#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8466 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8467 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8468
8469/* Pick the target format to use. */
8470
47926f60 8471const char *
e3bb37b5 8472i386_target_format (void)
252b5132 8473{
3e73aa7c 8474 if (!strcmp (default_arch, "x86_64"))
78f12dd3 8475 update_code_flag (CODE_64BIT, 1);
3e73aa7c 8476 else if (!strcmp (default_arch, "i386"))
78f12dd3 8477 update_code_flag (CODE_32BIT, 1);
3e73aa7c
JH		 8478 else
8479 as_fatal (_("Unknown architecture"));
89507696
JB		 8480
8481 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8482 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8483 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8484 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8485
252b5132
RH		 8486 switch (OUTPUT_FLAVOR)
8487 {
9384f2ff 8488#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8489 case bfd_target_aout_flavour:
47926f60 8490 return AOUT_TARGET_FORMAT;
4c63da97 8491#endif
9384f2ff
AM		 8492#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8493# if defined (TE_PE) || defined (TE_PEP)
8494 case bfd_target_coff_flavour:
8495 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8496# elif defined (TE_GO32)
0561d57c
JK		 8497 case bfd_target_coff_flavour:
8498 return "coff-go32";
9384f2ff 8499# else
252b5132
RH		 8500 case bfd_target_coff_flavour:
8501 return "coff-i386";
9384f2ff 8502# endif
4c63da97 8503#endif
3e73aa7c 8504#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8505 case bfd_target_elf_flavour:
3e73aa7c 8506 {
e5cb08ac 8507 if (flag_code == CODE_64BIT)
4fa24527
JB		 8508 {
8509 object_64bit = 1;
8510 use_rela_relocations = 1;
8511 }
3632d14b 8512 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8513 {
8514 if (flag_code != CODE_64BIT)
8515 as_fatal (_("Intel L1OM is 64bit only"));
8516 return ELF_TARGET_L1OM_FORMAT;
8517 }
8518 else
8519 return (flag_code == CODE_64BIT
8520 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8521 }
e57f8c65
TG		 8522#endif
8523#if defined (OBJ_MACH_O)
8524 case bfd_target_mach_o_flavour:
8525 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8526#endif
252b5132
RH		 8527 default:
8528 abort ();
8529 return NULL;
8530 }
8531}
8532
47926f60 8533#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8534
8535#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8536void
8537i386_elf_emit_arch_note (void)
a847613f 8538{
718ddfc0 8539 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8540 {
8541 char *p;
8542 asection *seg = now_seg;
8543 subsegT subseg = now_subseg;
8544 Elf_Internal_Note i_note;
8545 Elf_External_Note e_note;
8546 asection *note_secp;
8547 int len;
8548
8549 /* Create the .note section. */
8550 note_secp = subseg_new (".note", 0);
8551 bfd_set_section_flags (stdoutput,
8552 note_secp,
8553 SEC_HAS_CONTENTS | SEC_READONLY);
8554
8555 /* Process the arch string. */
8556 len = strlen (cpu_arch_name);
8557
8558 i_note.namesz = len + 1;
8559 i_note.descsz = 0;
8560 i_note.type = NT_ARCH;
8561 p = frag_more (sizeof (e_note.namesz));
8562 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8563 p = frag_more (sizeof (e_note.descsz));
8564 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8565 p = frag_more (sizeof (e_note.type));
8566 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8567 p = frag_more (len + 1);
8568 strcpy (p, cpu_arch_name);
8569
8570 frag_align (2, 0, 0);
8571
8572 subseg_set (seg, subseg);
8573 }
8574}
8575#endif
252b5132 8576\f
252b5132
RH		 8577symbolS *
8578md_undefined_symbol (name)
8579 char *name;
8580{
18dc2407
ILT		 8581 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8582 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8583 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8584 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8585 {
8586 if (!GOT_symbol)
8587 {
8588 if (symbol_find (name))
8589 as_bad (_("GOT already in symbol table"));
8590 GOT_symbol = symbol_new (name, undefined_section,
8591 (valueT) 0, &zero_address_frag);
8592 };
8593 return GOT_symbol;
8594 }
252b5132
RH		 8595 return 0;
8596}
8597
8598/* Round up a section size to the appropriate boundary. */
47926f60 8599
252b5132
RH		 8600valueT
8601md_section_align (segment, size)
ab9da554 8602 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8603 valueT size;
8604{
4c63da97
AM		 8605#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8606 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8607 {
8608 /* For a.out, force the section size to be aligned. If we don't do
8609 this, BFD will align it for us, but it will not write out the
8610 final bytes of the section. This may be a bug in BFD, but it is
8611 easier to fix it here since that is how the other a.out targets
8612 work. */
8613 int align;
8614
8615 align = bfd_get_section_alignment (stdoutput, segment);
8616 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8617 }
252b5132
RH		 8618#endif
8619
8620 return size;
8621}
8622
8623/* On the i386, PC-relative offsets are relative to the start of the
8624 next instruction. That is, the address of the offset, plus its
8625 size, since the offset is always the last part of the insn. */
8626
8627long
e3bb37b5 8628md_pcrel_from (fixS *fixP)
252b5132
RH		 8629{
8630 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8631}
8632
8633#ifndef I386COFF
8634
8635static void
e3bb37b5 8636s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8637{
29b0f896 8638 int temp;
252b5132 8639
8a75718c
JB		 8640#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8641 if (IS_ELF)
8642 obj_elf_section_change_hook ();
8643#endif
252b5132
RH		 8644 temp = get_absolute_expression ();
8645 subseg_set (bss_section, (subsegT) temp);
8646 demand_empty_rest_of_line ();
8647}
8648
8649#endif
8650
252b5132 8651void
e3bb37b5 8652i386_validate_fix (fixS *fixp)
252b5132
RH		 8653{
8654 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8655 {
23df1078
JH		 8656 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8657 {
4fa24527 8658 if (!object_64bit)
23df1078
JH		 8659 abort ();
8660 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8661 }
8662 else
8663 {
4fa24527 8664 if (!object_64bit)
d6ab8113
JB		 8665 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8666 else
8667 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8668 }
252b5132
RH		 8669 fixp->fx_subsy = 0;
8670 }
8671}
8672
252b5132
RH		 8673arelent *
8674tc_gen_reloc (section, fixp)
ab9da554 8675 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8676 fixS *fixp;
8677{
8678 arelent *rel;
8679 bfd_reloc_code_real_type code;
8680
8681 switch (fixp->fx_r_type)
8682 {
3e73aa7c
JH		 8683 case BFD_RELOC_X86_64_PLT32:
8684 case BFD_RELOC_X86_64_GOT32:
8685 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8686 case BFD_RELOC_386_PLT32:
8687 case BFD_RELOC_386_GOT32:
8688 case BFD_RELOC_386_GOTOFF:
8689 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8690 case BFD_RELOC_386_TLS_GD:
8691 case BFD_RELOC_386_TLS_LDM:
8692 case BFD_RELOC_386_TLS_LDO_32:
8693 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8694 case BFD_RELOC_386_TLS_IE:
8695 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8696 case BFD_RELOC_386_TLS_LE_32:
8697 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8698 case BFD_RELOC_386_TLS_GOTDESC:
8699 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8700 case BFD_RELOC_X86_64_TLSGD:
8701 case BFD_RELOC_X86_64_TLSLD:
8702 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8703 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8704 case BFD_RELOC_X86_64_GOTTPOFF:
8705 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8706 case BFD_RELOC_X86_64_TPOFF64:
8707 case BFD_RELOC_X86_64_GOTOFF64:
8708 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8709 case BFD_RELOC_X86_64_GOT64:
8710 case BFD_RELOC_X86_64_GOTPCREL64:
8711 case BFD_RELOC_X86_64_GOTPC64:
8712 case BFD_RELOC_X86_64_GOTPLT64:
8713 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8714 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8715 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8716 case BFD_RELOC_RVA:
8717 case BFD_RELOC_VTABLE_ENTRY:
8718 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8719#ifdef TE_PE
8720 case BFD_RELOC_32_SECREL:
8721#endif
252b5132
RH		 8722 code = fixp->fx_r_type;
8723 break;
dbbaec26
L		 8724 case BFD_RELOC_X86_64_32S:
8725 if (!fixp->fx_pcrel)
8726 {
8727 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8728 code = fixp->fx_r_type;
8729 break;
8730 }
252b5132 8731 default:
93382f6d 8732 if (fixp->fx_pcrel)
252b5132 8733 {
93382f6d
AM		 8734 switch (fixp->fx_size)
8735 {
8736 default:
b091f402
AM		 8737 as_bad_where (fixp->fx_file, fixp->fx_line,
8738 _("can not do %d byte pc-relative relocation"),
8739 fixp->fx_size);
93382f6d
AM		 8740 code = BFD_RELOC_32_PCREL;
8741 break;
8742 case 1: code = BFD_RELOC_8_PCREL; break;
8743 case 2: code = BFD_RELOC_16_PCREL; break;
8744 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8745#ifdef BFD64
8746 case 8: code = BFD_RELOC_64_PCREL; break;
8747#endif
93382f6d
AM		 8748 }
8749 }
8750 else
8751 {
8752 switch (fixp->fx_size)
8753 {
8754 default:
b091f402
AM		 8755 as_bad_where (fixp->fx_file, fixp->fx_line,
8756 _("can not do %d byte relocation"),
8757 fixp->fx_size);
93382f6d
AM		 8758 code = BFD_RELOC_32;
8759 break;
8760 case 1: code = BFD_RELOC_8; break;
8761 case 2: code = BFD_RELOC_16; break;
8762 case 4: code = BFD_RELOC_32; break;
937149dd 8763#ifdef BFD64
3e73aa7c 8764 case 8: code = BFD_RELOC_64; break;
937149dd 8765#endif
93382f6d 8766 }
252b5132
RH		 8767 }
8768 break;
8769 }
252b5132 8770
d182319b
JB		 8771 if ((code == BFD_RELOC_32
8772 || code == BFD_RELOC_32_PCREL
8773 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8774 && GOT_symbol
8775 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8776 {
4fa24527 8777 if (!object_64bit)
d6ab8113
JB		 8778 code = BFD_RELOC_386_GOTPC;
8779 else
8780 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8781 }
7b81dfbb
AJ		 8782 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8783 && GOT_symbol
8784 && fixp->fx_addsy == GOT_symbol)
8785 {
8786 code = BFD_RELOC_X86_64_GOTPC64;
8787 }
252b5132
RH		 8788
8789 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8790 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8791 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8792
8793 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8794
3e73aa7c
JH		 8795 if (!use_rela_relocations)
8796 {
8797 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8798 vtable entry to be used in the relocation's section offset. */
8799 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8800 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8801#if defined (OBJ_COFF) && defined (TE_PE)
8802 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8803 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8804 else
8805#endif
c6682705 8806 rel->addend = 0;
3e73aa7c
JH		 8807 }
8808 /* Use the rela in 64bit mode. */
252b5132 8809 else
3e73aa7c 8810 {
062cd5e7
AS		 8811 if (!fixp->fx_pcrel)
8812 rel->addend = fixp->fx_offset;
8813 else
8814 switch (code)
8815 {
8816 case BFD_RELOC_X86_64_PLT32:
8817 case BFD_RELOC_X86_64_GOT32:
8818 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8819 case BFD_RELOC_X86_64_TLSGD:
8820 case BFD_RELOC_X86_64_TLSLD:
8821 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8822 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8823 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8824 rel->addend = fixp->fx_offset - fixp->fx_size;
8825 break;
8826 default:
8827 rel->addend = (section->vma
8828 - fixp->fx_size
8829 + fixp->fx_addnumber
8830 + md_pcrel_from (fixp));
8831 break;
8832 }
3e73aa7c
JH		 8833 }
8834
252b5132
RH		 8835 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8836 if (rel->howto == NULL)
8837 {
8838 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8839 _("cannot represent relocation type %s"),
252b5132
RH		 8840 bfd_get_reloc_code_name (code));
8841 /* Set howto to a garbage value so that we can keep going. */
8842 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8843 gas_assert (rel->howto != NULL);
252b5132
RH		 8844 }
8845
8846 return rel;
8847}
8848
ee86248c 8849#include "tc-i386-intel.c"
54cfded0 8850
a60de03c
JB		 8851void
8852tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8853{
a60de03c
JB		 8854 int saved_naked_reg;
8855 char saved_register_dot;
54cfded0 8856
a60de03c
JB		 8857 saved_naked_reg = allow_naked_reg;
8858 allow_naked_reg = 1;
8859 saved_register_dot = register_chars['.'];
8860 register_chars['.'] = '.';
8861 allow_pseudo_reg = 1;
8862 expression_and_evaluate (exp);
8863 allow_pseudo_reg = 0;
8864 register_chars['.'] = saved_register_dot;
8865 allow_naked_reg = saved_naked_reg;
8866
e96d56a1 8867 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8868 {
a60de03c
JB		 8869 if ((addressT) exp->X_add_number < i386_regtab_size)
8870 {
8871 exp->X_op = O_constant;
8872 exp->X_add_number = i386_regtab[exp->X_add_number]
8873 .dw2_regnum[flag_code >> 1];
8874 }
8875 else
8876 exp->X_op = O_illegal;
54cfded0 8877 }
54cfded0
AM		 8878}
8879
8880void
8881tc_x86_frame_initial_instructions (void)
8882{
a60de03c
JB		 8883 static unsigned int sp_regno[2];
8884
8885 if (!sp_regno[flag_code >> 1])
8886 {
8887 char *saved_input = input_line_pointer;
8888 char sp[][4] = {"esp", "rsp"};
8889 expressionS exp;
a4447b93 8890
a60de03c
JB		 8891 input_line_pointer = sp[flag_code >> 1];
8892 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8893 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8894 sp_regno[flag_code >> 1] = exp.X_add_number;
8895 input_line_pointer = saved_input;
8896 }
a4447b93 8897
a60de03c 8898 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8899 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8900}
d2b2c203
DJ		 8901
8902int
8903i386_elf_section_type (const char *str, size_t len)
8904{
8905 if (flag_code == CODE_64BIT
8906 && len == sizeof ("unwind") - 1
8907 && strncmp (str, "unwind", 6) == 0)
8908 return SHT_X86_64_UNWIND;
8909
8910 return -1;
8911}
bb41ade5 8912
ad5fec3b
EB		 8913#ifdef TE_SOLARIS
8914void
8915i386_solaris_fix_up_eh_frame (segT sec)
8916{
8917 if (flag_code == CODE_64BIT)
8918 elf_section_type (sec) = SHT_X86_64_UNWIND;
8919}
8920#endif
8921
bb41ade5
AM		 8922#ifdef TE_PE
8923void
8924tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8925{
91d6fa6a 8926 expressionS exp;
bb41ade5 8927
91d6fa6a
NC		 8928 exp.X_op = O_secrel;
8929 exp.X_add_symbol = symbol;
8930 exp.X_add_number = 0;
8931 emit_expr (&exp, size);
bb41ade5
AM		 8932}
8933#endif
3b22753a
L		 8934
8935#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8936/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8937
01e1a5bc 8938bfd_vma
3b22753a
L		 8939x86_64_section_letter (int letter, char **ptr_msg)
8940{
8941 if (flag_code == CODE_64BIT)
8942 {
8943 if (letter == 'l')
8944 return SHF_X86_64_LARGE;
8945
8946 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8947 }
3b22753a 8948 else
64e74474 8949 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8950 return -1;
8951}
8952
01e1a5bc 8953bfd_vma
3b22753a
L		 8954x86_64_section_word (char *str, size_t len)
8955{
8620418b 8956 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8957 return SHF_X86_64_LARGE;
8958
8959 return -1;
8960}
8961
8962static void
8963handle_large_common (int small ATTRIBUTE_UNUSED)
8964{
8965 if (flag_code != CODE_64BIT)
8966 {
8967 s_comm_internal (0, elf_common_parse);
8968 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8969 }
8970 else
8971 {
8972 static segT lbss_section;
8973 asection *saved_com_section_ptr = elf_com_section_ptr;
8974 asection *saved_bss_section = bss_section;
8975
8976 if (lbss_section == NULL)
8977 {
8978 flagword applicable;
8979 segT seg = now_seg;
8980 subsegT subseg = now_subseg;
8981
8982 /* The .lbss section is for local .largecomm symbols. */
8983 lbss_section = subseg_new (".lbss", 0);
8984 applicable = bfd_applicable_section_flags (stdoutput);
8985 bfd_set_section_flags (stdoutput, lbss_section,
8986 applicable & SEC_ALLOC);
8987 seg_info (lbss_section)->bss = 1;
8988
8989 subseg_set (seg, subseg);
8990 }
8991
8992 elf_com_section_ptr = &_bfd_elf_large_com_section;
8993 bss_section = lbss_section;
8994
8995 s_comm_internal (0, elf_common_parse);
8996
8997 elf_com_section_ptr = saved_com_section_ptr;
8998 bss_section = saved_bss_section;
8999 }
9000}
9001#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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