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* gdb.ada/funcall_param: New test program.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
e3bb37b5
L		 58static void set_code_flag (int);
59static void set_16bit_gcc_code_flag (int);
60static void set_intel_syntax (int);
1efbbeb4 61static void set_intel_mnemonic (int);
db51cc60 62static void set_allow_index_reg (int);
e3bb37b5 63static void set_cpu_arch (int);
6482c264 64#ifdef TE_PE
e3bb37b5 65static void pe_directive_secrel (int);
6482c264 66#endif
e3bb37b5
L		 67static void signed_cons (int);
68static char *output_invalid (int c);
69static int i386_operand (char *);
70static int i386_intel_operand (char *, int);
71static const reg_entry *parse_register (char *, char **);
72static char *parse_insn (char *, char *);
73static char *parse_operands (char *, const char *);
74static void swap_operands (void);
4d456e3d 75static void swap_2_operands (int, int);
e3bb37b5
L		 76static void optimize_imm (void);
77static void optimize_disp (void);
78static int match_template (void);
79static int check_string (void);
80static int process_suffix (void);
81static int check_byte_reg (void);
82static int check_long_reg (void);
83static int check_qword_reg (void);
84static int check_word_reg (void);
85static int finalize_imm (void);
85f10a01 86static void process_drex (void);
e3bb37b5
L		 87static int process_operands (void);
88static const seg_entry *build_modrm_byte (void);
89static void output_insn (void);
90static void output_imm (fragS *, offsetT);
91static void output_disp (fragS *, offsetT);
29b0f896 92#ifndef I386COFF
e3bb37b5 93static void s_bss (int);
252b5132 94#endif
17d4e2a2
L		 95#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96static void handle_large_common (int small ATTRIBUTE_UNUSED);
97#endif
252b5132 98
a847613f 99static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 100
252b5132 101/* 'md_assemble ()' gathers together information and puts it into a
47926f60 102 i386_insn. */
252b5132 103
520dc8e8
AM		 104union i386_op
105 {
106 expressionS *disps;
107 expressionS *imms;
108 const reg_entry *regs;
109 };
110
252b5132
RH		 111struct _i386_insn
112 {
47926f60 113 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 114 template tm;
115
116 /* SUFFIX holds the instruction mnemonic suffix if given.
117 (e.g. 'l' for 'movl') */
118 char suffix;
119
47926f60 120 /* OPERANDS gives the number of given operands. */
252b5132
RH		 121 unsigned int operands;
122
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
47926f60 125 operands. */
252b5132
RH		 126 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
127
128 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 129 use OP[i] for the corresponding operand. */
40fb9820 130 i386_operand_type types[MAX_OPERANDS];
252b5132 131
520dc8e8
AM		 132 /* Displacement expression, immediate expression, or register for each
133 operand. */
134 union i386_op op[MAX_OPERANDS];
252b5132 135
3e73aa7c
JH		 136 /* Flags for operands. */
137 unsigned int flags[MAX_OPERANDS];
138#define Operand_PCrel 1
139
252b5132 140 /* Relocation type for operand */
f86103b7 141 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 142
252b5132
RH		 143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry *base_reg;
146 const reg_entry *index_reg;
147 unsigned int log2_scale_factor;
148
149 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 150 explicit segment overrides are given. */
ce8a8b2f 151 const seg_entry *seg[2];
252b5132
RH		 152
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes;
156 unsigned char prefix[MAX_PREFIXES];
157
158 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
252b5132
RH		 161
162 modrm_byte rm;
3e73aa7c 163 rex_byte rex;
252b5132 164 sib_byte sib;
85f10a01 165 drex_byte drex;
252b5132
RH		 166 };
167
168typedef struct _i386_insn i386_insn;
169
170/* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
32137342 172const char extra_symbol_chars[] = "*%-(["
252b5132 173#ifdef LEX_AT
32137342
NC		 174 "@"
175#endif
176#ifdef LEX_QM
177 "?"
252b5132 178#endif
32137342 179 ;
252b5132 180
29b0f896
AM		 181#if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 183 && !defined (TE_GNU) \
29b0f896 184 && !defined (TE_LINUX) \
32137342 185 && !defined (TE_NETWARE) \
29b0f896
AM		 186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
252b5132 188/* This array holds the chars that always start a comment. If the
b3b91714
AM		 189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191const char *i386_comment_chars = "#/";
192#define SVR4_COMMENT_CHARS 1
252b5132 193#define PREFIX_SEPARATOR '\\'
252b5132 194
b3b91714
AM		 195#else
196const char *i386_comment_chars = "#";
197#define PREFIX_SEPARATOR '/'
198#endif
199
252b5132
RH		 200/* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 204 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
252b5132 207 '/' isn't otherwise defined. */
b3b91714 208const char line_comment_chars[] = "#/";
252b5132 209
63a0b638 210const char line_separator_chars[] = ";";
252b5132 211
ce8a8b2f
AM		 212/* Chars that can be used to separate mant from exp in floating point
213 nums. */
252b5132
RH		 214const char EXP_CHARS[] = "eE";
215
ce8a8b2f
AM		 216/* Chars that mean this number is a floating point constant
217 As in 0f12.456
218 or 0d1.2345e12. */
252b5132
RH		 219const char FLT_CHARS[] = "fFdDxX";
220
ce8a8b2f 221/* Tables for lexical analysis. */
252b5132
RH		 222static char mnemonic_chars[256];
223static char register_chars[256];
224static char operand_chars[256];
225static char identifier_chars[256];
226static char digit_chars[256];
227
ce8a8b2f 228/* Lexical macros. */
252b5132
RH		 229#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230#define is_operand_char(x) (operand_chars[(unsigned char) x])
231#define is_register_char(x) (register_chars[(unsigned char) x])
232#define is_space_char(x) ((x) == ' ')
233#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234#define is_digit_char(x) (digit_chars[(unsigned char) x])
235
0234cb7c 236/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 237static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
238
239/* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
47926f60 242 assembler instruction). */
252b5132 243static char save_stack[32];
ce8a8b2f 244static char *save_stack_p;
252b5132
RH		 245#define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247#define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
249
47926f60 250/* The instruction we're assembling. */
252b5132
RH		 251static i386_insn i;
252
253/* Possible templates for current insn. */
254static const templates *current_templates;
255
31b2323c
L		 256/* Per instruction expressionS buffers: max displacements & immediates. */
257static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
258static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 259
47926f60
KH		 260/* Current operand we are working on. */
261static int this_operand;
252b5132 262
3e73aa7c
JH		 263/* We support four different modes. FLAG_CODE variable is used to distinguish
264 these. */
265
266enum flag_code {
267 CODE_32BIT,
268 CODE_16BIT,
269 CODE_64BIT };
270
271static enum flag_code flag_code;
4fa24527 272static unsigned int object_64bit;
3e73aa7c
JH		 273static int use_rela_relocations = 0;
274
275/* The names used to print error messages. */
b77a7acd 276static const char *flag_code_names[] =
3e73aa7c
JH		 277 {
278 "32",
279 "16",
280 "64"
281 };
252b5132 282
47926f60
KH		 283/* 1 for intel syntax,
284 0 if att syntax. */
285static int intel_syntax = 0;
252b5132 286
1efbbeb4
L		 287/* 1 for intel mnemonic,
288 0 if att mnemonic. */
289static int intel_mnemonic = !SYSV386_COMPAT;
290
5209009a 291/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 292static int old_gcc = OLDGCC_COMPAT;
293
47926f60
KH		 294/* 1 if register prefix % not required. */
295static int allow_naked_reg = 0;
252b5132 296
ba104c83 297/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 298static int allow_index_reg = 0;
299
2ca3ace5
L		 300/* Register prefix used for error message. */
301static const char *register_prefix = "%";
302
47926f60
KH		 303/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306static char stackop_size = '\0';
eecb386c 307
12b55ccc
L		 308/* Non-zero to optimize code alignment. */
309int optimize_align_code = 1;
310
47926f60
KH		 311/* Non-zero to quieten some warnings. */
312static int quiet_warnings = 0;
a38cf1db 313
47926f60
KH		 314/* CPU name. */
315static const char *cpu_arch_name = NULL;
5c6af06e 316static const char *cpu_sub_arch_name = NULL;
a38cf1db 317
47926f60 318/* CPU feature flags. */
40fb9820
L		 319static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
320
ccc9c027
L		 321/* If we have selected a cpu we are generating instructions for. */
322static int cpu_arch_tune_set = 0;
323
9103f4f4
L		 324/* Cpu we are generating instructions for. */
325static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
326
327/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 328static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 329
ccc9c027
L		 330/* CPU instruction set architecture used. */
331static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
332
9103f4f4 333/* CPU feature flags of instruction set architecture used. */
40fb9820 334static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 335
fddf5b5b
AM		 336/* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338static unsigned int no_cond_jump_promotion = 0;
339
29b0f896 340/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 341static symbolS *GOT_symbol;
29b0f896 342
a4447b93
RH		 343/* The dwarf2 return column, adjusted for 32 or 64 bit. */
344unsigned int x86_dwarf2_return_column;
345
346/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347int x86_cie_data_alignment;
348
252b5132 349/* Interface to relax_segment.
fddf5b5b
AM		 350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
252b5132 353
47926f60 354/* Types. */
93c2a809
AM		 355#define UNCOND_JUMP 0
356#define COND_JUMP 1
357#define COND_JUMP86 2
fddf5b5b 358
47926f60 359/* Sizes. */
252b5132
RH		 360#define CODE16 1
361#define SMALL 0
29b0f896 362#define SMALL16 (SMALL | CODE16)
252b5132 363#define BIG 2
29b0f896 364#define BIG16 (BIG | CODE16)
252b5132
RH		 365
366#ifndef INLINE
367#ifdef __GNUC__
368#define INLINE __inline__
369#else
370#define INLINE
371#endif
372#endif
373
fddf5b5b
AM		 374#define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376#define TYPE_FROM_RELAX_STATE(s) \
377 ((s) >> 2)
378#define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 380
381/* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
388
389const relax_typeS md_relax_table[] =
390{
24eab124
AM		 391 /* The fields are:
392 1) most positive reach of this state,
393 2) most negative reach of this state,
93c2a809 394 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 395 4) which index into the table to try if we can't fit into this one. */
252b5132 396
fddf5b5b 397 /* UNCOND_JUMP states. */
93c2a809
AM		 398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
252b5132 402 {0, 0, 4, 0},
93c2a809
AM		 403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 405 {0, 0, 2, 0},
406
93c2a809
AM		 407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
fddf5b5b 413 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 414 1 extra opcode byte, 2 displacement bytes. */
415 {0, 0, 3, 0},
416
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
422 {0, 0, 5, 0},
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
425 {0, 0, 4, 0}
252b5132
RH		 426};
427
9103f4f4
L		 428static const arch_entry cpu_arch[] =
429{
430 {"generic32", PROCESSOR_GENERIC32,
40fb9820 431 CPU_GENERIC32_FLAGS },
9103f4f4 432 {"generic64", PROCESSOR_GENERIC64,
40fb9820 433 CPU_GENERIC64_FLAGS },
9103f4f4 434 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 435 CPU_NONE_FLAGS },
9103f4f4 436 {"i186", PROCESSOR_UNKNOWN,
40fb9820 437 CPU_I186_FLAGS },
9103f4f4 438 {"i286", PROCESSOR_UNKNOWN,
40fb9820 439 CPU_I286_FLAGS },
76bc74dc 440 {"i386", PROCESSOR_I386,
40fb9820 441 CPU_I386_FLAGS },
9103f4f4 442 {"i486", PROCESSOR_I486,
40fb9820 443 CPU_I486_FLAGS },
9103f4f4 444 {"i586", PROCESSOR_PENTIUM,
40fb9820 445 CPU_I586_FLAGS },
9103f4f4 446 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 447 CPU_I686_FLAGS },
9103f4f4 448 {"pentium", PROCESSOR_PENTIUM,
40fb9820 449 CPU_I586_FLAGS },
9103f4f4 450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 451 CPU_I686_FLAGS },
9103f4f4 452 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 453 CPU_P2_FLAGS },
9103f4f4 454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 455 CPU_P3_FLAGS },
9103f4f4 456 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 457 CPU_P4_FLAGS },
9103f4f4 458 {"prescott", PROCESSOR_NOCONA,
40fb9820 459 CPU_CORE_FLAGS },
9103f4f4 460 {"nocona", PROCESSOR_NOCONA,
40fb9820 461 CPU_NOCONA_FLAGS },
ef05d495 462 {"yonah", PROCESSOR_CORE,
40fb9820 463 CPU_CORE_FLAGS },
ef05d495 464 {"core", PROCESSOR_CORE,
40fb9820 465 CPU_CORE_FLAGS },
ef05d495 466 {"merom", PROCESSOR_CORE2,
40fb9820 467 CPU_CORE2_FLAGS },
ef05d495 468 {"core2", PROCESSOR_CORE2,
40fb9820 469 CPU_CORE2_FLAGS },
9103f4f4 470 {"k6", PROCESSOR_K6,
40fb9820 471 CPU_K6_FLAGS },
9103f4f4 472 {"k6_2", PROCESSOR_K6,
40fb9820 473 CPU_K6_2_FLAGS },
9103f4f4 474 {"athlon", PROCESSOR_ATHLON,
40fb9820 475 CPU_ATHLON_FLAGS },
9103f4f4 476 {"sledgehammer", PROCESSOR_K8,
40fb9820 477 CPU_K8_FLAGS },
9103f4f4 478 {"opteron", PROCESSOR_K8,
40fb9820 479 CPU_K8_FLAGS },
9103f4f4 480 {"k8", PROCESSOR_K8,
40fb9820 481 CPU_K8_FLAGS },
050dfa73 482 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 483 CPU_AMDFAM10_FLAGS },
9103f4f4 484 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 485 CPU_MMX_FLAGS },
9103f4f4 486 {".sse", PROCESSOR_UNKNOWN,
40fb9820 487 CPU_SSE_FLAGS },
9103f4f4 488 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 489 CPU_SSE2_FLAGS },
9103f4f4 490 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 491 CPU_SSE3_FLAGS },
ef05d495 492 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 493 CPU_SSSE3_FLAGS },
42903f7f 494 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 495 CPU_SSE4_1_FLAGS },
381d071f 496 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 497 CPU_SSE4_2_FLAGS },
381d071f 498 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 499 CPU_SSE4_2_FLAGS },
9103f4f4 500 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 501 CPU_3DNOW_FLAGS },
9103f4f4 502 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 503 CPU_3DNOWA_FLAGS },
9103f4f4 504 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 505 CPU_PADLOCK_FLAGS },
9103f4f4 506 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 507 CPU_SVME_FLAGS },
9103f4f4 508 {".svme", PROCESSOR_UNKNOWN,
40fb9820 509 CPU_SVME_FLAGS },
050dfa73 510 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 511 CPU_SSE4A_FLAGS },
050dfa73 512 {".abm", PROCESSOR_UNKNOWN,
40fb9820 513 CPU_ABM_FLAGS },
85f10a01
MM		 514 {".sse5", PROCESSOR_UNKNOWN,
515 CPU_SSE5_FLAGS },
e413e4e9
AM		 516};
517
29b0f896
AM		 518const pseudo_typeS md_pseudo_table[] =
519{
520#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
522#else
523 {"align", s_align_ptwo, 0},
524#endif
525 {"arch", set_cpu_arch, 0},
526#ifndef I386COFF
527 {"bss", s_bss, 0},
528#endif
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
532 {"value", cons, 2},
d182319b 533 {"slong", signed_cons, 4},
29b0f896
AM		 534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 542 {"intel_mnemonic", set_intel_mnemonic, 1},
543 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 544 {"allow_index_reg", set_allow_index_reg, 1},
545 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
07a53e5c 548#else
e3bb37b5 549 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 552#endif
6482c264
NC		 553#ifdef TE_PE
554 {"secrel32", pe_directive_secrel, 0},
555#endif
29b0f896
AM		 556 {0, 0, 0}
557};
558
559/* For interface with expression (). */
560extern char *input_line_pointer;
561
562/* Hash table for instruction mnemonic lookup. */
563static struct hash_control *op_hash;
564
565/* Hash table for register lookup. */
566static struct hash_control *reg_hash;
567\f
252b5132 568void
e3bb37b5 569i386_align_code (fragS *fragP, int count)
252b5132 570{
ce8a8b2f
AM		 571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
252b5132
RH		 574 static const char f32_1[] =
575 {0x90}; /* nop */
576 static const char f32_2[] =
ccc9c027 577 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 578 static const char f32_3[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5[] =
583 {0x90, /* nop */
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8[] =
590 {0x90, /* nop */
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 610 static const char f16_3[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 612 static const char f16_4[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5[] =
615 {0x90, /* nop */
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 626 static const char jump_31[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 634 };
635 static const char *const f16_patt[] = {
76bc74dc 636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 637 };
ccc9c027
L		 638 /* nopl (%[re]ax) */
639 static const char alt_3[] =
640 {0x0f,0x1f,0x00};
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
665 {0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
671 {0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
679 {0x66,
680 0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 data16
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
689 {0x66,
690 0x66,
691 0x66,
692 0x66,
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 /* data16
695 data16
696 data16
697 data16
698 data16
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
701 {0x66,
702 0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax) */
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
727 /* nopl 0L(%[re]ax)
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
736 };
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
741 };
252b5132 742
76bc74dc
L		 743 /* Only align for at least a positive non-zero boundary. */
744 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 745 return;
3e73aa7c 746
ccc9c027
L		 747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
4eed87de 749
76bc74dc
L		 750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 757
76bc74dc
L		 758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
760 be used.
ccc9c027
L		 761
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
764
765 if (flag_code == CODE_16BIT)
766 {
ccc9c027 767 if (count > 8)
33fef721 768 {
76bc74dc
L		 769 memcpy (fragP->fr_literal + fragP->fr_fix,
770 jump_31, count);
771 /* Adjust jump offset. */
772 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 773 }
76bc74dc
L		 774 else
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
252b5132 777 }
33fef721 778 else
ccc9c027
L		 779 {
780 const char *const *patt = NULL;
781
782 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
783 {
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune)
786 {
787 case PROCESSOR_UNKNOWN:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
40fb9820 790 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 791 patt = alt_long_patt;
ccc9c027
L		 792 else
793 patt = f32_patt;
794 break;
ccc9c027
L		 795 case PROCESSOR_PENTIUMPRO:
796 case PROCESSOR_PENTIUM4:
797 case PROCESSOR_NOCONA:
ef05d495 798 case PROCESSOR_CORE:
76bc74dc
L		 799 case PROCESSOR_CORE2:
800 case PROCESSOR_GENERIC64:
801 patt = alt_long_patt;
802 break;
ccc9c027
L		 803 case PROCESSOR_K6:
804 case PROCESSOR_ATHLON:
805 case PROCESSOR_K8:
4eed87de 806 case PROCESSOR_AMDFAM10:
ccc9c027
L		 807 patt = alt_short_patt;
808 break;
76bc74dc 809 case PROCESSOR_I386:
ccc9c027
L		 810 case PROCESSOR_I486:
811 case PROCESSOR_PENTIUM:
812 case PROCESSOR_GENERIC32:
813 patt = f32_patt;
814 break;
4eed87de 815 }
ccc9c027
L		 816 }
817 else
818 {
819 switch (cpu_arch_tune)
820 {
821 case PROCESSOR_UNKNOWN:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
824 abort ();
825 break;
826
76bc74dc 827 case PROCESSOR_I386:
ccc9c027
L		 828 case PROCESSOR_I486:
829 case PROCESSOR_PENTIUM:
ccc9c027
L		 830 case PROCESSOR_K6:
831 case PROCESSOR_ATHLON:
832 case PROCESSOR_K8:
4eed87de 833 case PROCESSOR_AMDFAM10:
ccc9c027
L		 834 case PROCESSOR_GENERIC32:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
836 for Cpu686. */
40fb9820 837 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 838 patt = alt_short_patt;
839 else
840 patt = f32_patt;
841 break;
76bc74dc
L		 842 case PROCESSOR_PENTIUMPRO:
843 case PROCESSOR_PENTIUM4:
844 case PROCESSOR_NOCONA:
845 case PROCESSOR_CORE:
ef05d495 846 case PROCESSOR_CORE2:
40fb9820 847 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 848 patt = alt_long_patt;
849 else
850 patt = f32_patt;
851 break;
852 case PROCESSOR_GENERIC64:
76bc74dc 853 patt = alt_long_patt;
ccc9c027 854 break;
4eed87de 855 }
ccc9c027
L		 856 }
857
76bc74dc
L		 858 if (patt == f32_patt)
859 {
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
862 its offset. */
863 if (count < 15)
864 memcpy (fragP->fr_literal + fragP->fr_fix,
865 patt[count - 1], count);
866 else
867 {
868 memcpy (fragP->fr_literal + fragP->fr_fix,
869 jump_31, count);
870 /* Adjust jump offset. */
871 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
872 }
873 }
874 else
875 {
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
879 int padding = count;
880 while (padding > 15)
881 {
882 padding -= 15;
883 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
884 patt [14], 15);
885 }
886
887 if (padding)
888 memcpy (fragP->fr_literal + fragP->fr_fix,
889 patt [padding - 1], padding);
890 }
ccc9c027 891 }
33fef721 892 fragP->fr_var = count;
252b5132
RH		 893}
894
c6fb90c8
L		 895static INLINE int
896uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 897{
c6fb90c8
L		 898 switch (size)
899 {
900 case 3:
901 if (x[2])
902 return 0;
903 case 2:
904 if (x[1])
905 return 0;
906 case 1:
907 return !x[0];
908 default:
909 abort ();
910 }
40fb9820
L		 911}
912
c6fb90c8
L		 913static INLINE void
914uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 915{
c6fb90c8
L		 916 switch (size)
917 {
918 case 3:
919 x[2] = v;
920 case 2:
921 x[1] = v;
922 case 1:
923 x[0] = v;
924 break;
925 default:
926 abort ();
927 }
928}
40fb9820 929
c6fb90c8
L		 930static INLINE int
931uints_equal (const unsigned int *x, const unsigned int *y,
932 unsigned int size)
933{
934 switch (size)
935 {
936 case 3:
937 if (x[2] != y [2])
938 return 0;
939 case 2:
940 if (x[1] != y [1])
941 return 0;
942 case 1:
943 return x[0] == y [0];
944 break;
945 default:
946 abort ();
947 }
948}
40fb9820 949
c6fb90c8
L		 950#define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952#define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954#define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956#define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
958
959static INLINE int
960cpu_flags_check_cpu64 (i386_cpu_flags f)
961{
962 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
963 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 964}
965
c6fb90c8
L		 966static INLINE i386_cpu_flags
967cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 968{
c6fb90c8
L		 969 switch (ARRAY_SIZE (x.array))
970 {
971 case 3:
972 x.array [2] &= y.array [2];
973 case 2:
974 x.array [1] &= y.array [1];
975 case 1:
976 x.array [0] &= y.array [0];
977 break;
978 default:
979 abort ();
980 }
981 return x;
982}
40fb9820 983
c6fb90c8
L		 984static INLINE i386_cpu_flags
985cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 986{
c6fb90c8 987 switch (ARRAY_SIZE (x.array))
40fb9820 988 {
c6fb90c8
L		 989 case 3:
990 x.array [2] |= y.array [2];
991 case 2:
992 x.array [1] |= y.array [1];
993 case 1:
994 x.array [0] |= y.array [0];
40fb9820
L		 995 break;
996 default:
997 abort ();
998 }
40fb9820
L		 999 return x;
1000}
1001
3629bb00
L		 1002/* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1004
40fb9820
L		 1005static int
1006cpu_flags_match (i386_cpu_flags x)
1007{
3629bb00 1008 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
40fb9820
L		 1009
1010 x.bitfield.cpu64 = 0;
1011 x.bitfield.cpuno64 = 0;
1012
3629bb00
L		 1013 if (UINTS_ALL_ZERO (x))
1014 overlap |= 1;
1015 else
1016 {
1017 i386_cpu_flags cpu = cpu_arch_flags;
1018
1019 cpu.bitfield.cpu64 = 0;
1020 cpu.bitfield.cpuno64 = 0;
1021 cpu = cpu_flags_and (x, cpu);
1022 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1023 }
1024 return overlap;
40fb9820
L		 1025}
1026
c6fb90c8
L		 1027static INLINE i386_operand_type
1028operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1029{
c6fb90c8
L		 1030 switch (ARRAY_SIZE (x.array))
1031 {
1032 case 3:
1033 x.array [2] &= y.array [2];
1034 case 2:
1035 x.array [1] &= y.array [1];
1036 case 1:
1037 x.array [0] &= y.array [0];
1038 break;
1039 default:
1040 abort ();
1041 }
1042 return x;
40fb9820
L		 1043}
1044
c6fb90c8
L		 1045static INLINE i386_operand_type
1046operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1047{
c6fb90c8 1048 switch (ARRAY_SIZE (x.array))
40fb9820 1049 {
c6fb90c8
L		 1050 case 3:
1051 x.array [2] |= y.array [2];
1052 case 2:
1053 x.array [1] |= y.array [1];
1054 case 1:
1055 x.array [0] |= y.array [0];
40fb9820
L		 1056 break;
1057 default:
1058 abort ();
1059 }
c6fb90c8
L		 1060 return x;
1061}
40fb9820 1062
c6fb90c8
L		 1063static INLINE i386_operand_type
1064operand_type_xor (i386_operand_type x, i386_operand_type y)
1065{
1066 switch (ARRAY_SIZE (x.array))
1067 {
1068 case 3:
1069 x.array [2] ^= y.array [2];
1070 case 2:
1071 x.array [1] ^= y.array [1];
1072 case 1:
1073 x.array [0] ^= y.array [0];
1074 break;
1075 default:
1076 abort ();
1077 }
40fb9820
L		 1078 return x;
1079}
1080
1081static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1082static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1083static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1084static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG;
1086static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1087static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1088static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1089static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1090static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1092static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1093static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1094static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1095static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1096static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1097static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1098static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1099static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1100static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1101static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1102
1103enum operand_type
1104{
1105 reg,
40fb9820
L		 1106 imm,
1107 disp,
1108 anymem
1109};
1110
c6fb90c8 1111static INLINE int
40fb9820
L		 1112operand_type_check (i386_operand_type t, enum operand_type c)
1113{
1114 switch (c)
1115 {
1116 case reg:
1117 return (t.bitfield.reg8
1118 || t.bitfield.reg16
1119 || t.bitfield.reg32
1120 || t.bitfield.reg64);
1121
40fb9820
L		 1122 case imm:
1123 return (t.bitfield.imm8
1124 || t.bitfield.imm8s
1125 || t.bitfield.imm16
1126 || t.bitfield.imm32
1127 || t.bitfield.imm32s
1128 || t.bitfield.imm64);
1129
1130 case disp:
1131 return (t.bitfield.disp8
1132 || t.bitfield.disp16
1133 || t.bitfield.disp32
1134 || t.bitfield.disp32s
1135 || t.bitfield.disp64);
1136
1137 case anymem:
1138 return (t.bitfield.disp8
1139 || t.bitfield.disp16
1140 || t.bitfield.disp32
1141 || t.bitfield.disp32s
1142 || t.bitfield.disp64
1143 || t.bitfield.baseindex);
1144
1145 default:
1146 abort ();
1147 }
1148}
1149
c6fb90c8 1150static INLINE int
40fb9820
L		 1151operand_type_match (i386_operand_type overlap,
1152 i386_operand_type given)
1153{
1154 i386_operand_type temp = overlap;
1155
1156 temp.bitfield.jumpabsolute = 0;
c6fb90c8 1157 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1158 return 0;
1159
1160 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1161 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1162}
1163
1164/* If given types r0 and r1 are registers they must be of the same type
1165 unless the expected operand type register overlap is null.
1166 Note that Acc in a template matches every size of reg. */
1167
c6fb90c8 1168static INLINE int
40fb9820
L		 1169operand_type_register_match (i386_operand_type m0,
1170 i386_operand_type g0,
1171 i386_operand_type t0,
1172 i386_operand_type m1,
1173 i386_operand_type g1,
1174 i386_operand_type t1)
1175{
1176 if (!operand_type_check (g0, reg))
1177 return 1;
1178
1179 if (!operand_type_check (g1, reg))
1180 return 1;
1181
1182 if (g0.bitfield.reg8 == g1.bitfield.reg8
1183 && g0.bitfield.reg16 == g1.bitfield.reg16
1184 && g0.bitfield.reg32 == g1.bitfield.reg32
1185 && g0.bitfield.reg64 == g1.bitfield.reg64)
1186 return 1;
1187
1188 if (m0.bitfield.acc)
1189 {
1190 t0.bitfield.reg8 = 1;
1191 t0.bitfield.reg16 = 1;
1192 t0.bitfield.reg32 = 1;
1193 t0.bitfield.reg64 = 1;
1194 }
1195
1196 if (m1.bitfield.acc)
1197 {
1198 t1.bitfield.reg8 = 1;
1199 t1.bitfield.reg16 = 1;
1200 t1.bitfield.reg32 = 1;
1201 t1.bitfield.reg64 = 1;
1202 }
1203
1204 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1205 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1206 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1207 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1208}
1209
252b5132 1210static INLINE unsigned int
40fb9820 1211mode_from_disp_size (i386_operand_type t)
252b5132 1212{
40fb9820
L		 1213 if (t.bitfield.disp8)
1214 return 1;
1215 else if (t.bitfield.disp16
1216 || t.bitfield.disp32
1217 || t.bitfield.disp32s)
1218 return 2;
1219 else
1220 return 0;
252b5132
RH		 1221}
1222
1223static INLINE int
e3bb37b5 1224fits_in_signed_byte (offsetT num)
252b5132
RH		 1225{
1226 return (num >= -128) && (num <= 127);
47926f60 1227}
252b5132
RH		 1228
1229static INLINE int
e3bb37b5 1230fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1231{
1232 return (num & 0xff) == num;
47926f60 1233}
252b5132
RH		 1234
1235static INLINE int
e3bb37b5 1236fits_in_unsigned_word (offsetT num)
252b5132
RH		 1237{
1238 return (num & 0xffff) == num;
47926f60 1239}
252b5132
RH		 1240
1241static INLINE int
e3bb37b5 1242fits_in_signed_word (offsetT num)
252b5132
RH		 1243{
1244 return (-32768 <= num) && (num <= 32767);
47926f60 1245}
2a962e6d 1246
3e73aa7c 1247static INLINE int
e3bb37b5 1248fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1249{
1250#ifndef BFD64
1251 return 1;
1252#else
1253 return (!(((offsetT) -1 << 31) & num)
1254 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1255#endif
1256} /* fits_in_signed_long() */
2a962e6d 1257
3e73aa7c 1258static INLINE int
e3bb37b5 1259fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1260{
1261#ifndef BFD64
1262 return 1;
1263#else
1264 return (num & (((offsetT) 2 << 31) - 1)) == num;
1265#endif
1266} /* fits_in_unsigned_long() */
252b5132 1267
40fb9820 1268static i386_operand_type
e3bb37b5 1269smallest_imm_type (offsetT num)
252b5132 1270{
40fb9820
L		 1271 i386_operand_type t;
1272
c6fb90c8 1273 UINTS_CLEAR (t);
40fb9820
L		 1274 t.bitfield.imm64 = 1;
1275
1276 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1277 {
1278 /* This code is disabled on the 486 because all the Imm1 forms
1279 in the opcode table are slower on the i486. They're the
1280 versions with the implicitly specified single-position
1281 displacement, which has another syntax if you really want to
1282 use that form. */
40fb9820
L		 1283 t.bitfield.imm1 = 1;
1284 t.bitfield.imm8 = 1;
1285 t.bitfield.imm8s = 1;
1286 t.bitfield.imm16 = 1;
1287 t.bitfield.imm32 = 1;
1288 t.bitfield.imm32s = 1;
1289 }
1290 else if (fits_in_signed_byte (num))
1291 {
1292 t.bitfield.imm8 = 1;
1293 t.bitfield.imm8s = 1;
1294 t.bitfield.imm16 = 1;
1295 t.bitfield.imm32 = 1;
1296 t.bitfield.imm32s = 1;
1297 }
1298 else if (fits_in_unsigned_byte (num))
1299 {
1300 t.bitfield.imm8 = 1;
1301 t.bitfield.imm16 = 1;
1302 t.bitfield.imm32 = 1;
1303 t.bitfield.imm32s = 1;
1304 }
1305 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1306 {
1307 t.bitfield.imm16 = 1;
1308 t.bitfield.imm32 = 1;
1309 t.bitfield.imm32s = 1;
1310 }
1311 else if (fits_in_signed_long (num))
1312 {
1313 t.bitfield.imm32 = 1;
1314 t.bitfield.imm32s = 1;
1315 }
1316 else if (fits_in_unsigned_long (num))
1317 t.bitfield.imm32 = 1;
1318
1319 return t;
47926f60 1320}
252b5132 1321
847f7ad4 1322static offsetT
e3bb37b5 1323offset_in_range (offsetT val, int size)
847f7ad4 1324{
508866be 1325 addressT mask;
ba2adb93 1326
847f7ad4
AM		 1327 switch (size)
1328 {
508866be
L		 1329 case 1: mask = ((addressT) 1 << 8) - 1; break;
1330 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1331 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1332#ifdef BFD64
1333 case 8: mask = ((addressT) 2 << 63) - 1; break;
1334#endif
47926f60 1335 default: abort ();
847f7ad4
AM		 1336 }
1337
ba2adb93 1338 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1339 if (!use_rela_relocations)
1340 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1341 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1342
47926f60 1343 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1344 {
1345 char buf1[40], buf2[40];
1346
1347 sprint_value (buf1, val);
1348 sprint_value (buf2, val & mask);
1349 as_warn (_("%s shortened to %s"), buf1, buf2);
1350 }
1351 return val & mask;
1352}
1353
252b5132
RH		 1354/* Returns 0 if attempting to add a prefix where one from the same
1355 class already exists, 1 if non rep/repne added, 2 if rep/repne
1356 added. */
1357static int
e3bb37b5 1358add_prefix (unsigned int prefix)
252b5132
RH		 1359{
1360 int ret = 1;
b1905489 1361 unsigned int q;
252b5132 1362
29b0f896
AM		 1363 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1364 && flag_code == CODE_64BIT)
b1905489 1365 {
161a04f6
L		 1366 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1367 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1368 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1369 ret = 0;
1370 q = REX_PREFIX;
1371 }
3e73aa7c 1372 else
b1905489
JB		 1373 {
1374 switch (prefix)
1375 {
1376 default:
1377 abort ();
1378
1379 case CS_PREFIX_OPCODE:
1380 case DS_PREFIX_OPCODE:
1381 case ES_PREFIX_OPCODE:
1382 case FS_PREFIX_OPCODE:
1383 case GS_PREFIX_OPCODE:
1384 case SS_PREFIX_OPCODE:
1385 q = SEG_PREFIX;
1386 break;
1387
1388 case REPNE_PREFIX_OPCODE:
1389 case REPE_PREFIX_OPCODE:
1390 ret = 2;
1391 /* fall thru */
1392 case LOCK_PREFIX_OPCODE:
1393 q = LOCKREP_PREFIX;
1394 break;
1395
1396 case FWAIT_OPCODE:
1397 q = WAIT_PREFIX;
1398 break;
1399
1400 case ADDR_PREFIX_OPCODE:
1401 q = ADDR_PREFIX;
1402 break;
1403
1404 case DATA_PREFIX_OPCODE:
1405 q = DATA_PREFIX;
1406 break;
1407 }
1408 if (i.prefix[q] != 0)
1409 ret = 0;
1410 }
252b5132 1411
b1905489 1412 if (ret)
252b5132 1413 {
b1905489
JB		 1414 if (!i.prefix[q])
1415 ++i.prefixes;
1416 i.prefix[q] |= prefix;
252b5132 1417 }
b1905489
JB		 1418 else
1419 as_bad (_("same type of prefix used twice"));
252b5132 1420
252b5132
RH		 1421 return ret;
1422}
1423
1424static void
e3bb37b5 1425set_code_flag (int value)
eecb386c 1426{
3e73aa7c 1427 flag_code = value;
40fb9820
L		 1428 if (flag_code == CODE_64BIT)
1429 {
1430 cpu_arch_flags.bitfield.cpu64 = 1;
1431 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1432 }
1433 else
1434 {
1435 cpu_arch_flags.bitfield.cpu64 = 0;
1436 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1437 }
1438 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1439 {
1440 as_bad (_("64bit mode not supported on this CPU."));
1441 }
40fb9820 1442 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1443 {
1444 as_bad (_("32bit mode not supported on this CPU."));
1445 }
eecb386c
AM		 1446 stackop_size = '\0';
1447}
1448
1449static void
e3bb37b5 1450set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1451{
3e73aa7c 1452 flag_code = new_code_flag;
40fb9820
L		 1453 if (flag_code != CODE_16BIT)
1454 abort ();
1455 cpu_arch_flags.bitfield.cpu64 = 0;
1456 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1457 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1458}
1459
1460static void
e3bb37b5 1461set_intel_syntax (int syntax_flag)
252b5132
RH		 1462{
1463 /* Find out if register prefixing is specified. */
1464 int ask_naked_reg = 0;
1465
1466 SKIP_WHITESPACE ();
29b0f896 1467 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1468 {
1469 char *string = input_line_pointer;
1470 int e = get_symbol_end ();
1471
47926f60 1472 if (strcmp (string, "prefix") == 0)
252b5132 1473 ask_naked_reg = 1;
47926f60 1474 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1475 ask_naked_reg = -1;
1476 else
d0b47220 1477 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1478 *input_line_pointer = e;
1479 }
1480 demand_empty_rest_of_line ();
c3332e24 1481
252b5132
RH		 1482 intel_syntax = syntax_flag;
1483
1484 if (ask_naked_reg == 0)
f86103b7
AM		 1485 allow_naked_reg = (intel_syntax
1486 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1487 else
1488 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1489
e4a3b5a4 1490 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1491 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1492 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1493}
1494
1efbbeb4
L		 1495static void
1496set_intel_mnemonic (int mnemonic_flag)
1497{
e1d4d893 1498 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1499}
1500
db51cc60
L		 1501static void
1502set_allow_index_reg (int flag)
1503{
1504 allow_index_reg = flag;
1505}
1506
e413e4e9 1507static void
e3bb37b5 1508set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1509{
47926f60 1510 SKIP_WHITESPACE ();
e413e4e9 1511
29b0f896 1512 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1513 {
1514 char *string = input_line_pointer;
1515 int e = get_symbol_end ();
9103f4f4 1516 unsigned int i;
40fb9820 1517 i386_cpu_flags flags;
e413e4e9 1518
9103f4f4 1519 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1520 {
1521 if (strcmp (string, cpu_arch[i].name) == 0)
1522 {
5c6af06e
JB		 1523 if (*string != '.')
1524 {
1525 cpu_arch_name = cpu_arch[i].name;
1526 cpu_sub_arch_name = NULL;
40fb9820
L		 1527 cpu_arch_flags = cpu_arch[i].flags;
1528 if (flag_code == CODE_64BIT)
1529 {
1530 cpu_arch_flags.bitfield.cpu64 = 1;
1531 cpu_arch_flags.bitfield.cpuno64 = 0;
1532 }
1533 else
1534 {
1535 cpu_arch_flags.bitfield.cpu64 = 0;
1536 cpu_arch_flags.bitfield.cpuno64 = 1;
1537 }
ccc9c027 1538 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1539 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1540 if (!cpu_arch_tune_set)
1541 {
1542 cpu_arch_tune = cpu_arch_isa;
1543 cpu_arch_tune_flags = cpu_arch_isa_flags;
1544 }
5c6af06e
JB		 1545 break;
1546 }
40fb9820 1547
c6fb90c8
L		 1548 flags = cpu_flags_or (cpu_arch_flags,
1549 cpu_arch[i].flags);
1550 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1551 {
1552 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820 1553 cpu_arch_flags = flags;
5c6af06e
JB		 1554 }
1555 *input_line_pointer = e;
1556 demand_empty_rest_of_line ();
1557 return;
e413e4e9
AM		 1558 }
1559 }
9103f4f4 1560 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1561 as_bad (_("no such architecture: `%s'"), string);
1562
1563 *input_line_pointer = e;
1564 }
1565 else
1566 as_bad (_("missing cpu architecture"));
1567
fddf5b5b
AM		 1568 no_cond_jump_promotion = 0;
1569 if (*input_line_pointer == ','
29b0f896 1570 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1571 {
1572 char *string = ++input_line_pointer;
1573 int e = get_symbol_end ();
1574
1575 if (strcmp (string, "nojumps") == 0)
1576 no_cond_jump_promotion = 1;
1577 else if (strcmp (string, "jumps") == 0)
1578 ;
1579 else
1580 as_bad (_("no such architecture modifier: `%s'"), string);
1581
1582 *input_line_pointer = e;
1583 }
1584
e413e4e9
AM		 1585 demand_empty_rest_of_line ();
1586}
1587
b9d79e03
JH		 1588unsigned long
1589i386_mach ()
1590{
1591 if (!strcmp (default_arch, "x86_64"))
1592 return bfd_mach_x86_64;
1593 else if (!strcmp (default_arch, "i386"))
1594 return bfd_mach_i386_i386;
1595 else
1596 as_fatal (_("Unknown architecture"));
1597}
b9d79e03 1598\f
252b5132
RH		 1599void
1600md_begin ()
1601{
1602 const char *hash_err;
1603
47926f60 1604 /* Initialize op_hash hash table. */
252b5132
RH		 1605 op_hash = hash_new ();
1606
1607 {
29b0f896
AM		 1608 const template *optab;
1609 templates *core_optab;
252b5132 1610
47926f60
KH		 1611 /* Setup for loop. */
1612 optab = i386_optab;
252b5132
RH		 1613 core_optab = (templates *) xmalloc (sizeof (templates));
1614 core_optab->start = optab;
1615
1616 while (1)
1617 {
1618 ++optab;
1619 if (optab->name == NULL
1620 || strcmp (optab->name, (optab - 1)->name) != 0)
1621 {
1622 /* different name --> ship out current template list;
47926f60 1623 add to hash table; & begin anew. */
252b5132
RH		 1624 core_optab->end = optab;
1625 hash_err = hash_insert (op_hash,
1626 (optab - 1)->name,
1627 (PTR) core_optab);
1628 if (hash_err)
1629 {
252b5132
RH		 1630 as_fatal (_("Internal Error: Can't hash %s: %s"),
1631 (optab - 1)->name,
1632 hash_err);
1633 }
1634 if (optab->name == NULL)
1635 break;
1636 core_optab = (templates *) xmalloc (sizeof (templates));
1637 core_optab->start = optab;
1638 }
1639 }
1640 }
1641
47926f60 1642 /* Initialize reg_hash hash table. */
252b5132
RH		 1643 reg_hash = hash_new ();
1644 {
29b0f896 1645 const reg_entry *regtab;
c3fe08fa 1646 unsigned int regtab_size = i386_regtab_size;
252b5132 1647
c3fe08fa 1648 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1649 {
1650 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1651 if (hash_err)
3e73aa7c
JH		 1652 as_fatal (_("Internal Error: Can't hash %s: %s"),
1653 regtab->reg_name,
1654 hash_err);
252b5132
RH		 1655 }
1656 }
1657
47926f60 1658 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1659 {
29b0f896
AM		 1660 int c;
1661 char *p;
252b5132
RH		 1662
1663 for (c = 0; c < 256; c++)
1664 {
3882b010 1665 if (ISDIGIT (c))
252b5132
RH		 1666 {
1667 digit_chars[c] = c;
1668 mnemonic_chars[c] = c;
1669 register_chars[c] = c;
1670 operand_chars[c] = c;
1671 }
3882b010 1672 else if (ISLOWER (c))
252b5132
RH		 1673 {
1674 mnemonic_chars[c] = c;
1675 register_chars[c] = c;
1676 operand_chars[c] = c;
1677 }
3882b010 1678 else if (ISUPPER (c))
252b5132 1679 {
3882b010 1680 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1681 register_chars[c] = mnemonic_chars[c];
1682 operand_chars[c] = c;
1683 }
1684
3882b010 1685 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1686 identifier_chars[c] = c;
1687 else if (c >= 128)
1688 {
1689 identifier_chars[c] = c;
1690 operand_chars[c] = c;
1691 }
1692 }
1693
1694#ifdef LEX_AT
1695 identifier_chars['@'] = '@';
32137342
NC		 1696#endif
1697#ifdef LEX_QM
1698 identifier_chars['?'] = '?';
1699 operand_chars['?'] = '?';
252b5132 1700#endif
252b5132 1701 digit_chars['-'] = '-';
791fe849 1702 mnemonic_chars['-'] = '-';
0003779b 1703 mnemonic_chars['.'] = '.';
252b5132
RH		 1704 identifier_chars['_'] = '_';
1705 identifier_chars['.'] = '.';
1706
1707 for (p = operand_special_chars; *p != '\0'; p++)
1708 operand_chars[(unsigned char) *p] = *p;
1709 }
1710
1711#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1712 if (IS_ELF)
252b5132
RH		 1713 {
1714 record_alignment (text_section, 2);
1715 record_alignment (data_section, 2);
1716 record_alignment (bss_section, 2);
1717 }
1718#endif
a4447b93
RH		 1719
1720 if (flag_code == CODE_64BIT)
1721 {
1722 x86_dwarf2_return_column = 16;
1723 x86_cie_data_alignment = -8;
1724 }
1725 else
1726 {
1727 x86_dwarf2_return_column = 8;
1728 x86_cie_data_alignment = -4;
1729 }
252b5132
RH		 1730}
1731
1732void
e3bb37b5 1733i386_print_statistics (FILE *file)
252b5132
RH		 1734{
1735 hash_print_statistics (file, "i386 opcode", op_hash);
1736 hash_print_statistics (file, "i386 register", reg_hash);
1737}
1738\f
252b5132
RH		 1739#ifdef DEBUG386
1740
ce8a8b2f 1741/* Debugging routines for md_assemble. */
e3bb37b5 1742static void pte (template *);
40fb9820 1743static void pt (i386_operand_type);
e3bb37b5
L		 1744static void pe (expressionS *);
1745static void ps (symbolS *);
252b5132
RH		 1746
1747static void
e3bb37b5 1748pi (char *line, i386_insn *x)
252b5132 1749{
09f131f2 1750 unsigned int i;
252b5132
RH		 1751
1752 fprintf (stdout, "%s: template ", line);
1753 pte (&x->tm);
09f131f2
JH		 1754 fprintf (stdout, " address: base %s index %s scale %x\n",
1755 x->base_reg ? x->base_reg->reg_name : "none",
1756 x->index_reg ? x->index_reg->reg_name : "none",
1757 x->log2_scale_factor);
1758 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1759 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1760 fprintf (stdout, " sib: base %x index %x scale %x\n",
1761 x->sib.base, x->sib.index, x->sib.scale);
1762 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1763 (x->rex & REX_W) != 0,
1764 (x->rex & REX_R) != 0,
1765 (x->rex & REX_X) != 0,
1766 (x->rex & REX_B) != 0);
85f10a01
MM		 1767 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1768 x->drex.reg, x->drex.rex);
252b5132
RH		 1769 for (i = 0; i < x->operands; i++)
1770 {
1771 fprintf (stdout, " #%d: ", i + 1);
1772 pt (x->types[i]);
1773 fprintf (stdout, "\n");
40fb9820
L		 1774 if (x->types[i].bitfield.reg8
1775 || x->types[i].bitfield.reg16
1776 || x->types[i].bitfield.reg32
1777 || x->types[i].bitfield.reg64
1778 || x->types[i].bitfield.regmmx
1779 || x->types[i].bitfield.regxmm
1780 || x->types[i].bitfield.sreg2
1781 || x->types[i].bitfield.sreg3
1782 || x->types[i].bitfield.control
1783 || x->types[i].bitfield.debug
1784 || x->types[i].bitfield.test)
520dc8e8 1785 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1786 if (operand_type_check (x->types[i], imm))
520dc8e8 1787 pe (x->op[i].imms);
40fb9820 1788 if (operand_type_check (x->types[i], disp))
520dc8e8 1789 pe (x->op[i].disps);
252b5132
RH		 1790 }
1791}
1792
1793static void
e3bb37b5 1794pte (template *t)
252b5132 1795{
09f131f2 1796 unsigned int i;
252b5132 1797 fprintf (stdout, " %d operands ", t->operands);
47926f60 1798 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1799 if (t->extension_opcode != None)
1800 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1801 if (t->opcode_modifier.d)
252b5132 1802 fprintf (stdout, "D");
40fb9820 1803 if (t->opcode_modifier.w)
252b5132
RH		 1804 fprintf (stdout, "W");
1805 fprintf (stdout, "\n");
1806 for (i = 0; i < t->operands; i++)
1807 {
1808 fprintf (stdout, " #%d type ", i + 1);
1809 pt (t->operand_types[i]);
1810 fprintf (stdout, "\n");
1811 }
1812}
1813
1814static void
e3bb37b5 1815pe (expressionS *e)
252b5132 1816{
24eab124 1817 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1818 fprintf (stdout, " add_number %ld (%lx)\n",
1819 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1820 if (e->X_add_symbol)
1821 {
1822 fprintf (stdout, " add_symbol ");
1823 ps (e->X_add_symbol);
1824 fprintf (stdout, "\n");
1825 }
1826 if (e->X_op_symbol)
1827 {
1828 fprintf (stdout, " op_symbol ");
1829 ps (e->X_op_symbol);
1830 fprintf (stdout, "\n");
1831 }
1832}
1833
1834static void
e3bb37b5 1835ps (symbolS *s)
252b5132
RH		 1836{
1837 fprintf (stdout, "%s type %s%s",
1838 S_GET_NAME (s),
1839 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1840 segment_name (S_GET_SEGMENT (s)));
1841}
1842
7b81dfbb 1843static struct type_name
252b5132 1844 {
40fb9820
L		 1845 i386_operand_type mask;
1846 const char *name;
252b5132 1847 }
7b81dfbb 1848const type_names[] =
252b5132 1849{
40fb9820
L		 1850 { OPERAND_TYPE_REG8, "r8" },
1851 { OPERAND_TYPE_REG16, "r16" },
1852 { OPERAND_TYPE_REG32, "r32" },
1853 { OPERAND_TYPE_REG64, "r64" },
1854 { OPERAND_TYPE_IMM8, "i8" },
1855 { OPERAND_TYPE_IMM8, "i8s" },
1856 { OPERAND_TYPE_IMM16, "i16" },
1857 { OPERAND_TYPE_IMM32, "i32" },
1858 { OPERAND_TYPE_IMM32S, "i32s" },
1859 { OPERAND_TYPE_IMM64, "i64" },
1860 { OPERAND_TYPE_IMM1, "i1" },
1861 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1862 { OPERAND_TYPE_DISP8, "d8" },
1863 { OPERAND_TYPE_DISP16, "d16" },
1864 { OPERAND_TYPE_DISP32, "d32" },
1865 { OPERAND_TYPE_DISP32S, "d32s" },
1866 { OPERAND_TYPE_DISP64, "d64" },
1867 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1868 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1869 { OPERAND_TYPE_CONTROL, "control reg" },
1870 { OPERAND_TYPE_TEST, "test reg" },
1871 { OPERAND_TYPE_DEBUG, "debug reg" },
1872 { OPERAND_TYPE_FLOATREG, "FReg" },
1873 { OPERAND_TYPE_FLOATACC, "FAcc" },
1874 { OPERAND_TYPE_SREG2, "SReg2" },
1875 { OPERAND_TYPE_SREG3, "SReg3" },
1876 { OPERAND_TYPE_ACC, "Acc" },
1877 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1878 { OPERAND_TYPE_REGMMX, "rMMX" },
1879 { OPERAND_TYPE_REGXMM, "rXMM" },
1880 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1881};
1882
1883static void
40fb9820 1884pt (i386_operand_type t)
252b5132 1885{
40fb9820 1886 unsigned int j;
c6fb90c8 1887 i386_operand_type a;
252b5132 1888
40fb9820 1889 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1890 {
1891 a = operand_type_and (t, type_names[j].mask);
1892 if (!UINTS_ALL_ZERO (a))
1893 fprintf (stdout, "%s, ", type_names[j].name);
1894 }
252b5132
RH		 1895 fflush (stdout);
1896}
1897
1898#endif /* DEBUG386 */
1899\f
252b5132 1900static bfd_reloc_code_real_type
3956db08 1901reloc (unsigned int size,
64e74474
AM		 1902 int pcrel,
1903 int sign,
1904 bfd_reloc_code_real_type other)
252b5132 1905{
47926f60 1906 if (other != NO_RELOC)
3956db08
JB		 1907 {
1908 reloc_howto_type *reloc;
1909
1910 if (size == 8)
1911 switch (other)
1912 {
64e74474
AM		 1913 case BFD_RELOC_X86_64_GOT32:
1914 return BFD_RELOC_X86_64_GOT64;
1915 break;
1916 case BFD_RELOC_X86_64_PLTOFF64:
1917 return BFD_RELOC_X86_64_PLTOFF64;
1918 break;
1919 case BFD_RELOC_X86_64_GOTPC32:
1920 other = BFD_RELOC_X86_64_GOTPC64;
1921 break;
1922 case BFD_RELOC_X86_64_GOTPCREL:
1923 other = BFD_RELOC_X86_64_GOTPCREL64;
1924 break;
1925 case BFD_RELOC_X86_64_TPOFF32:
1926 other = BFD_RELOC_X86_64_TPOFF64;
1927 break;
1928 case BFD_RELOC_X86_64_DTPOFF32:
1929 other = BFD_RELOC_X86_64_DTPOFF64;
1930 break;
1931 default:
1932 break;
3956db08 1933 }
e05278af
JB		 1934
1935 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1936 if (size == 4 && flag_code != CODE_64BIT)
1937 sign = -1;
1938
3956db08
JB		 1939 reloc = bfd_reloc_type_lookup (stdoutput, other);
1940 if (!reloc)
1941 as_bad (_("unknown relocation (%u)"), other);
1942 else if (size != bfd_get_reloc_size (reloc))
1943 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1944 bfd_get_reloc_size (reloc),
1945 size);
1946 else if (pcrel && !reloc->pc_relative)
1947 as_bad (_("non-pc-relative relocation for pc-relative field"));
1948 else if ((reloc->complain_on_overflow == complain_overflow_signed
1949 && !sign)
1950 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1951 && sign > 0))
3956db08
JB		 1952 as_bad (_("relocated field and relocation type differ in signedness"));
1953 else
1954 return other;
1955 return NO_RELOC;
1956 }
252b5132
RH		 1957
1958 if (pcrel)
1959 {
3e73aa7c 1960 if (!sign)
3956db08 1961 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1962 switch (size)
1963 {
1964 case 1: return BFD_RELOC_8_PCREL;
1965 case 2: return BFD_RELOC_16_PCREL;
1966 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1967 case 8: return BFD_RELOC_64_PCREL;
252b5132 1968 }
3956db08 1969 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1970 }
1971 else
1972 {
3956db08 1973 if (sign > 0)
e5cb08ac 1974 switch (size)
3e73aa7c
JH		 1975 {
1976 case 4: return BFD_RELOC_X86_64_32S;
1977 }
1978 else
1979 switch (size)
1980 {
1981 case 1: return BFD_RELOC_8;
1982 case 2: return BFD_RELOC_16;
1983 case 4: return BFD_RELOC_32;
1984 case 8: return BFD_RELOC_64;
1985 }
3956db08
JB		 1986 as_bad (_("cannot do %s %u byte relocation"),
1987 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1988 }
1989
bfb32b52 1990 abort ();
252b5132
RH		 1991 return BFD_RELOC_NONE;
1992}
1993
47926f60
KH		 1994/* Here we decide which fixups can be adjusted to make them relative to
1995 the beginning of the section instead of the symbol. Basically we need
1996 to make sure that the dynamic relocations are done correctly, so in
1997 some cases we force the original symbol to be used. */
1998
252b5132 1999int
e3bb37b5 2000tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2001{
6d249963 2002#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2003 if (!IS_ELF)
31312f95
AM		 2004 return 1;
2005
a161fe53
AM		 2006 /* Don't adjust pc-relative references to merge sections in 64-bit
2007 mode. */
2008 if (use_rela_relocations
2009 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2010 && fixP->fx_pcrel)
252b5132 2011 return 0;
31312f95 2012
8d01d9a9
AJ		 2013 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2014 and changed later by validate_fix. */
2015 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2016 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2017 return 0;
2018
ce8a8b2f 2019 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2020 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2021 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2022 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2023 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2024 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2025 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2026 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2027 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2028 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2029 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2030 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2031 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2032 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2033 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2034 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2035 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2036 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2037 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2038 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2039 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2040 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2041 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2042 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2043 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2045 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2046 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2047 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2048 return 0;
31312f95 2049#endif
252b5132
RH		 2050 return 1;
2051}
252b5132 2052
b4cac588 2053static int
e3bb37b5 2054intel_float_operand (const char *mnemonic)
252b5132 2055{
9306ca4a
JB		 2056 /* Note that the value returned is meaningful only for opcodes with (memory)
2057 operands, hence the code here is free to improperly handle opcodes that
2058 have no operands (for better performance and smaller code). */
2059
2060 if (mnemonic[0] != 'f')
2061 return 0; /* non-math */
2062
2063 switch (mnemonic[1])
2064 {
2065 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2066 the fs segment override prefix not currently handled because no
2067 call path can make opcodes without operands get here */
2068 case 'i':
2069 return 2 /* integer op */;
2070 case 'l':
2071 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2072 return 3; /* fldcw/fldenv */
2073 break;
2074 case 'n':
2075 if (mnemonic[2] != 'o' /* fnop */)
2076 return 3; /* non-waiting control op */
2077 break;
2078 case 'r':
2079 if (mnemonic[2] == 's')
2080 return 3; /* frstor/frstpm */
2081 break;
2082 case 's':
2083 if (mnemonic[2] == 'a')
2084 return 3; /* fsave */
2085 if (mnemonic[2] == 't')
2086 {
2087 switch (mnemonic[3])
2088 {
2089 case 'c': /* fstcw */
2090 case 'd': /* fstdw */
2091 case 'e': /* fstenv */
2092 case 's': /* fsts[gw] */
2093 return 3;
2094 }
2095 }
2096 break;
2097 case 'x':
2098 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2099 return 0; /* fxsave/fxrstor are not really math ops */
2100 break;
2101 }
252b5132 2102
9306ca4a 2103 return 1;
252b5132
RH		 2104}
2105
2106/* This is the guts of the machine-dependent assembler. LINE points to a
2107 machine dependent instruction. This function is supposed to emit
2108 the frags/bytes it assembles to. */
2109
2110void
2111md_assemble (line)
2112 char *line;
2113{
40fb9820 2114 unsigned int j;
252b5132
RH		 2115 char mnemonic[MAX_MNEM_SIZE];
2116
47926f60 2117 /* Initialize globals. */
252b5132
RH		 2118 memset (&i, '\0', sizeof (i));
2119 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2120 i.reloc[j] = NO_RELOC;
252b5132
RH		 2121 memset (disp_expressions, '\0', sizeof (disp_expressions));
2122 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2123 save_stack_p = save_stack;
252b5132
RH		 2124
2125 /* First parse an instruction mnemonic & call i386_operand for the operands.
2126 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2127 start of a (possibly prefixed) mnemonic. */
252b5132 2128
29b0f896
AM		 2129 line = parse_insn (line, mnemonic);
2130 if (line == NULL)
2131 return;
252b5132 2132
29b0f896
AM		 2133 line = parse_operands (line, mnemonic);
2134 if (line == NULL)
2135 return;
252b5132 2136
29b0f896
AM		 2137 /* Now we've parsed the mnemonic into a set of templates, and have the
2138 operands at hand. */
2139
2140 /* All intel opcodes have reversed operands except for "bound" and
2141 "enter". We also don't reverse intersegment "jmp" and "call"
2142 instructions with 2 immediate operands so that the immediate segment
050dfa73 2143 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2144 if (intel_syntax
2145 && i.operands > 1
29b0f896 2146 && (strcmp (mnemonic, "bound") != 0)
30123838 2147 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2148 && !(operand_type_check (i.types[0], imm)
2149 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2150 swap_operands ();
2151
ec56d5c0
JB		 2152 /* The order of the immediates should be reversed
2153 for 2 immediates extrq and insertq instructions */
2154 if (i.imm_operands == 2
2155 && (strcmp (mnemonic, "extrq") == 0
2156 || strcmp (mnemonic, "insertq") == 0))
2157 swap_2_operands (0, 1);
2158
29b0f896
AM		 2159 if (i.imm_operands)
2160 optimize_imm ();
2161
b300c311
L		 2162 /* Don't optimize displacement for movabs since it only takes 64bit
2163 displacement. */
2164 if (i.disp_operands
2165 && (flag_code != CODE_64BIT
2166 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2167 optimize_disp ();
2168
2169 /* Next, we find a template that matches the given insn,
2170 making sure the overlap of the given operands types is consistent
2171 with the template operand types. */
252b5132 2172
29b0f896
AM		 2173 if (!match_template ())
2174 return;
252b5132 2175
cd61ebfe
AM		 2176 if (intel_syntax)
2177 {
cd61ebfe
AM		 2178 /* Zap movzx and movsx suffix. The suffix may have been set from
2179 "word ptr" or "byte ptr" on the source operand, but we'll use
2180 the suffix later to choose the destination register. */
2181 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2182 {
2183 if (i.reg_operands < 2
2184 && !i.suffix
40fb9820
L		 2185 && (!i.tm.opcode_modifier.no_bsuf
2186 || !i.tm.opcode_modifier.no_wsuf
2187 || !i.tm.opcode_modifier.no_lsuf
2188 || !i.tm.opcode_modifier.no_ssuf
7ce189b3 2189 || !i.tm.opcode_modifier.no_ldsuf
40fb9820 2190 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2191 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2192
2193 i.suffix = 0;
2194 }
cd61ebfe 2195 }
24eab124 2196
40fb9820 2197 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2198 if (!add_prefix (FWAIT_OPCODE))
2199 return;
252b5132 2200
29b0f896 2201 /* Check string instruction segment overrides. */
40fb9820 2202 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2203 {
2204 if (!check_string ())
5dd0794d 2205 return;
29b0f896 2206 }
5dd0794d 2207
29b0f896
AM		 2208 if (!process_suffix ())
2209 return;
e413e4e9 2210
29b0f896
AM		 2211 /* Make still unresolved immediate matches conform to size of immediate
2212 given in i.suffix. */
2213 if (!finalize_imm ())
2214 return;
252b5132 2215
40fb9820 2216 if (i.types[0].bitfield.imm1)
29b0f896 2217 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2218
40fb9820 2219 for (j = 0; j < 3; j++)
c6fb90c8
L		 2220 if (i.types[j].bitfield.inoutportreg
2221 || i.types[j].bitfield.shiftcount
2222 || i.types[j].bitfield.acc
2223 || i.types[j].bitfield.floatacc)
40fb9820
L		 2224 i.reg_operands--;
2225
2226 if (i.tm.opcode_modifier.immext)
29b0f896 2227 {
02fc3089
L		 2228 expressionS *exp;
2229
40fb9820 2230 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2231 {
b7d9ef37 2232 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2233 operands with an opcode suffix which is coded in the same
2234 place as an 8-bit immediate field would be. Here we check
2235 those operands and remove them afterwards. */
2236 unsigned int x;
2237
a4622f40 2238 for (x = 0; x < i.operands; x++)
ca164297 2239 if (i.op[x].regs->reg_num != x)
a540244d
L		 2240 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2241 register_prefix,
2242 i.op[x].regs->reg_name,
2243 x + 1,
2244 i.tm.name);
ca164297
L		 2245 i.operands = 0;
2246 }
2247
29b0f896
AM		 2248 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2249 opcode suffix which is coded in the same place as an 8-bit
2250 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2251 operand from the opcode suffix stored in tm.extension_opcode.
2252 SSE5 also uses this encoding, for some of its 3 argument
2253 instructions. */
252b5132 2254
85f10a01
MM		 2255 assert (i.imm_operands == 0
2256 && (i.operands <= 2
2257 || (i.tm.cpu_flags.bitfield.cpusse5
2258 && i.operands <= 3)));
252b5132 2259
29b0f896
AM		 2260 exp = &im_expressions[i.imm_operands++];
2261 i.op[i.operands].imms = exp;
c6fb90c8 2262 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2263 i.types[i.operands].bitfield.imm8 = 1;
2264 i.operands++;
29b0f896
AM		 2265 exp->X_op = O_constant;
2266 exp->X_add_number = i.tm.extension_opcode;
2267 i.tm.extension_opcode = None;
2268 }
252b5132 2269
29b0f896
AM		 2270 /* For insns with operands there are more diddles to do to the opcode. */
2271 if (i.operands)
2272 {
2273 if (!process_operands ())
2274 return;
2275 }
40fb9820 2276 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2277 {
2278 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2279 as_warn (_("translating to `%sp'"), i.tm.name);
2280 }
252b5132 2281
29b0f896
AM		 2282 /* Handle conversion of 'int $3' --> special int3 insn. */
2283 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2284 {
2285 i.tm.base_opcode = INT3_OPCODE;
2286 i.imm_operands = 0;
2287 }
252b5132 2288
40fb9820
L		 2289 if ((i.tm.opcode_modifier.jump
2290 || i.tm.opcode_modifier.jumpbyte
2291 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2292 && i.op[0].disps->X_op == O_constant)
2293 {
2294 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2295 the absolute address given by the constant. Since ix86 jumps and
2296 calls are pc relative, we need to generate a reloc. */
2297 i.op[0].disps->X_add_symbol = &abs_symbol;
2298 i.op[0].disps->X_op = O_symbol;
2299 }
252b5132 2300
40fb9820 2301 if (i.tm.opcode_modifier.rex64)
161a04f6 2302 i.rex |= REX_W;
252b5132 2303
29b0f896
AM		 2304 /* For 8 bit registers we need an empty rex prefix. Also if the
2305 instruction already has a prefix, we need to convert old
2306 registers to new ones. */
773f551c 2307
40fb9820 2308 if ((i.types[0].bitfield.reg8
29b0f896 2309 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2310 || (i.types[1].bitfield.reg8
29b0f896 2311 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2312 || ((i.types[0].bitfield.reg8
2313 || i.types[1].bitfield.reg8)
29b0f896
AM		 2314 && i.rex != 0))
2315 {
2316 int x;
726c5dcd 2317
29b0f896
AM		 2318 i.rex |= REX_OPCODE;
2319 for (x = 0; x < 2; x++)
2320 {
2321 /* Look for 8 bit operand that uses old registers. */
40fb9820 2322 if (i.types[x].bitfield.reg8
29b0f896 2323 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2324 {
29b0f896
AM		 2325 /* In case it is "hi" register, give up. */
2326 if (i.op[x].regs->reg_num > 3)
a540244d 2327 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2328 "instruction requiring REX prefix."),
a540244d 2329 register_prefix, i.op[x].regs->reg_name);
773f551c 2330
29b0f896
AM		 2331 /* Otherwise it is equivalent to the extended register.
2332 Since the encoding doesn't change this is merely
2333 cosmetic cleanup for debug output. */
2334
2335 i.op[x].regs = i.op[x].regs + 8;
773f551c 2336 }
29b0f896
AM		 2337 }
2338 }
773f551c 2339
85f10a01
MM		 2340 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2341 REX prefix. */
2342 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2343 {
2344 i.drex.rex = i.rex;
2345 i.rex = 0;
2346 }
2347 else if (i.rex != 0)
29b0f896
AM		 2348 add_prefix (REX_OPCODE | i.rex);
2349
2350 /* We are ready to output the insn. */
2351 output_insn ();
2352}
2353
2354static char *
e3bb37b5 2355parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2356{
2357 char *l = line;
2358 char *token_start = l;
2359 char *mnem_p;
5c6af06e
JB		 2360 int supported;
2361 const template *t;
29b0f896
AM		 2362
2363 /* Non-zero if we found a prefix only acceptable with string insns. */
2364 const char *expecting_string_instruction = NULL;
45288df1 2365
29b0f896
AM		 2366 while (1)
2367 {
2368 mnem_p = mnemonic;
2369 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2370 {
2371 mnem_p++;
2372 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2373 {
29b0f896
AM		 2374 as_bad (_("no such instruction: `%s'"), token_start);
2375 return NULL;
2376 }
2377 l++;
2378 }
2379 if (!is_space_char (*l)
2380 && *l != END_OF_INSN
e44823cf
JB		 2381 && (intel_syntax
2382 || (*l != PREFIX_SEPARATOR
2383 && *l != ',')))
29b0f896
AM		 2384 {
2385 as_bad (_("invalid character %s in mnemonic"),
2386 output_invalid (*l));
2387 return NULL;
2388 }
2389 if (token_start == l)
2390 {
e44823cf 2391 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2392 as_bad (_("expecting prefix; got nothing"));
2393 else
2394 as_bad (_("expecting mnemonic; got nothing"));
2395 return NULL;
2396 }
45288df1 2397
29b0f896
AM		 2398 /* Look up instruction (or prefix) via hash table. */
2399 current_templates = hash_find (op_hash, mnemonic);
47926f60 2400
29b0f896
AM		 2401 if (*l != END_OF_INSN
2402 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2403 && current_templates
40fb9820 2404 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2405 {
c6fb90c8 2406 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2407 {
2408 as_bad ((flag_code != CODE_64BIT
2409 ? _("`%s' is only supported in 64-bit mode")
2410 : _("`%s' is not supported in 64-bit mode")),
2411 current_templates->start->name);
2412 return NULL;
2413 }
29b0f896
AM		 2414 /* If we are in 16-bit mode, do not allow addr16 or data16.
2415 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2416 if ((current_templates->start->opcode_modifier.size16
2417 || current_templates->start->opcode_modifier.size32)
29b0f896 2418 && flag_code != CODE_64BIT
40fb9820 2419 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2420 ^ (flag_code == CODE_16BIT)))
2421 {
2422 as_bad (_("redundant %s prefix"),
2423 current_templates->start->name);
2424 return NULL;
45288df1 2425 }
29b0f896
AM		 2426 /* Add prefix, checking for repeated prefixes. */
2427 switch (add_prefix (current_templates->start->base_opcode))
2428 {
2429 case 0:
2430 return NULL;
2431 case 2:
2432 expecting_string_instruction = current_templates->start->name;
2433 break;
2434 }
2435 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2436 token_start = ++l;
2437 }
2438 else
2439 break;
2440 }
45288df1 2441
29b0f896
AM		 2442 if (!current_templates)
2443 {
2444 /* See if we can get a match by trimming off a suffix. */
2445 switch (mnem_p[-1])
2446 {
2447 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2448 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2449 i.suffix = SHORT_MNEM_SUFFIX;
2450 else
29b0f896
AM		 2451 case BYTE_MNEM_SUFFIX:
2452 case QWORD_MNEM_SUFFIX:
2453 i.suffix = mnem_p[-1];
2454 mnem_p[-1] = '\0';
2455 current_templates = hash_find (op_hash, mnemonic);
2456 break;
2457 case SHORT_MNEM_SUFFIX:
2458 case LONG_MNEM_SUFFIX:
2459 if (!intel_syntax)
2460 {
2461 i.suffix = mnem_p[-1];
2462 mnem_p[-1] = '\0';
2463 current_templates = hash_find (op_hash, mnemonic);
2464 }
2465 break;
252b5132 2466
29b0f896
AM		 2467 /* Intel Syntax. */
2468 case 'd':
2469 if (intel_syntax)
2470 {
9306ca4a 2471 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2472 i.suffix = SHORT_MNEM_SUFFIX;
2473 else
2474 i.suffix = LONG_MNEM_SUFFIX;
2475 mnem_p[-1] = '\0';
2476 current_templates = hash_find (op_hash, mnemonic);
2477 }
2478 break;
2479 }
2480 if (!current_templates)
2481 {
2482 as_bad (_("no such instruction: `%s'"), token_start);
2483 return NULL;
2484 }
2485 }
252b5132 2486
40fb9820
L		 2487 if (current_templates->start->opcode_modifier.jump
2488 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2489 {
2490 /* Check for a branch hint. We allow ",pt" and ",pn" for
2491 predict taken and predict not taken respectively.
2492 I'm not sure that branch hints actually do anything on loop
2493 and jcxz insns (JumpByte) for current Pentium4 chips. They
2494 may work in the future and it doesn't hurt to accept them
2495 now. */
2496 if (l[0] == ',' && l[1] == 'p')
2497 {
2498 if (l[2] == 't')
2499 {
2500 if (!add_prefix (DS_PREFIX_OPCODE))
2501 return NULL;
2502 l += 3;
2503 }
2504 else if (l[2] == 'n')
2505 {
2506 if (!add_prefix (CS_PREFIX_OPCODE))
2507 return NULL;
2508 l += 3;
2509 }
2510 }
2511 }
2512 /* Any other comma loses. */
2513 if (*l == ',')
2514 {
2515 as_bad (_("invalid character %s in mnemonic"),
2516 output_invalid (*l));
2517 return NULL;
2518 }
252b5132 2519
29b0f896 2520 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2521 supported = 0;
2522 for (t = current_templates->start; t < current_templates->end; ++t)
2523 {
3629bb00
L		 2524 supported |= cpu_flags_match (t->cpu_flags);
2525 if (supported == 3)
2526 goto skip;
5c6af06e 2527 }
3629bb00 2528
5c6af06e
JB		 2529 if (!(supported & 2))
2530 {
2531 as_bad (flag_code == CODE_64BIT
2532 ? _("`%s' is not supported in 64-bit mode")
2533 : _("`%s' is only supported in 64-bit mode"),
2534 current_templates->start->name);
2535 return NULL;
2536 }
2537 if (!(supported & 1))
29b0f896 2538 {
3629bb00
L		 2539 as_bad (_("`%s' is not supported on `%s%s'"),
2540 current_templates->start->name, cpu_arch_name,
2541 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2542 return NULL;
29b0f896 2543 }
3629bb00
L		 2544
2545skip:
2546 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 2547 && (flag_code != CODE_16BIT))
29b0f896
AM		 2548 {
2549 as_warn (_("use .code16 to ensure correct addressing mode"));
2550 }
252b5132 2551
29b0f896 2552 /* Check for rep/repne without a string instruction. */
f41bbced 2553 if (expecting_string_instruction)
29b0f896 2554 {
f41bbced
JB		 2555 static templates override;
2556
2557 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2558 if (t->opcode_modifier.isstring)
f41bbced
JB		 2559 break;
2560 if (t >= current_templates->end)
2561 {
2562 as_bad (_("expecting string instruction after `%s'"),
64e74474 2563 expecting_string_instruction);
f41bbced
JB		 2564 return NULL;
2565 }
2566 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2567 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2568 break;
2569 override.end = t;
2570 current_templates = &override;
29b0f896 2571 }
252b5132 2572
29b0f896
AM		 2573 return l;
2574}
252b5132 2575
29b0f896 2576static char *
e3bb37b5 2577parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2578{
2579 char *token_start;
3138f287 2580
29b0f896
AM		 2581 /* 1 if operand is pending after ','. */
2582 unsigned int expecting_operand = 0;
252b5132 2583
29b0f896
AM		 2584 /* Non-zero if operand parens not balanced. */
2585 unsigned int paren_not_balanced;
2586
2587 while (*l != END_OF_INSN)
2588 {
2589 /* Skip optional white space before operand. */
2590 if (is_space_char (*l))
2591 ++l;
2592 if (!is_operand_char (*l) && *l != END_OF_INSN)
2593 {
2594 as_bad (_("invalid character %s before operand %d"),
2595 output_invalid (*l),
2596 i.operands + 1);
2597 return NULL;
2598 }
2599 token_start = l; /* after white space */
2600 paren_not_balanced = 0;
2601 while (paren_not_balanced || *l != ',')
2602 {
2603 if (*l == END_OF_INSN)
2604 {
2605 if (paren_not_balanced)
2606 {
2607 if (!intel_syntax)
2608 as_bad (_("unbalanced parenthesis in operand %d."),
2609 i.operands + 1);
2610 else
2611 as_bad (_("unbalanced brackets in operand %d."),
2612 i.operands + 1);
2613 return NULL;
2614 }
2615 else
2616 break; /* we are done */
2617 }
2618 else if (!is_operand_char (*l) && !is_space_char (*l))
2619 {
2620 as_bad (_("invalid character %s in operand %d"),
2621 output_invalid (*l),
2622 i.operands + 1);
2623 return NULL;
2624 }
2625 if (!intel_syntax)
2626 {
2627 if (*l == '(')
2628 ++paren_not_balanced;
2629 if (*l == ')')
2630 --paren_not_balanced;
2631 }
2632 else
2633 {
2634 if (*l == '[')
2635 ++paren_not_balanced;
2636 if (*l == ']')
2637 --paren_not_balanced;
2638 }
2639 l++;
2640 }
2641 if (l != token_start)
2642 { /* Yes, we've read in another operand. */
2643 unsigned int operand_ok;
2644 this_operand = i.operands++;
2645 if (i.operands > MAX_OPERANDS)
2646 {
2647 as_bad (_("spurious operands; (%d operands/instruction max)"),
2648 MAX_OPERANDS);
2649 return NULL;
2650 }
2651 /* Now parse operand adding info to 'i' as we go along. */
2652 END_STRING_AND_SAVE (l);
2653
2654 if (intel_syntax)
2655 operand_ok =
2656 i386_intel_operand (token_start,
2657 intel_float_operand (mnemonic));
2658 else
2659 operand_ok = i386_operand (token_start);
2660
2661 RESTORE_END_STRING (l);
2662 if (!operand_ok)
2663 return NULL;
2664 }
2665 else
2666 {
2667 if (expecting_operand)
2668 {
2669 expecting_operand_after_comma:
2670 as_bad (_("expecting operand after ','; got nothing"));
2671 return NULL;
2672 }
2673 if (*l == ',')
2674 {
2675 as_bad (_("expecting operand before ','; got nothing"));
2676 return NULL;
2677 }
2678 }
7f3f1ea2 2679
29b0f896
AM		 2680 /* Now *l must be either ',' or END_OF_INSN. */
2681 if (*l == ',')
2682 {
2683 if (*++l == END_OF_INSN)
2684 {
2685 /* Just skip it, if it's \n complain. */
2686 goto expecting_operand_after_comma;
2687 }
2688 expecting_operand = 1;
2689 }
2690 }
2691 return l;
2692}
7f3f1ea2 2693
050dfa73 2694static void
4d456e3d 2695swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2696{
2697 union i386_op temp_op;
40fb9820 2698 i386_operand_type temp_type;
050dfa73 2699 enum bfd_reloc_code_real temp_reloc;
4eed87de 2700
050dfa73
MM		 2701 temp_type = i.types[xchg2];
2702 i.types[xchg2] = i.types[xchg1];
2703 i.types[xchg1] = temp_type;
2704 temp_op = i.op[xchg2];
2705 i.op[xchg2] = i.op[xchg1];
2706 i.op[xchg1] = temp_op;
2707 temp_reloc = i.reloc[xchg2];
2708 i.reloc[xchg2] = i.reloc[xchg1];
2709 i.reloc[xchg1] = temp_reloc;
2710}
2711
29b0f896 2712static void
e3bb37b5 2713swap_operands (void)
29b0f896 2714{
b7c61d9a 2715 switch (i.operands)
050dfa73 2716 {
b7c61d9a 2717 case 4:
4d456e3d 2718 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2719 case 3:
2720 case 2:
4d456e3d 2721 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2722 break;
2723 default:
2724 abort ();
29b0f896 2725 }
29b0f896
AM		 2726
2727 if (i.mem_operands == 2)
2728 {
2729 const seg_entry *temp_seg;
2730 temp_seg = i.seg[0];
2731 i.seg[0] = i.seg[1];
2732 i.seg[1] = temp_seg;
2733 }
2734}
252b5132 2735
29b0f896
AM		 2736/* Try to ensure constant immediates are represented in the smallest
2737 opcode possible. */
2738static void
e3bb37b5 2739optimize_imm (void)
29b0f896
AM		 2740{
2741 char guess_suffix = 0;
2742 int op;
252b5132 2743
29b0f896
AM		 2744 if (i.suffix)
2745 guess_suffix = i.suffix;
2746 else if (i.reg_operands)
2747 {
2748 /* Figure out a suffix from the last register operand specified.
2749 We can't do this properly yet, ie. excluding InOutPortReg,
2750 but the following works for instructions with immediates.
2751 In any case, we can't set i.suffix yet. */
2752 for (op = i.operands; --op >= 0;)
40fb9820
L		 2753 if (i.types[op].bitfield.reg8)
2754 {
2755 guess_suffix = BYTE_MNEM_SUFFIX;
2756 break;
2757 }
2758 else if (i.types[op].bitfield.reg16)
252b5132 2759 {
40fb9820
L		 2760 guess_suffix = WORD_MNEM_SUFFIX;
2761 break;
2762 }
2763 else if (i.types[op].bitfield.reg32)
2764 {
2765 guess_suffix = LONG_MNEM_SUFFIX;
2766 break;
2767 }
2768 else if (i.types[op].bitfield.reg64)
2769 {
2770 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2771 break;
252b5132 2772 }
29b0f896
AM		 2773 }
2774 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2775 guess_suffix = WORD_MNEM_SUFFIX;
2776
2777 for (op = i.operands; --op >= 0;)
40fb9820 2778 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2779 {
2780 switch (i.op[op].imms->X_op)
252b5132 2781 {
29b0f896
AM		 2782 case O_constant:
2783 /* If a suffix is given, this operand may be shortened. */
2784 switch (guess_suffix)
252b5132 2785 {
29b0f896 2786 case LONG_MNEM_SUFFIX:
40fb9820
L		 2787 i.types[op].bitfield.imm32 = 1;
2788 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2789 break;
2790 case WORD_MNEM_SUFFIX:
40fb9820
L		 2791 i.types[op].bitfield.imm16 = 1;
2792 i.types[op].bitfield.imm32 = 1;
2793 i.types[op].bitfield.imm32s = 1;
2794 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2795 break;
2796 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2797 i.types[op].bitfield.imm8 = 1;
2798 i.types[op].bitfield.imm8s = 1;
2799 i.types[op].bitfield.imm16 = 1;
2800 i.types[op].bitfield.imm32 = 1;
2801 i.types[op].bitfield.imm32s = 1;
2802 i.types[op].bitfield.imm64 = 1;
29b0f896 2803 break;
252b5132 2804 }
252b5132 2805
29b0f896
AM		 2806 /* If this operand is at most 16 bits, convert it
2807 to a signed 16 bit number before trying to see
2808 whether it will fit in an even smaller size.
2809 This allows a 16-bit operand such as $0xffe0 to
2810 be recognised as within Imm8S range. */
40fb9820 2811 if ((i.types[op].bitfield.imm16)
29b0f896 2812 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2813 {
29b0f896
AM		 2814 i.op[op].imms->X_add_number =
2815 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2816 }
40fb9820 2817 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2818 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2819 == 0))
2820 {
2821 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2822 ^ ((offsetT) 1 << 31))
2823 - ((offsetT) 1 << 31));
2824 }
40fb9820 2825 i.types[op]
c6fb90c8
L		 2826 = operand_type_or (i.types[op],
2827 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2828
29b0f896
AM		 2829 /* We must avoid matching of Imm32 templates when 64bit
2830 only immediate is available. */
2831 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2832 i.types[op].bitfield.imm32 = 0;
29b0f896 2833 break;
252b5132 2834
29b0f896
AM		 2835 case O_absent:
2836 case O_register:
2837 abort ();
2838
2839 /* Symbols and expressions. */
2840 default:
9cd96992
JB		 2841 /* Convert symbolic operand to proper sizes for matching, but don't
2842 prevent matching a set of insns that only supports sizes other
2843 than those matching the insn suffix. */
2844 {
40fb9820 2845 i386_operand_type mask, allowed;
9cd96992
JB		 2846 const template *t;
2847
c6fb90c8
L		 2848 UINTS_CLEAR (mask);
2849 UINTS_CLEAR (allowed);
40fb9820 2850
4eed87de
AM		 2851 for (t = current_templates->start;
2852 t < current_templates->end;
2853 ++t)
c6fb90c8
L		 2854 allowed = operand_type_or (allowed,
2855 t->operand_types[op]);
9cd96992
JB		 2856 switch (guess_suffix)
2857 {
2858 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2859 mask.bitfield.imm64 = 1;
2860 mask.bitfield.imm32s = 1;
9cd96992
JB		 2861 break;
2862 case LONG_MNEM_SUFFIX:
40fb9820 2863 mask.bitfield.imm32 = 1;
9cd96992
JB		 2864 break;
2865 case WORD_MNEM_SUFFIX:
40fb9820 2866 mask.bitfield.imm16 = 1;
9cd96992
JB		 2867 break;
2868 case BYTE_MNEM_SUFFIX:
40fb9820 2869 mask.bitfield.imm8 = 1;
9cd96992
JB		 2870 break;
2871 default:
9cd96992
JB		 2872 break;
2873 }
c6fb90c8
L		 2874 allowed = operand_type_and (mask, allowed);
2875 if (!UINTS_ALL_ZERO (allowed))
2876 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2877 }
29b0f896 2878 break;
252b5132 2879 }
29b0f896
AM		 2880 }
2881}
47926f60 2882
29b0f896
AM		 2883/* Try to use the smallest displacement type too. */
2884static void
e3bb37b5 2885optimize_disp (void)
29b0f896
AM		 2886{
2887 int op;
3e73aa7c 2888
29b0f896 2889 for (op = i.operands; --op >= 0;)
40fb9820 2890 if (operand_type_check (i.types[op], disp))
252b5132 2891 {
b300c311 2892 if (i.op[op].disps->X_op == O_constant)
252b5132 2893 {
b300c311 2894 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2895
40fb9820 2896 if (i.types[op].bitfield.disp16
b300c311
L		 2897 && (disp & ~(offsetT) 0xffff) == 0)
2898 {
2899 /* If this operand is at most 16 bits, convert
2900 to a signed 16 bit number and don't use 64bit
2901 displacement. */
2902 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2903 i.types[op].bitfield.disp64 = 0;
b300c311 2904 }
40fb9820 2905 if (i.types[op].bitfield.disp32
b300c311
L		 2906 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2907 {
2908 /* If this operand is at most 32 bits, convert
2909 to a signed 32 bit number and don't use 64bit
2910 displacement. */
2911 disp &= (((offsetT) 2 << 31) - 1);
2912 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2913 i.types[op].bitfield.disp64 = 0;
b300c311 2914 }
40fb9820 2915 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2916 {
40fb9820
L		 2917 i.types[op].bitfield.disp8 = 0;
2918 i.types[op].bitfield.disp16 = 0;
2919 i.types[op].bitfield.disp32 = 0;
2920 i.types[op].bitfield.disp32s = 0;
2921 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2922 i.op[op].disps = 0;
2923 i.disp_operands--;
2924 }
2925 else if (flag_code == CODE_64BIT)
2926 {
2927 if (fits_in_signed_long (disp))
28a9d8f5 2928 {
40fb9820
L		 2929 i.types[op].bitfield.disp64 = 0;
2930 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2931 }
b300c311 2932 if (fits_in_unsigned_long (disp))
40fb9820 2933 i.types[op].bitfield.disp32 = 1;
b300c311 2934 }
40fb9820
L		 2935 if ((i.types[op].bitfield.disp32
2936 || i.types[op].bitfield.disp32s
2937 || i.types[op].bitfield.disp16)
b300c311 2938 && fits_in_signed_byte (disp))
40fb9820 2939 i.types[op].bitfield.disp8 = 1;
252b5132 2940 }
67a4f2b7
AO		 2941 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2942 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2943 {
2944 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2945 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2946 i.types[op].bitfield.disp8 = 0;
2947 i.types[op].bitfield.disp16 = 0;
2948 i.types[op].bitfield.disp32 = 0;
2949 i.types[op].bitfield.disp32s = 0;
2950 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2951 }
2952 else
b300c311 2953 /* We only support 64bit displacement on constants. */
40fb9820 2954 i.types[op].bitfield.disp64 = 0;
252b5132 2955 }
29b0f896
AM		 2956}
2957
2958static int
e3bb37b5 2959match_template (void)
29b0f896
AM		 2960{
2961 /* Points to template once we've found it. */
2962 const template *t;
40fb9820 2963 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2964 unsigned int found_reverse_match;
40fb9820
L		 2965 i386_opcode_modifier suffix_check;
2966 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2967 int addr_prefix_disp;
a5c311ca 2968 unsigned int j;
3629bb00 2969 unsigned int found_cpu_match;
29b0f896 2970
f48ff2ae
L		 2971#if MAX_OPERANDS != 4
2972# error "MAX_OPERANDS must be 4."
2973#endif
2974
29b0f896 2975 found_reverse_match = 0;
539e75ad 2976 addr_prefix_disp = -1;
40fb9820
L		 2977
2978 memset (&suffix_check, 0, sizeof (suffix_check));
2979 if (i.suffix == BYTE_MNEM_SUFFIX)
2980 suffix_check.no_bsuf = 1;
2981 else if (i.suffix == WORD_MNEM_SUFFIX)
2982 suffix_check.no_wsuf = 1;
2983 else if (i.suffix == SHORT_MNEM_SUFFIX)
2984 suffix_check.no_ssuf = 1;
2985 else if (i.suffix == LONG_MNEM_SUFFIX)
2986 suffix_check.no_lsuf = 1;
2987 else if (i.suffix == QWORD_MNEM_SUFFIX)
2988 suffix_check.no_qsuf = 1;
2989 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 2990 suffix_check.no_ldsuf = 1;
582d5edd 2991 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
24995bd6 2992 suffix_check.xmmword = 1;
29b0f896 2993
45aa61fe 2994 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2995 {
539e75ad
L		 2996 addr_prefix_disp = -1;
2997
29b0f896
AM		 2998 /* Must have right number of operands. */
2999 if (i.operands != t->operands)
3000 continue;
3001
e1d4d893
L		 3002 /* Check old gcc support. */
3003 if (!old_gcc && t->opcode_modifier.oldgcc)
3004 continue;
3005
3006 /* Check AT&T mnemonic. */
3007 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3008 continue;
3009
e1d4d893
L		 3010 /* Check Intel syntax. */
3011 if (intel_syntax && t->opcode_modifier.attsyntax)
1efbbeb4
L		 3012 continue;
3013
20592a94 3014 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3015 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3016 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3017 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3018 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3019 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3020 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3021 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3022 continue;
3023
582d5edd
L		 3024 /* Check the memory size in Intel mode when it is provided if
3025 needed. */
3026 if (intel_syntax
3027 && i.suffix
3028 && t->opcode_modifier.checksize
3029 && (!t->opcode_modifier.byte || !suffix_check.no_bsuf)
3030 && (!t->opcode_modifier.word || !suffix_check.no_wsuf)
3031 && (!t->opcode_modifier.dword || !suffix_check.no_lsuf)
3032 && (!t->opcode_modifier.qword || !suffix_check.no_qsuf)
24995bd6 3033 && (!t->opcode_modifier.xmmword || !suffix_check.xmmword))
582d5edd
L		 3034 continue;
3035
a5c311ca
L		 3036 for (j = 0; j < MAX_OPERANDS; j++)
3037 operand_types [j] = t->operand_types [j];
539e75ad 3038
45aa61fe
AM		 3039 /* In general, don't allow 64-bit operands in 32-bit mode. */
3040 if (i.suffix == QWORD_MNEM_SUFFIX
3041 && flag_code != CODE_64BIT
3042 && (intel_syntax
40fb9820 3043 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3044 && !intel_float_operand (t->name))
3045 : intel_float_operand (t->name) != 2)
40fb9820
L		 3046 && ((!operand_types[0].bitfield.regmmx
3047 && !operand_types[0].bitfield.regxmm)
3048 || (!operand_types[t->operands > 1].bitfield.regmmx
3049 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3050 && (t->base_opcode != 0x0fc7
3051 || t->extension_opcode != 1 /* cmpxchg8b */))
3052 continue;
3053
29b0f896 3054 /* Do not verify operands when there are none. */
c6fb90c8 3055 else
29b0f896 3056 {
3629bb00 3057 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
c6fb90c8
L		 3058 if (!t->operands)
3059 {
3629bb00 3060 if (!found_cpu_match)
c6fb90c8
L		 3061 continue;
3062 /* We've found a match; break out of loop. */
3063 break;
3064 }
29b0f896 3065 }
252b5132 3066
539e75ad
L		 3067 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3068 into Disp32/Disp16/Disp32 operand. */
3069 if (i.prefix[ADDR_PREFIX] != 0)
3070 {
40fb9820 3071 /* There should be only one Disp operand. */
539e75ad
L		 3072 switch (flag_code)
3073 {
3074 case CODE_16BIT:
40fb9820
L		 3075 for (j = 0; j < MAX_OPERANDS; j++)
3076 {
3077 if (operand_types[j].bitfield.disp16)
3078 {
3079 addr_prefix_disp = j;
3080 operand_types[j].bitfield.disp32 = 1;
3081 operand_types[j].bitfield.disp16 = 0;
3082 break;
3083 }
3084 }
539e75ad
L		 3085 break;
3086 case CODE_32BIT:
40fb9820
L		 3087 for (j = 0; j < MAX_OPERANDS; j++)
3088 {
3089 if (operand_types[j].bitfield.disp32)
3090 {
3091 addr_prefix_disp = j;
3092 operand_types[j].bitfield.disp32 = 0;
3093 operand_types[j].bitfield.disp16 = 1;
3094 break;
3095 }
3096 }
539e75ad
L		 3097 break;
3098 case CODE_64BIT:
40fb9820
L		 3099 for (j = 0; j < MAX_OPERANDS; j++)
3100 {
3101 if (operand_types[j].bitfield.disp64)
3102 {
3103 addr_prefix_disp = j;
3104 operand_types[j].bitfield.disp64 = 0;
3105 operand_types[j].bitfield.disp32 = 1;
3106 break;
3107 }
3108 }
539e75ad
L		 3109 break;
3110 }
539e75ad
L		 3111 }
3112
c6fb90c8 3113 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3114 switch (t->operands)
3115 {
3116 case 1:
40fb9820 3117 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3118 continue;
3119 break;
3120 case 2:
8b38ad71
L		 3121 /* xchg %eax, %eax is a special case. It is an aliase for nop
3122 only in 32bit mode and we can use opcode 0x90. In 64bit
3123 mode, we can't use 0x90 for xchg %eax, %eax since it should
3124 zero-extend %eax to %rax. */
3125 if (flag_code == CODE_64BIT
3126 && t->base_opcode == 0x90
c6fb90c8
L		 3127 && UINTS_EQUAL (i.types [0], acc32)
3128 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3129 continue;
29b0f896 3130 case 3:
f48ff2ae 3131 case 4:
c6fb90c8 3132 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3133 if (!operand_type_match (overlap0, i.types[0])
3134 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3135 /* monitor in SSE3 is a very special case. The first
708587a4 3136 register and the second register may have different
26186d74
L		 3137 sizes. The same applies to crc32 in SSE4.2. It is
3138 also true for invlpga, vmload, vmrun and vmsave in
3139 SVME. */
cb712a9e 3140 || !((t->base_opcode == 0x0f01
26186d74
L		 3141 && (t->extension_opcode == 0xc8
3142 || t->extension_opcode == 0xd8
3143 || t->extension_opcode == 0xda
3144 || t->extension_opcode == 0xdb
3145 || t->extension_opcode == 0xdf))
381d071f 3146 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3147 || operand_type_register_match (overlap0, i.types[0],
3148 operand_types[0],
3149 overlap1, i.types[1],
3150 operand_types[1])))
29b0f896
AM		 3151 {
3152 /* Check if other direction is valid ... */
40fb9820 3153 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3154 continue;
3155
3156 /* Try reversing direction of operands. */
c6fb90c8
L		 3157 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3158 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3159 if (!operand_type_match (overlap0, i.types[0])
3160 || !operand_type_match (overlap1, i.types[1])
3161 || !operand_type_register_match (overlap0, i.types[0],
3162 operand_types[1],
3163 overlap1, i.types[1],
3164 operand_types[0]))
29b0f896
AM		 3165 {
3166 /* Does not match either direction. */
3167 continue;
3168 }
3169 /* found_reverse_match holds which of D or FloatDR
3170 we've found. */
40fb9820 3171 if (t->opcode_modifier.d)
8a2ed489 3172 found_reverse_match = Opcode_D;
40fb9820 3173 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3174 found_reverse_match = Opcode_FloatD;
3175 else
3176 found_reverse_match = 0;
40fb9820 3177 if (t->opcode_modifier.floatr)
8a2ed489 3178 found_reverse_match |= Opcode_FloatR;
29b0f896 3179 }
f48ff2ae 3180 else
29b0f896 3181 {
f48ff2ae 3182 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3183 switch (t->operands)
3184 {
3185 case 4:
c6fb90c8
L		 3186 overlap3 = operand_type_and (i.types[3],
3187 operand_types[3]);
d1cbb4db 3188 case 3:
c6fb90c8
L		 3189 overlap2 = operand_type_and (i.types[2],
3190 operand_types[2]);
d1cbb4db
L		 3191 break;
3192 }
29b0f896 3193
f48ff2ae
L		 3194 switch (t->operands)
3195 {
3196 case 4:
40fb9820
L		 3197 if (!operand_type_match (overlap3, i.types[3])
3198 || !operand_type_register_match (overlap2,
3199 i.types[2],
3200 operand_types[2],
3201 overlap3,
3202 i.types[3],
3203 operand_types[3]))
f48ff2ae
L		 3204 continue;
3205 case 3:
3206 /* Here we make use of the fact that there are no
3207 reverse match 3 operand instructions, and all 3
3208 operand instructions only need to be checked for
3209 register consistency between operands 2 and 3. */
40fb9820
L		 3210 if (!operand_type_match (overlap2, i.types[2])
3211 || !operand_type_register_match (overlap1,
3212 i.types[1],
3213 operand_types[1],
3214 overlap2,
3215 i.types[2],
3216 operand_types[2]))
f48ff2ae
L		 3217 continue;
3218 break;
3219 }
29b0f896 3220 }
f48ff2ae 3221 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3222 slip through to break. */
3223 }
3629bb00 3224 if (!found_cpu_match)
29b0f896
AM		 3225 {
3226 found_reverse_match = 0;
3227 continue;
3228 }
3229 /* We've found a match; break out of loop. */
3230 break;
3231 }
3232
3233 if (t == current_templates->end)
3234 {
3235 /* We found no match. */
3236 as_bad (_("suffix or operands invalid for `%s'"),
3237 current_templates->start->name);
3238 return 0;
3239 }
252b5132 3240
29b0f896
AM		 3241 if (!quiet_warnings)
3242 {
3243 if (!intel_syntax
40fb9820
L		 3244 && (i.types[0].bitfield.jumpabsolute
3245 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3246 {
3247 as_warn (_("indirect %s without `*'"), t->name);
3248 }
3249
40fb9820
L		 3250 if (t->opcode_modifier.isprefix
3251 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3252 {
3253 /* Warn them that a data or address size prefix doesn't
3254 affect assembly of the next line of code. */
3255 as_warn (_("stand-alone `%s' prefix"), t->name);
3256 }
3257 }
3258
3259 /* Copy the template we found. */
3260 i.tm = *t;
539e75ad
L		 3261
3262 if (addr_prefix_disp != -1)
3263 i.tm.operand_types[addr_prefix_disp]
3264 = operand_types[addr_prefix_disp];
3265
29b0f896
AM		 3266 if (found_reverse_match)
3267 {
3268 /* If we found a reverse match we must alter the opcode
3269 direction bit. found_reverse_match holds bits to change
3270 (different for int & float insns). */
3271
3272 i.tm.base_opcode ^= found_reverse_match;
3273
539e75ad
L		 3274 i.tm.operand_types[0] = operand_types[1];
3275 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3276 }
3277
3278 return 1;
3279}
3280
3281static int
e3bb37b5 3282check_string (void)
29b0f896 3283{
40fb9820
L		 3284 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3285 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3286 {
3287 if (i.seg[0] != NULL && i.seg[0] != &es)
3288 {
3289 as_bad (_("`%s' operand %d must use `%%es' segment"),
3290 i.tm.name,
3291 mem_op + 1);
3292 return 0;
3293 }
3294 /* There's only ever one segment override allowed per instruction.
3295 This instruction possibly has a legal segment override on the
3296 second operand, so copy the segment to where non-string
3297 instructions store it, allowing common code. */
3298 i.seg[0] = i.seg[1];
3299 }
40fb9820 3300 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3301 {
3302 if (i.seg[1] != NULL && i.seg[1] != &es)
3303 {
3304 as_bad (_("`%s' operand %d must use `%%es' segment"),
3305 i.tm.name,
3306 mem_op + 2);
3307 return 0;
3308 }
3309 }
3310 return 1;
3311}
3312
3313static int
543613e9 3314process_suffix (void)
29b0f896
AM		 3315{
3316 /* If matched instruction specifies an explicit instruction mnemonic
3317 suffix, use it. */
40fb9820
L		 3318 if (i.tm.opcode_modifier.size16)
3319 i.suffix = WORD_MNEM_SUFFIX;
3320 else if (i.tm.opcode_modifier.size32)
3321 i.suffix = LONG_MNEM_SUFFIX;
3322 else if (i.tm.opcode_modifier.size64)
3323 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3324 else if (i.reg_operands)
3325 {
3326 /* If there's no instruction mnemonic suffix we try to invent one
3327 based on register operands. */
3328 if (!i.suffix)
3329 {
3330 /* We take i.suffix from the last register operand specified,
3331 Destination register type is more significant than source
381d071f
L		 3332 register type. crc32 in SSE4.2 prefers source register
3333 type. */
3334 if (i.tm.base_opcode == 0xf20f38f1)
3335 {
40fb9820
L		 3336 if (i.types[0].bitfield.reg16)
3337 i.suffix = WORD_MNEM_SUFFIX;
3338 else if (i.types[0].bitfield.reg32)
3339 i.suffix = LONG_MNEM_SUFFIX;
3340 else if (i.types[0].bitfield.reg64)
3341 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3342 }
9344ff29 3343 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3344 {
40fb9820 3345 if (i.types[0].bitfield.reg8)
20592a94
L		 3346 i.suffix = BYTE_MNEM_SUFFIX;
3347 }
381d071f
L		 3348
3349 if (!i.suffix)
3350 {
3351 int op;
3352
20592a94
L		 3353 if (i.tm.base_opcode == 0xf20f38f1
3354 || i.tm.base_opcode == 0xf20f38f0)
3355 {
3356 /* We have to know the operand size for crc32. */
3357 as_bad (_("ambiguous memory operand size for `%s`"),
3358 i.tm.name);
3359 return 0;
3360 }
3361
381d071f 3362 for (op = i.operands; --op >= 0;)
40fb9820 3363 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3364 {
40fb9820
L		 3365 if (i.types[op].bitfield.reg8)
3366 {
3367 i.suffix = BYTE_MNEM_SUFFIX;
3368 break;
3369 }
3370 else if (i.types[op].bitfield.reg16)
3371 {
3372 i.suffix = WORD_MNEM_SUFFIX;
3373 break;
3374 }
3375 else if (i.types[op].bitfield.reg32)
3376 {
3377 i.suffix = LONG_MNEM_SUFFIX;
3378 break;
3379 }
3380 else if (i.types[op].bitfield.reg64)
3381 {
3382 i.suffix = QWORD_MNEM_SUFFIX;
3383 break;
3384 }
381d071f
L		 3385 }
3386 }
29b0f896
AM		 3387 }
3388 else if (i.suffix == BYTE_MNEM_SUFFIX)
3389 {
3390 if (!check_byte_reg ())
3391 return 0;
3392 }
3393 else if (i.suffix == LONG_MNEM_SUFFIX)
3394 {
3395 if (!check_long_reg ())
3396 return 0;
3397 }
3398 else if (i.suffix == QWORD_MNEM_SUFFIX)
3399 {
955e1e6a
L		 3400 if (intel_syntax
3401 && i.tm.opcode_modifier.ignoresize
3402 && i.tm.opcode_modifier.no_qsuf)
3403 i.suffix = 0;
3404 else if (!check_qword_reg ())
29b0f896
AM		 3405 return 0;
3406 }
3407 else if (i.suffix == WORD_MNEM_SUFFIX)
3408 {
3409 if (!check_word_reg ())
3410 return 0;
3411 }
582d5edd
L		 3412 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3413 {
3414 /* Skip if the instruction has x suffix. match_template
3415 should check if it is a valid suffix. */
3416 }
40fb9820 3417 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3418 /* Do nothing if the instruction is going to ignore the prefix. */
3419 ;
3420 else
3421 abort ();
3422 }
40fb9820 3423 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3424 && !i.suffix
3425 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3426 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3427 {
3428 i.suffix = stackop_size;
3429 }
9306ca4a
JB		 3430 else if (intel_syntax
3431 && !i.suffix
40fb9820
L		 3432 && (i.tm.operand_types[0].bitfield.jumpabsolute
3433 || i.tm.opcode_modifier.jumpbyte
3434 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3435 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3436 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3437 {
3438 switch (flag_code)
3439 {
3440 case CODE_64BIT:
40fb9820 3441 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3442 {
3443 i.suffix = QWORD_MNEM_SUFFIX;
3444 break;
3445 }
3446 case CODE_32BIT:
40fb9820 3447 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3448 i.suffix = LONG_MNEM_SUFFIX;
3449 break;
3450 case CODE_16BIT:
40fb9820 3451 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3452 i.suffix = WORD_MNEM_SUFFIX;
3453 break;
3454 }
3455 }
252b5132 3456
9306ca4a 3457 if (!i.suffix)
29b0f896 3458 {
9306ca4a
JB		 3459 if (!intel_syntax)
3460 {
40fb9820 3461 if (i.tm.opcode_modifier.w)
9306ca4a 3462 {
4eed87de
AM		 3463 as_bad (_("no instruction mnemonic suffix given and "
3464 "no register operands; can't size instruction"));
9306ca4a
JB		 3465 return 0;
3466 }
3467 }
3468 else
3469 {
40fb9820
L		 3470 unsigned int suffixes;
3471
3472 suffixes = !i.tm.opcode_modifier.no_bsuf;
3473 if (!i.tm.opcode_modifier.no_wsuf)
3474 suffixes |= 1 << 1;
3475 if (!i.tm.opcode_modifier.no_lsuf)
3476 suffixes |= 1 << 2;
fc4adea1 3477 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 3478 suffixes |= 1 << 3;
3479 if (!i.tm.opcode_modifier.no_ssuf)
3480 suffixes |= 1 << 4;
3481 if (!i.tm.opcode_modifier.no_qsuf)
3482 suffixes |= 1 << 5;
3483
3484 /* There are more than suffix matches. */
3485 if (i.tm.opcode_modifier.w
9306ca4a 3486 || ((suffixes & (suffixes - 1))
40fb9820
L		 3487 && !i.tm.opcode_modifier.defaultsize
3488 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3489 {
3490 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3491 return 0;
3492 }
3493 }
29b0f896 3494 }
252b5132 3495
9306ca4a
JB		 3496 /* Change the opcode based on the operand size given by i.suffix;
3497 We don't need to change things for byte insns. */
3498
582d5edd
L		 3499 if (i.suffix
3500 && i.suffix != BYTE_MNEM_SUFFIX
3501 && i.suffix != XMMWORD_MNEM_SUFFIX)
29b0f896
AM		 3502 {
3503 /* It's not a byte, select word/dword operation. */
40fb9820 3504 if (i.tm.opcode_modifier.w)
29b0f896 3505 {
40fb9820 3506 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3507 i.tm.base_opcode |= 8;
3508 else
3509 i.tm.base_opcode |= 1;
3510 }
0f3f3d8b 3511
29b0f896
AM		 3512 /* Now select between word & dword operations via the operand
3513 size prefix, except for instructions that will ignore this
3514 prefix anyway. */
ca61edf2 3515 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3516 {
ca61edf2
L		 3517 /* The address size override prefix changes the size of the
3518 first operand. */
40fb9820
L		 3519 if ((flag_code == CODE_32BIT
3520 && i.op->regs[0].reg_type.bitfield.reg16)
3521 || (flag_code != CODE_32BIT
3522 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3523 if (!add_prefix (ADDR_PREFIX_OPCODE))
3524 return 0;
3525 }
3526 else if (i.suffix != QWORD_MNEM_SUFFIX
3527 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3528 && !i.tm.opcode_modifier.ignoresize
3529 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3530 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3531 || (flag_code == CODE_64BIT
40fb9820 3532 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3533 {
3534 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3535
40fb9820 3536 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3537 prefix = ADDR_PREFIX_OPCODE;
252b5132 3538
29b0f896
AM		 3539 if (!add_prefix (prefix))
3540 return 0;
24eab124 3541 }
252b5132 3542
29b0f896
AM		 3543 /* Set mode64 for an operand. */
3544 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3545 && flag_code == CODE_64BIT
40fb9820 3546 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3547 {
3548 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3549 need rex64. cmpxchg8b is also a special case. */
3550 if (! (i.operands == 2
3551 && i.tm.base_opcode == 0x90
3552 && i.tm.extension_opcode == None
c6fb90c8
L		 3553 && UINTS_EQUAL (i.types [0], acc64)
3554 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3555 && ! (i.operands == 1
3556 && i.tm.base_opcode == 0xfc7
3557 && i.tm.extension_opcode == 1
40fb9820
L		 3558 && !operand_type_check (i.types [0], reg)
3559 && operand_type_check (i.types [0], anymem)))
f6bee062 3560 i.rex |= REX_W;
46e883c5 3561 }
3e73aa7c 3562
29b0f896
AM		 3563 /* Size floating point instruction. */
3564 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3565 if (i.tm.opcode_modifier.floatmf)
543613e9 3566 i.tm.base_opcode ^= 4;
29b0f896 3567 }
7ecd2f8b 3568
29b0f896
AM		 3569 return 1;
3570}
3e73aa7c 3571
29b0f896 3572static int
543613e9 3573check_byte_reg (void)
29b0f896
AM		 3574{
3575 int op;
543613e9 3576
29b0f896
AM		 3577 for (op = i.operands; --op >= 0;)
3578 {
3579 /* If this is an eight bit register, it's OK. If it's the 16 or
3580 32 bit version of an eight bit register, we will just use the
3581 low portion, and that's OK too. */
40fb9820 3582 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3583 continue;
3584
ca61edf2
L		 3585 /* Don't generate this warning if not needed. */
3586 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3587 continue;
3588
9344ff29
L		 3589 /* crc32 doesn't generate this warning. */
3590 if (i.tm.base_opcode == 0xf20f38f0)
3591 continue;
3592
40fb9820
L		 3593 if ((i.types[op].bitfield.reg16
3594 || i.types[op].bitfield.reg32
3595 || i.types[op].bitfield.reg64)
3596 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3597 {
3598 /* Prohibit these changes in the 64bit mode, since the
3599 lowering is more complicated. */
3600 if (flag_code == CODE_64BIT
40fb9820 3601 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3602 {
2ca3ace5
L		 3603 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3604 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3605 i.suffix);
3606 return 0;
3607 }
3608#if REGISTER_WARNINGS
3609 if (!quiet_warnings
40fb9820 3610 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3611 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3612 register_prefix,
40fb9820 3613 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3614 ? REGNAM_AL - REGNAM_AX
3615 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3616 register_prefix,
29b0f896
AM		 3617 i.op[op].regs->reg_name,
3618 i.suffix);
3619#endif
3620 continue;
3621 }
3622 /* Any other register is bad. */
40fb9820
L		 3623 if (i.types[op].bitfield.reg16
3624 || i.types[op].bitfield.reg32
3625 || i.types[op].bitfield.reg64
3626 || i.types[op].bitfield.regmmx
3627 || i.types[op].bitfield.regxmm
3628 || i.types[op].bitfield.sreg2
3629 || i.types[op].bitfield.sreg3
3630 || i.types[op].bitfield.control
3631 || i.types[op].bitfield.debug
3632 || i.types[op].bitfield.test
3633 || i.types[op].bitfield.floatreg
3634 || i.types[op].bitfield.floatacc)
29b0f896 3635 {
a540244d
L		 3636 as_bad (_("`%s%s' not allowed with `%s%c'"),
3637 register_prefix,
29b0f896
AM		 3638 i.op[op].regs->reg_name,
3639 i.tm.name,
3640 i.suffix);
3641 return 0;
3642 }
3643 }
3644 return 1;
3645}
3646
3647static int
e3bb37b5 3648check_long_reg (void)
29b0f896
AM		 3649{
3650 int op;
3651
3652 for (op = i.operands; --op >= 0;)
3653 /* Reject eight bit registers, except where the template requires
3654 them. (eg. movzb) */
40fb9820
L		 3655 if (i.types[op].bitfield.reg8
3656 && (i.tm.operand_types[op].bitfield.reg16
3657 || i.tm.operand_types[op].bitfield.reg32
3658 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3659 {
a540244d
L		 3660 as_bad (_("`%s%s' not allowed with `%s%c'"),
3661 register_prefix,
29b0f896
AM		 3662 i.op[op].regs->reg_name,
3663 i.tm.name,
3664 i.suffix);
3665 return 0;
3666 }
3667 /* Warn if the e prefix on a general reg is missing. */
3668 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3669 && i.types[op].bitfield.reg16
3670 && (i.tm.operand_types[op].bitfield.reg32
3671 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3672 {
3673 /* Prohibit these changes in the 64bit mode, since the
3674 lowering is more complicated. */
3675 if (flag_code == CODE_64BIT)
252b5132 3676 {
2ca3ace5
L		 3677 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3678 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3679 i.suffix);
3680 return 0;
252b5132 3681 }
29b0f896
AM		 3682#if REGISTER_WARNINGS
3683 else
a540244d
L		 3684 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3685 register_prefix,
29b0f896 3686 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3687 register_prefix,
29b0f896
AM		 3688 i.op[op].regs->reg_name,
3689 i.suffix);
3690#endif
252b5132 3691 }
29b0f896 3692 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3693 else if (i.types[op].bitfield.reg64
3694 && (i.tm.operand_types[op].bitfield.reg32
3695 || i.tm.operand_types[op].bitfield.acc))
252b5132 3696 {
34828aad 3697 if (intel_syntax
ca61edf2 3698 && i.tm.opcode_modifier.toqword
40fb9820 3699 && !i.types[0].bitfield.regxmm)
34828aad 3700 {
ca61edf2 3701 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3702 i.suffix = QWORD_MNEM_SUFFIX;
3703 }
3704 else
3705 {
3706 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3707 register_prefix, i.op[op].regs->reg_name,
3708 i.suffix);
3709 return 0;
3710 }
29b0f896
AM		 3711 }
3712 return 1;
3713}
252b5132 3714
29b0f896 3715static int
e3bb37b5 3716check_qword_reg (void)
29b0f896
AM		 3717{
3718 int op;
252b5132 3719
29b0f896
AM		 3720 for (op = i.operands; --op >= 0; )
3721 /* Reject eight bit registers, except where the template requires
3722 them. (eg. movzb) */
40fb9820
L		 3723 if (i.types[op].bitfield.reg8
3724 && (i.tm.operand_types[op].bitfield.reg16
3725 || i.tm.operand_types[op].bitfield.reg32
3726 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3727 {
a540244d
L		 3728 as_bad (_("`%s%s' not allowed with `%s%c'"),
3729 register_prefix,
29b0f896
AM		 3730 i.op[op].regs->reg_name,
3731 i.tm.name,
3732 i.suffix);
3733 return 0;
3734 }
3735 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3736 else if ((i.types[op].bitfield.reg16
3737 || i.types[op].bitfield.reg32)
3738 && (i.tm.operand_types[op].bitfield.reg32
3739 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3740 {
3741 /* Prohibit these changes in the 64bit mode, since the
3742 lowering is more complicated. */
34828aad 3743 if (intel_syntax
ca61edf2 3744 && i.tm.opcode_modifier.todword
40fb9820 3745 && !i.types[0].bitfield.regxmm)
34828aad 3746 {
ca61edf2 3747 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 3748 i.suffix = LONG_MNEM_SUFFIX;
3749 }
3750 else
3751 {
3752 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3753 register_prefix, i.op[op].regs->reg_name,
3754 i.suffix);
3755 return 0;
3756 }
252b5132 3757 }
29b0f896
AM		 3758 return 1;
3759}
252b5132 3760
29b0f896 3761static int
e3bb37b5 3762check_word_reg (void)
29b0f896
AM		 3763{
3764 int op;
3765 for (op = i.operands; --op >= 0;)
3766 /* Reject eight bit registers, except where the template requires
3767 them. (eg. movzb) */
40fb9820
L		 3768 if (i.types[op].bitfield.reg8
3769 && (i.tm.operand_types[op].bitfield.reg16
3770 || i.tm.operand_types[op].bitfield.reg32
3771 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3772 {
a540244d
L		 3773 as_bad (_("`%s%s' not allowed with `%s%c'"),
3774 register_prefix,
29b0f896
AM		 3775 i.op[op].regs->reg_name,
3776 i.tm.name,
3777 i.suffix);
3778 return 0;
3779 }
3780 /* Warn if the e prefix on a general reg is present. */
3781 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3782 && i.types[op].bitfield.reg32
3783 && (i.tm.operand_types[op].bitfield.reg16
3784 || i.tm.operand_types[op].bitfield.acc))
252b5132 3785 {
29b0f896
AM		 3786 /* Prohibit these changes in the 64bit mode, since the
3787 lowering is more complicated. */
3788 if (flag_code == CODE_64BIT)
252b5132 3789 {
2ca3ace5
L		 3790 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3791 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3792 i.suffix);
3793 return 0;
252b5132 3794 }
29b0f896
AM		 3795 else
3796#if REGISTER_WARNINGS
a540244d
L		 3797 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3798 register_prefix,
29b0f896 3799 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3800 register_prefix,
29b0f896
AM		 3801 i.op[op].regs->reg_name,
3802 i.suffix);
3803#endif
3804 }
3805 return 1;
3806}
252b5132 3807
29b0f896 3808static int
40fb9820 3809update_imm (unsigned int j)
29b0f896 3810{
40fb9820
L		 3811 i386_operand_type overlap;
3812
c6fb90c8 3813 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3814 if ((overlap.bitfield.imm8
3815 || overlap.bitfield.imm8s
3816 || overlap.bitfield.imm16
3817 || overlap.bitfield.imm32
3818 || overlap.bitfield.imm32s
3819 || overlap.bitfield.imm64)
c6fb90c8
L		 3820 && !UINTS_EQUAL (overlap, imm8)
3821 && !UINTS_EQUAL (overlap, imm8s)
3822 && !UINTS_EQUAL (overlap, imm16)
3823 && !UINTS_EQUAL (overlap, imm32)
3824 && !UINTS_EQUAL (overlap, imm32s)
3825 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3826 {
3827 if (i.suffix)
3828 {
40fb9820
L		 3829 i386_operand_type temp;
3830
c6fb90c8 3831 UINTS_CLEAR (temp);
40fb9820
L		 3832 if (i.suffix == BYTE_MNEM_SUFFIX)
3833 {
3834 temp.bitfield.imm8 = overlap.bitfield.imm8;
3835 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3836 }
3837 else if (i.suffix == WORD_MNEM_SUFFIX)
3838 temp.bitfield.imm16 = overlap.bitfield.imm16;
3839 else if (i.suffix == QWORD_MNEM_SUFFIX)
3840 {
3841 temp.bitfield.imm64 = overlap.bitfield.imm64;
3842 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3843 }
3844 else
3845 temp.bitfield.imm32 = overlap.bitfield.imm32;
3846 overlap = temp;
29b0f896 3847 }
c6fb90c8
L		 3848 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3849 || UINTS_EQUAL (overlap, imm16_32)
3850 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3851 {
c6fb90c8 3852 UINTS_CLEAR (overlap);
40fb9820
L		 3853 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3854 overlap.bitfield.imm16 = 1;
3855 else
3856 overlap.bitfield.imm32s = 1;
29b0f896 3857 }
c6fb90c8
L		 3858 if (!UINTS_EQUAL (overlap, imm8)
3859 && !UINTS_EQUAL (overlap, imm8s)
3860 && !UINTS_EQUAL (overlap, imm16)
3861 && !UINTS_EQUAL (overlap, imm32)
3862 && !UINTS_EQUAL (overlap, imm32s)
3863 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3864 {
4eed87de
AM		 3865 as_bad (_("no instruction mnemonic suffix given; "
3866 "can't determine immediate size"));
29b0f896
AM		 3867 return 0;
3868 }
3869 }
40fb9820 3870 i.types[j] = overlap;
29b0f896 3871
40fb9820
L		 3872 return 1;
3873}
3874
3875static int
3876finalize_imm (void)
3877{
3878 unsigned int j;
29b0f896 3879
40fb9820
L		 3880 for (j = 0; j < 2; j++)
3881 if (update_imm (j) == 0)
3882 return 0;
3883
c6fb90c8 3884 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3885 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3886
3887 return 1;
3888}
3889
85f10a01
MM		 3890static void
3891process_drex (void)
3892{
5dd15031
JJ		 3893 i.drex.modrm_reg = 0;
3894 i.drex.modrm_regmem = 0;
85f10a01
MM		 3895
3896 /* SSE5 4 operand instructions must have the destination the same as
3897 one of the inputs. Figure out the destination register and cache
3898 it away in the drex field, and remember which fields to use for
3899 the modrm byte. */
3900 if (i.tm.opcode_modifier.drex
3901 && i.tm.opcode_modifier.drexv
3902 && i.operands == 4)
3903 {
3904 i.tm.extension_opcode = None;
3905
3906 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3907 if (i.types[0].bitfield.regxmm != 0
3908 && i.types[1].bitfield.regxmm != 0
3909 && i.types[2].bitfield.regxmm != 0
3910 && i.types[3].bitfield.regxmm != 0
3911 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3912 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3913 {
3914 /* Clear the arguments that are stored in drex. */
3915 UINTS_CLEAR (i.types[0]);
3916 UINTS_CLEAR (i.types[3]);
3917 i.reg_operands -= 2;
3918
3919 /* There are two different ways to encode a 4 operand
3920 instruction with all registers that uses OC1 set to
3921 0 or 1. Favor setting OC1 to 0 since this mimics the
3922 actions of other SSE5 assemblers. Use modrm encoding 2
3923 for register/register. Include the high order bit that
3924 is normally stored in the REX byte in the register
3925 field. */
3926 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3927 i.drex.modrm_reg = 2;
3928 i.drex.modrm_regmem = 1;
3929 i.drex.reg = (i.op[3].regs->reg_num
3930 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3931 }
3932
3933 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3934 else if (i.types[0].bitfield.regxmm != 0
3935 && i.types[1].bitfield.regxmm != 0
3936 && (i.types[2].bitfield.regxmm
3937 || operand_type_check (i.types[2], anymem))
3938 && i.types[3].bitfield.regxmm != 0
3939 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3940 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3941 {
3942 /* clear the arguments that are stored in drex */
3943 UINTS_CLEAR (i.types[0]);
3944 UINTS_CLEAR (i.types[3]);
3945 i.reg_operands -= 2;
3946
3947 /* Specify the modrm encoding for memory addressing. Include
3948 the high order bit that is normally stored in the REX byte
3949 in the register field. */
3950 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3951 i.drex.modrm_reg = 1;
3952 i.drex.modrm_regmem = 2;
3953 i.drex.reg = (i.op[3].regs->reg_num
3954 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3955 }
3956
3957 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3958 else if (i.types[0].bitfield.regxmm != 0
3959 && operand_type_check (i.types[1], anymem) != 0
3960 && i.types[2].bitfield.regxmm != 0
3961 && i.types[3].bitfield.regxmm != 0
3962 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3963 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3964 {
3965 /* Clear the arguments that are stored in drex. */
3966 UINTS_CLEAR (i.types[0]);
3967 UINTS_CLEAR (i.types[3]);
3968 i.reg_operands -= 2;
3969
3970 /* Specify the modrm encoding for memory addressing. Include
3971 the high order bit that is normally stored in the REX byte
3972 in the register field. */
3973 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3974 i.drex.modrm_reg = 2;
3975 i.drex.modrm_regmem = 1;
3976 i.drex.reg = (i.op[3].regs->reg_num
3977 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3978 }
3979
3980 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3981 else if (i.types[0].bitfield.regxmm != 0
3982 && i.types[1].bitfield.regxmm != 0
3983 && i.types[2].bitfield.regxmm != 0
3984 && i.types[3].bitfield.regxmm != 0
3985 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3986 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3987 {
3988 /* clear the arguments that are stored in drex */
3989 UINTS_CLEAR (i.types[2]);
3990 UINTS_CLEAR (i.types[3]);
3991 i.reg_operands -= 2;
3992
3993 /* There are two different ways to encode a 4 operand
3994 instruction with all registers that uses OC1 set to
3995 0 or 1. Favor setting OC1 to 0 since this mimics the
3996 actions of other SSE5 assemblers. Use modrm encoding
3997 2 for register/register. Include the high order bit that
3998 is normally stored in the REX byte in the register
3999 field. */
4000 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4001 i.drex.modrm_reg = 1;
4002 i.drex.modrm_regmem = 0;
4003
4004 /* Remember the register, including the upper bits */
4005 i.drex.reg = (i.op[3].regs->reg_num
4006 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4007 }
4008
4009 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4010 else if (i.types[0].bitfield.regxmm != 0
4011 && (i.types[1].bitfield.regxmm
4012 || operand_type_check (i.types[1], anymem))
4013 && i.types[2].bitfield.regxmm != 0
4014 && i.types[3].bitfield.regxmm != 0
4015 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4016 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4017 {
4018 /* Clear the arguments that are stored in drex. */
4019 UINTS_CLEAR (i.types[2]);
4020 UINTS_CLEAR (i.types[3]);
4021 i.reg_operands -= 2;
4022
4023 /* Specify the modrm encoding and remember the register
4024 including the bits normally stored in the REX byte. */
4025 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4026 i.drex.modrm_reg = 0;
4027 i.drex.modrm_regmem = 1;
4028 i.drex.reg = (i.op[3].regs->reg_num
4029 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4030 }
4031
4032 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4033 else if (operand_type_check (i.types[0], anymem) != 0
4034 && i.types[1].bitfield.regxmm != 0
4035 && i.types[2].bitfield.regxmm != 0
4036 && i.types[3].bitfield.regxmm != 0
4037 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4038 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4039 {
4040 /* clear the arguments that are stored in drex */
4041 UINTS_CLEAR (i.types[2]);
4042 UINTS_CLEAR (i.types[3]);
4043 i.reg_operands -= 2;
4044
4045 /* Specify the modrm encoding and remember the register
4046 including the bits normally stored in the REX byte. */
4047 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4048 i.drex.modrm_reg = 1;
4049 i.drex.modrm_regmem = 0;
4050 i.drex.reg = (i.op[3].regs->reg_num
4051 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4052 }
4053
4054 else
4055 as_bad (_("Incorrect operands for the '%s' instruction"),
4056 i.tm.name);
4057 }
4058
4059 /* SSE5 instructions with the DREX byte where the only memory operand
4060 is in the 2nd argument, and the first and last xmm register must
4061 match, and is encoded in the DREX byte. */
4062 else if (i.tm.opcode_modifier.drex
4063 && !i.tm.opcode_modifier.drexv
4064 && i.operands == 4)
4065 {
4066 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4067 if (i.types[0].bitfield.regxmm != 0
4068 && (i.types[1].bitfield.regxmm
4069 || operand_type_check(i.types[1], anymem))
4070 && i.types[2].bitfield.regxmm != 0
4071 && i.types[3].bitfield.regxmm != 0
4072 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4073 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4074 {
4075 /* clear the arguments that are stored in drex */
4076 UINTS_CLEAR (i.types[0]);
4077 UINTS_CLEAR (i.types[3]);
4078 i.reg_operands -= 2;
4079
4080 /* Specify the modrm encoding and remember the register
4081 including the high bit normally stored in the REX
4082 byte. */
4083 i.drex.modrm_reg = 2;
4084 i.drex.modrm_regmem = 1;
4085 i.drex.reg = (i.op[3].regs->reg_num
4086 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4087 }
4088
4089 else
4090 as_bad (_("Incorrect operands for the '%s' instruction"),
4091 i.tm.name);
4092 }
4093
4094 /* SSE5 3 operand instructions that the result is a register, being
4095 either operand can be a memory operand, using OC0 to note which
4096 one is the memory. */
4097 else if (i.tm.opcode_modifier.drex
4098 && i.tm.opcode_modifier.drexv
4099 && i.operands == 3)
4100 {
4101 i.tm.extension_opcode = None;
4102
4103 /* Case 1: 3 operand insn, src1 = register. */
4104 if (i.types[0].bitfield.regxmm != 0
4105 && i.types[1].bitfield.regxmm != 0
4106 && i.types[2].bitfield.regxmm != 0)
4107 {
4108 /* Clear the arguments that are stored in drex. */
4109 UINTS_CLEAR (i.types[2]);
4110 i.reg_operands--;
4111
4112 /* Specify the modrm encoding and remember the register
4113 including the high bit normally stored in the REX byte. */
4114 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4115 i.drex.modrm_reg = 1;
4116 i.drex.modrm_regmem = 0;
4117 i.drex.reg = (i.op[2].regs->reg_num
4118 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4119 }
4120
4121 /* Case 2: 3 operand insn, src1 = memory. */
4122 else if (operand_type_check (i.types[0], anymem) != 0
4123 && i.types[1].bitfield.regxmm != 0
4124 && i.types[2].bitfield.regxmm != 0)
4125 {
4126 /* Clear the arguments that are stored in drex. */
4127 UINTS_CLEAR (i.types[2]);
4128 i.reg_operands--;
4129
4130 /* Specify the modrm encoding and remember the register
4131 including the high bit normally stored in the REX
4132 byte. */
4133 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4134 i.drex.modrm_reg = 1;
4135 i.drex.modrm_regmem = 0;
4136 i.drex.reg = (i.op[2].regs->reg_num
4137 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4138 }
4139
4140 /* Case 3: 3 operand insn, src2 = memory. */
4141 else if (i.types[0].bitfield.regxmm != 0
4142 && operand_type_check (i.types[1], anymem) != 0
4143 && i.types[2].bitfield.regxmm != 0)
4144 {
4145 /* Clear the arguments that are stored in drex. */
4146 UINTS_CLEAR (i.types[2]);
4147 i.reg_operands--;
4148
4149 /* Specify the modrm encoding and remember the register
4150 including the high bit normally stored in the REX byte. */
4151 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4152 i.drex.modrm_reg = 0;
4153 i.drex.modrm_regmem = 1;
4154 i.drex.reg = (i.op[2].regs->reg_num
4155 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4156 }
4157
4158 else
4159 as_bad (_("Incorrect operands for the '%s' instruction"),
4160 i.tm.name);
4161 }
4162
4163 /* SSE5 4 operand instructions that are the comparison instructions
4164 where the first operand is the immediate value of the comparison
4165 to be done. */
4166 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4167 {
4168 /* Case 1: 4 operand insn, src1 = reg/memory. */
4169 if (operand_type_check (i.types[0], imm) != 0
4170 && (i.types[1].bitfield.regxmm
4171 || operand_type_check (i.types[1], anymem))
4172 && i.types[2].bitfield.regxmm != 0
4173 && i.types[3].bitfield.regxmm != 0)
4174 {
4175 /* clear the arguments that are stored in drex */
4176 UINTS_CLEAR (i.types[3]);
4177 i.reg_operands--;
4178
4179 /* Specify the modrm encoding and remember the register
4180 including the high bit normally stored in the REX byte. */
4181 i.drex.modrm_reg = 2;
4182 i.drex.modrm_regmem = 1;
4183 i.drex.reg = (i.op[3].regs->reg_num
4184 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4185 }
4186
4187 /* Case 2: 3 operand insn with ImmExt that places the
4188 opcode_extension as an immediate argument. This is used for
4189 all of the varients of comparison that supplies the appropriate
4190 value as part of the instruction. */
4191 else if ((i.types[0].bitfield.regxmm
4192 || operand_type_check (i.types[0], anymem))
4193 && i.types[1].bitfield.regxmm != 0
4194 && i.types[2].bitfield.regxmm != 0
4195 && operand_type_check (i.types[3], imm) != 0)
4196 {
4197 /* clear the arguments that are stored in drex */
4198 UINTS_CLEAR (i.types[2]);
4199 i.reg_operands--;
4200
4201 /* Specify the modrm encoding and remember the register
4202 including the high bit normally stored in the REX byte. */
4203 i.drex.modrm_reg = 1;
4204 i.drex.modrm_regmem = 0;
4205 i.drex.reg = (i.op[2].regs->reg_num
4206 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4207 }
4208
4209 else
4210 as_bad (_("Incorrect operands for the '%s' instruction"),
4211 i.tm.name);
4212 }
4213
4214 else if (i.tm.opcode_modifier.drex
4215 || i.tm.opcode_modifier.drexv
4216 || i.tm.opcode_modifier.drexc)
4217 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4218}
4219
29b0f896 4220static int
e3bb37b5 4221process_operands (void)
29b0f896
AM		 4222{
4223 /* Default segment register this instruction will use for memory
4224 accesses. 0 means unknown. This is only for optimizing out
4225 unnecessary segment overrides. */
4226 const seg_entry *default_seg = 0;
4227
85f10a01
MM		 4228 /* Handle all of the DREX munging that SSE5 needs. */
4229 if (i.tm.opcode_modifier.drex
4230 || i.tm.opcode_modifier.drexv
4231 || i.tm.opcode_modifier.drexc)
4232 process_drex ();
4233
e2ec9d29 4234 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4235 {
9fcfb3d7
L		 4236 unsigned int j;
4237
e2ec9d29
L		 4238 /* The first operand is implicit and must be xmm0. */
4239 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4240 if (i.op[0].regs->reg_num != 0)
4241 {
4242 if (intel_syntax)
4243 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4244 i.tm.name, register_prefix);
4245 else
4246 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4247 i.tm.name, register_prefix);
4248 return 0;
4249 }
9fcfb3d7
L		 4250
4251 for (j = 1; j < i.operands; j++)
4252 {
4253 i.op[j - 1] = i.op[j];
4254 i.types[j - 1] = i.types[j];
4255
4256 /* We need to adjust fields in i.tm since they are used by
4257 build_modrm_byte. */
4258 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4259 }
4260
e2ec9d29
L		 4261 i.operands--;
4262 i.reg_operands--;
e2ec9d29
L		 4263 i.tm.operands--;
4264 }
4265 else if (i.tm.opcode_modifier.regkludge)
4266 {
4267 /* The imul $imm, %reg instruction is converted into
4268 imul $imm, %reg, %reg, and the clr %reg instruction
4269 is converted into xor %reg, %reg. */
4270
4271 unsigned int first_reg_op;
4272
4273 if (operand_type_check (i.types[0], reg))
4274 first_reg_op = 0;
4275 else
4276 first_reg_op = 1;
4277 /* Pretend we saw the extra register operand. */
4278 assert (i.reg_operands == 1
4279 && i.op[first_reg_op + 1].regs == 0);
4280 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4281 i.types[first_reg_op + 1] = i.types[first_reg_op];
4282 i.operands++;
4283 i.reg_operands++;
29b0f896
AM		 4284 }
4285
40fb9820 4286 if (i.tm.opcode_modifier.shortform)
29b0f896 4287 {
40fb9820
L		 4288 if (i.types[0].bitfield.sreg2
4289 || i.types[0].bitfield.sreg3)
29b0f896 4290 {
4eed87de
AM		 4291 if (i.tm.base_opcode == POP_SEG_SHORT
4292 && i.op[0].regs->reg_num == 1)
29b0f896 4293 {
4eed87de
AM		 4294 as_bad (_("you can't `pop %%cs'"));
4295 return 0;
29b0f896 4296 }
4eed87de
AM		 4297 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4298 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4299 i.rex |= REX_B;
4eed87de
AM		 4300 }
4301 else
4302 {
85f10a01
MM		 4303 /* The register or float register operand is in operand
4304 0 or 1. */
40fb9820
L		 4305 unsigned int op;
4306
4307 if (i.types[0].bitfield.floatreg
4308 || operand_type_check (i.types[0], reg))
4309 op = 0;
4310 else
4311 op = 1;
4eed87de
AM		 4312 /* Register goes in low 3 bits of opcode. */
4313 i.tm.base_opcode |= i.op[op].regs->reg_num;
4314 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4315 i.rex |= REX_B;
40fb9820 4316 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4317 {
4eed87de
AM		 4318 /* Warn about some common errors, but press on regardless.
4319 The first case can be generated by gcc (<= 2.8.1). */
4320 if (i.operands == 2)
4321 {
4322 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4323 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4324 register_prefix, i.op[1].regs->reg_name,
4325 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4326 }
4327 else
4328 {
4329 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4330 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4331 register_prefix, i.op[0].regs->reg_name);
4eed87de 4332 }
29b0f896
AM		 4333 }
4334 }
4335 }
40fb9820 4336 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4337 {
4338 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4339 must be put into the modrm byte). Now, we make the modrm and
4340 index base bytes based on all the info we've collected. */
29b0f896
AM		 4341
4342 default_seg = build_modrm_byte ();
4343 }
8a2ed489 4344 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4345 {
4346 default_seg = &ds;
4347 }
40fb9820 4348 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4349 {
4350 /* For the string instructions that allow a segment override
4351 on one of their operands, the default segment is ds. */
4352 default_seg = &ds;
4353 }
4354
75178d9d
L		 4355 if (i.tm.base_opcode == 0x8d /* lea */
4356 && i.seg[0]
4357 && !quiet_warnings)
30123838 4358 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4359
4360 /* If a segment was explicitly specified, and the specified segment
4361 is not the default, use an opcode prefix to select it. If we
4362 never figured out what the default segment is, then default_seg
4363 will be zero at this point, and the specified segment prefix will
4364 always be used. */
29b0f896
AM		 4365 if ((i.seg[0]) && (i.seg[0] != default_seg))
4366 {
4367 if (!add_prefix (i.seg[0]->seg_prefix))
4368 return 0;
4369 }
4370 return 1;
4371}
4372
4373static const seg_entry *
e3bb37b5 4374build_modrm_byte (void)
29b0f896
AM		 4375{
4376 const seg_entry *default_seg = 0;
4377
85f10a01
MM		 4378 /* SSE5 4 operand instructions are encoded in such a way that one of
4379 the inputs must match the destination register. Process_drex hides
4380 the 3rd argument in the drex field, so that by the time we get
4381 here, it looks to GAS as if this is a 2 operand instruction. */
4382 if ((i.tm.opcode_modifier.drex
4383 || i.tm.opcode_modifier.drexv
b5016f89 4384 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4385 && i.reg_operands == 2)
4386 {
4387 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4388 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4389
4390 i.rm.reg = reg->reg_num;
4391 i.rm.regmem = regmem->reg_num;
4392 i.rm.mode = 3;
4393 if ((reg->reg_flags & RegRex) != 0)
4394 i.rex |= REX_R;
4395 if ((regmem->reg_flags & RegRex) != 0)
4396 i.rex |= REX_B;
4397 }
4398
29b0f896
AM		 4399 /* i.reg_operands MUST be the number of real register operands;
4400 implicit registers do not count. */
85f10a01 4401 else if (i.reg_operands == 2)
29b0f896
AM		 4402 {
4403 unsigned int source, dest;
cab737b9
L		 4404
4405 switch (i.operands)
4406 {
4407 case 2:
4408 source = 0;
4409 break;
4410 case 3:
c81128dc
L		 4411 /* When there are 3 operands, one of them may be immediate,
4412 which may be the first or the last operand. Otherwise,
4413 the first operand must be shift count register (cl). */
4414 assert (i.imm_operands == 1
4415 || (i.imm_operands == 0
40fb9820
L		 4416 && i.types[0].bitfield.shiftcount));
4417 if (operand_type_check (i.types[0], imm)
4418 || i.types[0].bitfield.shiftcount)
4419 source = 1;
4420 else
4421 source = 0;
cab737b9
L		 4422 break;
4423 case 4:
368d64cc
L		 4424 /* When there are 4 operands, the first two must be 8bit
4425 immediate operands. The source operand will be the 3rd
4426 one. */
cab737b9 4427 assert (i.imm_operands == 2
368d64cc
L		 4428 && i.types[0].bitfield.imm8
4429 && i.types[1].bitfield.imm8);
cab737b9
L		 4430 source = 2;
4431 break;
4432 default:
4433 abort ();
4434 }
4435
29b0f896
AM		 4436 dest = source + 1;
4437
4438 i.rm.mode = 3;
4439 /* One of the register operands will be encoded in the i.tm.reg
4440 field, the other in the combined i.tm.mode and i.tm.regmem
4441 fields. If no form of this instruction supports a memory
4442 destination operand, then we assume the source operand may
4443 sometimes be a memory operand and so we need to store the
4444 destination in the i.rm.reg field. */
40fb9820
L		 4445 if (!i.tm.operand_types[dest].bitfield.regmem
4446 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4447 {
4448 i.rm.reg = i.op[dest].regs->reg_num;
4449 i.rm.regmem = i.op[source].regs->reg_num;
4450 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4451 i.rex |= REX_R;
29b0f896 4452 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4453 i.rex |= REX_B;
29b0f896
AM		 4454 }
4455 else
4456 {
4457 i.rm.reg = i.op[source].regs->reg_num;
4458 i.rm.regmem = i.op[dest].regs->reg_num;
4459 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4460 i.rex |= REX_B;
29b0f896 4461 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4462 i.rex |= REX_R;
29b0f896 4463 }
161a04f6 4464 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4465 {
40fb9820
L		 4466 if (!i.types[0].bitfield.control
4467 && !i.types[1].bitfield.control)
c4a530c5 4468 abort ();
161a04f6 4469 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4470 add_prefix (LOCK_PREFIX_OPCODE);
4471 }
29b0f896
AM		 4472 }
4473 else
4474 { /* If it's not 2 reg operands... */
4475 if (i.mem_operands)
4476 {
4477 unsigned int fake_zero_displacement = 0;
99018f42 4478 unsigned int op;
4eed87de 4479
85f10a01
MM		 4480 /* This has been precalculated for SSE5 instructions
4481 that have a DREX field earlier in process_drex. */
b5016f89
L		 4482 if (i.tm.opcode_modifier.drex
4483 || i.tm.opcode_modifier.drexv
4484 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4485 op = i.drex.modrm_regmem;
4486 else
4487 {
c0209578
L		 4488 for (op = 0; op < i.operands; op++)
4489 if (operand_type_check (i.types[op], anymem))
4490 break;
4491 assert (op < i.operands);
85f10a01 4492 }
29b0f896
AM		 4493
4494 default_seg = &ds;
4495
4496 if (i.base_reg == 0)
4497 {
4498 i.rm.mode = 0;
4499 if (!i.disp_operands)
4500 fake_zero_displacement = 1;
4501 if (i.index_reg == 0)
4502 {
4503 /* Operand is just <disp> */
20f0a1fc 4504 if (flag_code == CODE_64BIT)
29b0f896
AM		 4505 {
4506 /* 64bit mode overwrites the 32bit absolute
4507 addressing by RIP relative addressing and
4508 absolute addressing is encoded by one of the
4509 redundant SIB forms. */
4510 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4511 i.sib.base = NO_BASE_REGISTER;
4512 i.sib.index = NO_INDEX_REGISTER;
fc225355 4513 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4514 ? disp32s : disp32);
20f0a1fc 4515 }
fc225355
L		 4516 else if ((flag_code == CODE_16BIT)
4517 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4518 {
4519 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4520 i.types[op] = disp16;
20f0a1fc
NC		 4521 }
4522 else
4523 {
4524 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4525 i.types[op] = disp32;
29b0f896
AM		 4526 }
4527 }
4528 else /* !i.base_reg && i.index_reg */
4529 {
db51cc60
L		 4530 if (i.index_reg->reg_num == RegEiz
4531 || i.index_reg->reg_num == RegRiz)
4532 i.sib.index = NO_INDEX_REGISTER;
4533 else
4534 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4535 i.sib.base = NO_BASE_REGISTER;
4536 i.sib.scale = i.log2_scale_factor;
4537 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4538 i.types[op].bitfield.disp8 = 0;
4539 i.types[op].bitfield.disp16 = 0;
4540 i.types[op].bitfield.disp64 = 0;
29b0f896 4541 if (flag_code != CODE_64BIT)
40fb9820
L		 4542 {
4543 /* Must be 32 bit */
4544 i.types[op].bitfield.disp32 = 1;
4545 i.types[op].bitfield.disp32s = 0;
4546 }
29b0f896 4547 else
40fb9820
L		 4548 {
4549 i.types[op].bitfield.disp32 = 0;
4550 i.types[op].bitfield.disp32s = 1;
4551 }
29b0f896 4552 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4553 i.rex |= REX_X;
29b0f896
AM		 4554 }
4555 }
4556 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4557 else if (i.base_reg->reg_num == RegRip ||
4558 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4559 {
4560 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4561 i.types[op].bitfield.disp8 = 0;
4562 i.types[op].bitfield.disp16 = 0;
4563 i.types[op].bitfield.disp32 = 0;
4564 i.types[op].bitfield.disp32s = 1;
4565 i.types[op].bitfield.disp64 = 0;
71903a11 4566 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4567 if (! i.disp_operands)
4568 fake_zero_displacement = 1;
29b0f896 4569 }
40fb9820 4570 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4571 {
4572 switch (i.base_reg->reg_num)
4573 {
4574 case 3: /* (%bx) */
4575 if (i.index_reg == 0)
4576 i.rm.regmem = 7;
4577 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4578 i.rm.regmem = i.index_reg->reg_num - 6;
4579 break;
4580 case 5: /* (%bp) */
4581 default_seg = &ss;
4582 if (i.index_reg == 0)
4583 {
4584 i.rm.regmem = 6;
40fb9820 4585 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4586 {
4587 /* fake (%bp) into 0(%bp) */
40fb9820 4588 i.types[op].bitfield.disp8 = 1;
252b5132 4589 fake_zero_displacement = 1;
29b0f896
AM		 4590 }
4591 }
4592 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4593 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4594 break;
4595 default: /* (%si) -> 4 or (%di) -> 5 */
4596 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4597 }
4598 i.rm.mode = mode_from_disp_size (i.types[op]);
4599 }
4600 else /* i.base_reg and 32/64 bit mode */
4601 {
4602 if (flag_code == CODE_64BIT
40fb9820
L		 4603 && operand_type_check (i.types[op], disp))
4604 {
4605 i386_operand_type temp;
c6fb90c8 4606 UINTS_CLEAR (temp);
40fb9820
L		 4607 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4608 i.types[op] = temp;
4609 if (i.prefix[ADDR_PREFIX] == 0)
4610 i.types[op].bitfield.disp32s = 1;
4611 else
4612 i.types[op].bitfield.disp32 = 1;
4613 }
20f0a1fc 4614
29b0f896
AM		 4615 i.rm.regmem = i.base_reg->reg_num;
4616 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4617 i.rex |= REX_B;
29b0f896
AM		 4618 i.sib.base = i.base_reg->reg_num;
4619 /* x86-64 ignores REX prefix bit here to avoid decoder
4620 complications. */
4621 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4622 {
4623 default_seg = &ss;
4624 if (i.disp_operands == 0)
4625 {
4626 fake_zero_displacement = 1;
40fb9820 4627 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4628 }
4629 }
4630 else if (i.base_reg->reg_num == ESP_REG_NUM)
4631 {
4632 default_seg = &ss;
4633 }
4634 i.sib.scale = i.log2_scale_factor;
4635 if (i.index_reg == 0)
4636 {
4637 /* <disp>(%esp) becomes two byte modrm with no index
4638 register. We've already stored the code for esp
4639 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4640 Any base register besides %esp will not use the
4641 extra modrm byte. */
4642 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4643 }
4644 else
4645 {
db51cc60
L		 4646 if (i.index_reg->reg_num == RegEiz
4647 || i.index_reg->reg_num == RegRiz)
4648 i.sib.index = NO_INDEX_REGISTER;
4649 else
4650 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4651 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4652 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4653 i.rex |= REX_X;
29b0f896 4654 }
67a4f2b7
AO		 4655
4656 if (i.disp_operands
4657 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4658 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4659 i.rm.mode = 0;
4660 else
4661 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4662 }
252b5132 4663
29b0f896
AM		 4664 if (fake_zero_displacement)
4665 {
4666 /* Fakes a zero displacement assuming that i.types[op]
4667 holds the correct displacement size. */
4668 expressionS *exp;
4669
4670 assert (i.op[op].disps == 0);
4671 exp = &disp_expressions[i.disp_operands++];
4672 i.op[op].disps = exp;
4673 exp->X_op = O_constant;
4674 exp->X_add_number = 0;
4675 exp->X_add_symbol = (symbolS *) 0;
4676 exp->X_op_symbol = (symbolS *) 0;
4677 }
4678 }
252b5132 4679
29b0f896
AM		 4680 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4681 (if any) based on i.tm.extension_opcode. Again, we must be
4682 careful to make sure that segment/control/debug/test/MMX
4683 registers are coded into the i.rm.reg field. */
4684 if (i.reg_operands)
4685 {
99018f42
L		 4686 unsigned int op;
4687
85f10a01
MM		 4688 /* This has been precalculated for SSE5 instructions
4689 that have a DREX field earlier in process_drex. */
b5016f89
L		 4690 if (i.tm.opcode_modifier.drex
4691 || i.tm.opcode_modifier.drexv
4692 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4693 {
4694 op = i.drex.modrm_reg;
4695 i.rm.reg = i.op[op].regs->reg_num;
4696 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4697 i.rex |= REX_R;
4698 }
4699 else
4700 {
c0209578
L		 4701 for (op = 0; op < i.operands; op++)
4702 if (i.types[op].bitfield.reg8
4703 || i.types[op].bitfield.reg16
4704 || i.types[op].bitfield.reg32
4705 || i.types[op].bitfield.reg64
4706 || i.types[op].bitfield.regmmx
4707 || i.types[op].bitfield.regxmm
4708 || i.types[op].bitfield.sreg2
4709 || i.types[op].bitfield.sreg3
4710 || i.types[op].bitfield.control
4711 || i.types[op].bitfield.debug
4712 || i.types[op].bitfield.test)
4713 break;
4714
4715 assert (op < i.operands);
99018f42 4716
85f10a01
MM		 4717 /* If there is an extension opcode to put here, the
4718 register number must be put into the regmem field. */
c0209578
L		 4719 if (i.tm.extension_opcode != None)
4720 {
4721 i.rm.regmem = i.op[op].regs->reg_num;
4722 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4723 i.rex |= REX_B;
4724 }
4725 else
4726 {
4727 i.rm.reg = i.op[op].regs->reg_num;
4728 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4729 i.rex |= REX_R;
4730 }
85f10a01 4731 }
252b5132 4732
29b0f896
AM		 4733 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4734 must set it to 3 to indicate this is a register operand
4735 in the regmem field. */
4736 if (!i.mem_operands)
4737 i.rm.mode = 3;
4738 }
252b5132 4739
29b0f896 4740 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4741 if (i.tm.extension_opcode != None
4742 && !(i.tm.opcode_modifier.drex
4743 || i.tm.opcode_modifier.drexv
4744 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4745 i.rm.reg = i.tm.extension_opcode;
4746 }
4747 return default_seg;
4748}
252b5132 4749
29b0f896 4750static void
e3bb37b5 4751output_branch (void)
29b0f896
AM		 4752{
4753 char *p;
4754 int code16;
4755 int prefix;
4756 relax_substateT subtype;
4757 symbolS *sym;
4758 offsetT off;
4759
4760 code16 = 0;
4761 if (flag_code == CODE_16BIT)
4762 code16 = CODE16;
4763
4764 prefix = 0;
4765 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4766 {
29b0f896
AM		 4767 prefix = 1;
4768 i.prefixes -= 1;
4769 code16 ^= CODE16;
252b5132 4770 }
29b0f896
AM		 4771 /* Pentium4 branch hints. */
4772 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4773 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4774 {
29b0f896
AM		 4775 prefix++;
4776 i.prefixes--;
4777 }
4778 if (i.prefix[REX_PREFIX] != 0)
4779 {
4780 prefix++;
4781 i.prefixes--;
2f66722d
AM		 4782 }
4783
29b0f896
AM		 4784 if (i.prefixes != 0 && !intel_syntax)
4785 as_warn (_("skipping prefixes on this instruction"));
4786
4787 /* It's always a symbol; End frag & setup for relax.
4788 Make sure there is enough room in this frag for the largest
4789 instruction we may generate in md_convert_frag. This is 2
4790 bytes for the opcode and room for the prefix and largest
4791 displacement. */
4792 frag_grow (prefix + 2 + 4);
4793 /* Prefix and 1 opcode byte go in fr_fix. */
4794 p = frag_more (prefix + 1);
4795 if (i.prefix[DATA_PREFIX] != 0)
4796 *p++ = DATA_PREFIX_OPCODE;
4797 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4798 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4799 *p++ = i.prefix[SEG_PREFIX];
4800 if (i.prefix[REX_PREFIX] != 0)
4801 *p++ = i.prefix[REX_PREFIX];
4802 *p = i.tm.base_opcode;
4803
4804 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4805 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4806 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4807 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4808 else
4809 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4810 subtype |= code16;
3e73aa7c 4811
29b0f896
AM		 4812 sym = i.op[0].disps->X_add_symbol;
4813 off = i.op[0].disps->X_add_number;
3e73aa7c 4814
29b0f896
AM		 4815 if (i.op[0].disps->X_op != O_constant
4816 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4817 {
29b0f896
AM		 4818 /* Handle complex expressions. */
4819 sym = make_expr_symbol (i.op[0].disps);
4820 off = 0;
4821 }
3e73aa7c 4822
29b0f896
AM		 4823 /* 1 possible extra opcode + 4 byte displacement go in var part.
4824 Pass reloc in fr_var. */
4825 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4826}
3e73aa7c 4827
29b0f896 4828static void
e3bb37b5 4829output_jump (void)
29b0f896
AM		 4830{
4831 char *p;
4832 int size;
3e02c1cc 4833 fixS *fixP;
29b0f896 4834
40fb9820 4835 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4836 {
4837 /* This is a loop or jecxz type instruction. */
4838 size = 1;
4839 if (i.prefix[ADDR_PREFIX] != 0)
4840 {
4841 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4842 i.prefixes -= 1;
4843 }
4844 /* Pentium4 branch hints. */
4845 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4846 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4847 {
4848 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4849 i.prefixes--;
3e73aa7c
JH		 4850 }
4851 }
29b0f896
AM		 4852 else
4853 {
4854 int code16;
3e73aa7c 4855
29b0f896
AM		 4856 code16 = 0;
4857 if (flag_code == CODE_16BIT)
4858 code16 = CODE16;
3e73aa7c 4859
29b0f896
AM		 4860 if (i.prefix[DATA_PREFIX] != 0)
4861 {
4862 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4863 i.prefixes -= 1;
4864 code16 ^= CODE16;
4865 }
252b5132 4866
29b0f896
AM		 4867 size = 4;
4868 if (code16)
4869 size = 2;
4870 }
9fcc94b6 4871
29b0f896
AM		 4872 if (i.prefix[REX_PREFIX] != 0)
4873 {
4874 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4875 i.prefixes -= 1;
4876 }
252b5132 4877
29b0f896
AM		 4878 if (i.prefixes != 0 && !intel_syntax)
4879 as_warn (_("skipping prefixes on this instruction"));
e0890092 4880
29b0f896
AM		 4881 p = frag_more (1 + size);
4882 *p++ = i.tm.base_opcode;
e0890092 4883
3e02c1cc
AM		 4884 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4885 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4886
4887 /* All jumps handled here are signed, but don't use a signed limit
4888 check for 32 and 16 bit jumps as we want to allow wrap around at
4889 4G and 64k respectively. */
4890 if (size == 1)
4891 fixP->fx_signed = 1;
29b0f896 4892}
e0890092 4893
29b0f896 4894static void
e3bb37b5 4895output_interseg_jump (void)
29b0f896
AM		 4896{
4897 char *p;
4898 int size;
4899 int prefix;
4900 int code16;
252b5132 4901
29b0f896
AM		 4902 code16 = 0;
4903 if (flag_code == CODE_16BIT)
4904 code16 = CODE16;
a217f122 4905
29b0f896
AM		 4906 prefix = 0;
4907 if (i.prefix[DATA_PREFIX] != 0)
4908 {
4909 prefix = 1;
4910 i.prefixes -= 1;
4911 code16 ^= CODE16;
4912 }
4913 if (i.prefix[REX_PREFIX] != 0)
4914 {
4915 prefix++;
4916 i.prefixes -= 1;
4917 }
252b5132 4918
29b0f896
AM		 4919 size = 4;
4920 if (code16)
4921 size = 2;
252b5132 4922
29b0f896
AM		 4923 if (i.prefixes != 0 && !intel_syntax)
4924 as_warn (_("skipping prefixes on this instruction"));
252b5132 4925
29b0f896
AM		 4926 /* 1 opcode; 2 segment; offset */
4927 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4928
29b0f896
AM		 4929 if (i.prefix[DATA_PREFIX] != 0)
4930 *p++ = DATA_PREFIX_OPCODE;
252b5132 4931
29b0f896
AM		 4932 if (i.prefix[REX_PREFIX] != 0)
4933 *p++ = i.prefix[REX_PREFIX];
252b5132 4934
29b0f896
AM		 4935 *p++ = i.tm.base_opcode;
4936 if (i.op[1].imms->X_op == O_constant)
4937 {
4938 offsetT n = i.op[1].imms->X_add_number;
252b5132 4939
29b0f896
AM		 4940 if (size == 2
4941 && !fits_in_unsigned_word (n)
4942 && !fits_in_signed_word (n))
4943 {
4944 as_bad (_("16-bit jump out of range"));
4945 return;
4946 }
4947 md_number_to_chars (p, n, size);
4948 }
4949 else
4950 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4951 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4952 if (i.op[0].imms->X_op != O_constant)
4953 as_bad (_("can't handle non absolute segment in `%s'"),
4954 i.tm.name);
4955 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4956}
a217f122 4957
29b0f896 4958static void
e3bb37b5 4959output_insn (void)
29b0f896 4960{
2bbd9c25
JJ		 4961 fragS *insn_start_frag;
4962 offsetT insn_start_off;
4963
29b0f896
AM		 4964 /* Tie dwarf2 debug info to the address at the start of the insn.
4965 We can't do this after the insn has been output as the current
4966 frag may have been closed off. eg. by frag_var. */
4967 dwarf2_emit_insn (0);
4968
2bbd9c25
JJ		 4969 insn_start_frag = frag_now;
4970 insn_start_off = frag_now_fix ();
4971
29b0f896 4972 /* Output jumps. */
40fb9820 4973 if (i.tm.opcode_modifier.jump)
29b0f896 4974 output_branch ();
40fb9820
L		 4975 else if (i.tm.opcode_modifier.jumpbyte
4976 || i.tm.opcode_modifier.jumpdword)
29b0f896 4977 output_jump ();
40fb9820 4978 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 4979 output_interseg_jump ();
4980 else
4981 {
4982 /* Output normal instructions here. */
4983 char *p;
4984 unsigned char *q;
47465058 4985 unsigned int j;
331d2d0d 4986 unsigned int prefix;
4dffcebc
L		 4987
4988 switch (i.tm.opcode_length)
bc4bd9ab 4989 {
4dffcebc 4990 case 3:
331d2d0d
L		 4991 if (i.tm.base_opcode & 0xff000000)
4992 {
4993 prefix = (i.tm.base_opcode >> 24) & 0xff;
4994 goto check_prefix;
4995 }
4dffcebc
L		 4996 break;
4997 case 2:
4998 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 4999 {
4dffcebc
L		 5000 prefix = (i.tm.base_opcode >> 16) & 0xff;
5001 if (i.tm.cpu_flags.bitfield.cpupadlock)
5002 {
5003check_prefix:
5004 if (prefix != REPE_PREFIX_OPCODE
5005 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5006 add_prefix (prefix);
5007 }
5008 else
bc4bd9ab
MK		 5009 add_prefix (prefix);
5010 }
4dffcebc
L		 5011 break;
5012 case 1:
5013 break;
5014 default:
5015 abort ();
0f10071e 5016 }
252b5132 5017
29b0f896 5018 /* The prefix bytes. */
47465058
L		 5019 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5020 if (*q)
5021 FRAG_APPEND_1_CHAR (*q);
252b5132 5022
29b0f896 5023 /* Now the opcode; be careful about word order here! */
4dffcebc 5024 if (i.tm.opcode_length == 1)
29b0f896
AM		 5025 {
5026 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5027 }
5028 else
5029 {
4dffcebc 5030 switch (i.tm.opcode_length)
331d2d0d 5031 {
4dffcebc 5032 case 3:
331d2d0d
L		 5033 p = frag_more (3);
5034 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5035 break;
5036 case 2:
5037 p = frag_more (2);
5038 break;
5039 default:
5040 abort ();
5041 break;
331d2d0d 5042 }
0f10071e 5043
29b0f896
AM		 5044 /* Put out high byte first: can't use md_number_to_chars! */
5045 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5046 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5047
5048 /* On SSE5, encode the OC1 bit in the DREX field if this
5049 encoding has multiple formats. */
5050 if (i.tm.opcode_modifier.drex
5051 && i.tm.opcode_modifier.drexv
5052 && DREX_OC1 (i.tm.extension_opcode))
5053 *p |= DREX_OC1_MASK;
29b0f896 5054 }
3e73aa7c 5055
29b0f896 5056 /* Now the modrm byte and sib byte (if present). */
40fb9820 5057 if (i.tm.opcode_modifier.modrm)
29b0f896 5058 {
4a3523fa
L		 5059 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5060 | i.rm.reg << 3
5061 | i.rm.mode << 6));
29b0f896
AM		 5062 /* If i.rm.regmem == ESP (4)
5063 && i.rm.mode != (Register mode)
5064 && not 16 bit
5065 ==> need second modrm byte. */
5066 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5067 && i.rm.mode != 3
40fb9820 5068 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5069 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5070 | i.sib.index << 3
5071 | i.sib.scale << 6));
29b0f896 5072 }
3e73aa7c 5073
85f10a01
MM		 5074 /* Write the DREX byte if needed. */
5075 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5076 {
5077 p = frag_more (1);
5078 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5079
5080 /* Encode the OC0 bit if this encoding has multiple
5081 formats. */
5082 if ((i.tm.opcode_modifier.drex
5083 || i.tm.opcode_modifier.drexv)
5084 && DREX_OC0 (i.tm.extension_opcode))
5085 *p |= DREX_OC0_MASK;
5086 }
5087
29b0f896 5088 if (i.disp_operands)
2bbd9c25 5089 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5090
29b0f896 5091 if (i.imm_operands)
2bbd9c25 5092 output_imm (insn_start_frag, insn_start_off);
29b0f896 5093 }
252b5132 5094
29b0f896
AM		 5095#ifdef DEBUG386
5096 if (flag_debug)
5097 {
7b81dfbb 5098 pi ("" /*line*/, &i);
29b0f896
AM		 5099 }
5100#endif /* DEBUG386 */
5101}
252b5132 5102
e205caa7
L		 5103/* Return the size of the displacement operand N. */
5104
5105static int
5106disp_size (unsigned int n)
5107{
5108 int size = 4;
40fb9820
L		 5109 if (i.types[n].bitfield.disp64)
5110 size = 8;
5111 else if (i.types[n].bitfield.disp8)
5112 size = 1;
5113 else if (i.types[n].bitfield.disp16)
5114 size = 2;
e205caa7
L		 5115 return size;
5116}
5117
5118/* Return the size of the immediate operand N. */
5119
5120static int
5121imm_size (unsigned int n)
5122{
5123 int size = 4;
40fb9820
L		 5124 if (i.types[n].bitfield.imm64)
5125 size = 8;
5126 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5127 size = 1;
5128 else if (i.types[n].bitfield.imm16)
5129 size = 2;
e205caa7
L		 5130 return size;
5131}
5132
29b0f896 5133static void
64e74474 5134output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5135{
5136 char *p;
5137 unsigned int n;
252b5132 5138
29b0f896
AM		 5139 for (n = 0; n < i.operands; n++)
5140 {
40fb9820 5141 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5142 {
5143 if (i.op[n].disps->X_op == O_constant)
5144 {
e205caa7 5145 int size = disp_size (n);
29b0f896 5146 offsetT val;
252b5132 5147
29b0f896
AM		 5148 val = offset_in_range (i.op[n].disps->X_add_number,
5149 size);
5150 p = frag_more (size);
5151 md_number_to_chars (p, val, size);
5152 }
5153 else
5154 {
f86103b7 5155 enum bfd_reloc_code_real reloc_type;
e205caa7 5156 int size = disp_size (n);
40fb9820 5157 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5158 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5159
e205caa7 5160 /* We can't have 8 bit displacement here. */
40fb9820 5161 assert (!i.types[n].bitfield.disp8);
e205caa7 5162
29b0f896
AM		 5163 /* The PC relative address is computed relative
5164 to the instruction boundary, so in case immediate
5165 fields follows, we need to adjust the value. */
5166 if (pcrel && i.imm_operands)
5167 {
29b0f896 5168 unsigned int n1;
e205caa7 5169 int sz = 0;
252b5132 5170
29b0f896 5171 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5172 if (operand_type_check (i.types[n1], imm))
252b5132 5173 {
e205caa7
L		 5174 /* Only one immediate is allowed for PC
5175 relative address. */
5176 assert (sz == 0);
5177 sz = imm_size (n1);
5178 i.op[n].disps->X_add_number -= sz;
252b5132 5179 }
29b0f896 5180 /* We should find the immediate. */
e205caa7 5181 assert (sz != 0);
29b0f896 5182 }
520dc8e8 5183
29b0f896 5184 p = frag_more (size);
2bbd9c25 5185 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5186 if (GOT_symbol
2bbd9c25 5187 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5188 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5189 || reloc_type == BFD_RELOC_X86_64_32S
5190 || (reloc_type == BFD_RELOC_64
5191 && object_64bit))
d6ab8113
JB		 5192 && (i.op[n].disps->X_op == O_symbol
5193 || (i.op[n].disps->X_op == O_add
5194 && ((symbol_get_value_expression
5195 (i.op[n].disps->X_op_symbol)->X_op)
5196 == O_subtract))))
5197 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5198 {
5199 offsetT add;
5200
5201 if (insn_start_frag == frag_now)
5202 add = (p - frag_now->fr_literal) - insn_start_off;
5203 else
5204 {
5205 fragS *fr;
5206
5207 add = insn_start_frag->fr_fix - insn_start_off;
5208 for (fr = insn_start_frag->fr_next;
5209 fr && fr != frag_now; fr = fr->fr_next)
5210 add += fr->fr_fix;
5211 add += p - frag_now->fr_literal;
5212 }
5213
4fa24527 5214 if (!object_64bit)
7b81dfbb
AJ		 5215 {
5216 reloc_type = BFD_RELOC_386_GOTPC;
5217 i.op[n].imms->X_add_number += add;
5218 }
5219 else if (reloc_type == BFD_RELOC_64)
5220 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5221 else
7b81dfbb
AJ		 5222 /* Don't do the adjustment for x86-64, as there
5223 the pcrel addressing is relative to the _next_
5224 insn, and that is taken care of in other code. */
d6ab8113 5225 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5226 }
062cd5e7 5227 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5228 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5229 }
5230 }
5231 }
5232}
252b5132 5233
29b0f896 5234static void
64e74474 5235output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5236{
5237 char *p;
5238 unsigned int n;
252b5132 5239
29b0f896
AM		 5240 for (n = 0; n < i.operands; n++)
5241 {
40fb9820 5242 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5243 {
5244 if (i.op[n].imms->X_op == O_constant)
5245 {
e205caa7 5246 int size = imm_size (n);
29b0f896 5247 offsetT val;
b4cac588 5248
29b0f896
AM		 5249 val = offset_in_range (i.op[n].imms->X_add_number,
5250 size);
5251 p = frag_more (size);
5252 md_number_to_chars (p, val, size);
5253 }
5254 else
5255 {
5256 /* Not absolute_section.
5257 Need a 32-bit fixup (don't support 8bit
5258 non-absolute imms). Try to support other
5259 sizes ... */
f86103b7 5260 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5261 int size = imm_size (n);
5262 int sign;
29b0f896 5263
40fb9820 5264 if (i.types[n].bitfield.imm32s
a7d61044 5265 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5266 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5267 sign = 1;
e205caa7
L		 5268 else
5269 sign = 0;
520dc8e8 5270
29b0f896
AM		 5271 p = frag_more (size);
5272 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5273
2bbd9c25
JJ		 5274 /* This is tough to explain. We end up with this one if we
5275 * have operands that look like
5276 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5277 * obtain the absolute address of the GOT, and it is strongly
5278 * preferable from a performance point of view to avoid using
5279 * a runtime relocation for this. The actual sequence of
5280 * instructions often look something like:
5281 *
5282 * call .L66
5283 * .L66:
5284 * popl %ebx
5285 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5286 *
5287 * The call and pop essentially return the absolute address
5288 * of the label .L66 and store it in %ebx. The linker itself
5289 * will ultimately change the first operand of the addl so
5290 * that %ebx points to the GOT, but to keep things simple, the
5291 * .o file must have this operand set so that it generates not
5292 * the absolute address of .L66, but the absolute address of
5293 * itself. This allows the linker itself simply treat a GOTPC
5294 * relocation as asking for a pcrel offset to the GOT to be
5295 * added in, and the addend of the relocation is stored in the
5296 * operand field for the instruction itself.
5297 *
5298 * Our job here is to fix the operand so that it would add
5299 * the correct offset so that %ebx would point to itself. The
5300 * thing that is tricky is that .-.L66 will point to the
5301 * beginning of the instruction, so we need to further modify
5302 * the operand so that it will point to itself. There are
5303 * other cases where you have something like:
5304 *
5305 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5306 *
5307 * and here no correction would be required. Internally in
5308 * the assembler we treat operands of this form as not being
5309 * pcrel since the '.' is explicitly mentioned, and I wonder
5310 * whether it would simplify matters to do it this way. Who
5311 * knows. In earlier versions of the PIC patches, the
5312 * pcrel_adjust field was used to store the correction, but
5313 * since the expression is not pcrel, I felt it would be
5314 * confusing to do it this way. */
5315
d6ab8113 5316 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5317 || reloc_type == BFD_RELOC_X86_64_32S
5318 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5319 && GOT_symbol
5320 && GOT_symbol == i.op[n].imms->X_add_symbol
5321 && (i.op[n].imms->X_op == O_symbol
5322 || (i.op[n].imms->X_op == O_add
5323 && ((symbol_get_value_expression
5324 (i.op[n].imms->X_op_symbol)->X_op)
5325 == O_subtract))))
5326 {
2bbd9c25
JJ		 5327 offsetT add;
5328
5329 if (insn_start_frag == frag_now)
5330 add = (p - frag_now->fr_literal) - insn_start_off;
5331 else
5332 {
5333 fragS *fr;
5334
5335 add = insn_start_frag->fr_fix - insn_start_off;
5336 for (fr = insn_start_frag->fr_next;
5337 fr && fr != frag_now; fr = fr->fr_next)
5338 add += fr->fr_fix;
5339 add += p - frag_now->fr_literal;
5340 }
5341
4fa24527 5342 if (!object_64bit)
d6ab8113 5343 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5344 else if (size == 4)
d6ab8113 5345 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5346 else if (size == 8)
5347 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5348 i.op[n].imms->X_add_number += add;
29b0f896 5349 }
29b0f896
AM		 5350 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5351 i.op[n].imms, 0, reloc_type);
5352 }
5353 }
5354 }
252b5132
RH		 5355}
5356\f
d182319b
JB		 5357/* x86_cons_fix_new is called via the expression parsing code when a
5358 reloc is needed. We use this hook to get the correct .got reloc. */
5359static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5360static int cons_sign = -1;
5361
5362void
e3bb37b5 5363x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5364 expressionS *exp)
d182319b
JB		 5365{
5366 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5367
5368 got_reloc = NO_RELOC;
5369
5370#ifdef TE_PE
5371 if (exp->X_op == O_secrel)
5372 {
5373 exp->X_op = O_symbol;
5374 r = BFD_RELOC_32_SECREL;
5375 }
5376#endif
5377
5378 fix_new_exp (frag, off, len, exp, 0, r);
5379}
5380
718ddfc0
JB		 5381#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5382# define lex_got(reloc, adjust, types) NULL
5383#else
f3c180ae
AM		 5384/* Parse operands of the form
5385 <symbol>@GOTOFF+<nnn>
5386 and similar .plt or .got references.
5387
5388 If we find one, set up the correct relocation in RELOC and copy the
5389 input string, minus the `@GOTOFF' into a malloc'd buffer for
5390 parsing by the calling routine. Return this buffer, and if ADJUST
5391 is non-null set it to the length of the string we removed from the
5392 input line. Otherwise return NULL. */
5393static char *
3956db08 5394lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5395 int *adjust,
40fb9820 5396 i386_operand_type *types)
f3c180ae 5397{
7b81dfbb
AJ		 5398 /* Some of the relocations depend on the size of what field is to
5399 be relocated. But in our callers i386_immediate and i386_displacement
5400 we don't yet know the operand size (this will be set by insn
5401 matching). Hence we record the word32 relocation here,
5402 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5403 static const struct {
5404 const char *str;
4fa24527 5405 const enum bfd_reloc_code_real rel[2];
40fb9820 5406 const i386_operand_type types64;
f3c180ae 5407 } gotrel[] = {
4eed87de
AM		 5408 { "PLTOFF", { 0,
5409 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5410 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5411 { "PLT", { BFD_RELOC_386_PLT32,
5412 BFD_RELOC_X86_64_PLT32 },
40fb9820 5413 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5414 { "GOTPLT", { 0,
5415 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5416 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5417 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5418 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5419 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5420 { "GOTPCREL", { 0,
5421 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5422 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5423 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5424 BFD_RELOC_X86_64_TLSGD },
40fb9820 5425 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5426 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5427 0 },
40fb9820 5428 OPERAND_TYPE_NONE },
4eed87de
AM		 5429 { "TLSLD", { 0,
5430 BFD_RELOC_X86_64_TLSLD },
40fb9820 5431 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5432 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5433 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5434 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5435 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5436 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5437 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5438 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5439 0 },
40fb9820 5440 OPERAND_TYPE_NONE },
4eed87de
AM		 5441 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5442 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5443
5444 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5445 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5446 0 },
40fb9820 5447 OPERAND_TYPE_NONE },
4eed87de
AM		 5448 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5449 0 },
40fb9820 5450 OPERAND_TYPE_NONE },
4eed87de
AM		 5451 { "GOT", { BFD_RELOC_386_GOT32,
5452 BFD_RELOC_X86_64_GOT32 },
40fb9820 5453 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5454 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5455 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5456 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5457 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5458 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5459 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5460 };
5461 char *cp;
5462 unsigned int j;
5463
718ddfc0
JB		 5464 if (!IS_ELF)
5465 return NULL;
5466
f3c180ae 5467 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5468 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5469 return NULL;
5470
47465058 5471 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5472 {
5473 int len;
5474
5475 len = strlen (gotrel[j].str);
28f81592 5476 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5477 {
4fa24527 5478 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5479 {
28f81592
AM		 5480 int first, second;
5481 char *tmpbuf, *past_reloc;
f3c180ae 5482
4fa24527 5483 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5484 if (adjust)
5485 *adjust = len;
f3c180ae 5486
3956db08
JB		 5487 if (types)
5488 {
5489 if (flag_code != CODE_64BIT)
40fb9820
L		 5490 {
5491 types->bitfield.imm32 = 1;
5492 types->bitfield.disp32 = 1;
5493 }
3956db08
JB		 5494 else
5495 *types = gotrel[j].types64;
5496 }
5497
f3c180ae
AM		 5498 if (GOT_symbol == NULL)
5499 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5500
28f81592 5501 /* The length of the first part of our input line. */
f3c180ae 5502 first = cp - input_line_pointer;
28f81592
AM		 5503
5504 /* The second part goes from after the reloc token until
67c11a9b 5505 (and including) an end_of_line char or comma. */
28f81592 5506 past_reloc = cp + 1 + len;
67c11a9b
AM		 5507 cp = past_reloc;
5508 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5509 ++cp;
5510 second = cp + 1 - past_reloc;
28f81592
AM		 5511
5512 /* Allocate and copy string. The trailing NUL shouldn't
5513 be necessary, but be safe. */
5514 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5515 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5516 if (second != 0 && *past_reloc != ' ')
5517 /* Replace the relocation token with ' ', so that
5518 errors like foo@GOTOFF1 will be detected. */
5519 tmpbuf[first++] = ' ';
5520 memcpy (tmpbuf + first, past_reloc, second);
5521 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5522 return tmpbuf;
5523 }
5524
4fa24527
JB		 5525 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5526 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5527 return NULL;
5528 }
5529 }
5530
5531 /* Might be a symbol version string. Don't as_bad here. */
5532 return NULL;
5533}
5534
f3c180ae 5535void
e3bb37b5 5536x86_cons (expressionS *exp, int size)
f3c180ae 5537{
4fa24527 5538 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5539 {
5540 /* Handle @GOTOFF and the like in an expression. */
5541 char *save;
5542 char *gotfree_input_line;
5543 int adjust;
5544
5545 save = input_line_pointer;
3956db08 5546 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5547 if (gotfree_input_line)
5548 input_line_pointer = gotfree_input_line;
5549
5550 expression (exp);
5551
5552 if (gotfree_input_line)
5553 {
5554 /* expression () has merrily parsed up to the end of line,
5555 or a comma - in the wrong buffer. Transfer how far
5556 input_line_pointer has moved to the right buffer. */
5557 input_line_pointer = (save
5558 + (input_line_pointer - gotfree_input_line)
5559 + adjust);
5560 free (gotfree_input_line);
3992d3b7
AM		 5561 if (exp->X_op == O_constant
5562 || exp->X_op == O_absent
5563 || exp->X_op == O_illegal
5564 || exp->X_op == O_register
5565 || exp->X_op == O_big)
5566 {
5567 char c = *input_line_pointer;
5568 *input_line_pointer = 0;
5569 as_bad (_("missing or invalid expression `%s'"), save);
5570 *input_line_pointer = c;
5571 }
f3c180ae
AM		 5572 }
5573 }
5574 else
5575 expression (exp);
5576}
5577#endif
5578
d182319b 5579static void signed_cons (int size)
6482c264 5580{
d182319b
JB		 5581 if (flag_code == CODE_64BIT)
5582 cons_sign = 1;
5583 cons (size);
5584 cons_sign = -1;
6482c264
NC		 5585}
5586
d182319b 5587#ifdef TE_PE
6482c264
NC		 5588static void
5589pe_directive_secrel (dummy)
5590 int dummy ATTRIBUTE_UNUSED;
5591{
5592 expressionS exp;
5593
5594 do
5595 {
5596 expression (&exp);
5597 if (exp.X_op == O_symbol)
5598 exp.X_op = O_secrel;
5599
5600 emit_expr (&exp, 4);
5601 }
5602 while (*input_line_pointer++ == ',');
5603
5604 input_line_pointer--;
5605 demand_empty_rest_of_line ();
5606}
6482c264
NC		 5607#endif
5608
252b5132 5609static int
70e41ade 5610i386_immediate (char *imm_start)
252b5132
RH		 5611{
5612 char *save_input_line_pointer;
f3c180ae 5613 char *gotfree_input_line;
252b5132 5614 segT exp_seg = 0;
47926f60 5615 expressionS *exp;
40fb9820
L		 5616 i386_operand_type types;
5617
c6fb90c8 5618 UINTS_SET (types, ~0);
252b5132
RH		 5619
5620 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5621 {
31b2323c
L		 5622 as_bad (_("at most %d immediate operands are allowed"),
5623 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5624 return 0;
5625 }
5626
5627 exp = &im_expressions[i.imm_operands++];
520dc8e8 5628 i.op[this_operand].imms = exp;
252b5132
RH		 5629
5630 if (is_space_char (*imm_start))
5631 ++imm_start;
5632
5633 save_input_line_pointer = input_line_pointer;
5634 input_line_pointer = imm_start;
5635
3956db08 5636 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5637 if (gotfree_input_line)
5638 input_line_pointer = gotfree_input_line;
252b5132
RH		 5639
5640 exp_seg = expression (exp);
5641
83183c0c 5642 SKIP_WHITESPACE ();
252b5132 5643 if (*input_line_pointer)
f3c180ae 5644 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5645
5646 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5647 if (gotfree_input_line)
5648 free (gotfree_input_line);
252b5132 5649
3992d3b7
AM		 5650 if (exp->X_op == O_absent
5651 || exp->X_op == O_illegal
5652 || exp->X_op == O_big
5653 || (gotfree_input_line
5654 && (exp->X_op == O_constant
5655 || exp->X_op == O_register)))
252b5132 5656 {
3992d3b7 5657 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5658 imm_start);
3992d3b7 5659 return 0;
252b5132 5660 }
3e73aa7c 5661 else if (exp->X_op == O_constant)
252b5132 5662 {
47926f60 5663 /* Size it properly later. */
40fb9820 5664 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5665 /* If BFD64, sign extend val. */
4eed87de
AM		 5666 if (!use_rela_relocations
5667 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5668 exp->X_add_number
5669 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5670 }
4c63da97 5671#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5672 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5673 && exp_seg != absolute_section
47926f60 5674 && exp_seg != text_section
24eab124
AM		 5675 && exp_seg != data_section
5676 && exp_seg != bss_section
5677 && exp_seg != undefined_section
f86103b7 5678 && !bfd_is_com_section (exp_seg))
252b5132 5679 {
d0b47220 5680 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5681 return 0;
5682 }
5683#endif
bb8f5920
L		 5684 else if (!intel_syntax && exp->X_op == O_register)
5685 {
5686 as_bad (_("illegal immediate register operand %s"), imm_start);
5687 return 0;
5688 }
252b5132
RH		 5689 else
5690 {
5691 /* This is an address. The size of the address will be
24eab124 5692 determined later, depending on destination register,
3e73aa7c 5693 suffix, or the default for the section. */
40fb9820
L		 5694 i.types[this_operand].bitfield.imm8 = 1;
5695 i.types[this_operand].bitfield.imm16 = 1;
5696 i.types[this_operand].bitfield.imm32 = 1;
5697 i.types[this_operand].bitfield.imm32s = 1;
5698 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5699 i.types[this_operand] = operand_type_and (i.types[this_operand],
5700 types);
252b5132
RH		 5701 }
5702
5703 return 1;
5704}
5705
551c1ca1 5706static char *
e3bb37b5 5707i386_scale (char *scale)
252b5132 5708{
551c1ca1
AM		 5709 offsetT val;
5710 char *save = input_line_pointer;
252b5132 5711
551c1ca1
AM		 5712 input_line_pointer = scale;
5713 val = get_absolute_expression ();
5714
5715 switch (val)
252b5132 5716 {
551c1ca1 5717 case 1:
252b5132
RH		 5718 i.log2_scale_factor = 0;
5719 break;
551c1ca1 5720 case 2:
252b5132
RH		 5721 i.log2_scale_factor = 1;
5722 break;
551c1ca1 5723 case 4:
252b5132
RH		 5724 i.log2_scale_factor = 2;
5725 break;
551c1ca1 5726 case 8:
252b5132
RH		 5727 i.log2_scale_factor = 3;
5728 break;
5729 default:
a724f0f4
JB		 5730 {
5731 char sep = *input_line_pointer;
5732
5733 *input_line_pointer = '\0';
5734 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5735 scale);
5736 *input_line_pointer = sep;
5737 input_line_pointer = save;
5738 return NULL;
5739 }
252b5132 5740 }
29b0f896 5741 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5742 {
5743 as_warn (_("scale factor of %d without an index register"),
24eab124 5744 1 << i.log2_scale_factor);
252b5132 5745 i.log2_scale_factor = 0;
252b5132 5746 }
551c1ca1
AM		 5747 scale = input_line_pointer;
5748 input_line_pointer = save;
5749 return scale;
252b5132
RH		 5750}
5751
252b5132 5752static int
e3bb37b5 5753i386_displacement (char *disp_start, char *disp_end)
252b5132 5754{
29b0f896 5755 expressionS *exp;
252b5132
RH		 5756 segT exp_seg = 0;
5757 char *save_input_line_pointer;
f3c180ae 5758 char *gotfree_input_line;
40fb9820
L		 5759 int override;
5760 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5761 int ret;
252b5132 5762
31b2323c
L		 5763 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5764 {
5765 as_bad (_("at most %d displacement operands are allowed"),
5766 MAX_MEMORY_OPERANDS);
5767 return 0;
5768 }
5769
c6fb90c8 5770 UINTS_CLEAR (bigdisp);
40fb9820
L		 5771 if ((i.types[this_operand].bitfield.jumpabsolute)
5772 || (!current_templates->start->opcode_modifier.jump
5773 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5774 {
40fb9820 5775 bigdisp.bitfield.disp32 = 1;
e05278af 5776 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5777 if (flag_code == CODE_64BIT)
5778 {
5779 if (!override)
5780 {
5781 bigdisp.bitfield.disp32s = 1;
5782 bigdisp.bitfield.disp64 = 1;
5783 }
5784 }
5785 else if ((flag_code == CODE_16BIT) ^ override)
5786 {
5787 bigdisp.bitfield.disp32 = 0;
5788 bigdisp.bitfield.disp16 = 1;
5789 }
e05278af
JB		 5790 }
5791 else
5792 {
5793 /* For PC-relative branches, the width of the displacement
5794 is dependent upon data size, not address size. */
e05278af 5795 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5796 if (flag_code == CODE_64BIT)
5797 {
5798 if (override || i.suffix == WORD_MNEM_SUFFIX)
5799 bigdisp.bitfield.disp16 = 1;
5800 else
5801 {
5802 bigdisp.bitfield.disp32 = 1;
5803 bigdisp.bitfield.disp32s = 1;
5804 }
5805 }
5806 else
e05278af
JB		 5807 {
5808 if (!override)
5809 override = (i.suffix == (flag_code != CODE_16BIT
5810 ? WORD_MNEM_SUFFIX
5811 : LONG_MNEM_SUFFIX));
40fb9820
L		 5812 bigdisp.bitfield.disp32 = 1;
5813 if ((flag_code == CODE_16BIT) ^ override)
5814 {
5815 bigdisp.bitfield.disp32 = 0;
5816 bigdisp.bitfield.disp16 = 1;
5817 }
e05278af 5818 }
e05278af 5819 }
c6fb90c8
L		 5820 i.types[this_operand] = operand_type_or (i.types[this_operand],
5821 bigdisp);
252b5132
RH		 5822
5823 exp = &disp_expressions[i.disp_operands];
520dc8e8 5824 i.op[this_operand].disps = exp;
252b5132
RH		 5825 i.disp_operands++;
5826 save_input_line_pointer = input_line_pointer;
5827 input_line_pointer = disp_start;
5828 END_STRING_AND_SAVE (disp_end);
5829
5830#ifndef GCC_ASM_O_HACK
5831#define GCC_ASM_O_HACK 0
5832#endif
5833#if GCC_ASM_O_HACK
5834 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5835 if (i.types[this_operand].bitfield.baseIndex
24eab124 5836 && displacement_string_end[-1] == '+')
252b5132
RH		 5837 {
5838 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5839 constraint within gcc asm statements.
5840 For instance:
5841
5842 #define _set_tssldt_desc(n,addr,limit,type) \
5843 __asm__ __volatile__ ( \
5844 "movw %w2,%0\n\t" \
5845 "movw %w1,2+%0\n\t" \
5846 "rorl $16,%1\n\t" \
5847 "movb %b1,4+%0\n\t" \
5848 "movb %4,5+%0\n\t" \
5849 "movb $0,6+%0\n\t" \
5850 "movb %h1,7+%0\n\t" \
5851 "rorl $16,%1" \
5852 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5853
5854 This works great except that the output assembler ends
5855 up looking a bit weird if it turns out that there is
5856 no offset. You end up producing code that looks like:
5857
5858 #APP
5859 movw $235,(%eax)
5860 movw %dx,2+(%eax)
5861 rorl $16,%edx
5862 movb %dl,4+(%eax)
5863 movb $137,5+(%eax)
5864 movb $0,6+(%eax)
5865 movb %dh,7+(%eax)
5866 rorl $16,%edx
5867 #NO_APP
5868
47926f60 5869 So here we provide the missing zero. */
24eab124
AM		 5870
5871 *displacement_string_end = '0';
252b5132
RH		 5872 }
5873#endif
3956db08 5874 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5875 if (gotfree_input_line)
5876 input_line_pointer = gotfree_input_line;
252b5132 5877
24eab124 5878 exp_seg = expression (exp);
252b5132 5879
636c26b0
AM		 5880 SKIP_WHITESPACE ();
5881 if (*input_line_pointer)
5882 as_bad (_("junk `%s' after expression"), input_line_pointer);
5883#if GCC_ASM_O_HACK
5884 RESTORE_END_STRING (disp_end + 1);
5885#endif
636c26b0 5886 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5887 if (gotfree_input_line)
5888 free (gotfree_input_line);
3992d3b7 5889 ret = 1;
636c26b0 5890
24eab124
AM		 5891 /* We do this to make sure that the section symbol is in
5892 the symbol table. We will ultimately change the relocation
47926f60 5893 to be relative to the beginning of the section. */
1ae12ab7 5894 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5895 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5896 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5897 {
636c26b0 5898 if (exp->X_op != O_symbol)
3992d3b7 5899 goto inv_disp;
636c26b0 5900
e5cb08ac 5901 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5902 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5903 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5904 exp->X_op = O_subtract;
5905 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5906 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5907 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5908 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5909 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5910 else
29b0f896 5911 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5912 }
252b5132 5913
3992d3b7
AM		 5914 else if (exp->X_op == O_absent
5915 || exp->X_op == O_illegal
5916 || exp->X_op == O_big
5917 || (gotfree_input_line
5918 && (exp->X_op == O_constant
5919 || exp->X_op == O_register)))
2daf4fd8 5920 {
3992d3b7
AM		 5921 inv_disp:
5922 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5923 disp_start);
3992d3b7 5924 ret = 0;
2daf4fd8
AM		 5925 }
5926
4c63da97 5927#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5928 else if (exp->X_op != O_constant
5929 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5930 && exp_seg != absolute_section
5931 && exp_seg != text_section
5932 && exp_seg != data_section
5933 && exp_seg != bss_section
5934 && exp_seg != undefined_section
5935 && !bfd_is_com_section (exp_seg))
24eab124 5936 {
d0b47220 5937 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5938 ret = 0;
24eab124 5939 }
252b5132 5940#endif
3956db08 5941
3992d3b7
AM		 5942 RESTORE_END_STRING (disp_end);
5943
40fb9820
L		 5944 /* Check if this is a displacement only operand. */
5945 bigdisp = i.types[this_operand];
5946 bigdisp.bitfield.disp8 = 0;
5947 bigdisp.bitfield.disp16 = 0;
5948 bigdisp.bitfield.disp32 = 0;
5949 bigdisp.bitfield.disp32s = 0;
5950 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5951 if (UINTS_ALL_ZERO (bigdisp))
5952 i.types[this_operand] = operand_type_and (i.types[this_operand],
5953 types);
3956db08 5954
3992d3b7 5955 return ret;
252b5132
RH		 5956}
5957
eecb386c 5958/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5959 Return 1 on success, 0 on a failure. */
5960
252b5132 5961static int
e3bb37b5 5962i386_index_check (const char *operand_string)
252b5132 5963{
3e73aa7c 5964 int ok;
24eab124 5965#if INFER_ADDR_PREFIX
eecb386c
AM		 5966 int fudged = 0;
5967
24eab124
AM		 5968 tryprefix:
5969#endif
3e73aa7c 5970 ok = 1;
75178d9d 5971 if (flag_code == CODE_64BIT)
64e74474 5972 {
64e74474 5973 if ((i.base_reg
40fb9820
L		 5974 && ((i.prefix[ADDR_PREFIX] == 0
5975 && !i.base_reg->reg_type.bitfield.reg64)
5976 || (i.prefix[ADDR_PREFIX]
5977 && !i.base_reg->reg_type.bitfield.reg32))
5978 && (i.index_reg
9a04903e
JB		 5979 || i.base_reg->reg_num !=
5980 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 5981 || (i.index_reg
40fb9820
L		 5982 && (!i.index_reg->reg_type.bitfield.baseindex
5983 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 5984 && i.index_reg->reg_num != RegRiz
5985 && !i.index_reg->reg_type.bitfield.reg64
5986 )
40fb9820 5987 || (i.prefix[ADDR_PREFIX]
db51cc60 5988 && i.index_reg->reg_num != RegEiz
40fb9820 5989 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 5990 ok = 0;
3e73aa7c
JH		 5991 }
5992 else
5993 {
5994 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5995 {
5996 /* 16bit checks. */
5997 if ((i.base_reg
40fb9820
L		 5998 && (!i.base_reg->reg_type.bitfield.reg16
5999 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6000 || (i.index_reg
40fb9820
L		 6001 && (!i.index_reg->reg_type.bitfield.reg16
6002 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6003 || !(i.base_reg
6004 && i.base_reg->reg_num < 6
6005 && i.index_reg->reg_num >= 6
6006 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6007 ok = 0;
6008 }
6009 else
e5cb08ac 6010 {
3e73aa7c
JH		 6011 /* 32bit checks. */
6012 if ((i.base_reg
40fb9820 6013 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6014 || (i.index_reg
db51cc60
L		 6015 && ((!i.index_reg->reg_type.bitfield.reg32
6016 && i.index_reg->reg_num != RegEiz)
40fb9820 6017 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6018 ok = 0;
3e73aa7c
JH		 6019 }
6020 }
6021 if (!ok)
24eab124
AM		 6022 {
6023#if INFER_ADDR_PREFIX
20f0a1fc 6024 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6025 {
6026 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6027 i.prefixes += 1;
b23bac36
AM		 6028 /* Change the size of any displacement too. At most one of
6029 Disp16 or Disp32 is set.
6030 FIXME. There doesn't seem to be any real need for separate
6031 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6032 Removing them would probably clean up the code quite a lot. */
4eed87de 6033 if (flag_code != CODE_64BIT
40fb9820
L		 6034 && (i.types[this_operand].bitfield.disp16
6035 || i.types[this_operand].bitfield.disp32))
6036 i.types[this_operand]
c6fb90c8 6037 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6038 fudged = 1;
24eab124
AM		 6039 goto tryprefix;
6040 }
eecb386c
AM		 6041 if (fudged)
6042 as_bad (_("`%s' is not a valid base/index expression"),
6043 operand_string);
6044 else
c388dee8 6045#endif
eecb386c
AM		 6046 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6047 operand_string,
3e73aa7c 6048 flag_code_names[flag_code]);
24eab124 6049 }
20f0a1fc 6050 return ok;
24eab124 6051}
252b5132 6052
252b5132 6053/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6054 on error. */
252b5132 6055
252b5132 6056static int
e3bb37b5 6057i386_operand (char *operand_string)
252b5132 6058{
af6bdddf
AM		 6059 const reg_entry *r;
6060 char *end_op;
24eab124 6061 char *op_string = operand_string;
252b5132 6062
24eab124 6063 if (is_space_char (*op_string))
252b5132
RH		 6064 ++op_string;
6065
24eab124 6066 /* We check for an absolute prefix (differentiating,
47926f60 6067 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6068 if (*op_string == ABSOLUTE_PREFIX)
6069 {
6070 ++op_string;
6071 if (is_space_char (*op_string))
6072 ++op_string;
40fb9820 6073 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6074 }
252b5132 6075
47926f60 6076 /* Check if operand is a register. */
4d1bb795 6077 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6078 {
40fb9820
L		 6079 i386_operand_type temp;
6080
24eab124
AM		 6081 /* Check for a segment override by searching for ':' after a
6082 segment register. */
6083 op_string = end_op;
6084 if (is_space_char (*op_string))
6085 ++op_string;
40fb9820
L		 6086 if (*op_string == ':'
6087 && (r->reg_type.bitfield.sreg2
6088 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6089 {
6090 switch (r->reg_num)
6091 {
6092 case 0:
6093 i.seg[i.mem_operands] = &es;
6094 break;
6095 case 1:
6096 i.seg[i.mem_operands] = &cs;
6097 break;
6098 case 2:
6099 i.seg[i.mem_operands] = &ss;
6100 break;
6101 case 3:
6102 i.seg[i.mem_operands] = &ds;
6103 break;
6104 case 4:
6105 i.seg[i.mem_operands] = &fs;
6106 break;
6107 case 5:
6108 i.seg[i.mem_operands] = &gs;
6109 break;
6110 }
252b5132 6111
24eab124 6112 /* Skip the ':' and whitespace. */
252b5132
RH		 6113 ++op_string;
6114 if (is_space_char (*op_string))
24eab124 6115 ++op_string;
252b5132 6116
24eab124
AM		 6117 if (!is_digit_char (*op_string)
6118 && !is_identifier_char (*op_string)
6119 && *op_string != '('
6120 && *op_string != ABSOLUTE_PREFIX)
6121 {
6122 as_bad (_("bad memory operand `%s'"), op_string);
6123 return 0;
6124 }
47926f60 6125 /* Handle case of %es:*foo. */
24eab124
AM		 6126 if (*op_string == ABSOLUTE_PREFIX)
6127 {
6128 ++op_string;
6129 if (is_space_char (*op_string))
6130 ++op_string;
40fb9820 6131 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6132 }
6133 goto do_memory_reference;
6134 }
6135 if (*op_string)
6136 {
d0b47220 6137 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6138 return 0;
6139 }
40fb9820
L		 6140 temp = r->reg_type;
6141 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6142 i.types[this_operand] = operand_type_or (i.types[this_operand],
6143 temp);
520dc8e8 6144 i.op[this_operand].regs = r;
24eab124
AM		 6145 i.reg_operands++;
6146 }
af6bdddf
AM		 6147 else if (*op_string == REGISTER_PREFIX)
6148 {
6149 as_bad (_("bad register name `%s'"), op_string);
6150 return 0;
6151 }
24eab124 6152 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6153 {
24eab124 6154 ++op_string;
40fb9820 6155 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6156 {
d0b47220 6157 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6158 return 0;
6159 }
6160 if (!i386_immediate (op_string))
6161 return 0;
6162 }
6163 else if (is_digit_char (*op_string)
6164 || is_identifier_char (*op_string)
e5cb08ac 6165 || *op_string == '(')
24eab124 6166 {
47926f60 6167 /* This is a memory reference of some sort. */
af6bdddf 6168 char *base_string;
252b5132 6169
47926f60 6170 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6171 char *displacement_string_start;
6172 char *displacement_string_end;
252b5132 6173
24eab124 6174 do_memory_reference:
24eab124 6175 if ((i.mem_operands == 1
40fb9820 6176 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6177 || i.mem_operands == 2)
6178 {
6179 as_bad (_("too many memory references for `%s'"),
6180 current_templates->start->name);
6181 return 0;
6182 }
252b5132 6183
24eab124
AM		 6184 /* Check for base index form. We detect the base index form by
6185 looking for an ')' at the end of the operand, searching
6186 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6187 after the '('. */
af6bdddf 6188 base_string = op_string + strlen (op_string);
c3332e24 6189
af6bdddf
AM		 6190 --base_string;
6191 if (is_space_char (*base_string))
6192 --base_string;
252b5132 6193
47926f60 6194 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6195 displacement_string_start = op_string;
6196 displacement_string_end = base_string + 1;
252b5132 6197
24eab124
AM		 6198 if (*base_string == ')')
6199 {
af6bdddf 6200 char *temp_string;
24eab124
AM		 6201 unsigned int parens_balanced = 1;
6202 /* We've already checked that the number of left & right ()'s are
47926f60 6203 equal, so this loop will not be infinite. */
24eab124
AM		 6204 do
6205 {
6206 base_string--;
6207 if (*base_string == ')')
6208 parens_balanced++;
6209 if (*base_string == '(')
6210 parens_balanced--;
6211 }
6212 while (parens_balanced);
c3332e24 6213
af6bdddf 6214 temp_string = base_string;
c3332e24 6215
24eab124 6216 /* Skip past '(' and whitespace. */
252b5132
RH		 6217 ++base_string;
6218 if (is_space_char (*base_string))
24eab124 6219 ++base_string;
252b5132 6220
af6bdddf 6221 if (*base_string == ','
4eed87de
AM		 6222 || ((i.base_reg = parse_register (base_string, &end_op))
6223 != NULL))
252b5132 6224 {
af6bdddf 6225 displacement_string_end = temp_string;
252b5132 6226
40fb9820 6227 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6228
af6bdddf 6229 if (i.base_reg)
24eab124 6230 {
24eab124
AM		 6231 base_string = end_op;
6232 if (is_space_char (*base_string))
6233 ++base_string;
af6bdddf
AM		 6234 }
6235
6236 /* There may be an index reg or scale factor here. */
6237 if (*base_string == ',')
6238 {
6239 ++base_string;
6240 if (is_space_char (*base_string))
6241 ++base_string;
6242
4eed87de
AM		 6243 if ((i.index_reg = parse_register (base_string, &end_op))
6244 != NULL)
24eab124 6245 {
af6bdddf 6246 base_string = end_op;
24eab124
AM		 6247 if (is_space_char (*base_string))
6248 ++base_string;
af6bdddf
AM		 6249 if (*base_string == ',')
6250 {
6251 ++base_string;
6252 if (is_space_char (*base_string))
6253 ++base_string;
6254 }
e5cb08ac 6255 else if (*base_string != ')')
af6bdddf 6256 {
4eed87de
AM		 6257 as_bad (_("expecting `,' or `)' "
6258 "after index register in `%s'"),
af6bdddf
AM		 6259 operand_string);
6260 return 0;
6261 }
24eab124 6262 }
af6bdddf 6263 else if (*base_string == REGISTER_PREFIX)
24eab124 6264 {
af6bdddf 6265 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6266 return 0;
6267 }
252b5132 6268
47926f60 6269 /* Check for scale factor. */
551c1ca1 6270 if (*base_string != ')')
af6bdddf 6271 {
551c1ca1
AM		 6272 char *end_scale = i386_scale (base_string);
6273
6274 if (!end_scale)
af6bdddf 6275 return 0;
24eab124 6276
551c1ca1 6277 base_string = end_scale;
af6bdddf
AM		 6278 if (is_space_char (*base_string))
6279 ++base_string;
6280 if (*base_string != ')')
6281 {
4eed87de
AM		 6282 as_bad (_("expecting `)' "
6283 "after scale factor in `%s'"),
af6bdddf
AM		 6284 operand_string);
6285 return 0;
6286 }
6287 }
6288 else if (!i.index_reg)
24eab124 6289 {
4eed87de
AM		 6290 as_bad (_("expecting index register or scale factor "
6291 "after `,'; got '%c'"),
af6bdddf 6292 *base_string);
24eab124
AM		 6293 return 0;
6294 }
6295 }
af6bdddf 6296 else if (*base_string != ')')
24eab124 6297 {
4eed87de
AM		 6298 as_bad (_("expecting `,' or `)' "
6299 "after base register in `%s'"),
af6bdddf 6300 operand_string);
24eab124
AM		 6301 return 0;
6302 }
c3332e24 6303 }
af6bdddf 6304 else if (*base_string == REGISTER_PREFIX)
c3332e24 6305 {
af6bdddf 6306 as_bad (_("bad register name `%s'"), base_string);
24eab124 6307 return 0;
c3332e24 6308 }
24eab124
AM		 6309 }
6310
6311 /* If there's an expression beginning the operand, parse it,
6312 assuming displacement_string_start and
6313 displacement_string_end are meaningful. */
6314 if (displacement_string_start != displacement_string_end)
6315 {
6316 if (!i386_displacement (displacement_string_start,
6317 displacement_string_end))
6318 return 0;
6319 }
6320
6321 /* Special case for (%dx) while doing input/output op. */
6322 if (i.base_reg
c6fb90c8 6323 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6324 && i.index_reg == 0
6325 && i.log2_scale_factor == 0
6326 && i.seg[i.mem_operands] == 0
40fb9820 6327 && !operand_type_check (i.types[this_operand], disp))
24eab124 6328 {
c6fb90c8 6329 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6330 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6331 return 1;
6332 }
6333
eecb386c
AM		 6334 if (i386_index_check (operand_string) == 0)
6335 return 0;
24eab124
AM		 6336 i.mem_operands++;
6337 }
6338 else
ce8a8b2f
AM		 6339 {
6340 /* It's not a memory operand; argh! */
24eab124
AM		 6341 as_bad (_("invalid char %s beginning operand %d `%s'"),
6342 output_invalid (*op_string),
6343 this_operand + 1,
6344 op_string);
6345 return 0;
6346 }
47926f60 6347 return 1; /* Normal return. */
252b5132
RH		 6348}
6349\f
ee7fcc42
AM		 6350/* md_estimate_size_before_relax()
6351
6352 Called just before relax() for rs_machine_dependent frags. The x86
6353 assembler uses these frags to handle variable size jump
6354 instructions.
6355
6356 Any symbol that is now undefined will not become defined.
6357 Return the correct fr_subtype in the frag.
6358 Return the initial "guess for variable size of frag" to caller.
6359 The guess is actually the growth beyond the fixed part. Whatever
6360 we do to grow the fixed or variable part contributes to our
6361 returned value. */
6362
252b5132
RH		 6363int
6364md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6365 fragS *fragP;
6366 segT segment;
252b5132 6367{
252b5132 6368 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6369 check for un-relaxable symbols. On an ELF system, we can't relax
6370 an externally visible symbol, because it may be overridden by a
6371 shared library. */
6372 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6373#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6374 || (IS_ELF
31312f95
AM		 6375 && (S_IS_EXTERNAL (fragP->fr_symbol)
6376 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6377#endif
6378 )
252b5132 6379 {
b98ef147
AM		 6380 /* Symbol is undefined in this segment, or we need to keep a
6381 reloc so that weak symbols can be overridden. */
6382 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6383 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6384 unsigned char *opcode;
6385 int old_fr_fix;
f6af82bd 6386
ee7fcc42
AM		 6387 if (fragP->fr_var != NO_RELOC)
6388 reloc_type = fragP->fr_var;
b98ef147 6389 else if (size == 2)
f6af82bd
AM		 6390 reloc_type = BFD_RELOC_16_PCREL;
6391 else
6392 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6393
ee7fcc42
AM		 6394 old_fr_fix = fragP->fr_fix;
6395 opcode = (unsigned char *) fragP->fr_opcode;
6396
fddf5b5b 6397 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6398 {
fddf5b5b
AM		 6399 case UNCOND_JUMP:
6400 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6401 opcode[0] = 0xe9;
252b5132 6402 fragP->fr_fix += size;
062cd5e7
AS		 6403 fix_new (fragP, old_fr_fix, size,
6404 fragP->fr_symbol,
6405 fragP->fr_offset, 1,
6406 reloc_type);
252b5132
RH		 6407 break;
6408
fddf5b5b 6409 case COND_JUMP86:
412167cb
AM		 6410 if (size == 2
6411 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6412 {
6413 /* Negate the condition, and branch past an
6414 unconditional jump. */
6415 opcode[0] ^= 1;
6416 opcode[1] = 3;
6417 /* Insert an unconditional jump. */
6418 opcode[2] = 0xe9;
6419 /* We added two extra opcode bytes, and have a two byte
6420 offset. */
6421 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6422 fix_new (fragP, old_fr_fix + 2, 2,
6423 fragP->fr_symbol,
6424 fragP->fr_offset, 1,
6425 reloc_type);
fddf5b5b
AM		 6426 break;
6427 }
6428 /* Fall through. */
6429
6430 case COND_JUMP:
412167cb
AM		 6431 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6432 {
3e02c1cc
AM		 6433 fixS *fixP;
6434
412167cb 6435 fragP->fr_fix += 1;
3e02c1cc
AM		 6436 fixP = fix_new (fragP, old_fr_fix, 1,
6437 fragP->fr_symbol,
6438 fragP->fr_offset, 1,
6439 BFD_RELOC_8_PCREL);
6440 fixP->fx_signed = 1;
412167cb
AM		 6441 break;
6442 }
93c2a809 6443
24eab124 6444 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6445 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6446 opcode[1] = opcode[0] + 0x10;
f6af82bd 6447 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6448 /* We've added an opcode byte. */
6449 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6450 fix_new (fragP, old_fr_fix + 1, size,
6451 fragP->fr_symbol,
6452 fragP->fr_offset, 1,
6453 reloc_type);
252b5132 6454 break;
fddf5b5b
AM		 6455
6456 default:
6457 BAD_CASE (fragP->fr_subtype);
6458 break;
252b5132
RH		 6459 }
6460 frag_wane (fragP);
ee7fcc42 6461 return fragP->fr_fix - old_fr_fix;
252b5132 6462 }
93c2a809 6463
93c2a809
AM		 6464 /* Guess size depending on current relax state. Initially the relax
6465 state will correspond to a short jump and we return 1, because
6466 the variable part of the frag (the branch offset) is one byte
6467 long. However, we can relax a section more than once and in that
6468 case we must either set fr_subtype back to the unrelaxed state,
6469 or return the value for the appropriate branch. */
6470 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6471}
6472
47926f60
KH		 6473/* Called after relax() is finished.
6474
6475 In: Address of frag.
6476 fr_type == rs_machine_dependent.
6477 fr_subtype is what the address relaxed to.
6478
6479 Out: Any fixSs and constants are set up.
6480 Caller will turn frag into a ".space 0". */
6481
252b5132
RH		 6482void
6483md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6484 bfd *abfd ATTRIBUTE_UNUSED;
6485 segT sec ATTRIBUTE_UNUSED;
29b0f896 6486 fragS *fragP;
252b5132 6487{
29b0f896 6488 unsigned char *opcode;
252b5132 6489 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6490 offsetT target_address;
6491 offsetT opcode_address;
252b5132 6492 unsigned int extension = 0;
847f7ad4 6493 offsetT displacement_from_opcode_start;
252b5132
RH		 6494
6495 opcode = (unsigned char *) fragP->fr_opcode;
6496
47926f60 6497 /* Address we want to reach in file space. */
252b5132 6498 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6499
47926f60 6500 /* Address opcode resides at in file space. */
252b5132
RH		 6501 opcode_address = fragP->fr_address + fragP->fr_fix;
6502
47926f60 6503 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6504 displacement_from_opcode_start = target_address - opcode_address;
6505
fddf5b5b 6506 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6507 {
47926f60
KH		 6508 /* Don't have to change opcode. */
6509 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6510 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6511 }
6512 else
6513 {
6514 if (no_cond_jump_promotion
6515 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6516 as_warn_where (fragP->fr_file, fragP->fr_line,
6517 _("long jump required"));
252b5132 6518
fddf5b5b
AM		 6519 switch (fragP->fr_subtype)
6520 {
6521 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6522 extension = 4; /* 1 opcode + 4 displacement */
6523 opcode[0] = 0xe9;
6524 where_to_put_displacement = &opcode[1];
6525 break;
252b5132 6526
fddf5b5b
AM		 6527 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6528 extension = 2; /* 1 opcode + 2 displacement */
6529 opcode[0] = 0xe9;
6530 where_to_put_displacement = &opcode[1];
6531 break;
252b5132 6532
fddf5b5b
AM		 6533 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6534 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6535 extension = 5; /* 2 opcode + 4 displacement */
6536 opcode[1] = opcode[0] + 0x10;
6537 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6538 where_to_put_displacement = &opcode[2];
6539 break;
252b5132 6540
fddf5b5b
AM		 6541 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6542 extension = 3; /* 2 opcode + 2 displacement */
6543 opcode[1] = opcode[0] + 0x10;
6544 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6545 where_to_put_displacement = &opcode[2];
6546 break;
252b5132 6547
fddf5b5b
AM		 6548 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6549 extension = 4;
6550 opcode[0] ^= 1;
6551 opcode[1] = 3;
6552 opcode[2] = 0xe9;
6553 where_to_put_displacement = &opcode[3];
6554 break;
6555
6556 default:
6557 BAD_CASE (fragP->fr_subtype);
6558 break;
6559 }
252b5132 6560 }
fddf5b5b 6561
7b81dfbb
AJ		 6562 /* If size if less then four we are sure that the operand fits,
6563 but if it's 4, then it could be that the displacement is larger
6564 then -/+ 2GB. */
6565 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6566 && object_64bit
6567 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6568 + ((addressT) 1 << 31))
6569 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6570 {
6571 as_bad_where (fragP->fr_file, fragP->fr_line,
6572 _("jump target out of range"));
6573 /* Make us emit 0. */
6574 displacement_from_opcode_start = extension;
6575 }
47926f60 6576 /* Now put displacement after opcode. */
252b5132
RH		 6577 md_number_to_chars ((char *) where_to_put_displacement,
6578 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6579 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6580 fragP->fr_fix += extension;
6581}
6582\f
252b5132
RH		 6583/* Apply a fixup (fixS) to segment data, once it has been determined
6584 by our caller that we have all the info we need to fix it up.
6585
6586 On the 386, immediates, displacements, and data pointers are all in
6587 the same (little-endian) format, so we don't need to care about which
6588 we are handling. */
6589
94f592af 6590void
55cf6793 6591md_apply_fix (fixP, valP, seg)
47926f60
KH		 6592 /* The fix we're to put in. */
6593 fixS *fixP;
47926f60 6594 /* Pointer to the value of the bits. */
c6682705 6595 valueT *valP;
47926f60
KH		 6596 /* Segment fix is from. */
6597 segT seg ATTRIBUTE_UNUSED;
252b5132 6598{
94f592af 6599 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6600 valueT value = *valP;
252b5132 6601
f86103b7 6602#if !defined (TE_Mach)
93382f6d
AM		 6603 if (fixP->fx_pcrel)
6604 {
6605 switch (fixP->fx_r_type)
6606 {
5865bb77
ILT		 6607 default:
6608 break;
6609
d6ab8113
JB		 6610 case BFD_RELOC_64:
6611 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6612 break;
93382f6d 6613 case BFD_RELOC_32:
ae8887b5 6614 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6615 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6616 break;
6617 case BFD_RELOC_16:
6618 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6619 break;
6620 case BFD_RELOC_8:
6621 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6622 break;
6623 }
6624 }
252b5132 6625
a161fe53 6626 if (fixP->fx_addsy != NULL
31312f95 6627 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6628 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6629 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6630 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6631 && !use_rela_relocations)
252b5132 6632 {
31312f95
AM		 6633 /* This is a hack. There should be a better way to handle this.
6634 This covers for the fact that bfd_install_relocation will
6635 subtract the current location (for partial_inplace, PC relative
6636 relocations); see more below. */
252b5132 6637#ifndef OBJ_AOUT
718ddfc0 6638 if (IS_ELF
252b5132
RH		 6639#ifdef TE_PE
6640 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6641#endif
6642 )
6643 value += fixP->fx_where + fixP->fx_frag->fr_address;
6644#endif
6645#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6646 if (IS_ELF)
252b5132 6647 {
6539b54b 6648 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6649
6539b54b 6650 if ((sym_seg == seg
2f66722d 6651 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6652 && sym_seg != absolute_section))
ae6063d4 6653 && !generic_force_reloc (fixP))
2f66722d
AM		 6654 {
6655 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6656 bfd_install_relocation subtracts them out again. I think
6657 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6658 it. FIXME. */
6659 value += fixP->fx_where + fixP->fx_frag->fr_address;
6660 }
252b5132
RH		 6661 }
6662#endif
6663#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6664 /* For some reason, the PE format does not store a
6665 section address offset for a PC relative symbol. */
6666 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6667 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6668 value += md_pcrel_from (fixP);
6669#endif
6670 }
6671
6672 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6673 and we must not disappoint it. */
252b5132 6674#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6675 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6676 switch (fixP->fx_r_type)
6677 {
6678 case BFD_RELOC_386_PLT32:
3e73aa7c 6679 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6680 /* Make the jump instruction point to the address of the operand. At
6681 runtime we merely add the offset to the actual PLT entry. */
6682 value = -4;
6683 break;
31312f95 6684
13ae64f3
JJ		 6685 case BFD_RELOC_386_TLS_GD:
6686 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6687 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6688 case BFD_RELOC_386_TLS_IE:
6689 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6690 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6691 case BFD_RELOC_X86_64_TLSGD:
6692 case BFD_RELOC_X86_64_TLSLD:
6693 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6694 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6695 value = 0; /* Fully resolved at runtime. No addend. */
6696 /* Fallthrough */
6697 case BFD_RELOC_386_TLS_LE:
6698 case BFD_RELOC_386_TLS_LDO_32:
6699 case BFD_RELOC_386_TLS_LE_32:
6700 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6701 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6702 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6703 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6704 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6705 break;
6706
67a4f2b7
AO		 6707 case BFD_RELOC_386_TLS_DESC_CALL:
6708 case BFD_RELOC_X86_64_TLSDESC_CALL:
6709 value = 0; /* Fully resolved at runtime. No addend. */
6710 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6711 fixP->fx_done = 0;
6712 return;
6713
00f7efb6
JJ		 6714 case BFD_RELOC_386_GOT32:
6715 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6716 value = 0; /* Fully resolved at runtime. No addend. */
6717 break;
47926f60
KH		 6718
6719 case BFD_RELOC_VTABLE_INHERIT:
6720 case BFD_RELOC_VTABLE_ENTRY:
6721 fixP->fx_done = 0;
94f592af 6722 return;
47926f60
KH		 6723
6724 default:
6725 break;
6726 }
6727#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6728 *valP = value;
f86103b7 6729#endif /* !defined (TE_Mach) */
3e73aa7c 6730
3e73aa7c 6731 /* Are we finished with this relocation now? */
c6682705 6732 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6733 fixP->fx_done = 1;
6734 else if (use_rela_relocations)
6735 {
6736 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6737 /* Remember value for tc_gen_reloc. */
6738 fixP->fx_addnumber = value;
3e73aa7c
JH		 6739 value = 0;
6740 }
f86103b7 6741
94f592af 6742 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6743}
252b5132 6744\f
252b5132 6745char *
499ac353 6746md_atof (int type, char *litP, int *sizeP)
252b5132 6747{
499ac353
NC		 6748 /* This outputs the LITTLENUMs in REVERSE order;
6749 in accord with the bigendian 386. */
6750 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 6751}
6752\f
2d545b82 6753static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6754
252b5132 6755static char *
e3bb37b5 6756output_invalid (int c)
252b5132 6757{
3882b010 6758 if (ISPRINT (c))
f9f21a03
L		 6759 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6760 "'%c'", c);
252b5132 6761 else
f9f21a03 6762 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6763 "(0x%x)", (unsigned char) c);
252b5132
RH		 6764 return output_invalid_buf;
6765}
6766
af6bdddf 6767/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6768
6769static const reg_entry *
4d1bb795 6770parse_real_register (char *reg_string, char **end_op)
252b5132 6771{
af6bdddf
AM		 6772 char *s = reg_string;
6773 char *p;
252b5132
RH		 6774 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6775 const reg_entry *r;
6776
6777 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6778 if (*s == REGISTER_PREFIX)
6779 ++s;
6780
6781 if (is_space_char (*s))
6782 ++s;
6783
6784 p = reg_name_given;
af6bdddf 6785 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6786 {
6787 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6788 return (const reg_entry *) NULL;
6789 s++;
252b5132
RH		 6790 }
6791
6588847e
DN		 6792 /* For naked regs, make sure that we are not dealing with an identifier.
6793 This prevents confusing an identifier like `eax_var' with register
6794 `eax'. */
6795 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6796 return (const reg_entry *) NULL;
6797
af6bdddf 6798 *end_op = s;
252b5132
RH		 6799
6800 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6801
5f47d35b 6802 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6803 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6804 {
5f47d35b
AM		 6805 if (is_space_char (*s))
6806 ++s;
6807 if (*s == '(')
6808 {
af6bdddf 6809 ++s;
5f47d35b
AM		 6810 if (is_space_char (*s))
6811 ++s;
6812 if (*s >= '0' && *s <= '7')
6813 {
db557034 6814 int fpr = *s - '0';
af6bdddf 6815 ++s;
5f47d35b
AM		 6816 if (is_space_char (*s))
6817 ++s;
6818 if (*s == ')')
6819 {
6820 *end_op = s + 1;
db557034
AM		 6821 r = hash_find (reg_hash, "st(0)");
6822 know (r);
6823 return r + fpr;
5f47d35b 6824 }
5f47d35b 6825 }
47926f60 6826 /* We have "%st(" then garbage. */
5f47d35b
AM		 6827 return (const reg_entry *) NULL;
6828 }
6829 }
6830
db51cc60
L		 6831 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6832 if (r != NULL
6833 && !allow_index_reg
6834 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6835 return (const reg_entry *) NULL;
6836
1ae00879 6837 if (r != NULL
d946b91f 6838 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6839 || r->reg_type.bitfield.reg64)
6840 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6841 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6842 && flag_code != CODE_64BIT)
20f0a1fc 6843 return (const reg_entry *) NULL;
1ae00879 6844
252b5132
RH		 6845 return r;
6846}
4d1bb795
JB		 6847
6848/* REG_STRING starts *before* REGISTER_PREFIX. */
6849
6850static const reg_entry *
6851parse_register (char *reg_string, char **end_op)
6852{
6853 const reg_entry *r;
6854
6855 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6856 r = parse_real_register (reg_string, end_op);
6857 else
6858 r = NULL;
6859 if (!r)
6860 {
6861 char *save = input_line_pointer;
6862 char c;
6863 symbolS *symbolP;
6864
6865 input_line_pointer = reg_string;
6866 c = get_symbol_end ();
6867 symbolP = symbol_find (reg_string);
6868 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6869 {
6870 const expressionS *e = symbol_get_value_expression (symbolP);
6871
6872 know (e->X_op == O_register);
4eed87de 6873 know (e->X_add_number >= 0
c3fe08fa 6874 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6875 r = i386_regtab + e->X_add_number;
6876 *end_op = input_line_pointer;
6877 }
6878 *input_line_pointer = c;
6879 input_line_pointer = save;
6880 }
6881 return r;
6882}
6883
6884int
6885i386_parse_name (char *name, expressionS *e, char *nextcharP)
6886{
6887 const reg_entry *r;
6888 char *end = input_line_pointer;
6889
6890 *end = *nextcharP;
6891 r = parse_register (name, &input_line_pointer);
6892 if (r && end <= input_line_pointer)
6893 {
6894 *nextcharP = *input_line_pointer;
6895 *input_line_pointer = 0;
6896 e->X_op = O_register;
6897 e->X_add_number = r - i386_regtab;
6898 return 1;
6899 }
6900 input_line_pointer = end;
6901 *end = 0;
6902 return 0;
6903}
6904
6905void
6906md_operand (expressionS *e)
6907{
6908 if (*input_line_pointer == REGISTER_PREFIX)
6909 {
6910 char *end;
6911 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6912
6913 if (r)
6914 {
6915 e->X_op = O_register;
6916 e->X_add_number = r - i386_regtab;
6917 input_line_pointer = end;
6918 }
6919 }
6920}
6921
252b5132 6922\f
4cc782b5 6923#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 6924const char *md_shortopts = "kVQ:sqn";
252b5132 6925#else
12b55ccc 6926const char *md_shortopts = "qn";
252b5132 6927#endif
6e0b89ee 6928
3e73aa7c 6929#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 6930#define OPTION_64 (OPTION_MD_BASE + 1)
6931#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 6932#define OPTION_MARCH (OPTION_MD_BASE + 3)
6933#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 6934#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
6935#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
6936#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
6937#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
6938#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
b3b91714 6939
99ad8390
NC		 6940struct option md_longopts[] =
6941{
3e73aa7c 6942 {"32", no_argument, NULL, OPTION_32},
99ad8390 6943#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 6944 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 6945#endif
b3b91714 6946 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 6947 {"march", required_argument, NULL, OPTION_MARCH},
6948 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 6949 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
6950 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
6951 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
6952 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
6953 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
252b5132
RH		 6954 {NULL, no_argument, NULL, 0}
6955};
6956size_t md_longopts_size = sizeof (md_longopts);
6957
6958int
9103f4f4 6959md_parse_option (int c, char *arg)
252b5132 6960{
9103f4f4
L		 6961 unsigned int i;
6962
252b5132
RH		 6963 switch (c)
6964 {
12b55ccc
L		 6965 case 'n':
6966 optimize_align_code = 0;
6967 break;
6968
a38cf1db
AM		 6969 case 'q':
6970 quiet_warnings = 1;
252b5132
RH		 6971 break;
6972
6973#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 6974 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6975 should be emitted or not. FIXME: Not implemented. */
6976 case 'Q':
252b5132
RH		 6977 break;
6978
6979 /* -V: SVR4 argument to print version ID. */
6980 case 'V':
6981 print_version_id ();
6982 break;
6983
a38cf1db
AM		 6984 /* -k: Ignore for FreeBSD compatibility. */
6985 case 'k':
252b5132 6986 break;
4cc782b5
ILT		 6987
6988 case 's':
6989 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 6990 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 6991 break;
99ad8390
NC		 6992#endif
6993#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 6994 case OPTION_64:
6995 {
6996 const char **list, **l;
6997
3e73aa7c
JH		 6998 list = bfd_target_list ();
6999 for (l = list; *l != NULL; l++)
8620418b 7000 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7001 || strcmp (*l, "coff-x86-64") == 0
7002 || strcmp (*l, "pe-x86-64") == 0
7003 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7004 {
7005 default_arch = "x86_64";
7006 break;
7007 }
3e73aa7c 7008 if (*l == NULL)
6e0b89ee 7009 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7010 free (list);
7011 }
7012 break;
7013#endif
252b5132 7014
6e0b89ee
AM		 7015 case OPTION_32:
7016 default_arch = "i386";
7017 break;
7018
b3b91714
AM		 7019 case OPTION_DIVIDE:
7020#ifdef SVR4_COMMENT_CHARS
7021 {
7022 char *n, *t;
7023 const char *s;
7024
7025 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7026 t = n;
7027 for (s = i386_comment_chars; *s != '\0'; s++)
7028 if (*s != '/')
7029 *t++ = *s;
7030 *t = '\0';
7031 i386_comment_chars = n;
7032 }
7033#endif
7034 break;
7035
9103f4f4
L		 7036 case OPTION_MARCH:
7037 if (*arg == '.')
7038 as_fatal (_("Invalid -march= option: `%s'"), arg);
7039 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7040 {
7041 if (strcmp (arg, cpu_arch [i].name) == 0)
7042 {
ccc9c027 7043 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7044 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7045 if (!cpu_arch_tune_set)
7046 {
7047 cpu_arch_tune = cpu_arch_isa;
7048 cpu_arch_tune_flags = cpu_arch_isa_flags;
7049 }
9103f4f4
L		 7050 break;
7051 }
7052 }
7053 if (i >= ARRAY_SIZE (cpu_arch))
7054 as_fatal (_("Invalid -march= option: `%s'"), arg);
7055 break;
7056
7057 case OPTION_MTUNE:
7058 if (*arg == '.')
7059 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7060 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7061 {
7062 if (strcmp (arg, cpu_arch [i].name) == 0)
7063 {
ccc9c027 7064 cpu_arch_tune_set = 1;
9103f4f4
L		 7065 cpu_arch_tune = cpu_arch [i].type;
7066 cpu_arch_tune_flags = cpu_arch[i].flags;
7067 break;
7068 }
7069 }
7070 if (i >= ARRAY_SIZE (cpu_arch))
7071 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7072 break;
7073
1efbbeb4
L		 7074 case OPTION_MMNEMONIC:
7075 if (strcasecmp (arg, "att") == 0)
7076 intel_mnemonic = 0;
7077 else if (strcasecmp (arg, "intel") == 0)
7078 intel_mnemonic = 1;
7079 else
7080 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7081 break;
7082
7083 case OPTION_MSYNTAX:
7084 if (strcasecmp (arg, "att") == 0)
7085 intel_syntax = 0;
7086 else if (strcasecmp (arg, "intel") == 0)
7087 intel_syntax = 1;
7088 else
7089 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7090 break;
7091
7092 case OPTION_MINDEX_REG:
7093 allow_index_reg = 1;
7094 break;
7095
7096 case OPTION_MNAKED_REG:
7097 allow_naked_reg = 1;
7098 break;
7099
7100 case OPTION_MOLD_GCC:
7101 old_gcc = 1;
1efbbeb4
L		 7102 break;
7103
252b5132
RH		 7104 default:
7105 return 0;
7106 }
7107 return 1;
7108}
7109
7110void
7111md_show_usage (stream)
7112 FILE *stream;
7113{
4cc782b5
ILT		 7114#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7115 fprintf (stream, _("\
a38cf1db
AM		 7116 -Q ignored\n\
7117 -V print assembler version number\n\
b3b91714
AM		 7118 -k ignored\n"));
7119#endif
7120 fprintf (stream, _("\
12b55ccc 7121 -n Do not optimize code alignment\n\
b3b91714
AM		 7122 -q quieten some warnings\n"));
7123#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7124 fprintf (stream, _("\
a38cf1db 7125 -s ignored\n"));
b3b91714 7126#endif
751d281c
L		 7127#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7128 fprintf (stream, _("\
7129 --32/--64 generate 32bit/64bit code\n"));
7130#endif
b3b91714
AM		 7131#ifdef SVR4_COMMENT_CHARS
7132 fprintf (stream, _("\
7133 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7134#else
7135 fprintf (stream, _("\
b3b91714 7136 --divide ignored\n"));
4cc782b5 7137#endif
9103f4f4
L		 7138 fprintf (stream, _("\
7139 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7140 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7141 core, core2, k6, athlon, k8, generic32, generic64\n"));
ba104c83
L		 7142 fprintf (stream, _("\
7143 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7144 fprintf (stream, _("\
7145 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7146 fprintf (stream, _("\
7147 -mindex-reg support pseudo index registers\n"));
7148 fprintf (stream, _("\
7149 -mnaked-reg don't require `%%' prefix for registers\n"));
7150 fprintf (stream, _("\
7151 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7152}
7153
3e73aa7c 7154#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7155 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7156
7157/* Pick the target format to use. */
7158
47926f60 7159const char *
e3bb37b5 7160i386_target_format (void)
252b5132 7161{
3e73aa7c 7162 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7163 {
7164 set_code_flag (CODE_64BIT);
c6fb90c8 7165 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7166 {
7167 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7168 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7169 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7170 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7171 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7172 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7173 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7174 cpu_arch_isa_flags.bitfield.cpummx= 1;
7175 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7176 cpu_arch_isa_flags.bitfield.cpusse = 1;
7177 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7178 }
c6fb90c8 7179 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7180 {
7181 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7182 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7183 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7184 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7185 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7186 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7187 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7188 cpu_arch_tune_flags.bitfield.cpummx= 1;
7189 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7190 cpu_arch_tune_flags.bitfield.cpusse = 1;
7191 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7192 }
9103f4f4 7193 }
3e73aa7c 7194 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7195 {
7196 set_code_flag (CODE_32BIT);
c6fb90c8 7197 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7198 {
7199 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7200 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7201 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7202 }
c6fb90c8 7203 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7204 {
7205 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7206 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7207 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7208 }
9103f4f4 7209 }
3e73aa7c
JH		 7210 else
7211 as_fatal (_("Unknown architecture"));
252b5132
RH		 7212 switch (OUTPUT_FLAVOR)
7213 {
872ce6ff
L		 7214#ifdef TE_PEP
7215 case bfd_target_coff_flavour:
7216 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7217 break;
7218#endif
4c63da97
AM		 7219#ifdef OBJ_MAYBE_AOUT
7220 case bfd_target_aout_flavour:
47926f60 7221 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7222#endif
7223#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7224 case bfd_target_coff_flavour:
7225 return "coff-i386";
4c63da97 7226#endif
3e73aa7c 7227#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7228 case bfd_target_elf_flavour:
3e73aa7c 7229 {
e5cb08ac 7230 if (flag_code == CODE_64BIT)
4fa24527
JB		 7231 {
7232 object_64bit = 1;
7233 use_rela_relocations = 1;
7234 }
9d7cbccd 7235 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7236 }
4c63da97 7237#endif
252b5132
RH		 7238 default:
7239 abort ();
7240 return NULL;
7241 }
7242}
7243
47926f60 7244#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7245
7246#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7247void
7248i386_elf_emit_arch_note (void)
a847613f 7249{
718ddfc0 7250 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7251 {
7252 char *p;
7253 asection *seg = now_seg;
7254 subsegT subseg = now_subseg;
7255 Elf_Internal_Note i_note;
7256 Elf_External_Note e_note;
7257 asection *note_secp;
7258 int len;
7259
7260 /* Create the .note section. */
7261 note_secp = subseg_new (".note", 0);
7262 bfd_set_section_flags (stdoutput,
7263 note_secp,
7264 SEC_HAS_CONTENTS | SEC_READONLY);
7265
7266 /* Process the arch string. */
7267 len = strlen (cpu_arch_name);
7268
7269 i_note.namesz = len + 1;
7270 i_note.descsz = 0;
7271 i_note.type = NT_ARCH;
7272 p = frag_more (sizeof (e_note.namesz));
7273 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7274 p = frag_more (sizeof (e_note.descsz));
7275 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7276 p = frag_more (sizeof (e_note.type));
7277 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7278 p = frag_more (len + 1);
7279 strcpy (p, cpu_arch_name);
7280
7281 frag_align (2, 0, 0);
7282
7283 subseg_set (seg, subseg);
7284 }
7285}
7286#endif
252b5132 7287\f
252b5132
RH		 7288symbolS *
7289md_undefined_symbol (name)
7290 char *name;
7291{
18dc2407
ILT		 7292 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7293 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7294 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7295 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7296 {
7297 if (!GOT_symbol)
7298 {
7299 if (symbol_find (name))
7300 as_bad (_("GOT already in symbol table"));
7301 GOT_symbol = symbol_new (name, undefined_section,
7302 (valueT) 0, &zero_address_frag);
7303 };
7304 return GOT_symbol;
7305 }
252b5132
RH		 7306 return 0;
7307}
7308
7309/* Round up a section size to the appropriate boundary. */
47926f60 7310
252b5132
RH		 7311valueT
7312md_section_align (segment, size)
ab9da554 7313 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7314 valueT size;
7315{
4c63da97
AM		 7316#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7317 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7318 {
7319 /* For a.out, force the section size to be aligned. If we don't do
7320 this, BFD will align it for us, but it will not write out the
7321 final bytes of the section. This may be a bug in BFD, but it is
7322 easier to fix it here since that is how the other a.out targets
7323 work. */
7324 int align;
7325
7326 align = bfd_get_section_alignment (stdoutput, segment);
7327 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7328 }
252b5132
RH		 7329#endif
7330
7331 return size;
7332}
7333
7334/* On the i386, PC-relative offsets are relative to the start of the
7335 next instruction. That is, the address of the offset, plus its
7336 size, since the offset is always the last part of the insn. */
7337
7338long
e3bb37b5 7339md_pcrel_from (fixS *fixP)
252b5132
RH		 7340{
7341 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7342}
7343
7344#ifndef I386COFF
7345
7346static void
e3bb37b5 7347s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7348{
29b0f896 7349 int temp;
252b5132 7350
8a75718c
JB		 7351#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7352 if (IS_ELF)
7353 obj_elf_section_change_hook ();
7354#endif
252b5132
RH		 7355 temp = get_absolute_expression ();
7356 subseg_set (bss_section, (subsegT) temp);
7357 demand_empty_rest_of_line ();
7358}
7359
7360#endif
7361
252b5132 7362void
e3bb37b5 7363i386_validate_fix (fixS *fixp)
252b5132
RH		 7364{
7365 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7366 {
23df1078
JH		 7367 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7368 {
4fa24527 7369 if (!object_64bit)
23df1078
JH		 7370 abort ();
7371 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7372 }
7373 else
7374 {
4fa24527 7375 if (!object_64bit)
d6ab8113
JB		 7376 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7377 else
7378 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7379 }
252b5132
RH		 7380 fixp->fx_subsy = 0;
7381 }
7382}
7383
252b5132
RH		 7384arelent *
7385tc_gen_reloc (section, fixp)
ab9da554 7386 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7387 fixS *fixp;
7388{
7389 arelent *rel;
7390 bfd_reloc_code_real_type code;
7391
7392 switch (fixp->fx_r_type)
7393 {
3e73aa7c
JH		 7394 case BFD_RELOC_X86_64_PLT32:
7395 case BFD_RELOC_X86_64_GOT32:
7396 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7397 case BFD_RELOC_386_PLT32:
7398 case BFD_RELOC_386_GOT32:
7399 case BFD_RELOC_386_GOTOFF:
7400 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7401 case BFD_RELOC_386_TLS_GD:
7402 case BFD_RELOC_386_TLS_LDM:
7403 case BFD_RELOC_386_TLS_LDO_32:
7404 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7405 case BFD_RELOC_386_TLS_IE:
7406 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7407 case BFD_RELOC_386_TLS_LE_32:
7408 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7409 case BFD_RELOC_386_TLS_GOTDESC:
7410 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7411 case BFD_RELOC_X86_64_TLSGD:
7412 case BFD_RELOC_X86_64_TLSLD:
7413 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7414 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7415 case BFD_RELOC_X86_64_GOTTPOFF:
7416 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7417 case BFD_RELOC_X86_64_TPOFF64:
7418 case BFD_RELOC_X86_64_GOTOFF64:
7419 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7420 case BFD_RELOC_X86_64_GOT64:
7421 case BFD_RELOC_X86_64_GOTPCREL64:
7422 case BFD_RELOC_X86_64_GOTPC64:
7423 case BFD_RELOC_X86_64_GOTPLT64:
7424 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7425 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7426 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7427 case BFD_RELOC_RVA:
7428 case BFD_RELOC_VTABLE_ENTRY:
7429 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7430#ifdef TE_PE
7431 case BFD_RELOC_32_SECREL:
7432#endif
252b5132
RH		 7433 code = fixp->fx_r_type;
7434 break;
dbbaec26
L		 7435 case BFD_RELOC_X86_64_32S:
7436 if (!fixp->fx_pcrel)
7437 {
7438 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7439 code = fixp->fx_r_type;
7440 break;
7441 }
252b5132 7442 default:
93382f6d 7443 if (fixp->fx_pcrel)
252b5132 7444 {
93382f6d
AM		 7445 switch (fixp->fx_size)
7446 {
7447 default:
b091f402
AM		 7448 as_bad_where (fixp->fx_file, fixp->fx_line,
7449 _("can not do %d byte pc-relative relocation"),
7450 fixp->fx_size);
93382f6d
AM		 7451 code = BFD_RELOC_32_PCREL;
7452 break;
7453 case 1: code = BFD_RELOC_8_PCREL; break;
7454 case 2: code = BFD_RELOC_16_PCREL; break;
7455 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7456#ifdef BFD64
7457 case 8: code = BFD_RELOC_64_PCREL; break;
7458#endif
93382f6d
AM		 7459 }
7460 }
7461 else
7462 {
7463 switch (fixp->fx_size)
7464 {
7465 default:
b091f402
AM		 7466 as_bad_where (fixp->fx_file, fixp->fx_line,
7467 _("can not do %d byte relocation"),
7468 fixp->fx_size);
93382f6d
AM		 7469 code = BFD_RELOC_32;
7470 break;
7471 case 1: code = BFD_RELOC_8; break;
7472 case 2: code = BFD_RELOC_16; break;
7473 case 4: code = BFD_RELOC_32; break;
937149dd 7474#ifdef BFD64
3e73aa7c 7475 case 8: code = BFD_RELOC_64; break;
937149dd 7476#endif
93382f6d 7477 }
252b5132
RH		 7478 }
7479 break;
7480 }
252b5132 7481
d182319b
JB		 7482 if ((code == BFD_RELOC_32
7483 || code == BFD_RELOC_32_PCREL
7484 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7485 && GOT_symbol
7486 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7487 {
4fa24527 7488 if (!object_64bit)
d6ab8113
JB		 7489 code = BFD_RELOC_386_GOTPC;
7490 else
7491 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7492 }
7b81dfbb
AJ		 7493 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7494 && GOT_symbol
7495 && fixp->fx_addsy == GOT_symbol)
7496 {
7497 code = BFD_RELOC_X86_64_GOTPC64;
7498 }
252b5132
RH		 7499
7500 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7501 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7502 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7503
7504 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7505
3e73aa7c
JH		 7506 if (!use_rela_relocations)
7507 {
7508 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7509 vtable entry to be used in the relocation's section offset. */
7510 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7511 rel->address = fixp->fx_offset;
252b5132 7512
c6682705 7513 rel->addend = 0;
3e73aa7c
JH		 7514 }
7515 /* Use the rela in 64bit mode. */
252b5132 7516 else
3e73aa7c 7517 {
062cd5e7
AS		 7518 if (!fixp->fx_pcrel)
7519 rel->addend = fixp->fx_offset;
7520 else
7521 switch (code)
7522 {
7523 case BFD_RELOC_X86_64_PLT32:
7524 case BFD_RELOC_X86_64_GOT32:
7525 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7526 case BFD_RELOC_X86_64_TLSGD:
7527 case BFD_RELOC_X86_64_TLSLD:
7528 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7529 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7530 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7531 rel->addend = fixp->fx_offset - fixp->fx_size;
7532 break;
7533 default:
7534 rel->addend = (section->vma
7535 - fixp->fx_size
7536 + fixp->fx_addnumber
7537 + md_pcrel_from (fixp));
7538 break;
7539 }
3e73aa7c
JH		 7540 }
7541
252b5132
RH		 7542 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7543 if (rel->howto == NULL)
7544 {
7545 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7546 _("cannot represent relocation type %s"),
252b5132
RH		 7547 bfd_get_reloc_code_name (code));
7548 /* Set howto to a garbage value so that we can keep going. */
7549 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7550 assert (rel->howto != NULL);
7551 }
7552
7553 return rel;
7554}
7555
64a0c779
DN		 7556\f
7557/* Parse operands using Intel syntax. This implements a recursive descent
7558 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7559 Programmer's Guide.
7560
7561 FIXME: We do not recognize the full operand grammar defined in the MASM
7562 documentation. In particular, all the structure/union and
7563 high-level macro operands are missing.
7564
7565 Uppercase words are terminals, lower case words are non-terminals.
7566 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7567 bars '|' denote choices. Most grammar productions are implemented in
7568 functions called 'intel_<production>'.
7569
7570 Initial production is 'expr'.
7571
9306ca4a 7572 addOp + | -
64a0c779
DN		 7573
7574 alpha [a-zA-Z]
7575
9306ca4a
JB		 7576 binOp & | AND | \| | OR | ^ | XOR
7577
64a0c779
DN		 7578 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7579
7580 constant digits [[ radixOverride ]]
7581
9306ca4a 7582 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7583
7584 digits decdigit
b77a7acd
AJ		 7585 | digits decdigit
7586 | digits hexdigit
64a0c779
DN		 7587
7588 decdigit [0-9]
7589
9306ca4a
JB		 7590 e04 e04 addOp e05
7591 | e05
7592
7593 e05 e05 binOp e06
b77a7acd 7594 | e06
64a0c779
DN		 7595
7596 e06 e06 mulOp e09
b77a7acd 7597 | e09
64a0c779
DN		 7598
7599 e09 OFFSET e10
a724f0f4
JB		 7600 | SHORT e10
7601 | + e10
7602 | - e10
9306ca4a
JB		 7603 | ~ e10
7604 | NOT e10
64a0c779
DN		 7605 | e09 PTR e10
7606 | e09 : e10
7607 | e10
7608
7609 e10 e10 [ expr ]
b77a7acd 7610 | e11
64a0c779
DN		 7611
7612 e11 ( expr )
b77a7acd 7613 | [ expr ]
64a0c779
DN		 7614 | constant
7615 | dataType
7616 | id
7617 | $
7618 | register
7619
a724f0f4 7620 => expr expr cmpOp e04
9306ca4a 7621 | e04
64a0c779
DN		 7622
7623 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7624 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7625
7626 hexdigit a | b | c | d | e | f
b77a7acd 7627 | A | B | C | D | E | F
64a0c779
DN		 7628
7629 id alpha
b77a7acd 7630 | id alpha
64a0c779
DN		 7631 | id decdigit
7632
9306ca4a 7633 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7634
7635 quote " | '
7636
7637 register specialRegister
b77a7acd 7638 | gpRegister
64a0c779
DN		 7639 | byteRegister
7640
7641 segmentRegister CS | DS | ES | FS | GS | SS
7642
9306ca4a 7643 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7644 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7645 | TR3 | TR4 | TR5 | TR6 | TR7
7646
64a0c779
DN		 7647 We simplify the grammar in obvious places (e.g., register parsing is
7648 done by calling parse_register) and eliminate immediate left recursion
7649 to implement a recursive-descent parser.
7650
a724f0f4
JB		 7651 expr e04 expr'
7652
7653 expr' cmpOp e04 expr'
7654 | Empty
9306ca4a
JB		 7655
7656 e04 e05 e04'
7657
7658 e04' addOp e05 e04'
7659 | Empty
64a0c779
DN		 7660
7661 e05 e06 e05'
7662
9306ca4a 7663 e05' binOp e06 e05'
b77a7acd 7664 | Empty
64a0c779
DN		 7665
7666 e06 e09 e06'
7667
7668 e06' mulOp e09 e06'
b77a7acd 7669 | Empty
64a0c779
DN		 7670
7671 e09 OFFSET e10 e09'
a724f0f4
JB		 7672 | SHORT e10'
7673 | + e10'
7674 | - e10'
7675 | ~ e10'
7676 | NOT e10'
b77a7acd 7677 | e10 e09'
64a0c779
DN		 7678
7679 e09' PTR e10 e09'
b77a7acd 7680 | : e10 e09'
64a0c779
DN		 7681 | Empty
7682
7683 e10 e11 e10'
7684
7685 e10' [ expr ] e10'
b77a7acd 7686 | Empty
64a0c779
DN		 7687
7688 e11 ( expr )
b77a7acd 7689 | [ expr ]
64a0c779
DN		 7690 | BYTE
7691 | WORD
7692 | DWORD
9306ca4a 7693 | FWORD
64a0c779 7694 | QWORD
9306ca4a
JB		 7695 | TBYTE
7696 | OWORD
7697 | XMMWORD
64a0c779
DN		 7698 | .
7699 | $
7700 | register
7701 | id
7702 | constant */
7703
7704/* Parsing structure for the intel syntax parser. Used to implement the
7705 semantic actions for the operand grammar. */
7706struct intel_parser_s
7707 {
7708 char *op_string; /* The string being parsed. */
7709 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7710 int op_modifier; /* Operand modifier. */
64a0c779 7711 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7712 int in_offset; /* >=1 if parsing operand of offset. */
7713 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7714 const reg_entry *reg; /* Last register reference found. */
7715 char *disp; /* Displacement string being built. */
a724f0f4 7716 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7717 };
7718
7719static struct intel_parser_s intel_parser;
7720
7721/* Token structure for parsing intel syntax. */
7722struct intel_token
7723 {
7724 int code; /* Token code. */
7725 const reg_entry *reg; /* Register entry for register tokens. */
7726 char *str; /* String representation. */
7727 };
7728
7729static struct intel_token cur_token, prev_token;
7730
50705ef4
AM		 7731/* Token codes for the intel parser. Since T_SHORT is already used
7732 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7733#define T_NIL -1
7734#define T_CONST 1
7735#define T_REG 2
7736#define T_BYTE 3
7737#define T_WORD 4
9306ca4a
JB		 7738#define T_DWORD 5
7739#define T_FWORD 6
7740#define T_QWORD 7
7741#define T_TBYTE 8
7742#define T_XMMWORD 9
50705ef4 7743#undef T_SHORT
9306ca4a
JB		 7744#define T_SHORT 10
7745#define T_OFFSET 11
7746#define T_PTR 12
7747#define T_ID 13
7748#define T_SHL 14
7749#define T_SHR 15
64a0c779
DN		 7750
7751/* Prototypes for intel parser functions. */
e3bb37b5
L		 7752static int intel_match_token (int);
7753static void intel_putback_token (void);
7754static void intel_get_token (void);
7755static int intel_expr (void);
7756static int intel_e04 (void);
7757static int intel_e05 (void);
7758static int intel_e06 (void);
7759static int intel_e09 (void);
7760static int intel_e10 (void);
7761static int intel_e11 (void);
64a0c779 7762
64a0c779 7763static int
e3bb37b5 7764i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7765{
7766 int ret;
7767 char *p;
7768
a724f0f4
JB		 7769 p = intel_parser.op_string = xstrdup (operand_string);
7770 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7771
7772 for (;;)
64a0c779 7773 {
a724f0f4
JB		 7774 /* Initialize token holders. */
7775 cur_token.code = prev_token.code = T_NIL;
7776 cur_token.reg = prev_token.reg = NULL;
7777 cur_token.str = prev_token.str = NULL;
7778
7779 /* Initialize parser structure. */
7780 intel_parser.got_a_float = got_a_float;
7781 intel_parser.op_modifier = 0;
7782 intel_parser.is_mem = 0;
7783 intel_parser.in_offset = 0;
7784 intel_parser.in_bracket = 0;
7785 intel_parser.reg = NULL;
7786 intel_parser.disp[0] = '\0';
7787 intel_parser.next_operand = NULL;
7788
7789 /* Read the first token and start the parser. */
7790 intel_get_token ();
7791 ret = intel_expr ();
7792
7793 if (!ret)
7794 break;
7795
9306ca4a
JB		 7796 if (cur_token.code != T_NIL)
7797 {
7798 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7799 current_templates->start->name, cur_token.str);
7800 ret = 0;
7801 }
64a0c779
DN		 7802 /* If we found a memory reference, hand it over to i386_displacement
7803 to fill in the rest of the operand fields. */
9306ca4a 7804 else if (intel_parser.is_mem)
64a0c779
DN		 7805 {
7806 if ((i.mem_operands == 1
40fb9820 7807 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7808 || i.mem_operands == 2)
7809 {
7810 as_bad (_("too many memory references for '%s'"),
7811 current_templates->start->name);
7812 ret = 0;
7813 }
7814 else
7815 {
7816 char *s = intel_parser.disp;
7817 i.mem_operands++;
7818
a724f0f4
JB		 7819 if (!quiet_warnings && intel_parser.is_mem < 0)
7820 /* See the comments in intel_bracket_expr. */
7821 as_warn (_("Treating `%s' as memory reference"), operand_string);
7822
64a0c779
DN		 7823 /* Add the displacement expression. */
7824 if (*s != '\0')
a4622f40
AM		 7825 ret = i386_displacement (s, s + strlen (s));
7826 if (ret)
a724f0f4
JB		 7827 {
7828 /* Swap base and index in 16-bit memory operands like
7829 [si+bx]. Since i386_index_check is also used in AT&T
7830 mode we have to do that here. */
7831 if (i.base_reg
7832 && i.index_reg
40fb9820
L		 7833 && i.base_reg->reg_type.bitfield.reg16
7834 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7835 && i.base_reg->reg_num >= 6
7836 && i.index_reg->reg_num < 6)
7837 {
7838 const reg_entry *base = i.index_reg;
7839
7840 i.index_reg = i.base_reg;
7841 i.base_reg = base;
7842 }
7843 ret = i386_index_check (operand_string);
7844 }
64a0c779
DN		 7845 }
7846 }
7847
7848 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7849 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7850 || intel_parser.reg == NULL)
7851 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7852
7853 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7854 ret = 0;
a724f0f4
JB		 7855 if (!ret || !intel_parser.next_operand)
7856 break;
7857 intel_parser.op_string = intel_parser.next_operand;
7858 this_operand = i.operands++;
64a0c779
DN		 7859 }
7860
7861 free (p);
7862 free (intel_parser.disp);
7863
7864 return ret;
7865}
7866
a724f0f4
JB		 7867#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7868
7869/* expr e04 expr'
7870
7871 expr' cmpOp e04 expr'
7872 | Empty */
64a0c779 7873static int
e3bb37b5 7874intel_expr (void)
64a0c779 7875{
a724f0f4
JB		 7876 /* XXX Implement the comparison operators. */
7877 return intel_e04 ();
9306ca4a
JB		 7878}
7879
a724f0f4 7880/* e04 e05 e04'
9306ca4a 7881
a724f0f4 7882 e04' addOp e05 e04'
9306ca4a
JB		 7883 | Empty */
7884static int
e3bb37b5 7885intel_e04 (void)
9306ca4a 7886{
a724f0f4 7887 int nregs = -1;
9306ca4a 7888
a724f0f4 7889 for (;;)
9306ca4a 7890 {
a724f0f4
JB		 7891 if (!intel_e05())
7892 return 0;
9306ca4a 7893
a724f0f4
JB		 7894 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7895 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7896
a724f0f4
JB		 7897 if (cur_token.code == '+')
7898 nregs = -1;
7899 else if (cur_token.code == '-')
7900 nregs = NUM_ADDRESS_REGS;
7901 else
7902 return 1;
64a0c779 7903
a724f0f4
JB		 7904 strcat (intel_parser.disp, cur_token.str);
7905 intel_match_token (cur_token.code);
7906 }
64a0c779
DN		 7907}
7908
64a0c779
DN		 7909/* e05 e06 e05'
7910
9306ca4a 7911 e05' binOp e06 e05'
64a0c779
DN		 7912 | Empty */
7913static int
e3bb37b5 7914intel_e05 (void)
64a0c779 7915{
a724f0f4 7916 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7917
a724f0f4 7918 for (;;)
64a0c779 7919 {
a724f0f4
JB		 7920 if (!intel_e06())
7921 return 0;
7922
4eed87de
AM		 7923 if (cur_token.code == '&'
7924 || cur_token.code == '|'
7925 || cur_token.code == '^')
a724f0f4
JB		 7926 {
7927 char str[2];
7928
7929 str[0] = cur_token.code;
7930 str[1] = 0;
7931 strcat (intel_parser.disp, str);
7932 }
7933 else
7934 break;
9306ca4a 7935
64a0c779
DN		 7936 intel_match_token (cur_token.code);
7937
a724f0f4
JB		 7938 if (nregs < 0)
7939 nregs = ~nregs;
64a0c779 7940 }
a724f0f4
JB		 7941 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7942 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7943 return 1;
4a1805b1 7944}
64a0c779
DN		 7945
7946/* e06 e09 e06'
7947
7948 e06' mulOp e09 e06'
b77a7acd 7949 | Empty */
64a0c779 7950static int
e3bb37b5 7951intel_e06 (void)
64a0c779 7952{
a724f0f4 7953 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7954
a724f0f4 7955 for (;;)
64a0c779 7956 {
a724f0f4
JB		 7957 if (!intel_e09())
7958 return 0;
9306ca4a 7959
4eed87de
AM		 7960 if (cur_token.code == '*'
7961 || cur_token.code == '/'
7962 || cur_token.code == '%')
a724f0f4
JB		 7963 {
7964 char str[2];
9306ca4a 7965
a724f0f4
JB		 7966 str[0] = cur_token.code;
7967 str[1] = 0;
7968 strcat (intel_parser.disp, str);
7969 }
7970 else if (cur_token.code == T_SHL)
7971 strcat (intel_parser.disp, "<<");
7972 else if (cur_token.code == T_SHR)
7973 strcat (intel_parser.disp, ">>");
7974 else
7975 break;
9306ca4a 7976
64e74474 7977 intel_match_token (cur_token.code);
64a0c779 7978
a724f0f4
JB		 7979 if (nregs < 0)
7980 nregs = ~nregs;
64a0c779 7981 }
a724f0f4
JB		 7982 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7983 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
7984 return 1;
64a0c779
DN		 7985}
7986
a724f0f4
JB		 7987/* e09 OFFSET e09
7988 | SHORT e09
7989 | + e09
7990 | - e09
7991 | ~ e09
7992 | NOT e09
9306ca4a
JB		 7993 | e10 e09'
7994
64a0c779 7995 e09' PTR e10 e09'
b77a7acd 7996 | : e10 e09'
64a0c779
DN		 7997 | Empty */
7998static int
e3bb37b5 7999intel_e09 (void)
64a0c779 8000{
a724f0f4
JB		 8001 int nregs = ~NUM_ADDRESS_REGS;
8002 int in_offset = 0;
8003
8004 for (;;)
64a0c779 8005 {
a724f0f4
JB		 8006 /* Don't consume constants here. */
8007 if (cur_token.code == '+' || cur_token.code == '-')
8008 {
8009 /* Need to look one token ahead - if the next token
8010 is a constant, the current token is its sign. */
8011 int next_code;
8012
8013 intel_match_token (cur_token.code);
8014 next_code = cur_token.code;
8015 intel_putback_token ();
8016 if (next_code == T_CONST)
8017 break;
8018 }
8019
8020 /* e09 OFFSET e09 */
8021 if (cur_token.code == T_OFFSET)
8022 {
8023 if (!in_offset++)
8024 ++intel_parser.in_offset;
8025 }
8026
8027 /* e09 SHORT e09 */
8028 else if (cur_token.code == T_SHORT)
8029 intel_parser.op_modifier |= 1 << T_SHORT;
8030
8031 /* e09 + e09 */
8032 else if (cur_token.code == '+')
8033 strcat (intel_parser.disp, "+");
8034
8035 /* e09 - e09
8036 | ~ e09
8037 | NOT e09 */
8038 else if (cur_token.code == '-' || cur_token.code == '~')
8039 {
8040 char str[2];
64a0c779 8041
a724f0f4
JB		 8042 if (nregs < 0)
8043 nregs = ~nregs;
8044 str[0] = cur_token.code;
8045 str[1] = 0;
8046 strcat (intel_parser.disp, str);
8047 }
8048
8049 /* e09 e10 e09' */
8050 else
8051 break;
8052
8053 intel_match_token (cur_token.code);
64a0c779
DN		 8054 }
8055
a724f0f4 8056 for (;;)
9306ca4a 8057 {
a724f0f4
JB		 8058 if (!intel_e10 ())
8059 return 0;
9306ca4a 8060
a724f0f4
JB		 8061 /* e09' PTR e10 e09' */
8062 if (cur_token.code == T_PTR)
8063 {
8064 char suffix;
9306ca4a 8065
a724f0f4
JB		 8066 if (prev_token.code == T_BYTE)
8067 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 8068
a724f0f4
JB		 8069 else if (prev_token.code == T_WORD)
8070 {
8071 if (current_templates->start->name[0] == 'l'
8072 && current_templates->start->name[2] == 's'
8073 && current_templates->start->name[3] == 0)
8074 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8075 else if (intel_parser.got_a_float == 2) /* "fi..." */
8076 suffix = SHORT_MNEM_SUFFIX;
8077 else
8078 suffix = WORD_MNEM_SUFFIX;
8079 }
64a0c779 8080
a724f0f4
JB		 8081 else if (prev_token.code == T_DWORD)
8082 {
8083 if (current_templates->start->name[0] == 'l'
8084 && current_templates->start->name[2] == 's'
8085 && current_templates->start->name[3] == 0)
8086 suffix = WORD_MNEM_SUFFIX;
8087 else if (flag_code == CODE_16BIT
40fb9820
L		 8088 && (current_templates->start->opcode_modifier.jump
8089 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8090 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8091 else if (intel_parser.got_a_float == 1) /* "f..." */
8092 suffix = SHORT_MNEM_SUFFIX;
8093 else
8094 suffix = LONG_MNEM_SUFFIX;
8095 }
9306ca4a 8096
a724f0f4
JB		 8097 else if (prev_token.code == T_FWORD)
8098 {
8099 if (current_templates->start->name[0] == 'l'
8100 && current_templates->start->name[2] == 's'
8101 && current_templates->start->name[3] == 0)
8102 suffix = LONG_MNEM_SUFFIX;
8103 else if (!intel_parser.got_a_float)
8104 {
8105 if (flag_code == CODE_16BIT)
8106 add_prefix (DATA_PREFIX_OPCODE);
8107 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8108 }
8109 else
8110 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8111 }
64a0c779 8112
a724f0f4
JB		 8113 else if (prev_token.code == T_QWORD)
8114 {
8115 if (intel_parser.got_a_float == 1) /* "f..." */
8116 suffix = LONG_MNEM_SUFFIX;
8117 else
8118 suffix = QWORD_MNEM_SUFFIX;
8119 }
64a0c779 8120
a724f0f4
JB		 8121 else if (prev_token.code == T_TBYTE)
8122 {
8123 if (intel_parser.got_a_float == 1)
8124 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8125 else
8126 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8127 }
9306ca4a 8128
a724f0f4 8129 else if (prev_token.code == T_XMMWORD)
9306ca4a 8130 {
582d5edd 8131 suffix = XMMWORD_MNEM_SUFFIX;
9306ca4a 8132 }
64a0c779 8133
f16b83df 8134 else
a724f0f4
JB		 8135 {
8136 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8137 return 0;
8138 }
8139
435acd52
JB		 8140 /* Operands for jump/call using 'ptr' notation denote absolute
8141 addresses. */
40fb9820
L		 8142 if (current_templates->start->opcode_modifier.jump
8143 || current_templates->start->opcode_modifier.jumpdword)
8144 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8145
a724f0f4
JB		 8146 if (current_templates->start->base_opcode == 0x8d /* lea */)
8147 ;
8148 else if (!i.suffix)
8149 i.suffix = suffix;
8150 else if (i.suffix != suffix)
8151 {
8152 as_bad (_("Conflicting operand modifiers"));
8153 return 0;
8154 }
64a0c779 8155
9306ca4a
JB		 8156 }
8157
a724f0f4
JB		 8158 /* e09' : e10 e09' */
8159 else if (cur_token.code == ':')
9306ca4a 8160 {
a724f0f4
JB		 8161 if (prev_token.code != T_REG)
8162 {
8163 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8164 segment/group identifier (which we don't have), using comma
8165 as the operand separator there is even less consistent, since
8166 there all branches only have a single operand. */
8167 if (this_operand != 0
8168 || intel_parser.in_offset
8169 || intel_parser.in_bracket
40fb9820
L		 8170 || (!current_templates->start->opcode_modifier.jump
8171 && !current_templates->start->opcode_modifier.jumpdword
8172 && !current_templates->start->opcode_modifier.jumpintersegment
8173 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8174 return intel_match_token (T_NIL);
8175 /* Remember the start of the 2nd operand and terminate 1st
8176 operand here.
8177 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8178 another expression), but it gets at least the simplest case
8179 (a plain number or symbol on the left side) right. */
8180 intel_parser.next_operand = intel_parser.op_string;
8181 *--intel_parser.op_string = '\0';
8182 return intel_match_token (':');
8183 }
9306ca4a 8184 }
64a0c779 8185
a724f0f4 8186 /* e09' Empty */
64a0c779 8187 else
a724f0f4 8188 break;
64a0c779 8189
a724f0f4
JB		 8190 intel_match_token (cur_token.code);
8191
8192 }
8193
8194 if (in_offset)
8195 {
8196 --intel_parser.in_offset;
8197 if (nregs < 0)
8198 nregs = ~nregs;
8199 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8200 {
a724f0f4 8201 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8202 return 0;
8203 }
a724f0f4
JB		 8204 intel_parser.op_modifier |= 1 << T_OFFSET;
8205 }
9306ca4a 8206
a724f0f4
JB		 8207 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8208 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8209 return 1;
8210}
64a0c779 8211
a724f0f4 8212static int
e3bb37b5 8213intel_bracket_expr (void)
a724f0f4
JB		 8214{
8215 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8216 const char *start = intel_parser.op_string;
8217 int len;
8218
8219 if (i.op[this_operand].regs)
8220 return intel_match_token (T_NIL);
8221
8222 intel_match_token ('[');
8223
8224 /* Mark as a memory operand only if it's not already known to be an
8225 offset expression. If it's an offset expression, we need to keep
8226 the brace in. */
8227 if (!intel_parser.in_offset)
8228 {
8229 ++intel_parser.in_bracket;
435acd52
JB		 8230
8231 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8232 if (current_templates->start->opcode_modifier.jump
8233 || current_templates->start->opcode_modifier.jumpdword)
8234 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8235
a724f0f4
JB		 8236 /* Unfortunately gas always diverged from MASM in a respect that can't
8237 be easily fixed without risking to break code sequences likely to be
8238 encountered (the testsuite even check for this): MASM doesn't consider
8239 an expression inside brackets unconditionally as a memory reference.
8240 When that is e.g. a constant, an offset expression, or the sum of the
8241 two, this is still taken as a constant load. gas, however, always
8242 treated these as memory references. As a compromise, we'll try to make
8243 offset expressions inside brackets work the MASM way (since that's
8244 less likely to be found in real world code), but make constants alone
8245 continue to work the traditional gas way. In either case, issue a
8246 warning. */
8247 intel_parser.op_modifier &= ~was_offset;
64a0c779 8248 }
a724f0f4 8249 else
64e74474 8250 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8251
8252 /* Add a '+' to the displacement string if necessary. */
8253 if (*intel_parser.disp != '\0'
8254 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8255 strcat (intel_parser.disp, "+");
64a0c779 8256
a724f0f4
JB		 8257 if (intel_expr ()
8258 && (len = intel_parser.op_string - start - 1,
8259 intel_match_token (']')))
64a0c779 8260 {
a724f0f4
JB		 8261 /* Preserve brackets when the operand is an offset expression. */
8262 if (intel_parser.in_offset)
8263 strcat (intel_parser.disp, "]");
8264 else
8265 {
8266 --intel_parser.in_bracket;
8267 if (i.base_reg || i.index_reg)
8268 intel_parser.is_mem = 1;
8269 if (!intel_parser.is_mem)
8270 {
8271 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8272 /* Defer the warning until all of the operand was parsed. */
8273 intel_parser.is_mem = -1;
8274 else if (!quiet_warnings)
4eed87de
AM		 8275 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8276 len, start, len, start);
a724f0f4
JB		 8277 }
8278 }
8279 intel_parser.op_modifier |= was_offset;
64a0c779 8280
a724f0f4 8281 return 1;
64a0c779 8282 }
a724f0f4 8283 return 0;
64a0c779
DN		 8284}
8285
8286/* e10 e11 e10'
8287
8288 e10' [ expr ] e10'
b77a7acd 8289 | Empty */
64a0c779 8290static int
e3bb37b5 8291intel_e10 (void)
64a0c779 8292{
a724f0f4
JB		 8293 if (!intel_e11 ())
8294 return 0;
64a0c779 8295
a724f0f4 8296 while (cur_token.code == '[')
64a0c779 8297 {
a724f0f4 8298 if (!intel_bracket_expr ())
21d6c4af 8299 return 0;
64a0c779
DN		 8300 }
8301
a724f0f4 8302 return 1;
64a0c779
DN		 8303}
8304
64a0c779 8305/* e11 ( expr )
b77a7acd 8306 | [ expr ]
64a0c779
DN		 8307 | BYTE
8308 | WORD
8309 | DWORD
9306ca4a 8310 | FWORD
64a0c779 8311 | QWORD
9306ca4a
JB		 8312 | TBYTE
8313 | OWORD
8314 | XMMWORD
4a1805b1 8315 | $
64a0c779
DN		 8316 | .
8317 | register
8318 | id
8319 | constant */
8320static int
e3bb37b5 8321intel_e11 (void)
64a0c779 8322{
a724f0f4 8323 switch (cur_token.code)
64a0c779 8324 {
a724f0f4
JB		 8325 /* e11 ( expr ) */
8326 case '(':
64a0c779
DN		 8327 intel_match_token ('(');
8328 strcat (intel_parser.disp, "(");
8329
8330 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8331 {
8332 strcat (intel_parser.disp, ")");
8333 return 1;
8334 }
a724f0f4 8335 return 0;
4a1805b1 8336
a724f0f4
JB		 8337 /* e11 [ expr ] */
8338 case '[':
a724f0f4 8339 return intel_bracket_expr ();
64a0c779 8340
a724f0f4
JB		 8341 /* e11 $
8342 | . */
8343 case '.':
64a0c779
DN		 8344 strcat (intel_parser.disp, cur_token.str);
8345 intel_match_token (cur_token.code);
21d6c4af
DN		 8346
8347 /* Mark as a memory operand only if it's not already known to be an
8348 offset expression. */
a724f0f4 8349 if (!intel_parser.in_offset)
21d6c4af 8350 intel_parser.is_mem = 1;
64a0c779
DN		 8351
8352 return 1;
64a0c779 8353
a724f0f4
JB		 8354 /* e11 register */
8355 case T_REG:
8356 {
8357 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8358
a724f0f4 8359 intel_match_token (T_REG);
64a0c779 8360
a724f0f4
JB		 8361 /* Check for segment change. */
8362 if (cur_token.code == ':')
8363 {
40fb9820
L		 8364 if (!reg->reg_type.bitfield.sreg2
8365 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8366 {
4eed87de
AM		 8367 as_bad (_("`%s' is not a valid segment register"),
8368 reg->reg_name);
a724f0f4
JB		 8369 return 0;
8370 }
8371 else if (i.seg[i.mem_operands])
8372 as_warn (_("Extra segment override ignored"));
8373 else
8374 {
8375 if (!intel_parser.in_offset)
8376 intel_parser.is_mem = 1;
8377 switch (reg->reg_num)
8378 {
8379 case 0:
8380 i.seg[i.mem_operands] = &es;
8381 break;
8382 case 1:
8383 i.seg[i.mem_operands] = &cs;
8384 break;
8385 case 2:
8386 i.seg[i.mem_operands] = &ss;
8387 break;
8388 case 3:
8389 i.seg[i.mem_operands] = &ds;
8390 break;
8391 case 4:
8392 i.seg[i.mem_operands] = &fs;
8393 break;
8394 case 5:
8395 i.seg[i.mem_operands] = &gs;
8396 break;
8397 }
8398 }
8399 }
64a0c779 8400
a724f0f4
JB		 8401 /* Not a segment register. Check for register scaling. */
8402 else if (cur_token.code == '*')
8403 {
8404 if (!intel_parser.in_bracket)
8405 {
8406 as_bad (_("Register scaling only allowed in memory operands"));
8407 return 0;
8408 }
64a0c779 8409
40fb9820 8410 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8411 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8412 else if (i.index_reg)
8413 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8414
a724f0f4
JB		 8415 /* What follows must be a valid scale. */
8416 intel_match_token ('*');
8417 i.index_reg = reg;
40fb9820 8418 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8419
a724f0f4
JB		 8420 /* Set the scale after setting the register (otherwise,
8421 i386_scale will complain) */
8422 if (cur_token.code == '+' || cur_token.code == '-')
8423 {
8424 char *str, sign = cur_token.code;
8425 intel_match_token (cur_token.code);
8426 if (cur_token.code != T_CONST)
8427 {
8428 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8429 cur_token.str);
8430 return 0;
8431 }
8432 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8433 strcpy (str + 1, cur_token.str);
8434 *str = sign;
8435 if (!i386_scale (str))
8436 return 0;
8437 free (str);
8438 }
8439 else if (!i386_scale (cur_token.str))
64a0c779 8440 return 0;
a724f0f4
JB		 8441 intel_match_token (cur_token.code);
8442 }
64a0c779 8443
a724f0f4
JB		 8444 /* No scaling. If this is a memory operand, the register is either a
8445 base register (first occurrence) or an index register (second
8446 occurrence). */
7b0441f6 8447 else if (intel_parser.in_bracket)
a724f0f4 8448 {
64a0c779 8449
a724f0f4
JB		 8450 if (!i.base_reg)
8451 i.base_reg = reg;
8452 else if (!i.index_reg)
8453 i.index_reg = reg;
8454 else
8455 {
8456 as_bad (_("Too many register references in memory operand"));
8457 return 0;
8458 }
64a0c779 8459
40fb9820 8460 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8461 }
4a1805b1 8462
4d1bb795
JB		 8463 /* It's neither base nor index. */
8464 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8465 {
40fb9820
L		 8466 i386_operand_type temp = reg->reg_type;
8467 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8468 i.types[this_operand] = operand_type_or (i.types[this_operand],
8469 temp);
a724f0f4
JB		 8470 i.op[this_operand].regs = reg;
8471 i.reg_operands++;
8472 }
8473 else
8474 {
8475 as_bad (_("Invalid use of register"));
8476 return 0;
8477 }
64a0c779 8478
a724f0f4
JB		 8479 /* Since registers are not part of the displacement string (except
8480 when we're parsing offset operands), we may need to remove any
8481 preceding '+' from the displacement string. */
8482 if (*intel_parser.disp != '\0'
8483 && !intel_parser.in_offset)
8484 {
8485 char *s = intel_parser.disp;
8486 s += strlen (s) - 1;
8487 if (*s == '+')
8488 *s = '\0';
8489 }
4a1805b1 8490
a724f0f4
JB		 8491 return 1;
8492 }
8493
8494 /* e11 BYTE
8495 | WORD
8496 | DWORD
8497 | FWORD
8498 | QWORD
8499 | TBYTE
8500 | OWORD
8501 | XMMWORD */
8502 case T_BYTE:
8503 case T_WORD:
8504 case T_DWORD:
8505 case T_FWORD:
8506 case T_QWORD:
8507 case T_TBYTE:
8508 case T_XMMWORD:
8509 intel_match_token (cur_token.code);
64a0c779 8510
a724f0f4
JB		 8511 if (cur_token.code == T_PTR)
8512 return 1;
8513
8514 /* It must have been an identifier. */
8515 intel_putback_token ();
8516 cur_token.code = T_ID;
8517 /* FALLTHRU */
8518
8519 /* e11 id
8520 | constant */
8521 case T_ID:
8522 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8523 {
8524 symbolS *symbolP;
8525
a724f0f4
JB		 8526 /* The identifier represents a memory reference only if it's not
8527 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8528 symbolP = symbol_find(cur_token.str);
8529 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8530 intel_parser.is_mem = 1;
8531 }
a724f0f4 8532 /* FALLTHRU */
64a0c779 8533
a724f0f4
JB		 8534 case T_CONST:
8535 case '-':
8536 case '+':
8537 {
8538 char *save_str, sign = 0;
64a0c779 8539
a724f0f4
JB		 8540 /* Allow constants that start with `+' or `-'. */
8541 if (cur_token.code == '-' || cur_token.code == '+')
8542 {
8543 sign = cur_token.code;
8544 intel_match_token (cur_token.code);
8545 if (cur_token.code != T_CONST)
8546 {
8547 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8548 cur_token.str);
8549 return 0;
8550 }
8551 }
64a0c779 8552
a724f0f4
JB		 8553 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8554 strcpy (save_str + !!sign, cur_token.str);
8555 if (sign)
8556 *save_str = sign;
64a0c779 8557
a724f0f4
JB		 8558 /* Get the next token to check for register scaling. */
8559 intel_match_token (cur_token.code);
64a0c779 8560
4eed87de
AM		 8561 /* Check if this constant is a scaling factor for an
8562 index register. */
a724f0f4
JB		 8563 if (cur_token.code == '*')
8564 {
8565 if (intel_match_token ('*') && cur_token.code == T_REG)
8566 {
8567 const reg_entry *reg = cur_token.reg;
8568
8569 if (!intel_parser.in_bracket)
8570 {
4eed87de
AM		 8571 as_bad (_("Register scaling only allowed "
8572 "in memory operands"));
a724f0f4
JB		 8573 return 0;
8574 }
8575
4eed87de
AM		 8576 /* Disallow things like [1*si].
8577 sp and esp are invalid as index. */
40fb9820 8578 if (reg->reg_type.bitfield.reg16)
4eed87de 8579 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8580 else if (i.index_reg)
4eed87de 8581 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8582
8583 /* The constant is followed by `* reg', so it must be
8584 a valid scale. */
8585 i.index_reg = reg;
40fb9820 8586 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8587
8588 /* Set the scale after setting the register (otherwise,
8589 i386_scale will complain) */
8590 if (!i386_scale (save_str))
64a0c779 8591 return 0;
a724f0f4
JB		 8592 intel_match_token (T_REG);
8593
8594 /* Since registers are not part of the displacement
8595 string, we may need to remove any preceding '+' from
8596 the displacement string. */
8597 if (*intel_parser.disp != '\0')
8598 {
8599 char *s = intel_parser.disp;
8600 s += strlen (s) - 1;
8601 if (*s == '+')
8602 *s = '\0';
8603 }
8604
8605 free (save_str);
8606
8607 return 1;
8608 }
64a0c779 8609
a724f0f4
JB		 8610 /* The constant was not used for register scaling. Since we have
8611 already consumed the token following `*' we now need to put it
8612 back in the stream. */
64a0c779 8613 intel_putback_token ();
a724f0f4 8614 }
64a0c779 8615
a724f0f4
JB		 8616 /* Add the constant to the displacement string. */
8617 strcat (intel_parser.disp, save_str);
8618 free (save_str);
64a0c779 8619
a724f0f4
JB		 8620 return 1;
8621 }
64a0c779
DN		 8622 }
8623
64a0c779
DN		 8624 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8625 return 0;
8626}
8627
64a0c779
DN		 8628/* Match the given token against cur_token. If they match, read the next
8629 token from the operand string. */
8630static int
e3bb37b5 8631intel_match_token (int code)
64a0c779
DN		 8632{
8633 if (cur_token.code == code)
8634 {
8635 intel_get_token ();
8636 return 1;
8637 }
8638 else
8639 {
0477af35 8640 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8641 return 0;
8642 }
8643}
8644
64a0c779
DN		 8645/* Read a new token from intel_parser.op_string and store it in cur_token. */
8646static void
e3bb37b5 8647intel_get_token (void)
64a0c779
DN		 8648{
8649 char *end_op;
8650 const reg_entry *reg;
8651 struct intel_token new_token;
8652
8653 new_token.code = T_NIL;
8654 new_token.reg = NULL;
8655 new_token.str = NULL;
8656
4a1805b1 8657 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8658 cur_token to prev_token. */
8659 if (prev_token.str)
8660 free (prev_token.str);
8661
8662 prev_token = cur_token;
8663
8664 /* Skip whitespace. */
8665 while (is_space_char (*intel_parser.op_string))
8666 intel_parser.op_string++;
8667
8668 /* Return an empty token if we find nothing else on the line. */
8669 if (*intel_parser.op_string == '\0')
8670 {
8671 cur_token = new_token;
8672 return;
8673 }
8674
8675 /* The new token cannot be larger than the remainder of the operand
8676 string. */
a724f0f4 8677 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8678 new_token.str[0] = '\0';
8679
8680 if (strchr ("0123456789", *intel_parser.op_string))
8681 {
8682 char *p = new_token.str;
8683 char *q = intel_parser.op_string;
8684 new_token.code = T_CONST;
8685
8686 /* Allow any kind of identifier char to encompass floating point and
8687 hexadecimal numbers. */
8688 while (is_identifier_char (*q))
8689 *p++ = *q++;
8690 *p = '\0';
8691
8692 /* Recognize special symbol names [0-9][bf]. */
8693 if (strlen (intel_parser.op_string) == 2
4a1805b1 8694 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8695 || intel_parser.op_string[1] == 'f'))
8696 new_token.code = T_ID;
8697 }
8698
4d1bb795 8699 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8700 {
4d1bb795
JB		 8701 size_t len = end_op - intel_parser.op_string;
8702
64a0c779
DN		 8703 new_token.code = T_REG;
8704 new_token.reg = reg;
8705
4d1bb795
JB		 8706 memcpy (new_token.str, intel_parser.op_string, len);
8707 new_token.str[len] = '\0';
64a0c779
DN		 8708 }
8709
8710 else if (is_identifier_char (*intel_parser.op_string))
8711 {
8712 char *p = new_token.str;
8713 char *q = intel_parser.op_string;
8714
8715 /* A '.' or '$' followed by an identifier char is an identifier.
8716 Otherwise, it's operator '.' followed by an expression. */
8717 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8718 {
9306ca4a
JB		 8719 new_token.code = '.';
8720 new_token.str[0] = '.';
64a0c779
DN		 8721 new_token.str[1] = '\0';
8722 }
8723 else
8724 {
8725 while (is_identifier_char (*q) || *q == '@')
8726 *p++ = *q++;
8727 *p = '\0';
8728
9306ca4a
JB		 8729 if (strcasecmp (new_token.str, "NOT") == 0)
8730 new_token.code = '~';
8731
8732 else if (strcasecmp (new_token.str, "MOD") == 0)
8733 new_token.code = '%';
8734
8735 else if (strcasecmp (new_token.str, "AND") == 0)
8736 new_token.code = '&';
8737
8738 else if (strcasecmp (new_token.str, "OR") == 0)
8739 new_token.code = '|';
8740
8741 else if (strcasecmp (new_token.str, "XOR") == 0)
8742 new_token.code = '^';
8743
8744 else if (strcasecmp (new_token.str, "SHL") == 0)
8745 new_token.code = T_SHL;
8746
8747 else if (strcasecmp (new_token.str, "SHR") == 0)
8748 new_token.code = T_SHR;
8749
8750 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8751 new_token.code = T_BYTE;
8752
8753 else if (strcasecmp (new_token.str, "WORD") == 0)
8754 new_token.code = T_WORD;
8755
8756 else if (strcasecmp (new_token.str, "DWORD") == 0)
8757 new_token.code = T_DWORD;
8758
9306ca4a
JB		 8759 else if (strcasecmp (new_token.str, "FWORD") == 0)
8760 new_token.code = T_FWORD;
8761
64a0c779
DN		 8762 else if (strcasecmp (new_token.str, "QWORD") == 0)
8763 new_token.code = T_QWORD;
8764
9306ca4a
JB		 8765 else if (strcasecmp (new_token.str, "TBYTE") == 0
8766 /* XXX remove (gcc still uses it) */
8767 || strcasecmp (new_token.str, "XWORD") == 0)
8768 new_token.code = T_TBYTE;
8769
8770 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8771 || strcasecmp (new_token.str, "OWORD") == 0)
8772 new_token.code = T_XMMWORD;
64a0c779
DN		 8773
8774 else if (strcasecmp (new_token.str, "PTR") == 0)
8775 new_token.code = T_PTR;
8776
8777 else if (strcasecmp (new_token.str, "SHORT") == 0)
8778 new_token.code = T_SHORT;
8779
8780 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8781 {
8782 new_token.code = T_OFFSET;
8783
8784 /* ??? This is not mentioned in the MASM grammar but gcc
8785 makes use of it with -mintel-syntax. OFFSET may be
8786 followed by FLAT: */
8787 if (strncasecmp (q, " FLAT:", 6) == 0)
8788 strcat (new_token.str, " FLAT:");
8789 }
8790
8791 /* ??? This is not mentioned in the MASM grammar. */
8792 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8793 {
8794 new_token.code = T_OFFSET;
8795 if (*q == ':')
8796 strcat (new_token.str, ":");
8797 else
8798 as_bad (_("`:' expected"));
8799 }
64a0c779
DN		 8800
8801 else
8802 new_token.code = T_ID;
8803 }
8804 }
8805
9306ca4a
JB		 8806 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8807 {
8808 new_token.code = *intel_parser.op_string;
8809 new_token.str[0] = *intel_parser.op_string;
8810 new_token.str[1] = '\0';
8811 }
8812
8813 else if (strchr ("<>", *intel_parser.op_string)
8814 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8815 {
8816 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8817 new_token.str[0] = *intel_parser.op_string;
8818 new_token.str[1] = *intel_parser.op_string;
8819 new_token.str[2] = '\0';
8820 }
8821
64a0c779 8822 else
0477af35 8823 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8824
8825 intel_parser.op_string += strlen (new_token.str);
8826 cur_token = new_token;
8827}
8828
64a0c779
DN		 8829/* Put cur_token back into the token stream and make cur_token point to
8830 prev_token. */
8831static void
e3bb37b5 8832intel_putback_token (void)
64a0c779 8833{
a724f0f4
JB		 8834 if (cur_token.code != T_NIL)
8835 {
8836 intel_parser.op_string -= strlen (cur_token.str);
8837 free (cur_token.str);
8838 }
64a0c779 8839 cur_token = prev_token;
4a1805b1 8840
64a0c779
DN		 8841 /* Forget prev_token. */
8842 prev_token.code = T_NIL;
8843 prev_token.reg = NULL;
8844 prev_token.str = NULL;
8845}
54cfded0 8846
a4447b93 8847int
1df69f4f 8848tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8849{
8850 unsigned int regnum;
8851 unsigned int regnames_count;
089dfecd 8852 static const char *const regnames_32[] =
54cfded0 8853 {
a4447b93
RH		 8854 "eax", "ecx", "edx", "ebx",
8855 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8856 "eip", "eflags", NULL,
8857 "st0", "st1", "st2", "st3",
8858 "st4", "st5", "st6", "st7",
8859 NULL, NULL,
8860 "xmm0", "xmm1", "xmm2", "xmm3",
8861 "xmm4", "xmm5", "xmm6", "xmm7",
8862 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8863 "mm4", "mm5", "mm6", "mm7",
8864 "fcw", "fsw", "mxcsr",
8865 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8866 "tr", "ldtr"
54cfded0 8867 };
089dfecd 8868 static const char *const regnames_64[] =
54cfded0 8869 {
089dfecd
JB		 8870 "rax", "rdx", "rcx", "rbx",
8871 "rsi", "rdi", "rbp", "rsp",
8872 "r8", "r9", "r10", "r11",
54cfded0 8873 "r12", "r13", "r14", "r15",
089dfecd
JB		 8874 "rip",
8875 "xmm0", "xmm1", "xmm2", "xmm3",
8876 "xmm4", "xmm5", "xmm6", "xmm7",
8877 "xmm8", "xmm9", "xmm10", "xmm11",
8878 "xmm12", "xmm13", "xmm14", "xmm15",
8879 "st0", "st1", "st2", "st3",
8880 "st4", "st5", "st6", "st7",
8881 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8882 "mm4", "mm5", "mm6", "mm7",
8883 "rflags",
8884 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8885 "fs.base", "gs.base", NULL, NULL,
8886 "tr", "ldtr",
8887 "mxcsr", "fcw", "fsw"
54cfded0 8888 };
089dfecd 8889 const char *const *regnames;
54cfded0
AM		 8890
8891 if (flag_code == CODE_64BIT)
8892 {
8893 regnames = regnames_64;
0cea6190 8894 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8895 }
8896 else
8897 {
8898 regnames = regnames_32;
0cea6190 8899 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8900 }
8901
8902 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8903 if (regnames[regnum] != NULL
8904 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8905 return regnum;
8906
54cfded0
AM		 8907 return -1;
8908}
8909
8910void
8911tc_x86_frame_initial_instructions (void)
8912{
a4447b93
RH		 8913 static unsigned int sp_regno;
8914
8915 if (!sp_regno)
8916 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8917 ? "rsp" : "esp");
8918
8919 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8920 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8921}
d2b2c203
DJ		 8922
8923int
8924i386_elf_section_type (const char *str, size_t len)
8925{
8926 if (flag_code == CODE_64BIT
8927 && len == sizeof ("unwind") - 1
8928 && strncmp (str, "unwind", 6) == 0)
8929 return SHT_X86_64_UNWIND;
8930
8931 return -1;
8932}
bb41ade5
AM		 8933
8934#ifdef TE_PE
8935void
8936tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8937{
8938 expressionS expr;
8939
8940 expr.X_op = O_secrel;
8941 expr.X_add_symbol = symbol;
8942 expr.X_add_number = 0;
8943 emit_expr (&expr, size);
8944}
8945#endif
3b22753a
L		 8946
8947#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8948/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8949
8950int
8951x86_64_section_letter (int letter, char **ptr_msg)
8952{
8953 if (flag_code == CODE_64BIT)
8954 {
8955 if (letter == 'l')
8956 return SHF_X86_64_LARGE;
8957
8958 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8959 }
3b22753a 8960 else
64e74474 8961 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8962 return -1;
8963}
8964
8965int
8966x86_64_section_word (char *str, size_t len)
8967{
8620418b 8968 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8969 return SHF_X86_64_LARGE;
8970
8971 return -1;
8972}
8973
8974static void
8975handle_large_common (int small ATTRIBUTE_UNUSED)
8976{
8977 if (flag_code != CODE_64BIT)
8978 {
8979 s_comm_internal (0, elf_common_parse);
8980 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8981 }
8982 else
8983 {
8984 static segT lbss_section;
8985 asection *saved_com_section_ptr = elf_com_section_ptr;
8986 asection *saved_bss_section = bss_section;
8987
8988 if (lbss_section == NULL)
8989 {
8990 flagword applicable;
8991 segT seg = now_seg;
8992 subsegT subseg = now_subseg;
8993
8994 /* The .lbss section is for local .largecomm symbols. */
8995 lbss_section = subseg_new (".lbss", 0);
8996 applicable = bfd_applicable_section_flags (stdoutput);
8997 bfd_set_section_flags (stdoutput, lbss_section,
8998 applicable & SEC_ALLOC);
8999 seg_info (lbss_section)->bss = 1;
9000
9001 subseg_set (seg, subseg);
9002 }
9003
9004 elf_com_section_ptr = &_bfd_elf_large_com_section;
9005 bss_section = lbss_section;
9006
9007 s_comm_internal (0, elf_common_parse);
9008
9009 elf_com_section_ptr = saved_com_section_ptr;
9010 bss_section = saved_bss_section;
9011 }
9012}
9013#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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