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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
6305a203
L		 153/* x86 arch names, types and features */
154typedef struct
155{
156 const char *name; /* arch name */
157 enum processor_type type; /* arch type */
158 i386_cpu_flags flags; /* cpu feature flags */
159}
160arch_entry;
161
e3bb37b5
L		 162static void set_code_flag (int);
163static void set_16bit_gcc_code_flag (int);
164static void set_intel_syntax (int);
1efbbeb4 165static void set_intel_mnemonic (int);
db51cc60 166static void set_allow_index_reg (int);
cb19c032 167static void set_sse_check (int);
e3bb37b5 168static void set_cpu_arch (int);
6482c264 169#ifdef TE_PE
e3bb37b5 170static void pe_directive_secrel (int);
6482c264 171#endif
e3bb37b5
L		 172static void signed_cons (int);
173static char *output_invalid (int c);
a7619375 174static int i386_att_operand (char *);
e3bb37b5
L		 175static int i386_intel_operand (char *, int);
176static const reg_entry *parse_register (char *, char **);
177static char *parse_insn (char *, char *);
178static char *parse_operands (char *, const char *);
179static void swap_operands (void);
4d456e3d 180static void swap_2_operands (int, int);
e3bb37b5
L		 181static void optimize_imm (void);
182static void optimize_disp (void);
fa99fab2 183static const template *match_template (void);
e3bb37b5
L		 184static int check_string (void);
185static int process_suffix (void);
186static int check_byte_reg (void);
187static int check_long_reg (void);
188static int check_qword_reg (void);
189static int check_word_reg (void);
190static int finalize_imm (void);
85f10a01 191static void process_drex (void);
e3bb37b5
L		 192static int process_operands (void);
193static const seg_entry *build_modrm_byte (void);
194static void output_insn (void);
195static void output_imm (fragS *, offsetT);
196static void output_disp (fragS *, offsetT);
29b0f896 197#ifndef I386COFF
e3bb37b5 198static void s_bss (int);
252b5132 199#endif
17d4e2a2
L		 200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201static void handle_large_common (int small ATTRIBUTE_UNUSED);
202#endif
252b5132 203
a847613f 204static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 205
c0f3af97
L		 206/* VEX prefix. */
207typedef struct
208{
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes[3];
211 unsigned int length;
212 /* Destination or source register specifier. */
213 const reg_entry *register_specifier;
214} vex_prefix;
215
252b5132 216/* 'md_assemble ()' gathers together information and puts it into a
47926f60 217 i386_insn. */
252b5132 218
520dc8e8
AM		 219union i386_op
220 {
221 expressionS *disps;
222 expressionS *imms;
223 const reg_entry *regs;
224 };
225
252b5132
RH		 226struct _i386_insn
227 {
47926f60 228 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 229 template tm;
230
7d5e4556
L		 231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
252b5132
RH		 233 char suffix;
234
47926f60 235 /* OPERANDS gives the number of given operands. */
252b5132
RH		 236 unsigned int operands;
237
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
47926f60 240 operands. */
252b5132
RH		 241 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
242
243 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 244 use OP[i] for the corresponding operand. */
40fb9820 245 i386_operand_type types[MAX_OPERANDS];
252b5132 246
520dc8e8
AM		 247 /* Displacement expression, immediate expression, or register for each
248 operand. */
249 union i386_op op[MAX_OPERANDS];
252b5132 250
3e73aa7c
JH		 251 /* Flags for operands. */
252 unsigned int flags[MAX_OPERANDS];
253#define Operand_PCrel 1
254
252b5132 255 /* Relocation type for operand */
f86103b7 256 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 257
252b5132
RH		 258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry *base_reg;
261 const reg_entry *index_reg;
262 unsigned int log2_scale_factor;
263
264 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 265 explicit segment overrides are given. */
ce8a8b2f 266 const seg_entry *seg[2];
252b5132
RH		 267
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes;
271 unsigned char prefix[MAX_PREFIXES];
272
273 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
252b5132
RH		 276
277 modrm_byte rm;
3e73aa7c 278 rex_byte rex;
252b5132 279 sib_byte sib;
85f10a01 280 drex_byte drex;
c0f3af97 281 vex_prefix vex;
b6169b20
L		 282
283 /* Swap operand in encoding. */
284 unsigned int swap_operand : 1;
252b5132
RH		 285 };
286
287typedef struct _i386_insn i386_insn;
288
289/* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
32137342 291const char extra_symbol_chars[] = "*%-(["
252b5132 292#ifdef LEX_AT
32137342
NC		 293 "@"
294#endif
295#ifdef LEX_QM
296 "?"
252b5132 297#endif
32137342 298 ;
252b5132 299
29b0f896
AM		 300#if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 302 && !defined (TE_GNU) \
29b0f896 303 && !defined (TE_LINUX) \
32137342 304 && !defined (TE_NETWARE) \
29b0f896
AM		 305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
252b5132 307/* This array holds the chars that always start a comment. If the
b3b91714
AM		 308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310const char *i386_comment_chars = "#/";
311#define SVR4_COMMENT_CHARS 1
252b5132 312#define PREFIX_SEPARATOR '\\'
252b5132 313
b3b91714
AM		 314#else
315const char *i386_comment_chars = "#";
316#define PREFIX_SEPARATOR '/'
317#endif
318
252b5132
RH		 319/* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 323 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
252b5132 326 '/' isn't otherwise defined. */
b3b91714 327const char line_comment_chars[] = "#/";
252b5132 328
63a0b638 329const char line_separator_chars[] = ";";
252b5132 330
ce8a8b2f
AM		 331/* Chars that can be used to separate mant from exp in floating point
332 nums. */
252b5132
RH		 333const char EXP_CHARS[] = "eE";
334
ce8a8b2f
AM		 335/* Chars that mean this number is a floating point constant
336 As in 0f12.456
337 or 0d1.2345e12. */
252b5132
RH		 338const char FLT_CHARS[] = "fFdDxX";
339
ce8a8b2f 340/* Tables for lexical analysis. */
252b5132
RH		 341static char mnemonic_chars[256];
342static char register_chars[256];
343static char operand_chars[256];
344static char identifier_chars[256];
345static char digit_chars[256];
346
ce8a8b2f 347/* Lexical macros. */
252b5132
RH		 348#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349#define is_operand_char(x) (operand_chars[(unsigned char) x])
350#define is_register_char(x) (register_chars[(unsigned char) x])
351#define is_space_char(x) ((x) == ' ')
352#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353#define is_digit_char(x) (digit_chars[(unsigned char) x])
354
0234cb7c 355/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 356static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
357
358/* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
47926f60 361 assembler instruction). */
252b5132 362static char save_stack[32];
ce8a8b2f 363static char *save_stack_p;
252b5132
RH		 364#define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366#define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
368
47926f60 369/* The instruction we're assembling. */
252b5132
RH		 370static i386_insn i;
371
372/* Possible templates for current insn. */
373static const templates *current_templates;
374
31b2323c
L		 375/* Per instruction expressionS buffers: max displacements & immediates. */
376static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
377static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 378
47926f60
KH		 379/* Current operand we are working on. */
380static int this_operand;
252b5132 381
3e73aa7c
JH		 382/* We support four different modes. FLAG_CODE variable is used to distinguish
383 these. */
384
385enum flag_code {
386 CODE_32BIT,
387 CODE_16BIT,
388 CODE_64BIT };
389
390static enum flag_code flag_code;
4fa24527 391static unsigned int object_64bit;
3e73aa7c
JH		 392static int use_rela_relocations = 0;
393
394/* The names used to print error messages. */
b77a7acd 395static const char *flag_code_names[] =
3e73aa7c
JH		 396 {
397 "32",
398 "16",
399 "64"
400 };
252b5132 401
47926f60
KH		 402/* 1 for intel syntax,
403 0 if att syntax. */
404static int intel_syntax = 0;
252b5132 405
1efbbeb4
L		 406/* 1 for intel mnemonic,
407 0 if att mnemonic. */
408static int intel_mnemonic = !SYSV386_COMPAT;
409
5209009a 410/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 411static int old_gcc = OLDGCC_COMPAT;
412
a60de03c
JB		 413/* 1 if pseudo registers are permitted. */
414static int allow_pseudo_reg = 0;
415
47926f60
KH		 416/* 1 if register prefix % not required. */
417static int allow_naked_reg = 0;
252b5132 418
ba104c83 419/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 420static int allow_index_reg = 0;
421
daf50ae7
L		 422static enum
423 {
424 sse_check_none = 0,
425 sse_check_warning,
426 sse_check_error
427 }
428sse_check;
429
2ca3ace5
L		 430/* Register prefix used for error message. */
431static const char *register_prefix = "%";
432
47926f60
KH		 433/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436static char stackop_size = '\0';
eecb386c 437
12b55ccc
L		 438/* Non-zero to optimize code alignment. */
439int optimize_align_code = 1;
440
47926f60
KH		 441/* Non-zero to quieten some warnings. */
442static int quiet_warnings = 0;
a38cf1db 443
47926f60
KH		 444/* CPU name. */
445static const char *cpu_arch_name = NULL;
6305a203 446static char *cpu_sub_arch_name = NULL;
a38cf1db 447
47926f60 448/* CPU feature flags. */
40fb9820
L		 449static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
450
ccc9c027
L		 451/* If we have selected a cpu we are generating instructions for. */
452static int cpu_arch_tune_set = 0;
453
9103f4f4 454/* Cpu we are generating instructions for. */
fbf3f584 455enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 456
457/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 458static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 459
ccc9c027 460/* CPU instruction set architecture used. */
fbf3f584 461enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 462
9103f4f4 463/* CPU feature flags of instruction set architecture used. */
fbf3f584 464i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 465
fddf5b5b
AM		 466/* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468static unsigned int no_cond_jump_promotion = 0;
469
c0f3af97
L		 470/* Encode SSE instructions with VEX prefix. */
471static unsigned int sse2avx;
472
29b0f896 473/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 474static symbolS *GOT_symbol;
29b0f896 475
a4447b93
RH		 476/* The dwarf2 return column, adjusted for 32 or 64 bit. */
477unsigned int x86_dwarf2_return_column;
478
479/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480int x86_cie_data_alignment;
481
252b5132 482/* Interface to relax_segment.
fddf5b5b
AM		 483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
252b5132 486
47926f60 487/* Types. */
93c2a809
AM		 488#define UNCOND_JUMP 0
489#define COND_JUMP 1
490#define COND_JUMP86 2
fddf5b5b 491
47926f60 492/* Sizes. */
252b5132
RH		 493#define CODE16 1
494#define SMALL 0
29b0f896 495#define SMALL16 (SMALL | CODE16)
252b5132 496#define BIG 2
29b0f896 497#define BIG16 (BIG | CODE16)
252b5132
RH		 498
499#ifndef INLINE
500#ifdef __GNUC__
501#define INLINE __inline__
502#else
503#define INLINE
504#endif
505#endif
506
fddf5b5b
AM		 507#define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509#define TYPE_FROM_RELAX_STATE(s) \
510 ((s) >> 2)
511#define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 513
514/* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
521
522const relax_typeS md_relax_table[] =
523{
24eab124
AM		 524 /* The fields are:
525 1) most positive reach of this state,
526 2) most negative reach of this state,
93c2a809 527 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 528 4) which index into the table to try if we can't fit into this one. */
252b5132 529
fddf5b5b 530 /* UNCOND_JUMP states. */
93c2a809
AM		 531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
252b5132 535 {0, 0, 4, 0},
93c2a809
AM		 536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 538 {0, 0, 2, 0},
539
93c2a809
AM		 540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
545 {0, 0, 5, 0},
fddf5b5b 546 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 547 1 extra opcode byte, 2 displacement bytes. */
548 {0, 0, 3, 0},
549
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
555 {0, 0, 5, 0},
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
558 {0, 0, 4, 0}
252b5132
RH		 559};
560
9103f4f4
L		 561static const arch_entry cpu_arch[] =
562{
6305a203
L		 563 { "generic32", PROCESSOR_GENERIC32,
564 CPU_GENERIC32_FLAGS },
565 { "generic64", PROCESSOR_GENERIC64,
566 CPU_GENERIC64_FLAGS },
567 { "i8086", PROCESSOR_UNKNOWN,
568 CPU_NONE_FLAGS },
569 { "i186", PROCESSOR_UNKNOWN,
570 CPU_I186_FLAGS },
571 { "i286", PROCESSOR_UNKNOWN,
572 CPU_I286_FLAGS },
573 { "i386", PROCESSOR_I386,
574 CPU_I386_FLAGS },
575 { "i486", PROCESSOR_I486,
576 CPU_I486_FLAGS },
577 { "i586", PROCESSOR_PENTIUM,
578 CPU_I586_FLAGS },
579 { "i686", PROCESSOR_PENTIUMPRO,
580 CPU_I686_FLAGS },
581 { "pentium", PROCESSOR_PENTIUM,
582 CPU_I586_FLAGS },
583 { "pentiumpro", PROCESSOR_PENTIUMPRO,
584 CPU_I686_FLAGS },
585 { "pentiumii", PROCESSOR_PENTIUMPRO,
586 CPU_P2_FLAGS },
587 { "pentiumiii",PROCESSOR_PENTIUMPRO,
588 CPU_P3_FLAGS },
589 { "pentium4", PROCESSOR_PENTIUM4,
590 CPU_P4_FLAGS },
591 { "prescott", PROCESSOR_NOCONA,
592 CPU_CORE_FLAGS },
593 { "nocona", PROCESSOR_NOCONA,
594 CPU_NOCONA_FLAGS },
595 { "yonah", PROCESSOR_CORE,
596 CPU_CORE_FLAGS },
597 { "core", PROCESSOR_CORE,
598 CPU_CORE_FLAGS },
599 { "merom", PROCESSOR_CORE2,
600 CPU_CORE2_FLAGS },
601 { "core2", PROCESSOR_CORE2,
602 CPU_CORE2_FLAGS },
603 { "k6", PROCESSOR_K6,
604 CPU_K6_FLAGS },
605 { "k6_2", PROCESSOR_K6,
606 CPU_K6_2_FLAGS },
607 { "athlon", PROCESSOR_ATHLON,
608 CPU_ATHLON_FLAGS },
609 { "sledgehammer", PROCESSOR_K8,
610 CPU_K8_FLAGS },
611 { "opteron", PROCESSOR_K8,
612 CPU_K8_FLAGS },
613 { "k8", PROCESSOR_K8,
614 CPU_K8_FLAGS },
615 { "amdfam10", PROCESSOR_AMDFAM10,
616 CPU_AMDFAM10_FLAGS },
617 { ".mmx", PROCESSOR_UNKNOWN,
618 CPU_MMX_FLAGS },
619 { ".sse", PROCESSOR_UNKNOWN,
620 CPU_SSE_FLAGS },
621 { ".sse2", PROCESSOR_UNKNOWN,
622 CPU_SSE2_FLAGS },
623 { ".sse3", PROCESSOR_UNKNOWN,
624 CPU_SSE3_FLAGS },
625 { ".ssse3", PROCESSOR_UNKNOWN,
626 CPU_SSSE3_FLAGS },
627 { ".sse4.1", PROCESSOR_UNKNOWN,
628 CPU_SSE4_1_FLAGS },
629 { ".sse4.2", PROCESSOR_UNKNOWN,
630 CPU_SSE4_2_FLAGS },
631 { ".sse4", PROCESSOR_UNKNOWN,
632 CPU_SSE4_2_FLAGS },
c0f3af97
L		 633 { ".avx", PROCESSOR_UNKNOWN,
634 CPU_AVX_FLAGS },
6305a203
L		 635 { ".vmx", PROCESSOR_UNKNOWN,
636 CPU_VMX_FLAGS },
637 { ".smx", PROCESSOR_UNKNOWN,
638 CPU_SMX_FLAGS },
f03fe4c1
L		 639 { ".xsave", PROCESSOR_UNKNOWN,
640 CPU_XSAVE_FLAGS },
c0f3af97
L		 641 { ".aes", PROCESSOR_UNKNOWN,
642 CPU_AES_FLAGS },
594ab6a3
L		 643 { ".pclmul", PROCESSOR_UNKNOWN,
644 CPU_PCLMUL_FLAGS },
c0f3af97 645 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 646 CPU_PCLMUL_FLAGS },
c0f3af97
L		 647 { ".fma", PROCESSOR_UNKNOWN,
648 CPU_FMA_FLAGS },
f1f8f695
L		 649 { ".movbe", PROCESSOR_UNKNOWN,
650 CPU_MOVBE_FLAGS },
651 { ".ept", PROCESSOR_UNKNOWN,
652 CPU_EPT_FLAGS },
6305a203
L		 653 { ".3dnow", PROCESSOR_UNKNOWN,
654 CPU_3DNOW_FLAGS },
655 { ".3dnowa", PROCESSOR_UNKNOWN,
656 CPU_3DNOWA_FLAGS },
657 { ".padlock", PROCESSOR_UNKNOWN,
658 CPU_PADLOCK_FLAGS },
659 { ".pacifica", PROCESSOR_UNKNOWN,
660 CPU_SVME_FLAGS },
661 { ".svme", PROCESSOR_UNKNOWN,
662 CPU_SVME_FLAGS },
663 { ".sse4a", PROCESSOR_UNKNOWN,
664 CPU_SSE4A_FLAGS },
665 { ".abm", PROCESSOR_UNKNOWN,
666 CPU_ABM_FLAGS },
667 { ".sse5", PROCESSOR_UNKNOWN,
668 CPU_SSE5_FLAGS },
e413e4e9
AM		 669};
670
704209c0 671#ifdef I386COFF
a6c24e68
NC		 672/* Like s_lcomm_internal in gas/read.c but the alignment string
673 is allowed to be optional. */
674
675static symbolS *
676pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
677{
678 addressT align = 0;
679
680 SKIP_WHITESPACE ();
681
682 if (needs_align
683 && *input_line_pointer == ',')
684 {
685 align = parse_align (needs_align - 1);
686
687 if (align == (addressT) -1)
688 return NULL;
689 }
690 else
691 {
692 if (size >= 8)
693 align = 3;
694 else if (size >= 4)
695 align = 2;
696 else if (size >= 2)
697 align = 1;
698 else
699 align = 0;
700 }
701
702 bss_alloc (symbolP, size, align);
703 return symbolP;
704}
705
704209c0 706static void
a6c24e68
NC		 707pe_lcomm (int needs_align)
708{
709 s_comm_internal (needs_align * 2, pe_lcomm_internal);
710}
704209c0 711#endif
a6c24e68 712
29b0f896
AM		 713const pseudo_typeS md_pseudo_table[] =
714{
715#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
716 {"align", s_align_bytes, 0},
717#else
718 {"align", s_align_ptwo, 0},
719#endif
720 {"arch", set_cpu_arch, 0},
721#ifndef I386COFF
722 {"bss", s_bss, 0},
a6c24e68
NC		 723#else
724 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 725#endif
726 {"ffloat", float_cons, 'f'},
727 {"dfloat", float_cons, 'd'},
728 {"tfloat", float_cons, 'x'},
729 {"value", cons, 2},
d182319b 730 {"slong", signed_cons, 4},
29b0f896
AM		 731 {"noopt", s_ignore, 0},
732 {"optim", s_ignore, 0},
733 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
734 {"code16", set_code_flag, CODE_16BIT},
735 {"code32", set_code_flag, CODE_32BIT},
736 {"code64", set_code_flag, CODE_64BIT},
737 {"intel_syntax", set_intel_syntax, 1},
738 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 739 {"intel_mnemonic", set_intel_mnemonic, 1},
740 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 741 {"allow_index_reg", set_allow_index_reg, 1},
742 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 743 {"sse_check", set_sse_check, 0},
3b22753a
L		 744#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
745 {"largecomm", handle_large_common, 0},
07a53e5c 746#else
e3bb37b5 747 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 748 {"loc", dwarf2_directive_loc, 0},
749 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 750#endif
6482c264
NC		 751#ifdef TE_PE
752 {"secrel32", pe_directive_secrel, 0},
753#endif
29b0f896
AM		 754 {0, 0, 0}
755};
756
757/* For interface with expression (). */
758extern char *input_line_pointer;
759
760/* Hash table for instruction mnemonic lookup. */
761static struct hash_control *op_hash;
762
763/* Hash table for register lookup. */
764static struct hash_control *reg_hash;
765\f
252b5132 766void
e3bb37b5 767i386_align_code (fragS *fragP, int count)
252b5132 768{
ce8a8b2f
AM		 769 /* Various efficient no-op patterns for aligning code labels.
770 Note: Don't try to assemble the instructions in the comments.
771 0L and 0w are not legal. */
252b5132
RH		 772 static const char f32_1[] =
773 {0x90}; /* nop */
774 static const char f32_2[] =
ccc9c027 775 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 776 static const char f32_3[] =
777 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
778 static const char f32_4[] =
779 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
780 static const char f32_5[] =
781 {0x90, /* nop */
782 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
783 static const char f32_6[] =
784 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
785 static const char f32_7[] =
786 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
787 static const char f32_8[] =
788 {0x90, /* nop */
789 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
790 static const char f32_9[] =
791 {0x89,0xf6, /* movl %esi,%esi */
792 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
793 static const char f32_10[] =
794 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
795 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
796 static const char f32_11[] =
797 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
798 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
799 static const char f32_12[] =
800 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
801 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
802 static const char f32_13[] =
803 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f32_14[] =
806 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
807 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 808 static const char f16_3[] =
809 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 810 static const char f16_4[] =
811 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
812 static const char f16_5[] =
813 {0x90, /* nop */
814 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
815 static const char f16_6[] =
816 {0x89,0xf6, /* mov %si,%si */
817 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
818 static const char f16_7[] =
819 {0x8d,0x74,0x00, /* lea 0(%si),%si */
820 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
821 static const char f16_8[] =
822 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
823 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 824 static const char jump_31[] =
825 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
828 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 829 static const char *const f32_patt[] = {
830 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 831 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 832 };
833 static const char *const f16_patt[] = {
76bc74dc 834 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 835 };
ccc9c027
L		 836 /* nopl (%[re]ax) */
837 static const char alt_3[] =
838 {0x0f,0x1f,0x00};
839 /* nopl 0(%[re]ax) */
840 static const char alt_4[] =
841 {0x0f,0x1f,0x40,0x00};
842 /* nopl 0(%[re]ax,%[re]ax,1) */
843 static const char alt_5[] =
844 {0x0f,0x1f,0x44,0x00,0x00};
845 /* nopw 0(%[re]ax,%[re]ax,1) */
846 static const char alt_6[] =
847 {0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopl 0L(%[re]ax) */
849 static const char alt_7[] =
850 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
851 /* nopl 0L(%[re]ax,%[re]ax,1) */
852 static const char alt_8[] =
853 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
854 /* nopw 0L(%[re]ax,%[re]ax,1) */
855 static const char alt_9[] =
856 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
857 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
858 static const char alt_10[] =
859 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 /* data16
861 nopw %cs:0L(%[re]ax,%[re]ax,1) */
862 static const char alt_long_11[] =
863 {0x66,
864 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* data16
866 data16
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_12[] =
869 {0x66,
870 0x66,
871 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
872 /* data16
873 data16
874 data16
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_13[] =
877 {0x66,
878 0x66,
879 0x66,
880 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
881 /* data16
882 data16
883 data16
884 data16
885 nopw %cs:0L(%[re]ax,%[re]ax,1) */
886 static const char alt_long_14[] =
887 {0x66,
888 0x66,
889 0x66,
890 0x66,
891 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
892 /* data16
893 data16
894 data16
895 data16
896 data16
897 nopw %cs:0L(%[re]ax,%[re]ax,1) */
898 static const char alt_long_15[] =
899 {0x66,
900 0x66,
901 0x66,
902 0x66,
903 0x66,
904 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
905 /* nopl 0(%[re]ax,%[re]ax,1)
906 nopw 0(%[re]ax,%[re]ax,1) */
907 static const char alt_short_11[] =
908 {0x0f,0x1f,0x44,0x00,0x00,
909 0x66,0x0f,0x1f,0x44,0x00,0x00};
910 /* nopw 0(%[re]ax,%[re]ax,1)
911 nopw 0(%[re]ax,%[re]ax,1) */
912 static const char alt_short_12[] =
913 {0x66,0x0f,0x1f,0x44,0x00,0x00,
914 0x66,0x0f,0x1f,0x44,0x00,0x00};
915 /* nopw 0(%[re]ax,%[re]ax,1)
916 nopl 0L(%[re]ax) */
917 static const char alt_short_13[] =
918 {0x66,0x0f,0x1f,0x44,0x00,0x00,
919 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
920 /* nopl 0L(%[re]ax)
921 nopl 0L(%[re]ax) */
922 static const char alt_short_14[] =
923 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
924 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
925 /* nopl 0L(%[re]ax)
926 nopl 0L(%[re]ax,%[re]ax,1) */
927 static const char alt_short_15[] =
928 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
929 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
930 static const char *const alt_short_patt[] = {
931 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
932 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
933 alt_short_14, alt_short_15
934 };
935 static const char *const alt_long_patt[] = {
936 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
937 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
938 alt_long_14, alt_long_15
939 };
252b5132 940
76bc74dc
L		 941 /* Only align for at least a positive non-zero boundary. */
942 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 943 return;
3e73aa7c 944
ccc9c027
L		 945 /* We need to decide which NOP sequence to use for 32bit and
946 64bit. When -mtune= is used:
4eed87de 947
76bc74dc
L		 948 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
949 PROCESSOR_GENERIC32, f32_patt will be used.
950 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
951 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
952 alt_long_patt will be used.
953 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
954 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 955
76bc74dc
L		 956 When -mtune= isn't used, alt_long_patt will be used if
957 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
958 be used.
ccc9c027
L		 959
960 When -march= or .arch is used, we can't use anything beyond
961 cpu_arch_isa_flags. */
962
963 if (flag_code == CODE_16BIT)
964 {
ccc9c027 965 if (count > 8)
33fef721 966 {
76bc74dc
L		 967 memcpy (fragP->fr_literal + fragP->fr_fix,
968 jump_31, count);
969 /* Adjust jump offset. */
970 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 971 }
76bc74dc
L		 972 else
973 memcpy (fragP->fr_literal + fragP->fr_fix,
974 f16_patt[count - 1], count);
252b5132 975 }
33fef721 976 else
ccc9c027
L		 977 {
978 const char *const *patt = NULL;
979
fbf3f584 980 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 981 {
982 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
983 switch (cpu_arch_tune)
984 {
985 case PROCESSOR_UNKNOWN:
986 /* We use cpu_arch_isa_flags to check if we SHOULD
987 optimize for Cpu686. */
fbf3f584 988 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 989 patt = alt_long_patt;
ccc9c027
L		 990 else
991 patt = f32_patt;
992 break;
ccc9c027
L		 993 case PROCESSOR_PENTIUMPRO:
994 case PROCESSOR_PENTIUM4:
995 case PROCESSOR_NOCONA:
ef05d495 996 case PROCESSOR_CORE:
76bc74dc
L		 997 case PROCESSOR_CORE2:
998 case PROCESSOR_GENERIC64:
999 patt = alt_long_patt;
1000 break;
ccc9c027
L		 1001 case PROCESSOR_K6:
1002 case PROCESSOR_ATHLON:
1003 case PROCESSOR_K8:
4eed87de 1004 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1005 patt = alt_short_patt;
1006 break;
76bc74dc 1007 case PROCESSOR_I386:
ccc9c027
L		 1008 case PROCESSOR_I486:
1009 case PROCESSOR_PENTIUM:
1010 case PROCESSOR_GENERIC32:
1011 patt = f32_patt;
1012 break;
4eed87de 1013 }
ccc9c027
L		 1014 }
1015 else
1016 {
fbf3f584 1017 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1018 {
1019 case PROCESSOR_UNKNOWN:
e6a14101 1020 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1021 PROCESSOR_UNKNOWN. */
1022 abort ();
1023 break;
1024
76bc74dc 1025 case PROCESSOR_I386:
ccc9c027
L		 1026 case PROCESSOR_I486:
1027 case PROCESSOR_PENTIUM:
ccc9c027
L		 1028 case PROCESSOR_K6:
1029 case PROCESSOR_ATHLON:
1030 case PROCESSOR_K8:
4eed87de 1031 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1032 case PROCESSOR_GENERIC32:
1033 /* We use cpu_arch_isa_flags to check if we CAN optimize
1034 for Cpu686. */
fbf3f584 1035 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1036 patt = alt_short_patt;
1037 else
1038 patt = f32_patt;
1039 break;
76bc74dc
L		 1040 case PROCESSOR_PENTIUMPRO:
1041 case PROCESSOR_PENTIUM4:
1042 case PROCESSOR_NOCONA:
1043 case PROCESSOR_CORE:
ef05d495 1044 case PROCESSOR_CORE2:
fbf3f584 1045 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1046 patt = alt_long_patt;
1047 else
1048 patt = f32_patt;
1049 break;
1050 case PROCESSOR_GENERIC64:
76bc74dc 1051 patt = alt_long_patt;
ccc9c027 1052 break;
4eed87de 1053 }
ccc9c027
L		 1054 }
1055
76bc74dc
L		 1056 if (patt == f32_patt)
1057 {
1058 /* If the padding is less than 15 bytes, we use the normal
1059 ones. Otherwise, we use a jump instruction and adjust
1060 its offset. */
1061 if (count < 15)
1062 memcpy (fragP->fr_literal + fragP->fr_fix,
1063 patt[count - 1], count);
1064 else
1065 {
1066 memcpy (fragP->fr_literal + fragP->fr_fix,
1067 jump_31, count);
1068 /* Adjust jump offset. */
1069 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1070 }
1071 }
1072 else
1073 {
1074 /* Maximum length of an instruction is 15 byte. If the
1075 padding is greater than 15 bytes and we don't use jump,
1076 we have to break it into smaller pieces. */
1077 int padding = count;
1078 while (padding > 15)
1079 {
1080 padding -= 15;
1081 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1082 patt [14], 15);
1083 }
1084
1085 if (padding)
1086 memcpy (fragP->fr_literal + fragP->fr_fix,
1087 patt [padding - 1], padding);
1088 }
ccc9c027 1089 }
33fef721 1090 fragP->fr_var = count;
252b5132
RH		 1091}
1092
c6fb90c8 1093static INLINE int
0dfbf9d7 1094operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1095{
0dfbf9d7 1096 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1097 {
1098 case 3:
0dfbf9d7 1099 if (x->array[2])
c6fb90c8
L		 1100 return 0;
1101 case 2:
0dfbf9d7 1102 if (x->array[1])
c6fb90c8
L		 1103 return 0;
1104 case 1:
0dfbf9d7 1105 return !x->array[0];
c6fb90c8
L		 1106 default:
1107 abort ();
1108 }
40fb9820
L		 1109}
1110
c6fb90c8 1111static INLINE void
0dfbf9d7 1112operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1113{
0dfbf9d7 1114 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1115 {
1116 case 3:
0dfbf9d7 1117 x->array[2] = v;
c6fb90c8 1118 case 2:
0dfbf9d7 1119 x->array[1] = v;
c6fb90c8 1120 case 1:
0dfbf9d7 1121 x->array[0] = v;
c6fb90c8
L		 1122 break;
1123 default:
1124 abort ();
1125 }
1126}
40fb9820 1127
c6fb90c8 1128static INLINE int
0dfbf9d7
L		 1129operand_type_equal (const union i386_operand_type *x,
1130 const union i386_operand_type *y)
c6fb90c8 1131{
0dfbf9d7 1132 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1133 {
1134 case 3:
0dfbf9d7 1135 if (x->array[2] != y->array[2])
c6fb90c8
L		 1136 return 0;
1137 case 2:
0dfbf9d7 1138 if (x->array[1] != y->array[1])
c6fb90c8
L		 1139 return 0;
1140 case 1:
0dfbf9d7 1141 return x->array[0] == y->array[0];
c6fb90c8
L		 1142 break;
1143 default:
1144 abort ();
1145 }
1146}
40fb9820 1147
0dfbf9d7
L		 1148static INLINE int
1149cpu_flags_all_zero (const union i386_cpu_flags *x)
1150{
1151 switch (ARRAY_SIZE(x->array))
1152 {
1153 case 3:
1154 if (x->array[2])
1155 return 0;
1156 case 2:
1157 if (x->array[1])
1158 return 0;
1159 case 1:
1160 return !x->array[0];
1161 default:
1162 abort ();
1163 }
1164}
1165
1166static INLINE void
1167cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1168{
1169 switch (ARRAY_SIZE(x->array))
1170 {
1171 case 3:
1172 x->array[2] = v;
1173 case 2:
1174 x->array[1] = v;
1175 case 1:
1176 x->array[0] = v;
1177 break;
1178 default:
1179 abort ();
1180 }
1181}
1182
1183static INLINE int
1184cpu_flags_equal (const union i386_cpu_flags *x,
1185 const union i386_cpu_flags *y)
1186{
1187 switch (ARRAY_SIZE(x->array))
1188 {
1189 case 3:
1190 if (x->array[2] != y->array[2])
1191 return 0;
1192 case 2:
1193 if (x->array[1] != y->array[1])
1194 return 0;
1195 case 1:
1196 return x->array[0] == y->array[0];
1197 break;
1198 default:
1199 abort ();
1200 }
1201}
c6fb90c8
L		 1202
1203static INLINE int
1204cpu_flags_check_cpu64 (i386_cpu_flags f)
1205{
1206 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1207 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1208}
1209
c6fb90c8
L		 1210static INLINE i386_cpu_flags
1211cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1212{
c6fb90c8
L		 1213 switch (ARRAY_SIZE (x.array))
1214 {
1215 case 3:
1216 x.array [2] &= y.array [2];
1217 case 2:
1218 x.array [1] &= y.array [1];
1219 case 1:
1220 x.array [0] &= y.array [0];
1221 break;
1222 default:
1223 abort ();
1224 }
1225 return x;
1226}
40fb9820 1227
c6fb90c8
L		 1228static INLINE i386_cpu_flags
1229cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1230{
c6fb90c8 1231 switch (ARRAY_SIZE (x.array))
40fb9820 1232 {
c6fb90c8
L		 1233 case 3:
1234 x.array [2] |= y.array [2];
1235 case 2:
1236 x.array [1] |= y.array [1];
1237 case 1:
1238 x.array [0] |= y.array [0];
40fb9820
L		 1239 break;
1240 default:
1241 abort ();
1242 }
40fb9820
L		 1243 return x;
1244}
1245
c0f3af97
L		 1246#define CPU_FLAGS_ARCH_MATCH 0x1
1247#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2
L		 1248#define CPU_FLAGS_AES_MATCH 0x4
1249#define CPU_FLAGS_AVX_MATCH 0x8
c0f3af97 1250
a5ff0eb2
L		 1251#define CPU_FLAGS_32BIT_MATCH \
1252 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1253#define CPU_FLAGS_PERFECT_MATCH \
1254 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1255
1256/* Return CPU flags match bits. */
3629bb00 1257
40fb9820 1258static int
c0f3af97 1259cpu_flags_match (const template *t)
40fb9820 1260{
c0f3af97
L		 1261 i386_cpu_flags x = t->cpu_flags;
1262 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1263
1264 x.bitfield.cpu64 = 0;
1265 x.bitfield.cpuno64 = 0;
1266
0dfbf9d7 1267 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1268 {
1269 /* This instruction is available on all archs. */
1270 match |= CPU_FLAGS_32BIT_MATCH;
1271 }
3629bb00
L		 1272 else
1273 {
c0f3af97 1274 /* This instruction is available only on some archs. */
3629bb00
L		 1275 i386_cpu_flags cpu = cpu_arch_flags;
1276
1277 cpu.bitfield.cpu64 = 0;
1278 cpu.bitfield.cpuno64 = 0;
1279 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1280 if (!cpu_flags_all_zero (&cpu))
1281 {
a5ff0eb2
L		 1282 if (x.bitfield.cpuavx)
1283 {
1284 /* We only need to check AES/SSE2AVX with AVX. */
1285 if (cpu.bitfield.cpuavx)
1286 {
1287 /* Check SSE2AVX. */
1288 if (!t->opcode_modifier.sse2avx|| sse2avx)
1289 {
1290 match |= (CPU_FLAGS_ARCH_MATCH
1291 | CPU_FLAGS_AVX_MATCH);
1292 /* Check AES. */
1293 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1294 match |= CPU_FLAGS_AES_MATCH;
1295 }
1296 }
1297 else
1298 match |= CPU_FLAGS_ARCH_MATCH;
1299 }
1300 else
c0f3af97
L		 1301 match |= CPU_FLAGS_32BIT_MATCH;
1302 }
3629bb00 1303 }
c0f3af97 1304 return match;
40fb9820
L		 1305}
1306
c6fb90c8
L		 1307static INLINE i386_operand_type
1308operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1309{
c6fb90c8
L		 1310 switch (ARRAY_SIZE (x.array))
1311 {
1312 case 3:
1313 x.array [2] &= y.array [2];
1314 case 2:
1315 x.array [1] &= y.array [1];
1316 case 1:
1317 x.array [0] &= y.array [0];
1318 break;
1319 default:
1320 abort ();
1321 }
1322 return x;
40fb9820
L		 1323}
1324
c6fb90c8
L		 1325static INLINE i386_operand_type
1326operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1327{
c6fb90c8 1328 switch (ARRAY_SIZE (x.array))
40fb9820 1329 {
c6fb90c8
L		 1330 case 3:
1331 x.array [2] |= y.array [2];
1332 case 2:
1333 x.array [1] |= y.array [1];
1334 case 1:
1335 x.array [0] |= y.array [0];
40fb9820
L		 1336 break;
1337 default:
1338 abort ();
1339 }
c6fb90c8
L		 1340 return x;
1341}
40fb9820 1342
c6fb90c8
L		 1343static INLINE i386_operand_type
1344operand_type_xor (i386_operand_type x, i386_operand_type y)
1345{
1346 switch (ARRAY_SIZE (x.array))
1347 {
1348 case 3:
1349 x.array [2] ^= y.array [2];
1350 case 2:
1351 x.array [1] ^= y.array [1];
1352 case 1:
1353 x.array [0] ^= y.array [0];
1354 break;
1355 default:
1356 abort ();
1357 }
40fb9820
L		 1358 return x;
1359}
1360
1361static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1362static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1363static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1364static const i386_operand_type inoutportreg
1365 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1366static const i386_operand_type reg16_inoutportreg
1367 = OPERAND_TYPE_REG16_INOUTPORTREG;
1368static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1369static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1370static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1371static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1372static const i386_operand_type anydisp
1373 = OPERAND_TYPE_ANYDISP;
40fb9820 1374static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1375static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1376static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1377static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1378static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1379static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1380static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1381static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1382static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1383static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1384static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
c0f3af97 1385static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
40fb9820
L		 1386
1387enum operand_type
1388{
1389 reg,
40fb9820
L		 1390 imm,
1391 disp,
1392 anymem
1393};
1394
c6fb90c8 1395static INLINE int
40fb9820
L		 1396operand_type_check (i386_operand_type t, enum operand_type c)
1397{
1398 switch (c)
1399 {
1400 case reg:
1401 return (t.bitfield.reg8
1402 || t.bitfield.reg16
1403 || t.bitfield.reg32
1404 || t.bitfield.reg64);
1405
40fb9820
L		 1406 case imm:
1407 return (t.bitfield.imm8
1408 || t.bitfield.imm8s
1409 || t.bitfield.imm16
1410 || t.bitfield.imm32
1411 || t.bitfield.imm32s
1412 || t.bitfield.imm64);
1413
1414 case disp:
1415 return (t.bitfield.disp8
1416 || t.bitfield.disp16
1417 || t.bitfield.disp32
1418 || t.bitfield.disp32s
1419 || t.bitfield.disp64);
1420
1421 case anymem:
1422 return (t.bitfield.disp8
1423 || t.bitfield.disp16
1424 || t.bitfield.disp32
1425 || t.bitfield.disp32s
1426 || t.bitfield.disp64
1427 || t.bitfield.baseindex);
1428
1429 default:
1430 abort ();
1431 }
2cfe26b6
AM		 1432
1433 return 0;
40fb9820
L		 1434}
1435
5c07affc
L		 1436/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1437 operand J for instruction template T. */
1438
1439static INLINE int
1440match_reg_size (const template *t, unsigned int j)
1441{
1442 return !((i.types[j].bitfield.byte
1443 && !t->operand_types[j].bitfield.byte)
1444 || (i.types[j].bitfield.word
1445 && !t->operand_types[j].bitfield.word)
1446 || (i.types[j].bitfield.dword
1447 && !t->operand_types[j].bitfield.dword)
1448 || (i.types[j].bitfield.qword
1449 && !t->operand_types[j].bitfield.qword));
1450}
1451
1452/* Return 1 if there is no conflict in any size on operand J for
1453 instruction template T. */
1454
1455static INLINE int
1456match_mem_size (const template *t, unsigned int j)
1457{
1458 return (match_reg_size (t, j)
1459 && !((i.types[j].bitfield.unspecified
1460 && !t->operand_types[j].bitfield.unspecified)
1461 || (i.types[j].bitfield.fword
1462 && !t->operand_types[j].bitfield.fword)
1463 || (i.types[j].bitfield.tbyte
1464 && !t->operand_types[j].bitfield.tbyte)
1465 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1466 && !t->operand_types[j].bitfield.xmmword)
1467 || (i.types[j].bitfield.ymmword
1468 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1469}
1470
1471/* Return 1 if there is no size conflict on any operands for
1472 instruction template T. */
1473
1474static INLINE int
1475operand_size_match (const template *t)
1476{
1477 unsigned int j;
1478 int match = 1;
1479
1480 /* Don't check jump instructions. */
1481 if (t->opcode_modifier.jump
1482 || t->opcode_modifier.jumpbyte
1483 || t->opcode_modifier.jumpdword
1484 || t->opcode_modifier.jumpintersegment)
1485 return match;
1486
1487 /* Check memory and accumulator operand size. */
1488 for (j = 0; j < i.operands; j++)
1489 {
1490 if (t->operand_types[j].bitfield.anysize)
1491 continue;
1492
1493 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1494 {
1495 match = 0;
1496 break;
1497 }
1498
1499 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1500 {
1501 match = 0;
1502 break;
1503 }
1504 }
1505
1506 if (match
1507 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1508 return match;
1509
1510 /* Check reverse. */
1511 assert (i.operands == 2);
1512
1513 match = 1;
1514 for (j = 0; j < 2; j++)
1515 {
1516 if (t->operand_types[j].bitfield.acc
1517 && !match_reg_size (t, j ? 0 : 1))
1518 {
1519 match = 0;
1520 break;
1521 }
1522
1523 if (i.types[j].bitfield.mem
1524 && !match_mem_size (t, j ? 0 : 1))
1525 {
1526 match = 0;
1527 break;
1528 }
1529 }
1530
1531 return match;
1532}
1533
c6fb90c8 1534static INLINE int
40fb9820
L		 1535operand_type_match (i386_operand_type overlap,
1536 i386_operand_type given)
1537{
1538 i386_operand_type temp = overlap;
1539
1540 temp.bitfield.jumpabsolute = 0;
7d5e4556 1541 temp.bitfield.unspecified = 0;
5c07affc
L		 1542 temp.bitfield.byte = 0;
1543 temp.bitfield.word = 0;
1544 temp.bitfield.dword = 0;
1545 temp.bitfield.fword = 0;
1546 temp.bitfield.qword = 0;
1547 temp.bitfield.tbyte = 0;
1548 temp.bitfield.xmmword = 0;
c0f3af97 1549 temp.bitfield.ymmword = 0;
0dfbf9d7 1550 if (operand_type_all_zero (&temp))
40fb9820
L		 1551 return 0;
1552
1553 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1554 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1555}
1556
7d5e4556 1557/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1558 unless the expected operand type register overlap is null.
1559 Note that Acc in a template matches every size of reg. */
1560
c6fb90c8 1561static INLINE int
40fb9820
L		 1562operand_type_register_match (i386_operand_type m0,
1563 i386_operand_type g0,
1564 i386_operand_type t0,
1565 i386_operand_type m1,
1566 i386_operand_type g1,
1567 i386_operand_type t1)
1568{
1569 if (!operand_type_check (g0, reg))
1570 return 1;
1571
1572 if (!operand_type_check (g1, reg))
1573 return 1;
1574
1575 if (g0.bitfield.reg8 == g1.bitfield.reg8
1576 && g0.bitfield.reg16 == g1.bitfield.reg16
1577 && g0.bitfield.reg32 == g1.bitfield.reg32
1578 && g0.bitfield.reg64 == g1.bitfield.reg64)
1579 return 1;
1580
1581 if (m0.bitfield.acc)
1582 {
1583 t0.bitfield.reg8 = 1;
1584 t0.bitfield.reg16 = 1;
1585 t0.bitfield.reg32 = 1;
1586 t0.bitfield.reg64 = 1;
1587 }
1588
1589 if (m1.bitfield.acc)
1590 {
1591 t1.bitfield.reg8 = 1;
1592 t1.bitfield.reg16 = 1;
1593 t1.bitfield.reg32 = 1;
1594 t1.bitfield.reg64 = 1;
1595 }
1596
1597 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1598 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1599 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1600 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1601}
1602
252b5132 1603static INLINE unsigned int
40fb9820 1604mode_from_disp_size (i386_operand_type t)
252b5132 1605{
40fb9820
L		 1606 if (t.bitfield.disp8)
1607 return 1;
1608 else if (t.bitfield.disp16
1609 || t.bitfield.disp32
1610 || t.bitfield.disp32s)
1611 return 2;
1612 else
1613 return 0;
252b5132
RH		 1614}
1615
1616static INLINE int
e3bb37b5 1617fits_in_signed_byte (offsetT num)
252b5132
RH		 1618{
1619 return (num >= -128) && (num <= 127);
47926f60 1620}
252b5132
RH		 1621
1622static INLINE int
e3bb37b5 1623fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1624{
1625 return (num & 0xff) == num;
47926f60 1626}
252b5132
RH		 1627
1628static INLINE int
e3bb37b5 1629fits_in_unsigned_word (offsetT num)
252b5132
RH		 1630{
1631 return (num & 0xffff) == num;
47926f60 1632}
252b5132
RH		 1633
1634static INLINE int
e3bb37b5 1635fits_in_signed_word (offsetT num)
252b5132
RH		 1636{
1637 return (-32768 <= num) && (num <= 32767);
47926f60 1638}
2a962e6d 1639
3e73aa7c 1640static INLINE int
e3bb37b5 1641fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1642{
1643#ifndef BFD64
1644 return 1;
1645#else
1646 return (!(((offsetT) -1 << 31) & num)
1647 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1648#endif
1649} /* fits_in_signed_long() */
2a962e6d 1650
3e73aa7c 1651static INLINE int
e3bb37b5 1652fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1653{
1654#ifndef BFD64
1655 return 1;
1656#else
1657 return (num & (((offsetT) 2 << 31) - 1)) == num;
1658#endif
1659} /* fits_in_unsigned_long() */
252b5132 1660
c0f3af97
L		 1661static INLINE int
1662fits_in_imm4 (offsetT num)
1663{
1664 return (num & 0xf) == num;
1665}
1666
40fb9820 1667static i386_operand_type
e3bb37b5 1668smallest_imm_type (offsetT num)
252b5132 1669{
40fb9820
L		 1670 i386_operand_type t;
1671
0dfbf9d7 1672 operand_type_set (&t, 0);
40fb9820
L		 1673 t.bitfield.imm64 = 1;
1674
1675 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1676 {
1677 /* This code is disabled on the 486 because all the Imm1 forms
1678 in the opcode table are slower on the i486. They're the
1679 versions with the implicitly specified single-position
1680 displacement, which has another syntax if you really want to
1681 use that form. */
40fb9820
L		 1682 t.bitfield.imm1 = 1;
1683 t.bitfield.imm8 = 1;
1684 t.bitfield.imm8s = 1;
1685 t.bitfield.imm16 = 1;
1686 t.bitfield.imm32 = 1;
1687 t.bitfield.imm32s = 1;
1688 }
1689 else if (fits_in_signed_byte (num))
1690 {
1691 t.bitfield.imm8 = 1;
1692 t.bitfield.imm8s = 1;
1693 t.bitfield.imm16 = 1;
1694 t.bitfield.imm32 = 1;
1695 t.bitfield.imm32s = 1;
1696 }
1697 else if (fits_in_unsigned_byte (num))
1698 {
1699 t.bitfield.imm8 = 1;
1700 t.bitfield.imm16 = 1;
1701 t.bitfield.imm32 = 1;
1702 t.bitfield.imm32s = 1;
1703 }
1704 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1705 {
1706 t.bitfield.imm16 = 1;
1707 t.bitfield.imm32 = 1;
1708 t.bitfield.imm32s = 1;
1709 }
1710 else if (fits_in_signed_long (num))
1711 {
1712 t.bitfield.imm32 = 1;
1713 t.bitfield.imm32s = 1;
1714 }
1715 else if (fits_in_unsigned_long (num))
1716 t.bitfield.imm32 = 1;
1717
1718 return t;
47926f60 1719}
252b5132 1720
847f7ad4 1721static offsetT
e3bb37b5 1722offset_in_range (offsetT val, int size)
847f7ad4 1723{
508866be 1724 addressT mask;
ba2adb93 1725
847f7ad4
AM		 1726 switch (size)
1727 {
508866be
L		 1728 case 1: mask = ((addressT) 1 << 8) - 1; break;
1729 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1730 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1731#ifdef BFD64
1732 case 8: mask = ((addressT) 2 << 63) - 1; break;
1733#endif
47926f60 1734 default: abort ();
847f7ad4
AM		 1735 }
1736
ba2adb93 1737 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1738 if (!use_rela_relocations)
1739 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1740 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1741
47926f60 1742 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1743 {
1744 char buf1[40], buf2[40];
1745
1746 sprint_value (buf1, val);
1747 sprint_value (buf2, val & mask);
1748 as_warn (_("%s shortened to %s"), buf1, buf2);
1749 }
1750 return val & mask;
1751}
1752
252b5132
RH		 1753/* Returns 0 if attempting to add a prefix where one from the same
1754 class already exists, 1 if non rep/repne added, 2 if rep/repne
1755 added. */
1756static int
e3bb37b5 1757add_prefix (unsigned int prefix)
252b5132
RH		 1758{
1759 int ret = 1;
b1905489 1760 unsigned int q;
252b5132 1761
29b0f896
AM		 1762 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1763 && flag_code == CODE_64BIT)
b1905489 1764 {
161a04f6
L		 1765 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1766 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1767 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1768 ret = 0;
1769 q = REX_PREFIX;
1770 }
3e73aa7c 1771 else
b1905489
JB		 1772 {
1773 switch (prefix)
1774 {
1775 default:
1776 abort ();
1777
1778 case CS_PREFIX_OPCODE:
1779 case DS_PREFIX_OPCODE:
1780 case ES_PREFIX_OPCODE:
1781 case FS_PREFIX_OPCODE:
1782 case GS_PREFIX_OPCODE:
1783 case SS_PREFIX_OPCODE:
1784 q = SEG_PREFIX;
1785 break;
1786
1787 case REPNE_PREFIX_OPCODE:
1788 case REPE_PREFIX_OPCODE:
1789 ret = 2;
1790 /* fall thru */
1791 case LOCK_PREFIX_OPCODE:
1792 q = LOCKREP_PREFIX;
1793 break;
1794
1795 case FWAIT_OPCODE:
1796 q = WAIT_PREFIX;
1797 break;
1798
1799 case ADDR_PREFIX_OPCODE:
1800 q = ADDR_PREFIX;
1801 break;
1802
1803 case DATA_PREFIX_OPCODE:
1804 q = DATA_PREFIX;
1805 break;
1806 }
1807 if (i.prefix[q] != 0)
1808 ret = 0;
1809 }
252b5132 1810
b1905489 1811 if (ret)
252b5132 1812 {
b1905489
JB		 1813 if (!i.prefix[q])
1814 ++i.prefixes;
1815 i.prefix[q] |= prefix;
252b5132 1816 }
b1905489
JB		 1817 else
1818 as_bad (_("same type of prefix used twice"));
252b5132 1819
252b5132
RH		 1820 return ret;
1821}
1822
1823static void
e3bb37b5 1824set_code_flag (int value)
eecb386c 1825{
3e73aa7c 1826 flag_code = value;
40fb9820
L		 1827 if (flag_code == CODE_64BIT)
1828 {
1829 cpu_arch_flags.bitfield.cpu64 = 1;
1830 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1831 }
1832 else
1833 {
1834 cpu_arch_flags.bitfield.cpu64 = 0;
1835 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1836 }
1837 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1838 {
1839 as_bad (_("64bit mode not supported on this CPU."));
1840 }
40fb9820 1841 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1842 {
1843 as_bad (_("32bit mode not supported on this CPU."));
1844 }
eecb386c
AM		 1845 stackop_size = '\0';
1846}
1847
1848static void
e3bb37b5 1849set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1850{
3e73aa7c 1851 flag_code = new_code_flag;
40fb9820
L		 1852 if (flag_code != CODE_16BIT)
1853 abort ();
1854 cpu_arch_flags.bitfield.cpu64 = 0;
1855 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1856 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1857}
1858
1859static void
e3bb37b5 1860set_intel_syntax (int syntax_flag)
252b5132
RH		 1861{
1862 /* Find out if register prefixing is specified. */
1863 int ask_naked_reg = 0;
1864
1865 SKIP_WHITESPACE ();
29b0f896 1866 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1867 {
1868 char *string = input_line_pointer;
1869 int e = get_symbol_end ();
1870
47926f60 1871 if (strcmp (string, "prefix") == 0)
252b5132 1872 ask_naked_reg = 1;
47926f60 1873 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1874 ask_naked_reg = -1;
1875 else
d0b47220 1876 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1877 *input_line_pointer = e;
1878 }
1879 demand_empty_rest_of_line ();
c3332e24 1880
252b5132
RH		 1881 intel_syntax = syntax_flag;
1882
1883 if (ask_naked_reg == 0)
f86103b7
AM		 1884 allow_naked_reg = (intel_syntax
1885 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1886 else
1887 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1888
e4a3b5a4 1889 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1890 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1891 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1892}
1893
1efbbeb4
L		 1894static void
1895set_intel_mnemonic (int mnemonic_flag)
1896{
e1d4d893 1897 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1898}
1899
db51cc60
L		 1900static void
1901set_allow_index_reg (int flag)
1902{
1903 allow_index_reg = flag;
1904}
1905
cb19c032
L		 1906static void
1907set_sse_check (int dummy ATTRIBUTE_UNUSED)
1908{
1909 SKIP_WHITESPACE ();
1910
1911 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1912 {
1913 char *string = input_line_pointer;
1914 int e = get_symbol_end ();
1915
1916 if (strcmp (string, "none") == 0)
1917 sse_check = sse_check_none;
1918 else if (strcmp (string, "warning") == 0)
1919 sse_check = sse_check_warning;
1920 else if (strcmp (string, "error") == 0)
1921 sse_check = sse_check_error;
1922 else
1923 as_bad (_("bad argument to sse_check directive."));
1924 *input_line_pointer = e;
1925 }
1926 else
1927 as_bad (_("missing argument for sse_check directive"));
1928
1929 demand_empty_rest_of_line ();
1930}
1931
e413e4e9 1932static void
e3bb37b5 1933set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1934{
47926f60 1935 SKIP_WHITESPACE ();
e413e4e9 1936
29b0f896 1937 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1938 {
1939 char *string = input_line_pointer;
1940 int e = get_symbol_end ();
9103f4f4 1941 unsigned int i;
40fb9820 1942 i386_cpu_flags flags;
e413e4e9 1943
9103f4f4 1944 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1945 {
1946 if (strcmp (string, cpu_arch[i].name) == 0)
1947 {
5c6af06e
JB		 1948 if (*string != '.')
1949 {
1950 cpu_arch_name = cpu_arch[i].name;
1951 cpu_sub_arch_name = NULL;
40fb9820
L		 1952 cpu_arch_flags = cpu_arch[i].flags;
1953 if (flag_code == CODE_64BIT)
1954 {
1955 cpu_arch_flags.bitfield.cpu64 = 1;
1956 cpu_arch_flags.bitfield.cpuno64 = 0;
1957 }
1958 else
1959 {
1960 cpu_arch_flags.bitfield.cpu64 = 0;
1961 cpu_arch_flags.bitfield.cpuno64 = 1;
1962 }
ccc9c027 1963 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1964 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1965 if (!cpu_arch_tune_set)
1966 {
1967 cpu_arch_tune = cpu_arch_isa;
1968 cpu_arch_tune_flags = cpu_arch_isa_flags;
1969 }
5c6af06e
JB		 1970 break;
1971 }
40fb9820 1972
c6fb90c8
L		 1973 flags = cpu_flags_or (cpu_arch_flags,
1974 cpu_arch[i].flags);
0dfbf9d7 1975 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1976 {
6305a203
L		 1977 if (cpu_sub_arch_name)
1978 {
1979 char *name = cpu_sub_arch_name;
1980 cpu_sub_arch_name = concat (name,
1981 cpu_arch[i].name,
1bf57e9f 1982 (const char *) NULL);
6305a203
L		 1983 free (name);
1984 }
1985 else
1986 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1987 cpu_arch_flags = flags;
5c6af06e
JB		 1988 }
1989 *input_line_pointer = e;
1990 demand_empty_rest_of_line ();
1991 return;
e413e4e9
AM		 1992 }
1993 }
9103f4f4 1994 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1995 as_bad (_("no such architecture: `%s'"), string);
1996
1997 *input_line_pointer = e;
1998 }
1999 else
2000 as_bad (_("missing cpu architecture"));
2001
fddf5b5b
AM		 2002 no_cond_jump_promotion = 0;
2003 if (*input_line_pointer == ','
29b0f896 2004 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2005 {
2006 char *string = ++input_line_pointer;
2007 int e = get_symbol_end ();
2008
2009 if (strcmp (string, "nojumps") == 0)
2010 no_cond_jump_promotion = 1;
2011 else if (strcmp (string, "jumps") == 0)
2012 ;
2013 else
2014 as_bad (_("no such architecture modifier: `%s'"), string);
2015
2016 *input_line_pointer = e;
2017 }
2018
e413e4e9
AM		 2019 demand_empty_rest_of_line ();
2020}
2021
b9d79e03
JH		 2022unsigned long
2023i386_mach ()
2024{
2025 if (!strcmp (default_arch, "x86_64"))
2026 return bfd_mach_x86_64;
2027 else if (!strcmp (default_arch, "i386"))
2028 return bfd_mach_i386_i386;
2029 else
2030 as_fatal (_("Unknown architecture"));
2031}
b9d79e03 2032\f
252b5132
RH		 2033void
2034md_begin ()
2035{
2036 const char *hash_err;
2037
47926f60 2038 /* Initialize op_hash hash table. */
252b5132
RH		 2039 op_hash = hash_new ();
2040
2041 {
29b0f896
AM		 2042 const template *optab;
2043 templates *core_optab;
252b5132 2044
47926f60
KH		 2045 /* Setup for loop. */
2046 optab = i386_optab;
252b5132
RH		 2047 core_optab = (templates *) xmalloc (sizeof (templates));
2048 core_optab->start = optab;
2049
2050 while (1)
2051 {
2052 ++optab;
2053 if (optab->name == NULL
2054 || strcmp (optab->name, (optab - 1)->name) != 0)
2055 {
2056 /* different name --> ship out current template list;
47926f60 2057 add to hash table; & begin anew. */
252b5132
RH		 2058 core_optab->end = optab;
2059 hash_err = hash_insert (op_hash,
2060 (optab - 1)->name,
5a49b8ac 2061 (void *) core_optab);
252b5132
RH		 2062 if (hash_err)
2063 {
252b5132
RH		 2064 as_fatal (_("Internal Error: Can't hash %s: %s"),
2065 (optab - 1)->name,
2066 hash_err);
2067 }
2068 if (optab->name == NULL)
2069 break;
2070 core_optab = (templates *) xmalloc (sizeof (templates));
2071 core_optab->start = optab;
2072 }
2073 }
2074 }
2075
47926f60 2076 /* Initialize reg_hash hash table. */
252b5132
RH		 2077 reg_hash = hash_new ();
2078 {
29b0f896 2079 const reg_entry *regtab;
c3fe08fa 2080 unsigned int regtab_size = i386_regtab_size;
252b5132 2081
c3fe08fa 2082 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2083 {
5a49b8ac 2084 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2085 if (hash_err)
3e73aa7c
JH		 2086 as_fatal (_("Internal Error: Can't hash %s: %s"),
2087 regtab->reg_name,
2088 hash_err);
252b5132
RH		 2089 }
2090 }
2091
47926f60 2092 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2093 {
29b0f896
AM		 2094 int c;
2095 char *p;
252b5132
RH		 2096
2097 for (c = 0; c < 256; c++)
2098 {
3882b010 2099 if (ISDIGIT (c))
252b5132
RH		 2100 {
2101 digit_chars[c] = c;
2102 mnemonic_chars[c] = c;
2103 register_chars[c] = c;
2104 operand_chars[c] = c;
2105 }
3882b010 2106 else if (ISLOWER (c))
252b5132
RH		 2107 {
2108 mnemonic_chars[c] = c;
2109 register_chars[c] = c;
2110 operand_chars[c] = c;
2111 }
3882b010 2112 else if (ISUPPER (c))
252b5132 2113 {
3882b010 2114 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2115 register_chars[c] = mnemonic_chars[c];
2116 operand_chars[c] = c;
2117 }
2118
3882b010 2119 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2120 identifier_chars[c] = c;
2121 else if (c >= 128)
2122 {
2123 identifier_chars[c] = c;
2124 operand_chars[c] = c;
2125 }
2126 }
2127
2128#ifdef LEX_AT
2129 identifier_chars['@'] = '@';
32137342
NC		 2130#endif
2131#ifdef LEX_QM
2132 identifier_chars['?'] = '?';
2133 operand_chars['?'] = '?';
252b5132 2134#endif
252b5132 2135 digit_chars['-'] = '-';
c0f3af97 2136 mnemonic_chars['_'] = '_';
791fe849 2137 mnemonic_chars['-'] = '-';
0003779b 2138 mnemonic_chars['.'] = '.';
252b5132
RH		 2139 identifier_chars['_'] = '_';
2140 identifier_chars['.'] = '.';
2141
2142 for (p = operand_special_chars; *p != '\0'; p++)
2143 operand_chars[(unsigned char) *p] = *p;
2144 }
2145
2146#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2147 if (IS_ELF)
252b5132
RH		 2148 {
2149 record_alignment (text_section, 2);
2150 record_alignment (data_section, 2);
2151 record_alignment (bss_section, 2);
2152 }
2153#endif
a4447b93
RH		 2154
2155 if (flag_code == CODE_64BIT)
2156 {
2157 x86_dwarf2_return_column = 16;
2158 x86_cie_data_alignment = -8;
2159 }
2160 else
2161 {
2162 x86_dwarf2_return_column = 8;
2163 x86_cie_data_alignment = -4;
2164 }
252b5132
RH		 2165}
2166
2167void
e3bb37b5 2168i386_print_statistics (FILE *file)
252b5132
RH		 2169{
2170 hash_print_statistics (file, "i386 opcode", op_hash);
2171 hash_print_statistics (file, "i386 register", reg_hash);
2172}
2173\f
252b5132
RH		 2174#ifdef DEBUG386
2175
ce8a8b2f 2176/* Debugging routines for md_assemble. */
e3bb37b5 2177static void pte (template *);
40fb9820 2178static void pt (i386_operand_type);
e3bb37b5
L		 2179static void pe (expressionS *);
2180static void ps (symbolS *);
252b5132
RH		 2181
2182static void
e3bb37b5 2183pi (char *line, i386_insn *x)
252b5132 2184{
09f131f2 2185 unsigned int i;
252b5132
RH		 2186
2187 fprintf (stdout, "%s: template ", line);
2188 pte (&x->tm);
09f131f2
JH		 2189 fprintf (stdout, " address: base %s index %s scale %x\n",
2190 x->base_reg ? x->base_reg->reg_name : "none",
2191 x->index_reg ? x->index_reg->reg_name : "none",
2192 x->log2_scale_factor);
2193 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2194 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2195 fprintf (stdout, " sib: base %x index %x scale %x\n",
2196 x->sib.base, x->sib.index, x->sib.scale);
2197 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2198 (x->rex & REX_W) != 0,
2199 (x->rex & REX_R) != 0,
2200 (x->rex & REX_X) != 0,
2201 (x->rex & REX_B) != 0);
85f10a01
MM		 2202 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2203 x->drex.reg, x->drex.rex);
252b5132
RH		 2204 for (i = 0; i < x->operands; i++)
2205 {
2206 fprintf (stdout, " #%d: ", i + 1);
2207 pt (x->types[i]);
2208 fprintf (stdout, "\n");
40fb9820
L		 2209 if (x->types[i].bitfield.reg8
2210 || x->types[i].bitfield.reg16
2211 || x->types[i].bitfield.reg32
2212 || x->types[i].bitfield.reg64
2213 || x->types[i].bitfield.regmmx
2214 || x->types[i].bitfield.regxmm
c0f3af97 2215 || x->types[i].bitfield.regymm
40fb9820
L		 2216 || x->types[i].bitfield.sreg2
2217 || x->types[i].bitfield.sreg3
2218 || x->types[i].bitfield.control
2219 || x->types[i].bitfield.debug
2220 || x->types[i].bitfield.test)
520dc8e8 2221 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2222 if (operand_type_check (x->types[i], imm))
520dc8e8 2223 pe (x->op[i].imms);
40fb9820 2224 if (operand_type_check (x->types[i], disp))
520dc8e8 2225 pe (x->op[i].disps);
252b5132
RH		 2226 }
2227}
2228
2229static void
e3bb37b5 2230pte (template *t)
252b5132 2231{
09f131f2 2232 unsigned int i;
252b5132 2233 fprintf (stdout, " %d operands ", t->operands);
47926f60 2234 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2235 if (t->extension_opcode != None)
2236 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2237 if (t->opcode_modifier.d)
252b5132 2238 fprintf (stdout, "D");
40fb9820 2239 if (t->opcode_modifier.w)
252b5132
RH		 2240 fprintf (stdout, "W");
2241 fprintf (stdout, "\n");
2242 for (i = 0; i < t->operands; i++)
2243 {
2244 fprintf (stdout, " #%d type ", i + 1);
2245 pt (t->operand_types[i]);
2246 fprintf (stdout, "\n");
2247 }
2248}
2249
2250static void
e3bb37b5 2251pe (expressionS *e)
252b5132 2252{
24eab124 2253 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2254 fprintf (stdout, " add_number %ld (%lx)\n",
2255 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2256 if (e->X_add_symbol)
2257 {
2258 fprintf (stdout, " add_symbol ");
2259 ps (e->X_add_symbol);
2260 fprintf (stdout, "\n");
2261 }
2262 if (e->X_op_symbol)
2263 {
2264 fprintf (stdout, " op_symbol ");
2265 ps (e->X_op_symbol);
2266 fprintf (stdout, "\n");
2267 }
2268}
2269
2270static void
e3bb37b5 2271ps (symbolS *s)
252b5132
RH		 2272{
2273 fprintf (stdout, "%s type %s%s",
2274 S_GET_NAME (s),
2275 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2276 segment_name (S_GET_SEGMENT (s)));
2277}
2278
7b81dfbb 2279static struct type_name
252b5132 2280 {
40fb9820
L		 2281 i386_operand_type mask;
2282 const char *name;
252b5132 2283 }
7b81dfbb 2284const type_names[] =
252b5132 2285{
40fb9820
L		 2286 { OPERAND_TYPE_REG8, "r8" },
2287 { OPERAND_TYPE_REG16, "r16" },
2288 { OPERAND_TYPE_REG32, "r32" },
2289 { OPERAND_TYPE_REG64, "r64" },
2290 { OPERAND_TYPE_IMM8, "i8" },
2291 { OPERAND_TYPE_IMM8, "i8s" },
2292 { OPERAND_TYPE_IMM16, "i16" },
2293 { OPERAND_TYPE_IMM32, "i32" },
2294 { OPERAND_TYPE_IMM32S, "i32s" },
2295 { OPERAND_TYPE_IMM64, "i64" },
2296 { OPERAND_TYPE_IMM1, "i1" },
2297 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2298 { OPERAND_TYPE_DISP8, "d8" },
2299 { OPERAND_TYPE_DISP16, "d16" },
2300 { OPERAND_TYPE_DISP32, "d32" },
2301 { OPERAND_TYPE_DISP32S, "d32s" },
2302 { OPERAND_TYPE_DISP64, "d64" },
2303 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2304 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2305 { OPERAND_TYPE_CONTROL, "control reg" },
2306 { OPERAND_TYPE_TEST, "test reg" },
2307 { OPERAND_TYPE_DEBUG, "debug reg" },
2308 { OPERAND_TYPE_FLOATREG, "FReg" },
2309 { OPERAND_TYPE_FLOATACC, "FAcc" },
2310 { OPERAND_TYPE_SREG2, "SReg2" },
2311 { OPERAND_TYPE_SREG3, "SReg3" },
2312 { OPERAND_TYPE_ACC, "Acc" },
2313 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2314 { OPERAND_TYPE_REGMMX, "rMMX" },
2315 { OPERAND_TYPE_REGXMM, "rXMM" },
2316 { OPERAND_TYPE_ESSEG, "es" },
c0f3af97 2317 { OPERAND_TYPE_VEX_IMM4, "VEX i4" },
252b5132
RH		 2318};
2319
2320static void
40fb9820 2321pt (i386_operand_type t)
252b5132 2322{
40fb9820 2323 unsigned int j;
c6fb90c8 2324 i386_operand_type a;
252b5132 2325
40fb9820 2326 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2327 {
2328 a = operand_type_and (t, type_names[j].mask);
2329 if (!UINTS_ALL_ZERO (a))
2330 fprintf (stdout, "%s, ", type_names[j].name);
2331 }
252b5132
RH		 2332 fflush (stdout);
2333}
2334
2335#endif /* DEBUG386 */
2336\f
252b5132 2337static bfd_reloc_code_real_type
3956db08 2338reloc (unsigned int size,
64e74474
AM		 2339 int pcrel,
2340 int sign,
2341 bfd_reloc_code_real_type other)
252b5132 2342{
47926f60 2343 if (other != NO_RELOC)
3956db08
JB		 2344 {
2345 reloc_howto_type *reloc;
2346
2347 if (size == 8)
2348 switch (other)
2349 {
64e74474
AM		 2350 case BFD_RELOC_X86_64_GOT32:
2351 return BFD_RELOC_X86_64_GOT64;
2352 break;
2353 case BFD_RELOC_X86_64_PLTOFF64:
2354 return BFD_RELOC_X86_64_PLTOFF64;
2355 break;
2356 case BFD_RELOC_X86_64_GOTPC32:
2357 other = BFD_RELOC_X86_64_GOTPC64;
2358 break;
2359 case BFD_RELOC_X86_64_GOTPCREL:
2360 other = BFD_RELOC_X86_64_GOTPCREL64;
2361 break;
2362 case BFD_RELOC_X86_64_TPOFF32:
2363 other = BFD_RELOC_X86_64_TPOFF64;
2364 break;
2365 case BFD_RELOC_X86_64_DTPOFF32:
2366 other = BFD_RELOC_X86_64_DTPOFF64;
2367 break;
2368 default:
2369 break;
3956db08 2370 }
e05278af
JB		 2371
2372 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2373 if (size == 4 && flag_code != CODE_64BIT)
2374 sign = -1;
2375
3956db08
JB		 2376 reloc = bfd_reloc_type_lookup (stdoutput, other);
2377 if (!reloc)
2378 as_bad (_("unknown relocation (%u)"), other);
2379 else if (size != bfd_get_reloc_size (reloc))
2380 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2381 bfd_get_reloc_size (reloc),
2382 size);
2383 else if (pcrel && !reloc->pc_relative)
2384 as_bad (_("non-pc-relative relocation for pc-relative field"));
2385 else if ((reloc->complain_on_overflow == complain_overflow_signed
2386 && !sign)
2387 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2388 && sign > 0))
3956db08
JB		 2389 as_bad (_("relocated field and relocation type differ in signedness"));
2390 else
2391 return other;
2392 return NO_RELOC;
2393 }
252b5132
RH		 2394
2395 if (pcrel)
2396 {
3e73aa7c 2397 if (!sign)
3956db08 2398 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2399 switch (size)
2400 {
2401 case 1: return BFD_RELOC_8_PCREL;
2402 case 2: return BFD_RELOC_16_PCREL;
2403 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2404 case 8: return BFD_RELOC_64_PCREL;
252b5132 2405 }
3956db08 2406 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2407 }
2408 else
2409 {
3956db08 2410 if (sign > 0)
e5cb08ac 2411 switch (size)
3e73aa7c
JH		 2412 {
2413 case 4: return BFD_RELOC_X86_64_32S;
2414 }
2415 else
2416 switch (size)
2417 {
2418 case 1: return BFD_RELOC_8;
2419 case 2: return BFD_RELOC_16;
2420 case 4: return BFD_RELOC_32;
2421 case 8: return BFD_RELOC_64;
2422 }
3956db08
JB		 2423 as_bad (_("cannot do %s %u byte relocation"),
2424 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2425 }
2426
bfb32b52 2427 abort ();
252b5132
RH		 2428 return BFD_RELOC_NONE;
2429}
2430
47926f60
KH		 2431/* Here we decide which fixups can be adjusted to make them relative to
2432 the beginning of the section instead of the symbol. Basically we need
2433 to make sure that the dynamic relocations are done correctly, so in
2434 some cases we force the original symbol to be used. */
2435
252b5132 2436int
e3bb37b5 2437tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2438{
6d249963 2439#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2440 if (!IS_ELF)
31312f95
AM		 2441 return 1;
2442
a161fe53
AM		 2443 /* Don't adjust pc-relative references to merge sections in 64-bit
2444 mode. */
2445 if (use_rela_relocations
2446 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2447 && fixP->fx_pcrel)
252b5132 2448 return 0;
31312f95 2449
8d01d9a9
AJ		 2450 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2451 and changed later by validate_fix. */
2452 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2453 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2454 return 0;
2455
ce8a8b2f 2456 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2457 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2458 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2459 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2460 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2461 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2462 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2463 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2464 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2465 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2466 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2467 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2468 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2469 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2470 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2471 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2472 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2473 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2474 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2475 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2476 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2477 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2478 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2479 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2480 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2481 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2482 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2483 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2484 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2485 return 0;
31312f95 2486#endif
252b5132
RH		 2487 return 1;
2488}
252b5132 2489
b4cac588 2490static int
e3bb37b5 2491intel_float_operand (const char *mnemonic)
252b5132 2492{
9306ca4a
JB		 2493 /* Note that the value returned is meaningful only for opcodes with (memory)
2494 operands, hence the code here is free to improperly handle opcodes that
2495 have no operands (for better performance and smaller code). */
2496
2497 if (mnemonic[0] != 'f')
2498 return 0; /* non-math */
2499
2500 switch (mnemonic[1])
2501 {
2502 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2503 the fs segment override prefix not currently handled because no
2504 call path can make opcodes without operands get here */
2505 case 'i':
2506 return 2 /* integer op */;
2507 case 'l':
2508 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2509 return 3; /* fldcw/fldenv */
2510 break;
2511 case 'n':
2512 if (mnemonic[2] != 'o' /* fnop */)
2513 return 3; /* non-waiting control op */
2514 break;
2515 case 'r':
2516 if (mnemonic[2] == 's')
2517 return 3; /* frstor/frstpm */
2518 break;
2519 case 's':
2520 if (mnemonic[2] == 'a')
2521 return 3; /* fsave */
2522 if (mnemonic[2] == 't')
2523 {
2524 switch (mnemonic[3])
2525 {
2526 case 'c': /* fstcw */
2527 case 'd': /* fstdw */
2528 case 'e': /* fstenv */
2529 case 's': /* fsts[gw] */
2530 return 3;
2531 }
2532 }
2533 break;
2534 case 'x':
2535 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2536 return 0; /* fxsave/fxrstor are not really math ops */
2537 break;
2538 }
252b5132 2539
9306ca4a 2540 return 1;
252b5132
RH		 2541}
2542
c0f3af97
L		 2543/* Build the VEX prefix. */
2544
2545static void
fa99fab2 2546build_vex_prefix (const template *t)
c0f3af97
L		 2547{
2548 unsigned int register_specifier;
2549 unsigned int implied_prefix;
2550 unsigned int vector_length;
2551
2552 /* Check register specifier. */
2553 if (i.vex.register_specifier)
2554 {
2555 register_specifier = i.vex.register_specifier->reg_num;
2556 if ((i.vex.register_specifier->reg_flags & RegRex))
2557 register_specifier += 8;
2558 register_specifier = ~register_specifier & 0xf;
2559 }
2560 else
2561 register_specifier = 0xf;
2562
fa99fab2
L		 2563 /* Use 2-byte VEX prefix by swappping destination and source
2564 operand. */
2565 if (!i.swap_operand
2566 && i.operands == i.reg_operands
2567 && i.tm.opcode_modifier.vex0f
2568 && i.tm.opcode_modifier.s
2569 && i.rex == REX_B)
2570 {
2571 unsigned int xchg = i.operands - 1;
2572 union i386_op temp_op;
2573 i386_operand_type temp_type;
2574
2575 temp_type = i.types[xchg];
2576 i.types[xchg] = i.types[0];
2577 i.types[0] = temp_type;
2578 temp_op = i.op[xchg];
2579 i.op[xchg] = i.op[0];
2580 i.op[0] = temp_op;
2581
2582 assert (i.rm.mode == 3);
2583
2584 i.rex = REX_R;
2585 xchg = i.rm.regmem;
2586 i.rm.regmem = i.rm.reg;
2587 i.rm.reg = xchg;
2588
2589 /* Use the next insn. */
2590 i.tm = t[1];
2591 }
2592
c0f3af97
L		 2593 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2594
2595 switch ((i.tm.base_opcode >> 8) & 0xff)
2596 {
2597 case 0:
2598 implied_prefix = 0;
2599 break;
2600 case DATA_PREFIX_OPCODE:
2601 implied_prefix = 1;
2602 break;
2603 case REPE_PREFIX_OPCODE:
2604 implied_prefix = 2;
2605 break;
2606 case REPNE_PREFIX_OPCODE:
2607 implied_prefix = 3;
2608 break;
2609 default:
2610 abort ();
2611 }
2612
2613 /* Use 2-byte VEX prefix if possible. */
2614 if (i.tm.opcode_modifier.vex0f
2615 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2616 {
2617 /* 2-byte VEX prefix. */
2618 unsigned int r;
2619
2620 i.vex.length = 2;
2621 i.vex.bytes[0] = 0xc5;
2622
2623 /* Check the REX.R bit. */
2624 r = (i.rex & REX_R) ? 0 : 1;
2625 i.vex.bytes[1] = (r << 7
2626 | register_specifier << 3
2627 | vector_length << 2
2628 | implied_prefix);
2629 }
2630 else
2631 {
2632 /* 3-byte VEX prefix. */
2633 unsigned int m, w;
2634
2635 if (i.tm.opcode_modifier.vex0f)
2636 m = 0x1;
2637 else if (i.tm.opcode_modifier.vex0f38)
2638 m = 0x2;
2639 else if (i.tm.opcode_modifier.vex0f3a)
2640 m = 0x3;
2641 else
2642 abort ();
2643
2644 i.vex.length = 3;
2645 i.vex.bytes[0] = 0xc4;
2646
2647 /* The high 3 bits of the second VEX byte are 1's compliment
2648 of RXB bits from REX. */
2649 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2650
2651 /* Check the REX.W bit. */
2652 w = (i.rex & REX_W) ? 1 : 0;
2653 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2654 {
2655 if (w)
2656 abort ();
2657
2658 if (i.tm.opcode_modifier.vexw1)
2659 w = 1;
2660 }
2661
2662 i.vex.bytes[2] = (w << 7
2663 | register_specifier << 3
2664 | vector_length << 2
2665 | implied_prefix);
2666 }
2667}
2668
65da13b5
L		 2669static void
2670process_immext (void)
2671{
2672 expressionS *exp;
2673
2674 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2675 {
1fed0ba1
L		 2676 /* SSE3 Instructions have the fixed operands with an opcode
2677 suffix which is coded in the same place as an 8-bit immediate
2678 field would be. Here we check those operands and remove them
2679 afterwards. */
65da13b5
L		 2680 unsigned int x;
2681
2682 for (x = 0; x < i.operands; x++)
2683 if (i.op[x].regs->reg_num != x)
2684 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2685 register_prefix, i.op[x].regs->reg_name, x + 1,
2686 i.tm.name);
2687
2688 i.operands = 0;
65da13b5
L		 2689 }
2690
c0f3af97 2691 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2692 which is coded in the same place as an 8-bit immediate field
2693 would be. Here we fake an 8-bit immediate operand from the
2694 opcode suffix stored in tm.extension_opcode.
2695
c0f3af97
L		 2696 SSE5 and AVX instructions also use this encoding, for some of
2697 3 argument instructions. */
65da13b5
L		 2698
2699 assert (i.imm_operands == 0
2700 && (i.operands <= 2
2701 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L		 2702 && i.operands <= 3)
2703 || (i.tm.opcode_modifier.vex
2704 && i.operands <= 4)));
65da13b5
L		 2705
2706 exp = &im_expressions[i.imm_operands++];
2707 i.op[i.operands].imms = exp;
2708 i.types[i.operands] = imm8;
2709 i.operands++;
2710 exp->X_op = O_constant;
2711 exp->X_add_number = i.tm.extension_opcode;
2712 i.tm.extension_opcode = None;
2713}
2714
252b5132
RH		 2715/* This is the guts of the machine-dependent assembler. LINE points to a
2716 machine dependent instruction. This function is supposed to emit
2717 the frags/bytes it assembles to. */
2718
2719void
65da13b5 2720md_assemble (char *line)
252b5132 2721{
40fb9820 2722 unsigned int j;
252b5132 2723 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2724 const template *t;
252b5132 2725
47926f60 2726 /* Initialize globals. */
252b5132
RH		 2727 memset (&i, '\0', sizeof (i));
2728 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2729 i.reloc[j] = NO_RELOC;
252b5132
RH		 2730 memset (disp_expressions, '\0', sizeof (disp_expressions));
2731 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2732 save_stack_p = save_stack;
252b5132
RH		 2733
2734 /* First parse an instruction mnemonic & call i386_operand for the operands.
2735 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2736 start of a (possibly prefixed) mnemonic. */
252b5132 2737
29b0f896
AM		 2738 line = parse_insn (line, mnemonic);
2739 if (line == NULL)
2740 return;
252b5132 2741
29b0f896
AM		 2742 line = parse_operands (line, mnemonic);
2743 if (line == NULL)
2744 return;
252b5132 2745
29b0f896
AM		 2746 /* Now we've parsed the mnemonic into a set of templates, and have the
2747 operands at hand. */
2748
2749 /* All intel opcodes have reversed operands except for "bound" and
2750 "enter". We also don't reverse intersegment "jmp" and "call"
2751 instructions with 2 immediate operands so that the immediate segment
050dfa73 2752 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2753 if (intel_syntax
2754 && i.operands > 1
29b0f896 2755 && (strcmp (mnemonic, "bound") != 0)
30123838 2756 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2757 && !(operand_type_check (i.types[0], imm)
2758 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2759 swap_operands ();
2760
ec56d5c0
JB		 2761 /* The order of the immediates should be reversed
2762 for 2 immediates extrq and insertq instructions */
2763 if (i.imm_operands == 2
2764 && (strcmp (mnemonic, "extrq") == 0
2765 || strcmp (mnemonic, "insertq") == 0))
2766 swap_2_operands (0, 1);
2767
29b0f896
AM		 2768 if (i.imm_operands)
2769 optimize_imm ();
2770
b300c311
L		 2771 /* Don't optimize displacement for movabs since it only takes 64bit
2772 displacement. */
2773 if (i.disp_operands
2774 && (flag_code != CODE_64BIT
2775 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2776 optimize_disp ();
2777
2778 /* Next, we find a template that matches the given insn,
2779 making sure the overlap of the given operands types is consistent
2780 with the template operand types. */
252b5132 2781
fa99fab2 2782 if (!(t = match_template ()))
29b0f896 2783 return;
252b5132 2784
daf50ae7 2785 if (sse_check != sse_check_none
81f8a913 2786 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2787 && (i.tm.cpu_flags.bitfield.cpusse
2788 || i.tm.cpu_flags.bitfield.cpusse2
2789 || i.tm.cpu_flags.bitfield.cpusse3
2790 || i.tm.cpu_flags.bitfield.cpussse3
2791 || i.tm.cpu_flags.bitfield.cpusse4_1
2792 || i.tm.cpu_flags.bitfield.cpusse4_2))
2793 {
2794 (sse_check == sse_check_warning
2795 ? as_warn
2796 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2797 }
2798
321fd21e
L		 2799 /* Zap movzx and movsx suffix. The suffix has been set from
2800 "word ptr" or "byte ptr" on the source operand in Intel syntax
2801 or extracted from mnemonic in AT&T syntax. But we'll use
2802 the destination register to choose the suffix for encoding. */
2803 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2804 {
321fd21e
L		 2805 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2806 there is no suffix, the default will be byte extension. */
2807 if (i.reg_operands != 2
2808 && !i.suffix
2809 && intel_syntax)
2810 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2811
2812 i.suffix = 0;
cd61ebfe 2813 }
24eab124 2814
40fb9820 2815 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2816 if (!add_prefix (FWAIT_OPCODE))
2817 return;
252b5132 2818
29b0f896 2819 /* Check string instruction segment overrides. */
40fb9820 2820 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2821 {
2822 if (!check_string ())
5dd0794d 2823 return;
fc0763e6 2824 i.disp_operands = 0;
29b0f896 2825 }
5dd0794d 2826
29b0f896
AM		 2827 if (!process_suffix ())
2828 return;
e413e4e9 2829
29b0f896
AM		 2830 /* Make still unresolved immediate matches conform to size of immediate
2831 given in i.suffix. */
2832 if (!finalize_imm ())
2833 return;
252b5132 2834
40fb9820 2835 if (i.types[0].bitfield.imm1)
29b0f896 2836 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2837
40fb9820 2838 for (j = 0; j < 3; j++)
c6fb90c8
L		 2839 if (i.types[j].bitfield.inoutportreg
2840 || i.types[j].bitfield.shiftcount
2841 || i.types[j].bitfield.acc
2842 || i.types[j].bitfield.floatacc)
40fb9820
L		 2843 i.reg_operands--;
2844
c0f3af97
L		 2845 /* ImmExt should be processed after SSE2AVX. */
2846 if (!i.tm.opcode_modifier.sse2avx
2847 && i.tm.opcode_modifier.immext)
65da13b5 2848 process_immext ();
252b5132 2849
29b0f896
AM		 2850 /* For insns with operands there are more diddles to do to the opcode. */
2851 if (i.operands)
2852 {
2853 if (!process_operands ())
2854 return;
2855 }
40fb9820 2856 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2857 {
2858 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2859 as_warn (_("translating to `%sp'"), i.tm.name);
2860 }
252b5132 2861
c0f3af97 2862 if (i.tm.opcode_modifier.vex)
fa99fab2 2863 build_vex_prefix (t);
c0f3af97 2864
29b0f896
AM		 2865 /* Handle conversion of 'int $3' --> special int3 insn. */
2866 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2867 {
2868 i.tm.base_opcode = INT3_OPCODE;
2869 i.imm_operands = 0;
2870 }
252b5132 2871
40fb9820
L		 2872 if ((i.tm.opcode_modifier.jump
2873 || i.tm.opcode_modifier.jumpbyte
2874 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2875 && i.op[0].disps->X_op == O_constant)
2876 {
2877 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2878 the absolute address given by the constant. Since ix86 jumps and
2879 calls are pc relative, we need to generate a reloc. */
2880 i.op[0].disps->X_add_symbol = &abs_symbol;
2881 i.op[0].disps->X_op = O_symbol;
2882 }
252b5132 2883
40fb9820 2884 if (i.tm.opcode_modifier.rex64)
161a04f6 2885 i.rex |= REX_W;
252b5132 2886
29b0f896
AM		 2887 /* For 8 bit registers we need an empty rex prefix. Also if the
2888 instruction already has a prefix, we need to convert old
2889 registers to new ones. */
773f551c 2890
40fb9820 2891 if ((i.types[0].bitfield.reg8
29b0f896 2892 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2893 || (i.types[1].bitfield.reg8
29b0f896 2894 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2895 || ((i.types[0].bitfield.reg8
2896 || i.types[1].bitfield.reg8)
29b0f896
AM		 2897 && i.rex != 0))
2898 {
2899 int x;
726c5dcd 2900
29b0f896
AM		 2901 i.rex |= REX_OPCODE;
2902 for (x = 0; x < 2; x++)
2903 {
2904 /* Look for 8 bit operand that uses old registers. */
40fb9820 2905 if (i.types[x].bitfield.reg8
29b0f896 2906 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2907 {
29b0f896
AM		 2908 /* In case it is "hi" register, give up. */
2909 if (i.op[x].regs->reg_num > 3)
a540244d 2910 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2911 "instruction requiring REX prefix."),
a540244d 2912 register_prefix, i.op[x].regs->reg_name);
773f551c 2913
29b0f896
AM		 2914 /* Otherwise it is equivalent to the extended register.
2915 Since the encoding doesn't change this is merely
2916 cosmetic cleanup for debug output. */
2917
2918 i.op[x].regs = i.op[x].regs + 8;
773f551c 2919 }
29b0f896
AM		 2920 }
2921 }
773f551c 2922
85f10a01
MM		 2923 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2924 REX prefix. */
2925 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2926 {
2927 i.drex.rex = i.rex;
2928 i.rex = 0;
2929 }
2930 else if (i.rex != 0)
29b0f896
AM		 2931 add_prefix (REX_OPCODE | i.rex);
2932
2933 /* We are ready to output the insn. */
2934 output_insn ();
2935}
2936
2937static char *
e3bb37b5 2938parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2939{
2940 char *l = line;
2941 char *token_start = l;
2942 char *mnem_p;
5c6af06e
JB		 2943 int supported;
2944 const template *t;
b6169b20 2945 char *dot_p = NULL;
29b0f896
AM		 2946
2947 /* Non-zero if we found a prefix only acceptable with string insns. */
2948 const char *expecting_string_instruction = NULL;
45288df1 2949
29b0f896
AM		 2950 while (1)
2951 {
2952 mnem_p = mnemonic;
2953 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2954 {
b6169b20
L		 2955 if (*mnem_p == '.')
2956 dot_p = mnem_p;
29b0f896
AM		 2957 mnem_p++;
2958 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2959 {
29b0f896
AM		 2960 as_bad (_("no such instruction: `%s'"), token_start);
2961 return NULL;
2962 }
2963 l++;
2964 }
2965 if (!is_space_char (*l)
2966 && *l != END_OF_INSN
e44823cf
JB		 2967 && (intel_syntax
2968 || (*l != PREFIX_SEPARATOR
2969 && *l != ',')))
29b0f896
AM		 2970 {
2971 as_bad (_("invalid character %s in mnemonic"),
2972 output_invalid (*l));
2973 return NULL;
2974 }
2975 if (token_start == l)
2976 {
e44823cf 2977 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2978 as_bad (_("expecting prefix; got nothing"));
2979 else
2980 as_bad (_("expecting mnemonic; got nothing"));
2981 return NULL;
2982 }
45288df1 2983
29b0f896
AM		 2984 /* Look up instruction (or prefix) via hash table. */
2985 current_templates = hash_find (op_hash, mnemonic);
47926f60 2986
29b0f896
AM		 2987 if (*l != END_OF_INSN
2988 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2989 && current_templates
40fb9820 2990 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2991 {
c6fb90c8 2992 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2993 {
2994 as_bad ((flag_code != CODE_64BIT
2995 ? _("`%s' is only supported in 64-bit mode")
2996 : _("`%s' is not supported in 64-bit mode")),
2997 current_templates->start->name);
2998 return NULL;
2999 }
29b0f896
AM		 3000 /* If we are in 16-bit mode, do not allow addr16 or data16.
3001 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3002 if ((current_templates->start->opcode_modifier.size16
3003 || current_templates->start->opcode_modifier.size32)
29b0f896 3004 && flag_code != CODE_64BIT
40fb9820 3005 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3006 ^ (flag_code == CODE_16BIT)))
3007 {
3008 as_bad (_("redundant %s prefix"),
3009 current_templates->start->name);
3010 return NULL;
45288df1 3011 }
29b0f896
AM		 3012 /* Add prefix, checking for repeated prefixes. */
3013 switch (add_prefix (current_templates->start->base_opcode))
3014 {
3015 case 0:
3016 return NULL;
3017 case 2:
3018 expecting_string_instruction = current_templates->start->name;
3019 break;
3020 }
3021 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3022 token_start = ++l;
3023 }
3024 else
3025 break;
3026 }
45288df1 3027
30a55f88 3028 if (!current_templates)
b6169b20 3029 {
30a55f88
L		 3030 /* Check if we should swap operand in encoding. */
3031 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3032 i.swap_operand = 1;
3033 else
3034 goto check_suffix;
3035 mnem_p = dot_p;
3036 *dot_p = '\0';
3037 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L		 3038 }
3039
29b0f896
AM		 3040 if (!current_templates)
3041 {
b6169b20 3042check_suffix:
29b0f896
AM		 3043 /* See if we can get a match by trimming off a suffix. */
3044 switch (mnem_p[-1])
3045 {
3046 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3047 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3048 i.suffix = SHORT_MNEM_SUFFIX;
3049 else
29b0f896
AM		 3050 case BYTE_MNEM_SUFFIX:
3051 case QWORD_MNEM_SUFFIX:
3052 i.suffix = mnem_p[-1];
3053 mnem_p[-1] = '\0';
3054 current_templates = hash_find (op_hash, mnemonic);
3055 break;
3056 case SHORT_MNEM_SUFFIX:
3057 case LONG_MNEM_SUFFIX:
3058 if (!intel_syntax)
3059 {
3060 i.suffix = mnem_p[-1];
3061 mnem_p[-1] = '\0';
3062 current_templates = hash_find (op_hash, mnemonic);
3063 }
3064 break;
252b5132 3065
29b0f896
AM		 3066 /* Intel Syntax. */
3067 case 'd':
3068 if (intel_syntax)
3069 {
9306ca4a 3070 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3071 i.suffix = SHORT_MNEM_SUFFIX;
3072 else
3073 i.suffix = LONG_MNEM_SUFFIX;
3074 mnem_p[-1] = '\0';
3075 current_templates = hash_find (op_hash, mnemonic);
3076 }
3077 break;
3078 }
3079 if (!current_templates)
3080 {
3081 as_bad (_("no such instruction: `%s'"), token_start);
3082 return NULL;
3083 }
3084 }
252b5132 3085
40fb9820
L		 3086 if (current_templates->start->opcode_modifier.jump
3087 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3088 {
3089 /* Check for a branch hint. We allow ",pt" and ",pn" for
3090 predict taken and predict not taken respectively.
3091 I'm not sure that branch hints actually do anything on loop
3092 and jcxz insns (JumpByte) for current Pentium4 chips. They
3093 may work in the future and it doesn't hurt to accept them
3094 now. */
3095 if (l[0] == ',' && l[1] == 'p')
3096 {
3097 if (l[2] == 't')
3098 {
3099 if (!add_prefix (DS_PREFIX_OPCODE))
3100 return NULL;
3101 l += 3;
3102 }
3103 else if (l[2] == 'n')
3104 {
3105 if (!add_prefix (CS_PREFIX_OPCODE))
3106 return NULL;
3107 l += 3;
3108 }
3109 }
3110 }
3111 /* Any other comma loses. */
3112 if (*l == ',')
3113 {
3114 as_bad (_("invalid character %s in mnemonic"),
3115 output_invalid (*l));
3116 return NULL;
3117 }
252b5132 3118
29b0f896 3119 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3120 supported = 0;
3121 for (t = current_templates->start; t < current_templates->end; ++t)
3122 {
c0f3af97
L		 3123 supported |= cpu_flags_match (t);
3124 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3125 goto skip;
5c6af06e 3126 }
3629bb00 3127
c0f3af97 3128 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3129 {
3130 as_bad (flag_code == CODE_64BIT
3131 ? _("`%s' is not supported in 64-bit mode")
3132 : _("`%s' is only supported in 64-bit mode"),
3133 current_templates->start->name);
3134 return NULL;
3135 }
c0f3af97 3136 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3137 {
3629bb00
L		 3138 as_bad (_("`%s' is not supported on `%s%s'"),
3139 current_templates->start->name, cpu_arch_name,
3140 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3141 return NULL;
29b0f896 3142 }
3629bb00
L		 3143
3144skip:
3145 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3146 && (flag_code != CODE_16BIT))
29b0f896
AM		 3147 {
3148 as_warn (_("use .code16 to ensure correct addressing mode"));
3149 }
252b5132 3150
29b0f896 3151 /* Check for rep/repne without a string instruction. */
f41bbced 3152 if (expecting_string_instruction)
29b0f896 3153 {
f41bbced
JB		 3154 static templates override;
3155
3156 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3157 if (t->opcode_modifier.isstring)
f41bbced
JB		 3158 break;
3159 if (t >= current_templates->end)
3160 {
3161 as_bad (_("expecting string instruction after `%s'"),
64e74474 3162 expecting_string_instruction);
f41bbced
JB		 3163 return NULL;
3164 }
3165 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3166 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3167 break;
3168 override.end = t;
3169 current_templates = &override;
29b0f896 3170 }
252b5132 3171
29b0f896
AM		 3172 return l;
3173}
252b5132 3174
29b0f896 3175static char *
e3bb37b5 3176parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3177{
3178 char *token_start;
3138f287 3179
29b0f896
AM		 3180 /* 1 if operand is pending after ','. */
3181 unsigned int expecting_operand = 0;
252b5132 3182
29b0f896
AM		 3183 /* Non-zero if operand parens not balanced. */
3184 unsigned int paren_not_balanced;
3185
3186 while (*l != END_OF_INSN)
3187 {
3188 /* Skip optional white space before operand. */
3189 if (is_space_char (*l))
3190 ++l;
3191 if (!is_operand_char (*l) && *l != END_OF_INSN)
3192 {
3193 as_bad (_("invalid character %s before operand %d"),
3194 output_invalid (*l),
3195 i.operands + 1);
3196 return NULL;
3197 }
3198 token_start = l; /* after white space */
3199 paren_not_balanced = 0;
3200 while (paren_not_balanced || *l != ',')
3201 {
3202 if (*l == END_OF_INSN)
3203 {
3204 if (paren_not_balanced)
3205 {
3206 if (!intel_syntax)
3207 as_bad (_("unbalanced parenthesis in operand %d."),
3208 i.operands + 1);
3209 else
3210 as_bad (_("unbalanced brackets in operand %d."),
3211 i.operands + 1);
3212 return NULL;
3213 }
3214 else
3215 break; /* we are done */
3216 }
3217 else if (!is_operand_char (*l) && !is_space_char (*l))
3218 {
3219 as_bad (_("invalid character %s in operand %d"),
3220 output_invalid (*l),
3221 i.operands + 1);
3222 return NULL;
3223 }
3224 if (!intel_syntax)
3225 {
3226 if (*l == '(')
3227 ++paren_not_balanced;
3228 if (*l == ')')
3229 --paren_not_balanced;
3230 }
3231 else
3232 {
3233 if (*l == '[')
3234 ++paren_not_balanced;
3235 if (*l == ']')
3236 --paren_not_balanced;
3237 }
3238 l++;
3239 }
3240 if (l != token_start)
3241 { /* Yes, we've read in another operand. */
3242 unsigned int operand_ok;
3243 this_operand = i.operands++;
7d5e4556 3244 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3245 if (i.operands > MAX_OPERANDS)
3246 {
3247 as_bad (_("spurious operands; (%d operands/instruction max)"),
3248 MAX_OPERANDS);
3249 return NULL;
3250 }
3251 /* Now parse operand adding info to 'i' as we go along. */
3252 END_STRING_AND_SAVE (l);
3253
3254 if (intel_syntax)
3255 operand_ok =
3256 i386_intel_operand (token_start,
3257 intel_float_operand (mnemonic));
3258 else
a7619375 3259 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3260
3261 RESTORE_END_STRING (l);
3262 if (!operand_ok)
3263 return NULL;
3264 }
3265 else
3266 {
3267 if (expecting_operand)
3268 {
3269 expecting_operand_after_comma:
3270 as_bad (_("expecting operand after ','; got nothing"));
3271 return NULL;
3272 }
3273 if (*l == ',')
3274 {
3275 as_bad (_("expecting operand before ','; got nothing"));
3276 return NULL;
3277 }
3278 }
7f3f1ea2 3279
29b0f896
AM		 3280 /* Now *l must be either ',' or END_OF_INSN. */
3281 if (*l == ',')
3282 {
3283 if (*++l == END_OF_INSN)
3284 {
3285 /* Just skip it, if it's \n complain. */
3286 goto expecting_operand_after_comma;
3287 }
3288 expecting_operand = 1;
3289 }
3290 }
3291 return l;
3292}
7f3f1ea2 3293
050dfa73 3294static void
4d456e3d 3295swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3296{
3297 union i386_op temp_op;
40fb9820 3298 i386_operand_type temp_type;
050dfa73 3299 enum bfd_reloc_code_real temp_reloc;
4eed87de 3300
050dfa73
MM		 3301 temp_type = i.types[xchg2];
3302 i.types[xchg2] = i.types[xchg1];
3303 i.types[xchg1] = temp_type;
3304 temp_op = i.op[xchg2];
3305 i.op[xchg2] = i.op[xchg1];
3306 i.op[xchg1] = temp_op;
3307 temp_reloc = i.reloc[xchg2];
3308 i.reloc[xchg2] = i.reloc[xchg1];
3309 i.reloc[xchg1] = temp_reloc;
3310}
3311
29b0f896 3312static void
e3bb37b5 3313swap_operands (void)
29b0f896 3314{
b7c61d9a 3315 switch (i.operands)
050dfa73 3316 {
c0f3af97 3317 case 5:
b7c61d9a 3318 case 4:
4d456e3d 3319 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3320 case 3:
3321 case 2:
4d456e3d 3322 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3323 break;
3324 default:
3325 abort ();
29b0f896 3326 }
29b0f896
AM		 3327
3328 if (i.mem_operands == 2)
3329 {
3330 const seg_entry *temp_seg;
3331 temp_seg = i.seg[0];
3332 i.seg[0] = i.seg[1];
3333 i.seg[1] = temp_seg;
3334 }
3335}
252b5132 3336
29b0f896
AM		 3337/* Try to ensure constant immediates are represented in the smallest
3338 opcode possible. */
3339static void
e3bb37b5 3340optimize_imm (void)
29b0f896
AM		 3341{
3342 char guess_suffix = 0;
3343 int op;
252b5132 3344
29b0f896
AM		 3345 if (i.suffix)
3346 guess_suffix = i.suffix;
3347 else if (i.reg_operands)
3348 {
3349 /* Figure out a suffix from the last register operand specified.
3350 We can't do this properly yet, ie. excluding InOutPortReg,
3351 but the following works for instructions with immediates.
3352 In any case, we can't set i.suffix yet. */
3353 for (op = i.operands; --op >= 0;)
40fb9820
L		 3354 if (i.types[op].bitfield.reg8)
3355 {
3356 guess_suffix = BYTE_MNEM_SUFFIX;
3357 break;
3358 }
3359 else if (i.types[op].bitfield.reg16)
252b5132 3360 {
40fb9820
L		 3361 guess_suffix = WORD_MNEM_SUFFIX;
3362 break;
3363 }
3364 else if (i.types[op].bitfield.reg32)
3365 {
3366 guess_suffix = LONG_MNEM_SUFFIX;
3367 break;
3368 }
3369 else if (i.types[op].bitfield.reg64)
3370 {
3371 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3372 break;
252b5132 3373 }
29b0f896
AM		 3374 }
3375 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3376 guess_suffix = WORD_MNEM_SUFFIX;
3377
3378 for (op = i.operands; --op >= 0;)
40fb9820 3379 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3380 {
3381 switch (i.op[op].imms->X_op)
252b5132 3382 {
29b0f896
AM		 3383 case O_constant:
3384 /* If a suffix is given, this operand may be shortened. */
3385 switch (guess_suffix)
252b5132 3386 {
29b0f896 3387 case LONG_MNEM_SUFFIX:
40fb9820
L		 3388 i.types[op].bitfield.imm32 = 1;
3389 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3390 break;
3391 case WORD_MNEM_SUFFIX:
40fb9820
L		 3392 i.types[op].bitfield.imm16 = 1;
3393 i.types[op].bitfield.imm32 = 1;
3394 i.types[op].bitfield.imm32s = 1;
3395 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3396 break;
3397 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3398 i.types[op].bitfield.imm8 = 1;
3399 i.types[op].bitfield.imm8s = 1;
3400 i.types[op].bitfield.imm16 = 1;
3401 i.types[op].bitfield.imm32 = 1;
3402 i.types[op].bitfield.imm32s = 1;
3403 i.types[op].bitfield.imm64 = 1;
29b0f896 3404 break;
252b5132 3405 }
252b5132 3406
29b0f896
AM		 3407 /* If this operand is at most 16 bits, convert it
3408 to a signed 16 bit number before trying to see
3409 whether it will fit in an even smaller size.
3410 This allows a 16-bit operand such as $0xffe0 to
3411 be recognised as within Imm8S range. */
40fb9820 3412 if ((i.types[op].bitfield.imm16)
29b0f896 3413 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3414 {
29b0f896
AM		 3415 i.op[op].imms->X_add_number =
3416 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3417 }
40fb9820 3418 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3419 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3420 == 0))
3421 {
3422 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3423 ^ ((offsetT) 1 << 31))
3424 - ((offsetT) 1 << 31));
3425 }
40fb9820 3426 i.types[op]
c6fb90c8
L		 3427 = operand_type_or (i.types[op],
3428 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3429
29b0f896
AM		 3430 /* We must avoid matching of Imm32 templates when 64bit
3431 only immediate is available. */
3432 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3433 i.types[op].bitfield.imm32 = 0;
29b0f896 3434 break;
252b5132 3435
29b0f896
AM		 3436 case O_absent:
3437 case O_register:
3438 abort ();
3439
3440 /* Symbols and expressions. */
3441 default:
9cd96992
JB		 3442 /* Convert symbolic operand to proper sizes for matching, but don't
3443 prevent matching a set of insns that only supports sizes other
3444 than those matching the insn suffix. */
3445 {
40fb9820 3446 i386_operand_type mask, allowed;
9cd96992
JB		 3447 const template *t;
3448
0dfbf9d7
L		 3449 operand_type_set (&mask, 0);
3450 operand_type_set (&allowed, 0);
40fb9820 3451
4eed87de
AM		 3452 for (t = current_templates->start;
3453 t < current_templates->end;
3454 ++t)
c6fb90c8
L		 3455 allowed = operand_type_or (allowed,
3456 t->operand_types[op]);
9cd96992
JB		 3457 switch (guess_suffix)
3458 {
3459 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3460 mask.bitfield.imm64 = 1;
3461 mask.bitfield.imm32s = 1;
9cd96992
JB		 3462 break;
3463 case LONG_MNEM_SUFFIX:
40fb9820 3464 mask.bitfield.imm32 = 1;
9cd96992
JB		 3465 break;
3466 case WORD_MNEM_SUFFIX:
40fb9820 3467 mask.bitfield.imm16 = 1;
9cd96992
JB		 3468 break;
3469 case BYTE_MNEM_SUFFIX:
40fb9820 3470 mask.bitfield.imm8 = 1;
9cd96992
JB		 3471 break;
3472 default:
9cd96992
JB		 3473 break;
3474 }
c6fb90c8 3475 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3476 if (!operand_type_all_zero (&allowed))
c6fb90c8 3477 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3478 }
29b0f896 3479 break;
252b5132 3480 }
29b0f896
AM		 3481 }
3482}
47926f60 3483
29b0f896
AM		 3484/* Try to use the smallest displacement type too. */
3485static void
e3bb37b5 3486optimize_disp (void)
29b0f896
AM		 3487{
3488 int op;
3e73aa7c 3489
29b0f896 3490 for (op = i.operands; --op >= 0;)
40fb9820 3491 if (operand_type_check (i.types[op], disp))
252b5132 3492 {
b300c311 3493 if (i.op[op].disps->X_op == O_constant)
252b5132 3494 {
b300c311 3495 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3496
40fb9820 3497 if (i.types[op].bitfield.disp16
b300c311
L		 3498 && (disp & ~(offsetT) 0xffff) == 0)
3499 {
3500 /* If this operand is at most 16 bits, convert
3501 to a signed 16 bit number and don't use 64bit
3502 displacement. */
3503 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3504 i.types[op].bitfield.disp64 = 0;
b300c311 3505 }
40fb9820 3506 if (i.types[op].bitfield.disp32
b300c311
L		 3507 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3508 {
3509 /* If this operand is at most 32 bits, convert
3510 to a signed 32 bit number and don't use 64bit
3511 displacement. */
3512 disp &= (((offsetT) 2 << 31) - 1);
3513 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3514 i.types[op].bitfield.disp64 = 0;
b300c311 3515 }
40fb9820 3516 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3517 {
40fb9820
L		 3518 i.types[op].bitfield.disp8 = 0;
3519 i.types[op].bitfield.disp16 = 0;
3520 i.types[op].bitfield.disp32 = 0;
3521 i.types[op].bitfield.disp32s = 0;
3522 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3523 i.op[op].disps = 0;
3524 i.disp_operands--;
3525 }
3526 else if (flag_code == CODE_64BIT)
3527 {
3528 if (fits_in_signed_long (disp))
28a9d8f5 3529 {
40fb9820
L		 3530 i.types[op].bitfield.disp64 = 0;
3531 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3532 }
b300c311 3533 if (fits_in_unsigned_long (disp))
40fb9820 3534 i.types[op].bitfield.disp32 = 1;
b300c311 3535 }
40fb9820
L		 3536 if ((i.types[op].bitfield.disp32
3537 || i.types[op].bitfield.disp32s
3538 || i.types[op].bitfield.disp16)
b300c311 3539 && fits_in_signed_byte (disp))
40fb9820 3540 i.types[op].bitfield.disp8 = 1;
252b5132 3541 }
67a4f2b7
AO		 3542 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3543 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3544 {
3545 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3546 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3547 i.types[op].bitfield.disp8 = 0;
3548 i.types[op].bitfield.disp16 = 0;
3549 i.types[op].bitfield.disp32 = 0;
3550 i.types[op].bitfield.disp32s = 0;
3551 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3552 }
3553 else
b300c311 3554 /* We only support 64bit displacement on constants. */
40fb9820 3555 i.types[op].bitfield.disp64 = 0;
252b5132 3556 }
29b0f896
AM		 3557}
3558
c0f3af97
L		 3559/* Check if operands are valid for the instrucrtion. Update VEX
3560 operand types. */
3561
3562static int
3563VEX_check_operands (const template *t)
3564{
3565 if (!t->opcode_modifier.vex)
3566 return 0;
3567
3568 /* Only check VEX_Imm4, which must be the first operand. */
3569 if (t->operand_types[0].bitfield.vex_imm4)
3570 {
3571 if (i.op[0].imms->X_op != O_constant
3572 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3573 return 1;
3574
3575 /* Turn off Imm8 so that update_imm won't complain. */
3576 i.types[0] = vex_imm4;
3577 }
3578
3579 return 0;
3580}
3581
fa99fab2 3582static const template *
e3bb37b5 3583match_template (void)
29b0f896
AM		 3584{
3585 /* Points to template once we've found it. */
3586 const template *t;
40fb9820 3587 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3588 i386_operand_type overlap4;
29b0f896 3589 unsigned int found_reverse_match;
40fb9820
L		 3590 i386_opcode_modifier suffix_check;
3591 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3592 int addr_prefix_disp;
a5c311ca 3593 unsigned int j;
3629bb00 3594 unsigned int found_cpu_match;
45664ddb 3595 unsigned int check_register;
29b0f896 3596
c0f3af97
L		 3597#if MAX_OPERANDS != 5
3598# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3599#endif
3600
29b0f896 3601 found_reverse_match = 0;
539e75ad 3602 addr_prefix_disp = -1;
40fb9820
L		 3603
3604 memset (&suffix_check, 0, sizeof (suffix_check));
3605 if (i.suffix == BYTE_MNEM_SUFFIX)
3606 suffix_check.no_bsuf = 1;
3607 else if (i.suffix == WORD_MNEM_SUFFIX)
3608 suffix_check.no_wsuf = 1;
3609 else if (i.suffix == SHORT_MNEM_SUFFIX)
3610 suffix_check.no_ssuf = 1;
3611 else if (i.suffix == LONG_MNEM_SUFFIX)
3612 suffix_check.no_lsuf = 1;
3613 else if (i.suffix == QWORD_MNEM_SUFFIX)
3614 suffix_check.no_qsuf = 1;
3615 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3616 suffix_check.no_ldsuf = 1;
29b0f896 3617
45aa61fe 3618 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3619 {
539e75ad
L		 3620 addr_prefix_disp = -1;
3621
29b0f896
AM		 3622 /* Must have right number of operands. */
3623 if (i.operands != t->operands)
3624 continue;
3625
50aecf8c 3626 /* Check processor support. */
c0f3af97
L		 3627 found_cpu_match = (cpu_flags_match (t)
3628 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3629 if (!found_cpu_match)
3630 continue;
3631
e1d4d893
L		 3632 /* Check old gcc support. */
3633 if (!old_gcc && t->opcode_modifier.oldgcc)
3634 continue;
3635
3636 /* Check AT&T mnemonic. */
3637 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3638 continue;
3639
5c07affc
L		 3640 /* Check AT&T syntax Intel syntax. */
3641 if ((intel_syntax && t->opcode_modifier.attsyntax)
3642 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3643 continue;
3644
20592a94 3645 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3646 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3647 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3648 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3649 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3650 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3651 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3652 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3653 continue;
3654
5c07affc 3655 if (!operand_size_match (t))
7d5e4556 3656 continue;
539e75ad 3657
5c07affc
L		 3658 for (j = 0; j < MAX_OPERANDS; j++)
3659 operand_types[j] = t->operand_types[j];
3660
45aa61fe
AM		 3661 /* In general, don't allow 64-bit operands in 32-bit mode. */
3662 if (i.suffix == QWORD_MNEM_SUFFIX
3663 && flag_code != CODE_64BIT
3664 && (intel_syntax
40fb9820 3665 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3666 && !intel_float_operand (t->name))
3667 : intel_float_operand (t->name) != 2)
40fb9820 3668 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3669 && !operand_types[0].bitfield.regxmm
3670 && !operand_types[0].bitfield.regymm)
40fb9820 3671 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3672 && !!operand_types[t->operands > 1].bitfield.regxmm
3673 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3674 && (t->base_opcode != 0x0fc7
3675 || t->extension_opcode != 1 /* cmpxchg8b */))
3676 continue;
3677
192dc9c6
JB		 3678 /* In general, don't allow 32-bit operands on pre-386. */
3679 else if (i.suffix == LONG_MNEM_SUFFIX
3680 && !cpu_arch_flags.bitfield.cpui386
3681 && (intel_syntax
3682 ? (!t->opcode_modifier.ignoresize
3683 && !intel_float_operand (t->name))
3684 : intel_float_operand (t->name) != 2)
3685 && ((!operand_types[0].bitfield.regmmx
3686 && !operand_types[0].bitfield.regxmm)
3687 || (!operand_types[t->operands > 1].bitfield.regmmx
3688 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3689 continue;
3690
29b0f896 3691 /* Do not verify operands when there are none. */
50aecf8c 3692 else
29b0f896 3693 {
c6fb90c8 3694 if (!t->operands)
2dbab7d5
L		 3695 /* We've found a match; break out of loop. */
3696 break;
29b0f896 3697 }
252b5132 3698
539e75ad
L		 3699 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3700 into Disp32/Disp16/Disp32 operand. */
3701 if (i.prefix[ADDR_PREFIX] != 0)
3702 {
40fb9820 3703 /* There should be only one Disp operand. */
539e75ad
L		 3704 switch (flag_code)
3705 {
3706 case CODE_16BIT:
40fb9820
L		 3707 for (j = 0; j < MAX_OPERANDS; j++)
3708 {
3709 if (operand_types[j].bitfield.disp16)
3710 {
3711 addr_prefix_disp = j;
3712 operand_types[j].bitfield.disp32 = 1;
3713 operand_types[j].bitfield.disp16 = 0;
3714 break;
3715 }
3716 }
539e75ad
L		 3717 break;
3718 case CODE_32BIT:
40fb9820
L		 3719 for (j = 0; j < MAX_OPERANDS; j++)
3720 {
3721 if (operand_types[j].bitfield.disp32)
3722 {
3723 addr_prefix_disp = j;
3724 operand_types[j].bitfield.disp32 = 0;
3725 operand_types[j].bitfield.disp16 = 1;
3726 break;
3727 }
3728 }
539e75ad
L		 3729 break;
3730 case CODE_64BIT:
40fb9820
L		 3731 for (j = 0; j < MAX_OPERANDS; j++)
3732 {
3733 if (operand_types[j].bitfield.disp64)
3734 {
3735 addr_prefix_disp = j;
3736 operand_types[j].bitfield.disp64 = 0;
3737 operand_types[j].bitfield.disp32 = 1;
3738 break;
3739 }
3740 }
539e75ad
L		 3741 break;
3742 }
539e75ad
L		 3743 }
3744
45664ddb
L		 3745 /* We check register size only if size of operands can be
3746 encoded the canonical way. */
3747 check_register = t->opcode_modifier.w;
c6fb90c8 3748 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3749 switch (t->operands)
3750 {
3751 case 1:
40fb9820 3752 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3753 continue;
3754 break;
3755 case 2:
8b38ad71
L		 3756 /* xchg %eax, %eax is a special case. It is an aliase for nop
3757 only in 32bit mode and we can use opcode 0x90. In 64bit
3758 mode, we can't use 0x90 for xchg %eax, %eax since it should
3759 zero-extend %eax to %rax. */
3760 if (flag_code == CODE_64BIT
3761 && t->base_opcode == 0x90
0dfbf9d7
L		 3762 && operand_type_equal (&i.types [0], &acc32)
3763 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3764 continue;
b6169b20
L		 3765 if (i.swap_operand)
3766 {
3767 /* If we swap operand in encoding, we either match
3768 the next one or reverse direction of operands. */
3769 if (t->opcode_modifier.s)
3770 continue;
3771 else if (t->opcode_modifier.d)
3772 goto check_reverse;
3773 }
3774
29b0f896 3775 case 3:
fa99fab2
L		 3776 /* If we swap operand in encoding, we match the next one. */
3777 if (i.swap_operand && t->opcode_modifier.s)
3778 continue;
f48ff2ae 3779 case 4:
c0f3af97 3780 case 5:
c6fb90c8 3781 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3782 if (!operand_type_match (overlap0, i.types[0])
3783 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3784 || (check_register
3785 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3786 operand_types[0],
3787 overlap1, i.types[1],
3788 operand_types[1])))
29b0f896
AM		 3789 {
3790 /* Check if other direction is valid ... */
40fb9820 3791 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3792 continue;
3793
b6169b20 3794check_reverse:
29b0f896 3795 /* Try reversing direction of operands. */
c6fb90c8
L		 3796 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3797 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3798 if (!operand_type_match (overlap0, i.types[0])
3799 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3800 || (check_register
3801 && !operand_type_register_match (overlap0,
3802 i.types[0],
3803 operand_types[1],
3804 overlap1,
3805 i.types[1],
3806 operand_types[0])))
29b0f896
AM		 3807 {
3808 /* Does not match either direction. */
3809 continue;
3810 }
3811 /* found_reverse_match holds which of D or FloatDR
3812 we've found. */
40fb9820 3813 if (t->opcode_modifier.d)
8a2ed489 3814 found_reverse_match = Opcode_D;
40fb9820 3815 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3816 found_reverse_match = Opcode_FloatD;
3817 else
3818 found_reverse_match = 0;
40fb9820 3819 if (t->opcode_modifier.floatr)
8a2ed489 3820 found_reverse_match |= Opcode_FloatR;
29b0f896 3821 }
f48ff2ae 3822 else
29b0f896 3823 {
f48ff2ae 3824 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3825 switch (t->operands)
3826 {
c0f3af97
L		 3827 case 5:
3828 overlap4 = operand_type_and (i.types[4],
3829 operand_types[4]);
d1cbb4db 3830 case 4:
c6fb90c8
L		 3831 overlap3 = operand_type_and (i.types[3],
3832 operand_types[3]);
d1cbb4db 3833 case 3:
c6fb90c8
L		 3834 overlap2 = operand_type_and (i.types[2],
3835 operand_types[2]);
d1cbb4db
L		 3836 break;
3837 }
29b0f896 3838
f48ff2ae
L		 3839 switch (t->operands)
3840 {
c0f3af97
L		 3841 case 5:
3842 if (!operand_type_match (overlap4, i.types[4])
3843 || !operand_type_register_match (overlap3,
3844 i.types[3],
3845 operand_types[3],
3846 overlap4,
3847 i.types[4],
3848 operand_types[4]))
3849 continue;
f48ff2ae 3850 case 4:
40fb9820 3851 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3852 || (check_register
3853 && !operand_type_register_match (overlap2,
3854 i.types[2],
3855 operand_types[2],
3856 overlap3,
3857 i.types[3],
3858 operand_types[3])))
f48ff2ae
L		 3859 continue;
3860 case 3:
3861 /* Here we make use of the fact that there are no
3862 reverse match 3 operand instructions, and all 3
3863 operand instructions only need to be checked for
3864 register consistency between operands 2 and 3. */
40fb9820 3865 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3866 || (check_register
3867 && !operand_type_register_match (overlap1,
3868 i.types[1],
3869 operand_types[1],
3870 overlap2,
3871 i.types[2],
3872 operand_types[2])))
f48ff2ae
L		 3873 continue;
3874 break;
3875 }
29b0f896 3876 }
f48ff2ae 3877 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3878 slip through to break. */
3879 }
3629bb00 3880 if (!found_cpu_match)
29b0f896
AM		 3881 {
3882 found_reverse_match = 0;
3883 continue;
3884 }
c0f3af97
L		 3885
3886 /* Check if VEX operands are valid. */
3887 if (VEX_check_operands (t))
3888 continue;
3889
29b0f896
AM		 3890 /* We've found a match; break out of loop. */
3891 break;
3892 }
3893
3894 if (t == current_templates->end)
3895 {
3896 /* We found no match. */
95f283e8
L		 3897 if (intel_syntax)
3898 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3899 current_templates->start->name);
3900 else
3901 as_bad (_("suffix or operands invalid for `%s'"),
3902 current_templates->start->name);
fa99fab2 3903 return NULL;
29b0f896 3904 }
252b5132 3905
29b0f896
AM		 3906 if (!quiet_warnings)
3907 {
3908 if (!intel_syntax
40fb9820
L		 3909 && (i.types[0].bitfield.jumpabsolute
3910 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3911 {
3912 as_warn (_("indirect %s without `*'"), t->name);
3913 }
3914
40fb9820
L		 3915 if (t->opcode_modifier.isprefix
3916 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3917 {
3918 /* Warn them that a data or address size prefix doesn't
3919 affect assembly of the next line of code. */
3920 as_warn (_("stand-alone `%s' prefix"), t->name);
3921 }
3922 }
3923
3924 /* Copy the template we found. */
3925 i.tm = *t;
539e75ad
L		 3926
3927 if (addr_prefix_disp != -1)
3928 i.tm.operand_types[addr_prefix_disp]
3929 = operand_types[addr_prefix_disp];
3930
29b0f896
AM		 3931 if (found_reverse_match)
3932 {
3933 /* If we found a reverse match we must alter the opcode
3934 direction bit. found_reverse_match holds bits to change
3935 (different for int & float insns). */
3936
3937 i.tm.base_opcode ^= found_reverse_match;
3938
539e75ad
L		 3939 i.tm.operand_types[0] = operand_types[1];
3940 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3941 }
3942
fa99fab2 3943 return t;
29b0f896
AM		 3944}
3945
3946static int
e3bb37b5 3947check_string (void)
29b0f896 3948{
40fb9820
L		 3949 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3950 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3951 {
3952 if (i.seg[0] != NULL && i.seg[0] != &es)
3953 {
a87af027 3954 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3955 i.tm.name,
a87af027
JB		 3956 mem_op + 1,
3957 register_prefix);
29b0f896
AM		 3958 return 0;
3959 }
3960 /* There's only ever one segment override allowed per instruction.
3961 This instruction possibly has a legal segment override on the
3962 second operand, so copy the segment to where non-string
3963 instructions store it, allowing common code. */
3964 i.seg[0] = i.seg[1];
3965 }
40fb9820 3966 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3967 {
3968 if (i.seg[1] != NULL && i.seg[1] != &es)
3969 {
a87af027 3970 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3971 i.tm.name,
a87af027
JB		 3972 mem_op + 2,
3973 register_prefix);
29b0f896
AM		 3974 return 0;
3975 }
3976 }
3977 return 1;
3978}
3979
3980static int
543613e9 3981process_suffix (void)
29b0f896
AM		 3982{
3983 /* If matched instruction specifies an explicit instruction mnemonic
3984 suffix, use it. */
40fb9820
L		 3985 if (i.tm.opcode_modifier.size16)
3986 i.suffix = WORD_MNEM_SUFFIX;
3987 else if (i.tm.opcode_modifier.size32)
3988 i.suffix = LONG_MNEM_SUFFIX;
3989 else if (i.tm.opcode_modifier.size64)
3990 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3991 else if (i.reg_operands)
3992 {
3993 /* If there's no instruction mnemonic suffix we try to invent one
3994 based on register operands. */
3995 if (!i.suffix)
3996 {
3997 /* We take i.suffix from the last register operand specified,
3998 Destination register type is more significant than source
381d071f
L		 3999 register type. crc32 in SSE4.2 prefers source register
4000 type. */
4001 if (i.tm.base_opcode == 0xf20f38f1)
4002 {
40fb9820
L		 4003 if (i.types[0].bitfield.reg16)
4004 i.suffix = WORD_MNEM_SUFFIX;
4005 else if (i.types[0].bitfield.reg32)
4006 i.suffix = LONG_MNEM_SUFFIX;
4007 else if (i.types[0].bitfield.reg64)
4008 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4009 }
9344ff29 4010 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4011 {
40fb9820 4012 if (i.types[0].bitfield.reg8)
20592a94
L		 4013 i.suffix = BYTE_MNEM_SUFFIX;
4014 }
381d071f
L		 4015
4016 if (!i.suffix)
4017 {
4018 int op;
4019
20592a94
L		 4020 if (i.tm.base_opcode == 0xf20f38f1
4021 || i.tm.base_opcode == 0xf20f38f0)
4022 {
4023 /* We have to know the operand size for crc32. */
4024 as_bad (_("ambiguous memory operand size for `%s`"),
4025 i.tm.name);
4026 return 0;
4027 }
4028
381d071f 4029 for (op = i.operands; --op >= 0;)
40fb9820 4030 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4031 {
40fb9820
L		 4032 if (i.types[op].bitfield.reg8)
4033 {
4034 i.suffix = BYTE_MNEM_SUFFIX;
4035 break;
4036 }
4037 else if (i.types[op].bitfield.reg16)
4038 {
4039 i.suffix = WORD_MNEM_SUFFIX;
4040 break;
4041 }
4042 else if (i.types[op].bitfield.reg32)
4043 {
4044 i.suffix = LONG_MNEM_SUFFIX;
4045 break;
4046 }
4047 else if (i.types[op].bitfield.reg64)
4048 {
4049 i.suffix = QWORD_MNEM_SUFFIX;
4050 break;
4051 }
381d071f
L		 4052 }
4053 }
29b0f896
AM		 4054 }
4055 else if (i.suffix == BYTE_MNEM_SUFFIX)
4056 {
4057 if (!check_byte_reg ())
4058 return 0;
4059 }
4060 else if (i.suffix == LONG_MNEM_SUFFIX)
4061 {
4062 if (!check_long_reg ())
4063 return 0;
4064 }
4065 else if (i.suffix == QWORD_MNEM_SUFFIX)
4066 {
955e1e6a
L		 4067 if (intel_syntax
4068 && i.tm.opcode_modifier.ignoresize
4069 && i.tm.opcode_modifier.no_qsuf)
4070 i.suffix = 0;
4071 else if (!check_qword_reg ())
29b0f896
AM		 4072 return 0;
4073 }
4074 else if (i.suffix == WORD_MNEM_SUFFIX)
4075 {
4076 if (!check_word_reg ())
4077 return 0;
4078 }
c0f3af97
L		 4079 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4080 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4081 {
c0f3af97 4082 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4083 should check if it is a valid suffix. */
4084 }
40fb9820 4085 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4086 /* Do nothing if the instruction is going to ignore the prefix. */
4087 ;
4088 else
4089 abort ();
4090 }
40fb9820 4091 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4092 && !i.suffix
4093 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4094 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4095 {
4096 i.suffix = stackop_size;
4097 }
9306ca4a
JB		 4098 else if (intel_syntax
4099 && !i.suffix
40fb9820
L		 4100 && (i.tm.operand_types[0].bitfield.jumpabsolute
4101 || i.tm.opcode_modifier.jumpbyte
4102 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4103 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4104 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4105 {
4106 switch (flag_code)
4107 {
4108 case CODE_64BIT:
40fb9820 4109 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4110 {
4111 i.suffix = QWORD_MNEM_SUFFIX;
4112 break;
4113 }
4114 case CODE_32BIT:
40fb9820 4115 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4116 i.suffix = LONG_MNEM_SUFFIX;
4117 break;
4118 case CODE_16BIT:
40fb9820 4119 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4120 i.suffix = WORD_MNEM_SUFFIX;
4121 break;
4122 }
4123 }
252b5132 4124
9306ca4a 4125 if (!i.suffix)
29b0f896 4126 {
9306ca4a
JB		 4127 if (!intel_syntax)
4128 {
40fb9820 4129 if (i.tm.opcode_modifier.w)
9306ca4a 4130 {
4eed87de
AM		 4131 as_bad (_("no instruction mnemonic suffix given and "
4132 "no register operands; can't size instruction"));
9306ca4a
JB		 4133 return 0;
4134 }
4135 }
4136 else
4137 {
40fb9820
L		 4138 unsigned int suffixes;
4139
4140 suffixes = !i.tm.opcode_modifier.no_bsuf;
4141 if (!i.tm.opcode_modifier.no_wsuf)
4142 suffixes |= 1 << 1;
4143 if (!i.tm.opcode_modifier.no_lsuf)
4144 suffixes |= 1 << 2;
fc4adea1 4145 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4146 suffixes |= 1 << 3;
4147 if (!i.tm.opcode_modifier.no_ssuf)
4148 suffixes |= 1 << 4;
4149 if (!i.tm.opcode_modifier.no_qsuf)
4150 suffixes |= 1 << 5;
4151
4152 /* There are more than suffix matches. */
4153 if (i.tm.opcode_modifier.w
9306ca4a 4154 || ((suffixes & (suffixes - 1))
40fb9820
L		 4155 && !i.tm.opcode_modifier.defaultsize
4156 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4157 {
4158 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4159 return 0;
4160 }
4161 }
29b0f896 4162 }
252b5132 4163
9306ca4a
JB		 4164 /* Change the opcode based on the operand size given by i.suffix;
4165 We don't need to change things for byte insns. */
4166
582d5edd
L		 4167 if (i.suffix
4168 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4169 && i.suffix != XMMWORD_MNEM_SUFFIX
4170 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4171 {
4172 /* It's not a byte, select word/dword operation. */
40fb9820 4173 if (i.tm.opcode_modifier.w)
29b0f896 4174 {
40fb9820 4175 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4176 i.tm.base_opcode |= 8;
4177 else
4178 i.tm.base_opcode |= 1;
4179 }
0f3f3d8b 4180
29b0f896
AM		 4181 /* Now select between word & dword operations via the operand
4182 size prefix, except for instructions that will ignore this
4183 prefix anyway. */
ca61edf2 4184 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4185 {
ca61edf2
L		 4186 /* The address size override prefix changes the size of the
4187 first operand. */
40fb9820
L		 4188 if ((flag_code == CODE_32BIT
4189 && i.op->regs[0].reg_type.bitfield.reg16)
4190 || (flag_code != CODE_32BIT
4191 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4192 if (!add_prefix (ADDR_PREFIX_OPCODE))
4193 return 0;
4194 }
4195 else if (i.suffix != QWORD_MNEM_SUFFIX
4196 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4197 && !i.tm.opcode_modifier.ignoresize
4198 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4199 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4200 || (flag_code == CODE_64BIT
40fb9820 4201 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4202 {
4203 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4204
40fb9820 4205 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4206 prefix = ADDR_PREFIX_OPCODE;
252b5132 4207
29b0f896
AM		 4208 if (!add_prefix (prefix))
4209 return 0;
24eab124 4210 }
252b5132 4211
29b0f896
AM		 4212 /* Set mode64 for an operand. */
4213 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4214 && flag_code == CODE_64BIT
40fb9820 4215 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4216 {
4217 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4218 need rex64. cmpxchg8b is also a special case. */
4219 if (! (i.operands == 2
4220 && i.tm.base_opcode == 0x90
4221 && i.tm.extension_opcode == None
0dfbf9d7
L		 4222 && operand_type_equal (&i.types [0], &acc64)
4223 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4224 && ! (i.operands == 1
4225 && i.tm.base_opcode == 0xfc7
4226 && i.tm.extension_opcode == 1
40fb9820
L		 4227 && !operand_type_check (i.types [0], reg)
4228 && operand_type_check (i.types [0], anymem)))
f6bee062 4229 i.rex |= REX_W;
46e883c5 4230 }
3e73aa7c 4231
29b0f896
AM		 4232 /* Size floating point instruction. */
4233 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4234 if (i.tm.opcode_modifier.floatmf)
543613e9 4235 i.tm.base_opcode ^= 4;
29b0f896 4236 }
7ecd2f8b 4237
29b0f896
AM		 4238 return 1;
4239}
3e73aa7c 4240
29b0f896 4241static int
543613e9 4242check_byte_reg (void)
29b0f896
AM		 4243{
4244 int op;
543613e9 4245
29b0f896
AM		 4246 for (op = i.operands; --op >= 0;)
4247 {
4248 /* If this is an eight bit register, it's OK. If it's the 16 or
4249 32 bit version of an eight bit register, we will just use the
4250 low portion, and that's OK too. */
40fb9820 4251 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4252 continue;
4253
ca61edf2
L		 4254 /* Don't generate this warning if not needed. */
4255 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4256 continue;
4257
9344ff29
L		 4258 /* crc32 doesn't generate this warning. */
4259 if (i.tm.base_opcode == 0xf20f38f0)
4260 continue;
4261
40fb9820
L		 4262 if ((i.types[op].bitfield.reg16
4263 || i.types[op].bitfield.reg32
4264 || i.types[op].bitfield.reg64)
4265 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4266 {
4267 /* Prohibit these changes in the 64bit mode, since the
4268 lowering is more complicated. */
4269 if (flag_code == CODE_64BIT
40fb9820 4270 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4271 {
2ca3ace5
L		 4272 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4273 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4274 i.suffix);
4275 return 0;
4276 }
4277#if REGISTER_WARNINGS
4278 if (!quiet_warnings
40fb9820 4279 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4280 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4281 register_prefix,
40fb9820 4282 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4283 ? REGNAM_AL - REGNAM_AX
4284 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4285 register_prefix,
29b0f896
AM		 4286 i.op[op].regs->reg_name,
4287 i.suffix);
4288#endif
4289 continue;
4290 }
4291 /* Any other register is bad. */
40fb9820
L		 4292 if (i.types[op].bitfield.reg16
4293 || i.types[op].bitfield.reg32
4294 || i.types[op].bitfield.reg64
4295 || i.types[op].bitfield.regmmx
4296 || i.types[op].bitfield.regxmm
c0f3af97 4297 || i.types[op].bitfield.regymm
40fb9820
L		 4298 || i.types[op].bitfield.sreg2
4299 || i.types[op].bitfield.sreg3
4300 || i.types[op].bitfield.control
4301 || i.types[op].bitfield.debug
4302 || i.types[op].bitfield.test
4303 || i.types[op].bitfield.floatreg
4304 || i.types[op].bitfield.floatacc)
29b0f896 4305 {
a540244d
L		 4306 as_bad (_("`%s%s' not allowed with `%s%c'"),
4307 register_prefix,
29b0f896
AM		 4308 i.op[op].regs->reg_name,
4309 i.tm.name,
4310 i.suffix);
4311 return 0;
4312 }
4313 }
4314 return 1;
4315}
4316
4317static int
e3bb37b5 4318check_long_reg (void)
29b0f896
AM		 4319{
4320 int op;
4321
4322 for (op = i.operands; --op >= 0;)
4323 /* Reject eight bit registers, except where the template requires
4324 them. (eg. movzb) */
40fb9820
L		 4325 if (i.types[op].bitfield.reg8
4326 && (i.tm.operand_types[op].bitfield.reg16
4327 || i.tm.operand_types[op].bitfield.reg32
4328 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4329 {
a540244d
L		 4330 as_bad (_("`%s%s' not allowed with `%s%c'"),
4331 register_prefix,
29b0f896
AM		 4332 i.op[op].regs->reg_name,
4333 i.tm.name,
4334 i.suffix);
4335 return 0;
4336 }
4337 /* Warn if the e prefix on a general reg is missing. */
4338 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4339 && i.types[op].bitfield.reg16
4340 && (i.tm.operand_types[op].bitfield.reg32
4341 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4342 {
4343 /* Prohibit these changes in the 64bit mode, since the
4344 lowering is more complicated. */
4345 if (flag_code == CODE_64BIT)
252b5132 4346 {
2ca3ace5
L		 4347 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4348 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4349 i.suffix);
4350 return 0;
252b5132 4351 }
29b0f896
AM		 4352#if REGISTER_WARNINGS
4353 else
a540244d
L		 4354 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4355 register_prefix,
29b0f896 4356 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4357 register_prefix,
29b0f896
AM		 4358 i.op[op].regs->reg_name,
4359 i.suffix);
4360#endif
252b5132 4361 }
29b0f896 4362 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4363 else if (i.types[op].bitfield.reg64
4364 && (i.tm.operand_types[op].bitfield.reg32
4365 || i.tm.operand_types[op].bitfield.acc))
252b5132 4366 {
34828aad 4367 if (intel_syntax
ca61edf2 4368 && i.tm.opcode_modifier.toqword
40fb9820 4369 && !i.types[0].bitfield.regxmm)
34828aad 4370 {
ca61edf2 4371 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4372 i.suffix = QWORD_MNEM_SUFFIX;
4373 }
4374 else
4375 {
4376 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4377 register_prefix, i.op[op].regs->reg_name,
4378 i.suffix);
4379 return 0;
4380 }
29b0f896
AM		 4381 }
4382 return 1;
4383}
252b5132 4384
29b0f896 4385static int
e3bb37b5 4386check_qword_reg (void)
29b0f896
AM		 4387{
4388 int op;
252b5132 4389
29b0f896
AM		 4390 for (op = i.operands; --op >= 0; )
4391 /* Reject eight bit registers, except where the template requires
4392 them. (eg. movzb) */
40fb9820
L		 4393 if (i.types[op].bitfield.reg8
4394 && (i.tm.operand_types[op].bitfield.reg16
4395 || i.tm.operand_types[op].bitfield.reg32
4396 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4397 {
a540244d
L		 4398 as_bad (_("`%s%s' not allowed with `%s%c'"),
4399 register_prefix,
29b0f896
AM		 4400 i.op[op].regs->reg_name,
4401 i.tm.name,
4402 i.suffix);
4403 return 0;
4404 }
4405 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4406 else if ((i.types[op].bitfield.reg16
4407 || i.types[op].bitfield.reg32)
4408 && (i.tm.operand_types[op].bitfield.reg32
4409 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4410 {
4411 /* Prohibit these changes in the 64bit mode, since the
4412 lowering is more complicated. */
34828aad 4413 if (intel_syntax
ca61edf2 4414 && i.tm.opcode_modifier.todword
40fb9820 4415 && !i.types[0].bitfield.regxmm)
34828aad 4416 {
ca61edf2 4417 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4418 i.suffix = LONG_MNEM_SUFFIX;
4419 }
4420 else
4421 {
4422 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4423 register_prefix, i.op[op].regs->reg_name,
4424 i.suffix);
4425 return 0;
4426 }
252b5132 4427 }
29b0f896
AM		 4428 return 1;
4429}
252b5132 4430
29b0f896 4431static int
e3bb37b5 4432check_word_reg (void)
29b0f896
AM		 4433{
4434 int op;
4435 for (op = i.operands; --op >= 0;)
4436 /* Reject eight bit registers, except where the template requires
4437 them. (eg. movzb) */
40fb9820
L		 4438 if (i.types[op].bitfield.reg8
4439 && (i.tm.operand_types[op].bitfield.reg16
4440 || i.tm.operand_types[op].bitfield.reg32
4441 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4442 {
a540244d
L		 4443 as_bad (_("`%s%s' not allowed with `%s%c'"),
4444 register_prefix,
29b0f896
AM		 4445 i.op[op].regs->reg_name,
4446 i.tm.name,
4447 i.suffix);
4448 return 0;
4449 }
4450 /* Warn if the e prefix on a general reg is present. */
4451 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4452 && i.types[op].bitfield.reg32
4453 && (i.tm.operand_types[op].bitfield.reg16
4454 || i.tm.operand_types[op].bitfield.acc))
252b5132 4455 {
29b0f896
AM		 4456 /* Prohibit these changes in the 64bit mode, since the
4457 lowering is more complicated. */
4458 if (flag_code == CODE_64BIT)
252b5132 4459 {
2ca3ace5
L		 4460 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4461 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4462 i.suffix);
4463 return 0;
252b5132 4464 }
29b0f896
AM		 4465 else
4466#if REGISTER_WARNINGS
a540244d
L		 4467 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4468 register_prefix,
29b0f896 4469 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4470 register_prefix,
29b0f896
AM		 4471 i.op[op].regs->reg_name,
4472 i.suffix);
4473#endif
4474 }
4475 return 1;
4476}
252b5132 4477
29b0f896 4478static int
40fb9820 4479update_imm (unsigned int j)
29b0f896 4480{
40fb9820
L		 4481 i386_operand_type overlap;
4482
c6fb90c8 4483 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4484 if ((overlap.bitfield.imm8
4485 || overlap.bitfield.imm8s
4486 || overlap.bitfield.imm16
4487 || overlap.bitfield.imm32
4488 || overlap.bitfield.imm32s
4489 || overlap.bitfield.imm64)
0dfbf9d7
L		 4490 && !operand_type_equal (&overlap, &imm8)
4491 && !operand_type_equal (&overlap, &imm8s)
4492 && !operand_type_equal (&overlap, &imm16)
4493 && !operand_type_equal (&overlap, &imm32)
4494 && !operand_type_equal (&overlap, &imm32s)
4495 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4496 {
4497 if (i.suffix)
4498 {
40fb9820
L		 4499 i386_operand_type temp;
4500
0dfbf9d7 4501 operand_type_set (&temp, 0);
40fb9820
L		 4502 if (i.suffix == BYTE_MNEM_SUFFIX)
4503 {
4504 temp.bitfield.imm8 = overlap.bitfield.imm8;
4505 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4506 }
4507 else if (i.suffix == WORD_MNEM_SUFFIX)
4508 temp.bitfield.imm16 = overlap.bitfield.imm16;
4509 else if (i.suffix == QWORD_MNEM_SUFFIX)
4510 {
4511 temp.bitfield.imm64 = overlap.bitfield.imm64;
4512 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4513 }
4514 else
4515 temp.bitfield.imm32 = overlap.bitfield.imm32;
4516 overlap = temp;
29b0f896 4517 }
0dfbf9d7
L		 4518 else if (operand_type_equal (&overlap, &imm16_32_32s)
4519 || operand_type_equal (&overlap, &imm16_32)
4520 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4521 {
40fb9820 4522 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4523 overlap = imm16;
40fb9820 4524 else
65da13b5 4525 overlap = imm32s;
29b0f896 4526 }
0dfbf9d7
L		 4527 if (!operand_type_equal (&overlap, &imm8)
4528 && !operand_type_equal (&overlap, &imm8s)
4529 && !operand_type_equal (&overlap, &imm16)
4530 && !operand_type_equal (&overlap, &imm32)
4531 && !operand_type_equal (&overlap, &imm32s)
4532 && !operand_type_equal (&overlap, &imm64))
29b0f896 4533 {
4eed87de
AM		 4534 as_bad (_("no instruction mnemonic suffix given; "
4535 "can't determine immediate size"));
29b0f896
AM		 4536 return 0;
4537 }
4538 }
40fb9820 4539 i.types[j] = overlap;
29b0f896 4540
40fb9820
L		 4541 return 1;
4542}
4543
4544static int
4545finalize_imm (void)
4546{
4547 unsigned int j;
29b0f896 4548
40fb9820
L		 4549 for (j = 0; j < 2; j++)
4550 if (update_imm (j) == 0)
4551 return 0;
4552
c6fb90c8 4553 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4554 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4555
4556 return 1;
4557}
4558
85f10a01
MM		 4559static void
4560process_drex (void)
4561{
5dd15031
JJ		 4562 i.drex.modrm_reg = 0;
4563 i.drex.modrm_regmem = 0;
85f10a01
MM		 4564
4565 /* SSE5 4 operand instructions must have the destination the same as
4566 one of the inputs. Figure out the destination register and cache
4567 it away in the drex field, and remember which fields to use for
4568 the modrm byte. */
4569 if (i.tm.opcode_modifier.drex
4570 && i.tm.opcode_modifier.drexv
4571 && i.operands == 4)
4572 {
4573 i.tm.extension_opcode = None;
4574
4575 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4576 if (i.types[0].bitfield.regxmm != 0
4577 && i.types[1].bitfield.regxmm != 0
4578 && i.types[2].bitfield.regxmm != 0
4579 && i.types[3].bitfield.regxmm != 0
4580 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4581 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4582 {
4583 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4584 operand_type_set (&i.types[0], 0);
4585 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4586 i.reg_operands -= 2;
4587
4588 /* There are two different ways to encode a 4 operand
4589 instruction with all registers that uses OC1 set to
4590 0 or 1. Favor setting OC1 to 0 since this mimics the
4591 actions of other SSE5 assemblers. Use modrm encoding 2
4592 for register/register. Include the high order bit that
4593 is normally stored in the REX byte in the register
4594 field. */
4595 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4596 i.drex.modrm_reg = 2;
4597 i.drex.modrm_regmem = 1;
4598 i.drex.reg = (i.op[3].regs->reg_num
4599 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4600 }
4601
4602 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4603 else if (i.types[0].bitfield.regxmm != 0
4604 && i.types[1].bitfield.regxmm != 0
4605 && (i.types[2].bitfield.regxmm
4606 || operand_type_check (i.types[2], anymem))
4607 && i.types[3].bitfield.regxmm != 0
4608 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4609 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4610 {
4611 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4612 operand_type_set (&i.types[0], 0);
4613 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4614 i.reg_operands -= 2;
4615
4616 /* Specify the modrm encoding for memory addressing. Include
4617 the high order bit that is normally stored in the REX byte
4618 in the register field. */
4619 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4620 i.drex.modrm_reg = 1;
4621 i.drex.modrm_regmem = 2;
4622 i.drex.reg = (i.op[3].regs->reg_num
4623 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4624 }
4625
4626 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4627 else if (i.types[0].bitfield.regxmm != 0
4628 && operand_type_check (i.types[1], anymem) != 0
4629 && i.types[2].bitfield.regxmm != 0
4630 && i.types[3].bitfield.regxmm != 0
4631 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4632 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4633 {
4634 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4635 operand_type_set (&i.types[0], 0);
4636 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4637 i.reg_operands -= 2;
4638
4639 /* Specify the modrm encoding for memory addressing. Include
4640 the high order bit that is normally stored in the REX byte
4641 in the register field. */
4642 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4643 i.drex.modrm_reg = 2;
4644 i.drex.modrm_regmem = 1;
4645 i.drex.reg = (i.op[3].regs->reg_num
4646 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4647 }
4648
4649 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4650 else if (i.types[0].bitfield.regxmm != 0
4651 && i.types[1].bitfield.regxmm != 0
4652 && i.types[2].bitfield.regxmm != 0
4653 && i.types[3].bitfield.regxmm != 0
4654 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4655 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4656 {
4657 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4658 operand_type_set (&i.types[2], 0);
4659 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4660 i.reg_operands -= 2;
4661
4662 /* There are two different ways to encode a 4 operand
4663 instruction with all registers that uses OC1 set to
4664 0 or 1. Favor setting OC1 to 0 since this mimics the
4665 actions of other SSE5 assemblers. Use modrm encoding
4666 2 for register/register. Include the high order bit that
4667 is normally stored in the REX byte in the register
4668 field. */
4669 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4670 i.drex.modrm_reg = 1;
4671 i.drex.modrm_regmem = 0;
4672
4673 /* Remember the register, including the upper bits */
4674 i.drex.reg = (i.op[3].regs->reg_num
4675 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4676 }
4677
4678 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4679 else if (i.types[0].bitfield.regxmm != 0
4680 && (i.types[1].bitfield.regxmm
4681 || operand_type_check (i.types[1], anymem))
4682 && i.types[2].bitfield.regxmm != 0
4683 && i.types[3].bitfield.regxmm != 0
4684 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4685 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4686 {
4687 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4688 operand_type_set (&i.types[2], 0);
4689 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4690 i.reg_operands -= 2;
4691
4692 /* Specify the modrm encoding and remember the register
4693 including the bits normally stored in the REX byte. */
4694 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4695 i.drex.modrm_reg = 0;
4696 i.drex.modrm_regmem = 1;
4697 i.drex.reg = (i.op[3].regs->reg_num
4698 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4699 }
4700
4701 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4702 else if (operand_type_check (i.types[0], anymem) != 0
4703 && i.types[1].bitfield.regxmm != 0
4704 && i.types[2].bitfield.regxmm != 0
4705 && i.types[3].bitfield.regxmm != 0
4706 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4707 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4708 {
4709 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4710 operand_type_set (&i.types[2], 0);
4711 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4712 i.reg_operands -= 2;
4713
4714 /* Specify the modrm encoding and remember the register
4715 including the bits normally stored in the REX byte. */
4716 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4717 i.drex.modrm_reg = 1;
4718 i.drex.modrm_regmem = 0;
4719 i.drex.reg = (i.op[3].regs->reg_num
4720 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4721 }
4722
4723 else
4724 as_bad (_("Incorrect operands for the '%s' instruction"),
4725 i.tm.name);
4726 }
4727
4728 /* SSE5 instructions with the DREX byte where the only memory operand
4729 is in the 2nd argument, and the first and last xmm register must
4730 match, and is encoded in the DREX byte. */
4731 else if (i.tm.opcode_modifier.drex
4732 && !i.tm.opcode_modifier.drexv
4733 && i.operands == 4)
4734 {
4735 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4736 if (i.types[0].bitfield.regxmm != 0
4737 && (i.types[1].bitfield.regxmm
4738 || operand_type_check(i.types[1], anymem))
4739 && i.types[2].bitfield.regxmm != 0
4740 && i.types[3].bitfield.regxmm != 0
4741 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4742 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4743 {
4744 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4745 operand_type_set (&i.types[0], 0);
4746 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4747 i.reg_operands -= 2;
4748
4749 /* Specify the modrm encoding and remember the register
4750 including the high bit normally stored in the REX
4751 byte. */
4752 i.drex.modrm_reg = 2;
4753 i.drex.modrm_regmem = 1;
4754 i.drex.reg = (i.op[3].regs->reg_num
4755 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4756 }
4757
4758 else
4759 as_bad (_("Incorrect operands for the '%s' instruction"),
4760 i.tm.name);
4761 }
4762
4763 /* SSE5 3 operand instructions that the result is a register, being
4764 either operand can be a memory operand, using OC0 to note which
4765 one is the memory. */
4766 else if (i.tm.opcode_modifier.drex
4767 && i.tm.opcode_modifier.drexv
4768 && i.operands == 3)
4769 {
4770 i.tm.extension_opcode = None;
4771
4772 /* Case 1: 3 operand insn, src1 = register. */
4773 if (i.types[0].bitfield.regxmm != 0
4774 && i.types[1].bitfield.regxmm != 0
4775 && i.types[2].bitfield.regxmm != 0)
4776 {
4777 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4778 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4779 i.reg_operands--;
4780
4781 /* Specify the modrm encoding and remember the register
4782 including the high bit normally stored in the REX byte. */
4783 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4784 i.drex.modrm_reg = 1;
4785 i.drex.modrm_regmem = 0;
4786 i.drex.reg = (i.op[2].regs->reg_num
4787 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4788 }
4789
4790 /* Case 2: 3 operand insn, src1 = memory. */
4791 else if (operand_type_check (i.types[0], anymem) != 0
4792 && i.types[1].bitfield.regxmm != 0
4793 && i.types[2].bitfield.regxmm != 0)
4794 {
4795 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4796 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4797 i.reg_operands--;
4798
4799 /* Specify the modrm encoding and remember the register
4800 including the high bit normally stored in the REX
4801 byte. */
4802 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4803 i.drex.modrm_reg = 1;
4804 i.drex.modrm_regmem = 0;
4805 i.drex.reg = (i.op[2].regs->reg_num
4806 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4807 }
4808
4809 /* Case 3: 3 operand insn, src2 = memory. */
4810 else if (i.types[0].bitfield.regxmm != 0
4811 && operand_type_check (i.types[1], anymem) != 0
4812 && i.types[2].bitfield.regxmm != 0)
4813 {
4814 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4815 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4816 i.reg_operands--;
4817
4818 /* Specify the modrm encoding and remember the register
4819 including the high bit normally stored in the REX byte. */
4820 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4821 i.drex.modrm_reg = 0;
4822 i.drex.modrm_regmem = 1;
4823 i.drex.reg = (i.op[2].regs->reg_num
4824 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4825 }
4826
4827 else
4828 as_bad (_("Incorrect operands for the '%s' instruction"),
4829 i.tm.name);
4830 }
4831
4832 /* SSE5 4 operand instructions that are the comparison instructions
4833 where the first operand is the immediate value of the comparison
4834 to be done. */
4835 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4836 {
4837 /* Case 1: 4 operand insn, src1 = reg/memory. */
4838 if (operand_type_check (i.types[0], imm) != 0
4839 && (i.types[1].bitfield.regxmm
4840 || operand_type_check (i.types[1], anymem))
4841 && i.types[2].bitfield.regxmm != 0
4842 && i.types[3].bitfield.regxmm != 0)
4843 {
4844 /* clear the arguments that are stored in drex */
0dfbf9d7 4845 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4846 i.reg_operands--;
4847
4848 /* Specify the modrm encoding and remember the register
4849 including the high bit normally stored in the REX byte. */
4850 i.drex.modrm_reg = 2;
4851 i.drex.modrm_regmem = 1;
4852 i.drex.reg = (i.op[3].regs->reg_num
4853 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4854 }
4855
4856 /* Case 2: 3 operand insn with ImmExt that places the
4857 opcode_extension as an immediate argument. This is used for
4858 all of the varients of comparison that supplies the appropriate
4859 value as part of the instruction. */
4860 else if ((i.types[0].bitfield.regxmm
4861 || operand_type_check (i.types[0], anymem))
4862 && i.types[1].bitfield.regxmm != 0
4863 && i.types[2].bitfield.regxmm != 0
4864 && operand_type_check (i.types[3], imm) != 0)
4865 {
4866 /* clear the arguments that are stored in drex */
0dfbf9d7 4867 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4868 i.reg_operands--;
4869
4870 /* Specify the modrm encoding and remember the register
4871 including the high bit normally stored in the REX byte. */
4872 i.drex.modrm_reg = 1;
4873 i.drex.modrm_regmem = 0;
4874 i.drex.reg = (i.op[2].regs->reg_num
4875 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4876 }
4877
4878 else
4879 as_bad (_("Incorrect operands for the '%s' instruction"),
4880 i.tm.name);
4881 }
4882
4883 else if (i.tm.opcode_modifier.drex
4884 || i.tm.opcode_modifier.drexv
4885 || i.tm.opcode_modifier.drexc)
4886 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4887}
4888
c0f3af97
L		 4889static int
4890bad_implicit_operand (int xmm)
4891{
4892 const char *reg = xmm ? "xmm0" : "ymm0";
4893 if (intel_syntax)
4894 as_bad (_("the last operand of `%s' must be `%s%s'"),
4895 i.tm.name, register_prefix, reg);
4896 else
4897 as_bad (_("the first operand of `%s' must be `%s%s'"),
4898 i.tm.name, register_prefix, reg);
4899 return 0;
4900}
4901
29b0f896 4902static int
e3bb37b5 4903process_operands (void)
29b0f896
AM		 4904{
4905 /* Default segment register this instruction will use for memory
4906 accesses. 0 means unknown. This is only for optimizing out
4907 unnecessary segment overrides. */
4908 const seg_entry *default_seg = 0;
4909
85f10a01
MM		 4910 /* Handle all of the DREX munging that SSE5 needs. */
4911 if (i.tm.opcode_modifier.drex
4912 || i.tm.opcode_modifier.drexv
4913 || i.tm.opcode_modifier.drexc)
4914 process_drex ();
4915
c0f3af97
L		 4916 if (i.tm.opcode_modifier.sse2avx
4917 && (i.tm.opcode_modifier.vexnds
4918 || i.tm.opcode_modifier.vexndd))
29b0f896 4919 {
c0f3af97
L		 4920 unsigned int dup = i.operands;
4921 unsigned int dest = dup - 1;
9fcfb3d7
L		 4922 unsigned int j;
4923
c0f3af97 4924 /* The destination must be an xmm register. */
0dfbf9d7 4925 assert (i.reg_operands
c0f3af97
L		 4926 && MAX_OPERANDS > dup
4927 && operand_type_equal (&i.types[dest], &regxmm));
4928
4929 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4930 {
c0f3af97
L		 4931 /* The first operand is implicit and must be xmm0. */
4932 assert (operand_type_equal (&i.types[0], &regxmm));
4933 if (i.op[0].regs->reg_num != 0)
4934 return bad_implicit_operand (1);
4935
4936 if (i.tm.opcode_modifier.vex3sources)
4937 {
4938 /* Keep xmm0 for instructions with VEX prefix and 3
4939 sources. */
4940 goto duplicate;
4941 }
e2ec9d29 4942 else
c0f3af97
L		 4943 {
4944 /* We remove the first xmm0 and keep the number of
4945 operands unchanged, which in fact duplicates the
4946 destination. */
4947 for (j = 1; j < i.operands; j++)
4948 {
4949 i.op[j - 1] = i.op[j];
4950 i.types[j - 1] = i.types[j];
4951 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4952 }
4953 }
4954 }
4955 else if (i.tm.opcode_modifier.implicit1stxmm0)
4956 {
4957 assert ((MAX_OPERANDS - 1) > dup
4958 && i.tm.opcode_modifier.vex3sources);
4959
4960 /* Add the implicit xmm0 for instructions with VEX prefix
4961 and 3 sources. */
4962 for (j = i.operands; j > 0; j--)
4963 {
4964 i.op[j] = i.op[j - 1];
4965 i.types[j] = i.types[j - 1];
4966 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4967 }
4968 i.op[0].regs
4969 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4970 i.types[0] = regxmm;
4971 i.tm.operand_types[0] = regxmm;
4972
4973 i.operands += 2;
4974 i.reg_operands += 2;
4975 i.tm.operands += 2;
4976
4977 dup++;
4978 dest++;
4979 i.op[dup] = i.op[dest];
4980 i.types[dup] = i.types[dest];
4981 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4982 }
c0f3af97
L		 4983 else
4984 {
4985duplicate:
4986 i.operands++;
4987 i.reg_operands++;
4988 i.tm.operands++;
4989
4990 i.op[dup] = i.op[dest];
4991 i.types[dup] = i.types[dest];
4992 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4993 }
4994
4995 if (i.tm.opcode_modifier.immext)
4996 process_immext ();
4997 }
4998 else if (i.tm.opcode_modifier.firstxmm0)
4999 {
5000 unsigned int j;
5001
5002 /* The first operand is implicit and must be xmm0/ymm0. */
5003 assert (i.reg_operands
5004 && (operand_type_equal (&i.types[0], &regxmm)
5005 || operand_type_equal (&i.types[0], &regymm)));
5006 if (i.op[0].regs->reg_num != 0)
5007 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5008
5009 for (j = 1; j < i.operands; j++)
5010 {
5011 i.op[j - 1] = i.op[j];
5012 i.types[j - 1] = i.types[j];
5013
5014 /* We need to adjust fields in i.tm since they are used by
5015 build_modrm_byte. */
5016 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5017 }
5018
e2ec9d29
L		 5019 i.operands--;
5020 i.reg_operands--;
e2ec9d29
L		 5021 i.tm.operands--;
5022 }
5023 else if (i.tm.opcode_modifier.regkludge)
5024 {
5025 /* The imul $imm, %reg instruction is converted into
5026 imul $imm, %reg, %reg, and the clr %reg instruction
5027 is converted into xor %reg, %reg. */
5028
5029 unsigned int first_reg_op;
5030
5031 if (operand_type_check (i.types[0], reg))
5032 first_reg_op = 0;
5033 else
5034 first_reg_op = 1;
5035 /* Pretend we saw the extra register operand. */
5036 assert (i.reg_operands == 1
5037 && i.op[first_reg_op + 1].regs == 0);
5038 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5039 i.types[first_reg_op + 1] = i.types[first_reg_op];
5040 i.operands++;
5041 i.reg_operands++;
29b0f896
AM		 5042 }
5043
40fb9820 5044 if (i.tm.opcode_modifier.shortform)
29b0f896 5045 {
40fb9820
L		 5046 if (i.types[0].bitfield.sreg2
5047 || i.types[0].bitfield.sreg3)
29b0f896 5048 {
4eed87de
AM		 5049 if (i.tm.base_opcode == POP_SEG_SHORT
5050 && i.op[0].regs->reg_num == 1)
29b0f896 5051 {
a87af027 5052 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5053 return 0;
29b0f896 5054 }
4eed87de
AM		 5055 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5056 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5057 i.rex |= REX_B;
4eed87de
AM		 5058 }
5059 else
5060 {
85f10a01
MM		 5061 /* The register or float register operand is in operand
5062 0 or 1. */
40fb9820
L		 5063 unsigned int op;
5064
5065 if (i.types[0].bitfield.floatreg
5066 || operand_type_check (i.types[0], reg))
5067 op = 0;
5068 else
5069 op = 1;
4eed87de
AM		 5070 /* Register goes in low 3 bits of opcode. */
5071 i.tm.base_opcode |= i.op[op].regs->reg_num;
5072 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5073 i.rex |= REX_B;
40fb9820 5074 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5075 {
4eed87de
AM		 5076 /* Warn about some common errors, but press on regardless.
5077 The first case can be generated by gcc (<= 2.8.1). */
5078 if (i.operands == 2)
5079 {
5080 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 5081 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5082 register_prefix, i.op[1].regs->reg_name,
5083 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 5084 }
5085 else
5086 {
5087 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5088 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5089 register_prefix, i.op[0].regs->reg_name);
4eed87de 5090 }
29b0f896
AM		 5091 }
5092 }
5093 }
40fb9820 5094 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5095 {
5096 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5097 must be put into the modrm byte). Now, we make the modrm and
5098 index base bytes based on all the info we've collected. */
29b0f896
AM		 5099
5100 default_seg = build_modrm_byte ();
5101 }
8a2ed489 5102 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5103 {
5104 default_seg = &ds;
5105 }
40fb9820 5106 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5107 {
5108 /* For the string instructions that allow a segment override
5109 on one of their operands, the default segment is ds. */
5110 default_seg = &ds;
5111 }
5112
75178d9d
L		 5113 if (i.tm.base_opcode == 0x8d /* lea */
5114 && i.seg[0]
5115 && !quiet_warnings)
30123838 5116 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5117
5118 /* If a segment was explicitly specified, and the specified segment
5119 is not the default, use an opcode prefix to select it. If we
5120 never figured out what the default segment is, then default_seg
5121 will be zero at this point, and the specified segment prefix will
5122 always be used. */
29b0f896
AM		 5123 if ((i.seg[0]) && (i.seg[0] != default_seg))
5124 {
5125 if (!add_prefix (i.seg[0]->seg_prefix))
5126 return 0;
5127 }
5128 return 1;
5129}
5130
5131static const seg_entry *
e3bb37b5 5132build_modrm_byte (void)
29b0f896
AM		 5133{
5134 const seg_entry *default_seg = 0;
c0f3af97
L		 5135 unsigned int source, dest;
5136 int vex_3_sources;
5137
5138 /* The first operand of instructions with VEX prefix and 3 sources
5139 must be VEX_Imm4. */
5140 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5141 if (vex_3_sources)
5142 {
5143 unsigned int nds, reg;
5144
0bfee649 5145 dest = i.operands - 1;
c0f3af97 5146 nds = dest - 1;
0bfee649
L		 5147 source = 1;
5148 reg = 0;
5149
5150 /* This instruction must have 4 operands: 4 register operands
5151 or 3 register operands plus 1 memory operand. It must have
5152 VexNDS and VexImmExt. */
5153 assert (i.operands == 4
5154 && (i.reg_operands == 4
5155 || (i.reg_operands == 3 && i.mem_operands == 1))
5156 && i.tm.opcode_modifier.vexnds
5157 && i.tm.opcode_modifier.veximmext
5158 && (operand_type_equal (&i.tm.operand_types[dest],
5159 &regxmm)
5160 || operand_type_equal (&i.tm.operand_types[dest],
5161 &regymm))
5162 && (operand_type_equal (&i.tm.operand_types[nds],
5163 &regxmm)
5164 || operand_type_equal (&i.tm.operand_types[nds],
5165 &regymm))
5166 && (operand_type_equal (&i.tm.operand_types[reg],
5167 &regxmm)
c0f3af97 5168 || operand_type_equal (&i.tm.operand_types[reg],
0bfee649 5169 &regymm)));
c0f3af97 5170
0bfee649
L		 5171 /* Generate an 8bit immediate operand to encode the register
5172 operand. */
5173 expressionS *exp = &im_expressions[i.imm_operands++];
5174 i.op[i.operands].imms = exp;
5175 i.types[i.operands] = imm8;
5176 i.operands++;
5177 exp->X_op = O_constant;
5178 exp->X_add_number
5179 = ((i.op[0].regs->reg_num
5180 + ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 5181
dae39acc 5182 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5183 }
5184 else
5185 source = dest = 0;
29b0f896 5186
85f10a01
MM		 5187 /* SSE5 4 operand instructions are encoded in such a way that one of
5188 the inputs must match the destination register. Process_drex hides
5189 the 3rd argument in the drex field, so that by the time we get
5190 here, it looks to GAS as if this is a 2 operand instruction. */
5191 if ((i.tm.opcode_modifier.drex
5192 || i.tm.opcode_modifier.drexv
b5016f89 5193 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5194 && i.reg_operands == 2)
5195 {
5196 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5197 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5198
5199 i.rm.reg = reg->reg_num;
5200 i.rm.regmem = regmem->reg_num;
5201 i.rm.mode = 3;
5202 if ((reg->reg_flags & RegRex) != 0)
5203 i.rex |= REX_R;
5204 if ((regmem->reg_flags & RegRex) != 0)
5205 i.rex |= REX_B;
5206 }
5207
29b0f896 5208 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5209 implicit registers do not count. If there are 3 register
5210 operands, it must be a instruction with VexNDS. For a
5211 instruction with VexNDD, the destination register is encoded
5212 in VEX prefix. If there are 4 register operands, it must be
5213 a instruction with VEX prefix and 3 sources. */
5214 else if (i.mem_operands == 0
5215 && ((i.reg_operands == 2
5216 && !i.tm.opcode_modifier.vexndd)
5217 || (i.reg_operands == 3
5218 && i.tm.opcode_modifier.vexnds)
5219 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5220 {
cab737b9
L		 5221 switch (i.operands)
5222 {
5223 case 2:
5224 source = 0;
5225 break;
5226 case 3:
c81128dc
L		 5227 /* When there are 3 operands, one of them may be immediate,
5228 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5229 the first operand must be shift count register (cl) or it
5230 is an instruction with VexNDS. */
c81128dc
L		 5231 assert (i.imm_operands == 1
5232 || (i.imm_operands == 0
c0f3af97
L		 5233 && (i.tm.opcode_modifier.vexnds
5234 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5235 if (operand_type_check (i.types[0], imm)
5236 || i.types[0].bitfield.shiftcount)
5237 source = 1;
5238 else
5239 source = 0;
cab737b9
L		 5240 break;
5241 case 4:
368d64cc
L		 5242 /* When there are 4 operands, the first two must be 8bit
5243 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5244 one.
5245
5246 For instructions with VexNDS, if the first operand
5247 an imm8, the source operand is the 2nd one. If the last
5248 operand is imm8, the source operand is the first one. */
5249 assert ((i.imm_operands == 2
5250 && i.types[0].bitfield.imm8
5251 && i.types[1].bitfield.imm8)
5252 || (i.tm.opcode_modifier.vexnds
5253 && i.imm_operands == 1
5254 && (i.types[0].bitfield.imm8
5255 || i.types[i.operands - 1].bitfield.imm8)));
5256 if (i.tm.opcode_modifier.vexnds)
5257 {
5258 if (i.types[0].bitfield.imm8)
5259 source = 1;
5260 else
5261 source = 0;
5262 }
5263 else
5264 source = 2;
5265 break;
5266 case 5:
cab737b9
L		 5267 break;
5268 default:
5269 abort ();
5270 }
5271
c0f3af97
L		 5272 if (!vex_3_sources)
5273 {
5274 dest = source + 1;
5275
5276 if (i.tm.opcode_modifier.vexnds)
5277 {
5278 /* For instructions with VexNDS, the register-only
5279 source operand must be XMM or YMM register. It is
fa99fab2
L		 5280 encoded in VEX prefix. We need to clear RegMem bit
5281 before calling operand_type_equal. */
5282 i386_operand_type op = i.tm.operand_types[dest];
5283 op.bitfield.regmem = 0;
c0f3af97 5284 if ((dest + 1) >= i.operands
fa99fab2
L		 5285 || (!operand_type_equal (&op, &regxmm)
5286 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5287 abort ();
5288 i.vex.register_specifier = i.op[dest].regs;
5289 dest++;
5290 }
5291 }
29b0f896
AM		 5292
5293 i.rm.mode = 3;
5294 /* One of the register operands will be encoded in the i.tm.reg
5295 field, the other in the combined i.tm.mode and i.tm.regmem
5296 fields. If no form of this instruction supports a memory
5297 destination operand, then we assume the source operand may
5298 sometimes be a memory operand and so we need to store the
5299 destination in the i.rm.reg field. */
40fb9820
L		 5300 if (!i.tm.operand_types[dest].bitfield.regmem
5301 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5302 {
5303 i.rm.reg = i.op[dest].regs->reg_num;
5304 i.rm.regmem = i.op[source].regs->reg_num;
5305 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5306 i.rex |= REX_R;
29b0f896 5307 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5308 i.rex |= REX_B;
29b0f896
AM		 5309 }
5310 else
5311 {
5312 i.rm.reg = i.op[source].regs->reg_num;
5313 i.rm.regmem = i.op[dest].regs->reg_num;
5314 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5315 i.rex |= REX_B;
29b0f896 5316 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5317 i.rex |= REX_R;
29b0f896 5318 }
161a04f6 5319 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5320 {
40fb9820
L		 5321 if (!i.types[0].bitfield.control
5322 && !i.types[1].bitfield.control)
c4a530c5 5323 abort ();
161a04f6 5324 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5325 add_prefix (LOCK_PREFIX_OPCODE);
5326 }
29b0f896
AM		 5327 }
5328 else
5329 { /* If it's not 2 reg operands... */
c0f3af97
L		 5330 unsigned int mem;
5331
29b0f896
AM		 5332 if (i.mem_operands)
5333 {
5334 unsigned int fake_zero_displacement = 0;
99018f42 5335 unsigned int op;
4eed87de 5336
85f10a01
MM		 5337 /* This has been precalculated for SSE5 instructions
5338 that have a DREX field earlier in process_drex. */
b5016f89
L		 5339 if (i.tm.opcode_modifier.drex
5340 || i.tm.opcode_modifier.drexv
5341 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5342 op = i.drex.modrm_regmem;
5343 else
5344 {
c0209578
L		 5345 for (op = 0; op < i.operands; op++)
5346 if (operand_type_check (i.types[op], anymem))
5347 break;
5348 assert (op < i.operands);
85f10a01 5349 }
29b0f896
AM		 5350
5351 default_seg = &ds;
5352
5353 if (i.base_reg == 0)
5354 {
5355 i.rm.mode = 0;
5356 if (!i.disp_operands)
5357 fake_zero_displacement = 1;
5358 if (i.index_reg == 0)
5359 {
5360 /* Operand is just <disp> */
20f0a1fc 5361 if (flag_code == CODE_64BIT)
29b0f896
AM		 5362 {
5363 /* 64bit mode overwrites the 32bit absolute
5364 addressing by RIP relative addressing and
5365 absolute addressing is encoded by one of the
5366 redundant SIB forms. */
5367 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5368 i.sib.base = NO_BASE_REGISTER;
5369 i.sib.index = NO_INDEX_REGISTER;
fc225355 5370 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5371 ? disp32s : disp32);
20f0a1fc 5372 }
fc225355
L		 5373 else if ((flag_code == CODE_16BIT)
5374 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5375 {
5376 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5377 i.types[op] = disp16;
20f0a1fc
NC		 5378 }
5379 else
5380 {
5381 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5382 i.types[op] = disp32;
29b0f896
AM		 5383 }
5384 }
5385 else /* !i.base_reg && i.index_reg */
5386 {
db51cc60
L		 5387 if (i.index_reg->reg_num == RegEiz
5388 || i.index_reg->reg_num == RegRiz)
5389 i.sib.index = NO_INDEX_REGISTER;
5390 else
5391 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5392 i.sib.base = NO_BASE_REGISTER;
5393 i.sib.scale = i.log2_scale_factor;
5394 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5395 i.types[op].bitfield.disp8 = 0;
5396 i.types[op].bitfield.disp16 = 0;
5397 i.types[op].bitfield.disp64 = 0;
29b0f896 5398 if (flag_code != CODE_64BIT)
40fb9820
L		 5399 {
5400 /* Must be 32 bit */
5401 i.types[op].bitfield.disp32 = 1;
5402 i.types[op].bitfield.disp32s = 0;
5403 }
29b0f896 5404 else
40fb9820
L		 5405 {
5406 i.types[op].bitfield.disp32 = 0;
5407 i.types[op].bitfield.disp32s = 1;
5408 }
29b0f896 5409 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5410 i.rex |= REX_X;
29b0f896
AM		 5411 }
5412 }
5413 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5414 else if (i.base_reg->reg_num == RegRip ||
5415 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5416 {
5417 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5418 i.types[op].bitfield.disp8 = 0;
5419 i.types[op].bitfield.disp16 = 0;
5420 i.types[op].bitfield.disp32 = 0;
5421 i.types[op].bitfield.disp32s = 1;
5422 i.types[op].bitfield.disp64 = 0;
71903a11 5423 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5424 if (! i.disp_operands)
5425 fake_zero_displacement = 1;
29b0f896 5426 }
40fb9820 5427 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5428 {
5429 switch (i.base_reg->reg_num)
5430 {
5431 case 3: /* (%bx) */
5432 if (i.index_reg == 0)
5433 i.rm.regmem = 7;
5434 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5435 i.rm.regmem = i.index_reg->reg_num - 6;
5436 break;
5437 case 5: /* (%bp) */
5438 default_seg = &ss;
5439 if (i.index_reg == 0)
5440 {
5441 i.rm.regmem = 6;
40fb9820 5442 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5443 {
5444 /* fake (%bp) into 0(%bp) */
40fb9820 5445 i.types[op].bitfield.disp8 = 1;
252b5132 5446 fake_zero_displacement = 1;
29b0f896
AM		 5447 }
5448 }
5449 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5450 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5451 break;
5452 default: /* (%si) -> 4 or (%di) -> 5 */
5453 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5454 }
5455 i.rm.mode = mode_from_disp_size (i.types[op]);
5456 }
5457 else /* i.base_reg and 32/64 bit mode */
5458 {
5459 if (flag_code == CODE_64BIT
40fb9820
L		 5460 && operand_type_check (i.types[op], disp))
5461 {
5462 i386_operand_type temp;
0dfbf9d7 5463 operand_type_set (&temp, 0);
40fb9820
L		 5464 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5465 i.types[op] = temp;
5466 if (i.prefix[ADDR_PREFIX] == 0)
5467 i.types[op].bitfield.disp32s = 1;
5468 else
5469 i.types[op].bitfield.disp32 = 1;
5470 }
20f0a1fc 5471
29b0f896
AM		 5472 i.rm.regmem = i.base_reg->reg_num;
5473 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5474 i.rex |= REX_B;
29b0f896
AM		 5475 i.sib.base = i.base_reg->reg_num;
5476 /* x86-64 ignores REX prefix bit here to avoid decoder
5477 complications. */
5478 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5479 {
5480 default_seg = &ss;
5481 if (i.disp_operands == 0)
5482 {
5483 fake_zero_displacement = 1;
40fb9820 5484 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5485 }
5486 }
5487 else if (i.base_reg->reg_num == ESP_REG_NUM)
5488 {
5489 default_seg = &ss;
5490 }
5491 i.sib.scale = i.log2_scale_factor;
5492 if (i.index_reg == 0)
5493 {
5494 /* <disp>(%esp) becomes two byte modrm with no index
5495 register. We've already stored the code for esp
5496 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5497 Any base register besides %esp will not use the
5498 extra modrm byte. */
5499 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5500 }
5501 else
5502 {
db51cc60
L		 5503 if (i.index_reg->reg_num == RegEiz
5504 || i.index_reg->reg_num == RegRiz)
5505 i.sib.index = NO_INDEX_REGISTER;
5506 else
5507 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5508 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5509 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5510 i.rex |= REX_X;
29b0f896 5511 }
67a4f2b7
AO		 5512
5513 if (i.disp_operands
5514 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5515 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5516 i.rm.mode = 0;
5517 else
5518 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5519 }
252b5132 5520
29b0f896
AM		 5521 if (fake_zero_displacement)
5522 {
5523 /* Fakes a zero displacement assuming that i.types[op]
5524 holds the correct displacement size. */
5525 expressionS *exp;
5526
5527 assert (i.op[op].disps == 0);
5528 exp = &disp_expressions[i.disp_operands++];
5529 i.op[op].disps = exp;
5530 exp->X_op = O_constant;
5531 exp->X_add_number = 0;
5532 exp->X_add_symbol = (symbolS *) 0;
5533 exp->X_op_symbol = (symbolS *) 0;
5534 }
c0f3af97
L		 5535
5536 mem = op;
29b0f896 5537 }
c0f3af97
L		 5538 else
5539 mem = ~0;
252b5132 5540
29b0f896
AM		 5541 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5542 (if any) based on i.tm.extension_opcode. Again, we must be
5543 careful to make sure that segment/control/debug/test/MMX
5544 registers are coded into the i.rm.reg field. */
5545 if (i.reg_operands)
5546 {
99018f42
L		 5547 unsigned int op;
5548
85f10a01
MM		 5549 /* This has been precalculated for SSE5 instructions
5550 that have a DREX field earlier in process_drex. */
b5016f89
L		 5551 if (i.tm.opcode_modifier.drex
5552 || i.tm.opcode_modifier.drexv
5553 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5554 {
5555 op = i.drex.modrm_reg;
5556 i.rm.reg = i.op[op].regs->reg_num;
5557 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5558 i.rex |= REX_R;
5559 }
5560 else
5561 {
c0f3af97
L		 5562 unsigned int vex_reg = ~0;
5563
c0209578
L		 5564 for (op = 0; op < i.operands; op++)
5565 if (i.types[op].bitfield.reg8
5566 || i.types[op].bitfield.reg16
5567 || i.types[op].bitfield.reg32
5568 || i.types[op].bitfield.reg64
5569 || i.types[op].bitfield.regmmx
5570 || i.types[op].bitfield.regxmm
c0f3af97 5571 || i.types[op].bitfield.regymm
c0209578
L		 5572 || i.types[op].bitfield.sreg2
5573 || i.types[op].bitfield.sreg3
5574 || i.types[op].bitfield.control
5575 || i.types[op].bitfield.debug
5576 || i.types[op].bitfield.test)
5577 break;
5578
c0f3af97
L		 5579 if (vex_3_sources)
5580 op = dest;
5581 else if (i.tm.opcode_modifier.vexnds)
5582 {
5583 /* For instructions with VexNDS, the register-only
5584 source operand is encoded in VEX prefix. */
5585 assert (mem != (unsigned int) ~0);
5586
5587 if (op > mem)
5588 {
5589 vex_reg = op++;
5590 assert (op < i.operands);
5591 }
5592 else
5593 {
5594 vex_reg = op + 1;
5595 assert (vex_reg < i.operands);
5596 }
5597 }
5598 else if (i.tm.opcode_modifier.vexndd)
5599 {
5600 /* For instructions with VexNDD, there should be
5601 no memory operand and the register destination
5602 is encoded in VEX prefix. */
5603 assert (i.mem_operands == 0
5604 && (op + 2) == i.operands);
5605 vex_reg = op + 1;
5606 }
5607 else
5608 assert (op < i.operands);
5609
5610 if (vex_reg != (unsigned int) ~0)
5611 {
5612 assert (i.reg_operands == 2);
5613
5614 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5615 & regxmm)
5616 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5617 &regymm))
5618 abort ();
5619 i.vex.register_specifier = i.op[vex_reg].regs;
5620 }
99018f42 5621
85f10a01
MM		 5622 /* If there is an extension opcode to put here, the
5623 register number must be put into the regmem field. */
c0209578
L		 5624 if (i.tm.extension_opcode != None)
5625 {
5626 i.rm.regmem = i.op[op].regs->reg_num;
5627 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5628 i.rex |= REX_B;
5629 }
5630 else
5631 {
5632 i.rm.reg = i.op[op].regs->reg_num;
5633 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5634 i.rex |= REX_R;
5635 }
85f10a01 5636 }
252b5132 5637
29b0f896
AM		 5638 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5639 must set it to 3 to indicate this is a register operand
5640 in the regmem field. */
5641 if (!i.mem_operands)
5642 i.rm.mode = 3;
5643 }
252b5132 5644
29b0f896 5645 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5646 if (i.tm.extension_opcode != None
5647 && !(i.tm.opcode_modifier.drex
5648 || i.tm.opcode_modifier.drexv
5649 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5650 i.rm.reg = i.tm.extension_opcode;
5651 }
5652 return default_seg;
5653}
252b5132 5654
29b0f896 5655static void
e3bb37b5 5656output_branch (void)
29b0f896
AM		 5657{
5658 char *p;
5659 int code16;
5660 int prefix;
5661 relax_substateT subtype;
5662 symbolS *sym;
5663 offsetT off;
5664
5665 code16 = 0;
5666 if (flag_code == CODE_16BIT)
5667 code16 = CODE16;
5668
5669 prefix = 0;
5670 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5671 {
29b0f896
AM		 5672 prefix = 1;
5673 i.prefixes -= 1;
5674 code16 ^= CODE16;
252b5132 5675 }
29b0f896
AM		 5676 /* Pentium4 branch hints. */
5677 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5678 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5679 {
29b0f896
AM		 5680 prefix++;
5681 i.prefixes--;
5682 }
5683 if (i.prefix[REX_PREFIX] != 0)
5684 {
5685 prefix++;
5686 i.prefixes--;
2f66722d
AM		 5687 }
5688
29b0f896
AM		 5689 if (i.prefixes != 0 && !intel_syntax)
5690 as_warn (_("skipping prefixes on this instruction"));
5691
5692 /* It's always a symbol; End frag & setup for relax.
5693 Make sure there is enough room in this frag for the largest
5694 instruction we may generate in md_convert_frag. This is 2
5695 bytes for the opcode and room for the prefix and largest
5696 displacement. */
5697 frag_grow (prefix + 2 + 4);
5698 /* Prefix and 1 opcode byte go in fr_fix. */
5699 p = frag_more (prefix + 1);
5700 if (i.prefix[DATA_PREFIX] != 0)
5701 *p++ = DATA_PREFIX_OPCODE;
5702 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5703 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5704 *p++ = i.prefix[SEG_PREFIX];
5705 if (i.prefix[REX_PREFIX] != 0)
5706 *p++ = i.prefix[REX_PREFIX];
5707 *p = i.tm.base_opcode;
5708
5709 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5710 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5711 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5712 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5713 else
5714 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5715 subtype |= code16;
3e73aa7c 5716
29b0f896
AM		 5717 sym = i.op[0].disps->X_add_symbol;
5718 off = i.op[0].disps->X_add_number;
3e73aa7c 5719
29b0f896
AM		 5720 if (i.op[0].disps->X_op != O_constant
5721 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5722 {
29b0f896
AM		 5723 /* Handle complex expressions. */
5724 sym = make_expr_symbol (i.op[0].disps);
5725 off = 0;
5726 }
3e73aa7c 5727
29b0f896
AM		 5728 /* 1 possible extra opcode + 4 byte displacement go in var part.
5729 Pass reloc in fr_var. */
5730 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5731}
3e73aa7c 5732
29b0f896 5733static void
e3bb37b5 5734output_jump (void)
29b0f896
AM		 5735{
5736 char *p;
5737 int size;
3e02c1cc 5738 fixS *fixP;
29b0f896 5739
40fb9820 5740 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5741 {
5742 /* This is a loop or jecxz type instruction. */
5743 size = 1;
5744 if (i.prefix[ADDR_PREFIX] != 0)
5745 {
5746 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5747 i.prefixes -= 1;
5748 }
5749 /* Pentium4 branch hints. */
5750 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5751 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5752 {
5753 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5754 i.prefixes--;
3e73aa7c
JH		 5755 }
5756 }
29b0f896
AM		 5757 else
5758 {
5759 int code16;
3e73aa7c 5760
29b0f896
AM		 5761 code16 = 0;
5762 if (flag_code == CODE_16BIT)
5763 code16 = CODE16;
3e73aa7c 5764
29b0f896
AM		 5765 if (i.prefix[DATA_PREFIX] != 0)
5766 {
5767 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5768 i.prefixes -= 1;
5769 code16 ^= CODE16;
5770 }
252b5132 5771
29b0f896
AM		 5772 size = 4;
5773 if (code16)
5774 size = 2;
5775 }
9fcc94b6 5776
29b0f896
AM		 5777 if (i.prefix[REX_PREFIX] != 0)
5778 {
5779 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5780 i.prefixes -= 1;
5781 }
252b5132 5782
29b0f896
AM		 5783 if (i.prefixes != 0 && !intel_syntax)
5784 as_warn (_("skipping prefixes on this instruction"));
e0890092 5785
29b0f896
AM		 5786 p = frag_more (1 + size);
5787 *p++ = i.tm.base_opcode;
e0890092 5788
3e02c1cc
AM		 5789 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5790 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5791
5792 /* All jumps handled here are signed, but don't use a signed limit
5793 check for 32 and 16 bit jumps as we want to allow wrap around at
5794 4G and 64k respectively. */
5795 if (size == 1)
5796 fixP->fx_signed = 1;
29b0f896 5797}
e0890092 5798
29b0f896 5799static void
e3bb37b5 5800output_interseg_jump (void)
29b0f896
AM		 5801{
5802 char *p;
5803 int size;
5804 int prefix;
5805 int code16;
252b5132 5806
29b0f896
AM		 5807 code16 = 0;
5808 if (flag_code == CODE_16BIT)
5809 code16 = CODE16;
a217f122 5810
29b0f896
AM		 5811 prefix = 0;
5812 if (i.prefix[DATA_PREFIX] != 0)
5813 {
5814 prefix = 1;
5815 i.prefixes -= 1;
5816 code16 ^= CODE16;
5817 }
5818 if (i.prefix[REX_PREFIX] != 0)
5819 {
5820 prefix++;
5821 i.prefixes -= 1;
5822 }
252b5132 5823
29b0f896
AM		 5824 size = 4;
5825 if (code16)
5826 size = 2;
252b5132 5827
29b0f896
AM		 5828 if (i.prefixes != 0 && !intel_syntax)
5829 as_warn (_("skipping prefixes on this instruction"));
252b5132 5830
29b0f896
AM		 5831 /* 1 opcode; 2 segment; offset */
5832 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5833
29b0f896
AM		 5834 if (i.prefix[DATA_PREFIX] != 0)
5835 *p++ = DATA_PREFIX_OPCODE;
252b5132 5836
29b0f896
AM		 5837 if (i.prefix[REX_PREFIX] != 0)
5838 *p++ = i.prefix[REX_PREFIX];
252b5132 5839
29b0f896
AM		 5840 *p++ = i.tm.base_opcode;
5841 if (i.op[1].imms->X_op == O_constant)
5842 {
5843 offsetT n = i.op[1].imms->X_add_number;
252b5132 5844
29b0f896
AM		 5845 if (size == 2
5846 && !fits_in_unsigned_word (n)
5847 && !fits_in_signed_word (n))
5848 {
5849 as_bad (_("16-bit jump out of range"));
5850 return;
5851 }
5852 md_number_to_chars (p, n, size);
5853 }
5854 else
5855 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5856 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5857 if (i.op[0].imms->X_op != O_constant)
5858 as_bad (_("can't handle non absolute segment in `%s'"),
5859 i.tm.name);
5860 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5861}
a217f122 5862
29b0f896 5863static void
e3bb37b5 5864output_insn (void)
29b0f896 5865{
2bbd9c25
JJ		 5866 fragS *insn_start_frag;
5867 offsetT insn_start_off;
5868
29b0f896
AM		 5869 /* Tie dwarf2 debug info to the address at the start of the insn.
5870 We can't do this after the insn has been output as the current
5871 frag may have been closed off. eg. by frag_var. */
5872 dwarf2_emit_insn (0);
5873
2bbd9c25
JJ		 5874 insn_start_frag = frag_now;
5875 insn_start_off = frag_now_fix ();
5876
29b0f896 5877 /* Output jumps. */
40fb9820 5878 if (i.tm.opcode_modifier.jump)
29b0f896 5879 output_branch ();
40fb9820
L		 5880 else if (i.tm.opcode_modifier.jumpbyte
5881 || i.tm.opcode_modifier.jumpdword)
29b0f896 5882 output_jump ();
40fb9820 5883 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5884 output_interseg_jump ();
5885 else
5886 {
5887 /* Output normal instructions here. */
5888 char *p;
5889 unsigned char *q;
47465058 5890 unsigned int j;
331d2d0d 5891 unsigned int prefix;
4dffcebc 5892
c0f3af97
L		 5893 /* Since the VEX prefix contains the implicit prefix, we don't
5894 need the explicit prefix. */
5895 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5896 {
c0f3af97 5897 switch (i.tm.opcode_length)
bc4bd9ab 5898 {
c0f3af97
L		 5899 case 3:
5900 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5901 {
c0f3af97
L		 5902 prefix = (i.tm.base_opcode >> 24) & 0xff;
5903 goto check_prefix;
5904 }
5905 break;
5906 case 2:
5907 if ((i.tm.base_opcode & 0xff0000) != 0)
5908 {
5909 prefix = (i.tm.base_opcode >> 16) & 0xff;
5910 if (i.tm.cpu_flags.bitfield.cpupadlock)
5911 {
4dffcebc 5912check_prefix:
c0f3af97
L		 5913 if (prefix != REPE_PREFIX_OPCODE
5914 || (i.prefix[LOCKREP_PREFIX]
5915 != REPE_PREFIX_OPCODE))
5916 add_prefix (prefix);
5917 }
5918 else
4dffcebc
L		 5919 add_prefix (prefix);
5920 }
c0f3af97
L		 5921 break;
5922 case 1:
5923 break;
5924 default:
5925 abort ();
bc4bd9ab 5926 }
c0f3af97
L		 5927
5928 /* The prefix bytes. */
5929 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5930 if (*q)
5931 FRAG_APPEND_1_CHAR (*q);
0f10071e 5932 }
252b5132 5933
c0f3af97
L		 5934 if (i.tm.opcode_modifier.vex)
5935 {
5936 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5937 if (*q)
5938 switch (j)
5939 {
5940 case REX_PREFIX:
5941 /* REX byte is encoded in VEX prefix. */
5942 break;
5943 case SEG_PREFIX:
5944 case ADDR_PREFIX:
5945 FRAG_APPEND_1_CHAR (*q);
5946 break;
5947 default:
5948 /* There should be no other prefixes for instructions
5949 with VEX prefix. */
5950 abort ();
5951 }
5952
5953 /* Now the VEX prefix. */
5954 p = frag_more (i.vex.length);
5955 for (j = 0; j < i.vex.length; j++)
5956 p[j] = i.vex.bytes[j];
5957 }
252b5132 5958
29b0f896 5959 /* Now the opcode; be careful about word order here! */
4dffcebc 5960 if (i.tm.opcode_length == 1)
29b0f896
AM		 5961 {
5962 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5963 }
5964 else
5965 {
4dffcebc 5966 switch (i.tm.opcode_length)
331d2d0d 5967 {
4dffcebc 5968 case 3:
331d2d0d
L		 5969 p = frag_more (3);
5970 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5971 break;
5972 case 2:
5973 p = frag_more (2);
5974 break;
5975 default:
5976 abort ();
5977 break;
331d2d0d 5978 }
0f10071e 5979
29b0f896
AM		 5980 /* Put out high byte first: can't use md_number_to_chars! */
5981 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5982 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5983
5984 /* On SSE5, encode the OC1 bit in the DREX field if this
5985 encoding has multiple formats. */
5986 if (i.tm.opcode_modifier.drex
5987 && i.tm.opcode_modifier.drexv
5988 && DREX_OC1 (i.tm.extension_opcode))
5989 *p |= DREX_OC1_MASK;
29b0f896 5990 }
3e73aa7c 5991
29b0f896 5992 /* Now the modrm byte and sib byte (if present). */
40fb9820 5993 if (i.tm.opcode_modifier.modrm)
29b0f896 5994 {
4a3523fa
L		 5995 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5996 | i.rm.reg << 3
5997 | i.rm.mode << 6));
29b0f896
AM		 5998 /* If i.rm.regmem == ESP (4)
5999 && i.rm.mode != (Register mode)
6000 && not 16 bit
6001 ==> need second modrm byte. */
6002 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6003 && i.rm.mode != 3
40fb9820 6004 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6005 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6006 | i.sib.index << 3
6007 | i.sib.scale << 6));
29b0f896 6008 }
3e73aa7c 6009
85f10a01
MM		 6010 /* Write the DREX byte if needed. */
6011 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
6012 {
6013 p = frag_more (1);
6014 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
6015
6016 /* Encode the OC0 bit if this encoding has multiple
6017 formats. */
6018 if ((i.tm.opcode_modifier.drex
6019 || i.tm.opcode_modifier.drexv)
6020 && DREX_OC0 (i.tm.extension_opcode))
6021 *p |= DREX_OC0_MASK;
6022 }
6023
29b0f896 6024 if (i.disp_operands)
2bbd9c25 6025 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6026
29b0f896 6027 if (i.imm_operands)
2bbd9c25 6028 output_imm (insn_start_frag, insn_start_off);
29b0f896 6029 }
252b5132 6030
29b0f896
AM		 6031#ifdef DEBUG386
6032 if (flag_debug)
6033 {
7b81dfbb 6034 pi ("" /*line*/, &i);
29b0f896
AM		 6035 }
6036#endif /* DEBUG386 */
6037}
252b5132 6038
e205caa7
L		 6039/* Return the size of the displacement operand N. */
6040
6041static int
6042disp_size (unsigned int n)
6043{
6044 int size = 4;
40fb9820
L		 6045 if (i.types[n].bitfield.disp64)
6046 size = 8;
6047 else if (i.types[n].bitfield.disp8)
6048 size = 1;
6049 else if (i.types[n].bitfield.disp16)
6050 size = 2;
e205caa7
L		 6051 return size;
6052}
6053
6054/* Return the size of the immediate operand N. */
6055
6056static int
6057imm_size (unsigned int n)
6058{
6059 int size = 4;
40fb9820
L		 6060 if (i.types[n].bitfield.imm64)
6061 size = 8;
6062 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6063 size = 1;
6064 else if (i.types[n].bitfield.imm16)
6065 size = 2;
e205caa7
L		 6066 return size;
6067}
6068
29b0f896 6069static void
64e74474 6070output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6071{
6072 char *p;
6073 unsigned int n;
252b5132 6074
29b0f896
AM		 6075 for (n = 0; n < i.operands; n++)
6076 {
40fb9820 6077 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6078 {
6079 if (i.op[n].disps->X_op == O_constant)
6080 {
e205caa7 6081 int size = disp_size (n);
29b0f896 6082 offsetT val;
252b5132 6083
29b0f896
AM		 6084 val = offset_in_range (i.op[n].disps->X_add_number,
6085 size);
6086 p = frag_more (size);
6087 md_number_to_chars (p, val, size);
6088 }
6089 else
6090 {
f86103b7 6091 enum bfd_reloc_code_real reloc_type;
e205caa7 6092 int size = disp_size (n);
40fb9820 6093 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6094 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6095
e205caa7 6096 /* We can't have 8 bit displacement here. */
40fb9820 6097 assert (!i.types[n].bitfield.disp8);
e205caa7 6098
29b0f896
AM		 6099 /* The PC relative address is computed relative
6100 to the instruction boundary, so in case immediate
6101 fields follows, we need to adjust the value. */
6102 if (pcrel && i.imm_operands)
6103 {
29b0f896 6104 unsigned int n1;
e205caa7 6105 int sz = 0;
252b5132 6106
29b0f896 6107 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6108 if (operand_type_check (i.types[n1], imm))
252b5132 6109 {
e205caa7
L		 6110 /* Only one immediate is allowed for PC
6111 relative address. */
6112 assert (sz == 0);
6113 sz = imm_size (n1);
6114 i.op[n].disps->X_add_number -= sz;
252b5132 6115 }
29b0f896 6116 /* We should find the immediate. */
e205caa7 6117 assert (sz != 0);
29b0f896 6118 }
520dc8e8 6119
29b0f896 6120 p = frag_more (size);
2bbd9c25 6121 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6122 if (GOT_symbol
2bbd9c25 6123 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6124 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6125 || reloc_type == BFD_RELOC_X86_64_32S
6126 || (reloc_type == BFD_RELOC_64
6127 && object_64bit))
d6ab8113
JB		 6128 && (i.op[n].disps->X_op == O_symbol
6129 || (i.op[n].disps->X_op == O_add
6130 && ((symbol_get_value_expression
6131 (i.op[n].disps->X_op_symbol)->X_op)
6132 == O_subtract))))
6133 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6134 {
6135 offsetT add;
6136
6137 if (insn_start_frag == frag_now)
6138 add = (p - frag_now->fr_literal) - insn_start_off;
6139 else
6140 {
6141 fragS *fr;
6142
6143 add = insn_start_frag->fr_fix - insn_start_off;
6144 for (fr = insn_start_frag->fr_next;
6145 fr && fr != frag_now; fr = fr->fr_next)
6146 add += fr->fr_fix;
6147 add += p - frag_now->fr_literal;
6148 }
6149
4fa24527 6150 if (!object_64bit)
7b81dfbb
AJ		 6151 {
6152 reloc_type = BFD_RELOC_386_GOTPC;
6153 i.op[n].imms->X_add_number += add;
6154 }
6155 else if (reloc_type == BFD_RELOC_64)
6156 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6157 else
7b81dfbb
AJ		 6158 /* Don't do the adjustment for x86-64, as there
6159 the pcrel addressing is relative to the _next_
6160 insn, and that is taken care of in other code. */
d6ab8113 6161 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6162 }
062cd5e7 6163 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6164 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6165 }
6166 }
6167 }
6168}
252b5132 6169
29b0f896 6170static void
64e74474 6171output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6172{
6173 char *p;
6174 unsigned int n;
252b5132 6175
29b0f896
AM		 6176 for (n = 0; n < i.operands; n++)
6177 {
40fb9820 6178 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6179 {
6180 if (i.op[n].imms->X_op == O_constant)
6181 {
e205caa7 6182 int size = imm_size (n);
29b0f896 6183 offsetT val;
b4cac588 6184
29b0f896
AM		 6185 val = offset_in_range (i.op[n].imms->X_add_number,
6186 size);
6187 p = frag_more (size);
6188 md_number_to_chars (p, val, size);
6189 }
6190 else
6191 {
6192 /* Not absolute_section.
6193 Need a 32-bit fixup (don't support 8bit
6194 non-absolute imms). Try to support other
6195 sizes ... */
f86103b7 6196 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6197 int size = imm_size (n);
6198 int sign;
29b0f896 6199
40fb9820 6200 if (i.types[n].bitfield.imm32s
a7d61044 6201 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6202 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6203 sign = 1;
e205caa7
L		 6204 else
6205 sign = 0;
520dc8e8 6206
29b0f896
AM		 6207 p = frag_more (size);
6208 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6209
2bbd9c25
JJ		 6210 /* This is tough to explain. We end up with this one if we
6211 * have operands that look like
6212 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6213 * obtain the absolute address of the GOT, and it is strongly
6214 * preferable from a performance point of view to avoid using
6215 * a runtime relocation for this. The actual sequence of
6216 * instructions often look something like:
6217 *
6218 * call .L66
6219 * .L66:
6220 * popl %ebx
6221 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6222 *
6223 * The call and pop essentially return the absolute address
6224 * of the label .L66 and store it in %ebx. The linker itself
6225 * will ultimately change the first operand of the addl so
6226 * that %ebx points to the GOT, but to keep things simple, the
6227 * .o file must have this operand set so that it generates not
6228 * the absolute address of .L66, but the absolute address of
6229 * itself. This allows the linker itself simply treat a GOTPC
6230 * relocation as asking for a pcrel offset to the GOT to be
6231 * added in, and the addend of the relocation is stored in the
6232 * operand field for the instruction itself.
6233 *
6234 * Our job here is to fix the operand so that it would add
6235 * the correct offset so that %ebx would point to itself. The
6236 * thing that is tricky is that .-.L66 will point to the
6237 * beginning of the instruction, so we need to further modify
6238 * the operand so that it will point to itself. There are
6239 * other cases where you have something like:
6240 *
6241 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6242 *
6243 * and here no correction would be required. Internally in
6244 * the assembler we treat operands of this form as not being
6245 * pcrel since the '.' is explicitly mentioned, and I wonder
6246 * whether it would simplify matters to do it this way. Who
6247 * knows. In earlier versions of the PIC patches, the
6248 * pcrel_adjust field was used to store the correction, but
6249 * since the expression is not pcrel, I felt it would be
6250 * confusing to do it this way. */
6251
d6ab8113 6252 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6253 || reloc_type == BFD_RELOC_X86_64_32S
6254 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6255 && GOT_symbol
6256 && GOT_symbol == i.op[n].imms->X_add_symbol
6257 && (i.op[n].imms->X_op == O_symbol
6258 || (i.op[n].imms->X_op == O_add
6259 && ((symbol_get_value_expression
6260 (i.op[n].imms->X_op_symbol)->X_op)
6261 == O_subtract))))
6262 {
2bbd9c25
JJ		 6263 offsetT add;
6264
6265 if (insn_start_frag == frag_now)
6266 add = (p - frag_now->fr_literal) - insn_start_off;
6267 else
6268 {
6269 fragS *fr;
6270
6271 add = insn_start_frag->fr_fix - insn_start_off;
6272 for (fr = insn_start_frag->fr_next;
6273 fr && fr != frag_now; fr = fr->fr_next)
6274 add += fr->fr_fix;
6275 add += p - frag_now->fr_literal;
6276 }
6277
4fa24527 6278 if (!object_64bit)
d6ab8113 6279 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6280 else if (size == 4)
d6ab8113 6281 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6282 else if (size == 8)
6283 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6284 i.op[n].imms->X_add_number += add;
29b0f896 6285 }
29b0f896
AM		 6286 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6287 i.op[n].imms, 0, reloc_type);
6288 }
6289 }
6290 }
252b5132
RH		 6291}
6292\f
d182319b
JB		 6293/* x86_cons_fix_new is called via the expression parsing code when a
6294 reloc is needed. We use this hook to get the correct .got reloc. */
6295static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6296static int cons_sign = -1;
6297
6298void
e3bb37b5 6299x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6300 expressionS *exp)
d182319b
JB		 6301{
6302 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6303
6304 got_reloc = NO_RELOC;
6305
6306#ifdef TE_PE
6307 if (exp->X_op == O_secrel)
6308 {
6309 exp->X_op = O_symbol;
6310 r = BFD_RELOC_32_SECREL;
6311 }
6312#endif
6313
6314 fix_new_exp (frag, off, len, exp, 0, r);
6315}
6316
718ddfc0
JB		 6317#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6318# define lex_got(reloc, adjust, types) NULL
6319#else
f3c180ae
AM		 6320/* Parse operands of the form
6321 <symbol>@GOTOFF+<nnn>
6322 and similar .plt or .got references.
6323
6324 If we find one, set up the correct relocation in RELOC and copy the
6325 input string, minus the `@GOTOFF' into a malloc'd buffer for
6326 parsing by the calling routine. Return this buffer, and if ADJUST
6327 is non-null set it to the length of the string we removed from the
6328 input line. Otherwise return NULL. */
6329static char *
3956db08 6330lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6331 int *adjust,
40fb9820 6332 i386_operand_type *types)
f3c180ae 6333{
7b81dfbb
AJ		 6334 /* Some of the relocations depend on the size of what field is to
6335 be relocated. But in our callers i386_immediate and i386_displacement
6336 we don't yet know the operand size (this will be set by insn
6337 matching). Hence we record the word32 relocation here,
6338 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6339 static const struct {
6340 const char *str;
4fa24527 6341 const enum bfd_reloc_code_real rel[2];
40fb9820 6342 const i386_operand_type types64;
f3c180ae 6343 } gotrel[] = {
4eed87de
AM		 6344 { "PLTOFF", { 0,
6345 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6346 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6347 { "PLT", { BFD_RELOC_386_PLT32,
6348 BFD_RELOC_X86_64_PLT32 },
40fb9820 6349 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6350 { "GOTPLT", { 0,
6351 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6352 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6353 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6354 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6355 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6356 { "GOTPCREL", { 0,
6357 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6358 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6359 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6360 BFD_RELOC_X86_64_TLSGD },
40fb9820 6361 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6362 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6363 0 },
40fb9820 6364 OPERAND_TYPE_NONE },
4eed87de
AM		 6365 { "TLSLD", { 0,
6366 BFD_RELOC_X86_64_TLSLD },
40fb9820 6367 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6368 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6369 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6370 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6371 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6372 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6373 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6374 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6375 0 },
40fb9820 6376 OPERAND_TYPE_NONE },
4eed87de
AM		 6377 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6378 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 6379
6380 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6381 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6382 0 },
40fb9820 6383 OPERAND_TYPE_NONE },
4eed87de
AM		 6384 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6385 0 },
40fb9820 6386 OPERAND_TYPE_NONE },
4eed87de
AM		 6387 { "GOT", { BFD_RELOC_386_GOT32,
6388 BFD_RELOC_X86_64_GOT32 },
40fb9820 6389 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6390 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6391 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6392 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6393 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6394 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6395 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6396 };
6397 char *cp;
6398 unsigned int j;
6399
718ddfc0
JB		 6400 if (!IS_ELF)
6401 return NULL;
6402
f3c180ae 6403 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6404 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6405 return NULL;
6406
47465058 6407 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6408 {
6409 int len;
6410
6411 len = strlen (gotrel[j].str);
28f81592 6412 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6413 {
4fa24527 6414 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6415 {
28f81592
AM		 6416 int first, second;
6417 char *tmpbuf, *past_reloc;
f3c180ae 6418
4fa24527 6419 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6420 if (adjust)
6421 *adjust = len;
f3c180ae 6422
3956db08
JB		 6423 if (types)
6424 {
6425 if (flag_code != CODE_64BIT)
40fb9820
L		 6426 {
6427 types->bitfield.imm32 = 1;
6428 types->bitfield.disp32 = 1;
6429 }
3956db08
JB		 6430 else
6431 *types = gotrel[j].types64;
6432 }
6433
f3c180ae
AM		 6434 if (GOT_symbol == NULL)
6435 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6436
28f81592 6437 /* The length of the first part of our input line. */
f3c180ae 6438 first = cp - input_line_pointer;
28f81592
AM		 6439
6440 /* The second part goes from after the reloc token until
67c11a9b 6441 (and including) an end_of_line char or comma. */
28f81592 6442 past_reloc = cp + 1 + len;
67c11a9b
AM		 6443 cp = past_reloc;
6444 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6445 ++cp;
6446 second = cp + 1 - past_reloc;
28f81592
AM		 6447
6448 /* Allocate and copy string. The trailing NUL shouldn't
6449 be necessary, but be safe. */
6450 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6451 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6452 if (second != 0 && *past_reloc != ' ')
6453 /* Replace the relocation token with ' ', so that
6454 errors like foo@GOTOFF1 will be detected. */
6455 tmpbuf[first++] = ' ';
6456 memcpy (tmpbuf + first, past_reloc, second);
6457 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6458 return tmpbuf;
6459 }
6460
4fa24527
JB		 6461 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6462 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6463 return NULL;
6464 }
6465 }
6466
6467 /* Might be a symbol version string. Don't as_bad here. */
6468 return NULL;
6469}
6470
f3c180ae 6471void
e3bb37b5 6472x86_cons (expressionS *exp, int size)
f3c180ae 6473{
4fa24527 6474 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6475 {
6476 /* Handle @GOTOFF and the like in an expression. */
6477 char *save;
6478 char *gotfree_input_line;
6479 int adjust;
6480
6481 save = input_line_pointer;
3956db08 6482 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6483 if (gotfree_input_line)
6484 input_line_pointer = gotfree_input_line;
6485
6486 expression (exp);
6487
6488 if (gotfree_input_line)
6489 {
6490 /* expression () has merrily parsed up to the end of line,
6491 or a comma - in the wrong buffer. Transfer how far
6492 input_line_pointer has moved to the right buffer. */
6493 input_line_pointer = (save
6494 + (input_line_pointer - gotfree_input_line)
6495 + adjust);
6496 free (gotfree_input_line);
3992d3b7
AM		 6497 if (exp->X_op == O_constant
6498 || exp->X_op == O_absent
6499 || exp->X_op == O_illegal
6500 || exp->X_op == O_register
6501 || exp->X_op == O_big)
6502 {
6503 char c = *input_line_pointer;
6504 *input_line_pointer = 0;
6505 as_bad (_("missing or invalid expression `%s'"), save);
6506 *input_line_pointer = c;
6507 }
f3c180ae
AM		 6508 }
6509 }
6510 else
6511 expression (exp);
6512}
6513#endif
6514
d182319b 6515static void signed_cons (int size)
6482c264 6516{
d182319b
JB		 6517 if (flag_code == CODE_64BIT)
6518 cons_sign = 1;
6519 cons (size);
6520 cons_sign = -1;
6482c264
NC		 6521}
6522
d182319b 6523#ifdef TE_PE
6482c264
NC		 6524static void
6525pe_directive_secrel (dummy)
6526 int dummy ATTRIBUTE_UNUSED;
6527{
6528 expressionS exp;
6529
6530 do
6531 {
6532 expression (&exp);
6533 if (exp.X_op == O_symbol)
6534 exp.X_op = O_secrel;
6535
6536 emit_expr (&exp, 4);
6537 }
6538 while (*input_line_pointer++ == ',');
6539
6540 input_line_pointer--;
6541 demand_empty_rest_of_line ();
6542}
6482c264
NC		 6543#endif
6544
252b5132 6545static int
70e41ade 6546i386_immediate (char *imm_start)
252b5132
RH		 6547{
6548 char *save_input_line_pointer;
f3c180ae 6549 char *gotfree_input_line;
252b5132 6550 segT exp_seg = 0;
47926f60 6551 expressionS *exp;
40fb9820
L		 6552 i386_operand_type types;
6553
0dfbf9d7 6554 operand_type_set (&types, ~0);
252b5132
RH		 6555
6556 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6557 {
31b2323c
L		 6558 as_bad (_("at most %d immediate operands are allowed"),
6559 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6560 return 0;
6561 }
6562
6563 exp = &im_expressions[i.imm_operands++];
520dc8e8 6564 i.op[this_operand].imms = exp;
252b5132
RH		 6565
6566 if (is_space_char (*imm_start))
6567 ++imm_start;
6568
6569 save_input_line_pointer = input_line_pointer;
6570 input_line_pointer = imm_start;
6571
3956db08 6572 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6573 if (gotfree_input_line)
6574 input_line_pointer = gotfree_input_line;
252b5132
RH		 6575
6576 exp_seg = expression (exp);
6577
83183c0c 6578 SKIP_WHITESPACE ();
252b5132 6579 if (*input_line_pointer)
f3c180ae 6580 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6581
6582 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 6583 if (gotfree_input_line)
6584 free (gotfree_input_line);
252b5132 6585
3992d3b7
AM		 6586 if (exp->X_op == O_absent
6587 || exp->X_op == O_illegal
6588 || exp->X_op == O_big
6589 || (gotfree_input_line
6590 && (exp->X_op == O_constant
6591 || exp->X_op == O_register)))
252b5132 6592 {
3992d3b7 6593 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6594 imm_start);
3992d3b7 6595 return 0;
252b5132 6596 }
3e73aa7c 6597 else if (exp->X_op == O_constant)
252b5132 6598 {
47926f60 6599 /* Size it properly later. */
40fb9820 6600 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6601 /* If BFD64, sign extend val. */
4eed87de
AM		 6602 if (!use_rela_relocations
6603 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6604 exp->X_add_number
6605 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6606 }
4c63da97 6607#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6608 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6609 && exp_seg != absolute_section
47926f60 6610 && exp_seg != text_section
24eab124
AM		 6611 && exp_seg != data_section
6612 && exp_seg != bss_section
6613 && exp_seg != undefined_section
f86103b7 6614 && !bfd_is_com_section (exp_seg))
252b5132 6615 {
d0b47220 6616 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6617 return 0;
6618 }
6619#endif
bb8f5920
L		 6620 else if (!intel_syntax && exp->X_op == O_register)
6621 {
6622 as_bad (_("illegal immediate register operand %s"), imm_start);
6623 return 0;
6624 }
252b5132
RH		 6625 else
6626 {
6627 /* This is an address. The size of the address will be
24eab124 6628 determined later, depending on destination register,
3e73aa7c 6629 suffix, or the default for the section. */
40fb9820
L		 6630 i.types[this_operand].bitfield.imm8 = 1;
6631 i.types[this_operand].bitfield.imm16 = 1;
6632 i.types[this_operand].bitfield.imm32 = 1;
6633 i.types[this_operand].bitfield.imm32s = 1;
6634 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6635 i.types[this_operand] = operand_type_and (i.types[this_operand],
6636 types);
252b5132
RH		 6637 }
6638
6639 return 1;
6640}
6641
551c1ca1 6642static char *
e3bb37b5 6643i386_scale (char *scale)
252b5132 6644{
551c1ca1
AM		 6645 offsetT val;
6646 char *save = input_line_pointer;
252b5132 6647
551c1ca1
AM		 6648 input_line_pointer = scale;
6649 val = get_absolute_expression ();
6650
6651 switch (val)
252b5132 6652 {
551c1ca1 6653 case 1:
252b5132
RH		 6654 i.log2_scale_factor = 0;
6655 break;
551c1ca1 6656 case 2:
252b5132
RH		 6657 i.log2_scale_factor = 1;
6658 break;
551c1ca1 6659 case 4:
252b5132
RH		 6660 i.log2_scale_factor = 2;
6661 break;
551c1ca1 6662 case 8:
252b5132
RH		 6663 i.log2_scale_factor = 3;
6664 break;
6665 default:
a724f0f4
JB		 6666 {
6667 char sep = *input_line_pointer;
6668
6669 *input_line_pointer = '\0';
6670 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6671 scale);
6672 *input_line_pointer = sep;
6673 input_line_pointer = save;
6674 return NULL;
6675 }
252b5132 6676 }
29b0f896 6677 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6678 {
6679 as_warn (_("scale factor of %d without an index register"),
24eab124 6680 1 << i.log2_scale_factor);
252b5132 6681 i.log2_scale_factor = 0;
252b5132 6682 }
551c1ca1
AM		 6683 scale = input_line_pointer;
6684 input_line_pointer = save;
6685 return scale;
252b5132
RH		 6686}
6687
252b5132 6688static int
e3bb37b5 6689i386_displacement (char *disp_start, char *disp_end)
252b5132 6690{
29b0f896 6691 expressionS *exp;
252b5132
RH		 6692 segT exp_seg = 0;
6693 char *save_input_line_pointer;
f3c180ae 6694 char *gotfree_input_line;
40fb9820
L		 6695 int override;
6696 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6697 int ret;
252b5132 6698
31b2323c
L		 6699 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6700 {
6701 as_bad (_("at most %d displacement operands are allowed"),
6702 MAX_MEMORY_OPERANDS);
6703 return 0;
6704 }
6705
0dfbf9d7 6706 operand_type_set (&bigdisp, 0);
40fb9820
L		 6707 if ((i.types[this_operand].bitfield.jumpabsolute)
6708 || (!current_templates->start->opcode_modifier.jump
6709 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6710 {
40fb9820 6711 bigdisp.bitfield.disp32 = 1;
e05278af 6712 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6713 if (flag_code == CODE_64BIT)
6714 {
6715 if (!override)
6716 {
6717 bigdisp.bitfield.disp32s = 1;
6718 bigdisp.bitfield.disp64 = 1;
6719 }
6720 }
6721 else if ((flag_code == CODE_16BIT) ^ override)
6722 {
6723 bigdisp.bitfield.disp32 = 0;
6724 bigdisp.bitfield.disp16 = 1;
6725 }
e05278af
JB		 6726 }
6727 else
6728 {
6729 /* For PC-relative branches, the width of the displacement
6730 is dependent upon data size, not address size. */
e05278af 6731 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6732 if (flag_code == CODE_64BIT)
6733 {
6734 if (override || i.suffix == WORD_MNEM_SUFFIX)
6735 bigdisp.bitfield.disp16 = 1;
6736 else
6737 {
6738 bigdisp.bitfield.disp32 = 1;
6739 bigdisp.bitfield.disp32s = 1;
6740 }
6741 }
6742 else
e05278af
JB		 6743 {
6744 if (!override)
6745 override = (i.suffix == (flag_code != CODE_16BIT
6746 ? WORD_MNEM_SUFFIX
6747 : LONG_MNEM_SUFFIX));
40fb9820
L		 6748 bigdisp.bitfield.disp32 = 1;
6749 if ((flag_code == CODE_16BIT) ^ override)
6750 {
6751 bigdisp.bitfield.disp32 = 0;
6752 bigdisp.bitfield.disp16 = 1;
6753 }
e05278af 6754 }
e05278af 6755 }
c6fb90c8
L		 6756 i.types[this_operand] = operand_type_or (i.types[this_operand],
6757 bigdisp);
252b5132
RH		 6758
6759 exp = &disp_expressions[i.disp_operands];
520dc8e8 6760 i.op[this_operand].disps = exp;
252b5132
RH		 6761 i.disp_operands++;
6762 save_input_line_pointer = input_line_pointer;
6763 input_line_pointer = disp_start;
6764 END_STRING_AND_SAVE (disp_end);
6765
6766#ifndef GCC_ASM_O_HACK
6767#define GCC_ASM_O_HACK 0
6768#endif
6769#if GCC_ASM_O_HACK
6770 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6771 if (i.types[this_operand].bitfield.baseIndex
24eab124 6772 && displacement_string_end[-1] == '+')
252b5132
RH		 6773 {
6774 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6775 constraint within gcc asm statements.
6776 For instance:
6777
6778 #define _set_tssldt_desc(n,addr,limit,type) \
6779 __asm__ __volatile__ ( \
6780 "movw %w2,%0\n\t" \
6781 "movw %w1,2+%0\n\t" \
6782 "rorl $16,%1\n\t" \
6783 "movb %b1,4+%0\n\t" \
6784 "movb %4,5+%0\n\t" \
6785 "movb $0,6+%0\n\t" \
6786 "movb %h1,7+%0\n\t" \
6787 "rorl $16,%1" \
6788 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6789
6790 This works great except that the output assembler ends
6791 up looking a bit weird if it turns out that there is
6792 no offset. You end up producing code that looks like:
6793
6794 #APP
6795 movw $235,(%eax)
6796 movw %dx,2+(%eax)
6797 rorl $16,%edx
6798 movb %dl,4+(%eax)
6799 movb $137,5+(%eax)
6800 movb $0,6+(%eax)
6801 movb %dh,7+(%eax)
6802 rorl $16,%edx
6803 #NO_APP
6804
47926f60 6805 So here we provide the missing zero. */
24eab124
AM		 6806
6807 *displacement_string_end = '0';
252b5132
RH		 6808 }
6809#endif
3956db08 6810 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6811 if (gotfree_input_line)
6812 input_line_pointer = gotfree_input_line;
252b5132 6813
24eab124 6814 exp_seg = expression (exp);
252b5132 6815
636c26b0
AM		 6816 SKIP_WHITESPACE ();
6817 if (*input_line_pointer)
6818 as_bad (_("junk `%s' after expression"), input_line_pointer);
6819#if GCC_ASM_O_HACK
6820 RESTORE_END_STRING (disp_end + 1);
6821#endif
636c26b0 6822 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6823 if (gotfree_input_line)
6824 free (gotfree_input_line);
3992d3b7 6825 ret = 1;
636c26b0 6826
24eab124
AM		 6827 /* We do this to make sure that the section symbol is in
6828 the symbol table. We will ultimately change the relocation
47926f60 6829 to be relative to the beginning of the section. */
1ae12ab7 6830 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6831 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6832 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6833 {
636c26b0 6834 if (exp->X_op != O_symbol)
3992d3b7 6835 goto inv_disp;
636c26b0 6836
e5cb08ac 6837 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6838 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6839 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6840 exp->X_op = O_subtract;
6841 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6842 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6843 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6844 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6845 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6846 else
29b0f896 6847 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6848 }
252b5132 6849
3992d3b7
AM		 6850 else if (exp->X_op == O_absent
6851 || exp->X_op == O_illegal
6852 || exp->X_op == O_big
6853 || (gotfree_input_line
6854 && (exp->X_op == O_constant
6855 || exp->X_op == O_register)))
2daf4fd8 6856 {
3992d3b7
AM		 6857 inv_disp:
6858 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6859 disp_start);
3992d3b7 6860 ret = 0;
2daf4fd8
AM		 6861 }
6862
4c63da97 6863#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6864 else if (exp->X_op != O_constant
6865 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6866 && exp_seg != absolute_section
6867 && exp_seg != text_section
6868 && exp_seg != data_section
6869 && exp_seg != bss_section
6870 && exp_seg != undefined_section
6871 && !bfd_is_com_section (exp_seg))
24eab124 6872 {
d0b47220 6873 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6874 ret = 0;
24eab124 6875 }
252b5132 6876#endif
3956db08 6877
3992d3b7
AM		 6878 RESTORE_END_STRING (disp_end);
6879
40fb9820
L		 6880 /* Check if this is a displacement only operand. */
6881 bigdisp = i.types[this_operand];
6882 bigdisp.bitfield.disp8 = 0;
6883 bigdisp.bitfield.disp16 = 0;
6884 bigdisp.bitfield.disp32 = 0;
6885 bigdisp.bitfield.disp32s = 0;
6886 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6887 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6888 i.types[this_operand] = operand_type_and (i.types[this_operand],
6889 types);
3956db08 6890
3992d3b7 6891 return ret;
252b5132
RH		 6892}
6893
eecb386c 6894/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6895 Return 1 on success, 0 on a failure. */
6896
252b5132 6897static int
e3bb37b5 6898i386_index_check (const char *operand_string)
252b5132 6899{
3e73aa7c 6900 int ok;
fc0763e6 6901 const char *kind = "base/index";
24eab124 6902#if INFER_ADDR_PREFIX
eecb386c
AM		 6903 int fudged = 0;
6904
24eab124
AM		 6905 tryprefix:
6906#endif
3e73aa7c 6907 ok = 1;
fc0763e6
JB		 6908 if (current_templates->start->opcode_modifier.isstring
6909 && !current_templates->start->opcode_modifier.immext
6910 && (current_templates->end[-1].opcode_modifier.isstring
6911 || i.mem_operands))
6912 {
6913 /* Memory operands of string insns are special in that they only allow
6914 a single register (rDI, rSI, or rBX) as their memory address. */
6915 unsigned int expected;
6916
6917 kind = "string address";
6918
6919 if (current_templates->start->opcode_modifier.w)
6920 {
6921 i386_operand_type type = current_templates->end[-1].operand_types[0];
6922
6923 if (!type.bitfield.baseindex
6924 || ((!i.mem_operands != !intel_syntax)
6925 && current_templates->end[-1].operand_types[1]
6926 .bitfield.baseindex))
6927 type = current_templates->end[-1].operand_types[1];
6928 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6929 }
6930 else
6931 expected = 3 /* rBX */;
6932
6933 if (!i.base_reg || i.index_reg
6934 || operand_type_check (i.types[this_operand], disp))
6935 ok = -1;
6936 else if (!(flag_code == CODE_64BIT
6937 ? i.prefix[ADDR_PREFIX]
6938 ? i.base_reg->reg_type.bitfield.reg32
6939 : i.base_reg->reg_type.bitfield.reg64
6940 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6941 ? i.base_reg->reg_type.bitfield.reg32
6942 : i.base_reg->reg_type.bitfield.reg16))
6943 ok = 0;
6944 else if (i.base_reg->reg_num != expected)
6945 ok = -1;
6946
6947 if (ok < 0)
6948 {
6949 unsigned int j;
6950
6951 for (j = 0; j < i386_regtab_size; ++j)
6952 if ((flag_code == CODE_64BIT
6953 ? i.prefix[ADDR_PREFIX]
6954 ? i386_regtab[j].reg_type.bitfield.reg32
6955 : i386_regtab[j].reg_type.bitfield.reg64
6956 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6957 ? i386_regtab[j].reg_type.bitfield.reg32
6958 : i386_regtab[j].reg_type.bitfield.reg16)
6959 && i386_regtab[j].reg_num == expected)
6960 break;
6961 assert (j < i386_regtab_size);
6962 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6963 operand_string,
6964 intel_syntax ? '[' : '(',
6965 register_prefix,
6966 i386_regtab[j].reg_name,
6967 intel_syntax ? ']' : ')');
6968 ok = 1;
6969 }
6970 }
6971 else if (flag_code == CODE_64BIT)
64e74474 6972 {
64e74474 6973 if ((i.base_reg
40fb9820
L		 6974 && ((i.prefix[ADDR_PREFIX] == 0
6975 && !i.base_reg->reg_type.bitfield.reg64)
6976 || (i.prefix[ADDR_PREFIX]
6977 && !i.base_reg->reg_type.bitfield.reg32))
6978 && (i.index_reg
9a04903e
JB		 6979 || i.base_reg->reg_num !=
6980 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6981 || (i.index_reg
40fb9820
L		 6982 && (!i.index_reg->reg_type.bitfield.baseindex
6983 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6984 && i.index_reg->reg_num != RegRiz
6985 && !i.index_reg->reg_type.bitfield.reg64
6986 )
40fb9820 6987 || (i.prefix[ADDR_PREFIX]
db51cc60 6988 && i.index_reg->reg_num != RegEiz
40fb9820 6989 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6990 ok = 0;
3e73aa7c
JH		 6991 }
6992 else
6993 {
6994 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6995 {
6996 /* 16bit checks. */
6997 if ((i.base_reg
40fb9820
L		 6998 && (!i.base_reg->reg_type.bitfield.reg16
6999 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7000 || (i.index_reg
40fb9820
L		 7001 && (!i.index_reg->reg_type.bitfield.reg16
7002 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7003 || !(i.base_reg
7004 && i.base_reg->reg_num < 6
7005 && i.index_reg->reg_num >= 6
7006 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7007 ok = 0;
7008 }
7009 else
e5cb08ac 7010 {
3e73aa7c
JH		 7011 /* 32bit checks. */
7012 if ((i.base_reg
40fb9820 7013 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7014 || (i.index_reg
db51cc60
L		 7015 && ((!i.index_reg->reg_type.bitfield.reg32
7016 && i.index_reg->reg_num != RegEiz)
40fb9820 7017 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7018 ok = 0;
3e73aa7c
JH		 7019 }
7020 }
7021 if (!ok)
24eab124
AM		 7022 {
7023#if INFER_ADDR_PREFIX
fc0763e6 7024 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7025 {
7026 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7027 i.prefixes += 1;
b23bac36
AM		 7028 /* Change the size of any displacement too. At most one of
7029 Disp16 or Disp32 is set.
7030 FIXME. There doesn't seem to be any real need for separate
7031 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7032 Removing them would probably clean up the code quite a lot. */
4eed87de 7033 if (flag_code != CODE_64BIT
40fb9820
L		 7034 && (i.types[this_operand].bitfield.disp16
7035 || i.types[this_operand].bitfield.disp32))
7036 i.types[this_operand]
c6fb90c8 7037 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7038 fudged = 1;
24eab124
AM		 7039 goto tryprefix;
7040 }
eecb386c 7041 if (fudged)
fc0763e6
JB		 7042 as_bad (_("`%s' is not a valid %s expression"),
7043 operand_string,
7044 kind);
eecb386c 7045 else
c388dee8 7046#endif
fc0763e6 7047 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7048 operand_string,
fc0763e6
JB		 7049 flag_code_names[i.prefix[ADDR_PREFIX]
7050 ? flag_code == CODE_32BIT
7051 ? CODE_16BIT
7052 : CODE_32BIT
7053 : flag_code],
7054 kind);
24eab124 7055 }
20f0a1fc 7056 return ok;
24eab124 7057}
252b5132 7058
fc0763e6 7059/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7060 on error. */
252b5132 7061
252b5132 7062static int
a7619375 7063i386_att_operand (char *operand_string)
252b5132 7064{
af6bdddf
AM		 7065 const reg_entry *r;
7066 char *end_op;
24eab124 7067 char *op_string = operand_string;
252b5132 7068
24eab124 7069 if (is_space_char (*op_string))
252b5132
RH		 7070 ++op_string;
7071
24eab124 7072 /* We check for an absolute prefix (differentiating,
47926f60 7073 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7074 if (*op_string == ABSOLUTE_PREFIX)
7075 {
7076 ++op_string;
7077 if (is_space_char (*op_string))
7078 ++op_string;
40fb9820 7079 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7080 }
252b5132 7081
47926f60 7082 /* Check if operand is a register. */
4d1bb795 7083 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7084 {
40fb9820
L		 7085 i386_operand_type temp;
7086
24eab124
AM		 7087 /* Check for a segment override by searching for ':' after a
7088 segment register. */
7089 op_string = end_op;
7090 if (is_space_char (*op_string))
7091 ++op_string;
40fb9820
L		 7092 if (*op_string == ':'
7093 && (r->reg_type.bitfield.sreg2
7094 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7095 {
7096 switch (r->reg_num)
7097 {
7098 case 0:
7099 i.seg[i.mem_operands] = &es;
7100 break;
7101 case 1:
7102 i.seg[i.mem_operands] = &cs;
7103 break;
7104 case 2:
7105 i.seg[i.mem_operands] = &ss;
7106 break;
7107 case 3:
7108 i.seg[i.mem_operands] = &ds;
7109 break;
7110 case 4:
7111 i.seg[i.mem_operands] = &fs;
7112 break;
7113 case 5:
7114 i.seg[i.mem_operands] = &gs;
7115 break;
7116 }
252b5132 7117
24eab124 7118 /* Skip the ':' and whitespace. */
252b5132
RH		 7119 ++op_string;
7120 if (is_space_char (*op_string))
24eab124 7121 ++op_string;
252b5132 7122
24eab124
AM		 7123 if (!is_digit_char (*op_string)
7124 && !is_identifier_char (*op_string)
7125 && *op_string != '('
7126 && *op_string != ABSOLUTE_PREFIX)
7127 {
7128 as_bad (_("bad memory operand `%s'"), op_string);
7129 return 0;
7130 }
47926f60 7131 /* Handle case of %es:*foo. */
24eab124
AM		 7132 if (*op_string == ABSOLUTE_PREFIX)
7133 {
7134 ++op_string;
7135 if (is_space_char (*op_string))
7136 ++op_string;
40fb9820 7137 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7138 }
7139 goto do_memory_reference;
7140 }
7141 if (*op_string)
7142 {
d0b47220 7143 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7144 return 0;
7145 }
40fb9820
L		 7146 temp = r->reg_type;
7147 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7148 i.types[this_operand] = operand_type_or (i.types[this_operand],
7149 temp);
7d5e4556 7150 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7151 i.op[this_operand].regs = r;
24eab124
AM		 7152 i.reg_operands++;
7153 }
af6bdddf
AM		 7154 else if (*op_string == REGISTER_PREFIX)
7155 {
7156 as_bad (_("bad register name `%s'"), op_string);
7157 return 0;
7158 }
24eab124 7159 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7160 {
24eab124 7161 ++op_string;
40fb9820 7162 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7163 {
d0b47220 7164 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7165 return 0;
7166 }
7167 if (!i386_immediate (op_string))
7168 return 0;
7169 }
7170 else if (is_digit_char (*op_string)
7171 || is_identifier_char (*op_string)
e5cb08ac 7172 || *op_string == '(')
24eab124 7173 {
47926f60 7174 /* This is a memory reference of some sort. */
af6bdddf 7175 char *base_string;
252b5132 7176
47926f60 7177 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7178 char *displacement_string_start;
7179 char *displacement_string_end;
252b5132 7180
24eab124 7181 do_memory_reference:
24eab124 7182 if ((i.mem_operands == 1
40fb9820 7183 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7184 || i.mem_operands == 2)
7185 {
7186 as_bad (_("too many memory references for `%s'"),
7187 current_templates->start->name);
7188 return 0;
7189 }
252b5132 7190
24eab124
AM		 7191 /* Check for base index form. We detect the base index form by
7192 looking for an ')' at the end of the operand, searching
7193 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7194 after the '('. */
af6bdddf 7195 base_string = op_string + strlen (op_string);
c3332e24 7196
af6bdddf
AM		 7197 --base_string;
7198 if (is_space_char (*base_string))
7199 --base_string;
252b5132 7200
47926f60 7201 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7202 displacement_string_start = op_string;
7203 displacement_string_end = base_string + 1;
252b5132 7204
24eab124
AM		 7205 if (*base_string == ')')
7206 {
af6bdddf 7207 char *temp_string;
24eab124
AM		 7208 unsigned int parens_balanced = 1;
7209 /* We've already checked that the number of left & right ()'s are
47926f60 7210 equal, so this loop will not be infinite. */
24eab124
AM		 7211 do
7212 {
7213 base_string--;
7214 if (*base_string == ')')
7215 parens_balanced++;
7216 if (*base_string == '(')
7217 parens_balanced--;
7218 }
7219 while (parens_balanced);
c3332e24 7220
af6bdddf 7221 temp_string = base_string;
c3332e24 7222
24eab124 7223 /* Skip past '(' and whitespace. */
252b5132
RH		 7224 ++base_string;
7225 if (is_space_char (*base_string))
24eab124 7226 ++base_string;
252b5132 7227
af6bdddf 7228 if (*base_string == ','
4eed87de
AM		 7229 || ((i.base_reg = parse_register (base_string, &end_op))
7230 != NULL))
252b5132 7231 {
af6bdddf 7232 displacement_string_end = temp_string;
252b5132 7233
40fb9820 7234 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7235
af6bdddf 7236 if (i.base_reg)
24eab124 7237 {
24eab124
AM		 7238 base_string = end_op;
7239 if (is_space_char (*base_string))
7240 ++base_string;
af6bdddf
AM		 7241 }
7242
7243 /* There may be an index reg or scale factor here. */
7244 if (*base_string == ',')
7245 {
7246 ++base_string;
7247 if (is_space_char (*base_string))
7248 ++base_string;
7249
4eed87de
AM		 7250 if ((i.index_reg = parse_register (base_string, &end_op))
7251 != NULL)
24eab124 7252 {
af6bdddf 7253 base_string = end_op;
24eab124
AM		 7254 if (is_space_char (*base_string))
7255 ++base_string;
af6bdddf
AM		 7256 if (*base_string == ',')
7257 {
7258 ++base_string;
7259 if (is_space_char (*base_string))
7260 ++base_string;
7261 }
e5cb08ac 7262 else if (*base_string != ')')
af6bdddf 7263 {
4eed87de
AM		 7264 as_bad (_("expecting `,' or `)' "
7265 "after index register in `%s'"),
af6bdddf
AM		 7266 operand_string);
7267 return 0;
7268 }
24eab124 7269 }
af6bdddf 7270 else if (*base_string == REGISTER_PREFIX)
24eab124 7271 {
af6bdddf 7272 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7273 return 0;
7274 }
252b5132 7275
47926f60 7276 /* Check for scale factor. */
551c1ca1 7277 if (*base_string != ')')
af6bdddf 7278 {
551c1ca1
AM		 7279 char *end_scale = i386_scale (base_string);
7280
7281 if (!end_scale)
af6bdddf 7282 return 0;
24eab124 7283
551c1ca1 7284 base_string = end_scale;
af6bdddf
AM		 7285 if (is_space_char (*base_string))
7286 ++base_string;
7287 if (*base_string != ')')
7288 {
4eed87de
AM		 7289 as_bad (_("expecting `)' "
7290 "after scale factor in `%s'"),
af6bdddf
AM		 7291 operand_string);
7292 return 0;
7293 }
7294 }
7295 else if (!i.index_reg)
24eab124 7296 {
4eed87de
AM		 7297 as_bad (_("expecting index register or scale factor "
7298 "after `,'; got '%c'"),
af6bdddf 7299 *base_string);
24eab124
AM		 7300 return 0;
7301 }
7302 }
af6bdddf 7303 else if (*base_string != ')')
24eab124 7304 {
4eed87de
AM		 7305 as_bad (_("expecting `,' or `)' "
7306 "after base register in `%s'"),
af6bdddf 7307 operand_string);
24eab124
AM		 7308 return 0;
7309 }
c3332e24 7310 }
af6bdddf 7311 else if (*base_string == REGISTER_PREFIX)
c3332e24 7312 {
af6bdddf 7313 as_bad (_("bad register name `%s'"), base_string);
24eab124 7314 return 0;
c3332e24 7315 }
24eab124
AM		 7316 }
7317
7318 /* If there's an expression beginning the operand, parse it,
7319 assuming displacement_string_start and
7320 displacement_string_end are meaningful. */
7321 if (displacement_string_start != displacement_string_end)
7322 {
7323 if (!i386_displacement (displacement_string_start,
7324 displacement_string_end))
7325 return 0;
7326 }
7327
7328 /* Special case for (%dx) while doing input/output op. */
7329 if (i.base_reg
0dfbf9d7
L		 7330 && operand_type_equal (&i.base_reg->reg_type,
7331 &reg16_inoutportreg)
24eab124
AM		 7332 && i.index_reg == 0
7333 && i.log2_scale_factor == 0
7334 && i.seg[i.mem_operands] == 0
40fb9820 7335 && !operand_type_check (i.types[this_operand], disp))
24eab124 7336 {
65da13b5 7337 i.types[this_operand] = inoutportreg;
24eab124
AM		 7338 return 1;
7339 }
7340
eecb386c
AM		 7341 if (i386_index_check (operand_string) == 0)
7342 return 0;
5c07affc 7343 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7344 i.mem_operands++;
7345 }
7346 else
ce8a8b2f
AM		 7347 {
7348 /* It's not a memory operand; argh! */
24eab124
AM		 7349 as_bad (_("invalid char %s beginning operand %d `%s'"),
7350 output_invalid (*op_string),
7351 this_operand + 1,
7352 op_string);
7353 return 0;
7354 }
47926f60 7355 return 1; /* Normal return. */
252b5132
RH		 7356}
7357\f
ee7fcc42
AM		 7358/* md_estimate_size_before_relax()
7359
7360 Called just before relax() for rs_machine_dependent frags. The x86
7361 assembler uses these frags to handle variable size jump
7362 instructions.
7363
7364 Any symbol that is now undefined will not become defined.
7365 Return the correct fr_subtype in the frag.
7366 Return the initial "guess for variable size of frag" to caller.
7367 The guess is actually the growth beyond the fixed part. Whatever
7368 we do to grow the fixed or variable part contributes to our
7369 returned value. */
7370
252b5132
RH		 7371int
7372md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7373 fragS *fragP;
7374 segT segment;
252b5132 7375{
252b5132 7376 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7377 check for un-relaxable symbols. On an ELF system, we can't relax
7378 an externally visible symbol, because it may be overridden by a
7379 shared library. */
7380 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7381#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7382 || (IS_ELF
31312f95
AM		 7383 && (S_IS_EXTERNAL (fragP->fr_symbol)
7384 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 7385#endif
7386 )
252b5132 7387 {
b98ef147
AM		 7388 /* Symbol is undefined in this segment, or we need to keep a
7389 reloc so that weak symbols can be overridden. */
7390 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7391 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7392 unsigned char *opcode;
7393 int old_fr_fix;
f6af82bd 7394
ee7fcc42
AM		 7395 if (fragP->fr_var != NO_RELOC)
7396 reloc_type = fragP->fr_var;
b98ef147 7397 else if (size == 2)
f6af82bd
AM		 7398 reloc_type = BFD_RELOC_16_PCREL;
7399 else
7400 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7401
ee7fcc42
AM		 7402 old_fr_fix = fragP->fr_fix;
7403 opcode = (unsigned char *) fragP->fr_opcode;
7404
fddf5b5b 7405 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7406 {
fddf5b5b
AM		 7407 case UNCOND_JUMP:
7408 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7409 opcode[0] = 0xe9;
252b5132 7410 fragP->fr_fix += size;
062cd5e7
AS		 7411 fix_new (fragP, old_fr_fix, size,
7412 fragP->fr_symbol,
7413 fragP->fr_offset, 1,
7414 reloc_type);
252b5132
RH		 7415 break;
7416
fddf5b5b 7417 case COND_JUMP86:
412167cb
AM		 7418 if (size == 2
7419 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7420 {
7421 /* Negate the condition, and branch past an
7422 unconditional jump. */
7423 opcode[0] ^= 1;
7424 opcode[1] = 3;
7425 /* Insert an unconditional jump. */
7426 opcode[2] = 0xe9;
7427 /* We added two extra opcode bytes, and have a two byte
7428 offset. */
7429 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7430 fix_new (fragP, old_fr_fix + 2, 2,
7431 fragP->fr_symbol,
7432 fragP->fr_offset, 1,
7433 reloc_type);
fddf5b5b
AM		 7434 break;
7435 }
7436 /* Fall through. */
7437
7438 case COND_JUMP:
412167cb
AM		 7439 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7440 {
3e02c1cc
AM		 7441 fixS *fixP;
7442
412167cb 7443 fragP->fr_fix += 1;
3e02c1cc
AM		 7444 fixP = fix_new (fragP, old_fr_fix, 1,
7445 fragP->fr_symbol,
7446 fragP->fr_offset, 1,
7447 BFD_RELOC_8_PCREL);
7448 fixP->fx_signed = 1;
412167cb
AM		 7449 break;
7450 }
93c2a809 7451
24eab124 7452 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7453 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7454 opcode[1] = opcode[0] + 0x10;
f6af82bd 7455 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7456 /* We've added an opcode byte. */
7457 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7458 fix_new (fragP, old_fr_fix + 1, size,
7459 fragP->fr_symbol,
7460 fragP->fr_offset, 1,
7461 reloc_type);
252b5132 7462 break;
fddf5b5b
AM		 7463
7464 default:
7465 BAD_CASE (fragP->fr_subtype);
7466 break;
252b5132
RH		 7467 }
7468 frag_wane (fragP);
ee7fcc42 7469 return fragP->fr_fix - old_fr_fix;
252b5132 7470 }
93c2a809 7471
93c2a809
AM		 7472 /* Guess size depending on current relax state. Initially the relax
7473 state will correspond to a short jump and we return 1, because
7474 the variable part of the frag (the branch offset) is one byte
7475 long. However, we can relax a section more than once and in that
7476 case we must either set fr_subtype back to the unrelaxed state,
7477 or return the value for the appropriate branch. */
7478 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7479}
7480
47926f60
KH		 7481/* Called after relax() is finished.
7482
7483 In: Address of frag.
7484 fr_type == rs_machine_dependent.
7485 fr_subtype is what the address relaxed to.
7486
7487 Out: Any fixSs and constants are set up.
7488 Caller will turn frag into a ".space 0". */
7489
252b5132
RH		 7490void
7491md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7492 bfd *abfd ATTRIBUTE_UNUSED;
7493 segT sec ATTRIBUTE_UNUSED;
29b0f896 7494 fragS *fragP;
252b5132 7495{
29b0f896 7496 unsigned char *opcode;
252b5132 7497 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7498 offsetT target_address;
7499 offsetT opcode_address;
252b5132 7500 unsigned int extension = 0;
847f7ad4 7501 offsetT displacement_from_opcode_start;
252b5132
RH		 7502
7503 opcode = (unsigned char *) fragP->fr_opcode;
7504
47926f60 7505 /* Address we want to reach in file space. */
252b5132 7506 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7507
47926f60 7508 /* Address opcode resides at in file space. */
252b5132
RH		 7509 opcode_address = fragP->fr_address + fragP->fr_fix;
7510
47926f60 7511 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7512 displacement_from_opcode_start = target_address - opcode_address;
7513
fddf5b5b 7514 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7515 {
47926f60
KH		 7516 /* Don't have to change opcode. */
7517 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7518 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7519 }
7520 else
7521 {
7522 if (no_cond_jump_promotion
7523 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7524 as_warn_where (fragP->fr_file, fragP->fr_line,
7525 _("long jump required"));
252b5132 7526
fddf5b5b
AM		 7527 switch (fragP->fr_subtype)
7528 {
7529 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7530 extension = 4; /* 1 opcode + 4 displacement */
7531 opcode[0] = 0xe9;
7532 where_to_put_displacement = &opcode[1];
7533 break;
252b5132 7534
fddf5b5b
AM		 7535 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7536 extension = 2; /* 1 opcode + 2 displacement */
7537 opcode[0] = 0xe9;
7538 where_to_put_displacement = &opcode[1];
7539 break;
252b5132 7540
fddf5b5b
AM		 7541 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7542 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7543 extension = 5; /* 2 opcode + 4 displacement */
7544 opcode[1] = opcode[0] + 0x10;
7545 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7546 where_to_put_displacement = &opcode[2];
7547 break;
252b5132 7548
fddf5b5b
AM		 7549 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7550 extension = 3; /* 2 opcode + 2 displacement */
7551 opcode[1] = opcode[0] + 0x10;
7552 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7553 where_to_put_displacement = &opcode[2];
7554 break;
252b5132 7555
fddf5b5b
AM		 7556 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7557 extension = 4;
7558 opcode[0] ^= 1;
7559 opcode[1] = 3;
7560 opcode[2] = 0xe9;
7561 where_to_put_displacement = &opcode[3];
7562 break;
7563
7564 default:
7565 BAD_CASE (fragP->fr_subtype);
7566 break;
7567 }
252b5132 7568 }
fddf5b5b 7569
7b81dfbb
AJ		 7570 /* If size if less then four we are sure that the operand fits,
7571 but if it's 4, then it could be that the displacement is larger
7572 then -/+ 2GB. */
7573 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7574 && object_64bit
7575 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7576 + ((addressT) 1 << 31))
7577 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7578 {
7579 as_bad_where (fragP->fr_file, fragP->fr_line,
7580 _("jump target out of range"));
7581 /* Make us emit 0. */
7582 displacement_from_opcode_start = extension;
7583 }
47926f60 7584 /* Now put displacement after opcode. */
252b5132
RH		 7585 md_number_to_chars ((char *) where_to_put_displacement,
7586 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7587 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7588 fragP->fr_fix += extension;
7589}
7590\f
252b5132
RH		 7591/* Apply a fixup (fixS) to segment data, once it has been determined
7592 by our caller that we have all the info we need to fix it up.
7593
7594 On the 386, immediates, displacements, and data pointers are all in
7595 the same (little-endian) format, so we don't need to care about which
7596 we are handling. */
7597
94f592af 7598void
55cf6793 7599md_apply_fix (fixP, valP, seg)
47926f60
KH		 7600 /* The fix we're to put in. */
7601 fixS *fixP;
47926f60 7602 /* Pointer to the value of the bits. */
c6682705 7603 valueT *valP;
47926f60
KH		 7604 /* Segment fix is from. */
7605 segT seg ATTRIBUTE_UNUSED;
252b5132 7606{
94f592af 7607 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7608 valueT value = *valP;
252b5132 7609
f86103b7 7610#if !defined (TE_Mach)
93382f6d
AM		 7611 if (fixP->fx_pcrel)
7612 {
7613 switch (fixP->fx_r_type)
7614 {
5865bb77
ILT		 7615 default:
7616 break;
7617
d6ab8113
JB		 7618 case BFD_RELOC_64:
7619 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7620 break;
93382f6d 7621 case BFD_RELOC_32:
ae8887b5 7622 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7623 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7624 break;
7625 case BFD_RELOC_16:
7626 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7627 break;
7628 case BFD_RELOC_8:
7629 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7630 break;
7631 }
7632 }
252b5132 7633
a161fe53 7634 if (fixP->fx_addsy != NULL
31312f95 7635 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7636 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7637 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7638 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7639 && !use_rela_relocations)
252b5132 7640 {
31312f95
AM		 7641 /* This is a hack. There should be a better way to handle this.
7642 This covers for the fact that bfd_install_relocation will
7643 subtract the current location (for partial_inplace, PC relative
7644 relocations); see more below. */
252b5132 7645#ifndef OBJ_AOUT
718ddfc0 7646 if (IS_ELF
252b5132
RH		 7647#ifdef TE_PE
7648 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7649#endif
7650 )
7651 value += fixP->fx_where + fixP->fx_frag->fr_address;
7652#endif
7653#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7654 if (IS_ELF)
252b5132 7655 {
6539b54b 7656 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7657
6539b54b 7658 if ((sym_seg == seg
2f66722d 7659 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7660 && sym_seg != absolute_section))
ae6063d4 7661 && !generic_force_reloc (fixP))
2f66722d
AM		 7662 {
7663 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7664 bfd_install_relocation subtracts them out again. I think
7665 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7666 it. FIXME. */
7667 value += fixP->fx_where + fixP->fx_frag->fr_address;
7668 }
252b5132
RH		 7669 }
7670#endif
7671#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7672 /* For some reason, the PE format does not store a
7673 section address offset for a PC relative symbol. */
7674 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7675 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7676 value += md_pcrel_from (fixP);
7677#endif
7678 }
7679
7680 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7681 and we must not disappoint it. */
252b5132 7682#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7683 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7684 switch (fixP->fx_r_type)
7685 {
7686 case BFD_RELOC_386_PLT32:
3e73aa7c 7687 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7688 /* Make the jump instruction point to the address of the operand. At
7689 runtime we merely add the offset to the actual PLT entry. */
7690 value = -4;
7691 break;
31312f95 7692
13ae64f3
JJ		 7693 case BFD_RELOC_386_TLS_GD:
7694 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7695 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7696 case BFD_RELOC_386_TLS_IE:
7697 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7698 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7699 case BFD_RELOC_X86_64_TLSGD:
7700 case BFD_RELOC_X86_64_TLSLD:
7701 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7702 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7703 value = 0; /* Fully resolved at runtime. No addend. */
7704 /* Fallthrough */
7705 case BFD_RELOC_386_TLS_LE:
7706 case BFD_RELOC_386_TLS_LDO_32:
7707 case BFD_RELOC_386_TLS_LE_32:
7708 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7709 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7710 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7711 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7712 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7713 break;
7714
67a4f2b7
AO		 7715 case BFD_RELOC_386_TLS_DESC_CALL:
7716 case BFD_RELOC_X86_64_TLSDESC_CALL:
7717 value = 0; /* Fully resolved at runtime. No addend. */
7718 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7719 fixP->fx_done = 0;
7720 return;
7721
00f7efb6
JJ		 7722 case BFD_RELOC_386_GOT32:
7723 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7724 value = 0; /* Fully resolved at runtime. No addend. */
7725 break;
47926f60
KH		 7726
7727 case BFD_RELOC_VTABLE_INHERIT:
7728 case BFD_RELOC_VTABLE_ENTRY:
7729 fixP->fx_done = 0;
94f592af 7730 return;
47926f60
KH		 7731
7732 default:
7733 break;
7734 }
7735#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7736 *valP = value;
f86103b7 7737#endif /* !defined (TE_Mach) */
3e73aa7c 7738
3e73aa7c 7739 /* Are we finished with this relocation now? */
c6682705 7740 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7741 fixP->fx_done = 1;
7742 else if (use_rela_relocations)
7743 {
7744 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7745 /* Remember value for tc_gen_reloc. */
7746 fixP->fx_addnumber = value;
3e73aa7c
JH		 7747 value = 0;
7748 }
f86103b7 7749
94f592af 7750 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7751}
252b5132 7752\f
252b5132 7753char *
499ac353 7754md_atof (int type, char *litP, int *sizeP)
252b5132 7755{
499ac353
NC		 7756 /* This outputs the LITTLENUMs in REVERSE order;
7757 in accord with the bigendian 386. */
7758 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7759}
7760\f
2d545b82 7761static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7762
252b5132 7763static char *
e3bb37b5 7764output_invalid (int c)
252b5132 7765{
3882b010 7766 if (ISPRINT (c))
f9f21a03
L		 7767 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7768 "'%c'", c);
252b5132 7769 else
f9f21a03 7770 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7771 "(0x%x)", (unsigned char) c);
252b5132
RH		 7772 return output_invalid_buf;
7773}
7774
af6bdddf 7775/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7776
7777static const reg_entry *
4d1bb795 7778parse_real_register (char *reg_string, char **end_op)
252b5132 7779{
af6bdddf
AM		 7780 char *s = reg_string;
7781 char *p;
252b5132
RH		 7782 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7783 const reg_entry *r;
7784
7785 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7786 if (*s == REGISTER_PREFIX)
7787 ++s;
7788
7789 if (is_space_char (*s))
7790 ++s;
7791
7792 p = reg_name_given;
af6bdddf 7793 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7794 {
7795 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7796 return (const reg_entry *) NULL;
7797 s++;
252b5132
RH		 7798 }
7799
6588847e
DN		 7800 /* For naked regs, make sure that we are not dealing with an identifier.
7801 This prevents confusing an identifier like `eax_var' with register
7802 `eax'. */
7803 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7804 return (const reg_entry *) NULL;
7805
af6bdddf 7806 *end_op = s;
252b5132
RH		 7807
7808 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7809
5f47d35b 7810 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7811 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7812 {
5f47d35b
AM		 7813 if (is_space_char (*s))
7814 ++s;
7815 if (*s == '(')
7816 {
af6bdddf 7817 ++s;
5f47d35b
AM		 7818 if (is_space_char (*s))
7819 ++s;
7820 if (*s >= '0' && *s <= '7')
7821 {
db557034 7822 int fpr = *s - '0';
af6bdddf 7823 ++s;
5f47d35b
AM		 7824 if (is_space_char (*s))
7825 ++s;
7826 if (*s == ')')
7827 {
7828 *end_op = s + 1;
db557034
AM		 7829 r = hash_find (reg_hash, "st(0)");
7830 know (r);
7831 return r + fpr;
5f47d35b 7832 }
5f47d35b 7833 }
47926f60 7834 /* We have "%st(" then garbage. */
5f47d35b
AM		 7835 return (const reg_entry *) NULL;
7836 }
7837 }
7838
a60de03c
JB		 7839 if (r == NULL || allow_pseudo_reg)
7840 return r;
7841
0dfbf9d7 7842 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7843 return (const reg_entry *) NULL;
7844
192dc9c6
JB		 7845 if ((r->reg_type.bitfield.reg32
7846 || r->reg_type.bitfield.sreg3
7847 || r->reg_type.bitfield.control
7848 || r->reg_type.bitfield.debug
7849 || r->reg_type.bitfield.test)
7850 && !cpu_arch_flags.bitfield.cpui386)
7851 return (const reg_entry *) NULL;
7852
7853 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7854 return (const reg_entry *) NULL;
7855
7856 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7857 return (const reg_entry *) NULL;
7858
40f12533
L		 7859 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7860 return (const reg_entry *) NULL;
7861
db51cc60 7862 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7863 if (!allow_index_reg
db51cc60
L		 7864 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7865 return (const reg_entry *) NULL;
7866
a60de03c
JB		 7867 if (((r->reg_flags & (RegRex64 | RegRex))
7868 || r->reg_type.bitfield.reg64)
40fb9820 7869 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7870 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7871 && flag_code != CODE_64BIT)
20f0a1fc 7872 return (const reg_entry *) NULL;
1ae00879 7873
b7240065
JB		 7874 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7875 return (const reg_entry *) NULL;
7876
252b5132
RH		 7877 return r;
7878}
4d1bb795
JB		 7879
7880/* REG_STRING starts *before* REGISTER_PREFIX. */
7881
7882static const reg_entry *
7883parse_register (char *reg_string, char **end_op)
7884{
7885 const reg_entry *r;
7886
7887 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7888 r = parse_real_register (reg_string, end_op);
7889 else
7890 r = NULL;
7891 if (!r)
7892 {
7893 char *save = input_line_pointer;
7894 char c;
7895 symbolS *symbolP;
7896
7897 input_line_pointer = reg_string;
7898 c = get_symbol_end ();
7899 symbolP = symbol_find (reg_string);
7900 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7901 {
7902 const expressionS *e = symbol_get_value_expression (symbolP);
7903
7904 know (e->X_op == O_register);
4eed87de 7905 know (e->X_add_number >= 0
c3fe08fa 7906 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7907 r = i386_regtab + e->X_add_number;
7908 *end_op = input_line_pointer;
7909 }
7910 *input_line_pointer = c;
7911 input_line_pointer = save;
7912 }
7913 return r;
7914}
7915
7916int
7917i386_parse_name (char *name, expressionS *e, char *nextcharP)
7918{
7919 const reg_entry *r;
7920 char *end = input_line_pointer;
7921
7922 *end = *nextcharP;
7923 r = parse_register (name, &input_line_pointer);
7924 if (r && end <= input_line_pointer)
7925 {
7926 *nextcharP = *input_line_pointer;
7927 *input_line_pointer = 0;
7928 e->X_op = O_register;
7929 e->X_add_number = r - i386_regtab;
7930 return 1;
7931 }
7932 input_line_pointer = end;
7933 *end = 0;
7934 return 0;
7935}
7936
7937void
7938md_operand (expressionS *e)
7939{
7940 if (*input_line_pointer == REGISTER_PREFIX)
7941 {
7942 char *end;
7943 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7944
7945 if (r)
7946 {
7947 e->X_op = O_register;
7948 e->X_add_number = r - i386_regtab;
7949 input_line_pointer = end;
7950 }
7951 }
7952}
7953
252b5132 7954\f
4cc782b5 7955#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7956const char *md_shortopts = "kVQ:sqn";
252b5132 7957#else
12b55ccc 7958const char *md_shortopts = "qn";
252b5132 7959#endif
6e0b89ee 7960
3e73aa7c 7961#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7962#define OPTION_64 (OPTION_MD_BASE + 1)
7963#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7964#define OPTION_MARCH (OPTION_MD_BASE + 3)
7965#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7966#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7967#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7968#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7969#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7970#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7971#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7972#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7973
99ad8390
NC		 7974struct option md_longopts[] =
7975{
3e73aa7c 7976 {"32", no_argument, NULL, OPTION_32},
99ad8390 7977#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7978 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7979#endif
b3b91714 7980 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7981 {"march", required_argument, NULL, OPTION_MARCH},
7982 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7983 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7984 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7985 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7986 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7987 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7988 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7989 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7990 {NULL, no_argument, NULL, 0}
7991};
7992size_t md_longopts_size = sizeof (md_longopts);
7993
7994int
9103f4f4 7995md_parse_option (int c, char *arg)
252b5132 7996{
9103f4f4 7997 unsigned int i;
6305a203 7998 char *arch, *next;
9103f4f4 7999
252b5132
RH		 8000 switch (c)
8001 {
12b55ccc
L		 8002 case 'n':
8003 optimize_align_code = 0;
8004 break;
8005
a38cf1db
AM		 8006 case 'q':
8007 quiet_warnings = 1;
252b5132
RH		 8008 break;
8009
8010#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8011 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8012 should be emitted or not. FIXME: Not implemented. */
8013 case 'Q':
252b5132
RH		 8014 break;
8015
8016 /* -V: SVR4 argument to print version ID. */
8017 case 'V':
8018 print_version_id ();
8019 break;
8020
a38cf1db
AM		 8021 /* -k: Ignore for FreeBSD compatibility. */
8022 case 'k':
252b5132 8023 break;
4cc782b5
ILT		 8024
8025 case 's':
8026 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8027 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8028 break;
99ad8390
NC		 8029#endif
8030#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 8031 case OPTION_64:
8032 {
8033 const char **list, **l;
8034
3e73aa7c
JH		 8035 list = bfd_target_list ();
8036 for (l = list; *l != NULL; l++)
8620418b 8037 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8038 || strcmp (*l, "coff-x86-64") == 0
8039 || strcmp (*l, "pe-x86-64") == 0
8040 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8041 {
8042 default_arch = "x86_64";
8043 break;
8044 }
3e73aa7c 8045 if (*l == NULL)
6e0b89ee 8046 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8047 free (list);
8048 }
8049 break;
8050#endif
252b5132 8051
6e0b89ee
AM		 8052 case OPTION_32:
8053 default_arch = "i386";
8054 break;
8055
b3b91714
AM		 8056 case OPTION_DIVIDE:
8057#ifdef SVR4_COMMENT_CHARS
8058 {
8059 char *n, *t;
8060 const char *s;
8061
8062 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8063 t = n;
8064 for (s = i386_comment_chars; *s != '\0'; s++)
8065 if (*s != '/')
8066 *t++ = *s;
8067 *t = '\0';
8068 i386_comment_chars = n;
8069 }
8070#endif
8071 break;
8072
9103f4f4 8073 case OPTION_MARCH:
6305a203
L		 8074 arch = xstrdup (arg);
8075 do
9103f4f4 8076 {
6305a203
L		 8077 if (*arch == '.')
8078 as_fatal (_("Invalid -march= option: `%s'"), arg);
8079 next = strchr (arch, '+');
8080 if (next)
8081 *next++ = '\0';
8082 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 8083 {
6305a203 8084 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 8085 {
6305a203
L		 8086 /* Processor. */
8087 cpu_arch_name = cpu_arch[i].name;
8088 cpu_sub_arch_name = NULL;
8089 cpu_arch_flags = cpu_arch[i].flags;
8090 cpu_arch_isa = cpu_arch[i].type;
8091 cpu_arch_isa_flags = cpu_arch[i].flags;
8092 if (!cpu_arch_tune_set)
8093 {
8094 cpu_arch_tune = cpu_arch_isa;
8095 cpu_arch_tune_flags = cpu_arch_isa_flags;
8096 }
8097 break;
8098 }
8099 else if (*cpu_arch [i].name == '.'
8100 && strcmp (arch, cpu_arch [i].name + 1) == 0)
8101 {
8102 /* ISA entension. */
8103 i386_cpu_flags flags;
8104 flags = cpu_flags_or (cpu_arch_flags,
8105 cpu_arch[i].flags);
0dfbf9d7 8106 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8107 {
8108 if (cpu_sub_arch_name)
8109 {
8110 char *name = cpu_sub_arch_name;
8111 cpu_sub_arch_name = concat (name,
8112 cpu_arch[i].name,
1bf57e9f 8113 (const char *) NULL);
6305a203
L		 8114 free (name);
8115 }
8116 else
8117 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8118 cpu_arch_flags = flags;
8119 }
8120 break;
ccc9c027 8121 }
9103f4f4 8122 }
6305a203
L		 8123
8124 if (i >= ARRAY_SIZE (cpu_arch))
8125 as_fatal (_("Invalid -march= option: `%s'"), arg);
8126
8127 arch = next;
9103f4f4 8128 }
6305a203 8129 while (next != NULL );
9103f4f4
L		 8130 break;
8131
8132 case OPTION_MTUNE:
8133 if (*arg == '.')
8134 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8135 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8136 {
8137 if (strcmp (arg, cpu_arch [i].name) == 0)
8138 {
ccc9c027 8139 cpu_arch_tune_set = 1;
9103f4f4
L		 8140 cpu_arch_tune = cpu_arch [i].type;
8141 cpu_arch_tune_flags = cpu_arch[i].flags;
8142 break;
8143 }
8144 }
8145 if (i >= ARRAY_SIZE (cpu_arch))
8146 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8147 break;
8148
1efbbeb4
L		 8149 case OPTION_MMNEMONIC:
8150 if (strcasecmp (arg, "att") == 0)
8151 intel_mnemonic = 0;
8152 else if (strcasecmp (arg, "intel") == 0)
8153 intel_mnemonic = 1;
8154 else
8155 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8156 break;
8157
8158 case OPTION_MSYNTAX:
8159 if (strcasecmp (arg, "att") == 0)
8160 intel_syntax = 0;
8161 else if (strcasecmp (arg, "intel") == 0)
8162 intel_syntax = 1;
8163 else
8164 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8165 break;
8166
8167 case OPTION_MINDEX_REG:
8168 allow_index_reg = 1;
8169 break;
8170
8171 case OPTION_MNAKED_REG:
8172 allow_naked_reg = 1;
8173 break;
8174
8175 case OPTION_MOLD_GCC:
8176 old_gcc = 1;
1efbbeb4
L		 8177 break;
8178
c0f3af97
L		 8179 case OPTION_MSSE2AVX:
8180 sse2avx = 1;
8181 break;
8182
daf50ae7
L		 8183 case OPTION_MSSE_CHECK:
8184 if (strcasecmp (arg, "error") == 0)
8185 sse_check = sse_check_error;
8186 else if (strcasecmp (arg, "warning") == 0)
8187 sse_check = sse_check_warning;
8188 else if (strcasecmp (arg, "none") == 0)
8189 sse_check = sse_check_none;
8190 else
8191 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8192 break;
8193
252b5132
RH		 8194 default:
8195 return 0;
8196 }
8197 return 1;
8198}
8199
8200void
8201md_show_usage (stream)
8202 FILE *stream;
8203{
4cc782b5
ILT		 8204#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8205 fprintf (stream, _("\
a38cf1db
AM		 8206 -Q ignored\n\
8207 -V print assembler version number\n\
b3b91714
AM		 8208 -k ignored\n"));
8209#endif
8210 fprintf (stream, _("\
12b55ccc 8211 -n Do not optimize code alignment\n\
b3b91714
AM		 8212 -q quieten some warnings\n"));
8213#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8214 fprintf (stream, _("\
a38cf1db 8215 -s ignored\n"));
b3b91714 8216#endif
751d281c
L		 8217#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8218 fprintf (stream, _("\
8219 --32/--64 generate 32bit/64bit code\n"));
8220#endif
b3b91714
AM		 8221#ifdef SVR4_COMMENT_CHARS
8222 fprintf (stream, _("\
8223 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8224#else
8225 fprintf (stream, _("\
b3b91714 8226 --divide ignored\n"));
4cc782b5 8227#endif
9103f4f4 8228 fprintf (stream, _("\
6305a203
L		 8229 -march=CPU[,+EXTENSION...]\n\
8230 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8231 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8232 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8233 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8234 generic32, generic64\n\
599121aa
L		 8235 EXTENSION is combination of:\n\
8236 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695
L		 8237 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8238 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
6305a203 8239 fprintf (stream, _("\
2cb4f3d5
L		 8240 -mtune=CPU optimize for CPU, CPU is one of:\n\
8241 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8242 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8243 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8244 generic32, generic64\n"));
ba104c83 8245 fprintf (stream, _("\
c0f3af97
L		 8246 -msse2avx encode SSE instructions with VEX prefix\n"));
8247 fprintf (stream, _("\
daf50ae7
L		 8248 -msse-check=[none|error|warning]\n\
8249 check SSE instructions\n"));
8250 fprintf (stream, _("\
ba104c83
L		 8251 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8252 fprintf (stream, _("\
8253 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8254 fprintf (stream, _("\
8255 -mindex-reg support pseudo index registers\n"));
8256 fprintf (stream, _("\
8257 -mnaked-reg don't require `%%' prefix for registers\n"));
8258 fprintf (stream, _("\
8259 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8260}
8261
3e73aa7c 8262#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8263 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 8264
8265/* Pick the target format to use. */
8266
47926f60 8267const char *
e3bb37b5 8268i386_target_format (void)
252b5132 8269{
3e73aa7c 8270 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8271 {
8272 set_code_flag (CODE_64BIT);
0dfbf9d7 8273 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8274 {
8275 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8276 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8277 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8278 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8279 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8280 cpu_arch_isa_flags.bitfield.cpui686 = 1;
8281 cpu_arch_isa_flags.bitfield.cpup4 = 1;
8282 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8283 cpu_arch_isa_flags.bitfield.cpusse = 1;
8284 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8285 }
0dfbf9d7 8286 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8287 {
8288 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8289 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8290 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8291 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8292 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8293 cpu_arch_tune_flags.bitfield.cpui686 = 1;
8294 cpu_arch_tune_flags.bitfield.cpup4 = 1;
8295 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8296 cpu_arch_tune_flags.bitfield.cpusse = 1;
8297 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8298 }
9103f4f4 8299 }
3e73aa7c 8300 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8301 {
8302 set_code_flag (CODE_32BIT);
0dfbf9d7 8303 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8304 {
8305 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8306 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8307 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8308 }
0dfbf9d7 8309 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8310 {
8311 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8312 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8313 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8314 }
9103f4f4 8315 }
3e73aa7c
JH		 8316 else
8317 as_fatal (_("Unknown architecture"));
252b5132
RH		 8318 switch (OUTPUT_FLAVOR)
8319 {
872ce6ff
L		 8320#ifdef TE_PEP
8321 case bfd_target_coff_flavour:
b01ee69d 8322 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "pe-i386";
872ce6ff
L		 8323 break;
8324#endif
4c63da97
AM		 8325#ifdef OBJ_MAYBE_AOUT
8326 case bfd_target_aout_flavour:
47926f60 8327 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8328#endif
8329#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8330 case bfd_target_coff_flavour:
8331 return "coff-i386";
4c63da97 8332#endif
3e73aa7c 8333#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8334 case bfd_target_elf_flavour:
3e73aa7c 8335 {
e5cb08ac 8336 if (flag_code == CODE_64BIT)
4fa24527
JB		 8337 {
8338 object_64bit = 1;
8339 use_rela_relocations = 1;
8340 }
9d7cbccd 8341 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8342 }
4c63da97 8343#endif
252b5132
RH		 8344 default:
8345 abort ();
8346 return NULL;
8347 }
8348}
8349
47926f60 8350#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8351
8352#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8353void
8354i386_elf_emit_arch_note (void)
a847613f 8355{
718ddfc0 8356 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8357 {
8358 char *p;
8359 asection *seg = now_seg;
8360 subsegT subseg = now_subseg;
8361 Elf_Internal_Note i_note;
8362 Elf_External_Note e_note;
8363 asection *note_secp;
8364 int len;
8365
8366 /* Create the .note section. */
8367 note_secp = subseg_new (".note", 0);
8368 bfd_set_section_flags (stdoutput,
8369 note_secp,
8370 SEC_HAS_CONTENTS | SEC_READONLY);
8371
8372 /* Process the arch string. */
8373 len = strlen (cpu_arch_name);
8374
8375 i_note.namesz = len + 1;
8376 i_note.descsz = 0;
8377 i_note.type = NT_ARCH;
8378 p = frag_more (sizeof (e_note.namesz));
8379 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8380 p = frag_more (sizeof (e_note.descsz));
8381 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8382 p = frag_more (sizeof (e_note.type));
8383 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8384 p = frag_more (len + 1);
8385 strcpy (p, cpu_arch_name);
8386
8387 frag_align (2, 0, 0);
8388
8389 subseg_set (seg, subseg);
8390 }
8391}
8392#endif
252b5132 8393\f
252b5132
RH		 8394symbolS *
8395md_undefined_symbol (name)
8396 char *name;
8397{
18dc2407
ILT		 8398 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8399 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8400 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8401 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8402 {
8403 if (!GOT_symbol)
8404 {
8405 if (symbol_find (name))
8406 as_bad (_("GOT already in symbol table"));
8407 GOT_symbol = symbol_new (name, undefined_section,
8408 (valueT) 0, &zero_address_frag);
8409 };
8410 return GOT_symbol;
8411 }
252b5132
RH		 8412 return 0;
8413}
8414
8415/* Round up a section size to the appropriate boundary. */
47926f60 8416
252b5132
RH		 8417valueT
8418md_section_align (segment, size)
ab9da554 8419 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8420 valueT size;
8421{
4c63da97
AM		 8422#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8423 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8424 {
8425 /* For a.out, force the section size to be aligned. If we don't do
8426 this, BFD will align it for us, but it will not write out the
8427 final bytes of the section. This may be a bug in BFD, but it is
8428 easier to fix it here since that is how the other a.out targets
8429 work. */
8430 int align;
8431
8432 align = bfd_get_section_alignment (stdoutput, segment);
8433 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8434 }
252b5132
RH		 8435#endif
8436
8437 return size;
8438}
8439
8440/* On the i386, PC-relative offsets are relative to the start of the
8441 next instruction. That is, the address of the offset, plus its
8442 size, since the offset is always the last part of the insn. */
8443
8444long
e3bb37b5 8445md_pcrel_from (fixS *fixP)
252b5132
RH		 8446{
8447 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8448}
8449
8450#ifndef I386COFF
8451
8452static void
e3bb37b5 8453s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8454{
29b0f896 8455 int temp;
252b5132 8456
8a75718c
JB		 8457#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8458 if (IS_ELF)
8459 obj_elf_section_change_hook ();
8460#endif
252b5132
RH		 8461 temp = get_absolute_expression ();
8462 subseg_set (bss_section, (subsegT) temp);
8463 demand_empty_rest_of_line ();
8464}
8465
8466#endif
8467
252b5132 8468void
e3bb37b5 8469i386_validate_fix (fixS *fixp)
252b5132
RH		 8470{
8471 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8472 {
23df1078
JH		 8473 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8474 {
4fa24527 8475 if (!object_64bit)
23df1078
JH		 8476 abort ();
8477 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8478 }
8479 else
8480 {
4fa24527 8481 if (!object_64bit)
d6ab8113
JB		 8482 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8483 else
8484 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8485 }
252b5132
RH		 8486 fixp->fx_subsy = 0;
8487 }
8488}
8489
252b5132
RH		 8490arelent *
8491tc_gen_reloc (section, fixp)
ab9da554 8492 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8493 fixS *fixp;
8494{
8495 arelent *rel;
8496 bfd_reloc_code_real_type code;
8497
8498 switch (fixp->fx_r_type)
8499 {
3e73aa7c
JH		 8500 case BFD_RELOC_X86_64_PLT32:
8501 case BFD_RELOC_X86_64_GOT32:
8502 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8503 case BFD_RELOC_386_PLT32:
8504 case BFD_RELOC_386_GOT32:
8505 case BFD_RELOC_386_GOTOFF:
8506 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8507 case BFD_RELOC_386_TLS_GD:
8508 case BFD_RELOC_386_TLS_LDM:
8509 case BFD_RELOC_386_TLS_LDO_32:
8510 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8511 case BFD_RELOC_386_TLS_IE:
8512 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8513 case BFD_RELOC_386_TLS_LE_32:
8514 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8515 case BFD_RELOC_386_TLS_GOTDESC:
8516 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8517 case BFD_RELOC_X86_64_TLSGD:
8518 case BFD_RELOC_X86_64_TLSLD:
8519 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8520 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8521 case BFD_RELOC_X86_64_GOTTPOFF:
8522 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8523 case BFD_RELOC_X86_64_TPOFF64:
8524 case BFD_RELOC_X86_64_GOTOFF64:
8525 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8526 case BFD_RELOC_X86_64_GOT64:
8527 case BFD_RELOC_X86_64_GOTPCREL64:
8528 case BFD_RELOC_X86_64_GOTPC64:
8529 case BFD_RELOC_X86_64_GOTPLT64:
8530 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8531 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8532 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8533 case BFD_RELOC_RVA:
8534 case BFD_RELOC_VTABLE_ENTRY:
8535 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8536#ifdef TE_PE
8537 case BFD_RELOC_32_SECREL:
8538#endif
252b5132
RH		 8539 code = fixp->fx_r_type;
8540 break;
dbbaec26
L		 8541 case BFD_RELOC_X86_64_32S:
8542 if (!fixp->fx_pcrel)
8543 {
8544 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8545 code = fixp->fx_r_type;
8546 break;
8547 }
252b5132 8548 default:
93382f6d 8549 if (fixp->fx_pcrel)
252b5132 8550 {
93382f6d
AM		 8551 switch (fixp->fx_size)
8552 {
8553 default:
b091f402
AM		 8554 as_bad_where (fixp->fx_file, fixp->fx_line,
8555 _("can not do %d byte pc-relative relocation"),
8556 fixp->fx_size);
93382f6d
AM		 8557 code = BFD_RELOC_32_PCREL;
8558 break;
8559 case 1: code = BFD_RELOC_8_PCREL; break;
8560 case 2: code = BFD_RELOC_16_PCREL; break;
8561 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8562#ifdef BFD64
8563 case 8: code = BFD_RELOC_64_PCREL; break;
8564#endif
93382f6d
AM		 8565 }
8566 }
8567 else
8568 {
8569 switch (fixp->fx_size)
8570 {
8571 default:
b091f402
AM		 8572 as_bad_where (fixp->fx_file, fixp->fx_line,
8573 _("can not do %d byte relocation"),
8574 fixp->fx_size);
93382f6d
AM		 8575 code = BFD_RELOC_32;
8576 break;
8577 case 1: code = BFD_RELOC_8; break;
8578 case 2: code = BFD_RELOC_16; break;
8579 case 4: code = BFD_RELOC_32; break;
937149dd 8580#ifdef BFD64
3e73aa7c 8581 case 8: code = BFD_RELOC_64; break;
937149dd 8582#endif
93382f6d 8583 }
252b5132
RH		 8584 }
8585 break;
8586 }
252b5132 8587
d182319b
JB		 8588 if ((code == BFD_RELOC_32
8589 || code == BFD_RELOC_32_PCREL
8590 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8591 && GOT_symbol
8592 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8593 {
4fa24527 8594 if (!object_64bit)
d6ab8113
JB		 8595 code = BFD_RELOC_386_GOTPC;
8596 else
8597 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8598 }
7b81dfbb
AJ		 8599 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8600 && GOT_symbol
8601 && fixp->fx_addsy == GOT_symbol)
8602 {
8603 code = BFD_RELOC_X86_64_GOTPC64;
8604 }
252b5132
RH		 8605
8606 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8607 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8608 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8609
8610 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8611
3e73aa7c
JH		 8612 if (!use_rela_relocations)
8613 {
8614 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8615 vtable entry to be used in the relocation's section offset. */
8616 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8617 rel->address = fixp->fx_offset;
252b5132 8618
c6682705 8619 rel->addend = 0;
3e73aa7c
JH		 8620 }
8621 /* Use the rela in 64bit mode. */
252b5132 8622 else
3e73aa7c 8623 {
062cd5e7
AS		 8624 if (!fixp->fx_pcrel)
8625 rel->addend = fixp->fx_offset;
8626 else
8627 switch (code)
8628 {
8629 case BFD_RELOC_X86_64_PLT32:
8630 case BFD_RELOC_X86_64_GOT32:
8631 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8632 case BFD_RELOC_X86_64_TLSGD:
8633 case BFD_RELOC_X86_64_TLSLD:
8634 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8635 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8636 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8637 rel->addend = fixp->fx_offset - fixp->fx_size;
8638 break;
8639 default:
8640 rel->addend = (section->vma
8641 - fixp->fx_size
8642 + fixp->fx_addnumber
8643 + md_pcrel_from (fixp));
8644 break;
8645 }
3e73aa7c
JH		 8646 }
8647
252b5132
RH		 8648 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8649 if (rel->howto == NULL)
8650 {
8651 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8652 _("cannot represent relocation type %s"),
252b5132
RH		 8653 bfd_get_reloc_code_name (code));
8654 /* Set howto to a garbage value so that we can keep going. */
8655 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8656 assert (rel->howto != NULL);
8657 }
8658
8659 return rel;
8660}
8661
64a0c779
DN		 8662\f
8663/* Parse operands using Intel syntax. This implements a recursive descent
8664 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8665 Programmer's Guide.
8666
8667 FIXME: We do not recognize the full operand grammar defined in the MASM
8668 documentation. In particular, all the structure/union and
8669 high-level macro operands are missing.
8670
8671 Uppercase words are terminals, lower case words are non-terminals.
8672 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8673 bars '|' denote choices. Most grammar productions are implemented in
8674 functions called 'intel_<production>'.
8675
8676 Initial production is 'expr'.
8677
9306ca4a 8678 addOp + | -
64a0c779
DN		 8679
8680 alpha [a-zA-Z]
8681
9306ca4a
JB		 8682 binOp & | AND | \| | OR | ^ | XOR
8683
64a0c779
DN		 8684 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8685
8686 constant digits [[ radixOverride ]]
8687
c0f3af97 8688 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
64a0c779
DN		 8689
8690 digits decdigit
b77a7acd
AJ		 8691 | digits decdigit
8692 | digits hexdigit
64a0c779
DN		 8693
8694 decdigit [0-9]
8695
9306ca4a
JB		 8696 e04 e04 addOp e05
8697 | e05
8698
8699 e05 e05 binOp e06
b77a7acd 8700 | e06
64a0c779
DN		 8701
8702 e06 e06 mulOp e09
b77a7acd 8703 | e09
64a0c779
DN		 8704
8705 e09 OFFSET e10
a724f0f4
JB		 8706 | SHORT e10
8707 | + e10
8708 | - e10
9306ca4a
JB		 8709 | ~ e10
8710 | NOT e10
64a0c779
DN		 8711 | e09 PTR e10
8712 | e09 : e10
8713 | e10
8714
8715 e10 e10 [ expr ]
b77a7acd 8716 | e11
64a0c779
DN		 8717
8718 e11 ( expr )
b77a7acd 8719 | [ expr ]
64a0c779
DN		 8720 | constant
8721 | dataType
8722 | id
8723 | $
8724 | register
8725
a724f0f4 8726 => expr expr cmpOp e04
9306ca4a 8727 | e04
64a0c779
DN		 8728
8729 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 8730 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 8731
8732 hexdigit a | b | c | d | e | f
b77a7acd 8733 | A | B | C | D | E | F
64a0c779
DN		 8734
8735 id alpha
b77a7acd 8736 | id alpha
64a0c779
DN		 8737 | id decdigit
8738
9306ca4a 8739 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 8740
8741 quote " | '
8742
8743 register specialRegister
b77a7acd 8744 | gpRegister
64a0c779
DN		 8745 | byteRegister
8746
8747 segmentRegister CS | DS | ES | FS | GS | SS
8748
9306ca4a 8749 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8750 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8751 | TR3 | TR4 | TR5 | TR6 | TR7
8752
64a0c779
DN		 8753 We simplify the grammar in obvious places (e.g., register parsing is
8754 done by calling parse_register) and eliminate immediate left recursion
8755 to implement a recursive-descent parser.
8756
a724f0f4
JB		 8757 expr e04 expr'
8758
8759 expr' cmpOp e04 expr'
8760 | Empty
9306ca4a
JB		 8761
8762 e04 e05 e04'
8763
8764 e04' addOp e05 e04'
8765 | Empty
64a0c779
DN		 8766
8767 e05 e06 e05'
8768
9306ca4a 8769 e05' binOp e06 e05'
b77a7acd 8770 | Empty
64a0c779
DN		 8771
8772 e06 e09 e06'
8773
8774 e06' mulOp e09 e06'
b77a7acd 8775 | Empty
64a0c779
DN		 8776
8777 e09 OFFSET e10 e09'
a724f0f4
JB		 8778 | SHORT e10'
8779 | + e10'
8780 | - e10'
8781 | ~ e10'
8782 | NOT e10'
b77a7acd 8783 | e10 e09'
64a0c779
DN		 8784
8785 e09' PTR e10 e09'
b77a7acd 8786 | : e10 e09'
64a0c779
DN		 8787 | Empty
8788
8789 e10 e11 e10'
8790
8791 e10' [ expr ] e10'
b77a7acd 8792 | Empty
64a0c779
DN		 8793
8794 e11 ( expr )
b77a7acd 8795 | [ expr ]
64a0c779
DN		 8796 | BYTE
8797 | WORD
8798 | DWORD
9306ca4a 8799 | FWORD
64a0c779 8800 | QWORD
9306ca4a
JB		 8801 | TBYTE
8802 | OWORD
8803 | XMMWORD
c0f3af97 8804 | YMMWORD
64a0c779
DN		 8805 | .
8806 | $
8807 | register
8808 | id
8809 | constant */
8810
8811/* Parsing structure for the intel syntax parser. Used to implement the
8812 semantic actions for the operand grammar. */
8813struct intel_parser_s
8814 {
8815 char *op_string; /* The string being parsed. */
8816 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8817 int op_modifier; /* Operand modifier. */
64a0c779 8818 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8819 int in_offset; /* >=1 if parsing operand of offset. */
8820 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8821 const reg_entry *reg; /* Last register reference found. */
8822 char *disp; /* Displacement string being built. */
a724f0f4 8823 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8824 };
8825
8826static struct intel_parser_s intel_parser;
8827
8828/* Token structure for parsing intel syntax. */
8829struct intel_token
8830 {
8831 int code; /* Token code. */
8832 const reg_entry *reg; /* Register entry for register tokens. */
8833 char *str; /* String representation. */
8834 };
8835
8836static struct intel_token cur_token, prev_token;
8837
50705ef4
AM		 8838/* Token codes for the intel parser. Since T_SHORT is already used
8839 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8840#define T_NIL -1
8841#define T_CONST 1
8842#define T_REG 2
8843#define T_BYTE 3
8844#define T_WORD 4
9306ca4a
JB		 8845#define T_DWORD 5
8846#define T_FWORD 6
8847#define T_QWORD 7
8848#define T_TBYTE 8
8849#define T_XMMWORD 9
50705ef4 8850#undef T_SHORT
9306ca4a
JB		 8851#define T_SHORT 10
8852#define T_OFFSET 11
8853#define T_PTR 12
8854#define T_ID 13
8855#define T_SHL 14
8856#define T_SHR 15
c0f3af97 8857#define T_YMMWORD 16
64a0c779
DN		 8858
8859/* Prototypes for intel parser functions. */
e3bb37b5
L		 8860static int intel_match_token (int);
8861static void intel_putback_token (void);
8862static void intel_get_token (void);
8863static int intel_expr (void);
8864static int intel_e04 (void);
8865static int intel_e05 (void);
8866static int intel_e06 (void);
8867static int intel_e09 (void);
8868static int intel_e10 (void);
8869static int intel_e11 (void);
64a0c779 8870
64a0c779 8871static int
e3bb37b5 8872i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8873{
8874 int ret;
8875 char *p;
fc0763e6
JB		 8876 const reg_entry *final_base = i.base_reg;
8877 const reg_entry *final_index = i.index_reg;
64a0c779 8878
a724f0f4
JB		 8879 p = intel_parser.op_string = xstrdup (operand_string);
8880 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8881
8882 for (;;)
64a0c779 8883 {
a724f0f4
JB		 8884 /* Initialize token holders. */
8885 cur_token.code = prev_token.code = T_NIL;
8886 cur_token.reg = prev_token.reg = NULL;
8887 cur_token.str = prev_token.str = NULL;
8888
8889 /* Initialize parser structure. */
8890 intel_parser.got_a_float = got_a_float;
8891 intel_parser.op_modifier = 0;
8892 intel_parser.is_mem = 0;
8893 intel_parser.in_offset = 0;
8894 intel_parser.in_bracket = 0;
8895 intel_parser.reg = NULL;
8896 intel_parser.disp[0] = '\0';
8897 intel_parser.next_operand = NULL;
8898
fc0763e6
JB		 8899 i.base_reg = NULL;
8900 i.index_reg = NULL;
8901
a724f0f4
JB		 8902 /* Read the first token and start the parser. */
8903 intel_get_token ();
8904 ret = intel_expr ();
8905
8906 if (!ret)
8907 break;
8908
9306ca4a
JB		 8909 if (cur_token.code != T_NIL)
8910 {
8911 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8912 current_templates->start->name, cur_token.str);
8913 ret = 0;
8914 }
64a0c779
DN		 8915 /* If we found a memory reference, hand it over to i386_displacement
8916 to fill in the rest of the operand fields. */
9306ca4a 8917 else if (intel_parser.is_mem)
64a0c779
DN		 8918 {
8919 if ((i.mem_operands == 1
40fb9820 8920 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8921 || i.mem_operands == 2)
8922 {
8923 as_bad (_("too many memory references for '%s'"),
8924 current_templates->start->name);
8925 ret = 0;
8926 }
8927 else
8928 {
8929 char *s = intel_parser.disp;
64a0c779 8930
a724f0f4
JB		 8931 if (!quiet_warnings && intel_parser.is_mem < 0)
8932 /* See the comments in intel_bracket_expr. */
8933 as_warn (_("Treating `%s' as memory reference"), operand_string);
8934
64a0c779
DN		 8935 /* Add the displacement expression. */
8936 if (*s != '\0')
a4622f40
AM		 8937 ret = i386_displacement (s, s + strlen (s));
8938 if (ret)
a724f0f4
JB		 8939 {
8940 /* Swap base and index in 16-bit memory operands like
8941 [si+bx]. Since i386_index_check is also used in AT&T
8942 mode we have to do that here. */
8943 if (i.base_reg
8944 && i.index_reg
40fb9820
L		 8945 && i.base_reg->reg_type.bitfield.reg16
8946 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8947 && i.base_reg->reg_num >= 6
8948 && i.index_reg->reg_num < 6)
8949 {
8950 const reg_entry *base = i.index_reg;
8951
8952 i.index_reg = i.base_reg;
8953 i.base_reg = base;
8954 }
8955 ret = i386_index_check (operand_string);
8956 }
fc0763e6
JB		 8957 if (ret)
8958 {
8959 i.types[this_operand].bitfield.mem = 1;
8960 i.mem_operands++;
8961 }
64a0c779
DN		 8962 }
8963 }
8964
8965 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8966 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8967 || intel_parser.reg == NULL)
b7240065
JB		 8968 {
8969 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8970 {
8971 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8972 as_warn (_("Segment override ignored"));
8973 i.seg[i.mem_operands] = NULL;
8974 }
8975 ret = i386_immediate (intel_parser.disp);
8976 }
a724f0f4 8977
fc0763e6
JB		 8978 if (!final_base && !final_index)
8979 {
8980 final_base = i.base_reg;
8981 final_index = i.index_reg;
8982 }
8983
a724f0f4 8984 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8985 ret = 0;
a724f0f4
JB		 8986 if (!ret || !intel_parser.next_operand)
8987 break;
8988 intel_parser.op_string = intel_parser.next_operand;
8989 this_operand = i.operands++;
7d5e4556 8990 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8991 }
8992
8993 free (p);
8994 free (intel_parser.disp);
8995
fc0763e6
JB		 8996 if (final_base || final_index)
8997 {
8998 i.base_reg = final_base;
8999 i.index_reg = final_index;
9000 }
9001
64a0c779
DN		 9002 return ret;
9003}
9004
a724f0f4
JB		 9005#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
9006
9007/* expr e04 expr'
9008
9009 expr' cmpOp e04 expr'
9010 | Empty */
64a0c779 9011static int
e3bb37b5 9012intel_expr (void)
64a0c779 9013{
a724f0f4
JB		 9014 /* XXX Implement the comparison operators. */
9015 return intel_e04 ();
9306ca4a
JB		 9016}
9017
a724f0f4 9018/* e04 e05 e04'
9306ca4a 9019
a724f0f4 9020 e04' addOp e05 e04'
9306ca4a
JB		 9021 | Empty */
9022static int
e3bb37b5 9023intel_e04 (void)
9306ca4a 9024{
a724f0f4 9025 int nregs = -1;
9306ca4a 9026
a724f0f4 9027 for (;;)
9306ca4a 9028 {
a724f0f4
JB		 9029 if (!intel_e05())
9030 return 0;
9306ca4a 9031
a724f0f4
JB		 9032 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9033 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 9034
a724f0f4
JB		 9035 if (cur_token.code == '+')
9036 nregs = -1;
9037 else if (cur_token.code == '-')
9038 nregs = NUM_ADDRESS_REGS;
9039 else
9040 return 1;
64a0c779 9041
a724f0f4
JB		 9042 strcat (intel_parser.disp, cur_token.str);
9043 intel_match_token (cur_token.code);
9044 }
64a0c779
DN		 9045}
9046
64a0c779
DN		 9047/* e05 e06 e05'
9048
9306ca4a 9049 e05' binOp e06 e05'
64a0c779
DN		 9050 | Empty */
9051static int
e3bb37b5 9052intel_e05 (void)
64a0c779 9053{
a724f0f4 9054 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9055
a724f0f4 9056 for (;;)
64a0c779 9057 {
a724f0f4
JB		 9058 if (!intel_e06())
9059 return 0;
9060
4eed87de
AM		 9061 if (cur_token.code == '&'
9062 || cur_token.code == '|'
9063 || cur_token.code == '^')
a724f0f4
JB		 9064 {
9065 char str[2];
9066
9067 str[0] = cur_token.code;
9068 str[1] = 0;
9069 strcat (intel_parser.disp, str);
9070 }
9071 else
9072 break;
9306ca4a 9073
64a0c779
DN		 9074 intel_match_token (cur_token.code);
9075
a724f0f4
JB		 9076 if (nregs < 0)
9077 nregs = ~nregs;
64a0c779 9078 }
a724f0f4
JB		 9079 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9080 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
9081 return 1;
4a1805b1 9082}
64a0c779
DN		 9083
9084/* e06 e09 e06'
9085
9086 e06' mulOp e09 e06'
b77a7acd 9087 | Empty */
64a0c779 9088static int
e3bb37b5 9089intel_e06 (void)
64a0c779 9090{
a724f0f4 9091 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9092
a724f0f4 9093 for (;;)
64a0c779 9094 {
a724f0f4
JB		 9095 if (!intel_e09())
9096 return 0;
9306ca4a 9097
4eed87de
AM		 9098 if (cur_token.code == '*'
9099 || cur_token.code == '/'
9100 || cur_token.code == '%')
a724f0f4
JB		 9101 {
9102 char str[2];
9306ca4a 9103
a724f0f4
JB		 9104 str[0] = cur_token.code;
9105 str[1] = 0;
9106 strcat (intel_parser.disp, str);
9107 }
9108 else if (cur_token.code == T_SHL)
9109 strcat (intel_parser.disp, "<<");
9110 else if (cur_token.code == T_SHR)
9111 strcat (intel_parser.disp, ">>");
9112 else
9113 break;
9306ca4a 9114
64e74474 9115 intel_match_token (cur_token.code);
64a0c779 9116
a724f0f4
JB		 9117 if (nregs < 0)
9118 nregs = ~nregs;
64a0c779 9119 }
a724f0f4
JB		 9120 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9121 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
9122 return 1;
64a0c779
DN		 9123}
9124
a724f0f4
JB		 9125/* e09 OFFSET e09
9126 | SHORT e09
9127 | + e09
9128 | - e09
9129 | ~ e09
9130 | NOT e09
9306ca4a
JB		 9131 | e10 e09'
9132
64a0c779 9133 e09' PTR e10 e09'
b77a7acd 9134 | : e10 e09'
64a0c779
DN		 9135 | Empty */
9136static int
e3bb37b5 9137intel_e09 (void)
64a0c779 9138{
a724f0f4
JB		 9139 int nregs = ~NUM_ADDRESS_REGS;
9140 int in_offset = 0;
9141
9142 for (;;)
64a0c779 9143 {
a724f0f4
JB		 9144 /* Don't consume constants here. */
9145 if (cur_token.code == '+' || cur_token.code == '-')
9146 {
9147 /* Need to look one token ahead - if the next token
9148 is a constant, the current token is its sign. */
9149 int next_code;
9150
9151 intel_match_token (cur_token.code);
9152 next_code = cur_token.code;
9153 intel_putback_token ();
9154 if (next_code == T_CONST)
9155 break;
9156 }
9157
9158 /* e09 OFFSET e09 */
9159 if (cur_token.code == T_OFFSET)
9160 {
9161 if (!in_offset++)
9162 ++intel_parser.in_offset;
9163 }
9164
9165 /* e09 SHORT e09 */
9166 else if (cur_token.code == T_SHORT)
9167 intel_parser.op_modifier |= 1 << T_SHORT;
9168
9169 /* e09 + e09 */
9170 else if (cur_token.code == '+')
9171 strcat (intel_parser.disp, "+");
9172
9173 /* e09 - e09
9174 | ~ e09
9175 | NOT e09 */
9176 else if (cur_token.code == '-' || cur_token.code == '~')
9177 {
9178 char str[2];
64a0c779 9179
a724f0f4
JB		 9180 if (nregs < 0)
9181 nregs = ~nregs;
9182 str[0] = cur_token.code;
9183 str[1] = 0;
9184 strcat (intel_parser.disp, str);
9185 }
9186
9187 /* e09 e10 e09' */
9188 else
9189 break;
9190
9191 intel_match_token (cur_token.code);
64a0c779
DN		 9192 }
9193
a724f0f4 9194 for (;;)
9306ca4a 9195 {
a724f0f4
JB		 9196 if (!intel_e10 ())
9197 return 0;
9306ca4a 9198
a724f0f4
JB		 9199 /* e09' PTR e10 e09' */
9200 if (cur_token.code == T_PTR)
9201 {
9202 char suffix;
9306ca4a 9203
a724f0f4 9204 if (prev_token.code == T_BYTE)
7d5e4556
L		 9205 {
9206 suffix = BYTE_MNEM_SUFFIX;
9207 i.types[this_operand].bitfield.byte = 1;
9208 }
9306ca4a 9209
a724f0f4
JB		 9210 else if (prev_token.code == T_WORD)
9211 {
34b772a6
JB		 9212 if ((current_templates->start->name[0] == 'l'
9213 && current_templates->start->name[2] == 's'
9214 && current_templates->start->name[3] == 0)
9215 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9216 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9217 else if (intel_parser.got_a_float == 2) /* "fi..." */
9218 suffix = SHORT_MNEM_SUFFIX;
9219 else
9220 suffix = WORD_MNEM_SUFFIX;
7d5e4556 9221 i.types[this_operand].bitfield.word = 1;
a724f0f4 9222 }
64a0c779 9223
a724f0f4
JB		 9224 else if (prev_token.code == T_DWORD)
9225 {
34b772a6
JB		 9226 if ((current_templates->start->name[0] == 'l'
9227 && current_templates->start->name[2] == 's'
9228 && current_templates->start->name[3] == 0)
9229 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9230 suffix = WORD_MNEM_SUFFIX;
9231 else if (flag_code == CODE_16BIT
40fb9820
L		 9232 && (current_templates->start->opcode_modifier.jump
9233 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 9234 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9235 else if (intel_parser.got_a_float == 1) /* "f..." */
9236 suffix = SHORT_MNEM_SUFFIX;
9237 else
9238 suffix = LONG_MNEM_SUFFIX;
7d5e4556 9239 i.types[this_operand].bitfield.dword = 1;
a724f0f4 9240 }
9306ca4a 9241
a724f0f4
JB		 9242 else if (prev_token.code == T_FWORD)
9243 {
9244 if (current_templates->start->name[0] == 'l'
9245 && current_templates->start->name[2] == 's'
9246 && current_templates->start->name[3] == 0)
9247 suffix = LONG_MNEM_SUFFIX;
9248 else if (!intel_parser.got_a_float)
9249 {
9250 if (flag_code == CODE_16BIT)
9251 add_prefix (DATA_PREFIX_OPCODE);
9252 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9253 }
9254 else
9255 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 9256 i.types[this_operand].bitfield.fword = 1;
a724f0f4 9257 }
64a0c779 9258
a724f0f4
JB		 9259 else if (prev_token.code == T_QWORD)
9260 {
34b772a6
JB		 9261 if (current_templates->start->base_opcode == 0x62 /* bound */
9262 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 9263 suffix = LONG_MNEM_SUFFIX;
9264 else
34b772a6 9265 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 9266 i.types[this_operand].bitfield.qword = 1;
a724f0f4 9267 }
64a0c779 9268
a724f0f4
JB		 9269 else if (prev_token.code == T_TBYTE)
9270 {
9271 if (intel_parser.got_a_float == 1)
9272 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9273 else
9274 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9275 }
9306ca4a 9276
a724f0f4 9277 else if (prev_token.code == T_XMMWORD)
9306ca4a 9278 {
582d5edd 9279 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 9280 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 9281 }
64a0c779 9282
c0f3af97
L		 9283 else if (prev_token.code == T_YMMWORD)
9284 {
9285 suffix = YMMWORD_MNEM_SUFFIX;
9286 i.types[this_operand].bitfield.ymmword = 1;
9287 }
9288
f16b83df 9289 else
a724f0f4
JB		 9290 {
9291 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9292 return 0;
9293 }
9294
7d5e4556
L		 9295 i.types[this_operand].bitfield.unspecified = 0;
9296
435acd52
JB		 9297 /* Operands for jump/call using 'ptr' notation denote absolute
9298 addresses. */
40fb9820
L		 9299 if (current_templates->start->opcode_modifier.jump
9300 || current_templates->start->opcode_modifier.jumpdword)
9301 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9302
a724f0f4
JB		 9303 if (current_templates->start->base_opcode == 0x8d /* lea */)
9304 ;
9305 else if (!i.suffix)
9306 i.suffix = suffix;
9307 else if (i.suffix != suffix)
9308 {
9309 as_bad (_("Conflicting operand modifiers"));
9310 return 0;
9311 }
64a0c779 9312
9306ca4a
JB		 9313 }
9314
a724f0f4
JB		 9315 /* e09' : e10 e09' */
9316 else if (cur_token.code == ':')
9306ca4a 9317 {
a724f0f4
JB		 9318 if (prev_token.code != T_REG)
9319 {
9320 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9321 segment/group identifier (which we don't have), using comma
9322 as the operand separator there is even less consistent, since
9323 there all branches only have a single operand. */
9324 if (this_operand != 0
9325 || intel_parser.in_offset
9326 || intel_parser.in_bracket
40fb9820
L		 9327 || (!current_templates->start->opcode_modifier.jump
9328 && !current_templates->start->opcode_modifier.jumpdword
9329 && !current_templates->start->opcode_modifier.jumpintersegment
9330 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 9331 return intel_match_token (T_NIL);
9332 /* Remember the start of the 2nd operand and terminate 1st
9333 operand here.
9334 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9335 another expression), but it gets at least the simplest case
9336 (a plain number or symbol on the left side) right. */
9337 intel_parser.next_operand = intel_parser.op_string;
9338 *--intel_parser.op_string = '\0';
9339 return intel_match_token (':');
9340 }
9306ca4a 9341 }
64a0c779 9342
a724f0f4 9343 /* e09' Empty */
64a0c779 9344 else
a724f0f4 9345 break;
64a0c779 9346
a724f0f4
JB		 9347 intel_match_token (cur_token.code);
9348
9349 }
9350
9351 if (in_offset)
9352 {
9353 --intel_parser.in_offset;
9354 if (nregs < 0)
9355 nregs = ~nregs;
9356 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 9357 {
a724f0f4 9358 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 9359 return 0;
9360 }
a724f0f4
JB		 9361 intel_parser.op_modifier |= 1 << T_OFFSET;
9362 }
9306ca4a 9363
a724f0f4
JB		 9364 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9365 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9366 return 1;
9367}
64a0c779 9368
a724f0f4 9369static int
e3bb37b5 9370intel_bracket_expr (void)
a724f0f4
JB		 9371{
9372 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9373 const char *start = intel_parser.op_string;
9374 int len;
9375
9376 if (i.op[this_operand].regs)
9377 return intel_match_token (T_NIL);
9378
9379 intel_match_token ('[');
9380
9381 /* Mark as a memory operand only if it's not already known to be an
9382 offset expression. If it's an offset expression, we need to keep
9383 the brace in. */
9384 if (!intel_parser.in_offset)
9385 {
9386 ++intel_parser.in_bracket;
435acd52
JB		 9387
9388 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 9389 if (current_templates->start->opcode_modifier.jump
9390 || current_templates->start->opcode_modifier.jumpdword)
9391 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9392
a724f0f4
JB		 9393 /* Unfortunately gas always diverged from MASM in a respect that can't
9394 be easily fixed without risking to break code sequences likely to be
9395 encountered (the testsuite even check for this): MASM doesn't consider
9396 an expression inside brackets unconditionally as a memory reference.
9397 When that is e.g. a constant, an offset expression, or the sum of the
9398 two, this is still taken as a constant load. gas, however, always
9399 treated these as memory references. As a compromise, we'll try to make
9400 offset expressions inside brackets work the MASM way (since that's
9401 less likely to be found in real world code), but make constants alone
9402 continue to work the traditional gas way. In either case, issue a
9403 warning. */
9404 intel_parser.op_modifier &= ~was_offset;
64a0c779 9405 }
a724f0f4 9406 else
64e74474 9407 strcat (intel_parser.disp, "[");
a724f0f4
JB		 9408
9409 /* Add a '+' to the displacement string if necessary. */
9410 if (*intel_parser.disp != '\0'
9411 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9412 strcat (intel_parser.disp, "+");
64a0c779 9413
a724f0f4
JB		 9414 if (intel_expr ()
9415 && (len = intel_parser.op_string - start - 1,
9416 intel_match_token (']')))
64a0c779 9417 {
a724f0f4
JB		 9418 /* Preserve brackets when the operand is an offset expression. */
9419 if (intel_parser.in_offset)
9420 strcat (intel_parser.disp, "]");
9421 else
9422 {
9423 --intel_parser.in_bracket;
9424 if (i.base_reg || i.index_reg)
9425 intel_parser.is_mem = 1;
9426 if (!intel_parser.is_mem)
9427 {
9428 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9429 /* Defer the warning until all of the operand was parsed. */
9430 intel_parser.is_mem = -1;
9431 else if (!quiet_warnings)
4eed87de
AM		 9432 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9433 len, start, len, start);
a724f0f4
JB		 9434 }
9435 }
9436 intel_parser.op_modifier |= was_offset;
64a0c779 9437
a724f0f4 9438 return 1;
64a0c779 9439 }
a724f0f4 9440 return 0;
64a0c779
DN		 9441}
9442
9443/* e10 e11 e10'
9444
9445 e10' [ expr ] e10'
b77a7acd 9446 | Empty */
64a0c779 9447static int
e3bb37b5 9448intel_e10 (void)
64a0c779 9449{
a724f0f4
JB		 9450 if (!intel_e11 ())
9451 return 0;
64a0c779 9452
a724f0f4 9453 while (cur_token.code == '[')
64a0c779 9454 {
a724f0f4 9455 if (!intel_bracket_expr ())
21d6c4af 9456 return 0;
64a0c779
DN		 9457 }
9458
a724f0f4 9459 return 1;
64a0c779
DN		 9460}
9461
64a0c779 9462/* e11 ( expr )
b77a7acd 9463 | [ expr ]
64a0c779
DN		 9464 | BYTE
9465 | WORD
9466 | DWORD
9306ca4a 9467 | FWORD
64a0c779 9468 | QWORD
9306ca4a
JB		 9469 | TBYTE
9470 | OWORD
9471 | XMMWORD
c0f3af97 9472 | YMMWORD
4a1805b1 9473 | $
64a0c779
DN		 9474 | .
9475 | register
9476 | id
9477 | constant */
9478static int
e3bb37b5 9479intel_e11 (void)
64a0c779 9480{
a724f0f4 9481 switch (cur_token.code)
64a0c779 9482 {
a724f0f4
JB		 9483 /* e11 ( expr ) */
9484 case '(':
64a0c779
DN		 9485 intel_match_token ('(');
9486 strcat (intel_parser.disp, "(");
9487
9488 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 9489 {
9490 strcat (intel_parser.disp, ")");
9491 return 1;
9492 }
a724f0f4 9493 return 0;
4a1805b1 9494
a724f0f4
JB		 9495 /* e11 [ expr ] */
9496 case '[':
a724f0f4 9497 return intel_bracket_expr ();
64a0c779 9498
a724f0f4
JB		 9499 /* e11 $
9500 | . */
9501 case '.':
64a0c779
DN		 9502 strcat (intel_parser.disp, cur_token.str);
9503 intel_match_token (cur_token.code);
21d6c4af
DN		 9504
9505 /* Mark as a memory operand only if it's not already known to be an
9506 offset expression. */
a724f0f4 9507 if (!intel_parser.in_offset)
21d6c4af 9508 intel_parser.is_mem = 1;
64a0c779
DN		 9509
9510 return 1;
64a0c779 9511
a724f0f4
JB		 9512 /* e11 register */
9513 case T_REG:
9514 {
9515 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 9516
a724f0f4 9517 intel_match_token (T_REG);
64a0c779 9518
a724f0f4
JB		 9519 /* Check for segment change. */
9520 if (cur_token.code == ':')
9521 {
40fb9820
L		 9522 if (!reg->reg_type.bitfield.sreg2
9523 && !reg->reg_type.bitfield.sreg3)
a724f0f4 9524 {
4eed87de
AM		 9525 as_bad (_("`%s' is not a valid segment register"),
9526 reg->reg_name);
a724f0f4
JB		 9527 return 0;
9528 }
b7240065
JB		 9529 else if (i.mem_operands >= 2)
9530 as_warn (_("Segment override ignored"));
a724f0f4
JB		 9531 else if (i.seg[i.mem_operands])
9532 as_warn (_("Extra segment override ignored"));
9533 else
9534 {
9535 if (!intel_parser.in_offset)
9536 intel_parser.is_mem = 1;
9537 switch (reg->reg_num)
9538 {
9539 case 0:
9540 i.seg[i.mem_operands] = &es;
9541 break;
9542 case 1:
9543 i.seg[i.mem_operands] = &cs;
9544 break;
9545 case 2:
9546 i.seg[i.mem_operands] = &ss;
9547 break;
9548 case 3:
9549 i.seg[i.mem_operands] = &ds;
9550 break;
9551 case 4:
9552 i.seg[i.mem_operands] = &fs;
9553 break;
9554 case 5:
9555 i.seg[i.mem_operands] = &gs;
9556 break;
9557 }
9558 }
9559 }
64a0c779 9560
b7240065
JB		 9561 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9562 {
9563 as_bad (_("cannot use `FLAT' here"));
9564 return 0;
9565 }
9566
a724f0f4
JB		 9567 /* Not a segment register. Check for register scaling. */
9568 else if (cur_token.code == '*')
9569 {
9570 if (!intel_parser.in_bracket)
9571 {
9572 as_bad (_("Register scaling only allowed in memory operands"));
9573 return 0;
9574 }
64a0c779 9575
40fb9820 9576 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 9577 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9578 else if (i.index_reg)
9579 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 9580
a724f0f4
JB		 9581 /* What follows must be a valid scale. */
9582 intel_match_token ('*');
9583 i.index_reg = reg;
40fb9820 9584 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 9585
a724f0f4
JB		 9586 /* Set the scale after setting the register (otherwise,
9587 i386_scale will complain) */
9588 if (cur_token.code == '+' || cur_token.code == '-')
9589 {
9590 char *str, sign = cur_token.code;
9591 intel_match_token (cur_token.code);
9592 if (cur_token.code != T_CONST)
9593 {
9594 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9595 cur_token.str);
9596 return 0;
9597 }
9598 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9599 strcpy (str + 1, cur_token.str);
9600 *str = sign;
9601 if (!i386_scale (str))
9602 return 0;
9603 free (str);
9604 }
9605 else if (!i386_scale (cur_token.str))
64a0c779 9606 return 0;
a724f0f4
JB		 9607 intel_match_token (cur_token.code);
9608 }
64a0c779 9609
a724f0f4
JB		 9610 /* No scaling. If this is a memory operand, the register is either a
9611 base register (first occurrence) or an index register (second
9612 occurrence). */
7b0441f6 9613 else if (intel_parser.in_bracket)
a724f0f4 9614 {
64a0c779 9615
a724f0f4
JB		 9616 if (!i.base_reg)
9617 i.base_reg = reg;
9618 else if (!i.index_reg)
9619 i.index_reg = reg;
9620 else
9621 {
9622 as_bad (_("Too many register references in memory operand"));
9623 return 0;
9624 }
64a0c779 9625
40fb9820 9626 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 9627 }
4a1805b1 9628
4d1bb795
JB		 9629 /* It's neither base nor index. */
9630 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 9631 {
40fb9820
L		 9632 i386_operand_type temp = reg->reg_type;
9633 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9634 i.types[this_operand] = operand_type_or (i.types[this_operand],
9635 temp);
7d5e4556 9636 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 9637 i.op[this_operand].regs = reg;
9638 i.reg_operands++;
9639 }
9640 else
9641 {
9642 as_bad (_("Invalid use of register"));
9643 return 0;
9644 }
64a0c779 9645
a724f0f4
JB		 9646 /* Since registers are not part of the displacement string (except
9647 when we're parsing offset operands), we may need to remove any
9648 preceding '+' from the displacement string. */
9649 if (*intel_parser.disp != '\0'
9650 && !intel_parser.in_offset)
9651 {
9652 char *s = intel_parser.disp;
9653 s += strlen (s) - 1;
9654 if (*s == '+')
9655 *s = '\0';
9656 }
4a1805b1 9657
a724f0f4
JB		 9658 return 1;
9659 }
9660
9661 /* e11 BYTE
9662 | WORD
9663 | DWORD
9664 | FWORD
9665 | QWORD
9666 | TBYTE
9667 | OWORD
c0f3af97
L		 9668 | XMMWORD
9669 | YMMWORD */
a724f0f4
JB		 9670 case T_BYTE:
9671 case T_WORD:
9672 case T_DWORD:
9673 case T_FWORD:
9674 case T_QWORD:
9675 case T_TBYTE:
9676 case T_XMMWORD:
c0f3af97 9677 case T_YMMWORD:
a724f0f4 9678 intel_match_token (cur_token.code);
64a0c779 9679
a724f0f4
JB		 9680 if (cur_token.code == T_PTR)
9681 return 1;
9682
9683 /* It must have been an identifier. */
9684 intel_putback_token ();
9685 cur_token.code = T_ID;
9686 /* FALLTHRU */
9687
9688 /* e11 id
9689 | constant */
9690 case T_ID:
9691 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 9692 {
9693 symbolS *symbolP;
9694
a724f0f4
JB		 9695 /* The identifier represents a memory reference only if it's not
9696 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 9697 symbolP = symbol_find(cur_token.str);
9698 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9699 intel_parser.is_mem = 1;
9700 }
a724f0f4 9701 /* FALLTHRU */
64a0c779 9702
a724f0f4
JB		 9703 case T_CONST:
9704 case '-':
9705 case '+':
9706 {
9707 char *save_str, sign = 0;
64a0c779 9708
a724f0f4
JB		 9709 /* Allow constants that start with `+' or `-'. */
9710 if (cur_token.code == '-' || cur_token.code == '+')
9711 {
9712 sign = cur_token.code;
9713 intel_match_token (cur_token.code);
9714 if (cur_token.code != T_CONST)
9715 {
9716 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9717 cur_token.str);
9718 return 0;
9719 }
9720 }
64a0c779 9721
a724f0f4
JB		 9722 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9723 strcpy (save_str + !!sign, cur_token.str);
9724 if (sign)
9725 *save_str = sign;
64a0c779 9726
a724f0f4
JB		 9727 /* Get the next token to check for register scaling. */
9728 intel_match_token (cur_token.code);
64a0c779 9729
4eed87de
AM		 9730 /* Check if this constant is a scaling factor for an
9731 index register. */
a724f0f4
JB		 9732 if (cur_token.code == '*')
9733 {
9734 if (intel_match_token ('*') && cur_token.code == T_REG)
9735 {
9736 const reg_entry *reg = cur_token.reg;
9737
9738 if (!intel_parser.in_bracket)
9739 {
4eed87de
AM		 9740 as_bad (_("Register scaling only allowed "
9741 "in memory operands"));
a724f0f4
JB		 9742 return 0;
9743 }
9744
4eed87de
AM		 9745 /* Disallow things like [1*si].
9746 sp and esp are invalid as index. */
40fb9820 9747 if (reg->reg_type.bitfield.reg16)
4eed87de 9748 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 9749 else if (i.index_reg)
4eed87de 9750 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 9751
9752 /* The constant is followed by `* reg', so it must be
9753 a valid scale. */
9754 i.index_reg = reg;
40fb9820 9755 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 9756
9757 /* Set the scale after setting the register (otherwise,
9758 i386_scale will complain) */
9759 if (!i386_scale (save_str))
64a0c779 9760 return 0;
a724f0f4
JB		 9761 intel_match_token (T_REG);
9762
9763 /* Since registers are not part of the displacement
9764 string, we may need to remove any preceding '+' from
9765 the displacement string. */
9766 if (*intel_parser.disp != '\0')
9767 {
9768 char *s = intel_parser.disp;
9769 s += strlen (s) - 1;
9770 if (*s == '+')
9771 *s = '\0';
9772 }
9773
9774 free (save_str);
9775
9776 return 1;
9777 }
64a0c779 9778
a724f0f4
JB		 9779 /* The constant was not used for register scaling. Since we have
9780 already consumed the token following `*' we now need to put it
9781 back in the stream. */
64a0c779 9782 intel_putback_token ();
a724f0f4 9783 }
64a0c779 9784
a724f0f4
JB		 9785 /* Add the constant to the displacement string. */
9786 strcat (intel_parser.disp, save_str);
9787 free (save_str);
64a0c779 9788
a724f0f4
JB		 9789 return 1;
9790 }
64a0c779
DN		 9791 }
9792
64a0c779
DN		 9793 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9794 return 0;
9795}
9796
64a0c779
DN		 9797/* Match the given token against cur_token. If they match, read the next
9798 token from the operand string. */
9799static int
e3bb37b5 9800intel_match_token (int code)
64a0c779
DN		 9801{
9802 if (cur_token.code == code)
9803 {
9804 intel_get_token ();
9805 return 1;
9806 }
9807 else
9808 {
0477af35 9809 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9810 return 0;
9811 }
9812}
9813
64a0c779
DN		 9814/* Read a new token from intel_parser.op_string and store it in cur_token. */
9815static void
e3bb37b5 9816intel_get_token (void)
64a0c779
DN		 9817{
9818 char *end_op;
9819 const reg_entry *reg;
9820 struct intel_token new_token;
9821
9822 new_token.code = T_NIL;
9823 new_token.reg = NULL;
9824 new_token.str = NULL;
9825
4a1805b1 9826 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9827 cur_token to prev_token. */
9828 if (prev_token.str)
9829 free (prev_token.str);
9830
9831 prev_token = cur_token;
9832
9833 /* Skip whitespace. */
9834 while (is_space_char (*intel_parser.op_string))
9835 intel_parser.op_string++;
9836
9837 /* Return an empty token if we find nothing else on the line. */
9838 if (*intel_parser.op_string == '\0')
9839 {
9840 cur_token = new_token;
9841 return;
9842 }
9843
9844 /* The new token cannot be larger than the remainder of the operand
9845 string. */
a724f0f4 9846 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9847 new_token.str[0] = '\0';
9848
9849 if (strchr ("0123456789", *intel_parser.op_string))
9850 {
9851 char *p = new_token.str;
9852 char *q = intel_parser.op_string;
9853 new_token.code = T_CONST;
9854
9855 /* Allow any kind of identifier char to encompass floating point and
9856 hexadecimal numbers. */
9857 while (is_identifier_char (*q))
9858 *p++ = *q++;
9859 *p = '\0';
9860
9861 /* Recognize special symbol names [0-9][bf]. */
9862 if (strlen (intel_parser.op_string) == 2
4a1805b1 9863 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9864 || intel_parser.op_string[1] == 'f'))
9865 new_token.code = T_ID;
9866 }
9867
4d1bb795 9868 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9869 {
4d1bb795
JB		 9870 size_t len = end_op - intel_parser.op_string;
9871
64a0c779
DN		 9872 new_token.code = T_REG;
9873 new_token.reg = reg;
9874
4d1bb795
JB		 9875 memcpy (new_token.str, intel_parser.op_string, len);
9876 new_token.str[len] = '\0';
64a0c779
DN		 9877 }
9878
9879 else if (is_identifier_char (*intel_parser.op_string))
9880 {
9881 char *p = new_token.str;
9882 char *q = intel_parser.op_string;
9883
9884 /* A '.' or '$' followed by an identifier char is an identifier.
9885 Otherwise, it's operator '.' followed by an expression. */
9886 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9887 {
9306ca4a
JB		 9888 new_token.code = '.';
9889 new_token.str[0] = '.';
64a0c779
DN		 9890 new_token.str[1] = '\0';
9891 }
9892 else
9893 {
9894 while (is_identifier_char (*q) || *q == '@')
9895 *p++ = *q++;
9896 *p = '\0';
9897
9306ca4a
JB		 9898 if (strcasecmp (new_token.str, "NOT") == 0)
9899 new_token.code = '~';
9900
9901 else if (strcasecmp (new_token.str, "MOD") == 0)
9902 new_token.code = '%';
9903
9904 else if (strcasecmp (new_token.str, "AND") == 0)
9905 new_token.code = '&';
9906
9907 else if (strcasecmp (new_token.str, "OR") == 0)
9908 new_token.code = '|';
9909
9910 else if (strcasecmp (new_token.str, "XOR") == 0)
9911 new_token.code = '^';
9912
9913 else if (strcasecmp (new_token.str, "SHL") == 0)
9914 new_token.code = T_SHL;
9915
9916 else if (strcasecmp (new_token.str, "SHR") == 0)
9917 new_token.code = T_SHR;
9918
9919 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9920 new_token.code = T_BYTE;
9921
9922 else if (strcasecmp (new_token.str, "WORD") == 0)
9923 new_token.code = T_WORD;
9924
9925 else if (strcasecmp (new_token.str, "DWORD") == 0)
9926 new_token.code = T_DWORD;
9927
9306ca4a
JB		 9928 else if (strcasecmp (new_token.str, "FWORD") == 0)
9929 new_token.code = T_FWORD;
9930
64a0c779
DN		 9931 else if (strcasecmp (new_token.str, "QWORD") == 0)
9932 new_token.code = T_QWORD;
9933
9306ca4a
JB		 9934 else if (strcasecmp (new_token.str, "TBYTE") == 0
9935 /* XXX remove (gcc still uses it) */
9936 || strcasecmp (new_token.str, "XWORD") == 0)
9937 new_token.code = T_TBYTE;
9938
9939 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9940 || strcasecmp (new_token.str, "OWORD") == 0)
9941 new_token.code = T_XMMWORD;
64a0c779 9942
c0f3af97
L		 9943 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9944 new_token.code = T_YMMWORD;
9945
64a0c779
DN		 9946 else if (strcasecmp (new_token.str, "PTR") == 0)
9947 new_token.code = T_PTR;
9948
9949 else if (strcasecmp (new_token.str, "SHORT") == 0)
9950 new_token.code = T_SHORT;
9951
9952 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9953 {
9954 new_token.code = T_OFFSET;
9955
9956 /* ??? This is not mentioned in the MASM grammar but gcc
9957 makes use of it with -mintel-syntax. OFFSET may be
9958 followed by FLAT: */
9959 if (strncasecmp (q, " FLAT:", 6) == 0)
9960 strcat (new_token.str, " FLAT:");
9961 }
9962
64a0c779
DN		 9963 else
9964 new_token.code = T_ID;
9965 }
9966 }
9967
9306ca4a
JB		 9968 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9969 {
9970 new_token.code = *intel_parser.op_string;
9971 new_token.str[0] = *intel_parser.op_string;
9972 new_token.str[1] = '\0';
9973 }
9974
9975 else if (strchr ("<>", *intel_parser.op_string)
9976 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9977 {
9978 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9979 new_token.str[0] = *intel_parser.op_string;
9980 new_token.str[1] = *intel_parser.op_string;
9981 new_token.str[2] = '\0';
9982 }
9983
64a0c779 9984 else
0477af35 9985 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9986
9987 intel_parser.op_string += strlen (new_token.str);
9988 cur_token = new_token;
9989}
9990
64a0c779
DN		 9991/* Put cur_token back into the token stream and make cur_token point to
9992 prev_token. */
9993static void
e3bb37b5 9994intel_putback_token (void)
64a0c779 9995{
a724f0f4
JB		 9996 if (cur_token.code != T_NIL)
9997 {
9998 intel_parser.op_string -= strlen (cur_token.str);
9999 free (cur_token.str);
10000 }
64a0c779 10001 cur_token = prev_token;
4a1805b1 10002
64a0c779
DN		 10003 /* Forget prev_token. */
10004 prev_token.code = T_NIL;
10005 prev_token.reg = NULL;
10006 prev_token.str = NULL;
10007}
54cfded0 10008
a60de03c
JB		 10009void
10010tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10011{
a60de03c
JB		 10012 int saved_naked_reg;
10013 char saved_register_dot;
54cfded0 10014
a60de03c
JB		 10015 saved_naked_reg = allow_naked_reg;
10016 allow_naked_reg = 1;
10017 saved_register_dot = register_chars['.'];
10018 register_chars['.'] = '.';
10019 allow_pseudo_reg = 1;
10020 expression_and_evaluate (exp);
10021 allow_pseudo_reg = 0;
10022 register_chars['.'] = saved_register_dot;
10023 allow_naked_reg = saved_naked_reg;
10024
10025 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10026 {
a60de03c
JB		 10027 if ((addressT) exp->X_add_number < i386_regtab_size)
10028 {
10029 exp->X_op = O_constant;
10030 exp->X_add_number = i386_regtab[exp->X_add_number]
10031 .dw2_regnum[flag_code >> 1];
10032 }
10033 else
10034 exp->X_op = O_illegal;
54cfded0 10035 }
54cfded0
AM		 10036}
10037
10038void
10039tc_x86_frame_initial_instructions (void)
10040{
a60de03c
JB		 10041 static unsigned int sp_regno[2];
10042
10043 if (!sp_regno[flag_code >> 1])
10044 {
10045 char *saved_input = input_line_pointer;
10046 char sp[][4] = {"esp", "rsp"};
10047 expressionS exp;
a4447b93 10048
a60de03c
JB		 10049 input_line_pointer = sp[flag_code >> 1];
10050 tc_x86_parse_to_dw2regnum (&exp);
10051 assert (exp.X_op == O_constant);
10052 sp_regno[flag_code >> 1] = exp.X_add_number;
10053 input_line_pointer = saved_input;
10054 }
a4447b93 10055
a60de03c 10056 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 10057 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10058}
d2b2c203
DJ		 10059
10060int
10061i386_elf_section_type (const char *str, size_t len)
10062{
10063 if (flag_code == CODE_64BIT
10064 && len == sizeof ("unwind") - 1
10065 && strncmp (str, "unwind", 6) == 0)
10066 return SHT_X86_64_UNWIND;
10067
10068 return -1;
10069}
bb41ade5 10070
ad5fec3b
EB		 10071#ifdef TE_SOLARIS
10072void
10073i386_solaris_fix_up_eh_frame (segT sec)
10074{
10075 if (flag_code == CODE_64BIT)
10076 elf_section_type (sec) = SHT_X86_64_UNWIND;
10077}
10078#endif
10079
bb41ade5
AM		 10080#ifdef TE_PE
10081void
10082tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10083{
10084 expressionS expr;
10085
10086 expr.X_op = O_secrel;
10087 expr.X_add_symbol = symbol;
10088 expr.X_add_number = 0;
10089 emit_expr (&expr, size);
10090}
10091#endif
3b22753a
L		 10092
10093#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10094/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10095
10096int
10097x86_64_section_letter (int letter, char **ptr_msg)
10098{
10099 if (flag_code == CODE_64BIT)
10100 {
10101 if (letter == 'l')
10102 return SHF_X86_64_LARGE;
10103
10104 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10105 }
3b22753a 10106 else
64e74474 10107 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10108 return -1;
10109}
10110
10111int
10112x86_64_section_word (char *str, size_t len)
10113{
8620418b 10114 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10115 return SHF_X86_64_LARGE;
10116
10117 return -1;
10118}
10119
10120static void
10121handle_large_common (int small ATTRIBUTE_UNUSED)
10122{
10123 if (flag_code != CODE_64BIT)
10124 {
10125 s_comm_internal (0, elf_common_parse);
10126 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10127 }
10128 else
10129 {
10130 static segT lbss_section;
10131 asection *saved_com_section_ptr = elf_com_section_ptr;
10132 asection *saved_bss_section = bss_section;
10133
10134 if (lbss_section == NULL)
10135 {
10136 flagword applicable;
10137 segT seg = now_seg;
10138 subsegT subseg = now_subseg;
10139
10140 /* The .lbss section is for local .largecomm symbols. */
10141 lbss_section = subseg_new (".lbss", 0);
10142 applicable = bfd_applicable_section_flags (stdoutput);
10143 bfd_set_section_flags (stdoutput, lbss_section,
10144 applicable & SEC_ALLOC);
10145 seg_info (lbss_section)->bss = 1;
10146
10147 subseg_set (seg, subseg);
10148 }
10149
10150 elf_com_section_ptr = &_bfd_elf_large_com_section;
10151 bss_section = lbss_section;
10152
10153 s_comm_internal (0, elf_common_parse);
10154
10155 elf_com_section_ptr = saved_com_section_ptr;
10156 bss_section = saved_bss_section;
10157 }
10158}
10159#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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