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* infrun.c (insert_step_resume_breakpoint_at_caller): New function,
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
92static void optimize_imm PARAMS ((void));
93static void optimize_disp PARAMS ((void));
94static int match_template PARAMS ((void));
95static int check_string PARAMS ((void));
96static int process_suffix PARAMS ((void));
97static int check_byte_reg PARAMS ((void));
98static int check_long_reg PARAMS ((void));
99static int check_qword_reg PARAMS ((void));
100static int check_word_reg PARAMS ((void));
101static int finalize_imm PARAMS ((void));
102static int process_operands PARAMS ((void));
103static const seg_entry *build_modrm_byte PARAMS ((void));
104static void output_insn PARAMS ((void));
105static void output_branch PARAMS ((void));
106static void output_jump PARAMS ((void));
107static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 108static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
29b0f896
AM		 112#ifndef I386COFF
113static void s_bss PARAMS ((int));
252b5132 114#endif
17d4e2a2
L		 115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116static void handle_large_common (int small ATTRIBUTE_UNUSED);
117#endif
252b5132 118
a847613f 119static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 120
252b5132 121/* 'md_assemble ()' gathers together information and puts it into a
47926f60 122 i386_insn. */
252b5132 123
520dc8e8
AM		 124union i386_op
125 {
126 expressionS *disps;
127 expressionS *imms;
128 const reg_entry *regs;
129 };
130
252b5132
RH		 131struct _i386_insn
132 {
47926f60 133 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 134 template tm;
135
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
138 char suffix;
139
47926f60 140 /* OPERANDS gives the number of given operands. */
252b5132
RH		 141 unsigned int operands;
142
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
47926f60 145 operands. */
252b5132
RH		 146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
147
148 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 149 use OP[i] for the corresponding operand. */
252b5132
RH		 150 unsigned int types[MAX_OPERANDS];
151
520dc8e8
AM		 152 /* Displacement expression, immediate expression, or register for each
153 operand. */
154 union i386_op op[MAX_OPERANDS];
252b5132 155
3e73aa7c
JH		 156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158#define Operand_PCrel 1
159
252b5132 160 /* Relocation type for operand */
f86103b7 161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 162
252b5132
RH		 163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
168
169 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 170 explicit segment overrides are given. */
ce8a8b2f 171 const seg_entry *seg[2];
252b5132
RH		 172
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
177
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
180
181 modrm_byte rm;
3e73aa7c 182 rex_byte rex;
252b5132
RH		 183 sib_byte sib;
184 };
185
186typedef struct _i386_insn i386_insn;
187
188/* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
32137342 190const char extra_symbol_chars[] = "*%-(["
252b5132 191#ifdef LEX_AT
32137342
NC		 192 "@"
193#endif
194#ifdef LEX_QM
195 "?"
252b5132 196#endif
32137342 197 ;
252b5132 198
29b0f896
AM		 199#if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 201 && !defined (TE_GNU) \
29b0f896 202 && !defined (TE_LINUX) \
32137342 203 && !defined (TE_NETWARE) \
29b0f896
AM		 204 && !defined (TE_FreeBSD) \
205 && !defined (TE_NetBSD)))
252b5132 206/* This array holds the chars that always start a comment. If the
b3b91714
AM		 207 pre-processor is disabled, these aren't very useful. The option
208 --divide will remove '/' from this list. */
209const char *i386_comment_chars = "#/";
210#define SVR4_COMMENT_CHARS 1
252b5132 211#define PREFIX_SEPARATOR '\\'
252b5132 212
b3b91714
AM		 213#else
214const char *i386_comment_chars = "#";
215#define PREFIX_SEPARATOR '/'
216#endif
217
252b5132
RH		 218/* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 220 .line and .file directives will appear in the pre-processed output.
221 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 222 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 223 #NO_APP at the beginning of its output.
224 Also note that comments started like this one will always work if
252b5132 225 '/' isn't otherwise defined. */
b3b91714 226const char line_comment_chars[] = "#/";
252b5132 227
63a0b638 228const char line_separator_chars[] = ";";
252b5132 229
ce8a8b2f
AM		 230/* Chars that can be used to separate mant from exp in floating point
231 nums. */
252b5132
RH		 232const char EXP_CHARS[] = "eE";
233
ce8a8b2f
AM		 234/* Chars that mean this number is a floating point constant
235 As in 0f12.456
236 or 0d1.2345e12. */
252b5132
RH		 237const char FLT_CHARS[] = "fFdDxX";
238
ce8a8b2f 239/* Tables for lexical analysis. */
252b5132
RH		 240static char mnemonic_chars[256];
241static char register_chars[256];
242static char operand_chars[256];
243static char identifier_chars[256];
244static char digit_chars[256];
245
ce8a8b2f 246/* Lexical macros. */
252b5132
RH		 247#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248#define is_operand_char(x) (operand_chars[(unsigned char) x])
249#define is_register_char(x) (register_chars[(unsigned char) x])
250#define is_space_char(x) ((x) == ' ')
251#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252#define is_digit_char(x) (digit_chars[(unsigned char) x])
253
0234cb7c 254/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 255static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
256
257/* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
47926f60 260 assembler instruction). */
252b5132 261static char save_stack[32];
ce8a8b2f 262static char *save_stack_p;
252b5132
RH		 263#define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265#define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
267
47926f60 268/* The instruction we're assembling. */
252b5132
RH		 269static i386_insn i;
270
271/* Possible templates for current insn. */
272static const templates *current_templates;
273
47926f60 274/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 275static expressionS disp_expressions[2], im_expressions[2];
276
47926f60
KH		 277/* Current operand we are working on. */
278static int this_operand;
252b5132 279
3e73aa7c
JH		 280/* We support four different modes. FLAG_CODE variable is used to distinguish
281 these. */
282
283enum flag_code {
284 CODE_32BIT,
285 CODE_16BIT,
286 CODE_64BIT };
f3c180ae 287#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 288
289static enum flag_code flag_code;
4fa24527 290static unsigned int object_64bit;
3e73aa7c
JH		 291static int use_rela_relocations = 0;
292
293/* The names used to print error messages. */
b77a7acd 294static const char *flag_code_names[] =
3e73aa7c
JH		 295 {
296 "32",
297 "16",
298 "64"
299 };
252b5132 300
47926f60
KH		 301/* 1 for intel syntax,
302 0 if att syntax. */
303static int intel_syntax = 0;
252b5132 304
47926f60
KH		 305/* 1 if register prefix % not required. */
306static int allow_naked_reg = 0;
252b5132 307
47926f60
KH		 308/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311static char stackop_size = '\0';
eecb386c 312
12b55ccc
L		 313/* Non-zero to optimize code alignment. */
314int optimize_align_code = 1;
315
47926f60
KH		 316/* Non-zero to quieten some warnings. */
317static int quiet_warnings = 0;
a38cf1db 318
47926f60
KH		 319/* CPU name. */
320static const char *cpu_arch_name = NULL;
5c6af06e 321static const char *cpu_sub_arch_name = NULL;
a38cf1db 322
47926f60 323/* CPU feature flags. */
29b0f896 324static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 325
fddf5b5b
AM		 326/* If set, conditional jumps are not automatically promoted to handle
327 larger than a byte offset. */
328static unsigned int no_cond_jump_promotion = 0;
329
29b0f896 330/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 331static symbolS *GOT_symbol;
29b0f896 332
a4447b93
RH		 333/* The dwarf2 return column, adjusted for 32 or 64 bit. */
334unsigned int x86_dwarf2_return_column;
335
336/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
337int x86_cie_data_alignment;
338
252b5132 339/* Interface to relax_segment.
fddf5b5b
AM		 340 There are 3 major relax states for 386 jump insns because the
341 different types of jumps add different sizes to frags when we're
342 figuring out what sort of jump to choose to reach a given label. */
252b5132 343
47926f60 344/* Types. */
93c2a809
AM		 345#define UNCOND_JUMP 0
346#define COND_JUMP 1
347#define COND_JUMP86 2
fddf5b5b 348
47926f60 349/* Sizes. */
252b5132
RH		 350#define CODE16 1
351#define SMALL 0
29b0f896 352#define SMALL16 (SMALL | CODE16)
252b5132 353#define BIG 2
29b0f896 354#define BIG16 (BIG | CODE16)
252b5132
RH		 355
356#ifndef INLINE
357#ifdef __GNUC__
358#define INLINE __inline__
359#else
360#define INLINE
361#endif
362#endif
363
fddf5b5b
AM		 364#define ENCODE_RELAX_STATE(type, size) \
365 ((relax_substateT) (((type) << 2) | (size)))
366#define TYPE_FROM_RELAX_STATE(s) \
367 ((s) >> 2)
368#define DISP_SIZE_FROM_RELAX_STATE(s) \
369 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 370
371/* This table is used by relax_frag to promote short jumps to long
372 ones where necessary. SMALL (short) jumps may be promoted to BIG
373 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
374 don't allow a short jump in a 32 bit code segment to be promoted to
375 a 16 bit offset jump because it's slower (requires data size
376 prefix), and doesn't work, unless the destination is in the bottom
377 64k of the code segment (The top 16 bits of eip are zeroed). */
378
379const relax_typeS md_relax_table[] =
380{
24eab124
AM		 381 /* The fields are:
382 1) most positive reach of this state,
383 2) most negative reach of this state,
93c2a809 384 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 385 4) which index into the table to try if we can't fit into this one. */
252b5132 386
fddf5b5b 387 /* UNCOND_JUMP states. */
93c2a809
AM		 388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
390 /* dword jmp adds 4 bytes to frag:
391 0 extra opcode bytes, 4 displacement bytes. */
252b5132 392 {0, 0, 4, 0},
93c2a809
AM		 393 /* word jmp adds 2 byte2 to frag:
394 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 395 {0, 0, 2, 0},
396
93c2a809
AM		 397 /* COND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
402 {0, 0, 5, 0},
fddf5b5b 403 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 404 1 extra opcode byte, 2 displacement bytes. */
405 {0, 0, 3, 0},
406
407 /* COND_JUMP86 states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
413 /* word conditionals add 4 bytes to frag:
414 1 displacement byte and a 3 byte long branch insn. */
415 {0, 0, 4, 0}
252b5132
RH		 416};
417
e413e4e9
AM		 418static const arch_entry cpu_arch[] = {
419 {"i8086", Cpu086 },
420 {"i186", Cpu086|Cpu186 },
421 {"i286", Cpu086|Cpu186|Cpu286 },
422 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
423 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 424 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
425 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
426 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
427 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
428 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
429 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
430 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
431 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
432 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
433 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
434 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
435 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 436 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 437 {".mmx", CpuMMX },
438 {".sse", CpuMMX|CpuMMX2|CpuSSE },
439 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 440 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 441 {".3dnow", CpuMMX|Cpu3dnow },
442 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
443 {".padlock", CpuPadLock },
30123838
JB		 444 {".pacifica", CpuSVME },
445 {".svme", CpuSVME },
e413e4e9
AM		 446 {NULL, 0 }
447};
448
29b0f896
AM		 449const pseudo_typeS md_pseudo_table[] =
450{
451#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
452 {"align", s_align_bytes, 0},
453#else
454 {"align", s_align_ptwo, 0},
455#endif
456 {"arch", set_cpu_arch, 0},
457#ifndef I386COFF
458 {"bss", s_bss, 0},
459#endif
460 {"ffloat", float_cons, 'f'},
461 {"dfloat", float_cons, 'd'},
462 {"tfloat", float_cons, 'x'},
463 {"value", cons, 2},
d182319b 464 {"slong", signed_cons, 4},
29b0f896
AM		 465 {"noopt", s_ignore, 0},
466 {"optim", s_ignore, 0},
467 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
468 {"code16", set_code_flag, CODE_16BIT},
469 {"code32", set_code_flag, CODE_32BIT},
470 {"code64", set_code_flag, CODE_64BIT},
471 {"intel_syntax", set_intel_syntax, 1},
472 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 473#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
474 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 475#else
476 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
477 {"loc", dwarf2_directive_loc, 0},
478 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 479#endif
6482c264
NC		 480#ifdef TE_PE
481 {"secrel32", pe_directive_secrel, 0},
482#endif
29b0f896
AM		 483 {0, 0, 0}
484};
485
486/* For interface with expression (). */
487extern char *input_line_pointer;
488
489/* Hash table for instruction mnemonic lookup. */
490static struct hash_control *op_hash;
491
492/* Hash table for register lookup. */
493static struct hash_control *reg_hash;
494\f
252b5132
RH		 495void
496i386_align_code (fragP, count)
497 fragS *fragP;
498 int count;
499{
ce8a8b2f
AM		 500 /* Various efficient no-op patterns for aligning code labels.
501 Note: Don't try to assemble the instructions in the comments.
502 0L and 0w are not legal. */
252b5132
RH		 503 static const char f32_1[] =
504 {0x90}; /* nop */
505 static const char f32_2[] =
506 {0x89,0xf6}; /* movl %esi,%esi */
507 static const char f32_3[] =
508 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
509 static const char f32_4[] =
510 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
511 static const char f32_5[] =
512 {0x90, /* nop */
513 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
514 static const char f32_6[] =
515 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
516 static const char f32_7[] =
517 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
518 static const char f32_8[] =
519 {0x90, /* nop */
520 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
521 static const char f32_9[] =
522 {0x89,0xf6, /* movl %esi,%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_10[] =
525 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
526 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
527 static const char f32_11[] =
528 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_12[] =
531 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
532 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
533 static const char f32_13[] =
534 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
535 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
536 static const char f32_14[] =
537 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
538 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
539 static const char f32_15[] =
540 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
541 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 542 static const char f16_3[] =
543 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 544 static const char f16_4[] =
545 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
546 static const char f16_5[] =
547 {0x90, /* nop */
548 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
549 static const char f16_6[] =
550 {0x89,0xf6, /* mov %si,%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char f16_7[] =
553 {0x8d,0x74,0x00, /* lea 0(%si),%si */
554 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
555 static const char f16_8[] =
556 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
557 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
558 static const char *const f32_patt[] = {
559 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
560 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
561 };
562 static const char *const f16_patt[] = {
c3332e24 563 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 564 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
565 };
566
33fef721
JH		 567 if (count <= 0 || count > 15)
568 return;
3e73aa7c 569
33fef721
JH		 570 /* The recommended way to pad 64bit code is to use NOPs preceded by
571 maximally four 0x66 prefixes. Balance the size of nops. */
572 if (flag_code == CODE_64BIT)
252b5132 573 {
33fef721
JH		 574 int i;
575 int nnops = (count + 3) / 4;
576 int len = count / nnops;
577 int remains = count - nnops * len;
578 int pos = 0;
579
580 for (i = 0; i < remains; i++)
252b5132 581 {
33fef721
JH		 582 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
583 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
584 pos += len + 1;
585 }
586 for (; i < nnops; i++)
587 {
588 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
589 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
590 pos += len;
252b5132 591 }
252b5132 592 }
33fef721
JH		 593 else
594 if (flag_code == CODE_16BIT)
595 {
596 memcpy (fragP->fr_literal + fragP->fr_fix,
597 f16_patt[count - 1], count);
598 if (count > 8)
599 /* Adjust jump offset. */
600 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
601 }
602 else
603 memcpy (fragP->fr_literal + fragP->fr_fix,
604 f32_patt[count - 1], count);
605 fragP->fr_var = count;
252b5132
RH		 606}
607
252b5132
RH		 608static INLINE unsigned int
609mode_from_disp_size (t)
610 unsigned int t;
611{
3e73aa7c 612 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 613}
614
615static INLINE int
616fits_in_signed_byte (num)
847f7ad4 617 offsetT num;
252b5132
RH		 618{
619 return (num >= -128) && (num <= 127);
47926f60 620}
252b5132
RH		 621
622static INLINE int
623fits_in_unsigned_byte (num)
847f7ad4 624 offsetT num;
252b5132
RH		 625{
626 return (num & 0xff) == num;
47926f60 627}
252b5132
RH		 628
629static INLINE int
630fits_in_unsigned_word (num)
847f7ad4 631 offsetT num;
252b5132
RH		 632{
633 return (num & 0xffff) == num;
47926f60 634}
252b5132
RH		 635
636static INLINE int
637fits_in_signed_word (num)
847f7ad4 638 offsetT num;
252b5132
RH		 639{
640 return (-32768 <= num) && (num <= 32767);
47926f60 641}
3e73aa7c
JH		 642static INLINE int
643fits_in_signed_long (num)
644 offsetT num ATTRIBUTE_UNUSED;
645{
646#ifndef BFD64
647 return 1;
648#else
649 return (!(((offsetT) -1 << 31) & num)
650 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
651#endif
652} /* fits_in_signed_long() */
653static INLINE int
654fits_in_unsigned_long (num)
655 offsetT num ATTRIBUTE_UNUSED;
656{
657#ifndef BFD64
658 return 1;
659#else
660 return (num & (((offsetT) 2 << 31) - 1)) == num;
661#endif
662} /* fits_in_unsigned_long() */
252b5132
RH		 663
664static int
665smallest_imm_type (num)
847f7ad4 666 offsetT num;
252b5132 667{
a847613f 668 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 669 {
670 /* This code is disabled on the 486 because all the Imm1 forms
671 in the opcode table are slower on the i486. They're the
672 versions with the implicitly specified single-position
673 displacement, which has another syntax if you really want to
674 use that form. */
675 if (num == 1)
3e73aa7c 676 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 677 }
252b5132 678 return (fits_in_signed_byte (num)
3e73aa7c 679 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 680 : fits_in_unsigned_byte (num)
3e73aa7c 681 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 682 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 683 ? (Imm16 | Imm32 | Imm32S | Imm64)
684 : fits_in_signed_long (num)
685 ? (Imm32 | Imm32S | Imm64)
686 : fits_in_unsigned_long (num)
687 ? (Imm32 | Imm64)
688 : Imm64);
47926f60 689}
252b5132 690
847f7ad4
AM		 691static offsetT
692offset_in_range (val, size)
693 offsetT val;
694 int size;
695{
508866be 696 addressT mask;
ba2adb93 697
847f7ad4
AM		 698 switch (size)
699 {
508866be
L		 700 case 1: mask = ((addressT) 1 << 8) - 1; break;
701 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 702 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 703#ifdef BFD64
704 case 8: mask = ((addressT) 2 << 63) - 1; break;
705#endif
47926f60 706 default: abort ();
847f7ad4
AM		 707 }
708
ba2adb93 709 /* If BFD64, sign extend val. */
3e73aa7c
JH		 710 if (!use_rela_relocations)
711 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
712 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 713
47926f60 714 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 715 {
716 char buf1[40], buf2[40];
717
718 sprint_value (buf1, val);
719 sprint_value (buf2, val & mask);
720 as_warn (_("%s shortened to %s"), buf1, buf2);
721 }
722 return val & mask;
723}
724
252b5132
RH		 725/* Returns 0 if attempting to add a prefix where one from the same
726 class already exists, 1 if non rep/repne added, 2 if rep/repne
727 added. */
728static int
729add_prefix (prefix)
730 unsigned int prefix;
731{
732 int ret = 1;
b1905489 733 unsigned int q;
252b5132 734
29b0f896
AM		 735 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
736 && flag_code == CODE_64BIT)
b1905489
JB		 737 {
738 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
739 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
740 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
741 ret = 0;
742 q = REX_PREFIX;
743 }
3e73aa7c 744 else
b1905489
JB		 745 {
746 switch (prefix)
747 {
748 default:
749 abort ();
750
751 case CS_PREFIX_OPCODE:
752 case DS_PREFIX_OPCODE:
753 case ES_PREFIX_OPCODE:
754 case FS_PREFIX_OPCODE:
755 case GS_PREFIX_OPCODE:
756 case SS_PREFIX_OPCODE:
757 q = SEG_PREFIX;
758 break;
759
760 case REPNE_PREFIX_OPCODE:
761 case REPE_PREFIX_OPCODE:
762 ret = 2;
763 /* fall thru */
764 case LOCK_PREFIX_OPCODE:
765 q = LOCKREP_PREFIX;
766 break;
767
768 case FWAIT_OPCODE:
769 q = WAIT_PREFIX;
770 break;
771
772 case ADDR_PREFIX_OPCODE:
773 q = ADDR_PREFIX;
774 break;
775
776 case DATA_PREFIX_OPCODE:
777 q = DATA_PREFIX;
778 break;
779 }
780 if (i.prefix[q] != 0)
781 ret = 0;
782 }
252b5132 783
b1905489 784 if (ret)
252b5132 785 {
b1905489
JB		 786 if (!i.prefix[q])
787 ++i.prefixes;
788 i.prefix[q] |= prefix;
252b5132 789 }
b1905489
JB		 790 else
791 as_bad (_("same type of prefix used twice"));
252b5132 792
252b5132
RH		 793 return ret;
794}
795
796static void
3e73aa7c 797set_code_flag (value)
e5cb08ac 798 int value;
eecb386c 799{
3e73aa7c
JH		 800 flag_code = value;
801 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
802 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
803 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
804 {
805 as_bad (_("64bit mode not supported on this CPU."));
806 }
807 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
808 {
809 as_bad (_("32bit mode not supported on this CPU."));
810 }
eecb386c
AM		 811 stackop_size = '\0';
812}
813
814static void
3e73aa7c
JH		 815set_16bit_gcc_code_flag (new_code_flag)
816 int new_code_flag;
252b5132 817{
3e73aa7c
JH		 818 flag_code = new_code_flag;
819 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
820 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 821 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 822}
823
824static void
825set_intel_syntax (syntax_flag)
eecb386c 826 int syntax_flag;
252b5132
RH		 827{
828 /* Find out if register prefixing is specified. */
829 int ask_naked_reg = 0;
830
831 SKIP_WHITESPACE ();
29b0f896 832 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 833 {
834 char *string = input_line_pointer;
835 int e = get_symbol_end ();
836
47926f60 837 if (strcmp (string, "prefix") == 0)
252b5132 838 ask_naked_reg = 1;
47926f60 839 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 840 ask_naked_reg = -1;
841 else
d0b47220 842 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 843 *input_line_pointer = e;
844 }
845 demand_empty_rest_of_line ();
c3332e24 846
252b5132
RH		 847 intel_syntax = syntax_flag;
848
849 if (ask_naked_reg == 0)
f86103b7
AM		 850 allow_naked_reg = (intel_syntax
851 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 852 else
853 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 854
855 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
856 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 857}
858
e413e4e9
AM		 859static void
860set_cpu_arch (dummy)
47926f60 861 int dummy ATTRIBUTE_UNUSED;
e413e4e9 862{
47926f60 863 SKIP_WHITESPACE ();
e413e4e9 864
29b0f896 865 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 866 {
867 char *string = input_line_pointer;
868 int e = get_symbol_end ();
869 int i;
870
871 for (i = 0; cpu_arch[i].name; i++)
872 {
873 if (strcmp (string, cpu_arch[i].name) == 0)
874 {
5c6af06e
JB		 875 if (*string != '.')
876 {
877 cpu_arch_name = cpu_arch[i].name;
878 cpu_sub_arch_name = NULL;
879 cpu_arch_flags = (cpu_arch[i].flags
880 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
881 break;
882 }
883 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
884 {
885 cpu_sub_arch_name = cpu_arch[i].name;
886 cpu_arch_flags |= cpu_arch[i].flags;
887 }
888 *input_line_pointer = e;
889 demand_empty_rest_of_line ();
890 return;
e413e4e9
AM		 891 }
892 }
893 if (!cpu_arch[i].name)
894 as_bad (_("no such architecture: `%s'"), string);
895
896 *input_line_pointer = e;
897 }
898 else
899 as_bad (_("missing cpu architecture"));
900
fddf5b5b
AM		 901 no_cond_jump_promotion = 0;
902 if (*input_line_pointer == ','
29b0f896 903 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 904 {
905 char *string = ++input_line_pointer;
906 int e = get_symbol_end ();
907
908 if (strcmp (string, "nojumps") == 0)
909 no_cond_jump_promotion = 1;
910 else if (strcmp (string, "jumps") == 0)
911 ;
912 else
913 as_bad (_("no such architecture modifier: `%s'"), string);
914
915 *input_line_pointer = e;
916 }
917
e413e4e9
AM		 918 demand_empty_rest_of_line ();
919}
920
b9d79e03
JH		 921unsigned long
922i386_mach ()
923{
924 if (!strcmp (default_arch, "x86_64"))
925 return bfd_mach_x86_64;
926 else if (!strcmp (default_arch, "i386"))
927 return bfd_mach_i386_i386;
928 else
929 as_fatal (_("Unknown architecture"));
930}
b9d79e03 931\f
252b5132
RH		 932void
933md_begin ()
934{
935 const char *hash_err;
936
47926f60 937 /* Initialize op_hash hash table. */
252b5132
RH		 938 op_hash = hash_new ();
939
940 {
29b0f896
AM		 941 const template *optab;
942 templates *core_optab;
252b5132 943
47926f60
KH		 944 /* Setup for loop. */
945 optab = i386_optab;
252b5132
RH		 946 core_optab = (templates *) xmalloc (sizeof (templates));
947 core_optab->start = optab;
948
949 while (1)
950 {
951 ++optab;
952 if (optab->name == NULL
953 || strcmp (optab->name, (optab - 1)->name) != 0)
954 {
955 /* different name --> ship out current template list;
47926f60 956 add to hash table; & begin anew. */
252b5132
RH		 957 core_optab->end = optab;
958 hash_err = hash_insert (op_hash,
959 (optab - 1)->name,
960 (PTR) core_optab);
961 if (hash_err)
962 {
252b5132
RH		 963 as_fatal (_("Internal Error: Can't hash %s: %s"),
964 (optab - 1)->name,
965 hash_err);
966 }
967 if (optab->name == NULL)
968 break;
969 core_optab = (templates *) xmalloc (sizeof (templates));
970 core_optab->start = optab;
971 }
972 }
973 }
974
47926f60 975 /* Initialize reg_hash hash table. */
252b5132
RH		 976 reg_hash = hash_new ();
977 {
29b0f896 978 const reg_entry *regtab;
252b5132
RH		 979
980 for (regtab = i386_regtab;
981 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
982 regtab++)
983 {
984 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
985 if (hash_err)
3e73aa7c
JH		 986 as_fatal (_("Internal Error: Can't hash %s: %s"),
987 regtab->reg_name,
988 hash_err);
252b5132
RH		 989 }
990 }
991
47926f60 992 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 993 {
29b0f896
AM		 994 int c;
995 char *p;
252b5132
RH		 996
997 for (c = 0; c < 256; c++)
998 {
3882b010 999 if (ISDIGIT (c))
252b5132
RH		 1000 {
1001 digit_chars[c] = c;
1002 mnemonic_chars[c] = c;
1003 register_chars[c] = c;
1004 operand_chars[c] = c;
1005 }
3882b010 1006 else if (ISLOWER (c))
252b5132
RH		 1007 {
1008 mnemonic_chars[c] = c;
1009 register_chars[c] = c;
1010 operand_chars[c] = c;
1011 }
3882b010 1012 else if (ISUPPER (c))
252b5132 1013 {
3882b010 1014 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1015 register_chars[c] = mnemonic_chars[c];
1016 operand_chars[c] = c;
1017 }
1018
3882b010 1019 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1020 identifier_chars[c] = c;
1021 else if (c >= 128)
1022 {
1023 identifier_chars[c] = c;
1024 operand_chars[c] = c;
1025 }
1026 }
1027
1028#ifdef LEX_AT
1029 identifier_chars['@'] = '@';
32137342
NC		 1030#endif
1031#ifdef LEX_QM
1032 identifier_chars['?'] = '?';
1033 operand_chars['?'] = '?';
252b5132 1034#endif
252b5132 1035 digit_chars['-'] = '-';
791fe849 1036 mnemonic_chars['-'] = '-';
252b5132
RH		 1037 identifier_chars['_'] = '_';
1038 identifier_chars['.'] = '.';
1039
1040 for (p = operand_special_chars; *p != '\0'; p++)
1041 operand_chars[(unsigned char) *p] = *p;
1042 }
1043
1044#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1045 if (IS_ELF)
252b5132
RH		 1046 {
1047 record_alignment (text_section, 2);
1048 record_alignment (data_section, 2);
1049 record_alignment (bss_section, 2);
1050 }
1051#endif
a4447b93
RH		 1052
1053 if (flag_code == CODE_64BIT)
1054 {
1055 x86_dwarf2_return_column = 16;
1056 x86_cie_data_alignment = -8;
1057 }
1058 else
1059 {
1060 x86_dwarf2_return_column = 8;
1061 x86_cie_data_alignment = -4;
1062 }
252b5132
RH		 1063}
1064
1065void
1066i386_print_statistics (file)
1067 FILE *file;
1068{
1069 hash_print_statistics (file, "i386 opcode", op_hash);
1070 hash_print_statistics (file, "i386 register", reg_hash);
1071}
1072\f
252b5132
RH		 1073#ifdef DEBUG386
1074
ce8a8b2f 1075/* Debugging routines for md_assemble. */
252b5132
RH		 1076static void pi PARAMS ((char *, i386_insn *));
1077static void pte PARAMS ((template *));
1078static void pt PARAMS ((unsigned int));
1079static void pe PARAMS ((expressionS *));
1080static void ps PARAMS ((symbolS *));
1081
1082static void
1083pi (line, x)
1084 char *line;
1085 i386_insn *x;
1086{
09f131f2 1087 unsigned int i;
252b5132
RH		 1088
1089 fprintf (stdout, "%s: template ", line);
1090 pte (&x->tm);
09f131f2
JH		 1091 fprintf (stdout, " address: base %s index %s scale %x\n",
1092 x->base_reg ? x->base_reg->reg_name : "none",
1093 x->index_reg ? x->index_reg->reg_name : "none",
1094 x->log2_scale_factor);
1095 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1096 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1097 fprintf (stdout, " sib: base %x index %x scale %x\n",
1098 x->sib.base, x->sib.index, x->sib.scale);
1099 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1100 (x->rex & REX_MODE64) != 0,
1101 (x->rex & REX_EXTX) != 0,
1102 (x->rex & REX_EXTY) != 0,
1103 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1104 for (i = 0; i < x->operands; i++)
1105 {
1106 fprintf (stdout, " #%d: ", i + 1);
1107 pt (x->types[i]);
1108 fprintf (stdout, "\n");
1109 if (x->types[i]
3f4438ab 1110 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1111 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1112 if (x->types[i] & Imm)
520dc8e8 1113 pe (x->op[i].imms);
252b5132 1114 if (x->types[i] & Disp)
520dc8e8 1115 pe (x->op[i].disps);
252b5132
RH		 1116 }
1117}
1118
1119static void
1120pte (t)
1121 template *t;
1122{
09f131f2 1123 unsigned int i;
252b5132 1124 fprintf (stdout, " %d operands ", t->operands);
47926f60 1125 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1126 if (t->extension_opcode != None)
1127 fprintf (stdout, "ext %x ", t->extension_opcode);
1128 if (t->opcode_modifier & D)
1129 fprintf (stdout, "D");
1130 if (t->opcode_modifier & W)
1131 fprintf (stdout, "W");
1132 fprintf (stdout, "\n");
1133 for (i = 0; i < t->operands; i++)
1134 {
1135 fprintf (stdout, " #%d type ", i + 1);
1136 pt (t->operand_types[i]);
1137 fprintf (stdout, "\n");
1138 }
1139}
1140
1141static void
1142pe (e)
1143 expressionS *e;
1144{
24eab124 1145 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1146 fprintf (stdout, " add_number %ld (%lx)\n",
1147 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1148 if (e->X_add_symbol)
1149 {
1150 fprintf (stdout, " add_symbol ");
1151 ps (e->X_add_symbol);
1152 fprintf (stdout, "\n");
1153 }
1154 if (e->X_op_symbol)
1155 {
1156 fprintf (stdout, " op_symbol ");
1157 ps (e->X_op_symbol);
1158 fprintf (stdout, "\n");
1159 }
1160}
1161
1162static void
1163ps (s)
1164 symbolS *s;
1165{
1166 fprintf (stdout, "%s type %s%s",
1167 S_GET_NAME (s),
1168 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1169 segment_name (S_GET_SEGMENT (s)));
1170}
1171
7b81dfbb 1172static struct type_name
252b5132
RH		 1173 {
1174 unsigned int mask;
1175 char *tname;
1176 }
7b81dfbb 1177const type_names[] =
252b5132
RH		 1178{
1179 { Reg8, "r8" },
1180 { Reg16, "r16" },
1181 { Reg32, "r32" },
09f131f2 1182 { Reg64, "r64" },
252b5132
RH		 1183 { Imm8, "i8" },
1184 { Imm8S, "i8s" },
1185 { Imm16, "i16" },
1186 { Imm32, "i32" },
09f131f2
JH		 1187 { Imm32S, "i32s" },
1188 { Imm64, "i64" },
252b5132
RH		 1189 { Imm1, "i1" },
1190 { BaseIndex, "BaseIndex" },
1191 { Disp8, "d8" },
1192 { Disp16, "d16" },
1193 { Disp32, "d32" },
09f131f2
JH		 1194 { Disp32S, "d32s" },
1195 { Disp64, "d64" },
252b5132
RH		 1196 { InOutPortReg, "InOutPortReg" },
1197 { ShiftCount, "ShiftCount" },
1198 { Control, "control reg" },
1199 { Test, "test reg" },
1200 { Debug, "debug reg" },
1201 { FloatReg, "FReg" },
1202 { FloatAcc, "FAcc" },
1203 { SReg2, "SReg2" },
1204 { SReg3, "SReg3" },
1205 { Acc, "Acc" },
1206 { JumpAbsolute, "Jump Absolute" },
1207 { RegMMX, "rMMX" },
3f4438ab 1208 { RegXMM, "rXMM" },
252b5132
RH		 1209 { EsSeg, "es" },
1210 { 0, "" }
1211};
1212
1213static void
1214pt (t)
1215 unsigned int t;
1216{
29b0f896 1217 const struct type_name *ty;
252b5132 1218
09f131f2
JH		 1219 for (ty = type_names; ty->mask; ty++)
1220 if (t & ty->mask)
1221 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1222 fflush (stdout);
1223}
1224
1225#endif /* DEBUG386 */
1226\f
252b5132 1227static bfd_reloc_code_real_type
3956db08 1228reloc (unsigned int size,
64e74474
AM		 1229 int pcrel,
1230 int sign,
1231 bfd_reloc_code_real_type other)
252b5132 1232{
47926f60 1233 if (other != NO_RELOC)
3956db08
JB		 1234 {
1235 reloc_howto_type *reloc;
1236
1237 if (size == 8)
1238 switch (other)
1239 {
64e74474
AM		 1240 case BFD_RELOC_X86_64_GOT32:
1241 return BFD_RELOC_X86_64_GOT64;
1242 break;
1243 case BFD_RELOC_X86_64_PLTOFF64:
1244 return BFD_RELOC_X86_64_PLTOFF64;
1245 break;
1246 case BFD_RELOC_X86_64_GOTPC32:
1247 other = BFD_RELOC_X86_64_GOTPC64;
1248 break;
1249 case BFD_RELOC_X86_64_GOTPCREL:
1250 other = BFD_RELOC_X86_64_GOTPCREL64;
1251 break;
1252 case BFD_RELOC_X86_64_TPOFF32:
1253 other = BFD_RELOC_X86_64_TPOFF64;
1254 break;
1255 case BFD_RELOC_X86_64_DTPOFF32:
1256 other = BFD_RELOC_X86_64_DTPOFF64;
1257 break;
1258 default:
1259 break;
3956db08 1260 }
e05278af
JB		 1261
1262 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1263 if (size == 4 && flag_code != CODE_64BIT)
1264 sign = -1;
1265
3956db08
JB		 1266 reloc = bfd_reloc_type_lookup (stdoutput, other);
1267 if (!reloc)
1268 as_bad (_("unknown relocation (%u)"), other);
1269 else if (size != bfd_get_reloc_size (reloc))
1270 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1271 bfd_get_reloc_size (reloc),
1272 size);
1273 else if (pcrel && !reloc->pc_relative)
1274 as_bad (_("non-pc-relative relocation for pc-relative field"));
1275 else if ((reloc->complain_on_overflow == complain_overflow_signed
1276 && !sign)
1277 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1278 && sign > 0))
3956db08
JB		 1279 as_bad (_("relocated field and relocation type differ in signedness"));
1280 else
1281 return other;
1282 return NO_RELOC;
1283 }
252b5132
RH		 1284
1285 if (pcrel)
1286 {
3e73aa7c 1287 if (!sign)
3956db08 1288 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1289 switch (size)
1290 {
1291 case 1: return BFD_RELOC_8_PCREL;
1292 case 2: return BFD_RELOC_16_PCREL;
1293 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1294 case 8: return BFD_RELOC_64_PCREL;
252b5132 1295 }
3956db08 1296 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1297 }
1298 else
1299 {
3956db08 1300 if (sign > 0)
e5cb08ac 1301 switch (size)
3e73aa7c
JH		 1302 {
1303 case 4: return BFD_RELOC_X86_64_32S;
1304 }
1305 else
1306 switch (size)
1307 {
1308 case 1: return BFD_RELOC_8;
1309 case 2: return BFD_RELOC_16;
1310 case 4: return BFD_RELOC_32;
1311 case 8: return BFD_RELOC_64;
1312 }
3956db08
JB		 1313 as_bad (_("cannot do %s %u byte relocation"),
1314 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1315 }
1316
bfb32b52 1317 abort ();
252b5132
RH		 1318 return BFD_RELOC_NONE;
1319}
1320
47926f60
KH		 1321/* Here we decide which fixups can be adjusted to make them relative to
1322 the beginning of the section instead of the symbol. Basically we need
1323 to make sure that the dynamic relocations are done correctly, so in
1324 some cases we force the original symbol to be used. */
1325
252b5132 1326int
c0c949c7 1327tc_i386_fix_adjustable (fixP)
31312f95 1328 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1329{
6d249963 1330#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1331 if (!IS_ELF)
31312f95
AM		 1332 return 1;
1333
a161fe53
AM		 1334 /* Don't adjust pc-relative references to merge sections in 64-bit
1335 mode. */
1336 if (use_rela_relocations
1337 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1338 && fixP->fx_pcrel)
252b5132 1339 return 0;
31312f95 1340
8d01d9a9
AJ		 1341 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1342 and changed later by validate_fix. */
1343 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1344 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1345 return 0;
1346
ce8a8b2f 1347 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1348 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1349 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1350 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1351 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1352 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1353 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1354 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1355 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1356 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1357 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1358 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1359 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1360 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1361 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1362 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1363 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1364 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1365 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1366 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1367 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1368 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1369 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1370 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1371 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1372 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1373 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1374 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1375 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1376 return 0;
31312f95 1377#endif
252b5132
RH		 1378 return 1;
1379}
252b5132 1380
29b0f896 1381static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1382
1383static int
252b5132 1384intel_float_operand (mnemonic)
29b0f896 1385 const char *mnemonic;
252b5132 1386{
9306ca4a
JB		 1387 /* Note that the value returned is meaningful only for opcodes with (memory)
1388 operands, hence the code here is free to improperly handle opcodes that
1389 have no operands (for better performance and smaller code). */
1390
1391 if (mnemonic[0] != 'f')
1392 return 0; /* non-math */
1393
1394 switch (mnemonic[1])
1395 {
1396 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1397 the fs segment override prefix not currently handled because no
1398 call path can make opcodes without operands get here */
1399 case 'i':
1400 return 2 /* integer op */;
1401 case 'l':
1402 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1403 return 3; /* fldcw/fldenv */
1404 break;
1405 case 'n':
1406 if (mnemonic[2] != 'o' /* fnop */)
1407 return 3; /* non-waiting control op */
1408 break;
1409 case 'r':
1410 if (mnemonic[2] == 's')
1411 return 3; /* frstor/frstpm */
1412 break;
1413 case 's':
1414 if (mnemonic[2] == 'a')
1415 return 3; /* fsave */
1416 if (mnemonic[2] == 't')
1417 {
1418 switch (mnemonic[3])
1419 {
1420 case 'c': /* fstcw */
1421 case 'd': /* fstdw */
1422 case 'e': /* fstenv */
1423 case 's': /* fsts[gw] */
1424 return 3;
1425 }
1426 }
1427 break;
1428 case 'x':
1429 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1430 return 0; /* fxsave/fxrstor are not really math ops */
1431 break;
1432 }
252b5132 1433
9306ca4a 1434 return 1;
252b5132
RH		 1435}
1436
1437/* This is the guts of the machine-dependent assembler. LINE points to a
1438 machine dependent instruction. This function is supposed to emit
1439 the frags/bytes it assembles to. */
1440
1441void
1442md_assemble (line)
1443 char *line;
1444{
252b5132 1445 int j;
252b5132
RH		 1446 char mnemonic[MAX_MNEM_SIZE];
1447
47926f60 1448 /* Initialize globals. */
252b5132
RH		 1449 memset (&i, '\0', sizeof (i));
1450 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1451 i.reloc[j] = NO_RELOC;
252b5132
RH		 1452 memset (disp_expressions, '\0', sizeof (disp_expressions));
1453 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1454 save_stack_p = save_stack;
252b5132
RH		 1455
1456 /* First parse an instruction mnemonic & call i386_operand for the operands.
1457 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1458 start of a (possibly prefixed) mnemonic. */
252b5132 1459
29b0f896
AM		 1460 line = parse_insn (line, mnemonic);
1461 if (line == NULL)
1462 return;
252b5132 1463
29b0f896
AM		 1464 line = parse_operands (line, mnemonic);
1465 if (line == NULL)
1466 return;
252b5132 1467
29b0f896
AM		 1468 /* Now we've parsed the mnemonic into a set of templates, and have the
1469 operands at hand. */
1470
1471 /* All intel opcodes have reversed operands except for "bound" and
1472 "enter". We also don't reverse intersegment "jmp" and "call"
1473 instructions with 2 immediate operands so that the immediate segment
1474 precedes the offset, as it does when in AT&T mode. "enter" and the
1475 intersegment "jmp" and "call" instructions are the only ones that
1476 have two immediate operands. */
1477 if (intel_syntax && i.operands > 1
1478 && (strcmp (mnemonic, "bound") != 0)
30123838 1479 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1480 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1481 swap_operands ();
1482
1483 if (i.imm_operands)
1484 optimize_imm ();
1485
b300c311
L		 1486 /* Don't optimize displacement for movabs since it only takes 64bit
1487 displacement. */
1488 if (i.disp_operands
1489 && (flag_code != CODE_64BIT
1490 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1491 optimize_disp ();
1492
1493 /* Next, we find a template that matches the given insn,
1494 making sure the overlap of the given operands types is consistent
1495 with the template operand types. */
252b5132 1496
29b0f896
AM		 1497 if (!match_template ())
1498 return;
252b5132 1499
cd61ebfe
AM		 1500 if (intel_syntax)
1501 {
1502 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1503 if (SYSV386_COMPAT
1504 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1505 i.tm.base_opcode ^= FloatR;
1506
1507 /* Zap movzx and movsx suffix. The suffix may have been set from
1508 "word ptr" or "byte ptr" on the source operand, but we'll use
1509 the suffix later to choose the destination register. */
1510 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1511 {
1512 if (i.reg_operands < 2
1513 && !i.suffix
1514 && (~i.tm.opcode_modifier
1515 & (No_bSuf
1516 | No_wSuf
1517 | No_lSuf
1518 | No_sSuf
1519 | No_xSuf
1520 | No_qSuf)))
1521 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1522
1523 i.suffix = 0;
1524 }
cd61ebfe 1525 }
24eab124 1526
29b0f896
AM		 1527 if (i.tm.opcode_modifier & FWait)
1528 if (!add_prefix (FWAIT_OPCODE))
1529 return;
252b5132 1530
29b0f896
AM		 1531 /* Check string instruction segment overrides. */
1532 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1533 {
1534 if (!check_string ())
5dd0794d 1535 return;
29b0f896 1536 }
5dd0794d 1537
29b0f896
AM		 1538 if (!process_suffix ())
1539 return;
e413e4e9 1540
29b0f896
AM		 1541 /* Make still unresolved immediate matches conform to size of immediate
1542 given in i.suffix. */
1543 if (!finalize_imm ())
1544 return;
252b5132 1545
29b0f896
AM		 1546 if (i.types[0] & Imm1)
1547 i.imm_operands = 0; /* kludge for shift insns. */
1548 if (i.types[0] & ImplicitRegister)
1549 i.reg_operands--;
1550 if (i.types[1] & ImplicitRegister)
1551 i.reg_operands--;
1552 if (i.types[2] & ImplicitRegister)
1553 i.reg_operands--;
252b5132 1554
29b0f896
AM		 1555 if (i.tm.opcode_modifier & ImmExt)
1556 {
02fc3089
L		 1557 expressionS *exp;
1558
ca164297
L		 1559 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1560 {
67c1ffbe 1561 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1562 operands with an opcode suffix which is coded in the same
1563 place as an 8-bit immediate field would be. Here we check
1564 those operands and remove them afterwards. */
1565 unsigned int x;
1566
a4622f40 1567 for (x = 0; x < i.operands; x++)
ca164297
L		 1568 if (i.op[x].regs->reg_num != x)
1569 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1570 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1571 i.operands = 0;
1572 }
1573
29b0f896
AM		 1574 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1575 opcode suffix which is coded in the same place as an 8-bit
1576 immediate field would be. Here we fake an 8-bit immediate
1577 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1578
29b0f896 1579 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1580
29b0f896
AM		 1581 exp = &im_expressions[i.imm_operands++];
1582 i.op[i.operands].imms = exp;
1583 i.types[i.operands++] = Imm8;
1584 exp->X_op = O_constant;
1585 exp->X_add_number = i.tm.extension_opcode;
1586 i.tm.extension_opcode = None;
1587 }
252b5132 1588
29b0f896
AM		 1589 /* For insns with operands there are more diddles to do to the opcode. */
1590 if (i.operands)
1591 {
1592 if (!process_operands ())
1593 return;
1594 }
1595 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1596 {
1597 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1598 as_warn (_("translating to `%sp'"), i.tm.name);
1599 }
252b5132 1600
29b0f896
AM		 1601 /* Handle conversion of 'int $3' --> special int3 insn. */
1602 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1603 {
1604 i.tm.base_opcode = INT3_OPCODE;
1605 i.imm_operands = 0;
1606 }
252b5132 1607
29b0f896
AM		 1608 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1609 && i.op[0].disps->X_op == O_constant)
1610 {
1611 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1612 the absolute address given by the constant. Since ix86 jumps and
1613 calls are pc relative, we need to generate a reloc. */
1614 i.op[0].disps->X_add_symbol = &abs_symbol;
1615 i.op[0].disps->X_op = O_symbol;
1616 }
252b5132 1617
29b0f896
AM		 1618 if ((i.tm.opcode_modifier & Rex64) != 0)
1619 i.rex |= REX_MODE64;
252b5132 1620
29b0f896
AM		 1621 /* For 8 bit registers we need an empty rex prefix. Also if the
1622 instruction already has a prefix, we need to convert old
1623 registers to new ones. */
773f551c 1624
29b0f896
AM		 1625 if (((i.types[0] & Reg8) != 0
1626 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1627 || ((i.types[1] & Reg8) != 0
1628 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1629 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1630 && i.rex != 0))
1631 {
1632 int x;
726c5dcd 1633
29b0f896
AM		 1634 i.rex |= REX_OPCODE;
1635 for (x = 0; x < 2; x++)
1636 {
1637 /* Look for 8 bit operand that uses old registers. */
1638 if ((i.types[x] & Reg8) != 0
1639 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1640 {
29b0f896
AM		 1641 /* In case it is "hi" register, give up. */
1642 if (i.op[x].regs->reg_num > 3)
0477af35 1643 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1644 i.op[x].regs->reg_name);
773f551c 1645
29b0f896
AM		 1646 /* Otherwise it is equivalent to the extended register.
1647 Since the encoding doesn't change this is merely
1648 cosmetic cleanup for debug output. */
1649
1650 i.op[x].regs = i.op[x].regs + 8;
773f551c 1651 }
29b0f896
AM		 1652 }
1653 }
773f551c 1654
29b0f896
AM		 1655 if (i.rex != 0)
1656 add_prefix (REX_OPCODE | i.rex);
1657
1658 /* We are ready to output the insn. */
1659 output_insn ();
1660}
1661
1662static char *
1663parse_insn (line, mnemonic)
1664 char *line;
1665 char *mnemonic;
1666{
1667 char *l = line;
1668 char *token_start = l;
1669 char *mnem_p;
5c6af06e
JB		 1670 int supported;
1671 const template *t;
29b0f896
AM		 1672
1673 /* Non-zero if we found a prefix only acceptable with string insns. */
1674 const char *expecting_string_instruction = NULL;
45288df1 1675
29b0f896
AM		 1676 while (1)
1677 {
1678 mnem_p = mnemonic;
1679 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1680 {
1681 mnem_p++;
1682 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1683 {
29b0f896
AM		 1684 as_bad (_("no such instruction: `%s'"), token_start);
1685 return NULL;
1686 }
1687 l++;
1688 }
1689 if (!is_space_char (*l)
1690 && *l != END_OF_INSN
e44823cf
JB		 1691 && (intel_syntax
1692 || (*l != PREFIX_SEPARATOR
1693 && *l != ',')))
29b0f896
AM		 1694 {
1695 as_bad (_("invalid character %s in mnemonic"),
1696 output_invalid (*l));
1697 return NULL;
1698 }
1699 if (token_start == l)
1700 {
e44823cf 1701 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1702 as_bad (_("expecting prefix; got nothing"));
1703 else
1704 as_bad (_("expecting mnemonic; got nothing"));
1705 return NULL;
1706 }
45288df1 1707
29b0f896
AM		 1708 /* Look up instruction (or prefix) via hash table. */
1709 current_templates = hash_find (op_hash, mnemonic);
47926f60 1710
29b0f896
AM		 1711 if (*l != END_OF_INSN
1712 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1713 && current_templates
1714 && (current_templates->start->opcode_modifier & IsPrefix))
1715 {
2dd88dca
JB		 1716 if (current_templates->start->cpu_flags
1717 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1718 {
1719 as_bad ((flag_code != CODE_64BIT
1720 ? _("`%s' is only supported in 64-bit mode")
1721 : _("`%s' is not supported in 64-bit mode")),
1722 current_templates->start->name);
1723 return NULL;
1724 }
29b0f896
AM		 1725 /* If we are in 16-bit mode, do not allow addr16 or data16.
1726 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1727 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1728 && flag_code != CODE_64BIT
1729 && (((current_templates->start->opcode_modifier & Size32) != 0)
1730 ^ (flag_code == CODE_16BIT)))
1731 {
1732 as_bad (_("redundant %s prefix"),
1733 current_templates->start->name);
1734 return NULL;
45288df1 1735 }
29b0f896
AM		 1736 /* Add prefix, checking for repeated prefixes. */
1737 switch (add_prefix (current_templates->start->base_opcode))
1738 {
1739 case 0:
1740 return NULL;
1741 case 2:
1742 expecting_string_instruction = current_templates->start->name;
1743 break;
1744 }
1745 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1746 token_start = ++l;
1747 }
1748 else
1749 break;
1750 }
45288df1 1751
29b0f896
AM		 1752 if (!current_templates)
1753 {
1754 /* See if we can get a match by trimming off a suffix. */
1755 switch (mnem_p[-1])
1756 {
1757 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1758 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1759 i.suffix = SHORT_MNEM_SUFFIX;
1760 else
29b0f896
AM		 1761 case BYTE_MNEM_SUFFIX:
1762 case QWORD_MNEM_SUFFIX:
1763 i.suffix = mnem_p[-1];
1764 mnem_p[-1] = '\0';
1765 current_templates = hash_find (op_hash, mnemonic);
1766 break;
1767 case SHORT_MNEM_SUFFIX:
1768 case LONG_MNEM_SUFFIX:
1769 if (!intel_syntax)
1770 {
1771 i.suffix = mnem_p[-1];
1772 mnem_p[-1] = '\0';
1773 current_templates = hash_find (op_hash, mnemonic);
1774 }
1775 break;
252b5132 1776
29b0f896
AM		 1777 /* Intel Syntax. */
1778 case 'd':
1779 if (intel_syntax)
1780 {
9306ca4a 1781 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1782 i.suffix = SHORT_MNEM_SUFFIX;
1783 else
1784 i.suffix = LONG_MNEM_SUFFIX;
1785 mnem_p[-1] = '\0';
1786 current_templates = hash_find (op_hash, mnemonic);
1787 }
1788 break;
1789 }
1790 if (!current_templates)
1791 {
1792 as_bad (_("no such instruction: `%s'"), token_start);
1793 return NULL;
1794 }
1795 }
252b5132 1796
29b0f896
AM		 1797 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1798 {
1799 /* Check for a branch hint. We allow ",pt" and ",pn" for
1800 predict taken and predict not taken respectively.
1801 I'm not sure that branch hints actually do anything on loop
1802 and jcxz insns (JumpByte) for current Pentium4 chips. They
1803 may work in the future and it doesn't hurt to accept them
1804 now. */
1805 if (l[0] == ',' && l[1] == 'p')
1806 {
1807 if (l[2] == 't')
1808 {
1809 if (!add_prefix (DS_PREFIX_OPCODE))
1810 return NULL;
1811 l += 3;
1812 }
1813 else if (l[2] == 'n')
1814 {
1815 if (!add_prefix (CS_PREFIX_OPCODE))
1816 return NULL;
1817 l += 3;
1818 }
1819 }
1820 }
1821 /* Any other comma loses. */
1822 if (*l == ',')
1823 {
1824 as_bad (_("invalid character %s in mnemonic"),
1825 output_invalid (*l));
1826 return NULL;
1827 }
252b5132 1828
29b0f896 1829 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1830 supported = 0;
1831 for (t = current_templates->start; t < current_templates->end; ++t)
1832 {
1833 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1834 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 1835 supported |= 1;
5c6af06e 1836 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 1837 supported |= 2;
5c6af06e
JB		 1838 }
1839 if (!(supported & 2))
1840 {
1841 as_bad (flag_code == CODE_64BIT
1842 ? _("`%s' is not supported in 64-bit mode")
1843 : _("`%s' is only supported in 64-bit mode"),
1844 current_templates->start->name);
1845 return NULL;
1846 }
1847 if (!(supported & 1))
29b0f896 1848 {
5c6af06e
JB		 1849 as_warn (_("`%s' is not supported on `%s%s'"),
1850 current_templates->start->name,
1851 cpu_arch_name,
1852 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1853 }
1854 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1855 {
1856 as_warn (_("use .code16 to ensure correct addressing mode"));
1857 }
252b5132 1858
29b0f896 1859 /* Check for rep/repne without a string instruction. */
f41bbced 1860 if (expecting_string_instruction)
29b0f896 1861 {
f41bbced
JB		 1862 static templates override;
1863
1864 for (t = current_templates->start; t < current_templates->end; ++t)
1865 if (t->opcode_modifier & IsString)
1866 break;
1867 if (t >= current_templates->end)
1868 {
1869 as_bad (_("expecting string instruction after `%s'"),
64e74474 1870 expecting_string_instruction);
f41bbced
JB		 1871 return NULL;
1872 }
1873 for (override.start = t; t < current_templates->end; ++t)
1874 if (!(t->opcode_modifier & IsString))
1875 break;
1876 override.end = t;
1877 current_templates = &override;
29b0f896 1878 }
252b5132 1879
29b0f896
AM		 1880 return l;
1881}
252b5132 1882
29b0f896
AM		 1883static char *
1884parse_operands (l, mnemonic)
1885 char *l;
1886 const char *mnemonic;
1887{
1888 char *token_start;
3138f287 1889
29b0f896
AM		 1890 /* 1 if operand is pending after ','. */
1891 unsigned int expecting_operand = 0;
252b5132 1892
29b0f896
AM		 1893 /* Non-zero if operand parens not balanced. */
1894 unsigned int paren_not_balanced;
1895
1896 while (*l != END_OF_INSN)
1897 {
1898 /* Skip optional white space before operand. */
1899 if (is_space_char (*l))
1900 ++l;
1901 if (!is_operand_char (*l) && *l != END_OF_INSN)
1902 {
1903 as_bad (_("invalid character %s before operand %d"),
1904 output_invalid (*l),
1905 i.operands + 1);
1906 return NULL;
1907 }
1908 token_start = l; /* after white space */
1909 paren_not_balanced = 0;
1910 while (paren_not_balanced || *l != ',')
1911 {
1912 if (*l == END_OF_INSN)
1913 {
1914 if (paren_not_balanced)
1915 {
1916 if (!intel_syntax)
1917 as_bad (_("unbalanced parenthesis in operand %d."),
1918 i.operands + 1);
1919 else
1920 as_bad (_("unbalanced brackets in operand %d."),
1921 i.operands + 1);
1922 return NULL;
1923 }
1924 else
1925 break; /* we are done */
1926 }
1927 else if (!is_operand_char (*l) && !is_space_char (*l))
1928 {
1929 as_bad (_("invalid character %s in operand %d"),
1930 output_invalid (*l),
1931 i.operands + 1);
1932 return NULL;
1933 }
1934 if (!intel_syntax)
1935 {
1936 if (*l == '(')
1937 ++paren_not_balanced;
1938 if (*l == ')')
1939 --paren_not_balanced;
1940 }
1941 else
1942 {
1943 if (*l == '[')
1944 ++paren_not_balanced;
1945 if (*l == ']')
1946 --paren_not_balanced;
1947 }
1948 l++;
1949 }
1950 if (l != token_start)
1951 { /* Yes, we've read in another operand. */
1952 unsigned int operand_ok;
1953 this_operand = i.operands++;
1954 if (i.operands > MAX_OPERANDS)
1955 {
1956 as_bad (_("spurious operands; (%d operands/instruction max)"),
1957 MAX_OPERANDS);
1958 return NULL;
1959 }
1960 /* Now parse operand adding info to 'i' as we go along. */
1961 END_STRING_AND_SAVE (l);
1962
1963 if (intel_syntax)
1964 operand_ok =
1965 i386_intel_operand (token_start,
1966 intel_float_operand (mnemonic));
1967 else
1968 operand_ok = i386_operand (token_start);
1969
1970 RESTORE_END_STRING (l);
1971 if (!operand_ok)
1972 return NULL;
1973 }
1974 else
1975 {
1976 if (expecting_operand)
1977 {
1978 expecting_operand_after_comma:
1979 as_bad (_("expecting operand after ','; got nothing"));
1980 return NULL;
1981 }
1982 if (*l == ',')
1983 {
1984 as_bad (_("expecting operand before ','; got nothing"));
1985 return NULL;
1986 }
1987 }
7f3f1ea2 1988
29b0f896
AM		 1989 /* Now *l must be either ',' or END_OF_INSN. */
1990 if (*l == ',')
1991 {
1992 if (*++l == END_OF_INSN)
1993 {
1994 /* Just skip it, if it's \n complain. */
1995 goto expecting_operand_after_comma;
1996 }
1997 expecting_operand = 1;
1998 }
1999 }
2000 return l;
2001}
7f3f1ea2 2002
29b0f896
AM		 2003static void
2004swap_operands ()
2005{
2006 union i386_op temp_op;
2007 unsigned int temp_type;
f86103b7 2008 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2009 int xchg1 = 0;
2010 int xchg2 = 0;
252b5132 2011
29b0f896
AM		 2012 if (i.operands == 2)
2013 {
2014 xchg1 = 0;
2015 xchg2 = 1;
2016 }
2017 else if (i.operands == 3)
2018 {
2019 xchg1 = 0;
2020 xchg2 = 2;
2021 }
2022 temp_type = i.types[xchg2];
2023 i.types[xchg2] = i.types[xchg1];
2024 i.types[xchg1] = temp_type;
2025 temp_op = i.op[xchg2];
2026 i.op[xchg2] = i.op[xchg1];
2027 i.op[xchg1] = temp_op;
2028 temp_reloc = i.reloc[xchg2];
2029 i.reloc[xchg2] = i.reloc[xchg1];
2030 i.reloc[xchg1] = temp_reloc;
2031
2032 if (i.mem_operands == 2)
2033 {
2034 const seg_entry *temp_seg;
2035 temp_seg = i.seg[0];
2036 i.seg[0] = i.seg[1];
2037 i.seg[1] = temp_seg;
2038 }
2039}
252b5132 2040
29b0f896
AM		 2041/* Try to ensure constant immediates are represented in the smallest
2042 opcode possible. */
2043static void
2044optimize_imm ()
2045{
2046 char guess_suffix = 0;
2047 int op;
252b5132 2048
29b0f896
AM		 2049 if (i.suffix)
2050 guess_suffix = i.suffix;
2051 else if (i.reg_operands)
2052 {
2053 /* Figure out a suffix from the last register operand specified.
2054 We can't do this properly yet, ie. excluding InOutPortReg,
2055 but the following works for instructions with immediates.
2056 In any case, we can't set i.suffix yet. */
2057 for (op = i.operands; --op >= 0;)
2058 if (i.types[op] & Reg)
252b5132 2059 {
29b0f896
AM		 2060 if (i.types[op] & Reg8)
2061 guess_suffix = BYTE_MNEM_SUFFIX;
2062 else if (i.types[op] & Reg16)
2063 guess_suffix = WORD_MNEM_SUFFIX;
2064 else if (i.types[op] & Reg32)
2065 guess_suffix = LONG_MNEM_SUFFIX;
2066 else if (i.types[op] & Reg64)
2067 guess_suffix = QWORD_MNEM_SUFFIX;
2068 break;
252b5132 2069 }
29b0f896
AM		 2070 }
2071 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2072 guess_suffix = WORD_MNEM_SUFFIX;
2073
2074 for (op = i.operands; --op >= 0;)
2075 if (i.types[op] & Imm)
2076 {
2077 switch (i.op[op].imms->X_op)
252b5132 2078 {
29b0f896
AM		 2079 case O_constant:
2080 /* If a suffix is given, this operand may be shortened. */
2081 switch (guess_suffix)
252b5132 2082 {
29b0f896
AM		 2083 case LONG_MNEM_SUFFIX:
2084 i.types[op] |= Imm32 | Imm64;
2085 break;
2086 case WORD_MNEM_SUFFIX:
2087 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2088 break;
2089 case BYTE_MNEM_SUFFIX:
2090 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2091 break;
252b5132 2092 }
252b5132 2093
29b0f896
AM		 2094 /* If this operand is at most 16 bits, convert it
2095 to a signed 16 bit number before trying to see
2096 whether it will fit in an even smaller size.
2097 This allows a 16-bit operand such as $0xffe0 to
2098 be recognised as within Imm8S range. */
2099 if ((i.types[op] & Imm16)
2100 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2101 {
29b0f896
AM		 2102 i.op[op].imms->X_add_number =
2103 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2104 }
2105 if ((i.types[op] & Imm32)
2106 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2107 == 0))
2108 {
2109 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2110 ^ ((offsetT) 1 << 31))
2111 - ((offsetT) 1 << 31));
2112 }
2113 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2114
29b0f896
AM		 2115 /* We must avoid matching of Imm32 templates when 64bit
2116 only immediate is available. */
2117 if (guess_suffix == QWORD_MNEM_SUFFIX)
2118 i.types[op] &= ~Imm32;
2119 break;
252b5132 2120
29b0f896
AM		 2121 case O_absent:
2122 case O_register:
2123 abort ();
2124
2125 /* Symbols and expressions. */
2126 default:
9cd96992
JB		 2127 /* Convert symbolic operand to proper sizes for matching, but don't
2128 prevent matching a set of insns that only supports sizes other
2129 than those matching the insn suffix. */
2130 {
2131 unsigned int mask, allowed = 0;
2132 const template *t;
2133
2134 for (t = current_templates->start; t < current_templates->end; ++t)
2135 allowed |= t->operand_types[op];
2136 switch (guess_suffix)
2137 {
2138 case QWORD_MNEM_SUFFIX:
2139 mask = Imm64 | Imm32S;
2140 break;
2141 case LONG_MNEM_SUFFIX:
2142 mask = Imm32;
2143 break;
2144 case WORD_MNEM_SUFFIX:
2145 mask = Imm16;
2146 break;
2147 case BYTE_MNEM_SUFFIX:
2148 mask = Imm8;
2149 break;
2150 default:
2151 mask = 0;
2152 break;
2153 }
64e74474
AM		 2154 if (mask & allowed)
2155 i.types[op] &= mask;
9cd96992 2156 }
29b0f896 2157 break;
252b5132 2158 }
29b0f896
AM		 2159 }
2160}
47926f60 2161
29b0f896
AM		 2162/* Try to use the smallest displacement type too. */
2163static void
2164optimize_disp ()
2165{
2166 int op;
3e73aa7c 2167
29b0f896 2168 for (op = i.operands; --op >= 0;)
b300c311 2169 if (i.types[op] & Disp)
252b5132 2170 {
b300c311 2171 if (i.op[op].disps->X_op == O_constant)
252b5132 2172 {
b300c311 2173 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2174
b300c311
L		 2175 if ((i.types[op] & Disp16)
2176 && (disp & ~(offsetT) 0xffff) == 0)
2177 {
2178 /* If this operand is at most 16 bits, convert
2179 to a signed 16 bit number and don't use 64bit
2180 displacement. */
2181 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2182 i.types[op] &= ~Disp64;
2183 }
2184 if ((i.types[op] & Disp32)
2185 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2186 {
2187 /* If this operand is at most 32 bits, convert
2188 to a signed 32 bit number and don't use 64bit
2189 displacement. */
2190 disp &= (((offsetT) 2 << 31) - 1);
2191 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2192 i.types[op] &= ~Disp64;
2193 }
2194 if (!disp && (i.types[op] & BaseIndex))
2195 {
2196 i.types[op] &= ~Disp;
2197 i.op[op].disps = 0;
2198 i.disp_operands--;
2199 }
2200 else if (flag_code == CODE_64BIT)
2201 {
2202 if (fits_in_signed_long (disp))
28a9d8f5
L		 2203 {
2204 i.types[op] &= ~Disp64;
2205 i.types[op] |= Disp32S;
2206 }
b300c311
L		 2207 if (fits_in_unsigned_long (disp))
2208 i.types[op] |= Disp32;
2209 }
2210 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2211 && fits_in_signed_byte (disp))
2212 i.types[op] |= Disp8;
252b5132 2213 }
67a4f2b7
AO		 2214 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2215 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2216 {
2217 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2218 i.op[op].disps, 0, i.reloc[op]);
2219 i.types[op] &= ~Disp;
2220 }
2221 else
b300c311
L		 2222 /* We only support 64bit displacement on constants. */
2223 i.types[op] &= ~Disp64;
252b5132 2224 }
29b0f896
AM		 2225}
2226
2227static int
2228match_template ()
2229{
2230 /* Points to template once we've found it. */
2231 const template *t;
2232 unsigned int overlap0, overlap1, overlap2;
2233 unsigned int found_reverse_match;
2234 int suffix_check;
2235
2236#define MATCH(overlap, given, template) \
2237 ((overlap & ~JumpAbsolute) \
2238 && (((given) & (BaseIndex | JumpAbsolute)) \
2239 == ((overlap) & (BaseIndex | JumpAbsolute))))
2240
2241 /* If given types r0 and r1 are registers they must be of the same type
2242 unless the expected operand type register overlap is null.
2243 Note that Acc in a template matches every size of reg. */
2244#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2245 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2246 || ((g0) & Reg) == ((g1) & Reg) \
2247 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2248
2249 overlap0 = 0;
2250 overlap1 = 0;
2251 overlap2 = 0;
2252 found_reverse_match = 0;
2253 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2254 ? No_bSuf
2255 : (i.suffix == WORD_MNEM_SUFFIX
2256 ? No_wSuf
2257 : (i.suffix == SHORT_MNEM_SUFFIX
2258 ? No_sSuf
2259 : (i.suffix == LONG_MNEM_SUFFIX
2260 ? No_lSuf
2261 : (i.suffix == QWORD_MNEM_SUFFIX
2262 ? No_qSuf
2263 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2264 ? No_xSuf : 0))))));
2265
45aa61fe 2266 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896
AM		 2267 {
2268 /* Must have right number of operands. */
2269 if (i.operands != t->operands)
2270 continue;
2271
2272 /* Check the suffix, except for some instructions in intel mode. */
2273 if ((t->opcode_modifier & suffix_check)
2274 && !(intel_syntax
9306ca4a 2275 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2276 continue;
2277
45aa61fe
AM		 2278 /* In general, don't allow 64-bit operands in 32-bit mode. */
2279 if (i.suffix == QWORD_MNEM_SUFFIX
2280 && flag_code != CODE_64BIT
2281 && (intel_syntax
2282 ? (!(t->opcode_modifier & IgnoreSize)
2283 && !intel_float_operand (t->name))
2284 : intel_float_operand (t->name) != 2)
2285 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2286 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2287 && (t->base_opcode != 0x0fc7
2288 || t->extension_opcode != 1 /* cmpxchg8b */))
2289 continue;
2290
29b0f896
AM		 2291 /* Do not verify operands when there are none. */
2292 else if (!t->operands)
2293 {
2294 if (t->cpu_flags & ~cpu_arch_flags)
2295 continue;
2296 /* We've found a match; break out of loop. */
2297 break;
2298 }
252b5132 2299
29b0f896
AM		 2300 overlap0 = i.types[0] & t->operand_types[0];
2301 switch (t->operands)
2302 {
2303 case 1:
2304 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2305 continue;
2306 break;
2307 case 2:
2308 case 3:
2309 overlap1 = i.types[1] & t->operand_types[1];
2310 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2311 || !MATCH (overlap1, i.types[1], t->operand_types[1])
cb712a9e 2312 /* monitor in SSE3 is a very special case. The first
708587a4 2313 register and the second register may have different
cb712a9e
L		 2314 sizes. */
2315 || !((t->base_opcode == 0x0f01
2316 && t->extension_opcode == 0xc8)
2317 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2318 t->operand_types[0],
2319 overlap1, i.types[1],
2320 t->operand_types[1])))
29b0f896
AM		 2321 {
2322 /* Check if other direction is valid ... */
2323 if ((t->opcode_modifier & (D | FloatD)) == 0)
2324 continue;
2325
2326 /* Try reversing direction of operands. */
2327 overlap0 = i.types[0] & t->operand_types[1];
2328 overlap1 = i.types[1] & t->operand_types[0];
2329 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2330 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2331 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2332 t->operand_types[1],
2333 overlap1, i.types[1],
2334 t->operand_types[0]))
2335 {
2336 /* Does not match either direction. */
2337 continue;
2338 }
2339 /* found_reverse_match holds which of D or FloatDR
2340 we've found. */
2341 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2342 }
2343 /* Found a forward 2 operand match here. */
2344 else if (t->operands == 3)
2345 {
2346 /* Here we make use of the fact that there are no
2347 reverse match 3 operand instructions, and all 3
2348 operand instructions only need to be checked for
2349 register consistency between operands 2 and 3. */
2350 overlap2 = i.types[2] & t->operand_types[2];
2351 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2352 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2353 t->operand_types[1],
2354 overlap2, i.types[2],
2355 t->operand_types[2]))
2356
2357 continue;
2358 }
2359 /* Found either forward/reverse 2 or 3 operand match here:
2360 slip through to break. */
2361 }
2362 if (t->cpu_flags & ~cpu_arch_flags)
2363 {
2364 found_reverse_match = 0;
2365 continue;
2366 }
2367 /* We've found a match; break out of loop. */
2368 break;
2369 }
2370
2371 if (t == current_templates->end)
2372 {
2373 /* We found no match. */
2374 as_bad (_("suffix or operands invalid for `%s'"),
2375 current_templates->start->name);
2376 return 0;
2377 }
252b5132 2378
29b0f896
AM		 2379 if (!quiet_warnings)
2380 {
2381 if (!intel_syntax
2382 && ((i.types[0] & JumpAbsolute)
2383 != (t->operand_types[0] & JumpAbsolute)))
2384 {
2385 as_warn (_("indirect %s without `*'"), t->name);
2386 }
2387
2388 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2389 == (IsPrefix | IgnoreSize))
2390 {
2391 /* Warn them that a data or address size prefix doesn't
2392 affect assembly of the next line of code. */
2393 as_warn (_("stand-alone `%s' prefix"), t->name);
2394 }
2395 }
2396
2397 /* Copy the template we found. */
2398 i.tm = *t;
2399 if (found_reverse_match)
2400 {
2401 /* If we found a reverse match we must alter the opcode
2402 direction bit. found_reverse_match holds bits to change
2403 (different for int & float insns). */
2404
2405 i.tm.base_opcode ^= found_reverse_match;
2406
2407 i.tm.operand_types[0] = t->operand_types[1];
2408 i.tm.operand_types[1] = t->operand_types[0];
2409 }
2410
2411 return 1;
2412}
2413
2414static int
2415check_string ()
2416{
2417 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2418 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2419 {
2420 if (i.seg[0] != NULL && i.seg[0] != &es)
2421 {
2422 as_bad (_("`%s' operand %d must use `%%es' segment"),
2423 i.tm.name,
2424 mem_op + 1);
2425 return 0;
2426 }
2427 /* There's only ever one segment override allowed per instruction.
2428 This instruction possibly has a legal segment override on the
2429 second operand, so copy the segment to where non-string
2430 instructions store it, allowing common code. */
2431 i.seg[0] = i.seg[1];
2432 }
2433 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2434 {
2435 if (i.seg[1] != NULL && i.seg[1] != &es)
2436 {
2437 as_bad (_("`%s' operand %d must use `%%es' segment"),
2438 i.tm.name,
2439 mem_op + 2);
2440 return 0;
2441 }
2442 }
2443 return 1;
2444}
2445
2446static int
543613e9 2447process_suffix (void)
29b0f896
AM		 2448{
2449 /* If matched instruction specifies an explicit instruction mnemonic
2450 suffix, use it. */
2451 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2452 {
2453 if (i.tm.opcode_modifier & Size16)
2454 i.suffix = WORD_MNEM_SUFFIX;
2455 else if (i.tm.opcode_modifier & Size64)
2456 i.suffix = QWORD_MNEM_SUFFIX;
2457 else
2458 i.suffix = LONG_MNEM_SUFFIX;
2459 }
2460 else if (i.reg_operands)
2461 {
2462 /* If there's no instruction mnemonic suffix we try to invent one
2463 based on register operands. */
2464 if (!i.suffix)
2465 {
2466 /* We take i.suffix from the last register operand specified,
2467 Destination register type is more significant than source
2468 register type. */
2469 int op;
543613e9 2470
29b0f896
AM		 2471 for (op = i.operands; --op >= 0;)
2472 if ((i.types[op] & Reg)
2473 && !(i.tm.operand_types[op] & InOutPortReg))
2474 {
2475 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2476 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2477 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2478 LONG_MNEM_SUFFIX);
2479 break;
2480 }
2481 }
2482 else if (i.suffix == BYTE_MNEM_SUFFIX)
2483 {
2484 if (!check_byte_reg ())
2485 return 0;
2486 }
2487 else if (i.suffix == LONG_MNEM_SUFFIX)
2488 {
2489 if (!check_long_reg ())
2490 return 0;
2491 }
2492 else if (i.suffix == QWORD_MNEM_SUFFIX)
2493 {
2494 if (!check_qword_reg ())
2495 return 0;
2496 }
2497 else if (i.suffix == WORD_MNEM_SUFFIX)
2498 {
2499 if (!check_word_reg ())
2500 return 0;
2501 }
2502 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2503 /* Do nothing if the instruction is going to ignore the prefix. */
2504 ;
2505 else
2506 abort ();
2507 }
9306ca4a
JB		 2508 else if ((i.tm.opcode_modifier & DefaultSize)
2509 && !i.suffix
2510 /* exclude fldenv/frstor/fsave/fstenv */
2511 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2512 {
2513 i.suffix = stackop_size;
2514 }
9306ca4a
JB		 2515 else if (intel_syntax
2516 && !i.suffix
2517 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2518 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2519 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2520 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2521 {
2522 switch (flag_code)
2523 {
2524 case CODE_64BIT:
2525 if (!(i.tm.opcode_modifier & No_qSuf))
2526 {
2527 i.suffix = QWORD_MNEM_SUFFIX;
2528 break;
2529 }
2530 case CODE_32BIT:
2531 if (!(i.tm.opcode_modifier & No_lSuf))
2532 i.suffix = LONG_MNEM_SUFFIX;
2533 break;
2534 case CODE_16BIT:
2535 if (!(i.tm.opcode_modifier & No_wSuf))
2536 i.suffix = WORD_MNEM_SUFFIX;
2537 break;
2538 }
2539 }
252b5132 2540
9306ca4a 2541 if (!i.suffix)
29b0f896 2542 {
9306ca4a
JB		 2543 if (!intel_syntax)
2544 {
2545 if (i.tm.opcode_modifier & W)
2546 {
2547 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2548 return 0;
2549 }
2550 }
2551 else
2552 {
64e74474
AM		 2553 unsigned int suffixes = (~i.tm.opcode_modifier
2554 & (No_bSuf
2555 | No_wSuf
2556 | No_lSuf
2557 | No_sSuf
2558 | No_xSuf
2559 | No_qSuf));
9306ca4a
JB		 2560
2561 if ((i.tm.opcode_modifier & W)
2562 || ((suffixes & (suffixes - 1))
2563 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2564 {
2565 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2566 return 0;
2567 }
2568 }
29b0f896 2569 }
252b5132 2570
9306ca4a
JB		 2571 /* Change the opcode based on the operand size given by i.suffix;
2572 We don't need to change things for byte insns. */
2573
29b0f896
AM		 2574 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2575 {
2576 /* It's not a byte, select word/dword operation. */
2577 if (i.tm.opcode_modifier & W)
2578 {
2579 if (i.tm.opcode_modifier & ShortForm)
2580 i.tm.base_opcode |= 8;
2581 else
2582 i.tm.base_opcode |= 1;
2583 }
0f3f3d8b 2584
29b0f896
AM		 2585 /* Now select between word & dword operations via the operand
2586 size prefix, except for instructions that will ignore this
2587 prefix anyway. */
cb712a9e
L		 2588 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2589 {
2590 /* monitor in SSE3 is a very special case. The default size
2591 of AX is the size of mode. The address size override
2592 prefix will change the size of AX. */
2593 if (i.op->regs[0].reg_type &
2594 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2595 if (!add_prefix (ADDR_PREFIX_OPCODE))
2596 return 0;
2597 }
2598 else if (i.suffix != QWORD_MNEM_SUFFIX
2599 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2600 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2601 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2602 || (flag_code == CODE_64BIT
2603 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2604 {
2605 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2606
29b0f896
AM		 2607 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2608 prefix = ADDR_PREFIX_OPCODE;
252b5132 2609
29b0f896
AM		 2610 if (!add_prefix (prefix))
2611 return 0;
24eab124 2612 }
252b5132 2613
29b0f896
AM		 2614 /* Set mode64 for an operand. */
2615 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2616 && flag_code == CODE_64BIT
29b0f896 2617 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2618 {
2619 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2620 need rex64. */
2621 if (i.operands != 2
2622 || i.types [0] != (Acc | Reg64)
2623 || i.types [1] != (Acc | Reg64)
2624 || strcmp (i.tm.name, "xchg") != 0)
2625 i.rex |= REX_MODE64;
2626 }
3e73aa7c 2627
29b0f896
AM		 2628 /* Size floating point instruction. */
2629 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2630 if (i.tm.opcode_modifier & FloatMF)
2631 i.tm.base_opcode ^= 4;
29b0f896 2632 }
7ecd2f8b 2633
29b0f896
AM		 2634 return 1;
2635}
3e73aa7c 2636
29b0f896 2637static int
543613e9 2638check_byte_reg (void)
29b0f896
AM		 2639{
2640 int op;
543613e9 2641
29b0f896
AM		 2642 for (op = i.operands; --op >= 0;)
2643 {
2644 /* If this is an eight bit register, it's OK. If it's the 16 or
2645 32 bit version of an eight bit register, we will just use the
2646 low portion, and that's OK too. */
2647 if (i.types[op] & Reg8)
2648 continue;
2649
2650 /* movzx and movsx should not generate this warning. */
2651 if (intel_syntax
2652 && (i.tm.base_opcode == 0xfb7
2653 || i.tm.base_opcode == 0xfb6
2654 || i.tm.base_opcode == 0x63
2655 || i.tm.base_opcode == 0xfbe
2656 || i.tm.base_opcode == 0xfbf))
2657 continue;
2658
65ec77d2 2659 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2660 {
2661 /* Prohibit these changes in the 64bit mode, since the
2662 lowering is more complicated. */
2663 if (flag_code == CODE_64BIT
2664 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2665 {
0f3f3d8b 2666 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2667 i.op[op].regs->reg_name,
2668 i.suffix);
2669 return 0;
2670 }
2671#if REGISTER_WARNINGS
2672 if (!quiet_warnings
2673 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2674 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2675 (i.op[op].regs + (i.types[op] & Reg16
2676 ? REGNAM_AL - REGNAM_AX
2677 : REGNAM_AL - REGNAM_EAX))->reg_name,
2678 i.op[op].regs->reg_name,
2679 i.suffix);
2680#endif
2681 continue;
2682 }
2683 /* Any other register is bad. */
2684 if (i.types[op] & (Reg | RegMMX | RegXMM
2685 | SReg2 | SReg3
2686 | Control | Debug | Test
2687 | FloatReg | FloatAcc))
2688 {
2689 as_bad (_("`%%%s' not allowed with `%s%c'"),
2690 i.op[op].regs->reg_name,
2691 i.tm.name,
2692 i.suffix);
2693 return 0;
2694 }
2695 }
2696 return 1;
2697}
2698
2699static int
2700check_long_reg ()
2701{
2702 int op;
2703
2704 for (op = i.operands; --op >= 0;)
2705 /* Reject eight bit registers, except where the template requires
2706 them. (eg. movzb) */
2707 if ((i.types[op] & Reg8) != 0
2708 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2709 {
2710 as_bad (_("`%%%s' not allowed with `%s%c'"),
2711 i.op[op].regs->reg_name,
2712 i.tm.name,
2713 i.suffix);
2714 return 0;
2715 }
2716 /* Warn if the e prefix on a general reg is missing. */
2717 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2718 && (i.types[op] & Reg16) != 0
2719 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2720 {
2721 /* Prohibit these changes in the 64bit mode, since the
2722 lowering is more complicated. */
2723 if (flag_code == CODE_64BIT)
252b5132 2724 {
0f3f3d8b 2725 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2726 i.op[op].regs->reg_name,
2727 i.suffix);
2728 return 0;
252b5132 2729 }
29b0f896
AM		 2730#if REGISTER_WARNINGS
2731 else
2732 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2733 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2734 i.op[op].regs->reg_name,
2735 i.suffix);
2736#endif
252b5132 2737 }
29b0f896
AM		 2738 /* Warn if the r prefix on a general reg is missing. */
2739 else if ((i.types[op] & Reg64) != 0
2740 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2741 {
0f3f3d8b 2742 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2743 i.op[op].regs->reg_name,
2744 i.suffix);
2745 return 0;
2746 }
2747 return 1;
2748}
252b5132 2749
29b0f896
AM		 2750static int
2751check_qword_reg ()
2752{
2753 int op;
252b5132 2754
29b0f896
AM		 2755 for (op = i.operands; --op >= 0; )
2756 /* Reject eight bit registers, except where the template requires
2757 them. (eg. movzb) */
2758 if ((i.types[op] & Reg8) != 0
2759 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2760 {
2761 as_bad (_("`%%%s' not allowed with `%s%c'"),
2762 i.op[op].regs->reg_name,
2763 i.tm.name,
2764 i.suffix);
2765 return 0;
2766 }
2767 /* Warn if the e prefix on a general reg is missing. */
2768 else if (((i.types[op] & Reg16) != 0
2769 || (i.types[op] & Reg32) != 0)
2770 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2771 {
2772 /* Prohibit these changes in the 64bit mode, since the
2773 lowering is more complicated. */
0f3f3d8b 2774 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2775 i.op[op].regs->reg_name,
2776 i.suffix);
2777 return 0;
252b5132 2778 }
29b0f896
AM		 2779 return 1;
2780}
252b5132 2781
29b0f896
AM		 2782static int
2783check_word_reg ()
2784{
2785 int op;
2786 for (op = i.operands; --op >= 0;)
2787 /* Reject eight bit registers, except where the template requires
2788 them. (eg. movzb) */
2789 if ((i.types[op] & Reg8) != 0
2790 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2791 {
2792 as_bad (_("`%%%s' not allowed with `%s%c'"),
2793 i.op[op].regs->reg_name,
2794 i.tm.name,
2795 i.suffix);
2796 return 0;
2797 }
2798 /* Warn if the e prefix on a general reg is present. */
2799 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2800 && (i.types[op] & Reg32) != 0
2801 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2802 {
29b0f896
AM		 2803 /* Prohibit these changes in the 64bit mode, since the
2804 lowering is more complicated. */
2805 if (flag_code == CODE_64BIT)
252b5132 2806 {
0f3f3d8b 2807 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2808 i.op[op].regs->reg_name,
2809 i.suffix);
2810 return 0;
252b5132 2811 }
29b0f896
AM		 2812 else
2813#if REGISTER_WARNINGS
2814 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2815 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2816 i.op[op].regs->reg_name,
2817 i.suffix);
2818#endif
2819 }
2820 return 1;
2821}
252b5132 2822
29b0f896
AM		 2823static int
2824finalize_imm ()
2825{
2826 unsigned int overlap0, overlap1, overlap2;
2827
2828 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2829 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2830 && overlap0 != Imm8 && overlap0 != Imm8S
2831 && overlap0 != Imm16 && overlap0 != Imm32S
2832 && overlap0 != Imm32 && overlap0 != Imm64)
2833 {
2834 if (i.suffix)
2835 {
2836 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2837 ? Imm8 | Imm8S
2838 : (i.suffix == WORD_MNEM_SUFFIX
2839 ? Imm16
2840 : (i.suffix == QWORD_MNEM_SUFFIX
2841 ? Imm64 | Imm32S
2842 : Imm32)));
2843 }
2844 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2845 || overlap0 == (Imm16 | Imm32)
2846 || overlap0 == (Imm16 | Imm32S))
2847 {
2848 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2849 ? Imm16 : Imm32S);
2850 }
2851 if (overlap0 != Imm8 && overlap0 != Imm8S
2852 && overlap0 != Imm16 && overlap0 != Imm32S
2853 && overlap0 != Imm32 && overlap0 != Imm64)
2854 {
2855 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2856 return 0;
2857 }
2858 }
2859 i.types[0] = overlap0;
2860
2861 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2862 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2863 && overlap1 != Imm8 && overlap1 != Imm8S
2864 && overlap1 != Imm16 && overlap1 != Imm32S
2865 && overlap1 != Imm32 && overlap1 != Imm64)
2866 {
2867 if (i.suffix)
2868 {
2869 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2870 ? Imm8 | Imm8S
2871 : (i.suffix == WORD_MNEM_SUFFIX
2872 ? Imm16
2873 : (i.suffix == QWORD_MNEM_SUFFIX
2874 ? Imm64 | Imm32S
2875 : Imm32)));
2876 }
2877 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2878 || overlap1 == (Imm16 | Imm32)
2879 || overlap1 == (Imm16 | Imm32S))
2880 {
2881 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2882 ? Imm16 : Imm32S);
2883 }
2884 if (overlap1 != Imm8 && overlap1 != Imm8S
2885 && overlap1 != Imm16 && overlap1 != Imm32S
2886 && overlap1 != Imm32 && overlap1 != Imm64)
2887 {
2888 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2889 return 0;
2890 }
2891 }
2892 i.types[1] = overlap1;
2893
2894 overlap2 = i.types[2] & i.tm.operand_types[2];
2895 assert ((overlap2 & Imm) == 0);
2896 i.types[2] = overlap2;
2897
2898 return 1;
2899}
2900
2901static int
2902process_operands ()
2903{
2904 /* Default segment register this instruction will use for memory
2905 accesses. 0 means unknown. This is only for optimizing out
2906 unnecessary segment overrides. */
2907 const seg_entry *default_seg = 0;
2908
2909 /* The imul $imm, %reg instruction is converted into
2910 imul $imm, %reg, %reg, and the clr %reg instruction
2911 is converted into xor %reg, %reg. */
2912 if (i.tm.opcode_modifier & regKludge)
2913 {
2914 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2915 /* Pretend we saw the extra register operand. */
2916 assert (i.op[first_reg_op + 1].regs == 0);
2917 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2918 i.types[first_reg_op + 1] = i.types[first_reg_op];
2919 i.reg_operands = 2;
2920 }
2921
2922 if (i.tm.opcode_modifier & ShortForm)
2923 {
2924 /* The register or float register operand is in operand 0 or 1. */
2925 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2926 /* Register goes in low 3 bits of opcode. */
2927 i.tm.base_opcode |= i.op[op].regs->reg_num;
2928 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2929 i.rex |= REX_EXTZ;
2930 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2931 {
2932 /* Warn about some common errors, but press on regardless.
2933 The first case can be generated by gcc (<= 2.8.1). */
2934 if (i.operands == 2)
2935 {
2936 /* Reversed arguments on faddp, fsubp, etc. */
2937 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2938 i.op[1].regs->reg_name,
2939 i.op[0].regs->reg_name);
2940 }
2941 else
2942 {
2943 /* Extraneous `l' suffix on fp insn. */
2944 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2945 i.op[0].regs->reg_name);
2946 }
2947 }
2948 }
2949 else if (i.tm.opcode_modifier & Modrm)
2950 {
2951 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2952 must be put into the modrm byte). Now, we make the modrm and
2953 index base bytes based on all the info we've collected. */
29b0f896
AM		 2954
2955 default_seg = build_modrm_byte ();
2956 }
2957 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2958 {
2959 if (i.tm.base_opcode == POP_SEG_SHORT
2960 && i.op[0].regs->reg_num == 1)
2961 {
2962 as_bad (_("you can't `pop %%cs'"));
2963 return 0;
2964 }
2965 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2966 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2967 i.rex |= REX_EXTZ;
2968 }
2969 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2970 {
2971 default_seg = &ds;
2972 }
2973 else if ((i.tm.opcode_modifier & IsString) != 0)
2974 {
2975 /* For the string instructions that allow a segment override
2976 on one of their operands, the default segment is ds. */
2977 default_seg = &ds;
2978 }
2979
30123838
JB		 2980 if ((i.tm.base_opcode == 0x8d /* lea */
2981 || (i.tm.cpu_flags & CpuSVME))
2982 && i.seg[0] && !quiet_warnings)
2983 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2984
2985 /* If a segment was explicitly specified, and the specified segment
2986 is not the default, use an opcode prefix to select it. If we
2987 never figured out what the default segment is, then default_seg
2988 will be zero at this point, and the specified segment prefix will
2989 always be used. */
29b0f896
AM		 2990 if ((i.seg[0]) && (i.seg[0] != default_seg))
2991 {
2992 if (!add_prefix (i.seg[0]->seg_prefix))
2993 return 0;
2994 }
2995 return 1;
2996}
2997
2998static const seg_entry *
2999build_modrm_byte ()
3000{
3001 const seg_entry *default_seg = 0;
3002
3003 /* i.reg_operands MUST be the number of real register operands;
3004 implicit registers do not count. */
3005 if (i.reg_operands == 2)
3006 {
3007 unsigned int source, dest;
3008 source = ((i.types[0]
3009 & (Reg | RegMMX | RegXMM
3010 | SReg2 | SReg3
3011 | Control | Debug | Test))
3012 ? 0 : 1);
3013 dest = source + 1;
3014
3015 i.rm.mode = 3;
3016 /* One of the register operands will be encoded in the i.tm.reg
3017 field, the other in the combined i.tm.mode and i.tm.regmem
3018 fields. If no form of this instruction supports a memory
3019 destination operand, then we assume the source operand may
3020 sometimes be a memory operand and so we need to store the
3021 destination in the i.rm.reg field. */
3022 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3023 {
3024 i.rm.reg = i.op[dest].regs->reg_num;
3025 i.rm.regmem = i.op[source].regs->reg_num;
3026 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3027 i.rex |= REX_EXTX;
3028 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3029 i.rex |= REX_EXTZ;
3030 }
3031 else
3032 {
3033 i.rm.reg = i.op[source].regs->reg_num;
3034 i.rm.regmem = i.op[dest].regs->reg_num;
3035 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3036 i.rex |= REX_EXTZ;
3037 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3038 i.rex |= REX_EXTX;
3039 }
c4a530c5
JB		 3040 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3041 {
3042 if (!((i.types[0] | i.types[1]) & Control))
3043 abort ();
3044 i.rex &= ~(REX_EXTX | REX_EXTZ);
3045 add_prefix (LOCK_PREFIX_OPCODE);
3046 }
29b0f896
AM		 3047 }
3048 else
3049 { /* If it's not 2 reg operands... */
3050 if (i.mem_operands)
3051 {
3052 unsigned int fake_zero_displacement = 0;
3053 unsigned int op = ((i.types[0] & AnyMem)
3054 ? 0
3055 : (i.types[1] & AnyMem) ? 1 : 2);
3056
3057 default_seg = &ds;
3058
3059 if (i.base_reg == 0)
3060 {
3061 i.rm.mode = 0;
3062 if (!i.disp_operands)
3063 fake_zero_displacement = 1;
3064 if (i.index_reg == 0)
3065 {
3066 /* Operand is just <disp> */
20f0a1fc 3067 if (flag_code == CODE_64BIT)
29b0f896
AM		 3068 {
3069 /* 64bit mode overwrites the 32bit absolute
3070 addressing by RIP relative addressing and
3071 absolute addressing is encoded by one of the
3072 redundant SIB forms. */
3073 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3074 i.sib.base = NO_BASE_REGISTER;
3075 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3076 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3077 }
3078 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3079 {
3080 i.rm.regmem = NO_BASE_REGISTER_16;
3081 i.types[op] = Disp16;
3082 }
3083 else
3084 {
3085 i.rm.regmem = NO_BASE_REGISTER;
3086 i.types[op] = Disp32;
29b0f896
AM		 3087 }
3088 }
3089 else /* !i.base_reg && i.index_reg */
3090 {
3091 i.sib.index = i.index_reg->reg_num;
3092 i.sib.base = NO_BASE_REGISTER;
3093 i.sib.scale = i.log2_scale_factor;
3094 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3095 i.types[op] &= ~Disp;
3096 if (flag_code != CODE_64BIT)
3097 i.types[op] |= Disp32; /* Must be 32 bit */
3098 else
3099 i.types[op] |= Disp32S;
3100 if ((i.index_reg->reg_flags & RegRex) != 0)
3101 i.rex |= REX_EXTY;
3102 }
3103 }
3104 /* RIP addressing for 64bit mode. */
3105 else if (i.base_reg->reg_type == BaseIndex)
3106 {
3107 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3108 i.types[op] &= ~ Disp;
29b0f896
AM		 3109 i.types[op] |= Disp32S;
3110 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3111 if (! i.disp_operands)
3112 fake_zero_displacement = 1;
29b0f896
AM		 3113 }
3114 else if (i.base_reg->reg_type & Reg16)
3115 {
3116 switch (i.base_reg->reg_num)
3117 {
3118 case 3: /* (%bx) */
3119 if (i.index_reg == 0)
3120 i.rm.regmem = 7;
3121 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3122 i.rm.regmem = i.index_reg->reg_num - 6;
3123 break;
3124 case 5: /* (%bp) */
3125 default_seg = &ss;
3126 if (i.index_reg == 0)
3127 {
3128 i.rm.regmem = 6;
3129 if ((i.types[op] & Disp) == 0)
3130 {
3131 /* fake (%bp) into 0(%bp) */
3132 i.types[op] |= Disp8;
252b5132 3133 fake_zero_displacement = 1;
29b0f896
AM		 3134 }
3135 }
3136 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3137 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3138 break;
3139 default: /* (%si) -> 4 or (%di) -> 5 */
3140 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3141 }
3142 i.rm.mode = mode_from_disp_size (i.types[op]);
3143 }
3144 else /* i.base_reg and 32/64 bit mode */
3145 {
3146 if (flag_code == CODE_64BIT
3147 && (i.types[op] & Disp))
20f0a1fc
NC		 3148 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3149
29b0f896
AM		 3150 i.rm.regmem = i.base_reg->reg_num;
3151 if ((i.base_reg->reg_flags & RegRex) != 0)
3152 i.rex |= REX_EXTZ;
3153 i.sib.base = i.base_reg->reg_num;
3154 /* x86-64 ignores REX prefix bit here to avoid decoder
3155 complications. */
3156 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3157 {
3158 default_seg = &ss;
3159 if (i.disp_operands == 0)
3160 {
3161 fake_zero_displacement = 1;
3162 i.types[op] |= Disp8;
3163 }
3164 }
3165 else if (i.base_reg->reg_num == ESP_REG_NUM)
3166 {
3167 default_seg = &ss;
3168 }
3169 i.sib.scale = i.log2_scale_factor;
3170 if (i.index_reg == 0)
3171 {
3172 /* <disp>(%esp) becomes two byte modrm with no index
3173 register. We've already stored the code for esp
3174 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3175 Any base register besides %esp will not use the
3176 extra modrm byte. */
3177 i.sib.index = NO_INDEX_REGISTER;
3178#if !SCALE1_WHEN_NO_INDEX
3179 /* Another case where we force the second modrm byte. */
3180 if (i.log2_scale_factor)
3181 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3182#endif
29b0f896
AM		 3183 }
3184 else
3185 {
3186 i.sib.index = i.index_reg->reg_num;
3187 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3188 if ((i.index_reg->reg_flags & RegRex) != 0)
3189 i.rex |= REX_EXTY;
3190 }
67a4f2b7
AO		 3191
3192 if (i.disp_operands
3193 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3194 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3195 i.rm.mode = 0;
3196 else
3197 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3198 }
252b5132 3199
29b0f896
AM		 3200 if (fake_zero_displacement)
3201 {
3202 /* Fakes a zero displacement assuming that i.types[op]
3203 holds the correct displacement size. */
3204 expressionS *exp;
3205
3206 assert (i.op[op].disps == 0);
3207 exp = &disp_expressions[i.disp_operands++];
3208 i.op[op].disps = exp;
3209 exp->X_op = O_constant;
3210 exp->X_add_number = 0;
3211 exp->X_add_symbol = (symbolS *) 0;
3212 exp->X_op_symbol = (symbolS *) 0;
3213 }
3214 }
252b5132 3215
29b0f896
AM		 3216 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3217 (if any) based on i.tm.extension_opcode. Again, we must be
3218 careful to make sure that segment/control/debug/test/MMX
3219 registers are coded into the i.rm.reg field. */
3220 if (i.reg_operands)
3221 {
3222 unsigned int op =
3223 ((i.types[0]
3224 & (Reg | RegMMX | RegXMM
3225 | SReg2 | SReg3
3226 | Control | Debug | Test))
3227 ? 0
3228 : ((i.types[1]
3229 & (Reg | RegMMX | RegXMM
3230 | SReg2 | SReg3
3231 | Control | Debug | Test))
3232 ? 1
3233 : 2));
3234 /* If there is an extension opcode to put here, the register
3235 number must be put into the regmem field. */
3236 if (i.tm.extension_opcode != None)
3237 {
3238 i.rm.regmem = i.op[op].regs->reg_num;
3239 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3240 i.rex |= REX_EXTZ;
3241 }
3242 else
3243 {
3244 i.rm.reg = i.op[op].regs->reg_num;
3245 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3246 i.rex |= REX_EXTX;
3247 }
252b5132 3248
29b0f896
AM		 3249 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3250 must set it to 3 to indicate this is a register operand
3251 in the regmem field. */
3252 if (!i.mem_operands)
3253 i.rm.mode = 3;
3254 }
252b5132 3255
29b0f896
AM		 3256 /* Fill in i.rm.reg field with extension opcode (if any). */
3257 if (i.tm.extension_opcode != None)
3258 i.rm.reg = i.tm.extension_opcode;
3259 }
3260 return default_seg;
3261}
252b5132 3262
29b0f896
AM		 3263static void
3264output_branch ()
3265{
3266 char *p;
3267 int code16;
3268 int prefix;
3269 relax_substateT subtype;
3270 symbolS *sym;
3271 offsetT off;
3272
3273 code16 = 0;
3274 if (flag_code == CODE_16BIT)
3275 code16 = CODE16;
3276
3277 prefix = 0;
3278 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3279 {
29b0f896
AM		 3280 prefix = 1;
3281 i.prefixes -= 1;
3282 code16 ^= CODE16;
252b5132 3283 }
29b0f896
AM		 3284 /* Pentium4 branch hints. */
3285 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3286 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3287 {
29b0f896
AM		 3288 prefix++;
3289 i.prefixes--;
3290 }
3291 if (i.prefix[REX_PREFIX] != 0)
3292 {
3293 prefix++;
3294 i.prefixes--;
2f66722d
AM		 3295 }
3296
29b0f896
AM		 3297 if (i.prefixes != 0 && !intel_syntax)
3298 as_warn (_("skipping prefixes on this instruction"));
3299
3300 /* It's always a symbol; End frag & setup for relax.
3301 Make sure there is enough room in this frag for the largest
3302 instruction we may generate in md_convert_frag. This is 2
3303 bytes for the opcode and room for the prefix and largest
3304 displacement. */
3305 frag_grow (prefix + 2 + 4);
3306 /* Prefix and 1 opcode byte go in fr_fix. */
3307 p = frag_more (prefix + 1);
3308 if (i.prefix[DATA_PREFIX] != 0)
3309 *p++ = DATA_PREFIX_OPCODE;
3310 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3311 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3312 *p++ = i.prefix[SEG_PREFIX];
3313 if (i.prefix[REX_PREFIX] != 0)
3314 *p++ = i.prefix[REX_PREFIX];
3315 *p = i.tm.base_opcode;
3316
3317 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3318 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3319 else if ((cpu_arch_flags & Cpu386) != 0)
3320 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3321 else
3322 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3323 subtype |= code16;
3e73aa7c 3324
29b0f896
AM		 3325 sym = i.op[0].disps->X_add_symbol;
3326 off = i.op[0].disps->X_add_number;
3e73aa7c 3327
29b0f896
AM		 3328 if (i.op[0].disps->X_op != O_constant
3329 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3330 {
29b0f896
AM		 3331 /* Handle complex expressions. */
3332 sym = make_expr_symbol (i.op[0].disps);
3333 off = 0;
3334 }
3e73aa7c 3335
29b0f896
AM		 3336 /* 1 possible extra opcode + 4 byte displacement go in var part.
3337 Pass reloc in fr_var. */
3338 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3339}
3e73aa7c 3340
29b0f896
AM		 3341static void
3342output_jump ()
3343{
3344 char *p;
3345 int size;
3e02c1cc 3346 fixS *fixP;
29b0f896
AM		 3347
3348 if (i.tm.opcode_modifier & JumpByte)
3349 {
3350 /* This is a loop or jecxz type instruction. */
3351 size = 1;
3352 if (i.prefix[ADDR_PREFIX] != 0)
3353 {
3354 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3355 i.prefixes -= 1;
3356 }
3357 /* Pentium4 branch hints. */
3358 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3359 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3360 {
3361 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3362 i.prefixes--;
3e73aa7c
JH		 3363 }
3364 }
29b0f896
AM		 3365 else
3366 {
3367 int code16;
3e73aa7c 3368
29b0f896
AM		 3369 code16 = 0;
3370 if (flag_code == CODE_16BIT)
3371 code16 = CODE16;
3e73aa7c 3372
29b0f896
AM		 3373 if (i.prefix[DATA_PREFIX] != 0)
3374 {
3375 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3376 i.prefixes -= 1;
3377 code16 ^= CODE16;
3378 }
252b5132 3379
29b0f896
AM		 3380 size = 4;
3381 if (code16)
3382 size = 2;
3383 }
9fcc94b6 3384
29b0f896
AM		 3385 if (i.prefix[REX_PREFIX] != 0)
3386 {
3387 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3388 i.prefixes -= 1;
3389 }
252b5132 3390
29b0f896
AM		 3391 if (i.prefixes != 0 && !intel_syntax)
3392 as_warn (_("skipping prefixes on this instruction"));
e0890092 3393
29b0f896
AM		 3394 p = frag_more (1 + size);
3395 *p++ = i.tm.base_opcode;
e0890092 3396
3e02c1cc
AM		 3397 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3398 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3399
3400 /* All jumps handled here are signed, but don't use a signed limit
3401 check for 32 and 16 bit jumps as we want to allow wrap around at
3402 4G and 64k respectively. */
3403 if (size == 1)
3404 fixP->fx_signed = 1;
29b0f896 3405}
e0890092 3406
29b0f896
AM		 3407static void
3408output_interseg_jump ()
3409{
3410 char *p;
3411 int size;
3412 int prefix;
3413 int code16;
252b5132 3414
29b0f896
AM		 3415 code16 = 0;
3416 if (flag_code == CODE_16BIT)
3417 code16 = CODE16;
a217f122 3418
29b0f896
AM		 3419 prefix = 0;
3420 if (i.prefix[DATA_PREFIX] != 0)
3421 {
3422 prefix = 1;
3423 i.prefixes -= 1;
3424 code16 ^= CODE16;
3425 }
3426 if (i.prefix[REX_PREFIX] != 0)
3427 {
3428 prefix++;
3429 i.prefixes -= 1;
3430 }
252b5132 3431
29b0f896
AM		 3432 size = 4;
3433 if (code16)
3434 size = 2;
252b5132 3435
29b0f896
AM		 3436 if (i.prefixes != 0 && !intel_syntax)
3437 as_warn (_("skipping prefixes on this instruction"));
252b5132 3438
29b0f896
AM		 3439 /* 1 opcode; 2 segment; offset */
3440 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3441
29b0f896
AM		 3442 if (i.prefix[DATA_PREFIX] != 0)
3443 *p++ = DATA_PREFIX_OPCODE;
252b5132 3444
29b0f896
AM		 3445 if (i.prefix[REX_PREFIX] != 0)
3446 *p++ = i.prefix[REX_PREFIX];
252b5132 3447
29b0f896
AM		 3448 *p++ = i.tm.base_opcode;
3449 if (i.op[1].imms->X_op == O_constant)
3450 {
3451 offsetT n = i.op[1].imms->X_add_number;
252b5132 3452
29b0f896
AM		 3453 if (size == 2
3454 && !fits_in_unsigned_word (n)
3455 && !fits_in_signed_word (n))
3456 {
3457 as_bad (_("16-bit jump out of range"));
3458 return;
3459 }
3460 md_number_to_chars (p, n, size);
3461 }
3462 else
3463 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3464 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3465 if (i.op[0].imms->X_op != O_constant)
3466 as_bad (_("can't handle non absolute segment in `%s'"),
3467 i.tm.name);
3468 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3469}
a217f122 3470
29b0f896
AM		 3471static void
3472output_insn ()
3473{
2bbd9c25
JJ		 3474 fragS *insn_start_frag;
3475 offsetT insn_start_off;
3476
29b0f896
AM		 3477 /* Tie dwarf2 debug info to the address at the start of the insn.
3478 We can't do this after the insn has been output as the current
3479 frag may have been closed off. eg. by frag_var. */
3480 dwarf2_emit_insn (0);
3481
2bbd9c25
JJ		 3482 insn_start_frag = frag_now;
3483 insn_start_off = frag_now_fix ();
3484
29b0f896
AM		 3485 /* Output jumps. */
3486 if (i.tm.opcode_modifier & Jump)
3487 output_branch ();
3488 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3489 output_jump ();
3490 else if (i.tm.opcode_modifier & JumpInterSegment)
3491 output_interseg_jump ();
3492 else
3493 {
3494 /* Output normal instructions here. */
3495 char *p;
3496 unsigned char *q;
331d2d0d 3497 unsigned int prefix;
252b5132 3498
331d2d0d
L		 3499 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3500 Instructions have 3 bytes. We may use one more higher byte
3501 to specify a prefix the instruction requires. */
3502 if ((i.tm.cpu_flags & CpuMNI) != 0)
bc4bd9ab 3503 {
331d2d0d
L		 3504 if (i.tm.base_opcode & 0xff000000)
3505 {
3506 prefix = (i.tm.base_opcode >> 24) & 0xff;
3507 goto check_prefix;
3508 }
3509 }
3510 else if ((i.tm.base_opcode & 0xff0000) != 0)
3511 {
3512 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3513 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3514 {
64e74474 3515 check_prefix:
bc4bd9ab
MK		 3516 if (prefix != REPE_PREFIX_OPCODE
3517 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3518 add_prefix (prefix);
3519 }
3520 else
331d2d0d 3521 add_prefix (prefix);
0f10071e 3522 }
252b5132 3523
29b0f896
AM		 3524 /* The prefix bytes. */
3525 for (q = i.prefix;
3526 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3527 q++)
3528 {
3529 if (*q)
3530 {
3531 p = frag_more (1);
3532 md_number_to_chars (p, (valueT) *q, 1);
3533 }
3534 }
252b5132 3535
29b0f896
AM		 3536 /* Now the opcode; be careful about word order here! */
3537 if (fits_in_unsigned_byte (i.tm.base_opcode))
3538 {
3539 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3540 }
3541 else
3542 {
331d2d0d
L		 3543 if ((i.tm.cpu_flags & CpuMNI) != 0)
3544 {
3545 p = frag_more (3);
3546 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3547 }
3548 else
3549 p = frag_more (2);
0f10071e 3550
29b0f896
AM		 3551 /* Put out high byte first: can't use md_number_to_chars! */
3552 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3553 *p = i.tm.base_opcode & 0xff;
3554 }
3e73aa7c 3555
29b0f896
AM		 3556 /* Now the modrm byte and sib byte (if present). */
3557 if (i.tm.opcode_modifier & Modrm)
3558 {
3559 p = frag_more (1);
3560 md_number_to_chars (p,
3561 (valueT) (i.rm.regmem << 0
3562 | i.rm.reg << 3
3563 | i.rm.mode << 6),
3564 1);
3565 /* If i.rm.regmem == ESP (4)
3566 && i.rm.mode != (Register mode)
3567 && not 16 bit
3568 ==> need second modrm byte. */
3569 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3570 && i.rm.mode != 3
3571 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3572 {
3573 p = frag_more (1);
3574 md_number_to_chars (p,
3575 (valueT) (i.sib.base << 0
3576 | i.sib.index << 3
3577 | i.sib.scale << 6),
3578 1);
3579 }
3580 }
3e73aa7c 3581
29b0f896 3582 if (i.disp_operands)
2bbd9c25 3583 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3584
29b0f896 3585 if (i.imm_operands)
2bbd9c25 3586 output_imm (insn_start_frag, insn_start_off);
29b0f896 3587 }
252b5132 3588
29b0f896
AM		 3589#ifdef DEBUG386
3590 if (flag_debug)
3591 {
7b81dfbb 3592 pi ("" /*line*/, &i);
29b0f896
AM		 3593 }
3594#endif /* DEBUG386 */
3595}
252b5132 3596
29b0f896 3597static void
64e74474 3598output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3599{
3600 char *p;
3601 unsigned int n;
252b5132 3602
29b0f896
AM		 3603 for (n = 0; n < i.operands; n++)
3604 {
3605 if (i.types[n] & Disp)
3606 {
3607 if (i.op[n].disps->X_op == O_constant)
3608 {
3609 int size;
3610 offsetT val;
252b5132 3611
29b0f896
AM		 3612 size = 4;
3613 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3614 {
3615 size = 2;
3616 if (i.types[n] & Disp8)
3617 size = 1;
3618 if (i.types[n] & Disp64)
3619 size = 8;
3620 }
3621 val = offset_in_range (i.op[n].disps->X_add_number,
3622 size);
3623 p = frag_more (size);
3624 md_number_to_chars (p, val, size);
3625 }
3626 else
3627 {
f86103b7 3628 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3629 int size = 4;
3630 int sign = 0;
3631 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3632
3633 /* The PC relative address is computed relative
3634 to the instruction boundary, so in case immediate
3635 fields follows, we need to adjust the value. */
3636 if (pcrel && i.imm_operands)
3637 {
3638 int imm_size = 4;
3639 unsigned int n1;
252b5132 3640
29b0f896
AM		 3641 for (n1 = 0; n1 < i.operands; n1++)
3642 if (i.types[n1] & Imm)
252b5132 3643 {
29b0f896 3644 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3645 {
29b0f896
AM		 3646 imm_size = 2;
3647 if (i.types[n1] & (Imm8 | Imm8S))
3648 imm_size = 1;
3649 if (i.types[n1] & Imm64)
3650 imm_size = 8;
252b5132 3651 }
29b0f896 3652 break;
252b5132 3653 }
29b0f896
AM		 3654 /* We should find the immediate. */
3655 if (n1 == i.operands)
3656 abort ();
3657 i.op[n].disps->X_add_number -= imm_size;
3658 }
520dc8e8 3659
29b0f896
AM		 3660 if (i.types[n] & Disp32S)
3661 sign = 1;
3e73aa7c 3662
29b0f896
AM		 3663 if (i.types[n] & (Disp16 | Disp64))
3664 {
3665 size = 2;
3666 if (i.types[n] & Disp64)
3667 size = 8;
3668 }
520dc8e8 3669
29b0f896 3670 p = frag_more (size);
2bbd9c25 3671 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3672 if (GOT_symbol
2bbd9c25 3673 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 3674 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 3675 || reloc_type == BFD_RELOC_X86_64_32S
3676 || (reloc_type == BFD_RELOC_64
3677 && object_64bit))
d6ab8113
JB		 3678 && (i.op[n].disps->X_op == O_symbol
3679 || (i.op[n].disps->X_op == O_add
3680 && ((symbol_get_value_expression
3681 (i.op[n].disps->X_op_symbol)->X_op)
3682 == O_subtract))))
3683 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3684 {
3685 offsetT add;
3686
3687 if (insn_start_frag == frag_now)
3688 add = (p - frag_now->fr_literal) - insn_start_off;
3689 else
3690 {
3691 fragS *fr;
3692
3693 add = insn_start_frag->fr_fix - insn_start_off;
3694 for (fr = insn_start_frag->fr_next;
3695 fr && fr != frag_now; fr = fr->fr_next)
3696 add += fr->fr_fix;
3697 add += p - frag_now->fr_literal;
3698 }
3699
4fa24527 3700 if (!object_64bit)
7b81dfbb
AJ		 3701 {
3702 reloc_type = BFD_RELOC_386_GOTPC;
3703 i.op[n].imms->X_add_number += add;
3704 }
3705 else if (reloc_type == BFD_RELOC_64)
3706 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 3707 else
7b81dfbb
AJ		 3708 /* Don't do the adjustment for x86-64, as there
3709 the pcrel addressing is relative to the _next_
3710 insn, and that is taken care of in other code. */
d6ab8113 3711 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3712 }
062cd5e7 3713 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3714 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3715 }
3716 }
3717 }
3718}
252b5132 3719
29b0f896 3720static void
64e74474 3721output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3722{
3723 char *p;
3724 unsigned int n;
252b5132 3725
29b0f896
AM		 3726 for (n = 0; n < i.operands; n++)
3727 {
3728 if (i.types[n] & Imm)
3729 {
3730 if (i.op[n].imms->X_op == O_constant)
3731 {
3732 int size;
3733 offsetT val;
b4cac588 3734
29b0f896
AM		 3735 size = 4;
3736 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3737 {
3738 size = 2;
3739 if (i.types[n] & (Imm8 | Imm8S))
3740 size = 1;
3741 else if (i.types[n] & Imm64)
3742 size = 8;
3743 }
3744 val = offset_in_range (i.op[n].imms->X_add_number,
3745 size);
3746 p = frag_more (size);
3747 md_number_to_chars (p, val, size);
3748 }
3749 else
3750 {
3751 /* Not absolute_section.
3752 Need a 32-bit fixup (don't support 8bit
3753 non-absolute imms). Try to support other
3754 sizes ... */
f86103b7 3755 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3756 int size = 4;
3757 int sign = 0;
3758
3759 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3760 && (i.suffix == QWORD_MNEM_SUFFIX
3761 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3762 sign = 1;
3763 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3764 {
3765 size = 2;
3766 if (i.types[n] & (Imm8 | Imm8S))
3767 size = 1;
3768 if (i.types[n] & Imm64)
3769 size = 8;
3770 }
520dc8e8 3771
29b0f896
AM		 3772 p = frag_more (size);
3773 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3774
2bbd9c25
JJ		 3775 /* This is tough to explain. We end up with this one if we
3776 * have operands that look like
3777 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3778 * obtain the absolute address of the GOT, and it is strongly
3779 * preferable from a performance point of view to avoid using
3780 * a runtime relocation for this. The actual sequence of
3781 * instructions often look something like:
3782 *
3783 * call .L66
3784 * .L66:
3785 * popl %ebx
3786 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3787 *
3788 * The call and pop essentially return the absolute address
3789 * of the label .L66 and store it in %ebx. The linker itself
3790 * will ultimately change the first operand of the addl so
3791 * that %ebx points to the GOT, but to keep things simple, the
3792 * .o file must have this operand set so that it generates not
3793 * the absolute address of .L66, but the absolute address of
3794 * itself. This allows the linker itself simply treat a GOTPC
3795 * relocation as asking for a pcrel offset to the GOT to be
3796 * added in, and the addend of the relocation is stored in the
3797 * operand field for the instruction itself.
3798 *
3799 * Our job here is to fix the operand so that it would add
3800 * the correct offset so that %ebx would point to itself. The
3801 * thing that is tricky is that .-.L66 will point to the
3802 * beginning of the instruction, so we need to further modify
3803 * the operand so that it will point to itself. There are
3804 * other cases where you have something like:
3805 *
3806 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3807 *
3808 * and here no correction would be required. Internally in
3809 * the assembler we treat operands of this form as not being
3810 * pcrel since the '.' is explicitly mentioned, and I wonder
3811 * whether it would simplify matters to do it this way. Who
3812 * knows. In earlier versions of the PIC patches, the
3813 * pcrel_adjust field was used to store the correction, but
3814 * since the expression is not pcrel, I felt it would be
3815 * confusing to do it this way. */
3816
d6ab8113 3817 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 3818 || reloc_type == BFD_RELOC_X86_64_32S
3819 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 3820 && GOT_symbol
3821 && GOT_symbol == i.op[n].imms->X_add_symbol
3822 && (i.op[n].imms->X_op == O_symbol
3823 || (i.op[n].imms->X_op == O_add
3824 && ((symbol_get_value_expression
3825 (i.op[n].imms->X_op_symbol)->X_op)
3826 == O_subtract))))
3827 {
2bbd9c25
JJ		 3828 offsetT add;
3829
3830 if (insn_start_frag == frag_now)
3831 add = (p - frag_now->fr_literal) - insn_start_off;
3832 else
3833 {
3834 fragS *fr;
3835
3836 add = insn_start_frag->fr_fix - insn_start_off;
3837 for (fr = insn_start_frag->fr_next;
3838 fr && fr != frag_now; fr = fr->fr_next)
3839 add += fr->fr_fix;
3840 add += p - frag_now->fr_literal;
3841 }
3842
4fa24527 3843 if (!object_64bit)
d6ab8113 3844 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 3845 else if (size == 4)
d6ab8113 3846 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 3847 else if (size == 8)
3848 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 3849 i.op[n].imms->X_add_number += add;
29b0f896 3850 }
29b0f896
AM		 3851 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3852 i.op[n].imms, 0, reloc_type);
3853 }
3854 }
3855 }
252b5132
RH		 3856}
3857\f
d182319b
JB		 3858/* x86_cons_fix_new is called via the expression parsing code when a
3859 reloc is needed. We use this hook to get the correct .got reloc. */
3860static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3861static int cons_sign = -1;
3862
3863void
3864x86_cons_fix_new (fragS *frag,
64e74474
AM		 3865 unsigned int off,
3866 unsigned int len,
3867 expressionS *exp)
d182319b
JB		 3868{
3869 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
3870
3871 got_reloc = NO_RELOC;
3872
3873#ifdef TE_PE
3874 if (exp->X_op == O_secrel)
3875 {
3876 exp->X_op = O_symbol;
3877 r = BFD_RELOC_32_SECREL;
3878 }
3879#endif
3880
3881 fix_new_exp (frag, off, len, exp, 0, r);
3882}
3883
718ddfc0
JB		 3884#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3885# define lex_got(reloc, adjust, types) NULL
3886#else
f3c180ae
AM		 3887/* Parse operands of the form
3888 <symbol>@GOTOFF+<nnn>
3889 and similar .plt or .got references.
3890
3891 If we find one, set up the correct relocation in RELOC and copy the
3892 input string, minus the `@GOTOFF' into a malloc'd buffer for
3893 parsing by the calling routine. Return this buffer, and if ADJUST
3894 is non-null set it to the length of the string we removed from the
3895 input line. Otherwise return NULL. */
3896static char *
3956db08 3897lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 3898 int *adjust,
3899 unsigned int *types)
f3c180ae 3900{
7b81dfbb
AJ		 3901 /* Some of the relocations depend on the size of what field is to
3902 be relocated. But in our callers i386_immediate and i386_displacement
3903 we don't yet know the operand size (this will be set by insn
3904 matching). Hence we record the word32 relocation here,
3905 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 3906 static const struct {
3907 const char *str;
4fa24527 3908 const enum bfd_reloc_code_real rel[2];
3956db08 3909 const unsigned int types64;
f3c180ae 3910 } gotrel[] = {
7b81dfbb 3911 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 3912 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 3913 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 3914 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3915 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3916 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3917 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3918 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3919 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3920 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3921 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3922 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3923 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3924 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 3925 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 3926 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
3927 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3928 };
3929 char *cp;
3930 unsigned int j;
3931
718ddfc0
JB		 3932 if (!IS_ELF)
3933 return NULL;
3934
f3c180ae
AM		 3935 for (cp = input_line_pointer; *cp != '@'; cp++)
3936 if (is_end_of_line[(unsigned char) *cp])
3937 return NULL;
3938
3939 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3940 {
3941 int len;
3942
3943 len = strlen (gotrel[j].str);
28f81592 3944 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 3945 {
4fa24527 3946 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 3947 {
28f81592
AM		 3948 int first, second;
3949 char *tmpbuf, *past_reloc;
f3c180ae 3950
4fa24527 3951 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 3952 if (adjust)
3953 *adjust = len;
f3c180ae 3954
3956db08
JB		 3955 if (types)
3956 {
3957 if (flag_code != CODE_64BIT)
3958 *types = Imm32|Disp32;
3959 else
3960 *types = gotrel[j].types64;
3961 }
3962
f3c180ae
AM		 3963 if (GOT_symbol == NULL)
3964 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3965
3966 /* Replace the relocation token with ' ', so that
3967 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3968
3969 /* The length of the first part of our input line. */
f3c180ae 3970 first = cp - input_line_pointer;
28f81592
AM		 3971
3972 /* The second part goes from after the reloc token until
3973 (and including) an end_of_line char. Don't use strlen
3974 here as the end_of_line char may not be a NUL. */
3975 past_reloc = cp + 1 + len;
3976 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3977 ;
3978 second = cp - past_reloc;
3979
3980 /* Allocate and copy string. The trailing NUL shouldn't
3981 be necessary, but be safe. */
3982 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3983 memcpy (tmpbuf, input_line_pointer, first);
3984 tmpbuf[first] = ' ';
28f81592
AM		 3985 memcpy (tmpbuf + first + 1, past_reloc, second);
3986 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3987 return tmpbuf;
3988 }
3989
4fa24527
JB		 3990 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3991 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 3992 return NULL;
3993 }
3994 }
3995
3996 /* Might be a symbol version string. Don't as_bad here. */
3997 return NULL;
3998}
3999
f3c180ae
AM		 4000void
4001x86_cons (exp, size)
4002 expressionS *exp;
4003 int size;
4004{
4fa24527 4005 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4006 {
4007 /* Handle @GOTOFF and the like in an expression. */
4008 char *save;
4009 char *gotfree_input_line;
4010 int adjust;
4011
4012 save = input_line_pointer;
3956db08 4013 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4014 if (gotfree_input_line)
4015 input_line_pointer = gotfree_input_line;
4016
4017 expression (exp);
4018
4019 if (gotfree_input_line)
4020 {
4021 /* expression () has merrily parsed up to the end of line,
4022 or a comma - in the wrong buffer. Transfer how far
4023 input_line_pointer has moved to the right buffer. */
4024 input_line_pointer = (save
4025 + (input_line_pointer - gotfree_input_line)
4026 + adjust);
4027 free (gotfree_input_line);
4028 }
4029 }
4030 else
4031 expression (exp);
4032}
4033#endif
4034
d182319b 4035static void signed_cons (int size)
6482c264 4036{
d182319b
JB		 4037 if (flag_code == CODE_64BIT)
4038 cons_sign = 1;
4039 cons (size);
4040 cons_sign = -1;
6482c264
NC		 4041}
4042
d182319b 4043#ifdef TE_PE
6482c264
NC		 4044static void
4045pe_directive_secrel (dummy)
4046 int dummy ATTRIBUTE_UNUSED;
4047{
4048 expressionS exp;
4049
4050 do
4051 {
4052 expression (&exp);
4053 if (exp.X_op == O_symbol)
4054 exp.X_op = O_secrel;
4055
4056 emit_expr (&exp, 4);
4057 }
4058 while (*input_line_pointer++ == ',');
4059
4060 input_line_pointer--;
4061 demand_empty_rest_of_line ();
4062}
6482c264
NC		 4063#endif
4064
252b5132
RH		 4065static int i386_immediate PARAMS ((char *));
4066
4067static int
4068i386_immediate (imm_start)
4069 char *imm_start;
4070{
4071 char *save_input_line_pointer;
f3c180ae 4072 char *gotfree_input_line;
252b5132 4073 segT exp_seg = 0;
47926f60 4074 expressionS *exp;
3956db08 4075 unsigned int types = ~0U;
252b5132
RH		 4076
4077 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4078 {
d0b47220 4079 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4080 return 0;
4081 }
4082
4083 exp = &im_expressions[i.imm_operands++];
520dc8e8 4084 i.op[this_operand].imms = exp;
252b5132
RH		 4085
4086 if (is_space_char (*imm_start))
4087 ++imm_start;
4088
4089 save_input_line_pointer = input_line_pointer;
4090 input_line_pointer = imm_start;
4091
3956db08 4092 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4093 if (gotfree_input_line)
4094 input_line_pointer = gotfree_input_line;
252b5132
RH		 4095
4096 exp_seg = expression (exp);
4097
83183c0c 4098 SKIP_WHITESPACE ();
252b5132 4099 if (*input_line_pointer)
f3c180ae 4100 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4101
4102 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4103 if (gotfree_input_line)
4104 free (gotfree_input_line);
252b5132 4105
2daf4fd8 4106 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4107 {
47926f60 4108 /* Missing or bad expr becomes absolute 0. */
d0b47220 4109 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4110 imm_start);
252b5132
RH		 4111 exp->X_op = O_constant;
4112 exp->X_add_number = 0;
4113 exp->X_add_symbol = (symbolS *) 0;
4114 exp->X_op_symbol = (symbolS *) 0;
252b5132 4115 }
3e73aa7c 4116 else if (exp->X_op == O_constant)
252b5132 4117 {
47926f60 4118 /* Size it properly later. */
3e73aa7c
JH		 4119 i.types[this_operand] |= Imm64;
4120 /* If BFD64, sign extend val. */
4121 if (!use_rela_relocations)
4122 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4123 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4124 }
4c63da97 4125#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4126 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4127 && exp_seg != absolute_section
47926f60 4128 && exp_seg != text_section
24eab124
AM		 4129 && exp_seg != data_section
4130 && exp_seg != bss_section
4131 && exp_seg != undefined_section
f86103b7 4132 && !bfd_is_com_section (exp_seg))
252b5132 4133 {
d0b47220 4134 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4135 return 0;
4136 }
4137#endif
bb8f5920
L		 4138 else if (!intel_syntax && exp->X_op == O_register)
4139 {
4140 as_bad (_("illegal immediate register operand %s"), imm_start);
4141 return 0;
4142 }
252b5132
RH		 4143 else
4144 {
4145 /* This is an address. The size of the address will be
24eab124 4146 determined later, depending on destination register,
3e73aa7c
JH		 4147 suffix, or the default for the section. */
4148 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4149 i.types[this_operand] &= types;
252b5132
RH		 4150 }
4151
4152 return 1;
4153}
4154
551c1ca1 4155static char *i386_scale PARAMS ((char *));
252b5132 4156
551c1ca1 4157static char *
252b5132
RH		 4158i386_scale (scale)
4159 char *scale;
4160{
551c1ca1
AM		 4161 offsetT val;
4162 char *save = input_line_pointer;
252b5132 4163
551c1ca1
AM		 4164 input_line_pointer = scale;
4165 val = get_absolute_expression ();
4166
4167 switch (val)
252b5132 4168 {
551c1ca1 4169 case 1:
252b5132
RH		 4170 i.log2_scale_factor = 0;
4171 break;
551c1ca1 4172 case 2:
252b5132
RH		 4173 i.log2_scale_factor = 1;
4174 break;
551c1ca1 4175 case 4:
252b5132
RH		 4176 i.log2_scale_factor = 2;
4177 break;
551c1ca1 4178 case 8:
252b5132
RH		 4179 i.log2_scale_factor = 3;
4180 break;
4181 default:
a724f0f4
JB		 4182 {
4183 char sep = *input_line_pointer;
4184
4185 *input_line_pointer = '\0';
4186 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4187 scale);
4188 *input_line_pointer = sep;
4189 input_line_pointer = save;
4190 return NULL;
4191 }
252b5132 4192 }
29b0f896 4193 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4194 {
4195 as_warn (_("scale factor of %d without an index register"),
24eab124 4196 1 << i.log2_scale_factor);
252b5132
RH		 4197#if SCALE1_WHEN_NO_INDEX
4198 i.log2_scale_factor = 0;
4199#endif
4200 }
551c1ca1
AM		 4201 scale = input_line_pointer;
4202 input_line_pointer = save;
4203 return scale;
252b5132
RH		 4204}
4205
4206static int i386_displacement PARAMS ((char *, char *));
4207
4208static int
4209i386_displacement (disp_start, disp_end)
4210 char *disp_start;
4211 char *disp_end;
4212{
29b0f896 4213 expressionS *exp;
252b5132
RH		 4214 segT exp_seg = 0;
4215 char *save_input_line_pointer;
f3c180ae 4216 char *gotfree_input_line;
e05278af 4217 int bigdisp, override;
3956db08 4218 unsigned int types = Disp;
252b5132 4219
e05278af
JB		 4220 if ((i.types[this_operand] & JumpAbsolute)
4221 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4222 {
4223 bigdisp = Disp32;
4224 override = (i.prefix[ADDR_PREFIX] != 0);
4225 }
4226 else
4227 {
4228 /* For PC-relative branches, the width of the displacement
4229 is dependent upon data size, not address size. */
4230 bigdisp = 0;
4231 override = (i.prefix[DATA_PREFIX] != 0);
4232 }
3e73aa7c 4233 if (flag_code == CODE_64BIT)
7ecd2f8b 4234 {
e05278af 4235 if (!bigdisp)
64e74474
AM		 4236 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4237 ? Disp16
4238 : Disp32S | Disp32);
e05278af 4239 else if (!override)
3956db08 4240 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4241 }
e05278af
JB		 4242 else
4243 {
4244 if (!bigdisp)
4245 {
4246 if (!override)
4247 override = (i.suffix == (flag_code != CODE_16BIT
4248 ? WORD_MNEM_SUFFIX
4249 : LONG_MNEM_SUFFIX));
4250 bigdisp = Disp32;
4251 }
4252 if ((flag_code == CODE_16BIT) ^ override)
4253 bigdisp = Disp16;
4254 }
252b5132
RH		 4255 i.types[this_operand] |= bigdisp;
4256
4257 exp = &disp_expressions[i.disp_operands];
520dc8e8 4258 i.op[this_operand].disps = exp;
252b5132
RH		 4259 i.disp_operands++;
4260 save_input_line_pointer = input_line_pointer;
4261 input_line_pointer = disp_start;
4262 END_STRING_AND_SAVE (disp_end);
4263
4264#ifndef GCC_ASM_O_HACK
4265#define GCC_ASM_O_HACK 0
4266#endif
4267#if GCC_ASM_O_HACK
4268 END_STRING_AND_SAVE (disp_end + 1);
4269 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4270 && displacement_string_end[-1] == '+')
252b5132
RH		 4271 {
4272 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4273 constraint within gcc asm statements.
4274 For instance:
4275
4276 #define _set_tssldt_desc(n,addr,limit,type) \
4277 __asm__ __volatile__ ( \
4278 "movw %w2,%0\n\t" \
4279 "movw %w1,2+%0\n\t" \
4280 "rorl $16,%1\n\t" \
4281 "movb %b1,4+%0\n\t" \
4282 "movb %4,5+%0\n\t" \
4283 "movb $0,6+%0\n\t" \
4284 "movb %h1,7+%0\n\t" \
4285 "rorl $16,%1" \
4286 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4287
4288 This works great except that the output assembler ends
4289 up looking a bit weird if it turns out that there is
4290 no offset. You end up producing code that looks like:
4291
4292 #APP
4293 movw $235,(%eax)
4294 movw %dx,2+(%eax)
4295 rorl $16,%edx
4296 movb %dl,4+(%eax)
4297 movb $137,5+(%eax)
4298 movb $0,6+(%eax)
4299 movb %dh,7+(%eax)
4300 rorl $16,%edx
4301 #NO_APP
4302
47926f60 4303 So here we provide the missing zero. */
24eab124
AM		 4304
4305 *displacement_string_end = '0';
252b5132
RH		 4306 }
4307#endif
3956db08 4308 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4309 if (gotfree_input_line)
4310 input_line_pointer = gotfree_input_line;
252b5132 4311
24eab124 4312 exp_seg = expression (exp);
252b5132 4313
636c26b0
AM		 4314 SKIP_WHITESPACE ();
4315 if (*input_line_pointer)
4316 as_bad (_("junk `%s' after expression"), input_line_pointer);
4317#if GCC_ASM_O_HACK
4318 RESTORE_END_STRING (disp_end + 1);
4319#endif
4320 RESTORE_END_STRING (disp_end);
4321 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4322 if (gotfree_input_line)
4323 free (gotfree_input_line);
636c26b0 4324
24eab124
AM		 4325 /* We do this to make sure that the section symbol is in
4326 the symbol table. We will ultimately change the relocation
47926f60 4327 to be relative to the beginning of the section. */
1ae12ab7 4328 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4329 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4330 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4331 {
636c26b0
AM		 4332 if (exp->X_op != O_symbol)
4333 {
4334 as_bad (_("bad expression used with @%s"),
4335 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4336 ? "GOTPCREL"
4337 : "GOTOFF"));
4338 return 0;
4339 }
4340
e5cb08ac 4341 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4342 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4343 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4344 exp->X_op = O_subtract;
4345 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4346 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4347 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4348 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4349 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4350 else
29b0f896 4351 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4352 }
252b5132 4353
2daf4fd8
AM		 4354 if (exp->X_op == O_absent || exp->X_op == O_big)
4355 {
47926f60 4356 /* Missing or bad expr becomes absolute 0. */
d0b47220 4357 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4358 disp_start);
4359 exp->X_op = O_constant;
4360 exp->X_add_number = 0;
4361 exp->X_add_symbol = (symbolS *) 0;
4362 exp->X_op_symbol = (symbolS *) 0;
4363 }
4364
4c63da97 4365#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4366 if (exp->X_op != O_constant
45288df1 4367 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4368 && exp_seg != absolute_section
45288df1
AM		 4369 && exp_seg != text_section
4370 && exp_seg != data_section
4371 && exp_seg != bss_section
31312f95 4372 && exp_seg != undefined_section
f86103b7 4373 && !bfd_is_com_section (exp_seg))
24eab124 4374 {
d0b47220 4375 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4376 return 0;
4377 }
252b5132 4378#endif
3956db08
JB		 4379
4380 if (!(i.types[this_operand] & ~Disp))
4381 i.types[this_operand] &= types;
4382
252b5132
RH		 4383 return 1;
4384}
4385
e5cb08ac 4386static int i386_index_check PARAMS ((const char *));
252b5132 4387
eecb386c 4388/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4389 Return 1 on success, 0 on a failure. */
4390
252b5132 4391static int
eecb386c
AM		 4392i386_index_check (operand_string)
4393 const char *operand_string;
252b5132 4394{
3e73aa7c 4395 int ok;
24eab124 4396#if INFER_ADDR_PREFIX
eecb386c
AM		 4397 int fudged = 0;
4398
24eab124
AM		 4399 tryprefix:
4400#endif
3e73aa7c 4401 ok = 1;
30123838
JB		 4402 if ((current_templates->start->cpu_flags & CpuSVME)
4403 && current_templates->end[-1].operand_types[0] == AnyMem)
4404 {
4405 /* Memory operands of SVME insns are special in that they only allow
4406 rAX as their memory address and ignore any segment override. */
4407 unsigned RegXX;
4408
4409 /* SKINIT is even more restrictive: it always requires EAX. */
4410 if (strcmp (current_templates->start->name, "skinit") == 0)
4411 RegXX = Reg32;
4412 else if (flag_code == CODE_64BIT)
4413 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4414 else
64e74474
AM		 4415 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4416 ? Reg16
4417 : Reg32);
30123838
JB		 4418 if (!i.base_reg
4419 || !(i.base_reg->reg_type & Acc)
4420 || !(i.base_reg->reg_type & RegXX)
4421 || i.index_reg
4422 || (i.types[0] & Disp))
4423 ok = 0;
4424 }
4425 else if (flag_code == CODE_64BIT)
64e74474
AM		 4426 {
4427 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4428
4429 if ((i.base_reg
4430 && ((i.base_reg->reg_type & RegXX) == 0)
4431 && (i.base_reg->reg_type != BaseIndex
4432 || i.index_reg))
4433 || (i.index_reg
4434 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4435 != (RegXX | BaseIndex))))
4436 ok = 0;
3e73aa7c
JH		 4437 }
4438 else
4439 {
4440 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4441 {
4442 /* 16bit checks. */
4443 if ((i.base_reg
29b0f896
AM		 4444 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4445 != (Reg16 | BaseIndex)))
3e73aa7c 4446 || (i.index_reg
29b0f896
AM		 4447 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4448 != (Reg16 | BaseIndex))
4449 || !(i.base_reg
4450 && i.base_reg->reg_num < 6
4451 && i.index_reg->reg_num >= 6
4452 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4453 ok = 0;
4454 }
4455 else
e5cb08ac 4456 {
3e73aa7c
JH		 4457 /* 32bit checks. */
4458 if ((i.base_reg
4459 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4460 || (i.index_reg
29b0f896
AM		 4461 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4462 != (Reg32 | BaseIndex))))
e5cb08ac 4463 ok = 0;
3e73aa7c
JH		 4464 }
4465 }
4466 if (!ok)
24eab124
AM		 4467 {
4468#if INFER_ADDR_PREFIX
20f0a1fc 4469 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4470 {
4471 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4472 i.prefixes += 1;
b23bac36
AM		 4473 /* Change the size of any displacement too. At most one of
4474 Disp16 or Disp32 is set.
4475 FIXME. There doesn't seem to be any real need for separate
4476 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4477 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4478 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4479 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4480 fudged = 1;
24eab124
AM		 4481 goto tryprefix;
4482 }
eecb386c
AM		 4483 if (fudged)
4484 as_bad (_("`%s' is not a valid base/index expression"),
4485 operand_string);
4486 else
c388dee8 4487#endif
eecb386c
AM		 4488 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4489 operand_string,
3e73aa7c 4490 flag_code_names[flag_code]);
24eab124 4491 }
20f0a1fc 4492 return ok;
24eab124 4493}
252b5132 4494
252b5132 4495/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4496 on error. */
252b5132 4497
252b5132
RH		 4498static int
4499i386_operand (operand_string)
4500 char *operand_string;
4501{
af6bdddf
AM		 4502 const reg_entry *r;
4503 char *end_op;
24eab124 4504 char *op_string = operand_string;
252b5132 4505
24eab124 4506 if (is_space_char (*op_string))
252b5132
RH		 4507 ++op_string;
4508
24eab124 4509 /* We check for an absolute prefix (differentiating,
47926f60 4510 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4511 if (*op_string == ABSOLUTE_PREFIX)
4512 {
4513 ++op_string;
4514 if (is_space_char (*op_string))
4515 ++op_string;
4516 i.types[this_operand] |= JumpAbsolute;
4517 }
252b5132 4518
47926f60 4519 /* Check if operand is a register. */
4d1bb795 4520 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4521 {
24eab124
AM		 4522 /* Check for a segment override by searching for ':' after a
4523 segment register. */
4524 op_string = end_op;
4525 if (is_space_char (*op_string))
4526 ++op_string;
4527 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4528 {
4529 switch (r->reg_num)
4530 {
4531 case 0:
4532 i.seg[i.mem_operands] = &es;
4533 break;
4534 case 1:
4535 i.seg[i.mem_operands] = &cs;
4536 break;
4537 case 2:
4538 i.seg[i.mem_operands] = &ss;
4539 break;
4540 case 3:
4541 i.seg[i.mem_operands] = &ds;
4542 break;
4543 case 4:
4544 i.seg[i.mem_operands] = &fs;
4545 break;
4546 case 5:
4547 i.seg[i.mem_operands] = &gs;
4548 break;
4549 }
252b5132 4550
24eab124 4551 /* Skip the ':' and whitespace. */
252b5132
RH		 4552 ++op_string;
4553 if (is_space_char (*op_string))
24eab124 4554 ++op_string;
252b5132 4555
24eab124
AM		 4556 if (!is_digit_char (*op_string)
4557 && !is_identifier_char (*op_string)
4558 && *op_string != '('
4559 && *op_string != ABSOLUTE_PREFIX)
4560 {
4561 as_bad (_("bad memory operand `%s'"), op_string);
4562 return 0;
4563 }
47926f60 4564 /* Handle case of %es:*foo. */
24eab124
AM		 4565 if (*op_string == ABSOLUTE_PREFIX)
4566 {
4567 ++op_string;
4568 if (is_space_char (*op_string))
4569 ++op_string;
4570 i.types[this_operand] |= JumpAbsolute;
4571 }
4572 goto do_memory_reference;
4573 }
4574 if (*op_string)
4575 {
d0b47220 4576 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4577 return 0;
4578 }
4579 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4580 i.op[this_operand].regs = r;
24eab124
AM		 4581 i.reg_operands++;
4582 }
af6bdddf
AM		 4583 else if (*op_string == REGISTER_PREFIX)
4584 {
4585 as_bad (_("bad register name `%s'"), op_string);
4586 return 0;
4587 }
24eab124 4588 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4589 {
24eab124
AM		 4590 ++op_string;
4591 if (i.types[this_operand] & JumpAbsolute)
4592 {
d0b47220 4593 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4594 return 0;
4595 }
4596 if (!i386_immediate (op_string))
4597 return 0;
4598 }
4599 else if (is_digit_char (*op_string)
4600 || is_identifier_char (*op_string)
e5cb08ac 4601 || *op_string == '(')
24eab124 4602 {
47926f60 4603 /* This is a memory reference of some sort. */
af6bdddf 4604 char *base_string;
252b5132 4605
47926f60 4606 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4607 char *displacement_string_start;
4608 char *displacement_string_end;
252b5132 4609
24eab124 4610 do_memory_reference:
24eab124
AM		 4611 if ((i.mem_operands == 1
4612 && (current_templates->start->opcode_modifier & IsString) == 0)
4613 || i.mem_operands == 2)
4614 {
4615 as_bad (_("too many memory references for `%s'"),
4616 current_templates->start->name);
4617 return 0;
4618 }
252b5132 4619
24eab124
AM		 4620 /* Check for base index form. We detect the base index form by
4621 looking for an ')' at the end of the operand, searching
4622 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4623 after the '('. */
af6bdddf 4624 base_string = op_string + strlen (op_string);
c3332e24 4625
af6bdddf
AM		 4626 --base_string;
4627 if (is_space_char (*base_string))
4628 --base_string;
252b5132 4629
47926f60 4630 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4631 displacement_string_start = op_string;
4632 displacement_string_end = base_string + 1;
252b5132 4633
24eab124
AM		 4634 if (*base_string == ')')
4635 {
af6bdddf 4636 char *temp_string;
24eab124
AM		 4637 unsigned int parens_balanced = 1;
4638 /* We've already checked that the number of left & right ()'s are
47926f60 4639 equal, so this loop will not be infinite. */
24eab124
AM		 4640 do
4641 {
4642 base_string--;
4643 if (*base_string == ')')
4644 parens_balanced++;
4645 if (*base_string == '(')
4646 parens_balanced--;
4647 }
4648 while (parens_balanced);
c3332e24 4649
af6bdddf 4650 temp_string = base_string;
c3332e24 4651
24eab124 4652 /* Skip past '(' and whitespace. */
252b5132
RH		 4653 ++base_string;
4654 if (is_space_char (*base_string))
24eab124 4655 ++base_string;
252b5132 4656
af6bdddf 4657 if (*base_string == ','
4d1bb795 4658 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4659 {
af6bdddf 4660 displacement_string_end = temp_string;
252b5132 4661
af6bdddf 4662 i.types[this_operand] |= BaseIndex;
252b5132 4663
af6bdddf 4664 if (i.base_reg)
24eab124 4665 {
24eab124
AM		 4666 base_string = end_op;
4667 if (is_space_char (*base_string))
4668 ++base_string;
af6bdddf
AM		 4669 }
4670
4671 /* There may be an index reg or scale factor here. */
4672 if (*base_string == ',')
4673 {
4674 ++base_string;
4675 if (is_space_char (*base_string))
4676 ++base_string;
4677
4d1bb795 4678 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4679 {
af6bdddf 4680 base_string = end_op;
24eab124
AM		 4681 if (is_space_char (*base_string))
4682 ++base_string;
af6bdddf
AM		 4683 if (*base_string == ',')
4684 {
4685 ++base_string;
4686 if (is_space_char (*base_string))
4687 ++base_string;
4688 }
e5cb08ac 4689 else if (*base_string != ')')
af6bdddf
AM		 4690 {
4691 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4692 operand_string);
4693 return 0;
4694 }
24eab124 4695 }
af6bdddf 4696 else if (*base_string == REGISTER_PREFIX)
24eab124 4697 {
af6bdddf 4698 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4699 return 0;
4700 }
252b5132 4701
47926f60 4702 /* Check for scale factor. */
551c1ca1 4703 if (*base_string != ')')
af6bdddf 4704 {
551c1ca1
AM		 4705 char *end_scale = i386_scale (base_string);
4706
4707 if (!end_scale)
af6bdddf 4708 return 0;
24eab124 4709
551c1ca1 4710 base_string = end_scale;
af6bdddf
AM		 4711 if (is_space_char (*base_string))
4712 ++base_string;
4713 if (*base_string != ')')
4714 {
4715 as_bad (_("expecting `)' after scale factor in `%s'"),
4716 operand_string);
4717 return 0;
4718 }
4719 }
4720 else if (!i.index_reg)
24eab124 4721 {
af6bdddf
AM		 4722 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4723 *base_string);
24eab124
AM		 4724 return 0;
4725 }
4726 }
af6bdddf 4727 else if (*base_string != ')')
24eab124 4728 {
af6bdddf
AM		 4729 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4730 operand_string);
24eab124
AM		 4731 return 0;
4732 }
c3332e24 4733 }
af6bdddf 4734 else if (*base_string == REGISTER_PREFIX)
c3332e24 4735 {
af6bdddf 4736 as_bad (_("bad register name `%s'"), base_string);
24eab124 4737 return 0;
c3332e24 4738 }
24eab124
AM		 4739 }
4740
4741 /* If there's an expression beginning the operand, parse it,
4742 assuming displacement_string_start and
4743 displacement_string_end are meaningful. */
4744 if (displacement_string_start != displacement_string_end)
4745 {
4746 if (!i386_displacement (displacement_string_start,
4747 displacement_string_end))
4748 return 0;
4749 }
4750
4751 /* Special case for (%dx) while doing input/output op. */
4752 if (i.base_reg
4753 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4754 && i.index_reg == 0
4755 && i.log2_scale_factor == 0
4756 && i.seg[i.mem_operands] == 0
4757 && (i.types[this_operand] & Disp) == 0)
4758 {
4759 i.types[this_operand] = InOutPortReg;
4760 return 1;
4761 }
4762
eecb386c
AM		 4763 if (i386_index_check (operand_string) == 0)
4764 return 0;
24eab124
AM		 4765 i.mem_operands++;
4766 }
4767 else
ce8a8b2f
AM		 4768 {
4769 /* It's not a memory operand; argh! */
24eab124
AM		 4770 as_bad (_("invalid char %s beginning operand %d `%s'"),
4771 output_invalid (*op_string),
4772 this_operand + 1,
4773 op_string);
4774 return 0;
4775 }
47926f60 4776 return 1; /* Normal return. */
252b5132
RH		 4777}
4778\f
ee7fcc42
AM		 4779/* md_estimate_size_before_relax()
4780
4781 Called just before relax() for rs_machine_dependent frags. The x86
4782 assembler uses these frags to handle variable size jump
4783 instructions.
4784
4785 Any symbol that is now undefined will not become defined.
4786 Return the correct fr_subtype in the frag.
4787 Return the initial "guess for variable size of frag" to caller.
4788 The guess is actually the growth beyond the fixed part. Whatever
4789 we do to grow the fixed or variable part contributes to our
4790 returned value. */
4791
252b5132
RH		 4792int
4793md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4794 fragS *fragP;
4795 segT segment;
252b5132 4796{
252b5132 4797 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4798 check for un-relaxable symbols. On an ELF system, we can't relax
4799 an externally visible symbol, because it may be overridden by a
4800 shared library. */
4801 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4802#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4803 || (IS_ELF
31312f95
AM		 4804 && (S_IS_EXTERNAL (fragP->fr_symbol)
4805 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4806#endif
4807 )
252b5132 4808 {
b98ef147
AM		 4809 /* Symbol is undefined in this segment, or we need to keep a
4810 reloc so that weak symbols can be overridden. */
4811 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4812 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4813 unsigned char *opcode;
4814 int old_fr_fix;
f6af82bd 4815
ee7fcc42
AM		 4816 if (fragP->fr_var != NO_RELOC)
4817 reloc_type = fragP->fr_var;
b98ef147 4818 else if (size == 2)
f6af82bd
AM		 4819 reloc_type = BFD_RELOC_16_PCREL;
4820 else
4821 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4822
ee7fcc42
AM		 4823 old_fr_fix = fragP->fr_fix;
4824 opcode = (unsigned char *) fragP->fr_opcode;
4825
fddf5b5b 4826 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4827 {
fddf5b5b
AM		 4828 case UNCOND_JUMP:
4829 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4830 opcode[0] = 0xe9;
252b5132 4831 fragP->fr_fix += size;
062cd5e7
AS		 4832 fix_new (fragP, old_fr_fix, size,
4833 fragP->fr_symbol,
4834 fragP->fr_offset, 1,
4835 reloc_type);
252b5132
RH		 4836 break;
4837
fddf5b5b 4838 case COND_JUMP86:
412167cb
AM		 4839 if (size == 2
4840 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4841 {
4842 /* Negate the condition, and branch past an
4843 unconditional jump. */
4844 opcode[0] ^= 1;
4845 opcode[1] = 3;
4846 /* Insert an unconditional jump. */
4847 opcode[2] = 0xe9;
4848 /* We added two extra opcode bytes, and have a two byte
4849 offset. */
4850 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4851 fix_new (fragP, old_fr_fix + 2, 2,
4852 fragP->fr_symbol,
4853 fragP->fr_offset, 1,
4854 reloc_type);
fddf5b5b
AM		 4855 break;
4856 }
4857 /* Fall through. */
4858
4859 case COND_JUMP:
412167cb
AM		 4860 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4861 {
3e02c1cc
AM		 4862 fixS *fixP;
4863
412167cb 4864 fragP->fr_fix += 1;
3e02c1cc
AM		 4865 fixP = fix_new (fragP, old_fr_fix, 1,
4866 fragP->fr_symbol,
4867 fragP->fr_offset, 1,
4868 BFD_RELOC_8_PCREL);
4869 fixP->fx_signed = 1;
412167cb
AM		 4870 break;
4871 }
93c2a809 4872
24eab124 4873 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4874 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4875 opcode[1] = opcode[0] + 0x10;
f6af82bd 4876 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4877 /* We've added an opcode byte. */
4878 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4879 fix_new (fragP, old_fr_fix + 1, size,
4880 fragP->fr_symbol,
4881 fragP->fr_offset, 1,
4882 reloc_type);
252b5132 4883 break;
fddf5b5b
AM		 4884
4885 default:
4886 BAD_CASE (fragP->fr_subtype);
4887 break;
252b5132
RH		 4888 }
4889 frag_wane (fragP);
ee7fcc42 4890 return fragP->fr_fix - old_fr_fix;
252b5132 4891 }
93c2a809 4892
93c2a809
AM		 4893 /* Guess size depending on current relax state. Initially the relax
4894 state will correspond to a short jump and we return 1, because
4895 the variable part of the frag (the branch offset) is one byte
4896 long. However, we can relax a section more than once and in that
4897 case we must either set fr_subtype back to the unrelaxed state,
4898 or return the value for the appropriate branch. */
4899 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4900}
4901
47926f60
KH		 4902/* Called after relax() is finished.
4903
4904 In: Address of frag.
4905 fr_type == rs_machine_dependent.
4906 fr_subtype is what the address relaxed to.
4907
4908 Out: Any fixSs and constants are set up.
4909 Caller will turn frag into a ".space 0". */
4910
252b5132
RH		 4911void
4912md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4913 bfd *abfd ATTRIBUTE_UNUSED;
4914 segT sec ATTRIBUTE_UNUSED;
29b0f896 4915 fragS *fragP;
252b5132 4916{
29b0f896 4917 unsigned char *opcode;
252b5132 4918 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4919 offsetT target_address;
4920 offsetT opcode_address;
252b5132 4921 unsigned int extension = 0;
847f7ad4 4922 offsetT displacement_from_opcode_start;
252b5132
RH		 4923
4924 opcode = (unsigned char *) fragP->fr_opcode;
4925
47926f60 4926 /* Address we want to reach in file space. */
252b5132 4927 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4928
47926f60 4929 /* Address opcode resides at in file space. */
252b5132
RH		 4930 opcode_address = fragP->fr_address + fragP->fr_fix;
4931
47926f60 4932 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4933 displacement_from_opcode_start = target_address - opcode_address;
4934
fddf5b5b 4935 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4936 {
47926f60
KH		 4937 /* Don't have to change opcode. */
4938 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4939 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4940 }
4941 else
4942 {
4943 if (no_cond_jump_promotion
4944 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4945 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4946
fddf5b5b
AM		 4947 switch (fragP->fr_subtype)
4948 {
4949 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4950 extension = 4; /* 1 opcode + 4 displacement */
4951 opcode[0] = 0xe9;
4952 where_to_put_displacement = &opcode[1];
4953 break;
252b5132 4954
fddf5b5b
AM		 4955 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4956 extension = 2; /* 1 opcode + 2 displacement */
4957 opcode[0] = 0xe9;
4958 where_to_put_displacement = &opcode[1];
4959 break;
252b5132 4960
fddf5b5b
AM		 4961 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4962 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4963 extension = 5; /* 2 opcode + 4 displacement */
4964 opcode[1] = opcode[0] + 0x10;
4965 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4966 where_to_put_displacement = &opcode[2];
4967 break;
252b5132 4968
fddf5b5b
AM		 4969 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4970 extension = 3; /* 2 opcode + 2 displacement */
4971 opcode[1] = opcode[0] + 0x10;
4972 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4973 where_to_put_displacement = &opcode[2];
4974 break;
252b5132 4975
fddf5b5b
AM		 4976 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4977 extension = 4;
4978 opcode[0] ^= 1;
4979 opcode[1] = 3;
4980 opcode[2] = 0xe9;
4981 where_to_put_displacement = &opcode[3];
4982 break;
4983
4984 default:
4985 BAD_CASE (fragP->fr_subtype);
4986 break;
4987 }
252b5132 4988 }
fddf5b5b 4989
7b81dfbb
AJ		 4990 /* If size if less then four we are sure that the operand fits,
4991 but if it's 4, then it could be that the displacement is larger
4992 then -/+ 2GB. */
4993 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
4994 && object_64bit
4995 && ((addressT) (displacement_from_opcode_start - extension
4996 + ((addressT) 1 << 31))
4997 > (((addressT) 2 << 31) - 1)))
4998 {
4999 as_bad_where (fragP->fr_file, fragP->fr_line,
5000 _("jump target out of range"));
5001 /* Make us emit 0. */
5002 displacement_from_opcode_start = extension;
5003 }
47926f60 5004 /* Now put displacement after opcode. */
252b5132
RH		 5005 md_number_to_chars ((char *) where_to_put_displacement,
5006 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5007 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5008 fragP->fr_fix += extension;
5009}
5010\f
47926f60
KH		 5011/* Size of byte displacement jmp. */
5012int md_short_jump_size = 2;
5013
5014/* Size of dword displacement jmp. */
5015int md_long_jump_size = 5;
252b5132 5016
252b5132
RH		 5017void
5018md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5019 char *ptr;
5020 addressT from_addr, to_addr;
ab9da554
ILT		 5021 fragS *frag ATTRIBUTE_UNUSED;
5022 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5023{
847f7ad4 5024 offsetT offset;
252b5132
RH		 5025
5026 offset = to_addr - (from_addr + 2);
47926f60
KH		 5027 /* Opcode for byte-disp jump. */
5028 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5029 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5030}
5031
5032void
5033md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5034 char *ptr;
5035 addressT from_addr, to_addr;
a38cf1db
AM		 5036 fragS *frag ATTRIBUTE_UNUSED;
5037 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5038{
847f7ad4 5039 offsetT offset;
252b5132 5040
a38cf1db
AM		 5041 offset = to_addr - (from_addr + 5);
5042 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5043 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5044}
5045\f
5046/* Apply a fixup (fixS) to segment data, once it has been determined
5047 by our caller that we have all the info we need to fix it up.
5048
5049 On the 386, immediates, displacements, and data pointers are all in
5050 the same (little-endian) format, so we don't need to care about which
5051 we are handling. */
5052
94f592af 5053void
55cf6793 5054md_apply_fix (fixP, valP, seg)
47926f60
KH		 5055 /* The fix we're to put in. */
5056 fixS *fixP;
47926f60 5057 /* Pointer to the value of the bits. */
c6682705 5058 valueT *valP;
47926f60
KH		 5059 /* Segment fix is from. */
5060 segT seg ATTRIBUTE_UNUSED;
252b5132 5061{
94f592af 5062 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5063 valueT value = *valP;
252b5132 5064
f86103b7 5065#if !defined (TE_Mach)
93382f6d
AM		 5066 if (fixP->fx_pcrel)
5067 {
5068 switch (fixP->fx_r_type)
5069 {
5865bb77
ILT		 5070 default:
5071 break;
5072
d6ab8113
JB		 5073 case BFD_RELOC_64:
5074 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5075 break;
93382f6d 5076 case BFD_RELOC_32:
ae8887b5 5077 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5078 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5079 break;
5080 case BFD_RELOC_16:
5081 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5082 break;
5083 case BFD_RELOC_8:
5084 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5085 break;
5086 }
5087 }
252b5132 5088
a161fe53 5089 if (fixP->fx_addsy != NULL
31312f95 5090 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5091 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5092 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5093 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5094 && !use_rela_relocations)
252b5132 5095 {
31312f95
AM		 5096 /* This is a hack. There should be a better way to handle this.
5097 This covers for the fact that bfd_install_relocation will
5098 subtract the current location (for partial_inplace, PC relative
5099 relocations); see more below. */
252b5132 5100#ifndef OBJ_AOUT
718ddfc0 5101 if (IS_ELF
252b5132
RH		 5102#ifdef TE_PE
5103 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5104#endif
5105 )
5106 value += fixP->fx_where + fixP->fx_frag->fr_address;
5107#endif
5108#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5109 if (IS_ELF)
252b5132 5110 {
6539b54b 5111 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5112
6539b54b 5113 if ((sym_seg == seg
2f66722d 5114 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5115 && sym_seg != absolute_section))
ae6063d4 5116 && !generic_force_reloc (fixP))
2f66722d
AM		 5117 {
5118 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5119 bfd_install_relocation subtracts them out again. I think
5120 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5121 it. FIXME. */
5122 value += fixP->fx_where + fixP->fx_frag->fr_address;
5123 }
252b5132
RH		 5124 }
5125#endif
5126#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5127 /* For some reason, the PE format does not store a
5128 section address offset for a PC relative symbol. */
5129 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5130 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5131 value += md_pcrel_from (fixP);
5132#endif
5133 }
5134
5135 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5136 and we must not disappoint it. */
252b5132 5137#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5138 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5139 switch (fixP->fx_r_type)
5140 {
5141 case BFD_RELOC_386_PLT32:
3e73aa7c 5142 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5143 /* Make the jump instruction point to the address of the operand. At
5144 runtime we merely add the offset to the actual PLT entry. */
5145 value = -4;
5146 break;
31312f95 5147
13ae64f3
JJ		 5148 case BFD_RELOC_386_TLS_GD:
5149 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5150 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5151 case BFD_RELOC_386_TLS_IE:
5152 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5153 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5154 case BFD_RELOC_X86_64_TLSGD:
5155 case BFD_RELOC_X86_64_TLSLD:
5156 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5157 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5158 value = 0; /* Fully resolved at runtime. No addend. */
5159 /* Fallthrough */
5160 case BFD_RELOC_386_TLS_LE:
5161 case BFD_RELOC_386_TLS_LDO_32:
5162 case BFD_RELOC_386_TLS_LE_32:
5163 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5164 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5165 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5166 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5167 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5168 break;
5169
67a4f2b7
AO		 5170 case BFD_RELOC_386_TLS_DESC_CALL:
5171 case BFD_RELOC_X86_64_TLSDESC_CALL:
5172 value = 0; /* Fully resolved at runtime. No addend. */
5173 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5174 fixP->fx_done = 0;
5175 return;
5176
00f7efb6
JJ		 5177 case BFD_RELOC_386_GOT32:
5178 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5179 value = 0; /* Fully resolved at runtime. No addend. */
5180 break;
47926f60
KH		 5181
5182 case BFD_RELOC_VTABLE_INHERIT:
5183 case BFD_RELOC_VTABLE_ENTRY:
5184 fixP->fx_done = 0;
94f592af 5185 return;
47926f60
KH		 5186
5187 default:
5188 break;
5189 }
5190#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5191 *valP = value;
f86103b7 5192#endif /* !defined (TE_Mach) */
3e73aa7c 5193
3e73aa7c 5194 /* Are we finished with this relocation now? */
c6682705 5195 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5196 fixP->fx_done = 1;
5197 else if (use_rela_relocations)
5198 {
5199 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5200 /* Remember value for tc_gen_reloc. */
5201 fixP->fx_addnumber = value;
3e73aa7c
JH		 5202 value = 0;
5203 }
f86103b7 5204
94f592af 5205 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5206}
252b5132 5207\f
252b5132
RH		 5208#define MAX_LITTLENUMS 6
5209
47926f60
KH		 5210/* Turn the string pointed to by litP into a floating point constant
5211 of type TYPE, and emit the appropriate bytes. The number of
5212 LITTLENUMS emitted is stored in *SIZEP. An error message is
5213 returned, or NULL on OK. */
5214
252b5132
RH		 5215char *
5216md_atof (type, litP, sizeP)
2ab9b79e 5217 int type;
252b5132
RH		 5218 char *litP;
5219 int *sizeP;
5220{
5221 int prec;
5222 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5223 LITTLENUM_TYPE *wordP;
5224 char *t;
5225
5226 switch (type)
5227 {
5228 case 'f':
5229 case 'F':
5230 prec = 2;
5231 break;
5232
5233 case 'd':
5234 case 'D':
5235 prec = 4;
5236 break;
5237
5238 case 'x':
5239 case 'X':
5240 prec = 5;
5241 break;
5242
5243 default:
5244 *sizeP = 0;
5245 return _("Bad call to md_atof ()");
5246 }
5247 t = atof_ieee (input_line_pointer, type, words);
5248 if (t)
5249 input_line_pointer = t;
5250
5251 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5252 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5253 the bigendian 386. */
5254 for (wordP = words + prec - 1; prec--;)
5255 {
5256 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5257 litP += sizeof (LITTLENUM_TYPE);
5258 }
5259 return 0;
5260}
5261\f
2d545b82 5262static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5263
252b5132
RH		 5264static char *
5265output_invalid (c)
5266 int c;
5267{
3882b010 5268 if (ISPRINT (c))
f9f21a03
L		 5269 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5270 "'%c'", c);
252b5132 5271 else
f9f21a03 5272 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5273 "(0x%x)", (unsigned char) c);
252b5132
RH		 5274 return output_invalid_buf;
5275}
5276
af6bdddf 5277/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5278
5279static const reg_entry *
4d1bb795 5280parse_real_register (char *reg_string, char **end_op)
252b5132 5281{
af6bdddf
AM		 5282 char *s = reg_string;
5283 char *p;
252b5132
RH		 5284 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5285 const reg_entry *r;
5286
5287 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5288 if (*s == REGISTER_PREFIX)
5289 ++s;
5290
5291 if (is_space_char (*s))
5292 ++s;
5293
5294 p = reg_name_given;
af6bdddf 5295 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5296 {
5297 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5298 return (const reg_entry *) NULL;
5299 s++;
252b5132
RH		 5300 }
5301
6588847e
DN		 5302 /* For naked regs, make sure that we are not dealing with an identifier.
5303 This prevents confusing an identifier like `eax_var' with register
5304 `eax'. */
5305 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5306 return (const reg_entry *) NULL;
5307
af6bdddf 5308 *end_op = s;
252b5132
RH		 5309
5310 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5311
5f47d35b 5312 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5313 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5314 {
5f47d35b
AM		 5315 if (is_space_char (*s))
5316 ++s;
5317 if (*s == '(')
5318 {
af6bdddf 5319 ++s;
5f47d35b
AM		 5320 if (is_space_char (*s))
5321 ++s;
5322 if (*s >= '0' && *s <= '7')
5323 {
5324 r = &i386_float_regtab[*s - '0'];
af6bdddf 5325 ++s;
5f47d35b
AM		 5326 if (is_space_char (*s))
5327 ++s;
5328 if (*s == ')')
5329 {
5330 *end_op = s + 1;
5331 return r;
5332 }
5f47d35b 5333 }
47926f60 5334 /* We have "%st(" then garbage. */
5f47d35b
AM		 5335 return (const reg_entry *) NULL;
5336 }
5337 }
5338
1ae00879 5339 if (r != NULL
20f0a1fc 5340 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5341 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5342 && flag_code != CODE_64BIT)
20f0a1fc 5343 return (const reg_entry *) NULL;
1ae00879 5344
252b5132
RH		 5345 return r;
5346}
4d1bb795
JB		 5347
5348/* REG_STRING starts *before* REGISTER_PREFIX. */
5349
5350static const reg_entry *
5351parse_register (char *reg_string, char **end_op)
5352{
5353 const reg_entry *r;
5354
5355 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5356 r = parse_real_register (reg_string, end_op);
5357 else
5358 r = NULL;
5359 if (!r)
5360 {
5361 char *save = input_line_pointer;
5362 char c;
5363 symbolS *symbolP;
5364
5365 input_line_pointer = reg_string;
5366 c = get_symbol_end ();
5367 symbolP = symbol_find (reg_string);
5368 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5369 {
5370 const expressionS *e = symbol_get_value_expression (symbolP);
5371
5372 know (e->X_op == O_register);
5373 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5374 r = i386_regtab + e->X_add_number;
5375 *end_op = input_line_pointer;
5376 }
5377 *input_line_pointer = c;
5378 input_line_pointer = save;
5379 }
5380 return r;
5381}
5382
5383int
5384i386_parse_name (char *name, expressionS *e, char *nextcharP)
5385{
5386 const reg_entry *r;
5387 char *end = input_line_pointer;
5388
5389 *end = *nextcharP;
5390 r = parse_register (name, &input_line_pointer);
5391 if (r && end <= input_line_pointer)
5392 {
5393 *nextcharP = *input_line_pointer;
5394 *input_line_pointer = 0;
5395 e->X_op = O_register;
5396 e->X_add_number = r - i386_regtab;
5397 return 1;
5398 }
5399 input_line_pointer = end;
5400 *end = 0;
5401 return 0;
5402}
5403
5404void
5405md_operand (expressionS *e)
5406{
5407 if (*input_line_pointer == REGISTER_PREFIX)
5408 {
5409 char *end;
5410 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5411
5412 if (r)
5413 {
5414 e->X_op = O_register;
5415 e->X_add_number = r - i386_regtab;
5416 input_line_pointer = end;
5417 }
5418 }
5419}
5420
252b5132 5421\f
4cc782b5 5422#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5423const char *md_shortopts = "kVQ:sqn";
252b5132 5424#else
12b55ccc 5425const char *md_shortopts = "qn";
252b5132 5426#endif
6e0b89ee 5427
3e73aa7c 5428#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5429#define OPTION_64 (OPTION_MD_BASE + 1)
5430#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5431
5432struct option md_longopts[] = {
3e73aa7c 5433 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5434#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c 5435 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5436#endif
b3b91714 5437 {"divide", no_argument, NULL, OPTION_DIVIDE},
252b5132
RH		 5438 {NULL, no_argument, NULL, 0}
5439};
5440size_t md_longopts_size = sizeof (md_longopts);
5441
5442int
5443md_parse_option (c, arg)
5444 int c;
ab9da554 5445 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5446{
5447 switch (c)
5448 {
12b55ccc
L		 5449 case 'n':
5450 optimize_align_code = 0;
5451 break;
5452
a38cf1db
AM		 5453 case 'q':
5454 quiet_warnings = 1;
252b5132
RH		 5455 break;
5456
5457#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5458 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5459 should be emitted or not. FIXME: Not implemented. */
5460 case 'Q':
252b5132
RH		 5461 break;
5462
5463 /* -V: SVR4 argument to print version ID. */
5464 case 'V':
5465 print_version_id ();
5466 break;
5467
a38cf1db
AM		 5468 /* -k: Ignore for FreeBSD compatibility. */
5469 case 'k':
252b5132 5470 break;
4cc782b5
ILT		 5471
5472 case 's':
5473 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5474 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5475 break;
6e0b89ee 5476
3e73aa7c
JH		 5477 case OPTION_64:
5478 {
5479 const char **list, **l;
5480
3e73aa7c
JH		 5481 list = bfd_target_list ();
5482 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5483 if (strcmp (*l, "elf64-x86-64") == 0)
5484 {
5485 default_arch = "x86_64";
5486 break;
5487 }
3e73aa7c 5488 if (*l == NULL)
6e0b89ee 5489 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5490 free (list);
5491 }
5492 break;
5493#endif
252b5132 5494
6e0b89ee
AM		 5495 case OPTION_32:
5496 default_arch = "i386";
5497 break;
5498
b3b91714
AM		 5499 case OPTION_DIVIDE:
5500#ifdef SVR4_COMMENT_CHARS
5501 {
5502 char *n, *t;
5503 const char *s;
5504
5505 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5506 t = n;
5507 for (s = i386_comment_chars; *s != '\0'; s++)
5508 if (*s != '/')
5509 *t++ = *s;
5510 *t = '\0';
5511 i386_comment_chars = n;
5512 }
5513#endif
5514 break;
5515
252b5132
RH		 5516 default:
5517 return 0;
5518 }
5519 return 1;
5520}
5521
5522void
5523md_show_usage (stream)
5524 FILE *stream;
5525{
4cc782b5
ILT		 5526#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5527 fprintf (stream, _("\
a38cf1db
AM		 5528 -Q ignored\n\
5529 -V print assembler version number\n\
b3b91714
AM		 5530 -k ignored\n"));
5531#endif
5532 fprintf (stream, _("\
12b55ccc 5533 -n Do not optimize code alignment\n\
b3b91714
AM		 5534 -q quieten some warnings\n"));
5535#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5536 fprintf (stream, _("\
a38cf1db 5537 -s ignored\n"));
b3b91714
AM		 5538#endif
5539#ifdef SVR4_COMMENT_CHARS
5540 fprintf (stream, _("\
5541 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5542#else
5543 fprintf (stream, _("\
b3b91714 5544 --divide ignored\n"));
4cc782b5 5545#endif
252b5132
RH		 5546}
5547
3e73aa7c
JH		 5548#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5549 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5550
5551/* Pick the target format to use. */
5552
47926f60 5553const char *
252b5132
RH		 5554i386_target_format ()
5555{
3e73aa7c
JH		 5556 if (!strcmp (default_arch, "x86_64"))
5557 set_code_flag (CODE_64BIT);
5558 else if (!strcmp (default_arch, "i386"))
5559 set_code_flag (CODE_32BIT);
5560 else
5561 as_fatal (_("Unknown architecture"));
252b5132
RH		 5562 switch (OUTPUT_FLAVOR)
5563 {
4c63da97
AM		 5564#ifdef OBJ_MAYBE_AOUT
5565 case bfd_target_aout_flavour:
47926f60 5566 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5567#endif
5568#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5569 case bfd_target_coff_flavour:
5570 return "coff-i386";
4c63da97 5571#endif
3e73aa7c 5572#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5573 case bfd_target_elf_flavour:
3e73aa7c 5574 {
e5cb08ac 5575 if (flag_code == CODE_64BIT)
4fa24527
JB		 5576 {
5577 object_64bit = 1;
5578 use_rela_relocations = 1;
5579 }
4ada7262 5580 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5581 }
4c63da97 5582#endif
252b5132
RH		 5583 default:
5584 abort ();
5585 return NULL;
5586 }
5587}
5588
47926f60 5589#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5590
5591#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5592void i386_elf_emit_arch_note ()
5593{
718ddfc0 5594 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5595 {
5596 char *p;
5597 asection *seg = now_seg;
5598 subsegT subseg = now_subseg;
5599 Elf_Internal_Note i_note;
5600 Elf_External_Note e_note;
5601 asection *note_secp;
5602 int len;
5603
5604 /* Create the .note section. */
5605 note_secp = subseg_new (".note", 0);
5606 bfd_set_section_flags (stdoutput,
5607 note_secp,
5608 SEC_HAS_CONTENTS | SEC_READONLY);
5609
5610 /* Process the arch string. */
5611 len = strlen (cpu_arch_name);
5612
5613 i_note.namesz = len + 1;
5614 i_note.descsz = 0;
5615 i_note.type = NT_ARCH;
5616 p = frag_more (sizeof (e_note.namesz));
5617 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5618 p = frag_more (sizeof (e_note.descsz));
5619 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5620 p = frag_more (sizeof (e_note.type));
5621 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5622 p = frag_more (len + 1);
5623 strcpy (p, cpu_arch_name);
5624
5625 frag_align (2, 0, 0);
5626
5627 subseg_set (seg, subseg);
5628 }
5629}
5630#endif
252b5132 5631\f
252b5132
RH		 5632symbolS *
5633md_undefined_symbol (name)
5634 char *name;
5635{
18dc2407
ILT		 5636 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5637 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5638 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5639 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5640 {
5641 if (!GOT_symbol)
5642 {
5643 if (symbol_find (name))
5644 as_bad (_("GOT already in symbol table"));
5645 GOT_symbol = symbol_new (name, undefined_section,
5646 (valueT) 0, &zero_address_frag);
5647 };
5648 return GOT_symbol;
5649 }
252b5132
RH		 5650 return 0;
5651}
5652
5653/* Round up a section size to the appropriate boundary. */
47926f60 5654
252b5132
RH		 5655valueT
5656md_section_align (segment, size)
ab9da554 5657 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5658 valueT size;
5659{
4c63da97
AM		 5660#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5661 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5662 {
5663 /* For a.out, force the section size to be aligned. If we don't do
5664 this, BFD will align it for us, but it will not write out the
5665 final bytes of the section. This may be a bug in BFD, but it is
5666 easier to fix it here since that is how the other a.out targets
5667 work. */
5668 int align;
5669
5670 align = bfd_get_section_alignment (stdoutput, segment);
5671 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5672 }
252b5132
RH		 5673#endif
5674
5675 return size;
5676}
5677
5678/* On the i386, PC-relative offsets are relative to the start of the
5679 next instruction. That is, the address of the offset, plus its
5680 size, since the offset is always the last part of the insn. */
5681
5682long
5683md_pcrel_from (fixP)
5684 fixS *fixP;
5685{
5686 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5687}
5688
5689#ifndef I386COFF
5690
5691static void
5692s_bss (ignore)
ab9da554 5693 int ignore ATTRIBUTE_UNUSED;
252b5132 5694{
29b0f896 5695 int temp;
252b5132 5696
8a75718c
JB		 5697#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5698 if (IS_ELF)
5699 obj_elf_section_change_hook ();
5700#endif
252b5132
RH		 5701 temp = get_absolute_expression ();
5702 subseg_set (bss_section, (subsegT) temp);
5703 demand_empty_rest_of_line ();
5704}
5705
5706#endif
5707
252b5132
RH		 5708void
5709i386_validate_fix (fixp)
5710 fixS *fixp;
5711{
5712 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5713 {
23df1078
JH		 5714 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5715 {
4fa24527 5716 if (!object_64bit)
23df1078
JH		 5717 abort ();
5718 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5719 }
5720 else
5721 {
4fa24527 5722 if (!object_64bit)
d6ab8113
JB		 5723 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5724 else
5725 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5726 }
252b5132
RH		 5727 fixp->fx_subsy = 0;
5728 }
5729}
5730
252b5132
RH		 5731arelent *
5732tc_gen_reloc (section, fixp)
ab9da554 5733 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5734 fixS *fixp;
5735{
5736 arelent *rel;
5737 bfd_reloc_code_real_type code;
5738
5739 switch (fixp->fx_r_type)
5740 {
3e73aa7c
JH		 5741 case BFD_RELOC_X86_64_PLT32:
5742 case BFD_RELOC_X86_64_GOT32:
5743 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5744 case BFD_RELOC_386_PLT32:
5745 case BFD_RELOC_386_GOT32:
5746 case BFD_RELOC_386_GOTOFF:
5747 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5748 case BFD_RELOC_386_TLS_GD:
5749 case BFD_RELOC_386_TLS_LDM:
5750 case BFD_RELOC_386_TLS_LDO_32:
5751 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5752 case BFD_RELOC_386_TLS_IE:
5753 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5754 case BFD_RELOC_386_TLS_LE_32:
5755 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 5756 case BFD_RELOC_386_TLS_GOTDESC:
5757 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 5758 case BFD_RELOC_X86_64_TLSGD:
5759 case BFD_RELOC_X86_64_TLSLD:
5760 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5761 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5762 case BFD_RELOC_X86_64_GOTTPOFF:
5763 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5764 case BFD_RELOC_X86_64_TPOFF64:
5765 case BFD_RELOC_X86_64_GOTOFF64:
5766 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 5767 case BFD_RELOC_X86_64_GOT64:
5768 case BFD_RELOC_X86_64_GOTPCREL64:
5769 case BFD_RELOC_X86_64_GOTPC64:
5770 case BFD_RELOC_X86_64_GOTPLT64:
5771 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 5772 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5773 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 5774 case BFD_RELOC_RVA:
5775 case BFD_RELOC_VTABLE_ENTRY:
5776 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5777#ifdef TE_PE
5778 case BFD_RELOC_32_SECREL:
5779#endif
252b5132
RH		 5780 code = fixp->fx_r_type;
5781 break;
dbbaec26
L		 5782 case BFD_RELOC_X86_64_32S:
5783 if (!fixp->fx_pcrel)
5784 {
5785 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5786 code = fixp->fx_r_type;
5787 break;
5788 }
252b5132 5789 default:
93382f6d 5790 if (fixp->fx_pcrel)
252b5132 5791 {
93382f6d
AM		 5792 switch (fixp->fx_size)
5793 {
5794 default:
b091f402
AM		 5795 as_bad_where (fixp->fx_file, fixp->fx_line,
5796 _("can not do %d byte pc-relative relocation"),
5797 fixp->fx_size);
93382f6d
AM		 5798 code = BFD_RELOC_32_PCREL;
5799 break;
5800 case 1: code = BFD_RELOC_8_PCREL; break;
5801 case 2: code = BFD_RELOC_16_PCREL; break;
5802 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5803#ifdef BFD64
5804 case 8: code = BFD_RELOC_64_PCREL; break;
5805#endif
93382f6d
AM		 5806 }
5807 }
5808 else
5809 {
5810 switch (fixp->fx_size)
5811 {
5812 default:
b091f402
AM		 5813 as_bad_where (fixp->fx_file, fixp->fx_line,
5814 _("can not do %d byte relocation"),
5815 fixp->fx_size);
93382f6d
AM		 5816 code = BFD_RELOC_32;
5817 break;
5818 case 1: code = BFD_RELOC_8; break;
5819 case 2: code = BFD_RELOC_16; break;
5820 case 4: code = BFD_RELOC_32; break;
937149dd 5821#ifdef BFD64
3e73aa7c 5822 case 8: code = BFD_RELOC_64; break;
937149dd 5823#endif
93382f6d 5824 }
252b5132
RH		 5825 }
5826 break;
5827 }
252b5132 5828
d182319b
JB		 5829 if ((code == BFD_RELOC_32
5830 || code == BFD_RELOC_32_PCREL
5831 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 5832 && GOT_symbol
5833 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5834 {
4fa24527 5835 if (!object_64bit)
d6ab8113
JB		 5836 code = BFD_RELOC_386_GOTPC;
5837 else
5838 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5839 }
7b81dfbb
AJ		 5840 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
5841 && GOT_symbol
5842 && fixp->fx_addsy == GOT_symbol)
5843 {
5844 code = BFD_RELOC_X86_64_GOTPC64;
5845 }
252b5132
RH		 5846
5847 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5848 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5849 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5850
5851 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5852
3e73aa7c
JH		 5853 if (!use_rela_relocations)
5854 {
5855 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5856 vtable entry to be used in the relocation's section offset. */
5857 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5858 rel->address = fixp->fx_offset;
252b5132 5859
c6682705 5860 rel->addend = 0;
3e73aa7c
JH		 5861 }
5862 /* Use the rela in 64bit mode. */
252b5132 5863 else
3e73aa7c 5864 {
062cd5e7
AS		 5865 if (!fixp->fx_pcrel)
5866 rel->addend = fixp->fx_offset;
5867 else
5868 switch (code)
5869 {
5870 case BFD_RELOC_X86_64_PLT32:
5871 case BFD_RELOC_X86_64_GOT32:
5872 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5873 case BFD_RELOC_X86_64_TLSGD:
5874 case BFD_RELOC_X86_64_TLSLD:
5875 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 5876 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5877 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 5878 rel->addend = fixp->fx_offset - fixp->fx_size;
5879 break;
5880 default:
5881 rel->addend = (section->vma
5882 - fixp->fx_size
5883 + fixp->fx_addnumber
5884 + md_pcrel_from (fixp));
5885 break;
5886 }
3e73aa7c
JH		 5887 }
5888
252b5132
RH		 5889 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5890 if (rel->howto == NULL)
5891 {
5892 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5893 _("cannot represent relocation type %s"),
252b5132
RH		 5894 bfd_get_reloc_code_name (code));
5895 /* Set howto to a garbage value so that we can keep going. */
5896 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5897 assert (rel->howto != NULL);
5898 }
5899
5900 return rel;
5901}
5902
64a0c779
DN		 5903\f
5904/* Parse operands using Intel syntax. This implements a recursive descent
5905 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5906 Programmer's Guide.
5907
5908 FIXME: We do not recognize the full operand grammar defined in the MASM
5909 documentation. In particular, all the structure/union and
5910 high-level macro operands are missing.
5911
5912 Uppercase words are terminals, lower case words are non-terminals.
5913 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5914 bars '|' denote choices. Most grammar productions are implemented in
5915 functions called 'intel_<production>'.
5916
5917 Initial production is 'expr'.
5918
9306ca4a 5919 addOp + | -
64a0c779
DN		 5920
5921 alpha [a-zA-Z]
5922
9306ca4a
JB		 5923 binOp & | AND | \| | OR | ^ | XOR
5924
64a0c779
DN		 5925 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5926
5927 constant digits [[ radixOverride ]]
5928
9306ca4a 5929 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5930
5931 digits decdigit
b77a7acd
AJ		 5932 | digits decdigit
5933 | digits hexdigit
64a0c779
DN		 5934
5935 decdigit [0-9]
5936
9306ca4a
JB		 5937 e04 e04 addOp e05
5938 | e05
5939
5940 e05 e05 binOp e06
b77a7acd 5941 | e06
64a0c779
DN		 5942
5943 e06 e06 mulOp e09
b77a7acd 5944 | e09
64a0c779
DN		 5945
5946 e09 OFFSET e10
a724f0f4
JB		 5947 | SHORT e10
5948 | + e10
5949 | - e10
9306ca4a
JB		 5950 | ~ e10
5951 | NOT e10
64a0c779
DN		 5952 | e09 PTR e10
5953 | e09 : e10
5954 | e10
5955
5956 e10 e10 [ expr ]
b77a7acd 5957 | e11
64a0c779
DN		 5958
5959 e11 ( expr )
b77a7acd 5960 | [ expr ]
64a0c779
DN		 5961 | constant
5962 | dataType
5963 | id
5964 | $
5965 | register
5966
a724f0f4 5967 => expr expr cmpOp e04
9306ca4a 5968 | e04
64a0c779
DN		 5969
5970 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5971 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5972
5973 hexdigit a | b | c | d | e | f
b77a7acd 5974 | A | B | C | D | E | F
64a0c779
DN		 5975
5976 id alpha
b77a7acd 5977 | id alpha
64a0c779
DN		 5978 | id decdigit
5979
9306ca4a 5980 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5981
5982 quote " | '
5983
5984 register specialRegister
b77a7acd 5985 | gpRegister
64a0c779
DN		 5986 | byteRegister
5987
5988 segmentRegister CS | DS | ES | FS | GS | SS
5989
9306ca4a 5990 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5991 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5992 | TR3 | TR4 | TR5 | TR6 | TR7
5993
64a0c779
DN		 5994 We simplify the grammar in obvious places (e.g., register parsing is
5995 done by calling parse_register) and eliminate immediate left recursion
5996 to implement a recursive-descent parser.
5997
a724f0f4
JB		 5998 expr e04 expr'
5999
6000 expr' cmpOp e04 expr'
6001 | Empty
9306ca4a
JB		 6002
6003 e04 e05 e04'
6004
6005 e04' addOp e05 e04'
6006 | Empty
64a0c779
DN		 6007
6008 e05 e06 e05'
6009
9306ca4a 6010 e05' binOp e06 e05'
b77a7acd 6011 | Empty
64a0c779
DN		 6012
6013 e06 e09 e06'
6014
6015 e06' mulOp e09 e06'
b77a7acd 6016 | Empty
64a0c779
DN		 6017
6018 e09 OFFSET e10 e09'
a724f0f4
JB		 6019 | SHORT e10'
6020 | + e10'
6021 | - e10'
6022 | ~ e10'
6023 | NOT e10'
b77a7acd 6024 | e10 e09'
64a0c779
DN		 6025
6026 e09' PTR e10 e09'
b77a7acd 6027 | : e10 e09'
64a0c779
DN		 6028 | Empty
6029
6030 e10 e11 e10'
6031
6032 e10' [ expr ] e10'
b77a7acd 6033 | Empty
64a0c779
DN		 6034
6035 e11 ( expr )
b77a7acd 6036 | [ expr ]
64a0c779
DN		 6037 | BYTE
6038 | WORD
6039 | DWORD
9306ca4a 6040 | FWORD
64a0c779 6041 | QWORD
9306ca4a
JB		 6042 | TBYTE
6043 | OWORD
6044 | XMMWORD
64a0c779
DN		 6045 | .
6046 | $
6047 | register
6048 | id
6049 | constant */
6050
6051/* Parsing structure for the intel syntax parser. Used to implement the
6052 semantic actions for the operand grammar. */
6053struct intel_parser_s
6054 {
6055 char *op_string; /* The string being parsed. */
6056 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6057 int op_modifier; /* Operand modifier. */
64a0c779 6058 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6059 int in_offset; /* >=1 if parsing operand of offset. */
6060 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6061 const reg_entry *reg; /* Last register reference found. */
6062 char *disp; /* Displacement string being built. */
a724f0f4 6063 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6064 };
6065
6066static struct intel_parser_s intel_parser;
6067
6068/* Token structure for parsing intel syntax. */
6069struct intel_token
6070 {
6071 int code; /* Token code. */
6072 const reg_entry *reg; /* Register entry for register tokens. */
6073 char *str; /* String representation. */
6074 };
6075
6076static struct intel_token cur_token, prev_token;
6077
50705ef4
AM		 6078/* Token codes for the intel parser. Since T_SHORT is already used
6079 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6080#define T_NIL -1
6081#define T_CONST 1
6082#define T_REG 2
6083#define T_BYTE 3
6084#define T_WORD 4
9306ca4a
JB		 6085#define T_DWORD 5
6086#define T_FWORD 6
6087#define T_QWORD 7
6088#define T_TBYTE 8
6089#define T_XMMWORD 9
50705ef4 6090#undef T_SHORT
9306ca4a
JB		 6091#define T_SHORT 10
6092#define T_OFFSET 11
6093#define T_PTR 12
6094#define T_ID 13
6095#define T_SHL 14
6096#define T_SHR 15
64a0c779
DN		 6097
6098/* Prototypes for intel parser functions. */
6099static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6100static void intel_get_token PARAMS ((void));
6101static void intel_putback_token PARAMS ((void));
6102static int intel_expr PARAMS ((void));
9306ca4a 6103static int intel_e04 PARAMS ((void));
cce0cbdc 6104static int intel_e05 PARAMS ((void));
cce0cbdc 6105static int intel_e06 PARAMS ((void));
cce0cbdc 6106static int intel_e09 PARAMS ((void));
a724f0f4 6107static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6108static int intel_e10 PARAMS ((void));
cce0cbdc 6109static int intel_e11 PARAMS ((void));
64a0c779 6110
64a0c779
DN		 6111static int
6112i386_intel_operand (operand_string, got_a_float)
6113 char *operand_string;
6114 int got_a_float;
6115{
6116 int ret;
6117 char *p;
6118
a724f0f4
JB		 6119 p = intel_parser.op_string = xstrdup (operand_string);
6120 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6121
6122 for (;;)
64a0c779 6123 {
a724f0f4
JB		 6124 /* Initialize token holders. */
6125 cur_token.code = prev_token.code = T_NIL;
6126 cur_token.reg = prev_token.reg = NULL;
6127 cur_token.str = prev_token.str = NULL;
6128
6129 /* Initialize parser structure. */
6130 intel_parser.got_a_float = got_a_float;
6131 intel_parser.op_modifier = 0;
6132 intel_parser.is_mem = 0;
6133 intel_parser.in_offset = 0;
6134 intel_parser.in_bracket = 0;
6135 intel_parser.reg = NULL;
6136 intel_parser.disp[0] = '\0';
6137 intel_parser.next_operand = NULL;
6138
6139 /* Read the first token and start the parser. */
6140 intel_get_token ();
6141 ret = intel_expr ();
6142
6143 if (!ret)
6144 break;
6145
9306ca4a
JB		 6146 if (cur_token.code != T_NIL)
6147 {
6148 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6149 current_templates->start->name, cur_token.str);
6150 ret = 0;
6151 }
64a0c779
DN		 6152 /* If we found a memory reference, hand it over to i386_displacement
6153 to fill in the rest of the operand fields. */
9306ca4a 6154 else if (intel_parser.is_mem)
64a0c779
DN		 6155 {
6156 if ((i.mem_operands == 1
6157 && (current_templates->start->opcode_modifier & IsString) == 0)
6158 || i.mem_operands == 2)
6159 {
6160 as_bad (_("too many memory references for '%s'"),
6161 current_templates->start->name);
6162 ret = 0;
6163 }
6164 else
6165 {
6166 char *s = intel_parser.disp;
6167 i.mem_operands++;
6168
a724f0f4
JB		 6169 if (!quiet_warnings && intel_parser.is_mem < 0)
6170 /* See the comments in intel_bracket_expr. */
6171 as_warn (_("Treating `%s' as memory reference"), operand_string);
6172
64a0c779
DN		 6173 /* Add the displacement expression. */
6174 if (*s != '\0')
a4622f40
AM		 6175 ret = i386_displacement (s, s + strlen (s));
6176 if (ret)
a724f0f4
JB		 6177 {
6178 /* Swap base and index in 16-bit memory operands like
6179 [si+bx]. Since i386_index_check is also used in AT&T
6180 mode we have to do that here. */
6181 if (i.base_reg
6182 && i.index_reg
6183 && (i.base_reg->reg_type & Reg16)
6184 && (i.index_reg->reg_type & Reg16)
6185 && i.base_reg->reg_num >= 6
6186 && i.index_reg->reg_num < 6)
6187 {
6188 const reg_entry *base = i.index_reg;
6189
6190 i.index_reg = i.base_reg;
6191 i.base_reg = base;
6192 }
6193 ret = i386_index_check (operand_string);
6194 }
64a0c779
DN		 6195 }
6196 }
6197
6198 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6199 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6200 || intel_parser.reg == NULL)
6201 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6202
6203 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6204 ret = 0;
6205 if (!ret || !intel_parser.next_operand)
6206 break;
6207 intel_parser.op_string = intel_parser.next_operand;
6208 this_operand = i.operands++;
64a0c779
DN		 6209 }
6210
6211 free (p);
6212 free (intel_parser.disp);
6213
6214 return ret;
6215}
6216
a724f0f4
JB		 6217#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6218
6219/* expr e04 expr'
6220
6221 expr' cmpOp e04 expr'
6222 | Empty */
64a0c779
DN		 6223static int
6224intel_expr ()
6225{
a724f0f4
JB		 6226 /* XXX Implement the comparison operators. */
6227 return intel_e04 ();
9306ca4a
JB		 6228}
6229
a724f0f4 6230/* e04 e05 e04'
9306ca4a 6231
a724f0f4 6232 e04' addOp e05 e04'
9306ca4a
JB		 6233 | Empty */
6234static int
6235intel_e04 ()
6236{
a724f0f4 6237 int nregs = -1;
9306ca4a 6238
a724f0f4 6239 for (;;)
9306ca4a 6240 {
a724f0f4
JB		 6241 if (!intel_e05())
6242 return 0;
9306ca4a 6243
a724f0f4
JB		 6244 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6245 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6246
a724f0f4
JB		 6247 if (cur_token.code == '+')
6248 nregs = -1;
6249 else if (cur_token.code == '-')
6250 nregs = NUM_ADDRESS_REGS;
6251 else
6252 return 1;
64a0c779 6253
a724f0f4
JB		 6254 strcat (intel_parser.disp, cur_token.str);
6255 intel_match_token (cur_token.code);
6256 }
64a0c779
DN		 6257}
6258
64a0c779
DN		 6259/* e05 e06 e05'
6260
9306ca4a 6261 e05' binOp e06 e05'
64a0c779
DN		 6262 | Empty */
6263static int
6264intel_e05 ()
6265{
a724f0f4 6266 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6267
a724f0f4 6268 for (;;)
64a0c779 6269 {
a724f0f4
JB		 6270 if (!intel_e06())
6271 return 0;
6272
6273 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6274 {
6275 char str[2];
6276
6277 str[0] = cur_token.code;
6278 str[1] = 0;
6279 strcat (intel_parser.disp, str);
6280 }
6281 else
6282 break;
9306ca4a 6283
64a0c779
DN		 6284 intel_match_token (cur_token.code);
6285
a724f0f4
JB		 6286 if (nregs < 0)
6287 nregs = ~nregs;
64a0c779 6288 }
a724f0f4
JB		 6289 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6290 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6291 return 1;
4a1805b1 6292}
64a0c779
DN		 6293
6294/* e06 e09 e06'
6295
6296 e06' mulOp e09 e06'
b77a7acd 6297 | Empty */
64a0c779
DN		 6298static int
6299intel_e06 ()
6300{
a724f0f4 6301 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6302
a724f0f4 6303 for (;;)
64a0c779 6304 {
a724f0f4
JB		 6305 if (!intel_e09())
6306 return 0;
9306ca4a 6307
a724f0f4
JB		 6308 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6309 {
6310 char str[2];
9306ca4a 6311
a724f0f4
JB		 6312 str[0] = cur_token.code;
6313 str[1] = 0;
6314 strcat (intel_parser.disp, str);
6315 }
6316 else if (cur_token.code == T_SHL)
6317 strcat (intel_parser.disp, "<<");
6318 else if (cur_token.code == T_SHR)
6319 strcat (intel_parser.disp, ">>");
6320 else
6321 break;
9306ca4a 6322
64e74474 6323 intel_match_token (cur_token.code);
64a0c779 6324
a724f0f4
JB		 6325 if (nregs < 0)
6326 nregs = ~nregs;
64a0c779 6327 }
a724f0f4
JB		 6328 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6329 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6330 return 1;
64a0c779
DN		 6331}
6332
a724f0f4
JB		 6333/* e09 OFFSET e09
6334 | SHORT e09
6335 | + e09
6336 | - e09
6337 | ~ e09
6338 | NOT e09
9306ca4a
JB		 6339 | e10 e09'
6340
64a0c779 6341 e09' PTR e10 e09'
b77a7acd 6342 | : e10 e09'
64a0c779
DN		 6343 | Empty */
6344static int
6345intel_e09 ()
6346{
a724f0f4
JB		 6347 int nregs = ~NUM_ADDRESS_REGS;
6348 int in_offset = 0;
6349
6350 for (;;)
64a0c779 6351 {
a724f0f4
JB		 6352 /* Don't consume constants here. */
6353 if (cur_token.code == '+' || cur_token.code == '-')
6354 {
6355 /* Need to look one token ahead - if the next token
6356 is a constant, the current token is its sign. */
6357 int next_code;
6358
6359 intel_match_token (cur_token.code);
6360 next_code = cur_token.code;
6361 intel_putback_token ();
6362 if (next_code == T_CONST)
6363 break;
6364 }
6365
6366 /* e09 OFFSET e09 */
6367 if (cur_token.code == T_OFFSET)
6368 {
6369 if (!in_offset++)
6370 ++intel_parser.in_offset;
6371 }
6372
6373 /* e09 SHORT e09 */
6374 else if (cur_token.code == T_SHORT)
6375 intel_parser.op_modifier |= 1 << T_SHORT;
6376
6377 /* e09 + e09 */
6378 else if (cur_token.code == '+')
6379 strcat (intel_parser.disp, "+");
6380
6381 /* e09 - e09
6382 | ~ e09
6383 | NOT e09 */
6384 else if (cur_token.code == '-' || cur_token.code == '~')
6385 {
6386 char str[2];
64a0c779 6387
a724f0f4
JB		 6388 if (nregs < 0)
6389 nregs = ~nregs;
6390 str[0] = cur_token.code;
6391 str[1] = 0;
6392 strcat (intel_parser.disp, str);
6393 }
6394
6395 /* e09 e10 e09' */
6396 else
6397 break;
6398
6399 intel_match_token (cur_token.code);
64a0c779
DN		 6400 }
6401
a724f0f4 6402 for (;;)
9306ca4a 6403 {
a724f0f4
JB		 6404 if (!intel_e10 ())
6405 return 0;
9306ca4a 6406
a724f0f4
JB		 6407 /* e09' PTR e10 e09' */
6408 if (cur_token.code == T_PTR)
6409 {
6410 char suffix;
9306ca4a 6411
a724f0f4
JB		 6412 if (prev_token.code == T_BYTE)
6413 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6414
a724f0f4
JB		 6415 else if (prev_token.code == T_WORD)
6416 {
6417 if (current_templates->start->name[0] == 'l'
6418 && current_templates->start->name[2] == 's'
6419 && current_templates->start->name[3] == 0)
6420 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6421 else if (intel_parser.got_a_float == 2) /* "fi..." */
6422 suffix = SHORT_MNEM_SUFFIX;
6423 else
6424 suffix = WORD_MNEM_SUFFIX;
6425 }
64a0c779 6426
a724f0f4
JB		 6427 else if (prev_token.code == T_DWORD)
6428 {
6429 if (current_templates->start->name[0] == 'l'
6430 && current_templates->start->name[2] == 's'
6431 && current_templates->start->name[3] == 0)
6432 suffix = WORD_MNEM_SUFFIX;
6433 else if (flag_code == CODE_16BIT
6434 && (current_templates->start->opcode_modifier
435acd52 6435 & (Jump | JumpDword)))
a724f0f4
JB		 6436 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6437 else if (intel_parser.got_a_float == 1) /* "f..." */
6438 suffix = SHORT_MNEM_SUFFIX;
6439 else
6440 suffix = LONG_MNEM_SUFFIX;
6441 }
9306ca4a 6442
a724f0f4
JB		 6443 else if (prev_token.code == T_FWORD)
6444 {
6445 if (current_templates->start->name[0] == 'l'
6446 && current_templates->start->name[2] == 's'
6447 && current_templates->start->name[3] == 0)
6448 suffix = LONG_MNEM_SUFFIX;
6449 else if (!intel_parser.got_a_float)
6450 {
6451 if (flag_code == CODE_16BIT)
6452 add_prefix (DATA_PREFIX_OPCODE);
6453 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6454 }
6455 else
6456 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6457 }
64a0c779 6458
a724f0f4
JB		 6459 else if (prev_token.code == T_QWORD)
6460 {
6461 if (intel_parser.got_a_float == 1) /* "f..." */
6462 suffix = LONG_MNEM_SUFFIX;
6463 else
6464 suffix = QWORD_MNEM_SUFFIX;
6465 }
64a0c779 6466
a724f0f4
JB		 6467 else if (prev_token.code == T_TBYTE)
6468 {
6469 if (intel_parser.got_a_float == 1)
6470 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6471 else
6472 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6473 }
9306ca4a 6474
a724f0f4 6475 else if (prev_token.code == T_XMMWORD)
9306ca4a 6476 {
a724f0f4
JB		 6477 /* XXX ignored for now, but accepted since gcc uses it */
6478 suffix = 0;
9306ca4a 6479 }
64a0c779 6480
f16b83df 6481 else
a724f0f4
JB		 6482 {
6483 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6484 return 0;
6485 }
6486
435acd52
JB		 6487 /* Operands for jump/call using 'ptr' notation denote absolute
6488 addresses. */
6489 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6490 i.types[this_operand] |= JumpAbsolute;
6491
a724f0f4
JB		 6492 if (current_templates->start->base_opcode == 0x8d /* lea */)
6493 ;
6494 else if (!i.suffix)
6495 i.suffix = suffix;
6496 else if (i.suffix != suffix)
6497 {
6498 as_bad (_("Conflicting operand modifiers"));
6499 return 0;
6500 }
64a0c779 6501
9306ca4a
JB		 6502 }
6503
a724f0f4
JB		 6504 /* e09' : e10 e09' */
6505 else if (cur_token.code == ':')
9306ca4a 6506 {
a724f0f4
JB		 6507 if (prev_token.code != T_REG)
6508 {
6509 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6510 segment/group identifier (which we don't have), using comma
6511 as the operand separator there is even less consistent, since
6512 there all branches only have a single operand. */
6513 if (this_operand != 0
6514 || intel_parser.in_offset
6515 || intel_parser.in_bracket
6516 || (!(current_templates->start->opcode_modifier
6517 & (Jump|JumpDword|JumpInterSegment))
6518 && !(current_templates->start->operand_types[0]
6519 & JumpAbsolute)))
6520 return intel_match_token (T_NIL);
6521 /* Remember the start of the 2nd operand and terminate 1st
6522 operand here.
6523 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6524 another expression), but it gets at least the simplest case
6525 (a plain number or symbol on the left side) right. */
6526 intel_parser.next_operand = intel_parser.op_string;
6527 *--intel_parser.op_string = '\0';
6528 return intel_match_token (':');
6529 }
9306ca4a 6530 }
64a0c779 6531
a724f0f4 6532 /* e09' Empty */
64a0c779 6533 else
a724f0f4 6534 break;
64a0c779 6535
a724f0f4
JB		 6536 intel_match_token (cur_token.code);
6537
6538 }
6539
6540 if (in_offset)
6541 {
6542 --intel_parser.in_offset;
6543 if (nregs < 0)
6544 nregs = ~nregs;
6545 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6546 {
a724f0f4 6547 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6548 return 0;
6549 }
a724f0f4
JB		 6550 intel_parser.op_modifier |= 1 << T_OFFSET;
6551 }
9306ca4a 6552
a724f0f4
JB		 6553 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6554 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6555 return 1;
6556}
64a0c779 6557
a724f0f4
JB		 6558static int
6559intel_bracket_expr ()
6560{
6561 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6562 const char *start = intel_parser.op_string;
6563 int len;
6564
6565 if (i.op[this_operand].regs)
6566 return intel_match_token (T_NIL);
6567
6568 intel_match_token ('[');
6569
6570 /* Mark as a memory operand only if it's not already known to be an
6571 offset expression. If it's an offset expression, we need to keep
6572 the brace in. */
6573 if (!intel_parser.in_offset)
6574 {
6575 ++intel_parser.in_bracket;
435acd52
JB		 6576
6577 /* Operands for jump/call inside brackets denote absolute addresses. */
6578 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6579 i.types[this_operand] |= JumpAbsolute;
6580
a724f0f4
JB		 6581 /* Unfortunately gas always diverged from MASM in a respect that can't
6582 be easily fixed without risking to break code sequences likely to be
6583 encountered (the testsuite even check for this): MASM doesn't consider
6584 an expression inside brackets unconditionally as a memory reference.
6585 When that is e.g. a constant, an offset expression, or the sum of the
6586 two, this is still taken as a constant load. gas, however, always
6587 treated these as memory references. As a compromise, we'll try to make
6588 offset expressions inside brackets work the MASM way (since that's
6589 less likely to be found in real world code), but make constants alone
6590 continue to work the traditional gas way. In either case, issue a
6591 warning. */
6592 intel_parser.op_modifier &= ~was_offset;
64a0c779 6593 }
a724f0f4 6594 else
64e74474 6595 strcat (intel_parser.disp, "[");
a724f0f4
JB		 6596
6597 /* Add a '+' to the displacement string if necessary. */
6598 if (*intel_parser.disp != '\0'
6599 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6600 strcat (intel_parser.disp, "+");
64a0c779 6601
a724f0f4
JB		 6602 if (intel_expr ()
6603 && (len = intel_parser.op_string - start - 1,
6604 intel_match_token (']')))
64a0c779 6605 {
a724f0f4
JB		 6606 /* Preserve brackets when the operand is an offset expression. */
6607 if (intel_parser.in_offset)
6608 strcat (intel_parser.disp, "]");
6609 else
6610 {
6611 --intel_parser.in_bracket;
6612 if (i.base_reg || i.index_reg)
6613 intel_parser.is_mem = 1;
6614 if (!intel_parser.is_mem)
6615 {
6616 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6617 /* Defer the warning until all of the operand was parsed. */
6618 intel_parser.is_mem = -1;
6619 else if (!quiet_warnings)
6620 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6621 }
6622 }
6623 intel_parser.op_modifier |= was_offset;
64a0c779 6624
a724f0f4 6625 return 1;
64a0c779 6626 }
a724f0f4 6627 return 0;
64a0c779
DN		 6628}
6629
6630/* e10 e11 e10'
6631
6632 e10' [ expr ] e10'
b77a7acd 6633 | Empty */
64a0c779
DN		 6634static int
6635intel_e10 ()
6636{
a724f0f4
JB		 6637 if (!intel_e11 ())
6638 return 0;
64a0c779 6639
a724f0f4 6640 while (cur_token.code == '[')
64a0c779 6641 {
a724f0f4 6642 if (!intel_bracket_expr ())
21d6c4af 6643 return 0;
64a0c779
DN		 6644 }
6645
a724f0f4 6646 return 1;
64a0c779
DN		 6647}
6648
64a0c779 6649/* e11 ( expr )
b77a7acd 6650 | [ expr ]
64a0c779
DN		 6651 | BYTE
6652 | WORD
6653 | DWORD
9306ca4a 6654 | FWORD
64a0c779 6655 | QWORD
9306ca4a
JB		 6656 | TBYTE
6657 | OWORD
6658 | XMMWORD
4a1805b1 6659 | $
64a0c779
DN		 6660 | .
6661 | register
6662 | id
6663 | constant */
6664static int
6665intel_e11 ()
6666{
a724f0f4 6667 switch (cur_token.code)
64a0c779 6668 {
a724f0f4
JB		 6669 /* e11 ( expr ) */
6670 case '(':
64a0c779
DN		 6671 intel_match_token ('(');
6672 strcat (intel_parser.disp, "(");
6673
6674 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6675 {
6676 strcat (intel_parser.disp, ")");
6677 return 1;
6678 }
a724f0f4 6679 return 0;
4a1805b1 6680
a724f0f4
JB		 6681 /* e11 [ expr ] */
6682 case '[':
a724f0f4 6683 return intel_bracket_expr ();
64a0c779 6684
a724f0f4
JB		 6685 /* e11 $
6686 | . */
6687 case '.':
64a0c779
DN		 6688 strcat (intel_parser.disp, cur_token.str);
6689 intel_match_token (cur_token.code);
21d6c4af
DN		 6690
6691 /* Mark as a memory operand only if it's not already known to be an
6692 offset expression. */
a724f0f4 6693 if (!intel_parser.in_offset)
21d6c4af 6694 intel_parser.is_mem = 1;
64a0c779
DN		 6695
6696 return 1;
64a0c779 6697
a724f0f4
JB		 6698 /* e11 register */
6699 case T_REG:
6700 {
6701 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6702
a724f0f4 6703 intel_match_token (T_REG);
64a0c779 6704
a724f0f4
JB		 6705 /* Check for segment change. */
6706 if (cur_token.code == ':')
6707 {
6708 if (!(reg->reg_type & (SReg2 | SReg3)))
6709 {
6710 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6711 return 0;
6712 }
6713 else if (i.seg[i.mem_operands])
6714 as_warn (_("Extra segment override ignored"));
6715 else
6716 {
6717 if (!intel_parser.in_offset)
6718 intel_parser.is_mem = 1;
6719 switch (reg->reg_num)
6720 {
6721 case 0:
6722 i.seg[i.mem_operands] = &es;
6723 break;
6724 case 1:
6725 i.seg[i.mem_operands] = &cs;
6726 break;
6727 case 2:
6728 i.seg[i.mem_operands] = &ss;
6729 break;
6730 case 3:
6731 i.seg[i.mem_operands] = &ds;
6732 break;
6733 case 4:
6734 i.seg[i.mem_operands] = &fs;
6735 break;
6736 case 5:
6737 i.seg[i.mem_operands] = &gs;
6738 break;
6739 }
6740 }
6741 }
64a0c779 6742
a724f0f4
JB		 6743 /* Not a segment register. Check for register scaling. */
6744 else if (cur_token.code == '*')
6745 {
6746 if (!intel_parser.in_bracket)
6747 {
6748 as_bad (_("Register scaling only allowed in memory operands"));
6749 return 0;
6750 }
64a0c779 6751
a724f0f4
JB		 6752 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6753 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6754 else if (i.index_reg)
6755 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6756
a724f0f4
JB		 6757 /* What follows must be a valid scale. */
6758 intel_match_token ('*');
6759 i.index_reg = reg;
6760 i.types[this_operand] |= BaseIndex;
64a0c779 6761
a724f0f4
JB		 6762 /* Set the scale after setting the register (otherwise,
6763 i386_scale will complain) */
6764 if (cur_token.code == '+' || cur_token.code == '-')
6765 {
6766 char *str, sign = cur_token.code;
6767 intel_match_token (cur_token.code);
6768 if (cur_token.code != T_CONST)
6769 {
6770 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6771 cur_token.str);
6772 return 0;
6773 }
6774 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6775 strcpy (str + 1, cur_token.str);
6776 *str = sign;
6777 if (!i386_scale (str))
6778 return 0;
6779 free (str);
6780 }
6781 else if (!i386_scale (cur_token.str))
64a0c779 6782 return 0;
a724f0f4
JB		 6783 intel_match_token (cur_token.code);
6784 }
64a0c779 6785
a724f0f4
JB		 6786 /* No scaling. If this is a memory operand, the register is either a
6787 base register (first occurrence) or an index register (second
6788 occurrence). */
7b0441f6 6789 else if (intel_parser.in_bracket)
a724f0f4 6790 {
64a0c779 6791
a724f0f4
JB		 6792 if (!i.base_reg)
6793 i.base_reg = reg;
6794 else if (!i.index_reg)
6795 i.index_reg = reg;
6796 else
6797 {
6798 as_bad (_("Too many register references in memory operand"));
6799 return 0;
6800 }
64a0c779 6801
a724f0f4
JB		 6802 i.types[this_operand] |= BaseIndex;
6803 }
4a1805b1 6804
4d1bb795
JB		 6805 /* It's neither base nor index. */
6806 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 6807 {
6808 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6809 i.op[this_operand].regs = reg;
6810 i.reg_operands++;
6811 }
6812 else
6813 {
6814 as_bad (_("Invalid use of register"));
6815 return 0;
6816 }
64a0c779 6817
a724f0f4
JB		 6818 /* Since registers are not part of the displacement string (except
6819 when we're parsing offset operands), we may need to remove any
6820 preceding '+' from the displacement string. */
6821 if (*intel_parser.disp != '\0'
6822 && !intel_parser.in_offset)
6823 {
6824 char *s = intel_parser.disp;
6825 s += strlen (s) - 1;
6826 if (*s == '+')
6827 *s = '\0';
6828 }
4a1805b1 6829
a724f0f4
JB		 6830 return 1;
6831 }
6832
6833 /* e11 BYTE
6834 | WORD
6835 | DWORD
6836 | FWORD
6837 | QWORD
6838 | TBYTE
6839 | OWORD
6840 | XMMWORD */
6841 case T_BYTE:
6842 case T_WORD:
6843 case T_DWORD:
6844 case T_FWORD:
6845 case T_QWORD:
6846 case T_TBYTE:
6847 case T_XMMWORD:
6848 intel_match_token (cur_token.code);
64a0c779 6849
a724f0f4
JB		 6850 if (cur_token.code == T_PTR)
6851 return 1;
6852
6853 /* It must have been an identifier. */
6854 intel_putback_token ();
6855 cur_token.code = T_ID;
6856 /* FALLTHRU */
6857
6858 /* e11 id
6859 | constant */
6860 case T_ID:
6861 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6862 {
6863 symbolS *symbolP;
6864
a724f0f4
JB		 6865 /* The identifier represents a memory reference only if it's not
6866 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6867 symbolP = symbol_find(cur_token.str);
6868 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6869 intel_parser.is_mem = 1;
6870 }
a724f0f4 6871 /* FALLTHRU */
64a0c779 6872
a724f0f4
JB		 6873 case T_CONST:
6874 case '-':
6875 case '+':
6876 {
6877 char *save_str, sign = 0;
64a0c779 6878
a724f0f4
JB		 6879 /* Allow constants that start with `+' or `-'. */
6880 if (cur_token.code == '-' || cur_token.code == '+')
6881 {
6882 sign = cur_token.code;
6883 intel_match_token (cur_token.code);
6884 if (cur_token.code != T_CONST)
6885 {
6886 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6887 cur_token.str);
6888 return 0;
6889 }
6890 }
64a0c779 6891
a724f0f4
JB		 6892 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6893 strcpy (save_str + !!sign, cur_token.str);
6894 if (sign)
6895 *save_str = sign;
64a0c779 6896
a724f0f4
JB		 6897 /* Get the next token to check for register scaling. */
6898 intel_match_token (cur_token.code);
64a0c779 6899
a724f0f4
JB		 6900 /* Check if this constant is a scaling factor for an index register. */
6901 if (cur_token.code == '*')
6902 {
6903 if (intel_match_token ('*') && cur_token.code == T_REG)
6904 {
6905 const reg_entry *reg = cur_token.reg;
6906
6907 if (!intel_parser.in_bracket)
6908 {
6909 as_bad (_("Register scaling only allowed in memory operands"));
6910 return 0;
6911 }
6912
6913 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6914 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6915 else if (i.index_reg)
6916 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6917
6918 /* The constant is followed by `* reg', so it must be
6919 a valid scale. */
6920 i.index_reg = reg;
6921 i.types[this_operand] |= BaseIndex;
6922
6923 /* Set the scale after setting the register (otherwise,
6924 i386_scale will complain) */
6925 if (!i386_scale (save_str))
64a0c779 6926 return 0;
a724f0f4
JB		 6927 intel_match_token (T_REG);
6928
6929 /* Since registers are not part of the displacement
6930 string, we may need to remove any preceding '+' from
6931 the displacement string. */
6932 if (*intel_parser.disp != '\0')
6933 {
6934 char *s = intel_parser.disp;
6935 s += strlen (s) - 1;
6936 if (*s == '+')
6937 *s = '\0';
6938 }
6939
6940 free (save_str);
6941
6942 return 1;
6943 }
64a0c779 6944
a724f0f4
JB		 6945 /* The constant was not used for register scaling. Since we have
6946 already consumed the token following `*' we now need to put it
6947 back in the stream. */
64a0c779 6948 intel_putback_token ();
a724f0f4 6949 }
64a0c779 6950
a724f0f4
JB		 6951 /* Add the constant to the displacement string. */
6952 strcat (intel_parser.disp, save_str);
6953 free (save_str);
64a0c779 6954
a724f0f4
JB		 6955 return 1;
6956 }
64a0c779
DN		 6957 }
6958
64a0c779
DN		 6959 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6960 return 0;
6961}
6962
64a0c779
DN		 6963/* Match the given token against cur_token. If they match, read the next
6964 token from the operand string. */
6965static int
6966intel_match_token (code)
e5cb08ac 6967 int code;
64a0c779
DN		 6968{
6969 if (cur_token.code == code)
6970 {
6971 intel_get_token ();
6972 return 1;
6973 }
6974 else
6975 {
0477af35 6976 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6977 return 0;
6978 }
6979}
6980
64a0c779
DN		 6981/* Read a new token from intel_parser.op_string and store it in cur_token. */
6982static void
6983intel_get_token ()
6984{
6985 char *end_op;
6986 const reg_entry *reg;
6987 struct intel_token new_token;
6988
6989 new_token.code = T_NIL;
6990 new_token.reg = NULL;
6991 new_token.str = NULL;
6992
4a1805b1 6993 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6994 cur_token to prev_token. */
6995 if (prev_token.str)
6996 free (prev_token.str);
6997
6998 prev_token = cur_token;
6999
7000 /* Skip whitespace. */
7001 while (is_space_char (*intel_parser.op_string))
7002 intel_parser.op_string++;
7003
7004 /* Return an empty token if we find nothing else on the line. */
7005 if (*intel_parser.op_string == '\0')
7006 {
7007 cur_token = new_token;
7008 return;
7009 }
7010
7011 /* The new token cannot be larger than the remainder of the operand
7012 string. */
a724f0f4 7013 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7014 new_token.str[0] = '\0';
7015
7016 if (strchr ("0123456789", *intel_parser.op_string))
7017 {
7018 char *p = new_token.str;
7019 char *q = intel_parser.op_string;
7020 new_token.code = T_CONST;
7021
7022 /* Allow any kind of identifier char to encompass floating point and
7023 hexadecimal numbers. */
7024 while (is_identifier_char (*q))
7025 *p++ = *q++;
7026 *p = '\0';
7027
7028 /* Recognize special symbol names [0-9][bf]. */
7029 if (strlen (intel_parser.op_string) == 2
4a1805b1 7030 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7031 || intel_parser.op_string[1] == 'f'))
7032 new_token.code = T_ID;
7033 }
7034
4d1bb795 7035 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7036 {
4d1bb795
JB		 7037 size_t len = end_op - intel_parser.op_string;
7038
64a0c779
DN		 7039 new_token.code = T_REG;
7040 new_token.reg = reg;
7041
4d1bb795
JB		 7042 memcpy (new_token.str, intel_parser.op_string, len);
7043 new_token.str[len] = '\0';
64a0c779
DN		 7044 }
7045
7046 else if (is_identifier_char (*intel_parser.op_string))
7047 {
7048 char *p = new_token.str;
7049 char *q = intel_parser.op_string;
7050
7051 /* A '.' or '$' followed by an identifier char is an identifier.
7052 Otherwise, it's operator '.' followed by an expression. */
7053 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7054 {
9306ca4a
JB		 7055 new_token.code = '.';
7056 new_token.str[0] = '.';
64a0c779
DN		 7057 new_token.str[1] = '\0';
7058 }
7059 else
7060 {
7061 while (is_identifier_char (*q) || *q == '@')
7062 *p++ = *q++;
7063 *p = '\0';
7064
9306ca4a
JB		 7065 if (strcasecmp (new_token.str, "NOT") == 0)
7066 new_token.code = '~';
7067
7068 else if (strcasecmp (new_token.str, "MOD") == 0)
7069 new_token.code = '%';
7070
7071 else if (strcasecmp (new_token.str, "AND") == 0)
7072 new_token.code = '&';
7073
7074 else if (strcasecmp (new_token.str, "OR") == 0)
7075 new_token.code = '|';
7076
7077 else if (strcasecmp (new_token.str, "XOR") == 0)
7078 new_token.code = '^';
7079
7080 else if (strcasecmp (new_token.str, "SHL") == 0)
7081 new_token.code = T_SHL;
7082
7083 else if (strcasecmp (new_token.str, "SHR") == 0)
7084 new_token.code = T_SHR;
7085
7086 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7087 new_token.code = T_BYTE;
7088
7089 else if (strcasecmp (new_token.str, "WORD") == 0)
7090 new_token.code = T_WORD;
7091
7092 else if (strcasecmp (new_token.str, "DWORD") == 0)
7093 new_token.code = T_DWORD;
7094
9306ca4a
JB		 7095 else if (strcasecmp (new_token.str, "FWORD") == 0)
7096 new_token.code = T_FWORD;
7097
64a0c779
DN		 7098 else if (strcasecmp (new_token.str, "QWORD") == 0)
7099 new_token.code = T_QWORD;
7100
9306ca4a
JB		 7101 else if (strcasecmp (new_token.str, "TBYTE") == 0
7102 /* XXX remove (gcc still uses it) */
7103 || strcasecmp (new_token.str, "XWORD") == 0)
7104 new_token.code = T_TBYTE;
7105
7106 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7107 || strcasecmp (new_token.str, "OWORD") == 0)
7108 new_token.code = T_XMMWORD;
64a0c779
DN		 7109
7110 else if (strcasecmp (new_token.str, "PTR") == 0)
7111 new_token.code = T_PTR;
7112
7113 else if (strcasecmp (new_token.str, "SHORT") == 0)
7114 new_token.code = T_SHORT;
7115
7116 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7117 {
7118 new_token.code = T_OFFSET;
7119
7120 /* ??? This is not mentioned in the MASM grammar but gcc
7121 makes use of it with -mintel-syntax. OFFSET may be
7122 followed by FLAT: */
7123 if (strncasecmp (q, " FLAT:", 6) == 0)
7124 strcat (new_token.str, " FLAT:");
7125 }
7126
7127 /* ??? This is not mentioned in the MASM grammar. */
7128 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7129 {
7130 new_token.code = T_OFFSET;
7131 if (*q == ':')
7132 strcat (new_token.str, ":");
7133 else
7134 as_bad (_("`:' expected"));
7135 }
64a0c779
DN		 7136
7137 else
7138 new_token.code = T_ID;
7139 }
7140 }
7141
9306ca4a
JB		 7142 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7143 {
7144 new_token.code = *intel_parser.op_string;
7145 new_token.str[0] = *intel_parser.op_string;
7146 new_token.str[1] = '\0';
7147 }
7148
7149 else if (strchr ("<>", *intel_parser.op_string)
7150 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7151 {
7152 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7153 new_token.str[0] = *intel_parser.op_string;
7154 new_token.str[1] = *intel_parser.op_string;
7155 new_token.str[2] = '\0';
7156 }
7157
64a0c779 7158 else
0477af35 7159 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7160
7161 intel_parser.op_string += strlen (new_token.str);
7162 cur_token = new_token;
7163}
7164
64a0c779
DN		 7165/* Put cur_token back into the token stream and make cur_token point to
7166 prev_token. */
7167static void
7168intel_putback_token ()
7169{
a724f0f4
JB		 7170 if (cur_token.code != T_NIL)
7171 {
7172 intel_parser.op_string -= strlen (cur_token.str);
7173 free (cur_token.str);
7174 }
64a0c779 7175 cur_token = prev_token;
4a1805b1 7176
64a0c779
DN		 7177 /* Forget prev_token. */
7178 prev_token.code = T_NIL;
7179 prev_token.reg = NULL;
7180 prev_token.str = NULL;
7181}
54cfded0 7182
a4447b93 7183int
1df69f4f 7184tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7185{
7186 unsigned int regnum;
7187 unsigned int regnames_count;
089dfecd 7188 static const char *const regnames_32[] =
54cfded0 7189 {
a4447b93
RH		 7190 "eax", "ecx", "edx", "ebx",
7191 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7192 "eip", "eflags", NULL,
7193 "st0", "st1", "st2", "st3",
7194 "st4", "st5", "st6", "st7",
7195 NULL, NULL,
7196 "xmm0", "xmm1", "xmm2", "xmm3",
7197 "xmm4", "xmm5", "xmm6", "xmm7",
7198 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7199 "mm4", "mm5", "mm6", "mm7",
7200 "fcw", "fsw", "mxcsr",
7201 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7202 "tr", "ldtr"
54cfded0 7203 };
089dfecd 7204 static const char *const regnames_64[] =
54cfded0 7205 {
089dfecd
JB		 7206 "rax", "rdx", "rcx", "rbx",
7207 "rsi", "rdi", "rbp", "rsp",
7208 "r8", "r9", "r10", "r11",
54cfded0 7209 "r12", "r13", "r14", "r15",
089dfecd
JB		 7210 "rip",
7211 "xmm0", "xmm1", "xmm2", "xmm3",
7212 "xmm4", "xmm5", "xmm6", "xmm7",
7213 "xmm8", "xmm9", "xmm10", "xmm11",
7214 "xmm12", "xmm13", "xmm14", "xmm15",
7215 "st0", "st1", "st2", "st3",
7216 "st4", "st5", "st6", "st7",
7217 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7218 "mm4", "mm5", "mm6", "mm7",
7219 "rflags",
7220 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7221 "fs.base", "gs.base", NULL, NULL,
7222 "tr", "ldtr",
7223 "mxcsr", "fcw", "fsw"
54cfded0 7224 };
089dfecd 7225 const char *const *regnames;
54cfded0
AM		 7226
7227 if (flag_code == CODE_64BIT)
7228 {
7229 regnames = regnames_64;
0cea6190 7230 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7231 }
7232 else
7233 {
7234 regnames = regnames_32;
0cea6190 7235 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7236 }
7237
7238 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7239 if (regnames[regnum] != NULL
7240 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7241 return regnum;
7242
54cfded0
AM		 7243 return -1;
7244}
7245
7246void
7247tc_x86_frame_initial_instructions (void)
7248{
a4447b93
RH		 7249 static unsigned int sp_regno;
7250
7251 if (!sp_regno)
7252 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7253 ? "rsp" : "esp");
7254
7255 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7256 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7257}
d2b2c203
DJ		 7258
7259int
7260i386_elf_section_type (const char *str, size_t len)
7261{
7262 if (flag_code == CODE_64BIT
7263 && len == sizeof ("unwind") - 1
7264 && strncmp (str, "unwind", 6) == 0)
7265 return SHT_X86_64_UNWIND;
7266
7267 return -1;
7268}
bb41ade5
AM		 7269
7270#ifdef TE_PE
7271void
7272tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7273{
7274 expressionS expr;
7275
7276 expr.X_op = O_secrel;
7277 expr.X_add_symbol = symbol;
7278 expr.X_add_number = 0;
7279 emit_expr (&expr, size);
7280}
7281#endif
3b22753a
L		 7282
7283#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7284/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7285
7286int
7287x86_64_section_letter (int letter, char **ptr_msg)
7288{
7289 if (flag_code == CODE_64BIT)
7290 {
7291 if (letter == 'l')
7292 return SHF_X86_64_LARGE;
7293
7294 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7295 }
3b22753a 7296 else
64e74474 7297 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7298 return -1;
7299}
7300
7301int
7302x86_64_section_word (char *str, size_t len)
7303{
7304 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7305 return SHF_X86_64_LARGE;
7306
7307 return -1;
7308}
7309
7310static void
7311handle_large_common (int small ATTRIBUTE_UNUSED)
7312{
7313 if (flag_code != CODE_64BIT)
7314 {
7315 s_comm_internal (0, elf_common_parse);
7316 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7317 }
7318 else
7319 {
7320 static segT lbss_section;
7321 asection *saved_com_section_ptr = elf_com_section_ptr;
7322 asection *saved_bss_section = bss_section;
7323
7324 if (lbss_section == NULL)
7325 {
7326 flagword applicable;
7327 segT seg = now_seg;
7328 subsegT subseg = now_subseg;
7329
7330 /* The .lbss section is for local .largecomm symbols. */
7331 lbss_section = subseg_new (".lbss", 0);
7332 applicable = bfd_applicable_section_flags (stdoutput);
7333 bfd_set_section_flags (stdoutput, lbss_section,
7334 applicable & SEC_ALLOC);
7335 seg_info (lbss_section)->bss = 1;
7336
7337 subseg_set (seg, subseg);
7338 }
7339
7340 elf_com_section_ptr = &_bfd_elf_large_com_section;
7341 bss_section = lbss_section;
7342
7343 s_comm_internal (0, elf_common_parse);
7344
7345 elf_com_section_ptr = saved_com_section_ptr;
7346 bss_section = saved_bss_section;
7347 }
7348}
7349#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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