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Replace have_hle with hle_prefix
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579
TG		 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
4 2012
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d 68#define REP_PREFIX 4
42164a71 69#define HLE_PREFIX REP_PREFIX
c32fa91d
L		 70#define LOCK_PREFIX 5
71#define REX_PREFIX 6 /* must come last. */
72#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 73
74/* we define the syntax here (modulo base,index,scale syntax) */
75#define REGISTER_PREFIX '%'
76#define IMMEDIATE_PREFIX '$'
77#define ABSOLUTE_PREFIX '*'
78
79/* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81#define WORD_MNEM_SUFFIX 'w'
82#define BYTE_MNEM_SUFFIX 'b'
83#define SHORT_MNEM_SUFFIX 's'
84#define LONG_MNEM_SUFFIX 'l'
85#define QWORD_MNEM_SUFFIX 'q'
86#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 87#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 88/* Intel Syntax. Use a non-ascii letter since since it never appears
89 in instructions. */
90#define LONG_DOUBLE_MNEM_SUFFIX '\1'
91
92#define END_OF_INSN '\0'
93
94/*
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
99 END.
100 */
101typedef struct
102{
d3ce72d0
NC		 103 const insn_template *start;
104 const insn_template *end;
6305a203
L		 105}
106templates;
107
108/* 386 operand encoding bytes: see 386 book for details of this. */
109typedef struct
110{
111 unsigned int regmem; /* codes register or memory operand */
112 unsigned int reg; /* codes register operand (or extended opcode) */
113 unsigned int mode; /* how to interpret regmem & reg */
114}
115modrm_byte;
116
117/* x86-64 extension prefix. */
118typedef int rex_byte;
119
6305a203
L		 120/* 386 opcode byte to code indirect addressing. */
121typedef struct
122{
123 unsigned base;
124 unsigned index;
125 unsigned scale;
126}
127sib_byte;
128
6305a203
L		 129/* x86 arch names, types and features */
130typedef struct
131{
132 const char *name; /* arch name */
8a2c8fef 133 unsigned int len; /* arch string length */
6305a203
L		 134 enum processor_type type; /* arch type */
135 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 136 unsigned int skip; /* show_arch should skip this. */
22109423 137 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 138}
139arch_entry;
140
78f12dd3 141static void update_code_flag (int, int);
e3bb37b5
L		 142static void set_code_flag (int);
143static void set_16bit_gcc_code_flag (int);
144static void set_intel_syntax (int);
1efbbeb4 145static void set_intel_mnemonic (int);
db51cc60 146static void set_allow_index_reg (int);
7bab8ab5 147static void set_check (int);
e3bb37b5 148static void set_cpu_arch (int);
6482c264 149#ifdef TE_PE
e3bb37b5 150static void pe_directive_secrel (int);
6482c264 151#endif
e3bb37b5
L		 152static void signed_cons (int);
153static char *output_invalid (int c);
ee86248c
JB		 154static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
155 const char *);
156static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
157 const char *);
a7619375 158static int i386_att_operand (char *);
e3bb37b5 159static int i386_intel_operand (char *, int);
ee86248c
JB		 160static int i386_intel_simplify (expressionS *);
161static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 162static const reg_entry *parse_register (char *, char **);
163static char *parse_insn (char *, char *);
164static char *parse_operands (char *, const char *);
165static void swap_operands (void);
4d456e3d 166static void swap_2_operands (int, int);
e3bb37b5
L		 167static void optimize_imm (void);
168static void optimize_disp (void);
d3ce72d0 169static const insn_template *match_template (void);
e3bb37b5
L		 170static int check_string (void);
171static int process_suffix (void);
172static int check_byte_reg (void);
173static int check_long_reg (void);
174static int check_qword_reg (void);
175static int check_word_reg (void);
176static int finalize_imm (void);
177static int process_operands (void);
178static const seg_entry *build_modrm_byte (void);
179static void output_insn (void);
180static void output_imm (fragS *, offsetT);
181static void output_disp (fragS *, offsetT);
29b0f896 182#ifndef I386COFF
e3bb37b5 183static void s_bss (int);
252b5132 184#endif
17d4e2a2
L		 185#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186static void handle_large_common (int small ATTRIBUTE_UNUSED);
187#endif
252b5132 188
a847613f 189static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 190
c0f3af97
L		 191/* VEX prefix. */
192typedef struct
193{
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes[3];
196 unsigned int length;
197 /* Destination or source register specifier. */
198 const reg_entry *register_specifier;
199} vex_prefix;
200
252b5132 201/* 'md_assemble ()' gathers together information and puts it into a
47926f60 202 i386_insn. */
252b5132 203
520dc8e8
AM		 204union i386_op
205 {
206 expressionS *disps;
207 expressionS *imms;
208 const reg_entry *regs;
209 };
210
a65babc9
L		 211enum i386_error
212 {
86e026a4 213 operand_size_mismatch,
a65babc9
L		 214 operand_type_mismatch,
215 register_type_mismatch,
216 number_of_operands_mismatch,
217 invalid_instruction_suffix,
218 bad_imm4,
219 old_gcc_only,
220 unsupported_with_intel_mnemonic,
221 unsupported_syntax,
6c30d220
L		 222 unsupported,
223 invalid_vsib_address,
7bab8ab5 224 invalid_vector_register_set,
6c30d220 225 unsupported_vector_index_register
a65babc9
L		 226 };
227
252b5132
RH		 228struct _i386_insn
229 {
47926f60 230 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 231 insn_template tm;
252b5132 232
7d5e4556
L		 233 /* SUFFIX holds the instruction size suffix for byte, word, dword
234 or qword, if given. */
252b5132
RH		 235 char suffix;
236
47926f60 237 /* OPERANDS gives the number of given operands. */
252b5132
RH		 238 unsigned int operands;
239
240 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
241 of given register, displacement, memory operands and immediate
47926f60 242 operands. */
252b5132
RH		 243 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
244
245 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 246 use OP[i] for the corresponding operand. */
40fb9820 247 i386_operand_type types[MAX_OPERANDS];
252b5132 248
520dc8e8
AM		 249 /* Displacement expression, immediate expression, or register for each
250 operand. */
251 union i386_op op[MAX_OPERANDS];
252b5132 252
3e73aa7c
JH		 253 /* Flags for operands. */
254 unsigned int flags[MAX_OPERANDS];
255#define Operand_PCrel 1
256
252b5132 257 /* Relocation type for operand */
f86103b7 258 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 259
252b5132
RH		 260 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
261 the base index byte below. */
262 const reg_entry *base_reg;
263 const reg_entry *index_reg;
264 unsigned int log2_scale_factor;
265
266 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 267 explicit segment overrides are given. */
ce8a8b2f 268 const seg_entry *seg[2];
252b5132
RH		 269
270 /* PREFIX holds all the given prefix opcodes (usually null).
271 PREFIXES is the number of prefix opcodes. */
272 unsigned int prefixes;
273 unsigned char prefix[MAX_PREFIXES];
274
275 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 276 addressing modes of this insn are encoded. */
252b5132 277 modrm_byte rm;
3e73aa7c 278 rex_byte rex;
252b5132 279 sib_byte sib;
c0f3af97 280 vex_prefix vex;
b6169b20
L		 281
282 /* Swap operand in encoding. */
4473e004 283 unsigned int swap_operand;
891edac4 284
a501d77e
L		 285 /* Prefer 8bit or 32bit displacement in encoding. */
286 enum
287 {
288 disp_encoding_default = 0,
289 disp_encoding_8bit,
290 disp_encoding_32bit
291 } disp_encoding;
f8a5c266 292
d5de92cf
L		 293 /* REP prefix. */
294 const char *rep_prefix;
295
165de32a
L		 296 /* HLE prefix. */
297 const char *hle_prefix;
42164a71 298
891edac4 299 /* Error message. */
a65babc9 300 enum i386_error error;
252b5132
RH		 301 };
302
303typedef struct _i386_insn i386_insn;
304
305/* List of chars besides those in app.c:symbol_chars that can start an
306 operand. Used to prevent the scrubber eating vital white-space. */
32137342 307const char extra_symbol_chars[] = "*%-(["
252b5132 308#ifdef LEX_AT
32137342
NC		 309 "@"
310#endif
311#ifdef LEX_QM
312 "?"
252b5132 313#endif
32137342 314 ;
252b5132 315
29b0f896
AM		 316#if (defined (TE_I386AIX) \
317 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 318 && !defined (TE_GNU) \
29b0f896 319 && !defined (TE_LINUX) \
8d63c93e
RM		 320 && !defined (TE_NACL) \
321 && !defined (TE_NETWARE) \
29b0f896 322 && !defined (TE_FreeBSD) \
5b806d27 323 && !defined (TE_DragonFly) \
29b0f896 324 && !defined (TE_NetBSD)))
252b5132 325/* This array holds the chars that always start a comment. If the
b3b91714
AM		 326 pre-processor is disabled, these aren't very useful. The option
327 --divide will remove '/' from this list. */
328const char *i386_comment_chars = "#/";
329#define SVR4_COMMENT_CHARS 1
252b5132 330#define PREFIX_SEPARATOR '\\'
252b5132 331
b3b91714
AM		 332#else
333const char *i386_comment_chars = "#";
334#define PREFIX_SEPARATOR '/'
335#endif
336
252b5132
RH		 337/* This array holds the chars that only start a comment at the beginning of
338 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 339 .line and .file directives will appear in the pre-processed output.
340 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 341 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 342 #NO_APP at the beginning of its output.
343 Also note that comments started like this one will always work if
252b5132 344 '/' isn't otherwise defined. */
b3b91714 345const char line_comment_chars[] = "#/";
252b5132 346
63a0b638 347const char line_separator_chars[] = ";";
252b5132 348
ce8a8b2f
AM		 349/* Chars that can be used to separate mant from exp in floating point
350 nums. */
252b5132
RH		 351const char EXP_CHARS[] = "eE";
352
ce8a8b2f
AM		 353/* Chars that mean this number is a floating point constant
354 As in 0f12.456
355 or 0d1.2345e12. */
252b5132
RH		 356const char FLT_CHARS[] = "fFdDxX";
357
ce8a8b2f 358/* Tables for lexical analysis. */
252b5132
RH		 359static char mnemonic_chars[256];
360static char register_chars[256];
361static char operand_chars[256];
362static char identifier_chars[256];
363static char digit_chars[256];
364
ce8a8b2f 365/* Lexical macros. */
252b5132
RH		 366#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
367#define is_operand_char(x) (operand_chars[(unsigned char) x])
368#define is_register_char(x) (register_chars[(unsigned char) x])
369#define is_space_char(x) ((x) == ' ')
370#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
371#define is_digit_char(x) (digit_chars[(unsigned char) x])
372
0234cb7c 373/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 374static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
375
376/* md_assemble() always leaves the strings it's passed unaltered. To
377 effect this we maintain a stack of saved characters that we've smashed
378 with '\0's (indicating end of strings for various sub-fields of the
47926f60 379 assembler instruction). */
252b5132 380static char save_stack[32];
ce8a8b2f 381static char *save_stack_p;
252b5132
RH		 382#define END_STRING_AND_SAVE(s) \
383 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
384#define RESTORE_END_STRING(s) \
385 do { *(s) = *--save_stack_p; } while (0)
386
47926f60 387/* The instruction we're assembling. */
252b5132
RH		 388static i386_insn i;
389
390/* Possible templates for current insn. */
391static const templates *current_templates;
392
31b2323c
L		 393/* Per instruction expressionS buffers: max displacements & immediates. */
394static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
395static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 396
47926f60 397/* Current operand we are working on. */
ee86248c 398static int this_operand = -1;
252b5132 399
3e73aa7c
JH		 400/* We support four different modes. FLAG_CODE variable is used to distinguish
401 these. */
402
403enum flag_code {
404 CODE_32BIT,
405 CODE_16BIT,
406 CODE_64BIT };
407
408static enum flag_code flag_code;
4fa24527 409static unsigned int object_64bit;
862be3fb 410static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 411static int use_rela_relocations = 0;
412
7af8ed2d
NC		 413#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
414 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
415 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
416
351f65ca
L		 417/* The ELF ABI to use. */
418enum x86_elf_abi
419{
420 I386_ABI,
7f56bc95
L		 421 X86_64_ABI,
422 X86_64_X32_ABI
351f65ca
L		 423};
424
425static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 426#endif
351f65ca 427
3e73aa7c 428/* The names used to print error messages. */
b77a7acd 429static const char *flag_code_names[] =
3e73aa7c
JH		 430 {
431 "32",
432 "16",
433 "64"
434 };
252b5132 435
47926f60
KH		 436/* 1 for intel syntax,
437 0 if att syntax. */
438static int intel_syntax = 0;
252b5132 439
1efbbeb4
L		 440/* 1 for intel mnemonic,
441 0 if att mnemonic. */
442static int intel_mnemonic = !SYSV386_COMPAT;
443
5209009a 444/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 445static int old_gcc = OLDGCC_COMPAT;
446
a60de03c
JB		 447/* 1 if pseudo registers are permitted. */
448static int allow_pseudo_reg = 0;
449
47926f60
KH		 450/* 1 if register prefix % not required. */
451static int allow_naked_reg = 0;
252b5132 452
ba104c83 453/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 454static int allow_index_reg = 0;
455
7bab8ab5 456static enum check_kind
daf50ae7 457 {
7bab8ab5
JB		 458 check_none = 0,
459 check_warning,
460 check_error
daf50ae7 461 }
7bab8ab5 462sse_check, operand_check = check_warning;
daf50ae7 463
2ca3ace5
L		 464/* Register prefix used for error message. */
465static const char *register_prefix = "%";
466
47926f60
KH		 467/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
468 leave, push, and pop instructions so that gcc has the same stack
469 frame as in 32 bit mode. */
470static char stackop_size = '\0';
eecb386c 471
12b55ccc
L		 472/* Non-zero to optimize code alignment. */
473int optimize_align_code = 1;
474
47926f60
KH		 475/* Non-zero to quieten some warnings. */
476static int quiet_warnings = 0;
a38cf1db 477
47926f60
KH		 478/* CPU name. */
479static const char *cpu_arch_name = NULL;
6305a203 480static char *cpu_sub_arch_name = NULL;
a38cf1db 481
47926f60 482/* CPU feature flags. */
40fb9820
L		 483static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
484
ccc9c027
L		 485/* If we have selected a cpu we are generating instructions for. */
486static int cpu_arch_tune_set = 0;
487
9103f4f4 488/* Cpu we are generating instructions for. */
fbf3f584 489enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 490
491/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 492static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 493
ccc9c027 494/* CPU instruction set architecture used. */
fbf3f584 495enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 496
9103f4f4 497/* CPU feature flags of instruction set architecture used. */
fbf3f584 498i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 499
fddf5b5b
AM		 500/* If set, conditional jumps are not automatically promoted to handle
501 larger than a byte offset. */
502static unsigned int no_cond_jump_promotion = 0;
503
c0f3af97
L		 504/* Encode SSE instructions with VEX prefix. */
505static unsigned int sse2avx;
506
539f890d
L		 507/* Encode scalar AVX instructions with specific vector length. */
508static enum
509 {
510 vex128 = 0,
511 vex256
512 } avxscalar;
513
29b0f896 514/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 515static symbolS *GOT_symbol;
29b0f896 516
a4447b93
RH		 517/* The dwarf2 return column, adjusted for 32 or 64 bit. */
518unsigned int x86_dwarf2_return_column;
519
520/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
521int x86_cie_data_alignment;
522
252b5132 523/* Interface to relax_segment.
fddf5b5b
AM		 524 There are 3 major relax states for 386 jump insns because the
525 different types of jumps add different sizes to frags when we're
526 figuring out what sort of jump to choose to reach a given label. */
252b5132 527
47926f60 528/* Types. */
93c2a809
AM		 529#define UNCOND_JUMP 0
530#define COND_JUMP 1
531#define COND_JUMP86 2
fddf5b5b 532
47926f60 533/* Sizes. */
252b5132
RH		 534#define CODE16 1
535#define SMALL 0
29b0f896 536#define SMALL16 (SMALL | CODE16)
252b5132 537#define BIG 2
29b0f896 538#define BIG16 (BIG | CODE16)
252b5132
RH		 539
540#ifndef INLINE
541#ifdef __GNUC__
542#define INLINE __inline__
543#else
544#define INLINE
545#endif
546#endif
547
fddf5b5b
AM		 548#define ENCODE_RELAX_STATE(type, size) \
549 ((relax_substateT) (((type) << 2) | (size)))
550#define TYPE_FROM_RELAX_STATE(s) \
551 ((s) >> 2)
552#define DISP_SIZE_FROM_RELAX_STATE(s) \
553 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 554
555/* This table is used by relax_frag to promote short jumps to long
556 ones where necessary. SMALL (short) jumps may be promoted to BIG
557 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
558 don't allow a short jump in a 32 bit code segment to be promoted to
559 a 16 bit offset jump because it's slower (requires data size
560 prefix), and doesn't work, unless the destination is in the bottom
561 64k of the code segment (The top 16 bits of eip are zeroed). */
562
563const relax_typeS md_relax_table[] =
564{
24eab124
AM		 565 /* The fields are:
566 1) most positive reach of this state,
567 2) most negative reach of this state,
93c2a809 568 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 569 4) which index into the table to try if we can't fit into this one. */
252b5132 570
fddf5b5b 571 /* UNCOND_JUMP states. */
93c2a809
AM		 572 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
573 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
574 /* dword jmp adds 4 bytes to frag:
575 0 extra opcode bytes, 4 displacement bytes. */
252b5132 576 {0, 0, 4, 0},
93c2a809
AM		 577 /* word jmp adds 2 byte2 to frag:
578 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 579 {0, 0, 2, 0},
580
93c2a809
AM		 581 /* COND_JUMP states. */
582 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
583 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
584 /* dword conditionals adds 5 bytes to frag:
585 1 extra opcode byte, 4 displacement bytes. */
586 {0, 0, 5, 0},
fddf5b5b 587 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 588 1 extra opcode byte, 2 displacement bytes. */
589 {0, 0, 3, 0},
590
591 /* COND_JUMP86 states. */
592 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
593 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
594 /* dword conditionals adds 5 bytes to frag:
595 1 extra opcode byte, 4 displacement bytes. */
596 {0, 0, 5, 0},
597 /* word conditionals add 4 bytes to frag:
598 1 displacement byte and a 3 byte long branch insn. */
599 {0, 0, 4, 0}
252b5132
RH		 600};
601
9103f4f4
L		 602static const arch_entry cpu_arch[] =
603{
89507696
JB		 604 /* Do not replace the first two entries - i386_target_format()
605 relies on them being there in this order. */
8a2c8fef 606 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 607 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 609 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 611 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 613 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 615 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 617 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 619 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 621 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 623 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 625 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 627 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 629 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 630 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 631 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 632 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 633 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 634 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 635 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 636 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 637 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 639 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 640 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 641 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 642 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 643 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 644 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 645 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 646 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 647 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 648 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 649 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 650 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
651 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 652 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 653 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 654 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 655 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 656 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 657 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 658 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 659 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 660 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 661 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 662 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 663 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 664 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 665 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 666 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 667 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 668 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 669 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 670 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
671 CPU_BDVER3_FLAGS, 0, 0 },
7b458c12
L		 672 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
673 CPU_BTVER1_FLAGS, 0, 0 },
674 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
675 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 676 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 677 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 678 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 679 CPU_287_FLAGS, 0, 0 },
8a2c8fef 680 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 681 CPU_387_FLAGS, 0, 0 },
8a2c8fef 682 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 683 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 684 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 685 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 686 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 687 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 688 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 689 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 690 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 691 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 692 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 693 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 694 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 695 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 696 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 697 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 698 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 699 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 700 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 701 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 702 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 703 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 704 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 705 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 706 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
707 CPU_AVX2_FLAGS, 0, 0 },
8a2c8fef 708 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 709 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 710 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 711 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 712 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
713 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 715 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 716 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 717 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 718 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 719 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 721 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 722 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 723 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 725 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 726 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 727 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 728 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 729 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 730 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 731 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 732 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
733 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 735 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 737 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 739 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 741 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 743 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 744 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
745 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 747 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 748 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
749 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 750 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
751 CPU_HLE_FLAGS, 0, 0 },
752 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
753 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 754 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
755 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 756 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 757 CPU_CLFLUSH_FLAGS, 0, 0 },
758 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
759 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 760 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 761 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 762 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 763 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 765 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 766 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 767 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 768 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 769 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 770 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 771 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 772 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 773 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 774 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 775 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 776 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 777 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 778 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
779 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 780 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
781 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 782 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
783 CPU_ADX_FLAGS, 0, 0 },
784 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
785 CPU_RDSEED_FLAGS, 0, 0 },
786 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
787 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 788 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
789 CPU_SMAP_FLAGS, 0, 0 },
e413e4e9
AM		 790};
791
704209c0 792#ifdef I386COFF
a6c24e68
NC		 793/* Like s_lcomm_internal in gas/read.c but the alignment string
794 is allowed to be optional. */
795
796static symbolS *
797pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
798{
799 addressT align = 0;
800
801 SKIP_WHITESPACE ();
802
7ab9ffdd 803 if (needs_align
a6c24e68
NC		 804 && *input_line_pointer == ',')
805 {
806 align = parse_align (needs_align - 1);
7ab9ffdd 807
a6c24e68
NC		 808 if (align == (addressT) -1)
809 return NULL;
810 }
811 else
812 {
813 if (size >= 8)
814 align = 3;
815 else if (size >= 4)
816 align = 2;
817 else if (size >= 2)
818 align = 1;
819 else
820 align = 0;
821 }
822
823 bss_alloc (symbolP, size, align);
824 return symbolP;
825}
826
704209c0 827static void
a6c24e68
NC		 828pe_lcomm (int needs_align)
829{
830 s_comm_internal (needs_align * 2, pe_lcomm_internal);
831}
704209c0 832#endif
a6c24e68 833
29b0f896
AM		 834const pseudo_typeS md_pseudo_table[] =
835{
836#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
837 {"align", s_align_bytes, 0},
838#else
839 {"align", s_align_ptwo, 0},
840#endif
841 {"arch", set_cpu_arch, 0},
842#ifndef I386COFF
843 {"bss", s_bss, 0},
a6c24e68
NC		 844#else
845 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 846#endif
847 {"ffloat", float_cons, 'f'},
848 {"dfloat", float_cons, 'd'},
849 {"tfloat", float_cons, 'x'},
850 {"value", cons, 2},
d182319b 851 {"slong", signed_cons, 4},
29b0f896
AM		 852 {"noopt", s_ignore, 0},
853 {"optim", s_ignore, 0},
854 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
855 {"code16", set_code_flag, CODE_16BIT},
856 {"code32", set_code_flag, CODE_32BIT},
857 {"code64", set_code_flag, CODE_64BIT},
858 {"intel_syntax", set_intel_syntax, 1},
859 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 860 {"intel_mnemonic", set_intel_mnemonic, 1},
861 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 862 {"allow_index_reg", set_allow_index_reg, 1},
863 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 864 {"sse_check", set_check, 0},
865 {"operand_check", set_check, 1},
3b22753a
L		 866#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
867 {"largecomm", handle_large_common, 0},
07a53e5c 868#else
e3bb37b5 869 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 870 {"loc", dwarf2_directive_loc, 0},
871 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 872#endif
6482c264
NC		 873#ifdef TE_PE
874 {"secrel32", pe_directive_secrel, 0},
875#endif
29b0f896
AM		 876 {0, 0, 0}
877};
878
879/* For interface with expression (). */
880extern char *input_line_pointer;
881
882/* Hash table for instruction mnemonic lookup. */
883static struct hash_control *op_hash;
884
885/* Hash table for register lookup. */
886static struct hash_control *reg_hash;
887\f
252b5132 888void
e3bb37b5 889i386_align_code (fragS *fragP, int count)
252b5132 890{
ce8a8b2f
AM		 891 /* Various efficient no-op patterns for aligning code labels.
892 Note: Don't try to assemble the instructions in the comments.
893 0L and 0w are not legal. */
252b5132
RH		 894 static const char f32_1[] =
895 {0x90}; /* nop */
896 static const char f32_2[] =
ccc9c027 897 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 898 static const char f32_3[] =
899 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
900 static const char f32_4[] =
901 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
902 static const char f32_5[] =
903 {0x90, /* nop */
904 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
905 static const char f32_6[] =
906 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
907 static const char f32_7[] =
908 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
909 static const char f32_8[] =
910 {0x90, /* nop */
911 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
912 static const char f32_9[] =
913 {0x89,0xf6, /* movl %esi,%esi */
914 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
915 static const char f32_10[] =
916 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
917 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
918 static const char f32_11[] =
919 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
920 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
921 static const char f32_12[] =
922 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
923 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
924 static const char f32_13[] =
925 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
926 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
927 static const char f32_14[] =
928 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
929 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 930 static const char f16_3[] =
931 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 932 static const char f16_4[] =
933 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
934 static const char f16_5[] =
935 {0x90, /* nop */
936 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
937 static const char f16_6[] =
938 {0x89,0xf6, /* mov %si,%si */
939 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
940 static const char f16_7[] =
941 {0x8d,0x74,0x00, /* lea 0(%si),%si */
942 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
943 static const char f16_8[] =
944 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
945 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 946 static const char jump_31[] =
947 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
948 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
949 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
950 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 951 static const char *const f32_patt[] = {
952 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 953 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 954 };
955 static const char *const f16_patt[] = {
76bc74dc 956 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 957 };
ccc9c027
L		 958 /* nopl (%[re]ax) */
959 static const char alt_3[] =
960 {0x0f,0x1f,0x00};
961 /* nopl 0(%[re]ax) */
962 static const char alt_4[] =
963 {0x0f,0x1f,0x40,0x00};
964 /* nopl 0(%[re]ax,%[re]ax,1) */
965 static const char alt_5[] =
966 {0x0f,0x1f,0x44,0x00,0x00};
967 /* nopw 0(%[re]ax,%[re]ax,1) */
968 static const char alt_6[] =
969 {0x66,0x0f,0x1f,0x44,0x00,0x00};
970 /* nopl 0L(%[re]ax) */
971 static const char alt_7[] =
972 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
973 /* nopl 0L(%[re]ax,%[re]ax,1) */
974 static const char alt_8[] =
975 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
976 /* nopw 0L(%[re]ax,%[re]ax,1) */
977 static const char alt_9[] =
978 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
979 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
980 static const char alt_10[] =
981 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
982 /* data16
983 nopw %cs:0L(%[re]ax,%[re]ax,1) */
984 static const char alt_long_11[] =
985 {0x66,
986 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
987 /* data16
988 data16
989 nopw %cs:0L(%[re]ax,%[re]ax,1) */
990 static const char alt_long_12[] =
991 {0x66,
992 0x66,
993 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
994 /* data16
995 data16
996 data16
997 nopw %cs:0L(%[re]ax,%[re]ax,1) */
998 static const char alt_long_13[] =
999 {0x66,
1000 0x66,
1001 0x66,
1002 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1003 /* data16
1004 data16
1005 data16
1006 data16
1007 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1008 static const char alt_long_14[] =
1009 {0x66,
1010 0x66,
1011 0x66,
1012 0x66,
1013 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1014 /* data16
1015 data16
1016 data16
1017 data16
1018 data16
1019 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1020 static const char alt_long_15[] =
1021 {0x66,
1022 0x66,
1023 0x66,
1024 0x66,
1025 0x66,
1026 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1027 /* nopl 0(%[re]ax,%[re]ax,1)
1028 nopw 0(%[re]ax,%[re]ax,1) */
1029 static const char alt_short_11[] =
1030 {0x0f,0x1f,0x44,0x00,0x00,
1031 0x66,0x0f,0x1f,0x44,0x00,0x00};
1032 /* nopw 0(%[re]ax,%[re]ax,1)
1033 nopw 0(%[re]ax,%[re]ax,1) */
1034 static const char alt_short_12[] =
1035 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1036 0x66,0x0f,0x1f,0x44,0x00,0x00};
1037 /* nopw 0(%[re]ax,%[re]ax,1)
1038 nopl 0L(%[re]ax) */
1039 static const char alt_short_13[] =
1040 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1041 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1042 /* nopl 0L(%[re]ax)
1043 nopl 0L(%[re]ax) */
1044 static const char alt_short_14[] =
1045 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1046 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1047 /* nopl 0L(%[re]ax)
1048 nopl 0L(%[re]ax,%[re]ax,1) */
1049 static const char alt_short_15[] =
1050 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1051 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1052 static const char *const alt_short_patt[] = {
1053 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1054 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1055 alt_short_14, alt_short_15
1056 };
1057 static const char *const alt_long_patt[] = {
1058 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1059 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1060 alt_long_14, alt_long_15
1061 };
252b5132 1062
76bc74dc
L		 1063 /* Only align for at least a positive non-zero boundary. */
1064 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1065 return;
3e73aa7c 1066
ccc9c027
L		 1067 /* We need to decide which NOP sequence to use for 32bit and
1068 64bit. When -mtune= is used:
4eed87de 1069
76bc74dc
L		 1070 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1071 PROCESSOR_GENERIC32, f32_patt will be used.
1072 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1073 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1074 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1075 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1076 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1077 will be used.
ccc9c027 1078
76bc74dc 1079 When -mtune= isn't used, alt_long_patt will be used if
22109423 1080 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1081 be used.
ccc9c027
L		 1082
1083 When -march= or .arch is used, we can't use anything beyond
1084 cpu_arch_isa_flags. */
1085
1086 if (flag_code == CODE_16BIT)
1087 {
ccc9c027 1088 if (count > 8)
33fef721 1089 {
76bc74dc
L		 1090 memcpy (fragP->fr_literal + fragP->fr_fix,
1091 jump_31, count);
1092 /* Adjust jump offset. */
1093 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1094 }
76bc74dc
L		 1095 else
1096 memcpy (fragP->fr_literal + fragP->fr_fix,
1097 f16_patt[count - 1], count);
252b5132 1098 }
33fef721 1099 else
ccc9c027
L		 1100 {
1101 const char *const *patt = NULL;
1102
fbf3f584 1103 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1104 {
1105 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1106 switch (cpu_arch_tune)
1107 {
1108 case PROCESSOR_UNKNOWN:
1109 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1110 optimize with nops. */
1111 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1112 patt = alt_long_patt;
ccc9c027
L		 1113 else
1114 patt = f32_patt;
1115 break;
ccc9c027
L		 1116 case PROCESSOR_PENTIUM4:
1117 case PROCESSOR_NOCONA:
ef05d495 1118 case PROCESSOR_CORE:
76bc74dc 1119 case PROCESSOR_CORE2:
bd5295b2 1120 case PROCESSOR_COREI7:
3632d14b 1121 case PROCESSOR_L1OM:
7a9068fe 1122 case PROCESSOR_K1OM:
76bc74dc
L		 1123 case PROCESSOR_GENERIC64:
1124 patt = alt_long_patt;
1125 break;
ccc9c027
L		 1126 case PROCESSOR_K6:
1127 case PROCESSOR_ATHLON:
1128 case PROCESSOR_K8:
4eed87de 1129 case PROCESSOR_AMDFAM10:
8aedb9fe 1130 case PROCESSOR_BD:
7b458c12 1131 case PROCESSOR_BT:
ccc9c027
L		 1132 patt = alt_short_patt;
1133 break;
76bc74dc 1134 case PROCESSOR_I386:
ccc9c027
L		 1135 case PROCESSOR_I486:
1136 case PROCESSOR_PENTIUM:
2dde1948 1137 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1138 case PROCESSOR_GENERIC32:
1139 patt = f32_patt;
1140 break;
4eed87de 1141 }
ccc9c027
L		 1142 }
1143 else
1144 {
fbf3f584 1145 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1146 {
1147 case PROCESSOR_UNKNOWN:
e6a14101 1148 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1149 PROCESSOR_UNKNOWN. */
1150 abort ();
1151 break;
1152
76bc74dc 1153 case PROCESSOR_I386:
ccc9c027
L		 1154 case PROCESSOR_I486:
1155 case PROCESSOR_PENTIUM:
ccc9c027
L		 1156 case PROCESSOR_K6:
1157 case PROCESSOR_ATHLON:
1158 case PROCESSOR_K8:
4eed87de 1159 case PROCESSOR_AMDFAM10:
8aedb9fe 1160 case PROCESSOR_BD:
7b458c12 1161 case PROCESSOR_BT:
ccc9c027
L		 1162 case PROCESSOR_GENERIC32:
1163 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1164 with nops. */
1165 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1166 patt = alt_short_patt;
1167 else
1168 patt = f32_patt;
1169 break;
76bc74dc
L		 1170 case PROCESSOR_PENTIUMPRO:
1171 case PROCESSOR_PENTIUM4:
1172 case PROCESSOR_NOCONA:
1173 case PROCESSOR_CORE:
ef05d495 1174 case PROCESSOR_CORE2:
bd5295b2 1175 case PROCESSOR_COREI7:
3632d14b 1176 case PROCESSOR_L1OM:
7a9068fe 1177 case PROCESSOR_K1OM:
22109423 1178 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1179 patt = alt_long_patt;
1180 else
1181 patt = f32_patt;
1182 break;
1183 case PROCESSOR_GENERIC64:
76bc74dc 1184 patt = alt_long_patt;
ccc9c027 1185 break;
4eed87de 1186 }
ccc9c027
L		 1187 }
1188
76bc74dc
L		 1189 if (patt == f32_patt)
1190 {
1191 /* If the padding is less than 15 bytes, we use the normal
1192 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1193 its offset. */
1194 int limit;
76ba9986 1195
711eedef
L		 1196 /* For 64bit, the limit is 3 bytes. */
1197 if (flag_code == CODE_64BIT
1198 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1199 limit = 3;
1200 else
1201 limit = 15;
1202 if (count < limit)
76bc74dc
L		 1203 memcpy (fragP->fr_literal + fragP->fr_fix,
1204 patt[count - 1], count);
1205 else
1206 {
1207 memcpy (fragP->fr_literal + fragP->fr_fix,
1208 jump_31, count);
1209 /* Adjust jump offset. */
1210 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1211 }
1212 }
1213 else
1214 {
1215 /* Maximum length of an instruction is 15 byte. If the
1216 padding is greater than 15 bytes and we don't use jump,
1217 we have to break it into smaller pieces. */
1218 int padding = count;
1219 while (padding > 15)
1220 {
1221 padding -= 15;
1222 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1223 patt [14], 15);
1224 }
1225
1226 if (padding)
1227 memcpy (fragP->fr_literal + fragP->fr_fix,
1228 patt [padding - 1], padding);
1229 }
ccc9c027 1230 }
33fef721 1231 fragP->fr_var = count;
252b5132
RH		 1232}
1233
c6fb90c8 1234static INLINE int
0dfbf9d7 1235operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1236{
0dfbf9d7 1237 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1238 {
1239 case 3:
0dfbf9d7 1240 if (x->array[2])
c6fb90c8
L		 1241 return 0;
1242 case 2:
0dfbf9d7 1243 if (x->array[1])
c6fb90c8
L		 1244 return 0;
1245 case 1:
0dfbf9d7 1246 return !x->array[0];
c6fb90c8
L		 1247 default:
1248 abort ();
1249 }
40fb9820
L		 1250}
1251
c6fb90c8 1252static INLINE void
0dfbf9d7 1253operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1254{
0dfbf9d7 1255 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1256 {
1257 case 3:
0dfbf9d7 1258 x->array[2] = v;
c6fb90c8 1259 case 2:
0dfbf9d7 1260 x->array[1] = v;
c6fb90c8 1261 case 1:
0dfbf9d7 1262 x->array[0] = v;
c6fb90c8
L		 1263 break;
1264 default:
1265 abort ();
1266 }
1267}
40fb9820 1268
c6fb90c8 1269static INLINE int
0dfbf9d7
L		 1270operand_type_equal (const union i386_operand_type *x,
1271 const union i386_operand_type *y)
c6fb90c8 1272{
0dfbf9d7 1273 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1274 {
1275 case 3:
0dfbf9d7 1276 if (x->array[2] != y->array[2])
c6fb90c8
L		 1277 return 0;
1278 case 2:
0dfbf9d7 1279 if (x->array[1] != y->array[1])
c6fb90c8
L		 1280 return 0;
1281 case 1:
0dfbf9d7 1282 return x->array[0] == y->array[0];
c6fb90c8
L		 1283 break;
1284 default:
1285 abort ();
1286 }
1287}
40fb9820 1288
0dfbf9d7
L		 1289static INLINE int
1290cpu_flags_all_zero (const union i386_cpu_flags *x)
1291{
1292 switch (ARRAY_SIZE(x->array))
1293 {
1294 case 3:
1295 if (x->array[2])
1296 return 0;
1297 case 2:
1298 if (x->array[1])
1299 return 0;
1300 case 1:
1301 return !x->array[0];
1302 default:
1303 abort ();
1304 }
1305}
1306
1307static INLINE void
1308cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1309{
1310 switch (ARRAY_SIZE(x->array))
1311 {
1312 case 3:
1313 x->array[2] = v;
1314 case 2:
1315 x->array[1] = v;
1316 case 1:
1317 x->array[0] = v;
1318 break;
1319 default:
1320 abort ();
1321 }
1322}
1323
1324static INLINE int
1325cpu_flags_equal (const union i386_cpu_flags *x,
1326 const union i386_cpu_flags *y)
1327{
1328 switch (ARRAY_SIZE(x->array))
1329 {
1330 case 3:
1331 if (x->array[2] != y->array[2])
1332 return 0;
1333 case 2:
1334 if (x->array[1] != y->array[1])
1335 return 0;
1336 case 1:
1337 return x->array[0] == y->array[0];
1338 break;
1339 default:
1340 abort ();
1341 }
1342}
c6fb90c8
L		 1343
1344static INLINE int
1345cpu_flags_check_cpu64 (i386_cpu_flags f)
1346{
1347 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1348 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1349}
1350
c6fb90c8
L		 1351static INLINE i386_cpu_flags
1352cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1353{
c6fb90c8
L		 1354 switch (ARRAY_SIZE (x.array))
1355 {
1356 case 3:
1357 x.array [2] &= y.array [2];
1358 case 2:
1359 x.array [1] &= y.array [1];
1360 case 1:
1361 x.array [0] &= y.array [0];
1362 break;
1363 default:
1364 abort ();
1365 }
1366 return x;
1367}
40fb9820 1368
c6fb90c8
L		 1369static INLINE i386_cpu_flags
1370cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1371{
c6fb90c8 1372 switch (ARRAY_SIZE (x.array))
40fb9820 1373 {
c6fb90c8
L		 1374 case 3:
1375 x.array [2] |= y.array [2];
1376 case 2:
1377 x.array [1] |= y.array [1];
1378 case 1:
1379 x.array [0] |= y.array [0];
40fb9820
L		 1380 break;
1381 default:
1382 abort ();
1383 }
40fb9820
L		 1384 return x;
1385}
1386
309d3373
JB		 1387static INLINE i386_cpu_flags
1388cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1389{
1390 switch (ARRAY_SIZE (x.array))
1391 {
1392 case 3:
1393 x.array [2] &= ~y.array [2];
1394 case 2:
1395 x.array [1] &= ~y.array [1];
1396 case 1:
1397 x.array [0] &= ~y.array [0];
1398 break;
1399 default:
1400 abort ();
1401 }
1402 return x;
1403}
1404
c0f3af97
L		 1405#define CPU_FLAGS_ARCH_MATCH 0x1
1406#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1407#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1408#define CPU_FLAGS_PCLMUL_MATCH 0x8
1409#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1410
a5ff0eb2 1411#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1412 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1413 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1414#define CPU_FLAGS_PERFECT_MATCH \
1415 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1416
1417/* Return CPU flags match bits. */
3629bb00 1418
40fb9820 1419static int
d3ce72d0 1420cpu_flags_match (const insn_template *t)
40fb9820 1421{
c0f3af97
L		 1422 i386_cpu_flags x = t->cpu_flags;
1423 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1424
1425 x.bitfield.cpu64 = 0;
1426 x.bitfield.cpuno64 = 0;
1427
0dfbf9d7 1428 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1429 {
1430 /* This instruction is available on all archs. */
1431 match |= CPU_FLAGS_32BIT_MATCH;
1432 }
3629bb00
L		 1433 else
1434 {
c0f3af97 1435 /* This instruction is available only on some archs. */
3629bb00
L		 1436 i386_cpu_flags cpu = cpu_arch_flags;
1437
1438 cpu.bitfield.cpu64 = 0;
1439 cpu.bitfield.cpuno64 = 0;
1440 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1441 if (!cpu_flags_all_zero (&cpu))
1442 {
a5ff0eb2
L		 1443 if (x.bitfield.cpuavx)
1444 {
ce2f5b3c 1445 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1446 if (cpu.bitfield.cpuavx)
1447 {
1448 /* Check SSE2AVX. */
1449 if (!t->opcode_modifier.sse2avx|| sse2avx)
1450 {
1451 match |= (CPU_FLAGS_ARCH_MATCH
1452 | CPU_FLAGS_AVX_MATCH);
1453 /* Check AES. */
1454 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1455 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1456 /* Check PCLMUL. */
1457 if (!x.bitfield.cpupclmul
1458 || cpu.bitfield.cpupclmul)
1459 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1460 }
1461 }
1462 else
1463 match |= CPU_FLAGS_ARCH_MATCH;
1464 }
1465 else
c0f3af97
L		 1466 match |= CPU_FLAGS_32BIT_MATCH;
1467 }
3629bb00 1468 }
c0f3af97 1469 return match;
40fb9820
L		 1470}
1471
c6fb90c8
L		 1472static INLINE i386_operand_type
1473operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1474{
c6fb90c8
L		 1475 switch (ARRAY_SIZE (x.array))
1476 {
1477 case 3:
1478 x.array [2] &= y.array [2];
1479 case 2:
1480 x.array [1] &= y.array [1];
1481 case 1:
1482 x.array [0] &= y.array [0];
1483 break;
1484 default:
1485 abort ();
1486 }
1487 return x;
40fb9820
L		 1488}
1489
c6fb90c8
L		 1490static INLINE i386_operand_type
1491operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1492{
c6fb90c8 1493 switch (ARRAY_SIZE (x.array))
40fb9820 1494 {
c6fb90c8
L		 1495 case 3:
1496 x.array [2] |= y.array [2];
1497 case 2:
1498 x.array [1] |= y.array [1];
1499 case 1:
1500 x.array [0] |= y.array [0];
40fb9820
L		 1501 break;
1502 default:
1503 abort ();
1504 }
c6fb90c8
L		 1505 return x;
1506}
40fb9820 1507
c6fb90c8
L		 1508static INLINE i386_operand_type
1509operand_type_xor (i386_operand_type x, i386_operand_type y)
1510{
1511 switch (ARRAY_SIZE (x.array))
1512 {
1513 case 3:
1514 x.array [2] ^= y.array [2];
1515 case 2:
1516 x.array [1] ^= y.array [1];
1517 case 1:
1518 x.array [0] ^= y.array [0];
1519 break;
1520 default:
1521 abort ();
1522 }
40fb9820
L		 1523 return x;
1524}
1525
1526static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1527static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1528static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1529static const i386_operand_type inoutportreg
1530 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1531static const i386_operand_type reg16_inoutportreg
1532 = OPERAND_TYPE_REG16_INOUTPORTREG;
1533static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1534static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1535static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1536static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1537static const i386_operand_type anydisp
1538 = OPERAND_TYPE_ANYDISP;
40fb9820 1539static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1540static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1541static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1542static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1543static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1544static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1545static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1546static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1547static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1548static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1549static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1550static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1551
1552enum operand_type
1553{
1554 reg,
40fb9820
L		 1555 imm,
1556 disp,
1557 anymem
1558};
1559
c6fb90c8 1560static INLINE int
40fb9820
L		 1561operand_type_check (i386_operand_type t, enum operand_type c)
1562{
1563 switch (c)
1564 {
1565 case reg:
1566 return (t.bitfield.reg8
1567 || t.bitfield.reg16
1568 || t.bitfield.reg32
1569 || t.bitfield.reg64);
1570
40fb9820
L		 1571 case imm:
1572 return (t.bitfield.imm8
1573 || t.bitfield.imm8s
1574 || t.bitfield.imm16
1575 || t.bitfield.imm32
1576 || t.bitfield.imm32s
1577 || t.bitfield.imm64);
1578
1579 case disp:
1580 return (t.bitfield.disp8
1581 || t.bitfield.disp16
1582 || t.bitfield.disp32
1583 || t.bitfield.disp32s
1584 || t.bitfield.disp64);
1585
1586 case anymem:
1587 return (t.bitfield.disp8
1588 || t.bitfield.disp16
1589 || t.bitfield.disp32
1590 || t.bitfield.disp32s
1591 || t.bitfield.disp64
1592 || t.bitfield.baseindex);
1593
1594 default:
1595 abort ();
1596 }
2cfe26b6
AM		 1597
1598 return 0;
40fb9820
L		 1599}
1600
5c07affc
L		 1601/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1602 operand J for instruction template T. */
1603
1604static INLINE int
d3ce72d0 1605match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1606{
1607 return !((i.types[j].bitfield.byte
1608 && !t->operand_types[j].bitfield.byte)
1609 || (i.types[j].bitfield.word
1610 && !t->operand_types[j].bitfield.word)
1611 || (i.types[j].bitfield.dword
1612 && !t->operand_types[j].bitfield.dword)
1613 || (i.types[j].bitfield.qword
1614 && !t->operand_types[j].bitfield.qword));
1615}
1616
1617/* Return 1 if there is no conflict in any size on operand J for
1618 instruction template T. */
1619
1620static INLINE int
d3ce72d0 1621match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1622{
1623 return (match_reg_size (t, j)
1624 && !((i.types[j].bitfield.unspecified
1625 && !t->operand_types[j].bitfield.unspecified)
1626 || (i.types[j].bitfield.fword
1627 && !t->operand_types[j].bitfield.fword)
1628 || (i.types[j].bitfield.tbyte
1629 && !t->operand_types[j].bitfield.tbyte)
1630 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1631 && !t->operand_types[j].bitfield.xmmword)
1632 || (i.types[j].bitfield.ymmword
1633 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1634}
1635
1636/* Return 1 if there is no size conflict on any operands for
1637 instruction template T. */
1638
1639static INLINE int
d3ce72d0 1640operand_size_match (const insn_template *t)
5c07affc
L		 1641{
1642 unsigned int j;
1643 int match = 1;
1644
1645 /* Don't check jump instructions. */
1646 if (t->opcode_modifier.jump
1647 || t->opcode_modifier.jumpbyte
1648 || t->opcode_modifier.jumpdword
1649 || t->opcode_modifier.jumpintersegment)
1650 return match;
1651
1652 /* Check memory and accumulator operand size. */
1653 for (j = 0; j < i.operands; j++)
1654 {
1655 if (t->operand_types[j].bitfield.anysize)
1656 continue;
1657
1658 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1659 {
1660 match = 0;
1661 break;
1662 }
1663
1664 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1665 {
1666 match = 0;
1667 break;
1668 }
1669 }
1670
891edac4 1671 if (match)
5c07affc 1672 return match;
891edac4
L		 1673 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1674 {
1675mismatch:
86e026a4 1676 i.error = operand_size_mismatch;
891edac4
L		 1677 return 0;
1678 }
5c07affc
L		 1679
1680 /* Check reverse. */
9c2799c2 1681 gas_assert (i.operands == 2);
5c07affc
L		 1682
1683 match = 1;
1684 for (j = 0; j < 2; j++)
1685 {
1686 if (t->operand_types[j].bitfield.acc
1687 && !match_reg_size (t, j ? 0 : 1))
891edac4 1688 goto mismatch;
5c07affc
L		 1689
1690 if (i.types[j].bitfield.mem
1691 && !match_mem_size (t, j ? 0 : 1))
891edac4 1692 goto mismatch;
5c07affc
L		 1693 }
1694
1695 return match;
1696}
1697
c6fb90c8 1698static INLINE int
40fb9820
L		 1699operand_type_match (i386_operand_type overlap,
1700 i386_operand_type given)
1701{
1702 i386_operand_type temp = overlap;
1703
1704 temp.bitfield.jumpabsolute = 0;
7d5e4556 1705 temp.bitfield.unspecified = 0;
5c07affc
L		 1706 temp.bitfield.byte = 0;
1707 temp.bitfield.word = 0;
1708 temp.bitfield.dword = 0;
1709 temp.bitfield.fword = 0;
1710 temp.bitfield.qword = 0;
1711 temp.bitfield.tbyte = 0;
1712 temp.bitfield.xmmword = 0;
c0f3af97 1713 temp.bitfield.ymmword = 0;
0dfbf9d7 1714 if (operand_type_all_zero (&temp))
891edac4 1715 goto mismatch;
40fb9820 1716
891edac4
L		 1717 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1718 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1719 return 1;
1720
1721mismatch:
a65babc9 1722 i.error = operand_type_mismatch;
891edac4 1723 return 0;
40fb9820
L		 1724}
1725
7d5e4556 1726/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1727 unless the expected operand type register overlap is null.
1728 Note that Acc in a template matches every size of reg. */
1729
c6fb90c8 1730static INLINE int
40fb9820
L		 1731operand_type_register_match (i386_operand_type m0,
1732 i386_operand_type g0,
1733 i386_operand_type t0,
1734 i386_operand_type m1,
1735 i386_operand_type g1,
1736 i386_operand_type t1)
1737{
1738 if (!operand_type_check (g0, reg))
1739 return 1;
1740
1741 if (!operand_type_check (g1, reg))
1742 return 1;
1743
1744 if (g0.bitfield.reg8 == g1.bitfield.reg8
1745 && g0.bitfield.reg16 == g1.bitfield.reg16
1746 && g0.bitfield.reg32 == g1.bitfield.reg32
1747 && g0.bitfield.reg64 == g1.bitfield.reg64)
1748 return 1;
1749
1750 if (m0.bitfield.acc)
1751 {
1752 t0.bitfield.reg8 = 1;
1753 t0.bitfield.reg16 = 1;
1754 t0.bitfield.reg32 = 1;
1755 t0.bitfield.reg64 = 1;
1756 }
1757
1758 if (m1.bitfield.acc)
1759 {
1760 t1.bitfield.reg8 = 1;
1761 t1.bitfield.reg16 = 1;
1762 t1.bitfield.reg32 = 1;
1763 t1.bitfield.reg64 = 1;
1764 }
1765
891edac4
L		 1766 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1767 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1768 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1769 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1770 return 1;
1771
a65babc9 1772 i.error = register_type_mismatch;
891edac4
L		 1773
1774 return 0;
40fb9820
L		 1775}
1776
4c692bc7
JB		 1777static INLINE unsigned int
1778register_number (const reg_entry *r)
1779{
1780 unsigned int nr = r->reg_num;
1781
1782 if (r->reg_flags & RegRex)
1783 nr += 8;
1784
1785 return nr;
1786}
1787
252b5132 1788static INLINE unsigned int
40fb9820 1789mode_from_disp_size (i386_operand_type t)
252b5132 1790{
40fb9820
L		 1791 if (t.bitfield.disp8)
1792 return 1;
1793 else if (t.bitfield.disp16
1794 || t.bitfield.disp32
1795 || t.bitfield.disp32s)
1796 return 2;
1797 else
1798 return 0;
252b5132
RH		 1799}
1800
1801static INLINE int
e3bb37b5 1802fits_in_signed_byte (offsetT num)
252b5132
RH		 1803{
1804 return (num >= -128) && (num <= 127);
47926f60 1805}
252b5132
RH		 1806
1807static INLINE int
e3bb37b5 1808fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1809{
1810 return (num & 0xff) == num;
47926f60 1811}
252b5132
RH		 1812
1813static INLINE int
e3bb37b5 1814fits_in_unsigned_word (offsetT num)
252b5132
RH		 1815{
1816 return (num & 0xffff) == num;
47926f60 1817}
252b5132
RH		 1818
1819static INLINE int
e3bb37b5 1820fits_in_signed_word (offsetT num)
252b5132
RH		 1821{
1822 return (-32768 <= num) && (num <= 32767);
47926f60 1823}
2a962e6d 1824
3e73aa7c 1825static INLINE int
e3bb37b5 1826fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1827{
1828#ifndef BFD64
1829 return 1;
1830#else
1831 return (!(((offsetT) -1 << 31) & num)
1832 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1833#endif
1834} /* fits_in_signed_long() */
2a962e6d 1835
3e73aa7c 1836static INLINE int
e3bb37b5 1837fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1838{
1839#ifndef BFD64
1840 return 1;
1841#else
1842 return (num & (((offsetT) 2 << 31) - 1)) == num;
1843#endif
1844} /* fits_in_unsigned_long() */
252b5132 1845
a683cc34
SP		 1846static INLINE int
1847fits_in_imm4 (offsetT num)
1848{
1849 return (num & 0xf) == num;
1850}
1851
40fb9820 1852static i386_operand_type
e3bb37b5 1853smallest_imm_type (offsetT num)
252b5132 1854{
40fb9820 1855 i386_operand_type t;
7ab9ffdd 1856
0dfbf9d7 1857 operand_type_set (&t, 0);
40fb9820
L		 1858 t.bitfield.imm64 = 1;
1859
1860 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1861 {
1862 /* This code is disabled on the 486 because all the Imm1 forms
1863 in the opcode table are slower on the i486. They're the
1864 versions with the implicitly specified single-position
1865 displacement, which has another syntax if you really want to
1866 use that form. */
40fb9820
L		 1867 t.bitfield.imm1 = 1;
1868 t.bitfield.imm8 = 1;
1869 t.bitfield.imm8s = 1;
1870 t.bitfield.imm16 = 1;
1871 t.bitfield.imm32 = 1;
1872 t.bitfield.imm32s = 1;
1873 }
1874 else if (fits_in_signed_byte (num))
1875 {
1876 t.bitfield.imm8 = 1;
1877 t.bitfield.imm8s = 1;
1878 t.bitfield.imm16 = 1;
1879 t.bitfield.imm32 = 1;
1880 t.bitfield.imm32s = 1;
1881 }
1882 else if (fits_in_unsigned_byte (num))
1883 {
1884 t.bitfield.imm8 = 1;
1885 t.bitfield.imm16 = 1;
1886 t.bitfield.imm32 = 1;
1887 t.bitfield.imm32s = 1;
1888 }
1889 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1890 {
1891 t.bitfield.imm16 = 1;
1892 t.bitfield.imm32 = 1;
1893 t.bitfield.imm32s = 1;
1894 }
1895 else if (fits_in_signed_long (num))
1896 {
1897 t.bitfield.imm32 = 1;
1898 t.bitfield.imm32s = 1;
1899 }
1900 else if (fits_in_unsigned_long (num))
1901 t.bitfield.imm32 = 1;
1902
1903 return t;
47926f60 1904}
252b5132 1905
847f7ad4 1906static offsetT
e3bb37b5 1907offset_in_range (offsetT val, int size)
847f7ad4 1908{
508866be 1909 addressT mask;
ba2adb93 1910
847f7ad4
AM		 1911 switch (size)
1912 {
508866be
L		 1913 case 1: mask = ((addressT) 1 << 8) - 1; break;
1914 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1915 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1916#ifdef BFD64
1917 case 8: mask = ((addressT) 2 << 63) - 1; break;
1918#endif
47926f60 1919 default: abort ();
847f7ad4
AM		 1920 }
1921
9de868bf
L		 1922#ifdef BFD64
1923 /* If BFD64, sign extend val for 32bit address mode. */
1924 if (flag_code != CODE_64BIT
1925 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1926 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1927 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1928#endif
ba2adb93 1929
47926f60 1930 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1931 {
1932 char buf1[40], buf2[40];
1933
1934 sprint_value (buf1, val);
1935 sprint_value (buf2, val & mask);
1936 as_warn (_("%s shortened to %s"), buf1, buf2);
1937 }
1938 return val & mask;
1939}
1940
c32fa91d
L		 1941enum PREFIX_GROUP
1942{
1943 PREFIX_EXIST = 0,
1944 PREFIX_LOCK,
1945 PREFIX_REP,
1946 PREFIX_OTHER
1947};
1948
1949/* Returns
1950 a. PREFIX_EXIST if attempting to add a prefix where one from the
1951 same class already exists.
1952 b. PREFIX_LOCK if lock prefix is added.
1953 c. PREFIX_REP if rep/repne prefix is added.
1954 d. PREFIX_OTHER if other prefix is added.
1955 */
1956
1957static enum PREFIX_GROUP
e3bb37b5 1958add_prefix (unsigned int prefix)
252b5132 1959{
c32fa91d 1960 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1961 unsigned int q;
252b5132 1962
29b0f896
AM		 1963 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1964 && flag_code == CODE_64BIT)
b1905489 1965 {
161a04f6
L		 1966 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1967 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1968 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1969 ret = PREFIX_EXIST;
b1905489
JB		 1970 q = REX_PREFIX;
1971 }
3e73aa7c 1972 else
b1905489
JB		 1973 {
1974 switch (prefix)
1975 {
1976 default:
1977 abort ();
1978
1979 case CS_PREFIX_OPCODE:
1980 case DS_PREFIX_OPCODE:
1981 case ES_PREFIX_OPCODE:
1982 case FS_PREFIX_OPCODE:
1983 case GS_PREFIX_OPCODE:
1984 case SS_PREFIX_OPCODE:
1985 q = SEG_PREFIX;
1986 break;
1987
1988 case REPNE_PREFIX_OPCODE:
1989 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1990 q = REP_PREFIX;
1991 ret = PREFIX_REP;
1992 break;
1993
b1905489 1994 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1995 q = LOCK_PREFIX;
1996 ret = PREFIX_LOCK;
b1905489
JB		 1997 break;
1998
1999 case FWAIT_OPCODE:
2000 q = WAIT_PREFIX;
2001 break;
2002
2003 case ADDR_PREFIX_OPCODE:
2004 q = ADDR_PREFIX;
2005 break;
2006
2007 case DATA_PREFIX_OPCODE:
2008 q = DATA_PREFIX;
2009 break;
2010 }
2011 if (i.prefix[q] != 0)
c32fa91d 2012 ret = PREFIX_EXIST;
b1905489 2013 }
252b5132 2014
b1905489 2015 if (ret)
252b5132 2016 {
b1905489
JB		 2017 if (!i.prefix[q])
2018 ++i.prefixes;
2019 i.prefix[q] |= prefix;
252b5132 2020 }
b1905489
JB		 2021 else
2022 as_bad (_("same type of prefix used twice"));
252b5132 2023
252b5132
RH		 2024 return ret;
2025}
2026
2027static void
78f12dd3 2028update_code_flag (int value, int check)
eecb386c 2029{
78f12dd3
L		 2030 PRINTF_LIKE ((*as_error));
2031
1e9cc1c2 2032 flag_code = (enum flag_code) value;
40fb9820
L		 2033 if (flag_code == CODE_64BIT)
2034 {
2035 cpu_arch_flags.bitfield.cpu64 = 1;
2036 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2037 }
2038 else
2039 {
2040 cpu_arch_flags.bitfield.cpu64 = 0;
2041 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2042 }
2043 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2044 {
78f12dd3
L		 2045 if (check)
2046 as_error = as_fatal;
2047 else
2048 as_error = as_bad;
2049 (*as_error) (_("64bit mode not supported on `%s'."),
2050 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2051 }
40fb9820 2052 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2053 {
78f12dd3
L		 2054 if (check)
2055 as_error = as_fatal;
2056 else
2057 as_error = as_bad;
2058 (*as_error) (_("32bit mode not supported on `%s'."),
2059 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2060 }
eecb386c
AM		 2061 stackop_size = '\0';
2062}
2063
78f12dd3
L		 2064static void
2065set_code_flag (int value)
2066{
2067 update_code_flag (value, 0);
2068}
2069
eecb386c 2070static void
e3bb37b5 2071set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2072{
1e9cc1c2 2073 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2074 if (flag_code != CODE_16BIT)
2075 abort ();
2076 cpu_arch_flags.bitfield.cpu64 = 0;
2077 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2078 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2079}
2080
2081static void
e3bb37b5 2082set_intel_syntax (int syntax_flag)
252b5132
RH		 2083{
2084 /* Find out if register prefixing is specified. */
2085 int ask_naked_reg = 0;
2086
2087 SKIP_WHITESPACE ();
29b0f896 2088 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2089 {
2090 char *string = input_line_pointer;
2091 int e = get_symbol_end ();
2092
47926f60 2093 if (strcmp (string, "prefix") == 0)
252b5132 2094 ask_naked_reg = 1;
47926f60 2095 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2096 ask_naked_reg = -1;
2097 else
d0b47220 2098 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2099 *input_line_pointer = e;
2100 }
2101 demand_empty_rest_of_line ();
c3332e24 2102
252b5132
RH		 2103 intel_syntax = syntax_flag;
2104
2105 if (ask_naked_reg == 0)
f86103b7
AM		 2106 allow_naked_reg = (intel_syntax
2107 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2108 else
2109 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2110
ee86248c 2111 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2112
e4a3b5a4 2113 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2114 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2115 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2116}
2117
1efbbeb4
L		 2118static void
2119set_intel_mnemonic (int mnemonic_flag)
2120{
e1d4d893 2121 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2122}
2123
db51cc60
L		 2124static void
2125set_allow_index_reg (int flag)
2126{
2127 allow_index_reg = flag;
2128}
2129
cb19c032 2130static void
7bab8ab5 2131set_check (int what)
cb19c032 2132{
7bab8ab5
JB		 2133 enum check_kind *kind;
2134 const char *str;
2135
2136 if (what)
2137 {
2138 kind = &operand_check;
2139 str = "operand";
2140 }
2141 else
2142 {
2143 kind = &sse_check;
2144 str = "sse";
2145 }
2146
cb19c032
L		 2147 SKIP_WHITESPACE ();
2148
2149 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2150 {
2151 char *string = input_line_pointer;
2152 int e = get_symbol_end ();
2153
2154 if (strcmp (string, "none") == 0)
7bab8ab5 2155 *kind = check_none;
cb19c032 2156 else if (strcmp (string, "warning") == 0)
7bab8ab5 2157 *kind = check_warning;
cb19c032 2158 else if (strcmp (string, "error") == 0)
7bab8ab5 2159 *kind = check_error;
cb19c032 2160 else
7bab8ab5 2161 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2162 *input_line_pointer = e;
2163 }
2164 else
7bab8ab5 2165 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2166
2167 demand_empty_rest_of_line ();
2168}
2169
8a9036a4
L		 2170static void
2171check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2172 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2173{
2174#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2175 static const char *arch;
2176
2177 /* Intel LIOM is only supported on ELF. */
2178 if (!IS_ELF)
2179 return;
2180
2181 if (!arch)
2182 {
2183 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2184 use default_arch. */
2185 arch = cpu_arch_name;
2186 if (!arch)
2187 arch = default_arch;
2188 }
2189
3632d14b 2190 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2191 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2192 || new_flag.bitfield.cpul1om)
8a9036a4 2193 return;
76ba9986 2194
7a9068fe
L		 2195 /* If we are targeting Intel K1OM, we must enable it. */
2196 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2197 || new_flag.bitfield.cpuk1om)
2198 return;
2199
8a9036a4
L		 2200 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2201#endif
2202}
2203
e413e4e9 2204static void
e3bb37b5 2205set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2206{
47926f60 2207 SKIP_WHITESPACE ();
e413e4e9 2208
29b0f896 2209 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2210 {
2211 char *string = input_line_pointer;
2212 int e = get_symbol_end ();
91d6fa6a 2213 unsigned int j;
40fb9820 2214 i386_cpu_flags flags;
e413e4e9 2215
91d6fa6a 2216 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2217 {
91d6fa6a 2218 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2219 {
91d6fa6a 2220 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2221
5c6af06e
JB		 2222 if (*string != '.')
2223 {
91d6fa6a 2224 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2225 cpu_sub_arch_name = NULL;
91d6fa6a 2226 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2227 if (flag_code == CODE_64BIT)
2228 {
2229 cpu_arch_flags.bitfield.cpu64 = 1;
2230 cpu_arch_flags.bitfield.cpuno64 = 0;
2231 }
2232 else
2233 {
2234 cpu_arch_flags.bitfield.cpu64 = 0;
2235 cpu_arch_flags.bitfield.cpuno64 = 1;
2236 }
91d6fa6a
NC		 2237 cpu_arch_isa = cpu_arch[j].type;
2238 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2239 if (!cpu_arch_tune_set)
2240 {
2241 cpu_arch_tune = cpu_arch_isa;
2242 cpu_arch_tune_flags = cpu_arch_isa_flags;
2243 }
5c6af06e
JB		 2244 break;
2245 }
40fb9820 2246
22109423 2247 if (!cpu_arch[j].negated)
309d3373 2248 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2249 cpu_arch[j].flags);
309d3373
JB		 2250 else
2251 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2252 cpu_arch[j].flags);
0dfbf9d7 2253 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2254 {
6305a203
L		 2255 if (cpu_sub_arch_name)
2256 {
2257 char *name = cpu_sub_arch_name;
2258 cpu_sub_arch_name = concat (name,
91d6fa6a 2259 cpu_arch[j].name,
1bf57e9f 2260 (const char *) NULL);
6305a203
L		 2261 free (name);
2262 }
2263 else
91d6fa6a 2264 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2265 cpu_arch_flags = flags;
a586129e 2266 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2267 }
2268 *input_line_pointer = e;
2269 demand_empty_rest_of_line ();
2270 return;
e413e4e9
AM		 2271 }
2272 }
91d6fa6a 2273 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2274 as_bad (_("no such architecture: `%s'"), string);
2275
2276 *input_line_pointer = e;
2277 }
2278 else
2279 as_bad (_("missing cpu architecture"));
2280
fddf5b5b
AM		 2281 no_cond_jump_promotion = 0;
2282 if (*input_line_pointer == ','
29b0f896 2283 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2284 {
2285 char *string = ++input_line_pointer;
2286 int e = get_symbol_end ();
2287
2288 if (strcmp (string, "nojumps") == 0)
2289 no_cond_jump_promotion = 1;
2290 else if (strcmp (string, "jumps") == 0)
2291 ;
2292 else
2293 as_bad (_("no such architecture modifier: `%s'"), string);
2294
2295 *input_line_pointer = e;
2296 }
2297
e413e4e9
AM		 2298 demand_empty_rest_of_line ();
2299}
2300
8a9036a4
L		 2301enum bfd_architecture
2302i386_arch (void)
2303{
3632d14b 2304 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2305 {
2306 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2307 || flag_code != CODE_64BIT)
2308 as_fatal (_("Intel L1OM is 64bit ELF only"));
2309 return bfd_arch_l1om;
2310 }
7a9068fe
L		 2311 else if (cpu_arch_isa == PROCESSOR_K1OM)
2312 {
2313 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2314 || flag_code != CODE_64BIT)
2315 as_fatal (_("Intel K1OM is 64bit ELF only"));
2316 return bfd_arch_k1om;
2317 }
8a9036a4
L		 2318 else
2319 return bfd_arch_i386;
2320}
2321
b9d79e03 2322unsigned long
7016a5d5 2323i386_mach (void)
b9d79e03 2324{
351f65ca 2325 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2326 {
3632d14b 2327 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2328 {
351f65ca
L		 2329 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2330 || default_arch[6] != '\0')
8a9036a4
L		 2331 as_fatal (_("Intel L1OM is 64bit ELF only"));
2332 return bfd_mach_l1om;
2333 }
7a9068fe
L		 2334 else if (cpu_arch_isa == PROCESSOR_K1OM)
2335 {
2336 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2337 || default_arch[6] != '\0')
2338 as_fatal (_("Intel K1OM is 64bit ELF only"));
2339 return bfd_mach_k1om;
2340 }
351f65ca 2341 else if (default_arch[6] == '\0')
8a9036a4 2342 return bfd_mach_x86_64;
351f65ca
L		 2343 else
2344 return bfd_mach_x64_32;
8a9036a4 2345 }
b9d79e03
JH		 2346 else if (!strcmp (default_arch, "i386"))
2347 return bfd_mach_i386_i386;
2348 else
2b5d6a91 2349 as_fatal (_("unknown architecture"));
b9d79e03 2350}
b9d79e03 2351\f
252b5132 2352void
7016a5d5 2353md_begin (void)
252b5132
RH		 2354{
2355 const char *hash_err;
2356
47926f60 2357 /* Initialize op_hash hash table. */
252b5132
RH		 2358 op_hash = hash_new ();
2359
2360 {
d3ce72d0 2361 const insn_template *optab;
29b0f896 2362 templates *core_optab;
252b5132 2363
47926f60
KH		 2364 /* Setup for loop. */
2365 optab = i386_optab;
252b5132
RH		 2366 core_optab = (templates *) xmalloc (sizeof (templates));
2367 core_optab->start = optab;
2368
2369 while (1)
2370 {
2371 ++optab;
2372 if (optab->name == NULL
2373 || strcmp (optab->name, (optab - 1)->name) != 0)
2374 {
2375 /* different name --> ship out current template list;
47926f60 2376 add to hash table; & begin anew. */
252b5132
RH		 2377 core_optab->end = optab;
2378 hash_err = hash_insert (op_hash,
2379 (optab - 1)->name,
5a49b8ac 2380 (void *) core_optab);
252b5132
RH		 2381 if (hash_err)
2382 {
b37df7c4 2383 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2384 (optab - 1)->name,
2385 hash_err);
2386 }
2387 if (optab->name == NULL)
2388 break;
2389 core_optab = (templates *) xmalloc (sizeof (templates));
2390 core_optab->start = optab;
2391 }
2392 }
2393 }
2394
47926f60 2395 /* Initialize reg_hash hash table. */
252b5132
RH		 2396 reg_hash = hash_new ();
2397 {
29b0f896 2398 const reg_entry *regtab;
c3fe08fa 2399 unsigned int regtab_size = i386_regtab_size;
252b5132 2400
c3fe08fa 2401 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2402 {
5a49b8ac 2403 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2404 if (hash_err)
b37df7c4 2405 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2406 regtab->reg_name,
2407 hash_err);
252b5132
RH		 2408 }
2409 }
2410
47926f60 2411 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2412 {
29b0f896
AM		 2413 int c;
2414 char *p;
252b5132
RH		 2415
2416 for (c = 0; c < 256; c++)
2417 {
3882b010 2418 if (ISDIGIT (c))
252b5132
RH		 2419 {
2420 digit_chars[c] = c;
2421 mnemonic_chars[c] = c;
2422 register_chars[c] = c;
2423 operand_chars[c] = c;
2424 }
3882b010 2425 else if (ISLOWER (c))
252b5132
RH		 2426 {
2427 mnemonic_chars[c] = c;
2428 register_chars[c] = c;
2429 operand_chars[c] = c;
2430 }
3882b010 2431 else if (ISUPPER (c))
252b5132 2432 {
3882b010 2433 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2434 register_chars[c] = mnemonic_chars[c];
2435 operand_chars[c] = c;
2436 }
2437
3882b010 2438 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2439 identifier_chars[c] = c;
2440 else if (c >= 128)
2441 {
2442 identifier_chars[c] = c;
2443 operand_chars[c] = c;
2444 }
2445 }
2446
2447#ifdef LEX_AT
2448 identifier_chars['@'] = '@';
32137342
NC		 2449#endif
2450#ifdef LEX_QM
2451 identifier_chars['?'] = '?';
2452 operand_chars['?'] = '?';
252b5132 2453#endif
252b5132 2454 digit_chars['-'] = '-';
c0f3af97 2455 mnemonic_chars['_'] = '_';
791fe849 2456 mnemonic_chars['-'] = '-';
0003779b 2457 mnemonic_chars['.'] = '.';
252b5132
RH		 2458 identifier_chars['_'] = '_';
2459 identifier_chars['.'] = '.';
2460
2461 for (p = operand_special_chars; *p != '\0'; p++)
2462 operand_chars[(unsigned char) *p] = *p;
2463 }
2464
2465#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2466 if (IS_ELF)
252b5132
RH		 2467 {
2468 record_alignment (text_section, 2);
2469 record_alignment (data_section, 2);
2470 record_alignment (bss_section, 2);
2471 }
2472#endif
a4447b93
RH		 2473
2474 if (flag_code == CODE_64BIT)
2475 {
ca19b261
KT		 2476#if defined (OBJ_COFF) && defined (TE_PE)
2477 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2478 ? 32 : 16);
2479#else
a4447b93 2480 x86_dwarf2_return_column = 16;
ca19b261 2481#endif
61ff971f 2482 x86_cie_data_alignment = -8;
a4447b93
RH		 2483 }
2484 else
2485 {
2486 x86_dwarf2_return_column = 8;
2487 x86_cie_data_alignment = -4;
2488 }
252b5132
RH		 2489}
2490
2491void
e3bb37b5 2492i386_print_statistics (FILE *file)
252b5132
RH		 2493{
2494 hash_print_statistics (file, "i386 opcode", op_hash);
2495 hash_print_statistics (file, "i386 register", reg_hash);
2496}
2497\f
252b5132
RH		 2498#ifdef DEBUG386
2499
ce8a8b2f 2500/* Debugging routines for md_assemble. */
d3ce72d0 2501static void pte (insn_template *);
40fb9820 2502static void pt (i386_operand_type);
e3bb37b5
L		 2503static void pe (expressionS *);
2504static void ps (symbolS *);
252b5132
RH		 2505
2506static void
e3bb37b5 2507pi (char *line, i386_insn *x)
252b5132 2508{
09137c09 2509 unsigned int j;
252b5132
RH		 2510
2511 fprintf (stdout, "%s: template ", line);
2512 pte (&x->tm);
09f131f2
JH		 2513 fprintf (stdout, " address: base %s index %s scale %x\n",
2514 x->base_reg ? x->base_reg->reg_name : "none",
2515 x->index_reg ? x->index_reg->reg_name : "none",
2516 x->log2_scale_factor);
2517 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2518 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2519 fprintf (stdout, " sib: base %x index %x scale %x\n",
2520 x->sib.base, x->sib.index, x->sib.scale);
2521 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2522 (x->rex & REX_W) != 0,
2523 (x->rex & REX_R) != 0,
2524 (x->rex & REX_X) != 0,
2525 (x->rex & REX_B) != 0);
09137c09 2526 for (j = 0; j < x->operands; j++)
252b5132 2527 {
09137c09
SP		 2528 fprintf (stdout, " #%d: ", j + 1);
2529 pt (x->types[j]);
252b5132 2530 fprintf (stdout, "\n");
09137c09
SP		 2531 if (x->types[j].bitfield.reg8
2532 || x->types[j].bitfield.reg16
2533 || x->types[j].bitfield.reg32
2534 || x->types[j].bitfield.reg64
2535 || x->types[j].bitfield.regmmx
2536 || x->types[j].bitfield.regxmm
2537 || x->types[j].bitfield.regymm
2538 || x->types[j].bitfield.sreg2
2539 || x->types[j].bitfield.sreg3
2540 || x->types[j].bitfield.control
2541 || x->types[j].bitfield.debug
2542 || x->types[j].bitfield.test)
2543 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2544 if (operand_type_check (x->types[j], imm))
2545 pe (x->op[j].imms);
2546 if (operand_type_check (x->types[j], disp))
2547 pe (x->op[j].disps);
252b5132
RH		 2548 }
2549}
2550
2551static void
d3ce72d0 2552pte (insn_template *t)
252b5132 2553{
09137c09 2554 unsigned int j;
252b5132 2555 fprintf (stdout, " %d operands ", t->operands);
47926f60 2556 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2557 if (t->extension_opcode != None)
2558 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2559 if (t->opcode_modifier.d)
252b5132 2560 fprintf (stdout, "D");
40fb9820 2561 if (t->opcode_modifier.w)
252b5132
RH		 2562 fprintf (stdout, "W");
2563 fprintf (stdout, "\n");
09137c09 2564 for (j = 0; j < t->operands; j++)
252b5132 2565 {
09137c09
SP		 2566 fprintf (stdout, " #%d type ", j + 1);
2567 pt (t->operand_types[j]);
252b5132
RH		 2568 fprintf (stdout, "\n");
2569 }
2570}
2571
2572static void
e3bb37b5 2573pe (expressionS *e)
252b5132 2574{
24eab124 2575 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2576 fprintf (stdout, " add_number %ld (%lx)\n",
2577 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2578 if (e->X_add_symbol)
2579 {
2580 fprintf (stdout, " add_symbol ");
2581 ps (e->X_add_symbol);
2582 fprintf (stdout, "\n");
2583 }
2584 if (e->X_op_symbol)
2585 {
2586 fprintf (stdout, " op_symbol ");
2587 ps (e->X_op_symbol);
2588 fprintf (stdout, "\n");
2589 }
2590}
2591
2592static void
e3bb37b5 2593ps (symbolS *s)
252b5132
RH		 2594{
2595 fprintf (stdout, "%s type %s%s",
2596 S_GET_NAME (s),
2597 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2598 segment_name (S_GET_SEGMENT (s)));
2599}
2600
7b81dfbb 2601static struct type_name
252b5132 2602 {
40fb9820
L		 2603 i386_operand_type mask;
2604 const char *name;
252b5132 2605 }
7b81dfbb 2606const type_names[] =
252b5132 2607{
40fb9820
L		 2608 { OPERAND_TYPE_REG8, "r8" },
2609 { OPERAND_TYPE_REG16, "r16" },
2610 { OPERAND_TYPE_REG32, "r32" },
2611 { OPERAND_TYPE_REG64, "r64" },
2612 { OPERAND_TYPE_IMM8, "i8" },
2613 { OPERAND_TYPE_IMM8, "i8s" },
2614 { OPERAND_TYPE_IMM16, "i16" },
2615 { OPERAND_TYPE_IMM32, "i32" },
2616 { OPERAND_TYPE_IMM32S, "i32s" },
2617 { OPERAND_TYPE_IMM64, "i64" },
2618 { OPERAND_TYPE_IMM1, "i1" },
2619 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2620 { OPERAND_TYPE_DISP8, "d8" },
2621 { OPERAND_TYPE_DISP16, "d16" },
2622 { OPERAND_TYPE_DISP32, "d32" },
2623 { OPERAND_TYPE_DISP32S, "d32s" },
2624 { OPERAND_TYPE_DISP64, "d64" },
2625 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2626 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2627 { OPERAND_TYPE_CONTROL, "control reg" },
2628 { OPERAND_TYPE_TEST, "test reg" },
2629 { OPERAND_TYPE_DEBUG, "debug reg" },
2630 { OPERAND_TYPE_FLOATREG, "FReg" },
2631 { OPERAND_TYPE_FLOATACC, "FAcc" },
2632 { OPERAND_TYPE_SREG2, "SReg2" },
2633 { OPERAND_TYPE_SREG3, "SReg3" },
2634 { OPERAND_TYPE_ACC, "Acc" },
2635 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2636 { OPERAND_TYPE_REGMMX, "rMMX" },
2637 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2638 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2639 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2640};
2641
2642static void
40fb9820 2643pt (i386_operand_type t)
252b5132 2644{
40fb9820 2645 unsigned int j;
c6fb90c8 2646 i386_operand_type a;
252b5132 2647
40fb9820 2648 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2649 {
2650 a = operand_type_and (t, type_names[j].mask);
0349dc08 2651 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2652 fprintf (stdout, "%s, ", type_names[j].name);
2653 }
252b5132
RH		 2654 fflush (stdout);
2655}
2656
2657#endif /* DEBUG386 */
2658\f
252b5132 2659static bfd_reloc_code_real_type
3956db08 2660reloc (unsigned int size,
64e74474
AM		 2661 int pcrel,
2662 int sign,
2663 bfd_reloc_code_real_type other)
252b5132 2664{
47926f60 2665 if (other != NO_RELOC)
3956db08 2666 {
91d6fa6a 2667 reloc_howto_type *rel;
3956db08
JB		 2668
2669 if (size == 8)
2670 switch (other)
2671 {
64e74474
AM		 2672 case BFD_RELOC_X86_64_GOT32:
2673 return BFD_RELOC_X86_64_GOT64;
2674 break;
2675 case BFD_RELOC_X86_64_PLTOFF64:
2676 return BFD_RELOC_X86_64_PLTOFF64;
2677 break;
2678 case BFD_RELOC_X86_64_GOTPC32:
2679 other = BFD_RELOC_X86_64_GOTPC64;
2680 break;
2681 case BFD_RELOC_X86_64_GOTPCREL:
2682 other = BFD_RELOC_X86_64_GOTPCREL64;
2683 break;
2684 case BFD_RELOC_X86_64_TPOFF32:
2685 other = BFD_RELOC_X86_64_TPOFF64;
2686 break;
2687 case BFD_RELOC_X86_64_DTPOFF32:
2688 other = BFD_RELOC_X86_64_DTPOFF64;
2689 break;
2690 default:
2691 break;
3956db08 2692 }
e05278af 2693
8ce3d284 2694#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2695 if (other == BFD_RELOC_SIZE32)
2696 {
2697 if (size == 8)
2698 return BFD_RELOC_SIZE64;
2699 if (pcrel)
2700 as_bad (_("there are no pc-relative size relocations"));
2701 }
8ce3d284 2702#endif
8fd4256d 2703
e05278af 2704 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2705 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2706 sign = -1;
2707
91d6fa6a
NC		 2708 rel = bfd_reloc_type_lookup (stdoutput, other);
2709 if (!rel)
3956db08 2710 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2711 else if (size != bfd_get_reloc_size (rel))
3956db08 2712 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2713 bfd_get_reloc_size (rel),
3956db08 2714 size);
91d6fa6a 2715 else if (pcrel && !rel->pc_relative)
3956db08 2716 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2717 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2718 && !sign)
91d6fa6a 2719 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2720 && sign > 0))
3956db08
JB		 2721 as_bad (_("relocated field and relocation type differ in signedness"));
2722 else
2723 return other;
2724 return NO_RELOC;
2725 }
252b5132
RH		 2726
2727 if (pcrel)
2728 {
3e73aa7c 2729 if (!sign)
3956db08 2730 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2731 switch (size)
2732 {
2733 case 1: return BFD_RELOC_8_PCREL;
2734 case 2: return BFD_RELOC_16_PCREL;
2735 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2736 case 8: return BFD_RELOC_64_PCREL;
252b5132 2737 }
3956db08 2738 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2739 }
2740 else
2741 {
3956db08 2742 if (sign > 0)
e5cb08ac 2743 switch (size)
3e73aa7c
JH		 2744 {
2745 case 4: return BFD_RELOC_X86_64_32S;
2746 }
2747 else
2748 switch (size)
2749 {
2750 case 1: return BFD_RELOC_8;
2751 case 2: return BFD_RELOC_16;
2752 case 4: return BFD_RELOC_32;
2753 case 8: return BFD_RELOC_64;
2754 }
3956db08
JB		 2755 as_bad (_("cannot do %s %u byte relocation"),
2756 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2757 }
2758
0cc9e1d3 2759 return NO_RELOC;
252b5132
RH		 2760}
2761
47926f60
KH		 2762/* Here we decide which fixups can be adjusted to make them relative to
2763 the beginning of the section instead of the symbol. Basically we need
2764 to make sure that the dynamic relocations are done correctly, so in
2765 some cases we force the original symbol to be used. */
2766
252b5132 2767int
e3bb37b5 2768tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2769{
6d249963 2770#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2771 if (!IS_ELF)
31312f95
AM		 2772 return 1;
2773
a161fe53
AM		 2774 /* Don't adjust pc-relative references to merge sections in 64-bit
2775 mode. */
2776 if (use_rela_relocations
2777 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2778 && fixP->fx_pcrel)
252b5132 2779 return 0;
31312f95 2780
8d01d9a9
AJ		 2781 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2782 and changed later by validate_fix. */
2783 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2784 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2785 return 0;
2786
8fd4256d
L		 2787 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2788 for size relocations. */
2789 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2790 || fixP->fx_r_type == BFD_RELOC_SIZE64
2791 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2792 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2793 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2794 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2795 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2796 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2797 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2798 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2799 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2800 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2801 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2802 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2803 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2804 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2805 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2806 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2807 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2808 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2809 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2810 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2811 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2812 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2813 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2814 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2815 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2816 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2817 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2818 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2819 return 0;
31312f95 2820#endif
252b5132
RH		 2821 return 1;
2822}
252b5132 2823
b4cac588 2824static int
e3bb37b5 2825intel_float_operand (const char *mnemonic)
252b5132 2826{
9306ca4a
JB		 2827 /* Note that the value returned is meaningful only for opcodes with (memory)
2828 operands, hence the code here is free to improperly handle opcodes that
2829 have no operands (for better performance and smaller code). */
2830
2831 if (mnemonic[0] != 'f')
2832 return 0; /* non-math */
2833
2834 switch (mnemonic[1])
2835 {
2836 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2837 the fs segment override prefix not currently handled because no
2838 call path can make opcodes without operands get here */
2839 case 'i':
2840 return 2 /* integer op */;
2841 case 'l':
2842 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2843 return 3; /* fldcw/fldenv */
2844 break;
2845 case 'n':
2846 if (mnemonic[2] != 'o' /* fnop */)
2847 return 3; /* non-waiting control op */
2848 break;
2849 case 'r':
2850 if (mnemonic[2] == 's')
2851 return 3; /* frstor/frstpm */
2852 break;
2853 case 's':
2854 if (mnemonic[2] == 'a')
2855 return 3; /* fsave */
2856 if (mnemonic[2] == 't')
2857 {
2858 switch (mnemonic[3])
2859 {
2860 case 'c': /* fstcw */
2861 case 'd': /* fstdw */
2862 case 'e': /* fstenv */
2863 case 's': /* fsts[gw] */
2864 return 3;
2865 }
2866 }
2867 break;
2868 case 'x':
2869 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2870 return 0; /* fxsave/fxrstor are not really math ops */
2871 break;
2872 }
252b5132 2873
9306ca4a 2874 return 1;
252b5132
RH		 2875}
2876
c0f3af97
L		 2877/* Build the VEX prefix. */
2878
2879static void
d3ce72d0 2880build_vex_prefix (const insn_template *t)
c0f3af97
L		 2881{
2882 unsigned int register_specifier;
2883 unsigned int implied_prefix;
2884 unsigned int vector_length;
2885
2886 /* Check register specifier. */
2887 if (i.vex.register_specifier)
4c692bc7 2888 register_specifier = ~register_number (i.vex.register_specifier) & 0xf;
c0f3af97
L		 2889 else
2890 register_specifier = 0xf;
2891
fa99fab2
L		 2892 /* Use 2-byte VEX prefix by swappping destination and source
2893 operand. */
2894 if (!i.swap_operand
2895 && i.operands == i.reg_operands
7f399153 2896 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2897 && i.tm.opcode_modifier.s
2898 && i.rex == REX_B)
2899 {
2900 unsigned int xchg = i.operands - 1;
2901 union i386_op temp_op;
2902 i386_operand_type temp_type;
2903
2904 temp_type = i.types[xchg];
2905 i.types[xchg] = i.types[0];
2906 i.types[0] = temp_type;
2907 temp_op = i.op[xchg];
2908 i.op[xchg] = i.op[0];
2909 i.op[0] = temp_op;
2910
9c2799c2 2911 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2912
2913 i.rex = REX_R;
2914 xchg = i.rm.regmem;
2915 i.rm.regmem = i.rm.reg;
2916 i.rm.reg = xchg;
2917
2918 /* Use the next insn. */
2919 i.tm = t[1];
2920 }
2921
539f890d
L		 2922 if (i.tm.opcode_modifier.vex == VEXScalar)
2923 vector_length = avxscalar;
2924 else
2925 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2926
2927 switch ((i.tm.base_opcode >> 8) & 0xff)
2928 {
2929 case 0:
2930 implied_prefix = 0;
2931 break;
2932 case DATA_PREFIX_OPCODE:
2933 implied_prefix = 1;
2934 break;
2935 case REPE_PREFIX_OPCODE:
2936 implied_prefix = 2;
2937 break;
2938 case REPNE_PREFIX_OPCODE:
2939 implied_prefix = 3;
2940 break;
2941 default:
2942 abort ();
2943 }
2944
2945 /* Use 2-byte VEX prefix if possible. */
7f399153 2946 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2947 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2948 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2949 {
2950 /* 2-byte VEX prefix. */
2951 unsigned int r;
2952
2953 i.vex.length = 2;
2954 i.vex.bytes[0] = 0xc5;
2955
2956 /* Check the REX.R bit. */
2957 r = (i.rex & REX_R) ? 0 : 1;
2958 i.vex.bytes[1] = (r << 7
2959 | register_specifier << 3
2960 | vector_length << 2
2961 | implied_prefix);
2962 }
2963 else
2964 {
2965 /* 3-byte VEX prefix. */
2966 unsigned int m, w;
2967
f88c9eb0 2968 i.vex.length = 3;
f88c9eb0 2969
7f399153 2970 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2971 {
7f399153
L		 2972 case VEX0F:
2973 m = 0x1;
80de6e00 2974 i.vex.bytes[0] = 0xc4;
7f399153
L		 2975 break;
2976 case VEX0F38:
2977 m = 0x2;
80de6e00 2978 i.vex.bytes[0] = 0xc4;
7f399153
L		 2979 break;
2980 case VEX0F3A:
2981 m = 0x3;
80de6e00 2982 i.vex.bytes[0] = 0xc4;
7f399153
L		 2983 break;
2984 case XOP08:
5dd85c99
SP		 2985 m = 0x8;
2986 i.vex.bytes[0] = 0x8f;
7f399153
L		 2987 break;
2988 case XOP09:
f88c9eb0
SP		 2989 m = 0x9;
2990 i.vex.bytes[0] = 0x8f;
7f399153
L		 2991 break;
2992 case XOP0A:
f88c9eb0
SP		 2993 m = 0xa;
2994 i.vex.bytes[0] = 0x8f;
7f399153
L		 2995 break;
2996 default:
2997 abort ();
f88c9eb0 2998 }
c0f3af97 2999
c0f3af97
L		 3000 /* The high 3 bits of the second VEX byte are 1's compliment
3001 of RXB bits from REX. */
3002 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3003
3004 /* Check the REX.W bit. */
3005 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 3006 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3007 {
3008 if (w)
3009 abort ();
3010
1ef99a7b 3011 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3012 w = 1;
3013 }
3014
3015 i.vex.bytes[2] = (w << 7
3016 | register_specifier << 3
3017 | vector_length << 2
3018 | implied_prefix);
3019 }
3020}
3021
65da13b5
L		 3022static void
3023process_immext (void)
3024{
3025 expressionS *exp;
3026
4c692bc7
JB		 3027 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3028 && i.operands > 0)
65da13b5 3029 {
4c692bc7
JB		 3030 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3031 with an opcode suffix which is coded in the same place as an
3032 8-bit immediate field would be.
3033 Here we check those operands and remove them afterwards. */
65da13b5
L		 3034 unsigned int x;
3035
3036 for (x = 0; x < i.operands; x++)
4c692bc7 3037 if (register_number (i.op[x].regs) != x)
65da13b5 3038 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3039 register_prefix, i.op[x].regs->reg_name, x + 1,
3040 i.tm.name);
3041
3042 i.operands = 0;
65da13b5
L		 3043 }
3044
c0f3af97 3045 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3046 which is coded in the same place as an 8-bit immediate field
3047 would be. Here we fake an 8-bit immediate operand from the
3048 opcode suffix stored in tm.extension_opcode.
3049
c1e679ec 3050 AVX instructions also use this encoding, for some of
c0f3af97 3051 3 argument instructions. */
65da13b5 3052
9c2799c2 3053 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 3054 && (i.operands <= 2
3055 || (i.tm.opcode_modifier.vex
3056 && i.operands <= 4)));
65da13b5
L		 3057
3058 exp = &im_expressions[i.imm_operands++];
3059 i.op[i.operands].imms = exp;
3060 i.types[i.operands] = imm8;
3061 i.operands++;
3062 exp->X_op = O_constant;
3063 exp->X_add_number = i.tm.extension_opcode;
3064 i.tm.extension_opcode = None;
3065}
3066
42164a71
L		 3067
3068static int
3069check_hle (void)
3070{
3071 switch (i.tm.opcode_modifier.hleprefixok)
3072 {
3073 default:
3074 abort ();
82c2def5 3075 case HLEPrefixNone:
165de32a
L		 3076 as_bad (_("invalid instruction `%s' after `%s'"),
3077 i.tm.name, i.hle_prefix);
42164a71 3078 return 0;
82c2def5 3079 case HLEPrefixLock:
42164a71
L		 3080 if (i.prefix[LOCK_PREFIX])
3081 return 1;
165de32a 3082 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3083 return 0;
82c2def5 3084 case HLEPrefixAny:
42164a71 3085 return 1;
82c2def5 3086 case HLEPrefixRelease:
42164a71
L		 3087 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3088 {
3089 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3090 i.tm.name);
3091 return 0;
3092 }
3093 if (i.mem_operands == 0
3094 || !operand_type_check (i.types[i.operands - 1], anymem))
3095 {
3096 as_bad (_("memory destination needed for instruction `%s'"
3097 " after `xrelease'"), i.tm.name);
3098 return 0;
3099 }
3100 return 1;
3101 }
3102}
3103
252b5132
RH		 3104/* This is the guts of the machine-dependent assembler. LINE points to a
3105 machine dependent instruction. This function is supposed to emit
3106 the frags/bytes it assembles to. */
3107
3108void
65da13b5 3109md_assemble (char *line)
252b5132 3110{
40fb9820 3111 unsigned int j;
252b5132 3112 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3113 const insn_template *t;
252b5132 3114
47926f60 3115 /* Initialize globals. */
252b5132
RH		 3116 memset (&i, '\0', sizeof (i));
3117 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3118 i.reloc[j] = NO_RELOC;
252b5132
RH		 3119 memset (disp_expressions, '\0', sizeof (disp_expressions));
3120 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3121 save_stack_p = save_stack;
252b5132
RH		 3122
3123 /* First parse an instruction mnemonic & call i386_operand for the operands.
3124 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3125 start of a (possibly prefixed) mnemonic. */
252b5132 3126
29b0f896
AM		 3127 line = parse_insn (line, mnemonic);
3128 if (line == NULL)
3129 return;
252b5132 3130
29b0f896 3131 line = parse_operands (line, mnemonic);
ee86248c 3132 this_operand = -1;
29b0f896
AM		 3133 if (line == NULL)
3134 return;
252b5132 3135
29b0f896
AM		 3136 /* Now we've parsed the mnemonic into a set of templates, and have the
3137 operands at hand. */
3138
3139 /* All intel opcodes have reversed operands except for "bound" and
3140 "enter". We also don't reverse intersegment "jmp" and "call"
3141 instructions with 2 immediate operands so that the immediate segment
050dfa73 3142 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3143 if (intel_syntax
3144 && i.operands > 1
29b0f896 3145 && (strcmp (mnemonic, "bound") != 0)
30123838 3146 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3147 && !(operand_type_check (i.types[0], imm)
3148 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3149 swap_operands ();
3150
ec56d5c0
JB		 3151 /* The order of the immediates should be reversed
3152 for 2 immediates extrq and insertq instructions */
3153 if (i.imm_operands == 2
3154 && (strcmp (mnemonic, "extrq") == 0
3155 || strcmp (mnemonic, "insertq") == 0))
3156 swap_2_operands (0, 1);
3157
29b0f896
AM		 3158 if (i.imm_operands)
3159 optimize_imm ();
3160
b300c311
L		 3161 /* Don't optimize displacement for movabs since it only takes 64bit
3162 displacement. */
3163 if (i.disp_operands
a501d77e 3164 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3165 && (flag_code != CODE_64BIT
3166 || strcmp (mnemonic, "movabs") != 0))
3167 optimize_disp ();
29b0f896
AM		 3168
3169 /* Next, we find a template that matches the given insn,
3170 making sure the overlap of the given operands types is consistent
3171 with the template operand types. */
252b5132 3172
fa99fab2 3173 if (!(t = match_template ()))
29b0f896 3174 return;
252b5132 3175
7bab8ab5 3176 if (sse_check != check_none
81f8a913 3177 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3178 && (i.tm.cpu_flags.bitfield.cpusse
3179 || i.tm.cpu_flags.bitfield.cpusse2
3180 || i.tm.cpu_flags.bitfield.cpusse3
3181 || i.tm.cpu_flags.bitfield.cpussse3
3182 || i.tm.cpu_flags.bitfield.cpusse4_1
3183 || i.tm.cpu_flags.bitfield.cpusse4_2))
3184 {
7bab8ab5 3185 (sse_check == check_warning
daf50ae7
L		 3186 ? as_warn
3187 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3188 }
3189
321fd21e
L		 3190 /* Zap movzx and movsx suffix. The suffix has been set from
3191 "word ptr" or "byte ptr" on the source operand in Intel syntax
3192 or extracted from mnemonic in AT&T syntax. But we'll use
3193 the destination register to choose the suffix for encoding. */
3194 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3195 {
321fd21e
L		 3196 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3197 there is no suffix, the default will be byte extension. */
3198 if (i.reg_operands != 2
3199 && !i.suffix
7ab9ffdd 3200 && intel_syntax)
321fd21e
L		 3201 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3202
3203 i.suffix = 0;
cd61ebfe 3204 }
24eab124 3205
40fb9820 3206 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3207 if (!add_prefix (FWAIT_OPCODE))
3208 return;
252b5132 3209
d5de92cf
L		 3210 /* Check if REP prefix is OK. */
3211 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3212 {
3213 as_bad (_("invalid instruction `%s' after `%s'"),
3214 i.tm.name, i.rep_prefix);
3215 return;
3216 }
3217
c1ba0266
L		 3218 /* Check for lock without a lockable instruction. Destination operand
3219 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3220 if (i.prefix[LOCK_PREFIX]
3221 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3222 || i.mem_operands == 0
3223 || (i.tm.base_opcode != 0x86
3224 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3225 {
3226 as_bad (_("expecting lockable instruction after `lock'"));
3227 return;
3228 }
3229
42164a71 3230 /* Check if HLE prefix is OK. */
165de32a 3231 if (i.hle_prefix && !check_hle ())
42164a71
L		 3232 return;
3233
29b0f896 3234 /* Check string instruction segment overrides. */
40fb9820 3235 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3236 {
3237 if (!check_string ())
5dd0794d 3238 return;
fc0763e6 3239 i.disp_operands = 0;
29b0f896 3240 }
5dd0794d 3241
29b0f896
AM		 3242 if (!process_suffix ())
3243 return;
e413e4e9 3244
bc0844ae
L		 3245 /* Update operand types. */
3246 for (j = 0; j < i.operands; j++)
3247 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3248
29b0f896
AM		 3249 /* Make still unresolved immediate matches conform to size of immediate
3250 given in i.suffix. */
3251 if (!finalize_imm ())
3252 return;
252b5132 3253
40fb9820 3254 if (i.types[0].bitfield.imm1)
29b0f896 3255 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3256
9afe6eb8
L		 3257 /* We only need to check those implicit registers for instructions
3258 with 3 operands or less. */
3259 if (i.operands <= 3)
3260 for (j = 0; j < i.operands; j++)
3261 if (i.types[j].bitfield.inoutportreg
3262 || i.types[j].bitfield.shiftcount
3263 || i.types[j].bitfield.acc
3264 || i.types[j].bitfield.floatacc)
3265 i.reg_operands--;
40fb9820 3266
c0f3af97
L		 3267 /* ImmExt should be processed after SSE2AVX. */
3268 if (!i.tm.opcode_modifier.sse2avx
3269 && i.tm.opcode_modifier.immext)
65da13b5 3270 process_immext ();
252b5132 3271
29b0f896
AM		 3272 /* For insns with operands there are more diddles to do to the opcode. */
3273 if (i.operands)
3274 {
3275 if (!process_operands ())
3276 return;
3277 }
40fb9820 3278 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3279 {
3280 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3281 as_warn (_("translating to `%sp'"), i.tm.name);
3282 }
252b5132 3283
c0f3af97 3284 if (i.tm.opcode_modifier.vex)
fa99fab2 3285 build_vex_prefix (t);
c0f3af97 3286
5dd85c99
SP		 3287 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3288 instructions may define INT_OPCODE as well, so avoid this corner
3289 case for those instructions that use MODRM. */
3290 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3291 && !i.tm.opcode_modifier.modrm
3292 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3293 {
3294 i.tm.base_opcode = INT3_OPCODE;
3295 i.imm_operands = 0;
3296 }
252b5132 3297
40fb9820
L		 3298 if ((i.tm.opcode_modifier.jump
3299 || i.tm.opcode_modifier.jumpbyte
3300 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3301 && i.op[0].disps->X_op == O_constant)
3302 {
3303 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3304 the absolute address given by the constant. Since ix86 jumps and
3305 calls are pc relative, we need to generate a reloc. */
3306 i.op[0].disps->X_add_symbol = &abs_symbol;
3307 i.op[0].disps->X_op = O_symbol;
3308 }
252b5132 3309
40fb9820 3310 if (i.tm.opcode_modifier.rex64)
161a04f6 3311 i.rex |= REX_W;
252b5132 3312
29b0f896
AM		 3313 /* For 8 bit registers we need an empty rex prefix. Also if the
3314 instruction already has a prefix, we need to convert old
3315 registers to new ones. */
773f551c 3316
40fb9820 3317 if ((i.types[0].bitfield.reg8
29b0f896 3318 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3319 || (i.types[1].bitfield.reg8
29b0f896 3320 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3321 || ((i.types[0].bitfield.reg8
3322 || i.types[1].bitfield.reg8)
29b0f896
AM		 3323 && i.rex != 0))
3324 {
3325 int x;
726c5dcd 3326
29b0f896
AM		 3327 i.rex |= REX_OPCODE;
3328 for (x = 0; x < 2; x++)
3329 {
3330 /* Look for 8 bit operand that uses old registers. */
40fb9820 3331 if (i.types[x].bitfield.reg8
29b0f896 3332 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3333 {
29b0f896
AM		 3334 /* In case it is "hi" register, give up. */
3335 if (i.op[x].regs->reg_num > 3)
a540244d 3336 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3337 "instruction requiring REX prefix."),
a540244d 3338 register_prefix, i.op[x].regs->reg_name);
773f551c 3339
29b0f896
AM		 3340 /* Otherwise it is equivalent to the extended register.
3341 Since the encoding doesn't change this is merely
3342 cosmetic cleanup for debug output. */
3343
3344 i.op[x].regs = i.op[x].regs + 8;
773f551c 3345 }
29b0f896
AM		 3346 }
3347 }
773f551c 3348
7ab9ffdd 3349 if (i.rex != 0)
29b0f896
AM		 3350 add_prefix (REX_OPCODE | i.rex);
3351
3352 /* We are ready to output the insn. */
3353 output_insn ();
3354}
3355
3356static char *
e3bb37b5 3357parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3358{
3359 char *l = line;
3360 char *token_start = l;
3361 char *mnem_p;
5c6af06e 3362 int supported;
d3ce72d0 3363 const insn_template *t;
b6169b20 3364 char *dot_p = NULL;
29b0f896 3365
29b0f896
AM		 3366 while (1)
3367 {
3368 mnem_p = mnemonic;
3369 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3370 {
b6169b20
L		 3371 if (*mnem_p == '.')
3372 dot_p = mnem_p;
29b0f896
AM		 3373 mnem_p++;
3374 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3375 {
29b0f896
AM		 3376 as_bad (_("no such instruction: `%s'"), token_start);
3377 return NULL;
3378 }
3379 l++;
3380 }
3381 if (!is_space_char (*l)
3382 && *l != END_OF_INSN
e44823cf
JB		 3383 && (intel_syntax
3384 || (*l != PREFIX_SEPARATOR
3385 && *l != ',')))
29b0f896
AM		 3386 {
3387 as_bad (_("invalid character %s in mnemonic"),
3388 output_invalid (*l));
3389 return NULL;
3390 }
3391 if (token_start == l)
3392 {
e44823cf 3393 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3394 as_bad (_("expecting prefix; got nothing"));
3395 else
3396 as_bad (_("expecting mnemonic; got nothing"));
3397 return NULL;
3398 }
45288df1 3399
29b0f896 3400 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3401 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3402
29b0f896
AM		 3403 if (*l != END_OF_INSN
3404 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3405 && current_templates
40fb9820 3406 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3407 {
c6fb90c8 3408 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3409 {
3410 as_bad ((flag_code != CODE_64BIT
3411 ? _("`%s' is only supported in 64-bit mode")
3412 : _("`%s' is not supported in 64-bit mode")),
3413 current_templates->start->name);
3414 return NULL;
3415 }
29b0f896
AM		 3416 /* If we are in 16-bit mode, do not allow addr16 or data16.
3417 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3418 if ((current_templates->start->opcode_modifier.size16
3419 || current_templates->start->opcode_modifier.size32)
29b0f896 3420 && flag_code != CODE_64BIT
40fb9820 3421 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3422 ^ (flag_code == CODE_16BIT)))
3423 {
3424 as_bad (_("redundant %s prefix"),
3425 current_templates->start->name);
3426 return NULL;
45288df1 3427 }
29b0f896
AM		 3428 /* Add prefix, checking for repeated prefixes. */
3429 switch (add_prefix (current_templates->start->base_opcode))
3430 {
c32fa91d 3431 case PREFIX_EXIST:
29b0f896 3432 return NULL;
c32fa91d 3433 case PREFIX_REP:
42164a71 3434 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3435 i.hle_prefix = current_templates->start->name;
42164a71 3436 else
d5de92cf 3437 i.rep_prefix = current_templates->start->name;
29b0f896 3438 break;
c32fa91d
L		 3439 default:
3440 break;
29b0f896
AM		 3441 }
3442 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3443 token_start = ++l;
3444 }
3445 else
3446 break;
3447 }
45288df1 3448
30a55f88 3449 if (!current_templates)
b6169b20 3450 {
f8a5c266
L		 3451 /* Check if we should swap operand or force 32bit displacement in
3452 encoding. */
30a55f88
L		 3453 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3454 i.swap_operand = 1;
8d63c93e 3455 else if (mnem_p - 3 == dot_p
a501d77e
L		 3456 && dot_p[1] == 'd'
3457 && dot_p[2] == '8')
3458 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3459 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3460 && dot_p[1] == 'd'
3461 && dot_p[2] == '3'
3462 && dot_p[3] == '2')
a501d77e 3463 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3464 else
3465 goto check_suffix;
3466 mnem_p = dot_p;
3467 *dot_p = '\0';
d3ce72d0 3468 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3469 }
3470
29b0f896
AM		 3471 if (!current_templates)
3472 {
b6169b20 3473check_suffix:
29b0f896
AM		 3474 /* See if we can get a match by trimming off a suffix. */
3475 switch (mnem_p[-1])
3476 {
3477 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3478 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3479 i.suffix = SHORT_MNEM_SUFFIX;
3480 else
29b0f896
AM		 3481 case BYTE_MNEM_SUFFIX:
3482 case QWORD_MNEM_SUFFIX:
3483 i.suffix = mnem_p[-1];
3484 mnem_p[-1] = '\0';
d3ce72d0
NC		 3485 current_templates = (const templates *) hash_find (op_hash,
3486 mnemonic);
29b0f896
AM		 3487 break;
3488 case SHORT_MNEM_SUFFIX:
3489 case LONG_MNEM_SUFFIX:
3490 if (!intel_syntax)
3491 {
3492 i.suffix = mnem_p[-1];
3493 mnem_p[-1] = '\0';
d3ce72d0
NC		 3494 current_templates = (const templates *) hash_find (op_hash,
3495 mnemonic);
29b0f896
AM		 3496 }
3497 break;
252b5132 3498
29b0f896
AM		 3499 /* Intel Syntax. */
3500 case 'd':
3501 if (intel_syntax)
3502 {
9306ca4a 3503 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3504 i.suffix = SHORT_MNEM_SUFFIX;
3505 else
3506 i.suffix = LONG_MNEM_SUFFIX;
3507 mnem_p[-1] = '\0';
d3ce72d0
NC		 3508 current_templates = (const templates *) hash_find (op_hash,
3509 mnemonic);
29b0f896
AM		 3510 }
3511 break;
3512 }
3513 if (!current_templates)
3514 {
3515 as_bad (_("no such instruction: `%s'"), token_start);
3516 return NULL;
3517 }
3518 }
252b5132 3519
40fb9820
L		 3520 if (current_templates->start->opcode_modifier.jump
3521 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3522 {
3523 /* Check for a branch hint. We allow ",pt" and ",pn" for
3524 predict taken and predict not taken respectively.
3525 I'm not sure that branch hints actually do anything on loop
3526 and jcxz insns (JumpByte) for current Pentium4 chips. They
3527 may work in the future and it doesn't hurt to accept them
3528 now. */
3529 if (l[0] == ',' && l[1] == 'p')
3530 {
3531 if (l[2] == 't')
3532 {
3533 if (!add_prefix (DS_PREFIX_OPCODE))
3534 return NULL;
3535 l += 3;
3536 }
3537 else if (l[2] == 'n')
3538 {
3539 if (!add_prefix (CS_PREFIX_OPCODE))
3540 return NULL;
3541 l += 3;
3542 }
3543 }
3544 }
3545 /* Any other comma loses. */
3546 if (*l == ',')
3547 {
3548 as_bad (_("invalid character %s in mnemonic"),
3549 output_invalid (*l));
3550 return NULL;
3551 }
252b5132 3552
29b0f896 3553 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3554 supported = 0;
3555 for (t = current_templates->start; t < current_templates->end; ++t)
3556 {
c0f3af97
L		 3557 supported |= cpu_flags_match (t);
3558 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3559 goto skip;
5c6af06e 3560 }
3629bb00 3561
c0f3af97 3562 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3563 {
3564 as_bad (flag_code == CODE_64BIT
3565 ? _("`%s' is not supported in 64-bit mode")
3566 : _("`%s' is only supported in 64-bit mode"),
3567 current_templates->start->name);
3568 return NULL;
3569 }
c0f3af97 3570 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3571 {
3629bb00 3572 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3573 current_templates->start->name,
41aacd83 3574 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3575 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3576 return NULL;
29b0f896 3577 }
3629bb00
L		 3578
3579skip:
3580 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3581 && (flag_code != CODE_16BIT))
29b0f896
AM		 3582 {
3583 as_warn (_("use .code16 to ensure correct addressing mode"));
3584 }
252b5132 3585
29b0f896
AM		 3586 return l;
3587}
252b5132 3588
29b0f896 3589static char *
e3bb37b5 3590parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3591{
3592 char *token_start;
3138f287 3593
29b0f896
AM		 3594 /* 1 if operand is pending after ','. */
3595 unsigned int expecting_operand = 0;
252b5132 3596
29b0f896
AM		 3597 /* Non-zero if operand parens not balanced. */
3598 unsigned int paren_not_balanced;
3599
3600 while (*l != END_OF_INSN)
3601 {
3602 /* Skip optional white space before operand. */
3603 if (is_space_char (*l))
3604 ++l;
3605 if (!is_operand_char (*l) && *l != END_OF_INSN)
3606 {
3607 as_bad (_("invalid character %s before operand %d"),
3608 output_invalid (*l),
3609 i.operands + 1);
3610 return NULL;
3611 }
3612 token_start = l; /* after white space */
3613 paren_not_balanced = 0;
3614 while (paren_not_balanced || *l != ',')
3615 {
3616 if (*l == END_OF_INSN)
3617 {
3618 if (paren_not_balanced)
3619 {
3620 if (!intel_syntax)
3621 as_bad (_("unbalanced parenthesis in operand %d."),
3622 i.operands + 1);
3623 else
3624 as_bad (_("unbalanced brackets in operand %d."),
3625 i.operands + 1);
3626 return NULL;
3627 }
3628 else
3629 break; /* we are done */
3630 }
3631 else if (!is_operand_char (*l) && !is_space_char (*l))
3632 {
3633 as_bad (_("invalid character %s in operand %d"),
3634 output_invalid (*l),
3635 i.operands + 1);
3636 return NULL;
3637 }
3638 if (!intel_syntax)
3639 {
3640 if (*l == '(')
3641 ++paren_not_balanced;
3642 if (*l == ')')
3643 --paren_not_balanced;
3644 }
3645 else
3646 {
3647 if (*l == '[')
3648 ++paren_not_balanced;
3649 if (*l == ']')
3650 --paren_not_balanced;
3651 }
3652 l++;
3653 }
3654 if (l != token_start)
3655 { /* Yes, we've read in another operand. */
3656 unsigned int operand_ok;
3657 this_operand = i.operands++;
7d5e4556 3658 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3659 if (i.operands > MAX_OPERANDS)
3660 {
3661 as_bad (_("spurious operands; (%d operands/instruction max)"),
3662 MAX_OPERANDS);
3663 return NULL;
3664 }
3665 /* Now parse operand adding info to 'i' as we go along. */
3666 END_STRING_AND_SAVE (l);
3667
3668 if (intel_syntax)
3669 operand_ok =
3670 i386_intel_operand (token_start,
3671 intel_float_operand (mnemonic));
3672 else
a7619375 3673 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3674
3675 RESTORE_END_STRING (l);
3676 if (!operand_ok)
3677 return NULL;
3678 }
3679 else
3680 {
3681 if (expecting_operand)
3682 {
3683 expecting_operand_after_comma:
3684 as_bad (_("expecting operand after ','; got nothing"));
3685 return NULL;
3686 }
3687 if (*l == ',')
3688 {
3689 as_bad (_("expecting operand before ','; got nothing"));
3690 return NULL;
3691 }
3692 }
7f3f1ea2 3693
29b0f896
AM		 3694 /* Now *l must be either ',' or END_OF_INSN. */
3695 if (*l == ',')
3696 {
3697 if (*++l == END_OF_INSN)
3698 {
3699 /* Just skip it, if it's \n complain. */
3700 goto expecting_operand_after_comma;
3701 }
3702 expecting_operand = 1;
3703 }
3704 }
3705 return l;
3706}
7f3f1ea2 3707
050dfa73 3708static void
4d456e3d 3709swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3710{
3711 union i386_op temp_op;
40fb9820 3712 i386_operand_type temp_type;
050dfa73 3713 enum bfd_reloc_code_real temp_reloc;
4eed87de 3714
050dfa73
MM		 3715 temp_type = i.types[xchg2];
3716 i.types[xchg2] = i.types[xchg1];
3717 i.types[xchg1] = temp_type;
3718 temp_op = i.op[xchg2];
3719 i.op[xchg2] = i.op[xchg1];
3720 i.op[xchg1] = temp_op;
3721 temp_reloc = i.reloc[xchg2];
3722 i.reloc[xchg2] = i.reloc[xchg1];
3723 i.reloc[xchg1] = temp_reloc;
3724}
3725
29b0f896 3726static void
e3bb37b5 3727swap_operands (void)
29b0f896 3728{
b7c61d9a 3729 switch (i.operands)
050dfa73 3730 {
c0f3af97 3731 case 5:
b7c61d9a 3732 case 4:
4d456e3d 3733 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3734 case 3:
3735 case 2:
4d456e3d 3736 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3737 break;
3738 default:
3739 abort ();
29b0f896 3740 }
29b0f896
AM		 3741
3742 if (i.mem_operands == 2)
3743 {
3744 const seg_entry *temp_seg;
3745 temp_seg = i.seg[0];
3746 i.seg[0] = i.seg[1];
3747 i.seg[1] = temp_seg;
3748 }
3749}
252b5132 3750
29b0f896
AM		 3751/* Try to ensure constant immediates are represented in the smallest
3752 opcode possible. */
3753static void
e3bb37b5 3754optimize_imm (void)
29b0f896
AM		 3755{
3756 char guess_suffix = 0;
3757 int op;
252b5132 3758
29b0f896
AM		 3759 if (i.suffix)
3760 guess_suffix = i.suffix;
3761 else if (i.reg_operands)
3762 {
3763 /* Figure out a suffix from the last register operand specified.
3764 We can't do this properly yet, ie. excluding InOutPortReg,
3765 but the following works for instructions with immediates.
3766 In any case, we can't set i.suffix yet. */
3767 for (op = i.operands; --op >= 0;)
40fb9820 3768 if (i.types[op].bitfield.reg8)
7ab9ffdd 3769 {
40fb9820
L		 3770 guess_suffix = BYTE_MNEM_SUFFIX;
3771 break;
3772 }
3773 else if (i.types[op].bitfield.reg16)
252b5132 3774 {
40fb9820
L		 3775 guess_suffix = WORD_MNEM_SUFFIX;
3776 break;
3777 }
3778 else if (i.types[op].bitfield.reg32)
3779 {
3780 guess_suffix = LONG_MNEM_SUFFIX;
3781 break;
3782 }
3783 else if (i.types[op].bitfield.reg64)
3784 {
3785 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3786 break;
252b5132 3787 }
29b0f896
AM		 3788 }
3789 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3790 guess_suffix = WORD_MNEM_SUFFIX;
3791
3792 for (op = i.operands; --op >= 0;)
40fb9820 3793 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3794 {
3795 switch (i.op[op].imms->X_op)
252b5132 3796 {
29b0f896
AM		 3797 case O_constant:
3798 /* If a suffix is given, this operand may be shortened. */
3799 switch (guess_suffix)
252b5132 3800 {
29b0f896 3801 case LONG_MNEM_SUFFIX:
40fb9820
L		 3802 i.types[op].bitfield.imm32 = 1;
3803 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3804 break;
3805 case WORD_MNEM_SUFFIX:
40fb9820
L		 3806 i.types[op].bitfield.imm16 = 1;
3807 i.types[op].bitfield.imm32 = 1;
3808 i.types[op].bitfield.imm32s = 1;
3809 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3810 break;
3811 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3812 i.types[op].bitfield.imm8 = 1;
3813 i.types[op].bitfield.imm8s = 1;
3814 i.types[op].bitfield.imm16 = 1;
3815 i.types[op].bitfield.imm32 = 1;
3816 i.types[op].bitfield.imm32s = 1;
3817 i.types[op].bitfield.imm64 = 1;
29b0f896 3818 break;
252b5132 3819 }
252b5132 3820
29b0f896
AM		 3821 /* If this operand is at most 16 bits, convert it
3822 to a signed 16 bit number before trying to see
3823 whether it will fit in an even smaller size.
3824 This allows a 16-bit operand such as $0xffe0 to
3825 be recognised as within Imm8S range. */
40fb9820 3826 if ((i.types[op].bitfield.imm16)
29b0f896 3827 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3828 {
29b0f896
AM		 3829 i.op[op].imms->X_add_number =
3830 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3831 }
40fb9820 3832 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3833 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3834 == 0))
3835 {
3836 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3837 ^ ((offsetT) 1 << 31))
3838 - ((offsetT) 1 << 31));
3839 }
40fb9820 3840 i.types[op]
c6fb90c8
L		 3841 = operand_type_or (i.types[op],
3842 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3843
29b0f896
AM		 3844 /* We must avoid matching of Imm32 templates when 64bit
3845 only immediate is available. */
3846 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3847 i.types[op].bitfield.imm32 = 0;
29b0f896 3848 break;
252b5132 3849
29b0f896
AM		 3850 case O_absent:
3851 case O_register:
3852 abort ();
3853
3854 /* Symbols and expressions. */
3855 default:
9cd96992
JB		 3856 /* Convert symbolic operand to proper sizes for matching, but don't
3857 prevent matching a set of insns that only supports sizes other
3858 than those matching the insn suffix. */
3859 {
40fb9820 3860 i386_operand_type mask, allowed;
d3ce72d0 3861 const insn_template *t;
9cd96992 3862
0dfbf9d7
L		 3863 operand_type_set (&mask, 0);
3864 operand_type_set (&allowed, 0);
40fb9820 3865
4eed87de
AM		 3866 for (t = current_templates->start;
3867 t < current_templates->end;
3868 ++t)
c6fb90c8
L		 3869 allowed = operand_type_or (allowed,
3870 t->operand_types[op]);
9cd96992
JB		 3871 switch (guess_suffix)
3872 {
3873 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3874 mask.bitfield.imm64 = 1;
3875 mask.bitfield.imm32s = 1;
9cd96992
JB		 3876 break;
3877 case LONG_MNEM_SUFFIX:
40fb9820 3878 mask.bitfield.imm32 = 1;
9cd96992
JB		 3879 break;
3880 case WORD_MNEM_SUFFIX:
40fb9820 3881 mask.bitfield.imm16 = 1;
9cd96992
JB		 3882 break;
3883 case BYTE_MNEM_SUFFIX:
40fb9820 3884 mask.bitfield.imm8 = 1;
9cd96992
JB		 3885 break;
3886 default:
9cd96992
JB		 3887 break;
3888 }
c6fb90c8 3889 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3890 if (!operand_type_all_zero (&allowed))
c6fb90c8 3891 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3892 }
29b0f896 3893 break;
252b5132 3894 }
29b0f896
AM		 3895 }
3896}
47926f60 3897
29b0f896
AM		 3898/* Try to use the smallest displacement type too. */
3899static void
e3bb37b5 3900optimize_disp (void)
29b0f896
AM		 3901{
3902 int op;
3e73aa7c 3903
29b0f896 3904 for (op = i.operands; --op >= 0;)
40fb9820 3905 if (operand_type_check (i.types[op], disp))
252b5132 3906 {
b300c311 3907 if (i.op[op].disps->X_op == O_constant)
252b5132 3908 {
91d6fa6a 3909 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3910
40fb9820 3911 if (i.types[op].bitfield.disp16
91d6fa6a 3912 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3913 {
3914 /* If this operand is at most 16 bits, convert
3915 to a signed 16 bit number and don't use 64bit
3916 displacement. */
91d6fa6a 3917 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3918 i.types[op].bitfield.disp64 = 0;
b300c311 3919 }
40fb9820 3920 if (i.types[op].bitfield.disp32
91d6fa6a 3921 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3922 {
3923 /* If this operand is at most 32 bits, convert
3924 to a signed 32 bit number and don't use 64bit
3925 displacement. */
91d6fa6a
NC		 3926 op_disp &= (((offsetT) 2 << 31) - 1);
3927 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3928 i.types[op].bitfield.disp64 = 0;
b300c311 3929 }
91d6fa6a 3930 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3931 {
40fb9820
L		 3932 i.types[op].bitfield.disp8 = 0;
3933 i.types[op].bitfield.disp16 = 0;
3934 i.types[op].bitfield.disp32 = 0;
3935 i.types[op].bitfield.disp32s = 0;
3936 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3937 i.op[op].disps = 0;
3938 i.disp_operands--;
3939 }
3940 else if (flag_code == CODE_64BIT)
3941 {
91d6fa6a 3942 if (fits_in_signed_long (op_disp))
28a9d8f5 3943 {
40fb9820
L		 3944 i.types[op].bitfield.disp64 = 0;
3945 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3946 }
0e1147d9 3947 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3948 && fits_in_unsigned_long (op_disp))
40fb9820 3949 i.types[op].bitfield.disp32 = 1;
b300c311 3950 }
40fb9820
L		 3951 if ((i.types[op].bitfield.disp32
3952 || i.types[op].bitfield.disp32s
3953 || i.types[op].bitfield.disp16)
91d6fa6a 3954 && fits_in_signed_byte (op_disp))
40fb9820 3955 i.types[op].bitfield.disp8 = 1;
252b5132 3956 }
67a4f2b7
AO		 3957 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3958 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3959 {
3960 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3961 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3962 i.types[op].bitfield.disp8 = 0;
3963 i.types[op].bitfield.disp16 = 0;
3964 i.types[op].bitfield.disp32 = 0;
3965 i.types[op].bitfield.disp32s = 0;
3966 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3967 }
3968 else
b300c311 3969 /* We only support 64bit displacement on constants. */
40fb9820 3970 i.types[op].bitfield.disp64 = 0;
252b5132 3971 }
29b0f896
AM		 3972}
3973
6c30d220
L		 3974/* Check if operands are valid for the instruction. */
3975
3976static int
3977check_VecOperands (const insn_template *t)
3978{
3979 /* Without VSIB byte, we can't have a vector register for index. */
3980 if (!t->opcode_modifier.vecsib
3981 && i.index_reg
3982 && (i.index_reg->reg_type.bitfield.regxmm
3983 || i.index_reg->reg_type.bitfield.regymm))
3984 {
3985 i.error = unsupported_vector_index_register;
3986 return 1;
3987 }
3988
7bab8ab5
JB		 3989 /* For VSIB byte, we need a vector register for index, and all vector
3990 registers must be distinct. */
3991 if (t->opcode_modifier.vecsib)
3992 {
3993 if (!i.index_reg
6c30d220
L		 3994 || !((t->opcode_modifier.vecsib == VecSIB128
3995 && i.index_reg->reg_type.bitfield.regxmm)
3996 || (t->opcode_modifier.vecsib == VecSIB256
7bab8ab5
JB		 3997 && i.index_reg->reg_type.bitfield.regymm)))
3998 {
3999 i.error = invalid_vsib_address;
4000 return 1;
4001 }
4002
4003 gas_assert (i.reg_operands == 2);
4004 gas_assert (i.types[0].bitfield.regxmm
4005 || i.types[0].bitfield.regymm);
4006 gas_assert (i.types[2].bitfield.regxmm
4007 || i.types[2].bitfield.regymm);
4008
4009 if (operand_check == check_none)
4010 return 0;
4011 if (register_number (i.op[0].regs) != register_number (i.index_reg)
4012 && register_number (i.op[2].regs) != register_number (i.index_reg)
4013 && register_number (i.op[0].regs) != register_number (i.op[2].regs))
4014 return 0;
4015 if (operand_check == check_error)
4016 {
4017 i.error = invalid_vector_register_set;
4018 return 1;
4019 }
4020 as_warn (_("mask, index, and destination registers should be distinct"));
6c30d220
L		 4021 }
4022
4023 return 0;
4024}
4025
43f3e2ee 4026/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4027 operand types. */
4028
4029static int
4030VEX_check_operands (const insn_template *t)
4031{
4032 if (!t->opcode_modifier.vex)
4033 return 0;
4034
4035 /* Only check VEX_Imm4, which must be the first operand. */
4036 if (t->operand_types[0].bitfield.vec_imm4)
4037 {
4038 if (i.op[0].imms->X_op != O_constant
4039 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4040 {
a65babc9 4041 i.error = bad_imm4;
891edac4
L		 4042 return 1;
4043 }
a683cc34
SP		 4044
4045 /* Turn off Imm8 so that update_imm won't complain. */
4046 i.types[0] = vec_imm4;
4047 }
4048
4049 return 0;
4050}
4051
d3ce72d0 4052static const insn_template *
e3bb37b5 4053match_template (void)
29b0f896
AM		 4054{
4055 /* Points to template once we've found it. */
d3ce72d0 4056 const insn_template *t;
40fb9820 4057 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4058 i386_operand_type overlap4;
29b0f896 4059 unsigned int found_reverse_match;
40fb9820
L		 4060 i386_opcode_modifier suffix_check;
4061 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4062 int addr_prefix_disp;
a5c311ca 4063 unsigned int j;
3629bb00 4064 unsigned int found_cpu_match;
45664ddb 4065 unsigned int check_register;
5614d22c 4066 enum i386_error specific_error = 0;
29b0f896 4067
c0f3af97
L		 4068#if MAX_OPERANDS != 5
4069# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4070#endif
4071
29b0f896 4072 found_reverse_match = 0;
539e75ad 4073 addr_prefix_disp = -1;
40fb9820
L		 4074
4075 memset (&suffix_check, 0, sizeof (suffix_check));
4076 if (i.suffix == BYTE_MNEM_SUFFIX)
4077 suffix_check.no_bsuf = 1;
4078 else if (i.suffix == WORD_MNEM_SUFFIX)
4079 suffix_check.no_wsuf = 1;
4080 else if (i.suffix == SHORT_MNEM_SUFFIX)
4081 suffix_check.no_ssuf = 1;
4082 else if (i.suffix == LONG_MNEM_SUFFIX)
4083 suffix_check.no_lsuf = 1;
4084 else if (i.suffix == QWORD_MNEM_SUFFIX)
4085 suffix_check.no_qsuf = 1;
4086 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4087 suffix_check.no_ldsuf = 1;
29b0f896 4088
01559ecc
L		 4089 /* Must have right number of operands. */
4090 i.error = number_of_operands_mismatch;
4091
45aa61fe 4092 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4093 {
539e75ad
L		 4094 addr_prefix_disp = -1;
4095
29b0f896
AM		 4096 if (i.operands != t->operands)
4097 continue;
4098
50aecf8c 4099 /* Check processor support. */
a65babc9 4100 i.error = unsupported;
c0f3af97
L		 4101 found_cpu_match = (cpu_flags_match (t)
4102 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4103 if (!found_cpu_match)
4104 continue;
4105
e1d4d893 4106 /* Check old gcc support. */
a65babc9 4107 i.error = old_gcc_only;
e1d4d893
L		 4108 if (!old_gcc && t->opcode_modifier.oldgcc)
4109 continue;
4110
4111 /* Check AT&T mnemonic. */
a65babc9 4112 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4113 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4114 continue;
4115
891edac4 4116 /* Check AT&T/Intel syntax. */
a65babc9 4117 i.error = unsupported_syntax;
5c07affc
L		 4118 if ((intel_syntax && t->opcode_modifier.attsyntax)
4119 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4120 continue;
4121
20592a94 4122 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4123 i.error = invalid_instruction_suffix;
567e4e96
L		 4124 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4125 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4126 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4127 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4128 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4129 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4130 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4131 continue;
4132
5c07affc 4133 if (!operand_size_match (t))
7d5e4556 4134 continue;
539e75ad 4135
5c07affc
L		 4136 for (j = 0; j < MAX_OPERANDS; j++)
4137 operand_types[j] = t->operand_types[j];
4138
45aa61fe
AM		 4139 /* In general, don't allow 64-bit operands in 32-bit mode. */
4140 if (i.suffix == QWORD_MNEM_SUFFIX
4141 && flag_code != CODE_64BIT
4142 && (intel_syntax
40fb9820 4143 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4144 && !intel_float_operand (t->name))
4145 : intel_float_operand (t->name) != 2)
40fb9820 4146 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 4147 && !operand_types[0].bitfield.regxmm
4148 && !operand_types[0].bitfield.regymm)
40fb9820 4149 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 4150 && !!operand_types[t->operands > 1].bitfield.regxmm
4151 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 4152 && (t->base_opcode != 0x0fc7
4153 || t->extension_opcode != 1 /* cmpxchg8b */))
4154 continue;
4155
192dc9c6
JB		 4156 /* In general, don't allow 32-bit operands on pre-386. */
4157 else if (i.suffix == LONG_MNEM_SUFFIX
4158 && !cpu_arch_flags.bitfield.cpui386
4159 && (intel_syntax
4160 ? (!t->opcode_modifier.ignoresize
4161 && !intel_float_operand (t->name))
4162 : intel_float_operand (t->name) != 2)
4163 && ((!operand_types[0].bitfield.regmmx
4164 && !operand_types[0].bitfield.regxmm)
4165 || (!operand_types[t->operands > 1].bitfield.regmmx
4166 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4167 continue;
4168
29b0f896 4169 /* Do not verify operands when there are none. */
50aecf8c 4170 else
29b0f896 4171 {
c6fb90c8 4172 if (!t->operands)
2dbab7d5
L		 4173 /* We've found a match; break out of loop. */
4174 break;
29b0f896 4175 }
252b5132 4176
539e75ad
L		 4177 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4178 into Disp32/Disp16/Disp32 operand. */
4179 if (i.prefix[ADDR_PREFIX] != 0)
4180 {
40fb9820 4181 /* There should be only one Disp operand. */
539e75ad
L		 4182 switch (flag_code)
4183 {
4184 case CODE_16BIT:
40fb9820
L		 4185 for (j = 0; j < MAX_OPERANDS; j++)
4186 {
4187 if (operand_types[j].bitfield.disp16)
4188 {
4189 addr_prefix_disp = j;
4190 operand_types[j].bitfield.disp32 = 1;
4191 operand_types[j].bitfield.disp16 = 0;
4192 break;
4193 }
4194 }
539e75ad
L		 4195 break;
4196 case CODE_32BIT:
40fb9820
L		 4197 for (j = 0; j < MAX_OPERANDS; j++)
4198 {
4199 if (operand_types[j].bitfield.disp32)
4200 {
4201 addr_prefix_disp = j;
4202 operand_types[j].bitfield.disp32 = 0;
4203 operand_types[j].bitfield.disp16 = 1;
4204 break;
4205 }
4206 }
539e75ad
L		 4207 break;
4208 case CODE_64BIT:
40fb9820
L		 4209 for (j = 0; j < MAX_OPERANDS; j++)
4210 {
4211 if (operand_types[j].bitfield.disp64)
4212 {
4213 addr_prefix_disp = j;
4214 operand_types[j].bitfield.disp64 = 0;
4215 operand_types[j].bitfield.disp32 = 1;
4216 break;
4217 }
4218 }
539e75ad
L		 4219 break;
4220 }
539e75ad
L		 4221 }
4222
56ffb741
L		 4223 /* We check register size if needed. */
4224 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4225 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4226 switch (t->operands)
4227 {
4228 case 1:
40fb9820 4229 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4230 continue;
4231 break;
4232 case 2:
8b38ad71
L		 4233 /* xchg %eax, %eax is a special case. It is an aliase for nop
4234 only in 32bit mode and we can use opcode 0x90. In 64bit
4235 mode, we can't use 0x90 for xchg %eax, %eax since it should
4236 zero-extend %eax to %rax. */
4237 if (flag_code == CODE_64BIT
4238 && t->base_opcode == 0x90
0dfbf9d7
L		 4239 && operand_type_equal (&i.types [0], &acc32)
4240 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4241 continue;
b6169b20
L		 4242 if (i.swap_operand)
4243 {
4244 /* If we swap operand in encoding, we either match
4245 the next one or reverse direction of operands. */
4246 if (t->opcode_modifier.s)
4247 continue;
4248 else if (t->opcode_modifier.d)
4249 goto check_reverse;
4250 }
4251
29b0f896 4252 case 3:
fa99fab2
L		 4253 /* If we swap operand in encoding, we match the next one. */
4254 if (i.swap_operand && t->opcode_modifier.s)
4255 continue;
f48ff2ae 4256 case 4:
c0f3af97 4257 case 5:
c6fb90c8 4258 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4259 if (!operand_type_match (overlap0, i.types[0])
4260 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4261 || (check_register
4262 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4263 operand_types[0],
4264 overlap1, i.types[1],
4265 operand_types[1])))
29b0f896
AM		 4266 {
4267 /* Check if other direction is valid ... */
40fb9820 4268 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4269 continue;
4270
b6169b20 4271check_reverse:
29b0f896 4272 /* Try reversing direction of operands. */
c6fb90c8
L		 4273 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4274 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4275 if (!operand_type_match (overlap0, i.types[0])
4276 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4277 || (check_register
4278 && !operand_type_register_match (overlap0,
4279 i.types[0],
4280 operand_types[1],
4281 overlap1,
4282 i.types[1],
4283 operand_types[0])))
29b0f896
AM		 4284 {
4285 /* Does not match either direction. */
4286 continue;
4287 }
4288 /* found_reverse_match holds which of D or FloatDR
4289 we've found. */
40fb9820 4290 if (t->opcode_modifier.d)
8a2ed489 4291 found_reverse_match = Opcode_D;
40fb9820 4292 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4293 found_reverse_match = Opcode_FloatD;
4294 else
4295 found_reverse_match = 0;
40fb9820 4296 if (t->opcode_modifier.floatr)
8a2ed489 4297 found_reverse_match |= Opcode_FloatR;
29b0f896 4298 }
f48ff2ae 4299 else
29b0f896 4300 {
f48ff2ae 4301 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4302 switch (t->operands)
4303 {
c0f3af97
L		 4304 case 5:
4305 overlap4 = operand_type_and (i.types[4],
4306 operand_types[4]);
d1cbb4db 4307 case 4:
c6fb90c8
L		 4308 overlap3 = operand_type_and (i.types[3],
4309 operand_types[3]);
d1cbb4db 4310 case 3:
c6fb90c8
L		 4311 overlap2 = operand_type_and (i.types[2],
4312 operand_types[2]);
d1cbb4db
L		 4313 break;
4314 }
29b0f896 4315
f48ff2ae
L		 4316 switch (t->operands)
4317 {
c0f3af97
L		 4318 case 5:
4319 if (!operand_type_match (overlap4, i.types[4])
4320 || !operand_type_register_match (overlap3,
4321 i.types[3],
4322 operand_types[3],
4323 overlap4,
4324 i.types[4],
4325 operand_types[4]))
4326 continue;
f48ff2ae 4327 case 4:
40fb9820 4328 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4329 || (check_register
4330 && !operand_type_register_match (overlap2,
4331 i.types[2],
4332 operand_types[2],
4333 overlap3,
4334 i.types[3],
4335 operand_types[3])))
f48ff2ae
L		 4336 continue;
4337 case 3:
4338 /* Here we make use of the fact that there are no
4339 reverse match 3 operand instructions, and all 3
4340 operand instructions only need to be checked for
4341 register consistency between operands 2 and 3. */
40fb9820 4342 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4343 || (check_register
4344 && !operand_type_register_match (overlap1,
4345 i.types[1],
4346 operand_types[1],
4347 overlap2,
4348 i.types[2],
4349 operand_types[2])))
f48ff2ae
L		 4350 continue;
4351 break;
4352 }
29b0f896 4353 }
f48ff2ae 4354 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4355 slip through to break. */
4356 }
3629bb00 4357 if (!found_cpu_match)
29b0f896
AM		 4358 {
4359 found_reverse_match = 0;
4360 continue;
4361 }
c0f3af97 4362
5614d22c
JB		 4363 /* Check if vector and VEX operands are valid. */
4364 if (check_VecOperands (t) || VEX_check_operands (t))
4365 {
4366 specific_error = i.error;
4367 continue;
4368 }
a683cc34 4369
29b0f896
AM		 4370 /* We've found a match; break out of loop. */
4371 break;
4372 }
4373
4374 if (t == current_templates->end)
4375 {
4376 /* We found no match. */
a65babc9 4377 const char *err_msg;
5614d22c 4378 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4379 {
4380 default:
4381 abort ();
86e026a4 4382 case operand_size_mismatch:
a65babc9
L		 4383 err_msg = _("operand size mismatch");
4384 break;
4385 case operand_type_mismatch:
4386 err_msg = _("operand type mismatch");
4387 break;
4388 case register_type_mismatch:
4389 err_msg = _("register type mismatch");
4390 break;
4391 case number_of_operands_mismatch:
4392 err_msg = _("number of operands mismatch");
4393 break;
4394 case invalid_instruction_suffix:
4395 err_msg = _("invalid instruction suffix");
4396 break;
4397 case bad_imm4:
4a2608e3 4398 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4399 break;
4400 case old_gcc_only:
4401 err_msg = _("only supported with old gcc");
4402 break;
4403 case unsupported_with_intel_mnemonic:
4404 err_msg = _("unsupported with Intel mnemonic");
4405 break;
4406 case unsupported_syntax:
4407 err_msg = _("unsupported syntax");
4408 break;
4409 case unsupported:
35262a23 4410 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4411 current_templates->start->name);
4412 return NULL;
6c30d220
L		 4413 case invalid_vsib_address:
4414 err_msg = _("invalid VSIB address");
4415 break;
7bab8ab5
JB		 4416 case invalid_vector_register_set:
4417 err_msg = _("mask, index, and destination registers must be distinct");
4418 break;
6c30d220
L		 4419 case unsupported_vector_index_register:
4420 err_msg = _("unsupported vector index register");
4421 break;
a65babc9
L		 4422 }
4423 as_bad (_("%s for `%s'"), err_msg,
891edac4 4424 current_templates->start->name);
fa99fab2 4425 return NULL;
29b0f896 4426 }
252b5132 4427
29b0f896
AM		 4428 if (!quiet_warnings)
4429 {
4430 if (!intel_syntax
40fb9820
L		 4431 && (i.types[0].bitfield.jumpabsolute
4432 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4433 {
4434 as_warn (_("indirect %s without `*'"), t->name);
4435 }
4436
40fb9820
L		 4437 if (t->opcode_modifier.isprefix
4438 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4439 {
4440 /* Warn them that a data or address size prefix doesn't
4441 affect assembly of the next line of code. */
4442 as_warn (_("stand-alone `%s' prefix"), t->name);
4443 }
4444 }
4445
4446 /* Copy the template we found. */
4447 i.tm = *t;
539e75ad
L		 4448
4449 if (addr_prefix_disp != -1)
4450 i.tm.operand_types[addr_prefix_disp]
4451 = operand_types[addr_prefix_disp];
4452
29b0f896
AM		 4453 if (found_reverse_match)
4454 {
4455 /* If we found a reverse match we must alter the opcode
4456 direction bit. found_reverse_match holds bits to change
4457 (different for int & float insns). */
4458
4459 i.tm.base_opcode ^= found_reverse_match;
4460
539e75ad
L		 4461 i.tm.operand_types[0] = operand_types[1];
4462 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4463 }
4464
fa99fab2 4465 return t;
29b0f896
AM		 4466}
4467
4468static int
e3bb37b5 4469check_string (void)
29b0f896 4470{
40fb9820
L		 4471 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4472 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4473 {
4474 if (i.seg[0] != NULL && i.seg[0] != &es)
4475 {
a87af027 4476 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4477 i.tm.name,
a87af027
JB		 4478 mem_op + 1,
4479 register_prefix);
29b0f896
AM		 4480 return 0;
4481 }
4482 /* There's only ever one segment override allowed per instruction.
4483 This instruction possibly has a legal segment override on the
4484 second operand, so copy the segment to where non-string
4485 instructions store it, allowing common code. */
4486 i.seg[0] = i.seg[1];
4487 }
40fb9820 4488 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4489 {
4490 if (i.seg[1] != NULL && i.seg[1] != &es)
4491 {
a87af027 4492 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4493 i.tm.name,
a87af027
JB		 4494 mem_op + 2,
4495 register_prefix);
29b0f896
AM		 4496 return 0;
4497 }
4498 }
4499 return 1;
4500}
4501
4502static int
543613e9 4503process_suffix (void)
29b0f896
AM		 4504{
4505 /* If matched instruction specifies an explicit instruction mnemonic
4506 suffix, use it. */
40fb9820
L		 4507 if (i.tm.opcode_modifier.size16)
4508 i.suffix = WORD_MNEM_SUFFIX;
4509 else if (i.tm.opcode_modifier.size32)
4510 i.suffix = LONG_MNEM_SUFFIX;
4511 else if (i.tm.opcode_modifier.size64)
4512 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4513 else if (i.reg_operands)
4514 {
4515 /* If there's no instruction mnemonic suffix we try to invent one
4516 based on register operands. */
4517 if (!i.suffix)
4518 {
4519 /* We take i.suffix from the last register operand specified,
4520 Destination register type is more significant than source
381d071f
L		 4521 register type. crc32 in SSE4.2 prefers source register
4522 type. */
4523 if (i.tm.base_opcode == 0xf20f38f1)
4524 {
40fb9820
L		 4525 if (i.types[0].bitfield.reg16)
4526 i.suffix = WORD_MNEM_SUFFIX;
4527 else if (i.types[0].bitfield.reg32)
4528 i.suffix = LONG_MNEM_SUFFIX;
4529 else if (i.types[0].bitfield.reg64)
4530 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4531 }
9344ff29 4532 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4533 {
40fb9820 4534 if (i.types[0].bitfield.reg8)
20592a94
L		 4535 i.suffix = BYTE_MNEM_SUFFIX;
4536 }
381d071f
L		 4537
4538 if (!i.suffix)
4539 {
4540 int op;
4541
20592a94
L		 4542 if (i.tm.base_opcode == 0xf20f38f1
4543 || i.tm.base_opcode == 0xf20f38f0)
4544 {
4545 /* We have to know the operand size for crc32. */
4546 as_bad (_("ambiguous memory operand size for `%s`"),
4547 i.tm.name);
4548 return 0;
4549 }
4550
381d071f 4551 for (op = i.operands; --op >= 0;)
40fb9820 4552 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4553 {
40fb9820
L		 4554 if (i.types[op].bitfield.reg8)
4555 {
4556 i.suffix = BYTE_MNEM_SUFFIX;
4557 break;
4558 }
4559 else if (i.types[op].bitfield.reg16)
4560 {
4561 i.suffix = WORD_MNEM_SUFFIX;
4562 break;
4563 }
4564 else if (i.types[op].bitfield.reg32)
4565 {
4566 i.suffix = LONG_MNEM_SUFFIX;
4567 break;
4568 }
4569 else if (i.types[op].bitfield.reg64)
4570 {
4571 i.suffix = QWORD_MNEM_SUFFIX;
4572 break;
4573 }
381d071f
L		 4574 }
4575 }
29b0f896
AM		 4576 }
4577 else if (i.suffix == BYTE_MNEM_SUFFIX)
4578 {
2eb952a4
L		 4579 if (intel_syntax
4580 && i.tm.opcode_modifier.ignoresize
4581 && i.tm.opcode_modifier.no_bsuf)
4582 i.suffix = 0;
4583 else if (!check_byte_reg ())
29b0f896
AM		 4584 return 0;
4585 }
4586 else if (i.suffix == LONG_MNEM_SUFFIX)
4587 {
2eb952a4
L		 4588 if (intel_syntax
4589 && i.tm.opcode_modifier.ignoresize
4590 && i.tm.opcode_modifier.no_lsuf)
4591 i.suffix = 0;
4592 else if (!check_long_reg ())
29b0f896
AM		 4593 return 0;
4594 }
4595 else if (i.suffix == QWORD_MNEM_SUFFIX)
4596 {
955e1e6a
L		 4597 if (intel_syntax
4598 && i.tm.opcode_modifier.ignoresize
4599 && i.tm.opcode_modifier.no_qsuf)
4600 i.suffix = 0;
4601 else if (!check_qword_reg ())
29b0f896
AM		 4602 return 0;
4603 }
4604 else if (i.suffix == WORD_MNEM_SUFFIX)
4605 {
2eb952a4
L		 4606 if (intel_syntax
4607 && i.tm.opcode_modifier.ignoresize
4608 && i.tm.opcode_modifier.no_wsuf)
4609 i.suffix = 0;
4610 else if (!check_word_reg ())
29b0f896
AM		 4611 return 0;
4612 }
c0f3af97
L		 4613 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4614 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4615 {
c0f3af97 4616 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4617 should check if it is a valid suffix. */
4618 }
40fb9820 4619 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4620 /* Do nothing if the instruction is going to ignore the prefix. */
4621 ;
4622 else
4623 abort ();
4624 }
40fb9820 4625 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4626 && !i.suffix
4627 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4628 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4629 {
4630 i.suffix = stackop_size;
4631 }
9306ca4a
JB		 4632 else if (intel_syntax
4633 && !i.suffix
40fb9820
L		 4634 && (i.tm.operand_types[0].bitfield.jumpabsolute
4635 || i.tm.opcode_modifier.jumpbyte
4636 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4637 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4638 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4639 {
4640 switch (flag_code)
4641 {
4642 case CODE_64BIT:
40fb9820 4643 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4644 {
4645 i.suffix = QWORD_MNEM_SUFFIX;
4646 break;
4647 }
4648 case CODE_32BIT:
40fb9820 4649 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4650 i.suffix = LONG_MNEM_SUFFIX;
4651 break;
4652 case CODE_16BIT:
40fb9820 4653 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4654 i.suffix = WORD_MNEM_SUFFIX;
4655 break;
4656 }
4657 }
252b5132 4658
9306ca4a 4659 if (!i.suffix)
29b0f896 4660 {
9306ca4a
JB		 4661 if (!intel_syntax)
4662 {
40fb9820 4663 if (i.tm.opcode_modifier.w)
9306ca4a 4664 {
4eed87de
AM		 4665 as_bad (_("no instruction mnemonic suffix given and "
4666 "no register operands; can't size instruction"));
9306ca4a
JB		 4667 return 0;
4668 }
4669 }
4670 else
4671 {
40fb9820 4672 unsigned int suffixes;
7ab9ffdd 4673
40fb9820
L		 4674 suffixes = !i.tm.opcode_modifier.no_bsuf;
4675 if (!i.tm.opcode_modifier.no_wsuf)
4676 suffixes |= 1 << 1;
4677 if (!i.tm.opcode_modifier.no_lsuf)
4678 suffixes |= 1 << 2;
fc4adea1 4679 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4680 suffixes |= 1 << 3;
4681 if (!i.tm.opcode_modifier.no_ssuf)
4682 suffixes |= 1 << 4;
4683 if (!i.tm.opcode_modifier.no_qsuf)
4684 suffixes |= 1 << 5;
4685
4686 /* There are more than suffix matches. */
4687 if (i.tm.opcode_modifier.w
9306ca4a 4688 || ((suffixes & (suffixes - 1))
40fb9820
L		 4689 && !i.tm.opcode_modifier.defaultsize
4690 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4691 {
4692 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4693 return 0;
4694 }
4695 }
29b0f896 4696 }
252b5132 4697
9306ca4a
JB		 4698 /* Change the opcode based on the operand size given by i.suffix;
4699 We don't need to change things for byte insns. */
4700
582d5edd
L		 4701 if (i.suffix
4702 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4703 && i.suffix != XMMWORD_MNEM_SUFFIX
4704 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4705 {
4706 /* It's not a byte, select word/dword operation. */
40fb9820 4707 if (i.tm.opcode_modifier.w)
29b0f896 4708 {
40fb9820 4709 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4710 i.tm.base_opcode |= 8;
4711 else
4712 i.tm.base_opcode |= 1;
4713 }
0f3f3d8b 4714
29b0f896
AM		 4715 /* Now select between word & dword operations via the operand
4716 size prefix, except for instructions that will ignore this
4717 prefix anyway. */
ca61edf2 4718 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4719 {
ca61edf2
L		 4720 /* The address size override prefix changes the size of the
4721 first operand. */
40fb9820
L		 4722 if ((flag_code == CODE_32BIT
4723 && i.op->regs[0].reg_type.bitfield.reg16)
4724 || (flag_code != CODE_32BIT
4725 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4726 if (!add_prefix (ADDR_PREFIX_OPCODE))
4727 return 0;
4728 }
4729 else if (i.suffix != QWORD_MNEM_SUFFIX
4730 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4731 && !i.tm.opcode_modifier.ignoresize
4732 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4733 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4734 || (flag_code == CODE_64BIT
40fb9820 4735 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4736 {
4737 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4738
40fb9820 4739 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4740 prefix = ADDR_PREFIX_OPCODE;
252b5132 4741
29b0f896
AM		 4742 if (!add_prefix (prefix))
4743 return 0;
24eab124 4744 }
252b5132 4745
29b0f896
AM		 4746 /* Set mode64 for an operand. */
4747 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4748 && flag_code == CODE_64BIT
40fb9820 4749 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4750 {
4751 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4752 need rex64. cmpxchg8b is also a special case. */
4753 if (! (i.operands == 2
4754 && i.tm.base_opcode == 0x90
4755 && i.tm.extension_opcode == None
0dfbf9d7
L		 4756 && operand_type_equal (&i.types [0], &acc64)
4757 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4758 && ! (i.operands == 1
4759 && i.tm.base_opcode == 0xfc7
4760 && i.tm.extension_opcode == 1
40fb9820
L		 4761 && !operand_type_check (i.types [0], reg)
4762 && operand_type_check (i.types [0], anymem)))
f6bee062 4763 i.rex |= REX_W;
46e883c5 4764 }
3e73aa7c 4765
29b0f896
AM		 4766 /* Size floating point instruction. */
4767 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4768 if (i.tm.opcode_modifier.floatmf)
543613e9 4769 i.tm.base_opcode ^= 4;
29b0f896 4770 }
7ecd2f8b 4771
29b0f896
AM		 4772 return 1;
4773}
3e73aa7c 4774
29b0f896 4775static int
543613e9 4776check_byte_reg (void)
29b0f896
AM		 4777{
4778 int op;
543613e9 4779
29b0f896
AM		 4780 for (op = i.operands; --op >= 0;)
4781 {
4782 /* If this is an eight bit register, it's OK. If it's the 16 or
4783 32 bit version of an eight bit register, we will just use the
4784 low portion, and that's OK too. */
40fb9820 4785 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4786 continue;
4787
5a819eb9
JB		 4788 /* I/O port address operands are OK too. */
4789 if (i.tm.operand_types[op].bitfield.inoutportreg)
4790 continue;
4791
9344ff29
L		 4792 /* crc32 doesn't generate this warning. */
4793 if (i.tm.base_opcode == 0xf20f38f0)
4794 continue;
4795
40fb9820
L		 4796 if ((i.types[op].bitfield.reg16
4797 || i.types[op].bitfield.reg32
4798 || i.types[op].bitfield.reg64)
5a819eb9
JB		 4799 && i.op[op].regs->reg_num < 4
4800 /* Prohibit these changes in 64bit mode, since the lowering
4801 would be more complicated. */
4802 && flag_code != CODE_64BIT)
29b0f896 4803 {
29b0f896 4804#if REGISTER_WARNINGS
5a819eb9 4805 if (!quiet_warnings)
a540244d
L		 4806 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4807 register_prefix,
40fb9820 4808 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4809 ? REGNAM_AL - REGNAM_AX
4810 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4811 register_prefix,
29b0f896
AM		 4812 i.op[op].regs->reg_name,
4813 i.suffix);
4814#endif
4815 continue;
4816 }
4817 /* Any other register is bad. */
40fb9820
L		 4818 if (i.types[op].bitfield.reg16
4819 || i.types[op].bitfield.reg32
4820 || i.types[op].bitfield.reg64
4821 || i.types[op].bitfield.regmmx
4822 || i.types[op].bitfield.regxmm
c0f3af97 4823 || i.types[op].bitfield.regymm
40fb9820
L		 4824 || i.types[op].bitfield.sreg2
4825 || i.types[op].bitfield.sreg3
4826 || i.types[op].bitfield.control
4827 || i.types[op].bitfield.debug
4828 || i.types[op].bitfield.test
4829 || i.types[op].bitfield.floatreg
4830 || i.types[op].bitfield.floatacc)
29b0f896 4831 {
a540244d
L		 4832 as_bad (_("`%s%s' not allowed with `%s%c'"),
4833 register_prefix,
29b0f896
AM		 4834 i.op[op].regs->reg_name,
4835 i.tm.name,
4836 i.suffix);
4837 return 0;
4838 }
4839 }
4840 return 1;
4841}
4842
4843static int
e3bb37b5 4844check_long_reg (void)
29b0f896
AM		 4845{
4846 int op;
4847
4848 for (op = i.operands; --op >= 0;)
4849 /* Reject eight bit registers, except where the template requires
4850 them. (eg. movzb) */
40fb9820
L		 4851 if (i.types[op].bitfield.reg8
4852 && (i.tm.operand_types[op].bitfield.reg16
4853 || i.tm.operand_types[op].bitfield.reg32
4854 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4855 {
a540244d
L		 4856 as_bad (_("`%s%s' not allowed with `%s%c'"),
4857 register_prefix,
29b0f896
AM		 4858 i.op[op].regs->reg_name,
4859 i.tm.name,
4860 i.suffix);
4861 return 0;
4862 }
4863 /* Warn if the e prefix on a general reg is missing. */
4864 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4865 && i.types[op].bitfield.reg16
4866 && (i.tm.operand_types[op].bitfield.reg32
4867 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4868 {
4869 /* Prohibit these changes in the 64bit mode, since the
4870 lowering is more complicated. */
4871 if (flag_code == CODE_64BIT)
252b5132 4872 {
2b5d6a91 4873 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4874 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4875 i.suffix);
4876 return 0;
252b5132 4877 }
29b0f896
AM		 4878#if REGISTER_WARNINGS
4879 else
a540244d
L		 4880 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4881 register_prefix,
29b0f896 4882 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4883 register_prefix,
29b0f896
AM		 4884 i.op[op].regs->reg_name,
4885 i.suffix);
4886#endif
252b5132 4887 }
29b0f896 4888 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4889 else if (i.types[op].bitfield.reg64
4890 && (i.tm.operand_types[op].bitfield.reg32
4891 || i.tm.operand_types[op].bitfield.acc))
252b5132 4892 {
34828aad 4893 if (intel_syntax
ca61edf2 4894 && i.tm.opcode_modifier.toqword
40fb9820 4895 && !i.types[0].bitfield.regxmm)
34828aad 4896 {
ca61edf2 4897 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4898 i.suffix = QWORD_MNEM_SUFFIX;
4899 }
4900 else
4901 {
2b5d6a91 4902 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4903 register_prefix, i.op[op].regs->reg_name,
4904 i.suffix);
4905 return 0;
4906 }
29b0f896
AM		 4907 }
4908 return 1;
4909}
252b5132 4910
29b0f896 4911static int
e3bb37b5 4912check_qword_reg (void)
29b0f896
AM		 4913{
4914 int op;
252b5132 4915
29b0f896
AM		 4916 for (op = i.operands; --op >= 0; )
4917 /* Reject eight bit registers, except where the template requires
4918 them. (eg. movzb) */
40fb9820
L		 4919 if (i.types[op].bitfield.reg8
4920 && (i.tm.operand_types[op].bitfield.reg16
4921 || i.tm.operand_types[op].bitfield.reg32
4922 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4923 {
a540244d
L		 4924 as_bad (_("`%s%s' not allowed with `%s%c'"),
4925 register_prefix,
29b0f896
AM		 4926 i.op[op].regs->reg_name,
4927 i.tm.name,
4928 i.suffix);
4929 return 0;
4930 }
4931 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4932 else if ((i.types[op].bitfield.reg16
4933 || i.types[op].bitfield.reg32)
4934 && (i.tm.operand_types[op].bitfield.reg32
4935 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4936 {
4937 /* Prohibit these changes in the 64bit mode, since the
4938 lowering is more complicated. */
34828aad 4939 if (intel_syntax
ca61edf2 4940 && i.tm.opcode_modifier.todword
40fb9820 4941 && !i.types[0].bitfield.regxmm)
34828aad 4942 {
ca61edf2 4943 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4944 i.suffix = LONG_MNEM_SUFFIX;
4945 }
4946 else
4947 {
2b5d6a91 4948 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4949 register_prefix, i.op[op].regs->reg_name,
4950 i.suffix);
4951 return 0;
4952 }
252b5132 4953 }
29b0f896
AM		 4954 return 1;
4955}
252b5132 4956
29b0f896 4957static int
e3bb37b5 4958check_word_reg (void)
29b0f896
AM		 4959{
4960 int op;
4961 for (op = i.operands; --op >= 0;)
4962 /* Reject eight bit registers, except where the template requires
4963 them. (eg. movzb) */
40fb9820
L		 4964 if (i.types[op].bitfield.reg8
4965 && (i.tm.operand_types[op].bitfield.reg16
4966 || i.tm.operand_types[op].bitfield.reg32
4967 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4968 {
a540244d
L		 4969 as_bad (_("`%s%s' not allowed with `%s%c'"),
4970 register_prefix,
29b0f896
AM		 4971 i.op[op].regs->reg_name,
4972 i.tm.name,
4973 i.suffix);
4974 return 0;
4975 }
4976 /* Warn if the e prefix on a general reg is present. */
4977 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4978 && i.types[op].bitfield.reg32
4979 && (i.tm.operand_types[op].bitfield.reg16
4980 || i.tm.operand_types[op].bitfield.acc))
252b5132 4981 {
29b0f896
AM		 4982 /* Prohibit these changes in the 64bit mode, since the
4983 lowering is more complicated. */
4984 if (flag_code == CODE_64BIT)
252b5132 4985 {
2b5d6a91 4986 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4987 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4988 i.suffix);
4989 return 0;
252b5132 4990 }
29b0f896
AM		 4991 else
4992#if REGISTER_WARNINGS
a540244d
L		 4993 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4994 register_prefix,
29b0f896 4995 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4996 register_prefix,
29b0f896
AM		 4997 i.op[op].regs->reg_name,
4998 i.suffix);
4999#endif
5000 }
5001 return 1;
5002}
252b5132 5003
29b0f896 5004static int
40fb9820 5005update_imm (unsigned int j)
29b0f896 5006{
bc0844ae 5007 i386_operand_type overlap = i.types[j];
40fb9820
L		 5008 if ((overlap.bitfield.imm8
5009 || overlap.bitfield.imm8s
5010 || overlap.bitfield.imm16
5011 || overlap.bitfield.imm32
5012 || overlap.bitfield.imm32s
5013 || overlap.bitfield.imm64)
0dfbf9d7
L		 5014 && !operand_type_equal (&overlap, &imm8)
5015 && !operand_type_equal (&overlap, &imm8s)
5016 && !operand_type_equal (&overlap, &imm16)
5017 && !operand_type_equal (&overlap, &imm32)
5018 && !operand_type_equal (&overlap, &imm32s)
5019 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5020 {
5021 if (i.suffix)
5022 {
40fb9820
L		 5023 i386_operand_type temp;
5024
0dfbf9d7 5025 operand_type_set (&temp, 0);
7ab9ffdd 5026 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5027 {
5028 temp.bitfield.imm8 = overlap.bitfield.imm8;
5029 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5030 }
5031 else if (i.suffix == WORD_MNEM_SUFFIX)
5032 temp.bitfield.imm16 = overlap.bitfield.imm16;
5033 else if (i.suffix == QWORD_MNEM_SUFFIX)
5034 {
5035 temp.bitfield.imm64 = overlap.bitfield.imm64;
5036 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5037 }
5038 else
5039 temp.bitfield.imm32 = overlap.bitfield.imm32;
5040 overlap = temp;
29b0f896 5041 }
0dfbf9d7
L		 5042 else if (operand_type_equal (&overlap, &imm16_32_32s)
5043 || operand_type_equal (&overlap, &imm16_32)
5044 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5045 {
40fb9820 5046 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5047 overlap = imm16;
40fb9820 5048 else
65da13b5 5049 overlap = imm32s;
29b0f896 5050 }
0dfbf9d7
L		 5051 if (!operand_type_equal (&overlap, &imm8)
5052 && !operand_type_equal (&overlap, &imm8s)
5053 && !operand_type_equal (&overlap, &imm16)
5054 && !operand_type_equal (&overlap, &imm32)
5055 && !operand_type_equal (&overlap, &imm32s)
5056 && !operand_type_equal (&overlap, &imm64))
29b0f896 5057 {
4eed87de
AM		 5058 as_bad (_("no instruction mnemonic suffix given; "
5059 "can't determine immediate size"));
29b0f896
AM		 5060 return 0;
5061 }
5062 }
40fb9820 5063 i.types[j] = overlap;
29b0f896 5064
40fb9820
L		 5065 return 1;
5066}
5067
5068static int
5069finalize_imm (void)
5070{
bc0844ae 5071 unsigned int j, n;
29b0f896 5072
bc0844ae
L		 5073 /* Update the first 2 immediate operands. */
5074 n = i.operands > 2 ? 2 : i.operands;
5075 if (n)
5076 {
5077 for (j = 0; j < n; j++)
5078 if (update_imm (j) == 0)
5079 return 0;
40fb9820 5080
bc0844ae
L		 5081 /* The 3rd operand can't be immediate operand. */
5082 gas_assert (operand_type_check (i.types[2], imm) == 0);
5083 }
29b0f896
AM		 5084
5085 return 1;
5086}
5087
c0f3af97
L		 5088static int
5089bad_implicit_operand (int xmm)
5090{
91d6fa6a
NC		 5091 const char *ireg = xmm ? "xmm0" : "ymm0";
5092
c0f3af97
L		 5093 if (intel_syntax)
5094 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5095 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5096 else
5097 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5098 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5099 return 0;
5100}
5101
29b0f896 5102static int
e3bb37b5 5103process_operands (void)
29b0f896
AM		 5104{
5105 /* Default segment register this instruction will use for memory
5106 accesses. 0 means unknown. This is only for optimizing out
5107 unnecessary segment overrides. */
5108 const seg_entry *default_seg = 0;
5109
2426c15f 5110 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5111 {
91d6fa6a
NC		 5112 unsigned int dupl = i.operands;
5113 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5114 unsigned int j;
5115
c0f3af97 5116 /* The destination must be an xmm register. */
9c2799c2 5117 gas_assert (i.reg_operands
91d6fa6a 5118 && MAX_OPERANDS > dupl
7ab9ffdd 5119 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5120
5121 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5122 {
c0f3af97 5123 /* The first operand is implicit and must be xmm0. */
9c2799c2 5124 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5125 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5126 return bad_implicit_operand (1);
5127
8cd7925b 5128 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5129 {
5130 /* Keep xmm0 for instructions with VEX prefix and 3
5131 sources. */
5132 goto duplicate;
5133 }
e2ec9d29 5134 else
c0f3af97
L		 5135 {
5136 /* We remove the first xmm0 and keep the number of
5137 operands unchanged, which in fact duplicates the
5138 destination. */
5139 for (j = 1; j < i.operands; j++)
5140 {
5141 i.op[j - 1] = i.op[j];
5142 i.types[j - 1] = i.types[j];
5143 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5144 }
5145 }
5146 }
5147 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5148 {
91d6fa6a 5149 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5150 && (i.tm.opcode_modifier.vexsources
5151 == VEX3SOURCES));
c0f3af97
L		 5152
5153 /* Add the implicit xmm0 for instructions with VEX prefix
5154 and 3 sources. */
5155 for (j = i.operands; j > 0; j--)
5156 {
5157 i.op[j] = i.op[j - 1];
5158 i.types[j] = i.types[j - 1];
5159 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5160 }
5161 i.op[0].regs
5162 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5163 i.types[0] = regxmm;
c0f3af97
L		 5164 i.tm.operand_types[0] = regxmm;
5165
5166 i.operands += 2;
5167 i.reg_operands += 2;
5168 i.tm.operands += 2;
5169
91d6fa6a 5170 dupl++;
c0f3af97 5171 dest++;
91d6fa6a
NC		 5172 i.op[dupl] = i.op[dest];
5173 i.types[dupl] = i.types[dest];
5174 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5175 }
c0f3af97
L		 5176 else
5177 {
5178duplicate:
5179 i.operands++;
5180 i.reg_operands++;
5181 i.tm.operands++;
5182
91d6fa6a
NC		 5183 i.op[dupl] = i.op[dest];
5184 i.types[dupl] = i.types[dest];
5185 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5186 }
5187
5188 if (i.tm.opcode_modifier.immext)
5189 process_immext ();
5190 }
5191 else if (i.tm.opcode_modifier.firstxmm0)
5192 {
5193 unsigned int j;
5194
5195 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 5196 gas_assert (i.reg_operands
7ab9ffdd
L		 5197 && (operand_type_equal (&i.types[0], &regxmm)
5198 || operand_type_equal (&i.types[0], &regymm)));
4c692bc7 5199 if (register_number (i.op[0].regs) != 0)
c0f3af97 5200 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5201
5202 for (j = 1; j < i.operands; j++)
5203 {
5204 i.op[j - 1] = i.op[j];
5205 i.types[j - 1] = i.types[j];
5206
5207 /* We need to adjust fields in i.tm since they are used by
5208 build_modrm_byte. */
5209 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5210 }
5211
e2ec9d29
L		 5212 i.operands--;
5213 i.reg_operands--;
e2ec9d29
L		 5214 i.tm.operands--;
5215 }
5216 else if (i.tm.opcode_modifier.regkludge)
5217 {
5218 /* The imul $imm, %reg instruction is converted into
5219 imul $imm, %reg, %reg, and the clr %reg instruction
5220 is converted into xor %reg, %reg. */
5221
5222 unsigned int first_reg_op;
5223
5224 if (operand_type_check (i.types[0], reg))
5225 first_reg_op = 0;
5226 else
5227 first_reg_op = 1;
5228 /* Pretend we saw the extra register operand. */
9c2799c2 5229 gas_assert (i.reg_operands == 1
7ab9ffdd 5230 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5231 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5232 i.types[first_reg_op + 1] = i.types[first_reg_op];
5233 i.operands++;
5234 i.reg_operands++;
29b0f896
AM		 5235 }
5236
40fb9820 5237 if (i.tm.opcode_modifier.shortform)
29b0f896 5238 {
40fb9820
L		 5239 if (i.types[0].bitfield.sreg2
5240 || i.types[0].bitfield.sreg3)
29b0f896 5241 {
4eed87de
AM		 5242 if (i.tm.base_opcode == POP_SEG_SHORT
5243 && i.op[0].regs->reg_num == 1)
29b0f896 5244 {
a87af027 5245 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5246 return 0;
29b0f896 5247 }
4eed87de
AM		 5248 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5249 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5250 i.rex |= REX_B;
4eed87de
AM		 5251 }
5252 else
5253 {
7ab9ffdd 5254 /* The register or float register operand is in operand
85f10a01 5255 0 or 1. */
40fb9820 5256 unsigned int op;
7ab9ffdd
L		 5257
5258 if (i.types[0].bitfield.floatreg
5259 || operand_type_check (i.types[0], reg))
5260 op = 0;
5261 else
5262 op = 1;
4eed87de
AM		 5263 /* Register goes in low 3 bits of opcode. */
5264 i.tm.base_opcode |= i.op[op].regs->reg_num;
5265 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5266 i.rex |= REX_B;
40fb9820 5267 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5268 {
4eed87de
AM		 5269 /* Warn about some common errors, but press on regardless.
5270 The first case can be generated by gcc (<= 2.8.1). */
5271 if (i.operands == 2)
5272 {
5273 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5274 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5275 register_prefix, i.op[!intel_syntax].regs->reg_name,
5276 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5277 }
5278 else
5279 {
5280 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5281 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5282 register_prefix, i.op[0].regs->reg_name);
4eed87de 5283 }
29b0f896
AM		 5284 }
5285 }
5286 }
40fb9820 5287 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5288 {
5289 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5290 must be put into the modrm byte). Now, we make the modrm and
5291 index base bytes based on all the info we've collected. */
29b0f896
AM		 5292
5293 default_seg = build_modrm_byte ();
5294 }
8a2ed489 5295 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5296 {
5297 default_seg = &ds;
5298 }
40fb9820 5299 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5300 {
5301 /* For the string instructions that allow a segment override
5302 on one of their operands, the default segment is ds. */
5303 default_seg = &ds;
5304 }
5305
75178d9d
L		 5306 if (i.tm.base_opcode == 0x8d /* lea */
5307 && i.seg[0]
5308 && !quiet_warnings)
30123838 5309 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5310
5311 /* If a segment was explicitly specified, and the specified segment
5312 is not the default, use an opcode prefix to select it. If we
5313 never figured out what the default segment is, then default_seg
5314 will be zero at this point, and the specified segment prefix will
5315 always be used. */
29b0f896
AM		 5316 if ((i.seg[0]) && (i.seg[0] != default_seg))
5317 {
5318 if (!add_prefix (i.seg[0]->seg_prefix))
5319 return 0;
5320 }
5321 return 1;
5322}
5323
5324static const seg_entry *
e3bb37b5 5325build_modrm_byte (void)
29b0f896
AM		 5326{
5327 const seg_entry *default_seg = 0;
c0f3af97 5328 unsigned int source, dest;
8cd7925b 5329 int vex_3_sources;
c0f3af97
L		 5330
5331 /* The first operand of instructions with VEX prefix and 3 sources
5332 must be VEX_Imm4. */
8cd7925b 5333 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5334 if (vex_3_sources)
5335 {
91d6fa6a 5336 unsigned int nds, reg_slot;
4c2c6516 5337 expressionS *exp;
c0f3af97 5338
922d8de8 5339 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5340 && i.tm.opcode_modifier.immext)
5341 {
5342 dest = i.operands - 2;
5343 gas_assert (dest == 3);
5344 }
922d8de8 5345 else
a683cc34 5346 dest = i.operands - 1;
c0f3af97 5347 nds = dest - 1;
922d8de8 5348
a683cc34
SP		 5349 /* There are 2 kinds of instructions:
5350 1. 5 operands: 4 register operands or 3 register operands
5351 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5352 VexW0 or VexW1. The destination must be either XMM or YMM
5353 register.
5354 2. 4 operands: 4 register operands or 3 register operands
5355 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5356 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5357 || (i.reg_operands == 3 && i.mem_operands == 1))
5358 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5359 && (i.tm.opcode_modifier.veximmext
5360 || (i.imm_operands == 1
5361 && i.types[0].bitfield.vec_imm4
5362 && (i.tm.opcode_modifier.vexw == VEXW0
5363 || i.tm.opcode_modifier.vexw == VEXW1)
5364 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5365 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5366
5367 if (i.imm_operands == 0)
5368 {
5369 /* When there is no immediate operand, generate an 8bit
5370 immediate operand to encode the first operand. */
5371 exp = &im_expressions[i.imm_operands++];
5372 i.op[i.operands].imms = exp;
5373 i.types[i.operands] = imm8;
5374 i.operands++;
5375 /* If VexW1 is set, the first operand is the source and
5376 the second operand is encoded in the immediate operand. */
5377 if (i.tm.opcode_modifier.vexw == VEXW1)
5378 {
5379 source = 0;
5380 reg_slot = 1;
5381 }
5382 else
5383 {
5384 source = 1;
5385 reg_slot = 0;
5386 }
5387
5388 /* FMA swaps REG and NDS. */
5389 if (i.tm.cpu_flags.bitfield.cpufma)
5390 {
5391 unsigned int tmp;
5392 tmp = reg_slot;
5393 reg_slot = nds;
5394 nds = tmp;
5395 }
5396
24981e7b
L		 5397 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5398 &regxmm)
a683cc34
SP		 5399 || operand_type_equal (&i.tm.operand_types[reg_slot],
5400 &regymm));
5401 exp->X_op = O_constant;
4c692bc7 5402 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
a683cc34 5403 }
922d8de8 5404 else
a683cc34
SP		 5405 {
5406 unsigned int imm_slot;
5407
5408 if (i.tm.opcode_modifier.vexw == VEXW0)
5409 {
5410 /* If VexW0 is set, the third operand is the source and
5411 the second operand is encoded in the immediate
5412 operand. */
5413 source = 2;
5414 reg_slot = 1;
5415 }
5416 else
5417 {
5418 /* VexW1 is set, the second operand is the source and
5419 the third operand is encoded in the immediate
5420 operand. */
5421 source = 1;
5422 reg_slot = 2;
5423 }
5424
5425 if (i.tm.opcode_modifier.immext)
5426 {
5427 /* When ImmExt is set, the immdiate byte is the last
5428 operand. */
5429 imm_slot = i.operands - 1;
5430 source--;
5431 reg_slot--;
5432 }
5433 else
5434 {
5435 imm_slot = 0;
5436
5437 /* Turn on Imm8 so that output_imm will generate it. */
5438 i.types[imm_slot].bitfield.imm8 = 1;
5439 }
5440
24981e7b
L		 5441 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5442 &regxmm)
5443 || operand_type_equal (&i.tm.operand_types[reg_slot],
5444 &regymm));
a683cc34 5445 i.op[imm_slot].imms->X_add_number
4c692bc7 5446 |= register_number (i.op[reg_slot].regs) << 4;
a683cc34
SP		 5447 }
5448
5449 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5450 || operand_type_equal (&i.tm.operand_types[nds],
5451 &regymm));
dae39acc 5452 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5453 }
5454 else
5455 source = dest = 0;
29b0f896
AM		 5456
5457 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5458 implicit registers do not count. If there are 3 register
5459 operands, it must be a instruction with VexNDS. For a
5460 instruction with VexNDD, the destination register is encoded
5461 in VEX prefix. If there are 4 register operands, it must be
5462 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5463 if (i.mem_operands == 0
5464 && ((i.reg_operands == 2
2426c15f 5465 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5466 || (i.reg_operands == 3
2426c15f 5467 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5468 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5469 {
cab737b9
L		 5470 switch (i.operands)
5471 {
5472 case 2:
5473 source = 0;
5474 break;
5475 case 3:
c81128dc
L		 5476 /* When there are 3 operands, one of them may be immediate,
5477 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5478 the first operand must be shift count register (cl) or it
5479 is an instruction with VexNDS. */
9c2799c2 5480 gas_assert (i.imm_operands == 1
7ab9ffdd 5481 || (i.imm_operands == 0
2426c15f 5482 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5483 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5484 if (operand_type_check (i.types[0], imm)
5485 || i.types[0].bitfield.shiftcount)
5486 source = 1;
5487 else
5488 source = 0;
cab737b9
L		 5489 break;
5490 case 4:
368d64cc
L		 5491 /* When there are 4 operands, the first two must be 8bit
5492 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5493 one.
5494
5495 For instructions with VexNDS, if the first operand
5496 an imm8, the source operand is the 2nd one. If the last
5497 operand is imm8, the source operand is the first one. */
9c2799c2 5498 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5499 && i.types[0].bitfield.imm8
5500 && i.types[1].bitfield.imm8)
2426c15f 5501 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5502 && i.imm_operands == 1
5503 && (i.types[0].bitfield.imm8
5504 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5505 if (i.imm_operands == 2)
5506 source = 2;
5507 else
c0f3af97
L		 5508 {
5509 if (i.types[0].bitfield.imm8)
5510 source = 1;
5511 else
5512 source = 0;
5513 }
c0f3af97
L		 5514 break;
5515 case 5:
cab737b9
L		 5516 break;
5517 default:
5518 abort ();
5519 }
5520
c0f3af97
L		 5521 if (!vex_3_sources)
5522 {
5523 dest = source + 1;
5524
2426c15f 5525 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5526 {
5527 /* For instructions with VexNDS, the register-only
f12dc422
L		 5528 source operand must be 32/64bit integer, XMM or
5529 YMM register. It is encoded in VEX prefix. We
5530 need to clear RegMem bit before calling
5531 operand_type_equal. */
5532
5533 i386_operand_type op;
5534 unsigned int vvvv;
5535
5536 /* Check register-only source operand when two source
5537 operands are swapped. */
5538 if (!i.tm.operand_types[source].bitfield.baseindex
5539 && i.tm.operand_types[dest].bitfield.baseindex)
5540 {
5541 vvvv = source;
5542 source = dest;
5543 }
5544 else
5545 vvvv = dest;
5546
5547 op = i.tm.operand_types[vvvv];
fa99fab2 5548 op.bitfield.regmem = 0;
c0f3af97 5549 if ((dest + 1) >= i.operands
f12dc422
L		 5550 || (op.bitfield.reg32 != 1
5551 && !op.bitfield.reg64 != 1
5552 && !operand_type_equal (&op, &regxmm)
fa99fab2 5553 && !operand_type_equal (&op, &regymm)))
c0f3af97 5554 abort ();
f12dc422 5555 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5556 dest++;
5557 }
5558 }
29b0f896
AM		 5559
5560 i.rm.mode = 3;
5561 /* One of the register operands will be encoded in the i.tm.reg
5562 field, the other in the combined i.tm.mode and i.tm.regmem
5563 fields. If no form of this instruction supports a memory
5564 destination operand, then we assume the source operand may
5565 sometimes be a memory operand and so we need to store the
5566 destination in the i.rm.reg field. */
40fb9820
L		 5567 if (!i.tm.operand_types[dest].bitfield.regmem
5568 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5569 {
5570 i.rm.reg = i.op[dest].regs->reg_num;
5571 i.rm.regmem = i.op[source].regs->reg_num;
5572 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5573 i.rex |= REX_R;
29b0f896 5574 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5575 i.rex |= REX_B;
29b0f896
AM		 5576 }
5577 else
5578 {
5579 i.rm.reg = i.op[source].regs->reg_num;
5580 i.rm.regmem = i.op[dest].regs->reg_num;
5581 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5582 i.rex |= REX_B;
29b0f896 5583 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5584 i.rex |= REX_R;
29b0f896 5585 }
161a04f6 5586 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5587 {
40fb9820
L		 5588 if (!i.types[0].bitfield.control
5589 && !i.types[1].bitfield.control)
c4a530c5 5590 abort ();
161a04f6 5591 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5592 add_prefix (LOCK_PREFIX_OPCODE);
5593 }
29b0f896
AM		 5594 }
5595 else
5596 { /* If it's not 2 reg operands... */
c0f3af97
L		 5597 unsigned int mem;
5598
29b0f896
AM		 5599 if (i.mem_operands)
5600 {
5601 unsigned int fake_zero_displacement = 0;
99018f42 5602 unsigned int op;
4eed87de 5603
7ab9ffdd
L		 5604 for (op = 0; op < i.operands; op++)
5605 if (operand_type_check (i.types[op], anymem))
5606 break;
7ab9ffdd 5607 gas_assert (op < i.operands);
29b0f896 5608
6c30d220
L		 5609 if (i.tm.opcode_modifier.vecsib)
5610 {
5611 if (i.index_reg->reg_num == RegEiz
5612 || i.index_reg->reg_num == RegRiz)
5613 abort ();
5614
5615 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5616 if (!i.base_reg)
5617 {
5618 i.sib.base = NO_BASE_REGISTER;
5619 i.sib.scale = i.log2_scale_factor;
5620 i.types[op].bitfield.disp8 = 0;
5621 i.types[op].bitfield.disp16 = 0;
5622 i.types[op].bitfield.disp64 = 0;
5623 if (flag_code != CODE_64BIT)
5624 {
5625 /* Must be 32 bit */
5626 i.types[op].bitfield.disp32 = 1;
5627 i.types[op].bitfield.disp32s = 0;
5628 }
5629 else
5630 {
5631 i.types[op].bitfield.disp32 = 0;
5632 i.types[op].bitfield.disp32s = 1;
5633 }
5634 }
5635 i.sib.index = i.index_reg->reg_num;
5636 if ((i.index_reg->reg_flags & RegRex) != 0)
5637 i.rex |= REX_X;
5638 }
5639
29b0f896
AM		 5640 default_seg = &ds;
5641
5642 if (i.base_reg == 0)
5643 {
5644 i.rm.mode = 0;
5645 if (!i.disp_operands)
6c30d220
L		 5646 {
5647 fake_zero_displacement = 1;
5648 /* Instructions with VSIB byte need 32bit displacement
5649 if there is no base register. */
5650 if (i.tm.opcode_modifier.vecsib)
5651 i.types[op].bitfield.disp32 = 1;
5652 }
29b0f896
AM		 5653 if (i.index_reg == 0)
5654 {
6c30d220 5655 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5656 /* Operand is just <disp> */
20f0a1fc 5657 if (flag_code == CODE_64BIT)
29b0f896
AM		 5658 {
5659 /* 64bit mode overwrites the 32bit absolute
5660 addressing by RIP relative addressing and
5661 absolute addressing is encoded by one of the
5662 redundant SIB forms. */
5663 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5664 i.sib.base = NO_BASE_REGISTER;
5665 i.sib.index = NO_INDEX_REGISTER;
fc225355 5666 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5667 ? disp32s : disp32);
20f0a1fc 5668 }
fc225355
L		 5669 else if ((flag_code == CODE_16BIT)
5670 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5671 {
5672 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5673 i.types[op] = disp16;
20f0a1fc
NC		 5674 }
5675 else
5676 {
5677 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5678 i.types[op] = disp32;
29b0f896
AM		 5679 }
5680 }
6c30d220 5681 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5682 {
6c30d220 5683 /* !i.base_reg && i.index_reg */
db51cc60
L		 5684 if (i.index_reg->reg_num == RegEiz
5685 || i.index_reg->reg_num == RegRiz)
5686 i.sib.index = NO_INDEX_REGISTER;
5687 else
5688 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5689 i.sib.base = NO_BASE_REGISTER;
5690 i.sib.scale = i.log2_scale_factor;
5691 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5692 i.types[op].bitfield.disp8 = 0;
5693 i.types[op].bitfield.disp16 = 0;
5694 i.types[op].bitfield.disp64 = 0;
29b0f896 5695 if (flag_code != CODE_64BIT)
40fb9820
L		 5696 {
5697 /* Must be 32 bit */
5698 i.types[op].bitfield.disp32 = 1;
5699 i.types[op].bitfield.disp32s = 0;
5700 }
29b0f896 5701 else
40fb9820
L		 5702 {
5703 i.types[op].bitfield.disp32 = 0;
5704 i.types[op].bitfield.disp32s = 1;
5705 }
29b0f896 5706 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5707 i.rex |= REX_X;
29b0f896
AM		 5708 }
5709 }
5710 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5711 else if (i.base_reg->reg_num == RegRip ||
5712 i.base_reg->reg_num == RegEip)
29b0f896 5713 {
6c30d220 5714 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5715 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5716 i.types[op].bitfield.disp8 = 0;
5717 i.types[op].bitfield.disp16 = 0;
5718 i.types[op].bitfield.disp32 = 0;
5719 i.types[op].bitfield.disp32s = 1;
5720 i.types[op].bitfield.disp64 = 0;
71903a11 5721 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5722 if (! i.disp_operands)
5723 fake_zero_displacement = 1;
29b0f896 5724 }
40fb9820 5725 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 5726 {
6c30d220 5727 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5728 switch (i.base_reg->reg_num)
5729 {
5730 case 3: /* (%bx) */
5731 if (i.index_reg == 0)
5732 i.rm.regmem = 7;
5733 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5734 i.rm.regmem = i.index_reg->reg_num - 6;
5735 break;
5736 case 5: /* (%bp) */
5737 default_seg = &ss;
5738 if (i.index_reg == 0)
5739 {
5740 i.rm.regmem = 6;
40fb9820 5741 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5742 {
5743 /* fake (%bp) into 0(%bp) */
40fb9820 5744 i.types[op].bitfield.disp8 = 1;
252b5132 5745 fake_zero_displacement = 1;
29b0f896
AM		 5746 }
5747 }
5748 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5749 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5750 break;
5751 default: /* (%si) -> 4 or (%di) -> 5 */
5752 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5753 }
5754 i.rm.mode = mode_from_disp_size (i.types[op]);
5755 }
5756 else /* i.base_reg and 32/64 bit mode */
5757 {
5758 if (flag_code == CODE_64BIT
40fb9820
L		 5759 && operand_type_check (i.types[op], disp))
5760 {
5761 i386_operand_type temp;
0dfbf9d7 5762 operand_type_set (&temp, 0);
40fb9820
L		 5763 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5764 i.types[op] = temp;
5765 if (i.prefix[ADDR_PREFIX] == 0)
5766 i.types[op].bitfield.disp32s = 1;
5767 else
5768 i.types[op].bitfield.disp32 = 1;
5769 }
20f0a1fc 5770
6c30d220
L		 5771 if (!i.tm.opcode_modifier.vecsib)
5772 i.rm.regmem = i.base_reg->reg_num;
29b0f896 5773 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5774 i.rex |= REX_B;
29b0f896
AM		 5775 i.sib.base = i.base_reg->reg_num;
5776 /* x86-64 ignores REX prefix bit here to avoid decoder
5777 complications. */
848930b2
JB		 5778 if (!(i.base_reg->reg_flags & RegRex)
5779 && (i.base_reg->reg_num == EBP_REG_NUM
5780 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 5781 default_seg = &ss;
848930b2 5782 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 5783 {
848930b2
JB		 5784 fake_zero_displacement = 1;
5785 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5786 }
5787 i.sib.scale = i.log2_scale_factor;
5788 if (i.index_reg == 0)
5789 {
6c30d220 5790 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5791 /* <disp>(%esp) becomes two byte modrm with no index
5792 register. We've already stored the code for esp
5793 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5794 Any base register besides %esp will not use the
5795 extra modrm byte. */
5796 i.sib.index = NO_INDEX_REGISTER;
29b0f896 5797 }
6c30d220 5798 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5799 {
db51cc60
L		 5800 if (i.index_reg->reg_num == RegEiz
5801 || i.index_reg->reg_num == RegRiz)
5802 i.sib.index = NO_INDEX_REGISTER;
5803 else
5804 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5805 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5806 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5807 i.rex |= REX_X;
29b0f896 5808 }
67a4f2b7
AO		 5809
5810 if (i.disp_operands
5811 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5812 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5813 i.rm.mode = 0;
5814 else
a501d77e
L		 5815 {
5816 if (!fake_zero_displacement
5817 && !i.disp_operands
5818 && i.disp_encoding)
5819 {
5820 fake_zero_displacement = 1;
5821 if (i.disp_encoding == disp_encoding_8bit)
5822 i.types[op].bitfield.disp8 = 1;
5823 else
5824 i.types[op].bitfield.disp32 = 1;
5825 }
5826 i.rm.mode = mode_from_disp_size (i.types[op]);
5827 }
29b0f896 5828 }
252b5132 5829
29b0f896
AM		 5830 if (fake_zero_displacement)
5831 {
5832 /* Fakes a zero displacement assuming that i.types[op]
5833 holds the correct displacement size. */
5834 expressionS *exp;
5835
9c2799c2 5836 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5837 exp = &disp_expressions[i.disp_operands++];
5838 i.op[op].disps = exp;
5839 exp->X_op = O_constant;
5840 exp->X_add_number = 0;
5841 exp->X_add_symbol = (symbolS *) 0;
5842 exp->X_op_symbol = (symbolS *) 0;
5843 }
c0f3af97
L		 5844
5845 mem = op;
29b0f896 5846 }
c0f3af97
L		 5847 else
5848 mem = ~0;
252b5132 5849
8c43a48b 5850 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5851 {
5852 if (operand_type_check (i.types[0], imm))
5853 i.vex.register_specifier = NULL;
5854 else
5855 {
5856 /* VEX.vvvv encodes one of the sources when the first
5857 operand is not an immediate. */
1ef99a7b 5858 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5859 i.vex.register_specifier = i.op[0].regs;
5860 else
5861 i.vex.register_specifier = i.op[1].regs;
5862 }
5863
5864 /* Destination is a XMM register encoded in the ModRM.reg
5865 and VEX.R bit. */
5866 i.rm.reg = i.op[2].regs->reg_num;
5867 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5868 i.rex |= REX_R;
5869
5870 /* ModRM.rm and VEX.B encodes the other source. */
5871 if (!i.mem_operands)
5872 {
5873 i.rm.mode = 3;
5874
1ef99a7b 5875 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5876 i.rm.regmem = i.op[1].regs->reg_num;
5877 else
5878 i.rm.regmem = i.op[0].regs->reg_num;
5879
5880 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5881 i.rex |= REX_B;
5882 }
5883 }
2426c15f 5884 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5885 {
5886 i.vex.register_specifier = i.op[2].regs;
5887 if (!i.mem_operands)
5888 {
5889 i.rm.mode = 3;
5890 i.rm.regmem = i.op[1].regs->reg_num;
5891 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5892 i.rex |= REX_B;
5893 }
5894 }
29b0f896
AM		 5895 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5896 (if any) based on i.tm.extension_opcode. Again, we must be
5897 careful to make sure that segment/control/debug/test/MMX
5898 registers are coded into the i.rm.reg field. */
f88c9eb0 5899 else if (i.reg_operands)
29b0f896 5900 {
99018f42 5901 unsigned int op;
7ab9ffdd
L		 5902 unsigned int vex_reg = ~0;
5903
5904 for (op = 0; op < i.operands; op++)
5905 if (i.types[op].bitfield.reg8
5906 || i.types[op].bitfield.reg16
5907 || i.types[op].bitfield.reg32
5908 || i.types[op].bitfield.reg64
5909 || i.types[op].bitfield.regmmx
5910 || i.types[op].bitfield.regxmm
5911 || i.types[op].bitfield.regymm
5912 || i.types[op].bitfield.sreg2
5913 || i.types[op].bitfield.sreg3
5914 || i.types[op].bitfield.control
5915 || i.types[op].bitfield.debug
5916 || i.types[op].bitfield.test)
5917 break;
c0209578 5918
7ab9ffdd
L		 5919 if (vex_3_sources)
5920 op = dest;
2426c15f 5921 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5922 {
5923 /* For instructions with VexNDS, the register-only
5924 source operand is encoded in VEX prefix. */
5925 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5926
7ab9ffdd 5927 if (op > mem)
c0f3af97 5928 {
7ab9ffdd
L		 5929 vex_reg = op++;
5930 gas_assert (op < i.operands);
c0f3af97
L		 5931 }
5932 else
c0f3af97 5933 {
f12dc422
L		 5934 /* Check register-only source operand when two source
5935 operands are swapped. */
5936 if (!i.tm.operand_types[op].bitfield.baseindex
5937 && i.tm.operand_types[op + 1].bitfield.baseindex)
5938 {
5939 vex_reg = op;
5940 op += 2;
5941 gas_assert (mem == (vex_reg + 1)
5942 && op < i.operands);
5943 }
5944 else
5945 {
5946 vex_reg = op + 1;
5947 gas_assert (vex_reg < i.operands);
5948 }
c0f3af97 5949 }
7ab9ffdd 5950 }
2426c15f 5951 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5952 {
f12dc422 5953 /* For instructions with VexNDD, the register destination
7ab9ffdd 5954 is encoded in VEX prefix. */
f12dc422
L		 5955 if (i.mem_operands == 0)
5956 {
5957 /* There is no memory operand. */
5958 gas_assert ((op + 2) == i.operands);
5959 vex_reg = op + 1;
5960 }
5961 else
8d63c93e 5962 {
f12dc422
L		 5963 /* There are only 2 operands. */
5964 gas_assert (op < 2 && i.operands == 2);
5965 vex_reg = 1;
5966 }
7ab9ffdd
L		 5967 }
5968 else
5969 gas_assert (op < i.operands);
99018f42 5970
7ab9ffdd
L		 5971 if (vex_reg != (unsigned int) ~0)
5972 {
f12dc422 5973 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5974
f12dc422
L		 5975 if (type->bitfield.reg32 != 1
5976 && type->bitfield.reg64 != 1
5977 && !operand_type_equal (type, &regxmm)
5978 && !operand_type_equal (type, &regymm))
7ab9ffdd 5979 abort ();
f88c9eb0 5980
7ab9ffdd
L		 5981 i.vex.register_specifier = i.op[vex_reg].regs;
5982 }
5983
1b9f0c97
L		 5984 /* Don't set OP operand twice. */
5985 if (vex_reg != op)
7ab9ffdd 5986 {
1b9f0c97
L		 5987 /* If there is an extension opcode to put here, the
5988 register number must be put into the regmem field. */
5989 if (i.tm.extension_opcode != None)
5990 {
5991 i.rm.regmem = i.op[op].regs->reg_num;
5992 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5993 i.rex |= REX_B;
5994 }
5995 else
5996 {
5997 i.rm.reg = i.op[op].regs->reg_num;
5998 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5999 i.rex |= REX_R;
6000 }
7ab9ffdd 6001 }
252b5132 6002
29b0f896
AM		 6003 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6004 must set it to 3 to indicate this is a register operand
6005 in the regmem field. */
6006 if (!i.mem_operands)
6007 i.rm.mode = 3;
6008 }
252b5132 6009
29b0f896 6010 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6011 if (i.tm.extension_opcode != None)
29b0f896
AM		 6012 i.rm.reg = i.tm.extension_opcode;
6013 }
6014 return default_seg;
6015}
252b5132 6016
29b0f896 6017static void
e3bb37b5 6018output_branch (void)
29b0f896
AM		 6019{
6020 char *p;
f8a5c266 6021 int size;
29b0f896
AM		 6022 int code16;
6023 int prefix;
6024 relax_substateT subtype;
6025 symbolS *sym;
6026 offsetT off;
6027
f8a5c266 6028 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6029 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6030
6031 prefix = 0;
6032 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6033 {
29b0f896
AM		 6034 prefix = 1;
6035 i.prefixes -= 1;
6036 code16 ^= CODE16;
252b5132 6037 }
29b0f896
AM		 6038 /* Pentium4 branch hints. */
6039 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6040 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6041 {
29b0f896
AM		 6042 prefix++;
6043 i.prefixes--;
6044 }
6045 if (i.prefix[REX_PREFIX] != 0)
6046 {
6047 prefix++;
6048 i.prefixes--;
2f66722d
AM		 6049 }
6050
29b0f896
AM		 6051 if (i.prefixes != 0 && !intel_syntax)
6052 as_warn (_("skipping prefixes on this instruction"));
6053
6054 /* It's always a symbol; End frag & setup for relax.
6055 Make sure there is enough room in this frag for the largest
6056 instruction we may generate in md_convert_frag. This is 2
6057 bytes for the opcode and room for the prefix and largest
6058 displacement. */
6059 frag_grow (prefix + 2 + 4);
6060 /* Prefix and 1 opcode byte go in fr_fix. */
6061 p = frag_more (prefix + 1);
6062 if (i.prefix[DATA_PREFIX] != 0)
6063 *p++ = DATA_PREFIX_OPCODE;
6064 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6065 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6066 *p++ = i.prefix[SEG_PREFIX];
6067 if (i.prefix[REX_PREFIX] != 0)
6068 *p++ = i.prefix[REX_PREFIX];
6069 *p = i.tm.base_opcode;
6070
6071 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6072 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6073 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6074 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6075 else
f8a5c266 6076 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6077 subtype |= code16;
3e73aa7c 6078
29b0f896
AM		 6079 sym = i.op[0].disps->X_add_symbol;
6080 off = i.op[0].disps->X_add_number;
3e73aa7c 6081
29b0f896
AM		 6082 if (i.op[0].disps->X_op != O_constant
6083 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6084 {
29b0f896
AM		 6085 /* Handle complex expressions. */
6086 sym = make_expr_symbol (i.op[0].disps);
6087 off = 0;
6088 }
3e73aa7c 6089
29b0f896
AM		 6090 /* 1 possible extra opcode + 4 byte displacement go in var part.
6091 Pass reloc in fr_var. */
6092 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
6093}
3e73aa7c 6094
29b0f896 6095static void
e3bb37b5 6096output_jump (void)
29b0f896
AM		 6097{
6098 char *p;
6099 int size;
3e02c1cc 6100 fixS *fixP;
29b0f896 6101
40fb9820 6102 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6103 {
6104 /* This is a loop or jecxz type instruction. */
6105 size = 1;
6106 if (i.prefix[ADDR_PREFIX] != 0)
6107 {
6108 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6109 i.prefixes -= 1;
6110 }
6111 /* Pentium4 branch hints. */
6112 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6113 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6114 {
6115 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6116 i.prefixes--;
3e73aa7c
JH		 6117 }
6118 }
29b0f896
AM		 6119 else
6120 {
6121 int code16;
3e73aa7c 6122
29b0f896
AM		 6123 code16 = 0;
6124 if (flag_code == CODE_16BIT)
6125 code16 = CODE16;
3e73aa7c 6126
29b0f896
AM		 6127 if (i.prefix[DATA_PREFIX] != 0)
6128 {
6129 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6130 i.prefixes -= 1;
6131 code16 ^= CODE16;
6132 }
252b5132 6133
29b0f896
AM		 6134 size = 4;
6135 if (code16)
6136 size = 2;
6137 }
9fcc94b6 6138
29b0f896
AM		 6139 if (i.prefix[REX_PREFIX] != 0)
6140 {
6141 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6142 i.prefixes -= 1;
6143 }
252b5132 6144
29b0f896
AM		 6145 if (i.prefixes != 0 && !intel_syntax)
6146 as_warn (_("skipping prefixes on this instruction"));
e0890092 6147
42164a71
L		 6148 p = frag_more (i.tm.opcode_length + size);
6149 switch (i.tm.opcode_length)
6150 {
6151 case 2:
6152 *p++ = i.tm.base_opcode >> 8;
6153 case 1:
6154 *p++ = i.tm.base_opcode;
6155 break;
6156 default:
6157 abort ();
6158 }
e0890092 6159
3e02c1cc
AM		 6160 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6161 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6162
6163 /* All jumps handled here are signed, but don't use a signed limit
6164 check for 32 and 16 bit jumps as we want to allow wrap around at
6165 4G and 64k respectively. */
6166 if (size == 1)
6167 fixP->fx_signed = 1;
29b0f896 6168}
e0890092 6169
29b0f896 6170static void
e3bb37b5 6171output_interseg_jump (void)
29b0f896
AM		 6172{
6173 char *p;
6174 int size;
6175 int prefix;
6176 int code16;
252b5132 6177
29b0f896
AM		 6178 code16 = 0;
6179 if (flag_code == CODE_16BIT)
6180 code16 = CODE16;
a217f122 6181
29b0f896
AM		 6182 prefix = 0;
6183 if (i.prefix[DATA_PREFIX] != 0)
6184 {
6185 prefix = 1;
6186 i.prefixes -= 1;
6187 code16 ^= CODE16;
6188 }
6189 if (i.prefix[REX_PREFIX] != 0)
6190 {
6191 prefix++;
6192 i.prefixes -= 1;
6193 }
252b5132 6194
29b0f896
AM		 6195 size = 4;
6196 if (code16)
6197 size = 2;
252b5132 6198
29b0f896
AM		 6199 if (i.prefixes != 0 && !intel_syntax)
6200 as_warn (_("skipping prefixes on this instruction"));
252b5132 6201
29b0f896
AM		 6202 /* 1 opcode; 2 segment; offset */
6203 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6204
29b0f896
AM		 6205 if (i.prefix[DATA_PREFIX] != 0)
6206 *p++ = DATA_PREFIX_OPCODE;
252b5132 6207
29b0f896
AM		 6208 if (i.prefix[REX_PREFIX] != 0)
6209 *p++ = i.prefix[REX_PREFIX];
252b5132 6210
29b0f896
AM		 6211 *p++ = i.tm.base_opcode;
6212 if (i.op[1].imms->X_op == O_constant)
6213 {
6214 offsetT n = i.op[1].imms->X_add_number;
252b5132 6215
29b0f896
AM		 6216 if (size == 2
6217 && !fits_in_unsigned_word (n)
6218 && !fits_in_signed_word (n))
6219 {
6220 as_bad (_("16-bit jump out of range"));
6221 return;
6222 }
6223 md_number_to_chars (p, n, size);
6224 }
6225 else
6226 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6227 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6228 if (i.op[0].imms->X_op != O_constant)
6229 as_bad (_("can't handle non absolute segment in `%s'"),
6230 i.tm.name);
6231 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6232}
a217f122 6233
29b0f896 6234static void
e3bb37b5 6235output_insn (void)
29b0f896 6236{
2bbd9c25
JJ		 6237 fragS *insn_start_frag;
6238 offsetT insn_start_off;
6239
29b0f896
AM		 6240 /* Tie dwarf2 debug info to the address at the start of the insn.
6241 We can't do this after the insn has been output as the current
6242 frag may have been closed off. eg. by frag_var. */
6243 dwarf2_emit_insn (0);
6244
2bbd9c25
JJ		 6245 insn_start_frag = frag_now;
6246 insn_start_off = frag_now_fix ();
6247
29b0f896 6248 /* Output jumps. */
40fb9820 6249 if (i.tm.opcode_modifier.jump)
29b0f896 6250 output_branch ();
40fb9820
L		 6251 else if (i.tm.opcode_modifier.jumpbyte
6252 || i.tm.opcode_modifier.jumpdword)
29b0f896 6253 output_jump ();
40fb9820 6254 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6255 output_interseg_jump ();
6256 else
6257 {
6258 /* Output normal instructions here. */
6259 char *p;
6260 unsigned char *q;
47465058 6261 unsigned int j;
331d2d0d 6262 unsigned int prefix;
4dffcebc 6263
c0f3af97 6264 /* Since the VEX prefix contains the implicit prefix, we don't
89e71f5c 6265 need the explicit prefix. */
c0f3af97 6266 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6267 {
c0f3af97 6268 switch (i.tm.opcode_length)
bc4bd9ab 6269 {
c0f3af97
L		 6270 case 3:
6271 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6272 {
c0f3af97
L		 6273 prefix = (i.tm.base_opcode >> 24) & 0xff;
6274 goto check_prefix;
6275 }
6276 break;
6277 case 2:
6278 if ((i.tm.base_opcode & 0xff0000) != 0)
6279 {
6280 prefix = (i.tm.base_opcode >> 16) & 0xff;
6281 if (i.tm.cpu_flags.bitfield.cpupadlock)
6282 {
4dffcebc 6283check_prefix:
c0f3af97 6284 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6285 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6286 != REPE_PREFIX_OPCODE))
6287 add_prefix (prefix);
6288 }
6289 else
4dffcebc
L		 6290 add_prefix (prefix);
6291 }
c0f3af97
L		 6292 break;
6293 case 1:
6294 break;
6295 default:
6296 abort ();
bc4bd9ab 6297 }
c0f3af97
L		 6298
6299 /* The prefix bytes. */
6300 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6301 if (*q)
6302 FRAG_APPEND_1_CHAR (*q);
0f10071e 6303 }
ae5c1c7b 6304 else
c0f3af97
L		 6305 {
6306 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6307 if (*q)
6308 switch (j)
6309 {
6310 case REX_PREFIX:
6311 /* REX byte is encoded in VEX prefix. */
6312 break;
6313 case SEG_PREFIX:
6314 case ADDR_PREFIX:
6315 FRAG_APPEND_1_CHAR (*q);
6316 break;
6317 default:
6318 /* There should be no other prefixes for instructions
6319 with VEX prefix. */
6320 abort ();
6321 }
6322
6323 /* Now the VEX prefix. */
6324 p = frag_more (i.vex.length);
6325 for (j = 0; j < i.vex.length; j++)
6326 p[j] = i.vex.bytes[j];
6327 }
252b5132 6328
29b0f896 6329 /* Now the opcode; be careful about word order here! */
4dffcebc 6330 if (i.tm.opcode_length == 1)
29b0f896
AM		 6331 {
6332 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6333 }
6334 else
6335 {
4dffcebc 6336 switch (i.tm.opcode_length)
331d2d0d 6337 {
4dffcebc 6338 case 3:
331d2d0d
L		 6339 p = frag_more (3);
6340 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6341 break;
6342 case 2:
6343 p = frag_more (2);
6344 break;
6345 default:
6346 abort ();
6347 break;
331d2d0d 6348 }
0f10071e 6349
29b0f896
AM		 6350 /* Put out high byte first: can't use md_number_to_chars! */
6351 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6352 *p = i.tm.base_opcode & 0xff;
6353 }
3e73aa7c 6354
29b0f896 6355 /* Now the modrm byte and sib byte (if present). */
40fb9820 6356 if (i.tm.opcode_modifier.modrm)
29b0f896 6357 {
4a3523fa
L		 6358 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6359 | i.rm.reg << 3
6360 | i.rm.mode << 6));
29b0f896
AM		 6361 /* If i.rm.regmem == ESP (4)
6362 && i.rm.mode != (Register mode)
6363 && not 16 bit
6364 ==> need second modrm byte. */
6365 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6366 && i.rm.mode != 3
40fb9820 6367 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6368 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6369 | i.sib.index << 3
6370 | i.sib.scale << 6));
29b0f896 6371 }
3e73aa7c 6372
29b0f896 6373 if (i.disp_operands)
2bbd9c25 6374 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6375
29b0f896 6376 if (i.imm_operands)
2bbd9c25 6377 output_imm (insn_start_frag, insn_start_off);
29b0f896 6378 }
252b5132 6379
29b0f896
AM		 6380#ifdef DEBUG386
6381 if (flag_debug)
6382 {
7b81dfbb 6383 pi ("" /*line*/, &i);
29b0f896
AM		 6384 }
6385#endif /* DEBUG386 */
6386}
252b5132 6387
e205caa7
L		 6388/* Return the size of the displacement operand N. */
6389
6390static int
6391disp_size (unsigned int n)
6392{
6393 int size = 4;
40fb9820
L		 6394 if (i.types[n].bitfield.disp64)
6395 size = 8;
6396 else if (i.types[n].bitfield.disp8)
6397 size = 1;
6398 else if (i.types[n].bitfield.disp16)
6399 size = 2;
e205caa7
L		 6400 return size;
6401}
6402
6403/* Return the size of the immediate operand N. */
6404
6405static int
6406imm_size (unsigned int n)
6407{
6408 int size = 4;
40fb9820
L		 6409 if (i.types[n].bitfield.imm64)
6410 size = 8;
6411 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6412 size = 1;
6413 else if (i.types[n].bitfield.imm16)
6414 size = 2;
e205caa7
L		 6415 return size;
6416}
6417
29b0f896 6418static void
64e74474 6419output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6420{
6421 char *p;
6422 unsigned int n;
252b5132 6423
29b0f896
AM		 6424 for (n = 0; n < i.operands; n++)
6425 {
40fb9820 6426 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6427 {
6428 if (i.op[n].disps->X_op == O_constant)
6429 {
e205caa7 6430 int size = disp_size (n);
29b0f896 6431 offsetT val;
252b5132 6432
29b0f896
AM		 6433 val = offset_in_range (i.op[n].disps->X_add_number,
6434 size);
6435 p = frag_more (size);
6436 md_number_to_chars (p, val, size);
6437 }
6438 else
6439 {
f86103b7 6440 enum bfd_reloc_code_real reloc_type;
e205caa7 6441 int size = disp_size (n);
40fb9820 6442 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6443 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6444
e205caa7 6445 /* We can't have 8 bit displacement here. */
9c2799c2 6446 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6447
29b0f896
AM		 6448 /* The PC relative address is computed relative
6449 to the instruction boundary, so in case immediate
6450 fields follows, we need to adjust the value. */
6451 if (pcrel && i.imm_operands)
6452 {
29b0f896 6453 unsigned int n1;
e205caa7 6454 int sz = 0;
252b5132 6455
29b0f896 6456 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6457 if (operand_type_check (i.types[n1], imm))
252b5132 6458 {
e205caa7
L		 6459 /* Only one immediate is allowed for PC
6460 relative address. */
9c2799c2 6461 gas_assert (sz == 0);
e205caa7
L		 6462 sz = imm_size (n1);
6463 i.op[n].disps->X_add_number -= sz;
252b5132 6464 }
29b0f896 6465 /* We should find the immediate. */
9c2799c2 6466 gas_assert (sz != 0);
29b0f896 6467 }
520dc8e8 6468
29b0f896 6469 p = frag_more (size);
2bbd9c25 6470 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6471 if (GOT_symbol
2bbd9c25 6472 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6473 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6474 || reloc_type == BFD_RELOC_X86_64_32S
6475 || (reloc_type == BFD_RELOC_64
6476 && object_64bit))
d6ab8113
JB		 6477 && (i.op[n].disps->X_op == O_symbol
6478 || (i.op[n].disps->X_op == O_add
6479 && ((symbol_get_value_expression
6480 (i.op[n].disps->X_op_symbol)->X_op)
6481 == O_subtract))))
6482 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6483 {
6484 offsetT add;
6485
6486 if (insn_start_frag == frag_now)
6487 add = (p - frag_now->fr_literal) - insn_start_off;
6488 else
6489 {
6490 fragS *fr;
6491
6492 add = insn_start_frag->fr_fix - insn_start_off;
6493 for (fr = insn_start_frag->fr_next;
6494 fr && fr != frag_now; fr = fr->fr_next)
6495 add += fr->fr_fix;
6496 add += p - frag_now->fr_literal;
6497 }
6498
4fa24527 6499 if (!object_64bit)
7b81dfbb
AJ		 6500 {
6501 reloc_type = BFD_RELOC_386_GOTPC;
6502 i.op[n].imms->X_add_number += add;
6503 }
6504 else if (reloc_type == BFD_RELOC_64)
6505 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6506 else
7b81dfbb
AJ		 6507 /* Don't do the adjustment for x86-64, as there
6508 the pcrel addressing is relative to the _next_
6509 insn, and that is taken care of in other code. */
d6ab8113 6510 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6511 }
062cd5e7 6512 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6513 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6514 }
6515 }
6516 }
6517}
252b5132 6518
29b0f896 6519static void
64e74474 6520output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6521{
6522 char *p;
6523 unsigned int n;
252b5132 6524
29b0f896
AM		 6525 for (n = 0; n < i.operands; n++)
6526 {
40fb9820 6527 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6528 {
6529 if (i.op[n].imms->X_op == O_constant)
6530 {
e205caa7 6531 int size = imm_size (n);
29b0f896 6532 offsetT val;
b4cac588 6533
29b0f896
AM		 6534 val = offset_in_range (i.op[n].imms->X_add_number,
6535 size);
6536 p = frag_more (size);
6537 md_number_to_chars (p, val, size);
6538 }
6539 else
6540 {
6541 /* Not absolute_section.
6542 Need a 32-bit fixup (don't support 8bit
6543 non-absolute imms). Try to support other
6544 sizes ... */
f86103b7 6545 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6546 int size = imm_size (n);
6547 int sign;
29b0f896 6548
40fb9820 6549 if (i.types[n].bitfield.imm32s
a7d61044 6550 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6551 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6552 sign = 1;
e205caa7
L		 6553 else
6554 sign = 0;
520dc8e8 6555
29b0f896
AM		 6556 p = frag_more (size);
6557 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6558
2bbd9c25
JJ		 6559 /* This is tough to explain. We end up with this one if we
6560 * have operands that look like
6561 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6562 * obtain the absolute address of the GOT, and it is strongly
6563 * preferable from a performance point of view to avoid using
6564 * a runtime relocation for this. The actual sequence of
6565 * instructions often look something like:
6566 *
6567 * call .L66
6568 * .L66:
6569 * popl %ebx
6570 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6571 *
6572 * The call and pop essentially return the absolute address
6573 * of the label .L66 and store it in %ebx. The linker itself
6574 * will ultimately change the first operand of the addl so
6575 * that %ebx points to the GOT, but to keep things simple, the
6576 * .o file must have this operand set so that it generates not
6577 * the absolute address of .L66, but the absolute address of
6578 * itself. This allows the linker itself simply treat a GOTPC
6579 * relocation as asking for a pcrel offset to the GOT to be
6580 * added in, and the addend of the relocation is stored in the
6581 * operand field for the instruction itself.
6582 *
6583 * Our job here is to fix the operand so that it would add
6584 * the correct offset so that %ebx would point to itself. The
6585 * thing that is tricky is that .-.L66 will point to the
6586 * beginning of the instruction, so we need to further modify
6587 * the operand so that it will point to itself. There are
6588 * other cases where you have something like:
6589 *
6590 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6591 *
6592 * and here no correction would be required. Internally in
6593 * the assembler we treat operands of this form as not being
6594 * pcrel since the '.' is explicitly mentioned, and I wonder
6595 * whether it would simplify matters to do it this way. Who
6596 * knows. In earlier versions of the PIC patches, the
6597 * pcrel_adjust field was used to store the correction, but
6598 * since the expression is not pcrel, I felt it would be
6599 * confusing to do it this way. */
6600
d6ab8113 6601 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6602 || reloc_type == BFD_RELOC_X86_64_32S
6603 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6604 && GOT_symbol
6605 && GOT_symbol == i.op[n].imms->X_add_symbol
6606 && (i.op[n].imms->X_op == O_symbol
6607 || (i.op[n].imms->X_op == O_add
6608 && ((symbol_get_value_expression
6609 (i.op[n].imms->X_op_symbol)->X_op)
6610 == O_subtract))))
6611 {
2bbd9c25
JJ		 6612 offsetT add;
6613
6614 if (insn_start_frag == frag_now)
6615 add = (p - frag_now->fr_literal) - insn_start_off;
6616 else
6617 {
6618 fragS *fr;
6619
6620 add = insn_start_frag->fr_fix - insn_start_off;
6621 for (fr = insn_start_frag->fr_next;
6622 fr && fr != frag_now; fr = fr->fr_next)
6623 add += fr->fr_fix;
6624 add += p - frag_now->fr_literal;
6625 }
6626
4fa24527 6627 if (!object_64bit)
d6ab8113 6628 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6629 else if (size == 4)
d6ab8113 6630 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6631 else if (size == 8)
6632 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6633 i.op[n].imms->X_add_number += add;
29b0f896 6634 }
29b0f896
AM		 6635 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6636 i.op[n].imms, 0, reloc_type);
6637 }
6638 }
6639 }
252b5132
RH		 6640}
6641\f
d182319b
JB		 6642/* x86_cons_fix_new is called via the expression parsing code when a
6643 reloc is needed. We use this hook to get the correct .got reloc. */
6644static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6645static int cons_sign = -1;
6646
6647void
e3bb37b5 6648x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6649 expressionS *exp)
d182319b
JB		 6650{
6651 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6652
6653 got_reloc = NO_RELOC;
6654
6655#ifdef TE_PE
6656 if (exp->X_op == O_secrel)
6657 {
6658 exp->X_op = O_symbol;
6659 r = BFD_RELOC_32_SECREL;
6660 }
6661#endif
6662
6663 fix_new_exp (frag, off, len, exp, 0, r);
6664}
6665
357d1bd8
L		 6666/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6667 purpose of the `.dc.a' internal pseudo-op. */
6668
6669int
6670x86_address_bytes (void)
6671{
6672 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
6673 return 4;
6674 return stdoutput->arch_info->bits_per_address / 8;
6675}
6676
d382c579
TG		 6677#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6678 || defined (LEX_AT)
718ddfc0
JB		 6679# define lex_got(reloc, adjust, types) NULL
6680#else
f3c180ae
AM		 6681/* Parse operands of the form
6682 <symbol>@GOTOFF+<nnn>
6683 and similar .plt or .got references.
6684
6685 If we find one, set up the correct relocation in RELOC and copy the
6686 input string, minus the `@GOTOFF' into a malloc'd buffer for
6687 parsing by the calling routine. Return this buffer, and if ADJUST
6688 is non-null set it to the length of the string we removed from the
6689 input line. Otherwise return NULL. */
6690static char *
91d6fa6a 6691lex_got (enum bfd_reloc_code_real *rel,
64e74474 6692 int *adjust,
40fb9820 6693 i386_operand_type *types)
f3c180ae 6694{
7b81dfbb
AJ		 6695 /* Some of the relocations depend on the size of what field is to
6696 be relocated. But in our callers i386_immediate and i386_displacement
6697 we don't yet know the operand size (this will be set by insn
6698 matching). Hence we record the word32 relocation here,
6699 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6700 static const struct {
6701 const char *str;
cff8d58a 6702 int len;
4fa24527 6703 const enum bfd_reloc_code_real rel[2];
40fb9820 6704 const i386_operand_type types64;
f3c180ae 6705 } gotrel[] = {
8ce3d284 6706#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 6707 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
6708 BFD_RELOC_SIZE32 },
6709 OPERAND_TYPE_IMM32_64 },
8ce3d284 6710#endif
cff8d58a
L		 6711 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6712 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6713 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6714 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6715 BFD_RELOC_X86_64_PLT32 },
40fb9820 6716 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6717 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6718 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6719 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6720 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6721 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6722 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6723 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6724 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6725 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6726 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6727 BFD_RELOC_X86_64_TLSGD },
40fb9820 6728 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6729 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6730 _dummy_first_bfd_reloc_code_real },
40fb9820 6731 OPERAND_TYPE_NONE },
cff8d58a
L		 6732 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6733 BFD_RELOC_X86_64_TLSLD },
40fb9820 6734 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6735 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6736 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6737 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6738 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6739 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6740 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6741 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6742 _dummy_first_bfd_reloc_code_real },
40fb9820 6743 OPERAND_TYPE_NONE },
cff8d58a
L		 6744 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6745 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6746 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6747 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6748 _dummy_first_bfd_reloc_code_real },
40fb9820 6749 OPERAND_TYPE_NONE },
cff8d58a
L		 6750 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6751 _dummy_first_bfd_reloc_code_real },
40fb9820 6752 OPERAND_TYPE_NONE },
cff8d58a
L		 6753 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6754 BFD_RELOC_X86_64_GOT32 },
40fb9820 6755 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6756 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6757 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6758 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6759 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6760 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6761 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6762 };
6763 char *cp;
6764 unsigned int j;
6765
d382c579 6766#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 6767 if (!IS_ELF)
6768 return NULL;
d382c579 6769#endif
718ddfc0 6770
f3c180ae 6771 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6772 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6773 return NULL;
6774
47465058 6775 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6776 {
cff8d58a 6777 int len = gotrel[j].len;
28f81592 6778 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6779 {
4fa24527 6780 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6781 {
28f81592
AM		 6782 int first, second;
6783 char *tmpbuf, *past_reloc;
f3c180ae 6784
91d6fa6a 6785 *rel = gotrel[j].rel[object_64bit];
f3c180ae 6786
3956db08
JB		 6787 if (types)
6788 {
6789 if (flag_code != CODE_64BIT)
40fb9820
L		 6790 {
6791 types->bitfield.imm32 = 1;
6792 types->bitfield.disp32 = 1;
6793 }
3956db08
JB		 6794 else
6795 *types = gotrel[j].types64;
6796 }
6797
8fd4256d 6798 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 6799 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6800
28f81592 6801 /* The length of the first part of our input line. */
f3c180ae 6802 first = cp - input_line_pointer;
28f81592
AM		 6803
6804 /* The second part goes from after the reloc token until
67c11a9b 6805 (and including) an end_of_line char or comma. */
28f81592 6806 past_reloc = cp + 1 + len;
67c11a9b
AM		 6807 cp = past_reloc;
6808 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6809 ++cp;
6810 second = cp + 1 - past_reloc;
28f81592
AM		 6811
6812 /* Allocate and copy string. The trailing NUL shouldn't
6813 be necessary, but be safe. */
1e9cc1c2 6814 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6815 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6816 if (second != 0 && *past_reloc != ' ')
6817 /* Replace the relocation token with ' ', so that
6818 errors like foo@GOTOFF1 will be detected. */
6819 tmpbuf[first++] = ' ';
af89796a
L		 6820 else
6821 /* Increment length by 1 if the relocation token is
6822 removed. */
6823 len++;
6824 if (adjust)
6825 *adjust = len;
0787a12d
AM		 6826 memcpy (tmpbuf + first, past_reloc, second);
6827 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6828 return tmpbuf;
6829 }
6830
4fa24527
JB		 6831 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6832 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6833 return NULL;
6834 }
6835 }
6836
6837 /* Might be a symbol version string. Don't as_bad here. */
6838 return NULL;
6839}
4e4f7c87 6840#endif
f3c180ae 6841
a988325c
NC		 6842#ifdef TE_PE
6843#ifdef lex_got
6844#undef lex_got
6845#endif
6846/* Parse operands of the form
6847 <symbol>@SECREL32+<nnn>
6848
6849 If we find one, set up the correct relocation in RELOC and copy the
6850 input string, minus the `@SECREL32' into a malloc'd buffer for
6851 parsing by the calling routine. Return this buffer, and if ADJUST
6852 is non-null set it to the length of the string we removed from the
34bca508
L		 6853 input line. Otherwise return NULL.
6854
a988325c
NC		 6855 This function is copied from the ELF version above adjusted for PE targets. */
6856
6857static char *
6858lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
6859 int *adjust ATTRIBUTE_UNUSED,
6860 i386_operand_type *types ATTRIBUTE_UNUSED)
6861{
6862 static const struct
6863 {
6864 const char *str;
6865 int len;
6866 const enum bfd_reloc_code_real rel[2];
6867 const i386_operand_type types64;
6868 }
6869 gotrel[] =
6870 {
6871 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
6872 BFD_RELOC_32_SECREL },
6873 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6874 };
6875
6876 char *cp;
6877 unsigned j;
6878
6879 for (cp = input_line_pointer; *cp != '@'; cp++)
6880 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
6881 return NULL;
6882
6883 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
6884 {
6885 int len = gotrel[j].len;
6886
6887 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
6888 {
6889 if (gotrel[j].rel[object_64bit] != 0)
6890 {
6891 int first, second;
6892 char *tmpbuf, *past_reloc;
6893
6894 *rel = gotrel[j].rel[object_64bit];
6895 if (adjust)
6896 *adjust = len;
6897
6898 if (types)
6899 {
6900 if (flag_code != CODE_64BIT)
6901 {
6902 types->bitfield.imm32 = 1;
6903 types->bitfield.disp32 = 1;
6904 }
6905 else
6906 *types = gotrel[j].types64;
6907 }
6908
6909 /* The length of the first part of our input line. */
6910 first = cp - input_line_pointer;
6911
6912 /* The second part goes from after the reloc token until
6913 (and including) an end_of_line char or comma. */
6914 past_reloc = cp + 1 + len;
6915 cp = past_reloc;
6916 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6917 ++cp;
6918 second = cp + 1 - past_reloc;
6919
6920 /* Allocate and copy string. The trailing NUL shouldn't
6921 be necessary, but be safe. */
6922 tmpbuf = (char *) xmalloc (first + second + 2);
6923 memcpy (tmpbuf, input_line_pointer, first);
6924 if (second != 0 && *past_reloc != ' ')
6925 /* Replace the relocation token with ' ', so that
6926 errors like foo@SECLREL321 will be detected. */
6927 tmpbuf[first++] = ' ';
6928 memcpy (tmpbuf + first, past_reloc, second);
6929 tmpbuf[first + second] = '\0';
6930 return tmpbuf;
6931 }
6932
6933 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6934 gotrel[j].str, 1 << (5 + object_64bit));
6935 return NULL;
6936 }
6937 }
6938
6939 /* Might be a symbol version string. Don't as_bad here. */
6940 return NULL;
6941}
6942
6943#endif /* TE_PE */
6944
f3c180ae 6945void
e3bb37b5 6946x86_cons (expressionS *exp, int size)
f3c180ae 6947{
ee86248c
JB		 6948 intel_syntax = -intel_syntax;
6949
3c7b9c2c 6950 exp->X_md = 0;
4fa24527 6951 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6952 {
6953 /* Handle @GOTOFF and the like in an expression. */
6954 char *save;
6955 char *gotfree_input_line;
4a57f2cf 6956 int adjust = 0;
f3c180ae
AM		 6957
6958 save = input_line_pointer;
3956db08 6959 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6960 if (gotfree_input_line)
6961 input_line_pointer = gotfree_input_line;
6962
6963 expression (exp);
6964
6965 if (gotfree_input_line)
6966 {
6967 /* expression () has merrily parsed up to the end of line,
6968 or a comma - in the wrong buffer. Transfer how far
6969 input_line_pointer has moved to the right buffer. */
6970 input_line_pointer = (save
6971 + (input_line_pointer - gotfree_input_line)
6972 + adjust);
6973 free (gotfree_input_line);
3992d3b7
AM		 6974 if (exp->X_op == O_constant
6975 || exp->X_op == O_absent
6976 || exp->X_op == O_illegal
0398aac5 6977 || exp->X_op == O_register
3992d3b7
AM		 6978 || exp->X_op == O_big)
6979 {
6980 char c = *input_line_pointer;
6981 *input_line_pointer = 0;
6982 as_bad (_("missing or invalid expression `%s'"), save);
6983 *input_line_pointer = c;
6984 }
f3c180ae
AM		 6985 }
6986 }
6987 else
6988 expression (exp);
ee86248c
JB		 6989
6990 intel_syntax = -intel_syntax;
6991
6992 if (intel_syntax)
6993 i386_intel_simplify (exp);
f3c180ae 6994}
f3c180ae 6995
9f32dd5b
L		 6996static void
6997signed_cons (int size)
6482c264 6998{
d182319b
JB		 6999 if (flag_code == CODE_64BIT)
7000 cons_sign = 1;
7001 cons (size);
7002 cons_sign = -1;
6482c264
NC		 7003}
7004
d182319b 7005#ifdef TE_PE
6482c264 7006static void
7016a5d5 7007pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7008{
7009 expressionS exp;
7010
7011 do
7012 {
7013 expression (&exp);
7014 if (exp.X_op == O_symbol)
7015 exp.X_op = O_secrel;
7016
7017 emit_expr (&exp, 4);
7018 }
7019 while (*input_line_pointer++ == ',');
7020
7021 input_line_pointer--;
7022 demand_empty_rest_of_line ();
7023}
6482c264
NC		 7024#endif
7025
252b5132 7026static int
70e41ade 7027i386_immediate (char *imm_start)
252b5132
RH		 7028{
7029 char *save_input_line_pointer;
f3c180ae 7030 char *gotfree_input_line;
252b5132 7031 segT exp_seg = 0;
47926f60 7032 expressionS *exp;
40fb9820
L		 7033 i386_operand_type types;
7034
0dfbf9d7 7035 operand_type_set (&types, ~0);
252b5132
RH		 7036
7037 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7038 {
31b2323c
L		 7039 as_bad (_("at most %d immediate operands are allowed"),
7040 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7041 return 0;
7042 }
7043
7044 exp = &im_expressions[i.imm_operands++];
520dc8e8 7045 i.op[this_operand].imms = exp;
252b5132
RH		 7046
7047 if (is_space_char (*imm_start))
7048 ++imm_start;
7049
7050 save_input_line_pointer = input_line_pointer;
7051 input_line_pointer = imm_start;
7052
3956db08 7053 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7054 if (gotfree_input_line)
7055 input_line_pointer = gotfree_input_line;
252b5132
RH		 7056
7057 exp_seg = expression (exp);
7058
83183c0c 7059 SKIP_WHITESPACE ();
252b5132 7060 if (*input_line_pointer)
f3c180ae 7061 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7062
7063 input_line_pointer = save_input_line_pointer;
f3c180ae 7064 if (gotfree_input_line)
ee86248c
JB		 7065 {
7066 free (gotfree_input_line);
7067
7068 if (exp->X_op == O_constant || exp->X_op == O_register)
7069 exp->X_op = O_illegal;
7070 }
7071
7072 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7073}
252b5132 7074
ee86248c
JB		 7075static int
7076i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7077 i386_operand_type types, const char *imm_start)
7078{
7079 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7080 {
313c53d1
L		 7081 if (imm_start)
7082 as_bad (_("missing or invalid immediate expression `%s'"),
7083 imm_start);
3992d3b7 7084 return 0;
252b5132 7085 }
3e73aa7c 7086 else if (exp->X_op == O_constant)
252b5132 7087 {
47926f60 7088 /* Size it properly later. */
40fb9820 7089 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7090 /* If not 64bit, sign extend val. */
7091 if (flag_code != CODE_64BIT
4eed87de
AM		 7092 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7093 exp->X_add_number
7094 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7095 }
4c63da97 7096#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7097 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7098 && exp_seg != absolute_section
47926f60 7099 && exp_seg != text_section
24eab124
AM		 7100 && exp_seg != data_section
7101 && exp_seg != bss_section
7102 && exp_seg != undefined_section
f86103b7 7103 && !bfd_is_com_section (exp_seg))
252b5132 7104 {
d0b47220 7105 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7106 return 0;
7107 }
7108#endif
bb8f5920
L		 7109 else if (!intel_syntax && exp->X_op == O_register)
7110 {
313c53d1
L		 7111 if (imm_start)
7112 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7113 return 0;
7114 }
252b5132
RH		 7115 else
7116 {
7117 /* This is an address. The size of the address will be
24eab124 7118 determined later, depending on destination register,
3e73aa7c 7119 suffix, or the default for the section. */
40fb9820
L		 7120 i.types[this_operand].bitfield.imm8 = 1;
7121 i.types[this_operand].bitfield.imm16 = 1;
7122 i.types[this_operand].bitfield.imm32 = 1;
7123 i.types[this_operand].bitfield.imm32s = 1;
7124 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7125 i.types[this_operand] = operand_type_and (i.types[this_operand],
7126 types);
252b5132
RH		 7127 }
7128
7129 return 1;
7130}
7131
551c1ca1 7132static char *
e3bb37b5 7133i386_scale (char *scale)
252b5132 7134{
551c1ca1
AM		 7135 offsetT val;
7136 char *save = input_line_pointer;
252b5132 7137
551c1ca1
AM		 7138 input_line_pointer = scale;
7139 val = get_absolute_expression ();
7140
7141 switch (val)
252b5132 7142 {
551c1ca1 7143 case 1:
252b5132
RH		 7144 i.log2_scale_factor = 0;
7145 break;
551c1ca1 7146 case 2:
252b5132
RH		 7147 i.log2_scale_factor = 1;
7148 break;
551c1ca1 7149 case 4:
252b5132
RH		 7150 i.log2_scale_factor = 2;
7151 break;
551c1ca1 7152 case 8:
252b5132
RH		 7153 i.log2_scale_factor = 3;
7154 break;
7155 default:
a724f0f4
JB		 7156 {
7157 char sep = *input_line_pointer;
7158
7159 *input_line_pointer = '\0';
7160 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7161 scale);
7162 *input_line_pointer = sep;
7163 input_line_pointer = save;
7164 return NULL;
7165 }
252b5132 7166 }
29b0f896 7167 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7168 {
7169 as_warn (_("scale factor of %d without an index register"),
24eab124 7170 1 << i.log2_scale_factor);
252b5132 7171 i.log2_scale_factor = 0;
252b5132 7172 }
551c1ca1
AM		 7173 scale = input_line_pointer;
7174 input_line_pointer = save;
7175 return scale;
252b5132
RH		 7176}
7177
252b5132 7178static int
e3bb37b5 7179i386_displacement (char *disp_start, char *disp_end)
252b5132 7180{
29b0f896 7181 expressionS *exp;
252b5132
RH		 7182 segT exp_seg = 0;
7183 char *save_input_line_pointer;
f3c180ae 7184 char *gotfree_input_line;
40fb9820
L		 7185 int override;
7186 i386_operand_type bigdisp, types = anydisp;
3992d3b7 7187 int ret;
252b5132 7188
31b2323c
L		 7189 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7190 {
7191 as_bad (_("at most %d displacement operands are allowed"),
7192 MAX_MEMORY_OPERANDS);
7193 return 0;
7194 }
7195
0dfbf9d7 7196 operand_type_set (&bigdisp, 0);
40fb9820
L		 7197 if ((i.types[this_operand].bitfield.jumpabsolute)
7198 || (!current_templates->start->opcode_modifier.jump
7199 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 7200 {
40fb9820 7201 bigdisp.bitfield.disp32 = 1;
e05278af 7202 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 7203 if (flag_code == CODE_64BIT)
7204 {
7205 if (!override)
7206 {
7207 bigdisp.bitfield.disp32s = 1;
7208 bigdisp.bitfield.disp64 = 1;
7209 }
7210 }
7211 else if ((flag_code == CODE_16BIT) ^ override)
7212 {
7213 bigdisp.bitfield.disp32 = 0;
7214 bigdisp.bitfield.disp16 = 1;
7215 }
e05278af
JB		 7216 }
7217 else
7218 {
7219 /* For PC-relative branches, the width of the displacement
7220 is dependent upon data size, not address size. */
e05278af 7221 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 7222 if (flag_code == CODE_64BIT)
7223 {
7224 if (override || i.suffix == WORD_MNEM_SUFFIX)
7225 bigdisp.bitfield.disp16 = 1;
7226 else
7227 {
7228 bigdisp.bitfield.disp32 = 1;
7229 bigdisp.bitfield.disp32s = 1;
7230 }
7231 }
7232 else
e05278af
JB		 7233 {
7234 if (!override)
7235 override = (i.suffix == (flag_code != CODE_16BIT
7236 ? WORD_MNEM_SUFFIX
7237 : LONG_MNEM_SUFFIX));
40fb9820
L		 7238 bigdisp.bitfield.disp32 = 1;
7239 if ((flag_code == CODE_16BIT) ^ override)
7240 {
7241 bigdisp.bitfield.disp32 = 0;
7242 bigdisp.bitfield.disp16 = 1;
7243 }
e05278af 7244 }
e05278af 7245 }
c6fb90c8
L		 7246 i.types[this_operand] = operand_type_or (i.types[this_operand],
7247 bigdisp);
252b5132
RH		 7248
7249 exp = &disp_expressions[i.disp_operands];
520dc8e8 7250 i.op[this_operand].disps = exp;
252b5132
RH		 7251 i.disp_operands++;
7252 save_input_line_pointer = input_line_pointer;
7253 input_line_pointer = disp_start;
7254 END_STRING_AND_SAVE (disp_end);
7255
7256#ifndef GCC_ASM_O_HACK
7257#define GCC_ASM_O_HACK 0
7258#endif
7259#if GCC_ASM_O_HACK
7260 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 7261 if (i.types[this_operand].bitfield.baseIndex
24eab124 7262 && displacement_string_end[-1] == '+')
252b5132
RH		 7263 {
7264 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 7265 constraint within gcc asm statements.
7266 For instance:
7267
7268 #define _set_tssldt_desc(n,addr,limit,type) \
7269 __asm__ __volatile__ ( \
7270 "movw %w2,%0\n\t" \
7271 "movw %w1,2+%0\n\t" \
7272 "rorl $16,%1\n\t" \
7273 "movb %b1,4+%0\n\t" \
7274 "movb %4,5+%0\n\t" \
7275 "movb $0,6+%0\n\t" \
7276 "movb %h1,7+%0\n\t" \
7277 "rorl $16,%1" \
7278 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7279
7280 This works great except that the output assembler ends
7281 up looking a bit weird if it turns out that there is
7282 no offset. You end up producing code that looks like:
7283
7284 #APP
7285 movw $235,(%eax)
7286 movw %dx,2+(%eax)
7287 rorl $16,%edx
7288 movb %dl,4+(%eax)
7289 movb $137,5+(%eax)
7290 movb $0,6+(%eax)
7291 movb %dh,7+(%eax)
7292 rorl $16,%edx
7293 #NO_APP
7294
47926f60 7295 So here we provide the missing zero. */
24eab124
AM		 7296
7297 *displacement_string_end = '0';
252b5132
RH		 7298 }
7299#endif
3956db08 7300 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7301 if (gotfree_input_line)
7302 input_line_pointer = gotfree_input_line;
252b5132 7303
24eab124 7304 exp_seg = expression (exp);
252b5132 7305
636c26b0
AM		 7306 SKIP_WHITESPACE ();
7307 if (*input_line_pointer)
7308 as_bad (_("junk `%s' after expression"), input_line_pointer);
7309#if GCC_ASM_O_HACK
7310 RESTORE_END_STRING (disp_end + 1);
7311#endif
636c26b0 7312 input_line_pointer = save_input_line_pointer;
636c26b0 7313 if (gotfree_input_line)
ee86248c
JB		 7314 {
7315 free (gotfree_input_line);
7316
7317 if (exp->X_op == O_constant || exp->X_op == O_register)
7318 exp->X_op = O_illegal;
7319 }
7320
7321 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
7322
7323 RESTORE_END_STRING (disp_end);
7324
7325 return ret;
7326}
7327
7328static int
7329i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7330 i386_operand_type types, const char *disp_start)
7331{
7332 i386_operand_type bigdisp;
7333 int ret = 1;
636c26b0 7334
24eab124
AM		 7335 /* We do this to make sure that the section symbol is in
7336 the symbol table. We will ultimately change the relocation
47926f60 7337 to be relative to the beginning of the section. */
1ae12ab7 7338 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 7339 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
7340 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 7341 {
636c26b0 7342 if (exp->X_op != O_symbol)
3992d3b7 7343 goto inv_disp;
636c26b0 7344
e5cb08ac 7345 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 7346 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
7347 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 7348 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 7349 exp->X_op = O_subtract;
7350 exp->X_op_symbol = GOT_symbol;
1ae12ab7 7351 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 7352 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 7353 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
7354 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 7355 else
29b0f896 7356 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 7357 }
252b5132 7358
3992d3b7
AM		 7359 else if (exp->X_op == O_absent
7360 || exp->X_op == O_illegal
ee86248c 7361 || exp->X_op == O_big)
2daf4fd8 7362 {
3992d3b7
AM		 7363 inv_disp:
7364 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 7365 disp_start);
3992d3b7 7366 ret = 0;
2daf4fd8
AM		 7367 }
7368
0e1147d9
L		 7369 else if (flag_code == CODE_64BIT
7370 && !i.prefix[ADDR_PREFIX]
7371 && exp->X_op == O_constant)
7372 {
7373 /* Since displacement is signed extended to 64bit, don't allow
7374 disp32 and turn off disp32s if they are out of range. */
7375 i.types[this_operand].bitfield.disp32 = 0;
7376 if (!fits_in_signed_long (exp->X_add_number))
7377 {
7378 i.types[this_operand].bitfield.disp32s = 0;
7379 if (i.types[this_operand].bitfield.baseindex)
7380 {
7381 as_bad (_("0x%lx out range of signed 32bit displacement"),
7382 (long) exp->X_add_number);
7383 ret = 0;
7384 }
7385 }
7386 }
7387
4c63da97 7388#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7389 else if (exp->X_op != O_constant
7390 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7391 && exp_seg != absolute_section
7392 && exp_seg != text_section
7393 && exp_seg != data_section
7394 && exp_seg != bss_section
7395 && exp_seg != undefined_section
7396 && !bfd_is_com_section (exp_seg))
24eab124 7397 {
d0b47220 7398 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7399 ret = 0;
24eab124 7400 }
252b5132 7401#endif
3956db08 7402
40fb9820
L		 7403 /* Check if this is a displacement only operand. */
7404 bigdisp = i.types[this_operand];
7405 bigdisp.bitfield.disp8 = 0;
7406 bigdisp.bitfield.disp16 = 0;
7407 bigdisp.bitfield.disp32 = 0;
7408 bigdisp.bitfield.disp32s = 0;
7409 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7410 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7411 i.types[this_operand] = operand_type_and (i.types[this_operand],
7412 types);
3956db08 7413
3992d3b7 7414 return ret;
252b5132
RH		 7415}
7416
eecb386c 7417/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7418 Return 1 on success, 0 on a failure. */
7419
252b5132 7420static int
e3bb37b5 7421i386_index_check (const char *operand_string)
252b5132 7422{
3e73aa7c 7423 int ok;
fc0763e6 7424 const char *kind = "base/index";
24eab124 7425#if INFER_ADDR_PREFIX
eecb386c
AM		 7426 int fudged = 0;
7427
24eab124
AM		 7428 tryprefix:
7429#endif
3e73aa7c 7430 ok = 1;
fc0763e6
JB		 7431 if (current_templates->start->opcode_modifier.isstring
7432 && !current_templates->start->opcode_modifier.immext
7433 && (current_templates->end[-1].opcode_modifier.isstring
7434 || i.mem_operands))
7435 {
7436 /* Memory operands of string insns are special in that they only allow
7437 a single register (rDI, rSI, or rBX) as their memory address. */
7438 unsigned int expected;
7439
7440 kind = "string address";
7441
7442 if (current_templates->start->opcode_modifier.w)
7443 {
7444 i386_operand_type type = current_templates->end[-1].operand_types[0];
7445
7446 if (!type.bitfield.baseindex
7447 || ((!i.mem_operands != !intel_syntax)
7448 && current_templates->end[-1].operand_types[1]
7449 .bitfield.baseindex))
7450 type = current_templates->end[-1].operand_types[1];
7451 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7452 }
7453 else
7454 expected = 3 /* rBX */;
7455
7456 if (!i.base_reg || i.index_reg
7457 || operand_type_check (i.types[this_operand], disp))
7458 ok = -1;
7459 else if (!(flag_code == CODE_64BIT
7460 ? i.prefix[ADDR_PREFIX]
7461 ? i.base_reg->reg_type.bitfield.reg32
7462 : i.base_reg->reg_type.bitfield.reg64
7463 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7464 ? i.base_reg->reg_type.bitfield.reg32
7465 : i.base_reg->reg_type.bitfield.reg16))
7466 ok = 0;
4c692bc7 7467 else if (register_number (i.base_reg) != expected)
fc0763e6
JB		 7468 ok = -1;
7469
7470 if (ok < 0)
7471 {
7472 unsigned int j;
7473
7474 for (j = 0; j < i386_regtab_size; ++j)
7475 if ((flag_code == CODE_64BIT
7476 ? i.prefix[ADDR_PREFIX]
7477 ? i386_regtab[j].reg_type.bitfield.reg32
7478 : i386_regtab[j].reg_type.bitfield.reg64
7479 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7480 ? i386_regtab[j].reg_type.bitfield.reg32
7481 : i386_regtab[j].reg_type.bitfield.reg16)
4c692bc7 7482 && register_number(i386_regtab + j) == expected)
fc0763e6 7483 break;
9c2799c2 7484 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7485 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7486 operand_string,
7487 intel_syntax ? '[' : '(',
7488 register_prefix,
7489 i386_regtab[j].reg_name,
7490 intel_syntax ? ']' : ')');
7491 ok = 1;
7492 }
7493 }
7494 else if (flag_code == CODE_64BIT)
64e74474 7495 {
64e74474 7496 if ((i.base_reg
40fb9820
L		 7497 && ((i.prefix[ADDR_PREFIX] == 0
7498 && !i.base_reg->reg_type.bitfield.reg64)
7499 || (i.prefix[ADDR_PREFIX]
7500 && !i.base_reg->reg_type.bitfield.reg32))
7501 && (i.index_reg
9a04903e
JB		 7502 || i.base_reg->reg_num !=
7503 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7504 || (i.index_reg
6c30d220
L		 7505 && !(i.index_reg->reg_type.bitfield.regxmm
7506 || i.index_reg->reg_type.bitfield.regymm)
40fb9820
L		 7507 && (!i.index_reg->reg_type.bitfield.baseindex
7508 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7509 && i.index_reg->reg_num != RegRiz
7510 && !i.index_reg->reg_type.bitfield.reg64
7511 )
40fb9820 7512 || (i.prefix[ADDR_PREFIX]
db51cc60 7513 && i.index_reg->reg_num != RegEiz
40fb9820 7514 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7515 ok = 0;
3e73aa7c
JH		 7516 }
7517 else
7518 {
7519 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7520 {
7521 /* 16bit checks. */
7522 if ((i.base_reg
40fb9820
L		 7523 && (!i.base_reg->reg_type.bitfield.reg16
7524 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7525 || (i.index_reg
40fb9820
L		 7526 && (!i.index_reg->reg_type.bitfield.reg16
7527 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7528 || !(i.base_reg
7529 && i.base_reg->reg_num < 6
7530 && i.index_reg->reg_num >= 6
7531 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7532 ok = 0;
7533 }
7534 else
e5cb08ac 7535 {
3e73aa7c
JH		 7536 /* 32bit checks. */
7537 if ((i.base_reg
40fb9820 7538 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7539 || (i.index_reg
6c30d220
L		 7540 && !i.index_reg->reg_type.bitfield.regxmm
7541 && !i.index_reg->reg_type.bitfield.regymm
db51cc60
L		 7542 && ((!i.index_reg->reg_type.bitfield.reg32
7543 && i.index_reg->reg_num != RegEiz)
40fb9820 7544 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7545 ok = 0;
3e73aa7c
JH		 7546 }
7547 }
7548 if (!ok)
24eab124
AM		 7549 {
7550#if INFER_ADDR_PREFIX
fc0763e6 7551 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7552 {
7553 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7554 i.prefixes += 1;
b23bac36
AM		 7555 /* Change the size of any displacement too. At most one of
7556 Disp16 or Disp32 is set.
7557 FIXME. There doesn't seem to be any real need for separate
7558 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7559 Removing them would probably clean up the code quite a lot. */
4eed87de 7560 if (flag_code != CODE_64BIT
40fb9820
L		 7561 && (i.types[this_operand].bitfield.disp16
7562 || i.types[this_operand].bitfield.disp32))
7563 i.types[this_operand]
c6fb90c8 7564 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7565 fudged = 1;
24eab124
AM		 7566 goto tryprefix;
7567 }
eecb386c 7568 if (fudged)
fc0763e6
JB		 7569 as_bad (_("`%s' is not a valid %s expression"),
7570 operand_string,
7571 kind);
eecb386c 7572 else
c388dee8 7573#endif
fc0763e6 7574 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7575 operand_string,
fc0763e6
JB		 7576 flag_code_names[i.prefix[ADDR_PREFIX]
7577 ? flag_code == CODE_32BIT
7578 ? CODE_16BIT
7579 : CODE_32BIT
7580 : flag_code],
7581 kind);
24eab124 7582 }
20f0a1fc 7583 return ok;
24eab124 7584}
252b5132 7585
fc0763e6 7586/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7587 on error. */
252b5132 7588
252b5132 7589static int
a7619375 7590i386_att_operand (char *operand_string)
252b5132 7591{
af6bdddf
AM		 7592 const reg_entry *r;
7593 char *end_op;
24eab124 7594 char *op_string = operand_string;
252b5132 7595
24eab124 7596 if (is_space_char (*op_string))
252b5132
RH		 7597 ++op_string;
7598
24eab124 7599 /* We check for an absolute prefix (differentiating,
47926f60 7600 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7601 if (*op_string == ABSOLUTE_PREFIX)
7602 {
7603 ++op_string;
7604 if (is_space_char (*op_string))
7605 ++op_string;
40fb9820 7606 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7607 }
252b5132 7608
47926f60 7609 /* Check if operand is a register. */
4d1bb795 7610 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7611 {
40fb9820
L		 7612 i386_operand_type temp;
7613
24eab124
AM		 7614 /* Check for a segment override by searching for ':' after a
7615 segment register. */
7616 op_string = end_op;
7617 if (is_space_char (*op_string))
7618 ++op_string;
40fb9820
L		 7619 if (*op_string == ':'
7620 && (r->reg_type.bitfield.sreg2
7621 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7622 {
7623 switch (r->reg_num)
7624 {
7625 case 0:
7626 i.seg[i.mem_operands] = &es;
7627 break;
7628 case 1:
7629 i.seg[i.mem_operands] = &cs;
7630 break;
7631 case 2:
7632 i.seg[i.mem_operands] = &ss;
7633 break;
7634 case 3:
7635 i.seg[i.mem_operands] = &ds;
7636 break;
7637 case 4:
7638 i.seg[i.mem_operands] = &fs;
7639 break;
7640 case 5:
7641 i.seg[i.mem_operands] = &gs;
7642 break;
7643 }
252b5132 7644
24eab124 7645 /* Skip the ':' and whitespace. */
252b5132
RH		 7646 ++op_string;
7647 if (is_space_char (*op_string))
24eab124 7648 ++op_string;
252b5132 7649
24eab124
AM		 7650 if (!is_digit_char (*op_string)
7651 && !is_identifier_char (*op_string)
7652 && *op_string != '('
7653 && *op_string != ABSOLUTE_PREFIX)
7654 {
7655 as_bad (_("bad memory operand `%s'"), op_string);
7656 return 0;
7657 }
47926f60 7658 /* Handle case of %es:*foo. */
24eab124
AM		 7659 if (*op_string == ABSOLUTE_PREFIX)
7660 {
7661 ++op_string;
7662 if (is_space_char (*op_string))
7663 ++op_string;
40fb9820 7664 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7665 }
7666 goto do_memory_reference;
7667 }
7668 if (*op_string)
7669 {
d0b47220 7670 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7671 return 0;
7672 }
40fb9820
L		 7673 temp = r->reg_type;
7674 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7675 i.types[this_operand] = operand_type_or (i.types[this_operand],
7676 temp);
7d5e4556 7677 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7678 i.op[this_operand].regs = r;
24eab124
AM		 7679 i.reg_operands++;
7680 }
af6bdddf
AM		 7681 else if (*op_string == REGISTER_PREFIX)
7682 {
7683 as_bad (_("bad register name `%s'"), op_string);
7684 return 0;
7685 }
24eab124 7686 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7687 {
24eab124 7688 ++op_string;
40fb9820 7689 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7690 {
d0b47220 7691 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7692 return 0;
7693 }
7694 if (!i386_immediate (op_string))
7695 return 0;
7696 }
7697 else if (is_digit_char (*op_string)
7698 || is_identifier_char (*op_string)
e5cb08ac 7699 || *op_string == '(')
24eab124 7700 {
47926f60 7701 /* This is a memory reference of some sort. */
af6bdddf 7702 char *base_string;
252b5132 7703
47926f60 7704 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7705 char *displacement_string_start;
7706 char *displacement_string_end;
252b5132 7707
24eab124 7708 do_memory_reference:
24eab124 7709 if ((i.mem_operands == 1
40fb9820 7710 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7711 || i.mem_operands == 2)
7712 {
7713 as_bad (_("too many memory references for `%s'"),
7714 current_templates->start->name);
7715 return 0;
7716 }
252b5132 7717
24eab124
AM		 7718 /* Check for base index form. We detect the base index form by
7719 looking for an ')' at the end of the operand, searching
7720 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7721 after the '('. */
af6bdddf 7722 base_string = op_string + strlen (op_string);
c3332e24 7723
af6bdddf
AM		 7724 --base_string;
7725 if (is_space_char (*base_string))
7726 --base_string;
252b5132 7727
47926f60 7728 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7729 displacement_string_start = op_string;
7730 displacement_string_end = base_string + 1;
252b5132 7731
24eab124
AM		 7732 if (*base_string == ')')
7733 {
af6bdddf 7734 char *temp_string;
24eab124
AM		 7735 unsigned int parens_balanced = 1;
7736 /* We've already checked that the number of left & right ()'s are
47926f60 7737 equal, so this loop will not be infinite. */
24eab124
AM		 7738 do
7739 {
7740 base_string--;
7741 if (*base_string == ')')
7742 parens_balanced++;
7743 if (*base_string == '(')
7744 parens_balanced--;
7745 }
7746 while (parens_balanced);
c3332e24 7747
af6bdddf 7748 temp_string = base_string;
c3332e24 7749
24eab124 7750 /* Skip past '(' and whitespace. */
252b5132
RH		 7751 ++base_string;
7752 if (is_space_char (*base_string))
24eab124 7753 ++base_string;
252b5132 7754
af6bdddf 7755 if (*base_string == ','
4eed87de
AM		 7756 || ((i.base_reg = parse_register (base_string, &end_op))
7757 != NULL))
252b5132 7758 {
af6bdddf 7759 displacement_string_end = temp_string;
252b5132 7760
40fb9820 7761 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7762
af6bdddf 7763 if (i.base_reg)
24eab124 7764 {
24eab124
AM		 7765 base_string = end_op;
7766 if (is_space_char (*base_string))
7767 ++base_string;
af6bdddf
AM		 7768 }
7769
7770 /* There may be an index reg or scale factor here. */
7771 if (*base_string == ',')
7772 {
7773 ++base_string;
7774 if (is_space_char (*base_string))
7775 ++base_string;
7776
4eed87de
AM		 7777 if ((i.index_reg = parse_register (base_string, &end_op))
7778 != NULL)
24eab124 7779 {
af6bdddf 7780 base_string = end_op;
24eab124
AM		 7781 if (is_space_char (*base_string))
7782 ++base_string;
af6bdddf
AM		 7783 if (*base_string == ',')
7784 {
7785 ++base_string;
7786 if (is_space_char (*base_string))
7787 ++base_string;
7788 }
e5cb08ac 7789 else if (*base_string != ')')
af6bdddf 7790 {
4eed87de
AM		 7791 as_bad (_("expecting `,' or `)' "
7792 "after index register in `%s'"),
af6bdddf
AM		 7793 operand_string);
7794 return 0;
7795 }
24eab124 7796 }
af6bdddf 7797 else if (*base_string == REGISTER_PREFIX)
24eab124 7798 {
f76bf5e0
L		 7799 end_op = strchr (base_string, ',');
7800 if (end_op)
7801 *end_op = '\0';
af6bdddf 7802 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7803 return 0;
7804 }
252b5132 7805
47926f60 7806 /* Check for scale factor. */
551c1ca1 7807 if (*base_string != ')')
af6bdddf 7808 {
551c1ca1
AM		 7809 char *end_scale = i386_scale (base_string);
7810
7811 if (!end_scale)
af6bdddf 7812 return 0;
24eab124 7813
551c1ca1 7814 base_string = end_scale;
af6bdddf
AM		 7815 if (is_space_char (*base_string))
7816 ++base_string;
7817 if (*base_string != ')')
7818 {
4eed87de
AM		 7819 as_bad (_("expecting `)' "
7820 "after scale factor in `%s'"),
af6bdddf
AM		 7821 operand_string);
7822 return 0;
7823 }
7824 }
7825 else if (!i.index_reg)
24eab124 7826 {
4eed87de
AM		 7827 as_bad (_("expecting index register or scale factor "
7828 "after `,'; got '%c'"),
af6bdddf 7829 *base_string);
24eab124
AM		 7830 return 0;
7831 }
7832 }
af6bdddf 7833 else if (*base_string != ')')
24eab124 7834 {
4eed87de
AM		 7835 as_bad (_("expecting `,' or `)' "
7836 "after base register in `%s'"),
af6bdddf 7837 operand_string);
24eab124
AM		 7838 return 0;
7839 }
c3332e24 7840 }
af6bdddf 7841 else if (*base_string == REGISTER_PREFIX)
c3332e24 7842 {
f76bf5e0
L		 7843 end_op = strchr (base_string, ',');
7844 if (end_op)
7845 *end_op = '\0';
af6bdddf 7846 as_bad (_("bad register name `%s'"), base_string);
24eab124 7847 return 0;
c3332e24 7848 }
24eab124
AM		 7849 }
7850
7851 /* If there's an expression beginning the operand, parse it,
7852 assuming displacement_string_start and
7853 displacement_string_end are meaningful. */
7854 if (displacement_string_start != displacement_string_end)
7855 {
7856 if (!i386_displacement (displacement_string_start,
7857 displacement_string_end))
7858 return 0;
7859 }
7860
7861 /* Special case for (%dx) while doing input/output op. */
7862 if (i.base_reg
0dfbf9d7
L		 7863 && operand_type_equal (&i.base_reg->reg_type,
7864 &reg16_inoutportreg)
24eab124
AM		 7865 && i.index_reg == 0
7866 && i.log2_scale_factor == 0
7867 && i.seg[i.mem_operands] == 0
40fb9820 7868 && !operand_type_check (i.types[this_operand], disp))
24eab124 7869 {
65da13b5 7870 i.types[this_operand] = inoutportreg;
24eab124
AM		 7871 return 1;
7872 }
7873
eecb386c
AM		 7874 if (i386_index_check (operand_string) == 0)
7875 return 0;
5c07affc 7876 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7877 i.mem_operands++;
7878 }
7879 else
ce8a8b2f
AM		 7880 {
7881 /* It's not a memory operand; argh! */
24eab124
AM		 7882 as_bad (_("invalid char %s beginning operand %d `%s'"),
7883 output_invalid (*op_string),
7884 this_operand + 1,
7885 op_string);
7886 return 0;
7887 }
47926f60 7888 return 1; /* Normal return. */
252b5132
RH		 7889}
7890\f
fa94de6b
RM		 7891/* Calculate the maximum variable size (i.e., excluding fr_fix)
7892 that an rs_machine_dependent frag may reach. */
7893
7894unsigned int
7895i386_frag_max_var (fragS *frag)
7896{
7897 /* The only relaxable frags are for jumps.
7898 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7899 gas_assert (frag->fr_type == rs_machine_dependent);
7900 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
7901}
7902
ee7fcc42
AM		 7903/* md_estimate_size_before_relax()
7904
7905 Called just before relax() for rs_machine_dependent frags. The x86
7906 assembler uses these frags to handle variable size jump
7907 instructions.
7908
7909 Any symbol that is now undefined will not become defined.
7910 Return the correct fr_subtype in the frag.
7911 Return the initial "guess for variable size of frag" to caller.
7912 The guess is actually the growth beyond the fixed part. Whatever
7913 we do to grow the fixed or variable part contributes to our
7914 returned value. */
7915
252b5132 7916int
7016a5d5 7917md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 7918{
252b5132 7919 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7920 check for un-relaxable symbols. On an ELF system, we can't relax
7921 an externally visible symbol, because it may be overridden by a
7922 shared library. */
7923 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7924#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7925 || (IS_ELF
31312f95 7926 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7927 || S_IS_WEAK (fragP->fr_symbol)
7928 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7929 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7930#endif
7931#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7932 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7933 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7934#endif
7935 )
252b5132 7936 {
b98ef147
AM		 7937 /* Symbol is undefined in this segment, or we need to keep a
7938 reloc so that weak symbols can be overridden. */
7939 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7940 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7941 unsigned char *opcode;
7942 int old_fr_fix;
f6af82bd 7943
ee7fcc42 7944 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7945 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7946 else if (size == 2)
f6af82bd
AM		 7947 reloc_type = BFD_RELOC_16_PCREL;
7948 else
7949 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7950
ee7fcc42
AM		 7951 old_fr_fix = fragP->fr_fix;
7952 opcode = (unsigned char *) fragP->fr_opcode;
7953
fddf5b5b 7954 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7955 {
fddf5b5b
AM		 7956 case UNCOND_JUMP:
7957 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7958 opcode[0] = 0xe9;
252b5132 7959 fragP->fr_fix += size;
062cd5e7
AS		 7960 fix_new (fragP, old_fr_fix, size,
7961 fragP->fr_symbol,
7962 fragP->fr_offset, 1,
7963 reloc_type);
252b5132
RH		 7964 break;
7965
fddf5b5b 7966 case COND_JUMP86:
412167cb
AM		 7967 if (size == 2
7968 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7969 {
7970 /* Negate the condition, and branch past an
7971 unconditional jump. */
7972 opcode[0] ^= 1;
7973 opcode[1] = 3;
7974 /* Insert an unconditional jump. */
7975 opcode[2] = 0xe9;
7976 /* We added two extra opcode bytes, and have a two byte
7977 offset. */
7978 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7979 fix_new (fragP, old_fr_fix + 2, 2,
7980 fragP->fr_symbol,
7981 fragP->fr_offset, 1,
7982 reloc_type);
fddf5b5b
AM		 7983 break;
7984 }
7985 /* Fall through. */
7986
7987 case COND_JUMP:
412167cb
AM		 7988 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7989 {
3e02c1cc
AM		 7990 fixS *fixP;
7991
412167cb 7992 fragP->fr_fix += 1;
3e02c1cc
AM		 7993 fixP = fix_new (fragP, old_fr_fix, 1,
7994 fragP->fr_symbol,
7995 fragP->fr_offset, 1,
7996 BFD_RELOC_8_PCREL);
7997 fixP->fx_signed = 1;
412167cb
AM		 7998 break;
7999 }
93c2a809 8000
24eab124 8001 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8002 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8003 opcode[1] = opcode[0] + 0x10;
f6af82bd 8004 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8005 /* We've added an opcode byte. */
8006 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8007 fix_new (fragP, old_fr_fix + 1, size,
8008 fragP->fr_symbol,
8009 fragP->fr_offset, 1,
8010 reloc_type);
252b5132 8011 break;
fddf5b5b
AM		 8012
8013 default:
8014 BAD_CASE (fragP->fr_subtype);
8015 break;
252b5132
RH		 8016 }
8017 frag_wane (fragP);
ee7fcc42 8018 return fragP->fr_fix - old_fr_fix;
252b5132 8019 }
93c2a809 8020
93c2a809
AM		 8021 /* Guess size depending on current relax state. Initially the relax
8022 state will correspond to a short jump and we return 1, because
8023 the variable part of the frag (the branch offset) is one byte
8024 long. However, we can relax a section more than once and in that
8025 case we must either set fr_subtype back to the unrelaxed state,
8026 or return the value for the appropriate branch. */
8027 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8028}
8029
47926f60
KH		 8030/* Called after relax() is finished.
8031
8032 In: Address of frag.
8033 fr_type == rs_machine_dependent.
8034 fr_subtype is what the address relaxed to.
8035
8036 Out: Any fixSs and constants are set up.
8037 Caller will turn frag into a ".space 0". */
8038
252b5132 8039void
7016a5d5
TG		 8040md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8041 fragS *fragP)
252b5132 8042{
29b0f896 8043 unsigned char *opcode;
252b5132 8044 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8045 offsetT target_address;
8046 offsetT opcode_address;
252b5132 8047 unsigned int extension = 0;
847f7ad4 8048 offsetT displacement_from_opcode_start;
252b5132
RH		 8049
8050 opcode = (unsigned char *) fragP->fr_opcode;
8051
47926f60 8052 /* Address we want to reach in file space. */
252b5132 8053 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8054
47926f60 8055 /* Address opcode resides at in file space. */
252b5132
RH		 8056 opcode_address = fragP->fr_address + fragP->fr_fix;
8057
47926f60 8058 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8059 displacement_from_opcode_start = target_address - opcode_address;
8060
fddf5b5b 8061 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8062 {
47926f60
KH		 8063 /* Don't have to change opcode. */
8064 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8065 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8066 }
8067 else
8068 {
8069 if (no_cond_jump_promotion
8070 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8071 as_warn_where (fragP->fr_file, fragP->fr_line,
8072 _("long jump required"));
252b5132 8073
fddf5b5b
AM		 8074 switch (fragP->fr_subtype)
8075 {
8076 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8077 extension = 4; /* 1 opcode + 4 displacement */
8078 opcode[0] = 0xe9;
8079 where_to_put_displacement = &opcode[1];
8080 break;
252b5132 8081
fddf5b5b
AM		 8082 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8083 extension = 2; /* 1 opcode + 2 displacement */
8084 opcode[0] = 0xe9;
8085 where_to_put_displacement = &opcode[1];
8086 break;
252b5132 8087
fddf5b5b
AM		 8088 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8089 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8090 extension = 5; /* 2 opcode + 4 displacement */
8091 opcode[1] = opcode[0] + 0x10;
8092 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8093 where_to_put_displacement = &opcode[2];
8094 break;
252b5132 8095
fddf5b5b
AM		 8096 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8097 extension = 3; /* 2 opcode + 2 displacement */
8098 opcode[1] = opcode[0] + 0x10;
8099 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8100 where_to_put_displacement = &opcode[2];
8101 break;
252b5132 8102
fddf5b5b
AM		 8103 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
8104 extension = 4;
8105 opcode[0] ^= 1;
8106 opcode[1] = 3;
8107 opcode[2] = 0xe9;
8108 where_to_put_displacement = &opcode[3];
8109 break;
8110
8111 default:
8112 BAD_CASE (fragP->fr_subtype);
8113 break;
8114 }
252b5132 8115 }
fddf5b5b 8116
7b81dfbb
AJ		 8117 /* If size if less then four we are sure that the operand fits,
8118 but if it's 4, then it could be that the displacement is larger
8119 then -/+ 2GB. */
8120 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
8121 && object_64bit
8122 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 8123 + ((addressT) 1 << 31))
8124 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 8125 {
8126 as_bad_where (fragP->fr_file, fragP->fr_line,
8127 _("jump target out of range"));
8128 /* Make us emit 0. */
8129 displacement_from_opcode_start = extension;
8130 }
47926f60 8131 /* Now put displacement after opcode. */
252b5132
RH		 8132 md_number_to_chars ((char *) where_to_put_displacement,
8133 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 8134 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 8135 fragP->fr_fix += extension;
8136}
8137\f
7016a5d5 8138/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 8139 by our caller that we have all the info we need to fix it up.
8140
7016a5d5
TG		 8141 Parameter valP is the pointer to the value of the bits.
8142
252b5132
RH		 8143 On the 386, immediates, displacements, and data pointers are all in
8144 the same (little-endian) format, so we don't need to care about which
8145 we are handling. */
8146
94f592af 8147void
7016a5d5 8148md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 8149{
94f592af 8150 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 8151 valueT value = *valP;
252b5132 8152
f86103b7 8153#if !defined (TE_Mach)
93382f6d
AM		 8154 if (fixP->fx_pcrel)
8155 {
8156 switch (fixP->fx_r_type)
8157 {
5865bb77
ILT		 8158 default:
8159 break;
8160
d6ab8113
JB		 8161 case BFD_RELOC_64:
8162 fixP->fx_r_type = BFD_RELOC_64_PCREL;
8163 break;
93382f6d 8164 case BFD_RELOC_32:
ae8887b5 8165 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 8166 fixP->fx_r_type = BFD_RELOC_32_PCREL;
8167 break;
8168 case BFD_RELOC_16:
8169 fixP->fx_r_type = BFD_RELOC_16_PCREL;
8170 break;
8171 case BFD_RELOC_8:
8172 fixP->fx_r_type = BFD_RELOC_8_PCREL;
8173 break;
8174 }
8175 }
252b5132 8176
a161fe53 8177 if (fixP->fx_addsy != NULL
31312f95 8178 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 8179 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 8180 || fixP->fx_r_type == BFD_RELOC_16_PCREL
8181 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
8182 && !use_rela_relocations)
252b5132 8183 {
31312f95
AM		 8184 /* This is a hack. There should be a better way to handle this.
8185 This covers for the fact that bfd_install_relocation will
8186 subtract the current location (for partial_inplace, PC relative
8187 relocations); see more below. */
252b5132 8188#ifndef OBJ_AOUT
718ddfc0 8189 if (IS_ELF
252b5132
RH		 8190#ifdef TE_PE
8191 || OUTPUT_FLAVOR == bfd_target_coff_flavour
8192#endif
8193 )
8194 value += fixP->fx_where + fixP->fx_frag->fr_address;
8195#endif
8196#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8197 if (IS_ELF)
252b5132 8198 {
6539b54b 8199 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 8200
6539b54b 8201 if ((sym_seg == seg
2f66722d 8202 || (symbol_section_p (fixP->fx_addsy)
6539b54b 8203 && sym_seg != absolute_section))
af65af87 8204 && !generic_force_reloc (fixP))
2f66722d
AM		 8205 {
8206 /* Yes, we add the values in twice. This is because
6539b54b
AM		 8207 bfd_install_relocation subtracts them out again. I think
8208 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 8209 it. FIXME. */
8210 value += fixP->fx_where + fixP->fx_frag->fr_address;
8211 }
252b5132
RH		 8212 }
8213#endif
8214#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 8215 /* For some reason, the PE format does not store a
8216 section address offset for a PC relative symbol. */
8217 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 8218 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 8219 value += md_pcrel_from (fixP);
8220#endif
8221 }
fbeb56a4
DK		 8222#if defined (OBJ_COFF) && defined (TE_PE)
8223 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8224 {
8225 value -= S_GET_VALUE (fixP->fx_addsy);
8226 }
8227#endif
252b5132
RH		 8228
8229 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 8230 and we must not disappoint it. */
252b5132 8231#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8232 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 8233 switch (fixP->fx_r_type)
8234 {
8235 case BFD_RELOC_386_PLT32:
3e73aa7c 8236 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 8237 /* Make the jump instruction point to the address of the operand. At
8238 runtime we merely add the offset to the actual PLT entry. */
8239 value = -4;
8240 break;
31312f95 8241
13ae64f3
JJ		 8242 case BFD_RELOC_386_TLS_GD:
8243 case BFD_RELOC_386_TLS_LDM:
13ae64f3 8244 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8245 case BFD_RELOC_386_TLS_IE:
8246 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 8247 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 8248 case BFD_RELOC_X86_64_TLSGD:
8249 case BFD_RELOC_X86_64_TLSLD:
8250 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 8251 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 8252 value = 0; /* Fully resolved at runtime. No addend. */
8253 /* Fallthrough */
8254 case BFD_RELOC_386_TLS_LE:
8255 case BFD_RELOC_386_TLS_LDO_32:
8256 case BFD_RELOC_386_TLS_LE_32:
8257 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8258 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 8259 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 8260 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 8261 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8262 break;
8263
67a4f2b7
AO		 8264 case BFD_RELOC_386_TLS_DESC_CALL:
8265 case BFD_RELOC_X86_64_TLSDESC_CALL:
8266 value = 0; /* Fully resolved at runtime. No addend. */
8267 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8268 fixP->fx_done = 0;
8269 return;
8270
00f7efb6
JJ		 8271 case BFD_RELOC_386_GOT32:
8272 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 8273 value = 0; /* Fully resolved at runtime. No addend. */
8274 break;
47926f60
KH		 8275
8276 case BFD_RELOC_VTABLE_INHERIT:
8277 case BFD_RELOC_VTABLE_ENTRY:
8278 fixP->fx_done = 0;
94f592af 8279 return;
47926f60
KH		 8280
8281 default:
8282 break;
8283 }
8284#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 8285 *valP = value;
f86103b7 8286#endif /* !defined (TE_Mach) */
3e73aa7c 8287
3e73aa7c 8288 /* Are we finished with this relocation now? */
c6682705 8289 if (fixP->fx_addsy == NULL)
3e73aa7c 8290 fixP->fx_done = 1;
fbeb56a4
DK		 8291#if defined (OBJ_COFF) && defined (TE_PE)
8292 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8293 {
8294 fixP->fx_done = 0;
8295 /* Remember value for tc_gen_reloc. */
8296 fixP->fx_addnumber = value;
8297 /* Clear out the frag for now. */
8298 value = 0;
8299 }
8300#endif
3e73aa7c
JH		 8301 else if (use_rela_relocations)
8302 {
8303 fixP->fx_no_overflow = 1;
062cd5e7
AS		 8304 /* Remember value for tc_gen_reloc. */
8305 fixP->fx_addnumber = value;
3e73aa7c
JH		 8306 value = 0;
8307 }
f86103b7 8308
94f592af 8309 md_number_to_chars (p, value, fixP->fx_size);
252b5132 8310}
252b5132 8311\f
252b5132 8312char *
499ac353 8313md_atof (int type, char *litP, int *sizeP)
252b5132 8314{
499ac353
NC		 8315 /* This outputs the LITTLENUMs in REVERSE order;
8316 in accord with the bigendian 386. */
8317 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 8318}
8319\f
2d545b82 8320static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 8321
252b5132 8322static char *
e3bb37b5 8323output_invalid (int c)
252b5132 8324{
3882b010 8325 if (ISPRINT (c))
f9f21a03
L		 8326 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
8327 "'%c'", c);
252b5132 8328 else
f9f21a03 8329 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 8330 "(0x%x)", (unsigned char) c);
252b5132
RH		 8331 return output_invalid_buf;
8332}
8333
af6bdddf 8334/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 8335
8336static const reg_entry *
4d1bb795 8337parse_real_register (char *reg_string, char **end_op)
252b5132 8338{
af6bdddf
AM		 8339 char *s = reg_string;
8340 char *p;
252b5132
RH		 8341 char reg_name_given[MAX_REG_NAME_SIZE + 1];
8342 const reg_entry *r;
8343
8344 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8345 if (*s == REGISTER_PREFIX)
8346 ++s;
8347
8348 if (is_space_char (*s))
8349 ++s;
8350
8351 p = reg_name_given;
af6bdddf 8352 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 8353 {
8354 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 8355 return (const reg_entry *) NULL;
8356 s++;
252b5132
RH		 8357 }
8358
6588847e
DN		 8359 /* For naked regs, make sure that we are not dealing with an identifier.
8360 This prevents confusing an identifier like `eax_var' with register
8361 `eax'. */
8362 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
8363 return (const reg_entry *) NULL;
8364
af6bdddf 8365 *end_op = s;
252b5132
RH		 8366
8367 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
8368
5f47d35b 8369 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 8370 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 8371 {
5f47d35b
AM		 8372 if (is_space_char (*s))
8373 ++s;
8374 if (*s == '(')
8375 {
af6bdddf 8376 ++s;
5f47d35b
AM		 8377 if (is_space_char (*s))
8378 ++s;
8379 if (*s >= '0' && *s <= '7')
8380 {
db557034 8381 int fpr = *s - '0';
af6bdddf 8382 ++s;
5f47d35b
AM		 8383 if (is_space_char (*s))
8384 ++s;
8385 if (*s == ')')
8386 {
8387 *end_op = s + 1;
1e9cc1c2 8388 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 8389 know (r);
8390 return r + fpr;
5f47d35b 8391 }
5f47d35b 8392 }
47926f60 8393 /* We have "%st(" then garbage. */
5f47d35b
AM		 8394 return (const reg_entry *) NULL;
8395 }
8396 }
8397
a60de03c
JB		 8398 if (r == NULL || allow_pseudo_reg)
8399 return r;
8400
0dfbf9d7 8401 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8402 return (const reg_entry *) NULL;
8403
192dc9c6
JB		 8404 if ((r->reg_type.bitfield.reg32
8405 || r->reg_type.bitfield.sreg3
8406 || r->reg_type.bitfield.control
8407 || r->reg_type.bitfield.debug
8408 || r->reg_type.bitfield.test)
8409 && !cpu_arch_flags.bitfield.cpui386)
8410 return (const reg_entry *) NULL;
8411
309d3373
JB		 8412 if (r->reg_type.bitfield.floatreg
8413 && !cpu_arch_flags.bitfield.cpu8087
8414 && !cpu_arch_flags.bitfield.cpu287
8415 && !cpu_arch_flags.bitfield.cpu387)
8416 return (const reg_entry *) NULL;
8417
192dc9c6
JB		 8418 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8419 return (const reg_entry *) NULL;
8420
8421 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8422 return (const reg_entry *) NULL;
8423
40f12533
L		 8424 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8425 return (const reg_entry *) NULL;
8426
db51cc60 8427 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8428 if (!allow_index_reg
db51cc60
L		 8429 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8430 return (const reg_entry *) NULL;
8431
a60de03c
JB		 8432 if (((r->reg_flags & (RegRex64 | RegRex))
8433 || r->reg_type.bitfield.reg64)
40fb9820 8434 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8435 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8436 && flag_code != CODE_64BIT)
20f0a1fc 8437 return (const reg_entry *) NULL;
1ae00879 8438
b7240065
JB		 8439 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8440 return (const reg_entry *) NULL;
8441
252b5132
RH		 8442 return r;
8443}
4d1bb795
JB		 8444
8445/* REG_STRING starts *before* REGISTER_PREFIX. */
8446
8447static const reg_entry *
8448parse_register (char *reg_string, char **end_op)
8449{
8450 const reg_entry *r;
8451
8452 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8453 r = parse_real_register (reg_string, end_op);
8454 else
8455 r = NULL;
8456 if (!r)
8457 {
8458 char *save = input_line_pointer;
8459 char c;
8460 symbolS *symbolP;
8461
8462 input_line_pointer = reg_string;
8463 c = get_symbol_end ();
8464 symbolP = symbol_find (reg_string);
8465 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8466 {
8467 const expressionS *e = symbol_get_value_expression (symbolP);
8468
0398aac5 8469 know (e->X_op == O_register);
4eed87de 8470 know (e->X_add_number >= 0
c3fe08fa 8471 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8472 r = i386_regtab + e->X_add_number;
8473 *end_op = input_line_pointer;
8474 }
8475 *input_line_pointer = c;
8476 input_line_pointer = save;
8477 }
8478 return r;
8479}
8480
8481int
8482i386_parse_name (char *name, expressionS *e, char *nextcharP)
8483{
8484 const reg_entry *r;
8485 char *end = input_line_pointer;
8486
8487 *end = *nextcharP;
8488 r = parse_register (name, &input_line_pointer);
8489 if (r && end <= input_line_pointer)
8490 {
8491 *nextcharP = *input_line_pointer;
8492 *input_line_pointer = 0;
8493 e->X_op = O_register;
8494 e->X_add_number = r - i386_regtab;
8495 return 1;
8496 }
8497 input_line_pointer = end;
8498 *end = 0;
ee86248c 8499 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8500}
8501
8502void
8503md_operand (expressionS *e)
8504{
ee86248c
JB		 8505 char *end;
8506 const reg_entry *r;
4d1bb795 8507
ee86248c
JB		 8508 switch (*input_line_pointer)
8509 {
8510 case REGISTER_PREFIX:
8511 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8512 if (r)
8513 {
8514 e->X_op = O_register;
8515 e->X_add_number = r - i386_regtab;
8516 input_line_pointer = end;
8517 }
ee86248c
JB		 8518 break;
8519
8520 case '[':
9c2799c2 8521 gas_assert (intel_syntax);
ee86248c
JB		 8522 end = input_line_pointer++;
8523 expression (e);
8524 if (*input_line_pointer == ']')
8525 {
8526 ++input_line_pointer;
8527 e->X_op_symbol = make_expr_symbol (e);
8528 e->X_add_symbol = NULL;
8529 e->X_add_number = 0;
8530 e->X_op = O_index;
8531 }
8532 else
8533 {
8534 e->X_op = O_absent;
8535 input_line_pointer = end;
8536 }
8537 break;
4d1bb795
JB		 8538 }
8539}
8540
252b5132 8541\f
4cc782b5 8542#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8543const char *md_shortopts = "kVQ:sqn";
252b5132 8544#else
12b55ccc 8545const char *md_shortopts = "qn";
252b5132 8546#endif
6e0b89ee 8547
3e73aa7c 8548#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8549#define OPTION_64 (OPTION_MD_BASE + 1)
8550#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8551#define OPTION_MARCH (OPTION_MD_BASE + 3)
8552#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8553#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8554#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8555#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8556#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8557#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8558#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8559#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 8560#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
8561#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
8562#define OPTION_X32 (OPTION_MD_BASE + 14)
b3b91714 8563
99ad8390
NC		 8564struct option md_longopts[] =
8565{
3e73aa7c 8566 {"32", no_argument, NULL, OPTION_32},
321098a5 8567#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8568 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 8569 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8570#endif
8571#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8572 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8573#endif
b3b91714 8574 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8575 {"march", required_argument, NULL, OPTION_MARCH},
8576 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8577 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8578 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8579 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8580 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8581 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8582 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8583 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 8584 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 8585 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8586 {NULL, no_argument, NULL, 0}
8587};
8588size_t md_longopts_size = sizeof (md_longopts);
8589
8590int
9103f4f4 8591md_parse_option (int c, char *arg)
252b5132 8592{
91d6fa6a 8593 unsigned int j;
6305a203 8594 char *arch, *next;
9103f4f4 8595
252b5132
RH		 8596 switch (c)
8597 {
12b55ccc
L		 8598 case 'n':
8599 optimize_align_code = 0;
8600 break;
8601
a38cf1db
AM		 8602 case 'q':
8603 quiet_warnings = 1;
252b5132
RH		 8604 break;
8605
8606#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8607 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8608 should be emitted or not. FIXME: Not implemented. */
8609 case 'Q':
252b5132
RH		 8610 break;
8611
8612 /* -V: SVR4 argument to print version ID. */
8613 case 'V':
8614 print_version_id ();
8615 break;
8616
a38cf1db
AM		 8617 /* -k: Ignore for FreeBSD compatibility. */
8618 case 'k':
252b5132 8619 break;
4cc782b5
ILT		 8620
8621 case 's':
8622 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8623 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8624 break;
99ad8390 8625#endif
321098a5 8626#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8627 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 8628 case OPTION_64:
8629 {
8630 const char **list, **l;
8631
3e73aa7c
JH		 8632 list = bfd_target_list ();
8633 for (l = list; *l != NULL; l++)
8620418b 8634 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8635 || strcmp (*l, "coff-x86-64") == 0
8636 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 8637 || strcmp (*l, "pei-x86-64") == 0
8638 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 8639 {
8640 default_arch = "x86_64";
8641 break;
8642 }
3e73aa7c 8643 if (*l == NULL)
2b5d6a91 8644 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 8645 free (list);
8646 }
8647 break;
8648#endif
252b5132 8649
351f65ca 8650#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8651 case OPTION_X32:
351f65ca
L		 8652 if (IS_ELF)
8653 {
8654 const char **list, **l;
8655
8656 list = bfd_target_list ();
8657 for (l = list; *l != NULL; l++)
8658 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8659 {
8660 default_arch = "x86_64:32";
8661 break;
8662 }
8663 if (*l == NULL)
2b5d6a91 8664 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 8665 free (list);
8666 }
8667 else
8668 as_fatal (_("32bit x86_64 is only supported for ELF"));
8669 break;
8670#endif
8671
6e0b89ee
AM		 8672 case OPTION_32:
8673 default_arch = "i386";
8674 break;
8675
b3b91714
AM		 8676 case OPTION_DIVIDE:
8677#ifdef SVR4_COMMENT_CHARS
8678 {
8679 char *n, *t;
8680 const char *s;
8681
8682 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8683 t = n;
8684 for (s = i386_comment_chars; *s != '\0'; s++)
8685 if (*s != '/')
8686 *t++ = *s;
8687 *t = '\0';
8688 i386_comment_chars = n;
8689 }
8690#endif
8691 break;
8692
9103f4f4 8693 case OPTION_MARCH:
6305a203
L		 8694 arch = xstrdup (arg);
8695 do
9103f4f4 8696 {
6305a203 8697 if (*arch == '.')
2b5d6a91 8698 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8699 next = strchr (arch, '+');
8700 if (next)
8701 *next++ = '\0';
91d6fa6a 8702 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8703 {
91d6fa6a 8704 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8705 {
6305a203 8706 /* Processor. */
1ded5609
JB		 8707 if (! cpu_arch[j].flags.bitfield.cpui386)
8708 continue;
8709
91d6fa6a 8710 cpu_arch_name = cpu_arch[j].name;
6305a203 8711 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8712 cpu_arch_flags = cpu_arch[j].flags;
8713 cpu_arch_isa = cpu_arch[j].type;
8714 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8715 if (!cpu_arch_tune_set)
8716 {
8717 cpu_arch_tune = cpu_arch_isa;
8718 cpu_arch_tune_flags = cpu_arch_isa_flags;
8719 }
8720 break;
8721 }
91d6fa6a
NC		 8722 else if (*cpu_arch [j].name == '.'
8723 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8724 {
8725 /* ISA entension. */
8726 i386_cpu_flags flags;
309d3373 8727
49021df2 8728 if (!cpu_arch[j].negated)
309d3373 8729 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8730 cpu_arch[j].flags);
309d3373
JB		 8731 else
8732 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8733 cpu_arch[j].flags);
0dfbf9d7 8734 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8735 {
8736 if (cpu_sub_arch_name)
8737 {
8738 char *name = cpu_sub_arch_name;
8739 cpu_sub_arch_name = concat (name,
91d6fa6a 8740 cpu_arch[j].name,
1bf57e9f 8741 (const char *) NULL);
6305a203
L		 8742 free (name);
8743 }
8744 else
91d6fa6a 8745 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8746 cpu_arch_flags = flags;
a586129e 8747 cpu_arch_isa_flags = flags;
6305a203
L		 8748 }
8749 break;
ccc9c027 8750 }
9103f4f4 8751 }
6305a203 8752
91d6fa6a 8753 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8754 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8755
8756 arch = next;
9103f4f4 8757 }
6305a203 8758 while (next != NULL );
9103f4f4
L		 8759 break;
8760
8761 case OPTION_MTUNE:
8762 if (*arg == '.')
2b5d6a91 8763 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 8764 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8765 {
91d6fa6a 8766 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8767 {
ccc9c027 8768 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8769 cpu_arch_tune = cpu_arch [j].type;
8770 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8771 break;
8772 }
8773 }
91d6fa6a 8774 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8775 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 8776 break;
8777
1efbbeb4
L		 8778 case OPTION_MMNEMONIC:
8779 if (strcasecmp (arg, "att") == 0)
8780 intel_mnemonic = 0;
8781 else if (strcasecmp (arg, "intel") == 0)
8782 intel_mnemonic = 1;
8783 else
2b5d6a91 8784 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 8785 break;
8786
8787 case OPTION_MSYNTAX:
8788 if (strcasecmp (arg, "att") == 0)
8789 intel_syntax = 0;
8790 else if (strcasecmp (arg, "intel") == 0)
8791 intel_syntax = 1;
8792 else
2b5d6a91 8793 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 8794 break;
8795
8796 case OPTION_MINDEX_REG:
8797 allow_index_reg = 1;
8798 break;
8799
8800 case OPTION_MNAKED_REG:
8801 allow_naked_reg = 1;
8802 break;
8803
8804 case OPTION_MOLD_GCC:
8805 old_gcc = 1;
1efbbeb4
L		 8806 break;
8807
c0f3af97
L		 8808 case OPTION_MSSE2AVX:
8809 sse2avx = 1;
8810 break;
8811
daf50ae7
L		 8812 case OPTION_MSSE_CHECK:
8813 if (strcasecmp (arg, "error") == 0)
7bab8ab5 8814 sse_check = check_error;
daf50ae7 8815 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 8816 sse_check = check_warning;
daf50ae7 8817 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 8818 sse_check = check_none;
daf50ae7 8819 else
2b5d6a91 8820 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 8821 break;
8822
7bab8ab5
JB		 8823 case OPTION_MOPERAND_CHECK:
8824 if (strcasecmp (arg, "error") == 0)
8825 operand_check = check_error;
8826 else if (strcasecmp (arg, "warning") == 0)
8827 operand_check = check_warning;
8828 else if (strcasecmp (arg, "none") == 0)
8829 operand_check = check_none;
8830 else
8831 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
8832 break;
8833
539f890d
L		 8834 case OPTION_MAVXSCALAR:
8835 if (strcasecmp (arg, "128") == 0)
8836 avxscalar = vex128;
8837 else if (strcasecmp (arg, "256") == 0)
8838 avxscalar = vex256;
8839 else
2b5d6a91 8840 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 8841 break;
8842
252b5132
RH		 8843 default:
8844 return 0;
8845 }
8846 return 1;
8847}
8848
8a2c8fef
L		 8849#define MESSAGE_TEMPLATE \
8850" "
8851
8852static void
1ded5609 8853show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8854{
8855 static char message[] = MESSAGE_TEMPLATE;
8856 char *start = message + 27;
8857 char *p;
8858 int size = sizeof (MESSAGE_TEMPLATE);
8859 int left;
8860 const char *name;
8861 int len;
8862 unsigned int j;
8863
8864 p = start;
8865 left = size - (start - message);
8866 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8867 {
8868 /* Should it be skipped? */
8869 if (cpu_arch [j].skip)
8870 continue;
8871
8872 name = cpu_arch [j].name;
8873 len = cpu_arch [j].len;
8874 if (*name == '.')
8875 {
8876 /* It is an extension. Skip if we aren't asked to show it. */
8877 if (ext)
8878 {
8879 name++;
8880 len--;
8881 }
8882 else
8883 continue;
8884 }
8885 else if (ext)
8886 {
8887 /* It is an processor. Skip if we show only extension. */
8888 continue;
8889 }
1ded5609
JB		 8890 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8891 {
8892 /* It is an impossible processor - skip. */
8893 continue;
8894 }
8a2c8fef
L		 8895
8896 /* Reserve 2 spaces for ", " or ",\0" */
8897 left -= len + 2;
8898
8899 /* Check if there is any room. */
8900 if (left >= 0)
8901 {
8902 if (p != start)
8903 {
8904 *p++ = ',';
8905 *p++ = ' ';
8906 }
8907 p = mempcpy (p, name, len);
8908 }
8909 else
8910 {
8911 /* Output the current message now and start a new one. */
8912 *p++ = ',';
8913 *p = '\0';
8914 fprintf (stream, "%s\n", message);
8915 p = start;
8916 left = size - (start - message) - len - 2;
8d63c93e 8917
8a2c8fef
L		 8918 gas_assert (left >= 0);
8919
8920 p = mempcpy (p, name, len);
8921 }
8922 }
8923
8924 *p = '\0';
8925 fprintf (stream, "%s\n", message);
8926}
8927
252b5132 8928void
8a2c8fef 8929md_show_usage (FILE *stream)
252b5132 8930{
4cc782b5
ILT		 8931#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8932 fprintf (stream, _("\
a38cf1db
AM		 8933 -Q ignored\n\
8934 -V print assembler version number\n\
b3b91714
AM		 8935 -k ignored\n"));
8936#endif
8937 fprintf (stream, _("\
12b55ccc 8938 -n Do not optimize code alignment\n\
b3b91714
AM		 8939 -q quieten some warnings\n"));
8940#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8941 fprintf (stream, _("\
a38cf1db 8942 -s ignored\n"));
b3b91714 8943#endif
321098a5
L		 8944#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8945 || defined (TE_PE) || defined (TE_PEP))
751d281c 8946 fprintf (stream, _("\
570561f7 8947 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8948#endif
b3b91714
AM		 8949#ifdef SVR4_COMMENT_CHARS
8950 fprintf (stream, _("\
8951 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8952#else
8953 fprintf (stream, _("\
b3b91714 8954 --divide ignored\n"));
4cc782b5 8955#endif
9103f4f4 8956 fprintf (stream, _("\
6305a203 8957 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8958 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8959 show_arch (stream, 0, 1);
8a2c8fef
L		 8960 fprintf (stream, _("\
8961 EXTENSION is combination of:\n"));
1ded5609 8962 show_arch (stream, 1, 0);
6305a203 8963 fprintf (stream, _("\
8a2c8fef 8964 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8965 show_arch (stream, 0, 0);
ba104c83 8966 fprintf (stream, _("\
c0f3af97
L		 8967 -msse2avx encode SSE instructions with VEX prefix\n"));
8968 fprintf (stream, _("\
daf50ae7
L		 8969 -msse-check=[none|error|warning]\n\
8970 check SSE instructions\n"));
8971 fprintf (stream, _("\
7bab8ab5
JB		 8972 -moperand-check=[none|error|warning]\n\
8973 check operand combinations for validity\n"));
8974 fprintf (stream, _("\
539f890d
L		 8975 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8976 length\n"));
8977 fprintf (stream, _("\
ba104c83
L		 8978 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8979 fprintf (stream, _("\
8980 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8981 fprintf (stream, _("\
8982 -mindex-reg support pseudo index registers\n"));
8983 fprintf (stream, _("\
8984 -mnaked-reg don't require `%%' prefix for registers\n"));
8985 fprintf (stream, _("\
8986 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8987}
8988
3e73aa7c 8989#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8990 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8991 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8992
8993/* Pick the target format to use. */
8994
47926f60 8995const char *
e3bb37b5 8996i386_target_format (void)
252b5132 8997{
351f65ca
L		 8998 if (!strncmp (default_arch, "x86_64", 6))
8999 {
9000 update_code_flag (CODE_64BIT, 1);
9001 if (default_arch[6] == '\0')
7f56bc95 9002 x86_elf_abi = X86_64_ABI;
351f65ca 9003 else
7f56bc95 9004 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9005 }
3e73aa7c 9006 else if (!strcmp (default_arch, "i386"))
78f12dd3 9007 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9008 else
2b5d6a91 9009 as_fatal (_("unknown architecture"));
89507696
JB		 9010
9011 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9012 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9013 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9014 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9015
252b5132
RH		 9016 switch (OUTPUT_FLAVOR)
9017 {
9384f2ff 9018#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 9019 case bfd_target_aout_flavour:
47926f60 9020 return AOUT_TARGET_FORMAT;
4c63da97 9021#endif
9384f2ff
AM		 9022#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9023# if defined (TE_PE) || defined (TE_PEP)
9024 case bfd_target_coff_flavour:
9025 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9026# elif defined (TE_GO32)
0561d57c
JK		 9027 case bfd_target_coff_flavour:
9028 return "coff-go32";
9384f2ff 9029# else
252b5132
RH		 9030 case bfd_target_coff_flavour:
9031 return "coff-i386";
9384f2ff 9032# endif
4c63da97 9033#endif
3e73aa7c 9034#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 9035 case bfd_target_elf_flavour:
3e73aa7c 9036 {
351f65ca
L		 9037 const char *format;
9038
9039 switch (x86_elf_abi)
4fa24527 9040 {
351f65ca
L		 9041 default:
9042 format = ELF_TARGET_FORMAT;
9043 break;
7f56bc95 9044 case X86_64_ABI:
351f65ca 9045 use_rela_relocations = 1;
4fa24527 9046 object_64bit = 1;
351f65ca
L		 9047 format = ELF_TARGET_FORMAT64;
9048 break;
7f56bc95 9049 case X86_64_X32_ABI:
4fa24527 9050 use_rela_relocations = 1;
351f65ca 9051 object_64bit = 1;
862be3fb 9052 disallow_64bit_reloc = 1;
351f65ca
L		 9053 format = ELF_TARGET_FORMAT32;
9054 break;
4fa24527 9055 }
3632d14b 9056 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 9057 {
7f56bc95 9058 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 9059 as_fatal (_("Intel L1OM is 64bit only"));
9060 return ELF_TARGET_L1OM_FORMAT;
9061 }
7a9068fe
L		 9062 if (cpu_arch_isa == PROCESSOR_K1OM)
9063 {
9064 if (x86_elf_abi != X86_64_ABI)
9065 as_fatal (_("Intel K1OM is 64bit only"));
9066 return ELF_TARGET_K1OM_FORMAT;
9067 }
8a9036a4 9068 else
351f65ca 9069 return format;
3e73aa7c 9070 }
e57f8c65
TG		 9071#endif
9072#if defined (OBJ_MACH_O)
9073 case bfd_target_mach_o_flavour:
d382c579
TG		 9074 if (flag_code == CODE_64BIT)
9075 {
9076 use_rela_relocations = 1;
9077 object_64bit = 1;
9078 return "mach-o-x86-64";
9079 }
9080 else
9081 return "mach-o-i386";
4c63da97 9082#endif
252b5132
RH		 9083 default:
9084 abort ();
9085 return NULL;
9086 }
9087}
9088
47926f60 9089#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 9090
9091#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 9092void
9093i386_elf_emit_arch_note (void)
a847613f 9094{
718ddfc0 9095 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 9096 {
9097 char *p;
9098 asection *seg = now_seg;
9099 subsegT subseg = now_subseg;
9100 Elf_Internal_Note i_note;
9101 Elf_External_Note e_note;
9102 asection *note_secp;
9103 int len;
9104
9105 /* Create the .note section. */
9106 note_secp = subseg_new (".note", 0);
9107 bfd_set_section_flags (stdoutput,
9108 note_secp,
9109 SEC_HAS_CONTENTS | SEC_READONLY);
9110
9111 /* Process the arch string. */
9112 len = strlen (cpu_arch_name);
9113
9114 i_note.namesz = len + 1;
9115 i_note.descsz = 0;
9116 i_note.type = NT_ARCH;
9117 p = frag_more (sizeof (e_note.namesz));
9118 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
9119 p = frag_more (sizeof (e_note.descsz));
9120 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
9121 p = frag_more (sizeof (e_note.type));
9122 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
9123 p = frag_more (len + 1);
9124 strcpy (p, cpu_arch_name);
9125
9126 frag_align (2, 0, 0);
9127
9128 subseg_set (seg, subseg);
9129 }
9130}
9131#endif
252b5132 9132\f
252b5132 9133symbolS *
7016a5d5 9134md_undefined_symbol (char *name)
252b5132 9135{
18dc2407
ILT		 9136 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
9137 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
9138 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
9139 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 9140 {
9141 if (!GOT_symbol)
9142 {
9143 if (symbol_find (name))
9144 as_bad (_("GOT already in symbol table"));
9145 GOT_symbol = symbol_new (name, undefined_section,
9146 (valueT) 0, &zero_address_frag);
9147 };
9148 return GOT_symbol;
9149 }
252b5132
RH		 9150 return 0;
9151}
9152
9153/* Round up a section size to the appropriate boundary. */
47926f60 9154
252b5132 9155valueT
7016a5d5 9156md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 9157{
4c63da97
AM		 9158#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9159 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
9160 {
9161 /* For a.out, force the section size to be aligned. If we don't do
9162 this, BFD will align it for us, but it will not write out the
9163 final bytes of the section. This may be a bug in BFD, but it is
9164 easier to fix it here since that is how the other a.out targets
9165 work. */
9166 int align;
9167
9168 align = bfd_get_section_alignment (stdoutput, segment);
9169 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
9170 }
252b5132
RH		 9171#endif
9172
9173 return size;
9174}
9175
9176/* On the i386, PC-relative offsets are relative to the start of the
9177 next instruction. That is, the address of the offset, plus its
9178 size, since the offset is always the last part of the insn. */
9179
9180long
e3bb37b5 9181md_pcrel_from (fixS *fixP)
252b5132
RH		 9182{
9183 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
9184}
9185
9186#ifndef I386COFF
9187
9188static void
e3bb37b5 9189s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 9190{
29b0f896 9191 int temp;
252b5132 9192
8a75718c
JB		 9193#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9194 if (IS_ELF)
9195 obj_elf_section_change_hook ();
9196#endif
252b5132
RH		 9197 temp = get_absolute_expression ();
9198 subseg_set (bss_section, (subsegT) temp);
9199 demand_empty_rest_of_line ();
9200}
9201
9202#endif
9203
252b5132 9204void
e3bb37b5 9205i386_validate_fix (fixS *fixp)
252b5132
RH		 9206{
9207 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
9208 {
23df1078
JH		 9209 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
9210 {
4fa24527 9211 if (!object_64bit)
23df1078
JH		 9212 abort ();
9213 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
9214 }
9215 else
9216 {
4fa24527 9217 if (!object_64bit)
d6ab8113
JB		 9218 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
9219 else
9220 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 9221 }
252b5132
RH		 9222 fixp->fx_subsy = 0;
9223 }
9224}
9225
252b5132 9226arelent *
7016a5d5 9227tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 9228{
9229 arelent *rel;
9230 bfd_reloc_code_real_type code;
9231
9232 switch (fixp->fx_r_type)
9233 {
8ce3d284 9234#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 9235 case BFD_RELOC_SIZE32:
9236 case BFD_RELOC_SIZE64:
9237 if (S_IS_DEFINED (fixp->fx_addsy)
9238 && !S_IS_EXTERNAL (fixp->fx_addsy))
9239 {
9240 /* Resolve size relocation against local symbol to size of
9241 the symbol plus addend. */
9242 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
9243 if (fixp->fx_r_type == BFD_RELOC_SIZE32
9244 && !fits_in_unsigned_long (value))
9245 as_bad_where (fixp->fx_file, fixp->fx_line,
9246 _("symbol size computation overflow"));
9247 fixp->fx_addsy = NULL;
9248 fixp->fx_subsy = NULL;
9249 md_apply_fix (fixp, (valueT *) &value, NULL);
9250 return NULL;
9251 }
8ce3d284 9252#endif
8fd4256d 9253
3e73aa7c
JH		 9254 case BFD_RELOC_X86_64_PLT32:
9255 case BFD_RELOC_X86_64_GOT32:
9256 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 9257 case BFD_RELOC_386_PLT32:
9258 case BFD_RELOC_386_GOT32:
9259 case BFD_RELOC_386_GOTOFF:
9260 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 9261 case BFD_RELOC_386_TLS_GD:
9262 case BFD_RELOC_386_TLS_LDM:
9263 case BFD_RELOC_386_TLS_LDO_32:
9264 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9265 case BFD_RELOC_386_TLS_IE:
9266 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 9267 case BFD_RELOC_386_TLS_LE_32:
9268 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 9269 case BFD_RELOC_386_TLS_GOTDESC:
9270 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 9271 case BFD_RELOC_X86_64_TLSGD:
9272 case BFD_RELOC_X86_64_TLSLD:
9273 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9274 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 9275 case BFD_RELOC_X86_64_GOTTPOFF:
9276 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 9277 case BFD_RELOC_X86_64_TPOFF64:
9278 case BFD_RELOC_X86_64_GOTOFF64:
9279 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 9280 case BFD_RELOC_X86_64_GOT64:
9281 case BFD_RELOC_X86_64_GOTPCREL64:
9282 case BFD_RELOC_X86_64_GOTPC64:
9283 case BFD_RELOC_X86_64_GOTPLT64:
9284 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 9285 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9286 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 9287 case BFD_RELOC_RVA:
9288 case BFD_RELOC_VTABLE_ENTRY:
9289 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 9290#ifdef TE_PE
9291 case BFD_RELOC_32_SECREL:
9292#endif
252b5132
RH		 9293 code = fixp->fx_r_type;
9294 break;
dbbaec26
L		 9295 case BFD_RELOC_X86_64_32S:
9296 if (!fixp->fx_pcrel)
9297 {
9298 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9299 code = fixp->fx_r_type;
9300 break;
9301 }
252b5132 9302 default:
93382f6d 9303 if (fixp->fx_pcrel)
252b5132 9304 {
93382f6d
AM		 9305 switch (fixp->fx_size)
9306 {
9307 default:
b091f402
AM		 9308 as_bad_where (fixp->fx_file, fixp->fx_line,
9309 _("can not do %d byte pc-relative relocation"),
9310 fixp->fx_size);
93382f6d
AM		 9311 code = BFD_RELOC_32_PCREL;
9312 break;
9313 case 1: code = BFD_RELOC_8_PCREL; break;
9314 case 2: code = BFD_RELOC_16_PCREL; break;
9315 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 9316#ifdef BFD64
9317 case 8: code = BFD_RELOC_64_PCREL; break;
9318#endif
93382f6d
AM		 9319 }
9320 }
9321 else
9322 {
9323 switch (fixp->fx_size)
9324 {
9325 default:
b091f402
AM		 9326 as_bad_where (fixp->fx_file, fixp->fx_line,
9327 _("can not do %d byte relocation"),
9328 fixp->fx_size);
93382f6d
AM		 9329 code = BFD_RELOC_32;
9330 break;
9331 case 1: code = BFD_RELOC_8; break;
9332 case 2: code = BFD_RELOC_16; break;
9333 case 4: code = BFD_RELOC_32; break;
937149dd 9334#ifdef BFD64
3e73aa7c 9335 case 8: code = BFD_RELOC_64; break;
937149dd 9336#endif
93382f6d 9337 }
252b5132
RH		 9338 }
9339 break;
9340 }
252b5132 9341
d182319b
JB		 9342 if ((code == BFD_RELOC_32
9343 || code == BFD_RELOC_32_PCREL
9344 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 9345 && GOT_symbol
9346 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 9347 {
4fa24527 9348 if (!object_64bit)
d6ab8113
JB		 9349 code = BFD_RELOC_386_GOTPC;
9350 else
9351 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 9352 }
7b81dfbb
AJ		 9353 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
9354 && GOT_symbol
9355 && fixp->fx_addsy == GOT_symbol)
9356 {
9357 code = BFD_RELOC_X86_64_GOTPC64;
9358 }
252b5132
RH		 9359
9360 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 9361 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9362 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 9363
9364 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 9365
3e73aa7c
JH		 9366 if (!use_rela_relocations)
9367 {
9368 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9369 vtable entry to be used in the relocation's section offset. */
9370 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
9371 rel->address = fixp->fx_offset;
fbeb56a4
DK		 9372#if defined (OBJ_COFF) && defined (TE_PE)
9373 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
9374 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
9375 else
9376#endif
c6682705 9377 rel->addend = 0;
3e73aa7c
JH		 9378 }
9379 /* Use the rela in 64bit mode. */
252b5132 9380 else
3e73aa7c 9381 {
862be3fb
L		 9382 if (disallow_64bit_reloc)
9383 switch (code)
9384 {
862be3fb
L		 9385 case BFD_RELOC_X86_64_DTPOFF64:
9386 case BFD_RELOC_X86_64_TPOFF64:
9387 case BFD_RELOC_64_PCREL:
9388 case BFD_RELOC_X86_64_GOTOFF64:
9389 case BFD_RELOC_X86_64_GOT64:
9390 case BFD_RELOC_X86_64_GOTPCREL64:
9391 case BFD_RELOC_X86_64_GOTPC64:
9392 case BFD_RELOC_X86_64_GOTPLT64:
9393 case BFD_RELOC_X86_64_PLTOFF64:
9394 as_bad_where (fixp->fx_file, fixp->fx_line,
9395 _("cannot represent relocation type %s in x32 mode"),
9396 bfd_get_reloc_code_name (code));
9397 break;
9398 default:
9399 break;
9400 }
9401
062cd5e7
AS		 9402 if (!fixp->fx_pcrel)
9403 rel->addend = fixp->fx_offset;
9404 else
9405 switch (code)
9406 {
9407 case BFD_RELOC_X86_64_PLT32:
9408 case BFD_RELOC_X86_64_GOT32:
9409 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 9410 case BFD_RELOC_X86_64_TLSGD:
9411 case BFD_RELOC_X86_64_TLSLD:
9412 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 9413 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9414 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 9415 rel->addend = fixp->fx_offset - fixp->fx_size;
9416 break;
9417 default:
9418 rel->addend = (section->vma
9419 - fixp->fx_size
9420 + fixp->fx_addnumber
9421 + md_pcrel_from (fixp));
9422 break;
9423 }
3e73aa7c
JH		 9424 }
9425
252b5132
RH		 9426 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
9427 if (rel->howto == NULL)
9428 {
9429 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 9430 _("cannot represent relocation type %s"),
252b5132
RH		 9431 bfd_get_reloc_code_name (code));
9432 /* Set howto to a garbage value so that we can keep going. */
9433 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 9434 gas_assert (rel->howto != NULL);
252b5132
RH		 9435 }
9436
9437 return rel;
9438}
9439
ee86248c 9440#include "tc-i386-intel.c"
54cfded0 9441
a60de03c
JB		 9442void
9443tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9444{
a60de03c
JB		 9445 int saved_naked_reg;
9446 char saved_register_dot;
54cfded0 9447
a60de03c
JB		 9448 saved_naked_reg = allow_naked_reg;
9449 allow_naked_reg = 1;
9450 saved_register_dot = register_chars['.'];
9451 register_chars['.'] = '.';
9452 allow_pseudo_reg = 1;
9453 expression_and_evaluate (exp);
9454 allow_pseudo_reg = 0;
9455 register_chars['.'] = saved_register_dot;
9456 allow_naked_reg = saved_naked_reg;
9457
e96d56a1 9458 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9459 {
a60de03c
JB		 9460 if ((addressT) exp->X_add_number < i386_regtab_size)
9461 {
9462 exp->X_op = O_constant;
9463 exp->X_add_number = i386_regtab[exp->X_add_number]
9464 .dw2_regnum[flag_code >> 1];
9465 }
9466 else
9467 exp->X_op = O_illegal;
54cfded0 9468 }
54cfded0
AM		 9469}
9470
9471void
9472tc_x86_frame_initial_instructions (void)
9473{
a60de03c
JB		 9474 static unsigned int sp_regno[2];
9475
9476 if (!sp_regno[flag_code >> 1])
9477 {
9478 char *saved_input = input_line_pointer;
9479 char sp[][4] = {"esp", "rsp"};
9480 expressionS exp;
a4447b93 9481
a60de03c
JB		 9482 input_line_pointer = sp[flag_code >> 1];
9483 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9484 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9485 sp_regno[flag_code >> 1] = exp.X_add_number;
9486 input_line_pointer = saved_input;
9487 }
a4447b93 9488
61ff971f
L		 9489 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9490 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9491}
d2b2c203 9492
d7921315
L		 9493int
9494x86_dwarf2_addr_size (void)
9495{
9496#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9497 if (x86_elf_abi == X86_64_X32_ABI)
9498 return 4;
9499#endif
9500 return bfd_arch_bits_per_address (stdoutput) / 8;
9501}
9502
d2b2c203
DJ		 9503int
9504i386_elf_section_type (const char *str, size_t len)
9505{
9506 if (flag_code == CODE_64BIT
9507 && len == sizeof ("unwind") - 1
9508 && strncmp (str, "unwind", 6) == 0)
9509 return SHT_X86_64_UNWIND;
9510
9511 return -1;
9512}
bb41ade5 9513
ad5fec3b
EB		 9514#ifdef TE_SOLARIS
9515void
9516i386_solaris_fix_up_eh_frame (segT sec)
9517{
9518 if (flag_code == CODE_64BIT)
9519 elf_section_type (sec) = SHT_X86_64_UNWIND;
9520}
9521#endif
9522
bb41ade5
AM		 9523#ifdef TE_PE
9524void
9525tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9526{
91d6fa6a 9527 expressionS exp;
bb41ade5 9528
91d6fa6a
NC		 9529 exp.X_op = O_secrel;
9530 exp.X_add_symbol = symbol;
9531 exp.X_add_number = 0;
9532 emit_expr (&exp, size);
bb41ade5
AM		 9533}
9534#endif
3b22753a
L		 9535
9536#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9537/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9538
01e1a5bc 9539bfd_vma
3b22753a
L		 9540x86_64_section_letter (int letter, char **ptr_msg)
9541{
9542 if (flag_code == CODE_64BIT)
9543 {
9544 if (letter == 'l')
9545 return SHF_X86_64_LARGE;
9546
8f3bae45 9547 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9548 }
3b22753a 9549 else
8f3bae45 9550 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9551 return -1;
9552}
9553
01e1a5bc 9554bfd_vma
3b22753a
L		 9555x86_64_section_word (char *str, size_t len)
9556{
8620418b 9557 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9558 return SHF_X86_64_LARGE;
9559
9560 return -1;
9561}
9562
9563static void
9564handle_large_common (int small ATTRIBUTE_UNUSED)
9565{
9566 if (flag_code != CODE_64BIT)
9567 {
9568 s_comm_internal (0, elf_common_parse);
9569 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9570 }
9571 else
9572 {
9573 static segT lbss_section;
9574 asection *saved_com_section_ptr = elf_com_section_ptr;
9575 asection *saved_bss_section = bss_section;
9576
9577 if (lbss_section == NULL)
9578 {
9579 flagword applicable;
9580 segT seg = now_seg;
9581 subsegT subseg = now_subseg;
9582
9583 /* The .lbss section is for local .largecomm symbols. */
9584 lbss_section = subseg_new (".lbss", 0);
9585 applicable = bfd_applicable_section_flags (stdoutput);
9586 bfd_set_section_flags (stdoutput, lbss_section,
9587 applicable & SEC_ALLOC);
9588 seg_info (lbss_section)->bss = 1;
9589
9590 subseg_set (seg, subseg);
9591 }
9592
9593 elf_com_section_ptr = &_bfd_elf_large_com_section;
9594 bss_section = lbss_section;
9595
9596 s_comm_internal (0, elf_common_parse);
9597
9598 elf_com_section_ptr = saved_com_section_ptr;
9599 bss_section = saved_bss_section;
9600 }
9601}
9602#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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