Commit | Line | Data |
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fecd2382 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
e715a027 | 2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999 |
dddc8a82 | 3 | Free Software Foundation. |
355afbcd | 4 | |
a39116f1 | 5 | This file is part of GAS, the GNU Assembler. |
355afbcd | 6 | |
a39116f1 RP |
7 | GAS is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
355afbcd | 11 | |
a39116f1 RP |
12 | GAS is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
355afbcd | 16 | |
a39116f1 | 17 | You should have received a copy of the GNU General Public License |
e592f0e6 ILT |
18 | along with GAS; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
fecd2382 | 21 | |
fecd2382 RP |
22 | /* |
23 | Intel 80386 machine specific gas. | |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
25 | Bugs & suggestions are completely welcome. This is free software. | |
26 | Please help us make it better. | |
a39116f1 | 27 | */ |
fecd2382 | 28 | |
4b77b129 ILT |
29 | #include <ctype.h> |
30 | ||
fecd2382 | 31 | #include "as.h" |
0877841d | 32 | #include "subsegs.h" |
a39116f1 | 33 | #include "opcode/i386.h" |
fecd2382 | 34 | |
f0b37b4a KR |
35 | #ifndef TC_RELOC |
36 | #define TC_RELOC(X,Y) (Y) | |
37 | #endif | |
38 | ||
73a8be66 ILT |
39 | #ifndef REGISTER_WARNINGS |
40 | #define REGISTER_WARNINGS 1 | |
41 | #endif | |
42 | ||
ec1e6bb8 ILT |
43 | #ifndef SCALE1_WHEN_NO_INDEX |
44 | /* Specifying a scale factor besides 1 when there is no index is | |
45 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
46 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
47 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
48 | #define SCALE1_WHEN_NO_INDEX 1 | |
49 | #endif | |
50 | ||
e715a027 RH |
51 | #define true 1 |
52 | #define false 0 | |
53 | ||
61c49d66 | 54 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); |
f59fb6ca ILT |
55 | static int fits_in_signed_byte PARAMS ((long)); |
56 | static int fits_in_unsigned_byte PARAMS ((long)); | |
57 | static int fits_in_unsigned_word PARAMS ((long)); | |
58 | static int fits_in_signed_word PARAMS ((long)); | |
59 | static int smallest_imm_type PARAMS ((long)); | |
73a8be66 | 60 | static int add_prefix PARAMS ((unsigned int)); |
f59fb6ca | 61 | static void set_16bit_code_flag PARAMS ((int)); |
e715a027 RH |
62 | static void set_intel_syntax PARAMS ((int)); |
63 | ||
f59fb6ca ILT |
64 | #ifdef BFD_ASSEMBLER |
65 | static bfd_reloc_code_real_type reloc | |
66 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
67 | #endif | |
68 | ||
fecd2382 RP |
69 | /* 'md_assemble ()' gathers together information and puts it into a |
70 | i386_insn. */ | |
71 | ||
3c8df4ba | 72 | struct _i386_insn |
355afbcd KR |
73 | { |
74 | /* TM holds the template for the insn were currently assembling. */ | |
75 | template tm; | |
73a8be66 | 76 | |
668f52e0 ILT |
77 | /* SUFFIX holds the instruction mnemonic suffix if given. |
78 | (e.g. 'l' for 'movl') */ | |
355afbcd | 79 | char suffix; |
73a8be66 | 80 | |
355afbcd KR |
81 | /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */ |
82 | ||
83 | /* OPERANDS gives the number of given operands. */ | |
84 | unsigned int operands; | |
85 | ||
49864cfa KR |
86 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
87 | of given register, displacement, memory operands and immediate | |
88 | operands. */ | |
355afbcd KR |
89 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
90 | ||
91 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
49864cfa KR |
92 | search through DISPS [i] & IMMS [i] & REGS [i] for the required |
93 | operand. */ | |
355afbcd KR |
94 | unsigned int types[MAX_OPERANDS]; |
95 | ||
96 | /* Displacements (if given) for each operand. */ | |
97 | expressionS *disps[MAX_OPERANDS]; | |
98 | ||
f0b37b4a KR |
99 | /* Relocation type for operand */ |
100 | #ifdef BFD_ASSEMBLER | |
101 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
102 | #else | |
103 | int disp_reloc[MAX_OPERANDS]; | |
104 | #endif | |
105 | ||
355afbcd KR |
106 | /* Immediate operands (if given) for each operand. */ |
107 | expressionS *imms[MAX_OPERANDS]; | |
108 | ||
109 | /* Register operands (if given) for each operand. */ | |
73a8be66 | 110 | const reg_entry *regs[MAX_OPERANDS]; |
355afbcd KR |
111 | |
112 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode | |
49864cfa | 113 | the base index byte below. */ |
73a8be66 ILT |
114 | const reg_entry *base_reg; |
115 | const reg_entry *index_reg; | |
355afbcd KR |
116 | unsigned int log2_scale_factor; |
117 | ||
4498e3d6 ILT |
118 | /* SEG gives the seg_entries of this insn. They are zero unless |
119 | explicit segment overrides are given. */ | |
120 | const seg_entry *seg[2]; /* segments for memory operands (if given) */ | |
355afbcd KR |
121 | |
122 | /* PREFIX holds all the given prefix opcodes (usually null). | |
ec1e6bb8 | 123 | PREFIXES is the number of prefix opcodes. */ |
355afbcd | 124 | unsigned int prefixes; |
ec1e6bb8 | 125 | unsigned char prefix[MAX_PREFIXES]; |
355afbcd | 126 | |
0351b70c | 127 | /* RM and SIB are the modrm byte and the sib byte where the |
73a8be66 | 128 | addressing modes of this insn are encoded. */ |
355afbcd KR |
129 | |
130 | modrm_byte rm; | |
0351b70c | 131 | sib_byte sib; |
3c8df4ba | 132 | }; |
355afbcd | 133 | |
3c8df4ba | 134 | typedef struct _i386_insn i386_insn; |
fecd2382 | 135 | |
4edc93e9 ILT |
136 | /* List of chars besides those in app.c:symbol_chars that can start an |
137 | operand. Used to prevent the scrubber eating vital white-space. */ | |
138 | #ifdef LEX_AT | |
139 | const char extra_symbol_chars[] = "*%-(@"; | |
140 | #else | |
141 | const char extra_symbol_chars[] = "*%-("; | |
142 | #endif | |
143 | ||
a39116f1 RP |
144 | /* This array holds the chars that always start a comment. If the |
145 | pre-processor is disabled, these aren't very useful */ | |
4edc93e9 ILT |
146 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX)) |
147 | /* Putting '/' here makes it impossible to use the divide operator. | |
148 | However, we need it for compatibility with SVR4 systems. */ | |
49864cfa | 149 | const char comment_chars[] = "#/"; |
0351b70c | 150 | #define PREFIX_SEPARATOR '\\' |
49864cfa | 151 | #else |
a39116f1 | 152 | const char comment_chars[] = "#"; |
0351b70c | 153 | #define PREFIX_SEPARATOR '/' |
49864cfa | 154 | #endif |
fecd2382 | 155 | |
a39116f1 RP |
156 | /* This array holds the chars that only start a comment at the beginning of |
157 | a line. If the line seems to have the form '# 123 filename' | |
158 | .line and .file directives will appear in the pre-processed output */ | |
159 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
160 | first line of the input file. This is because the compiler outputs | |
161 | #NO_APP at the beginning of its output. */ | |
162 | /* Also note that comments started like this one will always work if | |
f3d817d8 | 163 | '/' isn't otherwise defined. */ |
4edc93e9 | 164 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX)) |
ad660eb1 | 165 | const char line_comment_chars[] = ""; |
7b23213f KR |
166 | #else |
167 | const char line_comment_chars[] = "/"; | |
168 | #endif | |
0351b70c | 169 | |
355afbcd | 170 | const char line_separator_chars[] = ""; |
fecd2382 | 171 | |
a39116f1 RP |
172 | /* Chars that can be used to separate mant from exp in floating point nums */ |
173 | const char EXP_CHARS[] = "eE"; | |
fecd2382 | 174 | |
a39116f1 RP |
175 | /* Chars that mean this number is a floating point constant */ |
176 | /* As in 0f12.456 */ | |
177 | /* or 0d1.2345e12 */ | |
178 | const char FLT_CHARS[] = "fFdDxX"; | |
fecd2382 RP |
179 | |
180 | /* tables for lexical analysis */ | |
668f52e0 | 181 | static char mnemonic_chars[256]; |
fecd2382 RP |
182 | static char register_chars[256]; |
183 | static char operand_chars[256]; | |
fecd2382 RP |
184 | static char identifier_chars[256]; |
185 | static char digit_chars[256]; | |
186 | ||
187 | /* lexical macros */ | |
668f52e0 | 188 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
fecd2382 RP |
189 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) |
190 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
4edc93e9 | 191 | #define is_space_char(x) ((x) == ' ') |
fecd2382 RP |
192 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) |
193 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
194 | ||
195 | /* put here all non-digit non-letter charcters that may occur in an operand */ | |
f0b37b4a | 196 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
fecd2382 | 197 | |
fecd2382 RP |
198 | /* md_assemble() always leaves the strings it's passed unaltered. To |
199 | effect this we maintain a stack of saved characters that we've smashed | |
200 | with '\0's (indicating end of strings for various sub-fields of the | |
201 | assembler instruction). */ | |
202 | static char save_stack[32]; | |
203 | static char *save_stack_p; /* stack pointer */ | |
aa56747a ILT |
204 | #define END_STRING_AND_SAVE(s) \ |
205 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
206 | #define RESTORE_END_STRING(s) \ | |
207 | do { *(s) = *--save_stack_p; } while (0) | |
355afbcd KR |
208 | |
209 | /* The instruction we're assembling. */ | |
210 | static i386_insn i; | |
fecd2382 | 211 | |
4498e3d6 | 212 | /* Possible templates for current insn. */ |
0351b70c | 213 | static const templates *current_templates; |
4498e3d6 | 214 | |
fecd2382 RP |
215 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
216 | static expressionS disp_expressions[2], im_expressions[2]; | |
217 | ||
fecd2382 RP |
218 | static int this_operand; /* current operand we are working on */ |
219 | ||
ade614d5 KR |
220 | static int flag_do_long_jump; /* FIXME what does this do? */ |
221 | ||
c54c7aac KR |
222 | static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */ |
223 | ||
e715a027 RH |
224 | static int intel_syntax = 0; /* 1 for intel syntax, 0 if att syntax */ |
225 | ||
226 | static int allow_naked_reg = 0; /* 1 if register prefix % not required */ | |
227 | ||
3c8df4ba KR |
228 | /* Interface to relax_segment. |
229 | There are 2 relax states for 386 jump insns: one for conditional & | |
230 | one for unconditional jumps. This is because the these two types | |
231 | of jumps add different sizes to frags when we're figuring out what | |
232 | sort of jump to choose to reach a given label. */ | |
fecd2382 RP |
233 | |
234 | /* types */ | |
235 | #define COND_JUMP 1 /* conditional jump */ | |
236 | #define UNCOND_JUMP 2 /* unconditional jump */ | |
237 | /* sizes */ | |
0351b70c ILT |
238 | #define CODE16 1 |
239 | #define SMALL 0 | |
240 | #define SMALL16 (SMALL|CODE16) | |
241 | #define BIG 2 | |
242 | #define BIG16 (BIG|CODE16) | |
fecd2382 | 243 | |
3c8df4ba KR |
244 | #ifndef INLINE |
245 | #ifdef __GNUC__ | |
246 | #define INLINE __inline__ | |
247 | #else | |
248 | #define INLINE | |
249 | #endif | |
250 | #endif | |
251 | ||
ad660eb1 ILT |
252 | #define ENCODE_RELAX_STATE(type,size) \ |
253 | ((relax_substateT)((type<<2) | (size))) | |
fecd2382 | 254 | #define SIZE_FROM_RELAX_STATE(s) \ |
0351b70c ILT |
255 | ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) |
256 | ||
257 | /* This table is used by relax_frag to promote short jumps to long | |
258 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
259 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
260 | don't allow a short jump in a 32 bit code segment to be promoted to | |
261 | a 16 bit offset jump because it's slower (requires data size | |
262 | prefix), and doesn't work, unless the destination is in the bottom | |
263 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
fecd2382 | 264 | |
355afbcd KR |
265 | const relax_typeS md_relax_table[] = |
266 | { | |
49864cfa KR |
267 | /* The fields are: |
268 | 1) most positive reach of this state, | |
269 | 2) most negative reach of this state, | |
270 | 3) how many bytes this mode will add to the size of the current frag | |
271 | 4) which index into the table to try if we can't fit into this one. | |
272 | */ | |
355afbcd KR |
273 | {1, 1, 0, 0}, |
274 | {1, 1, 0, 0}, | |
275 | {1, 1, 0, 0}, | |
276 | {1, 1, 0, 0}, | |
277 | ||
0351b70c ILT |
278 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, |
279 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
3c8df4ba | 280 | /* dword conditionals adds 4 bytes to frag: |
0351b70c | 281 | 1 extra opcode byte, 3 extra displacement bytes. */ |
355afbcd | 282 | {0, 0, 4, 0}, |
0351b70c ILT |
283 | /* word conditionals add 2 bytes to frag: |
284 | 1 extra opcode byte, 1 extra displacement byte. */ | |
285 | {0, 0, 2, 0}, | |
355afbcd | 286 | |
0351b70c ILT |
287 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
288 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
3c8df4ba | 289 | /* dword jmp adds 3 bytes to frag: |
0351b70c | 290 | 0 extra opcode bytes, 3 extra displacement bytes. */ |
355afbcd | 291 | {0, 0, 3, 0}, |
0351b70c ILT |
292 | /* word jmp adds 1 byte to frag: |
293 | 0 extra opcode bytes, 1 extra displacement byte. */ | |
294 | {0, 0, 1, 0} | |
355afbcd | 295 | |
fecd2382 RP |
296 | }; |
297 | ||
3ea36b53 ILT |
298 | |
299 | void | |
300 | i386_align_code (fragP, count) | |
301 | fragS *fragP; | |
302 | int count; | |
303 | { | |
304 | /* Various efficient no-op patterns for aligning code labels. */ | |
fb50cd4e ILT |
305 | /* Note: Don't try to assemble the instructions in the comments. */ |
306 | /* 0L and 0w are not legal */ | |
307 | static const char f32_1[] = | |
308 | {0x90}; /* nop */ | |
309 | static const char f32_2[] = | |
310 | {0x89,0xf6}; /* movl %esi,%esi */ | |
311 | static const char f32_3[] = | |
312 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
313 | static const char f32_4[] = | |
314 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
315 | static const char f32_5[] = | |
316 | {0x90, /* nop */ | |
317 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
318 | static const char f32_6[] = | |
319 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
320 | static const char f32_7[] = | |
321 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
322 | static const char f32_8[] = | |
323 | {0x90, /* nop */ | |
324 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
325 | static const char f32_9[] = | |
326 | {0x89,0xf6, /* movl %esi,%esi */ | |
327 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
328 | static const char f32_10[] = | |
329 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
330 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
331 | static const char f32_11[] = | |
332 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
333 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
334 | static const char f32_12[] = | |
335 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
336 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
337 | static const char f32_13[] = | |
338 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
339 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
340 | static const char f32_14[] = | |
341 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
342 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
343 | static const char f32_15[] = | |
344 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
345 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
346 | static const char f16_4[] = | |
388fa5c6 | 347 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
fb50cd4e ILT |
348 | static const char f16_5[] = |
349 | {0x90, /* nop */ | |
388fa5c6 | 350 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
fb50cd4e ILT |
351 | static const char f16_6[] = |
352 | {0x89,0xf6, /* mov %si,%si */ | |
353 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
354 | static const char f16_7[] = | |
388fa5c6 | 355 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
fb50cd4e ILT |
356 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
357 | static const char f16_8[] = | |
388fa5c6 | 358 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
fb50cd4e | 359 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
3ea36b53 ILT |
360 | static const char *const f32_patt[] = { |
361 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
362 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
363 | }; | |
364 | static const char *const f16_patt[] = { | |
365 | f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8, | |
366 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 | |
367 | }; | |
368 | ||
369 | if (count > 0 && count <= 15) | |
370 | { | |
371 | if (flag_16bit_code) | |
372 | { | |
373 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
374 | f16_patt[count - 1], count); | |
375 | if (count > 8) /* adjust jump offset */ | |
376 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
377 | } | |
378 | else | |
379 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
380 | f32_patt[count - 1], count); | |
381 | fragP->fr_var = count; | |
382 | } | |
383 | } | |
384 | ||
49864cfa KR |
385 | static char *output_invalid PARAMS ((int c)); |
386 | static int i386_operand PARAMS ((char *operand_string)); | |
e715a027 | 387 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); |
4edc93e9 ILT |
388 | static const reg_entry *parse_register PARAMS ((char *reg_string, |
389 | char **end_op)); | |
e715a027 | 390 | |
49864cfa | 391 | #ifndef I386COFF |
ad660eb1 | 392 | static void s_bss PARAMS ((int)); |
49864cfa | 393 | #endif |
fecd2382 | 394 | |
4498e3d6 | 395 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
f0b37b4a | 396 | |
61c49d66 | 397 | static INLINE unsigned int |
49864cfa | 398 | mode_from_disp_size (t) |
61c49d66 | 399 | unsigned int t; |
49864cfa | 400 | { |
73a8be66 | 401 | return (t & Disp8) ? 1 : (t & (Disp16|Disp32)) ? 2 : 0; |
3c8df4ba | 402 | } |
49864cfa | 403 | |
3c8df4ba | 404 | static INLINE int |
49864cfa KR |
405 | fits_in_signed_byte (num) |
406 | long num; | |
407 | { | |
3c8df4ba | 408 | return (num >= -128) && (num <= 127); |
49864cfa KR |
409 | } /* fits_in_signed_byte() */ |
410 | ||
3c8df4ba | 411 | static INLINE int |
49864cfa KR |
412 | fits_in_unsigned_byte (num) |
413 | long num; | |
414 | { | |
3c8df4ba | 415 | return (num & 0xff) == num; |
49864cfa KR |
416 | } /* fits_in_unsigned_byte() */ |
417 | ||
3c8df4ba | 418 | static INLINE int |
49864cfa KR |
419 | fits_in_unsigned_word (num) |
420 | long num; | |
421 | { | |
3c8df4ba | 422 | return (num & 0xffff) == num; |
49864cfa KR |
423 | } /* fits_in_unsigned_word() */ |
424 | ||
3c8df4ba | 425 | static INLINE int |
49864cfa KR |
426 | fits_in_signed_word (num) |
427 | long num; | |
428 | { | |
3c8df4ba | 429 | return (-32768 <= num) && (num <= 32767); |
49864cfa KR |
430 | } /* fits_in_signed_word() */ |
431 | ||
432 | static int | |
433 | smallest_imm_type (num) | |
434 | long num; | |
435 | { | |
f3d817d8 DM |
436 | #if 0 |
437 | /* This code is disabled because all the Imm1 forms in the opcode table | |
438 | are slower on the i486, and they're the versions with the implicitly | |
439 | specified single-position displacement, which has another syntax if | |
440 | you really want to use that form. If you really prefer to have the | |
441 | one-byte-shorter Imm1 form despite these problems, re-enable this | |
442 | code. */ | |
443 | if (num == 1) | |
444 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
445 | #endif | |
446 | return (fits_in_signed_byte (num) | |
3c8df4ba KR |
447 | ? (Imm8S | Imm8 | Imm16 | Imm32) |
448 | : fits_in_unsigned_byte (num) | |
449 | ? (Imm8 | Imm16 | Imm32) | |
450 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
451 | ? (Imm16 | Imm32) | |
452 | : (Imm32)); | |
49864cfa | 453 | } /* smallest_imm_type() */ |
fecd2382 | 454 | |
aa56747a ILT |
455 | /* Returns 0 if attempting to add a prefix where one from the same |
456 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
457 | added. */ | |
4498e3d6 | 458 | static int |
aa56747a | 459 | add_prefix (prefix) |
73a8be66 | 460 | unsigned int prefix; |
4498e3d6 | 461 | { |
aa56747a | 462 | int ret = 1; |
4498e3d6 ILT |
463 | int q; |
464 | ||
aa56747a | 465 | switch (prefix) |
4498e3d6 | 466 | { |
73a8be66 ILT |
467 | default: |
468 | abort (); | |
469 | ||
aa56747a ILT |
470 | case CS_PREFIX_OPCODE: |
471 | case DS_PREFIX_OPCODE: | |
472 | case ES_PREFIX_OPCODE: | |
473 | case FS_PREFIX_OPCODE: | |
474 | case GS_PREFIX_OPCODE: | |
475 | case SS_PREFIX_OPCODE: | |
476 | q = SEG_PREFIX; | |
477 | break; | |
4498e3d6 | 478 | |
0351b70c ILT |
479 | case REPNE_PREFIX_OPCODE: |
480 | case REPE_PREFIX_OPCODE: | |
aa56747a ILT |
481 | ret = 2; |
482 | /* fall thru */ | |
483 | case LOCK_PREFIX_OPCODE: | |
484 | q = LOCKREP_PREFIX; | |
485 | break; | |
4498e3d6 | 486 | |
aa56747a ILT |
487 | case FWAIT_OPCODE: |
488 | q = WAIT_PREFIX; | |
489 | break; | |
4498e3d6 | 490 | |
aa56747a ILT |
491 | case ADDR_PREFIX_OPCODE: |
492 | q = ADDR_PREFIX; | |
493 | break; | |
494 | ||
73a8be66 | 495 | case DATA_PREFIX_OPCODE: |
aa56747a | 496 | q = DATA_PREFIX; |
73a8be66 | 497 | break; |
4498e3d6 ILT |
498 | } |
499 | ||
aa56747a | 500 | if (i.prefix[q]) |
4498e3d6 | 501 | { |
aa56747a | 502 | as_bad (_("same type of prefix used twice")); |
4498e3d6 ILT |
503 | return 0; |
504 | } | |
505 | ||
aa56747a ILT |
506 | i.prefixes += 1; |
507 | i.prefix[q] = prefix; | |
508 | return ret; | |
4498e3d6 ILT |
509 | } |
510 | ||
f59fb6ca ILT |
511 | static void |
512 | set_16bit_code_flag (new_16bit_code_flag) | |
c54c7aac KR |
513 | int new_16bit_code_flag; |
514 | { | |
515 | flag_16bit_code = new_16bit_code_flag; | |
516 | } | |
517 | ||
e715a027 RH |
518 | static void |
519 | set_intel_syntax (syntax_flag) | |
520 | int syntax_flag; | |
521 | { | |
522 | /* Find out if register prefixing is specified. */ | |
523 | int ask_naked_reg = 0; | |
524 | ||
525 | SKIP_WHITESPACE (); | |
526 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
527 | { | |
528 | char *string = input_line_pointer; | |
529 | int e = get_symbol_end (); | |
530 | ||
531 | if (strcmp(string, "prefix") == 0) | |
532 | ask_naked_reg = 1; | |
533 | else if (strcmp(string, "noprefix") == 0) | |
534 | ask_naked_reg = -1; | |
535 | else | |
536 | as_bad (_("Bad argument to syntax directive.")); | |
537 | *input_line_pointer = e; | |
538 | } | |
539 | demand_empty_rest_of_line (); | |
540 | ||
541 | intel_syntax = syntax_flag; | |
542 | ||
543 | if (ask_naked_reg == 0) | |
544 | { | |
545 | #ifdef BFD_ASSEMBLER | |
546 | allow_naked_reg = (intel_syntax | |
547 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
548 | #else | |
549 | allow_naked_reg = 0; /* conservative default */ | |
550 | #endif | |
551 | } | |
552 | else | |
553 | allow_naked_reg = (ask_naked_reg < 0); | |
554 | } | |
555 | ||
355afbcd KR |
556 | const pseudo_typeS md_pseudo_table[] = |
557 | { | |
49864cfa | 558 | #ifndef I386COFF |
355afbcd | 559 | {"bss", s_bss, 0}, |
49864cfa | 560 | #endif |
02bdbd8b | 561 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
355afbcd | 562 | {"align", s_align_bytes, 0}, |
49864cfa KR |
563 | #else |
564 | {"align", s_align_ptwo, 0}, | |
565 | #endif | |
355afbcd KR |
566 | {"ffloat", float_cons, 'f'}, |
567 | {"dfloat", float_cons, 'd'}, | |
568 | {"tfloat", float_cons, 'x'}, | |
569 | {"value", cons, 2}, | |
49864cfa KR |
570 | {"noopt", s_ignore, 0}, |
571 | {"optim", s_ignore, 0}, | |
c54c7aac KR |
572 | {"code16", set_16bit_code_flag, 1}, |
573 | {"code32", set_16bit_code_flag, 0}, | |
e715a027 RH |
574 | {"intel_syntax", set_intel_syntax, 1}, |
575 | {"att_syntax", set_intel_syntax, 0}, | |
355afbcd | 576 | {0, 0, 0} |
fecd2382 RP |
577 | }; |
578 | ||
579 | /* for interface with expression () */ | |
355afbcd | 580 | extern char *input_line_pointer; |
fecd2382 | 581 | |
668f52e0 | 582 | /* hash table for instruction mnemonic lookup */ |
f3d817d8 | 583 | static struct hash_control *op_hash; |
fecd2382 | 584 | /* hash table for register lookup */ |
f3d817d8 | 585 | static struct hash_control *reg_hash; |
fecd2382 | 586 | \f |
355afbcd KR |
587 | |
588 | void | |
589 | md_begin () | |
fecd2382 | 590 | { |
ad660eb1 | 591 | const char *hash_err; |
355afbcd | 592 | |
355afbcd | 593 | /* initialize op_hash hash table */ |
f3d817d8 | 594 | op_hash = hash_new (); |
355afbcd KR |
595 | |
596 | { | |
597 | register const template *optab; | |
598 | register templates *core_optab; | |
355afbcd KR |
599 | |
600 | optab = i386_optab; /* setup for loop */ | |
355afbcd | 601 | core_optab = (templates *) xmalloc (sizeof (templates)); |
0351b70c | 602 | core_optab->start = optab; |
355afbcd | 603 | |
0351b70c | 604 | while (1) |
355afbcd | 605 | { |
0351b70c ILT |
606 | ++optab; |
607 | if (optab->name == NULL | |
608 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
355afbcd KR |
609 | { |
610 | /* different name --> ship out current template list; | |
49864cfa | 611 | add to hash table; & begin anew */ |
0351b70c ILT |
612 | core_optab->end = optab; |
613 | hash_err = hash_insert (op_hash, | |
614 | (optab - 1)->name, | |
615 | (PTR) core_optab); | |
ad660eb1 | 616 | if (hash_err) |
355afbcd KR |
617 | { |
618 | hash_error: | |
0351b70c ILT |
619 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
620 | (optab - 1)->name, | |
3c8df4ba | 621 | hash_err); |
355afbcd | 622 | } |
0351b70c ILT |
623 | if (optab->name == NULL) |
624 | break; | |
355afbcd | 625 | core_optab = (templates *) xmalloc (sizeof (templates)); |
0351b70c | 626 | core_optab->start = optab; |
355afbcd KR |
627 | } |
628 | } | |
629 | } | |
630 | ||
631 | /* initialize reg_hash hash table */ | |
632 | reg_hash = hash_new (); | |
633 | { | |
634 | register const reg_entry *regtab; | |
635 | ||
0351b70c ILT |
636 | for (regtab = i386_regtab; |
637 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
638 | regtab++) | |
355afbcd | 639 | { |
ad660eb1 ILT |
640 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); |
641 | if (hash_err) | |
355afbcd KR |
642 | goto hash_error; |
643 | } | |
644 | } | |
645 | ||
668f52e0 | 646 | /* fill in lexical tables: mnemonic_chars, operand_chars. */ |
355afbcd | 647 | { |
ad660eb1 ILT |
648 | register int c; |
649 | register char *p; | |
355afbcd KR |
650 | |
651 | for (c = 0; c < 256; c++) | |
652 | { | |
0351b70c | 653 | if (isdigit (c)) |
355afbcd | 654 | { |
0351b70c | 655 | digit_chars[c] = c; |
668f52e0 | 656 | mnemonic_chars[c] = c; |
355afbcd | 657 | register_chars[c] = c; |
0351b70c | 658 | operand_chars[c] = c; |
355afbcd | 659 | } |
0351b70c | 660 | else if (islower (c)) |
355afbcd | 661 | { |
668f52e0 | 662 | mnemonic_chars[c] = c; |
0351b70c ILT |
663 | register_chars[c] = c; |
664 | operand_chars[c] = c; | |
355afbcd | 665 | } |
0351b70c | 666 | else if (isupper (c)) |
355afbcd | 667 | { |
668f52e0 ILT |
668 | mnemonic_chars[c] = tolower (c); |
669 | register_chars[c] = mnemonic_chars[c]; | |
0351b70c | 670 | operand_chars[c] = c; |
355afbcd KR |
671 | } |
672 | ||
0351b70c | 673 | if (isalpha (c) || isdigit (c)) |
355afbcd | 674 | identifier_chars[c] = c; |
668f52e0 ILT |
675 | else if (c >= 128) |
676 | { | |
677 | identifier_chars[c] = c; | |
678 | operand_chars[c] = c; | |
679 | } | |
0351b70c | 680 | } |
355afbcd | 681 | |
30355216 | 682 | #ifdef LEX_AT |
0351b70c | 683 | identifier_chars['@'] = '@'; |
30355216 | 684 | #endif |
0351b70c ILT |
685 | register_chars[')'] = ')'; |
686 | register_chars['('] = '('; | |
687 | digit_chars['-'] = '-'; | |
688 | identifier_chars['_'] = '_'; | |
689 | identifier_chars['.'] = '.'; | |
ad660eb1 ILT |
690 | |
691 | for (p = operand_special_chars; *p != '\0'; p++) | |
692 | operand_chars[(unsigned char) *p] = *p; | |
355afbcd | 693 | } |
ad660eb1 | 694 | |
590c50d8 ILT |
695 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
696 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
697 | { | |
698 | record_alignment (text_section, 2); | |
699 | record_alignment (data_section, 2); | |
700 | record_alignment (bss_section, 2); | |
701 | } | |
ad660eb1 | 702 | #endif |
fecd2382 | 703 | } |
3ea36b53 ILT |
704 | |
705 | void | |
706 | i386_print_statistics (file) | |
707 | FILE *file; | |
708 | { | |
709 | hash_print_statistics (file, "i386 opcode", op_hash); | |
710 | hash_print_statistics (file, "i386 register", reg_hash); | |
3ea36b53 | 711 | } |
fecd2382 | 712 | \f |
355afbcd | 713 | |
fecd2382 RP |
714 | #ifdef DEBUG386 |
715 | ||
716 | /* debugging routines for md_assemble */ | |
ad660eb1 ILT |
717 | static void pi PARAMS ((char *, i386_insn *)); |
718 | static void pte PARAMS ((template *)); | |
719 | static void pt PARAMS ((unsigned int)); | |
720 | static void pe PARAMS ((expressionS *)); | |
721 | static void ps PARAMS ((symbolS *)); | |
fecd2382 | 722 | |
355afbcd KR |
723 | static void |
724 | pi (line, x) | |
725 | char *line; | |
726 | i386_insn *x; | |
fecd2382 | 727 | { |
355afbcd KR |
728 | register template *p; |
729 | int i; | |
730 | ||
731 | fprintf (stdout, "%s: template ", line); | |
732 | pte (&x->tm); | |
733 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
734 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
735 | fprintf (stdout, " base %x index %x scale %x\n", | |
736 | x->bi.base, x->bi.index, x->bi.scale); | |
737 | for (i = 0; i < x->operands; i++) | |
738 | { | |
739 | fprintf (stdout, " #%d: ", i + 1); | |
740 | pt (x->types[i]); | |
741 | fprintf (stdout, "\n"); | |
a52f90a4 ILT |
742 | if (x->types[i] |
743 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
744 | fprintf (stdout, "%s\n", x->regs[i]->reg_name); |
745 | if (x->types[i] & Imm) | |
746 | pe (x->imms[i]); | |
73a8be66 | 747 | if (x->types[i] & Disp) |
355afbcd KR |
748 | pe (x->disps[i]); |
749 | } | |
fecd2382 RP |
750 | } |
751 | ||
355afbcd KR |
752 | static void |
753 | pte (t) | |
754 | template *t; | |
fecd2382 | 755 | { |
355afbcd KR |
756 | int i; |
757 | fprintf (stdout, " %d operands ", t->operands); | |
758 | fprintf (stdout, "opcode %x ", | |
759 | t->base_opcode); | |
760 | if (t->extension_opcode != None) | |
761 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
762 | if (t->opcode_modifier & D) | |
763 | fprintf (stdout, "D"); | |
764 | if (t->opcode_modifier & W) | |
765 | fprintf (stdout, "W"); | |
766 | fprintf (stdout, "\n"); | |
767 | for (i = 0; i < t->operands; i++) | |
768 | { | |
769 | fprintf (stdout, " #%d type ", i + 1); | |
770 | pt (t->operand_types[i]); | |
771 | fprintf (stdout, "\n"); | |
772 | } | |
fecd2382 RP |
773 | } |
774 | ||
355afbcd KR |
775 | static void |
776 | pe (e) | |
777 | expressionS *e; | |
fecd2382 | 778 | { |
5ac34ac3 | 779 | fprintf (stdout, " operation %d\n", e->X_op); |
355afbcd KR |
780 | fprintf (stdout, " add_number %d (%x)\n", |
781 | e->X_add_number, e->X_add_number); | |
782 | if (e->X_add_symbol) | |
783 | { | |
784 | fprintf (stdout, " add_symbol "); | |
785 | ps (e->X_add_symbol); | |
786 | fprintf (stdout, "\n"); | |
787 | } | |
5ac34ac3 | 788 | if (e->X_op_symbol) |
355afbcd | 789 | { |
5ac34ac3 ILT |
790 | fprintf (stdout, " op_symbol "); |
791 | ps (e->X_op_symbol); | |
355afbcd KR |
792 | fprintf (stdout, "\n"); |
793 | } | |
fecd2382 RP |
794 | } |
795 | ||
355afbcd KR |
796 | static void |
797 | ps (s) | |
798 | symbolS *s; | |
fecd2382 | 799 | { |
355afbcd KR |
800 | fprintf (stdout, "%s type %s%s", |
801 | S_GET_NAME (s), | |
802 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
803 | segment_name (S_GET_SEGMENT (s))); | |
fecd2382 RP |
804 | } |
805 | ||
355afbcd KR |
806 | struct type_name |
807 | { | |
808 | unsigned int mask; | |
809 | char *tname; | |
810 | } | |
811 | ||
812 | type_names[] = | |
813 | { | |
814 | { Reg8, "r8" }, | |
815 | { Reg16, "r16" }, | |
816 | { Reg32, "r32" }, | |
817 | { Imm8, "i8" }, | |
818 | { Imm8S, "i8s" }, | |
819 | { Imm16, "i16" }, | |
820 | { Imm32, "i32" }, | |
73a8be66 | 821 | { Imm1, "i1" }, |
355afbcd | 822 | { BaseIndex, "BaseIndex" }, |
355afbcd KR |
823 | { Disp8, "d8" }, |
824 | { Disp16, "d16" }, | |
825 | { Disp32, "d32" }, | |
355afbcd KR |
826 | { InOutPortReg, "InOutPortReg" }, |
827 | { ShiftCount, "ShiftCount" }, | |
355afbcd KR |
828 | { Control, "control reg" }, |
829 | { Test, "test reg" }, | |
4498e3d6 | 830 | { Debug, "debug reg" }, |
355afbcd KR |
831 | { FloatReg, "FReg" }, |
832 | { FloatAcc, "FAcc" }, | |
73a8be66 ILT |
833 | { SReg2, "SReg2" }, |
834 | { SReg3, "SReg3" }, | |
835 | { Acc, "Acc" }, | |
355afbcd | 836 | { JumpAbsolute, "Jump Absolute" }, |
454b0ccd | 837 | { RegMMX, "rMMX" }, |
4498e3d6 | 838 | { EsSeg, "es" }, |
355afbcd | 839 | { 0, "" } |
fecd2382 RP |
840 | }; |
841 | ||
355afbcd KR |
842 | static void |
843 | pt (t) | |
844 | unsigned int t; | |
fecd2382 | 845 | { |
355afbcd KR |
846 | register struct type_name *ty; |
847 | ||
848 | if (t == Unknown) | |
849 | { | |
48401fcf | 850 | fprintf (stdout, _("Unknown")); |
355afbcd KR |
851 | } |
852 | else | |
853 | { | |
854 | for (ty = type_names; ty->mask; ty++) | |
855 | if (t & ty->mask) | |
856 | fprintf (stdout, "%s, ", ty->tname); | |
857 | } | |
858 | fflush (stdout); | |
fecd2382 RP |
859 | } |
860 | ||
861 | #endif /* DEBUG386 */ | |
862 | \f | |
a1624e3f RH |
863 | int |
864 | tc_i386_force_relocation (fixp) | |
865 | struct fix *fixp; | |
866 | { | |
867 | #ifdef BFD_ASSEMBLER | |
868 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
869 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
870 | return 1; | |
871 | return 0; | |
872 | #else | |
873 | /* For COFF */ | |
874 | return fixp->fx_r_type==7; | |
875 | #endif | |
876 | } | |
877 | ||
49864cfa | 878 | #ifdef BFD_ASSEMBLER |
e715a027 RH |
879 | static bfd_reloc_code_real_type reloc |
880 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
881 | ||
49864cfa | 882 | static bfd_reloc_code_real_type |
f0b37b4a | 883 | reloc (size, pcrel, other) |
49864cfa KR |
884 | int size; |
885 | int pcrel; | |
f0b37b4a | 886 | bfd_reloc_code_real_type other; |
49864cfa | 887 | { |
f0b37b4a KR |
888 | if (other != NO_RELOC) return other; |
889 | ||
49864cfa | 890 | if (pcrel) |
0351b70c ILT |
891 | { |
892 | switch (size) | |
893 | { | |
894 | case 1: return BFD_RELOC_8_PCREL; | |
895 | case 2: return BFD_RELOC_16_PCREL; | |
896 | case 4: return BFD_RELOC_32_PCREL; | |
897 | } | |
898 | as_bad (_("Can not do %d byte pc-relative relocation"), size); | |
899 | } | |
48401fcf | 900 | else |
0351b70c ILT |
901 | { |
902 | switch (size) | |
903 | { | |
904 | case 1: return BFD_RELOC_8; | |
905 | case 2: return BFD_RELOC_16; | |
906 | case 4: return BFD_RELOC_32; | |
907 | } | |
908 | as_bad (_("Can not do %d byte relocation"), size); | |
909 | } | |
48401fcf | 910 | |
ad660eb1 | 911 | return BFD_RELOC_NONE; |
49864cfa | 912 | } |
49864cfa | 913 | |
f0b37b4a KR |
914 | /* |
915 | * Here we decide which fixups can be adjusted to make them relative to | |
916 | * the beginning of the section instead of the symbol. Basically we need | |
917 | * to make sure that the dynamic relocations are done correctly, so in | |
918 | * some cases we force the original symbol to be used. | |
919 | */ | |
0877841d | 920 | int |
f0b37b4a KR |
921 | tc_i386_fix_adjustable(fixP) |
922 | fixS * fixP; | |
923 | { | |
76fb6d2f | 924 | #ifdef OBJ_ELF |
c54c7aac | 925 | /* Prevent all adjustments to global symbols. */ |
0877841d | 926 | if (S_IS_EXTERN (fixP->fx_addsy)) |
c54c7aac | 927 | return 0; |
0b476c53 ILT |
928 | if (S_IS_WEAK (fixP->fx_addsy)) |
929 | return 0; | |
a1624e3f | 930 | #endif |
c54c7aac | 931 | /* adjust_reloc_syms doesn't know about the GOT */ |
0877841d ILT |
932 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
933 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
a1624e3f RH |
934 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
935 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
936 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c54c7aac | 937 | return 0; |
c54c7aac | 938 | return 1; |
f0b37b4a | 939 | } |
454b0ccd ILT |
940 | #else |
941 | #define reloc(SIZE,PCREL,OTHER) 0 | |
0351b70c | 942 | #define BFD_RELOC_16 0 |
454b0ccd | 943 | #define BFD_RELOC_32 0 |
0351b70c | 944 | #define BFD_RELOC_16_PCREL 0 |
454b0ccd ILT |
945 | #define BFD_RELOC_32_PCREL 0 |
946 | #define BFD_RELOC_386_PLT32 0 | |
947 | #define BFD_RELOC_386_GOT32 0 | |
948 | #define BFD_RELOC_386_GOTOFF 0 | |
949 | #endif | |
f0b37b4a | 950 | |
e715a027 RH |
951 | int |
952 | intel_float_operand (mnemonic) | |
953 | char *mnemonic; | |
954 | { | |
955 | if (mnemonic[0] == 'f' && mnemonic[1] =='i') | |
956 | return 0; | |
957 | ||
958 | if (mnemonic[0] == 'f') | |
959 | return 1; | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
49864cfa | 964 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3c8df4ba | 965 | machine dependent instruction. This function is supposed to emit |
49864cfa | 966 | the frags/bytes it assembles to. */ |
f0b37b4a | 967 | |
355afbcd KR |
968 | void |
969 | md_assemble (line) | |
970 | char *line; | |
fecd2382 | 971 | { |
227b6b55 ILT |
972 | /* Points to template once we've found it. */ |
973 | const template *t; | |
355afbcd | 974 | |
ad660eb1 ILT |
975 | /* Count the size of the instruction generated. */ |
976 | int insn_size = 0; | |
977 | ||
f0b37b4a KR |
978 | int j; |
979 | ||
e715a027 RH |
980 | char mnemonic[MAX_MNEM_SIZE]; |
981 | ||
355afbcd KR |
982 | /* Initialize globals. */ |
983 | memset (&i, '\0', sizeof (i)); | |
f0b37b4a KR |
984 | for (j = 0; j < MAX_OPERANDS; j++) |
985 | i.disp_reloc[j] = NO_RELOC; | |
355afbcd KR |
986 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
987 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
988 | save_stack_p = save_stack; /* reset stack pointer */ | |
989 | ||
668f52e0 | 990 | /* First parse an instruction mnemonic & call i386_operand for the operands. |
49864cfa | 991 | We assume that the scrubber has arranged it so that line[0] is the valid |
668f52e0 | 992 | start of a (possibly prefixed) mnemonic. */ |
355afbcd | 993 | { |
f3d817d8 | 994 | char *l = line; |
0351b70c | 995 | char *token_start = l; |
668f52e0 | 996 | char *mnem_p; |
355afbcd | 997 | |
4498e3d6 ILT |
998 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
999 | const char *expecting_string_instruction = NULL; | |
355afbcd | 1000 | |
0351b70c | 1001 | while (1) |
355afbcd | 1002 | { |
668f52e0 ILT |
1003 | mnem_p = mnemonic; |
1004 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
355afbcd | 1005 | { |
668f52e0 ILT |
1006 | mnem_p++; |
1007 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
0351b70c ILT |
1008 | { |
1009 | as_bad (_("no such 386 instruction: `%s'"), token_start); | |
1010 | return; | |
1011 | } | |
1012 | l++; | |
355afbcd | 1013 | } |
0351b70c ILT |
1014 | if (!is_space_char (*l) |
1015 | && *l != END_OF_INSN | |
1016 | && *l != PREFIX_SEPARATOR) | |
355afbcd | 1017 | { |
668f52e0 | 1018 | as_bad (_("invalid character %s in mnemonic"), |
0351b70c ILT |
1019 | output_invalid (*l)); |
1020 | return; | |
355afbcd | 1021 | } |
0351b70c | 1022 | if (token_start == l) |
f3d817d8 | 1023 | { |
0351b70c ILT |
1024 | if (*l == PREFIX_SEPARATOR) |
1025 | as_bad (_("expecting prefix; got nothing")); | |
1026 | else | |
668f52e0 | 1027 | as_bad (_("expecting mnemonic; got nothing")); |
0351b70c ILT |
1028 | return; |
1029 | } | |
355afbcd | 1030 | |
0351b70c | 1031 | /* Look up instruction (or prefix) via hash table. */ |
668f52e0 | 1032 | current_templates = hash_find (op_hash, mnemonic); |
0351b70c ILT |
1033 | |
1034 | if (*l != END_OF_INSN | |
61c49d66 | 1035 | && (! is_space_char (*l) || l[1] != END_OF_INSN) |
0351b70c | 1036 | && current_templates |
284f02bb | 1037 | && (current_templates->start->opcode_modifier & IsPrefix)) |
0351b70c | 1038 | { |
284f02bb ILT |
1039 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
1040 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1041 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1042 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
1043 | ^ flag_16bit_code)) | |
1044 | { | |
1045 | as_bad (_("redundant %s prefix"), | |
1046 | current_templates->start->name); | |
1047 | return; | |
1048 | } | |
0351b70c ILT |
1049 | /* Add prefix, checking for repeated prefixes. */ |
1050 | switch (add_prefix (current_templates->start->base_opcode)) | |
4498e3d6 | 1051 | { |
73a8be66 ILT |
1052 | case 0: |
1053 | return; | |
aa56747a | 1054 | case 2: |
0351b70c ILT |
1055 | expecting_string_instruction = |
1056 | current_templates->start->name; | |
aa56747a | 1057 | break; |
355afbcd | 1058 | } |
4498e3d6 | 1059 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ |
355afbcd KR |
1060 | token_start = ++l; |
1061 | } | |
0351b70c ILT |
1062 | else |
1063 | break; | |
355afbcd KR |
1064 | } |
1065 | ||
355afbcd KR |
1066 | if (!current_templates) |
1067 | { | |
0351b70c | 1068 | /* See if we can get a match by trimming off a suffix. */ |
668f52e0 | 1069 | switch (mnem_p[-1]) |
355afbcd | 1070 | { |
668f52e0 ILT |
1071 | case DWORD_MNEM_SUFFIX: |
1072 | case WORD_MNEM_SUFFIX: | |
1073 | case BYTE_MNEM_SUFFIX: | |
1074 | case SHORT_MNEM_SUFFIX: | |
1075 | #if LONG_MNEM_SUFFIX != DWORD_MNEM_SUFFIX | |
1076 | case LONG_MNEM_SUFFIX: | |
73a8be66 | 1077 | #endif |
668f52e0 ILT |
1078 | i.suffix = mnem_p[-1]; |
1079 | mnem_p[-1] = '\0'; | |
1080 | current_templates = hash_find (op_hash, mnemonic); | |
e715a027 RH |
1081 | break; |
1082 | ||
1083 | /* Intel Syntax */ | |
1084 | case INTEL_DWORD_MNEM_SUFFIX: | |
1085 | if (intel_syntax) | |
1086 | { | |
1087 | i.suffix = mnem_p[-1]; | |
1088 | mnem_p[-1] = '\0'; | |
1089 | current_templates = hash_find (op_hash, mnemonic); | |
1090 | break; | |
1091 | } | |
355afbcd KR |
1092 | } |
1093 | if (!current_templates) | |
1094 | { | |
48401fcf | 1095 | as_bad (_("no such 386 instruction: `%s'"), token_start); |
355afbcd KR |
1096 | return; |
1097 | } | |
1098 | } | |
355afbcd KR |
1099 | |
1100 | /* check for rep/repne without a string instruction */ | |
73a8be66 ILT |
1101 | if (expecting_string_instruction |
1102 | && !(current_templates->start->opcode_modifier & IsString)) | |
355afbcd | 1103 | { |
48401fcf | 1104 | as_bad (_("expecting string instruction after `%s'"), |
4498e3d6 | 1105 | expecting_string_instruction); |
355afbcd KR |
1106 | return; |
1107 | } | |
1108 | ||
1109 | /* There may be operands to parse. */ | |
4498e3d6 | 1110 | if (*l != END_OF_INSN) |
355afbcd KR |
1111 | { |
1112 | /* parse operands */ | |
0351b70c ILT |
1113 | |
1114 | /* 1 if operand is pending after ','. */ | |
1115 | unsigned int expecting_operand = 0; | |
1116 | ||
1117 | /* Non-zero if operand parens not balanced. */ | |
1118 | unsigned int paren_not_balanced; | |
1119 | ||
355afbcd KR |
1120 | do |
1121 | { | |
1122 | /* skip optional white space before operand */ | |
4edc93e9 ILT |
1123 | if (is_space_char (*l)) |
1124 | ++l; | |
1125 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
355afbcd | 1126 | { |
4edc93e9 ILT |
1127 | as_bad (_("invalid character %s before operand %d"), |
1128 | output_invalid (*l), | |
1129 | i.operands + 1); | |
1130 | return; | |
355afbcd KR |
1131 | } |
1132 | token_start = l; /* after white space */ | |
0b476c53 ILT |
1133 | paren_not_balanced = 0; |
1134 | while (paren_not_balanced || *l != ',') | |
355afbcd KR |
1135 | { |
1136 | if (*l == END_OF_INSN) | |
1137 | { | |
0b476c53 | 1138 | if (paren_not_balanced) |
355afbcd | 1139 | { |
e715a027 RH |
1140 | if (!intel_syntax) |
1141 | as_bad (_("unbalanced parenthesis in operand %d."), | |
1142 | i.operands + 1); | |
1143 | else | |
1144 | as_bad (_("unbalanced brackets in operand %d."), | |
1145 | i.operands + 1); | |
355afbcd KR |
1146 | return; |
1147 | } | |
1148 | else | |
1149 | break; /* we are done */ | |
1150 | } | |
ad660eb1 | 1151 | else if (!is_operand_char (*l) && !is_space_char (*l)) |
355afbcd | 1152 | { |
48401fcf | 1153 | as_bad (_("invalid character %s in operand %d"), |
aa56747a ILT |
1154 | output_invalid (*l), |
1155 | i.operands + 1); | |
355afbcd KR |
1156 | return; |
1157 | } | |
e715a027 RH |
1158 | if (!intel_syntax) |
1159 | { | |
1160 | if (*l == '(') | |
1161 | ++paren_not_balanced; | |
1162 | if (*l == ')') | |
1163 | --paren_not_balanced; | |
1164 | } | |
1165 | else | |
1166 | { | |
1167 | if (*l == '[') | |
1168 | ++paren_not_balanced; | |
1169 | if (*l == ']') | |
1170 | --paren_not_balanced; | |
1171 | } | |
355afbcd KR |
1172 | l++; |
1173 | } | |
1174 | if (l != token_start) | |
1175 | { /* yes, we've read in another operand */ | |
1176 | unsigned int operand_ok; | |
1177 | this_operand = i.operands++; | |
1178 | if (i.operands > MAX_OPERANDS) | |
1179 | { | |
48401fcf | 1180 | as_bad (_("spurious operands; (%d operands/instruction max)"), |
355afbcd KR |
1181 | MAX_OPERANDS); |
1182 | return; | |
1183 | } | |
1184 | /* now parse operand adding info to 'i' as we go along */ | |
1185 | END_STRING_AND_SAVE (l); | |
e715a027 RH |
1186 | |
1187 | if (intel_syntax) | |
1188 | operand_ok = i386_intel_operand (token_start, intel_float_operand (mnemonic)); | |
1189 | else | |
1190 | operand_ok = i386_operand (token_start); | |
1191 | ||
355afbcd KR |
1192 | RESTORE_END_STRING (l); /* restore old contents */ |
1193 | if (!operand_ok) | |
1194 | return; | |
1195 | } | |
1196 | else | |
1197 | { | |
1198 | if (expecting_operand) | |
1199 | { | |
1200 | expecting_operand_after_comma: | |
48401fcf | 1201 | as_bad (_("expecting operand after ','; got nothing")); |
355afbcd KR |
1202 | return; |
1203 | } | |
1204 | if (*l == ',') | |
1205 | { | |
48401fcf | 1206 | as_bad (_("expecting operand before ','; got nothing")); |
355afbcd KR |
1207 | return; |
1208 | } | |
1209 | } | |
1210 | ||
1211 | /* now *l must be either ',' or END_OF_INSN */ | |
1212 | if (*l == ',') | |
1213 | { | |
1214 | if (*++l == END_OF_INSN) | |
1215 | { /* just skip it, if it's \n complain */ | |
1216 | goto expecting_operand_after_comma; | |
1217 | } | |
1218 | expecting_operand = 1; | |
1219 | } | |
1220 | } | |
1221 | while (*l != END_OF_INSN); /* until we get end of insn */ | |
1222 | } | |
1223 | } | |
1224 | ||
668f52e0 | 1225 | /* Now we've parsed the mnemonic into a set of templates, and have the |
c5dd66a1 KR |
1226 | operands at hand. |
1227 | ||
1228 | Next, we find a template that matches the given insn, | |
1229 | making sure the overlap of the given operands types is consistent | |
1230 | with the template operand types. */ | |
355afbcd | 1231 | |
73a8be66 ILT |
1232 | #define MATCH(overlap, given, template) \ |
1233 | ((overlap) \ | |
0351b70c ILT |
1234 | && ((given) & BaseIndex) == ((overlap) & BaseIndex) \ |
1235 | && ((given) & JumpAbsolute) == ((template) & JumpAbsolute)) | |
73a8be66 ILT |
1236 | |
1237 | /* If given types r0 and r1 are registers they must be of the same type | |
1238 | unless the expected operand type register overlap is null. | |
1239 | Note that Acc in a template matches every size of reg. */ | |
1240 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1241 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1242 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1243 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1244 | ||
355afbcd KR |
1245 | { |
1246 | register unsigned int overlap0, overlap1; | |
1247 | expressionS *exp; | |
1248 | unsigned int overlap2; | |
1249 | unsigned int found_reverse_match; | |
73a8be66 ILT |
1250 | int suffix_check; |
1251 | ||
e715a027 RH |
1252 | /* All intel opcodes have reversed operands except for BOUND and ENTER */ |
1253 | if (intel_syntax | |
1254 | && (strcmp (mnemonic, "enter") != 0) | |
1255 | && (strcmp (mnemonic, "bound") != 0) | |
1256 | && (strncmp (mnemonic, "fsub", 4) !=0) | |
1257 | && (strncmp (mnemonic, "fdiv", 4) !=0)) | |
1258 | { | |
1259 | const reg_entry *temp_reg; | |
1260 | expressionS *temp_disp; | |
1261 | expressionS *temp_imm; | |
1262 | unsigned int temp_type; | |
1263 | int xchg1, xchg2; | |
1264 | ||
1265 | if (i.operands == 2) | |
1266 | { | |
1267 | xchg1 = 0; | |
1268 | xchg2 = 1; | |
1269 | } | |
1270 | else if (i.operands == 3) | |
1271 | { | |
1272 | xchg1 = 0; | |
1273 | xchg2 = 2; | |
1274 | } | |
1275 | ||
1276 | if (i.operands > 1) | |
1277 | { | |
1278 | temp_type = i.types[xchg2]; | |
1279 | if (temp_type & (Reg | FloatReg)) | |
1280 | temp_reg = i.regs[xchg2]; | |
1281 | else if (temp_type & Imm) | |
1282 | temp_imm = i.imms[xchg2]; | |
1283 | else if (temp_type & Disp) | |
1284 | temp_disp = i.disps[xchg2]; | |
1285 | ||
1286 | i.types[xchg2] = i.types[xchg1]; | |
1287 | ||
1288 | if (i.types[xchg1] & (Reg | FloatReg)) | |
1289 | { | |
1290 | i.regs[xchg2] = i.regs[xchg1]; | |
1291 | i.regs[xchg1] = NULL; | |
1292 | } | |
1293 | else if (i.types[xchg2] & Imm) | |
1294 | { | |
1295 | i.imms[xchg2] = i.imms[xchg1]; | |
1296 | i.imms[xchg1] = NULL; | |
1297 | } | |
1298 | else if (i.types[xchg2] & Disp) | |
1299 | { | |
1300 | i.disps[xchg2] = i.disps[xchg1]; | |
1301 | i.disps[xchg1] = NULL; | |
1302 | } | |
1303 | ||
1304 | if (temp_type & (Reg | FloatReg)) | |
1305 | { | |
1306 | i.regs[xchg1] = temp_reg; | |
1307 | if (! (i.types[xchg1] & (Reg | FloatReg))) | |
1308 | i.regs[xchg2] = NULL; | |
1309 | } | |
1310 | else if (temp_type & Imm) | |
1311 | { | |
1312 | i.imms[xchg1] = temp_imm; | |
1313 | if (! (i.types[xchg1] & Imm)) | |
1314 | i.imms[xchg2] = NULL; | |
1315 | } | |
1316 | else if (temp_type & Disp) | |
1317 | { | |
1318 | i.disps[xchg1] = temp_disp; | |
1319 | if (! (i.types[xchg1] & Disp)) | |
1320 | i.disps[xchg2] = NULL; | |
1321 | } | |
1322 | ||
1323 | i.types[xchg1] = temp_type; | |
1324 | } | |
1325 | if (!strcmp(mnemonic,"jmp") | |
1326 | || !strcmp (mnemonic, "call")) | |
1327 | if ((i.types[0] & Reg) || i.types[0] & BaseIndex) | |
1328 | i.types[0] |= JumpAbsolute; | |
1329 | ||
1330 | } | |
73a8be66 ILT |
1331 | overlap0 = 0; |
1332 | overlap1 = 0; | |
1333 | overlap2 = 0; | |
1334 | found_reverse_match = 0; | |
668f52e0 | 1335 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX |
73a8be66 | 1336 | ? No_bSuf |
668f52e0 | 1337 | : (i.suffix == WORD_MNEM_SUFFIX |
73a8be66 | 1338 | ? No_wSuf |
668f52e0 | 1339 | : (i.suffix == SHORT_MNEM_SUFFIX |
73a8be66 | 1340 | ? No_sSuf |
e715a027 RH |
1341 | : (i.suffix == LONG_MNEM_SUFFIX |
1342 | ? No_lSuf | |
1343 | : (i.suffix == INTEL_DWORD_MNEM_SUFFIX | |
1344 | ? No_dSuf | |
1345 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); | |
355afbcd | 1346 | |
355afbcd KR |
1347 | for (t = current_templates->start; |
1348 | t < current_templates->end; | |
1349 | t++) | |
1350 | { | |
e715a027 RH |
1351 | /* Must have right number of operands. */ |
1352 | if (i.operands != t->operands) | |
355afbcd | 1353 | continue; |
e715a027 RH |
1354 | |
1355 | /* For some opcodes, don't check the suffix */ | |
1356 | if (intel_syntax) | |
1357 | { | |
1358 | if (strcmp (t->name, "fnstcw") | |
1359 | && strcmp (t->name, "fldcw") | |
1360 | && (t->opcode_modifier & suffix_check)) | |
1361 | continue; | |
1362 | } | |
1363 | /* Must not have disallowed suffix. */ | |
1364 | else if ((t->opcode_modifier & suffix_check)) | |
1365 | continue; | |
1366 | ||
355afbcd KR |
1367 | else if (!t->operands) |
1368 | break; /* 0 operands always matches */ | |
1369 | ||
1370 | overlap0 = i.types[0] & t->operand_types[0]; | |
1371 | switch (t->operands) | |
1372 | { | |
1373 | case 1: | |
73a8be66 | 1374 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) |
355afbcd KR |
1375 | continue; |
1376 | break; | |
1377 | case 2: | |
1378 | case 3: | |
1379 | overlap1 = i.types[1] & t->operand_types[1]; | |
73a8be66 ILT |
1380 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) |
1381 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1382 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1383 | t->operand_types[0], | |
1384 | overlap1, i.types[1], | |
1385 | t->operand_types[1])) | |
542e1629 | 1386 | { |
355afbcd KR |
1387 | |
1388 | /* check if other direction is valid ... */ | |
73a8be66 | 1389 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
355afbcd KR |
1390 | continue; |
1391 | ||
1392 | /* try reversing direction of operands */ | |
1393 | overlap0 = i.types[0] & t->operand_types[1]; | |
1394 | overlap1 = i.types[1] & t->operand_types[0]; | |
73a8be66 ILT |
1395 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) |
1396 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1397 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1398 | t->operand_types[1], | |
1399 | overlap1, i.types[1], | |
1400 | t->operand_types[0])) | |
355afbcd KR |
1401 | { |
1402 | /* does not match either direction */ | |
1403 | continue; | |
1404 | } | |
73a8be66 ILT |
1405 | /* found_reverse_match holds which of D or FloatDR |
1406 | we've found. */ | |
1407 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
1408 | break; | |
1409 | } | |
1410 | /* found a forward 2 operand match here */ | |
355afbcd KR |
1411 | if (t->operands == 3) |
1412 | { | |
73a8be66 ILT |
1413 | /* Here we make use of the fact that there are no |
1414 | reverse match 3 operand instructions, and all 3 | |
1415 | operand instructions only need to be checked for | |
1416 | register consistency between operands 2 and 3. */ | |
355afbcd | 1417 | overlap2 = i.types[2] & t->operand_types[2]; |
73a8be66 ILT |
1418 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) |
1419 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1420 | t->operand_types[1], | |
1421 | overlap2, i.types[2], | |
e715a027 RH |
1422 | t->operand_types[2])) |
1423 | ||
1424 | continue; | |
355afbcd KR |
1425 | } |
1426 | /* found either forward/reverse 2 or 3 operand match here: | |
c5dd66a1 | 1427 | slip through to break */ |
355afbcd KR |
1428 | } |
1429 | break; /* we've found a match; break out of loop */ | |
1430 | } /* for (t = ... */ | |
1431 | if (t == current_templates->end) | |
1432 | { /* we found no match */ | |
48401fcf | 1433 | as_bad (_("suffix or operands invalid for `%s'"), |
4498e3d6 | 1434 | current_templates->start->name); |
355afbcd KR |
1435 | return; |
1436 | } | |
1437 | ||
61c49d66 ILT |
1438 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) == (IsPrefix|IgnoreSize)) |
1439 | { | |
1440 | /* Warn them that a data or address size prefix doesn't affect | |
1441 | assembly of the next line of code. */ | |
1442 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1443 | } | |
1444 | ||
4498e3d6 | 1445 | /* Copy the template we found. */ |
f3d817d8 | 1446 | i.tm = *t; |
227b6b55 ILT |
1447 | if (found_reverse_match) |
1448 | { | |
1449 | i.tm.operand_types[0] = t->operand_types[1]; | |
1450 | i.tm.operand_types[1] = t->operand_types[0]; | |
1451 | } | |
355afbcd | 1452 | |
e715a027 | 1453 | |
73a8be66 ILT |
1454 | if (i.tm.opcode_modifier & FWait) |
1455 | if (! add_prefix (FWAIT_OPCODE)) | |
1456 | return; | |
1457 | ||
4498e3d6 ILT |
1458 | /* Check string instruction segment overrides */ |
1459 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1460 | { | |
73a8be66 | 1461 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; |
8081c2be | 1462 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) |
4498e3d6 | 1463 | { |
73a8be66 | 1464 | if (i.seg[0] != NULL && i.seg[0] != &es) |
4498e3d6 | 1465 | { |
aa56747a ILT |
1466 | as_bad (_("`%s' operand %d must use `%%es' segment"), |
1467 | i.tm.name, | |
1468 | mem_op + 1); | |
4498e3d6 ILT |
1469 | return; |
1470 | } | |
1471 | /* There's only ever one segment override allowed per instruction. | |
1472 | This instruction possibly has a legal segment override on the | |
1473 | second operand, so copy the segment to where non-string | |
1474 | instructions store it, allowing common code. */ | |
1475 | i.seg[0] = i.seg[1]; | |
1476 | } | |
8081c2be | 1477 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) |
4498e3d6 | 1478 | { |
73a8be66 | 1479 | if (i.seg[1] != NULL && i.seg[1] != &es) |
4498e3d6 | 1480 | { |
aa56747a ILT |
1481 | as_bad (_("`%s' operand %d must use `%%es' segment"), |
1482 | i.tm.name, | |
1483 | mem_op + 2); | |
4498e3d6 ILT |
1484 | return; |
1485 | } | |
1486 | } | |
1487 | } | |
1488 | ||
668f52e0 ILT |
1489 | /* If matched instruction specifies an explicit instruction mnemonic |
1490 | suffix, use it. */ | |
284f02bb | 1491 | if (i.tm.opcode_modifier & (Size16 | Size32)) |
c54c7aac | 1492 | { |
284f02bb | 1493 | if (i.tm.opcode_modifier & Size16) |
668f52e0 | 1494 | i.suffix = WORD_MNEM_SUFFIX; |
c54c7aac | 1495 | else |
668f52e0 | 1496 | i.suffix = DWORD_MNEM_SUFFIX; |
c54c7aac | 1497 | } |
73a8be66 | 1498 | else if (i.reg_operands) |
355afbcd | 1499 | { |
668f52e0 ILT |
1500 | /* If there's no instruction mnemonic suffix we try to invent one |
1501 | based on register operands. */ | |
73a8be66 | 1502 | if (!i.suffix) |
3ea36b53 | 1503 | { |
73a8be66 ILT |
1504 | /* We take i.suffix from the last register operand specified, |
1505 | Destination register type is more significant than source | |
1506 | register type. */ | |
1507 | int op; | |
1508 | for (op = i.operands; --op >= 0; ) | |
1509 | if (i.types[op] & Reg) | |
1510 | { | |
668f52e0 ILT |
1511 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : |
1512 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
1513 | DWORD_MNEM_SUFFIX); | |
73a8be66 ILT |
1514 | break; |
1515 | } | |
1516 | } | |
668f52e0 | 1517 | else if (i.suffix == BYTE_MNEM_SUFFIX) |
73a8be66 ILT |
1518 | { |
1519 | int op; | |
1520 | for (op = i.operands; --op >= 0; ) | |
1521 | { | |
1522 | /* If this is an eight bit register, it's OK. If it's | |
1523 | the 16 or 32 bit version of an eight bit register, | |
1524 | we will just use the low portion, and that's OK too. */ | |
1525 | if (i.types[op] & Reg8) | |
1526 | continue; | |
e715a027 RH |
1527 | |
1528 | /* movzx and movsx should not generate this warning. */ | |
1529 | if (intel_syntax | |
1530 | && (i.tm.base_opcode == 0xfb7 | |
1531 | || i.tm.base_opcode == 0xfb6 | |
1532 | || i.tm.base_opcode == 0xfbe | |
1533 | || i.tm.base_opcode == 0xfbf)) | |
1534 | continue; | |
1535 | ||
73a8be66 ILT |
1536 | if ((i.types[op] & WordReg) && i.regs[op]->reg_num < 4 |
1537 | #if 0 | |
1538 | /* Check that the template allows eight bit regs | |
1539 | This kills insns such as `orb $1,%edx', which | |
1540 | maybe should be allowed. */ | |
1541 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1542 | #endif | |
1543 | ) | |
1544 | { | |
1545 | #if REGISTER_WARNINGS | |
1546 | if ((i.tm.operand_types[op] & InOutPortReg) == 0) | |
1547 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
1548 | (i.regs[op] - (i.types[op] & Reg16 ? 8 : 16))->reg_name, | |
1549 | i.regs[op]->reg_name, | |
1550 | i.suffix); | |
1551 | #endif | |
1552 | continue; | |
1553 | } | |
1554 | /* Any other register is bad */ | |
1555 | if (i.types[op] & (Reg | RegMMX | Control | Debug | Test | |
1556 | | FloatReg | FloatAcc | SReg2 | SReg3)) | |
1557 | { | |
1558 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
1559 | i.regs[op]->reg_name, | |
1560 | i.tm.name, | |
1561 | i.suffix); | |
1562 | return; | |
1563 | } | |
1564 | } | |
3ea36b53 | 1565 | } |
668f52e0 | 1566 | else if (i.suffix == DWORD_MNEM_SUFFIX) |
73a8be66 ILT |
1567 | { |
1568 | int op; | |
1569 | for (op = i.operands; --op >= 0; ) | |
1570 | /* Reject eight bit registers, except where the template | |
1571 | requires them. (eg. movzb) */ | |
1572 | if ((i.types[op] & Reg8) != 0 | |
1573 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1574 | { | |
1575 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
1576 | i.regs[op]->reg_name, | |
1577 | i.tm.name, | |
1578 | i.suffix); | |
1579 | return; | |
1580 | } | |
1581 | #if REGISTER_WARNINGS | |
1582 | /* Warn if the e prefix on a general reg is missing. */ | |
1583 | else if ((i.types[op] & Reg16) != 0 | |
1584 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
1585 | { | |
1586 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
1587 | (i.regs[op] + 8)->reg_name, | |
1588 | i.regs[op]->reg_name, | |
1589 | i.suffix); | |
1590 | } | |
1591 | #endif | |
1592 | } | |
668f52e0 | 1593 | else if (i.suffix == WORD_MNEM_SUFFIX) |
73a8be66 ILT |
1594 | { |
1595 | int op; | |
1596 | for (op = i.operands; --op >= 0; ) | |
1597 | /* Reject eight bit registers, except where the template | |
1598 | requires them. (eg. movzb) */ | |
1599 | if ((i.types[op] & Reg8) != 0 | |
1600 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1601 | { | |
1602 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
1603 | i.regs[op]->reg_name, | |
1604 | i.tm.name, | |
1605 | i.suffix); | |
1606 | return; | |
1607 | } | |
1608 | #if REGISTER_WARNINGS | |
1609 | /* Warn if the e prefix on a general reg is present. */ | |
1610 | else if ((i.types[op] & Reg32) != 0 | |
1611 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) | |
1612 | { | |
1613 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
1614 | (i.regs[op] - 8)->reg_name, | |
1615 | i.regs[op]->reg_name, | |
1616 | i.suffix); | |
1617 | } | |
1618 | #endif | |
1619 | } | |
1620 | else | |
1621 | abort(); | |
3ea36b53 | 1622 | } |
355afbcd KR |
1623 | |
1624 | /* Make still unresolved immediate matches conform to size of immediate | |
5819d632 | 1625 | given in i.suffix. Note: overlap2 cannot be an immediate! */ |
355afbcd KR |
1626 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) |
1627 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1628 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1629 | { | |
0351b70c ILT |
1630 | if (i.suffix) |
1631 | { | |
668f52e0 ILT |
1632 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1633 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
0351b70c ILT |
1634 | } |
1635 | else if (overlap0 == (Imm16 | Imm32)) | |
1636 | { | |
1637 | overlap0 = | |
1638 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; | |
1639 | } | |
1640 | else | |
355afbcd | 1641 | { |
668f52e0 | 1642 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); |
355afbcd KR |
1643 | return; |
1644 | } | |
355afbcd KR |
1645 | } |
1646 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1647 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1648 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1649 | { | |
0351b70c ILT |
1650 | if (i.suffix) |
1651 | { | |
668f52e0 ILT |
1652 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1653 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
0351b70c ILT |
1654 | } |
1655 | else if (overlap1 == (Imm16 | Imm32)) | |
1656 | { | |
1657 | overlap1 = | |
1658 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; | |
1659 | } | |
1660 | else | |
355afbcd | 1661 | { |
668f52e0 | 1662 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); |
355afbcd KR |
1663 | return; |
1664 | } | |
355afbcd | 1665 | } |
5819d632 | 1666 | assert ((overlap2 & Imm) == 0); |
355afbcd KR |
1667 | |
1668 | i.types[0] = overlap0; | |
355afbcd KR |
1669 | if (overlap0 & ImplicitRegister) |
1670 | i.reg_operands--; | |
0351b70c ILT |
1671 | if (overlap0 & Imm1) |
1672 | i.imm_operands = 0; /* kludge for shift insns */ | |
1673 | ||
1674 | i.types[1] = overlap1; | |
355afbcd KR |
1675 | if (overlap1 & ImplicitRegister) |
1676 | i.reg_operands--; | |
0351b70c ILT |
1677 | |
1678 | i.types[2] = overlap2; | |
355afbcd KR |
1679 | if (overlap2 & ImplicitRegister) |
1680 | i.reg_operands--; | |
355afbcd | 1681 | |
355afbcd | 1682 | /* Finalize opcode. First, we change the opcode based on the operand |
668f52e0 | 1683 | size given by i.suffix: We need not change things for byte insns. */ |
355afbcd | 1684 | |
227b6b55 | 1685 | if (!i.suffix && (i.tm.opcode_modifier & W)) |
355afbcd | 1686 | { |
668f52e0 | 1687 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); |
355afbcd KR |
1688 | return; |
1689 | } | |
1690 | ||
e715a027 RH |
1691 | /* For movzx and movsx, need to check the register type */ |
1692 | if (intel_syntax | |
1693 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) | |
1694 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) | |
1695 | { | |
1696 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
1697 | ||
1698 | if ((i.regs[1]->reg_type & Reg16) != 0) | |
1699 | if (!add_prefix (prefix)) | |
1700 | return; | |
1701 | } | |
1702 | ||
668f52e0 | 1703 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) |
355afbcd | 1704 | { |
668f52e0 | 1705 | /* It's not a byte, select word/dword operation. */ |
227b6b55 | 1706 | if (i.tm.opcode_modifier & W) |
73a8be66 ILT |
1707 | { |
1708 | if (i.tm.opcode_modifier & ShortForm) | |
1709 | i.tm.base_opcode |= 8; | |
1710 | else | |
1711 | i.tm.base_opcode |= 1; | |
1712 | } | |
8c927202 | 1713 | /* Now select between word & dword operations via the operand |
73a8be66 ILT |
1714 | size prefix, except for instructions that will ignore this |
1715 | prefix anyway. */ | |
e715a027 RH |
1716 | if (((intel_syntax && (i.suffix == INTEL_DWORD_MNEM_SUFFIX)) |
1717 | || i.suffix == DWORD_MNEM_SUFFIX | |
668f52e0 | 1718 | || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code |
284f02bb | 1719 | && !(i.tm.opcode_modifier & IgnoreSize)) |
355afbcd | 1720 | { |
73a8be66 | 1721 | unsigned int prefix = DATA_PREFIX_OPCODE; |
aa56747a ILT |
1722 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ |
1723 | prefix = ADDR_PREFIX_OPCODE; | |
1724 | ||
1725 | if (! add_prefix (prefix)) | |
4498e3d6 | 1726 | return; |
355afbcd | 1727 | } |
73a8be66 | 1728 | /* Size floating point instruction. */ |
e715a027 RH |
1729 | if (i.suffix == LONG_MNEM_SUFFIX |
1730 | || (intel_syntax && i.suffix == INTEL_DWORD_MNEM_SUFFIX)) | |
73a8be66 ILT |
1731 | { |
1732 | if (i.tm.opcode_modifier & FloatMF) | |
1733 | i.tm.base_opcode ^= 4; | |
1734 | } | |
e715a027 RH |
1735 | |
1736 | if (intel_syntax && i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
1737 | { | |
1738 | if (i.tm.opcode_modifier & FloatMF) | |
1739 | i.tm.base_opcode ^= 2; | |
1740 | } | |
355afbcd KR |
1741 | } |
1742 | ||
f5003e7d ILT |
1743 | if (i.tm.base_opcode == AMD_3DNOW_OPCODE) |
1744 | { | |
1745 | /* These AMD specific instructions have an opcode suffix which | |
1746 | is coded in the same place as an 8-bit immediate field | |
1747 | would be. Here we fake an 8-bit immediate operand from the | |
668f52e0 | 1748 | opcode suffix stored in tm.extension_opcode. */ |
f5003e7d ILT |
1749 | |
1750 | expressionS *exp; | |
1751 | ||
1752 | assert(i.imm_operands == 0 && i.operands <= 2); | |
1753 | ||
1754 | exp = &im_expressions[i.imm_operands++]; | |
1755 | i.imms[i.operands] = exp; | |
1756 | i.types[i.operands++] = Imm8; | |
1757 | exp->X_op = O_constant; | |
1758 | exp->X_add_number = i.tm.extension_opcode; | |
1759 | i.tm.extension_opcode = None; | |
1760 | } | |
1761 | ||
355afbcd KR |
1762 | /* For insns with operands there are more diddles to do to the opcode. */ |
1763 | if (i.operands) | |
1764 | { | |
c54c7aac KR |
1765 | /* Default segment register this instruction will use |
1766 | for memory accesses. 0 means unknown. | |
1767 | This is only for optimizing out unnecessary segment overrides. */ | |
1768 | const seg_entry *default_seg = 0; | |
1769 | ||
aa56747a ILT |
1770 | /* If we found a reverse match we must alter the opcode |
1771 | direction bit. found_reverse_match holds bits to change | |
1772 | (different for int & float insns). */ | |
355afbcd | 1773 | |
4498e3d6 | 1774 | i.tm.base_opcode ^= found_reverse_match; |
355afbcd | 1775 | |
c5dd66a1 | 1776 | /* The imul $imm, %reg instruction is converted into |
4498e3d6 ILT |
1777 | imul $imm, %reg, %reg, and the clr %reg instruction |
1778 | is converted into xor %reg, %reg. */ | |
1779 | if (i.tm.opcode_modifier & regKludge) | |
2fb44892 | 1780 | { |
4498e3d6 ILT |
1781 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; |
1782 | /* Pretend we saw the extra register operand. */ | |
1783 | i.regs[first_reg_op+1] = i.regs[first_reg_op]; | |
2fb44892 ILT |
1784 | i.reg_operands = 2; |
1785 | } | |
1786 | ||
227b6b55 | 1787 | if (i.tm.opcode_modifier & ShortForm) |
355afbcd KR |
1788 | { |
1789 | /* The register or float register operand is in operand 0 or 1. */ | |
ad660eb1 | 1790 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
355afbcd | 1791 | /* Register goes in low 3 bits of opcode. */ |
227b6b55 | 1792 | i.tm.base_opcode |= i.regs[op]->reg_num; |
73a8be66 ILT |
1793 | if ((i.tm.opcode_modifier & Ugh) != 0) |
1794 | { | |
1795 | /* Warn about some common errors, but press on regardless. | |
1796 | The first case can be generated by gcc (<= 2.8.1). */ | |
1797 | if (i.operands == 2) | |
1798 | { | |
1799 | /* reversed arguments on faddp, fsubp, etc. */ | |
1800 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, | |
1801 | i.regs[1]->reg_name, | |
1802 | i.regs[0]->reg_name); | |
1803 | } | |
1804 | else | |
1805 | { | |
1806 | /* extraneous `l' suffix on fp insn */ | |
1807 | as_warn (_("translating to `%s %%%s'"), i.tm.name, | |
1808 | i.regs[0]->reg_name); | |
1809 | } | |
1810 | } | |
355afbcd | 1811 | } |
227b6b55 | 1812 | else if (i.tm.opcode_modifier & Modrm) |
355afbcd | 1813 | { |
227b6b55 ILT |
1814 | /* The opcode is completed (modulo i.tm.extension_opcode which |
1815 | must be put into the modrm byte). | |
1816 | Now, we make the modrm & index base bytes based on all the | |
1817 | info we've collected. */ | |
355afbcd KR |
1818 | |
1819 | /* i.reg_operands MUST be the number of real register operands; | |
c5dd66a1 | 1820 | implicit registers do not count. */ |
355afbcd KR |
1821 | if (i.reg_operands == 2) |
1822 | { | |
1823 | unsigned int source, dest; | |
454b0ccd ILT |
1824 | source = ((i.types[0] |
1825 | & (Reg | |
1826 | | SReg2 | |
1827 | | SReg3 | |
1828 | | Control | |
1829 | | Debug | |
1830 | | Test | |
1831 | | RegMMX)) | |
1832 | ? 0 : 1); | |
355afbcd | 1833 | dest = source + 1; |
4498e3d6 ILT |
1834 | |
1835 | /* Certain instructions expect the destination to be | |
1836 | in the i.rm.reg field. This is by far the | |
1837 | exceptional case. For these instructions, if the | |
1838 | source operand is a register, we must reverse the | |
1839 | i.rm.reg and i.rm.regmem fields. We accomplish | |
1840 | this by pretending that the two register operands | |
1841 | were given in the reverse order. */ | |
1842 | if (i.tm.opcode_modifier & ReverseRegRegmem) | |
1843 | { | |
73a8be66 | 1844 | const reg_entry *tmp = i.regs[source]; |
4498e3d6 ILT |
1845 | i.regs[source] = i.regs[dest]; |
1846 | i.regs[dest] = tmp; | |
1847 | } | |
1848 | ||
355afbcd | 1849 | i.rm.mode = 3; |
c5dd66a1 | 1850 | /* We must be careful to make sure that all |
454b0ccd | 1851 | segment/control/test/debug/MMX registers go into |
4498e3d6 | 1852 | the i.rm.reg field (despite whether they are |
454b0ccd ILT |
1853 | source or destination operands). */ |
1854 | if (i.regs[dest]->reg_type | |
1855 | & (SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
1856 | { |
1857 | i.rm.reg = i.regs[dest]->reg_num; | |
1858 | i.rm.regmem = i.regs[source]->reg_num; | |
1859 | } | |
1860 | else | |
1861 | { | |
1862 | i.rm.reg = i.regs[source]->reg_num; | |
1863 | i.rm.regmem = i.regs[dest]->reg_num; | |
1864 | } | |
1865 | } | |
1866 | else | |
1867 | { /* if it's not 2 reg operands... */ | |
1868 | if (i.mem_operands) | |
1869 | { | |
1870 | unsigned int fake_zero_displacement = 0; | |
73a8be66 | 1871 | unsigned int op = ((i.types[0] & AnyMem) |
4498e3d6 | 1872 | ? 0 |
73a8be66 | 1873 | : (i.types[1] & AnyMem) ? 1 : 2); |
355afbcd | 1874 | |
ec1e6bb8 | 1875 | default_seg = &ds; |
355afbcd | 1876 | |
ec1e6bb8 | 1877 | if (! i.base_reg) |
355afbcd | 1878 | { |
ec1e6bb8 ILT |
1879 | i.rm.mode = 0; |
1880 | if (! i.disp_operands) | |
1881 | fake_zero_displacement = 1; | |
1882 | if (! i.index_reg) | |
355afbcd | 1883 | { |
ec1e6bb8 | 1884 | /* Operand is just <disp> */ |
0351b70c ILT |
1885 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
1886 | { | |
1887 | i.rm.regmem = NO_BASE_REGISTER_16; | |
1888 | i.types[op] &= ~Disp; | |
1889 | i.types[op] |= Disp16; | |
1890 | } | |
1891 | else | |
1892 | { | |
1893 | i.rm.regmem = NO_BASE_REGISTER; | |
1894 | i.types[op] &= ~Disp; | |
1895 | i.types[op] |= Disp32; | |
1896 | } | |
355afbcd | 1897 | } |
0351b70c | 1898 | else /* ! i.base_reg && i.index_reg */ |
355afbcd | 1899 | { |
0351b70c ILT |
1900 | i.sib.index = i.index_reg->reg_num; |
1901 | i.sib.base = NO_BASE_REGISTER; | |
1902 | i.sib.scale = i.log2_scale_factor; | |
ec1e6bb8 ILT |
1903 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
1904 | i.types[op] &= ~Disp; | |
1905 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
355afbcd KR |
1906 | } |
1907 | } | |
0351b70c ILT |
1908 | else if (i.base_reg->reg_type & Reg16) |
1909 | { | |
1910 | switch (i.base_reg->reg_num) | |
1911 | { | |
1912 | case 3: /* (%bx) */ | |
1913 | if (! i.index_reg) | |
1914 | i.rm.regmem = 7; | |
1915 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
1916 | i.rm.regmem = i.index_reg->reg_num - 6; | |
1917 | break; | |
1918 | case 5: /* (%bp) */ | |
1919 | default_seg = &ss; | |
1920 | if (! i.index_reg) | |
1921 | { | |
1922 | i.rm.regmem = 6; | |
1923 | if ((i.types[op] & Disp) == 0) | |
1924 | { | |
1925 | /* fake (%bp) into 0(%bp) */ | |
1926 | i.types[op] |= Disp8; | |
1927 | fake_zero_displacement = 1; | |
1928 | } | |
1929 | } | |
1930 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
1931 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
1932 | break; | |
1933 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
1934 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
1935 | } | |
1936 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
1937 | } | |
1938 | else /* i.base_reg and 32 bit mode */ | |
355afbcd | 1939 | { |
355afbcd | 1940 | i.rm.regmem = i.base_reg->reg_num; |
0351b70c | 1941 | i.sib.base = i.base_reg->reg_num; |
ec1e6bb8 | 1942 | if (i.base_reg->reg_num == EBP_REG_NUM) |
355afbcd | 1943 | { |
ec1e6bb8 ILT |
1944 | default_seg = &ss; |
1945 | if (i.disp_operands == 0) | |
1946 | { | |
355afbcd | 1947 | fake_zero_displacement = 1; |
ad660eb1 | 1948 | i.types[op] |= Disp8; |
355afbcd KR |
1949 | } |
1950 | } | |
ec1e6bb8 ILT |
1951 | else if (i.base_reg->reg_num == ESP_REG_NUM) |
1952 | { | |
1953 | default_seg = &ss; | |
1954 | } | |
0351b70c | 1955 | i.sib.scale = i.log2_scale_factor; |
ec1e6bb8 ILT |
1956 | if (! i.index_reg) |
1957 | { | |
1958 | /* <disp>(%esp) becomes two byte modrm | |
1959 | with no index register. We've already | |
1960 | stored the code for esp in i.rm.regmem | |
1961 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
1962 | base register besides %esp will not use | |
1963 | the extra modrm byte. */ | |
0351b70c | 1964 | i.sib.index = NO_INDEX_REGISTER; |
ec1e6bb8 ILT |
1965 | #if ! SCALE1_WHEN_NO_INDEX |
1966 | /* Another case where we force the second | |
1967 | modrm byte. */ | |
1968 | if (i.log2_scale_factor) | |
1969 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
1970 | #endif | |
1971 | } | |
1972 | else | |
1973 | { | |
0351b70c | 1974 | i.sib.index = i.index_reg->reg_num; |
ec1e6bb8 ILT |
1975 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
1976 | } | |
1977 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
355afbcd | 1978 | } |
ec1e6bb8 | 1979 | |
355afbcd KR |
1980 | if (fake_zero_displacement) |
1981 | { | |
ad660eb1 | 1982 | /* Fakes a zero displacement assuming that i.types[op] |
c5dd66a1 | 1983 | holds the correct displacement size. */ |
355afbcd | 1984 | exp = &disp_expressions[i.disp_operands++]; |
ad660eb1 | 1985 | i.disps[op] = exp; |
5ac34ac3 | 1986 | exp->X_op = O_constant; |
355afbcd KR |
1987 | exp->X_add_number = 0; |
1988 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 1989 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd | 1990 | } |
355afbcd KR |
1991 | } |
1992 | ||
454b0ccd | 1993 | /* Fill in i.rm.reg or i.rm.regmem field with register |
227b6b55 ILT |
1994 | operand (if any) based on i.tm.extension_opcode. |
1995 | Again, we must be careful to make sure that | |
1996 | segment/control/debug/test/MMX registers are coded | |
1997 | into the i.rm.reg field. */ | |
355afbcd KR |
1998 | if (i.reg_operands) |
1999 | { | |
ad660eb1 | 2000 | unsigned int op = |
454b0ccd ILT |
2001 | ((i.types[0] |
2002 | & (Reg | SReg2 | SReg3 | Control | Debug | |
2003 | | Test | RegMMX)) | |
2004 | ? 0 | |
2005 | : ((i.types[1] | |
2006 | & (Reg | SReg2 | SReg3 | Control | Debug | |
2007 | | Test | RegMMX)) | |
2008 | ? 1 | |
2009 | : 2)); | |
c5dd66a1 KR |
2010 | /* If there is an extension opcode to put here, the |
2011 | register number must be put into the regmem field. */ | |
227b6b55 | 2012 | if (i.tm.extension_opcode != None) |
ad660eb1 | 2013 | i.rm.regmem = i.regs[op]->reg_num; |
355afbcd | 2014 | else |
ad660eb1 | 2015 | i.rm.reg = i.regs[op]->reg_num; |
355afbcd KR |
2016 | |
2017 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
c5dd66a1 | 2018 | we must set it to 3 to indicate this is a register |
4498e3d6 | 2019 | operand in the regmem field. */ |
355afbcd KR |
2020 | if (!i.mem_operands) |
2021 | i.rm.mode = 3; | |
2022 | } | |
2023 | ||
2024 | /* Fill in i.rm.reg field with extension opcode (if any). */ | |
227b6b55 ILT |
2025 | if (i.tm.extension_opcode != None) |
2026 | i.rm.reg = i.tm.extension_opcode; | |
355afbcd | 2027 | } |
c54c7aac | 2028 | } |
73a8be66 | 2029 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) |
4498e3d6 ILT |
2030 | { |
2031 | if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1) | |
2032 | { | |
73a8be66 | 2033 | as_bad (_("you can't `pop %%cs'")); |
4498e3d6 ILT |
2034 | return; |
2035 | } | |
2036 | i.tm.base_opcode |= (i.regs[0]->reg_num << 3); | |
2037 | } | |
73a8be66 | 2038 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) |
4498e3d6 | 2039 | { |
4498e3d6 ILT |
2040 | default_seg = &ds; |
2041 | } | |
2042 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2043 | { | |
2044 | /* For the string instructions that allow a segment override | |
2045 | on one of their operands, the default segment is ds. */ | |
2046 | default_seg = &ds; | |
2047 | } | |
c54c7aac | 2048 | |
c54c7aac KR |
2049 | /* If a segment was explicitly specified, |
2050 | and the specified segment is not the default, | |
2051 | use an opcode prefix to select it. | |
2052 | If we never figured out what the default segment is, | |
2053 | then default_seg will be zero at this point, | |
2054 | and the specified segment prefix will always be used. */ | |
4498e3d6 | 2055 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
c54c7aac | 2056 | { |
aa56747a | 2057 | if (! add_prefix (i.seg[0]->seg_prefix)) |
4498e3d6 | 2058 | return; |
355afbcd KR |
2059 | } |
2060 | } | |
73a8be66 ILT |
2061 | else if ((i.tm.opcode_modifier & Ugh) != 0) |
2062 | { | |
2063 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc */ | |
2064 | as_warn (_("translating to `%sp'"), i.tm.name); | |
2065 | } | |
355afbcd KR |
2066 | } |
2067 | ||
2068 | /* Handle conversion of 'int $3' --> special int3 insn. */ | |
227b6b55 | 2069 | if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3) |
355afbcd | 2070 | { |
227b6b55 | 2071 | i.tm.base_opcode = INT3_OPCODE; |
355afbcd KR |
2072 | i.imm_operands = 0; |
2073 | } | |
2074 | ||
2075 | /* We are ready to output the insn. */ | |
2076 | { | |
2077 | register char *p; | |
2078 | ||
2079 | /* Output jumps. */ | |
227b6b55 | 2080 | if (i.tm.opcode_modifier & Jump) |
355afbcd | 2081 | { |
61c49d66 | 2082 | long n = (long) i.disps[0]->X_add_number; |
0351b70c ILT |
2083 | int prefix = (i.prefix[DATA_PREFIX] != 0); |
2084 | int code16 = 0; | |
2085 | ||
2086 | if (prefix) | |
2087 | { | |
2088 | i.prefixes -= 1; | |
2089 | code16 = CODE16; | |
2090 | } | |
2091 | if (flag_16bit_code) | |
2092 | code16 ^= CODE16; | |
355afbcd | 2093 | |
e715a027 | 2094 | if (!intel_syntax && (i.prefixes != 0)) |
aa56747a | 2095 | as_warn (_("skipping prefixes on this instruction")); |
4498e3d6 | 2096 | |
5ac34ac3 | 2097 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 2098 | { |
355afbcd KR |
2099 | if (fits_in_signed_byte (n)) |
2100 | { | |
ad660eb1 | 2101 | insn_size += 2; |
0351b70c | 2102 | p = frag_more (2); |
227b6b55 | 2103 | p[0] = i.tm.base_opcode; |
355afbcd | 2104 | p[1] = n; |
355afbcd | 2105 | } |
355afbcd | 2106 | else |
0351b70c | 2107 | { |
4498e3d6 | 2108 | /* Use 16-bit jumps only for 16-bit code, |
c54c7aac | 2109 | because text segments are limited to 64K anyway; |
4498e3d6 ILT |
2110 | Use 32-bit jumps for 32-bit code, because they're faster, |
2111 | and a 16-bit jump will clear the top 16 bits of %eip. */ | |
0351b70c ILT |
2112 | int jmp_size = code16 ? 2 : 4; |
2113 | if (code16 && !fits_in_signed_word (n)) | |
c54c7aac | 2114 | { |
48401fcf | 2115 | as_bad (_("16-bit jump out of range")); |
c54c7aac KR |
2116 | return; |
2117 | } | |
2118 | ||
227b6b55 | 2119 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) |
355afbcd KR |
2120 | { /* pace */ |
2121 | /* unconditional jump */ | |
0351b70c ILT |
2122 | insn_size += prefix + 1 + jmp_size; |
2123 | p = frag_more (prefix + 1 + jmp_size); | |
2124 | if (prefix) | |
2125 | *p++ = DATA_PREFIX_OPCODE; | |
2126 | *p++ = (char) 0xe9; | |
2127 | md_number_to_chars (p, (valueT) n, jmp_size); | |
355afbcd KR |
2128 | } |
2129 | else | |
2130 | { | |
2131 | /* conditional jump */ | |
0351b70c ILT |
2132 | insn_size += prefix + 2 + jmp_size; |
2133 | p = frag_more (prefix + 2 + jmp_size); | |
2134 | if (prefix) | |
2135 | *p++ = DATA_PREFIX_OPCODE; | |
2136 | *p++ = TWO_BYTE_OPCODE_ESCAPE; | |
2137 | *p++ = i.tm.base_opcode + 0x10; | |
2138 | md_number_to_chars (p, (valueT) n, jmp_size); | |
355afbcd KR |
2139 | } |
2140 | } | |
49864cfa KR |
2141 | } |
2142 | else | |
2143 | { | |
0351b70c | 2144 | int size = code16 ? 2 : 4; |
c54c7aac | 2145 | |
355afbcd | 2146 | /* It's a symbol; end frag & setup for relax. |
49864cfa KR |
2147 | Make sure there are more than 6 chars left in the current frag; |
2148 | if not we'll have to start a new one. */ | |
0351b70c ILT |
2149 | frag_grow (prefix + 1 + 2 + size); |
2150 | insn_size += 1 + prefix; | |
2151 | p = frag_more (1 + prefix); | |
2152 | if (prefix) | |
2153 | *p++ = DATA_PREFIX_OPCODE; | |
2154 | *p = i.tm.base_opcode; | |
355afbcd | 2155 | frag_var (rs_machine_dependent, |
0351b70c | 2156 | prefix + 2 + size, /* 2 opcode/prefix + displacement */ |
355afbcd KR |
2157 | 1, |
2158 | ((unsigned char) *p == JUMP_PC_RELATIVE | |
0351b70c ILT |
2159 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 |
2160 | : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), | |
355afbcd | 2161 | i.disps[0]->X_add_symbol, |
f59fb6ca | 2162 | (offsetT) n, p); |
355afbcd KR |
2163 | } |
2164 | } | |
227b6b55 | 2165 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) |
355afbcd | 2166 | { |
227b6b55 | 2167 | int size = (i.tm.opcode_modifier & JumpByte) ? 1 : 4; |
61c49d66 | 2168 | long n = (long) i.disps[0]->X_add_number; |
c54c7aac | 2169 | |
aa56747a | 2170 | if (size == 1) /* then this is a loop or jecxz type instruction */ |
c54c7aac | 2171 | { |
aa56747a | 2172 | if (i.prefix[ADDR_PREFIX]) |
c54c7aac | 2173 | { |
0351b70c | 2174 | insn_size += 1; |
aa56747a | 2175 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
0351b70c ILT |
2176 | i.prefixes -= 1; |
2177 | } | |
2178 | } | |
2179 | else | |
2180 | { | |
2181 | int code16 = 0; | |
2182 | ||
2183 | if (i.prefix[DATA_PREFIX]) | |
2184 | { | |
aa56747a | 2185 | insn_size += 1; |
0351b70c | 2186 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); |
73a8be66 | 2187 | i.prefixes -= 1; |
0351b70c | 2188 | code16 = CODE16; |
c54c7aac | 2189 | } |
0351b70c ILT |
2190 | if (flag_16bit_code) |
2191 | code16 ^= CODE16; | |
2192 | ||
2193 | if (code16) | |
2194 | size = 2; | |
c54c7aac KR |
2195 | } |
2196 | ||
e715a027 | 2197 | if (!intel_syntax && (i.prefixes != 0)) |
aa56747a ILT |
2198 | as_warn (_("skipping prefixes on this instruction")); |
2199 | ||
227b6b55 | 2200 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
355afbcd | 2201 | { |
0351b70c ILT |
2202 | insn_size += 1 + size; |
2203 | p = frag_more (1 + size); | |
355afbcd KR |
2204 | } |
2205 | else | |
2206 | { | |
0351b70c ILT |
2207 | insn_size += 2 + size; /* opcode can be at most two bytes */ |
2208 | p = frag_more (2 + size); | |
227b6b55 | 2209 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
355afbcd | 2210 | } |
0351b70c | 2211 | *p++ = i.tm.base_opcode & 0xff; |
355afbcd | 2212 | |
5ac34ac3 | 2213 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 2214 | { |
355afbcd KR |
2215 | if (size == 1 && !fits_in_signed_byte (n)) |
2216 | { | |
61c49d66 | 2217 | as_bad (_("`%s' only takes byte displacement; %ld shortened to %d"), |
73a8be66 | 2218 | i.tm.name, n, *p); |
355afbcd | 2219 | } |
0351b70c ILT |
2220 | else if (size == 2 && !fits_in_signed_word (n)) |
2221 | { | |
2222 | as_bad (_("16-bit jump out of range")); | |
2223 | return; | |
2224 | } | |
2225 | md_number_to_chars (p, (valueT) n, size); | |
49864cfa KR |
2226 | } |
2227 | else | |
2228 | { | |
5ac34ac3 | 2229 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a KR |
2230 | i.disps[0], 1, reloc (size, 1, i.disp_reloc[0])); |
2231 | ||
355afbcd KR |
2232 | } |
2233 | } | |
227b6b55 | 2234 | else if (i.tm.opcode_modifier & JumpInterSegment) |
355afbcd | 2235 | { |
0351b70c ILT |
2236 | int size; |
2237 | int reloc_type; | |
2238 | int prefix = i.prefix[DATA_PREFIX] != 0; | |
2239 | int code16 = 0; | |
4498e3d6 | 2240 | |
0351b70c ILT |
2241 | if (prefix) |
2242 | { | |
2243 | code16 = CODE16; | |
2244 | i.prefixes -= 1; | |
2245 | } | |
c54c7aac | 2246 | if (flag_16bit_code) |
0351b70c ILT |
2247 | code16 ^= CODE16; |
2248 | ||
2249 | size = 4; | |
2250 | reloc_type = BFD_RELOC_32; | |
2251 | if (code16) | |
c54c7aac | 2252 | { |
0351b70c ILT |
2253 | size = 2; |
2254 | reloc_type = BFD_RELOC_16; | |
c54c7aac KR |
2255 | } |
2256 | ||
e715a027 | 2257 | if (!intel_syntax && (i.prefixes != 0)) |
0351b70c ILT |
2258 | as_warn (_("skipping prefixes on this instruction")); |
2259 | ||
2260 | insn_size += prefix + 1 + 2 + size; /* 1 opcode; 2 segment; offset */ | |
2261 | p = frag_more (prefix + 1 + 2 + size); | |
2262 | if (prefix) | |
2263 | *p++ = DATA_PREFIX_OPCODE; | |
2264 | *p++ = i.tm.base_opcode; | |
5ac34ac3 | 2265 | if (i.imms[1]->X_op == O_constant) |
0351b70c | 2266 | { |
61c49d66 ILT |
2267 | long n = (long) i.imms[1]->X_add_number; |
2268 | ||
0351b70c ILT |
2269 | if (size == 2 && !fits_in_unsigned_word (n)) |
2270 | { | |
2271 | as_bad (_("16-bit jump out of range")); | |
2272 | return; | |
2273 | } | |
2274 | md_number_to_chars (p, (valueT) n, size); | |
2275 | } | |
355afbcd | 2276 | else |
0351b70c ILT |
2277 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2278 | i.imms[1], 0, reloc_type); | |
5ac34ac3 | 2279 | if (i.imms[0]->X_op != O_constant) |
0351b70c ILT |
2280 | as_bad (_("can't handle non absolute segment in `%s'"), |
2281 | i.tm.name); | |
2282 | md_number_to_chars (p + size, (valueT) i.imms[0]->X_add_number, 2); | |
355afbcd KR |
2283 | } |
2284 | else | |
2285 | { | |
2286 | /* Output normal instructions here. */ | |
2287 | unsigned char *q; | |
2288 | ||
4498e3d6 | 2289 | /* The prefix bytes. */ |
aa56747a ILT |
2290 | for (q = i.prefix; |
2291 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2292 | q++) | |
355afbcd | 2293 | { |
aa56747a ILT |
2294 | if (*q) |
2295 | { | |
aa56747a | 2296 | insn_size += 1; |
0351b70c | 2297 | p = frag_more (1); |
aa56747a ILT |
2298 | md_number_to_chars (p, (valueT) *q, 1); |
2299 | } | |
355afbcd KR |
2300 | } |
2301 | ||
2302 | /* Now the opcode; be careful about word order here! */ | |
227b6b55 | 2303 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
355afbcd | 2304 | { |
ad660eb1 | 2305 | insn_size += 1; |
0351b70c | 2306 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
355afbcd | 2307 | } |
227b6b55 | 2308 | else if (fits_in_unsigned_word (i.tm.base_opcode)) |
355afbcd | 2309 | { |
ad660eb1 | 2310 | insn_size += 2; |
0351b70c | 2311 | p = frag_more (2); |
355afbcd | 2312 | /* put out high byte first: can't use md_number_to_chars! */ |
227b6b55 ILT |
2313 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
2314 | *p = i.tm.base_opcode & 0xff; | |
355afbcd KR |
2315 | } |
2316 | else | |
2317 | { /* opcode is either 3 or 4 bytes */ | |
227b6b55 | 2318 | if (i.tm.base_opcode & 0xff000000) |
355afbcd | 2319 | { |
ad660eb1 | 2320 | insn_size += 4; |
0351b70c | 2321 | p = frag_more (4); |
227b6b55 | 2322 | *p++ = (i.tm.base_opcode >> 24) & 0xff; |
355afbcd KR |
2323 | } |
2324 | else | |
ad660eb1 | 2325 | { |
ad660eb1 | 2326 | insn_size += 3; |
0351b70c | 2327 | p = frag_more (3); |
ad660eb1 | 2328 | } |
227b6b55 ILT |
2329 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
2330 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2331 | *p = (i.tm.base_opcode) & 0xff; | |
355afbcd KR |
2332 | } |
2333 | ||
0351b70c | 2334 | /* Now the modrm byte and sib byte (if present). */ |
227b6b55 | 2335 | if (i.tm.opcode_modifier & Modrm) |
355afbcd | 2336 | { |
ad660eb1 | 2337 | insn_size += 1; |
0351b70c | 2338 | p = frag_more (1); |
ad660eb1 ILT |
2339 | md_number_to_chars (p, |
2340 | (valueT) (i.rm.regmem << 0 | |
2341 | | i.rm.reg << 3 | |
2342 | | i.rm.mode << 6), | |
2343 | 1); | |
73a8be66 ILT |
2344 | /* If i.rm.regmem == ESP (4) |
2345 | && i.rm.mode != (Register mode) | |
0351b70c | 2346 | && not 16 bit |
73a8be66 | 2347 | ==> need second modrm byte. */ |
ec1e6bb8 | 2348 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING |
0351b70c ILT |
2349 | && i.rm.mode != 3 |
2350 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
355afbcd | 2351 | { |
ad660eb1 | 2352 | insn_size += 1; |
0351b70c ILT |
2353 | p = frag_more (1); |
2354 | md_number_to_chars (p, | |
2355 | (valueT) (i.sib.base << 0 | |
2356 | | i.sib.index << 3 | |
2357 | | i.sib.scale << 6), | |
ad660eb1 | 2358 | 1); |
355afbcd KR |
2359 | } |
2360 | } | |
2361 | ||
2362 | if (i.disp_operands) | |
2363 | { | |
2364 | register unsigned int n; | |
2365 | ||
2366 | for (n = 0; n < i.operands; n++) | |
2367 | { | |
2368 | if (i.disps[n]) | |
2369 | { | |
5ac34ac3 | 2370 | if (i.disps[n]->X_op == O_constant) |
355afbcd | 2371 | { |
73a8be66 | 2372 | if (i.types[n] & Disp8) |
355afbcd | 2373 | { |
ad660eb1 | 2374 | insn_size += 1; |
0351b70c | 2375 | p = frag_more (1); |
ad660eb1 ILT |
2376 | md_number_to_chars (p, |
2377 | (valueT) i.disps[n]->X_add_number, | |
2378 | 1); | |
355afbcd | 2379 | } |
73a8be66 | 2380 | else if (i.types[n] & Disp16) |
355afbcd | 2381 | { |
ad660eb1 | 2382 | insn_size += 2; |
0351b70c | 2383 | p = frag_more (2); |
ad660eb1 ILT |
2384 | md_number_to_chars (p, |
2385 | (valueT) i.disps[n]->X_add_number, | |
2386 | 2); | |
355afbcd KR |
2387 | } |
2388 | else | |
73a8be66 | 2389 | { /* Disp32 */ |
ad660eb1 | 2390 | insn_size += 4; |
0351b70c | 2391 | p = frag_more (4); |
ad660eb1 ILT |
2392 | md_number_to_chars (p, |
2393 | (valueT) i.disps[n]->X_add_number, | |
2394 | 4); | |
355afbcd KR |
2395 | } |
2396 | } | |
0351b70c ILT |
2397 | else if (i.types[n] & Disp32) |
2398 | { | |
ad660eb1 | 2399 | insn_size += 4; |
0351b70c | 2400 | p = frag_more (4); |
5ac34ac3 | 2401 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, |
0351b70c ILT |
2402 | i.disps[n], 0, |
2403 | TC_RELOC (i.disp_reloc[n], BFD_RELOC_32)); | |
2404 | } | |
2405 | else | |
2406 | { /* must be Disp16 */ | |
2407 | insn_size += 2; | |
2408 | p = frag_more (2); | |
2409 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
2410 | i.disps[n], 0, | |
2411 | TC_RELOC (i.disp_reloc[n], BFD_RELOC_16)); | |
355afbcd KR |
2412 | } |
2413 | } | |
2414 | } | |
2415 | } /* end displacement output */ | |
2416 | ||
2417 | /* output immediate */ | |
2418 | if (i.imm_operands) | |
2419 | { | |
2420 | register unsigned int n; | |
2421 | ||
2422 | for (n = 0; n < i.operands; n++) | |
2423 | { | |
2424 | if (i.imms[n]) | |
2425 | { | |
5ac34ac3 | 2426 | if (i.imms[n]->X_op == O_constant) |
355afbcd KR |
2427 | { |
2428 | if (i.types[n] & (Imm8 | Imm8S)) | |
2429 | { | |
ad660eb1 | 2430 | insn_size += 1; |
0351b70c | 2431 | p = frag_more (1); |
ad660eb1 ILT |
2432 | md_number_to_chars (p, |
2433 | (valueT) i.imms[n]->X_add_number, | |
2434 | 1); | |
355afbcd KR |
2435 | } |
2436 | else if (i.types[n] & Imm16) | |
2437 | { | |
ad660eb1 | 2438 | insn_size += 2; |
0351b70c | 2439 | p = frag_more (2); |
ad660eb1 ILT |
2440 | md_number_to_chars (p, |
2441 | (valueT) i.imms[n]->X_add_number, | |
2442 | 2); | |
355afbcd KR |
2443 | } |
2444 | else | |
2445 | { | |
ad660eb1 | 2446 | insn_size += 4; |
0351b70c | 2447 | p = frag_more (4); |
ad660eb1 ILT |
2448 | md_number_to_chars (p, |
2449 | (valueT) i.imms[n]->X_add_number, | |
2450 | 4); | |
355afbcd KR |
2451 | } |
2452 | } | |
2453 | else | |
49864cfa | 2454 | { /* not absolute_section */ |
f0b37b4a KR |
2455 | /* Need a 32-bit fixup (don't support 8bit |
2456 | non-absolute ims). Try to support other | |
2457 | sizes ... */ | |
2458 | int r_type; | |
355afbcd | 2459 | int size; |
f0b37b4a KR |
2460 | int pcrel = 0; |
2461 | ||
355afbcd KR |
2462 | if (i.types[n] & (Imm8 | Imm8S)) |
2463 | size = 1; | |
2464 | else if (i.types[n] & Imm16) | |
2465 | size = 2; | |
2466 | else | |
2467 | size = 4; | |
ad660eb1 | 2468 | insn_size += size; |
0351b70c ILT |
2469 | p = frag_more (size); |
2470 | r_type = reloc (size, 0, i.disp_reloc[0]); | |
f0b37b4a | 2471 | #ifdef BFD_ASSEMBLER |
c54c7aac | 2472 | if (r_type == BFD_RELOC_32 |
f0b37b4a | 2473 | && GOT_symbol |
0877841d ILT |
2474 | && GOT_symbol == i.imms[n]->X_add_symbol |
2475 | && (i.imms[n]->X_op == O_symbol | |
2476 | || (i.imms[n]->X_op == O_add | |
2477 | && (i.imms[n]->X_op_symbol->sy_value.X_op | |
2478 | == O_subtract)))) | |
f0b37b4a KR |
2479 | { |
2480 | r_type = BFD_RELOC_386_GOTPC; | |
2481 | i.imms[n]->X_add_number += 3; | |
2482 | } | |
2483 | #endif | |
5ac34ac3 | 2484 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a | 2485 | i.imms[n], pcrel, r_type); |
355afbcd KR |
2486 | } |
2487 | } | |
2488 | } | |
2489 | } /* end immediate output */ | |
2490 | } | |
2491 | ||
fecd2382 | 2492 | #ifdef DEBUG386 |
ade614d5 | 2493 | if (flag_debug) |
355afbcd KR |
2494 | { |
2495 | pi (line, &i); | |
2496 | } | |
fecd2382 | 2497 | #endif /* DEBUG386 */ |
355afbcd | 2498 | } |
fecd2382 RP |
2499 | } |
2500 | \f | |
e715a027 RH |
2501 | static int i386_is_reg PARAMS ((char *)); |
2502 | ||
2503 | static int | |
2504 | i386_is_reg (reg_string) | |
2505 | char *reg_string; | |
2506 | { | |
2507 | register char *s = reg_string; | |
2508 | register char *p; | |
2509 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; | |
2510 | ||
2511 | if (is_space_char (*s)) | |
2512 | ++s; | |
2513 | ||
2514 | p = reg_name_given; | |
2515 | while ((*p++ = register_chars[(unsigned char) *s++]) != '\0') | |
2516 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
2517 | return 0; | |
2518 | ||
2519 | if (!hash_find (reg_hash, reg_name_given)) | |
2520 | return 0; | |
2521 | else | |
2522 | return 1; | |
2523 | } | |
2524 | ||
2525 | static int i386_immediate PARAMS ((char *)); | |
2526 | ||
2527 | static int | |
2528 | i386_immediate (imm_start) | |
2529 | char *imm_start; | |
2530 | { | |
2531 | char *save_input_line_pointer; | |
2532 | segT exp_seg = 0; | |
2533 | expressionS * exp; | |
2534 | ||
2535 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2536 | { | |
2537 | as_bad (_ ("only 1 or 2 immediate operands are allowed")); | |
2538 | return 0; | |
2539 | } | |
2540 | ||
2541 | exp = &im_expressions[i.imm_operands++]; | |
2542 | i.imms[this_operand] = exp; | |
2543 | ||
2544 | if (is_space_char (*imm_start)) | |
2545 | ++imm_start; | |
2546 | ||
2547 | save_input_line_pointer = input_line_pointer; | |
2548 | input_line_pointer = imm_start; | |
2549 | exp_seg = expression (exp); | |
2550 | ||
2551 | input_line_pointer = save_input_line_pointer; | |
2552 | ||
2553 | if (exp->X_op == O_absent) | |
2554 | { | |
2555 | /* missing or bad expr becomes absolute 0 */ | |
2556 | as_bad (_ ("missing or invalid immediate expression `%s' taken as 0"), | |
2557 | imm_start); | |
2558 | exp->X_op = O_constant; | |
2559 | exp->X_add_number = 0; | |
2560 | exp->X_add_symbol = (symbolS *) 0; | |
2561 | exp->X_op_symbol = (symbolS *) 0; | |
2562 | i.types[this_operand] |= Imm; | |
2563 | } | |
2564 | else if (exp->X_op == O_constant) | |
2565 | { | |
2566 | i.types[this_operand] |= | |
2567 | smallest_imm_type ((long) exp->X_add_number); | |
2568 | ||
2569 | /* If a suffix is given, this operand may be shortended. */ | |
2570 | switch (i.suffix) | |
2571 | { | |
2572 | case WORD_MNEM_SUFFIX: | |
2573 | i.types[this_operand] |= Imm16; | |
2574 | break; | |
2575 | case BYTE_MNEM_SUFFIX: | |
2576 | i.types[this_operand] |= Imm16 | Imm8 | Imm8S; | |
2577 | break; | |
2578 | } | |
2579 | } | |
2580 | #ifdef OBJ_AOUT | |
2581 | else if (exp_seg != text_section | |
2582 | && exp_seg != data_section | |
2583 | && exp_seg != bss_section | |
2584 | && exp_seg != undefined_section | |
2585 | #ifdef BFD_ASSEMBLER | |
2586 | && !bfd_is_com_section (exp_seg) | |
2587 | #endif | |
2588 | ) | |
2589 | { | |
2590 | seg_unimplemented: | |
2591 | as_bad (_ ("Unimplemented segment type %d in operand"), exp_seg); | |
2592 | return 0; | |
2593 | } | |
2594 | #endif | |
2595 | else | |
2596 | { | |
2597 | /* This is an address. The size of the address will be | |
2598 | determined later, depending on destination register, | |
2599 | suffix, or the default for the section. We exclude | |
2600 | Imm8S here so that `push $foo' and other instructions | |
2601 | with an Imm8S form will use Imm16 or Imm32. */ | |
2602 | i.types[this_operand] |= (Imm8 | Imm16 | Imm32); | |
2603 | } | |
2604 | ||
2605 | return 1; | |
2606 | ||
2607 | } | |
2608 | ||
2609 | static int i386_scale PARAMS ((char *)); | |
2610 | ||
2611 | static int | |
2612 | i386_scale (scale) | |
2613 | char *scale; | |
2614 | { | |
2615 | if (!isdigit (*scale)) | |
2616 | goto bad_scale; | |
2617 | ||
2618 | switch (*scale) | |
2619 | { | |
2620 | case '0': | |
2621 | case '1': | |
2622 | i.log2_scale_factor = 0; | |
2623 | break; | |
2624 | case '2': | |
2625 | i.log2_scale_factor = 1; | |
2626 | break; | |
2627 | case '4': | |
2628 | i.log2_scale_factor = 2; | |
2629 | break; | |
2630 | case '8': | |
2631 | i.log2_scale_factor = 3; | |
2632 | break; | |
2633 | default: | |
2634 | bad_scale: | |
2635 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
2636 | scale); | |
2637 | return 0; | |
2638 | } | |
2639 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
2640 | { | |
2641 | as_warn (_("scale factor of %d without an index register"), | |
2642 | 1 << i.log2_scale_factor); | |
2643 | #if SCALE1_WHEN_NO_INDEX | |
2644 | i.log2_scale_factor = 0; | |
2645 | #endif | |
2646 | } | |
2647 | } | |
2648 | ||
2649 | static int i386_displacement PARAMS ((char *, char *)); | |
2650 | ||
2651 | static int | |
2652 | i386_displacement (disp_start, disp_end) | |
2653 | char *disp_start; | |
2654 | char *disp_end; | |
2655 | { | |
2656 | register expressionS *exp; | |
2657 | segT exp_seg = 0; | |
2658 | char *save_input_line_pointer; | |
2659 | int bigdisp = Disp32; | |
2660 | ||
2661 | /* All of the pieces of the displacement expression are handled together. */ | |
2662 | if (intel_syntax && i.disp_operands != 0) | |
2663 | return 1; | |
2664 | ||
2665 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) | |
2666 | bigdisp = Disp16; | |
2667 | i.types[this_operand] |= bigdisp; | |
2668 | ||
2669 | exp = &disp_expressions[i.disp_operands]; | |
2670 | i.disps[this_operand] = exp; | |
2671 | i.disp_reloc[this_operand] = NO_RELOC; | |
2672 | i.disp_operands++; | |
2673 | save_input_line_pointer = input_line_pointer; | |
2674 | input_line_pointer = disp_start; | |
2675 | END_STRING_AND_SAVE (disp_end); | |
2676 | ||
2677 | #ifndef GCC_ASM_O_HACK | |
2678 | #define GCC_ASM_O_HACK 0 | |
2679 | #endif | |
2680 | #if GCC_ASM_O_HACK | |
2681 | END_STRING_AND_SAVE (disp_end + 1); | |
2682 | if ((i.types[this_operand] & BaseIndex) != 0 | |
2683 | && displacement_string_end[-1] == '+') | |
2684 | { | |
2685 | /* This hack is to avoid a warning when using the "o" | |
2686 | constraint within gcc asm statements. | |
2687 | For instance: | |
2688 | ||
2689 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
2690 | __asm__ __volatile__ ( \ | |
2691 | "movw %w2,%0\n\t" \ | |
2692 | "movw %w1,2+%0\n\t" \ | |
2693 | "rorl $16,%1\n\t" \ | |
2694 | "movb %b1,4+%0\n\t" \ | |
2695 | "movb %4,5+%0\n\t" \ | |
2696 | "movb $0,6+%0\n\t" \ | |
2697 | "movb %h1,7+%0\n\t" \ | |
2698 | "rorl $16,%1" \ | |
2699 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
2700 | ||
2701 | This works great except that the output assembler ends | |
2702 | up looking a bit weird if it turns out that there is | |
2703 | no offset. You end up producing code that looks like: | |
2704 | ||
2705 | #APP | |
2706 | movw $235,(%eax) | |
2707 | movw %dx,2+(%eax) | |
2708 | rorl $16,%edx | |
2709 | movb %dl,4+(%eax) | |
2710 | movb $137,5+(%eax) | |
2711 | movb $0,6+(%eax) | |
2712 | movb %dh,7+(%eax) | |
2713 | rorl $16,%edx | |
2714 | #NO_APP | |
2715 | ||
2716 | So here we provide the missing zero. | |
2717 | */ | |
2718 | ||
2719 | *displacement_string_end = '0'; | |
2720 | } | |
2721 | #endif | |
2722 | #ifndef LEX_AT | |
2723 | { | |
2724 | /* | |
2725 | * We can have operands of the form | |
2726 | * <symbol>@GOTOFF+<nnn> | |
2727 | * Take the easy way out here and copy everything | |
2728 | * into a temporary buffer... | |
2729 | */ | |
2730 | register char *cp; | |
2731 | ||
2732 | cp = strchr (input_line_pointer, '@'); | |
2733 | if (cp != NULL) | |
2734 | { | |
2735 | char *tmpbuf; | |
2736 | ||
2737 | if (GOT_symbol == NULL) | |
2738 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2739 | ||
2740 | tmpbuf = (char *) alloca ((cp - input_line_pointer) + 20); | |
2741 | ||
2742 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2743 | { | |
2744 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2745 | *cp = '\0'; | |
2746 | strcpy (tmpbuf, input_line_pointer); | |
2747 | strcat (tmpbuf, cp + 1 + 3); | |
2748 | *cp = '@'; | |
2749 | } | |
2750 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2751 | { | |
2752 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2753 | *cp = '\0'; | |
2754 | strcpy (tmpbuf, input_line_pointer); | |
2755 | strcat (tmpbuf, cp + 1 + 6); | |
2756 | *cp = '@'; | |
2757 | } | |
2758 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2759 | { | |
2760 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2761 | *cp = '\0'; | |
2762 | strcpy (tmpbuf, input_line_pointer); | |
2763 | strcat (tmpbuf, cp + 1 + 3); | |
2764 | *cp = '@'; | |
2765 | } | |
2766 | else | |
2767 | as_bad (_("Bad reloc specifier `%s' in expression"), cp + 1); | |
2768 | ||
2769 | /* GOT relocations are not supported in 16 bit mode */ | |
2770 | if (flag_16bit_code) | |
2771 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2772 | ||
2773 | input_line_pointer = tmpbuf; | |
2774 | } | |
2775 | } | |
2776 | #endif | |
2777 | ||
2778 | exp_seg = expression (exp); | |
2779 | ||
2780 | #ifdef BFD_ASSEMBLER | |
2781 | /* We do this to make sure that the section symbol is in | |
2782 | the symbol table. We will ultimately change the relocation | |
2783 | to be relative to the beginning of the section */ | |
2784 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) | |
2785 | { | |
2786 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2787 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2788 | section_symbol(exp->X_add_symbol->bsym->section); | |
2789 | assert (exp->X_op == O_symbol); | |
2790 | exp->X_op = O_subtract; | |
2791 | exp->X_op_symbol = GOT_symbol; | |
2792 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2793 | } | |
2794 | #endif | |
2795 | ||
2796 | if (*input_line_pointer) | |
2797 | as_bad (_("Ignoring junk `%s' after expression"), | |
2798 | input_line_pointer); | |
2799 | #if GCC_ASM_O_HACK | |
2800 | RESTORE_END_STRING (disp_end + 1); | |
2801 | #endif | |
2802 | RESTORE_END_STRING (disp_end); | |
2803 | input_line_pointer = save_input_line_pointer; | |
2804 | ||
2805 | if (exp->X_op == O_constant) | |
2806 | { | |
2807 | if (fits_in_signed_byte (exp->X_add_number)) | |
2808 | i.types[this_operand] |= Disp8; | |
2809 | } | |
2810 | #ifdef OBJ_AOUT | |
2811 | else if (exp_seg != text_section | |
2812 | && exp_seg != data_section | |
2813 | && exp_seg != bss_section | |
2814 | && exp_seg != undefined_section) | |
2815 | { | |
2816 | as_bad (_ ("Unimplemented segment type %d in operand"), exp_seg); | |
2817 | return 0; | |
2818 | } | |
2819 | #endif | |
2820 | return 1; | |
2821 | } | |
2822 | ||
2823 | static int i386_operand_modifier PARAMS ((char **, int)); | |
2824 | ||
2825 | static int | |
2826 | i386_operand_modifier (op_string, got_a_float) | |
2827 | char **op_string; | |
2828 | int got_a_float; | |
2829 | { | |
2830 | if (!strncasecmp (*op_string, "BYTE PTR", 8)) | |
2831 | { | |
2832 | i.suffix = BYTE_MNEM_SUFFIX; | |
2833 | *op_string += 8; | |
2834 | return BYTE_PTR; | |
2835 | ||
2836 | } | |
2837 | else if (!strncasecmp (*op_string, "WORD PTR", 8)) | |
2838 | { | |
2839 | i.suffix = WORD_MNEM_SUFFIX; | |
2840 | *op_string += 8; | |
2841 | return WORD_PTR; | |
2842 | } | |
2843 | ||
2844 | else if (!strncasecmp (*op_string, "DWORD PTR", 9)) | |
2845 | { | |
2846 | if (got_a_float) | |
2847 | i.suffix = SHORT_MNEM_SUFFIX; | |
2848 | else | |
2849 | i.suffix = DWORD_MNEM_SUFFIX; | |
2850 | *op_string += 9; | |
2851 | return DWORD_PTR; | |
2852 | } | |
2853 | ||
2854 | else if (!strncasecmp (*op_string, "QWORD PTR", 9)) | |
2855 | { | |
2856 | i.suffix = INTEL_DWORD_MNEM_SUFFIX; | |
2857 | *op_string += 9; | |
2858 | return QWORD_PTR; | |
2859 | } | |
2860 | ||
2861 | else if (!strncasecmp (*op_string, "XWORD PTR", 9)) | |
2862 | { | |
2863 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
2864 | *op_string += 9; | |
2865 | return XWORD_PTR; | |
2866 | } | |
2867 | ||
2868 | else if (!strncasecmp (*op_string, "SHORT", 5)) | |
2869 | { | |
2870 | *op_string += 5; | |
2871 | return SHORT; | |
2872 | } | |
2873 | ||
2874 | else if (!strncasecmp (*op_string, "OFFSET FLAT:", 12)) | |
2875 | { | |
2876 | *op_string += 12; | |
2877 | return OFFSET_FLAT; | |
2878 | } | |
2879 | ||
2880 | else if (!strncasecmp (*op_string, "FLAT", 4)) | |
2881 | { | |
2882 | *op_string += 4; | |
2883 | return FLAT; | |
2884 | } | |
2885 | ||
2886 | else return NONE_FOUND; | |
2887 | } | |
2888 | ||
2889 | static char * build_displacement_string PARAMS ((int, char *)); | |
2890 | ||
2891 | static char * | |
2892 | build_displacement_string (initial_disp, op_string) | |
2893 | int initial_disp; | |
2894 | char *op_string; | |
2895 | { | |
2896 | char *temp_string = (char *) malloc (strlen (op_string) + 1); | |
2897 | char *end_of_operand_string; | |
2898 | char *tc; | |
2899 | char *temp_disp, *temp_disp2; | |
2900 | ||
2901 | temp_string[0] = '\0'; | |
2902 | tc = end_of_operand_string = strchr (op_string, '['); | |
2903 | if ( initial_disp && !end_of_operand_string) | |
2904 | { | |
2905 | strcpy (temp_string, op_string); | |
2906 | return (temp_string); | |
2907 | } | |
2908 | ||
2909 | /* Build the whole displacement string */ | |
2910 | if (initial_disp) | |
2911 | { | |
2912 | strncpy (temp_string, op_string, end_of_operand_string - op_string); | |
2913 | temp_string[end_of_operand_string - op_string] = '\0'; | |
2914 | temp_disp = tc; | |
2915 | } | |
2916 | else | |
2917 | temp_disp = op_string; | |
2918 | ||
2919 | while (*temp_disp != '\0') | |
2920 | { | |
2921 | int add_minus = (*temp_disp == '-'); | |
2922 | ||
2923 | if (*temp_disp == '+' || *temp_disp == '-' || *temp_disp == '[') | |
2924 | temp_disp++; | |
2925 | ||
2926 | if (is_space_char (*temp_disp)) | |
2927 | temp_disp++; | |
2928 | ||
2929 | /* Don't consider registers */ | |
2930 | if (*temp_disp != REGISTER_PREFIX | |
2931 | && !(allow_naked_reg && i386_is_reg (temp_disp))) | |
2932 | { | |
2933 | char *string_start = temp_disp; | |
2934 | ||
2935 | while (*temp_disp != ']' | |
2936 | && *temp_disp != '+' | |
2937 | && *temp_disp != '-' | |
2938 | && *temp_disp != '*') | |
2939 | ++temp_disp; | |
2940 | ||
2941 | if (add_minus) | |
2942 | strcat (temp_string, "-"); | |
2943 | else | |
2944 | strcat (temp_string, "+"); | |
2945 | ||
2946 | strncat (temp_string, string_start, temp_disp - string_start); | |
2947 | if (*temp_disp == '+' || *temp_disp == '-') | |
2948 | --temp_disp; | |
2949 | } | |
2950 | ||
2951 | while (*temp_disp != '\0' | |
2952 | && *temp_disp != '+' | |
2953 | && *temp_disp != '-') | |
2954 | ++temp_disp; | |
2955 | } | |
2956 | ||
2957 | return temp_string; | |
2958 | } | |
2959 | ||
2960 | static int i386_parse_seg PARAMS ((char *)); | |
2961 | ||
2962 | static int | |
2963 | i386_parse_seg (op_string) | |
2964 | char *op_string; | |
2965 | { | |
2966 | if (is_space_char (*op_string)) | |
2967 | ++op_string; | |
2968 | ||
2969 | /* Should be one of es, cs, ss, ds fs or gs */ | |
2970 | switch (*op_string++) | |
2971 | { | |
2972 | case 'e': | |
2973 | i.seg[i.mem_operands] = &es; | |
2974 | break; | |
2975 | case 'c': | |
2976 | i.seg[i.mem_operands] = &cs; | |
2977 | break; | |
2978 | case 's': | |
2979 | i.seg[i.mem_operands] = &ss; | |
2980 | break; | |
2981 | case 'd': | |
2982 | i.seg[i.mem_operands] = &ds; | |
2983 | break; | |
2984 | case 'f': | |
2985 | i.seg[i.mem_operands] = &fs; | |
2986 | break; | |
2987 | case 'g': | |
2988 | i.seg[i.mem_operands] = &gs; | |
2989 | break; | |
2990 | default: | |
2991 | as_bad (_("bad segment name `%s'"), op_string); | |
2992 | return 0; | |
2993 | } | |
2994 | ||
2995 | if (*op_string++ != 's') | |
2996 | { | |
2997 | as_bad (_("bad segment name `%s'"), op_string); | |
2998 | return 0; | |
2999 | } | |
3000 | ||
3001 | if (is_space_char (*op_string)) | |
3002 | ++op_string; | |
3003 | ||
3004 | if (*op_string != ':') | |
3005 | { | |
3006 | as_bad (_("bad segment name `%s'"), op_string); | |
3007 | return 0; | |
3008 | } | |
3009 | ||
3010 | return 1; | |
3011 | ||
3012 | } | |
3013 | ||
3014 | static int i386_intel_memory_operand PARAMS ((char *)); | |
3015 | ||
3016 | static int | |
3017 | i386_intel_memory_operand (op_string) | |
3018 | char *op_string; | |
3019 | { | |
3020 | ||
3021 | char *end_of_operand_string; | |
3022 | ||
3023 | if (is_digit_char (*op_string) | |
3024 | && strchr (op_string, '[') == 0) | |
3025 | { | |
3026 | if (!i386_immediate (op_string)) | |
3027 | return 0; | |
3028 | else | |
3029 | return 1; | |
3030 | } | |
3031 | ||
3032 | /* Look for displacement preceding open bracket */ | |
3033 | if (*op_string != '[') | |
3034 | { | |
3035 | char *end_seg; | |
3036 | char *temp_string; | |
3037 | ||
3038 | end_seg = strchr (op_string, ':'); | |
3039 | if (end_seg) | |
3040 | { | |
3041 | if (!i386_parse_seg (op_string)) | |
3042 | return 0; | |
3043 | op_string = end_seg + 1; | |
3044 | } | |
3045 | ||
3046 | temp_string = build_displacement_string (true, op_string); | |
3047 | if (!i386_displacement (temp_string, temp_string + strlen (temp_string))) | |
3048 | return 0; | |
3049 | ||
3050 | end_of_operand_string = strchr (op_string, '['); | |
3051 | if (!end_of_operand_string) | |
3052 | end_of_operand_string = op_string + strlen (op_string); | |
3053 | ||
3054 | if (is_space_char (*end_of_operand_string)) | |
3055 | --end_of_operand_string; | |
3056 | ||
3057 | op_string = end_of_operand_string; | |
3058 | } | |
3059 | ||
3060 | if (*op_string == '[') | |
3061 | { | |
3062 | ++op_string; | |
3063 | ||
3064 | /* Pick off each component and figure out where it belongs */ | |
3065 | ||
3066 | end_of_operand_string = op_string; | |
3067 | ||
3068 | while (*op_string != ']') | |
3069 | { | |
3070 | ||
3071 | while (*end_of_operand_string != '+' | |
3072 | && *end_of_operand_string != '-' | |
3073 | && *end_of_operand_string != '*' | |
3074 | && *end_of_operand_string != ']') | |
3075 | end_of_operand_string++; | |
3076 | ||
3077 | if (*op_string == '+') | |
3078 | { | |
3079 | char *temp_string = op_string + 1; | |
3080 | if (is_space_char (*temp_string)) | |
3081 | ++temp_string; | |
3082 | if (*temp_string == REGISTER_PREFIX | |
3083 | || allow_naked_reg && i386_is_reg (temp_string)) | |
3084 | ++op_string; | |
3085 | } | |
3086 | ||
3087 | if (*op_string == REGISTER_PREFIX | |
3088 | || allow_naked_reg && i386_is_reg (op_string)) | |
3089 | { | |
3090 | const reg_entry *temp_reg; | |
3091 | char *end_op; | |
3092 | ||
3093 | END_STRING_AND_SAVE (end_of_operand_string); | |
3094 | temp_reg = parse_register (op_string, &end_op); | |
3095 | RESTORE_END_STRING (end_of_operand_string); | |
3096 | ||
3097 | if (temp_reg == NULL) | |
3098 | return 0; | |
3099 | ||
3100 | if (i.base_reg == NULL) | |
3101 | i.base_reg = temp_reg; | |
3102 | else | |
3103 | i.index_reg = temp_reg; | |
3104 | ||
3105 | i.types[this_operand] |= BaseIndex; | |
3106 | ||
3107 | } | |
3108 | else if (is_digit_char (*op_string) || *op_string == '+' || *op_string == '-') | |
3109 | { | |
3110 | ||
3111 | char *temp_string = build_displacement_string (false, op_string); | |
3112 | ||
3113 | if (*temp_string == '+') | |
3114 | ++temp_string; | |
3115 | ||
3116 | if (!i386_displacement (temp_string, temp_string + strlen (temp_string))) | |
3117 | return 0; | |
3118 | ||
3119 | ++op_string; | |
3120 | end_of_operand_string = op_string; | |
3121 | while (*end_of_operand_string != ']' | |
3122 | && *end_of_operand_string != '+' | |
3123 | && *end_of_operand_string != '-' | |
3124 | && *end_of_operand_string != '*') | |
3125 | ++end_of_operand_string; | |
3126 | } | |
3127 | else if (*op_string == '*') | |
3128 | { | |
3129 | ++op_string; | |
3130 | ||
3131 | if (i.base_reg && !i.index_reg) | |
3132 | { | |
3133 | i.index_reg = i.base_reg; | |
3134 | i.base_reg = 0; | |
3135 | } | |
3136 | ||
3137 | if (!i386_scale (op_string)) | |
3138 | return 0; | |
3139 | } | |
3140 | op_string = end_of_operand_string; | |
3141 | ++end_of_operand_string; | |
3142 | } | |
3143 | } | |
3144 | ||
3145 | return 1; | |
3146 | } | |
3147 | ||
3148 | static int i386_intel_operand PARAMS ((char *, int)); | |
3149 | ||
3150 | static int | |
3151 | i386_intel_operand (operand_string, got_a_float) | |
3152 | char *operand_string; | |
3153 | int got_a_float; | |
3154 | { | |
3155 | char *op_string = operand_string; | |
3156 | char *end_of_operand_string; | |
3157 | ||
3158 | int operand_modifier = i386_operand_modifier (&op_string, got_a_float); | |
3159 | if (is_space_char (*op_string)) | |
3160 | ++op_string; | |
3161 | ||
3162 | switch (operand_modifier) | |
3163 | { | |
3164 | case BYTE_PTR: | |
3165 | case WORD_PTR: | |
3166 | case DWORD_PTR: | |
3167 | case QWORD_PTR: | |
3168 | case XWORD_PTR: | |
3169 | if ((i.mem_operands == 1 | |
3170 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3171 | || i.mem_operands == 2) | |
3172 | { | |
3173 | as_bad (_("too many memory references for `%s'"), | |
3174 | current_templates->start->name); | |
3175 | return 0; | |
3176 | } | |
3177 | ||
3178 | if (!i386_intel_memory_operand (op_string)) | |
3179 | return 0; | |
3180 | ||
3181 | i.mem_operands++; | |
3182 | break; | |
3183 | ||
3184 | case SHORT: | |
3185 | ||
3186 | case FLAT: | |
3187 | ||
3188 | case OFFSET_FLAT: | |
3189 | if (!i386_immediate (op_string)) | |
3190 | return 0; | |
3191 | break; | |
3192 | ||
3193 | case NONE_FOUND: | |
3194 | /* Should be register or immediate */ | |
3195 | if (is_digit_char (*op_string) | |
3196 | && strchr (op_string, '[') == 0) | |
3197 | { | |
3198 | if (!i386_immediate (op_string)) | |
3199 | return 0; | |
3200 | } | |
3201 | else if (*op_string == REGISTER_PREFIX | |
3202 | || (allow_naked_reg | |
3203 | && i386_is_reg (op_string))) | |
3204 | { | |
3205 | ||
3206 | register const reg_entry * r; | |
3207 | char *end_op; | |
3208 | ||
3209 | r = parse_register (op_string, &end_op); | |
3210 | if (r == NULL) | |
3211 | return 0; | |
3212 | ||
3213 | /* Check for a segment override by searching for ':' after a | |
3214 | segment register. */ | |
3215 | op_string = end_op; | |
3216 | if (is_space_char (*op_string)) | |
3217 | ++op_string; | |
3218 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3219 | { | |
3220 | switch (r->reg_num) | |
3221 | { | |
3222 | case 0: | |
3223 | i.seg[i.mem_operands] = &es; | |
3224 | break; | |
3225 | case 1: | |
3226 | i.seg[i.mem_operands] = &cs; | |
3227 | break; | |
3228 | case 2: | |
3229 | i.seg[i.mem_operands] = &ss; | |
3230 | break; | |
3231 | case 3: | |
3232 | i.seg[i.mem_operands] = &ds; | |
3233 | break; | |
3234 | case 4: | |
3235 | i.seg[i.mem_operands] = &fs; | |
3236 | break; | |
3237 | case 5: | |
3238 | i.seg[i.mem_operands] = &gs; | |
3239 | break; | |
3240 | } | |
3241 | ||
3242 | } | |
3243 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
3244 | i.regs[this_operand] = r; | |
3245 | i.reg_operands++; | |
3246 | } | |
3247 | ||
3248 | else | |
3249 | { | |
3250 | ||
3251 | if (!i386_intel_memory_operand (op_string)) | |
3252 | return 0; | |
3253 | ||
3254 | i.mem_operands++; | |
3255 | } | |
3256 | break; | |
3257 | ||
3258 | } /* end switch */ | |
3259 | /* Special case for (%dx) while doing input/output op. */ | |
3260 | if (i.base_reg | |
3261 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3262 | && i.index_reg == 0 | |
3263 | && i.log2_scale_factor == 0 | |
3264 | && i.seg[i.mem_operands] == 0 | |
3265 | && (i.types[this_operand] & Disp) == 0) | |
3266 | { | |
3267 | i.types[this_operand] = InOutPortReg; | |
3268 | return 1; | |
3269 | } | |
3270 | /* Make sure the memory operand we've been dealt is valid. */ | |
3271 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) | |
3272 | { | |
3273 | if ((i.base_reg | |
3274 | && ((i.base_reg->reg_type & (Reg16|BaseIndex)) | |
3275 | != (Reg16|BaseIndex))) | |
3276 | || (i.index_reg | |
3277 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3278 | != (Reg16|BaseIndex)) | |
3279 | || ! (i.base_reg | |
3280 | && i.base_reg->reg_num < 6 | |
3281 | && i.index_reg->reg_num >= 6 | |
3282 | && i.log2_scale_factor == 0)))) | |
3283 | { | |
3284 | as_bad (_("`%s' is not a valid %s bit base/index expression"), | |
3285 | operand_string, "16"); | |
3286 | return 0; | |
3287 | } | |
3288 | } | |
3289 | else | |
3290 | { | |
3291 | if ((i.base_reg | |
3292 | && (i.base_reg->reg_type & Reg32) == 0) | |
3293 | || (i.index_reg | |
3294 | && ((i.index_reg->reg_type & (Reg32|BaseIndex)) | |
3295 | != (Reg32|BaseIndex)))) | |
3296 | { | |
3297 | as_bad (_("`%s' is not a valid %s bit base/index expression"), | |
3298 | operand_string, "32"); | |
3299 | return 0; | |
3300 | } | |
3301 | } | |
3302 | return 1; | |
3303 | } | |
3304 | ||
fecd2382 RP |
3305 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
3306 | on error. */ | |
3307 | ||
e715a027 RH |
3308 | static int i386_operand PARAMS ((char *)); |
3309 | ||
355afbcd KR |
3310 | static int |
3311 | i386_operand (operand_string) | |
3312 | char *operand_string; | |
fecd2382 | 3313 | { |
e715a027 RH |
3314 | char *op_string = operand_string; |
3315 | ||
3316 | if (is_space_char (*op_string)) | |
3317 | ++op_string; | |
355afbcd | 3318 | |
355afbcd | 3319 | /* We check for an absolute prefix (differentiating, |
3c8df4ba | 3320 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
355afbcd KR |
3321 | if (*op_string == ABSOLUTE_PREFIX) |
3322 | { | |
4edc93e9 ILT |
3323 | ++op_string; |
3324 | if (is_space_char (*op_string)) | |
e715a027 | 3325 | ++op_string; |
355afbcd KR |
3326 | i.types[this_operand] |= JumpAbsolute; |
3327 | } | |
3328 | ||
3329 | /* Check if operand is a register. */ | |
e715a027 RH |
3330 | if (*op_string == REGISTER_PREFIX |
3331 | || (allow_naked_reg && i386_is_reg (op_string))) | |
355afbcd | 3332 | { |
0351b70c | 3333 | register const reg_entry *r; |
4edc93e9 ILT |
3334 | char *end_op; |
3335 | ||
3336 | r = parse_register (op_string, &end_op); | |
3337 | if (r == NULL) | |
e715a027 RH |
3338 | return 0; |
3339 | ||
4edc93e9 ILT |
3340 | /* Check for a segment override by searching for ':' after a |
3341 | segment register. */ | |
3342 | op_string = end_op; | |
3343 | if (is_space_char (*op_string)) | |
e715a027 | 3344 | ++op_string; |
7540e470 | 3345 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) |
e715a027 RH |
3346 | { |
3347 | switch (r->reg_num) | |
3348 | { | |
3349 | case 0: | |
7540e470 ILT |
3350 | i.seg[i.mem_operands] = &es; |
3351 | break; | |
3352 | case 1: | |
3353 | i.seg[i.mem_operands] = &cs; | |
3354 | break; | |
3355 | case 2: | |
3356 | i.seg[i.mem_operands] = &ss; | |
3357 | break; | |
3358 | case 3: | |
3359 | i.seg[i.mem_operands] = &ds; | |
3360 | break; | |
3361 | case 4: | |
3362 | i.seg[i.mem_operands] = &fs; | |
3363 | break; | |
3364 | case 5: | |
3365 | i.seg[i.mem_operands] = &gs; | |
3366 | break; | |
3367 | } | |
4edc93e9 | 3368 | |
7540e470 ILT |
3369 | /* Skip the ':' and whitespace. */ |
3370 | ++op_string; | |
3371 | if (is_space_char (*op_string)) | |
3372 | ++op_string; | |
3373 | ||
3374 | /* Pretend given string starts here. */ | |
3375 | operand_string = op_string; | |
3376 | if (!is_digit_char (*op_string) | |
3377 | && !is_identifier_char (*op_string) | |
3378 | && *op_string != '(' | |
3379 | && *op_string != ABSOLUTE_PREFIX) | |
3380 | { | |
3381 | as_bad (_("bad memory operand `%s'"), op_string); | |
3382 | return 0; | |
3383 | } | |
3384 | /* Handle case of %es:*foo. */ | |
3385 | if (*op_string == ABSOLUTE_PREFIX) | |
3386 | { | |
4edc93e9 ILT |
3387 | ++op_string; |
3388 | if (is_space_char (*op_string)) | |
3389 | ++op_string; | |
7540e470 | 3390 | i.types[this_operand] |= JumpAbsolute; |
355afbcd | 3391 | } |
7540e470 ILT |
3392 | goto do_memory_reference; |
3393 | } | |
3394 | if (*op_string) | |
3395 | { | |
3396 | as_bad (_("Junk `%s' after register"), op_string); | |
3397 | return 0; | |
355afbcd | 3398 | } |
ec1e6bb8 | 3399 | i.types[this_operand] |= r->reg_type & ~BaseIndex; |
355afbcd KR |
3400 | i.regs[this_operand] = r; |
3401 | i.reg_operands++; | |
3402 | } | |
3403 | else if (*op_string == IMMEDIATE_PREFIX) | |
3404 | { /* ... or an immediate */ | |
4edc93e9 | 3405 | ++op_string; |
e715a027 RH |
3406 | if (!i386_immediate (op_string)) |
3407 | return 0; | |
355afbcd | 3408 | } |
e715a027 RH |
3409 | else if (is_digit_char (*op_string) |
3410 | || is_identifier_char (*op_string) | |
3411 | || *op_string == '(' ) | |
355afbcd KR |
3412 | { |
3413 | /* This is a memory reference of some sort. */ | |
0351b70c | 3414 | char *end_of_operand_string; |
355afbcd | 3415 | register char *base_string; |
ec1e6bb8 | 3416 | int found_base_index_form; |
e715a027 | 3417 | int operand_modifier; |
355afbcd | 3418 | |
0351b70c ILT |
3419 | /* Start and end of displacement string expression (if found). */ |
3420 | char *displacement_string_start; | |
3421 | char *displacement_string_end; | |
3422 | ||
355afbcd | 3423 | do_memory_reference: |
e715a027 | 3424 | |
4498e3d6 ILT |
3425 | if ((i.mem_operands == 1 |
3426 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3427 | || i.mem_operands == 2) | |
355afbcd | 3428 | { |
48401fcf | 3429 | as_bad (_("too many memory references for `%s'"), |
4498e3d6 | 3430 | current_templates->start->name); |
355afbcd KR |
3431 | return 0; |
3432 | } | |
355afbcd | 3433 | |
49864cfa KR |
3434 | /* Check for base index form. We detect the base index form by |
3435 | looking for an ')' at the end of the operand, searching | |
3436 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
4edc93e9 | 3437 | after the '('. */ |
355afbcd | 3438 | found_base_index_form = 0; |
0351b70c | 3439 | end_of_operand_string = op_string + strlen (op_string); |
4edc93e9 ILT |
3440 | |
3441 | --end_of_operand_string; | |
3442 | if (is_space_char (*end_of_operand_string)) | |
3443 | --end_of_operand_string; | |
3444 | ||
3445 | base_string = end_of_operand_string; | |
e715a027 | 3446 | |
355afbcd KR |
3447 | if (*base_string == ')') |
3448 | { | |
0b476c53 | 3449 | unsigned int parens_balanced = 1; |
49864cfa KR |
3450 | /* We've already checked that the number of left & right ()'s are |
3451 | equal, so this loop will not be infinite. */ | |
355afbcd KR |
3452 | do |
3453 | { | |
3454 | base_string--; | |
3455 | if (*base_string == ')') | |
0b476c53 | 3456 | parens_balanced++; |
355afbcd | 3457 | if (*base_string == '(') |
0b476c53 | 3458 | parens_balanced--; |
355afbcd | 3459 | } |
0b476c53 | 3460 | while (parens_balanced); |
4edc93e9 ILT |
3461 | |
3462 | /* If there is a displacement set-up for it to be parsed later. */ | |
3463 | displacement_string_start = op_string; | |
3464 | displacement_string_end = base_string; | |
3465 | ||
3466 | /* Skip past '(' and whitespace. */ | |
3467 | ++base_string; | |
3468 | if (is_space_char (*base_string)) | |
3469 | ++base_string; | |
3470 | ||
e715a027 RH |
3471 | if (*base_string == REGISTER_PREFIX |
3472 | || (allow_naked_reg && i386_is_reg (base_string)) | |
3473 | || *base_string == ',') | |
355afbcd KR |
3474 | found_base_index_form = 1; |
3475 | } | |
3476 | ||
3477 | /* If we can't parse a base index register expression, we've found | |
49864cfa KR |
3478 | a pure displacement expression. We set up displacement_string_start |
3479 | and displacement_string_end for the code below. */ | |
355afbcd KR |
3480 | if (!found_base_index_form) |
3481 | { | |
3482 | displacement_string_start = op_string; | |
4edc93e9 | 3483 | displacement_string_end = end_of_operand_string + 1; |
355afbcd KR |
3484 | } |
3485 | else | |
3486 | { | |
355afbcd KR |
3487 | i.types[this_operand] |= BaseIndex; |
3488 | ||
355afbcd KR |
3489 | /* Find base register (if any). */ |
3490 | if (*base_string != ',') | |
3491 | { | |
4edc93e9 ILT |
3492 | char *end_op; |
3493 | ||
3494 | /* Trim off the closing ')' so that parse_register won't | |
3495 | see it. */ | |
3496 | END_STRING_AND_SAVE (end_of_operand_string); | |
3497 | i.base_reg = parse_register (base_string, &end_op); | |
4edc93e9 | 3498 | RESTORE_END_STRING (end_of_operand_string); |
61c49d66 ILT |
3499 | |
3500 | if (i.base_reg == NULL) | |
3501 | return 0; | |
3502 | ||
4edc93e9 ILT |
3503 | base_string = end_op; |
3504 | if (is_space_char (*base_string)) | |
3505 | ++base_string; | |
355afbcd KR |
3506 | } |
3507 | ||
4edc93e9 ILT |
3508 | /* There may be an index reg or scale factor here. */ |
3509 | if (*base_string == ',') | |
355afbcd | 3510 | { |
4edc93e9 ILT |
3511 | ++base_string; |
3512 | if (is_space_char (*base_string)) | |
3513 | ++base_string; | |
355afbcd | 3514 | |
e715a027 RH |
3515 | if (*base_string == REGISTER_PREFIX |
3516 | || allow_naked_reg && i386_is_reg (base_string)) | |
355afbcd | 3517 | { |
4edc93e9 ILT |
3518 | char *end_op; |
3519 | ||
3520 | END_STRING_AND_SAVE (end_of_operand_string); | |
3521 | i.index_reg = parse_register (base_string, &end_op); | |
3522 | RESTORE_END_STRING (end_of_operand_string); | |
3523 | ||
3524 | if (i.index_reg == NULL) | |
3525 | return 0; | |
3526 | ||
3527 | base_string = end_op; | |
3528 | if (is_space_char (*base_string)) | |
3529 | ++base_string; | |
3530 | if (*base_string == ',') | |
3531 | { | |
3532 | ++base_string; | |
3533 | if (is_space_char (*base_string)) | |
3534 | ++base_string; | |
3535 | } | |
e715a027 | 3536 | else if (*base_string != ')' ) |
4edc93e9 ILT |
3537 | { |
3538 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
3539 | operand_string); | |
3540 | return 0; | |
3541 | } | |
a39116f1 | 3542 | } |
355afbcd | 3543 | |
4edc93e9 ILT |
3544 | /* Check for scale factor. */ |
3545 | if (isdigit ((unsigned char) *base_string)) | |
ec1e6bb8 | 3546 | { |
e715a027 RH |
3547 | if (!i386_scale (base_string)) |
3548 | return 0; | |
4edc93e9 ILT |
3549 | |
3550 | ++base_string; | |
3551 | if (is_space_char (*base_string)) | |
3552 | ++base_string; | |
3553 | if (*base_string != ')') | |
3554 | { | |
3555 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
3556 | operand_string); | |
3557 | return 0; | |
3558 | } | |
ec1e6bb8 | 3559 | } |
4edc93e9 | 3560 | else if (!i.index_reg) |
355afbcd | 3561 | { |
48401fcf | 3562 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
4edc93e9 | 3563 | *base_string); |
355afbcd | 3564 | return 0; |
a39116f1 | 3565 | } |
355afbcd | 3566 | } |
4edc93e9 ILT |
3567 | else if (*base_string != ')') |
3568 | { | |
3569 | as_bad (_("expecting `,' or `)' after base register in `%s'"), | |
3570 | operand_string); | |
3571 | return 0; | |
3572 | } | |
355afbcd KR |
3573 | } |
3574 | ||
e715a027 | 3575 | /* If there's an expression beginning the operand, parse it, |
4edc93e9 ILT |
3576 | assuming displacement_string_start and |
3577 | displacement_string_end are meaningful. */ | |
3578 | if (displacement_string_start != displacement_string_end) | |
355afbcd | 3579 | { |
e715a027 RH |
3580 | if (!i386_displacement (displacement_string_start, |
3581 | displacement_string_end)) | |
3582 | return 0; | |
355afbcd KR |
3583 | } |
3584 | ||
ec1e6bb8 | 3585 | /* Special case for (%dx) while doing input/output op. */ |
73a8be66 ILT |
3586 | if (i.base_reg |
3587 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3588 | && i.index_reg == 0 | |
3589 | && i.log2_scale_factor == 0 | |
3590 | && i.seg[i.mem_operands] == 0 | |
3591 | && (i.types[this_operand] & Disp) == 0) | |
355afbcd | 3592 | { |
ec1e6bb8 | 3593 | i.types[this_operand] = InOutPortReg; |
49864cfa KR |
3594 | return 1; |
3595 | } | |
73a8be66 | 3596 | /* Make sure the memory operand we've been dealt is valid. */ |
0351b70c | 3597 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
355afbcd | 3598 | { |
0351b70c ILT |
3599 | if ((i.base_reg |
3600 | && ((i.base_reg->reg_type & (Reg16|BaseIndex)) | |
3601 | != (Reg16|BaseIndex))) | |
3602 | || (i.index_reg | |
3603 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3604 | != (Reg16|BaseIndex)) | |
3605 | || ! (i.base_reg | |
3606 | && i.base_reg->reg_num < 6 | |
3607 | && i.index_reg->reg_num >= 6 | |
3608 | && i.log2_scale_factor == 0)))) | |
3609 | { | |
3610 | as_bad (_("`%s' is not a valid %s bit base/index expression"), | |
3611 | operand_string, "16"); | |
3612 | return 0; | |
3613 | } | |
3614 | } | |
3615 | else | |
3616 | { | |
3617 | if ((i.base_reg | |
3618 | && (i.base_reg->reg_type & Reg32) == 0) | |
3619 | || (i.index_reg | |
3620 | && ((i.index_reg->reg_type & (Reg32|BaseIndex)) | |
3621 | != (Reg32|BaseIndex)))) | |
3622 | { | |
3623 | as_bad (_("`%s' is not a valid %s bit base/index expression"), | |
3624 | operand_string, "32"); | |
3625 | return 0; | |
3626 | } | |
fecd2382 | 3627 | } |
ec1e6bb8 | 3628 | i.mem_operands++; |
355afbcd KR |
3629 | } |
3630 | else | |
3631 | { /* it's not a memory operand; argh! */ | |
e715a027 | 3632 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
aa56747a ILT |
3633 | output_invalid (*op_string), |
3634 | this_operand + 1, | |
355afbcd KR |
3635 | op_string); |
3636 | return 0; | |
3637 | } | |
3638 | return 1; /* normal return */ | |
fecd2382 RP |
3639 | } |
3640 | \f | |
3641 | /* | |
3642 | * md_estimate_size_before_relax() | |
3643 | * | |
3644 | * Called just before relax(). | |
3645 | * Any symbol that is now undefined will not become defined. | |
3646 | * Return the correct fr_subtype in the frag. | |
3647 | * Return the initial "guess for fr_var" to caller. | |
3648 | * The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
3649 | * Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
3650 | * Although it may not be explicit in the frag, pretend fr_var starts with a | |
3651 | * 0 value. | |
3652 | */ | |
3653 | int | |
355afbcd KR |
3654 | md_estimate_size_before_relax (fragP, segment) |
3655 | register fragS *fragP; | |
3656 | register segT segment; | |
fecd2382 | 3657 | { |
355afbcd KR |
3658 | register unsigned char *opcode; |
3659 | register int old_fr_fix; | |
3660 | ||
3661 | old_fr_fix = fragP->fr_fix; | |
3662 | opcode = (unsigned char *) fragP->fr_opcode; | |
73a8be66 ILT |
3663 | /* We've already got fragP->fr_subtype right; all we have to do is |
3664 | check for un-relaxable symbols. */ | |
355afbcd KR |
3665 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) |
3666 | { | |
3667 | /* symbol is undefined in this segment */ | |
0351b70c ILT |
3668 | int code16 = fragP->fr_subtype & CODE16; |
3669 | int size = code16 ? 2 : 4; | |
3670 | int pcrel_reloc = code16 ? BFD_RELOC_16_PCREL : BFD_RELOC_32_PCREL; | |
3671 | ||
355afbcd KR |
3672 | switch (opcode[0]) |
3673 | { | |
3674 | case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */ | |
3675 | opcode[0] = 0xe9; /* dword disp jmp */ | |
0351b70c ILT |
3676 | fragP->fr_fix += size; |
3677 | fix_new (fragP, old_fr_fix, size, | |
73a8be66 | 3678 | fragP->fr_symbol, |
f0b37b4a KR |
3679 | fragP->fr_offset, 1, |
3680 | (GOT_symbol && /* Not quite right - we should switch on | |
3681 | presence of @PLT, but I cannot see how | |
3682 | to get to that from here. We should have | |
3683 | done this in md_assemble to really | |
3684 | get it right all of the time, but I | |
3685 | think it does not matter that much, as | |
3686 | this will be right most of the time. ERY*/ | |
0351b70c ILT |
3687 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section) |
3688 | ? BFD_RELOC_386_PLT32 : pcrel_reloc); | |
355afbcd KR |
3689 | break; |
3690 | ||
3691 | default: | |
3692 | /* This changes the byte-displacement jump 0x7N --> | |
a39116f1 | 3693 | the dword-displacement jump 0x0f8N */ |
355afbcd KR |
3694 | opcode[1] = opcode[0] + 0x10; |
3695 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */ | |
0351b70c ILT |
3696 | fragP->fr_fix += 1 + size; /* we've added an opcode byte */ |
3697 | fix_new (fragP, old_fr_fix + 1, size, | |
355afbcd | 3698 | fragP->fr_symbol, |
0351b70c | 3699 | fragP->fr_offset, 1, |
f0b37b4a KR |
3700 | (GOT_symbol && /* Not quite right - we should switch on |
3701 | presence of @PLT, but I cannot see how | |
3702 | to get to that from here. ERY */ | |
0351b70c ILT |
3703 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section) |
3704 | ? BFD_RELOC_386_PLT32 : pcrel_reloc); | |
355afbcd | 3705 | break; |
a39116f1 | 3706 | } |
355afbcd KR |
3707 | frag_wane (fragP); |
3708 | } | |
3709 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
fecd2382 RP |
3710 | } /* md_estimate_size_before_relax() */ |
3711 | \f | |
3712 | /* | |
3713 | * md_convert_frag(); | |
3714 | * | |
3715 | * Called after relax() is finished. | |
3716 | * In: Address of frag. | |
3717 | * fr_type == rs_machine_dependent. | |
3718 | * fr_subtype is what the address relaxed to. | |
3719 | * | |
3720 | * Out: Any fixSs and constants are set up. | |
3721 | * Caller will turn frag into a ".space 0". | |
3722 | */ | |
49864cfa | 3723 | #ifndef BFD_ASSEMBLER |
fecd2382 | 3724 | void |
3ea36b53 | 3725 | md_convert_frag (headers, sec, fragP) |
355afbcd | 3726 | object_headers *headers; |
3ea36b53 | 3727 | segT sec; |
355afbcd | 3728 | register fragS *fragP; |
49864cfa KR |
3729 | #else |
3730 | void | |
3731 | md_convert_frag (abfd, sec, fragP) | |
3732 | bfd *abfd; | |
3733 | segT sec; | |
3734 | register fragS *fragP; | |
3735 | #endif | |
fecd2382 | 3736 | { |
355afbcd KR |
3737 | register unsigned char *opcode; |
3738 | unsigned char *where_to_put_displacement = NULL; | |
3739 | unsigned int target_address; | |
3740 | unsigned int opcode_address; | |
3741 | unsigned int extension = 0; | |
3742 | int displacement_from_opcode_start; | |
3743 | ||
3744 | opcode = (unsigned char *) fragP->fr_opcode; | |
3745 | ||
3746 | /* Address we want to reach in file space. */ | |
3747 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
7b23213f KR |
3748 | #ifdef BFD_ASSEMBLER /* not needed otherwise? */ |
3749 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
3750 | #endif | |
355afbcd KR |
3751 | |
3752 | /* Address opcode resides at in file space. */ | |
3753 | opcode_address = fragP->fr_address + fragP->fr_fix; | |
3754 | ||
3755 | /* Displacement from opcode start to fill into instruction. */ | |
3756 | displacement_from_opcode_start = target_address - opcode_address; | |
3757 | ||
3758 | switch (fragP->fr_subtype) | |
3759 | { | |
0351b70c ILT |
3760 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL): |
3761 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): | |
3762 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): | |
3763 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): | |
355afbcd KR |
3764 | /* don't have to change opcode */ |
3765 | extension = 1; /* 1 opcode + 1 displacement */ | |
3766 | where_to_put_displacement = &opcode[1]; | |
3767 | break; | |
3768 | ||
0351b70c ILT |
3769 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
3770 | extension = 5; /* 2 opcode + 4 displacement */ | |
3771 | opcode[1] = opcode[0] + 0x10; | |
3772 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3773 | where_to_put_displacement = &opcode[2]; | |
355afbcd KR |
3774 | break; |
3775 | ||
0351b70c ILT |
3776 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): |
3777 | extension = 4; /* 1 opcode + 4 displacement */ | |
3778 | opcode[0] = 0xe9; | |
3779 | where_to_put_displacement = &opcode[1]; | |
355afbcd KR |
3780 | break; |
3781 | ||
0351b70c ILT |
3782 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
3783 | extension = 3; /* 2 opcode + 2 displacement */ | |
355afbcd KR |
3784 | opcode[1] = opcode[0] + 0x10; |
3785 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
355afbcd KR |
3786 | where_to_put_displacement = &opcode[2]; |
3787 | break; | |
3788 | ||
0351b70c ILT |
3789 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
3790 | extension = 2; /* 1 opcode + 2 displacement */ | |
355afbcd | 3791 | opcode[0] = 0xe9; |
355afbcd KR |
3792 | where_to_put_displacement = &opcode[1]; |
3793 | break; | |
3794 | ||
3795 | default: | |
3796 | BAD_CASE (fragP->fr_subtype); | |
3797 | break; | |
3798 | } | |
3799 | /* now put displacement after opcode */ | |
3800 | md_number_to_chars ((char *) where_to_put_displacement, | |
ad660eb1 | 3801 | (valueT) (displacement_from_opcode_start - extension), |
355afbcd KR |
3802 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
3803 | fragP->fr_fix += extension; | |
fecd2382 | 3804 | } |
fecd2382 | 3805 | \f |
355afbcd | 3806 | |
fecd2382 | 3807 | int md_short_jump_size = 2; /* size of byte displacement jmp */ |
355afbcd | 3808 | int md_long_jump_size = 5; /* size of dword displacement jmp */ |
49864cfa | 3809 | const int md_reloc_size = 8; /* Size of relocation record */ |
fecd2382 | 3810 | |
355afbcd KR |
3811 | void |
3812 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3813 | char *ptr; | |
025b0302 | 3814 | addressT from_addr, to_addr; |
355afbcd KR |
3815 | fragS *frag; |
3816 | symbolS *to_symbol; | |
fecd2382 | 3817 | { |
355afbcd KR |
3818 | long offset; |
3819 | ||
3820 | offset = to_addr - (from_addr + 2); | |
ad660eb1 ILT |
3821 | md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */ |
3822 | md_number_to_chars (ptr + 1, (valueT) offset, 1); | |
fecd2382 RP |
3823 | } |
3824 | ||
355afbcd KR |
3825 | void |
3826 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3827 | char *ptr; | |
025b0302 | 3828 | addressT from_addr, to_addr; |
355afbcd KR |
3829 | fragS *frag; |
3830 | symbolS *to_symbol; | |
fecd2382 | 3831 | { |
355afbcd KR |
3832 | long offset; |
3833 | ||
ade614d5 | 3834 | if (flag_do_long_jump) |
355afbcd KR |
3835 | { |
3836 | offset = to_addr - S_GET_VALUE (to_symbol); | |
ad660eb1 ILT |
3837 | md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */ |
3838 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 3839 | fix_new (frag, (ptr + 1) - frag->fr_literal, 4, |
7b23213f | 3840 | to_symbol, (offsetT) 0, 0, BFD_RELOC_32); |
355afbcd KR |
3841 | } |
3842 | else | |
3843 | { | |
3844 | offset = to_addr - (from_addr + 5); | |
ad660eb1 ILT |
3845 | md_number_to_chars (ptr, (valueT) 0xe9, 1); |
3846 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 3847 | } |
fecd2382 RP |
3848 | } |
3849 | \f | |
fecd2382 | 3850 | /* Apply a fixup (fixS) to segment data, once it has been determined |
355afbcd KR |
3851 | by our caller that we have all the info we need to fix it up. |
3852 | ||
fecd2382 RP |
3853 | On the 386, immediates, displacements, and data pointers are all in |
3854 | the same (little-endian) format, so we don't need to care about which | |
3855 | we are handling. */ | |
3856 | ||
3ea36b53 ILT |
3857 | int |
3858 | md_apply_fix3 (fixP, valp, seg) | |
3859 | fixS *fixP; /* The fix we're to put in. */ | |
3860 | valueT *valp; /* Pointer to the value of the bits. */ | |
3861 | segT seg; /* Segment fix is from. */ | |
fecd2382 | 3862 | { |
355afbcd | 3863 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
3ea36b53 | 3864 | valueT value = *valp; |
355afbcd | 3865 | |
388fa5c6 ILT |
3866 | if (fixP->fx_r_type == BFD_RELOC_32 && fixP->fx_pcrel) |
3867 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
3868 | ||
f3d817d8 | 3869 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
7b23213f KR |
3870 | /* |
3871 | * This is a hack. There should be a better way to | |
3872 | * handle this. | |
3873 | */ | |
3874 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy) | |
3875 | { | |
0b476c53 | 3876 | #ifndef OBJ_AOUT |
76fb6d2f | 3877 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
f5003e7d ILT |
3878 | #ifdef TE_PE |
3879 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3880 | #endif | |
3881 | ) | |
590c50d8 | 3882 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
0b476c53 | 3883 | #endif |
590c50d8 ILT |
3884 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3885 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
3886 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg | |
ec1e6bb8 ILT |
3887 | || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0) |
3888 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
3889 | && ! S_IS_WEAK (fixP->fx_addsy) | |
3890 | && S_IS_DEFINED (fixP->fx_addsy) | |
3891 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
f3d817d8 DM |
3892 | { |
3893 | /* Yes, we add the values in twice. This is because | |
3894 | bfd_perform_relocation subtracts them out again. I think | |
3895 | bfd_perform_relocation is broken, but I don't dare change | |
3896 | it. FIXME. */ | |
3897 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
3898 | } | |
76fb6d2f ILT |
3899 | #endif |
3900 | #if defined (OBJ_COFF) && defined (TE_PE) | |
3901 | /* For some reason, the PE format does not store a section | |
3902 | address offset for a PC relative symbol. */ | |
3903 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
3904 | value += md_pcrel_from (fixP); | |
7b23213f | 3905 | #endif |
355afbcd | 3906 | } |
f0b37b4a KR |
3907 | |
3908 | /* Fix a few things - the dynamic linker expects certain values here, | |
3909 | and we must not dissappoint it. */ | |
590c50d8 ILT |
3910 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3911 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
3912 | && fixP->fx_addsy) | |
0351b70c | 3913 | switch (fixP->fx_r_type) { |
f0b37b4a KR |
3914 | case BFD_RELOC_386_PLT32: |
3915 | /* Make the jump instruction point to the address of the operand. At | |
3916 | runtime we merely add the offset to the actual PLT entry. */ | |
3917 | value = 0xfffffffc; | |
3918 | break; | |
3919 | case BFD_RELOC_386_GOTPC: | |
3920 | /* | |
3921 | * This is tough to explain. We end up with this one if we have | |
3922 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal | |
3923 | * here is to obtain the absolute address of the GOT, and it is strongly | |
3924 | * preferable from a performance point of view to avoid using a runtime | |
3925 | * relocation for this. The actual sequence of instructions often look | |
3926 | * something like: | |
3927 | * | |
3928 | * call .L66 | |
3929 | * .L66: | |
3930 | * popl %ebx | |
3931 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
3932 | * | |
3933 | * The call and pop essentially return the absolute address of | |
3934 | * the label .L66 and store it in %ebx. The linker itself will | |
3935 | * ultimately change the first operand of the addl so that %ebx points to | |
3936 | * the GOT, but to keep things simple, the .o file must have this operand | |
3937 | * set so that it generates not the absolute address of .L66, but the | |
3938 | * absolute address of itself. This allows the linker itself simply | |
3939 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
3940 | * added in, and the addend of the relocation is stored in the operand | |
3941 | * field for the instruction itself. | |
3942 | * | |
3943 | * Our job here is to fix the operand so that it would add the correct | |
3944 | * offset so that %ebx would point to itself. The thing that is tricky is | |
3945 | * that .-.L66 will point to the beginning of the instruction, so we need | |
3946 | * to further modify the operand so that it will point to itself. | |
3947 | * There are other cases where you have something like: | |
3948 | * | |
3949 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
3950 | * | |
3951 | * and here no correction would be required. Internally in the assembler | |
3952 | * we treat operands of this form as not being pcrel since the '.' is | |
3953 | * explicitly mentioned, and I wonder whether it would simplify matters | |
3954 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
3955 | * the pcrel_adjust field was used to store the correction, but since the | |
3956 | * expression is not pcrel, I felt it would be confusing to do it this way. | |
3957 | */ | |
c54c7aac | 3958 | value -= 1; |
f0b37b4a KR |
3959 | break; |
3960 | case BFD_RELOC_386_GOT32: | |
3961 | value = 0; /* Fully resolved at runtime. No addend. */ | |
c54c7aac | 3962 | break; |
f0b37b4a | 3963 | case BFD_RELOC_386_GOTOFF: |
c54c7aac KR |
3964 | break; |
3965 | ||
a1624e3f RH |
3966 | case BFD_RELOC_VTABLE_INHERIT: |
3967 | case BFD_RELOC_VTABLE_ENTRY: | |
3968 | fixP->fx_done = 0; | |
3969 | return 1; | |
3970 | ||
f0b37b4a KR |
3971 | default: |
3972 | break; | |
3973 | } | |
3974 | #endif | |
3975 | ||
f3d817d8 DM |
3976 | #endif |
3977 | md_number_to_chars (p, value, fixP->fx_size); | |
fecd2382 | 3978 | |
49864cfa KR |
3979 | return 1; |
3980 | } | |
49864cfa | 3981 | |
ad660eb1 ILT |
3982 | #if 0 |
3983 | /* This is never used. */ | |
355afbcd KR |
3984 | long /* Knows about the byte order in a word. */ |
3985 | md_chars_to_number (con, nbytes) | |
3986 | unsigned char con[]; /* Low order byte 1st. */ | |
3987 | int nbytes; /* Number of bytes in the input. */ | |
fecd2382 | 3988 | { |
355afbcd KR |
3989 | long retval; |
3990 | for (retval = 0, con += nbytes - 1; nbytes--; con--) | |
3991 | { | |
3992 | retval <<= BITS_PER_CHAR; | |
3993 | retval |= *con; | |
3994 | } | |
3995 | return retval; | |
fecd2382 | 3996 | } |
ad660eb1 | 3997 | #endif /* 0 */ |
fecd2382 | 3998 | \f |
355afbcd | 3999 | |
fecd2382 RP |
4000 | #define MAX_LITTLENUMS 6 |
4001 | ||
4002 | /* Turn the string pointed to by litP into a floating point constant of type | |
4003 | type, and emit the appropriate bytes. The number of LITTLENUMS emitted | |
3c8df4ba | 4004 | is stored in *sizeP . An error message is returned, or NULL on OK. */ |
fecd2382 | 4005 | char * |
355afbcd KR |
4006 | md_atof (type, litP, sizeP) |
4007 | char type; | |
4008 | char *litP; | |
4009 | int *sizeP; | |
fecd2382 | 4010 | { |
355afbcd KR |
4011 | int prec; |
4012 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4013 | LITTLENUM_TYPE *wordP; | |
4014 | char *t; | |
4015 | ||
4016 | switch (type) | |
4017 | { | |
4018 | case 'f': | |
4019 | case 'F': | |
4020 | prec = 2; | |
4021 | break; | |
4022 | ||
4023 | case 'd': | |
4024 | case 'D': | |
4025 | prec = 4; | |
4026 | break; | |
4027 | ||
4028 | case 'x': | |
4029 | case 'X': | |
4030 | prec = 5; | |
4031 | break; | |
4032 | ||
4033 | default: | |
4034 | *sizeP = 0; | |
48401fcf | 4035 | return _("Bad call to md_atof ()"); |
355afbcd KR |
4036 | } |
4037 | t = atof_ieee (input_line_pointer, type, words); | |
4038 | if (t) | |
4039 | input_line_pointer = t; | |
4040 | ||
4041 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
3c8df4ba KR |
4042 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with |
4043 | the bigendian 386. */ | |
355afbcd KR |
4044 | for (wordP = words + prec - 1; prec--;) |
4045 | { | |
ad660eb1 | 4046 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); |
355afbcd KR |
4047 | litP += sizeof (LITTLENUM_TYPE); |
4048 | } | |
49864cfa | 4049 | return 0; |
fecd2382 RP |
4050 | } |
4051 | \f | |
4052 | char output_invalid_buf[8]; | |
4053 | ||
e715a027 RH |
4054 | static char * output_invalid PARAMS ((int)); |
4055 | ||
355afbcd KR |
4056 | static char * |
4057 | output_invalid (c) | |
e715a027 | 4058 | int c; |
fecd2382 | 4059 | { |
355afbcd KR |
4060 | if (isprint (c)) |
4061 | sprintf (output_invalid_buf, "'%c'", c); | |
4062 | else | |
4063 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4064 | return output_invalid_buf; | |
fecd2382 RP |
4065 | } |
4066 | ||
4edc93e9 ILT |
4067 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
4068 | ||
e715a027 RH |
4069 | static const reg_entry * parse_register PARAMS ((char *, char **)); |
4070 | ||
0351b70c | 4071 | static const reg_entry * |
4edc93e9 ILT |
4072 | parse_register (reg_string, end_op) |
4073 | char *reg_string; | |
4074 | char **end_op; | |
fecd2382 | 4075 | { |
4edc93e9 | 4076 | register char *s = reg_string; |
355afbcd | 4077 | register char *p; |
4edc93e9 ILT |
4078 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4079 | const reg_entry *r; | |
4080 | ||
e715a027 RH |
4081 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ |
4082 | if (*s == REGISTER_PREFIX) | |
4083 | ++s; | |
4084 | ||
4edc93e9 ILT |
4085 | if (is_space_char (*s)) |
4086 | ++s; | |
355afbcd | 4087 | |
0351b70c ILT |
4088 | p = reg_name_given; |
4089 | while ((*p++ = register_chars[(unsigned char) *s++]) != '\0') | |
355afbcd | 4090 | { |
355afbcd | 4091 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) |
4edc93e9 | 4092 | { |
e715a027 RH |
4093 | if (!allow_naked_reg) |
4094 | { | |
4095 | *p = '\0'; | |
4096 | as_bad (_("bad register name `%s'"), reg_name_given); | |
4097 | } | |
4edc93e9 ILT |
4098 | return (const reg_entry *) NULL; |
4099 | } | |
355afbcd | 4100 | } |
4edc93e9 ILT |
4101 | |
4102 | *end_op = s - 1; | |
4103 | ||
4104 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4105 | ||
4106 | if (r == NULL) | |
4107 | { | |
e715a027 RH |
4108 | if (!allow_naked_reg) |
4109 | as_bad (_("bad register name `%s'"), reg_name_given); | |
4edc93e9 ILT |
4110 | return (const reg_entry *) NULL; |
4111 | } | |
4112 | ||
4113 | return r; | |
fecd2382 | 4114 | } |
f3d817d8 | 4115 | \f |
ade614d5 | 4116 | #ifdef OBJ_ELF |
3ea36b53 | 4117 | CONST char *md_shortopts = "kmVQ:"; |
ade614d5 KR |
4118 | #else |
4119 | CONST char *md_shortopts = "m"; | |
4120 | #endif | |
f3d817d8 DM |
4121 | struct option md_longopts[] = { |
4122 | {NULL, no_argument, NULL, 0} | |
4123 | }; | |
0351b70c | 4124 | size_t md_longopts_size = sizeof (md_longopts); |
fecd2382 | 4125 | |
f3d817d8 DM |
4126 | int |
4127 | md_parse_option (c, arg) | |
4128 | int c; | |
4129 | char *arg; | |
4130 | { | |
ade614d5 KR |
4131 | switch (c) |
4132 | { | |
4133 | case 'm': | |
4134 | flag_do_long_jump = 1; | |
4135 | break; | |
4136 | ||
590c50d8 | 4137 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3ea36b53 ILT |
4138 | /* -k: Ignore for FreeBSD compatibility. */ |
4139 | case 'k': | |
4140 | break; | |
4141 | ||
ade614d5 KR |
4142 | /* -V: SVR4 argument to print version ID. */ |
4143 | case 'V': | |
4144 | print_version_id (); | |
4145 | break; | |
4146 | ||
4147 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
4148 | should be emitted or not. FIXME: Not implemented. */ | |
4149 | case 'Q': | |
4150 | break; | |
4151 | #endif | |
4152 | ||
4153 | default: | |
4154 | return 0; | |
4155 | } | |
4156 | return 1; | |
f3d817d8 | 4157 | } |
fecd2382 | 4158 | |
f3d817d8 DM |
4159 | void |
4160 | md_show_usage (stream) | |
4161 | FILE *stream; | |
4162 | { | |
48401fcf TT |
4163 | fprintf (stream, _("\ |
4164 | -m do long jump\n")); | |
f3d817d8 | 4165 | } |
fecd2382 | 4166 | |
590c50d8 ILT |
4167 | #ifdef BFD_ASSEMBLER |
4168 | #ifdef OBJ_MAYBE_ELF | |
4169 | #ifdef OBJ_MAYBE_COFF | |
4170 | ||
4171 | /* Pick the target format to use. */ | |
4172 | ||
4173 | const char * | |
4174 | i386_target_format () | |
4175 | { | |
4176 | switch (OUTPUT_FLAVOR) | |
4177 | { | |
4178 | case bfd_target_coff_flavour: | |
4179 | return "coff-i386"; | |
4180 | case bfd_target_elf_flavour: | |
4181 | return "elf32-i386"; | |
4182 | default: | |
4183 | abort (); | |
4184 | return NULL; | |
4185 | } | |
4186 | } | |
4187 | ||
4188 | #endif /* OBJ_MAYBE_COFF */ | |
4189 | #endif /* OBJ_MAYBE_ELF */ | |
4190 | #endif /* BFD_ASSEMBLER */ | |
4191 | \f | |
fecd2382 RP |
4192 | /* ARGSUSED */ |
4193 | symbolS * | |
355afbcd KR |
4194 | md_undefined_symbol (name) |
4195 | char *name; | |
fecd2382 | 4196 | { |
f0b37b4a KR |
4197 | if (*name == '_' && *(name+1) == 'G' |
4198 | && strcmp(name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
4199 | { | |
0351b70c | 4200 | if (!GOT_symbol) |
f0b37b4a | 4201 | { |
0351b70c | 4202 | if (symbol_find (name)) |
aa56747a | 4203 | as_bad (_("GOT already in symbol table")); |
0351b70c | 4204 | GOT_symbol = symbol_new (name, undefined_section, |
f0b37b4a KR |
4205 | (valueT) 0, &zero_address_frag); |
4206 | }; | |
4207 | return GOT_symbol; | |
4208 | } | |
355afbcd | 4209 | return 0; |
fecd2382 RP |
4210 | } |
4211 | ||
fecd2382 | 4212 | /* Round up a section size to the appropriate boundary. */ |
3c8df4ba | 4213 | valueT |
355afbcd KR |
4214 | md_section_align (segment, size) |
4215 | segT segment; | |
3c8df4ba | 4216 | valueT size; |
fecd2382 | 4217 | { |
91951af6 ILT |
4218 | #ifdef OBJ_AOUT |
4219 | #ifdef BFD_ASSEMBLER | |
4220 | /* For a.out, force the section size to be aligned. If we don't do | |
4221 | this, BFD will align it for us, but it will not write out the | |
4222 | final bytes of the section. This may be a bug in BFD, but it is | |
4223 | easier to fix it here since that is how the other a.out targets | |
4224 | work. */ | |
4225 | int align; | |
4226 | ||
4227 | align = bfd_get_section_alignment (stdoutput, segment); | |
4228 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
4229 | #endif | |
4230 | #endif | |
4231 | ||
4232 | return size; | |
fecd2382 RP |
4233 | } |
4234 | ||
4edc93e9 ILT |
4235 | /* On the i386, PC-relative offsets are relative to the start of the |
4236 | next instruction. That is, the address of the offset, plus its | |
4237 | size, since the offset is always the last part of the insn. */ | |
4238 | ||
fecd2382 | 4239 | long |
355afbcd KR |
4240 | md_pcrel_from (fixP) |
4241 | fixS *fixP; | |
fecd2382 | 4242 | { |
355afbcd | 4243 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
fecd2382 RP |
4244 | } |
4245 | ||
49864cfa | 4246 | #ifndef I386COFF |
542e1629 | 4247 | |
49864cfa | 4248 | static void |
ad660eb1 ILT |
4249 | s_bss (ignore) |
4250 | int ignore; | |
542e1629 | 4251 | { |
49864cfa | 4252 | register int temp; |
542e1629 | 4253 | |
49864cfa | 4254 | temp = get_absolute_expression (); |
49864cfa | 4255 | subseg_set (bss_section, (subsegT) temp); |
49864cfa KR |
4256 | demand_empty_rest_of_line (); |
4257 | } | |
542e1629 | 4258 | |
49864cfa | 4259 | #endif |
355afbcd | 4260 | |
542e1629 | 4261 | |
49864cfa | 4262 | #ifdef BFD_ASSEMBLER |
c54c7aac KR |
4263 | |
4264 | void | |
4265 | i386_validate_fix (fixp) | |
4266 | fixS *fixp; | |
4267 | { | |
4268 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
4269 | { | |
4270 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
4271 | fixp->fx_subsy = 0; | |
4272 | } | |
4273 | } | |
4274 | ||
f0b37b4a KR |
4275 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) |
4276 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
542e1629 | 4277 | |
49864cfa KR |
4278 | arelent * |
4279 | tc_gen_reloc (section, fixp) | |
4280 | asection *section; | |
4281 | fixS *fixp; | |
542e1629 | 4282 | { |
ad660eb1 | 4283 | arelent *rel; |
49864cfa | 4284 | bfd_reloc_code_real_type code; |
542e1629 | 4285 | |
73a8be66 | 4286 | switch (fixp->fx_r_type) |
49864cfa | 4287 | { |
f0b37b4a KR |
4288 | case BFD_RELOC_386_PLT32: |
4289 | case BFD_RELOC_386_GOT32: | |
4290 | case BFD_RELOC_386_GOTOFF: | |
4291 | case BFD_RELOC_386_GOTPC: | |
a52f90a4 | 4292 | case BFD_RELOC_RVA: |
a1624e3f RH |
4293 | case BFD_RELOC_VTABLE_ENTRY: |
4294 | case BFD_RELOC_VTABLE_INHERIT: | |
f0b37b4a KR |
4295 | code = fixp->fx_r_type; |
4296 | break; | |
4297 | default: | |
4298 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
4299 | { | |
f0b37b4a KR |
4300 | MAP (1, 0, BFD_RELOC_8); |
4301 | MAP (2, 0, BFD_RELOC_16); | |
f0b37b4a | 4302 | MAP (4, 0, BFD_RELOC_32); |
f0b37b4a KR |
4303 | MAP (1, 1, BFD_RELOC_8_PCREL); |
4304 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
f0b37b4a KR |
4305 | MAP (4, 1, BFD_RELOC_32_PCREL); |
4306 | default: | |
48401fcf TT |
4307 | if (fixp->fx_pcrel) |
4308 | as_bad (_("Can not do %d byte pc-relative relocation"), | |
4309 | fixp->fx_size); | |
4310 | else | |
4311 | as_bad (_("Can not do %d byte relocation"), fixp->fx_size); | |
73a8be66 ILT |
4312 | code = BFD_RELOC_32; |
4313 | break; | |
f0b37b4a | 4314 | } |
73a8be66 | 4315 | break; |
49864cfa | 4316 | } |
3c8df4ba KR |
4317 | #undef MAP |
4318 | #undef F | |
542e1629 | 4319 | |
f0b37b4a KR |
4320 | if (code == BFD_RELOC_32 |
4321 | && GOT_symbol | |
4322 | && fixp->fx_addsy == GOT_symbol) | |
4323 | code = BFD_RELOC_386_GOTPC; | |
4324 | ||
590c50d8 | 4325 | rel = (arelent *) xmalloc (sizeof (arelent)); |
ad660eb1 | 4326 | rel->sym_ptr_ptr = &fixp->fx_addsy->bsym; |
a1624e3f | 4327 | |
ad660eb1 | 4328 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; |
a1624e3f RH |
4329 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the |
4330 | vtable entry to be used in the relocation's section offset. */ | |
4331 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4332 | rel->address = fixp->fx_offset; | |
4333 | ||
49864cfa | 4334 | if (fixp->fx_pcrel) |
ad660eb1 | 4335 | rel->addend = fixp->fx_addnumber; |
49864cfa | 4336 | else |
ad660eb1 | 4337 | rel->addend = 0; |
355afbcd | 4338 | |
ad660eb1 | 4339 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
e592f0e6 | 4340 | if (rel->howto == NULL) |
ad660eb1 | 4341 | { |
e592f0e6 | 4342 | as_bad_where (fixp->fx_file, fixp->fx_line, |
48401fcf | 4343 | _("Cannot represent relocation type %s"), |
e592f0e6 ILT |
4344 | bfd_get_reloc_code_name (code)); |
4345 | /* Set howto to a garbage value so that we can keep going. */ | |
4346 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
4347 | assert (rel->howto != NULL); | |
ad660eb1 | 4348 | } |
49864cfa | 4349 | |
ad660eb1 | 4350 | return rel; |
49864cfa KR |
4351 | } |
4352 | ||
4353 | #else /* ! BFD_ASSEMBLER */ | |
4354 | ||
4355 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
4356 | void | |
4357 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4358 | char *where; | |
4359 | fixS *fixP; | |
4360 | relax_addressT segment_address_in_file; | |
4b77b129 | 4361 | { |
49864cfa KR |
4362 | /* |
4363 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
4364 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
4365 | */ | |
4b77b129 | 4366 | |
3c8df4ba | 4367 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; |
49864cfa KR |
4368 | long r_symbolnum; |
4369 | ||
4370 | know (fixP->fx_addsy != NULL); | |
4371 | ||
4372 | md_number_to_chars (where, | |
ad660eb1 ILT |
4373 | (valueT) (fixP->fx_frag->fr_address |
4374 | + fixP->fx_where - segment_address_in_file), | |
49864cfa KR |
4375 | 4); |
4376 | ||
4377 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
4378 | ? S_GET_TYPE (fixP->fx_addsy) | |
4379 | : fixP->fx_addsy->sy_number); | |
4380 | ||
4381 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
4382 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4383 | where[4] = r_symbolnum & 0x0ff; | |
4384 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
4385 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
4386 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4b77b129 | 4387 | } |
355afbcd | 4388 | |
49864cfa | 4389 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
4b77b129 | 4390 | |
49864cfa | 4391 | #if defined (I386COFF) |
4b77b129 | 4392 | |
355afbcd KR |
4393 | short |
4394 | tc_coff_fix2rtype (fixP) | |
4395 | fixS *fixP; | |
4b77b129 | 4396 | { |
3ea36b53 ILT |
4397 | if (fixP->fx_r_type == R_IMAGEBASE) |
4398 | return R_IMAGEBASE; | |
4399 | ||
355afbcd KR |
4400 | return (fixP->fx_pcrel ? |
4401 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
4402 | fixP->fx_size == 2 ? R_PCRWORD : | |
4403 | R_PCRLONG) : | |
4404 | (fixP->fx_size == 1 ? R_RELBYTE : | |
4405 | fixP->fx_size == 2 ? R_RELWORD : | |
4406 | R_DIR32)); | |
4b77b129 ILT |
4407 | } |
4408 | ||
49864cfa KR |
4409 | int |
4410 | tc_coff_sizemachdep (frag) | |
4411 | fragS *frag; | |
4412 | { | |
4413 | if (frag->fr_next) | |
4414 | return (frag->fr_next->fr_address - frag->fr_address); | |
4415 | else | |
4416 | return 0; | |
4417 | } | |
4418 | ||
4419 | #endif /* I386COFF */ | |
4420 | ||
4421 | #endif /* BFD_ASSEMBLER? */ | |
3ea36b53 | 4422 | \f |
fecd2382 | 4423 | /* end of tc-i386.c */ |