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* cpu-powerpc.c (bfd_powerpc_archs): Add ppc 750.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
92static void optimize_imm PARAMS ((void));
93static void optimize_disp PARAMS ((void));
94static int match_template PARAMS ((void));
95static int check_string PARAMS ((void));
96static int process_suffix PARAMS ((void));
97static int check_byte_reg PARAMS ((void));
98static int check_long_reg PARAMS ((void));
99static int check_qword_reg PARAMS ((void));
100static int check_word_reg PARAMS ((void));
101static int finalize_imm PARAMS ((void));
102static int process_operands PARAMS ((void));
103static const seg_entry *build_modrm_byte PARAMS ((void));
104static void output_insn PARAMS ((void));
105static void output_branch PARAMS ((void));
106static void output_jump PARAMS ((void));
107static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 108static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
29b0f896
AM		 112#ifndef I386COFF
113static void s_bss PARAMS ((int));
252b5132 114#endif
17d4e2a2
L		 115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116static void handle_large_common (int small ATTRIBUTE_UNUSED);
117#endif
252b5132 118
a847613f 119static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 120
252b5132 121/* 'md_assemble ()' gathers together information and puts it into a
47926f60 122 i386_insn. */
252b5132 123
520dc8e8
AM		 124union i386_op
125 {
126 expressionS *disps;
127 expressionS *imms;
128 const reg_entry *regs;
129 };
130
252b5132
RH		 131struct _i386_insn
132 {
47926f60 133 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 134 template tm;
135
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
138 char suffix;
139
47926f60 140 /* OPERANDS gives the number of given operands. */
252b5132
RH		 141 unsigned int operands;
142
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
47926f60 145 operands. */
252b5132
RH		 146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
147
148 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 149 use OP[i] for the corresponding operand. */
252b5132
RH		 150 unsigned int types[MAX_OPERANDS];
151
520dc8e8
AM		 152 /* Displacement expression, immediate expression, or register for each
153 operand. */
154 union i386_op op[MAX_OPERANDS];
252b5132 155
3e73aa7c
JH		 156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158#define Operand_PCrel 1
159
252b5132 160 /* Relocation type for operand */
f86103b7 161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 162
252b5132
RH		 163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
168
169 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 170 explicit segment overrides are given. */
ce8a8b2f 171 const seg_entry *seg[2];
252b5132
RH		 172
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
177
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
180
181 modrm_byte rm;
3e73aa7c 182 rex_byte rex;
252b5132
RH		 183 sib_byte sib;
184 };
185
186typedef struct _i386_insn i386_insn;
187
188/* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
32137342 190const char extra_symbol_chars[] = "*%-(["
252b5132 191#ifdef LEX_AT
32137342
NC		 192 "@"
193#endif
194#ifdef LEX_QM
195 "?"
252b5132 196#endif
32137342 197 ;
252b5132 198
29b0f896
AM		 199#if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 201 && !defined (TE_GNU) \
29b0f896 202 && !defined (TE_LINUX) \
32137342 203 && !defined (TE_NETWARE) \
29b0f896
AM		 204 && !defined (TE_FreeBSD) \
205 && !defined (TE_NetBSD)))
252b5132 206/* This array holds the chars that always start a comment. If the
b3b91714
AM		 207 pre-processor is disabled, these aren't very useful. The option
208 --divide will remove '/' from this list. */
209const char *i386_comment_chars = "#/";
210#define SVR4_COMMENT_CHARS 1
252b5132 211#define PREFIX_SEPARATOR '\\'
252b5132 212
b3b91714
AM		 213#else
214const char *i386_comment_chars = "#";
215#define PREFIX_SEPARATOR '/'
216#endif
217
252b5132
RH		 218/* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 220 .line and .file directives will appear in the pre-processed output.
221 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 222 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 223 #NO_APP at the beginning of its output.
224 Also note that comments started like this one will always work if
252b5132 225 '/' isn't otherwise defined. */
b3b91714 226const char line_comment_chars[] = "#/";
252b5132 227
63a0b638 228const char line_separator_chars[] = ";";
252b5132 229
ce8a8b2f
AM		 230/* Chars that can be used to separate mant from exp in floating point
231 nums. */
252b5132
RH		 232const char EXP_CHARS[] = "eE";
233
ce8a8b2f
AM		 234/* Chars that mean this number is a floating point constant
235 As in 0f12.456
236 or 0d1.2345e12. */
252b5132
RH		 237const char FLT_CHARS[] = "fFdDxX";
238
ce8a8b2f 239/* Tables for lexical analysis. */
252b5132
RH		 240static char mnemonic_chars[256];
241static char register_chars[256];
242static char operand_chars[256];
243static char identifier_chars[256];
244static char digit_chars[256];
245
ce8a8b2f 246/* Lexical macros. */
252b5132
RH		 247#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248#define is_operand_char(x) (operand_chars[(unsigned char) x])
249#define is_register_char(x) (register_chars[(unsigned char) x])
250#define is_space_char(x) ((x) == ' ')
251#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252#define is_digit_char(x) (digit_chars[(unsigned char) x])
253
0234cb7c 254/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 255static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
256
257/* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
47926f60 260 assembler instruction). */
252b5132 261static char save_stack[32];
ce8a8b2f 262static char *save_stack_p;
252b5132
RH		 263#define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265#define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
267
47926f60 268/* The instruction we're assembling. */
252b5132
RH		 269static i386_insn i;
270
271/* Possible templates for current insn. */
272static const templates *current_templates;
273
47926f60 274/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 275static expressionS disp_expressions[2], im_expressions[2];
276
47926f60
KH		 277/* Current operand we are working on. */
278static int this_operand;
252b5132 279
3e73aa7c
JH		 280/* We support four different modes. FLAG_CODE variable is used to distinguish
281 these. */
282
283enum flag_code {
284 CODE_32BIT,
285 CODE_16BIT,
286 CODE_64BIT };
f3c180ae 287#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 288
289static enum flag_code flag_code;
4fa24527 290static unsigned int object_64bit;
3e73aa7c
JH		 291static int use_rela_relocations = 0;
292
293/* The names used to print error messages. */
b77a7acd 294static const char *flag_code_names[] =
3e73aa7c
JH		 295 {
296 "32",
297 "16",
298 "64"
299 };
252b5132 300
47926f60
KH		 301/* 1 for intel syntax,
302 0 if att syntax. */
303static int intel_syntax = 0;
252b5132 304
47926f60
KH		 305/* 1 if register prefix % not required. */
306static int allow_naked_reg = 0;
252b5132 307
47926f60
KH		 308/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311static char stackop_size = '\0';
eecb386c 312
12b55ccc
L		 313/* Non-zero to optimize code alignment. */
314int optimize_align_code = 1;
315
47926f60
KH		 316/* Non-zero to quieten some warnings. */
317static int quiet_warnings = 0;
a38cf1db 318
47926f60
KH		 319/* CPU name. */
320static const char *cpu_arch_name = NULL;
5c6af06e 321static const char *cpu_sub_arch_name = NULL;
a38cf1db 322
47926f60 323/* CPU feature flags. */
29b0f896 324static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 325
fddf5b5b
AM		 326/* If set, conditional jumps are not automatically promoted to handle
327 larger than a byte offset. */
328static unsigned int no_cond_jump_promotion = 0;
329
29b0f896 330/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 331static symbolS *GOT_symbol;
29b0f896 332
a4447b93
RH		 333/* The dwarf2 return column, adjusted for 32 or 64 bit. */
334unsigned int x86_dwarf2_return_column;
335
336/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
337int x86_cie_data_alignment;
338
252b5132 339/* Interface to relax_segment.
fddf5b5b
AM		 340 There are 3 major relax states for 386 jump insns because the
341 different types of jumps add different sizes to frags when we're
342 figuring out what sort of jump to choose to reach a given label. */
252b5132 343
47926f60 344/* Types. */
93c2a809
AM		 345#define UNCOND_JUMP 0
346#define COND_JUMP 1
347#define COND_JUMP86 2
fddf5b5b 348
47926f60 349/* Sizes. */
252b5132
RH		 350#define CODE16 1
351#define SMALL 0
29b0f896 352#define SMALL16 (SMALL | CODE16)
252b5132 353#define BIG 2
29b0f896 354#define BIG16 (BIG | CODE16)
252b5132
RH		 355
356#ifndef INLINE
357#ifdef __GNUC__
358#define INLINE __inline__
359#else
360#define INLINE
361#endif
362#endif
363
fddf5b5b
AM		 364#define ENCODE_RELAX_STATE(type, size) \
365 ((relax_substateT) (((type) << 2) | (size)))
366#define TYPE_FROM_RELAX_STATE(s) \
367 ((s) >> 2)
368#define DISP_SIZE_FROM_RELAX_STATE(s) \
369 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 370
371/* This table is used by relax_frag to promote short jumps to long
372 ones where necessary. SMALL (short) jumps may be promoted to BIG
373 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
374 don't allow a short jump in a 32 bit code segment to be promoted to
375 a 16 bit offset jump because it's slower (requires data size
376 prefix), and doesn't work, unless the destination is in the bottom
377 64k of the code segment (The top 16 bits of eip are zeroed). */
378
379const relax_typeS md_relax_table[] =
380{
24eab124
AM		 381 /* The fields are:
382 1) most positive reach of this state,
383 2) most negative reach of this state,
93c2a809 384 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 385 4) which index into the table to try if we can't fit into this one. */
252b5132 386
fddf5b5b 387 /* UNCOND_JUMP states. */
93c2a809
AM		 388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
390 /* dword jmp adds 4 bytes to frag:
391 0 extra opcode bytes, 4 displacement bytes. */
252b5132 392 {0, 0, 4, 0},
93c2a809
AM		 393 /* word jmp adds 2 byte2 to frag:
394 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 395 {0, 0, 2, 0},
396
93c2a809
AM		 397 /* COND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
402 {0, 0, 5, 0},
fddf5b5b 403 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 404 1 extra opcode byte, 2 displacement bytes. */
405 {0, 0, 3, 0},
406
407 /* COND_JUMP86 states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
413 /* word conditionals add 4 bytes to frag:
414 1 displacement byte and a 3 byte long branch insn. */
415 {0, 0, 4, 0}
252b5132
RH		 416};
417
e413e4e9
AM		 418static const arch_entry cpu_arch[] = {
419 {"i8086", Cpu086 },
420 {"i186", Cpu086|Cpu186 },
421 {"i286", Cpu086|Cpu186|Cpu286 },
422 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
423 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 424 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
425 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
426 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
427 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
428 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
429 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
430 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
431 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
432 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
433 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
434 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
435 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 436 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 437 {".mmx", CpuMMX },
438 {".sse", CpuMMX|CpuMMX2|CpuSSE },
439 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 440 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 441 {".3dnow", CpuMMX|Cpu3dnow },
442 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
443 {".padlock", CpuPadLock },
30123838
JB		 444 {".pacifica", CpuSVME },
445 {".svme", CpuSVME },
e413e4e9
AM		 446 {NULL, 0 }
447};
448
29b0f896
AM		 449const pseudo_typeS md_pseudo_table[] =
450{
451#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
452 {"align", s_align_bytes, 0},
453#else
454 {"align", s_align_ptwo, 0},
455#endif
456 {"arch", set_cpu_arch, 0},
457#ifndef I386COFF
458 {"bss", s_bss, 0},
459#endif
460 {"ffloat", float_cons, 'f'},
461 {"dfloat", float_cons, 'd'},
462 {"tfloat", float_cons, 'x'},
463 {"value", cons, 2},
d182319b 464 {"slong", signed_cons, 4},
29b0f896
AM		 465 {"noopt", s_ignore, 0},
466 {"optim", s_ignore, 0},
467 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
468 {"code16", set_code_flag, CODE_16BIT},
469 {"code32", set_code_flag, CODE_32BIT},
470 {"code64", set_code_flag, CODE_64BIT},
471 {"intel_syntax", set_intel_syntax, 1},
472 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 473#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
474 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 475#else
476 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
477 {"loc", dwarf2_directive_loc, 0},
478 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 479#endif
6482c264
NC		 480#ifdef TE_PE
481 {"secrel32", pe_directive_secrel, 0},
482#endif
29b0f896
AM		 483 {0, 0, 0}
484};
485
486/* For interface with expression (). */
487extern char *input_line_pointer;
488
489/* Hash table for instruction mnemonic lookup. */
490static struct hash_control *op_hash;
491
492/* Hash table for register lookup. */
493static struct hash_control *reg_hash;
494\f
252b5132
RH		 495void
496i386_align_code (fragP, count)
497 fragS *fragP;
498 int count;
499{
ce8a8b2f
AM		 500 /* Various efficient no-op patterns for aligning code labels.
501 Note: Don't try to assemble the instructions in the comments.
502 0L and 0w are not legal. */
252b5132
RH		 503 static const char f32_1[] =
504 {0x90}; /* nop */
505 static const char f32_2[] =
506 {0x89,0xf6}; /* movl %esi,%esi */
507 static const char f32_3[] =
508 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
509 static const char f32_4[] =
510 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
511 static const char f32_5[] =
512 {0x90, /* nop */
513 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
514 static const char f32_6[] =
515 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
516 static const char f32_7[] =
517 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
518 static const char f32_8[] =
519 {0x90, /* nop */
520 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
521 static const char f32_9[] =
522 {0x89,0xf6, /* movl %esi,%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_10[] =
525 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
526 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
527 static const char f32_11[] =
528 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_12[] =
531 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
532 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
533 static const char f32_13[] =
534 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
535 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
536 static const char f32_14[] =
537 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
538 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
539 static const char f32_15[] =
540 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
541 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 542 static const char f16_3[] =
543 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 544 static const char f16_4[] =
545 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
546 static const char f16_5[] =
547 {0x90, /* nop */
548 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
549 static const char f16_6[] =
550 {0x89,0xf6, /* mov %si,%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char f16_7[] =
553 {0x8d,0x74,0x00, /* lea 0(%si),%si */
554 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
555 static const char f16_8[] =
556 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
557 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
558 static const char *const f32_patt[] = {
559 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
560 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
561 };
562 static const char *const f16_patt[] = {
c3332e24 563 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 564 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
565 };
566
33fef721
JH		 567 if (count <= 0 || count > 15)
568 return;
3e73aa7c 569
33fef721
JH		 570 /* The recommended way to pad 64bit code is to use NOPs preceded by
571 maximally four 0x66 prefixes. Balance the size of nops. */
572 if (flag_code == CODE_64BIT)
252b5132 573 {
33fef721
JH		 574 int i;
575 int nnops = (count + 3) / 4;
576 int len = count / nnops;
577 int remains = count - nnops * len;
578 int pos = 0;
579
580 for (i = 0; i < remains; i++)
252b5132 581 {
33fef721
JH		 582 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
583 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
584 pos += len + 1;
585 }
586 for (; i < nnops; i++)
587 {
588 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
589 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
590 pos += len;
252b5132 591 }
252b5132 592 }
33fef721
JH		 593 else
594 if (flag_code == CODE_16BIT)
595 {
596 memcpy (fragP->fr_literal + fragP->fr_fix,
597 f16_patt[count - 1], count);
598 if (count > 8)
599 /* Adjust jump offset. */
600 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
601 }
602 else
603 memcpy (fragP->fr_literal + fragP->fr_fix,
604 f32_patt[count - 1], count);
605 fragP->fr_var = count;
252b5132
RH		 606}
607
252b5132
RH		 608static INLINE unsigned int
609mode_from_disp_size (t)
610 unsigned int t;
611{
3e73aa7c 612 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 613}
614
615static INLINE int
616fits_in_signed_byte (num)
847f7ad4 617 offsetT num;
252b5132
RH		 618{
619 return (num >= -128) && (num <= 127);
47926f60 620}
252b5132
RH		 621
622static INLINE int
623fits_in_unsigned_byte (num)
847f7ad4 624 offsetT num;
252b5132
RH		 625{
626 return (num & 0xff) == num;
47926f60 627}
252b5132
RH		 628
629static INLINE int
630fits_in_unsigned_word (num)
847f7ad4 631 offsetT num;
252b5132
RH		 632{
633 return (num & 0xffff) == num;
47926f60 634}
252b5132
RH		 635
636static INLINE int
637fits_in_signed_word (num)
847f7ad4 638 offsetT num;
252b5132
RH		 639{
640 return (-32768 <= num) && (num <= 32767);
47926f60 641}
3e73aa7c
JH		 642static INLINE int
643fits_in_signed_long (num)
644 offsetT num ATTRIBUTE_UNUSED;
645{
646#ifndef BFD64
647 return 1;
648#else
649 return (!(((offsetT) -1 << 31) & num)
650 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
651#endif
652} /* fits_in_signed_long() */
653static INLINE int
654fits_in_unsigned_long (num)
655 offsetT num ATTRIBUTE_UNUSED;
656{
657#ifndef BFD64
658 return 1;
659#else
660 return (num & (((offsetT) 2 << 31) - 1)) == num;
661#endif
662} /* fits_in_unsigned_long() */
252b5132
RH		 663
664static int
665smallest_imm_type (num)
847f7ad4 666 offsetT num;
252b5132 667{
a847613f 668 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 669 {
670 /* This code is disabled on the 486 because all the Imm1 forms
671 in the opcode table are slower on the i486. They're the
672 versions with the implicitly specified single-position
673 displacement, which has another syntax if you really want to
674 use that form. */
675 if (num == 1)
3e73aa7c 676 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 677 }
252b5132 678 return (fits_in_signed_byte (num)
3e73aa7c 679 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 680 : fits_in_unsigned_byte (num)
3e73aa7c 681 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 682 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 683 ? (Imm16 | Imm32 | Imm32S | Imm64)
684 : fits_in_signed_long (num)
685 ? (Imm32 | Imm32S | Imm64)
686 : fits_in_unsigned_long (num)
687 ? (Imm32 | Imm64)
688 : Imm64);
47926f60 689}
252b5132 690
847f7ad4
AM		 691static offsetT
692offset_in_range (val, size)
693 offsetT val;
694 int size;
695{
508866be 696 addressT mask;
ba2adb93 697
847f7ad4
AM		 698 switch (size)
699 {
508866be
L		 700 case 1: mask = ((addressT) 1 << 8) - 1; break;
701 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 702 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 703#ifdef BFD64
704 case 8: mask = ((addressT) 2 << 63) - 1; break;
705#endif
47926f60 706 default: abort ();
847f7ad4
AM		 707 }
708
ba2adb93 709 /* If BFD64, sign extend val. */
3e73aa7c
JH		 710 if (!use_rela_relocations)
711 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
712 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 713
47926f60 714 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 715 {
716 char buf1[40], buf2[40];
717
718 sprint_value (buf1, val);
719 sprint_value (buf2, val & mask);
720 as_warn (_("%s shortened to %s"), buf1, buf2);
721 }
722 return val & mask;
723}
724
252b5132
RH		 725/* Returns 0 if attempting to add a prefix where one from the same
726 class already exists, 1 if non rep/repne added, 2 if rep/repne
727 added. */
728static int
729add_prefix (prefix)
730 unsigned int prefix;
731{
732 int ret = 1;
733 int q;
734
29b0f896
AM		 735 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
736 && flag_code == CODE_64BIT)
3e73aa7c
JH		 737 q = REX_PREFIX;
738 else
739 switch (prefix)
740 {
741 default:
742 abort ();
743
744 case CS_PREFIX_OPCODE:
745 case DS_PREFIX_OPCODE:
746 case ES_PREFIX_OPCODE:
747 case FS_PREFIX_OPCODE:
748 case GS_PREFIX_OPCODE:
749 case SS_PREFIX_OPCODE:
750 q = SEG_PREFIX;
751 break;
252b5132 752
3e73aa7c
JH		 753 case REPNE_PREFIX_OPCODE:
754 case REPE_PREFIX_OPCODE:
755 ret = 2;
756 /* fall thru */
757 case LOCK_PREFIX_OPCODE:
758 q = LOCKREP_PREFIX;
759 break;
252b5132 760
3e73aa7c
JH		 761 case FWAIT_OPCODE:
762 q = WAIT_PREFIX;
763 break;
252b5132 764
3e73aa7c
JH		 765 case ADDR_PREFIX_OPCODE:
766 q = ADDR_PREFIX;
767 break;
252b5132 768
3e73aa7c
JH		 769 case DATA_PREFIX_OPCODE:
770 q = DATA_PREFIX;
771 break;
772 }
252b5132 773
29b0f896 774 if (i.prefix[q] != 0)
252b5132
RH		 775 {
776 as_bad (_("same type of prefix used twice"));
777 return 0;
778 }
779
780 i.prefixes += 1;
781 i.prefix[q] = prefix;
782 return ret;
783}
784
785static void
3e73aa7c 786set_code_flag (value)
e5cb08ac 787 int value;
eecb386c 788{
3e73aa7c
JH		 789 flag_code = value;
790 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
791 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
792 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
793 {
794 as_bad (_("64bit mode not supported on this CPU."));
795 }
796 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
797 {
798 as_bad (_("32bit mode not supported on this CPU."));
799 }
eecb386c
AM		 800 stackop_size = '\0';
801}
802
803static void
3e73aa7c
JH		 804set_16bit_gcc_code_flag (new_code_flag)
805 int new_code_flag;
252b5132 806{
3e73aa7c
JH		 807 flag_code = new_code_flag;
808 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
809 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 810 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 811}
812
813static void
814set_intel_syntax (syntax_flag)
eecb386c 815 int syntax_flag;
252b5132
RH		 816{
817 /* Find out if register prefixing is specified. */
818 int ask_naked_reg = 0;
819
820 SKIP_WHITESPACE ();
29b0f896 821 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 822 {
823 char *string = input_line_pointer;
824 int e = get_symbol_end ();
825
47926f60 826 if (strcmp (string, "prefix") == 0)
252b5132 827 ask_naked_reg = 1;
47926f60 828 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 829 ask_naked_reg = -1;
830 else
d0b47220 831 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 832 *input_line_pointer = e;
833 }
834 demand_empty_rest_of_line ();
c3332e24 835
252b5132
RH		 836 intel_syntax = syntax_flag;
837
838 if (ask_naked_reg == 0)
f86103b7
AM		 839 allow_naked_reg = (intel_syntax
840 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 841 else
842 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 843
844 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
845 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 846}
847
e413e4e9
AM		 848static void
849set_cpu_arch (dummy)
47926f60 850 int dummy ATTRIBUTE_UNUSED;
e413e4e9 851{
47926f60 852 SKIP_WHITESPACE ();
e413e4e9 853
29b0f896 854 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 855 {
856 char *string = input_line_pointer;
857 int e = get_symbol_end ();
858 int i;
859
860 for (i = 0; cpu_arch[i].name; i++)
861 {
862 if (strcmp (string, cpu_arch[i].name) == 0)
863 {
5c6af06e
JB		 864 if (*string != '.')
865 {
866 cpu_arch_name = cpu_arch[i].name;
867 cpu_sub_arch_name = NULL;
868 cpu_arch_flags = (cpu_arch[i].flags
869 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
870 break;
871 }
872 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
873 {
874 cpu_sub_arch_name = cpu_arch[i].name;
875 cpu_arch_flags |= cpu_arch[i].flags;
876 }
877 *input_line_pointer = e;
878 demand_empty_rest_of_line ();
879 return;
e413e4e9
AM		 880 }
881 }
882 if (!cpu_arch[i].name)
883 as_bad (_("no such architecture: `%s'"), string);
884
885 *input_line_pointer = e;
886 }
887 else
888 as_bad (_("missing cpu architecture"));
889
fddf5b5b
AM		 890 no_cond_jump_promotion = 0;
891 if (*input_line_pointer == ','
29b0f896 892 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 893 {
894 char *string = ++input_line_pointer;
895 int e = get_symbol_end ();
896
897 if (strcmp (string, "nojumps") == 0)
898 no_cond_jump_promotion = 1;
899 else if (strcmp (string, "jumps") == 0)
900 ;
901 else
902 as_bad (_("no such architecture modifier: `%s'"), string);
903
904 *input_line_pointer = e;
905 }
906
e413e4e9
AM		 907 demand_empty_rest_of_line ();
908}
909
b9d79e03
JH		 910unsigned long
911i386_mach ()
912{
913 if (!strcmp (default_arch, "x86_64"))
914 return bfd_mach_x86_64;
915 else if (!strcmp (default_arch, "i386"))
916 return bfd_mach_i386_i386;
917 else
918 as_fatal (_("Unknown architecture"));
919}
b9d79e03 920\f
252b5132
RH		 921void
922md_begin ()
923{
924 const char *hash_err;
925
47926f60 926 /* Initialize op_hash hash table. */
252b5132
RH		 927 op_hash = hash_new ();
928
929 {
29b0f896
AM		 930 const template *optab;
931 templates *core_optab;
252b5132 932
47926f60
KH		 933 /* Setup for loop. */
934 optab = i386_optab;
252b5132
RH		 935 core_optab = (templates *) xmalloc (sizeof (templates));
936 core_optab->start = optab;
937
938 while (1)
939 {
940 ++optab;
941 if (optab->name == NULL
942 || strcmp (optab->name, (optab - 1)->name) != 0)
943 {
944 /* different name --> ship out current template list;
47926f60 945 add to hash table; & begin anew. */
252b5132
RH		 946 core_optab->end = optab;
947 hash_err = hash_insert (op_hash,
948 (optab - 1)->name,
949 (PTR) core_optab);
950 if (hash_err)
951 {
252b5132
RH		 952 as_fatal (_("Internal Error: Can't hash %s: %s"),
953 (optab - 1)->name,
954 hash_err);
955 }
956 if (optab->name == NULL)
957 break;
958 core_optab = (templates *) xmalloc (sizeof (templates));
959 core_optab->start = optab;
960 }
961 }
962 }
963
47926f60 964 /* Initialize reg_hash hash table. */
252b5132
RH		 965 reg_hash = hash_new ();
966 {
29b0f896 967 const reg_entry *regtab;
252b5132
RH		 968
969 for (regtab = i386_regtab;
970 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
971 regtab++)
972 {
973 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
974 if (hash_err)
3e73aa7c
JH		 975 as_fatal (_("Internal Error: Can't hash %s: %s"),
976 regtab->reg_name,
977 hash_err);
252b5132
RH		 978 }
979 }
980
47926f60 981 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 982 {
29b0f896
AM		 983 int c;
984 char *p;
252b5132
RH		 985
986 for (c = 0; c < 256; c++)
987 {
3882b010 988 if (ISDIGIT (c))
252b5132
RH		 989 {
990 digit_chars[c] = c;
991 mnemonic_chars[c] = c;
992 register_chars[c] = c;
993 operand_chars[c] = c;
994 }
3882b010 995 else if (ISLOWER (c))
252b5132
RH		 996 {
997 mnemonic_chars[c] = c;
998 register_chars[c] = c;
999 operand_chars[c] = c;
1000 }
3882b010 1001 else if (ISUPPER (c))
252b5132 1002 {
3882b010 1003 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1004 register_chars[c] = mnemonic_chars[c];
1005 operand_chars[c] = c;
1006 }
1007
3882b010 1008 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1009 identifier_chars[c] = c;
1010 else if (c >= 128)
1011 {
1012 identifier_chars[c] = c;
1013 operand_chars[c] = c;
1014 }
1015 }
1016
1017#ifdef LEX_AT
1018 identifier_chars['@'] = '@';
32137342
NC		 1019#endif
1020#ifdef LEX_QM
1021 identifier_chars['?'] = '?';
1022 operand_chars['?'] = '?';
252b5132 1023#endif
252b5132 1024 digit_chars['-'] = '-';
791fe849 1025 mnemonic_chars['-'] = '-';
252b5132
RH		 1026 identifier_chars['_'] = '_';
1027 identifier_chars['.'] = '.';
1028
1029 for (p = operand_special_chars; *p != '\0'; p++)
1030 operand_chars[(unsigned char) *p] = *p;
1031 }
1032
1033#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1034 if (IS_ELF)
252b5132
RH		 1035 {
1036 record_alignment (text_section, 2);
1037 record_alignment (data_section, 2);
1038 record_alignment (bss_section, 2);
1039 }
1040#endif
a4447b93
RH		 1041
1042 if (flag_code == CODE_64BIT)
1043 {
1044 x86_dwarf2_return_column = 16;
1045 x86_cie_data_alignment = -8;
1046 }
1047 else
1048 {
1049 x86_dwarf2_return_column = 8;
1050 x86_cie_data_alignment = -4;
1051 }
252b5132
RH		 1052}
1053
1054void
1055i386_print_statistics (file)
1056 FILE *file;
1057{
1058 hash_print_statistics (file, "i386 opcode", op_hash);
1059 hash_print_statistics (file, "i386 register", reg_hash);
1060}
1061\f
252b5132
RH		 1062#ifdef DEBUG386
1063
ce8a8b2f 1064/* Debugging routines for md_assemble. */
252b5132
RH		 1065static void pi PARAMS ((char *, i386_insn *));
1066static void pte PARAMS ((template *));
1067static void pt PARAMS ((unsigned int));
1068static void pe PARAMS ((expressionS *));
1069static void ps PARAMS ((symbolS *));
1070
1071static void
1072pi (line, x)
1073 char *line;
1074 i386_insn *x;
1075{
09f131f2 1076 unsigned int i;
252b5132
RH		 1077
1078 fprintf (stdout, "%s: template ", line);
1079 pte (&x->tm);
09f131f2
JH		 1080 fprintf (stdout, " address: base %s index %s scale %x\n",
1081 x->base_reg ? x->base_reg->reg_name : "none",
1082 x->index_reg ? x->index_reg->reg_name : "none",
1083 x->log2_scale_factor);
1084 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1085 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1086 fprintf (stdout, " sib: base %x index %x scale %x\n",
1087 x->sib.base, x->sib.index, x->sib.scale);
1088 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1089 (x->rex & REX_MODE64) != 0,
1090 (x->rex & REX_EXTX) != 0,
1091 (x->rex & REX_EXTY) != 0,
1092 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1093 for (i = 0; i < x->operands; i++)
1094 {
1095 fprintf (stdout, " #%d: ", i + 1);
1096 pt (x->types[i]);
1097 fprintf (stdout, "\n");
1098 if (x->types[i]
3f4438ab 1099 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1100 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1101 if (x->types[i] & Imm)
520dc8e8 1102 pe (x->op[i].imms);
252b5132 1103 if (x->types[i] & Disp)
520dc8e8 1104 pe (x->op[i].disps);
252b5132
RH		 1105 }
1106}
1107
1108static void
1109pte (t)
1110 template *t;
1111{
09f131f2 1112 unsigned int i;
252b5132 1113 fprintf (stdout, " %d operands ", t->operands);
47926f60 1114 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1115 if (t->extension_opcode != None)
1116 fprintf (stdout, "ext %x ", t->extension_opcode);
1117 if (t->opcode_modifier & D)
1118 fprintf (stdout, "D");
1119 if (t->opcode_modifier & W)
1120 fprintf (stdout, "W");
1121 fprintf (stdout, "\n");
1122 for (i = 0; i < t->operands; i++)
1123 {
1124 fprintf (stdout, " #%d type ", i + 1);
1125 pt (t->operand_types[i]);
1126 fprintf (stdout, "\n");
1127 }
1128}
1129
1130static void
1131pe (e)
1132 expressionS *e;
1133{
24eab124 1134 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1135 fprintf (stdout, " add_number %ld (%lx)\n",
1136 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1137 if (e->X_add_symbol)
1138 {
1139 fprintf (stdout, " add_symbol ");
1140 ps (e->X_add_symbol);
1141 fprintf (stdout, "\n");
1142 }
1143 if (e->X_op_symbol)
1144 {
1145 fprintf (stdout, " op_symbol ");
1146 ps (e->X_op_symbol);
1147 fprintf (stdout, "\n");
1148 }
1149}
1150
1151static void
1152ps (s)
1153 symbolS *s;
1154{
1155 fprintf (stdout, "%s type %s%s",
1156 S_GET_NAME (s),
1157 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1158 segment_name (S_GET_SEGMENT (s)));
1159}
1160
1161struct type_name
1162 {
1163 unsigned int mask;
1164 char *tname;
1165 }
1166
29b0f896 1167static const type_names[] =
252b5132
RH		 1168{
1169 { Reg8, "r8" },
1170 { Reg16, "r16" },
1171 { Reg32, "r32" },
09f131f2 1172 { Reg64, "r64" },
252b5132
RH		 1173 { Imm8, "i8" },
1174 { Imm8S, "i8s" },
1175 { Imm16, "i16" },
1176 { Imm32, "i32" },
09f131f2
JH		 1177 { Imm32S, "i32s" },
1178 { Imm64, "i64" },
252b5132
RH		 1179 { Imm1, "i1" },
1180 { BaseIndex, "BaseIndex" },
1181 { Disp8, "d8" },
1182 { Disp16, "d16" },
1183 { Disp32, "d32" },
09f131f2
JH		 1184 { Disp32S, "d32s" },
1185 { Disp64, "d64" },
252b5132
RH		 1186 { InOutPortReg, "InOutPortReg" },
1187 { ShiftCount, "ShiftCount" },
1188 { Control, "control reg" },
1189 { Test, "test reg" },
1190 { Debug, "debug reg" },
1191 { FloatReg, "FReg" },
1192 { FloatAcc, "FAcc" },
1193 { SReg2, "SReg2" },
1194 { SReg3, "SReg3" },
1195 { Acc, "Acc" },
1196 { JumpAbsolute, "Jump Absolute" },
1197 { RegMMX, "rMMX" },
3f4438ab 1198 { RegXMM, "rXMM" },
252b5132
RH		 1199 { EsSeg, "es" },
1200 { 0, "" }
1201};
1202
1203static void
1204pt (t)
1205 unsigned int t;
1206{
29b0f896 1207 const struct type_name *ty;
252b5132 1208
09f131f2
JH		 1209 for (ty = type_names; ty->mask; ty++)
1210 if (t & ty->mask)
1211 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1212 fflush (stdout);
1213}
1214
1215#endif /* DEBUG386 */
1216\f
252b5132 1217static bfd_reloc_code_real_type
3956db08
JB		 1218reloc (unsigned int size,
1219 int pcrel,
1220 int sign,
1221 bfd_reloc_code_real_type other)
252b5132 1222{
47926f60 1223 if (other != NO_RELOC)
3956db08
JB		 1224 {
1225 reloc_howto_type *reloc;
1226
1227 if (size == 8)
1228 switch (other)
1229 {
1230 case BFD_RELOC_X86_64_TPOFF32:
1231 other = BFD_RELOC_X86_64_TPOFF64;
1232 break;
1233 case BFD_RELOC_X86_64_DTPOFF32:
1234 other = BFD_RELOC_X86_64_DTPOFF64;
1235 break;
1236 default:
1237 break;
1238 }
e05278af
JB		 1239
1240 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1241 if (size == 4 && flag_code != CODE_64BIT)
1242 sign = -1;
1243
3956db08
JB		 1244 reloc = bfd_reloc_type_lookup (stdoutput, other);
1245 if (!reloc)
1246 as_bad (_("unknown relocation (%u)"), other);
1247 else if (size != bfd_get_reloc_size (reloc))
1248 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1249 bfd_get_reloc_size (reloc),
1250 size);
1251 else if (pcrel && !reloc->pc_relative)
1252 as_bad (_("non-pc-relative relocation for pc-relative field"));
1253 else if ((reloc->complain_on_overflow == complain_overflow_signed
1254 && !sign)
1255 || (reloc->complain_on_overflow == complain_overflow_unsigned
1256 && sign > 0))
1257 as_bad (_("relocated field and relocation type differ in signedness"));
1258 else
1259 return other;
1260 return NO_RELOC;
1261 }
252b5132
RH		 1262
1263 if (pcrel)
1264 {
3e73aa7c 1265 if (!sign)
3956db08 1266 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1267 switch (size)
1268 {
1269 case 1: return BFD_RELOC_8_PCREL;
1270 case 2: return BFD_RELOC_16_PCREL;
1271 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1272 case 8: return BFD_RELOC_64_PCREL;
252b5132 1273 }
3956db08 1274 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1275 }
1276 else
1277 {
3956db08 1278 if (sign > 0)
e5cb08ac 1279 switch (size)
3e73aa7c
JH		 1280 {
1281 case 4: return BFD_RELOC_X86_64_32S;
1282 }
1283 else
1284 switch (size)
1285 {
1286 case 1: return BFD_RELOC_8;
1287 case 2: return BFD_RELOC_16;
1288 case 4: return BFD_RELOC_32;
1289 case 8: return BFD_RELOC_64;
1290 }
3956db08
JB		 1291 as_bad (_("cannot do %s %u byte relocation"),
1292 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1293 }
1294
bfb32b52 1295 abort ();
252b5132
RH		 1296 return BFD_RELOC_NONE;
1297}
1298
47926f60
KH		 1299/* Here we decide which fixups can be adjusted to make them relative to
1300 the beginning of the section instead of the symbol. Basically we need
1301 to make sure that the dynamic relocations are done correctly, so in
1302 some cases we force the original symbol to be used. */
1303
252b5132 1304int
c0c949c7 1305tc_i386_fix_adjustable (fixP)
31312f95 1306 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1307{
6d249963 1308#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1309 if (!IS_ELF)
31312f95
AM		 1310 return 1;
1311
a161fe53
AM		 1312 /* Don't adjust pc-relative references to merge sections in 64-bit
1313 mode. */
1314 if (use_rela_relocations
1315 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1316 && fixP->fx_pcrel)
252b5132 1317 return 0;
31312f95 1318
8d01d9a9
AJ		 1319 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1320 and changed later by validate_fix. */
1321 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1322 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1323 return 0;
1324
ce8a8b2f 1325 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1326 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1327 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1328 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1329 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1330 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1331 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1332 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1333 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1334 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1335 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1336 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1337 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1338 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1339 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1340 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1341 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1342 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1343 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1344 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1345 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1346 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1347 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
252b5132
RH		 1348 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1349 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1350 return 0;
31312f95 1351#endif
252b5132
RH		 1352 return 1;
1353}
252b5132 1354
29b0f896 1355static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1356
1357static int
252b5132 1358intel_float_operand (mnemonic)
29b0f896 1359 const char *mnemonic;
252b5132 1360{
9306ca4a
JB		 1361 /* Note that the value returned is meaningful only for opcodes with (memory)
1362 operands, hence the code here is free to improperly handle opcodes that
1363 have no operands (for better performance and smaller code). */
1364
1365 if (mnemonic[0] != 'f')
1366 return 0; /* non-math */
1367
1368 switch (mnemonic[1])
1369 {
1370 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1371 the fs segment override prefix not currently handled because no
1372 call path can make opcodes without operands get here */
1373 case 'i':
1374 return 2 /* integer op */;
1375 case 'l':
1376 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1377 return 3; /* fldcw/fldenv */
1378 break;
1379 case 'n':
1380 if (mnemonic[2] != 'o' /* fnop */)
1381 return 3; /* non-waiting control op */
1382 break;
1383 case 'r':
1384 if (mnemonic[2] == 's')
1385 return 3; /* frstor/frstpm */
1386 break;
1387 case 's':
1388 if (mnemonic[2] == 'a')
1389 return 3; /* fsave */
1390 if (mnemonic[2] == 't')
1391 {
1392 switch (mnemonic[3])
1393 {
1394 case 'c': /* fstcw */
1395 case 'd': /* fstdw */
1396 case 'e': /* fstenv */
1397 case 's': /* fsts[gw] */
1398 return 3;
1399 }
1400 }
1401 break;
1402 case 'x':
1403 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1404 return 0; /* fxsave/fxrstor are not really math ops */
1405 break;
1406 }
252b5132 1407
9306ca4a 1408 return 1;
252b5132
RH		 1409}
1410
1411/* This is the guts of the machine-dependent assembler. LINE points to a
1412 machine dependent instruction. This function is supposed to emit
1413 the frags/bytes it assembles to. */
1414
1415void
1416md_assemble (line)
1417 char *line;
1418{
252b5132 1419 int j;
252b5132
RH		 1420 char mnemonic[MAX_MNEM_SIZE];
1421
47926f60 1422 /* Initialize globals. */
252b5132
RH		 1423 memset (&i, '\0', sizeof (i));
1424 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1425 i.reloc[j] = NO_RELOC;
252b5132
RH		 1426 memset (disp_expressions, '\0', sizeof (disp_expressions));
1427 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1428 save_stack_p = save_stack;
252b5132
RH		 1429
1430 /* First parse an instruction mnemonic & call i386_operand for the operands.
1431 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1432 start of a (possibly prefixed) mnemonic. */
252b5132 1433
29b0f896
AM		 1434 line = parse_insn (line, mnemonic);
1435 if (line == NULL)
1436 return;
252b5132 1437
29b0f896
AM		 1438 line = parse_operands (line, mnemonic);
1439 if (line == NULL)
1440 return;
252b5132 1441
29b0f896
AM		 1442 /* Now we've parsed the mnemonic into a set of templates, and have the
1443 operands at hand. */
1444
1445 /* All intel opcodes have reversed operands except for "bound" and
1446 "enter". We also don't reverse intersegment "jmp" and "call"
1447 instructions with 2 immediate operands so that the immediate segment
1448 precedes the offset, as it does when in AT&T mode. "enter" and the
1449 intersegment "jmp" and "call" instructions are the only ones that
1450 have two immediate operands. */
1451 if (intel_syntax && i.operands > 1
1452 && (strcmp (mnemonic, "bound") != 0)
30123838 1453 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1454 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1455 swap_operands ();
1456
1457 if (i.imm_operands)
1458 optimize_imm ();
1459
b300c311
L		 1460 /* Don't optimize displacement for movabs since it only takes 64bit
1461 displacement. */
1462 if (i.disp_operands
1463 && (flag_code != CODE_64BIT
1464 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1465 optimize_disp ();
1466
1467 /* Next, we find a template that matches the given insn,
1468 making sure the overlap of the given operands types is consistent
1469 with the template operand types. */
252b5132 1470
29b0f896
AM		 1471 if (!match_template ())
1472 return;
252b5132 1473
cd61ebfe
AM		 1474 if (intel_syntax)
1475 {
1476 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1477 if (SYSV386_COMPAT
1478 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1479 i.tm.base_opcode ^= FloatR;
1480
1481 /* Zap movzx and movsx suffix. The suffix may have been set from
1482 "word ptr" or "byte ptr" on the source operand, but we'll use
1483 the suffix later to choose the destination register. */
1484 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1485 {
1486 if (i.reg_operands < 2
1487 && !i.suffix
1488 && (~i.tm.opcode_modifier
1489 & (No_bSuf
1490 | No_wSuf
1491 | No_lSuf
1492 | No_sSuf
1493 | No_xSuf
1494 | No_qSuf)))
1495 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1496
1497 i.suffix = 0;
1498 }
cd61ebfe 1499 }
24eab124 1500
29b0f896
AM		 1501 if (i.tm.opcode_modifier & FWait)
1502 if (!add_prefix (FWAIT_OPCODE))
1503 return;
252b5132 1504
29b0f896
AM		 1505 /* Check string instruction segment overrides. */
1506 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1507 {
1508 if (!check_string ())
5dd0794d 1509 return;
29b0f896 1510 }
5dd0794d 1511
29b0f896
AM		 1512 if (!process_suffix ())
1513 return;
e413e4e9 1514
29b0f896
AM		 1515 /* Make still unresolved immediate matches conform to size of immediate
1516 given in i.suffix. */
1517 if (!finalize_imm ())
1518 return;
252b5132 1519
29b0f896
AM		 1520 if (i.types[0] & Imm1)
1521 i.imm_operands = 0; /* kludge for shift insns. */
1522 if (i.types[0] & ImplicitRegister)
1523 i.reg_operands--;
1524 if (i.types[1] & ImplicitRegister)
1525 i.reg_operands--;
1526 if (i.types[2] & ImplicitRegister)
1527 i.reg_operands--;
252b5132 1528
29b0f896
AM		 1529 if (i.tm.opcode_modifier & ImmExt)
1530 {
02fc3089
L		 1531 expressionS *exp;
1532
ca164297
L		 1533 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1534 {
67c1ffbe 1535 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1536 operands with an opcode suffix which is coded in the same
1537 place as an 8-bit immediate field would be. Here we check
1538 those operands and remove them afterwards. */
1539 unsigned int x;
1540
a4622f40 1541 for (x = 0; x < i.operands; x++)
ca164297
L		 1542 if (i.op[x].regs->reg_num != x)
1543 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1544 i.op[x].regs->reg_name, x + 1, i.tm.name);
1545 i.operands = 0;
1546 }
1547
29b0f896
AM		 1548 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1549 opcode suffix which is coded in the same place as an 8-bit
1550 immediate field would be. Here we fake an 8-bit immediate
1551 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1552
29b0f896 1553 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1554
29b0f896
AM		 1555 exp = &im_expressions[i.imm_operands++];
1556 i.op[i.operands].imms = exp;
1557 i.types[i.operands++] = Imm8;
1558 exp->X_op = O_constant;
1559 exp->X_add_number = i.tm.extension_opcode;
1560 i.tm.extension_opcode = None;
1561 }
252b5132 1562
29b0f896
AM		 1563 /* For insns with operands there are more diddles to do to the opcode. */
1564 if (i.operands)
1565 {
1566 if (!process_operands ())
1567 return;
1568 }
1569 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1570 {
1571 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1572 as_warn (_("translating to `%sp'"), i.tm.name);
1573 }
252b5132 1574
29b0f896
AM		 1575 /* Handle conversion of 'int $3' --> special int3 insn. */
1576 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1577 {
1578 i.tm.base_opcode = INT3_OPCODE;
1579 i.imm_operands = 0;
1580 }
252b5132 1581
29b0f896
AM		 1582 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1583 && i.op[0].disps->X_op == O_constant)
1584 {
1585 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1586 the absolute address given by the constant. Since ix86 jumps and
1587 calls are pc relative, we need to generate a reloc. */
1588 i.op[0].disps->X_add_symbol = &abs_symbol;
1589 i.op[0].disps->X_op = O_symbol;
1590 }
252b5132 1591
29b0f896
AM		 1592 if ((i.tm.opcode_modifier & Rex64) != 0)
1593 i.rex |= REX_MODE64;
252b5132 1594
29b0f896
AM		 1595 /* For 8 bit registers we need an empty rex prefix. Also if the
1596 instruction already has a prefix, we need to convert old
1597 registers to new ones. */
773f551c 1598
29b0f896
AM		 1599 if (((i.types[0] & Reg8) != 0
1600 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1601 || ((i.types[1] & Reg8) != 0
1602 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1603 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1604 && i.rex != 0))
1605 {
1606 int x;
726c5dcd 1607
29b0f896
AM		 1608 i.rex |= REX_OPCODE;
1609 for (x = 0; x < 2; x++)
1610 {
1611 /* Look for 8 bit operand that uses old registers. */
1612 if ((i.types[x] & Reg8) != 0
1613 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1614 {
29b0f896
AM		 1615 /* In case it is "hi" register, give up. */
1616 if (i.op[x].regs->reg_num > 3)
0477af35 1617 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1618 i.op[x].regs->reg_name);
773f551c 1619
29b0f896
AM		 1620 /* Otherwise it is equivalent to the extended register.
1621 Since the encoding doesn't change this is merely
1622 cosmetic cleanup for debug output. */
1623
1624 i.op[x].regs = i.op[x].regs + 8;
773f551c 1625 }
29b0f896
AM		 1626 }
1627 }
773f551c 1628
29b0f896
AM		 1629 if (i.rex != 0)
1630 add_prefix (REX_OPCODE | i.rex);
1631
1632 /* We are ready to output the insn. */
1633 output_insn ();
1634}
1635
1636static char *
1637parse_insn (line, mnemonic)
1638 char *line;
1639 char *mnemonic;
1640{
1641 char *l = line;
1642 char *token_start = l;
1643 char *mnem_p;
5c6af06e
JB		 1644 int supported;
1645 const template *t;
29b0f896
AM		 1646
1647 /* Non-zero if we found a prefix only acceptable with string insns. */
1648 const char *expecting_string_instruction = NULL;
45288df1 1649
29b0f896
AM		 1650 while (1)
1651 {
1652 mnem_p = mnemonic;
1653 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1654 {
1655 mnem_p++;
1656 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1657 {
29b0f896
AM		 1658 as_bad (_("no such instruction: `%s'"), token_start);
1659 return NULL;
1660 }
1661 l++;
1662 }
1663 if (!is_space_char (*l)
1664 && *l != END_OF_INSN
e44823cf
JB		 1665 && (intel_syntax
1666 || (*l != PREFIX_SEPARATOR
1667 && *l != ',')))
29b0f896
AM		 1668 {
1669 as_bad (_("invalid character %s in mnemonic"),
1670 output_invalid (*l));
1671 return NULL;
1672 }
1673 if (token_start == l)
1674 {
e44823cf 1675 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1676 as_bad (_("expecting prefix; got nothing"));
1677 else
1678 as_bad (_("expecting mnemonic; got nothing"));
1679 return NULL;
1680 }
45288df1 1681
29b0f896
AM		 1682 /* Look up instruction (or prefix) via hash table. */
1683 current_templates = hash_find (op_hash, mnemonic);
47926f60 1684
29b0f896
AM		 1685 if (*l != END_OF_INSN
1686 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1687 && current_templates
1688 && (current_templates->start->opcode_modifier & IsPrefix))
1689 {
2dd88dca
JB		 1690 if (current_templates->start->cpu_flags
1691 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1692 {
1693 as_bad ((flag_code != CODE_64BIT
1694 ? _("`%s' is only supported in 64-bit mode")
1695 : _("`%s' is not supported in 64-bit mode")),
1696 current_templates->start->name);
1697 return NULL;
1698 }
29b0f896
AM		 1699 /* If we are in 16-bit mode, do not allow addr16 or data16.
1700 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1701 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1702 && flag_code != CODE_64BIT
1703 && (((current_templates->start->opcode_modifier & Size32) != 0)
1704 ^ (flag_code == CODE_16BIT)))
1705 {
1706 as_bad (_("redundant %s prefix"),
1707 current_templates->start->name);
1708 return NULL;
45288df1 1709 }
29b0f896
AM		 1710 /* Add prefix, checking for repeated prefixes. */
1711 switch (add_prefix (current_templates->start->base_opcode))
1712 {
1713 case 0:
1714 return NULL;
1715 case 2:
1716 expecting_string_instruction = current_templates->start->name;
1717 break;
1718 }
1719 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1720 token_start = ++l;
1721 }
1722 else
1723 break;
1724 }
45288df1 1725
29b0f896
AM		 1726 if (!current_templates)
1727 {
1728 /* See if we can get a match by trimming off a suffix. */
1729 switch (mnem_p[-1])
1730 {
1731 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1732 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1733 i.suffix = SHORT_MNEM_SUFFIX;
1734 else
29b0f896
AM		 1735 case BYTE_MNEM_SUFFIX:
1736 case QWORD_MNEM_SUFFIX:
1737 i.suffix = mnem_p[-1];
1738 mnem_p[-1] = '\0';
1739 current_templates = hash_find (op_hash, mnemonic);
1740 break;
1741 case SHORT_MNEM_SUFFIX:
1742 case LONG_MNEM_SUFFIX:
1743 if (!intel_syntax)
1744 {
1745 i.suffix = mnem_p[-1];
1746 mnem_p[-1] = '\0';
1747 current_templates = hash_find (op_hash, mnemonic);
1748 }
1749 break;
252b5132 1750
29b0f896
AM		 1751 /* Intel Syntax. */
1752 case 'd':
1753 if (intel_syntax)
1754 {
9306ca4a 1755 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1756 i.suffix = SHORT_MNEM_SUFFIX;
1757 else
1758 i.suffix = LONG_MNEM_SUFFIX;
1759 mnem_p[-1] = '\0';
1760 current_templates = hash_find (op_hash, mnemonic);
1761 }
1762 break;
1763 }
1764 if (!current_templates)
1765 {
1766 as_bad (_("no such instruction: `%s'"), token_start);
1767 return NULL;
1768 }
1769 }
252b5132 1770
29b0f896
AM		 1771 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1772 {
1773 /* Check for a branch hint. We allow ",pt" and ",pn" for
1774 predict taken and predict not taken respectively.
1775 I'm not sure that branch hints actually do anything on loop
1776 and jcxz insns (JumpByte) for current Pentium4 chips. They
1777 may work in the future and it doesn't hurt to accept them
1778 now. */
1779 if (l[0] == ',' && l[1] == 'p')
1780 {
1781 if (l[2] == 't')
1782 {
1783 if (!add_prefix (DS_PREFIX_OPCODE))
1784 return NULL;
1785 l += 3;
1786 }
1787 else if (l[2] == 'n')
1788 {
1789 if (!add_prefix (CS_PREFIX_OPCODE))
1790 return NULL;
1791 l += 3;
1792 }
1793 }
1794 }
1795 /* Any other comma loses. */
1796 if (*l == ',')
1797 {
1798 as_bad (_("invalid character %s in mnemonic"),
1799 output_invalid (*l));
1800 return NULL;
1801 }
252b5132 1802
29b0f896 1803 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1804 supported = 0;
1805 for (t = current_templates->start; t < current_templates->end; ++t)
1806 {
1807 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1808 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1809 supported |= 1;
1810 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1811 supported |= 2;
1812 }
1813 if (!(supported & 2))
1814 {
1815 as_bad (flag_code == CODE_64BIT
1816 ? _("`%s' is not supported in 64-bit mode")
1817 : _("`%s' is only supported in 64-bit mode"),
1818 current_templates->start->name);
1819 return NULL;
1820 }
1821 if (!(supported & 1))
29b0f896 1822 {
5c6af06e
JB		 1823 as_warn (_("`%s' is not supported on `%s%s'"),
1824 current_templates->start->name,
1825 cpu_arch_name,
1826 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1827 }
1828 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1829 {
1830 as_warn (_("use .code16 to ensure correct addressing mode"));
1831 }
252b5132 1832
29b0f896 1833 /* Check for rep/repne without a string instruction. */
f41bbced 1834 if (expecting_string_instruction)
29b0f896 1835 {
f41bbced
JB		 1836 static templates override;
1837
1838 for (t = current_templates->start; t < current_templates->end; ++t)
1839 if (t->opcode_modifier & IsString)
1840 break;
1841 if (t >= current_templates->end)
1842 {
1843 as_bad (_("expecting string instruction after `%s'"),
1844 expecting_string_instruction);
1845 return NULL;
1846 }
1847 for (override.start = t; t < current_templates->end; ++t)
1848 if (!(t->opcode_modifier & IsString))
1849 break;
1850 override.end = t;
1851 current_templates = &override;
29b0f896 1852 }
252b5132 1853
29b0f896
AM		 1854 return l;
1855}
252b5132 1856
29b0f896
AM		 1857static char *
1858parse_operands (l, mnemonic)
1859 char *l;
1860 const char *mnemonic;
1861{
1862 char *token_start;
3138f287 1863
29b0f896
AM		 1864 /* 1 if operand is pending after ','. */
1865 unsigned int expecting_operand = 0;
252b5132 1866
29b0f896
AM		 1867 /* Non-zero if operand parens not balanced. */
1868 unsigned int paren_not_balanced;
1869
1870 while (*l != END_OF_INSN)
1871 {
1872 /* Skip optional white space before operand. */
1873 if (is_space_char (*l))
1874 ++l;
1875 if (!is_operand_char (*l) && *l != END_OF_INSN)
1876 {
1877 as_bad (_("invalid character %s before operand %d"),
1878 output_invalid (*l),
1879 i.operands + 1);
1880 return NULL;
1881 }
1882 token_start = l; /* after white space */
1883 paren_not_balanced = 0;
1884 while (paren_not_balanced || *l != ',')
1885 {
1886 if (*l == END_OF_INSN)
1887 {
1888 if (paren_not_balanced)
1889 {
1890 if (!intel_syntax)
1891 as_bad (_("unbalanced parenthesis in operand %d."),
1892 i.operands + 1);
1893 else
1894 as_bad (_("unbalanced brackets in operand %d."),
1895 i.operands + 1);
1896 return NULL;
1897 }
1898 else
1899 break; /* we are done */
1900 }
1901 else if (!is_operand_char (*l) && !is_space_char (*l))
1902 {
1903 as_bad (_("invalid character %s in operand %d"),
1904 output_invalid (*l),
1905 i.operands + 1);
1906 return NULL;
1907 }
1908 if (!intel_syntax)
1909 {
1910 if (*l == '(')
1911 ++paren_not_balanced;
1912 if (*l == ')')
1913 --paren_not_balanced;
1914 }
1915 else
1916 {
1917 if (*l == '[')
1918 ++paren_not_balanced;
1919 if (*l == ']')
1920 --paren_not_balanced;
1921 }
1922 l++;
1923 }
1924 if (l != token_start)
1925 { /* Yes, we've read in another operand. */
1926 unsigned int operand_ok;
1927 this_operand = i.operands++;
1928 if (i.operands > MAX_OPERANDS)
1929 {
1930 as_bad (_("spurious operands; (%d operands/instruction max)"),
1931 MAX_OPERANDS);
1932 return NULL;
1933 }
1934 /* Now parse operand adding info to 'i' as we go along. */
1935 END_STRING_AND_SAVE (l);
1936
1937 if (intel_syntax)
1938 operand_ok =
1939 i386_intel_operand (token_start,
1940 intel_float_operand (mnemonic));
1941 else
1942 operand_ok = i386_operand (token_start);
1943
1944 RESTORE_END_STRING (l);
1945 if (!operand_ok)
1946 return NULL;
1947 }
1948 else
1949 {
1950 if (expecting_operand)
1951 {
1952 expecting_operand_after_comma:
1953 as_bad (_("expecting operand after ','; got nothing"));
1954 return NULL;
1955 }
1956 if (*l == ',')
1957 {
1958 as_bad (_("expecting operand before ','; got nothing"));
1959 return NULL;
1960 }
1961 }
7f3f1ea2 1962
29b0f896
AM		 1963 /* Now *l must be either ',' or END_OF_INSN. */
1964 if (*l == ',')
1965 {
1966 if (*++l == END_OF_INSN)
1967 {
1968 /* Just skip it, if it's \n complain. */
1969 goto expecting_operand_after_comma;
1970 }
1971 expecting_operand = 1;
1972 }
1973 }
1974 return l;
1975}
7f3f1ea2 1976
29b0f896
AM		 1977static void
1978swap_operands ()
1979{
1980 union i386_op temp_op;
1981 unsigned int temp_type;
f86103b7 1982 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1983 int xchg1 = 0;
1984 int xchg2 = 0;
252b5132 1985
29b0f896
AM		 1986 if (i.operands == 2)
1987 {
1988 xchg1 = 0;
1989 xchg2 = 1;
1990 }
1991 else if (i.operands == 3)
1992 {
1993 xchg1 = 0;
1994 xchg2 = 2;
1995 }
1996 temp_type = i.types[xchg2];
1997 i.types[xchg2] = i.types[xchg1];
1998 i.types[xchg1] = temp_type;
1999 temp_op = i.op[xchg2];
2000 i.op[xchg2] = i.op[xchg1];
2001 i.op[xchg1] = temp_op;
2002 temp_reloc = i.reloc[xchg2];
2003 i.reloc[xchg2] = i.reloc[xchg1];
2004 i.reloc[xchg1] = temp_reloc;
2005
2006 if (i.mem_operands == 2)
2007 {
2008 const seg_entry *temp_seg;
2009 temp_seg = i.seg[0];
2010 i.seg[0] = i.seg[1];
2011 i.seg[1] = temp_seg;
2012 }
2013}
252b5132 2014
29b0f896
AM		 2015/* Try to ensure constant immediates are represented in the smallest
2016 opcode possible. */
2017static void
2018optimize_imm ()
2019{
2020 char guess_suffix = 0;
2021 int op;
252b5132 2022
29b0f896
AM		 2023 if (i.suffix)
2024 guess_suffix = i.suffix;
2025 else if (i.reg_operands)
2026 {
2027 /* Figure out a suffix from the last register operand specified.
2028 We can't do this properly yet, ie. excluding InOutPortReg,
2029 but the following works for instructions with immediates.
2030 In any case, we can't set i.suffix yet. */
2031 for (op = i.operands; --op >= 0;)
2032 if (i.types[op] & Reg)
252b5132 2033 {
29b0f896
AM		 2034 if (i.types[op] & Reg8)
2035 guess_suffix = BYTE_MNEM_SUFFIX;
2036 else if (i.types[op] & Reg16)
2037 guess_suffix = WORD_MNEM_SUFFIX;
2038 else if (i.types[op] & Reg32)
2039 guess_suffix = LONG_MNEM_SUFFIX;
2040 else if (i.types[op] & Reg64)
2041 guess_suffix = QWORD_MNEM_SUFFIX;
2042 break;
252b5132 2043 }
29b0f896
AM		 2044 }
2045 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2046 guess_suffix = WORD_MNEM_SUFFIX;
2047
2048 for (op = i.operands; --op >= 0;)
2049 if (i.types[op] & Imm)
2050 {
2051 switch (i.op[op].imms->X_op)
252b5132 2052 {
29b0f896
AM		 2053 case O_constant:
2054 /* If a suffix is given, this operand may be shortened. */
2055 switch (guess_suffix)
252b5132 2056 {
29b0f896
AM		 2057 case LONG_MNEM_SUFFIX:
2058 i.types[op] |= Imm32 | Imm64;
2059 break;
2060 case WORD_MNEM_SUFFIX:
2061 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2062 break;
2063 case BYTE_MNEM_SUFFIX:
2064 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2065 break;
252b5132 2066 }
252b5132 2067
29b0f896
AM		 2068 /* If this operand is at most 16 bits, convert it
2069 to a signed 16 bit number before trying to see
2070 whether it will fit in an even smaller size.
2071 This allows a 16-bit operand such as $0xffe0 to
2072 be recognised as within Imm8S range. */
2073 if ((i.types[op] & Imm16)
2074 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2075 {
29b0f896
AM		 2076 i.op[op].imms->X_add_number =
2077 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2078 }
2079 if ((i.types[op] & Imm32)
2080 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2081 == 0))
2082 {
2083 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2084 ^ ((offsetT) 1 << 31))
2085 - ((offsetT) 1 << 31));
2086 }
2087 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2088
29b0f896
AM		 2089 /* We must avoid matching of Imm32 templates when 64bit
2090 only immediate is available. */
2091 if (guess_suffix == QWORD_MNEM_SUFFIX)
2092 i.types[op] &= ~Imm32;
2093 break;
252b5132 2094
29b0f896
AM		 2095 case O_absent:
2096 case O_register:
2097 abort ();
2098
2099 /* Symbols and expressions. */
2100 default:
9cd96992
JB		 2101 /* Convert symbolic operand to proper sizes for matching, but don't
2102 prevent matching a set of insns that only supports sizes other
2103 than those matching the insn suffix. */
2104 {
2105 unsigned int mask, allowed = 0;
2106 const template *t;
2107
2108 for (t = current_templates->start; t < current_templates->end; ++t)
2109 allowed |= t->operand_types[op];
2110 switch (guess_suffix)
2111 {
2112 case QWORD_MNEM_SUFFIX:
2113 mask = Imm64 | Imm32S;
2114 break;
2115 case LONG_MNEM_SUFFIX:
2116 mask = Imm32;
2117 break;
2118 case WORD_MNEM_SUFFIX:
2119 mask = Imm16;
2120 break;
2121 case BYTE_MNEM_SUFFIX:
2122 mask = Imm8;
2123 break;
2124 default:
2125 mask = 0;
2126 break;
2127 }
2128 if (mask & allowed)
2129 i.types[op] &= mask;
2130 }
29b0f896 2131 break;
252b5132 2132 }
29b0f896
AM		 2133 }
2134}
47926f60 2135
29b0f896
AM		 2136/* Try to use the smallest displacement type too. */
2137static void
2138optimize_disp ()
2139{
2140 int op;
3e73aa7c 2141
29b0f896 2142 for (op = i.operands; --op >= 0;)
b300c311 2143 if (i.types[op] & Disp)
252b5132 2144 {
b300c311 2145 if (i.op[op].disps->X_op == O_constant)
252b5132 2146 {
b300c311 2147 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2148
b300c311
L		 2149 if ((i.types[op] & Disp16)
2150 && (disp & ~(offsetT) 0xffff) == 0)
2151 {
2152 /* If this operand is at most 16 bits, convert
2153 to a signed 16 bit number and don't use 64bit
2154 displacement. */
2155 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2156 i.types[op] &= ~Disp64;
2157 }
2158 if ((i.types[op] & Disp32)
2159 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2160 {
2161 /* If this operand is at most 32 bits, convert
2162 to a signed 32 bit number and don't use 64bit
2163 displacement. */
2164 disp &= (((offsetT) 2 << 31) - 1);
2165 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2166 i.types[op] &= ~Disp64;
2167 }
2168 if (!disp && (i.types[op] & BaseIndex))
2169 {
2170 i.types[op] &= ~Disp;
2171 i.op[op].disps = 0;
2172 i.disp_operands--;
2173 }
2174 else if (flag_code == CODE_64BIT)
2175 {
2176 if (fits_in_signed_long (disp))
28a9d8f5
L		 2177 {
2178 i.types[op] &= ~Disp64;
2179 i.types[op] |= Disp32S;
2180 }
b300c311
L		 2181 if (fits_in_unsigned_long (disp))
2182 i.types[op] |= Disp32;
2183 }
2184 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2185 && fits_in_signed_byte (disp))
2186 i.types[op] |= Disp8;
252b5132 2187 }
b300c311
L		 2188 else
2189 /* We only support 64bit displacement on constants. */
2190 i.types[op] &= ~Disp64;
252b5132 2191 }
29b0f896
AM		 2192}
2193
2194static int
2195match_template ()
2196{
2197 /* Points to template once we've found it. */
2198 const template *t;
2199 unsigned int overlap0, overlap1, overlap2;
2200 unsigned int found_reverse_match;
2201 int suffix_check;
2202
2203#define MATCH(overlap, given, template) \
2204 ((overlap & ~JumpAbsolute) \
2205 && (((given) & (BaseIndex | JumpAbsolute)) \
2206 == ((overlap) & (BaseIndex | JumpAbsolute))))
2207
2208 /* If given types r0 and r1 are registers they must be of the same type
2209 unless the expected operand type register overlap is null.
2210 Note that Acc in a template matches every size of reg. */
2211#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2212 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2213 || ((g0) & Reg) == ((g1) & Reg) \
2214 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2215
2216 overlap0 = 0;
2217 overlap1 = 0;
2218 overlap2 = 0;
2219 found_reverse_match = 0;
2220 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2221 ? No_bSuf
2222 : (i.suffix == WORD_MNEM_SUFFIX
2223 ? No_wSuf
2224 : (i.suffix == SHORT_MNEM_SUFFIX
2225 ? No_sSuf
2226 : (i.suffix == LONG_MNEM_SUFFIX
2227 ? No_lSuf
2228 : (i.suffix == QWORD_MNEM_SUFFIX
2229 ? No_qSuf
2230 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2231 ? No_xSuf : 0))))));
2232
20f0a1fc
NC		 2233 t = current_templates->start;
2234 if (i.suffix == QWORD_MNEM_SUFFIX
2235 && flag_code != CODE_64BIT
9306ca4a
JB		 2236 && (intel_syntax
2237 ? !(t->opcode_modifier & IgnoreSize)
2238 && !intel_float_operand (t->name)
2239 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2240 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2241 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2242 && (t->base_opcode != 0x0fc7
2243 || t->extension_opcode != 1 /* cmpxchg8b */))
2244 t = current_templates->end;
2245 for (; t < current_templates->end; t++)
29b0f896
AM		 2246 {
2247 /* Must have right number of operands. */
2248 if (i.operands != t->operands)
2249 continue;
2250
2251 /* Check the suffix, except for some instructions in intel mode. */
2252 if ((t->opcode_modifier & suffix_check)
2253 && !(intel_syntax
9306ca4a 2254 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2255 continue;
2256
2257 /* Do not verify operands when there are none. */
2258 else if (!t->operands)
2259 {
2260 if (t->cpu_flags & ~cpu_arch_flags)
2261 continue;
2262 /* We've found a match; break out of loop. */
2263 break;
2264 }
252b5132 2265
29b0f896
AM		 2266 overlap0 = i.types[0] & t->operand_types[0];
2267 switch (t->operands)
2268 {
2269 case 1:
2270 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2271 continue;
2272 break;
2273 case 2:
2274 case 3:
2275 overlap1 = i.types[1] & t->operand_types[1];
2276 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2277 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2278 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2279 t->operand_types[0],
2280 overlap1, i.types[1],
2281 t->operand_types[1]))
2282 {
2283 /* Check if other direction is valid ... */
2284 if ((t->opcode_modifier & (D | FloatD)) == 0)
2285 continue;
2286
2287 /* Try reversing direction of operands. */
2288 overlap0 = i.types[0] & t->operand_types[1];
2289 overlap1 = i.types[1] & t->operand_types[0];
2290 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2291 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2292 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2293 t->operand_types[1],
2294 overlap1, i.types[1],
2295 t->operand_types[0]))
2296 {
2297 /* Does not match either direction. */
2298 continue;
2299 }
2300 /* found_reverse_match holds which of D or FloatDR
2301 we've found. */
2302 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2303 }
2304 /* Found a forward 2 operand match here. */
2305 else if (t->operands == 3)
2306 {
2307 /* Here we make use of the fact that there are no
2308 reverse match 3 operand instructions, and all 3
2309 operand instructions only need to be checked for
2310 register consistency between operands 2 and 3. */
2311 overlap2 = i.types[2] & t->operand_types[2];
2312 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2313 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2314 t->operand_types[1],
2315 overlap2, i.types[2],
2316 t->operand_types[2]))
2317
2318 continue;
2319 }
2320 /* Found either forward/reverse 2 or 3 operand match here:
2321 slip through to break. */
2322 }
2323 if (t->cpu_flags & ~cpu_arch_flags)
2324 {
2325 found_reverse_match = 0;
2326 continue;
2327 }
2328 /* We've found a match; break out of loop. */
2329 break;
2330 }
2331
2332 if (t == current_templates->end)
2333 {
2334 /* We found no match. */
2335 as_bad (_("suffix or operands invalid for `%s'"),
2336 current_templates->start->name);
2337 return 0;
2338 }
252b5132 2339
29b0f896
AM		 2340 if (!quiet_warnings)
2341 {
2342 if (!intel_syntax
2343 && ((i.types[0] & JumpAbsolute)
2344 != (t->operand_types[0] & JumpAbsolute)))
2345 {
2346 as_warn (_("indirect %s without `*'"), t->name);
2347 }
2348
2349 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2350 == (IsPrefix | IgnoreSize))
2351 {
2352 /* Warn them that a data or address size prefix doesn't
2353 affect assembly of the next line of code. */
2354 as_warn (_("stand-alone `%s' prefix"), t->name);
2355 }
2356 }
2357
2358 /* Copy the template we found. */
2359 i.tm = *t;
2360 if (found_reverse_match)
2361 {
2362 /* If we found a reverse match we must alter the opcode
2363 direction bit. found_reverse_match holds bits to change
2364 (different for int & float insns). */
2365
2366 i.tm.base_opcode ^= found_reverse_match;
2367
2368 i.tm.operand_types[0] = t->operand_types[1];
2369 i.tm.operand_types[1] = t->operand_types[0];
2370 }
2371
2372 return 1;
2373}
2374
2375static int
2376check_string ()
2377{
2378 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2379 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2380 {
2381 if (i.seg[0] != NULL && i.seg[0] != &es)
2382 {
2383 as_bad (_("`%s' operand %d must use `%%es' segment"),
2384 i.tm.name,
2385 mem_op + 1);
2386 return 0;
2387 }
2388 /* There's only ever one segment override allowed per instruction.
2389 This instruction possibly has a legal segment override on the
2390 second operand, so copy the segment to where non-string
2391 instructions store it, allowing common code. */
2392 i.seg[0] = i.seg[1];
2393 }
2394 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2395 {
2396 if (i.seg[1] != NULL && i.seg[1] != &es)
2397 {
2398 as_bad (_("`%s' operand %d must use `%%es' segment"),
2399 i.tm.name,
2400 mem_op + 2);
2401 return 0;
2402 }
2403 }
2404 return 1;
2405}
2406
2407static int
543613e9 2408process_suffix (void)
29b0f896
AM		 2409{
2410 /* If matched instruction specifies an explicit instruction mnemonic
2411 suffix, use it. */
2412 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2413 {
2414 if (i.tm.opcode_modifier & Size16)
2415 i.suffix = WORD_MNEM_SUFFIX;
2416 else if (i.tm.opcode_modifier & Size64)
2417 i.suffix = QWORD_MNEM_SUFFIX;
2418 else
2419 i.suffix = LONG_MNEM_SUFFIX;
2420 }
2421 else if (i.reg_operands)
2422 {
2423 /* If there's no instruction mnemonic suffix we try to invent one
2424 based on register operands. */
2425 if (!i.suffix)
2426 {
2427 /* We take i.suffix from the last register operand specified,
2428 Destination register type is more significant than source
2429 register type. */
2430 int op;
543613e9 2431
29b0f896
AM		 2432 for (op = i.operands; --op >= 0;)
2433 if ((i.types[op] & Reg)
2434 && !(i.tm.operand_types[op] & InOutPortReg))
2435 {
2436 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2437 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2438 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2439 LONG_MNEM_SUFFIX);
2440 break;
2441 }
2442 }
2443 else if (i.suffix == BYTE_MNEM_SUFFIX)
2444 {
2445 if (!check_byte_reg ())
2446 return 0;
2447 }
2448 else if (i.suffix == LONG_MNEM_SUFFIX)
2449 {
2450 if (!check_long_reg ())
2451 return 0;
2452 }
2453 else if (i.suffix == QWORD_MNEM_SUFFIX)
2454 {
2455 if (!check_qword_reg ())
2456 return 0;
2457 }
2458 else if (i.suffix == WORD_MNEM_SUFFIX)
2459 {
2460 if (!check_word_reg ())
2461 return 0;
2462 }
2463 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2464 /* Do nothing if the instruction is going to ignore the prefix. */
2465 ;
2466 else
2467 abort ();
2468 }
9306ca4a
JB		 2469 else if ((i.tm.opcode_modifier & DefaultSize)
2470 && !i.suffix
2471 /* exclude fldenv/frstor/fsave/fstenv */
2472 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2473 {
2474 i.suffix = stackop_size;
2475 }
9306ca4a
JB		 2476 else if (intel_syntax
2477 && !i.suffix
2478 && ((i.tm.operand_types[0] & JumpAbsolute)
2479 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2480 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2481 && i.tm.extension_opcode <= 3)))
2482 {
2483 switch (flag_code)
2484 {
2485 case CODE_64BIT:
2486 if (!(i.tm.opcode_modifier & No_qSuf))
2487 {
2488 i.suffix = QWORD_MNEM_SUFFIX;
2489 break;
2490 }
2491 case CODE_32BIT:
2492 if (!(i.tm.opcode_modifier & No_lSuf))
2493 i.suffix = LONG_MNEM_SUFFIX;
2494 break;
2495 case CODE_16BIT:
2496 if (!(i.tm.opcode_modifier & No_wSuf))
2497 i.suffix = WORD_MNEM_SUFFIX;
2498 break;
2499 }
2500 }
252b5132 2501
9306ca4a 2502 if (!i.suffix)
29b0f896 2503 {
9306ca4a
JB		 2504 if (!intel_syntax)
2505 {
2506 if (i.tm.opcode_modifier & W)
2507 {
2508 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2509 return 0;
2510 }
2511 }
2512 else
2513 {
2514 unsigned int suffixes = ~i.tm.opcode_modifier
2515 & (No_bSuf
2516 | No_wSuf
2517 | No_lSuf
2518 | No_sSuf
2519 | No_xSuf
2520 | No_qSuf);
2521
2522 if ((i.tm.opcode_modifier & W)
2523 || ((suffixes & (suffixes - 1))
2524 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2525 {
2526 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2527 return 0;
2528 }
2529 }
29b0f896 2530 }
252b5132 2531
9306ca4a
JB		 2532 /* Change the opcode based on the operand size given by i.suffix;
2533 We don't need to change things for byte insns. */
2534
29b0f896
AM		 2535 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2536 {
2537 /* It's not a byte, select word/dword operation. */
2538 if (i.tm.opcode_modifier & W)
2539 {
2540 if (i.tm.opcode_modifier & ShortForm)
2541 i.tm.base_opcode |= 8;
2542 else
2543 i.tm.base_opcode |= 1;
2544 }
0f3f3d8b 2545
29b0f896
AM		 2546 /* Now select between word & dword operations via the operand
2547 size prefix, except for instructions that will ignore this
2548 prefix anyway. */
2549 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2550 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2551 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2552 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2553 || (flag_code == CODE_64BIT
2554 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2555 {
2556 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2557
29b0f896
AM		 2558 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2559 prefix = ADDR_PREFIX_OPCODE;
252b5132 2560
29b0f896
AM		 2561 if (!add_prefix (prefix))
2562 return 0;
24eab124 2563 }
252b5132 2564
29b0f896
AM		 2565 /* Set mode64 for an operand. */
2566 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2567 && flag_code == CODE_64BIT
29b0f896 2568 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2569 i.rex |= REX_MODE64;
3e73aa7c 2570
29b0f896
AM		 2571 /* Size floating point instruction. */
2572 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2573 if (i.tm.opcode_modifier & FloatMF)
2574 i.tm.base_opcode ^= 4;
29b0f896 2575 }
7ecd2f8b 2576
29b0f896
AM		 2577 return 1;
2578}
3e73aa7c 2579
29b0f896 2580static int
543613e9 2581check_byte_reg (void)
29b0f896
AM		 2582{
2583 int op;
543613e9 2584
29b0f896
AM		 2585 for (op = i.operands; --op >= 0;)
2586 {
2587 /* If this is an eight bit register, it's OK. If it's the 16 or
2588 32 bit version of an eight bit register, we will just use the
2589 low portion, and that's OK too. */
2590 if (i.types[op] & Reg8)
2591 continue;
2592
2593 /* movzx and movsx should not generate this warning. */
2594 if (intel_syntax
2595 && (i.tm.base_opcode == 0xfb7
2596 || i.tm.base_opcode == 0xfb6
2597 || i.tm.base_opcode == 0x63
2598 || i.tm.base_opcode == 0xfbe
2599 || i.tm.base_opcode == 0xfbf))
2600 continue;
2601
65ec77d2 2602 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2603 {
2604 /* Prohibit these changes in the 64bit mode, since the
2605 lowering is more complicated. */
2606 if (flag_code == CODE_64BIT
2607 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2608 {
0f3f3d8b 2609 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2610 i.op[op].regs->reg_name,
2611 i.suffix);
2612 return 0;
2613 }
2614#if REGISTER_WARNINGS
2615 if (!quiet_warnings
2616 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2617 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2618 (i.op[op].regs + (i.types[op] & Reg16
2619 ? REGNAM_AL - REGNAM_AX
2620 : REGNAM_AL - REGNAM_EAX))->reg_name,
2621 i.op[op].regs->reg_name,
2622 i.suffix);
2623#endif
2624 continue;
2625 }
2626 /* Any other register is bad. */
2627 if (i.types[op] & (Reg | RegMMX | RegXMM
2628 | SReg2 | SReg3
2629 | Control | Debug | Test
2630 | FloatReg | FloatAcc))
2631 {
2632 as_bad (_("`%%%s' not allowed with `%s%c'"),
2633 i.op[op].regs->reg_name,
2634 i.tm.name,
2635 i.suffix);
2636 return 0;
2637 }
2638 }
2639 return 1;
2640}
2641
2642static int
2643check_long_reg ()
2644{
2645 int op;
2646
2647 for (op = i.operands; --op >= 0;)
2648 /* Reject eight bit registers, except where the template requires
2649 them. (eg. movzb) */
2650 if ((i.types[op] & Reg8) != 0
2651 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2652 {
2653 as_bad (_("`%%%s' not allowed with `%s%c'"),
2654 i.op[op].regs->reg_name,
2655 i.tm.name,
2656 i.suffix);
2657 return 0;
2658 }
2659 /* Warn if the e prefix on a general reg is missing. */
2660 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2661 && (i.types[op] & Reg16) != 0
2662 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2663 {
2664 /* Prohibit these changes in the 64bit mode, since the
2665 lowering is more complicated. */
2666 if (flag_code == CODE_64BIT)
252b5132 2667 {
0f3f3d8b 2668 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2669 i.op[op].regs->reg_name,
2670 i.suffix);
2671 return 0;
252b5132 2672 }
29b0f896
AM		 2673#if REGISTER_WARNINGS
2674 else
2675 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2676 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2677 i.op[op].regs->reg_name,
2678 i.suffix);
2679#endif
252b5132 2680 }
29b0f896
AM		 2681 /* Warn if the r prefix on a general reg is missing. */
2682 else if ((i.types[op] & Reg64) != 0
2683 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2684 {
0f3f3d8b 2685 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2686 i.op[op].regs->reg_name,
2687 i.suffix);
2688 return 0;
2689 }
2690 return 1;
2691}
252b5132 2692
29b0f896
AM		 2693static int
2694check_qword_reg ()
2695{
2696 int op;
252b5132 2697
29b0f896
AM		 2698 for (op = i.operands; --op >= 0; )
2699 /* Reject eight bit registers, except where the template requires
2700 them. (eg. movzb) */
2701 if ((i.types[op] & Reg8) != 0
2702 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2703 {
2704 as_bad (_("`%%%s' not allowed with `%s%c'"),
2705 i.op[op].regs->reg_name,
2706 i.tm.name,
2707 i.suffix);
2708 return 0;
2709 }
2710 /* Warn if the e prefix on a general reg is missing. */
2711 else if (((i.types[op] & Reg16) != 0
2712 || (i.types[op] & Reg32) != 0)
2713 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2714 {
2715 /* Prohibit these changes in the 64bit mode, since the
2716 lowering is more complicated. */
0f3f3d8b 2717 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2718 i.op[op].regs->reg_name,
2719 i.suffix);
2720 return 0;
252b5132 2721 }
29b0f896
AM		 2722 return 1;
2723}
252b5132 2724
29b0f896
AM		 2725static int
2726check_word_reg ()
2727{
2728 int op;
2729 for (op = i.operands; --op >= 0;)
2730 /* Reject eight bit registers, except where the template requires
2731 them. (eg. movzb) */
2732 if ((i.types[op] & Reg8) != 0
2733 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2734 {
2735 as_bad (_("`%%%s' not allowed with `%s%c'"),
2736 i.op[op].regs->reg_name,
2737 i.tm.name,
2738 i.suffix);
2739 return 0;
2740 }
2741 /* Warn if the e prefix on a general reg is present. */
2742 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2743 && (i.types[op] & Reg32) != 0
2744 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2745 {
29b0f896
AM		 2746 /* Prohibit these changes in the 64bit mode, since the
2747 lowering is more complicated. */
2748 if (flag_code == CODE_64BIT)
252b5132 2749 {
0f3f3d8b 2750 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2751 i.op[op].regs->reg_name,
2752 i.suffix);
2753 return 0;
252b5132 2754 }
29b0f896
AM		 2755 else
2756#if REGISTER_WARNINGS
2757 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2758 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2759 i.op[op].regs->reg_name,
2760 i.suffix);
2761#endif
2762 }
2763 return 1;
2764}
252b5132 2765
29b0f896
AM		 2766static int
2767finalize_imm ()
2768{
2769 unsigned int overlap0, overlap1, overlap2;
2770
2771 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2772 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2773 && overlap0 != Imm8 && overlap0 != Imm8S
2774 && overlap0 != Imm16 && overlap0 != Imm32S
2775 && overlap0 != Imm32 && overlap0 != Imm64)
2776 {
2777 if (i.suffix)
2778 {
2779 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2780 ? Imm8 | Imm8S
2781 : (i.suffix == WORD_MNEM_SUFFIX
2782 ? Imm16
2783 : (i.suffix == QWORD_MNEM_SUFFIX
2784 ? Imm64 | Imm32S
2785 : Imm32)));
2786 }
2787 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2788 || overlap0 == (Imm16 | Imm32)
2789 || overlap0 == (Imm16 | Imm32S))
2790 {
2791 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2792 ? Imm16 : Imm32S);
2793 }
2794 if (overlap0 != Imm8 && overlap0 != Imm8S
2795 && overlap0 != Imm16 && overlap0 != Imm32S
2796 && overlap0 != Imm32 && overlap0 != Imm64)
2797 {
2798 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2799 return 0;
2800 }
2801 }
2802 i.types[0] = overlap0;
2803
2804 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2805 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2806 && overlap1 != Imm8 && overlap1 != Imm8S
2807 && overlap1 != Imm16 && overlap1 != Imm32S
2808 && overlap1 != Imm32 && overlap1 != Imm64)
2809 {
2810 if (i.suffix)
2811 {
2812 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2813 ? Imm8 | Imm8S
2814 : (i.suffix == WORD_MNEM_SUFFIX
2815 ? Imm16
2816 : (i.suffix == QWORD_MNEM_SUFFIX
2817 ? Imm64 | Imm32S
2818 : Imm32)));
2819 }
2820 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2821 || overlap1 == (Imm16 | Imm32)
2822 || overlap1 == (Imm16 | Imm32S))
2823 {
2824 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2825 ? Imm16 : Imm32S);
2826 }
2827 if (overlap1 != Imm8 && overlap1 != Imm8S
2828 && overlap1 != Imm16 && overlap1 != Imm32S
2829 && overlap1 != Imm32 && overlap1 != Imm64)
2830 {
2831 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2832 return 0;
2833 }
2834 }
2835 i.types[1] = overlap1;
2836
2837 overlap2 = i.types[2] & i.tm.operand_types[2];
2838 assert ((overlap2 & Imm) == 0);
2839 i.types[2] = overlap2;
2840
2841 return 1;
2842}
2843
2844static int
2845process_operands ()
2846{
2847 /* Default segment register this instruction will use for memory
2848 accesses. 0 means unknown. This is only for optimizing out
2849 unnecessary segment overrides. */
2850 const seg_entry *default_seg = 0;
2851
2852 /* The imul $imm, %reg instruction is converted into
2853 imul $imm, %reg, %reg, and the clr %reg instruction
2854 is converted into xor %reg, %reg. */
2855 if (i.tm.opcode_modifier & regKludge)
2856 {
2857 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2858 /* Pretend we saw the extra register operand. */
2859 assert (i.op[first_reg_op + 1].regs == 0);
2860 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2861 i.types[first_reg_op + 1] = i.types[first_reg_op];
2862 i.reg_operands = 2;
2863 }
2864
2865 if (i.tm.opcode_modifier & ShortForm)
2866 {
2867 /* The register or float register operand is in operand 0 or 1. */
2868 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2869 /* Register goes in low 3 bits of opcode. */
2870 i.tm.base_opcode |= i.op[op].regs->reg_num;
2871 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2872 i.rex |= REX_EXTZ;
2873 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2874 {
2875 /* Warn about some common errors, but press on regardless.
2876 The first case can be generated by gcc (<= 2.8.1). */
2877 if (i.operands == 2)
2878 {
2879 /* Reversed arguments on faddp, fsubp, etc. */
2880 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2881 i.op[1].regs->reg_name,
2882 i.op[0].regs->reg_name);
2883 }
2884 else
2885 {
2886 /* Extraneous `l' suffix on fp insn. */
2887 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2888 i.op[0].regs->reg_name);
2889 }
2890 }
2891 }
2892 else if (i.tm.opcode_modifier & Modrm)
2893 {
2894 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2895 must be put into the modrm byte). Now, we make the modrm and
2896 index base bytes based on all the info we've collected. */
29b0f896
AM		 2897
2898 default_seg = build_modrm_byte ();
2899 }
2900 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2901 {
2902 if (i.tm.base_opcode == POP_SEG_SHORT
2903 && i.op[0].regs->reg_num == 1)
2904 {
2905 as_bad (_("you can't `pop %%cs'"));
2906 return 0;
2907 }
2908 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2909 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2910 i.rex |= REX_EXTZ;
2911 }
2912 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2913 {
2914 default_seg = &ds;
2915 }
2916 else if ((i.tm.opcode_modifier & IsString) != 0)
2917 {
2918 /* For the string instructions that allow a segment override
2919 on one of their operands, the default segment is ds. */
2920 default_seg = &ds;
2921 }
2922
30123838
JB		 2923 if ((i.tm.base_opcode == 0x8d /* lea */
2924 || (i.tm.cpu_flags & CpuSVME))
2925 && i.seg[0] && !quiet_warnings)
2926 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2927
2928 /* If a segment was explicitly specified, and the specified segment
2929 is not the default, use an opcode prefix to select it. If we
2930 never figured out what the default segment is, then default_seg
2931 will be zero at this point, and the specified segment prefix will
2932 always be used. */
29b0f896
AM		 2933 if ((i.seg[0]) && (i.seg[0] != default_seg))
2934 {
2935 if (!add_prefix (i.seg[0]->seg_prefix))
2936 return 0;
2937 }
2938 return 1;
2939}
2940
2941static const seg_entry *
2942build_modrm_byte ()
2943{
2944 const seg_entry *default_seg = 0;
2945
2946 /* i.reg_operands MUST be the number of real register operands;
2947 implicit registers do not count. */
2948 if (i.reg_operands == 2)
2949 {
2950 unsigned int source, dest;
2951 source = ((i.types[0]
2952 & (Reg | RegMMX | RegXMM
2953 | SReg2 | SReg3
2954 | Control | Debug | Test))
2955 ? 0 : 1);
2956 dest = source + 1;
2957
2958 i.rm.mode = 3;
2959 /* One of the register operands will be encoded in the i.tm.reg
2960 field, the other in the combined i.tm.mode and i.tm.regmem
2961 fields. If no form of this instruction supports a memory
2962 destination operand, then we assume the source operand may
2963 sometimes be a memory operand and so we need to store the
2964 destination in the i.rm.reg field. */
2965 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2966 {
2967 i.rm.reg = i.op[dest].regs->reg_num;
2968 i.rm.regmem = i.op[source].regs->reg_num;
2969 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2970 i.rex |= REX_EXTX;
2971 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2972 i.rex |= REX_EXTZ;
2973 }
2974 else
2975 {
2976 i.rm.reg = i.op[source].regs->reg_num;
2977 i.rm.regmem = i.op[dest].regs->reg_num;
2978 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2979 i.rex |= REX_EXTZ;
2980 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2981 i.rex |= REX_EXTX;
2982 }
c4a530c5
JB		 2983 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2984 {
2985 if (!((i.types[0] | i.types[1]) & Control))
2986 abort ();
2987 i.rex &= ~(REX_EXTX | REX_EXTZ);
2988 add_prefix (LOCK_PREFIX_OPCODE);
2989 }
29b0f896
AM		 2990 }
2991 else
2992 { /* If it's not 2 reg operands... */
2993 if (i.mem_operands)
2994 {
2995 unsigned int fake_zero_displacement = 0;
2996 unsigned int op = ((i.types[0] & AnyMem)
2997 ? 0
2998 : (i.types[1] & AnyMem) ? 1 : 2);
2999
3000 default_seg = &ds;
3001
3002 if (i.base_reg == 0)
3003 {
3004 i.rm.mode = 0;
3005 if (!i.disp_operands)
3006 fake_zero_displacement = 1;
3007 if (i.index_reg == 0)
3008 {
3009 /* Operand is just <disp> */
20f0a1fc 3010 if (flag_code == CODE_64BIT)
29b0f896
AM		 3011 {
3012 /* 64bit mode overwrites the 32bit absolute
3013 addressing by RIP relative addressing and
3014 absolute addressing is encoded by one of the
3015 redundant SIB forms. */
3016 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3017 i.sib.base = NO_BASE_REGISTER;
3018 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3019 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3020 }
3021 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3022 {
3023 i.rm.regmem = NO_BASE_REGISTER_16;
3024 i.types[op] = Disp16;
3025 }
3026 else
3027 {
3028 i.rm.regmem = NO_BASE_REGISTER;
3029 i.types[op] = Disp32;
29b0f896
AM		 3030 }
3031 }
3032 else /* !i.base_reg && i.index_reg */
3033 {
3034 i.sib.index = i.index_reg->reg_num;
3035 i.sib.base = NO_BASE_REGISTER;
3036 i.sib.scale = i.log2_scale_factor;
3037 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3038 i.types[op] &= ~Disp;
3039 if (flag_code != CODE_64BIT)
3040 i.types[op] |= Disp32; /* Must be 32 bit */
3041 else
3042 i.types[op] |= Disp32S;
3043 if ((i.index_reg->reg_flags & RegRex) != 0)
3044 i.rex |= REX_EXTY;
3045 }
3046 }
3047 /* RIP addressing for 64bit mode. */
3048 else if (i.base_reg->reg_type == BaseIndex)
3049 {
3050 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3051 i.types[op] &= ~ Disp;
29b0f896
AM		 3052 i.types[op] |= Disp32S;
3053 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3054 if (! i.disp_operands)
3055 fake_zero_displacement = 1;
29b0f896
AM		 3056 }
3057 else if (i.base_reg->reg_type & Reg16)
3058 {
3059 switch (i.base_reg->reg_num)
3060 {
3061 case 3: /* (%bx) */
3062 if (i.index_reg == 0)
3063 i.rm.regmem = 7;
3064 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3065 i.rm.regmem = i.index_reg->reg_num - 6;
3066 break;
3067 case 5: /* (%bp) */
3068 default_seg = &ss;
3069 if (i.index_reg == 0)
3070 {
3071 i.rm.regmem = 6;
3072 if ((i.types[op] & Disp) == 0)
3073 {
3074 /* fake (%bp) into 0(%bp) */
3075 i.types[op] |= Disp8;
252b5132 3076 fake_zero_displacement = 1;
29b0f896
AM		 3077 }
3078 }
3079 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3080 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3081 break;
3082 default: /* (%si) -> 4 or (%di) -> 5 */
3083 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3084 }
3085 i.rm.mode = mode_from_disp_size (i.types[op]);
3086 }
3087 else /* i.base_reg and 32/64 bit mode */
3088 {
3089 if (flag_code == CODE_64BIT
3090 && (i.types[op] & Disp))
20f0a1fc
NC		 3091 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3092
29b0f896
AM		 3093 i.rm.regmem = i.base_reg->reg_num;
3094 if ((i.base_reg->reg_flags & RegRex) != 0)
3095 i.rex |= REX_EXTZ;
3096 i.sib.base = i.base_reg->reg_num;
3097 /* x86-64 ignores REX prefix bit here to avoid decoder
3098 complications. */
3099 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3100 {
3101 default_seg = &ss;
3102 if (i.disp_operands == 0)
3103 {
3104 fake_zero_displacement = 1;
3105 i.types[op] |= Disp8;
3106 }
3107 }
3108 else if (i.base_reg->reg_num == ESP_REG_NUM)
3109 {
3110 default_seg = &ss;
3111 }
3112 i.sib.scale = i.log2_scale_factor;
3113 if (i.index_reg == 0)
3114 {
3115 /* <disp>(%esp) becomes two byte modrm with no index
3116 register. We've already stored the code for esp
3117 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3118 Any base register besides %esp will not use the
3119 extra modrm byte. */
3120 i.sib.index = NO_INDEX_REGISTER;
3121#if !SCALE1_WHEN_NO_INDEX
3122 /* Another case where we force the second modrm byte. */
3123 if (i.log2_scale_factor)
3124 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3125#endif
29b0f896
AM		 3126 }
3127 else
3128 {
3129 i.sib.index = i.index_reg->reg_num;
3130 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3131 if ((i.index_reg->reg_flags & RegRex) != 0)
3132 i.rex |= REX_EXTY;
3133 }
3134 i.rm.mode = mode_from_disp_size (i.types[op]);
3135 }
252b5132 3136
29b0f896
AM		 3137 if (fake_zero_displacement)
3138 {
3139 /* Fakes a zero displacement assuming that i.types[op]
3140 holds the correct displacement size. */
3141 expressionS *exp;
3142
3143 assert (i.op[op].disps == 0);
3144 exp = &disp_expressions[i.disp_operands++];
3145 i.op[op].disps = exp;
3146 exp->X_op = O_constant;
3147 exp->X_add_number = 0;
3148 exp->X_add_symbol = (symbolS *) 0;
3149 exp->X_op_symbol = (symbolS *) 0;
3150 }
3151 }
252b5132 3152
29b0f896
AM		 3153 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3154 (if any) based on i.tm.extension_opcode. Again, we must be
3155 careful to make sure that segment/control/debug/test/MMX
3156 registers are coded into the i.rm.reg field. */
3157 if (i.reg_operands)
3158 {
3159 unsigned int op =
3160 ((i.types[0]
3161 & (Reg | RegMMX | RegXMM
3162 | SReg2 | SReg3
3163 | Control | Debug | Test))
3164 ? 0
3165 : ((i.types[1]
3166 & (Reg | RegMMX | RegXMM
3167 | SReg2 | SReg3
3168 | Control | Debug | Test))
3169 ? 1
3170 : 2));
3171 /* If there is an extension opcode to put here, the register
3172 number must be put into the regmem field. */
3173 if (i.tm.extension_opcode != None)
3174 {
3175 i.rm.regmem = i.op[op].regs->reg_num;
3176 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3177 i.rex |= REX_EXTZ;
3178 }
3179 else
3180 {
3181 i.rm.reg = i.op[op].regs->reg_num;
3182 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3183 i.rex |= REX_EXTX;
3184 }
252b5132 3185
29b0f896
AM		 3186 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3187 must set it to 3 to indicate this is a register operand
3188 in the regmem field. */
3189 if (!i.mem_operands)
3190 i.rm.mode = 3;
3191 }
252b5132 3192
29b0f896
AM		 3193 /* Fill in i.rm.reg field with extension opcode (if any). */
3194 if (i.tm.extension_opcode != None)
3195 i.rm.reg = i.tm.extension_opcode;
3196 }
3197 return default_seg;
3198}
252b5132 3199
29b0f896
AM		 3200static void
3201output_branch ()
3202{
3203 char *p;
3204 int code16;
3205 int prefix;
3206 relax_substateT subtype;
3207 symbolS *sym;
3208 offsetT off;
3209
3210 code16 = 0;
3211 if (flag_code == CODE_16BIT)
3212 code16 = CODE16;
3213
3214 prefix = 0;
3215 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3216 {
29b0f896
AM		 3217 prefix = 1;
3218 i.prefixes -= 1;
3219 code16 ^= CODE16;
252b5132 3220 }
29b0f896
AM		 3221 /* Pentium4 branch hints. */
3222 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3223 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3224 {
29b0f896
AM		 3225 prefix++;
3226 i.prefixes--;
3227 }
3228 if (i.prefix[REX_PREFIX] != 0)
3229 {
3230 prefix++;
3231 i.prefixes--;
2f66722d
AM		 3232 }
3233
29b0f896
AM		 3234 if (i.prefixes != 0 && !intel_syntax)
3235 as_warn (_("skipping prefixes on this instruction"));
3236
3237 /* It's always a symbol; End frag & setup for relax.
3238 Make sure there is enough room in this frag for the largest
3239 instruction we may generate in md_convert_frag. This is 2
3240 bytes for the opcode and room for the prefix and largest
3241 displacement. */
3242 frag_grow (prefix + 2 + 4);
3243 /* Prefix and 1 opcode byte go in fr_fix. */
3244 p = frag_more (prefix + 1);
3245 if (i.prefix[DATA_PREFIX] != 0)
3246 *p++ = DATA_PREFIX_OPCODE;
3247 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3248 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3249 *p++ = i.prefix[SEG_PREFIX];
3250 if (i.prefix[REX_PREFIX] != 0)
3251 *p++ = i.prefix[REX_PREFIX];
3252 *p = i.tm.base_opcode;
3253
3254 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3255 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3256 else if ((cpu_arch_flags & Cpu386) != 0)
3257 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3258 else
3259 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3260 subtype |= code16;
3e73aa7c 3261
29b0f896
AM		 3262 sym = i.op[0].disps->X_add_symbol;
3263 off = i.op[0].disps->X_add_number;
3e73aa7c 3264
29b0f896
AM		 3265 if (i.op[0].disps->X_op != O_constant
3266 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3267 {
29b0f896
AM		 3268 /* Handle complex expressions. */
3269 sym = make_expr_symbol (i.op[0].disps);
3270 off = 0;
3271 }
3e73aa7c 3272
29b0f896
AM		 3273 /* 1 possible extra opcode + 4 byte displacement go in var part.
3274 Pass reloc in fr_var. */
3275 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3276}
3e73aa7c 3277
29b0f896
AM		 3278static void
3279output_jump ()
3280{
3281 char *p;
3282 int size;
3e02c1cc 3283 fixS *fixP;
29b0f896
AM		 3284
3285 if (i.tm.opcode_modifier & JumpByte)
3286 {
3287 /* This is a loop or jecxz type instruction. */
3288 size = 1;
3289 if (i.prefix[ADDR_PREFIX] != 0)
3290 {
3291 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3292 i.prefixes -= 1;
3293 }
3294 /* Pentium4 branch hints. */
3295 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3296 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3297 {
3298 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3299 i.prefixes--;
3e73aa7c
JH		 3300 }
3301 }
29b0f896
AM		 3302 else
3303 {
3304 int code16;
3e73aa7c 3305
29b0f896
AM		 3306 code16 = 0;
3307 if (flag_code == CODE_16BIT)
3308 code16 = CODE16;
3e73aa7c 3309
29b0f896
AM		 3310 if (i.prefix[DATA_PREFIX] != 0)
3311 {
3312 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3313 i.prefixes -= 1;
3314 code16 ^= CODE16;
3315 }
252b5132 3316
29b0f896
AM		 3317 size = 4;
3318 if (code16)
3319 size = 2;
3320 }
9fcc94b6 3321
29b0f896
AM		 3322 if (i.prefix[REX_PREFIX] != 0)
3323 {
3324 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3325 i.prefixes -= 1;
3326 }
252b5132 3327
29b0f896
AM		 3328 if (i.prefixes != 0 && !intel_syntax)
3329 as_warn (_("skipping prefixes on this instruction"));
e0890092 3330
29b0f896
AM		 3331 p = frag_more (1 + size);
3332 *p++ = i.tm.base_opcode;
e0890092 3333
3e02c1cc
AM		 3334 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3335 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3336
3337 /* All jumps handled here are signed, but don't use a signed limit
3338 check for 32 and 16 bit jumps as we want to allow wrap around at
3339 4G and 64k respectively. */
3340 if (size == 1)
3341 fixP->fx_signed = 1;
29b0f896 3342}
e0890092 3343
29b0f896
AM		 3344static void
3345output_interseg_jump ()
3346{
3347 char *p;
3348 int size;
3349 int prefix;
3350 int code16;
252b5132 3351
29b0f896
AM		 3352 code16 = 0;
3353 if (flag_code == CODE_16BIT)
3354 code16 = CODE16;
a217f122 3355
29b0f896
AM		 3356 prefix = 0;
3357 if (i.prefix[DATA_PREFIX] != 0)
3358 {
3359 prefix = 1;
3360 i.prefixes -= 1;
3361 code16 ^= CODE16;
3362 }
3363 if (i.prefix[REX_PREFIX] != 0)
3364 {
3365 prefix++;
3366 i.prefixes -= 1;
3367 }
252b5132 3368
29b0f896
AM		 3369 size = 4;
3370 if (code16)
3371 size = 2;
252b5132 3372
29b0f896
AM		 3373 if (i.prefixes != 0 && !intel_syntax)
3374 as_warn (_("skipping prefixes on this instruction"));
252b5132 3375
29b0f896
AM		 3376 /* 1 opcode; 2 segment; offset */
3377 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3378
29b0f896
AM		 3379 if (i.prefix[DATA_PREFIX] != 0)
3380 *p++ = DATA_PREFIX_OPCODE;
252b5132 3381
29b0f896
AM		 3382 if (i.prefix[REX_PREFIX] != 0)
3383 *p++ = i.prefix[REX_PREFIX];
252b5132 3384
29b0f896
AM		 3385 *p++ = i.tm.base_opcode;
3386 if (i.op[1].imms->X_op == O_constant)
3387 {
3388 offsetT n = i.op[1].imms->X_add_number;
252b5132 3389
29b0f896
AM		 3390 if (size == 2
3391 && !fits_in_unsigned_word (n)
3392 && !fits_in_signed_word (n))
3393 {
3394 as_bad (_("16-bit jump out of range"));
3395 return;
3396 }
3397 md_number_to_chars (p, n, size);
3398 }
3399 else
3400 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3401 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3402 if (i.op[0].imms->X_op != O_constant)
3403 as_bad (_("can't handle non absolute segment in `%s'"),
3404 i.tm.name);
3405 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3406}
a217f122 3407
29b0f896
AM		 3408static void
3409output_insn ()
3410{
2bbd9c25
JJ		 3411 fragS *insn_start_frag;
3412 offsetT insn_start_off;
3413
29b0f896
AM		 3414 /* Tie dwarf2 debug info to the address at the start of the insn.
3415 We can't do this after the insn has been output as the current
3416 frag may have been closed off. eg. by frag_var. */
3417 dwarf2_emit_insn (0);
3418
2bbd9c25
JJ		 3419 insn_start_frag = frag_now;
3420 insn_start_off = frag_now_fix ();
3421
29b0f896
AM		 3422 /* Output jumps. */
3423 if (i.tm.opcode_modifier & Jump)
3424 output_branch ();
3425 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3426 output_jump ();
3427 else if (i.tm.opcode_modifier & JumpInterSegment)
3428 output_interseg_jump ();
3429 else
3430 {
3431 /* Output normal instructions here. */
3432 char *p;
3433 unsigned char *q;
252b5132 3434
bc4bd9ab
MK		 3435 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3436 more higher byte to specify a prefix the instruction
3437 requires. */
3438 if ((i.tm.base_opcode & 0xff0000) != 0)
3439 {
3440 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3441 {
3442 unsigned int prefix;
3443 prefix = (i.tm.base_opcode >> 16) & 0xff;
3444
3445 if (prefix != REPE_PREFIX_OPCODE
3446 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3447 add_prefix (prefix);
3448 }
3449 else
3450 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3451 }
252b5132 3452
29b0f896
AM		 3453 /* The prefix bytes. */
3454 for (q = i.prefix;
3455 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3456 q++)
3457 {
3458 if (*q)
3459 {
3460 p = frag_more (1);
3461 md_number_to_chars (p, (valueT) *q, 1);
3462 }
3463 }
252b5132 3464
29b0f896
AM		 3465 /* Now the opcode; be careful about word order here! */
3466 if (fits_in_unsigned_byte (i.tm.base_opcode))
3467 {
3468 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3469 }
3470 else
3471 {
bc4bd9ab 3472 p = frag_more (2);
0f10071e 3473
29b0f896
AM		 3474 /* Put out high byte first: can't use md_number_to_chars! */
3475 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3476 *p = i.tm.base_opcode & 0xff;
3477 }
3e73aa7c 3478
29b0f896
AM		 3479 /* Now the modrm byte and sib byte (if present). */
3480 if (i.tm.opcode_modifier & Modrm)
3481 {
3482 p = frag_more (1);
3483 md_number_to_chars (p,
3484 (valueT) (i.rm.regmem << 0
3485 | i.rm.reg << 3
3486 | i.rm.mode << 6),
3487 1);
3488 /* If i.rm.regmem == ESP (4)
3489 && i.rm.mode != (Register mode)
3490 && not 16 bit
3491 ==> need second modrm byte. */
3492 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3493 && i.rm.mode != 3
3494 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3495 {
3496 p = frag_more (1);
3497 md_number_to_chars (p,
3498 (valueT) (i.sib.base << 0
3499 | i.sib.index << 3
3500 | i.sib.scale << 6),
3501 1);
3502 }
3503 }
3e73aa7c 3504
29b0f896 3505 if (i.disp_operands)
2bbd9c25 3506 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3507
29b0f896 3508 if (i.imm_operands)
2bbd9c25 3509 output_imm (insn_start_frag, insn_start_off);
29b0f896 3510 }
252b5132 3511
29b0f896
AM		 3512#ifdef DEBUG386
3513 if (flag_debug)
3514 {
3515 pi (line, &i);
3516 }
3517#endif /* DEBUG386 */
3518}
252b5132 3519
29b0f896 3520static void
2bbd9c25
JJ		 3521output_disp (insn_start_frag, insn_start_off)
3522 fragS *insn_start_frag;
3523 offsetT insn_start_off;
29b0f896
AM		 3524{
3525 char *p;
3526 unsigned int n;
252b5132 3527
29b0f896
AM		 3528 for (n = 0; n < i.operands; n++)
3529 {
3530 if (i.types[n] & Disp)
3531 {
3532 if (i.op[n].disps->X_op == O_constant)
3533 {
3534 int size;
3535 offsetT val;
252b5132 3536
29b0f896
AM		 3537 size = 4;
3538 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3539 {
3540 size = 2;
3541 if (i.types[n] & Disp8)
3542 size = 1;
3543 if (i.types[n] & Disp64)
3544 size = 8;
3545 }
3546 val = offset_in_range (i.op[n].disps->X_add_number,
3547 size);
3548 p = frag_more (size);
3549 md_number_to_chars (p, val, size);
3550 }
3551 else
3552 {
f86103b7 3553 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3554 int size = 4;
3555 int sign = 0;
3556 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3557
3558 /* The PC relative address is computed relative
3559 to the instruction boundary, so in case immediate
3560 fields follows, we need to adjust the value. */
3561 if (pcrel && i.imm_operands)
3562 {
3563 int imm_size = 4;
3564 unsigned int n1;
252b5132 3565
29b0f896
AM		 3566 for (n1 = 0; n1 < i.operands; n1++)
3567 if (i.types[n1] & Imm)
252b5132 3568 {
29b0f896 3569 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3570 {
29b0f896
AM		 3571 imm_size = 2;
3572 if (i.types[n1] & (Imm8 | Imm8S))
3573 imm_size = 1;
3574 if (i.types[n1] & Imm64)
3575 imm_size = 8;
252b5132 3576 }
29b0f896 3577 break;
252b5132 3578 }
29b0f896
AM		 3579 /* We should find the immediate. */
3580 if (n1 == i.operands)
3581 abort ();
3582 i.op[n].disps->X_add_number -= imm_size;
3583 }
520dc8e8 3584
29b0f896
AM		 3585 if (i.types[n] & Disp32S)
3586 sign = 1;
3e73aa7c 3587
29b0f896
AM		 3588 if (i.types[n] & (Disp16 | Disp64))
3589 {
3590 size = 2;
3591 if (i.types[n] & Disp64)
3592 size = 8;
3593 }
520dc8e8 3594
29b0f896 3595 p = frag_more (size);
2bbd9c25 3596 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3597 if (GOT_symbol
2bbd9c25 3598 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113
JB		 3599 && (((reloc_type == BFD_RELOC_32
3600 || reloc_type == BFD_RELOC_X86_64_32S)
3601 && (i.op[n].disps->X_op == O_symbol
3602 || (i.op[n].disps->X_op == O_add
3603 && ((symbol_get_value_expression
3604 (i.op[n].disps->X_op_symbol)->X_op)
3605 == O_subtract))))
3606 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3607 {
3608 offsetT add;
3609
3610 if (insn_start_frag == frag_now)
3611 add = (p - frag_now->fr_literal) - insn_start_off;
3612 else
3613 {
3614 fragS *fr;
3615
3616 add = insn_start_frag->fr_fix - insn_start_off;
3617 for (fr = insn_start_frag->fr_next;
3618 fr && fr != frag_now; fr = fr->fr_next)
3619 add += fr->fr_fix;
3620 add += p - frag_now->fr_literal;
3621 }
3622
4fa24527 3623 if (!object_64bit)
d6ab8113
JB		 3624 reloc_type = BFD_RELOC_386_GOTPC;
3625 else
3626 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25
JJ		 3627 i.op[n].disps->X_add_number += add;
3628 }
062cd5e7 3629 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3630 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3631 }
3632 }
3633 }
3634}
252b5132 3635
29b0f896 3636static void
2bbd9c25
JJ		 3637output_imm (insn_start_frag, insn_start_off)
3638 fragS *insn_start_frag;
3639 offsetT insn_start_off;
29b0f896
AM		 3640{
3641 char *p;
3642 unsigned int n;
252b5132 3643
29b0f896
AM		 3644 for (n = 0; n < i.operands; n++)
3645 {
3646 if (i.types[n] & Imm)
3647 {
3648 if (i.op[n].imms->X_op == O_constant)
3649 {
3650 int size;
3651 offsetT val;
b4cac588 3652
29b0f896
AM		 3653 size = 4;
3654 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3655 {
3656 size = 2;
3657 if (i.types[n] & (Imm8 | Imm8S))
3658 size = 1;
3659 else if (i.types[n] & Imm64)
3660 size = 8;
3661 }
3662 val = offset_in_range (i.op[n].imms->X_add_number,
3663 size);
3664 p = frag_more (size);
3665 md_number_to_chars (p, val, size);
3666 }
3667 else
3668 {
3669 /* Not absolute_section.
3670 Need a 32-bit fixup (don't support 8bit
3671 non-absolute imms). Try to support other
3672 sizes ... */
f86103b7 3673 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3674 int size = 4;
3675 int sign = 0;
3676
3677 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3678 && (i.suffix == QWORD_MNEM_SUFFIX
3679 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3680 sign = 1;
3681 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3682 {
3683 size = 2;
3684 if (i.types[n] & (Imm8 | Imm8S))
3685 size = 1;
3686 if (i.types[n] & Imm64)
3687 size = 8;
3688 }
520dc8e8 3689
29b0f896
AM		 3690 p = frag_more (size);
3691 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3692
2bbd9c25
JJ		 3693 /* This is tough to explain. We end up with this one if we
3694 * have operands that look like
3695 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3696 * obtain the absolute address of the GOT, and it is strongly
3697 * preferable from a performance point of view to avoid using
3698 * a runtime relocation for this. The actual sequence of
3699 * instructions often look something like:
3700 *
3701 * call .L66
3702 * .L66:
3703 * popl %ebx
3704 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3705 *
3706 * The call and pop essentially return the absolute address
3707 * of the label .L66 and store it in %ebx. The linker itself
3708 * will ultimately change the first operand of the addl so
3709 * that %ebx points to the GOT, but to keep things simple, the
3710 * .o file must have this operand set so that it generates not
3711 * the absolute address of .L66, but the absolute address of
3712 * itself. This allows the linker itself simply treat a GOTPC
3713 * relocation as asking for a pcrel offset to the GOT to be
3714 * added in, and the addend of the relocation is stored in the
3715 * operand field for the instruction itself.
3716 *
3717 * Our job here is to fix the operand so that it would add
3718 * the correct offset so that %ebx would point to itself. The
3719 * thing that is tricky is that .-.L66 will point to the
3720 * beginning of the instruction, so we need to further modify
3721 * the operand so that it will point to itself. There are
3722 * other cases where you have something like:
3723 *
3724 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3725 *
3726 * and here no correction would be required. Internally in
3727 * the assembler we treat operands of this form as not being
3728 * pcrel since the '.' is explicitly mentioned, and I wonder
3729 * whether it would simplify matters to do it this way. Who
3730 * knows. In earlier versions of the PIC patches, the
3731 * pcrel_adjust field was used to store the correction, but
3732 * since the expression is not pcrel, I felt it would be
3733 * confusing to do it this way. */
3734
d6ab8113
JB		 3735 if ((reloc_type == BFD_RELOC_32
3736 || reloc_type == BFD_RELOC_X86_64_32S)
29b0f896
AM		 3737 && GOT_symbol
3738 && GOT_symbol == i.op[n].imms->X_add_symbol
3739 && (i.op[n].imms->X_op == O_symbol
3740 || (i.op[n].imms->X_op == O_add
3741 && ((symbol_get_value_expression
3742 (i.op[n].imms->X_op_symbol)->X_op)
3743 == O_subtract))))
3744 {
2bbd9c25
JJ		 3745 offsetT add;
3746
3747 if (insn_start_frag == frag_now)
3748 add = (p - frag_now->fr_literal) - insn_start_off;
3749 else
3750 {
3751 fragS *fr;
3752
3753 add = insn_start_frag->fr_fix - insn_start_off;
3754 for (fr = insn_start_frag->fr_next;
3755 fr && fr != frag_now; fr = fr->fr_next)
3756 add += fr->fr_fix;
3757 add += p - frag_now->fr_literal;
3758 }
3759
4fa24527 3760 if (!object_64bit)
d6ab8113
JB		 3761 reloc_type = BFD_RELOC_386_GOTPC;
3762 else
3763 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3764 i.op[n].imms->X_add_number += add;
29b0f896 3765 }
29b0f896
AM		 3766 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3767 i.op[n].imms, 0, reloc_type);
3768 }
3769 }
3770 }
252b5132
RH		 3771}
3772\f
d182319b
JB		 3773/* x86_cons_fix_new is called via the expression parsing code when a
3774 reloc is needed. We use this hook to get the correct .got reloc. */
3775static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3776static int cons_sign = -1;
3777
3778void
3779x86_cons_fix_new (fragS *frag,
3780 unsigned int off,
3781 unsigned int len,
3782 expressionS *exp)
3783{
3784 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
3785
3786 got_reloc = NO_RELOC;
3787
3788#ifdef TE_PE
3789 if (exp->X_op == O_secrel)
3790 {
3791 exp->X_op = O_symbol;
3792 r = BFD_RELOC_32_SECREL;
3793 }
3794#endif
3795
3796 fix_new_exp (frag, off, len, exp, 0, r);
3797}
3798
718ddfc0
JB		 3799#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3800# define lex_got(reloc, adjust, types) NULL
3801#else
f3c180ae
AM		 3802/* Parse operands of the form
3803 <symbol>@GOTOFF+<nnn>
3804 and similar .plt or .got references.
3805
3806 If we find one, set up the correct relocation in RELOC and copy the
3807 input string, minus the `@GOTOFF' into a malloc'd buffer for
3808 parsing by the calling routine. Return this buffer, and if ADJUST
3809 is non-null set it to the length of the string we removed from the
3810 input line. Otherwise return NULL. */
3811static char *
3956db08
JB		 3812lex_got (enum bfd_reloc_code_real *reloc,
3813 int *adjust,
3814 unsigned int *types)
f3c180ae 3815{
f3c180ae
AM		 3816 static const struct {
3817 const char *str;
4fa24527 3818 const enum bfd_reloc_code_real rel[2];
3956db08 3819 const unsigned int types64;
f3c180ae 3820 } gotrel[] = {
4fa24527
JB		 3821 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3822 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3823 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3824 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3825 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3826 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3827 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3828 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3829 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3830 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3831 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3832 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
3833 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3834 };
3835 char *cp;
3836 unsigned int j;
3837
718ddfc0
JB		 3838 if (!IS_ELF)
3839 return NULL;
3840
f3c180ae
AM		 3841 for (cp = input_line_pointer; *cp != '@'; cp++)
3842 if (is_end_of_line[(unsigned char) *cp])
3843 return NULL;
3844
3845 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3846 {
3847 int len;
3848
3849 len = strlen (gotrel[j].str);
28f81592 3850 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 3851 {
4fa24527 3852 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 3853 {
28f81592
AM		 3854 int first, second;
3855 char *tmpbuf, *past_reloc;
f3c180ae 3856
4fa24527 3857 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 3858 if (adjust)
3859 *adjust = len;
f3c180ae 3860
3956db08
JB		 3861 if (types)
3862 {
3863 if (flag_code != CODE_64BIT)
3864 *types = Imm32|Disp32;
3865 else
3866 *types = gotrel[j].types64;
3867 }
3868
f3c180ae
AM		 3869 if (GOT_symbol == NULL)
3870 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3871
3872 /* Replace the relocation token with ' ', so that
3873 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3874
3875 /* The length of the first part of our input line. */
f3c180ae 3876 first = cp - input_line_pointer;
28f81592
AM		 3877
3878 /* The second part goes from after the reloc token until
3879 (and including) an end_of_line char. Don't use strlen
3880 here as the end_of_line char may not be a NUL. */
3881 past_reloc = cp + 1 + len;
3882 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3883 ;
3884 second = cp - past_reloc;
3885
3886 /* Allocate and copy string. The trailing NUL shouldn't
3887 be necessary, but be safe. */
3888 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3889 memcpy (tmpbuf, input_line_pointer, first);
3890 tmpbuf[first] = ' ';
28f81592
AM		 3891 memcpy (tmpbuf + first + 1, past_reloc, second);
3892 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3893 return tmpbuf;
3894 }
3895
4fa24527
JB		 3896 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3897 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 3898 return NULL;
3899 }
3900 }
3901
3902 /* Might be a symbol version string. Don't as_bad here. */
3903 return NULL;
3904}
3905
f3c180ae
AM		 3906void
3907x86_cons (exp, size)
3908 expressionS *exp;
3909 int size;
3910{
4fa24527 3911 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 3912 {
3913 /* Handle @GOTOFF and the like in an expression. */
3914 char *save;
3915 char *gotfree_input_line;
3916 int adjust;
3917
3918 save = input_line_pointer;
3956db08 3919 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 3920 if (gotfree_input_line)
3921 input_line_pointer = gotfree_input_line;
3922
3923 expression (exp);
3924
3925 if (gotfree_input_line)
3926 {
3927 /* expression () has merrily parsed up to the end of line,
3928 or a comma - in the wrong buffer. Transfer how far
3929 input_line_pointer has moved to the right buffer. */
3930 input_line_pointer = (save
3931 + (input_line_pointer - gotfree_input_line)
3932 + adjust);
3933 free (gotfree_input_line);
3934 }
3935 }
3936 else
3937 expression (exp);
3938}
3939#endif
3940
d182319b 3941static void signed_cons (int size)
6482c264 3942{
d182319b
JB		 3943 if (flag_code == CODE_64BIT)
3944 cons_sign = 1;
3945 cons (size);
3946 cons_sign = -1;
6482c264
NC		 3947}
3948
d182319b 3949#ifdef TE_PE
6482c264
NC		 3950static void
3951pe_directive_secrel (dummy)
3952 int dummy ATTRIBUTE_UNUSED;
3953{
3954 expressionS exp;
3955
3956 do
3957 {
3958 expression (&exp);
3959 if (exp.X_op == O_symbol)
3960 exp.X_op = O_secrel;
3961
3962 emit_expr (&exp, 4);
3963 }
3964 while (*input_line_pointer++ == ',');
3965
3966 input_line_pointer--;
3967 demand_empty_rest_of_line ();
3968}
6482c264
NC		 3969#endif
3970
252b5132
RH		 3971static int i386_immediate PARAMS ((char *));
3972
3973static int
3974i386_immediate (imm_start)
3975 char *imm_start;
3976{
3977 char *save_input_line_pointer;
f3c180ae 3978 char *gotfree_input_line;
252b5132 3979 segT exp_seg = 0;
47926f60 3980 expressionS *exp;
3956db08 3981 unsigned int types = ~0U;
252b5132
RH		 3982
3983 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3984 {
d0b47220 3985 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3986 return 0;
3987 }
3988
3989 exp = &im_expressions[i.imm_operands++];
520dc8e8 3990 i.op[this_operand].imms = exp;
252b5132
RH		 3991
3992 if (is_space_char (*imm_start))
3993 ++imm_start;
3994
3995 save_input_line_pointer = input_line_pointer;
3996 input_line_pointer = imm_start;
3997
3956db08 3998 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 3999 if (gotfree_input_line)
4000 input_line_pointer = gotfree_input_line;
252b5132
RH		 4001
4002 exp_seg = expression (exp);
4003
83183c0c 4004 SKIP_WHITESPACE ();
252b5132 4005 if (*input_line_pointer)
f3c180ae 4006 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4007
4008 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4009 if (gotfree_input_line)
4010 free (gotfree_input_line);
252b5132 4011
2daf4fd8 4012 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4013 {
47926f60 4014 /* Missing or bad expr becomes absolute 0. */
d0b47220 4015 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4016 imm_start);
252b5132
RH		 4017 exp->X_op = O_constant;
4018 exp->X_add_number = 0;
4019 exp->X_add_symbol = (symbolS *) 0;
4020 exp->X_op_symbol = (symbolS *) 0;
252b5132 4021 }
3e73aa7c 4022 else if (exp->X_op == O_constant)
252b5132 4023 {
47926f60 4024 /* Size it properly later. */
3e73aa7c
JH		 4025 i.types[this_operand] |= Imm64;
4026 /* If BFD64, sign extend val. */
4027 if (!use_rela_relocations)
4028 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4029 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4030 }
4c63da97 4031#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4032 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4033 && exp_seg != absolute_section
47926f60 4034 && exp_seg != text_section
24eab124
AM		 4035 && exp_seg != data_section
4036 && exp_seg != bss_section
4037 && exp_seg != undefined_section
f86103b7 4038 && !bfd_is_com_section (exp_seg))
252b5132 4039 {
d0b47220 4040 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4041 return 0;
4042 }
4043#endif
4044 else
4045 {
4046 /* This is an address. The size of the address will be
24eab124 4047 determined later, depending on destination register,
3e73aa7c
JH		 4048 suffix, or the default for the section. */
4049 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4050 i.types[this_operand] &= types;
252b5132
RH		 4051 }
4052
4053 return 1;
4054}
4055
551c1ca1 4056static char *i386_scale PARAMS ((char *));
252b5132 4057
551c1ca1 4058static char *
252b5132
RH		 4059i386_scale (scale)
4060 char *scale;
4061{
551c1ca1
AM		 4062 offsetT val;
4063 char *save = input_line_pointer;
252b5132 4064
551c1ca1
AM		 4065 input_line_pointer = scale;
4066 val = get_absolute_expression ();
4067
4068 switch (val)
252b5132 4069 {
551c1ca1 4070 case 1:
252b5132
RH		 4071 i.log2_scale_factor = 0;
4072 break;
551c1ca1 4073 case 2:
252b5132
RH		 4074 i.log2_scale_factor = 1;
4075 break;
551c1ca1 4076 case 4:
252b5132
RH		 4077 i.log2_scale_factor = 2;
4078 break;
551c1ca1 4079 case 8:
252b5132
RH		 4080 i.log2_scale_factor = 3;
4081 break;
4082 default:
a724f0f4
JB		 4083 {
4084 char sep = *input_line_pointer;
4085
4086 *input_line_pointer = '\0';
4087 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4088 scale);
4089 *input_line_pointer = sep;
4090 input_line_pointer = save;
4091 return NULL;
4092 }
252b5132 4093 }
29b0f896 4094 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4095 {
4096 as_warn (_("scale factor of %d without an index register"),
24eab124 4097 1 << i.log2_scale_factor);
252b5132
RH		 4098#if SCALE1_WHEN_NO_INDEX
4099 i.log2_scale_factor = 0;
4100#endif
4101 }
551c1ca1
AM		 4102 scale = input_line_pointer;
4103 input_line_pointer = save;
4104 return scale;
252b5132
RH		 4105}
4106
4107static int i386_displacement PARAMS ((char *, char *));
4108
4109static int
4110i386_displacement (disp_start, disp_end)
4111 char *disp_start;
4112 char *disp_end;
4113{
29b0f896 4114 expressionS *exp;
252b5132
RH		 4115 segT exp_seg = 0;
4116 char *save_input_line_pointer;
f3c180ae 4117 char *gotfree_input_line;
e05278af 4118 int bigdisp, override;
3956db08 4119 unsigned int types = Disp;
252b5132 4120
e05278af
JB		 4121 if ((i.types[this_operand] & JumpAbsolute)
4122 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4123 {
4124 bigdisp = Disp32;
4125 override = (i.prefix[ADDR_PREFIX] != 0);
4126 }
4127 else
4128 {
4129 /* For PC-relative branches, the width of the displacement
4130 is dependent upon data size, not address size. */
4131 bigdisp = 0;
4132 override = (i.prefix[DATA_PREFIX] != 0);
4133 }
3e73aa7c 4134 if (flag_code == CODE_64BIT)
7ecd2f8b 4135 {
e05278af
JB		 4136 if (!bigdisp)
4137 bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX)
4138 ? Disp16
4139 : Disp32S | Disp32;
4140 else if (!override)
3956db08 4141 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4142 }
e05278af
JB		 4143 else
4144 {
4145 if (!bigdisp)
4146 {
4147 if (!override)
4148 override = (i.suffix == (flag_code != CODE_16BIT
4149 ? WORD_MNEM_SUFFIX
4150 : LONG_MNEM_SUFFIX));
4151 bigdisp = Disp32;
4152 }
4153 if ((flag_code == CODE_16BIT) ^ override)
4154 bigdisp = Disp16;
4155 }
252b5132
RH		 4156 i.types[this_operand] |= bigdisp;
4157
4158 exp = &disp_expressions[i.disp_operands];
520dc8e8 4159 i.op[this_operand].disps = exp;
252b5132
RH		 4160 i.disp_operands++;
4161 save_input_line_pointer = input_line_pointer;
4162 input_line_pointer = disp_start;
4163 END_STRING_AND_SAVE (disp_end);
4164
4165#ifndef GCC_ASM_O_HACK
4166#define GCC_ASM_O_HACK 0
4167#endif
4168#if GCC_ASM_O_HACK
4169 END_STRING_AND_SAVE (disp_end + 1);
4170 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4171 && displacement_string_end[-1] == '+')
252b5132
RH		 4172 {
4173 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4174 constraint within gcc asm statements.
4175 For instance:
4176
4177 #define _set_tssldt_desc(n,addr,limit,type) \
4178 __asm__ __volatile__ ( \
4179 "movw %w2,%0\n\t" \
4180 "movw %w1,2+%0\n\t" \
4181 "rorl $16,%1\n\t" \
4182 "movb %b1,4+%0\n\t" \
4183 "movb %4,5+%0\n\t" \
4184 "movb $0,6+%0\n\t" \
4185 "movb %h1,7+%0\n\t" \
4186 "rorl $16,%1" \
4187 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4188
4189 This works great except that the output assembler ends
4190 up looking a bit weird if it turns out that there is
4191 no offset. You end up producing code that looks like:
4192
4193 #APP
4194 movw $235,(%eax)
4195 movw %dx,2+(%eax)
4196 rorl $16,%edx
4197 movb %dl,4+(%eax)
4198 movb $137,5+(%eax)
4199 movb $0,6+(%eax)
4200 movb %dh,7+(%eax)
4201 rorl $16,%edx
4202 #NO_APP
4203
47926f60 4204 So here we provide the missing zero. */
24eab124
AM		 4205
4206 *displacement_string_end = '0';
252b5132
RH		 4207 }
4208#endif
3956db08 4209 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4210 if (gotfree_input_line)
4211 input_line_pointer = gotfree_input_line;
252b5132 4212
24eab124 4213 exp_seg = expression (exp);
252b5132 4214
636c26b0
AM		 4215 SKIP_WHITESPACE ();
4216 if (*input_line_pointer)
4217 as_bad (_("junk `%s' after expression"), input_line_pointer);
4218#if GCC_ASM_O_HACK
4219 RESTORE_END_STRING (disp_end + 1);
4220#endif
4221 RESTORE_END_STRING (disp_end);
4222 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4223 if (gotfree_input_line)
4224 free (gotfree_input_line);
636c26b0 4225
24eab124
AM		 4226 /* We do this to make sure that the section symbol is in
4227 the symbol table. We will ultimately change the relocation
47926f60 4228 to be relative to the beginning of the section. */
1ae12ab7 4229 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4230 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4231 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4232 {
636c26b0
AM		 4233 if (exp->X_op != O_symbol)
4234 {
4235 as_bad (_("bad expression used with @%s"),
4236 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4237 ? "GOTPCREL"
4238 : "GOTOFF"));
4239 return 0;
4240 }
4241
e5cb08ac 4242 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4243 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4244 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4245 exp->X_op = O_subtract;
4246 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4247 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4248 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4249 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4250 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4251 else
29b0f896 4252 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4253 }
252b5132 4254
2daf4fd8
AM		 4255 if (exp->X_op == O_absent || exp->X_op == O_big)
4256 {
47926f60 4257 /* Missing or bad expr becomes absolute 0. */
d0b47220 4258 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4259 disp_start);
4260 exp->X_op = O_constant;
4261 exp->X_add_number = 0;
4262 exp->X_add_symbol = (symbolS *) 0;
4263 exp->X_op_symbol = (symbolS *) 0;
4264 }
4265
4c63da97 4266#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4267 if (exp->X_op != O_constant
45288df1 4268 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4269 && exp_seg != absolute_section
45288df1
AM		 4270 && exp_seg != text_section
4271 && exp_seg != data_section
4272 && exp_seg != bss_section
31312f95 4273 && exp_seg != undefined_section
f86103b7 4274 && !bfd_is_com_section (exp_seg))
24eab124 4275 {
d0b47220 4276 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4277 return 0;
4278 }
252b5132 4279#endif
3956db08
JB		 4280
4281 if (!(i.types[this_operand] & ~Disp))
4282 i.types[this_operand] &= types;
4283
252b5132
RH		 4284 return 1;
4285}
4286
e5cb08ac 4287static int i386_index_check PARAMS ((const char *));
252b5132 4288
eecb386c 4289/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4290 Return 1 on success, 0 on a failure. */
4291
252b5132 4292static int
eecb386c
AM		 4293i386_index_check (operand_string)
4294 const char *operand_string;
252b5132 4295{
3e73aa7c 4296 int ok;
24eab124 4297#if INFER_ADDR_PREFIX
eecb386c
AM		 4298 int fudged = 0;
4299
24eab124
AM		 4300 tryprefix:
4301#endif
3e73aa7c 4302 ok = 1;
30123838
JB		 4303 if ((current_templates->start->cpu_flags & CpuSVME)
4304 && current_templates->end[-1].operand_types[0] == AnyMem)
4305 {
4306 /* Memory operands of SVME insns are special in that they only allow
4307 rAX as their memory address and ignore any segment override. */
4308 unsigned RegXX;
4309
4310 /* SKINIT is even more restrictive: it always requires EAX. */
4311 if (strcmp (current_templates->start->name, "skinit") == 0)
4312 RegXX = Reg32;
4313 else if (flag_code == CODE_64BIT)
4314 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4315 else
4316 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4317 ? Reg16
4318 : Reg32;
4319 if (!i.base_reg
4320 || !(i.base_reg->reg_type & Acc)
4321 || !(i.base_reg->reg_type & RegXX)
4322 || i.index_reg
4323 || (i.types[0] & Disp))
4324 ok = 0;
4325 }
4326 else if (flag_code == CODE_64BIT)
20f0a1fc
NC		 4327 {
4328 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4329
4330 if ((i.base_reg
4331 && ((i.base_reg->reg_type & RegXX) == 0)
4332 && (i.base_reg->reg_type != BaseIndex
4333 || i.index_reg))
4334 || (i.index_reg
4335 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4336 != (RegXX | BaseIndex))))
4337 ok = 0;
3e73aa7c
JH		 4338 }
4339 else
4340 {
4341 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4342 {
4343 /* 16bit checks. */
4344 if ((i.base_reg
29b0f896
AM		 4345 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4346 != (Reg16 | BaseIndex)))
3e73aa7c 4347 || (i.index_reg
29b0f896
AM		 4348 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4349 != (Reg16 | BaseIndex))
4350 || !(i.base_reg
4351 && i.base_reg->reg_num < 6
4352 && i.index_reg->reg_num >= 6
4353 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4354 ok = 0;
4355 }
4356 else
e5cb08ac 4357 {
3e73aa7c
JH		 4358 /* 32bit checks. */
4359 if ((i.base_reg
4360 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4361 || (i.index_reg
29b0f896
AM		 4362 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4363 != (Reg32 | BaseIndex))))
e5cb08ac 4364 ok = 0;
3e73aa7c
JH		 4365 }
4366 }
4367 if (!ok)
24eab124
AM		 4368 {
4369#if INFER_ADDR_PREFIX
20f0a1fc 4370 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4371 {
4372 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4373 i.prefixes += 1;
b23bac36
AM		 4374 /* Change the size of any displacement too. At most one of
4375 Disp16 or Disp32 is set.
4376 FIXME. There doesn't seem to be any real need for separate
4377 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4378 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4379 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4380 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4381 fudged = 1;
24eab124
AM		 4382 goto tryprefix;
4383 }
eecb386c
AM		 4384 if (fudged)
4385 as_bad (_("`%s' is not a valid base/index expression"),
4386 operand_string);
4387 else
c388dee8 4388#endif
eecb386c
AM		 4389 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4390 operand_string,
3e73aa7c 4391 flag_code_names[flag_code]);
24eab124 4392 }
20f0a1fc 4393 return ok;
24eab124 4394}
252b5132 4395
252b5132 4396/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4397 on error. */
252b5132 4398
252b5132
RH		 4399static int
4400i386_operand (operand_string)
4401 char *operand_string;
4402{
af6bdddf
AM		 4403 const reg_entry *r;
4404 char *end_op;
24eab124 4405 char *op_string = operand_string;
252b5132 4406
24eab124 4407 if (is_space_char (*op_string))
252b5132
RH		 4408 ++op_string;
4409
24eab124 4410 /* We check for an absolute prefix (differentiating,
47926f60 4411 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4412 if (*op_string == ABSOLUTE_PREFIX)
4413 {
4414 ++op_string;
4415 if (is_space_char (*op_string))
4416 ++op_string;
4417 i.types[this_operand] |= JumpAbsolute;
4418 }
252b5132 4419
47926f60 4420 /* Check if operand is a register. */
4d1bb795 4421 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4422 {
24eab124
AM		 4423 /* Check for a segment override by searching for ':' after a
4424 segment register. */
4425 op_string = end_op;
4426 if (is_space_char (*op_string))
4427 ++op_string;
4428 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4429 {
4430 switch (r->reg_num)
4431 {
4432 case 0:
4433 i.seg[i.mem_operands] = &es;
4434 break;
4435 case 1:
4436 i.seg[i.mem_operands] = &cs;
4437 break;
4438 case 2:
4439 i.seg[i.mem_operands] = &ss;
4440 break;
4441 case 3:
4442 i.seg[i.mem_operands] = &ds;
4443 break;
4444 case 4:
4445 i.seg[i.mem_operands] = &fs;
4446 break;
4447 case 5:
4448 i.seg[i.mem_operands] = &gs;
4449 break;
4450 }
252b5132 4451
24eab124 4452 /* Skip the ':' and whitespace. */
252b5132
RH		 4453 ++op_string;
4454 if (is_space_char (*op_string))
24eab124 4455 ++op_string;
252b5132 4456
24eab124
AM		 4457 if (!is_digit_char (*op_string)
4458 && !is_identifier_char (*op_string)
4459 && *op_string != '('
4460 && *op_string != ABSOLUTE_PREFIX)
4461 {
4462 as_bad (_("bad memory operand `%s'"), op_string);
4463 return 0;
4464 }
47926f60 4465 /* Handle case of %es:*foo. */
24eab124
AM		 4466 if (*op_string == ABSOLUTE_PREFIX)
4467 {
4468 ++op_string;
4469 if (is_space_char (*op_string))
4470 ++op_string;
4471 i.types[this_operand] |= JumpAbsolute;
4472 }
4473 goto do_memory_reference;
4474 }
4475 if (*op_string)
4476 {
d0b47220 4477 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4478 return 0;
4479 }
4480 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4481 i.op[this_operand].regs = r;
24eab124
AM		 4482 i.reg_operands++;
4483 }
af6bdddf
AM		 4484 else if (*op_string == REGISTER_PREFIX)
4485 {
4486 as_bad (_("bad register name `%s'"), op_string);
4487 return 0;
4488 }
24eab124 4489 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4490 {
24eab124
AM		 4491 ++op_string;
4492 if (i.types[this_operand] & JumpAbsolute)
4493 {
d0b47220 4494 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4495 return 0;
4496 }
4497 if (!i386_immediate (op_string))
4498 return 0;
4499 }
4500 else if (is_digit_char (*op_string)
4501 || is_identifier_char (*op_string)
e5cb08ac 4502 || *op_string == '(')
24eab124 4503 {
47926f60 4504 /* This is a memory reference of some sort. */
af6bdddf 4505 char *base_string;
252b5132 4506
47926f60 4507 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4508 char *displacement_string_start;
4509 char *displacement_string_end;
252b5132 4510
24eab124 4511 do_memory_reference:
24eab124
AM		 4512 if ((i.mem_operands == 1
4513 && (current_templates->start->opcode_modifier & IsString) == 0)
4514 || i.mem_operands == 2)
4515 {
4516 as_bad (_("too many memory references for `%s'"),
4517 current_templates->start->name);
4518 return 0;
4519 }
252b5132 4520
24eab124
AM		 4521 /* Check for base index form. We detect the base index form by
4522 looking for an ')' at the end of the operand, searching
4523 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4524 after the '('. */
af6bdddf 4525 base_string = op_string + strlen (op_string);
c3332e24 4526
af6bdddf
AM		 4527 --base_string;
4528 if (is_space_char (*base_string))
4529 --base_string;
252b5132 4530
47926f60 4531 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4532 displacement_string_start = op_string;
4533 displacement_string_end = base_string + 1;
252b5132 4534
24eab124
AM		 4535 if (*base_string == ')')
4536 {
af6bdddf 4537 char *temp_string;
24eab124
AM		 4538 unsigned int parens_balanced = 1;
4539 /* We've already checked that the number of left & right ()'s are
47926f60 4540 equal, so this loop will not be infinite. */
24eab124
AM		 4541 do
4542 {
4543 base_string--;
4544 if (*base_string == ')')
4545 parens_balanced++;
4546 if (*base_string == '(')
4547 parens_balanced--;
4548 }
4549 while (parens_balanced);
c3332e24 4550
af6bdddf 4551 temp_string = base_string;
c3332e24 4552
24eab124 4553 /* Skip past '(' and whitespace. */
252b5132
RH		 4554 ++base_string;
4555 if (is_space_char (*base_string))
24eab124 4556 ++base_string;
252b5132 4557
af6bdddf 4558 if (*base_string == ','
4d1bb795 4559 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4560 {
af6bdddf 4561 displacement_string_end = temp_string;
252b5132 4562
af6bdddf 4563 i.types[this_operand] |= BaseIndex;
252b5132 4564
af6bdddf 4565 if (i.base_reg)
24eab124 4566 {
24eab124
AM		 4567 base_string = end_op;
4568 if (is_space_char (*base_string))
4569 ++base_string;
af6bdddf
AM		 4570 }
4571
4572 /* There may be an index reg or scale factor here. */
4573 if (*base_string == ',')
4574 {
4575 ++base_string;
4576 if (is_space_char (*base_string))
4577 ++base_string;
4578
4d1bb795 4579 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4580 {
af6bdddf 4581 base_string = end_op;
24eab124
AM		 4582 if (is_space_char (*base_string))
4583 ++base_string;
af6bdddf
AM		 4584 if (*base_string == ',')
4585 {
4586 ++base_string;
4587 if (is_space_char (*base_string))
4588 ++base_string;
4589 }
e5cb08ac 4590 else if (*base_string != ')')
af6bdddf
AM		 4591 {
4592 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4593 operand_string);
4594 return 0;
4595 }
24eab124 4596 }
af6bdddf 4597 else if (*base_string == REGISTER_PREFIX)
24eab124 4598 {
af6bdddf 4599 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4600 return 0;
4601 }
252b5132 4602
47926f60 4603 /* Check for scale factor. */
551c1ca1 4604 if (*base_string != ')')
af6bdddf 4605 {
551c1ca1
AM		 4606 char *end_scale = i386_scale (base_string);
4607
4608 if (!end_scale)
af6bdddf 4609 return 0;
24eab124 4610
551c1ca1 4611 base_string = end_scale;
af6bdddf
AM		 4612 if (is_space_char (*base_string))
4613 ++base_string;
4614 if (*base_string != ')')
4615 {
4616 as_bad (_("expecting `)' after scale factor in `%s'"),
4617 operand_string);
4618 return 0;
4619 }
4620 }
4621 else if (!i.index_reg)
24eab124 4622 {
af6bdddf
AM		 4623 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4624 *base_string);
24eab124
AM		 4625 return 0;
4626 }
4627 }
af6bdddf 4628 else if (*base_string != ')')
24eab124 4629 {
af6bdddf
AM		 4630 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4631 operand_string);
24eab124
AM		 4632 return 0;
4633 }
c3332e24 4634 }
af6bdddf 4635 else if (*base_string == REGISTER_PREFIX)
c3332e24 4636 {
af6bdddf 4637 as_bad (_("bad register name `%s'"), base_string);
24eab124 4638 return 0;
c3332e24 4639 }
24eab124
AM		 4640 }
4641
4642 /* If there's an expression beginning the operand, parse it,
4643 assuming displacement_string_start and
4644 displacement_string_end are meaningful. */
4645 if (displacement_string_start != displacement_string_end)
4646 {
4647 if (!i386_displacement (displacement_string_start,
4648 displacement_string_end))
4649 return 0;
4650 }
4651
4652 /* Special case for (%dx) while doing input/output op. */
4653 if (i.base_reg
4654 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4655 && i.index_reg == 0
4656 && i.log2_scale_factor == 0
4657 && i.seg[i.mem_operands] == 0
4658 && (i.types[this_operand] & Disp) == 0)
4659 {
4660 i.types[this_operand] = InOutPortReg;
4661 return 1;
4662 }
4663
eecb386c
AM		 4664 if (i386_index_check (operand_string) == 0)
4665 return 0;
24eab124
AM		 4666 i.mem_operands++;
4667 }
4668 else
ce8a8b2f
AM		 4669 {
4670 /* It's not a memory operand; argh! */
24eab124
AM		 4671 as_bad (_("invalid char %s beginning operand %d `%s'"),
4672 output_invalid (*op_string),
4673 this_operand + 1,
4674 op_string);
4675 return 0;
4676 }
47926f60 4677 return 1; /* Normal return. */
252b5132
RH		 4678}
4679\f
ee7fcc42
AM		 4680/* md_estimate_size_before_relax()
4681
4682 Called just before relax() for rs_machine_dependent frags. The x86
4683 assembler uses these frags to handle variable size jump
4684 instructions.
4685
4686 Any symbol that is now undefined will not become defined.
4687 Return the correct fr_subtype in the frag.
4688 Return the initial "guess for variable size of frag" to caller.
4689 The guess is actually the growth beyond the fixed part. Whatever
4690 we do to grow the fixed or variable part contributes to our
4691 returned value. */
4692
252b5132
RH		 4693int
4694md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4695 fragS *fragP;
4696 segT segment;
252b5132 4697{
252b5132 4698 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4699 check for un-relaxable symbols. On an ELF system, we can't relax
4700 an externally visible symbol, because it may be overridden by a
4701 shared library. */
4702 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4703#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4704 || (IS_ELF
31312f95
AM		 4705 && (S_IS_EXTERNAL (fragP->fr_symbol)
4706 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4707#endif
4708 )
252b5132 4709 {
b98ef147
AM		 4710 /* Symbol is undefined in this segment, or we need to keep a
4711 reloc so that weak symbols can be overridden. */
4712 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4713 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4714 unsigned char *opcode;
4715 int old_fr_fix;
f6af82bd 4716
ee7fcc42
AM		 4717 if (fragP->fr_var != NO_RELOC)
4718 reloc_type = fragP->fr_var;
b98ef147 4719 else if (size == 2)
f6af82bd
AM		 4720 reloc_type = BFD_RELOC_16_PCREL;
4721 else
4722 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4723
ee7fcc42
AM		 4724 old_fr_fix = fragP->fr_fix;
4725 opcode = (unsigned char *) fragP->fr_opcode;
4726
fddf5b5b 4727 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4728 {
fddf5b5b
AM		 4729 case UNCOND_JUMP:
4730 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4731 opcode[0] = 0xe9;
252b5132 4732 fragP->fr_fix += size;
062cd5e7
AS		 4733 fix_new (fragP, old_fr_fix, size,
4734 fragP->fr_symbol,
4735 fragP->fr_offset, 1,
4736 reloc_type);
252b5132
RH		 4737 break;
4738
fddf5b5b 4739 case COND_JUMP86:
412167cb
AM		 4740 if (size == 2
4741 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4742 {
4743 /* Negate the condition, and branch past an
4744 unconditional jump. */
4745 opcode[0] ^= 1;
4746 opcode[1] = 3;
4747 /* Insert an unconditional jump. */
4748 opcode[2] = 0xe9;
4749 /* We added two extra opcode bytes, and have a two byte
4750 offset. */
4751 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4752 fix_new (fragP, old_fr_fix + 2, 2,
4753 fragP->fr_symbol,
4754 fragP->fr_offset, 1,
4755 reloc_type);
fddf5b5b
AM		 4756 break;
4757 }
4758 /* Fall through. */
4759
4760 case COND_JUMP:
412167cb
AM		 4761 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4762 {
3e02c1cc
AM		 4763 fixS *fixP;
4764
412167cb 4765 fragP->fr_fix += 1;
3e02c1cc
AM		 4766 fixP = fix_new (fragP, old_fr_fix, 1,
4767 fragP->fr_symbol,
4768 fragP->fr_offset, 1,
4769 BFD_RELOC_8_PCREL);
4770 fixP->fx_signed = 1;
412167cb
AM		 4771 break;
4772 }
93c2a809 4773
24eab124 4774 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4775 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4776 opcode[1] = opcode[0] + 0x10;
f6af82bd 4777 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4778 /* We've added an opcode byte. */
4779 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4780 fix_new (fragP, old_fr_fix + 1, size,
4781 fragP->fr_symbol,
4782 fragP->fr_offset, 1,
4783 reloc_type);
252b5132 4784 break;
fddf5b5b
AM		 4785
4786 default:
4787 BAD_CASE (fragP->fr_subtype);
4788 break;
252b5132
RH		 4789 }
4790 frag_wane (fragP);
ee7fcc42 4791 return fragP->fr_fix - old_fr_fix;
252b5132 4792 }
93c2a809 4793
93c2a809
AM		 4794 /* Guess size depending on current relax state. Initially the relax
4795 state will correspond to a short jump and we return 1, because
4796 the variable part of the frag (the branch offset) is one byte
4797 long. However, we can relax a section more than once and in that
4798 case we must either set fr_subtype back to the unrelaxed state,
4799 or return the value for the appropriate branch. */
4800 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4801}
4802
47926f60
KH		 4803/* Called after relax() is finished.
4804
4805 In: Address of frag.
4806 fr_type == rs_machine_dependent.
4807 fr_subtype is what the address relaxed to.
4808
4809 Out: Any fixSs and constants are set up.
4810 Caller will turn frag into a ".space 0". */
4811
252b5132
RH		 4812void
4813md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4814 bfd *abfd ATTRIBUTE_UNUSED;
4815 segT sec ATTRIBUTE_UNUSED;
29b0f896 4816 fragS *fragP;
252b5132 4817{
29b0f896 4818 unsigned char *opcode;
252b5132 4819 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4820 offsetT target_address;
4821 offsetT opcode_address;
252b5132 4822 unsigned int extension = 0;
847f7ad4 4823 offsetT displacement_from_opcode_start;
252b5132
RH		 4824
4825 opcode = (unsigned char *) fragP->fr_opcode;
4826
47926f60 4827 /* Address we want to reach in file space. */
252b5132 4828 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4829
47926f60 4830 /* Address opcode resides at in file space. */
252b5132
RH		 4831 opcode_address = fragP->fr_address + fragP->fr_fix;
4832
47926f60 4833 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4834 displacement_from_opcode_start = target_address - opcode_address;
4835
fddf5b5b 4836 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4837 {
47926f60
KH		 4838 /* Don't have to change opcode. */
4839 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4840 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4841 }
4842 else
4843 {
4844 if (no_cond_jump_promotion
4845 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4846 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4847
fddf5b5b
AM		 4848 switch (fragP->fr_subtype)
4849 {
4850 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4851 extension = 4; /* 1 opcode + 4 displacement */
4852 opcode[0] = 0xe9;
4853 where_to_put_displacement = &opcode[1];
4854 break;
252b5132 4855
fddf5b5b
AM		 4856 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4857 extension = 2; /* 1 opcode + 2 displacement */
4858 opcode[0] = 0xe9;
4859 where_to_put_displacement = &opcode[1];
4860 break;
252b5132 4861
fddf5b5b
AM		 4862 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4863 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4864 extension = 5; /* 2 opcode + 4 displacement */
4865 opcode[1] = opcode[0] + 0x10;
4866 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4867 where_to_put_displacement = &opcode[2];
4868 break;
252b5132 4869
fddf5b5b
AM		 4870 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4871 extension = 3; /* 2 opcode + 2 displacement */
4872 opcode[1] = opcode[0] + 0x10;
4873 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4874 where_to_put_displacement = &opcode[2];
4875 break;
252b5132 4876
fddf5b5b
AM		 4877 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4878 extension = 4;
4879 opcode[0] ^= 1;
4880 opcode[1] = 3;
4881 opcode[2] = 0xe9;
4882 where_to_put_displacement = &opcode[3];
4883 break;
4884
4885 default:
4886 BAD_CASE (fragP->fr_subtype);
4887 break;
4888 }
252b5132 4889 }
fddf5b5b 4890
47926f60 4891 /* Now put displacement after opcode. */
252b5132
RH		 4892 md_number_to_chars ((char *) where_to_put_displacement,
4893 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4894 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4895 fragP->fr_fix += extension;
4896}
4897\f
47926f60
KH		 4898/* Size of byte displacement jmp. */
4899int md_short_jump_size = 2;
4900
4901/* Size of dword displacement jmp. */
4902int md_long_jump_size = 5;
252b5132 4903
252b5132
RH		 4904void
4905md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4906 char *ptr;
4907 addressT from_addr, to_addr;
ab9da554
ILT		 4908 fragS *frag ATTRIBUTE_UNUSED;
4909 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4910{
847f7ad4 4911 offsetT offset;
252b5132
RH		 4912
4913 offset = to_addr - (from_addr + 2);
47926f60
KH		 4914 /* Opcode for byte-disp jump. */
4915 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4916 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4917}
4918
4919void
4920md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4921 char *ptr;
4922 addressT from_addr, to_addr;
a38cf1db
AM		 4923 fragS *frag ATTRIBUTE_UNUSED;
4924 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4925{
847f7ad4 4926 offsetT offset;
252b5132 4927
a38cf1db
AM		 4928 offset = to_addr - (from_addr + 5);
4929 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4930 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4931}
4932\f
4933/* Apply a fixup (fixS) to segment data, once it has been determined
4934 by our caller that we have all the info we need to fix it up.
4935
4936 On the 386, immediates, displacements, and data pointers are all in
4937 the same (little-endian) format, so we don't need to care about which
4938 we are handling. */
4939
94f592af 4940void
55cf6793 4941md_apply_fix (fixP, valP, seg)
47926f60
KH		 4942 /* The fix we're to put in. */
4943 fixS *fixP;
47926f60 4944 /* Pointer to the value of the bits. */
c6682705 4945 valueT *valP;
47926f60
KH		 4946 /* Segment fix is from. */
4947 segT seg ATTRIBUTE_UNUSED;
252b5132 4948{
94f592af 4949 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4950 valueT value = *valP;
252b5132 4951
f86103b7 4952#if !defined (TE_Mach)
93382f6d
AM		 4953 if (fixP->fx_pcrel)
4954 {
4955 switch (fixP->fx_r_type)
4956 {
5865bb77
ILT		 4957 default:
4958 break;
4959
d6ab8113
JB		 4960 case BFD_RELOC_64:
4961 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4962 break;
93382f6d 4963 case BFD_RELOC_32:
ae8887b5 4964 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4965 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4966 break;
4967 case BFD_RELOC_16:
4968 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4969 break;
4970 case BFD_RELOC_8:
4971 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4972 break;
4973 }
4974 }
252b5132 4975
a161fe53 4976 if (fixP->fx_addsy != NULL
31312f95 4977 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 4978 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 4979 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4980 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4981 && !use_rela_relocations)
252b5132 4982 {
31312f95
AM		 4983 /* This is a hack. There should be a better way to handle this.
4984 This covers for the fact that bfd_install_relocation will
4985 subtract the current location (for partial_inplace, PC relative
4986 relocations); see more below. */
252b5132 4987#ifndef OBJ_AOUT
718ddfc0 4988 if (IS_ELF
252b5132
RH		 4989#ifdef TE_PE
4990 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4991#endif
4992 )
4993 value += fixP->fx_where + fixP->fx_frag->fr_address;
4994#endif
4995#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4996 if (IS_ELF)
252b5132 4997 {
6539b54b 4998 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4999
6539b54b 5000 if ((sym_seg == seg
2f66722d 5001 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5002 && sym_seg != absolute_section))
ae6063d4 5003 && !generic_force_reloc (fixP))
2f66722d
AM		 5004 {
5005 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5006 bfd_install_relocation subtracts them out again. I think
5007 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5008 it. FIXME. */
5009 value += fixP->fx_where + fixP->fx_frag->fr_address;
5010 }
252b5132
RH		 5011 }
5012#endif
5013#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5014 /* For some reason, the PE format does not store a
5015 section address offset for a PC relative symbol. */
5016 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5017 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5018 value += md_pcrel_from (fixP);
5019#endif
5020 }
5021
5022 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5023 and we must not disappoint it. */
252b5132 5024#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5025 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5026 switch (fixP->fx_r_type)
5027 {
5028 case BFD_RELOC_386_PLT32:
3e73aa7c 5029 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5030 /* Make the jump instruction point to the address of the operand. At
5031 runtime we merely add the offset to the actual PLT entry. */
5032 value = -4;
5033 break;
31312f95 5034
13ae64f3
JJ		 5035 case BFD_RELOC_386_TLS_GD:
5036 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5037 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5038 case BFD_RELOC_386_TLS_IE:
5039 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 5040 case BFD_RELOC_X86_64_TLSGD:
5041 case BFD_RELOC_X86_64_TLSLD:
5042 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 5043 value = 0; /* Fully resolved at runtime. No addend. */
5044 /* Fallthrough */
5045 case BFD_RELOC_386_TLS_LE:
5046 case BFD_RELOC_386_TLS_LDO_32:
5047 case BFD_RELOC_386_TLS_LE_32:
5048 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5049 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5050 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5051 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5052 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5053 break;
5054
5055 case BFD_RELOC_386_GOT32:
5056 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5057 value = 0; /* Fully resolved at runtime. No addend. */
5058 break;
47926f60
KH		 5059
5060 case BFD_RELOC_VTABLE_INHERIT:
5061 case BFD_RELOC_VTABLE_ENTRY:
5062 fixP->fx_done = 0;
94f592af 5063 return;
47926f60
KH		 5064
5065 default:
5066 break;
5067 }
5068#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5069 *valP = value;
f86103b7 5070#endif /* !defined (TE_Mach) */
3e73aa7c 5071
3e73aa7c 5072 /* Are we finished with this relocation now? */
c6682705 5073 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5074 fixP->fx_done = 1;
5075 else if (use_rela_relocations)
5076 {
5077 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5078 /* Remember value for tc_gen_reloc. */
5079 fixP->fx_addnumber = value;
3e73aa7c
JH		 5080 value = 0;
5081 }
f86103b7 5082
94f592af 5083 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5084}
252b5132 5085\f
252b5132
RH		 5086#define MAX_LITTLENUMS 6
5087
47926f60
KH		 5088/* Turn the string pointed to by litP into a floating point constant
5089 of type TYPE, and emit the appropriate bytes. The number of
5090 LITTLENUMS emitted is stored in *SIZEP. An error message is
5091 returned, or NULL on OK. */
5092
252b5132
RH		 5093char *
5094md_atof (type, litP, sizeP)
2ab9b79e 5095 int type;
252b5132
RH		 5096 char *litP;
5097 int *sizeP;
5098{
5099 int prec;
5100 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5101 LITTLENUM_TYPE *wordP;
5102 char *t;
5103
5104 switch (type)
5105 {
5106 case 'f':
5107 case 'F':
5108 prec = 2;
5109 break;
5110
5111 case 'd':
5112 case 'D':
5113 prec = 4;
5114 break;
5115
5116 case 'x':
5117 case 'X':
5118 prec = 5;
5119 break;
5120
5121 default:
5122 *sizeP = 0;
5123 return _("Bad call to md_atof ()");
5124 }
5125 t = atof_ieee (input_line_pointer, type, words);
5126 if (t)
5127 input_line_pointer = t;
5128
5129 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5130 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5131 the bigendian 386. */
5132 for (wordP = words + prec - 1; prec--;)
5133 {
5134 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5135 litP += sizeof (LITTLENUM_TYPE);
5136 }
5137 return 0;
5138}
5139\f
87c245cc 5140static char output_invalid_buf[8];
252b5132 5141
252b5132
RH		 5142static char *
5143output_invalid (c)
5144 int c;
5145{
3882b010 5146 if (ISPRINT (c))
252b5132
RH		 5147 sprintf (output_invalid_buf, "'%c'", c);
5148 else
5149 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5150 return output_invalid_buf;
5151}
5152
af6bdddf 5153/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5154
5155static const reg_entry *
4d1bb795 5156parse_real_register (char *reg_string, char **end_op)
252b5132 5157{
af6bdddf
AM		 5158 char *s = reg_string;
5159 char *p;
252b5132
RH		 5160 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5161 const reg_entry *r;
5162
5163 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5164 if (*s == REGISTER_PREFIX)
5165 ++s;
5166
5167 if (is_space_char (*s))
5168 ++s;
5169
5170 p = reg_name_given;
af6bdddf 5171 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5172 {
5173 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5174 return (const reg_entry *) NULL;
5175 s++;
252b5132
RH		 5176 }
5177
6588847e
DN		 5178 /* For naked regs, make sure that we are not dealing with an identifier.
5179 This prevents confusing an identifier like `eax_var' with register
5180 `eax'. */
5181 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5182 return (const reg_entry *) NULL;
5183
af6bdddf 5184 *end_op = s;
252b5132
RH		 5185
5186 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5187
5f47d35b 5188 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5189 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5190 {
5f47d35b
AM		 5191 if (is_space_char (*s))
5192 ++s;
5193 if (*s == '(')
5194 {
af6bdddf 5195 ++s;
5f47d35b
AM		 5196 if (is_space_char (*s))
5197 ++s;
5198 if (*s >= '0' && *s <= '7')
5199 {
5200 r = &i386_float_regtab[*s - '0'];
af6bdddf 5201 ++s;
5f47d35b
AM		 5202 if (is_space_char (*s))
5203 ++s;
5204 if (*s == ')')
5205 {
5206 *end_op = s + 1;
5207 return r;
5208 }
5f47d35b 5209 }
47926f60 5210 /* We have "%st(" then garbage. */
5f47d35b
AM		 5211 return (const reg_entry *) NULL;
5212 }
5213 }
5214
1ae00879 5215 if (r != NULL
20f0a1fc 5216 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5217 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5218 && flag_code != CODE_64BIT)
20f0a1fc 5219 return (const reg_entry *) NULL;
1ae00879 5220
252b5132
RH		 5221 return r;
5222}
4d1bb795
JB		 5223
5224/* REG_STRING starts *before* REGISTER_PREFIX. */
5225
5226static const reg_entry *
5227parse_register (char *reg_string, char **end_op)
5228{
5229 const reg_entry *r;
5230
5231 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5232 r = parse_real_register (reg_string, end_op);
5233 else
5234 r = NULL;
5235 if (!r)
5236 {
5237 char *save = input_line_pointer;
5238 char c;
5239 symbolS *symbolP;
5240
5241 input_line_pointer = reg_string;
5242 c = get_symbol_end ();
5243 symbolP = symbol_find (reg_string);
5244 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5245 {
5246 const expressionS *e = symbol_get_value_expression (symbolP);
5247
5248 know (e->X_op == O_register);
5249 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5250 r = i386_regtab + e->X_add_number;
5251 *end_op = input_line_pointer;
5252 }
5253 *input_line_pointer = c;
5254 input_line_pointer = save;
5255 }
5256 return r;
5257}
5258
5259int
5260i386_parse_name (char *name, expressionS *e, char *nextcharP)
5261{
5262 const reg_entry *r;
5263 char *end = input_line_pointer;
5264
5265 *end = *nextcharP;
5266 r = parse_register (name, &input_line_pointer);
5267 if (r && end <= input_line_pointer)
5268 {
5269 *nextcharP = *input_line_pointer;
5270 *input_line_pointer = 0;
5271 e->X_op = O_register;
5272 e->X_add_number = r - i386_regtab;
5273 return 1;
5274 }
5275 input_line_pointer = end;
5276 *end = 0;
5277 return 0;
5278}
5279
5280void
5281md_operand (expressionS *e)
5282{
5283 if (*input_line_pointer == REGISTER_PREFIX)
5284 {
5285 char *end;
5286 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5287
5288 if (r)
5289 {
5290 e->X_op = O_register;
5291 e->X_add_number = r - i386_regtab;
5292 input_line_pointer = end;
5293 }
5294 }
5295}
5296
252b5132 5297\f
4cc782b5 5298#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5299const char *md_shortopts = "kVQ:sqn";
252b5132 5300#else
12b55ccc 5301const char *md_shortopts = "qn";
252b5132 5302#endif
6e0b89ee 5303
3e73aa7c 5304#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5305#define OPTION_64 (OPTION_MD_BASE + 1)
5306#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5307
5308struct option md_longopts[] = {
3e73aa7c 5309 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5310#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c 5311 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5312#endif
b3b91714 5313 {"divide", no_argument, NULL, OPTION_DIVIDE},
252b5132
RH		 5314 {NULL, no_argument, NULL, 0}
5315};
5316size_t md_longopts_size = sizeof (md_longopts);
5317
5318int
5319md_parse_option (c, arg)
5320 int c;
ab9da554 5321 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5322{
5323 switch (c)
5324 {
12b55ccc
L		 5325 case 'n':
5326 optimize_align_code = 0;
5327 break;
5328
a38cf1db
AM		 5329 case 'q':
5330 quiet_warnings = 1;
252b5132
RH		 5331 break;
5332
5333#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5334 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5335 should be emitted or not. FIXME: Not implemented. */
5336 case 'Q':
252b5132
RH		 5337 break;
5338
5339 /* -V: SVR4 argument to print version ID. */
5340 case 'V':
5341 print_version_id ();
5342 break;
5343
a38cf1db
AM		 5344 /* -k: Ignore for FreeBSD compatibility. */
5345 case 'k':
252b5132 5346 break;
4cc782b5
ILT		 5347
5348 case 's':
5349 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5350 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5351 break;
6e0b89ee 5352
3e73aa7c
JH		 5353 case OPTION_64:
5354 {
5355 const char **list, **l;
5356
3e73aa7c
JH		 5357 list = bfd_target_list ();
5358 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5359 if (strcmp (*l, "elf64-x86-64") == 0)
5360 {
5361 default_arch = "x86_64";
5362 break;
5363 }
3e73aa7c 5364 if (*l == NULL)
6e0b89ee 5365 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5366 free (list);
5367 }
5368 break;
5369#endif
252b5132 5370
6e0b89ee
AM		 5371 case OPTION_32:
5372 default_arch = "i386";
5373 break;
5374
b3b91714
AM		 5375 case OPTION_DIVIDE:
5376#ifdef SVR4_COMMENT_CHARS
5377 {
5378 char *n, *t;
5379 const char *s;
5380
5381 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5382 t = n;
5383 for (s = i386_comment_chars; *s != '\0'; s++)
5384 if (*s != '/')
5385 *t++ = *s;
5386 *t = '\0';
5387 i386_comment_chars = n;
5388 }
5389#endif
5390 break;
5391
252b5132
RH		 5392 default:
5393 return 0;
5394 }
5395 return 1;
5396}
5397
5398void
5399md_show_usage (stream)
5400 FILE *stream;
5401{
4cc782b5
ILT		 5402#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5403 fprintf (stream, _("\
a38cf1db
AM		 5404 -Q ignored\n\
5405 -V print assembler version number\n\
b3b91714
AM		 5406 -k ignored\n"));
5407#endif
5408 fprintf (stream, _("\
12b55ccc 5409 -n Do not optimize code alignment\n\
b3b91714
AM		 5410 -q quieten some warnings\n"));
5411#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5412 fprintf (stream, _("\
a38cf1db 5413 -s ignored\n"));
b3b91714
AM		 5414#endif
5415#ifdef SVR4_COMMENT_CHARS
5416 fprintf (stream, _("\
5417 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5418#else
5419 fprintf (stream, _("\
b3b91714 5420 --divide ignored\n"));
4cc782b5 5421#endif
252b5132
RH		 5422}
5423
3e73aa7c
JH		 5424#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5425 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5426
5427/* Pick the target format to use. */
5428
47926f60 5429const char *
252b5132
RH		 5430i386_target_format ()
5431{
3e73aa7c
JH		 5432 if (!strcmp (default_arch, "x86_64"))
5433 set_code_flag (CODE_64BIT);
5434 else if (!strcmp (default_arch, "i386"))
5435 set_code_flag (CODE_32BIT);
5436 else
5437 as_fatal (_("Unknown architecture"));
252b5132
RH		 5438 switch (OUTPUT_FLAVOR)
5439 {
4c63da97
AM		 5440#ifdef OBJ_MAYBE_AOUT
5441 case bfd_target_aout_flavour:
47926f60 5442 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5443#endif
5444#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5445 case bfd_target_coff_flavour:
5446 return "coff-i386";
4c63da97 5447#endif
3e73aa7c 5448#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5449 case bfd_target_elf_flavour:
3e73aa7c 5450 {
e5cb08ac 5451 if (flag_code == CODE_64BIT)
4fa24527
JB		 5452 {
5453 object_64bit = 1;
5454 use_rela_relocations = 1;
5455 }
4ada7262 5456 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5457 }
4c63da97 5458#endif
252b5132
RH		 5459 default:
5460 abort ();
5461 return NULL;
5462 }
5463}
5464
47926f60 5465#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5466
5467#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5468void i386_elf_emit_arch_note ()
5469{
718ddfc0 5470 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5471 {
5472 char *p;
5473 asection *seg = now_seg;
5474 subsegT subseg = now_subseg;
5475 Elf_Internal_Note i_note;
5476 Elf_External_Note e_note;
5477 asection *note_secp;
5478 int len;
5479
5480 /* Create the .note section. */
5481 note_secp = subseg_new (".note", 0);
5482 bfd_set_section_flags (stdoutput,
5483 note_secp,
5484 SEC_HAS_CONTENTS | SEC_READONLY);
5485
5486 /* Process the arch string. */
5487 len = strlen (cpu_arch_name);
5488
5489 i_note.namesz = len + 1;
5490 i_note.descsz = 0;
5491 i_note.type = NT_ARCH;
5492 p = frag_more (sizeof (e_note.namesz));
5493 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5494 p = frag_more (sizeof (e_note.descsz));
5495 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5496 p = frag_more (sizeof (e_note.type));
5497 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5498 p = frag_more (len + 1);
5499 strcpy (p, cpu_arch_name);
5500
5501 frag_align (2, 0, 0);
5502
5503 subseg_set (seg, subseg);
5504 }
5505}
5506#endif
252b5132 5507\f
252b5132
RH		 5508symbolS *
5509md_undefined_symbol (name)
5510 char *name;
5511{
18dc2407
ILT		 5512 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5513 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5514 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5515 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5516 {
5517 if (!GOT_symbol)
5518 {
5519 if (symbol_find (name))
5520 as_bad (_("GOT already in symbol table"));
5521 GOT_symbol = symbol_new (name, undefined_section,
5522 (valueT) 0, &zero_address_frag);
5523 };
5524 return GOT_symbol;
5525 }
252b5132
RH		 5526 return 0;
5527}
5528
5529/* Round up a section size to the appropriate boundary. */
47926f60 5530
252b5132
RH		 5531valueT
5532md_section_align (segment, size)
ab9da554 5533 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5534 valueT size;
5535{
4c63da97
AM		 5536#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5537 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5538 {
5539 /* For a.out, force the section size to be aligned. If we don't do
5540 this, BFD will align it for us, but it will not write out the
5541 final bytes of the section. This may be a bug in BFD, but it is
5542 easier to fix it here since that is how the other a.out targets
5543 work. */
5544 int align;
5545
5546 align = bfd_get_section_alignment (stdoutput, segment);
5547 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5548 }
252b5132
RH		 5549#endif
5550
5551 return size;
5552}
5553
5554/* On the i386, PC-relative offsets are relative to the start of the
5555 next instruction. That is, the address of the offset, plus its
5556 size, since the offset is always the last part of the insn. */
5557
5558long
5559md_pcrel_from (fixP)
5560 fixS *fixP;
5561{
5562 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5563}
5564
5565#ifndef I386COFF
5566
5567static void
5568s_bss (ignore)
ab9da554 5569 int ignore ATTRIBUTE_UNUSED;
252b5132 5570{
29b0f896 5571 int temp;
252b5132 5572
8a75718c
JB		 5573#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5574 if (IS_ELF)
5575 obj_elf_section_change_hook ();
5576#endif
252b5132
RH		 5577 temp = get_absolute_expression ();
5578 subseg_set (bss_section, (subsegT) temp);
5579 demand_empty_rest_of_line ();
5580}
5581
5582#endif
5583
252b5132
RH		 5584void
5585i386_validate_fix (fixp)
5586 fixS *fixp;
5587{
5588 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5589 {
23df1078
JH		 5590 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5591 {
4fa24527 5592 if (!object_64bit)
23df1078
JH		 5593 abort ();
5594 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5595 }
5596 else
5597 {
4fa24527 5598 if (!object_64bit)
d6ab8113
JB		 5599 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5600 else
5601 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5602 }
252b5132
RH		 5603 fixp->fx_subsy = 0;
5604 }
5605}
5606
252b5132
RH		 5607arelent *
5608tc_gen_reloc (section, fixp)
ab9da554 5609 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5610 fixS *fixp;
5611{
5612 arelent *rel;
5613 bfd_reloc_code_real_type code;
5614
5615 switch (fixp->fx_r_type)
5616 {
3e73aa7c
JH		 5617 case BFD_RELOC_X86_64_PLT32:
5618 case BFD_RELOC_X86_64_GOT32:
5619 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5620 case BFD_RELOC_386_PLT32:
5621 case BFD_RELOC_386_GOT32:
5622 case BFD_RELOC_386_GOTOFF:
5623 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5624 case BFD_RELOC_386_TLS_GD:
5625 case BFD_RELOC_386_TLS_LDM:
5626 case BFD_RELOC_386_TLS_LDO_32:
5627 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5628 case BFD_RELOC_386_TLS_IE:
5629 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5630 case BFD_RELOC_386_TLS_LE_32:
5631 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5632 case BFD_RELOC_X86_64_TLSGD:
5633 case BFD_RELOC_X86_64_TLSLD:
5634 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5635 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5636 case BFD_RELOC_X86_64_GOTTPOFF:
5637 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5638 case BFD_RELOC_X86_64_TPOFF64:
5639 case BFD_RELOC_X86_64_GOTOFF64:
5640 case BFD_RELOC_X86_64_GOTPC32:
252b5132
RH		 5641 case BFD_RELOC_RVA:
5642 case BFD_RELOC_VTABLE_ENTRY:
5643 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5644#ifdef TE_PE
5645 case BFD_RELOC_32_SECREL:
5646#endif
252b5132
RH		 5647 code = fixp->fx_r_type;
5648 break;
dbbaec26
L		 5649 case BFD_RELOC_X86_64_32S:
5650 if (!fixp->fx_pcrel)
5651 {
5652 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5653 code = fixp->fx_r_type;
5654 break;
5655 }
252b5132 5656 default:
93382f6d 5657 if (fixp->fx_pcrel)
252b5132 5658 {
93382f6d
AM		 5659 switch (fixp->fx_size)
5660 {
5661 default:
b091f402
AM		 5662 as_bad_where (fixp->fx_file, fixp->fx_line,
5663 _("can not do %d byte pc-relative relocation"),
5664 fixp->fx_size);
93382f6d
AM		 5665 code = BFD_RELOC_32_PCREL;
5666 break;
5667 case 1: code = BFD_RELOC_8_PCREL; break;
5668 case 2: code = BFD_RELOC_16_PCREL; break;
5669 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5670#ifdef BFD64
5671 case 8: code = BFD_RELOC_64_PCREL; break;
5672#endif
93382f6d
AM		 5673 }
5674 }
5675 else
5676 {
5677 switch (fixp->fx_size)
5678 {
5679 default:
b091f402
AM		 5680 as_bad_where (fixp->fx_file, fixp->fx_line,
5681 _("can not do %d byte relocation"),
5682 fixp->fx_size);
93382f6d
AM		 5683 code = BFD_RELOC_32;
5684 break;
5685 case 1: code = BFD_RELOC_8; break;
5686 case 2: code = BFD_RELOC_16; break;
5687 case 4: code = BFD_RELOC_32; break;
937149dd 5688#ifdef BFD64
3e73aa7c 5689 case 8: code = BFD_RELOC_64; break;
937149dd 5690#endif
93382f6d 5691 }
252b5132
RH		 5692 }
5693 break;
5694 }
252b5132 5695
d182319b
JB		 5696 if ((code == BFD_RELOC_32
5697 || code == BFD_RELOC_32_PCREL
5698 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 5699 && GOT_symbol
5700 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5701 {
4fa24527 5702 if (!object_64bit)
d6ab8113
JB		 5703 code = BFD_RELOC_386_GOTPC;
5704 else
5705 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5706 }
252b5132
RH		 5707
5708 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5709 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5710 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5711
5712 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5713
3e73aa7c
JH		 5714 if (!use_rela_relocations)
5715 {
5716 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5717 vtable entry to be used in the relocation's section offset. */
5718 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5719 rel->address = fixp->fx_offset;
252b5132 5720
c6682705 5721 rel->addend = 0;
3e73aa7c
JH		 5722 }
5723 /* Use the rela in 64bit mode. */
252b5132 5724 else
3e73aa7c 5725 {
062cd5e7
AS		 5726 if (!fixp->fx_pcrel)
5727 rel->addend = fixp->fx_offset;
5728 else
5729 switch (code)
5730 {
5731 case BFD_RELOC_X86_64_PLT32:
5732 case BFD_RELOC_X86_64_GOT32:
5733 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5734 case BFD_RELOC_X86_64_TLSGD:
5735 case BFD_RELOC_X86_64_TLSLD:
5736 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5737 rel->addend = fixp->fx_offset - fixp->fx_size;
5738 break;
5739 default:
5740 rel->addend = (section->vma
5741 - fixp->fx_size
5742 + fixp->fx_addnumber
5743 + md_pcrel_from (fixp));
5744 break;
5745 }
3e73aa7c
JH		 5746 }
5747
252b5132
RH		 5748 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5749 if (rel->howto == NULL)
5750 {
5751 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5752 _("cannot represent relocation type %s"),
252b5132
RH		 5753 bfd_get_reloc_code_name (code));
5754 /* Set howto to a garbage value so that we can keep going. */
5755 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5756 assert (rel->howto != NULL);
5757 }
5758
5759 return rel;
5760}
5761
64a0c779
DN		 5762\f
5763/* Parse operands using Intel syntax. This implements a recursive descent
5764 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5765 Programmer's Guide.
5766
5767 FIXME: We do not recognize the full operand grammar defined in the MASM
5768 documentation. In particular, all the structure/union and
5769 high-level macro operands are missing.
5770
5771 Uppercase words are terminals, lower case words are non-terminals.
5772 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5773 bars '|' denote choices. Most grammar productions are implemented in
5774 functions called 'intel_<production>'.
5775
5776 Initial production is 'expr'.
5777
9306ca4a 5778 addOp + | -
64a0c779
DN		 5779
5780 alpha [a-zA-Z]
5781
9306ca4a
JB		 5782 binOp & | AND | \| | OR | ^ | XOR
5783
64a0c779
DN		 5784 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5785
5786 constant digits [[ radixOverride ]]
5787
9306ca4a 5788 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5789
5790 digits decdigit
b77a7acd
AJ		 5791 | digits decdigit
5792 | digits hexdigit
64a0c779
DN		 5793
5794 decdigit [0-9]
5795
9306ca4a
JB		 5796 e04 e04 addOp e05
5797 | e05
5798
5799 e05 e05 binOp e06
b77a7acd 5800 | e06
64a0c779
DN		 5801
5802 e06 e06 mulOp e09
b77a7acd 5803 | e09
64a0c779
DN		 5804
5805 e09 OFFSET e10
a724f0f4
JB		 5806 | SHORT e10
5807 | + e10
5808 | - e10
9306ca4a
JB		 5809 | ~ e10
5810 | NOT e10
64a0c779
DN		 5811 | e09 PTR e10
5812 | e09 : e10
5813 | e10
5814
5815 e10 e10 [ expr ]
b77a7acd 5816 | e11
64a0c779
DN		 5817
5818 e11 ( expr )
b77a7acd 5819 | [ expr ]
64a0c779
DN		 5820 | constant
5821 | dataType
5822 | id
5823 | $
5824 | register
5825
a724f0f4 5826 => expr expr cmpOp e04
9306ca4a 5827 | e04
64a0c779
DN		 5828
5829 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5830 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5831
5832 hexdigit a | b | c | d | e | f
b77a7acd 5833 | A | B | C | D | E | F
64a0c779
DN		 5834
5835 id alpha
b77a7acd 5836 | id alpha
64a0c779
DN		 5837 | id decdigit
5838
9306ca4a 5839 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5840
5841 quote " | '
5842
5843 register specialRegister
b77a7acd 5844 | gpRegister
64a0c779
DN		 5845 | byteRegister
5846
5847 segmentRegister CS | DS | ES | FS | GS | SS
5848
9306ca4a 5849 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5850 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5851 | TR3 | TR4 | TR5 | TR6 | TR7
5852
64a0c779
DN		 5853 We simplify the grammar in obvious places (e.g., register parsing is
5854 done by calling parse_register) and eliminate immediate left recursion
5855 to implement a recursive-descent parser.
5856
a724f0f4
JB		 5857 expr e04 expr'
5858
5859 expr' cmpOp e04 expr'
5860 | Empty
9306ca4a
JB		 5861
5862 e04 e05 e04'
5863
5864 e04' addOp e05 e04'
5865 | Empty
64a0c779
DN		 5866
5867 e05 e06 e05'
5868
9306ca4a 5869 e05' binOp e06 e05'
b77a7acd 5870 | Empty
64a0c779
DN		 5871
5872 e06 e09 e06'
5873
5874 e06' mulOp e09 e06'
b77a7acd 5875 | Empty
64a0c779
DN		 5876
5877 e09 OFFSET e10 e09'
a724f0f4
JB		 5878 | SHORT e10'
5879 | + e10'
5880 | - e10'
5881 | ~ e10'
5882 | NOT e10'
b77a7acd 5883 | e10 e09'
64a0c779
DN		 5884
5885 e09' PTR e10 e09'
b77a7acd 5886 | : e10 e09'
64a0c779
DN		 5887 | Empty
5888
5889 e10 e11 e10'
5890
5891 e10' [ expr ] e10'
b77a7acd 5892 | Empty
64a0c779
DN		 5893
5894 e11 ( expr )
b77a7acd 5895 | [ expr ]
64a0c779
DN		 5896 | BYTE
5897 | WORD
5898 | DWORD
9306ca4a 5899 | FWORD
64a0c779 5900 | QWORD
9306ca4a
JB		 5901 | TBYTE
5902 | OWORD
5903 | XMMWORD
64a0c779
DN		 5904 | .
5905 | $
5906 | register
5907 | id
5908 | constant */
5909
5910/* Parsing structure for the intel syntax parser. Used to implement the
5911 semantic actions for the operand grammar. */
5912struct intel_parser_s
5913 {
5914 char *op_string; /* The string being parsed. */
5915 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5916 int op_modifier; /* Operand modifier. */
64a0c779 5917 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5918 int in_offset; /* >=1 if parsing operand of offset. */
5919 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5920 const reg_entry *reg; /* Last register reference found. */
5921 char *disp; /* Displacement string being built. */
a724f0f4 5922 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5923 };
5924
5925static struct intel_parser_s intel_parser;
5926
5927/* Token structure for parsing intel syntax. */
5928struct intel_token
5929 {
5930 int code; /* Token code. */
5931 const reg_entry *reg; /* Register entry for register tokens. */
5932 char *str; /* String representation. */
5933 };
5934
5935static struct intel_token cur_token, prev_token;
5936
50705ef4
AM		 5937/* Token codes for the intel parser. Since T_SHORT is already used
5938 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5939#define T_NIL -1
5940#define T_CONST 1
5941#define T_REG 2
5942#define T_BYTE 3
5943#define T_WORD 4
9306ca4a
JB		 5944#define T_DWORD 5
5945#define T_FWORD 6
5946#define T_QWORD 7
5947#define T_TBYTE 8
5948#define T_XMMWORD 9
50705ef4 5949#undef T_SHORT
9306ca4a
JB		 5950#define T_SHORT 10
5951#define T_OFFSET 11
5952#define T_PTR 12
5953#define T_ID 13
5954#define T_SHL 14
5955#define T_SHR 15
64a0c779
DN		 5956
5957/* Prototypes for intel parser functions. */
5958static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5959static void intel_get_token PARAMS ((void));
5960static void intel_putback_token PARAMS ((void));
5961static int intel_expr PARAMS ((void));
9306ca4a 5962static int intel_e04 PARAMS ((void));
cce0cbdc 5963static int intel_e05 PARAMS ((void));
cce0cbdc 5964static int intel_e06 PARAMS ((void));
cce0cbdc 5965static int intel_e09 PARAMS ((void));
a724f0f4 5966static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5967static int intel_e10 PARAMS ((void));
cce0cbdc 5968static int intel_e11 PARAMS ((void));
64a0c779 5969
64a0c779
DN		 5970static int
5971i386_intel_operand (operand_string, got_a_float)
5972 char *operand_string;
5973 int got_a_float;
5974{
5975 int ret;
5976 char *p;
5977
a724f0f4
JB		 5978 p = intel_parser.op_string = xstrdup (operand_string);
5979 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5980
5981 for (;;)
64a0c779 5982 {
a724f0f4
JB		 5983 /* Initialize token holders. */
5984 cur_token.code = prev_token.code = T_NIL;
5985 cur_token.reg = prev_token.reg = NULL;
5986 cur_token.str = prev_token.str = NULL;
5987
5988 /* Initialize parser structure. */
5989 intel_parser.got_a_float = got_a_float;
5990 intel_parser.op_modifier = 0;
5991 intel_parser.is_mem = 0;
5992 intel_parser.in_offset = 0;
5993 intel_parser.in_bracket = 0;
5994 intel_parser.reg = NULL;
5995 intel_parser.disp[0] = '\0';
5996 intel_parser.next_operand = NULL;
5997
5998 /* Read the first token and start the parser. */
5999 intel_get_token ();
6000 ret = intel_expr ();
6001
6002 if (!ret)
6003 break;
6004
9306ca4a
JB		 6005 if (cur_token.code != T_NIL)
6006 {
6007 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6008 current_templates->start->name, cur_token.str);
6009 ret = 0;
6010 }
64a0c779
DN		 6011 /* If we found a memory reference, hand it over to i386_displacement
6012 to fill in the rest of the operand fields. */
9306ca4a 6013 else if (intel_parser.is_mem)
64a0c779
DN		 6014 {
6015 if ((i.mem_operands == 1
6016 && (current_templates->start->opcode_modifier & IsString) == 0)
6017 || i.mem_operands == 2)
6018 {
6019 as_bad (_("too many memory references for '%s'"),
6020 current_templates->start->name);
6021 ret = 0;
6022 }
6023 else
6024 {
6025 char *s = intel_parser.disp;
6026 i.mem_operands++;
6027
a724f0f4
JB		 6028 if (!quiet_warnings && intel_parser.is_mem < 0)
6029 /* See the comments in intel_bracket_expr. */
6030 as_warn (_("Treating `%s' as memory reference"), operand_string);
6031
64a0c779
DN		 6032 /* Add the displacement expression. */
6033 if (*s != '\0')
a4622f40
AM		 6034 ret = i386_displacement (s, s + strlen (s));
6035 if (ret)
a724f0f4
JB		 6036 {
6037 /* Swap base and index in 16-bit memory operands like
6038 [si+bx]. Since i386_index_check is also used in AT&T
6039 mode we have to do that here. */
6040 if (i.base_reg
6041 && i.index_reg
6042 && (i.base_reg->reg_type & Reg16)
6043 && (i.index_reg->reg_type & Reg16)
6044 && i.base_reg->reg_num >= 6
6045 && i.index_reg->reg_num < 6)
6046 {
6047 const reg_entry *base = i.index_reg;
6048
6049 i.index_reg = i.base_reg;
6050 i.base_reg = base;
6051 }
6052 ret = i386_index_check (operand_string);
6053 }
64a0c779
DN		 6054 }
6055 }
6056
6057 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6058 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6059 || intel_parser.reg == NULL)
6060 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6061
6062 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6063 ret = 0;
6064 if (!ret || !intel_parser.next_operand)
6065 break;
6066 intel_parser.op_string = intel_parser.next_operand;
6067 this_operand = i.operands++;
64a0c779
DN		 6068 }
6069
6070 free (p);
6071 free (intel_parser.disp);
6072
6073 return ret;
6074}
6075
a724f0f4
JB		 6076#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6077
6078/* expr e04 expr'
6079
6080 expr' cmpOp e04 expr'
6081 | Empty */
64a0c779
DN		 6082static int
6083intel_expr ()
6084{
a724f0f4
JB		 6085 /* XXX Implement the comparison operators. */
6086 return intel_e04 ();
9306ca4a
JB		 6087}
6088
a724f0f4 6089/* e04 e05 e04'
9306ca4a 6090
a724f0f4 6091 e04' addOp e05 e04'
9306ca4a
JB		 6092 | Empty */
6093static int
6094intel_e04 ()
6095{
a724f0f4 6096 int nregs = -1;
9306ca4a 6097
a724f0f4 6098 for (;;)
9306ca4a 6099 {
a724f0f4
JB		 6100 if (!intel_e05())
6101 return 0;
9306ca4a 6102
a724f0f4
JB		 6103 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6104 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6105
a724f0f4
JB		 6106 if (cur_token.code == '+')
6107 nregs = -1;
6108 else if (cur_token.code == '-')
6109 nregs = NUM_ADDRESS_REGS;
6110 else
6111 return 1;
64a0c779 6112
a724f0f4
JB		 6113 strcat (intel_parser.disp, cur_token.str);
6114 intel_match_token (cur_token.code);
6115 }
64a0c779
DN		 6116}
6117
64a0c779
DN		 6118/* e05 e06 e05'
6119
9306ca4a 6120 e05' binOp e06 e05'
64a0c779
DN		 6121 | Empty */
6122static int
6123intel_e05 ()
6124{
a724f0f4 6125 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6126
a724f0f4 6127 for (;;)
64a0c779 6128 {
a724f0f4
JB		 6129 if (!intel_e06())
6130 return 0;
6131
6132 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6133 {
6134 char str[2];
6135
6136 str[0] = cur_token.code;
6137 str[1] = 0;
6138 strcat (intel_parser.disp, str);
6139 }
6140 else
6141 break;
9306ca4a 6142
64a0c779
DN		 6143 intel_match_token (cur_token.code);
6144
a724f0f4
JB		 6145 if (nregs < 0)
6146 nregs = ~nregs;
64a0c779 6147 }
a724f0f4
JB		 6148 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6149 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6150 return 1;
4a1805b1 6151}
64a0c779
DN		 6152
6153/* e06 e09 e06'
6154
6155 e06' mulOp e09 e06'
b77a7acd 6156 | Empty */
64a0c779
DN		 6157static int
6158intel_e06 ()
6159{
a724f0f4 6160 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6161
a724f0f4 6162 for (;;)
64a0c779 6163 {
a724f0f4
JB		 6164 if (!intel_e09())
6165 return 0;
9306ca4a 6166
a724f0f4
JB		 6167 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6168 {
6169 char str[2];
9306ca4a 6170
a724f0f4
JB		 6171 str[0] = cur_token.code;
6172 str[1] = 0;
6173 strcat (intel_parser.disp, str);
6174 }
6175 else if (cur_token.code == T_SHL)
6176 strcat (intel_parser.disp, "<<");
6177 else if (cur_token.code == T_SHR)
6178 strcat (intel_parser.disp, ">>");
6179 else
6180 break;
9306ca4a 6181
a724f0f4 6182 intel_match_token (cur_token.code);
64a0c779 6183
a724f0f4
JB		 6184 if (nregs < 0)
6185 nregs = ~nregs;
64a0c779 6186 }
a724f0f4
JB		 6187 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6188 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6189 return 1;
64a0c779
DN		 6190}
6191
a724f0f4
JB		 6192/* e09 OFFSET e09
6193 | SHORT e09
6194 | + e09
6195 | - e09
6196 | ~ e09
6197 | NOT e09
9306ca4a
JB		 6198 | e10 e09'
6199
64a0c779 6200 e09' PTR e10 e09'
b77a7acd 6201 | : e10 e09'
64a0c779
DN		 6202 | Empty */
6203static int
6204intel_e09 ()
6205{
a724f0f4
JB		 6206 int nregs = ~NUM_ADDRESS_REGS;
6207 int in_offset = 0;
6208
6209 for (;;)
64a0c779 6210 {
a724f0f4
JB		 6211 /* Don't consume constants here. */
6212 if (cur_token.code == '+' || cur_token.code == '-')
6213 {
6214 /* Need to look one token ahead - if the next token
6215 is a constant, the current token is its sign. */
6216 int next_code;
6217
6218 intel_match_token (cur_token.code);
6219 next_code = cur_token.code;
6220 intel_putback_token ();
6221 if (next_code == T_CONST)
6222 break;
6223 }
6224
6225 /* e09 OFFSET e09 */
6226 if (cur_token.code == T_OFFSET)
6227 {
6228 if (!in_offset++)
6229 ++intel_parser.in_offset;
6230 }
6231
6232 /* e09 SHORT e09 */
6233 else if (cur_token.code == T_SHORT)
6234 intel_parser.op_modifier |= 1 << T_SHORT;
6235
6236 /* e09 + e09 */
6237 else if (cur_token.code == '+')
6238 strcat (intel_parser.disp, "+");
6239
6240 /* e09 - e09
6241 | ~ e09
6242 | NOT e09 */
6243 else if (cur_token.code == '-' || cur_token.code == '~')
6244 {
6245 char str[2];
64a0c779 6246
a724f0f4
JB		 6247 if (nregs < 0)
6248 nregs = ~nregs;
6249 str[0] = cur_token.code;
6250 str[1] = 0;
6251 strcat (intel_parser.disp, str);
6252 }
6253
6254 /* e09 e10 e09' */
6255 else
6256 break;
6257
6258 intel_match_token (cur_token.code);
64a0c779
DN		 6259 }
6260
a724f0f4 6261 for (;;)
9306ca4a 6262 {
a724f0f4
JB		 6263 if (!intel_e10 ())
6264 return 0;
9306ca4a 6265
a724f0f4
JB		 6266 /* e09' PTR e10 e09' */
6267 if (cur_token.code == T_PTR)
6268 {
6269 char suffix;
9306ca4a 6270
a724f0f4
JB		 6271 if (prev_token.code == T_BYTE)
6272 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6273
a724f0f4
JB		 6274 else if (prev_token.code == T_WORD)
6275 {
6276 if (current_templates->start->name[0] == 'l'
6277 && current_templates->start->name[2] == 's'
6278 && current_templates->start->name[3] == 0)
6279 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6280 else if (intel_parser.got_a_float == 2) /* "fi..." */
6281 suffix = SHORT_MNEM_SUFFIX;
6282 else
6283 suffix = WORD_MNEM_SUFFIX;
6284 }
64a0c779 6285
a724f0f4
JB		 6286 else if (prev_token.code == T_DWORD)
6287 {
6288 if (current_templates->start->name[0] == 'l'
6289 && current_templates->start->name[2] == 's'
6290 && current_templates->start->name[3] == 0)
6291 suffix = WORD_MNEM_SUFFIX;
6292 else if (flag_code == CODE_16BIT
6293 && (current_templates->start->opcode_modifier
435acd52 6294 & (Jump | JumpDword)))
a724f0f4
JB		 6295 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6296 else if (intel_parser.got_a_float == 1) /* "f..." */
6297 suffix = SHORT_MNEM_SUFFIX;
6298 else
6299 suffix = LONG_MNEM_SUFFIX;
6300 }
9306ca4a 6301
a724f0f4
JB		 6302 else if (prev_token.code == T_FWORD)
6303 {
6304 if (current_templates->start->name[0] == 'l'
6305 && current_templates->start->name[2] == 's'
6306 && current_templates->start->name[3] == 0)
6307 suffix = LONG_MNEM_SUFFIX;
6308 else if (!intel_parser.got_a_float)
6309 {
6310 if (flag_code == CODE_16BIT)
6311 add_prefix (DATA_PREFIX_OPCODE);
6312 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6313 }
6314 else
6315 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6316 }
64a0c779 6317
a724f0f4
JB		 6318 else if (prev_token.code == T_QWORD)
6319 {
6320 if (intel_parser.got_a_float == 1) /* "f..." */
6321 suffix = LONG_MNEM_SUFFIX;
6322 else
6323 suffix = QWORD_MNEM_SUFFIX;
6324 }
64a0c779 6325
a724f0f4
JB		 6326 else if (prev_token.code == T_TBYTE)
6327 {
6328 if (intel_parser.got_a_float == 1)
6329 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6330 else
6331 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6332 }
9306ca4a 6333
a724f0f4 6334 else if (prev_token.code == T_XMMWORD)
9306ca4a 6335 {
a724f0f4
JB		 6336 /* XXX ignored for now, but accepted since gcc uses it */
6337 suffix = 0;
9306ca4a 6338 }
64a0c779 6339
f16b83df 6340 else
a724f0f4
JB		 6341 {
6342 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6343 return 0;
6344 }
6345
435acd52
JB		 6346 /* Operands for jump/call using 'ptr' notation denote absolute
6347 addresses. */
6348 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6349 i.types[this_operand] |= JumpAbsolute;
6350
a724f0f4
JB		 6351 if (current_templates->start->base_opcode == 0x8d /* lea */)
6352 ;
6353 else if (!i.suffix)
6354 i.suffix = suffix;
6355 else if (i.suffix != suffix)
6356 {
6357 as_bad (_("Conflicting operand modifiers"));
6358 return 0;
6359 }
64a0c779 6360
9306ca4a
JB		 6361 }
6362
a724f0f4
JB		 6363 /* e09' : e10 e09' */
6364 else if (cur_token.code == ':')
9306ca4a 6365 {
a724f0f4
JB		 6366 if (prev_token.code != T_REG)
6367 {
6368 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6369 segment/group identifier (which we don't have), using comma
6370 as the operand separator there is even less consistent, since
6371 there all branches only have a single operand. */
6372 if (this_operand != 0
6373 || intel_parser.in_offset
6374 || intel_parser.in_bracket
6375 || (!(current_templates->start->opcode_modifier
6376 & (Jump|JumpDword|JumpInterSegment))
6377 && !(current_templates->start->operand_types[0]
6378 & JumpAbsolute)))
6379 return intel_match_token (T_NIL);
6380 /* Remember the start of the 2nd operand and terminate 1st
6381 operand here.
6382 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6383 another expression), but it gets at least the simplest case
6384 (a plain number or symbol on the left side) right. */
6385 intel_parser.next_operand = intel_parser.op_string;
6386 *--intel_parser.op_string = '\0';
6387 return intel_match_token (':');
6388 }
9306ca4a 6389 }
64a0c779 6390
a724f0f4 6391 /* e09' Empty */
64a0c779 6392 else
a724f0f4 6393 break;
64a0c779 6394
a724f0f4
JB		 6395 intel_match_token (cur_token.code);
6396
6397 }
6398
6399 if (in_offset)
6400 {
6401 --intel_parser.in_offset;
6402 if (nregs < 0)
6403 nregs = ~nregs;
6404 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6405 {
a724f0f4 6406 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6407 return 0;
6408 }
a724f0f4
JB		 6409 intel_parser.op_modifier |= 1 << T_OFFSET;
6410 }
9306ca4a 6411
a724f0f4
JB		 6412 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6413 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6414 return 1;
6415}
64a0c779 6416
a724f0f4
JB		 6417static int
6418intel_bracket_expr ()
6419{
6420 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6421 const char *start = intel_parser.op_string;
6422 int len;
6423
6424 if (i.op[this_operand].regs)
6425 return intel_match_token (T_NIL);
6426
6427 intel_match_token ('[');
6428
6429 /* Mark as a memory operand only if it's not already known to be an
6430 offset expression. If it's an offset expression, we need to keep
6431 the brace in. */
6432 if (!intel_parser.in_offset)
6433 {
6434 ++intel_parser.in_bracket;
435acd52
JB		 6435
6436 /* Operands for jump/call inside brackets denote absolute addresses. */
6437 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6438 i.types[this_operand] |= JumpAbsolute;
6439
a724f0f4
JB		 6440 /* Unfortunately gas always diverged from MASM in a respect that can't
6441 be easily fixed without risking to break code sequences likely to be
6442 encountered (the testsuite even check for this): MASM doesn't consider
6443 an expression inside brackets unconditionally as a memory reference.
6444 When that is e.g. a constant, an offset expression, or the sum of the
6445 two, this is still taken as a constant load. gas, however, always
6446 treated these as memory references. As a compromise, we'll try to make
6447 offset expressions inside brackets work the MASM way (since that's
6448 less likely to be found in real world code), but make constants alone
6449 continue to work the traditional gas way. In either case, issue a
6450 warning. */
6451 intel_parser.op_modifier &= ~was_offset;
64a0c779 6452 }
a724f0f4
JB		 6453 else
6454 strcat (intel_parser.disp, "[");
6455
6456 /* Add a '+' to the displacement string if necessary. */
6457 if (*intel_parser.disp != '\0'
6458 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6459 strcat (intel_parser.disp, "+");
64a0c779 6460
a724f0f4
JB		 6461 if (intel_expr ()
6462 && (len = intel_parser.op_string - start - 1,
6463 intel_match_token (']')))
64a0c779 6464 {
a724f0f4
JB		 6465 /* Preserve brackets when the operand is an offset expression. */
6466 if (intel_parser.in_offset)
6467 strcat (intel_parser.disp, "]");
6468 else
6469 {
6470 --intel_parser.in_bracket;
6471 if (i.base_reg || i.index_reg)
6472 intel_parser.is_mem = 1;
6473 if (!intel_parser.is_mem)
6474 {
6475 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6476 /* Defer the warning until all of the operand was parsed. */
6477 intel_parser.is_mem = -1;
6478 else if (!quiet_warnings)
6479 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6480 }
6481 }
6482 intel_parser.op_modifier |= was_offset;
64a0c779 6483
a724f0f4 6484 return 1;
64a0c779 6485 }
a724f0f4 6486 return 0;
64a0c779
DN		 6487}
6488
6489/* e10 e11 e10'
6490
6491 e10' [ expr ] e10'
b77a7acd 6492 | Empty */
64a0c779
DN		 6493static int
6494intel_e10 ()
6495{
a724f0f4
JB		 6496 if (!intel_e11 ())
6497 return 0;
64a0c779 6498
a724f0f4 6499 while (cur_token.code == '[')
64a0c779 6500 {
a724f0f4 6501 if (!intel_bracket_expr ())
21d6c4af 6502 return 0;
64a0c779
DN		 6503 }
6504
a724f0f4 6505 return 1;
64a0c779
DN		 6506}
6507
64a0c779 6508/* e11 ( expr )
b77a7acd 6509 | [ expr ]
64a0c779
DN		 6510 | BYTE
6511 | WORD
6512 | DWORD
9306ca4a 6513 | FWORD
64a0c779 6514 | QWORD
9306ca4a
JB		 6515 | TBYTE
6516 | OWORD
6517 | XMMWORD
4a1805b1 6518 | $
64a0c779
DN		 6519 | .
6520 | register
6521 | id
6522 | constant */
6523static int
6524intel_e11 ()
6525{
a724f0f4 6526 switch (cur_token.code)
64a0c779 6527 {
a724f0f4
JB		 6528 /* e11 ( expr ) */
6529 case '(':
64a0c779
DN		 6530 intel_match_token ('(');
6531 strcat (intel_parser.disp, "(");
6532
6533 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6534 {
6535 strcat (intel_parser.disp, ")");
6536 return 1;
6537 }
a724f0f4 6538 return 0;
4a1805b1 6539
a724f0f4
JB		 6540 /* e11 [ expr ] */
6541 case '[':
a724f0f4 6542 return intel_bracket_expr ();
64a0c779 6543
a724f0f4
JB		 6544 /* e11 $
6545 | . */
6546 case '.':
64a0c779
DN		 6547 strcat (intel_parser.disp, cur_token.str);
6548 intel_match_token (cur_token.code);
21d6c4af
DN		 6549
6550 /* Mark as a memory operand only if it's not already known to be an
6551 offset expression. */
a724f0f4 6552 if (!intel_parser.in_offset)
21d6c4af 6553 intel_parser.is_mem = 1;
64a0c779
DN		 6554
6555 return 1;
64a0c779 6556
a724f0f4
JB		 6557 /* e11 register */
6558 case T_REG:
6559 {
6560 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6561
a724f0f4 6562 intel_match_token (T_REG);
64a0c779 6563
a724f0f4
JB		 6564 /* Check for segment change. */
6565 if (cur_token.code == ':')
6566 {
6567 if (!(reg->reg_type & (SReg2 | SReg3)))
6568 {
6569 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6570 return 0;
6571 }
6572 else if (i.seg[i.mem_operands])
6573 as_warn (_("Extra segment override ignored"));
6574 else
6575 {
6576 if (!intel_parser.in_offset)
6577 intel_parser.is_mem = 1;
6578 switch (reg->reg_num)
6579 {
6580 case 0:
6581 i.seg[i.mem_operands] = &es;
6582 break;
6583 case 1:
6584 i.seg[i.mem_operands] = &cs;
6585 break;
6586 case 2:
6587 i.seg[i.mem_operands] = &ss;
6588 break;
6589 case 3:
6590 i.seg[i.mem_operands] = &ds;
6591 break;
6592 case 4:
6593 i.seg[i.mem_operands] = &fs;
6594 break;
6595 case 5:
6596 i.seg[i.mem_operands] = &gs;
6597 break;
6598 }
6599 }
6600 }
64a0c779 6601
a724f0f4
JB		 6602 /* Not a segment register. Check for register scaling. */
6603 else if (cur_token.code == '*')
6604 {
6605 if (!intel_parser.in_bracket)
6606 {
6607 as_bad (_("Register scaling only allowed in memory operands"));
6608 return 0;
6609 }
64a0c779 6610
a724f0f4
JB		 6611 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6612 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6613 else if (i.index_reg)
6614 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6615
a724f0f4
JB		 6616 /* What follows must be a valid scale. */
6617 intel_match_token ('*');
6618 i.index_reg = reg;
6619 i.types[this_operand] |= BaseIndex;
64a0c779 6620
a724f0f4
JB		 6621 /* Set the scale after setting the register (otherwise,
6622 i386_scale will complain) */
6623 if (cur_token.code == '+' || cur_token.code == '-')
6624 {
6625 char *str, sign = cur_token.code;
6626 intel_match_token (cur_token.code);
6627 if (cur_token.code != T_CONST)
6628 {
6629 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6630 cur_token.str);
6631 return 0;
6632 }
6633 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6634 strcpy (str + 1, cur_token.str);
6635 *str = sign;
6636 if (!i386_scale (str))
6637 return 0;
6638 free (str);
6639 }
6640 else if (!i386_scale (cur_token.str))
64a0c779 6641 return 0;
a724f0f4
JB		 6642 intel_match_token (cur_token.code);
6643 }
64a0c779 6644
a724f0f4
JB		 6645 /* No scaling. If this is a memory operand, the register is either a
6646 base register (first occurrence) or an index register (second
6647 occurrence). */
7b0441f6 6648 else if (intel_parser.in_bracket)
a724f0f4 6649 {
64a0c779 6650
a724f0f4
JB		 6651 if (!i.base_reg)
6652 i.base_reg = reg;
6653 else if (!i.index_reg)
6654 i.index_reg = reg;
6655 else
6656 {
6657 as_bad (_("Too many register references in memory operand"));
6658 return 0;
6659 }
64a0c779 6660
a724f0f4
JB		 6661 i.types[this_operand] |= BaseIndex;
6662 }
4a1805b1 6663
4d1bb795
JB		 6664 /* It's neither base nor index. */
6665 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 6666 {
6667 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6668 i.op[this_operand].regs = reg;
6669 i.reg_operands++;
6670 }
6671 else
6672 {
6673 as_bad (_("Invalid use of register"));
6674 return 0;
6675 }
64a0c779 6676
a724f0f4
JB		 6677 /* Since registers are not part of the displacement string (except
6678 when we're parsing offset operands), we may need to remove any
6679 preceding '+' from the displacement string. */
6680 if (*intel_parser.disp != '\0'
6681 && !intel_parser.in_offset)
6682 {
6683 char *s = intel_parser.disp;
6684 s += strlen (s) - 1;
6685 if (*s == '+')
6686 *s = '\0';
6687 }
4a1805b1 6688
a724f0f4
JB		 6689 return 1;
6690 }
6691
6692 /* e11 BYTE
6693 | WORD
6694 | DWORD
6695 | FWORD
6696 | QWORD
6697 | TBYTE
6698 | OWORD
6699 | XMMWORD */
6700 case T_BYTE:
6701 case T_WORD:
6702 case T_DWORD:
6703 case T_FWORD:
6704 case T_QWORD:
6705 case T_TBYTE:
6706 case T_XMMWORD:
6707 intel_match_token (cur_token.code);
64a0c779 6708
a724f0f4
JB		 6709 if (cur_token.code == T_PTR)
6710 return 1;
6711
6712 /* It must have been an identifier. */
6713 intel_putback_token ();
6714 cur_token.code = T_ID;
6715 /* FALLTHRU */
6716
6717 /* e11 id
6718 | constant */
6719 case T_ID:
6720 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6721 {
6722 symbolS *symbolP;
6723
a724f0f4
JB		 6724 /* The identifier represents a memory reference only if it's not
6725 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6726 symbolP = symbol_find(cur_token.str);
6727 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6728 intel_parser.is_mem = 1;
6729 }
a724f0f4 6730 /* FALLTHRU */
64a0c779 6731
a724f0f4
JB		 6732 case T_CONST:
6733 case '-':
6734 case '+':
6735 {
6736 char *save_str, sign = 0;
64a0c779 6737
a724f0f4
JB		 6738 /* Allow constants that start with `+' or `-'. */
6739 if (cur_token.code == '-' || cur_token.code == '+')
6740 {
6741 sign = cur_token.code;
6742 intel_match_token (cur_token.code);
6743 if (cur_token.code != T_CONST)
6744 {
6745 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6746 cur_token.str);
6747 return 0;
6748 }
6749 }
64a0c779 6750
a724f0f4
JB		 6751 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6752 strcpy (save_str + !!sign, cur_token.str);
6753 if (sign)
6754 *save_str = sign;
64a0c779 6755
a724f0f4
JB		 6756 /* Get the next token to check for register scaling. */
6757 intel_match_token (cur_token.code);
64a0c779 6758
a724f0f4
JB		 6759 /* Check if this constant is a scaling factor for an index register. */
6760 if (cur_token.code == '*')
6761 {
6762 if (intel_match_token ('*') && cur_token.code == T_REG)
6763 {
6764 const reg_entry *reg = cur_token.reg;
6765
6766 if (!intel_parser.in_bracket)
6767 {
6768 as_bad (_("Register scaling only allowed in memory operands"));
6769 return 0;
6770 }
6771
6772 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6773 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6774 else if (i.index_reg)
6775 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6776
6777 /* The constant is followed by `* reg', so it must be
6778 a valid scale. */
6779 i.index_reg = reg;
6780 i.types[this_operand] |= BaseIndex;
6781
6782 /* Set the scale after setting the register (otherwise,
6783 i386_scale will complain) */
6784 if (!i386_scale (save_str))
64a0c779 6785 return 0;
a724f0f4
JB		 6786 intel_match_token (T_REG);
6787
6788 /* Since registers are not part of the displacement
6789 string, we may need to remove any preceding '+' from
6790 the displacement string. */
6791 if (*intel_parser.disp != '\0')
6792 {
6793 char *s = intel_parser.disp;
6794 s += strlen (s) - 1;
6795 if (*s == '+')
6796 *s = '\0';
6797 }
6798
6799 free (save_str);
6800
6801 return 1;
6802 }
64a0c779 6803
a724f0f4
JB		 6804 /* The constant was not used for register scaling. Since we have
6805 already consumed the token following `*' we now need to put it
6806 back in the stream. */
64a0c779 6807 intel_putback_token ();
a724f0f4 6808 }
64a0c779 6809
a724f0f4
JB		 6810 /* Add the constant to the displacement string. */
6811 strcat (intel_parser.disp, save_str);
6812 free (save_str);
64a0c779 6813
a724f0f4
JB		 6814 return 1;
6815 }
64a0c779
DN		 6816 }
6817
64a0c779
DN		 6818 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6819 return 0;
6820}
6821
64a0c779
DN		 6822/* Match the given token against cur_token. If they match, read the next
6823 token from the operand string. */
6824static int
6825intel_match_token (code)
e5cb08ac 6826 int code;
64a0c779
DN		 6827{
6828 if (cur_token.code == code)
6829 {
6830 intel_get_token ();
6831 return 1;
6832 }
6833 else
6834 {
0477af35 6835 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6836 return 0;
6837 }
6838}
6839
64a0c779
DN		 6840/* Read a new token from intel_parser.op_string and store it in cur_token. */
6841static void
6842intel_get_token ()
6843{
6844 char *end_op;
6845 const reg_entry *reg;
6846 struct intel_token new_token;
6847
6848 new_token.code = T_NIL;
6849 new_token.reg = NULL;
6850 new_token.str = NULL;
6851
4a1805b1 6852 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6853 cur_token to prev_token. */
6854 if (prev_token.str)
6855 free (prev_token.str);
6856
6857 prev_token = cur_token;
6858
6859 /* Skip whitespace. */
6860 while (is_space_char (*intel_parser.op_string))
6861 intel_parser.op_string++;
6862
6863 /* Return an empty token if we find nothing else on the line. */
6864 if (*intel_parser.op_string == '\0')
6865 {
6866 cur_token = new_token;
6867 return;
6868 }
6869
6870 /* The new token cannot be larger than the remainder of the operand
6871 string. */
a724f0f4 6872 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6873 new_token.str[0] = '\0';
6874
6875 if (strchr ("0123456789", *intel_parser.op_string))
6876 {
6877 char *p = new_token.str;
6878 char *q = intel_parser.op_string;
6879 new_token.code = T_CONST;
6880
6881 /* Allow any kind of identifier char to encompass floating point and
6882 hexadecimal numbers. */
6883 while (is_identifier_char (*q))
6884 *p++ = *q++;
6885 *p = '\0';
6886
6887 /* Recognize special symbol names [0-9][bf]. */
6888 if (strlen (intel_parser.op_string) == 2
4a1805b1 6889 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6890 || intel_parser.op_string[1] == 'f'))
6891 new_token.code = T_ID;
6892 }
6893
4d1bb795 6894 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 6895 {
4d1bb795
JB		 6896 size_t len = end_op - intel_parser.op_string;
6897
64a0c779
DN		 6898 new_token.code = T_REG;
6899 new_token.reg = reg;
6900
4d1bb795
JB		 6901 memcpy (new_token.str, intel_parser.op_string, len);
6902 new_token.str[len] = '\0';
64a0c779
DN		 6903 }
6904
6905 else if (is_identifier_char (*intel_parser.op_string))
6906 {
6907 char *p = new_token.str;
6908 char *q = intel_parser.op_string;
6909
6910 /* A '.' or '$' followed by an identifier char is an identifier.
6911 Otherwise, it's operator '.' followed by an expression. */
6912 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6913 {
9306ca4a
JB		 6914 new_token.code = '.';
6915 new_token.str[0] = '.';
64a0c779
DN		 6916 new_token.str[1] = '\0';
6917 }
6918 else
6919 {
6920 while (is_identifier_char (*q) || *q == '@')
6921 *p++ = *q++;
6922 *p = '\0';
6923
9306ca4a
JB		 6924 if (strcasecmp (new_token.str, "NOT") == 0)
6925 new_token.code = '~';
6926
6927 else if (strcasecmp (new_token.str, "MOD") == 0)
6928 new_token.code = '%';
6929
6930 else if (strcasecmp (new_token.str, "AND") == 0)
6931 new_token.code = '&';
6932
6933 else if (strcasecmp (new_token.str, "OR") == 0)
6934 new_token.code = '|';
6935
6936 else if (strcasecmp (new_token.str, "XOR") == 0)
6937 new_token.code = '^';
6938
6939 else if (strcasecmp (new_token.str, "SHL") == 0)
6940 new_token.code = T_SHL;
6941
6942 else if (strcasecmp (new_token.str, "SHR") == 0)
6943 new_token.code = T_SHR;
6944
6945 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6946 new_token.code = T_BYTE;
6947
6948 else if (strcasecmp (new_token.str, "WORD") == 0)
6949 new_token.code = T_WORD;
6950
6951 else if (strcasecmp (new_token.str, "DWORD") == 0)
6952 new_token.code = T_DWORD;
6953
9306ca4a
JB		 6954 else if (strcasecmp (new_token.str, "FWORD") == 0)
6955 new_token.code = T_FWORD;
6956
64a0c779
DN		 6957 else if (strcasecmp (new_token.str, "QWORD") == 0)
6958 new_token.code = T_QWORD;
6959
9306ca4a
JB		 6960 else if (strcasecmp (new_token.str, "TBYTE") == 0
6961 /* XXX remove (gcc still uses it) */
6962 || strcasecmp (new_token.str, "XWORD") == 0)
6963 new_token.code = T_TBYTE;
6964
6965 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6966 || strcasecmp (new_token.str, "OWORD") == 0)
6967 new_token.code = T_XMMWORD;
64a0c779
DN		 6968
6969 else if (strcasecmp (new_token.str, "PTR") == 0)
6970 new_token.code = T_PTR;
6971
6972 else if (strcasecmp (new_token.str, "SHORT") == 0)
6973 new_token.code = T_SHORT;
6974
6975 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6976 {
6977 new_token.code = T_OFFSET;
6978
6979 /* ??? This is not mentioned in the MASM grammar but gcc
6980 makes use of it with -mintel-syntax. OFFSET may be
6981 followed by FLAT: */
6982 if (strncasecmp (q, " FLAT:", 6) == 0)
6983 strcat (new_token.str, " FLAT:");
6984 }
6985
6986 /* ??? This is not mentioned in the MASM grammar. */
6987 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6988 {
6989 new_token.code = T_OFFSET;
6990 if (*q == ':')
6991 strcat (new_token.str, ":");
6992 else
6993 as_bad (_("`:' expected"));
6994 }
64a0c779
DN		 6995
6996 else
6997 new_token.code = T_ID;
6998 }
6999 }
7000
9306ca4a
JB		 7001 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7002 {
7003 new_token.code = *intel_parser.op_string;
7004 new_token.str[0] = *intel_parser.op_string;
7005 new_token.str[1] = '\0';
7006 }
7007
7008 else if (strchr ("<>", *intel_parser.op_string)
7009 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7010 {
7011 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7012 new_token.str[0] = *intel_parser.op_string;
7013 new_token.str[1] = *intel_parser.op_string;
7014 new_token.str[2] = '\0';
7015 }
7016
64a0c779 7017 else
0477af35 7018 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7019
7020 intel_parser.op_string += strlen (new_token.str);
7021 cur_token = new_token;
7022}
7023
64a0c779
DN		 7024/* Put cur_token back into the token stream and make cur_token point to
7025 prev_token. */
7026static void
7027intel_putback_token ()
7028{
a724f0f4
JB		 7029 if (cur_token.code != T_NIL)
7030 {
7031 intel_parser.op_string -= strlen (cur_token.str);
7032 free (cur_token.str);
7033 }
64a0c779 7034 cur_token = prev_token;
4a1805b1 7035
64a0c779
DN		 7036 /* Forget prev_token. */
7037 prev_token.code = T_NIL;
7038 prev_token.reg = NULL;
7039 prev_token.str = NULL;
7040}
54cfded0 7041
a4447b93 7042int
54cfded0
AM		 7043tc_x86_regname_to_dw2regnum (const char *regname)
7044{
7045 unsigned int regnum;
7046 unsigned int regnames_count;
089dfecd 7047 static const char *const regnames_32[] =
54cfded0 7048 {
a4447b93
RH		 7049 "eax", "ecx", "edx", "ebx",
7050 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7051 "eip", "eflags", NULL,
7052 "st0", "st1", "st2", "st3",
7053 "st4", "st5", "st6", "st7",
7054 NULL, NULL,
7055 "xmm0", "xmm1", "xmm2", "xmm3",
7056 "xmm4", "xmm5", "xmm6", "xmm7",
7057 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7058 "mm4", "mm5", "mm6", "mm7",
7059 "fcw", "fsw", "mxcsr",
7060 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7061 "tr", "ldtr"
54cfded0 7062 };
089dfecd 7063 static const char *const regnames_64[] =
54cfded0 7064 {
089dfecd
JB		 7065 "rax", "rdx", "rcx", "rbx",
7066 "rsi", "rdi", "rbp", "rsp",
7067 "r8", "r9", "r10", "r11",
54cfded0 7068 "r12", "r13", "r14", "r15",
089dfecd
JB		 7069 "rip",
7070 "xmm0", "xmm1", "xmm2", "xmm3",
7071 "xmm4", "xmm5", "xmm6", "xmm7",
7072 "xmm8", "xmm9", "xmm10", "xmm11",
7073 "xmm12", "xmm13", "xmm14", "xmm15",
7074 "st0", "st1", "st2", "st3",
7075 "st4", "st5", "st6", "st7",
7076 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7077 "mm4", "mm5", "mm6", "mm7",
7078 "rflags",
7079 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7080 "fs.base", "gs.base", NULL, NULL,
7081 "tr", "ldtr",
7082 "mxcsr", "fcw", "fsw"
54cfded0 7083 };
089dfecd 7084 const char *const *regnames;
54cfded0
AM		 7085
7086 if (flag_code == CODE_64BIT)
7087 {
7088 regnames = regnames_64;
0cea6190 7089 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7090 }
7091 else
7092 {
7093 regnames = regnames_32;
0cea6190 7094 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7095 }
7096
7097 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7098 if (regnames[regnum] != NULL
7099 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7100 return regnum;
7101
54cfded0
AM		 7102 return -1;
7103}
7104
7105void
7106tc_x86_frame_initial_instructions (void)
7107{
a4447b93
RH		 7108 static unsigned int sp_regno;
7109
7110 if (!sp_regno)
7111 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7112 ? "rsp" : "esp");
7113
7114 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7115 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7116}
d2b2c203
DJ		 7117
7118int
7119i386_elf_section_type (const char *str, size_t len)
7120{
7121 if (flag_code == CODE_64BIT
7122 && len == sizeof ("unwind") - 1
7123 && strncmp (str, "unwind", 6) == 0)
7124 return SHT_X86_64_UNWIND;
7125
7126 return -1;
7127}
bb41ade5
AM		 7128
7129#ifdef TE_PE
7130void
7131tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7132{
7133 expressionS expr;
7134
7135 expr.X_op = O_secrel;
7136 expr.X_add_symbol = symbol;
7137 expr.X_add_number = 0;
7138 emit_expr (&expr, size);
7139}
7140#endif
3b22753a
L		 7141
7142#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7143/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7144
7145int
7146x86_64_section_letter (int letter, char **ptr_msg)
7147{
7148 if (flag_code == CODE_64BIT)
7149 {
7150 if (letter == 'l')
7151 return SHF_X86_64_LARGE;
7152
7153 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7154 }
7155 else
7156 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7157 return -1;
7158}
7159
7160int
7161x86_64_section_word (char *str, size_t len)
7162{
7163 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7164 return SHF_X86_64_LARGE;
7165
7166 return -1;
7167}
7168
7169static void
7170handle_large_common (int small ATTRIBUTE_UNUSED)
7171{
7172 if (flag_code != CODE_64BIT)
7173 {
7174 s_comm_internal (0, elf_common_parse);
7175 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7176 }
7177 else
7178 {
7179 static segT lbss_section;
7180 asection *saved_com_section_ptr = elf_com_section_ptr;
7181 asection *saved_bss_section = bss_section;
7182
7183 if (lbss_section == NULL)
7184 {
7185 flagword applicable;
7186 segT seg = now_seg;
7187 subsegT subseg = now_subseg;
7188
7189 /* The .lbss section is for local .largecomm symbols. */
7190 lbss_section = subseg_new (".lbss", 0);
7191 applicable = bfd_applicable_section_flags (stdoutput);
7192 bfd_set_section_flags (stdoutput, lbss_section,
7193 applicable & SEC_ALLOC);
7194 seg_info (lbss_section)->bss = 1;
7195
7196 subseg_set (seg, subseg);
7197 }
7198
7199 elf_com_section_ptr = &_bfd_elf_large_com_section;
7200 bss_section = lbss_section;
7201
7202 s_comm_internal (0, elf_common_parse);
7203
7204 elf_com_section_ptr = saved_com_section_ptr;
7205 bss_section = saved_bss_section;
7206 }
7207}
7208#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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