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PR 10419
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
6305a203
L		 117/* 386 opcode byte to code indirect addressing. */
118typedef struct
119{
120 unsigned base;
121 unsigned index;
122 unsigned scale;
123}
124sib_byte;
125
6305a203
L		 126/* x86 arch names, types and features */
127typedef struct
128{
129 const char *name; /* arch name */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132}
133arch_entry;
134
e3bb37b5
L		 135static void set_code_flag (int);
136static void set_16bit_gcc_code_flag (int);
137static void set_intel_syntax (int);
1efbbeb4 138static void set_intel_mnemonic (int);
db51cc60 139static void set_allow_index_reg (int);
cb19c032 140static void set_sse_check (int);
e3bb37b5 141static void set_cpu_arch (int);
6482c264 142#ifdef TE_PE
e3bb37b5 143static void pe_directive_secrel (int);
6482c264 144#endif
e3bb37b5
L		 145static void signed_cons (int);
146static char *output_invalid (int c);
ee86248c
JB		 147static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
148 const char *);
149static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
150 const char *);
a7619375 151static int i386_att_operand (char *);
e3bb37b5 152static int i386_intel_operand (char *, int);
ee86248c
JB		 153static int i386_intel_simplify (expressionS *);
154static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 155static const reg_entry *parse_register (char *, char **);
156static char *parse_insn (char *, char *);
157static char *parse_operands (char *, const char *);
158static void swap_operands (void);
4d456e3d 159static void swap_2_operands (int, int);
e3bb37b5
L		 160static void optimize_imm (void);
161static void optimize_disp (void);
fa99fab2 162static const template *match_template (void);
e3bb37b5
L		 163static int check_string (void);
164static int process_suffix (void);
165static int check_byte_reg (void);
166static int check_long_reg (void);
167static int check_qword_reg (void);
168static int check_word_reg (void);
169static int finalize_imm (void);
170static int process_operands (void);
171static const seg_entry *build_modrm_byte (void);
172static void output_insn (void);
173static void output_imm (fragS *, offsetT);
174static void output_disp (fragS *, offsetT);
29b0f896 175#ifndef I386COFF
e3bb37b5 176static void s_bss (int);
252b5132 177#endif
17d4e2a2
L		 178#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179static void handle_large_common (int small ATTRIBUTE_UNUSED);
180#endif
252b5132 181
a847613f 182static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 183
c0f3af97
L		 184/* VEX prefix. */
185typedef struct
186{
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes[3];
189 unsigned int length;
190 /* Destination or source register specifier. */
191 const reg_entry *register_specifier;
192} vex_prefix;
193
252b5132 194/* 'md_assemble ()' gathers together information and puts it into a
47926f60 195 i386_insn. */
252b5132 196
520dc8e8
AM		 197union i386_op
198 {
199 expressionS *disps;
200 expressionS *imms;
201 const reg_entry *regs;
202 };
203
252b5132
RH		 204struct _i386_insn
205 {
47926f60 206 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 207 template tm;
208
7d5e4556
L		 209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
252b5132
RH		 211 char suffix;
212
47926f60 213 /* OPERANDS gives the number of given operands. */
252b5132
RH		 214 unsigned int operands;
215
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
47926f60 218 operands. */
252b5132
RH		 219 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
220
221 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 222 use OP[i] for the corresponding operand. */
40fb9820 223 i386_operand_type types[MAX_OPERANDS];
252b5132 224
520dc8e8
AM		 225 /* Displacement expression, immediate expression, or register for each
226 operand. */
227 union i386_op op[MAX_OPERANDS];
252b5132 228
3e73aa7c
JH		 229 /* Flags for operands. */
230 unsigned int flags[MAX_OPERANDS];
231#define Operand_PCrel 1
232
252b5132 233 /* Relocation type for operand */
f86103b7 234 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 235
252b5132
RH		 236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry *base_reg;
239 const reg_entry *index_reg;
240 unsigned int log2_scale_factor;
241
242 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 243 explicit segment overrides are given. */
ce8a8b2f 244 const seg_entry *seg[2];
252b5132
RH		 245
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes;
249 unsigned char prefix[MAX_PREFIXES];
250
251 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 252 addressing modes of this insn are encoded. */
252b5132 253 modrm_byte rm;
3e73aa7c 254 rex_byte rex;
252b5132 255 sib_byte sib;
c0f3af97 256 vex_prefix vex;
b6169b20
L		 257
258 /* Swap operand in encoding. */
259 unsigned int swap_operand : 1;
252b5132
RH		 260 };
261
262typedef struct _i386_insn i386_insn;
263
264/* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
32137342 266const char extra_symbol_chars[] = "*%-(["
252b5132 267#ifdef LEX_AT
32137342
NC		 268 "@"
269#endif
270#ifdef LEX_QM
271 "?"
252b5132 272#endif
32137342 273 ;
252b5132 274
29b0f896
AM		 275#if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 277 && !defined (TE_GNU) \
29b0f896 278 && !defined (TE_LINUX) \
32137342 279 && !defined (TE_NETWARE) \
29b0f896
AM		 280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
252b5132 282/* This array holds the chars that always start a comment. If the
b3b91714
AM		 283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285const char *i386_comment_chars = "#/";
286#define SVR4_COMMENT_CHARS 1
252b5132 287#define PREFIX_SEPARATOR '\\'
252b5132 288
b3b91714
AM		 289#else
290const char *i386_comment_chars = "#";
291#define PREFIX_SEPARATOR '/'
292#endif
293
252b5132
RH		 294/* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 298 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
252b5132 301 '/' isn't otherwise defined. */
b3b91714 302const char line_comment_chars[] = "#/";
252b5132 303
63a0b638 304const char line_separator_chars[] = ";";
252b5132 305
ce8a8b2f
AM		 306/* Chars that can be used to separate mant from exp in floating point
307 nums. */
252b5132
RH		 308const char EXP_CHARS[] = "eE";
309
ce8a8b2f
AM		 310/* Chars that mean this number is a floating point constant
311 As in 0f12.456
312 or 0d1.2345e12. */
252b5132
RH		 313const char FLT_CHARS[] = "fFdDxX";
314
ce8a8b2f 315/* Tables for lexical analysis. */
252b5132
RH		 316static char mnemonic_chars[256];
317static char register_chars[256];
318static char operand_chars[256];
319static char identifier_chars[256];
320static char digit_chars[256];
321
ce8a8b2f 322/* Lexical macros. */
252b5132
RH		 323#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324#define is_operand_char(x) (operand_chars[(unsigned char) x])
325#define is_register_char(x) (register_chars[(unsigned char) x])
326#define is_space_char(x) ((x) == ' ')
327#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328#define is_digit_char(x) (digit_chars[(unsigned char) x])
329
0234cb7c 330/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 331static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
332
333/* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
47926f60 336 assembler instruction). */
252b5132 337static char save_stack[32];
ce8a8b2f 338static char *save_stack_p;
252b5132
RH		 339#define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341#define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
343
47926f60 344/* The instruction we're assembling. */
252b5132
RH		 345static i386_insn i;
346
347/* Possible templates for current insn. */
348static const templates *current_templates;
349
31b2323c
L		 350/* Per instruction expressionS buffers: max displacements & immediates. */
351static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
352static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 353
47926f60 354/* Current operand we are working on. */
ee86248c 355static int this_operand = -1;
252b5132 356
3e73aa7c
JH		 357/* We support four different modes. FLAG_CODE variable is used to distinguish
358 these. */
359
360enum flag_code {
361 CODE_32BIT,
362 CODE_16BIT,
363 CODE_64BIT };
364
365static enum flag_code flag_code;
4fa24527 366static unsigned int object_64bit;
3e73aa7c
JH		 367static int use_rela_relocations = 0;
368
369/* The names used to print error messages. */
b77a7acd 370static const char *flag_code_names[] =
3e73aa7c
JH		 371 {
372 "32",
373 "16",
374 "64"
375 };
252b5132 376
47926f60
KH		 377/* 1 for intel syntax,
378 0 if att syntax. */
379static int intel_syntax = 0;
252b5132 380
1efbbeb4
L		 381/* 1 for intel mnemonic,
382 0 if att mnemonic. */
383static int intel_mnemonic = !SYSV386_COMPAT;
384
5209009a 385/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 386static int old_gcc = OLDGCC_COMPAT;
387
a60de03c
JB		 388/* 1 if pseudo registers are permitted. */
389static int allow_pseudo_reg = 0;
390
47926f60
KH		 391/* 1 if register prefix % not required. */
392static int allow_naked_reg = 0;
252b5132 393
ba104c83 394/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 395static int allow_index_reg = 0;
396
daf50ae7
L		 397static enum
398 {
399 sse_check_none = 0,
400 sse_check_warning,
401 sse_check_error
402 }
403sse_check;
404
2ca3ace5
L		 405/* Register prefix used for error message. */
406static const char *register_prefix = "%";
407
47926f60
KH		 408/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411static char stackop_size = '\0';
eecb386c 412
12b55ccc
L		 413/* Non-zero to optimize code alignment. */
414int optimize_align_code = 1;
415
47926f60
KH		 416/* Non-zero to quieten some warnings. */
417static int quiet_warnings = 0;
a38cf1db 418
47926f60
KH		 419/* CPU name. */
420static const char *cpu_arch_name = NULL;
6305a203 421static char *cpu_sub_arch_name = NULL;
a38cf1db 422
47926f60 423/* CPU feature flags. */
40fb9820
L		 424static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
425
ccc9c027
L		 426/* If we have selected a cpu we are generating instructions for. */
427static int cpu_arch_tune_set = 0;
428
9103f4f4 429/* Cpu we are generating instructions for. */
fbf3f584 430enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 431
432/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 433static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 434
ccc9c027 435/* CPU instruction set architecture used. */
fbf3f584 436enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 437
9103f4f4 438/* CPU feature flags of instruction set architecture used. */
fbf3f584 439i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 440
fddf5b5b
AM		 441/* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443static unsigned int no_cond_jump_promotion = 0;
444
c0f3af97
L		 445/* Encode SSE instructions with VEX prefix. */
446static unsigned int sse2avx;
447
29b0f896 448/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 449static symbolS *GOT_symbol;
29b0f896 450
a4447b93
RH		 451/* The dwarf2 return column, adjusted for 32 or 64 bit. */
452unsigned int x86_dwarf2_return_column;
453
454/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455int x86_cie_data_alignment;
456
252b5132 457/* Interface to relax_segment.
fddf5b5b
AM		 458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
252b5132 461
47926f60 462/* Types. */
93c2a809
AM		 463#define UNCOND_JUMP 0
464#define COND_JUMP 1
465#define COND_JUMP86 2
fddf5b5b 466
47926f60 467/* Sizes. */
252b5132
RH		 468#define CODE16 1
469#define SMALL 0
29b0f896 470#define SMALL16 (SMALL | CODE16)
252b5132 471#define BIG 2
29b0f896 472#define BIG16 (BIG | CODE16)
252b5132
RH		 473
474#ifndef INLINE
475#ifdef __GNUC__
476#define INLINE __inline__
477#else
478#define INLINE
479#endif
480#endif
481
fddf5b5b
AM		 482#define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484#define TYPE_FROM_RELAX_STATE(s) \
485 ((s) >> 2)
486#define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 488
489/* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
496
497const relax_typeS md_relax_table[] =
498{
24eab124
AM		 499 /* The fields are:
500 1) most positive reach of this state,
501 2) most negative reach of this state,
93c2a809 502 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 503 4) which index into the table to try if we can't fit into this one. */
252b5132 504
fddf5b5b 505 /* UNCOND_JUMP states. */
93c2a809
AM		 506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
252b5132 510 {0, 0, 4, 0},
93c2a809
AM		 511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 513 {0, 0, 2, 0},
514
93c2a809
AM		 515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
520 {0, 0, 5, 0},
fddf5b5b 521 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 522 1 extra opcode byte, 2 displacement bytes. */
523 {0, 0, 3, 0},
524
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
530 {0, 0, 5, 0},
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
533 {0, 0, 4, 0}
252b5132
RH		 534};
535
9103f4f4
L		 536static const arch_entry cpu_arch[] =
537{
6305a203
L		 538 { "generic32", PROCESSOR_GENERIC32,
539 CPU_GENERIC32_FLAGS },
540 { "generic64", PROCESSOR_GENERIC64,
541 CPU_GENERIC64_FLAGS },
542 { "i8086", PROCESSOR_UNKNOWN,
543 CPU_NONE_FLAGS },
544 { "i186", PROCESSOR_UNKNOWN,
545 CPU_I186_FLAGS },
546 { "i286", PROCESSOR_UNKNOWN,
547 CPU_I286_FLAGS },
548 { "i386", PROCESSOR_I386,
549 CPU_I386_FLAGS },
550 { "i486", PROCESSOR_I486,
551 CPU_I486_FLAGS },
552 { "i586", PROCESSOR_PENTIUM,
553 CPU_I586_FLAGS },
554 { "i686", PROCESSOR_PENTIUMPRO,
555 CPU_I686_FLAGS },
556 { "pentium", PROCESSOR_PENTIUM,
557 CPU_I586_FLAGS },
558 { "pentiumpro", PROCESSOR_PENTIUMPRO,
559 CPU_I686_FLAGS },
560 { "pentiumii", PROCESSOR_PENTIUMPRO,
561 CPU_P2_FLAGS },
562 { "pentiumiii",PROCESSOR_PENTIUMPRO,
563 CPU_P3_FLAGS },
564 { "pentium4", PROCESSOR_PENTIUM4,
565 CPU_P4_FLAGS },
566 { "prescott", PROCESSOR_NOCONA,
567 CPU_CORE_FLAGS },
568 { "nocona", PROCESSOR_NOCONA,
569 CPU_NOCONA_FLAGS },
570 { "yonah", PROCESSOR_CORE,
571 CPU_CORE_FLAGS },
572 { "core", PROCESSOR_CORE,
573 CPU_CORE_FLAGS },
574 { "merom", PROCESSOR_CORE2,
575 CPU_CORE2_FLAGS },
576 { "core2", PROCESSOR_CORE2,
577 CPU_CORE2_FLAGS },
bd5295b2
L		 578 { "corei7", PROCESSOR_COREI7,
579 CPU_COREI7_FLAGS },
6305a203
L		 580 { "k6", PROCESSOR_K6,
581 CPU_K6_FLAGS },
582 { "k6_2", PROCESSOR_K6,
583 CPU_K6_2_FLAGS },
584 { "athlon", PROCESSOR_ATHLON,
585 CPU_ATHLON_FLAGS },
586 { "sledgehammer", PROCESSOR_K8,
587 CPU_K8_FLAGS },
588 { "opteron", PROCESSOR_K8,
589 CPU_K8_FLAGS },
590 { "k8", PROCESSOR_K8,
591 CPU_K8_FLAGS },
592 { "amdfam10", PROCESSOR_AMDFAM10,
593 CPU_AMDFAM10_FLAGS },
594 { ".mmx", PROCESSOR_UNKNOWN,
595 CPU_MMX_FLAGS },
596 { ".sse", PROCESSOR_UNKNOWN,
597 CPU_SSE_FLAGS },
598 { ".sse2", PROCESSOR_UNKNOWN,
599 CPU_SSE2_FLAGS },
600 { ".sse3", PROCESSOR_UNKNOWN,
601 CPU_SSE3_FLAGS },
602 { ".ssse3", PROCESSOR_UNKNOWN,
603 CPU_SSSE3_FLAGS },
604 { ".sse4.1", PROCESSOR_UNKNOWN,
605 CPU_SSE4_1_FLAGS },
606 { ".sse4.2", PROCESSOR_UNKNOWN,
607 CPU_SSE4_2_FLAGS },
608 { ".sse4", PROCESSOR_UNKNOWN,
609 CPU_SSE4_2_FLAGS },
c0f3af97
L		 610 { ".avx", PROCESSOR_UNKNOWN,
611 CPU_AVX_FLAGS },
6305a203
L		 612 { ".vmx", PROCESSOR_UNKNOWN,
613 CPU_VMX_FLAGS },
614 { ".smx", PROCESSOR_UNKNOWN,
615 CPU_SMX_FLAGS },
f03fe4c1
L		 616 { ".xsave", PROCESSOR_UNKNOWN,
617 CPU_XSAVE_FLAGS },
c0f3af97
L		 618 { ".aes", PROCESSOR_UNKNOWN,
619 CPU_AES_FLAGS },
594ab6a3
L		 620 { ".pclmul", PROCESSOR_UNKNOWN,
621 CPU_PCLMUL_FLAGS },
c0f3af97 622 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 623 CPU_PCLMUL_FLAGS },
c0f3af97
L		 624 { ".fma", PROCESSOR_UNKNOWN,
625 CPU_FMA_FLAGS },
922d8de8
DR		 626 { ".fma4", PROCESSOR_UNKNOWN,
627 CPU_FMA4_FLAGS },
f1f8f695
L		 628 { ".movbe", PROCESSOR_UNKNOWN,
629 CPU_MOVBE_FLAGS },
630 { ".ept", PROCESSOR_UNKNOWN,
631 CPU_EPT_FLAGS },
bd5295b2
L		 632 { ".clflush", PROCESSOR_UNKNOWN,
633 CPU_CLFLUSH_FLAGS },
634 { ".syscall", PROCESSOR_UNKNOWN,
635 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 636 { ".rdtscp", PROCESSOR_UNKNOWN,
637 CPU_RDTSCP_FLAGS },
6305a203
L		 638 { ".3dnow", PROCESSOR_UNKNOWN,
639 CPU_3DNOW_FLAGS },
640 { ".3dnowa", PROCESSOR_UNKNOWN,
641 CPU_3DNOWA_FLAGS },
642 { ".padlock", PROCESSOR_UNKNOWN,
643 CPU_PADLOCK_FLAGS },
644 { ".pacifica", PROCESSOR_UNKNOWN,
645 CPU_SVME_FLAGS },
646 { ".svme", PROCESSOR_UNKNOWN,
647 CPU_SVME_FLAGS },
648 { ".sse4a", PROCESSOR_UNKNOWN,
649 CPU_SSE4A_FLAGS },
650 { ".abm", PROCESSOR_UNKNOWN,
651 CPU_ABM_FLAGS },
e413e4e9
AM		 652};
653
704209c0 654#ifdef I386COFF
a6c24e68
NC		 655/* Like s_lcomm_internal in gas/read.c but the alignment string
656 is allowed to be optional. */
657
658static symbolS *
659pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
660{
661 addressT align = 0;
662
663 SKIP_WHITESPACE ();
664
7ab9ffdd 665 if (needs_align
a6c24e68
NC		 666 && *input_line_pointer == ',')
667 {
668 align = parse_align (needs_align - 1);
7ab9ffdd 669
a6c24e68
NC		 670 if (align == (addressT) -1)
671 return NULL;
672 }
673 else
674 {
675 if (size >= 8)
676 align = 3;
677 else if (size >= 4)
678 align = 2;
679 else if (size >= 2)
680 align = 1;
681 else
682 align = 0;
683 }
684
685 bss_alloc (symbolP, size, align);
686 return symbolP;
687}
688
704209c0 689static void
a6c24e68
NC		 690pe_lcomm (int needs_align)
691{
692 s_comm_internal (needs_align * 2, pe_lcomm_internal);
693}
704209c0 694#endif
a6c24e68 695
29b0f896
AM		 696const pseudo_typeS md_pseudo_table[] =
697{
698#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
699 {"align", s_align_bytes, 0},
700#else
701 {"align", s_align_ptwo, 0},
702#endif
703 {"arch", set_cpu_arch, 0},
704#ifndef I386COFF
705 {"bss", s_bss, 0},
a6c24e68
NC		 706#else
707 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 708#endif
709 {"ffloat", float_cons, 'f'},
710 {"dfloat", float_cons, 'd'},
711 {"tfloat", float_cons, 'x'},
712 {"value", cons, 2},
d182319b 713 {"slong", signed_cons, 4},
29b0f896
AM		 714 {"noopt", s_ignore, 0},
715 {"optim", s_ignore, 0},
716 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
717 {"code16", set_code_flag, CODE_16BIT},
718 {"code32", set_code_flag, CODE_32BIT},
719 {"code64", set_code_flag, CODE_64BIT},
720 {"intel_syntax", set_intel_syntax, 1},
721 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 722 {"intel_mnemonic", set_intel_mnemonic, 1},
723 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 724 {"allow_index_reg", set_allow_index_reg, 1},
725 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 726 {"sse_check", set_sse_check, 0},
3b22753a
L		 727#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
728 {"largecomm", handle_large_common, 0},
07a53e5c 729#else
e3bb37b5 730 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 731 {"loc", dwarf2_directive_loc, 0},
732 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 733#endif
6482c264
NC		 734#ifdef TE_PE
735 {"secrel32", pe_directive_secrel, 0},
736#endif
29b0f896
AM		 737 {0, 0, 0}
738};
739
740/* For interface with expression (). */
741extern char *input_line_pointer;
742
743/* Hash table for instruction mnemonic lookup. */
744static struct hash_control *op_hash;
745
746/* Hash table for register lookup. */
747static struct hash_control *reg_hash;
748\f
252b5132 749void
e3bb37b5 750i386_align_code (fragS *fragP, int count)
252b5132 751{
ce8a8b2f
AM		 752 /* Various efficient no-op patterns for aligning code labels.
753 Note: Don't try to assemble the instructions in the comments.
754 0L and 0w are not legal. */
252b5132
RH		 755 static const char f32_1[] =
756 {0x90}; /* nop */
757 static const char f32_2[] =
ccc9c027 758 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 759 static const char f32_3[] =
760 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
761 static const char f32_4[] =
762 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
763 static const char f32_5[] =
764 {0x90, /* nop */
765 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
766 static const char f32_6[] =
767 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
768 static const char f32_7[] =
769 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
770 static const char f32_8[] =
771 {0x90, /* nop */
772 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
773 static const char f32_9[] =
774 {0x89,0xf6, /* movl %esi,%esi */
775 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
776 static const char f32_10[] =
777 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
778 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
779 static const char f32_11[] =
780 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
781 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
782 static const char f32_12[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
784 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
785 static const char f32_13[] =
786 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
787 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
788 static const char f32_14[] =
789 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
790 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 791 static const char f16_3[] =
792 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 793 static const char f16_4[] =
794 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
795 static const char f16_5[] =
796 {0x90, /* nop */
797 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
798 static const char f16_6[] =
799 {0x89,0xf6, /* mov %si,%si */
800 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
801 static const char f16_7[] =
802 {0x8d,0x74,0x00, /* lea 0(%si),%si */
803 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
804 static const char f16_8[] =
805 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
806 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 807 static const char jump_31[] =
808 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
809 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
810 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
811 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 812 static const char *const f32_patt[] = {
813 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 814 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 815 };
816 static const char *const f16_patt[] = {
76bc74dc 817 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 818 };
ccc9c027
L		 819 /* nopl (%[re]ax) */
820 static const char alt_3[] =
821 {0x0f,0x1f,0x00};
822 /* nopl 0(%[re]ax) */
823 static const char alt_4[] =
824 {0x0f,0x1f,0x40,0x00};
825 /* nopl 0(%[re]ax,%[re]ax,1) */
826 static const char alt_5[] =
827 {0x0f,0x1f,0x44,0x00,0x00};
828 /* nopw 0(%[re]ax,%[re]ax,1) */
829 static const char alt_6[] =
830 {0x66,0x0f,0x1f,0x44,0x00,0x00};
831 /* nopl 0L(%[re]ax) */
832 static const char alt_7[] =
833 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
834 /* nopl 0L(%[re]ax,%[re]ax,1) */
835 static const char alt_8[] =
836 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
837 /* nopw 0L(%[re]ax,%[re]ax,1) */
838 static const char alt_9[] =
839 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
840 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
841 static const char alt_10[] =
842 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
843 /* data16
844 nopw %cs:0L(%[re]ax,%[re]ax,1) */
845 static const char alt_long_11[] =
846 {0x66,
847 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
848 /* data16
849 data16
850 nopw %cs:0L(%[re]ax,%[re]ax,1) */
851 static const char alt_long_12[] =
852 {0x66,
853 0x66,
854 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
855 /* data16
856 data16
857 data16
858 nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_long_13[] =
860 {0x66,
861 0x66,
862 0x66,
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
864 /* data16
865 data16
866 data16
867 data16
868 nopw %cs:0L(%[re]ax,%[re]ax,1) */
869 static const char alt_long_14[] =
870 {0x66,
871 0x66,
872 0x66,
873 0x66,
874 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 /* data16
876 data16
877 data16
878 data16
879 data16
880 nopw %cs:0L(%[re]ax,%[re]ax,1) */
881 static const char alt_long_15[] =
882 {0x66,
883 0x66,
884 0x66,
885 0x66,
886 0x66,
887 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
888 /* nopl 0(%[re]ax,%[re]ax,1)
889 nopw 0(%[re]ax,%[re]ax,1) */
890 static const char alt_short_11[] =
891 {0x0f,0x1f,0x44,0x00,0x00,
892 0x66,0x0f,0x1f,0x44,0x00,0x00};
893 /* nopw 0(%[re]ax,%[re]ax,1)
894 nopw 0(%[re]ax,%[re]ax,1) */
895 static const char alt_short_12[] =
896 {0x66,0x0f,0x1f,0x44,0x00,0x00,
897 0x66,0x0f,0x1f,0x44,0x00,0x00};
898 /* nopw 0(%[re]ax,%[re]ax,1)
899 nopl 0L(%[re]ax) */
900 static const char alt_short_13[] =
901 {0x66,0x0f,0x1f,0x44,0x00,0x00,
902 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
903 /* nopl 0L(%[re]ax)
904 nopl 0L(%[re]ax) */
905 static const char alt_short_14[] =
906 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
907 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
908 /* nopl 0L(%[re]ax)
909 nopl 0L(%[re]ax,%[re]ax,1) */
910 static const char alt_short_15[] =
911 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
912 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 static const char *const alt_short_patt[] = {
914 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
915 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
916 alt_short_14, alt_short_15
917 };
918 static const char *const alt_long_patt[] = {
919 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
920 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
921 alt_long_14, alt_long_15
922 };
252b5132 923
76bc74dc
L		 924 /* Only align for at least a positive non-zero boundary. */
925 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 926 return;
3e73aa7c 927
ccc9c027
L		 928 /* We need to decide which NOP sequence to use for 32bit and
929 64bit. When -mtune= is used:
4eed87de 930
76bc74dc
L		 931 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
932 PROCESSOR_GENERIC32, f32_patt will be used.
933 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 934 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
935 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 936 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
937 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 938
76bc74dc
L		 939 When -mtune= isn't used, alt_long_patt will be used if
940 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
941 be used.
ccc9c027
L		 942
943 When -march= or .arch is used, we can't use anything beyond
944 cpu_arch_isa_flags. */
945
946 if (flag_code == CODE_16BIT)
947 {
ccc9c027 948 if (count > 8)
33fef721 949 {
76bc74dc
L		 950 memcpy (fragP->fr_literal + fragP->fr_fix,
951 jump_31, count);
952 /* Adjust jump offset. */
953 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 954 }
76bc74dc
L		 955 else
956 memcpy (fragP->fr_literal + fragP->fr_fix,
957 f16_patt[count - 1], count);
252b5132 958 }
33fef721 959 else
ccc9c027
L		 960 {
961 const char *const *patt = NULL;
962
fbf3f584 963 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 964 {
965 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
966 switch (cpu_arch_tune)
967 {
968 case PROCESSOR_UNKNOWN:
969 /* We use cpu_arch_isa_flags to check if we SHOULD
970 optimize for Cpu686. */
fbf3f584 971 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 972 patt = alt_long_patt;
ccc9c027
L		 973 else
974 patt = f32_patt;
975 break;
ccc9c027
L		 976 case PROCESSOR_PENTIUMPRO:
977 case PROCESSOR_PENTIUM4:
978 case PROCESSOR_NOCONA:
ef05d495 979 case PROCESSOR_CORE:
76bc74dc 980 case PROCESSOR_CORE2:
bd5295b2 981 case PROCESSOR_COREI7:
76bc74dc
L		 982 case PROCESSOR_GENERIC64:
983 patt = alt_long_patt;
984 break;
ccc9c027
L		 985 case PROCESSOR_K6:
986 case PROCESSOR_ATHLON:
987 case PROCESSOR_K8:
4eed87de 988 case PROCESSOR_AMDFAM10:
ccc9c027
L		 989 patt = alt_short_patt;
990 break;
76bc74dc 991 case PROCESSOR_I386:
ccc9c027
L		 992 case PROCESSOR_I486:
993 case PROCESSOR_PENTIUM:
994 case PROCESSOR_GENERIC32:
995 patt = f32_patt;
996 break;
4eed87de 997 }
ccc9c027
L		 998 }
999 else
1000 {
fbf3f584 1001 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1002 {
1003 case PROCESSOR_UNKNOWN:
e6a14101 1004 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1005 PROCESSOR_UNKNOWN. */
1006 abort ();
1007 break;
1008
76bc74dc 1009 case PROCESSOR_I386:
ccc9c027
L		 1010 case PROCESSOR_I486:
1011 case PROCESSOR_PENTIUM:
ccc9c027
L		 1012 case PROCESSOR_K6:
1013 case PROCESSOR_ATHLON:
1014 case PROCESSOR_K8:
4eed87de 1015 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1016 case PROCESSOR_GENERIC32:
1017 /* We use cpu_arch_isa_flags to check if we CAN optimize
1018 for Cpu686. */
fbf3f584 1019 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1020 patt = alt_short_patt;
1021 else
1022 patt = f32_patt;
1023 break;
76bc74dc
L		 1024 case PROCESSOR_PENTIUMPRO:
1025 case PROCESSOR_PENTIUM4:
1026 case PROCESSOR_NOCONA:
1027 case PROCESSOR_CORE:
ef05d495 1028 case PROCESSOR_CORE2:
bd5295b2 1029 case PROCESSOR_COREI7:
fbf3f584 1030 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1031 patt = alt_long_patt;
1032 else
1033 patt = f32_patt;
1034 break;
1035 case PROCESSOR_GENERIC64:
76bc74dc 1036 patt = alt_long_patt;
ccc9c027 1037 break;
4eed87de 1038 }
ccc9c027
L		 1039 }
1040
76bc74dc
L		 1041 if (patt == f32_patt)
1042 {
1043 /* If the padding is less than 15 bytes, we use the normal
1044 ones. Otherwise, we use a jump instruction and adjust
1045 its offset. */
1046 if (count < 15)
1047 memcpy (fragP->fr_literal + fragP->fr_fix,
1048 patt[count - 1], count);
1049 else
1050 {
1051 memcpy (fragP->fr_literal + fragP->fr_fix,
1052 jump_31, count);
1053 /* Adjust jump offset. */
1054 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1055 }
1056 }
1057 else
1058 {
1059 /* Maximum length of an instruction is 15 byte. If the
1060 padding is greater than 15 bytes and we don't use jump,
1061 we have to break it into smaller pieces. */
1062 int padding = count;
1063 while (padding > 15)
1064 {
1065 padding -= 15;
1066 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1067 patt [14], 15);
1068 }
1069
1070 if (padding)
1071 memcpy (fragP->fr_literal + fragP->fr_fix,
1072 patt [padding - 1], padding);
1073 }
ccc9c027 1074 }
33fef721 1075 fragP->fr_var = count;
252b5132
RH		 1076}
1077
c6fb90c8 1078static INLINE int
0dfbf9d7 1079operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1080{
0dfbf9d7 1081 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1082 {
1083 case 3:
0dfbf9d7 1084 if (x->array[2])
c6fb90c8
L		 1085 return 0;
1086 case 2:
0dfbf9d7 1087 if (x->array[1])
c6fb90c8
L		 1088 return 0;
1089 case 1:
0dfbf9d7 1090 return !x->array[0];
c6fb90c8
L		 1091 default:
1092 abort ();
1093 }
40fb9820
L		 1094}
1095
c6fb90c8 1096static INLINE void
0dfbf9d7 1097operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1098{
0dfbf9d7 1099 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1100 {
1101 case 3:
0dfbf9d7 1102 x->array[2] = v;
c6fb90c8 1103 case 2:
0dfbf9d7 1104 x->array[1] = v;
c6fb90c8 1105 case 1:
0dfbf9d7 1106 x->array[0] = v;
c6fb90c8
L		 1107 break;
1108 default:
1109 abort ();
1110 }
1111}
40fb9820 1112
c6fb90c8 1113static INLINE int
0dfbf9d7
L		 1114operand_type_equal (const union i386_operand_type *x,
1115 const union i386_operand_type *y)
c6fb90c8 1116{
0dfbf9d7 1117 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1118 {
1119 case 3:
0dfbf9d7 1120 if (x->array[2] != y->array[2])
c6fb90c8
L		 1121 return 0;
1122 case 2:
0dfbf9d7 1123 if (x->array[1] != y->array[1])
c6fb90c8
L		 1124 return 0;
1125 case 1:
0dfbf9d7 1126 return x->array[0] == y->array[0];
c6fb90c8
L		 1127 break;
1128 default:
1129 abort ();
1130 }
1131}
40fb9820 1132
0dfbf9d7
L		 1133static INLINE int
1134cpu_flags_all_zero (const union i386_cpu_flags *x)
1135{
1136 switch (ARRAY_SIZE(x->array))
1137 {
1138 case 3:
1139 if (x->array[2])
1140 return 0;
1141 case 2:
1142 if (x->array[1])
1143 return 0;
1144 case 1:
1145 return !x->array[0];
1146 default:
1147 abort ();
1148 }
1149}
1150
1151static INLINE void
1152cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1153{
1154 switch (ARRAY_SIZE(x->array))
1155 {
1156 case 3:
1157 x->array[2] = v;
1158 case 2:
1159 x->array[1] = v;
1160 case 1:
1161 x->array[0] = v;
1162 break;
1163 default:
1164 abort ();
1165 }
1166}
1167
1168static INLINE int
1169cpu_flags_equal (const union i386_cpu_flags *x,
1170 const union i386_cpu_flags *y)
1171{
1172 switch (ARRAY_SIZE(x->array))
1173 {
1174 case 3:
1175 if (x->array[2] != y->array[2])
1176 return 0;
1177 case 2:
1178 if (x->array[1] != y->array[1])
1179 return 0;
1180 case 1:
1181 return x->array[0] == y->array[0];
1182 break;
1183 default:
1184 abort ();
1185 }
1186}
c6fb90c8
L		 1187
1188static INLINE int
1189cpu_flags_check_cpu64 (i386_cpu_flags f)
1190{
1191 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1192 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1193}
1194
c6fb90c8
L		 1195static INLINE i386_cpu_flags
1196cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1197{
c6fb90c8
L		 1198 switch (ARRAY_SIZE (x.array))
1199 {
1200 case 3:
1201 x.array [2] &= y.array [2];
1202 case 2:
1203 x.array [1] &= y.array [1];
1204 case 1:
1205 x.array [0] &= y.array [0];
1206 break;
1207 default:
1208 abort ();
1209 }
1210 return x;
1211}
40fb9820 1212
c6fb90c8
L		 1213static INLINE i386_cpu_flags
1214cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1215{
c6fb90c8 1216 switch (ARRAY_SIZE (x.array))
40fb9820 1217 {
c6fb90c8
L		 1218 case 3:
1219 x.array [2] |= y.array [2];
1220 case 2:
1221 x.array [1] |= y.array [1];
1222 case 1:
1223 x.array [0] |= y.array [0];
40fb9820
L		 1224 break;
1225 default:
1226 abort ();
1227 }
40fb9820
L		 1228 return x;
1229}
1230
c0f3af97
L		 1231#define CPU_FLAGS_ARCH_MATCH 0x1
1232#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1233#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1234#define CPU_FLAGS_PCLMUL_MATCH 0x8
1235#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1236
a5ff0eb2 1237#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1238 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1239 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1240#define CPU_FLAGS_PERFECT_MATCH \
1241 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1242
1243/* Return CPU flags match bits. */
3629bb00 1244
40fb9820 1245static int
c0f3af97 1246cpu_flags_match (const template *t)
40fb9820 1247{
c0f3af97
L		 1248 i386_cpu_flags x = t->cpu_flags;
1249 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1250
1251 x.bitfield.cpu64 = 0;
1252 x.bitfield.cpuno64 = 0;
1253
0dfbf9d7 1254 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1255 {
1256 /* This instruction is available on all archs. */
1257 match |= CPU_FLAGS_32BIT_MATCH;
1258 }
3629bb00
L		 1259 else
1260 {
c0f3af97 1261 /* This instruction is available only on some archs. */
3629bb00
L		 1262 i386_cpu_flags cpu = cpu_arch_flags;
1263
1264 cpu.bitfield.cpu64 = 0;
1265 cpu.bitfield.cpuno64 = 0;
1266 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1267 if (!cpu_flags_all_zero (&cpu))
1268 {
a5ff0eb2
L		 1269 if (x.bitfield.cpuavx)
1270 {
ce2f5b3c 1271 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1272 if (cpu.bitfield.cpuavx)
1273 {
1274 /* Check SSE2AVX. */
1275 if (!t->opcode_modifier.sse2avx|| sse2avx)
1276 {
1277 match |= (CPU_FLAGS_ARCH_MATCH
1278 | CPU_FLAGS_AVX_MATCH);
1279 /* Check AES. */
1280 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1281 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1282 /* Check PCLMUL. */
1283 if (!x.bitfield.cpupclmul
1284 || cpu.bitfield.cpupclmul)
1285 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1286 }
1287 }
1288 else
1289 match |= CPU_FLAGS_ARCH_MATCH;
1290 }
1291 else
c0f3af97
L		 1292 match |= CPU_FLAGS_32BIT_MATCH;
1293 }
3629bb00 1294 }
c0f3af97 1295 return match;
40fb9820
L		 1296}
1297
c6fb90c8
L		 1298static INLINE i386_operand_type
1299operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1300{
c6fb90c8
L		 1301 switch (ARRAY_SIZE (x.array))
1302 {
1303 case 3:
1304 x.array [2] &= y.array [2];
1305 case 2:
1306 x.array [1] &= y.array [1];
1307 case 1:
1308 x.array [0] &= y.array [0];
1309 break;
1310 default:
1311 abort ();
1312 }
1313 return x;
40fb9820
L		 1314}
1315
c6fb90c8
L		 1316static INLINE i386_operand_type
1317operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1318{
c6fb90c8 1319 switch (ARRAY_SIZE (x.array))
40fb9820 1320 {
c6fb90c8
L		 1321 case 3:
1322 x.array [2] |= y.array [2];
1323 case 2:
1324 x.array [1] |= y.array [1];
1325 case 1:
1326 x.array [0] |= y.array [0];
40fb9820
L		 1327 break;
1328 default:
1329 abort ();
1330 }
c6fb90c8
L		 1331 return x;
1332}
40fb9820 1333
c6fb90c8
L		 1334static INLINE i386_operand_type
1335operand_type_xor (i386_operand_type x, i386_operand_type y)
1336{
1337 switch (ARRAY_SIZE (x.array))
1338 {
1339 case 3:
1340 x.array [2] ^= y.array [2];
1341 case 2:
1342 x.array [1] ^= y.array [1];
1343 case 1:
1344 x.array [0] ^= y.array [0];
1345 break;
1346 default:
1347 abort ();
1348 }
40fb9820
L		 1349 return x;
1350}
1351
1352static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1353static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1354static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1355static const i386_operand_type inoutportreg
1356 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1357static const i386_operand_type reg16_inoutportreg
1358 = OPERAND_TYPE_REG16_INOUTPORTREG;
1359static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1360static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1361static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1362static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1363static const i386_operand_type anydisp
1364 = OPERAND_TYPE_ANYDISP;
40fb9820 1365static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1366static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1367static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1368static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1369static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1370static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1371static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1372static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1373static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1374static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1375static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1376
1377enum operand_type
1378{
1379 reg,
40fb9820
L		 1380 imm,
1381 disp,
1382 anymem
1383};
1384
c6fb90c8 1385static INLINE int
40fb9820
L		 1386operand_type_check (i386_operand_type t, enum operand_type c)
1387{
1388 switch (c)
1389 {
1390 case reg:
1391 return (t.bitfield.reg8
1392 || t.bitfield.reg16
1393 || t.bitfield.reg32
1394 || t.bitfield.reg64);
1395
40fb9820
L		 1396 case imm:
1397 return (t.bitfield.imm8
1398 || t.bitfield.imm8s
1399 || t.bitfield.imm16
1400 || t.bitfield.imm32
1401 || t.bitfield.imm32s
1402 || t.bitfield.imm64);
1403
1404 case disp:
1405 return (t.bitfield.disp8
1406 || t.bitfield.disp16
1407 || t.bitfield.disp32
1408 || t.bitfield.disp32s
1409 || t.bitfield.disp64);
1410
1411 case anymem:
1412 return (t.bitfield.disp8
1413 || t.bitfield.disp16
1414 || t.bitfield.disp32
1415 || t.bitfield.disp32s
1416 || t.bitfield.disp64
1417 || t.bitfield.baseindex);
1418
1419 default:
1420 abort ();
1421 }
2cfe26b6
AM		 1422
1423 return 0;
40fb9820
L		 1424}
1425
5c07affc
L		 1426/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1427 operand J for instruction template T. */
1428
1429static INLINE int
1430match_reg_size (const template *t, unsigned int j)
1431{
1432 return !((i.types[j].bitfield.byte
1433 && !t->operand_types[j].bitfield.byte)
1434 || (i.types[j].bitfield.word
1435 && !t->operand_types[j].bitfield.word)
1436 || (i.types[j].bitfield.dword
1437 && !t->operand_types[j].bitfield.dword)
1438 || (i.types[j].bitfield.qword
1439 && !t->operand_types[j].bitfield.qword));
1440}
1441
1442/* Return 1 if there is no conflict in any size on operand J for
1443 instruction template T. */
1444
1445static INLINE int
1446match_mem_size (const template *t, unsigned int j)
1447{
1448 return (match_reg_size (t, j)
1449 && !((i.types[j].bitfield.unspecified
1450 && !t->operand_types[j].bitfield.unspecified)
1451 || (i.types[j].bitfield.fword
1452 && !t->operand_types[j].bitfield.fword)
1453 || (i.types[j].bitfield.tbyte
1454 && !t->operand_types[j].bitfield.tbyte)
1455 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1456 && !t->operand_types[j].bitfield.xmmword)
1457 || (i.types[j].bitfield.ymmword
1458 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1459}
1460
1461/* Return 1 if there is no size conflict on any operands for
1462 instruction template T. */
1463
1464static INLINE int
1465operand_size_match (const template *t)
1466{
1467 unsigned int j;
1468 int match = 1;
1469
1470 /* Don't check jump instructions. */
1471 if (t->opcode_modifier.jump
1472 || t->opcode_modifier.jumpbyte
1473 || t->opcode_modifier.jumpdword
1474 || t->opcode_modifier.jumpintersegment)
1475 return match;
1476
1477 /* Check memory and accumulator operand size. */
1478 for (j = 0; j < i.operands; j++)
1479 {
1480 if (t->operand_types[j].bitfield.anysize)
1481 continue;
1482
1483 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1484 {
1485 match = 0;
1486 break;
1487 }
1488
1489 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1490 {
1491 match = 0;
1492 break;
1493 }
1494 }
1495
1496 if (match
1497 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1498 return match;
1499
1500 /* Check reverse. */
9c2799c2 1501 gas_assert (i.operands == 2);
5c07affc
L		 1502
1503 match = 1;
1504 for (j = 0; j < 2; j++)
1505 {
1506 if (t->operand_types[j].bitfield.acc
1507 && !match_reg_size (t, j ? 0 : 1))
1508 {
1509 match = 0;
1510 break;
1511 }
1512
1513 if (i.types[j].bitfield.mem
1514 && !match_mem_size (t, j ? 0 : 1))
1515 {
1516 match = 0;
1517 break;
1518 }
1519 }
1520
1521 return match;
1522}
1523
c6fb90c8 1524static INLINE int
40fb9820
L		 1525operand_type_match (i386_operand_type overlap,
1526 i386_operand_type given)
1527{
1528 i386_operand_type temp = overlap;
1529
1530 temp.bitfield.jumpabsolute = 0;
7d5e4556 1531 temp.bitfield.unspecified = 0;
5c07affc
L		 1532 temp.bitfield.byte = 0;
1533 temp.bitfield.word = 0;
1534 temp.bitfield.dword = 0;
1535 temp.bitfield.fword = 0;
1536 temp.bitfield.qword = 0;
1537 temp.bitfield.tbyte = 0;
1538 temp.bitfield.xmmword = 0;
c0f3af97 1539 temp.bitfield.ymmword = 0;
0dfbf9d7 1540 if (operand_type_all_zero (&temp))
40fb9820
L		 1541 return 0;
1542
1543 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1544 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1545}
1546
7d5e4556 1547/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1548 unless the expected operand type register overlap is null.
1549 Note that Acc in a template matches every size of reg. */
1550
c6fb90c8 1551static INLINE int
40fb9820
L		 1552operand_type_register_match (i386_operand_type m0,
1553 i386_operand_type g0,
1554 i386_operand_type t0,
1555 i386_operand_type m1,
1556 i386_operand_type g1,
1557 i386_operand_type t1)
1558{
1559 if (!operand_type_check (g0, reg))
1560 return 1;
1561
1562 if (!operand_type_check (g1, reg))
1563 return 1;
1564
1565 if (g0.bitfield.reg8 == g1.bitfield.reg8
1566 && g0.bitfield.reg16 == g1.bitfield.reg16
1567 && g0.bitfield.reg32 == g1.bitfield.reg32
1568 && g0.bitfield.reg64 == g1.bitfield.reg64)
1569 return 1;
1570
1571 if (m0.bitfield.acc)
1572 {
1573 t0.bitfield.reg8 = 1;
1574 t0.bitfield.reg16 = 1;
1575 t0.bitfield.reg32 = 1;
1576 t0.bitfield.reg64 = 1;
1577 }
1578
1579 if (m1.bitfield.acc)
1580 {
1581 t1.bitfield.reg8 = 1;
1582 t1.bitfield.reg16 = 1;
1583 t1.bitfield.reg32 = 1;
1584 t1.bitfield.reg64 = 1;
1585 }
1586
1587 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1588 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1589 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1590 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1591}
1592
252b5132 1593static INLINE unsigned int
40fb9820 1594mode_from_disp_size (i386_operand_type t)
252b5132 1595{
40fb9820
L		 1596 if (t.bitfield.disp8)
1597 return 1;
1598 else if (t.bitfield.disp16
1599 || t.bitfield.disp32
1600 || t.bitfield.disp32s)
1601 return 2;
1602 else
1603 return 0;
252b5132
RH		 1604}
1605
1606static INLINE int
e3bb37b5 1607fits_in_signed_byte (offsetT num)
252b5132
RH		 1608{
1609 return (num >= -128) && (num <= 127);
47926f60 1610}
252b5132
RH		 1611
1612static INLINE int
e3bb37b5 1613fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1614{
1615 return (num & 0xff) == num;
47926f60 1616}
252b5132
RH		 1617
1618static INLINE int
e3bb37b5 1619fits_in_unsigned_word (offsetT num)
252b5132
RH		 1620{
1621 return (num & 0xffff) == num;
47926f60 1622}
252b5132
RH		 1623
1624static INLINE int
e3bb37b5 1625fits_in_signed_word (offsetT num)
252b5132
RH		 1626{
1627 return (-32768 <= num) && (num <= 32767);
47926f60 1628}
2a962e6d 1629
3e73aa7c 1630static INLINE int
e3bb37b5 1631fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1632{
1633#ifndef BFD64
1634 return 1;
1635#else
1636 return (!(((offsetT) -1 << 31) & num)
1637 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1638#endif
1639} /* fits_in_signed_long() */
2a962e6d 1640
3e73aa7c 1641static INLINE int
e3bb37b5 1642fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1643{
1644#ifndef BFD64
1645 return 1;
1646#else
1647 return (num & (((offsetT) 2 << 31) - 1)) == num;
1648#endif
1649} /* fits_in_unsigned_long() */
252b5132 1650
40fb9820 1651static i386_operand_type
e3bb37b5 1652smallest_imm_type (offsetT num)
252b5132 1653{
40fb9820 1654 i386_operand_type t;
7ab9ffdd 1655
0dfbf9d7 1656 operand_type_set (&t, 0);
40fb9820
L		 1657 t.bitfield.imm64 = 1;
1658
1659 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1660 {
1661 /* This code is disabled on the 486 because all the Imm1 forms
1662 in the opcode table are slower on the i486. They're the
1663 versions with the implicitly specified single-position
1664 displacement, which has another syntax if you really want to
1665 use that form. */
40fb9820
L		 1666 t.bitfield.imm1 = 1;
1667 t.bitfield.imm8 = 1;
1668 t.bitfield.imm8s = 1;
1669 t.bitfield.imm16 = 1;
1670 t.bitfield.imm32 = 1;
1671 t.bitfield.imm32s = 1;
1672 }
1673 else if (fits_in_signed_byte (num))
1674 {
1675 t.bitfield.imm8 = 1;
1676 t.bitfield.imm8s = 1;
1677 t.bitfield.imm16 = 1;
1678 t.bitfield.imm32 = 1;
1679 t.bitfield.imm32s = 1;
1680 }
1681 else if (fits_in_unsigned_byte (num))
1682 {
1683 t.bitfield.imm8 = 1;
1684 t.bitfield.imm16 = 1;
1685 t.bitfield.imm32 = 1;
1686 t.bitfield.imm32s = 1;
1687 }
1688 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1689 {
1690 t.bitfield.imm16 = 1;
1691 t.bitfield.imm32 = 1;
1692 t.bitfield.imm32s = 1;
1693 }
1694 else if (fits_in_signed_long (num))
1695 {
1696 t.bitfield.imm32 = 1;
1697 t.bitfield.imm32s = 1;
1698 }
1699 else if (fits_in_unsigned_long (num))
1700 t.bitfield.imm32 = 1;
1701
1702 return t;
47926f60 1703}
252b5132 1704
847f7ad4 1705static offsetT
e3bb37b5 1706offset_in_range (offsetT val, int size)
847f7ad4 1707{
508866be 1708 addressT mask;
ba2adb93 1709
847f7ad4
AM		 1710 switch (size)
1711 {
508866be
L		 1712 case 1: mask = ((addressT) 1 << 8) - 1; break;
1713 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1714 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1715#ifdef BFD64
1716 case 8: mask = ((addressT) 2 << 63) - 1; break;
1717#endif
47926f60 1718 default: abort ();
847f7ad4
AM		 1719 }
1720
ba2adb93 1721 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1722 if (!use_rela_relocations)
1723 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1724 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1725
47926f60 1726 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1727 {
1728 char buf1[40], buf2[40];
1729
1730 sprint_value (buf1, val);
1731 sprint_value (buf2, val & mask);
1732 as_warn (_("%s shortened to %s"), buf1, buf2);
1733 }
1734 return val & mask;
1735}
1736
252b5132
RH		 1737/* Returns 0 if attempting to add a prefix where one from the same
1738 class already exists, 1 if non rep/repne added, 2 if rep/repne
1739 added. */
1740static int
e3bb37b5 1741add_prefix (unsigned int prefix)
252b5132
RH		 1742{
1743 int ret = 1;
b1905489 1744 unsigned int q;
252b5132 1745
29b0f896
AM		 1746 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1747 && flag_code == CODE_64BIT)
b1905489 1748 {
161a04f6
L		 1749 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1750 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1751 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1752 ret = 0;
1753 q = REX_PREFIX;
1754 }
3e73aa7c 1755 else
b1905489
JB		 1756 {
1757 switch (prefix)
1758 {
1759 default:
1760 abort ();
1761
1762 case CS_PREFIX_OPCODE:
1763 case DS_PREFIX_OPCODE:
1764 case ES_PREFIX_OPCODE:
1765 case FS_PREFIX_OPCODE:
1766 case GS_PREFIX_OPCODE:
1767 case SS_PREFIX_OPCODE:
1768 q = SEG_PREFIX;
1769 break;
1770
1771 case REPNE_PREFIX_OPCODE:
1772 case REPE_PREFIX_OPCODE:
1773 ret = 2;
1774 /* fall thru */
1775 case LOCK_PREFIX_OPCODE:
1776 q = LOCKREP_PREFIX;
1777 break;
1778
1779 case FWAIT_OPCODE:
1780 q = WAIT_PREFIX;
1781 break;
1782
1783 case ADDR_PREFIX_OPCODE:
1784 q = ADDR_PREFIX;
1785 break;
1786
1787 case DATA_PREFIX_OPCODE:
1788 q = DATA_PREFIX;
1789 break;
1790 }
1791 if (i.prefix[q] != 0)
1792 ret = 0;
1793 }
252b5132 1794
b1905489 1795 if (ret)
252b5132 1796 {
b1905489
JB		 1797 if (!i.prefix[q])
1798 ++i.prefixes;
1799 i.prefix[q] |= prefix;
252b5132 1800 }
b1905489
JB		 1801 else
1802 as_bad (_("same type of prefix used twice"));
252b5132 1803
252b5132
RH		 1804 return ret;
1805}
1806
1807static void
e3bb37b5 1808set_code_flag (int value)
eecb386c 1809{
3e73aa7c 1810 flag_code = value;
40fb9820
L		 1811 if (flag_code == CODE_64BIT)
1812 {
1813 cpu_arch_flags.bitfield.cpu64 = 1;
1814 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1815 }
1816 else
1817 {
1818 cpu_arch_flags.bitfield.cpu64 = 0;
1819 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1820 }
1821 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1822 {
1823 as_bad (_("64bit mode not supported on this CPU."));
1824 }
40fb9820 1825 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1826 {
1827 as_bad (_("32bit mode not supported on this CPU."));
1828 }
eecb386c
AM		 1829 stackop_size = '\0';
1830}
1831
1832static void
e3bb37b5 1833set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1834{
3e73aa7c 1835 flag_code = new_code_flag;
40fb9820
L		 1836 if (flag_code != CODE_16BIT)
1837 abort ();
1838 cpu_arch_flags.bitfield.cpu64 = 0;
1839 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1840 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1841}
1842
1843static void
e3bb37b5 1844set_intel_syntax (int syntax_flag)
252b5132
RH		 1845{
1846 /* Find out if register prefixing is specified. */
1847 int ask_naked_reg = 0;
1848
1849 SKIP_WHITESPACE ();
29b0f896 1850 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1851 {
1852 char *string = input_line_pointer;
1853 int e = get_symbol_end ();
1854
47926f60 1855 if (strcmp (string, "prefix") == 0)
252b5132 1856 ask_naked_reg = 1;
47926f60 1857 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1858 ask_naked_reg = -1;
1859 else
d0b47220 1860 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1861 *input_line_pointer = e;
1862 }
1863 demand_empty_rest_of_line ();
c3332e24 1864
252b5132
RH		 1865 intel_syntax = syntax_flag;
1866
1867 if (ask_naked_reg == 0)
f86103b7
AM		 1868 allow_naked_reg = (intel_syntax
1869 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1870 else
1871 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1872
ee86248c 1873 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1874
e4a3b5a4 1875 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1876 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1877 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1878}
1879
1efbbeb4
L		 1880static void
1881set_intel_mnemonic (int mnemonic_flag)
1882{
e1d4d893 1883 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1884}
1885
db51cc60
L		 1886static void
1887set_allow_index_reg (int flag)
1888{
1889 allow_index_reg = flag;
1890}
1891
cb19c032
L		 1892static void
1893set_sse_check (int dummy ATTRIBUTE_UNUSED)
1894{
1895 SKIP_WHITESPACE ();
1896
1897 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1898 {
1899 char *string = input_line_pointer;
1900 int e = get_symbol_end ();
1901
1902 if (strcmp (string, "none") == 0)
1903 sse_check = sse_check_none;
1904 else if (strcmp (string, "warning") == 0)
1905 sse_check = sse_check_warning;
1906 else if (strcmp (string, "error") == 0)
1907 sse_check = sse_check_error;
1908 else
1909 as_bad (_("bad argument to sse_check directive."));
1910 *input_line_pointer = e;
1911 }
1912 else
1913 as_bad (_("missing argument for sse_check directive"));
1914
1915 demand_empty_rest_of_line ();
1916}
1917
e413e4e9 1918static void
e3bb37b5 1919set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1920{
47926f60 1921 SKIP_WHITESPACE ();
e413e4e9 1922
29b0f896 1923 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1924 {
1925 char *string = input_line_pointer;
1926 int e = get_symbol_end ();
9103f4f4 1927 unsigned int i;
40fb9820 1928 i386_cpu_flags flags;
e413e4e9 1929
9103f4f4 1930 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1931 {
1932 if (strcmp (string, cpu_arch[i].name) == 0)
1933 {
5c6af06e
JB		 1934 if (*string != '.')
1935 {
1936 cpu_arch_name = cpu_arch[i].name;
1937 cpu_sub_arch_name = NULL;
40fb9820
L		 1938 cpu_arch_flags = cpu_arch[i].flags;
1939 if (flag_code == CODE_64BIT)
1940 {
1941 cpu_arch_flags.bitfield.cpu64 = 1;
1942 cpu_arch_flags.bitfield.cpuno64 = 0;
1943 }
1944 else
1945 {
1946 cpu_arch_flags.bitfield.cpu64 = 0;
1947 cpu_arch_flags.bitfield.cpuno64 = 1;
1948 }
ccc9c027 1949 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1950 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1951 if (!cpu_arch_tune_set)
1952 {
1953 cpu_arch_tune = cpu_arch_isa;
1954 cpu_arch_tune_flags = cpu_arch_isa_flags;
1955 }
5c6af06e
JB		 1956 break;
1957 }
40fb9820 1958
c6fb90c8
L		 1959 flags = cpu_flags_or (cpu_arch_flags,
1960 cpu_arch[i].flags);
0dfbf9d7 1961 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1962 {
6305a203
L		 1963 if (cpu_sub_arch_name)
1964 {
1965 char *name = cpu_sub_arch_name;
1966 cpu_sub_arch_name = concat (name,
1967 cpu_arch[i].name,
1bf57e9f 1968 (const char *) NULL);
6305a203
L		 1969 free (name);
1970 }
1971 else
1972 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1973 cpu_arch_flags = flags;
5c6af06e
JB		 1974 }
1975 *input_line_pointer = e;
1976 demand_empty_rest_of_line ();
1977 return;
e413e4e9
AM		 1978 }
1979 }
9103f4f4 1980 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1981 as_bad (_("no such architecture: `%s'"), string);
1982
1983 *input_line_pointer = e;
1984 }
1985 else
1986 as_bad (_("missing cpu architecture"));
1987
fddf5b5b
AM		 1988 no_cond_jump_promotion = 0;
1989 if (*input_line_pointer == ','
29b0f896 1990 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1991 {
1992 char *string = ++input_line_pointer;
1993 int e = get_symbol_end ();
1994
1995 if (strcmp (string, "nojumps") == 0)
1996 no_cond_jump_promotion = 1;
1997 else if (strcmp (string, "jumps") == 0)
1998 ;
1999 else
2000 as_bad (_("no such architecture modifier: `%s'"), string);
2001
2002 *input_line_pointer = e;
2003 }
2004
e413e4e9
AM		 2005 demand_empty_rest_of_line ();
2006}
2007
b9d79e03
JH		 2008unsigned long
2009i386_mach ()
2010{
2011 if (!strcmp (default_arch, "x86_64"))
2012 return bfd_mach_x86_64;
2013 else if (!strcmp (default_arch, "i386"))
2014 return bfd_mach_i386_i386;
2015 else
2016 as_fatal (_("Unknown architecture"));
2017}
b9d79e03 2018\f
252b5132
RH		 2019void
2020md_begin ()
2021{
2022 const char *hash_err;
2023
47926f60 2024 /* Initialize op_hash hash table. */
252b5132
RH		 2025 op_hash = hash_new ();
2026
2027 {
29b0f896
AM		 2028 const template *optab;
2029 templates *core_optab;
252b5132 2030
47926f60
KH		 2031 /* Setup for loop. */
2032 optab = i386_optab;
252b5132
RH		 2033 core_optab = (templates *) xmalloc (sizeof (templates));
2034 core_optab->start = optab;
2035
2036 while (1)
2037 {
2038 ++optab;
2039 if (optab->name == NULL
2040 || strcmp (optab->name, (optab - 1)->name) != 0)
2041 {
2042 /* different name --> ship out current template list;
47926f60 2043 add to hash table; & begin anew. */
252b5132
RH		 2044 core_optab->end = optab;
2045 hash_err = hash_insert (op_hash,
2046 (optab - 1)->name,
5a49b8ac 2047 (void *) core_optab);
252b5132
RH		 2048 if (hash_err)
2049 {
252b5132
RH		 2050 as_fatal (_("Internal Error: Can't hash %s: %s"),
2051 (optab - 1)->name,
2052 hash_err);
2053 }
2054 if (optab->name == NULL)
2055 break;
2056 core_optab = (templates *) xmalloc (sizeof (templates));
2057 core_optab->start = optab;
2058 }
2059 }
2060 }
2061
47926f60 2062 /* Initialize reg_hash hash table. */
252b5132
RH		 2063 reg_hash = hash_new ();
2064 {
29b0f896 2065 const reg_entry *regtab;
c3fe08fa 2066 unsigned int regtab_size = i386_regtab_size;
252b5132 2067
c3fe08fa 2068 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2069 {
5a49b8ac 2070 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2071 if (hash_err)
3e73aa7c
JH		 2072 as_fatal (_("Internal Error: Can't hash %s: %s"),
2073 regtab->reg_name,
2074 hash_err);
252b5132
RH		 2075 }
2076 }
2077
47926f60 2078 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2079 {
29b0f896
AM		 2080 int c;
2081 char *p;
252b5132
RH		 2082
2083 for (c = 0; c < 256; c++)
2084 {
3882b010 2085 if (ISDIGIT (c))
252b5132
RH		 2086 {
2087 digit_chars[c] = c;
2088 mnemonic_chars[c] = c;
2089 register_chars[c] = c;
2090 operand_chars[c] = c;
2091 }
3882b010 2092 else if (ISLOWER (c))
252b5132
RH		 2093 {
2094 mnemonic_chars[c] = c;
2095 register_chars[c] = c;
2096 operand_chars[c] = c;
2097 }
3882b010 2098 else if (ISUPPER (c))
252b5132 2099 {
3882b010 2100 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2101 register_chars[c] = mnemonic_chars[c];
2102 operand_chars[c] = c;
2103 }
2104
3882b010 2105 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2106 identifier_chars[c] = c;
2107 else if (c >= 128)
2108 {
2109 identifier_chars[c] = c;
2110 operand_chars[c] = c;
2111 }
2112 }
2113
2114#ifdef LEX_AT
2115 identifier_chars['@'] = '@';
32137342
NC		 2116#endif
2117#ifdef LEX_QM
2118 identifier_chars['?'] = '?';
2119 operand_chars['?'] = '?';
252b5132 2120#endif
252b5132 2121 digit_chars['-'] = '-';
c0f3af97 2122 mnemonic_chars['_'] = '_';
791fe849 2123 mnemonic_chars['-'] = '-';
0003779b 2124 mnemonic_chars['.'] = '.';
252b5132
RH		 2125 identifier_chars['_'] = '_';
2126 identifier_chars['.'] = '.';
2127
2128 for (p = operand_special_chars; *p != '\0'; p++)
2129 operand_chars[(unsigned char) *p] = *p;
2130 }
2131
2132#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2133 if (IS_ELF)
252b5132
RH		 2134 {
2135 record_alignment (text_section, 2);
2136 record_alignment (data_section, 2);
2137 record_alignment (bss_section, 2);
2138 }
2139#endif
a4447b93
RH		 2140
2141 if (flag_code == CODE_64BIT)
2142 {
2143 x86_dwarf2_return_column = 16;
2144 x86_cie_data_alignment = -8;
2145 }
2146 else
2147 {
2148 x86_dwarf2_return_column = 8;
2149 x86_cie_data_alignment = -4;
2150 }
252b5132
RH		 2151}
2152
2153void
e3bb37b5 2154i386_print_statistics (FILE *file)
252b5132
RH		 2155{
2156 hash_print_statistics (file, "i386 opcode", op_hash);
2157 hash_print_statistics (file, "i386 register", reg_hash);
2158}
2159\f
252b5132
RH		 2160#ifdef DEBUG386
2161
ce8a8b2f 2162/* Debugging routines for md_assemble. */
e3bb37b5 2163static void pte (template *);
40fb9820 2164static void pt (i386_operand_type);
e3bb37b5
L		 2165static void pe (expressionS *);
2166static void ps (symbolS *);
252b5132
RH		 2167
2168static void
e3bb37b5 2169pi (char *line, i386_insn *x)
252b5132 2170{
09f131f2 2171 unsigned int i;
252b5132
RH		 2172
2173 fprintf (stdout, "%s: template ", line);
2174 pte (&x->tm);
09f131f2
JH		 2175 fprintf (stdout, " address: base %s index %s scale %x\n",
2176 x->base_reg ? x->base_reg->reg_name : "none",
2177 x->index_reg ? x->index_reg->reg_name : "none",
2178 x->log2_scale_factor);
2179 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2180 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2181 fprintf (stdout, " sib: base %x index %x scale %x\n",
2182 x->sib.base, x->sib.index, x->sib.scale);
2183 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2184 (x->rex & REX_W) != 0,
2185 (x->rex & REX_R) != 0,
2186 (x->rex & REX_X) != 0,
2187 (x->rex & REX_B) != 0);
252b5132
RH		 2188 for (i = 0; i < x->operands; i++)
2189 {
2190 fprintf (stdout, " #%d: ", i + 1);
2191 pt (x->types[i]);
2192 fprintf (stdout, "\n");
40fb9820
L		 2193 if (x->types[i].bitfield.reg8
2194 || x->types[i].bitfield.reg16
2195 || x->types[i].bitfield.reg32
2196 || x->types[i].bitfield.reg64
2197 || x->types[i].bitfield.regmmx
2198 || x->types[i].bitfield.regxmm
c0f3af97 2199 || x->types[i].bitfield.regymm
40fb9820
L		 2200 || x->types[i].bitfield.sreg2
2201 || x->types[i].bitfield.sreg3
2202 || x->types[i].bitfield.control
2203 || x->types[i].bitfield.debug
2204 || x->types[i].bitfield.test)
520dc8e8 2205 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2206 if (operand_type_check (x->types[i], imm))
520dc8e8 2207 pe (x->op[i].imms);
40fb9820 2208 if (operand_type_check (x->types[i], disp))
520dc8e8 2209 pe (x->op[i].disps);
252b5132
RH		 2210 }
2211}
2212
2213static void
e3bb37b5 2214pte (template *t)
252b5132 2215{
09f131f2 2216 unsigned int i;
252b5132 2217 fprintf (stdout, " %d operands ", t->operands);
47926f60 2218 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2219 if (t->extension_opcode != None)
2220 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2221 if (t->opcode_modifier.d)
252b5132 2222 fprintf (stdout, "D");
40fb9820 2223 if (t->opcode_modifier.w)
252b5132
RH		 2224 fprintf (stdout, "W");
2225 fprintf (stdout, "\n");
2226 for (i = 0; i < t->operands; i++)
2227 {
2228 fprintf (stdout, " #%d type ", i + 1);
2229 pt (t->operand_types[i]);
2230 fprintf (stdout, "\n");
2231 }
2232}
2233
2234static void
e3bb37b5 2235pe (expressionS *e)
252b5132 2236{
24eab124 2237 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2238 fprintf (stdout, " add_number %ld (%lx)\n",
2239 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2240 if (e->X_add_symbol)
2241 {
2242 fprintf (stdout, " add_symbol ");
2243 ps (e->X_add_symbol);
2244 fprintf (stdout, "\n");
2245 }
2246 if (e->X_op_symbol)
2247 {
2248 fprintf (stdout, " op_symbol ");
2249 ps (e->X_op_symbol);
2250 fprintf (stdout, "\n");
2251 }
2252}
2253
2254static void
e3bb37b5 2255ps (symbolS *s)
252b5132
RH		 2256{
2257 fprintf (stdout, "%s type %s%s",
2258 S_GET_NAME (s),
2259 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2260 segment_name (S_GET_SEGMENT (s)));
2261}
2262
7b81dfbb 2263static struct type_name
252b5132 2264 {
40fb9820
L		 2265 i386_operand_type mask;
2266 const char *name;
252b5132 2267 }
7b81dfbb 2268const type_names[] =
252b5132 2269{
40fb9820
L		 2270 { OPERAND_TYPE_REG8, "r8" },
2271 { OPERAND_TYPE_REG16, "r16" },
2272 { OPERAND_TYPE_REG32, "r32" },
2273 { OPERAND_TYPE_REG64, "r64" },
2274 { OPERAND_TYPE_IMM8, "i8" },
2275 { OPERAND_TYPE_IMM8, "i8s" },
2276 { OPERAND_TYPE_IMM16, "i16" },
2277 { OPERAND_TYPE_IMM32, "i32" },
2278 { OPERAND_TYPE_IMM32S, "i32s" },
2279 { OPERAND_TYPE_IMM64, "i64" },
2280 { OPERAND_TYPE_IMM1, "i1" },
2281 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2282 { OPERAND_TYPE_DISP8, "d8" },
2283 { OPERAND_TYPE_DISP16, "d16" },
2284 { OPERAND_TYPE_DISP32, "d32" },
2285 { OPERAND_TYPE_DISP32S, "d32s" },
2286 { OPERAND_TYPE_DISP64, "d64" },
2287 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2288 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2289 { OPERAND_TYPE_CONTROL, "control reg" },
2290 { OPERAND_TYPE_TEST, "test reg" },
2291 { OPERAND_TYPE_DEBUG, "debug reg" },
2292 { OPERAND_TYPE_FLOATREG, "FReg" },
2293 { OPERAND_TYPE_FLOATACC, "FAcc" },
2294 { OPERAND_TYPE_SREG2, "SReg2" },
2295 { OPERAND_TYPE_SREG3, "SReg3" },
2296 { OPERAND_TYPE_ACC, "Acc" },
2297 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2298 { OPERAND_TYPE_REGMMX, "rMMX" },
2299 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2300 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2301 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2302};
2303
2304static void
40fb9820 2305pt (i386_operand_type t)
252b5132 2306{
40fb9820 2307 unsigned int j;
c6fb90c8 2308 i386_operand_type a;
252b5132 2309
40fb9820 2310 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2311 {
2312 a = operand_type_and (t, type_names[j].mask);
0349dc08 2313 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2314 fprintf (stdout, "%s, ", type_names[j].name);
2315 }
252b5132
RH		 2316 fflush (stdout);
2317}
2318
2319#endif /* DEBUG386 */
2320\f
252b5132 2321static bfd_reloc_code_real_type
3956db08 2322reloc (unsigned int size,
64e74474
AM		 2323 int pcrel,
2324 int sign,
2325 bfd_reloc_code_real_type other)
252b5132 2326{
47926f60 2327 if (other != NO_RELOC)
3956db08
JB		 2328 {
2329 reloc_howto_type *reloc;
2330
2331 if (size == 8)
2332 switch (other)
2333 {
64e74474
AM		 2334 case BFD_RELOC_X86_64_GOT32:
2335 return BFD_RELOC_X86_64_GOT64;
2336 break;
2337 case BFD_RELOC_X86_64_PLTOFF64:
2338 return BFD_RELOC_X86_64_PLTOFF64;
2339 break;
2340 case BFD_RELOC_X86_64_GOTPC32:
2341 other = BFD_RELOC_X86_64_GOTPC64;
2342 break;
2343 case BFD_RELOC_X86_64_GOTPCREL:
2344 other = BFD_RELOC_X86_64_GOTPCREL64;
2345 break;
2346 case BFD_RELOC_X86_64_TPOFF32:
2347 other = BFD_RELOC_X86_64_TPOFF64;
2348 break;
2349 case BFD_RELOC_X86_64_DTPOFF32:
2350 other = BFD_RELOC_X86_64_DTPOFF64;
2351 break;
2352 default:
2353 break;
3956db08 2354 }
e05278af
JB		 2355
2356 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2357 if (size == 4 && flag_code != CODE_64BIT)
2358 sign = -1;
2359
3956db08
JB		 2360 reloc = bfd_reloc_type_lookup (stdoutput, other);
2361 if (!reloc)
2362 as_bad (_("unknown relocation (%u)"), other);
2363 else if (size != bfd_get_reloc_size (reloc))
2364 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2365 bfd_get_reloc_size (reloc),
2366 size);
2367 else if (pcrel && !reloc->pc_relative)
2368 as_bad (_("non-pc-relative relocation for pc-relative field"));
2369 else if ((reloc->complain_on_overflow == complain_overflow_signed
2370 && !sign)
2371 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2372 && sign > 0))
3956db08
JB		 2373 as_bad (_("relocated field and relocation type differ in signedness"));
2374 else
2375 return other;
2376 return NO_RELOC;
2377 }
252b5132
RH		 2378
2379 if (pcrel)
2380 {
3e73aa7c 2381 if (!sign)
3956db08 2382 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2383 switch (size)
2384 {
2385 case 1: return BFD_RELOC_8_PCREL;
2386 case 2: return BFD_RELOC_16_PCREL;
2387 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2388 case 8: return BFD_RELOC_64_PCREL;
252b5132 2389 }
3956db08 2390 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2391 }
2392 else
2393 {
3956db08 2394 if (sign > 0)
e5cb08ac 2395 switch (size)
3e73aa7c
JH		 2396 {
2397 case 4: return BFD_RELOC_X86_64_32S;
2398 }
2399 else
2400 switch (size)
2401 {
2402 case 1: return BFD_RELOC_8;
2403 case 2: return BFD_RELOC_16;
2404 case 4: return BFD_RELOC_32;
2405 case 8: return BFD_RELOC_64;
2406 }
3956db08
JB		 2407 as_bad (_("cannot do %s %u byte relocation"),
2408 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2409 }
2410
0cc9e1d3 2411 return NO_RELOC;
252b5132
RH		 2412}
2413
47926f60
KH		 2414/* Here we decide which fixups can be adjusted to make them relative to
2415 the beginning of the section instead of the symbol. Basically we need
2416 to make sure that the dynamic relocations are done correctly, so in
2417 some cases we force the original symbol to be used. */
2418
252b5132 2419int
e3bb37b5 2420tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2421{
6d249963 2422#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2423 if (!IS_ELF)
31312f95
AM		 2424 return 1;
2425
a161fe53
AM		 2426 /* Don't adjust pc-relative references to merge sections in 64-bit
2427 mode. */
2428 if (use_rela_relocations
2429 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2430 && fixP->fx_pcrel)
252b5132 2431 return 0;
31312f95 2432
8d01d9a9
AJ		 2433 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2434 and changed later by validate_fix. */
2435 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2436 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2437 return 0;
2438
ce8a8b2f 2439 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2440 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2441 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2442 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2443 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2444 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2445 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2446 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2447 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2448 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2449 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2450 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2451 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2452 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2453 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2454 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2455 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2456 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2457 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2458 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2459 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2460 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2461 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2462 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2463 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2464 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2465 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2466 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2467 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2468 return 0;
d8045f23
NC		 2469
2470 if (fixP->fx_addsy != NULL
2471 && symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_GNU_INDIRECT_FUNCTION)
2472 return 0;
31312f95 2473#endif
252b5132
RH		 2474 return 1;
2475}
252b5132 2476
b4cac588 2477static int
e3bb37b5 2478intel_float_operand (const char *mnemonic)
252b5132 2479{
9306ca4a
JB		 2480 /* Note that the value returned is meaningful only for opcodes with (memory)
2481 operands, hence the code here is free to improperly handle opcodes that
2482 have no operands (for better performance and smaller code). */
2483
2484 if (mnemonic[0] != 'f')
2485 return 0; /* non-math */
2486
2487 switch (mnemonic[1])
2488 {
2489 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2490 the fs segment override prefix not currently handled because no
2491 call path can make opcodes without operands get here */
2492 case 'i':
2493 return 2 /* integer op */;
2494 case 'l':
2495 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2496 return 3; /* fldcw/fldenv */
2497 break;
2498 case 'n':
2499 if (mnemonic[2] != 'o' /* fnop */)
2500 return 3; /* non-waiting control op */
2501 break;
2502 case 'r':
2503 if (mnemonic[2] == 's')
2504 return 3; /* frstor/frstpm */
2505 break;
2506 case 's':
2507 if (mnemonic[2] == 'a')
2508 return 3; /* fsave */
2509 if (mnemonic[2] == 't')
2510 {
2511 switch (mnemonic[3])
2512 {
2513 case 'c': /* fstcw */
2514 case 'd': /* fstdw */
2515 case 'e': /* fstenv */
2516 case 's': /* fsts[gw] */
2517 return 3;
2518 }
2519 }
2520 break;
2521 case 'x':
2522 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2523 return 0; /* fxsave/fxrstor are not really math ops */
2524 break;
2525 }
252b5132 2526
9306ca4a 2527 return 1;
252b5132
RH		 2528}
2529
c0f3af97
L		 2530/* Build the VEX prefix. */
2531
2532static void
fa99fab2 2533build_vex_prefix (const template *t)
c0f3af97
L		 2534{
2535 unsigned int register_specifier;
2536 unsigned int implied_prefix;
2537 unsigned int vector_length;
2538
2539 /* Check register specifier. */
2540 if (i.vex.register_specifier)
2541 {
2542 register_specifier = i.vex.register_specifier->reg_num;
2543 if ((i.vex.register_specifier->reg_flags & RegRex))
2544 register_specifier += 8;
2545 register_specifier = ~register_specifier & 0xf;
2546 }
2547 else
2548 register_specifier = 0xf;
2549
fa99fab2
L		 2550 /* Use 2-byte VEX prefix by swappping destination and source
2551 operand. */
2552 if (!i.swap_operand
2553 && i.operands == i.reg_operands
2554 && i.tm.opcode_modifier.vex0f
2555 && i.tm.opcode_modifier.s
2556 && i.rex == REX_B)
2557 {
2558 unsigned int xchg = i.operands - 1;
2559 union i386_op temp_op;
2560 i386_operand_type temp_type;
2561
2562 temp_type = i.types[xchg];
2563 i.types[xchg] = i.types[0];
2564 i.types[0] = temp_type;
2565 temp_op = i.op[xchg];
2566 i.op[xchg] = i.op[0];
2567 i.op[0] = temp_op;
2568
9c2799c2 2569 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2570
2571 i.rex = REX_R;
2572 xchg = i.rm.regmem;
2573 i.rm.regmem = i.rm.reg;
2574 i.rm.reg = xchg;
2575
2576 /* Use the next insn. */
2577 i.tm = t[1];
2578 }
2579
c0f3af97
L		 2580 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2581
2582 switch ((i.tm.base_opcode >> 8) & 0xff)
2583 {
2584 case 0:
2585 implied_prefix = 0;
2586 break;
2587 case DATA_PREFIX_OPCODE:
2588 implied_prefix = 1;
2589 break;
2590 case REPE_PREFIX_OPCODE:
2591 implied_prefix = 2;
2592 break;
2593 case REPNE_PREFIX_OPCODE:
2594 implied_prefix = 3;
2595 break;
2596 default:
2597 abort ();
2598 }
2599
2600 /* Use 2-byte VEX prefix if possible. */
2601 if (i.tm.opcode_modifier.vex0f
2602 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2603 {
2604 /* 2-byte VEX prefix. */
2605 unsigned int r;
2606
2607 i.vex.length = 2;
2608 i.vex.bytes[0] = 0xc5;
2609
2610 /* Check the REX.R bit. */
2611 r = (i.rex & REX_R) ? 0 : 1;
2612 i.vex.bytes[1] = (r << 7
2613 | register_specifier << 3
2614 | vector_length << 2
2615 | implied_prefix);
2616 }
2617 else
2618 {
2619 /* 3-byte VEX prefix. */
2620 unsigned int m, w;
2621
2622 if (i.tm.opcode_modifier.vex0f)
2623 m = 0x1;
2624 else if (i.tm.opcode_modifier.vex0f38)
2625 m = 0x2;
2626 else if (i.tm.opcode_modifier.vex0f3a)
2627 m = 0x3;
2628 else
2629 abort ();
2630
2631 i.vex.length = 3;
2632 i.vex.bytes[0] = 0xc4;
2633
2634 /* The high 3 bits of the second VEX byte are 1's compliment
2635 of RXB bits from REX. */
2636 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2637
2638 /* Check the REX.W bit. */
2639 w = (i.rex & REX_W) ? 1 : 0;
2640 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2641 {
2642 if (w)
2643 abort ();
2644
2645 if (i.tm.opcode_modifier.vexw1)
2646 w = 1;
2647 }
2648
2649 i.vex.bytes[2] = (w << 7
2650 | register_specifier << 3
2651 | vector_length << 2
2652 | implied_prefix);
2653 }
2654}
2655
65da13b5
L		 2656static void
2657process_immext (void)
2658{
2659 expressionS *exp;
2660
2661 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2662 {
1fed0ba1
L		 2663 /* SSE3 Instructions have the fixed operands with an opcode
2664 suffix which is coded in the same place as an 8-bit immediate
2665 field would be. Here we check those operands and remove them
2666 afterwards. */
65da13b5
L		 2667 unsigned int x;
2668
2669 for (x = 0; x < i.operands; x++)
2670 if (i.op[x].regs->reg_num != x)
2671 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2672 register_prefix, i.op[x].regs->reg_name, x + 1,
2673 i.tm.name);
2674
2675 i.operands = 0;
65da13b5
L		 2676 }
2677
c0f3af97 2678 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2679 which is coded in the same place as an 8-bit immediate field
2680 would be. Here we fake an 8-bit immediate operand from the
2681 opcode suffix stored in tm.extension_opcode.
2682
c1e679ec 2683 AVX instructions also use this encoding, for some of
c0f3af97 2684 3 argument instructions. */
65da13b5 2685
9c2799c2 2686 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2687 && (i.operands <= 2
2688 || (i.tm.opcode_modifier.vex
2689 && i.operands <= 4)));
65da13b5
L		 2690
2691 exp = &im_expressions[i.imm_operands++];
2692 i.op[i.operands].imms = exp;
2693 i.types[i.operands] = imm8;
2694 i.operands++;
2695 exp->X_op = O_constant;
2696 exp->X_add_number = i.tm.extension_opcode;
2697 i.tm.extension_opcode = None;
2698}
2699
252b5132
RH		 2700/* This is the guts of the machine-dependent assembler. LINE points to a
2701 machine dependent instruction. This function is supposed to emit
2702 the frags/bytes it assembles to. */
2703
2704void
65da13b5 2705md_assemble (char *line)
252b5132 2706{
40fb9820 2707 unsigned int j;
252b5132 2708 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2709 const template *t;
252b5132 2710
47926f60 2711 /* Initialize globals. */
252b5132
RH		 2712 memset (&i, '\0', sizeof (i));
2713 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2714 i.reloc[j] = NO_RELOC;
252b5132
RH		 2715 memset (disp_expressions, '\0', sizeof (disp_expressions));
2716 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2717 save_stack_p = save_stack;
252b5132
RH		 2718
2719 /* First parse an instruction mnemonic & call i386_operand for the operands.
2720 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2721 start of a (possibly prefixed) mnemonic. */
252b5132 2722
29b0f896
AM		 2723 line = parse_insn (line, mnemonic);
2724 if (line == NULL)
2725 return;
252b5132 2726
29b0f896 2727 line = parse_operands (line, mnemonic);
ee86248c 2728 this_operand = -1;
29b0f896
AM		 2729 if (line == NULL)
2730 return;
252b5132 2731
29b0f896
AM		 2732 /* Now we've parsed the mnemonic into a set of templates, and have the
2733 operands at hand. */
2734
2735 /* All intel opcodes have reversed operands except for "bound" and
2736 "enter". We also don't reverse intersegment "jmp" and "call"
2737 instructions with 2 immediate operands so that the immediate segment
050dfa73 2738 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2739 if (intel_syntax
2740 && i.operands > 1
29b0f896 2741 && (strcmp (mnemonic, "bound") != 0)
30123838 2742 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2743 && !(operand_type_check (i.types[0], imm)
2744 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2745 swap_operands ();
2746
ec56d5c0
JB		 2747 /* The order of the immediates should be reversed
2748 for 2 immediates extrq and insertq instructions */
2749 if (i.imm_operands == 2
2750 && (strcmp (mnemonic, "extrq") == 0
2751 || strcmp (mnemonic, "insertq") == 0))
2752 swap_2_operands (0, 1);
2753
29b0f896
AM		 2754 if (i.imm_operands)
2755 optimize_imm ();
2756
b300c311
L		 2757 /* Don't optimize displacement for movabs since it only takes 64bit
2758 displacement. */
2759 if (i.disp_operands
2760 && (flag_code != CODE_64BIT
2761 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2762 optimize_disp ();
2763
2764 /* Next, we find a template that matches the given insn,
2765 making sure the overlap of the given operands types is consistent
2766 with the template operand types. */
252b5132 2767
fa99fab2 2768 if (!(t = match_template ()))
29b0f896 2769 return;
252b5132 2770
daf50ae7 2771 if (sse_check != sse_check_none
81f8a913 2772 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2773 && (i.tm.cpu_flags.bitfield.cpusse
2774 || i.tm.cpu_flags.bitfield.cpusse2
2775 || i.tm.cpu_flags.bitfield.cpusse3
2776 || i.tm.cpu_flags.bitfield.cpussse3
2777 || i.tm.cpu_flags.bitfield.cpusse4_1
2778 || i.tm.cpu_flags.bitfield.cpusse4_2))
2779 {
2780 (sse_check == sse_check_warning
2781 ? as_warn
2782 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2783 }
2784
321fd21e
L		 2785 /* Zap movzx and movsx suffix. The suffix has been set from
2786 "word ptr" or "byte ptr" on the source operand in Intel syntax
2787 or extracted from mnemonic in AT&T syntax. But we'll use
2788 the destination register to choose the suffix for encoding. */
2789 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2790 {
321fd21e
L		 2791 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2792 there is no suffix, the default will be byte extension. */
2793 if (i.reg_operands != 2
2794 && !i.suffix
7ab9ffdd 2795 && intel_syntax)
321fd21e
L		 2796 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2797
2798 i.suffix = 0;
cd61ebfe 2799 }
24eab124 2800
40fb9820 2801 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2802 if (!add_prefix (FWAIT_OPCODE))
2803 return;
252b5132 2804
29b0f896 2805 /* Check string instruction segment overrides. */
40fb9820 2806 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2807 {
2808 if (!check_string ())
5dd0794d 2809 return;
fc0763e6 2810 i.disp_operands = 0;
29b0f896 2811 }
5dd0794d 2812
29b0f896
AM		 2813 if (!process_suffix ())
2814 return;
e413e4e9 2815
bc0844ae
L		 2816 /* Update operand types. */
2817 for (j = 0; j < i.operands; j++)
2818 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2819
29b0f896
AM		 2820 /* Make still unresolved immediate matches conform to size of immediate
2821 given in i.suffix. */
2822 if (!finalize_imm ())
2823 return;
252b5132 2824
40fb9820 2825 if (i.types[0].bitfield.imm1)
29b0f896 2826 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2827
9afe6eb8
L		 2828 /* We only need to check those implicit registers for instructions
2829 with 3 operands or less. */
2830 if (i.operands <= 3)
2831 for (j = 0; j < i.operands; j++)
2832 if (i.types[j].bitfield.inoutportreg
2833 || i.types[j].bitfield.shiftcount
2834 || i.types[j].bitfield.acc
2835 || i.types[j].bitfield.floatacc)
2836 i.reg_operands--;
40fb9820 2837
c0f3af97
L		 2838 /* ImmExt should be processed after SSE2AVX. */
2839 if (!i.tm.opcode_modifier.sse2avx
2840 && i.tm.opcode_modifier.immext)
65da13b5 2841 process_immext ();
252b5132 2842
29b0f896
AM		 2843 /* For insns with operands there are more diddles to do to the opcode. */
2844 if (i.operands)
2845 {
2846 if (!process_operands ())
2847 return;
2848 }
40fb9820 2849 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2850 {
2851 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2852 as_warn (_("translating to `%sp'"), i.tm.name);
2853 }
252b5132 2854
c0f3af97 2855 if (i.tm.opcode_modifier.vex)
fa99fab2 2856 build_vex_prefix (t);
c0f3af97 2857
29b0f896
AM		 2858 /* Handle conversion of 'int $3' --> special int3 insn. */
2859 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2860 {
2861 i.tm.base_opcode = INT3_OPCODE;
2862 i.imm_operands = 0;
2863 }
252b5132 2864
40fb9820
L		 2865 if ((i.tm.opcode_modifier.jump
2866 || i.tm.opcode_modifier.jumpbyte
2867 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2868 && i.op[0].disps->X_op == O_constant)
2869 {
2870 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2871 the absolute address given by the constant. Since ix86 jumps and
2872 calls are pc relative, we need to generate a reloc. */
2873 i.op[0].disps->X_add_symbol = &abs_symbol;
2874 i.op[0].disps->X_op = O_symbol;
2875 }
252b5132 2876
40fb9820 2877 if (i.tm.opcode_modifier.rex64)
161a04f6 2878 i.rex |= REX_W;
252b5132 2879
29b0f896
AM		 2880 /* For 8 bit registers we need an empty rex prefix. Also if the
2881 instruction already has a prefix, we need to convert old
2882 registers to new ones. */
773f551c 2883
40fb9820 2884 if ((i.types[0].bitfield.reg8
29b0f896 2885 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2886 || (i.types[1].bitfield.reg8
29b0f896 2887 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2888 || ((i.types[0].bitfield.reg8
2889 || i.types[1].bitfield.reg8)
29b0f896
AM		 2890 && i.rex != 0))
2891 {
2892 int x;
726c5dcd 2893
29b0f896
AM		 2894 i.rex |= REX_OPCODE;
2895 for (x = 0; x < 2; x++)
2896 {
2897 /* Look for 8 bit operand that uses old registers. */
40fb9820 2898 if (i.types[x].bitfield.reg8
29b0f896 2899 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2900 {
29b0f896
AM		 2901 /* In case it is "hi" register, give up. */
2902 if (i.op[x].regs->reg_num > 3)
a540244d 2903 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2904 "instruction requiring REX prefix."),
a540244d 2905 register_prefix, i.op[x].regs->reg_name);
773f551c 2906
29b0f896
AM		 2907 /* Otherwise it is equivalent to the extended register.
2908 Since the encoding doesn't change this is merely
2909 cosmetic cleanup for debug output. */
2910
2911 i.op[x].regs = i.op[x].regs + 8;
773f551c 2912 }
29b0f896
AM		 2913 }
2914 }
773f551c 2915
7ab9ffdd 2916 if (i.rex != 0)
29b0f896
AM		 2917 add_prefix (REX_OPCODE | i.rex);
2918
2919 /* We are ready to output the insn. */
2920 output_insn ();
2921}
2922
2923static char *
e3bb37b5 2924parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2925{
2926 char *l = line;
2927 char *token_start = l;
2928 char *mnem_p;
5c6af06e
JB		 2929 int supported;
2930 const template *t;
b6169b20 2931 char *dot_p = NULL;
29b0f896
AM		 2932
2933 /* Non-zero if we found a prefix only acceptable with string insns. */
2934 const char *expecting_string_instruction = NULL;
45288df1 2935
29b0f896
AM		 2936 while (1)
2937 {
2938 mnem_p = mnemonic;
2939 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2940 {
b6169b20
L		 2941 if (*mnem_p == '.')
2942 dot_p = mnem_p;
29b0f896
AM		 2943 mnem_p++;
2944 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2945 {
29b0f896
AM		 2946 as_bad (_("no such instruction: `%s'"), token_start);
2947 return NULL;
2948 }
2949 l++;
2950 }
2951 if (!is_space_char (*l)
2952 && *l != END_OF_INSN
e44823cf
JB		 2953 && (intel_syntax
2954 || (*l != PREFIX_SEPARATOR
2955 && *l != ',')))
29b0f896
AM		 2956 {
2957 as_bad (_("invalid character %s in mnemonic"),
2958 output_invalid (*l));
2959 return NULL;
2960 }
2961 if (token_start == l)
2962 {
e44823cf 2963 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2964 as_bad (_("expecting prefix; got nothing"));
2965 else
2966 as_bad (_("expecting mnemonic; got nothing"));
2967 return NULL;
2968 }
45288df1 2969
29b0f896
AM		 2970 /* Look up instruction (or prefix) via hash table. */
2971 current_templates = hash_find (op_hash, mnemonic);
47926f60 2972
29b0f896
AM		 2973 if (*l != END_OF_INSN
2974 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2975 && current_templates
40fb9820 2976 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2977 {
c6fb90c8 2978 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2979 {
2980 as_bad ((flag_code != CODE_64BIT
2981 ? _("`%s' is only supported in 64-bit mode")
2982 : _("`%s' is not supported in 64-bit mode")),
2983 current_templates->start->name);
2984 return NULL;
2985 }
29b0f896
AM		 2986 /* If we are in 16-bit mode, do not allow addr16 or data16.
2987 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2988 if ((current_templates->start->opcode_modifier.size16
2989 || current_templates->start->opcode_modifier.size32)
29b0f896 2990 && flag_code != CODE_64BIT
40fb9820 2991 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2992 ^ (flag_code == CODE_16BIT)))
2993 {
2994 as_bad (_("redundant %s prefix"),
2995 current_templates->start->name);
2996 return NULL;
45288df1 2997 }
29b0f896
AM		 2998 /* Add prefix, checking for repeated prefixes. */
2999 switch (add_prefix (current_templates->start->base_opcode))
3000 {
3001 case 0:
3002 return NULL;
3003 case 2:
3004 expecting_string_instruction = current_templates->start->name;
3005 break;
3006 }
3007 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3008 token_start = ++l;
3009 }
3010 else
3011 break;
3012 }
45288df1 3013
30a55f88 3014 if (!current_templates)
b6169b20 3015 {
30a55f88
L		 3016 /* Check if we should swap operand in encoding. */
3017 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3018 i.swap_operand = 1;
3019 else
3020 goto check_suffix;
3021 mnem_p = dot_p;
3022 *dot_p = '\0';
3023 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L		 3024 }
3025
29b0f896
AM		 3026 if (!current_templates)
3027 {
b6169b20 3028check_suffix:
29b0f896
AM		 3029 /* See if we can get a match by trimming off a suffix. */
3030 switch (mnem_p[-1])
3031 {
3032 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3033 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3034 i.suffix = SHORT_MNEM_SUFFIX;
3035 else
29b0f896
AM		 3036 case BYTE_MNEM_SUFFIX:
3037 case QWORD_MNEM_SUFFIX:
3038 i.suffix = mnem_p[-1];
3039 mnem_p[-1] = '\0';
3040 current_templates = hash_find (op_hash, mnemonic);
3041 break;
3042 case SHORT_MNEM_SUFFIX:
3043 case LONG_MNEM_SUFFIX:
3044 if (!intel_syntax)
3045 {
3046 i.suffix = mnem_p[-1];
3047 mnem_p[-1] = '\0';
3048 current_templates = hash_find (op_hash, mnemonic);
3049 }
3050 break;
252b5132 3051
29b0f896
AM		 3052 /* Intel Syntax. */
3053 case 'd':
3054 if (intel_syntax)
3055 {
9306ca4a 3056 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3057 i.suffix = SHORT_MNEM_SUFFIX;
3058 else
3059 i.suffix = LONG_MNEM_SUFFIX;
3060 mnem_p[-1] = '\0';
3061 current_templates = hash_find (op_hash, mnemonic);
3062 }
3063 break;
3064 }
3065 if (!current_templates)
3066 {
3067 as_bad (_("no such instruction: `%s'"), token_start);
3068 return NULL;
3069 }
3070 }
252b5132 3071
40fb9820
L		 3072 if (current_templates->start->opcode_modifier.jump
3073 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3074 {
3075 /* Check for a branch hint. We allow ",pt" and ",pn" for
3076 predict taken and predict not taken respectively.
3077 I'm not sure that branch hints actually do anything on loop
3078 and jcxz insns (JumpByte) for current Pentium4 chips. They
3079 may work in the future and it doesn't hurt to accept them
3080 now. */
3081 if (l[0] == ',' && l[1] == 'p')
3082 {
3083 if (l[2] == 't')
3084 {
3085 if (!add_prefix (DS_PREFIX_OPCODE))
3086 return NULL;
3087 l += 3;
3088 }
3089 else if (l[2] == 'n')
3090 {
3091 if (!add_prefix (CS_PREFIX_OPCODE))
3092 return NULL;
3093 l += 3;
3094 }
3095 }
3096 }
3097 /* Any other comma loses. */
3098 if (*l == ',')
3099 {
3100 as_bad (_("invalid character %s in mnemonic"),
3101 output_invalid (*l));
3102 return NULL;
3103 }
252b5132 3104
29b0f896 3105 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3106 supported = 0;
3107 for (t = current_templates->start; t < current_templates->end; ++t)
3108 {
c0f3af97
L		 3109 supported |= cpu_flags_match (t);
3110 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3111 goto skip;
5c6af06e 3112 }
3629bb00 3113
c0f3af97 3114 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3115 {
3116 as_bad (flag_code == CODE_64BIT
3117 ? _("`%s' is not supported in 64-bit mode")
3118 : _("`%s' is only supported in 64-bit mode"),
3119 current_templates->start->name);
3120 return NULL;
3121 }
c0f3af97 3122 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3123 {
3629bb00 3124 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3125 current_templates->start->name,
41aacd83 3126 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3127 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3128 return NULL;
29b0f896 3129 }
3629bb00
L		 3130
3131skip:
3132 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3133 && (flag_code != CODE_16BIT))
29b0f896
AM		 3134 {
3135 as_warn (_("use .code16 to ensure correct addressing mode"));
3136 }
252b5132 3137
29b0f896 3138 /* Check for rep/repne without a string instruction. */
f41bbced 3139 if (expecting_string_instruction)
29b0f896 3140 {
f41bbced
JB		 3141 static templates override;
3142
3143 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3144 if (t->opcode_modifier.isstring)
f41bbced
JB		 3145 break;
3146 if (t >= current_templates->end)
3147 {
3148 as_bad (_("expecting string instruction after `%s'"),
64e74474 3149 expecting_string_instruction);
f41bbced
JB		 3150 return NULL;
3151 }
3152 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3153 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3154 break;
3155 override.end = t;
3156 current_templates = &override;
29b0f896 3157 }
252b5132 3158
29b0f896
AM		 3159 return l;
3160}
252b5132 3161
29b0f896 3162static char *
e3bb37b5 3163parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3164{
3165 char *token_start;
3138f287 3166
29b0f896
AM		 3167 /* 1 if operand is pending after ','. */
3168 unsigned int expecting_operand = 0;
252b5132 3169
29b0f896
AM		 3170 /* Non-zero if operand parens not balanced. */
3171 unsigned int paren_not_balanced;
3172
3173 while (*l != END_OF_INSN)
3174 {
3175 /* Skip optional white space before operand. */
3176 if (is_space_char (*l))
3177 ++l;
3178 if (!is_operand_char (*l) && *l != END_OF_INSN)
3179 {
3180 as_bad (_("invalid character %s before operand %d"),
3181 output_invalid (*l),
3182 i.operands + 1);
3183 return NULL;
3184 }
3185 token_start = l; /* after white space */
3186 paren_not_balanced = 0;
3187 while (paren_not_balanced || *l != ',')
3188 {
3189 if (*l == END_OF_INSN)
3190 {
3191 if (paren_not_balanced)
3192 {
3193 if (!intel_syntax)
3194 as_bad (_("unbalanced parenthesis in operand %d."),
3195 i.operands + 1);
3196 else
3197 as_bad (_("unbalanced brackets in operand %d."),
3198 i.operands + 1);
3199 return NULL;
3200 }
3201 else
3202 break; /* we are done */
3203 }
3204 else if (!is_operand_char (*l) && !is_space_char (*l))
3205 {
3206 as_bad (_("invalid character %s in operand %d"),
3207 output_invalid (*l),
3208 i.operands + 1);
3209 return NULL;
3210 }
3211 if (!intel_syntax)
3212 {
3213 if (*l == '(')
3214 ++paren_not_balanced;
3215 if (*l == ')')
3216 --paren_not_balanced;
3217 }
3218 else
3219 {
3220 if (*l == '[')
3221 ++paren_not_balanced;
3222 if (*l == ']')
3223 --paren_not_balanced;
3224 }
3225 l++;
3226 }
3227 if (l != token_start)
3228 { /* Yes, we've read in another operand. */
3229 unsigned int operand_ok;
3230 this_operand = i.operands++;
7d5e4556 3231 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3232 if (i.operands > MAX_OPERANDS)
3233 {
3234 as_bad (_("spurious operands; (%d operands/instruction max)"),
3235 MAX_OPERANDS);
3236 return NULL;
3237 }
3238 /* Now parse operand adding info to 'i' as we go along. */
3239 END_STRING_AND_SAVE (l);
3240
3241 if (intel_syntax)
3242 operand_ok =
3243 i386_intel_operand (token_start,
3244 intel_float_operand (mnemonic));
3245 else
a7619375 3246 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3247
3248 RESTORE_END_STRING (l);
3249 if (!operand_ok)
3250 return NULL;
3251 }
3252 else
3253 {
3254 if (expecting_operand)
3255 {
3256 expecting_operand_after_comma:
3257 as_bad (_("expecting operand after ','; got nothing"));
3258 return NULL;
3259 }
3260 if (*l == ',')
3261 {
3262 as_bad (_("expecting operand before ','; got nothing"));
3263 return NULL;
3264 }
3265 }
7f3f1ea2 3266
29b0f896
AM		 3267 /* Now *l must be either ',' or END_OF_INSN. */
3268 if (*l == ',')
3269 {
3270 if (*++l == END_OF_INSN)
3271 {
3272 /* Just skip it, if it's \n complain. */
3273 goto expecting_operand_after_comma;
3274 }
3275 expecting_operand = 1;
3276 }
3277 }
3278 return l;
3279}
7f3f1ea2 3280
050dfa73 3281static void
4d456e3d 3282swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3283{
3284 union i386_op temp_op;
40fb9820 3285 i386_operand_type temp_type;
050dfa73 3286 enum bfd_reloc_code_real temp_reloc;
4eed87de 3287
050dfa73
MM		 3288 temp_type = i.types[xchg2];
3289 i.types[xchg2] = i.types[xchg1];
3290 i.types[xchg1] = temp_type;
3291 temp_op = i.op[xchg2];
3292 i.op[xchg2] = i.op[xchg1];
3293 i.op[xchg1] = temp_op;
3294 temp_reloc = i.reloc[xchg2];
3295 i.reloc[xchg2] = i.reloc[xchg1];
3296 i.reloc[xchg1] = temp_reloc;
3297}
3298
29b0f896 3299static void
e3bb37b5 3300swap_operands (void)
29b0f896 3301{
b7c61d9a 3302 switch (i.operands)
050dfa73 3303 {
c0f3af97 3304 case 5:
b7c61d9a 3305 case 4:
4d456e3d 3306 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3307 case 3:
3308 case 2:
4d456e3d 3309 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3310 break;
3311 default:
3312 abort ();
29b0f896 3313 }
29b0f896
AM		 3314
3315 if (i.mem_operands == 2)
3316 {
3317 const seg_entry *temp_seg;
3318 temp_seg = i.seg[0];
3319 i.seg[0] = i.seg[1];
3320 i.seg[1] = temp_seg;
3321 }
3322}
252b5132 3323
29b0f896
AM		 3324/* Try to ensure constant immediates are represented in the smallest
3325 opcode possible. */
3326static void
e3bb37b5 3327optimize_imm (void)
29b0f896
AM		 3328{
3329 char guess_suffix = 0;
3330 int op;
252b5132 3331
29b0f896
AM		 3332 if (i.suffix)
3333 guess_suffix = i.suffix;
3334 else if (i.reg_operands)
3335 {
3336 /* Figure out a suffix from the last register operand specified.
3337 We can't do this properly yet, ie. excluding InOutPortReg,
3338 but the following works for instructions with immediates.
3339 In any case, we can't set i.suffix yet. */
3340 for (op = i.operands; --op >= 0;)
40fb9820 3341 if (i.types[op].bitfield.reg8)
7ab9ffdd 3342 {
40fb9820
L		 3343 guess_suffix = BYTE_MNEM_SUFFIX;
3344 break;
3345 }
3346 else if (i.types[op].bitfield.reg16)
252b5132 3347 {
40fb9820
L		 3348 guess_suffix = WORD_MNEM_SUFFIX;
3349 break;
3350 }
3351 else if (i.types[op].bitfield.reg32)
3352 {
3353 guess_suffix = LONG_MNEM_SUFFIX;
3354 break;
3355 }
3356 else if (i.types[op].bitfield.reg64)
3357 {
3358 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3359 break;
252b5132 3360 }
29b0f896
AM		 3361 }
3362 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3363 guess_suffix = WORD_MNEM_SUFFIX;
3364
3365 for (op = i.operands; --op >= 0;)
40fb9820 3366 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3367 {
3368 switch (i.op[op].imms->X_op)
252b5132 3369 {
29b0f896
AM		 3370 case O_constant:
3371 /* If a suffix is given, this operand may be shortened. */
3372 switch (guess_suffix)
252b5132 3373 {
29b0f896 3374 case LONG_MNEM_SUFFIX:
40fb9820
L		 3375 i.types[op].bitfield.imm32 = 1;
3376 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3377 break;
3378 case WORD_MNEM_SUFFIX:
40fb9820
L		 3379 i.types[op].bitfield.imm16 = 1;
3380 i.types[op].bitfield.imm32 = 1;
3381 i.types[op].bitfield.imm32s = 1;
3382 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3383 break;
3384 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3385 i.types[op].bitfield.imm8 = 1;
3386 i.types[op].bitfield.imm8s = 1;
3387 i.types[op].bitfield.imm16 = 1;
3388 i.types[op].bitfield.imm32 = 1;
3389 i.types[op].bitfield.imm32s = 1;
3390 i.types[op].bitfield.imm64 = 1;
29b0f896 3391 break;
252b5132 3392 }
252b5132 3393
29b0f896
AM		 3394 /* If this operand is at most 16 bits, convert it
3395 to a signed 16 bit number before trying to see
3396 whether it will fit in an even smaller size.
3397 This allows a 16-bit operand such as $0xffe0 to
3398 be recognised as within Imm8S range. */
40fb9820 3399 if ((i.types[op].bitfield.imm16)
29b0f896 3400 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3401 {
29b0f896
AM		 3402 i.op[op].imms->X_add_number =
3403 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3404 }
40fb9820 3405 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3406 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3407 == 0))
3408 {
3409 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3410 ^ ((offsetT) 1 << 31))
3411 - ((offsetT) 1 << 31));
3412 }
40fb9820 3413 i.types[op]
c6fb90c8
L		 3414 = operand_type_or (i.types[op],
3415 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3416
29b0f896
AM		 3417 /* We must avoid matching of Imm32 templates when 64bit
3418 only immediate is available. */
3419 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3420 i.types[op].bitfield.imm32 = 0;
29b0f896 3421 break;
252b5132 3422
29b0f896
AM		 3423 case O_absent:
3424 case O_register:
3425 abort ();
3426
3427 /* Symbols and expressions. */
3428 default:
9cd96992
JB		 3429 /* Convert symbolic operand to proper sizes for matching, but don't
3430 prevent matching a set of insns that only supports sizes other
3431 than those matching the insn suffix. */
3432 {
40fb9820 3433 i386_operand_type mask, allowed;
9cd96992
JB		 3434 const template *t;
3435
0dfbf9d7
L		 3436 operand_type_set (&mask, 0);
3437 operand_type_set (&allowed, 0);
40fb9820 3438
4eed87de
AM		 3439 for (t = current_templates->start;
3440 t < current_templates->end;
3441 ++t)
c6fb90c8
L		 3442 allowed = operand_type_or (allowed,
3443 t->operand_types[op]);
9cd96992
JB		 3444 switch (guess_suffix)
3445 {
3446 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3447 mask.bitfield.imm64 = 1;
3448 mask.bitfield.imm32s = 1;
9cd96992
JB		 3449 break;
3450 case LONG_MNEM_SUFFIX:
40fb9820 3451 mask.bitfield.imm32 = 1;
9cd96992
JB		 3452 break;
3453 case WORD_MNEM_SUFFIX:
40fb9820 3454 mask.bitfield.imm16 = 1;
9cd96992
JB		 3455 break;
3456 case BYTE_MNEM_SUFFIX:
40fb9820 3457 mask.bitfield.imm8 = 1;
9cd96992
JB		 3458 break;
3459 default:
9cd96992
JB		 3460 break;
3461 }
c6fb90c8 3462 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3463 if (!operand_type_all_zero (&allowed))
c6fb90c8 3464 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3465 }
29b0f896 3466 break;
252b5132 3467 }
29b0f896
AM		 3468 }
3469}
47926f60 3470
29b0f896
AM		 3471/* Try to use the smallest displacement type too. */
3472static void
e3bb37b5 3473optimize_disp (void)
29b0f896
AM		 3474{
3475 int op;
3e73aa7c 3476
29b0f896 3477 for (op = i.operands; --op >= 0;)
40fb9820 3478 if (operand_type_check (i.types[op], disp))
252b5132 3479 {
b300c311 3480 if (i.op[op].disps->X_op == O_constant)
252b5132 3481 {
b300c311 3482 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3483
40fb9820 3484 if (i.types[op].bitfield.disp16
b300c311
L		 3485 && (disp & ~(offsetT) 0xffff) == 0)
3486 {
3487 /* If this operand is at most 16 bits, convert
3488 to a signed 16 bit number and don't use 64bit
3489 displacement. */
3490 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3491 i.types[op].bitfield.disp64 = 0;
b300c311 3492 }
40fb9820 3493 if (i.types[op].bitfield.disp32
b300c311
L		 3494 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3495 {
3496 /* If this operand is at most 32 bits, convert
3497 to a signed 32 bit number and don't use 64bit
3498 displacement. */
3499 disp &= (((offsetT) 2 << 31) - 1);
3500 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3501 i.types[op].bitfield.disp64 = 0;
b300c311 3502 }
40fb9820 3503 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3504 {
40fb9820
L		 3505 i.types[op].bitfield.disp8 = 0;
3506 i.types[op].bitfield.disp16 = 0;
3507 i.types[op].bitfield.disp32 = 0;
3508 i.types[op].bitfield.disp32s = 0;
3509 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3510 i.op[op].disps = 0;
3511 i.disp_operands--;
3512 }
3513 else if (flag_code == CODE_64BIT)
3514 {
3515 if (fits_in_signed_long (disp))
28a9d8f5 3516 {
40fb9820
L		 3517 i.types[op].bitfield.disp64 = 0;
3518 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3519 }
b300c311 3520 if (fits_in_unsigned_long (disp))
40fb9820 3521 i.types[op].bitfield.disp32 = 1;
b300c311 3522 }
40fb9820
L		 3523 if ((i.types[op].bitfield.disp32
3524 || i.types[op].bitfield.disp32s
3525 || i.types[op].bitfield.disp16)
b300c311 3526 && fits_in_signed_byte (disp))
40fb9820 3527 i.types[op].bitfield.disp8 = 1;
252b5132 3528 }
67a4f2b7
AO		 3529 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3530 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3531 {
3532 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3533 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3534 i.types[op].bitfield.disp8 = 0;
3535 i.types[op].bitfield.disp16 = 0;
3536 i.types[op].bitfield.disp32 = 0;
3537 i.types[op].bitfield.disp32s = 0;
3538 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3539 }
3540 else
b300c311 3541 /* We only support 64bit displacement on constants. */
40fb9820 3542 i.types[op].bitfield.disp64 = 0;
252b5132 3543 }
29b0f896
AM		 3544}
3545
fa99fab2 3546static const template *
e3bb37b5 3547match_template (void)
29b0f896
AM		 3548{
3549 /* Points to template once we've found it. */
3550 const template *t;
40fb9820 3551 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3552 i386_operand_type overlap4;
29b0f896 3553 unsigned int found_reverse_match;
40fb9820
L		 3554 i386_opcode_modifier suffix_check;
3555 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3556 int addr_prefix_disp;
a5c311ca 3557 unsigned int j;
3629bb00 3558 unsigned int found_cpu_match;
45664ddb 3559 unsigned int check_register;
29b0f896 3560
c0f3af97
L		 3561#if MAX_OPERANDS != 5
3562# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3563#endif
3564
29b0f896 3565 found_reverse_match = 0;
539e75ad 3566 addr_prefix_disp = -1;
40fb9820
L		 3567
3568 memset (&suffix_check, 0, sizeof (suffix_check));
3569 if (i.suffix == BYTE_MNEM_SUFFIX)
3570 suffix_check.no_bsuf = 1;
3571 else if (i.suffix == WORD_MNEM_SUFFIX)
3572 suffix_check.no_wsuf = 1;
3573 else if (i.suffix == SHORT_MNEM_SUFFIX)
3574 suffix_check.no_ssuf = 1;
3575 else if (i.suffix == LONG_MNEM_SUFFIX)
3576 suffix_check.no_lsuf = 1;
3577 else if (i.suffix == QWORD_MNEM_SUFFIX)
3578 suffix_check.no_qsuf = 1;
3579 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3580 suffix_check.no_ldsuf = 1;
29b0f896 3581
45aa61fe 3582 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3583 {
539e75ad
L		 3584 addr_prefix_disp = -1;
3585
29b0f896
AM		 3586 /* Must have right number of operands. */
3587 if (i.operands != t->operands)
3588 continue;
3589
50aecf8c 3590 /* Check processor support. */
c0f3af97
L		 3591 found_cpu_match = (cpu_flags_match (t)
3592 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3593 if (!found_cpu_match)
3594 continue;
3595
e1d4d893
L		 3596 /* Check old gcc support. */
3597 if (!old_gcc && t->opcode_modifier.oldgcc)
3598 continue;
3599
3600 /* Check AT&T mnemonic. */
3601 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3602 continue;
3603
5c07affc
L		 3604 /* Check AT&T syntax Intel syntax. */
3605 if ((intel_syntax && t->opcode_modifier.attsyntax)
3606 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3607 continue;
3608
20592a94 3609 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3610 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3611 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3612 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3613 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3614 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3615 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3616 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3617 continue;
3618
5c07affc 3619 if (!operand_size_match (t))
7d5e4556 3620 continue;
539e75ad 3621
5c07affc
L		 3622 for (j = 0; j < MAX_OPERANDS; j++)
3623 operand_types[j] = t->operand_types[j];
3624
45aa61fe
AM		 3625 /* In general, don't allow 64-bit operands in 32-bit mode. */
3626 if (i.suffix == QWORD_MNEM_SUFFIX
3627 && flag_code != CODE_64BIT
3628 && (intel_syntax
40fb9820 3629 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3630 && !intel_float_operand (t->name))
3631 : intel_float_operand (t->name) != 2)
40fb9820 3632 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3633 && !operand_types[0].bitfield.regxmm
3634 && !operand_types[0].bitfield.regymm)
40fb9820 3635 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3636 && !!operand_types[t->operands > 1].bitfield.regxmm
3637 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3638 && (t->base_opcode != 0x0fc7
3639 || t->extension_opcode != 1 /* cmpxchg8b */))
3640 continue;
3641
192dc9c6
JB		 3642 /* In general, don't allow 32-bit operands on pre-386. */
3643 else if (i.suffix == LONG_MNEM_SUFFIX
3644 && !cpu_arch_flags.bitfield.cpui386
3645 && (intel_syntax
3646 ? (!t->opcode_modifier.ignoresize
3647 && !intel_float_operand (t->name))
3648 : intel_float_operand (t->name) != 2)
3649 && ((!operand_types[0].bitfield.regmmx
3650 && !operand_types[0].bitfield.regxmm)
3651 || (!operand_types[t->operands > 1].bitfield.regmmx
3652 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3653 continue;
3654
29b0f896 3655 /* Do not verify operands when there are none. */
50aecf8c 3656 else
29b0f896 3657 {
c6fb90c8 3658 if (!t->operands)
2dbab7d5
L		 3659 /* We've found a match; break out of loop. */
3660 break;
29b0f896 3661 }
252b5132 3662
539e75ad
L		 3663 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3664 into Disp32/Disp16/Disp32 operand. */
3665 if (i.prefix[ADDR_PREFIX] != 0)
3666 {
40fb9820 3667 /* There should be only one Disp operand. */
539e75ad
L		 3668 switch (flag_code)
3669 {
3670 case CODE_16BIT:
40fb9820
L		 3671 for (j = 0; j < MAX_OPERANDS; j++)
3672 {
3673 if (operand_types[j].bitfield.disp16)
3674 {
3675 addr_prefix_disp = j;
3676 operand_types[j].bitfield.disp32 = 1;
3677 operand_types[j].bitfield.disp16 = 0;
3678 break;
3679 }
3680 }
539e75ad
L		 3681 break;
3682 case CODE_32BIT:
40fb9820
L		 3683 for (j = 0; j < MAX_OPERANDS; j++)
3684 {
3685 if (operand_types[j].bitfield.disp32)
3686 {
3687 addr_prefix_disp = j;
3688 operand_types[j].bitfield.disp32 = 0;
3689 operand_types[j].bitfield.disp16 = 1;
3690 break;
3691 }
3692 }
539e75ad
L		 3693 break;
3694 case CODE_64BIT:
40fb9820
L		 3695 for (j = 0; j < MAX_OPERANDS; j++)
3696 {
3697 if (operand_types[j].bitfield.disp64)
3698 {
3699 addr_prefix_disp = j;
3700 operand_types[j].bitfield.disp64 = 0;
3701 operand_types[j].bitfield.disp32 = 1;
3702 break;
3703 }
3704 }
539e75ad
L		 3705 break;
3706 }
539e75ad
L		 3707 }
3708
45664ddb
L		 3709 /* We check register size only if size of operands can be
3710 encoded the canonical way. */
3711 check_register = t->opcode_modifier.w;
c6fb90c8 3712 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3713 switch (t->operands)
3714 {
3715 case 1:
40fb9820 3716 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3717 continue;
3718 break;
3719 case 2:
8b38ad71
L		 3720 /* xchg %eax, %eax is a special case. It is an aliase for nop
3721 only in 32bit mode and we can use opcode 0x90. In 64bit
3722 mode, we can't use 0x90 for xchg %eax, %eax since it should
3723 zero-extend %eax to %rax. */
3724 if (flag_code == CODE_64BIT
3725 && t->base_opcode == 0x90
0dfbf9d7
L		 3726 && operand_type_equal (&i.types [0], &acc32)
3727 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3728 continue;
b6169b20
L		 3729 if (i.swap_operand)
3730 {
3731 /* If we swap operand in encoding, we either match
3732 the next one or reverse direction of operands. */
3733 if (t->opcode_modifier.s)
3734 continue;
3735 else if (t->opcode_modifier.d)
3736 goto check_reverse;
3737 }
3738
29b0f896 3739 case 3:
fa99fab2
L		 3740 /* If we swap operand in encoding, we match the next one. */
3741 if (i.swap_operand && t->opcode_modifier.s)
3742 continue;
f48ff2ae 3743 case 4:
c0f3af97 3744 case 5:
c6fb90c8 3745 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3746 if (!operand_type_match (overlap0, i.types[0])
3747 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3748 || (check_register
3749 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3750 operand_types[0],
3751 overlap1, i.types[1],
3752 operand_types[1])))
29b0f896
AM		 3753 {
3754 /* Check if other direction is valid ... */
40fb9820 3755 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3756 continue;
3757
b6169b20 3758check_reverse:
29b0f896 3759 /* Try reversing direction of operands. */
c6fb90c8
L		 3760 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3761 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3762 if (!operand_type_match (overlap0, i.types[0])
3763 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3764 || (check_register
3765 && !operand_type_register_match (overlap0,
3766 i.types[0],
3767 operand_types[1],
3768 overlap1,
3769 i.types[1],
3770 operand_types[0])))
29b0f896
AM		 3771 {
3772 /* Does not match either direction. */
3773 continue;
3774 }
3775 /* found_reverse_match holds which of D or FloatDR
3776 we've found. */
40fb9820 3777 if (t->opcode_modifier.d)
8a2ed489 3778 found_reverse_match = Opcode_D;
40fb9820 3779 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3780 found_reverse_match = Opcode_FloatD;
3781 else
3782 found_reverse_match = 0;
40fb9820 3783 if (t->opcode_modifier.floatr)
8a2ed489 3784 found_reverse_match |= Opcode_FloatR;
29b0f896 3785 }
f48ff2ae 3786 else
29b0f896 3787 {
f48ff2ae 3788 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3789 switch (t->operands)
3790 {
c0f3af97
L		 3791 case 5:
3792 overlap4 = operand_type_and (i.types[4],
3793 operand_types[4]);
d1cbb4db 3794 case 4:
c6fb90c8
L		 3795 overlap3 = operand_type_and (i.types[3],
3796 operand_types[3]);
d1cbb4db 3797 case 3:
c6fb90c8
L		 3798 overlap2 = operand_type_and (i.types[2],
3799 operand_types[2]);
d1cbb4db
L		 3800 break;
3801 }
29b0f896 3802
f48ff2ae
L		 3803 switch (t->operands)
3804 {
c0f3af97
L		 3805 case 5:
3806 if (!operand_type_match (overlap4, i.types[4])
3807 || !operand_type_register_match (overlap3,
3808 i.types[3],
3809 operand_types[3],
3810 overlap4,
3811 i.types[4],
3812 operand_types[4]))
3813 continue;
f48ff2ae 3814 case 4:
40fb9820 3815 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3816 || (check_register
3817 && !operand_type_register_match (overlap2,
3818 i.types[2],
3819 operand_types[2],
3820 overlap3,
3821 i.types[3],
3822 operand_types[3])))
f48ff2ae
L		 3823 continue;
3824 case 3:
3825 /* Here we make use of the fact that there are no
3826 reverse match 3 operand instructions, and all 3
3827 operand instructions only need to be checked for
3828 register consistency between operands 2 and 3. */
40fb9820 3829 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3830 || (check_register
3831 && !operand_type_register_match (overlap1,
3832 i.types[1],
3833 operand_types[1],
3834 overlap2,
3835 i.types[2],
3836 operand_types[2])))
f48ff2ae
L		 3837 continue;
3838 break;
3839 }
29b0f896 3840 }
f48ff2ae 3841 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3842 slip through to break. */
3843 }
3629bb00 3844 if (!found_cpu_match)
29b0f896
AM		 3845 {
3846 found_reverse_match = 0;
3847 continue;
3848 }
c0f3af97 3849
29b0f896
AM		 3850 /* We've found a match; break out of loop. */
3851 break;
3852 }
3853
3854 if (t == current_templates->end)
3855 {
3856 /* We found no match. */
95f283e8
L		 3857 if (intel_syntax)
3858 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3859 current_templates->start->name);
3860 else
3861 as_bad (_("suffix or operands invalid for `%s'"),
3862 current_templates->start->name);
fa99fab2 3863 return NULL;
29b0f896 3864 }
252b5132 3865
29b0f896
AM		 3866 if (!quiet_warnings)
3867 {
3868 if (!intel_syntax
40fb9820
L		 3869 && (i.types[0].bitfield.jumpabsolute
3870 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3871 {
3872 as_warn (_("indirect %s without `*'"), t->name);
3873 }
3874
40fb9820
L		 3875 if (t->opcode_modifier.isprefix
3876 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3877 {
3878 /* Warn them that a data or address size prefix doesn't
3879 affect assembly of the next line of code. */
3880 as_warn (_("stand-alone `%s' prefix"), t->name);
3881 }
3882 }
3883
3884 /* Copy the template we found. */
3885 i.tm = *t;
539e75ad
L		 3886
3887 if (addr_prefix_disp != -1)
3888 i.tm.operand_types[addr_prefix_disp]
3889 = operand_types[addr_prefix_disp];
3890
29b0f896
AM		 3891 if (found_reverse_match)
3892 {
3893 /* If we found a reverse match we must alter the opcode
3894 direction bit. found_reverse_match holds bits to change
3895 (different for int & float insns). */
3896
3897 i.tm.base_opcode ^= found_reverse_match;
3898
539e75ad
L		 3899 i.tm.operand_types[0] = operand_types[1];
3900 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3901 }
3902
fa99fab2 3903 return t;
29b0f896
AM		 3904}
3905
3906static int
e3bb37b5 3907check_string (void)
29b0f896 3908{
40fb9820
L		 3909 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3910 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3911 {
3912 if (i.seg[0] != NULL && i.seg[0] != &es)
3913 {
a87af027 3914 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3915 i.tm.name,
a87af027
JB		 3916 mem_op + 1,
3917 register_prefix);
29b0f896
AM		 3918 return 0;
3919 }
3920 /* There's only ever one segment override allowed per instruction.
3921 This instruction possibly has a legal segment override on the
3922 second operand, so copy the segment to where non-string
3923 instructions store it, allowing common code. */
3924 i.seg[0] = i.seg[1];
3925 }
40fb9820 3926 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3927 {
3928 if (i.seg[1] != NULL && i.seg[1] != &es)
3929 {
a87af027 3930 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3931 i.tm.name,
a87af027
JB		 3932 mem_op + 2,
3933 register_prefix);
29b0f896
AM		 3934 return 0;
3935 }
3936 }
3937 return 1;
3938}
3939
3940static int
543613e9 3941process_suffix (void)
29b0f896
AM		 3942{
3943 /* If matched instruction specifies an explicit instruction mnemonic
3944 suffix, use it. */
40fb9820
L		 3945 if (i.tm.opcode_modifier.size16)
3946 i.suffix = WORD_MNEM_SUFFIX;
3947 else if (i.tm.opcode_modifier.size32)
3948 i.suffix = LONG_MNEM_SUFFIX;
3949 else if (i.tm.opcode_modifier.size64)
3950 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3951 else if (i.reg_operands)
3952 {
3953 /* If there's no instruction mnemonic suffix we try to invent one
3954 based on register operands. */
3955 if (!i.suffix)
3956 {
3957 /* We take i.suffix from the last register operand specified,
3958 Destination register type is more significant than source
381d071f
L		 3959 register type. crc32 in SSE4.2 prefers source register
3960 type. */
3961 if (i.tm.base_opcode == 0xf20f38f1)
3962 {
40fb9820
L		 3963 if (i.types[0].bitfield.reg16)
3964 i.suffix = WORD_MNEM_SUFFIX;
3965 else if (i.types[0].bitfield.reg32)
3966 i.suffix = LONG_MNEM_SUFFIX;
3967 else if (i.types[0].bitfield.reg64)
3968 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3969 }
9344ff29 3970 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3971 {
40fb9820 3972 if (i.types[0].bitfield.reg8)
20592a94
L		 3973 i.suffix = BYTE_MNEM_SUFFIX;
3974 }
381d071f
L		 3975
3976 if (!i.suffix)
3977 {
3978 int op;
3979
20592a94
L		 3980 if (i.tm.base_opcode == 0xf20f38f1
3981 || i.tm.base_opcode == 0xf20f38f0)
3982 {
3983 /* We have to know the operand size for crc32. */
3984 as_bad (_("ambiguous memory operand size for `%s`"),
3985 i.tm.name);
3986 return 0;
3987 }
3988
381d071f 3989 for (op = i.operands; --op >= 0;)
40fb9820 3990 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3991 {
40fb9820
L		 3992 if (i.types[op].bitfield.reg8)
3993 {
3994 i.suffix = BYTE_MNEM_SUFFIX;
3995 break;
3996 }
3997 else if (i.types[op].bitfield.reg16)
3998 {
3999 i.suffix = WORD_MNEM_SUFFIX;
4000 break;
4001 }
4002 else if (i.types[op].bitfield.reg32)
4003 {
4004 i.suffix = LONG_MNEM_SUFFIX;
4005 break;
4006 }
4007 else if (i.types[op].bitfield.reg64)
4008 {
4009 i.suffix = QWORD_MNEM_SUFFIX;
4010 break;
4011 }
381d071f
L		 4012 }
4013 }
29b0f896
AM		 4014 }
4015 else if (i.suffix == BYTE_MNEM_SUFFIX)
4016 {
4017 if (!check_byte_reg ())
4018 return 0;
4019 }
4020 else if (i.suffix == LONG_MNEM_SUFFIX)
4021 {
4022 if (!check_long_reg ())
4023 return 0;
4024 }
4025 else if (i.suffix == QWORD_MNEM_SUFFIX)
4026 {
955e1e6a
L		 4027 if (intel_syntax
4028 && i.tm.opcode_modifier.ignoresize
4029 && i.tm.opcode_modifier.no_qsuf)
4030 i.suffix = 0;
4031 else if (!check_qword_reg ())
29b0f896
AM		 4032 return 0;
4033 }
4034 else if (i.suffix == WORD_MNEM_SUFFIX)
4035 {
4036 if (!check_word_reg ())
4037 return 0;
4038 }
c0f3af97
L		 4039 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4040 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4041 {
c0f3af97 4042 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4043 should check if it is a valid suffix. */
4044 }
40fb9820 4045 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4046 /* Do nothing if the instruction is going to ignore the prefix. */
4047 ;
4048 else
4049 abort ();
4050 }
40fb9820 4051 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4052 && !i.suffix
4053 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4054 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4055 {
4056 i.suffix = stackop_size;
4057 }
9306ca4a
JB		 4058 else if (intel_syntax
4059 && !i.suffix
40fb9820
L		 4060 && (i.tm.operand_types[0].bitfield.jumpabsolute
4061 || i.tm.opcode_modifier.jumpbyte
4062 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4063 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4064 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4065 {
4066 switch (flag_code)
4067 {
4068 case CODE_64BIT:
40fb9820 4069 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4070 {
4071 i.suffix = QWORD_MNEM_SUFFIX;
4072 break;
4073 }
4074 case CODE_32BIT:
40fb9820 4075 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4076 i.suffix = LONG_MNEM_SUFFIX;
4077 break;
4078 case CODE_16BIT:
40fb9820 4079 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4080 i.suffix = WORD_MNEM_SUFFIX;
4081 break;
4082 }
4083 }
252b5132 4084
9306ca4a 4085 if (!i.suffix)
29b0f896 4086 {
9306ca4a
JB		 4087 if (!intel_syntax)
4088 {
40fb9820 4089 if (i.tm.opcode_modifier.w)
9306ca4a 4090 {
4eed87de
AM		 4091 as_bad (_("no instruction mnemonic suffix given and "
4092 "no register operands; can't size instruction"));
9306ca4a
JB		 4093 return 0;
4094 }
4095 }
4096 else
4097 {
40fb9820 4098 unsigned int suffixes;
7ab9ffdd 4099
40fb9820
L		 4100 suffixes = !i.tm.opcode_modifier.no_bsuf;
4101 if (!i.tm.opcode_modifier.no_wsuf)
4102 suffixes |= 1 << 1;
4103 if (!i.tm.opcode_modifier.no_lsuf)
4104 suffixes |= 1 << 2;
fc4adea1 4105 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4106 suffixes |= 1 << 3;
4107 if (!i.tm.opcode_modifier.no_ssuf)
4108 suffixes |= 1 << 4;
4109 if (!i.tm.opcode_modifier.no_qsuf)
4110 suffixes |= 1 << 5;
4111
4112 /* There are more than suffix matches. */
4113 if (i.tm.opcode_modifier.w
9306ca4a 4114 || ((suffixes & (suffixes - 1))
40fb9820
L		 4115 && !i.tm.opcode_modifier.defaultsize
4116 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4117 {
4118 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4119 return 0;
4120 }
4121 }
29b0f896 4122 }
252b5132 4123
9306ca4a
JB		 4124 /* Change the opcode based on the operand size given by i.suffix;
4125 We don't need to change things for byte insns. */
4126
582d5edd
L		 4127 if (i.suffix
4128 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4129 && i.suffix != XMMWORD_MNEM_SUFFIX
4130 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4131 {
4132 /* It's not a byte, select word/dword operation. */
40fb9820 4133 if (i.tm.opcode_modifier.w)
29b0f896 4134 {
40fb9820 4135 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4136 i.tm.base_opcode |= 8;
4137 else
4138 i.tm.base_opcode |= 1;
4139 }
0f3f3d8b 4140
29b0f896
AM		 4141 /* Now select between word & dword operations via the operand
4142 size prefix, except for instructions that will ignore this
4143 prefix anyway. */
ca61edf2 4144 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4145 {
ca61edf2
L		 4146 /* The address size override prefix changes the size of the
4147 first operand. */
40fb9820
L		 4148 if ((flag_code == CODE_32BIT
4149 && i.op->regs[0].reg_type.bitfield.reg16)
4150 || (flag_code != CODE_32BIT
4151 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4152 if (!add_prefix (ADDR_PREFIX_OPCODE))
4153 return 0;
4154 }
4155 else if (i.suffix != QWORD_MNEM_SUFFIX
4156 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4157 && !i.tm.opcode_modifier.ignoresize
4158 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4159 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4160 || (flag_code == CODE_64BIT
40fb9820 4161 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4162 {
4163 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4164
40fb9820 4165 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4166 prefix = ADDR_PREFIX_OPCODE;
252b5132 4167
29b0f896
AM		 4168 if (!add_prefix (prefix))
4169 return 0;
24eab124 4170 }
252b5132 4171
29b0f896
AM		 4172 /* Set mode64 for an operand. */
4173 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4174 && flag_code == CODE_64BIT
40fb9820 4175 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4176 {
4177 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4178 need rex64. cmpxchg8b is also a special case. */
4179 if (! (i.operands == 2
4180 && i.tm.base_opcode == 0x90
4181 && i.tm.extension_opcode == None
0dfbf9d7
L		 4182 && operand_type_equal (&i.types [0], &acc64)
4183 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4184 && ! (i.operands == 1
4185 && i.tm.base_opcode == 0xfc7
4186 && i.tm.extension_opcode == 1
40fb9820
L		 4187 && !operand_type_check (i.types [0], reg)
4188 && operand_type_check (i.types [0], anymem)))
f6bee062 4189 i.rex |= REX_W;
46e883c5 4190 }
3e73aa7c 4191
29b0f896
AM		 4192 /* Size floating point instruction. */
4193 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4194 if (i.tm.opcode_modifier.floatmf)
543613e9 4195 i.tm.base_opcode ^= 4;
29b0f896 4196 }
7ecd2f8b 4197
29b0f896
AM		 4198 return 1;
4199}
3e73aa7c 4200
29b0f896 4201static int
543613e9 4202check_byte_reg (void)
29b0f896
AM		 4203{
4204 int op;
543613e9 4205
29b0f896
AM		 4206 for (op = i.operands; --op >= 0;)
4207 {
4208 /* If this is an eight bit register, it's OK. If it's the 16 or
4209 32 bit version of an eight bit register, we will just use the
4210 low portion, and that's OK too. */
40fb9820 4211 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4212 continue;
4213
ca61edf2
L		 4214 /* Don't generate this warning if not needed. */
4215 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4216 continue;
4217
9344ff29
L		 4218 /* crc32 doesn't generate this warning. */
4219 if (i.tm.base_opcode == 0xf20f38f0)
4220 continue;
4221
40fb9820
L		 4222 if ((i.types[op].bitfield.reg16
4223 || i.types[op].bitfield.reg32
4224 || i.types[op].bitfield.reg64)
4225 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4226 {
4227 /* Prohibit these changes in the 64bit mode, since the
4228 lowering is more complicated. */
4229 if (flag_code == CODE_64BIT
40fb9820 4230 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4231 {
2ca3ace5
L		 4232 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4233 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4234 i.suffix);
4235 return 0;
4236 }
4237#if REGISTER_WARNINGS
4238 if (!quiet_warnings
40fb9820 4239 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4240 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4241 register_prefix,
40fb9820 4242 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4243 ? REGNAM_AL - REGNAM_AX
4244 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4245 register_prefix,
29b0f896
AM		 4246 i.op[op].regs->reg_name,
4247 i.suffix);
4248#endif
4249 continue;
4250 }
4251 /* Any other register is bad. */
40fb9820
L		 4252 if (i.types[op].bitfield.reg16
4253 || i.types[op].bitfield.reg32
4254 || i.types[op].bitfield.reg64
4255 || i.types[op].bitfield.regmmx
4256 || i.types[op].bitfield.regxmm
c0f3af97 4257 || i.types[op].bitfield.regymm
40fb9820
L		 4258 || i.types[op].bitfield.sreg2
4259 || i.types[op].bitfield.sreg3
4260 || i.types[op].bitfield.control
4261 || i.types[op].bitfield.debug
4262 || i.types[op].bitfield.test
4263 || i.types[op].bitfield.floatreg
4264 || i.types[op].bitfield.floatacc)
29b0f896 4265 {
a540244d
L		 4266 as_bad (_("`%s%s' not allowed with `%s%c'"),
4267 register_prefix,
29b0f896
AM		 4268 i.op[op].regs->reg_name,
4269 i.tm.name,
4270 i.suffix);
4271 return 0;
4272 }
4273 }
4274 return 1;
4275}
4276
4277static int
e3bb37b5 4278check_long_reg (void)
29b0f896
AM		 4279{
4280 int op;
4281
4282 for (op = i.operands; --op >= 0;)
4283 /* Reject eight bit registers, except where the template requires
4284 them. (eg. movzb) */
40fb9820
L		 4285 if (i.types[op].bitfield.reg8
4286 && (i.tm.operand_types[op].bitfield.reg16
4287 || i.tm.operand_types[op].bitfield.reg32
4288 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4289 {
a540244d
L		 4290 as_bad (_("`%s%s' not allowed with `%s%c'"),
4291 register_prefix,
29b0f896
AM		 4292 i.op[op].regs->reg_name,
4293 i.tm.name,
4294 i.suffix);
4295 return 0;
4296 }
4297 /* Warn if the e prefix on a general reg is missing. */
4298 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4299 && i.types[op].bitfield.reg16
4300 && (i.tm.operand_types[op].bitfield.reg32
4301 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4302 {
4303 /* Prohibit these changes in the 64bit mode, since the
4304 lowering is more complicated. */
4305 if (flag_code == CODE_64BIT)
252b5132 4306 {
2ca3ace5
L		 4307 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4308 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4309 i.suffix);
4310 return 0;
252b5132 4311 }
29b0f896
AM		 4312#if REGISTER_WARNINGS
4313 else
a540244d
L		 4314 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4315 register_prefix,
29b0f896 4316 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4317 register_prefix,
29b0f896
AM		 4318 i.op[op].regs->reg_name,
4319 i.suffix);
4320#endif
252b5132 4321 }
29b0f896 4322 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4323 else if (i.types[op].bitfield.reg64
4324 && (i.tm.operand_types[op].bitfield.reg32
4325 || i.tm.operand_types[op].bitfield.acc))
252b5132 4326 {
34828aad 4327 if (intel_syntax
ca61edf2 4328 && i.tm.opcode_modifier.toqword
40fb9820 4329 && !i.types[0].bitfield.regxmm)
34828aad 4330 {
ca61edf2 4331 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4332 i.suffix = QWORD_MNEM_SUFFIX;
4333 }
4334 else
4335 {
4336 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4337 register_prefix, i.op[op].regs->reg_name,
4338 i.suffix);
4339 return 0;
4340 }
29b0f896
AM		 4341 }
4342 return 1;
4343}
252b5132 4344
29b0f896 4345static int
e3bb37b5 4346check_qword_reg (void)
29b0f896
AM		 4347{
4348 int op;
252b5132 4349
29b0f896
AM		 4350 for (op = i.operands; --op >= 0; )
4351 /* Reject eight bit registers, except where the template requires
4352 them. (eg. movzb) */
40fb9820
L		 4353 if (i.types[op].bitfield.reg8
4354 && (i.tm.operand_types[op].bitfield.reg16
4355 || i.tm.operand_types[op].bitfield.reg32
4356 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4357 {
a540244d
L		 4358 as_bad (_("`%s%s' not allowed with `%s%c'"),
4359 register_prefix,
29b0f896
AM		 4360 i.op[op].regs->reg_name,
4361 i.tm.name,
4362 i.suffix);
4363 return 0;
4364 }
4365 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4366 else if ((i.types[op].bitfield.reg16
4367 || i.types[op].bitfield.reg32)
4368 && (i.tm.operand_types[op].bitfield.reg32
4369 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4370 {
4371 /* Prohibit these changes in the 64bit mode, since the
4372 lowering is more complicated. */
34828aad 4373 if (intel_syntax
ca61edf2 4374 && i.tm.opcode_modifier.todword
40fb9820 4375 && !i.types[0].bitfield.regxmm)
34828aad 4376 {
ca61edf2 4377 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4378 i.suffix = LONG_MNEM_SUFFIX;
4379 }
4380 else
4381 {
4382 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4383 register_prefix, i.op[op].regs->reg_name,
4384 i.suffix);
4385 return 0;
4386 }
252b5132 4387 }
29b0f896
AM		 4388 return 1;
4389}
252b5132 4390
29b0f896 4391static int
e3bb37b5 4392check_word_reg (void)
29b0f896
AM		 4393{
4394 int op;
4395 for (op = i.operands; --op >= 0;)
4396 /* Reject eight bit registers, except where the template requires
4397 them. (eg. movzb) */
40fb9820
L		 4398 if (i.types[op].bitfield.reg8
4399 && (i.tm.operand_types[op].bitfield.reg16
4400 || i.tm.operand_types[op].bitfield.reg32
4401 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4402 {
a540244d
L		 4403 as_bad (_("`%s%s' not allowed with `%s%c'"),
4404 register_prefix,
29b0f896
AM		 4405 i.op[op].regs->reg_name,
4406 i.tm.name,
4407 i.suffix);
4408 return 0;
4409 }
4410 /* Warn if the e prefix on a general reg is present. */
4411 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4412 && i.types[op].bitfield.reg32
4413 && (i.tm.operand_types[op].bitfield.reg16
4414 || i.tm.operand_types[op].bitfield.acc))
252b5132 4415 {
29b0f896
AM		 4416 /* Prohibit these changes in the 64bit mode, since the
4417 lowering is more complicated. */
4418 if (flag_code == CODE_64BIT)
252b5132 4419 {
2ca3ace5
L		 4420 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4421 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4422 i.suffix);
4423 return 0;
252b5132 4424 }
29b0f896
AM		 4425 else
4426#if REGISTER_WARNINGS
a540244d
L		 4427 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4428 register_prefix,
29b0f896 4429 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4430 register_prefix,
29b0f896
AM		 4431 i.op[op].regs->reg_name,
4432 i.suffix);
4433#endif
4434 }
4435 return 1;
4436}
252b5132 4437
29b0f896 4438static int
40fb9820 4439update_imm (unsigned int j)
29b0f896 4440{
bc0844ae 4441 i386_operand_type overlap = i.types[j];
40fb9820
L		 4442 if ((overlap.bitfield.imm8
4443 || overlap.bitfield.imm8s
4444 || overlap.bitfield.imm16
4445 || overlap.bitfield.imm32
4446 || overlap.bitfield.imm32s
4447 || overlap.bitfield.imm64)
0dfbf9d7
L		 4448 && !operand_type_equal (&overlap, &imm8)
4449 && !operand_type_equal (&overlap, &imm8s)
4450 && !operand_type_equal (&overlap, &imm16)
4451 && !operand_type_equal (&overlap, &imm32)
4452 && !operand_type_equal (&overlap, &imm32s)
4453 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4454 {
4455 if (i.suffix)
4456 {
40fb9820
L		 4457 i386_operand_type temp;
4458
0dfbf9d7 4459 operand_type_set (&temp, 0);
7ab9ffdd 4460 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4461 {
4462 temp.bitfield.imm8 = overlap.bitfield.imm8;
4463 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4464 }
4465 else if (i.suffix == WORD_MNEM_SUFFIX)
4466 temp.bitfield.imm16 = overlap.bitfield.imm16;
4467 else if (i.suffix == QWORD_MNEM_SUFFIX)
4468 {
4469 temp.bitfield.imm64 = overlap.bitfield.imm64;
4470 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4471 }
4472 else
4473 temp.bitfield.imm32 = overlap.bitfield.imm32;
4474 overlap = temp;
29b0f896 4475 }
0dfbf9d7
L		 4476 else if (operand_type_equal (&overlap, &imm16_32_32s)
4477 || operand_type_equal (&overlap, &imm16_32)
4478 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4479 {
40fb9820 4480 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4481 overlap = imm16;
40fb9820 4482 else
65da13b5 4483 overlap = imm32s;
29b0f896 4484 }
0dfbf9d7
L		 4485 if (!operand_type_equal (&overlap, &imm8)
4486 && !operand_type_equal (&overlap, &imm8s)
4487 && !operand_type_equal (&overlap, &imm16)
4488 && !operand_type_equal (&overlap, &imm32)
4489 && !operand_type_equal (&overlap, &imm32s)
4490 && !operand_type_equal (&overlap, &imm64))
29b0f896 4491 {
4eed87de
AM		 4492 as_bad (_("no instruction mnemonic suffix given; "
4493 "can't determine immediate size"));
29b0f896
AM		 4494 return 0;
4495 }
4496 }
40fb9820 4497 i.types[j] = overlap;
29b0f896 4498
40fb9820
L		 4499 return 1;
4500}
4501
4502static int
4503finalize_imm (void)
4504{
bc0844ae 4505 unsigned int j, n;
29b0f896 4506
bc0844ae
L		 4507 /* Update the first 2 immediate operands. */
4508 n = i.operands > 2 ? 2 : i.operands;
4509 if (n)
4510 {
4511 for (j = 0; j < n; j++)
4512 if (update_imm (j) == 0)
4513 return 0;
40fb9820 4514
bc0844ae
L		 4515 /* The 3rd operand can't be immediate operand. */
4516 gas_assert (operand_type_check (i.types[2], imm) == 0);
4517 }
29b0f896
AM		 4518
4519 return 1;
4520}
4521
c0f3af97
L		 4522static int
4523bad_implicit_operand (int xmm)
4524{
4525 const char *reg = xmm ? "xmm0" : "ymm0";
4526 if (intel_syntax)
4527 as_bad (_("the last operand of `%s' must be `%s%s'"),
4528 i.tm.name, register_prefix, reg);
4529 else
4530 as_bad (_("the first operand of `%s' must be `%s%s'"),
4531 i.tm.name, register_prefix, reg);
4532 return 0;
4533}
4534
29b0f896 4535static int
e3bb37b5 4536process_operands (void)
29b0f896
AM		 4537{
4538 /* Default segment register this instruction will use for memory
4539 accesses. 0 means unknown. This is only for optimizing out
4540 unnecessary segment overrides. */
4541 const seg_entry *default_seg = 0;
4542
c0f3af97
L		 4543 if (i.tm.opcode_modifier.sse2avx
4544 && (i.tm.opcode_modifier.vexnds
4545 || i.tm.opcode_modifier.vexndd))
29b0f896 4546 {
c0f3af97
L		 4547 unsigned int dup = i.operands;
4548 unsigned int dest = dup - 1;
9fcfb3d7
L		 4549 unsigned int j;
4550
c0f3af97 4551 /* The destination must be an xmm register. */
9c2799c2 4552 gas_assert (i.reg_operands
7ab9ffdd
L		 4553 && MAX_OPERANDS > dup
4554 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4555
4556 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4557 {
c0f3af97 4558 /* The first operand is implicit and must be xmm0. */
9c2799c2 4559 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4560 if (i.op[0].regs->reg_num != 0)
4561 return bad_implicit_operand (1);
4562
4563 if (i.tm.opcode_modifier.vex3sources)
4564 {
4565 /* Keep xmm0 for instructions with VEX prefix and 3
4566 sources. */
4567 goto duplicate;
4568 }
e2ec9d29 4569 else
c0f3af97
L		 4570 {
4571 /* We remove the first xmm0 and keep the number of
4572 operands unchanged, which in fact duplicates the
4573 destination. */
4574 for (j = 1; j < i.operands; j++)
4575 {
4576 i.op[j - 1] = i.op[j];
4577 i.types[j - 1] = i.types[j];
4578 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4579 }
4580 }
4581 }
4582 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4583 {
9c2799c2 4584 gas_assert ((MAX_OPERANDS - 1) > dup
7ab9ffdd 4585 && i.tm.opcode_modifier.vex3sources);
c0f3af97
L		 4586
4587 /* Add the implicit xmm0 for instructions with VEX prefix
4588 and 3 sources. */
4589 for (j = i.operands; j > 0; j--)
4590 {
4591 i.op[j] = i.op[j - 1];
4592 i.types[j] = i.types[j - 1];
4593 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4594 }
4595 i.op[0].regs
4596 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4597 i.types[0] = regxmm;
c0f3af97
L		 4598 i.tm.operand_types[0] = regxmm;
4599
4600 i.operands += 2;
4601 i.reg_operands += 2;
4602 i.tm.operands += 2;
4603
4604 dup++;
4605 dest++;
4606 i.op[dup] = i.op[dest];
4607 i.types[dup] = i.types[dest];
4608 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4609 }
c0f3af97
L		 4610 else
4611 {
4612duplicate:
4613 i.operands++;
4614 i.reg_operands++;
4615 i.tm.operands++;
4616
4617 i.op[dup] = i.op[dest];
4618 i.types[dup] = i.types[dest];
4619 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4620 }
4621
4622 if (i.tm.opcode_modifier.immext)
4623 process_immext ();
4624 }
4625 else if (i.tm.opcode_modifier.firstxmm0)
4626 {
4627 unsigned int j;
4628
4629 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4630 gas_assert (i.reg_operands
7ab9ffdd
L		 4631 && (operand_type_equal (&i.types[0], &regxmm)
4632 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4633 if (i.op[0].regs->reg_num != 0)
4634 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4635
4636 for (j = 1; j < i.operands; j++)
4637 {
4638 i.op[j - 1] = i.op[j];
4639 i.types[j - 1] = i.types[j];
4640
4641 /* We need to adjust fields in i.tm since they are used by
4642 build_modrm_byte. */
4643 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4644 }
4645
e2ec9d29
L		 4646 i.operands--;
4647 i.reg_operands--;
e2ec9d29
L		 4648 i.tm.operands--;
4649 }
4650 else if (i.tm.opcode_modifier.regkludge)
4651 {
4652 /* The imul $imm, %reg instruction is converted into
4653 imul $imm, %reg, %reg, and the clr %reg instruction
4654 is converted into xor %reg, %reg. */
4655
4656 unsigned int first_reg_op;
4657
4658 if (operand_type_check (i.types[0], reg))
4659 first_reg_op = 0;
4660 else
4661 first_reg_op = 1;
4662 /* Pretend we saw the extra register operand. */
9c2799c2 4663 gas_assert (i.reg_operands == 1
7ab9ffdd 4664 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4665 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4666 i.types[first_reg_op + 1] = i.types[first_reg_op];
4667 i.operands++;
4668 i.reg_operands++;
29b0f896
AM		 4669 }
4670
40fb9820 4671 if (i.tm.opcode_modifier.shortform)
29b0f896 4672 {
40fb9820
L		 4673 if (i.types[0].bitfield.sreg2
4674 || i.types[0].bitfield.sreg3)
29b0f896 4675 {
4eed87de
AM		 4676 if (i.tm.base_opcode == POP_SEG_SHORT
4677 && i.op[0].regs->reg_num == 1)
29b0f896 4678 {
a87af027 4679 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4680 return 0;
29b0f896 4681 }
4eed87de
AM		 4682 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4683 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4684 i.rex |= REX_B;
4eed87de
AM		 4685 }
4686 else
4687 {
7ab9ffdd 4688 /* The register or float register operand is in operand
85f10a01 4689 0 or 1. */
40fb9820 4690 unsigned int op;
7ab9ffdd
L		 4691
4692 if (i.types[0].bitfield.floatreg
4693 || operand_type_check (i.types[0], reg))
4694 op = 0;
4695 else
4696 op = 1;
4eed87de
AM		 4697 /* Register goes in low 3 bits of opcode. */
4698 i.tm.base_opcode |= i.op[op].regs->reg_num;
4699 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4700 i.rex |= REX_B;
40fb9820 4701 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4702 {
4eed87de
AM		 4703 /* Warn about some common errors, but press on regardless.
4704 The first case can be generated by gcc (<= 2.8.1). */
4705 if (i.operands == 2)
4706 {
4707 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4708 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4709 register_prefix, i.op[!intel_syntax].regs->reg_name,
4710 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4711 }
4712 else
4713 {
4714 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4715 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4716 register_prefix, i.op[0].regs->reg_name);
4eed87de 4717 }
29b0f896
AM		 4718 }
4719 }
4720 }
40fb9820 4721 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4722 {
4723 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4724 must be put into the modrm byte). Now, we make the modrm and
4725 index base bytes based on all the info we've collected. */
29b0f896
AM		 4726
4727 default_seg = build_modrm_byte ();
4728 }
8a2ed489 4729 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4730 {
4731 default_seg = &ds;
4732 }
40fb9820 4733 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4734 {
4735 /* For the string instructions that allow a segment override
4736 on one of their operands, the default segment is ds. */
4737 default_seg = &ds;
4738 }
4739
75178d9d
L		 4740 if (i.tm.base_opcode == 0x8d /* lea */
4741 && i.seg[0]
4742 && !quiet_warnings)
30123838 4743 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4744
4745 /* If a segment was explicitly specified, and the specified segment
4746 is not the default, use an opcode prefix to select it. If we
4747 never figured out what the default segment is, then default_seg
4748 will be zero at this point, and the specified segment prefix will
4749 always be used. */
29b0f896
AM		 4750 if ((i.seg[0]) && (i.seg[0] != default_seg))
4751 {
4752 if (!add_prefix (i.seg[0]->seg_prefix))
4753 return 0;
4754 }
4755 return 1;
4756}
4757
4758static const seg_entry *
e3bb37b5 4759build_modrm_byte (void)
29b0f896
AM		 4760{
4761 const seg_entry *default_seg = 0;
c0f3af97 4762 unsigned int source, dest;
7ab9ffdd 4763 int vex_3_sources;
c0f3af97
L		 4764
4765 /* The first operand of instructions with VEX prefix and 3 sources
4766 must be VEX_Imm4. */
4767 vex_3_sources = i.tm.opcode_modifier.vex3sources;
4768 if (vex_3_sources)
4769 {
4770 unsigned int nds, reg;
4771
922d8de8
DR		 4772 if (i.tm.opcode_modifier.veximmext
4773 && i.tm.opcode_modifier.immext)
4774 {
4775 dest = i.operands - 2;
4776 gas_assert (dest == 3);
4777 }
4778 else
0bfee649 4779 dest = i.operands - 1;
c0f3af97 4780 nds = dest - 1;
922d8de8
DR		 4781
4782 /* This instruction must have 4 register operands
4783 or 3 register operands plus 1 memory operand.
4784 It must have VexNDS and VexImmExt. */
4785 gas_assert ((i.reg_operands == 4
7ab9ffdd
L		 4786 || (i.reg_operands == 3 && i.mem_operands == 1))
4787 && i.tm.opcode_modifier.vexnds
4788 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4789 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4790 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4791
0bfee649
L		 4792 /* Generate an 8bit immediate operand to encode the register
4793 operand. */
4794 expressionS *exp = &im_expressions[i.imm_operands++];
4795 i.op[i.operands].imms = exp;
4796 i.types[i.operands] = imm8;
4797 i.operands++;
922d8de8
DR		 4798 /* If VexW1 is set, the first operand is the source and
4799 the second operand is encoded in the immediate operand. */
4800 if (i.tm.opcode_modifier.vexw1)
4801 {
4802 source = 0;
4803 reg = 1;
4804 }
4805 else
4806 {
4807 source = 1;
4808 reg = 0;
4809 }
4810 /* FMA4 swaps REG and NDS. */
4811 if (i.tm.cpu_flags.bitfield.cpufma4)
4812 {
4813 unsigned int tmp;
4814 tmp = reg;
4815 reg = nds;
4816 nds = tmp;
4817 }
4818 gas_assert ((operand_type_equal (&i.tm.operand_types[reg], &regxmm)
4819 || operand_type_equal (&i.tm.operand_types[reg],
4820 &regymm))
4821 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
4822 || operand_type_equal (&i.tm.operand_types[nds],
4823 &regymm)));
0bfee649
L		 4824 exp->X_op = O_constant;
4825 exp->X_add_number
922d8de8
DR		 4826 = ((i.op[reg].regs->reg_num
4827 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4828 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4829 }
4830 else
4831 source = dest = 0;
29b0f896
AM		 4832
4833 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4834 implicit registers do not count. If there are 3 register
4835 operands, it must be a instruction with VexNDS. For a
4836 instruction with VexNDD, the destination register is encoded
4837 in VEX prefix. If there are 4 register operands, it must be
4838 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 4839 if (i.mem_operands == 0
4840 && ((i.reg_operands == 2
4841 && !i.tm.opcode_modifier.vexndd)
4842 || (i.reg_operands == 3
4843 && i.tm.opcode_modifier.vexnds)
4844 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 4845 {
cab737b9
L		 4846 switch (i.operands)
4847 {
4848 case 2:
4849 source = 0;
4850 break;
4851 case 3:
c81128dc
L		 4852 /* When there are 3 operands, one of them may be immediate,
4853 which may be the first or the last operand. Otherwise,
c0f3af97
L		 4854 the first operand must be shift count register (cl) or it
4855 is an instruction with VexNDS. */
9c2799c2 4856 gas_assert (i.imm_operands == 1
7ab9ffdd
L		 4857 || (i.imm_operands == 0
4858 && (i.tm.opcode_modifier.vexnds
4859 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 4860 if (operand_type_check (i.types[0], imm)
4861 || i.types[0].bitfield.shiftcount)
4862 source = 1;
4863 else
4864 source = 0;
cab737b9
L		 4865 break;
4866 case 4:
368d64cc
L		 4867 /* When there are 4 operands, the first two must be 8bit
4868 immediate operands. The source operand will be the 3rd
c0f3af97
L		 4869 one.
4870
4871 For instructions with VexNDS, if the first operand
4872 an imm8, the source operand is the 2nd one. If the last
4873 operand is imm8, the source operand is the first one. */
9c2799c2 4874 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 4875 && i.types[0].bitfield.imm8
4876 && i.types[1].bitfield.imm8)
4877 || (i.tm.opcode_modifier.vexnds
4878 && i.imm_operands == 1
4879 && (i.types[0].bitfield.imm8
4880 || i.types[i.operands - 1].bitfield.imm8)));
c0f3af97
L		 4881 if (i.tm.opcode_modifier.vexnds)
4882 {
4883 if (i.types[0].bitfield.imm8)
4884 source = 1;
4885 else
4886 source = 0;
4887 }
4888 else
4889 source = 2;
4890 break;
4891 case 5:
cab737b9
L		 4892 break;
4893 default:
4894 abort ();
4895 }
4896
c0f3af97
L		 4897 if (!vex_3_sources)
4898 {
4899 dest = source + 1;
4900
4901 if (i.tm.opcode_modifier.vexnds)
4902 {
4903 /* For instructions with VexNDS, the register-only
4904 source operand must be XMM or YMM register. It is
fa99fab2
L		 4905 encoded in VEX prefix. We need to clear RegMem bit
4906 before calling operand_type_equal. */
4907 i386_operand_type op = i.tm.operand_types[dest];
4908 op.bitfield.regmem = 0;
c0f3af97 4909 if ((dest + 1) >= i.operands
fa99fab2
L		 4910 || (!operand_type_equal (&op, &regxmm)
4911 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 4912 abort ();
4913 i.vex.register_specifier = i.op[dest].regs;
4914 dest++;
4915 }
4916 }
29b0f896
AM		 4917
4918 i.rm.mode = 3;
4919 /* One of the register operands will be encoded in the i.tm.reg
4920 field, the other in the combined i.tm.mode and i.tm.regmem
4921 fields. If no form of this instruction supports a memory
4922 destination operand, then we assume the source operand may
4923 sometimes be a memory operand and so we need to store the
4924 destination in the i.rm.reg field. */
40fb9820
L		 4925 if (!i.tm.operand_types[dest].bitfield.regmem
4926 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4927 {
4928 i.rm.reg = i.op[dest].regs->reg_num;
4929 i.rm.regmem = i.op[source].regs->reg_num;
4930 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4931 i.rex |= REX_R;
29b0f896 4932 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4933 i.rex |= REX_B;
29b0f896
AM		 4934 }
4935 else
4936 {
4937 i.rm.reg = i.op[source].regs->reg_num;
4938 i.rm.regmem = i.op[dest].regs->reg_num;
4939 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4940 i.rex |= REX_B;
29b0f896 4941 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4942 i.rex |= REX_R;
29b0f896 4943 }
161a04f6 4944 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4945 {
40fb9820
L		 4946 if (!i.types[0].bitfield.control
4947 && !i.types[1].bitfield.control)
c4a530c5 4948 abort ();
161a04f6 4949 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4950 add_prefix (LOCK_PREFIX_OPCODE);
4951 }
29b0f896
AM		 4952 }
4953 else
4954 { /* If it's not 2 reg operands... */
c0f3af97
L		 4955 unsigned int mem;
4956
29b0f896
AM		 4957 if (i.mem_operands)
4958 {
4959 unsigned int fake_zero_displacement = 0;
99018f42 4960 unsigned int op;
4eed87de 4961
7ab9ffdd
L		 4962 for (op = 0; op < i.operands; op++)
4963 if (operand_type_check (i.types[op], anymem))
4964 break;
7ab9ffdd 4965 gas_assert (op < i.operands);
29b0f896
AM		 4966
4967 default_seg = &ds;
4968
4969 if (i.base_reg == 0)
4970 {
4971 i.rm.mode = 0;
4972 if (!i.disp_operands)
4973 fake_zero_displacement = 1;
4974 if (i.index_reg == 0)
4975 {
4976 /* Operand is just <disp> */
20f0a1fc 4977 if (flag_code == CODE_64BIT)
29b0f896
AM		 4978 {
4979 /* 64bit mode overwrites the 32bit absolute
4980 addressing by RIP relative addressing and
4981 absolute addressing is encoded by one of the
4982 redundant SIB forms. */
4983 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4984 i.sib.base = NO_BASE_REGISTER;
4985 i.sib.index = NO_INDEX_REGISTER;
fc225355 4986 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4987 ? disp32s : disp32);
20f0a1fc 4988 }
fc225355
L		 4989 else if ((flag_code == CODE_16BIT)
4990 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4991 {
4992 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4993 i.types[op] = disp16;
20f0a1fc
NC		 4994 }
4995 else
4996 {
4997 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4998 i.types[op] = disp32;
29b0f896
AM		 4999 }
5000 }
5001 else /* !i.base_reg && i.index_reg */
5002 {
db51cc60
L		 5003 if (i.index_reg->reg_num == RegEiz
5004 || i.index_reg->reg_num == RegRiz)
5005 i.sib.index = NO_INDEX_REGISTER;
5006 else
5007 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5008 i.sib.base = NO_BASE_REGISTER;
5009 i.sib.scale = i.log2_scale_factor;
5010 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5011 i.types[op].bitfield.disp8 = 0;
5012 i.types[op].bitfield.disp16 = 0;
5013 i.types[op].bitfield.disp64 = 0;
29b0f896 5014 if (flag_code != CODE_64BIT)
40fb9820
L		 5015 {
5016 /* Must be 32 bit */
5017 i.types[op].bitfield.disp32 = 1;
5018 i.types[op].bitfield.disp32s = 0;
5019 }
29b0f896 5020 else
40fb9820
L		 5021 {
5022 i.types[op].bitfield.disp32 = 0;
5023 i.types[op].bitfield.disp32s = 1;
5024 }
29b0f896 5025 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5026 i.rex |= REX_X;
29b0f896
AM		 5027 }
5028 }
5029 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5030 else if (i.base_reg->reg_num == RegRip ||
5031 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5032 {
5033 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5034 i.types[op].bitfield.disp8 = 0;
5035 i.types[op].bitfield.disp16 = 0;
5036 i.types[op].bitfield.disp32 = 0;
5037 i.types[op].bitfield.disp32s = 1;
5038 i.types[op].bitfield.disp64 = 0;
71903a11 5039 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5040 if (! i.disp_operands)
5041 fake_zero_displacement = 1;
29b0f896 5042 }
40fb9820 5043 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5044 {
5045 switch (i.base_reg->reg_num)
5046 {
5047 case 3: /* (%bx) */
5048 if (i.index_reg == 0)
5049 i.rm.regmem = 7;
5050 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5051 i.rm.regmem = i.index_reg->reg_num - 6;
5052 break;
5053 case 5: /* (%bp) */
5054 default_seg = &ss;
5055 if (i.index_reg == 0)
5056 {
5057 i.rm.regmem = 6;
40fb9820 5058 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5059 {
5060 /* fake (%bp) into 0(%bp) */
40fb9820 5061 i.types[op].bitfield.disp8 = 1;
252b5132 5062 fake_zero_displacement = 1;
29b0f896
AM		 5063 }
5064 }
5065 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5066 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5067 break;
5068 default: /* (%si) -> 4 or (%di) -> 5 */
5069 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5070 }
5071 i.rm.mode = mode_from_disp_size (i.types[op]);
5072 }
5073 else /* i.base_reg and 32/64 bit mode */
5074 {
5075 if (flag_code == CODE_64BIT
40fb9820
L		 5076 && operand_type_check (i.types[op], disp))
5077 {
5078 i386_operand_type temp;
0dfbf9d7 5079 operand_type_set (&temp, 0);
40fb9820
L		 5080 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5081 i.types[op] = temp;
5082 if (i.prefix[ADDR_PREFIX] == 0)
5083 i.types[op].bitfield.disp32s = 1;
5084 else
5085 i.types[op].bitfield.disp32 = 1;
5086 }
20f0a1fc 5087
29b0f896
AM		 5088 i.rm.regmem = i.base_reg->reg_num;
5089 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5090 i.rex |= REX_B;
29b0f896
AM		 5091 i.sib.base = i.base_reg->reg_num;
5092 /* x86-64 ignores REX prefix bit here to avoid decoder
5093 complications. */
5094 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5095 {
5096 default_seg = &ss;
5097 if (i.disp_operands == 0)
5098 {
5099 fake_zero_displacement = 1;
40fb9820 5100 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5101 }
5102 }
5103 else if (i.base_reg->reg_num == ESP_REG_NUM)
5104 {
5105 default_seg = &ss;
5106 }
5107 i.sib.scale = i.log2_scale_factor;
5108 if (i.index_reg == 0)
5109 {
5110 /* <disp>(%esp) becomes two byte modrm with no index
5111 register. We've already stored the code for esp
5112 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5113 Any base register besides %esp will not use the
5114 extra modrm byte. */
5115 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5116 }
5117 else
5118 {
db51cc60
L		 5119 if (i.index_reg->reg_num == RegEiz
5120 || i.index_reg->reg_num == RegRiz)
5121 i.sib.index = NO_INDEX_REGISTER;
5122 else
5123 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5124 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5125 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5126 i.rex |= REX_X;
29b0f896 5127 }
67a4f2b7
AO		 5128
5129 if (i.disp_operands
5130 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5131 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5132 i.rm.mode = 0;
5133 else
5134 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5135 }
252b5132 5136
29b0f896
AM		 5137 if (fake_zero_displacement)
5138 {
5139 /* Fakes a zero displacement assuming that i.types[op]
5140 holds the correct displacement size. */
5141 expressionS *exp;
5142
9c2799c2 5143 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5144 exp = &disp_expressions[i.disp_operands++];
5145 i.op[op].disps = exp;
5146 exp->X_op = O_constant;
5147 exp->X_add_number = 0;
5148 exp->X_add_symbol = (symbolS *) 0;
5149 exp->X_op_symbol = (symbolS *) 0;
5150 }
c0f3af97
L		 5151
5152 mem = op;
29b0f896 5153 }
c0f3af97
L		 5154 else
5155 mem = ~0;
252b5132 5156
29b0f896
AM		 5157 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5158 (if any) based on i.tm.extension_opcode. Again, we must be
5159 careful to make sure that segment/control/debug/test/MMX
5160 registers are coded into the i.rm.reg field. */
5161 if (i.reg_operands)
5162 {
99018f42 5163 unsigned int op;
7ab9ffdd
L		 5164 unsigned int vex_reg = ~0;
5165
5166 for (op = 0; op < i.operands; op++)
5167 if (i.types[op].bitfield.reg8
5168 || i.types[op].bitfield.reg16
5169 || i.types[op].bitfield.reg32
5170 || i.types[op].bitfield.reg64
5171 || i.types[op].bitfield.regmmx
5172 || i.types[op].bitfield.regxmm
5173 || i.types[op].bitfield.regymm
5174 || i.types[op].bitfield.sreg2
5175 || i.types[op].bitfield.sreg3
5176 || i.types[op].bitfield.control
5177 || i.types[op].bitfield.debug
5178 || i.types[op].bitfield.test)
5179 break;
c0209578 5180
7ab9ffdd
L		 5181 if (vex_3_sources)
5182 op = dest;
5183 else if (i.tm.opcode_modifier.vexnds)
5184 {
5185 /* For instructions with VexNDS, the register-only
5186 source operand is encoded in VEX prefix. */
5187 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5188
7ab9ffdd 5189 if (op > mem)
c0f3af97 5190 {
7ab9ffdd
L		 5191 vex_reg = op++;
5192 gas_assert (op < i.operands);
c0f3af97
L		 5193 }
5194 else
c0f3af97 5195 {
7ab9ffdd
L		 5196 vex_reg = op + 1;
5197 gas_assert (vex_reg < i.operands);
c0f3af97 5198 }
7ab9ffdd
L		 5199 }
5200 else if (i.tm.opcode_modifier.vexndd)
5201 {
5202 /* For instructions with VexNDD, there should be
5203 no memory operand and the register destination
5204 is encoded in VEX prefix. */
5205 gas_assert (i.mem_operands == 0
5206 && (op + 2) == i.operands);
5207 vex_reg = op + 1;
5208 }
5209 else
5210 gas_assert (op < i.operands);
99018f42 5211
7ab9ffdd
L		 5212 if (vex_reg != (unsigned int) ~0)
5213 {
5214 gas_assert (i.reg_operands == 2);
5215
5216 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5217 & regxmm)
5218 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5219 &regymm))
5220 abort ();
5221 i.vex.register_specifier = i.op[vex_reg].regs;
5222 }
5223
5224 /* If there is an extension opcode to put here, the
5225 register number must be put into the regmem field. */
5226 if (i.tm.extension_opcode != None)
5227 {
5228 i.rm.regmem = i.op[op].regs->reg_num;
5229 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5230 i.rex |= REX_B;
5231 }
5232 else
5233 {
5234 i.rm.reg = i.op[op].regs->reg_num;
5235 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5236 i.rex |= REX_R;
5237 }
252b5132 5238
29b0f896
AM		 5239 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5240 must set it to 3 to indicate this is a register operand
5241 in the regmem field. */
5242 if (!i.mem_operands)
5243 i.rm.mode = 3;
5244 }
252b5132 5245
29b0f896 5246 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5247 if (i.tm.extension_opcode != None)
29b0f896
AM		 5248 i.rm.reg = i.tm.extension_opcode;
5249 }
5250 return default_seg;
5251}
252b5132 5252
29b0f896 5253static void
e3bb37b5 5254output_branch (void)
29b0f896
AM		 5255{
5256 char *p;
5257 int code16;
5258 int prefix;
5259 relax_substateT subtype;
5260 symbolS *sym;
5261 offsetT off;
5262
5263 code16 = 0;
5264 if (flag_code == CODE_16BIT)
5265 code16 = CODE16;
5266
5267 prefix = 0;
5268 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5269 {
29b0f896
AM		 5270 prefix = 1;
5271 i.prefixes -= 1;
5272 code16 ^= CODE16;
252b5132 5273 }
29b0f896
AM		 5274 /* Pentium4 branch hints. */
5275 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5276 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5277 {
29b0f896
AM		 5278 prefix++;
5279 i.prefixes--;
5280 }
5281 if (i.prefix[REX_PREFIX] != 0)
5282 {
5283 prefix++;
5284 i.prefixes--;
2f66722d
AM		 5285 }
5286
29b0f896
AM		 5287 if (i.prefixes != 0 && !intel_syntax)
5288 as_warn (_("skipping prefixes on this instruction"));
5289
5290 /* It's always a symbol; End frag & setup for relax.
5291 Make sure there is enough room in this frag for the largest
5292 instruction we may generate in md_convert_frag. This is 2
5293 bytes for the opcode and room for the prefix and largest
5294 displacement. */
5295 frag_grow (prefix + 2 + 4);
5296 /* Prefix and 1 opcode byte go in fr_fix. */
5297 p = frag_more (prefix + 1);
5298 if (i.prefix[DATA_PREFIX] != 0)
5299 *p++ = DATA_PREFIX_OPCODE;
5300 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5301 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5302 *p++ = i.prefix[SEG_PREFIX];
5303 if (i.prefix[REX_PREFIX] != 0)
5304 *p++ = i.prefix[REX_PREFIX];
5305 *p = i.tm.base_opcode;
5306
5307 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5308 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5309 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5310 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5311 else
5312 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5313 subtype |= code16;
3e73aa7c 5314
29b0f896
AM		 5315 sym = i.op[0].disps->X_add_symbol;
5316 off = i.op[0].disps->X_add_number;
3e73aa7c 5317
29b0f896
AM		 5318 if (i.op[0].disps->X_op != O_constant
5319 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5320 {
29b0f896
AM		 5321 /* Handle complex expressions. */
5322 sym = make_expr_symbol (i.op[0].disps);
5323 off = 0;
5324 }
3e73aa7c 5325
29b0f896
AM		 5326 /* 1 possible extra opcode + 4 byte displacement go in var part.
5327 Pass reloc in fr_var. */
5328 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5329}
3e73aa7c 5330
29b0f896 5331static void
e3bb37b5 5332output_jump (void)
29b0f896
AM		 5333{
5334 char *p;
5335 int size;
3e02c1cc 5336 fixS *fixP;
29b0f896 5337
40fb9820 5338 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5339 {
5340 /* This is a loop or jecxz type instruction. */
5341 size = 1;
5342 if (i.prefix[ADDR_PREFIX] != 0)
5343 {
5344 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5345 i.prefixes -= 1;
5346 }
5347 /* Pentium4 branch hints. */
5348 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5349 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5350 {
5351 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5352 i.prefixes--;
3e73aa7c
JH		 5353 }
5354 }
29b0f896
AM		 5355 else
5356 {
5357 int code16;
3e73aa7c 5358
29b0f896
AM		 5359 code16 = 0;
5360 if (flag_code == CODE_16BIT)
5361 code16 = CODE16;
3e73aa7c 5362
29b0f896
AM		 5363 if (i.prefix[DATA_PREFIX] != 0)
5364 {
5365 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5366 i.prefixes -= 1;
5367 code16 ^= CODE16;
5368 }
252b5132 5369
29b0f896
AM		 5370 size = 4;
5371 if (code16)
5372 size = 2;
5373 }
9fcc94b6 5374
29b0f896
AM		 5375 if (i.prefix[REX_PREFIX] != 0)
5376 {
5377 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5378 i.prefixes -= 1;
5379 }
252b5132 5380
29b0f896
AM		 5381 if (i.prefixes != 0 && !intel_syntax)
5382 as_warn (_("skipping prefixes on this instruction"));
e0890092 5383
29b0f896
AM		 5384 p = frag_more (1 + size);
5385 *p++ = i.tm.base_opcode;
e0890092 5386
3e02c1cc
AM		 5387 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5388 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5389
5390 /* All jumps handled here are signed, but don't use a signed limit
5391 check for 32 and 16 bit jumps as we want to allow wrap around at
5392 4G and 64k respectively. */
5393 if (size == 1)
5394 fixP->fx_signed = 1;
29b0f896 5395}
e0890092 5396
29b0f896 5397static void
e3bb37b5 5398output_interseg_jump (void)
29b0f896
AM		 5399{
5400 char *p;
5401 int size;
5402 int prefix;
5403 int code16;
252b5132 5404
29b0f896
AM		 5405 code16 = 0;
5406 if (flag_code == CODE_16BIT)
5407 code16 = CODE16;
a217f122 5408
29b0f896
AM		 5409 prefix = 0;
5410 if (i.prefix[DATA_PREFIX] != 0)
5411 {
5412 prefix = 1;
5413 i.prefixes -= 1;
5414 code16 ^= CODE16;
5415 }
5416 if (i.prefix[REX_PREFIX] != 0)
5417 {
5418 prefix++;
5419 i.prefixes -= 1;
5420 }
252b5132 5421
29b0f896
AM		 5422 size = 4;
5423 if (code16)
5424 size = 2;
252b5132 5425
29b0f896
AM		 5426 if (i.prefixes != 0 && !intel_syntax)
5427 as_warn (_("skipping prefixes on this instruction"));
252b5132 5428
29b0f896
AM		 5429 /* 1 opcode; 2 segment; offset */
5430 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5431
29b0f896
AM		 5432 if (i.prefix[DATA_PREFIX] != 0)
5433 *p++ = DATA_PREFIX_OPCODE;
252b5132 5434
29b0f896
AM		 5435 if (i.prefix[REX_PREFIX] != 0)
5436 *p++ = i.prefix[REX_PREFIX];
252b5132 5437
29b0f896
AM		 5438 *p++ = i.tm.base_opcode;
5439 if (i.op[1].imms->X_op == O_constant)
5440 {
5441 offsetT n = i.op[1].imms->X_add_number;
252b5132 5442
29b0f896
AM		 5443 if (size == 2
5444 && !fits_in_unsigned_word (n)
5445 && !fits_in_signed_word (n))
5446 {
5447 as_bad (_("16-bit jump out of range"));
5448 return;
5449 }
5450 md_number_to_chars (p, n, size);
5451 }
5452 else
5453 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5454 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5455 if (i.op[0].imms->X_op != O_constant)
5456 as_bad (_("can't handle non absolute segment in `%s'"),
5457 i.tm.name);
5458 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5459}
a217f122 5460
29b0f896 5461static void
e3bb37b5 5462output_insn (void)
29b0f896 5463{
2bbd9c25
JJ		 5464 fragS *insn_start_frag;
5465 offsetT insn_start_off;
5466
29b0f896
AM		 5467 /* Tie dwarf2 debug info to the address at the start of the insn.
5468 We can't do this after the insn has been output as the current
5469 frag may have been closed off. eg. by frag_var. */
5470 dwarf2_emit_insn (0);
5471
2bbd9c25
JJ		 5472 insn_start_frag = frag_now;
5473 insn_start_off = frag_now_fix ();
5474
29b0f896 5475 /* Output jumps. */
40fb9820 5476 if (i.tm.opcode_modifier.jump)
29b0f896 5477 output_branch ();
40fb9820
L		 5478 else if (i.tm.opcode_modifier.jumpbyte
5479 || i.tm.opcode_modifier.jumpdword)
29b0f896 5480 output_jump ();
40fb9820 5481 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5482 output_interseg_jump ();
5483 else
5484 {
5485 /* Output normal instructions here. */
5486 char *p;
5487 unsigned char *q;
47465058 5488 unsigned int j;
331d2d0d 5489 unsigned int prefix;
4dffcebc 5490
c0f3af97
L		 5491 /* Since the VEX prefix contains the implicit prefix, we don't
5492 need the explicit prefix. */
5493 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5494 {
c0f3af97 5495 switch (i.tm.opcode_length)
bc4bd9ab 5496 {
c0f3af97
L		 5497 case 3:
5498 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5499 {
c0f3af97
L		 5500 prefix = (i.tm.base_opcode >> 24) & 0xff;
5501 goto check_prefix;
5502 }
5503 break;
5504 case 2:
5505 if ((i.tm.base_opcode & 0xff0000) != 0)
5506 {
5507 prefix = (i.tm.base_opcode >> 16) & 0xff;
5508 if (i.tm.cpu_flags.bitfield.cpupadlock)
5509 {
4dffcebc 5510check_prefix:
c0f3af97
L		 5511 if (prefix != REPE_PREFIX_OPCODE
5512 || (i.prefix[LOCKREP_PREFIX]
5513 != REPE_PREFIX_OPCODE))
5514 add_prefix (prefix);
5515 }
5516 else
4dffcebc
L		 5517 add_prefix (prefix);
5518 }
c0f3af97
L		 5519 break;
5520 case 1:
5521 break;
5522 default:
5523 abort ();
bc4bd9ab 5524 }
c0f3af97
L		 5525
5526 /* The prefix bytes. */
5527 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5528 if (*q)
5529 FRAG_APPEND_1_CHAR (*q);
0f10071e 5530 }
252b5132 5531
c0f3af97
L		 5532 if (i.tm.opcode_modifier.vex)
5533 {
5534 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5535 if (*q)
5536 switch (j)
5537 {
5538 case REX_PREFIX:
5539 /* REX byte is encoded in VEX prefix. */
5540 break;
5541 case SEG_PREFIX:
5542 case ADDR_PREFIX:
5543 FRAG_APPEND_1_CHAR (*q);
5544 break;
5545 default:
5546 /* There should be no other prefixes for instructions
5547 with VEX prefix. */
5548 abort ();
5549 }
5550
5551 /* Now the VEX prefix. */
5552 p = frag_more (i.vex.length);
5553 for (j = 0; j < i.vex.length; j++)
5554 p[j] = i.vex.bytes[j];
5555 }
252b5132 5556
29b0f896 5557 /* Now the opcode; be careful about word order here! */
4dffcebc 5558 if (i.tm.opcode_length == 1)
29b0f896
AM		 5559 {
5560 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5561 }
5562 else
5563 {
4dffcebc 5564 switch (i.tm.opcode_length)
331d2d0d 5565 {
4dffcebc 5566 case 3:
331d2d0d
L		 5567 p = frag_more (3);
5568 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5569 break;
5570 case 2:
5571 p = frag_more (2);
5572 break;
5573 default:
5574 abort ();
5575 break;
331d2d0d 5576 }
0f10071e 5577
29b0f896
AM		 5578 /* Put out high byte first: can't use md_number_to_chars! */
5579 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5580 *p = i.tm.base_opcode & 0xff;
5581 }
3e73aa7c 5582
29b0f896 5583 /* Now the modrm byte and sib byte (if present). */
40fb9820 5584 if (i.tm.opcode_modifier.modrm)
29b0f896 5585 {
4a3523fa
L		 5586 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5587 | i.rm.reg << 3
5588 | i.rm.mode << 6));
29b0f896
AM		 5589 /* If i.rm.regmem == ESP (4)
5590 && i.rm.mode != (Register mode)
5591 && not 16 bit
5592 ==> need second modrm byte. */
5593 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5594 && i.rm.mode != 3
40fb9820 5595 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5596 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5597 | i.sib.index << 3
5598 | i.sib.scale << 6));
29b0f896 5599 }
3e73aa7c 5600
29b0f896 5601 if (i.disp_operands)
2bbd9c25 5602 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5603
29b0f896 5604 if (i.imm_operands)
2bbd9c25 5605 output_imm (insn_start_frag, insn_start_off);
29b0f896 5606 }
252b5132 5607
29b0f896
AM		 5608#ifdef DEBUG386
5609 if (flag_debug)
5610 {
7b81dfbb 5611 pi ("" /*line*/, &i);
29b0f896
AM		 5612 }
5613#endif /* DEBUG386 */
5614}
252b5132 5615
e205caa7
L		 5616/* Return the size of the displacement operand N. */
5617
5618static int
5619disp_size (unsigned int n)
5620{
5621 int size = 4;
40fb9820
L		 5622 if (i.types[n].bitfield.disp64)
5623 size = 8;
5624 else if (i.types[n].bitfield.disp8)
5625 size = 1;
5626 else if (i.types[n].bitfield.disp16)
5627 size = 2;
e205caa7
L		 5628 return size;
5629}
5630
5631/* Return the size of the immediate operand N. */
5632
5633static int
5634imm_size (unsigned int n)
5635{
5636 int size = 4;
40fb9820
L		 5637 if (i.types[n].bitfield.imm64)
5638 size = 8;
5639 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5640 size = 1;
5641 else if (i.types[n].bitfield.imm16)
5642 size = 2;
e205caa7
L		 5643 return size;
5644}
5645
29b0f896 5646static void
64e74474 5647output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5648{
5649 char *p;
5650 unsigned int n;
252b5132 5651
29b0f896
AM		 5652 for (n = 0; n < i.operands; n++)
5653 {
40fb9820 5654 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5655 {
5656 if (i.op[n].disps->X_op == O_constant)
5657 {
e205caa7 5658 int size = disp_size (n);
29b0f896 5659 offsetT val;
252b5132 5660
29b0f896
AM		 5661 val = offset_in_range (i.op[n].disps->X_add_number,
5662 size);
5663 p = frag_more (size);
5664 md_number_to_chars (p, val, size);
5665 }
5666 else
5667 {
f86103b7 5668 enum bfd_reloc_code_real reloc_type;
e205caa7 5669 int size = disp_size (n);
40fb9820 5670 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5671 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5672
e205caa7 5673 /* We can't have 8 bit displacement here. */
9c2799c2 5674 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5675
29b0f896
AM		 5676 /* The PC relative address is computed relative
5677 to the instruction boundary, so in case immediate
5678 fields follows, we need to adjust the value. */
5679 if (pcrel && i.imm_operands)
5680 {
29b0f896 5681 unsigned int n1;
e205caa7 5682 int sz = 0;
252b5132 5683
29b0f896 5684 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5685 if (operand_type_check (i.types[n1], imm))
252b5132 5686 {
e205caa7
L		 5687 /* Only one immediate is allowed for PC
5688 relative address. */
9c2799c2 5689 gas_assert (sz == 0);
e205caa7
L		 5690 sz = imm_size (n1);
5691 i.op[n].disps->X_add_number -= sz;
252b5132 5692 }
29b0f896 5693 /* We should find the immediate. */
9c2799c2 5694 gas_assert (sz != 0);
29b0f896 5695 }
520dc8e8 5696
29b0f896 5697 p = frag_more (size);
2bbd9c25 5698 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5699 if (GOT_symbol
2bbd9c25 5700 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5701 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5702 || reloc_type == BFD_RELOC_X86_64_32S
5703 || (reloc_type == BFD_RELOC_64
5704 && object_64bit))
d6ab8113
JB		 5705 && (i.op[n].disps->X_op == O_symbol
5706 || (i.op[n].disps->X_op == O_add
5707 && ((symbol_get_value_expression
5708 (i.op[n].disps->X_op_symbol)->X_op)
5709 == O_subtract))))
5710 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5711 {
5712 offsetT add;
5713
5714 if (insn_start_frag == frag_now)
5715 add = (p - frag_now->fr_literal) - insn_start_off;
5716 else
5717 {
5718 fragS *fr;
5719
5720 add = insn_start_frag->fr_fix - insn_start_off;
5721 for (fr = insn_start_frag->fr_next;
5722 fr && fr != frag_now; fr = fr->fr_next)
5723 add += fr->fr_fix;
5724 add += p - frag_now->fr_literal;
5725 }
5726
4fa24527 5727 if (!object_64bit)
7b81dfbb
AJ		 5728 {
5729 reloc_type = BFD_RELOC_386_GOTPC;
5730 i.op[n].imms->X_add_number += add;
5731 }
5732 else if (reloc_type == BFD_RELOC_64)
5733 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5734 else
7b81dfbb
AJ		 5735 /* Don't do the adjustment for x86-64, as there
5736 the pcrel addressing is relative to the _next_
5737 insn, and that is taken care of in other code. */
d6ab8113 5738 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5739 }
062cd5e7 5740 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5741 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5742 }
5743 }
5744 }
5745}
252b5132 5746
29b0f896 5747static void
64e74474 5748output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5749{
5750 char *p;
5751 unsigned int n;
252b5132 5752
29b0f896
AM		 5753 for (n = 0; n < i.operands; n++)
5754 {
40fb9820 5755 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5756 {
5757 if (i.op[n].imms->X_op == O_constant)
5758 {
e205caa7 5759 int size = imm_size (n);
29b0f896 5760 offsetT val;
b4cac588 5761
29b0f896
AM		 5762 val = offset_in_range (i.op[n].imms->X_add_number,
5763 size);
5764 p = frag_more (size);
5765 md_number_to_chars (p, val, size);
5766 }
5767 else
5768 {
5769 /* Not absolute_section.
5770 Need a 32-bit fixup (don't support 8bit
5771 non-absolute imms). Try to support other
5772 sizes ... */
f86103b7 5773 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5774 int size = imm_size (n);
5775 int sign;
29b0f896 5776
40fb9820 5777 if (i.types[n].bitfield.imm32s
a7d61044 5778 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5779 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5780 sign = 1;
e205caa7
L		 5781 else
5782 sign = 0;
520dc8e8 5783
29b0f896
AM		 5784 p = frag_more (size);
5785 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5786
2bbd9c25
JJ		 5787 /* This is tough to explain. We end up with this one if we
5788 * have operands that look like
5789 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5790 * obtain the absolute address of the GOT, and it is strongly
5791 * preferable from a performance point of view to avoid using
5792 * a runtime relocation for this. The actual sequence of
5793 * instructions often look something like:
5794 *
5795 * call .L66
5796 * .L66:
5797 * popl %ebx
5798 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5799 *
5800 * The call and pop essentially return the absolute address
5801 * of the label .L66 and store it in %ebx. The linker itself
5802 * will ultimately change the first operand of the addl so
5803 * that %ebx points to the GOT, but to keep things simple, the
5804 * .o file must have this operand set so that it generates not
5805 * the absolute address of .L66, but the absolute address of
5806 * itself. This allows the linker itself simply treat a GOTPC
5807 * relocation as asking for a pcrel offset to the GOT to be
5808 * added in, and the addend of the relocation is stored in the
5809 * operand field for the instruction itself.
5810 *
5811 * Our job here is to fix the operand so that it would add
5812 * the correct offset so that %ebx would point to itself. The
5813 * thing that is tricky is that .-.L66 will point to the
5814 * beginning of the instruction, so we need to further modify
5815 * the operand so that it will point to itself. There are
5816 * other cases where you have something like:
5817 *
5818 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5819 *
5820 * and here no correction would be required. Internally in
5821 * the assembler we treat operands of this form as not being
5822 * pcrel since the '.' is explicitly mentioned, and I wonder
5823 * whether it would simplify matters to do it this way. Who
5824 * knows. In earlier versions of the PIC patches, the
5825 * pcrel_adjust field was used to store the correction, but
5826 * since the expression is not pcrel, I felt it would be
5827 * confusing to do it this way. */
5828
d6ab8113 5829 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5830 || reloc_type == BFD_RELOC_X86_64_32S
5831 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5832 && GOT_symbol
5833 && GOT_symbol == i.op[n].imms->X_add_symbol
5834 && (i.op[n].imms->X_op == O_symbol
5835 || (i.op[n].imms->X_op == O_add
5836 && ((symbol_get_value_expression
5837 (i.op[n].imms->X_op_symbol)->X_op)
5838 == O_subtract))))
5839 {
2bbd9c25
JJ		 5840 offsetT add;
5841
5842 if (insn_start_frag == frag_now)
5843 add = (p - frag_now->fr_literal) - insn_start_off;
5844 else
5845 {
5846 fragS *fr;
5847
5848 add = insn_start_frag->fr_fix - insn_start_off;
5849 for (fr = insn_start_frag->fr_next;
5850 fr && fr != frag_now; fr = fr->fr_next)
5851 add += fr->fr_fix;
5852 add += p - frag_now->fr_literal;
5853 }
5854
4fa24527 5855 if (!object_64bit)
d6ab8113 5856 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5857 else if (size == 4)
d6ab8113 5858 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5859 else if (size == 8)
5860 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5861 i.op[n].imms->X_add_number += add;
29b0f896 5862 }
29b0f896
AM		 5863 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5864 i.op[n].imms, 0, reloc_type);
5865 }
5866 }
5867 }
252b5132
RH		 5868}
5869\f
d182319b
JB		 5870/* x86_cons_fix_new is called via the expression parsing code when a
5871 reloc is needed. We use this hook to get the correct .got reloc. */
5872static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5873static int cons_sign = -1;
5874
5875void
e3bb37b5 5876x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5877 expressionS *exp)
d182319b
JB		 5878{
5879 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5880
5881 got_reloc = NO_RELOC;
5882
5883#ifdef TE_PE
5884 if (exp->X_op == O_secrel)
5885 {
5886 exp->X_op = O_symbol;
5887 r = BFD_RELOC_32_SECREL;
5888 }
5889#endif
5890
5891 fix_new_exp (frag, off, len, exp, 0, r);
5892}
5893
718ddfc0
JB		 5894#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5895# define lex_got(reloc, adjust, types) NULL
5896#else
f3c180ae
AM		 5897/* Parse operands of the form
5898 <symbol>@GOTOFF+<nnn>
5899 and similar .plt or .got references.
5900
5901 If we find one, set up the correct relocation in RELOC and copy the
5902 input string, minus the `@GOTOFF' into a malloc'd buffer for
5903 parsing by the calling routine. Return this buffer, and if ADJUST
5904 is non-null set it to the length of the string we removed from the
5905 input line. Otherwise return NULL. */
5906static char *
3956db08 5907lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5908 int *adjust,
40fb9820 5909 i386_operand_type *types)
f3c180ae 5910{
7b81dfbb
AJ		 5911 /* Some of the relocations depend on the size of what field is to
5912 be relocated. But in our callers i386_immediate and i386_displacement
5913 we don't yet know the operand size (this will be set by insn
5914 matching). Hence we record the word32 relocation here,
5915 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5916 static const struct {
5917 const char *str;
4fa24527 5918 const enum bfd_reloc_code_real rel[2];
40fb9820 5919 const i386_operand_type types64;
f3c180ae 5920 } gotrel[] = {
4eed87de
AM		 5921 { "PLTOFF", { 0,
5922 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5923 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5924 { "PLT", { BFD_RELOC_386_PLT32,
5925 BFD_RELOC_X86_64_PLT32 },
40fb9820 5926 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5927 { "GOTPLT", { 0,
5928 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5929 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5930 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5931 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5932 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5933 { "GOTPCREL", { 0,
5934 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5935 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5936 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5937 BFD_RELOC_X86_64_TLSGD },
40fb9820 5938 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5939 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5940 0 },
40fb9820 5941 OPERAND_TYPE_NONE },
4eed87de
AM		 5942 { "TLSLD", { 0,
5943 BFD_RELOC_X86_64_TLSLD },
40fb9820 5944 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5945 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5946 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5947 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5948 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5949 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5950 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5951 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5952 0 },
40fb9820 5953 OPERAND_TYPE_NONE },
4eed87de
AM		 5954 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5955 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 5956
40fb9820 5957 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5958 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5959 0 },
40fb9820 5960 OPERAND_TYPE_NONE },
4eed87de
AM		 5961 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5962 0 },
40fb9820 5963 OPERAND_TYPE_NONE },
4eed87de
AM		 5964 { "GOT", { BFD_RELOC_386_GOT32,
5965 BFD_RELOC_X86_64_GOT32 },
40fb9820 5966 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5967 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5968 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5969 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5970 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5971 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5972 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5973 };
5974 char *cp;
5975 unsigned int j;
5976
718ddfc0
JB		 5977 if (!IS_ELF)
5978 return NULL;
5979
f3c180ae 5980 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5981 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5982 return NULL;
5983
47465058 5984 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5985 {
5986 int len;
5987
5988 len = strlen (gotrel[j].str);
28f81592 5989 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5990 {
4fa24527 5991 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5992 {
28f81592
AM		 5993 int first, second;
5994 char *tmpbuf, *past_reloc;
f3c180ae 5995
4fa24527 5996 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5997 if (adjust)
5998 *adjust = len;
f3c180ae 5999
3956db08
JB		 6000 if (types)
6001 {
6002 if (flag_code != CODE_64BIT)
40fb9820
L		 6003 {
6004 types->bitfield.imm32 = 1;
6005 types->bitfield.disp32 = 1;
6006 }
3956db08
JB		 6007 else
6008 *types = gotrel[j].types64;
6009 }
6010
f3c180ae
AM		 6011 if (GOT_symbol == NULL)
6012 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6013
28f81592 6014 /* The length of the first part of our input line. */
f3c180ae 6015 first = cp - input_line_pointer;
28f81592
AM		 6016
6017 /* The second part goes from after the reloc token until
67c11a9b 6018 (and including) an end_of_line char or comma. */
28f81592 6019 past_reloc = cp + 1 + len;
67c11a9b
AM		 6020 cp = past_reloc;
6021 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6022 ++cp;
6023 second = cp + 1 - past_reloc;
28f81592
AM		 6024
6025 /* Allocate and copy string. The trailing NUL shouldn't
6026 be necessary, but be safe. */
6027 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6028 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6029 if (second != 0 && *past_reloc != ' ')
6030 /* Replace the relocation token with ' ', so that
6031 errors like foo@GOTOFF1 will be detected. */
6032 tmpbuf[first++] = ' ';
6033 memcpy (tmpbuf + first, past_reloc, second);
6034 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6035 return tmpbuf;
6036 }
6037
4fa24527
JB		 6038 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6039 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6040 return NULL;
6041 }
6042 }
6043
6044 /* Might be a symbol version string. Don't as_bad here. */
6045 return NULL;
6046}
6047
f3c180ae 6048void
e3bb37b5 6049x86_cons (expressionS *exp, int size)
f3c180ae 6050{
ee86248c
JB		 6051 intel_syntax = -intel_syntax;
6052
4fa24527 6053 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6054 {
6055 /* Handle @GOTOFF and the like in an expression. */
6056 char *save;
6057 char *gotfree_input_line;
6058 int adjust;
6059
6060 save = input_line_pointer;
3956db08 6061 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6062 if (gotfree_input_line)
6063 input_line_pointer = gotfree_input_line;
6064
6065 expression (exp);
6066
6067 if (gotfree_input_line)
6068 {
6069 /* expression () has merrily parsed up to the end of line,
6070 or a comma - in the wrong buffer. Transfer how far
6071 input_line_pointer has moved to the right buffer. */
6072 input_line_pointer = (save
6073 + (input_line_pointer - gotfree_input_line)
6074 + adjust);
6075 free (gotfree_input_line);
3992d3b7
AM		 6076 if (exp->X_op == O_constant
6077 || exp->X_op == O_absent
6078 || exp->X_op == O_illegal
6079 || exp->X_op == O_register
6080 || exp->X_op == O_big)
6081 {
6082 char c = *input_line_pointer;
6083 *input_line_pointer = 0;
6084 as_bad (_("missing or invalid expression `%s'"), save);
6085 *input_line_pointer = c;
6086 }
f3c180ae
AM		 6087 }
6088 }
6089 else
6090 expression (exp);
ee86248c
JB		 6091
6092 intel_syntax = -intel_syntax;
6093
6094 if (intel_syntax)
6095 i386_intel_simplify (exp);
f3c180ae
AM		 6096}
6097#endif
6098
d182319b 6099static void signed_cons (int size)
6482c264 6100{
d182319b
JB		 6101 if (flag_code == CODE_64BIT)
6102 cons_sign = 1;
6103 cons (size);
6104 cons_sign = -1;
6482c264
NC		 6105}
6106
d182319b 6107#ifdef TE_PE
6482c264
NC		 6108static void
6109pe_directive_secrel (dummy)
6110 int dummy ATTRIBUTE_UNUSED;
6111{
6112 expressionS exp;
6113
6114 do
6115 {
6116 expression (&exp);
6117 if (exp.X_op == O_symbol)
6118 exp.X_op = O_secrel;
6119
6120 emit_expr (&exp, 4);
6121 }
6122 while (*input_line_pointer++ == ',');
6123
6124 input_line_pointer--;
6125 demand_empty_rest_of_line ();
6126}
6482c264
NC		 6127#endif
6128
252b5132 6129static int
70e41ade 6130i386_immediate (char *imm_start)
252b5132
RH		 6131{
6132 char *save_input_line_pointer;
f3c180ae 6133 char *gotfree_input_line;
252b5132 6134 segT exp_seg = 0;
47926f60 6135 expressionS *exp;
40fb9820
L		 6136 i386_operand_type types;
6137
0dfbf9d7 6138 operand_type_set (&types, ~0);
252b5132
RH		 6139
6140 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6141 {
31b2323c
L		 6142 as_bad (_("at most %d immediate operands are allowed"),
6143 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6144 return 0;
6145 }
6146
6147 exp = &im_expressions[i.imm_operands++];
520dc8e8 6148 i.op[this_operand].imms = exp;
252b5132
RH		 6149
6150 if (is_space_char (*imm_start))
6151 ++imm_start;
6152
6153 save_input_line_pointer = input_line_pointer;
6154 input_line_pointer = imm_start;
6155
3956db08 6156 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6157 if (gotfree_input_line)
6158 input_line_pointer = gotfree_input_line;
252b5132
RH		 6159
6160 exp_seg = expression (exp);
6161
83183c0c 6162 SKIP_WHITESPACE ();
252b5132 6163 if (*input_line_pointer)
f3c180ae 6164 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6165
6166 input_line_pointer = save_input_line_pointer;
f3c180ae 6167 if (gotfree_input_line)
ee86248c
JB		 6168 {
6169 free (gotfree_input_line);
6170
6171 if (exp->X_op == O_constant || exp->X_op == O_register)
6172 exp->X_op = O_illegal;
6173 }
6174
6175 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6176}
252b5132 6177
ee86248c
JB		 6178static int
6179i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6180 i386_operand_type types, const char *imm_start)
6181{
6182 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6183 {
3992d3b7 6184 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6185 imm_start);
3992d3b7 6186 return 0;
252b5132 6187 }
3e73aa7c 6188 else if (exp->X_op == O_constant)
252b5132 6189 {
47926f60 6190 /* Size it properly later. */
40fb9820 6191 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6192 /* If BFD64, sign extend val. */
4eed87de
AM		 6193 if (!use_rela_relocations
6194 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6195 exp->X_add_number
6196 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6197 }
4c63da97 6198#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6199 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6200 && exp_seg != absolute_section
47926f60 6201 && exp_seg != text_section
24eab124
AM		 6202 && exp_seg != data_section
6203 && exp_seg != bss_section
6204 && exp_seg != undefined_section
f86103b7 6205 && !bfd_is_com_section (exp_seg))
252b5132 6206 {
d0b47220 6207 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6208 return 0;
6209 }
6210#endif
bb8f5920
L		 6211 else if (!intel_syntax && exp->X_op == O_register)
6212 {
6213 as_bad (_("illegal immediate register operand %s"), imm_start);
6214 return 0;
6215 }
252b5132
RH		 6216 else
6217 {
6218 /* This is an address. The size of the address will be
24eab124 6219 determined later, depending on destination register,
3e73aa7c 6220 suffix, or the default for the section. */
40fb9820
L		 6221 i.types[this_operand].bitfield.imm8 = 1;
6222 i.types[this_operand].bitfield.imm16 = 1;
6223 i.types[this_operand].bitfield.imm32 = 1;
6224 i.types[this_operand].bitfield.imm32s = 1;
6225 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6226 i.types[this_operand] = operand_type_and (i.types[this_operand],
6227 types);
252b5132
RH		 6228 }
6229
6230 return 1;
6231}
6232
551c1ca1 6233static char *
e3bb37b5 6234i386_scale (char *scale)
252b5132 6235{
551c1ca1
AM		 6236 offsetT val;
6237 char *save = input_line_pointer;
252b5132 6238
551c1ca1
AM		 6239 input_line_pointer = scale;
6240 val = get_absolute_expression ();
6241
6242 switch (val)
252b5132 6243 {
551c1ca1 6244 case 1:
252b5132
RH		 6245 i.log2_scale_factor = 0;
6246 break;
551c1ca1 6247 case 2:
252b5132
RH		 6248 i.log2_scale_factor = 1;
6249 break;
551c1ca1 6250 case 4:
252b5132
RH		 6251 i.log2_scale_factor = 2;
6252 break;
551c1ca1 6253 case 8:
252b5132
RH		 6254 i.log2_scale_factor = 3;
6255 break;
6256 default:
a724f0f4
JB		 6257 {
6258 char sep = *input_line_pointer;
6259
6260 *input_line_pointer = '\0';
6261 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6262 scale);
6263 *input_line_pointer = sep;
6264 input_line_pointer = save;
6265 return NULL;
6266 }
252b5132 6267 }
29b0f896 6268 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6269 {
6270 as_warn (_("scale factor of %d without an index register"),
24eab124 6271 1 << i.log2_scale_factor);
252b5132 6272 i.log2_scale_factor = 0;
252b5132 6273 }
551c1ca1
AM		 6274 scale = input_line_pointer;
6275 input_line_pointer = save;
6276 return scale;
252b5132
RH		 6277}
6278
252b5132 6279static int
e3bb37b5 6280i386_displacement (char *disp_start, char *disp_end)
252b5132 6281{
29b0f896 6282 expressionS *exp;
252b5132
RH		 6283 segT exp_seg = 0;
6284 char *save_input_line_pointer;
f3c180ae 6285 char *gotfree_input_line;
40fb9820
L		 6286 int override;
6287 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6288 int ret;
252b5132 6289
31b2323c
L		 6290 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6291 {
6292 as_bad (_("at most %d displacement operands are allowed"),
6293 MAX_MEMORY_OPERANDS);
6294 return 0;
6295 }
6296
0dfbf9d7 6297 operand_type_set (&bigdisp, 0);
40fb9820
L		 6298 if ((i.types[this_operand].bitfield.jumpabsolute)
6299 || (!current_templates->start->opcode_modifier.jump
6300 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6301 {
40fb9820 6302 bigdisp.bitfield.disp32 = 1;
e05278af 6303 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6304 if (flag_code == CODE_64BIT)
6305 {
6306 if (!override)
6307 {
6308 bigdisp.bitfield.disp32s = 1;
6309 bigdisp.bitfield.disp64 = 1;
6310 }
6311 }
6312 else if ((flag_code == CODE_16BIT) ^ override)
6313 {
6314 bigdisp.bitfield.disp32 = 0;
6315 bigdisp.bitfield.disp16 = 1;
6316 }
e05278af
JB		 6317 }
6318 else
6319 {
6320 /* For PC-relative branches, the width of the displacement
6321 is dependent upon data size, not address size. */
e05278af 6322 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6323 if (flag_code == CODE_64BIT)
6324 {
6325 if (override || i.suffix == WORD_MNEM_SUFFIX)
6326 bigdisp.bitfield.disp16 = 1;
6327 else
6328 {
6329 bigdisp.bitfield.disp32 = 1;
6330 bigdisp.bitfield.disp32s = 1;
6331 }
6332 }
6333 else
e05278af
JB		 6334 {
6335 if (!override)
6336 override = (i.suffix == (flag_code != CODE_16BIT
6337 ? WORD_MNEM_SUFFIX
6338 : LONG_MNEM_SUFFIX));
40fb9820
L		 6339 bigdisp.bitfield.disp32 = 1;
6340 if ((flag_code == CODE_16BIT) ^ override)
6341 {
6342 bigdisp.bitfield.disp32 = 0;
6343 bigdisp.bitfield.disp16 = 1;
6344 }
e05278af 6345 }
e05278af 6346 }
c6fb90c8
L		 6347 i.types[this_operand] = operand_type_or (i.types[this_operand],
6348 bigdisp);
252b5132
RH		 6349
6350 exp = &disp_expressions[i.disp_operands];
520dc8e8 6351 i.op[this_operand].disps = exp;
252b5132
RH		 6352 i.disp_operands++;
6353 save_input_line_pointer = input_line_pointer;
6354 input_line_pointer = disp_start;
6355 END_STRING_AND_SAVE (disp_end);
6356
6357#ifndef GCC_ASM_O_HACK
6358#define GCC_ASM_O_HACK 0
6359#endif
6360#if GCC_ASM_O_HACK
6361 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6362 if (i.types[this_operand].bitfield.baseIndex
24eab124 6363 && displacement_string_end[-1] == '+')
252b5132
RH		 6364 {
6365 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6366 constraint within gcc asm statements.
6367 For instance:
6368
6369 #define _set_tssldt_desc(n,addr,limit,type) \
6370 __asm__ __volatile__ ( \
6371 "movw %w2,%0\n\t" \
6372 "movw %w1,2+%0\n\t" \
6373 "rorl $16,%1\n\t" \
6374 "movb %b1,4+%0\n\t" \
6375 "movb %4,5+%0\n\t" \
6376 "movb $0,6+%0\n\t" \
6377 "movb %h1,7+%0\n\t" \
6378 "rorl $16,%1" \
6379 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6380
6381 This works great except that the output assembler ends
6382 up looking a bit weird if it turns out that there is
6383 no offset. You end up producing code that looks like:
6384
6385 #APP
6386 movw $235,(%eax)
6387 movw %dx,2+(%eax)
6388 rorl $16,%edx
6389 movb %dl,4+(%eax)
6390 movb $137,5+(%eax)
6391 movb $0,6+(%eax)
6392 movb %dh,7+(%eax)
6393 rorl $16,%edx
6394 #NO_APP
6395
47926f60 6396 So here we provide the missing zero. */
24eab124
AM		 6397
6398 *displacement_string_end = '0';
252b5132
RH		 6399 }
6400#endif
3956db08 6401 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6402 if (gotfree_input_line)
6403 input_line_pointer = gotfree_input_line;
252b5132 6404
24eab124 6405 exp_seg = expression (exp);
252b5132 6406
636c26b0
AM		 6407 SKIP_WHITESPACE ();
6408 if (*input_line_pointer)
6409 as_bad (_("junk `%s' after expression"), input_line_pointer);
6410#if GCC_ASM_O_HACK
6411 RESTORE_END_STRING (disp_end + 1);
6412#endif
636c26b0 6413 input_line_pointer = save_input_line_pointer;
636c26b0 6414 if (gotfree_input_line)
ee86248c
JB		 6415 {
6416 free (gotfree_input_line);
6417
6418 if (exp->X_op == O_constant || exp->X_op == O_register)
6419 exp->X_op = O_illegal;
6420 }
6421
6422 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6423
6424 RESTORE_END_STRING (disp_end);
6425
6426 return ret;
6427}
6428
6429static int
6430i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6431 i386_operand_type types, const char *disp_start)
6432{
6433 i386_operand_type bigdisp;
6434 int ret = 1;
636c26b0 6435
24eab124
AM		 6436 /* We do this to make sure that the section symbol is in
6437 the symbol table. We will ultimately change the relocation
47926f60 6438 to be relative to the beginning of the section. */
1ae12ab7 6439 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6440 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6441 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6442 {
636c26b0 6443 if (exp->X_op != O_symbol)
3992d3b7 6444 goto inv_disp;
636c26b0 6445
e5cb08ac 6446 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6447 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6448 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6449 exp->X_op = O_subtract;
6450 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6451 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6452 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6453 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6454 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6455 else
29b0f896 6456 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6457 }
252b5132 6458
3992d3b7
AM		 6459 else if (exp->X_op == O_absent
6460 || exp->X_op == O_illegal
ee86248c 6461 || exp->X_op == O_big)
2daf4fd8 6462 {
3992d3b7
AM		 6463 inv_disp:
6464 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6465 disp_start);
3992d3b7 6466 ret = 0;
2daf4fd8
AM		 6467 }
6468
4c63da97 6469#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6470 else if (exp->X_op != O_constant
6471 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6472 && exp_seg != absolute_section
6473 && exp_seg != text_section
6474 && exp_seg != data_section
6475 && exp_seg != bss_section
6476 && exp_seg != undefined_section
6477 && !bfd_is_com_section (exp_seg))
24eab124 6478 {
d0b47220 6479 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6480 ret = 0;
24eab124 6481 }
252b5132 6482#endif
3956db08 6483
40fb9820
L		 6484 /* Check if this is a displacement only operand. */
6485 bigdisp = i.types[this_operand];
6486 bigdisp.bitfield.disp8 = 0;
6487 bigdisp.bitfield.disp16 = 0;
6488 bigdisp.bitfield.disp32 = 0;
6489 bigdisp.bitfield.disp32s = 0;
6490 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6491 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6492 i.types[this_operand] = operand_type_and (i.types[this_operand],
6493 types);
3956db08 6494
3992d3b7 6495 return ret;
252b5132
RH		 6496}
6497
eecb386c 6498/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6499 Return 1 on success, 0 on a failure. */
6500
252b5132 6501static int
e3bb37b5 6502i386_index_check (const char *operand_string)
252b5132 6503{
3e73aa7c 6504 int ok;
fc0763e6 6505 const char *kind = "base/index";
24eab124 6506#if INFER_ADDR_PREFIX
eecb386c
AM		 6507 int fudged = 0;
6508
24eab124
AM		 6509 tryprefix:
6510#endif
3e73aa7c 6511 ok = 1;
fc0763e6
JB		 6512 if (current_templates->start->opcode_modifier.isstring
6513 && !current_templates->start->opcode_modifier.immext
6514 && (current_templates->end[-1].opcode_modifier.isstring
6515 || i.mem_operands))
6516 {
6517 /* Memory operands of string insns are special in that they only allow
6518 a single register (rDI, rSI, or rBX) as their memory address. */
6519 unsigned int expected;
6520
6521 kind = "string address";
6522
6523 if (current_templates->start->opcode_modifier.w)
6524 {
6525 i386_operand_type type = current_templates->end[-1].operand_types[0];
6526
6527 if (!type.bitfield.baseindex
6528 || ((!i.mem_operands != !intel_syntax)
6529 && current_templates->end[-1].operand_types[1]
6530 .bitfield.baseindex))
6531 type = current_templates->end[-1].operand_types[1];
6532 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6533 }
6534 else
6535 expected = 3 /* rBX */;
6536
6537 if (!i.base_reg || i.index_reg
6538 || operand_type_check (i.types[this_operand], disp))
6539 ok = -1;
6540 else if (!(flag_code == CODE_64BIT
6541 ? i.prefix[ADDR_PREFIX]
6542 ? i.base_reg->reg_type.bitfield.reg32
6543 : i.base_reg->reg_type.bitfield.reg64
6544 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6545 ? i.base_reg->reg_type.bitfield.reg32
6546 : i.base_reg->reg_type.bitfield.reg16))
6547 ok = 0;
6548 else if (i.base_reg->reg_num != expected)
6549 ok = -1;
6550
6551 if (ok < 0)
6552 {
6553 unsigned int j;
6554
6555 for (j = 0; j < i386_regtab_size; ++j)
6556 if ((flag_code == CODE_64BIT
6557 ? i.prefix[ADDR_PREFIX]
6558 ? i386_regtab[j].reg_type.bitfield.reg32
6559 : i386_regtab[j].reg_type.bitfield.reg64
6560 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6561 ? i386_regtab[j].reg_type.bitfield.reg32
6562 : i386_regtab[j].reg_type.bitfield.reg16)
6563 && i386_regtab[j].reg_num == expected)
6564 break;
9c2799c2 6565 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6566 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6567 operand_string,
6568 intel_syntax ? '[' : '(',
6569 register_prefix,
6570 i386_regtab[j].reg_name,
6571 intel_syntax ? ']' : ')');
6572 ok = 1;
6573 }
6574 }
6575 else if (flag_code == CODE_64BIT)
64e74474 6576 {
64e74474 6577 if ((i.base_reg
40fb9820
L		 6578 && ((i.prefix[ADDR_PREFIX] == 0
6579 && !i.base_reg->reg_type.bitfield.reg64)
6580 || (i.prefix[ADDR_PREFIX]
6581 && !i.base_reg->reg_type.bitfield.reg32))
6582 && (i.index_reg
9a04903e
JB		 6583 || i.base_reg->reg_num !=
6584 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6585 || (i.index_reg
40fb9820
L		 6586 && (!i.index_reg->reg_type.bitfield.baseindex
6587 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6588 && i.index_reg->reg_num != RegRiz
6589 && !i.index_reg->reg_type.bitfield.reg64
6590 )
40fb9820 6591 || (i.prefix[ADDR_PREFIX]
db51cc60 6592 && i.index_reg->reg_num != RegEiz
40fb9820 6593 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6594 ok = 0;
3e73aa7c
JH		 6595 }
6596 else
6597 {
6598 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6599 {
6600 /* 16bit checks. */
6601 if ((i.base_reg
40fb9820
L		 6602 && (!i.base_reg->reg_type.bitfield.reg16
6603 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6604 || (i.index_reg
40fb9820
L		 6605 && (!i.index_reg->reg_type.bitfield.reg16
6606 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6607 || !(i.base_reg
6608 && i.base_reg->reg_num < 6
6609 && i.index_reg->reg_num >= 6
6610 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6611 ok = 0;
6612 }
6613 else
e5cb08ac 6614 {
3e73aa7c
JH		 6615 /* 32bit checks. */
6616 if ((i.base_reg
40fb9820 6617 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6618 || (i.index_reg
db51cc60
L		 6619 && ((!i.index_reg->reg_type.bitfield.reg32
6620 && i.index_reg->reg_num != RegEiz)
40fb9820 6621 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6622 ok = 0;
3e73aa7c
JH		 6623 }
6624 }
6625 if (!ok)
24eab124
AM		 6626 {
6627#if INFER_ADDR_PREFIX
fc0763e6 6628 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6629 {
6630 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6631 i.prefixes += 1;
b23bac36
AM		 6632 /* Change the size of any displacement too. At most one of
6633 Disp16 or Disp32 is set.
6634 FIXME. There doesn't seem to be any real need for separate
6635 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6636 Removing them would probably clean up the code quite a lot. */
4eed87de 6637 if (flag_code != CODE_64BIT
40fb9820
L		 6638 && (i.types[this_operand].bitfield.disp16
6639 || i.types[this_operand].bitfield.disp32))
6640 i.types[this_operand]
c6fb90c8 6641 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6642 fudged = 1;
24eab124
AM		 6643 goto tryprefix;
6644 }
eecb386c 6645 if (fudged)
fc0763e6
JB		 6646 as_bad (_("`%s' is not a valid %s expression"),
6647 operand_string,
6648 kind);
eecb386c 6649 else
c388dee8 6650#endif
fc0763e6 6651 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6652 operand_string,
fc0763e6
JB		 6653 flag_code_names[i.prefix[ADDR_PREFIX]
6654 ? flag_code == CODE_32BIT
6655 ? CODE_16BIT
6656 : CODE_32BIT
6657 : flag_code],
6658 kind);
24eab124 6659 }
20f0a1fc 6660 return ok;
24eab124 6661}
252b5132 6662
fc0763e6 6663/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6664 on error. */
252b5132 6665
252b5132 6666static int
a7619375 6667i386_att_operand (char *operand_string)
252b5132 6668{
af6bdddf
AM		 6669 const reg_entry *r;
6670 char *end_op;
24eab124 6671 char *op_string = operand_string;
252b5132 6672
24eab124 6673 if (is_space_char (*op_string))
252b5132
RH		 6674 ++op_string;
6675
24eab124 6676 /* We check for an absolute prefix (differentiating,
47926f60 6677 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6678 if (*op_string == ABSOLUTE_PREFIX)
6679 {
6680 ++op_string;
6681 if (is_space_char (*op_string))
6682 ++op_string;
40fb9820 6683 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6684 }
252b5132 6685
47926f60 6686 /* Check if operand is a register. */
4d1bb795 6687 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6688 {
40fb9820
L		 6689 i386_operand_type temp;
6690
24eab124
AM		 6691 /* Check for a segment override by searching for ':' after a
6692 segment register. */
6693 op_string = end_op;
6694 if (is_space_char (*op_string))
6695 ++op_string;
40fb9820
L		 6696 if (*op_string == ':'
6697 && (r->reg_type.bitfield.sreg2
6698 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6699 {
6700 switch (r->reg_num)
6701 {
6702 case 0:
6703 i.seg[i.mem_operands] = &es;
6704 break;
6705 case 1:
6706 i.seg[i.mem_operands] = &cs;
6707 break;
6708 case 2:
6709 i.seg[i.mem_operands] = &ss;
6710 break;
6711 case 3:
6712 i.seg[i.mem_operands] = &ds;
6713 break;
6714 case 4:
6715 i.seg[i.mem_operands] = &fs;
6716 break;
6717 case 5:
6718 i.seg[i.mem_operands] = &gs;
6719 break;
6720 }
252b5132 6721
24eab124 6722 /* Skip the ':' and whitespace. */
252b5132
RH		 6723 ++op_string;
6724 if (is_space_char (*op_string))
24eab124 6725 ++op_string;
252b5132 6726
24eab124
AM		 6727 if (!is_digit_char (*op_string)
6728 && !is_identifier_char (*op_string)
6729 && *op_string != '('
6730 && *op_string != ABSOLUTE_PREFIX)
6731 {
6732 as_bad (_("bad memory operand `%s'"), op_string);
6733 return 0;
6734 }
47926f60 6735 /* Handle case of %es:*foo. */
24eab124
AM		 6736 if (*op_string == ABSOLUTE_PREFIX)
6737 {
6738 ++op_string;
6739 if (is_space_char (*op_string))
6740 ++op_string;
40fb9820 6741 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6742 }
6743 goto do_memory_reference;
6744 }
6745 if (*op_string)
6746 {
d0b47220 6747 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6748 return 0;
6749 }
40fb9820
L		 6750 temp = r->reg_type;
6751 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6752 i.types[this_operand] = operand_type_or (i.types[this_operand],
6753 temp);
7d5e4556 6754 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6755 i.op[this_operand].regs = r;
24eab124
AM		 6756 i.reg_operands++;
6757 }
af6bdddf
AM		 6758 else if (*op_string == REGISTER_PREFIX)
6759 {
6760 as_bad (_("bad register name `%s'"), op_string);
6761 return 0;
6762 }
24eab124 6763 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6764 {
24eab124 6765 ++op_string;
40fb9820 6766 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6767 {
d0b47220 6768 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6769 return 0;
6770 }
6771 if (!i386_immediate (op_string))
6772 return 0;
6773 }
6774 else if (is_digit_char (*op_string)
6775 || is_identifier_char (*op_string)
e5cb08ac 6776 || *op_string == '(')
24eab124 6777 {
47926f60 6778 /* This is a memory reference of some sort. */
af6bdddf 6779 char *base_string;
252b5132 6780
47926f60 6781 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6782 char *displacement_string_start;
6783 char *displacement_string_end;
252b5132 6784
24eab124 6785 do_memory_reference:
24eab124 6786 if ((i.mem_operands == 1
40fb9820 6787 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6788 || i.mem_operands == 2)
6789 {
6790 as_bad (_("too many memory references for `%s'"),
6791 current_templates->start->name);
6792 return 0;
6793 }
252b5132 6794
24eab124
AM		 6795 /* Check for base index form. We detect the base index form by
6796 looking for an ')' at the end of the operand, searching
6797 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6798 after the '('. */
af6bdddf 6799 base_string = op_string + strlen (op_string);
c3332e24 6800
af6bdddf
AM		 6801 --base_string;
6802 if (is_space_char (*base_string))
6803 --base_string;
252b5132 6804
47926f60 6805 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6806 displacement_string_start = op_string;
6807 displacement_string_end = base_string + 1;
252b5132 6808
24eab124
AM		 6809 if (*base_string == ')')
6810 {
af6bdddf 6811 char *temp_string;
24eab124
AM		 6812 unsigned int parens_balanced = 1;
6813 /* We've already checked that the number of left & right ()'s are
47926f60 6814 equal, so this loop will not be infinite. */
24eab124
AM		 6815 do
6816 {
6817 base_string--;
6818 if (*base_string == ')')
6819 parens_balanced++;
6820 if (*base_string == '(')
6821 parens_balanced--;
6822 }
6823 while (parens_balanced);
c3332e24 6824
af6bdddf 6825 temp_string = base_string;
c3332e24 6826
24eab124 6827 /* Skip past '(' and whitespace. */
252b5132
RH		 6828 ++base_string;
6829 if (is_space_char (*base_string))
24eab124 6830 ++base_string;
252b5132 6831
af6bdddf 6832 if (*base_string == ','
4eed87de
AM		 6833 || ((i.base_reg = parse_register (base_string, &end_op))
6834 != NULL))
252b5132 6835 {
af6bdddf 6836 displacement_string_end = temp_string;
252b5132 6837
40fb9820 6838 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6839
af6bdddf 6840 if (i.base_reg)
24eab124 6841 {
24eab124
AM		 6842 base_string = end_op;
6843 if (is_space_char (*base_string))
6844 ++base_string;
af6bdddf
AM		 6845 }
6846
6847 /* There may be an index reg or scale factor here. */
6848 if (*base_string == ',')
6849 {
6850 ++base_string;
6851 if (is_space_char (*base_string))
6852 ++base_string;
6853
4eed87de
AM		 6854 if ((i.index_reg = parse_register (base_string, &end_op))
6855 != NULL)
24eab124 6856 {
af6bdddf 6857 base_string = end_op;
24eab124
AM		 6858 if (is_space_char (*base_string))
6859 ++base_string;
af6bdddf
AM		 6860 if (*base_string == ',')
6861 {
6862 ++base_string;
6863 if (is_space_char (*base_string))
6864 ++base_string;
6865 }
e5cb08ac 6866 else if (*base_string != ')')
af6bdddf 6867 {
4eed87de
AM		 6868 as_bad (_("expecting `,' or `)' "
6869 "after index register in `%s'"),
af6bdddf
AM		 6870 operand_string);
6871 return 0;
6872 }
24eab124 6873 }
af6bdddf 6874 else if (*base_string == REGISTER_PREFIX)
24eab124 6875 {
af6bdddf 6876 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6877 return 0;
6878 }
252b5132 6879
47926f60 6880 /* Check for scale factor. */
551c1ca1 6881 if (*base_string != ')')
af6bdddf 6882 {
551c1ca1
AM		 6883 char *end_scale = i386_scale (base_string);
6884
6885 if (!end_scale)
af6bdddf 6886 return 0;
24eab124 6887
551c1ca1 6888 base_string = end_scale;
af6bdddf
AM		 6889 if (is_space_char (*base_string))
6890 ++base_string;
6891 if (*base_string != ')')
6892 {
4eed87de
AM		 6893 as_bad (_("expecting `)' "
6894 "after scale factor in `%s'"),
af6bdddf
AM		 6895 operand_string);
6896 return 0;
6897 }
6898 }
6899 else if (!i.index_reg)
24eab124 6900 {
4eed87de
AM		 6901 as_bad (_("expecting index register or scale factor "
6902 "after `,'; got '%c'"),
af6bdddf 6903 *base_string);
24eab124
AM		 6904 return 0;
6905 }
6906 }
af6bdddf 6907 else if (*base_string != ')')
24eab124 6908 {
4eed87de
AM		 6909 as_bad (_("expecting `,' or `)' "
6910 "after base register in `%s'"),
af6bdddf 6911 operand_string);
24eab124
AM		 6912 return 0;
6913 }
c3332e24 6914 }
af6bdddf 6915 else if (*base_string == REGISTER_PREFIX)
c3332e24 6916 {
af6bdddf 6917 as_bad (_("bad register name `%s'"), base_string);
24eab124 6918 return 0;
c3332e24 6919 }
24eab124
AM		 6920 }
6921
6922 /* If there's an expression beginning the operand, parse it,
6923 assuming displacement_string_start and
6924 displacement_string_end are meaningful. */
6925 if (displacement_string_start != displacement_string_end)
6926 {
6927 if (!i386_displacement (displacement_string_start,
6928 displacement_string_end))
6929 return 0;
6930 }
6931
6932 /* Special case for (%dx) while doing input/output op. */
6933 if (i.base_reg
0dfbf9d7
L		 6934 && operand_type_equal (&i.base_reg->reg_type,
6935 &reg16_inoutportreg)
24eab124
AM		 6936 && i.index_reg == 0
6937 && i.log2_scale_factor == 0
6938 && i.seg[i.mem_operands] == 0
40fb9820 6939 && !operand_type_check (i.types[this_operand], disp))
24eab124 6940 {
65da13b5 6941 i.types[this_operand] = inoutportreg;
24eab124
AM		 6942 return 1;
6943 }
6944
eecb386c
AM		 6945 if (i386_index_check (operand_string) == 0)
6946 return 0;
5c07affc 6947 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6948 i.mem_operands++;
6949 }
6950 else
ce8a8b2f
AM		 6951 {
6952 /* It's not a memory operand; argh! */
24eab124
AM		 6953 as_bad (_("invalid char %s beginning operand %d `%s'"),
6954 output_invalid (*op_string),
6955 this_operand + 1,
6956 op_string);
6957 return 0;
6958 }
47926f60 6959 return 1; /* Normal return. */
252b5132
RH		 6960}
6961\f
ee7fcc42
AM		 6962/* md_estimate_size_before_relax()
6963
6964 Called just before relax() for rs_machine_dependent frags. The x86
6965 assembler uses these frags to handle variable size jump
6966 instructions.
6967
6968 Any symbol that is now undefined will not become defined.
6969 Return the correct fr_subtype in the frag.
6970 Return the initial "guess for variable size of frag" to caller.
6971 The guess is actually the growth beyond the fixed part. Whatever
6972 we do to grow the fixed or variable part contributes to our
6973 returned value. */
6974
252b5132
RH		 6975int
6976md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6977 fragS *fragP;
6978 segT segment;
252b5132 6979{
252b5132 6980 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6981 check for un-relaxable symbols. On an ELF system, we can't relax
6982 an externally visible symbol, because it may be overridden by a
6983 shared library. */
6984 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6985#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6986 || (IS_ELF
31312f95 6987 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 6988 || S_IS_WEAK (fragP->fr_symbol)
6989 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
6990 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 6991#endif
6992#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 6993 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 6994 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 6995#endif
6996 )
252b5132 6997 {
b98ef147
AM		 6998 /* Symbol is undefined in this segment, or we need to keep a
6999 reloc so that weak symbols can be overridden. */
7000 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7001 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7002 unsigned char *opcode;
7003 int old_fr_fix;
f6af82bd 7004
ee7fcc42
AM		 7005 if (fragP->fr_var != NO_RELOC)
7006 reloc_type = fragP->fr_var;
b98ef147 7007 else if (size == 2)
f6af82bd
AM		 7008 reloc_type = BFD_RELOC_16_PCREL;
7009 else
7010 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7011
ee7fcc42
AM		 7012 old_fr_fix = fragP->fr_fix;
7013 opcode = (unsigned char *) fragP->fr_opcode;
7014
fddf5b5b 7015 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7016 {
fddf5b5b
AM		 7017 case UNCOND_JUMP:
7018 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7019 opcode[0] = 0xe9;
252b5132 7020 fragP->fr_fix += size;
062cd5e7
AS		 7021 fix_new (fragP, old_fr_fix, size,
7022 fragP->fr_symbol,
7023 fragP->fr_offset, 1,
7024 reloc_type);
252b5132
RH		 7025 break;
7026
fddf5b5b 7027 case COND_JUMP86:
412167cb
AM		 7028 if (size == 2
7029 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7030 {
7031 /* Negate the condition, and branch past an
7032 unconditional jump. */
7033 opcode[0] ^= 1;
7034 opcode[1] = 3;
7035 /* Insert an unconditional jump. */
7036 opcode[2] = 0xe9;
7037 /* We added two extra opcode bytes, and have a two byte
7038 offset. */
7039 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7040 fix_new (fragP, old_fr_fix + 2, 2,
7041 fragP->fr_symbol,
7042 fragP->fr_offset, 1,
7043 reloc_type);
fddf5b5b
AM		 7044 break;
7045 }
7046 /* Fall through. */
7047
7048 case COND_JUMP:
412167cb
AM		 7049 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7050 {
3e02c1cc
AM		 7051 fixS *fixP;
7052
412167cb 7053 fragP->fr_fix += 1;
3e02c1cc
AM		 7054 fixP = fix_new (fragP, old_fr_fix, 1,
7055 fragP->fr_symbol,
7056 fragP->fr_offset, 1,
7057 BFD_RELOC_8_PCREL);
7058 fixP->fx_signed = 1;
412167cb
AM		 7059 break;
7060 }
93c2a809 7061
24eab124 7062 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7063 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7064 opcode[1] = opcode[0] + 0x10;
f6af82bd 7065 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7066 /* We've added an opcode byte. */
7067 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7068 fix_new (fragP, old_fr_fix + 1, size,
7069 fragP->fr_symbol,
7070 fragP->fr_offset, 1,
7071 reloc_type);
252b5132 7072 break;
fddf5b5b
AM		 7073
7074 default:
7075 BAD_CASE (fragP->fr_subtype);
7076 break;
252b5132
RH		 7077 }
7078 frag_wane (fragP);
ee7fcc42 7079 return fragP->fr_fix - old_fr_fix;
252b5132 7080 }
93c2a809 7081
93c2a809
AM		 7082 /* Guess size depending on current relax state. Initially the relax
7083 state will correspond to a short jump and we return 1, because
7084 the variable part of the frag (the branch offset) is one byte
7085 long. However, we can relax a section more than once and in that
7086 case we must either set fr_subtype back to the unrelaxed state,
7087 or return the value for the appropriate branch. */
7088 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7089}
7090
47926f60
KH		 7091/* Called after relax() is finished.
7092
7093 In: Address of frag.
7094 fr_type == rs_machine_dependent.
7095 fr_subtype is what the address relaxed to.
7096
7097 Out: Any fixSs and constants are set up.
7098 Caller will turn frag into a ".space 0". */
7099
252b5132
RH		 7100void
7101md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7102 bfd *abfd ATTRIBUTE_UNUSED;
7103 segT sec ATTRIBUTE_UNUSED;
29b0f896 7104 fragS *fragP;
252b5132 7105{
29b0f896 7106 unsigned char *opcode;
252b5132 7107 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7108 offsetT target_address;
7109 offsetT opcode_address;
252b5132 7110 unsigned int extension = 0;
847f7ad4 7111 offsetT displacement_from_opcode_start;
252b5132
RH		 7112
7113 opcode = (unsigned char *) fragP->fr_opcode;
7114
47926f60 7115 /* Address we want to reach in file space. */
252b5132 7116 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7117
47926f60 7118 /* Address opcode resides at in file space. */
252b5132
RH		 7119 opcode_address = fragP->fr_address + fragP->fr_fix;
7120
47926f60 7121 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7122 displacement_from_opcode_start = target_address - opcode_address;
7123
fddf5b5b 7124 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7125 {
47926f60
KH		 7126 /* Don't have to change opcode. */
7127 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7128 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7129 }
7130 else
7131 {
7132 if (no_cond_jump_promotion
7133 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7134 as_warn_where (fragP->fr_file, fragP->fr_line,
7135 _("long jump required"));
252b5132 7136
fddf5b5b
AM		 7137 switch (fragP->fr_subtype)
7138 {
7139 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7140 extension = 4; /* 1 opcode + 4 displacement */
7141 opcode[0] = 0xe9;
7142 where_to_put_displacement = &opcode[1];
7143 break;
252b5132 7144
fddf5b5b
AM		 7145 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7146 extension = 2; /* 1 opcode + 2 displacement */
7147 opcode[0] = 0xe9;
7148 where_to_put_displacement = &opcode[1];
7149 break;
252b5132 7150
fddf5b5b
AM		 7151 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7152 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7153 extension = 5; /* 2 opcode + 4 displacement */
7154 opcode[1] = opcode[0] + 0x10;
7155 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7156 where_to_put_displacement = &opcode[2];
7157 break;
252b5132 7158
fddf5b5b
AM		 7159 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7160 extension = 3; /* 2 opcode + 2 displacement */
7161 opcode[1] = opcode[0] + 0x10;
7162 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7163 where_to_put_displacement = &opcode[2];
7164 break;
252b5132 7165
fddf5b5b
AM		 7166 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7167 extension = 4;
7168 opcode[0] ^= 1;
7169 opcode[1] = 3;
7170 opcode[2] = 0xe9;
7171 where_to_put_displacement = &opcode[3];
7172 break;
7173
7174 default:
7175 BAD_CASE (fragP->fr_subtype);
7176 break;
7177 }
252b5132 7178 }
fddf5b5b 7179
7b81dfbb
AJ		 7180 /* If size if less then four we are sure that the operand fits,
7181 but if it's 4, then it could be that the displacement is larger
7182 then -/+ 2GB. */
7183 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7184 && object_64bit
7185 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7186 + ((addressT) 1 << 31))
7187 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7188 {
7189 as_bad_where (fragP->fr_file, fragP->fr_line,
7190 _("jump target out of range"));
7191 /* Make us emit 0. */
7192 displacement_from_opcode_start = extension;
7193 }
47926f60 7194 /* Now put displacement after opcode. */
252b5132
RH		 7195 md_number_to_chars ((char *) where_to_put_displacement,
7196 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7197 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7198 fragP->fr_fix += extension;
7199}
7200\f
252b5132
RH		 7201/* Apply a fixup (fixS) to segment data, once it has been determined
7202 by our caller that we have all the info we need to fix it up.
7203
7204 On the 386, immediates, displacements, and data pointers are all in
7205 the same (little-endian) format, so we don't need to care about which
7206 we are handling. */
7207
94f592af 7208void
55cf6793 7209md_apply_fix (fixP, valP, seg)
47926f60
KH		 7210 /* The fix we're to put in. */
7211 fixS *fixP;
47926f60 7212 /* Pointer to the value of the bits. */
c6682705 7213 valueT *valP;
47926f60
KH		 7214 /* Segment fix is from. */
7215 segT seg ATTRIBUTE_UNUSED;
252b5132 7216{
94f592af 7217 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7218 valueT value = *valP;
252b5132 7219
f86103b7 7220#if !defined (TE_Mach)
93382f6d
AM		 7221 if (fixP->fx_pcrel)
7222 {
7223 switch (fixP->fx_r_type)
7224 {
5865bb77
ILT		 7225 default:
7226 break;
7227
d6ab8113
JB		 7228 case BFD_RELOC_64:
7229 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7230 break;
93382f6d 7231 case BFD_RELOC_32:
ae8887b5 7232 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7233 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7234 break;
7235 case BFD_RELOC_16:
7236 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7237 break;
7238 case BFD_RELOC_8:
7239 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7240 break;
7241 }
7242 }
252b5132 7243
a161fe53 7244 if (fixP->fx_addsy != NULL
31312f95 7245 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7246 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7247 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7248 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7249 && !use_rela_relocations)
252b5132 7250 {
31312f95
AM		 7251 /* This is a hack. There should be a better way to handle this.
7252 This covers for the fact that bfd_install_relocation will
7253 subtract the current location (for partial_inplace, PC relative
7254 relocations); see more below. */
252b5132 7255#ifndef OBJ_AOUT
718ddfc0 7256 if (IS_ELF
252b5132
RH		 7257#ifdef TE_PE
7258 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7259#endif
7260 )
7261 value += fixP->fx_where + fixP->fx_frag->fr_address;
7262#endif
7263#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7264 if (IS_ELF)
252b5132 7265 {
6539b54b 7266 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7267
6539b54b 7268 if ((sym_seg == seg
2f66722d 7269 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7270 && sym_seg != absolute_section))
c25bc9fc 7271 && !TC_FORCE_RELOCATION (fixP))
2f66722d
AM		 7272 {
7273 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7274 bfd_install_relocation subtracts them out again. I think
7275 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7276 it. FIXME. */
7277 value += fixP->fx_where + fixP->fx_frag->fr_address;
7278 }
252b5132
RH		 7279 }
7280#endif
7281#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7282 /* For some reason, the PE format does not store a
7283 section address offset for a PC relative symbol. */
7284 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7285 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7286 value += md_pcrel_from (fixP);
7287#endif
7288 }
fbeb56a4
DK		 7289#if defined (OBJ_COFF) && defined (TE_PE)
7290 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7291 {
7292 value -= S_GET_VALUE (fixP->fx_addsy);
7293 }
7294#endif
252b5132
RH		 7295
7296 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7297 and we must not disappoint it. */
252b5132 7298#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7299 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7300 switch (fixP->fx_r_type)
7301 {
7302 case BFD_RELOC_386_PLT32:
3e73aa7c 7303 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7304 /* Make the jump instruction point to the address of the operand. At
7305 runtime we merely add the offset to the actual PLT entry. */
7306 value = -4;
7307 break;
31312f95 7308
13ae64f3
JJ		 7309 case BFD_RELOC_386_TLS_GD:
7310 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7311 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7312 case BFD_RELOC_386_TLS_IE:
7313 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7314 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7315 case BFD_RELOC_X86_64_TLSGD:
7316 case BFD_RELOC_X86_64_TLSLD:
7317 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7318 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7319 value = 0; /* Fully resolved at runtime. No addend. */
7320 /* Fallthrough */
7321 case BFD_RELOC_386_TLS_LE:
7322 case BFD_RELOC_386_TLS_LDO_32:
7323 case BFD_RELOC_386_TLS_LE_32:
7324 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7325 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7326 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7327 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7328 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7329 break;
7330
67a4f2b7
AO		 7331 case BFD_RELOC_386_TLS_DESC_CALL:
7332 case BFD_RELOC_X86_64_TLSDESC_CALL:
7333 value = 0; /* Fully resolved at runtime. No addend. */
7334 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7335 fixP->fx_done = 0;
7336 return;
7337
00f7efb6
JJ		 7338 case BFD_RELOC_386_GOT32:
7339 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7340 value = 0; /* Fully resolved at runtime. No addend. */
7341 break;
47926f60
KH		 7342
7343 case BFD_RELOC_VTABLE_INHERIT:
7344 case BFD_RELOC_VTABLE_ENTRY:
7345 fixP->fx_done = 0;
94f592af 7346 return;
47926f60
KH		 7347
7348 default:
7349 break;
7350 }
7351#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7352 *valP = value;
f86103b7 7353#endif /* !defined (TE_Mach) */
3e73aa7c 7354
3e73aa7c 7355 /* Are we finished with this relocation now? */
c6682705 7356 if (fixP->fx_addsy == NULL)
3e73aa7c 7357 fixP->fx_done = 1;
fbeb56a4
DK		 7358#if defined (OBJ_COFF) && defined (TE_PE)
7359 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7360 {
7361 fixP->fx_done = 0;
7362 /* Remember value for tc_gen_reloc. */
7363 fixP->fx_addnumber = value;
7364 /* Clear out the frag for now. */
7365 value = 0;
7366 }
7367#endif
3e73aa7c
JH		 7368 else if (use_rela_relocations)
7369 {
7370 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7371 /* Remember value for tc_gen_reloc. */
7372 fixP->fx_addnumber = value;
3e73aa7c
JH		 7373 value = 0;
7374 }
f86103b7 7375
94f592af 7376 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7377}
252b5132 7378\f
252b5132 7379char *
499ac353 7380md_atof (int type, char *litP, int *sizeP)
252b5132 7381{
499ac353
NC		 7382 /* This outputs the LITTLENUMs in REVERSE order;
7383 in accord with the bigendian 386. */
7384 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7385}
7386\f
2d545b82 7387static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7388
252b5132 7389static char *
e3bb37b5 7390output_invalid (int c)
252b5132 7391{
3882b010 7392 if (ISPRINT (c))
f9f21a03
L		 7393 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7394 "'%c'", c);
252b5132 7395 else
f9f21a03 7396 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7397 "(0x%x)", (unsigned char) c);
252b5132
RH		 7398 return output_invalid_buf;
7399}
7400
af6bdddf 7401/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7402
7403static const reg_entry *
4d1bb795 7404parse_real_register (char *reg_string, char **end_op)
252b5132 7405{
af6bdddf
AM		 7406 char *s = reg_string;
7407 char *p;
252b5132
RH		 7408 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7409 const reg_entry *r;
7410
7411 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7412 if (*s == REGISTER_PREFIX)
7413 ++s;
7414
7415 if (is_space_char (*s))
7416 ++s;
7417
7418 p = reg_name_given;
af6bdddf 7419 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7420 {
7421 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7422 return (const reg_entry *) NULL;
7423 s++;
252b5132
RH		 7424 }
7425
6588847e
DN		 7426 /* For naked regs, make sure that we are not dealing with an identifier.
7427 This prevents confusing an identifier like `eax_var' with register
7428 `eax'. */
7429 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7430 return (const reg_entry *) NULL;
7431
af6bdddf 7432 *end_op = s;
252b5132
RH		 7433
7434 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7435
5f47d35b 7436 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7437 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7438 {
5f47d35b
AM		 7439 if (is_space_char (*s))
7440 ++s;
7441 if (*s == '(')
7442 {
af6bdddf 7443 ++s;
5f47d35b
AM		 7444 if (is_space_char (*s))
7445 ++s;
7446 if (*s >= '0' && *s <= '7')
7447 {
db557034 7448 int fpr = *s - '0';
af6bdddf 7449 ++s;
5f47d35b
AM		 7450 if (is_space_char (*s))
7451 ++s;
7452 if (*s == ')')
7453 {
7454 *end_op = s + 1;
db557034
AM		 7455 r = hash_find (reg_hash, "st(0)");
7456 know (r);
7457 return r + fpr;
5f47d35b 7458 }
5f47d35b 7459 }
47926f60 7460 /* We have "%st(" then garbage. */
5f47d35b
AM		 7461 return (const reg_entry *) NULL;
7462 }
7463 }
7464
a60de03c
JB		 7465 if (r == NULL || allow_pseudo_reg)
7466 return r;
7467
0dfbf9d7 7468 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7469 return (const reg_entry *) NULL;
7470
192dc9c6
JB		 7471 if ((r->reg_type.bitfield.reg32
7472 || r->reg_type.bitfield.sreg3
7473 || r->reg_type.bitfield.control
7474 || r->reg_type.bitfield.debug
7475 || r->reg_type.bitfield.test)
7476 && !cpu_arch_flags.bitfield.cpui386)
7477 return (const reg_entry *) NULL;
7478
7479 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7480 return (const reg_entry *) NULL;
7481
7482 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7483 return (const reg_entry *) NULL;
7484
40f12533
L		 7485 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7486 return (const reg_entry *) NULL;
7487
db51cc60 7488 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7489 if (!allow_index_reg
db51cc60
L		 7490 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7491 return (const reg_entry *) NULL;
7492
a60de03c
JB		 7493 if (((r->reg_flags & (RegRex64 | RegRex))
7494 || r->reg_type.bitfield.reg64)
40fb9820 7495 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7496 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7497 && flag_code != CODE_64BIT)
20f0a1fc 7498 return (const reg_entry *) NULL;
1ae00879 7499
b7240065
JB		 7500 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7501 return (const reg_entry *) NULL;
7502
252b5132
RH		 7503 return r;
7504}
4d1bb795
JB		 7505
7506/* REG_STRING starts *before* REGISTER_PREFIX. */
7507
7508static const reg_entry *
7509parse_register (char *reg_string, char **end_op)
7510{
7511 const reg_entry *r;
7512
7513 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7514 r = parse_real_register (reg_string, end_op);
7515 else
7516 r = NULL;
7517 if (!r)
7518 {
7519 char *save = input_line_pointer;
7520 char c;
7521 symbolS *symbolP;
7522
7523 input_line_pointer = reg_string;
7524 c = get_symbol_end ();
7525 symbolP = symbol_find (reg_string);
7526 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7527 {
7528 const expressionS *e = symbol_get_value_expression (symbolP);
7529
7530 know (e->X_op == O_register);
4eed87de 7531 know (e->X_add_number >= 0
c3fe08fa 7532 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7533 r = i386_regtab + e->X_add_number;
7534 *end_op = input_line_pointer;
7535 }
7536 *input_line_pointer = c;
7537 input_line_pointer = save;
7538 }
7539 return r;
7540}
7541
7542int
7543i386_parse_name (char *name, expressionS *e, char *nextcharP)
7544{
7545 const reg_entry *r;
7546 char *end = input_line_pointer;
7547
7548 *end = *nextcharP;
7549 r = parse_register (name, &input_line_pointer);
7550 if (r && end <= input_line_pointer)
7551 {
7552 *nextcharP = *input_line_pointer;
7553 *input_line_pointer = 0;
7554 e->X_op = O_register;
7555 e->X_add_number = r - i386_regtab;
7556 return 1;
7557 }
7558 input_line_pointer = end;
7559 *end = 0;
ee86248c 7560 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7561}
7562
7563void
7564md_operand (expressionS *e)
7565{
ee86248c
JB		 7566 char *end;
7567 const reg_entry *r;
4d1bb795 7568
ee86248c
JB		 7569 switch (*input_line_pointer)
7570 {
7571 case REGISTER_PREFIX:
7572 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7573 if (r)
7574 {
7575 e->X_op = O_register;
7576 e->X_add_number = r - i386_regtab;
7577 input_line_pointer = end;
7578 }
ee86248c
JB		 7579 break;
7580
7581 case '[':
9c2799c2 7582 gas_assert (intel_syntax);
ee86248c
JB		 7583 end = input_line_pointer++;
7584 expression (e);
7585 if (*input_line_pointer == ']')
7586 {
7587 ++input_line_pointer;
7588 e->X_op_symbol = make_expr_symbol (e);
7589 e->X_add_symbol = NULL;
7590 e->X_add_number = 0;
7591 e->X_op = O_index;
7592 }
7593 else
7594 {
7595 e->X_op = O_absent;
7596 input_line_pointer = end;
7597 }
7598 break;
4d1bb795
JB		 7599 }
7600}
7601
252b5132 7602\f
4cc782b5 7603#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7604const char *md_shortopts = "kVQ:sqn";
252b5132 7605#else
12b55ccc 7606const char *md_shortopts = "qn";
252b5132 7607#endif
6e0b89ee 7608
3e73aa7c 7609#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7610#define OPTION_64 (OPTION_MD_BASE + 1)
7611#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7612#define OPTION_MARCH (OPTION_MD_BASE + 3)
7613#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7614#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7615#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7616#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7617#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7618#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7619#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7620#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7621
99ad8390
NC		 7622struct option md_longopts[] =
7623{
3e73aa7c 7624 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7625#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7626 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7627 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7628#endif
b3b91714 7629 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7630 {"march", required_argument, NULL, OPTION_MARCH},
7631 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7632 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7633 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7634 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7635 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7636 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7637 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7638 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7639 {NULL, no_argument, NULL, 0}
7640};
7641size_t md_longopts_size = sizeof (md_longopts);
7642
7643int
9103f4f4 7644md_parse_option (int c, char *arg)
252b5132 7645{
9103f4f4 7646 unsigned int i;
6305a203 7647 char *arch, *next;
9103f4f4 7648
252b5132
RH		 7649 switch (c)
7650 {
12b55ccc
L		 7651 case 'n':
7652 optimize_align_code = 0;
7653 break;
7654
a38cf1db
AM		 7655 case 'q':
7656 quiet_warnings = 1;
252b5132
RH		 7657 break;
7658
7659#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7660 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7661 should be emitted or not. FIXME: Not implemented. */
7662 case 'Q':
252b5132
RH		 7663 break;
7664
7665 /* -V: SVR4 argument to print version ID. */
7666 case 'V':
7667 print_version_id ();
7668 break;
7669
a38cf1db
AM		 7670 /* -k: Ignore for FreeBSD compatibility. */
7671 case 'k':
252b5132 7672 break;
4cc782b5
ILT		 7673
7674 case 's':
7675 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7676 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7677 break;
99ad8390 7678#endif
321098a5
L		 7679#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7680 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7681 case OPTION_64:
7682 {
7683 const char **list, **l;
7684
3e73aa7c
JH		 7685 list = bfd_target_list ();
7686 for (l = list; *l != NULL; l++)
8620418b 7687 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7688 || strcmp (*l, "coff-x86-64") == 0
7689 || strcmp (*l, "pe-x86-64") == 0
7690 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7691 {
7692 default_arch = "x86_64";
7693 break;
7694 }
3e73aa7c 7695 if (*l == NULL)
6e0b89ee 7696 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7697 free (list);
7698 }
7699 break;
7700#endif
252b5132 7701
6e0b89ee
AM		 7702 case OPTION_32:
7703 default_arch = "i386";
7704 break;
7705
b3b91714
AM		 7706 case OPTION_DIVIDE:
7707#ifdef SVR4_COMMENT_CHARS
7708 {
7709 char *n, *t;
7710 const char *s;
7711
7712 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7713 t = n;
7714 for (s = i386_comment_chars; *s != '\0'; s++)
7715 if (*s != '/')
7716 *t++ = *s;
7717 *t = '\0';
7718 i386_comment_chars = n;
7719 }
7720#endif
7721 break;
7722
9103f4f4 7723 case OPTION_MARCH:
6305a203
L		 7724 arch = xstrdup (arg);
7725 do
9103f4f4 7726 {
6305a203
L		 7727 if (*arch == '.')
7728 as_fatal (_("Invalid -march= option: `%s'"), arg);
7729 next = strchr (arch, '+');
7730 if (next)
7731 *next++ = '\0';
7732 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7733 {
6305a203 7734 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7735 {
6305a203
L		 7736 /* Processor. */
7737 cpu_arch_name = cpu_arch[i].name;
7738 cpu_sub_arch_name = NULL;
7739 cpu_arch_flags = cpu_arch[i].flags;
7740 cpu_arch_isa = cpu_arch[i].type;
7741 cpu_arch_isa_flags = cpu_arch[i].flags;
7742 if (!cpu_arch_tune_set)
7743 {
7744 cpu_arch_tune = cpu_arch_isa;
7745 cpu_arch_tune_flags = cpu_arch_isa_flags;
7746 }
7747 break;
7748 }
7749 else if (*cpu_arch [i].name == '.'
7750 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7751 {
7752 /* ISA entension. */
7753 i386_cpu_flags flags;
7754 flags = cpu_flags_or (cpu_arch_flags,
7755 cpu_arch[i].flags);
0dfbf9d7 7756 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7757 {
7758 if (cpu_sub_arch_name)
7759 {
7760 char *name = cpu_sub_arch_name;
7761 cpu_sub_arch_name = concat (name,
7762 cpu_arch[i].name,
1bf57e9f 7763 (const char *) NULL);
6305a203
L		 7764 free (name);
7765 }
7766 else
7767 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7768 cpu_arch_flags = flags;
7769 }
7770 break;
ccc9c027 7771 }
9103f4f4 7772 }
6305a203
L		 7773
7774 if (i >= ARRAY_SIZE (cpu_arch))
7775 as_fatal (_("Invalid -march= option: `%s'"), arg);
7776
7777 arch = next;
9103f4f4 7778 }
6305a203 7779 while (next != NULL );
9103f4f4
L		 7780 break;
7781
7782 case OPTION_MTUNE:
7783 if (*arg == '.')
7784 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7785 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7786 {
7787 if (strcmp (arg, cpu_arch [i].name) == 0)
7788 {
ccc9c027 7789 cpu_arch_tune_set = 1;
9103f4f4
L		 7790 cpu_arch_tune = cpu_arch [i].type;
7791 cpu_arch_tune_flags = cpu_arch[i].flags;
7792 break;
7793 }
7794 }
7795 if (i >= ARRAY_SIZE (cpu_arch))
7796 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7797 break;
7798
1efbbeb4
L		 7799 case OPTION_MMNEMONIC:
7800 if (strcasecmp (arg, "att") == 0)
7801 intel_mnemonic = 0;
7802 else if (strcasecmp (arg, "intel") == 0)
7803 intel_mnemonic = 1;
7804 else
7805 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7806 break;
7807
7808 case OPTION_MSYNTAX:
7809 if (strcasecmp (arg, "att") == 0)
7810 intel_syntax = 0;
7811 else if (strcasecmp (arg, "intel") == 0)
7812 intel_syntax = 1;
7813 else
7814 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7815 break;
7816
7817 case OPTION_MINDEX_REG:
7818 allow_index_reg = 1;
7819 break;
7820
7821 case OPTION_MNAKED_REG:
7822 allow_naked_reg = 1;
7823 break;
7824
7825 case OPTION_MOLD_GCC:
7826 old_gcc = 1;
1efbbeb4
L		 7827 break;
7828
c0f3af97
L		 7829 case OPTION_MSSE2AVX:
7830 sse2avx = 1;
7831 break;
7832
daf50ae7
L		 7833 case OPTION_MSSE_CHECK:
7834 if (strcasecmp (arg, "error") == 0)
7835 sse_check = sse_check_error;
7836 else if (strcasecmp (arg, "warning") == 0)
7837 sse_check = sse_check_warning;
7838 else if (strcasecmp (arg, "none") == 0)
7839 sse_check = sse_check_none;
7840 else
7841 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
7842 break;
7843
252b5132
RH		 7844 default:
7845 return 0;
7846 }
7847 return 1;
7848}
7849
7850void
7851md_show_usage (stream)
7852 FILE *stream;
7853{
4cc782b5
ILT		 7854#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7855 fprintf (stream, _("\
a38cf1db
AM		 7856 -Q ignored\n\
7857 -V print assembler version number\n\
b3b91714
AM		 7858 -k ignored\n"));
7859#endif
7860 fprintf (stream, _("\
12b55ccc 7861 -n Do not optimize code alignment\n\
b3b91714
AM		 7862 -q quieten some warnings\n"));
7863#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7864 fprintf (stream, _("\
a38cf1db 7865 -s ignored\n"));
b3b91714 7866#endif
321098a5
L		 7867#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7868 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 7869 fprintf (stream, _("\
7870 --32/--64 generate 32bit/64bit code\n"));
7871#endif
b3b91714
AM		 7872#ifdef SVR4_COMMENT_CHARS
7873 fprintf (stream, _("\
7874 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7875#else
7876 fprintf (stream, _("\
b3b91714 7877 --divide ignored\n"));
4cc782b5 7878#endif
9103f4f4 7879 fprintf (stream, _("\
6305a203
L		 7880 -march=CPU[,+EXTENSION...]\n\
7881 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 7882 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7883 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 7884 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 7885 generic32, generic64\n\
599121aa
L		 7886 EXTENSION is combination of:\n\
7887 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695 7888 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2 7889 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
922d8de8 7890 svme, abm, padlock, fma4\n"));
6305a203 7891 fprintf (stream, _("\
2cb4f3d5
L		 7892 -mtune=CPU optimize for CPU, CPU is one of:\n\
7893 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7894 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 7895 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 7896 generic32, generic64\n"));
ba104c83 7897 fprintf (stream, _("\
c0f3af97
L		 7898 -msse2avx encode SSE instructions with VEX prefix\n"));
7899 fprintf (stream, _("\
daf50ae7
L		 7900 -msse-check=[none|error|warning]\n\
7901 check SSE instructions\n"));
7902 fprintf (stream, _("\
ba104c83
L		 7903 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7904 fprintf (stream, _("\
7905 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7906 fprintf (stream, _("\
7907 -mindex-reg support pseudo index registers\n"));
7908 fprintf (stream, _("\
7909 -mnaked-reg don't require `%%' prefix for registers\n"));
7910 fprintf (stream, _("\
7911 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7912}
7913
3e73aa7c 7914#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 7915 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 7916 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 7917
7918/* Pick the target format to use. */
7919
47926f60 7920const char *
e3bb37b5 7921i386_target_format (void)
252b5132 7922{
3e73aa7c 7923 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7924 {
7925 set_code_flag (CODE_64BIT);
0dfbf9d7 7926 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7927 {
7928 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7929 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7930 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7931 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7932 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7933 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 7934 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 7935 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 7936 cpu_arch_isa_flags.bitfield.cpusse = 1;
7937 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7938 }
0dfbf9d7 7939 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7940 {
7941 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7942 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7943 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7944 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7945 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7946 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 7947 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 7948 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 7949 cpu_arch_tune_flags.bitfield.cpusse = 1;
7950 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7951 }
9103f4f4 7952 }
3e73aa7c 7953 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7954 {
7955 set_code_flag (CODE_32BIT);
0dfbf9d7 7956 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7957 {
7958 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7959 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7960 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7961 }
0dfbf9d7 7962 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7963 {
7964 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7965 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7966 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7967 }
9103f4f4 7968 }
3e73aa7c
JH		 7969 else
7970 as_fatal (_("Unknown architecture"));
252b5132
RH		 7971 switch (OUTPUT_FLAVOR)
7972 {
321098a5 7973#if defined (TE_PE) || defined (TE_PEP)
872ce6ff 7974 case bfd_target_coff_flavour:
321098a5 7975 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
872ce6ff 7976#endif
4c63da97
AM		 7977#ifdef OBJ_MAYBE_AOUT
7978 case bfd_target_aout_flavour:
47926f60 7979 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7980#endif
7981#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7982 case bfd_target_coff_flavour:
7983 return "coff-i386";
4c63da97 7984#endif
3e73aa7c 7985#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7986 case bfd_target_elf_flavour:
3e73aa7c 7987 {
e5cb08ac 7988 if (flag_code == CODE_64BIT)
4fa24527
JB		 7989 {
7990 object_64bit = 1;
7991 use_rela_relocations = 1;
7992 }
9d7cbccd 7993 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7994 }
e57f8c65
TG		 7995#endif
7996#if defined (OBJ_MACH_O)
7997 case bfd_target_mach_o_flavour:
7998 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 7999#endif
252b5132
RH		 8000 default:
8001 abort ();
8002 return NULL;
8003 }
8004}
8005
47926f60 8006#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8007
8008#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8009void
8010i386_elf_emit_arch_note (void)
a847613f 8011{
718ddfc0 8012 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8013 {
8014 char *p;
8015 asection *seg = now_seg;
8016 subsegT subseg = now_subseg;
8017 Elf_Internal_Note i_note;
8018 Elf_External_Note e_note;
8019 asection *note_secp;
8020 int len;
8021
8022 /* Create the .note section. */
8023 note_secp = subseg_new (".note", 0);
8024 bfd_set_section_flags (stdoutput,
8025 note_secp,
8026 SEC_HAS_CONTENTS | SEC_READONLY);
8027
8028 /* Process the arch string. */
8029 len = strlen (cpu_arch_name);
8030
8031 i_note.namesz = len + 1;
8032 i_note.descsz = 0;
8033 i_note.type = NT_ARCH;
8034 p = frag_more (sizeof (e_note.namesz));
8035 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8036 p = frag_more (sizeof (e_note.descsz));
8037 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8038 p = frag_more (sizeof (e_note.type));
8039 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8040 p = frag_more (len + 1);
8041 strcpy (p, cpu_arch_name);
8042
8043 frag_align (2, 0, 0);
8044
8045 subseg_set (seg, subseg);
8046 }
8047}
8048#endif
252b5132 8049\f
252b5132
RH		 8050symbolS *
8051md_undefined_symbol (name)
8052 char *name;
8053{
18dc2407
ILT		 8054 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8055 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8056 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8057 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8058 {
8059 if (!GOT_symbol)
8060 {
8061 if (symbol_find (name))
8062 as_bad (_("GOT already in symbol table"));
8063 GOT_symbol = symbol_new (name, undefined_section,
8064 (valueT) 0, &zero_address_frag);
8065 };
8066 return GOT_symbol;
8067 }
252b5132
RH		 8068 return 0;
8069}
8070
8071/* Round up a section size to the appropriate boundary. */
47926f60 8072
252b5132
RH		 8073valueT
8074md_section_align (segment, size)
ab9da554 8075 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8076 valueT size;
8077{
4c63da97
AM		 8078#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8079 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8080 {
8081 /* For a.out, force the section size to be aligned. If we don't do
8082 this, BFD will align it for us, but it will not write out the
8083 final bytes of the section. This may be a bug in BFD, but it is
8084 easier to fix it here since that is how the other a.out targets
8085 work. */
8086 int align;
8087
8088 align = bfd_get_section_alignment (stdoutput, segment);
8089 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8090 }
252b5132
RH		 8091#endif
8092
8093 return size;
8094}
8095
8096/* On the i386, PC-relative offsets are relative to the start of the
8097 next instruction. That is, the address of the offset, plus its
8098 size, since the offset is always the last part of the insn. */
8099
8100long
e3bb37b5 8101md_pcrel_from (fixS *fixP)
252b5132
RH		 8102{
8103 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8104}
8105
8106#ifndef I386COFF
8107
8108static void
e3bb37b5 8109s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8110{
29b0f896 8111 int temp;
252b5132 8112
8a75718c
JB		 8113#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8114 if (IS_ELF)
8115 obj_elf_section_change_hook ();
8116#endif
252b5132
RH		 8117 temp = get_absolute_expression ();
8118 subseg_set (bss_section, (subsegT) temp);
8119 demand_empty_rest_of_line ();
8120}
8121
8122#endif
8123
252b5132 8124void
e3bb37b5 8125i386_validate_fix (fixS *fixp)
252b5132
RH		 8126{
8127 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8128 {
23df1078
JH		 8129 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8130 {
4fa24527 8131 if (!object_64bit)
23df1078
JH		 8132 abort ();
8133 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8134 }
8135 else
8136 {
4fa24527 8137 if (!object_64bit)
d6ab8113
JB		 8138 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8139 else
8140 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8141 }
252b5132
RH		 8142 fixp->fx_subsy = 0;
8143 }
8144}
8145
252b5132
RH		 8146arelent *
8147tc_gen_reloc (section, fixp)
ab9da554 8148 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8149 fixS *fixp;
8150{
8151 arelent *rel;
8152 bfd_reloc_code_real_type code;
8153
8154 switch (fixp->fx_r_type)
8155 {
3e73aa7c
JH		 8156 case BFD_RELOC_X86_64_PLT32:
8157 case BFD_RELOC_X86_64_GOT32:
8158 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8159 case BFD_RELOC_386_PLT32:
8160 case BFD_RELOC_386_GOT32:
8161 case BFD_RELOC_386_GOTOFF:
8162 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8163 case BFD_RELOC_386_TLS_GD:
8164 case BFD_RELOC_386_TLS_LDM:
8165 case BFD_RELOC_386_TLS_LDO_32:
8166 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8167 case BFD_RELOC_386_TLS_IE:
8168 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8169 case BFD_RELOC_386_TLS_LE_32:
8170 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8171 case BFD_RELOC_386_TLS_GOTDESC:
8172 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8173 case BFD_RELOC_X86_64_TLSGD:
8174 case BFD_RELOC_X86_64_TLSLD:
8175 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8176 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8177 case BFD_RELOC_X86_64_GOTTPOFF:
8178 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8179 case BFD_RELOC_X86_64_TPOFF64:
8180 case BFD_RELOC_X86_64_GOTOFF64:
8181 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8182 case BFD_RELOC_X86_64_GOT64:
8183 case BFD_RELOC_X86_64_GOTPCREL64:
8184 case BFD_RELOC_X86_64_GOTPC64:
8185 case BFD_RELOC_X86_64_GOTPLT64:
8186 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8187 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8188 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8189 case BFD_RELOC_RVA:
8190 case BFD_RELOC_VTABLE_ENTRY:
8191 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8192#ifdef TE_PE
8193 case BFD_RELOC_32_SECREL:
8194#endif
252b5132
RH		 8195 code = fixp->fx_r_type;
8196 break;
dbbaec26
L		 8197 case BFD_RELOC_X86_64_32S:
8198 if (!fixp->fx_pcrel)
8199 {
8200 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8201 code = fixp->fx_r_type;
8202 break;
8203 }
252b5132 8204 default:
93382f6d 8205 if (fixp->fx_pcrel)
252b5132 8206 {
93382f6d
AM		 8207 switch (fixp->fx_size)
8208 {
8209 default:
b091f402
AM		 8210 as_bad_where (fixp->fx_file, fixp->fx_line,
8211 _("can not do %d byte pc-relative relocation"),
8212 fixp->fx_size);
93382f6d
AM		 8213 code = BFD_RELOC_32_PCREL;
8214 break;
8215 case 1: code = BFD_RELOC_8_PCREL; break;
8216 case 2: code = BFD_RELOC_16_PCREL; break;
8217 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8218#ifdef BFD64
8219 case 8: code = BFD_RELOC_64_PCREL; break;
8220#endif
93382f6d
AM		 8221 }
8222 }
8223 else
8224 {
8225 switch (fixp->fx_size)
8226 {
8227 default:
b091f402
AM		 8228 as_bad_where (fixp->fx_file, fixp->fx_line,
8229 _("can not do %d byte relocation"),
8230 fixp->fx_size);
93382f6d
AM		 8231 code = BFD_RELOC_32;
8232 break;
8233 case 1: code = BFD_RELOC_8; break;
8234 case 2: code = BFD_RELOC_16; break;
8235 case 4: code = BFD_RELOC_32; break;
937149dd 8236#ifdef BFD64
3e73aa7c 8237 case 8: code = BFD_RELOC_64; break;
937149dd 8238#endif
93382f6d 8239 }
252b5132
RH		 8240 }
8241 break;
8242 }
252b5132 8243
d182319b
JB		 8244 if ((code == BFD_RELOC_32
8245 || code == BFD_RELOC_32_PCREL
8246 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8247 && GOT_symbol
8248 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8249 {
4fa24527 8250 if (!object_64bit)
d6ab8113
JB		 8251 code = BFD_RELOC_386_GOTPC;
8252 else
8253 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8254 }
7b81dfbb
AJ		 8255 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8256 && GOT_symbol
8257 && fixp->fx_addsy == GOT_symbol)
8258 {
8259 code = BFD_RELOC_X86_64_GOTPC64;
8260 }
252b5132
RH		 8261
8262 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8263 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8264 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8265
8266 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8267
3e73aa7c
JH		 8268 if (!use_rela_relocations)
8269 {
8270 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8271 vtable entry to be used in the relocation's section offset. */
8272 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8273 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8274#if defined (OBJ_COFF) && defined (TE_PE)
8275 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8276 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8277 else
8278#endif
c6682705 8279 rel->addend = 0;
3e73aa7c
JH		 8280 }
8281 /* Use the rela in 64bit mode. */
252b5132 8282 else
3e73aa7c 8283 {
062cd5e7
AS		 8284 if (!fixp->fx_pcrel)
8285 rel->addend = fixp->fx_offset;
8286 else
8287 switch (code)
8288 {
8289 case BFD_RELOC_X86_64_PLT32:
8290 case BFD_RELOC_X86_64_GOT32:
8291 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8292 case BFD_RELOC_X86_64_TLSGD:
8293 case BFD_RELOC_X86_64_TLSLD:
8294 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8295 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8296 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8297 rel->addend = fixp->fx_offset - fixp->fx_size;
8298 break;
8299 default:
8300 rel->addend = (section->vma
8301 - fixp->fx_size
8302 + fixp->fx_addnumber
8303 + md_pcrel_from (fixp));
8304 break;
8305 }
3e73aa7c
JH		 8306 }
8307
252b5132
RH		 8308 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8309 if (rel->howto == NULL)
8310 {
8311 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8312 _("cannot represent relocation type %s"),
252b5132
RH		 8313 bfd_get_reloc_code_name (code));
8314 /* Set howto to a garbage value so that we can keep going. */
8315 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8316 gas_assert (rel->howto != NULL);
252b5132
RH		 8317 }
8318
8319 return rel;
8320}
8321
ee86248c 8322#include "tc-i386-intel.c"
54cfded0 8323
a60de03c
JB		 8324void
8325tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8326{
a60de03c
JB		 8327 int saved_naked_reg;
8328 char saved_register_dot;
54cfded0 8329
a60de03c
JB		 8330 saved_naked_reg = allow_naked_reg;
8331 allow_naked_reg = 1;
8332 saved_register_dot = register_chars['.'];
8333 register_chars['.'] = '.';
8334 allow_pseudo_reg = 1;
8335 expression_and_evaluate (exp);
8336 allow_pseudo_reg = 0;
8337 register_chars['.'] = saved_register_dot;
8338 allow_naked_reg = saved_naked_reg;
8339
8340 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8341 {
a60de03c
JB		 8342 if ((addressT) exp->X_add_number < i386_regtab_size)
8343 {
8344 exp->X_op = O_constant;
8345 exp->X_add_number = i386_regtab[exp->X_add_number]
8346 .dw2_regnum[flag_code >> 1];
8347 }
8348 else
8349 exp->X_op = O_illegal;
54cfded0 8350 }
54cfded0
AM		 8351}
8352
8353void
8354tc_x86_frame_initial_instructions (void)
8355{
a60de03c
JB		 8356 static unsigned int sp_regno[2];
8357
8358 if (!sp_regno[flag_code >> 1])
8359 {
8360 char *saved_input = input_line_pointer;
8361 char sp[][4] = {"esp", "rsp"};
8362 expressionS exp;
a4447b93 8363
a60de03c
JB		 8364 input_line_pointer = sp[flag_code >> 1];
8365 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8366 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8367 sp_regno[flag_code >> 1] = exp.X_add_number;
8368 input_line_pointer = saved_input;
8369 }
a4447b93 8370
a60de03c 8371 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8372 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8373}
d2b2c203
DJ		 8374
8375int
8376i386_elf_section_type (const char *str, size_t len)
8377{
8378 if (flag_code == CODE_64BIT
8379 && len == sizeof ("unwind") - 1
8380 && strncmp (str, "unwind", 6) == 0)
8381 return SHT_X86_64_UNWIND;
8382
8383 return -1;
8384}
bb41ade5 8385
ad5fec3b
EB		 8386#ifdef TE_SOLARIS
8387void
8388i386_solaris_fix_up_eh_frame (segT sec)
8389{
8390 if (flag_code == CODE_64BIT)
8391 elf_section_type (sec) = SHT_X86_64_UNWIND;
8392}
8393#endif
8394
bb41ade5
AM		 8395#ifdef TE_PE
8396void
8397tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8398{
8399 expressionS expr;
8400
8401 expr.X_op = O_secrel;
8402 expr.X_add_symbol = symbol;
8403 expr.X_add_number = 0;
8404 emit_expr (&expr, size);
8405}
8406#endif
3b22753a
L		 8407
8408#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8409/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8410
01e1a5bc 8411bfd_vma
3b22753a
L		 8412x86_64_section_letter (int letter, char **ptr_msg)
8413{
8414 if (flag_code == CODE_64BIT)
8415 {
8416 if (letter == 'l')
8417 return SHF_X86_64_LARGE;
8418
8419 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8420 }
3b22753a 8421 else
64e74474 8422 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8423 return -1;
8424}
8425
01e1a5bc 8426bfd_vma
3b22753a
L		 8427x86_64_section_word (char *str, size_t len)
8428{
8620418b 8429 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8430 return SHF_X86_64_LARGE;
8431
8432 return -1;
8433}
8434
8435static void
8436handle_large_common (int small ATTRIBUTE_UNUSED)
8437{
8438 if (flag_code != CODE_64BIT)
8439 {
8440 s_comm_internal (0, elf_common_parse);
8441 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8442 }
8443 else
8444 {
8445 static segT lbss_section;
8446 asection *saved_com_section_ptr = elf_com_section_ptr;
8447 asection *saved_bss_section = bss_section;
8448
8449 if (lbss_section == NULL)
8450 {
8451 flagword applicable;
8452 segT seg = now_seg;
8453 subsegT subseg = now_subseg;
8454
8455 /* The .lbss section is for local .largecomm symbols. */
8456 lbss_section = subseg_new (".lbss", 0);
8457 applicable = bfd_applicable_section_flags (stdoutput);
8458 bfd_set_section_flags (stdoutput, lbss_section,
8459 applicable & SEC_ALLOC);
8460 seg_info (lbss_section)->bss = 1;
8461
8462 subseg_set (seg, subseg);
8463 }
8464
8465 elf_com_section_ptr = &_bfd_elf_large_com_section;
8466 bss_section = lbss_section;
8467
8468 s_comm_internal (0, elf_common_parse);
8469
8470 elf_com_section_ptr = saved_com_section_ptr;
8471 bss_section = saved_bss_section;
8472 }
8473}
8474#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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