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-Wimplicit-fallthrough noreturn fixes
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132 328
8325cc63
JB		 329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
252b5132
RH		 332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 338 addressing modes of this insn are encoded. */
252b5132 339 modrm_byte rm;
3e73aa7c 340 rex_byte rex;
43234a1e 341 rex_byte vrex;
252b5132 342 sib_byte sib;
c0f3af97 343 vex_prefix vex;
b6169b20 344
43234a1e
L		 345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
b6169b20 357 /* Swap operand in encoding. */
4473e004 358 unsigned int swap_operand;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
d5de92cf
L		 368 /* REP prefix. */
369 const char *rep_prefix;
370
165de32a
L		 371 /* HLE prefix. */
372 const char *hle_prefix;
42164a71 373
7e8b059b
L		 374 /* Have BND prefix. */
375 const char *bnd_prefix;
376
43234a1e
L		 377 /* Need VREX to support upper 16 registers. */
378 int need_vrex;
379
891edac4 380 /* Error message. */
a65babc9 381 enum i386_error error;
252b5132
RH		 382 };
383
384typedef struct _i386_insn i386_insn;
385
43234a1e
L		 386/* Link RC type with corresponding string, that'll be looked for in
387 asm. */
388struct RC_name
389{
390 enum rc_type type;
391 const char *name;
392 unsigned int len;
393};
394
395static const struct RC_name RC_NamesTable[] =
396{
397 { rne, STRING_COMMA_LEN ("rn-sae") },
398 { rd, STRING_COMMA_LEN ("rd-sae") },
399 { ru, STRING_COMMA_LEN ("ru-sae") },
400 { rz, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly, STRING_COMMA_LEN ("sae") },
402};
403
252b5132
RH		 404/* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 406const char extra_symbol_chars[] = "*%-([{"
252b5132 407#ifdef LEX_AT
32137342
NC		 408 "@"
409#endif
410#ifdef LEX_QM
411 "?"
252b5132 412#endif
32137342 413 ;
252b5132 414
29b0f896
AM		 415#if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 417 && !defined (TE_GNU) \
29b0f896 418 && !defined (TE_LINUX) \
8d63c93e
RM		 419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
29b0f896 421 && !defined (TE_FreeBSD) \
5b806d27 422 && !defined (TE_DragonFly) \
29b0f896 423 && !defined (TE_NetBSD)))
252b5132 424/* This array holds the chars that always start a comment. If the
b3b91714
AM		 425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427const char *i386_comment_chars = "#/";
428#define SVR4_COMMENT_CHARS 1
252b5132 429#define PREFIX_SEPARATOR '\\'
252b5132 430
b3b91714
AM		 431#else
432const char *i386_comment_chars = "#";
433#define PREFIX_SEPARATOR '/'
434#endif
435
252b5132
RH		 436/* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 440 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
252b5132 443 '/' isn't otherwise defined. */
b3b91714 444const char line_comment_chars[] = "#/";
252b5132 445
63a0b638 446const char line_separator_chars[] = ";";
252b5132 447
ce8a8b2f
AM		 448/* Chars that can be used to separate mant from exp in floating point
449 nums. */
252b5132
RH		 450const char EXP_CHARS[] = "eE";
451
ce8a8b2f
AM		 452/* Chars that mean this number is a floating point constant
453 As in 0f12.456
454 or 0d1.2345e12. */
252b5132
RH		 455const char FLT_CHARS[] = "fFdDxX";
456
ce8a8b2f 457/* Tables for lexical analysis. */
252b5132
RH		 458static char mnemonic_chars[256];
459static char register_chars[256];
460static char operand_chars[256];
461static char identifier_chars[256];
462static char digit_chars[256];
463
ce8a8b2f 464/* Lexical macros. */
252b5132
RH		 465#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466#define is_operand_char(x) (operand_chars[(unsigned char) x])
467#define is_register_char(x) (register_chars[(unsigned char) x])
468#define is_space_char(x) ((x) == ' ')
469#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470#define is_digit_char(x) (digit_chars[(unsigned char) x])
471
0234cb7c 472/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 473static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
474
475/* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
47926f60 478 assembler instruction). */
252b5132 479static char save_stack[32];
ce8a8b2f 480static char *save_stack_p;
252b5132
RH		 481#define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483#define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
485
47926f60 486/* The instruction we're assembling. */
252b5132
RH		 487static i386_insn i;
488
489/* Possible templates for current insn. */
490static const templates *current_templates;
491
31b2323c
L		 492/* Per instruction expressionS buffers: max displacements & immediates. */
493static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
494static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 495
47926f60 496/* Current operand we are working on. */
ee86248c 497static int this_operand = -1;
252b5132 498
3e73aa7c
JH		 499/* We support four different modes. FLAG_CODE variable is used to distinguish
500 these. */
501
502enum flag_code {
503 CODE_32BIT,
504 CODE_16BIT,
505 CODE_64BIT };
506
507static enum flag_code flag_code;
4fa24527 508static unsigned int object_64bit;
862be3fb 509static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 510static int use_rela_relocations = 0;
511
7af8ed2d
NC		 512#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
515
351f65ca
L		 516/* The ELF ABI to use. */
517enum x86_elf_abi
518{
519 I386_ABI,
7f56bc95
L		 520 X86_64_ABI,
521 X86_64_X32_ABI
351f65ca
L		 522};
523
524static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 525#endif
351f65ca 526
167ad85b
TG		 527#if defined (TE_PE) || defined (TE_PEP)
528/* Use big object file format. */
529static int use_big_obj = 0;
530#endif
531
8dcea932
L		 532#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533/* 1 if generating code for a shared library. */
534static int shared = 0;
535#endif
536
47926f60
KH		 537/* 1 for intel syntax,
538 0 if att syntax. */
539static int intel_syntax = 0;
252b5132 540
e89c5eaa
L		 541/* 1 for Intel64 ISA,
542 0 if AMD64 ISA. */
543static int intel64;
544
1efbbeb4
L		 545/* 1 for intel mnemonic,
546 0 if att mnemonic. */
547static int intel_mnemonic = !SYSV386_COMPAT;
548
5209009a 549/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 550static int old_gcc = OLDGCC_COMPAT;
551
a60de03c
JB		 552/* 1 if pseudo registers are permitted. */
553static int allow_pseudo_reg = 0;
554
47926f60
KH		 555/* 1 if register prefix % not required. */
556static int allow_naked_reg = 0;
252b5132 557
7e8b059b
L		 558/* 1 if the assembler should add BND prefix for all control-tranferring
559 instructions supporting it, even if this prefix wasn't specified
560 explicitly. */
561static int add_bnd_prefix = 0;
562
ba104c83 563/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 564static int allow_index_reg = 0;
565
d022bddd
IT		 566/* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568static int omit_lock_prefix = 0;
569
e4e00185
AS		 570/* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572static int avoid_fence = 0;
573
0cb4071e
L		 574/* 1 if the assembler should generate relax relocations. */
575
576static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
578
7bab8ab5 579static enum check_kind
daf50ae7 580 {
7bab8ab5
JB		 581 check_none = 0,
582 check_warning,
583 check_error
daf50ae7 584 }
7bab8ab5 585sse_check, operand_check = check_warning;
daf50ae7 586
2ca3ace5
L		 587/* Register prefix used for error message. */
588static const char *register_prefix = "%";
589
47926f60
KH		 590/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593static char stackop_size = '\0';
eecb386c 594
12b55ccc
L		 595/* Non-zero to optimize code alignment. */
596int optimize_align_code = 1;
597
47926f60
KH		 598/* Non-zero to quieten some warnings. */
599static int quiet_warnings = 0;
a38cf1db 600
47926f60
KH		 601/* CPU name. */
602static const char *cpu_arch_name = NULL;
6305a203 603static char *cpu_sub_arch_name = NULL;
a38cf1db 604
47926f60 605/* CPU feature flags. */
40fb9820
L		 606static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
607
ccc9c027
L		 608/* If we have selected a cpu we are generating instructions for. */
609static int cpu_arch_tune_set = 0;
610
9103f4f4 611/* Cpu we are generating instructions for. */
fbf3f584 612enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 613
614/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 615static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 616
ccc9c027 617/* CPU instruction set architecture used. */
fbf3f584 618enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 619
9103f4f4 620/* CPU feature flags of instruction set architecture used. */
fbf3f584 621i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 622
fddf5b5b
AM		 623/* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625static unsigned int no_cond_jump_promotion = 0;
626
c0f3af97
L		 627/* Encode SSE instructions with VEX prefix. */
628static unsigned int sse2avx;
629
539f890d
L		 630/* Encode scalar AVX instructions with specific vector length. */
631static enum
632 {
633 vex128 = 0,
634 vex256
635 } avxscalar;
636
43234a1e
L		 637/* Encode scalar EVEX LIG instructions with specific vector length. */
638static enum
639 {
640 evexl128 = 0,
641 evexl256,
642 evexl512
643 } evexlig;
644
645/* Encode EVEX WIG instructions with specific evex.w. */
646static enum
647 {
648 evexw0 = 0,
649 evexw1
650 } evexwig;
651
d3d3c6db
IT		 652/* Value to encode in EVEX RC bits, for SAE-only instructions. */
653static enum rc_type evexrcig = rne;
654
29b0f896 655/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 656static symbolS *GOT_symbol;
29b0f896 657
a4447b93
RH		 658/* The dwarf2 return column, adjusted for 32 or 64 bit. */
659unsigned int x86_dwarf2_return_column;
660
661/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662int x86_cie_data_alignment;
663
252b5132 664/* Interface to relax_segment.
fddf5b5b
AM		 665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
252b5132 668
47926f60 669/* Types. */
93c2a809
AM		 670#define UNCOND_JUMP 0
671#define COND_JUMP 1
672#define COND_JUMP86 2
fddf5b5b 673
47926f60 674/* Sizes. */
252b5132
RH		 675#define CODE16 1
676#define SMALL 0
29b0f896 677#define SMALL16 (SMALL | CODE16)
252b5132 678#define BIG 2
29b0f896 679#define BIG16 (BIG | CODE16)
252b5132
RH		 680
681#ifndef INLINE
682#ifdef __GNUC__
683#define INLINE __inline__
684#else
685#define INLINE
686#endif
687#endif
688
fddf5b5b
AM		 689#define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691#define TYPE_FROM_RELAX_STATE(s) \
692 ((s) >> 2)
693#define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 695
696/* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
703
704const relax_typeS md_relax_table[] =
705{
24eab124
AM		 706 /* The fields are:
707 1) most positive reach of this state,
708 2) most negative reach of this state,
93c2a809 709 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 710 4) which index into the table to try if we can't fit into this one. */
252b5132 711
fddf5b5b 712 /* UNCOND_JUMP states. */
93c2a809
AM		 713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
252b5132 717 {0, 0, 4, 0},
93c2a809
AM		 718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 720 {0, 0, 2, 0},
721
93c2a809
AM		 722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
727 {0, 0, 5, 0},
fddf5b5b 728 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 729 1 extra opcode byte, 2 displacement bytes. */
730 {0, 0, 3, 0},
731
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
737 {0, 0, 5, 0},
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
740 {0, 0, 4, 0}
252b5132
RH		 741};
742
9103f4f4
L		 743static const arch_entry cpu_arch[] =
744{
89507696
JB		 745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
8a2c8fef 747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 748 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 750 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 752 CPU_NONE_FLAGS, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 754 CPU_I186_FLAGS, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 756 CPU_I286_FLAGS, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 758 CPU_I386_FLAGS, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 760 CPU_I486_FLAGS, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 762 CPU_I586_FLAGS, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 764 CPU_I686_FLAGS, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 766 CPU_I586_FLAGS, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 768 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 770 CPU_P2_FLAGS, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 772 CPU_P3_FLAGS, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 774 CPU_P4_FLAGS, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 776 CPU_CORE_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 778 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 780 CPU_CORE_FLAGS, 1 },
8a2c8fef 781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 782 CPU_CORE_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 784 CPU_CORE2_FLAGS, 1 },
8a2c8fef 785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 786 CPU_CORE2_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 788 CPU_COREI7_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 790 CPU_L1OM_FLAGS, 0 },
7a9068fe 791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 792 CPU_K1OM_FLAGS, 0 },
81486035 793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 794 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 796 CPU_K6_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 798 CPU_K6_2_FLAGS, 0 },
8a2c8fef 799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 800 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 802 CPU_K8_FLAGS, 1 },
8a2c8fef 803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 804 CPU_K8_FLAGS, 0 },
8a2c8fef 805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 806 CPU_K8_FLAGS, 0 },
8a2c8fef 807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 808 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 810 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 812 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 814 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 816 CPU_BDVER4_FLAGS, 0 },
029f3522 817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 818 CPU_ZNVER1_FLAGS, 0 },
7b458c12 819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 820 CPU_BTVER1_FLAGS, 0 },
7b458c12 821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 822 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 824 CPU_8087_FLAGS, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 826 CPU_287_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 828 CPU_387_FLAGS, 0 },
1848e567
L		 829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
830 CPU_687_FLAGS, 0 },
8a2c8fef 831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 832 CPU_MMX_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 834 CPU_SSE_FLAGS, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 836 CPU_SSE2_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 838 CPU_SSE3_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 840 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 842 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 844 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 846 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 848 CPU_AVX_FLAGS, 0 },
6c30d220 849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 850 CPU_AVX2_FLAGS, 0 },
43234a1e 851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_AVX512F_FLAGS, 0 },
43234a1e 853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_AVX512CD_FLAGS, 0 },
43234a1e 855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_AVX512ER_FLAGS, 0 },
43234a1e 857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 858 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_VMX_FLAGS, 0 },
8729a6f6 867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_SMX_FLAGS, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_AES_FLAGS, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_F16C_FLAGS, 0 },
6c30d220 891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_BMI2_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_FMA_FLAGS, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_FMA4_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_XOP_FLAGS, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_LWP_FLAGS, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_MOVBE_FLAGS, 0 },
60aa667e 903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_CX16_FLAGS, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_EPT_FLAGS, 0 },
6c30d220 907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_LZCNT_FLAGS, 0 },
42164a71 909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_HLE_FLAGS, 0 },
42164a71 911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_RTM_FLAGS, 0 },
6c30d220 913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_CLFLUSH_FLAGS, 0 },
22109423 917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_NOP_FLAGS, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_SVME_FLAGS, 1 },
8a2c8fef 931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_SVME_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_ABM_FLAGS, 0 },
87973e9f 937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_BMI_FLAGS, 0 },
2a2a0f38 939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_TBM_FLAGS, 0 },
e2e1fcde 941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_ADX_FLAGS, 0 },
e2e1fcde 943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_PRFCHW_FLAGS, 0 },
5c111e37 947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SMAP_FLAGS, 0 },
7e8b059b 949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_MPX_FLAGS, 0 },
a0046408 951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_SHA_FLAGS, 0 },
963f3586 953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_SE1_FLAGS, 0 },
c5e7287a 959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_CLWB_FLAGS, 0 },
9d8596f0 961 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_PCOMMIT_FLAGS, 0 },
2cc1b5aa 963 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 965 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_AVX512VBMI_FLAGS, 0 },
029f3522 967 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_CLZERO_FLAGS, 0 },
9916071f 969 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_MWAITX_FLAGS, 0 },
8eab4136 971 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_OSPKE_FLAGS, 0 },
8bc52696 973 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 975 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
976 CPU_PTWRITE_FLAGS, 0 },
293f5f65
L		 977};
978
979static const noarch_entry cpu_noarch[] =
980{
981 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 982 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
983 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
984 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 985 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
986 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 987 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
988 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
989 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
990 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
991 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
992 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 993 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 994 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 995 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
996 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
997 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
998 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
999 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1000 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1001 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1002 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1003 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
e413e4e9
AM		 1004};
1005
704209c0 1006#ifdef I386COFF
a6c24e68
NC		 1007/* Like s_lcomm_internal in gas/read.c but the alignment string
1008 is allowed to be optional. */
1009
1010static symbolS *
1011pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1012{
1013 addressT align = 0;
1014
1015 SKIP_WHITESPACE ();
1016
7ab9ffdd 1017 if (needs_align
a6c24e68
NC		 1018 && *input_line_pointer == ',')
1019 {
1020 align = parse_align (needs_align - 1);
7ab9ffdd 1021
a6c24e68
NC		 1022 if (align == (addressT) -1)
1023 return NULL;
1024 }
1025 else
1026 {
1027 if (size >= 8)
1028 align = 3;
1029 else if (size >= 4)
1030 align = 2;
1031 else if (size >= 2)
1032 align = 1;
1033 else
1034 align = 0;
1035 }
1036
1037 bss_alloc (symbolP, size, align);
1038 return symbolP;
1039}
1040
704209c0 1041static void
a6c24e68
NC		 1042pe_lcomm (int needs_align)
1043{
1044 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1045}
704209c0 1046#endif
a6c24e68 1047
29b0f896
AM		 1048const pseudo_typeS md_pseudo_table[] =
1049{
1050#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1051 {"align", s_align_bytes, 0},
1052#else
1053 {"align", s_align_ptwo, 0},
1054#endif
1055 {"arch", set_cpu_arch, 0},
1056#ifndef I386COFF
1057 {"bss", s_bss, 0},
a6c24e68
NC		 1058#else
1059 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1060#endif
1061 {"ffloat", float_cons, 'f'},
1062 {"dfloat", float_cons, 'd'},
1063 {"tfloat", float_cons, 'x'},
1064 {"value", cons, 2},
d182319b 1065 {"slong", signed_cons, 4},
29b0f896
AM		 1066 {"noopt", s_ignore, 0},
1067 {"optim", s_ignore, 0},
1068 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1069 {"code16", set_code_flag, CODE_16BIT},
1070 {"code32", set_code_flag, CODE_32BIT},
1071 {"code64", set_code_flag, CODE_64BIT},
1072 {"intel_syntax", set_intel_syntax, 1},
1073 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1074 {"intel_mnemonic", set_intel_mnemonic, 1},
1075 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1076 {"allow_index_reg", set_allow_index_reg, 1},
1077 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1078 {"sse_check", set_check, 0},
1079 {"operand_check", set_check, 1},
3b22753a
L		 1080#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1081 {"largecomm", handle_large_common, 0},
07a53e5c 1082#else
e3bb37b5 1083 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1084 {"loc", dwarf2_directive_loc, 0},
1085 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1086#endif
6482c264
NC		 1087#ifdef TE_PE
1088 {"secrel32", pe_directive_secrel, 0},
1089#endif
29b0f896
AM		 1090 {0, 0, 0}
1091};
1092
1093/* For interface with expression (). */
1094extern char *input_line_pointer;
1095
1096/* Hash table for instruction mnemonic lookup. */
1097static struct hash_control *op_hash;
1098
1099/* Hash table for register lookup. */
1100static struct hash_control *reg_hash;
1101\f
252b5132 1102void
e3bb37b5 1103i386_align_code (fragS *fragP, int count)
252b5132 1104{
ce8a8b2f
AM		 1105 /* Various efficient no-op patterns for aligning code labels.
1106 Note: Don't try to assemble the instructions in the comments.
1107 0L and 0w are not legal. */
bad6e36d 1108 static const unsigned char f32_1[] =
252b5132 1109 {0x90}; /* nop */
bad6e36d 1110 static const unsigned char f32_2[] =
ccc9c027 1111 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1112 static const unsigned char f32_3[] =
252b5132 1113 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1114 static const unsigned char f32_4[] =
252b5132 1115 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1116 static const unsigned char f32_5[] =
252b5132
RH		 1117 {0x90, /* nop */
1118 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1119 static const unsigned char f32_6[] =
252b5132 1120 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1121 static const unsigned char f32_7[] =
252b5132 1122 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1123 static const unsigned char f32_8[] =
252b5132
RH		 1124 {0x90, /* nop */
1125 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1126 static const unsigned char f32_9[] =
252b5132
RH		 1127 {0x89,0xf6, /* movl %esi,%esi */
1128 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1129 static const unsigned char f32_10[] =
252b5132
RH		 1130 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1131 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1132 static const unsigned char f32_11[] =
252b5132
RH		 1133 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1134 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1135 static const unsigned char f32_12[] =
252b5132
RH		 1136 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1137 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1138 static const unsigned char f32_13[] =
252b5132
RH		 1139 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1140 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1141 static const unsigned char f32_14[] =
252b5132
RH		 1142 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1143 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1144 static const unsigned char f16_3[] =
c3332e24 1145 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1146 static const unsigned char f16_4[] =
252b5132 1147 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1148 static const unsigned char f16_5[] =
252b5132
RH		 1149 {0x90, /* nop */
1150 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1151 static const unsigned char f16_6[] =
252b5132
RH		 1152 {0x89,0xf6, /* mov %si,%si */
1153 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1154 static const unsigned char f16_7[] =
252b5132
RH		 1155 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1156 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1157 static const unsigned char f16_8[] =
252b5132
RH		 1158 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1159 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1160 static const unsigned char jump_31[] =
76bc74dc
L		 1161 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1162 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1163 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1164 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1165 static const unsigned char *const f32_patt[] = {
252b5132 1166 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1167 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1168 };
bad6e36d 1169 static const unsigned char *const f16_patt[] = {
76bc74dc 1170 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1171 };
ccc9c027 1172 /* nopl (%[re]ax) */
bad6e36d 1173 static const unsigned char alt_3[] =
ccc9c027
L		 1174 {0x0f,0x1f,0x00};
1175 /* nopl 0(%[re]ax) */
bad6e36d 1176 static const unsigned char alt_4[] =
ccc9c027
L		 1177 {0x0f,0x1f,0x40,0x00};
1178 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1179 static const unsigned char alt_5[] =
ccc9c027
L		 1180 {0x0f,0x1f,0x44,0x00,0x00};
1181 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1182 static const unsigned char alt_6[] =
ccc9c027
L		 1183 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1184 /* nopl 0L(%[re]ax) */
bad6e36d 1185 static const unsigned char alt_7[] =
ccc9c027
L		 1186 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1187 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1188 static const unsigned char alt_8[] =
ccc9c027
L		 1189 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1190 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1191 static const unsigned char alt_9[] =
ccc9c027
L		 1192 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1193 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1194 static const unsigned char alt_10[] =
ccc9c027 1195 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1196 static const unsigned char *const alt_patt[] = {
ccc9c027 1197 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1198 alt_9, alt_10
ccc9c027 1199 };
252b5132 1200
76bc74dc
L		 1201 /* Only align for at least a positive non-zero boundary. */
1202 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1203 return;
3e73aa7c 1204
ccc9c027
L		 1205 /* We need to decide which NOP sequence to use for 32bit and
1206 64bit. When -mtune= is used:
4eed87de 1207
76bc74dc
L		 1208 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1209 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1210 2. For the rest, alt_patt will be used.
1211
1212 When -mtune= isn't used, alt_patt will be used if
22109423 1213 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1214 be used.
ccc9c027
L		 1215
1216 When -march= or .arch is used, we can't use anything beyond
1217 cpu_arch_isa_flags. */
1218
1219 if (flag_code == CODE_16BIT)
1220 {
ccc9c027 1221 if (count > 8)
33fef721 1222 {
76bc74dc
L		 1223 memcpy (fragP->fr_literal + fragP->fr_fix,
1224 jump_31, count);
1225 /* Adjust jump offset. */
1226 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1227 }
76bc74dc
L		 1228 else
1229 memcpy (fragP->fr_literal + fragP->fr_fix,
1230 f16_patt[count - 1], count);
252b5132 1231 }
33fef721 1232 else
ccc9c027 1233 {
bad6e36d 1234 const unsigned char *const *patt = NULL;
ccc9c027 1235
fbf3f584 1236 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1237 {
1238 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1239 switch (cpu_arch_tune)
1240 {
1241 case PROCESSOR_UNKNOWN:
1242 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1243 optimize with nops. */
1244 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1245 patt = alt_patt;
ccc9c027
L		 1246 else
1247 patt = f32_patt;
1248 break;
ccc9c027
L		 1249 case PROCESSOR_PENTIUM4:
1250 case PROCESSOR_NOCONA:
ef05d495 1251 case PROCESSOR_CORE:
76bc74dc 1252 case PROCESSOR_CORE2:
bd5295b2 1253 case PROCESSOR_COREI7:
3632d14b 1254 case PROCESSOR_L1OM:
7a9068fe 1255 case PROCESSOR_K1OM:
76bc74dc 1256 case PROCESSOR_GENERIC64:
ccc9c027
L		 1257 case PROCESSOR_K6:
1258 case PROCESSOR_ATHLON:
1259 case PROCESSOR_K8:
4eed87de 1260 case PROCESSOR_AMDFAM10:
8aedb9fe 1261 case PROCESSOR_BD:
029f3522 1262 case PROCESSOR_ZNVER:
7b458c12 1263 case PROCESSOR_BT:
80b8656c 1264 patt = alt_patt;
ccc9c027 1265 break;
76bc74dc 1266 case PROCESSOR_I386:
ccc9c027
L		 1267 case PROCESSOR_I486:
1268 case PROCESSOR_PENTIUM:
2dde1948 1269 case PROCESSOR_PENTIUMPRO:
81486035 1270 case PROCESSOR_IAMCU:
ccc9c027
L		 1271 case PROCESSOR_GENERIC32:
1272 patt = f32_patt;
1273 break;
4eed87de 1274 }
ccc9c027
L		 1275 }
1276 else
1277 {
fbf3f584 1278 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1279 {
1280 case PROCESSOR_UNKNOWN:
e6a14101 1281 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1282 PROCESSOR_UNKNOWN. */
1283 abort ();
1284 break;
1285
76bc74dc 1286 case PROCESSOR_I386:
ccc9c027
L		 1287 case PROCESSOR_I486:
1288 case PROCESSOR_PENTIUM:
81486035 1289 case PROCESSOR_IAMCU:
ccc9c027
L		 1290 case PROCESSOR_K6:
1291 case PROCESSOR_ATHLON:
1292 case PROCESSOR_K8:
4eed87de 1293 case PROCESSOR_AMDFAM10:
8aedb9fe 1294 case PROCESSOR_BD:
029f3522 1295 case PROCESSOR_ZNVER:
7b458c12 1296 case PROCESSOR_BT:
ccc9c027
L		 1297 case PROCESSOR_GENERIC32:
1298 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1299 with nops. */
1300 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1301 patt = alt_patt;
ccc9c027
L		 1302 else
1303 patt = f32_patt;
1304 break;
76bc74dc
L		 1305 case PROCESSOR_PENTIUMPRO:
1306 case PROCESSOR_PENTIUM4:
1307 case PROCESSOR_NOCONA:
1308 case PROCESSOR_CORE:
ef05d495 1309 case PROCESSOR_CORE2:
bd5295b2 1310 case PROCESSOR_COREI7:
3632d14b 1311 case PROCESSOR_L1OM:
7a9068fe 1312 case PROCESSOR_K1OM:
22109423 1313 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1314 patt = alt_patt;
ccc9c027
L		 1315 else
1316 patt = f32_patt;
1317 break;
1318 case PROCESSOR_GENERIC64:
80b8656c 1319 patt = alt_patt;
ccc9c027 1320 break;
4eed87de 1321 }
ccc9c027
L		 1322 }
1323
76bc74dc
L		 1324 if (patt == f32_patt)
1325 {
1326 /* If the padding is less than 15 bytes, we use the normal
1327 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1328 its offset. */
1329 int limit;
76ba9986 1330
711eedef
L		 1331 /* For 64bit, the limit is 3 bytes. */
1332 if (flag_code == CODE_64BIT
1333 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1334 limit = 3;
1335 else
1336 limit = 15;
1337 if (count < limit)
76bc74dc
L		 1338 memcpy (fragP->fr_literal + fragP->fr_fix,
1339 patt[count - 1], count);
1340 else
1341 {
1342 memcpy (fragP->fr_literal + fragP->fr_fix,
1343 jump_31, count);
1344 /* Adjust jump offset. */
1345 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1346 }
1347 }
1348 else
1349 {
80b8656c
L		 1350 /* Maximum length of an instruction is 10 byte. If the
1351 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1352 we have to break it into smaller pieces. */
1353 int padding = count;
80b8656c 1354 while (padding > 10)
76bc74dc 1355 {
80b8656c 1356 padding -= 10;
76bc74dc 1357 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1358 patt [9], 10);
76bc74dc
L		 1359 }
1360
1361 if (padding)
1362 memcpy (fragP->fr_literal + fragP->fr_fix,
1363 patt [padding - 1], padding);
1364 }
ccc9c027 1365 }
33fef721 1366 fragP->fr_var = count;
252b5132
RH		 1367}
1368
c6fb90c8 1369static INLINE int
0dfbf9d7 1370operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1371{
0dfbf9d7 1372 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1373 {
1374 case 3:
0dfbf9d7 1375 if (x->array[2])
c6fb90c8
L		 1376 return 0;
1377 case 2:
0dfbf9d7 1378 if (x->array[1])
c6fb90c8
L		 1379 return 0;
1380 case 1:
0dfbf9d7 1381 return !x->array[0];
c6fb90c8
L		 1382 default:
1383 abort ();
1384 }
40fb9820
L		 1385}
1386
c6fb90c8 1387static INLINE void
0dfbf9d7 1388operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1389{
0dfbf9d7 1390 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1391 {
1392 case 3:
0dfbf9d7 1393 x->array[2] = v;
c6fb90c8 1394 case 2:
0dfbf9d7 1395 x->array[1] = v;
c6fb90c8 1396 case 1:
0dfbf9d7 1397 x->array[0] = v;
c6fb90c8
L		 1398 break;
1399 default:
1400 abort ();
1401 }
1402}
40fb9820 1403
c6fb90c8 1404static INLINE int
0dfbf9d7
L		 1405operand_type_equal (const union i386_operand_type *x,
1406 const union i386_operand_type *y)
c6fb90c8 1407{
0dfbf9d7 1408 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1409 {
1410 case 3:
0dfbf9d7 1411 if (x->array[2] != y->array[2])
c6fb90c8
L		 1412 return 0;
1413 case 2:
0dfbf9d7 1414 if (x->array[1] != y->array[1])
c6fb90c8
L		 1415 return 0;
1416 case 1:
0dfbf9d7 1417 return x->array[0] == y->array[0];
c6fb90c8
L		 1418 break;
1419 default:
1420 abort ();
1421 }
1422}
40fb9820 1423
0dfbf9d7
L		 1424static INLINE int
1425cpu_flags_all_zero (const union i386_cpu_flags *x)
1426{
1427 switch (ARRAY_SIZE(x->array))
1428 {
1429 case 3:
1430 if (x->array[2])
1431 return 0;
1432 case 2:
1433 if (x->array[1])
1434 return 0;
1435 case 1:
1436 return !x->array[0];
1437 default:
1438 abort ();
1439 }
1440}
1441
0dfbf9d7
L		 1442static INLINE int
1443cpu_flags_equal (const union i386_cpu_flags *x,
1444 const union i386_cpu_flags *y)
1445{
1446 switch (ARRAY_SIZE(x->array))
1447 {
1448 case 3:
1449 if (x->array[2] != y->array[2])
1450 return 0;
1451 case 2:
1452 if (x->array[1] != y->array[1])
1453 return 0;
1454 case 1:
1455 return x->array[0] == y->array[0];
1456 break;
1457 default:
1458 abort ();
1459 }
1460}
c6fb90c8
L		 1461
1462static INLINE int
1463cpu_flags_check_cpu64 (i386_cpu_flags f)
1464{
1465 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1466 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1467}
1468
c6fb90c8
L		 1469static INLINE i386_cpu_flags
1470cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1471{
c6fb90c8
L		 1472 switch (ARRAY_SIZE (x.array))
1473 {
1474 case 3:
1475 x.array [2] &= y.array [2];
1476 case 2:
1477 x.array [1] &= y.array [1];
1478 case 1:
1479 x.array [0] &= y.array [0];
1480 break;
1481 default:
1482 abort ();
1483 }
1484 return x;
1485}
40fb9820 1486
c6fb90c8
L		 1487static INLINE i386_cpu_flags
1488cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1489{
c6fb90c8 1490 switch (ARRAY_SIZE (x.array))
40fb9820 1491 {
c6fb90c8
L		 1492 case 3:
1493 x.array [2] |= y.array [2];
1494 case 2:
1495 x.array [1] |= y.array [1];
1496 case 1:
1497 x.array [0] |= y.array [0];
40fb9820
L		 1498 break;
1499 default:
1500 abort ();
1501 }
40fb9820
L		 1502 return x;
1503}
1504
309d3373
JB		 1505static INLINE i386_cpu_flags
1506cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1507{
1508 switch (ARRAY_SIZE (x.array))
1509 {
1510 case 3:
1511 x.array [2] &= ~y.array [2];
1512 case 2:
1513 x.array [1] &= ~y.array [1];
1514 case 1:
1515 x.array [0] &= ~y.array [0];
1516 break;
1517 default:
1518 abort ();
1519 }
1520 return x;
1521}
1522
c0f3af97
L		 1523#define CPU_FLAGS_ARCH_MATCH 0x1
1524#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1525#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1526#define CPU_FLAGS_PCLMUL_MATCH 0x8
1527#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1528
a5ff0eb2 1529#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1530 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1531 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1532#define CPU_FLAGS_PERFECT_MATCH \
1533 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1534
1535/* Return CPU flags match bits. */
3629bb00 1536
40fb9820 1537static int
d3ce72d0 1538cpu_flags_match (const insn_template *t)
40fb9820 1539{
c0f3af97
L		 1540 i386_cpu_flags x = t->cpu_flags;
1541 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1542
1543 x.bitfield.cpu64 = 0;
1544 x.bitfield.cpuno64 = 0;
1545
0dfbf9d7 1546 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1547 {
1548 /* This instruction is available on all archs. */
1549 match |= CPU_FLAGS_32BIT_MATCH;
1550 }
3629bb00
L		 1551 else
1552 {
c0f3af97 1553 /* This instruction is available only on some archs. */
3629bb00
L		 1554 i386_cpu_flags cpu = cpu_arch_flags;
1555
3629bb00 1556 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1557 if (!cpu_flags_all_zero (&cpu))
1558 {
a5ff0eb2
L		 1559 if (x.bitfield.cpuavx)
1560 {
ce2f5b3c 1561 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1562 if (cpu.bitfield.cpuavx)
1563 {
1564 /* Check SSE2AVX. */
1565 if (!t->opcode_modifier.sse2avx|| sse2avx)
1566 {
1567 match |= (CPU_FLAGS_ARCH_MATCH
1568 | CPU_FLAGS_AVX_MATCH);
1569 /* Check AES. */
1570 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1571 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1572 /* Check PCLMUL. */
1573 if (!x.bitfield.cpupclmul
1574 || cpu.bitfield.cpupclmul)
1575 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1576 }
1577 }
1578 else
1579 match |= CPU_FLAGS_ARCH_MATCH;
1580 }
73b090a9
L		 1581 else if (x.bitfield.cpuavx512vl)
1582 {
1583 /* Match AVX512VL. */
1584 if (cpu.bitfield.cpuavx512vl)
1585 {
1586 /* Need another match. */
1587 cpu.bitfield.cpuavx512vl = 0;
1588 if (!cpu_flags_all_zero (&cpu))
1589 match |= CPU_FLAGS_32BIT_MATCH;
1590 else
1591 match |= CPU_FLAGS_ARCH_MATCH;
1592 }
1593 else
1594 match |= CPU_FLAGS_ARCH_MATCH;
1595 }
a5ff0eb2 1596 else
c0f3af97
L		 1597 match |= CPU_FLAGS_32BIT_MATCH;
1598 }
3629bb00 1599 }
c0f3af97 1600 return match;
40fb9820
L		 1601}
1602
c6fb90c8
L		 1603static INLINE i386_operand_type
1604operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1605{
c6fb90c8
L		 1606 switch (ARRAY_SIZE (x.array))
1607 {
1608 case 3:
1609 x.array [2] &= y.array [2];
1610 case 2:
1611 x.array [1] &= y.array [1];
1612 case 1:
1613 x.array [0] &= y.array [0];
1614 break;
1615 default:
1616 abort ();
1617 }
1618 return x;
40fb9820
L		 1619}
1620
c6fb90c8
L		 1621static INLINE i386_operand_type
1622operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1623{
c6fb90c8 1624 switch (ARRAY_SIZE (x.array))
40fb9820 1625 {
c6fb90c8
L		 1626 case 3:
1627 x.array [2] |= y.array [2];
1628 case 2:
1629 x.array [1] |= y.array [1];
1630 case 1:
1631 x.array [0] |= y.array [0];
40fb9820
L		 1632 break;
1633 default:
1634 abort ();
1635 }
c6fb90c8
L		 1636 return x;
1637}
40fb9820 1638
c6fb90c8
L		 1639static INLINE i386_operand_type
1640operand_type_xor (i386_operand_type x, i386_operand_type y)
1641{
1642 switch (ARRAY_SIZE (x.array))
1643 {
1644 case 3:
1645 x.array [2] ^= y.array [2];
1646 case 2:
1647 x.array [1] ^= y.array [1];
1648 case 1:
1649 x.array [0] ^= y.array [0];
1650 break;
1651 default:
1652 abort ();
1653 }
40fb9820
L		 1654 return x;
1655}
1656
1657static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1658static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1659static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1660static const i386_operand_type inoutportreg
1661 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1662static const i386_operand_type reg16_inoutportreg
1663 = OPERAND_TYPE_REG16_INOUTPORTREG;
1664static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1665static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1666static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1667static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1668static const i386_operand_type anydisp
1669 = OPERAND_TYPE_ANYDISP;
40fb9820 1670static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1671static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1672static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1673static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1674static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1675static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1676static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1677static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1678static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1679static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1680static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1681static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1682static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1683static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1684
1685enum operand_type
1686{
1687 reg,
40fb9820
L		 1688 imm,
1689 disp,
1690 anymem
1691};
1692
c6fb90c8 1693static INLINE int
40fb9820
L		 1694operand_type_check (i386_operand_type t, enum operand_type c)
1695{
1696 switch (c)
1697 {
1698 case reg:
1699 return (t.bitfield.reg8
1700 || t.bitfield.reg16
1701 || t.bitfield.reg32
1702 || t.bitfield.reg64);
1703
40fb9820
L		 1704 case imm:
1705 return (t.bitfield.imm8
1706 || t.bitfield.imm8s
1707 || t.bitfield.imm16
1708 || t.bitfield.imm32
1709 || t.bitfield.imm32s
1710 || t.bitfield.imm64);
1711
1712 case disp:
1713 return (t.bitfield.disp8
1714 || t.bitfield.disp16
1715 || t.bitfield.disp32
1716 || t.bitfield.disp32s
1717 || t.bitfield.disp64);
1718
1719 case anymem:
1720 return (t.bitfield.disp8
1721 || t.bitfield.disp16
1722 || t.bitfield.disp32
1723 || t.bitfield.disp32s
1724 || t.bitfield.disp64
1725 || t.bitfield.baseindex);
1726
1727 default:
1728 abort ();
1729 }
2cfe26b6
AM		 1730
1731 return 0;
40fb9820
L		 1732}
1733
5c07affc
L		 1734/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1735 operand J for instruction template T. */
1736
1737static INLINE int
d3ce72d0 1738match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1739{
1740 return !((i.types[j].bitfield.byte
1741 && !t->operand_types[j].bitfield.byte)
1742 || (i.types[j].bitfield.word
1743 && !t->operand_types[j].bitfield.word)
1744 || (i.types[j].bitfield.dword
1745 && !t->operand_types[j].bitfield.dword)
1746 || (i.types[j].bitfield.qword
1747 && !t->operand_types[j].bitfield.qword));
1748}
1749
1750/* Return 1 if there is no conflict in any size on operand J for
1751 instruction template T. */
1752
1753static INLINE int
d3ce72d0 1754match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1755{
1756 return (match_reg_size (t, j)
1757 && !((i.types[j].bitfield.unspecified
af508cb9 1758 && !i.broadcast
5c07affc
L		 1759 && !t->operand_types[j].bitfield.unspecified)
1760 || (i.types[j].bitfield.fword
1761 && !t->operand_types[j].bitfield.fword)
1762 || (i.types[j].bitfield.tbyte
1763 && !t->operand_types[j].bitfield.tbyte)
1764 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1765 && !t->operand_types[j].bitfield.xmmword)
1766 || (i.types[j].bitfield.ymmword
43234a1e
L		 1767 && !t->operand_types[j].bitfield.ymmword)
1768 || (i.types[j].bitfield.zmmword
1769 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1770}
1771
1772/* Return 1 if there is no size conflict on any operands for
1773 instruction template T. */
1774
1775static INLINE int
d3ce72d0 1776operand_size_match (const insn_template *t)
5c07affc
L		 1777{
1778 unsigned int j;
1779 int match = 1;
1780
1781 /* Don't check jump instructions. */
1782 if (t->opcode_modifier.jump
1783 || t->opcode_modifier.jumpbyte
1784 || t->opcode_modifier.jumpdword
1785 || t->opcode_modifier.jumpintersegment)
1786 return match;
1787
1788 /* Check memory and accumulator operand size. */
1789 for (j = 0; j < i.operands; j++)
1790 {
1791 if (t->operand_types[j].bitfield.anysize)
1792 continue;
1793
1794 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1795 {
1796 match = 0;
1797 break;
1798 }
1799
1800 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1801 {
1802 match = 0;
1803 break;
1804 }
1805 }
1806
891edac4 1807 if (match)
5c07affc 1808 return match;
891edac4
L		 1809 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1810 {
1811mismatch:
86e026a4 1812 i.error = operand_size_mismatch;
891edac4
L		 1813 return 0;
1814 }
5c07affc
L		 1815
1816 /* Check reverse. */
9c2799c2 1817 gas_assert (i.operands == 2);
5c07affc
L		 1818
1819 match = 1;
1820 for (j = 0; j < 2; j++)
1821 {
1822 if (t->operand_types[j].bitfield.acc
1823 && !match_reg_size (t, j ? 0 : 1))
891edac4 1824 goto mismatch;
5c07affc
L		 1825
1826 if (i.types[j].bitfield.mem
1827 && !match_mem_size (t, j ? 0 : 1))
891edac4 1828 goto mismatch;
5c07affc
L		 1829 }
1830
1831 return match;
1832}
1833
c6fb90c8 1834static INLINE int
40fb9820
L		 1835operand_type_match (i386_operand_type overlap,
1836 i386_operand_type given)
1837{
1838 i386_operand_type temp = overlap;
1839
1840 temp.bitfield.jumpabsolute = 0;
7d5e4556 1841 temp.bitfield.unspecified = 0;
5c07affc
L		 1842 temp.bitfield.byte = 0;
1843 temp.bitfield.word = 0;
1844 temp.bitfield.dword = 0;
1845 temp.bitfield.fword = 0;
1846 temp.bitfield.qword = 0;
1847 temp.bitfield.tbyte = 0;
1848 temp.bitfield.xmmword = 0;
c0f3af97 1849 temp.bitfield.ymmword = 0;
43234a1e 1850 temp.bitfield.zmmword = 0;
0dfbf9d7 1851 if (operand_type_all_zero (&temp))
891edac4 1852 goto mismatch;
40fb9820 1853
891edac4
L		 1854 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1855 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1856 return 1;
1857
1858mismatch:
a65babc9 1859 i.error = operand_type_mismatch;
891edac4 1860 return 0;
40fb9820
L		 1861}
1862
7d5e4556 1863/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1864 unless the expected operand type register overlap is null.
1865 Note that Acc in a template matches every size of reg. */
1866
c6fb90c8 1867static INLINE int
40fb9820
L		 1868operand_type_register_match (i386_operand_type m0,
1869 i386_operand_type g0,
1870 i386_operand_type t0,
1871 i386_operand_type m1,
1872 i386_operand_type g1,
1873 i386_operand_type t1)
1874{
1875 if (!operand_type_check (g0, reg))
1876 return 1;
1877
1878 if (!operand_type_check (g1, reg))
1879 return 1;
1880
1881 if (g0.bitfield.reg8 == g1.bitfield.reg8
1882 && g0.bitfield.reg16 == g1.bitfield.reg16
1883 && g0.bitfield.reg32 == g1.bitfield.reg32
1884 && g0.bitfield.reg64 == g1.bitfield.reg64)
1885 return 1;
1886
1887 if (m0.bitfield.acc)
1888 {
1889 t0.bitfield.reg8 = 1;
1890 t0.bitfield.reg16 = 1;
1891 t0.bitfield.reg32 = 1;
1892 t0.bitfield.reg64 = 1;
1893 }
1894
1895 if (m1.bitfield.acc)
1896 {
1897 t1.bitfield.reg8 = 1;
1898 t1.bitfield.reg16 = 1;
1899 t1.bitfield.reg32 = 1;
1900 t1.bitfield.reg64 = 1;
1901 }
1902
891edac4
L		 1903 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1904 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1905 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1906 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1907 return 1;
1908
a65babc9 1909 i.error = register_type_mismatch;
891edac4
L		 1910
1911 return 0;
40fb9820
L		 1912}
1913
4c692bc7
JB		 1914static INLINE unsigned int
1915register_number (const reg_entry *r)
1916{
1917 unsigned int nr = r->reg_num;
1918
1919 if (r->reg_flags & RegRex)
1920 nr += 8;
1921
200cbe0f
L		 1922 if (r->reg_flags & RegVRex)
1923 nr += 16;
1924
4c692bc7
JB		 1925 return nr;
1926}
1927
252b5132 1928static INLINE unsigned int
40fb9820 1929mode_from_disp_size (i386_operand_type t)
252b5132 1930{
43234a1e 1931 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1932 return 1;
1933 else if (t.bitfield.disp16
1934 || t.bitfield.disp32
1935 || t.bitfield.disp32s)
1936 return 2;
1937 else
1938 return 0;
252b5132
RH		 1939}
1940
1941static INLINE int
65879393 1942fits_in_signed_byte (addressT num)
252b5132 1943{
65879393 1944 return num + 0x80 <= 0xff;
47926f60 1945}
252b5132
RH		 1946
1947static INLINE int
65879393 1948fits_in_unsigned_byte (addressT num)
252b5132 1949{
65879393 1950 return num <= 0xff;
47926f60 1951}
252b5132
RH		 1952
1953static INLINE int
65879393 1954fits_in_unsigned_word (addressT num)
252b5132 1955{
65879393 1956 return num <= 0xffff;
47926f60 1957}
252b5132
RH		 1958
1959static INLINE int
65879393 1960fits_in_signed_word (addressT num)
252b5132 1961{
65879393 1962 return num + 0x8000 <= 0xffff;
47926f60 1963}
2a962e6d 1964
3e73aa7c 1965static INLINE int
65879393 1966fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1967{
1968#ifndef BFD64
1969 return 1;
1970#else
65879393 1971 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1972#endif
1973} /* fits_in_signed_long() */
2a962e6d 1974
3e73aa7c 1975static INLINE int
65879393 1976fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1977{
1978#ifndef BFD64
1979 return 1;
1980#else
65879393 1981 return num <= 0xffffffff;
3e73aa7c
JH		 1982#endif
1983} /* fits_in_unsigned_long() */
252b5132 1984
43234a1e
L		 1985static INLINE int
1986fits_in_vec_disp8 (offsetT num)
1987{
1988 int shift = i.memshift;
1989 unsigned int mask;
1990
1991 if (shift == -1)
1992 abort ();
1993
1994 mask = (1 << shift) - 1;
1995
1996 /* Return 0 if NUM isn't properly aligned. */
1997 if ((num & mask))
1998 return 0;
1999
2000 /* Check if NUM will fit in 8bit after shift. */
2001 return fits_in_signed_byte (num >> shift);
2002}
2003
a683cc34
SP		 2004static INLINE int
2005fits_in_imm4 (offsetT num)
2006{
2007 return (num & 0xf) == num;
2008}
2009
40fb9820 2010static i386_operand_type
e3bb37b5 2011smallest_imm_type (offsetT num)
252b5132 2012{
40fb9820 2013 i386_operand_type t;
7ab9ffdd 2014
0dfbf9d7 2015 operand_type_set (&t, 0);
40fb9820
L		 2016 t.bitfield.imm64 = 1;
2017
2018 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2019 {
2020 /* This code is disabled on the 486 because all the Imm1 forms
2021 in the opcode table are slower on the i486. They're the
2022 versions with the implicitly specified single-position
2023 displacement, which has another syntax if you really want to
2024 use that form. */
40fb9820
L		 2025 t.bitfield.imm1 = 1;
2026 t.bitfield.imm8 = 1;
2027 t.bitfield.imm8s = 1;
2028 t.bitfield.imm16 = 1;
2029 t.bitfield.imm32 = 1;
2030 t.bitfield.imm32s = 1;
2031 }
2032 else if (fits_in_signed_byte (num))
2033 {
2034 t.bitfield.imm8 = 1;
2035 t.bitfield.imm8s = 1;
2036 t.bitfield.imm16 = 1;
2037 t.bitfield.imm32 = 1;
2038 t.bitfield.imm32s = 1;
2039 }
2040 else if (fits_in_unsigned_byte (num))
2041 {
2042 t.bitfield.imm8 = 1;
2043 t.bitfield.imm16 = 1;
2044 t.bitfield.imm32 = 1;
2045 t.bitfield.imm32s = 1;
2046 }
2047 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2048 {
2049 t.bitfield.imm16 = 1;
2050 t.bitfield.imm32 = 1;
2051 t.bitfield.imm32s = 1;
2052 }
2053 else if (fits_in_signed_long (num))
2054 {
2055 t.bitfield.imm32 = 1;
2056 t.bitfield.imm32s = 1;
2057 }
2058 else if (fits_in_unsigned_long (num))
2059 t.bitfield.imm32 = 1;
2060
2061 return t;
47926f60 2062}
252b5132 2063
847f7ad4 2064static offsetT
e3bb37b5 2065offset_in_range (offsetT val, int size)
847f7ad4 2066{
508866be 2067 addressT mask;
ba2adb93 2068
847f7ad4
AM		 2069 switch (size)
2070 {
508866be
L		 2071 case 1: mask = ((addressT) 1 << 8) - 1; break;
2072 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2073 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2074#ifdef BFD64
2075 case 8: mask = ((addressT) 2 << 63) - 1; break;
2076#endif
47926f60 2077 default: abort ();
847f7ad4
AM		 2078 }
2079
9de868bf
L		 2080#ifdef BFD64
2081 /* If BFD64, sign extend val for 32bit address mode. */
2082 if (flag_code != CODE_64BIT
2083 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2084 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2085 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2086#endif
ba2adb93 2087
47926f60 2088 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2089 {
2090 char buf1[40], buf2[40];
2091
2092 sprint_value (buf1, val);
2093 sprint_value (buf2, val & mask);
2094 as_warn (_("%s shortened to %s"), buf1, buf2);
2095 }
2096 return val & mask;
2097}
2098
c32fa91d
L		 2099enum PREFIX_GROUP
2100{
2101 PREFIX_EXIST = 0,
2102 PREFIX_LOCK,
2103 PREFIX_REP,
2104 PREFIX_OTHER
2105};
2106
2107/* Returns
2108 a. PREFIX_EXIST if attempting to add a prefix where one from the
2109 same class already exists.
2110 b. PREFIX_LOCK if lock prefix is added.
2111 c. PREFIX_REP if rep/repne prefix is added.
2112 d. PREFIX_OTHER if other prefix is added.
2113 */
2114
2115static enum PREFIX_GROUP
e3bb37b5 2116add_prefix (unsigned int prefix)
252b5132 2117{
c32fa91d 2118 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2119 unsigned int q;
252b5132 2120
29b0f896
AM		 2121 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2122 && flag_code == CODE_64BIT)
b1905489 2123 {
161a04f6
L		 2124 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2125 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2126 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2127 ret = PREFIX_EXIST;
b1905489
JB		 2128 q = REX_PREFIX;
2129 }
3e73aa7c 2130 else
b1905489
JB		 2131 {
2132 switch (prefix)
2133 {
2134 default:
2135 abort ();
2136
2137 case CS_PREFIX_OPCODE:
2138 case DS_PREFIX_OPCODE:
2139 case ES_PREFIX_OPCODE:
2140 case FS_PREFIX_OPCODE:
2141 case GS_PREFIX_OPCODE:
2142 case SS_PREFIX_OPCODE:
2143 q = SEG_PREFIX;
2144 break;
2145
2146 case REPNE_PREFIX_OPCODE:
2147 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2148 q = REP_PREFIX;
2149 ret = PREFIX_REP;
2150 break;
2151
b1905489 2152 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2153 q = LOCK_PREFIX;
2154 ret = PREFIX_LOCK;
b1905489
JB		 2155 break;
2156
2157 case FWAIT_OPCODE:
2158 q = WAIT_PREFIX;
2159 break;
2160
2161 case ADDR_PREFIX_OPCODE:
2162 q = ADDR_PREFIX;
2163 break;
2164
2165 case DATA_PREFIX_OPCODE:
2166 q = DATA_PREFIX;
2167 break;
2168 }
2169 if (i.prefix[q] != 0)
c32fa91d 2170 ret = PREFIX_EXIST;
b1905489 2171 }
252b5132 2172
b1905489 2173 if (ret)
252b5132 2174 {
b1905489
JB		 2175 if (!i.prefix[q])
2176 ++i.prefixes;
2177 i.prefix[q] |= prefix;
252b5132 2178 }
b1905489
JB		 2179 else
2180 as_bad (_("same type of prefix used twice"));
252b5132 2181
252b5132
RH		 2182 return ret;
2183}
2184
2185static void
78f12dd3 2186update_code_flag (int value, int check)
eecb386c 2187{
78f12dd3
L		 2188 PRINTF_LIKE ((*as_error));
2189
1e9cc1c2 2190 flag_code = (enum flag_code) value;
40fb9820
L		 2191 if (flag_code == CODE_64BIT)
2192 {
2193 cpu_arch_flags.bitfield.cpu64 = 1;
2194 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2195 }
2196 else
2197 {
2198 cpu_arch_flags.bitfield.cpu64 = 0;
2199 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2200 }
2201 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2202 {
78f12dd3
L		 2203 if (check)
2204 as_error = as_fatal;
2205 else
2206 as_error = as_bad;
2207 (*as_error) (_("64bit mode not supported on `%s'."),
2208 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2209 }
40fb9820 2210 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2211 {
78f12dd3
L		 2212 if (check)
2213 as_error = as_fatal;
2214 else
2215 as_error = as_bad;
2216 (*as_error) (_("32bit mode not supported on `%s'."),
2217 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2218 }
eecb386c
AM		 2219 stackop_size = '\0';
2220}
2221
78f12dd3
L		 2222static void
2223set_code_flag (int value)
2224{
2225 update_code_flag (value, 0);
2226}
2227
eecb386c 2228static void
e3bb37b5 2229set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2230{
1e9cc1c2 2231 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2232 if (flag_code != CODE_16BIT)
2233 abort ();
2234 cpu_arch_flags.bitfield.cpu64 = 0;
2235 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2236 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2237}
2238
2239static void
e3bb37b5 2240set_intel_syntax (int syntax_flag)
252b5132
RH		 2241{
2242 /* Find out if register prefixing is specified. */
2243 int ask_naked_reg = 0;
2244
2245 SKIP_WHITESPACE ();
29b0f896 2246 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2247 {
d02603dc
NC		 2248 char *string;
2249 int e = get_symbol_name (&string);
252b5132 2250
47926f60 2251 if (strcmp (string, "prefix") == 0)
252b5132 2252 ask_naked_reg = 1;
47926f60 2253 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2254 ask_naked_reg = -1;
2255 else
d0b47220 2256 as_bad (_("bad argument to syntax directive."));
d02603dc 2257 (void) restore_line_pointer (e);
252b5132
RH		 2258 }
2259 demand_empty_rest_of_line ();
c3332e24 2260
252b5132
RH		 2261 intel_syntax = syntax_flag;
2262
2263 if (ask_naked_reg == 0)
f86103b7
AM		 2264 allow_naked_reg = (intel_syntax
2265 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2266 else
2267 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2268
ee86248c 2269 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2270
e4a3b5a4 2271 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2272 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2273 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2274}
2275
1efbbeb4
L		 2276static void
2277set_intel_mnemonic (int mnemonic_flag)
2278{
e1d4d893 2279 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2280}
2281
db51cc60
L		 2282static void
2283set_allow_index_reg (int flag)
2284{
2285 allow_index_reg = flag;
2286}
2287
cb19c032 2288static void
7bab8ab5 2289set_check (int what)
cb19c032 2290{
7bab8ab5
JB		 2291 enum check_kind *kind;
2292 const char *str;
2293
2294 if (what)
2295 {
2296 kind = &operand_check;
2297 str = "operand";
2298 }
2299 else
2300 {
2301 kind = &sse_check;
2302 str = "sse";
2303 }
2304
cb19c032
L		 2305 SKIP_WHITESPACE ();
2306
2307 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2308 {
d02603dc
NC		 2309 char *string;
2310 int e = get_symbol_name (&string);
cb19c032
L		 2311
2312 if (strcmp (string, "none") == 0)
7bab8ab5 2313 *kind = check_none;
cb19c032 2314 else if (strcmp (string, "warning") == 0)
7bab8ab5 2315 *kind = check_warning;
cb19c032 2316 else if (strcmp (string, "error") == 0)
7bab8ab5 2317 *kind = check_error;
cb19c032 2318 else
7bab8ab5 2319 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2320 (void) restore_line_pointer (e);
cb19c032
L		 2321 }
2322 else
7bab8ab5 2323 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2324
2325 demand_empty_rest_of_line ();
2326}
2327
8a9036a4
L		 2328static void
2329check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2330 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2331{
2332#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2333 static const char *arch;
2334
2335 /* Intel LIOM is only supported on ELF. */
2336 if (!IS_ELF)
2337 return;
2338
2339 if (!arch)
2340 {
2341 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2342 use default_arch. */
2343 arch = cpu_arch_name;
2344 if (!arch)
2345 arch = default_arch;
2346 }
2347
81486035
L		 2348 /* If we are targeting Intel MCU, we must enable it. */
2349 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2350 || new_flag.bitfield.cpuiamcu)
2351 return;
2352
3632d14b 2353 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2354 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2355 || new_flag.bitfield.cpul1om)
8a9036a4 2356 return;
76ba9986 2357
7a9068fe
L		 2358 /* If we are targeting Intel K1OM, we must enable it. */
2359 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2360 || new_flag.bitfield.cpuk1om)
2361 return;
2362
8a9036a4
L		 2363 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2364#endif
2365}
2366
e413e4e9 2367static void
e3bb37b5 2368set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2369{
47926f60 2370 SKIP_WHITESPACE ();
e413e4e9 2371
29b0f896 2372 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2373 {
d02603dc
NC		 2374 char *string;
2375 int e = get_symbol_name (&string);
91d6fa6a 2376 unsigned int j;
40fb9820 2377 i386_cpu_flags flags;
e413e4e9 2378
91d6fa6a 2379 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2380 {
91d6fa6a 2381 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2382 {
91d6fa6a 2383 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2384
5c6af06e
JB		 2385 if (*string != '.')
2386 {
91d6fa6a 2387 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2388 cpu_sub_arch_name = NULL;
91d6fa6a 2389 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2390 if (flag_code == CODE_64BIT)
2391 {
2392 cpu_arch_flags.bitfield.cpu64 = 1;
2393 cpu_arch_flags.bitfield.cpuno64 = 0;
2394 }
2395 else
2396 {
2397 cpu_arch_flags.bitfield.cpu64 = 0;
2398 cpu_arch_flags.bitfield.cpuno64 = 1;
2399 }
91d6fa6a
NC		 2400 cpu_arch_isa = cpu_arch[j].type;
2401 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2402 if (!cpu_arch_tune_set)
2403 {
2404 cpu_arch_tune = cpu_arch_isa;
2405 cpu_arch_tune_flags = cpu_arch_isa_flags;
2406 }
5c6af06e
JB		 2407 break;
2408 }
40fb9820 2409
293f5f65
L		 2410 flags = cpu_flags_or (cpu_arch_flags,
2411 cpu_arch[j].flags);
81486035 2412
5b64d091 2413 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2414 {
6305a203
L		 2415 if (cpu_sub_arch_name)
2416 {
2417 char *name = cpu_sub_arch_name;
2418 cpu_sub_arch_name = concat (name,
91d6fa6a 2419 cpu_arch[j].name,
1bf57e9f 2420 (const char *) NULL);
6305a203
L		 2421 free (name);
2422 }
2423 else
91d6fa6a 2424 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2425 cpu_arch_flags = flags;
a586129e 2426 cpu_arch_isa_flags = flags;
5c6af06e 2427 }
d02603dc 2428 (void) restore_line_pointer (e);
5c6af06e
JB		 2429 demand_empty_rest_of_line ();
2430 return;
e413e4e9
AM		 2431 }
2432 }
293f5f65
L		 2433
2434 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2435 {
2436 /* Disable an ISA entension. */
2437 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2438 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2439 {
2440 flags = cpu_flags_and_not (cpu_arch_flags,
2441 cpu_noarch[j].flags);
2442 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2443 {
2444 if (cpu_sub_arch_name)
2445 {
2446 char *name = cpu_sub_arch_name;
2447 cpu_sub_arch_name = concat (name, string,
2448 (const char *) NULL);
2449 free (name);
2450 }
2451 else
2452 cpu_sub_arch_name = xstrdup (string);
2453 cpu_arch_flags = flags;
2454 cpu_arch_isa_flags = flags;
2455 }
2456 (void) restore_line_pointer (e);
2457 demand_empty_rest_of_line ();
2458 return;
2459 }
2460
2461 j = ARRAY_SIZE (cpu_arch);
2462 }
2463
91d6fa6a 2464 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2465 as_bad (_("no such architecture: `%s'"), string);
2466
2467 *input_line_pointer = e;
2468 }
2469 else
2470 as_bad (_("missing cpu architecture"));
2471
fddf5b5b
AM		 2472 no_cond_jump_promotion = 0;
2473 if (*input_line_pointer == ','
29b0f896 2474 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2475 {
d02603dc
NC		 2476 char *string;
2477 char e;
2478
2479 ++input_line_pointer;
2480 e = get_symbol_name (&string);
fddf5b5b
AM		 2481
2482 if (strcmp (string, "nojumps") == 0)
2483 no_cond_jump_promotion = 1;
2484 else if (strcmp (string, "jumps") == 0)
2485 ;
2486 else
2487 as_bad (_("no such architecture modifier: `%s'"), string);
2488
d02603dc 2489 (void) restore_line_pointer (e);
fddf5b5b
AM		 2490 }
2491
e413e4e9
AM		 2492 demand_empty_rest_of_line ();
2493}
2494
8a9036a4
L		 2495enum bfd_architecture
2496i386_arch (void)
2497{
3632d14b 2498 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2499 {
2500 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2501 || flag_code != CODE_64BIT)
2502 as_fatal (_("Intel L1OM is 64bit ELF only"));
2503 return bfd_arch_l1om;
2504 }
7a9068fe
L		 2505 else if (cpu_arch_isa == PROCESSOR_K1OM)
2506 {
2507 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2508 || flag_code != CODE_64BIT)
2509 as_fatal (_("Intel K1OM is 64bit ELF only"));
2510 return bfd_arch_k1om;
2511 }
81486035
L		 2512 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2513 {
2514 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2515 || flag_code == CODE_64BIT)
2516 as_fatal (_("Intel MCU is 32bit ELF only"));
2517 return bfd_arch_iamcu;
2518 }
8a9036a4
L		 2519 else
2520 return bfd_arch_i386;
2521}
2522
b9d79e03 2523unsigned long
7016a5d5 2524i386_mach (void)
b9d79e03 2525{
351f65ca 2526 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2527 {
3632d14b 2528 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2529 {
351f65ca
L		 2530 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2531 || default_arch[6] != '\0')
8a9036a4
L		 2532 as_fatal (_("Intel L1OM is 64bit ELF only"));
2533 return bfd_mach_l1om;
2534 }
7a9068fe
L		 2535 else if (cpu_arch_isa == PROCESSOR_K1OM)
2536 {
2537 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2538 || default_arch[6] != '\0')
2539 as_fatal (_("Intel K1OM is 64bit ELF only"));
2540 return bfd_mach_k1om;
2541 }
351f65ca 2542 else if (default_arch[6] == '\0')
8a9036a4 2543 return bfd_mach_x86_64;
351f65ca
L		 2544 else
2545 return bfd_mach_x64_32;
8a9036a4 2546 }
5197d474
L		 2547 else if (!strcmp (default_arch, "i386")
2548 || !strcmp (default_arch, "iamcu"))
81486035
L		 2549 {
2550 if (cpu_arch_isa == PROCESSOR_IAMCU)
2551 {
2552 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2553 as_fatal (_("Intel MCU is 32bit ELF only"));
2554 return bfd_mach_i386_iamcu;
2555 }
2556 else
2557 return bfd_mach_i386_i386;
2558 }
b9d79e03 2559 else
2b5d6a91 2560 as_fatal (_("unknown architecture"));
b9d79e03 2561}
b9d79e03 2562\f
252b5132 2563void
7016a5d5 2564md_begin (void)
252b5132
RH		 2565{
2566 const char *hash_err;
2567
47926f60 2568 /* Initialize op_hash hash table. */
252b5132
RH		 2569 op_hash = hash_new ();
2570
2571 {
d3ce72d0 2572 const insn_template *optab;
29b0f896 2573 templates *core_optab;
252b5132 2574
47926f60
KH		 2575 /* Setup for loop. */
2576 optab = i386_optab;
add39d23 2577 core_optab = XNEW (templates);
252b5132
RH		 2578 core_optab->start = optab;
2579
2580 while (1)
2581 {
2582 ++optab;
2583 if (optab->name == NULL
2584 || strcmp (optab->name, (optab - 1)->name) != 0)
2585 {
2586 /* different name --> ship out current template list;
47926f60 2587 add to hash table; & begin anew. */
252b5132
RH		 2588 core_optab->end = optab;
2589 hash_err = hash_insert (op_hash,
2590 (optab - 1)->name,
5a49b8ac 2591 (void *) core_optab);
252b5132
RH		 2592 if (hash_err)
2593 {
b37df7c4 2594 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2595 (optab - 1)->name,
2596 hash_err);
2597 }
2598 if (optab->name == NULL)
2599 break;
add39d23 2600 core_optab = XNEW (templates);
252b5132
RH		 2601 core_optab->start = optab;
2602 }
2603 }
2604 }
2605
47926f60 2606 /* Initialize reg_hash hash table. */
252b5132
RH		 2607 reg_hash = hash_new ();
2608 {
29b0f896 2609 const reg_entry *regtab;
c3fe08fa 2610 unsigned int regtab_size = i386_regtab_size;
252b5132 2611
c3fe08fa 2612 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2613 {
5a49b8ac 2614 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2615 if (hash_err)
b37df7c4 2616 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2617 regtab->reg_name,
2618 hash_err);
252b5132
RH		 2619 }
2620 }
2621
47926f60 2622 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2623 {
29b0f896
AM		 2624 int c;
2625 char *p;
252b5132
RH		 2626
2627 for (c = 0; c < 256; c++)
2628 {
3882b010 2629 if (ISDIGIT (c))
252b5132
RH		 2630 {
2631 digit_chars[c] = c;
2632 mnemonic_chars[c] = c;
2633 register_chars[c] = c;
2634 operand_chars[c] = c;
2635 }
3882b010 2636 else if (ISLOWER (c))
252b5132
RH		 2637 {
2638 mnemonic_chars[c] = c;
2639 register_chars[c] = c;
2640 operand_chars[c] = c;
2641 }
3882b010 2642 else if (ISUPPER (c))
252b5132 2643 {
3882b010 2644 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2645 register_chars[c] = mnemonic_chars[c];
2646 operand_chars[c] = c;
2647 }
43234a1e
L		 2648 else if (c == '{' || c == '}')
2649 operand_chars[c] = c;
252b5132 2650
3882b010 2651 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2652 identifier_chars[c] = c;
2653 else if (c >= 128)
2654 {
2655 identifier_chars[c] = c;
2656 operand_chars[c] = c;
2657 }
2658 }
2659
2660#ifdef LEX_AT
2661 identifier_chars['@'] = '@';
32137342
NC		 2662#endif
2663#ifdef LEX_QM
2664 identifier_chars['?'] = '?';
2665 operand_chars['?'] = '?';
252b5132 2666#endif
252b5132 2667 digit_chars['-'] = '-';
c0f3af97 2668 mnemonic_chars['_'] = '_';
791fe849 2669 mnemonic_chars['-'] = '-';
0003779b 2670 mnemonic_chars['.'] = '.';
252b5132
RH		 2671 identifier_chars['_'] = '_';
2672 identifier_chars['.'] = '.';
2673
2674 for (p = operand_special_chars; *p != '\0'; p++)
2675 operand_chars[(unsigned char) *p] = *p;
2676 }
2677
a4447b93
RH		 2678 if (flag_code == CODE_64BIT)
2679 {
ca19b261
KT		 2680#if defined (OBJ_COFF) && defined (TE_PE)
2681 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2682 ? 32 : 16);
2683#else
a4447b93 2684 x86_dwarf2_return_column = 16;
ca19b261 2685#endif
61ff971f 2686 x86_cie_data_alignment = -8;
a4447b93
RH		 2687 }
2688 else
2689 {
2690 x86_dwarf2_return_column = 8;
2691 x86_cie_data_alignment = -4;
2692 }
252b5132
RH		 2693}
2694
2695void
e3bb37b5 2696i386_print_statistics (FILE *file)
252b5132
RH		 2697{
2698 hash_print_statistics (file, "i386 opcode", op_hash);
2699 hash_print_statistics (file, "i386 register", reg_hash);
2700}
2701\f
252b5132
RH		 2702#ifdef DEBUG386
2703
ce8a8b2f 2704/* Debugging routines for md_assemble. */
d3ce72d0 2705static void pte (insn_template *);
40fb9820 2706static void pt (i386_operand_type);
e3bb37b5
L		 2707static void pe (expressionS *);
2708static void ps (symbolS *);
252b5132
RH		 2709
2710static void
e3bb37b5 2711pi (char *line, i386_insn *x)
252b5132 2712{
09137c09 2713 unsigned int j;
252b5132
RH		 2714
2715 fprintf (stdout, "%s: template ", line);
2716 pte (&x->tm);
09f131f2
JH		 2717 fprintf (stdout, " address: base %s index %s scale %x\n",
2718 x->base_reg ? x->base_reg->reg_name : "none",
2719 x->index_reg ? x->index_reg->reg_name : "none",
2720 x->log2_scale_factor);
2721 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2722 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2723 fprintf (stdout, " sib: base %x index %x scale %x\n",
2724 x->sib.base, x->sib.index, x->sib.scale);
2725 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2726 (x->rex & REX_W) != 0,
2727 (x->rex & REX_R) != 0,
2728 (x->rex & REX_X) != 0,
2729 (x->rex & REX_B) != 0);
09137c09 2730 for (j = 0; j < x->operands; j++)
252b5132 2731 {
09137c09
SP		 2732 fprintf (stdout, " #%d: ", j + 1);
2733 pt (x->types[j]);
252b5132 2734 fprintf (stdout, "\n");
09137c09
SP		 2735 if (x->types[j].bitfield.reg8
2736 || x->types[j].bitfield.reg16
2737 || x->types[j].bitfield.reg32
2738 || x->types[j].bitfield.reg64
2739 || x->types[j].bitfield.regmmx
2740 || x->types[j].bitfield.regxmm
2741 || x->types[j].bitfield.regymm
43234a1e 2742 || x->types[j].bitfield.regzmm
09137c09
SP		 2743 || x->types[j].bitfield.sreg2
2744 || x->types[j].bitfield.sreg3
2745 || x->types[j].bitfield.control
2746 || x->types[j].bitfield.debug
2747 || x->types[j].bitfield.test)
2748 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2749 if (operand_type_check (x->types[j], imm))
2750 pe (x->op[j].imms);
2751 if (operand_type_check (x->types[j], disp))
2752 pe (x->op[j].disps);
252b5132
RH		 2753 }
2754}
2755
2756static void
d3ce72d0 2757pte (insn_template *t)
252b5132 2758{
09137c09 2759 unsigned int j;
252b5132 2760 fprintf (stdout, " %d operands ", t->operands);
47926f60 2761 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2762 if (t->extension_opcode != None)
2763 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2764 if (t->opcode_modifier.d)
252b5132 2765 fprintf (stdout, "D");
40fb9820 2766 if (t->opcode_modifier.w)
252b5132
RH		 2767 fprintf (stdout, "W");
2768 fprintf (stdout, "\n");
09137c09 2769 for (j = 0; j < t->operands; j++)
252b5132 2770 {
09137c09
SP		 2771 fprintf (stdout, " #%d type ", j + 1);
2772 pt (t->operand_types[j]);
252b5132
RH		 2773 fprintf (stdout, "\n");
2774 }
2775}
2776
2777static void
e3bb37b5 2778pe (expressionS *e)
252b5132 2779{
24eab124 2780 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2781 fprintf (stdout, " add_number %ld (%lx)\n",
2782 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2783 if (e->X_add_symbol)
2784 {
2785 fprintf (stdout, " add_symbol ");
2786 ps (e->X_add_symbol);
2787 fprintf (stdout, "\n");
2788 }
2789 if (e->X_op_symbol)
2790 {
2791 fprintf (stdout, " op_symbol ");
2792 ps (e->X_op_symbol);
2793 fprintf (stdout, "\n");
2794 }
2795}
2796
2797static void
e3bb37b5 2798ps (symbolS *s)
252b5132
RH		 2799{
2800 fprintf (stdout, "%s type %s%s",
2801 S_GET_NAME (s),
2802 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2803 segment_name (S_GET_SEGMENT (s)));
2804}
2805
7b81dfbb 2806static struct type_name
252b5132 2807 {
40fb9820
L		 2808 i386_operand_type mask;
2809 const char *name;
252b5132 2810 }
7b81dfbb 2811const type_names[] =
252b5132 2812{
40fb9820
L		 2813 { OPERAND_TYPE_REG8, "r8" },
2814 { OPERAND_TYPE_REG16, "r16" },
2815 { OPERAND_TYPE_REG32, "r32" },
2816 { OPERAND_TYPE_REG64, "r64" },
2817 { OPERAND_TYPE_IMM8, "i8" },
2818 { OPERAND_TYPE_IMM8, "i8s" },
2819 { OPERAND_TYPE_IMM16, "i16" },
2820 { OPERAND_TYPE_IMM32, "i32" },
2821 { OPERAND_TYPE_IMM32S, "i32s" },
2822 { OPERAND_TYPE_IMM64, "i64" },
2823 { OPERAND_TYPE_IMM1, "i1" },
2824 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2825 { OPERAND_TYPE_DISP8, "d8" },
2826 { OPERAND_TYPE_DISP16, "d16" },
2827 { OPERAND_TYPE_DISP32, "d32" },
2828 { OPERAND_TYPE_DISP32S, "d32s" },
2829 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2830 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2831 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2832 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2833 { OPERAND_TYPE_CONTROL, "control reg" },
2834 { OPERAND_TYPE_TEST, "test reg" },
2835 { OPERAND_TYPE_DEBUG, "debug reg" },
2836 { OPERAND_TYPE_FLOATREG, "FReg" },
2837 { OPERAND_TYPE_FLOATACC, "FAcc" },
2838 { OPERAND_TYPE_SREG2, "SReg2" },
2839 { OPERAND_TYPE_SREG3, "SReg3" },
2840 { OPERAND_TYPE_ACC, "Acc" },
2841 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2842 { OPERAND_TYPE_REGMMX, "rMMX" },
2843 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2844 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2845 { OPERAND_TYPE_REGZMM, "rZMM" },
2846 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2847 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2848};
2849
2850static void
40fb9820 2851pt (i386_operand_type t)
252b5132 2852{
40fb9820 2853 unsigned int j;
c6fb90c8 2854 i386_operand_type a;
252b5132 2855
40fb9820 2856 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2857 {
2858 a = operand_type_and (t, type_names[j].mask);
0349dc08 2859 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2860 fprintf (stdout, "%s, ", type_names[j].name);
2861 }
252b5132
RH		 2862 fflush (stdout);
2863}
2864
2865#endif /* DEBUG386 */
2866\f
252b5132 2867static bfd_reloc_code_real_type
3956db08 2868reloc (unsigned int size,
64e74474
AM		 2869 int pcrel,
2870 int sign,
2871 bfd_reloc_code_real_type other)
252b5132 2872{
47926f60 2873 if (other != NO_RELOC)
3956db08 2874 {
91d6fa6a 2875 reloc_howto_type *rel;
3956db08
JB		 2876
2877 if (size == 8)
2878 switch (other)
2879 {
64e74474
AM		 2880 case BFD_RELOC_X86_64_GOT32:
2881 return BFD_RELOC_X86_64_GOT64;
2882 break;
553d1284
L		 2883 case BFD_RELOC_X86_64_GOTPLT64:
2884 return BFD_RELOC_X86_64_GOTPLT64;
2885 break;
64e74474
AM		 2886 case BFD_RELOC_X86_64_PLTOFF64:
2887 return BFD_RELOC_X86_64_PLTOFF64;
2888 break;
2889 case BFD_RELOC_X86_64_GOTPC32:
2890 other = BFD_RELOC_X86_64_GOTPC64;
2891 break;
2892 case BFD_RELOC_X86_64_GOTPCREL:
2893 other = BFD_RELOC_X86_64_GOTPCREL64;
2894 break;
2895 case BFD_RELOC_X86_64_TPOFF32:
2896 other = BFD_RELOC_X86_64_TPOFF64;
2897 break;
2898 case BFD_RELOC_X86_64_DTPOFF32:
2899 other = BFD_RELOC_X86_64_DTPOFF64;
2900 break;
2901 default:
2902 break;
3956db08 2903 }
e05278af 2904
8ce3d284 2905#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2906 if (other == BFD_RELOC_SIZE32)
2907 {
2908 if (size == 8)
1ab668bf 2909 other = BFD_RELOC_SIZE64;
8fd4256d 2910 if (pcrel)
1ab668bf
AM		 2911 {
2912 as_bad (_("there are no pc-relative size relocations"));
2913 return NO_RELOC;
2914 }
8fd4256d 2915 }
8ce3d284 2916#endif
8fd4256d 2917
e05278af 2918 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2919 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2920 sign = -1;
2921
91d6fa6a
NC		 2922 rel = bfd_reloc_type_lookup (stdoutput, other);
2923 if (!rel)
3956db08 2924 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2925 else if (size != bfd_get_reloc_size (rel))
3956db08 2926 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2927 bfd_get_reloc_size (rel),
3956db08 2928 size);
91d6fa6a 2929 else if (pcrel && !rel->pc_relative)
3956db08 2930 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2931 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2932 && !sign)
91d6fa6a 2933 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2934 && sign > 0))
3956db08
JB		 2935 as_bad (_("relocated field and relocation type differ in signedness"));
2936 else
2937 return other;
2938 return NO_RELOC;
2939 }
252b5132
RH		 2940
2941 if (pcrel)
2942 {
3e73aa7c 2943 if (!sign)
3956db08 2944 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2945 switch (size)
2946 {
2947 case 1: return BFD_RELOC_8_PCREL;
2948 case 2: return BFD_RELOC_16_PCREL;
d258b828 2949 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2950 case 8: return BFD_RELOC_64_PCREL;
252b5132 2951 }
3956db08 2952 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2953 }
2954 else
2955 {
3956db08 2956 if (sign > 0)
e5cb08ac 2957 switch (size)
3e73aa7c
JH		 2958 {
2959 case 4: return BFD_RELOC_X86_64_32S;
2960 }
2961 else
2962 switch (size)
2963 {
2964 case 1: return BFD_RELOC_8;
2965 case 2: return BFD_RELOC_16;
2966 case 4: return BFD_RELOC_32;
2967 case 8: return BFD_RELOC_64;
2968 }
3956db08
JB		 2969 as_bad (_("cannot do %s %u byte relocation"),
2970 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2971 }
2972
0cc9e1d3 2973 return NO_RELOC;
252b5132
RH		 2974}
2975
47926f60
KH		 2976/* Here we decide which fixups can be adjusted to make them relative to
2977 the beginning of the section instead of the symbol. Basically we need
2978 to make sure that the dynamic relocations are done correctly, so in
2979 some cases we force the original symbol to be used. */
2980
252b5132 2981int
e3bb37b5 2982tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2983{
6d249963 2984#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2985 if (!IS_ELF)
31312f95
AM		 2986 return 1;
2987
a161fe53
AM		 2988 /* Don't adjust pc-relative references to merge sections in 64-bit
2989 mode. */
2990 if (use_rela_relocations
2991 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2992 && fixP->fx_pcrel)
252b5132 2993 return 0;
31312f95 2994
8d01d9a9
AJ		 2995 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2996 and changed later by validate_fix. */
2997 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2998 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2999 return 0;
3000
8fd4256d
L		 3001 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3002 for size relocations. */
3003 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3004 || fixP->fx_r_type == BFD_RELOC_SIZE64
3005 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3006 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3007 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3008 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3009 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3010 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3011 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3012 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3013 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3014 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3015 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3016 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3017 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3018 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3019 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3020 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3021 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3022 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3023 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3024 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3025 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3026 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3027 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3028 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3029 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3030 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3031 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3032 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3033 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3034 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3035 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3036 return 0;
31312f95 3037#endif
252b5132
RH		 3038 return 1;
3039}
252b5132 3040
b4cac588 3041static int
e3bb37b5 3042intel_float_operand (const char *mnemonic)
252b5132 3043{
9306ca4a
JB		 3044 /* Note that the value returned is meaningful only for opcodes with (memory)
3045 operands, hence the code here is free to improperly handle opcodes that
3046 have no operands (for better performance and smaller code). */
3047
3048 if (mnemonic[0] != 'f')
3049 return 0; /* non-math */
3050
3051 switch (mnemonic[1])
3052 {
3053 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3054 the fs segment override prefix not currently handled because no
3055 call path can make opcodes without operands get here */
3056 case 'i':
3057 return 2 /* integer op */;
3058 case 'l':
3059 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3060 return 3; /* fldcw/fldenv */
3061 break;
3062 case 'n':
3063 if (mnemonic[2] != 'o' /* fnop */)
3064 return 3; /* non-waiting control op */
3065 break;
3066 case 'r':
3067 if (mnemonic[2] == 's')
3068 return 3; /* frstor/frstpm */
3069 break;
3070 case 's':
3071 if (mnemonic[2] == 'a')
3072 return 3; /* fsave */
3073 if (mnemonic[2] == 't')
3074 {
3075 switch (mnemonic[3])
3076 {
3077 case 'c': /* fstcw */
3078 case 'd': /* fstdw */
3079 case 'e': /* fstenv */
3080 case 's': /* fsts[gw] */
3081 return 3;
3082 }
3083 }
3084 break;
3085 case 'x':
3086 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3087 return 0; /* fxsave/fxrstor are not really math ops */
3088 break;
3089 }
252b5132 3090
9306ca4a 3091 return 1;
252b5132
RH		 3092}
3093
c0f3af97
L		 3094/* Build the VEX prefix. */
3095
3096static void
d3ce72d0 3097build_vex_prefix (const insn_template *t)
c0f3af97
L		 3098{
3099 unsigned int register_specifier;
3100 unsigned int implied_prefix;
3101 unsigned int vector_length;
3102
3103 /* Check register specifier. */
3104 if (i.vex.register_specifier)
43234a1e
L		 3105 {
3106 register_specifier =
3107 ~register_number (i.vex.register_specifier) & 0xf;
3108 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3109 }
c0f3af97
L		 3110 else
3111 register_specifier = 0xf;
3112
fa99fab2
L		 3113 /* Use 2-byte VEX prefix by swappping destination and source
3114 operand. */
3115 if (!i.swap_operand
3116 && i.operands == i.reg_operands
7f399153 3117 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3118 && i.tm.opcode_modifier.s
3119 && i.rex == REX_B)
3120 {
3121 unsigned int xchg = i.operands - 1;
3122 union i386_op temp_op;
3123 i386_operand_type temp_type;
3124
3125 temp_type = i.types[xchg];
3126 i.types[xchg] = i.types[0];
3127 i.types[0] = temp_type;
3128 temp_op = i.op[xchg];
3129 i.op[xchg] = i.op[0];
3130 i.op[0] = temp_op;
3131
9c2799c2 3132 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3133
3134 i.rex = REX_R;
3135 xchg = i.rm.regmem;
3136 i.rm.regmem = i.rm.reg;
3137 i.rm.reg = xchg;
3138
3139 /* Use the next insn. */
3140 i.tm = t[1];
3141 }
3142
539f890d
L		 3143 if (i.tm.opcode_modifier.vex == VEXScalar)
3144 vector_length = avxscalar;
3145 else
3146 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3147
3148 switch ((i.tm.base_opcode >> 8) & 0xff)
3149 {
3150 case 0:
3151 implied_prefix = 0;
3152 break;
3153 case DATA_PREFIX_OPCODE:
3154 implied_prefix = 1;
3155 break;
3156 case REPE_PREFIX_OPCODE:
3157 implied_prefix = 2;
3158 break;
3159 case REPNE_PREFIX_OPCODE:
3160 implied_prefix = 3;
3161 break;
3162 default:
3163 abort ();
3164 }
3165
3166 /* Use 2-byte VEX prefix if possible. */
7f399153 3167 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3168 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3169 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3170 {
3171 /* 2-byte VEX prefix. */
3172 unsigned int r;
3173
3174 i.vex.length = 2;
3175 i.vex.bytes[0] = 0xc5;
3176
3177 /* Check the REX.R bit. */
3178 r = (i.rex & REX_R) ? 0 : 1;
3179 i.vex.bytes[1] = (r << 7
3180 | register_specifier << 3
3181 | vector_length << 2
3182 | implied_prefix);
3183 }
3184 else
3185 {
3186 /* 3-byte VEX prefix. */
3187 unsigned int m, w;
3188
f88c9eb0 3189 i.vex.length = 3;
f88c9eb0 3190
7f399153 3191 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3192 {
7f399153
L		 3193 case VEX0F:
3194 m = 0x1;
80de6e00 3195 i.vex.bytes[0] = 0xc4;
7f399153
L		 3196 break;
3197 case VEX0F38:
3198 m = 0x2;
80de6e00 3199 i.vex.bytes[0] = 0xc4;
7f399153
L		 3200 break;
3201 case VEX0F3A:
3202 m = 0x3;
80de6e00 3203 i.vex.bytes[0] = 0xc4;
7f399153
L		 3204 break;
3205 case XOP08:
5dd85c99
SP		 3206 m = 0x8;
3207 i.vex.bytes[0] = 0x8f;
7f399153
L		 3208 break;
3209 case XOP09:
f88c9eb0
SP		 3210 m = 0x9;
3211 i.vex.bytes[0] = 0x8f;
7f399153
L		 3212 break;
3213 case XOP0A:
f88c9eb0
SP		 3214 m = 0xa;
3215 i.vex.bytes[0] = 0x8f;
7f399153
L		 3216 break;
3217 default:
3218 abort ();
f88c9eb0 3219 }
c0f3af97 3220
c0f3af97
L		 3221 /* The high 3 bits of the second VEX byte are 1's compliment
3222 of RXB bits from REX. */
3223 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3224
3225 /* Check the REX.W bit. */
3226 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3227 if (i.tm.opcode_modifier.vexw == VEXW1)
3228 w = 1;
c0f3af97
L		 3229
3230 i.vex.bytes[2] = (w << 7
3231 | register_specifier << 3
3232 | vector_length << 2
3233 | implied_prefix);
3234 }
3235}
3236
43234a1e
L		 3237/* Build the EVEX prefix. */
3238
3239static void
3240build_evex_prefix (void)
3241{
3242 unsigned int register_specifier;
3243 unsigned int implied_prefix;
3244 unsigned int m, w;
3245 rex_byte vrex_used = 0;
3246
3247 /* Check register specifier. */
3248 if (i.vex.register_specifier)
3249 {
3250 gas_assert ((i.vrex & REX_X) == 0);
3251
3252 register_specifier = i.vex.register_specifier->reg_num;
3253 if ((i.vex.register_specifier->reg_flags & RegRex))
3254 register_specifier += 8;
3255 /* The upper 16 registers are encoded in the fourth byte of the
3256 EVEX prefix. */
3257 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3258 i.vex.bytes[3] = 0x8;
3259 register_specifier = ~register_specifier & 0xf;
3260 }
3261 else
3262 {
3263 register_specifier = 0xf;
3264
3265 /* Encode upper 16 vector index register in the fourth byte of
3266 the EVEX prefix. */
3267 if (!(i.vrex & REX_X))
3268 i.vex.bytes[3] = 0x8;
3269 else
3270 vrex_used |= REX_X;
3271 }
3272
3273 switch ((i.tm.base_opcode >> 8) & 0xff)
3274 {
3275 case 0:
3276 implied_prefix = 0;
3277 break;
3278 case DATA_PREFIX_OPCODE:
3279 implied_prefix = 1;
3280 break;
3281 case REPE_PREFIX_OPCODE:
3282 implied_prefix = 2;
3283 break;
3284 case REPNE_PREFIX_OPCODE:
3285 implied_prefix = 3;
3286 break;
3287 default:
3288 abort ();
3289 }
3290
3291 /* 4 byte EVEX prefix. */
3292 i.vex.length = 4;
3293 i.vex.bytes[0] = 0x62;
3294
3295 /* mmmm bits. */
3296 switch (i.tm.opcode_modifier.vexopcode)
3297 {
3298 case VEX0F:
3299 m = 1;
3300 break;
3301 case VEX0F38:
3302 m = 2;
3303 break;
3304 case VEX0F3A:
3305 m = 3;
3306 break;
3307 default:
3308 abort ();
3309 break;
3310 }
3311
3312 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3313 bits from REX. */
3314 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3315
3316 /* The fifth bit of the second EVEX byte is 1's compliment of the
3317 REX_R bit in VREX. */
3318 if (!(i.vrex & REX_R))
3319 i.vex.bytes[1] |= 0x10;
3320 else
3321 vrex_used |= REX_R;
3322
3323 if ((i.reg_operands + i.imm_operands) == i.operands)
3324 {
3325 /* When all operands are registers, the REX_X bit in REX is not
3326 used. We reuse it to encode the upper 16 registers, which is
3327 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3328 as 1's compliment. */
3329 if ((i.vrex & REX_B))
3330 {
3331 vrex_used |= REX_B;
3332 i.vex.bytes[1] &= ~0x40;
3333 }
3334 }
3335
3336 /* EVEX instructions shouldn't need the REX prefix. */
3337 i.vrex &= ~vrex_used;
3338 gas_assert (i.vrex == 0);
3339
3340 /* Check the REX.W bit. */
3341 w = (i.rex & REX_W) ? 1 : 0;
3342 if (i.tm.opcode_modifier.vexw)
3343 {
3344 if (i.tm.opcode_modifier.vexw == VEXW1)
3345 w = 1;
3346 }
3347 /* If w is not set it means we are dealing with WIG instruction. */
3348 else if (!w)
3349 {
3350 if (evexwig == evexw1)
3351 w = 1;
3352 }
3353
3354 /* Encode the U bit. */
3355 implied_prefix |= 0x4;
3356
3357 /* The third byte of the EVEX prefix. */
3358 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3359
3360 /* The fourth byte of the EVEX prefix. */
3361 /* The zeroing-masking bit. */
3362 if (i.mask && i.mask->zeroing)
3363 i.vex.bytes[3] |= 0x80;
3364
3365 /* Don't always set the broadcast bit if there is no RC. */
3366 if (!i.rounding)
3367 {
3368 /* Encode the vector length. */
3369 unsigned int vec_length;
3370
3371 switch (i.tm.opcode_modifier.evex)
3372 {
3373 case EVEXLIG: /* LL' is ignored */
3374 vec_length = evexlig << 5;
3375 break;
3376 case EVEX128:
3377 vec_length = 0 << 5;
3378 break;
3379 case EVEX256:
3380 vec_length = 1 << 5;
3381 break;
3382 case EVEX512:
3383 vec_length = 2 << 5;
3384 break;
3385 default:
3386 abort ();
3387 break;
3388 }
3389 i.vex.bytes[3] |= vec_length;
3390 /* Encode the broadcast bit. */
3391 if (i.broadcast)
3392 i.vex.bytes[3] |= 0x10;
3393 }
3394 else
3395 {
3396 if (i.rounding->type != saeonly)
3397 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3398 else
d3d3c6db 3399 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3400 }
3401
3402 if (i.mask && i.mask->mask)
3403 i.vex.bytes[3] |= i.mask->mask->reg_num;
3404}
3405
65da13b5
L		 3406static void
3407process_immext (void)
3408{
3409 expressionS *exp;
3410
4c692bc7
JB		 3411 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3412 && i.operands > 0)
65da13b5 3413 {
4c692bc7
JB		 3414 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3415 with an opcode suffix which is coded in the same place as an
3416 8-bit immediate field would be.
3417 Here we check those operands and remove them afterwards. */
65da13b5
L		 3418 unsigned int x;
3419
3420 for (x = 0; x < i.operands; x++)
4c692bc7 3421 if (register_number (i.op[x].regs) != x)
65da13b5 3422 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3423 register_prefix, i.op[x].regs->reg_name, x + 1,
3424 i.tm.name);
3425
3426 i.operands = 0;
65da13b5
L		 3427 }
3428
9916071f
AP		 3429 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3430 {
3431 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3432 suffix which is coded in the same place as an 8-bit immediate
3433 field would be.
3434 Here we check those operands and remove them afterwards. */
3435 unsigned int x;
3436
3437 if (i.operands != 3)
3438 abort();
3439
3440 for (x = 0; x < 2; x++)
3441 if (register_number (i.op[x].regs) != x)
3442 goto bad_register_operand;
3443
3444 /* Check for third operand for mwaitx/monitorx insn. */
3445 if (register_number (i.op[x].regs)
3446 != (x + (i.tm.extension_opcode == 0xfb)))
3447 {
3448bad_register_operand:
3449 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3450 register_prefix, i.op[x].regs->reg_name, x+1,
3451 i.tm.name);
3452 }
3453
3454 i.operands = 0;
3455 }
3456
c0f3af97 3457 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3458 which is coded in the same place as an 8-bit immediate field
3459 would be. Here we fake an 8-bit immediate operand from the
3460 opcode suffix stored in tm.extension_opcode.
3461
c1e679ec 3462 AVX instructions also use this encoding, for some of
c0f3af97 3463 3 argument instructions. */
65da13b5 3464
43234a1e 3465 gas_assert (i.imm_operands <= 1
7ab9ffdd 3466 && (i.operands <= 2
43234a1e
L		 3467 || ((i.tm.opcode_modifier.vex
3468 || i.tm.opcode_modifier.evex)
7ab9ffdd 3469 && i.operands <= 4)));
65da13b5
L		 3470
3471 exp = &im_expressions[i.imm_operands++];
3472 i.op[i.operands].imms = exp;
3473 i.types[i.operands] = imm8;
3474 i.operands++;
3475 exp->X_op = O_constant;
3476 exp->X_add_number = i.tm.extension_opcode;
3477 i.tm.extension_opcode = None;
3478}
3479
42164a71
L		 3480
3481static int
3482check_hle (void)
3483{
3484 switch (i.tm.opcode_modifier.hleprefixok)
3485 {
3486 default:
3487 abort ();
82c2def5 3488 case HLEPrefixNone:
165de32a
L		 3489 as_bad (_("invalid instruction `%s' after `%s'"),
3490 i.tm.name, i.hle_prefix);
42164a71 3491 return 0;
82c2def5 3492 case HLEPrefixLock:
42164a71
L		 3493 if (i.prefix[LOCK_PREFIX])
3494 return 1;
165de32a 3495 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3496 return 0;
82c2def5 3497 case HLEPrefixAny:
42164a71 3498 return 1;
82c2def5 3499 case HLEPrefixRelease:
42164a71
L		 3500 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3501 {
3502 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3503 i.tm.name);
3504 return 0;
3505 }
3506 if (i.mem_operands == 0
3507 || !operand_type_check (i.types[i.operands - 1], anymem))
3508 {
3509 as_bad (_("memory destination needed for instruction `%s'"
3510 " after `xrelease'"), i.tm.name);
3511 return 0;
3512 }
3513 return 1;
3514 }
3515}
3516
252b5132
RH		 3517/* This is the guts of the machine-dependent assembler. LINE points to a
3518 machine dependent instruction. This function is supposed to emit
3519 the frags/bytes it assembles to. */
3520
3521void
65da13b5 3522md_assemble (char *line)
252b5132 3523{
40fb9820 3524 unsigned int j;
83b16ac6 3525 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3526 const insn_template *t;
252b5132 3527
47926f60 3528 /* Initialize globals. */
252b5132
RH		 3529 memset (&i, '\0', sizeof (i));
3530 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3531 i.reloc[j] = NO_RELOC;
252b5132
RH		 3532 memset (disp_expressions, '\0', sizeof (disp_expressions));
3533 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3534 save_stack_p = save_stack;
252b5132
RH		 3535
3536 /* First parse an instruction mnemonic & call i386_operand for the operands.
3537 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3538 start of a (possibly prefixed) mnemonic. */
252b5132 3539
29b0f896
AM		 3540 line = parse_insn (line, mnemonic);
3541 if (line == NULL)
3542 return;
83b16ac6 3543 mnem_suffix = i.suffix;
252b5132 3544
29b0f896 3545 line = parse_operands (line, mnemonic);
ee86248c 3546 this_operand = -1;
8325cc63
JB		 3547 xfree (i.memop1_string);
3548 i.memop1_string = NULL;
29b0f896
AM		 3549 if (line == NULL)
3550 return;
252b5132 3551
29b0f896
AM		 3552 /* Now we've parsed the mnemonic into a set of templates, and have the
3553 operands at hand. */
3554
3555 /* All intel opcodes have reversed operands except for "bound" and
3556 "enter". We also don't reverse intersegment "jmp" and "call"
3557 instructions with 2 immediate operands so that the immediate segment
050dfa73 3558 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3559 if (intel_syntax
3560 && i.operands > 1
29b0f896 3561 && (strcmp (mnemonic, "bound") != 0)
30123838 3562 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3563 && !(operand_type_check (i.types[0], imm)
3564 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3565 swap_operands ();
3566
ec56d5c0
JB		 3567 /* The order of the immediates should be reversed
3568 for 2 immediates extrq and insertq instructions */
3569 if (i.imm_operands == 2
3570 && (strcmp (mnemonic, "extrq") == 0
3571 || strcmp (mnemonic, "insertq") == 0))
3572 swap_2_operands (0, 1);
3573
29b0f896
AM		 3574 if (i.imm_operands)
3575 optimize_imm ();
3576
b300c311
L		 3577 /* Don't optimize displacement for movabs since it only takes 64bit
3578 displacement. */
3579 if (i.disp_operands
a501d77e 3580 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3581 && (flag_code != CODE_64BIT
3582 || strcmp (mnemonic, "movabs") != 0))
3583 optimize_disp ();
29b0f896
AM		 3584
3585 /* Next, we find a template that matches the given insn,
3586 making sure the overlap of the given operands types is consistent
3587 with the template operand types. */
252b5132 3588
83b16ac6 3589 if (!(t = match_template (mnem_suffix)))
29b0f896 3590 return;
252b5132 3591
7bab8ab5 3592 if (sse_check != check_none
81f8a913 3593 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3594 && (i.tm.cpu_flags.bitfield.cpusse
3595 || i.tm.cpu_flags.bitfield.cpusse2
3596 || i.tm.cpu_flags.bitfield.cpusse3
3597 || i.tm.cpu_flags.bitfield.cpussse3
3598 || i.tm.cpu_flags.bitfield.cpusse4_1
3599 || i.tm.cpu_flags.bitfield.cpusse4_2))
3600 {
7bab8ab5 3601 (sse_check == check_warning
daf50ae7
L		 3602 ? as_warn
3603 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3604 }
3605
321fd21e
L		 3606 /* Zap movzx and movsx suffix. The suffix has been set from
3607 "word ptr" or "byte ptr" on the source operand in Intel syntax
3608 or extracted from mnemonic in AT&T syntax. But we'll use
3609 the destination register to choose the suffix for encoding. */
3610 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3611 {
321fd21e
L		 3612 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3613 there is no suffix, the default will be byte extension. */
3614 if (i.reg_operands != 2
3615 && !i.suffix
7ab9ffdd 3616 && intel_syntax)
321fd21e
L		 3617 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3618
3619 i.suffix = 0;
cd61ebfe 3620 }
24eab124 3621
40fb9820 3622 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3623 if (!add_prefix (FWAIT_OPCODE))
3624 return;
252b5132 3625
d5de92cf
L		 3626 /* Check if REP prefix is OK. */
3627 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3628 {
3629 as_bad (_("invalid instruction `%s' after `%s'"),
3630 i.tm.name, i.rep_prefix);
3631 return;
3632 }
3633
c1ba0266
L		 3634 /* Check for lock without a lockable instruction. Destination operand
3635 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3636 if (i.prefix[LOCK_PREFIX]
3637 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3638 || i.mem_operands == 0
3639 || (i.tm.base_opcode != 0x86
3640 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3641 {
3642 as_bad (_("expecting lockable instruction after `lock'"));
3643 return;
3644 }
3645
42164a71 3646 /* Check if HLE prefix is OK. */
165de32a 3647 if (i.hle_prefix && !check_hle ())
42164a71
L		 3648 return;
3649
7e8b059b
L		 3650 /* Check BND prefix. */
3651 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3652 as_bad (_("expecting valid branch instruction after `bnd'"));
3653
327e8c42
JB		 3654 if (i.tm.cpu_flags.bitfield.cpumpx)
3655 {
3656 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3657 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3658 else if (flag_code != CODE_16BIT
3659 ? i.prefix[ADDR_PREFIX]
3660 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3661 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3662 }
7e8b059b
L		 3663
3664 /* Insert BND prefix. */
3665 if (add_bnd_prefix
3666 && i.tm.opcode_modifier.bndprefixok
3667 && !i.prefix[BND_PREFIX])
3668 add_prefix (BND_PREFIX_OPCODE);
3669
29b0f896 3670 /* Check string instruction segment overrides. */
40fb9820 3671 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3672 {
3673 if (!check_string ())
5dd0794d 3674 return;
fc0763e6 3675 i.disp_operands = 0;
29b0f896 3676 }
5dd0794d 3677
29b0f896
AM		 3678 if (!process_suffix ())
3679 return;
e413e4e9 3680
bc0844ae
L		 3681 /* Update operand types. */
3682 for (j = 0; j < i.operands; j++)
3683 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3684
29b0f896
AM		 3685 /* Make still unresolved immediate matches conform to size of immediate
3686 given in i.suffix. */
3687 if (!finalize_imm ())
3688 return;
252b5132 3689
40fb9820 3690 if (i.types[0].bitfield.imm1)
29b0f896 3691 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3692
9afe6eb8
L		 3693 /* We only need to check those implicit registers for instructions
3694 with 3 operands or less. */
3695 if (i.operands <= 3)
3696 for (j = 0; j < i.operands; j++)
3697 if (i.types[j].bitfield.inoutportreg
3698 || i.types[j].bitfield.shiftcount
3699 || i.types[j].bitfield.acc
3700 || i.types[j].bitfield.floatacc)
3701 i.reg_operands--;
40fb9820 3702
c0f3af97
L		 3703 /* ImmExt should be processed after SSE2AVX. */
3704 if (!i.tm.opcode_modifier.sse2avx
3705 && i.tm.opcode_modifier.immext)
65da13b5 3706 process_immext ();
252b5132 3707
29b0f896
AM		 3708 /* For insns with operands there are more diddles to do to the opcode. */
3709 if (i.operands)
3710 {
3711 if (!process_operands ())
3712 return;
3713 }
40fb9820 3714 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3715 {
3716 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3717 as_warn (_("translating to `%sp'"), i.tm.name);
3718 }
252b5132 3719
9e5e5283
L		 3720 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3721 {
3722 if (flag_code == CODE_16BIT)
3723 {
3724 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3725 i.tm.name);
3726 return;
3727 }
c0f3af97 3728
9e5e5283
L		 3729 if (i.tm.opcode_modifier.vex)
3730 build_vex_prefix (t);
3731 else
3732 build_evex_prefix ();
3733 }
43234a1e 3734
5dd85c99
SP		 3735 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3736 instructions may define INT_OPCODE as well, so avoid this corner
3737 case for those instructions that use MODRM. */
3738 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3739 && !i.tm.opcode_modifier.modrm
3740 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3741 {
3742 i.tm.base_opcode = INT3_OPCODE;
3743 i.imm_operands = 0;
3744 }
252b5132 3745
40fb9820
L		 3746 if ((i.tm.opcode_modifier.jump
3747 || i.tm.opcode_modifier.jumpbyte
3748 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3749 && i.op[0].disps->X_op == O_constant)
3750 {
3751 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3752 the absolute address given by the constant. Since ix86 jumps and
3753 calls are pc relative, we need to generate a reloc. */
3754 i.op[0].disps->X_add_symbol = &abs_symbol;
3755 i.op[0].disps->X_op = O_symbol;
3756 }
252b5132 3757
40fb9820 3758 if (i.tm.opcode_modifier.rex64)
161a04f6 3759 i.rex |= REX_W;
252b5132 3760
29b0f896
AM		 3761 /* For 8 bit registers we need an empty rex prefix. Also if the
3762 instruction already has a prefix, we need to convert old
3763 registers to new ones. */
773f551c 3764
40fb9820 3765 if ((i.types[0].bitfield.reg8
29b0f896 3766 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3767 || (i.types[1].bitfield.reg8
29b0f896 3768 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3769 || ((i.types[0].bitfield.reg8
3770 || i.types[1].bitfield.reg8)
29b0f896
AM		 3771 && i.rex != 0))
3772 {
3773 int x;
726c5dcd 3774
29b0f896
AM		 3775 i.rex |= REX_OPCODE;
3776 for (x = 0; x < 2; x++)
3777 {
3778 /* Look for 8 bit operand that uses old registers. */
40fb9820 3779 if (i.types[x].bitfield.reg8
29b0f896 3780 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3781 {
29b0f896
AM		 3782 /* In case it is "hi" register, give up. */
3783 if (i.op[x].regs->reg_num > 3)
a540244d 3784 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3785 "instruction requiring REX prefix."),
a540244d 3786 register_prefix, i.op[x].regs->reg_name);
773f551c 3787
29b0f896
AM		 3788 /* Otherwise it is equivalent to the extended register.
3789 Since the encoding doesn't change this is merely
3790 cosmetic cleanup for debug output. */
3791
3792 i.op[x].regs = i.op[x].regs + 8;
773f551c 3793 }
29b0f896
AM		 3794 }
3795 }
773f551c 3796
7ab9ffdd 3797 if (i.rex != 0)
29b0f896
AM		 3798 add_prefix (REX_OPCODE | i.rex);
3799
3800 /* We are ready to output the insn. */
3801 output_insn ();
3802}
3803
3804static char *
e3bb37b5 3805parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3806{
3807 char *l = line;
3808 char *token_start = l;
3809 char *mnem_p;
5c6af06e 3810 int supported;
d3ce72d0 3811 const insn_template *t;
b6169b20 3812 char *dot_p = NULL;
29b0f896 3813
29b0f896
AM		 3814 while (1)
3815 {
3816 mnem_p = mnemonic;
3817 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3818 {
b6169b20
L		 3819 if (*mnem_p == '.')
3820 dot_p = mnem_p;
29b0f896
AM		 3821 mnem_p++;
3822 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3823 {
29b0f896
AM		 3824 as_bad (_("no such instruction: `%s'"), token_start);
3825 return NULL;
3826 }
3827 l++;
3828 }
3829 if (!is_space_char (*l)
3830 && *l != END_OF_INSN
e44823cf
JB		 3831 && (intel_syntax
3832 || (*l != PREFIX_SEPARATOR
3833 && *l != ',')))
29b0f896
AM		 3834 {
3835 as_bad (_("invalid character %s in mnemonic"),
3836 output_invalid (*l));
3837 return NULL;
3838 }
3839 if (token_start == l)
3840 {
e44823cf 3841 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3842 as_bad (_("expecting prefix; got nothing"));
3843 else
3844 as_bad (_("expecting mnemonic; got nothing"));
3845 return NULL;
3846 }
45288df1 3847
29b0f896 3848 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3849 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3850
29b0f896
AM		 3851 if (*l != END_OF_INSN
3852 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3853 && current_templates
40fb9820 3854 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3855 {
c6fb90c8 3856 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3857 {
3858 as_bad ((flag_code != CODE_64BIT
3859 ? _("`%s' is only supported in 64-bit mode")
3860 : _("`%s' is not supported in 64-bit mode")),
3861 current_templates->start->name);
3862 return NULL;
3863 }
29b0f896
AM		 3864 /* If we are in 16-bit mode, do not allow addr16 or data16.
3865 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3866 if ((current_templates->start->opcode_modifier.size16
3867 || current_templates->start->opcode_modifier.size32)
29b0f896 3868 && flag_code != CODE_64BIT
40fb9820 3869 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3870 ^ (flag_code == CODE_16BIT)))
3871 {
3872 as_bad (_("redundant %s prefix"),
3873 current_templates->start->name);
3874 return NULL;
45288df1 3875 }
29b0f896
AM		 3876 /* Add prefix, checking for repeated prefixes. */
3877 switch (add_prefix (current_templates->start->base_opcode))
3878 {
c32fa91d 3879 case PREFIX_EXIST:
29b0f896 3880 return NULL;
c32fa91d 3881 case PREFIX_REP:
42164a71 3882 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3883 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3884 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3885 i.bnd_prefix = current_templates->start->name;
42164a71 3886 else
d5de92cf 3887 i.rep_prefix = current_templates->start->name;
29b0f896 3888 break;
c32fa91d
L		 3889 default:
3890 break;
29b0f896
AM		 3891 }
3892 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3893 token_start = ++l;
3894 }
3895 else
3896 break;
3897 }
45288df1 3898
30a55f88 3899 if (!current_templates)
b6169b20 3900 {
f8a5c266
L		 3901 /* Check if we should swap operand or force 32bit displacement in
3902 encoding. */
30a55f88
L		 3903 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3904 i.swap_operand = 1;
8d63c93e 3905 else if (mnem_p - 3 == dot_p
a501d77e
L		 3906 && dot_p[1] == 'd'
3907 && dot_p[2] == '8')
3908 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3909 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3910 && dot_p[1] == 'd'
3911 && dot_p[2] == '3'
3912 && dot_p[3] == '2')
a501d77e 3913 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3914 else
3915 goto check_suffix;
3916 mnem_p = dot_p;
3917 *dot_p = '\0';
d3ce72d0 3918 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3919 }
3920
29b0f896
AM		 3921 if (!current_templates)
3922 {
b6169b20 3923check_suffix:
29b0f896
AM		 3924 /* See if we can get a match by trimming off a suffix. */
3925 switch (mnem_p[-1])
3926 {
3927 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3928 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3929 i.suffix = SHORT_MNEM_SUFFIX;
3930 else
29b0f896
AM		 3931 case BYTE_MNEM_SUFFIX:
3932 case QWORD_MNEM_SUFFIX:
3933 i.suffix = mnem_p[-1];
3934 mnem_p[-1] = '\0';
d3ce72d0
NC		 3935 current_templates = (const templates *) hash_find (op_hash,
3936 mnemonic);
29b0f896
AM		 3937 break;
3938 case SHORT_MNEM_SUFFIX:
3939 case LONG_MNEM_SUFFIX:
3940 if (!intel_syntax)
3941 {
3942 i.suffix = mnem_p[-1];
3943 mnem_p[-1] = '\0';
d3ce72d0
NC		 3944 current_templates = (const templates *) hash_find (op_hash,
3945 mnemonic);
29b0f896
AM		 3946 }
3947 break;
252b5132 3948
29b0f896
AM		 3949 /* Intel Syntax. */
3950 case 'd':
3951 if (intel_syntax)
3952 {
9306ca4a 3953 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3954 i.suffix = SHORT_MNEM_SUFFIX;
3955 else
3956 i.suffix = LONG_MNEM_SUFFIX;
3957 mnem_p[-1] = '\0';
d3ce72d0
NC		 3958 current_templates = (const templates *) hash_find (op_hash,
3959 mnemonic);
29b0f896
AM		 3960 }
3961 break;
3962 }
3963 if (!current_templates)
3964 {
3965 as_bad (_("no such instruction: `%s'"), token_start);
3966 return NULL;
3967 }
3968 }
252b5132 3969
40fb9820
L		 3970 if (current_templates->start->opcode_modifier.jump
3971 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3972 {
3973 /* Check for a branch hint. We allow ",pt" and ",pn" for
3974 predict taken and predict not taken respectively.
3975 I'm not sure that branch hints actually do anything on loop
3976 and jcxz insns (JumpByte) for current Pentium4 chips. They
3977 may work in the future and it doesn't hurt to accept them
3978 now. */
3979 if (l[0] == ',' && l[1] == 'p')
3980 {
3981 if (l[2] == 't')
3982 {
3983 if (!add_prefix (DS_PREFIX_OPCODE))
3984 return NULL;
3985 l += 3;
3986 }
3987 else if (l[2] == 'n')
3988 {
3989 if (!add_prefix (CS_PREFIX_OPCODE))
3990 return NULL;
3991 l += 3;
3992 }
3993 }
3994 }
3995 /* Any other comma loses. */
3996 if (*l == ',')
3997 {
3998 as_bad (_("invalid character %s in mnemonic"),
3999 output_invalid (*l));
4000 return NULL;
4001 }
252b5132 4002
29b0f896 4003 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4004 supported = 0;
4005 for (t = current_templates->start; t < current_templates->end; ++t)
4006 {
c0f3af97
L		 4007 supported |= cpu_flags_match (t);
4008 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4009 goto skip;
5c6af06e 4010 }
3629bb00 4011
c0f3af97 4012 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4013 {
4014 as_bad (flag_code == CODE_64BIT
4015 ? _("`%s' is not supported in 64-bit mode")
4016 : _("`%s' is only supported in 64-bit mode"),
4017 current_templates->start->name);
4018 return NULL;
4019 }
c0f3af97 4020 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4021 {
3629bb00 4022 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4023 current_templates->start->name,
41aacd83 4024 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4025 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4026 return NULL;
29b0f896 4027 }
3629bb00
L		 4028
4029skip:
4030 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4031 && (flag_code != CODE_16BIT))
29b0f896
AM		 4032 {
4033 as_warn (_("use .code16 to ensure correct addressing mode"));
4034 }
252b5132 4035
29b0f896
AM		 4036 return l;
4037}
252b5132 4038
29b0f896 4039static char *
e3bb37b5 4040parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4041{
4042 char *token_start;
3138f287 4043
29b0f896
AM		 4044 /* 1 if operand is pending after ','. */
4045 unsigned int expecting_operand = 0;
252b5132 4046
29b0f896
AM		 4047 /* Non-zero if operand parens not balanced. */
4048 unsigned int paren_not_balanced;
4049
4050 while (*l != END_OF_INSN)
4051 {
4052 /* Skip optional white space before operand. */
4053 if (is_space_char (*l))
4054 ++l;
d02603dc 4055 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4056 {
4057 as_bad (_("invalid character %s before operand %d"),
4058 output_invalid (*l),
4059 i.operands + 1);
4060 return NULL;
4061 }
d02603dc 4062 token_start = l; /* After white space. */
29b0f896
AM		 4063 paren_not_balanced = 0;
4064 while (paren_not_balanced || *l != ',')
4065 {
4066 if (*l == END_OF_INSN)
4067 {
4068 if (paren_not_balanced)
4069 {
4070 if (!intel_syntax)
4071 as_bad (_("unbalanced parenthesis in operand %d."),
4072 i.operands + 1);
4073 else
4074 as_bad (_("unbalanced brackets in operand %d."),
4075 i.operands + 1);
4076 return NULL;
4077 }
4078 else
4079 break; /* we are done */
4080 }
d02603dc 4081 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4082 {
4083 as_bad (_("invalid character %s in operand %d"),
4084 output_invalid (*l),
4085 i.operands + 1);
4086 return NULL;
4087 }
4088 if (!intel_syntax)
4089 {
4090 if (*l == '(')
4091 ++paren_not_balanced;
4092 if (*l == ')')
4093 --paren_not_balanced;
4094 }
4095 else
4096 {
4097 if (*l == '[')
4098 ++paren_not_balanced;
4099 if (*l == ']')
4100 --paren_not_balanced;
4101 }
4102 l++;
4103 }
4104 if (l != token_start)
4105 { /* Yes, we've read in another operand. */
4106 unsigned int operand_ok;
4107 this_operand = i.operands++;
7d5e4556 4108 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4109 if (i.operands > MAX_OPERANDS)
4110 {
4111 as_bad (_("spurious operands; (%d operands/instruction max)"),
4112 MAX_OPERANDS);
4113 return NULL;
4114 }
4115 /* Now parse operand adding info to 'i' as we go along. */
4116 END_STRING_AND_SAVE (l);
4117
4118 if (intel_syntax)
4119 operand_ok =
4120 i386_intel_operand (token_start,
4121 intel_float_operand (mnemonic));
4122 else
a7619375 4123 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4124
4125 RESTORE_END_STRING (l);
4126 if (!operand_ok)
4127 return NULL;
4128 }
4129 else
4130 {
4131 if (expecting_operand)
4132 {
4133 expecting_operand_after_comma:
4134 as_bad (_("expecting operand after ','; got nothing"));
4135 return NULL;
4136 }
4137 if (*l == ',')
4138 {
4139 as_bad (_("expecting operand before ','; got nothing"));
4140 return NULL;
4141 }
4142 }
7f3f1ea2 4143
29b0f896
AM		 4144 /* Now *l must be either ',' or END_OF_INSN. */
4145 if (*l == ',')
4146 {
4147 if (*++l == END_OF_INSN)
4148 {
4149 /* Just skip it, if it's \n complain. */
4150 goto expecting_operand_after_comma;
4151 }
4152 expecting_operand = 1;
4153 }
4154 }
4155 return l;
4156}
7f3f1ea2 4157
050dfa73 4158static void
4d456e3d 4159swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4160{
4161 union i386_op temp_op;
40fb9820 4162 i386_operand_type temp_type;
050dfa73 4163 enum bfd_reloc_code_real temp_reloc;
4eed87de 4164
050dfa73
MM		 4165 temp_type = i.types[xchg2];
4166 i.types[xchg2] = i.types[xchg1];
4167 i.types[xchg1] = temp_type;
4168 temp_op = i.op[xchg2];
4169 i.op[xchg2] = i.op[xchg1];
4170 i.op[xchg1] = temp_op;
4171 temp_reloc = i.reloc[xchg2];
4172 i.reloc[xchg2] = i.reloc[xchg1];
4173 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4174
4175 if (i.mask)
4176 {
4177 if (i.mask->operand == xchg1)
4178 i.mask->operand = xchg2;
4179 else if (i.mask->operand == xchg2)
4180 i.mask->operand = xchg1;
4181 }
4182 if (i.broadcast)
4183 {
4184 if (i.broadcast->operand == xchg1)
4185 i.broadcast->operand = xchg2;
4186 else if (i.broadcast->operand == xchg2)
4187 i.broadcast->operand = xchg1;
4188 }
4189 if (i.rounding)
4190 {
4191 if (i.rounding->operand == xchg1)
4192 i.rounding->operand = xchg2;
4193 else if (i.rounding->operand == xchg2)
4194 i.rounding->operand = xchg1;
4195 }
050dfa73
MM		 4196}
4197
29b0f896 4198static void
e3bb37b5 4199swap_operands (void)
29b0f896 4200{
b7c61d9a 4201 switch (i.operands)
050dfa73 4202 {
c0f3af97 4203 case 5:
b7c61d9a 4204 case 4:
4d456e3d 4205 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4206 case 3:
4207 case 2:
4d456e3d 4208 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4209 break;
4210 default:
4211 abort ();
29b0f896 4212 }
29b0f896
AM		 4213
4214 if (i.mem_operands == 2)
4215 {
4216 const seg_entry *temp_seg;
4217 temp_seg = i.seg[0];
4218 i.seg[0] = i.seg[1];
4219 i.seg[1] = temp_seg;
4220 }
4221}
252b5132 4222
29b0f896
AM		 4223/* Try to ensure constant immediates are represented in the smallest
4224 opcode possible. */
4225static void
e3bb37b5 4226optimize_imm (void)
29b0f896
AM		 4227{
4228 char guess_suffix = 0;
4229 int op;
252b5132 4230
29b0f896
AM		 4231 if (i.suffix)
4232 guess_suffix = i.suffix;
4233 else if (i.reg_operands)
4234 {
4235 /* Figure out a suffix from the last register operand specified.
4236 We can't do this properly yet, ie. excluding InOutPortReg,
4237 but the following works for instructions with immediates.
4238 In any case, we can't set i.suffix yet. */
4239 for (op = i.operands; --op >= 0;)
40fb9820 4240 if (i.types[op].bitfield.reg8)
7ab9ffdd 4241 {
40fb9820
L		 4242 guess_suffix = BYTE_MNEM_SUFFIX;
4243 break;
4244 }
4245 else if (i.types[op].bitfield.reg16)
252b5132 4246 {
40fb9820
L		 4247 guess_suffix = WORD_MNEM_SUFFIX;
4248 break;
4249 }
4250 else if (i.types[op].bitfield.reg32)
4251 {
4252 guess_suffix = LONG_MNEM_SUFFIX;
4253 break;
4254 }
4255 else if (i.types[op].bitfield.reg64)
4256 {
4257 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4258 break;
252b5132 4259 }
29b0f896
AM		 4260 }
4261 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4262 guess_suffix = WORD_MNEM_SUFFIX;
4263
4264 for (op = i.operands; --op >= 0;)
40fb9820 4265 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4266 {
4267 switch (i.op[op].imms->X_op)
252b5132 4268 {
29b0f896
AM		 4269 case O_constant:
4270 /* If a suffix is given, this operand may be shortened. */
4271 switch (guess_suffix)
252b5132 4272 {
29b0f896 4273 case LONG_MNEM_SUFFIX:
40fb9820
L		 4274 i.types[op].bitfield.imm32 = 1;
4275 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4276 break;
4277 case WORD_MNEM_SUFFIX:
40fb9820
L		 4278 i.types[op].bitfield.imm16 = 1;
4279 i.types[op].bitfield.imm32 = 1;
4280 i.types[op].bitfield.imm32s = 1;
4281 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4282 break;
4283 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4284 i.types[op].bitfield.imm8 = 1;
4285 i.types[op].bitfield.imm8s = 1;
4286 i.types[op].bitfield.imm16 = 1;
4287 i.types[op].bitfield.imm32 = 1;
4288 i.types[op].bitfield.imm32s = 1;
4289 i.types[op].bitfield.imm64 = 1;
29b0f896 4290 break;
252b5132 4291 }
252b5132 4292
29b0f896
AM		 4293 /* If this operand is at most 16 bits, convert it
4294 to a signed 16 bit number before trying to see
4295 whether it will fit in an even smaller size.
4296 This allows a 16-bit operand such as $0xffe0 to
4297 be recognised as within Imm8S range. */
40fb9820 4298 if ((i.types[op].bitfield.imm16)
29b0f896 4299 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4300 {
29b0f896
AM		 4301 i.op[op].imms->X_add_number =
4302 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4303 }
a28def75
L		 4304#ifdef BFD64
4305 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4306 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4307 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4308 == 0))
4309 {
4310 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4311 ^ ((offsetT) 1 << 31))
4312 - ((offsetT) 1 << 31));
4313 }
a28def75 4314#endif
40fb9820 4315 i.types[op]
c6fb90c8
L		 4316 = operand_type_or (i.types[op],
4317 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4318
29b0f896
AM		 4319 /* We must avoid matching of Imm32 templates when 64bit
4320 only immediate is available. */
4321 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4322 i.types[op].bitfield.imm32 = 0;
29b0f896 4323 break;
252b5132 4324
29b0f896
AM		 4325 case O_absent:
4326 case O_register:
4327 abort ();
4328
4329 /* Symbols and expressions. */
4330 default:
9cd96992
JB		 4331 /* Convert symbolic operand to proper sizes for matching, but don't
4332 prevent matching a set of insns that only supports sizes other
4333 than those matching the insn suffix. */
4334 {
40fb9820 4335 i386_operand_type mask, allowed;
d3ce72d0 4336 const insn_template *t;
9cd96992 4337
0dfbf9d7
L		 4338 operand_type_set (&mask, 0);
4339 operand_type_set (&allowed, 0);
40fb9820 4340
4eed87de
AM		 4341 for (t = current_templates->start;
4342 t < current_templates->end;
4343 ++t)
c6fb90c8
L		 4344 allowed = operand_type_or (allowed,
4345 t->operand_types[op]);
9cd96992
JB		 4346 switch (guess_suffix)
4347 {
4348 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4349 mask.bitfield.imm64 = 1;
4350 mask.bitfield.imm32s = 1;
9cd96992
JB		 4351 break;
4352 case LONG_MNEM_SUFFIX:
40fb9820 4353 mask.bitfield.imm32 = 1;
9cd96992
JB		 4354 break;
4355 case WORD_MNEM_SUFFIX:
40fb9820 4356 mask.bitfield.imm16 = 1;
9cd96992
JB		 4357 break;
4358 case BYTE_MNEM_SUFFIX:
40fb9820 4359 mask.bitfield.imm8 = 1;
9cd96992
JB		 4360 break;
4361 default:
9cd96992
JB		 4362 break;
4363 }
c6fb90c8 4364 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4365 if (!operand_type_all_zero (&allowed))
c6fb90c8 4366 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4367 }
29b0f896 4368 break;
252b5132 4369 }
29b0f896
AM		 4370 }
4371}
47926f60 4372
29b0f896
AM		 4373/* Try to use the smallest displacement type too. */
4374static void
e3bb37b5 4375optimize_disp (void)
29b0f896
AM		 4376{
4377 int op;
3e73aa7c 4378
29b0f896 4379 for (op = i.operands; --op >= 0;)
40fb9820 4380 if (operand_type_check (i.types[op], disp))
252b5132 4381 {
b300c311 4382 if (i.op[op].disps->X_op == O_constant)
252b5132 4383 {
91d6fa6a 4384 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4385
40fb9820 4386 if (i.types[op].bitfield.disp16
91d6fa6a 4387 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4388 {
4389 /* If this operand is at most 16 bits, convert
4390 to a signed 16 bit number and don't use 64bit
4391 displacement. */
91d6fa6a 4392 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4393 i.types[op].bitfield.disp64 = 0;
b300c311 4394 }
a28def75
L		 4395#ifdef BFD64
4396 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4397 if (i.types[op].bitfield.disp32
91d6fa6a 4398 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4399 {
4400 /* If this operand is at most 32 bits, convert
4401 to a signed 32 bit number and don't use 64bit
4402 displacement. */
91d6fa6a
NC		 4403 op_disp &= (((offsetT) 2 << 31) - 1);
4404 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4405 i.types[op].bitfield.disp64 = 0;
b300c311 4406 }
a28def75 4407#endif
91d6fa6a 4408 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4409 {
40fb9820
L		 4410 i.types[op].bitfield.disp8 = 0;
4411 i.types[op].bitfield.disp16 = 0;
4412 i.types[op].bitfield.disp32 = 0;
4413 i.types[op].bitfield.disp32s = 0;
4414 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4415 i.op[op].disps = 0;
4416 i.disp_operands--;
4417 }
4418 else if (flag_code == CODE_64BIT)
4419 {
91d6fa6a 4420 if (fits_in_signed_long (op_disp))
28a9d8f5 4421 {
40fb9820
L		 4422 i.types[op].bitfield.disp64 = 0;
4423 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4424 }
0e1147d9 4425 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4426 && fits_in_unsigned_long (op_disp))
40fb9820 4427 i.types[op].bitfield.disp32 = 1;
b300c311 4428 }
40fb9820
L		 4429 if ((i.types[op].bitfield.disp32
4430 || i.types[op].bitfield.disp32s
4431 || i.types[op].bitfield.disp16)
91d6fa6a 4432 && fits_in_signed_byte (op_disp))
40fb9820 4433 i.types[op].bitfield.disp8 = 1;
252b5132 4434 }
67a4f2b7
AO		 4435 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4436 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4437 {
4438 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4439 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4440 i.types[op].bitfield.disp8 = 0;
4441 i.types[op].bitfield.disp16 = 0;
4442 i.types[op].bitfield.disp32 = 0;
4443 i.types[op].bitfield.disp32s = 0;
4444 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4445 }
4446 else
b300c311 4447 /* We only support 64bit displacement on constants. */
40fb9820 4448 i.types[op].bitfield.disp64 = 0;
252b5132 4449 }
29b0f896
AM		 4450}
4451
6c30d220
L		 4452/* Check if operands are valid for the instruction. */
4453
4454static int
4455check_VecOperands (const insn_template *t)
4456{
43234a1e
L		 4457 unsigned int op;
4458
6c30d220
L		 4459 /* Without VSIB byte, we can't have a vector register for index. */
4460 if (!t->opcode_modifier.vecsib
4461 && i.index_reg
4462 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4463 || i.index_reg->reg_type.bitfield.regymm
4464 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4465 {
4466 i.error = unsupported_vector_index_register;
4467 return 1;
4468 }
4469
ad8ecc81
MZ		 4470 /* Check if default mask is allowed. */
4471 if (t->opcode_modifier.nodefmask
4472 && (!i.mask || i.mask->mask->reg_num == 0))
4473 {
4474 i.error = no_default_mask;
4475 return 1;
4476 }
4477
7bab8ab5
JB		 4478 /* For VSIB byte, we need a vector register for index, and all vector
4479 registers must be distinct. */
4480 if (t->opcode_modifier.vecsib)
4481 {
4482 if (!i.index_reg
6c30d220
L		 4483 || !((t->opcode_modifier.vecsib == VecSIB128
4484 && i.index_reg->reg_type.bitfield.regxmm)
4485 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4486 && i.index_reg->reg_type.bitfield.regymm)
4487 || (t->opcode_modifier.vecsib == VecSIB512
4488 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4489 {
4490 i.error = invalid_vsib_address;
4491 return 1;
4492 }
4493
43234a1e
L		 4494 gas_assert (i.reg_operands == 2 || i.mask);
4495 if (i.reg_operands == 2 && !i.mask)
4496 {
4497 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4498 || i.types[0].bitfield.regymm);
43234a1e 4499 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4500 || i.types[2].bitfield.regymm);
43234a1e
L		 4501 if (operand_check == check_none)
4502 return 0;
4503 if (register_number (i.op[0].regs)
4504 != register_number (i.index_reg)
4505 && register_number (i.op[2].regs)
4506 != register_number (i.index_reg)
4507 && register_number (i.op[0].regs)
4508 != register_number (i.op[2].regs))
4509 return 0;
4510 if (operand_check == check_error)
4511 {
4512 i.error = invalid_vector_register_set;
4513 return 1;
4514 }
4515 as_warn (_("mask, index, and destination registers should be distinct"));
4516 }
8444f82a
MZ		 4517 else if (i.reg_operands == 1 && i.mask)
4518 {
4519 if ((i.types[1].bitfield.regymm
4520 || i.types[1].bitfield.regzmm)
4521 && (register_number (i.op[1].regs)
4522 == register_number (i.index_reg)))
4523 {
4524 if (operand_check == check_error)
4525 {
4526 i.error = invalid_vector_register_set;
4527 return 1;
4528 }
4529 if (operand_check != check_none)
4530 as_warn (_("index and destination registers should be distinct"));
4531 }
4532 }
43234a1e 4533 }
7bab8ab5 4534
43234a1e
L		 4535 /* Check if broadcast is supported by the instruction and is applied
4536 to the memory operand. */
4537 if (i.broadcast)
4538 {
4539 int broadcasted_opnd_size;
4540
4541 /* Check if specified broadcast is supported in this instruction,
4542 and it's applied to memory operand of DWORD or QWORD type,
4543 depending on VecESize. */
4544 if (i.broadcast->type != t->opcode_modifier.broadcast
4545 || !i.types[i.broadcast->operand].bitfield.mem
4546 || (t->opcode_modifier.vecesize == 0
4547 && !i.types[i.broadcast->operand].bitfield.dword
4548 && !i.types[i.broadcast->operand].bitfield.unspecified)
4549 || (t->opcode_modifier.vecesize == 1
4550 && !i.types[i.broadcast->operand].bitfield.qword
4551 && !i.types[i.broadcast->operand].bitfield.unspecified))
4552 goto bad_broadcast;
4553
4554 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4555 if (i.broadcast->type == BROADCAST_1TO16)
4556 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4557 else if (i.broadcast->type == BROADCAST_1TO8)
4558 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4559 else if (i.broadcast->type == BROADCAST_1TO4)
4560 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4561 else if (i.broadcast->type == BROADCAST_1TO2)
4562 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4563 else
4564 goto bad_broadcast;
4565
4566 if ((broadcasted_opnd_size == 256
4567 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4568 || (broadcasted_opnd_size == 512
4569 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4570 {
4571 bad_broadcast:
4572 i.error = unsupported_broadcast;
4573 return 1;
4574 }
4575 }
4576 /* If broadcast is supported in this instruction, we need to check if
4577 operand of one-element size isn't specified without broadcast. */
4578 else if (t->opcode_modifier.broadcast && i.mem_operands)
4579 {
4580 /* Find memory operand. */
4581 for (op = 0; op < i.operands; op++)
4582 if (operand_type_check (i.types[op], anymem))
4583 break;
4584 gas_assert (op < i.operands);
4585 /* Check size of the memory operand. */
4586 if ((t->opcode_modifier.vecesize == 0
4587 && i.types[op].bitfield.dword)
4588 || (t->opcode_modifier.vecesize == 1
4589 && i.types[op].bitfield.qword))
4590 {
4591 i.error = broadcast_needed;
4592 return 1;
4593 }
4594 }
4595
4596 /* Check if requested masking is supported. */
4597 if (i.mask
4598 && (!t->opcode_modifier.masking
4599 || (i.mask->zeroing
4600 && t->opcode_modifier.masking == MERGING_MASKING)))
4601 {
4602 i.error = unsupported_masking;
4603 return 1;
4604 }
4605
4606 /* Check if masking is applied to dest operand. */
4607 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4608 {
4609 i.error = mask_not_on_destination;
4610 return 1;
4611 }
4612
43234a1e
L		 4613 /* Check RC/SAE. */
4614 if (i.rounding)
4615 {
4616 if ((i.rounding->type != saeonly
4617 && !t->opcode_modifier.staticrounding)
4618 || (i.rounding->type == saeonly
4619 && (t->opcode_modifier.staticrounding
4620 || !t->opcode_modifier.sae)))
4621 {
4622 i.error = unsupported_rc_sae;
4623 return 1;
4624 }
4625 /* If the instruction has several immediate operands and one of
4626 them is rounding, the rounding operand should be the last
4627 immediate operand. */
4628 if (i.imm_operands > 1
4629 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4630 {
43234a1e 4631 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4632 return 1;
4633 }
6c30d220
L		 4634 }
4635
43234a1e
L		 4636 /* Check vector Disp8 operand. */
4637 if (t->opcode_modifier.disp8memshift)
4638 {
4639 if (i.broadcast)
4640 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4641 else
4642 i.memshift = t->opcode_modifier.disp8memshift;
4643
4644 for (op = 0; op < i.operands; op++)
4645 if (operand_type_check (i.types[op], disp)
4646 && i.op[op].disps->X_op == O_constant)
4647 {
4648 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4649 int vec_disp8_ok
4650 = (i.disp_encoding != disp_encoding_32bit
4651 && fits_in_vec_disp8 (value));
43234a1e
L		 4652 if (t->operand_types [op].bitfield.vec_disp8)
4653 {
4654 if (vec_disp8_ok)
4655 i.types[op].bitfield.vec_disp8 = 1;
4656 else
4657 {
4658 /* Vector insn can only have Vec_Disp8/Disp32 in
4659 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4660 mode. */
4661 i.types[op].bitfield.disp8 = 0;
4662 if (flag_code != CODE_16BIT)
4663 i.types[op].bitfield.disp16 = 0;
4664 }
4665 }
4666 else if (flag_code != CODE_16BIT)
4667 {
4668 /* One form of this instruction supports vector Disp8.
4669 Try vector Disp8 if we need to use Disp32. */
4670 if (vec_disp8_ok && !fits_in_signed_byte (value))
4671 {
4672 i.error = try_vector_disp8;
4673 return 1;
4674 }
4675 }
4676 }
4677 }
4678 else
4679 i.memshift = -1;
4680
6c30d220
L		 4681 return 0;
4682}
4683
43f3e2ee 4684/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4685 operand types. */
4686
4687static int
4688VEX_check_operands (const insn_template *t)
4689{
43234a1e
L		 4690 /* VREX is only valid with EVEX prefix. */
4691 if (i.need_vrex && !t->opcode_modifier.evex)
4692 {
4693 i.error = invalid_register_operand;
4694 return 1;
4695 }
4696
a683cc34
SP		 4697 if (!t->opcode_modifier.vex)
4698 return 0;
4699
4700 /* Only check VEX_Imm4, which must be the first operand. */
4701 if (t->operand_types[0].bitfield.vec_imm4)
4702 {
4703 if (i.op[0].imms->X_op != O_constant
4704 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4705 {
a65babc9 4706 i.error = bad_imm4;
891edac4
L		 4707 return 1;
4708 }
a683cc34
SP		 4709
4710 /* Turn off Imm8 so that update_imm won't complain. */
4711 i.types[0] = vec_imm4;
4712 }
4713
4714 return 0;
4715}
4716
d3ce72d0 4717static const insn_template *
83b16ac6 4718match_template (char mnem_suffix)
29b0f896
AM		 4719{
4720 /* Points to template once we've found it. */
d3ce72d0 4721 const insn_template *t;
40fb9820 4722 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4723 i386_operand_type overlap4;
29b0f896 4724 unsigned int found_reverse_match;
83b16ac6 4725 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4726 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4727 int addr_prefix_disp;
a5c311ca 4728 unsigned int j;
3629bb00 4729 unsigned int found_cpu_match;
45664ddb 4730 unsigned int check_register;
5614d22c 4731 enum i386_error specific_error = 0;
29b0f896 4732
c0f3af97
L		 4733#if MAX_OPERANDS != 5
4734# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4735#endif
4736
29b0f896 4737 found_reverse_match = 0;
539e75ad 4738 addr_prefix_disp = -1;
40fb9820
L		 4739
4740 memset (&suffix_check, 0, sizeof (suffix_check));
4741 if (i.suffix == BYTE_MNEM_SUFFIX)
4742 suffix_check.no_bsuf = 1;
4743 else if (i.suffix == WORD_MNEM_SUFFIX)
4744 suffix_check.no_wsuf = 1;
4745 else if (i.suffix == SHORT_MNEM_SUFFIX)
4746 suffix_check.no_ssuf = 1;
4747 else if (i.suffix == LONG_MNEM_SUFFIX)
4748 suffix_check.no_lsuf = 1;
4749 else if (i.suffix == QWORD_MNEM_SUFFIX)
4750 suffix_check.no_qsuf = 1;
4751 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4752 suffix_check.no_ldsuf = 1;
29b0f896 4753
83b16ac6
JB		 4754 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4755 if (intel_syntax)
4756 {
4757 switch (mnem_suffix)
4758 {
4759 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4760 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4761 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4762 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4763 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4764 }
4765 }
4766
01559ecc
L		 4767 /* Must have right number of operands. */
4768 i.error = number_of_operands_mismatch;
4769
45aa61fe 4770 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4771 {
539e75ad
L		 4772 addr_prefix_disp = -1;
4773
29b0f896
AM		 4774 if (i.operands != t->operands)
4775 continue;
4776
50aecf8c 4777 /* Check processor support. */
a65babc9 4778 i.error = unsupported;
c0f3af97
L		 4779 found_cpu_match = (cpu_flags_match (t)
4780 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4781 if (!found_cpu_match)
4782 continue;
4783
e1d4d893 4784 /* Check old gcc support. */
a65babc9 4785 i.error = old_gcc_only;
e1d4d893
L		 4786 if (!old_gcc && t->opcode_modifier.oldgcc)
4787 continue;
4788
4789 /* Check AT&T mnemonic. */
a65babc9 4790 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4791 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4792 continue;
4793
e92bae62 4794 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4795 i.error = unsupported_syntax;
5c07affc 4796 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4797 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4798 || (intel64 && t->opcode_modifier.amd64)
4799 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4800 continue;
4801
20592a94 4802 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4803 i.error = invalid_instruction_suffix;
567e4e96
L		 4804 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4805 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4806 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4807 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4808 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4809 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4810 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4811 continue;
83b16ac6
JB		 4812 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4813 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4814 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4815 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4816 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4817 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4818 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4819 continue;
29b0f896 4820
5c07affc 4821 if (!operand_size_match (t))
7d5e4556 4822 continue;
539e75ad 4823
5c07affc
L		 4824 for (j = 0; j < MAX_OPERANDS; j++)
4825 operand_types[j] = t->operand_types[j];
4826
45aa61fe
AM		 4827 /* In general, don't allow 64-bit operands in 32-bit mode. */
4828 if (i.suffix == QWORD_MNEM_SUFFIX
4829 && flag_code != CODE_64BIT
4830 && (intel_syntax
40fb9820 4831 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4832 && !intel_float_operand (t->name))
4833 : intel_float_operand (t->name) != 2)
40fb9820 4834 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4835 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4836 && !operand_types[0].bitfield.regymm
4837 && !operand_types[0].bitfield.regzmm)
40fb9820 4838 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4839 && operand_types[t->operands > 1].bitfield.regxmm
4840 && operand_types[t->operands > 1].bitfield.regymm
4841 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4842 && (t->base_opcode != 0x0fc7
4843 || t->extension_opcode != 1 /* cmpxchg8b */))
4844 continue;
4845
192dc9c6
JB		 4846 /* In general, don't allow 32-bit operands on pre-386. */
4847 else if (i.suffix == LONG_MNEM_SUFFIX
4848 && !cpu_arch_flags.bitfield.cpui386
4849 && (intel_syntax
4850 ? (!t->opcode_modifier.ignoresize
4851 && !intel_float_operand (t->name))
4852 : intel_float_operand (t->name) != 2)
4853 && ((!operand_types[0].bitfield.regmmx
4854 && !operand_types[0].bitfield.regxmm)
4855 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4856 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4857 continue;
4858
29b0f896 4859 /* Do not verify operands when there are none. */
50aecf8c 4860 else
29b0f896 4861 {
c6fb90c8 4862 if (!t->operands)
2dbab7d5
L		 4863 /* We've found a match; break out of loop. */
4864 break;
29b0f896 4865 }
252b5132 4866
539e75ad
L		 4867 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4868 into Disp32/Disp16/Disp32 operand. */
4869 if (i.prefix[ADDR_PREFIX] != 0)
4870 {
40fb9820 4871 /* There should be only one Disp operand. */
539e75ad
L		 4872 switch (flag_code)
4873 {
4874 case CODE_16BIT:
40fb9820
L		 4875 for (j = 0; j < MAX_OPERANDS; j++)
4876 {
4877 if (operand_types[j].bitfield.disp16)
4878 {
4879 addr_prefix_disp = j;
4880 operand_types[j].bitfield.disp32 = 1;
4881 operand_types[j].bitfield.disp16 = 0;
4882 break;
4883 }
4884 }
539e75ad
L		 4885 break;
4886 case CODE_32BIT:
40fb9820
L		 4887 for (j = 0; j < MAX_OPERANDS; j++)
4888 {
4889 if (operand_types[j].bitfield.disp32)
4890 {
4891 addr_prefix_disp = j;
4892 operand_types[j].bitfield.disp32 = 0;
4893 operand_types[j].bitfield.disp16 = 1;
4894 break;
4895 }
4896 }
539e75ad
L		 4897 break;
4898 case CODE_64BIT:
40fb9820
L		 4899 for (j = 0; j < MAX_OPERANDS; j++)
4900 {
4901 if (operand_types[j].bitfield.disp64)
4902 {
4903 addr_prefix_disp = j;
4904 operand_types[j].bitfield.disp64 = 0;
4905 operand_types[j].bitfield.disp32 = 1;
4906 break;
4907 }
4908 }
539e75ad
L		 4909 break;
4910 }
539e75ad
L		 4911 }
4912
02a86693
L		 4913 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4914 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4915 continue;
4916
56ffb741
L		 4917 /* We check register size if needed. */
4918 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4919 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4920 switch (t->operands)
4921 {
4922 case 1:
40fb9820 4923 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4924 continue;
4925 break;
4926 case 2:
8b38ad71
L		 4927 /* xchg %eax, %eax is a special case. It is an aliase for nop
4928 only in 32bit mode and we can use opcode 0x90. In 64bit
4929 mode, we can't use 0x90 for xchg %eax, %eax since it should
4930 zero-extend %eax to %rax. */
4931 if (flag_code == CODE_64BIT
4932 && t->base_opcode == 0x90
0dfbf9d7
L		 4933 && operand_type_equal (&i.types [0], &acc32)
4934 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4935 continue;
b6169b20
L		 4936 if (i.swap_operand)
4937 {
4938 /* If we swap operand in encoding, we either match
4939 the next one or reverse direction of operands. */
4940 if (t->opcode_modifier.s)
4941 continue;
4942 else if (t->opcode_modifier.d)
4943 goto check_reverse;
4944 }
4945
29b0f896 4946 case 3:
fa99fab2
L		 4947 /* If we swap operand in encoding, we match the next one. */
4948 if (i.swap_operand && t->opcode_modifier.s)
4949 continue;
f48ff2ae 4950 case 4:
c0f3af97 4951 case 5:
c6fb90c8 4952 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4953 if (!operand_type_match (overlap0, i.types[0])
4954 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4955 || (check_register
4956 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4957 operand_types[0],
4958 overlap1, i.types[1],
4959 operand_types[1])))
29b0f896
AM		 4960 {
4961 /* Check if other direction is valid ... */
40fb9820 4962 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4963 continue;
4964
b6169b20 4965check_reverse:
29b0f896 4966 /* Try reversing direction of operands. */
c6fb90c8
L		 4967 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4968 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4969 if (!operand_type_match (overlap0, i.types[0])
4970 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4971 || (check_register
4972 && !operand_type_register_match (overlap0,
4973 i.types[0],
4974 operand_types[1],
4975 overlap1,
4976 i.types[1],
4977 operand_types[0])))
29b0f896
AM		 4978 {
4979 /* Does not match either direction. */
4980 continue;
4981 }
4982 /* found_reverse_match holds which of D or FloatDR
4983 we've found. */
40fb9820 4984 if (t->opcode_modifier.d)
8a2ed489 4985 found_reverse_match = Opcode_D;
40fb9820 4986 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4987 found_reverse_match = Opcode_FloatD;
4988 else
4989 found_reverse_match = 0;
40fb9820 4990 if (t->opcode_modifier.floatr)
8a2ed489 4991 found_reverse_match |= Opcode_FloatR;
29b0f896 4992 }
f48ff2ae 4993 else
29b0f896 4994 {
f48ff2ae 4995 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4996 switch (t->operands)
4997 {
c0f3af97
L		 4998 case 5:
4999 overlap4 = operand_type_and (i.types[4],
5000 operand_types[4]);
d1cbb4db 5001 case 4:
c6fb90c8
L		 5002 overlap3 = operand_type_and (i.types[3],
5003 operand_types[3]);
d1cbb4db 5004 case 3:
c6fb90c8
L		 5005 overlap2 = operand_type_and (i.types[2],
5006 operand_types[2]);
d1cbb4db
L		 5007 break;
5008 }
29b0f896 5009
f48ff2ae
L		 5010 switch (t->operands)
5011 {
c0f3af97
L		 5012 case 5:
5013 if (!operand_type_match (overlap4, i.types[4])
5014 || !operand_type_register_match (overlap3,
5015 i.types[3],
5016 operand_types[3],
5017 overlap4,
5018 i.types[4],
5019 operand_types[4]))
5020 continue;
f48ff2ae 5021 case 4:
40fb9820 5022 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5023 || (check_register
5024 && !operand_type_register_match (overlap2,
5025 i.types[2],
5026 operand_types[2],
5027 overlap3,
5028 i.types[3],
5029 operand_types[3])))
f48ff2ae
L		 5030 continue;
5031 case 3:
5032 /* Here we make use of the fact that there are no
5033 reverse match 3 operand instructions, and all 3
5034 operand instructions only need to be checked for
5035 register consistency between operands 2 and 3. */
40fb9820 5036 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5037 || (check_register
5038 && !operand_type_register_match (overlap1,
5039 i.types[1],
5040 operand_types[1],
5041 overlap2,
5042 i.types[2],
5043 operand_types[2])))
f48ff2ae
L		 5044 continue;
5045 break;
5046 }
29b0f896 5047 }
f48ff2ae 5048 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5049 slip through to break. */
5050 }
3629bb00 5051 if (!found_cpu_match)
29b0f896
AM		 5052 {
5053 found_reverse_match = 0;
5054 continue;
5055 }
c0f3af97 5056
5614d22c
JB		 5057 /* Check if vector and VEX operands are valid. */
5058 if (check_VecOperands (t) || VEX_check_operands (t))
5059 {
5060 specific_error = i.error;
5061 continue;
5062 }
a683cc34 5063
29b0f896
AM		 5064 /* We've found a match; break out of loop. */
5065 break;
5066 }
5067
5068 if (t == current_templates->end)
5069 {
5070 /* We found no match. */
a65babc9 5071 const char *err_msg;
5614d22c 5072 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5073 {
5074 default:
5075 abort ();
86e026a4 5076 case operand_size_mismatch:
a65babc9
L		 5077 err_msg = _("operand size mismatch");
5078 break;
5079 case operand_type_mismatch:
5080 err_msg = _("operand type mismatch");
5081 break;
5082 case register_type_mismatch:
5083 err_msg = _("register type mismatch");
5084 break;
5085 case number_of_operands_mismatch:
5086 err_msg = _("number of operands mismatch");
5087 break;
5088 case invalid_instruction_suffix:
5089 err_msg = _("invalid instruction suffix");
5090 break;
5091 case bad_imm4:
4a2608e3 5092 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5093 break;
5094 case old_gcc_only:
5095 err_msg = _("only supported with old gcc");
5096 break;
5097 case unsupported_with_intel_mnemonic:
5098 err_msg = _("unsupported with Intel mnemonic");
5099 break;
5100 case unsupported_syntax:
5101 err_msg = _("unsupported syntax");
5102 break;
5103 case unsupported:
35262a23 5104 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5105 current_templates->start->name);
5106 return NULL;
6c30d220
L		 5107 case invalid_vsib_address:
5108 err_msg = _("invalid VSIB address");
5109 break;
7bab8ab5
JB		 5110 case invalid_vector_register_set:
5111 err_msg = _("mask, index, and destination registers must be distinct");
5112 break;
6c30d220
L		 5113 case unsupported_vector_index_register:
5114 err_msg = _("unsupported vector index register");
5115 break;
43234a1e
L		 5116 case unsupported_broadcast:
5117 err_msg = _("unsupported broadcast");
5118 break;
5119 case broadcast_not_on_src_operand:
5120 err_msg = _("broadcast not on source memory operand");
5121 break;
5122 case broadcast_needed:
5123 err_msg = _("broadcast is needed for operand of such type");
5124 break;
5125 case unsupported_masking:
5126 err_msg = _("unsupported masking");
5127 break;
5128 case mask_not_on_destination:
5129 err_msg = _("mask not on destination operand");
5130 break;
5131 case no_default_mask:
5132 err_msg = _("default mask isn't allowed");
5133 break;
5134 case unsupported_rc_sae:
5135 err_msg = _("unsupported static rounding/sae");
5136 break;
5137 case rc_sae_operand_not_last_imm:
5138 if (intel_syntax)
5139 err_msg = _("RC/SAE operand must precede immediate operands");
5140 else
5141 err_msg = _("RC/SAE operand must follow immediate operands");
5142 break;
5143 case invalid_register_operand:
5144 err_msg = _("invalid register operand");
5145 break;
a65babc9
L		 5146 }
5147 as_bad (_("%s for `%s'"), err_msg,
891edac4 5148 current_templates->start->name);
fa99fab2 5149 return NULL;
29b0f896 5150 }
252b5132 5151
29b0f896
AM		 5152 if (!quiet_warnings)
5153 {
5154 if (!intel_syntax
40fb9820
L		 5155 && (i.types[0].bitfield.jumpabsolute
5156 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5157 {
5158 as_warn (_("indirect %s without `*'"), t->name);
5159 }
5160
40fb9820
L		 5161 if (t->opcode_modifier.isprefix
5162 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5163 {
5164 /* Warn them that a data or address size prefix doesn't
5165 affect assembly of the next line of code. */
5166 as_warn (_("stand-alone `%s' prefix"), t->name);
5167 }
5168 }
5169
5170 /* Copy the template we found. */
5171 i.tm = *t;
539e75ad
L		 5172
5173 if (addr_prefix_disp != -1)
5174 i.tm.operand_types[addr_prefix_disp]
5175 = operand_types[addr_prefix_disp];
5176
29b0f896
AM		 5177 if (found_reverse_match)
5178 {
5179 /* If we found a reverse match we must alter the opcode
5180 direction bit. found_reverse_match holds bits to change
5181 (different for int & float insns). */
5182
5183 i.tm.base_opcode ^= found_reverse_match;
5184
539e75ad
L		 5185 i.tm.operand_types[0] = operand_types[1];
5186 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5187 }
5188
fa99fab2 5189 return t;
29b0f896
AM		 5190}
5191
5192static int
e3bb37b5 5193check_string (void)
29b0f896 5194{
40fb9820
L		 5195 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5196 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5197 {
5198 if (i.seg[0] != NULL && i.seg[0] != &es)
5199 {
a87af027 5200 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5201 i.tm.name,
a87af027
JB		 5202 mem_op + 1,
5203 register_prefix);
29b0f896
AM		 5204 return 0;
5205 }
5206 /* There's only ever one segment override allowed per instruction.
5207 This instruction possibly has a legal segment override on the
5208 second operand, so copy the segment to where non-string
5209 instructions store it, allowing common code. */
5210 i.seg[0] = i.seg[1];
5211 }
40fb9820 5212 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5213 {
5214 if (i.seg[1] != NULL && i.seg[1] != &es)
5215 {
a87af027 5216 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5217 i.tm.name,
a87af027
JB		 5218 mem_op + 2,
5219 register_prefix);
29b0f896
AM		 5220 return 0;
5221 }
5222 }
5223 return 1;
5224}
5225
5226static int
543613e9 5227process_suffix (void)
29b0f896
AM		 5228{
5229 /* If matched instruction specifies an explicit instruction mnemonic
5230 suffix, use it. */
40fb9820
L		 5231 if (i.tm.opcode_modifier.size16)
5232 i.suffix = WORD_MNEM_SUFFIX;
5233 else if (i.tm.opcode_modifier.size32)
5234 i.suffix = LONG_MNEM_SUFFIX;
5235 else if (i.tm.opcode_modifier.size64)
5236 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5237 else if (i.reg_operands)
5238 {
5239 /* If there's no instruction mnemonic suffix we try to invent one
5240 based on register operands. */
5241 if (!i.suffix)
5242 {
5243 /* We take i.suffix from the last register operand specified,
5244 Destination register type is more significant than source
381d071f
L		 5245 register type. crc32 in SSE4.2 prefers source register
5246 type. */
5247 if (i.tm.base_opcode == 0xf20f38f1)
5248 {
40fb9820
L		 5249 if (i.types[0].bitfield.reg16)
5250 i.suffix = WORD_MNEM_SUFFIX;
5251 else if (i.types[0].bitfield.reg32)
5252 i.suffix = LONG_MNEM_SUFFIX;
5253 else if (i.types[0].bitfield.reg64)
5254 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5255 }
9344ff29 5256 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5257 {
40fb9820 5258 if (i.types[0].bitfield.reg8)
20592a94
L		 5259 i.suffix = BYTE_MNEM_SUFFIX;
5260 }
381d071f
L		 5261
5262 if (!i.suffix)
5263 {
5264 int op;
5265
20592a94
L		 5266 if (i.tm.base_opcode == 0xf20f38f1
5267 || i.tm.base_opcode == 0xf20f38f0)
5268 {
5269 /* We have to know the operand size for crc32. */
5270 as_bad (_("ambiguous memory operand size for `%s`"),
5271 i.tm.name);
5272 return 0;
5273 }
5274
381d071f 5275 for (op = i.operands; --op >= 0;)
40fb9820 5276 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5277 {
40fb9820
L		 5278 if (i.types[op].bitfield.reg8)
5279 {
5280 i.suffix = BYTE_MNEM_SUFFIX;
5281 break;
5282 }
5283 else if (i.types[op].bitfield.reg16)
5284 {
5285 i.suffix = WORD_MNEM_SUFFIX;
5286 break;
5287 }
5288 else if (i.types[op].bitfield.reg32)
5289 {
5290 i.suffix = LONG_MNEM_SUFFIX;
5291 break;
5292 }
5293 else if (i.types[op].bitfield.reg64)
5294 {
5295 i.suffix = QWORD_MNEM_SUFFIX;
5296 break;
5297 }
381d071f
L		 5298 }
5299 }
29b0f896
AM		 5300 }
5301 else if (i.suffix == BYTE_MNEM_SUFFIX)
5302 {
2eb952a4
L		 5303 if (intel_syntax
5304 && i.tm.opcode_modifier.ignoresize
5305 && i.tm.opcode_modifier.no_bsuf)
5306 i.suffix = 0;
5307 else if (!check_byte_reg ())
29b0f896
AM		 5308 return 0;
5309 }
5310 else if (i.suffix == LONG_MNEM_SUFFIX)
5311 {
2eb952a4
L		 5312 if (intel_syntax
5313 && i.tm.opcode_modifier.ignoresize
5314 && i.tm.opcode_modifier.no_lsuf)
5315 i.suffix = 0;
5316 else if (!check_long_reg ())
29b0f896
AM		 5317 return 0;
5318 }
5319 else if (i.suffix == QWORD_MNEM_SUFFIX)
5320 {
955e1e6a
L		 5321 if (intel_syntax
5322 && i.tm.opcode_modifier.ignoresize
5323 && i.tm.opcode_modifier.no_qsuf)
5324 i.suffix = 0;
5325 else if (!check_qword_reg ())
29b0f896
AM		 5326 return 0;
5327 }
5328 else if (i.suffix == WORD_MNEM_SUFFIX)
5329 {
2eb952a4
L		 5330 if (intel_syntax
5331 && i.tm.opcode_modifier.ignoresize
5332 && i.tm.opcode_modifier.no_wsuf)
5333 i.suffix = 0;
5334 else if (!check_word_reg ())
29b0f896
AM		 5335 return 0;
5336 }
c0f3af97 5337 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5338 || i.suffix == YMMWORD_MNEM_SUFFIX
5339 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5340 {
43234a1e 5341 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5342 should check if it is a valid suffix. */
5343 }
40fb9820 5344 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5345 /* Do nothing if the instruction is going to ignore the prefix. */
5346 ;
5347 else
5348 abort ();
5349 }
40fb9820 5350 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5351 && !i.suffix
5352 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5353 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5354 {
5355 i.suffix = stackop_size;
5356 }
9306ca4a
JB		 5357 else if (intel_syntax
5358 && !i.suffix
40fb9820
L		 5359 && (i.tm.operand_types[0].bitfield.jumpabsolute
5360 || i.tm.opcode_modifier.jumpbyte
5361 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5362 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5363 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5364 {
5365 switch (flag_code)
5366 {
5367 case CODE_64BIT:
40fb9820 5368 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5369 {
5370 i.suffix = QWORD_MNEM_SUFFIX;
5371 break;
5372 }
5373 case CODE_32BIT:
40fb9820 5374 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5375 i.suffix = LONG_MNEM_SUFFIX;
5376 break;
5377 case CODE_16BIT:
40fb9820 5378 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5379 i.suffix = WORD_MNEM_SUFFIX;
5380 break;
5381 }
5382 }
252b5132 5383
9306ca4a 5384 if (!i.suffix)
29b0f896 5385 {
9306ca4a
JB		 5386 if (!intel_syntax)
5387 {
40fb9820 5388 if (i.tm.opcode_modifier.w)
9306ca4a 5389 {
4eed87de
AM		 5390 as_bad (_("no instruction mnemonic suffix given and "
5391 "no register operands; can't size instruction"));
9306ca4a
JB		 5392 return 0;
5393 }
5394 }
5395 else
5396 {
40fb9820 5397 unsigned int suffixes;
7ab9ffdd 5398
40fb9820
L		 5399 suffixes = !i.tm.opcode_modifier.no_bsuf;
5400 if (!i.tm.opcode_modifier.no_wsuf)
5401 suffixes |= 1 << 1;
5402 if (!i.tm.opcode_modifier.no_lsuf)
5403 suffixes |= 1 << 2;
fc4adea1 5404 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5405 suffixes |= 1 << 3;
5406 if (!i.tm.opcode_modifier.no_ssuf)
5407 suffixes |= 1 << 4;
5408 if (!i.tm.opcode_modifier.no_qsuf)
5409 suffixes |= 1 << 5;
5410
5411 /* There are more than suffix matches. */
5412 if (i.tm.opcode_modifier.w
9306ca4a 5413 || ((suffixes & (suffixes - 1))
40fb9820
L		 5414 && !i.tm.opcode_modifier.defaultsize
5415 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5416 {
5417 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5418 return 0;
5419 }
5420 }
29b0f896 5421 }
252b5132 5422
9306ca4a
JB		 5423 /* Change the opcode based on the operand size given by i.suffix;
5424 We don't need to change things for byte insns. */
5425
582d5edd
L		 5426 if (i.suffix
5427 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5428 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5429 && i.suffix != YMMWORD_MNEM_SUFFIX
5430 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5431 {
5432 /* It's not a byte, select word/dword operation. */
40fb9820 5433 if (i.tm.opcode_modifier.w)
29b0f896 5434 {
40fb9820 5435 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5436 i.tm.base_opcode |= 8;
5437 else
5438 i.tm.base_opcode |= 1;
5439 }
0f3f3d8b 5440
29b0f896
AM		 5441 /* Now select between word & dword operations via the operand
5442 size prefix, except for instructions that will ignore this
5443 prefix anyway. */
ca61edf2 5444 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5445 {
ca61edf2
L		 5446 /* The address size override prefix changes the size of the
5447 first operand. */
40fb9820
L		 5448 if ((flag_code == CODE_32BIT
5449 && i.op->regs[0].reg_type.bitfield.reg16)
5450 || (flag_code != CODE_32BIT
5451 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5452 if (!add_prefix (ADDR_PREFIX_OPCODE))
5453 return 0;
5454 }
5455 else if (i.suffix != QWORD_MNEM_SUFFIX
5456 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5457 && !i.tm.opcode_modifier.ignoresize
5458 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5459 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5460 || (flag_code == CODE_64BIT
40fb9820 5461 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5462 {
5463 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5464
40fb9820 5465 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5466 prefix = ADDR_PREFIX_OPCODE;
252b5132 5467
29b0f896
AM		 5468 if (!add_prefix (prefix))
5469 return 0;
24eab124 5470 }
252b5132 5471
29b0f896
AM		 5472 /* Set mode64 for an operand. */
5473 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5474 && flag_code == CODE_64BIT
40fb9820 5475 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5476 {
5477 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5478 need rex64. cmpxchg8b is also a special case. */
5479 if (! (i.operands == 2
5480 && i.tm.base_opcode == 0x90
5481 && i.tm.extension_opcode == None
0dfbf9d7
L		 5482 && operand_type_equal (&i.types [0], &acc64)
5483 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5484 && ! (i.operands == 1
5485 && i.tm.base_opcode == 0xfc7
5486 && i.tm.extension_opcode == 1
40fb9820
L		 5487 && !operand_type_check (i.types [0], reg)
5488 && operand_type_check (i.types [0], anymem)))
f6bee062 5489 i.rex |= REX_W;
46e883c5 5490 }
3e73aa7c 5491
29b0f896
AM		 5492 /* Size floating point instruction. */
5493 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5494 if (i.tm.opcode_modifier.floatmf)
543613e9 5495 i.tm.base_opcode ^= 4;
29b0f896 5496 }
7ecd2f8b 5497
29b0f896
AM		 5498 return 1;
5499}
3e73aa7c 5500
29b0f896 5501static int
543613e9 5502check_byte_reg (void)
29b0f896
AM		 5503{
5504 int op;
543613e9 5505
29b0f896
AM		 5506 for (op = i.operands; --op >= 0;)
5507 {
5508 /* If this is an eight bit register, it's OK. If it's the 16 or
5509 32 bit version of an eight bit register, we will just use the
5510 low portion, and that's OK too. */
40fb9820 5511 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5512 continue;
5513
5a819eb9
JB		 5514 /* I/O port address operands are OK too. */
5515 if (i.tm.operand_types[op].bitfield.inoutportreg)
5516 continue;
5517
9344ff29
L		 5518 /* crc32 doesn't generate this warning. */
5519 if (i.tm.base_opcode == 0xf20f38f0)
5520 continue;
5521
40fb9820
L		 5522 if ((i.types[op].bitfield.reg16
5523 || i.types[op].bitfield.reg32
5524 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5525 && i.op[op].regs->reg_num < 4
5526 /* Prohibit these changes in 64bit mode, since the lowering
5527 would be more complicated. */
5528 && flag_code != CODE_64BIT)
29b0f896 5529 {
29b0f896 5530#if REGISTER_WARNINGS
5a819eb9 5531 if (!quiet_warnings)
a540244d
L		 5532 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5533 register_prefix,
40fb9820 5534 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5535 ? REGNAM_AL - REGNAM_AX
5536 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5537 register_prefix,
29b0f896
AM		 5538 i.op[op].regs->reg_name,
5539 i.suffix);
5540#endif
5541 continue;
5542 }
5543 /* Any other register is bad. */
40fb9820
L		 5544 if (i.types[op].bitfield.reg16
5545 || i.types[op].bitfield.reg32
5546 || i.types[op].bitfield.reg64
5547 || i.types[op].bitfield.regmmx
5548 || i.types[op].bitfield.regxmm
c0f3af97 5549 || i.types[op].bitfield.regymm
43234a1e 5550 || i.types[op].bitfield.regzmm
40fb9820
L		 5551 || i.types[op].bitfield.sreg2
5552 || i.types[op].bitfield.sreg3
5553 || i.types[op].bitfield.control
5554 || i.types[op].bitfield.debug
5555 || i.types[op].bitfield.test
5556 || i.types[op].bitfield.floatreg
5557 || i.types[op].bitfield.floatacc)
29b0f896 5558 {
a540244d
L		 5559 as_bad (_("`%s%s' not allowed with `%s%c'"),
5560 register_prefix,
29b0f896
AM		 5561 i.op[op].regs->reg_name,
5562 i.tm.name,
5563 i.suffix);
5564 return 0;
5565 }
5566 }
5567 return 1;
5568}
5569
5570static int
e3bb37b5 5571check_long_reg (void)
29b0f896
AM		 5572{
5573 int op;
5574
5575 for (op = i.operands; --op >= 0;)
5576 /* Reject eight bit registers, except where the template requires
5577 them. (eg. movzb) */
40fb9820
L		 5578 if (i.types[op].bitfield.reg8
5579 && (i.tm.operand_types[op].bitfield.reg16
5580 || i.tm.operand_types[op].bitfield.reg32
5581 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5582 {
a540244d
L		 5583 as_bad (_("`%s%s' not allowed with `%s%c'"),
5584 register_prefix,
29b0f896
AM		 5585 i.op[op].regs->reg_name,
5586 i.tm.name,
5587 i.suffix);
5588 return 0;
5589 }
e4630f71 5590 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5591 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5592 && i.types[op].bitfield.reg16
5593 && (i.tm.operand_types[op].bitfield.reg32
5594 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5595 {
5596 /* Prohibit these changes in the 64bit mode, since the
5597 lowering is more complicated. */
5598 if (flag_code == CODE_64BIT)
252b5132 5599 {
2b5d6a91 5600 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5601 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5602 i.suffix);
5603 return 0;
252b5132 5604 }
29b0f896 5605#if REGISTER_WARNINGS
cecf1424
JB		 5606 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5607 register_prefix,
5608 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5609 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5610#endif
252b5132 5611 }
e4630f71 5612 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5613 else if (i.types[op].bitfield.reg64
5614 && (i.tm.operand_types[op].bitfield.reg32
5615 || i.tm.operand_types[op].bitfield.acc))
252b5132 5616 {
34828aad 5617 if (intel_syntax
ca61edf2 5618 && i.tm.opcode_modifier.toqword
40fb9820 5619 && !i.types[0].bitfield.regxmm)
34828aad 5620 {
ca61edf2 5621 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5622 i.suffix = QWORD_MNEM_SUFFIX;
5623 }
5624 else
5625 {
2b5d6a91 5626 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5627 register_prefix, i.op[op].regs->reg_name,
5628 i.suffix);
5629 return 0;
5630 }
29b0f896
AM		 5631 }
5632 return 1;
5633}
252b5132 5634
29b0f896 5635static int
e3bb37b5 5636check_qword_reg (void)
29b0f896
AM		 5637{
5638 int op;
252b5132 5639
29b0f896
AM		 5640 for (op = i.operands; --op >= 0; )
5641 /* Reject eight bit registers, except where the template requires
5642 them. (eg. movzb) */
40fb9820
L		 5643 if (i.types[op].bitfield.reg8
5644 && (i.tm.operand_types[op].bitfield.reg16
5645 || i.tm.operand_types[op].bitfield.reg32
5646 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5647 {
a540244d
L		 5648 as_bad (_("`%s%s' not allowed with `%s%c'"),
5649 register_prefix,
29b0f896
AM		 5650 i.op[op].regs->reg_name,
5651 i.tm.name,
5652 i.suffix);
5653 return 0;
5654 }
e4630f71 5655 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5656 else if ((i.types[op].bitfield.reg16
5657 || i.types[op].bitfield.reg32)
33d0ab95 5658 && (i.tm.operand_types[op].bitfield.reg64
40fb9820 5659 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5660 {
5661 /* Prohibit these changes in the 64bit mode, since the
5662 lowering is more complicated. */
34828aad 5663 if (intel_syntax
ca61edf2 5664 && i.tm.opcode_modifier.todword
40fb9820 5665 && !i.types[0].bitfield.regxmm)
34828aad 5666 {
ca61edf2 5667 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5668 i.suffix = LONG_MNEM_SUFFIX;
5669 }
5670 else
5671 {
2b5d6a91 5672 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5673 register_prefix, i.op[op].regs->reg_name,
5674 i.suffix);
5675 return 0;
5676 }
252b5132 5677 }
29b0f896
AM		 5678 return 1;
5679}
252b5132 5680
29b0f896 5681static int
e3bb37b5 5682check_word_reg (void)
29b0f896
AM		 5683{
5684 int op;
5685 for (op = i.operands; --op >= 0;)
5686 /* Reject eight bit registers, except where the template requires
5687 them. (eg. movzb) */
40fb9820
L		 5688 if (i.types[op].bitfield.reg8
5689 && (i.tm.operand_types[op].bitfield.reg16
5690 || i.tm.operand_types[op].bitfield.reg32
5691 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5692 {
a540244d
L		 5693 as_bad (_("`%s%s' not allowed with `%s%c'"),
5694 register_prefix,
29b0f896
AM		 5695 i.op[op].regs->reg_name,
5696 i.tm.name,
5697 i.suffix);
5698 return 0;
5699 }
e4630f71 5700 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5701 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5702 && (i.types[op].bitfield.reg32
5703 || i.types[op].bitfield.reg64)
40fb9820
L		 5704 && (i.tm.operand_types[op].bitfield.reg16
5705 || i.tm.operand_types[op].bitfield.acc))
252b5132 5706 {
29b0f896
AM		 5707 /* Prohibit these changes in the 64bit mode, since the
5708 lowering is more complicated. */
5709 if (flag_code == CODE_64BIT)
252b5132 5710 {
2b5d6a91 5711 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5712 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5713 i.suffix);
5714 return 0;
252b5132 5715 }
29b0f896 5716#if REGISTER_WARNINGS
cecf1424
JB		 5717 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5718 register_prefix,
5719 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5720 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5721#endif
5722 }
5723 return 1;
5724}
252b5132 5725
29b0f896 5726static int
40fb9820 5727update_imm (unsigned int j)
29b0f896 5728{
bc0844ae 5729 i386_operand_type overlap = i.types[j];
40fb9820
L		 5730 if ((overlap.bitfield.imm8
5731 || overlap.bitfield.imm8s
5732 || overlap.bitfield.imm16
5733 || overlap.bitfield.imm32
5734 || overlap.bitfield.imm32s
5735 || overlap.bitfield.imm64)
0dfbf9d7
L		 5736 && !operand_type_equal (&overlap, &imm8)
5737 && !operand_type_equal (&overlap, &imm8s)
5738 && !operand_type_equal (&overlap, &imm16)
5739 && !operand_type_equal (&overlap, &imm32)
5740 && !operand_type_equal (&overlap, &imm32s)
5741 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5742 {
5743 if (i.suffix)
5744 {
40fb9820
L		 5745 i386_operand_type temp;
5746
0dfbf9d7 5747 operand_type_set (&temp, 0);
7ab9ffdd 5748 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5749 {
5750 temp.bitfield.imm8 = overlap.bitfield.imm8;
5751 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5752 }
5753 else if (i.suffix == WORD_MNEM_SUFFIX)
5754 temp.bitfield.imm16 = overlap.bitfield.imm16;
5755 else if (i.suffix == QWORD_MNEM_SUFFIX)
5756 {
5757 temp.bitfield.imm64 = overlap.bitfield.imm64;
5758 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5759 }
5760 else
5761 temp.bitfield.imm32 = overlap.bitfield.imm32;
5762 overlap = temp;
29b0f896 5763 }
0dfbf9d7
L		 5764 else if (operand_type_equal (&overlap, &imm16_32_32s)
5765 || operand_type_equal (&overlap, &imm16_32)
5766 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5767 {
40fb9820 5768 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5769 overlap = imm16;
40fb9820 5770 else
65da13b5 5771 overlap = imm32s;
29b0f896 5772 }
0dfbf9d7
L		 5773 if (!operand_type_equal (&overlap, &imm8)
5774 && !operand_type_equal (&overlap, &imm8s)
5775 && !operand_type_equal (&overlap, &imm16)
5776 && !operand_type_equal (&overlap, &imm32)
5777 && !operand_type_equal (&overlap, &imm32s)
5778 && !operand_type_equal (&overlap, &imm64))
29b0f896 5779 {
4eed87de
AM		 5780 as_bad (_("no instruction mnemonic suffix given; "
5781 "can't determine immediate size"));
29b0f896
AM		 5782 return 0;
5783 }
5784 }
40fb9820 5785 i.types[j] = overlap;
29b0f896 5786
40fb9820
L		 5787 return 1;
5788}
5789
5790static int
5791finalize_imm (void)
5792{
bc0844ae 5793 unsigned int j, n;
29b0f896 5794
bc0844ae
L		 5795 /* Update the first 2 immediate operands. */
5796 n = i.operands > 2 ? 2 : i.operands;
5797 if (n)
5798 {
5799 for (j = 0; j < n; j++)
5800 if (update_imm (j) == 0)
5801 return 0;
40fb9820 5802
bc0844ae
L		 5803 /* The 3rd operand can't be immediate operand. */
5804 gas_assert (operand_type_check (i.types[2], imm) == 0);
5805 }
29b0f896
AM		 5806
5807 return 1;
5808}
5809
c0f3af97
L		 5810static int
5811bad_implicit_operand (int xmm)
5812{
91d6fa6a
NC		 5813 const char *ireg = xmm ? "xmm0" : "ymm0";
5814
c0f3af97
L		 5815 if (intel_syntax)
5816 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5817 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5818 else
5819 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5820 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5821 return 0;
5822}
5823
29b0f896 5824static int
e3bb37b5 5825process_operands (void)
29b0f896
AM		 5826{
5827 /* Default segment register this instruction will use for memory
5828 accesses. 0 means unknown. This is only for optimizing out
5829 unnecessary segment overrides. */
5830 const seg_entry *default_seg = 0;
5831
2426c15f 5832 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5833 {
91d6fa6a
NC		 5834 unsigned int dupl = i.operands;
5835 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5836 unsigned int j;
5837
c0f3af97 5838 /* The destination must be an xmm register. */
9c2799c2 5839 gas_assert (i.reg_operands
91d6fa6a 5840 && MAX_OPERANDS > dupl
7ab9ffdd 5841 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5842
5843 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5844 {
c0f3af97 5845 /* The first operand is implicit and must be xmm0. */
9c2799c2 5846 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5847 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5848 return bad_implicit_operand (1);
5849
8cd7925b 5850 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5851 {
5852 /* Keep xmm0 for instructions with VEX prefix and 3
5853 sources. */
5854 goto duplicate;
5855 }
e2ec9d29 5856 else
c0f3af97
L		 5857 {
5858 /* We remove the first xmm0 and keep the number of
5859 operands unchanged, which in fact duplicates the
5860 destination. */
5861 for (j = 1; j < i.operands; j++)
5862 {
5863 i.op[j - 1] = i.op[j];
5864 i.types[j - 1] = i.types[j];
5865 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5866 }
5867 }
5868 }
5869 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5870 {
91d6fa6a 5871 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5872 && (i.tm.opcode_modifier.vexsources
5873 == VEX3SOURCES));
c0f3af97
L		 5874
5875 /* Add the implicit xmm0 for instructions with VEX prefix
5876 and 3 sources. */
5877 for (j = i.operands; j > 0; j--)
5878 {
5879 i.op[j] = i.op[j - 1];
5880 i.types[j] = i.types[j - 1];
5881 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5882 }
5883 i.op[0].regs
5884 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5885 i.types[0] = regxmm;
c0f3af97
L		 5886 i.tm.operand_types[0] = regxmm;
5887
5888 i.operands += 2;
5889 i.reg_operands += 2;
5890 i.tm.operands += 2;
5891
91d6fa6a 5892 dupl++;
c0f3af97 5893 dest++;
91d6fa6a
NC		 5894 i.op[dupl] = i.op[dest];
5895 i.types[dupl] = i.types[dest];
5896 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5897 }
c0f3af97
L		 5898 else
5899 {
5900duplicate:
5901 i.operands++;
5902 i.reg_operands++;
5903 i.tm.operands++;
5904
91d6fa6a
NC		 5905 i.op[dupl] = i.op[dest];
5906 i.types[dupl] = i.types[dest];
5907 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5908 }
5909
5910 if (i.tm.opcode_modifier.immext)
5911 process_immext ();
5912 }
5913 else if (i.tm.opcode_modifier.firstxmm0)
5914 {
5915 unsigned int j;
5916
43234a1e 5917 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5918 gas_assert (i.reg_operands
7ab9ffdd 5919 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5920 || operand_type_equal (&i.types[0], &regymm)
5921 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5922 if (register_number (i.op[0].regs) != 0)
c0f3af97 5923 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5924
5925 for (j = 1; j < i.operands; j++)
5926 {
5927 i.op[j - 1] = i.op[j];
5928 i.types[j - 1] = i.types[j];
5929
5930 /* We need to adjust fields in i.tm since they are used by
5931 build_modrm_byte. */
5932 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5933 }
5934
e2ec9d29
L		 5935 i.operands--;
5936 i.reg_operands--;
e2ec9d29
L		 5937 i.tm.operands--;
5938 }
5939 else if (i.tm.opcode_modifier.regkludge)
5940 {
5941 /* The imul $imm, %reg instruction is converted into
5942 imul $imm, %reg, %reg, and the clr %reg instruction
5943 is converted into xor %reg, %reg. */
5944
5945 unsigned int first_reg_op;
5946
5947 if (operand_type_check (i.types[0], reg))
5948 first_reg_op = 0;
5949 else
5950 first_reg_op = 1;
5951 /* Pretend we saw the extra register operand. */
9c2799c2 5952 gas_assert (i.reg_operands == 1
7ab9ffdd 5953 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5954 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5955 i.types[first_reg_op + 1] = i.types[first_reg_op];
5956 i.operands++;
5957 i.reg_operands++;
29b0f896
AM		 5958 }
5959
40fb9820 5960 if (i.tm.opcode_modifier.shortform)
29b0f896 5961 {
40fb9820
L		 5962 if (i.types[0].bitfield.sreg2
5963 || i.types[0].bitfield.sreg3)
29b0f896 5964 {
4eed87de
AM		 5965 if (i.tm.base_opcode == POP_SEG_SHORT
5966 && i.op[0].regs->reg_num == 1)
29b0f896 5967 {
a87af027 5968 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5969 return 0;
29b0f896 5970 }
4eed87de
AM		 5971 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5972 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5973 i.rex |= REX_B;
4eed87de
AM		 5974 }
5975 else
5976 {
7ab9ffdd 5977 /* The register or float register operand is in operand
85f10a01 5978 0 or 1. */
40fb9820 5979 unsigned int op;
7ab9ffdd
L		 5980
5981 if (i.types[0].bitfield.floatreg
5982 || operand_type_check (i.types[0], reg))
5983 op = 0;
5984 else
5985 op = 1;
4eed87de
AM		 5986 /* Register goes in low 3 bits of opcode. */
5987 i.tm.base_opcode |= i.op[op].regs->reg_num;
5988 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5989 i.rex |= REX_B;
40fb9820 5990 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5991 {
4eed87de
AM		 5992 /* Warn about some common errors, but press on regardless.
5993 The first case can be generated by gcc (<= 2.8.1). */
5994 if (i.operands == 2)
5995 {
5996 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5997 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5998 register_prefix, i.op[!intel_syntax].regs->reg_name,
5999 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6000 }
6001 else
6002 {
6003 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6004 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6005 register_prefix, i.op[0].regs->reg_name);
4eed87de 6006 }
29b0f896
AM		 6007 }
6008 }
6009 }
40fb9820 6010 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6011 {
6012 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6013 must be put into the modrm byte). Now, we make the modrm and
6014 index base bytes based on all the info we've collected. */
29b0f896
AM		 6015
6016 default_seg = build_modrm_byte ();
6017 }
8a2ed489 6018 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6019 {
6020 default_seg = &ds;
6021 }
40fb9820 6022 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6023 {
6024 /* For the string instructions that allow a segment override
6025 on one of their operands, the default segment is ds. */
6026 default_seg = &ds;
6027 }
6028
75178d9d
L		 6029 if (i.tm.base_opcode == 0x8d /* lea */
6030 && i.seg[0]
6031 && !quiet_warnings)
30123838 6032 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6033
6034 /* If a segment was explicitly specified, and the specified segment
6035 is not the default, use an opcode prefix to select it. If we
6036 never figured out what the default segment is, then default_seg
6037 will be zero at this point, and the specified segment prefix will
6038 always be used. */
29b0f896
AM		 6039 if ((i.seg[0]) && (i.seg[0] != default_seg))
6040 {
6041 if (!add_prefix (i.seg[0]->seg_prefix))
6042 return 0;
6043 }
6044 return 1;
6045}
6046
6047static const seg_entry *
e3bb37b5 6048build_modrm_byte (void)
29b0f896
AM		 6049{
6050 const seg_entry *default_seg = 0;
c0f3af97 6051 unsigned int source, dest;
8cd7925b 6052 int vex_3_sources;
c0f3af97
L		 6053
6054 /* The first operand of instructions with VEX prefix and 3 sources
6055 must be VEX_Imm4. */
8cd7925b 6056 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6057 if (vex_3_sources)
6058 {
91d6fa6a 6059 unsigned int nds, reg_slot;
4c2c6516 6060 expressionS *exp;
c0f3af97 6061
922d8de8 6062 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6063 && i.tm.opcode_modifier.immext)
6064 {
6065 dest = i.operands - 2;
6066 gas_assert (dest == 3);
6067 }
922d8de8 6068 else
a683cc34 6069 dest = i.operands - 1;
c0f3af97 6070 nds = dest - 1;
922d8de8 6071
a683cc34
SP		 6072 /* There are 2 kinds of instructions:
6073 1. 5 operands: 4 register operands or 3 register operands
6074 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6075 VexW0 or VexW1. The destination must be either XMM, YMM or
6076 ZMM register.
a683cc34
SP		 6077 2. 4 operands: 4 register operands or 3 register operands
6078 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6079 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6080 || (i.reg_operands == 3 && i.mem_operands == 1))
6081 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6082 && (i.tm.opcode_modifier.veximmext
6083 || (i.imm_operands == 1
6084 && i.types[0].bitfield.vec_imm4
6085 && (i.tm.opcode_modifier.vexw == VEXW0
6086 || i.tm.opcode_modifier.vexw == VEXW1)
6087 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6088 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6089 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6090
6091 if (i.imm_operands == 0)
6092 {
6093 /* When there is no immediate operand, generate an 8bit
6094 immediate operand to encode the first operand. */
6095 exp = &im_expressions[i.imm_operands++];
6096 i.op[i.operands].imms = exp;
6097 i.types[i.operands] = imm8;
6098 i.operands++;
6099 /* If VexW1 is set, the first operand is the source and
6100 the second operand is encoded in the immediate operand. */
6101 if (i.tm.opcode_modifier.vexw == VEXW1)
6102 {
6103 source = 0;
6104 reg_slot = 1;
6105 }
6106 else
6107 {
6108 source = 1;
6109 reg_slot = 0;
6110 }
6111
6112 /* FMA swaps REG and NDS. */
6113 if (i.tm.cpu_flags.bitfield.cpufma)
6114 {
6115 unsigned int tmp;
6116 tmp = reg_slot;
6117 reg_slot = nds;
6118 nds = tmp;
6119 }
6120
24981e7b
L		 6121 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6122 &regxmm)
a683cc34 6123 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6124 &regymm)
6125 || operand_type_equal (&i.tm.operand_types[reg_slot],
6126 &regzmm));
a683cc34 6127 exp->X_op = O_constant;
4c692bc7 6128 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6129 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6130 }
922d8de8 6131 else
a683cc34
SP		 6132 {
6133 unsigned int imm_slot;
6134
6135 if (i.tm.opcode_modifier.vexw == VEXW0)
6136 {
6137 /* If VexW0 is set, the third operand is the source and
6138 the second operand is encoded in the immediate
6139 operand. */
6140 source = 2;
6141 reg_slot = 1;
6142 }
6143 else
6144 {
6145 /* VexW1 is set, the second operand is the source and
6146 the third operand is encoded in the immediate
6147 operand. */
6148 source = 1;
6149 reg_slot = 2;
6150 }
6151
6152 if (i.tm.opcode_modifier.immext)
6153 {
6154 /* When ImmExt is set, the immdiate byte is the last
6155 operand. */
6156 imm_slot = i.operands - 1;
6157 source--;
6158 reg_slot--;
6159 }
6160 else
6161 {
6162 imm_slot = 0;
6163
6164 /* Turn on Imm8 so that output_imm will generate it. */
6165 i.types[imm_slot].bitfield.imm8 = 1;
6166 }
6167
24981e7b
L		 6168 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6169 &regxmm)
6170 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6171 &regymm)
6172 || operand_type_equal (&i.tm.operand_types[reg_slot],
6173 &regzmm));
a683cc34 6174 i.op[imm_slot].imms->X_add_number
4c692bc7 6175 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6176 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6177 }
6178
6179 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6180 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6181 &regymm)
6182 || operand_type_equal (&i.tm.operand_types[nds],
6183 &regzmm));
dae39acc 6184 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6185 }
6186 else
6187 source = dest = 0;
29b0f896
AM		 6188
6189 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6190 implicit registers do not count. If there are 3 register
6191 operands, it must be a instruction with VexNDS. For a
6192 instruction with VexNDD, the destination register is encoded
6193 in VEX prefix. If there are 4 register operands, it must be
6194 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6195 if (i.mem_operands == 0
6196 && ((i.reg_operands == 2
2426c15f 6197 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6198 || (i.reg_operands == 3
2426c15f 6199 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6200 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6201 {
cab737b9
L		 6202 switch (i.operands)
6203 {
6204 case 2:
6205 source = 0;
6206 break;
6207 case 3:
c81128dc
L		 6208 /* When there are 3 operands, one of them may be immediate,
6209 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6210 the first operand must be shift count register (cl) or it
6211 is an instruction with VexNDS. */
9c2799c2 6212 gas_assert (i.imm_operands == 1
7ab9ffdd 6213 || (i.imm_operands == 0
2426c15f 6214 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6215 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6216 if (operand_type_check (i.types[0], imm)
6217 || i.types[0].bitfield.shiftcount)
6218 source = 1;
6219 else
6220 source = 0;
cab737b9
L		 6221 break;
6222 case 4:
368d64cc
L		 6223 /* When there are 4 operands, the first two must be 8bit
6224 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6225 one.
6226
6227 For instructions with VexNDS, if the first operand
6228 an imm8, the source operand is the 2nd one. If the last
6229 operand is imm8, the source operand is the first one. */
9c2799c2 6230 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6231 && i.types[0].bitfield.imm8
6232 && i.types[1].bitfield.imm8)
2426c15f 6233 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6234 && i.imm_operands == 1
6235 && (i.types[0].bitfield.imm8
43234a1e
L		 6236 || i.types[i.operands - 1].bitfield.imm8
6237 || i.rounding)));
9f2670f2
L		 6238 if (i.imm_operands == 2)
6239 source = 2;
6240 else
c0f3af97
L		 6241 {
6242 if (i.types[0].bitfield.imm8)
6243 source = 1;
6244 else
6245 source = 0;
6246 }
c0f3af97
L		 6247 break;
6248 case 5:
43234a1e
L		 6249 if (i.tm.opcode_modifier.evex)
6250 {
6251 /* For EVEX instructions, when there are 5 operands, the
6252 first one must be immediate operand. If the second one
6253 is immediate operand, the source operand is the 3th
6254 one. If the last one is immediate operand, the source
6255 operand is the 2nd one. */
6256 gas_assert (i.imm_operands == 2
6257 && i.tm.opcode_modifier.sae
6258 && operand_type_check (i.types[0], imm));
6259 if (operand_type_check (i.types[1], imm))
6260 source = 2;
6261 else if (operand_type_check (i.types[4], imm))
6262 source = 1;
6263 else
6264 abort ();
6265 }
cab737b9
L		 6266 break;
6267 default:
6268 abort ();
6269 }
6270
c0f3af97
L		 6271 if (!vex_3_sources)
6272 {
6273 dest = source + 1;
6274
43234a1e
L		 6275 /* RC/SAE operand could be between DEST and SRC. That happens
6276 when one operand is GPR and the other one is XMM/YMM/ZMM
6277 register. */
6278 if (i.rounding && i.rounding->operand == (int) dest)
6279 dest++;
6280
2426c15f 6281 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6282 {
43234a1e
L		 6283 /* For instructions with VexNDS, the register-only source
6284 operand must be 32/64bit integer, XMM, YMM or ZMM
6285 register. It is encoded in VEX prefix. We need to
6286 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6287
6288 i386_operand_type op;
6289 unsigned int vvvv;
6290
6291 /* Check register-only source operand when two source
6292 operands are swapped. */
6293 if (!i.tm.operand_types[source].bitfield.baseindex
6294 && i.tm.operand_types[dest].bitfield.baseindex)
6295 {
6296 vvvv = source;
6297 source = dest;
6298 }
6299 else
6300 vvvv = dest;
6301
6302 op = i.tm.operand_types[vvvv];
fa99fab2 6303 op.bitfield.regmem = 0;
c0f3af97 6304 if ((dest + 1) >= i.operands
ac4eb736
AM		 6305 || (!op.bitfield.reg32
6306 && op.bitfield.reg64
f12dc422 6307 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6308 && !operand_type_equal (&op, &regymm)
6309 && !operand_type_equal (&op, &regzmm)
6310 && !operand_type_equal (&op, &regmask)))
c0f3af97 6311 abort ();
f12dc422 6312 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6313 dest++;
6314 }
6315 }
29b0f896
AM		 6316
6317 i.rm.mode = 3;
6318 /* One of the register operands will be encoded in the i.tm.reg
6319 field, the other in the combined i.tm.mode and i.tm.regmem
6320 fields. If no form of this instruction supports a memory
6321 destination operand, then we assume the source operand may
6322 sometimes be a memory operand and so we need to store the
6323 destination in the i.rm.reg field. */
40fb9820
L		 6324 if (!i.tm.operand_types[dest].bitfield.regmem
6325 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6326 {
6327 i.rm.reg = i.op[dest].regs->reg_num;
6328 i.rm.regmem = i.op[source].regs->reg_num;
6329 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6330 i.rex |= REX_R;
43234a1e
L		 6331 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6332 i.vrex |= REX_R;
29b0f896 6333 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6334 i.rex |= REX_B;
43234a1e
L		 6335 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6336 i.vrex |= REX_B;
29b0f896
AM		 6337 }
6338 else
6339 {
6340 i.rm.reg = i.op[source].regs->reg_num;
6341 i.rm.regmem = i.op[dest].regs->reg_num;
6342 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6343 i.rex |= REX_B;
43234a1e
L		 6344 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6345 i.vrex |= REX_B;
29b0f896 6346 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6347 i.rex |= REX_R;
43234a1e
L		 6348 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6349 i.vrex |= REX_R;
29b0f896 6350 }
161a04f6 6351 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6352 {
40fb9820
L		 6353 if (!i.types[0].bitfield.control
6354 && !i.types[1].bitfield.control)
c4a530c5 6355 abort ();
161a04f6 6356 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6357 add_prefix (LOCK_PREFIX_OPCODE);
6358 }
29b0f896
AM		 6359 }
6360 else
6361 { /* If it's not 2 reg operands... */
c0f3af97
L		 6362 unsigned int mem;
6363
29b0f896
AM		 6364 if (i.mem_operands)
6365 {
6366 unsigned int fake_zero_displacement = 0;
99018f42 6367 unsigned int op;
4eed87de 6368
7ab9ffdd
L		 6369 for (op = 0; op < i.operands; op++)
6370 if (operand_type_check (i.types[op], anymem))
6371 break;
7ab9ffdd 6372 gas_assert (op < i.operands);
29b0f896 6373
6c30d220
L		 6374 if (i.tm.opcode_modifier.vecsib)
6375 {
6376 if (i.index_reg->reg_num == RegEiz
6377 || i.index_reg->reg_num == RegRiz)
6378 abort ();
6379
6380 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6381 if (!i.base_reg)
6382 {
6383 i.sib.base = NO_BASE_REGISTER;
6384 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6385 /* No Vec_Disp8 if there is no base. */
6386 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6387 i.types[op].bitfield.disp8 = 0;
6388 i.types[op].bitfield.disp16 = 0;
6389 i.types[op].bitfield.disp64 = 0;
6390 if (flag_code != CODE_64BIT)
6391 {
6392 /* Must be 32 bit */
6393 i.types[op].bitfield.disp32 = 1;
6394 i.types[op].bitfield.disp32s = 0;
6395 }
6396 else
6397 {
6398 i.types[op].bitfield.disp32 = 0;
6399 i.types[op].bitfield.disp32s = 1;
6400 }
6401 }
6402 i.sib.index = i.index_reg->reg_num;
6403 if ((i.index_reg->reg_flags & RegRex) != 0)
6404 i.rex |= REX_X;
43234a1e
L		 6405 if ((i.index_reg->reg_flags & RegVRex) != 0)
6406 i.vrex |= REX_X;
6c30d220
L		 6407 }
6408
29b0f896
AM		 6409 default_seg = &ds;
6410
6411 if (i.base_reg == 0)
6412 {
6413 i.rm.mode = 0;
6414 if (!i.disp_operands)
6c30d220
L		 6415 {
6416 fake_zero_displacement = 1;
6417 /* Instructions with VSIB byte need 32bit displacement
6418 if there is no base register. */
6419 if (i.tm.opcode_modifier.vecsib)
6420 i.types[op].bitfield.disp32 = 1;
6421 }
29b0f896
AM		 6422 if (i.index_reg == 0)
6423 {
6c30d220 6424 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6425 /* Operand is just <disp> */
20f0a1fc 6426 if (flag_code == CODE_64BIT)
29b0f896
AM		 6427 {
6428 /* 64bit mode overwrites the 32bit absolute
6429 addressing by RIP relative addressing and
6430 absolute addressing is encoded by one of the
6431 redundant SIB forms. */
6432 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6433 i.sib.base = NO_BASE_REGISTER;
6434 i.sib.index = NO_INDEX_REGISTER;
fc225355 6435 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6436 ? disp32s : disp32);
20f0a1fc 6437 }
fc225355
L		 6438 else if ((flag_code == CODE_16BIT)
6439 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6440 {
6441 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6442 i.types[op] = disp16;
20f0a1fc
NC		 6443 }
6444 else
6445 {
6446 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6447 i.types[op] = disp32;
29b0f896
AM		 6448 }
6449 }
6c30d220 6450 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6451 {
6c30d220 6452 /* !i.base_reg && i.index_reg */
db51cc60
L		 6453 if (i.index_reg->reg_num == RegEiz
6454 || i.index_reg->reg_num == RegRiz)
6455 i.sib.index = NO_INDEX_REGISTER;
6456 else
6457 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6458 i.sib.base = NO_BASE_REGISTER;
6459 i.sib.scale = i.log2_scale_factor;
6460 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6461 /* No Vec_Disp8 if there is no base. */
6462 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6463 i.types[op].bitfield.disp8 = 0;
6464 i.types[op].bitfield.disp16 = 0;
6465 i.types[op].bitfield.disp64 = 0;
29b0f896 6466 if (flag_code != CODE_64BIT)
40fb9820
L		 6467 {
6468 /* Must be 32 bit */
6469 i.types[op].bitfield.disp32 = 1;
6470 i.types[op].bitfield.disp32s = 0;
6471 }
29b0f896 6472 else
40fb9820
L		 6473 {
6474 i.types[op].bitfield.disp32 = 0;
6475 i.types[op].bitfield.disp32s = 1;
6476 }
29b0f896 6477 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6478 i.rex |= REX_X;
29b0f896
AM		 6479 }
6480 }
6481 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6482 else if (i.base_reg->reg_num == RegRip ||
6483 i.base_reg->reg_num == RegEip)
29b0f896 6484 {
6c30d220 6485 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6486 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6487 i.types[op].bitfield.disp8 = 0;
6488 i.types[op].bitfield.disp16 = 0;
6489 i.types[op].bitfield.disp32 = 0;
6490 i.types[op].bitfield.disp32s = 1;
6491 i.types[op].bitfield.disp64 = 0;
43234a1e 6492 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6493 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6494 if (! i.disp_operands)
6495 fake_zero_displacement = 1;
29b0f896 6496 }
40fb9820 6497 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6498 {
6c30d220 6499 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6500 switch (i.base_reg->reg_num)
6501 {
6502 case 3: /* (%bx) */
6503 if (i.index_reg == 0)
6504 i.rm.regmem = 7;
6505 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6506 i.rm.regmem = i.index_reg->reg_num - 6;
6507 break;
6508 case 5: /* (%bp) */
6509 default_seg = &ss;
6510 if (i.index_reg == 0)
6511 {
6512 i.rm.regmem = 6;
40fb9820 6513 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6514 {
6515 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6516 if (i.tm.operand_types[op].bitfield.vec_disp8)
6517 i.types[op].bitfield.vec_disp8 = 1;
6518 else
6519 i.types[op].bitfield.disp8 = 1;
252b5132 6520 fake_zero_displacement = 1;
29b0f896
AM		 6521 }
6522 }
6523 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6524 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6525 break;
6526 default: /* (%si) -> 4 or (%di) -> 5 */
6527 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6528 }
6529 i.rm.mode = mode_from_disp_size (i.types[op]);
6530 }
6531 else /* i.base_reg and 32/64 bit mode */
6532 {
6533 if (flag_code == CODE_64BIT
40fb9820
L		 6534 && operand_type_check (i.types[op], disp))
6535 {
6536 i386_operand_type temp;
0dfbf9d7 6537 operand_type_set (&temp, 0);
40fb9820 6538 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6539 temp.bitfield.vec_disp8
6540 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6541 i.types[op] = temp;
6542 if (i.prefix[ADDR_PREFIX] == 0)
6543 i.types[op].bitfield.disp32s = 1;
6544 else
6545 i.types[op].bitfield.disp32 = 1;
6546 }
20f0a1fc 6547
6c30d220
L		 6548 if (!i.tm.opcode_modifier.vecsib)
6549 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6550 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6551 i.rex |= REX_B;
29b0f896
AM		 6552 i.sib.base = i.base_reg->reg_num;
6553 /* x86-64 ignores REX prefix bit here to avoid decoder
6554 complications. */
848930b2
JB		 6555 if (!(i.base_reg->reg_flags & RegRex)
6556 && (i.base_reg->reg_num == EBP_REG_NUM
6557 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6558 default_seg = &ss;
848930b2 6559 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6560 {
848930b2 6561 fake_zero_displacement = 1;
43234a1e
L		 6562 if (i.tm.operand_types [op].bitfield.vec_disp8)
6563 i.types[op].bitfield.vec_disp8 = 1;
6564 else
6565 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6566 }
6567 i.sib.scale = i.log2_scale_factor;
6568 if (i.index_reg == 0)
6569 {
6c30d220 6570 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6571 /* <disp>(%esp) becomes two byte modrm with no index
6572 register. We've already stored the code for esp
6573 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6574 Any base register besides %esp will not use the
6575 extra modrm byte. */
6576 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6577 }
6c30d220 6578 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6579 {
db51cc60
L		 6580 if (i.index_reg->reg_num == RegEiz
6581 || i.index_reg->reg_num == RegRiz)
6582 i.sib.index = NO_INDEX_REGISTER;
6583 else
6584 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6585 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6586 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6587 i.rex |= REX_X;
29b0f896 6588 }
67a4f2b7
AO		 6589
6590 if (i.disp_operands
6591 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6592 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6593 i.rm.mode = 0;
6594 else
a501d77e
L		 6595 {
6596 if (!fake_zero_displacement
6597 && !i.disp_operands
6598 && i.disp_encoding)
6599 {
6600 fake_zero_displacement = 1;
6601 if (i.disp_encoding == disp_encoding_8bit)
6602 i.types[op].bitfield.disp8 = 1;
6603 else
6604 i.types[op].bitfield.disp32 = 1;
6605 }
6606 i.rm.mode = mode_from_disp_size (i.types[op]);
6607 }
29b0f896 6608 }
252b5132 6609
29b0f896
AM		 6610 if (fake_zero_displacement)
6611 {
6612 /* Fakes a zero displacement assuming that i.types[op]
6613 holds the correct displacement size. */
6614 expressionS *exp;
6615
9c2799c2 6616 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6617 exp = &disp_expressions[i.disp_operands++];
6618 i.op[op].disps = exp;
6619 exp->X_op = O_constant;
6620 exp->X_add_number = 0;
6621 exp->X_add_symbol = (symbolS *) 0;
6622 exp->X_op_symbol = (symbolS *) 0;
6623 }
c0f3af97
L		 6624
6625 mem = op;
29b0f896 6626 }
c0f3af97
L		 6627 else
6628 mem = ~0;
252b5132 6629
8c43a48b 6630 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6631 {
6632 if (operand_type_check (i.types[0], imm))
6633 i.vex.register_specifier = NULL;
6634 else
6635 {
6636 /* VEX.vvvv encodes one of the sources when the first
6637 operand is not an immediate. */
1ef99a7b 6638 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6639 i.vex.register_specifier = i.op[0].regs;
6640 else
6641 i.vex.register_specifier = i.op[1].regs;
6642 }
6643
6644 /* Destination is a XMM register encoded in the ModRM.reg
6645 and VEX.R bit. */
6646 i.rm.reg = i.op[2].regs->reg_num;
6647 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6648 i.rex |= REX_R;
6649
6650 /* ModRM.rm and VEX.B encodes the other source. */
6651 if (!i.mem_operands)
6652 {
6653 i.rm.mode = 3;
6654
1ef99a7b 6655 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6656 i.rm.regmem = i.op[1].regs->reg_num;
6657 else
6658 i.rm.regmem = i.op[0].regs->reg_num;
6659
6660 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6661 i.rex |= REX_B;
6662 }
6663 }
2426c15f 6664 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6665 {
6666 i.vex.register_specifier = i.op[2].regs;
6667 if (!i.mem_operands)
6668 {
6669 i.rm.mode = 3;
6670 i.rm.regmem = i.op[1].regs->reg_num;
6671 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6672 i.rex |= REX_B;
6673 }
6674 }
29b0f896
AM		 6675 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6676 (if any) based on i.tm.extension_opcode. Again, we must be
6677 careful to make sure that segment/control/debug/test/MMX
6678 registers are coded into the i.rm.reg field. */
f88c9eb0 6679 else if (i.reg_operands)
29b0f896 6680 {
99018f42 6681 unsigned int op;
7ab9ffdd
L		 6682 unsigned int vex_reg = ~0;
6683
6684 for (op = 0; op < i.operands; op++)
6685 if (i.types[op].bitfield.reg8
6686 || i.types[op].bitfield.reg16
6687 || i.types[op].bitfield.reg32
6688 || i.types[op].bitfield.reg64
6689 || i.types[op].bitfield.regmmx
6690 || i.types[op].bitfield.regxmm
6691 || i.types[op].bitfield.regymm
7e8b059b 6692 || i.types[op].bitfield.regbnd
43234a1e
L		 6693 || i.types[op].bitfield.regzmm
6694 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6695 || i.types[op].bitfield.sreg2
6696 || i.types[op].bitfield.sreg3
6697 || i.types[op].bitfield.control
6698 || i.types[op].bitfield.debug
6699 || i.types[op].bitfield.test)
6700 break;
c0209578 6701
7ab9ffdd
L		 6702 if (vex_3_sources)
6703 op = dest;
2426c15f 6704 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6705 {
6706 /* For instructions with VexNDS, the register-only
6707 source operand is encoded in VEX prefix. */
6708 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6709
7ab9ffdd 6710 if (op > mem)
c0f3af97 6711 {
7ab9ffdd
L		 6712 vex_reg = op++;
6713 gas_assert (op < i.operands);
c0f3af97
L		 6714 }
6715 else
c0f3af97 6716 {
f12dc422
L		 6717 /* Check register-only source operand when two source
6718 operands are swapped. */
6719 if (!i.tm.operand_types[op].bitfield.baseindex
6720 && i.tm.operand_types[op + 1].bitfield.baseindex)
6721 {
6722 vex_reg = op;
6723 op += 2;
6724 gas_assert (mem == (vex_reg + 1)
6725 && op < i.operands);
6726 }
6727 else
6728 {
6729 vex_reg = op + 1;
6730 gas_assert (vex_reg < i.operands);
6731 }
c0f3af97 6732 }
7ab9ffdd 6733 }
2426c15f 6734 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6735 {
f12dc422 6736 /* For instructions with VexNDD, the register destination
7ab9ffdd 6737 is encoded in VEX prefix. */
f12dc422
L		 6738 if (i.mem_operands == 0)
6739 {
6740 /* There is no memory operand. */
6741 gas_assert ((op + 2) == i.operands);
6742 vex_reg = op + 1;
6743 }
6744 else
8d63c93e 6745 {
f12dc422
L		 6746 /* There are only 2 operands. */
6747 gas_assert (op < 2 && i.operands == 2);
6748 vex_reg = 1;
6749 }
7ab9ffdd
L		 6750 }
6751 else
6752 gas_assert (op < i.operands);
99018f42 6753
7ab9ffdd
L		 6754 if (vex_reg != (unsigned int) ~0)
6755 {
f12dc422 6756 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6757
f12dc422
L		 6758 if (type->bitfield.reg32 != 1
6759 && type->bitfield.reg64 != 1
6760 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6761 && !operand_type_equal (type, &regymm)
6762 && !operand_type_equal (type, &regzmm)
6763 && !operand_type_equal (type, &regmask))
7ab9ffdd 6764 abort ();
f88c9eb0 6765
7ab9ffdd
L		 6766 i.vex.register_specifier = i.op[vex_reg].regs;
6767 }
6768
1b9f0c97
L		 6769 /* Don't set OP operand twice. */
6770 if (vex_reg != op)
7ab9ffdd 6771 {
1b9f0c97
L		 6772 /* If there is an extension opcode to put here, the
6773 register number must be put into the regmem field. */
6774 if (i.tm.extension_opcode != None)
6775 {
6776 i.rm.regmem = i.op[op].regs->reg_num;
6777 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6778 i.rex |= REX_B;
43234a1e
L		 6779 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6780 i.vrex |= REX_B;
1b9f0c97
L		 6781 }
6782 else
6783 {
6784 i.rm.reg = i.op[op].regs->reg_num;
6785 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6786 i.rex |= REX_R;
43234a1e
L		 6787 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6788 i.vrex |= REX_R;
1b9f0c97 6789 }
7ab9ffdd 6790 }
252b5132 6791
29b0f896
AM		 6792 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6793 must set it to 3 to indicate this is a register operand
6794 in the regmem field. */
6795 if (!i.mem_operands)
6796 i.rm.mode = 3;
6797 }
252b5132 6798
29b0f896 6799 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6800 if (i.tm.extension_opcode != None)
29b0f896
AM		 6801 i.rm.reg = i.tm.extension_opcode;
6802 }
6803 return default_seg;
6804}
252b5132 6805
29b0f896 6806static void
e3bb37b5 6807output_branch (void)
29b0f896
AM		 6808{
6809 char *p;
f8a5c266 6810 int size;
29b0f896
AM		 6811 int code16;
6812 int prefix;
6813 relax_substateT subtype;
6814 symbolS *sym;
6815 offsetT off;
6816
f8a5c266 6817 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6818 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6819
6820 prefix = 0;
6821 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6822 {
29b0f896
AM		 6823 prefix = 1;
6824 i.prefixes -= 1;
6825 code16 ^= CODE16;
252b5132 6826 }
29b0f896
AM		 6827 /* Pentium4 branch hints. */
6828 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6829 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6830 {
29b0f896
AM		 6831 prefix++;
6832 i.prefixes--;
6833 }
6834 if (i.prefix[REX_PREFIX] != 0)
6835 {
6836 prefix++;
6837 i.prefixes--;
2f66722d
AM		 6838 }
6839
7e8b059b
L		 6840 /* BND prefixed jump. */
6841 if (i.prefix[BND_PREFIX] != 0)
6842 {
6843 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6844 i.prefixes -= 1;
6845 }
6846
29b0f896
AM		 6847 if (i.prefixes != 0 && !intel_syntax)
6848 as_warn (_("skipping prefixes on this instruction"));
6849
6850 /* It's always a symbol; End frag & setup for relax.
6851 Make sure there is enough room in this frag for the largest
6852 instruction we may generate in md_convert_frag. This is 2
6853 bytes for the opcode and room for the prefix and largest
6854 displacement. */
6855 frag_grow (prefix + 2 + 4);
6856 /* Prefix and 1 opcode byte go in fr_fix. */
6857 p = frag_more (prefix + 1);
6858 if (i.prefix[DATA_PREFIX] != 0)
6859 *p++ = DATA_PREFIX_OPCODE;
6860 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6861 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6862 *p++ = i.prefix[SEG_PREFIX];
6863 if (i.prefix[REX_PREFIX] != 0)
6864 *p++ = i.prefix[REX_PREFIX];
6865 *p = i.tm.base_opcode;
6866
6867 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6868 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6869 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6870 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6871 else
f8a5c266 6872 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6873 subtype |= code16;
3e73aa7c 6874
29b0f896
AM		 6875 sym = i.op[0].disps->X_add_symbol;
6876 off = i.op[0].disps->X_add_number;
3e73aa7c 6877
29b0f896
AM		 6878 if (i.op[0].disps->X_op != O_constant
6879 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6880 {
29b0f896
AM		 6881 /* Handle complex expressions. */
6882 sym = make_expr_symbol (i.op[0].disps);
6883 off = 0;
6884 }
3e73aa7c 6885
29b0f896
AM		 6886 /* 1 possible extra opcode + 4 byte displacement go in var part.
6887 Pass reloc in fr_var. */
d258b828 6888 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6889}
3e73aa7c 6890
29b0f896 6891static void
e3bb37b5 6892output_jump (void)
29b0f896
AM		 6893{
6894 char *p;
6895 int size;
3e02c1cc 6896 fixS *fixP;
29b0f896 6897
40fb9820 6898 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6899 {
6900 /* This is a loop or jecxz type instruction. */
6901 size = 1;
6902 if (i.prefix[ADDR_PREFIX] != 0)
6903 {
6904 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6905 i.prefixes -= 1;
6906 }
6907 /* Pentium4 branch hints. */
6908 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6909 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6910 {
6911 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6912 i.prefixes--;
3e73aa7c
JH		 6913 }
6914 }
29b0f896
AM		 6915 else
6916 {
6917 int code16;
3e73aa7c 6918
29b0f896
AM		 6919 code16 = 0;
6920 if (flag_code == CODE_16BIT)
6921 code16 = CODE16;
3e73aa7c 6922
29b0f896
AM		 6923 if (i.prefix[DATA_PREFIX] != 0)
6924 {
6925 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6926 i.prefixes -= 1;
6927 code16 ^= CODE16;
6928 }
252b5132 6929
29b0f896
AM		 6930 size = 4;
6931 if (code16)
6932 size = 2;
6933 }
9fcc94b6 6934
29b0f896
AM		 6935 if (i.prefix[REX_PREFIX] != 0)
6936 {
6937 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6938 i.prefixes -= 1;
6939 }
252b5132 6940
7e8b059b
L		 6941 /* BND prefixed jump. */
6942 if (i.prefix[BND_PREFIX] != 0)
6943 {
6944 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6945 i.prefixes -= 1;
6946 }
6947
29b0f896
AM		 6948 if (i.prefixes != 0 && !intel_syntax)
6949 as_warn (_("skipping prefixes on this instruction"));
e0890092 6950
42164a71
L		 6951 p = frag_more (i.tm.opcode_length + size);
6952 switch (i.tm.opcode_length)
6953 {
6954 case 2:
6955 *p++ = i.tm.base_opcode >> 8;
6956 case 1:
6957 *p++ = i.tm.base_opcode;
6958 break;
6959 default:
6960 abort ();
6961 }
e0890092 6962
3e02c1cc 6963 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6964 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6965
6966 /* All jumps handled here are signed, but don't use a signed limit
6967 check for 32 and 16 bit jumps as we want to allow wrap around at
6968 4G and 64k respectively. */
6969 if (size == 1)
6970 fixP->fx_signed = 1;
29b0f896 6971}
e0890092 6972
29b0f896 6973static void
e3bb37b5 6974output_interseg_jump (void)
29b0f896
AM		 6975{
6976 char *p;
6977 int size;
6978 int prefix;
6979 int code16;
252b5132 6980
29b0f896
AM		 6981 code16 = 0;
6982 if (flag_code == CODE_16BIT)
6983 code16 = CODE16;
a217f122 6984
29b0f896
AM		 6985 prefix = 0;
6986 if (i.prefix[DATA_PREFIX] != 0)
6987 {
6988 prefix = 1;
6989 i.prefixes -= 1;
6990 code16 ^= CODE16;
6991 }
6992 if (i.prefix[REX_PREFIX] != 0)
6993 {
6994 prefix++;
6995 i.prefixes -= 1;
6996 }
252b5132 6997
29b0f896
AM		 6998 size = 4;
6999 if (code16)
7000 size = 2;
252b5132 7001
29b0f896
AM		 7002 if (i.prefixes != 0 && !intel_syntax)
7003 as_warn (_("skipping prefixes on this instruction"));
252b5132 7004
29b0f896
AM		 7005 /* 1 opcode; 2 segment; offset */
7006 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7007
29b0f896
AM		 7008 if (i.prefix[DATA_PREFIX] != 0)
7009 *p++ = DATA_PREFIX_OPCODE;
252b5132 7010
29b0f896
AM		 7011 if (i.prefix[REX_PREFIX] != 0)
7012 *p++ = i.prefix[REX_PREFIX];
252b5132 7013
29b0f896
AM		 7014 *p++ = i.tm.base_opcode;
7015 if (i.op[1].imms->X_op == O_constant)
7016 {
7017 offsetT n = i.op[1].imms->X_add_number;
252b5132 7018
29b0f896
AM		 7019 if (size == 2
7020 && !fits_in_unsigned_word (n)
7021 && !fits_in_signed_word (n))
7022 {
7023 as_bad (_("16-bit jump out of range"));
7024 return;
7025 }
7026 md_number_to_chars (p, n, size);
7027 }
7028 else
7029 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7030 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7031 if (i.op[0].imms->X_op != O_constant)
7032 as_bad (_("can't handle non absolute segment in `%s'"),
7033 i.tm.name);
7034 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7035}
a217f122 7036
29b0f896 7037static void
e3bb37b5 7038output_insn (void)
29b0f896 7039{
2bbd9c25
JJ		 7040 fragS *insn_start_frag;
7041 offsetT insn_start_off;
7042
29b0f896
AM		 7043 /* Tie dwarf2 debug info to the address at the start of the insn.
7044 We can't do this after the insn has been output as the current
7045 frag may have been closed off. eg. by frag_var. */
7046 dwarf2_emit_insn (0);
7047
2bbd9c25
JJ		 7048 insn_start_frag = frag_now;
7049 insn_start_off = frag_now_fix ();
7050
29b0f896 7051 /* Output jumps. */
40fb9820 7052 if (i.tm.opcode_modifier.jump)
29b0f896 7053 output_branch ();
40fb9820
L		 7054 else if (i.tm.opcode_modifier.jumpbyte
7055 || i.tm.opcode_modifier.jumpdword)
29b0f896 7056 output_jump ();
40fb9820 7057 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7058 output_interseg_jump ();
7059 else
7060 {
7061 /* Output normal instructions here. */
7062 char *p;
7063 unsigned char *q;
47465058 7064 unsigned int j;
331d2d0d 7065 unsigned int prefix;
4dffcebc 7066
e4e00185
AS		 7067 if (avoid_fence
7068 && i.tm.base_opcode == 0xfae
7069 && i.operands == 1
7070 && i.imm_operands == 1
7071 && (i.op[0].imms->X_add_number == 0xe8
7072 || i.op[0].imms->X_add_number == 0xf0
7073 || i.op[0].imms->X_add_number == 0xf8))
7074 {
7075 /* Encode lfence, mfence, and sfence as
7076 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7077 offsetT val = 0x240483f0ULL;
7078 p = frag_more (5);
7079 md_number_to_chars (p, val, 5);
7080 return;
7081 }
7082
d022bddd
IT		 7083 /* Some processors fail on LOCK prefix. This options makes
7084 assembler ignore LOCK prefix and serves as a workaround. */
7085 if (omit_lock_prefix)
7086 {
7087 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7088 return;
7089 i.prefix[LOCK_PREFIX] = 0;
7090 }
7091
43234a1e
L		 7092 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7093 don't need the explicit prefix. */
7094 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7095 {
c0f3af97 7096 switch (i.tm.opcode_length)
bc4bd9ab 7097 {
c0f3af97
L		 7098 case 3:
7099 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7100 {
c0f3af97
L		 7101 prefix = (i.tm.base_opcode >> 24) & 0xff;
7102 goto check_prefix;
7103 }
7104 break;
7105 case 2:
7106 if ((i.tm.base_opcode & 0xff0000) != 0)
7107 {
7108 prefix = (i.tm.base_opcode >> 16) & 0xff;
7109 if (i.tm.cpu_flags.bitfield.cpupadlock)
7110 {
4dffcebc 7111check_prefix:
c0f3af97 7112 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7113 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7114 != REPE_PREFIX_OPCODE))
7115 add_prefix (prefix);
7116 }
7117 else
4dffcebc
L		 7118 add_prefix (prefix);
7119 }
c0f3af97
L		 7120 break;
7121 case 1:
7122 break;
7123 default:
7124 abort ();
bc4bd9ab 7125 }
c0f3af97 7126
6d19a37a 7127#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7128 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7129 R_X86_64_GOTTPOFF relocation so that linker can safely
7130 perform IE->LE optimization. */
7131 if (x86_elf_abi == X86_64_X32_ABI
7132 && i.operands == 2
7133 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7134 && i.prefix[REX_PREFIX] == 0)
7135 add_prefix (REX_OPCODE);
6d19a37a 7136#endif
cf61b747 7137
c0f3af97
L		 7138 /* The prefix bytes. */
7139 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7140 if (*q)
7141 FRAG_APPEND_1_CHAR (*q);
0f10071e 7142 }
ae5c1c7b 7143 else
c0f3af97
L		 7144 {
7145 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7146 if (*q)
7147 switch (j)
7148 {
7149 case REX_PREFIX:
7150 /* REX byte is encoded in VEX prefix. */
7151 break;
7152 case SEG_PREFIX:
7153 case ADDR_PREFIX:
7154 FRAG_APPEND_1_CHAR (*q);
7155 break;
7156 default:
7157 /* There should be no other prefixes for instructions
7158 with VEX prefix. */
7159 abort ();
7160 }
7161
43234a1e
L		 7162 /* For EVEX instructions i.vrex should become 0 after
7163 build_evex_prefix. For VEX instructions upper 16 registers
7164 aren't available, so VREX should be 0. */
7165 if (i.vrex)
7166 abort ();
c0f3af97
L		 7167 /* Now the VEX prefix. */
7168 p = frag_more (i.vex.length);
7169 for (j = 0; j < i.vex.length; j++)
7170 p[j] = i.vex.bytes[j];
7171 }
252b5132 7172
29b0f896 7173 /* Now the opcode; be careful about word order here! */
4dffcebc 7174 if (i.tm.opcode_length == 1)
29b0f896
AM		 7175 {
7176 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7177 }
7178 else
7179 {
4dffcebc 7180 switch (i.tm.opcode_length)
331d2d0d 7181 {
43234a1e
L		 7182 case 4:
7183 p = frag_more (4);
7184 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7185 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7186 break;
4dffcebc 7187 case 3:
331d2d0d
L		 7188 p = frag_more (3);
7189 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7190 break;
7191 case 2:
7192 p = frag_more (2);
7193 break;
7194 default:
7195 abort ();
7196 break;
331d2d0d 7197 }
0f10071e 7198
29b0f896
AM		 7199 /* Put out high byte first: can't use md_number_to_chars! */
7200 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7201 *p = i.tm.base_opcode & 0xff;
7202 }
3e73aa7c 7203
29b0f896 7204 /* Now the modrm byte and sib byte (if present). */
40fb9820 7205 if (i.tm.opcode_modifier.modrm)
29b0f896 7206 {
4a3523fa
L		 7207 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7208 | i.rm.reg << 3
7209 | i.rm.mode << 6));
29b0f896
AM		 7210 /* If i.rm.regmem == ESP (4)
7211 && i.rm.mode != (Register mode)
7212 && not 16 bit
7213 ==> need second modrm byte. */
7214 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7215 && i.rm.mode != 3
40fb9820 7216 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7217 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7218 | i.sib.index << 3
7219 | i.sib.scale << 6));
29b0f896 7220 }
3e73aa7c 7221
29b0f896 7222 if (i.disp_operands)
2bbd9c25 7223 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7224
29b0f896 7225 if (i.imm_operands)
2bbd9c25 7226 output_imm (insn_start_frag, insn_start_off);
29b0f896 7227 }
252b5132 7228
29b0f896
AM		 7229#ifdef DEBUG386
7230 if (flag_debug)
7231 {
7b81dfbb 7232 pi ("" /*line*/, &i);
29b0f896
AM		 7233 }
7234#endif /* DEBUG386 */
7235}
252b5132 7236
e205caa7
L		 7237/* Return the size of the displacement operand N. */
7238
7239static int
7240disp_size (unsigned int n)
7241{
7242 int size = 4;
43234a1e
L		 7243
7244 /* Vec_Disp8 has to be 8bit. */
7245 if (i.types[n].bitfield.vec_disp8)
7246 size = 1;
7247 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7248 size = 8;
7249 else if (i.types[n].bitfield.disp8)
7250 size = 1;
7251 else if (i.types[n].bitfield.disp16)
7252 size = 2;
e205caa7
L		 7253 return size;
7254}
7255
7256/* Return the size of the immediate operand N. */
7257
7258static int
7259imm_size (unsigned int n)
7260{
7261 int size = 4;
40fb9820
L		 7262 if (i.types[n].bitfield.imm64)
7263 size = 8;
7264 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7265 size = 1;
7266 else if (i.types[n].bitfield.imm16)
7267 size = 2;
e205caa7
L		 7268 return size;
7269}
7270
29b0f896 7271static void
64e74474 7272output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7273{
7274 char *p;
7275 unsigned int n;
252b5132 7276
29b0f896
AM		 7277 for (n = 0; n < i.operands; n++)
7278 {
43234a1e
L		 7279 if (i.types[n].bitfield.vec_disp8
7280 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7281 {
7282 if (i.op[n].disps->X_op == O_constant)
7283 {
e205caa7 7284 int size = disp_size (n);
43234a1e 7285 offsetT val = i.op[n].disps->X_add_number;
252b5132 7286
43234a1e
L		 7287 if (i.types[n].bitfield.vec_disp8)
7288 val >>= i.memshift;
7289 val = offset_in_range (val, size);
29b0f896
AM		 7290 p = frag_more (size);
7291 md_number_to_chars (p, val, size);
7292 }
7293 else
7294 {
f86103b7 7295 enum bfd_reloc_code_real reloc_type;
e205caa7 7296 int size = disp_size (n);
40fb9820 7297 int sign = i.types[n].bitfield.disp32s;
29b0f896 7298 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7299 fixS *fixP;
29b0f896 7300
e205caa7 7301 /* We can't have 8 bit displacement here. */
9c2799c2 7302 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7303
29b0f896
AM		 7304 /* The PC relative address is computed relative
7305 to the instruction boundary, so in case immediate
7306 fields follows, we need to adjust the value. */
7307 if (pcrel && i.imm_operands)
7308 {
29b0f896 7309 unsigned int n1;
e205caa7 7310 int sz = 0;
252b5132 7311
29b0f896 7312 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7313 if (operand_type_check (i.types[n1], imm))
252b5132 7314 {
e205caa7
L		 7315 /* Only one immediate is allowed for PC
7316 relative address. */
9c2799c2 7317 gas_assert (sz == 0);
e205caa7
L		 7318 sz = imm_size (n1);
7319 i.op[n].disps->X_add_number -= sz;
252b5132 7320 }
29b0f896 7321 /* We should find the immediate. */
9c2799c2 7322 gas_assert (sz != 0);
29b0f896 7323 }
520dc8e8 7324
29b0f896 7325 p = frag_more (size);
d258b828 7326 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7327 if (GOT_symbol
2bbd9c25 7328 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7329 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7330 || reloc_type == BFD_RELOC_X86_64_32S
7331 || (reloc_type == BFD_RELOC_64
7332 && object_64bit))
d6ab8113
JB		 7333 && (i.op[n].disps->X_op == O_symbol
7334 || (i.op[n].disps->X_op == O_add
7335 && ((symbol_get_value_expression
7336 (i.op[n].disps->X_op_symbol)->X_op)
7337 == O_subtract))))
7338 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7339 {
7340 offsetT add;
7341
7342 if (insn_start_frag == frag_now)
7343 add = (p - frag_now->fr_literal) - insn_start_off;
7344 else
7345 {
7346 fragS *fr;
7347
7348 add = insn_start_frag->fr_fix - insn_start_off;
7349 for (fr = insn_start_frag->fr_next;
7350 fr && fr != frag_now; fr = fr->fr_next)
7351 add += fr->fr_fix;
7352 add += p - frag_now->fr_literal;
7353 }
7354
4fa24527 7355 if (!object_64bit)
7b81dfbb
AJ		 7356 {
7357 reloc_type = BFD_RELOC_386_GOTPC;
7358 i.op[n].imms->X_add_number += add;
7359 }
7360 else if (reloc_type == BFD_RELOC_64)
7361 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7362 else
7b81dfbb
AJ		 7363 /* Don't do the adjustment for x86-64, as there
7364 the pcrel addressing is relative to the _next_
7365 insn, and that is taken care of in other code. */
d6ab8113 7366 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7367 }
02a86693
L		 7368 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7369 size, i.op[n].disps, pcrel,
7370 reloc_type);
7371 /* Check for "call/jmp *mem", "mov mem, %reg",
7372 "test %reg, mem" and "binop mem, %reg" where binop
7373 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7374 instructions. Always generate R_386_GOT32X for
7375 "sym*GOT" operand in 32-bit mode. */
7376 if ((generate_relax_relocations
7377 || (!object_64bit
7378 && i.rm.mode == 0
7379 && i.rm.regmem == 5))
7380 && (i.rm.mode == 2
7381 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7382 && ((i.operands == 1
7383 && i.tm.base_opcode == 0xff
7384 && (i.rm.reg == 2 || i.rm.reg == 4))
7385 || (i.operands == 2
7386 && (i.tm.base_opcode == 0x8b
7387 || i.tm.base_opcode == 0x85
7388 || (i.tm.base_opcode & 0xc7) == 0x03))))
7389 {
7390 if (object_64bit)
7391 {
7392 fixP->fx_tcbit = i.rex != 0;
7393 if (i.base_reg
7394 && (i.base_reg->reg_num == RegRip
7395 || i.base_reg->reg_num == RegEip))
7396 fixP->fx_tcbit2 = 1;
7397 }
7398 else
7399 fixP->fx_tcbit2 = 1;
7400 }
29b0f896
AM		 7401 }
7402 }
7403 }
7404}
252b5132 7405
29b0f896 7406static void
64e74474 7407output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7408{
7409 char *p;
7410 unsigned int n;
252b5132 7411
29b0f896
AM		 7412 for (n = 0; n < i.operands; n++)
7413 {
43234a1e
L		 7414 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7415 if (i.rounding && (int) n == i.rounding->operand)
7416 continue;
7417
40fb9820 7418 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7419 {
7420 if (i.op[n].imms->X_op == O_constant)
7421 {
e205caa7 7422 int size = imm_size (n);
29b0f896 7423 offsetT val;
b4cac588 7424
29b0f896
AM		 7425 val = offset_in_range (i.op[n].imms->X_add_number,
7426 size);
7427 p = frag_more (size);
7428 md_number_to_chars (p, val, size);
7429 }
7430 else
7431 {
7432 /* Not absolute_section.
7433 Need a 32-bit fixup (don't support 8bit
7434 non-absolute imms). Try to support other
7435 sizes ... */
f86103b7 7436 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7437 int size = imm_size (n);
7438 int sign;
29b0f896 7439
40fb9820 7440 if (i.types[n].bitfield.imm32s
a7d61044 7441 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7442 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7443 sign = 1;
e205caa7
L		 7444 else
7445 sign = 0;
520dc8e8 7446
29b0f896 7447 p = frag_more (size);
d258b828 7448 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7449
2bbd9c25
JJ		 7450 /* This is tough to explain. We end up with this one if we
7451 * have operands that look like
7452 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7453 * obtain the absolute address of the GOT, and it is strongly
7454 * preferable from a performance point of view to avoid using
7455 * a runtime relocation for this. The actual sequence of
7456 * instructions often look something like:
7457 *
7458 * call .L66
7459 * .L66:
7460 * popl %ebx
7461 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7462 *
7463 * The call and pop essentially return the absolute address
7464 * of the label .L66 and store it in %ebx. The linker itself
7465 * will ultimately change the first operand of the addl so
7466 * that %ebx points to the GOT, but to keep things simple, the
7467 * .o file must have this operand set so that it generates not
7468 * the absolute address of .L66, but the absolute address of
7469 * itself. This allows the linker itself simply treat a GOTPC
7470 * relocation as asking for a pcrel offset to the GOT to be
7471 * added in, and the addend of the relocation is stored in the
7472 * operand field for the instruction itself.
7473 *
7474 * Our job here is to fix the operand so that it would add
7475 * the correct offset so that %ebx would point to itself. The
7476 * thing that is tricky is that .-.L66 will point to the
7477 * beginning of the instruction, so we need to further modify
7478 * the operand so that it will point to itself. There are
7479 * other cases where you have something like:
7480 *
7481 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7482 *
7483 * and here no correction would be required. Internally in
7484 * the assembler we treat operands of this form as not being
7485 * pcrel since the '.' is explicitly mentioned, and I wonder
7486 * whether it would simplify matters to do it this way. Who
7487 * knows. In earlier versions of the PIC patches, the
7488 * pcrel_adjust field was used to store the correction, but
7489 * since the expression is not pcrel, I felt it would be
7490 * confusing to do it this way. */
7491
d6ab8113 7492 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7493 || reloc_type == BFD_RELOC_X86_64_32S
7494 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7495 && GOT_symbol
7496 && GOT_symbol == i.op[n].imms->X_add_symbol
7497 && (i.op[n].imms->X_op == O_symbol
7498 || (i.op[n].imms->X_op == O_add
7499 && ((symbol_get_value_expression
7500 (i.op[n].imms->X_op_symbol)->X_op)
7501 == O_subtract))))
7502 {
2bbd9c25
JJ		 7503 offsetT add;
7504
7505 if (insn_start_frag == frag_now)
7506 add = (p - frag_now->fr_literal) - insn_start_off;
7507 else
7508 {
7509 fragS *fr;
7510
7511 add = insn_start_frag->fr_fix - insn_start_off;
7512 for (fr = insn_start_frag->fr_next;
7513 fr && fr != frag_now; fr = fr->fr_next)
7514 add += fr->fr_fix;
7515 add += p - frag_now->fr_literal;
7516 }
7517
4fa24527 7518 if (!object_64bit)
d6ab8113 7519 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7520 else if (size == 4)
d6ab8113 7521 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7522 else if (size == 8)
7523 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7524 i.op[n].imms->X_add_number += add;
29b0f896 7525 }
29b0f896
AM		 7526 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7527 i.op[n].imms, 0, reloc_type);
7528 }
7529 }
7530 }
252b5132
RH		 7531}
7532\f
d182319b
JB		 7533/* x86_cons_fix_new is called via the expression parsing code when a
7534 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7535static int cons_sign = -1;
7536
7537void
e3bb37b5 7538x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7539 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7540{
d258b828 7541 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7542
7543#ifdef TE_PE
7544 if (exp->X_op == O_secrel)
7545 {
7546 exp->X_op = O_symbol;
7547 r = BFD_RELOC_32_SECREL;
7548 }
7549#endif
7550
7551 fix_new_exp (frag, off, len, exp, 0, r);
7552}
7553
357d1bd8
L		 7554/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7555 purpose of the `.dc.a' internal pseudo-op. */
7556
7557int
7558x86_address_bytes (void)
7559{
7560 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7561 return 4;
7562 return stdoutput->arch_info->bits_per_address / 8;
7563}
7564
d382c579
TG		 7565#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7566 || defined (LEX_AT)
d258b828 7567# define lex_got(reloc, adjust, types) NULL
718ddfc0 7568#else
f3c180ae
AM		 7569/* Parse operands of the form
7570 <symbol>@GOTOFF+<nnn>
7571 and similar .plt or .got references.
7572
7573 If we find one, set up the correct relocation in RELOC and copy the
7574 input string, minus the `@GOTOFF' into a malloc'd buffer for
7575 parsing by the calling routine. Return this buffer, and if ADJUST
7576 is non-null set it to the length of the string we removed from the
7577 input line. Otherwise return NULL. */
7578static char *
91d6fa6a 7579lex_got (enum bfd_reloc_code_real *rel,
64e74474 7580 int *adjust,
d258b828 7581 i386_operand_type *types)
f3c180ae 7582{
7b81dfbb
AJ		 7583 /* Some of the relocations depend on the size of what field is to
7584 be relocated. But in our callers i386_immediate and i386_displacement
7585 we don't yet know the operand size (this will be set by insn
7586 matching). Hence we record the word32 relocation here,
7587 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7588 static const struct {
7589 const char *str;
cff8d58a 7590 int len;
4fa24527 7591 const enum bfd_reloc_code_real rel[2];
40fb9820 7592 const i386_operand_type types64;
f3c180ae 7593 } gotrel[] = {
8ce3d284 7594#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7595 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7596 BFD_RELOC_SIZE32 },
7597 OPERAND_TYPE_IMM32_64 },
8ce3d284 7598#endif
cff8d58a
L		 7599 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7600 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7601 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7602 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7603 BFD_RELOC_X86_64_PLT32 },
40fb9820 7604 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7605 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7606 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7607 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7608 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7609 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7610 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7611 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7612 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7613 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7614 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7615 BFD_RELOC_X86_64_TLSGD },
40fb9820 7616 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7617 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7618 _dummy_first_bfd_reloc_code_real },
40fb9820 7619 OPERAND_TYPE_NONE },
cff8d58a
L		 7620 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7621 BFD_RELOC_X86_64_TLSLD },
40fb9820 7622 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7623 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7624 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7625 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7626 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7627 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7628 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7629 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7630 _dummy_first_bfd_reloc_code_real },
40fb9820 7631 OPERAND_TYPE_NONE },
cff8d58a
L		 7632 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7633 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7634 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7635 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7636 _dummy_first_bfd_reloc_code_real },
40fb9820 7637 OPERAND_TYPE_NONE },
cff8d58a
L		 7638 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7639 _dummy_first_bfd_reloc_code_real },
40fb9820 7640 OPERAND_TYPE_NONE },
cff8d58a
L		 7641 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7642 BFD_RELOC_X86_64_GOT32 },
40fb9820 7643 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7644 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7645 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7646 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7647 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7648 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7649 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7650 };
7651 char *cp;
7652 unsigned int j;
7653
d382c579 7654#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7655 if (!IS_ELF)
7656 return NULL;
d382c579 7657#endif
718ddfc0 7658
f3c180ae 7659 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7660 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7661 return NULL;
7662
47465058 7663 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7664 {
cff8d58a 7665 int len = gotrel[j].len;
28f81592 7666 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7667 {
4fa24527 7668 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7669 {
28f81592
AM		 7670 int first, second;
7671 char *tmpbuf, *past_reloc;
f3c180ae 7672
91d6fa6a 7673 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7674
3956db08
JB		 7675 if (types)
7676 {
7677 if (flag_code != CODE_64BIT)
40fb9820
L		 7678 {
7679 types->bitfield.imm32 = 1;
7680 types->bitfield.disp32 = 1;
7681 }
3956db08
JB		 7682 else
7683 *types = gotrel[j].types64;
7684 }
7685
8fd4256d 7686 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7687 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7688
28f81592 7689 /* The length of the first part of our input line. */
f3c180ae 7690 first = cp - input_line_pointer;
28f81592
AM		 7691
7692 /* The second part goes from after the reloc token until
67c11a9b 7693 (and including) an end_of_line char or comma. */
28f81592 7694 past_reloc = cp + 1 + len;
67c11a9b
AM		 7695 cp = past_reloc;
7696 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7697 ++cp;
7698 second = cp + 1 - past_reloc;
28f81592
AM		 7699
7700 /* Allocate and copy string. The trailing NUL shouldn't
7701 be necessary, but be safe. */
add39d23 7702 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7703 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7704 if (second != 0 && *past_reloc != ' ')
7705 /* Replace the relocation token with ' ', so that
7706 errors like foo@GOTOFF1 will be detected. */
7707 tmpbuf[first++] = ' ';
af89796a
L		 7708 else
7709 /* Increment length by 1 if the relocation token is
7710 removed. */
7711 len++;
7712 if (adjust)
7713 *adjust = len;
0787a12d
AM		 7714 memcpy (tmpbuf + first, past_reloc, second);
7715 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7716 return tmpbuf;
7717 }
7718
4fa24527
JB		 7719 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7720 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7721 return NULL;
7722 }
7723 }
7724
7725 /* Might be a symbol version string. Don't as_bad here. */
7726 return NULL;
7727}
4e4f7c87 7728#endif
f3c180ae 7729
a988325c
NC		 7730#ifdef TE_PE
7731#ifdef lex_got
7732#undef lex_got
7733#endif
7734/* Parse operands of the form
7735 <symbol>@SECREL32+<nnn>
7736
7737 If we find one, set up the correct relocation in RELOC and copy the
7738 input string, minus the `@SECREL32' into a malloc'd buffer for
7739 parsing by the calling routine. Return this buffer, and if ADJUST
7740 is non-null set it to the length of the string we removed from the
34bca508
L		 7741 input line. Otherwise return NULL.
7742
a988325c
NC		 7743 This function is copied from the ELF version above adjusted for PE targets. */
7744
7745static char *
7746lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7747 int *adjust ATTRIBUTE_UNUSED,
d258b828 7748 i386_operand_type *types)
a988325c
NC		 7749{
7750 static const struct
7751 {
7752 const char *str;
7753 int len;
7754 const enum bfd_reloc_code_real rel[2];
7755 const i386_operand_type types64;
7756 }
7757 gotrel[] =
7758 {
7759 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7760 BFD_RELOC_32_SECREL },
7761 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7762 };
7763
7764 char *cp;
7765 unsigned j;
7766
7767 for (cp = input_line_pointer; *cp != '@'; cp++)
7768 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7769 return NULL;
7770
7771 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7772 {
7773 int len = gotrel[j].len;
7774
7775 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7776 {
7777 if (gotrel[j].rel[object_64bit] != 0)
7778 {
7779 int first, second;
7780 char *tmpbuf, *past_reloc;
7781
7782 *rel = gotrel[j].rel[object_64bit];
7783 if (adjust)
7784 *adjust = len;
7785
7786 if (types)
7787 {
7788 if (flag_code != CODE_64BIT)
7789 {
7790 types->bitfield.imm32 = 1;
7791 types->bitfield.disp32 = 1;
7792 }
7793 else
7794 *types = gotrel[j].types64;
7795 }
7796
7797 /* The length of the first part of our input line. */
7798 first = cp - input_line_pointer;
7799
7800 /* The second part goes from after the reloc token until
7801 (and including) an end_of_line char or comma. */
7802 past_reloc = cp + 1 + len;
7803 cp = past_reloc;
7804 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7805 ++cp;
7806 second = cp + 1 - past_reloc;
7807
7808 /* Allocate and copy string. The trailing NUL shouldn't
7809 be necessary, but be safe. */
add39d23 7810 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7811 memcpy (tmpbuf, input_line_pointer, first);
7812 if (second != 0 && *past_reloc != ' ')
7813 /* Replace the relocation token with ' ', so that
7814 errors like foo@SECLREL321 will be detected. */
7815 tmpbuf[first++] = ' ';
7816 memcpy (tmpbuf + first, past_reloc, second);
7817 tmpbuf[first + second] = '\0';
7818 return tmpbuf;
7819 }
7820
7821 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7822 gotrel[j].str, 1 << (5 + object_64bit));
7823 return NULL;
7824 }
7825 }
7826
7827 /* Might be a symbol version string. Don't as_bad here. */
7828 return NULL;
7829}
7830
7831#endif /* TE_PE */
7832
62ebcb5c 7833bfd_reloc_code_real_type
e3bb37b5 7834x86_cons (expressionS *exp, int size)
f3c180ae 7835{
62ebcb5c
AM		 7836 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7837
ee86248c
JB		 7838 intel_syntax = -intel_syntax;
7839
3c7b9c2c 7840 exp->X_md = 0;
4fa24527 7841 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7842 {
7843 /* Handle @GOTOFF and the like in an expression. */
7844 char *save;
7845 char *gotfree_input_line;
4a57f2cf 7846 int adjust = 0;
f3c180ae
AM		 7847
7848 save = input_line_pointer;
d258b828 7849 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7850 if (gotfree_input_line)
7851 input_line_pointer = gotfree_input_line;
7852
7853 expression (exp);
7854
7855 if (gotfree_input_line)
7856 {
7857 /* expression () has merrily parsed up to the end of line,
7858 or a comma - in the wrong buffer. Transfer how far
7859 input_line_pointer has moved to the right buffer. */
7860 input_line_pointer = (save
7861 + (input_line_pointer - gotfree_input_line)
7862 + adjust);
7863 free (gotfree_input_line);
3992d3b7
AM		 7864 if (exp->X_op == O_constant
7865 || exp->X_op == O_absent
7866 || exp->X_op == O_illegal
0398aac5 7867 || exp->X_op == O_register
3992d3b7
AM		 7868 || exp->X_op == O_big)
7869 {
7870 char c = *input_line_pointer;
7871 *input_line_pointer = 0;
7872 as_bad (_("missing or invalid expression `%s'"), save);
7873 *input_line_pointer = c;
7874 }
f3c180ae
AM		 7875 }
7876 }
7877 else
7878 expression (exp);
ee86248c
JB		 7879
7880 intel_syntax = -intel_syntax;
7881
7882 if (intel_syntax)
7883 i386_intel_simplify (exp);
62ebcb5c
AM		 7884
7885 return got_reloc;
f3c180ae 7886}
f3c180ae 7887
9f32dd5b
L		 7888static void
7889signed_cons (int size)
6482c264 7890{
d182319b
JB		 7891 if (flag_code == CODE_64BIT)
7892 cons_sign = 1;
7893 cons (size);
7894 cons_sign = -1;
6482c264
NC		 7895}
7896
d182319b 7897#ifdef TE_PE
6482c264 7898static void
7016a5d5 7899pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7900{
7901 expressionS exp;
7902
7903 do
7904 {
7905 expression (&exp);
7906 if (exp.X_op == O_symbol)
7907 exp.X_op = O_secrel;
7908
7909 emit_expr (&exp, 4);
7910 }
7911 while (*input_line_pointer++ == ',');
7912
7913 input_line_pointer--;
7914 demand_empty_rest_of_line ();
7915}
6482c264
NC		 7916#endif
7917
43234a1e
L		 7918/* Handle Vector operations. */
7919
7920static char *
7921check_VecOperations (char *op_string, char *op_end)
7922{
7923 const reg_entry *mask;
7924 const char *saved;
7925 char *end_op;
7926
7927 while (*op_string
7928 && (op_end == NULL || op_string < op_end))
7929 {
7930 saved = op_string;
7931 if (*op_string == '{')
7932 {
7933 op_string++;
7934
7935 /* Check broadcasts. */
7936 if (strncmp (op_string, "1to", 3) == 0)
7937 {
7938 int bcst_type;
7939
7940 if (i.broadcast)
7941 goto duplicated_vec_op;
7942
7943 op_string += 3;
7944 if (*op_string == '8')
7945 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7946 else if (*op_string == '4')
7947 bcst_type = BROADCAST_1TO4;
7948 else if (*op_string == '2')
7949 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7950 else if (*op_string == '1'
7951 && *(op_string+1) == '6')
7952 {
7953 bcst_type = BROADCAST_1TO16;
7954 op_string++;
7955 }
7956 else
7957 {
7958 as_bad (_("Unsupported broadcast: `%s'"), saved);
7959 return NULL;
7960 }
7961 op_string++;
7962
7963 broadcast_op.type = bcst_type;
7964 broadcast_op.operand = this_operand;
7965 i.broadcast = &broadcast_op;
7966 }
7967 /* Check masking operation. */
7968 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7969 {
7970 /* k0 can't be used for write mask. */
7971 if (mask->reg_num == 0)
7972 {
7973 as_bad (_("`%s' can't be used for write mask"),
7974 op_string);
7975 return NULL;
7976 }
7977
7978 if (!i.mask)
7979 {
7980 mask_op.mask = mask;
7981 mask_op.zeroing = 0;
7982 mask_op.operand = this_operand;
7983 i.mask = &mask_op;
7984 }
7985 else
7986 {
7987 if (i.mask->mask)
7988 goto duplicated_vec_op;
7989
7990 i.mask->mask = mask;
7991
7992 /* Only "{z}" is allowed here. No need to check
7993 zeroing mask explicitly. */
7994 if (i.mask->operand != this_operand)
7995 {
7996 as_bad (_("invalid write mask `%s'"), saved);
7997 return NULL;
7998 }
7999 }
8000
8001 op_string = end_op;
8002 }
8003 /* Check zeroing-flag for masking operation. */
8004 else if (*op_string == 'z')
8005 {
8006 if (!i.mask)
8007 {
8008 mask_op.mask = NULL;
8009 mask_op.zeroing = 1;
8010 mask_op.operand = this_operand;
8011 i.mask = &mask_op;
8012 }
8013 else
8014 {
8015 if (i.mask->zeroing)
8016 {
8017 duplicated_vec_op:
8018 as_bad (_("duplicated `%s'"), saved);
8019 return NULL;
8020 }
8021
8022 i.mask->zeroing = 1;
8023
8024 /* Only "{%k}" is allowed here. No need to check mask
8025 register explicitly. */
8026 if (i.mask->operand != this_operand)
8027 {
8028 as_bad (_("invalid zeroing-masking `%s'"),
8029 saved);
8030 return NULL;
8031 }
8032 }
8033
8034 op_string++;
8035 }
8036 else
8037 goto unknown_vec_op;
8038
8039 if (*op_string != '}')
8040 {
8041 as_bad (_("missing `}' in `%s'"), saved);
8042 return NULL;
8043 }
8044 op_string++;
8045 continue;
8046 }
8047 unknown_vec_op:
8048 /* We don't know this one. */
8049 as_bad (_("unknown vector operation: `%s'"), saved);
8050 return NULL;
8051 }
8052
8053 return op_string;
8054}
8055
252b5132 8056static int
70e41ade 8057i386_immediate (char *imm_start)
252b5132
RH		 8058{
8059 char *save_input_line_pointer;
f3c180ae 8060 char *gotfree_input_line;
252b5132 8061 segT exp_seg = 0;
47926f60 8062 expressionS *exp;
40fb9820
L		 8063 i386_operand_type types;
8064
0dfbf9d7 8065 operand_type_set (&types, ~0);
252b5132
RH		 8066
8067 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8068 {
31b2323c
L		 8069 as_bad (_("at most %d immediate operands are allowed"),
8070 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8071 return 0;
8072 }
8073
8074 exp = &im_expressions[i.imm_operands++];
520dc8e8 8075 i.op[this_operand].imms = exp;
252b5132
RH		 8076
8077 if (is_space_char (*imm_start))
8078 ++imm_start;
8079
8080 save_input_line_pointer = input_line_pointer;
8081 input_line_pointer = imm_start;
8082
d258b828 8083 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8084 if (gotfree_input_line)
8085 input_line_pointer = gotfree_input_line;
252b5132
RH		 8086
8087 exp_seg = expression (exp);
8088
83183c0c 8089 SKIP_WHITESPACE ();
43234a1e
L		 8090
8091 /* Handle vector operations. */
8092 if (*input_line_pointer == '{')
8093 {
8094 input_line_pointer = check_VecOperations (input_line_pointer,
8095 NULL);
8096 if (input_line_pointer == NULL)
8097 return 0;
8098 }
8099
252b5132 8100 if (*input_line_pointer)
f3c180ae 8101 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8102
8103 input_line_pointer = save_input_line_pointer;
f3c180ae 8104 if (gotfree_input_line)
ee86248c
JB		 8105 {
8106 free (gotfree_input_line);
8107
8108 if (exp->X_op == O_constant || exp->X_op == O_register)
8109 exp->X_op = O_illegal;
8110 }
8111
8112 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8113}
252b5132 8114
ee86248c
JB		 8115static int
8116i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8117 i386_operand_type types, const char *imm_start)
8118{
8119 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8120 {
313c53d1
L		 8121 if (imm_start)
8122 as_bad (_("missing or invalid immediate expression `%s'"),
8123 imm_start);
3992d3b7 8124 return 0;
252b5132 8125 }
3e73aa7c 8126 else if (exp->X_op == O_constant)
252b5132 8127 {
47926f60 8128 /* Size it properly later. */
40fb9820 8129 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8130 /* If not 64bit, sign extend val. */
8131 if (flag_code != CODE_64BIT
4eed87de
AM		 8132 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8133 exp->X_add_number
8134 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8135 }
4c63da97 8136#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8137 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8138 && exp_seg != absolute_section
47926f60 8139 && exp_seg != text_section
24eab124
AM		 8140 && exp_seg != data_section
8141 && exp_seg != bss_section
8142 && exp_seg != undefined_section
f86103b7 8143 && !bfd_is_com_section (exp_seg))
252b5132 8144 {
d0b47220 8145 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8146 return 0;
8147 }
8148#endif
a841bdf5 8149 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8150 {
313c53d1
L		 8151 if (imm_start)
8152 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8153 return 0;
8154 }
252b5132
RH		 8155 else
8156 {
8157 /* This is an address. The size of the address will be
24eab124 8158 determined later, depending on destination register,
3e73aa7c 8159 suffix, or the default for the section. */
40fb9820
L		 8160 i.types[this_operand].bitfield.imm8 = 1;
8161 i.types[this_operand].bitfield.imm16 = 1;
8162 i.types[this_operand].bitfield.imm32 = 1;
8163 i.types[this_operand].bitfield.imm32s = 1;
8164 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8165 i.types[this_operand] = operand_type_and (i.types[this_operand],
8166 types);
252b5132
RH		 8167 }
8168
8169 return 1;
8170}
8171
551c1ca1 8172static char *
e3bb37b5 8173i386_scale (char *scale)
252b5132 8174{
551c1ca1
AM		 8175 offsetT val;
8176 char *save = input_line_pointer;
252b5132 8177
551c1ca1
AM		 8178 input_line_pointer = scale;
8179 val = get_absolute_expression ();
8180
8181 switch (val)
252b5132 8182 {
551c1ca1 8183 case 1:
252b5132
RH		 8184 i.log2_scale_factor = 0;
8185 break;
551c1ca1 8186 case 2:
252b5132
RH		 8187 i.log2_scale_factor = 1;
8188 break;
551c1ca1 8189 case 4:
252b5132
RH		 8190 i.log2_scale_factor = 2;
8191 break;
551c1ca1 8192 case 8:
252b5132
RH		 8193 i.log2_scale_factor = 3;
8194 break;
8195 default:
a724f0f4
JB		 8196 {
8197 char sep = *input_line_pointer;
8198
8199 *input_line_pointer = '\0';
8200 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8201 scale);
8202 *input_line_pointer = sep;
8203 input_line_pointer = save;
8204 return NULL;
8205 }
252b5132 8206 }
29b0f896 8207 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8208 {
8209 as_warn (_("scale factor of %d without an index register"),
24eab124 8210 1 << i.log2_scale_factor);
252b5132 8211 i.log2_scale_factor = 0;
252b5132 8212 }
551c1ca1
AM		 8213 scale = input_line_pointer;
8214 input_line_pointer = save;
8215 return scale;
252b5132
RH		 8216}
8217
252b5132 8218static int
e3bb37b5 8219i386_displacement (char *disp_start, char *disp_end)
252b5132 8220{
29b0f896 8221 expressionS *exp;
252b5132
RH		 8222 segT exp_seg = 0;
8223 char *save_input_line_pointer;
f3c180ae 8224 char *gotfree_input_line;
40fb9820
L		 8225 int override;
8226 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8227 int ret;
252b5132 8228
31b2323c
L		 8229 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8230 {
8231 as_bad (_("at most %d displacement operands are allowed"),
8232 MAX_MEMORY_OPERANDS);
8233 return 0;
8234 }
8235
0dfbf9d7 8236 operand_type_set (&bigdisp, 0);
40fb9820
L		 8237 if ((i.types[this_operand].bitfield.jumpabsolute)
8238 || (!current_templates->start->opcode_modifier.jump
8239 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8240 {
40fb9820 8241 bigdisp.bitfield.disp32 = 1;
e05278af 8242 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8243 if (flag_code == CODE_64BIT)
8244 {
8245 if (!override)
8246 {
8247 bigdisp.bitfield.disp32s = 1;
8248 bigdisp.bitfield.disp64 = 1;
8249 }
8250 }
8251 else if ((flag_code == CODE_16BIT) ^ override)
8252 {
8253 bigdisp.bitfield.disp32 = 0;
8254 bigdisp.bitfield.disp16 = 1;
8255 }
e05278af
JB		 8256 }
8257 else
8258 {
8259 /* For PC-relative branches, the width of the displacement
8260 is dependent upon data size, not address size. */
e05278af 8261 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8262 if (flag_code == CODE_64BIT)
8263 {
8264 if (override || i.suffix == WORD_MNEM_SUFFIX)
8265 bigdisp.bitfield.disp16 = 1;
8266 else
8267 {
8268 bigdisp.bitfield.disp32 = 1;
8269 bigdisp.bitfield.disp32s = 1;
8270 }
8271 }
8272 else
e05278af
JB		 8273 {
8274 if (!override)
8275 override = (i.suffix == (flag_code != CODE_16BIT
8276 ? WORD_MNEM_SUFFIX
8277 : LONG_MNEM_SUFFIX));
40fb9820
L		 8278 bigdisp.bitfield.disp32 = 1;
8279 if ((flag_code == CODE_16BIT) ^ override)
8280 {
8281 bigdisp.bitfield.disp32 = 0;
8282 bigdisp.bitfield.disp16 = 1;
8283 }
e05278af 8284 }
e05278af 8285 }
c6fb90c8
L		 8286 i.types[this_operand] = operand_type_or (i.types[this_operand],
8287 bigdisp);
252b5132
RH		 8288
8289 exp = &disp_expressions[i.disp_operands];
520dc8e8 8290 i.op[this_operand].disps = exp;
252b5132
RH		 8291 i.disp_operands++;
8292 save_input_line_pointer = input_line_pointer;
8293 input_line_pointer = disp_start;
8294 END_STRING_AND_SAVE (disp_end);
8295
8296#ifndef GCC_ASM_O_HACK
8297#define GCC_ASM_O_HACK 0
8298#endif
8299#if GCC_ASM_O_HACK
8300 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8301 if (i.types[this_operand].bitfield.baseIndex
24eab124 8302 && displacement_string_end[-1] == '+')
252b5132
RH		 8303 {
8304 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8305 constraint within gcc asm statements.
8306 For instance:
8307
8308 #define _set_tssldt_desc(n,addr,limit,type) \
8309 __asm__ __volatile__ ( \
8310 "movw %w2,%0\n\t" \
8311 "movw %w1,2+%0\n\t" \
8312 "rorl $16,%1\n\t" \
8313 "movb %b1,4+%0\n\t" \
8314 "movb %4,5+%0\n\t" \
8315 "movb $0,6+%0\n\t" \
8316 "movb %h1,7+%0\n\t" \
8317 "rorl $16,%1" \
8318 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8319
8320 This works great except that the output assembler ends
8321 up looking a bit weird if it turns out that there is
8322 no offset. You end up producing code that looks like:
8323
8324 #APP
8325 movw $235,(%eax)
8326 movw %dx,2+(%eax)
8327 rorl $16,%edx
8328 movb %dl,4+(%eax)
8329 movb $137,5+(%eax)
8330 movb $0,6+(%eax)
8331 movb %dh,7+(%eax)
8332 rorl $16,%edx
8333 #NO_APP
8334
47926f60 8335 So here we provide the missing zero. */
24eab124
AM		 8336
8337 *displacement_string_end = '0';
252b5132
RH		 8338 }
8339#endif
d258b828 8340 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8341 if (gotfree_input_line)
8342 input_line_pointer = gotfree_input_line;
252b5132 8343
24eab124 8344 exp_seg = expression (exp);
252b5132 8345
636c26b0
AM		 8346 SKIP_WHITESPACE ();
8347 if (*input_line_pointer)
8348 as_bad (_("junk `%s' after expression"), input_line_pointer);
8349#if GCC_ASM_O_HACK
8350 RESTORE_END_STRING (disp_end + 1);
8351#endif
636c26b0 8352 input_line_pointer = save_input_line_pointer;
636c26b0 8353 if (gotfree_input_line)
ee86248c
JB		 8354 {
8355 free (gotfree_input_line);
8356
8357 if (exp->X_op == O_constant || exp->X_op == O_register)
8358 exp->X_op = O_illegal;
8359 }
8360
8361 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8362
8363 RESTORE_END_STRING (disp_end);
8364
8365 return ret;
8366}
8367
8368static int
8369i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8370 i386_operand_type types, const char *disp_start)
8371{
8372 i386_operand_type bigdisp;
8373 int ret = 1;
636c26b0 8374
24eab124
AM		 8375 /* We do this to make sure that the section symbol is in
8376 the symbol table. We will ultimately change the relocation
47926f60 8377 to be relative to the beginning of the section. */
1ae12ab7 8378 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8379 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8380 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8381 {
636c26b0 8382 if (exp->X_op != O_symbol)
3992d3b7 8383 goto inv_disp;
636c26b0 8384
e5cb08ac 8385 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8386 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8387 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8388 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8389 exp->X_op = O_subtract;
8390 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8391 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8392 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8393 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8394 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8395 else
29b0f896 8396 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8397 }
252b5132 8398
3992d3b7
AM		 8399 else if (exp->X_op == O_absent
8400 || exp->X_op == O_illegal
ee86248c 8401 || exp->X_op == O_big)
2daf4fd8 8402 {
3992d3b7
AM		 8403 inv_disp:
8404 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8405 disp_start);
3992d3b7 8406 ret = 0;
2daf4fd8
AM		 8407 }
8408
0e1147d9
L		 8409 else if (flag_code == CODE_64BIT
8410 && !i.prefix[ADDR_PREFIX]
8411 && exp->X_op == O_constant)
8412 {
8413 /* Since displacement is signed extended to 64bit, don't allow
8414 disp32 and turn off disp32s if they are out of range. */
8415 i.types[this_operand].bitfield.disp32 = 0;
8416 if (!fits_in_signed_long (exp->X_add_number))
8417 {
8418 i.types[this_operand].bitfield.disp32s = 0;
8419 if (i.types[this_operand].bitfield.baseindex)
8420 {
8421 as_bad (_("0x%lx out range of signed 32bit displacement"),
8422 (long) exp->X_add_number);
8423 ret = 0;
8424 }
8425 }
8426 }
8427
4c63da97 8428#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8429 else if (exp->X_op != O_constant
8430 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8431 && exp_seg != absolute_section
8432 && exp_seg != text_section
8433 && exp_seg != data_section
8434 && exp_seg != bss_section
8435 && exp_seg != undefined_section
8436 && !bfd_is_com_section (exp_seg))
24eab124 8437 {
d0b47220 8438 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8439 ret = 0;
24eab124 8440 }
252b5132 8441#endif
3956db08 8442
40fb9820
L		 8443 /* Check if this is a displacement only operand. */
8444 bigdisp = i.types[this_operand];
8445 bigdisp.bitfield.disp8 = 0;
8446 bigdisp.bitfield.disp16 = 0;
8447 bigdisp.bitfield.disp32 = 0;
8448 bigdisp.bitfield.disp32s = 0;
8449 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8450 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8451 i.types[this_operand] = operand_type_and (i.types[this_operand],
8452 types);
3956db08 8453
3992d3b7 8454 return ret;
252b5132
RH		 8455}
8456
eecb386c 8457/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8458 Return 1 on success, 0 on a failure. */
8459
252b5132 8460static int
e3bb37b5 8461i386_index_check (const char *operand_string)
252b5132 8462{
fc0763e6 8463 const char *kind = "base/index";
be05d201
L		 8464 enum flag_code addr_mode;
8465
8466 if (i.prefix[ADDR_PREFIX])
8467 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8468 else
8469 {
8470 addr_mode = flag_code;
8471
24eab124 8472#if INFER_ADDR_PREFIX
be05d201
L		 8473 if (i.mem_operands == 0)
8474 {
8475 /* Infer address prefix from the first memory operand. */
8476 const reg_entry *addr_reg = i.base_reg;
8477
8478 if (addr_reg == NULL)
8479 addr_reg = i.index_reg;
eecb386c 8480
be05d201
L		 8481 if (addr_reg)
8482 {
8483 if (addr_reg->reg_num == RegEip
8484 || addr_reg->reg_num == RegEiz
8485 || addr_reg->reg_type.bitfield.reg32)
8486 addr_mode = CODE_32BIT;
8487 else if (flag_code != CODE_64BIT
8488 && addr_reg->reg_type.bitfield.reg16)
8489 addr_mode = CODE_16BIT;
8490
8491 if (addr_mode != flag_code)
8492 {
8493 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8494 i.prefixes += 1;
8495 /* Change the size of any displacement too. At most one
8496 of Disp16 or Disp32 is set.
8497 FIXME. There doesn't seem to be any real need for
8498 separate Disp16 and Disp32 flags. The same goes for
8499 Imm16 and Imm32. Removing them would probably clean
8500 up the code quite a lot. */
8501 if (flag_code != CODE_64BIT
8502 && (i.types[this_operand].bitfield.disp16
8503 || i.types[this_operand].bitfield.disp32))
8504 i.types[this_operand]
8505 = operand_type_xor (i.types[this_operand], disp16_32);
8506 }
8507 }
8508 }
24eab124 8509#endif
be05d201
L		 8510 }
8511
fc0763e6
JB		 8512 if (current_templates->start->opcode_modifier.isstring
8513 && !current_templates->start->opcode_modifier.immext
8514 && (current_templates->end[-1].opcode_modifier.isstring
8515 || i.mem_operands))
8516 {
8517 /* Memory operands of string insns are special in that they only allow
8518 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8519 const reg_entry *expected_reg;
8520 static const char *di_si[][2] =
8521 {
8522 { "esi", "edi" },
8523 { "si", "di" },
8524 { "rsi", "rdi" }
8525 };
8526 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8527
8528 kind = "string address";
8529
8325cc63 8530 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8531 {
8532 i386_operand_type type = current_templates->end[-1].operand_types[0];
8533
8534 if (!type.bitfield.baseindex
8535 || ((!i.mem_operands != !intel_syntax)
8536 && current_templates->end[-1].operand_types[1]
8537 .bitfield.baseindex))
8538 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8539 expected_reg = hash_find (reg_hash,
8540 di_si[addr_mode][type.bitfield.esseg]);
8541
fc0763e6
JB		 8542 }
8543 else
be05d201 8544 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8545
be05d201
L		 8546 if (i.base_reg != expected_reg
8547 || i.index_reg
fc0763e6 8548 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8549 {
be05d201
L		 8550 /* The second memory operand must have the same size as
8551 the first one. */
8552 if (i.mem_operands
8553 && i.base_reg
8554 && !((addr_mode == CODE_64BIT
8555 && i.base_reg->reg_type.bitfield.reg64)
8556 || (addr_mode == CODE_32BIT
8557 ? i.base_reg->reg_type.bitfield.reg32
8558 : i.base_reg->reg_type.bitfield.reg16)))
8559 goto bad_address;
8560
fc0763e6
JB		 8561 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8562 operand_string,
8563 intel_syntax ? '[' : '(',
8564 register_prefix,
be05d201 8565 expected_reg->reg_name,
fc0763e6 8566 intel_syntax ? ']' : ')');
be05d201 8567 return 1;
fc0763e6 8568 }
be05d201
L		 8569 else
8570 return 1;
8571
8572bad_address:
8573 as_bad (_("`%s' is not a valid %s expression"),
8574 operand_string, kind);
8575 return 0;
3e73aa7c
JH		 8576 }
8577 else
8578 {
be05d201
L		 8579 if (addr_mode != CODE_16BIT)
8580 {
8581 /* 32-bit/64-bit checks. */
8582 if ((i.base_reg
8583 && (addr_mode == CODE_64BIT
8584 ? !i.base_reg->reg_type.bitfield.reg64
8585 : !i.base_reg->reg_type.bitfield.reg32)
8586 && (i.index_reg
8587 || (i.base_reg->reg_num
8588 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8589 || (i.index_reg
8590 && !i.index_reg->reg_type.bitfield.regxmm
8591 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8592 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8593 && ((addr_mode == CODE_64BIT
8594 ? !(i.index_reg->reg_type.bitfield.reg64
8595 || i.index_reg->reg_num == RegRiz)
8596 : !(i.index_reg->reg_type.bitfield.reg32
8597 || i.index_reg->reg_num == RegEiz))
8598 || !i.index_reg->reg_type.bitfield.baseindex)))
8599 goto bad_address;
8178be5b
JB		 8600
8601 /* bndmk, bndldx, and bndstx have special restrictions. */
8602 if (current_templates->start->base_opcode == 0xf30f1b
8603 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8604 {
8605 /* They cannot use RIP-relative addressing. */
8606 if (i.base_reg && i.base_reg->reg_num == RegRip)
8607 {
8608 as_bad (_("`%s' cannot be used here"), operand_string);
8609 return 0;
8610 }
8611
8612 /* bndldx and bndstx ignore their scale factor. */
8613 if (current_templates->start->base_opcode != 0xf30f1b
8614 && i.log2_scale_factor)
8615 as_warn (_("register scaling is being ignored here"));
8616 }
be05d201
L		 8617 }
8618 else
3e73aa7c 8619 {
be05d201 8620 /* 16-bit checks. */
3e73aa7c 8621 if ((i.base_reg
40fb9820
L		 8622 && (!i.base_reg->reg_type.bitfield.reg16
8623 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8624 || (i.index_reg
40fb9820
L		 8625 && (!i.index_reg->reg_type.bitfield.reg16
8626 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8627 || !(i.base_reg
8628 && i.base_reg->reg_num < 6
8629 && i.index_reg->reg_num >= 6
8630 && i.log2_scale_factor == 0))))
be05d201 8631 goto bad_address;
3e73aa7c
JH		 8632 }
8633 }
be05d201 8634 return 1;
24eab124 8635}
252b5132 8636
43234a1e
L		 8637/* Handle vector immediates. */
8638
8639static int
8640RC_SAE_immediate (const char *imm_start)
8641{
8642 unsigned int match_found, j;
8643 const char *pstr = imm_start;
8644 expressionS *exp;
8645
8646 if (*pstr != '{')
8647 return 0;
8648
8649 pstr++;
8650 match_found = 0;
8651 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8652 {
8653 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8654 {
8655 if (!i.rounding)
8656 {
8657 rc_op.type = RC_NamesTable[j].type;
8658 rc_op.operand = this_operand;
8659 i.rounding = &rc_op;
8660 }
8661 else
8662 {
8663 as_bad (_("duplicated `%s'"), imm_start);
8664 return 0;
8665 }
8666 pstr += RC_NamesTable[j].len;
8667 match_found = 1;
8668 break;
8669 }
8670 }
8671 if (!match_found)
8672 return 0;
8673
8674 if (*pstr++ != '}')
8675 {
8676 as_bad (_("Missing '}': '%s'"), imm_start);
8677 return 0;
8678 }
8679 /* RC/SAE immediate string should contain nothing more. */;
8680 if (*pstr != 0)
8681 {
8682 as_bad (_("Junk after '}': '%s'"), imm_start);
8683 return 0;
8684 }
8685
8686 exp = &im_expressions[i.imm_operands++];
8687 i.op[this_operand].imms = exp;
8688
8689 exp->X_op = O_constant;
8690 exp->X_add_number = 0;
8691 exp->X_add_symbol = (symbolS *) 0;
8692 exp->X_op_symbol = (symbolS *) 0;
8693
8694 i.types[this_operand].bitfield.imm8 = 1;
8695 return 1;
8696}
8697
8325cc63
JB		 8698/* Only string instructions can have a second memory operand, so
8699 reduce current_templates to just those if it contains any. */
8700static int
8701maybe_adjust_templates (void)
8702{
8703 const insn_template *t;
8704
8705 gas_assert (i.mem_operands == 1);
8706
8707 for (t = current_templates->start; t < current_templates->end; ++t)
8708 if (t->opcode_modifier.isstring)
8709 break;
8710
8711 if (t < current_templates->end)
8712 {
8713 static templates aux_templates;
8714 bfd_boolean recheck;
8715
8716 aux_templates.start = t;
8717 for (; t < current_templates->end; ++t)
8718 if (!t->opcode_modifier.isstring)
8719 break;
8720 aux_templates.end = t;
8721
8722 /* Determine whether to re-check the first memory operand. */
8723 recheck = (aux_templates.start != current_templates->start
8724 || t != current_templates->end);
8725
8726 current_templates = &aux_templates;
8727
8728 if (recheck)
8729 {
8730 i.mem_operands = 0;
8731 if (i.memop1_string != NULL
8732 && i386_index_check (i.memop1_string) == 0)
8733 return 0;
8734 i.mem_operands = 1;
8735 }
8736 }
8737
8738 return 1;
8739}
8740
fc0763e6 8741/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8742 on error. */
252b5132 8743
252b5132 8744static int
a7619375 8745i386_att_operand (char *operand_string)
252b5132 8746{
af6bdddf
AM		 8747 const reg_entry *r;
8748 char *end_op;
24eab124 8749 char *op_string = operand_string;
252b5132 8750
24eab124 8751 if (is_space_char (*op_string))
252b5132
RH		 8752 ++op_string;
8753
24eab124 8754 /* We check for an absolute prefix (differentiating,
47926f60 8755 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8756 if (*op_string == ABSOLUTE_PREFIX)
8757 {
8758 ++op_string;
8759 if (is_space_char (*op_string))
8760 ++op_string;
40fb9820 8761 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8762 }
252b5132 8763
47926f60 8764 /* Check if operand is a register. */
4d1bb795 8765 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8766 {
40fb9820
L		 8767 i386_operand_type temp;
8768
24eab124
AM		 8769 /* Check for a segment override by searching for ':' after a
8770 segment register. */
8771 op_string = end_op;
8772 if (is_space_char (*op_string))
8773 ++op_string;
40fb9820
L		 8774 if (*op_string == ':'
8775 && (r->reg_type.bitfield.sreg2
8776 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8777 {
8778 switch (r->reg_num)
8779 {
8780 case 0:
8781 i.seg[i.mem_operands] = &es;
8782 break;
8783 case 1:
8784 i.seg[i.mem_operands] = &cs;
8785 break;
8786 case 2:
8787 i.seg[i.mem_operands] = &ss;
8788 break;
8789 case 3:
8790 i.seg[i.mem_operands] = &ds;
8791 break;
8792 case 4:
8793 i.seg[i.mem_operands] = &fs;
8794 break;
8795 case 5:
8796 i.seg[i.mem_operands] = &gs;
8797 break;
8798 }
252b5132 8799
24eab124 8800 /* Skip the ':' and whitespace. */
252b5132
RH		 8801 ++op_string;
8802 if (is_space_char (*op_string))
24eab124 8803 ++op_string;
252b5132 8804
24eab124
AM		 8805 if (!is_digit_char (*op_string)
8806 && !is_identifier_char (*op_string)
8807 && *op_string != '('
8808 && *op_string != ABSOLUTE_PREFIX)
8809 {
8810 as_bad (_("bad memory operand `%s'"), op_string);
8811 return 0;
8812 }
47926f60 8813 /* Handle case of %es:*foo. */
24eab124
AM		 8814 if (*op_string == ABSOLUTE_PREFIX)
8815 {
8816 ++op_string;
8817 if (is_space_char (*op_string))
8818 ++op_string;
40fb9820 8819 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8820 }
8821 goto do_memory_reference;
8822 }
43234a1e
L		 8823
8824 /* Handle vector operations. */
8825 if (*op_string == '{')
8826 {
8827 op_string = check_VecOperations (op_string, NULL);
8828 if (op_string == NULL)
8829 return 0;
8830 }
8831
24eab124
AM		 8832 if (*op_string)
8833 {
d0b47220 8834 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8835 return 0;
8836 }
40fb9820
L		 8837 temp = r->reg_type;
8838 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8839 i.types[this_operand] = operand_type_or (i.types[this_operand],
8840 temp);
7d5e4556 8841 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8842 i.op[this_operand].regs = r;
24eab124
AM		 8843 i.reg_operands++;
8844 }
af6bdddf
AM		 8845 else if (*op_string == REGISTER_PREFIX)
8846 {
8847 as_bad (_("bad register name `%s'"), op_string);
8848 return 0;
8849 }
24eab124 8850 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8851 {
24eab124 8852 ++op_string;
40fb9820 8853 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8854 {
d0b47220 8855 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8856 return 0;
8857 }
8858 if (!i386_immediate (op_string))
8859 return 0;
8860 }
43234a1e
L		 8861 else if (RC_SAE_immediate (operand_string))
8862 {
8863 /* If it is a RC or SAE immediate, do nothing. */
8864 ;
8865 }
24eab124
AM		 8866 else if (is_digit_char (*op_string)
8867 || is_identifier_char (*op_string)
d02603dc 8868 || *op_string == '"'
e5cb08ac 8869 || *op_string == '(')
24eab124 8870 {
47926f60 8871 /* This is a memory reference of some sort. */
af6bdddf 8872 char *base_string;
252b5132 8873
47926f60 8874 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8875 char *displacement_string_start;
8876 char *displacement_string_end;
43234a1e 8877 char *vop_start;
252b5132 8878
24eab124 8879 do_memory_reference:
8325cc63
JB		 8880 if (i.mem_operands == 1 && !maybe_adjust_templates ())
8881 return 0;
24eab124 8882 if ((i.mem_operands == 1
40fb9820 8883 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8884 || i.mem_operands == 2)
8885 {
8886 as_bad (_("too many memory references for `%s'"),
8887 current_templates->start->name);
8888 return 0;
8889 }
252b5132 8890
24eab124
AM		 8891 /* Check for base index form. We detect the base index form by
8892 looking for an ')' at the end of the operand, searching
8893 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8894 after the '('. */
af6bdddf 8895 base_string = op_string + strlen (op_string);
c3332e24 8896
43234a1e
L		 8897 /* Handle vector operations. */
8898 vop_start = strchr (op_string, '{');
8899 if (vop_start && vop_start < base_string)
8900 {
8901 if (check_VecOperations (vop_start, base_string) == NULL)
8902 return 0;
8903 base_string = vop_start;
8904 }
8905
af6bdddf
AM		 8906 --base_string;
8907 if (is_space_char (*base_string))
8908 --base_string;
252b5132 8909
47926f60 8910 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8911 displacement_string_start = op_string;
8912 displacement_string_end = base_string + 1;
252b5132 8913
24eab124
AM		 8914 if (*base_string == ')')
8915 {
af6bdddf 8916 char *temp_string;
24eab124
AM		 8917 unsigned int parens_balanced = 1;
8918 /* We've already checked that the number of left & right ()'s are
47926f60 8919 equal, so this loop will not be infinite. */
24eab124
AM		 8920 do
8921 {
8922 base_string--;
8923 if (*base_string == ')')
8924 parens_balanced++;
8925 if (*base_string == '(')
8926 parens_balanced--;
8927 }
8928 while (parens_balanced);
c3332e24 8929
af6bdddf 8930 temp_string = base_string;
c3332e24 8931
24eab124 8932 /* Skip past '(' and whitespace. */
252b5132
RH		 8933 ++base_string;
8934 if (is_space_char (*base_string))
24eab124 8935 ++base_string;
252b5132 8936
af6bdddf 8937 if (*base_string == ','
4eed87de
AM		 8938 || ((i.base_reg = parse_register (base_string, &end_op))
8939 != NULL))
252b5132 8940 {
af6bdddf 8941 displacement_string_end = temp_string;
252b5132 8942
40fb9820 8943 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8944
af6bdddf 8945 if (i.base_reg)
24eab124 8946 {
24eab124
AM		 8947 base_string = end_op;
8948 if (is_space_char (*base_string))
8949 ++base_string;
af6bdddf
AM		 8950 }
8951
8952 /* There may be an index reg or scale factor here. */
8953 if (*base_string == ',')
8954 {
8955 ++base_string;
8956 if (is_space_char (*base_string))
8957 ++base_string;
8958
4eed87de
AM		 8959 if ((i.index_reg = parse_register (base_string, &end_op))
8960 != NULL)
24eab124 8961 {
af6bdddf 8962 base_string = end_op;
24eab124
AM		 8963 if (is_space_char (*base_string))
8964 ++base_string;
af6bdddf
AM		 8965 if (*base_string == ',')
8966 {
8967 ++base_string;
8968 if (is_space_char (*base_string))
8969 ++base_string;
8970 }
e5cb08ac 8971 else if (*base_string != ')')
af6bdddf 8972 {
4eed87de
AM		 8973 as_bad (_("expecting `,' or `)' "
8974 "after index register in `%s'"),
af6bdddf
AM		 8975 operand_string);
8976 return 0;
8977 }
24eab124 8978 }
af6bdddf 8979 else if (*base_string == REGISTER_PREFIX)
24eab124 8980 {
f76bf5e0
L		 8981 end_op = strchr (base_string, ',');
8982 if (end_op)
8983 *end_op = '\0';
af6bdddf 8984 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8985 return 0;
8986 }
252b5132 8987
47926f60 8988 /* Check for scale factor. */
551c1ca1 8989 if (*base_string != ')')
af6bdddf 8990 {
551c1ca1
AM		 8991 char *end_scale = i386_scale (base_string);
8992
8993 if (!end_scale)
af6bdddf 8994 return 0;
24eab124 8995
551c1ca1 8996 base_string = end_scale;
af6bdddf
AM		 8997 if (is_space_char (*base_string))
8998 ++base_string;
8999 if (*base_string != ')')
9000 {
4eed87de
AM		 9001 as_bad (_("expecting `)' "
9002 "after scale factor in `%s'"),
af6bdddf
AM		 9003 operand_string);
9004 return 0;
9005 }
9006 }
9007 else if (!i.index_reg)
24eab124 9008 {
4eed87de
AM		 9009 as_bad (_("expecting index register or scale factor "
9010 "after `,'; got '%c'"),
af6bdddf 9011 *base_string);
24eab124
AM		 9012 return 0;
9013 }
9014 }
af6bdddf 9015 else if (*base_string != ')')
24eab124 9016 {
4eed87de
AM		 9017 as_bad (_("expecting `,' or `)' "
9018 "after base register in `%s'"),
af6bdddf 9019 operand_string);
24eab124
AM		 9020 return 0;
9021 }
c3332e24 9022 }
af6bdddf 9023 else if (*base_string == REGISTER_PREFIX)
c3332e24 9024 {
f76bf5e0
L		 9025 end_op = strchr (base_string, ',');
9026 if (end_op)
9027 *end_op = '\0';
af6bdddf 9028 as_bad (_("bad register name `%s'"), base_string);
24eab124 9029 return 0;
c3332e24 9030 }
24eab124
AM		 9031 }
9032
9033 /* If there's an expression beginning the operand, parse it,
9034 assuming displacement_string_start and
9035 displacement_string_end are meaningful. */
9036 if (displacement_string_start != displacement_string_end)
9037 {
9038 if (!i386_displacement (displacement_string_start,
9039 displacement_string_end))
9040 return 0;
9041 }
9042
9043 /* Special case for (%dx) while doing input/output op. */
9044 if (i.base_reg
0dfbf9d7
L		 9045 && operand_type_equal (&i.base_reg->reg_type,
9046 &reg16_inoutportreg)
24eab124
AM		 9047 && i.index_reg == 0
9048 && i.log2_scale_factor == 0
9049 && i.seg[i.mem_operands] == 0
40fb9820 9050 && !operand_type_check (i.types[this_operand], disp))
24eab124 9051 {
65da13b5 9052 i.types[this_operand] = inoutportreg;
24eab124
AM		 9053 return 1;
9054 }
9055
eecb386c
AM		 9056 if (i386_index_check (operand_string) == 0)
9057 return 0;
5c07affc 9058 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9059 if (i.mem_operands == 0)
9060 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9061 i.mem_operands++;
9062 }
9063 else
ce8a8b2f
AM		 9064 {
9065 /* It's not a memory operand; argh! */
24eab124
AM		 9066 as_bad (_("invalid char %s beginning operand %d `%s'"),
9067 output_invalid (*op_string),
9068 this_operand + 1,
9069 op_string);
9070 return 0;
9071 }
47926f60 9072 return 1; /* Normal return. */
252b5132
RH		 9073}
9074\f
fa94de6b
RM		 9075/* Calculate the maximum variable size (i.e., excluding fr_fix)
9076 that an rs_machine_dependent frag may reach. */
9077
9078unsigned int
9079i386_frag_max_var (fragS *frag)
9080{
9081 /* The only relaxable frags are for jumps.
9082 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9083 gas_assert (frag->fr_type == rs_machine_dependent);
9084 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9085}
9086
b084df0b
L		 9087#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9088static int
8dcea932 9089elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9090{
9091 /* STT_GNU_IFUNC symbol must go through PLT. */
9092 if ((symbol_get_bfdsym (fr_symbol)->flags
9093 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9094 return 0;
9095
9096 if (!S_IS_EXTERNAL (fr_symbol))
9097 /* Symbol may be weak or local. */
9098 return !S_IS_WEAK (fr_symbol);
9099
8dcea932
L		 9100 /* Global symbols with non-default visibility can't be preempted. */
9101 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9102 return 1;
9103
9104 if (fr_var != NO_RELOC)
9105 switch ((enum bfd_reloc_code_real) fr_var)
9106 {
9107 case BFD_RELOC_386_PLT32:
9108 case BFD_RELOC_X86_64_PLT32:
9109 /* Symbol with PLT relocatin may be preempted. */
9110 return 0;
9111 default:
9112 abort ();
9113 }
9114
b084df0b
L		 9115 /* Global symbols with default visibility in a shared library may be
9116 preempted by another definition. */
8dcea932 9117 return !shared;
b084df0b
L		 9118}
9119#endif
9120
ee7fcc42
AM		 9121/* md_estimate_size_before_relax()
9122
9123 Called just before relax() for rs_machine_dependent frags. The x86
9124 assembler uses these frags to handle variable size jump
9125 instructions.
9126
9127 Any symbol that is now undefined will not become defined.
9128 Return the correct fr_subtype in the frag.
9129 Return the initial "guess for variable size of frag" to caller.
9130 The guess is actually the growth beyond the fixed part. Whatever
9131 we do to grow the fixed or variable part contributes to our
9132 returned value. */
9133
252b5132 9134int
7016a5d5 9135md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9136{
252b5132 9137 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9138 check for un-relaxable symbols. On an ELF system, we can't relax
9139 an externally visible symbol, because it may be overridden by a
9140 shared library. */
9141 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9142#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9143 || (IS_ELF
8dcea932
L		 9144 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9145 fragP->fr_var))
fbeb56a4
DK		 9146#endif
9147#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9148 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9149 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9150#endif
9151 )
252b5132 9152 {
b98ef147
AM		 9153 /* Symbol is undefined in this segment, or we need to keep a
9154 reloc so that weak symbols can be overridden. */
9155 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9156 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9157 unsigned char *opcode;
9158 int old_fr_fix;
f6af82bd 9159
ee7fcc42 9160 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9161 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9162 else if (size == 2)
f6af82bd
AM		 9163 reloc_type = BFD_RELOC_16_PCREL;
9164 else
9165 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9166
ee7fcc42
AM		 9167 old_fr_fix = fragP->fr_fix;
9168 opcode = (unsigned char *) fragP->fr_opcode;
9169
fddf5b5b 9170 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9171 {
fddf5b5b
AM		 9172 case UNCOND_JUMP:
9173 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9174 opcode[0] = 0xe9;
252b5132 9175 fragP->fr_fix += size;
062cd5e7
AS		 9176 fix_new (fragP, old_fr_fix, size,
9177 fragP->fr_symbol,
9178 fragP->fr_offset, 1,
9179 reloc_type);
252b5132
RH		 9180 break;
9181
fddf5b5b 9182 case COND_JUMP86:
412167cb
AM		 9183 if (size == 2
9184 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9185 {
9186 /* Negate the condition, and branch past an
9187 unconditional jump. */
9188 opcode[0] ^= 1;
9189 opcode[1] = 3;
9190 /* Insert an unconditional jump. */
9191 opcode[2] = 0xe9;
9192 /* We added two extra opcode bytes, and have a two byte
9193 offset. */
9194 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9195 fix_new (fragP, old_fr_fix + 2, 2,
9196 fragP->fr_symbol,
9197 fragP->fr_offset, 1,
9198 reloc_type);
fddf5b5b
AM		 9199 break;
9200 }
9201 /* Fall through. */
9202
9203 case COND_JUMP:
412167cb
AM		 9204 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9205 {
3e02c1cc
AM		 9206 fixS *fixP;
9207
412167cb 9208 fragP->fr_fix += 1;
3e02c1cc
AM		 9209 fixP = fix_new (fragP, old_fr_fix, 1,
9210 fragP->fr_symbol,
9211 fragP->fr_offset, 1,
9212 BFD_RELOC_8_PCREL);
9213 fixP->fx_signed = 1;
412167cb
AM		 9214 break;
9215 }
93c2a809 9216
24eab124 9217 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9218 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9219 opcode[1] = opcode[0] + 0x10;
f6af82bd 9220 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9221 /* We've added an opcode byte. */
9222 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9223 fix_new (fragP, old_fr_fix + 1, size,
9224 fragP->fr_symbol,
9225 fragP->fr_offset, 1,
9226 reloc_type);
252b5132 9227 break;
fddf5b5b
AM		 9228
9229 default:
9230 BAD_CASE (fragP->fr_subtype);
9231 break;
252b5132
RH		 9232 }
9233 frag_wane (fragP);
ee7fcc42 9234 return fragP->fr_fix - old_fr_fix;
252b5132 9235 }
93c2a809 9236
93c2a809
AM		 9237 /* Guess size depending on current relax state. Initially the relax
9238 state will correspond to a short jump and we return 1, because
9239 the variable part of the frag (the branch offset) is one byte
9240 long. However, we can relax a section more than once and in that
9241 case we must either set fr_subtype back to the unrelaxed state,
9242 or return the value for the appropriate branch. */
9243 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9244}
9245
47926f60
KH		 9246/* Called after relax() is finished.
9247
9248 In: Address of frag.
9249 fr_type == rs_machine_dependent.
9250 fr_subtype is what the address relaxed to.
9251
9252 Out: Any fixSs and constants are set up.
9253 Caller will turn frag into a ".space 0". */
9254
252b5132 9255void
7016a5d5
TG		 9256md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9257 fragS *fragP)
252b5132 9258{
29b0f896 9259 unsigned char *opcode;
252b5132 9260 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9261 offsetT target_address;
9262 offsetT opcode_address;
252b5132 9263 unsigned int extension = 0;
847f7ad4 9264 offsetT displacement_from_opcode_start;
252b5132
RH		 9265
9266 opcode = (unsigned char *) fragP->fr_opcode;
9267
47926f60 9268 /* Address we want to reach in file space. */
252b5132 9269 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9270
47926f60 9271 /* Address opcode resides at in file space. */
252b5132
RH		 9272 opcode_address = fragP->fr_address + fragP->fr_fix;
9273
47926f60 9274 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9275 displacement_from_opcode_start = target_address - opcode_address;
9276
fddf5b5b 9277 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9278 {
47926f60
KH		 9279 /* Don't have to change opcode. */
9280 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9281 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9282 }
9283 else
9284 {
9285 if (no_cond_jump_promotion
9286 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9287 as_warn_where (fragP->fr_file, fragP->fr_line,
9288 _("long jump required"));
252b5132 9289
fddf5b5b
AM		 9290 switch (fragP->fr_subtype)
9291 {
9292 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9293 extension = 4; /* 1 opcode + 4 displacement */
9294 opcode[0] = 0xe9;
9295 where_to_put_displacement = &opcode[1];
9296 break;
252b5132 9297
fddf5b5b
AM		 9298 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9299 extension = 2; /* 1 opcode + 2 displacement */
9300 opcode[0] = 0xe9;
9301 where_to_put_displacement = &opcode[1];
9302 break;
252b5132 9303
fddf5b5b
AM		 9304 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9305 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9306 extension = 5; /* 2 opcode + 4 displacement */
9307 opcode[1] = opcode[0] + 0x10;
9308 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9309 where_to_put_displacement = &opcode[2];
9310 break;
252b5132 9311
fddf5b5b
AM		 9312 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9313 extension = 3; /* 2 opcode + 2 displacement */
9314 opcode[1] = opcode[0] + 0x10;
9315 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9316 where_to_put_displacement = &opcode[2];
9317 break;
252b5132 9318
fddf5b5b
AM		 9319 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9320 extension = 4;
9321 opcode[0] ^= 1;
9322 opcode[1] = 3;
9323 opcode[2] = 0xe9;
9324 where_to_put_displacement = &opcode[3];
9325 break;
9326
9327 default:
9328 BAD_CASE (fragP->fr_subtype);
9329 break;
9330 }
252b5132 9331 }
fddf5b5b 9332
7b81dfbb
AJ		 9333 /* If size if less then four we are sure that the operand fits,
9334 but if it's 4, then it could be that the displacement is larger
9335 then -/+ 2GB. */
9336 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9337 && object_64bit
9338 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9339 + ((addressT) 1 << 31))
9340 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9341 {
9342 as_bad_where (fragP->fr_file, fragP->fr_line,
9343 _("jump target out of range"));
9344 /* Make us emit 0. */
9345 displacement_from_opcode_start = extension;
9346 }
47926f60 9347 /* Now put displacement after opcode. */
252b5132
RH		 9348 md_number_to_chars ((char *) where_to_put_displacement,
9349 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9350 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9351 fragP->fr_fix += extension;
9352}
9353\f
7016a5d5 9354/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9355 by our caller that we have all the info we need to fix it up.
9356
7016a5d5
TG		 9357 Parameter valP is the pointer to the value of the bits.
9358
252b5132
RH		 9359 On the 386, immediates, displacements, and data pointers are all in
9360 the same (little-endian) format, so we don't need to care about which
9361 we are handling. */
9362
94f592af 9363void
7016a5d5 9364md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9365{
94f592af 9366 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9367 valueT value = *valP;
252b5132 9368
f86103b7 9369#if !defined (TE_Mach)
93382f6d
AM		 9370 if (fixP->fx_pcrel)
9371 {
9372 switch (fixP->fx_r_type)
9373 {
5865bb77
ILT		 9374 default:
9375 break;
9376
d6ab8113
JB		 9377 case BFD_RELOC_64:
9378 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9379 break;
93382f6d 9380 case BFD_RELOC_32:
ae8887b5 9381 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9382 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9383 break;
9384 case BFD_RELOC_16:
9385 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9386 break;
9387 case BFD_RELOC_8:
9388 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9389 break;
9390 }
9391 }
252b5132 9392
a161fe53 9393 if (fixP->fx_addsy != NULL
31312f95 9394 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9395 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9396 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9397 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9398 && !use_rela_relocations)
252b5132 9399 {
31312f95
AM		 9400 /* This is a hack. There should be a better way to handle this.
9401 This covers for the fact that bfd_install_relocation will
9402 subtract the current location (for partial_inplace, PC relative
9403 relocations); see more below. */
252b5132 9404#ifndef OBJ_AOUT
718ddfc0 9405 if (IS_ELF
252b5132
RH		 9406#ifdef TE_PE
9407 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9408#endif
9409 )
9410 value += fixP->fx_where + fixP->fx_frag->fr_address;
9411#endif
9412#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9413 if (IS_ELF)
252b5132 9414 {
6539b54b 9415 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9416
6539b54b 9417 if ((sym_seg == seg
2f66722d 9418 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9419 && sym_seg != absolute_section))
af65af87 9420 && !generic_force_reloc (fixP))
2f66722d
AM		 9421 {
9422 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9423 bfd_install_relocation subtracts them out again. I think
9424 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9425 it. FIXME. */
9426 value += fixP->fx_where + fixP->fx_frag->fr_address;
9427 }
252b5132
RH		 9428 }
9429#endif
9430#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9431 /* For some reason, the PE format does not store a
9432 section address offset for a PC relative symbol. */
9433 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9434 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9435 value += md_pcrel_from (fixP);
9436#endif
9437 }
fbeb56a4 9438#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9439 if (fixP->fx_addsy != NULL
9440 && S_IS_WEAK (fixP->fx_addsy)
9441 /* PR 16858: Do not modify weak function references. */
9442 && ! fixP->fx_pcrel)
fbeb56a4 9443 {
296a8689
NC		 9444#if !defined (TE_PEP)
9445 /* For x86 PE weak function symbols are neither PC-relative
9446 nor do they set S_IS_FUNCTION. So the only reliable way
9447 to detect them is to check the flags of their containing
9448 section. */
9449 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9450 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9451 ;
9452 else
9453#endif
fbeb56a4
DK		 9454 value -= S_GET_VALUE (fixP->fx_addsy);
9455 }
9456#endif
252b5132
RH		 9457
9458 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9459 and we must not disappoint it. */
252b5132 9460#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9461 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9462 switch (fixP->fx_r_type)
9463 {
9464 case BFD_RELOC_386_PLT32:
3e73aa7c 9465 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9466 /* Make the jump instruction point to the address of the operand. At
9467 runtime we merely add the offset to the actual PLT entry. */
9468 value = -4;
9469 break;
31312f95 9470
13ae64f3
JJ		 9471 case BFD_RELOC_386_TLS_GD:
9472 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9473 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9474 case BFD_RELOC_386_TLS_IE:
9475 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9476 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9477 case BFD_RELOC_X86_64_TLSGD:
9478 case BFD_RELOC_X86_64_TLSLD:
9479 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9480 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9481 value = 0; /* Fully resolved at runtime. No addend. */
9482 /* Fallthrough */
9483 case BFD_RELOC_386_TLS_LE:
9484 case BFD_RELOC_386_TLS_LDO_32:
9485 case BFD_RELOC_386_TLS_LE_32:
9486 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9487 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9488 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9489 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9490 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9491 break;
9492
67a4f2b7
AO		 9493 case BFD_RELOC_386_TLS_DESC_CALL:
9494 case BFD_RELOC_X86_64_TLSDESC_CALL:
9495 value = 0; /* Fully resolved at runtime. No addend. */
9496 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9497 fixP->fx_done = 0;
9498 return;
9499
47926f60
KH		 9500 case BFD_RELOC_VTABLE_INHERIT:
9501 case BFD_RELOC_VTABLE_ENTRY:
9502 fixP->fx_done = 0;
94f592af 9503 return;
47926f60
KH		 9504
9505 default:
9506 break;
9507 }
9508#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9509 *valP = value;
f86103b7 9510#endif /* !defined (TE_Mach) */
3e73aa7c 9511
3e73aa7c 9512 /* Are we finished with this relocation now? */
c6682705 9513 if (fixP->fx_addsy == NULL)
3e73aa7c 9514 fixP->fx_done = 1;
fbeb56a4
DK		 9515#if defined (OBJ_COFF) && defined (TE_PE)
9516 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9517 {
9518 fixP->fx_done = 0;
9519 /* Remember value for tc_gen_reloc. */
9520 fixP->fx_addnumber = value;
9521 /* Clear out the frag for now. */
9522 value = 0;
9523 }
9524#endif
3e73aa7c
JH		 9525 else if (use_rela_relocations)
9526 {
9527 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9528 /* Remember value for tc_gen_reloc. */
9529 fixP->fx_addnumber = value;
3e73aa7c
JH		 9530 value = 0;
9531 }
f86103b7 9532
94f592af 9533 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9534}
252b5132 9535\f
6d4af3c2 9536const char *
499ac353 9537md_atof (int type, char *litP, int *sizeP)
252b5132 9538{
499ac353
NC		 9539 /* This outputs the LITTLENUMs in REVERSE order;
9540 in accord with the bigendian 386. */
9541 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9542}
9543\f
2d545b82 9544static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9545
252b5132 9546static char *
e3bb37b5 9547output_invalid (int c)
252b5132 9548{
3882b010 9549 if (ISPRINT (c))
f9f21a03
L		 9550 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9551 "'%c'", c);
252b5132 9552 else
f9f21a03 9553 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9554 "(0x%x)", (unsigned char) c);
252b5132
RH		 9555 return output_invalid_buf;
9556}
9557
af6bdddf 9558/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9559
9560static const reg_entry *
4d1bb795 9561parse_real_register (char *reg_string, char **end_op)
252b5132 9562{
af6bdddf
AM		 9563 char *s = reg_string;
9564 char *p;
252b5132
RH		 9565 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9566 const reg_entry *r;
9567
9568 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9569 if (*s == REGISTER_PREFIX)
9570 ++s;
9571
9572 if (is_space_char (*s))
9573 ++s;
9574
9575 p = reg_name_given;
af6bdddf 9576 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9577 {
9578 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9579 return (const reg_entry *) NULL;
9580 s++;
252b5132
RH		 9581 }
9582
6588847e
DN		 9583 /* For naked regs, make sure that we are not dealing with an identifier.
9584 This prevents confusing an identifier like `eax_var' with register
9585 `eax'. */
9586 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9587 return (const reg_entry *) NULL;
9588
af6bdddf 9589 *end_op = s;
252b5132
RH		 9590
9591 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9592
5f47d35b 9593 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9594 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9595 {
5f47d35b
AM		 9596 if (is_space_char (*s))
9597 ++s;
9598 if (*s == '(')
9599 {
af6bdddf 9600 ++s;
5f47d35b
AM		 9601 if (is_space_char (*s))
9602 ++s;
9603 if (*s >= '0' && *s <= '7')
9604 {
db557034 9605 int fpr = *s - '0';
af6bdddf 9606 ++s;
5f47d35b
AM		 9607 if (is_space_char (*s))
9608 ++s;
9609 if (*s == ')')
9610 {
9611 *end_op = s + 1;
1e9cc1c2 9612 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9613 know (r);
9614 return r + fpr;
5f47d35b 9615 }
5f47d35b 9616 }
47926f60 9617 /* We have "%st(" then garbage. */
5f47d35b
AM		 9618 return (const reg_entry *) NULL;
9619 }
9620 }
9621
a60de03c
JB		 9622 if (r == NULL || allow_pseudo_reg)
9623 return r;
9624
0dfbf9d7 9625 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9626 return (const reg_entry *) NULL;
9627
192dc9c6
JB		 9628 if ((r->reg_type.bitfield.reg32
9629 || r->reg_type.bitfield.sreg3
9630 || r->reg_type.bitfield.control
9631 || r->reg_type.bitfield.debug
9632 || r->reg_type.bitfield.test)
9633 && !cpu_arch_flags.bitfield.cpui386)
9634 return (const reg_entry *) NULL;
9635
309d3373
JB		 9636 if (r->reg_type.bitfield.floatreg
9637 && !cpu_arch_flags.bitfield.cpu8087
9638 && !cpu_arch_flags.bitfield.cpu287
9639 && !cpu_arch_flags.bitfield.cpu387)
9640 return (const reg_entry *) NULL;
9641
1848e567 9642 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9643 return (const reg_entry *) NULL;
9644
1848e567 9645 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9646 return (const reg_entry *) NULL;
9647
1848e567 9648 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9649 return (const reg_entry *) NULL;
9650
1848e567
L		 9651 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9652 return (const reg_entry *) NULL;
9653
9654 if (r->reg_type.bitfield.regmask
9655 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9656 return (const reg_entry *) NULL;
9657
db51cc60 9658 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9659 if (!allow_index_reg
db51cc60
L		 9660 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9661 return (const reg_entry *) NULL;
9662
43234a1e
L		 9663 /* Upper 16 vector register is only available with VREX in 64bit
9664 mode. */
9665 if ((r->reg_flags & RegVRex))
9666 {
9667 if (!cpu_arch_flags.bitfield.cpuvrex
9668 || flag_code != CODE_64BIT)
9669 return (const reg_entry *) NULL;
9670
9671 i.need_vrex = 1;
9672 }
9673
a60de03c
JB		 9674 if (((r->reg_flags & (RegRex64 | RegRex))
9675 || r->reg_type.bitfield.reg64)
40fb9820 9676 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9677 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9678 && flag_code != CODE_64BIT)
20f0a1fc 9679 return (const reg_entry *) NULL;
1ae00879 9680
b7240065
JB		 9681 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9682 return (const reg_entry *) NULL;
9683
252b5132
RH		 9684 return r;
9685}
4d1bb795
JB		 9686
9687/* REG_STRING starts *before* REGISTER_PREFIX. */
9688
9689static const reg_entry *
9690parse_register (char *reg_string, char **end_op)
9691{
9692 const reg_entry *r;
9693
9694 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9695 r = parse_real_register (reg_string, end_op);
9696 else
9697 r = NULL;
9698 if (!r)
9699 {
9700 char *save = input_line_pointer;
9701 char c;
9702 symbolS *symbolP;
9703
9704 input_line_pointer = reg_string;
d02603dc 9705 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9706 symbolP = symbol_find (reg_string);
9707 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9708 {
9709 const expressionS *e = symbol_get_value_expression (symbolP);
9710
0398aac5 9711 know (e->X_op == O_register);
4eed87de 9712 know (e->X_add_number >= 0
c3fe08fa 9713 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9714 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9715 if ((r->reg_flags & RegVRex))
9716 i.need_vrex = 1;
4d1bb795
JB		 9717 *end_op = input_line_pointer;
9718 }
9719 *input_line_pointer = c;
9720 input_line_pointer = save;
9721 }
9722 return r;
9723}
9724
9725int
9726i386_parse_name (char *name, expressionS *e, char *nextcharP)
9727{
9728 const reg_entry *r;
9729 char *end = input_line_pointer;
9730
9731 *end = *nextcharP;
9732 r = parse_register (name, &input_line_pointer);
9733 if (r && end <= input_line_pointer)
9734 {
9735 *nextcharP = *input_line_pointer;
9736 *input_line_pointer = 0;
9737 e->X_op = O_register;
9738 e->X_add_number = r - i386_regtab;
9739 return 1;
9740 }
9741 input_line_pointer = end;
9742 *end = 0;
ee86248c 9743 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9744}
9745
9746void
9747md_operand (expressionS *e)
9748{
ee86248c
JB		 9749 char *end;
9750 const reg_entry *r;
4d1bb795 9751
ee86248c
JB		 9752 switch (*input_line_pointer)
9753 {
9754 case REGISTER_PREFIX:
9755 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9756 if (r)
9757 {
9758 e->X_op = O_register;
9759 e->X_add_number = r - i386_regtab;
9760 input_line_pointer = end;
9761 }
ee86248c
JB		 9762 break;
9763
9764 case '[':
9c2799c2 9765 gas_assert (intel_syntax);
ee86248c
JB		 9766 end = input_line_pointer++;
9767 expression (e);
9768 if (*input_line_pointer == ']')
9769 {
9770 ++input_line_pointer;
9771 e->X_op_symbol = make_expr_symbol (e);
9772 e->X_add_symbol = NULL;
9773 e->X_add_number = 0;
9774 e->X_op = O_index;
9775 }
9776 else
9777 {
9778 e->X_op = O_absent;
9779 input_line_pointer = end;
9780 }
9781 break;
4d1bb795
JB		 9782 }
9783}
9784
252b5132 9785\f
4cc782b5 9786#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9787const char *md_shortopts = "kVQ:sqn";
252b5132 9788#else
12b55ccc 9789const char *md_shortopts = "qn";
252b5132 9790#endif
6e0b89ee 9791
3e73aa7c 9792#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9793#define OPTION_64 (OPTION_MD_BASE + 1)
9794#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9795#define OPTION_MARCH (OPTION_MD_BASE + 3)
9796#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9797#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9798#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9799#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9800#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9801#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9802#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9803#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9804#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9805#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9806#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9807#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9808#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9809#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9810#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9811#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9812#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9813#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9814#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9815#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9816#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9817#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9818
99ad8390
NC		 9819struct option md_longopts[] =
9820{
3e73aa7c 9821 {"32", no_argument, NULL, OPTION_32},
321098a5 9822#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9823 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9824 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9825#endif
9826#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9827 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9828 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9829#endif
b3b91714 9830 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9831 {"march", required_argument, NULL, OPTION_MARCH},
9832 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9833 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9834 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9835 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9836 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9837 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9838 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9839 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9840 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9841 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9842 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9843 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9844 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9845# if defined (TE_PE) || defined (TE_PEP)
9846 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9847#endif
d1982f93 9848 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9849 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9850 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9851 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9852 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9853 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9854 {NULL, no_argument, NULL, 0}
9855};
9856size_t md_longopts_size = sizeof (md_longopts);
9857
9858int
17b9d67d 9859md_parse_option (int c, const char *arg)
252b5132 9860{
91d6fa6a 9861 unsigned int j;
293f5f65 9862 char *arch, *next, *saved;
9103f4f4 9863
252b5132
RH		 9864 switch (c)
9865 {
12b55ccc
L		 9866 case 'n':
9867 optimize_align_code = 0;
9868 break;
9869
a38cf1db
AM		 9870 case 'q':
9871 quiet_warnings = 1;
252b5132
RH		 9872 break;
9873
9874#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9875 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9876 should be emitted or not. FIXME: Not implemented. */
9877 case 'Q':
252b5132
RH		 9878 break;
9879
9880 /* -V: SVR4 argument to print version ID. */
9881 case 'V':
9882 print_version_id ();
9883 break;
9884
a38cf1db
AM		 9885 /* -k: Ignore for FreeBSD compatibility. */
9886 case 'k':
252b5132 9887 break;
4cc782b5
ILT		 9888
9889 case 's':
9890 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9891 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9892 break;
8dcea932
L		 9893
9894 case OPTION_MSHARED:
9895 shared = 1;
9896 break;
99ad8390 9897#endif
321098a5 9898#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9899 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9900 case OPTION_64:
9901 {
9902 const char **list, **l;
9903
3e73aa7c
JH		 9904 list = bfd_target_list ();
9905 for (l = list; *l != NULL; l++)
8620418b 9906 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9907 || strcmp (*l, "coff-x86-64") == 0
9908 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9909 || strcmp (*l, "pei-x86-64") == 0
9910 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9911 {
9912 default_arch = "x86_64";
9913 break;
9914 }
3e73aa7c 9915 if (*l == NULL)
2b5d6a91 9916 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9917 free (list);
9918 }
9919 break;
9920#endif
252b5132 9921
351f65ca 9922#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9923 case OPTION_X32:
351f65ca
L		 9924 if (IS_ELF)
9925 {
9926 const char **list, **l;
9927
9928 list = bfd_target_list ();
9929 for (l = list; *l != NULL; l++)
9930 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9931 {
9932 default_arch = "x86_64:32";
9933 break;
9934 }
9935 if (*l == NULL)
2b5d6a91 9936 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9937 free (list);
9938 }
9939 else
9940 as_fatal (_("32bit x86_64 is only supported for ELF"));
9941 break;
9942#endif
9943
6e0b89ee
AM		 9944 case OPTION_32:
9945 default_arch = "i386";
9946 break;
9947
b3b91714
AM		 9948 case OPTION_DIVIDE:
9949#ifdef SVR4_COMMENT_CHARS
9950 {
9951 char *n, *t;
9952 const char *s;
9953
add39d23 9954 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 9955 t = n;
9956 for (s = i386_comment_chars; *s != '\0'; s++)
9957 if (*s != '/')
9958 *t++ = *s;
9959 *t = '\0';
9960 i386_comment_chars = n;
9961 }
9962#endif
9963 break;
9964
9103f4f4 9965 case OPTION_MARCH:
293f5f65
L		 9966 saved = xstrdup (arg);
9967 arch = saved;
9968 /* Allow -march=+nosse. */
9969 if (*arch == '+')
9970 arch++;
6305a203 9971 do
9103f4f4 9972 {
6305a203 9973 if (*arch == '.')
2b5d6a91 9974 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9975 next = strchr (arch, '+');
9976 if (next)
9977 *next++ = '\0';
91d6fa6a 9978 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9979 {
91d6fa6a 9980 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9981 {
6305a203 9982 /* Processor. */
1ded5609
JB		 9983 if (! cpu_arch[j].flags.bitfield.cpui386)
9984 continue;
9985
91d6fa6a 9986 cpu_arch_name = cpu_arch[j].name;
6305a203 9987 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9988 cpu_arch_flags = cpu_arch[j].flags;
9989 cpu_arch_isa = cpu_arch[j].type;
9990 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9991 if (!cpu_arch_tune_set)
9992 {
9993 cpu_arch_tune = cpu_arch_isa;
9994 cpu_arch_tune_flags = cpu_arch_isa_flags;
9995 }
9996 break;
9997 }
91d6fa6a
NC		 9998 else if (*cpu_arch [j].name == '.'
9999 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 10000 {
10001 /* ISA entension. */
10002 i386_cpu_flags flags;
309d3373 10003
293f5f65
L		 10004 flags = cpu_flags_or (cpu_arch_flags,
10005 cpu_arch[j].flags);
81486035 10006
5b64d091 10007 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10008 {
10009 if (cpu_sub_arch_name)
10010 {
10011 char *name = cpu_sub_arch_name;
10012 cpu_sub_arch_name = concat (name,
91d6fa6a 10013 cpu_arch[j].name,
1bf57e9f 10014 (const char *) NULL);
6305a203
L		 10015 free (name);
10016 }
10017 else
91d6fa6a 10018 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10019 cpu_arch_flags = flags;
a586129e 10020 cpu_arch_isa_flags = flags;
6305a203
L		 10021 }
10022 break;
ccc9c027 10023 }
9103f4f4 10024 }
6305a203 10025
293f5f65
L		 10026 if (j >= ARRAY_SIZE (cpu_arch))
10027 {
10028 /* Disable an ISA entension. */
10029 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10030 if (strcmp (arch, cpu_noarch [j].name) == 0)
10031 {
10032 i386_cpu_flags flags;
10033
10034 flags = cpu_flags_and_not (cpu_arch_flags,
10035 cpu_noarch[j].flags);
10036 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10037 {
10038 if (cpu_sub_arch_name)
10039 {
10040 char *name = cpu_sub_arch_name;
10041 cpu_sub_arch_name = concat (arch,
10042 (const char *) NULL);
10043 free (name);
10044 }
10045 else
10046 cpu_sub_arch_name = xstrdup (arch);
10047 cpu_arch_flags = flags;
10048 cpu_arch_isa_flags = flags;
10049 }
10050 break;
10051 }
10052
10053 if (j >= ARRAY_SIZE (cpu_noarch))
10054 j = ARRAY_SIZE (cpu_arch);
10055 }
10056
91d6fa6a 10057 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10058 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10059
10060 arch = next;
9103f4f4 10061 }
293f5f65
L		 10062 while (next != NULL);
10063 free (saved);
9103f4f4
L		 10064 break;
10065
10066 case OPTION_MTUNE:
10067 if (*arg == '.')
2b5d6a91 10068 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10069 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10070 {
91d6fa6a 10071 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10072 {
ccc9c027 10073 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10074 cpu_arch_tune = cpu_arch [j].type;
10075 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10076 break;
10077 }
10078 }
91d6fa6a 10079 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10080 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10081 break;
10082
1efbbeb4
L		 10083 case OPTION_MMNEMONIC:
10084 if (strcasecmp (arg, "att") == 0)
10085 intel_mnemonic = 0;
10086 else if (strcasecmp (arg, "intel") == 0)
10087 intel_mnemonic = 1;
10088 else
2b5d6a91 10089 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10090 break;
10091
10092 case OPTION_MSYNTAX:
10093 if (strcasecmp (arg, "att") == 0)
10094 intel_syntax = 0;
10095 else if (strcasecmp (arg, "intel") == 0)
10096 intel_syntax = 1;
10097 else
2b5d6a91 10098 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10099 break;
10100
10101 case OPTION_MINDEX_REG:
10102 allow_index_reg = 1;
10103 break;
10104
10105 case OPTION_MNAKED_REG:
10106 allow_naked_reg = 1;
10107 break;
10108
10109 case OPTION_MOLD_GCC:
10110 old_gcc = 1;
1efbbeb4
L		 10111 break;
10112
c0f3af97
L		 10113 case OPTION_MSSE2AVX:
10114 sse2avx = 1;
10115 break;
10116
daf50ae7
L		 10117 case OPTION_MSSE_CHECK:
10118 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10119 sse_check = check_error;
daf50ae7 10120 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10121 sse_check = check_warning;
daf50ae7 10122 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10123 sse_check = check_none;
daf50ae7 10124 else
2b5d6a91 10125 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10126 break;
10127
7bab8ab5
JB		 10128 case OPTION_MOPERAND_CHECK:
10129 if (strcasecmp (arg, "error") == 0)
10130 operand_check = check_error;
10131 else if (strcasecmp (arg, "warning") == 0)
10132 operand_check = check_warning;
10133 else if (strcasecmp (arg, "none") == 0)
10134 operand_check = check_none;
10135 else
10136 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10137 break;
10138
539f890d
L		 10139 case OPTION_MAVXSCALAR:
10140 if (strcasecmp (arg, "128") == 0)
10141 avxscalar = vex128;
10142 else if (strcasecmp (arg, "256") == 0)
10143 avxscalar = vex256;
10144 else
2b5d6a91 10145 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10146 break;
10147
7e8b059b
L		 10148 case OPTION_MADD_BND_PREFIX:
10149 add_bnd_prefix = 1;
10150 break;
10151
43234a1e
L		 10152 case OPTION_MEVEXLIG:
10153 if (strcmp (arg, "128") == 0)
10154 evexlig = evexl128;
10155 else if (strcmp (arg, "256") == 0)
10156 evexlig = evexl256;
10157 else if (strcmp (arg, "512") == 0)
10158 evexlig = evexl512;
10159 else
10160 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10161 break;
10162
d3d3c6db
IT		 10163 case OPTION_MEVEXRCIG:
10164 if (strcmp (arg, "rne") == 0)
10165 evexrcig = rne;
10166 else if (strcmp (arg, "rd") == 0)
10167 evexrcig = rd;
10168 else if (strcmp (arg, "ru") == 0)
10169 evexrcig = ru;
10170 else if (strcmp (arg, "rz") == 0)
10171 evexrcig = rz;
10172 else
10173 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10174 break;
10175
43234a1e
L		 10176 case OPTION_MEVEXWIG:
10177 if (strcmp (arg, "0") == 0)
10178 evexwig = evexw0;
10179 else if (strcmp (arg, "1") == 0)
10180 evexwig = evexw1;
10181 else
10182 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10183 break;
10184
167ad85b
TG		 10185# if defined (TE_PE) || defined (TE_PEP)
10186 case OPTION_MBIG_OBJ:
10187 use_big_obj = 1;
10188 break;
10189#endif
10190
d1982f93 10191 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10192 if (strcasecmp (arg, "yes") == 0)
10193 omit_lock_prefix = 1;
10194 else if (strcasecmp (arg, "no") == 0)
10195 omit_lock_prefix = 0;
10196 else
10197 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10198 break;
10199
e4e00185
AS		 10200 case OPTION_MFENCE_AS_LOCK_ADD:
10201 if (strcasecmp (arg, "yes") == 0)
10202 avoid_fence = 1;
10203 else if (strcasecmp (arg, "no") == 0)
10204 avoid_fence = 0;
10205 else
10206 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10207 break;
10208
0cb4071e
L		 10209 case OPTION_MRELAX_RELOCATIONS:
10210 if (strcasecmp (arg, "yes") == 0)
10211 generate_relax_relocations = 1;
10212 else if (strcasecmp (arg, "no") == 0)
10213 generate_relax_relocations = 0;
10214 else
10215 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10216 break;
10217
5db04b09 10218 case OPTION_MAMD64:
e89c5eaa 10219 intel64 = 0;
5db04b09
L		 10220 break;
10221
10222 case OPTION_MINTEL64:
e89c5eaa 10223 intel64 = 1;
5db04b09
L		 10224 break;
10225
252b5132
RH		 10226 default:
10227 return 0;
10228 }
10229 return 1;
10230}
10231
8a2c8fef
L		 10232#define MESSAGE_TEMPLATE \
10233" "
10234
293f5f65
L		 10235static char *
10236output_message (FILE *stream, char *p, char *message, char *start,
10237 int *left_p, const char *name, int len)
10238{
10239 int size = sizeof (MESSAGE_TEMPLATE);
10240 int left = *left_p;
10241
10242 /* Reserve 2 spaces for ", " or ",\0" */
10243 left -= len + 2;
10244
10245 /* Check if there is any room. */
10246 if (left >= 0)
10247 {
10248 if (p != start)
10249 {
10250 *p++ = ',';
10251 *p++ = ' ';
10252 }
10253 p = mempcpy (p, name, len);
10254 }
10255 else
10256 {
10257 /* Output the current message now and start a new one. */
10258 *p++ = ',';
10259 *p = '\0';
10260 fprintf (stream, "%s\n", message);
10261 p = start;
10262 left = size - (start - message) - len - 2;
10263
10264 gas_assert (left >= 0);
10265
10266 p = mempcpy (p, name, len);
10267 }
10268
10269 *left_p = left;
10270 return p;
10271}
10272
8a2c8fef 10273static void
1ded5609 10274show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10275{
10276 static char message[] = MESSAGE_TEMPLATE;
10277 char *start = message + 27;
10278 char *p;
10279 int size = sizeof (MESSAGE_TEMPLATE);
10280 int left;
10281 const char *name;
10282 int len;
10283 unsigned int j;
10284
10285 p = start;
10286 left = size - (start - message);
10287 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10288 {
10289 /* Should it be skipped? */
10290 if (cpu_arch [j].skip)
10291 continue;
10292
10293 name = cpu_arch [j].name;
10294 len = cpu_arch [j].len;
10295 if (*name == '.')
10296 {
10297 /* It is an extension. Skip if we aren't asked to show it. */
10298 if (ext)
10299 {
10300 name++;
10301 len--;
10302 }
10303 else
10304 continue;
10305 }
10306 else if (ext)
10307 {
10308 /* It is an processor. Skip if we show only extension. */
10309 continue;
10310 }
1ded5609
JB		 10311 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10312 {
10313 /* It is an impossible processor - skip. */
10314 continue;
10315 }
8a2c8fef 10316
293f5f65 10317 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10318 }
10319
293f5f65
L		 10320 /* Display disabled extensions. */
10321 if (ext)
10322 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10323 {
10324 name = cpu_noarch [j].name;
10325 len = cpu_noarch [j].len;
10326 p = output_message (stream, p, message, start, &left, name,
10327 len);
10328 }
10329
8a2c8fef
L		 10330 *p = '\0';
10331 fprintf (stream, "%s\n", message);
10332}
10333
252b5132 10334void
8a2c8fef 10335md_show_usage (FILE *stream)
252b5132 10336{
4cc782b5
ILT		 10337#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10338 fprintf (stream, _("\
a38cf1db
AM		 10339 -Q ignored\n\
10340 -V print assembler version number\n\
b3b91714
AM		 10341 -k ignored\n"));
10342#endif
10343 fprintf (stream, _("\
12b55ccc 10344 -n Do not optimize code alignment\n\
b3b91714
AM		 10345 -q quieten some warnings\n"));
10346#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10347 fprintf (stream, _("\
a38cf1db 10348 -s ignored\n"));
b3b91714 10349#endif
321098a5
L		 10350#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10351 || defined (TE_PE) || defined (TE_PEP))
751d281c 10352 fprintf (stream, _("\
570561f7 10353 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10354#endif
b3b91714
AM		 10355#ifdef SVR4_COMMENT_CHARS
10356 fprintf (stream, _("\
10357 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10358#else
10359 fprintf (stream, _("\
b3b91714 10360 --divide ignored\n"));
4cc782b5 10361#endif
9103f4f4 10362 fprintf (stream, _("\
6305a203 10363 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10364 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10365 show_arch (stream, 0, 1);
8a2c8fef
L		 10366 fprintf (stream, _("\
10367 EXTENSION is combination of:\n"));
1ded5609 10368 show_arch (stream, 1, 0);
6305a203 10369 fprintf (stream, _("\
8a2c8fef 10370 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10371 show_arch (stream, 0, 0);
ba104c83 10372 fprintf (stream, _("\
c0f3af97
L		 10373 -msse2avx encode SSE instructions with VEX prefix\n"));
10374 fprintf (stream, _("\
daf50ae7
L		 10375 -msse-check=[none|error|warning]\n\
10376 check SSE instructions\n"));
10377 fprintf (stream, _("\
7bab8ab5
JB		 10378 -moperand-check=[none|error|warning]\n\
10379 check operand combinations for validity\n"));
10380 fprintf (stream, _("\
539f890d
L		 10381 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10382 length\n"));
10383 fprintf (stream, _("\
43234a1e
L		 10384 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10385 length\n"));
10386 fprintf (stream, _("\
10387 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10388 for EVEX.W bit ignored instructions\n"));
10389 fprintf (stream, _("\
d3d3c6db
IT		 10390 -mevexrcig=[rne|rd|ru|rz]\n\
10391 encode EVEX instructions with specific EVEX.RC value\n\
10392 for SAE-only ignored instructions\n"));
10393 fprintf (stream, _("\
ba104c83
L		 10394 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10395 fprintf (stream, _("\
10396 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10397 fprintf (stream, _("\
10398 -mindex-reg support pseudo index registers\n"));
10399 fprintf (stream, _("\
10400 -mnaked-reg don't require `%%' prefix for registers\n"));
10401 fprintf (stream, _("\
10402 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10403 fprintf (stream, _("\
10404 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10405 fprintf (stream, _("\
10406 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10407# if defined (TE_PE) || defined (TE_PEP)
10408 fprintf (stream, _("\
10409 -mbig-obj generate big object files\n"));
10410#endif
d022bddd
IT		 10411 fprintf (stream, _("\
10412 -momit-lock-prefix=[no|yes]\n\
10413 strip all lock prefixes\n"));
5db04b09 10414 fprintf (stream, _("\
e4e00185
AS		 10415 -mfence-as-lock-add=[no|yes]\n\
10416 encode lfence, mfence and sfence as\n\
10417 lock addl $0x0, (%%{re}sp)\n"));
10418 fprintf (stream, _("\
0cb4071e
L		 10419 -mrelax-relocations=[no|yes]\n\
10420 generate relax relocations\n"));
10421 fprintf (stream, _("\
5db04b09
L		 10422 -mamd64 accept only AMD64 ISA\n"));
10423 fprintf (stream, _("\
10424 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10425}
10426
3e73aa7c 10427#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10428 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10429 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10430
10431/* Pick the target format to use. */
10432
47926f60 10433const char *
e3bb37b5 10434i386_target_format (void)
252b5132 10435{
351f65ca
L		 10436 if (!strncmp (default_arch, "x86_64", 6))
10437 {
10438 update_code_flag (CODE_64BIT, 1);
10439 if (default_arch[6] == '\0')
7f56bc95 10440 x86_elf_abi = X86_64_ABI;
351f65ca 10441 else
7f56bc95 10442 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10443 }
3e73aa7c 10444 else if (!strcmp (default_arch, "i386"))
78f12dd3 10445 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10446 else if (!strcmp (default_arch, "iamcu"))
10447 {
10448 update_code_flag (CODE_32BIT, 1);
10449 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10450 {
10451 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10452 cpu_arch_name = "iamcu";
10453 cpu_sub_arch_name = NULL;
10454 cpu_arch_flags = iamcu_flags;
10455 cpu_arch_isa = PROCESSOR_IAMCU;
10456 cpu_arch_isa_flags = iamcu_flags;
10457 if (!cpu_arch_tune_set)
10458 {
10459 cpu_arch_tune = cpu_arch_isa;
10460 cpu_arch_tune_flags = cpu_arch_isa_flags;
10461 }
10462 }
8d471ec1 10463 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10464 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10465 cpu_arch_name);
10466 }
3e73aa7c 10467 else
2b5d6a91 10468 as_fatal (_("unknown architecture"));
89507696
JB		 10469
10470 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10471 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10472 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10473 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10474
252b5132
RH		 10475 switch (OUTPUT_FLAVOR)
10476 {
9384f2ff 10477#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10478 case bfd_target_aout_flavour:
47926f60 10479 return AOUT_TARGET_FORMAT;
4c63da97 10480#endif
9384f2ff
AM		 10481#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10482# if defined (TE_PE) || defined (TE_PEP)
10483 case bfd_target_coff_flavour:
167ad85b
TG		 10484 if (flag_code == CODE_64BIT)
10485 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10486 else
10487 return "pe-i386";
9384f2ff 10488# elif defined (TE_GO32)
0561d57c
JK		 10489 case bfd_target_coff_flavour:
10490 return "coff-go32";
9384f2ff 10491# else
252b5132
RH		 10492 case bfd_target_coff_flavour:
10493 return "coff-i386";
9384f2ff 10494# endif
4c63da97 10495#endif
3e73aa7c 10496#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10497 case bfd_target_elf_flavour:
3e73aa7c 10498 {
351f65ca
L		 10499 const char *format;
10500
10501 switch (x86_elf_abi)
4fa24527 10502 {
351f65ca
L		 10503 default:
10504 format = ELF_TARGET_FORMAT;
10505 break;
7f56bc95 10506 case X86_64_ABI:
351f65ca 10507 use_rela_relocations = 1;
4fa24527 10508 object_64bit = 1;
351f65ca
L		 10509 format = ELF_TARGET_FORMAT64;
10510 break;
7f56bc95 10511 case X86_64_X32_ABI:
4fa24527 10512 use_rela_relocations = 1;
351f65ca 10513 object_64bit = 1;
862be3fb 10514 disallow_64bit_reloc = 1;
351f65ca
L		 10515 format = ELF_TARGET_FORMAT32;
10516 break;
4fa24527 10517 }
3632d14b 10518 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10519 {
7f56bc95 10520 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10521 as_fatal (_("Intel L1OM is 64bit only"));
10522 return ELF_TARGET_L1OM_FORMAT;
10523 }
b49f93f6 10524 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10525 {
10526 if (x86_elf_abi != X86_64_ABI)
10527 as_fatal (_("Intel K1OM is 64bit only"));
10528 return ELF_TARGET_K1OM_FORMAT;
10529 }
81486035
L		 10530 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10531 {
10532 if (x86_elf_abi != I386_ABI)
10533 as_fatal (_("Intel MCU is 32bit only"));
10534 return ELF_TARGET_IAMCU_FORMAT;
10535 }
8a9036a4 10536 else
351f65ca 10537 return format;
3e73aa7c 10538 }
e57f8c65
TG		 10539#endif
10540#if defined (OBJ_MACH_O)
10541 case bfd_target_mach_o_flavour:
d382c579
TG		 10542 if (flag_code == CODE_64BIT)
10543 {
10544 use_rela_relocations = 1;
10545 object_64bit = 1;
10546 return "mach-o-x86-64";
10547 }
10548 else
10549 return "mach-o-i386";
4c63da97 10550#endif
252b5132
RH		 10551 default:
10552 abort ();
10553 return NULL;
10554 }
10555}
10556
47926f60 10557#endif /* OBJ_MAYBE_ more than one */
252b5132 10558\f
252b5132 10559symbolS *
7016a5d5 10560md_undefined_symbol (char *name)
252b5132 10561{
18dc2407
ILT		 10562 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10563 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10564 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10565 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10566 {
10567 if (!GOT_symbol)
10568 {
10569 if (symbol_find (name))
10570 as_bad (_("GOT already in symbol table"));
10571 GOT_symbol = symbol_new (name, undefined_section,
10572 (valueT) 0, &zero_address_frag);
10573 };
10574 return GOT_symbol;
10575 }
252b5132
RH		 10576 return 0;
10577}
10578
10579/* Round up a section size to the appropriate boundary. */
47926f60 10580
252b5132 10581valueT
7016a5d5 10582md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10583{
4c63da97
AM		 10584#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10585 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10586 {
10587 /* For a.out, force the section size to be aligned. If we don't do
10588 this, BFD will align it for us, but it will not write out the
10589 final bytes of the section. This may be a bug in BFD, but it is
10590 easier to fix it here since that is how the other a.out targets
10591 work. */
10592 int align;
10593
10594 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10595 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10596 }
252b5132
RH		 10597#endif
10598
10599 return size;
10600}
10601
10602/* On the i386, PC-relative offsets are relative to the start of the
10603 next instruction. That is, the address of the offset, plus its
10604 size, since the offset is always the last part of the insn. */
10605
10606long
e3bb37b5 10607md_pcrel_from (fixS *fixP)
252b5132
RH		 10608{
10609 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10610}
10611
10612#ifndef I386COFF
10613
10614static void
e3bb37b5 10615s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10616{
29b0f896 10617 int temp;
252b5132 10618
8a75718c
JB		 10619#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10620 if (IS_ELF)
10621 obj_elf_section_change_hook ();
10622#endif
252b5132
RH		 10623 temp = get_absolute_expression ();
10624 subseg_set (bss_section, (subsegT) temp);
10625 demand_empty_rest_of_line ();
10626}
10627
10628#endif
10629
252b5132 10630void
e3bb37b5 10631i386_validate_fix (fixS *fixp)
252b5132 10632{
02a86693 10633 if (fixp->fx_subsy)
252b5132 10634 {
02a86693 10635 if (fixp->fx_subsy == GOT_symbol)
23df1078 10636 {
02a86693
L		 10637 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10638 {
10639 if (!object_64bit)
10640 abort ();
10641#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10642 if (fixp->fx_tcbit2)
56ceb5b5
L		 10643 fixp->fx_r_type = (fixp->fx_tcbit
10644 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10645 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10646 else
10647#endif
10648 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10649 }
d6ab8113 10650 else
02a86693
L		 10651 {
10652 if (!object_64bit)
10653 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10654 else
10655 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10656 }
10657 fixp->fx_subsy = 0;
23df1078 10658 }
252b5132 10659 }
02a86693
L		 10660#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10661 else if (!object_64bit)
10662 {
10663 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10664 && fixp->fx_tcbit2)
10665 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10666 }
10667#endif
252b5132
RH		 10668}
10669
252b5132 10670arelent *
7016a5d5 10671tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10672{
10673 arelent *rel;
10674 bfd_reloc_code_real_type code;
10675
10676 switch (fixp->fx_r_type)
10677 {
8ce3d284 10678#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10679 case BFD_RELOC_SIZE32:
10680 case BFD_RELOC_SIZE64:
10681 if (S_IS_DEFINED (fixp->fx_addsy)
10682 && !S_IS_EXTERNAL (fixp->fx_addsy))
10683 {
10684 /* Resolve size relocation against local symbol to size of
10685 the symbol plus addend. */
10686 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10687 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10688 && !fits_in_unsigned_long (value))
10689 as_bad_where (fixp->fx_file, fixp->fx_line,
10690 _("symbol size computation overflow"));
10691 fixp->fx_addsy = NULL;
10692 fixp->fx_subsy = NULL;
10693 md_apply_fix (fixp, (valueT *) &value, NULL);
10694 return NULL;
10695 }
8ce3d284 10696#endif
8fd4256d 10697
3e73aa7c
JH		 10698 case BFD_RELOC_X86_64_PLT32:
10699 case BFD_RELOC_X86_64_GOT32:
10700 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10701 case BFD_RELOC_X86_64_GOTPCRELX:
10702 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10703 case BFD_RELOC_386_PLT32:
10704 case BFD_RELOC_386_GOT32:
02a86693 10705 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10706 case BFD_RELOC_386_GOTOFF:
10707 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10708 case BFD_RELOC_386_TLS_GD:
10709 case BFD_RELOC_386_TLS_LDM:
10710 case BFD_RELOC_386_TLS_LDO_32:
10711 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10712 case BFD_RELOC_386_TLS_IE:
10713 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10714 case BFD_RELOC_386_TLS_LE_32:
10715 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10716 case BFD_RELOC_386_TLS_GOTDESC:
10717 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10718 case BFD_RELOC_X86_64_TLSGD:
10719 case BFD_RELOC_X86_64_TLSLD:
10720 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10721 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10722 case BFD_RELOC_X86_64_GOTTPOFF:
10723 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10724 case BFD_RELOC_X86_64_TPOFF64:
10725 case BFD_RELOC_X86_64_GOTOFF64:
10726 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10727 case BFD_RELOC_X86_64_GOT64:
10728 case BFD_RELOC_X86_64_GOTPCREL64:
10729 case BFD_RELOC_X86_64_GOTPC64:
10730 case BFD_RELOC_X86_64_GOTPLT64:
10731 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10732 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10733 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10734 case BFD_RELOC_RVA:
10735 case BFD_RELOC_VTABLE_ENTRY:
10736 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10737#ifdef TE_PE
10738 case BFD_RELOC_32_SECREL:
10739#endif
252b5132
RH		 10740 code = fixp->fx_r_type;
10741 break;
dbbaec26
L		 10742 case BFD_RELOC_X86_64_32S:
10743 if (!fixp->fx_pcrel)
10744 {
10745 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10746 code = fixp->fx_r_type;
10747 break;
10748 }
252b5132 10749 default:
93382f6d 10750 if (fixp->fx_pcrel)
252b5132 10751 {
93382f6d
AM		 10752 switch (fixp->fx_size)
10753 {
10754 default:
b091f402
AM		 10755 as_bad_where (fixp->fx_file, fixp->fx_line,
10756 _("can not do %d byte pc-relative relocation"),
10757 fixp->fx_size);
93382f6d
AM		 10758 code = BFD_RELOC_32_PCREL;
10759 break;
10760 case 1: code = BFD_RELOC_8_PCREL; break;
10761 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10762 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10763#ifdef BFD64
10764 case 8: code = BFD_RELOC_64_PCREL; break;
10765#endif
93382f6d
AM		 10766 }
10767 }
10768 else
10769 {
10770 switch (fixp->fx_size)
10771 {
10772 default:
b091f402
AM		 10773 as_bad_where (fixp->fx_file, fixp->fx_line,
10774 _("can not do %d byte relocation"),
10775 fixp->fx_size);
93382f6d
AM		 10776 code = BFD_RELOC_32;
10777 break;
10778 case 1: code = BFD_RELOC_8; break;
10779 case 2: code = BFD_RELOC_16; break;
10780 case 4: code = BFD_RELOC_32; break;
937149dd 10781#ifdef BFD64
3e73aa7c 10782 case 8: code = BFD_RELOC_64; break;
937149dd 10783#endif
93382f6d 10784 }
252b5132
RH		 10785 }
10786 break;
10787 }
252b5132 10788
d182319b
JB		 10789 if ((code == BFD_RELOC_32
10790 || code == BFD_RELOC_32_PCREL
10791 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10792 && GOT_symbol
10793 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10794 {
4fa24527 10795 if (!object_64bit)
d6ab8113
JB		 10796 code = BFD_RELOC_386_GOTPC;
10797 else
10798 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10799 }
7b81dfbb
AJ		 10800 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10801 && GOT_symbol
10802 && fixp->fx_addsy == GOT_symbol)
10803 {
10804 code = BFD_RELOC_X86_64_GOTPC64;
10805 }
252b5132 10806
add39d23
TS		 10807 rel = XNEW (arelent);
10808 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10809 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10810
10811 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10812
3e73aa7c
JH		 10813 if (!use_rela_relocations)
10814 {
10815 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10816 vtable entry to be used in the relocation's section offset. */
10817 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10818 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10819#if defined (OBJ_COFF) && defined (TE_PE)
10820 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10821 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10822 else
10823#endif
c6682705 10824 rel->addend = 0;
3e73aa7c
JH		 10825 }
10826 /* Use the rela in 64bit mode. */
252b5132 10827 else
3e73aa7c 10828 {
862be3fb
L		 10829 if (disallow_64bit_reloc)
10830 switch (code)
10831 {
862be3fb
L		 10832 case BFD_RELOC_X86_64_DTPOFF64:
10833 case BFD_RELOC_X86_64_TPOFF64:
10834 case BFD_RELOC_64_PCREL:
10835 case BFD_RELOC_X86_64_GOTOFF64:
10836 case BFD_RELOC_X86_64_GOT64:
10837 case BFD_RELOC_X86_64_GOTPCREL64:
10838 case BFD_RELOC_X86_64_GOTPC64:
10839 case BFD_RELOC_X86_64_GOTPLT64:
10840 case BFD_RELOC_X86_64_PLTOFF64:
10841 as_bad_where (fixp->fx_file, fixp->fx_line,
10842 _("cannot represent relocation type %s in x32 mode"),
10843 bfd_get_reloc_code_name (code));
10844 break;
10845 default:
10846 break;
10847 }
10848
062cd5e7
AS		 10849 if (!fixp->fx_pcrel)
10850 rel->addend = fixp->fx_offset;
10851 else
10852 switch (code)
10853 {
10854 case BFD_RELOC_X86_64_PLT32:
10855 case BFD_RELOC_X86_64_GOT32:
10856 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10857 case BFD_RELOC_X86_64_GOTPCRELX:
10858 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10859 case BFD_RELOC_X86_64_TLSGD:
10860 case BFD_RELOC_X86_64_TLSLD:
10861 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10862 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10863 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10864 rel->addend = fixp->fx_offset - fixp->fx_size;
10865 break;
10866 default:
10867 rel->addend = (section->vma
10868 - fixp->fx_size
10869 + fixp->fx_addnumber
10870 + md_pcrel_from (fixp));
10871 break;
10872 }
3e73aa7c
JH		 10873 }
10874
252b5132
RH		 10875 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10876 if (rel->howto == NULL)
10877 {
10878 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10879 _("cannot represent relocation type %s"),
252b5132
RH		 10880 bfd_get_reloc_code_name (code));
10881 /* Set howto to a garbage value so that we can keep going. */
10882 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10883 gas_assert (rel->howto != NULL);
252b5132
RH		 10884 }
10885
10886 return rel;
10887}
10888
ee86248c 10889#include "tc-i386-intel.c"
54cfded0 10890
a60de03c
JB		 10891void
10892tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10893{
a60de03c
JB		 10894 int saved_naked_reg;
10895 char saved_register_dot;
54cfded0 10896
a60de03c
JB		 10897 saved_naked_reg = allow_naked_reg;
10898 allow_naked_reg = 1;
10899 saved_register_dot = register_chars['.'];
10900 register_chars['.'] = '.';
10901 allow_pseudo_reg = 1;
10902 expression_and_evaluate (exp);
10903 allow_pseudo_reg = 0;
10904 register_chars['.'] = saved_register_dot;
10905 allow_naked_reg = saved_naked_reg;
10906
e96d56a1 10907 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10908 {
a60de03c
JB		 10909 if ((addressT) exp->X_add_number < i386_regtab_size)
10910 {
10911 exp->X_op = O_constant;
10912 exp->X_add_number = i386_regtab[exp->X_add_number]
10913 .dw2_regnum[flag_code >> 1];
10914 }
10915 else
10916 exp->X_op = O_illegal;
54cfded0 10917 }
54cfded0
AM		 10918}
10919
10920void
10921tc_x86_frame_initial_instructions (void)
10922{
a60de03c
JB		 10923 static unsigned int sp_regno[2];
10924
10925 if (!sp_regno[flag_code >> 1])
10926 {
10927 char *saved_input = input_line_pointer;
10928 char sp[][4] = {"esp", "rsp"};
10929 expressionS exp;
a4447b93 10930
a60de03c
JB		 10931 input_line_pointer = sp[flag_code >> 1];
10932 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10933 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10934 sp_regno[flag_code >> 1] = exp.X_add_number;
10935 input_line_pointer = saved_input;
10936 }
a4447b93 10937
61ff971f
L		 10938 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10939 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10940}
d2b2c203 10941
d7921315
L		 10942int
10943x86_dwarf2_addr_size (void)
10944{
10945#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10946 if (x86_elf_abi == X86_64_X32_ABI)
10947 return 4;
10948#endif
10949 return bfd_arch_bits_per_address (stdoutput) / 8;
10950}
10951
d2b2c203
DJ		 10952int
10953i386_elf_section_type (const char *str, size_t len)
10954{
10955 if (flag_code == CODE_64BIT
10956 && len == sizeof ("unwind") - 1
10957 && strncmp (str, "unwind", 6) == 0)
10958 return SHT_X86_64_UNWIND;
10959
10960 return -1;
10961}
bb41ade5 10962
ad5fec3b
EB		 10963#ifdef TE_SOLARIS
10964void
10965i386_solaris_fix_up_eh_frame (segT sec)
10966{
10967 if (flag_code == CODE_64BIT)
10968 elf_section_type (sec) = SHT_X86_64_UNWIND;
10969}
10970#endif
10971
bb41ade5
AM		 10972#ifdef TE_PE
10973void
10974tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10975{
91d6fa6a 10976 expressionS exp;
bb41ade5 10977
91d6fa6a
NC		 10978 exp.X_op = O_secrel;
10979 exp.X_add_symbol = symbol;
10980 exp.X_add_number = 0;
10981 emit_expr (&exp, size);
bb41ade5
AM		 10982}
10983#endif
3b22753a
L		 10984
10985#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10986/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10987
01e1a5bc 10988bfd_vma
6d4af3c2 10989x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 10990{
10991 if (flag_code == CODE_64BIT)
10992 {
10993 if (letter == 'l')
10994 return SHF_X86_64_LARGE;
10995
8f3bae45 10996 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10997 }
3b22753a 10998 else
8f3bae45 10999 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11000 return -1;
11001}
11002
01e1a5bc 11003bfd_vma
3b22753a
L		 11004x86_64_section_word (char *str, size_t len)
11005{
8620418b 11006 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11007 return SHF_X86_64_LARGE;
11008
11009 return -1;
11010}
11011
11012static void
11013handle_large_common (int small ATTRIBUTE_UNUSED)
11014{
11015 if (flag_code != CODE_64BIT)
11016 {
11017 s_comm_internal (0, elf_common_parse);
11018 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11019 }
11020 else
11021 {
11022 static segT lbss_section;
11023 asection *saved_com_section_ptr = elf_com_section_ptr;
11024 asection *saved_bss_section = bss_section;
11025
11026 if (lbss_section == NULL)
11027 {
11028 flagword applicable;
11029 segT seg = now_seg;
11030 subsegT subseg = now_subseg;
11031
11032 /* The .lbss section is for local .largecomm symbols. */
11033 lbss_section = subseg_new (".lbss", 0);
11034 applicable = bfd_applicable_section_flags (stdoutput);
11035 bfd_set_section_flags (stdoutput, lbss_section,
11036 applicable & SEC_ALLOC);
11037 seg_info (lbss_section)->bss = 1;
11038
11039 subseg_set (seg, subseg);
11040 }
11041
11042 elf_com_section_ptr = &_bfd_elf_large_com_section;
11043 bss_section = lbss_section;
11044
11045 s_comm_internal (0, elf_common_parse);
11046
11047 elf_com_section_ptr = saved_com_section_ptr;
11048 bss_section = saved_bss_section;
11049 }
11050}
11051#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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