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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
4c63da97 2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
252b5132
RH
3 Free Software Foundation.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22/*
23 Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better.
27 */
28
29#include <ctype.h>
30
31#include "as.h"
32#include "subsegs.h"
33#include "opcode/i386.h"
34
35#ifndef TC_RELOC
36#define TC_RELOC(X,Y) (Y)
37#endif
38
39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM
45#endif
46
252b5132
RH
47#ifndef SCALE1_WHEN_NO_INDEX
48/* Specifying a scale factor besides 1 when there is no index is
49 futile. eg. `mov (%ebx,2),%al' does exactly the same as
50 `mov (%ebx),%al'. To slavishly follow what the programmer
51 specified, set SCALE1_WHEN_NO_INDEX to 0. */
52#define SCALE1_WHEN_NO_INDEX 1
53#endif
54
55#define true 1
56#define false 0
57
58static unsigned int mode_from_disp_size PARAMS ((unsigned int));
59static int fits_in_signed_byte PARAMS ((long));
60static int fits_in_unsigned_byte PARAMS ((long));
61static int fits_in_unsigned_word PARAMS ((long));
62static int fits_in_signed_word PARAMS ((long));
63static int smallest_imm_type PARAMS ((long));
64static int add_prefix PARAMS ((unsigned int));
65static void set_16bit_code_flag PARAMS ((int));
eecb386c 66static void set_16bit_gcc_code_flag PARAMS((int));
252b5132
RH
67static void set_intel_syntax PARAMS ((int));
68
69#ifdef BFD_ASSEMBLER
70static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, bfd_reloc_code_real_type));
72#endif
73
74/* 'md_assemble ()' gathers together information and puts it into a
75 i386_insn. */
76
77struct _i386_insn
78 {
79 /* TM holds the template for the insn were currently assembling. */
80 template tm;
81
82 /* SUFFIX holds the instruction mnemonic suffix if given.
83 (e.g. 'l' for 'movl') */
84 char suffix;
85
86 /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */
87
88 /* OPERANDS gives the number of given operands. */
89 unsigned int operands;
90
91 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
92 of given register, displacement, memory operands and immediate
93 operands. */
94 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
95
96 /* TYPES [i] is the type (see above #defines) which tells us how to
97 search through DISPS [i] & IMMS [i] & REGS [i] for the required
98 operand. */
99 unsigned int types[MAX_OPERANDS];
100
101 /* Displacements (if given) for each operand. */
102 expressionS *disps[MAX_OPERANDS];
103
104 /* Relocation type for operand */
105#ifdef BFD_ASSEMBLER
106 enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS];
107#else
108 int disp_reloc[MAX_OPERANDS];
109#endif
110
111 /* Immediate operands (if given) for each operand. */
112 expressionS *imms[MAX_OPERANDS];
113
114 /* Register operands (if given) for each operand. */
115 const reg_entry *regs[MAX_OPERANDS];
116
117 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
118 the base index byte below. */
119 const reg_entry *base_reg;
120 const reg_entry *index_reg;
121 unsigned int log2_scale_factor;
122
123 /* SEG gives the seg_entries of this insn. They are zero unless
124 explicit segment overrides are given. */
125 const seg_entry *seg[2]; /* segments for memory operands (if given) */
126
127 /* PREFIX holds all the given prefix opcodes (usually null).
128 PREFIXES is the number of prefix opcodes. */
129 unsigned int prefixes;
130 unsigned char prefix[MAX_PREFIXES];
131
132 /* RM and SIB are the modrm byte and the sib byte where the
133 addressing modes of this insn are encoded. */
134
135 modrm_byte rm;
136 sib_byte sib;
137 };
138
139typedef struct _i386_insn i386_insn;
140
141/* List of chars besides those in app.c:symbol_chars that can start an
142 operand. Used to prevent the scrubber eating vital white-space. */
143#ifdef LEX_AT
144const char extra_symbol_chars[] = "*%-(@";
145#else
146const char extra_symbol_chars[] = "*%-(";
147#endif
148
149/* This array holds the chars that always start a comment. If the
150 pre-processor is disabled, these aren't very useful */
151#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX))
152/* Putting '/' here makes it impossible to use the divide operator.
153 However, we need it for compatibility with SVR4 systems. */
154const char comment_chars[] = "#/";
155#define PREFIX_SEPARATOR '\\'
156#else
157const char comment_chars[] = "#";
158#define PREFIX_SEPARATOR '/'
159#endif
160
161/* This array holds the chars that only start a comment at the beginning of
162 a line. If the line seems to have the form '# 123 filename'
163 .line and .file directives will appear in the pre-processed output */
164/* Note that input_file.c hand checks for '#' at the beginning of the
165 first line of the input file. This is because the compiler outputs
166 #NO_APP at the beginning of its output. */
167/* Also note that comments started like this one will always work if
168 '/' isn't otherwise defined. */
169#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX))
170const char line_comment_chars[] = "";
171#else
172const char line_comment_chars[] = "/";
173#endif
174
175const char line_separator_chars[] = "";
176
177/* Chars that can be used to separate mant from exp in floating point nums */
178const char EXP_CHARS[] = "eE";
179
180/* Chars that mean this number is a floating point constant */
181/* As in 0f12.456 */
182/* or 0d1.2345e12 */
183const char FLT_CHARS[] = "fFdDxX";
184
185/* tables for lexical analysis */
186static char mnemonic_chars[256];
187static char register_chars[256];
188static char operand_chars[256];
189static char identifier_chars[256];
190static char digit_chars[256];
191
192/* lexical macros */
193#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
194#define is_operand_char(x) (operand_chars[(unsigned char) x])
195#define is_register_char(x) (register_chars[(unsigned char) x])
196#define is_space_char(x) ((x) == ' ')
197#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
198#define is_digit_char(x) (digit_chars[(unsigned char) x])
199
200/* put here all non-digit non-letter charcters that may occur in an operand */
201static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
202
203/* md_assemble() always leaves the strings it's passed unaltered. To
204 effect this we maintain a stack of saved characters that we've smashed
205 with '\0's (indicating end of strings for various sub-fields of the
206 assembler instruction). */
207static char save_stack[32];
208static char *save_stack_p; /* stack pointer */
209#define END_STRING_AND_SAVE(s) \
210 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
211#define RESTORE_END_STRING(s) \
212 do { *(s) = *--save_stack_p; } while (0)
213
214/* The instruction we're assembling. */
215static i386_insn i;
216
217/* Possible templates for current insn. */
218static const templates *current_templates;
219
220/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
221static expressionS disp_expressions[2], im_expressions[2];
222
223static int this_operand; /* current operand we are working on */
224
225static int flag_do_long_jump; /* FIXME what does this do? */
226
227static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */
228
229static int intel_syntax = 0; /* 1 for intel syntax, 0 if att syntax */
230
231static int allow_naked_reg = 0; /* 1 if register prefix % not required */
232
eecb386c
AM
233static char stackop_size = '\0'; /* Used in 16 bit gcc mode to add an l
234 suffix to call, ret, enter, leave, push,
add0c677
AM
235 and pop instructions so that gcc has the
236 same stack frame as in 32 bit mode. */
eecb386c 237
252b5132
RH
238/* Interface to relax_segment.
239 There are 2 relax states for 386 jump insns: one for conditional &
a217f122
AM
240 one for unconditional jumps. This is because these two types of
241 jumps add different sizes to frags when we're figuring out what
252b5132
RH
242 sort of jump to choose to reach a given label. */
243
244/* types */
245#define COND_JUMP 1 /* conditional jump */
246#define UNCOND_JUMP 2 /* unconditional jump */
247/* sizes */
248#define CODE16 1
249#define SMALL 0
250#define SMALL16 (SMALL|CODE16)
251#define BIG 2
252#define BIG16 (BIG|CODE16)
253
254#ifndef INLINE
255#ifdef __GNUC__
256#define INLINE __inline__
257#else
258#define INLINE
259#endif
260#endif
261
262#define ENCODE_RELAX_STATE(type,size) \
263 ((relax_substateT)((type<<2) | (size)))
264#define SIZE_FROM_RELAX_STATE(s) \
265 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
266
267/* This table is used by relax_frag to promote short jumps to long
268 ones where necessary. SMALL (short) jumps may be promoted to BIG
269 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
270 don't allow a short jump in a 32 bit code segment to be promoted to
271 a 16 bit offset jump because it's slower (requires data size
272 prefix), and doesn't work, unless the destination is in the bottom
273 64k of the code segment (The top 16 bits of eip are zeroed). */
274
275const relax_typeS md_relax_table[] =
276{
24eab124
AM
277 /* The fields are:
278 1) most positive reach of this state,
279 2) most negative reach of this state,
280 3) how many bytes this mode will add to the size of the current frag
281 4) which index into the table to try if we can't fit into this one.
282 */
252b5132
RH
283 {1, 1, 0, 0},
284 {1, 1, 0, 0},
285 {1, 1, 0, 0},
286 {1, 1, 0, 0},
287
288 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
289 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
290 /* dword conditionals adds 4 bytes to frag:
291 1 extra opcode byte, 3 extra displacement bytes. */
292 {0, 0, 4, 0},
293 /* word conditionals add 2 bytes to frag:
294 1 extra opcode byte, 1 extra displacement byte. */
295 {0, 0, 2, 0},
296
297 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
298 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
299 /* dword jmp adds 3 bytes to frag:
300 0 extra opcode bytes, 3 extra displacement bytes. */
301 {0, 0, 3, 0},
302 /* word jmp adds 1 byte to frag:
303 0 extra opcode bytes, 1 extra displacement byte. */
304 {0, 0, 1, 0}
305
306};
307
308
309void
310i386_align_code (fragP, count)
311 fragS *fragP;
312 int count;
313{
314 /* Various efficient no-op patterns for aligning code labels. */
315 /* Note: Don't try to assemble the instructions in the comments. */
316 /* 0L and 0w are not legal */
317 static const char f32_1[] =
318 {0x90}; /* nop */
319 static const char f32_2[] =
320 {0x89,0xf6}; /* movl %esi,%esi */
321 static const char f32_3[] =
322 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
323 static const char f32_4[] =
324 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
325 static const char f32_5[] =
326 {0x90, /* nop */
327 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
328 static const char f32_6[] =
329 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
330 static const char f32_7[] =
331 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
332 static const char f32_8[] =
333 {0x90, /* nop */
334 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
335 static const char f32_9[] =
336 {0x89,0xf6, /* movl %esi,%esi */
337 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
338 static const char f32_10[] =
339 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
340 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
341 static const char f32_11[] =
342 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
343 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
344 static const char f32_12[] =
345 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
346 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
347 static const char f32_13[] =
348 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
349 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
350 static const char f32_14[] =
351 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
352 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
353 static const char f32_15[] =
354 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
355 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM
356 static const char f16_3[] =
357 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH
358 static const char f16_4[] =
359 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
360 static const char f16_5[] =
361 {0x90, /* nop */
362 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
363 static const char f16_6[] =
364 {0x89,0xf6, /* mov %si,%si */
365 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
366 static const char f16_7[] =
367 {0x8d,0x74,0x00, /* lea 0(%si),%si */
368 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
369 static const char f16_8[] =
370 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
371 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
372 static const char *const f32_patt[] = {
373 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
374 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
375 };
376 static const char *const f16_patt[] = {
c3332e24 377 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH
378 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
379 };
380
381 if (count > 0 && count <= 15)
382 {
383 if (flag_16bit_code)
384 {
385 memcpy(fragP->fr_literal + fragP->fr_fix,
386 f16_patt[count - 1], count);
387 if (count > 8) /* adjust jump offset */
388 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
389 }
390 else
391 memcpy(fragP->fr_literal + fragP->fr_fix,
392 f32_patt[count - 1], count);
393 fragP->fr_var = count;
394 }
395}
396
397static char *output_invalid PARAMS ((int c));
398static int i386_operand PARAMS ((char *operand_string));
399static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
400static const reg_entry *parse_register PARAMS ((char *reg_string,
401 char **end_op));
402
403#ifndef I386COFF
404static void s_bss PARAMS ((int));
405#endif
406
407symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
408
409static INLINE unsigned int
410mode_from_disp_size (t)
411 unsigned int t;
412{
413 return (t & Disp8) ? 1 : (t & (Disp16|Disp32)) ? 2 : 0;
414}
415
416static INLINE int
417fits_in_signed_byte (num)
418 long num;
419{
420 return (num >= -128) && (num <= 127);
421} /* fits_in_signed_byte() */
422
423static INLINE int
424fits_in_unsigned_byte (num)
425 long num;
426{
427 return (num & 0xff) == num;
428} /* fits_in_unsigned_byte() */
429
430static INLINE int
431fits_in_unsigned_word (num)
432 long num;
433{
434 return (num & 0xffff) == num;
435} /* fits_in_unsigned_word() */
436
437static INLINE int
438fits_in_signed_word (num)
439 long num;
440{
441 return (-32768 <= num) && (num <= 32767);
442} /* fits_in_signed_word() */
443
444static int
445smallest_imm_type (num)
446 long num;
447{
448#if 0
449 /* This code is disabled because all the Imm1 forms in the opcode table
450 are slower on the i486, and they're the versions with the implicitly
451 specified single-position displacement, which has another syntax if
452 you really want to use that form. If you really prefer to have the
453 one-byte-shorter Imm1 form despite these problems, re-enable this
454 code. */
455 if (num == 1)
456 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32;
457#endif
458 return (fits_in_signed_byte (num)
459 ? (Imm8S | Imm8 | Imm16 | Imm32)
460 : fits_in_unsigned_byte (num)
461 ? (Imm8 | Imm16 | Imm32)
462 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
463 ? (Imm16 | Imm32)
464 : (Imm32));
465} /* smallest_imm_type() */
466
467/* Returns 0 if attempting to add a prefix where one from the same
468 class already exists, 1 if non rep/repne added, 2 if rep/repne
469 added. */
470static int
471add_prefix (prefix)
472 unsigned int prefix;
473{
474 int ret = 1;
475 int q;
476
477 switch (prefix)
478 {
479 default:
480 abort ();
481
482 case CS_PREFIX_OPCODE:
483 case DS_PREFIX_OPCODE:
484 case ES_PREFIX_OPCODE:
485 case FS_PREFIX_OPCODE:
486 case GS_PREFIX_OPCODE:
487 case SS_PREFIX_OPCODE:
488 q = SEG_PREFIX;
489 break;
490
491 case REPNE_PREFIX_OPCODE:
492 case REPE_PREFIX_OPCODE:
493 ret = 2;
494 /* fall thru */
495 case LOCK_PREFIX_OPCODE:
496 q = LOCKREP_PREFIX;
497 break;
498
499 case FWAIT_OPCODE:
500 q = WAIT_PREFIX;
501 break;
502
503 case ADDR_PREFIX_OPCODE:
504 q = ADDR_PREFIX;
505 break;
506
507 case DATA_PREFIX_OPCODE:
508 q = DATA_PREFIX;
509 break;
510 }
511
512 if (i.prefix[q])
513 {
514 as_bad (_("same type of prefix used twice"));
515 return 0;
516 }
517
518 i.prefixes += 1;
519 i.prefix[q] = prefix;
520 return ret;
521}
522
523static void
524set_16bit_code_flag (new_16bit_code_flag)
eecb386c
AM
525 int new_16bit_code_flag;
526{
527 flag_16bit_code = new_16bit_code_flag;
528 stackop_size = '\0';
529}
530
531static void
532set_16bit_gcc_code_flag (new_16bit_code_flag)
533 int new_16bit_code_flag;
252b5132
RH
534{
535 flag_16bit_code = new_16bit_code_flag;
eecb386c 536 stackop_size = new_16bit_code_flag ? 'l' : '\0';
252b5132
RH
537}
538
539static void
540set_intel_syntax (syntax_flag)
eecb386c 541 int syntax_flag;
252b5132
RH
542{
543 /* Find out if register prefixing is specified. */
544 int ask_naked_reg = 0;
545
546 SKIP_WHITESPACE ();
547 if (! is_end_of_line[(unsigned char) *input_line_pointer])
548 {
549 char *string = input_line_pointer;
550 int e = get_symbol_end ();
551
552 if (strcmp(string, "prefix") == 0)
553 ask_naked_reg = 1;
554 else if (strcmp(string, "noprefix") == 0)
555 ask_naked_reg = -1;
556 else
557 as_bad (_("Bad argument to syntax directive."));
558 *input_line_pointer = e;
559 }
560 demand_empty_rest_of_line ();
c3332e24 561
252b5132
RH
562 intel_syntax = syntax_flag;
563
564 if (ask_naked_reg == 0)
565 {
566#ifdef BFD_ASSEMBLER
567 allow_naked_reg = (intel_syntax
24eab124 568 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH
569#else
570 allow_naked_reg = 0; /* conservative default */
571#endif
572 }
573 else
574 allow_naked_reg = (ask_naked_reg < 0);
575}
576
577const pseudo_typeS md_pseudo_table[] =
578{
579#ifndef I386COFF
580 {"bss", s_bss, 0},
581#endif
582#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
583 {"align", s_align_bytes, 0},
584#else
585 {"align", s_align_ptwo, 0},
586#endif
587 {"ffloat", float_cons, 'f'},
588 {"dfloat", float_cons, 'd'},
589 {"tfloat", float_cons, 'x'},
590 {"value", cons, 2},
591 {"noopt", s_ignore, 0},
592 {"optim", s_ignore, 0},
eecb386c 593 {"code16gcc", set_16bit_gcc_code_flag, 1},
252b5132
RH
594 {"code16", set_16bit_code_flag, 1},
595 {"code32", set_16bit_code_flag, 0},
596 {"intel_syntax", set_intel_syntax, 1},
597 {"att_syntax", set_intel_syntax, 0},
598 {0, 0, 0}
599};
600
601/* for interface with expression () */
602extern char *input_line_pointer;
603
604/* hash table for instruction mnemonic lookup */
605static struct hash_control *op_hash;
606/* hash table for register lookup */
607static struct hash_control *reg_hash;
608\f
609
610void
611md_begin ()
612{
613 const char *hash_err;
614
615 /* initialize op_hash hash table */
616 op_hash = hash_new ();
617
618 {
619 register const template *optab;
620 register templates *core_optab;
621
622 optab = i386_optab; /* setup for loop */
623 core_optab = (templates *) xmalloc (sizeof (templates));
624 core_optab->start = optab;
625
626 while (1)
627 {
628 ++optab;
629 if (optab->name == NULL
630 || strcmp (optab->name, (optab - 1)->name) != 0)
631 {
632 /* different name --> ship out current template list;
633 add to hash table; & begin anew */
634 core_optab->end = optab;
635 hash_err = hash_insert (op_hash,
636 (optab - 1)->name,
637 (PTR) core_optab);
638 if (hash_err)
639 {
640 hash_error:
641 as_fatal (_("Internal Error: Can't hash %s: %s"),
642 (optab - 1)->name,
643 hash_err);
644 }
645 if (optab->name == NULL)
646 break;
647 core_optab = (templates *) xmalloc (sizeof (templates));
648 core_optab->start = optab;
649 }
650 }
651 }
652
653 /* initialize reg_hash hash table */
654 reg_hash = hash_new ();
655 {
656 register const reg_entry *regtab;
657
658 for (regtab = i386_regtab;
659 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
660 regtab++)
661 {
662 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
663 if (hash_err)
664 goto hash_error;
665 }
666 }
667
668 /* fill in lexical tables: mnemonic_chars, operand_chars. */
669 {
670 register int c;
671 register char *p;
672
673 for (c = 0; c < 256; c++)
674 {
675 if (isdigit (c))
676 {
677 digit_chars[c] = c;
678 mnemonic_chars[c] = c;
679 register_chars[c] = c;
680 operand_chars[c] = c;
681 }
682 else if (islower (c))
683 {
684 mnemonic_chars[c] = c;
685 register_chars[c] = c;
686 operand_chars[c] = c;
687 }
688 else if (isupper (c))
689 {
690 mnemonic_chars[c] = tolower (c);
691 register_chars[c] = mnemonic_chars[c];
692 operand_chars[c] = c;
693 }
694
695 if (isalpha (c) || isdigit (c))
696 identifier_chars[c] = c;
697 else if (c >= 128)
698 {
699 identifier_chars[c] = c;
700 operand_chars[c] = c;
701 }
702 }
703
704#ifdef LEX_AT
705 identifier_chars['@'] = '@';
706#endif
252b5132
RH
707 digit_chars['-'] = '-';
708 identifier_chars['_'] = '_';
709 identifier_chars['.'] = '.';
710
711 for (p = operand_special_chars; *p != '\0'; p++)
712 operand_chars[(unsigned char) *p] = *p;
713 }
714
715#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
716 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
717 {
718 record_alignment (text_section, 2);
719 record_alignment (data_section, 2);
720 record_alignment (bss_section, 2);
721 }
722#endif
723}
724
725void
726i386_print_statistics (file)
727 FILE *file;
728{
729 hash_print_statistics (file, "i386 opcode", op_hash);
730 hash_print_statistics (file, "i386 register", reg_hash);
731}
732\f
733
734#ifdef DEBUG386
735
736/* debugging routines for md_assemble */
737static void pi PARAMS ((char *, i386_insn *));
738static void pte PARAMS ((template *));
739static void pt PARAMS ((unsigned int));
740static void pe PARAMS ((expressionS *));
741static void ps PARAMS ((symbolS *));
742
743static void
744pi (line, x)
745 char *line;
746 i386_insn *x;
747{
748 register template *p;
749 int i;
750
751 fprintf (stdout, "%s: template ", line);
752 pte (&x->tm);
753 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x",
754 x->rm.mode, x->rm.reg, x->rm.regmem);
755 fprintf (stdout, " base %x index %x scale %x\n",
756 x->bi.base, x->bi.index, x->bi.scale);
757 for (i = 0; i < x->operands; i++)
758 {
759 fprintf (stdout, " #%d: ", i + 1);
760 pt (x->types[i]);
761 fprintf (stdout, "\n");
762 if (x->types[i]
3f4438ab 763 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
252b5132
RH
764 fprintf (stdout, "%s\n", x->regs[i]->reg_name);
765 if (x->types[i] & Imm)
766 pe (x->imms[i]);
767 if (x->types[i] & Disp)
768 pe (x->disps[i]);
769 }
770}
771
772static void
773pte (t)
774 template *t;
775{
776 int i;
777 fprintf (stdout, " %d operands ", t->operands);
778 fprintf (stdout, "opcode %x ",
779 t->base_opcode);
780 if (t->extension_opcode != None)
781 fprintf (stdout, "ext %x ", t->extension_opcode);
782 if (t->opcode_modifier & D)
783 fprintf (stdout, "D");
784 if (t->opcode_modifier & W)
785 fprintf (stdout, "W");
786 fprintf (stdout, "\n");
787 for (i = 0; i < t->operands; i++)
788 {
789 fprintf (stdout, " #%d type ", i + 1);
790 pt (t->operand_types[i]);
791 fprintf (stdout, "\n");
792 }
793}
794
795static void
796pe (e)
797 expressionS *e;
798{
24eab124 799 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM
800 fprintf (stdout, " add_number %ld (%lx)\n",
801 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH
802 if (e->X_add_symbol)
803 {
804 fprintf (stdout, " add_symbol ");
805 ps (e->X_add_symbol);
806 fprintf (stdout, "\n");
807 }
808 if (e->X_op_symbol)
809 {
810 fprintf (stdout, " op_symbol ");
811 ps (e->X_op_symbol);
812 fprintf (stdout, "\n");
813 }
814}
815
816static void
817ps (s)
818 symbolS *s;
819{
820 fprintf (stdout, "%s type %s%s",
821 S_GET_NAME (s),
822 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
823 segment_name (S_GET_SEGMENT (s)));
824}
825
826struct type_name
827 {
828 unsigned int mask;
829 char *tname;
830 }
831
832type_names[] =
833{
834 { Reg8, "r8" },
835 { Reg16, "r16" },
836 { Reg32, "r32" },
837 { Imm8, "i8" },
838 { Imm8S, "i8s" },
839 { Imm16, "i16" },
840 { Imm32, "i32" },
841 { Imm1, "i1" },
842 { BaseIndex, "BaseIndex" },
843 { Disp8, "d8" },
844 { Disp16, "d16" },
845 { Disp32, "d32" },
846 { InOutPortReg, "InOutPortReg" },
847 { ShiftCount, "ShiftCount" },
848 { Control, "control reg" },
849 { Test, "test reg" },
850 { Debug, "debug reg" },
851 { FloatReg, "FReg" },
852 { FloatAcc, "FAcc" },
853 { SReg2, "SReg2" },
854 { SReg3, "SReg3" },
855 { Acc, "Acc" },
856 { JumpAbsolute, "Jump Absolute" },
857 { RegMMX, "rMMX" },
3f4438ab 858 { RegXMM, "rXMM" },
252b5132
RH
859 { EsSeg, "es" },
860 { 0, "" }
861};
862
863static void
864pt (t)
865 unsigned int t;
866{
867 register struct type_name *ty;
868
869 if (t == Unknown)
870 {
871 fprintf (stdout, _("Unknown"));
872 }
873 else
874 {
875 for (ty = type_names; ty->mask; ty++)
876 if (t & ty->mask)
877 fprintf (stdout, "%s, ", ty->tname);
878 }
879 fflush (stdout);
880}
881
882#endif /* DEBUG386 */
883\f
884int
885tc_i386_force_relocation (fixp)
886 struct fix *fixp;
887{
888#ifdef BFD_ASSEMBLER
889 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
890 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
891 return 1;
892 return 0;
893#else
894 /* For COFF */
895 return fixp->fx_r_type==7;
896#endif
897}
898
899#ifdef BFD_ASSEMBLER
900static bfd_reloc_code_real_type reloc
901 PARAMS ((int, int, bfd_reloc_code_real_type));
902
903static bfd_reloc_code_real_type
904reloc (size, pcrel, other)
905 int size;
906 int pcrel;
907 bfd_reloc_code_real_type other;
908{
909 if (other != NO_RELOC) return other;
910
911 if (pcrel)
912 {
913 switch (size)
914 {
915 case 1: return BFD_RELOC_8_PCREL;
916 case 2: return BFD_RELOC_16_PCREL;
917 case 4: return BFD_RELOC_32_PCREL;
918 }
919 as_bad (_("Can not do %d byte pc-relative relocation"), size);
920 }
921 else
922 {
923 switch (size)
924 {
925 case 1: return BFD_RELOC_8;
926 case 2: return BFD_RELOC_16;
927 case 4: return BFD_RELOC_32;
928 }
929 as_bad (_("Can not do %d byte relocation"), size);
930 }
931
932 return BFD_RELOC_NONE;
933}
934
935/*
936 * Here we decide which fixups can be adjusted to make them relative to
937 * the beginning of the section instead of the symbol. Basically we need
938 * to make sure that the dynamic relocations are done correctly, so in
939 * some cases we force the original symbol to be used.
940 */
941int
c0c949c7
ILT
942tc_i386_fix_adjustable (fixP)
943 fixS *fixP;
252b5132 944{
79d292aa
ILT
945#if defined (OBJ_ELF) || defined (TE_PE)
946 /* Prevent all adjustments to global symbols, or else dynamic
947 linking will not work correctly. */
252b5132
RH
948 if (S_IS_EXTERN (fixP->fx_addsy))
949 return 0;
950 if (S_IS_WEAK (fixP->fx_addsy))
951 return 0;
952#endif
953 /* adjust_reloc_syms doesn't know about the GOT */
954 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
955 || fixP->fx_r_type == BFD_RELOC_386_PLT32
956 || fixP->fx_r_type == BFD_RELOC_386_GOT32
d33e1d24 957 || fixP->fx_r_type == BFD_RELOC_RVA
252b5132
RH
958 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
959 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
960 return 0;
961 return 1;
962}
963#else
964#define reloc(SIZE,PCREL,OTHER) 0
965#define BFD_RELOC_16 0
966#define BFD_RELOC_32 0
967#define BFD_RELOC_16_PCREL 0
968#define BFD_RELOC_32_PCREL 0
969#define BFD_RELOC_386_PLT32 0
970#define BFD_RELOC_386_GOT32 0
971#define BFD_RELOC_386_GOTOFF 0
972#endif
973
b4cac588
AM
974static int
975intel_float_operand PARAMS ((char *mnemonic));
976
977static int
252b5132
RH
978intel_float_operand (mnemonic)
979 char *mnemonic;
980{
981 if (mnemonic[0] == 'f' && mnemonic[1] =='i')
982 return 0;
983
984 if (mnemonic[0] == 'f')
985 return 1;
986
987 return 0;
988}
989
990/* This is the guts of the machine-dependent assembler. LINE points to a
991 machine dependent instruction. This function is supposed to emit
992 the frags/bytes it assembles to. */
993
994void
995md_assemble (line)
996 char *line;
997{
998 /* Points to template once we've found it. */
999 const template *t;
1000
1001 /* Count the size of the instruction generated. */
1002 int insn_size = 0;
1003
1004 int j;
1005
1006 char mnemonic[MAX_MNEM_SIZE];
1007
1008 /* Initialize globals. */
1009 memset (&i, '\0', sizeof (i));
1010 for (j = 0; j < MAX_OPERANDS; j++)
1011 i.disp_reloc[j] = NO_RELOC;
1012 memset (disp_expressions, '\0', sizeof (disp_expressions));
1013 memset (im_expressions, '\0', sizeof (im_expressions));
1014 save_stack_p = save_stack; /* reset stack pointer */
1015
1016 /* First parse an instruction mnemonic & call i386_operand for the operands.
1017 We assume that the scrubber has arranged it so that line[0] is the valid
1018 start of a (possibly prefixed) mnemonic. */
1019 {
1020 char *l = line;
1021 char *token_start = l;
1022 char *mnem_p;
1023
1024 /* Non-zero if we found a prefix only acceptable with string insns. */
1025 const char *expecting_string_instruction = NULL;
1026
1027 while (1)
1028 {
1029 mnem_p = mnemonic;
1030 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1031 {
1032 mnem_p++;
1033 if (mnem_p >= mnemonic + sizeof (mnemonic))
1034 {
1035 as_bad (_("no such 386 instruction: `%s'"), token_start);
1036 return;
1037 }
1038 l++;
1039 }
1040 if (!is_space_char (*l)
1041 && *l != END_OF_INSN
1042 && *l != PREFIX_SEPARATOR)
1043 {
1044 as_bad (_("invalid character %s in mnemonic"),
1045 output_invalid (*l));
1046 return;
1047 }
1048 if (token_start == l)
1049 {
1050 if (*l == PREFIX_SEPARATOR)
1051 as_bad (_("expecting prefix; got nothing"));
1052 else
1053 as_bad (_("expecting mnemonic; got nothing"));
1054 return;
1055 }
1056
1057 /* Look up instruction (or prefix) via hash table. */
1058 current_templates = hash_find (op_hash, mnemonic);
1059
1060 if (*l != END_OF_INSN
1061 && (! is_space_char (*l) || l[1] != END_OF_INSN)
1062 && current_templates
1063 && (current_templates->start->opcode_modifier & IsPrefix))
1064 {
1065 /* If we are in 16-bit mode, do not allow addr16 or data16.
1066 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1067 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1068 && (((current_templates->start->opcode_modifier & Size32) != 0)
1069 ^ flag_16bit_code))
1070 {
1071 as_bad (_("redundant %s prefix"),
1072 current_templates->start->name);
1073 return;
1074 }
1075 /* Add prefix, checking for repeated prefixes. */
1076 switch (add_prefix (current_templates->start->base_opcode))
1077 {
1078 case 0:
1079 return;
1080 case 2:
1081 expecting_string_instruction =
1082 current_templates->start->name;
1083 break;
1084 }
1085 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1086 token_start = ++l;
1087 }
1088 else
1089 break;
1090 }
1091
1092 if (!current_templates)
1093 {
24eab124 1094 /* See if we can get a match by trimming off a suffix. */
252b5132
RH
1095 switch (mnem_p[-1])
1096 {
252b5132
RH
1097 case WORD_MNEM_SUFFIX:
1098 case BYTE_MNEM_SUFFIX:
1099 case SHORT_MNEM_SUFFIX:
252b5132 1100 case LONG_MNEM_SUFFIX:
252b5132
RH
1101 i.suffix = mnem_p[-1];
1102 mnem_p[-1] = '\0';
1103 current_templates = hash_find (op_hash, mnemonic);
24eab124
AM
1104 break;
1105
1106 /* Intel Syntax */
add0c677 1107 case DWORD_MNEM_SUFFIX:
24eab124
AM
1108 if (intel_syntax)
1109 {
1110 i.suffix = mnem_p[-1];
1111 mnem_p[-1] = '\0';
1112 current_templates = hash_find (op_hash, mnemonic);
1113 break;
1114 }
252b5132
RH
1115 }
1116 if (!current_templates)
1117 {
1118 as_bad (_("no such 386 instruction: `%s'"), token_start);
1119 return;
1120 }
1121 }
1122
1123 /* check for rep/repne without a string instruction */
1124 if (expecting_string_instruction
1125 && !(current_templates->start->opcode_modifier & IsString))
1126 {
1127 as_bad (_("expecting string instruction after `%s'"),
1128 expecting_string_instruction);
1129 return;
1130 }
1131
1132 /* There may be operands to parse. */
1133 if (*l != END_OF_INSN)
1134 {
1135 /* parse operands */
1136
1137 /* 1 if operand is pending after ','. */
1138 unsigned int expecting_operand = 0;
1139
1140 /* Non-zero if operand parens not balanced. */
1141 unsigned int paren_not_balanced;
1142
1143 do
1144 {
1145 /* skip optional white space before operand */
1146 if (is_space_char (*l))
1147 ++l;
1148 if (!is_operand_char (*l) && *l != END_OF_INSN)
1149 {
1150 as_bad (_("invalid character %s before operand %d"),
1151 output_invalid (*l),
1152 i.operands + 1);
1153 return;
1154 }
1155 token_start = l; /* after white space */
1156 paren_not_balanced = 0;
1157 while (paren_not_balanced || *l != ',')
1158 {
1159 if (*l == END_OF_INSN)
1160 {
1161 if (paren_not_balanced)
1162 {
24eab124 1163 if (!intel_syntax)
252b5132
RH
1164 as_bad (_("unbalanced parenthesis in operand %d."),
1165 i.operands + 1);
24eab124 1166 else
252b5132
RH
1167 as_bad (_("unbalanced brackets in operand %d."),
1168 i.operands + 1);
1169 return;
1170 }
1171 else
1172 break; /* we are done */
1173 }
1174 else if (!is_operand_char (*l) && !is_space_char (*l))
1175 {
1176 as_bad (_("invalid character %s in operand %d"),
1177 output_invalid (*l),
1178 i.operands + 1);
1179 return;
1180 }
24eab124
AM
1181 if (!intel_syntax)
1182 {
252b5132
RH
1183 if (*l == '(')
1184 ++paren_not_balanced;
1185 if (*l == ')')
1186 --paren_not_balanced;
24eab124
AM
1187 }
1188 else
1189 {
252b5132
RH
1190 if (*l == '[')
1191 ++paren_not_balanced;
1192 if (*l == ']')
1193 --paren_not_balanced;
24eab124 1194 }
252b5132
RH
1195 l++;
1196 }
1197 if (l != token_start)
1198 { /* yes, we've read in another operand */
1199 unsigned int operand_ok;
1200 this_operand = i.operands++;
1201 if (i.operands > MAX_OPERANDS)
1202 {
1203 as_bad (_("spurious operands; (%d operands/instruction max)"),
1204 MAX_OPERANDS);
1205 return;
1206 }
1207 /* now parse operand adding info to 'i' as we go along */
1208 END_STRING_AND_SAVE (l);
1209
24eab124
AM
1210 if (intel_syntax)
1211 operand_ok = i386_intel_operand (token_start, intel_float_operand (mnemonic));
1212 else
1213 operand_ok = i386_operand (token_start);
252b5132
RH
1214
1215 RESTORE_END_STRING (l); /* restore old contents */
1216 if (!operand_ok)
1217 return;
1218 }
1219 else
1220 {
1221 if (expecting_operand)
1222 {
1223 expecting_operand_after_comma:
1224 as_bad (_("expecting operand after ','; got nothing"));
1225 return;
1226 }
1227 if (*l == ',')
1228 {
1229 as_bad (_("expecting operand before ','; got nothing"));
1230 return;
1231 }
1232 }
1233
1234 /* now *l must be either ',' or END_OF_INSN */
1235 if (*l == ',')
1236 {
1237 if (*++l == END_OF_INSN)
1238 { /* just skip it, if it's \n complain */
1239 goto expecting_operand_after_comma;
1240 }
1241 expecting_operand = 1;
1242 }
1243 }
1244 while (*l != END_OF_INSN); /* until we get end of insn */
1245 }
1246 }
1247
1248 /* Now we've parsed the mnemonic into a set of templates, and have the
1249 operands at hand.
1250
1251 Next, we find a template that matches the given insn,
1252 making sure the overlap of the given operands types is consistent
1253 with the template operand types. */
1254
1255#define MATCH(overlap, given, template) \
3138f287
AM
1256 ((overlap & ~JumpAbsolute) \
1257 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
252b5132
RH
1258
1259 /* If given types r0 and r1 are registers they must be of the same type
1260 unless the expected operand type register overlap is null.
1261 Note that Acc in a template matches every size of reg. */
1262#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1263 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1264 ((g0) & Reg) == ((g1) & Reg) || \
1265 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1266
1267 {
1268 register unsigned int overlap0, overlap1;
252b5132
RH
1269 unsigned int overlap2;
1270 unsigned int found_reverse_match;
1271 int suffix_check;
1272
1273 /* All intel opcodes have reversed operands except for BOUND and ENTER */
1274 if (intel_syntax
24eab124
AM
1275 && (strcmp (mnemonic, "enter") != 0)
1276 && (strcmp (mnemonic, "bound") != 0)
1277 && (strncmp (mnemonic, "fsub", 4) !=0)
1278 && (strncmp (mnemonic, "fdiv", 4) !=0))
252b5132 1279 {
24eab124
AM
1280 const reg_entry *temp_reg = NULL;
1281 expressionS *temp_disp = NULL;
1282 expressionS *temp_imm = NULL;
1283 unsigned int temp_type;
1284 int xchg1 = 0;
ab9da554 1285 int xchg2 = 0;
252b5132 1286
24eab124
AM
1287 if (i.operands == 2)
1288 {
1289 xchg1 = 0;
1290 xchg2 = 1;
1291 }
1292 else if (i.operands == 3)
1293 {
1294 xchg1 = 0;
1295 xchg2 = 2;
1296 }
1297
1298 if (i.operands > 1)
1299 {
1300 temp_type = i.types[xchg2];
1301 if (temp_type & (Reg | FloatReg))
1302 temp_reg = i.regs[xchg2];
1303 else if (temp_type & Imm)
1304 temp_imm = i.imms[xchg2];
1305 else if (temp_type & Disp)
1306 temp_disp = i.disps[xchg2];
1307
1308 i.types[xchg2] = i.types[xchg1];
1309
1310 if (i.types[xchg1] & (Reg | FloatReg))
1311 {
1312 i.regs[xchg2] = i.regs[xchg1];
1313 i.regs[xchg1] = NULL;
1314 }
1315 else if (i.types[xchg2] & Imm)
1316 {
1317 i.imms[xchg2] = i.imms[xchg1];
1318 i.imms[xchg1] = NULL;
1319 }
1320 else if (i.types[xchg2] & Disp)
1321 {
1322 i.disps[xchg2] = i.disps[xchg1];
1323 i.disps[xchg1] = NULL;
1324 }
1325
1326 if (temp_type & (Reg | FloatReg))
1327 {
1328 i.regs[xchg1] = temp_reg;
1329 if (! (i.types[xchg1] & (Reg | FloatReg)))
1330 i.regs[xchg2] = NULL;
1331 }
1332 else if (temp_type & Imm)
1333 {
1334 i.imms[xchg1] = temp_imm;
1335 if (! (i.types[xchg1] & Imm))
1336 i.imms[xchg2] = NULL;
1337 }
1338 else if (temp_type & Disp)
1339 {
1340 i.disps[xchg1] = temp_disp;
1341 if (! (i.types[xchg1] & Disp))
1342 i.disps[xchg2] = NULL;
1343 }
1344
1345 i.types[xchg1] = temp_type;
1346 }
24eab124 1347 }
252b5132
RH
1348 overlap0 = 0;
1349 overlap1 = 0;
1350 overlap2 = 0;
1351 found_reverse_match = 0;
1352 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1353 ? No_bSuf
1354 : (i.suffix == WORD_MNEM_SUFFIX
1355 ? No_wSuf
1356 : (i.suffix == SHORT_MNEM_SUFFIX
1357 ? No_sSuf
1358 : (i.suffix == LONG_MNEM_SUFFIX
24eab124 1359 ? No_lSuf
add0c677 1360 : (i.suffix == DWORD_MNEM_SUFFIX
24eab124
AM
1361 ? No_dSuf
1362 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
252b5132
RH
1363
1364 for (t = current_templates->start;
1365 t < current_templates->end;
1366 t++)
1367 {
1368 /* Must have right number of operands. */
1369 if (i.operands != t->operands)
1370 continue;
1371
24eab124
AM
1372 /* For some opcodes, don't check the suffix */
1373 if (intel_syntax)
1374 {
1375 if (strcmp (t->name, "fnstcw")
1376 && strcmp (t->name, "fldcw")
1377 && (t->opcode_modifier & suffix_check))
1378 continue;
1379 }
1380 /* Must not have disallowed suffix. */
1381 else if ((t->opcode_modifier & suffix_check))
1382 continue;
252b5132
RH
1383
1384 else if (!t->operands)
1385 break; /* 0 operands always matches */
1386
1387 overlap0 = i.types[0] & t->operand_types[0];
1388 switch (t->operands)
1389 {
1390 case 1:
1391 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
1392 continue;
1393 break;
1394 case 2:
1395 case 3:
1396 overlap1 = i.types[1] & t->operand_types[1];
1397 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
1398 || !MATCH (overlap1, i.types[1], t->operand_types[1])
1399 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1400 t->operand_types[0],
1401 overlap1, i.types[1],
1402 t->operand_types[1]))
1403 {
1404
1405 /* check if other direction is valid ... */
1406 if ((t->opcode_modifier & (D|FloatD)) == 0)
1407 continue;
1408
1409 /* try reversing direction of operands */
1410 overlap0 = i.types[0] & t->operand_types[1];
1411 overlap1 = i.types[1] & t->operand_types[0];
1412 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
1413 || !MATCH (overlap1, i.types[1], t->operand_types[0])
1414 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1415 t->operand_types[1],
1416 overlap1, i.types[1],
1417 t->operand_types[0]))
1418 {
1419 /* does not match either direction */
1420 continue;
1421 }
1422 /* found_reverse_match holds which of D or FloatDR
1423 we've found. */
1424 found_reverse_match = t->opcode_modifier & (D|FloatDR);
1425 break;
1426 }
1427 /* found a forward 2 operand match here */
1428 if (t->operands == 3)
1429 {
1430 /* Here we make use of the fact that there are no
1431 reverse match 3 operand instructions, and all 3
1432 operand instructions only need to be checked for
1433 register consistency between operands 2 and 3. */
1434 overlap2 = i.types[2] & t->operand_types[2];
1435 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
1436 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
1437 t->operand_types[1],
1438 overlap2, i.types[2],
24eab124 1439 t->operand_types[2]))
252b5132 1440
24eab124 1441 continue;
252b5132
RH
1442 }
1443 /* found either forward/reverse 2 or 3 operand match here:
1444 slip through to break */
1445 }
1446 break; /* we've found a match; break out of loop */
1447 } /* for (t = ... */
1448 if (t == current_templates->end)
1449 { /* we found no match */
1450 as_bad (_("suffix or operands invalid for `%s'"),
1451 current_templates->start->name);
1452 return;
1453 }
1454
3138f287
AM
1455 if (!intel_syntax
1456 && (i.types[0] & JumpAbsolute) != (t->operand_types[0] & JumpAbsolute))
1457 {
1458 as_warn (_("Indirect %s without `*'"), t->name);
1459 }
1460
252b5132
RH
1461 if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) == (IsPrefix|IgnoreSize))
1462 {
1463 /* Warn them that a data or address size prefix doesn't affect
1464 assembly of the next line of code. */
1465 as_warn (_("stand-alone `%s' prefix"), t->name);
1466 }
1467
1468 /* Copy the template we found. */
1469 i.tm = *t;
1470 if (found_reverse_match)
1471 {
1472 i.tm.operand_types[0] = t->operand_types[1];
1473 i.tm.operand_types[1] = t->operand_types[0];
1474 }
1475
1476
1477 if (i.tm.opcode_modifier & FWait)
1478 if (! add_prefix (FWAIT_OPCODE))
1479 return;
1480
1481 /* Check string instruction segment overrides */
1482 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1483 {
1484 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
1485 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
1486 {
1487 if (i.seg[0] != NULL && i.seg[0] != &es)
1488 {
1489 as_bad (_("`%s' operand %d must use `%%es' segment"),
1490 i.tm.name,
1491 mem_op + 1);
1492 return;
1493 }
1494 /* There's only ever one segment override allowed per instruction.
1495 This instruction possibly has a legal segment override on the
1496 second operand, so copy the segment to where non-string
1497 instructions store it, allowing common code. */
1498 i.seg[0] = i.seg[1];
1499 }
1500 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
1501 {
1502 if (i.seg[1] != NULL && i.seg[1] != &es)
1503 {
1504 as_bad (_("`%s' operand %d must use `%%es' segment"),
1505 i.tm.name,
1506 mem_op + 2);
1507 return;
1508 }
1509 }
1510 }
1511
1512 /* If matched instruction specifies an explicit instruction mnemonic
1513 suffix, use it. */
1514 if (i.tm.opcode_modifier & (Size16 | Size32))
1515 {
1516 if (i.tm.opcode_modifier & Size16)
1517 i.suffix = WORD_MNEM_SUFFIX;
1518 else
add0c677 1519 i.suffix = LONG_MNEM_SUFFIX;
252b5132
RH
1520 }
1521 else if (i.reg_operands)
1522 {
1523 /* If there's no instruction mnemonic suffix we try to invent one
1524 based on register operands. */
1525 if (!i.suffix)
1526 {
1527 /* We take i.suffix from the last register operand specified,
1528 Destination register type is more significant than source
1529 register type. */
1530 int op;
1531 for (op = i.operands; --op >= 0; )
1532 if (i.types[op] & Reg)
1533 {
1534 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
1535 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
add0c677 1536 LONG_MNEM_SUFFIX);
252b5132
RH
1537 break;
1538 }
1539 }
1540 else if (i.suffix == BYTE_MNEM_SUFFIX)
1541 {
1542 int op;
1543 for (op = i.operands; --op >= 0; )
1544 {
1545 /* If this is an eight bit register, it's OK. If it's
1546 the 16 or 32 bit version of an eight bit register,
1547 we will just use the low portion, and that's OK too. */
1548 if (i.types[op] & Reg8)
1549 continue;
1550
24eab124
AM
1551 /* movzx and movsx should not generate this warning. */
1552 if (intel_syntax
1553 && (i.tm.base_opcode == 0xfb7
1554 || i.tm.base_opcode == 0xfb6
1555 || i.tm.base_opcode == 0xfbe
1556 || i.tm.base_opcode == 0xfbf))
1557 continue;
252b5132
RH
1558
1559 if ((i.types[op] & WordReg) && i.regs[op]->reg_num < 4
1560#if 0
1561 /* Check that the template allows eight bit regs
1562 This kills insns such as `orb $1,%edx', which
1563 maybe should be allowed. */
1564 && (i.tm.operand_types[op] & (Reg8|InOutPortReg))
1565#endif
1566 )
1567 {
1568#if REGISTER_WARNINGS
1569 if ((i.tm.operand_types[op] & InOutPortReg) == 0)
1570 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1571 (i.regs[op] - (i.types[op] & Reg16 ? 8 : 16))->reg_name,
1572 i.regs[op]->reg_name,
1573 i.suffix);
1574#endif
1575 continue;
1576 }
1577 /* Any other register is bad */
3f4438ab
AM
1578 if (i.types[op] & (Reg | RegMMX | RegXMM
1579 | SReg2 | SReg3
1580 | Control | Debug | Test
1581 | FloatReg | FloatAcc))
252b5132
RH
1582 {
1583 as_bad (_("`%%%s' not allowed with `%s%c'"),
1584 i.regs[op]->reg_name,
1585 i.tm.name,
1586 i.suffix);
1587 return;
1588 }
1589 }
1590 }
add0c677 1591 else if (i.suffix == LONG_MNEM_SUFFIX)
252b5132
RH
1592 {
1593 int op;
1594 for (op = i.operands; --op >= 0; )
1595 /* Reject eight bit registers, except where the template
1596 requires them. (eg. movzb) */
1597 if ((i.types[op] & Reg8) != 0
1598 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
1599 {
1600 as_bad (_("`%%%s' not allowed with `%s%c'"),
1601 i.regs[op]->reg_name,
1602 i.tm.name,
1603 i.suffix);
1604 return;
1605 }
1606#if REGISTER_WARNINGS
1607 /* Warn if the e prefix on a general reg is missing. */
1608 else if ((i.types[op] & Reg16) != 0
1609 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
1610 {
1611 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1612 (i.regs[op] + 8)->reg_name,
1613 i.regs[op]->reg_name,
1614 i.suffix);
1615 }
1616#endif
1617 }
1618 else if (i.suffix == WORD_MNEM_SUFFIX)
1619 {
1620 int op;
1621 for (op = i.operands; --op >= 0; )
1622 /* Reject eight bit registers, except where the template
1623 requires them. (eg. movzb) */
1624 if ((i.types[op] & Reg8) != 0
1625 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
1626 {
1627 as_bad (_("`%%%s' not allowed with `%s%c'"),
1628 i.regs[op]->reg_name,
1629 i.tm.name,
1630 i.suffix);
1631 return;
1632 }
1633#if REGISTER_WARNINGS
1634 /* Warn if the e prefix on a general reg is present. */
1635 else if ((i.types[op] & Reg32) != 0
1636 && (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
1637 {
1638 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1639 (i.regs[op] - 8)->reg_name,
1640 i.regs[op]->reg_name,
1641 i.suffix);
1642 }
1643#endif
1644 }
1645 else
1646 abort();
1647 }
eecb386c
AM
1648 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
1649 {
1650 i.suffix = stackop_size;
1651 }
252b5132
RH
1652
1653 /* Make still unresolved immediate matches conform to size of immediate
1654 given in i.suffix. Note: overlap2 cannot be an immediate! */
1655 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32))
1656 && overlap0 != Imm8 && overlap0 != Imm8S
1657 && overlap0 != Imm16 && overlap0 != Imm32)
1658 {
1659 if (i.suffix)
1660 {
24eab124
AM
1661 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
1662 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32));
252b5132
RH
1663 }
1664 else if (overlap0 == (Imm16 | Imm32))
1665 {
24eab124 1666 overlap0 =
252b5132
RH
1667 (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32;
1668 }
1669 else
1670 {
1671 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1672 return;
1673 }
1674 }
1675 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32))
1676 && overlap1 != Imm8 && overlap1 != Imm8S
1677 && overlap1 != Imm16 && overlap1 != Imm32)
1678 {
1679 if (i.suffix)
1680 {
24eab124
AM
1681 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
1682 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32));
252b5132
RH
1683 }
1684 else if (overlap1 == (Imm16 | Imm32))
1685 {
24eab124 1686 overlap1 =
252b5132
RH
1687 (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32;
1688 }
1689 else
1690 {
1691 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1692 return;
1693 }
1694 }
1695 assert ((overlap2 & Imm) == 0);
1696
1697 i.types[0] = overlap0;
1698 if (overlap0 & ImplicitRegister)
1699 i.reg_operands--;
1700 if (overlap0 & Imm1)
1701 i.imm_operands = 0; /* kludge for shift insns */
1702
1703 i.types[1] = overlap1;
1704 if (overlap1 & ImplicitRegister)
1705 i.reg_operands--;
1706
1707 i.types[2] = overlap2;
1708 if (overlap2 & ImplicitRegister)
1709 i.reg_operands--;
1710
1711 /* Finalize opcode. First, we change the opcode based on the operand
1712 size given by i.suffix: We need not change things for byte insns. */
1713
1714 if (!i.suffix && (i.tm.opcode_modifier & W))
1715 {
1716 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1717 return;
1718 }
1719
1720 /* For movzx and movsx, need to check the register type */
1721 if (intel_syntax
24eab124 1722 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
252b5132 1723 if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
24eab124
AM
1724 {
1725 unsigned int prefix = DATA_PREFIX_OPCODE;
252b5132 1726
24eab124
AM
1727 if ((i.regs[1]->reg_type & Reg16) != 0)
1728 if (!add_prefix (prefix))
1729 return;
1730 }
252b5132
RH
1731
1732 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
1733 {
1734 /* It's not a byte, select word/dword operation. */
1735 if (i.tm.opcode_modifier & W)
1736 {
1737 if (i.tm.opcode_modifier & ShortForm)
1738 i.tm.base_opcode |= 8;
1739 else
1740 i.tm.base_opcode |= 1;
1741 }
1742 /* Now select between word & dword operations via the operand
1743 size prefix, except for instructions that will ignore this
1744 prefix anyway. */
add0c677 1745 if (((intel_syntax && (i.suffix == DWORD_MNEM_SUFFIX))
252b5132
RH
1746 || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code
1747 && !(i.tm.opcode_modifier & IgnoreSize))
1748 {
1749 unsigned int prefix = DATA_PREFIX_OPCODE;
1750 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
1751 prefix = ADDR_PREFIX_OPCODE;
1752
1753 if (! add_prefix (prefix))
1754 return;
1755 }
1756 /* Size floating point instruction. */
1757 if (i.suffix == LONG_MNEM_SUFFIX
add0c677 1758 || (intel_syntax && i.suffix == DWORD_MNEM_SUFFIX))
252b5132
RH
1759 {
1760 if (i.tm.opcode_modifier & FloatMF)
1761 i.tm.base_opcode ^= 4;
1762 }
252b5132
RH
1763 }
1764
3f4438ab 1765 if (i.tm.opcode_modifier & ImmExt)
252b5132 1766 {
3f4438ab
AM
1767 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1768 opcode suffix which is coded in the same place as an 8-bit
1769 immediate field would be. Here we fake an 8-bit immediate
1770 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132
RH
1771
1772 expressionS *exp;
1773
1774 assert(i.imm_operands == 0 && i.operands <= 2);
1775
1776 exp = &im_expressions[i.imm_operands++];
1777 i.imms[i.operands] = exp;
1778 i.types[i.operands++] = Imm8;
1779 exp->X_op = O_constant;
1780 exp->X_add_number = i.tm.extension_opcode;
1781 i.tm.extension_opcode = None;
1782 }
1783
1784 /* For insns with operands there are more diddles to do to the opcode. */
1785 if (i.operands)
1786 {
24eab124 1787 /* Default segment register this instruction will use
252b5132
RH
1788 for memory accesses. 0 means unknown.
1789 This is only for optimizing out unnecessary segment overrides. */
1790 const seg_entry *default_seg = 0;
1791
1792 /* If we found a reverse match we must alter the opcode
1793 direction bit. found_reverse_match holds bits to change
1794 (different for int & float insns). */
1795
1796 i.tm.base_opcode ^= found_reverse_match;
1797
1798 /* The imul $imm, %reg instruction is converted into
1799 imul $imm, %reg, %reg, and the clr %reg instruction
1800 is converted into xor %reg, %reg. */
1801 if (i.tm.opcode_modifier & regKludge)
1802 {
1803 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
1804 /* Pretend we saw the extra register operand. */
1805 i.regs[first_reg_op+1] = i.regs[first_reg_op];
1806 i.reg_operands = 2;
1807 }
1808
1809 if (i.tm.opcode_modifier & ShortForm)
1810 {
1811 /* The register or float register operand is in operand 0 or 1. */
1812 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
1813 /* Register goes in low 3 bits of opcode. */
1814 i.tm.base_opcode |= i.regs[op]->reg_num;
1815 if ((i.tm.opcode_modifier & Ugh) != 0)
1816 {
1817 /* Warn about some common errors, but press on regardless.
1818 The first case can be generated by gcc (<= 2.8.1). */
1819 if (i.operands == 2)
1820 {
1821 /* reversed arguments on faddp, fsubp, etc. */
1822 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
1823 i.regs[1]->reg_name,
1824 i.regs[0]->reg_name);
1825 }
1826 else
1827 {
1828 /* extraneous `l' suffix on fp insn */
1829 as_warn (_("translating to `%s %%%s'"), i.tm.name,
1830 i.regs[0]->reg_name);
1831 }
1832 }
1833 }
1834 else if (i.tm.opcode_modifier & Modrm)
1835 {
1836 /* The opcode is completed (modulo i.tm.extension_opcode which
1837 must be put into the modrm byte).
1838 Now, we make the modrm & index base bytes based on all the
1839 info we've collected. */
1840
1841 /* i.reg_operands MUST be the number of real register operands;
1842 implicit registers do not count. */
1843 if (i.reg_operands == 2)
1844 {
1845 unsigned int source, dest;
1846 source = ((i.types[0]
3f4438ab
AM
1847 & (Reg | RegMMX | RegXMM
1848 | SReg2 | SReg3
1849 | Control | Debug | Test))
252b5132
RH
1850 ? 0 : 1);
1851 dest = source + 1;
1852
252b5132 1853 i.rm.mode = 3;
3f4438ab
AM
1854 /* One of the register operands will be encoded in the
1855 i.tm.reg field, the other in the combined i.tm.mode
1856 and i.tm.regmem fields. If no form of this
1857 instruction supports a memory destination operand,
1858 then we assume the source operand may sometimes be
1859 a memory operand and so we need to store the
1860 destination in the i.rm.reg field. */
1861 if ((i.tm.operand_types[dest] & AnyMem) == 0)
252b5132
RH
1862 {
1863 i.rm.reg = i.regs[dest]->reg_num;
1864 i.rm.regmem = i.regs[source]->reg_num;
1865 }
1866 else
1867 {
1868 i.rm.reg = i.regs[source]->reg_num;
1869 i.rm.regmem = i.regs[dest]->reg_num;
1870 }
1871 }
1872 else
1873 { /* if it's not 2 reg operands... */
1874 if (i.mem_operands)
1875 {
1876 unsigned int fake_zero_displacement = 0;
1877 unsigned int op = ((i.types[0] & AnyMem)
1878 ? 0
1879 : (i.types[1] & AnyMem) ? 1 : 2);
1880
1881 default_seg = &ds;
1882
1883 if (! i.base_reg)
1884 {
1885 i.rm.mode = 0;
1886 if (! i.disp_operands)
1887 fake_zero_displacement = 1;
1888 if (! i.index_reg)
1889 {
1890 /* Operand is just <disp> */
1891 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0))
1892 {
1893 i.rm.regmem = NO_BASE_REGISTER_16;
1894 i.types[op] &= ~Disp;
1895 i.types[op] |= Disp16;
1896 }
1897 else
1898 {
1899 i.rm.regmem = NO_BASE_REGISTER;
1900 i.types[op] &= ~Disp;
1901 i.types[op] |= Disp32;
1902 }
1903 }
1904 else /* ! i.base_reg && i.index_reg */
1905 {
1906 i.sib.index = i.index_reg->reg_num;
1907 i.sib.base = NO_BASE_REGISTER;
1908 i.sib.scale = i.log2_scale_factor;
1909 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1910 i.types[op] &= ~Disp;
1911 i.types[op] |= Disp32; /* Must be 32 bit */
1912 }
1913 }
1914 else if (i.base_reg->reg_type & Reg16)
1915 {
1916 switch (i.base_reg->reg_num)
1917 {
1918 case 3: /* (%bx) */
1919 if (! i.index_reg)
1920 i.rm.regmem = 7;
1921 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
1922 i.rm.regmem = i.index_reg->reg_num - 6;
1923 break;
1924 case 5: /* (%bp) */
1925 default_seg = &ss;
1926 if (! i.index_reg)
1927 {
1928 i.rm.regmem = 6;
1929 if ((i.types[op] & Disp) == 0)
1930 {
1931 /* fake (%bp) into 0(%bp) */
1932 i.types[op] |= Disp8;
1933 fake_zero_displacement = 1;
1934 }
1935 }
1936 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
1937 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
1938 break;
1939 default: /* (%si) -> 4 or (%di) -> 5 */
1940 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
1941 }
1942 i.rm.mode = mode_from_disp_size (i.types[op]);
1943 }
1944 else /* i.base_reg and 32 bit mode */
1945 {
1946 i.rm.regmem = i.base_reg->reg_num;
1947 i.sib.base = i.base_reg->reg_num;
1948 if (i.base_reg->reg_num == EBP_REG_NUM)
1949 {
1950 default_seg = &ss;
1951 if (i.disp_operands == 0)
1952 {
1953 fake_zero_displacement = 1;
1954 i.types[op] |= Disp8;
1955 }
1956 }
1957 else if (i.base_reg->reg_num == ESP_REG_NUM)
1958 {
1959 default_seg = &ss;
1960 }
1961 i.sib.scale = i.log2_scale_factor;
1962 if (! i.index_reg)
1963 {
1964 /* <disp>(%esp) becomes two byte modrm
1965 with no index register. We've already
1966 stored the code for esp in i.rm.regmem
1967 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
1968 base register besides %esp will not use
1969 the extra modrm byte. */
1970 i.sib.index = NO_INDEX_REGISTER;
1971#if ! SCALE1_WHEN_NO_INDEX
1972 /* Another case where we force the second
1973 modrm byte. */
1974 if (i.log2_scale_factor)
1975 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1976#endif
1977 }
1978 else
1979 {
1980 i.sib.index = i.index_reg->reg_num;
1981 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1982 }
1983 i.rm.mode = mode_from_disp_size (i.types[op]);
1984 }
1985
1986 if (fake_zero_displacement)
1987 {
1988 /* Fakes a zero displacement assuming that i.types[op]
1989 holds the correct displacement size. */
b4cac588
AM
1990 expressionS *exp;
1991
252b5132
RH
1992 exp = &disp_expressions[i.disp_operands++];
1993 i.disps[op] = exp;
1994 exp->X_op = O_constant;
1995 exp->X_add_number = 0;
1996 exp->X_add_symbol = (symbolS *) 0;
1997 exp->X_op_symbol = (symbolS *) 0;
1998 }
1999 }
2000
2001 /* Fill in i.rm.reg or i.rm.regmem field with register
2002 operand (if any) based on i.tm.extension_opcode.
2003 Again, we must be careful to make sure that
2004 segment/control/debug/test/MMX registers are coded
2005 into the i.rm.reg field. */
2006 if (i.reg_operands)
2007 {
2008 unsigned int op =
2009 ((i.types[0]
3f4438ab
AM
2010 & (Reg | RegMMX | RegXMM
2011 | SReg2 | SReg3
2012 | Control | Debug | Test))
252b5132
RH
2013 ? 0
2014 : ((i.types[1]
3f4438ab
AM
2015 & (Reg | RegMMX | RegXMM
2016 | SReg2 | SReg3
2017 | Control | Debug | Test))
252b5132
RH
2018 ? 1
2019 : 2));
2020 /* If there is an extension opcode to put here, the
2021 register number must be put into the regmem field. */
2022 if (i.tm.extension_opcode != None)
2023 i.rm.regmem = i.regs[op]->reg_num;
2024 else
2025 i.rm.reg = i.regs[op]->reg_num;
2026
2027 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2028 we must set it to 3 to indicate this is a register
2029 operand in the regmem field. */
2030 if (!i.mem_operands)
2031 i.rm.mode = 3;
2032 }
2033
2034 /* Fill in i.rm.reg field with extension opcode (if any). */
2035 if (i.tm.extension_opcode != None)
2036 i.rm.reg = i.tm.extension_opcode;
2037 }
2038 }
2039 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2040 {
2041 if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
2042 {
2043 as_bad (_("you can't `pop %%cs'"));
2044 return;
2045 }
2046 i.tm.base_opcode |= (i.regs[0]->reg_num << 3);
2047 }
2048 else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32)
2049 {
2050 default_seg = &ds;
2051 }
2052 else if ((i.tm.opcode_modifier & IsString) != 0)
2053 {
2054 /* For the string instructions that allow a segment override
2055 on one of their operands, the default segment is ds. */
2056 default_seg = &ds;
2057 }
2058
2059 /* If a segment was explicitly specified,
2060 and the specified segment is not the default,
2061 use an opcode prefix to select it.
2062 If we never figured out what the default segment is,
2063 then default_seg will be zero at this point,
2064 and the specified segment prefix will always be used. */
2065 if ((i.seg[0]) && (i.seg[0] != default_seg))
2066 {
2067 if (! add_prefix (i.seg[0]->seg_prefix))
2068 return;
2069 }
2070 }
2071 else if ((i.tm.opcode_modifier & Ugh) != 0)
2072 {
24eab124
AM
2073 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2074 as_warn (_("translating to `%sp'"), i.tm.name);
252b5132
RH
2075 }
2076 }
2077
2078 /* Handle conversion of 'int $3' --> special int3 insn. */
2079 if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
2080 {
2081 i.tm.base_opcode = INT3_OPCODE;
2082 i.imm_operands = 0;
2083 }
2084
2f66722d
AM
2085 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
2086 && i.disps[0]->X_op == O_constant)
2087 {
2088 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2089 the absolute address given by the constant. Since ix86 jumps and
2090 calls are pc relative, we need to generate a reloc. */
2091 i.disps[0]->X_add_symbol = &abs_symbol;
2092 i.disps[0]->X_op = O_symbol;
2093 }
2094
252b5132
RH
2095 /* We are ready to output the insn. */
2096 {
2097 register char *p;
2098
2099 /* Output jumps. */
2100 if (i.tm.opcode_modifier & Jump)
2101 {
a217f122
AM
2102 int size;
2103 int code16;
2104 int prefix;
252b5132 2105
a217f122
AM
2106 code16 = 0;
2107 if (flag_16bit_code)
2108 code16 = CODE16;
2109
2110 prefix = 0;
2111 if (i.prefix[DATA_PREFIX])
252b5132 2112 {
a217f122 2113 prefix = 1;
252b5132 2114 i.prefixes -= 1;
a217f122 2115 code16 ^= CODE16;
252b5132 2116 }
252b5132 2117
a217f122
AM
2118 size = 4;
2119 if (code16)
2120 size = 2;
2121
2122 if (i.prefixes != 0 && !intel_syntax)
252b5132
RH
2123 as_warn (_("skipping prefixes on this instruction"));
2124
2f66722d
AM
2125 /* It's always a symbol; End frag & setup for relax.
2126 Make sure there is enough room in this frag for the largest
2127 instruction we may generate in md_convert_frag. This is 2
2128 bytes for the opcode and room for the prefix and largest
2129 displacement. */
2130 frag_grow (prefix + 2 + size);
2131 insn_size += prefix + 1;
2132 /* Prefix and 1 opcode byte go in fr_fix. */
2133 p = frag_more (prefix + 1);
2134 if (prefix)
2135 *p++ = DATA_PREFIX_OPCODE;
2136 *p = i.tm.base_opcode;
2137 /* 1 possible extra opcode + displacement go in fr_var. */
2138 frag_var (rs_machine_dependent,
2139 1 + size,
2140 1,
2141 ((unsigned char) *p == JUMP_PC_RELATIVE
2142 ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16
2143 : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16),
2144 i.disps[0]->X_add_symbol,
2145 i.disps[0]->X_add_number,
2146 p);
252b5132
RH
2147 }
2148 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
2149 {
a217f122 2150 int size;
252b5132 2151
a217f122 2152 if (i.tm.opcode_modifier & JumpByte)
252b5132 2153 {
a217f122
AM
2154 /* This is a loop or jecxz type instruction. */
2155 size = 1;
252b5132
RH
2156 if (i.prefix[ADDR_PREFIX])
2157 {
2158 insn_size += 1;
2159 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2160 i.prefixes -= 1;
2161 }
2162 }
2163 else
2164 {
a217f122
AM
2165 int code16;
2166
2167 code16 = 0;
2168 if (flag_16bit_code)
2169 code16 = CODE16;
252b5132
RH
2170
2171 if (i.prefix[DATA_PREFIX])
2172 {
2173 insn_size += 1;
2174 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
2175 i.prefixes -= 1;
a217f122 2176 code16 ^= CODE16;
252b5132 2177 }
252b5132 2178
a217f122 2179 size = 4;
252b5132
RH
2180 if (code16)
2181 size = 2;
2182 }
2183
a217f122 2184 if (i.prefixes != 0 && !intel_syntax)
252b5132
RH
2185 as_warn (_("skipping prefixes on this instruction"));
2186
2187 if (fits_in_unsigned_byte (i.tm.base_opcode))
2188 {
2189 insn_size += 1 + size;
2190 p = frag_more (1 + size);
2191 }
2192 else
2193 {
a217f122
AM
2194 /* opcode can be at most two bytes */
2195 insn_size += 2 + size;
252b5132
RH
2196 p = frag_more (2 + size);
2197 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2198 }
2199 *p++ = i.tm.base_opcode & 0xff;
2200
2f66722d
AM
2201 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2202 i.disps[0], 1, reloc (size, 1, i.disp_reloc[0]));
252b5132
RH
2203 }
2204 else if (i.tm.opcode_modifier & JumpInterSegment)
2205 {
2206 int size;
2207 int reloc_type;
a217f122
AM
2208 int prefix;
2209 int code16;
252b5132 2210
a217f122
AM
2211 code16 = 0;
2212 if (flag_16bit_code)
2213 code16 = CODE16;
2214
2215 prefix = 0;
2216 if (i.prefix[DATA_PREFIX])
252b5132 2217 {
a217f122 2218 prefix = 1;
252b5132 2219 i.prefixes -= 1;
a217f122 2220 code16 ^= CODE16;
252b5132 2221 }
252b5132
RH
2222
2223 size = 4;
2224 reloc_type = BFD_RELOC_32;
2225 if (code16)
2226 {
2227 size = 2;
2228 reloc_type = BFD_RELOC_16;
2229 }
2230
a217f122 2231 if (i.prefixes != 0 && !intel_syntax)
252b5132
RH
2232 as_warn (_("skipping prefixes on this instruction"));
2233
2234 insn_size += prefix + 1 + 2 + size; /* 1 opcode; 2 segment; offset */
2235 p = frag_more (prefix + 1 + 2 + size);
2236 if (prefix)
2237 *p++ = DATA_PREFIX_OPCODE;
2238 *p++ = i.tm.base_opcode;
2239 if (i.imms[1]->X_op == O_constant)
2240 {
2241 long n = (long) i.imms[1]->X_add_number;
2242
2243 if (size == 2 && !fits_in_unsigned_word (n))
2244 {
2245 as_bad (_("16-bit jump out of range"));
2246 return;
2247 }
2248 md_number_to_chars (p, (valueT) n, size);
2249 }
2250 else
2251 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2252 i.imms[1], 0, reloc_type);
2253 if (i.imms[0]->X_op != O_constant)
2254 as_bad (_("can't handle non absolute segment in `%s'"),
2255 i.tm.name);
2256 md_number_to_chars (p + size, (valueT) i.imms[0]->X_add_number, 2);
2257 }
2258 else
2259 {
2260 /* Output normal instructions here. */
2261 unsigned char *q;
2262
2263 /* The prefix bytes. */
2264 for (q = i.prefix;
2265 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
2266 q++)
2267 {
2268 if (*q)
2269 {
2270 insn_size += 1;
2271 p = frag_more (1);
2272 md_number_to_chars (p, (valueT) *q, 1);
2273 }
2274 }
2275
2276 /* Now the opcode; be careful about word order here! */
2277 if (fits_in_unsigned_byte (i.tm.base_opcode))
2278 {
2279 insn_size += 1;
2280 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
2281 }
2282 else if (fits_in_unsigned_word (i.tm.base_opcode))
2283 {
2284 insn_size += 2;
2285 p = frag_more (2);
2286 /* put out high byte first: can't use md_number_to_chars! */
2287 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2288 *p = i.tm.base_opcode & 0xff;
2289 }
2290 else
2291 { /* opcode is either 3 or 4 bytes */
2292 if (i.tm.base_opcode & 0xff000000)
2293 {
2294 insn_size += 4;
2295 p = frag_more (4);
2296 *p++ = (i.tm.base_opcode >> 24) & 0xff;
2297 }
2298 else
2299 {
2300 insn_size += 3;
2301 p = frag_more (3);
2302 }
2303 *p++ = (i.tm.base_opcode >> 16) & 0xff;
2304 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2305 *p = (i.tm.base_opcode) & 0xff;
2306 }
2307
2308 /* Now the modrm byte and sib byte (if present). */
2309 if (i.tm.opcode_modifier & Modrm)
2310 {
2311 insn_size += 1;
2312 p = frag_more (1);
2313 md_number_to_chars (p,
2314 (valueT) (i.rm.regmem << 0
2315 | i.rm.reg << 3
2316 | i.rm.mode << 6),
2317 1);
2318 /* If i.rm.regmem == ESP (4)
2319 && i.rm.mode != (Register mode)
2320 && not 16 bit
2321 ==> need second modrm byte. */
2322 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
2323 && i.rm.mode != 3
2324 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
2325 {
2326 insn_size += 1;
2327 p = frag_more (1);
2328 md_number_to_chars (p,
2329 (valueT) (i.sib.base << 0
2330 | i.sib.index << 3
2331 | i.sib.scale << 6),
2332 1);
2333 }
2334 }
2335
2336 if (i.disp_operands)
2337 {
2338 register unsigned int n;
2339
2340 for (n = 0; n < i.operands; n++)
2341 {
2342 if (i.disps[n])
2343 {
2344 if (i.disps[n]->X_op == O_constant)
2345 {
b4cac588
AM
2346 int size = 4;
2347 long val = (long) i.disps[n]->X_add_number;
2348
2349 if (i.types[n] & (Disp8 | Disp16))
252b5132 2350 {
b4cac588
AM
2351 long mask;
2352
2353 size = 2;
2354 mask = ~ (long) 0xffff;
2355 if (i.types[n] & Disp8)
2356 {
2357 size = 1;
2358 mask = ~ (long) 0xff;
2359 }
2360
2361 if ((val & mask) != 0 && (val & mask) != mask)
24eab124
AM
2362 as_warn (_("%ld shortened to %ld"),
2363 val, val & ~mask);
252b5132 2364 }
b4cac588
AM
2365 insn_size += size;
2366 p = frag_more (size);
2367 md_number_to_chars (p, (valueT) val, size);
252b5132
RH
2368 }
2369 else if (i.types[n] & Disp32)
2370 {
2371 insn_size += 4;
2372 p = frag_more (4);
2373 fix_new_exp (frag_now, p - frag_now->fr_literal, 4,
2374 i.disps[n], 0,
2375 TC_RELOC (i.disp_reloc[n], BFD_RELOC_32));
2376 }
2377 else
2378 { /* must be Disp16 */
2379 insn_size += 2;
2380 p = frag_more (2);
2381 fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
2382 i.disps[n], 0,
2383 TC_RELOC (i.disp_reloc[n], BFD_RELOC_16));
2384 }
2385 }
2386 }
2387 } /* end displacement output */
2388
2389 /* output immediate */
2390 if (i.imm_operands)
2391 {
2392 register unsigned int n;
2393
2394 for (n = 0; n < i.operands; n++)
2395 {
2396 if (i.imms[n])
2397 {
2398 if (i.imms[n]->X_op == O_constant)
2399 {
b4cac588
AM
2400 int size = 4;
2401 long val = (long) i.imms[n]->X_add_number;
2402
2403 if (i.types[n] & (Imm8 | Imm8S | Imm16))
252b5132 2404 {
b4cac588
AM
2405 long mask;
2406
2407 size = 2;
2408 mask = ~ (long) 0xffff;
2409 if (i.types[n] & (Imm8 | Imm8S))
2410 {
2411 size = 1;
2412 mask = ~ (long) 0xff;
2413 }
2414 if ((val & mask) != 0 && (val & mask) != mask)
24eab124
AM
2415 as_warn (_("%ld shortened to %ld"),
2416 val, val & ~mask);
252b5132 2417 }
b4cac588
AM
2418 insn_size += size;
2419 p = frag_more (size);
2420 md_number_to_chars (p, (valueT) val, size);
252b5132
RH
2421 }
2422 else
2423 { /* not absolute_section */
2424 /* Need a 32-bit fixup (don't support 8bit
2425 non-absolute ims). Try to support other
2426 sizes ... */
2427 int r_type;
2428 int size;
2429 int pcrel = 0;
2430
2431 if (i.types[n] & (Imm8 | Imm8S))
2432 size = 1;
2433 else if (i.types[n] & Imm16)
2434 size = 2;
2435 else
2436 size = 4;
2437 insn_size += size;
2438 p = frag_more (size);
2439 r_type = reloc (size, 0, i.disp_reloc[0]);
2440#ifdef BFD_ASSEMBLER
2441 if (r_type == BFD_RELOC_32
2442 && GOT_symbol
2443 && GOT_symbol == i.imms[n]->X_add_symbol
2444 && (i.imms[n]->X_op == O_symbol
2445 || (i.imms[n]->X_op == O_add
49309057
ILT
2446 && ((symbol_get_value_expression
2447 (i.imms[n]->X_op_symbol)->X_op)
252b5132
RH
2448 == O_subtract))))
2449 {
2450 r_type = BFD_RELOC_386_GOTPC;
2451 i.imms[n]->X_add_number += 3;
2452 }
2453#endif
2454 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2455 i.imms[n], pcrel, r_type);
2456 }
2457 }
2458 }
2459 } /* end immediate output */
2460 }
2461
2462#ifdef DEBUG386
2463 if (flag_debug)
2464 {
2465 pi (line, &i);
2466 }
2467#endif /* DEBUG386 */
2468 }
2469}
2470\f
252b5132
RH
2471static int i386_immediate PARAMS ((char *));
2472
2473static int
2474i386_immediate (imm_start)
2475 char *imm_start;
2476{
2477 char *save_input_line_pointer;
2478 segT exp_seg = 0;
2479 expressionS * exp;
2480
2481 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
2482 {
2483 as_bad (_("Only 1 or 2 immediate operands are allowed"));
2484 return 0;
2485 }
2486
2487 exp = &im_expressions[i.imm_operands++];
2488 i.imms[this_operand] = exp;
2489
2490 if (is_space_char (*imm_start))
2491 ++imm_start;
2492
2493 save_input_line_pointer = input_line_pointer;
2494 input_line_pointer = imm_start;
2495
2496#ifndef LEX_AT
24eab124
AM
2497 {
2498 /*
2499 * We can have operands of the form
2500 * <symbol>@GOTOFF+<nnn>
2501 * Take the easy way out here and copy everything
2502 * into a temporary buffer...
2503 */
2504 register char *cp;
2505
2506 cp = strchr (input_line_pointer, '@');
2507 if (cp != NULL)
2508 {
2509 char *tmpbuf;
2510 int len = 0;
2511 int first;
2512
2513 /* GOT relocations are not supported in 16 bit mode */
2514 if (flag_16bit_code)
2515 as_bad (_("GOT relocations not supported in 16 bit mode"));
2516
2517 if (GOT_symbol == NULL)
2518 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2519
2520 if (strncmp (cp + 1, "PLT", 3) == 0)
2521 {
2522 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2523 len = 3;
2524 }
2525 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
2526 {
2527 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2528 len = 6;
2529 }
2530 else if (strncmp (cp + 1, "GOT", 3) == 0)
2531 {
2532 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2533 len = 3;
2534 }
2535 else
2536 as_bad (_("Bad reloc specifier in expression"));
2537
2538 /* Replace the relocation token with ' ', so that errors like
2539 foo@GOTOFF1 will be detected. */
2540 first = cp - input_line_pointer;
2541 tmpbuf = (char *) alloca (strlen(input_line_pointer));
2542 memcpy (tmpbuf, input_line_pointer, first);
2543 tmpbuf[first] = ' ';
2544 strcpy (tmpbuf + first + 1, cp + 1 + len);
2545 input_line_pointer = tmpbuf;
2546 }
2547 }
252b5132
RH
2548#endif
2549
2550 exp_seg = expression (exp);
2551
83183c0c 2552 SKIP_WHITESPACE ();
252b5132
RH
2553 if (*input_line_pointer)
2554 as_bad (_("Ignoring junk `%s' after expression"), input_line_pointer);
2555
2556 input_line_pointer = save_input_line_pointer;
2557
2daf4fd8 2558 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132
RH
2559 {
2560 /* missing or bad expr becomes absolute 0 */
2561 as_bad (_("Missing or invalid immediate expression `%s' taken as 0"),
24eab124 2562 imm_start);
252b5132
RH
2563 exp->X_op = O_constant;
2564 exp->X_add_number = 0;
2565 exp->X_add_symbol = (symbolS *) 0;
2566 exp->X_op_symbol = (symbolS *) 0;
252b5132 2567 }
2daf4fd8
AM
2568
2569 if (exp->X_op == O_constant)
252b5132 2570 {
b4cac588
AM
2571 int bigimm = Imm32;
2572 if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0))
2573 bigimm = Imm16;
2574
252b5132 2575 i.types[this_operand] |=
b4cac588
AM
2576 (bigimm | smallest_imm_type ((long) exp->X_add_number));
2577
add0c677 2578 /* If a suffix is given, this operand may be shortened. */
252b5132 2579 switch (i.suffix)
24eab124
AM
2580 {
2581 case WORD_MNEM_SUFFIX:
2582 i.types[this_operand] |= Imm16;
2583 break;
2584 case BYTE_MNEM_SUFFIX:
2585 i.types[this_operand] |= Imm16 | Imm8 | Imm8S;
2586 break;
2587 }
252b5132 2588 }
4c63da97
AM
2589#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2590 else if (
2591#ifdef BFD_ASSEMBLER
2592 OUTPUT_FLAVOR == bfd_target_aout_flavour &&
2593#endif
2594 exp_seg != text_section
24eab124
AM
2595 && exp_seg != data_section
2596 && exp_seg != bss_section
2597 && exp_seg != undefined_section
252b5132 2598#ifdef BFD_ASSEMBLER
24eab124 2599 && !bfd_is_com_section (exp_seg)
252b5132 2600#endif
24eab124 2601 )
252b5132 2602 {
4c63da97
AM
2603#ifdef BFD_ASSEMBLER
2604 as_bad (_("Unimplemented segment %s in operand"), exp_seg->name);
2605#else
252b5132 2606 as_bad (_("Unimplemented segment type %d in operand"), exp_seg);
4c63da97 2607#endif
252b5132
RH
2608 return 0;
2609 }
2610#endif
2611 else
2612 {
2613 /* This is an address. The size of the address will be
24eab124
AM
2614 determined later, depending on destination register,
2615 suffix, or the default for the section. We exclude
2616 Imm8S here so that `push $foo' and other instructions
2617 with an Imm8S form will use Imm16 or Imm32. */
252b5132
RH
2618 i.types[this_operand] |= (Imm8 | Imm16 | Imm32);
2619 }
2620
2621 return 1;
2622}
2623
2624static int i386_scale PARAMS ((char *));
2625
2626static int
2627i386_scale (scale)
2628 char *scale;
2629{
2630 if (!isdigit (*scale))
2631 goto bad_scale;
2632
2633 switch (*scale)
2634 {
2635 case '0':
2636 case '1':
2637 i.log2_scale_factor = 0;
2638 break;
2639 case '2':
2640 i.log2_scale_factor = 1;
2641 break;
2642 case '4':
2643 i.log2_scale_factor = 2;
2644 break;
2645 case '8':
2646 i.log2_scale_factor = 3;
2647 break;
2648 default:
2649 bad_scale:
2650 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 2651 scale);
252b5132
RH
2652 return 0;
2653 }
2654 if (i.log2_scale_factor != 0 && ! i.index_reg)
2655 {
2656 as_warn (_("scale factor of %d without an index register"),
24eab124 2657 1 << i.log2_scale_factor);
252b5132
RH
2658#if SCALE1_WHEN_NO_INDEX
2659 i.log2_scale_factor = 0;
2660#endif
2661 }
2662 return 1;
2663}
2664
2665static int i386_displacement PARAMS ((char *, char *));
2666
2667static int
2668i386_displacement (disp_start, disp_end)
2669 char *disp_start;
2670 char *disp_end;
2671{
2672 register expressionS *exp;
2673 segT exp_seg = 0;
2674 char *save_input_line_pointer;
2675 int bigdisp = Disp32;
2676
252b5132
RH
2677 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0))
2678 bigdisp = Disp16;
2679 i.types[this_operand] |= bigdisp;
2680
2681 exp = &disp_expressions[i.disp_operands];
2682 i.disps[this_operand] = exp;
2683 i.disp_reloc[this_operand] = NO_RELOC;
2684 i.disp_operands++;
2685 save_input_line_pointer = input_line_pointer;
2686 input_line_pointer = disp_start;
2687 END_STRING_AND_SAVE (disp_end);
2688
2689#ifndef GCC_ASM_O_HACK
2690#define GCC_ASM_O_HACK 0
2691#endif
2692#if GCC_ASM_O_HACK
2693 END_STRING_AND_SAVE (disp_end + 1);
2694 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 2695 && displacement_string_end[-1] == '+')
252b5132
RH
2696 {
2697 /* This hack is to avoid a warning when using the "o"
24eab124
AM
2698 constraint within gcc asm statements.
2699 For instance:
2700
2701 #define _set_tssldt_desc(n,addr,limit,type) \
2702 __asm__ __volatile__ ( \
2703 "movw %w2,%0\n\t" \
2704 "movw %w1,2+%0\n\t" \
2705 "rorl $16,%1\n\t" \
2706 "movb %b1,4+%0\n\t" \
2707 "movb %4,5+%0\n\t" \
2708 "movb $0,6+%0\n\t" \
2709 "movb %h1,7+%0\n\t" \
2710 "rorl $16,%1" \
2711 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2712
2713 This works great except that the output assembler ends
2714 up looking a bit weird if it turns out that there is
2715 no offset. You end up producing code that looks like:
2716
2717 #APP
2718 movw $235,(%eax)
2719 movw %dx,2+(%eax)
2720 rorl $16,%edx
2721 movb %dl,4+(%eax)
2722 movb $137,5+(%eax)
2723 movb $0,6+(%eax)
2724 movb %dh,7+(%eax)
2725 rorl $16,%edx
2726 #NO_APP
2727
2728 So here we provide the missing zero.
2729 */
2730
2731 *displacement_string_end = '0';
252b5132
RH
2732 }
2733#endif
2734#ifndef LEX_AT
24eab124
AM
2735 {
2736 /*
2737 * We can have operands of the form
2738 * <symbol>@GOTOFF+<nnn>
2739 * Take the easy way out here and copy everything
2740 * into a temporary buffer...
2741 */
2742 register char *cp;
2743
2744 cp = strchr (input_line_pointer, '@');
2745 if (cp != NULL)
2746 {
2747 char *tmpbuf;
2748 int len = 0;
2749 int first;
2750
2751 /* GOT relocations are not supported in 16 bit mode */
2752 if (flag_16bit_code)
2753 as_bad (_("GOT relocations not supported in 16 bit mode"));
2754
2755 if (GOT_symbol == NULL)
2756 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2757
2758 if (strncmp (cp + 1, "PLT", 3) == 0)
2759 {
2760 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2761 len = 3;
2762 }
2763 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
2764 {
2765 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2766 len = 6;
2767 }
2768 else if (strncmp (cp + 1, "GOT", 3) == 0)
2769 {
2770 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2771 len = 3;
2772 }
2773 else
2774 as_bad (_("Bad reloc specifier in expression"));
2775
2776 /* Replace the relocation token with ' ', so that errors like
2777 foo@GOTOFF1 will be detected. */
2778 first = cp - input_line_pointer;
2779 tmpbuf = (char *) alloca (strlen(input_line_pointer));
2780 memcpy (tmpbuf, input_line_pointer, first);
2781 tmpbuf[first] = ' ';
2782 strcpy (tmpbuf + first + 1, cp + 1 + len);
2783 input_line_pointer = tmpbuf;
2784 }
2785 }
252b5132
RH
2786#endif
2787
24eab124 2788 exp_seg = expression (exp);
252b5132
RH
2789
2790#ifdef BFD_ASSEMBLER
24eab124
AM
2791 /* We do this to make sure that the section symbol is in
2792 the symbol table. We will ultimately change the relocation
2793 to be relative to the beginning of the section */
2794 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
2795 {
2796 if (S_IS_LOCAL(exp->X_add_symbol)
2797 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
2798 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
2799 assert (exp->X_op == O_symbol);
2800 exp->X_op = O_subtract;
2801 exp->X_op_symbol = GOT_symbol;
2802 i.disp_reloc[this_operand] = BFD_RELOC_32;
2803 }
252b5132
RH
2804#endif
2805
24eab124
AM
2806 SKIP_WHITESPACE ();
2807 if (*input_line_pointer)
2808 as_bad (_("Ignoring junk `%s' after expression"),
2809 input_line_pointer);
252b5132 2810#if GCC_ASM_O_HACK
24eab124 2811 RESTORE_END_STRING (disp_end + 1);
252b5132 2812#endif
24eab124
AM
2813 RESTORE_END_STRING (disp_end);
2814 input_line_pointer = save_input_line_pointer;
2815
2daf4fd8
AM
2816 if (exp->X_op == O_absent || exp->X_op == O_big)
2817 {
2818 /* missing or bad expr becomes absolute 0 */
2819 as_bad (_("Missing or invalid displacement expression `%s' taken as 0"),
2820 disp_start);
2821 exp->X_op = O_constant;
2822 exp->X_add_number = 0;
2823 exp->X_add_symbol = (symbolS *) 0;
2824 exp->X_op_symbol = (symbolS *) 0;
2825 }
2826
24eab124
AM
2827 if (exp->X_op == O_constant)
2828 {
2829 if (fits_in_signed_byte (exp->X_add_number))
2830 i.types[this_operand] |= Disp8;
2831 }
4c63da97
AM
2832#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2833 else if (
2834#ifdef BFD_ASSEMBLER
2835 OUTPUT_FLAVOR == bfd_target_aout_flavour &&
2836#endif
2837 exp_seg != text_section
24eab124
AM
2838 && exp_seg != data_section
2839 && exp_seg != bss_section
2840 && exp_seg != undefined_section)
2841 {
4c63da97
AM
2842#ifdef BFD_ASSEMBLER
2843 as_bad (_("Unimplemented segment %s in operand"), exp_seg->name);
2844#else
2845 as_bad (_("Unimplemented segment type %d in operand"), exp_seg);
2846#endif
24eab124
AM
2847 return 0;
2848 }
252b5132
RH
2849#endif
2850 return 1;
2851}
2852
2853static int i386_operand_modifier PARAMS ((char **, int));
2854
2855static int
2856i386_operand_modifier (op_string, got_a_float)
2857 char **op_string;
2858 int got_a_float;
2859{
24eab124
AM
2860 if (!strncasecmp (*op_string, "BYTE PTR", 8))
2861 {
2862 i.suffix = BYTE_MNEM_SUFFIX;
2863 *op_string += 8;
2864 return BYTE_PTR;
252b5132 2865
24eab124
AM
2866 }
2867 else if (!strncasecmp (*op_string, "WORD PTR", 8))
2868 {
2869 i.suffix = WORD_MNEM_SUFFIX;
2870 *op_string += 8;
2871 return WORD_PTR;
2872 }
252b5132 2873
24eab124
AM
2874 else if (!strncasecmp (*op_string, "DWORD PTR", 9))
2875 {
2876 if (got_a_float)
2877 i.suffix = SHORT_MNEM_SUFFIX;
2878 else
add0c677 2879 i.suffix = LONG_MNEM_SUFFIX;
24eab124
AM
2880 *op_string += 9;
2881 return DWORD_PTR;
2882 }
252b5132 2883
24eab124
AM
2884 else if (!strncasecmp (*op_string, "QWORD PTR", 9))
2885 {
add0c677 2886 i.suffix = DWORD_MNEM_SUFFIX;
24eab124
AM
2887 *op_string += 9;
2888 return QWORD_PTR;
2889 }
252b5132 2890
24eab124
AM
2891 else if (!strncasecmp (*op_string, "XWORD PTR", 9))
2892 {
2893 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
2894 *op_string += 9;
2895 return XWORD_PTR;
2896 }
252b5132 2897
24eab124
AM
2898 else if (!strncasecmp (*op_string, "SHORT", 5))
2899 {
2900 *op_string += 5;
2901 return SHORT;
2902 }
252b5132 2903
24eab124
AM
2904 else if (!strncasecmp (*op_string, "OFFSET FLAT:", 12))
2905 {
2906 *op_string += 12;
2907 return OFFSET_FLAT;
2908 }
252b5132 2909
24eab124
AM
2910 else if (!strncasecmp (*op_string, "FLAT", 4))
2911 {
2912 *op_string += 4;
2913 return FLAT;
2914 }
252b5132 2915
24eab124 2916 else return NONE_FOUND;
c3332e24 2917}
252b5132
RH
2918
2919static char * build_displacement_string PARAMS ((int, char *));
2920
2921static char *
2922build_displacement_string (initial_disp, op_string)
2923 int initial_disp;
2924 char *op_string;
2925{
2926 char *temp_string = (char *) malloc (strlen (op_string) + 1);
2927 char *end_of_operand_string;
2928 char *tc;
2929 char *temp_disp;
2930
2931 temp_string[0] = '\0';
2932 tc = end_of_operand_string = strchr (op_string, '[');
2933 if ( initial_disp && !end_of_operand_string)
2934 {
2935 strcpy (temp_string, op_string);
2936 return (temp_string);
2937 }
2938
2939 /* Build the whole displacement string */
2940 if (initial_disp)
2941 {
2942 strncpy (temp_string, op_string, end_of_operand_string - op_string);
2943 temp_string[end_of_operand_string - op_string] = '\0';
2944 temp_disp = tc;
2945 }
c3332e24 2946 else
252b5132
RH
2947 temp_disp = op_string;
2948
2949 while (*temp_disp != '\0')
2950 {
af6bdddf 2951 char *end_op;
252b5132
RH
2952 int add_minus = (*temp_disp == '-');
2953
2954 if (*temp_disp == '+' || *temp_disp == '-' || *temp_disp == '[')
24eab124 2955 temp_disp++;
252b5132
RH
2956
2957 if (is_space_char (*temp_disp))
24eab124 2958 temp_disp++;
252b5132
RH
2959
2960 /* Don't consider registers */
af6bdddf
AM
2961 if ( !((*temp_disp == REGISTER_PREFIX || allow_naked_reg)
2962 && parse_register (temp_disp, &end_op)) )
24eab124
AM
2963 {
2964 char *string_start = temp_disp;
2965
2966 while (*temp_disp != ']'
2967 && *temp_disp != '+'
2968 && *temp_disp != '-'
2969 && *temp_disp != '*')
2970 ++temp_disp;
2971
2972 if (add_minus)
2973 strcat (temp_string, "-");
2974 else
2975 strcat (temp_string, "+");
2976
2977 strncat (temp_string, string_start, temp_disp - string_start);
2978 if (*temp_disp == '+' || *temp_disp == '-')
2979 --temp_disp;
2980 }
252b5132
RH
2981
2982 while (*temp_disp != '\0'
24eab124
AM
2983 && *temp_disp != '+'
2984 && *temp_disp != '-')
2985 ++temp_disp;
252b5132
RH
2986 }
2987
2988 return temp_string;
2989}
2990
2991static int i386_parse_seg PARAMS ((char *));
2992
2993static int
2994i386_parse_seg (op_string)
2995 char *op_string;
2996{
2997 if (is_space_char (*op_string))
2998 ++op_string;
2999
3000 /* Should be one of es, cs, ss, ds fs or gs */
3001 switch (*op_string++)
3002 {
3003 case 'e':
3004 i.seg[i.mem_operands] = &es;
3005 break;
3006 case 'c':
3007 i.seg[i.mem_operands] = &cs;
3008 break;
3009 case 's':
3010 i.seg[i.mem_operands] = &ss;
3011 break;
3012 case 'd':
3013 i.seg[i.mem_operands] = &ds;
3014 break;
3015 case 'f':
3016 i.seg[i.mem_operands] = &fs;
3017 break;
3018 case 'g':
3019 i.seg[i.mem_operands] = &gs;
3020 break;
3021 default:
3022 as_bad (_("bad segment name `%s'"), op_string);
3023 return 0;
3024 }
3025
3026 if (*op_string++ != 's')
3027 {
24eab124
AM
3028 as_bad (_("bad segment name `%s'"), op_string);
3029 return 0;
252b5132
RH
3030 }
3031
3032 if (is_space_char (*op_string))
3033 ++op_string;
3034
3035 if (*op_string != ':')
3036 {
24eab124
AM
3037 as_bad (_("bad segment name `%s'"), op_string);
3038 return 0;
252b5132
RH
3039 }
3040
c3332e24
AM
3041 return 1;
3042
252b5132
RH
3043}
3044
eecb386c 3045static int i386_index_check PARAMS((const char *));
252b5132 3046
eecb386c
AM
3047/* Make sure the memory operand we've been dealt is valid.
3048 Returns 1 on success, 0 on a failure.
3049*/
252b5132 3050static int
eecb386c
AM
3051i386_index_check (operand_string)
3052 const char *operand_string;
252b5132 3053{
24eab124 3054#if INFER_ADDR_PREFIX
eecb386c
AM
3055 int fudged = 0;
3056
24eab124
AM
3057 tryprefix:
3058#endif
3059 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ?
3060 /* 16 bit mode checks */
3061 ((i.base_reg
3062 && ((i.base_reg->reg_type & (Reg16|BaseIndex))
3063 != (Reg16|BaseIndex)))
3064 || (i.index_reg
3065 && (((i.index_reg->reg_type & (Reg16|BaseIndex))
3066 != (Reg16|BaseIndex))
3067 || ! (i.base_reg
3068 && i.base_reg->reg_num < 6
3069 && i.index_reg->reg_num >= 6
3070 && i.log2_scale_factor == 0)))) :
3071 /* 32 bit mode checks */
3072 ((i.base_reg
3073 && (i.base_reg->reg_type & Reg32) == 0)
3074 || (i.index_reg
3075 && ((i.index_reg->reg_type & (Reg32|BaseIndex))
3076 != (Reg32|BaseIndex)))))
3077 {
3078#if INFER_ADDR_PREFIX
eecb386c 3079 if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM
3080 {
3081 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3082 i.prefixes += 1;
b23bac36
AM
3083 /* Change the size of any displacement too. At most one of
3084 Disp16 or Disp32 is set.
3085 FIXME. There doesn't seem to be any real need for separate
3086 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3087 Removing them would probably clean up the code quite a lot.
3088 */
3089 if (i.types[this_operand] & (Disp16|Disp32))
3090 i.types[this_operand] ^= (Disp16|Disp32);
eecb386c 3091 fudged = 1;
24eab124
AM
3092 goto tryprefix;
3093 }
eecb386c
AM
3094 if (fudged)
3095 as_bad (_("`%s' is not a valid base/index expression"),
3096 operand_string);
3097 else
c388dee8 3098#endif
eecb386c
AM
3099 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3100 operand_string,
3101 flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32");
3102 return 0;
24eab124
AM
3103 }
3104 return 1;
3105}
252b5132 3106
24eab124
AM
3107static int i386_intel_memory_operand PARAMS ((char *));
3108
3109static int
3110i386_intel_memory_operand (operand_string)
3111 char *operand_string;
3112{
3113 char *op_string = operand_string;
252b5132
RH
3114 char *end_of_operand_string;
3115
24eab124
AM
3116 if ((i.mem_operands == 1
3117 && (current_templates->start->opcode_modifier & IsString) == 0)
3118 || i.mem_operands == 2)
252b5132 3119 {
24eab124
AM
3120 as_bad (_("too many memory references for `%s'"),
3121 current_templates->start->name);
3122 return 0;
252b5132
RH
3123 }
3124
3125 /* Look for displacement preceding open bracket */
3126 if (*op_string != '[')
3127 {
3128 char *end_seg;
3129 char *temp_string;
3130
3131 end_seg = strchr (op_string, ':');
3132 if (end_seg)
24eab124
AM
3133 {
3134 if (!i386_parse_seg (op_string))
3135 return 0;
3136 op_string = end_seg + 1;
3137 }
252b5132
RH
3138
3139 temp_string = build_displacement_string (true, op_string);
24eab124
AM
3140
3141 if (i.disp_operands == 0 &&
3142 !i386_displacement (temp_string, temp_string + strlen (temp_string)))
3143 return 0;
252b5132
RH
3144
3145 end_of_operand_string = strchr (op_string, '[');
3146 if (!end_of_operand_string)
24eab124 3147 end_of_operand_string = op_string + strlen (op_string);
252b5132
RH
3148
3149 if (is_space_char (*end_of_operand_string))
24eab124 3150 --end_of_operand_string;
252b5132
RH
3151
3152 op_string = end_of_operand_string;
24eab124 3153 }
252b5132
RH
3154
3155 if (*op_string == '[')
3156 {
3157 ++op_string;
3158
3159 /* Pick off each component and figure out where it belongs */
3160
3161 end_of_operand_string = op_string;
3162
3163 while (*op_string != ']')
24eab124 3164 {
af6bdddf
AM
3165 const reg_entry *temp_reg;
3166 char *end_op;
3167 char *temp_string;
24eab124
AM
3168
3169 while (*end_of_operand_string != '+'
3170 && *end_of_operand_string != '-'
3171 && *end_of_operand_string != '*'
3172 && *end_of_operand_string != ']')
3173 end_of_operand_string++;
3174
af6bdddf
AM
3175 temp_string = op_string;
3176 if (*temp_string == '+')
24eab124 3177 {
af6bdddf 3178 ++temp_string;
24eab124
AM
3179 if (is_space_char (*temp_string))
3180 ++temp_string;
24eab124
AM
3181 }
3182
af6bdddf
AM
3183 if ((*temp_string == REGISTER_PREFIX || allow_naked_reg)
3184 && (temp_reg = parse_register (temp_string, &end_op)) != NULL)
24eab124 3185 {
24eab124
AM
3186 if (i.base_reg == NULL)
3187 i.base_reg = temp_reg;
3188 else
3189 i.index_reg = temp_reg;
3190
3191 i.types[this_operand] |= BaseIndex;
24eab124 3192 }
af6bdddf 3193 else if (*temp_string == REGISTER_PREFIX)
24eab124 3194 {
af6bdddf
AM
3195 as_bad (_("bad register name `%s'"), temp_string);
3196 return 0;
3197 }
3198 else if (is_digit_char (*op_string)
3199 || *op_string == '+' || *op_string == '-')
3200 {
3201 temp_string = build_displacement_string (false, op_string);
24eab124
AM
3202
3203 if (*temp_string == '+')
3204 ++temp_string;
3205
3206 if (i.disp_operands == 0 &&
3207 !i386_displacement (temp_string, temp_string + strlen (temp_string)))
3208 return 0;
3209
3210 ++op_string;
3211 end_of_operand_string = op_string;
3212 while (*end_of_operand_string != ']'
3213 && *end_of_operand_string != '+'
3214 && *end_of_operand_string != '-'
3215 && *end_of_operand_string != '*')
3216 ++end_of_operand_string;
3217 }
3218 else if (*op_string == '*')
3219 {
3220 ++op_string;
3221
3222 if (i.base_reg && !i.index_reg)
3223 {
3224 i.index_reg = i.base_reg;
3225 i.base_reg = 0;
3226 }
3227
3228 if (!i386_scale (op_string))
3229 return 0;
3230 }
3231 op_string = end_of_operand_string;
3232 ++end_of_operand_string;
3233 }
3234 }
3235
eecb386c
AM
3236 if (i386_index_check (operand_string) == 0)
3237 return 0;
252b5132 3238
24eab124 3239 i.mem_operands++;
252b5132
RH
3240 return 1;
3241}
3242
252b5132
RH
3243static int
3244i386_intel_operand (operand_string, got_a_float)
3245 char *operand_string;
3246 int got_a_float;
3247{
af6bdddf
AM
3248 const reg_entry * r;
3249 char *end_op;
252b5132
RH
3250 char *op_string = operand_string;
3251
3252 int operand_modifier = i386_operand_modifier (&op_string, got_a_float);
3253 if (is_space_char (*op_string))
3254 ++op_string;
3255
3256 switch (operand_modifier)
3257 {
3258 case BYTE_PTR:
3259 case WORD_PTR:
3260 case DWORD_PTR:
3261 case QWORD_PTR:
3262 case XWORD_PTR:
252b5132 3263 if (!i386_intel_memory_operand (op_string))
24eab124 3264 return 0;
252b5132
RH
3265 break;
3266
3267 case FLAT:
252b5132
RH
3268 case OFFSET_FLAT:
3269 if (!i386_immediate (op_string))
24eab124 3270 return 0;
252b5132
RH
3271 break;
3272
3273 case SHORT:
252b5132 3274 case NONE_FOUND:
c3332e24
AM
3275 /* Should be register or immediate */
3276 if (is_digit_char (*op_string)
3277 && strchr (op_string, '[') == 0)
3278 {
3279 if (!i386_immediate (op_string))
3280 return 0;
3281 }
af6bdddf
AM
3282 else if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3283 && (r = parse_register (op_string, &end_op)) != NULL)
c3332e24 3284 {
c3332e24
AM
3285 /* Check for a segment override by searching for ':' after a
3286 segment register. */
3287 op_string = end_op;
3288 if (is_space_char (*op_string))
3289 ++op_string;
3290 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3291 {
3292 switch (r->reg_num)
3293 {
3294 case 0:
3295 i.seg[i.mem_operands] = &es;
3296 break;
3297 case 1:
3298 i.seg[i.mem_operands] = &cs;
3299 break;
3300 case 2:
3301 i.seg[i.mem_operands] = &ss;
3302 break;
3303 case 3:
3304 i.seg[i.mem_operands] = &ds;
3305 break;
3306 case 4:
3307 i.seg[i.mem_operands] = &fs;
3308 break;
3309 case 5:
3310 i.seg[i.mem_operands] = &gs;
3311 break;
3312 }
252b5132 3313
c3332e24
AM
3314 }
3315 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3316 i.regs[this_operand] = r;
3317 i.reg_operands++;
3318 }
af6bdddf 3319 else if (*op_string == REGISTER_PREFIX)
c3332e24 3320 {
af6bdddf
AM
3321 as_bad (_("bad register name `%s'"), op_string);
3322 return 0;
c3332e24 3323 }
af6bdddf
AM
3324 else if (!i386_intel_memory_operand (op_string))
3325 return 0;
3326
c3332e24 3327 break;
c3332e24 3328 } /* end switch */
24eab124 3329
252b5132
RH
3330 return 1;
3331}
3332
3333/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3334 on error. */
3335
252b5132
RH
3336static int
3337i386_operand (operand_string)
3338 char *operand_string;
3339{
af6bdddf
AM
3340 const reg_entry *r;
3341 char *end_op;
24eab124 3342 char *op_string = operand_string;
252b5132 3343
24eab124 3344 if (is_space_char (*op_string))
252b5132
RH
3345 ++op_string;
3346
24eab124
AM
3347 /* We check for an absolute prefix (differentiating,
3348 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3349 if (*op_string == ABSOLUTE_PREFIX)
3350 {
3351 ++op_string;
3352 if (is_space_char (*op_string))
3353 ++op_string;
3354 i.types[this_operand] |= JumpAbsolute;
3355 }
252b5132 3356
24eab124 3357 /* Check if operand is a register. */
af6bdddf
AM
3358 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3359 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 3360 {
24eab124
AM
3361 /* Check for a segment override by searching for ':' after a
3362 segment register. */
3363 op_string = end_op;
3364 if (is_space_char (*op_string))
3365 ++op_string;
3366 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3367 {
3368 switch (r->reg_num)
3369 {
3370 case 0:
3371 i.seg[i.mem_operands] = &es;
3372 break;
3373 case 1:
3374 i.seg[i.mem_operands] = &cs;
3375 break;
3376 case 2:
3377 i.seg[i.mem_operands] = &ss;
3378 break;
3379 case 3:
3380 i.seg[i.mem_operands] = &ds;
3381 break;
3382 case 4:
3383 i.seg[i.mem_operands] = &fs;
3384 break;
3385 case 5:
3386 i.seg[i.mem_operands] = &gs;
3387 break;
3388 }
252b5132 3389
24eab124 3390 /* Skip the ':' and whitespace. */
252b5132
RH
3391 ++op_string;
3392 if (is_space_char (*op_string))
24eab124 3393 ++op_string;
252b5132 3394
24eab124
AM
3395 if (!is_digit_char (*op_string)
3396 && !is_identifier_char (*op_string)
3397 && *op_string != '('
3398 && *op_string != ABSOLUTE_PREFIX)
3399 {
3400 as_bad (_("bad memory operand `%s'"), op_string);
3401 return 0;
3402 }
3403 /* Handle case of %es:*foo. */
3404 if (*op_string == ABSOLUTE_PREFIX)
3405 {
3406 ++op_string;
3407 if (is_space_char (*op_string))
3408 ++op_string;
3409 i.types[this_operand] |= JumpAbsolute;
3410 }
3411 goto do_memory_reference;
3412 }
3413 if (*op_string)
3414 {
3415 as_bad (_("Junk `%s' after register"), op_string);
3416 return 0;
3417 }
3418 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3419 i.regs[this_operand] = r;
3420 i.reg_operands++;
3421 }
af6bdddf
AM
3422 else if (*op_string == REGISTER_PREFIX)
3423 {
3424 as_bad (_("bad register name `%s'"), op_string);
3425 return 0;
3426 }
24eab124
AM
3427 else if (*op_string == IMMEDIATE_PREFIX)
3428 { /* ... or an immediate */
3429 ++op_string;
3430 if (i.types[this_operand] & JumpAbsolute)
3431 {
3432 as_bad (_("Immediate operand illegal with absolute jump"));
3433 return 0;
3434 }
3435 if (!i386_immediate (op_string))
3436 return 0;
3437 }
3438 else if (is_digit_char (*op_string)
3439 || is_identifier_char (*op_string)
3440 || *op_string == '(' )
3441 {
3442 /* This is a memory reference of some sort. */
af6bdddf 3443 char *base_string;
252b5132 3444
24eab124 3445 /* Start and end of displacement string expression (if found). */
eecb386c
AM
3446 char *displacement_string_start;
3447 char *displacement_string_end;
252b5132 3448
24eab124 3449 do_memory_reference:
24eab124
AM
3450 if ((i.mem_operands == 1
3451 && (current_templates->start->opcode_modifier & IsString) == 0)
3452 || i.mem_operands == 2)
3453 {
3454 as_bad (_("too many memory references for `%s'"),
3455 current_templates->start->name);
3456 return 0;
3457 }
252b5132 3458
24eab124
AM
3459 /* Check for base index form. We detect the base index form by
3460 looking for an ')' at the end of the operand, searching
3461 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3462 after the '('. */
af6bdddf 3463 base_string = op_string + strlen (op_string);
c3332e24 3464
af6bdddf
AM
3465 --base_string;
3466 if (is_space_char (*base_string))
3467 --base_string;
252b5132 3468
af6bdddf
AM
3469 /* If we only have a displacement, set-up for it to be parsed later. */
3470 displacement_string_start = op_string;
3471 displacement_string_end = base_string + 1;
252b5132 3472
24eab124
AM
3473 if (*base_string == ')')
3474 {
af6bdddf 3475 char *temp_string;
24eab124
AM
3476 unsigned int parens_balanced = 1;
3477 /* We've already checked that the number of left & right ()'s are
3478 equal, so this loop will not be infinite. */
3479 do
3480 {
3481 base_string--;
3482 if (*base_string == ')')
3483 parens_balanced++;
3484 if (*base_string == '(')
3485 parens_balanced--;
3486 }
3487 while (parens_balanced);
c3332e24 3488
af6bdddf 3489 temp_string = base_string;
c3332e24 3490
24eab124 3491 /* Skip past '(' and whitespace. */
252b5132
RH
3492 ++base_string;
3493 if (is_space_char (*base_string))
24eab124 3494 ++base_string;
252b5132 3495
af6bdddf
AM
3496 if (*base_string == ','
3497 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3498 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 3499 {
af6bdddf 3500 displacement_string_end = temp_string;
252b5132 3501
af6bdddf 3502 i.types[this_operand] |= BaseIndex;
252b5132 3503
af6bdddf 3504 if (i.base_reg)
24eab124 3505 {
24eab124
AM
3506 base_string = end_op;
3507 if (is_space_char (*base_string))
3508 ++base_string;
af6bdddf
AM
3509 }
3510
3511 /* There may be an index reg or scale factor here. */
3512 if (*base_string == ',')
3513 {
3514 ++base_string;
3515 if (is_space_char (*base_string))
3516 ++base_string;
3517
3518 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3519 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 3520 {
af6bdddf 3521 base_string = end_op;
24eab124
AM
3522 if (is_space_char (*base_string))
3523 ++base_string;
af6bdddf
AM
3524 if (*base_string == ',')
3525 {
3526 ++base_string;
3527 if (is_space_char (*base_string))
3528 ++base_string;
3529 }
3530 else if (*base_string != ')' )
3531 {
3532 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3533 operand_string);
3534 return 0;
3535 }
24eab124 3536 }
af6bdddf 3537 else if (*base_string == REGISTER_PREFIX)
24eab124 3538 {
af6bdddf 3539 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM
3540 return 0;
3541 }
252b5132 3542
af6bdddf
AM
3543 /* Check for scale factor. */
3544 if (isdigit ((unsigned char) *base_string))
3545 {
3546 if (!i386_scale (base_string))
3547 return 0;
24eab124 3548
af6bdddf
AM
3549 ++base_string;
3550 if (is_space_char (*base_string))
3551 ++base_string;
3552 if (*base_string != ')')
3553 {
3554 as_bad (_("expecting `)' after scale factor in `%s'"),
3555 operand_string);
3556 return 0;
3557 }
3558 }
3559 else if (!i.index_reg)
24eab124 3560 {
af6bdddf
AM
3561 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3562 *base_string);
24eab124
AM
3563 return 0;
3564 }
3565 }
af6bdddf 3566 else if (*base_string != ')')
24eab124 3567 {
af6bdddf
AM
3568 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3569 operand_string);
24eab124
AM
3570 return 0;
3571 }
c3332e24 3572 }
af6bdddf 3573 else if (*base_string == REGISTER_PREFIX)
c3332e24 3574 {
af6bdddf 3575 as_bad (_("bad register name `%s'"), base_string);
24eab124 3576 return 0;
c3332e24 3577 }
24eab124
AM
3578 }
3579
3580 /* If there's an expression beginning the operand, parse it,
3581 assuming displacement_string_start and
3582 displacement_string_end are meaningful. */
3583 if (displacement_string_start != displacement_string_end)
3584 {
3585 if (!i386_displacement (displacement_string_start,
3586 displacement_string_end))
3587 return 0;
3588 }
3589
3590 /* Special case for (%dx) while doing input/output op. */
3591 if (i.base_reg
3592 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
3593 && i.index_reg == 0
3594 && i.log2_scale_factor == 0
3595 && i.seg[i.mem_operands] == 0
3596 && (i.types[this_operand] & Disp) == 0)
3597 {
3598 i.types[this_operand] = InOutPortReg;
3599 return 1;
3600 }
3601
eecb386c
AM
3602 if (i386_index_check (operand_string) == 0)
3603 return 0;
24eab124
AM
3604 i.mem_operands++;
3605 }
3606 else
3607 { /* it's not a memory operand; argh! */
3608 as_bad (_("invalid char %s beginning operand %d `%s'"),
3609 output_invalid (*op_string),
3610 this_operand + 1,
3611 op_string);
3612 return 0;
3613 }
3614 return 1; /* normal return */
252b5132
RH
3615}
3616\f
3617/*
24eab124 3618 * md_estimate_size_before_relax()
252b5132
RH
3619 *
3620 * Called just before relax().
3621 * Any symbol that is now undefined will not become defined.
3622 * Return the correct fr_subtype in the frag.
3623 * Return the initial "guess for fr_var" to caller.
3624 * The guess for fr_var is ACTUALLY the growth beyond fr_fix.
3625 * Whatever we do to grow fr_fix or fr_var contributes to our returned value.
3626 * Although it may not be explicit in the frag, pretend fr_var starts with a
3627 * 0 value.
3628 */
3629int
3630md_estimate_size_before_relax (fragP, segment)
3631 register fragS *fragP;
3632 register segT segment;
3633{
3634 register unsigned char *opcode;
3635 register int old_fr_fix;
3636
3637 old_fr_fix = fragP->fr_fix;
3638 opcode = (unsigned char *) fragP->fr_opcode;
3639 /* We've already got fragP->fr_subtype right; all we have to do is
3640 check for un-relaxable symbols. */
3641 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
3642 {
3643 /* symbol is undefined in this segment */
3644 int code16 = fragP->fr_subtype & CODE16;
3645 int size = code16 ? 2 : 4;
3646 int pcrel_reloc = code16 ? BFD_RELOC_16_PCREL : BFD_RELOC_32_PCREL;
3647
3648 switch (opcode[0])
3649 {
3650 case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */
3651 opcode[0] = 0xe9; /* dword disp jmp */
3652 fragP->fr_fix += size;
3653 fix_new (fragP, old_fr_fix, size,
3654 fragP->fr_symbol,
3655 fragP->fr_offset, 1,
3656 (GOT_symbol && /* Not quite right - we should switch on
3657 presence of @PLT, but I cannot see how
3658 to get to that from here. We should have
3659 done this in md_assemble to really
3660 get it right all of the time, but I
3661 think it does not matter that much, as
3662 this will be right most of the time. ERY*/
3663 S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)
3664 ? BFD_RELOC_386_PLT32 : pcrel_reloc);
3665 break;
3666
3667 default:
24eab124
AM
3668 /* This changes the byte-displacement jump 0x7N
3669 to the dword-displacement jump 0x0f8N. */
252b5132
RH
3670 opcode[1] = opcode[0] + 0x10;
3671 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */
3672 fragP->fr_fix += 1 + size; /* we've added an opcode byte */
3673 fix_new (fragP, old_fr_fix + 1, size,
3674 fragP->fr_symbol,
3675 fragP->fr_offset, 1,
3676 (GOT_symbol && /* Not quite right - we should switch on
24eab124
AM
3677 presence of @PLT, but I cannot see how
3678 to get to that from here. ERY */
252b5132
RH
3679 S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)
3680 ? BFD_RELOC_386_PLT32 : pcrel_reloc);
3681 break;
3682 }
3683 frag_wane (fragP);
3684 }
3685 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
3686} /* md_estimate_size_before_relax() */
3687\f
3688/*
3689 * md_convert_frag();
3690 *
3691 * Called after relax() is finished.
3692 * In: Address of frag.
3693 * fr_type == rs_machine_dependent.
3694 * fr_subtype is what the address relaxed to.
3695 *
3696 * Out: Any fixSs and constants are set up.
3697 * Caller will turn frag into a ".space 0".
3698 */
3699#ifndef BFD_ASSEMBLER
3700void
3701md_convert_frag (headers, sec, fragP)
a04b544b
ILT
3702 object_headers *headers ATTRIBUTE_UNUSED;
3703 segT sec ATTRIBUTE_UNUSED;
252b5132
RH
3704 register fragS *fragP;
3705#else
3706void
3707md_convert_frag (abfd, sec, fragP)
ab9da554
ILT
3708 bfd *abfd ATTRIBUTE_UNUSED;
3709 segT sec ATTRIBUTE_UNUSED;
252b5132
RH
3710 register fragS *fragP;
3711#endif
3712{
3713 register unsigned char *opcode;
3714 unsigned char *where_to_put_displacement = NULL;
3715 unsigned int target_address;
3716 unsigned int opcode_address;
3717 unsigned int extension = 0;
3718 int displacement_from_opcode_start;
3719
3720 opcode = (unsigned char *) fragP->fr_opcode;
3721
3722 /* Address we want to reach in file space. */
3723 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
3724#ifdef BFD_ASSEMBLER /* not needed otherwise? */
49309057 3725 target_address += symbol_get_frag (fragP->fr_symbol)->fr_address;
252b5132
RH
3726#endif
3727
3728 /* Address opcode resides at in file space. */
3729 opcode_address = fragP->fr_address + fragP->fr_fix;
3730
3731 /* Displacement from opcode start to fill into instruction. */
3732 displacement_from_opcode_start = target_address - opcode_address;
3733
3734 switch (fragP->fr_subtype)
3735 {
3736 case ENCODE_RELAX_STATE (COND_JUMP, SMALL):
3737 case ENCODE_RELAX_STATE (COND_JUMP, SMALL16):
3738 case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL):
3739 case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16):
3740 /* don't have to change opcode */
3741 extension = 1; /* 1 opcode + 1 displacement */
3742 where_to_put_displacement = &opcode[1];
3743 break;
3744
3745 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
3746 extension = 5; /* 2 opcode + 4 displacement */
3747 opcode[1] = opcode[0] + 0x10;
3748 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3749 where_to_put_displacement = &opcode[2];
3750 break;
3751
3752 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
3753 extension = 4; /* 1 opcode + 4 displacement */
3754 opcode[0] = 0xe9;
3755 where_to_put_displacement = &opcode[1];
3756 break;
3757
3758 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
3759 extension = 3; /* 2 opcode + 2 displacement */
3760 opcode[1] = opcode[0] + 0x10;
3761 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3762 where_to_put_displacement = &opcode[2];
3763 break;
3764
3765 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
3766 extension = 2; /* 1 opcode + 2 displacement */
3767 opcode[0] = 0xe9;
3768 where_to_put_displacement = &opcode[1];
3769 break;
3770
3771 default:
3772 BAD_CASE (fragP->fr_subtype);
3773 break;
3774 }
3775 /* now put displacement after opcode */
3776 md_number_to_chars ((char *) where_to_put_displacement,
3777 (valueT) (displacement_from_opcode_start - extension),
3778 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
3779 fragP->fr_fix += extension;
3780}
3781\f
3782
3783int md_short_jump_size = 2; /* size of byte displacement jmp */
3784int md_long_jump_size = 5; /* size of dword displacement jmp */
3785const int md_reloc_size = 8; /* Size of relocation record */
3786
3787void
3788md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3789 char *ptr;
3790 addressT from_addr, to_addr;
ab9da554
ILT
3791 fragS *frag ATTRIBUTE_UNUSED;
3792 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH
3793{
3794 long offset;
3795
3796 offset = to_addr - (from_addr + 2);
3797 md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */
3798 md_number_to_chars (ptr + 1, (valueT) offset, 1);
3799}
3800
3801void
3802md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3803 char *ptr;
3804 addressT from_addr, to_addr;
3805 fragS *frag;
3806 symbolS *to_symbol;
3807{
3808 long offset;
3809
3810 if (flag_do_long_jump)
3811 {
3812 offset = to_addr - S_GET_VALUE (to_symbol);
3813 md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */
3814 md_number_to_chars (ptr + 1, (valueT) offset, 4);
3815 fix_new (frag, (ptr + 1) - frag->fr_literal, 4,
3816 to_symbol, (offsetT) 0, 0, BFD_RELOC_32);
3817 }
3818 else
3819 {
3820 offset = to_addr - (from_addr + 5);
3821 md_number_to_chars (ptr, (valueT) 0xe9, 1);
3822 md_number_to_chars (ptr + 1, (valueT) offset, 4);
3823 }
3824}
3825\f
3826/* Apply a fixup (fixS) to segment data, once it has been determined
3827 by our caller that we have all the info we need to fix it up.
3828
3829 On the 386, immediates, displacements, and data pointers are all in
3830 the same (little-endian) format, so we don't need to care about which
3831 we are handling. */
3832
3833int
3834md_apply_fix3 (fixP, valp, seg)
3835 fixS *fixP; /* The fix we're to put in. */
3836 valueT *valp; /* Pointer to the value of the bits. */
a04b544b 3837 segT seg ATTRIBUTE_UNUSED; /* Segment fix is from. */
252b5132
RH
3838{
3839 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
3840 valueT value = *valp;
3841
e1b283bb 3842#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM
3843 if (fixP->fx_pcrel)
3844 {
3845 switch (fixP->fx_r_type)
3846 {
5865bb77
ILT
3847 default:
3848 break;
3849
93382f6d
AM
3850 case BFD_RELOC_32:
3851 fixP->fx_r_type = BFD_RELOC_32_PCREL;
3852 break;
3853 case BFD_RELOC_16:
3854 fixP->fx_r_type = BFD_RELOC_16_PCREL;
3855 break;
3856 case BFD_RELOC_8:
3857 fixP->fx_r_type = BFD_RELOC_8_PCREL;
3858 break;
3859 }
3860 }
252b5132 3861
0723899b
ILT
3862 /* This is a hack. There should be a better way to handle this.
3863 This covers for the fact that bfd_install_relocation will
3864 subtract the current location (for partial_inplace, PC relative
3865 relocations); see more below. */
93382f6d
AM
3866 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
3867 || fixP->fx_r_type == BFD_RELOC_16_PCREL
3868 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
3869 && fixP->fx_addsy)
252b5132
RH
3870 {
3871#ifndef OBJ_AOUT
3872 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
3873#ifdef TE_PE
3874 || OUTPUT_FLAVOR == bfd_target_coff_flavour
3875#endif
3876 )
3877 value += fixP->fx_where + fixP->fx_frag->fr_address;
3878#endif
3879#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 3880 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 3881 {
2f66722d
AM
3882 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
3883
3884 if ((fseg == seg
3885 || (symbol_section_p (fixP->fx_addsy)
3886 && fseg != absolute_section))
3887 && ! S_IS_EXTERNAL (fixP->fx_addsy)
3888 && ! S_IS_WEAK (fixP->fx_addsy)
3889 && S_IS_DEFINED (fixP->fx_addsy)
3890 && ! S_IS_COMMON (fixP->fx_addsy))
3891 {
3892 /* Yes, we add the values in twice. This is because
3893 bfd_perform_relocation subtracts them out again. I think
3894 bfd_perform_relocation is broken, but I don't dare change
3895 it. FIXME. */
3896 value += fixP->fx_where + fixP->fx_frag->fr_address;
3897 }
252b5132
RH
3898 }
3899#endif
3900#if defined (OBJ_COFF) && defined (TE_PE)
3901 /* For some reason, the PE format does not store a section
24eab124 3902 address offset for a PC relative symbol. */
252b5132
RH
3903 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
3904 value += md_pcrel_from (fixP);
c0c949c7
ILT
3905 else if (S_IS_EXTERNAL (fixP->fx_addsy)
3906 || S_IS_WEAK (fixP->fx_addsy))
3907 {
3908 /* We are generating an external relocation for this defined
3909 symbol. We add the address, because
3910 bfd_install_relocation will subtract it. VALUE already
3911 holds the symbol value, because fixup_segment added it
3912 in. We subtract it out, and then we subtract it out
3913 again because bfd_install_relocation will add it in
3914 again. */
3915 value += md_pcrel_from (fixP);
3916 value -= 2 * S_GET_VALUE (fixP->fx_addsy);
3917 }
252b5132
RH
3918#endif
3919 }
c0c949c7
ILT
3920#ifdef TE_PE
3921 else if (fixP->fx_addsy != NULL
3922 && S_IS_DEFINED (fixP->fx_addsy)
3923 && (S_IS_EXTERNAL (fixP->fx_addsy)
3924 || S_IS_WEAK (fixP->fx_addsy)))
3925 {
3926 /* We are generating an external relocation for this defined
3927 symbol. VALUE already holds the symbol value, and
3928 bfd_install_relocation will add it in again. We don't want
3929 either addition. */
3930 value -= 2 * S_GET_VALUE (fixP->fx_addsy);
3931 }
3932#endif
252b5132
RH
3933
3934 /* Fix a few things - the dynamic linker expects certain values here,
3935 and we must not dissappoint it. */
3936#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3937 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
3938 && fixP->fx_addsy)
3939 switch (fixP->fx_r_type) {
3940 case BFD_RELOC_386_PLT32:
3941 /* Make the jump instruction point to the address of the operand. At
3942 runtime we merely add the offset to the actual PLT entry. */
3943 value = 0xfffffffc;
3944 break;
3945 case BFD_RELOC_386_GOTPC:
3946/*
24eab124 3947 * This is tough to explain. We end up with this one if we have
252b5132
RH
3948 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
3949 * here is to obtain the absolute address of the GOT, and it is strongly
3950 * preferable from a performance point of view to avoid using a runtime
c3332e24 3951 * relocation for this. The actual sequence of instructions often look
252b5132 3952 * something like:
c3332e24 3953 *
24eab124 3954 * call .L66
252b5132 3955 * .L66:
24eab124
AM
3956 * popl %ebx
3957 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
c3332e24 3958 *
24eab124 3959 * The call and pop essentially return the absolute address of
252b5132
RH
3960 * the label .L66 and store it in %ebx. The linker itself will
3961 * ultimately change the first operand of the addl so that %ebx points to
3962 * the GOT, but to keep things simple, the .o file must have this operand
3963 * set so that it generates not the absolute address of .L66, but the
3964 * absolute address of itself. This allows the linker itself simply
3965 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
3966 * added in, and the addend of the relocation is stored in the operand
3967 * field for the instruction itself.
c3332e24 3968 *
24eab124 3969 * Our job here is to fix the operand so that it would add the correct
252b5132
RH
3970 * offset so that %ebx would point to itself. The thing that is tricky is
3971 * that .-.L66 will point to the beginning of the instruction, so we need
3972 * to further modify the operand so that it will point to itself.
3973 * There are other cases where you have something like:
c3332e24 3974 *
24eab124 3975 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
c3332e24 3976 *
252b5132 3977 * and here no correction would be required. Internally in the assembler
c3332e24 3978 * we treat operands of this form as not being pcrel since the '.' is
252b5132
RH
3979 * explicitly mentioned, and I wonder whether it would simplify matters
3980 * to do it this way. Who knows. In earlier versions of the PIC patches,
3981 * the pcrel_adjust field was used to store the correction, but since the
3982 * expression is not pcrel, I felt it would be confusing to do it this way.
3983 */
3984 value -= 1;
3985 break;
3986 case BFD_RELOC_386_GOT32:
24eab124 3987 value = 0; /* Fully resolved at runtime. No addend. */
252b5132
RH
3988 break;
3989 case BFD_RELOC_386_GOTOFF:
3990 break;
3991
3992 case BFD_RELOC_VTABLE_INHERIT:
3993 case BFD_RELOC_VTABLE_ENTRY:
3994 fixP->fx_done = 0;
3995 return 1;
3996
3997 default:
3998 break;
3999 }
93382f6d
AM
4000#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4001 *valp = value;
4002#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
252b5132
RH
4003 md_number_to_chars (p, value, fixP->fx_size);
4004
4005 return 1;
4006}
4007
4008#if 0
4009/* This is never used. */
4010long /* Knows about the byte order in a word. */
4011md_chars_to_number (con, nbytes)
4012 unsigned char con[]; /* Low order byte 1st. */
4013 int nbytes; /* Number of bytes in the input. */
4014{
4015 long retval;
4016 for (retval = 0, con += nbytes - 1; nbytes--; con--)
4017 {
4018 retval <<= BITS_PER_CHAR;
4019 retval |= *con;
4020 }
4021 return retval;
4022}
4023#endif /* 0 */
4024\f
4025
4026#define MAX_LITTLENUMS 6
4027
4028/* Turn the string pointed to by litP into a floating point constant of type
4029 type, and emit the appropriate bytes. The number of LITTLENUMS emitted
4030 is stored in *sizeP . An error message is returned, or NULL on OK. */
4031char *
4032md_atof (type, litP, sizeP)
2ab9b79e 4033 int type;
252b5132
RH
4034 char *litP;
4035 int *sizeP;
4036{
4037 int prec;
4038 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4039 LITTLENUM_TYPE *wordP;
4040 char *t;
4041
4042 switch (type)
4043 {
4044 case 'f':
4045 case 'F':
4046 prec = 2;
4047 break;
4048
4049 case 'd':
4050 case 'D':
4051 prec = 4;
4052 break;
4053
4054 case 'x':
4055 case 'X':
4056 prec = 5;
4057 break;
4058
4059 default:
4060 *sizeP = 0;
4061 return _("Bad call to md_atof ()");
4062 }
4063 t = atof_ieee (input_line_pointer, type, words);
4064 if (t)
4065 input_line_pointer = t;
4066
4067 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4068 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4069 the bigendian 386. */
4070 for (wordP = words + prec - 1; prec--;)
4071 {
4072 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4073 litP += sizeof (LITTLENUM_TYPE);
4074 }
4075 return 0;
4076}
4077\f
4078char output_invalid_buf[8];
4079
4080static char * output_invalid PARAMS ((int));
4081
4082static char *
4083output_invalid (c)
4084 int c;
4085{
4086 if (isprint (c))
4087 sprintf (output_invalid_buf, "'%c'", c);
4088 else
4089 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4090 return output_invalid_buf;
4091}
4092
252b5132 4093
af6bdddf 4094/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH
4095
4096static const reg_entry *
4097parse_register (reg_string, end_op)
4098 char *reg_string;
4099 char **end_op;
4100{
af6bdddf
AM
4101 char *s = reg_string;
4102 char *p;
252b5132
RH
4103 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4104 const reg_entry *r;
4105
4106 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4107 if (*s == REGISTER_PREFIX)
4108 ++s;
4109
4110 if (is_space_char (*s))
4111 ++s;
4112
4113 p = reg_name_given;
af6bdddf 4114 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH
4115 {
4116 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM
4117 return (const reg_entry *) NULL;
4118 s++;
252b5132
RH
4119 }
4120
af6bdddf 4121 *end_op = s;
252b5132
RH
4122
4123 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4124
5f47d35b
AM
4125 /* Handle floating point regs, allowing spaces in the (i) part. */
4126 if (r == i386_regtab /* %st is first entry of table */)
4127 {
5f47d35b
AM
4128 if (is_space_char (*s))
4129 ++s;
4130 if (*s == '(')
4131 {
af6bdddf 4132 ++s;
5f47d35b
AM
4133 if (is_space_char (*s))
4134 ++s;
4135 if (*s >= '0' && *s <= '7')
4136 {
4137 r = &i386_float_regtab[*s - '0'];
af6bdddf 4138 ++s;
5f47d35b
AM
4139 if (is_space_char (*s))
4140 ++s;
4141 if (*s == ')')
4142 {
4143 *end_op = s + 1;
4144 return r;
4145 }
5f47d35b 4146 }
af6bdddf 4147 /* We have "%st(" then garbage */
5f47d35b
AM
4148 return (const reg_entry *) NULL;
4149 }
4150 }
4151
252b5132
RH
4152 return r;
4153}
4154\f
4cc782b5
ILT
4155#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4156CONST char *md_shortopts = "kmVQ:sq";
252b5132
RH
4157#else
4158CONST char *md_shortopts = "m";
4159#endif
4160struct option md_longopts[] = {
4161 {NULL, no_argument, NULL, 0}
4162};
4163size_t md_longopts_size = sizeof (md_longopts);
4164
4165int
4166md_parse_option (c, arg)
4167 int c;
ab9da554 4168 char *arg ATTRIBUTE_UNUSED;
252b5132
RH
4169{
4170 switch (c)
4171 {
4172 case 'm':
4173 flag_do_long_jump = 1;
4174 break;
4175
4176#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4177 /* -k: Ignore for FreeBSD compatibility. */
4178 case 'k':
4179 break;
4180
4181 /* -V: SVR4 argument to print version ID. */
4182 case 'V':
4183 print_version_id ();
4184 break;
4185
4186 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4187 should be emitted or not. FIXME: Not implemented. */
4188 case 'Q':
4189 break;
4cc782b5
ILT
4190
4191 case 's':
4192 /* -s: On i386 Solaris, this tells the native assembler to use
4193 .stab instead of .stab.excl. We always use .stab anyhow. */
4194 break;
4195
4196 case 'q':
4197 /* -q: On i386 Solaris, this tells the native assembler does
4198 fewer checks. */
4199 break;
252b5132
RH
4200#endif
4201
4202 default:
4203 return 0;
4204 }
4205 return 1;
4206}
4207
4208void
4209md_show_usage (stream)
4210 FILE *stream;
4211{
4212 fprintf (stream, _("\
4cc782b5
ILT
4213 -m do long jump\n"));
4214#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4215 fprintf (stream, _("\
4216 -V print assembler version number\n\
4217 -k ignored\n\
4218 -Qy, -Qn ignored\n\
4219 -q ignored\n\
4220 -s ignored\n"));
4221#endif
252b5132
RH
4222}
4223
4224#ifdef BFD_ASSEMBLER
4c63da97
AM
4225#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
4226 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
4227 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
252b5132
RH
4228
4229/* Pick the target format to use. */
4230
4231const char *
4232i386_target_format ()
4233{
4234 switch (OUTPUT_FLAVOR)
4235 {
4c63da97
AM
4236#ifdef OBJ_MAYBE_AOUT
4237 case bfd_target_aout_flavour:
4238 return AOUT_TARGET_FORMAT;
4239#endif
4240#ifdef OBJ_MAYBE_COFF
252b5132
RH
4241 case bfd_target_coff_flavour:
4242 return "coff-i386";
4c63da97
AM
4243#endif
4244#ifdef OBJ_MAYBE_ELF
252b5132
RH
4245 case bfd_target_elf_flavour:
4246 return "elf32-i386";
4c63da97 4247#endif
252b5132
RH
4248 default:
4249 abort ();
4250 return NULL;
4251 }
4252}
4253
4c63da97 4254#endif /* OBJ_MAYBE_ more than one */
252b5132
RH
4255#endif /* BFD_ASSEMBLER */
4256\f
252b5132
RH
4257symbolS *
4258md_undefined_symbol (name)
4259 char *name;
4260{
18dc2407
ILT
4261 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4262 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4263 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4264 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM
4265 {
4266 if (!GOT_symbol)
4267 {
4268 if (symbol_find (name))
4269 as_bad (_("GOT already in symbol table"));
4270 GOT_symbol = symbol_new (name, undefined_section,
4271 (valueT) 0, &zero_address_frag);
4272 };
4273 return GOT_symbol;
4274 }
252b5132
RH
4275 return 0;
4276}
4277
4278/* Round up a section size to the appropriate boundary. */
4279valueT
4280md_section_align (segment, size)
ab9da554 4281 segT segment ATTRIBUTE_UNUSED;
252b5132
RH
4282 valueT size;
4283{
252b5132 4284#ifdef BFD_ASSEMBLER
4c63da97
AM
4285#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4286 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4287 {
4288 /* For a.out, force the section size to be aligned. If we don't do
4289 this, BFD will align it for us, but it will not write out the
4290 final bytes of the section. This may be a bug in BFD, but it is
4291 easier to fix it here since that is how the other a.out targets
4292 work. */
4293 int align;
4294
4295 align = bfd_get_section_alignment (stdoutput, segment);
4296 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4297 }
252b5132
RH
4298#endif
4299#endif
4300
4301 return size;
4302}
4303
4304/* On the i386, PC-relative offsets are relative to the start of the
4305 next instruction. That is, the address of the offset, plus its
4306 size, since the offset is always the last part of the insn. */
4307
4308long
4309md_pcrel_from (fixP)
4310 fixS *fixP;
4311{
4312 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
4313}
4314
4315#ifndef I386COFF
4316
4317static void
4318s_bss (ignore)
ab9da554 4319 int ignore ATTRIBUTE_UNUSED;
252b5132
RH
4320{
4321 register int temp;
4322
4323 temp = get_absolute_expression ();
4324 subseg_set (bss_section, (subsegT) temp);
4325 demand_empty_rest_of_line ();
4326}
4327
4328#endif
4329
4330
4331#ifdef BFD_ASSEMBLER
4332
4333void
4334i386_validate_fix (fixp)
4335 fixS *fixp;
4336{
4337 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
4338 {
4339 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
4340 fixp->fx_subsy = 0;
4341 }
4342}
4343
252b5132
RH
4344arelent *
4345tc_gen_reloc (section, fixp)
ab9da554 4346 asection *section ATTRIBUTE_UNUSED;
252b5132
RH
4347 fixS *fixp;
4348{
4349 arelent *rel;
4350 bfd_reloc_code_real_type code;
4351
4352 switch (fixp->fx_r_type)
4353 {
4354 case BFD_RELOC_386_PLT32:
4355 case BFD_RELOC_386_GOT32:
4356 case BFD_RELOC_386_GOTOFF:
4357 case BFD_RELOC_386_GOTPC:
4358 case BFD_RELOC_RVA:
4359 case BFD_RELOC_VTABLE_ENTRY:
4360 case BFD_RELOC_VTABLE_INHERIT:
4361 code = fixp->fx_r_type;
4362 break;
4363 default:
93382f6d 4364 if (fixp->fx_pcrel)
252b5132 4365 {
93382f6d
AM
4366 switch (fixp->fx_size)
4367 {
4368 default:
4369 as_bad (_("Can not do %d byte pc-relative relocation"),
4370 fixp->fx_size);
4371 code = BFD_RELOC_32_PCREL;
4372 break;
4373 case 1: code = BFD_RELOC_8_PCREL; break;
4374 case 2: code = BFD_RELOC_16_PCREL; break;
4375 case 4: code = BFD_RELOC_32_PCREL; break;
4376 }
4377 }
4378 else
4379 {
4380 switch (fixp->fx_size)
4381 {
4382 default:
4383 as_bad (_("Can not do %d byte relocation"), fixp->fx_size);
4384 code = BFD_RELOC_32;
4385 break;
4386 case 1: code = BFD_RELOC_8; break;
4387 case 2: code = BFD_RELOC_16; break;
4388 case 4: code = BFD_RELOC_32; break;
4389 }
252b5132
RH
4390 }
4391 break;
4392 }
252b5132
RH
4393
4394 if (code == BFD_RELOC_32
4395 && GOT_symbol
4396 && fixp->fx_addsy == GOT_symbol)
4397 code = BFD_RELOC_386_GOTPC;
4398
4399 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT
4400 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
4401 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH
4402
4403 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
4404 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4405 vtable entry to be used in the relocation's section offset. */
4406 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4407 rel->address = fixp->fx_offset;
4408
4409 if (fixp->fx_pcrel)
4410 rel->addend = fixp->fx_addnumber;
4411 else
4412 rel->addend = 0;
4413
4414 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
4415 if (rel->howto == NULL)
4416 {
4417 as_bad_where (fixp->fx_file, fixp->fx_line,
4418 _("Cannot represent relocation type %s"),
4419 bfd_get_reloc_code_name (code));
4420 /* Set howto to a garbage value so that we can keep going. */
4421 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
4422 assert (rel->howto != NULL);
4423 }
4424
4425 return rel;
4426}
4427
4428#else /* ! BFD_ASSEMBLER */
4429
4430#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4431void
4432tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4433 char *where;
4434 fixS *fixP;
4435 relax_addressT segment_address_in_file;
4436{
4437 /*
4438 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4439 * Out: GNU LD relocation length code: 0, 1, or 2.
4440 */
4441
4442 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4443 long r_symbolnum;
4444
4445 know (fixP->fx_addsy != NULL);
4446
4447 md_number_to_chars (where,
4448 (valueT) (fixP->fx_frag->fr_address
4449 + fixP->fx_where - segment_address_in_file),
4450 4);
4451
4452 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4453 ? S_GET_TYPE (fixP->fx_addsy)
4454 : fixP->fx_addsy->sy_number);
4455
4456 where[6] = (r_symbolnum >> 16) & 0x0ff;
4457 where[5] = (r_symbolnum >> 8) & 0x0ff;
4458 where[4] = r_symbolnum & 0x0ff;
4459 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
4460 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
4461 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
4462}
4463
4464#endif /* OBJ_AOUT or OBJ_BOUT */
4465
4466#if defined (I386COFF)
4467
4468short
4469tc_coff_fix2rtype (fixP)
4470 fixS *fixP;
4471{
4472 if (fixP->fx_r_type == R_IMAGEBASE)
4473 return R_IMAGEBASE;
4474
4475 return (fixP->fx_pcrel ?
4476 (fixP->fx_size == 1 ? R_PCRBYTE :
4477 fixP->fx_size == 2 ? R_PCRWORD :
4478 R_PCRLONG) :
4479 (fixP->fx_size == 1 ? R_RELBYTE :
4480 fixP->fx_size == 2 ? R_RELWORD :
4481 R_DIR32));
4482}
4483
4484int
4485tc_coff_sizemachdep (frag)
4486 fragS *frag;
4487{
4488 if (frag->fr_next)
4489 return (frag->fr_next->fr_address - frag->fr_address);
4490 else
4491 return 0;
4492}
4493
4494#endif /* I386COFF */
4495
93382f6d 4496#endif /* ! BFD_ASSEMBLER */
252b5132
RH
4497\f
4498/* end of tc-i386.c */
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