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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
219d1afa | 2 | Copyright (C) 1989-2018 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 68 | #define LOCK_PREFIX 5 |
4e9ac44a L |
69 | #define REX_PREFIX 6 /* must come last. */ |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
84 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
85 | in instructions. */ | |
86 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
87 | ||
88 | #define END_OF_INSN '\0' | |
89 | ||
90 | /* | |
91 | 'templates' is for grouping together 'template' structures for opcodes | |
92 | of the same name. This is only used for storing the insns in the grand | |
93 | ole hash table of insns. | |
94 | The templates themselves start at START and range up to (but not including) | |
95 | END. | |
96 | */ | |
97 | typedef struct | |
98 | { | |
d3ce72d0 NC |
99 | const insn_template *start; |
100 | const insn_template *end; | |
6305a203 L |
101 | } |
102 | templates; | |
103 | ||
104 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
105 | typedef struct | |
106 | { | |
107 | unsigned int regmem; /* codes register or memory operand */ | |
108 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
109 | unsigned int mode; /* how to interpret regmem & reg */ | |
110 | } | |
111 | modrm_byte; | |
112 | ||
113 | /* x86-64 extension prefix. */ | |
114 | typedef int rex_byte; | |
115 | ||
6305a203 L |
116 | /* 386 opcode byte to code indirect addressing. */ |
117 | typedef struct | |
118 | { | |
119 | unsigned base; | |
120 | unsigned index; | |
121 | unsigned scale; | |
122 | } | |
123 | sib_byte; | |
124 | ||
6305a203 L |
125 | /* x86 arch names, types and features */ |
126 | typedef struct | |
127 | { | |
128 | const char *name; /* arch name */ | |
8a2c8fef | 129 | unsigned int len; /* arch string length */ |
6305a203 L |
130 | enum processor_type type; /* arch type */ |
131 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 132 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
133 | } |
134 | arch_entry; | |
135 | ||
293f5f65 L |
136 | /* Used to turn off indicated flags. */ |
137 | typedef struct | |
138 | { | |
139 | const char *name; /* arch name */ | |
140 | unsigned int len; /* arch string length */ | |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
142 | } | |
143 | noarch_entry; | |
144 | ||
78f12dd3 | 145 | static void update_code_flag (int, int); |
e3bb37b5 L |
146 | static void set_code_flag (int); |
147 | static void set_16bit_gcc_code_flag (int); | |
148 | static void set_intel_syntax (int); | |
1efbbeb4 | 149 | static void set_intel_mnemonic (int); |
db51cc60 | 150 | static void set_allow_index_reg (int); |
7bab8ab5 | 151 | static void set_check (int); |
e3bb37b5 | 152 | static void set_cpu_arch (int); |
6482c264 | 153 | #ifdef TE_PE |
e3bb37b5 | 154 | static void pe_directive_secrel (int); |
6482c264 | 155 | #endif |
e3bb37b5 L |
156 | static void signed_cons (int); |
157 | static char *output_invalid (int c); | |
ee86248c JB |
158 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
159 | const char *); | |
160 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
161 | const char *); | |
a7619375 | 162 | static int i386_att_operand (char *); |
e3bb37b5 | 163 | static int i386_intel_operand (char *, int); |
ee86248c JB |
164 | static int i386_intel_simplify (expressionS *); |
165 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
166 | static const reg_entry *parse_register (char *, char **); |
167 | static char *parse_insn (char *, char *); | |
168 | static char *parse_operands (char *, const char *); | |
169 | static void swap_operands (void); | |
4d456e3d | 170 | static void swap_2_operands (int, int); |
e3bb37b5 L |
171 | static void optimize_imm (void); |
172 | static void optimize_disp (void); | |
83b16ac6 | 173 | static const insn_template *match_template (char); |
e3bb37b5 L |
174 | static int check_string (void); |
175 | static int process_suffix (void); | |
176 | static int check_byte_reg (void); | |
177 | static int check_long_reg (void); | |
178 | static int check_qword_reg (void); | |
179 | static int check_word_reg (void); | |
180 | static int finalize_imm (void); | |
181 | static int process_operands (void); | |
182 | static const seg_entry *build_modrm_byte (void); | |
183 | static void output_insn (void); | |
184 | static void output_imm (fragS *, offsetT); | |
185 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 186 | #ifndef I386COFF |
e3bb37b5 | 187 | static void s_bss (int); |
252b5132 | 188 | #endif |
17d4e2a2 L |
189 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
190 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
191 | #endif | |
252b5132 | 192 | |
a847613f | 193 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 194 | |
43234a1e L |
195 | /* This struct describes rounding control and SAE in the instruction. */ |
196 | struct RC_Operation | |
197 | { | |
198 | enum rc_type | |
199 | { | |
200 | rne = 0, | |
201 | rd, | |
202 | ru, | |
203 | rz, | |
204 | saeonly | |
205 | } type; | |
206 | int operand; | |
207 | }; | |
208 | ||
209 | static struct RC_Operation rc_op; | |
210 | ||
211 | /* The struct describes masking, applied to OPERAND in the instruction. | |
212 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
213 | whether merging or zeroing mask is used. */ | |
214 | struct Mask_Operation | |
215 | { | |
216 | const reg_entry *mask; | |
217 | unsigned int zeroing; | |
218 | /* The operand where this operation is associated. */ | |
219 | int operand; | |
220 | }; | |
221 | ||
222 | static struct Mask_Operation mask_op; | |
223 | ||
224 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
225 | broadcast factor. */ | |
226 | struct Broadcast_Operation | |
227 | { | |
8e6e0792 | 228 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
229 | int type; |
230 | ||
231 | /* Index of broadcasted operand. */ | |
232 | int operand; | |
4a1b91ea L |
233 | |
234 | /* Number of bytes to broadcast. */ | |
235 | int bytes; | |
43234a1e L |
236 | }; |
237 | ||
238 | static struct Broadcast_Operation broadcast_op; | |
239 | ||
c0f3af97 L |
240 | /* VEX prefix. */ |
241 | typedef struct | |
242 | { | |
43234a1e L |
243 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
244 | unsigned char bytes[4]; | |
c0f3af97 L |
245 | unsigned int length; |
246 | /* Destination or source register specifier. */ | |
247 | const reg_entry *register_specifier; | |
248 | } vex_prefix; | |
249 | ||
252b5132 | 250 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 251 | i386_insn. */ |
252b5132 | 252 | |
520dc8e8 AM |
253 | union i386_op |
254 | { | |
255 | expressionS *disps; | |
256 | expressionS *imms; | |
257 | const reg_entry *regs; | |
258 | }; | |
259 | ||
a65babc9 L |
260 | enum i386_error |
261 | { | |
86e026a4 | 262 | operand_size_mismatch, |
a65babc9 L |
263 | operand_type_mismatch, |
264 | register_type_mismatch, | |
265 | number_of_operands_mismatch, | |
266 | invalid_instruction_suffix, | |
267 | bad_imm4, | |
a65babc9 L |
268 | unsupported_with_intel_mnemonic, |
269 | unsupported_syntax, | |
6c30d220 L |
270 | unsupported, |
271 | invalid_vsib_address, | |
7bab8ab5 | 272 | invalid_vector_register_set, |
43234a1e L |
273 | unsupported_vector_index_register, |
274 | unsupported_broadcast, | |
43234a1e L |
275 | broadcast_needed, |
276 | unsupported_masking, | |
277 | mask_not_on_destination, | |
278 | no_default_mask, | |
279 | unsupported_rc_sae, | |
280 | rc_sae_operand_not_last_imm, | |
281 | invalid_register_operand, | |
a65babc9 L |
282 | }; |
283 | ||
252b5132 RH |
284 | struct _i386_insn |
285 | { | |
47926f60 | 286 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 287 | insn_template tm; |
252b5132 | 288 | |
7d5e4556 L |
289 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
290 | or qword, if given. */ | |
252b5132 RH |
291 | char suffix; |
292 | ||
47926f60 | 293 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
294 | unsigned int operands; |
295 | ||
296 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
297 | of given register, displacement, memory operands and immediate | |
47926f60 | 298 | operands. */ |
252b5132 RH |
299 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
300 | ||
301 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 302 | use OP[i] for the corresponding operand. */ |
40fb9820 | 303 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 304 | |
520dc8e8 AM |
305 | /* Displacement expression, immediate expression, or register for each |
306 | operand. */ | |
307 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 308 | |
3e73aa7c JH |
309 | /* Flags for operands. */ |
310 | unsigned int flags[MAX_OPERANDS]; | |
311 | #define Operand_PCrel 1 | |
312 | ||
252b5132 | 313 | /* Relocation type for operand */ |
f86103b7 | 314 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 315 | |
252b5132 RH |
316 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
317 | the base index byte below. */ | |
318 | const reg_entry *base_reg; | |
319 | const reg_entry *index_reg; | |
320 | unsigned int log2_scale_factor; | |
321 | ||
322 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 323 | explicit segment overrides are given. */ |
ce8a8b2f | 324 | const seg_entry *seg[2]; |
252b5132 | 325 | |
8325cc63 JB |
326 | /* Copied first memory operand string, for re-checking. */ |
327 | char *memop1_string; | |
328 | ||
252b5132 RH |
329 | /* PREFIX holds all the given prefix opcodes (usually null). |
330 | PREFIXES is the number of prefix opcodes. */ | |
331 | unsigned int prefixes; | |
332 | unsigned char prefix[MAX_PREFIXES]; | |
333 | ||
334 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 335 | addressing modes of this insn are encoded. */ |
252b5132 | 336 | modrm_byte rm; |
3e73aa7c | 337 | rex_byte rex; |
43234a1e | 338 | rex_byte vrex; |
252b5132 | 339 | sib_byte sib; |
c0f3af97 | 340 | vex_prefix vex; |
b6169b20 | 341 | |
43234a1e L |
342 | /* Masking attributes. */ |
343 | struct Mask_Operation *mask; | |
344 | ||
345 | /* Rounding control and SAE attributes. */ | |
346 | struct RC_Operation *rounding; | |
347 | ||
348 | /* Broadcasting attributes. */ | |
349 | struct Broadcast_Operation *broadcast; | |
350 | ||
351 | /* Compressed disp8*N attribute. */ | |
352 | unsigned int memshift; | |
353 | ||
86fa6981 L |
354 | /* Prefer load or store in encoding. */ |
355 | enum | |
356 | { | |
357 | dir_encoding_default = 0, | |
358 | dir_encoding_load, | |
359 | dir_encoding_store | |
360 | } dir_encoding; | |
891edac4 | 361 | |
a501d77e L |
362 | /* Prefer 8bit or 32bit displacement in encoding. */ |
363 | enum | |
364 | { | |
365 | disp_encoding_default = 0, | |
366 | disp_encoding_8bit, | |
367 | disp_encoding_32bit | |
368 | } disp_encoding; | |
f8a5c266 | 369 | |
6b6b6807 L |
370 | /* Prefer the REX byte in encoding. */ |
371 | bfd_boolean rex_encoding; | |
372 | ||
b6f8c7c4 L |
373 | /* Disable instruction size optimization. */ |
374 | bfd_boolean no_optimize; | |
375 | ||
86fa6981 L |
376 | /* How to encode vector instructions. */ |
377 | enum | |
378 | { | |
379 | vex_encoding_default = 0, | |
380 | vex_encoding_vex2, | |
381 | vex_encoding_vex3, | |
382 | vex_encoding_evex | |
383 | } vec_encoding; | |
384 | ||
d5de92cf L |
385 | /* REP prefix. */ |
386 | const char *rep_prefix; | |
387 | ||
165de32a L |
388 | /* HLE prefix. */ |
389 | const char *hle_prefix; | |
42164a71 | 390 | |
7e8b059b L |
391 | /* Have BND prefix. */ |
392 | const char *bnd_prefix; | |
393 | ||
04ef582a L |
394 | /* Have NOTRACK prefix. */ |
395 | const char *notrack_prefix; | |
396 | ||
891edac4 | 397 | /* Error message. */ |
a65babc9 | 398 | enum i386_error error; |
252b5132 RH |
399 | }; |
400 | ||
401 | typedef struct _i386_insn i386_insn; | |
402 | ||
43234a1e L |
403 | /* Link RC type with corresponding string, that'll be looked for in |
404 | asm. */ | |
405 | struct RC_name | |
406 | { | |
407 | enum rc_type type; | |
408 | const char *name; | |
409 | unsigned int len; | |
410 | }; | |
411 | ||
412 | static const struct RC_name RC_NamesTable[] = | |
413 | { | |
414 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
415 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
416 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
417 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
418 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
419 | }; | |
420 | ||
252b5132 RH |
421 | /* List of chars besides those in app.c:symbol_chars that can start an |
422 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 423 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 424 | #ifdef LEX_AT |
32137342 NC |
425 | "@" |
426 | #endif | |
427 | #ifdef LEX_QM | |
428 | "?" | |
252b5132 | 429 | #endif |
32137342 | 430 | ; |
252b5132 | 431 | |
29b0f896 AM |
432 | #if (defined (TE_I386AIX) \ |
433 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 434 | && !defined (TE_GNU) \ |
29b0f896 | 435 | && !defined (TE_LINUX) \ |
8d63c93e | 436 | && !defined (TE_NACL) \ |
29b0f896 | 437 | && !defined (TE_FreeBSD) \ |
5b806d27 | 438 | && !defined (TE_DragonFly) \ |
29b0f896 | 439 | && !defined (TE_NetBSD))) |
252b5132 | 440 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
441 | pre-processor is disabled, these aren't very useful. The option |
442 | --divide will remove '/' from this list. */ | |
443 | const char *i386_comment_chars = "#/"; | |
444 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 445 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 446 | |
b3b91714 AM |
447 | #else |
448 | const char *i386_comment_chars = "#"; | |
449 | #define PREFIX_SEPARATOR '/' | |
450 | #endif | |
451 | ||
252b5132 RH |
452 | /* This array holds the chars that only start a comment at the beginning of |
453 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
454 | .line and .file directives will appear in the pre-processed output. |
455 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 456 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
457 | #NO_APP at the beginning of its output. |
458 | Also note that comments started like this one will always work if | |
252b5132 | 459 | '/' isn't otherwise defined. */ |
b3b91714 | 460 | const char line_comment_chars[] = "#/"; |
252b5132 | 461 | |
63a0b638 | 462 | const char line_separator_chars[] = ";"; |
252b5132 | 463 | |
ce8a8b2f AM |
464 | /* Chars that can be used to separate mant from exp in floating point |
465 | nums. */ | |
252b5132 RH |
466 | const char EXP_CHARS[] = "eE"; |
467 | ||
ce8a8b2f AM |
468 | /* Chars that mean this number is a floating point constant |
469 | As in 0f12.456 | |
470 | or 0d1.2345e12. */ | |
252b5132 RH |
471 | const char FLT_CHARS[] = "fFdDxX"; |
472 | ||
ce8a8b2f | 473 | /* Tables for lexical analysis. */ |
252b5132 RH |
474 | static char mnemonic_chars[256]; |
475 | static char register_chars[256]; | |
476 | static char operand_chars[256]; | |
477 | static char identifier_chars[256]; | |
478 | static char digit_chars[256]; | |
479 | ||
ce8a8b2f | 480 | /* Lexical macros. */ |
252b5132 RH |
481 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
482 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
483 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
484 | #define is_space_char(x) ((x) == ' ') | |
485 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
486 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
487 | ||
0234cb7c | 488 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
489 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
490 | ||
491 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
492 | effect this we maintain a stack of saved characters that we've smashed | |
493 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 494 | assembler instruction). */ |
252b5132 | 495 | static char save_stack[32]; |
ce8a8b2f | 496 | static char *save_stack_p; |
252b5132 RH |
497 | #define END_STRING_AND_SAVE(s) \ |
498 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
499 | #define RESTORE_END_STRING(s) \ | |
500 | do { *(s) = *--save_stack_p; } while (0) | |
501 | ||
47926f60 | 502 | /* The instruction we're assembling. */ |
252b5132 RH |
503 | static i386_insn i; |
504 | ||
505 | /* Possible templates for current insn. */ | |
506 | static const templates *current_templates; | |
507 | ||
31b2323c L |
508 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
509 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
510 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 511 | |
47926f60 | 512 | /* Current operand we are working on. */ |
ee86248c | 513 | static int this_operand = -1; |
252b5132 | 514 | |
3e73aa7c JH |
515 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
516 | these. */ | |
517 | ||
518 | enum flag_code { | |
519 | CODE_32BIT, | |
520 | CODE_16BIT, | |
521 | CODE_64BIT }; | |
522 | ||
523 | static enum flag_code flag_code; | |
4fa24527 | 524 | static unsigned int object_64bit; |
862be3fb | 525 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
526 | static int use_rela_relocations = 0; |
527 | ||
7af8ed2d NC |
528 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
529 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
530 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
531 | ||
351f65ca L |
532 | /* The ELF ABI to use. */ |
533 | enum x86_elf_abi | |
534 | { | |
535 | I386_ABI, | |
7f56bc95 L |
536 | X86_64_ABI, |
537 | X86_64_X32_ABI | |
351f65ca L |
538 | }; |
539 | ||
540 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 541 | #endif |
351f65ca | 542 | |
167ad85b TG |
543 | #if defined (TE_PE) || defined (TE_PEP) |
544 | /* Use big object file format. */ | |
545 | static int use_big_obj = 0; | |
546 | #endif | |
547 | ||
8dcea932 L |
548 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
549 | /* 1 if generating code for a shared library. */ | |
550 | static int shared = 0; | |
551 | #endif | |
552 | ||
47926f60 KH |
553 | /* 1 for intel syntax, |
554 | 0 if att syntax. */ | |
555 | static int intel_syntax = 0; | |
252b5132 | 556 | |
e89c5eaa L |
557 | /* 1 for Intel64 ISA, |
558 | 0 if AMD64 ISA. */ | |
559 | static int intel64; | |
560 | ||
1efbbeb4 L |
561 | /* 1 for intel mnemonic, |
562 | 0 if att mnemonic. */ | |
563 | static int intel_mnemonic = !SYSV386_COMPAT; | |
564 | ||
a60de03c JB |
565 | /* 1 if pseudo registers are permitted. */ |
566 | static int allow_pseudo_reg = 0; | |
567 | ||
47926f60 KH |
568 | /* 1 if register prefix % not required. */ |
569 | static int allow_naked_reg = 0; | |
252b5132 | 570 | |
33eaf5de | 571 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
572 | instructions supporting it, even if this prefix wasn't specified |
573 | explicitly. */ | |
574 | static int add_bnd_prefix = 0; | |
575 | ||
ba104c83 | 576 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
577 | static int allow_index_reg = 0; |
578 | ||
d022bddd IT |
579 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
580 | specified explicitly. */ | |
581 | static int omit_lock_prefix = 0; | |
582 | ||
e4e00185 AS |
583 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
584 | "lock addl $0, (%{re}sp)". */ | |
585 | static int avoid_fence = 0; | |
586 | ||
0cb4071e L |
587 | /* 1 if the assembler should generate relax relocations. */ |
588 | ||
589 | static int generate_relax_relocations | |
590 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
591 | ||
7bab8ab5 | 592 | static enum check_kind |
daf50ae7 | 593 | { |
7bab8ab5 JB |
594 | check_none = 0, |
595 | check_warning, | |
596 | check_error | |
daf50ae7 | 597 | } |
7bab8ab5 | 598 | sse_check, operand_check = check_warning; |
daf50ae7 | 599 | |
b6f8c7c4 L |
600 | /* Optimization: |
601 | 1. Clear the REX_W bit with register operand if possible. | |
602 | 2. Above plus use 128bit vector instruction to clear the full vector | |
603 | register. | |
604 | */ | |
605 | static int optimize = 0; | |
606 | ||
607 | /* Optimization: | |
608 | 1. Clear the REX_W bit with register operand if possible. | |
609 | 2. Above plus use 128bit vector instruction to clear the full vector | |
610 | register. | |
611 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
612 | "testb $imm7,%r8". | |
613 | */ | |
614 | static int optimize_for_space = 0; | |
615 | ||
2ca3ace5 L |
616 | /* Register prefix used for error message. */ |
617 | static const char *register_prefix = "%"; | |
618 | ||
47926f60 KH |
619 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
620 | leave, push, and pop instructions so that gcc has the same stack | |
621 | frame as in 32 bit mode. */ | |
622 | static char stackop_size = '\0'; | |
eecb386c | 623 | |
12b55ccc L |
624 | /* Non-zero to optimize code alignment. */ |
625 | int optimize_align_code = 1; | |
626 | ||
47926f60 KH |
627 | /* Non-zero to quieten some warnings. */ |
628 | static int quiet_warnings = 0; | |
a38cf1db | 629 | |
47926f60 KH |
630 | /* CPU name. */ |
631 | static const char *cpu_arch_name = NULL; | |
6305a203 | 632 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 633 | |
47926f60 | 634 | /* CPU feature flags. */ |
40fb9820 L |
635 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
636 | ||
ccc9c027 L |
637 | /* If we have selected a cpu we are generating instructions for. */ |
638 | static int cpu_arch_tune_set = 0; | |
639 | ||
9103f4f4 | 640 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 641 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
642 | |
643 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 644 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 645 | |
ccc9c027 | 646 | /* CPU instruction set architecture used. */ |
fbf3f584 | 647 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 648 | |
9103f4f4 | 649 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 650 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 651 | |
fddf5b5b AM |
652 | /* If set, conditional jumps are not automatically promoted to handle |
653 | larger than a byte offset. */ | |
654 | static unsigned int no_cond_jump_promotion = 0; | |
655 | ||
c0f3af97 L |
656 | /* Encode SSE instructions with VEX prefix. */ |
657 | static unsigned int sse2avx; | |
658 | ||
539f890d L |
659 | /* Encode scalar AVX instructions with specific vector length. */ |
660 | static enum | |
661 | { | |
662 | vex128 = 0, | |
663 | vex256 | |
664 | } avxscalar; | |
665 | ||
43234a1e L |
666 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
667 | static enum | |
668 | { | |
669 | evexl128 = 0, | |
670 | evexl256, | |
671 | evexl512 | |
672 | } evexlig; | |
673 | ||
674 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
675 | static enum | |
676 | { | |
677 | evexw0 = 0, | |
678 | evexw1 | |
679 | } evexwig; | |
680 | ||
d3d3c6db IT |
681 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
682 | static enum rc_type evexrcig = rne; | |
683 | ||
29b0f896 | 684 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 685 | static symbolS *GOT_symbol; |
29b0f896 | 686 | |
a4447b93 RH |
687 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
688 | unsigned int x86_dwarf2_return_column; | |
689 | ||
690 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
691 | int x86_cie_data_alignment; | |
692 | ||
252b5132 | 693 | /* Interface to relax_segment. |
fddf5b5b AM |
694 | There are 3 major relax states for 386 jump insns because the |
695 | different types of jumps add different sizes to frags when we're | |
696 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 697 | |
47926f60 | 698 | /* Types. */ |
93c2a809 AM |
699 | #define UNCOND_JUMP 0 |
700 | #define COND_JUMP 1 | |
701 | #define COND_JUMP86 2 | |
fddf5b5b | 702 | |
47926f60 | 703 | /* Sizes. */ |
252b5132 RH |
704 | #define CODE16 1 |
705 | #define SMALL 0 | |
29b0f896 | 706 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 707 | #define BIG 2 |
29b0f896 | 708 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
709 | |
710 | #ifndef INLINE | |
711 | #ifdef __GNUC__ | |
712 | #define INLINE __inline__ | |
713 | #else | |
714 | #define INLINE | |
715 | #endif | |
716 | #endif | |
717 | ||
fddf5b5b AM |
718 | #define ENCODE_RELAX_STATE(type, size) \ |
719 | ((relax_substateT) (((type) << 2) | (size))) | |
720 | #define TYPE_FROM_RELAX_STATE(s) \ | |
721 | ((s) >> 2) | |
722 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
723 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
724 | |
725 | /* This table is used by relax_frag to promote short jumps to long | |
726 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
727 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
728 | don't allow a short jump in a 32 bit code segment to be promoted to | |
729 | a 16 bit offset jump because it's slower (requires data size | |
730 | prefix), and doesn't work, unless the destination is in the bottom | |
731 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
732 | ||
733 | const relax_typeS md_relax_table[] = | |
734 | { | |
24eab124 AM |
735 | /* The fields are: |
736 | 1) most positive reach of this state, | |
737 | 2) most negative reach of this state, | |
93c2a809 | 738 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 739 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 740 | |
fddf5b5b | 741 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
742 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
743 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
744 | /* dword jmp adds 4 bytes to frag: | |
745 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 746 | {0, 0, 4, 0}, |
93c2a809 AM |
747 | /* word jmp adds 2 byte2 to frag: |
748 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
749 | {0, 0, 2, 0}, |
750 | ||
93c2a809 AM |
751 | /* COND_JUMP states. */ |
752 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
753 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
754 | /* dword conditionals adds 5 bytes to frag: | |
755 | 1 extra opcode byte, 4 displacement bytes. */ | |
756 | {0, 0, 5, 0}, | |
fddf5b5b | 757 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
758 | 1 extra opcode byte, 2 displacement bytes. */ |
759 | {0, 0, 3, 0}, | |
760 | ||
761 | /* COND_JUMP86 states. */ | |
762 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
763 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
764 | /* dword conditionals adds 5 bytes to frag: | |
765 | 1 extra opcode byte, 4 displacement bytes. */ | |
766 | {0, 0, 5, 0}, | |
767 | /* word conditionals add 4 bytes to frag: | |
768 | 1 displacement byte and a 3 byte long branch insn. */ | |
769 | {0, 0, 4, 0} | |
252b5132 RH |
770 | }; |
771 | ||
9103f4f4 L |
772 | static const arch_entry cpu_arch[] = |
773 | { | |
89507696 JB |
774 | /* Do not replace the first two entries - i386_target_format() |
775 | relies on them being there in this order. */ | |
8a2c8fef | 776 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 777 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 778 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 779 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 780 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 781 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 782 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 783 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 784 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 785 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 786 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 787 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 788 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 789 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 790 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 791 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 792 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 793 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 794 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 795 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 796 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 797 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 798 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 799 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 800 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 801 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 802 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 803 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 804 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 805 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 806 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 807 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 808 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 809 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 810 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 811 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 812 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 813 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 814 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 815 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 816 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 817 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 818 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 819 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 820 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 821 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 822 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 823 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 824 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 825 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 826 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 827 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 828 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 829 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 830 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 831 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 832 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 833 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 834 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 835 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 836 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 837 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 838 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 839 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 840 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 841 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 842 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 843 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 844 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 845 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 846 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 847 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
848 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
849 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 850 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 851 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 852 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 853 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 854 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 855 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 856 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 857 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 858 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 859 | CPU_387_FLAGS, 0 }, |
1848e567 L |
860 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
861 | CPU_687_FLAGS, 0 }, | |
8a2c8fef | 862 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 863 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 864 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 865 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 866 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 867 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 868 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 869 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 870 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 871 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 872 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 873 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 874 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 875 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 876 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 877 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 878 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 879 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 880 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 881 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 882 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 883 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 884 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 885 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 886 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 887 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 888 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 889 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 890 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 891 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 892 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 893 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 894 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 895 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 896 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 897 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 898 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 899 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 900 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 901 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 902 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 903 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 904 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 905 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 906 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 907 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 908 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 909 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 910 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 911 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 912 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 913 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 914 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 915 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 916 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 917 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 918 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 919 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 920 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 921 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 922 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 923 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 924 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 925 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 926 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 927 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 928 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 929 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 930 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 931 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 932 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 933 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 934 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 935 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 936 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 937 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 938 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 939 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 940 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 941 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 942 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 943 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 944 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 945 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 946 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 947 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 948 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 949 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 950 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 951 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 952 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 953 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 954 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 955 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 956 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 957 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 958 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 959 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 960 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 961 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 962 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 963 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 964 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 965 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 966 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 967 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 968 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 969 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 970 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 971 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 972 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 973 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 974 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 975 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 976 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 977 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 978 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 979 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 980 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 981 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 982 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 983 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 984 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 985 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 986 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 987 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 988 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 989 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 990 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 991 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 992 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 993 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 994 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 995 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
996 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
997 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
998 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
999 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1000 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1001 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1002 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1003 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1004 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1005 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1006 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1007 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1008 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1009 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1010 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1011 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1012 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1013 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1014 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1015 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1016 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1017 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1018 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1019 | CPU_IBT_FLAGS, 0 }, | |
1020 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1021 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1022 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1023 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1024 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1025 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1026 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1027 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1028 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1029 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1030 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1031 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1032 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1033 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1034 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1035 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1036 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1037 | CPU_MOVDIRI_FLAGS, 0 }, | |
1038 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1039 | CPU_MOVDIR64B_FLAGS, 0 }, | |
293f5f65 L |
1040 | }; |
1041 | ||
1042 | static const noarch_entry cpu_noarch[] = | |
1043 | { | |
1044 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1045 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1046 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1047 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
293f5f65 L |
1048 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1049 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1050 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1051 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1052 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1053 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1054 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1055 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1056 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1057 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1058 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1059 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1060 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1061 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1062 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1063 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1064 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1065 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1066 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1067 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1068 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1069 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1070 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1071 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1072 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1073 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1074 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1075 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1076 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
e413e4e9 AM |
1077 | }; |
1078 | ||
704209c0 | 1079 | #ifdef I386COFF |
a6c24e68 NC |
1080 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1081 | is allowed to be optional. */ | |
1082 | ||
1083 | static symbolS * | |
1084 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1085 | { | |
1086 | addressT align = 0; | |
1087 | ||
1088 | SKIP_WHITESPACE (); | |
1089 | ||
7ab9ffdd | 1090 | if (needs_align |
a6c24e68 NC |
1091 | && *input_line_pointer == ',') |
1092 | { | |
1093 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1094 | |
a6c24e68 NC |
1095 | if (align == (addressT) -1) |
1096 | return NULL; | |
1097 | } | |
1098 | else | |
1099 | { | |
1100 | if (size >= 8) | |
1101 | align = 3; | |
1102 | else if (size >= 4) | |
1103 | align = 2; | |
1104 | else if (size >= 2) | |
1105 | align = 1; | |
1106 | else | |
1107 | align = 0; | |
1108 | } | |
1109 | ||
1110 | bss_alloc (symbolP, size, align); | |
1111 | return symbolP; | |
1112 | } | |
1113 | ||
704209c0 | 1114 | static void |
a6c24e68 NC |
1115 | pe_lcomm (int needs_align) |
1116 | { | |
1117 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1118 | } | |
704209c0 | 1119 | #endif |
a6c24e68 | 1120 | |
29b0f896 AM |
1121 | const pseudo_typeS md_pseudo_table[] = |
1122 | { | |
1123 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1124 | {"align", s_align_bytes, 0}, | |
1125 | #else | |
1126 | {"align", s_align_ptwo, 0}, | |
1127 | #endif | |
1128 | {"arch", set_cpu_arch, 0}, | |
1129 | #ifndef I386COFF | |
1130 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1131 | #else |
1132 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1133 | #endif |
1134 | {"ffloat", float_cons, 'f'}, | |
1135 | {"dfloat", float_cons, 'd'}, | |
1136 | {"tfloat", float_cons, 'x'}, | |
1137 | {"value", cons, 2}, | |
d182319b | 1138 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1139 | {"noopt", s_ignore, 0}, |
1140 | {"optim", s_ignore, 0}, | |
1141 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1142 | {"code16", set_code_flag, CODE_16BIT}, | |
1143 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1144 | #ifdef BFD64 |
29b0f896 | 1145 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1146 | #endif |
29b0f896 AM |
1147 | {"intel_syntax", set_intel_syntax, 1}, |
1148 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1149 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1150 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1151 | {"allow_index_reg", set_allow_index_reg, 1}, |
1152 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1153 | {"sse_check", set_check, 0}, |
1154 | {"operand_check", set_check, 1}, | |
3b22753a L |
1155 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1156 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1157 | #else |
68d20676 | 1158 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1159 | {"loc", dwarf2_directive_loc, 0}, |
1160 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1161 | #endif |
6482c264 NC |
1162 | #ifdef TE_PE |
1163 | {"secrel32", pe_directive_secrel, 0}, | |
1164 | #endif | |
29b0f896 AM |
1165 | {0, 0, 0} |
1166 | }; | |
1167 | ||
1168 | /* For interface with expression (). */ | |
1169 | extern char *input_line_pointer; | |
1170 | ||
1171 | /* Hash table for instruction mnemonic lookup. */ | |
1172 | static struct hash_control *op_hash; | |
1173 | ||
1174 | /* Hash table for register lookup. */ | |
1175 | static struct hash_control *reg_hash; | |
1176 | \f | |
ce8a8b2f AM |
1177 | /* Various efficient no-op patterns for aligning code labels. |
1178 | Note: Don't try to assemble the instructions in the comments. | |
1179 | 0L and 0w are not legal. */ | |
62a02d25 L |
1180 | static const unsigned char f32_1[] = |
1181 | {0x90}; /* nop */ | |
1182 | static const unsigned char f32_2[] = | |
1183 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1184 | static const unsigned char f32_3[] = | |
1185 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1186 | static const unsigned char f32_4[] = | |
1187 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1188 | static const unsigned char f32_6[] = |
1189 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1190 | static const unsigned char f32_7[] = | |
1191 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1192 | static const unsigned char f16_3[] = |
3ae729d5 | 1193 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1194 | static const unsigned char f16_4[] = |
3ae729d5 L |
1195 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1196 | static const unsigned char jump_disp8[] = | |
1197 | {0xeb}; /* jmp disp8 */ | |
1198 | static const unsigned char jump32_disp32[] = | |
1199 | {0xe9}; /* jmp disp32 */ | |
1200 | static const unsigned char jump16_disp32[] = | |
1201 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1202 | /* 32-bit NOPs patterns. */ |
1203 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1204 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1205 | }; |
1206 | /* 16-bit NOPs patterns. */ | |
1207 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1208 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1209 | }; |
1210 | /* nopl (%[re]ax) */ | |
1211 | static const unsigned char alt_3[] = | |
1212 | {0x0f,0x1f,0x00}; | |
1213 | /* nopl 0(%[re]ax) */ | |
1214 | static const unsigned char alt_4[] = | |
1215 | {0x0f,0x1f,0x40,0x00}; | |
1216 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1217 | static const unsigned char alt_5[] = | |
1218 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1219 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1220 | static const unsigned char alt_6[] = | |
1221 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1222 | /* nopl 0L(%[re]ax) */ | |
1223 | static const unsigned char alt_7[] = | |
1224 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1225 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1226 | static const unsigned char alt_8[] = | |
1227 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1228 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1229 | static const unsigned char alt_9[] = | |
1230 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1231 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1232 | static const unsigned char alt_10[] = | |
1233 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1234 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1235 | static const unsigned char alt_11[] = | |
1236 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1237 | /* 32-bit and 64-bit NOPs patterns. */ |
1238 | static const unsigned char *const alt_patt[] = { | |
1239 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1240 | alt_9, alt_10, alt_11 |
62a02d25 L |
1241 | }; |
1242 | ||
1243 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1244 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1245 | ||
1246 | static void | |
1247 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1248 | int count, int max_single_nop_size) | |
1249 | ||
1250 | { | |
3ae729d5 L |
1251 | /* Place the longer NOP first. */ |
1252 | int last; | |
1253 | int offset; | |
1254 | const unsigned char *nops = patt[max_single_nop_size - 1]; | |
1255 | ||
1256 | /* Use the smaller one if the requsted one isn't available. */ | |
1257 | if (nops == NULL) | |
62a02d25 | 1258 | { |
3ae729d5 L |
1259 | max_single_nop_size--; |
1260 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1261 | } |
1262 | ||
3ae729d5 L |
1263 | last = count % max_single_nop_size; |
1264 | ||
1265 | count -= last; | |
1266 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1267 | memcpy (where + offset, nops, max_single_nop_size); | |
1268 | ||
1269 | if (last) | |
1270 | { | |
1271 | nops = patt[last - 1]; | |
1272 | if (nops == NULL) | |
1273 | { | |
1274 | /* Use the smaller one plus one-byte NOP if the needed one | |
1275 | isn't available. */ | |
1276 | last--; | |
1277 | nops = patt[last - 1]; | |
1278 | memcpy (where + offset, nops, last); | |
1279 | where[offset + last] = *patt[0]; | |
1280 | } | |
1281 | else | |
1282 | memcpy (where + offset, nops, last); | |
1283 | } | |
62a02d25 L |
1284 | } |
1285 | ||
3ae729d5 L |
1286 | static INLINE int |
1287 | fits_in_imm7 (offsetT num) | |
1288 | { | |
1289 | return (num & 0x7f) == num; | |
1290 | } | |
1291 | ||
1292 | static INLINE int | |
1293 | fits_in_imm31 (offsetT num) | |
1294 | { | |
1295 | return (num & 0x7fffffff) == num; | |
1296 | } | |
62a02d25 L |
1297 | |
1298 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1299 | single NOP instruction LIMIT. */ | |
1300 | ||
1301 | void | |
3ae729d5 | 1302 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1303 | { |
3ae729d5 | 1304 | const unsigned char *const *patt = NULL; |
62a02d25 | 1305 | int max_single_nop_size; |
3ae729d5 L |
1306 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1307 | int max_number_of_nops; | |
62a02d25 | 1308 | |
3ae729d5 | 1309 | switch (fragP->fr_type) |
62a02d25 | 1310 | { |
3ae729d5 L |
1311 | case rs_fill_nop: |
1312 | case rs_align_code: | |
1313 | break; | |
1314 | default: | |
62a02d25 L |
1315 | return; |
1316 | } | |
1317 | ||
ccc9c027 L |
1318 | /* We need to decide which NOP sequence to use for 32bit and |
1319 | 64bit. When -mtune= is used: | |
4eed87de | 1320 | |
76bc74dc L |
1321 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1322 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1323 | 2. For the rest, alt_patt will be used. |
1324 | ||
1325 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1326 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1327 | be used. |
ccc9c027 L |
1328 | |
1329 | When -march= or .arch is used, we can't use anything beyond | |
1330 | cpu_arch_isa_flags. */ | |
1331 | ||
1332 | if (flag_code == CODE_16BIT) | |
1333 | { | |
3ae729d5 L |
1334 | patt = f16_patt; |
1335 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1336 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1337 | max_number_of_nops = 2; | |
252b5132 | 1338 | } |
33fef721 | 1339 | else |
ccc9c027 | 1340 | { |
fbf3f584 | 1341 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1342 | { |
1343 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1344 | switch (cpu_arch_tune) | |
1345 | { | |
1346 | case PROCESSOR_UNKNOWN: | |
1347 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1348 | optimize with nops. */ |
1349 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1350 | patt = alt_patt; |
ccc9c027 L |
1351 | else |
1352 | patt = f32_patt; | |
1353 | break; | |
ccc9c027 L |
1354 | case PROCESSOR_PENTIUM4: |
1355 | case PROCESSOR_NOCONA: | |
ef05d495 | 1356 | case PROCESSOR_CORE: |
76bc74dc | 1357 | case PROCESSOR_CORE2: |
bd5295b2 | 1358 | case PROCESSOR_COREI7: |
3632d14b | 1359 | case PROCESSOR_L1OM: |
7a9068fe | 1360 | case PROCESSOR_K1OM: |
76bc74dc | 1361 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1362 | case PROCESSOR_K6: |
1363 | case PROCESSOR_ATHLON: | |
1364 | case PROCESSOR_K8: | |
4eed87de | 1365 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1366 | case PROCESSOR_BD: |
029f3522 | 1367 | case PROCESSOR_ZNVER: |
7b458c12 | 1368 | case PROCESSOR_BT: |
80b8656c | 1369 | patt = alt_patt; |
ccc9c027 | 1370 | break; |
76bc74dc | 1371 | case PROCESSOR_I386: |
ccc9c027 L |
1372 | case PROCESSOR_I486: |
1373 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1374 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1375 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1376 | case PROCESSOR_GENERIC32: |
1377 | patt = f32_patt; | |
1378 | break; | |
4eed87de | 1379 | } |
ccc9c027 L |
1380 | } |
1381 | else | |
1382 | { | |
fbf3f584 | 1383 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1384 | { |
1385 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1386 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1387 | PROCESSOR_UNKNOWN. */ |
1388 | abort (); | |
1389 | break; | |
1390 | ||
76bc74dc | 1391 | case PROCESSOR_I386: |
ccc9c027 L |
1392 | case PROCESSOR_I486: |
1393 | case PROCESSOR_PENTIUM: | |
81486035 | 1394 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1395 | case PROCESSOR_K6: |
1396 | case PROCESSOR_ATHLON: | |
1397 | case PROCESSOR_K8: | |
4eed87de | 1398 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1399 | case PROCESSOR_BD: |
029f3522 | 1400 | case PROCESSOR_ZNVER: |
7b458c12 | 1401 | case PROCESSOR_BT: |
ccc9c027 L |
1402 | case PROCESSOR_GENERIC32: |
1403 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1404 | with nops. */ |
1405 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1406 | patt = alt_patt; |
ccc9c027 L |
1407 | else |
1408 | patt = f32_patt; | |
1409 | break; | |
76bc74dc L |
1410 | case PROCESSOR_PENTIUMPRO: |
1411 | case PROCESSOR_PENTIUM4: | |
1412 | case PROCESSOR_NOCONA: | |
1413 | case PROCESSOR_CORE: | |
ef05d495 | 1414 | case PROCESSOR_CORE2: |
bd5295b2 | 1415 | case PROCESSOR_COREI7: |
3632d14b | 1416 | case PROCESSOR_L1OM: |
7a9068fe | 1417 | case PROCESSOR_K1OM: |
22109423 | 1418 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1419 | patt = alt_patt; |
ccc9c027 L |
1420 | else |
1421 | patt = f32_patt; | |
1422 | break; | |
1423 | case PROCESSOR_GENERIC64: | |
80b8656c | 1424 | patt = alt_patt; |
ccc9c027 | 1425 | break; |
4eed87de | 1426 | } |
ccc9c027 L |
1427 | } |
1428 | ||
76bc74dc L |
1429 | if (patt == f32_patt) |
1430 | { | |
3ae729d5 L |
1431 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1432 | /* Limit number of NOPs to 2 for older processors. */ | |
1433 | max_number_of_nops = 2; | |
76bc74dc L |
1434 | } |
1435 | else | |
1436 | { | |
3ae729d5 L |
1437 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1438 | /* Limit number of NOPs to 7 for newer processors. */ | |
1439 | max_number_of_nops = 7; | |
1440 | } | |
1441 | } | |
1442 | ||
1443 | if (limit == 0) | |
1444 | limit = max_single_nop_size; | |
1445 | ||
1446 | if (fragP->fr_type == rs_fill_nop) | |
1447 | { | |
1448 | /* Output NOPs for .nop directive. */ | |
1449 | if (limit > max_single_nop_size) | |
1450 | { | |
1451 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1452 | _("invalid single nop size: %d " | |
1453 | "(expect within [0, %d])"), | |
1454 | limit, max_single_nop_size); | |
1455 | return; | |
1456 | } | |
1457 | } | |
1458 | else | |
1459 | fragP->fr_var = count; | |
1460 | ||
1461 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1462 | { | |
1463 | /* Generate jump over NOPs. */ | |
1464 | offsetT disp = count - 2; | |
1465 | if (fits_in_imm7 (disp)) | |
1466 | { | |
1467 | /* Use "jmp disp8" if possible. */ | |
1468 | count = disp; | |
1469 | where[0] = jump_disp8[0]; | |
1470 | where[1] = count; | |
1471 | where += 2; | |
1472 | } | |
1473 | else | |
1474 | { | |
1475 | unsigned int size_of_jump; | |
1476 | ||
1477 | if (flag_code == CODE_16BIT) | |
1478 | { | |
1479 | where[0] = jump16_disp32[0]; | |
1480 | where[1] = jump16_disp32[1]; | |
1481 | size_of_jump = 2; | |
1482 | } | |
1483 | else | |
1484 | { | |
1485 | where[0] = jump32_disp32[0]; | |
1486 | size_of_jump = 1; | |
1487 | } | |
1488 | ||
1489 | count -= size_of_jump + 4; | |
1490 | if (!fits_in_imm31 (count)) | |
1491 | { | |
1492 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1493 | _("jump over nop padding out of range")); | |
1494 | return; | |
1495 | } | |
1496 | ||
1497 | md_number_to_chars (where + size_of_jump, count, 4); | |
1498 | where += size_of_jump + 4; | |
76bc74dc | 1499 | } |
ccc9c027 | 1500 | } |
3ae729d5 L |
1501 | |
1502 | /* Generate multiple NOPs. */ | |
1503 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1504 | } |
1505 | ||
c6fb90c8 | 1506 | static INLINE int |
0dfbf9d7 | 1507 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1508 | { |
0dfbf9d7 | 1509 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1510 | { |
1511 | case 3: | |
0dfbf9d7 | 1512 | if (x->array[2]) |
c6fb90c8 | 1513 | return 0; |
1a0670f3 | 1514 | /* Fall through. */ |
c6fb90c8 | 1515 | case 2: |
0dfbf9d7 | 1516 | if (x->array[1]) |
c6fb90c8 | 1517 | return 0; |
1a0670f3 | 1518 | /* Fall through. */ |
c6fb90c8 | 1519 | case 1: |
0dfbf9d7 | 1520 | return !x->array[0]; |
c6fb90c8 L |
1521 | default: |
1522 | abort (); | |
1523 | } | |
40fb9820 L |
1524 | } |
1525 | ||
c6fb90c8 | 1526 | static INLINE void |
0dfbf9d7 | 1527 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1528 | { |
0dfbf9d7 | 1529 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1530 | { |
1531 | case 3: | |
0dfbf9d7 | 1532 | x->array[2] = v; |
1a0670f3 | 1533 | /* Fall through. */ |
c6fb90c8 | 1534 | case 2: |
0dfbf9d7 | 1535 | x->array[1] = v; |
1a0670f3 | 1536 | /* Fall through. */ |
c6fb90c8 | 1537 | case 1: |
0dfbf9d7 | 1538 | x->array[0] = v; |
1a0670f3 | 1539 | /* Fall through. */ |
c6fb90c8 L |
1540 | break; |
1541 | default: | |
1542 | abort (); | |
1543 | } | |
1544 | } | |
40fb9820 | 1545 | |
c6fb90c8 | 1546 | static INLINE int |
0dfbf9d7 L |
1547 | operand_type_equal (const union i386_operand_type *x, |
1548 | const union i386_operand_type *y) | |
c6fb90c8 | 1549 | { |
0dfbf9d7 | 1550 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1551 | { |
1552 | case 3: | |
0dfbf9d7 | 1553 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1554 | return 0; |
1a0670f3 | 1555 | /* Fall through. */ |
c6fb90c8 | 1556 | case 2: |
0dfbf9d7 | 1557 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1558 | return 0; |
1a0670f3 | 1559 | /* Fall through. */ |
c6fb90c8 | 1560 | case 1: |
0dfbf9d7 | 1561 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1562 | break; |
1563 | default: | |
1564 | abort (); | |
1565 | } | |
1566 | } | |
40fb9820 | 1567 | |
0dfbf9d7 L |
1568 | static INLINE int |
1569 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1570 | { | |
1571 | switch (ARRAY_SIZE(x->array)) | |
1572 | { | |
53467f57 IT |
1573 | case 4: |
1574 | if (x->array[3]) | |
1575 | return 0; | |
1576 | /* Fall through. */ | |
0dfbf9d7 L |
1577 | case 3: |
1578 | if (x->array[2]) | |
1579 | return 0; | |
1a0670f3 | 1580 | /* Fall through. */ |
0dfbf9d7 L |
1581 | case 2: |
1582 | if (x->array[1]) | |
1583 | return 0; | |
1a0670f3 | 1584 | /* Fall through. */ |
0dfbf9d7 L |
1585 | case 1: |
1586 | return !x->array[0]; | |
1587 | default: | |
1588 | abort (); | |
1589 | } | |
1590 | } | |
1591 | ||
0dfbf9d7 L |
1592 | static INLINE int |
1593 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1594 | const union i386_cpu_flags *y) | |
1595 | { | |
1596 | switch (ARRAY_SIZE(x->array)) | |
1597 | { | |
53467f57 IT |
1598 | case 4: |
1599 | if (x->array[3] != y->array[3]) | |
1600 | return 0; | |
1601 | /* Fall through. */ | |
0dfbf9d7 L |
1602 | case 3: |
1603 | if (x->array[2] != y->array[2]) | |
1604 | return 0; | |
1a0670f3 | 1605 | /* Fall through. */ |
0dfbf9d7 L |
1606 | case 2: |
1607 | if (x->array[1] != y->array[1]) | |
1608 | return 0; | |
1a0670f3 | 1609 | /* Fall through. */ |
0dfbf9d7 L |
1610 | case 1: |
1611 | return x->array[0] == y->array[0]; | |
1612 | break; | |
1613 | default: | |
1614 | abort (); | |
1615 | } | |
1616 | } | |
c6fb90c8 L |
1617 | |
1618 | static INLINE int | |
1619 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1620 | { | |
1621 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1622 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1623 | } |
1624 | ||
c6fb90c8 L |
1625 | static INLINE i386_cpu_flags |
1626 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1627 | { |
c6fb90c8 L |
1628 | switch (ARRAY_SIZE (x.array)) |
1629 | { | |
53467f57 IT |
1630 | case 4: |
1631 | x.array [3] &= y.array [3]; | |
1632 | /* Fall through. */ | |
c6fb90c8 L |
1633 | case 3: |
1634 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1635 | /* Fall through. */ |
c6fb90c8 L |
1636 | case 2: |
1637 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1638 | /* Fall through. */ |
c6fb90c8 L |
1639 | case 1: |
1640 | x.array [0] &= y.array [0]; | |
1641 | break; | |
1642 | default: | |
1643 | abort (); | |
1644 | } | |
1645 | return x; | |
1646 | } | |
40fb9820 | 1647 | |
c6fb90c8 L |
1648 | static INLINE i386_cpu_flags |
1649 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1650 | { |
c6fb90c8 | 1651 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1652 | { |
53467f57 IT |
1653 | case 4: |
1654 | x.array [3] |= y.array [3]; | |
1655 | /* Fall through. */ | |
c6fb90c8 L |
1656 | case 3: |
1657 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1658 | /* Fall through. */ |
c6fb90c8 L |
1659 | case 2: |
1660 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1661 | /* Fall through. */ |
c6fb90c8 L |
1662 | case 1: |
1663 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1664 | break; |
1665 | default: | |
1666 | abort (); | |
1667 | } | |
40fb9820 L |
1668 | return x; |
1669 | } | |
1670 | ||
309d3373 JB |
1671 | static INLINE i386_cpu_flags |
1672 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1673 | { | |
1674 | switch (ARRAY_SIZE (x.array)) | |
1675 | { | |
53467f57 IT |
1676 | case 4: |
1677 | x.array [3] &= ~y.array [3]; | |
1678 | /* Fall through. */ | |
309d3373 JB |
1679 | case 3: |
1680 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1681 | /* Fall through. */ |
309d3373 JB |
1682 | case 2: |
1683 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1684 | /* Fall through. */ |
309d3373 JB |
1685 | case 1: |
1686 | x.array [0] &= ~y.array [0]; | |
1687 | break; | |
1688 | default: | |
1689 | abort (); | |
1690 | } | |
1691 | return x; | |
1692 | } | |
1693 | ||
c0f3af97 L |
1694 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1695 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1696 | ||
c0f3af97 | 1697 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1698 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1699 | |
1700 | /* Return CPU flags match bits. */ | |
3629bb00 | 1701 | |
40fb9820 | 1702 | static int |
d3ce72d0 | 1703 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1704 | { |
c0f3af97 L |
1705 | i386_cpu_flags x = t->cpu_flags; |
1706 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1707 | |
1708 | x.bitfield.cpu64 = 0; | |
1709 | x.bitfield.cpuno64 = 0; | |
1710 | ||
0dfbf9d7 | 1711 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1712 | { |
1713 | /* This instruction is available on all archs. */ | |
db12e14e | 1714 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1715 | } |
3629bb00 L |
1716 | else |
1717 | { | |
c0f3af97 | 1718 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1719 | i386_cpu_flags cpu = cpu_arch_flags; |
1720 | ||
ab592e75 JB |
1721 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1722 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1723 | return match; | |
1724 | x.bitfield.cpuavx512vl = 0; | |
1725 | ||
3629bb00 | 1726 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1727 | if (!cpu_flags_all_zero (&cpu)) |
1728 | { | |
a5ff0eb2 L |
1729 | if (x.bitfield.cpuavx) |
1730 | { | |
929f69fa | 1731 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1732 | if (cpu.bitfield.cpuavx |
1733 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1734 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1735 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1736 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1737 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1738 | } |
929f69fa JB |
1739 | else if (x.bitfield.cpuavx512f) |
1740 | { | |
1741 | /* We need to check a few extra flags with AVX512F. */ | |
1742 | if (cpu.bitfield.cpuavx512f | |
1743 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1744 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1745 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1746 | match |= CPU_FLAGS_ARCH_MATCH; | |
1747 | } | |
a5ff0eb2 | 1748 | else |
db12e14e | 1749 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1750 | } |
3629bb00 | 1751 | } |
c0f3af97 | 1752 | return match; |
40fb9820 L |
1753 | } |
1754 | ||
c6fb90c8 L |
1755 | static INLINE i386_operand_type |
1756 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1757 | { |
c6fb90c8 L |
1758 | switch (ARRAY_SIZE (x.array)) |
1759 | { | |
1760 | case 3: | |
1761 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1762 | /* Fall through. */ |
c6fb90c8 L |
1763 | case 2: |
1764 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1765 | /* Fall through. */ |
c6fb90c8 L |
1766 | case 1: |
1767 | x.array [0] &= y.array [0]; | |
1768 | break; | |
1769 | default: | |
1770 | abort (); | |
1771 | } | |
1772 | return x; | |
40fb9820 L |
1773 | } |
1774 | ||
73053c1f JB |
1775 | static INLINE i386_operand_type |
1776 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1777 | { | |
1778 | switch (ARRAY_SIZE (x.array)) | |
1779 | { | |
1780 | case 3: | |
1781 | x.array [2] &= ~y.array [2]; | |
1782 | /* Fall through. */ | |
1783 | case 2: | |
1784 | x.array [1] &= ~y.array [1]; | |
1785 | /* Fall through. */ | |
1786 | case 1: | |
1787 | x.array [0] &= ~y.array [0]; | |
1788 | break; | |
1789 | default: | |
1790 | abort (); | |
1791 | } | |
1792 | return x; | |
1793 | } | |
1794 | ||
c6fb90c8 L |
1795 | static INLINE i386_operand_type |
1796 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1797 | { |
c6fb90c8 | 1798 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1799 | { |
c6fb90c8 L |
1800 | case 3: |
1801 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1802 | /* Fall through. */ |
c6fb90c8 L |
1803 | case 2: |
1804 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1805 | /* Fall through. */ |
c6fb90c8 L |
1806 | case 1: |
1807 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1808 | break; |
1809 | default: | |
1810 | abort (); | |
1811 | } | |
c6fb90c8 L |
1812 | return x; |
1813 | } | |
40fb9820 | 1814 | |
c6fb90c8 L |
1815 | static INLINE i386_operand_type |
1816 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1817 | { | |
1818 | switch (ARRAY_SIZE (x.array)) | |
1819 | { | |
1820 | case 3: | |
1821 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1822 | /* Fall through. */ |
c6fb90c8 L |
1823 | case 2: |
1824 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1825 | /* Fall through. */ |
c6fb90c8 L |
1826 | case 1: |
1827 | x.array [0] ^= y.array [0]; | |
1828 | break; | |
1829 | default: | |
1830 | abort (); | |
1831 | } | |
40fb9820 L |
1832 | return x; |
1833 | } | |
1834 | ||
1835 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1836 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
40fb9820 L |
1837 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
1838 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1839 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1840 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1841 | static const i386_operand_type anydisp | |
1842 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1843 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1844 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1845 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1846 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1847 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1848 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1849 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1850 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1851 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1852 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1853 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1854 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1855 | |
1856 | enum operand_type | |
1857 | { | |
1858 | reg, | |
40fb9820 L |
1859 | imm, |
1860 | disp, | |
1861 | anymem | |
1862 | }; | |
1863 | ||
c6fb90c8 | 1864 | static INLINE int |
40fb9820 L |
1865 | operand_type_check (i386_operand_type t, enum operand_type c) |
1866 | { | |
1867 | switch (c) | |
1868 | { | |
1869 | case reg: | |
dc821c5f | 1870 | return t.bitfield.reg; |
40fb9820 | 1871 | |
40fb9820 L |
1872 | case imm: |
1873 | return (t.bitfield.imm8 | |
1874 | || t.bitfield.imm8s | |
1875 | || t.bitfield.imm16 | |
1876 | || t.bitfield.imm32 | |
1877 | || t.bitfield.imm32s | |
1878 | || t.bitfield.imm64); | |
1879 | ||
1880 | case disp: | |
1881 | return (t.bitfield.disp8 | |
1882 | || t.bitfield.disp16 | |
1883 | || t.bitfield.disp32 | |
1884 | || t.bitfield.disp32s | |
1885 | || t.bitfield.disp64); | |
1886 | ||
1887 | case anymem: | |
1888 | return (t.bitfield.disp8 | |
1889 | || t.bitfield.disp16 | |
1890 | || t.bitfield.disp32 | |
1891 | || t.bitfield.disp32s | |
1892 | || t.bitfield.disp64 | |
1893 | || t.bitfield.baseindex); | |
1894 | ||
1895 | default: | |
1896 | abort (); | |
1897 | } | |
2cfe26b6 AM |
1898 | |
1899 | return 0; | |
40fb9820 L |
1900 | } |
1901 | ||
7a54636a L |
1902 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
1903 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
1904 | |
1905 | static INLINE int | |
7a54636a L |
1906 | match_operand_size (const insn_template *t, unsigned int wanted, |
1907 | unsigned int given) | |
5c07affc | 1908 | { |
3ac21baa JB |
1909 | return !((i.types[given].bitfield.byte |
1910 | && !t->operand_types[wanted].bitfield.byte) | |
1911 | || (i.types[given].bitfield.word | |
1912 | && !t->operand_types[wanted].bitfield.word) | |
1913 | || (i.types[given].bitfield.dword | |
1914 | && !t->operand_types[wanted].bitfield.dword) | |
1915 | || (i.types[given].bitfield.qword | |
1916 | && !t->operand_types[wanted].bitfield.qword) | |
1917 | || (i.types[given].bitfield.tbyte | |
1918 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
1919 | } |
1920 | ||
dd40ce22 L |
1921 | /* Return 1 if there is no conflict in SIMD register between operand |
1922 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
1923 | |
1924 | static INLINE int | |
dd40ce22 L |
1925 | match_simd_size (const insn_template *t, unsigned int wanted, |
1926 | unsigned int given) | |
1b54b8d7 | 1927 | { |
3ac21baa JB |
1928 | return !((i.types[given].bitfield.xmmword |
1929 | && !t->operand_types[wanted].bitfield.xmmword) | |
1930 | || (i.types[given].bitfield.ymmword | |
1931 | && !t->operand_types[wanted].bitfield.ymmword) | |
1932 | || (i.types[given].bitfield.zmmword | |
1933 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
1934 | } |
1935 | ||
7a54636a L |
1936 | /* Return 1 if there is no conflict in any size between operand GIVEN |
1937 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
1938 | |
1939 | static INLINE int | |
dd40ce22 L |
1940 | match_mem_size (const insn_template *t, unsigned int wanted, |
1941 | unsigned int given) | |
5c07affc | 1942 | { |
7a54636a | 1943 | return (match_operand_size (t, wanted, given) |
3ac21baa | 1944 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 1945 | && !i.broadcast |
3ac21baa JB |
1946 | && !t->operand_types[wanted].bitfield.unspecified) |
1947 | || (i.types[given].bitfield.fword | |
1948 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
1949 | /* For scalar opcode templates to allow register and memory |
1950 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
1951 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
1952 | down-conversion vpmov*. */ | |
3ac21baa | 1953 | || ((t->operand_types[wanted].bitfield.regsimd |
1b54b8d7 | 1954 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
1955 | && (t->operand_types[wanted].bitfield.byte |
1956 | || t->operand_types[wanted].bitfield.word | |
1957 | || t->operand_types[wanted].bitfield.dword | |
1958 | || t->operand_types[wanted].bitfield.qword)) | |
1959 | ? (i.types[given].bitfield.xmmword | |
1960 | || i.types[given].bitfield.ymmword | |
1961 | || i.types[given].bitfield.zmmword) | |
1962 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
1963 | } |
1964 | ||
3ac21baa JB |
1965 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
1966 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
1967 | is no size conflict on any operands for the template with operands reversed | |
1968 | (and the template allows for reversing in the first place). */ | |
5c07affc | 1969 | |
3ac21baa JB |
1970 | #define MATCH_STRAIGHT 1 |
1971 | #define MATCH_REVERSE 2 | |
1972 | ||
1973 | static INLINE unsigned int | |
d3ce72d0 | 1974 | operand_size_match (const insn_template *t) |
5c07affc | 1975 | { |
3ac21baa | 1976 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc L |
1977 | |
1978 | /* Don't check jump instructions. */ | |
1979 | if (t->opcode_modifier.jump | |
1980 | || t->opcode_modifier.jumpbyte | |
1981 | || t->opcode_modifier.jumpdword | |
1982 | || t->opcode_modifier.jumpintersegment) | |
1983 | return match; | |
1984 | ||
1985 | /* Check memory and accumulator operand size. */ | |
1986 | for (j = 0; j < i.operands; j++) | |
1987 | { | |
1b54b8d7 JB |
1988 | if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd |
1989 | && t->operand_types[j].bitfield.anysize) | |
5c07affc L |
1990 | continue; |
1991 | ||
1b54b8d7 | 1992 | if (t->operand_types[j].bitfield.reg |
7a54636a | 1993 | && !match_operand_size (t, j, j)) |
5c07affc L |
1994 | { |
1995 | match = 0; | |
1996 | break; | |
1997 | } | |
1998 | ||
1b54b8d7 | 1999 | if (t->operand_types[j].bitfield.regsimd |
3ac21baa | 2000 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2001 | { |
2002 | match = 0; | |
2003 | break; | |
2004 | } | |
2005 | ||
2006 | if (t->operand_types[j].bitfield.acc | |
7a54636a | 2007 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2008 | { |
2009 | match = 0; | |
2010 | break; | |
2011 | } | |
2012 | ||
3ac21baa | 2013 | if (i.types[j].bitfield.mem && !match_mem_size (t, j, j)) |
5c07affc L |
2014 | { |
2015 | match = 0; | |
2016 | break; | |
2017 | } | |
2018 | } | |
2019 | ||
3ac21baa | 2020 | if (!t->opcode_modifier.d) |
891edac4 L |
2021 | { |
2022 | mismatch: | |
3ac21baa JB |
2023 | if (!match) |
2024 | i.error = operand_size_mismatch; | |
2025 | return match; | |
891edac4 | 2026 | } |
5c07affc L |
2027 | |
2028 | /* Check reverse. */ | |
9c2799c2 | 2029 | gas_assert (i.operands == 2); |
5c07affc | 2030 | |
5c07affc L |
2031 | for (j = 0; j < 2; j++) |
2032 | { | |
dc821c5f JB |
2033 | if ((t->operand_types[j].bitfield.reg |
2034 | || t->operand_types[j].bitfield.acc) | |
7a54636a | 2035 | && !match_operand_size (t, j, !j)) |
891edac4 | 2036 | goto mismatch; |
5c07affc | 2037 | |
3ac21baa JB |
2038 | if (i.types[!j].bitfield.mem |
2039 | && !match_mem_size (t, j, !j)) | |
891edac4 | 2040 | goto mismatch; |
5c07affc L |
2041 | } |
2042 | ||
3ac21baa | 2043 | return match | MATCH_REVERSE; |
5c07affc L |
2044 | } |
2045 | ||
c6fb90c8 | 2046 | static INLINE int |
40fb9820 L |
2047 | operand_type_match (i386_operand_type overlap, |
2048 | i386_operand_type given) | |
2049 | { | |
2050 | i386_operand_type temp = overlap; | |
2051 | ||
2052 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 2053 | temp.bitfield.unspecified = 0; |
5c07affc L |
2054 | temp.bitfield.byte = 0; |
2055 | temp.bitfield.word = 0; | |
2056 | temp.bitfield.dword = 0; | |
2057 | temp.bitfield.fword = 0; | |
2058 | temp.bitfield.qword = 0; | |
2059 | temp.bitfield.tbyte = 0; | |
2060 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2061 | temp.bitfield.ymmword = 0; |
43234a1e | 2062 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2063 | if (operand_type_all_zero (&temp)) |
891edac4 | 2064 | goto mismatch; |
40fb9820 | 2065 | |
891edac4 L |
2066 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
2067 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
2068 | return 1; | |
2069 | ||
2070 | mismatch: | |
a65babc9 | 2071 | i.error = operand_type_mismatch; |
891edac4 | 2072 | return 0; |
40fb9820 L |
2073 | } |
2074 | ||
7d5e4556 | 2075 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2076 | unless the expected operand type register overlap is null. |
2077 | Memory operand size of certain SIMD instructions is also being checked | |
2078 | here. */ | |
40fb9820 | 2079 | |
c6fb90c8 | 2080 | static INLINE int |
dc821c5f | 2081 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2082 | i386_operand_type t0, |
40fb9820 L |
2083 | i386_operand_type g1, |
2084 | i386_operand_type t1) | |
2085 | { | |
10c17abd JB |
2086 | if (!g0.bitfield.reg |
2087 | && !g0.bitfield.regsimd | |
2088 | && (!operand_type_check (g0, anymem) | |
2089 | || g0.bitfield.unspecified | |
2090 | || !t0.bitfield.regsimd)) | |
40fb9820 L |
2091 | return 1; |
2092 | ||
10c17abd JB |
2093 | if (!g1.bitfield.reg |
2094 | && !g1.bitfield.regsimd | |
2095 | && (!operand_type_check (g1, anymem) | |
2096 | || g1.bitfield.unspecified | |
2097 | || !t1.bitfield.regsimd)) | |
40fb9820 L |
2098 | return 1; |
2099 | ||
dc821c5f JB |
2100 | if (g0.bitfield.byte == g1.bitfield.byte |
2101 | && g0.bitfield.word == g1.bitfield.word | |
2102 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2103 | && g0.bitfield.qword == g1.bitfield.qword |
2104 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2105 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2106 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2107 | return 1; |
2108 | ||
dc821c5f JB |
2109 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2110 | && !(t0.bitfield.word & t1.bitfield.word) | |
2111 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2112 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2113 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2114 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2115 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2116 | return 1; |
2117 | ||
a65babc9 | 2118 | i.error = register_type_mismatch; |
891edac4 L |
2119 | |
2120 | return 0; | |
40fb9820 L |
2121 | } |
2122 | ||
4c692bc7 JB |
2123 | static INLINE unsigned int |
2124 | register_number (const reg_entry *r) | |
2125 | { | |
2126 | unsigned int nr = r->reg_num; | |
2127 | ||
2128 | if (r->reg_flags & RegRex) | |
2129 | nr += 8; | |
2130 | ||
200cbe0f L |
2131 | if (r->reg_flags & RegVRex) |
2132 | nr += 16; | |
2133 | ||
4c692bc7 JB |
2134 | return nr; |
2135 | } | |
2136 | ||
252b5132 | 2137 | static INLINE unsigned int |
40fb9820 | 2138 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2139 | { |
b5014f7a | 2140 | if (t.bitfield.disp8) |
40fb9820 L |
2141 | return 1; |
2142 | else if (t.bitfield.disp16 | |
2143 | || t.bitfield.disp32 | |
2144 | || t.bitfield.disp32s) | |
2145 | return 2; | |
2146 | else | |
2147 | return 0; | |
252b5132 RH |
2148 | } |
2149 | ||
2150 | static INLINE int | |
65879393 | 2151 | fits_in_signed_byte (addressT num) |
252b5132 | 2152 | { |
65879393 | 2153 | return num + 0x80 <= 0xff; |
47926f60 | 2154 | } |
252b5132 RH |
2155 | |
2156 | static INLINE int | |
65879393 | 2157 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2158 | { |
65879393 | 2159 | return num <= 0xff; |
47926f60 | 2160 | } |
252b5132 RH |
2161 | |
2162 | static INLINE int | |
65879393 | 2163 | fits_in_unsigned_word (addressT num) |
252b5132 | 2164 | { |
65879393 | 2165 | return num <= 0xffff; |
47926f60 | 2166 | } |
252b5132 RH |
2167 | |
2168 | static INLINE int | |
65879393 | 2169 | fits_in_signed_word (addressT num) |
252b5132 | 2170 | { |
65879393 | 2171 | return num + 0x8000 <= 0xffff; |
47926f60 | 2172 | } |
2a962e6d | 2173 | |
3e73aa7c | 2174 | static INLINE int |
65879393 | 2175 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2176 | { |
2177 | #ifndef BFD64 | |
2178 | return 1; | |
2179 | #else | |
65879393 | 2180 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2181 | #endif |
2182 | } /* fits_in_signed_long() */ | |
2a962e6d | 2183 | |
3e73aa7c | 2184 | static INLINE int |
65879393 | 2185 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2186 | { |
2187 | #ifndef BFD64 | |
2188 | return 1; | |
2189 | #else | |
65879393 | 2190 | return num <= 0xffffffff; |
3e73aa7c JH |
2191 | #endif |
2192 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2193 | |
43234a1e | 2194 | static INLINE int |
b5014f7a | 2195 | fits_in_disp8 (offsetT num) |
43234a1e L |
2196 | { |
2197 | int shift = i.memshift; | |
2198 | unsigned int mask; | |
2199 | ||
2200 | if (shift == -1) | |
2201 | abort (); | |
2202 | ||
2203 | mask = (1 << shift) - 1; | |
2204 | ||
2205 | /* Return 0 if NUM isn't properly aligned. */ | |
2206 | if ((num & mask)) | |
2207 | return 0; | |
2208 | ||
2209 | /* Check if NUM will fit in 8bit after shift. */ | |
2210 | return fits_in_signed_byte (num >> shift); | |
2211 | } | |
2212 | ||
a683cc34 SP |
2213 | static INLINE int |
2214 | fits_in_imm4 (offsetT num) | |
2215 | { | |
2216 | return (num & 0xf) == num; | |
2217 | } | |
2218 | ||
40fb9820 | 2219 | static i386_operand_type |
e3bb37b5 | 2220 | smallest_imm_type (offsetT num) |
252b5132 | 2221 | { |
40fb9820 | 2222 | i386_operand_type t; |
7ab9ffdd | 2223 | |
0dfbf9d7 | 2224 | operand_type_set (&t, 0); |
40fb9820 L |
2225 | t.bitfield.imm64 = 1; |
2226 | ||
2227 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2228 | { |
2229 | /* This code is disabled on the 486 because all the Imm1 forms | |
2230 | in the opcode table are slower on the i486. They're the | |
2231 | versions with the implicitly specified single-position | |
2232 | displacement, which has another syntax if you really want to | |
2233 | use that form. */ | |
40fb9820 L |
2234 | t.bitfield.imm1 = 1; |
2235 | t.bitfield.imm8 = 1; | |
2236 | t.bitfield.imm8s = 1; | |
2237 | t.bitfield.imm16 = 1; | |
2238 | t.bitfield.imm32 = 1; | |
2239 | t.bitfield.imm32s = 1; | |
2240 | } | |
2241 | else if (fits_in_signed_byte (num)) | |
2242 | { | |
2243 | t.bitfield.imm8 = 1; | |
2244 | t.bitfield.imm8s = 1; | |
2245 | t.bitfield.imm16 = 1; | |
2246 | t.bitfield.imm32 = 1; | |
2247 | t.bitfield.imm32s = 1; | |
2248 | } | |
2249 | else if (fits_in_unsigned_byte (num)) | |
2250 | { | |
2251 | t.bitfield.imm8 = 1; | |
2252 | t.bitfield.imm16 = 1; | |
2253 | t.bitfield.imm32 = 1; | |
2254 | t.bitfield.imm32s = 1; | |
2255 | } | |
2256 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2257 | { | |
2258 | t.bitfield.imm16 = 1; | |
2259 | t.bitfield.imm32 = 1; | |
2260 | t.bitfield.imm32s = 1; | |
2261 | } | |
2262 | else if (fits_in_signed_long (num)) | |
2263 | { | |
2264 | t.bitfield.imm32 = 1; | |
2265 | t.bitfield.imm32s = 1; | |
2266 | } | |
2267 | else if (fits_in_unsigned_long (num)) | |
2268 | t.bitfield.imm32 = 1; | |
2269 | ||
2270 | return t; | |
47926f60 | 2271 | } |
252b5132 | 2272 | |
847f7ad4 | 2273 | static offsetT |
e3bb37b5 | 2274 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2275 | { |
508866be | 2276 | addressT mask; |
ba2adb93 | 2277 | |
847f7ad4 AM |
2278 | switch (size) |
2279 | { | |
508866be L |
2280 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2281 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2282 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2283 | #ifdef BFD64 |
2284 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2285 | #endif | |
47926f60 | 2286 | default: abort (); |
847f7ad4 AM |
2287 | } |
2288 | ||
9de868bf L |
2289 | #ifdef BFD64 |
2290 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2291 | if (flag_code != CODE_64BIT | |
2292 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2293 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2294 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2295 | #endif |
ba2adb93 | 2296 | |
47926f60 | 2297 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2298 | { |
2299 | char buf1[40], buf2[40]; | |
2300 | ||
2301 | sprint_value (buf1, val); | |
2302 | sprint_value (buf2, val & mask); | |
2303 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2304 | } | |
2305 | return val & mask; | |
2306 | } | |
2307 | ||
c32fa91d L |
2308 | enum PREFIX_GROUP |
2309 | { | |
2310 | PREFIX_EXIST = 0, | |
2311 | PREFIX_LOCK, | |
2312 | PREFIX_REP, | |
04ef582a | 2313 | PREFIX_DS, |
c32fa91d L |
2314 | PREFIX_OTHER |
2315 | }; | |
2316 | ||
2317 | /* Returns | |
2318 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2319 | same class already exists. | |
2320 | b. PREFIX_LOCK if lock prefix is added. | |
2321 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2322 | d. PREFIX_DS if ds prefix is added. |
2323 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2324 | */ |
2325 | ||
2326 | static enum PREFIX_GROUP | |
e3bb37b5 | 2327 | add_prefix (unsigned int prefix) |
252b5132 | 2328 | { |
c32fa91d | 2329 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2330 | unsigned int q; |
252b5132 | 2331 | |
29b0f896 AM |
2332 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2333 | && flag_code == CODE_64BIT) | |
b1905489 | 2334 | { |
161a04f6 | 2335 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2336 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2337 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2338 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2339 | ret = PREFIX_EXIST; |
b1905489 JB |
2340 | q = REX_PREFIX; |
2341 | } | |
3e73aa7c | 2342 | else |
b1905489 JB |
2343 | { |
2344 | switch (prefix) | |
2345 | { | |
2346 | default: | |
2347 | abort (); | |
2348 | ||
b1905489 | 2349 | case DS_PREFIX_OPCODE: |
04ef582a L |
2350 | ret = PREFIX_DS; |
2351 | /* Fall through. */ | |
2352 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2353 | case ES_PREFIX_OPCODE: |
2354 | case FS_PREFIX_OPCODE: | |
2355 | case GS_PREFIX_OPCODE: | |
2356 | case SS_PREFIX_OPCODE: | |
2357 | q = SEG_PREFIX; | |
2358 | break; | |
2359 | ||
2360 | case REPNE_PREFIX_OPCODE: | |
2361 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2362 | q = REP_PREFIX; |
2363 | ret = PREFIX_REP; | |
2364 | break; | |
2365 | ||
b1905489 | 2366 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2367 | q = LOCK_PREFIX; |
2368 | ret = PREFIX_LOCK; | |
b1905489 JB |
2369 | break; |
2370 | ||
2371 | case FWAIT_OPCODE: | |
2372 | q = WAIT_PREFIX; | |
2373 | break; | |
2374 | ||
2375 | case ADDR_PREFIX_OPCODE: | |
2376 | q = ADDR_PREFIX; | |
2377 | break; | |
2378 | ||
2379 | case DATA_PREFIX_OPCODE: | |
2380 | q = DATA_PREFIX; | |
2381 | break; | |
2382 | } | |
2383 | if (i.prefix[q] != 0) | |
c32fa91d | 2384 | ret = PREFIX_EXIST; |
b1905489 | 2385 | } |
252b5132 | 2386 | |
b1905489 | 2387 | if (ret) |
252b5132 | 2388 | { |
b1905489 JB |
2389 | if (!i.prefix[q]) |
2390 | ++i.prefixes; | |
2391 | i.prefix[q] |= prefix; | |
252b5132 | 2392 | } |
b1905489 JB |
2393 | else |
2394 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2395 | |
252b5132 RH |
2396 | return ret; |
2397 | } | |
2398 | ||
2399 | static void | |
78f12dd3 | 2400 | update_code_flag (int value, int check) |
eecb386c | 2401 | { |
78f12dd3 L |
2402 | PRINTF_LIKE ((*as_error)); |
2403 | ||
1e9cc1c2 | 2404 | flag_code = (enum flag_code) value; |
40fb9820 L |
2405 | if (flag_code == CODE_64BIT) |
2406 | { | |
2407 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2408 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2409 | } |
2410 | else | |
2411 | { | |
2412 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2413 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2414 | } |
2415 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2416 | { |
78f12dd3 L |
2417 | if (check) |
2418 | as_error = as_fatal; | |
2419 | else | |
2420 | as_error = as_bad; | |
2421 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2422 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2423 | } |
40fb9820 | 2424 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2425 | { |
78f12dd3 L |
2426 | if (check) |
2427 | as_error = as_fatal; | |
2428 | else | |
2429 | as_error = as_bad; | |
2430 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2431 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2432 | } |
eecb386c AM |
2433 | stackop_size = '\0'; |
2434 | } | |
2435 | ||
78f12dd3 L |
2436 | static void |
2437 | set_code_flag (int value) | |
2438 | { | |
2439 | update_code_flag (value, 0); | |
2440 | } | |
2441 | ||
eecb386c | 2442 | static void |
e3bb37b5 | 2443 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2444 | { |
1e9cc1c2 | 2445 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2446 | if (flag_code != CODE_16BIT) |
2447 | abort (); | |
2448 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2449 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2450 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2451 | } |
2452 | ||
2453 | static void | |
e3bb37b5 | 2454 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2455 | { |
2456 | /* Find out if register prefixing is specified. */ | |
2457 | int ask_naked_reg = 0; | |
2458 | ||
2459 | SKIP_WHITESPACE (); | |
29b0f896 | 2460 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2461 | { |
d02603dc NC |
2462 | char *string; |
2463 | int e = get_symbol_name (&string); | |
252b5132 | 2464 | |
47926f60 | 2465 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2466 | ask_naked_reg = 1; |
47926f60 | 2467 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2468 | ask_naked_reg = -1; |
2469 | else | |
d0b47220 | 2470 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2471 | (void) restore_line_pointer (e); |
252b5132 RH |
2472 | } |
2473 | demand_empty_rest_of_line (); | |
c3332e24 | 2474 | |
252b5132 RH |
2475 | intel_syntax = syntax_flag; |
2476 | ||
2477 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2478 | allow_naked_reg = (intel_syntax |
2479 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2480 | else |
2481 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2482 | |
ee86248c | 2483 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2484 | |
e4a3b5a4 | 2485 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2486 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2487 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2488 | } |
2489 | ||
1efbbeb4 L |
2490 | static void |
2491 | set_intel_mnemonic (int mnemonic_flag) | |
2492 | { | |
e1d4d893 | 2493 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2494 | } |
2495 | ||
db51cc60 L |
2496 | static void |
2497 | set_allow_index_reg (int flag) | |
2498 | { | |
2499 | allow_index_reg = flag; | |
2500 | } | |
2501 | ||
cb19c032 | 2502 | static void |
7bab8ab5 | 2503 | set_check (int what) |
cb19c032 | 2504 | { |
7bab8ab5 JB |
2505 | enum check_kind *kind; |
2506 | const char *str; | |
2507 | ||
2508 | if (what) | |
2509 | { | |
2510 | kind = &operand_check; | |
2511 | str = "operand"; | |
2512 | } | |
2513 | else | |
2514 | { | |
2515 | kind = &sse_check; | |
2516 | str = "sse"; | |
2517 | } | |
2518 | ||
cb19c032 L |
2519 | SKIP_WHITESPACE (); |
2520 | ||
2521 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2522 | { | |
d02603dc NC |
2523 | char *string; |
2524 | int e = get_symbol_name (&string); | |
cb19c032 L |
2525 | |
2526 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2527 | *kind = check_none; |
cb19c032 | 2528 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2529 | *kind = check_warning; |
cb19c032 | 2530 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2531 | *kind = check_error; |
cb19c032 | 2532 | else |
7bab8ab5 | 2533 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2534 | (void) restore_line_pointer (e); |
cb19c032 L |
2535 | } |
2536 | else | |
7bab8ab5 | 2537 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2538 | |
2539 | demand_empty_rest_of_line (); | |
2540 | } | |
2541 | ||
8a9036a4 L |
2542 | static void |
2543 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2544 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2545 | { |
2546 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2547 | static const char *arch; | |
2548 | ||
2549 | /* Intel LIOM is only supported on ELF. */ | |
2550 | if (!IS_ELF) | |
2551 | return; | |
2552 | ||
2553 | if (!arch) | |
2554 | { | |
2555 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2556 | use default_arch. */ | |
2557 | arch = cpu_arch_name; | |
2558 | if (!arch) | |
2559 | arch = default_arch; | |
2560 | } | |
2561 | ||
81486035 L |
2562 | /* If we are targeting Intel MCU, we must enable it. */ |
2563 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2564 | || new_flag.bitfield.cpuiamcu) | |
2565 | return; | |
2566 | ||
3632d14b | 2567 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2568 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2569 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2570 | return; |
76ba9986 | 2571 | |
7a9068fe L |
2572 | /* If we are targeting Intel K1OM, we must enable it. */ |
2573 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2574 | || new_flag.bitfield.cpuk1om) | |
2575 | return; | |
2576 | ||
8a9036a4 L |
2577 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2578 | #endif | |
2579 | } | |
2580 | ||
e413e4e9 | 2581 | static void |
e3bb37b5 | 2582 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2583 | { |
47926f60 | 2584 | SKIP_WHITESPACE (); |
e413e4e9 | 2585 | |
29b0f896 | 2586 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2587 | { |
d02603dc NC |
2588 | char *string; |
2589 | int e = get_symbol_name (&string); | |
91d6fa6a | 2590 | unsigned int j; |
40fb9820 | 2591 | i386_cpu_flags flags; |
e413e4e9 | 2592 | |
91d6fa6a | 2593 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2594 | { |
91d6fa6a | 2595 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2596 | { |
91d6fa6a | 2597 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2598 | |
5c6af06e JB |
2599 | if (*string != '.') |
2600 | { | |
91d6fa6a | 2601 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2602 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2603 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2604 | if (flag_code == CODE_64BIT) |
2605 | { | |
2606 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2607 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2608 | } | |
2609 | else | |
2610 | { | |
2611 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2612 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2613 | } | |
91d6fa6a NC |
2614 | cpu_arch_isa = cpu_arch[j].type; |
2615 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2616 | if (!cpu_arch_tune_set) |
2617 | { | |
2618 | cpu_arch_tune = cpu_arch_isa; | |
2619 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2620 | } | |
5c6af06e JB |
2621 | break; |
2622 | } | |
40fb9820 | 2623 | |
293f5f65 L |
2624 | flags = cpu_flags_or (cpu_arch_flags, |
2625 | cpu_arch[j].flags); | |
81486035 | 2626 | |
5b64d091 | 2627 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2628 | { |
6305a203 L |
2629 | if (cpu_sub_arch_name) |
2630 | { | |
2631 | char *name = cpu_sub_arch_name; | |
2632 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2633 | cpu_arch[j].name, |
1bf57e9f | 2634 | (const char *) NULL); |
6305a203 L |
2635 | free (name); |
2636 | } | |
2637 | else | |
91d6fa6a | 2638 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2639 | cpu_arch_flags = flags; |
a586129e | 2640 | cpu_arch_isa_flags = flags; |
5c6af06e | 2641 | } |
0089dace L |
2642 | else |
2643 | cpu_arch_isa_flags | |
2644 | = cpu_flags_or (cpu_arch_isa_flags, | |
2645 | cpu_arch[j].flags); | |
d02603dc | 2646 | (void) restore_line_pointer (e); |
5c6af06e JB |
2647 | demand_empty_rest_of_line (); |
2648 | return; | |
e413e4e9 AM |
2649 | } |
2650 | } | |
293f5f65 L |
2651 | |
2652 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2653 | { | |
33eaf5de | 2654 | /* Disable an ISA extension. */ |
293f5f65 L |
2655 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2656 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2657 | { | |
2658 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2659 | cpu_noarch[j].flags); | |
2660 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2661 | { | |
2662 | if (cpu_sub_arch_name) | |
2663 | { | |
2664 | char *name = cpu_sub_arch_name; | |
2665 | cpu_sub_arch_name = concat (name, string, | |
2666 | (const char *) NULL); | |
2667 | free (name); | |
2668 | } | |
2669 | else | |
2670 | cpu_sub_arch_name = xstrdup (string); | |
2671 | cpu_arch_flags = flags; | |
2672 | cpu_arch_isa_flags = flags; | |
2673 | } | |
2674 | (void) restore_line_pointer (e); | |
2675 | demand_empty_rest_of_line (); | |
2676 | return; | |
2677 | } | |
2678 | ||
2679 | j = ARRAY_SIZE (cpu_arch); | |
2680 | } | |
2681 | ||
91d6fa6a | 2682 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2683 | as_bad (_("no such architecture: `%s'"), string); |
2684 | ||
2685 | *input_line_pointer = e; | |
2686 | } | |
2687 | else | |
2688 | as_bad (_("missing cpu architecture")); | |
2689 | ||
fddf5b5b AM |
2690 | no_cond_jump_promotion = 0; |
2691 | if (*input_line_pointer == ',' | |
29b0f896 | 2692 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2693 | { |
d02603dc NC |
2694 | char *string; |
2695 | char e; | |
2696 | ||
2697 | ++input_line_pointer; | |
2698 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2699 | |
2700 | if (strcmp (string, "nojumps") == 0) | |
2701 | no_cond_jump_promotion = 1; | |
2702 | else if (strcmp (string, "jumps") == 0) | |
2703 | ; | |
2704 | else | |
2705 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2706 | ||
d02603dc | 2707 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2708 | } |
2709 | ||
e413e4e9 AM |
2710 | demand_empty_rest_of_line (); |
2711 | } | |
2712 | ||
8a9036a4 L |
2713 | enum bfd_architecture |
2714 | i386_arch (void) | |
2715 | { | |
3632d14b | 2716 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2717 | { |
2718 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2719 | || flag_code != CODE_64BIT) | |
2720 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2721 | return bfd_arch_l1om; | |
2722 | } | |
7a9068fe L |
2723 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2724 | { | |
2725 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2726 | || flag_code != CODE_64BIT) | |
2727 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2728 | return bfd_arch_k1om; | |
2729 | } | |
81486035 L |
2730 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2731 | { | |
2732 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2733 | || flag_code == CODE_64BIT) | |
2734 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2735 | return bfd_arch_iamcu; | |
2736 | } | |
8a9036a4 L |
2737 | else |
2738 | return bfd_arch_i386; | |
2739 | } | |
2740 | ||
b9d79e03 | 2741 | unsigned long |
7016a5d5 | 2742 | i386_mach (void) |
b9d79e03 | 2743 | { |
351f65ca | 2744 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2745 | { |
3632d14b | 2746 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2747 | { |
351f65ca L |
2748 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2749 | || default_arch[6] != '\0') | |
8a9036a4 L |
2750 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2751 | return bfd_mach_l1om; | |
2752 | } | |
7a9068fe L |
2753 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2754 | { | |
2755 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2756 | || default_arch[6] != '\0') | |
2757 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2758 | return bfd_mach_k1om; | |
2759 | } | |
351f65ca | 2760 | else if (default_arch[6] == '\0') |
8a9036a4 | 2761 | return bfd_mach_x86_64; |
351f65ca L |
2762 | else |
2763 | return bfd_mach_x64_32; | |
8a9036a4 | 2764 | } |
5197d474 L |
2765 | else if (!strcmp (default_arch, "i386") |
2766 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2767 | { |
2768 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2769 | { | |
2770 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2771 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2772 | return bfd_mach_i386_iamcu; | |
2773 | } | |
2774 | else | |
2775 | return bfd_mach_i386_i386; | |
2776 | } | |
b9d79e03 | 2777 | else |
2b5d6a91 | 2778 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2779 | } |
b9d79e03 | 2780 | \f |
252b5132 | 2781 | void |
7016a5d5 | 2782 | md_begin (void) |
252b5132 RH |
2783 | { |
2784 | const char *hash_err; | |
2785 | ||
86fa6981 L |
2786 | /* Support pseudo prefixes like {disp32}. */ |
2787 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2788 | ||
47926f60 | 2789 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2790 | op_hash = hash_new (); |
2791 | ||
2792 | { | |
d3ce72d0 | 2793 | const insn_template *optab; |
29b0f896 | 2794 | templates *core_optab; |
252b5132 | 2795 | |
47926f60 KH |
2796 | /* Setup for loop. */ |
2797 | optab = i386_optab; | |
add39d23 | 2798 | core_optab = XNEW (templates); |
252b5132 RH |
2799 | core_optab->start = optab; |
2800 | ||
2801 | while (1) | |
2802 | { | |
2803 | ++optab; | |
2804 | if (optab->name == NULL | |
2805 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2806 | { | |
2807 | /* different name --> ship out current template list; | |
47926f60 | 2808 | add to hash table; & begin anew. */ |
252b5132 RH |
2809 | core_optab->end = optab; |
2810 | hash_err = hash_insert (op_hash, | |
2811 | (optab - 1)->name, | |
5a49b8ac | 2812 | (void *) core_optab); |
252b5132 RH |
2813 | if (hash_err) |
2814 | { | |
b37df7c4 | 2815 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2816 | (optab - 1)->name, |
2817 | hash_err); | |
2818 | } | |
2819 | if (optab->name == NULL) | |
2820 | break; | |
add39d23 | 2821 | core_optab = XNEW (templates); |
252b5132 RH |
2822 | core_optab->start = optab; |
2823 | } | |
2824 | } | |
2825 | } | |
2826 | ||
47926f60 | 2827 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2828 | reg_hash = hash_new (); |
2829 | { | |
29b0f896 | 2830 | const reg_entry *regtab; |
c3fe08fa | 2831 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2832 | |
c3fe08fa | 2833 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2834 | { |
5a49b8ac | 2835 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2836 | if (hash_err) |
b37df7c4 | 2837 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2838 | regtab->reg_name, |
2839 | hash_err); | |
252b5132 RH |
2840 | } |
2841 | } | |
2842 | ||
47926f60 | 2843 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2844 | { |
29b0f896 AM |
2845 | int c; |
2846 | char *p; | |
252b5132 RH |
2847 | |
2848 | for (c = 0; c < 256; c++) | |
2849 | { | |
3882b010 | 2850 | if (ISDIGIT (c)) |
252b5132 RH |
2851 | { |
2852 | digit_chars[c] = c; | |
2853 | mnemonic_chars[c] = c; | |
2854 | register_chars[c] = c; | |
2855 | operand_chars[c] = c; | |
2856 | } | |
3882b010 | 2857 | else if (ISLOWER (c)) |
252b5132 RH |
2858 | { |
2859 | mnemonic_chars[c] = c; | |
2860 | register_chars[c] = c; | |
2861 | operand_chars[c] = c; | |
2862 | } | |
3882b010 | 2863 | else if (ISUPPER (c)) |
252b5132 | 2864 | { |
3882b010 | 2865 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2866 | register_chars[c] = mnemonic_chars[c]; |
2867 | operand_chars[c] = c; | |
2868 | } | |
43234a1e | 2869 | else if (c == '{' || c == '}') |
86fa6981 L |
2870 | { |
2871 | mnemonic_chars[c] = c; | |
2872 | operand_chars[c] = c; | |
2873 | } | |
252b5132 | 2874 | |
3882b010 | 2875 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2876 | identifier_chars[c] = c; |
2877 | else if (c >= 128) | |
2878 | { | |
2879 | identifier_chars[c] = c; | |
2880 | operand_chars[c] = c; | |
2881 | } | |
2882 | } | |
2883 | ||
2884 | #ifdef LEX_AT | |
2885 | identifier_chars['@'] = '@'; | |
32137342 NC |
2886 | #endif |
2887 | #ifdef LEX_QM | |
2888 | identifier_chars['?'] = '?'; | |
2889 | operand_chars['?'] = '?'; | |
252b5132 | 2890 | #endif |
252b5132 | 2891 | digit_chars['-'] = '-'; |
c0f3af97 | 2892 | mnemonic_chars['_'] = '_'; |
791fe849 | 2893 | mnemonic_chars['-'] = '-'; |
0003779b | 2894 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2895 | identifier_chars['_'] = '_'; |
2896 | identifier_chars['.'] = '.'; | |
2897 | ||
2898 | for (p = operand_special_chars; *p != '\0'; p++) | |
2899 | operand_chars[(unsigned char) *p] = *p; | |
2900 | } | |
2901 | ||
a4447b93 RH |
2902 | if (flag_code == CODE_64BIT) |
2903 | { | |
ca19b261 KT |
2904 | #if defined (OBJ_COFF) && defined (TE_PE) |
2905 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2906 | ? 32 : 16); | |
2907 | #else | |
a4447b93 | 2908 | x86_dwarf2_return_column = 16; |
ca19b261 | 2909 | #endif |
61ff971f | 2910 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2911 | } |
2912 | else | |
2913 | { | |
2914 | x86_dwarf2_return_column = 8; | |
2915 | x86_cie_data_alignment = -4; | |
2916 | } | |
252b5132 RH |
2917 | } |
2918 | ||
2919 | void | |
e3bb37b5 | 2920 | i386_print_statistics (FILE *file) |
252b5132 RH |
2921 | { |
2922 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2923 | hash_print_statistics (file, "i386 register", reg_hash); | |
2924 | } | |
2925 | \f | |
252b5132 RH |
2926 | #ifdef DEBUG386 |
2927 | ||
ce8a8b2f | 2928 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2929 | static void pte (insn_template *); |
40fb9820 | 2930 | static void pt (i386_operand_type); |
e3bb37b5 L |
2931 | static void pe (expressionS *); |
2932 | static void ps (symbolS *); | |
252b5132 RH |
2933 | |
2934 | static void | |
e3bb37b5 | 2935 | pi (char *line, i386_insn *x) |
252b5132 | 2936 | { |
09137c09 | 2937 | unsigned int j; |
252b5132 RH |
2938 | |
2939 | fprintf (stdout, "%s: template ", line); | |
2940 | pte (&x->tm); | |
09f131f2 JH |
2941 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2942 | x->base_reg ? x->base_reg->reg_name : "none", | |
2943 | x->index_reg ? x->index_reg->reg_name : "none", | |
2944 | x->log2_scale_factor); | |
2945 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2946 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2947 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2948 | x->sib.base, x->sib.index, x->sib.scale); | |
2949 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2950 | (x->rex & REX_W) != 0, |
2951 | (x->rex & REX_R) != 0, | |
2952 | (x->rex & REX_X) != 0, | |
2953 | (x->rex & REX_B) != 0); | |
09137c09 | 2954 | for (j = 0; j < x->operands; j++) |
252b5132 | 2955 | { |
09137c09 SP |
2956 | fprintf (stdout, " #%d: ", j + 1); |
2957 | pt (x->types[j]); | |
252b5132 | 2958 | fprintf (stdout, "\n"); |
dc821c5f | 2959 | if (x->types[j].bitfield.reg |
09137c09 | 2960 | || x->types[j].bitfield.regmmx |
1b54b8d7 | 2961 | || x->types[j].bitfield.regsimd |
09137c09 SP |
2962 | || x->types[j].bitfield.sreg2 |
2963 | || x->types[j].bitfield.sreg3 | |
2964 | || x->types[j].bitfield.control | |
2965 | || x->types[j].bitfield.debug | |
2966 | || x->types[j].bitfield.test) | |
2967 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2968 | if (operand_type_check (x->types[j], imm)) | |
2969 | pe (x->op[j].imms); | |
2970 | if (operand_type_check (x->types[j], disp)) | |
2971 | pe (x->op[j].disps); | |
252b5132 RH |
2972 | } |
2973 | } | |
2974 | ||
2975 | static void | |
d3ce72d0 | 2976 | pte (insn_template *t) |
252b5132 | 2977 | { |
09137c09 | 2978 | unsigned int j; |
252b5132 | 2979 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2980 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2981 | if (t->extension_opcode != None) |
2982 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2983 | if (t->opcode_modifier.d) |
252b5132 | 2984 | fprintf (stdout, "D"); |
40fb9820 | 2985 | if (t->opcode_modifier.w) |
252b5132 RH |
2986 | fprintf (stdout, "W"); |
2987 | fprintf (stdout, "\n"); | |
09137c09 | 2988 | for (j = 0; j < t->operands; j++) |
252b5132 | 2989 | { |
09137c09 SP |
2990 | fprintf (stdout, " #%d type ", j + 1); |
2991 | pt (t->operand_types[j]); | |
252b5132 RH |
2992 | fprintf (stdout, "\n"); |
2993 | } | |
2994 | } | |
2995 | ||
2996 | static void | |
e3bb37b5 | 2997 | pe (expressionS *e) |
252b5132 | 2998 | { |
24eab124 | 2999 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3000 | fprintf (stdout, " add_number %ld (%lx)\n", |
3001 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3002 | if (e->X_add_symbol) |
3003 | { | |
3004 | fprintf (stdout, " add_symbol "); | |
3005 | ps (e->X_add_symbol); | |
3006 | fprintf (stdout, "\n"); | |
3007 | } | |
3008 | if (e->X_op_symbol) | |
3009 | { | |
3010 | fprintf (stdout, " op_symbol "); | |
3011 | ps (e->X_op_symbol); | |
3012 | fprintf (stdout, "\n"); | |
3013 | } | |
3014 | } | |
3015 | ||
3016 | static void | |
e3bb37b5 | 3017 | ps (symbolS *s) |
252b5132 RH |
3018 | { |
3019 | fprintf (stdout, "%s type %s%s", | |
3020 | S_GET_NAME (s), | |
3021 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3022 | segment_name (S_GET_SEGMENT (s))); | |
3023 | } | |
3024 | ||
7b81dfbb | 3025 | static struct type_name |
252b5132 | 3026 | { |
40fb9820 L |
3027 | i386_operand_type mask; |
3028 | const char *name; | |
252b5132 | 3029 | } |
7b81dfbb | 3030 | const type_names[] = |
252b5132 | 3031 | { |
40fb9820 L |
3032 | { OPERAND_TYPE_REG8, "r8" }, |
3033 | { OPERAND_TYPE_REG16, "r16" }, | |
3034 | { OPERAND_TYPE_REG32, "r32" }, | |
3035 | { OPERAND_TYPE_REG64, "r64" }, | |
3036 | { OPERAND_TYPE_IMM8, "i8" }, | |
3037 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3038 | { OPERAND_TYPE_IMM16, "i16" }, | |
3039 | { OPERAND_TYPE_IMM32, "i32" }, | |
3040 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3041 | { OPERAND_TYPE_IMM64, "i64" }, | |
3042 | { OPERAND_TYPE_IMM1, "i1" }, | |
3043 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3044 | { OPERAND_TYPE_DISP8, "d8" }, | |
3045 | { OPERAND_TYPE_DISP16, "d16" }, | |
3046 | { OPERAND_TYPE_DISP32, "d32" }, | |
3047 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3048 | { OPERAND_TYPE_DISP64, "d64" }, | |
3049 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3050 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3051 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3052 | { OPERAND_TYPE_TEST, "test reg" }, | |
3053 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3054 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3055 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
3056 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
3057 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
3058 | { OPERAND_TYPE_ACC, "Acc" }, | |
3059 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
3060 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
3061 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3062 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3063 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3064 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 3065 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
3066 | }; |
3067 | ||
3068 | static void | |
40fb9820 | 3069 | pt (i386_operand_type t) |
252b5132 | 3070 | { |
40fb9820 | 3071 | unsigned int j; |
c6fb90c8 | 3072 | i386_operand_type a; |
252b5132 | 3073 | |
40fb9820 | 3074 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3075 | { |
3076 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 3077 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
3078 | fprintf (stdout, "%s, ", type_names[j].name); |
3079 | } | |
252b5132 RH |
3080 | fflush (stdout); |
3081 | } | |
3082 | ||
3083 | #endif /* DEBUG386 */ | |
3084 | \f | |
252b5132 | 3085 | static bfd_reloc_code_real_type |
3956db08 | 3086 | reloc (unsigned int size, |
64e74474 AM |
3087 | int pcrel, |
3088 | int sign, | |
3089 | bfd_reloc_code_real_type other) | |
252b5132 | 3090 | { |
47926f60 | 3091 | if (other != NO_RELOC) |
3956db08 | 3092 | { |
91d6fa6a | 3093 | reloc_howto_type *rel; |
3956db08 JB |
3094 | |
3095 | if (size == 8) | |
3096 | switch (other) | |
3097 | { | |
64e74474 AM |
3098 | case BFD_RELOC_X86_64_GOT32: |
3099 | return BFD_RELOC_X86_64_GOT64; | |
3100 | break; | |
553d1284 L |
3101 | case BFD_RELOC_X86_64_GOTPLT64: |
3102 | return BFD_RELOC_X86_64_GOTPLT64; | |
3103 | break; | |
64e74474 AM |
3104 | case BFD_RELOC_X86_64_PLTOFF64: |
3105 | return BFD_RELOC_X86_64_PLTOFF64; | |
3106 | break; | |
3107 | case BFD_RELOC_X86_64_GOTPC32: | |
3108 | other = BFD_RELOC_X86_64_GOTPC64; | |
3109 | break; | |
3110 | case BFD_RELOC_X86_64_GOTPCREL: | |
3111 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3112 | break; | |
3113 | case BFD_RELOC_X86_64_TPOFF32: | |
3114 | other = BFD_RELOC_X86_64_TPOFF64; | |
3115 | break; | |
3116 | case BFD_RELOC_X86_64_DTPOFF32: | |
3117 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3118 | break; | |
3119 | default: | |
3120 | break; | |
3956db08 | 3121 | } |
e05278af | 3122 | |
8ce3d284 | 3123 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3124 | if (other == BFD_RELOC_SIZE32) |
3125 | { | |
3126 | if (size == 8) | |
1ab668bf | 3127 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3128 | if (pcrel) |
1ab668bf AM |
3129 | { |
3130 | as_bad (_("there are no pc-relative size relocations")); | |
3131 | return NO_RELOC; | |
3132 | } | |
8fd4256d | 3133 | } |
8ce3d284 | 3134 | #endif |
8fd4256d | 3135 | |
e05278af | 3136 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3137 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3138 | sign = -1; |
3139 | ||
91d6fa6a NC |
3140 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3141 | if (!rel) | |
3956db08 | 3142 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3143 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3144 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3145 | bfd_get_reloc_size (rel), |
3956db08 | 3146 | size); |
91d6fa6a | 3147 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3148 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3149 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3150 | && !sign) |
91d6fa6a | 3151 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3152 | && sign > 0)) |
3956db08 JB |
3153 | as_bad (_("relocated field and relocation type differ in signedness")); |
3154 | else | |
3155 | return other; | |
3156 | return NO_RELOC; | |
3157 | } | |
252b5132 RH |
3158 | |
3159 | if (pcrel) | |
3160 | { | |
3e73aa7c | 3161 | if (!sign) |
3956db08 | 3162 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3163 | switch (size) |
3164 | { | |
3165 | case 1: return BFD_RELOC_8_PCREL; | |
3166 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3167 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3168 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3169 | } |
3956db08 | 3170 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3171 | } |
3172 | else | |
3173 | { | |
3956db08 | 3174 | if (sign > 0) |
e5cb08ac | 3175 | switch (size) |
3e73aa7c JH |
3176 | { |
3177 | case 4: return BFD_RELOC_X86_64_32S; | |
3178 | } | |
3179 | else | |
3180 | switch (size) | |
3181 | { | |
3182 | case 1: return BFD_RELOC_8; | |
3183 | case 2: return BFD_RELOC_16; | |
3184 | case 4: return BFD_RELOC_32; | |
3185 | case 8: return BFD_RELOC_64; | |
3186 | } | |
3956db08 JB |
3187 | as_bad (_("cannot do %s %u byte relocation"), |
3188 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3189 | } |
3190 | ||
0cc9e1d3 | 3191 | return NO_RELOC; |
252b5132 RH |
3192 | } |
3193 | ||
47926f60 KH |
3194 | /* Here we decide which fixups can be adjusted to make them relative to |
3195 | the beginning of the section instead of the symbol. Basically we need | |
3196 | to make sure that the dynamic relocations are done correctly, so in | |
3197 | some cases we force the original symbol to be used. */ | |
3198 | ||
252b5132 | 3199 | int |
e3bb37b5 | 3200 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3201 | { |
6d249963 | 3202 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3203 | if (!IS_ELF) |
31312f95 AM |
3204 | return 1; |
3205 | ||
a161fe53 AM |
3206 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3207 | mode. */ | |
3208 | if (use_rela_relocations | |
3209 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3210 | && fixP->fx_pcrel) | |
252b5132 | 3211 | return 0; |
31312f95 | 3212 | |
8d01d9a9 AJ |
3213 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3214 | and changed later by validate_fix. */ | |
3215 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3216 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3217 | return 0; | |
3218 | ||
8fd4256d L |
3219 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3220 | for size relocations. */ | |
3221 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3222 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3223 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3224 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3225 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3226 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3227 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3228 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3229 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3230 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3231 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3232 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3233 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3234 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3235 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3236 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3237 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3238 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3239 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3240 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3241 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3242 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3243 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3244 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3245 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3246 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3247 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3248 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3249 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3250 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3251 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3252 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3253 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3254 | return 0; | |
31312f95 | 3255 | #endif |
252b5132 RH |
3256 | return 1; |
3257 | } | |
252b5132 | 3258 | |
b4cac588 | 3259 | static int |
e3bb37b5 | 3260 | intel_float_operand (const char *mnemonic) |
252b5132 | 3261 | { |
9306ca4a JB |
3262 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3263 | operands, hence the code here is free to improperly handle opcodes that | |
3264 | have no operands (for better performance and smaller code). */ | |
3265 | ||
3266 | if (mnemonic[0] != 'f') | |
3267 | return 0; /* non-math */ | |
3268 | ||
3269 | switch (mnemonic[1]) | |
3270 | { | |
3271 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3272 | the fs segment override prefix not currently handled because no | |
3273 | call path can make opcodes without operands get here */ | |
3274 | case 'i': | |
3275 | return 2 /* integer op */; | |
3276 | case 'l': | |
3277 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3278 | return 3; /* fldcw/fldenv */ | |
3279 | break; | |
3280 | case 'n': | |
3281 | if (mnemonic[2] != 'o' /* fnop */) | |
3282 | return 3; /* non-waiting control op */ | |
3283 | break; | |
3284 | case 'r': | |
3285 | if (mnemonic[2] == 's') | |
3286 | return 3; /* frstor/frstpm */ | |
3287 | break; | |
3288 | case 's': | |
3289 | if (mnemonic[2] == 'a') | |
3290 | return 3; /* fsave */ | |
3291 | if (mnemonic[2] == 't') | |
3292 | { | |
3293 | switch (mnemonic[3]) | |
3294 | { | |
3295 | case 'c': /* fstcw */ | |
3296 | case 'd': /* fstdw */ | |
3297 | case 'e': /* fstenv */ | |
3298 | case 's': /* fsts[gw] */ | |
3299 | return 3; | |
3300 | } | |
3301 | } | |
3302 | break; | |
3303 | case 'x': | |
3304 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3305 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3306 | break; | |
3307 | } | |
252b5132 | 3308 | |
9306ca4a | 3309 | return 1; |
252b5132 RH |
3310 | } |
3311 | ||
c0f3af97 L |
3312 | /* Build the VEX prefix. */ |
3313 | ||
3314 | static void | |
d3ce72d0 | 3315 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3316 | { |
3317 | unsigned int register_specifier; | |
3318 | unsigned int implied_prefix; | |
3319 | unsigned int vector_length; | |
3320 | ||
3321 | /* Check register specifier. */ | |
3322 | if (i.vex.register_specifier) | |
43234a1e L |
3323 | { |
3324 | register_specifier = | |
3325 | ~register_number (i.vex.register_specifier) & 0xf; | |
3326 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3327 | } | |
c0f3af97 L |
3328 | else |
3329 | register_specifier = 0xf; | |
3330 | ||
33eaf5de | 3331 | /* Use 2-byte VEX prefix by swapping destination and source |
fa99fab2 | 3332 | operand. */ |
86fa6981 L |
3333 | if (i.vec_encoding != vex_encoding_vex3 |
3334 | && i.dir_encoding == dir_encoding_default | |
fa99fab2 | 3335 | && i.operands == i.reg_operands |
7f399153 | 3336 | && i.tm.opcode_modifier.vexopcode == VEX0F |
86fa6981 | 3337 | && i.tm.opcode_modifier.load |
fa99fab2 L |
3338 | && i.rex == REX_B) |
3339 | { | |
3340 | unsigned int xchg = i.operands - 1; | |
3341 | union i386_op temp_op; | |
3342 | i386_operand_type temp_type; | |
3343 | ||
3344 | temp_type = i.types[xchg]; | |
3345 | i.types[xchg] = i.types[0]; | |
3346 | i.types[0] = temp_type; | |
3347 | temp_op = i.op[xchg]; | |
3348 | i.op[xchg] = i.op[0]; | |
3349 | i.op[0] = temp_op; | |
3350 | ||
9c2799c2 | 3351 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3352 | |
3353 | i.rex = REX_R; | |
3354 | xchg = i.rm.regmem; | |
3355 | i.rm.regmem = i.rm.reg; | |
3356 | i.rm.reg = xchg; | |
3357 | ||
3358 | /* Use the next insn. */ | |
3359 | i.tm = t[1]; | |
3360 | } | |
3361 | ||
539f890d L |
3362 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3363 | vector_length = avxscalar; | |
10c17abd JB |
3364 | else if (i.tm.opcode_modifier.vex == VEX256) |
3365 | vector_length = 1; | |
539f890d | 3366 | else |
10c17abd | 3367 | { |
56522fc5 | 3368 | unsigned int op; |
10c17abd | 3369 | |
c7213af9 L |
3370 | /* Determine vector length from the last multi-length vector |
3371 | operand. */ | |
10c17abd | 3372 | vector_length = 0; |
56522fc5 | 3373 | for (op = t->operands; op--;) |
10c17abd JB |
3374 | if (t->operand_types[op].bitfield.xmmword |
3375 | && t->operand_types[op].bitfield.ymmword | |
3376 | && i.types[op].bitfield.ymmword) | |
3377 | { | |
3378 | vector_length = 1; | |
3379 | break; | |
3380 | } | |
3381 | } | |
c0f3af97 L |
3382 | |
3383 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3384 | { | |
3385 | case 0: | |
3386 | implied_prefix = 0; | |
3387 | break; | |
3388 | case DATA_PREFIX_OPCODE: | |
3389 | implied_prefix = 1; | |
3390 | break; | |
3391 | case REPE_PREFIX_OPCODE: | |
3392 | implied_prefix = 2; | |
3393 | break; | |
3394 | case REPNE_PREFIX_OPCODE: | |
3395 | implied_prefix = 3; | |
3396 | break; | |
3397 | default: | |
3398 | abort (); | |
3399 | } | |
3400 | ||
3401 | /* Use 2-byte VEX prefix if possible. */ | |
86fa6981 L |
3402 | if (i.vec_encoding != vex_encoding_vex3 |
3403 | && i.tm.opcode_modifier.vexopcode == VEX0F | |
04251de0 | 3404 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
3405 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3406 | { | |
3407 | /* 2-byte VEX prefix. */ | |
3408 | unsigned int r; | |
3409 | ||
3410 | i.vex.length = 2; | |
3411 | i.vex.bytes[0] = 0xc5; | |
3412 | ||
3413 | /* Check the REX.R bit. */ | |
3414 | r = (i.rex & REX_R) ? 0 : 1; | |
3415 | i.vex.bytes[1] = (r << 7 | |
3416 | | register_specifier << 3 | |
3417 | | vector_length << 2 | |
3418 | | implied_prefix); | |
3419 | } | |
3420 | else | |
3421 | { | |
3422 | /* 3-byte VEX prefix. */ | |
3423 | unsigned int m, w; | |
3424 | ||
f88c9eb0 | 3425 | i.vex.length = 3; |
f88c9eb0 | 3426 | |
7f399153 | 3427 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3428 | { |
7f399153 L |
3429 | case VEX0F: |
3430 | m = 0x1; | |
80de6e00 | 3431 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3432 | break; |
3433 | case VEX0F38: | |
3434 | m = 0x2; | |
80de6e00 | 3435 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3436 | break; |
3437 | case VEX0F3A: | |
3438 | m = 0x3; | |
80de6e00 | 3439 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3440 | break; |
3441 | case XOP08: | |
5dd85c99 SP |
3442 | m = 0x8; |
3443 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3444 | break; |
3445 | case XOP09: | |
f88c9eb0 SP |
3446 | m = 0x9; |
3447 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3448 | break; |
3449 | case XOP0A: | |
f88c9eb0 SP |
3450 | m = 0xa; |
3451 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3452 | break; |
3453 | default: | |
3454 | abort (); | |
f88c9eb0 | 3455 | } |
c0f3af97 | 3456 | |
c0f3af97 L |
3457 | /* The high 3 bits of the second VEX byte are 1's compliment |
3458 | of RXB bits from REX. */ | |
3459 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3460 | ||
3461 | /* Check the REX.W bit. */ | |
3462 | w = (i.rex & REX_W) ? 1 : 0; | |
b28d1bda IT |
3463 | if (i.tm.opcode_modifier.vexw == VEXW1) |
3464 | w = 1; | |
c0f3af97 L |
3465 | |
3466 | i.vex.bytes[2] = (w << 7 | |
3467 | | register_specifier << 3 | |
3468 | | vector_length << 2 | |
3469 | | implied_prefix); | |
3470 | } | |
3471 | } | |
3472 | ||
e771e7c9 JB |
3473 | static INLINE bfd_boolean |
3474 | is_evex_encoding (const insn_template *t) | |
3475 | { | |
7091c612 | 3476 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 JB |
3477 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
3478 | || t->opcode_modifier.staticrounding || t->opcode_modifier.sae; | |
3479 | } | |
3480 | ||
43234a1e L |
3481 | /* Build the EVEX prefix. */ |
3482 | ||
3483 | static void | |
3484 | build_evex_prefix (void) | |
3485 | { | |
3486 | unsigned int register_specifier; | |
3487 | unsigned int implied_prefix; | |
3488 | unsigned int m, w; | |
3489 | rex_byte vrex_used = 0; | |
3490 | ||
3491 | /* Check register specifier. */ | |
3492 | if (i.vex.register_specifier) | |
3493 | { | |
3494 | gas_assert ((i.vrex & REX_X) == 0); | |
3495 | ||
3496 | register_specifier = i.vex.register_specifier->reg_num; | |
3497 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3498 | register_specifier += 8; | |
3499 | /* The upper 16 registers are encoded in the fourth byte of the | |
3500 | EVEX prefix. */ | |
3501 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3502 | i.vex.bytes[3] = 0x8; | |
3503 | register_specifier = ~register_specifier & 0xf; | |
3504 | } | |
3505 | else | |
3506 | { | |
3507 | register_specifier = 0xf; | |
3508 | ||
3509 | /* Encode upper 16 vector index register in the fourth byte of | |
3510 | the EVEX prefix. */ | |
3511 | if (!(i.vrex & REX_X)) | |
3512 | i.vex.bytes[3] = 0x8; | |
3513 | else | |
3514 | vrex_used |= REX_X; | |
3515 | } | |
3516 | ||
3517 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3518 | { | |
3519 | case 0: | |
3520 | implied_prefix = 0; | |
3521 | break; | |
3522 | case DATA_PREFIX_OPCODE: | |
3523 | implied_prefix = 1; | |
3524 | break; | |
3525 | case REPE_PREFIX_OPCODE: | |
3526 | implied_prefix = 2; | |
3527 | break; | |
3528 | case REPNE_PREFIX_OPCODE: | |
3529 | implied_prefix = 3; | |
3530 | break; | |
3531 | default: | |
3532 | abort (); | |
3533 | } | |
3534 | ||
3535 | /* 4 byte EVEX prefix. */ | |
3536 | i.vex.length = 4; | |
3537 | i.vex.bytes[0] = 0x62; | |
3538 | ||
3539 | /* mmmm bits. */ | |
3540 | switch (i.tm.opcode_modifier.vexopcode) | |
3541 | { | |
3542 | case VEX0F: | |
3543 | m = 1; | |
3544 | break; | |
3545 | case VEX0F38: | |
3546 | m = 2; | |
3547 | break; | |
3548 | case VEX0F3A: | |
3549 | m = 3; | |
3550 | break; | |
3551 | default: | |
3552 | abort (); | |
3553 | break; | |
3554 | } | |
3555 | ||
3556 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3557 | bits from REX. */ | |
3558 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3559 | ||
3560 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3561 | REX_R bit in VREX. */ | |
3562 | if (!(i.vrex & REX_R)) | |
3563 | i.vex.bytes[1] |= 0x10; | |
3564 | else | |
3565 | vrex_used |= REX_R; | |
3566 | ||
3567 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3568 | { | |
3569 | /* When all operands are registers, the REX_X bit in REX is not | |
3570 | used. We reuse it to encode the upper 16 registers, which is | |
3571 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3572 | as 1's compliment. */ | |
3573 | if ((i.vrex & REX_B)) | |
3574 | { | |
3575 | vrex_used |= REX_B; | |
3576 | i.vex.bytes[1] &= ~0x40; | |
3577 | } | |
3578 | } | |
3579 | ||
3580 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3581 | i.vrex &= ~vrex_used; | |
3582 | gas_assert (i.vrex == 0); | |
3583 | ||
3584 | /* Check the REX.W bit. */ | |
3585 | w = (i.rex & REX_W) ? 1 : 0; | |
3586 | if (i.tm.opcode_modifier.vexw) | |
3587 | { | |
3588 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
3589 | w = 1; | |
3590 | } | |
3591 | /* If w is not set it means we are dealing with WIG instruction. */ | |
3592 | else if (!w) | |
3593 | { | |
3594 | if (evexwig == evexw1) | |
3595 | w = 1; | |
3596 | } | |
3597 | ||
3598 | /* Encode the U bit. */ | |
3599 | implied_prefix |= 0x4; | |
3600 | ||
3601 | /* The third byte of the EVEX prefix. */ | |
3602 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3603 | ||
3604 | /* The fourth byte of the EVEX prefix. */ | |
3605 | /* The zeroing-masking bit. */ | |
3606 | if (i.mask && i.mask->zeroing) | |
3607 | i.vex.bytes[3] |= 0x80; | |
3608 | ||
3609 | /* Don't always set the broadcast bit if there is no RC. */ | |
3610 | if (!i.rounding) | |
3611 | { | |
3612 | /* Encode the vector length. */ | |
3613 | unsigned int vec_length; | |
3614 | ||
e771e7c9 JB |
3615 | if (!i.tm.opcode_modifier.evex |
3616 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3617 | { | |
56522fc5 | 3618 | unsigned int op; |
e771e7c9 | 3619 | |
c7213af9 L |
3620 | /* Determine vector length from the last multi-length vector |
3621 | operand. */ | |
e771e7c9 | 3622 | vec_length = 0; |
56522fc5 | 3623 | for (op = i.operands; op--;) |
e771e7c9 JB |
3624 | if (i.tm.operand_types[op].bitfield.xmmword |
3625 | + i.tm.operand_types[op].bitfield.ymmword | |
3626 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3627 | { | |
3628 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3629 | { |
3630 | i.tm.opcode_modifier.evex = EVEX512; | |
3631 | break; | |
3632 | } | |
e771e7c9 | 3633 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3634 | { |
3635 | i.tm.opcode_modifier.evex = EVEX256; | |
3636 | break; | |
3637 | } | |
e771e7c9 | 3638 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3639 | { |
3640 | i.tm.opcode_modifier.evex = EVEX128; | |
3641 | break; | |
3642 | } | |
625cbd7a JB |
3643 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3644 | { | |
4a1b91ea | 3645 | switch (i.broadcast->bytes) |
625cbd7a JB |
3646 | { |
3647 | case 64: | |
3648 | i.tm.opcode_modifier.evex = EVEX512; | |
3649 | break; | |
3650 | case 32: | |
3651 | i.tm.opcode_modifier.evex = EVEX256; | |
3652 | break; | |
3653 | case 16: | |
3654 | i.tm.opcode_modifier.evex = EVEX128; | |
3655 | break; | |
3656 | default: | |
c7213af9 | 3657 | abort (); |
625cbd7a | 3658 | } |
c7213af9 | 3659 | break; |
625cbd7a | 3660 | } |
e771e7c9 | 3661 | } |
c7213af9 | 3662 | |
56522fc5 | 3663 | if (op >= MAX_OPERANDS) |
c7213af9 | 3664 | abort (); |
e771e7c9 JB |
3665 | } |
3666 | ||
43234a1e L |
3667 | switch (i.tm.opcode_modifier.evex) |
3668 | { | |
3669 | case EVEXLIG: /* LL' is ignored */ | |
3670 | vec_length = evexlig << 5; | |
3671 | break; | |
3672 | case EVEX128: | |
3673 | vec_length = 0 << 5; | |
3674 | break; | |
3675 | case EVEX256: | |
3676 | vec_length = 1 << 5; | |
3677 | break; | |
3678 | case EVEX512: | |
3679 | vec_length = 2 << 5; | |
3680 | break; | |
3681 | default: | |
3682 | abort (); | |
3683 | break; | |
3684 | } | |
3685 | i.vex.bytes[3] |= vec_length; | |
3686 | /* Encode the broadcast bit. */ | |
3687 | if (i.broadcast) | |
3688 | i.vex.bytes[3] |= 0x10; | |
3689 | } | |
3690 | else | |
3691 | { | |
3692 | if (i.rounding->type != saeonly) | |
3693 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3694 | else | |
d3d3c6db | 3695 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3696 | } |
3697 | ||
3698 | if (i.mask && i.mask->mask) | |
3699 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3700 | } | |
3701 | ||
65da13b5 L |
3702 | static void |
3703 | process_immext (void) | |
3704 | { | |
3705 | expressionS *exp; | |
3706 | ||
4c692bc7 JB |
3707 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3708 | && i.operands > 0) | |
65da13b5 | 3709 | { |
4c692bc7 JB |
3710 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3711 | with an opcode suffix which is coded in the same place as an | |
3712 | 8-bit immediate field would be. | |
3713 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3714 | unsigned int x; |
3715 | ||
3716 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3717 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3718 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3719 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3720 | i.tm.name); | |
3721 | ||
3722 | i.operands = 0; | |
65da13b5 L |
3723 | } |
3724 | ||
9916071f AP |
3725 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3726 | { | |
3727 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3728 | suffix which is coded in the same place as an 8-bit immediate | |
3729 | field would be. | |
3730 | Here we check those operands and remove them afterwards. */ | |
3731 | unsigned int x; | |
3732 | ||
3733 | if (i.operands != 3) | |
3734 | abort(); | |
3735 | ||
3736 | for (x = 0; x < 2; x++) | |
3737 | if (register_number (i.op[x].regs) != x) | |
3738 | goto bad_register_operand; | |
3739 | ||
3740 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3741 | if (register_number (i.op[x].regs) | |
3742 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3743 | { | |
3744 | bad_register_operand: | |
3745 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3746 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3747 | i.tm.name); | |
3748 | } | |
3749 | ||
3750 | i.operands = 0; | |
3751 | } | |
3752 | ||
c0f3af97 | 3753 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3754 | which is coded in the same place as an 8-bit immediate field |
3755 | would be. Here we fake an 8-bit immediate operand from the | |
3756 | opcode suffix stored in tm.extension_opcode. | |
3757 | ||
c1e679ec | 3758 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3759 | 3 argument instructions. */ |
65da13b5 | 3760 | |
43234a1e | 3761 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3762 | && (i.operands <= 2 |
43234a1e | 3763 | || ((i.tm.opcode_modifier.vex |
e771e7c9 JB |
3764 | || i.tm.opcode_modifier.vexopcode |
3765 | || is_evex_encoding (&i.tm)) | |
7ab9ffdd | 3766 | && i.operands <= 4))); |
65da13b5 L |
3767 | |
3768 | exp = &im_expressions[i.imm_operands++]; | |
3769 | i.op[i.operands].imms = exp; | |
3770 | i.types[i.operands] = imm8; | |
3771 | i.operands++; | |
3772 | exp->X_op = O_constant; | |
3773 | exp->X_add_number = i.tm.extension_opcode; | |
3774 | i.tm.extension_opcode = None; | |
3775 | } | |
3776 | ||
42164a71 L |
3777 | |
3778 | static int | |
3779 | check_hle (void) | |
3780 | { | |
3781 | switch (i.tm.opcode_modifier.hleprefixok) | |
3782 | { | |
3783 | default: | |
3784 | abort (); | |
82c2def5 | 3785 | case HLEPrefixNone: |
165de32a L |
3786 | as_bad (_("invalid instruction `%s' after `%s'"), |
3787 | i.tm.name, i.hle_prefix); | |
42164a71 | 3788 | return 0; |
82c2def5 | 3789 | case HLEPrefixLock: |
42164a71 L |
3790 | if (i.prefix[LOCK_PREFIX]) |
3791 | return 1; | |
165de32a | 3792 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3793 | return 0; |
82c2def5 | 3794 | case HLEPrefixAny: |
42164a71 | 3795 | return 1; |
82c2def5 | 3796 | case HLEPrefixRelease: |
42164a71 L |
3797 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3798 | { | |
3799 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3800 | i.tm.name); | |
3801 | return 0; | |
3802 | } | |
3803 | if (i.mem_operands == 0 | |
3804 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3805 | { | |
3806 | as_bad (_("memory destination needed for instruction `%s'" | |
3807 | " after `xrelease'"), i.tm.name); | |
3808 | return 0; | |
3809 | } | |
3810 | return 1; | |
3811 | } | |
3812 | } | |
3813 | ||
b6f8c7c4 L |
3814 | /* Try the shortest encoding by shortening operand size. */ |
3815 | ||
3816 | static void | |
3817 | optimize_encoding (void) | |
3818 | { | |
3819 | int j; | |
3820 | ||
3821 | if (optimize_for_space | |
3822 | && i.reg_operands == 1 | |
3823 | && i.imm_operands == 1 | |
3824 | && !i.types[1].bitfield.byte | |
3825 | && i.op[0].imms->X_op == O_constant | |
3826 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
3827 | && ((i.tm.base_opcode == 0xa8 | |
3828 | && i.tm.extension_opcode == None) | |
3829 | || (i.tm.base_opcode == 0xf6 | |
3830 | && i.tm.extension_opcode == 0x0))) | |
3831 | { | |
3832 | /* Optimize: -Os: | |
3833 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
3834 | */ | |
3835 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
3836 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
3837 | { | |
3838 | i.types[1].bitfield.byte = 1; | |
3839 | /* Ignore the suffix. */ | |
3840 | i.suffix = 0; | |
3841 | if (base_regnum >= 4 | |
3842 | && !(i.op[1].regs->reg_flags & RegRex)) | |
3843 | { | |
3844 | /* Handle SP, BP, SI and DI registers. */ | |
3845 | if (i.types[1].bitfield.word) | |
3846 | j = 16; | |
3847 | else if (i.types[1].bitfield.dword) | |
3848 | j = 32; | |
3849 | else | |
3850 | j = 48; | |
3851 | i.op[1].regs -= j; | |
3852 | } | |
3853 | } | |
3854 | } | |
3855 | else if (flag_code == CODE_64BIT | |
d3d50934 L |
3856 | && ((i.types[1].bitfield.qword |
3857 | && i.reg_operands == 1 | |
b6f8c7c4 L |
3858 | && i.imm_operands == 1 |
3859 | && i.op[0].imms->X_op == O_constant | |
3860 | && ((i.tm.base_opcode == 0xb0 | |
3861 | && i.tm.extension_opcode == None | |
3862 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
3863 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
3864 | && (((i.tm.base_opcode == 0x24 | |
3865 | || i.tm.base_opcode == 0xa8) | |
3866 | && i.tm.extension_opcode == None) | |
3867 | || (i.tm.base_opcode == 0x80 | |
3868 | && i.tm.extension_opcode == 0x4) | |
3869 | || ((i.tm.base_opcode == 0xf6 | |
3870 | || i.tm.base_opcode == 0xc6) | |
3871 | && i.tm.extension_opcode == 0x0))))) | |
d3d50934 L |
3872 | || (i.types[0].bitfield.qword |
3873 | && ((i.reg_operands == 2 | |
3874 | && i.op[0].regs == i.op[1].regs | |
3875 | && ((i.tm.base_opcode == 0x30 | |
3876 | || i.tm.base_opcode == 0x28) | |
3877 | && i.tm.extension_opcode == None)) | |
3878 | || (i.reg_operands == 1 | |
3879 | && i.operands == 1 | |
3880 | && i.tm.base_opcode == 0x30 | |
3881 | && i.tm.extension_opcode == None))))) | |
b6f8c7c4 L |
3882 | { |
3883 | /* Optimize: -O: | |
3884 | andq $imm31, %r64 -> andl $imm31, %r32 | |
3885 | testq $imm31, %r64 -> testl $imm31, %r32 | |
3886 | xorq %r64, %r64 -> xorl %r32, %r32 | |
3887 | subq %r64, %r64 -> subl %r32, %r32 | |
3888 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3889 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3890 | */ | |
3891 | i.tm.opcode_modifier.norex64 = 1; | |
3892 | if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6) | |
3893 | { | |
3894 | /* Handle | |
3895 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3896 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3897 | */ | |
3898 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
3899 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
3900 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
3901 | i.types[0].bitfield.imm32 = 1; | |
3902 | i.types[0].bitfield.imm32s = 0; | |
3903 | i.types[0].bitfield.imm64 = 0; | |
3904 | i.types[1].bitfield.dword = 1; | |
3905 | i.types[1].bitfield.qword = 0; | |
3906 | if (i.tm.base_opcode == 0xc6) | |
3907 | { | |
3908 | /* Handle | |
3909 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3910 | */ | |
3911 | i.tm.base_opcode = 0xb0; | |
3912 | i.tm.extension_opcode = None; | |
3913 | i.tm.opcode_modifier.shortform = 1; | |
3914 | i.tm.opcode_modifier.modrm = 0; | |
3915 | } | |
3916 | } | |
3917 | } | |
3918 | else if (optimize > 1 | |
3919 | && i.reg_operands == 3 | |
3920 | && i.op[0].regs == i.op[1].regs | |
3921 | && !i.types[2].bitfield.xmmword | |
3922 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 3923 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 3924 | && !i.rounding |
e771e7c9 | 3925 | && is_evex_encoding (&i.tm) |
80c34c38 L |
3926 | && (i.vec_encoding != vex_encoding_evex |
3927 | || i.tm.cpu_flags.bitfield.cpuavx512vl | |
7091c612 JB |
3928 | || (i.tm.operand_types[2].bitfield.zmmword |
3929 | && i.types[2].bitfield.ymmword) | |
0089dace | 3930 | || cpu_arch_isa_flags.bitfield.cpuavx512vl))) |
b6f8c7c4 L |
3931 | && ((i.tm.base_opcode == 0x55 |
3932 | || i.tm.base_opcode == 0x6655 | |
3933 | || i.tm.base_opcode == 0x66df | |
3934 | || i.tm.base_opcode == 0x57 | |
3935 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
3936 | || i.tm.base_opcode == 0x66ef |
3937 | || i.tm.base_opcode == 0x66f8 | |
3938 | || i.tm.base_opcode == 0x66f9 | |
3939 | || i.tm.base_opcode == 0x66fa | |
3940 | || i.tm.base_opcode == 0x66fb) | |
b6f8c7c4 L |
3941 | && i.tm.extension_opcode == None)) |
3942 | { | |
3943 | /* Optimize: -O2: | |
8305403a L |
3944 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
3945 | vpsubq and vpsubw: | |
b6f8c7c4 L |
3946 | EVEX VOP %zmmM, %zmmM, %zmmN |
3947 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
3948 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3949 | EVEX VOP %ymmM, %ymmM, %ymmN | |
3950 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
3951 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3952 | VEX VOP %ymmM, %ymmM, %ymmN | |
3953 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
3954 | VOP, one of vpandn and vpxor: | |
3955 | VEX VOP %ymmM, %ymmM, %ymmN | |
3956 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
3957 | VOP, one of vpandnd and vpandnq: | |
3958 | EVEX VOP %zmmM, %zmmM, %zmmN | |
3959 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
3960 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3961 | EVEX VOP %ymmM, %ymmM, %ymmN | |
3962 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
3963 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3964 | VOP, one of vpxord and vpxorq: | |
3965 | EVEX VOP %zmmM, %zmmM, %zmmN | |
3966 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
3967 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3968 | EVEX VOP %ymmM, %ymmM, %ymmN | |
3969 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
3970 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) | |
3971 | */ | |
e771e7c9 | 3972 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 3973 | { |
0089dace | 3974 | if (i.vec_encoding == vex_encoding_evex) |
b6f8c7c4 L |
3975 | i.tm.opcode_modifier.evex = EVEX128; |
3976 | else | |
3977 | { | |
3978 | i.tm.opcode_modifier.vex = VEX128; | |
3979 | i.tm.opcode_modifier.vexw = VEXW0; | |
3980 | i.tm.opcode_modifier.evex = 0; | |
3981 | } | |
3982 | } | |
3983 | else | |
3984 | i.tm.opcode_modifier.vex = VEX128; | |
3985 | ||
3986 | if (i.tm.opcode_modifier.vex) | |
3987 | for (j = 0; j < 3; j++) | |
3988 | { | |
3989 | i.types[j].bitfield.xmmword = 1; | |
3990 | i.types[j].bitfield.ymmword = 0; | |
3991 | } | |
3992 | } | |
3993 | } | |
3994 | ||
252b5132 RH |
3995 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3996 | machine dependent instruction. This function is supposed to emit | |
3997 | the frags/bytes it assembles to. */ | |
3998 | ||
3999 | void | |
65da13b5 | 4000 | md_assemble (char *line) |
252b5132 | 4001 | { |
40fb9820 | 4002 | unsigned int j; |
83b16ac6 | 4003 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4004 | const insn_template *t; |
252b5132 | 4005 | |
47926f60 | 4006 | /* Initialize globals. */ |
252b5132 RH |
4007 | memset (&i, '\0', sizeof (i)); |
4008 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4009 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4010 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4011 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4012 | save_stack_p = save_stack; |
252b5132 RH |
4013 | |
4014 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4015 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4016 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4017 | |
29b0f896 AM |
4018 | line = parse_insn (line, mnemonic); |
4019 | if (line == NULL) | |
4020 | return; | |
83b16ac6 | 4021 | mnem_suffix = i.suffix; |
252b5132 | 4022 | |
29b0f896 | 4023 | line = parse_operands (line, mnemonic); |
ee86248c | 4024 | this_operand = -1; |
8325cc63 JB |
4025 | xfree (i.memop1_string); |
4026 | i.memop1_string = NULL; | |
29b0f896 AM |
4027 | if (line == NULL) |
4028 | return; | |
252b5132 | 4029 | |
29b0f896 AM |
4030 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4031 | operands at hand. */ | |
4032 | ||
4033 | /* All intel opcodes have reversed operands except for "bound" and | |
4034 | "enter". We also don't reverse intersegment "jmp" and "call" | |
4035 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 4036 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
4037 | if (intel_syntax |
4038 | && i.operands > 1 | |
29b0f896 | 4039 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4040 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
4041 | && !(operand_type_check (i.types[0], imm) |
4042 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4043 | swap_operands (); |
4044 | ||
ec56d5c0 JB |
4045 | /* The order of the immediates should be reversed |
4046 | for 2 immediates extrq and insertq instructions */ | |
4047 | if (i.imm_operands == 2 | |
4048 | && (strcmp (mnemonic, "extrq") == 0 | |
4049 | || strcmp (mnemonic, "insertq") == 0)) | |
4050 | swap_2_operands (0, 1); | |
4051 | ||
29b0f896 AM |
4052 | if (i.imm_operands) |
4053 | optimize_imm (); | |
4054 | ||
b300c311 L |
4055 | /* Don't optimize displacement for movabs since it only takes 64bit |
4056 | displacement. */ | |
4057 | if (i.disp_operands | |
a501d77e | 4058 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4059 | && (flag_code != CODE_64BIT |
4060 | || strcmp (mnemonic, "movabs") != 0)) | |
4061 | optimize_disp (); | |
29b0f896 AM |
4062 | |
4063 | /* Next, we find a template that matches the given insn, | |
4064 | making sure the overlap of the given operands types is consistent | |
4065 | with the template operand types. */ | |
252b5132 | 4066 | |
83b16ac6 | 4067 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4068 | return; |
252b5132 | 4069 | |
7bab8ab5 | 4070 | if (sse_check != check_none |
81f8a913 | 4071 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4072 | && !i.tm.cpu_flags.bitfield.cpuavx |
daf50ae7 L |
4073 | && (i.tm.cpu_flags.bitfield.cpusse |
4074 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4075 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4076 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4077 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4078 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4079 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4080 | || i.tm.cpu_flags.bitfield.cpuaes | |
4081 | || i.tm.cpu_flags.bitfield.cpugfni)) | |
daf50ae7 | 4082 | { |
7bab8ab5 | 4083 | (sse_check == check_warning |
daf50ae7 L |
4084 | ? as_warn |
4085 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4086 | } | |
4087 | ||
321fd21e L |
4088 | /* Zap movzx and movsx suffix. The suffix has been set from |
4089 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4090 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4091 | the destination register to choose the suffix for encoding. */ | |
4092 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4093 | { |
321fd21e L |
4094 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4095 | there is no suffix, the default will be byte extension. */ | |
4096 | if (i.reg_operands != 2 | |
4097 | && !i.suffix | |
7ab9ffdd | 4098 | && intel_syntax) |
321fd21e L |
4099 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4100 | ||
4101 | i.suffix = 0; | |
cd61ebfe | 4102 | } |
24eab124 | 4103 | |
40fb9820 | 4104 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4105 | if (!add_prefix (FWAIT_OPCODE)) |
4106 | return; | |
252b5132 | 4107 | |
d5de92cf L |
4108 | /* Check if REP prefix is OK. */ |
4109 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4110 | { | |
4111 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4112 | i.tm.name, i.rep_prefix); | |
4113 | return; | |
4114 | } | |
4115 | ||
c1ba0266 L |
4116 | /* Check for lock without a lockable instruction. Destination operand |
4117 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4118 | if (i.prefix[LOCK_PREFIX] |
4119 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4120 | || i.mem_operands == 0 |
4121 | || (i.tm.base_opcode != 0x86 | |
4122 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
4123 | { |
4124 | as_bad (_("expecting lockable instruction after `lock'")); | |
4125 | return; | |
4126 | } | |
4127 | ||
42164a71 | 4128 | /* Check if HLE prefix is OK. */ |
165de32a | 4129 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4130 | return; |
4131 | ||
7e8b059b L |
4132 | /* Check BND prefix. */ |
4133 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4134 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4135 | ||
04ef582a | 4136 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4137 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4138 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4139 | |
327e8c42 JB |
4140 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4141 | { | |
4142 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4143 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4144 | else if (flag_code != CODE_16BIT | |
4145 | ? i.prefix[ADDR_PREFIX] | |
4146 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4147 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4148 | } | |
7e8b059b L |
4149 | |
4150 | /* Insert BND prefix. */ | |
76d3a78a JB |
4151 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4152 | { | |
4153 | if (!i.prefix[BND_PREFIX]) | |
4154 | add_prefix (BND_PREFIX_OPCODE); | |
4155 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4156 | { | |
4157 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4158 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4159 | } | |
4160 | } | |
7e8b059b | 4161 | |
29b0f896 | 4162 | /* Check string instruction segment overrides. */ |
40fb9820 | 4163 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
4164 | { |
4165 | if (!check_string ()) | |
5dd0794d | 4166 | return; |
fc0763e6 | 4167 | i.disp_operands = 0; |
29b0f896 | 4168 | } |
5dd0794d | 4169 | |
b6f8c7c4 L |
4170 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4171 | optimize_encoding (); | |
4172 | ||
29b0f896 AM |
4173 | if (!process_suffix ()) |
4174 | return; | |
e413e4e9 | 4175 | |
bc0844ae L |
4176 | /* Update operand types. */ |
4177 | for (j = 0; j < i.operands; j++) | |
4178 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4179 | ||
29b0f896 AM |
4180 | /* Make still unresolved immediate matches conform to size of immediate |
4181 | given in i.suffix. */ | |
4182 | if (!finalize_imm ()) | |
4183 | return; | |
252b5132 | 4184 | |
40fb9820 | 4185 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4186 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4187 | |
9afe6eb8 L |
4188 | /* We only need to check those implicit registers for instructions |
4189 | with 3 operands or less. */ | |
4190 | if (i.operands <= 3) | |
4191 | for (j = 0; j < i.operands; j++) | |
4192 | if (i.types[j].bitfield.inoutportreg | |
4193 | || i.types[j].bitfield.shiftcount | |
1b54b8d7 | 4194 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
9afe6eb8 | 4195 | i.reg_operands--; |
40fb9820 | 4196 | |
c0f3af97 L |
4197 | /* ImmExt should be processed after SSE2AVX. */ |
4198 | if (!i.tm.opcode_modifier.sse2avx | |
4199 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4200 | process_immext (); |
252b5132 | 4201 | |
29b0f896 AM |
4202 | /* For insns with operands there are more diddles to do to the opcode. */ |
4203 | if (i.operands) | |
4204 | { | |
4205 | if (!process_operands ()) | |
4206 | return; | |
4207 | } | |
40fb9820 | 4208 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4209 | { |
4210 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4211 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4212 | } | |
252b5132 | 4213 | |
e771e7c9 JB |
4214 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode |
4215 | || is_evex_encoding (&i.tm)) | |
9e5e5283 L |
4216 | { |
4217 | if (flag_code == CODE_16BIT) | |
4218 | { | |
4219 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
4220 | i.tm.name); | |
4221 | return; | |
4222 | } | |
c0f3af97 | 4223 | |
9e5e5283 L |
4224 | if (i.tm.opcode_modifier.vex) |
4225 | build_vex_prefix (t); | |
4226 | else | |
4227 | build_evex_prefix (); | |
4228 | } | |
43234a1e | 4229 | |
5dd85c99 SP |
4230 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4231 | instructions may define INT_OPCODE as well, so avoid this corner | |
4232 | case for those instructions that use MODRM. */ | |
4233 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4234 | && !i.tm.opcode_modifier.modrm |
4235 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4236 | { |
4237 | i.tm.base_opcode = INT3_OPCODE; | |
4238 | i.imm_operands = 0; | |
4239 | } | |
252b5132 | 4240 | |
40fb9820 L |
4241 | if ((i.tm.opcode_modifier.jump |
4242 | || i.tm.opcode_modifier.jumpbyte | |
4243 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
4244 | && i.op[0].disps->X_op == O_constant) |
4245 | { | |
4246 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4247 | the absolute address given by the constant. Since ix86 jumps and | |
4248 | calls are pc relative, we need to generate a reloc. */ | |
4249 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4250 | i.op[0].disps->X_op = O_symbol; | |
4251 | } | |
252b5132 | 4252 | |
40fb9820 | 4253 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4254 | i.rex |= REX_W; |
252b5132 | 4255 | |
29b0f896 AM |
4256 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4257 | instruction already has a prefix, we need to convert old | |
4258 | registers to new ones. */ | |
773f551c | 4259 | |
dc821c5f | 4260 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte |
29b0f896 | 4261 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
dc821c5f | 4262 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte |
29b0f896 | 4263 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
dc821c5f JB |
4264 | || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
4265 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4266 | && i.rex != 0)) |
4267 | { | |
4268 | int x; | |
726c5dcd | 4269 | |
29b0f896 AM |
4270 | i.rex |= REX_OPCODE; |
4271 | for (x = 0; x < 2; x++) | |
4272 | { | |
4273 | /* Look for 8 bit operand that uses old registers. */ | |
dc821c5f | 4274 | if (i.types[x].bitfield.reg && i.types[x].bitfield.byte |
29b0f896 | 4275 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4276 | { |
29b0f896 AM |
4277 | /* In case it is "hi" register, give up. */ |
4278 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4279 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4280 | "instruction requiring REX prefix."), |
a540244d | 4281 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4282 | |
29b0f896 AM |
4283 | /* Otherwise it is equivalent to the extended register. |
4284 | Since the encoding doesn't change this is merely | |
4285 | cosmetic cleanup for debug output. */ | |
4286 | ||
4287 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4288 | } |
29b0f896 AM |
4289 | } |
4290 | } | |
773f551c | 4291 | |
6b6b6807 L |
4292 | if (i.rex == 0 && i.rex_encoding) |
4293 | { | |
4294 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4295 | that uses legacy register. If it is "hi" register, don't add | |
4296 | the REX_OPCODE byte. */ | |
4297 | int x; | |
4298 | for (x = 0; x < 2; x++) | |
4299 | if (i.types[x].bitfield.reg | |
4300 | && i.types[x].bitfield.byte | |
4301 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4302 | && i.op[x].regs->reg_num > 3) | |
4303 | { | |
4304 | i.rex_encoding = FALSE; | |
4305 | break; | |
4306 | } | |
4307 | ||
4308 | if (i.rex_encoding) | |
4309 | i.rex = REX_OPCODE; | |
4310 | } | |
4311 | ||
7ab9ffdd | 4312 | if (i.rex != 0) |
29b0f896 AM |
4313 | add_prefix (REX_OPCODE | i.rex); |
4314 | ||
4315 | /* We are ready to output the insn. */ | |
4316 | output_insn (); | |
4317 | } | |
4318 | ||
4319 | static char * | |
e3bb37b5 | 4320 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4321 | { |
4322 | char *l = line; | |
4323 | char *token_start = l; | |
4324 | char *mnem_p; | |
5c6af06e | 4325 | int supported; |
d3ce72d0 | 4326 | const insn_template *t; |
b6169b20 | 4327 | char *dot_p = NULL; |
29b0f896 | 4328 | |
29b0f896 AM |
4329 | while (1) |
4330 | { | |
4331 | mnem_p = mnemonic; | |
4332 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4333 | { | |
b6169b20 L |
4334 | if (*mnem_p == '.') |
4335 | dot_p = mnem_p; | |
29b0f896 AM |
4336 | mnem_p++; |
4337 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4338 | { |
29b0f896 AM |
4339 | as_bad (_("no such instruction: `%s'"), token_start); |
4340 | return NULL; | |
4341 | } | |
4342 | l++; | |
4343 | } | |
4344 | if (!is_space_char (*l) | |
4345 | && *l != END_OF_INSN | |
e44823cf JB |
4346 | && (intel_syntax |
4347 | || (*l != PREFIX_SEPARATOR | |
4348 | && *l != ','))) | |
29b0f896 AM |
4349 | { |
4350 | as_bad (_("invalid character %s in mnemonic"), | |
4351 | output_invalid (*l)); | |
4352 | return NULL; | |
4353 | } | |
4354 | if (token_start == l) | |
4355 | { | |
e44823cf | 4356 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4357 | as_bad (_("expecting prefix; got nothing")); |
4358 | else | |
4359 | as_bad (_("expecting mnemonic; got nothing")); | |
4360 | return NULL; | |
4361 | } | |
45288df1 | 4362 | |
29b0f896 | 4363 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4364 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4365 | |
29b0f896 AM |
4366 | if (*l != END_OF_INSN |
4367 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4368 | && current_templates | |
40fb9820 | 4369 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4370 | { |
c6fb90c8 | 4371 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4372 | { |
4373 | as_bad ((flag_code != CODE_64BIT | |
4374 | ? _("`%s' is only supported in 64-bit mode") | |
4375 | : _("`%s' is not supported in 64-bit mode")), | |
4376 | current_templates->start->name); | |
4377 | return NULL; | |
4378 | } | |
29b0f896 AM |
4379 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4380 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
4381 | if ((current_templates->start->opcode_modifier.size16 |
4382 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 4383 | && flag_code != CODE_64BIT |
40fb9820 | 4384 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
4385 | ^ (flag_code == CODE_16BIT))) |
4386 | { | |
4387 | as_bad (_("redundant %s prefix"), | |
4388 | current_templates->start->name); | |
4389 | return NULL; | |
45288df1 | 4390 | } |
86fa6981 | 4391 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4392 | { |
86fa6981 L |
4393 | /* Handle pseudo prefixes. */ |
4394 | switch (current_templates->start->base_opcode) | |
4395 | { | |
4396 | case 0x0: | |
4397 | /* {disp8} */ | |
4398 | i.disp_encoding = disp_encoding_8bit; | |
4399 | break; | |
4400 | case 0x1: | |
4401 | /* {disp32} */ | |
4402 | i.disp_encoding = disp_encoding_32bit; | |
4403 | break; | |
4404 | case 0x2: | |
4405 | /* {load} */ | |
4406 | i.dir_encoding = dir_encoding_load; | |
4407 | break; | |
4408 | case 0x3: | |
4409 | /* {store} */ | |
4410 | i.dir_encoding = dir_encoding_store; | |
4411 | break; | |
4412 | case 0x4: | |
4413 | /* {vex2} */ | |
4414 | i.vec_encoding = vex_encoding_vex2; | |
4415 | break; | |
4416 | case 0x5: | |
4417 | /* {vex3} */ | |
4418 | i.vec_encoding = vex_encoding_vex3; | |
4419 | break; | |
4420 | case 0x6: | |
4421 | /* {evex} */ | |
4422 | i.vec_encoding = vex_encoding_evex; | |
4423 | break; | |
6b6b6807 L |
4424 | case 0x7: |
4425 | /* {rex} */ | |
4426 | i.rex_encoding = TRUE; | |
4427 | break; | |
b6f8c7c4 L |
4428 | case 0x8: |
4429 | /* {nooptimize} */ | |
4430 | i.no_optimize = TRUE; | |
4431 | break; | |
86fa6981 L |
4432 | default: |
4433 | abort (); | |
4434 | } | |
4435 | } | |
4436 | else | |
4437 | { | |
4438 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4439 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4440 | { |
4e9ac44a L |
4441 | case PREFIX_EXIST: |
4442 | return NULL; | |
4443 | case PREFIX_DS: | |
d777820b | 4444 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4445 | i.notrack_prefix = current_templates->start->name; |
4446 | break; | |
4447 | case PREFIX_REP: | |
4448 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4449 | i.hle_prefix = current_templates->start->name; | |
4450 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4451 | i.bnd_prefix = current_templates->start->name; | |
4452 | else | |
4453 | i.rep_prefix = current_templates->start->name; | |
4454 | break; | |
4455 | default: | |
4456 | break; | |
86fa6981 | 4457 | } |
29b0f896 AM |
4458 | } |
4459 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4460 | token_start = ++l; | |
4461 | } | |
4462 | else | |
4463 | break; | |
4464 | } | |
45288df1 | 4465 | |
30a55f88 | 4466 | if (!current_templates) |
b6169b20 | 4467 | { |
f8a5c266 L |
4468 | /* Check if we should swap operand or force 32bit displacement in |
4469 | encoding. */ | |
30a55f88 | 4470 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
86fa6981 | 4471 | i.dir_encoding = dir_encoding_store; |
8d63c93e | 4472 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4473 | && dot_p[1] == 'd' |
4474 | && dot_p[2] == '8') | |
4475 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4476 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4477 | && dot_p[1] == 'd' |
4478 | && dot_p[2] == '3' | |
4479 | && dot_p[3] == '2') | |
a501d77e | 4480 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4481 | else |
4482 | goto check_suffix; | |
4483 | mnem_p = dot_p; | |
4484 | *dot_p = '\0'; | |
d3ce72d0 | 4485 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4486 | } |
4487 | ||
29b0f896 AM |
4488 | if (!current_templates) |
4489 | { | |
b6169b20 | 4490 | check_suffix: |
29b0f896 AM |
4491 | /* See if we can get a match by trimming off a suffix. */ |
4492 | switch (mnem_p[-1]) | |
4493 | { | |
4494 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
4495 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
4496 | i.suffix = SHORT_MNEM_SUFFIX; | |
4497 | else | |
1a0670f3 | 4498 | /* Fall through. */ |
29b0f896 AM |
4499 | case BYTE_MNEM_SUFFIX: |
4500 | case QWORD_MNEM_SUFFIX: | |
4501 | i.suffix = mnem_p[-1]; | |
4502 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4503 | current_templates = (const templates *) hash_find (op_hash, |
4504 | mnemonic); | |
29b0f896 AM |
4505 | break; |
4506 | case SHORT_MNEM_SUFFIX: | |
4507 | case LONG_MNEM_SUFFIX: | |
4508 | if (!intel_syntax) | |
4509 | { | |
4510 | i.suffix = mnem_p[-1]; | |
4511 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4512 | current_templates = (const templates *) hash_find (op_hash, |
4513 | mnemonic); | |
29b0f896 AM |
4514 | } |
4515 | break; | |
252b5132 | 4516 | |
29b0f896 AM |
4517 | /* Intel Syntax. */ |
4518 | case 'd': | |
4519 | if (intel_syntax) | |
4520 | { | |
9306ca4a | 4521 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
4522 | i.suffix = SHORT_MNEM_SUFFIX; |
4523 | else | |
4524 | i.suffix = LONG_MNEM_SUFFIX; | |
4525 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4526 | current_templates = (const templates *) hash_find (op_hash, |
4527 | mnemonic); | |
29b0f896 AM |
4528 | } |
4529 | break; | |
4530 | } | |
4531 | if (!current_templates) | |
4532 | { | |
4533 | as_bad (_("no such instruction: `%s'"), token_start); | |
4534 | return NULL; | |
4535 | } | |
4536 | } | |
252b5132 | 4537 | |
40fb9820 L |
4538 | if (current_templates->start->opcode_modifier.jump |
4539 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4540 | { |
4541 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4542 | predict taken and predict not taken respectively. | |
4543 | I'm not sure that branch hints actually do anything on loop | |
4544 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4545 | may work in the future and it doesn't hurt to accept them | |
4546 | now. */ | |
4547 | if (l[0] == ',' && l[1] == 'p') | |
4548 | { | |
4549 | if (l[2] == 't') | |
4550 | { | |
4551 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4552 | return NULL; | |
4553 | l += 3; | |
4554 | } | |
4555 | else if (l[2] == 'n') | |
4556 | { | |
4557 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4558 | return NULL; | |
4559 | l += 3; | |
4560 | } | |
4561 | } | |
4562 | } | |
4563 | /* Any other comma loses. */ | |
4564 | if (*l == ',') | |
4565 | { | |
4566 | as_bad (_("invalid character %s in mnemonic"), | |
4567 | output_invalid (*l)); | |
4568 | return NULL; | |
4569 | } | |
252b5132 | 4570 | |
29b0f896 | 4571 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4572 | supported = 0; |
4573 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4574 | { | |
c0f3af97 L |
4575 | supported |= cpu_flags_match (t); |
4576 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4577 | { |
4578 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4579 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4580 | |
548d0ee6 JB |
4581 | return l; |
4582 | } | |
29b0f896 | 4583 | } |
3629bb00 | 4584 | |
548d0ee6 JB |
4585 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4586 | as_bad (flag_code == CODE_64BIT | |
4587 | ? _("`%s' is not supported in 64-bit mode") | |
4588 | : _("`%s' is only supported in 64-bit mode"), | |
4589 | current_templates->start->name); | |
4590 | else | |
4591 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4592 | current_templates->start->name, | |
4593 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4594 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4595 | |
548d0ee6 | 4596 | return NULL; |
29b0f896 | 4597 | } |
252b5132 | 4598 | |
29b0f896 | 4599 | static char * |
e3bb37b5 | 4600 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4601 | { |
4602 | char *token_start; | |
3138f287 | 4603 | |
29b0f896 AM |
4604 | /* 1 if operand is pending after ','. */ |
4605 | unsigned int expecting_operand = 0; | |
252b5132 | 4606 | |
29b0f896 AM |
4607 | /* Non-zero if operand parens not balanced. */ |
4608 | unsigned int paren_not_balanced; | |
4609 | ||
4610 | while (*l != END_OF_INSN) | |
4611 | { | |
4612 | /* Skip optional white space before operand. */ | |
4613 | if (is_space_char (*l)) | |
4614 | ++l; | |
d02603dc | 4615 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4616 | { |
4617 | as_bad (_("invalid character %s before operand %d"), | |
4618 | output_invalid (*l), | |
4619 | i.operands + 1); | |
4620 | return NULL; | |
4621 | } | |
d02603dc | 4622 | token_start = l; /* After white space. */ |
29b0f896 AM |
4623 | paren_not_balanced = 0; |
4624 | while (paren_not_balanced || *l != ',') | |
4625 | { | |
4626 | if (*l == END_OF_INSN) | |
4627 | { | |
4628 | if (paren_not_balanced) | |
4629 | { | |
4630 | if (!intel_syntax) | |
4631 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4632 | i.operands + 1); | |
4633 | else | |
4634 | as_bad (_("unbalanced brackets in operand %d."), | |
4635 | i.operands + 1); | |
4636 | return NULL; | |
4637 | } | |
4638 | else | |
4639 | break; /* we are done */ | |
4640 | } | |
d02603dc | 4641 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4642 | { |
4643 | as_bad (_("invalid character %s in operand %d"), | |
4644 | output_invalid (*l), | |
4645 | i.operands + 1); | |
4646 | return NULL; | |
4647 | } | |
4648 | if (!intel_syntax) | |
4649 | { | |
4650 | if (*l == '(') | |
4651 | ++paren_not_balanced; | |
4652 | if (*l == ')') | |
4653 | --paren_not_balanced; | |
4654 | } | |
4655 | else | |
4656 | { | |
4657 | if (*l == '[') | |
4658 | ++paren_not_balanced; | |
4659 | if (*l == ']') | |
4660 | --paren_not_balanced; | |
4661 | } | |
4662 | l++; | |
4663 | } | |
4664 | if (l != token_start) | |
4665 | { /* Yes, we've read in another operand. */ | |
4666 | unsigned int operand_ok; | |
4667 | this_operand = i.operands++; | |
4668 | if (i.operands > MAX_OPERANDS) | |
4669 | { | |
4670 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4671 | MAX_OPERANDS); | |
4672 | return NULL; | |
4673 | } | |
9d46ce34 | 4674 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4675 | /* Now parse operand adding info to 'i' as we go along. */ |
4676 | END_STRING_AND_SAVE (l); | |
4677 | ||
1286ab78 L |
4678 | if (i.mem_operands > 1) |
4679 | { | |
4680 | as_bad (_("too many memory references for `%s'"), | |
4681 | mnemonic); | |
4682 | return 0; | |
4683 | } | |
4684 | ||
29b0f896 AM |
4685 | if (intel_syntax) |
4686 | operand_ok = | |
4687 | i386_intel_operand (token_start, | |
4688 | intel_float_operand (mnemonic)); | |
4689 | else | |
a7619375 | 4690 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4691 | |
4692 | RESTORE_END_STRING (l); | |
4693 | if (!operand_ok) | |
4694 | return NULL; | |
4695 | } | |
4696 | else | |
4697 | { | |
4698 | if (expecting_operand) | |
4699 | { | |
4700 | expecting_operand_after_comma: | |
4701 | as_bad (_("expecting operand after ','; got nothing")); | |
4702 | return NULL; | |
4703 | } | |
4704 | if (*l == ',') | |
4705 | { | |
4706 | as_bad (_("expecting operand before ','; got nothing")); | |
4707 | return NULL; | |
4708 | } | |
4709 | } | |
7f3f1ea2 | 4710 | |
29b0f896 AM |
4711 | /* Now *l must be either ',' or END_OF_INSN. */ |
4712 | if (*l == ',') | |
4713 | { | |
4714 | if (*++l == END_OF_INSN) | |
4715 | { | |
4716 | /* Just skip it, if it's \n complain. */ | |
4717 | goto expecting_operand_after_comma; | |
4718 | } | |
4719 | expecting_operand = 1; | |
4720 | } | |
4721 | } | |
4722 | return l; | |
4723 | } | |
7f3f1ea2 | 4724 | |
050dfa73 | 4725 | static void |
4d456e3d | 4726 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4727 | { |
4728 | union i386_op temp_op; | |
40fb9820 | 4729 | i386_operand_type temp_type; |
050dfa73 | 4730 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4731 | |
050dfa73 MM |
4732 | temp_type = i.types[xchg2]; |
4733 | i.types[xchg2] = i.types[xchg1]; | |
4734 | i.types[xchg1] = temp_type; | |
4735 | temp_op = i.op[xchg2]; | |
4736 | i.op[xchg2] = i.op[xchg1]; | |
4737 | i.op[xchg1] = temp_op; | |
4738 | temp_reloc = i.reloc[xchg2]; | |
4739 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4740 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4741 | |
4742 | if (i.mask) | |
4743 | { | |
4744 | if (i.mask->operand == xchg1) | |
4745 | i.mask->operand = xchg2; | |
4746 | else if (i.mask->operand == xchg2) | |
4747 | i.mask->operand = xchg1; | |
4748 | } | |
4749 | if (i.broadcast) | |
4750 | { | |
4751 | if (i.broadcast->operand == xchg1) | |
4752 | i.broadcast->operand = xchg2; | |
4753 | else if (i.broadcast->operand == xchg2) | |
4754 | i.broadcast->operand = xchg1; | |
4755 | } | |
4756 | if (i.rounding) | |
4757 | { | |
4758 | if (i.rounding->operand == xchg1) | |
4759 | i.rounding->operand = xchg2; | |
4760 | else if (i.rounding->operand == xchg2) | |
4761 | i.rounding->operand = xchg1; | |
4762 | } | |
050dfa73 MM |
4763 | } |
4764 | ||
29b0f896 | 4765 | static void |
e3bb37b5 | 4766 | swap_operands (void) |
29b0f896 | 4767 | { |
b7c61d9a | 4768 | switch (i.operands) |
050dfa73 | 4769 | { |
c0f3af97 | 4770 | case 5: |
b7c61d9a | 4771 | case 4: |
4d456e3d | 4772 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4773 | /* Fall through. */ |
b7c61d9a L |
4774 | case 3: |
4775 | case 2: | |
4d456e3d | 4776 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4777 | break; |
4778 | default: | |
4779 | abort (); | |
29b0f896 | 4780 | } |
29b0f896 AM |
4781 | |
4782 | if (i.mem_operands == 2) | |
4783 | { | |
4784 | const seg_entry *temp_seg; | |
4785 | temp_seg = i.seg[0]; | |
4786 | i.seg[0] = i.seg[1]; | |
4787 | i.seg[1] = temp_seg; | |
4788 | } | |
4789 | } | |
252b5132 | 4790 | |
29b0f896 AM |
4791 | /* Try to ensure constant immediates are represented in the smallest |
4792 | opcode possible. */ | |
4793 | static void | |
e3bb37b5 | 4794 | optimize_imm (void) |
29b0f896 AM |
4795 | { |
4796 | char guess_suffix = 0; | |
4797 | int op; | |
252b5132 | 4798 | |
29b0f896 AM |
4799 | if (i.suffix) |
4800 | guess_suffix = i.suffix; | |
4801 | else if (i.reg_operands) | |
4802 | { | |
4803 | /* Figure out a suffix from the last register operand specified. | |
4804 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4805 | but the following works for instructions with immediates. | |
4806 | In any case, we can't set i.suffix yet. */ | |
4807 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 4808 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
7ab9ffdd | 4809 | { |
40fb9820 L |
4810 | guess_suffix = BYTE_MNEM_SUFFIX; |
4811 | break; | |
4812 | } | |
dc821c5f | 4813 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
252b5132 | 4814 | { |
40fb9820 L |
4815 | guess_suffix = WORD_MNEM_SUFFIX; |
4816 | break; | |
4817 | } | |
dc821c5f | 4818 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
4819 | { |
4820 | guess_suffix = LONG_MNEM_SUFFIX; | |
4821 | break; | |
4822 | } | |
dc821c5f | 4823 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
4824 | { |
4825 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4826 | break; |
252b5132 | 4827 | } |
29b0f896 AM |
4828 | } |
4829 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4830 | guess_suffix = WORD_MNEM_SUFFIX; | |
4831 | ||
4832 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4833 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4834 | { |
4835 | switch (i.op[op].imms->X_op) | |
252b5132 | 4836 | { |
29b0f896 AM |
4837 | case O_constant: |
4838 | /* If a suffix is given, this operand may be shortened. */ | |
4839 | switch (guess_suffix) | |
252b5132 | 4840 | { |
29b0f896 | 4841 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
4842 | i.types[op].bitfield.imm32 = 1; |
4843 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4844 | break; |
4845 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
4846 | i.types[op].bitfield.imm16 = 1; |
4847 | i.types[op].bitfield.imm32 = 1; | |
4848 | i.types[op].bitfield.imm32s = 1; | |
4849 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4850 | break; |
4851 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
4852 | i.types[op].bitfield.imm8 = 1; |
4853 | i.types[op].bitfield.imm8s = 1; | |
4854 | i.types[op].bitfield.imm16 = 1; | |
4855 | i.types[op].bitfield.imm32 = 1; | |
4856 | i.types[op].bitfield.imm32s = 1; | |
4857 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 4858 | break; |
252b5132 | 4859 | } |
252b5132 | 4860 | |
29b0f896 AM |
4861 | /* If this operand is at most 16 bits, convert it |
4862 | to a signed 16 bit number before trying to see | |
4863 | whether it will fit in an even smaller size. | |
4864 | This allows a 16-bit operand such as $0xffe0 to | |
4865 | be recognised as within Imm8S range. */ | |
40fb9820 | 4866 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 4867 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 4868 | { |
29b0f896 AM |
4869 | i.op[op].imms->X_add_number = |
4870 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
4871 | } | |
a28def75 L |
4872 | #ifdef BFD64 |
4873 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 4874 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
4875 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
4876 | == 0)) | |
4877 | { | |
4878 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
4879 | ^ ((offsetT) 1 << 31)) | |
4880 | - ((offsetT) 1 << 31)); | |
4881 | } | |
a28def75 | 4882 | #endif |
40fb9820 | 4883 | i.types[op] |
c6fb90c8 L |
4884 | = operand_type_or (i.types[op], |
4885 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 4886 | |
29b0f896 AM |
4887 | /* We must avoid matching of Imm32 templates when 64bit |
4888 | only immediate is available. */ | |
4889 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 4890 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 4891 | break; |
252b5132 | 4892 | |
29b0f896 AM |
4893 | case O_absent: |
4894 | case O_register: | |
4895 | abort (); | |
4896 | ||
4897 | /* Symbols and expressions. */ | |
4898 | default: | |
9cd96992 JB |
4899 | /* Convert symbolic operand to proper sizes for matching, but don't |
4900 | prevent matching a set of insns that only supports sizes other | |
4901 | than those matching the insn suffix. */ | |
4902 | { | |
40fb9820 | 4903 | i386_operand_type mask, allowed; |
d3ce72d0 | 4904 | const insn_template *t; |
9cd96992 | 4905 | |
0dfbf9d7 L |
4906 | operand_type_set (&mask, 0); |
4907 | operand_type_set (&allowed, 0); | |
40fb9820 | 4908 | |
4eed87de AM |
4909 | for (t = current_templates->start; |
4910 | t < current_templates->end; | |
4911 | ++t) | |
c6fb90c8 L |
4912 | allowed = operand_type_or (allowed, |
4913 | t->operand_types[op]); | |
9cd96992 JB |
4914 | switch (guess_suffix) |
4915 | { | |
4916 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
4917 | mask.bitfield.imm64 = 1; |
4918 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
4919 | break; |
4920 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 4921 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
4922 | break; |
4923 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 4924 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
4925 | break; |
4926 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 4927 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
4928 | break; |
4929 | default: | |
9cd96992 JB |
4930 | break; |
4931 | } | |
c6fb90c8 | 4932 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 4933 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 4934 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 4935 | } |
29b0f896 | 4936 | break; |
252b5132 | 4937 | } |
29b0f896 AM |
4938 | } |
4939 | } | |
47926f60 | 4940 | |
29b0f896 AM |
4941 | /* Try to use the smallest displacement type too. */ |
4942 | static void | |
e3bb37b5 | 4943 | optimize_disp (void) |
29b0f896 AM |
4944 | { |
4945 | int op; | |
3e73aa7c | 4946 | |
29b0f896 | 4947 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4948 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 4949 | { |
b300c311 | 4950 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 4951 | { |
91d6fa6a | 4952 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 4953 | |
40fb9820 | 4954 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 4955 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
4956 | { |
4957 | /* If this operand is at most 16 bits, convert | |
4958 | to a signed 16 bit number and don't use 64bit | |
4959 | displacement. */ | |
91d6fa6a | 4960 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 4961 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4962 | } |
a28def75 L |
4963 | #ifdef BFD64 |
4964 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 4965 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 4966 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
4967 | { |
4968 | /* If this operand is at most 32 bits, convert | |
4969 | to a signed 32 bit number and don't use 64bit | |
4970 | displacement. */ | |
91d6fa6a NC |
4971 | op_disp &= (((offsetT) 2 << 31) - 1); |
4972 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 4973 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4974 | } |
a28def75 | 4975 | #endif |
91d6fa6a | 4976 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 4977 | { |
40fb9820 L |
4978 | i.types[op].bitfield.disp8 = 0; |
4979 | i.types[op].bitfield.disp16 = 0; | |
4980 | i.types[op].bitfield.disp32 = 0; | |
4981 | i.types[op].bitfield.disp32s = 0; | |
4982 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
4983 | i.op[op].disps = 0; |
4984 | i.disp_operands--; | |
4985 | } | |
4986 | else if (flag_code == CODE_64BIT) | |
4987 | { | |
91d6fa6a | 4988 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 4989 | { |
40fb9820 L |
4990 | i.types[op].bitfield.disp64 = 0; |
4991 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 4992 | } |
0e1147d9 | 4993 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 4994 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 4995 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 4996 | } |
40fb9820 L |
4997 | if ((i.types[op].bitfield.disp32 |
4998 | || i.types[op].bitfield.disp32s | |
4999 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5000 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5001 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5002 | } |
67a4f2b7 AO |
5003 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5004 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5005 | { | |
5006 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5007 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5008 | i.types[op].bitfield.disp8 = 0; |
5009 | i.types[op].bitfield.disp16 = 0; | |
5010 | i.types[op].bitfield.disp32 = 0; | |
5011 | i.types[op].bitfield.disp32s = 0; | |
5012 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5013 | } |
5014 | else | |
b300c311 | 5015 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5016 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5017 | } |
29b0f896 AM |
5018 | } |
5019 | ||
4a1b91ea L |
5020 | /* Return 1 if there is a match in broadcast bytes between operand |
5021 | GIVEN and instruction template T. */ | |
5022 | ||
5023 | static INLINE int | |
5024 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5025 | { | |
5026 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5027 | && i.types[given].bitfield.byte) | |
5028 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5029 | && i.types[given].bitfield.word) | |
5030 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5031 | && i.types[given].bitfield.dword) | |
5032 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5033 | && i.types[given].bitfield.qword)); | |
5034 | } | |
5035 | ||
6c30d220 L |
5036 | /* Check if operands are valid for the instruction. */ |
5037 | ||
5038 | static int | |
5039 | check_VecOperands (const insn_template *t) | |
5040 | { | |
43234a1e | 5041 | unsigned int op; |
e2195274 JB |
5042 | i386_cpu_flags cpu; |
5043 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; | |
5044 | ||
5045 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5046 | any one operand are implicity requiring AVX512VL support if the actual | |
5047 | operand size is YMMword or XMMword. Since this function runs after | |
5048 | template matching, there's no need to check for YMMword/XMMword in | |
5049 | the template. */ | |
5050 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5051 | if (!cpu_flags_all_zero (&cpu) | |
5052 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5053 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5054 | { | |
5055 | for (op = 0; op < t->operands; ++op) | |
5056 | { | |
5057 | if (t->operand_types[op].bitfield.zmmword | |
5058 | && (i.types[op].bitfield.ymmword | |
5059 | || i.types[op].bitfield.xmmword)) | |
5060 | { | |
5061 | i.error = unsupported; | |
5062 | return 1; | |
5063 | } | |
5064 | } | |
5065 | } | |
43234a1e | 5066 | |
6c30d220 L |
5067 | /* Without VSIB byte, we can't have a vector register for index. */ |
5068 | if (!t->opcode_modifier.vecsib | |
5069 | && i.index_reg | |
1b54b8d7 JB |
5070 | && (i.index_reg->reg_type.bitfield.xmmword |
5071 | || i.index_reg->reg_type.bitfield.ymmword | |
5072 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5073 | { |
5074 | i.error = unsupported_vector_index_register; | |
5075 | return 1; | |
5076 | } | |
5077 | ||
ad8ecc81 MZ |
5078 | /* Check if default mask is allowed. */ |
5079 | if (t->opcode_modifier.nodefmask | |
5080 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5081 | { | |
5082 | i.error = no_default_mask; | |
5083 | return 1; | |
5084 | } | |
5085 | ||
7bab8ab5 JB |
5086 | /* For VSIB byte, we need a vector register for index, and all vector |
5087 | registers must be distinct. */ | |
5088 | if (t->opcode_modifier.vecsib) | |
5089 | { | |
5090 | if (!i.index_reg | |
6c30d220 | 5091 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5092 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5093 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5094 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5095 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5096 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5097 | { |
5098 | i.error = invalid_vsib_address; | |
5099 | return 1; | |
5100 | } | |
5101 | ||
43234a1e L |
5102 | gas_assert (i.reg_operands == 2 || i.mask); |
5103 | if (i.reg_operands == 2 && !i.mask) | |
5104 | { | |
1b54b8d7 JB |
5105 | gas_assert (i.types[0].bitfield.regsimd); |
5106 | gas_assert (i.types[0].bitfield.xmmword | |
5107 | || i.types[0].bitfield.ymmword); | |
5108 | gas_assert (i.types[2].bitfield.regsimd); | |
5109 | gas_assert (i.types[2].bitfield.xmmword | |
5110 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5111 | if (operand_check == check_none) |
5112 | return 0; | |
5113 | if (register_number (i.op[0].regs) | |
5114 | != register_number (i.index_reg) | |
5115 | && register_number (i.op[2].regs) | |
5116 | != register_number (i.index_reg) | |
5117 | && register_number (i.op[0].regs) | |
5118 | != register_number (i.op[2].regs)) | |
5119 | return 0; | |
5120 | if (operand_check == check_error) | |
5121 | { | |
5122 | i.error = invalid_vector_register_set; | |
5123 | return 1; | |
5124 | } | |
5125 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5126 | } | |
8444f82a MZ |
5127 | else if (i.reg_operands == 1 && i.mask) |
5128 | { | |
1b54b8d7 JB |
5129 | if (i.types[1].bitfield.regsimd |
5130 | && (i.types[1].bitfield.xmmword | |
5131 | || i.types[1].bitfield.ymmword | |
5132 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5133 | && (register_number (i.op[1].regs) |
5134 | == register_number (i.index_reg))) | |
5135 | { | |
5136 | if (operand_check == check_error) | |
5137 | { | |
5138 | i.error = invalid_vector_register_set; | |
5139 | return 1; | |
5140 | } | |
5141 | if (operand_check != check_none) | |
5142 | as_warn (_("index and destination registers should be distinct")); | |
5143 | } | |
5144 | } | |
43234a1e | 5145 | } |
7bab8ab5 | 5146 | |
43234a1e L |
5147 | /* Check if broadcast is supported by the instruction and is applied |
5148 | to the memory operand. */ | |
5149 | if (i.broadcast) | |
5150 | { | |
8e6e0792 | 5151 | i386_operand_type type, overlap; |
43234a1e L |
5152 | |
5153 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5154 | and its broadcast bytes match the memory operand. */ |
32546502 | 5155 | op = i.broadcast->operand; |
8e6e0792 | 5156 | if (!t->opcode_modifier.broadcast |
32546502 | 5157 | || !i.types[op].bitfield.mem |
c39e5b26 | 5158 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5159 | && !match_broadcast_size (t, op))) |
43234a1e L |
5160 | { |
5161 | bad_broadcast: | |
5162 | i.error = unsupported_broadcast; | |
5163 | return 1; | |
5164 | } | |
8e6e0792 | 5165 | |
4a1b91ea L |
5166 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5167 | * i.broadcast->type); | |
8e6e0792 | 5168 | operand_type_set (&type, 0); |
4a1b91ea | 5169 | switch (i.broadcast->bytes) |
8e6e0792 | 5170 | { |
4a1b91ea L |
5171 | case 2: |
5172 | type.bitfield.word = 1; | |
5173 | break; | |
5174 | case 4: | |
5175 | type.bitfield.dword = 1; | |
5176 | break; | |
8e6e0792 JB |
5177 | case 8: |
5178 | type.bitfield.qword = 1; | |
5179 | break; | |
5180 | case 16: | |
5181 | type.bitfield.xmmword = 1; | |
5182 | break; | |
5183 | case 32: | |
5184 | type.bitfield.ymmword = 1; | |
5185 | break; | |
5186 | case 64: | |
5187 | type.bitfield.zmmword = 1; | |
5188 | break; | |
5189 | default: | |
5190 | goto bad_broadcast; | |
5191 | } | |
5192 | ||
5193 | overlap = operand_type_and (type, t->operand_types[op]); | |
5194 | if (operand_type_all_zero (&overlap)) | |
5195 | goto bad_broadcast; | |
5196 | ||
5197 | if (t->opcode_modifier.checkregsize) | |
5198 | { | |
5199 | unsigned int j; | |
5200 | ||
e2195274 | 5201 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5202 | for (j = 0; j < i.operands; ++j) |
5203 | { | |
5204 | if (j != op | |
5205 | && !operand_type_register_match(i.types[j], | |
5206 | t->operand_types[j], | |
5207 | type, | |
5208 | t->operand_types[op])) | |
5209 | goto bad_broadcast; | |
5210 | } | |
5211 | } | |
43234a1e L |
5212 | } |
5213 | /* If broadcast is supported in this instruction, we need to check if | |
5214 | operand of one-element size isn't specified without broadcast. */ | |
5215 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5216 | { | |
5217 | /* Find memory operand. */ | |
5218 | for (op = 0; op < i.operands; op++) | |
5219 | if (operand_type_check (i.types[op], anymem)) | |
5220 | break; | |
5221 | gas_assert (op < i.operands); | |
5222 | /* Check size of the memory operand. */ | |
4a1b91ea | 5223 | if (match_broadcast_size (t, op)) |
43234a1e L |
5224 | { |
5225 | i.error = broadcast_needed; | |
5226 | return 1; | |
5227 | } | |
5228 | } | |
c39e5b26 JB |
5229 | else |
5230 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5231 | |
5232 | /* Check if requested masking is supported. */ | |
5233 | if (i.mask | |
5234 | && (!t->opcode_modifier.masking | |
5235 | || (i.mask->zeroing | |
5236 | && t->opcode_modifier.masking == MERGING_MASKING))) | |
5237 | { | |
5238 | i.error = unsupported_masking; | |
5239 | return 1; | |
5240 | } | |
5241 | ||
5242 | /* Check if masking is applied to dest operand. */ | |
5243 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5244 | { | |
5245 | i.error = mask_not_on_destination; | |
5246 | return 1; | |
5247 | } | |
5248 | ||
43234a1e L |
5249 | /* Check RC/SAE. */ |
5250 | if (i.rounding) | |
5251 | { | |
5252 | if ((i.rounding->type != saeonly | |
5253 | && !t->opcode_modifier.staticrounding) | |
5254 | || (i.rounding->type == saeonly | |
5255 | && (t->opcode_modifier.staticrounding | |
5256 | || !t->opcode_modifier.sae))) | |
5257 | { | |
5258 | i.error = unsupported_rc_sae; | |
5259 | return 1; | |
5260 | } | |
5261 | /* If the instruction has several immediate operands and one of | |
5262 | them is rounding, the rounding operand should be the last | |
5263 | immediate operand. */ | |
5264 | if (i.imm_operands > 1 | |
5265 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5266 | { |
43234a1e | 5267 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5268 | return 1; |
5269 | } | |
6c30d220 L |
5270 | } |
5271 | ||
43234a1e | 5272 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5273 | if (t->opcode_modifier.disp8memshift |
5274 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5275 | { |
5276 | if (i.broadcast) | |
4a1b91ea | 5277 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5278 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5279 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5280 | else |
5281 | { | |
5282 | const i386_operand_type *type = NULL; | |
5283 | ||
5284 | i.memshift = 0; | |
5285 | for (op = 0; op < i.operands; op++) | |
5286 | if (operand_type_check (i.types[op], anymem)) | |
5287 | { | |
4174bfff JB |
5288 | if (t->opcode_modifier.evex == EVEXLIG) |
5289 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5290 | else if (t->operand_types[op].bitfield.xmmword | |
5291 | + t->operand_types[op].bitfield.ymmword | |
5292 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5293 | type = &t->operand_types[op]; |
5294 | else if (!i.types[op].bitfield.unspecified) | |
5295 | type = &i.types[op]; | |
5296 | } | |
4174bfff JB |
5297 | else if (i.types[op].bitfield.regsimd |
5298 | && t->opcode_modifier.evex != EVEXLIG) | |
7091c612 JB |
5299 | { |
5300 | if (i.types[op].bitfield.zmmword) | |
5301 | i.memshift = 6; | |
5302 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5303 | i.memshift = 5; | |
5304 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5305 | i.memshift = 4; | |
5306 | } | |
5307 | ||
5308 | if (type) | |
5309 | { | |
5310 | if (type->bitfield.zmmword) | |
5311 | i.memshift = 6; | |
5312 | else if (type->bitfield.ymmword) | |
5313 | i.memshift = 5; | |
5314 | else if (type->bitfield.xmmword) | |
5315 | i.memshift = 4; | |
5316 | } | |
5317 | ||
5318 | /* For the check in fits_in_disp8(). */ | |
5319 | if (i.memshift == 0) | |
5320 | i.memshift = -1; | |
5321 | } | |
43234a1e L |
5322 | |
5323 | for (op = 0; op < i.operands; op++) | |
5324 | if (operand_type_check (i.types[op], disp) | |
5325 | && i.op[op].disps->X_op == O_constant) | |
5326 | { | |
b5014f7a | 5327 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5328 | { |
b5014f7a JB |
5329 | i.types[op].bitfield.disp8 = 1; |
5330 | return 0; | |
43234a1e | 5331 | } |
b5014f7a | 5332 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5333 | } |
5334 | } | |
b5014f7a JB |
5335 | |
5336 | i.memshift = 0; | |
43234a1e | 5337 | |
6c30d220 L |
5338 | return 0; |
5339 | } | |
5340 | ||
43f3e2ee | 5341 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5342 | operand types. */ |
5343 | ||
5344 | static int | |
5345 | VEX_check_operands (const insn_template *t) | |
5346 | { | |
86fa6981 | 5347 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5348 | { |
86fa6981 | 5349 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5350 | if (!is_evex_encoding (t)) |
86fa6981 L |
5351 | { |
5352 | i.error = unsupported; | |
5353 | return 1; | |
5354 | } | |
5355 | return 0; | |
43234a1e L |
5356 | } |
5357 | ||
a683cc34 | 5358 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5359 | { |
5360 | /* This instruction template doesn't have VEX prefix. */ | |
5361 | if (i.vec_encoding != vex_encoding_default) | |
5362 | { | |
5363 | i.error = unsupported; | |
5364 | return 1; | |
5365 | } | |
5366 | return 0; | |
5367 | } | |
a683cc34 SP |
5368 | |
5369 | /* Only check VEX_Imm4, which must be the first operand. */ | |
5370 | if (t->operand_types[0].bitfield.vec_imm4) | |
5371 | { | |
5372 | if (i.op[0].imms->X_op != O_constant | |
5373 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5374 | { |
a65babc9 | 5375 | i.error = bad_imm4; |
891edac4 L |
5376 | return 1; |
5377 | } | |
a683cc34 SP |
5378 | |
5379 | /* Turn off Imm8 so that update_imm won't complain. */ | |
5380 | i.types[0] = vec_imm4; | |
5381 | } | |
5382 | ||
5383 | return 0; | |
5384 | } | |
5385 | ||
d3ce72d0 | 5386 | static const insn_template * |
83b16ac6 | 5387 | match_template (char mnem_suffix) |
29b0f896 AM |
5388 | { |
5389 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5390 | const insn_template *t; |
40fb9820 | 5391 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5392 | i386_operand_type overlap4; |
29b0f896 | 5393 | unsigned int found_reverse_match; |
83b16ac6 | 5394 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 5395 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5396 | int addr_prefix_disp; |
a5c311ca | 5397 | unsigned int j; |
3ac21baa | 5398 | unsigned int found_cpu_match, size_match; |
45664ddb | 5399 | unsigned int check_register; |
5614d22c | 5400 | enum i386_error specific_error = 0; |
29b0f896 | 5401 | |
c0f3af97 L |
5402 | #if MAX_OPERANDS != 5 |
5403 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5404 | #endif |
5405 | ||
29b0f896 | 5406 | found_reverse_match = 0; |
539e75ad | 5407 | addr_prefix_disp = -1; |
40fb9820 L |
5408 | |
5409 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
e2195274 JB |
5410 | if (intel_syntax && i.broadcast) |
5411 | /* nothing */; | |
5412 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
40fb9820 L |
5413 | suffix_check.no_bsuf = 1; |
5414 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5415 | suffix_check.no_wsuf = 1; | |
5416 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
5417 | suffix_check.no_ssuf = 1; | |
5418 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5419 | suffix_check.no_lsuf = 1; | |
5420 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5421 | suffix_check.no_qsuf = 1; | |
5422 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 5423 | suffix_check.no_ldsuf = 1; |
29b0f896 | 5424 | |
83b16ac6 JB |
5425 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
5426 | if (intel_syntax) | |
5427 | { | |
5428 | switch (mnem_suffix) | |
5429 | { | |
5430 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
5431 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
5432 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
5433 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
5434 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
5435 | } | |
5436 | } | |
5437 | ||
01559ecc L |
5438 | /* Must have right number of operands. */ |
5439 | i.error = number_of_operands_mismatch; | |
5440 | ||
45aa61fe | 5441 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5442 | { |
539e75ad L |
5443 | addr_prefix_disp = -1; |
5444 | ||
29b0f896 AM |
5445 | if (i.operands != t->operands) |
5446 | continue; | |
5447 | ||
50aecf8c | 5448 | /* Check processor support. */ |
a65babc9 | 5449 | i.error = unsupported; |
c0f3af97 L |
5450 | found_cpu_match = (cpu_flags_match (t) |
5451 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5452 | if (!found_cpu_match) |
5453 | continue; | |
5454 | ||
e1d4d893 | 5455 | /* Check AT&T mnemonic. */ |
a65babc9 | 5456 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5457 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5458 | continue; |
5459 | ||
e92bae62 | 5460 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5461 | i.error = unsupported_syntax; |
5c07affc | 5462 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5463 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5464 | || (intel64 && t->opcode_modifier.amd64) | |
5465 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5466 | continue; |
5467 | ||
20592a94 | 5468 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 5469 | i.error = invalid_instruction_suffix; |
567e4e96 L |
5470 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
5471 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
5472 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5473 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5474 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5475 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5476 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 5477 | continue; |
83b16ac6 JB |
5478 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
5479 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
5480 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
5481 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
5482 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
5483 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
5484 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
5485 | continue; | |
29b0f896 | 5486 | |
3ac21baa JB |
5487 | size_match = operand_size_match (t); |
5488 | if (!size_match) | |
7d5e4556 | 5489 | continue; |
539e75ad | 5490 | |
5c07affc L |
5491 | for (j = 0; j < MAX_OPERANDS; j++) |
5492 | operand_types[j] = t->operand_types[j]; | |
5493 | ||
45aa61fe AM |
5494 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5495 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5496 | && flag_code != CODE_64BIT | |
5497 | && (intel_syntax | |
40fb9820 | 5498 | ? (!t->opcode_modifier.ignoresize |
625cbd7a | 5499 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5500 | && !intel_float_operand (t->name)) |
5501 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 5502 | && ((!operand_types[0].bitfield.regmmx |
1b54b8d7 | 5503 | && !operand_types[0].bitfield.regsimd) |
40fb9820 | 5504 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5505 | && !operand_types[t->operands > 1].bitfield.regsimd)) |
45aa61fe AM |
5506 | && (t->base_opcode != 0x0fc7 |
5507 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5508 | continue; | |
5509 | ||
192dc9c6 JB |
5510 | /* In general, don't allow 32-bit operands on pre-386. */ |
5511 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5512 | && !cpu_arch_flags.bitfield.cpui386 | |
5513 | && (intel_syntax | |
5514 | ? (!t->opcode_modifier.ignoresize | |
5515 | && !intel_float_operand (t->name)) | |
5516 | : intel_float_operand (t->name) != 2) | |
5517 | && ((!operand_types[0].bitfield.regmmx | |
1b54b8d7 | 5518 | && !operand_types[0].bitfield.regsimd) |
192dc9c6 | 5519 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5520 | && !operand_types[t->operands > 1].bitfield.regsimd))) |
192dc9c6 JB |
5521 | continue; |
5522 | ||
29b0f896 | 5523 | /* Do not verify operands when there are none. */ |
50aecf8c | 5524 | else |
29b0f896 | 5525 | { |
c6fb90c8 | 5526 | if (!t->operands) |
2dbab7d5 L |
5527 | /* We've found a match; break out of loop. */ |
5528 | break; | |
29b0f896 | 5529 | } |
252b5132 | 5530 | |
539e75ad L |
5531 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5532 | into Disp32/Disp16/Disp32 operand. */ | |
5533 | if (i.prefix[ADDR_PREFIX] != 0) | |
5534 | { | |
40fb9820 | 5535 | /* There should be only one Disp operand. */ |
539e75ad L |
5536 | switch (flag_code) |
5537 | { | |
5538 | case CODE_16BIT: | |
40fb9820 L |
5539 | for (j = 0; j < MAX_OPERANDS; j++) |
5540 | { | |
5541 | if (operand_types[j].bitfield.disp16) | |
5542 | { | |
5543 | addr_prefix_disp = j; | |
5544 | operand_types[j].bitfield.disp32 = 1; | |
5545 | operand_types[j].bitfield.disp16 = 0; | |
5546 | break; | |
5547 | } | |
5548 | } | |
539e75ad L |
5549 | break; |
5550 | case CODE_32BIT: | |
40fb9820 L |
5551 | for (j = 0; j < MAX_OPERANDS; j++) |
5552 | { | |
5553 | if (operand_types[j].bitfield.disp32) | |
5554 | { | |
5555 | addr_prefix_disp = j; | |
5556 | operand_types[j].bitfield.disp32 = 0; | |
5557 | operand_types[j].bitfield.disp16 = 1; | |
5558 | break; | |
5559 | } | |
5560 | } | |
539e75ad L |
5561 | break; |
5562 | case CODE_64BIT: | |
40fb9820 L |
5563 | for (j = 0; j < MAX_OPERANDS; j++) |
5564 | { | |
5565 | if (operand_types[j].bitfield.disp64) | |
5566 | { | |
5567 | addr_prefix_disp = j; | |
5568 | operand_types[j].bitfield.disp64 = 0; | |
5569 | operand_types[j].bitfield.disp32 = 1; | |
5570 | break; | |
5571 | } | |
5572 | } | |
539e75ad L |
5573 | break; |
5574 | } | |
539e75ad L |
5575 | } |
5576 | ||
02a86693 L |
5577 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5578 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5579 | continue; | |
5580 | ||
56ffb741 | 5581 | /* We check register size if needed. */ |
e2195274 JB |
5582 | if (t->opcode_modifier.checkregsize) |
5583 | { | |
5584 | check_register = (1 << t->operands) - 1; | |
5585 | if (i.broadcast) | |
5586 | check_register &= ~(1 << i.broadcast->operand); | |
5587 | } | |
5588 | else | |
5589 | check_register = 0; | |
5590 | ||
c6fb90c8 | 5591 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5592 | switch (t->operands) |
5593 | { | |
5594 | case 1: | |
40fb9820 | 5595 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5596 | continue; |
5597 | break; | |
5598 | case 2: | |
33eaf5de | 5599 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5600 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5601 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5602 | zero-extend %eax to %rax. */ | |
5603 | if (flag_code == CODE_64BIT | |
5604 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
5605 | && operand_type_equal (&i.types [0], &acc32) |
5606 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 5607 | continue; |
1212781b JB |
5608 | /* xrelease mov %eax, <disp> is another special case. It must not |
5609 | match the accumulator-only encoding of mov. */ | |
5610 | if (flag_code != CODE_64BIT | |
5611 | && i.hle_prefix | |
5612 | && t->base_opcode == 0xa0 | |
5613 | && i.types[0].bitfield.acc | |
5614 | && operand_type_check (i.types[1], anymem)) | |
5615 | continue; | |
3ac21baa JB |
5616 | if (!(size_match & MATCH_STRAIGHT)) |
5617 | goto check_reverse; | |
86fa6981 L |
5618 | /* If we want store form, we reverse direction of operands. */ |
5619 | if (i.dir_encoding == dir_encoding_store | |
5620 | && t->opcode_modifier.d) | |
5621 | goto check_reverse; | |
1a0670f3 | 5622 | /* Fall through. */ |
b6169b20 | 5623 | |
29b0f896 | 5624 | case 3: |
86fa6981 L |
5625 | /* If we want store form, we skip the current load. */ |
5626 | if (i.dir_encoding == dir_encoding_store | |
5627 | && i.mem_operands == 0 | |
5628 | && t->opcode_modifier.load) | |
fa99fab2 | 5629 | continue; |
1a0670f3 | 5630 | /* Fall through. */ |
f48ff2ae | 5631 | case 4: |
c0f3af97 | 5632 | case 5: |
c6fb90c8 | 5633 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5634 | if (!operand_type_match (overlap0, i.types[0]) |
5635 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 5636 | || ((check_register & 3) == 3 |
dc821c5f | 5637 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5638 | operand_types[0], |
dc821c5f | 5639 | i.types[1], |
40fb9820 | 5640 | operand_types[1]))) |
29b0f896 AM |
5641 | { |
5642 | /* Check if other direction is valid ... */ | |
38e314eb | 5643 | if (!t->opcode_modifier.d) |
29b0f896 AM |
5644 | continue; |
5645 | ||
b6169b20 | 5646 | check_reverse: |
3ac21baa JB |
5647 | if (!(size_match & MATCH_REVERSE)) |
5648 | continue; | |
29b0f896 | 5649 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
5650 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
5651 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
5652 | if (!operand_type_match (overlap0, i.types[0]) |
5653 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb | 5654 | || (check_register |
dc821c5f | 5655 | && !operand_type_register_match (i.types[0], |
45664ddb | 5656 | operand_types[1], |
45664ddb L |
5657 | i.types[1], |
5658 | operand_types[0]))) | |
29b0f896 AM |
5659 | { |
5660 | /* Does not match either direction. */ | |
5661 | continue; | |
5662 | } | |
38e314eb | 5663 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 5664 | we've found. */ |
38e314eb JB |
5665 | if (!t->opcode_modifier.d) |
5666 | found_reverse_match = 0; | |
5667 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 L |
5668 | found_reverse_match = Opcode_FloatD; |
5669 | else | |
38e314eb | 5670 | found_reverse_match = Opcode_D; |
40fb9820 | 5671 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5672 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5673 | } |
f48ff2ae | 5674 | else |
29b0f896 | 5675 | { |
f48ff2ae | 5676 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5677 | switch (t->operands) |
5678 | { | |
c0f3af97 L |
5679 | case 5: |
5680 | overlap4 = operand_type_and (i.types[4], | |
5681 | operand_types[4]); | |
1a0670f3 | 5682 | /* Fall through. */ |
d1cbb4db | 5683 | case 4: |
c6fb90c8 L |
5684 | overlap3 = operand_type_and (i.types[3], |
5685 | operand_types[3]); | |
1a0670f3 | 5686 | /* Fall through. */ |
d1cbb4db | 5687 | case 3: |
c6fb90c8 L |
5688 | overlap2 = operand_type_and (i.types[2], |
5689 | operand_types[2]); | |
d1cbb4db L |
5690 | break; |
5691 | } | |
29b0f896 | 5692 | |
f48ff2ae L |
5693 | switch (t->operands) |
5694 | { | |
c0f3af97 L |
5695 | case 5: |
5696 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 5697 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 5698 | operand_types[3], |
c0f3af97 L |
5699 | i.types[4], |
5700 | operand_types[4])) | |
5701 | continue; | |
1a0670f3 | 5702 | /* Fall through. */ |
f48ff2ae | 5703 | case 4: |
40fb9820 | 5704 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
5705 | || ((check_register & 0xa) == 0xa |
5706 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
5707 | operand_types[1], |
5708 | i.types[3], | |
e2195274 JB |
5709 | operand_types[3])) |
5710 | || ((check_register & 0xc) == 0xc | |
5711 | && !operand_type_register_match (i.types[2], | |
5712 | operand_types[2], | |
5713 | i.types[3], | |
5714 | operand_types[3]))) | |
f48ff2ae | 5715 | continue; |
1a0670f3 | 5716 | /* Fall through. */ |
f48ff2ae L |
5717 | case 3: |
5718 | /* Here we make use of the fact that there are no | |
23e42951 | 5719 | reverse match 3 operand instructions. */ |
40fb9820 | 5720 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
5721 | || ((check_register & 5) == 5 |
5722 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
5723 | operand_types[0], |
5724 | i.types[2], | |
e2195274 JB |
5725 | operand_types[2])) |
5726 | || ((check_register & 6) == 6 | |
5727 | && !operand_type_register_match (i.types[1], | |
5728 | operand_types[1], | |
5729 | i.types[2], | |
5730 | operand_types[2]))) | |
f48ff2ae L |
5731 | continue; |
5732 | break; | |
5733 | } | |
29b0f896 | 5734 | } |
f48ff2ae | 5735 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5736 | slip through to break. */ |
5737 | } | |
3629bb00 | 5738 | if (!found_cpu_match) |
29b0f896 AM |
5739 | { |
5740 | found_reverse_match = 0; | |
5741 | continue; | |
5742 | } | |
c0f3af97 | 5743 | |
5614d22c JB |
5744 | /* Check if vector and VEX operands are valid. */ |
5745 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5746 | { | |
5747 | specific_error = i.error; | |
5748 | continue; | |
5749 | } | |
a683cc34 | 5750 | |
29b0f896 AM |
5751 | /* We've found a match; break out of loop. */ |
5752 | break; | |
5753 | } | |
5754 | ||
5755 | if (t == current_templates->end) | |
5756 | { | |
5757 | /* We found no match. */ | |
a65babc9 | 5758 | const char *err_msg; |
5614d22c | 5759 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5760 | { |
5761 | default: | |
5762 | abort (); | |
86e026a4 | 5763 | case operand_size_mismatch: |
a65babc9 L |
5764 | err_msg = _("operand size mismatch"); |
5765 | break; | |
5766 | case operand_type_mismatch: | |
5767 | err_msg = _("operand type mismatch"); | |
5768 | break; | |
5769 | case register_type_mismatch: | |
5770 | err_msg = _("register type mismatch"); | |
5771 | break; | |
5772 | case number_of_operands_mismatch: | |
5773 | err_msg = _("number of operands mismatch"); | |
5774 | break; | |
5775 | case invalid_instruction_suffix: | |
5776 | err_msg = _("invalid instruction suffix"); | |
5777 | break; | |
5778 | case bad_imm4: | |
4a2608e3 | 5779 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 5780 | break; |
a65babc9 L |
5781 | case unsupported_with_intel_mnemonic: |
5782 | err_msg = _("unsupported with Intel mnemonic"); | |
5783 | break; | |
5784 | case unsupported_syntax: | |
5785 | err_msg = _("unsupported syntax"); | |
5786 | break; | |
5787 | case unsupported: | |
35262a23 | 5788 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
5789 | current_templates->start->name); |
5790 | return NULL; | |
6c30d220 L |
5791 | case invalid_vsib_address: |
5792 | err_msg = _("invalid VSIB address"); | |
5793 | break; | |
7bab8ab5 JB |
5794 | case invalid_vector_register_set: |
5795 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5796 | break; | |
6c30d220 L |
5797 | case unsupported_vector_index_register: |
5798 | err_msg = _("unsupported vector index register"); | |
5799 | break; | |
43234a1e L |
5800 | case unsupported_broadcast: |
5801 | err_msg = _("unsupported broadcast"); | |
5802 | break; | |
43234a1e L |
5803 | case broadcast_needed: |
5804 | err_msg = _("broadcast is needed for operand of such type"); | |
5805 | break; | |
5806 | case unsupported_masking: | |
5807 | err_msg = _("unsupported masking"); | |
5808 | break; | |
5809 | case mask_not_on_destination: | |
5810 | err_msg = _("mask not on destination operand"); | |
5811 | break; | |
5812 | case no_default_mask: | |
5813 | err_msg = _("default mask isn't allowed"); | |
5814 | break; | |
5815 | case unsupported_rc_sae: | |
5816 | err_msg = _("unsupported static rounding/sae"); | |
5817 | break; | |
5818 | case rc_sae_operand_not_last_imm: | |
5819 | if (intel_syntax) | |
5820 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
5821 | else | |
5822 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
5823 | break; | |
5824 | case invalid_register_operand: | |
5825 | err_msg = _("invalid register operand"); | |
5826 | break; | |
a65babc9 L |
5827 | } |
5828 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 5829 | current_templates->start->name); |
fa99fab2 | 5830 | return NULL; |
29b0f896 | 5831 | } |
252b5132 | 5832 | |
29b0f896 AM |
5833 | if (!quiet_warnings) |
5834 | { | |
5835 | if (!intel_syntax | |
40fb9820 L |
5836 | && (i.types[0].bitfield.jumpabsolute |
5837 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
5838 | { |
5839 | as_warn (_("indirect %s without `*'"), t->name); | |
5840 | } | |
5841 | ||
40fb9820 L |
5842 | if (t->opcode_modifier.isprefix |
5843 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
5844 | { |
5845 | /* Warn them that a data or address size prefix doesn't | |
5846 | affect assembly of the next line of code. */ | |
5847 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
5848 | } | |
5849 | } | |
5850 | ||
5851 | /* Copy the template we found. */ | |
5852 | i.tm = *t; | |
539e75ad L |
5853 | |
5854 | if (addr_prefix_disp != -1) | |
5855 | i.tm.operand_types[addr_prefix_disp] | |
5856 | = operand_types[addr_prefix_disp]; | |
5857 | ||
29b0f896 AM |
5858 | if (found_reverse_match) |
5859 | { | |
5860 | /* If we found a reverse match we must alter the opcode | |
5861 | direction bit. found_reverse_match holds bits to change | |
5862 | (different for int & float insns). */ | |
5863 | ||
5864 | i.tm.base_opcode ^= found_reverse_match; | |
5865 | ||
539e75ad L |
5866 | i.tm.operand_types[0] = operand_types[1]; |
5867 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
5868 | } |
5869 | ||
fa99fab2 | 5870 | return t; |
29b0f896 AM |
5871 | } |
5872 | ||
5873 | static int | |
e3bb37b5 | 5874 | check_string (void) |
29b0f896 | 5875 | { |
40fb9820 L |
5876 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
5877 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
5878 | { |
5879 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
5880 | { | |
a87af027 | 5881 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5882 | i.tm.name, |
a87af027 JB |
5883 | mem_op + 1, |
5884 | register_prefix); | |
29b0f896 AM |
5885 | return 0; |
5886 | } | |
5887 | /* There's only ever one segment override allowed per instruction. | |
5888 | This instruction possibly has a legal segment override on the | |
5889 | second operand, so copy the segment to where non-string | |
5890 | instructions store it, allowing common code. */ | |
5891 | i.seg[0] = i.seg[1]; | |
5892 | } | |
40fb9820 | 5893 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
5894 | { |
5895 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
5896 | { | |
a87af027 | 5897 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5898 | i.tm.name, |
a87af027 JB |
5899 | mem_op + 2, |
5900 | register_prefix); | |
29b0f896 AM |
5901 | return 0; |
5902 | } | |
5903 | } | |
5904 | return 1; | |
5905 | } | |
5906 | ||
5907 | static int | |
543613e9 | 5908 | process_suffix (void) |
29b0f896 AM |
5909 | { |
5910 | /* If matched instruction specifies an explicit instruction mnemonic | |
5911 | suffix, use it. */ | |
40fb9820 L |
5912 | if (i.tm.opcode_modifier.size16) |
5913 | i.suffix = WORD_MNEM_SUFFIX; | |
5914 | else if (i.tm.opcode_modifier.size32) | |
5915 | i.suffix = LONG_MNEM_SUFFIX; | |
5916 | else if (i.tm.opcode_modifier.size64) | |
5917 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
5918 | else if (i.reg_operands) |
5919 | { | |
5920 | /* If there's no instruction mnemonic suffix we try to invent one | |
5921 | based on register operands. */ | |
5922 | if (!i.suffix) | |
5923 | { | |
5924 | /* We take i.suffix from the last register operand specified, | |
5925 | Destination register type is more significant than source | |
381d071f L |
5926 | register type. crc32 in SSE4.2 prefers source register |
5927 | type. */ | |
5928 | if (i.tm.base_opcode == 0xf20f38f1) | |
5929 | { | |
dc821c5f | 5930 | if (i.types[0].bitfield.reg && i.types[0].bitfield.word) |
40fb9820 | 5931 | i.suffix = WORD_MNEM_SUFFIX; |
dc821c5f | 5932 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword) |
40fb9820 | 5933 | i.suffix = LONG_MNEM_SUFFIX; |
dc821c5f | 5934 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword) |
40fb9820 | 5935 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f | 5936 | } |
9344ff29 | 5937 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 5938 | { |
dc821c5f | 5939 | if (i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
20592a94 L |
5940 | i.suffix = BYTE_MNEM_SUFFIX; |
5941 | } | |
381d071f L |
5942 | |
5943 | if (!i.suffix) | |
5944 | { | |
5945 | int op; | |
5946 | ||
20592a94 L |
5947 | if (i.tm.base_opcode == 0xf20f38f1 |
5948 | || i.tm.base_opcode == 0xf20f38f0) | |
5949 | { | |
5950 | /* We have to know the operand size for crc32. */ | |
5951 | as_bad (_("ambiguous memory operand size for `%s`"), | |
5952 | i.tm.name); | |
5953 | return 0; | |
5954 | } | |
5955 | ||
381d071f | 5956 | for (op = i.operands; --op >= 0;) |
b76bc5d5 JB |
5957 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
5958 | && !i.tm.operand_types[op].bitfield.shiftcount) | |
381d071f | 5959 | { |
8819ada6 JB |
5960 | if (!i.types[op].bitfield.reg) |
5961 | continue; | |
5962 | if (i.types[op].bitfield.byte) | |
5963 | i.suffix = BYTE_MNEM_SUFFIX; | |
5964 | else if (i.types[op].bitfield.word) | |
5965 | i.suffix = WORD_MNEM_SUFFIX; | |
5966 | else if (i.types[op].bitfield.dword) | |
5967 | i.suffix = LONG_MNEM_SUFFIX; | |
5968 | else if (i.types[op].bitfield.qword) | |
5969 | i.suffix = QWORD_MNEM_SUFFIX; | |
5970 | else | |
5971 | continue; | |
5972 | break; | |
381d071f L |
5973 | } |
5974 | } | |
29b0f896 AM |
5975 | } |
5976 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
5977 | { | |
2eb952a4 L |
5978 | if (intel_syntax |
5979 | && i.tm.opcode_modifier.ignoresize | |
5980 | && i.tm.opcode_modifier.no_bsuf) | |
5981 | i.suffix = 0; | |
5982 | else if (!check_byte_reg ()) | |
29b0f896 AM |
5983 | return 0; |
5984 | } | |
5985 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5986 | { | |
2eb952a4 L |
5987 | if (intel_syntax |
5988 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
5989 | && i.tm.opcode_modifier.no_lsuf |
5990 | && !i.tm.opcode_modifier.todword | |
5991 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
5992 | i.suffix = 0; |
5993 | else if (!check_long_reg ()) | |
29b0f896 AM |
5994 | return 0; |
5995 | } | |
5996 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5997 | { | |
955e1e6a L |
5998 | if (intel_syntax |
5999 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6000 | && i.tm.opcode_modifier.no_qsuf |
6001 | && !i.tm.opcode_modifier.todword | |
6002 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6003 | i.suffix = 0; |
6004 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6005 | return 0; |
6006 | } | |
6007 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6008 | { | |
2eb952a4 L |
6009 | if (intel_syntax |
6010 | && i.tm.opcode_modifier.ignoresize | |
6011 | && i.tm.opcode_modifier.no_wsuf) | |
6012 | i.suffix = 0; | |
6013 | else if (!check_word_reg ()) | |
29b0f896 AM |
6014 | return 0; |
6015 | } | |
40fb9820 | 6016 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
6017 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6018 | ; | |
6019 | else | |
6020 | abort (); | |
6021 | } | |
40fb9820 | 6022 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
6023 | && !i.suffix |
6024 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 6025 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
6026 | { |
6027 | i.suffix = stackop_size; | |
6028 | } | |
9306ca4a JB |
6029 | else if (intel_syntax |
6030 | && !i.suffix | |
40fb9820 L |
6031 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
6032 | || i.tm.opcode_modifier.jumpbyte | |
6033 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
6034 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6035 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6036 | { |
6037 | switch (flag_code) | |
6038 | { | |
6039 | case CODE_64BIT: | |
40fb9820 | 6040 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6041 | { |
6042 | i.suffix = QWORD_MNEM_SUFFIX; | |
6043 | break; | |
6044 | } | |
1a0670f3 | 6045 | /* Fall through. */ |
9306ca4a | 6046 | case CODE_32BIT: |
40fb9820 | 6047 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6048 | i.suffix = LONG_MNEM_SUFFIX; |
6049 | break; | |
6050 | case CODE_16BIT: | |
40fb9820 | 6051 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6052 | i.suffix = WORD_MNEM_SUFFIX; |
6053 | break; | |
6054 | } | |
6055 | } | |
252b5132 | 6056 | |
9306ca4a | 6057 | if (!i.suffix) |
29b0f896 | 6058 | { |
9306ca4a JB |
6059 | if (!intel_syntax) |
6060 | { | |
40fb9820 | 6061 | if (i.tm.opcode_modifier.w) |
9306ca4a | 6062 | { |
4eed87de AM |
6063 | as_bad (_("no instruction mnemonic suffix given and " |
6064 | "no register operands; can't size instruction")); | |
9306ca4a JB |
6065 | return 0; |
6066 | } | |
6067 | } | |
6068 | else | |
6069 | { | |
40fb9820 | 6070 | unsigned int suffixes; |
7ab9ffdd | 6071 | |
40fb9820 L |
6072 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
6073 | if (!i.tm.opcode_modifier.no_wsuf) | |
6074 | suffixes |= 1 << 1; | |
6075 | if (!i.tm.opcode_modifier.no_lsuf) | |
6076 | suffixes |= 1 << 2; | |
fc4adea1 | 6077 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
6078 | suffixes |= 1 << 3; |
6079 | if (!i.tm.opcode_modifier.no_ssuf) | |
6080 | suffixes |= 1 << 4; | |
c2b9da16 | 6081 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
6082 | suffixes |= 1 << 5; |
6083 | ||
6084 | /* There are more than suffix matches. */ | |
6085 | if (i.tm.opcode_modifier.w | |
9306ca4a | 6086 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
6087 | && !i.tm.opcode_modifier.defaultsize |
6088 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
6089 | { |
6090 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
6091 | return 0; | |
6092 | } | |
6093 | } | |
29b0f896 | 6094 | } |
252b5132 | 6095 | |
d2224064 JB |
6096 | /* Change the opcode based on the operand size given by i.suffix. */ |
6097 | switch (i.suffix) | |
29b0f896 | 6098 | { |
d2224064 JB |
6099 | /* Size floating point instruction. */ |
6100 | case LONG_MNEM_SUFFIX: | |
6101 | if (i.tm.opcode_modifier.floatmf) | |
6102 | { | |
6103 | i.tm.base_opcode ^= 4; | |
6104 | break; | |
6105 | } | |
6106 | /* fall through */ | |
6107 | case WORD_MNEM_SUFFIX: | |
6108 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6109 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6110 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6111 | { |
40fb9820 | 6112 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
6113 | i.tm.base_opcode |= 8; |
6114 | else | |
6115 | i.tm.base_opcode |= 1; | |
6116 | } | |
d2224064 JB |
6117 | /* fall through */ |
6118 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6119 | /* Now select between word & dword operations via the operand |
6120 | size prefix, except for instructions that will ignore this | |
6121 | prefix anyway. */ | |
75c0a438 L |
6122 | if (i.reg_operands > 0 |
6123 | && i.types[0].bitfield.reg | |
6124 | && i.tm.opcode_modifier.addrprefixopreg | |
6125 | && (i.tm.opcode_modifier.immext | |
6126 | || i.operands == 1)) | |
cb712a9e | 6127 | { |
ca61edf2 L |
6128 | /* The address size override prefix changes the size of the |
6129 | first operand. */ | |
40fb9820 | 6130 | if ((flag_code == CODE_32BIT |
75c0a438 | 6131 | && i.op[0].regs->reg_type.bitfield.word) |
40fb9820 | 6132 | || (flag_code != CODE_32BIT |
75c0a438 | 6133 | && i.op[0].regs->reg_type.bitfield.dword)) |
cb712a9e L |
6134 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
6135 | return 0; | |
6136 | } | |
6137 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
40fb9820 L |
6138 | && !i.tm.opcode_modifier.ignoresize |
6139 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
6140 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
6141 | || (flag_code == CODE_64BIT | |
40fb9820 | 6142 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
6143 | { |
6144 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6145 | |
40fb9820 | 6146 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 6147 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6148 | |
29b0f896 AM |
6149 | if (!add_prefix (prefix)) |
6150 | return 0; | |
24eab124 | 6151 | } |
252b5132 | 6152 | |
29b0f896 AM |
6153 | /* Set mode64 for an operand. */ |
6154 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6155 | && flag_code == CODE_64BIT |
d2224064 | 6156 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6157 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6158 | need rex64. */ |
6159 | && ! (i.operands == 2 | |
6160 | && i.tm.base_opcode == 0x90 | |
6161 | && i.tm.extension_opcode == None | |
6162 | && operand_type_equal (&i.types [0], &acc64) | |
6163 | && operand_type_equal (&i.types [1], &acc64))) | |
6164 | i.rex |= REX_W; | |
3e73aa7c | 6165 | |
d2224064 | 6166 | break; |
29b0f896 | 6167 | } |
7ecd2f8b | 6168 | |
c0a30a9f L |
6169 | if (i.reg_operands != 0 |
6170 | && i.operands > 1 | |
6171 | && i.tm.opcode_modifier.addrprefixopreg | |
6172 | && !i.tm.opcode_modifier.immext) | |
6173 | { | |
6174 | /* Check invalid register operand when the address size override | |
6175 | prefix changes the size of register operands. */ | |
6176 | unsigned int op; | |
6177 | enum { need_word, need_dword, need_qword } need; | |
6178 | ||
6179 | if (flag_code == CODE_32BIT) | |
6180 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6181 | else | |
6182 | { | |
6183 | if (i.prefix[ADDR_PREFIX]) | |
6184 | need = need_dword; | |
6185 | else | |
6186 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
6187 | } | |
6188 | ||
6189 | for (op = 0; op < i.operands; op++) | |
6190 | if (i.types[op].bitfield.reg | |
6191 | && ((need == need_word | |
6192 | && !i.op[op].regs->reg_type.bitfield.word) | |
6193 | || (need == need_dword | |
6194 | && !i.op[op].regs->reg_type.bitfield.dword) | |
6195 | || (need == need_qword | |
6196 | && !i.op[op].regs->reg_type.bitfield.qword))) | |
6197 | { | |
6198 | as_bad (_("invalid register operand size for `%s'"), | |
6199 | i.tm.name); | |
6200 | return 0; | |
6201 | } | |
6202 | } | |
6203 | ||
29b0f896 AM |
6204 | return 1; |
6205 | } | |
3e73aa7c | 6206 | |
29b0f896 | 6207 | static int |
543613e9 | 6208 | check_byte_reg (void) |
29b0f896 AM |
6209 | { |
6210 | int op; | |
543613e9 | 6211 | |
29b0f896 AM |
6212 | for (op = i.operands; --op >= 0;) |
6213 | { | |
dc821c5f JB |
6214 | /* Skip non-register operands. */ |
6215 | if (!i.types[op].bitfield.reg) | |
6216 | continue; | |
6217 | ||
29b0f896 AM |
6218 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6219 | 32 bit version of an eight bit register, we will just use the | |
6220 | low portion, and that's OK too. */ | |
dc821c5f | 6221 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6222 | continue; |
6223 | ||
5a819eb9 JB |
6224 | /* I/O port address operands are OK too. */ |
6225 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
6226 | continue; | |
6227 | ||
9344ff29 L |
6228 | /* crc32 doesn't generate this warning. */ |
6229 | if (i.tm.base_opcode == 0xf20f38f0) | |
6230 | continue; | |
6231 | ||
dc821c5f JB |
6232 | if ((i.types[op].bitfield.word |
6233 | || i.types[op].bitfield.dword | |
6234 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
6235 | && i.op[op].regs->reg_num < 4 |
6236 | /* Prohibit these changes in 64bit mode, since the lowering | |
6237 | would be more complicated. */ | |
6238 | && flag_code != CODE_64BIT) | |
29b0f896 | 6239 | { |
29b0f896 | 6240 | #if REGISTER_WARNINGS |
5a819eb9 | 6241 | if (!quiet_warnings) |
a540244d L |
6242 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6243 | register_prefix, | |
dc821c5f | 6244 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
6245 | ? REGNAM_AL - REGNAM_AX |
6246 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 6247 | register_prefix, |
29b0f896 AM |
6248 | i.op[op].regs->reg_name, |
6249 | i.suffix); | |
6250 | #endif | |
6251 | continue; | |
6252 | } | |
6253 | /* Any other register is bad. */ | |
dc821c5f | 6254 | if (i.types[op].bitfield.reg |
40fb9820 | 6255 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 6256 | || i.types[op].bitfield.regsimd |
40fb9820 L |
6257 | || i.types[op].bitfield.sreg2 |
6258 | || i.types[op].bitfield.sreg3 | |
6259 | || i.types[op].bitfield.control | |
6260 | || i.types[op].bitfield.debug | |
ca0d63fe | 6261 | || i.types[op].bitfield.test) |
29b0f896 | 6262 | { |
a540244d L |
6263 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6264 | register_prefix, | |
29b0f896 AM |
6265 | i.op[op].regs->reg_name, |
6266 | i.tm.name, | |
6267 | i.suffix); | |
6268 | return 0; | |
6269 | } | |
6270 | } | |
6271 | return 1; | |
6272 | } | |
6273 | ||
6274 | static int | |
e3bb37b5 | 6275 | check_long_reg (void) |
29b0f896 AM |
6276 | { |
6277 | int op; | |
6278 | ||
6279 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6280 | /* Skip non-register operands. */ |
6281 | if (!i.types[op].bitfield.reg) | |
6282 | continue; | |
29b0f896 AM |
6283 | /* Reject eight bit registers, except where the template requires |
6284 | them. (eg. movzb) */ | |
dc821c5f JB |
6285 | else if (i.types[op].bitfield.byte |
6286 | && (i.tm.operand_types[op].bitfield.reg | |
6287 | || i.tm.operand_types[op].bitfield.acc) | |
6288 | && (i.tm.operand_types[op].bitfield.word | |
6289 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6290 | { |
a540244d L |
6291 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6292 | register_prefix, | |
29b0f896 AM |
6293 | i.op[op].regs->reg_name, |
6294 | i.tm.name, | |
6295 | i.suffix); | |
6296 | return 0; | |
6297 | } | |
e4630f71 | 6298 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 6299 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6300 | && i.types[op].bitfield.word |
6301 | && (i.tm.operand_types[op].bitfield.reg | |
6302 | || i.tm.operand_types[op].bitfield.acc) | |
6303 | && i.tm.operand_types[op].bitfield.dword) | |
29b0f896 AM |
6304 | { |
6305 | /* Prohibit these changes in the 64bit mode, since the | |
6306 | lowering is more complicated. */ | |
6307 | if (flag_code == CODE_64BIT) | |
252b5132 | 6308 | { |
2b5d6a91 | 6309 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6310 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6311 | i.suffix); |
6312 | return 0; | |
252b5132 | 6313 | } |
29b0f896 | 6314 | #if REGISTER_WARNINGS |
cecf1424 JB |
6315 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6316 | register_prefix, | |
6317 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
6318 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 6319 | #endif |
252b5132 | 6320 | } |
e4630f71 | 6321 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f JB |
6322 | else if (i.types[op].bitfield.qword |
6323 | && (i.tm.operand_types[op].bitfield.reg | |
6324 | || i.tm.operand_types[op].bitfield.acc) | |
6325 | && i.tm.operand_types[op].bitfield.dword) | |
252b5132 | 6326 | { |
34828aad | 6327 | if (intel_syntax |
ca61edf2 | 6328 | && i.tm.opcode_modifier.toqword |
1b54b8d7 | 6329 | && !i.types[0].bitfield.regsimd) |
34828aad | 6330 | { |
ca61edf2 | 6331 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6332 | i.suffix = QWORD_MNEM_SUFFIX; |
6333 | } | |
6334 | else | |
6335 | { | |
2b5d6a91 | 6336 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6337 | register_prefix, i.op[op].regs->reg_name, |
6338 | i.suffix); | |
6339 | return 0; | |
6340 | } | |
29b0f896 AM |
6341 | } |
6342 | return 1; | |
6343 | } | |
252b5132 | 6344 | |
29b0f896 | 6345 | static int |
e3bb37b5 | 6346 | check_qword_reg (void) |
29b0f896 AM |
6347 | { |
6348 | int op; | |
252b5132 | 6349 | |
29b0f896 | 6350 | for (op = i.operands; --op >= 0; ) |
dc821c5f JB |
6351 | /* Skip non-register operands. */ |
6352 | if (!i.types[op].bitfield.reg) | |
6353 | continue; | |
29b0f896 AM |
6354 | /* Reject eight bit registers, except where the template requires |
6355 | them. (eg. movzb) */ | |
dc821c5f JB |
6356 | else if (i.types[op].bitfield.byte |
6357 | && (i.tm.operand_types[op].bitfield.reg | |
6358 | || i.tm.operand_types[op].bitfield.acc) | |
6359 | && (i.tm.operand_types[op].bitfield.word | |
6360 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6361 | { |
a540244d L |
6362 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6363 | register_prefix, | |
29b0f896 AM |
6364 | i.op[op].regs->reg_name, |
6365 | i.tm.name, | |
6366 | i.suffix); | |
6367 | return 0; | |
6368 | } | |
e4630f71 | 6369 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6370 | else if ((i.types[op].bitfield.word |
6371 | || i.types[op].bitfield.dword) | |
6372 | && (i.tm.operand_types[op].bitfield.reg | |
6373 | || i.tm.operand_types[op].bitfield.acc) | |
6374 | && i.tm.operand_types[op].bitfield.qword) | |
29b0f896 AM |
6375 | { |
6376 | /* Prohibit these changes in the 64bit mode, since the | |
6377 | lowering is more complicated. */ | |
34828aad | 6378 | if (intel_syntax |
ca61edf2 | 6379 | && i.tm.opcode_modifier.todword |
1b54b8d7 | 6380 | && !i.types[0].bitfield.regsimd) |
34828aad | 6381 | { |
ca61edf2 | 6382 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6383 | i.suffix = LONG_MNEM_SUFFIX; |
6384 | } | |
6385 | else | |
6386 | { | |
2b5d6a91 | 6387 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6388 | register_prefix, i.op[op].regs->reg_name, |
6389 | i.suffix); | |
6390 | return 0; | |
6391 | } | |
252b5132 | 6392 | } |
29b0f896 AM |
6393 | return 1; |
6394 | } | |
252b5132 | 6395 | |
29b0f896 | 6396 | static int |
e3bb37b5 | 6397 | check_word_reg (void) |
29b0f896 AM |
6398 | { |
6399 | int op; | |
6400 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6401 | /* Skip non-register operands. */ |
6402 | if (!i.types[op].bitfield.reg) | |
6403 | continue; | |
29b0f896 AM |
6404 | /* Reject eight bit registers, except where the template requires |
6405 | them. (eg. movzb) */ | |
dc821c5f JB |
6406 | else if (i.types[op].bitfield.byte |
6407 | && (i.tm.operand_types[op].bitfield.reg | |
6408 | || i.tm.operand_types[op].bitfield.acc) | |
6409 | && (i.tm.operand_types[op].bitfield.word | |
6410 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6411 | { |
a540244d L |
6412 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6413 | register_prefix, | |
29b0f896 AM |
6414 | i.op[op].regs->reg_name, |
6415 | i.tm.name, | |
6416 | i.suffix); | |
6417 | return 0; | |
6418 | } | |
e4630f71 | 6419 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 6420 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6421 | && (i.types[op].bitfield.dword |
6422 | || i.types[op].bitfield.qword) | |
6423 | && (i.tm.operand_types[op].bitfield.reg | |
6424 | || i.tm.operand_types[op].bitfield.acc) | |
6425 | && i.tm.operand_types[op].bitfield.word) | |
252b5132 | 6426 | { |
29b0f896 AM |
6427 | /* Prohibit these changes in the 64bit mode, since the |
6428 | lowering is more complicated. */ | |
6429 | if (flag_code == CODE_64BIT) | |
252b5132 | 6430 | { |
2b5d6a91 | 6431 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6432 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6433 | i.suffix); |
6434 | return 0; | |
252b5132 | 6435 | } |
29b0f896 | 6436 | #if REGISTER_WARNINGS |
cecf1424 JB |
6437 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6438 | register_prefix, | |
6439 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
6440 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
6441 | #endif |
6442 | } | |
6443 | return 1; | |
6444 | } | |
252b5132 | 6445 | |
29b0f896 | 6446 | static int |
40fb9820 | 6447 | update_imm (unsigned int j) |
29b0f896 | 6448 | { |
bc0844ae | 6449 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6450 | if ((overlap.bitfield.imm8 |
6451 | || overlap.bitfield.imm8s | |
6452 | || overlap.bitfield.imm16 | |
6453 | || overlap.bitfield.imm32 | |
6454 | || overlap.bitfield.imm32s | |
6455 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6456 | && !operand_type_equal (&overlap, &imm8) |
6457 | && !operand_type_equal (&overlap, &imm8s) | |
6458 | && !operand_type_equal (&overlap, &imm16) | |
6459 | && !operand_type_equal (&overlap, &imm32) | |
6460 | && !operand_type_equal (&overlap, &imm32s) | |
6461 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6462 | { |
6463 | if (i.suffix) | |
6464 | { | |
40fb9820 L |
6465 | i386_operand_type temp; |
6466 | ||
0dfbf9d7 | 6467 | operand_type_set (&temp, 0); |
7ab9ffdd | 6468 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6469 | { |
6470 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6471 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6472 | } | |
6473 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6474 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6475 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6476 | { | |
6477 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6478 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6479 | } | |
6480 | else | |
6481 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6482 | overlap = temp; | |
29b0f896 | 6483 | } |
0dfbf9d7 L |
6484 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6485 | || operand_type_equal (&overlap, &imm16_32) | |
6486 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6487 | { |
40fb9820 | 6488 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6489 | overlap = imm16; |
40fb9820 | 6490 | else |
65da13b5 | 6491 | overlap = imm32s; |
29b0f896 | 6492 | } |
0dfbf9d7 L |
6493 | if (!operand_type_equal (&overlap, &imm8) |
6494 | && !operand_type_equal (&overlap, &imm8s) | |
6495 | && !operand_type_equal (&overlap, &imm16) | |
6496 | && !operand_type_equal (&overlap, &imm32) | |
6497 | && !operand_type_equal (&overlap, &imm32s) | |
6498 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6499 | { |
4eed87de AM |
6500 | as_bad (_("no instruction mnemonic suffix given; " |
6501 | "can't determine immediate size")); | |
29b0f896 AM |
6502 | return 0; |
6503 | } | |
6504 | } | |
40fb9820 | 6505 | i.types[j] = overlap; |
29b0f896 | 6506 | |
40fb9820 L |
6507 | return 1; |
6508 | } | |
6509 | ||
6510 | static int | |
6511 | finalize_imm (void) | |
6512 | { | |
bc0844ae | 6513 | unsigned int j, n; |
29b0f896 | 6514 | |
bc0844ae L |
6515 | /* Update the first 2 immediate operands. */ |
6516 | n = i.operands > 2 ? 2 : i.operands; | |
6517 | if (n) | |
6518 | { | |
6519 | for (j = 0; j < n; j++) | |
6520 | if (update_imm (j) == 0) | |
6521 | return 0; | |
40fb9820 | 6522 | |
bc0844ae L |
6523 | /* The 3rd operand can't be immediate operand. */ |
6524 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6525 | } | |
29b0f896 AM |
6526 | |
6527 | return 1; | |
6528 | } | |
6529 | ||
6530 | static int | |
e3bb37b5 | 6531 | process_operands (void) |
29b0f896 AM |
6532 | { |
6533 | /* Default segment register this instruction will use for memory | |
6534 | accesses. 0 means unknown. This is only for optimizing out | |
6535 | unnecessary segment overrides. */ | |
6536 | const seg_entry *default_seg = 0; | |
6537 | ||
2426c15f | 6538 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6539 | { |
91d6fa6a NC |
6540 | unsigned int dupl = i.operands; |
6541 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6542 | unsigned int j; |
6543 | ||
c0f3af97 | 6544 | /* The destination must be an xmm register. */ |
9c2799c2 | 6545 | gas_assert (i.reg_operands |
91d6fa6a | 6546 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6547 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6548 | |
1b54b8d7 JB |
6549 | if (i.tm.operand_types[0].bitfield.acc |
6550 | && i.tm.operand_types[0].bitfield.xmmword) | |
e2ec9d29 | 6551 | { |
8cd7925b | 6552 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6553 | { |
6554 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6555 | sources. */ | |
1b54b8d7 JB |
6556 | i.tm.operand_types[0].bitfield.acc = 0; |
6557 | i.tm.operand_types[0].bitfield.regsimd = 1; | |
c0f3af97 L |
6558 | goto duplicate; |
6559 | } | |
e2ec9d29 | 6560 | else |
c0f3af97 L |
6561 | { |
6562 | /* We remove the first xmm0 and keep the number of | |
6563 | operands unchanged, which in fact duplicates the | |
6564 | destination. */ | |
6565 | for (j = 1; j < i.operands; j++) | |
6566 | { | |
6567 | i.op[j - 1] = i.op[j]; | |
6568 | i.types[j - 1] = i.types[j]; | |
6569 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
6570 | } | |
6571 | } | |
6572 | } | |
6573 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6574 | { |
91d6fa6a | 6575 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6576 | && (i.tm.opcode_modifier.vexsources |
6577 | == VEX3SOURCES)); | |
c0f3af97 L |
6578 | |
6579 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6580 | and 3 sources. */ | |
6581 | for (j = i.operands; j > 0; j--) | |
6582 | { | |
6583 | i.op[j] = i.op[j - 1]; | |
6584 | i.types[j] = i.types[j - 1]; | |
6585 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
6586 | } | |
6587 | i.op[0].regs | |
6588 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6589 | i.types[0] = regxmm; |
c0f3af97 L |
6590 | i.tm.operand_types[0] = regxmm; |
6591 | ||
6592 | i.operands += 2; | |
6593 | i.reg_operands += 2; | |
6594 | i.tm.operands += 2; | |
6595 | ||
91d6fa6a | 6596 | dupl++; |
c0f3af97 | 6597 | dest++; |
91d6fa6a NC |
6598 | i.op[dupl] = i.op[dest]; |
6599 | i.types[dupl] = i.types[dest]; | |
6600 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 6601 | } |
c0f3af97 L |
6602 | else |
6603 | { | |
6604 | duplicate: | |
6605 | i.operands++; | |
6606 | i.reg_operands++; | |
6607 | i.tm.operands++; | |
6608 | ||
91d6fa6a NC |
6609 | i.op[dupl] = i.op[dest]; |
6610 | i.types[dupl] = i.types[dest]; | |
6611 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
6612 | } |
6613 | ||
6614 | if (i.tm.opcode_modifier.immext) | |
6615 | process_immext (); | |
6616 | } | |
1b54b8d7 JB |
6617 | else if (i.tm.operand_types[0].bitfield.acc |
6618 | && i.tm.operand_types[0].bitfield.xmmword) | |
c0f3af97 L |
6619 | { |
6620 | unsigned int j; | |
6621 | ||
9fcfb3d7 L |
6622 | for (j = 1; j < i.operands; j++) |
6623 | { | |
6624 | i.op[j - 1] = i.op[j]; | |
6625 | i.types[j - 1] = i.types[j]; | |
6626 | ||
6627 | /* We need to adjust fields in i.tm since they are used by | |
6628 | build_modrm_byte. */ | |
6629 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
6630 | } | |
6631 | ||
e2ec9d29 L |
6632 | i.operands--; |
6633 | i.reg_operands--; | |
e2ec9d29 L |
6634 | i.tm.operands--; |
6635 | } | |
920d2ddc IT |
6636 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6637 | { | |
a477a8c4 JB |
6638 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
6639 | ||
920d2ddc | 6640 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
10c17abd | 6641 | gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); |
a477a8c4 JB |
6642 | regnum = register_number (i.op[1].regs); |
6643 | first_reg_in_group = regnum & ~3; | |
6644 | last_reg_in_group = first_reg_in_group + 3; | |
6645 | if (regnum != first_reg_in_group) | |
6646 | as_warn (_("source register `%s%s' implicitly denotes" | |
6647 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
6648 | register_prefix, i.op[1].regs->reg_name, | |
6649 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6650 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6651 | i.tm.name); | |
6652 | } | |
e2ec9d29 L |
6653 | else if (i.tm.opcode_modifier.regkludge) |
6654 | { | |
6655 | /* The imul $imm, %reg instruction is converted into | |
6656 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6657 | is converted into xor %reg, %reg. */ | |
6658 | ||
6659 | unsigned int first_reg_op; | |
6660 | ||
6661 | if (operand_type_check (i.types[0], reg)) | |
6662 | first_reg_op = 0; | |
6663 | else | |
6664 | first_reg_op = 1; | |
6665 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6666 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6667 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6668 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6669 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6670 | i.operands++; | |
6671 | i.reg_operands++; | |
29b0f896 AM |
6672 | } |
6673 | ||
40fb9820 | 6674 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6675 | { |
40fb9820 L |
6676 | if (i.types[0].bitfield.sreg2 |
6677 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6678 | { |
4eed87de AM |
6679 | if (i.tm.base_opcode == POP_SEG_SHORT |
6680 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6681 | { |
a87af027 | 6682 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6683 | return 0; |
29b0f896 | 6684 | } |
4eed87de AM |
6685 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6686 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6687 | i.rex |= REX_B; |
4eed87de AM |
6688 | } |
6689 | else | |
6690 | { | |
7ab9ffdd | 6691 | /* The register or float register operand is in operand |
85f10a01 | 6692 | 0 or 1. */ |
40fb9820 | 6693 | unsigned int op; |
7ab9ffdd | 6694 | |
ca0d63fe | 6695 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte) |
7ab9ffdd L |
6696 | || operand_type_check (i.types[0], reg)) |
6697 | op = 0; | |
6698 | else | |
6699 | op = 1; | |
4eed87de AM |
6700 | /* Register goes in low 3 bits of opcode. */ |
6701 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6702 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6703 | i.rex |= REX_B; |
40fb9820 | 6704 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6705 | { |
4eed87de AM |
6706 | /* Warn about some common errors, but press on regardless. |
6707 | The first case can be generated by gcc (<= 2.8.1). */ | |
6708 | if (i.operands == 2) | |
6709 | { | |
6710 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6711 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6712 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6713 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6714 | } |
6715 | else | |
6716 | { | |
6717 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6718 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6719 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6720 | } |
29b0f896 AM |
6721 | } |
6722 | } | |
6723 | } | |
40fb9820 | 6724 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6725 | { |
6726 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6727 | must be put into the modrm byte). Now, we make the modrm and |
6728 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6729 | |
6730 | default_seg = build_modrm_byte (); | |
6731 | } | |
8a2ed489 | 6732 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6733 | { |
6734 | default_seg = &ds; | |
6735 | } | |
40fb9820 | 6736 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6737 | { |
6738 | /* For the string instructions that allow a segment override | |
6739 | on one of their operands, the default segment is ds. */ | |
6740 | default_seg = &ds; | |
6741 | } | |
6742 | ||
75178d9d L |
6743 | if (i.tm.base_opcode == 0x8d /* lea */ |
6744 | && i.seg[0] | |
6745 | && !quiet_warnings) | |
30123838 | 6746 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6747 | |
6748 | /* If a segment was explicitly specified, and the specified segment | |
6749 | is not the default, use an opcode prefix to select it. If we | |
6750 | never figured out what the default segment is, then default_seg | |
6751 | will be zero at this point, and the specified segment prefix will | |
6752 | always be used. */ | |
29b0f896 AM |
6753 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6754 | { | |
6755 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6756 | return 0; | |
6757 | } | |
6758 | return 1; | |
6759 | } | |
6760 | ||
6761 | static const seg_entry * | |
e3bb37b5 | 6762 | build_modrm_byte (void) |
29b0f896 AM |
6763 | { |
6764 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6765 | unsigned int source, dest; |
8cd7925b | 6766 | int vex_3_sources; |
c0f3af97 | 6767 | |
8cd7925b | 6768 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6769 | if (vex_3_sources) |
6770 | { | |
91d6fa6a | 6771 | unsigned int nds, reg_slot; |
4c2c6516 | 6772 | expressionS *exp; |
c0f3af97 | 6773 | |
6b8d3588 | 6774 | dest = i.operands - 1; |
c0f3af97 | 6775 | nds = dest - 1; |
922d8de8 | 6776 | |
a683cc34 | 6777 | /* There are 2 kinds of instructions: |
bed3d976 JB |
6778 | 1. 5 operands: 4 register operands or 3 register operands |
6779 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
6780 | VexW0 or VexW1. The destination must be either XMM, YMM or | |
43234a1e | 6781 | ZMM register. |
bed3d976 | 6782 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 6783 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 6784 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
6785 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
6786 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 JB |
6787 | && i.tm.opcode_modifier.vexw |
6788 | && i.tm.operand_types[dest].bitfield.regsimd); | |
a683cc34 | 6789 | |
48db9223 JB |
6790 | /* If VexW1 is set, the first non-immediate operand is the source and |
6791 | the second non-immediate one is encoded in the immediate operand. */ | |
6792 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
6793 | { | |
6794 | source = i.imm_operands; | |
6795 | reg_slot = i.imm_operands + 1; | |
6796 | } | |
6797 | else | |
6798 | { | |
6799 | source = i.imm_operands + 1; | |
6800 | reg_slot = i.imm_operands; | |
6801 | } | |
6802 | ||
a683cc34 | 6803 | if (i.imm_operands == 0) |
bed3d976 JB |
6804 | { |
6805 | /* When there is no immediate operand, generate an 8bit | |
6806 | immediate operand to encode the first operand. */ | |
6807 | exp = &im_expressions[i.imm_operands++]; | |
6808 | i.op[i.operands].imms = exp; | |
6809 | i.types[i.operands] = imm8; | |
6810 | i.operands++; | |
6811 | ||
6812 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); | |
6813 | exp->X_op = O_constant; | |
6814 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
6815 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
6816 | } | |
922d8de8 | 6817 | else |
bed3d976 JB |
6818 | { |
6819 | unsigned int imm_slot; | |
a683cc34 | 6820 | |
2f1bada2 JB |
6821 | gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4); |
6822 | ||
bed3d976 JB |
6823 | if (i.tm.opcode_modifier.immext) |
6824 | { | |
6825 | /* When ImmExt is set, the immediate byte is the last | |
6826 | operand. */ | |
6827 | imm_slot = i.operands - 1; | |
6828 | source--; | |
6829 | reg_slot--; | |
6830 | } | |
6831 | else | |
6832 | { | |
6833 | imm_slot = 0; | |
6834 | ||
6835 | /* Turn on Imm8 so that output_imm will generate it. */ | |
6836 | i.types[imm_slot].bitfield.imm8 = 1; | |
6837 | } | |
6838 | ||
6839 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); | |
6840 | i.op[imm_slot].imms->X_add_number | |
6841 | |= register_number (i.op[reg_slot].regs) << 4; | |
43234a1e | 6842 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 6843 | } |
a683cc34 | 6844 | |
10c17abd | 6845 | gas_assert (i.tm.operand_types[nds].bitfield.regsimd); |
dae39acc | 6846 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
6847 | } |
6848 | else | |
6849 | source = dest = 0; | |
29b0f896 AM |
6850 | |
6851 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
6852 | implicit registers do not count. If there are 3 register |
6853 | operands, it must be a instruction with VexNDS. For a | |
6854 | instruction with VexNDD, the destination register is encoded | |
6855 | in VEX prefix. If there are 4 register operands, it must be | |
6856 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
6857 | if (i.mem_operands == 0 |
6858 | && ((i.reg_operands == 2 | |
2426c15f | 6859 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 6860 | || (i.reg_operands == 3 |
2426c15f | 6861 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 6862 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 6863 | { |
cab737b9 L |
6864 | switch (i.operands) |
6865 | { | |
6866 | case 2: | |
6867 | source = 0; | |
6868 | break; | |
6869 | case 3: | |
c81128dc L |
6870 | /* When there are 3 operands, one of them may be immediate, |
6871 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
6872 | the first operand must be shift count register (cl) or it |
6873 | is an instruction with VexNDS. */ | |
9c2799c2 | 6874 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 6875 | || (i.imm_operands == 0 |
2426c15f | 6876 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 6877 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
6878 | if (operand_type_check (i.types[0], imm) |
6879 | || i.types[0].bitfield.shiftcount) | |
6880 | source = 1; | |
6881 | else | |
6882 | source = 0; | |
cab737b9 L |
6883 | break; |
6884 | case 4: | |
368d64cc L |
6885 | /* When there are 4 operands, the first two must be 8bit |
6886 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
6887 | one. |
6888 | ||
6889 | For instructions with VexNDS, if the first operand | |
6890 | an imm8, the source operand is the 2nd one. If the last | |
6891 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 6892 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
6893 | && i.types[0].bitfield.imm8 |
6894 | && i.types[1].bitfield.imm8) | |
2426c15f | 6895 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
6896 | && i.imm_operands == 1 |
6897 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
6898 | || i.types[i.operands - 1].bitfield.imm8 |
6899 | || i.rounding))); | |
9f2670f2 L |
6900 | if (i.imm_operands == 2) |
6901 | source = 2; | |
6902 | else | |
c0f3af97 L |
6903 | { |
6904 | if (i.types[0].bitfield.imm8) | |
6905 | source = 1; | |
6906 | else | |
6907 | source = 0; | |
6908 | } | |
c0f3af97 L |
6909 | break; |
6910 | case 5: | |
e771e7c9 | 6911 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
6912 | { |
6913 | /* For EVEX instructions, when there are 5 operands, the | |
6914 | first one must be immediate operand. If the second one | |
6915 | is immediate operand, the source operand is the 3th | |
6916 | one. If the last one is immediate operand, the source | |
6917 | operand is the 2nd one. */ | |
6918 | gas_assert (i.imm_operands == 2 | |
6919 | && i.tm.opcode_modifier.sae | |
6920 | && operand_type_check (i.types[0], imm)); | |
6921 | if (operand_type_check (i.types[1], imm)) | |
6922 | source = 2; | |
6923 | else if (operand_type_check (i.types[4], imm)) | |
6924 | source = 1; | |
6925 | else | |
6926 | abort (); | |
6927 | } | |
cab737b9 L |
6928 | break; |
6929 | default: | |
6930 | abort (); | |
6931 | } | |
6932 | ||
c0f3af97 L |
6933 | if (!vex_3_sources) |
6934 | { | |
6935 | dest = source + 1; | |
6936 | ||
43234a1e L |
6937 | /* RC/SAE operand could be between DEST and SRC. That happens |
6938 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
6939 | register. */ | |
6940 | if (i.rounding && i.rounding->operand == (int) dest) | |
6941 | dest++; | |
6942 | ||
2426c15f | 6943 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 6944 | { |
43234a1e | 6945 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 6946 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
43234a1e L |
6947 | register. It is encoded in VEX prefix. We need to |
6948 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
6949 | |
6950 | i386_operand_type op; | |
6951 | unsigned int vvvv; | |
6952 | ||
6953 | /* Check register-only source operand when two source | |
6954 | operands are swapped. */ | |
6955 | if (!i.tm.operand_types[source].bitfield.baseindex | |
6956 | && i.tm.operand_types[dest].bitfield.baseindex) | |
6957 | { | |
6958 | vvvv = source; | |
6959 | source = dest; | |
6960 | } | |
6961 | else | |
6962 | vvvv = dest; | |
6963 | ||
6964 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 6965 | op.bitfield.regmem = 0; |
c0f3af97 | 6966 | if ((dest + 1) >= i.operands |
dc821c5f JB |
6967 | || ((!op.bitfield.reg |
6968 | || (!op.bitfield.dword && !op.bitfield.qword)) | |
10c17abd | 6969 | && !op.bitfield.regsimd |
43234a1e | 6970 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 6971 | abort (); |
f12dc422 | 6972 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
6973 | dest++; |
6974 | } | |
6975 | } | |
29b0f896 AM |
6976 | |
6977 | i.rm.mode = 3; | |
6978 | /* One of the register operands will be encoded in the i.tm.reg | |
6979 | field, the other in the combined i.tm.mode and i.tm.regmem | |
6980 | fields. If no form of this instruction supports a memory | |
6981 | destination operand, then we assume the source operand may | |
6982 | sometimes be a memory operand and so we need to store the | |
6983 | destination in the i.rm.reg field. */ | |
40fb9820 L |
6984 | if (!i.tm.operand_types[dest].bitfield.regmem |
6985 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
6986 | { |
6987 | i.rm.reg = i.op[dest].regs->reg_num; | |
6988 | i.rm.regmem = i.op[source].regs->reg_num; | |
6989 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6990 | i.rex |= REX_R; |
43234a1e L |
6991 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6992 | i.vrex |= REX_R; | |
29b0f896 | 6993 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6994 | i.rex |= REX_B; |
43234a1e L |
6995 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6996 | i.vrex |= REX_B; | |
29b0f896 AM |
6997 | } |
6998 | else | |
6999 | { | |
7000 | i.rm.reg = i.op[source].regs->reg_num; | |
7001 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7002 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7003 | i.rex |= REX_B; |
43234a1e L |
7004 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7005 | i.vrex |= REX_B; | |
29b0f896 | 7006 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7007 | i.rex |= REX_R; |
43234a1e L |
7008 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7009 | i.vrex |= REX_R; | |
29b0f896 | 7010 | } |
e0c7f900 | 7011 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7012 | { |
e0c7f900 | 7013 | if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control) |
c4a530c5 | 7014 | abort (); |
e0c7f900 | 7015 | i.rex &= ~REX_R; |
c4a530c5 JB |
7016 | add_prefix (LOCK_PREFIX_OPCODE); |
7017 | } | |
29b0f896 AM |
7018 | } |
7019 | else | |
7020 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7021 | unsigned int mem; |
7022 | ||
29b0f896 AM |
7023 | if (i.mem_operands) |
7024 | { | |
7025 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7026 | unsigned int op; |
4eed87de | 7027 | |
7ab9ffdd L |
7028 | for (op = 0; op < i.operands; op++) |
7029 | if (operand_type_check (i.types[op], anymem)) | |
7030 | break; | |
7ab9ffdd | 7031 | gas_assert (op < i.operands); |
29b0f896 | 7032 | |
6c30d220 L |
7033 | if (i.tm.opcode_modifier.vecsib) |
7034 | { | |
7035 | if (i.index_reg->reg_num == RegEiz | |
7036 | || i.index_reg->reg_num == RegRiz) | |
7037 | abort (); | |
7038 | ||
7039 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7040 | if (!i.base_reg) | |
7041 | { | |
7042 | i.sib.base = NO_BASE_REGISTER; | |
7043 | i.sib.scale = i.log2_scale_factor; | |
7044 | i.types[op].bitfield.disp8 = 0; | |
7045 | i.types[op].bitfield.disp16 = 0; | |
7046 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7047 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7048 | { |
7049 | /* Must be 32 bit */ | |
7050 | i.types[op].bitfield.disp32 = 1; | |
7051 | i.types[op].bitfield.disp32s = 0; | |
7052 | } | |
7053 | else | |
7054 | { | |
7055 | i.types[op].bitfield.disp32 = 0; | |
7056 | i.types[op].bitfield.disp32s = 1; | |
7057 | } | |
7058 | } | |
7059 | i.sib.index = i.index_reg->reg_num; | |
7060 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7061 | i.rex |= REX_X; | |
43234a1e L |
7062 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7063 | i.vrex |= REX_X; | |
6c30d220 L |
7064 | } |
7065 | ||
29b0f896 AM |
7066 | default_seg = &ds; |
7067 | ||
7068 | if (i.base_reg == 0) | |
7069 | { | |
7070 | i.rm.mode = 0; | |
7071 | if (!i.disp_operands) | |
9bb129e8 | 7072 | fake_zero_displacement = 1; |
29b0f896 AM |
7073 | if (i.index_reg == 0) |
7074 | { | |
73053c1f JB |
7075 | i386_operand_type newdisp; |
7076 | ||
6c30d220 | 7077 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7078 | /* Operand is just <disp> */ |
20f0a1fc | 7079 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7080 | { |
7081 | /* 64bit mode overwrites the 32bit absolute | |
7082 | addressing by RIP relative addressing and | |
7083 | absolute addressing is encoded by one of the | |
7084 | redundant SIB forms. */ | |
7085 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7086 | i.sib.base = NO_BASE_REGISTER; | |
7087 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7088 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7089 | } |
fc225355 L |
7090 | else if ((flag_code == CODE_16BIT) |
7091 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7092 | { |
7093 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7094 | newdisp = disp16; |
20f0a1fc NC |
7095 | } |
7096 | else | |
7097 | { | |
7098 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7099 | newdisp = disp32; |
29b0f896 | 7100 | } |
73053c1f JB |
7101 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7102 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7103 | } |
6c30d220 | 7104 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7105 | { |
6c30d220 | 7106 | /* !i.base_reg && i.index_reg */ |
db51cc60 L |
7107 | if (i.index_reg->reg_num == RegEiz |
7108 | || i.index_reg->reg_num == RegRiz) | |
7109 | i.sib.index = NO_INDEX_REGISTER; | |
7110 | else | |
7111 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7112 | i.sib.base = NO_BASE_REGISTER; |
7113 | i.sib.scale = i.log2_scale_factor; | |
7114 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7115 | i.types[op].bitfield.disp8 = 0; |
7116 | i.types[op].bitfield.disp16 = 0; | |
7117 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7118 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7119 | { |
7120 | /* Must be 32 bit */ | |
7121 | i.types[op].bitfield.disp32 = 1; | |
7122 | i.types[op].bitfield.disp32s = 0; | |
7123 | } | |
29b0f896 | 7124 | else |
40fb9820 L |
7125 | { |
7126 | i.types[op].bitfield.disp32 = 0; | |
7127 | i.types[op].bitfield.disp32s = 1; | |
7128 | } | |
29b0f896 | 7129 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7130 | i.rex |= REX_X; |
29b0f896 AM |
7131 | } |
7132 | } | |
7133 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
7134 | else if (i.base_reg->reg_num == RegRip || |
7135 | i.base_reg->reg_num == RegEip) | |
29b0f896 | 7136 | { |
6c30d220 | 7137 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7138 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7139 | i.types[op].bitfield.disp8 = 0; |
7140 | i.types[op].bitfield.disp16 = 0; | |
7141 | i.types[op].bitfield.disp32 = 0; | |
7142 | i.types[op].bitfield.disp32s = 1; | |
7143 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7144 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7145 | if (! i.disp_operands) |
7146 | fake_zero_displacement = 1; | |
29b0f896 | 7147 | } |
dc821c5f | 7148 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7149 | { |
6c30d220 | 7150 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7151 | switch (i.base_reg->reg_num) |
7152 | { | |
7153 | case 3: /* (%bx) */ | |
7154 | if (i.index_reg == 0) | |
7155 | i.rm.regmem = 7; | |
7156 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7157 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7158 | break; | |
7159 | case 5: /* (%bp) */ | |
7160 | default_seg = &ss; | |
7161 | if (i.index_reg == 0) | |
7162 | { | |
7163 | i.rm.regmem = 6; | |
40fb9820 | 7164 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7165 | { |
7166 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7167 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7168 | fake_zero_displacement = 1; |
29b0f896 AM |
7169 | } |
7170 | } | |
7171 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7172 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7173 | break; | |
7174 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7175 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7176 | } | |
7177 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7178 | } | |
7179 | else /* i.base_reg and 32/64 bit mode */ | |
7180 | { | |
7181 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7182 | && operand_type_check (i.types[op], disp)) |
7183 | { | |
73053c1f JB |
7184 | i.types[op].bitfield.disp16 = 0; |
7185 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7186 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7187 | { |
7188 | i.types[op].bitfield.disp32 = 0; | |
7189 | i.types[op].bitfield.disp32s = 1; | |
7190 | } | |
40fb9820 | 7191 | else |
73053c1f JB |
7192 | { |
7193 | i.types[op].bitfield.disp32 = 1; | |
7194 | i.types[op].bitfield.disp32s = 0; | |
7195 | } | |
40fb9820 | 7196 | } |
20f0a1fc | 7197 | |
6c30d220 L |
7198 | if (!i.tm.opcode_modifier.vecsib) |
7199 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7200 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7201 | i.rex |= REX_B; |
29b0f896 AM |
7202 | i.sib.base = i.base_reg->reg_num; |
7203 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7204 | complications. */ | |
848930b2 JB |
7205 | if (!(i.base_reg->reg_flags & RegRex) |
7206 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7207 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7208 | default_seg = &ss; |
848930b2 | 7209 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7210 | { |
848930b2 | 7211 | fake_zero_displacement = 1; |
b5014f7a | 7212 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7213 | } |
7214 | i.sib.scale = i.log2_scale_factor; | |
7215 | if (i.index_reg == 0) | |
7216 | { | |
6c30d220 | 7217 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7218 | /* <disp>(%esp) becomes two byte modrm with no index |
7219 | register. We've already stored the code for esp | |
7220 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7221 | Any base register besides %esp will not use the | |
7222 | extra modrm byte. */ | |
7223 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7224 | } |
6c30d220 | 7225 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7226 | { |
db51cc60 L |
7227 | if (i.index_reg->reg_num == RegEiz |
7228 | || i.index_reg->reg_num == RegRiz) | |
7229 | i.sib.index = NO_INDEX_REGISTER; | |
7230 | else | |
7231 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7232 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7233 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7234 | i.rex |= REX_X; |
29b0f896 | 7235 | } |
67a4f2b7 AO |
7236 | |
7237 | if (i.disp_operands | |
7238 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7239 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7240 | i.rm.mode = 0; | |
7241 | else | |
a501d77e L |
7242 | { |
7243 | if (!fake_zero_displacement | |
7244 | && !i.disp_operands | |
7245 | && i.disp_encoding) | |
7246 | { | |
7247 | fake_zero_displacement = 1; | |
7248 | if (i.disp_encoding == disp_encoding_8bit) | |
7249 | i.types[op].bitfield.disp8 = 1; | |
7250 | else | |
7251 | i.types[op].bitfield.disp32 = 1; | |
7252 | } | |
7253 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7254 | } | |
29b0f896 | 7255 | } |
252b5132 | 7256 | |
29b0f896 AM |
7257 | if (fake_zero_displacement) |
7258 | { | |
7259 | /* Fakes a zero displacement assuming that i.types[op] | |
7260 | holds the correct displacement size. */ | |
7261 | expressionS *exp; | |
7262 | ||
9c2799c2 | 7263 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7264 | exp = &disp_expressions[i.disp_operands++]; |
7265 | i.op[op].disps = exp; | |
7266 | exp->X_op = O_constant; | |
7267 | exp->X_add_number = 0; | |
7268 | exp->X_add_symbol = (symbolS *) 0; | |
7269 | exp->X_op_symbol = (symbolS *) 0; | |
7270 | } | |
c0f3af97 L |
7271 | |
7272 | mem = op; | |
29b0f896 | 7273 | } |
c0f3af97 L |
7274 | else |
7275 | mem = ~0; | |
252b5132 | 7276 | |
8c43a48b | 7277 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7278 | { |
7279 | if (operand_type_check (i.types[0], imm)) | |
7280 | i.vex.register_specifier = NULL; | |
7281 | else | |
7282 | { | |
7283 | /* VEX.vvvv encodes one of the sources when the first | |
7284 | operand is not an immediate. */ | |
1ef99a7b | 7285 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7286 | i.vex.register_specifier = i.op[0].regs; |
7287 | else | |
7288 | i.vex.register_specifier = i.op[1].regs; | |
7289 | } | |
7290 | ||
7291 | /* Destination is a XMM register encoded in the ModRM.reg | |
7292 | and VEX.R bit. */ | |
7293 | i.rm.reg = i.op[2].regs->reg_num; | |
7294 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7295 | i.rex |= REX_R; | |
7296 | ||
7297 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7298 | if (!i.mem_operands) | |
7299 | { | |
7300 | i.rm.mode = 3; | |
7301 | ||
1ef99a7b | 7302 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7303 | i.rm.regmem = i.op[1].regs->reg_num; |
7304 | else | |
7305 | i.rm.regmem = i.op[0].regs->reg_num; | |
7306 | ||
7307 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7308 | i.rex |= REX_B; | |
7309 | } | |
7310 | } | |
2426c15f | 7311 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7312 | { |
7313 | i.vex.register_specifier = i.op[2].regs; | |
7314 | if (!i.mem_operands) | |
7315 | { | |
7316 | i.rm.mode = 3; | |
7317 | i.rm.regmem = i.op[1].regs->reg_num; | |
7318 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7319 | i.rex |= REX_B; | |
7320 | } | |
7321 | } | |
29b0f896 AM |
7322 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7323 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7324 | careful to make sure that segment/control/debug/test/MMX | |
7325 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7326 | else if (i.reg_operands) |
29b0f896 | 7327 | { |
99018f42 | 7328 | unsigned int op; |
7ab9ffdd L |
7329 | unsigned int vex_reg = ~0; |
7330 | ||
7331 | for (op = 0; op < i.operands; op++) | |
dc821c5f | 7332 | if (i.types[op].bitfield.reg |
7ab9ffdd | 7333 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 7334 | || i.types[op].bitfield.regsimd |
7e8b059b | 7335 | || i.types[op].bitfield.regbnd |
43234a1e | 7336 | || i.types[op].bitfield.regmask |
7ab9ffdd L |
7337 | || i.types[op].bitfield.sreg2 |
7338 | || i.types[op].bitfield.sreg3 | |
7339 | || i.types[op].bitfield.control | |
7340 | || i.types[op].bitfield.debug | |
7341 | || i.types[op].bitfield.test) | |
7342 | break; | |
c0209578 | 7343 | |
7ab9ffdd L |
7344 | if (vex_3_sources) |
7345 | op = dest; | |
2426c15f | 7346 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7347 | { |
7348 | /* For instructions with VexNDS, the register-only | |
7349 | source operand is encoded in VEX prefix. */ | |
7350 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7351 | |
7ab9ffdd | 7352 | if (op > mem) |
c0f3af97 | 7353 | { |
7ab9ffdd L |
7354 | vex_reg = op++; |
7355 | gas_assert (op < i.operands); | |
c0f3af97 L |
7356 | } |
7357 | else | |
c0f3af97 | 7358 | { |
f12dc422 L |
7359 | /* Check register-only source operand when two source |
7360 | operands are swapped. */ | |
7361 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7362 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7363 | { | |
7364 | vex_reg = op; | |
7365 | op += 2; | |
7366 | gas_assert (mem == (vex_reg + 1) | |
7367 | && op < i.operands); | |
7368 | } | |
7369 | else | |
7370 | { | |
7371 | vex_reg = op + 1; | |
7372 | gas_assert (vex_reg < i.operands); | |
7373 | } | |
c0f3af97 | 7374 | } |
7ab9ffdd | 7375 | } |
2426c15f | 7376 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7377 | { |
f12dc422 | 7378 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7379 | is encoded in VEX prefix. */ |
f12dc422 L |
7380 | if (i.mem_operands == 0) |
7381 | { | |
7382 | /* There is no memory operand. */ | |
7383 | gas_assert ((op + 2) == i.operands); | |
7384 | vex_reg = op + 1; | |
7385 | } | |
7386 | else | |
8d63c93e | 7387 | { |
ed438a93 JB |
7388 | /* There are only 2 non-immediate operands. */ |
7389 | gas_assert (op < i.imm_operands + 2 | |
7390 | && i.operands == i.imm_operands + 2); | |
7391 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7392 | } |
7ab9ffdd L |
7393 | } |
7394 | else | |
7395 | gas_assert (op < i.operands); | |
99018f42 | 7396 | |
7ab9ffdd L |
7397 | if (vex_reg != (unsigned int) ~0) |
7398 | { | |
f12dc422 | 7399 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7400 | |
dc821c5f JB |
7401 | if ((!type->bitfield.reg |
7402 | || (!type->bitfield.dword && !type->bitfield.qword)) | |
10c17abd | 7403 | && !type->bitfield.regsimd |
43234a1e | 7404 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7405 | abort (); |
f88c9eb0 | 7406 | |
7ab9ffdd L |
7407 | i.vex.register_specifier = i.op[vex_reg].regs; |
7408 | } | |
7409 | ||
1b9f0c97 L |
7410 | /* Don't set OP operand twice. */ |
7411 | if (vex_reg != op) | |
7ab9ffdd | 7412 | { |
1b9f0c97 L |
7413 | /* If there is an extension opcode to put here, the |
7414 | register number must be put into the regmem field. */ | |
7415 | if (i.tm.extension_opcode != None) | |
7416 | { | |
7417 | i.rm.regmem = i.op[op].regs->reg_num; | |
7418 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7419 | i.rex |= REX_B; | |
43234a1e L |
7420 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7421 | i.vrex |= REX_B; | |
1b9f0c97 L |
7422 | } |
7423 | else | |
7424 | { | |
7425 | i.rm.reg = i.op[op].regs->reg_num; | |
7426 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7427 | i.rex |= REX_R; | |
43234a1e L |
7428 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7429 | i.vrex |= REX_R; | |
1b9f0c97 | 7430 | } |
7ab9ffdd | 7431 | } |
252b5132 | 7432 | |
29b0f896 AM |
7433 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7434 | must set it to 3 to indicate this is a register operand | |
7435 | in the regmem field. */ | |
7436 | if (!i.mem_operands) | |
7437 | i.rm.mode = 3; | |
7438 | } | |
252b5132 | 7439 | |
29b0f896 | 7440 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7441 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7442 | i.rm.reg = i.tm.extension_opcode; |
7443 | } | |
7444 | return default_seg; | |
7445 | } | |
252b5132 | 7446 | |
29b0f896 | 7447 | static void |
e3bb37b5 | 7448 | output_branch (void) |
29b0f896 AM |
7449 | { |
7450 | char *p; | |
f8a5c266 | 7451 | int size; |
29b0f896 AM |
7452 | int code16; |
7453 | int prefix; | |
7454 | relax_substateT subtype; | |
7455 | symbolS *sym; | |
7456 | offsetT off; | |
7457 | ||
f8a5c266 | 7458 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7459 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7460 | |
7461 | prefix = 0; | |
7462 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7463 | { |
29b0f896 AM |
7464 | prefix = 1; |
7465 | i.prefixes -= 1; | |
7466 | code16 ^= CODE16; | |
252b5132 | 7467 | } |
29b0f896 AM |
7468 | /* Pentium4 branch hints. */ |
7469 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7470 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7471 | { |
29b0f896 AM |
7472 | prefix++; |
7473 | i.prefixes--; | |
7474 | } | |
7475 | if (i.prefix[REX_PREFIX] != 0) | |
7476 | { | |
7477 | prefix++; | |
7478 | i.prefixes--; | |
2f66722d AM |
7479 | } |
7480 | ||
7e8b059b L |
7481 | /* BND prefixed jump. */ |
7482 | if (i.prefix[BND_PREFIX] != 0) | |
7483 | { | |
7484 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7485 | i.prefixes -= 1; | |
7486 | } | |
7487 | ||
29b0f896 AM |
7488 | if (i.prefixes != 0 && !intel_syntax) |
7489 | as_warn (_("skipping prefixes on this instruction")); | |
7490 | ||
7491 | /* It's always a symbol; End frag & setup for relax. | |
7492 | Make sure there is enough room in this frag for the largest | |
7493 | instruction we may generate in md_convert_frag. This is 2 | |
7494 | bytes for the opcode and room for the prefix and largest | |
7495 | displacement. */ | |
7496 | frag_grow (prefix + 2 + 4); | |
7497 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7498 | p = frag_more (prefix + 1); | |
7499 | if (i.prefix[DATA_PREFIX] != 0) | |
7500 | *p++ = DATA_PREFIX_OPCODE; | |
7501 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7502 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7503 | *p++ = i.prefix[SEG_PREFIX]; | |
7504 | if (i.prefix[REX_PREFIX] != 0) | |
7505 | *p++ = i.prefix[REX_PREFIX]; | |
7506 | *p = i.tm.base_opcode; | |
7507 | ||
7508 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7509 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7510 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7511 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7512 | else |
f8a5c266 | 7513 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7514 | subtype |= code16; |
3e73aa7c | 7515 | |
29b0f896 AM |
7516 | sym = i.op[0].disps->X_add_symbol; |
7517 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7518 | |
29b0f896 AM |
7519 | if (i.op[0].disps->X_op != O_constant |
7520 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7521 | { |
29b0f896 AM |
7522 | /* Handle complex expressions. */ |
7523 | sym = make_expr_symbol (i.op[0].disps); | |
7524 | off = 0; | |
7525 | } | |
3e73aa7c | 7526 | |
29b0f896 AM |
7527 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7528 | Pass reloc in fr_var. */ | |
d258b828 | 7529 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7530 | } |
3e73aa7c | 7531 | |
bd7ab16b L |
7532 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7533 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7534 | symbol S. */ | |
7535 | ||
7536 | static bfd_boolean | |
7537 | need_plt32_p (symbolS *s) | |
7538 | { | |
7539 | /* PLT32 relocation is ELF only. */ | |
7540 | if (!IS_ELF) | |
7541 | return FALSE; | |
7542 | ||
7543 | /* Since there is no need to prepare for PLT branch on x86-64, we | |
7544 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7545 | be used as a marker for 32-bit PC-relative branches. */ | |
7546 | if (!object_64bit) | |
7547 | return FALSE; | |
7548 | ||
7549 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7550 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7551 | return TRUE; | |
7552 | ||
7553 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7554 | if (! S_IS_EXTERNAL (s)) | |
7555 | return FALSE; | |
7556 | ||
7557 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7558 | non-default visibilities are treated as normal global symbol | |
7559 | so that PLT32 relocation can be used as a marker for 32-bit | |
7560 | PC-relative branches. It is useful for linker relaxation. */ | |
7561 | return TRUE; | |
7562 | } | |
7563 | #endif | |
7564 | ||
29b0f896 | 7565 | static void |
e3bb37b5 | 7566 | output_jump (void) |
29b0f896 AM |
7567 | { |
7568 | char *p; | |
7569 | int size; | |
3e02c1cc | 7570 | fixS *fixP; |
bd7ab16b | 7571 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 7572 | |
40fb9820 | 7573 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7574 | { |
7575 | /* This is a loop or jecxz type instruction. */ | |
7576 | size = 1; | |
7577 | if (i.prefix[ADDR_PREFIX] != 0) | |
7578 | { | |
7579 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7580 | i.prefixes -= 1; | |
7581 | } | |
7582 | /* Pentium4 branch hints. */ | |
7583 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7584 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7585 | { | |
7586 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7587 | i.prefixes--; | |
3e73aa7c JH |
7588 | } |
7589 | } | |
29b0f896 AM |
7590 | else |
7591 | { | |
7592 | int code16; | |
3e73aa7c | 7593 | |
29b0f896 AM |
7594 | code16 = 0; |
7595 | if (flag_code == CODE_16BIT) | |
7596 | code16 = CODE16; | |
3e73aa7c | 7597 | |
29b0f896 AM |
7598 | if (i.prefix[DATA_PREFIX] != 0) |
7599 | { | |
7600 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7601 | i.prefixes -= 1; | |
7602 | code16 ^= CODE16; | |
7603 | } | |
252b5132 | 7604 | |
29b0f896 AM |
7605 | size = 4; |
7606 | if (code16) | |
7607 | size = 2; | |
7608 | } | |
9fcc94b6 | 7609 | |
29b0f896 AM |
7610 | if (i.prefix[REX_PREFIX] != 0) |
7611 | { | |
7612 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7613 | i.prefixes -= 1; | |
7614 | } | |
252b5132 | 7615 | |
7e8b059b L |
7616 | /* BND prefixed jump. */ |
7617 | if (i.prefix[BND_PREFIX] != 0) | |
7618 | { | |
7619 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7620 | i.prefixes -= 1; | |
7621 | } | |
7622 | ||
29b0f896 AM |
7623 | if (i.prefixes != 0 && !intel_syntax) |
7624 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7625 | |
42164a71 L |
7626 | p = frag_more (i.tm.opcode_length + size); |
7627 | switch (i.tm.opcode_length) | |
7628 | { | |
7629 | case 2: | |
7630 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7631 | /* Fall through. */ |
42164a71 L |
7632 | case 1: |
7633 | *p++ = i.tm.base_opcode; | |
7634 | break; | |
7635 | default: | |
7636 | abort (); | |
7637 | } | |
e0890092 | 7638 | |
bd7ab16b L |
7639 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7640 | if (size == 4 | |
7641 | && jump_reloc == NO_RELOC | |
7642 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
7643 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
7644 | #endif | |
7645 | ||
7646 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
7647 | ||
3e02c1cc | 7648 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 7649 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
7650 | |
7651 | /* All jumps handled here are signed, but don't use a signed limit | |
7652 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7653 | 4G and 64k respectively. */ | |
7654 | if (size == 1) | |
7655 | fixP->fx_signed = 1; | |
29b0f896 | 7656 | } |
e0890092 | 7657 | |
29b0f896 | 7658 | static void |
e3bb37b5 | 7659 | output_interseg_jump (void) |
29b0f896 AM |
7660 | { |
7661 | char *p; | |
7662 | int size; | |
7663 | int prefix; | |
7664 | int code16; | |
252b5132 | 7665 | |
29b0f896 AM |
7666 | code16 = 0; |
7667 | if (flag_code == CODE_16BIT) | |
7668 | code16 = CODE16; | |
a217f122 | 7669 | |
29b0f896 AM |
7670 | prefix = 0; |
7671 | if (i.prefix[DATA_PREFIX] != 0) | |
7672 | { | |
7673 | prefix = 1; | |
7674 | i.prefixes -= 1; | |
7675 | code16 ^= CODE16; | |
7676 | } | |
7677 | if (i.prefix[REX_PREFIX] != 0) | |
7678 | { | |
7679 | prefix++; | |
7680 | i.prefixes -= 1; | |
7681 | } | |
252b5132 | 7682 | |
29b0f896 AM |
7683 | size = 4; |
7684 | if (code16) | |
7685 | size = 2; | |
252b5132 | 7686 | |
29b0f896 AM |
7687 | if (i.prefixes != 0 && !intel_syntax) |
7688 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7689 | |
29b0f896 AM |
7690 | /* 1 opcode; 2 segment; offset */ |
7691 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7692 | |
29b0f896 AM |
7693 | if (i.prefix[DATA_PREFIX] != 0) |
7694 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7695 | |
29b0f896 AM |
7696 | if (i.prefix[REX_PREFIX] != 0) |
7697 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7698 | |
29b0f896 AM |
7699 | *p++ = i.tm.base_opcode; |
7700 | if (i.op[1].imms->X_op == O_constant) | |
7701 | { | |
7702 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7703 | |
29b0f896 AM |
7704 | if (size == 2 |
7705 | && !fits_in_unsigned_word (n) | |
7706 | && !fits_in_signed_word (n)) | |
7707 | { | |
7708 | as_bad (_("16-bit jump out of range")); | |
7709 | return; | |
7710 | } | |
7711 | md_number_to_chars (p, n, size); | |
7712 | } | |
7713 | else | |
7714 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7715 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7716 | if (i.op[0].imms->X_op != O_constant) |
7717 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7718 | i.tm.name); | |
7719 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7720 | } | |
a217f122 | 7721 | |
29b0f896 | 7722 | static void |
e3bb37b5 | 7723 | output_insn (void) |
29b0f896 | 7724 | { |
2bbd9c25 JJ |
7725 | fragS *insn_start_frag; |
7726 | offsetT insn_start_off; | |
7727 | ||
29b0f896 AM |
7728 | /* Tie dwarf2 debug info to the address at the start of the insn. |
7729 | We can't do this after the insn has been output as the current | |
7730 | frag may have been closed off. eg. by frag_var. */ | |
7731 | dwarf2_emit_insn (0); | |
7732 | ||
2bbd9c25 JJ |
7733 | insn_start_frag = frag_now; |
7734 | insn_start_off = frag_now_fix (); | |
7735 | ||
29b0f896 | 7736 | /* Output jumps. */ |
40fb9820 | 7737 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 7738 | output_branch (); |
40fb9820 L |
7739 | else if (i.tm.opcode_modifier.jumpbyte |
7740 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 7741 | output_jump (); |
40fb9820 | 7742 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
7743 | output_interseg_jump (); |
7744 | else | |
7745 | { | |
7746 | /* Output normal instructions here. */ | |
7747 | char *p; | |
7748 | unsigned char *q; | |
47465058 | 7749 | unsigned int j; |
331d2d0d | 7750 | unsigned int prefix; |
4dffcebc | 7751 | |
e4e00185 AS |
7752 | if (avoid_fence |
7753 | && i.tm.base_opcode == 0xfae | |
7754 | && i.operands == 1 | |
7755 | && i.imm_operands == 1 | |
7756 | && (i.op[0].imms->X_add_number == 0xe8 | |
7757 | || i.op[0].imms->X_add_number == 0xf0 | |
7758 | || i.op[0].imms->X_add_number == 0xf8)) | |
7759 | { | |
7760 | /* Encode lfence, mfence, and sfence as | |
7761 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
7762 | offsetT val = 0x240483f0ULL; | |
7763 | p = frag_more (5); | |
7764 | md_number_to_chars (p, val, 5); | |
7765 | return; | |
7766 | } | |
7767 | ||
d022bddd IT |
7768 | /* Some processors fail on LOCK prefix. This options makes |
7769 | assembler ignore LOCK prefix and serves as a workaround. */ | |
7770 | if (omit_lock_prefix) | |
7771 | { | |
7772 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
7773 | return; | |
7774 | i.prefix[LOCK_PREFIX] = 0; | |
7775 | } | |
7776 | ||
43234a1e L |
7777 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
7778 | don't need the explicit prefix. */ | |
7779 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 7780 | { |
c0f3af97 | 7781 | switch (i.tm.opcode_length) |
bc4bd9ab | 7782 | { |
c0f3af97 L |
7783 | case 3: |
7784 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 7785 | { |
c0f3af97 | 7786 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
bd59a631 | 7787 | add_prefix (prefix); |
c0f3af97 L |
7788 | } |
7789 | break; | |
7790 | case 2: | |
7791 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
7792 | { | |
7793 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
bd59a631 JB |
7794 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
7795 | || prefix != REPE_PREFIX_OPCODE | |
7796 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
4dffcebc L |
7797 | add_prefix (prefix); |
7798 | } | |
c0f3af97 L |
7799 | break; |
7800 | case 1: | |
7801 | break; | |
390c91cf L |
7802 | case 0: |
7803 | /* Check for pseudo prefixes. */ | |
7804 | as_bad_where (insn_start_frag->fr_file, | |
7805 | insn_start_frag->fr_line, | |
7806 | _("pseudo prefix without instruction")); | |
7807 | return; | |
c0f3af97 L |
7808 | default: |
7809 | abort (); | |
bc4bd9ab | 7810 | } |
c0f3af97 | 7811 | |
6d19a37a | 7812 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
7813 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
7814 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
7815 | perform IE->LE optimization. */ | |
7816 | if (x86_elf_abi == X86_64_X32_ABI | |
7817 | && i.operands == 2 | |
7818 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
7819 | && i.prefix[REX_PREFIX] == 0) | |
7820 | add_prefix (REX_OPCODE); | |
6d19a37a | 7821 | #endif |
cf61b747 | 7822 | |
c0f3af97 L |
7823 | /* The prefix bytes. */ |
7824 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
7825 | if (*q) | |
7826 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 7827 | } |
ae5c1c7b | 7828 | else |
c0f3af97 L |
7829 | { |
7830 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
7831 | if (*q) | |
7832 | switch (j) | |
7833 | { | |
7834 | case REX_PREFIX: | |
7835 | /* REX byte is encoded in VEX prefix. */ | |
7836 | break; | |
7837 | case SEG_PREFIX: | |
7838 | case ADDR_PREFIX: | |
7839 | FRAG_APPEND_1_CHAR (*q); | |
7840 | break; | |
7841 | default: | |
7842 | /* There should be no other prefixes for instructions | |
7843 | with VEX prefix. */ | |
7844 | abort (); | |
7845 | } | |
7846 | ||
43234a1e L |
7847 | /* For EVEX instructions i.vrex should become 0 after |
7848 | build_evex_prefix. For VEX instructions upper 16 registers | |
7849 | aren't available, so VREX should be 0. */ | |
7850 | if (i.vrex) | |
7851 | abort (); | |
c0f3af97 L |
7852 | /* Now the VEX prefix. */ |
7853 | p = frag_more (i.vex.length); | |
7854 | for (j = 0; j < i.vex.length; j++) | |
7855 | p[j] = i.vex.bytes[j]; | |
7856 | } | |
252b5132 | 7857 | |
29b0f896 | 7858 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 7859 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
7860 | { |
7861 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
7862 | } | |
7863 | else | |
7864 | { | |
4dffcebc | 7865 | switch (i.tm.opcode_length) |
331d2d0d | 7866 | { |
43234a1e L |
7867 | case 4: |
7868 | p = frag_more (4); | |
7869 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
7870 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
7871 | break; | |
4dffcebc | 7872 | case 3: |
331d2d0d L |
7873 | p = frag_more (3); |
7874 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
7875 | break; |
7876 | case 2: | |
7877 | p = frag_more (2); | |
7878 | break; | |
7879 | default: | |
7880 | abort (); | |
7881 | break; | |
331d2d0d | 7882 | } |
0f10071e | 7883 | |
29b0f896 AM |
7884 | /* Put out high byte first: can't use md_number_to_chars! */ |
7885 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
7886 | *p = i.tm.base_opcode & 0xff; | |
7887 | } | |
3e73aa7c | 7888 | |
29b0f896 | 7889 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 7890 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 7891 | { |
4a3523fa L |
7892 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
7893 | | i.rm.reg << 3 | |
7894 | | i.rm.mode << 6)); | |
29b0f896 AM |
7895 | /* If i.rm.regmem == ESP (4) |
7896 | && i.rm.mode != (Register mode) | |
7897 | && not 16 bit | |
7898 | ==> need second modrm byte. */ | |
7899 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
7900 | && i.rm.mode != 3 | |
dc821c5f | 7901 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
7902 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
7903 | | i.sib.index << 3 | |
7904 | | i.sib.scale << 6)); | |
29b0f896 | 7905 | } |
3e73aa7c | 7906 | |
29b0f896 | 7907 | if (i.disp_operands) |
2bbd9c25 | 7908 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 7909 | |
29b0f896 | 7910 | if (i.imm_operands) |
2bbd9c25 | 7911 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 7912 | } |
252b5132 | 7913 | |
29b0f896 AM |
7914 | #ifdef DEBUG386 |
7915 | if (flag_debug) | |
7916 | { | |
7b81dfbb | 7917 | pi ("" /*line*/, &i); |
29b0f896 AM |
7918 | } |
7919 | #endif /* DEBUG386 */ | |
7920 | } | |
252b5132 | 7921 | |
e205caa7 L |
7922 | /* Return the size of the displacement operand N. */ |
7923 | ||
7924 | static int | |
7925 | disp_size (unsigned int n) | |
7926 | { | |
7927 | int size = 4; | |
43234a1e | 7928 | |
b5014f7a | 7929 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
7930 | size = 8; |
7931 | else if (i.types[n].bitfield.disp8) | |
7932 | size = 1; | |
7933 | else if (i.types[n].bitfield.disp16) | |
7934 | size = 2; | |
e205caa7 L |
7935 | return size; |
7936 | } | |
7937 | ||
7938 | /* Return the size of the immediate operand N. */ | |
7939 | ||
7940 | static int | |
7941 | imm_size (unsigned int n) | |
7942 | { | |
7943 | int size = 4; | |
40fb9820 L |
7944 | if (i.types[n].bitfield.imm64) |
7945 | size = 8; | |
7946 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
7947 | size = 1; | |
7948 | else if (i.types[n].bitfield.imm16) | |
7949 | size = 2; | |
e205caa7 L |
7950 | return size; |
7951 | } | |
7952 | ||
29b0f896 | 7953 | static void |
64e74474 | 7954 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7955 | { |
7956 | char *p; | |
7957 | unsigned int n; | |
252b5132 | 7958 | |
29b0f896 AM |
7959 | for (n = 0; n < i.operands; n++) |
7960 | { | |
b5014f7a | 7961 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
7962 | { |
7963 | if (i.op[n].disps->X_op == O_constant) | |
7964 | { | |
e205caa7 | 7965 | int size = disp_size (n); |
43234a1e | 7966 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 7967 | |
b5014f7a | 7968 | val = offset_in_range (val >> i.memshift, size); |
29b0f896 AM |
7969 | p = frag_more (size); |
7970 | md_number_to_chars (p, val, size); | |
7971 | } | |
7972 | else | |
7973 | { | |
f86103b7 | 7974 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 7975 | int size = disp_size (n); |
40fb9820 | 7976 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 7977 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 7978 | fixS *fixP; |
29b0f896 | 7979 | |
e205caa7 | 7980 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 7981 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 7982 | |
29b0f896 AM |
7983 | /* The PC relative address is computed relative |
7984 | to the instruction boundary, so in case immediate | |
7985 | fields follows, we need to adjust the value. */ | |
7986 | if (pcrel && i.imm_operands) | |
7987 | { | |
29b0f896 | 7988 | unsigned int n1; |
e205caa7 | 7989 | int sz = 0; |
252b5132 | 7990 | |
29b0f896 | 7991 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 7992 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 7993 | { |
e205caa7 L |
7994 | /* Only one immediate is allowed for PC |
7995 | relative address. */ | |
9c2799c2 | 7996 | gas_assert (sz == 0); |
e205caa7 L |
7997 | sz = imm_size (n1); |
7998 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 7999 | } |
29b0f896 | 8000 | /* We should find the immediate. */ |
9c2799c2 | 8001 | gas_assert (sz != 0); |
29b0f896 | 8002 | } |
520dc8e8 | 8003 | |
29b0f896 | 8004 | p = frag_more (size); |
d258b828 | 8005 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 8006 | if (GOT_symbol |
2bbd9c25 | 8007 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 8008 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8009 | || reloc_type == BFD_RELOC_X86_64_32S |
8010 | || (reloc_type == BFD_RELOC_64 | |
8011 | && object_64bit)) | |
d6ab8113 JB |
8012 | && (i.op[n].disps->X_op == O_symbol |
8013 | || (i.op[n].disps->X_op == O_add | |
8014 | && ((symbol_get_value_expression | |
8015 | (i.op[n].disps->X_op_symbol)->X_op) | |
8016 | == O_subtract)))) | |
8017 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
8018 | { |
8019 | offsetT add; | |
8020 | ||
8021 | if (insn_start_frag == frag_now) | |
8022 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8023 | else | |
8024 | { | |
8025 | fragS *fr; | |
8026 | ||
8027 | add = insn_start_frag->fr_fix - insn_start_off; | |
8028 | for (fr = insn_start_frag->fr_next; | |
8029 | fr && fr != frag_now; fr = fr->fr_next) | |
8030 | add += fr->fr_fix; | |
8031 | add += p - frag_now->fr_literal; | |
8032 | } | |
8033 | ||
4fa24527 | 8034 | if (!object_64bit) |
7b81dfbb AJ |
8035 | { |
8036 | reloc_type = BFD_RELOC_386_GOTPC; | |
8037 | i.op[n].imms->X_add_number += add; | |
8038 | } | |
8039 | else if (reloc_type == BFD_RELOC_64) | |
8040 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 8041 | else |
7b81dfbb AJ |
8042 | /* Don't do the adjustment for x86-64, as there |
8043 | the pcrel addressing is relative to the _next_ | |
8044 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 8045 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 8046 | } |
02a86693 L |
8047 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
8048 | size, i.op[n].disps, pcrel, | |
8049 | reloc_type); | |
8050 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
8051 | "test %reg, mem" and "binop mem, %reg" where binop | |
8052 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
0cb4071e L |
8053 | instructions. Always generate R_386_GOT32X for |
8054 | "sym*GOT" operand in 32-bit mode. */ | |
8055 | if ((generate_relax_relocations | |
8056 | || (!object_64bit | |
8057 | && i.rm.mode == 0 | |
8058 | && i.rm.regmem == 5)) | |
8059 | && (i.rm.mode == 2 | |
8060 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
8061 | && ((i.operands == 1 |
8062 | && i.tm.base_opcode == 0xff | |
8063 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
8064 | || (i.operands == 2 | |
8065 | && (i.tm.base_opcode == 0x8b | |
8066 | || i.tm.base_opcode == 0x85 | |
8067 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
8068 | { | |
8069 | if (object_64bit) | |
8070 | { | |
8071 | fixP->fx_tcbit = i.rex != 0; | |
8072 | if (i.base_reg | |
8073 | && (i.base_reg->reg_num == RegRip | |
8074 | || i.base_reg->reg_num == RegEip)) | |
8075 | fixP->fx_tcbit2 = 1; | |
8076 | } | |
8077 | else | |
8078 | fixP->fx_tcbit2 = 1; | |
8079 | } | |
29b0f896 AM |
8080 | } |
8081 | } | |
8082 | } | |
8083 | } | |
252b5132 | 8084 | |
29b0f896 | 8085 | static void |
64e74474 | 8086 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8087 | { |
8088 | char *p; | |
8089 | unsigned int n; | |
252b5132 | 8090 | |
29b0f896 AM |
8091 | for (n = 0; n < i.operands; n++) |
8092 | { | |
43234a1e L |
8093 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
8094 | if (i.rounding && (int) n == i.rounding->operand) | |
8095 | continue; | |
8096 | ||
40fb9820 | 8097 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
8098 | { |
8099 | if (i.op[n].imms->X_op == O_constant) | |
8100 | { | |
e205caa7 | 8101 | int size = imm_size (n); |
29b0f896 | 8102 | offsetT val; |
b4cac588 | 8103 | |
29b0f896 AM |
8104 | val = offset_in_range (i.op[n].imms->X_add_number, |
8105 | size); | |
8106 | p = frag_more (size); | |
8107 | md_number_to_chars (p, val, size); | |
8108 | } | |
8109 | else | |
8110 | { | |
8111 | /* Not absolute_section. | |
8112 | Need a 32-bit fixup (don't support 8bit | |
8113 | non-absolute imms). Try to support other | |
8114 | sizes ... */ | |
f86103b7 | 8115 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
8116 | int size = imm_size (n); |
8117 | int sign; | |
29b0f896 | 8118 | |
40fb9820 | 8119 | if (i.types[n].bitfield.imm32s |
a7d61044 | 8120 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 8121 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 8122 | sign = 1; |
e205caa7 L |
8123 | else |
8124 | sign = 0; | |
520dc8e8 | 8125 | |
29b0f896 | 8126 | p = frag_more (size); |
d258b828 | 8127 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 8128 | |
2bbd9c25 JJ |
8129 | /* This is tough to explain. We end up with this one if we |
8130 | * have operands that look like | |
8131 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
8132 | * obtain the absolute address of the GOT, and it is strongly | |
8133 | * preferable from a performance point of view to avoid using | |
8134 | * a runtime relocation for this. The actual sequence of | |
8135 | * instructions often look something like: | |
8136 | * | |
8137 | * call .L66 | |
8138 | * .L66: | |
8139 | * popl %ebx | |
8140 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
8141 | * | |
8142 | * The call and pop essentially return the absolute address | |
8143 | * of the label .L66 and store it in %ebx. The linker itself | |
8144 | * will ultimately change the first operand of the addl so | |
8145 | * that %ebx points to the GOT, but to keep things simple, the | |
8146 | * .o file must have this operand set so that it generates not | |
8147 | * the absolute address of .L66, but the absolute address of | |
8148 | * itself. This allows the linker itself simply treat a GOTPC | |
8149 | * relocation as asking for a pcrel offset to the GOT to be | |
8150 | * added in, and the addend of the relocation is stored in the | |
8151 | * operand field for the instruction itself. | |
8152 | * | |
8153 | * Our job here is to fix the operand so that it would add | |
8154 | * the correct offset so that %ebx would point to itself. The | |
8155 | * thing that is tricky is that .-.L66 will point to the | |
8156 | * beginning of the instruction, so we need to further modify | |
8157 | * the operand so that it will point to itself. There are | |
8158 | * other cases where you have something like: | |
8159 | * | |
8160 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
8161 | * | |
8162 | * and here no correction would be required. Internally in | |
8163 | * the assembler we treat operands of this form as not being | |
8164 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
8165 | * whether it would simplify matters to do it this way. Who | |
8166 | * knows. In earlier versions of the PIC patches, the | |
8167 | * pcrel_adjust field was used to store the correction, but | |
8168 | * since the expression is not pcrel, I felt it would be | |
8169 | * confusing to do it this way. */ | |
8170 | ||
d6ab8113 | 8171 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8172 | || reloc_type == BFD_RELOC_X86_64_32S |
8173 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
8174 | && GOT_symbol |
8175 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
8176 | && (i.op[n].imms->X_op == O_symbol | |
8177 | || (i.op[n].imms->X_op == O_add | |
8178 | && ((symbol_get_value_expression | |
8179 | (i.op[n].imms->X_op_symbol)->X_op) | |
8180 | == O_subtract)))) | |
8181 | { | |
2bbd9c25 JJ |
8182 | offsetT add; |
8183 | ||
8184 | if (insn_start_frag == frag_now) | |
8185 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8186 | else | |
8187 | { | |
8188 | fragS *fr; | |
8189 | ||
8190 | add = insn_start_frag->fr_fix - insn_start_off; | |
8191 | for (fr = insn_start_frag->fr_next; | |
8192 | fr && fr != frag_now; fr = fr->fr_next) | |
8193 | add += fr->fr_fix; | |
8194 | add += p - frag_now->fr_literal; | |
8195 | } | |
8196 | ||
4fa24527 | 8197 | if (!object_64bit) |
d6ab8113 | 8198 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 8199 | else if (size == 4) |
d6ab8113 | 8200 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
8201 | else if (size == 8) |
8202 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 8203 | i.op[n].imms->X_add_number += add; |
29b0f896 | 8204 | } |
29b0f896 AM |
8205 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
8206 | i.op[n].imms, 0, reloc_type); | |
8207 | } | |
8208 | } | |
8209 | } | |
252b5132 RH |
8210 | } |
8211 | \f | |
d182319b JB |
8212 | /* x86_cons_fix_new is called via the expression parsing code when a |
8213 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
8214 | static int cons_sign = -1; |
8215 | ||
8216 | void | |
e3bb37b5 | 8217 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 8218 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 8219 | { |
d258b828 | 8220 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
8221 | |
8222 | #ifdef TE_PE | |
8223 | if (exp->X_op == O_secrel) | |
8224 | { | |
8225 | exp->X_op = O_symbol; | |
8226 | r = BFD_RELOC_32_SECREL; | |
8227 | } | |
8228 | #endif | |
8229 | ||
8230 | fix_new_exp (frag, off, len, exp, 0, r); | |
8231 | } | |
8232 | ||
357d1bd8 L |
8233 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
8234 | purpose of the `.dc.a' internal pseudo-op. */ | |
8235 | ||
8236 | int | |
8237 | x86_address_bytes (void) | |
8238 | { | |
8239 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
8240 | return 4; | |
8241 | return stdoutput->arch_info->bits_per_address / 8; | |
8242 | } | |
8243 | ||
d382c579 TG |
8244 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
8245 | || defined (LEX_AT) | |
d258b828 | 8246 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 8247 | #else |
f3c180ae AM |
8248 | /* Parse operands of the form |
8249 | <symbol>@GOTOFF+<nnn> | |
8250 | and similar .plt or .got references. | |
8251 | ||
8252 | If we find one, set up the correct relocation in RELOC and copy the | |
8253 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
8254 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8255 | is non-null set it to the length of the string we removed from the | |
8256 | input line. Otherwise return NULL. */ | |
8257 | static char * | |
91d6fa6a | 8258 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 8259 | int *adjust, |
d258b828 | 8260 | i386_operand_type *types) |
f3c180ae | 8261 | { |
7b81dfbb AJ |
8262 | /* Some of the relocations depend on the size of what field is to |
8263 | be relocated. But in our callers i386_immediate and i386_displacement | |
8264 | we don't yet know the operand size (this will be set by insn | |
8265 | matching). Hence we record the word32 relocation here, | |
8266 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
8267 | static const struct { |
8268 | const char *str; | |
cff8d58a | 8269 | int len; |
4fa24527 | 8270 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 8271 | const i386_operand_type types64; |
f3c180ae | 8272 | } gotrel[] = { |
8ce3d284 | 8273 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
8274 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
8275 | BFD_RELOC_SIZE32 }, | |
8276 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 8277 | #endif |
cff8d58a L |
8278 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
8279 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 8280 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
8281 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
8282 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 8283 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8284 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
8285 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 8286 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8287 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
8288 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 8289 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8290 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
8291 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 8292 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8293 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
8294 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 8295 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8296 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
8297 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8298 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8299 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
8300 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 8301 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8302 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
8303 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 8304 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8305 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
8306 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 8307 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8308 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
8309 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8310 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8311 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
8312 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 8313 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8314 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
8315 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8316 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8317 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
8318 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8319 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8320 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
8321 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 8322 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
8323 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
8324 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 8325 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8326 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
8327 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 8328 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
8329 | }; |
8330 | char *cp; | |
8331 | unsigned int j; | |
8332 | ||
d382c579 | 8333 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
8334 | if (!IS_ELF) |
8335 | return NULL; | |
d382c579 | 8336 | #endif |
718ddfc0 | 8337 | |
f3c180ae | 8338 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 8339 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
8340 | return NULL; |
8341 | ||
47465058 | 8342 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 8343 | { |
cff8d58a | 8344 | int len = gotrel[j].len; |
28f81592 | 8345 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 8346 | { |
4fa24527 | 8347 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 8348 | { |
28f81592 AM |
8349 | int first, second; |
8350 | char *tmpbuf, *past_reloc; | |
f3c180ae | 8351 | |
91d6fa6a | 8352 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 8353 | |
3956db08 JB |
8354 | if (types) |
8355 | { | |
8356 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
8357 | { |
8358 | types->bitfield.imm32 = 1; | |
8359 | types->bitfield.disp32 = 1; | |
8360 | } | |
3956db08 JB |
8361 | else |
8362 | *types = gotrel[j].types64; | |
8363 | } | |
8364 | ||
8fd4256d | 8365 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
8366 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
8367 | ||
28f81592 | 8368 | /* The length of the first part of our input line. */ |
f3c180ae | 8369 | first = cp - input_line_pointer; |
28f81592 AM |
8370 | |
8371 | /* The second part goes from after the reloc token until | |
67c11a9b | 8372 | (and including) an end_of_line char or comma. */ |
28f81592 | 8373 | past_reloc = cp + 1 + len; |
67c11a9b AM |
8374 | cp = past_reloc; |
8375 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8376 | ++cp; | |
8377 | second = cp + 1 - past_reloc; | |
28f81592 AM |
8378 | |
8379 | /* Allocate and copy string. The trailing NUL shouldn't | |
8380 | be necessary, but be safe. */ | |
add39d23 | 8381 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 8382 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
8383 | if (second != 0 && *past_reloc != ' ') |
8384 | /* Replace the relocation token with ' ', so that | |
8385 | errors like foo@GOTOFF1 will be detected. */ | |
8386 | tmpbuf[first++] = ' '; | |
af89796a L |
8387 | else |
8388 | /* Increment length by 1 if the relocation token is | |
8389 | removed. */ | |
8390 | len++; | |
8391 | if (adjust) | |
8392 | *adjust = len; | |
0787a12d AM |
8393 | memcpy (tmpbuf + first, past_reloc, second); |
8394 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
8395 | return tmpbuf; |
8396 | } | |
8397 | ||
4fa24527 JB |
8398 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
8399 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
8400 | return NULL; |
8401 | } | |
8402 | } | |
8403 | ||
8404 | /* Might be a symbol version string. Don't as_bad here. */ | |
8405 | return NULL; | |
8406 | } | |
4e4f7c87 | 8407 | #endif |
f3c180ae | 8408 | |
a988325c NC |
8409 | #ifdef TE_PE |
8410 | #ifdef lex_got | |
8411 | #undef lex_got | |
8412 | #endif | |
8413 | /* Parse operands of the form | |
8414 | <symbol>@SECREL32+<nnn> | |
8415 | ||
8416 | If we find one, set up the correct relocation in RELOC and copy the | |
8417 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
8418 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8419 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
8420 | input line. Otherwise return NULL. |
8421 | ||
a988325c NC |
8422 | This function is copied from the ELF version above adjusted for PE targets. */ |
8423 | ||
8424 | static char * | |
8425 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
8426 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 8427 | i386_operand_type *types) |
a988325c NC |
8428 | { |
8429 | static const struct | |
8430 | { | |
8431 | const char *str; | |
8432 | int len; | |
8433 | const enum bfd_reloc_code_real rel[2]; | |
8434 | const i386_operand_type types64; | |
8435 | } | |
8436 | gotrel[] = | |
8437 | { | |
8438 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
8439 | BFD_RELOC_32_SECREL }, | |
8440 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
8441 | }; | |
8442 | ||
8443 | char *cp; | |
8444 | unsigned j; | |
8445 | ||
8446 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
8447 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
8448 | return NULL; | |
8449 | ||
8450 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
8451 | { | |
8452 | int len = gotrel[j].len; | |
8453 | ||
8454 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
8455 | { | |
8456 | if (gotrel[j].rel[object_64bit] != 0) | |
8457 | { | |
8458 | int first, second; | |
8459 | char *tmpbuf, *past_reloc; | |
8460 | ||
8461 | *rel = gotrel[j].rel[object_64bit]; | |
8462 | if (adjust) | |
8463 | *adjust = len; | |
8464 | ||
8465 | if (types) | |
8466 | { | |
8467 | if (flag_code != CODE_64BIT) | |
8468 | { | |
8469 | types->bitfield.imm32 = 1; | |
8470 | types->bitfield.disp32 = 1; | |
8471 | } | |
8472 | else | |
8473 | *types = gotrel[j].types64; | |
8474 | } | |
8475 | ||
8476 | /* The length of the first part of our input line. */ | |
8477 | first = cp - input_line_pointer; | |
8478 | ||
8479 | /* The second part goes from after the reloc token until | |
8480 | (and including) an end_of_line char or comma. */ | |
8481 | past_reloc = cp + 1 + len; | |
8482 | cp = past_reloc; | |
8483 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8484 | ++cp; | |
8485 | second = cp + 1 - past_reloc; | |
8486 | ||
8487 | /* Allocate and copy string. The trailing NUL shouldn't | |
8488 | be necessary, but be safe. */ | |
add39d23 | 8489 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
8490 | memcpy (tmpbuf, input_line_pointer, first); |
8491 | if (second != 0 && *past_reloc != ' ') | |
8492 | /* Replace the relocation token with ' ', so that | |
8493 | errors like foo@SECLREL321 will be detected. */ | |
8494 | tmpbuf[first++] = ' '; | |
8495 | memcpy (tmpbuf + first, past_reloc, second); | |
8496 | tmpbuf[first + second] = '\0'; | |
8497 | return tmpbuf; | |
8498 | } | |
8499 | ||
8500 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
8501 | gotrel[j].str, 1 << (5 + object_64bit)); | |
8502 | return NULL; | |
8503 | } | |
8504 | } | |
8505 | ||
8506 | /* Might be a symbol version string. Don't as_bad here. */ | |
8507 | return NULL; | |
8508 | } | |
8509 | ||
8510 | #endif /* TE_PE */ | |
8511 | ||
62ebcb5c | 8512 | bfd_reloc_code_real_type |
e3bb37b5 | 8513 | x86_cons (expressionS *exp, int size) |
f3c180ae | 8514 | { |
62ebcb5c AM |
8515 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
8516 | ||
ee86248c JB |
8517 | intel_syntax = -intel_syntax; |
8518 | ||
3c7b9c2c | 8519 | exp->X_md = 0; |
4fa24527 | 8520 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
8521 | { |
8522 | /* Handle @GOTOFF and the like in an expression. */ | |
8523 | char *save; | |
8524 | char *gotfree_input_line; | |
4a57f2cf | 8525 | int adjust = 0; |
f3c180ae AM |
8526 | |
8527 | save = input_line_pointer; | |
d258b828 | 8528 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
8529 | if (gotfree_input_line) |
8530 | input_line_pointer = gotfree_input_line; | |
8531 | ||
8532 | expression (exp); | |
8533 | ||
8534 | if (gotfree_input_line) | |
8535 | { | |
8536 | /* expression () has merrily parsed up to the end of line, | |
8537 | or a comma - in the wrong buffer. Transfer how far | |
8538 | input_line_pointer has moved to the right buffer. */ | |
8539 | input_line_pointer = (save | |
8540 | + (input_line_pointer - gotfree_input_line) | |
8541 | + adjust); | |
8542 | free (gotfree_input_line); | |
3992d3b7 AM |
8543 | if (exp->X_op == O_constant |
8544 | || exp->X_op == O_absent | |
8545 | || exp->X_op == O_illegal | |
0398aac5 | 8546 | || exp->X_op == O_register |
3992d3b7 AM |
8547 | || exp->X_op == O_big) |
8548 | { | |
8549 | char c = *input_line_pointer; | |
8550 | *input_line_pointer = 0; | |
8551 | as_bad (_("missing or invalid expression `%s'"), save); | |
8552 | *input_line_pointer = c; | |
8553 | } | |
f3c180ae AM |
8554 | } |
8555 | } | |
8556 | else | |
8557 | expression (exp); | |
ee86248c JB |
8558 | |
8559 | intel_syntax = -intel_syntax; | |
8560 | ||
8561 | if (intel_syntax) | |
8562 | i386_intel_simplify (exp); | |
62ebcb5c AM |
8563 | |
8564 | return got_reloc; | |
f3c180ae | 8565 | } |
f3c180ae | 8566 | |
9f32dd5b L |
8567 | static void |
8568 | signed_cons (int size) | |
6482c264 | 8569 | { |
d182319b JB |
8570 | if (flag_code == CODE_64BIT) |
8571 | cons_sign = 1; | |
8572 | cons (size); | |
8573 | cons_sign = -1; | |
6482c264 NC |
8574 | } |
8575 | ||
d182319b | 8576 | #ifdef TE_PE |
6482c264 | 8577 | static void |
7016a5d5 | 8578 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
8579 | { |
8580 | expressionS exp; | |
8581 | ||
8582 | do | |
8583 | { | |
8584 | expression (&exp); | |
8585 | if (exp.X_op == O_symbol) | |
8586 | exp.X_op = O_secrel; | |
8587 | ||
8588 | emit_expr (&exp, 4); | |
8589 | } | |
8590 | while (*input_line_pointer++ == ','); | |
8591 | ||
8592 | input_line_pointer--; | |
8593 | demand_empty_rest_of_line (); | |
8594 | } | |
6482c264 NC |
8595 | #endif |
8596 | ||
43234a1e L |
8597 | /* Handle Vector operations. */ |
8598 | ||
8599 | static char * | |
8600 | check_VecOperations (char *op_string, char *op_end) | |
8601 | { | |
8602 | const reg_entry *mask; | |
8603 | const char *saved; | |
8604 | char *end_op; | |
8605 | ||
8606 | while (*op_string | |
8607 | && (op_end == NULL || op_string < op_end)) | |
8608 | { | |
8609 | saved = op_string; | |
8610 | if (*op_string == '{') | |
8611 | { | |
8612 | op_string++; | |
8613 | ||
8614 | /* Check broadcasts. */ | |
8615 | if (strncmp (op_string, "1to", 3) == 0) | |
8616 | { | |
8617 | int bcst_type; | |
8618 | ||
8619 | if (i.broadcast) | |
8620 | goto duplicated_vec_op; | |
8621 | ||
8622 | op_string += 3; | |
8623 | if (*op_string == '8') | |
8e6e0792 | 8624 | bcst_type = 8; |
b28d1bda | 8625 | else if (*op_string == '4') |
8e6e0792 | 8626 | bcst_type = 4; |
b28d1bda | 8627 | else if (*op_string == '2') |
8e6e0792 | 8628 | bcst_type = 2; |
43234a1e L |
8629 | else if (*op_string == '1' |
8630 | && *(op_string+1) == '6') | |
8631 | { | |
8e6e0792 | 8632 | bcst_type = 16; |
43234a1e L |
8633 | op_string++; |
8634 | } | |
8635 | else | |
8636 | { | |
8637 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
8638 | return NULL; | |
8639 | } | |
8640 | op_string++; | |
8641 | ||
8642 | broadcast_op.type = bcst_type; | |
8643 | broadcast_op.operand = this_operand; | |
1f75763a | 8644 | broadcast_op.bytes = 0; |
43234a1e L |
8645 | i.broadcast = &broadcast_op; |
8646 | } | |
8647 | /* Check masking operation. */ | |
8648 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
8649 | { | |
8650 | /* k0 can't be used for write mask. */ | |
6d2cd6b2 | 8651 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
43234a1e | 8652 | { |
6d2cd6b2 JB |
8653 | as_bad (_("`%s%s' can't be used for write mask"), |
8654 | register_prefix, mask->reg_name); | |
43234a1e L |
8655 | return NULL; |
8656 | } | |
8657 | ||
8658 | if (!i.mask) | |
8659 | { | |
8660 | mask_op.mask = mask; | |
8661 | mask_op.zeroing = 0; | |
8662 | mask_op.operand = this_operand; | |
8663 | i.mask = &mask_op; | |
8664 | } | |
8665 | else | |
8666 | { | |
8667 | if (i.mask->mask) | |
8668 | goto duplicated_vec_op; | |
8669 | ||
8670 | i.mask->mask = mask; | |
8671 | ||
8672 | /* Only "{z}" is allowed here. No need to check | |
8673 | zeroing mask explicitly. */ | |
8674 | if (i.mask->operand != this_operand) | |
8675 | { | |
8676 | as_bad (_("invalid write mask `%s'"), saved); | |
8677 | return NULL; | |
8678 | } | |
8679 | } | |
8680 | ||
8681 | op_string = end_op; | |
8682 | } | |
8683 | /* Check zeroing-flag for masking operation. */ | |
8684 | else if (*op_string == 'z') | |
8685 | { | |
8686 | if (!i.mask) | |
8687 | { | |
8688 | mask_op.mask = NULL; | |
8689 | mask_op.zeroing = 1; | |
8690 | mask_op.operand = this_operand; | |
8691 | i.mask = &mask_op; | |
8692 | } | |
8693 | else | |
8694 | { | |
8695 | if (i.mask->zeroing) | |
8696 | { | |
8697 | duplicated_vec_op: | |
8698 | as_bad (_("duplicated `%s'"), saved); | |
8699 | return NULL; | |
8700 | } | |
8701 | ||
8702 | i.mask->zeroing = 1; | |
8703 | ||
8704 | /* Only "{%k}" is allowed here. No need to check mask | |
8705 | register explicitly. */ | |
8706 | if (i.mask->operand != this_operand) | |
8707 | { | |
8708 | as_bad (_("invalid zeroing-masking `%s'"), | |
8709 | saved); | |
8710 | return NULL; | |
8711 | } | |
8712 | } | |
8713 | ||
8714 | op_string++; | |
8715 | } | |
8716 | else | |
8717 | goto unknown_vec_op; | |
8718 | ||
8719 | if (*op_string != '}') | |
8720 | { | |
8721 | as_bad (_("missing `}' in `%s'"), saved); | |
8722 | return NULL; | |
8723 | } | |
8724 | op_string++; | |
0ba3a731 L |
8725 | |
8726 | /* Strip whitespace since the addition of pseudo prefixes | |
8727 | changed how the scrubber treats '{'. */ | |
8728 | if (is_space_char (*op_string)) | |
8729 | ++op_string; | |
8730 | ||
43234a1e L |
8731 | continue; |
8732 | } | |
8733 | unknown_vec_op: | |
8734 | /* We don't know this one. */ | |
8735 | as_bad (_("unknown vector operation: `%s'"), saved); | |
8736 | return NULL; | |
8737 | } | |
8738 | ||
6d2cd6b2 JB |
8739 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
8740 | { | |
8741 | as_bad (_("zeroing-masking only allowed with write mask")); | |
8742 | return NULL; | |
8743 | } | |
8744 | ||
43234a1e L |
8745 | return op_string; |
8746 | } | |
8747 | ||
252b5132 | 8748 | static int |
70e41ade | 8749 | i386_immediate (char *imm_start) |
252b5132 RH |
8750 | { |
8751 | char *save_input_line_pointer; | |
f3c180ae | 8752 | char *gotfree_input_line; |
252b5132 | 8753 | segT exp_seg = 0; |
47926f60 | 8754 | expressionS *exp; |
40fb9820 L |
8755 | i386_operand_type types; |
8756 | ||
0dfbf9d7 | 8757 | operand_type_set (&types, ~0); |
252b5132 RH |
8758 | |
8759 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
8760 | { | |
31b2323c L |
8761 | as_bad (_("at most %d immediate operands are allowed"), |
8762 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
8763 | return 0; |
8764 | } | |
8765 | ||
8766 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 8767 | i.op[this_operand].imms = exp; |
252b5132 RH |
8768 | |
8769 | if (is_space_char (*imm_start)) | |
8770 | ++imm_start; | |
8771 | ||
8772 | save_input_line_pointer = input_line_pointer; | |
8773 | input_line_pointer = imm_start; | |
8774 | ||
d258b828 | 8775 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8776 | if (gotfree_input_line) |
8777 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
8778 | |
8779 | exp_seg = expression (exp); | |
8780 | ||
83183c0c | 8781 | SKIP_WHITESPACE (); |
43234a1e L |
8782 | |
8783 | /* Handle vector operations. */ | |
8784 | if (*input_line_pointer == '{') | |
8785 | { | |
8786 | input_line_pointer = check_VecOperations (input_line_pointer, | |
8787 | NULL); | |
8788 | if (input_line_pointer == NULL) | |
8789 | return 0; | |
8790 | } | |
8791 | ||
252b5132 | 8792 | if (*input_line_pointer) |
f3c180ae | 8793 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
8794 | |
8795 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 8796 | if (gotfree_input_line) |
ee86248c JB |
8797 | { |
8798 | free (gotfree_input_line); | |
8799 | ||
8800 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8801 | exp->X_op = O_illegal; | |
8802 | } | |
8803 | ||
8804 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
8805 | } | |
252b5132 | 8806 | |
ee86248c JB |
8807 | static int |
8808 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8809 | i386_operand_type types, const char *imm_start) | |
8810 | { | |
8811 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 8812 | { |
313c53d1 L |
8813 | if (imm_start) |
8814 | as_bad (_("missing or invalid immediate expression `%s'"), | |
8815 | imm_start); | |
3992d3b7 | 8816 | return 0; |
252b5132 | 8817 | } |
3e73aa7c | 8818 | else if (exp->X_op == O_constant) |
252b5132 | 8819 | { |
47926f60 | 8820 | /* Size it properly later. */ |
40fb9820 | 8821 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
8822 | /* If not 64bit, sign extend val. */ |
8823 | if (flag_code != CODE_64BIT | |
4eed87de AM |
8824 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
8825 | exp->X_add_number | |
8826 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 8827 | } |
4c63da97 | 8828 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 8829 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 8830 | && exp_seg != absolute_section |
47926f60 | 8831 | && exp_seg != text_section |
24eab124 AM |
8832 | && exp_seg != data_section |
8833 | && exp_seg != bss_section | |
8834 | && exp_seg != undefined_section | |
f86103b7 | 8835 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 8836 | { |
d0b47220 | 8837 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
8838 | return 0; |
8839 | } | |
8840 | #endif | |
a841bdf5 | 8841 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 8842 | { |
313c53d1 L |
8843 | if (imm_start) |
8844 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
8845 | return 0; |
8846 | } | |
252b5132 RH |
8847 | else |
8848 | { | |
8849 | /* This is an address. The size of the address will be | |
24eab124 | 8850 | determined later, depending on destination register, |
3e73aa7c | 8851 | suffix, or the default for the section. */ |
40fb9820 L |
8852 | i.types[this_operand].bitfield.imm8 = 1; |
8853 | i.types[this_operand].bitfield.imm16 = 1; | |
8854 | i.types[this_operand].bitfield.imm32 = 1; | |
8855 | i.types[this_operand].bitfield.imm32s = 1; | |
8856 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
8857 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8858 | types); | |
252b5132 RH |
8859 | } |
8860 | ||
8861 | return 1; | |
8862 | } | |
8863 | ||
551c1ca1 | 8864 | static char * |
e3bb37b5 | 8865 | i386_scale (char *scale) |
252b5132 | 8866 | { |
551c1ca1 AM |
8867 | offsetT val; |
8868 | char *save = input_line_pointer; | |
252b5132 | 8869 | |
551c1ca1 AM |
8870 | input_line_pointer = scale; |
8871 | val = get_absolute_expression (); | |
8872 | ||
8873 | switch (val) | |
252b5132 | 8874 | { |
551c1ca1 | 8875 | case 1: |
252b5132 RH |
8876 | i.log2_scale_factor = 0; |
8877 | break; | |
551c1ca1 | 8878 | case 2: |
252b5132 RH |
8879 | i.log2_scale_factor = 1; |
8880 | break; | |
551c1ca1 | 8881 | case 4: |
252b5132 RH |
8882 | i.log2_scale_factor = 2; |
8883 | break; | |
551c1ca1 | 8884 | case 8: |
252b5132 RH |
8885 | i.log2_scale_factor = 3; |
8886 | break; | |
8887 | default: | |
a724f0f4 JB |
8888 | { |
8889 | char sep = *input_line_pointer; | |
8890 | ||
8891 | *input_line_pointer = '\0'; | |
8892 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
8893 | scale); | |
8894 | *input_line_pointer = sep; | |
8895 | input_line_pointer = save; | |
8896 | return NULL; | |
8897 | } | |
252b5132 | 8898 | } |
29b0f896 | 8899 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
8900 | { |
8901 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 8902 | 1 << i.log2_scale_factor); |
252b5132 | 8903 | i.log2_scale_factor = 0; |
252b5132 | 8904 | } |
551c1ca1 AM |
8905 | scale = input_line_pointer; |
8906 | input_line_pointer = save; | |
8907 | return scale; | |
252b5132 RH |
8908 | } |
8909 | ||
252b5132 | 8910 | static int |
e3bb37b5 | 8911 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 8912 | { |
29b0f896 | 8913 | expressionS *exp; |
252b5132 RH |
8914 | segT exp_seg = 0; |
8915 | char *save_input_line_pointer; | |
f3c180ae | 8916 | char *gotfree_input_line; |
40fb9820 L |
8917 | int override; |
8918 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 8919 | int ret; |
252b5132 | 8920 | |
31b2323c L |
8921 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
8922 | { | |
8923 | as_bad (_("at most %d displacement operands are allowed"), | |
8924 | MAX_MEMORY_OPERANDS); | |
8925 | return 0; | |
8926 | } | |
8927 | ||
0dfbf9d7 | 8928 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
8929 | if ((i.types[this_operand].bitfield.jumpabsolute) |
8930 | || (!current_templates->start->opcode_modifier.jump | |
8931 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 8932 | { |
40fb9820 | 8933 | bigdisp.bitfield.disp32 = 1; |
e05278af | 8934 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
8935 | if (flag_code == CODE_64BIT) |
8936 | { | |
8937 | if (!override) | |
8938 | { | |
8939 | bigdisp.bitfield.disp32s = 1; | |
8940 | bigdisp.bitfield.disp64 = 1; | |
8941 | } | |
8942 | } | |
8943 | else if ((flag_code == CODE_16BIT) ^ override) | |
8944 | { | |
8945 | bigdisp.bitfield.disp32 = 0; | |
8946 | bigdisp.bitfield.disp16 = 1; | |
8947 | } | |
e05278af JB |
8948 | } |
8949 | else | |
8950 | { | |
8951 | /* For PC-relative branches, the width of the displacement | |
8952 | is dependent upon data size, not address size. */ | |
e05278af | 8953 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
8954 | if (flag_code == CODE_64BIT) |
8955 | { | |
8956 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
8957 | bigdisp.bitfield.disp16 = 1; | |
8958 | else | |
8959 | { | |
8960 | bigdisp.bitfield.disp32 = 1; | |
8961 | bigdisp.bitfield.disp32s = 1; | |
8962 | } | |
8963 | } | |
8964 | else | |
e05278af JB |
8965 | { |
8966 | if (!override) | |
8967 | override = (i.suffix == (flag_code != CODE_16BIT | |
8968 | ? WORD_MNEM_SUFFIX | |
8969 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
8970 | bigdisp.bitfield.disp32 = 1; |
8971 | if ((flag_code == CODE_16BIT) ^ override) | |
8972 | { | |
8973 | bigdisp.bitfield.disp32 = 0; | |
8974 | bigdisp.bitfield.disp16 = 1; | |
8975 | } | |
e05278af | 8976 | } |
e05278af | 8977 | } |
c6fb90c8 L |
8978 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8979 | bigdisp); | |
252b5132 RH |
8980 | |
8981 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 8982 | i.op[this_operand].disps = exp; |
252b5132 RH |
8983 | i.disp_operands++; |
8984 | save_input_line_pointer = input_line_pointer; | |
8985 | input_line_pointer = disp_start; | |
8986 | END_STRING_AND_SAVE (disp_end); | |
8987 | ||
8988 | #ifndef GCC_ASM_O_HACK | |
8989 | #define GCC_ASM_O_HACK 0 | |
8990 | #endif | |
8991 | #if GCC_ASM_O_HACK | |
8992 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 8993 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 8994 | && displacement_string_end[-1] == '+') |
252b5132 RH |
8995 | { |
8996 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
8997 | constraint within gcc asm statements. |
8998 | For instance: | |
8999 | ||
9000 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
9001 | __asm__ __volatile__ ( \ | |
9002 | "movw %w2,%0\n\t" \ | |
9003 | "movw %w1,2+%0\n\t" \ | |
9004 | "rorl $16,%1\n\t" \ | |
9005 | "movb %b1,4+%0\n\t" \ | |
9006 | "movb %4,5+%0\n\t" \ | |
9007 | "movb $0,6+%0\n\t" \ | |
9008 | "movb %h1,7+%0\n\t" \ | |
9009 | "rorl $16,%1" \ | |
9010 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
9011 | ||
9012 | This works great except that the output assembler ends | |
9013 | up looking a bit weird if it turns out that there is | |
9014 | no offset. You end up producing code that looks like: | |
9015 | ||
9016 | #APP | |
9017 | movw $235,(%eax) | |
9018 | movw %dx,2+(%eax) | |
9019 | rorl $16,%edx | |
9020 | movb %dl,4+(%eax) | |
9021 | movb $137,5+(%eax) | |
9022 | movb $0,6+(%eax) | |
9023 | movb %dh,7+(%eax) | |
9024 | rorl $16,%edx | |
9025 | #NO_APP | |
9026 | ||
47926f60 | 9027 | So here we provide the missing zero. */ |
24eab124 AM |
9028 | |
9029 | *displacement_string_end = '0'; | |
252b5132 RH |
9030 | } |
9031 | #endif | |
d258b828 | 9032 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9033 | if (gotfree_input_line) |
9034 | input_line_pointer = gotfree_input_line; | |
252b5132 | 9035 | |
24eab124 | 9036 | exp_seg = expression (exp); |
252b5132 | 9037 | |
636c26b0 AM |
9038 | SKIP_WHITESPACE (); |
9039 | if (*input_line_pointer) | |
9040 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
9041 | #if GCC_ASM_O_HACK | |
9042 | RESTORE_END_STRING (disp_end + 1); | |
9043 | #endif | |
636c26b0 | 9044 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 9045 | if (gotfree_input_line) |
ee86248c JB |
9046 | { |
9047 | free (gotfree_input_line); | |
9048 | ||
9049 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9050 | exp->X_op = O_illegal; | |
9051 | } | |
9052 | ||
9053 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
9054 | ||
9055 | RESTORE_END_STRING (disp_end); | |
9056 | ||
9057 | return ret; | |
9058 | } | |
9059 | ||
9060 | static int | |
9061 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9062 | i386_operand_type types, const char *disp_start) | |
9063 | { | |
9064 | i386_operand_type bigdisp; | |
9065 | int ret = 1; | |
636c26b0 | 9066 | |
24eab124 AM |
9067 | /* We do this to make sure that the section symbol is in |
9068 | the symbol table. We will ultimately change the relocation | |
47926f60 | 9069 | to be relative to the beginning of the section. */ |
1ae12ab7 | 9070 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
9071 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
9072 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 9073 | { |
636c26b0 | 9074 | if (exp->X_op != O_symbol) |
3992d3b7 | 9075 | goto inv_disp; |
636c26b0 | 9076 | |
e5cb08ac | 9077 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
9078 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
9079 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 9080 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
9081 | exp->X_op = O_subtract; |
9082 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 9083 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 9084 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
9085 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
9086 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 9087 | else |
29b0f896 | 9088 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 9089 | } |
252b5132 | 9090 | |
3992d3b7 AM |
9091 | else if (exp->X_op == O_absent |
9092 | || exp->X_op == O_illegal | |
ee86248c | 9093 | || exp->X_op == O_big) |
2daf4fd8 | 9094 | { |
3992d3b7 AM |
9095 | inv_disp: |
9096 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 9097 | disp_start); |
3992d3b7 | 9098 | ret = 0; |
2daf4fd8 AM |
9099 | } |
9100 | ||
0e1147d9 L |
9101 | else if (flag_code == CODE_64BIT |
9102 | && !i.prefix[ADDR_PREFIX] | |
9103 | && exp->X_op == O_constant) | |
9104 | { | |
9105 | /* Since displacement is signed extended to 64bit, don't allow | |
9106 | disp32 and turn off disp32s if they are out of range. */ | |
9107 | i.types[this_operand].bitfield.disp32 = 0; | |
9108 | if (!fits_in_signed_long (exp->X_add_number)) | |
9109 | { | |
9110 | i.types[this_operand].bitfield.disp32s = 0; | |
9111 | if (i.types[this_operand].bitfield.baseindex) | |
9112 | { | |
9113 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
9114 | (long) exp->X_add_number); | |
9115 | ret = 0; | |
9116 | } | |
9117 | } | |
9118 | } | |
9119 | ||
4c63da97 | 9120 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
9121 | else if (exp->X_op != O_constant |
9122 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
9123 | && exp_seg != absolute_section | |
9124 | && exp_seg != text_section | |
9125 | && exp_seg != data_section | |
9126 | && exp_seg != bss_section | |
9127 | && exp_seg != undefined_section | |
9128 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 9129 | { |
d0b47220 | 9130 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 9131 | ret = 0; |
24eab124 | 9132 | } |
252b5132 | 9133 | #endif |
3956db08 | 9134 | |
40fb9820 L |
9135 | /* Check if this is a displacement only operand. */ |
9136 | bigdisp = i.types[this_operand]; | |
9137 | bigdisp.bitfield.disp8 = 0; | |
9138 | bigdisp.bitfield.disp16 = 0; | |
9139 | bigdisp.bitfield.disp32 = 0; | |
9140 | bigdisp.bitfield.disp32s = 0; | |
9141 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 9142 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
9143 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9144 | types); | |
3956db08 | 9145 | |
3992d3b7 | 9146 | return ret; |
252b5132 RH |
9147 | } |
9148 | ||
2abc2bec JB |
9149 | /* Return the active addressing mode, taking address override and |
9150 | registers forming the address into consideration. Update the | |
9151 | address override prefix if necessary. */ | |
47926f60 | 9152 | |
2abc2bec JB |
9153 | static enum flag_code |
9154 | i386_addressing_mode (void) | |
252b5132 | 9155 | { |
be05d201 L |
9156 | enum flag_code addr_mode; |
9157 | ||
9158 | if (i.prefix[ADDR_PREFIX]) | |
9159 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
9160 | else | |
9161 | { | |
9162 | addr_mode = flag_code; | |
9163 | ||
24eab124 | 9164 | #if INFER_ADDR_PREFIX |
be05d201 L |
9165 | if (i.mem_operands == 0) |
9166 | { | |
9167 | /* Infer address prefix from the first memory operand. */ | |
9168 | const reg_entry *addr_reg = i.base_reg; | |
9169 | ||
9170 | if (addr_reg == NULL) | |
9171 | addr_reg = i.index_reg; | |
eecb386c | 9172 | |
be05d201 L |
9173 | if (addr_reg) |
9174 | { | |
9175 | if (addr_reg->reg_num == RegEip | |
9176 | || addr_reg->reg_num == RegEiz | |
dc821c5f | 9177 | || addr_reg->reg_type.bitfield.dword) |
be05d201 L |
9178 | addr_mode = CODE_32BIT; |
9179 | else if (flag_code != CODE_64BIT | |
dc821c5f | 9180 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
9181 | addr_mode = CODE_16BIT; |
9182 | ||
9183 | if (addr_mode != flag_code) | |
9184 | { | |
9185 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
9186 | i.prefixes += 1; | |
9187 | /* Change the size of any displacement too. At most one | |
9188 | of Disp16 or Disp32 is set. | |
9189 | FIXME. There doesn't seem to be any real need for | |
9190 | separate Disp16 and Disp32 flags. The same goes for | |
9191 | Imm16 and Imm32. Removing them would probably clean | |
9192 | up the code quite a lot. */ | |
9193 | if (flag_code != CODE_64BIT | |
9194 | && (i.types[this_operand].bitfield.disp16 | |
9195 | || i.types[this_operand].bitfield.disp32)) | |
9196 | i.types[this_operand] | |
9197 | = operand_type_xor (i.types[this_operand], disp16_32); | |
9198 | } | |
9199 | } | |
9200 | } | |
24eab124 | 9201 | #endif |
be05d201 L |
9202 | } |
9203 | ||
2abc2bec JB |
9204 | return addr_mode; |
9205 | } | |
9206 | ||
9207 | /* Make sure the memory operand we've been dealt is valid. | |
9208 | Return 1 on success, 0 on a failure. */ | |
9209 | ||
9210 | static int | |
9211 | i386_index_check (const char *operand_string) | |
9212 | { | |
9213 | const char *kind = "base/index"; | |
9214 | enum flag_code addr_mode = i386_addressing_mode (); | |
9215 | ||
fc0763e6 JB |
9216 | if (current_templates->start->opcode_modifier.isstring |
9217 | && !current_templates->start->opcode_modifier.immext | |
9218 | && (current_templates->end[-1].opcode_modifier.isstring | |
9219 | || i.mem_operands)) | |
9220 | { | |
9221 | /* Memory operands of string insns are special in that they only allow | |
9222 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
9223 | const reg_entry *expected_reg; |
9224 | static const char *di_si[][2] = | |
9225 | { | |
9226 | { "esi", "edi" }, | |
9227 | { "si", "di" }, | |
9228 | { "rsi", "rdi" } | |
9229 | }; | |
9230 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
9231 | |
9232 | kind = "string address"; | |
9233 | ||
8325cc63 | 9234 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
9235 | { |
9236 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
9237 | ||
9238 | if (!type.bitfield.baseindex | |
9239 | || ((!i.mem_operands != !intel_syntax) | |
9240 | && current_templates->end[-1].operand_types[1] | |
9241 | .bitfield.baseindex)) | |
9242 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
9243 | expected_reg = hash_find (reg_hash, |
9244 | di_si[addr_mode][type.bitfield.esseg]); | |
9245 | ||
fc0763e6 JB |
9246 | } |
9247 | else | |
be05d201 | 9248 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 9249 | |
be05d201 L |
9250 | if (i.base_reg != expected_reg |
9251 | || i.index_reg | |
fc0763e6 | 9252 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 9253 | { |
be05d201 L |
9254 | /* The second memory operand must have the same size as |
9255 | the first one. */ | |
9256 | if (i.mem_operands | |
9257 | && i.base_reg | |
9258 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 9259 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 9260 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
9261 | ? i.base_reg->reg_type.bitfield.dword |
9262 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
9263 | goto bad_address; |
9264 | ||
fc0763e6 JB |
9265 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
9266 | operand_string, | |
9267 | intel_syntax ? '[' : '(', | |
9268 | register_prefix, | |
be05d201 | 9269 | expected_reg->reg_name, |
fc0763e6 | 9270 | intel_syntax ? ']' : ')'); |
be05d201 | 9271 | return 1; |
fc0763e6 | 9272 | } |
be05d201 L |
9273 | else |
9274 | return 1; | |
9275 | ||
9276 | bad_address: | |
9277 | as_bad (_("`%s' is not a valid %s expression"), | |
9278 | operand_string, kind); | |
9279 | return 0; | |
3e73aa7c JH |
9280 | } |
9281 | else | |
9282 | { | |
be05d201 L |
9283 | if (addr_mode != CODE_16BIT) |
9284 | { | |
9285 | /* 32-bit/64-bit checks. */ | |
9286 | if ((i.base_reg | |
9287 | && (addr_mode == CODE_64BIT | |
dc821c5f JB |
9288 | ? !i.base_reg->reg_type.bitfield.qword |
9289 | : !i.base_reg->reg_type.bitfield.dword) | |
be05d201 L |
9290 | && (i.index_reg |
9291 | || (i.base_reg->reg_num | |
9292 | != (addr_mode == CODE_64BIT ? RegRip : RegEip)))) | |
9293 | || (i.index_reg | |
1b54b8d7 JB |
9294 | && !i.index_reg->reg_type.bitfield.xmmword |
9295 | && !i.index_reg->reg_type.bitfield.ymmword | |
9296 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 9297 | && ((addr_mode == CODE_64BIT |
dc821c5f | 9298 | ? !(i.index_reg->reg_type.bitfield.qword |
be05d201 | 9299 | || i.index_reg->reg_num == RegRiz) |
dc821c5f | 9300 | : !(i.index_reg->reg_type.bitfield.dword |
be05d201 L |
9301 | || i.index_reg->reg_num == RegEiz)) |
9302 | || !i.index_reg->reg_type.bitfield.baseindex))) | |
9303 | goto bad_address; | |
8178be5b JB |
9304 | |
9305 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
9306 | if (current_templates->start->base_opcode == 0xf30f1b | |
9307 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
9308 | { | |
9309 | /* They cannot use RIP-relative addressing. */ | |
9310 | if (i.base_reg && i.base_reg->reg_num == RegRip) | |
9311 | { | |
9312 | as_bad (_("`%s' cannot be used here"), operand_string); | |
9313 | return 0; | |
9314 | } | |
9315 | ||
9316 | /* bndldx and bndstx ignore their scale factor. */ | |
9317 | if (current_templates->start->base_opcode != 0xf30f1b | |
9318 | && i.log2_scale_factor) | |
9319 | as_warn (_("register scaling is being ignored here")); | |
9320 | } | |
be05d201 L |
9321 | } |
9322 | else | |
3e73aa7c | 9323 | { |
be05d201 | 9324 | /* 16-bit checks. */ |
3e73aa7c | 9325 | if ((i.base_reg |
dc821c5f | 9326 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 9327 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 9328 | || (i.index_reg |
dc821c5f | 9329 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 9330 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
9331 | || !(i.base_reg |
9332 | && i.base_reg->reg_num < 6 | |
9333 | && i.index_reg->reg_num >= 6 | |
9334 | && i.log2_scale_factor == 0)))) | |
be05d201 | 9335 | goto bad_address; |
3e73aa7c JH |
9336 | } |
9337 | } | |
be05d201 | 9338 | return 1; |
24eab124 | 9339 | } |
252b5132 | 9340 | |
43234a1e L |
9341 | /* Handle vector immediates. */ |
9342 | ||
9343 | static int | |
9344 | RC_SAE_immediate (const char *imm_start) | |
9345 | { | |
9346 | unsigned int match_found, j; | |
9347 | const char *pstr = imm_start; | |
9348 | expressionS *exp; | |
9349 | ||
9350 | if (*pstr != '{') | |
9351 | return 0; | |
9352 | ||
9353 | pstr++; | |
9354 | match_found = 0; | |
9355 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
9356 | { | |
9357 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
9358 | { | |
9359 | if (!i.rounding) | |
9360 | { | |
9361 | rc_op.type = RC_NamesTable[j].type; | |
9362 | rc_op.operand = this_operand; | |
9363 | i.rounding = &rc_op; | |
9364 | } | |
9365 | else | |
9366 | { | |
9367 | as_bad (_("duplicated `%s'"), imm_start); | |
9368 | return 0; | |
9369 | } | |
9370 | pstr += RC_NamesTable[j].len; | |
9371 | match_found = 1; | |
9372 | break; | |
9373 | } | |
9374 | } | |
9375 | if (!match_found) | |
9376 | return 0; | |
9377 | ||
9378 | if (*pstr++ != '}') | |
9379 | { | |
9380 | as_bad (_("Missing '}': '%s'"), imm_start); | |
9381 | return 0; | |
9382 | } | |
9383 | /* RC/SAE immediate string should contain nothing more. */; | |
9384 | if (*pstr != 0) | |
9385 | { | |
9386 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
9387 | return 0; | |
9388 | } | |
9389 | ||
9390 | exp = &im_expressions[i.imm_operands++]; | |
9391 | i.op[this_operand].imms = exp; | |
9392 | ||
9393 | exp->X_op = O_constant; | |
9394 | exp->X_add_number = 0; | |
9395 | exp->X_add_symbol = (symbolS *) 0; | |
9396 | exp->X_op_symbol = (symbolS *) 0; | |
9397 | ||
9398 | i.types[this_operand].bitfield.imm8 = 1; | |
9399 | return 1; | |
9400 | } | |
9401 | ||
8325cc63 JB |
9402 | /* Only string instructions can have a second memory operand, so |
9403 | reduce current_templates to just those if it contains any. */ | |
9404 | static int | |
9405 | maybe_adjust_templates (void) | |
9406 | { | |
9407 | const insn_template *t; | |
9408 | ||
9409 | gas_assert (i.mem_operands == 1); | |
9410 | ||
9411 | for (t = current_templates->start; t < current_templates->end; ++t) | |
9412 | if (t->opcode_modifier.isstring) | |
9413 | break; | |
9414 | ||
9415 | if (t < current_templates->end) | |
9416 | { | |
9417 | static templates aux_templates; | |
9418 | bfd_boolean recheck; | |
9419 | ||
9420 | aux_templates.start = t; | |
9421 | for (; t < current_templates->end; ++t) | |
9422 | if (!t->opcode_modifier.isstring) | |
9423 | break; | |
9424 | aux_templates.end = t; | |
9425 | ||
9426 | /* Determine whether to re-check the first memory operand. */ | |
9427 | recheck = (aux_templates.start != current_templates->start | |
9428 | || t != current_templates->end); | |
9429 | ||
9430 | current_templates = &aux_templates; | |
9431 | ||
9432 | if (recheck) | |
9433 | { | |
9434 | i.mem_operands = 0; | |
9435 | if (i.memop1_string != NULL | |
9436 | && i386_index_check (i.memop1_string) == 0) | |
9437 | return 0; | |
9438 | i.mem_operands = 1; | |
9439 | } | |
9440 | } | |
9441 | ||
9442 | return 1; | |
9443 | } | |
9444 | ||
fc0763e6 | 9445 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 9446 | on error. */ |
252b5132 | 9447 | |
252b5132 | 9448 | static int |
a7619375 | 9449 | i386_att_operand (char *operand_string) |
252b5132 | 9450 | { |
af6bdddf AM |
9451 | const reg_entry *r; |
9452 | char *end_op; | |
24eab124 | 9453 | char *op_string = operand_string; |
252b5132 | 9454 | |
24eab124 | 9455 | if (is_space_char (*op_string)) |
252b5132 RH |
9456 | ++op_string; |
9457 | ||
24eab124 | 9458 | /* We check for an absolute prefix (differentiating, |
47926f60 | 9459 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
9460 | if (*op_string == ABSOLUTE_PREFIX) |
9461 | { | |
9462 | ++op_string; | |
9463 | if (is_space_char (*op_string)) | |
9464 | ++op_string; | |
40fb9820 | 9465 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 9466 | } |
252b5132 | 9467 | |
47926f60 | 9468 | /* Check if operand is a register. */ |
4d1bb795 | 9469 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 9470 | { |
40fb9820 L |
9471 | i386_operand_type temp; |
9472 | ||
24eab124 AM |
9473 | /* Check for a segment override by searching for ':' after a |
9474 | segment register. */ | |
9475 | op_string = end_op; | |
9476 | if (is_space_char (*op_string)) | |
9477 | ++op_string; | |
40fb9820 L |
9478 | if (*op_string == ':' |
9479 | && (r->reg_type.bitfield.sreg2 | |
9480 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
9481 | { |
9482 | switch (r->reg_num) | |
9483 | { | |
9484 | case 0: | |
9485 | i.seg[i.mem_operands] = &es; | |
9486 | break; | |
9487 | case 1: | |
9488 | i.seg[i.mem_operands] = &cs; | |
9489 | break; | |
9490 | case 2: | |
9491 | i.seg[i.mem_operands] = &ss; | |
9492 | break; | |
9493 | case 3: | |
9494 | i.seg[i.mem_operands] = &ds; | |
9495 | break; | |
9496 | case 4: | |
9497 | i.seg[i.mem_operands] = &fs; | |
9498 | break; | |
9499 | case 5: | |
9500 | i.seg[i.mem_operands] = &gs; | |
9501 | break; | |
9502 | } | |
252b5132 | 9503 | |
24eab124 | 9504 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
9505 | ++op_string; |
9506 | if (is_space_char (*op_string)) | |
24eab124 | 9507 | ++op_string; |
252b5132 | 9508 | |
24eab124 AM |
9509 | if (!is_digit_char (*op_string) |
9510 | && !is_identifier_char (*op_string) | |
9511 | && *op_string != '(' | |
9512 | && *op_string != ABSOLUTE_PREFIX) | |
9513 | { | |
9514 | as_bad (_("bad memory operand `%s'"), op_string); | |
9515 | return 0; | |
9516 | } | |
47926f60 | 9517 | /* Handle case of %es:*foo. */ |
24eab124 AM |
9518 | if (*op_string == ABSOLUTE_PREFIX) |
9519 | { | |
9520 | ++op_string; | |
9521 | if (is_space_char (*op_string)) | |
9522 | ++op_string; | |
40fb9820 | 9523 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
9524 | } |
9525 | goto do_memory_reference; | |
9526 | } | |
43234a1e L |
9527 | |
9528 | /* Handle vector operations. */ | |
9529 | if (*op_string == '{') | |
9530 | { | |
9531 | op_string = check_VecOperations (op_string, NULL); | |
9532 | if (op_string == NULL) | |
9533 | return 0; | |
9534 | } | |
9535 | ||
24eab124 AM |
9536 | if (*op_string) |
9537 | { | |
d0b47220 | 9538 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
9539 | return 0; |
9540 | } | |
40fb9820 L |
9541 | temp = r->reg_type; |
9542 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
9543 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9544 | temp); | |
7d5e4556 | 9545 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 9546 | i.op[this_operand].regs = r; |
24eab124 AM |
9547 | i.reg_operands++; |
9548 | } | |
af6bdddf AM |
9549 | else if (*op_string == REGISTER_PREFIX) |
9550 | { | |
9551 | as_bad (_("bad register name `%s'"), op_string); | |
9552 | return 0; | |
9553 | } | |
24eab124 | 9554 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 9555 | { |
24eab124 | 9556 | ++op_string; |
40fb9820 | 9557 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 9558 | { |
d0b47220 | 9559 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
9560 | return 0; |
9561 | } | |
9562 | if (!i386_immediate (op_string)) | |
9563 | return 0; | |
9564 | } | |
43234a1e L |
9565 | else if (RC_SAE_immediate (operand_string)) |
9566 | { | |
9567 | /* If it is a RC or SAE immediate, do nothing. */ | |
9568 | ; | |
9569 | } | |
24eab124 AM |
9570 | else if (is_digit_char (*op_string) |
9571 | || is_identifier_char (*op_string) | |
d02603dc | 9572 | || *op_string == '"' |
e5cb08ac | 9573 | || *op_string == '(') |
24eab124 | 9574 | { |
47926f60 | 9575 | /* This is a memory reference of some sort. */ |
af6bdddf | 9576 | char *base_string; |
252b5132 | 9577 | |
47926f60 | 9578 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
9579 | char *displacement_string_start; |
9580 | char *displacement_string_end; | |
43234a1e | 9581 | char *vop_start; |
252b5132 | 9582 | |
24eab124 | 9583 | do_memory_reference: |
8325cc63 JB |
9584 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
9585 | return 0; | |
24eab124 | 9586 | if ((i.mem_operands == 1 |
40fb9820 | 9587 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
9588 | || i.mem_operands == 2) |
9589 | { | |
9590 | as_bad (_("too many memory references for `%s'"), | |
9591 | current_templates->start->name); | |
9592 | return 0; | |
9593 | } | |
252b5132 | 9594 | |
24eab124 AM |
9595 | /* Check for base index form. We detect the base index form by |
9596 | looking for an ')' at the end of the operand, searching | |
9597 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
9598 | after the '('. */ | |
af6bdddf | 9599 | base_string = op_string + strlen (op_string); |
c3332e24 | 9600 | |
43234a1e L |
9601 | /* Handle vector operations. */ |
9602 | vop_start = strchr (op_string, '{'); | |
9603 | if (vop_start && vop_start < base_string) | |
9604 | { | |
9605 | if (check_VecOperations (vop_start, base_string) == NULL) | |
9606 | return 0; | |
9607 | base_string = vop_start; | |
9608 | } | |
9609 | ||
af6bdddf AM |
9610 | --base_string; |
9611 | if (is_space_char (*base_string)) | |
9612 | --base_string; | |
252b5132 | 9613 | |
47926f60 | 9614 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
9615 | displacement_string_start = op_string; |
9616 | displacement_string_end = base_string + 1; | |
252b5132 | 9617 | |
24eab124 AM |
9618 | if (*base_string == ')') |
9619 | { | |
af6bdddf | 9620 | char *temp_string; |
24eab124 AM |
9621 | unsigned int parens_balanced = 1; |
9622 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 9623 | equal, so this loop will not be infinite. */ |
24eab124 AM |
9624 | do |
9625 | { | |
9626 | base_string--; | |
9627 | if (*base_string == ')') | |
9628 | parens_balanced++; | |
9629 | if (*base_string == '(') | |
9630 | parens_balanced--; | |
9631 | } | |
9632 | while (parens_balanced); | |
c3332e24 | 9633 | |
af6bdddf | 9634 | temp_string = base_string; |
c3332e24 | 9635 | |
24eab124 | 9636 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
9637 | ++base_string; |
9638 | if (is_space_char (*base_string)) | |
24eab124 | 9639 | ++base_string; |
252b5132 | 9640 | |
af6bdddf | 9641 | if (*base_string == ',' |
4eed87de AM |
9642 | || ((i.base_reg = parse_register (base_string, &end_op)) |
9643 | != NULL)) | |
252b5132 | 9644 | { |
af6bdddf | 9645 | displacement_string_end = temp_string; |
252b5132 | 9646 | |
40fb9820 | 9647 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 9648 | |
af6bdddf | 9649 | if (i.base_reg) |
24eab124 | 9650 | { |
24eab124 AM |
9651 | base_string = end_op; |
9652 | if (is_space_char (*base_string)) | |
9653 | ++base_string; | |
af6bdddf AM |
9654 | } |
9655 | ||
9656 | /* There may be an index reg or scale factor here. */ | |
9657 | if (*base_string == ',') | |
9658 | { | |
9659 | ++base_string; | |
9660 | if (is_space_char (*base_string)) | |
9661 | ++base_string; | |
9662 | ||
4eed87de AM |
9663 | if ((i.index_reg = parse_register (base_string, &end_op)) |
9664 | != NULL) | |
24eab124 | 9665 | { |
af6bdddf | 9666 | base_string = end_op; |
24eab124 AM |
9667 | if (is_space_char (*base_string)) |
9668 | ++base_string; | |
af6bdddf AM |
9669 | if (*base_string == ',') |
9670 | { | |
9671 | ++base_string; | |
9672 | if (is_space_char (*base_string)) | |
9673 | ++base_string; | |
9674 | } | |
e5cb08ac | 9675 | else if (*base_string != ')') |
af6bdddf | 9676 | { |
4eed87de AM |
9677 | as_bad (_("expecting `,' or `)' " |
9678 | "after index register in `%s'"), | |
af6bdddf AM |
9679 | operand_string); |
9680 | return 0; | |
9681 | } | |
24eab124 | 9682 | } |
af6bdddf | 9683 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 9684 | { |
f76bf5e0 L |
9685 | end_op = strchr (base_string, ','); |
9686 | if (end_op) | |
9687 | *end_op = '\0'; | |
af6bdddf | 9688 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
9689 | return 0; |
9690 | } | |
252b5132 | 9691 | |
47926f60 | 9692 | /* Check for scale factor. */ |
551c1ca1 | 9693 | if (*base_string != ')') |
af6bdddf | 9694 | { |
551c1ca1 AM |
9695 | char *end_scale = i386_scale (base_string); |
9696 | ||
9697 | if (!end_scale) | |
af6bdddf | 9698 | return 0; |
24eab124 | 9699 | |
551c1ca1 | 9700 | base_string = end_scale; |
af6bdddf AM |
9701 | if (is_space_char (*base_string)) |
9702 | ++base_string; | |
9703 | if (*base_string != ')') | |
9704 | { | |
4eed87de AM |
9705 | as_bad (_("expecting `)' " |
9706 | "after scale factor in `%s'"), | |
af6bdddf AM |
9707 | operand_string); |
9708 | return 0; | |
9709 | } | |
9710 | } | |
9711 | else if (!i.index_reg) | |
24eab124 | 9712 | { |
4eed87de AM |
9713 | as_bad (_("expecting index register or scale factor " |
9714 | "after `,'; got '%c'"), | |
af6bdddf | 9715 | *base_string); |
24eab124 AM |
9716 | return 0; |
9717 | } | |
9718 | } | |
af6bdddf | 9719 | else if (*base_string != ')') |
24eab124 | 9720 | { |
4eed87de AM |
9721 | as_bad (_("expecting `,' or `)' " |
9722 | "after base register in `%s'"), | |
af6bdddf | 9723 | operand_string); |
24eab124 AM |
9724 | return 0; |
9725 | } | |
c3332e24 | 9726 | } |
af6bdddf | 9727 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 9728 | { |
f76bf5e0 L |
9729 | end_op = strchr (base_string, ','); |
9730 | if (end_op) | |
9731 | *end_op = '\0'; | |
af6bdddf | 9732 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 9733 | return 0; |
c3332e24 | 9734 | } |
24eab124 AM |
9735 | } |
9736 | ||
9737 | /* If there's an expression beginning the operand, parse it, | |
9738 | assuming displacement_string_start and | |
9739 | displacement_string_end are meaningful. */ | |
9740 | if (displacement_string_start != displacement_string_end) | |
9741 | { | |
9742 | if (!i386_displacement (displacement_string_start, | |
9743 | displacement_string_end)) | |
9744 | return 0; | |
9745 | } | |
9746 | ||
9747 | /* Special case for (%dx) while doing input/output op. */ | |
9748 | if (i.base_reg | |
2fb5be8d | 9749 | && i.base_reg->reg_type.bitfield.inoutportreg |
24eab124 AM |
9750 | && i.index_reg == 0 |
9751 | && i.log2_scale_factor == 0 | |
9752 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 9753 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 9754 | { |
2fb5be8d | 9755 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
9756 | return 1; |
9757 | } | |
9758 | ||
eecb386c AM |
9759 | if (i386_index_check (operand_string) == 0) |
9760 | return 0; | |
5c07affc | 9761 | i.types[this_operand].bitfield.mem = 1; |
8325cc63 JB |
9762 | if (i.mem_operands == 0) |
9763 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
9764 | i.mem_operands++; |
9765 | } | |
9766 | else | |
ce8a8b2f AM |
9767 | { |
9768 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
9769 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
9770 | output_invalid (*op_string), | |
9771 | this_operand + 1, | |
9772 | op_string); | |
9773 | return 0; | |
9774 | } | |
47926f60 | 9775 | return 1; /* Normal return. */ |
252b5132 RH |
9776 | } |
9777 | \f | |
fa94de6b RM |
9778 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
9779 | that an rs_machine_dependent frag may reach. */ | |
9780 | ||
9781 | unsigned int | |
9782 | i386_frag_max_var (fragS *frag) | |
9783 | { | |
9784 | /* The only relaxable frags are for jumps. | |
9785 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
9786 | gas_assert (frag->fr_type == rs_machine_dependent); | |
9787 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
9788 | } | |
9789 | ||
b084df0b L |
9790 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9791 | static int | |
8dcea932 | 9792 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
9793 | { |
9794 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
9795 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
9796 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
9797 | return 0; | |
9798 | ||
9799 | if (!S_IS_EXTERNAL (fr_symbol)) | |
9800 | /* Symbol may be weak or local. */ | |
9801 | return !S_IS_WEAK (fr_symbol); | |
9802 | ||
8dcea932 L |
9803 | /* Global symbols with non-default visibility can't be preempted. */ |
9804 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
9805 | return 1; | |
9806 | ||
9807 | if (fr_var != NO_RELOC) | |
9808 | switch ((enum bfd_reloc_code_real) fr_var) | |
9809 | { | |
9810 | case BFD_RELOC_386_PLT32: | |
9811 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 9812 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
9813 | return 0; |
9814 | default: | |
9815 | abort (); | |
9816 | } | |
9817 | ||
b084df0b L |
9818 | /* Global symbols with default visibility in a shared library may be |
9819 | preempted by another definition. */ | |
8dcea932 | 9820 | return !shared; |
b084df0b L |
9821 | } |
9822 | #endif | |
9823 | ||
ee7fcc42 AM |
9824 | /* md_estimate_size_before_relax() |
9825 | ||
9826 | Called just before relax() for rs_machine_dependent frags. The x86 | |
9827 | assembler uses these frags to handle variable size jump | |
9828 | instructions. | |
9829 | ||
9830 | Any symbol that is now undefined will not become defined. | |
9831 | Return the correct fr_subtype in the frag. | |
9832 | Return the initial "guess for variable size of frag" to caller. | |
9833 | The guess is actually the growth beyond the fixed part. Whatever | |
9834 | we do to grow the fixed or variable part contributes to our | |
9835 | returned value. */ | |
9836 | ||
252b5132 | 9837 | int |
7016a5d5 | 9838 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 9839 | { |
252b5132 | 9840 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
9841 | check for un-relaxable symbols. On an ELF system, we can't relax |
9842 | an externally visible symbol, because it may be overridden by a | |
9843 | shared library. */ | |
9844 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 9845 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9846 | || (IS_ELF |
8dcea932 L |
9847 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
9848 | fragP->fr_var)) | |
fbeb56a4 DK |
9849 | #endif |
9850 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 9851 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 9852 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
9853 | #endif |
9854 | ) | |
252b5132 | 9855 | { |
b98ef147 AM |
9856 | /* Symbol is undefined in this segment, or we need to keep a |
9857 | reloc so that weak symbols can be overridden. */ | |
9858 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 9859 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
9860 | unsigned char *opcode; |
9861 | int old_fr_fix; | |
f6af82bd | 9862 | |
ee7fcc42 | 9863 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 9864 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 9865 | else if (size == 2) |
f6af82bd | 9866 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
9867 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9868 | else if (need_plt32_p (fragP->fr_symbol)) | |
9869 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
9870 | #endif | |
f6af82bd AM |
9871 | else |
9872 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 9873 | |
ee7fcc42 AM |
9874 | old_fr_fix = fragP->fr_fix; |
9875 | opcode = (unsigned char *) fragP->fr_opcode; | |
9876 | ||
fddf5b5b | 9877 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 9878 | { |
fddf5b5b AM |
9879 | case UNCOND_JUMP: |
9880 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 9881 | opcode[0] = 0xe9; |
252b5132 | 9882 | fragP->fr_fix += size; |
062cd5e7 AS |
9883 | fix_new (fragP, old_fr_fix, size, |
9884 | fragP->fr_symbol, | |
9885 | fragP->fr_offset, 1, | |
9886 | reloc_type); | |
252b5132 RH |
9887 | break; |
9888 | ||
fddf5b5b | 9889 | case COND_JUMP86: |
412167cb AM |
9890 | if (size == 2 |
9891 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
9892 | { |
9893 | /* Negate the condition, and branch past an | |
9894 | unconditional jump. */ | |
9895 | opcode[0] ^= 1; | |
9896 | opcode[1] = 3; | |
9897 | /* Insert an unconditional jump. */ | |
9898 | opcode[2] = 0xe9; | |
9899 | /* We added two extra opcode bytes, and have a two byte | |
9900 | offset. */ | |
9901 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
9902 | fix_new (fragP, old_fr_fix + 2, 2, |
9903 | fragP->fr_symbol, | |
9904 | fragP->fr_offset, 1, | |
9905 | reloc_type); | |
fddf5b5b AM |
9906 | break; |
9907 | } | |
9908 | /* Fall through. */ | |
9909 | ||
9910 | case COND_JUMP: | |
412167cb AM |
9911 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
9912 | { | |
3e02c1cc AM |
9913 | fixS *fixP; |
9914 | ||
412167cb | 9915 | fragP->fr_fix += 1; |
3e02c1cc AM |
9916 | fixP = fix_new (fragP, old_fr_fix, 1, |
9917 | fragP->fr_symbol, | |
9918 | fragP->fr_offset, 1, | |
9919 | BFD_RELOC_8_PCREL); | |
9920 | fixP->fx_signed = 1; | |
412167cb AM |
9921 | break; |
9922 | } | |
93c2a809 | 9923 | |
24eab124 | 9924 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 9925 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 9926 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 9927 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
9928 | /* We've added an opcode byte. */ |
9929 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
9930 | fix_new (fragP, old_fr_fix + 1, size, |
9931 | fragP->fr_symbol, | |
9932 | fragP->fr_offset, 1, | |
9933 | reloc_type); | |
252b5132 | 9934 | break; |
fddf5b5b AM |
9935 | |
9936 | default: | |
9937 | BAD_CASE (fragP->fr_subtype); | |
9938 | break; | |
252b5132 RH |
9939 | } |
9940 | frag_wane (fragP); | |
ee7fcc42 | 9941 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 9942 | } |
93c2a809 | 9943 | |
93c2a809 AM |
9944 | /* Guess size depending on current relax state. Initially the relax |
9945 | state will correspond to a short jump and we return 1, because | |
9946 | the variable part of the frag (the branch offset) is one byte | |
9947 | long. However, we can relax a section more than once and in that | |
9948 | case we must either set fr_subtype back to the unrelaxed state, | |
9949 | or return the value for the appropriate branch. */ | |
9950 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
9951 | } |
9952 | ||
47926f60 KH |
9953 | /* Called after relax() is finished. |
9954 | ||
9955 | In: Address of frag. | |
9956 | fr_type == rs_machine_dependent. | |
9957 | fr_subtype is what the address relaxed to. | |
9958 | ||
9959 | Out: Any fixSs and constants are set up. | |
9960 | Caller will turn frag into a ".space 0". */ | |
9961 | ||
252b5132 | 9962 | void |
7016a5d5 TG |
9963 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
9964 | fragS *fragP) | |
252b5132 | 9965 | { |
29b0f896 | 9966 | unsigned char *opcode; |
252b5132 | 9967 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
9968 | offsetT target_address; |
9969 | offsetT opcode_address; | |
252b5132 | 9970 | unsigned int extension = 0; |
847f7ad4 | 9971 | offsetT displacement_from_opcode_start; |
252b5132 RH |
9972 | |
9973 | opcode = (unsigned char *) fragP->fr_opcode; | |
9974 | ||
47926f60 | 9975 | /* Address we want to reach in file space. */ |
252b5132 | 9976 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 9977 | |
47926f60 | 9978 | /* Address opcode resides at in file space. */ |
252b5132 RH |
9979 | opcode_address = fragP->fr_address + fragP->fr_fix; |
9980 | ||
47926f60 | 9981 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
9982 | displacement_from_opcode_start = target_address - opcode_address; |
9983 | ||
fddf5b5b | 9984 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 9985 | { |
47926f60 KH |
9986 | /* Don't have to change opcode. */ |
9987 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 9988 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
9989 | } |
9990 | else | |
9991 | { | |
9992 | if (no_cond_jump_promotion | |
9993 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
9994 | as_warn_where (fragP->fr_file, fragP->fr_line, |
9995 | _("long jump required")); | |
252b5132 | 9996 | |
fddf5b5b AM |
9997 | switch (fragP->fr_subtype) |
9998 | { | |
9999 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
10000 | extension = 4; /* 1 opcode + 4 displacement */ | |
10001 | opcode[0] = 0xe9; | |
10002 | where_to_put_displacement = &opcode[1]; | |
10003 | break; | |
252b5132 | 10004 | |
fddf5b5b AM |
10005 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
10006 | extension = 2; /* 1 opcode + 2 displacement */ | |
10007 | opcode[0] = 0xe9; | |
10008 | where_to_put_displacement = &opcode[1]; | |
10009 | break; | |
252b5132 | 10010 | |
fddf5b5b AM |
10011 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
10012 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
10013 | extension = 5; /* 2 opcode + 4 displacement */ | |
10014 | opcode[1] = opcode[0] + 0x10; | |
10015 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10016 | where_to_put_displacement = &opcode[2]; | |
10017 | break; | |
252b5132 | 10018 | |
fddf5b5b AM |
10019 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
10020 | extension = 3; /* 2 opcode + 2 displacement */ | |
10021 | opcode[1] = opcode[0] + 0x10; | |
10022 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10023 | where_to_put_displacement = &opcode[2]; | |
10024 | break; | |
252b5132 | 10025 | |
fddf5b5b AM |
10026 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
10027 | extension = 4; | |
10028 | opcode[0] ^= 1; | |
10029 | opcode[1] = 3; | |
10030 | opcode[2] = 0xe9; | |
10031 | where_to_put_displacement = &opcode[3]; | |
10032 | break; | |
10033 | ||
10034 | default: | |
10035 | BAD_CASE (fragP->fr_subtype); | |
10036 | break; | |
10037 | } | |
252b5132 | 10038 | } |
fddf5b5b | 10039 | |
7b81dfbb AJ |
10040 | /* If size if less then four we are sure that the operand fits, |
10041 | but if it's 4, then it could be that the displacement is larger | |
10042 | then -/+ 2GB. */ | |
10043 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
10044 | && object_64bit | |
10045 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
10046 | + ((addressT) 1 << 31)) |
10047 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
10048 | { |
10049 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10050 | _("jump target out of range")); | |
10051 | /* Make us emit 0. */ | |
10052 | displacement_from_opcode_start = extension; | |
10053 | } | |
47926f60 | 10054 | /* Now put displacement after opcode. */ |
252b5132 RH |
10055 | md_number_to_chars ((char *) where_to_put_displacement, |
10056 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 10057 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
10058 | fragP->fr_fix += extension; |
10059 | } | |
10060 | \f | |
7016a5d5 | 10061 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
10062 | by our caller that we have all the info we need to fix it up. |
10063 | ||
7016a5d5 TG |
10064 | Parameter valP is the pointer to the value of the bits. |
10065 | ||
252b5132 RH |
10066 | On the 386, immediates, displacements, and data pointers are all in |
10067 | the same (little-endian) format, so we don't need to care about which | |
10068 | we are handling. */ | |
10069 | ||
94f592af | 10070 | void |
7016a5d5 | 10071 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10072 | { |
94f592af | 10073 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 10074 | valueT value = *valP; |
252b5132 | 10075 | |
f86103b7 | 10076 | #if !defined (TE_Mach) |
93382f6d AM |
10077 | if (fixP->fx_pcrel) |
10078 | { | |
10079 | switch (fixP->fx_r_type) | |
10080 | { | |
5865bb77 ILT |
10081 | default: |
10082 | break; | |
10083 | ||
d6ab8113 JB |
10084 | case BFD_RELOC_64: |
10085 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
10086 | break; | |
93382f6d | 10087 | case BFD_RELOC_32: |
ae8887b5 | 10088 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
10089 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
10090 | break; | |
10091 | case BFD_RELOC_16: | |
10092 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
10093 | break; | |
10094 | case BFD_RELOC_8: | |
10095 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
10096 | break; | |
10097 | } | |
10098 | } | |
252b5132 | 10099 | |
a161fe53 | 10100 | if (fixP->fx_addsy != NULL |
31312f95 | 10101 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 10102 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 10103 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 10104 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 10105 | && !use_rela_relocations) |
252b5132 | 10106 | { |
31312f95 AM |
10107 | /* This is a hack. There should be a better way to handle this. |
10108 | This covers for the fact that bfd_install_relocation will | |
10109 | subtract the current location (for partial_inplace, PC relative | |
10110 | relocations); see more below. */ | |
252b5132 | 10111 | #ifndef OBJ_AOUT |
718ddfc0 | 10112 | if (IS_ELF |
252b5132 RH |
10113 | #ifdef TE_PE |
10114 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
10115 | #endif | |
10116 | ) | |
10117 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10118 | #endif | |
10119 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 10120 | if (IS_ELF) |
252b5132 | 10121 | { |
6539b54b | 10122 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 10123 | |
6539b54b | 10124 | if ((sym_seg == seg |
2f66722d | 10125 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 10126 | && sym_seg != absolute_section)) |
af65af87 | 10127 | && !generic_force_reloc (fixP)) |
2f66722d AM |
10128 | { |
10129 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
10130 | bfd_install_relocation subtracts them out again. I think |
10131 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
10132 | it. FIXME. */ |
10133 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10134 | } | |
252b5132 RH |
10135 | } |
10136 | #endif | |
10137 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
10138 | /* For some reason, the PE format does not store a |
10139 | section address offset for a PC relative symbol. */ | |
10140 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 10141 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
10142 | value += md_pcrel_from (fixP); |
10143 | #endif | |
10144 | } | |
fbeb56a4 | 10145 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
10146 | if (fixP->fx_addsy != NULL |
10147 | && S_IS_WEAK (fixP->fx_addsy) | |
10148 | /* PR 16858: Do not modify weak function references. */ | |
10149 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 10150 | { |
296a8689 NC |
10151 | #if !defined (TE_PEP) |
10152 | /* For x86 PE weak function symbols are neither PC-relative | |
10153 | nor do they set S_IS_FUNCTION. So the only reliable way | |
10154 | to detect them is to check the flags of their containing | |
10155 | section. */ | |
10156 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
10157 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
10158 | ; | |
10159 | else | |
10160 | #endif | |
fbeb56a4 DK |
10161 | value -= S_GET_VALUE (fixP->fx_addsy); |
10162 | } | |
10163 | #endif | |
252b5132 RH |
10164 | |
10165 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 10166 | and we must not disappoint it. */ |
252b5132 | 10167 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10168 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
10169 | switch (fixP->fx_r_type) |
10170 | { | |
10171 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 10172 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
10173 | /* Make the jump instruction point to the address of the operand. At |
10174 | runtime we merely add the offset to the actual PLT entry. */ | |
10175 | value = -4; | |
10176 | break; | |
31312f95 | 10177 | |
13ae64f3 JJ |
10178 | case BFD_RELOC_386_TLS_GD: |
10179 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 10180 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
10181 | case BFD_RELOC_386_TLS_IE: |
10182 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 10183 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
10184 | case BFD_RELOC_X86_64_TLSGD: |
10185 | case BFD_RELOC_X86_64_TLSLD: | |
10186 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 10187 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
10188 | value = 0; /* Fully resolved at runtime. No addend. */ |
10189 | /* Fallthrough */ | |
10190 | case BFD_RELOC_386_TLS_LE: | |
10191 | case BFD_RELOC_386_TLS_LDO_32: | |
10192 | case BFD_RELOC_386_TLS_LE_32: | |
10193 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10194 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 10195 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 10196 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
10197 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
10198 | break; | |
10199 | ||
67a4f2b7 AO |
10200 | case BFD_RELOC_386_TLS_DESC_CALL: |
10201 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
10202 | value = 0; /* Fully resolved at runtime. No addend. */ | |
10203 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10204 | fixP->fx_done = 0; | |
10205 | return; | |
10206 | ||
47926f60 KH |
10207 | case BFD_RELOC_VTABLE_INHERIT: |
10208 | case BFD_RELOC_VTABLE_ENTRY: | |
10209 | fixP->fx_done = 0; | |
94f592af | 10210 | return; |
47926f60 KH |
10211 | |
10212 | default: | |
10213 | break; | |
10214 | } | |
10215 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 10216 | *valP = value; |
f86103b7 | 10217 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 10218 | |
3e73aa7c | 10219 | /* Are we finished with this relocation now? */ |
c6682705 | 10220 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 10221 | fixP->fx_done = 1; |
fbeb56a4 DK |
10222 | #if defined (OBJ_COFF) && defined (TE_PE) |
10223 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
10224 | { | |
10225 | fixP->fx_done = 0; | |
10226 | /* Remember value for tc_gen_reloc. */ | |
10227 | fixP->fx_addnumber = value; | |
10228 | /* Clear out the frag for now. */ | |
10229 | value = 0; | |
10230 | } | |
10231 | #endif | |
3e73aa7c JH |
10232 | else if (use_rela_relocations) |
10233 | { | |
10234 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
10235 | /* Remember value for tc_gen_reloc. */ |
10236 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
10237 | value = 0; |
10238 | } | |
f86103b7 | 10239 | |
94f592af | 10240 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 10241 | } |
252b5132 | 10242 | \f |
6d4af3c2 | 10243 | const char * |
499ac353 | 10244 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10245 | { |
499ac353 NC |
10246 | /* This outputs the LITTLENUMs in REVERSE order; |
10247 | in accord with the bigendian 386. */ | |
10248 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
10249 | } |
10250 | \f | |
2d545b82 | 10251 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 10252 | |
252b5132 | 10253 | static char * |
e3bb37b5 | 10254 | output_invalid (int c) |
252b5132 | 10255 | { |
3882b010 | 10256 | if (ISPRINT (c)) |
f9f21a03 L |
10257 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
10258 | "'%c'", c); | |
252b5132 | 10259 | else |
f9f21a03 | 10260 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 10261 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
10262 | return output_invalid_buf; |
10263 | } | |
10264 | ||
af6bdddf | 10265 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
10266 | |
10267 | static const reg_entry * | |
4d1bb795 | 10268 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 10269 | { |
af6bdddf AM |
10270 | char *s = reg_string; |
10271 | char *p; | |
252b5132 RH |
10272 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
10273 | const reg_entry *r; | |
10274 | ||
10275 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
10276 | if (*s == REGISTER_PREFIX) | |
10277 | ++s; | |
10278 | ||
10279 | if (is_space_char (*s)) | |
10280 | ++s; | |
10281 | ||
10282 | p = reg_name_given; | |
af6bdddf | 10283 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
10284 | { |
10285 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
10286 | return (const reg_entry *) NULL; |
10287 | s++; | |
252b5132 RH |
10288 | } |
10289 | ||
6588847e DN |
10290 | /* For naked regs, make sure that we are not dealing with an identifier. |
10291 | This prevents confusing an identifier like `eax_var' with register | |
10292 | `eax'. */ | |
10293 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
10294 | return (const reg_entry *) NULL; | |
10295 | ||
af6bdddf | 10296 | *end_op = s; |
252b5132 RH |
10297 | |
10298 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
10299 | ||
5f47d35b | 10300 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 10301 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 10302 | { |
0e0eea78 JB |
10303 | if (!cpu_arch_flags.bitfield.cpu8087 |
10304 | && !cpu_arch_flags.bitfield.cpu287 | |
10305 | && !cpu_arch_flags.bitfield.cpu387) | |
10306 | return (const reg_entry *) NULL; | |
10307 | ||
5f47d35b AM |
10308 | if (is_space_char (*s)) |
10309 | ++s; | |
10310 | if (*s == '(') | |
10311 | { | |
af6bdddf | 10312 | ++s; |
5f47d35b AM |
10313 | if (is_space_char (*s)) |
10314 | ++s; | |
10315 | if (*s >= '0' && *s <= '7') | |
10316 | { | |
db557034 | 10317 | int fpr = *s - '0'; |
af6bdddf | 10318 | ++s; |
5f47d35b AM |
10319 | if (is_space_char (*s)) |
10320 | ++s; | |
10321 | if (*s == ')') | |
10322 | { | |
10323 | *end_op = s + 1; | |
1e9cc1c2 | 10324 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
10325 | know (r); |
10326 | return r + fpr; | |
5f47d35b | 10327 | } |
5f47d35b | 10328 | } |
47926f60 | 10329 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
10330 | return (const reg_entry *) NULL; |
10331 | } | |
10332 | } | |
10333 | ||
a60de03c JB |
10334 | if (r == NULL || allow_pseudo_reg) |
10335 | return r; | |
10336 | ||
0dfbf9d7 | 10337 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
10338 | return (const reg_entry *) NULL; |
10339 | ||
dc821c5f | 10340 | if ((r->reg_type.bitfield.dword |
192dc9c6 JB |
10341 | || r->reg_type.bitfield.sreg3 |
10342 | || r->reg_type.bitfield.control | |
10343 | || r->reg_type.bitfield.debug | |
10344 | || r->reg_type.bitfield.test) | |
10345 | && !cpu_arch_flags.bitfield.cpui386) | |
10346 | return (const reg_entry *) NULL; | |
10347 | ||
6e041cf4 | 10348 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
10349 | return (const reg_entry *) NULL; |
10350 | ||
6e041cf4 JB |
10351 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
10352 | { | |
10353 | if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask) | |
10354 | return (const reg_entry *) NULL; | |
40f12533 | 10355 | |
6e041cf4 JB |
10356 | if (!cpu_arch_flags.bitfield.cpuavx) |
10357 | { | |
10358 | if (r->reg_type.bitfield.ymmword) | |
10359 | return (const reg_entry *) NULL; | |
1848e567 | 10360 | |
6e041cf4 JB |
10361 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
10362 | return (const reg_entry *) NULL; | |
10363 | } | |
10364 | } | |
43234a1e | 10365 | |
1adf7f56 JB |
10366 | if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx) |
10367 | return (const reg_entry *) NULL; | |
10368 | ||
db51cc60 | 10369 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 10370 | if (!allow_index_reg |
db51cc60 L |
10371 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
10372 | return (const reg_entry *) NULL; | |
10373 | ||
1d3f8286 JB |
10374 | /* Upper 16 vector registers are only available with VREX in 64bit |
10375 | mode, and require EVEX encoding. */ | |
10376 | if (r->reg_flags & RegVRex) | |
43234a1e L |
10377 | { |
10378 | if (!cpu_arch_flags.bitfield.cpuvrex | |
10379 | || flag_code != CODE_64BIT) | |
10380 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
10381 | |
10382 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
10383 | } |
10384 | ||
4787f4a5 JB |
10385 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
10386 | && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control) | |
1ae00879 | 10387 | && flag_code != CODE_64BIT) |
20f0a1fc | 10388 | return (const reg_entry *) NULL; |
1ae00879 | 10389 | |
b7240065 JB |
10390 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
10391 | return (const reg_entry *) NULL; | |
10392 | ||
252b5132 RH |
10393 | return r; |
10394 | } | |
4d1bb795 JB |
10395 | |
10396 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
10397 | ||
10398 | static const reg_entry * | |
10399 | parse_register (char *reg_string, char **end_op) | |
10400 | { | |
10401 | const reg_entry *r; | |
10402 | ||
10403 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
10404 | r = parse_real_register (reg_string, end_op); | |
10405 | else | |
10406 | r = NULL; | |
10407 | if (!r) | |
10408 | { | |
10409 | char *save = input_line_pointer; | |
10410 | char c; | |
10411 | symbolS *symbolP; | |
10412 | ||
10413 | input_line_pointer = reg_string; | |
d02603dc | 10414 | c = get_symbol_name (®_string); |
4d1bb795 JB |
10415 | symbolP = symbol_find (reg_string); |
10416 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
10417 | { | |
10418 | const expressionS *e = symbol_get_value_expression (symbolP); | |
10419 | ||
0398aac5 | 10420 | know (e->X_op == O_register); |
4eed87de | 10421 | know (e->X_add_number >= 0 |
c3fe08fa | 10422 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 10423 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 10424 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 10425 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
10426 | *end_op = input_line_pointer; |
10427 | } | |
10428 | *input_line_pointer = c; | |
10429 | input_line_pointer = save; | |
10430 | } | |
10431 | return r; | |
10432 | } | |
10433 | ||
10434 | int | |
10435 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
10436 | { | |
10437 | const reg_entry *r; | |
10438 | char *end = input_line_pointer; | |
10439 | ||
10440 | *end = *nextcharP; | |
10441 | r = parse_register (name, &input_line_pointer); | |
10442 | if (r && end <= input_line_pointer) | |
10443 | { | |
10444 | *nextcharP = *input_line_pointer; | |
10445 | *input_line_pointer = 0; | |
10446 | e->X_op = O_register; | |
10447 | e->X_add_number = r - i386_regtab; | |
10448 | return 1; | |
10449 | } | |
10450 | input_line_pointer = end; | |
10451 | *end = 0; | |
ee86248c | 10452 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
10453 | } |
10454 | ||
10455 | void | |
10456 | md_operand (expressionS *e) | |
10457 | { | |
ee86248c JB |
10458 | char *end; |
10459 | const reg_entry *r; | |
4d1bb795 | 10460 | |
ee86248c JB |
10461 | switch (*input_line_pointer) |
10462 | { | |
10463 | case REGISTER_PREFIX: | |
10464 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
10465 | if (r) |
10466 | { | |
10467 | e->X_op = O_register; | |
10468 | e->X_add_number = r - i386_regtab; | |
10469 | input_line_pointer = end; | |
10470 | } | |
ee86248c JB |
10471 | break; |
10472 | ||
10473 | case '[': | |
9c2799c2 | 10474 | gas_assert (intel_syntax); |
ee86248c JB |
10475 | end = input_line_pointer++; |
10476 | expression (e); | |
10477 | if (*input_line_pointer == ']') | |
10478 | { | |
10479 | ++input_line_pointer; | |
10480 | e->X_op_symbol = make_expr_symbol (e); | |
10481 | e->X_add_symbol = NULL; | |
10482 | e->X_add_number = 0; | |
10483 | e->X_op = O_index; | |
10484 | } | |
10485 | else | |
10486 | { | |
10487 | e->X_op = O_absent; | |
10488 | input_line_pointer = end; | |
10489 | } | |
10490 | break; | |
4d1bb795 JB |
10491 | } |
10492 | } | |
10493 | ||
252b5132 | 10494 | \f |
4cc782b5 | 10495 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 10496 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 10497 | #else |
b6f8c7c4 | 10498 | const char *md_shortopts = "qnO::"; |
252b5132 | 10499 | #endif |
6e0b89ee | 10500 | |
3e73aa7c | 10501 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
10502 | #define OPTION_64 (OPTION_MD_BASE + 1) |
10503 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
10504 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
10505 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
10506 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
10507 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
10508 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
10509 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 10510 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 10511 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 10512 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
10513 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
10514 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
10515 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 10516 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
10517 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
10518 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 10519 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 10520 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 10521 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 10522 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
10523 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
10524 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 10525 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b3b91714 | 10526 | |
99ad8390 NC |
10527 | struct option md_longopts[] = |
10528 | { | |
3e73aa7c | 10529 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 10530 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10531 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 10532 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
10533 | #endif |
10534 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 10535 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 10536 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
6e0b89ee | 10537 | #endif |
b3b91714 | 10538 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
10539 | {"march", required_argument, NULL, OPTION_MARCH}, |
10540 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
10541 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
10542 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
10543 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
10544 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 10545 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 10546 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 10547 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 10548 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
7e8b059b | 10549 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
10550 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
10551 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
10552 | # if defined (TE_PE) || defined (TE_PEP) |
10553 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
10554 | #endif | |
d1982f93 | 10555 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 10556 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 10557 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 10558 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
10559 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
10560 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
10561 | {NULL, no_argument, NULL, 0} |
10562 | }; | |
10563 | size_t md_longopts_size = sizeof (md_longopts); | |
10564 | ||
10565 | int | |
17b9d67d | 10566 | md_parse_option (int c, const char *arg) |
252b5132 | 10567 | { |
91d6fa6a | 10568 | unsigned int j; |
293f5f65 | 10569 | char *arch, *next, *saved; |
9103f4f4 | 10570 | |
252b5132 RH |
10571 | switch (c) |
10572 | { | |
12b55ccc L |
10573 | case 'n': |
10574 | optimize_align_code = 0; | |
10575 | break; | |
10576 | ||
a38cf1db AM |
10577 | case 'q': |
10578 | quiet_warnings = 1; | |
252b5132 RH |
10579 | break; |
10580 | ||
10581 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
10582 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
10583 | should be emitted or not. FIXME: Not implemented. */ | |
10584 | case 'Q': | |
252b5132 RH |
10585 | break; |
10586 | ||
10587 | /* -V: SVR4 argument to print version ID. */ | |
10588 | case 'V': | |
10589 | print_version_id (); | |
10590 | break; | |
10591 | ||
a38cf1db AM |
10592 | /* -k: Ignore for FreeBSD compatibility. */ |
10593 | case 'k': | |
252b5132 | 10594 | break; |
4cc782b5 ILT |
10595 | |
10596 | case 's': | |
10597 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 10598 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 10599 | break; |
8dcea932 L |
10600 | |
10601 | case OPTION_MSHARED: | |
10602 | shared = 1; | |
10603 | break; | |
99ad8390 | 10604 | #endif |
321098a5 | 10605 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10606 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
10607 | case OPTION_64: |
10608 | { | |
10609 | const char **list, **l; | |
10610 | ||
3e73aa7c JH |
10611 | list = bfd_target_list (); |
10612 | for (l = list; *l != NULL; l++) | |
8620418b | 10613 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
10614 | || strcmp (*l, "coff-x86-64") == 0 |
10615 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
10616 | || strcmp (*l, "pei-x86-64") == 0 |
10617 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
10618 | { |
10619 | default_arch = "x86_64"; | |
10620 | break; | |
10621 | } | |
3e73aa7c | 10622 | if (*l == NULL) |
2b5d6a91 | 10623 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
10624 | free (list); |
10625 | } | |
10626 | break; | |
10627 | #endif | |
252b5132 | 10628 | |
351f65ca | 10629 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 10630 | case OPTION_X32: |
351f65ca L |
10631 | if (IS_ELF) |
10632 | { | |
10633 | const char **list, **l; | |
10634 | ||
10635 | list = bfd_target_list (); | |
10636 | for (l = list; *l != NULL; l++) | |
10637 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
10638 | { | |
10639 | default_arch = "x86_64:32"; | |
10640 | break; | |
10641 | } | |
10642 | if (*l == NULL) | |
2b5d6a91 | 10643 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
10644 | free (list); |
10645 | } | |
10646 | else | |
10647 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
10648 | break; | |
10649 | #endif | |
10650 | ||
6e0b89ee AM |
10651 | case OPTION_32: |
10652 | default_arch = "i386"; | |
10653 | break; | |
10654 | ||
b3b91714 AM |
10655 | case OPTION_DIVIDE: |
10656 | #ifdef SVR4_COMMENT_CHARS | |
10657 | { | |
10658 | char *n, *t; | |
10659 | const char *s; | |
10660 | ||
add39d23 | 10661 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
10662 | t = n; |
10663 | for (s = i386_comment_chars; *s != '\0'; s++) | |
10664 | if (*s != '/') | |
10665 | *t++ = *s; | |
10666 | *t = '\0'; | |
10667 | i386_comment_chars = n; | |
10668 | } | |
10669 | #endif | |
10670 | break; | |
10671 | ||
9103f4f4 | 10672 | case OPTION_MARCH: |
293f5f65 L |
10673 | saved = xstrdup (arg); |
10674 | arch = saved; | |
10675 | /* Allow -march=+nosse. */ | |
10676 | if (*arch == '+') | |
10677 | arch++; | |
6305a203 | 10678 | do |
9103f4f4 | 10679 | { |
6305a203 | 10680 | if (*arch == '.') |
2b5d6a91 | 10681 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10682 | next = strchr (arch, '+'); |
10683 | if (next) | |
10684 | *next++ = '\0'; | |
91d6fa6a | 10685 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10686 | { |
91d6fa6a | 10687 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 10688 | { |
6305a203 | 10689 | /* Processor. */ |
1ded5609 JB |
10690 | if (! cpu_arch[j].flags.bitfield.cpui386) |
10691 | continue; | |
10692 | ||
91d6fa6a | 10693 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 10694 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
10695 | cpu_arch_flags = cpu_arch[j].flags; |
10696 | cpu_arch_isa = cpu_arch[j].type; | |
10697 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
10698 | if (!cpu_arch_tune_set) |
10699 | { | |
10700 | cpu_arch_tune = cpu_arch_isa; | |
10701 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10702 | } | |
10703 | break; | |
10704 | } | |
91d6fa6a NC |
10705 | else if (*cpu_arch [j].name == '.' |
10706 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 10707 | { |
33eaf5de | 10708 | /* ISA extension. */ |
6305a203 | 10709 | i386_cpu_flags flags; |
309d3373 | 10710 | |
293f5f65 L |
10711 | flags = cpu_flags_or (cpu_arch_flags, |
10712 | cpu_arch[j].flags); | |
81486035 | 10713 | |
5b64d091 | 10714 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
10715 | { |
10716 | if (cpu_sub_arch_name) | |
10717 | { | |
10718 | char *name = cpu_sub_arch_name; | |
10719 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 10720 | cpu_arch[j].name, |
1bf57e9f | 10721 | (const char *) NULL); |
6305a203 L |
10722 | free (name); |
10723 | } | |
10724 | else | |
91d6fa6a | 10725 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 10726 | cpu_arch_flags = flags; |
a586129e | 10727 | cpu_arch_isa_flags = flags; |
6305a203 | 10728 | } |
0089dace L |
10729 | else |
10730 | cpu_arch_isa_flags | |
10731 | = cpu_flags_or (cpu_arch_isa_flags, | |
10732 | cpu_arch[j].flags); | |
6305a203 | 10733 | break; |
ccc9c027 | 10734 | } |
9103f4f4 | 10735 | } |
6305a203 | 10736 | |
293f5f65 L |
10737 | if (j >= ARRAY_SIZE (cpu_arch)) |
10738 | { | |
33eaf5de | 10739 | /* Disable an ISA extension. */ |
293f5f65 L |
10740 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
10741 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
10742 | { | |
10743 | i386_cpu_flags flags; | |
10744 | ||
10745 | flags = cpu_flags_and_not (cpu_arch_flags, | |
10746 | cpu_noarch[j].flags); | |
10747 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
10748 | { | |
10749 | if (cpu_sub_arch_name) | |
10750 | { | |
10751 | char *name = cpu_sub_arch_name; | |
10752 | cpu_sub_arch_name = concat (arch, | |
10753 | (const char *) NULL); | |
10754 | free (name); | |
10755 | } | |
10756 | else | |
10757 | cpu_sub_arch_name = xstrdup (arch); | |
10758 | cpu_arch_flags = flags; | |
10759 | cpu_arch_isa_flags = flags; | |
10760 | } | |
10761 | break; | |
10762 | } | |
10763 | ||
10764 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
10765 | j = ARRAY_SIZE (cpu_arch); | |
10766 | } | |
10767 | ||
91d6fa6a | 10768 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10769 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10770 | |
10771 | arch = next; | |
9103f4f4 | 10772 | } |
293f5f65 L |
10773 | while (next != NULL); |
10774 | free (saved); | |
9103f4f4 L |
10775 | break; |
10776 | ||
10777 | case OPTION_MTUNE: | |
10778 | if (*arg == '.') | |
2b5d6a91 | 10779 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 10780 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10781 | { |
91d6fa6a | 10782 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 10783 | { |
ccc9c027 | 10784 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
10785 | cpu_arch_tune = cpu_arch [j].type; |
10786 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
10787 | break; |
10788 | } | |
10789 | } | |
91d6fa6a | 10790 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10791 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
10792 | break; |
10793 | ||
1efbbeb4 L |
10794 | case OPTION_MMNEMONIC: |
10795 | if (strcasecmp (arg, "att") == 0) | |
10796 | intel_mnemonic = 0; | |
10797 | else if (strcasecmp (arg, "intel") == 0) | |
10798 | intel_mnemonic = 1; | |
10799 | else | |
2b5d6a91 | 10800 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
10801 | break; |
10802 | ||
10803 | case OPTION_MSYNTAX: | |
10804 | if (strcasecmp (arg, "att") == 0) | |
10805 | intel_syntax = 0; | |
10806 | else if (strcasecmp (arg, "intel") == 0) | |
10807 | intel_syntax = 1; | |
10808 | else | |
2b5d6a91 | 10809 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
10810 | break; |
10811 | ||
10812 | case OPTION_MINDEX_REG: | |
10813 | allow_index_reg = 1; | |
10814 | break; | |
10815 | ||
10816 | case OPTION_MNAKED_REG: | |
10817 | allow_naked_reg = 1; | |
10818 | break; | |
10819 | ||
c0f3af97 L |
10820 | case OPTION_MSSE2AVX: |
10821 | sse2avx = 1; | |
10822 | break; | |
10823 | ||
daf50ae7 L |
10824 | case OPTION_MSSE_CHECK: |
10825 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 10826 | sse_check = check_error; |
daf50ae7 | 10827 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 10828 | sse_check = check_warning; |
daf50ae7 | 10829 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 10830 | sse_check = check_none; |
daf50ae7 | 10831 | else |
2b5d6a91 | 10832 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
10833 | break; |
10834 | ||
7bab8ab5 JB |
10835 | case OPTION_MOPERAND_CHECK: |
10836 | if (strcasecmp (arg, "error") == 0) | |
10837 | operand_check = check_error; | |
10838 | else if (strcasecmp (arg, "warning") == 0) | |
10839 | operand_check = check_warning; | |
10840 | else if (strcasecmp (arg, "none") == 0) | |
10841 | operand_check = check_none; | |
10842 | else | |
10843 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
10844 | break; | |
10845 | ||
539f890d L |
10846 | case OPTION_MAVXSCALAR: |
10847 | if (strcasecmp (arg, "128") == 0) | |
10848 | avxscalar = vex128; | |
10849 | else if (strcasecmp (arg, "256") == 0) | |
10850 | avxscalar = vex256; | |
10851 | else | |
2b5d6a91 | 10852 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
10853 | break; |
10854 | ||
7e8b059b L |
10855 | case OPTION_MADD_BND_PREFIX: |
10856 | add_bnd_prefix = 1; | |
10857 | break; | |
10858 | ||
43234a1e L |
10859 | case OPTION_MEVEXLIG: |
10860 | if (strcmp (arg, "128") == 0) | |
10861 | evexlig = evexl128; | |
10862 | else if (strcmp (arg, "256") == 0) | |
10863 | evexlig = evexl256; | |
10864 | else if (strcmp (arg, "512") == 0) | |
10865 | evexlig = evexl512; | |
10866 | else | |
10867 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
10868 | break; | |
10869 | ||
d3d3c6db IT |
10870 | case OPTION_MEVEXRCIG: |
10871 | if (strcmp (arg, "rne") == 0) | |
10872 | evexrcig = rne; | |
10873 | else if (strcmp (arg, "rd") == 0) | |
10874 | evexrcig = rd; | |
10875 | else if (strcmp (arg, "ru") == 0) | |
10876 | evexrcig = ru; | |
10877 | else if (strcmp (arg, "rz") == 0) | |
10878 | evexrcig = rz; | |
10879 | else | |
10880 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
10881 | break; | |
10882 | ||
43234a1e L |
10883 | case OPTION_MEVEXWIG: |
10884 | if (strcmp (arg, "0") == 0) | |
10885 | evexwig = evexw0; | |
10886 | else if (strcmp (arg, "1") == 0) | |
10887 | evexwig = evexw1; | |
10888 | else | |
10889 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
10890 | break; | |
10891 | ||
167ad85b TG |
10892 | # if defined (TE_PE) || defined (TE_PEP) |
10893 | case OPTION_MBIG_OBJ: | |
10894 | use_big_obj = 1; | |
10895 | break; | |
10896 | #endif | |
10897 | ||
d1982f93 | 10898 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
10899 | if (strcasecmp (arg, "yes") == 0) |
10900 | omit_lock_prefix = 1; | |
10901 | else if (strcasecmp (arg, "no") == 0) | |
10902 | omit_lock_prefix = 0; | |
10903 | else | |
10904 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
10905 | break; | |
10906 | ||
e4e00185 AS |
10907 | case OPTION_MFENCE_AS_LOCK_ADD: |
10908 | if (strcasecmp (arg, "yes") == 0) | |
10909 | avoid_fence = 1; | |
10910 | else if (strcasecmp (arg, "no") == 0) | |
10911 | avoid_fence = 0; | |
10912 | else | |
10913 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
10914 | break; | |
10915 | ||
0cb4071e L |
10916 | case OPTION_MRELAX_RELOCATIONS: |
10917 | if (strcasecmp (arg, "yes") == 0) | |
10918 | generate_relax_relocations = 1; | |
10919 | else if (strcasecmp (arg, "no") == 0) | |
10920 | generate_relax_relocations = 0; | |
10921 | else | |
10922 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
10923 | break; | |
10924 | ||
5db04b09 | 10925 | case OPTION_MAMD64: |
e89c5eaa | 10926 | intel64 = 0; |
5db04b09 L |
10927 | break; |
10928 | ||
10929 | case OPTION_MINTEL64: | |
e89c5eaa | 10930 | intel64 = 1; |
5db04b09 L |
10931 | break; |
10932 | ||
b6f8c7c4 L |
10933 | case 'O': |
10934 | if (arg == NULL) | |
10935 | { | |
10936 | optimize = 1; | |
10937 | /* Turn off -Os. */ | |
10938 | optimize_for_space = 0; | |
10939 | } | |
10940 | else if (*arg == 's') | |
10941 | { | |
10942 | optimize_for_space = 1; | |
10943 | /* Turn on all encoding optimizations. */ | |
10944 | optimize = -1; | |
10945 | } | |
10946 | else | |
10947 | { | |
10948 | optimize = atoi (arg); | |
10949 | /* Turn off -Os. */ | |
10950 | optimize_for_space = 0; | |
10951 | } | |
10952 | break; | |
10953 | ||
252b5132 RH |
10954 | default: |
10955 | return 0; | |
10956 | } | |
10957 | return 1; | |
10958 | } | |
10959 | ||
8a2c8fef L |
10960 | #define MESSAGE_TEMPLATE \ |
10961 | " " | |
10962 | ||
293f5f65 L |
10963 | static char * |
10964 | output_message (FILE *stream, char *p, char *message, char *start, | |
10965 | int *left_p, const char *name, int len) | |
10966 | { | |
10967 | int size = sizeof (MESSAGE_TEMPLATE); | |
10968 | int left = *left_p; | |
10969 | ||
10970 | /* Reserve 2 spaces for ", " or ",\0" */ | |
10971 | left -= len + 2; | |
10972 | ||
10973 | /* Check if there is any room. */ | |
10974 | if (left >= 0) | |
10975 | { | |
10976 | if (p != start) | |
10977 | { | |
10978 | *p++ = ','; | |
10979 | *p++ = ' '; | |
10980 | } | |
10981 | p = mempcpy (p, name, len); | |
10982 | } | |
10983 | else | |
10984 | { | |
10985 | /* Output the current message now and start a new one. */ | |
10986 | *p++ = ','; | |
10987 | *p = '\0'; | |
10988 | fprintf (stream, "%s\n", message); | |
10989 | p = start; | |
10990 | left = size - (start - message) - len - 2; | |
10991 | ||
10992 | gas_assert (left >= 0); | |
10993 | ||
10994 | p = mempcpy (p, name, len); | |
10995 | } | |
10996 | ||
10997 | *left_p = left; | |
10998 | return p; | |
10999 | } | |
11000 | ||
8a2c8fef | 11001 | static void |
1ded5609 | 11002 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
11003 | { |
11004 | static char message[] = MESSAGE_TEMPLATE; | |
11005 | char *start = message + 27; | |
11006 | char *p; | |
11007 | int size = sizeof (MESSAGE_TEMPLATE); | |
11008 | int left; | |
11009 | const char *name; | |
11010 | int len; | |
11011 | unsigned int j; | |
11012 | ||
11013 | p = start; | |
11014 | left = size - (start - message); | |
11015 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
11016 | { | |
11017 | /* Should it be skipped? */ | |
11018 | if (cpu_arch [j].skip) | |
11019 | continue; | |
11020 | ||
11021 | name = cpu_arch [j].name; | |
11022 | len = cpu_arch [j].len; | |
11023 | if (*name == '.') | |
11024 | { | |
11025 | /* It is an extension. Skip if we aren't asked to show it. */ | |
11026 | if (ext) | |
11027 | { | |
11028 | name++; | |
11029 | len--; | |
11030 | } | |
11031 | else | |
11032 | continue; | |
11033 | } | |
11034 | else if (ext) | |
11035 | { | |
11036 | /* It is an processor. Skip if we show only extension. */ | |
11037 | continue; | |
11038 | } | |
1ded5609 JB |
11039 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
11040 | { | |
11041 | /* It is an impossible processor - skip. */ | |
11042 | continue; | |
11043 | } | |
8a2c8fef | 11044 | |
293f5f65 | 11045 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
11046 | } |
11047 | ||
293f5f65 L |
11048 | /* Display disabled extensions. */ |
11049 | if (ext) | |
11050 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
11051 | { | |
11052 | name = cpu_noarch [j].name; | |
11053 | len = cpu_noarch [j].len; | |
11054 | p = output_message (stream, p, message, start, &left, name, | |
11055 | len); | |
11056 | } | |
11057 | ||
8a2c8fef L |
11058 | *p = '\0'; |
11059 | fprintf (stream, "%s\n", message); | |
11060 | } | |
11061 | ||
252b5132 | 11062 | void |
8a2c8fef | 11063 | md_show_usage (FILE *stream) |
252b5132 | 11064 | { |
4cc782b5 ILT |
11065 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11066 | fprintf (stream, _("\ | |
a38cf1db AM |
11067 | -Q ignored\n\ |
11068 | -V print assembler version number\n\ | |
b3b91714 AM |
11069 | -k ignored\n")); |
11070 | #endif | |
11071 | fprintf (stream, _("\ | |
12b55ccc | 11072 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
11073 | -q quieten some warnings\n")); |
11074 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11075 | fprintf (stream, _("\ | |
a38cf1db | 11076 | -s ignored\n")); |
b3b91714 | 11077 | #endif |
321098a5 L |
11078 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
11079 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 11080 | fprintf (stream, _("\ |
570561f7 | 11081 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 11082 | #endif |
b3b91714 AM |
11083 | #ifdef SVR4_COMMENT_CHARS |
11084 | fprintf (stream, _("\ | |
11085 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
11086 | #else |
11087 | fprintf (stream, _("\ | |
b3b91714 | 11088 | --divide ignored\n")); |
4cc782b5 | 11089 | #endif |
9103f4f4 | 11090 | fprintf (stream, _("\ |
6305a203 | 11091 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 11092 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 11093 | show_arch (stream, 0, 1); |
8a2c8fef L |
11094 | fprintf (stream, _("\ |
11095 | EXTENSION is combination of:\n")); | |
1ded5609 | 11096 | show_arch (stream, 1, 0); |
6305a203 | 11097 | fprintf (stream, _("\ |
8a2c8fef | 11098 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 11099 | show_arch (stream, 0, 0); |
ba104c83 | 11100 | fprintf (stream, _("\ |
c0f3af97 L |
11101 | -msse2avx encode SSE instructions with VEX prefix\n")); |
11102 | fprintf (stream, _("\ | |
daf50ae7 L |
11103 | -msse-check=[none|error|warning]\n\ |
11104 | check SSE instructions\n")); | |
11105 | fprintf (stream, _("\ | |
7bab8ab5 JB |
11106 | -moperand-check=[none|error|warning]\n\ |
11107 | check operand combinations for validity\n")); | |
11108 | fprintf (stream, _("\ | |
539f890d L |
11109 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
11110 | length\n")); | |
11111 | fprintf (stream, _("\ | |
43234a1e L |
11112 | -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ |
11113 | length\n")); | |
11114 | fprintf (stream, _("\ | |
11115 | -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ | |
11116 | for EVEX.W bit ignored instructions\n")); | |
11117 | fprintf (stream, _("\ | |
d3d3c6db IT |
11118 | -mevexrcig=[rne|rd|ru|rz]\n\ |
11119 | encode EVEX instructions with specific EVEX.RC value\n\ | |
11120 | for SAE-only ignored instructions\n")); | |
11121 | fprintf (stream, _("\ | |
ba104c83 L |
11122 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
11123 | fprintf (stream, _("\ | |
11124 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
11125 | fprintf (stream, _("\ | |
11126 | -mindex-reg support pseudo index registers\n")); | |
11127 | fprintf (stream, _("\ | |
11128 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
11129 | fprintf (stream, _("\ | |
7e8b059b | 11130 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
8dcea932 L |
11131 | fprintf (stream, _("\ |
11132 | -mshared disable branch optimization for shared code\n")); | |
167ad85b TG |
11133 | # if defined (TE_PE) || defined (TE_PEP) |
11134 | fprintf (stream, _("\ | |
11135 | -mbig-obj generate big object files\n")); | |
11136 | #endif | |
d022bddd IT |
11137 | fprintf (stream, _("\ |
11138 | -momit-lock-prefix=[no|yes]\n\ | |
11139 | strip all lock prefixes\n")); | |
5db04b09 | 11140 | fprintf (stream, _("\ |
e4e00185 AS |
11141 | -mfence-as-lock-add=[no|yes]\n\ |
11142 | encode lfence, mfence and sfence as\n\ | |
11143 | lock addl $0x0, (%%{re}sp)\n")); | |
11144 | fprintf (stream, _("\ | |
0cb4071e L |
11145 | -mrelax-relocations=[no|yes]\n\ |
11146 | generate relax relocations\n")); | |
11147 | fprintf (stream, _("\ | |
5db04b09 L |
11148 | -mamd64 accept only AMD64 ISA\n")); |
11149 | fprintf (stream, _("\ | |
11150 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
11151 | } |
11152 | ||
3e73aa7c | 11153 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 11154 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 11155 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
11156 | |
11157 | /* Pick the target format to use. */ | |
11158 | ||
47926f60 | 11159 | const char * |
e3bb37b5 | 11160 | i386_target_format (void) |
252b5132 | 11161 | { |
351f65ca L |
11162 | if (!strncmp (default_arch, "x86_64", 6)) |
11163 | { | |
11164 | update_code_flag (CODE_64BIT, 1); | |
11165 | if (default_arch[6] == '\0') | |
7f56bc95 | 11166 | x86_elf_abi = X86_64_ABI; |
351f65ca | 11167 | else |
7f56bc95 | 11168 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 11169 | } |
3e73aa7c | 11170 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 11171 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
11172 | else if (!strcmp (default_arch, "iamcu")) |
11173 | { | |
11174 | update_code_flag (CODE_32BIT, 1); | |
11175 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
11176 | { | |
11177 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
11178 | cpu_arch_name = "iamcu"; | |
11179 | cpu_sub_arch_name = NULL; | |
11180 | cpu_arch_flags = iamcu_flags; | |
11181 | cpu_arch_isa = PROCESSOR_IAMCU; | |
11182 | cpu_arch_isa_flags = iamcu_flags; | |
11183 | if (!cpu_arch_tune_set) | |
11184 | { | |
11185 | cpu_arch_tune = cpu_arch_isa; | |
11186 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11187 | } | |
11188 | } | |
8d471ec1 | 11189 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
11190 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
11191 | cpu_arch_name); | |
11192 | } | |
3e73aa7c | 11193 | else |
2b5d6a91 | 11194 | as_fatal (_("unknown architecture")); |
89507696 JB |
11195 | |
11196 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
11197 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11198 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
11199 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11200 | ||
252b5132 RH |
11201 | switch (OUTPUT_FLAVOR) |
11202 | { | |
9384f2ff | 11203 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 11204 | case bfd_target_aout_flavour: |
47926f60 | 11205 | return AOUT_TARGET_FORMAT; |
4c63da97 | 11206 | #endif |
9384f2ff AM |
11207 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
11208 | # if defined (TE_PE) || defined (TE_PEP) | |
11209 | case bfd_target_coff_flavour: | |
167ad85b TG |
11210 | if (flag_code == CODE_64BIT) |
11211 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
11212 | else | |
11213 | return "pe-i386"; | |
9384f2ff | 11214 | # elif defined (TE_GO32) |
0561d57c JK |
11215 | case bfd_target_coff_flavour: |
11216 | return "coff-go32"; | |
9384f2ff | 11217 | # else |
252b5132 RH |
11218 | case bfd_target_coff_flavour: |
11219 | return "coff-i386"; | |
9384f2ff | 11220 | # endif |
4c63da97 | 11221 | #endif |
3e73aa7c | 11222 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 11223 | case bfd_target_elf_flavour: |
3e73aa7c | 11224 | { |
351f65ca L |
11225 | const char *format; |
11226 | ||
11227 | switch (x86_elf_abi) | |
4fa24527 | 11228 | { |
351f65ca L |
11229 | default: |
11230 | format = ELF_TARGET_FORMAT; | |
11231 | break; | |
7f56bc95 | 11232 | case X86_64_ABI: |
351f65ca | 11233 | use_rela_relocations = 1; |
4fa24527 | 11234 | object_64bit = 1; |
351f65ca L |
11235 | format = ELF_TARGET_FORMAT64; |
11236 | break; | |
7f56bc95 | 11237 | case X86_64_X32_ABI: |
4fa24527 | 11238 | use_rela_relocations = 1; |
351f65ca | 11239 | object_64bit = 1; |
862be3fb | 11240 | disallow_64bit_reloc = 1; |
351f65ca L |
11241 | format = ELF_TARGET_FORMAT32; |
11242 | break; | |
4fa24527 | 11243 | } |
3632d14b | 11244 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 11245 | { |
7f56bc95 | 11246 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
11247 | as_fatal (_("Intel L1OM is 64bit only")); |
11248 | return ELF_TARGET_L1OM_FORMAT; | |
11249 | } | |
b49f93f6 | 11250 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
11251 | { |
11252 | if (x86_elf_abi != X86_64_ABI) | |
11253 | as_fatal (_("Intel K1OM is 64bit only")); | |
11254 | return ELF_TARGET_K1OM_FORMAT; | |
11255 | } | |
81486035 L |
11256 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
11257 | { | |
11258 | if (x86_elf_abi != I386_ABI) | |
11259 | as_fatal (_("Intel MCU is 32bit only")); | |
11260 | return ELF_TARGET_IAMCU_FORMAT; | |
11261 | } | |
8a9036a4 | 11262 | else |
351f65ca | 11263 | return format; |
3e73aa7c | 11264 | } |
e57f8c65 TG |
11265 | #endif |
11266 | #if defined (OBJ_MACH_O) | |
11267 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
11268 | if (flag_code == CODE_64BIT) |
11269 | { | |
11270 | use_rela_relocations = 1; | |
11271 | object_64bit = 1; | |
11272 | return "mach-o-x86-64"; | |
11273 | } | |
11274 | else | |
11275 | return "mach-o-i386"; | |
4c63da97 | 11276 | #endif |
252b5132 RH |
11277 | default: |
11278 | abort (); | |
11279 | return NULL; | |
11280 | } | |
11281 | } | |
11282 | ||
47926f60 | 11283 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 11284 | \f |
252b5132 | 11285 | symbolS * |
7016a5d5 | 11286 | md_undefined_symbol (char *name) |
252b5132 | 11287 | { |
18dc2407 ILT |
11288 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
11289 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
11290 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
11291 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
11292 | { |
11293 | if (!GOT_symbol) | |
11294 | { | |
11295 | if (symbol_find (name)) | |
11296 | as_bad (_("GOT already in symbol table")); | |
11297 | GOT_symbol = symbol_new (name, undefined_section, | |
11298 | (valueT) 0, &zero_address_frag); | |
11299 | }; | |
11300 | return GOT_symbol; | |
11301 | } | |
252b5132 RH |
11302 | return 0; |
11303 | } | |
11304 | ||
11305 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 11306 | |
252b5132 | 11307 | valueT |
7016a5d5 | 11308 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 11309 | { |
4c63da97 AM |
11310 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
11311 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
11312 | { | |
11313 | /* For a.out, force the section size to be aligned. If we don't do | |
11314 | this, BFD will align it for us, but it will not write out the | |
11315 | final bytes of the section. This may be a bug in BFD, but it is | |
11316 | easier to fix it here since that is how the other a.out targets | |
11317 | work. */ | |
11318 | int align; | |
11319 | ||
11320 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 11321 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 11322 | } |
252b5132 RH |
11323 | #endif |
11324 | ||
11325 | return size; | |
11326 | } | |
11327 | ||
11328 | /* On the i386, PC-relative offsets are relative to the start of the | |
11329 | next instruction. That is, the address of the offset, plus its | |
11330 | size, since the offset is always the last part of the insn. */ | |
11331 | ||
11332 | long | |
e3bb37b5 | 11333 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
11334 | { |
11335 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
11336 | } | |
11337 | ||
11338 | #ifndef I386COFF | |
11339 | ||
11340 | static void | |
e3bb37b5 | 11341 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 11342 | { |
29b0f896 | 11343 | int temp; |
252b5132 | 11344 | |
8a75718c JB |
11345 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11346 | if (IS_ELF) | |
11347 | obj_elf_section_change_hook (); | |
11348 | #endif | |
252b5132 RH |
11349 | temp = get_absolute_expression (); |
11350 | subseg_set (bss_section, (subsegT) temp); | |
11351 | demand_empty_rest_of_line (); | |
11352 | } | |
11353 | ||
11354 | #endif | |
11355 | ||
252b5132 | 11356 | void |
e3bb37b5 | 11357 | i386_validate_fix (fixS *fixp) |
252b5132 | 11358 | { |
02a86693 | 11359 | if (fixp->fx_subsy) |
252b5132 | 11360 | { |
02a86693 | 11361 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 11362 | { |
02a86693 L |
11363 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
11364 | { | |
11365 | if (!object_64bit) | |
11366 | abort (); | |
11367 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11368 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
11369 | fixp->fx_r_type = (fixp->fx_tcbit |
11370 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
11371 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
11372 | else |
11373 | #endif | |
11374 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
11375 | } | |
d6ab8113 | 11376 | else |
02a86693 L |
11377 | { |
11378 | if (!object_64bit) | |
11379 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
11380 | else | |
11381 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
11382 | } | |
11383 | fixp->fx_subsy = 0; | |
23df1078 | 11384 | } |
252b5132 | 11385 | } |
02a86693 L |
11386 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11387 | else if (!object_64bit) | |
11388 | { | |
11389 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
11390 | && fixp->fx_tcbit2) | |
11391 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
11392 | } | |
11393 | #endif | |
252b5132 RH |
11394 | } |
11395 | ||
252b5132 | 11396 | arelent * |
7016a5d5 | 11397 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
11398 | { |
11399 | arelent *rel; | |
11400 | bfd_reloc_code_real_type code; | |
11401 | ||
11402 | switch (fixp->fx_r_type) | |
11403 | { | |
8ce3d284 | 11404 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
11405 | case BFD_RELOC_SIZE32: |
11406 | case BFD_RELOC_SIZE64: | |
11407 | if (S_IS_DEFINED (fixp->fx_addsy) | |
11408 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
11409 | { | |
11410 | /* Resolve size relocation against local symbol to size of | |
11411 | the symbol plus addend. */ | |
11412 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
11413 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
11414 | && !fits_in_unsigned_long (value)) | |
11415 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11416 | _("symbol size computation overflow")); | |
11417 | fixp->fx_addsy = NULL; | |
11418 | fixp->fx_subsy = NULL; | |
11419 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
11420 | return NULL; | |
11421 | } | |
8ce3d284 | 11422 | #endif |
1a0670f3 | 11423 | /* Fall through. */ |
8fd4256d | 11424 | |
3e73aa7c JH |
11425 | case BFD_RELOC_X86_64_PLT32: |
11426 | case BFD_RELOC_X86_64_GOT32: | |
11427 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11428 | case BFD_RELOC_X86_64_GOTPCRELX: |
11429 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
11430 | case BFD_RELOC_386_PLT32: |
11431 | case BFD_RELOC_386_GOT32: | |
02a86693 | 11432 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
11433 | case BFD_RELOC_386_GOTOFF: |
11434 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
11435 | case BFD_RELOC_386_TLS_GD: |
11436 | case BFD_RELOC_386_TLS_LDM: | |
11437 | case BFD_RELOC_386_TLS_LDO_32: | |
11438 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
11439 | case BFD_RELOC_386_TLS_IE: |
11440 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
11441 | case BFD_RELOC_386_TLS_LE_32: |
11442 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
11443 | case BFD_RELOC_386_TLS_GOTDESC: |
11444 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
11445 | case BFD_RELOC_X86_64_TLSGD: |
11446 | case BFD_RELOC_X86_64_TLSLD: | |
11447 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11448 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
11449 | case BFD_RELOC_X86_64_GOTTPOFF: |
11450 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
11451 | case BFD_RELOC_X86_64_TPOFF64: |
11452 | case BFD_RELOC_X86_64_GOTOFF64: | |
11453 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
11454 | case BFD_RELOC_X86_64_GOT64: |
11455 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11456 | case BFD_RELOC_X86_64_GOTPC64: | |
11457 | case BFD_RELOC_X86_64_GOTPLT64: | |
11458 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
11459 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11460 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
11461 | case BFD_RELOC_RVA: |
11462 | case BFD_RELOC_VTABLE_ENTRY: | |
11463 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
11464 | #ifdef TE_PE |
11465 | case BFD_RELOC_32_SECREL: | |
11466 | #endif | |
252b5132 RH |
11467 | code = fixp->fx_r_type; |
11468 | break; | |
dbbaec26 L |
11469 | case BFD_RELOC_X86_64_32S: |
11470 | if (!fixp->fx_pcrel) | |
11471 | { | |
11472 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
11473 | code = fixp->fx_r_type; | |
11474 | break; | |
11475 | } | |
1a0670f3 | 11476 | /* Fall through. */ |
252b5132 | 11477 | default: |
93382f6d | 11478 | if (fixp->fx_pcrel) |
252b5132 | 11479 | { |
93382f6d AM |
11480 | switch (fixp->fx_size) |
11481 | { | |
11482 | default: | |
b091f402 AM |
11483 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11484 | _("can not do %d byte pc-relative relocation"), | |
11485 | fixp->fx_size); | |
93382f6d AM |
11486 | code = BFD_RELOC_32_PCREL; |
11487 | break; | |
11488 | case 1: code = BFD_RELOC_8_PCREL; break; | |
11489 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 11490 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
11491 | #ifdef BFD64 |
11492 | case 8: code = BFD_RELOC_64_PCREL; break; | |
11493 | #endif | |
93382f6d AM |
11494 | } |
11495 | } | |
11496 | else | |
11497 | { | |
11498 | switch (fixp->fx_size) | |
11499 | { | |
11500 | default: | |
b091f402 AM |
11501 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11502 | _("can not do %d byte relocation"), | |
11503 | fixp->fx_size); | |
93382f6d AM |
11504 | code = BFD_RELOC_32; |
11505 | break; | |
11506 | case 1: code = BFD_RELOC_8; break; | |
11507 | case 2: code = BFD_RELOC_16; break; | |
11508 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 11509 | #ifdef BFD64 |
3e73aa7c | 11510 | case 8: code = BFD_RELOC_64; break; |
937149dd | 11511 | #endif |
93382f6d | 11512 | } |
252b5132 RH |
11513 | } |
11514 | break; | |
11515 | } | |
252b5132 | 11516 | |
d182319b JB |
11517 | if ((code == BFD_RELOC_32 |
11518 | || code == BFD_RELOC_32_PCREL | |
11519 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
11520 | && GOT_symbol |
11521 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 11522 | { |
4fa24527 | 11523 | if (!object_64bit) |
d6ab8113 JB |
11524 | code = BFD_RELOC_386_GOTPC; |
11525 | else | |
11526 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 11527 | } |
7b81dfbb AJ |
11528 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
11529 | && GOT_symbol | |
11530 | && fixp->fx_addsy == GOT_symbol) | |
11531 | { | |
11532 | code = BFD_RELOC_X86_64_GOTPC64; | |
11533 | } | |
252b5132 | 11534 | |
add39d23 TS |
11535 | rel = XNEW (arelent); |
11536 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 11537 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
11538 | |
11539 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 11540 | |
3e73aa7c JH |
11541 | if (!use_rela_relocations) |
11542 | { | |
11543 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
11544 | vtable entry to be used in the relocation's section offset. */ | |
11545 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11546 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
11547 | #if defined (OBJ_COFF) && defined (TE_PE) |
11548 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
11549 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
11550 | else | |
11551 | #endif | |
c6682705 | 11552 | rel->addend = 0; |
3e73aa7c JH |
11553 | } |
11554 | /* Use the rela in 64bit mode. */ | |
252b5132 | 11555 | else |
3e73aa7c | 11556 | { |
862be3fb L |
11557 | if (disallow_64bit_reloc) |
11558 | switch (code) | |
11559 | { | |
862be3fb L |
11560 | case BFD_RELOC_X86_64_DTPOFF64: |
11561 | case BFD_RELOC_X86_64_TPOFF64: | |
11562 | case BFD_RELOC_64_PCREL: | |
11563 | case BFD_RELOC_X86_64_GOTOFF64: | |
11564 | case BFD_RELOC_X86_64_GOT64: | |
11565 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11566 | case BFD_RELOC_X86_64_GOTPC64: | |
11567 | case BFD_RELOC_X86_64_GOTPLT64: | |
11568 | case BFD_RELOC_X86_64_PLTOFF64: | |
11569 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11570 | _("cannot represent relocation type %s in x32 mode"), | |
11571 | bfd_get_reloc_code_name (code)); | |
11572 | break; | |
11573 | default: | |
11574 | break; | |
11575 | } | |
11576 | ||
062cd5e7 AS |
11577 | if (!fixp->fx_pcrel) |
11578 | rel->addend = fixp->fx_offset; | |
11579 | else | |
11580 | switch (code) | |
11581 | { | |
11582 | case BFD_RELOC_X86_64_PLT32: | |
11583 | case BFD_RELOC_X86_64_GOT32: | |
11584 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11585 | case BFD_RELOC_X86_64_GOTPCRELX: |
11586 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
11587 | case BFD_RELOC_X86_64_TLSGD: |
11588 | case BFD_RELOC_X86_64_TLSLD: | |
11589 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
11590 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11591 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
11592 | rel->addend = fixp->fx_offset - fixp->fx_size; |
11593 | break; | |
11594 | default: | |
11595 | rel->addend = (section->vma | |
11596 | - fixp->fx_size | |
11597 | + fixp->fx_addnumber | |
11598 | + md_pcrel_from (fixp)); | |
11599 | break; | |
11600 | } | |
3e73aa7c JH |
11601 | } |
11602 | ||
252b5132 RH |
11603 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
11604 | if (rel->howto == NULL) | |
11605 | { | |
11606 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 11607 | _("cannot represent relocation type %s"), |
252b5132 RH |
11608 | bfd_get_reloc_code_name (code)); |
11609 | /* Set howto to a garbage value so that we can keep going. */ | |
11610 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 11611 | gas_assert (rel->howto != NULL); |
252b5132 RH |
11612 | } |
11613 | ||
11614 | return rel; | |
11615 | } | |
11616 | ||
ee86248c | 11617 | #include "tc-i386-intel.c" |
54cfded0 | 11618 | |
a60de03c JB |
11619 | void |
11620 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 11621 | { |
a60de03c JB |
11622 | int saved_naked_reg; |
11623 | char saved_register_dot; | |
54cfded0 | 11624 | |
a60de03c JB |
11625 | saved_naked_reg = allow_naked_reg; |
11626 | allow_naked_reg = 1; | |
11627 | saved_register_dot = register_chars['.']; | |
11628 | register_chars['.'] = '.'; | |
11629 | allow_pseudo_reg = 1; | |
11630 | expression_and_evaluate (exp); | |
11631 | allow_pseudo_reg = 0; | |
11632 | register_chars['.'] = saved_register_dot; | |
11633 | allow_naked_reg = saved_naked_reg; | |
11634 | ||
e96d56a1 | 11635 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 11636 | { |
a60de03c JB |
11637 | if ((addressT) exp->X_add_number < i386_regtab_size) |
11638 | { | |
11639 | exp->X_op = O_constant; | |
11640 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
11641 | .dw2_regnum[flag_code >> 1]; | |
11642 | } | |
11643 | else | |
11644 | exp->X_op = O_illegal; | |
54cfded0 | 11645 | } |
54cfded0 AM |
11646 | } |
11647 | ||
11648 | void | |
11649 | tc_x86_frame_initial_instructions (void) | |
11650 | { | |
a60de03c JB |
11651 | static unsigned int sp_regno[2]; |
11652 | ||
11653 | if (!sp_regno[flag_code >> 1]) | |
11654 | { | |
11655 | char *saved_input = input_line_pointer; | |
11656 | char sp[][4] = {"esp", "rsp"}; | |
11657 | expressionS exp; | |
a4447b93 | 11658 | |
a60de03c JB |
11659 | input_line_pointer = sp[flag_code >> 1]; |
11660 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 11661 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
11662 | sp_regno[flag_code >> 1] = exp.X_add_number; |
11663 | input_line_pointer = saved_input; | |
11664 | } | |
a4447b93 | 11665 | |
61ff971f L |
11666 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
11667 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 11668 | } |
d2b2c203 | 11669 | |
d7921315 L |
11670 | int |
11671 | x86_dwarf2_addr_size (void) | |
11672 | { | |
11673 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
11674 | if (x86_elf_abi == X86_64_X32_ABI) | |
11675 | return 4; | |
11676 | #endif | |
11677 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
11678 | } | |
11679 | ||
d2b2c203 DJ |
11680 | int |
11681 | i386_elf_section_type (const char *str, size_t len) | |
11682 | { | |
11683 | if (flag_code == CODE_64BIT | |
11684 | && len == sizeof ("unwind") - 1 | |
11685 | && strncmp (str, "unwind", 6) == 0) | |
11686 | return SHT_X86_64_UNWIND; | |
11687 | ||
11688 | return -1; | |
11689 | } | |
bb41ade5 | 11690 | |
ad5fec3b EB |
11691 | #ifdef TE_SOLARIS |
11692 | void | |
11693 | i386_solaris_fix_up_eh_frame (segT sec) | |
11694 | { | |
11695 | if (flag_code == CODE_64BIT) | |
11696 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
11697 | } | |
11698 | #endif | |
11699 | ||
bb41ade5 AM |
11700 | #ifdef TE_PE |
11701 | void | |
11702 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
11703 | { | |
91d6fa6a | 11704 | expressionS exp; |
bb41ade5 | 11705 | |
91d6fa6a NC |
11706 | exp.X_op = O_secrel; |
11707 | exp.X_add_symbol = symbol; | |
11708 | exp.X_add_number = 0; | |
11709 | emit_expr (&exp, size); | |
bb41ade5 AM |
11710 | } |
11711 | #endif | |
3b22753a L |
11712 | |
11713 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11714 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
11715 | ||
01e1a5bc | 11716 | bfd_vma |
6d4af3c2 | 11717 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
11718 | { |
11719 | if (flag_code == CODE_64BIT) | |
11720 | { | |
11721 | if (letter == 'l') | |
11722 | return SHF_X86_64_LARGE; | |
11723 | ||
8f3bae45 | 11724 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 11725 | } |
3b22753a | 11726 | else |
8f3bae45 | 11727 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
11728 | return -1; |
11729 | } | |
11730 | ||
01e1a5bc | 11731 | bfd_vma |
3b22753a L |
11732 | x86_64_section_word (char *str, size_t len) |
11733 | { | |
8620418b | 11734 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
11735 | return SHF_X86_64_LARGE; |
11736 | ||
11737 | return -1; | |
11738 | } | |
11739 | ||
11740 | static void | |
11741 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
11742 | { | |
11743 | if (flag_code != CODE_64BIT) | |
11744 | { | |
11745 | s_comm_internal (0, elf_common_parse); | |
11746 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
11747 | } | |
11748 | else | |
11749 | { | |
11750 | static segT lbss_section; | |
11751 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
11752 | asection *saved_bss_section = bss_section; | |
11753 | ||
11754 | if (lbss_section == NULL) | |
11755 | { | |
11756 | flagword applicable; | |
11757 | segT seg = now_seg; | |
11758 | subsegT subseg = now_subseg; | |
11759 | ||
11760 | /* The .lbss section is for local .largecomm symbols. */ | |
11761 | lbss_section = subseg_new (".lbss", 0); | |
11762 | applicable = bfd_applicable_section_flags (stdoutput); | |
11763 | bfd_set_section_flags (stdoutput, lbss_section, | |
11764 | applicable & SEC_ALLOC); | |
11765 | seg_info (lbss_section)->bss = 1; | |
11766 | ||
11767 | subseg_set (seg, subseg); | |
11768 | } | |
11769 | ||
11770 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
11771 | bss_section = lbss_section; | |
11772 | ||
11773 | s_comm_internal (0, elf_common_parse); | |
11774 | ||
11775 | elf_com_section_ptr = saved_com_section_ptr; | |
11776 | bss_section = saved_bss_section; | |
11777 | } | |
11778 | } | |
11779 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |