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Add AVX512IFMA instructions
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
4b95cf5c 2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
47926f60
KH		 521/* 1 for intel syntax,
522 0 if att syntax. */
523static int intel_syntax = 0;
252b5132 524
1efbbeb4
L		 525/* 1 for intel mnemonic,
526 0 if att mnemonic. */
527static int intel_mnemonic = !SYSV386_COMPAT;
528
5209009a 529/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 530static int old_gcc = OLDGCC_COMPAT;
531
a60de03c
JB		 532/* 1 if pseudo registers are permitted. */
533static int allow_pseudo_reg = 0;
534
47926f60
KH		 535/* 1 if register prefix % not required. */
536static int allow_naked_reg = 0;
252b5132 537
7e8b059b
L		 538/* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
540 explicitly. */
541static int add_bnd_prefix = 0;
542
ba104c83 543/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 544static int allow_index_reg = 0;
545
d022bddd
IT		 546/* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548static int omit_lock_prefix = 0;
549
7bab8ab5 550static enum check_kind
daf50ae7 551 {
7bab8ab5
JB		 552 check_none = 0,
553 check_warning,
554 check_error
daf50ae7 555 }
7bab8ab5 556sse_check, operand_check = check_warning;
daf50ae7 557
2ca3ace5
L		 558/* Register prefix used for error message. */
559static const char *register_prefix = "%";
560
47926f60
KH		 561/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564static char stackop_size = '\0';
eecb386c 565
12b55ccc
L		 566/* Non-zero to optimize code alignment. */
567int optimize_align_code = 1;
568
47926f60
KH		 569/* Non-zero to quieten some warnings. */
570static int quiet_warnings = 0;
a38cf1db 571
47926f60
KH		 572/* CPU name. */
573static const char *cpu_arch_name = NULL;
6305a203 574static char *cpu_sub_arch_name = NULL;
a38cf1db 575
47926f60 576/* CPU feature flags. */
40fb9820
L		 577static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
578
ccc9c027
L		 579/* If we have selected a cpu we are generating instructions for. */
580static int cpu_arch_tune_set = 0;
581
9103f4f4 582/* Cpu we are generating instructions for. */
fbf3f584 583enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 584
585/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 586static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 587
ccc9c027 588/* CPU instruction set architecture used. */
fbf3f584 589enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 590
9103f4f4 591/* CPU feature flags of instruction set architecture used. */
fbf3f584 592i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 593
fddf5b5b
AM		 594/* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596static unsigned int no_cond_jump_promotion = 0;
597
c0f3af97
L		 598/* Encode SSE instructions with VEX prefix. */
599static unsigned int sse2avx;
600
539f890d
L		 601/* Encode scalar AVX instructions with specific vector length. */
602static enum
603 {
604 vex128 = 0,
605 vex256
606 } avxscalar;
607
43234a1e
L		 608/* Encode scalar EVEX LIG instructions with specific vector length. */
609static enum
610 {
611 evexl128 = 0,
612 evexl256,
613 evexl512
614 } evexlig;
615
616/* Encode EVEX WIG instructions with specific evex.w. */
617static enum
618 {
619 evexw0 = 0,
620 evexw1
621 } evexwig;
622
d3d3c6db
IT		 623/* Value to encode in EVEX RC bits, for SAE-only instructions. */
624static enum rc_type evexrcig = rne;
625
29b0f896 626/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 627static symbolS *GOT_symbol;
29b0f896 628
a4447b93
RH		 629/* The dwarf2 return column, adjusted for 32 or 64 bit. */
630unsigned int x86_dwarf2_return_column;
631
632/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633int x86_cie_data_alignment;
634
252b5132 635/* Interface to relax_segment.
fddf5b5b
AM		 636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
252b5132 639
47926f60 640/* Types. */
93c2a809
AM		 641#define UNCOND_JUMP 0
642#define COND_JUMP 1
643#define COND_JUMP86 2
fddf5b5b 644
47926f60 645/* Sizes. */
252b5132
RH		 646#define CODE16 1
647#define SMALL 0
29b0f896 648#define SMALL16 (SMALL | CODE16)
252b5132 649#define BIG 2
29b0f896 650#define BIG16 (BIG | CODE16)
252b5132
RH		 651
652#ifndef INLINE
653#ifdef __GNUC__
654#define INLINE __inline__
655#else
656#define INLINE
657#endif
658#endif
659
fddf5b5b
AM		 660#define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662#define TYPE_FROM_RELAX_STATE(s) \
663 ((s) >> 2)
664#define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 666
667/* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
674
675const relax_typeS md_relax_table[] =
676{
24eab124
AM		 677 /* The fields are:
678 1) most positive reach of this state,
679 2) most negative reach of this state,
93c2a809 680 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 681 4) which index into the table to try if we can't fit into this one. */
252b5132 682
fddf5b5b 683 /* UNCOND_JUMP states. */
93c2a809
AM		 684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
252b5132 688 {0, 0, 4, 0},
93c2a809
AM		 689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 691 {0, 0, 2, 0},
692
93c2a809
AM		 693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
698 {0, 0, 5, 0},
fddf5b5b 699 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 700 1 extra opcode byte, 2 displacement bytes. */
701 {0, 0, 3, 0},
702
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
708 {0, 0, 5, 0},
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
711 {0, 0, 4, 0}
252b5132
RH		 712};
713
9103f4f4
L		 714static const arch_entry cpu_arch[] =
715{
89507696
JB		 716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
8a2c8fef 718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 719 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 721 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 723 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 725 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 727 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 729 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 731 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 733 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 735 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 737 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 739 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 741 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 743 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 745 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 747 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 749 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 751 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 753 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 755 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 757 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 759 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 761 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
763 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 765 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 767 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 769 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 771 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 773 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 775 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 777 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 779 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 781 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
783 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
785 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
787 CPU_BTVER1_FLAGS, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
789 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 791 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 793 CPU_287_FLAGS, 0, 0 },
8a2c8fef 794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 795 CPU_387_FLAGS, 0, 0 },
8a2c8fef 796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 797 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 799 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 801 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 803 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 805 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 807 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 809 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 811 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 813 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 815 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 817 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 819 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
821 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
823 CPU_AVX512F_FLAGS, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
825 CPU_AVX512CD_FLAGS, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
827 CPU_AVX512ER_FLAGS, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
829 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
831 CPU_AVX512DQ_FLAGS, 0, 0 },
832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
833 CPU_AVX512BW_FLAGS, 0, 0 },
834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
835 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 837 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 839 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
841 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 843 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 845 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 847 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
849 CPU_XSAVEC_FLAGS, 0, 0 },
850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
851 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 853 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 855 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 857 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 859 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 861 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 863 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
865 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 867 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 869 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 871 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 873 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 875 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
877 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 879 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
881 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
883 CPU_HLE_FLAGS, 0, 0 },
884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
885 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
887 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 889 CPU_CLFLUSH_FLAGS, 0, 0 },
890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
891 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 893 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 895 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 897 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 899 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 901 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 903 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 905 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 907 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 909 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
911 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
913 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
915 CPU_ADX_FLAGS, 0, 0 },
916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
917 CPU_RDSEED_FLAGS, 0, 0 },
918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
919 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
921 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
923 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
925 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
927 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
929 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
931 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
933 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
935 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 936 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
937 CPU_AVX512IFMA_FLAGS, 0, 0 },
e413e4e9
AM		 938};
939
704209c0 940#ifdef I386COFF
a6c24e68
NC		 941/* Like s_lcomm_internal in gas/read.c but the alignment string
942 is allowed to be optional. */
943
944static symbolS *
945pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
946{
947 addressT align = 0;
948
949 SKIP_WHITESPACE ();
950
7ab9ffdd 951 if (needs_align
a6c24e68
NC		 952 && *input_line_pointer == ',')
953 {
954 align = parse_align (needs_align - 1);
7ab9ffdd 955
a6c24e68
NC		 956 if (align == (addressT) -1)
957 return NULL;
958 }
959 else
960 {
961 if (size >= 8)
962 align = 3;
963 else if (size >= 4)
964 align = 2;
965 else if (size >= 2)
966 align = 1;
967 else
968 align = 0;
969 }
970
971 bss_alloc (symbolP, size, align);
972 return symbolP;
973}
974
704209c0 975static void
a6c24e68
NC		 976pe_lcomm (int needs_align)
977{
978 s_comm_internal (needs_align * 2, pe_lcomm_internal);
979}
704209c0 980#endif
a6c24e68 981
29b0f896
AM		 982const pseudo_typeS md_pseudo_table[] =
983{
984#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
985 {"align", s_align_bytes, 0},
986#else
987 {"align", s_align_ptwo, 0},
988#endif
989 {"arch", set_cpu_arch, 0},
990#ifndef I386COFF
991 {"bss", s_bss, 0},
a6c24e68
NC		 992#else
993 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 994#endif
995 {"ffloat", float_cons, 'f'},
996 {"dfloat", float_cons, 'd'},
997 {"tfloat", float_cons, 'x'},
998 {"value", cons, 2},
d182319b 999 {"slong", signed_cons, 4},
29b0f896
AM		 1000 {"noopt", s_ignore, 0},
1001 {"optim", s_ignore, 0},
1002 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1003 {"code16", set_code_flag, CODE_16BIT},
1004 {"code32", set_code_flag, CODE_32BIT},
1005 {"code64", set_code_flag, CODE_64BIT},
1006 {"intel_syntax", set_intel_syntax, 1},
1007 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1008 {"intel_mnemonic", set_intel_mnemonic, 1},
1009 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1010 {"allow_index_reg", set_allow_index_reg, 1},
1011 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1012 {"sse_check", set_check, 0},
1013 {"operand_check", set_check, 1},
3b22753a
L		 1014#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1015 {"largecomm", handle_large_common, 0},
07a53e5c 1016#else
e3bb37b5 1017 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1018 {"loc", dwarf2_directive_loc, 0},
1019 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1020#endif
6482c264
NC		 1021#ifdef TE_PE
1022 {"secrel32", pe_directive_secrel, 0},
1023#endif
29b0f896
AM		 1024 {0, 0, 0}
1025};
1026
1027/* For interface with expression (). */
1028extern char *input_line_pointer;
1029
1030/* Hash table for instruction mnemonic lookup. */
1031static struct hash_control *op_hash;
1032
1033/* Hash table for register lookup. */
1034static struct hash_control *reg_hash;
1035\f
252b5132 1036void
e3bb37b5 1037i386_align_code (fragS *fragP, int count)
252b5132 1038{
ce8a8b2f
AM		 1039 /* Various efficient no-op patterns for aligning code labels.
1040 Note: Don't try to assemble the instructions in the comments.
1041 0L and 0w are not legal. */
252b5132
RH		 1042 static const char f32_1[] =
1043 {0x90}; /* nop */
1044 static const char f32_2[] =
ccc9c027 1045 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1046 static const char f32_3[] =
1047 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1048 static const char f32_4[] =
1049 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1050 static const char f32_5[] =
1051 {0x90, /* nop */
1052 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1053 static const char f32_6[] =
1054 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1055 static const char f32_7[] =
1056 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1057 static const char f32_8[] =
1058 {0x90, /* nop */
1059 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1060 static const char f32_9[] =
1061 {0x89,0xf6, /* movl %esi,%esi */
1062 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1063 static const char f32_10[] =
1064 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1065 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1066 static const char f32_11[] =
1067 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1068 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1069 static const char f32_12[] =
1070 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1071 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1072 static const char f32_13[] =
1073 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1074 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1075 static const char f32_14[] =
1076 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1078 static const char f16_3[] =
1079 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1080 static const char f16_4[] =
1081 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1082 static const char f16_5[] =
1083 {0x90, /* nop */
1084 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1085 static const char f16_6[] =
1086 {0x89,0xf6, /* mov %si,%si */
1087 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1088 static const char f16_7[] =
1089 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1090 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1091 static const char f16_8[] =
1092 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1093 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1094 static const char jump_31[] =
1095 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1096 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1097 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1098 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1099 static const char *const f32_patt[] = {
1100 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1101 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1102 };
1103 static const char *const f16_patt[] = {
76bc74dc 1104 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1105 };
ccc9c027
L		 1106 /* nopl (%[re]ax) */
1107 static const char alt_3[] =
1108 {0x0f,0x1f,0x00};
1109 /* nopl 0(%[re]ax) */
1110 static const char alt_4[] =
1111 {0x0f,0x1f,0x40,0x00};
1112 /* nopl 0(%[re]ax,%[re]ax,1) */
1113 static const char alt_5[] =
1114 {0x0f,0x1f,0x44,0x00,0x00};
1115 /* nopw 0(%[re]ax,%[re]ax,1) */
1116 static const char alt_6[] =
1117 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1118 /* nopl 0L(%[re]ax) */
1119 static const char alt_7[] =
1120 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1121 /* nopl 0L(%[re]ax,%[re]ax,1) */
1122 static const char alt_8[] =
1123 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1124 /* nopw 0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_9[] =
1126 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1127 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1128 static const char alt_10[] =
1129 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1130 /* data16
1131 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1132 static const char alt_long_11[] =
1133 {0x66,
1134 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1135 /* data16
1136 data16
1137 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1138 static const char alt_long_12[] =
1139 {0x66,
1140 0x66,
1141 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 /* data16
1143 data16
1144 data16
1145 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1146 static const char alt_long_13[] =
1147 {0x66,
1148 0x66,
1149 0x66,
1150 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1151 /* data16
1152 data16
1153 data16
1154 data16
1155 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1156 static const char alt_long_14[] =
1157 {0x66,
1158 0x66,
1159 0x66,
1160 0x66,
1161 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1162 /* data16
1163 data16
1164 data16
1165 data16
1166 data16
1167 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1168 static const char alt_long_15[] =
1169 {0x66,
1170 0x66,
1171 0x66,
1172 0x66,
1173 0x66,
1174 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1175 /* nopl 0(%[re]ax,%[re]ax,1)
1176 nopw 0(%[re]ax,%[re]ax,1) */
1177 static const char alt_short_11[] =
1178 {0x0f,0x1f,0x44,0x00,0x00,
1179 0x66,0x0f,0x1f,0x44,0x00,0x00};
1180 /* nopw 0(%[re]ax,%[re]ax,1)
1181 nopw 0(%[re]ax,%[re]ax,1) */
1182 static const char alt_short_12[] =
1183 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1184 0x66,0x0f,0x1f,0x44,0x00,0x00};
1185 /* nopw 0(%[re]ax,%[re]ax,1)
1186 nopl 0L(%[re]ax) */
1187 static const char alt_short_13[] =
1188 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1189 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1190 /* nopl 0L(%[re]ax)
1191 nopl 0L(%[re]ax) */
1192 static const char alt_short_14[] =
1193 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1194 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1195 /* nopl 0L(%[re]ax)
1196 nopl 0L(%[re]ax,%[re]ax,1) */
1197 static const char alt_short_15[] =
1198 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1199 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1200 static const char *const alt_short_patt[] = {
1201 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1202 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1203 alt_short_14, alt_short_15
1204 };
1205 static const char *const alt_long_patt[] = {
1206 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1207 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1208 alt_long_14, alt_long_15
1209 };
252b5132 1210
76bc74dc
L		 1211 /* Only align for at least a positive non-zero boundary. */
1212 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1213 return;
3e73aa7c 1214
ccc9c027
L		 1215 /* We need to decide which NOP sequence to use for 32bit and
1216 64bit. When -mtune= is used:
4eed87de 1217
76bc74dc
L		 1218 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1219 PROCESSOR_GENERIC32, f32_patt will be used.
1220 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1221 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1222 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1223 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1224 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1225 will be used.
ccc9c027 1226
76bc74dc 1227 When -mtune= isn't used, alt_long_patt will be used if
22109423 1228 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1229 be used.
ccc9c027
L		 1230
1231 When -march= or .arch is used, we can't use anything beyond
1232 cpu_arch_isa_flags. */
1233
1234 if (flag_code == CODE_16BIT)
1235 {
ccc9c027 1236 if (count > 8)
33fef721 1237 {
76bc74dc
L		 1238 memcpy (fragP->fr_literal + fragP->fr_fix,
1239 jump_31, count);
1240 /* Adjust jump offset. */
1241 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1242 }
76bc74dc
L		 1243 else
1244 memcpy (fragP->fr_literal + fragP->fr_fix,
1245 f16_patt[count - 1], count);
252b5132 1246 }
33fef721 1247 else
ccc9c027
L		 1248 {
1249 const char *const *patt = NULL;
1250
fbf3f584 1251 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1252 {
1253 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1254 switch (cpu_arch_tune)
1255 {
1256 case PROCESSOR_UNKNOWN:
1257 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1258 optimize with nops. */
1259 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1260 patt = alt_long_patt;
ccc9c027
L		 1261 else
1262 patt = f32_patt;
1263 break;
ccc9c027
L		 1264 case PROCESSOR_PENTIUM4:
1265 case PROCESSOR_NOCONA:
ef05d495 1266 case PROCESSOR_CORE:
76bc74dc 1267 case PROCESSOR_CORE2:
bd5295b2 1268 case PROCESSOR_COREI7:
3632d14b 1269 case PROCESSOR_L1OM:
7a9068fe 1270 case PROCESSOR_K1OM:
76bc74dc
L		 1271 case PROCESSOR_GENERIC64:
1272 patt = alt_long_patt;
1273 break;
ccc9c027
L		 1274 case PROCESSOR_K6:
1275 case PROCESSOR_ATHLON:
1276 case PROCESSOR_K8:
4eed87de 1277 case PROCESSOR_AMDFAM10:
8aedb9fe 1278 case PROCESSOR_BD:
7b458c12 1279 case PROCESSOR_BT:
ccc9c027
L		 1280 patt = alt_short_patt;
1281 break;
76bc74dc 1282 case PROCESSOR_I386:
ccc9c027
L		 1283 case PROCESSOR_I486:
1284 case PROCESSOR_PENTIUM:
2dde1948 1285 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1286 case PROCESSOR_GENERIC32:
1287 patt = f32_patt;
1288 break;
4eed87de 1289 }
ccc9c027
L		 1290 }
1291 else
1292 {
fbf3f584 1293 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1294 {
1295 case PROCESSOR_UNKNOWN:
e6a14101 1296 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1297 PROCESSOR_UNKNOWN. */
1298 abort ();
1299 break;
1300
76bc74dc 1301 case PROCESSOR_I386:
ccc9c027
L		 1302 case PROCESSOR_I486:
1303 case PROCESSOR_PENTIUM:
ccc9c027
L		 1304 case PROCESSOR_K6:
1305 case PROCESSOR_ATHLON:
1306 case PROCESSOR_K8:
4eed87de 1307 case PROCESSOR_AMDFAM10:
8aedb9fe 1308 case PROCESSOR_BD:
7b458c12 1309 case PROCESSOR_BT:
ccc9c027
L		 1310 case PROCESSOR_GENERIC32:
1311 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1312 with nops. */
1313 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1314 patt = alt_short_patt;
1315 else
1316 patt = f32_patt;
1317 break;
76bc74dc
L		 1318 case PROCESSOR_PENTIUMPRO:
1319 case PROCESSOR_PENTIUM4:
1320 case PROCESSOR_NOCONA:
1321 case PROCESSOR_CORE:
ef05d495 1322 case PROCESSOR_CORE2:
bd5295b2 1323 case PROCESSOR_COREI7:
3632d14b 1324 case PROCESSOR_L1OM:
7a9068fe 1325 case PROCESSOR_K1OM:
22109423 1326 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1327 patt = alt_long_patt;
1328 else
1329 patt = f32_patt;
1330 break;
1331 case PROCESSOR_GENERIC64:
76bc74dc 1332 patt = alt_long_patt;
ccc9c027 1333 break;
4eed87de 1334 }
ccc9c027
L		 1335 }
1336
76bc74dc
L		 1337 if (patt == f32_patt)
1338 {
1339 /* If the padding is less than 15 bytes, we use the normal
1340 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1341 its offset. */
1342 int limit;
76ba9986 1343
711eedef
L		 1344 /* For 64bit, the limit is 3 bytes. */
1345 if (flag_code == CODE_64BIT
1346 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1347 limit = 3;
1348 else
1349 limit = 15;
1350 if (count < limit)
76bc74dc
L		 1351 memcpy (fragP->fr_literal + fragP->fr_fix,
1352 patt[count - 1], count);
1353 else
1354 {
1355 memcpy (fragP->fr_literal + fragP->fr_fix,
1356 jump_31, count);
1357 /* Adjust jump offset. */
1358 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1359 }
1360 }
1361 else
1362 {
1363 /* Maximum length of an instruction is 15 byte. If the
1364 padding is greater than 15 bytes and we don't use jump,
1365 we have to break it into smaller pieces. */
1366 int padding = count;
1367 while (padding > 15)
1368 {
1369 padding -= 15;
1370 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1371 patt [14], 15);
1372 }
1373
1374 if (padding)
1375 memcpy (fragP->fr_literal + fragP->fr_fix,
1376 patt [padding - 1], padding);
1377 }
ccc9c027 1378 }
33fef721 1379 fragP->fr_var = count;
252b5132
RH		 1380}
1381
c6fb90c8 1382static INLINE int
0dfbf9d7 1383operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1384{
0dfbf9d7 1385 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1386 {
1387 case 3:
0dfbf9d7 1388 if (x->array[2])
c6fb90c8
L		 1389 return 0;
1390 case 2:
0dfbf9d7 1391 if (x->array[1])
c6fb90c8
L		 1392 return 0;
1393 case 1:
0dfbf9d7 1394 return !x->array[0];
c6fb90c8
L		 1395 default:
1396 abort ();
1397 }
40fb9820
L		 1398}
1399
c6fb90c8 1400static INLINE void
0dfbf9d7 1401operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1402{
0dfbf9d7 1403 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1404 {
1405 case 3:
0dfbf9d7 1406 x->array[2] = v;
c6fb90c8 1407 case 2:
0dfbf9d7 1408 x->array[1] = v;
c6fb90c8 1409 case 1:
0dfbf9d7 1410 x->array[0] = v;
c6fb90c8
L		 1411 break;
1412 default:
1413 abort ();
1414 }
1415}
40fb9820 1416
c6fb90c8 1417static INLINE int
0dfbf9d7
L		 1418operand_type_equal (const union i386_operand_type *x,
1419 const union i386_operand_type *y)
c6fb90c8 1420{
0dfbf9d7 1421 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1422 {
1423 case 3:
0dfbf9d7 1424 if (x->array[2] != y->array[2])
c6fb90c8
L		 1425 return 0;
1426 case 2:
0dfbf9d7 1427 if (x->array[1] != y->array[1])
c6fb90c8
L		 1428 return 0;
1429 case 1:
0dfbf9d7 1430 return x->array[0] == y->array[0];
c6fb90c8
L		 1431 break;
1432 default:
1433 abort ();
1434 }
1435}
40fb9820 1436
0dfbf9d7
L		 1437static INLINE int
1438cpu_flags_all_zero (const union i386_cpu_flags *x)
1439{
1440 switch (ARRAY_SIZE(x->array))
1441 {
1442 case 3:
1443 if (x->array[2])
1444 return 0;
1445 case 2:
1446 if (x->array[1])
1447 return 0;
1448 case 1:
1449 return !x->array[0];
1450 default:
1451 abort ();
1452 }
1453}
1454
1455static INLINE void
1456cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1457{
1458 switch (ARRAY_SIZE(x->array))
1459 {
1460 case 3:
1461 x->array[2] = v;
1462 case 2:
1463 x->array[1] = v;
1464 case 1:
1465 x->array[0] = v;
1466 break;
1467 default:
1468 abort ();
1469 }
1470}
1471
1472static INLINE int
1473cpu_flags_equal (const union i386_cpu_flags *x,
1474 const union i386_cpu_flags *y)
1475{
1476 switch (ARRAY_SIZE(x->array))
1477 {
1478 case 3:
1479 if (x->array[2] != y->array[2])
1480 return 0;
1481 case 2:
1482 if (x->array[1] != y->array[1])
1483 return 0;
1484 case 1:
1485 return x->array[0] == y->array[0];
1486 break;
1487 default:
1488 abort ();
1489 }
1490}
c6fb90c8
L		 1491
1492static INLINE int
1493cpu_flags_check_cpu64 (i386_cpu_flags f)
1494{
1495 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1496 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1497}
1498
c6fb90c8
L		 1499static INLINE i386_cpu_flags
1500cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1501{
c6fb90c8
L		 1502 switch (ARRAY_SIZE (x.array))
1503 {
1504 case 3:
1505 x.array [2] &= y.array [2];
1506 case 2:
1507 x.array [1] &= y.array [1];
1508 case 1:
1509 x.array [0] &= y.array [0];
1510 break;
1511 default:
1512 abort ();
1513 }
1514 return x;
1515}
40fb9820 1516
c6fb90c8
L		 1517static INLINE i386_cpu_flags
1518cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1519{
c6fb90c8 1520 switch (ARRAY_SIZE (x.array))
40fb9820 1521 {
c6fb90c8
L		 1522 case 3:
1523 x.array [2] |= y.array [2];
1524 case 2:
1525 x.array [1] |= y.array [1];
1526 case 1:
1527 x.array [0] |= y.array [0];
40fb9820
L		 1528 break;
1529 default:
1530 abort ();
1531 }
40fb9820
L		 1532 return x;
1533}
1534
309d3373
JB		 1535static INLINE i386_cpu_flags
1536cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1537{
1538 switch (ARRAY_SIZE (x.array))
1539 {
1540 case 3:
1541 x.array [2] &= ~y.array [2];
1542 case 2:
1543 x.array [1] &= ~y.array [1];
1544 case 1:
1545 x.array [0] &= ~y.array [0];
1546 break;
1547 default:
1548 abort ();
1549 }
1550 return x;
1551}
1552
c0f3af97
L		 1553#define CPU_FLAGS_ARCH_MATCH 0x1
1554#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1555#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1556#define CPU_FLAGS_PCLMUL_MATCH 0x8
1557#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1558
a5ff0eb2 1559#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1560 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1561 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1562#define CPU_FLAGS_PERFECT_MATCH \
1563 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1564
1565/* Return CPU flags match bits. */
3629bb00 1566
40fb9820 1567static int
d3ce72d0 1568cpu_flags_match (const insn_template *t)
40fb9820 1569{
c0f3af97
L		 1570 i386_cpu_flags x = t->cpu_flags;
1571 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1572
1573 x.bitfield.cpu64 = 0;
1574 x.bitfield.cpuno64 = 0;
1575
0dfbf9d7 1576 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1577 {
1578 /* This instruction is available on all archs. */
1579 match |= CPU_FLAGS_32BIT_MATCH;
1580 }
3629bb00
L		 1581 else
1582 {
c0f3af97 1583 /* This instruction is available only on some archs. */
3629bb00
L		 1584 i386_cpu_flags cpu = cpu_arch_flags;
1585
1586 cpu.bitfield.cpu64 = 0;
1587 cpu.bitfield.cpuno64 = 0;
1588 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1589 if (!cpu_flags_all_zero (&cpu))
1590 {
a5ff0eb2
L		 1591 if (x.bitfield.cpuavx)
1592 {
ce2f5b3c 1593 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1594 if (cpu.bitfield.cpuavx)
1595 {
1596 /* Check SSE2AVX. */
1597 if (!t->opcode_modifier.sse2avx|| sse2avx)
1598 {
1599 match |= (CPU_FLAGS_ARCH_MATCH
1600 | CPU_FLAGS_AVX_MATCH);
1601 /* Check AES. */
1602 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1603 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1604 /* Check PCLMUL. */
1605 if (!x.bitfield.cpupclmul
1606 || cpu.bitfield.cpupclmul)
1607 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1608 }
1609 }
1610 else
1611 match |= CPU_FLAGS_ARCH_MATCH;
1612 }
1613 else
c0f3af97
L		 1614 match |= CPU_FLAGS_32BIT_MATCH;
1615 }
3629bb00 1616 }
c0f3af97 1617 return match;
40fb9820
L		 1618}
1619
c6fb90c8
L		 1620static INLINE i386_operand_type
1621operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1622{
c6fb90c8
L		 1623 switch (ARRAY_SIZE (x.array))
1624 {
1625 case 3:
1626 x.array [2] &= y.array [2];
1627 case 2:
1628 x.array [1] &= y.array [1];
1629 case 1:
1630 x.array [0] &= y.array [0];
1631 break;
1632 default:
1633 abort ();
1634 }
1635 return x;
40fb9820
L		 1636}
1637
c6fb90c8
L		 1638static INLINE i386_operand_type
1639operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1640{
c6fb90c8 1641 switch (ARRAY_SIZE (x.array))
40fb9820 1642 {
c6fb90c8
L		 1643 case 3:
1644 x.array [2] |= y.array [2];
1645 case 2:
1646 x.array [1] |= y.array [1];
1647 case 1:
1648 x.array [0] |= y.array [0];
40fb9820
L		 1649 break;
1650 default:
1651 abort ();
1652 }
c6fb90c8
L		 1653 return x;
1654}
40fb9820 1655
c6fb90c8
L		 1656static INLINE i386_operand_type
1657operand_type_xor (i386_operand_type x, i386_operand_type y)
1658{
1659 switch (ARRAY_SIZE (x.array))
1660 {
1661 case 3:
1662 x.array [2] ^= y.array [2];
1663 case 2:
1664 x.array [1] ^= y.array [1];
1665 case 1:
1666 x.array [0] ^= y.array [0];
1667 break;
1668 default:
1669 abort ();
1670 }
40fb9820
L		 1671 return x;
1672}
1673
1674static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1675static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1676static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1677static const i386_operand_type inoutportreg
1678 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1679static const i386_operand_type reg16_inoutportreg
1680 = OPERAND_TYPE_REG16_INOUTPORTREG;
1681static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1682static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1683static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1684static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1685static const i386_operand_type anydisp
1686 = OPERAND_TYPE_ANYDISP;
40fb9820 1687static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1688static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1689static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1690static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1691static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1692static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1693static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1694static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1695static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1696static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1697static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1698static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1699static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1700static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1701
1702enum operand_type
1703{
1704 reg,
40fb9820
L		 1705 imm,
1706 disp,
1707 anymem
1708};
1709
c6fb90c8 1710static INLINE int
40fb9820
L		 1711operand_type_check (i386_operand_type t, enum operand_type c)
1712{
1713 switch (c)
1714 {
1715 case reg:
1716 return (t.bitfield.reg8
1717 || t.bitfield.reg16
1718 || t.bitfield.reg32
1719 || t.bitfield.reg64);
1720
40fb9820
L		 1721 case imm:
1722 return (t.bitfield.imm8
1723 || t.bitfield.imm8s
1724 || t.bitfield.imm16
1725 || t.bitfield.imm32
1726 || t.bitfield.imm32s
1727 || t.bitfield.imm64);
1728
1729 case disp:
1730 return (t.bitfield.disp8
1731 || t.bitfield.disp16
1732 || t.bitfield.disp32
1733 || t.bitfield.disp32s
1734 || t.bitfield.disp64);
1735
1736 case anymem:
1737 return (t.bitfield.disp8
1738 || t.bitfield.disp16
1739 || t.bitfield.disp32
1740 || t.bitfield.disp32s
1741 || t.bitfield.disp64
1742 || t.bitfield.baseindex);
1743
1744 default:
1745 abort ();
1746 }
2cfe26b6
AM		 1747
1748 return 0;
40fb9820
L		 1749}
1750
5c07affc
L		 1751/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1752 operand J for instruction template T. */
1753
1754static INLINE int
d3ce72d0 1755match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1756{
1757 return !((i.types[j].bitfield.byte
1758 && !t->operand_types[j].bitfield.byte)
1759 || (i.types[j].bitfield.word
1760 && !t->operand_types[j].bitfield.word)
1761 || (i.types[j].bitfield.dword
1762 && !t->operand_types[j].bitfield.dword)
1763 || (i.types[j].bitfield.qword
1764 && !t->operand_types[j].bitfield.qword));
1765}
1766
1767/* Return 1 if there is no conflict in any size on operand J for
1768 instruction template T. */
1769
1770static INLINE int
d3ce72d0 1771match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1772{
1773 return (match_reg_size (t, j)
1774 && !((i.types[j].bitfield.unspecified
1775 && !t->operand_types[j].bitfield.unspecified)
1776 || (i.types[j].bitfield.fword
1777 && !t->operand_types[j].bitfield.fword)
1778 || (i.types[j].bitfield.tbyte
1779 && !t->operand_types[j].bitfield.tbyte)
1780 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1781 && !t->operand_types[j].bitfield.xmmword)
1782 || (i.types[j].bitfield.ymmword
43234a1e
L		 1783 && !t->operand_types[j].bitfield.ymmword)
1784 || (i.types[j].bitfield.zmmword
1785 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1786}
1787
1788/* Return 1 if there is no size conflict on any operands for
1789 instruction template T. */
1790
1791static INLINE int
d3ce72d0 1792operand_size_match (const insn_template *t)
5c07affc
L		 1793{
1794 unsigned int j;
1795 int match = 1;
1796
1797 /* Don't check jump instructions. */
1798 if (t->opcode_modifier.jump
1799 || t->opcode_modifier.jumpbyte
1800 || t->opcode_modifier.jumpdword
1801 || t->opcode_modifier.jumpintersegment)
1802 return match;
1803
1804 /* Check memory and accumulator operand size. */
1805 for (j = 0; j < i.operands; j++)
1806 {
1807 if (t->operand_types[j].bitfield.anysize)
1808 continue;
1809
1810 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1811 {
1812 match = 0;
1813 break;
1814 }
1815
1816 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1817 {
1818 match = 0;
1819 break;
1820 }
1821 }
1822
891edac4 1823 if (match)
5c07affc 1824 return match;
891edac4
L		 1825 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1826 {
1827mismatch:
86e026a4 1828 i.error = operand_size_mismatch;
891edac4
L		 1829 return 0;
1830 }
5c07affc
L		 1831
1832 /* Check reverse. */
9c2799c2 1833 gas_assert (i.operands == 2);
5c07affc
L		 1834
1835 match = 1;
1836 for (j = 0; j < 2; j++)
1837 {
1838 if (t->operand_types[j].bitfield.acc
1839 && !match_reg_size (t, j ? 0 : 1))
891edac4 1840 goto mismatch;
5c07affc
L		 1841
1842 if (i.types[j].bitfield.mem
1843 && !match_mem_size (t, j ? 0 : 1))
891edac4 1844 goto mismatch;
5c07affc
L		 1845 }
1846
1847 return match;
1848}
1849
c6fb90c8 1850static INLINE int
40fb9820
L		 1851operand_type_match (i386_operand_type overlap,
1852 i386_operand_type given)
1853{
1854 i386_operand_type temp = overlap;
1855
1856 temp.bitfield.jumpabsolute = 0;
7d5e4556 1857 temp.bitfield.unspecified = 0;
5c07affc
L		 1858 temp.bitfield.byte = 0;
1859 temp.bitfield.word = 0;
1860 temp.bitfield.dword = 0;
1861 temp.bitfield.fword = 0;
1862 temp.bitfield.qword = 0;
1863 temp.bitfield.tbyte = 0;
1864 temp.bitfield.xmmword = 0;
c0f3af97 1865 temp.bitfield.ymmword = 0;
43234a1e 1866 temp.bitfield.zmmword = 0;
0dfbf9d7 1867 if (operand_type_all_zero (&temp))
891edac4 1868 goto mismatch;
40fb9820 1869
891edac4
L		 1870 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1871 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1872 return 1;
1873
1874mismatch:
a65babc9 1875 i.error = operand_type_mismatch;
891edac4 1876 return 0;
40fb9820
L		 1877}
1878
7d5e4556 1879/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1880 unless the expected operand type register overlap is null.
1881 Note that Acc in a template matches every size of reg. */
1882
c6fb90c8 1883static INLINE int
40fb9820
L		 1884operand_type_register_match (i386_operand_type m0,
1885 i386_operand_type g0,
1886 i386_operand_type t0,
1887 i386_operand_type m1,
1888 i386_operand_type g1,
1889 i386_operand_type t1)
1890{
1891 if (!operand_type_check (g0, reg))
1892 return 1;
1893
1894 if (!operand_type_check (g1, reg))
1895 return 1;
1896
1897 if (g0.bitfield.reg8 == g1.bitfield.reg8
1898 && g0.bitfield.reg16 == g1.bitfield.reg16
1899 && g0.bitfield.reg32 == g1.bitfield.reg32
1900 && g0.bitfield.reg64 == g1.bitfield.reg64)
1901 return 1;
1902
1903 if (m0.bitfield.acc)
1904 {
1905 t0.bitfield.reg8 = 1;
1906 t0.bitfield.reg16 = 1;
1907 t0.bitfield.reg32 = 1;
1908 t0.bitfield.reg64 = 1;
1909 }
1910
1911 if (m1.bitfield.acc)
1912 {
1913 t1.bitfield.reg8 = 1;
1914 t1.bitfield.reg16 = 1;
1915 t1.bitfield.reg32 = 1;
1916 t1.bitfield.reg64 = 1;
1917 }
1918
891edac4
L		 1919 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1920 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1921 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1922 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1923 return 1;
1924
a65babc9 1925 i.error = register_type_mismatch;
891edac4
L		 1926
1927 return 0;
40fb9820
L		 1928}
1929
4c692bc7
JB		 1930static INLINE unsigned int
1931register_number (const reg_entry *r)
1932{
1933 unsigned int nr = r->reg_num;
1934
1935 if (r->reg_flags & RegRex)
1936 nr += 8;
1937
1938 return nr;
1939}
1940
252b5132 1941static INLINE unsigned int
40fb9820 1942mode_from_disp_size (i386_operand_type t)
252b5132 1943{
43234a1e 1944 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1945 return 1;
1946 else if (t.bitfield.disp16
1947 || t.bitfield.disp32
1948 || t.bitfield.disp32s)
1949 return 2;
1950 else
1951 return 0;
252b5132
RH		 1952}
1953
1954static INLINE int
65879393 1955fits_in_signed_byte (addressT num)
252b5132 1956{
65879393 1957 return num + 0x80 <= 0xff;
47926f60 1958}
252b5132
RH		 1959
1960static INLINE int
65879393 1961fits_in_unsigned_byte (addressT num)
252b5132 1962{
65879393 1963 return num <= 0xff;
47926f60 1964}
252b5132
RH		 1965
1966static INLINE int
65879393 1967fits_in_unsigned_word (addressT num)
252b5132 1968{
65879393 1969 return num <= 0xffff;
47926f60 1970}
252b5132
RH		 1971
1972static INLINE int
65879393 1973fits_in_signed_word (addressT num)
252b5132 1974{
65879393 1975 return num + 0x8000 <= 0xffff;
47926f60 1976}
2a962e6d 1977
3e73aa7c 1978static INLINE int
65879393 1979fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1980{
1981#ifndef BFD64
1982 return 1;
1983#else
65879393 1984 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1985#endif
1986} /* fits_in_signed_long() */
2a962e6d 1987
3e73aa7c 1988static INLINE int
65879393 1989fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1990{
1991#ifndef BFD64
1992 return 1;
1993#else
65879393 1994 return num <= 0xffffffff;
3e73aa7c
JH		 1995#endif
1996} /* fits_in_unsigned_long() */
252b5132 1997
43234a1e
L		 1998static INLINE int
1999fits_in_vec_disp8 (offsetT num)
2000{
2001 int shift = i.memshift;
2002 unsigned int mask;
2003
2004 if (shift == -1)
2005 abort ();
2006
2007 mask = (1 << shift) - 1;
2008
2009 /* Return 0 if NUM isn't properly aligned. */
2010 if ((num & mask))
2011 return 0;
2012
2013 /* Check if NUM will fit in 8bit after shift. */
2014 return fits_in_signed_byte (num >> shift);
2015}
2016
a683cc34
SP		 2017static INLINE int
2018fits_in_imm4 (offsetT num)
2019{
2020 return (num & 0xf) == num;
2021}
2022
40fb9820 2023static i386_operand_type
e3bb37b5 2024smallest_imm_type (offsetT num)
252b5132 2025{
40fb9820 2026 i386_operand_type t;
7ab9ffdd 2027
0dfbf9d7 2028 operand_type_set (&t, 0);
40fb9820
L		 2029 t.bitfield.imm64 = 1;
2030
2031 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2032 {
2033 /* This code is disabled on the 486 because all the Imm1 forms
2034 in the opcode table are slower on the i486. They're the
2035 versions with the implicitly specified single-position
2036 displacement, which has another syntax if you really want to
2037 use that form. */
40fb9820
L		 2038 t.bitfield.imm1 = 1;
2039 t.bitfield.imm8 = 1;
2040 t.bitfield.imm8s = 1;
2041 t.bitfield.imm16 = 1;
2042 t.bitfield.imm32 = 1;
2043 t.bitfield.imm32s = 1;
2044 }
2045 else if (fits_in_signed_byte (num))
2046 {
2047 t.bitfield.imm8 = 1;
2048 t.bitfield.imm8s = 1;
2049 t.bitfield.imm16 = 1;
2050 t.bitfield.imm32 = 1;
2051 t.bitfield.imm32s = 1;
2052 }
2053 else if (fits_in_unsigned_byte (num))
2054 {
2055 t.bitfield.imm8 = 1;
2056 t.bitfield.imm16 = 1;
2057 t.bitfield.imm32 = 1;
2058 t.bitfield.imm32s = 1;
2059 }
2060 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2061 {
2062 t.bitfield.imm16 = 1;
2063 t.bitfield.imm32 = 1;
2064 t.bitfield.imm32s = 1;
2065 }
2066 else if (fits_in_signed_long (num))
2067 {
2068 t.bitfield.imm32 = 1;
2069 t.bitfield.imm32s = 1;
2070 }
2071 else if (fits_in_unsigned_long (num))
2072 t.bitfield.imm32 = 1;
2073
2074 return t;
47926f60 2075}
252b5132 2076
847f7ad4 2077static offsetT
e3bb37b5 2078offset_in_range (offsetT val, int size)
847f7ad4 2079{
508866be 2080 addressT mask;
ba2adb93 2081
847f7ad4
AM		 2082 switch (size)
2083 {
508866be
L		 2084 case 1: mask = ((addressT) 1 << 8) - 1; break;
2085 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2086 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2087#ifdef BFD64
2088 case 8: mask = ((addressT) 2 << 63) - 1; break;
2089#endif
47926f60 2090 default: abort ();
847f7ad4
AM		 2091 }
2092
9de868bf
L		 2093#ifdef BFD64
2094 /* If BFD64, sign extend val for 32bit address mode. */
2095 if (flag_code != CODE_64BIT
2096 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2097 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2098 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2099#endif
ba2adb93 2100
47926f60 2101 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2102 {
2103 char buf1[40], buf2[40];
2104
2105 sprint_value (buf1, val);
2106 sprint_value (buf2, val & mask);
2107 as_warn (_("%s shortened to %s"), buf1, buf2);
2108 }
2109 return val & mask;
2110}
2111
c32fa91d
L		 2112enum PREFIX_GROUP
2113{
2114 PREFIX_EXIST = 0,
2115 PREFIX_LOCK,
2116 PREFIX_REP,
2117 PREFIX_OTHER
2118};
2119
2120/* Returns
2121 a. PREFIX_EXIST if attempting to add a prefix where one from the
2122 same class already exists.
2123 b. PREFIX_LOCK if lock prefix is added.
2124 c. PREFIX_REP if rep/repne prefix is added.
2125 d. PREFIX_OTHER if other prefix is added.
2126 */
2127
2128static enum PREFIX_GROUP
e3bb37b5 2129add_prefix (unsigned int prefix)
252b5132 2130{
c32fa91d 2131 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2132 unsigned int q;
252b5132 2133
29b0f896
AM		 2134 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2135 && flag_code == CODE_64BIT)
b1905489 2136 {
161a04f6
L		 2137 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2138 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2139 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2140 ret = PREFIX_EXIST;
b1905489
JB		 2141 q = REX_PREFIX;
2142 }
3e73aa7c 2143 else
b1905489
JB		 2144 {
2145 switch (prefix)
2146 {
2147 default:
2148 abort ();
2149
2150 case CS_PREFIX_OPCODE:
2151 case DS_PREFIX_OPCODE:
2152 case ES_PREFIX_OPCODE:
2153 case FS_PREFIX_OPCODE:
2154 case GS_PREFIX_OPCODE:
2155 case SS_PREFIX_OPCODE:
2156 q = SEG_PREFIX;
2157 break;
2158
2159 case REPNE_PREFIX_OPCODE:
2160 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2161 q = REP_PREFIX;
2162 ret = PREFIX_REP;
2163 break;
2164
b1905489 2165 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2166 q = LOCK_PREFIX;
2167 ret = PREFIX_LOCK;
b1905489
JB		 2168 break;
2169
2170 case FWAIT_OPCODE:
2171 q = WAIT_PREFIX;
2172 break;
2173
2174 case ADDR_PREFIX_OPCODE:
2175 q = ADDR_PREFIX;
2176 break;
2177
2178 case DATA_PREFIX_OPCODE:
2179 q = DATA_PREFIX;
2180 break;
2181 }
2182 if (i.prefix[q] != 0)
c32fa91d 2183 ret = PREFIX_EXIST;
b1905489 2184 }
252b5132 2185
b1905489 2186 if (ret)
252b5132 2187 {
b1905489
JB		 2188 if (!i.prefix[q])
2189 ++i.prefixes;
2190 i.prefix[q] |= prefix;
252b5132 2191 }
b1905489
JB		 2192 else
2193 as_bad (_("same type of prefix used twice"));
252b5132 2194
252b5132
RH		 2195 return ret;
2196}
2197
2198static void
78f12dd3 2199update_code_flag (int value, int check)
eecb386c 2200{
78f12dd3
L		 2201 PRINTF_LIKE ((*as_error));
2202
1e9cc1c2 2203 flag_code = (enum flag_code) value;
40fb9820
L		 2204 if (flag_code == CODE_64BIT)
2205 {
2206 cpu_arch_flags.bitfield.cpu64 = 1;
2207 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2208 }
2209 else
2210 {
2211 cpu_arch_flags.bitfield.cpu64 = 0;
2212 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2213 }
2214 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2215 {
78f12dd3
L		 2216 if (check)
2217 as_error = as_fatal;
2218 else
2219 as_error = as_bad;
2220 (*as_error) (_("64bit mode not supported on `%s'."),
2221 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2222 }
40fb9820 2223 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2224 {
78f12dd3
L		 2225 if (check)
2226 as_error = as_fatal;
2227 else
2228 as_error = as_bad;
2229 (*as_error) (_("32bit mode not supported on `%s'."),
2230 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2231 }
eecb386c
AM		 2232 stackop_size = '\0';
2233}
2234
78f12dd3
L		 2235static void
2236set_code_flag (int value)
2237{
2238 update_code_flag (value, 0);
2239}
2240
eecb386c 2241static void
e3bb37b5 2242set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2243{
1e9cc1c2 2244 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2245 if (flag_code != CODE_16BIT)
2246 abort ();
2247 cpu_arch_flags.bitfield.cpu64 = 0;
2248 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2249 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2250}
2251
2252static void
e3bb37b5 2253set_intel_syntax (int syntax_flag)
252b5132
RH		 2254{
2255 /* Find out if register prefixing is specified. */
2256 int ask_naked_reg = 0;
2257
2258 SKIP_WHITESPACE ();
29b0f896 2259 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2260 {
2261 char *string = input_line_pointer;
2262 int e = get_symbol_end ();
2263
47926f60 2264 if (strcmp (string, "prefix") == 0)
252b5132 2265 ask_naked_reg = 1;
47926f60 2266 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2267 ask_naked_reg = -1;
2268 else
d0b47220 2269 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2270 *input_line_pointer = e;
2271 }
2272 demand_empty_rest_of_line ();
c3332e24 2273
252b5132
RH		 2274 intel_syntax = syntax_flag;
2275
2276 if (ask_naked_reg == 0)
f86103b7
AM		 2277 allow_naked_reg = (intel_syntax
2278 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2279 else
2280 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2281
ee86248c 2282 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2283
e4a3b5a4 2284 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2285 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2286 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2287}
2288
1efbbeb4
L		 2289static void
2290set_intel_mnemonic (int mnemonic_flag)
2291{
e1d4d893 2292 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2293}
2294
db51cc60
L		 2295static void
2296set_allow_index_reg (int flag)
2297{
2298 allow_index_reg = flag;
2299}
2300
cb19c032 2301static void
7bab8ab5 2302set_check (int what)
cb19c032 2303{
7bab8ab5
JB		 2304 enum check_kind *kind;
2305 const char *str;
2306
2307 if (what)
2308 {
2309 kind = &operand_check;
2310 str = "operand";
2311 }
2312 else
2313 {
2314 kind = &sse_check;
2315 str = "sse";
2316 }
2317
cb19c032
L		 2318 SKIP_WHITESPACE ();
2319
2320 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2321 {
2322 char *string = input_line_pointer;
2323 int e = get_symbol_end ();
2324
2325 if (strcmp (string, "none") == 0)
7bab8ab5 2326 *kind = check_none;
cb19c032 2327 else if (strcmp (string, "warning") == 0)
7bab8ab5 2328 *kind = check_warning;
cb19c032 2329 else if (strcmp (string, "error") == 0)
7bab8ab5 2330 *kind = check_error;
cb19c032 2331 else
7bab8ab5 2332 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2333 *input_line_pointer = e;
2334 }
2335 else
7bab8ab5 2336 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2337
2338 demand_empty_rest_of_line ();
2339}
2340
8a9036a4
L		 2341static void
2342check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2343 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2344{
2345#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2346 static const char *arch;
2347
2348 /* Intel LIOM is only supported on ELF. */
2349 if (!IS_ELF)
2350 return;
2351
2352 if (!arch)
2353 {
2354 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2355 use default_arch. */
2356 arch = cpu_arch_name;
2357 if (!arch)
2358 arch = default_arch;
2359 }
2360
3632d14b 2361 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2362 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2363 || new_flag.bitfield.cpul1om)
8a9036a4 2364 return;
76ba9986 2365
7a9068fe
L		 2366 /* If we are targeting Intel K1OM, we must enable it. */
2367 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2368 || new_flag.bitfield.cpuk1om)
2369 return;
2370
8a9036a4
L		 2371 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2372#endif
2373}
2374
e413e4e9 2375static void
e3bb37b5 2376set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2377{
47926f60 2378 SKIP_WHITESPACE ();
e413e4e9 2379
29b0f896 2380 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2381 {
2382 char *string = input_line_pointer;
2383 int e = get_symbol_end ();
91d6fa6a 2384 unsigned int j;
40fb9820 2385 i386_cpu_flags flags;
e413e4e9 2386
91d6fa6a 2387 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2388 {
91d6fa6a 2389 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2390 {
91d6fa6a 2391 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2392
5c6af06e
JB		 2393 if (*string != '.')
2394 {
91d6fa6a 2395 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2396 cpu_sub_arch_name = NULL;
91d6fa6a 2397 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2398 if (flag_code == CODE_64BIT)
2399 {
2400 cpu_arch_flags.bitfield.cpu64 = 1;
2401 cpu_arch_flags.bitfield.cpuno64 = 0;
2402 }
2403 else
2404 {
2405 cpu_arch_flags.bitfield.cpu64 = 0;
2406 cpu_arch_flags.bitfield.cpuno64 = 1;
2407 }
91d6fa6a
NC		 2408 cpu_arch_isa = cpu_arch[j].type;
2409 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2410 if (!cpu_arch_tune_set)
2411 {
2412 cpu_arch_tune = cpu_arch_isa;
2413 cpu_arch_tune_flags = cpu_arch_isa_flags;
2414 }
5c6af06e
JB		 2415 break;
2416 }
40fb9820 2417
22109423 2418 if (!cpu_arch[j].negated)
309d3373 2419 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2420 cpu_arch[j].flags);
309d3373
JB		 2421 else
2422 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2423 cpu_arch[j].flags);
0dfbf9d7 2424 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2425 {
6305a203
L		 2426 if (cpu_sub_arch_name)
2427 {
2428 char *name = cpu_sub_arch_name;
2429 cpu_sub_arch_name = concat (name,
91d6fa6a 2430 cpu_arch[j].name,
1bf57e9f 2431 (const char *) NULL);
6305a203
L		 2432 free (name);
2433 }
2434 else
91d6fa6a 2435 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2436 cpu_arch_flags = flags;
a586129e 2437 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2438 }
2439 *input_line_pointer = e;
2440 demand_empty_rest_of_line ();
2441 return;
e413e4e9
AM		 2442 }
2443 }
91d6fa6a 2444 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2445 as_bad (_("no such architecture: `%s'"), string);
2446
2447 *input_line_pointer = e;
2448 }
2449 else
2450 as_bad (_("missing cpu architecture"));
2451
fddf5b5b
AM		 2452 no_cond_jump_promotion = 0;
2453 if (*input_line_pointer == ','
29b0f896 2454 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2455 {
2456 char *string = ++input_line_pointer;
2457 int e = get_symbol_end ();
2458
2459 if (strcmp (string, "nojumps") == 0)
2460 no_cond_jump_promotion = 1;
2461 else if (strcmp (string, "jumps") == 0)
2462 ;
2463 else
2464 as_bad (_("no such architecture modifier: `%s'"), string);
2465
2466 *input_line_pointer = e;
2467 }
2468
e413e4e9
AM		 2469 demand_empty_rest_of_line ();
2470}
2471
8a9036a4
L		 2472enum bfd_architecture
2473i386_arch (void)
2474{
3632d14b 2475 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2476 {
2477 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2478 || flag_code != CODE_64BIT)
2479 as_fatal (_("Intel L1OM is 64bit ELF only"));
2480 return bfd_arch_l1om;
2481 }
7a9068fe
L		 2482 else if (cpu_arch_isa == PROCESSOR_K1OM)
2483 {
2484 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2485 || flag_code != CODE_64BIT)
2486 as_fatal (_("Intel K1OM is 64bit ELF only"));
2487 return bfd_arch_k1om;
2488 }
8a9036a4
L		 2489 else
2490 return bfd_arch_i386;
2491}
2492
b9d79e03 2493unsigned long
7016a5d5 2494i386_mach (void)
b9d79e03 2495{
351f65ca 2496 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2497 {
3632d14b 2498 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2499 {
351f65ca
L		 2500 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2501 || default_arch[6] != '\0')
8a9036a4
L		 2502 as_fatal (_("Intel L1OM is 64bit ELF only"));
2503 return bfd_mach_l1om;
2504 }
7a9068fe
L		 2505 else if (cpu_arch_isa == PROCESSOR_K1OM)
2506 {
2507 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2508 || default_arch[6] != '\0')
2509 as_fatal (_("Intel K1OM is 64bit ELF only"));
2510 return bfd_mach_k1om;
2511 }
351f65ca 2512 else if (default_arch[6] == '\0')
8a9036a4 2513 return bfd_mach_x86_64;
351f65ca
L		 2514 else
2515 return bfd_mach_x64_32;
8a9036a4 2516 }
b9d79e03
JH		 2517 else if (!strcmp (default_arch, "i386"))
2518 return bfd_mach_i386_i386;
2519 else
2b5d6a91 2520 as_fatal (_("unknown architecture"));
b9d79e03 2521}
b9d79e03 2522\f
252b5132 2523void
7016a5d5 2524md_begin (void)
252b5132
RH		 2525{
2526 const char *hash_err;
2527
47926f60 2528 /* Initialize op_hash hash table. */
252b5132
RH		 2529 op_hash = hash_new ();
2530
2531 {
d3ce72d0 2532 const insn_template *optab;
29b0f896 2533 templates *core_optab;
252b5132 2534
47926f60
KH		 2535 /* Setup for loop. */
2536 optab = i386_optab;
252b5132
RH		 2537 core_optab = (templates *) xmalloc (sizeof (templates));
2538 core_optab->start = optab;
2539
2540 while (1)
2541 {
2542 ++optab;
2543 if (optab->name == NULL
2544 || strcmp (optab->name, (optab - 1)->name) != 0)
2545 {
2546 /* different name --> ship out current template list;
47926f60 2547 add to hash table; & begin anew. */
252b5132
RH		 2548 core_optab->end = optab;
2549 hash_err = hash_insert (op_hash,
2550 (optab - 1)->name,
5a49b8ac 2551 (void *) core_optab);
252b5132
RH		 2552 if (hash_err)
2553 {
b37df7c4 2554 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2555 (optab - 1)->name,
2556 hash_err);
2557 }
2558 if (optab->name == NULL)
2559 break;
2560 core_optab = (templates *) xmalloc (sizeof (templates));
2561 core_optab->start = optab;
2562 }
2563 }
2564 }
2565
47926f60 2566 /* Initialize reg_hash hash table. */
252b5132
RH		 2567 reg_hash = hash_new ();
2568 {
29b0f896 2569 const reg_entry *regtab;
c3fe08fa 2570 unsigned int regtab_size = i386_regtab_size;
252b5132 2571
c3fe08fa 2572 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2573 {
5a49b8ac 2574 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2575 if (hash_err)
b37df7c4 2576 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2577 regtab->reg_name,
2578 hash_err);
252b5132
RH		 2579 }
2580 }
2581
47926f60 2582 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2583 {
29b0f896
AM		 2584 int c;
2585 char *p;
252b5132
RH		 2586
2587 for (c = 0; c < 256; c++)
2588 {
3882b010 2589 if (ISDIGIT (c))
252b5132
RH		 2590 {
2591 digit_chars[c] = c;
2592 mnemonic_chars[c] = c;
2593 register_chars[c] = c;
2594 operand_chars[c] = c;
2595 }
3882b010 2596 else if (ISLOWER (c))
252b5132
RH		 2597 {
2598 mnemonic_chars[c] = c;
2599 register_chars[c] = c;
2600 operand_chars[c] = c;
2601 }
3882b010 2602 else if (ISUPPER (c))
252b5132 2603 {
3882b010 2604 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2605 register_chars[c] = mnemonic_chars[c];
2606 operand_chars[c] = c;
2607 }
43234a1e
L		 2608 else if (c == '{' || c == '}')
2609 operand_chars[c] = c;
252b5132 2610
3882b010 2611 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2612 identifier_chars[c] = c;
2613 else if (c >= 128)
2614 {
2615 identifier_chars[c] = c;
2616 operand_chars[c] = c;
2617 }
2618 }
2619
2620#ifdef LEX_AT
2621 identifier_chars['@'] = '@';
32137342
NC		 2622#endif
2623#ifdef LEX_QM
2624 identifier_chars['?'] = '?';
2625 operand_chars['?'] = '?';
252b5132 2626#endif
252b5132 2627 digit_chars['-'] = '-';
c0f3af97 2628 mnemonic_chars['_'] = '_';
791fe849 2629 mnemonic_chars['-'] = '-';
0003779b 2630 mnemonic_chars['.'] = '.';
252b5132
RH		 2631 identifier_chars['_'] = '_';
2632 identifier_chars['.'] = '.';
2633
2634 for (p = operand_special_chars; *p != '\0'; p++)
2635 operand_chars[(unsigned char) *p] = *p;
2636 }
2637
a4447b93
RH		 2638 if (flag_code == CODE_64BIT)
2639 {
ca19b261
KT		 2640#if defined (OBJ_COFF) && defined (TE_PE)
2641 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2642 ? 32 : 16);
2643#else
a4447b93 2644 x86_dwarf2_return_column = 16;
ca19b261 2645#endif
61ff971f 2646 x86_cie_data_alignment = -8;
a4447b93
RH		 2647 }
2648 else
2649 {
2650 x86_dwarf2_return_column = 8;
2651 x86_cie_data_alignment = -4;
2652 }
252b5132
RH		 2653}
2654
2655void
e3bb37b5 2656i386_print_statistics (FILE *file)
252b5132
RH		 2657{
2658 hash_print_statistics (file, "i386 opcode", op_hash);
2659 hash_print_statistics (file, "i386 register", reg_hash);
2660}
2661\f
252b5132
RH		 2662#ifdef DEBUG386
2663
ce8a8b2f 2664/* Debugging routines for md_assemble. */
d3ce72d0 2665static void pte (insn_template *);
40fb9820 2666static void pt (i386_operand_type);
e3bb37b5
L		 2667static void pe (expressionS *);
2668static void ps (symbolS *);
252b5132
RH		 2669
2670static void
e3bb37b5 2671pi (char *line, i386_insn *x)
252b5132 2672{
09137c09 2673 unsigned int j;
252b5132
RH		 2674
2675 fprintf (stdout, "%s: template ", line);
2676 pte (&x->tm);
09f131f2
JH		 2677 fprintf (stdout, " address: base %s index %s scale %x\n",
2678 x->base_reg ? x->base_reg->reg_name : "none",
2679 x->index_reg ? x->index_reg->reg_name : "none",
2680 x->log2_scale_factor);
2681 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2682 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2683 fprintf (stdout, " sib: base %x index %x scale %x\n",
2684 x->sib.base, x->sib.index, x->sib.scale);
2685 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2686 (x->rex & REX_W) != 0,
2687 (x->rex & REX_R) != 0,
2688 (x->rex & REX_X) != 0,
2689 (x->rex & REX_B) != 0);
09137c09 2690 for (j = 0; j < x->operands; j++)
252b5132 2691 {
09137c09
SP		 2692 fprintf (stdout, " #%d: ", j + 1);
2693 pt (x->types[j]);
252b5132 2694 fprintf (stdout, "\n");
09137c09
SP		 2695 if (x->types[j].bitfield.reg8
2696 || x->types[j].bitfield.reg16
2697 || x->types[j].bitfield.reg32
2698 || x->types[j].bitfield.reg64
2699 || x->types[j].bitfield.regmmx
2700 || x->types[j].bitfield.regxmm
2701 || x->types[j].bitfield.regymm
43234a1e 2702 || x->types[j].bitfield.regzmm
09137c09
SP		 2703 || x->types[j].bitfield.sreg2
2704 || x->types[j].bitfield.sreg3
2705 || x->types[j].bitfield.control
2706 || x->types[j].bitfield.debug
2707 || x->types[j].bitfield.test)
2708 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2709 if (operand_type_check (x->types[j], imm))
2710 pe (x->op[j].imms);
2711 if (operand_type_check (x->types[j], disp))
2712 pe (x->op[j].disps);
252b5132
RH		 2713 }
2714}
2715
2716static void
d3ce72d0 2717pte (insn_template *t)
252b5132 2718{
09137c09 2719 unsigned int j;
252b5132 2720 fprintf (stdout, " %d operands ", t->operands);
47926f60 2721 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2722 if (t->extension_opcode != None)
2723 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2724 if (t->opcode_modifier.d)
252b5132 2725 fprintf (stdout, "D");
40fb9820 2726 if (t->opcode_modifier.w)
252b5132
RH		 2727 fprintf (stdout, "W");
2728 fprintf (stdout, "\n");
09137c09 2729 for (j = 0; j < t->operands; j++)
252b5132 2730 {
09137c09
SP		 2731 fprintf (stdout, " #%d type ", j + 1);
2732 pt (t->operand_types[j]);
252b5132
RH		 2733 fprintf (stdout, "\n");
2734 }
2735}
2736
2737static void
e3bb37b5 2738pe (expressionS *e)
252b5132 2739{
24eab124 2740 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2741 fprintf (stdout, " add_number %ld (%lx)\n",
2742 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2743 if (e->X_add_symbol)
2744 {
2745 fprintf (stdout, " add_symbol ");
2746 ps (e->X_add_symbol);
2747 fprintf (stdout, "\n");
2748 }
2749 if (e->X_op_symbol)
2750 {
2751 fprintf (stdout, " op_symbol ");
2752 ps (e->X_op_symbol);
2753 fprintf (stdout, "\n");
2754 }
2755}
2756
2757static void
e3bb37b5 2758ps (symbolS *s)
252b5132
RH		 2759{
2760 fprintf (stdout, "%s type %s%s",
2761 S_GET_NAME (s),
2762 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2763 segment_name (S_GET_SEGMENT (s)));
2764}
2765
7b81dfbb 2766static struct type_name
252b5132 2767 {
40fb9820
L		 2768 i386_operand_type mask;
2769 const char *name;
252b5132 2770 }
7b81dfbb 2771const type_names[] =
252b5132 2772{
40fb9820
L		 2773 { OPERAND_TYPE_REG8, "r8" },
2774 { OPERAND_TYPE_REG16, "r16" },
2775 { OPERAND_TYPE_REG32, "r32" },
2776 { OPERAND_TYPE_REG64, "r64" },
2777 { OPERAND_TYPE_IMM8, "i8" },
2778 { OPERAND_TYPE_IMM8, "i8s" },
2779 { OPERAND_TYPE_IMM16, "i16" },
2780 { OPERAND_TYPE_IMM32, "i32" },
2781 { OPERAND_TYPE_IMM32S, "i32s" },
2782 { OPERAND_TYPE_IMM64, "i64" },
2783 { OPERAND_TYPE_IMM1, "i1" },
2784 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2785 { OPERAND_TYPE_DISP8, "d8" },
2786 { OPERAND_TYPE_DISP16, "d16" },
2787 { OPERAND_TYPE_DISP32, "d32" },
2788 { OPERAND_TYPE_DISP32S, "d32s" },
2789 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2790 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2791 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2792 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2793 { OPERAND_TYPE_CONTROL, "control reg" },
2794 { OPERAND_TYPE_TEST, "test reg" },
2795 { OPERAND_TYPE_DEBUG, "debug reg" },
2796 { OPERAND_TYPE_FLOATREG, "FReg" },
2797 { OPERAND_TYPE_FLOATACC, "FAcc" },
2798 { OPERAND_TYPE_SREG2, "SReg2" },
2799 { OPERAND_TYPE_SREG3, "SReg3" },
2800 { OPERAND_TYPE_ACC, "Acc" },
2801 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2802 { OPERAND_TYPE_REGMMX, "rMMX" },
2803 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2804 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2805 { OPERAND_TYPE_REGZMM, "rZMM" },
2806 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2807 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2808};
2809
2810static void
40fb9820 2811pt (i386_operand_type t)
252b5132 2812{
40fb9820 2813 unsigned int j;
c6fb90c8 2814 i386_operand_type a;
252b5132 2815
40fb9820 2816 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2817 {
2818 a = operand_type_and (t, type_names[j].mask);
0349dc08 2819 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2820 fprintf (stdout, "%s, ", type_names[j].name);
2821 }
252b5132
RH		 2822 fflush (stdout);
2823}
2824
2825#endif /* DEBUG386 */
2826\f
252b5132 2827static bfd_reloc_code_real_type
3956db08 2828reloc (unsigned int size,
64e74474
AM		 2829 int pcrel,
2830 int sign,
c3320543 2831 int bnd_prefix,
64e74474 2832 bfd_reloc_code_real_type other)
252b5132 2833{
47926f60 2834 if (other != NO_RELOC)
3956db08 2835 {
91d6fa6a 2836 reloc_howto_type *rel;
3956db08
JB		 2837
2838 if (size == 8)
2839 switch (other)
2840 {
64e74474
AM		 2841 case BFD_RELOC_X86_64_GOT32:
2842 return BFD_RELOC_X86_64_GOT64;
2843 break;
553d1284
L		 2844 case BFD_RELOC_X86_64_GOTPLT64:
2845 return BFD_RELOC_X86_64_GOTPLT64;
2846 break;
64e74474
AM		 2847 case BFD_RELOC_X86_64_PLTOFF64:
2848 return BFD_RELOC_X86_64_PLTOFF64;
2849 break;
2850 case BFD_RELOC_X86_64_GOTPC32:
2851 other = BFD_RELOC_X86_64_GOTPC64;
2852 break;
2853 case BFD_RELOC_X86_64_GOTPCREL:
2854 other = BFD_RELOC_X86_64_GOTPCREL64;
2855 break;
2856 case BFD_RELOC_X86_64_TPOFF32:
2857 other = BFD_RELOC_X86_64_TPOFF64;
2858 break;
2859 case BFD_RELOC_X86_64_DTPOFF32:
2860 other = BFD_RELOC_X86_64_DTPOFF64;
2861 break;
2862 default:
2863 break;
3956db08 2864 }
e05278af 2865
8ce3d284 2866#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2867 if (other == BFD_RELOC_SIZE32)
2868 {
2869 if (size == 8)
1ab668bf 2870 other = BFD_RELOC_SIZE64;
8fd4256d 2871 if (pcrel)
1ab668bf
AM		 2872 {
2873 as_bad (_("there are no pc-relative size relocations"));
2874 return NO_RELOC;
2875 }
8fd4256d 2876 }
8ce3d284 2877#endif
8fd4256d 2878
e05278af 2879 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2880 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2881 sign = -1;
2882
91d6fa6a
NC		 2883 rel = bfd_reloc_type_lookup (stdoutput, other);
2884 if (!rel)
3956db08 2885 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2886 else if (size != bfd_get_reloc_size (rel))
3956db08 2887 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2888 bfd_get_reloc_size (rel),
3956db08 2889 size);
91d6fa6a 2890 else if (pcrel && !rel->pc_relative)
3956db08 2891 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2892 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2893 && !sign)
91d6fa6a 2894 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2895 && sign > 0))
3956db08
JB		 2896 as_bad (_("relocated field and relocation type differ in signedness"));
2897 else
2898 return other;
2899 return NO_RELOC;
2900 }
252b5132
RH		 2901
2902 if (pcrel)
2903 {
3e73aa7c 2904 if (!sign)
3956db08 2905 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2906 switch (size)
2907 {
2908 case 1: return BFD_RELOC_8_PCREL;
2909 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2910 case 4: return (bnd_prefix && object_64bit
2911 ? BFD_RELOC_X86_64_PC32_BND
2912 : BFD_RELOC_32_PCREL);
d6ab8113 2913 case 8: return BFD_RELOC_64_PCREL;
252b5132 2914 }
3956db08 2915 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2916 }
2917 else
2918 {
3956db08 2919 if (sign > 0)
e5cb08ac 2920 switch (size)
3e73aa7c
JH		 2921 {
2922 case 4: return BFD_RELOC_X86_64_32S;
2923 }
2924 else
2925 switch (size)
2926 {
2927 case 1: return BFD_RELOC_8;
2928 case 2: return BFD_RELOC_16;
2929 case 4: return BFD_RELOC_32;
2930 case 8: return BFD_RELOC_64;
2931 }
3956db08
JB		 2932 as_bad (_("cannot do %s %u byte relocation"),
2933 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2934 }
2935
0cc9e1d3 2936 return NO_RELOC;
252b5132
RH		 2937}
2938
47926f60
KH		 2939/* Here we decide which fixups can be adjusted to make them relative to
2940 the beginning of the section instead of the symbol. Basically we need
2941 to make sure that the dynamic relocations are done correctly, so in
2942 some cases we force the original symbol to be used. */
2943
252b5132 2944int
e3bb37b5 2945tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2946{
6d249963 2947#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2948 if (!IS_ELF)
31312f95
AM		 2949 return 1;
2950
a161fe53
AM		 2951 /* Don't adjust pc-relative references to merge sections in 64-bit
2952 mode. */
2953 if (use_rela_relocations
2954 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2955 && fixP->fx_pcrel)
252b5132 2956 return 0;
31312f95 2957
8d01d9a9
AJ		 2958 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2959 and changed later by validate_fix. */
2960 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2961 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2962 return 0;
2963
8fd4256d
L		 2964 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2965 for size relocations. */
2966 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2967 || fixP->fx_r_type == BFD_RELOC_SIZE64
2968 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2969 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2970 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2971 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2972 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2973 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2974 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2975 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2976 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2977 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2978 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2979 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2980 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2981 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2982 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2983 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2984 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2985 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2986 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2987 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2988 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2989 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2990 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2991 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2992 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2993 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2994 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2995 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2996 return 0;
31312f95 2997#endif
252b5132
RH		 2998 return 1;
2999}
252b5132 3000
b4cac588 3001static int
e3bb37b5 3002intel_float_operand (const char *mnemonic)
252b5132 3003{
9306ca4a
JB		 3004 /* Note that the value returned is meaningful only for opcodes with (memory)
3005 operands, hence the code here is free to improperly handle opcodes that
3006 have no operands (for better performance and smaller code). */
3007
3008 if (mnemonic[0] != 'f')
3009 return 0; /* non-math */
3010
3011 switch (mnemonic[1])
3012 {
3013 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3014 the fs segment override prefix not currently handled because no
3015 call path can make opcodes without operands get here */
3016 case 'i':
3017 return 2 /* integer op */;
3018 case 'l':
3019 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3020 return 3; /* fldcw/fldenv */
3021 break;
3022 case 'n':
3023 if (mnemonic[2] != 'o' /* fnop */)
3024 return 3; /* non-waiting control op */
3025 break;
3026 case 'r':
3027 if (mnemonic[2] == 's')
3028 return 3; /* frstor/frstpm */
3029 break;
3030 case 's':
3031 if (mnemonic[2] == 'a')
3032 return 3; /* fsave */
3033 if (mnemonic[2] == 't')
3034 {
3035 switch (mnemonic[3])
3036 {
3037 case 'c': /* fstcw */
3038 case 'd': /* fstdw */
3039 case 'e': /* fstenv */
3040 case 's': /* fsts[gw] */
3041 return 3;
3042 }
3043 }
3044 break;
3045 case 'x':
3046 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3047 return 0; /* fxsave/fxrstor are not really math ops */
3048 break;
3049 }
252b5132 3050
9306ca4a 3051 return 1;
252b5132
RH		 3052}
3053
c0f3af97
L		 3054/* Build the VEX prefix. */
3055
3056static void
d3ce72d0 3057build_vex_prefix (const insn_template *t)
c0f3af97
L		 3058{
3059 unsigned int register_specifier;
3060 unsigned int implied_prefix;
3061 unsigned int vector_length;
3062
3063 /* Check register specifier. */
3064 if (i.vex.register_specifier)
43234a1e
L		 3065 {
3066 register_specifier =
3067 ~register_number (i.vex.register_specifier) & 0xf;
3068 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3069 }
c0f3af97
L		 3070 else
3071 register_specifier = 0xf;
3072
fa99fab2
L		 3073 /* Use 2-byte VEX prefix by swappping destination and source
3074 operand. */
3075 if (!i.swap_operand
3076 && i.operands == i.reg_operands
7f399153 3077 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3078 && i.tm.opcode_modifier.s
3079 && i.rex == REX_B)
3080 {
3081 unsigned int xchg = i.operands - 1;
3082 union i386_op temp_op;
3083 i386_operand_type temp_type;
3084
3085 temp_type = i.types[xchg];
3086 i.types[xchg] = i.types[0];
3087 i.types[0] = temp_type;
3088 temp_op = i.op[xchg];
3089 i.op[xchg] = i.op[0];
3090 i.op[0] = temp_op;
3091
9c2799c2 3092 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3093
3094 i.rex = REX_R;
3095 xchg = i.rm.regmem;
3096 i.rm.regmem = i.rm.reg;
3097 i.rm.reg = xchg;
3098
3099 /* Use the next insn. */
3100 i.tm = t[1];
3101 }
3102
539f890d
L		 3103 if (i.tm.opcode_modifier.vex == VEXScalar)
3104 vector_length = avxscalar;
3105 else
3106 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3107
3108 switch ((i.tm.base_opcode >> 8) & 0xff)
3109 {
3110 case 0:
3111 implied_prefix = 0;
3112 break;
3113 case DATA_PREFIX_OPCODE:
3114 implied_prefix = 1;
3115 break;
3116 case REPE_PREFIX_OPCODE:
3117 implied_prefix = 2;
3118 break;
3119 case REPNE_PREFIX_OPCODE:
3120 implied_prefix = 3;
3121 break;
3122 default:
3123 abort ();
3124 }
3125
3126 /* Use 2-byte VEX prefix if possible. */
7f399153 3127 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3128 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3129 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3130 {
3131 /* 2-byte VEX prefix. */
3132 unsigned int r;
3133
3134 i.vex.length = 2;
3135 i.vex.bytes[0] = 0xc5;
3136
3137 /* Check the REX.R bit. */
3138 r = (i.rex & REX_R) ? 0 : 1;
3139 i.vex.bytes[1] = (r << 7
3140 | register_specifier << 3
3141 | vector_length << 2
3142 | implied_prefix);
3143 }
3144 else
3145 {
3146 /* 3-byte VEX prefix. */
3147 unsigned int m, w;
3148
f88c9eb0 3149 i.vex.length = 3;
f88c9eb0 3150
7f399153 3151 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3152 {
7f399153
L		 3153 case VEX0F:
3154 m = 0x1;
80de6e00 3155 i.vex.bytes[0] = 0xc4;
7f399153
L		 3156 break;
3157 case VEX0F38:
3158 m = 0x2;
80de6e00 3159 i.vex.bytes[0] = 0xc4;
7f399153
L		 3160 break;
3161 case VEX0F3A:
3162 m = 0x3;
80de6e00 3163 i.vex.bytes[0] = 0xc4;
7f399153
L		 3164 break;
3165 case XOP08:
5dd85c99
SP		 3166 m = 0x8;
3167 i.vex.bytes[0] = 0x8f;
7f399153
L		 3168 break;
3169 case XOP09:
f88c9eb0
SP		 3170 m = 0x9;
3171 i.vex.bytes[0] = 0x8f;
7f399153
L		 3172 break;
3173 case XOP0A:
f88c9eb0
SP		 3174 m = 0xa;
3175 i.vex.bytes[0] = 0x8f;
7f399153
L		 3176 break;
3177 default:
3178 abort ();
f88c9eb0 3179 }
c0f3af97 3180
c0f3af97
L		 3181 /* The high 3 bits of the second VEX byte are 1's compliment
3182 of RXB bits from REX. */
3183 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3184
3185 /* Check the REX.W bit. */
3186 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3187 if (i.tm.opcode_modifier.vexw == VEXW1)
3188 w = 1;
c0f3af97
L		 3189
3190 i.vex.bytes[2] = (w << 7
3191 | register_specifier << 3
3192 | vector_length << 2
3193 | implied_prefix);
3194 }
3195}
3196
43234a1e
L		 3197/* Build the EVEX prefix. */
3198
3199static void
3200build_evex_prefix (void)
3201{
3202 unsigned int register_specifier;
3203 unsigned int implied_prefix;
3204 unsigned int m, w;
3205 rex_byte vrex_used = 0;
3206
3207 /* Check register specifier. */
3208 if (i.vex.register_specifier)
3209 {
3210 gas_assert ((i.vrex & REX_X) == 0);
3211
3212 register_specifier = i.vex.register_specifier->reg_num;
3213 if ((i.vex.register_specifier->reg_flags & RegRex))
3214 register_specifier += 8;
3215 /* The upper 16 registers are encoded in the fourth byte of the
3216 EVEX prefix. */
3217 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3218 i.vex.bytes[3] = 0x8;
3219 register_specifier = ~register_specifier & 0xf;
3220 }
3221 else
3222 {
3223 register_specifier = 0xf;
3224
3225 /* Encode upper 16 vector index register in the fourth byte of
3226 the EVEX prefix. */
3227 if (!(i.vrex & REX_X))
3228 i.vex.bytes[3] = 0x8;
3229 else
3230 vrex_used |= REX_X;
3231 }
3232
3233 switch ((i.tm.base_opcode >> 8) & 0xff)
3234 {
3235 case 0:
3236 implied_prefix = 0;
3237 break;
3238 case DATA_PREFIX_OPCODE:
3239 implied_prefix = 1;
3240 break;
3241 case REPE_PREFIX_OPCODE:
3242 implied_prefix = 2;
3243 break;
3244 case REPNE_PREFIX_OPCODE:
3245 implied_prefix = 3;
3246 break;
3247 default:
3248 abort ();
3249 }
3250
3251 /* 4 byte EVEX prefix. */
3252 i.vex.length = 4;
3253 i.vex.bytes[0] = 0x62;
3254
3255 /* mmmm bits. */
3256 switch (i.tm.opcode_modifier.vexopcode)
3257 {
3258 case VEX0F:
3259 m = 1;
3260 break;
3261 case VEX0F38:
3262 m = 2;
3263 break;
3264 case VEX0F3A:
3265 m = 3;
3266 break;
3267 default:
3268 abort ();
3269 break;
3270 }
3271
3272 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3273 bits from REX. */
3274 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3275
3276 /* The fifth bit of the second EVEX byte is 1's compliment of the
3277 REX_R bit in VREX. */
3278 if (!(i.vrex & REX_R))
3279 i.vex.bytes[1] |= 0x10;
3280 else
3281 vrex_used |= REX_R;
3282
3283 if ((i.reg_operands + i.imm_operands) == i.operands)
3284 {
3285 /* When all operands are registers, the REX_X bit in REX is not
3286 used. We reuse it to encode the upper 16 registers, which is
3287 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3288 as 1's compliment. */
3289 if ((i.vrex & REX_B))
3290 {
3291 vrex_used |= REX_B;
3292 i.vex.bytes[1] &= ~0x40;
3293 }
3294 }
3295
3296 /* EVEX instructions shouldn't need the REX prefix. */
3297 i.vrex &= ~vrex_used;
3298 gas_assert (i.vrex == 0);
3299
3300 /* Check the REX.W bit. */
3301 w = (i.rex & REX_W) ? 1 : 0;
3302 if (i.tm.opcode_modifier.vexw)
3303 {
3304 if (i.tm.opcode_modifier.vexw == VEXW1)
3305 w = 1;
3306 }
3307 /* If w is not set it means we are dealing with WIG instruction. */
3308 else if (!w)
3309 {
3310 if (evexwig == evexw1)
3311 w = 1;
3312 }
3313
3314 /* Encode the U bit. */
3315 implied_prefix |= 0x4;
3316
3317 /* The third byte of the EVEX prefix. */
3318 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3319
3320 /* The fourth byte of the EVEX prefix. */
3321 /* The zeroing-masking bit. */
3322 if (i.mask && i.mask->zeroing)
3323 i.vex.bytes[3] |= 0x80;
3324
3325 /* Don't always set the broadcast bit if there is no RC. */
3326 if (!i.rounding)
3327 {
3328 /* Encode the vector length. */
3329 unsigned int vec_length;
3330
3331 switch (i.tm.opcode_modifier.evex)
3332 {
3333 case EVEXLIG: /* LL' is ignored */
3334 vec_length = evexlig << 5;
3335 break;
3336 case EVEX128:
3337 vec_length = 0 << 5;
3338 break;
3339 case EVEX256:
3340 vec_length = 1 << 5;
3341 break;
3342 case EVEX512:
3343 vec_length = 2 << 5;
3344 break;
3345 default:
3346 abort ();
3347 break;
3348 }
3349 i.vex.bytes[3] |= vec_length;
3350 /* Encode the broadcast bit. */
3351 if (i.broadcast)
3352 i.vex.bytes[3] |= 0x10;
3353 }
3354 else
3355 {
3356 if (i.rounding->type != saeonly)
3357 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3358 else
d3d3c6db 3359 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3360 }
3361
3362 if (i.mask && i.mask->mask)
3363 i.vex.bytes[3] |= i.mask->mask->reg_num;
3364}
3365
65da13b5
L		 3366static void
3367process_immext (void)
3368{
3369 expressionS *exp;
3370
4c692bc7
JB		 3371 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3372 && i.operands > 0)
65da13b5 3373 {
4c692bc7
JB		 3374 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3375 with an opcode suffix which is coded in the same place as an
3376 8-bit immediate field would be.
3377 Here we check those operands and remove them afterwards. */
65da13b5
L		 3378 unsigned int x;
3379
3380 for (x = 0; x < i.operands; x++)
4c692bc7 3381 if (register_number (i.op[x].regs) != x)
65da13b5 3382 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3383 register_prefix, i.op[x].regs->reg_name, x + 1,
3384 i.tm.name);
3385
3386 i.operands = 0;
65da13b5
L		 3387 }
3388
c0f3af97 3389 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3390 which is coded in the same place as an 8-bit immediate field
3391 would be. Here we fake an 8-bit immediate operand from the
3392 opcode suffix stored in tm.extension_opcode.
3393
c1e679ec 3394 AVX instructions also use this encoding, for some of
c0f3af97 3395 3 argument instructions. */
65da13b5 3396
43234a1e 3397 gas_assert (i.imm_operands <= 1
7ab9ffdd 3398 && (i.operands <= 2
43234a1e
L		 3399 || ((i.tm.opcode_modifier.vex
3400 || i.tm.opcode_modifier.evex)
7ab9ffdd 3401 && i.operands <= 4)));
65da13b5
L		 3402
3403 exp = &im_expressions[i.imm_operands++];
3404 i.op[i.operands].imms = exp;
3405 i.types[i.operands] = imm8;
3406 i.operands++;
3407 exp->X_op = O_constant;
3408 exp->X_add_number = i.tm.extension_opcode;
3409 i.tm.extension_opcode = None;
3410}
3411
42164a71
L		 3412
3413static int
3414check_hle (void)
3415{
3416 switch (i.tm.opcode_modifier.hleprefixok)
3417 {
3418 default:
3419 abort ();
82c2def5 3420 case HLEPrefixNone:
165de32a
L		 3421 as_bad (_("invalid instruction `%s' after `%s'"),
3422 i.tm.name, i.hle_prefix);
42164a71 3423 return 0;
82c2def5 3424 case HLEPrefixLock:
42164a71
L		 3425 if (i.prefix[LOCK_PREFIX])
3426 return 1;
165de32a 3427 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3428 return 0;
82c2def5 3429 case HLEPrefixAny:
42164a71 3430 return 1;
82c2def5 3431 case HLEPrefixRelease:
42164a71
L		 3432 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3433 {
3434 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3435 i.tm.name);
3436 return 0;
3437 }
3438 if (i.mem_operands == 0
3439 || !operand_type_check (i.types[i.operands - 1], anymem))
3440 {
3441 as_bad (_("memory destination needed for instruction `%s'"
3442 " after `xrelease'"), i.tm.name);
3443 return 0;
3444 }
3445 return 1;
3446 }
3447}
3448
252b5132
RH		 3449/* This is the guts of the machine-dependent assembler. LINE points to a
3450 machine dependent instruction. This function is supposed to emit
3451 the frags/bytes it assembles to. */
3452
3453void
65da13b5 3454md_assemble (char *line)
252b5132 3455{
40fb9820 3456 unsigned int j;
252b5132 3457 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3458 const insn_template *t;
252b5132 3459
47926f60 3460 /* Initialize globals. */
252b5132
RH		 3461 memset (&i, '\0', sizeof (i));
3462 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3463 i.reloc[j] = NO_RELOC;
252b5132
RH		 3464 memset (disp_expressions, '\0', sizeof (disp_expressions));
3465 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3466 save_stack_p = save_stack;
252b5132
RH		 3467
3468 /* First parse an instruction mnemonic & call i386_operand for the operands.
3469 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3470 start of a (possibly prefixed) mnemonic. */
252b5132 3471
29b0f896
AM		 3472 line = parse_insn (line, mnemonic);
3473 if (line == NULL)
3474 return;
252b5132 3475
29b0f896 3476 line = parse_operands (line, mnemonic);
ee86248c 3477 this_operand = -1;
29b0f896
AM		 3478 if (line == NULL)
3479 return;
252b5132 3480
29b0f896
AM		 3481 /* Now we've parsed the mnemonic into a set of templates, and have the
3482 operands at hand. */
3483
3484 /* All intel opcodes have reversed operands except for "bound" and
3485 "enter". We also don't reverse intersegment "jmp" and "call"
3486 instructions with 2 immediate operands so that the immediate segment
050dfa73 3487 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3488 if (intel_syntax
3489 && i.operands > 1
29b0f896 3490 && (strcmp (mnemonic, "bound") != 0)
30123838 3491 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3492 && !(operand_type_check (i.types[0], imm)
3493 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3494 swap_operands ();
3495
ec56d5c0
JB		 3496 /* The order of the immediates should be reversed
3497 for 2 immediates extrq and insertq instructions */
3498 if (i.imm_operands == 2
3499 && (strcmp (mnemonic, "extrq") == 0
3500 || strcmp (mnemonic, "insertq") == 0))
3501 swap_2_operands (0, 1);
3502
29b0f896
AM		 3503 if (i.imm_operands)
3504 optimize_imm ();
3505
b300c311
L		 3506 /* Don't optimize displacement for movabs since it only takes 64bit
3507 displacement. */
3508 if (i.disp_operands
a501d77e 3509 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3510 && (flag_code != CODE_64BIT
3511 || strcmp (mnemonic, "movabs") != 0))
3512 optimize_disp ();
29b0f896
AM		 3513
3514 /* Next, we find a template that matches the given insn,
3515 making sure the overlap of the given operands types is consistent
3516 with the template operand types. */
252b5132 3517
fa99fab2 3518 if (!(t = match_template ()))
29b0f896 3519 return;
252b5132 3520
7bab8ab5 3521 if (sse_check != check_none
81f8a913 3522 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3523 && (i.tm.cpu_flags.bitfield.cpusse
3524 || i.tm.cpu_flags.bitfield.cpusse2
3525 || i.tm.cpu_flags.bitfield.cpusse3
3526 || i.tm.cpu_flags.bitfield.cpussse3
3527 || i.tm.cpu_flags.bitfield.cpusse4_1
3528 || i.tm.cpu_flags.bitfield.cpusse4_2))
3529 {
7bab8ab5 3530 (sse_check == check_warning
daf50ae7
L		 3531 ? as_warn
3532 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3533 }
3534
321fd21e
L		 3535 /* Zap movzx and movsx suffix. The suffix has been set from
3536 "word ptr" or "byte ptr" on the source operand in Intel syntax
3537 or extracted from mnemonic in AT&T syntax. But we'll use
3538 the destination register to choose the suffix for encoding. */
3539 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3540 {
321fd21e
L		 3541 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3542 there is no suffix, the default will be byte extension. */
3543 if (i.reg_operands != 2
3544 && !i.suffix
7ab9ffdd 3545 && intel_syntax)
321fd21e
L		 3546 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3547
3548 i.suffix = 0;
cd61ebfe 3549 }
24eab124 3550
40fb9820 3551 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3552 if (!add_prefix (FWAIT_OPCODE))
3553 return;
252b5132 3554
d5de92cf
L		 3555 /* Check if REP prefix is OK. */
3556 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3557 {
3558 as_bad (_("invalid instruction `%s' after `%s'"),
3559 i.tm.name, i.rep_prefix);
3560 return;
3561 }
3562
c1ba0266
L		 3563 /* Check for lock without a lockable instruction. Destination operand
3564 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3565 if (i.prefix[LOCK_PREFIX]
3566 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3567 || i.mem_operands == 0
3568 || (i.tm.base_opcode != 0x86
3569 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3570 {
3571 as_bad (_("expecting lockable instruction after `lock'"));
3572 return;
3573 }
3574
42164a71 3575 /* Check if HLE prefix is OK. */
165de32a 3576 if (i.hle_prefix && !check_hle ())
42164a71
L		 3577 return;
3578
7e8b059b
L		 3579 /* Check BND prefix. */
3580 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3581 as_bad (_("expecting valid branch instruction after `bnd'"));
3582
3583 if (i.tm.cpu_flags.bitfield.cpumpx
3584 && flag_code == CODE_64BIT
3585 && i.prefix[ADDR_PREFIX])
3586 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3587
3588 /* Insert BND prefix. */
3589 if (add_bnd_prefix
3590 && i.tm.opcode_modifier.bndprefixok
3591 && !i.prefix[BND_PREFIX])
3592 add_prefix (BND_PREFIX_OPCODE);
3593
29b0f896 3594 /* Check string instruction segment overrides. */
40fb9820 3595 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3596 {
3597 if (!check_string ())
5dd0794d 3598 return;
fc0763e6 3599 i.disp_operands = 0;
29b0f896 3600 }
5dd0794d 3601
29b0f896
AM		 3602 if (!process_suffix ())
3603 return;
e413e4e9 3604
bc0844ae
L		 3605 /* Update operand types. */
3606 for (j = 0; j < i.operands; j++)
3607 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3608
29b0f896
AM		 3609 /* Make still unresolved immediate matches conform to size of immediate
3610 given in i.suffix. */
3611 if (!finalize_imm ())
3612 return;
252b5132 3613
40fb9820 3614 if (i.types[0].bitfield.imm1)
29b0f896 3615 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3616
9afe6eb8
L		 3617 /* We only need to check those implicit registers for instructions
3618 with 3 operands or less. */
3619 if (i.operands <= 3)
3620 for (j = 0; j < i.operands; j++)
3621 if (i.types[j].bitfield.inoutportreg
3622 || i.types[j].bitfield.shiftcount
3623 || i.types[j].bitfield.acc
3624 || i.types[j].bitfield.floatacc)
3625 i.reg_operands--;
40fb9820 3626
c0f3af97
L		 3627 /* ImmExt should be processed after SSE2AVX. */
3628 if (!i.tm.opcode_modifier.sse2avx
3629 && i.tm.opcode_modifier.immext)
65da13b5 3630 process_immext ();
252b5132 3631
29b0f896
AM		 3632 /* For insns with operands there are more diddles to do to the opcode. */
3633 if (i.operands)
3634 {
3635 if (!process_operands ())
3636 return;
3637 }
40fb9820 3638 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3639 {
3640 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3641 as_warn (_("translating to `%sp'"), i.tm.name);
3642 }
252b5132 3643
9e5e5283
L		 3644 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3645 {
3646 if (flag_code == CODE_16BIT)
3647 {
3648 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3649 i.tm.name);
3650 return;
3651 }
c0f3af97 3652
9e5e5283
L		 3653 if (i.tm.opcode_modifier.vex)
3654 build_vex_prefix (t);
3655 else
3656 build_evex_prefix ();
3657 }
43234a1e 3658
5dd85c99
SP		 3659 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3660 instructions may define INT_OPCODE as well, so avoid this corner
3661 case for those instructions that use MODRM. */
3662 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3663 && !i.tm.opcode_modifier.modrm
3664 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3665 {
3666 i.tm.base_opcode = INT3_OPCODE;
3667 i.imm_operands = 0;
3668 }
252b5132 3669
40fb9820
L		 3670 if ((i.tm.opcode_modifier.jump
3671 || i.tm.opcode_modifier.jumpbyte
3672 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3673 && i.op[0].disps->X_op == O_constant)
3674 {
3675 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3676 the absolute address given by the constant. Since ix86 jumps and
3677 calls are pc relative, we need to generate a reloc. */
3678 i.op[0].disps->X_add_symbol = &abs_symbol;
3679 i.op[0].disps->X_op = O_symbol;
3680 }
252b5132 3681
40fb9820 3682 if (i.tm.opcode_modifier.rex64)
161a04f6 3683 i.rex |= REX_W;
252b5132 3684
29b0f896
AM		 3685 /* For 8 bit registers we need an empty rex prefix. Also if the
3686 instruction already has a prefix, we need to convert old
3687 registers to new ones. */
773f551c 3688
40fb9820 3689 if ((i.types[0].bitfield.reg8
29b0f896 3690 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3691 || (i.types[1].bitfield.reg8
29b0f896 3692 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3693 || ((i.types[0].bitfield.reg8
3694 || i.types[1].bitfield.reg8)
29b0f896
AM		 3695 && i.rex != 0))
3696 {
3697 int x;
726c5dcd 3698
29b0f896
AM		 3699 i.rex |= REX_OPCODE;
3700 for (x = 0; x < 2; x++)
3701 {
3702 /* Look for 8 bit operand that uses old registers. */
40fb9820 3703 if (i.types[x].bitfield.reg8
29b0f896 3704 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3705 {
29b0f896
AM		 3706 /* In case it is "hi" register, give up. */
3707 if (i.op[x].regs->reg_num > 3)
a540244d 3708 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3709 "instruction requiring REX prefix."),
a540244d 3710 register_prefix, i.op[x].regs->reg_name);
773f551c 3711
29b0f896
AM		 3712 /* Otherwise it is equivalent to the extended register.
3713 Since the encoding doesn't change this is merely
3714 cosmetic cleanup for debug output. */
3715
3716 i.op[x].regs = i.op[x].regs + 8;
773f551c 3717 }
29b0f896
AM		 3718 }
3719 }
773f551c 3720
7ab9ffdd 3721 if (i.rex != 0)
29b0f896
AM		 3722 add_prefix (REX_OPCODE | i.rex);
3723
3724 /* We are ready to output the insn. */
3725 output_insn ();
3726}
3727
3728static char *
e3bb37b5 3729parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3730{
3731 char *l = line;
3732 char *token_start = l;
3733 char *mnem_p;
5c6af06e 3734 int supported;
d3ce72d0 3735 const insn_template *t;
b6169b20 3736 char *dot_p = NULL;
29b0f896 3737
29b0f896
AM		 3738 while (1)
3739 {
3740 mnem_p = mnemonic;
3741 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3742 {
b6169b20
L		 3743 if (*mnem_p == '.')
3744 dot_p = mnem_p;
29b0f896
AM		 3745 mnem_p++;
3746 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3747 {
29b0f896
AM		 3748 as_bad (_("no such instruction: `%s'"), token_start);
3749 return NULL;
3750 }
3751 l++;
3752 }
3753 if (!is_space_char (*l)
3754 && *l != END_OF_INSN
e44823cf
JB		 3755 && (intel_syntax
3756 || (*l != PREFIX_SEPARATOR
3757 && *l != ',')))
29b0f896
AM		 3758 {
3759 as_bad (_("invalid character %s in mnemonic"),
3760 output_invalid (*l));
3761 return NULL;
3762 }
3763 if (token_start == l)
3764 {
e44823cf 3765 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3766 as_bad (_("expecting prefix; got nothing"));
3767 else
3768 as_bad (_("expecting mnemonic; got nothing"));
3769 return NULL;
3770 }
45288df1 3771
29b0f896 3772 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3773 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3774
29b0f896
AM		 3775 if (*l != END_OF_INSN
3776 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3777 && current_templates
40fb9820 3778 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3779 {
c6fb90c8 3780 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3781 {
3782 as_bad ((flag_code != CODE_64BIT
3783 ? _("`%s' is only supported in 64-bit mode")
3784 : _("`%s' is not supported in 64-bit mode")),
3785 current_templates->start->name);
3786 return NULL;
3787 }
29b0f896
AM		 3788 /* If we are in 16-bit mode, do not allow addr16 or data16.
3789 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3790 if ((current_templates->start->opcode_modifier.size16
3791 || current_templates->start->opcode_modifier.size32)
29b0f896 3792 && flag_code != CODE_64BIT
40fb9820 3793 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3794 ^ (flag_code == CODE_16BIT)))
3795 {
3796 as_bad (_("redundant %s prefix"),
3797 current_templates->start->name);
3798 return NULL;
45288df1 3799 }
29b0f896
AM		 3800 /* Add prefix, checking for repeated prefixes. */
3801 switch (add_prefix (current_templates->start->base_opcode))
3802 {
c32fa91d 3803 case PREFIX_EXIST:
29b0f896 3804 return NULL;
c32fa91d 3805 case PREFIX_REP:
42164a71 3806 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3807 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3808 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3809 i.bnd_prefix = current_templates->start->name;
42164a71 3810 else
d5de92cf 3811 i.rep_prefix = current_templates->start->name;
29b0f896 3812 break;
c32fa91d
L		 3813 default:
3814 break;
29b0f896
AM		 3815 }
3816 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3817 token_start = ++l;
3818 }
3819 else
3820 break;
3821 }
45288df1 3822
30a55f88 3823 if (!current_templates)
b6169b20 3824 {
f8a5c266
L		 3825 /* Check if we should swap operand or force 32bit displacement in
3826 encoding. */
30a55f88
L		 3827 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3828 i.swap_operand = 1;
8d63c93e 3829 else if (mnem_p - 3 == dot_p
a501d77e
L		 3830 && dot_p[1] == 'd'
3831 && dot_p[2] == '8')
3832 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3833 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3834 && dot_p[1] == 'd'
3835 && dot_p[2] == '3'
3836 && dot_p[3] == '2')
a501d77e 3837 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3838 else
3839 goto check_suffix;
3840 mnem_p = dot_p;
3841 *dot_p = '\0';
d3ce72d0 3842 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3843 }
3844
29b0f896
AM		 3845 if (!current_templates)
3846 {
b6169b20 3847check_suffix:
29b0f896
AM		 3848 /* See if we can get a match by trimming off a suffix. */
3849 switch (mnem_p[-1])
3850 {
3851 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3852 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3853 i.suffix = SHORT_MNEM_SUFFIX;
3854 else
29b0f896
AM		 3855 case BYTE_MNEM_SUFFIX:
3856 case QWORD_MNEM_SUFFIX:
3857 i.suffix = mnem_p[-1];
3858 mnem_p[-1] = '\0';
d3ce72d0
NC		 3859 current_templates = (const templates *) hash_find (op_hash,
3860 mnemonic);
29b0f896
AM		 3861 break;
3862 case SHORT_MNEM_SUFFIX:
3863 case LONG_MNEM_SUFFIX:
3864 if (!intel_syntax)
3865 {
3866 i.suffix = mnem_p[-1];
3867 mnem_p[-1] = '\0';
d3ce72d0
NC		 3868 current_templates = (const templates *) hash_find (op_hash,
3869 mnemonic);
29b0f896
AM		 3870 }
3871 break;
252b5132 3872
29b0f896
AM		 3873 /* Intel Syntax. */
3874 case 'd':
3875 if (intel_syntax)
3876 {
9306ca4a 3877 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3878 i.suffix = SHORT_MNEM_SUFFIX;
3879 else
3880 i.suffix = LONG_MNEM_SUFFIX;
3881 mnem_p[-1] = '\0';
d3ce72d0
NC		 3882 current_templates = (const templates *) hash_find (op_hash,
3883 mnemonic);
29b0f896
AM		 3884 }
3885 break;
3886 }
3887 if (!current_templates)
3888 {
3889 as_bad (_("no such instruction: `%s'"), token_start);
3890 return NULL;
3891 }
3892 }
252b5132 3893
40fb9820
L		 3894 if (current_templates->start->opcode_modifier.jump
3895 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3896 {
3897 /* Check for a branch hint. We allow ",pt" and ",pn" for
3898 predict taken and predict not taken respectively.
3899 I'm not sure that branch hints actually do anything on loop
3900 and jcxz insns (JumpByte) for current Pentium4 chips. They
3901 may work in the future and it doesn't hurt to accept them
3902 now. */
3903 if (l[0] == ',' && l[1] == 'p')
3904 {
3905 if (l[2] == 't')
3906 {
3907 if (!add_prefix (DS_PREFIX_OPCODE))
3908 return NULL;
3909 l += 3;
3910 }
3911 else if (l[2] == 'n')
3912 {
3913 if (!add_prefix (CS_PREFIX_OPCODE))
3914 return NULL;
3915 l += 3;
3916 }
3917 }
3918 }
3919 /* Any other comma loses. */
3920 if (*l == ',')
3921 {
3922 as_bad (_("invalid character %s in mnemonic"),
3923 output_invalid (*l));
3924 return NULL;
3925 }
252b5132 3926
29b0f896 3927 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3928 supported = 0;
3929 for (t = current_templates->start; t < current_templates->end; ++t)
3930 {
c0f3af97
L		 3931 supported |= cpu_flags_match (t);
3932 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3933 goto skip;
5c6af06e 3934 }
3629bb00 3935
c0f3af97 3936 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3937 {
3938 as_bad (flag_code == CODE_64BIT
3939 ? _("`%s' is not supported in 64-bit mode")
3940 : _("`%s' is only supported in 64-bit mode"),
3941 current_templates->start->name);
3942 return NULL;
3943 }
c0f3af97 3944 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3945 {
3629bb00 3946 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3947 current_templates->start->name,
41aacd83 3948 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3949 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3950 return NULL;
29b0f896 3951 }
3629bb00
L		 3952
3953skip:
3954 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3955 && (flag_code != CODE_16BIT))
29b0f896
AM		 3956 {
3957 as_warn (_("use .code16 to ensure correct addressing mode"));
3958 }
252b5132 3959
29b0f896
AM		 3960 return l;
3961}
252b5132 3962
29b0f896 3963static char *
e3bb37b5 3964parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3965{
3966 char *token_start;
3138f287 3967
29b0f896
AM		 3968 /* 1 if operand is pending after ','. */
3969 unsigned int expecting_operand = 0;
252b5132 3970
29b0f896
AM		 3971 /* Non-zero if operand parens not balanced. */
3972 unsigned int paren_not_balanced;
3973
3974 while (*l != END_OF_INSN)
3975 {
3976 /* Skip optional white space before operand. */
3977 if (is_space_char (*l))
3978 ++l;
3979 if (!is_operand_char (*l) && *l != END_OF_INSN)
3980 {
3981 as_bad (_("invalid character %s before operand %d"),
3982 output_invalid (*l),
3983 i.operands + 1);
3984 return NULL;
3985 }
3986 token_start = l; /* after white space */
3987 paren_not_balanced = 0;
3988 while (paren_not_balanced || *l != ',')
3989 {
3990 if (*l == END_OF_INSN)
3991 {
3992 if (paren_not_balanced)
3993 {
3994 if (!intel_syntax)
3995 as_bad (_("unbalanced parenthesis in operand %d."),
3996 i.operands + 1);
3997 else
3998 as_bad (_("unbalanced brackets in operand %d."),
3999 i.operands + 1);
4000 return NULL;
4001 }
4002 else
4003 break; /* we are done */
4004 }
4005 else if (!is_operand_char (*l) && !is_space_char (*l))
4006 {
4007 as_bad (_("invalid character %s in operand %d"),
4008 output_invalid (*l),
4009 i.operands + 1);
4010 return NULL;
4011 }
4012 if (!intel_syntax)
4013 {
4014 if (*l == '(')
4015 ++paren_not_balanced;
4016 if (*l == ')')
4017 --paren_not_balanced;
4018 }
4019 else
4020 {
4021 if (*l == '[')
4022 ++paren_not_balanced;
4023 if (*l == ']')
4024 --paren_not_balanced;
4025 }
4026 l++;
4027 }
4028 if (l != token_start)
4029 { /* Yes, we've read in another operand. */
4030 unsigned int operand_ok;
4031 this_operand = i.operands++;
7d5e4556 4032 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4033 if (i.operands > MAX_OPERANDS)
4034 {
4035 as_bad (_("spurious operands; (%d operands/instruction max)"),
4036 MAX_OPERANDS);
4037 return NULL;
4038 }
4039 /* Now parse operand adding info to 'i' as we go along. */
4040 END_STRING_AND_SAVE (l);
4041
4042 if (intel_syntax)
4043 operand_ok =
4044 i386_intel_operand (token_start,
4045 intel_float_operand (mnemonic));
4046 else
a7619375 4047 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4048
4049 RESTORE_END_STRING (l);
4050 if (!operand_ok)
4051 return NULL;
4052 }
4053 else
4054 {
4055 if (expecting_operand)
4056 {
4057 expecting_operand_after_comma:
4058 as_bad (_("expecting operand after ','; got nothing"));
4059 return NULL;
4060 }
4061 if (*l == ',')
4062 {
4063 as_bad (_("expecting operand before ','; got nothing"));
4064 return NULL;
4065 }
4066 }
7f3f1ea2 4067
29b0f896
AM		 4068 /* Now *l must be either ',' or END_OF_INSN. */
4069 if (*l == ',')
4070 {
4071 if (*++l == END_OF_INSN)
4072 {
4073 /* Just skip it, if it's \n complain. */
4074 goto expecting_operand_after_comma;
4075 }
4076 expecting_operand = 1;
4077 }
4078 }
4079 return l;
4080}
7f3f1ea2 4081
050dfa73 4082static void
4d456e3d 4083swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4084{
4085 union i386_op temp_op;
40fb9820 4086 i386_operand_type temp_type;
050dfa73 4087 enum bfd_reloc_code_real temp_reloc;
4eed87de 4088
050dfa73
MM		 4089 temp_type = i.types[xchg2];
4090 i.types[xchg2] = i.types[xchg1];
4091 i.types[xchg1] = temp_type;
4092 temp_op = i.op[xchg2];
4093 i.op[xchg2] = i.op[xchg1];
4094 i.op[xchg1] = temp_op;
4095 temp_reloc = i.reloc[xchg2];
4096 i.reloc[xchg2] = i.reloc[xchg1];
4097 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4098
4099 if (i.mask)
4100 {
4101 if (i.mask->operand == xchg1)
4102 i.mask->operand = xchg2;
4103 else if (i.mask->operand == xchg2)
4104 i.mask->operand = xchg1;
4105 }
4106 if (i.broadcast)
4107 {
4108 if (i.broadcast->operand == xchg1)
4109 i.broadcast->operand = xchg2;
4110 else if (i.broadcast->operand == xchg2)
4111 i.broadcast->operand = xchg1;
4112 }
4113 if (i.rounding)
4114 {
4115 if (i.rounding->operand == xchg1)
4116 i.rounding->operand = xchg2;
4117 else if (i.rounding->operand == xchg2)
4118 i.rounding->operand = xchg1;
4119 }
050dfa73
MM		 4120}
4121
29b0f896 4122static void
e3bb37b5 4123swap_operands (void)
29b0f896 4124{
b7c61d9a 4125 switch (i.operands)
050dfa73 4126 {
c0f3af97 4127 case 5:
b7c61d9a 4128 case 4:
4d456e3d 4129 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4130 case 3:
4131 case 2:
4d456e3d 4132 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4133 break;
4134 default:
4135 abort ();
29b0f896 4136 }
29b0f896
AM		 4137
4138 if (i.mem_operands == 2)
4139 {
4140 const seg_entry *temp_seg;
4141 temp_seg = i.seg[0];
4142 i.seg[0] = i.seg[1];
4143 i.seg[1] = temp_seg;
4144 }
4145}
252b5132 4146
29b0f896
AM		 4147/* Try to ensure constant immediates are represented in the smallest
4148 opcode possible. */
4149static void
e3bb37b5 4150optimize_imm (void)
29b0f896
AM		 4151{
4152 char guess_suffix = 0;
4153 int op;
252b5132 4154
29b0f896
AM		 4155 if (i.suffix)
4156 guess_suffix = i.suffix;
4157 else if (i.reg_operands)
4158 {
4159 /* Figure out a suffix from the last register operand specified.
4160 We can't do this properly yet, ie. excluding InOutPortReg,
4161 but the following works for instructions with immediates.
4162 In any case, we can't set i.suffix yet. */
4163 for (op = i.operands; --op >= 0;)
40fb9820 4164 if (i.types[op].bitfield.reg8)
7ab9ffdd 4165 {
40fb9820
L		 4166 guess_suffix = BYTE_MNEM_SUFFIX;
4167 break;
4168 }
4169 else if (i.types[op].bitfield.reg16)
252b5132 4170 {
40fb9820
L		 4171 guess_suffix = WORD_MNEM_SUFFIX;
4172 break;
4173 }
4174 else if (i.types[op].bitfield.reg32)
4175 {
4176 guess_suffix = LONG_MNEM_SUFFIX;
4177 break;
4178 }
4179 else if (i.types[op].bitfield.reg64)
4180 {
4181 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4182 break;
252b5132 4183 }
29b0f896
AM		 4184 }
4185 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4186 guess_suffix = WORD_MNEM_SUFFIX;
4187
4188 for (op = i.operands; --op >= 0;)
40fb9820 4189 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4190 {
4191 switch (i.op[op].imms->X_op)
252b5132 4192 {
29b0f896
AM		 4193 case O_constant:
4194 /* If a suffix is given, this operand may be shortened. */
4195 switch (guess_suffix)
252b5132 4196 {
29b0f896 4197 case LONG_MNEM_SUFFIX:
40fb9820
L		 4198 i.types[op].bitfield.imm32 = 1;
4199 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4200 break;
4201 case WORD_MNEM_SUFFIX:
40fb9820
L		 4202 i.types[op].bitfield.imm16 = 1;
4203 i.types[op].bitfield.imm32 = 1;
4204 i.types[op].bitfield.imm32s = 1;
4205 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4206 break;
4207 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4208 i.types[op].bitfield.imm8 = 1;
4209 i.types[op].bitfield.imm8s = 1;
4210 i.types[op].bitfield.imm16 = 1;
4211 i.types[op].bitfield.imm32 = 1;
4212 i.types[op].bitfield.imm32s = 1;
4213 i.types[op].bitfield.imm64 = 1;
29b0f896 4214 break;
252b5132 4215 }
252b5132 4216
29b0f896
AM		 4217 /* If this operand is at most 16 bits, convert it
4218 to a signed 16 bit number before trying to see
4219 whether it will fit in an even smaller size.
4220 This allows a 16-bit operand such as $0xffe0 to
4221 be recognised as within Imm8S range. */
40fb9820 4222 if ((i.types[op].bitfield.imm16)
29b0f896 4223 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4224 {
29b0f896
AM		 4225 i.op[op].imms->X_add_number =
4226 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4227 }
40fb9820 4228 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4229 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4230 == 0))
4231 {
4232 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4233 ^ ((offsetT) 1 << 31))
4234 - ((offsetT) 1 << 31));
4235 }
40fb9820 4236 i.types[op]
c6fb90c8
L		 4237 = operand_type_or (i.types[op],
4238 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4239
29b0f896
AM		 4240 /* We must avoid matching of Imm32 templates when 64bit
4241 only immediate is available. */
4242 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4243 i.types[op].bitfield.imm32 = 0;
29b0f896 4244 break;
252b5132 4245
29b0f896
AM		 4246 case O_absent:
4247 case O_register:
4248 abort ();
4249
4250 /* Symbols and expressions. */
4251 default:
9cd96992
JB		 4252 /* Convert symbolic operand to proper sizes for matching, but don't
4253 prevent matching a set of insns that only supports sizes other
4254 than those matching the insn suffix. */
4255 {
40fb9820 4256 i386_operand_type mask, allowed;
d3ce72d0 4257 const insn_template *t;
9cd96992 4258
0dfbf9d7
L		 4259 operand_type_set (&mask, 0);
4260 operand_type_set (&allowed, 0);
40fb9820 4261
4eed87de
AM		 4262 for (t = current_templates->start;
4263 t < current_templates->end;
4264 ++t)
c6fb90c8
L		 4265 allowed = operand_type_or (allowed,
4266 t->operand_types[op]);
9cd96992
JB		 4267 switch (guess_suffix)
4268 {
4269 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4270 mask.bitfield.imm64 = 1;
4271 mask.bitfield.imm32s = 1;
9cd96992
JB		 4272 break;
4273 case LONG_MNEM_SUFFIX:
40fb9820 4274 mask.bitfield.imm32 = 1;
9cd96992
JB		 4275 break;
4276 case WORD_MNEM_SUFFIX:
40fb9820 4277 mask.bitfield.imm16 = 1;
9cd96992
JB		 4278 break;
4279 case BYTE_MNEM_SUFFIX:
40fb9820 4280 mask.bitfield.imm8 = 1;
9cd96992
JB		 4281 break;
4282 default:
9cd96992
JB		 4283 break;
4284 }
c6fb90c8 4285 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4286 if (!operand_type_all_zero (&allowed))
c6fb90c8 4287 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4288 }
29b0f896 4289 break;
252b5132 4290 }
29b0f896
AM		 4291 }
4292}
47926f60 4293
29b0f896
AM		 4294/* Try to use the smallest displacement type too. */
4295static void
e3bb37b5 4296optimize_disp (void)
29b0f896
AM		 4297{
4298 int op;
3e73aa7c 4299
29b0f896 4300 for (op = i.operands; --op >= 0;)
40fb9820 4301 if (operand_type_check (i.types[op], disp))
252b5132 4302 {
b300c311 4303 if (i.op[op].disps->X_op == O_constant)
252b5132 4304 {
91d6fa6a 4305 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4306
40fb9820 4307 if (i.types[op].bitfield.disp16
91d6fa6a 4308 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4309 {
4310 /* If this operand is at most 16 bits, convert
4311 to a signed 16 bit number and don't use 64bit
4312 displacement. */
91d6fa6a 4313 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4314 i.types[op].bitfield.disp64 = 0;
b300c311 4315 }
40fb9820 4316 if (i.types[op].bitfield.disp32
91d6fa6a 4317 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4318 {
4319 /* If this operand is at most 32 bits, convert
4320 to a signed 32 bit number and don't use 64bit
4321 displacement. */
91d6fa6a
NC		 4322 op_disp &= (((offsetT) 2 << 31) - 1);
4323 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4324 i.types[op].bitfield.disp64 = 0;
b300c311 4325 }
91d6fa6a 4326 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4327 {
40fb9820
L		 4328 i.types[op].bitfield.disp8 = 0;
4329 i.types[op].bitfield.disp16 = 0;
4330 i.types[op].bitfield.disp32 = 0;
4331 i.types[op].bitfield.disp32s = 0;
4332 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4333 i.op[op].disps = 0;
4334 i.disp_operands--;
4335 }
4336 else if (flag_code == CODE_64BIT)
4337 {
91d6fa6a 4338 if (fits_in_signed_long (op_disp))
28a9d8f5 4339 {
40fb9820
L		 4340 i.types[op].bitfield.disp64 = 0;
4341 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4342 }
0e1147d9 4343 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4344 && fits_in_unsigned_long (op_disp))
40fb9820 4345 i.types[op].bitfield.disp32 = 1;
b300c311 4346 }
40fb9820
L		 4347 if ((i.types[op].bitfield.disp32
4348 || i.types[op].bitfield.disp32s
4349 || i.types[op].bitfield.disp16)
91d6fa6a 4350 && fits_in_signed_byte (op_disp))
40fb9820 4351 i.types[op].bitfield.disp8 = 1;
252b5132 4352 }
67a4f2b7
AO		 4353 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4354 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4355 {
4356 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4357 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4358 i.types[op].bitfield.disp8 = 0;
4359 i.types[op].bitfield.disp16 = 0;
4360 i.types[op].bitfield.disp32 = 0;
4361 i.types[op].bitfield.disp32s = 0;
4362 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4363 }
4364 else
b300c311 4365 /* We only support 64bit displacement on constants. */
40fb9820 4366 i.types[op].bitfield.disp64 = 0;
252b5132 4367 }
29b0f896
AM		 4368}
4369
6c30d220
L		 4370/* Check if operands are valid for the instruction. */
4371
4372static int
4373check_VecOperands (const insn_template *t)
4374{
43234a1e
L		 4375 unsigned int op;
4376
6c30d220
L		 4377 /* Without VSIB byte, we can't have a vector register for index. */
4378 if (!t->opcode_modifier.vecsib
4379 && i.index_reg
4380 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4381 || i.index_reg->reg_type.bitfield.regymm
4382 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4383 {
4384 i.error = unsupported_vector_index_register;
4385 return 1;
4386 }
4387
ad8ecc81
MZ		 4388 /* Check if default mask is allowed. */
4389 if (t->opcode_modifier.nodefmask
4390 && (!i.mask || i.mask->mask->reg_num == 0))
4391 {
4392 i.error = no_default_mask;
4393 return 1;
4394 }
4395
7bab8ab5
JB		 4396 /* For VSIB byte, we need a vector register for index, and all vector
4397 registers must be distinct. */
4398 if (t->opcode_modifier.vecsib)
4399 {
4400 if (!i.index_reg
6c30d220
L		 4401 || !((t->opcode_modifier.vecsib == VecSIB128
4402 && i.index_reg->reg_type.bitfield.regxmm)
4403 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4404 && i.index_reg->reg_type.bitfield.regymm)
4405 || (t->opcode_modifier.vecsib == VecSIB512
4406 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4407 {
4408 i.error = invalid_vsib_address;
4409 return 1;
4410 }
4411
43234a1e
L		 4412 gas_assert (i.reg_operands == 2 || i.mask);
4413 if (i.reg_operands == 2 && !i.mask)
4414 {
4415 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4416 || i.types[0].bitfield.regymm);
43234a1e 4417 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4418 || i.types[2].bitfield.regymm);
43234a1e
L		 4419 if (operand_check == check_none)
4420 return 0;
4421 if (register_number (i.op[0].regs)
4422 != register_number (i.index_reg)
4423 && register_number (i.op[2].regs)
4424 != register_number (i.index_reg)
4425 && register_number (i.op[0].regs)
4426 != register_number (i.op[2].regs))
4427 return 0;
4428 if (operand_check == check_error)
4429 {
4430 i.error = invalid_vector_register_set;
4431 return 1;
4432 }
4433 as_warn (_("mask, index, and destination registers should be distinct"));
4434 }
8444f82a
MZ		 4435 else if (i.reg_operands == 1 && i.mask)
4436 {
4437 if ((i.types[1].bitfield.regymm
4438 || i.types[1].bitfield.regzmm)
4439 && (register_number (i.op[1].regs)
4440 == register_number (i.index_reg)))
4441 {
4442 if (operand_check == check_error)
4443 {
4444 i.error = invalid_vector_register_set;
4445 return 1;
4446 }
4447 if (operand_check != check_none)
4448 as_warn (_("index and destination registers should be distinct"));
4449 }
4450 }
43234a1e 4451 }
7bab8ab5 4452
43234a1e
L		 4453 /* Check if broadcast is supported by the instruction and is applied
4454 to the memory operand. */
4455 if (i.broadcast)
4456 {
4457 int broadcasted_opnd_size;
4458
4459 /* Check if specified broadcast is supported in this instruction,
4460 and it's applied to memory operand of DWORD or QWORD type,
4461 depending on VecESize. */
4462 if (i.broadcast->type != t->opcode_modifier.broadcast
4463 || !i.types[i.broadcast->operand].bitfield.mem
4464 || (t->opcode_modifier.vecesize == 0
4465 && !i.types[i.broadcast->operand].bitfield.dword
4466 && !i.types[i.broadcast->operand].bitfield.unspecified)
4467 || (t->opcode_modifier.vecesize == 1
4468 && !i.types[i.broadcast->operand].bitfield.qword
4469 && !i.types[i.broadcast->operand].bitfield.unspecified))
4470 goto bad_broadcast;
4471
4472 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4473 if (i.broadcast->type == BROADCAST_1TO16)
4474 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4475 else if (i.broadcast->type == BROADCAST_1TO8)
4476 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4477 else if (i.broadcast->type == BROADCAST_1TO4)
4478 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4479 else if (i.broadcast->type == BROADCAST_1TO2)
4480 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4481 else
4482 goto bad_broadcast;
4483
4484 if ((broadcasted_opnd_size == 256
4485 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4486 || (broadcasted_opnd_size == 512
4487 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4488 {
4489 bad_broadcast:
4490 i.error = unsupported_broadcast;
4491 return 1;
4492 }
4493 }
4494 /* If broadcast is supported in this instruction, we need to check if
4495 operand of one-element size isn't specified without broadcast. */
4496 else if (t->opcode_modifier.broadcast && i.mem_operands)
4497 {
4498 /* Find memory operand. */
4499 for (op = 0; op < i.operands; op++)
4500 if (operand_type_check (i.types[op], anymem))
4501 break;
4502 gas_assert (op < i.operands);
4503 /* Check size of the memory operand. */
4504 if ((t->opcode_modifier.vecesize == 0
4505 && i.types[op].bitfield.dword)
4506 || (t->opcode_modifier.vecesize == 1
4507 && i.types[op].bitfield.qword))
4508 {
4509 i.error = broadcast_needed;
4510 return 1;
4511 }
4512 }
4513
4514 /* Check if requested masking is supported. */
4515 if (i.mask
4516 && (!t->opcode_modifier.masking
4517 || (i.mask->zeroing
4518 && t->opcode_modifier.masking == MERGING_MASKING)))
4519 {
4520 i.error = unsupported_masking;
4521 return 1;
4522 }
4523
4524 /* Check if masking is applied to dest operand. */
4525 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4526 {
4527 i.error = mask_not_on_destination;
4528 return 1;
4529 }
4530
43234a1e
L		 4531 /* Check RC/SAE. */
4532 if (i.rounding)
4533 {
4534 if ((i.rounding->type != saeonly
4535 && !t->opcode_modifier.staticrounding)
4536 || (i.rounding->type == saeonly
4537 && (t->opcode_modifier.staticrounding
4538 || !t->opcode_modifier.sae)))
4539 {
4540 i.error = unsupported_rc_sae;
4541 return 1;
4542 }
4543 /* If the instruction has several immediate operands and one of
4544 them is rounding, the rounding operand should be the last
4545 immediate operand. */
4546 if (i.imm_operands > 1
4547 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4548 {
43234a1e 4549 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4550 return 1;
4551 }
6c30d220
L		 4552 }
4553
43234a1e
L		 4554 /* Check vector Disp8 operand. */
4555 if (t->opcode_modifier.disp8memshift)
4556 {
4557 if (i.broadcast)
4558 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4559 else
4560 i.memshift = t->opcode_modifier.disp8memshift;
4561
4562 for (op = 0; op < i.operands; op++)
4563 if (operand_type_check (i.types[op], disp)
4564 && i.op[op].disps->X_op == O_constant)
4565 {
4566 offsetT value = i.op[op].disps->X_add_number;
4567 int vec_disp8_ok = fits_in_vec_disp8 (value);
4568 if (t->operand_types [op].bitfield.vec_disp8)
4569 {
4570 if (vec_disp8_ok)
4571 i.types[op].bitfield.vec_disp8 = 1;
4572 else
4573 {
4574 /* Vector insn can only have Vec_Disp8/Disp32 in
4575 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4576 mode. */
4577 i.types[op].bitfield.disp8 = 0;
4578 if (flag_code != CODE_16BIT)
4579 i.types[op].bitfield.disp16 = 0;
4580 }
4581 }
4582 else if (flag_code != CODE_16BIT)
4583 {
4584 /* One form of this instruction supports vector Disp8.
4585 Try vector Disp8 if we need to use Disp32. */
4586 if (vec_disp8_ok && !fits_in_signed_byte (value))
4587 {
4588 i.error = try_vector_disp8;
4589 return 1;
4590 }
4591 }
4592 }
4593 }
4594 else
4595 i.memshift = -1;
4596
6c30d220
L		 4597 return 0;
4598}
4599
43f3e2ee 4600/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4601 operand types. */
4602
4603static int
4604VEX_check_operands (const insn_template *t)
4605{
43234a1e
L		 4606 /* VREX is only valid with EVEX prefix. */
4607 if (i.need_vrex && !t->opcode_modifier.evex)
4608 {
4609 i.error = invalid_register_operand;
4610 return 1;
4611 }
4612
a683cc34
SP		 4613 if (!t->opcode_modifier.vex)
4614 return 0;
4615
4616 /* Only check VEX_Imm4, which must be the first operand. */
4617 if (t->operand_types[0].bitfield.vec_imm4)
4618 {
4619 if (i.op[0].imms->X_op != O_constant
4620 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4621 {
a65babc9 4622 i.error = bad_imm4;
891edac4
L		 4623 return 1;
4624 }
a683cc34
SP		 4625
4626 /* Turn off Imm8 so that update_imm won't complain. */
4627 i.types[0] = vec_imm4;
4628 }
4629
4630 return 0;
4631}
4632
d3ce72d0 4633static const insn_template *
e3bb37b5 4634match_template (void)
29b0f896
AM		 4635{
4636 /* Points to template once we've found it. */
d3ce72d0 4637 const insn_template *t;
40fb9820 4638 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4639 i386_operand_type overlap4;
29b0f896 4640 unsigned int found_reverse_match;
40fb9820
L		 4641 i386_opcode_modifier suffix_check;
4642 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4643 int addr_prefix_disp;
a5c311ca 4644 unsigned int j;
3629bb00 4645 unsigned int found_cpu_match;
45664ddb 4646 unsigned int check_register;
5614d22c 4647 enum i386_error specific_error = 0;
29b0f896 4648
c0f3af97
L		 4649#if MAX_OPERANDS != 5
4650# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4651#endif
4652
29b0f896 4653 found_reverse_match = 0;
539e75ad 4654 addr_prefix_disp = -1;
40fb9820
L		 4655
4656 memset (&suffix_check, 0, sizeof (suffix_check));
4657 if (i.suffix == BYTE_MNEM_SUFFIX)
4658 suffix_check.no_bsuf = 1;
4659 else if (i.suffix == WORD_MNEM_SUFFIX)
4660 suffix_check.no_wsuf = 1;
4661 else if (i.suffix == SHORT_MNEM_SUFFIX)
4662 suffix_check.no_ssuf = 1;
4663 else if (i.suffix == LONG_MNEM_SUFFIX)
4664 suffix_check.no_lsuf = 1;
4665 else if (i.suffix == QWORD_MNEM_SUFFIX)
4666 suffix_check.no_qsuf = 1;
4667 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4668 suffix_check.no_ldsuf = 1;
29b0f896 4669
01559ecc
L		 4670 /* Must have right number of operands. */
4671 i.error = number_of_operands_mismatch;
4672
45aa61fe 4673 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4674 {
539e75ad
L		 4675 addr_prefix_disp = -1;
4676
29b0f896
AM		 4677 if (i.operands != t->operands)
4678 continue;
4679
50aecf8c 4680 /* Check processor support. */
a65babc9 4681 i.error = unsupported;
c0f3af97
L		 4682 found_cpu_match = (cpu_flags_match (t)
4683 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4684 if (!found_cpu_match)
4685 continue;
4686
e1d4d893 4687 /* Check old gcc support. */
a65babc9 4688 i.error = old_gcc_only;
e1d4d893
L		 4689 if (!old_gcc && t->opcode_modifier.oldgcc)
4690 continue;
4691
4692 /* Check AT&T mnemonic. */
a65babc9 4693 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4694 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4695 continue;
4696
891edac4 4697 /* Check AT&T/Intel syntax. */
a65babc9 4698 i.error = unsupported_syntax;
5c07affc
L		 4699 if ((intel_syntax && t->opcode_modifier.attsyntax)
4700 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4701 continue;
4702
20592a94 4703 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4704 i.error = invalid_instruction_suffix;
567e4e96
L		 4705 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4706 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4707 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4708 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4709 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4710 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4711 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4712 continue;
4713
5c07affc 4714 if (!operand_size_match (t))
7d5e4556 4715 continue;
539e75ad 4716
5c07affc
L		 4717 for (j = 0; j < MAX_OPERANDS; j++)
4718 operand_types[j] = t->operand_types[j];
4719
45aa61fe
AM		 4720 /* In general, don't allow 64-bit operands in 32-bit mode. */
4721 if (i.suffix == QWORD_MNEM_SUFFIX
4722 && flag_code != CODE_64BIT
4723 && (intel_syntax
40fb9820 4724 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4725 && !intel_float_operand (t->name))
4726 : intel_float_operand (t->name) != 2)
40fb9820 4727 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4728 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4729 && !operand_types[0].bitfield.regymm
4730 && !operand_types[0].bitfield.regzmm)
40fb9820 4731 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4732 && operand_types[t->operands > 1].bitfield.regxmm
4733 && operand_types[t->operands > 1].bitfield.regymm
4734 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4735 && (t->base_opcode != 0x0fc7
4736 || t->extension_opcode != 1 /* cmpxchg8b */))
4737 continue;
4738
192dc9c6
JB		 4739 /* In general, don't allow 32-bit operands on pre-386. */
4740 else if (i.suffix == LONG_MNEM_SUFFIX
4741 && !cpu_arch_flags.bitfield.cpui386
4742 && (intel_syntax
4743 ? (!t->opcode_modifier.ignoresize
4744 && !intel_float_operand (t->name))
4745 : intel_float_operand (t->name) != 2)
4746 && ((!operand_types[0].bitfield.regmmx
4747 && !operand_types[0].bitfield.regxmm)
4748 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4749 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4750 continue;
4751
29b0f896 4752 /* Do not verify operands when there are none. */
50aecf8c 4753 else
29b0f896 4754 {
c6fb90c8 4755 if (!t->operands)
2dbab7d5
L		 4756 /* We've found a match; break out of loop. */
4757 break;
29b0f896 4758 }
252b5132 4759
539e75ad
L		 4760 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4761 into Disp32/Disp16/Disp32 operand. */
4762 if (i.prefix[ADDR_PREFIX] != 0)
4763 {
40fb9820 4764 /* There should be only one Disp operand. */
539e75ad
L		 4765 switch (flag_code)
4766 {
4767 case CODE_16BIT:
40fb9820
L		 4768 for (j = 0; j < MAX_OPERANDS; j++)
4769 {
4770 if (operand_types[j].bitfield.disp16)
4771 {
4772 addr_prefix_disp = j;
4773 operand_types[j].bitfield.disp32 = 1;
4774 operand_types[j].bitfield.disp16 = 0;
4775 break;
4776 }
4777 }
539e75ad
L		 4778 break;
4779 case CODE_32BIT:
40fb9820
L		 4780 for (j = 0; j < MAX_OPERANDS; j++)
4781 {
4782 if (operand_types[j].bitfield.disp32)
4783 {
4784 addr_prefix_disp = j;
4785 operand_types[j].bitfield.disp32 = 0;
4786 operand_types[j].bitfield.disp16 = 1;
4787 break;
4788 }
4789 }
539e75ad
L		 4790 break;
4791 case CODE_64BIT:
40fb9820
L		 4792 for (j = 0; j < MAX_OPERANDS; j++)
4793 {
4794 if (operand_types[j].bitfield.disp64)
4795 {
4796 addr_prefix_disp = j;
4797 operand_types[j].bitfield.disp64 = 0;
4798 operand_types[j].bitfield.disp32 = 1;
4799 break;
4800 }
4801 }
539e75ad
L		 4802 break;
4803 }
539e75ad
L		 4804 }
4805
56ffb741
L		 4806 /* We check register size if needed. */
4807 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4808 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4809 switch (t->operands)
4810 {
4811 case 1:
40fb9820 4812 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4813 continue;
4814 break;
4815 case 2:
8b38ad71
L		 4816 /* xchg %eax, %eax is a special case. It is an aliase for nop
4817 only in 32bit mode and we can use opcode 0x90. In 64bit
4818 mode, we can't use 0x90 for xchg %eax, %eax since it should
4819 zero-extend %eax to %rax. */
4820 if (flag_code == CODE_64BIT
4821 && t->base_opcode == 0x90
0dfbf9d7
L		 4822 && operand_type_equal (&i.types [0], &acc32)
4823 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4824 continue;
b6169b20
L		 4825 if (i.swap_operand)
4826 {
4827 /* If we swap operand in encoding, we either match
4828 the next one or reverse direction of operands. */
4829 if (t->opcode_modifier.s)
4830 continue;
4831 else if (t->opcode_modifier.d)
4832 goto check_reverse;
4833 }
4834
29b0f896 4835 case 3:
fa99fab2
L		 4836 /* If we swap operand in encoding, we match the next one. */
4837 if (i.swap_operand && t->opcode_modifier.s)
4838 continue;
f48ff2ae 4839 case 4:
c0f3af97 4840 case 5:
c6fb90c8 4841 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4842 if (!operand_type_match (overlap0, i.types[0])
4843 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4844 || (check_register
4845 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4846 operand_types[0],
4847 overlap1, i.types[1],
4848 operand_types[1])))
29b0f896
AM		 4849 {
4850 /* Check if other direction is valid ... */
40fb9820 4851 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4852 continue;
4853
b6169b20 4854check_reverse:
29b0f896 4855 /* Try reversing direction of operands. */
c6fb90c8
L		 4856 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4857 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4858 if (!operand_type_match (overlap0, i.types[0])
4859 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4860 || (check_register
4861 && !operand_type_register_match (overlap0,
4862 i.types[0],
4863 operand_types[1],
4864 overlap1,
4865 i.types[1],
4866 operand_types[0])))
29b0f896
AM		 4867 {
4868 /* Does not match either direction. */
4869 continue;
4870 }
4871 /* found_reverse_match holds which of D or FloatDR
4872 we've found. */
40fb9820 4873 if (t->opcode_modifier.d)
8a2ed489 4874 found_reverse_match = Opcode_D;
40fb9820 4875 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4876 found_reverse_match = Opcode_FloatD;
4877 else
4878 found_reverse_match = 0;
40fb9820 4879 if (t->opcode_modifier.floatr)
8a2ed489 4880 found_reverse_match |= Opcode_FloatR;
29b0f896 4881 }
f48ff2ae 4882 else
29b0f896 4883 {
f48ff2ae 4884 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4885 switch (t->operands)
4886 {
c0f3af97
L		 4887 case 5:
4888 overlap4 = operand_type_and (i.types[4],
4889 operand_types[4]);
d1cbb4db 4890 case 4:
c6fb90c8
L		 4891 overlap3 = operand_type_and (i.types[3],
4892 operand_types[3]);
d1cbb4db 4893 case 3:
c6fb90c8
L		 4894 overlap2 = operand_type_and (i.types[2],
4895 operand_types[2]);
d1cbb4db
L		 4896 break;
4897 }
29b0f896 4898
f48ff2ae
L		 4899 switch (t->operands)
4900 {
c0f3af97
L		 4901 case 5:
4902 if (!operand_type_match (overlap4, i.types[4])
4903 || !operand_type_register_match (overlap3,
4904 i.types[3],
4905 operand_types[3],
4906 overlap4,
4907 i.types[4],
4908 operand_types[4]))
4909 continue;
f48ff2ae 4910 case 4:
40fb9820 4911 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4912 || (check_register
4913 && !operand_type_register_match (overlap2,
4914 i.types[2],
4915 operand_types[2],
4916 overlap3,
4917 i.types[3],
4918 operand_types[3])))
f48ff2ae
L		 4919 continue;
4920 case 3:
4921 /* Here we make use of the fact that there are no
4922 reverse match 3 operand instructions, and all 3
4923 operand instructions only need to be checked for
4924 register consistency between operands 2 and 3. */
40fb9820 4925 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4926 || (check_register
4927 && !operand_type_register_match (overlap1,
4928 i.types[1],
4929 operand_types[1],
4930 overlap2,
4931 i.types[2],
4932 operand_types[2])))
f48ff2ae
L		 4933 continue;
4934 break;
4935 }
29b0f896 4936 }
f48ff2ae 4937 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4938 slip through to break. */
4939 }
3629bb00 4940 if (!found_cpu_match)
29b0f896
AM		 4941 {
4942 found_reverse_match = 0;
4943 continue;
4944 }
c0f3af97 4945
5614d22c
JB		 4946 /* Check if vector and VEX operands are valid. */
4947 if (check_VecOperands (t) || VEX_check_operands (t))
4948 {
4949 specific_error = i.error;
4950 continue;
4951 }
a683cc34 4952
29b0f896
AM		 4953 /* We've found a match; break out of loop. */
4954 break;
4955 }
4956
4957 if (t == current_templates->end)
4958 {
4959 /* We found no match. */
a65babc9 4960 const char *err_msg;
5614d22c 4961 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4962 {
4963 default:
4964 abort ();
86e026a4 4965 case operand_size_mismatch:
a65babc9
L		 4966 err_msg = _("operand size mismatch");
4967 break;
4968 case operand_type_mismatch:
4969 err_msg = _("operand type mismatch");
4970 break;
4971 case register_type_mismatch:
4972 err_msg = _("register type mismatch");
4973 break;
4974 case number_of_operands_mismatch:
4975 err_msg = _("number of operands mismatch");
4976 break;
4977 case invalid_instruction_suffix:
4978 err_msg = _("invalid instruction suffix");
4979 break;
4980 case bad_imm4:
4a2608e3 4981 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4982 break;
4983 case old_gcc_only:
4984 err_msg = _("only supported with old gcc");
4985 break;
4986 case unsupported_with_intel_mnemonic:
4987 err_msg = _("unsupported with Intel mnemonic");
4988 break;
4989 case unsupported_syntax:
4990 err_msg = _("unsupported syntax");
4991 break;
4992 case unsupported:
35262a23 4993 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4994 current_templates->start->name);
4995 return NULL;
6c30d220
L		 4996 case invalid_vsib_address:
4997 err_msg = _("invalid VSIB address");
4998 break;
7bab8ab5
JB		 4999 case invalid_vector_register_set:
5000 err_msg = _("mask, index, and destination registers must be distinct");
5001 break;
6c30d220
L		 5002 case unsupported_vector_index_register:
5003 err_msg = _("unsupported vector index register");
5004 break;
43234a1e
L		 5005 case unsupported_broadcast:
5006 err_msg = _("unsupported broadcast");
5007 break;
5008 case broadcast_not_on_src_operand:
5009 err_msg = _("broadcast not on source memory operand");
5010 break;
5011 case broadcast_needed:
5012 err_msg = _("broadcast is needed for operand of such type");
5013 break;
5014 case unsupported_masking:
5015 err_msg = _("unsupported masking");
5016 break;
5017 case mask_not_on_destination:
5018 err_msg = _("mask not on destination operand");
5019 break;
5020 case no_default_mask:
5021 err_msg = _("default mask isn't allowed");
5022 break;
5023 case unsupported_rc_sae:
5024 err_msg = _("unsupported static rounding/sae");
5025 break;
5026 case rc_sae_operand_not_last_imm:
5027 if (intel_syntax)
5028 err_msg = _("RC/SAE operand must precede immediate operands");
5029 else
5030 err_msg = _("RC/SAE operand must follow immediate operands");
5031 break;
5032 case invalid_register_operand:
5033 err_msg = _("invalid register operand");
5034 break;
a65babc9
L		 5035 }
5036 as_bad (_("%s for `%s'"), err_msg,
891edac4 5037 current_templates->start->name);
fa99fab2 5038 return NULL;
29b0f896 5039 }
252b5132 5040
29b0f896
AM		 5041 if (!quiet_warnings)
5042 {
5043 if (!intel_syntax
40fb9820
L		 5044 && (i.types[0].bitfield.jumpabsolute
5045 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5046 {
5047 as_warn (_("indirect %s without `*'"), t->name);
5048 }
5049
40fb9820
L		 5050 if (t->opcode_modifier.isprefix
5051 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5052 {
5053 /* Warn them that a data or address size prefix doesn't
5054 affect assembly of the next line of code. */
5055 as_warn (_("stand-alone `%s' prefix"), t->name);
5056 }
5057 }
5058
5059 /* Copy the template we found. */
5060 i.tm = *t;
539e75ad
L		 5061
5062 if (addr_prefix_disp != -1)
5063 i.tm.operand_types[addr_prefix_disp]
5064 = operand_types[addr_prefix_disp];
5065
29b0f896
AM		 5066 if (found_reverse_match)
5067 {
5068 /* If we found a reverse match we must alter the opcode
5069 direction bit. found_reverse_match holds bits to change
5070 (different for int & float insns). */
5071
5072 i.tm.base_opcode ^= found_reverse_match;
5073
539e75ad
L		 5074 i.tm.operand_types[0] = operand_types[1];
5075 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5076 }
5077
fa99fab2 5078 return t;
29b0f896
AM		 5079}
5080
5081static int
e3bb37b5 5082check_string (void)
29b0f896 5083{
40fb9820
L		 5084 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5085 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5086 {
5087 if (i.seg[0] != NULL && i.seg[0] != &es)
5088 {
a87af027 5089 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5090 i.tm.name,
a87af027
JB		 5091 mem_op + 1,
5092 register_prefix);
29b0f896
AM		 5093 return 0;
5094 }
5095 /* There's only ever one segment override allowed per instruction.
5096 This instruction possibly has a legal segment override on the
5097 second operand, so copy the segment to where non-string
5098 instructions store it, allowing common code. */
5099 i.seg[0] = i.seg[1];
5100 }
40fb9820 5101 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5102 {
5103 if (i.seg[1] != NULL && i.seg[1] != &es)
5104 {
a87af027 5105 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5106 i.tm.name,
a87af027
JB		 5107 mem_op + 2,
5108 register_prefix);
29b0f896
AM		 5109 return 0;
5110 }
5111 }
5112 return 1;
5113}
5114
5115static int
543613e9 5116process_suffix (void)
29b0f896
AM		 5117{
5118 /* If matched instruction specifies an explicit instruction mnemonic
5119 suffix, use it. */
40fb9820
L		 5120 if (i.tm.opcode_modifier.size16)
5121 i.suffix = WORD_MNEM_SUFFIX;
5122 else if (i.tm.opcode_modifier.size32)
5123 i.suffix = LONG_MNEM_SUFFIX;
5124 else if (i.tm.opcode_modifier.size64)
5125 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5126 else if (i.reg_operands)
5127 {
5128 /* If there's no instruction mnemonic suffix we try to invent one
5129 based on register operands. */
5130 if (!i.suffix)
5131 {
5132 /* We take i.suffix from the last register operand specified,
5133 Destination register type is more significant than source
381d071f
L		 5134 register type. crc32 in SSE4.2 prefers source register
5135 type. */
5136 if (i.tm.base_opcode == 0xf20f38f1)
5137 {
40fb9820
L		 5138 if (i.types[0].bitfield.reg16)
5139 i.suffix = WORD_MNEM_SUFFIX;
5140 else if (i.types[0].bitfield.reg32)
5141 i.suffix = LONG_MNEM_SUFFIX;
5142 else if (i.types[0].bitfield.reg64)
5143 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5144 }
9344ff29 5145 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5146 {
40fb9820 5147 if (i.types[0].bitfield.reg8)
20592a94
L		 5148 i.suffix = BYTE_MNEM_SUFFIX;
5149 }
381d071f
L		 5150
5151 if (!i.suffix)
5152 {
5153 int op;
5154
20592a94
L		 5155 if (i.tm.base_opcode == 0xf20f38f1
5156 || i.tm.base_opcode == 0xf20f38f0)
5157 {
5158 /* We have to know the operand size for crc32. */
5159 as_bad (_("ambiguous memory operand size for `%s`"),
5160 i.tm.name);
5161 return 0;
5162 }
5163
381d071f 5164 for (op = i.operands; --op >= 0;)
40fb9820 5165 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5166 {
40fb9820
L		 5167 if (i.types[op].bitfield.reg8)
5168 {
5169 i.suffix = BYTE_MNEM_SUFFIX;
5170 break;
5171 }
5172 else if (i.types[op].bitfield.reg16)
5173 {
5174 i.suffix = WORD_MNEM_SUFFIX;
5175 break;
5176 }
5177 else if (i.types[op].bitfield.reg32)
5178 {
5179 i.suffix = LONG_MNEM_SUFFIX;
5180 break;
5181 }
5182 else if (i.types[op].bitfield.reg64)
5183 {
5184 i.suffix = QWORD_MNEM_SUFFIX;
5185 break;
5186 }
381d071f
L		 5187 }
5188 }
29b0f896
AM		 5189 }
5190 else if (i.suffix == BYTE_MNEM_SUFFIX)
5191 {
2eb952a4
L		 5192 if (intel_syntax
5193 && i.tm.opcode_modifier.ignoresize
5194 && i.tm.opcode_modifier.no_bsuf)
5195 i.suffix = 0;
5196 else if (!check_byte_reg ())
29b0f896
AM		 5197 return 0;
5198 }
5199 else if (i.suffix == LONG_MNEM_SUFFIX)
5200 {
2eb952a4
L		 5201 if (intel_syntax
5202 && i.tm.opcode_modifier.ignoresize
5203 && i.tm.opcode_modifier.no_lsuf)
5204 i.suffix = 0;
5205 else if (!check_long_reg ())
29b0f896
AM		 5206 return 0;
5207 }
5208 else if (i.suffix == QWORD_MNEM_SUFFIX)
5209 {
955e1e6a
L		 5210 if (intel_syntax
5211 && i.tm.opcode_modifier.ignoresize
5212 && i.tm.opcode_modifier.no_qsuf)
5213 i.suffix = 0;
5214 else if (!check_qword_reg ())
29b0f896
AM		 5215 return 0;
5216 }
5217 else if (i.suffix == WORD_MNEM_SUFFIX)
5218 {
2eb952a4
L		 5219 if (intel_syntax
5220 && i.tm.opcode_modifier.ignoresize
5221 && i.tm.opcode_modifier.no_wsuf)
5222 i.suffix = 0;
5223 else if (!check_word_reg ())
29b0f896
AM		 5224 return 0;
5225 }
c0f3af97 5226 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5227 || i.suffix == YMMWORD_MNEM_SUFFIX
5228 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5229 {
43234a1e 5230 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5231 should check if it is a valid suffix. */
5232 }
40fb9820 5233 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5234 /* Do nothing if the instruction is going to ignore the prefix. */
5235 ;
5236 else
5237 abort ();
5238 }
40fb9820 5239 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5240 && !i.suffix
5241 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5242 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5243 {
5244 i.suffix = stackop_size;
5245 }
9306ca4a
JB		 5246 else if (intel_syntax
5247 && !i.suffix
40fb9820
L		 5248 && (i.tm.operand_types[0].bitfield.jumpabsolute
5249 || i.tm.opcode_modifier.jumpbyte
5250 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5251 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5252 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5253 {
5254 switch (flag_code)
5255 {
5256 case CODE_64BIT:
40fb9820 5257 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5258 {
5259 i.suffix = QWORD_MNEM_SUFFIX;
5260 break;
5261 }
5262 case CODE_32BIT:
40fb9820 5263 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5264 i.suffix = LONG_MNEM_SUFFIX;
5265 break;
5266 case CODE_16BIT:
40fb9820 5267 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5268 i.suffix = WORD_MNEM_SUFFIX;
5269 break;
5270 }
5271 }
252b5132 5272
9306ca4a 5273 if (!i.suffix)
29b0f896 5274 {
9306ca4a
JB		 5275 if (!intel_syntax)
5276 {
40fb9820 5277 if (i.tm.opcode_modifier.w)
9306ca4a 5278 {
4eed87de
AM		 5279 as_bad (_("no instruction mnemonic suffix given and "
5280 "no register operands; can't size instruction"));
9306ca4a
JB		 5281 return 0;
5282 }
5283 }
5284 else
5285 {
40fb9820 5286 unsigned int suffixes;
7ab9ffdd 5287
40fb9820
L		 5288 suffixes = !i.tm.opcode_modifier.no_bsuf;
5289 if (!i.tm.opcode_modifier.no_wsuf)
5290 suffixes |= 1 << 1;
5291 if (!i.tm.opcode_modifier.no_lsuf)
5292 suffixes |= 1 << 2;
fc4adea1 5293 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5294 suffixes |= 1 << 3;
5295 if (!i.tm.opcode_modifier.no_ssuf)
5296 suffixes |= 1 << 4;
5297 if (!i.tm.opcode_modifier.no_qsuf)
5298 suffixes |= 1 << 5;
5299
5300 /* There are more than suffix matches. */
5301 if (i.tm.opcode_modifier.w
9306ca4a 5302 || ((suffixes & (suffixes - 1))
40fb9820
L		 5303 && !i.tm.opcode_modifier.defaultsize
5304 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5305 {
5306 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5307 return 0;
5308 }
5309 }
29b0f896 5310 }
252b5132 5311
9306ca4a
JB		 5312 /* Change the opcode based on the operand size given by i.suffix;
5313 We don't need to change things for byte insns. */
5314
582d5edd
L		 5315 if (i.suffix
5316 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5317 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5318 && i.suffix != YMMWORD_MNEM_SUFFIX
5319 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5320 {
5321 /* It's not a byte, select word/dword operation. */
40fb9820 5322 if (i.tm.opcode_modifier.w)
29b0f896 5323 {
40fb9820 5324 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5325 i.tm.base_opcode |= 8;
5326 else
5327 i.tm.base_opcode |= 1;
5328 }
0f3f3d8b 5329
29b0f896
AM		 5330 /* Now select between word & dword operations via the operand
5331 size prefix, except for instructions that will ignore this
5332 prefix anyway. */
ca61edf2 5333 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5334 {
ca61edf2
L		 5335 /* The address size override prefix changes the size of the
5336 first operand. */
40fb9820
L		 5337 if ((flag_code == CODE_32BIT
5338 && i.op->regs[0].reg_type.bitfield.reg16)
5339 || (flag_code != CODE_32BIT
5340 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5341 if (!add_prefix (ADDR_PREFIX_OPCODE))
5342 return 0;
5343 }
5344 else if (i.suffix != QWORD_MNEM_SUFFIX
5345 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5346 && !i.tm.opcode_modifier.ignoresize
5347 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5348 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5349 || (flag_code == CODE_64BIT
40fb9820 5350 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5351 {
5352 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5353
40fb9820 5354 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5355 prefix = ADDR_PREFIX_OPCODE;
252b5132 5356
29b0f896
AM		 5357 if (!add_prefix (prefix))
5358 return 0;
24eab124 5359 }
252b5132 5360
29b0f896
AM		 5361 /* Set mode64 for an operand. */
5362 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5363 && flag_code == CODE_64BIT
40fb9820 5364 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5365 {
5366 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5367 need rex64. cmpxchg8b is also a special case. */
5368 if (! (i.operands == 2
5369 && i.tm.base_opcode == 0x90
5370 && i.tm.extension_opcode == None
0dfbf9d7
L		 5371 && operand_type_equal (&i.types [0], &acc64)
5372 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5373 && ! (i.operands == 1
5374 && i.tm.base_opcode == 0xfc7
5375 && i.tm.extension_opcode == 1
40fb9820
L		 5376 && !operand_type_check (i.types [0], reg)
5377 && operand_type_check (i.types [0], anymem)))
f6bee062 5378 i.rex |= REX_W;
46e883c5 5379 }
3e73aa7c 5380
29b0f896
AM		 5381 /* Size floating point instruction. */
5382 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5383 if (i.tm.opcode_modifier.floatmf)
543613e9 5384 i.tm.base_opcode ^= 4;
29b0f896 5385 }
7ecd2f8b 5386
29b0f896
AM		 5387 return 1;
5388}
3e73aa7c 5389
29b0f896 5390static int
543613e9 5391check_byte_reg (void)
29b0f896
AM		 5392{
5393 int op;
543613e9 5394
29b0f896
AM		 5395 for (op = i.operands; --op >= 0;)
5396 {
5397 /* If this is an eight bit register, it's OK. If it's the 16 or
5398 32 bit version of an eight bit register, we will just use the
5399 low portion, and that's OK too. */
40fb9820 5400 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5401 continue;
5402
5a819eb9
JB		 5403 /* I/O port address operands are OK too. */
5404 if (i.tm.operand_types[op].bitfield.inoutportreg)
5405 continue;
5406
9344ff29
L		 5407 /* crc32 doesn't generate this warning. */
5408 if (i.tm.base_opcode == 0xf20f38f0)
5409 continue;
5410
40fb9820
L		 5411 if ((i.types[op].bitfield.reg16
5412 || i.types[op].bitfield.reg32
5413 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5414 && i.op[op].regs->reg_num < 4
5415 /* Prohibit these changes in 64bit mode, since the lowering
5416 would be more complicated. */
5417 && flag_code != CODE_64BIT)
29b0f896 5418 {
29b0f896 5419#if REGISTER_WARNINGS
5a819eb9 5420 if (!quiet_warnings)
a540244d
L		 5421 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5422 register_prefix,
40fb9820 5423 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5424 ? REGNAM_AL - REGNAM_AX
5425 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5426 register_prefix,
29b0f896
AM		 5427 i.op[op].regs->reg_name,
5428 i.suffix);
5429#endif
5430 continue;
5431 }
5432 /* Any other register is bad. */
40fb9820
L		 5433 if (i.types[op].bitfield.reg16
5434 || i.types[op].bitfield.reg32
5435 || i.types[op].bitfield.reg64
5436 || i.types[op].bitfield.regmmx
5437 || i.types[op].bitfield.regxmm
c0f3af97 5438 || i.types[op].bitfield.regymm
43234a1e 5439 || i.types[op].bitfield.regzmm
40fb9820
L		 5440 || i.types[op].bitfield.sreg2
5441 || i.types[op].bitfield.sreg3
5442 || i.types[op].bitfield.control
5443 || i.types[op].bitfield.debug
5444 || i.types[op].bitfield.test
5445 || i.types[op].bitfield.floatreg
5446 || i.types[op].bitfield.floatacc)
29b0f896 5447 {
a540244d
L		 5448 as_bad (_("`%s%s' not allowed with `%s%c'"),
5449 register_prefix,
29b0f896
AM		 5450 i.op[op].regs->reg_name,
5451 i.tm.name,
5452 i.suffix);
5453 return 0;
5454 }
5455 }
5456 return 1;
5457}
5458
5459static int
e3bb37b5 5460check_long_reg (void)
29b0f896
AM		 5461{
5462 int op;
5463
5464 for (op = i.operands; --op >= 0;)
5465 /* Reject eight bit registers, except where the template requires
5466 them. (eg. movzb) */
40fb9820
L		 5467 if (i.types[op].bitfield.reg8
5468 && (i.tm.operand_types[op].bitfield.reg16
5469 || i.tm.operand_types[op].bitfield.reg32
5470 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5471 {
a540244d
L		 5472 as_bad (_("`%s%s' not allowed with `%s%c'"),
5473 register_prefix,
29b0f896
AM		 5474 i.op[op].regs->reg_name,
5475 i.tm.name,
5476 i.suffix);
5477 return 0;
5478 }
e4630f71 5479 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5480 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5481 && i.types[op].bitfield.reg16
5482 && (i.tm.operand_types[op].bitfield.reg32
5483 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5484 {
5485 /* Prohibit these changes in the 64bit mode, since the
5486 lowering is more complicated. */
5487 if (flag_code == CODE_64BIT)
252b5132 5488 {
2b5d6a91 5489 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5490 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5491 i.suffix);
5492 return 0;
252b5132 5493 }
29b0f896 5494#if REGISTER_WARNINGS
cecf1424
JB		 5495 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5496 register_prefix,
5497 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5498 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5499#endif
252b5132 5500 }
e4630f71 5501 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5502 else if (i.types[op].bitfield.reg64
5503 && (i.tm.operand_types[op].bitfield.reg32
5504 || i.tm.operand_types[op].bitfield.acc))
252b5132 5505 {
34828aad 5506 if (intel_syntax
ca61edf2 5507 && i.tm.opcode_modifier.toqword
40fb9820 5508 && !i.types[0].bitfield.regxmm)
34828aad 5509 {
ca61edf2 5510 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5511 i.suffix = QWORD_MNEM_SUFFIX;
5512 }
5513 else
5514 {
2b5d6a91 5515 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5516 register_prefix, i.op[op].regs->reg_name,
5517 i.suffix);
5518 return 0;
5519 }
29b0f896
AM		 5520 }
5521 return 1;
5522}
252b5132 5523
29b0f896 5524static int
e3bb37b5 5525check_qword_reg (void)
29b0f896
AM		 5526{
5527 int op;
252b5132 5528
29b0f896
AM		 5529 for (op = i.operands; --op >= 0; )
5530 /* Reject eight bit registers, except where the template requires
5531 them. (eg. movzb) */
40fb9820
L		 5532 if (i.types[op].bitfield.reg8
5533 && (i.tm.operand_types[op].bitfield.reg16
5534 || i.tm.operand_types[op].bitfield.reg32
5535 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5536 {
a540244d
L		 5537 as_bad (_("`%s%s' not allowed with `%s%c'"),
5538 register_prefix,
29b0f896
AM		 5539 i.op[op].regs->reg_name,
5540 i.tm.name,
5541 i.suffix);
5542 return 0;
5543 }
e4630f71 5544 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5545 else if ((i.types[op].bitfield.reg16
5546 || i.types[op].bitfield.reg32)
5547 && (i.tm.operand_types[op].bitfield.reg32
5548 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5549 {
5550 /* Prohibit these changes in the 64bit mode, since the
5551 lowering is more complicated. */
34828aad 5552 if (intel_syntax
ca61edf2 5553 && i.tm.opcode_modifier.todword
40fb9820 5554 && !i.types[0].bitfield.regxmm)
34828aad 5555 {
ca61edf2 5556 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5557 i.suffix = LONG_MNEM_SUFFIX;
5558 }
5559 else
5560 {
2b5d6a91 5561 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5562 register_prefix, i.op[op].regs->reg_name,
5563 i.suffix);
5564 return 0;
5565 }
252b5132 5566 }
29b0f896
AM		 5567 return 1;
5568}
252b5132 5569
29b0f896 5570static int
e3bb37b5 5571check_word_reg (void)
29b0f896
AM		 5572{
5573 int op;
5574 for (op = i.operands; --op >= 0;)
5575 /* Reject eight bit registers, except where the template requires
5576 them. (eg. movzb) */
40fb9820
L		 5577 if (i.types[op].bitfield.reg8
5578 && (i.tm.operand_types[op].bitfield.reg16
5579 || i.tm.operand_types[op].bitfield.reg32
5580 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5581 {
a540244d
L		 5582 as_bad (_("`%s%s' not allowed with `%s%c'"),
5583 register_prefix,
29b0f896
AM		 5584 i.op[op].regs->reg_name,
5585 i.tm.name,
5586 i.suffix);
5587 return 0;
5588 }
e4630f71 5589 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5590 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5591 && (i.types[op].bitfield.reg32
5592 || i.types[op].bitfield.reg64)
40fb9820
L		 5593 && (i.tm.operand_types[op].bitfield.reg16
5594 || i.tm.operand_types[op].bitfield.acc))
252b5132 5595 {
29b0f896
AM		 5596 /* Prohibit these changes in the 64bit mode, since the
5597 lowering is more complicated. */
5598 if (flag_code == CODE_64BIT)
252b5132 5599 {
2b5d6a91 5600 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5601 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5602 i.suffix);
5603 return 0;
252b5132 5604 }
29b0f896 5605#if REGISTER_WARNINGS
cecf1424
JB		 5606 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5607 register_prefix,
5608 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5609 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5610#endif
5611 }
5612 return 1;
5613}
252b5132 5614
29b0f896 5615static int
40fb9820 5616update_imm (unsigned int j)
29b0f896 5617{
bc0844ae 5618 i386_operand_type overlap = i.types[j];
40fb9820
L		 5619 if ((overlap.bitfield.imm8
5620 || overlap.bitfield.imm8s
5621 || overlap.bitfield.imm16
5622 || overlap.bitfield.imm32
5623 || overlap.bitfield.imm32s
5624 || overlap.bitfield.imm64)
0dfbf9d7
L		 5625 && !operand_type_equal (&overlap, &imm8)
5626 && !operand_type_equal (&overlap, &imm8s)
5627 && !operand_type_equal (&overlap, &imm16)
5628 && !operand_type_equal (&overlap, &imm32)
5629 && !operand_type_equal (&overlap, &imm32s)
5630 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5631 {
5632 if (i.suffix)
5633 {
40fb9820
L		 5634 i386_operand_type temp;
5635
0dfbf9d7 5636 operand_type_set (&temp, 0);
7ab9ffdd 5637 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5638 {
5639 temp.bitfield.imm8 = overlap.bitfield.imm8;
5640 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5641 }
5642 else if (i.suffix == WORD_MNEM_SUFFIX)
5643 temp.bitfield.imm16 = overlap.bitfield.imm16;
5644 else if (i.suffix == QWORD_MNEM_SUFFIX)
5645 {
5646 temp.bitfield.imm64 = overlap.bitfield.imm64;
5647 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5648 }
5649 else
5650 temp.bitfield.imm32 = overlap.bitfield.imm32;
5651 overlap = temp;
29b0f896 5652 }
0dfbf9d7
L		 5653 else if (operand_type_equal (&overlap, &imm16_32_32s)
5654 || operand_type_equal (&overlap, &imm16_32)
5655 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5656 {
40fb9820 5657 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5658 overlap = imm16;
40fb9820 5659 else
65da13b5 5660 overlap = imm32s;
29b0f896 5661 }
0dfbf9d7
L		 5662 if (!operand_type_equal (&overlap, &imm8)
5663 && !operand_type_equal (&overlap, &imm8s)
5664 && !operand_type_equal (&overlap, &imm16)
5665 && !operand_type_equal (&overlap, &imm32)
5666 && !operand_type_equal (&overlap, &imm32s)
5667 && !operand_type_equal (&overlap, &imm64))
29b0f896 5668 {
4eed87de
AM		 5669 as_bad (_("no instruction mnemonic suffix given; "
5670 "can't determine immediate size"));
29b0f896
AM		 5671 return 0;
5672 }
5673 }
40fb9820 5674 i.types[j] = overlap;
29b0f896 5675
40fb9820
L		 5676 return 1;
5677}
5678
5679static int
5680finalize_imm (void)
5681{
bc0844ae 5682 unsigned int j, n;
29b0f896 5683
bc0844ae
L		 5684 /* Update the first 2 immediate operands. */
5685 n = i.operands > 2 ? 2 : i.operands;
5686 if (n)
5687 {
5688 for (j = 0; j < n; j++)
5689 if (update_imm (j) == 0)
5690 return 0;
40fb9820 5691
bc0844ae
L		 5692 /* The 3rd operand can't be immediate operand. */
5693 gas_assert (operand_type_check (i.types[2], imm) == 0);
5694 }
29b0f896
AM		 5695
5696 return 1;
5697}
5698
c0f3af97
L		 5699static int
5700bad_implicit_operand (int xmm)
5701{
91d6fa6a
NC		 5702 const char *ireg = xmm ? "xmm0" : "ymm0";
5703
c0f3af97
L		 5704 if (intel_syntax)
5705 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5706 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5707 else
5708 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5709 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5710 return 0;
5711}
5712
29b0f896 5713static int
e3bb37b5 5714process_operands (void)
29b0f896
AM		 5715{
5716 /* Default segment register this instruction will use for memory
5717 accesses. 0 means unknown. This is only for optimizing out
5718 unnecessary segment overrides. */
5719 const seg_entry *default_seg = 0;
5720
2426c15f 5721 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5722 {
91d6fa6a
NC		 5723 unsigned int dupl = i.operands;
5724 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5725 unsigned int j;
5726
c0f3af97 5727 /* The destination must be an xmm register. */
9c2799c2 5728 gas_assert (i.reg_operands
91d6fa6a 5729 && MAX_OPERANDS > dupl
7ab9ffdd 5730 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5731
5732 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5733 {
c0f3af97 5734 /* The first operand is implicit and must be xmm0. */
9c2799c2 5735 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5736 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5737 return bad_implicit_operand (1);
5738
8cd7925b 5739 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5740 {
5741 /* Keep xmm0 for instructions with VEX prefix and 3
5742 sources. */
5743 goto duplicate;
5744 }
e2ec9d29 5745 else
c0f3af97
L		 5746 {
5747 /* We remove the first xmm0 and keep the number of
5748 operands unchanged, which in fact duplicates the
5749 destination. */
5750 for (j = 1; j < i.operands; j++)
5751 {
5752 i.op[j - 1] = i.op[j];
5753 i.types[j - 1] = i.types[j];
5754 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5755 }
5756 }
5757 }
5758 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5759 {
91d6fa6a 5760 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5761 && (i.tm.opcode_modifier.vexsources
5762 == VEX3SOURCES));
c0f3af97
L		 5763
5764 /* Add the implicit xmm0 for instructions with VEX prefix
5765 and 3 sources. */
5766 for (j = i.operands; j > 0; j--)
5767 {
5768 i.op[j] = i.op[j - 1];
5769 i.types[j] = i.types[j - 1];
5770 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5771 }
5772 i.op[0].regs
5773 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5774 i.types[0] = regxmm;
c0f3af97
L		 5775 i.tm.operand_types[0] = regxmm;
5776
5777 i.operands += 2;
5778 i.reg_operands += 2;
5779 i.tm.operands += 2;
5780
91d6fa6a 5781 dupl++;
c0f3af97 5782 dest++;
91d6fa6a
NC		 5783 i.op[dupl] = i.op[dest];
5784 i.types[dupl] = i.types[dest];
5785 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5786 }
c0f3af97
L		 5787 else
5788 {
5789duplicate:
5790 i.operands++;
5791 i.reg_operands++;
5792 i.tm.operands++;
5793
91d6fa6a
NC		 5794 i.op[dupl] = i.op[dest];
5795 i.types[dupl] = i.types[dest];
5796 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5797 }
5798
5799 if (i.tm.opcode_modifier.immext)
5800 process_immext ();
5801 }
5802 else if (i.tm.opcode_modifier.firstxmm0)
5803 {
5804 unsigned int j;
5805
43234a1e 5806 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5807 gas_assert (i.reg_operands
7ab9ffdd 5808 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5809 || operand_type_equal (&i.types[0], &regymm)
5810 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5811 if (register_number (i.op[0].regs) != 0)
c0f3af97 5812 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5813
5814 for (j = 1; j < i.operands; j++)
5815 {
5816 i.op[j - 1] = i.op[j];
5817 i.types[j - 1] = i.types[j];
5818
5819 /* We need to adjust fields in i.tm since they are used by
5820 build_modrm_byte. */
5821 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5822 }
5823
e2ec9d29
L		 5824 i.operands--;
5825 i.reg_operands--;
e2ec9d29
L		 5826 i.tm.operands--;
5827 }
5828 else if (i.tm.opcode_modifier.regkludge)
5829 {
5830 /* The imul $imm, %reg instruction is converted into
5831 imul $imm, %reg, %reg, and the clr %reg instruction
5832 is converted into xor %reg, %reg. */
5833
5834 unsigned int first_reg_op;
5835
5836 if (operand_type_check (i.types[0], reg))
5837 first_reg_op = 0;
5838 else
5839 first_reg_op = 1;
5840 /* Pretend we saw the extra register operand. */
9c2799c2 5841 gas_assert (i.reg_operands == 1
7ab9ffdd 5842 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5843 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5844 i.types[first_reg_op + 1] = i.types[first_reg_op];
5845 i.operands++;
5846 i.reg_operands++;
29b0f896
AM		 5847 }
5848
40fb9820 5849 if (i.tm.opcode_modifier.shortform)
29b0f896 5850 {
40fb9820
L		 5851 if (i.types[0].bitfield.sreg2
5852 || i.types[0].bitfield.sreg3)
29b0f896 5853 {
4eed87de
AM		 5854 if (i.tm.base_opcode == POP_SEG_SHORT
5855 && i.op[0].regs->reg_num == 1)
29b0f896 5856 {
a87af027 5857 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5858 return 0;
29b0f896 5859 }
4eed87de
AM		 5860 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5861 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5862 i.rex |= REX_B;
4eed87de
AM		 5863 }
5864 else
5865 {
7ab9ffdd 5866 /* The register or float register operand is in operand
85f10a01 5867 0 or 1. */
40fb9820 5868 unsigned int op;
7ab9ffdd
L		 5869
5870 if (i.types[0].bitfield.floatreg
5871 || operand_type_check (i.types[0], reg))
5872 op = 0;
5873 else
5874 op = 1;
4eed87de
AM		 5875 /* Register goes in low 3 bits of opcode. */
5876 i.tm.base_opcode |= i.op[op].regs->reg_num;
5877 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5878 i.rex |= REX_B;
40fb9820 5879 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5880 {
4eed87de
AM		 5881 /* Warn about some common errors, but press on regardless.
5882 The first case can be generated by gcc (<= 2.8.1). */
5883 if (i.operands == 2)
5884 {
5885 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5886 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5887 register_prefix, i.op[!intel_syntax].regs->reg_name,
5888 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5889 }
5890 else
5891 {
5892 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5893 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5894 register_prefix, i.op[0].regs->reg_name);
4eed87de 5895 }
29b0f896
AM		 5896 }
5897 }
5898 }
40fb9820 5899 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5900 {
5901 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5902 must be put into the modrm byte). Now, we make the modrm and
5903 index base bytes based on all the info we've collected. */
29b0f896
AM		 5904
5905 default_seg = build_modrm_byte ();
5906 }
8a2ed489 5907 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5908 {
5909 default_seg = &ds;
5910 }
40fb9820 5911 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5912 {
5913 /* For the string instructions that allow a segment override
5914 on one of their operands, the default segment is ds. */
5915 default_seg = &ds;
5916 }
5917
75178d9d
L		 5918 if (i.tm.base_opcode == 0x8d /* lea */
5919 && i.seg[0]
5920 && !quiet_warnings)
30123838 5921 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5922
5923 /* If a segment was explicitly specified, and the specified segment
5924 is not the default, use an opcode prefix to select it. If we
5925 never figured out what the default segment is, then default_seg
5926 will be zero at this point, and the specified segment prefix will
5927 always be used. */
29b0f896
AM		 5928 if ((i.seg[0]) && (i.seg[0] != default_seg))
5929 {
5930 if (!add_prefix (i.seg[0]->seg_prefix))
5931 return 0;
5932 }
5933 return 1;
5934}
5935
5936static const seg_entry *
e3bb37b5 5937build_modrm_byte (void)
29b0f896
AM		 5938{
5939 const seg_entry *default_seg = 0;
c0f3af97 5940 unsigned int source, dest;
8cd7925b 5941 int vex_3_sources;
c0f3af97
L		 5942
5943 /* The first operand of instructions with VEX prefix and 3 sources
5944 must be VEX_Imm4. */
8cd7925b 5945 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5946 if (vex_3_sources)
5947 {
91d6fa6a 5948 unsigned int nds, reg_slot;
4c2c6516 5949 expressionS *exp;
c0f3af97 5950
922d8de8 5951 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5952 && i.tm.opcode_modifier.immext)
5953 {
5954 dest = i.operands - 2;
5955 gas_assert (dest == 3);
5956 }
922d8de8 5957 else
a683cc34 5958 dest = i.operands - 1;
c0f3af97 5959 nds = dest - 1;
922d8de8 5960
a683cc34
SP		 5961 /* There are 2 kinds of instructions:
5962 1. 5 operands: 4 register operands or 3 register operands
5963 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5964 VexW0 or VexW1. The destination must be either XMM, YMM or
5965 ZMM register.
a683cc34
SP		 5966 2. 4 operands: 4 register operands or 3 register operands
5967 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5968 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5969 || (i.reg_operands == 3 && i.mem_operands == 1))
5970 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5971 && (i.tm.opcode_modifier.veximmext
5972 || (i.imm_operands == 1
5973 && i.types[0].bitfield.vec_imm4
5974 && (i.tm.opcode_modifier.vexw == VEXW0
5975 || i.tm.opcode_modifier.vexw == VEXW1)
5976 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5977 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5978 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5979
5980 if (i.imm_operands == 0)
5981 {
5982 /* When there is no immediate operand, generate an 8bit
5983 immediate operand to encode the first operand. */
5984 exp = &im_expressions[i.imm_operands++];
5985 i.op[i.operands].imms = exp;
5986 i.types[i.operands] = imm8;
5987 i.operands++;
5988 /* If VexW1 is set, the first operand is the source and
5989 the second operand is encoded in the immediate operand. */
5990 if (i.tm.opcode_modifier.vexw == VEXW1)
5991 {
5992 source = 0;
5993 reg_slot = 1;
5994 }
5995 else
5996 {
5997 source = 1;
5998 reg_slot = 0;
5999 }
6000
6001 /* FMA swaps REG and NDS. */
6002 if (i.tm.cpu_flags.bitfield.cpufma)
6003 {
6004 unsigned int tmp;
6005 tmp = reg_slot;
6006 reg_slot = nds;
6007 nds = tmp;
6008 }
6009
24981e7b
L		 6010 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6011 &regxmm)
a683cc34 6012 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6013 &regymm)
6014 || operand_type_equal (&i.tm.operand_types[reg_slot],
6015 &regzmm));
a683cc34 6016 exp->X_op = O_constant;
4c692bc7 6017 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6018 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6019 }
922d8de8 6020 else
a683cc34
SP		 6021 {
6022 unsigned int imm_slot;
6023
6024 if (i.tm.opcode_modifier.vexw == VEXW0)
6025 {
6026 /* If VexW0 is set, the third operand is the source and
6027 the second operand is encoded in the immediate
6028 operand. */
6029 source = 2;
6030 reg_slot = 1;
6031 }
6032 else
6033 {
6034 /* VexW1 is set, the second operand is the source and
6035 the third operand is encoded in the immediate
6036 operand. */
6037 source = 1;
6038 reg_slot = 2;
6039 }
6040
6041 if (i.tm.opcode_modifier.immext)
6042 {
6043 /* When ImmExt is set, the immdiate byte is the last
6044 operand. */
6045 imm_slot = i.operands - 1;
6046 source--;
6047 reg_slot--;
6048 }
6049 else
6050 {
6051 imm_slot = 0;
6052
6053 /* Turn on Imm8 so that output_imm will generate it. */
6054 i.types[imm_slot].bitfield.imm8 = 1;
6055 }
6056
24981e7b
L		 6057 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6058 &regxmm)
6059 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6060 &regymm)
6061 || operand_type_equal (&i.tm.operand_types[reg_slot],
6062 &regzmm));
a683cc34 6063 i.op[imm_slot].imms->X_add_number
4c692bc7 6064 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6065 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6066 }
6067
6068 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6069 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6070 &regymm)
6071 || operand_type_equal (&i.tm.operand_types[nds],
6072 &regzmm));
dae39acc 6073 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6074 }
6075 else
6076 source = dest = 0;
29b0f896
AM		 6077
6078 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6079 implicit registers do not count. If there are 3 register
6080 operands, it must be a instruction with VexNDS. For a
6081 instruction with VexNDD, the destination register is encoded
6082 in VEX prefix. If there are 4 register operands, it must be
6083 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6084 if (i.mem_operands == 0
6085 && ((i.reg_operands == 2
2426c15f 6086 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6087 || (i.reg_operands == 3
2426c15f 6088 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6089 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6090 {
cab737b9
L		 6091 switch (i.operands)
6092 {
6093 case 2:
6094 source = 0;
6095 break;
6096 case 3:
c81128dc
L		 6097 /* When there are 3 operands, one of them may be immediate,
6098 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6099 the first operand must be shift count register (cl) or it
6100 is an instruction with VexNDS. */
9c2799c2 6101 gas_assert (i.imm_operands == 1
7ab9ffdd 6102 || (i.imm_operands == 0
2426c15f 6103 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6104 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6105 if (operand_type_check (i.types[0], imm)
6106 || i.types[0].bitfield.shiftcount)
6107 source = 1;
6108 else
6109 source = 0;
cab737b9
L		 6110 break;
6111 case 4:
368d64cc
L		 6112 /* When there are 4 operands, the first two must be 8bit
6113 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6114 one.
6115
6116 For instructions with VexNDS, if the first operand
6117 an imm8, the source operand is the 2nd one. If the last
6118 operand is imm8, the source operand is the first one. */
9c2799c2 6119 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6120 && i.types[0].bitfield.imm8
6121 && i.types[1].bitfield.imm8)
2426c15f 6122 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6123 && i.imm_operands == 1
6124 && (i.types[0].bitfield.imm8
43234a1e
L		 6125 || i.types[i.operands - 1].bitfield.imm8
6126 || i.rounding)));
9f2670f2
L		 6127 if (i.imm_operands == 2)
6128 source = 2;
6129 else
c0f3af97
L		 6130 {
6131 if (i.types[0].bitfield.imm8)
6132 source = 1;
6133 else
6134 source = 0;
6135 }
c0f3af97
L		 6136 break;
6137 case 5:
43234a1e
L		 6138 if (i.tm.opcode_modifier.evex)
6139 {
6140 /* For EVEX instructions, when there are 5 operands, the
6141 first one must be immediate operand. If the second one
6142 is immediate operand, the source operand is the 3th
6143 one. If the last one is immediate operand, the source
6144 operand is the 2nd one. */
6145 gas_assert (i.imm_operands == 2
6146 && i.tm.opcode_modifier.sae
6147 && operand_type_check (i.types[0], imm));
6148 if (operand_type_check (i.types[1], imm))
6149 source = 2;
6150 else if (operand_type_check (i.types[4], imm))
6151 source = 1;
6152 else
6153 abort ();
6154 }
cab737b9
L		 6155 break;
6156 default:
6157 abort ();
6158 }
6159
c0f3af97
L		 6160 if (!vex_3_sources)
6161 {
6162 dest = source + 1;
6163
43234a1e
L		 6164 /* RC/SAE operand could be between DEST and SRC. That happens
6165 when one operand is GPR and the other one is XMM/YMM/ZMM
6166 register. */
6167 if (i.rounding && i.rounding->operand == (int) dest)
6168 dest++;
6169
2426c15f 6170 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6171 {
43234a1e
L		 6172 /* For instructions with VexNDS, the register-only source
6173 operand must be 32/64bit integer, XMM, YMM or ZMM
6174 register. It is encoded in VEX prefix. We need to
6175 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6176
6177 i386_operand_type op;
6178 unsigned int vvvv;
6179
6180 /* Check register-only source operand when two source
6181 operands are swapped. */
6182 if (!i.tm.operand_types[source].bitfield.baseindex
6183 && i.tm.operand_types[dest].bitfield.baseindex)
6184 {
6185 vvvv = source;
6186 source = dest;
6187 }
6188 else
6189 vvvv = dest;
6190
6191 op = i.tm.operand_types[vvvv];
fa99fab2 6192 op.bitfield.regmem = 0;
c0f3af97 6193 if ((dest + 1) >= i.operands
ac4eb736
AM		 6194 || (!op.bitfield.reg32
6195 && op.bitfield.reg64
f12dc422 6196 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6197 && !operand_type_equal (&op, &regymm)
6198 && !operand_type_equal (&op, &regzmm)
6199 && !operand_type_equal (&op, &regmask)))
c0f3af97 6200 abort ();
f12dc422 6201 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6202 dest++;
6203 }
6204 }
29b0f896
AM		 6205
6206 i.rm.mode = 3;
6207 /* One of the register operands will be encoded in the i.tm.reg
6208 field, the other in the combined i.tm.mode and i.tm.regmem
6209 fields. If no form of this instruction supports a memory
6210 destination operand, then we assume the source operand may
6211 sometimes be a memory operand and so we need to store the
6212 destination in the i.rm.reg field. */
40fb9820
L		 6213 if (!i.tm.operand_types[dest].bitfield.regmem
6214 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6215 {
6216 i.rm.reg = i.op[dest].regs->reg_num;
6217 i.rm.regmem = i.op[source].regs->reg_num;
6218 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6219 i.rex |= REX_R;
43234a1e
L		 6220 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6221 i.vrex |= REX_R;
29b0f896 6222 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6223 i.rex |= REX_B;
43234a1e
L		 6224 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6225 i.vrex |= REX_B;
29b0f896
AM		 6226 }
6227 else
6228 {
6229 i.rm.reg = i.op[source].regs->reg_num;
6230 i.rm.regmem = i.op[dest].regs->reg_num;
6231 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6232 i.rex |= REX_B;
43234a1e
L		 6233 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6234 i.vrex |= REX_B;
29b0f896 6235 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6236 i.rex |= REX_R;
43234a1e
L		 6237 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6238 i.vrex |= REX_R;
29b0f896 6239 }
161a04f6 6240 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6241 {
40fb9820
L		 6242 if (!i.types[0].bitfield.control
6243 && !i.types[1].bitfield.control)
c4a530c5 6244 abort ();
161a04f6 6245 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6246 add_prefix (LOCK_PREFIX_OPCODE);
6247 }
29b0f896
AM		 6248 }
6249 else
6250 { /* If it's not 2 reg operands... */
c0f3af97
L		 6251 unsigned int mem;
6252
29b0f896
AM		 6253 if (i.mem_operands)
6254 {
6255 unsigned int fake_zero_displacement = 0;
99018f42 6256 unsigned int op;
4eed87de 6257
7ab9ffdd
L		 6258 for (op = 0; op < i.operands; op++)
6259 if (operand_type_check (i.types[op], anymem))
6260 break;
7ab9ffdd 6261 gas_assert (op < i.operands);
29b0f896 6262
6c30d220
L		 6263 if (i.tm.opcode_modifier.vecsib)
6264 {
6265 if (i.index_reg->reg_num == RegEiz
6266 || i.index_reg->reg_num == RegRiz)
6267 abort ();
6268
6269 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6270 if (!i.base_reg)
6271 {
6272 i.sib.base = NO_BASE_REGISTER;
6273 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6274 /* No Vec_Disp8 if there is no base. */
6275 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6276 i.types[op].bitfield.disp8 = 0;
6277 i.types[op].bitfield.disp16 = 0;
6278 i.types[op].bitfield.disp64 = 0;
6279 if (flag_code != CODE_64BIT)
6280 {
6281 /* Must be 32 bit */
6282 i.types[op].bitfield.disp32 = 1;
6283 i.types[op].bitfield.disp32s = 0;
6284 }
6285 else
6286 {
6287 i.types[op].bitfield.disp32 = 0;
6288 i.types[op].bitfield.disp32s = 1;
6289 }
6290 }
6291 i.sib.index = i.index_reg->reg_num;
6292 if ((i.index_reg->reg_flags & RegRex) != 0)
6293 i.rex |= REX_X;
43234a1e
L		 6294 if ((i.index_reg->reg_flags & RegVRex) != 0)
6295 i.vrex |= REX_X;
6c30d220
L		 6296 }
6297
29b0f896
AM		 6298 default_seg = &ds;
6299
6300 if (i.base_reg == 0)
6301 {
6302 i.rm.mode = 0;
6303 if (!i.disp_operands)
6c30d220
L		 6304 {
6305 fake_zero_displacement = 1;
6306 /* Instructions with VSIB byte need 32bit displacement
6307 if there is no base register. */
6308 if (i.tm.opcode_modifier.vecsib)
6309 i.types[op].bitfield.disp32 = 1;
6310 }
29b0f896
AM		 6311 if (i.index_reg == 0)
6312 {
6c30d220 6313 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6314 /* Operand is just <disp> */
20f0a1fc 6315 if (flag_code == CODE_64BIT)
29b0f896
AM		 6316 {
6317 /* 64bit mode overwrites the 32bit absolute
6318 addressing by RIP relative addressing and
6319 absolute addressing is encoded by one of the
6320 redundant SIB forms. */
6321 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6322 i.sib.base = NO_BASE_REGISTER;
6323 i.sib.index = NO_INDEX_REGISTER;
fc225355 6324 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6325 ? disp32s : disp32);
20f0a1fc 6326 }
fc225355
L		 6327 else if ((flag_code == CODE_16BIT)
6328 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6329 {
6330 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6331 i.types[op] = disp16;
20f0a1fc
NC		 6332 }
6333 else
6334 {
6335 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6336 i.types[op] = disp32;
29b0f896
AM		 6337 }
6338 }
6c30d220 6339 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6340 {
6c30d220 6341 /* !i.base_reg && i.index_reg */
db51cc60
L		 6342 if (i.index_reg->reg_num == RegEiz
6343 || i.index_reg->reg_num == RegRiz)
6344 i.sib.index = NO_INDEX_REGISTER;
6345 else
6346 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6347 i.sib.base = NO_BASE_REGISTER;
6348 i.sib.scale = i.log2_scale_factor;
6349 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6350 /* No Vec_Disp8 if there is no base. */
6351 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6352 i.types[op].bitfield.disp8 = 0;
6353 i.types[op].bitfield.disp16 = 0;
6354 i.types[op].bitfield.disp64 = 0;
29b0f896 6355 if (flag_code != CODE_64BIT)
40fb9820
L		 6356 {
6357 /* Must be 32 bit */
6358 i.types[op].bitfield.disp32 = 1;
6359 i.types[op].bitfield.disp32s = 0;
6360 }
29b0f896 6361 else
40fb9820
L		 6362 {
6363 i.types[op].bitfield.disp32 = 0;
6364 i.types[op].bitfield.disp32s = 1;
6365 }
29b0f896 6366 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6367 i.rex |= REX_X;
29b0f896
AM		 6368 }
6369 }
6370 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6371 else if (i.base_reg->reg_num == RegRip ||
6372 i.base_reg->reg_num == RegEip)
29b0f896 6373 {
6c30d220 6374 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6375 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6376 i.types[op].bitfield.disp8 = 0;
6377 i.types[op].bitfield.disp16 = 0;
6378 i.types[op].bitfield.disp32 = 0;
6379 i.types[op].bitfield.disp32s = 1;
6380 i.types[op].bitfield.disp64 = 0;
43234a1e 6381 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6382 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6383 if (! i.disp_operands)
6384 fake_zero_displacement = 1;
29b0f896 6385 }
40fb9820 6386 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6387 {
6c30d220 6388 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6389 switch (i.base_reg->reg_num)
6390 {
6391 case 3: /* (%bx) */
6392 if (i.index_reg == 0)
6393 i.rm.regmem = 7;
6394 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6395 i.rm.regmem = i.index_reg->reg_num - 6;
6396 break;
6397 case 5: /* (%bp) */
6398 default_seg = &ss;
6399 if (i.index_reg == 0)
6400 {
6401 i.rm.regmem = 6;
40fb9820 6402 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6403 {
6404 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6405 if (i.tm.operand_types[op].bitfield.vec_disp8)
6406 i.types[op].bitfield.vec_disp8 = 1;
6407 else
6408 i.types[op].bitfield.disp8 = 1;
252b5132 6409 fake_zero_displacement = 1;
29b0f896
AM		 6410 }
6411 }
6412 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6413 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6414 break;
6415 default: /* (%si) -> 4 or (%di) -> 5 */
6416 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6417 }
6418 i.rm.mode = mode_from_disp_size (i.types[op]);
6419 }
6420 else /* i.base_reg and 32/64 bit mode */
6421 {
6422 if (flag_code == CODE_64BIT
40fb9820
L		 6423 && operand_type_check (i.types[op], disp))
6424 {
6425 i386_operand_type temp;
0dfbf9d7 6426 operand_type_set (&temp, 0);
40fb9820 6427 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6428 temp.bitfield.vec_disp8
6429 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6430 i.types[op] = temp;
6431 if (i.prefix[ADDR_PREFIX] == 0)
6432 i.types[op].bitfield.disp32s = 1;
6433 else
6434 i.types[op].bitfield.disp32 = 1;
6435 }
20f0a1fc 6436
6c30d220
L		 6437 if (!i.tm.opcode_modifier.vecsib)
6438 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6439 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6440 i.rex |= REX_B;
29b0f896
AM		 6441 i.sib.base = i.base_reg->reg_num;
6442 /* x86-64 ignores REX prefix bit here to avoid decoder
6443 complications. */
848930b2
JB		 6444 if (!(i.base_reg->reg_flags & RegRex)
6445 && (i.base_reg->reg_num == EBP_REG_NUM
6446 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6447 default_seg = &ss;
848930b2 6448 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6449 {
848930b2 6450 fake_zero_displacement = 1;
43234a1e
L		 6451 if (i.tm.operand_types [op].bitfield.vec_disp8)
6452 i.types[op].bitfield.vec_disp8 = 1;
6453 else
6454 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6455 }
6456 i.sib.scale = i.log2_scale_factor;
6457 if (i.index_reg == 0)
6458 {
6c30d220 6459 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6460 /* <disp>(%esp) becomes two byte modrm with no index
6461 register. We've already stored the code for esp
6462 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6463 Any base register besides %esp will not use the
6464 extra modrm byte. */
6465 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6466 }
6c30d220 6467 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6468 {
db51cc60
L		 6469 if (i.index_reg->reg_num == RegEiz
6470 || i.index_reg->reg_num == RegRiz)
6471 i.sib.index = NO_INDEX_REGISTER;
6472 else
6473 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6474 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6475 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6476 i.rex |= REX_X;
29b0f896 6477 }
67a4f2b7
AO		 6478
6479 if (i.disp_operands
6480 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6481 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6482 i.rm.mode = 0;
6483 else
a501d77e
L		 6484 {
6485 if (!fake_zero_displacement
6486 && !i.disp_operands
6487 && i.disp_encoding)
6488 {
6489 fake_zero_displacement = 1;
6490 if (i.disp_encoding == disp_encoding_8bit)
6491 i.types[op].bitfield.disp8 = 1;
6492 else
6493 i.types[op].bitfield.disp32 = 1;
6494 }
6495 i.rm.mode = mode_from_disp_size (i.types[op]);
6496 }
29b0f896 6497 }
252b5132 6498
29b0f896
AM		 6499 if (fake_zero_displacement)
6500 {
6501 /* Fakes a zero displacement assuming that i.types[op]
6502 holds the correct displacement size. */
6503 expressionS *exp;
6504
9c2799c2 6505 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6506 exp = &disp_expressions[i.disp_operands++];
6507 i.op[op].disps = exp;
6508 exp->X_op = O_constant;
6509 exp->X_add_number = 0;
6510 exp->X_add_symbol = (symbolS *) 0;
6511 exp->X_op_symbol = (symbolS *) 0;
6512 }
c0f3af97
L		 6513
6514 mem = op;
29b0f896 6515 }
c0f3af97
L		 6516 else
6517 mem = ~0;
252b5132 6518
8c43a48b 6519 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6520 {
6521 if (operand_type_check (i.types[0], imm))
6522 i.vex.register_specifier = NULL;
6523 else
6524 {
6525 /* VEX.vvvv encodes one of the sources when the first
6526 operand is not an immediate. */
1ef99a7b 6527 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6528 i.vex.register_specifier = i.op[0].regs;
6529 else
6530 i.vex.register_specifier = i.op[1].regs;
6531 }
6532
6533 /* Destination is a XMM register encoded in the ModRM.reg
6534 and VEX.R bit. */
6535 i.rm.reg = i.op[2].regs->reg_num;
6536 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6537 i.rex |= REX_R;
6538
6539 /* ModRM.rm and VEX.B encodes the other source. */
6540 if (!i.mem_operands)
6541 {
6542 i.rm.mode = 3;
6543
1ef99a7b 6544 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6545 i.rm.regmem = i.op[1].regs->reg_num;
6546 else
6547 i.rm.regmem = i.op[0].regs->reg_num;
6548
6549 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6550 i.rex |= REX_B;
6551 }
6552 }
2426c15f 6553 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6554 {
6555 i.vex.register_specifier = i.op[2].regs;
6556 if (!i.mem_operands)
6557 {
6558 i.rm.mode = 3;
6559 i.rm.regmem = i.op[1].regs->reg_num;
6560 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6561 i.rex |= REX_B;
6562 }
6563 }
29b0f896
AM		 6564 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6565 (if any) based on i.tm.extension_opcode. Again, we must be
6566 careful to make sure that segment/control/debug/test/MMX
6567 registers are coded into the i.rm.reg field. */
f88c9eb0 6568 else if (i.reg_operands)
29b0f896 6569 {
99018f42 6570 unsigned int op;
7ab9ffdd
L		 6571 unsigned int vex_reg = ~0;
6572
6573 for (op = 0; op < i.operands; op++)
6574 if (i.types[op].bitfield.reg8
6575 || i.types[op].bitfield.reg16
6576 || i.types[op].bitfield.reg32
6577 || i.types[op].bitfield.reg64
6578 || i.types[op].bitfield.regmmx
6579 || i.types[op].bitfield.regxmm
6580 || i.types[op].bitfield.regymm
7e8b059b 6581 || i.types[op].bitfield.regbnd
43234a1e
L		 6582 || i.types[op].bitfield.regzmm
6583 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6584 || i.types[op].bitfield.sreg2
6585 || i.types[op].bitfield.sreg3
6586 || i.types[op].bitfield.control
6587 || i.types[op].bitfield.debug
6588 || i.types[op].bitfield.test)
6589 break;
c0209578 6590
7ab9ffdd
L		 6591 if (vex_3_sources)
6592 op = dest;
2426c15f 6593 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6594 {
6595 /* For instructions with VexNDS, the register-only
6596 source operand is encoded in VEX prefix. */
6597 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6598
7ab9ffdd 6599 if (op > mem)
c0f3af97 6600 {
7ab9ffdd
L		 6601 vex_reg = op++;
6602 gas_assert (op < i.operands);
c0f3af97
L		 6603 }
6604 else
c0f3af97 6605 {
f12dc422
L		 6606 /* Check register-only source operand when two source
6607 operands are swapped. */
6608 if (!i.tm.operand_types[op].bitfield.baseindex
6609 && i.tm.operand_types[op + 1].bitfield.baseindex)
6610 {
6611 vex_reg = op;
6612 op += 2;
6613 gas_assert (mem == (vex_reg + 1)
6614 && op < i.operands);
6615 }
6616 else
6617 {
6618 vex_reg = op + 1;
6619 gas_assert (vex_reg < i.operands);
6620 }
c0f3af97 6621 }
7ab9ffdd 6622 }
2426c15f 6623 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6624 {
f12dc422 6625 /* For instructions with VexNDD, the register destination
7ab9ffdd 6626 is encoded in VEX prefix. */
f12dc422
L		 6627 if (i.mem_operands == 0)
6628 {
6629 /* There is no memory operand. */
6630 gas_assert ((op + 2) == i.operands);
6631 vex_reg = op + 1;
6632 }
6633 else
8d63c93e 6634 {
f12dc422
L		 6635 /* There are only 2 operands. */
6636 gas_assert (op < 2 && i.operands == 2);
6637 vex_reg = 1;
6638 }
7ab9ffdd
L		 6639 }
6640 else
6641 gas_assert (op < i.operands);
99018f42 6642
7ab9ffdd
L		 6643 if (vex_reg != (unsigned int) ~0)
6644 {
f12dc422 6645 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6646
f12dc422
L		 6647 if (type->bitfield.reg32 != 1
6648 && type->bitfield.reg64 != 1
6649 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6650 && !operand_type_equal (type, &regymm)
6651 && !operand_type_equal (type, &regzmm)
6652 && !operand_type_equal (type, &regmask))
7ab9ffdd 6653 abort ();
f88c9eb0 6654
7ab9ffdd
L		 6655 i.vex.register_specifier = i.op[vex_reg].regs;
6656 }
6657
1b9f0c97
L		 6658 /* Don't set OP operand twice. */
6659 if (vex_reg != op)
7ab9ffdd 6660 {
1b9f0c97
L		 6661 /* If there is an extension opcode to put here, the
6662 register number must be put into the regmem field. */
6663 if (i.tm.extension_opcode != None)
6664 {
6665 i.rm.regmem = i.op[op].regs->reg_num;
6666 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6667 i.rex |= REX_B;
43234a1e
L		 6668 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6669 i.vrex |= REX_B;
1b9f0c97
L		 6670 }
6671 else
6672 {
6673 i.rm.reg = i.op[op].regs->reg_num;
6674 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6675 i.rex |= REX_R;
43234a1e
L		 6676 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6677 i.vrex |= REX_R;
1b9f0c97 6678 }
7ab9ffdd 6679 }
252b5132 6680
29b0f896
AM		 6681 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6682 must set it to 3 to indicate this is a register operand
6683 in the regmem field. */
6684 if (!i.mem_operands)
6685 i.rm.mode = 3;
6686 }
252b5132 6687
29b0f896 6688 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6689 if (i.tm.extension_opcode != None)
29b0f896
AM		 6690 i.rm.reg = i.tm.extension_opcode;
6691 }
6692 return default_seg;
6693}
252b5132 6694
29b0f896 6695static void
e3bb37b5 6696output_branch (void)
29b0f896
AM		 6697{
6698 char *p;
f8a5c266 6699 int size;
29b0f896
AM		 6700 int code16;
6701 int prefix;
6702 relax_substateT subtype;
6703 symbolS *sym;
6704 offsetT off;
6705
f8a5c266 6706 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6707 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6708
6709 prefix = 0;
6710 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6711 {
29b0f896
AM		 6712 prefix = 1;
6713 i.prefixes -= 1;
6714 code16 ^= CODE16;
252b5132 6715 }
29b0f896
AM		 6716 /* Pentium4 branch hints. */
6717 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6718 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6719 {
29b0f896
AM		 6720 prefix++;
6721 i.prefixes--;
6722 }
6723 if (i.prefix[REX_PREFIX] != 0)
6724 {
6725 prefix++;
6726 i.prefixes--;
2f66722d
AM		 6727 }
6728
7e8b059b
L		 6729 /* BND prefixed jump. */
6730 if (i.prefix[BND_PREFIX] != 0)
6731 {
6732 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6733 i.prefixes -= 1;
6734 }
6735
29b0f896
AM		 6736 if (i.prefixes != 0 && !intel_syntax)
6737 as_warn (_("skipping prefixes on this instruction"));
6738
6739 /* It's always a symbol; End frag & setup for relax.
6740 Make sure there is enough room in this frag for the largest
6741 instruction we may generate in md_convert_frag. This is 2
6742 bytes for the opcode and room for the prefix and largest
6743 displacement. */
6744 frag_grow (prefix + 2 + 4);
6745 /* Prefix and 1 opcode byte go in fr_fix. */
6746 p = frag_more (prefix + 1);
6747 if (i.prefix[DATA_PREFIX] != 0)
6748 *p++ = DATA_PREFIX_OPCODE;
6749 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6750 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6751 *p++ = i.prefix[SEG_PREFIX];
6752 if (i.prefix[REX_PREFIX] != 0)
6753 *p++ = i.prefix[REX_PREFIX];
6754 *p = i.tm.base_opcode;
6755
6756 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6757 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6758 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6759 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6760 else
f8a5c266 6761 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6762 subtype |= code16;
3e73aa7c 6763
29b0f896
AM		 6764 sym = i.op[0].disps->X_add_symbol;
6765 off = i.op[0].disps->X_add_number;
3e73aa7c 6766
29b0f896
AM		 6767 if (i.op[0].disps->X_op != O_constant
6768 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6769 {
29b0f896
AM		 6770 /* Handle complex expressions. */
6771 sym = make_expr_symbol (i.op[0].disps);
6772 off = 0;
6773 }
3e73aa7c 6774
29b0f896
AM		 6775 /* 1 possible extra opcode + 4 byte displacement go in var part.
6776 Pass reloc in fr_var. */
c3320543
L		 6777 frag_var (rs_machine_dependent, 5,
6778 ((!object_64bit
6779 || i.reloc[0] != NO_RELOC
6780 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6781 ? i.reloc[0]
6782 : BFD_RELOC_X86_64_PC32_BND),
6783 subtype, sym, off, p);
29b0f896 6784}
3e73aa7c 6785
29b0f896 6786static void
e3bb37b5 6787output_jump (void)
29b0f896
AM		 6788{
6789 char *p;
6790 int size;
3e02c1cc 6791 fixS *fixP;
29b0f896 6792
40fb9820 6793 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6794 {
6795 /* This is a loop or jecxz type instruction. */
6796 size = 1;
6797 if (i.prefix[ADDR_PREFIX] != 0)
6798 {
6799 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6800 i.prefixes -= 1;
6801 }
6802 /* Pentium4 branch hints. */
6803 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6804 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6805 {
6806 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6807 i.prefixes--;
3e73aa7c
JH		 6808 }
6809 }
29b0f896
AM		 6810 else
6811 {
6812 int code16;
3e73aa7c 6813
29b0f896
AM		 6814 code16 = 0;
6815 if (flag_code == CODE_16BIT)
6816 code16 = CODE16;
3e73aa7c 6817
29b0f896
AM		 6818 if (i.prefix[DATA_PREFIX] != 0)
6819 {
6820 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6821 i.prefixes -= 1;
6822 code16 ^= CODE16;
6823 }
252b5132 6824
29b0f896
AM		 6825 size = 4;
6826 if (code16)
6827 size = 2;
6828 }
9fcc94b6 6829
29b0f896
AM		 6830 if (i.prefix[REX_PREFIX] != 0)
6831 {
6832 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6833 i.prefixes -= 1;
6834 }
252b5132 6835
7e8b059b
L		 6836 /* BND prefixed jump. */
6837 if (i.prefix[BND_PREFIX] != 0)
6838 {
6839 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6840 i.prefixes -= 1;
6841 }
6842
29b0f896
AM		 6843 if (i.prefixes != 0 && !intel_syntax)
6844 as_warn (_("skipping prefixes on this instruction"));
e0890092 6845
42164a71
L		 6846 p = frag_more (i.tm.opcode_length + size);
6847 switch (i.tm.opcode_length)
6848 {
6849 case 2:
6850 *p++ = i.tm.base_opcode >> 8;
6851 case 1:
6852 *p++ = i.tm.base_opcode;
6853 break;
6854 default:
6855 abort ();
6856 }
e0890092 6857
3e02c1cc 6858 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6859 i.op[0].disps, 1, reloc (size, 1, 1,
6860 (i.bnd_prefix != NULL
6861 || add_bnd_prefix),
6862 i.reloc[0]));
3e02c1cc
AM		 6863
6864 /* All jumps handled here are signed, but don't use a signed limit
6865 check for 32 and 16 bit jumps as we want to allow wrap around at
6866 4G and 64k respectively. */
6867 if (size == 1)
6868 fixP->fx_signed = 1;
29b0f896 6869}
e0890092 6870
29b0f896 6871static void
e3bb37b5 6872output_interseg_jump (void)
29b0f896
AM		 6873{
6874 char *p;
6875 int size;
6876 int prefix;
6877 int code16;
252b5132 6878
29b0f896
AM		 6879 code16 = 0;
6880 if (flag_code == CODE_16BIT)
6881 code16 = CODE16;
a217f122 6882
29b0f896
AM		 6883 prefix = 0;
6884 if (i.prefix[DATA_PREFIX] != 0)
6885 {
6886 prefix = 1;
6887 i.prefixes -= 1;
6888 code16 ^= CODE16;
6889 }
6890 if (i.prefix[REX_PREFIX] != 0)
6891 {
6892 prefix++;
6893 i.prefixes -= 1;
6894 }
252b5132 6895
29b0f896
AM		 6896 size = 4;
6897 if (code16)
6898 size = 2;
252b5132 6899
29b0f896
AM		 6900 if (i.prefixes != 0 && !intel_syntax)
6901 as_warn (_("skipping prefixes on this instruction"));
252b5132 6902
29b0f896
AM		 6903 /* 1 opcode; 2 segment; offset */
6904 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6905
29b0f896
AM		 6906 if (i.prefix[DATA_PREFIX] != 0)
6907 *p++ = DATA_PREFIX_OPCODE;
252b5132 6908
29b0f896
AM		 6909 if (i.prefix[REX_PREFIX] != 0)
6910 *p++ = i.prefix[REX_PREFIX];
252b5132 6911
29b0f896
AM		 6912 *p++ = i.tm.base_opcode;
6913 if (i.op[1].imms->X_op == O_constant)
6914 {
6915 offsetT n = i.op[1].imms->X_add_number;
252b5132 6916
29b0f896
AM		 6917 if (size == 2
6918 && !fits_in_unsigned_word (n)
6919 && !fits_in_signed_word (n))
6920 {
6921 as_bad (_("16-bit jump out of range"));
6922 return;
6923 }
6924 md_number_to_chars (p, n, size);
6925 }
6926 else
6927 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6928 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6929 if (i.op[0].imms->X_op != O_constant)
6930 as_bad (_("can't handle non absolute segment in `%s'"),
6931 i.tm.name);
6932 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6933}
a217f122 6934
29b0f896 6935static void
e3bb37b5 6936output_insn (void)
29b0f896 6937{
2bbd9c25
JJ		 6938 fragS *insn_start_frag;
6939 offsetT insn_start_off;
6940
29b0f896
AM		 6941 /* Tie dwarf2 debug info to the address at the start of the insn.
6942 We can't do this after the insn has been output as the current
6943 frag may have been closed off. eg. by frag_var. */
6944 dwarf2_emit_insn (0);
6945
2bbd9c25
JJ		 6946 insn_start_frag = frag_now;
6947 insn_start_off = frag_now_fix ();
6948
29b0f896 6949 /* Output jumps. */
40fb9820 6950 if (i.tm.opcode_modifier.jump)
29b0f896 6951 output_branch ();
40fb9820
L		 6952 else if (i.tm.opcode_modifier.jumpbyte
6953 || i.tm.opcode_modifier.jumpdword)
29b0f896 6954 output_jump ();
40fb9820 6955 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6956 output_interseg_jump ();
6957 else
6958 {
6959 /* Output normal instructions here. */
6960 char *p;
6961 unsigned char *q;
47465058 6962 unsigned int j;
331d2d0d 6963 unsigned int prefix;
4dffcebc 6964
d022bddd
IT		 6965 /* Some processors fail on LOCK prefix. This options makes
6966 assembler ignore LOCK prefix and serves as a workaround. */
6967 if (omit_lock_prefix)
6968 {
6969 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6970 return;
6971 i.prefix[LOCK_PREFIX] = 0;
6972 }
6973
43234a1e
L		 6974 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6975 don't need the explicit prefix. */
6976 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6977 {
c0f3af97 6978 switch (i.tm.opcode_length)
bc4bd9ab 6979 {
c0f3af97
L		 6980 case 3:
6981 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6982 {
c0f3af97
L		 6983 prefix = (i.tm.base_opcode >> 24) & 0xff;
6984 goto check_prefix;
6985 }
6986 break;
6987 case 2:
6988 if ((i.tm.base_opcode & 0xff0000) != 0)
6989 {
6990 prefix = (i.tm.base_opcode >> 16) & 0xff;
6991 if (i.tm.cpu_flags.bitfield.cpupadlock)
6992 {
4dffcebc 6993check_prefix:
c0f3af97 6994 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6995 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6996 != REPE_PREFIX_OPCODE))
6997 add_prefix (prefix);
6998 }
6999 else
4dffcebc
L		 7000 add_prefix (prefix);
7001 }
c0f3af97
L		 7002 break;
7003 case 1:
7004 break;
7005 default:
7006 abort ();
bc4bd9ab 7007 }
c0f3af97 7008
6d19a37a 7009#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7010 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7011 R_X86_64_GOTTPOFF relocation so that linker can safely
7012 perform IE->LE optimization. */
7013 if (x86_elf_abi == X86_64_X32_ABI
7014 && i.operands == 2
7015 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7016 && i.prefix[REX_PREFIX] == 0)
7017 add_prefix (REX_OPCODE);
6d19a37a 7018#endif
cf61b747 7019
c0f3af97
L		 7020 /* The prefix bytes. */
7021 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7022 if (*q)
7023 FRAG_APPEND_1_CHAR (*q);
0f10071e 7024 }
ae5c1c7b 7025 else
c0f3af97
L		 7026 {
7027 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7028 if (*q)
7029 switch (j)
7030 {
7031 case REX_PREFIX:
7032 /* REX byte is encoded in VEX prefix. */
7033 break;
7034 case SEG_PREFIX:
7035 case ADDR_PREFIX:
7036 FRAG_APPEND_1_CHAR (*q);
7037 break;
7038 default:
7039 /* There should be no other prefixes for instructions
7040 with VEX prefix. */
7041 abort ();
7042 }
7043
43234a1e
L		 7044 /* For EVEX instructions i.vrex should become 0 after
7045 build_evex_prefix. For VEX instructions upper 16 registers
7046 aren't available, so VREX should be 0. */
7047 if (i.vrex)
7048 abort ();
c0f3af97
L		 7049 /* Now the VEX prefix. */
7050 p = frag_more (i.vex.length);
7051 for (j = 0; j < i.vex.length; j++)
7052 p[j] = i.vex.bytes[j];
7053 }
252b5132 7054
29b0f896 7055 /* Now the opcode; be careful about word order here! */
4dffcebc 7056 if (i.tm.opcode_length == 1)
29b0f896
AM		 7057 {
7058 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7059 }
7060 else
7061 {
4dffcebc 7062 switch (i.tm.opcode_length)
331d2d0d 7063 {
43234a1e
L		 7064 case 4:
7065 p = frag_more (4);
7066 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7067 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7068 break;
4dffcebc 7069 case 3:
331d2d0d
L		 7070 p = frag_more (3);
7071 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7072 break;
7073 case 2:
7074 p = frag_more (2);
7075 break;
7076 default:
7077 abort ();
7078 break;
331d2d0d 7079 }
0f10071e 7080
29b0f896
AM		 7081 /* Put out high byte first: can't use md_number_to_chars! */
7082 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7083 *p = i.tm.base_opcode & 0xff;
7084 }
3e73aa7c 7085
29b0f896 7086 /* Now the modrm byte and sib byte (if present). */
40fb9820 7087 if (i.tm.opcode_modifier.modrm)
29b0f896 7088 {
4a3523fa
L		 7089 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7090 | i.rm.reg << 3
7091 | i.rm.mode << 6));
29b0f896
AM		 7092 /* If i.rm.regmem == ESP (4)
7093 && i.rm.mode != (Register mode)
7094 && not 16 bit
7095 ==> need second modrm byte. */
7096 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7097 && i.rm.mode != 3
40fb9820 7098 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7099 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7100 | i.sib.index << 3
7101 | i.sib.scale << 6));
29b0f896 7102 }
3e73aa7c 7103
29b0f896 7104 if (i.disp_operands)
2bbd9c25 7105 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7106
29b0f896 7107 if (i.imm_operands)
2bbd9c25 7108 output_imm (insn_start_frag, insn_start_off);
29b0f896 7109 }
252b5132 7110
29b0f896
AM		 7111#ifdef DEBUG386
7112 if (flag_debug)
7113 {
7b81dfbb 7114 pi ("" /*line*/, &i);
29b0f896
AM		 7115 }
7116#endif /* DEBUG386 */
7117}
252b5132 7118
e205caa7
L		 7119/* Return the size of the displacement operand N. */
7120
7121static int
7122disp_size (unsigned int n)
7123{
7124 int size = 4;
43234a1e
L		 7125
7126 /* Vec_Disp8 has to be 8bit. */
7127 if (i.types[n].bitfield.vec_disp8)
7128 size = 1;
7129 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7130 size = 8;
7131 else if (i.types[n].bitfield.disp8)
7132 size = 1;
7133 else if (i.types[n].bitfield.disp16)
7134 size = 2;
e205caa7
L		 7135 return size;
7136}
7137
7138/* Return the size of the immediate operand N. */
7139
7140static int
7141imm_size (unsigned int n)
7142{
7143 int size = 4;
40fb9820
L		 7144 if (i.types[n].bitfield.imm64)
7145 size = 8;
7146 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7147 size = 1;
7148 else if (i.types[n].bitfield.imm16)
7149 size = 2;
e205caa7
L		 7150 return size;
7151}
7152
29b0f896 7153static void
64e74474 7154output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7155{
7156 char *p;
7157 unsigned int n;
252b5132 7158
29b0f896
AM		 7159 for (n = 0; n < i.operands; n++)
7160 {
43234a1e
L		 7161 if (i.types[n].bitfield.vec_disp8
7162 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7163 {
7164 if (i.op[n].disps->X_op == O_constant)
7165 {
e205caa7 7166 int size = disp_size (n);
43234a1e 7167 offsetT val = i.op[n].disps->X_add_number;
252b5132 7168
43234a1e
L		 7169 if (i.types[n].bitfield.vec_disp8)
7170 val >>= i.memshift;
7171 val = offset_in_range (val, size);
29b0f896
AM		 7172 p = frag_more (size);
7173 md_number_to_chars (p, val, size);
7174 }
7175 else
7176 {
f86103b7 7177 enum bfd_reloc_code_real reloc_type;
e205caa7 7178 int size = disp_size (n);
40fb9820 7179 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7180 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7181
e205caa7 7182 /* We can't have 8 bit displacement here. */
9c2799c2 7183 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7184
29b0f896
AM		 7185 /* The PC relative address is computed relative
7186 to the instruction boundary, so in case immediate
7187 fields follows, we need to adjust the value. */
7188 if (pcrel && i.imm_operands)
7189 {
29b0f896 7190 unsigned int n1;
e205caa7 7191 int sz = 0;
252b5132 7192
29b0f896 7193 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7194 if (operand_type_check (i.types[n1], imm))
252b5132 7195 {
e205caa7
L		 7196 /* Only one immediate is allowed for PC
7197 relative address. */
9c2799c2 7198 gas_assert (sz == 0);
e205caa7
L		 7199 sz = imm_size (n1);
7200 i.op[n].disps->X_add_number -= sz;
252b5132 7201 }
29b0f896 7202 /* We should find the immediate. */
9c2799c2 7203 gas_assert (sz != 0);
29b0f896 7204 }
520dc8e8 7205
29b0f896 7206 p = frag_more (size);
c3320543
L		 7207 reloc_type = reloc (size, pcrel, sign,
7208 (i.bnd_prefix != NULL
7209 || add_bnd_prefix),
7210 i.reloc[n]);
d6ab8113 7211 if (GOT_symbol
2bbd9c25 7212 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7213 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7214 || reloc_type == BFD_RELOC_X86_64_32S
7215 || (reloc_type == BFD_RELOC_64
7216 && object_64bit))
d6ab8113
JB		 7217 && (i.op[n].disps->X_op == O_symbol
7218 || (i.op[n].disps->X_op == O_add
7219 && ((symbol_get_value_expression
7220 (i.op[n].disps->X_op_symbol)->X_op)
7221 == O_subtract))))
7222 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7223 {
7224 offsetT add;
7225
7226 if (insn_start_frag == frag_now)
7227 add = (p - frag_now->fr_literal) - insn_start_off;
7228 else
7229 {
7230 fragS *fr;
7231
7232 add = insn_start_frag->fr_fix - insn_start_off;
7233 for (fr = insn_start_frag->fr_next;
7234 fr && fr != frag_now; fr = fr->fr_next)
7235 add += fr->fr_fix;
7236 add += p - frag_now->fr_literal;
7237 }
7238
4fa24527 7239 if (!object_64bit)
7b81dfbb
AJ		 7240 {
7241 reloc_type = BFD_RELOC_386_GOTPC;
7242 i.op[n].imms->X_add_number += add;
7243 }
7244 else if (reloc_type == BFD_RELOC_64)
7245 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7246 else
7b81dfbb
AJ		 7247 /* Don't do the adjustment for x86-64, as there
7248 the pcrel addressing is relative to the _next_
7249 insn, and that is taken care of in other code. */
d6ab8113 7250 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7251 }
062cd5e7 7252 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7253 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7254 }
7255 }
7256 }
7257}
252b5132 7258
29b0f896 7259static void
64e74474 7260output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7261{
7262 char *p;
7263 unsigned int n;
252b5132 7264
29b0f896
AM		 7265 for (n = 0; n < i.operands; n++)
7266 {
43234a1e
L		 7267 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7268 if (i.rounding && (int) n == i.rounding->operand)
7269 continue;
7270
40fb9820 7271 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7272 {
7273 if (i.op[n].imms->X_op == O_constant)
7274 {
e205caa7 7275 int size = imm_size (n);
29b0f896 7276 offsetT val;
b4cac588 7277
29b0f896
AM		 7278 val = offset_in_range (i.op[n].imms->X_add_number,
7279 size);
7280 p = frag_more (size);
7281 md_number_to_chars (p, val, size);
7282 }
7283 else
7284 {
7285 /* Not absolute_section.
7286 Need a 32-bit fixup (don't support 8bit
7287 non-absolute imms). Try to support other
7288 sizes ... */
f86103b7 7289 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7290 int size = imm_size (n);
7291 int sign;
29b0f896 7292
40fb9820 7293 if (i.types[n].bitfield.imm32s
a7d61044 7294 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7295 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7296 sign = 1;
e205caa7
L		 7297 else
7298 sign = 0;
520dc8e8 7299
29b0f896 7300 p = frag_more (size);
c3320543 7301 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7302
2bbd9c25
JJ		 7303 /* This is tough to explain. We end up with this one if we
7304 * have operands that look like
7305 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7306 * obtain the absolute address of the GOT, and it is strongly
7307 * preferable from a performance point of view to avoid using
7308 * a runtime relocation for this. The actual sequence of
7309 * instructions often look something like:
7310 *
7311 * call .L66
7312 * .L66:
7313 * popl %ebx
7314 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7315 *
7316 * The call and pop essentially return the absolute address
7317 * of the label .L66 and store it in %ebx. The linker itself
7318 * will ultimately change the first operand of the addl so
7319 * that %ebx points to the GOT, but to keep things simple, the
7320 * .o file must have this operand set so that it generates not
7321 * the absolute address of .L66, but the absolute address of
7322 * itself. This allows the linker itself simply treat a GOTPC
7323 * relocation as asking for a pcrel offset to the GOT to be
7324 * added in, and the addend of the relocation is stored in the
7325 * operand field for the instruction itself.
7326 *
7327 * Our job here is to fix the operand so that it would add
7328 * the correct offset so that %ebx would point to itself. The
7329 * thing that is tricky is that .-.L66 will point to the
7330 * beginning of the instruction, so we need to further modify
7331 * the operand so that it will point to itself. There are
7332 * other cases where you have something like:
7333 *
7334 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7335 *
7336 * and here no correction would be required. Internally in
7337 * the assembler we treat operands of this form as not being
7338 * pcrel since the '.' is explicitly mentioned, and I wonder
7339 * whether it would simplify matters to do it this way. Who
7340 * knows. In earlier versions of the PIC patches, the
7341 * pcrel_adjust field was used to store the correction, but
7342 * since the expression is not pcrel, I felt it would be
7343 * confusing to do it this way. */
7344
d6ab8113 7345 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7346 || reloc_type == BFD_RELOC_X86_64_32S
7347 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7348 && GOT_symbol
7349 && GOT_symbol == i.op[n].imms->X_add_symbol
7350 && (i.op[n].imms->X_op == O_symbol
7351 || (i.op[n].imms->X_op == O_add
7352 && ((symbol_get_value_expression
7353 (i.op[n].imms->X_op_symbol)->X_op)
7354 == O_subtract))))
7355 {
2bbd9c25
JJ		 7356 offsetT add;
7357
7358 if (insn_start_frag == frag_now)
7359 add = (p - frag_now->fr_literal) - insn_start_off;
7360 else
7361 {
7362 fragS *fr;
7363
7364 add = insn_start_frag->fr_fix - insn_start_off;
7365 for (fr = insn_start_frag->fr_next;
7366 fr && fr != frag_now; fr = fr->fr_next)
7367 add += fr->fr_fix;
7368 add += p - frag_now->fr_literal;
7369 }
7370
4fa24527 7371 if (!object_64bit)
d6ab8113 7372 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7373 else if (size == 4)
d6ab8113 7374 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7375 else if (size == 8)
7376 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7377 i.op[n].imms->X_add_number += add;
29b0f896 7378 }
29b0f896
AM		 7379 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7380 i.op[n].imms, 0, reloc_type);
7381 }
7382 }
7383 }
252b5132
RH		 7384}
7385\f
d182319b
JB		 7386/* x86_cons_fix_new is called via the expression parsing code when a
7387 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7388static int cons_sign = -1;
7389
7390void
e3bb37b5 7391x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7392 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7393{
62ebcb5c 7394 r = reloc (len, 0, cons_sign, 0, r);
d182319b
JB		 7395
7396#ifdef TE_PE
7397 if (exp->X_op == O_secrel)
7398 {
7399 exp->X_op = O_symbol;
7400 r = BFD_RELOC_32_SECREL;
7401 }
7402#endif
7403
7404 fix_new_exp (frag, off, len, exp, 0, r);
7405}
7406
357d1bd8
L		 7407/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7408 purpose of the `.dc.a' internal pseudo-op. */
7409
7410int
7411x86_address_bytes (void)
7412{
7413 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7414 return 4;
7415 return stdoutput->arch_info->bits_per_address / 8;
7416}
7417
d382c579
TG		 7418#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7419 || defined (LEX_AT)
c06ec724 7420# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7421#else
f3c180ae
AM		 7422/* Parse operands of the form
7423 <symbol>@GOTOFF+<nnn>
7424 and similar .plt or .got references.
7425
7426 If we find one, set up the correct relocation in RELOC and copy the
7427 input string, minus the `@GOTOFF' into a malloc'd buffer for
7428 parsing by the calling routine. Return this buffer, and if ADJUST
7429 is non-null set it to the length of the string we removed from the
7430 input line. Otherwise return NULL. */
7431static char *
91d6fa6a 7432lex_got (enum bfd_reloc_code_real *rel,
64e74474 7433 int *adjust,
c3320543
L		 7434 i386_operand_type *types,
7435 int bnd_prefix)
f3c180ae 7436{
7b81dfbb
AJ		 7437 /* Some of the relocations depend on the size of what field is to
7438 be relocated. But in our callers i386_immediate and i386_displacement
7439 we don't yet know the operand size (this will be set by insn
7440 matching). Hence we record the word32 relocation here,
7441 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7442 static const struct {
7443 const char *str;
cff8d58a 7444 int len;
4fa24527 7445 const enum bfd_reloc_code_real rel[2];
40fb9820 7446 const i386_operand_type types64;
f3c180ae 7447 } gotrel[] = {
8ce3d284 7448#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7449 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7450 BFD_RELOC_SIZE32 },
7451 OPERAND_TYPE_IMM32_64 },
8ce3d284 7452#endif
cff8d58a
L		 7453 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7454 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7455 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7456 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7457 BFD_RELOC_X86_64_PLT32 },
40fb9820 7458 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7459 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7460 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7461 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7462 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7463 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7464 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7465 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7466 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7467 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7468 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7469 BFD_RELOC_X86_64_TLSGD },
40fb9820 7470 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7471 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7472 _dummy_first_bfd_reloc_code_real },
40fb9820 7473 OPERAND_TYPE_NONE },
cff8d58a
L		 7474 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7475 BFD_RELOC_X86_64_TLSLD },
40fb9820 7476 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7477 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7478 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7479 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7480 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7481 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7482 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7483 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7484 _dummy_first_bfd_reloc_code_real },
40fb9820 7485 OPERAND_TYPE_NONE },
cff8d58a
L		 7486 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7487 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7488 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7489 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7490 _dummy_first_bfd_reloc_code_real },
40fb9820 7491 OPERAND_TYPE_NONE },
cff8d58a
L		 7492 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7493 _dummy_first_bfd_reloc_code_real },
40fb9820 7494 OPERAND_TYPE_NONE },
cff8d58a
L		 7495 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7496 BFD_RELOC_X86_64_GOT32 },
40fb9820 7497 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7498 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7499 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7500 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7501 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7502 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7503 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7504 };
7505 char *cp;
7506 unsigned int j;
7507
d382c579 7508#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7509 if (!IS_ELF)
7510 return NULL;
d382c579 7511#endif
718ddfc0 7512
f3c180ae 7513 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7514 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7515 return NULL;
7516
47465058 7517 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7518 {
cff8d58a 7519 int len = gotrel[j].len;
28f81592 7520 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7521 {
4fa24527 7522 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7523 {
28f81592
AM		 7524 int first, second;
7525 char *tmpbuf, *past_reloc;
f3c180ae 7526
91d6fa6a 7527 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7528
3956db08
JB		 7529 if (types)
7530 {
7531 if (flag_code != CODE_64BIT)
40fb9820
L		 7532 {
7533 types->bitfield.imm32 = 1;
7534 types->bitfield.disp32 = 1;
7535 }
3956db08
JB		 7536 else
7537 *types = gotrel[j].types64;
7538 }
7539
8fd4256d 7540 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7541 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7542
28f81592 7543 /* The length of the first part of our input line. */
f3c180ae 7544 first = cp - input_line_pointer;
28f81592
AM		 7545
7546 /* The second part goes from after the reloc token until
67c11a9b 7547 (and including) an end_of_line char or comma. */
28f81592 7548 past_reloc = cp + 1 + len;
67c11a9b
AM		 7549 cp = past_reloc;
7550 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7551 ++cp;
7552 second = cp + 1 - past_reloc;
28f81592
AM		 7553
7554 /* Allocate and copy string. The trailing NUL shouldn't
7555 be necessary, but be safe. */
1e9cc1c2 7556 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7557 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7558 if (second != 0 && *past_reloc != ' ')
7559 /* Replace the relocation token with ' ', so that
7560 errors like foo@GOTOFF1 will be detected. */
7561 tmpbuf[first++] = ' ';
af89796a
L		 7562 else
7563 /* Increment length by 1 if the relocation token is
7564 removed. */
7565 len++;
7566 if (adjust)
7567 *adjust = len;
0787a12d
AM		 7568 memcpy (tmpbuf + first, past_reloc, second);
7569 tmpbuf[first + second] = '\0';
c3320543
L		 7570 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7571 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7572 return tmpbuf;
7573 }
7574
4fa24527
JB		 7575 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7576 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7577 return NULL;
7578 }
7579 }
7580
7581 /* Might be a symbol version string. Don't as_bad here. */
7582 return NULL;
7583}
4e4f7c87 7584#endif
f3c180ae 7585
a988325c
NC		 7586#ifdef TE_PE
7587#ifdef lex_got
7588#undef lex_got
7589#endif
7590/* Parse operands of the form
7591 <symbol>@SECREL32+<nnn>
7592
7593 If we find one, set up the correct relocation in RELOC and copy the
7594 input string, minus the `@SECREL32' into a malloc'd buffer for
7595 parsing by the calling routine. Return this buffer, and if ADJUST
7596 is non-null set it to the length of the string we removed from the
34bca508
L		 7597 input line. Otherwise return NULL.
7598
a988325c
NC		 7599 This function is copied from the ELF version above adjusted for PE targets. */
7600
7601static char *
7602lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7603 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7604 i386_operand_type *types,
7605 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7606{
7607 static const struct
7608 {
7609 const char *str;
7610 int len;
7611 const enum bfd_reloc_code_real rel[2];
7612 const i386_operand_type types64;
7613 }
7614 gotrel[] =
7615 {
7616 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7617 BFD_RELOC_32_SECREL },
7618 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7619 };
7620
7621 char *cp;
7622 unsigned j;
7623
7624 for (cp = input_line_pointer; *cp != '@'; cp++)
7625 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7626 return NULL;
7627
7628 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7629 {
7630 int len = gotrel[j].len;
7631
7632 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7633 {
7634 if (gotrel[j].rel[object_64bit] != 0)
7635 {
7636 int first, second;
7637 char *tmpbuf, *past_reloc;
7638
7639 *rel = gotrel[j].rel[object_64bit];
7640 if (adjust)
7641 *adjust = len;
7642
7643 if (types)
7644 {
7645 if (flag_code != CODE_64BIT)
7646 {
7647 types->bitfield.imm32 = 1;
7648 types->bitfield.disp32 = 1;
7649 }
7650 else
7651 *types = gotrel[j].types64;
7652 }
7653
7654 /* The length of the first part of our input line. */
7655 first = cp - input_line_pointer;
7656
7657 /* The second part goes from after the reloc token until
7658 (and including) an end_of_line char or comma. */
7659 past_reloc = cp + 1 + len;
7660 cp = past_reloc;
7661 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7662 ++cp;
7663 second = cp + 1 - past_reloc;
7664
7665 /* Allocate and copy string. The trailing NUL shouldn't
7666 be necessary, but be safe. */
7667 tmpbuf = (char *) xmalloc (first + second + 2);
7668 memcpy (tmpbuf, input_line_pointer, first);
7669 if (second != 0 && *past_reloc != ' ')
7670 /* Replace the relocation token with ' ', so that
7671 errors like foo@SECLREL321 will be detected. */
7672 tmpbuf[first++] = ' ';
7673 memcpy (tmpbuf + first, past_reloc, second);
7674 tmpbuf[first + second] = '\0';
7675 return tmpbuf;
7676 }
7677
7678 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7679 gotrel[j].str, 1 << (5 + object_64bit));
7680 return NULL;
7681 }
7682 }
7683
7684 /* Might be a symbol version string. Don't as_bad here. */
7685 return NULL;
7686}
7687
7688#endif /* TE_PE */
7689
62ebcb5c 7690bfd_reloc_code_real_type
e3bb37b5 7691x86_cons (expressionS *exp, int size)
f3c180ae 7692{
62ebcb5c
AM		 7693 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7694
ee86248c
JB		 7695 intel_syntax = -intel_syntax;
7696
3c7b9c2c 7697 exp->X_md = 0;
4fa24527 7698 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7699 {
7700 /* Handle @GOTOFF and the like in an expression. */
7701 char *save;
7702 char *gotfree_input_line;
4a57f2cf 7703 int adjust = 0;
f3c180ae
AM		 7704
7705 save = input_line_pointer;
c3320543 7706 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7707 if (gotfree_input_line)
7708 input_line_pointer = gotfree_input_line;
7709
7710 expression (exp);
7711
7712 if (gotfree_input_line)
7713 {
7714 /* expression () has merrily parsed up to the end of line,
7715 or a comma - in the wrong buffer. Transfer how far
7716 input_line_pointer has moved to the right buffer. */
7717 input_line_pointer = (save
7718 + (input_line_pointer - gotfree_input_line)
7719 + adjust);
7720 free (gotfree_input_line);
3992d3b7
AM		 7721 if (exp->X_op == O_constant
7722 || exp->X_op == O_absent
7723 || exp->X_op == O_illegal
0398aac5 7724 || exp->X_op == O_register
3992d3b7
AM		 7725 || exp->X_op == O_big)
7726 {
7727 char c = *input_line_pointer;
7728 *input_line_pointer = 0;
7729 as_bad (_("missing or invalid expression `%s'"), save);
7730 *input_line_pointer = c;
7731 }
f3c180ae
AM		 7732 }
7733 }
7734 else
7735 expression (exp);
ee86248c
JB		 7736
7737 intel_syntax = -intel_syntax;
7738
7739 if (intel_syntax)
7740 i386_intel_simplify (exp);
62ebcb5c
AM		 7741
7742 return got_reloc;
f3c180ae 7743}
f3c180ae 7744
9f32dd5b
L		 7745static void
7746signed_cons (int size)
6482c264 7747{
d182319b
JB		 7748 if (flag_code == CODE_64BIT)
7749 cons_sign = 1;
7750 cons (size);
7751 cons_sign = -1;
6482c264
NC		 7752}
7753
d182319b 7754#ifdef TE_PE
6482c264 7755static void
7016a5d5 7756pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7757{
7758 expressionS exp;
7759
7760 do
7761 {
7762 expression (&exp);
7763 if (exp.X_op == O_symbol)
7764 exp.X_op = O_secrel;
7765
7766 emit_expr (&exp, 4);
7767 }
7768 while (*input_line_pointer++ == ',');
7769
7770 input_line_pointer--;
7771 demand_empty_rest_of_line ();
7772}
6482c264
NC		 7773#endif
7774
43234a1e
L		 7775/* Handle Vector operations. */
7776
7777static char *
7778check_VecOperations (char *op_string, char *op_end)
7779{
7780 const reg_entry *mask;
7781 const char *saved;
7782 char *end_op;
7783
7784 while (*op_string
7785 && (op_end == NULL || op_string < op_end))
7786 {
7787 saved = op_string;
7788 if (*op_string == '{')
7789 {
7790 op_string++;
7791
7792 /* Check broadcasts. */
7793 if (strncmp (op_string, "1to", 3) == 0)
7794 {
7795 int bcst_type;
7796
7797 if (i.broadcast)
7798 goto duplicated_vec_op;
7799
7800 op_string += 3;
7801 if (*op_string == '8')
7802 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7803 else if (*op_string == '4')
7804 bcst_type = BROADCAST_1TO4;
7805 else if (*op_string == '2')
7806 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7807 else if (*op_string == '1'
7808 && *(op_string+1) == '6')
7809 {
7810 bcst_type = BROADCAST_1TO16;
7811 op_string++;
7812 }
7813 else
7814 {
7815 as_bad (_("Unsupported broadcast: `%s'"), saved);
7816 return NULL;
7817 }
7818 op_string++;
7819
7820 broadcast_op.type = bcst_type;
7821 broadcast_op.operand = this_operand;
7822 i.broadcast = &broadcast_op;
7823 }
7824 /* Check masking operation. */
7825 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7826 {
7827 /* k0 can't be used for write mask. */
7828 if (mask->reg_num == 0)
7829 {
7830 as_bad (_("`%s' can't be used for write mask"),
7831 op_string);
7832 return NULL;
7833 }
7834
7835 if (!i.mask)
7836 {
7837 mask_op.mask = mask;
7838 mask_op.zeroing = 0;
7839 mask_op.operand = this_operand;
7840 i.mask = &mask_op;
7841 }
7842 else
7843 {
7844 if (i.mask->mask)
7845 goto duplicated_vec_op;
7846
7847 i.mask->mask = mask;
7848
7849 /* Only "{z}" is allowed here. No need to check
7850 zeroing mask explicitly. */
7851 if (i.mask->operand != this_operand)
7852 {
7853 as_bad (_("invalid write mask `%s'"), saved);
7854 return NULL;
7855 }
7856 }
7857
7858 op_string = end_op;
7859 }
7860 /* Check zeroing-flag for masking operation. */
7861 else if (*op_string == 'z')
7862 {
7863 if (!i.mask)
7864 {
7865 mask_op.mask = NULL;
7866 mask_op.zeroing = 1;
7867 mask_op.operand = this_operand;
7868 i.mask = &mask_op;
7869 }
7870 else
7871 {
7872 if (i.mask->zeroing)
7873 {
7874 duplicated_vec_op:
7875 as_bad (_("duplicated `%s'"), saved);
7876 return NULL;
7877 }
7878
7879 i.mask->zeroing = 1;
7880
7881 /* Only "{%k}" is allowed here. No need to check mask
7882 register explicitly. */
7883 if (i.mask->operand != this_operand)
7884 {
7885 as_bad (_("invalid zeroing-masking `%s'"),
7886 saved);
7887 return NULL;
7888 }
7889 }
7890
7891 op_string++;
7892 }
7893 else
7894 goto unknown_vec_op;
7895
7896 if (*op_string != '}')
7897 {
7898 as_bad (_("missing `}' in `%s'"), saved);
7899 return NULL;
7900 }
7901 op_string++;
7902 continue;
7903 }
7904 unknown_vec_op:
7905 /* We don't know this one. */
7906 as_bad (_("unknown vector operation: `%s'"), saved);
7907 return NULL;
7908 }
7909
7910 return op_string;
7911}
7912
252b5132 7913static int
70e41ade 7914i386_immediate (char *imm_start)
252b5132
RH		 7915{
7916 char *save_input_line_pointer;
f3c180ae 7917 char *gotfree_input_line;
252b5132 7918 segT exp_seg = 0;
47926f60 7919 expressionS *exp;
40fb9820
L		 7920 i386_operand_type types;
7921
0dfbf9d7 7922 operand_type_set (&types, ~0);
252b5132
RH		 7923
7924 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7925 {
31b2323c
L		 7926 as_bad (_("at most %d immediate operands are allowed"),
7927 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7928 return 0;
7929 }
7930
7931 exp = &im_expressions[i.imm_operands++];
520dc8e8 7932 i.op[this_operand].imms = exp;
252b5132
RH		 7933
7934 if (is_space_char (*imm_start))
7935 ++imm_start;
7936
7937 save_input_line_pointer = input_line_pointer;
7938 input_line_pointer = imm_start;
7939
c3320543
L		 7940 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7941 (i.bnd_prefix != NULL
7942 || add_bnd_prefix));
f3c180ae
AM		 7943 if (gotfree_input_line)
7944 input_line_pointer = gotfree_input_line;
252b5132
RH		 7945
7946 exp_seg = expression (exp);
7947
83183c0c 7948 SKIP_WHITESPACE ();
43234a1e
L		 7949
7950 /* Handle vector operations. */
7951 if (*input_line_pointer == '{')
7952 {
7953 input_line_pointer = check_VecOperations (input_line_pointer,
7954 NULL);
7955 if (input_line_pointer == NULL)
7956 return 0;
7957 }
7958
252b5132 7959 if (*input_line_pointer)
f3c180ae 7960 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7961
7962 input_line_pointer = save_input_line_pointer;
f3c180ae 7963 if (gotfree_input_line)
ee86248c
JB		 7964 {
7965 free (gotfree_input_line);
7966
7967 if (exp->X_op == O_constant || exp->X_op == O_register)
7968 exp->X_op = O_illegal;
7969 }
7970
7971 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7972}
252b5132 7973
ee86248c
JB		 7974static int
7975i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7976 i386_operand_type types, const char *imm_start)
7977{
7978 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7979 {
313c53d1
L		 7980 if (imm_start)
7981 as_bad (_("missing or invalid immediate expression `%s'"),
7982 imm_start);
3992d3b7 7983 return 0;
252b5132 7984 }
3e73aa7c 7985 else if (exp->X_op == O_constant)
252b5132 7986 {
47926f60 7987 /* Size it properly later. */
40fb9820 7988 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7989 /* If not 64bit, sign extend val. */
7990 if (flag_code != CODE_64BIT
4eed87de
AM		 7991 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7992 exp->X_add_number
7993 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7994 }
4c63da97 7995#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7996 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7997 && exp_seg != absolute_section
47926f60 7998 && exp_seg != text_section
24eab124
AM		 7999 && exp_seg != data_section
8000 && exp_seg != bss_section
8001 && exp_seg != undefined_section
f86103b7 8002 && !bfd_is_com_section (exp_seg))
252b5132 8003 {
d0b47220 8004 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8005 return 0;
8006 }
8007#endif
a841bdf5 8008 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8009 {
313c53d1
L		 8010 if (imm_start)
8011 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8012 return 0;
8013 }
252b5132
RH		 8014 else
8015 {
8016 /* This is an address. The size of the address will be
24eab124 8017 determined later, depending on destination register,
3e73aa7c 8018 suffix, or the default for the section. */
40fb9820
L		 8019 i.types[this_operand].bitfield.imm8 = 1;
8020 i.types[this_operand].bitfield.imm16 = 1;
8021 i.types[this_operand].bitfield.imm32 = 1;
8022 i.types[this_operand].bitfield.imm32s = 1;
8023 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8024 i.types[this_operand] = operand_type_and (i.types[this_operand],
8025 types);
252b5132
RH		 8026 }
8027
8028 return 1;
8029}
8030
551c1ca1 8031static char *
e3bb37b5 8032i386_scale (char *scale)
252b5132 8033{
551c1ca1
AM		 8034 offsetT val;
8035 char *save = input_line_pointer;
252b5132 8036
551c1ca1
AM		 8037 input_line_pointer = scale;
8038 val = get_absolute_expression ();
8039
8040 switch (val)
252b5132 8041 {
551c1ca1 8042 case 1:
252b5132
RH		 8043 i.log2_scale_factor = 0;
8044 break;
551c1ca1 8045 case 2:
252b5132
RH		 8046 i.log2_scale_factor = 1;
8047 break;
551c1ca1 8048 case 4:
252b5132
RH		 8049 i.log2_scale_factor = 2;
8050 break;
551c1ca1 8051 case 8:
252b5132
RH		 8052 i.log2_scale_factor = 3;
8053 break;
8054 default:
a724f0f4
JB		 8055 {
8056 char sep = *input_line_pointer;
8057
8058 *input_line_pointer = '\0';
8059 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8060 scale);
8061 *input_line_pointer = sep;
8062 input_line_pointer = save;
8063 return NULL;
8064 }
252b5132 8065 }
29b0f896 8066 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8067 {
8068 as_warn (_("scale factor of %d without an index register"),
24eab124 8069 1 << i.log2_scale_factor);
252b5132 8070 i.log2_scale_factor = 0;
252b5132 8071 }
551c1ca1
AM		 8072 scale = input_line_pointer;
8073 input_line_pointer = save;
8074 return scale;
252b5132
RH		 8075}
8076
252b5132 8077static int
e3bb37b5 8078i386_displacement (char *disp_start, char *disp_end)
252b5132 8079{
29b0f896 8080 expressionS *exp;
252b5132
RH		 8081 segT exp_seg = 0;
8082 char *save_input_line_pointer;
f3c180ae 8083 char *gotfree_input_line;
40fb9820
L		 8084 int override;
8085 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8086 int ret;
252b5132 8087
31b2323c
L		 8088 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8089 {
8090 as_bad (_("at most %d displacement operands are allowed"),
8091 MAX_MEMORY_OPERANDS);
8092 return 0;
8093 }
8094
0dfbf9d7 8095 operand_type_set (&bigdisp, 0);
40fb9820
L		 8096 if ((i.types[this_operand].bitfield.jumpabsolute)
8097 || (!current_templates->start->opcode_modifier.jump
8098 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8099 {
40fb9820 8100 bigdisp.bitfield.disp32 = 1;
e05278af 8101 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8102 if (flag_code == CODE_64BIT)
8103 {
8104 if (!override)
8105 {
8106 bigdisp.bitfield.disp32s = 1;
8107 bigdisp.bitfield.disp64 = 1;
8108 }
8109 }
8110 else if ((flag_code == CODE_16BIT) ^ override)
8111 {
8112 bigdisp.bitfield.disp32 = 0;
8113 bigdisp.bitfield.disp16 = 1;
8114 }
e05278af
JB		 8115 }
8116 else
8117 {
8118 /* For PC-relative branches, the width of the displacement
8119 is dependent upon data size, not address size. */
e05278af 8120 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8121 if (flag_code == CODE_64BIT)
8122 {
8123 if (override || i.suffix == WORD_MNEM_SUFFIX)
8124 bigdisp.bitfield.disp16 = 1;
8125 else
8126 {
8127 bigdisp.bitfield.disp32 = 1;
8128 bigdisp.bitfield.disp32s = 1;
8129 }
8130 }
8131 else
e05278af
JB		 8132 {
8133 if (!override)
8134 override = (i.suffix == (flag_code != CODE_16BIT
8135 ? WORD_MNEM_SUFFIX
8136 : LONG_MNEM_SUFFIX));
40fb9820
L		 8137 bigdisp.bitfield.disp32 = 1;
8138 if ((flag_code == CODE_16BIT) ^ override)
8139 {
8140 bigdisp.bitfield.disp32 = 0;
8141 bigdisp.bitfield.disp16 = 1;
8142 }
e05278af 8143 }
e05278af 8144 }
c6fb90c8
L		 8145 i.types[this_operand] = operand_type_or (i.types[this_operand],
8146 bigdisp);
252b5132
RH		 8147
8148 exp = &disp_expressions[i.disp_operands];
520dc8e8 8149 i.op[this_operand].disps = exp;
252b5132
RH		 8150 i.disp_operands++;
8151 save_input_line_pointer = input_line_pointer;
8152 input_line_pointer = disp_start;
8153 END_STRING_AND_SAVE (disp_end);
8154
8155#ifndef GCC_ASM_O_HACK
8156#define GCC_ASM_O_HACK 0
8157#endif
8158#if GCC_ASM_O_HACK
8159 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8160 if (i.types[this_operand].bitfield.baseIndex
24eab124 8161 && displacement_string_end[-1] == '+')
252b5132
RH		 8162 {
8163 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8164 constraint within gcc asm statements.
8165 For instance:
8166
8167 #define _set_tssldt_desc(n,addr,limit,type) \
8168 __asm__ __volatile__ ( \
8169 "movw %w2,%0\n\t" \
8170 "movw %w1,2+%0\n\t" \
8171 "rorl $16,%1\n\t" \
8172 "movb %b1,4+%0\n\t" \
8173 "movb %4,5+%0\n\t" \
8174 "movb $0,6+%0\n\t" \
8175 "movb %h1,7+%0\n\t" \
8176 "rorl $16,%1" \
8177 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8178
8179 This works great except that the output assembler ends
8180 up looking a bit weird if it turns out that there is
8181 no offset. You end up producing code that looks like:
8182
8183 #APP
8184 movw $235,(%eax)
8185 movw %dx,2+(%eax)
8186 rorl $16,%edx
8187 movb %dl,4+(%eax)
8188 movb $137,5+(%eax)
8189 movb $0,6+(%eax)
8190 movb %dh,7+(%eax)
8191 rorl $16,%edx
8192 #NO_APP
8193
47926f60 8194 So here we provide the missing zero. */
24eab124
AM		 8195
8196 *displacement_string_end = '0';
252b5132
RH		 8197 }
8198#endif
c3320543
L		 8199 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8200 (i.bnd_prefix != NULL
8201 || add_bnd_prefix));
f3c180ae
AM		 8202 if (gotfree_input_line)
8203 input_line_pointer = gotfree_input_line;
252b5132 8204
24eab124 8205 exp_seg = expression (exp);
252b5132 8206
636c26b0
AM		 8207 SKIP_WHITESPACE ();
8208 if (*input_line_pointer)
8209 as_bad (_("junk `%s' after expression"), input_line_pointer);
8210#if GCC_ASM_O_HACK
8211 RESTORE_END_STRING (disp_end + 1);
8212#endif
636c26b0 8213 input_line_pointer = save_input_line_pointer;
636c26b0 8214 if (gotfree_input_line)
ee86248c
JB		 8215 {
8216 free (gotfree_input_line);
8217
8218 if (exp->X_op == O_constant || exp->X_op == O_register)
8219 exp->X_op = O_illegal;
8220 }
8221
8222 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8223
8224 RESTORE_END_STRING (disp_end);
8225
8226 return ret;
8227}
8228
8229static int
8230i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8231 i386_operand_type types, const char *disp_start)
8232{
8233 i386_operand_type bigdisp;
8234 int ret = 1;
636c26b0 8235
24eab124
AM		 8236 /* We do this to make sure that the section symbol is in
8237 the symbol table. We will ultimately change the relocation
47926f60 8238 to be relative to the beginning of the section. */
1ae12ab7 8239 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8240 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8241 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8242 {
636c26b0 8243 if (exp->X_op != O_symbol)
3992d3b7 8244 goto inv_disp;
636c26b0 8245
e5cb08ac 8246 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8247 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8248 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8249 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8250 exp->X_op = O_subtract;
8251 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8252 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8253 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8254 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8255 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8256 else
29b0f896 8257 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8258 }
252b5132 8259
3992d3b7
AM		 8260 else if (exp->X_op == O_absent
8261 || exp->X_op == O_illegal
ee86248c 8262 || exp->X_op == O_big)
2daf4fd8 8263 {
3992d3b7
AM		 8264 inv_disp:
8265 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8266 disp_start);
3992d3b7 8267 ret = 0;
2daf4fd8
AM		 8268 }
8269
0e1147d9
L		 8270 else if (flag_code == CODE_64BIT
8271 && !i.prefix[ADDR_PREFIX]
8272 && exp->X_op == O_constant)
8273 {
8274 /* Since displacement is signed extended to 64bit, don't allow
8275 disp32 and turn off disp32s if they are out of range. */
8276 i.types[this_operand].bitfield.disp32 = 0;
8277 if (!fits_in_signed_long (exp->X_add_number))
8278 {
8279 i.types[this_operand].bitfield.disp32s = 0;
8280 if (i.types[this_operand].bitfield.baseindex)
8281 {
8282 as_bad (_("0x%lx out range of signed 32bit displacement"),
8283 (long) exp->X_add_number);
8284 ret = 0;
8285 }
8286 }
8287 }
8288
4c63da97 8289#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8290 else if (exp->X_op != O_constant
8291 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8292 && exp_seg != absolute_section
8293 && exp_seg != text_section
8294 && exp_seg != data_section
8295 && exp_seg != bss_section
8296 && exp_seg != undefined_section
8297 && !bfd_is_com_section (exp_seg))
24eab124 8298 {
d0b47220 8299 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8300 ret = 0;
24eab124 8301 }
252b5132 8302#endif
3956db08 8303
40fb9820
L		 8304 /* Check if this is a displacement only operand. */
8305 bigdisp = i.types[this_operand];
8306 bigdisp.bitfield.disp8 = 0;
8307 bigdisp.bitfield.disp16 = 0;
8308 bigdisp.bitfield.disp32 = 0;
8309 bigdisp.bitfield.disp32s = 0;
8310 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8311 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8312 i.types[this_operand] = operand_type_and (i.types[this_operand],
8313 types);
3956db08 8314
3992d3b7 8315 return ret;
252b5132
RH		 8316}
8317
eecb386c 8318/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8319 Return 1 on success, 0 on a failure. */
8320
252b5132 8321static int
e3bb37b5 8322i386_index_check (const char *operand_string)
252b5132 8323{
fc0763e6 8324 const char *kind = "base/index";
be05d201
L		 8325 enum flag_code addr_mode;
8326
8327 if (i.prefix[ADDR_PREFIX])
8328 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8329 else
8330 {
8331 addr_mode = flag_code;
8332
24eab124 8333#if INFER_ADDR_PREFIX
be05d201
L		 8334 if (i.mem_operands == 0)
8335 {
8336 /* Infer address prefix from the first memory operand. */
8337 const reg_entry *addr_reg = i.base_reg;
8338
8339 if (addr_reg == NULL)
8340 addr_reg = i.index_reg;
eecb386c 8341
be05d201
L		 8342 if (addr_reg)
8343 {
8344 if (addr_reg->reg_num == RegEip
8345 || addr_reg->reg_num == RegEiz
8346 || addr_reg->reg_type.bitfield.reg32)
8347 addr_mode = CODE_32BIT;
8348 else if (flag_code != CODE_64BIT
8349 && addr_reg->reg_type.bitfield.reg16)
8350 addr_mode = CODE_16BIT;
8351
8352 if (addr_mode != flag_code)
8353 {
8354 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8355 i.prefixes += 1;
8356 /* Change the size of any displacement too. At most one
8357 of Disp16 or Disp32 is set.
8358 FIXME. There doesn't seem to be any real need for
8359 separate Disp16 and Disp32 flags. The same goes for
8360 Imm16 and Imm32. Removing them would probably clean
8361 up the code quite a lot. */
8362 if (flag_code != CODE_64BIT
8363 && (i.types[this_operand].bitfield.disp16
8364 || i.types[this_operand].bitfield.disp32))
8365 i.types[this_operand]
8366 = operand_type_xor (i.types[this_operand], disp16_32);
8367 }
8368 }
8369 }
24eab124 8370#endif
be05d201
L		 8371 }
8372
fc0763e6
JB		 8373 if (current_templates->start->opcode_modifier.isstring
8374 && !current_templates->start->opcode_modifier.immext
8375 && (current_templates->end[-1].opcode_modifier.isstring
8376 || i.mem_operands))
8377 {
8378 /* Memory operands of string insns are special in that they only allow
8379 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8380 const reg_entry *expected_reg;
8381 static const char *di_si[][2] =
8382 {
8383 { "esi", "edi" },
8384 { "si", "di" },
8385 { "rsi", "rdi" }
8386 };
8387 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8388
8389 kind = "string address";
8390
8391 if (current_templates->start->opcode_modifier.w)
8392 {
8393 i386_operand_type type = current_templates->end[-1].operand_types[0];
8394
8395 if (!type.bitfield.baseindex
8396 || ((!i.mem_operands != !intel_syntax)
8397 && current_templates->end[-1].operand_types[1]
8398 .bitfield.baseindex))
8399 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8400 expected_reg = hash_find (reg_hash,
8401 di_si[addr_mode][type.bitfield.esseg]);
8402
fc0763e6
JB		 8403 }
8404 else
be05d201 8405 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8406
be05d201
L		 8407 if (i.base_reg != expected_reg
8408 || i.index_reg
fc0763e6 8409 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8410 {
be05d201
L		 8411 /* The second memory operand must have the same size as
8412 the first one. */
8413 if (i.mem_operands
8414 && i.base_reg
8415 && !((addr_mode == CODE_64BIT
8416 && i.base_reg->reg_type.bitfield.reg64)
8417 || (addr_mode == CODE_32BIT
8418 ? i.base_reg->reg_type.bitfield.reg32
8419 : i.base_reg->reg_type.bitfield.reg16)))
8420 goto bad_address;
8421
fc0763e6
JB		 8422 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8423 operand_string,
8424 intel_syntax ? '[' : '(',
8425 register_prefix,
be05d201 8426 expected_reg->reg_name,
fc0763e6 8427 intel_syntax ? ']' : ')');
be05d201 8428 return 1;
fc0763e6 8429 }
be05d201
L		 8430 else
8431 return 1;
8432
8433bad_address:
8434 as_bad (_("`%s' is not a valid %s expression"),
8435 operand_string, kind);
8436 return 0;
3e73aa7c
JH		 8437 }
8438 else
8439 {
be05d201
L		 8440 if (addr_mode != CODE_16BIT)
8441 {
8442 /* 32-bit/64-bit checks. */
8443 if ((i.base_reg
8444 && (addr_mode == CODE_64BIT
8445 ? !i.base_reg->reg_type.bitfield.reg64
8446 : !i.base_reg->reg_type.bitfield.reg32)
8447 && (i.index_reg
8448 || (i.base_reg->reg_num
8449 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8450 || (i.index_reg
8451 && !i.index_reg->reg_type.bitfield.regxmm
8452 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8453 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8454 && ((addr_mode == CODE_64BIT
8455 ? !(i.index_reg->reg_type.bitfield.reg64
8456 || i.index_reg->reg_num == RegRiz)
8457 : !(i.index_reg->reg_type.bitfield.reg32
8458 || i.index_reg->reg_num == RegEiz))
8459 || !i.index_reg->reg_type.bitfield.baseindex)))
8460 goto bad_address;
8461 }
8462 else
3e73aa7c 8463 {
be05d201 8464 /* 16-bit checks. */
3e73aa7c 8465 if ((i.base_reg
40fb9820
L		 8466 && (!i.base_reg->reg_type.bitfield.reg16
8467 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8468 || (i.index_reg
40fb9820
L		 8469 && (!i.index_reg->reg_type.bitfield.reg16
8470 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8471 || !(i.base_reg
8472 && i.base_reg->reg_num < 6
8473 && i.index_reg->reg_num >= 6
8474 && i.log2_scale_factor == 0))))
be05d201 8475 goto bad_address;
3e73aa7c
JH		 8476 }
8477 }
be05d201 8478 return 1;
24eab124 8479}
252b5132 8480
43234a1e
L		 8481/* Handle vector immediates. */
8482
8483static int
8484RC_SAE_immediate (const char *imm_start)
8485{
8486 unsigned int match_found, j;
8487 const char *pstr = imm_start;
8488 expressionS *exp;
8489
8490 if (*pstr != '{')
8491 return 0;
8492
8493 pstr++;
8494 match_found = 0;
8495 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8496 {
8497 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8498 {
8499 if (!i.rounding)
8500 {
8501 rc_op.type = RC_NamesTable[j].type;
8502 rc_op.operand = this_operand;
8503 i.rounding = &rc_op;
8504 }
8505 else
8506 {
8507 as_bad (_("duplicated `%s'"), imm_start);
8508 return 0;
8509 }
8510 pstr += RC_NamesTable[j].len;
8511 match_found = 1;
8512 break;
8513 }
8514 }
8515 if (!match_found)
8516 return 0;
8517
8518 if (*pstr++ != '}')
8519 {
8520 as_bad (_("Missing '}': '%s'"), imm_start);
8521 return 0;
8522 }
8523 /* RC/SAE immediate string should contain nothing more. */;
8524 if (*pstr != 0)
8525 {
8526 as_bad (_("Junk after '}': '%s'"), imm_start);
8527 return 0;
8528 }
8529
8530 exp = &im_expressions[i.imm_operands++];
8531 i.op[this_operand].imms = exp;
8532
8533 exp->X_op = O_constant;
8534 exp->X_add_number = 0;
8535 exp->X_add_symbol = (symbolS *) 0;
8536 exp->X_op_symbol = (symbolS *) 0;
8537
8538 i.types[this_operand].bitfield.imm8 = 1;
8539 return 1;
8540}
8541
fc0763e6 8542/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8543 on error. */
252b5132 8544
252b5132 8545static int
a7619375 8546i386_att_operand (char *operand_string)
252b5132 8547{
af6bdddf
AM		 8548 const reg_entry *r;
8549 char *end_op;
24eab124 8550 char *op_string = operand_string;
252b5132 8551
24eab124 8552 if (is_space_char (*op_string))
252b5132
RH		 8553 ++op_string;
8554
24eab124 8555 /* We check for an absolute prefix (differentiating,
47926f60 8556 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8557 if (*op_string == ABSOLUTE_PREFIX)
8558 {
8559 ++op_string;
8560 if (is_space_char (*op_string))
8561 ++op_string;
40fb9820 8562 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8563 }
252b5132 8564
47926f60 8565 /* Check if operand is a register. */
4d1bb795 8566 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8567 {
40fb9820
L		 8568 i386_operand_type temp;
8569
24eab124
AM		 8570 /* Check for a segment override by searching for ':' after a
8571 segment register. */
8572 op_string = end_op;
8573 if (is_space_char (*op_string))
8574 ++op_string;
40fb9820
L		 8575 if (*op_string == ':'
8576 && (r->reg_type.bitfield.sreg2
8577 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8578 {
8579 switch (r->reg_num)
8580 {
8581 case 0:
8582 i.seg[i.mem_operands] = &es;
8583 break;
8584 case 1:
8585 i.seg[i.mem_operands] = &cs;
8586 break;
8587 case 2:
8588 i.seg[i.mem_operands] = &ss;
8589 break;
8590 case 3:
8591 i.seg[i.mem_operands] = &ds;
8592 break;
8593 case 4:
8594 i.seg[i.mem_operands] = &fs;
8595 break;
8596 case 5:
8597 i.seg[i.mem_operands] = &gs;
8598 break;
8599 }
252b5132 8600
24eab124 8601 /* Skip the ':' and whitespace. */
252b5132
RH		 8602 ++op_string;
8603 if (is_space_char (*op_string))
24eab124 8604 ++op_string;
252b5132 8605
24eab124
AM		 8606 if (!is_digit_char (*op_string)
8607 && !is_identifier_char (*op_string)
8608 && *op_string != '('
8609 && *op_string != ABSOLUTE_PREFIX)
8610 {
8611 as_bad (_("bad memory operand `%s'"), op_string);
8612 return 0;
8613 }
47926f60 8614 /* Handle case of %es:*foo. */
24eab124
AM		 8615 if (*op_string == ABSOLUTE_PREFIX)
8616 {
8617 ++op_string;
8618 if (is_space_char (*op_string))
8619 ++op_string;
40fb9820 8620 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8621 }
8622 goto do_memory_reference;
8623 }
43234a1e
L		 8624
8625 /* Handle vector operations. */
8626 if (*op_string == '{')
8627 {
8628 op_string = check_VecOperations (op_string, NULL);
8629 if (op_string == NULL)
8630 return 0;
8631 }
8632
24eab124
AM		 8633 if (*op_string)
8634 {
d0b47220 8635 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8636 return 0;
8637 }
40fb9820
L		 8638 temp = r->reg_type;
8639 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8640 i.types[this_operand] = operand_type_or (i.types[this_operand],
8641 temp);
7d5e4556 8642 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8643 i.op[this_operand].regs = r;
24eab124
AM		 8644 i.reg_operands++;
8645 }
af6bdddf
AM		 8646 else if (*op_string == REGISTER_PREFIX)
8647 {
8648 as_bad (_("bad register name `%s'"), op_string);
8649 return 0;
8650 }
24eab124 8651 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8652 {
24eab124 8653 ++op_string;
40fb9820 8654 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8655 {
d0b47220 8656 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8657 return 0;
8658 }
8659 if (!i386_immediate (op_string))
8660 return 0;
8661 }
43234a1e
L		 8662 else if (RC_SAE_immediate (operand_string))
8663 {
8664 /* If it is a RC or SAE immediate, do nothing. */
8665 ;
8666 }
24eab124
AM		 8667 else if (is_digit_char (*op_string)
8668 || is_identifier_char (*op_string)
e5cb08ac 8669 || *op_string == '(')
24eab124 8670 {
47926f60 8671 /* This is a memory reference of some sort. */
af6bdddf 8672 char *base_string;
252b5132 8673
47926f60 8674 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8675 char *displacement_string_start;
8676 char *displacement_string_end;
43234a1e 8677 char *vop_start;
252b5132 8678
24eab124 8679 do_memory_reference:
24eab124 8680 if ((i.mem_operands == 1
40fb9820 8681 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8682 || i.mem_operands == 2)
8683 {
8684 as_bad (_("too many memory references for `%s'"),
8685 current_templates->start->name);
8686 return 0;
8687 }
252b5132 8688
24eab124
AM		 8689 /* Check for base index form. We detect the base index form by
8690 looking for an ')' at the end of the operand, searching
8691 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8692 after the '('. */
af6bdddf 8693 base_string = op_string + strlen (op_string);
c3332e24 8694
43234a1e
L		 8695 /* Handle vector operations. */
8696 vop_start = strchr (op_string, '{');
8697 if (vop_start && vop_start < base_string)
8698 {
8699 if (check_VecOperations (vop_start, base_string) == NULL)
8700 return 0;
8701 base_string = vop_start;
8702 }
8703
af6bdddf
AM		 8704 --base_string;
8705 if (is_space_char (*base_string))
8706 --base_string;
252b5132 8707
47926f60 8708 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8709 displacement_string_start = op_string;
8710 displacement_string_end = base_string + 1;
252b5132 8711
24eab124
AM		 8712 if (*base_string == ')')
8713 {
af6bdddf 8714 char *temp_string;
24eab124
AM		 8715 unsigned int parens_balanced = 1;
8716 /* We've already checked that the number of left & right ()'s are
47926f60 8717 equal, so this loop will not be infinite. */
24eab124
AM		 8718 do
8719 {
8720 base_string--;
8721 if (*base_string == ')')
8722 parens_balanced++;
8723 if (*base_string == '(')
8724 parens_balanced--;
8725 }
8726 while (parens_balanced);
c3332e24 8727
af6bdddf 8728 temp_string = base_string;
c3332e24 8729
24eab124 8730 /* Skip past '(' and whitespace. */
252b5132
RH		 8731 ++base_string;
8732 if (is_space_char (*base_string))
24eab124 8733 ++base_string;
252b5132 8734
af6bdddf 8735 if (*base_string == ','
4eed87de
AM		 8736 || ((i.base_reg = parse_register (base_string, &end_op))
8737 != NULL))
252b5132 8738 {
af6bdddf 8739 displacement_string_end = temp_string;
252b5132 8740
40fb9820 8741 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8742
af6bdddf 8743 if (i.base_reg)
24eab124 8744 {
24eab124
AM		 8745 base_string = end_op;
8746 if (is_space_char (*base_string))
8747 ++base_string;
af6bdddf
AM		 8748 }
8749
8750 /* There may be an index reg or scale factor here. */
8751 if (*base_string == ',')
8752 {
8753 ++base_string;
8754 if (is_space_char (*base_string))
8755 ++base_string;
8756
4eed87de
AM		 8757 if ((i.index_reg = parse_register (base_string, &end_op))
8758 != NULL)
24eab124 8759 {
af6bdddf 8760 base_string = end_op;
24eab124
AM		 8761 if (is_space_char (*base_string))
8762 ++base_string;
af6bdddf
AM		 8763 if (*base_string == ',')
8764 {
8765 ++base_string;
8766 if (is_space_char (*base_string))
8767 ++base_string;
8768 }
e5cb08ac 8769 else if (*base_string != ')')
af6bdddf 8770 {
4eed87de
AM		 8771 as_bad (_("expecting `,' or `)' "
8772 "after index register in `%s'"),
af6bdddf
AM		 8773 operand_string);
8774 return 0;
8775 }
24eab124 8776 }
af6bdddf 8777 else if (*base_string == REGISTER_PREFIX)
24eab124 8778 {
f76bf5e0
L		 8779 end_op = strchr (base_string, ',');
8780 if (end_op)
8781 *end_op = '\0';
af6bdddf 8782 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8783 return 0;
8784 }
252b5132 8785
47926f60 8786 /* Check for scale factor. */
551c1ca1 8787 if (*base_string != ')')
af6bdddf 8788 {
551c1ca1
AM		 8789 char *end_scale = i386_scale (base_string);
8790
8791 if (!end_scale)
af6bdddf 8792 return 0;
24eab124 8793
551c1ca1 8794 base_string = end_scale;
af6bdddf
AM		 8795 if (is_space_char (*base_string))
8796 ++base_string;
8797 if (*base_string != ')')
8798 {
4eed87de
AM		 8799 as_bad (_("expecting `)' "
8800 "after scale factor in `%s'"),
af6bdddf
AM		 8801 operand_string);
8802 return 0;
8803 }
8804 }
8805 else if (!i.index_reg)
24eab124 8806 {
4eed87de
AM		 8807 as_bad (_("expecting index register or scale factor "
8808 "after `,'; got '%c'"),
af6bdddf 8809 *base_string);
24eab124
AM		 8810 return 0;
8811 }
8812 }
af6bdddf 8813 else if (*base_string != ')')
24eab124 8814 {
4eed87de
AM		 8815 as_bad (_("expecting `,' or `)' "
8816 "after base register in `%s'"),
af6bdddf 8817 operand_string);
24eab124
AM		 8818 return 0;
8819 }
c3332e24 8820 }
af6bdddf 8821 else if (*base_string == REGISTER_PREFIX)
c3332e24 8822 {
f76bf5e0
L		 8823 end_op = strchr (base_string, ',');
8824 if (end_op)
8825 *end_op = '\0';
af6bdddf 8826 as_bad (_("bad register name `%s'"), base_string);
24eab124 8827 return 0;
c3332e24 8828 }
24eab124
AM		 8829 }
8830
8831 /* If there's an expression beginning the operand, parse it,
8832 assuming displacement_string_start and
8833 displacement_string_end are meaningful. */
8834 if (displacement_string_start != displacement_string_end)
8835 {
8836 if (!i386_displacement (displacement_string_start,
8837 displacement_string_end))
8838 return 0;
8839 }
8840
8841 /* Special case for (%dx) while doing input/output op. */
8842 if (i.base_reg
0dfbf9d7
L		 8843 && operand_type_equal (&i.base_reg->reg_type,
8844 &reg16_inoutportreg)
24eab124
AM		 8845 && i.index_reg == 0
8846 && i.log2_scale_factor == 0
8847 && i.seg[i.mem_operands] == 0
40fb9820 8848 && !operand_type_check (i.types[this_operand], disp))
24eab124 8849 {
65da13b5 8850 i.types[this_operand] = inoutportreg;
24eab124
AM		 8851 return 1;
8852 }
8853
eecb386c
AM		 8854 if (i386_index_check (operand_string) == 0)
8855 return 0;
5c07affc 8856 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8857 i.mem_operands++;
8858 }
8859 else
ce8a8b2f
AM		 8860 {
8861 /* It's not a memory operand; argh! */
24eab124
AM		 8862 as_bad (_("invalid char %s beginning operand %d `%s'"),
8863 output_invalid (*op_string),
8864 this_operand + 1,
8865 op_string);
8866 return 0;
8867 }
47926f60 8868 return 1; /* Normal return. */
252b5132
RH		 8869}
8870\f
fa94de6b
RM		 8871/* Calculate the maximum variable size (i.e., excluding fr_fix)
8872 that an rs_machine_dependent frag may reach. */
8873
8874unsigned int
8875i386_frag_max_var (fragS *frag)
8876{
8877 /* The only relaxable frags are for jumps.
8878 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8879 gas_assert (frag->fr_type == rs_machine_dependent);
8880 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8881}
8882
ee7fcc42
AM		 8883/* md_estimate_size_before_relax()
8884
8885 Called just before relax() for rs_machine_dependent frags. The x86
8886 assembler uses these frags to handle variable size jump
8887 instructions.
8888
8889 Any symbol that is now undefined will not become defined.
8890 Return the correct fr_subtype in the frag.
8891 Return the initial "guess for variable size of frag" to caller.
8892 The guess is actually the growth beyond the fixed part. Whatever
8893 we do to grow the fixed or variable part contributes to our
8894 returned value. */
8895
252b5132 8896int
7016a5d5 8897md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8898{
252b5132 8899 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8900 check for un-relaxable symbols. On an ELF system, we can't relax
8901 an externally visible symbol, because it may be overridden by a
8902 shared library. */
8903 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8904#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8905 || (IS_ELF
31312f95 8906 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8907 || S_IS_WEAK (fragP->fr_symbol)
8908 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8909 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8910#endif
8911#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8912 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8913 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8914#endif
8915 )
252b5132 8916 {
b98ef147
AM		 8917 /* Symbol is undefined in this segment, or we need to keep a
8918 reloc so that weak symbols can be overridden. */
8919 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8920 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8921 unsigned char *opcode;
8922 int old_fr_fix;
f6af82bd 8923
ee7fcc42 8924 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8925 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8926 else if (size == 2)
f6af82bd
AM		 8927 reloc_type = BFD_RELOC_16_PCREL;
8928 else
8929 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8930
ee7fcc42
AM		 8931 old_fr_fix = fragP->fr_fix;
8932 opcode = (unsigned char *) fragP->fr_opcode;
8933
fddf5b5b 8934 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8935 {
fddf5b5b
AM		 8936 case UNCOND_JUMP:
8937 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8938 opcode[0] = 0xe9;
252b5132 8939 fragP->fr_fix += size;
062cd5e7
AS		 8940 fix_new (fragP, old_fr_fix, size,
8941 fragP->fr_symbol,
8942 fragP->fr_offset, 1,
8943 reloc_type);
252b5132
RH		 8944 break;
8945
fddf5b5b 8946 case COND_JUMP86:
412167cb
AM		 8947 if (size == 2
8948 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8949 {
8950 /* Negate the condition, and branch past an
8951 unconditional jump. */
8952 opcode[0] ^= 1;
8953 opcode[1] = 3;
8954 /* Insert an unconditional jump. */
8955 opcode[2] = 0xe9;
8956 /* We added two extra opcode bytes, and have a two byte
8957 offset. */
8958 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8959 fix_new (fragP, old_fr_fix + 2, 2,
8960 fragP->fr_symbol,
8961 fragP->fr_offset, 1,
8962 reloc_type);
fddf5b5b
AM		 8963 break;
8964 }
8965 /* Fall through. */
8966
8967 case COND_JUMP:
412167cb
AM		 8968 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8969 {
3e02c1cc
AM		 8970 fixS *fixP;
8971
412167cb 8972 fragP->fr_fix += 1;
3e02c1cc
AM		 8973 fixP = fix_new (fragP, old_fr_fix, 1,
8974 fragP->fr_symbol,
8975 fragP->fr_offset, 1,
8976 BFD_RELOC_8_PCREL);
8977 fixP->fx_signed = 1;
412167cb
AM		 8978 break;
8979 }
93c2a809 8980
24eab124 8981 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8982 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8983 opcode[1] = opcode[0] + 0x10;
f6af82bd 8984 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8985 /* We've added an opcode byte. */
8986 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8987 fix_new (fragP, old_fr_fix + 1, size,
8988 fragP->fr_symbol,
8989 fragP->fr_offset, 1,
8990 reloc_type);
252b5132 8991 break;
fddf5b5b
AM		 8992
8993 default:
8994 BAD_CASE (fragP->fr_subtype);
8995 break;
252b5132
RH		 8996 }
8997 frag_wane (fragP);
ee7fcc42 8998 return fragP->fr_fix - old_fr_fix;
252b5132 8999 }
93c2a809 9000
93c2a809
AM		 9001 /* Guess size depending on current relax state. Initially the relax
9002 state will correspond to a short jump and we return 1, because
9003 the variable part of the frag (the branch offset) is one byte
9004 long. However, we can relax a section more than once and in that
9005 case we must either set fr_subtype back to the unrelaxed state,
9006 or return the value for the appropriate branch. */
9007 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9008}
9009
47926f60
KH		 9010/* Called after relax() is finished.
9011
9012 In: Address of frag.
9013 fr_type == rs_machine_dependent.
9014 fr_subtype is what the address relaxed to.
9015
9016 Out: Any fixSs and constants are set up.
9017 Caller will turn frag into a ".space 0". */
9018
252b5132 9019void
7016a5d5
TG		 9020md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9021 fragS *fragP)
252b5132 9022{
29b0f896 9023 unsigned char *opcode;
252b5132 9024 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9025 offsetT target_address;
9026 offsetT opcode_address;
252b5132 9027 unsigned int extension = 0;
847f7ad4 9028 offsetT displacement_from_opcode_start;
252b5132
RH		 9029
9030 opcode = (unsigned char *) fragP->fr_opcode;
9031
47926f60 9032 /* Address we want to reach in file space. */
252b5132 9033 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9034
47926f60 9035 /* Address opcode resides at in file space. */
252b5132
RH		 9036 opcode_address = fragP->fr_address + fragP->fr_fix;
9037
47926f60 9038 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9039 displacement_from_opcode_start = target_address - opcode_address;
9040
fddf5b5b 9041 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9042 {
47926f60
KH		 9043 /* Don't have to change opcode. */
9044 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9045 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9046 }
9047 else
9048 {
9049 if (no_cond_jump_promotion
9050 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9051 as_warn_where (fragP->fr_file, fragP->fr_line,
9052 _("long jump required"));
252b5132 9053
fddf5b5b
AM		 9054 switch (fragP->fr_subtype)
9055 {
9056 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9057 extension = 4; /* 1 opcode + 4 displacement */
9058 opcode[0] = 0xe9;
9059 where_to_put_displacement = &opcode[1];
9060 break;
252b5132 9061
fddf5b5b
AM		 9062 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9063 extension = 2; /* 1 opcode + 2 displacement */
9064 opcode[0] = 0xe9;
9065 where_to_put_displacement = &opcode[1];
9066 break;
252b5132 9067
fddf5b5b
AM		 9068 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9069 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9070 extension = 5; /* 2 opcode + 4 displacement */
9071 opcode[1] = opcode[0] + 0x10;
9072 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9073 where_to_put_displacement = &opcode[2];
9074 break;
252b5132 9075
fddf5b5b
AM		 9076 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9077 extension = 3; /* 2 opcode + 2 displacement */
9078 opcode[1] = opcode[0] + 0x10;
9079 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9080 where_to_put_displacement = &opcode[2];
9081 break;
252b5132 9082
fddf5b5b
AM		 9083 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9084 extension = 4;
9085 opcode[0] ^= 1;
9086 opcode[1] = 3;
9087 opcode[2] = 0xe9;
9088 where_to_put_displacement = &opcode[3];
9089 break;
9090
9091 default:
9092 BAD_CASE (fragP->fr_subtype);
9093 break;
9094 }
252b5132 9095 }
fddf5b5b 9096
7b81dfbb
AJ		 9097 /* If size if less then four we are sure that the operand fits,
9098 but if it's 4, then it could be that the displacement is larger
9099 then -/+ 2GB. */
9100 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9101 && object_64bit
9102 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9103 + ((addressT) 1 << 31))
9104 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9105 {
9106 as_bad_where (fragP->fr_file, fragP->fr_line,
9107 _("jump target out of range"));
9108 /* Make us emit 0. */
9109 displacement_from_opcode_start = extension;
9110 }
47926f60 9111 /* Now put displacement after opcode. */
252b5132
RH		 9112 md_number_to_chars ((char *) where_to_put_displacement,
9113 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9114 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9115 fragP->fr_fix += extension;
9116}
9117\f
7016a5d5 9118/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9119 by our caller that we have all the info we need to fix it up.
9120
7016a5d5
TG		 9121 Parameter valP is the pointer to the value of the bits.
9122
252b5132
RH		 9123 On the 386, immediates, displacements, and data pointers are all in
9124 the same (little-endian) format, so we don't need to care about which
9125 we are handling. */
9126
94f592af 9127void
7016a5d5 9128md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9129{
94f592af 9130 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9131 valueT value = *valP;
252b5132 9132
f86103b7 9133#if !defined (TE_Mach)
93382f6d
AM		 9134 if (fixP->fx_pcrel)
9135 {
9136 switch (fixP->fx_r_type)
9137 {
5865bb77
ILT		 9138 default:
9139 break;
9140
d6ab8113
JB		 9141 case BFD_RELOC_64:
9142 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9143 break;
93382f6d 9144 case BFD_RELOC_32:
ae8887b5 9145 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9146 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9147 break;
9148 case BFD_RELOC_16:
9149 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9150 break;
9151 case BFD_RELOC_8:
9152 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9153 break;
9154 }
9155 }
252b5132 9156
a161fe53 9157 if (fixP->fx_addsy != NULL
31312f95 9158 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9159 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9160 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9161 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9162 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9163 && !use_rela_relocations)
252b5132 9164 {
31312f95
AM		 9165 /* This is a hack. There should be a better way to handle this.
9166 This covers for the fact that bfd_install_relocation will
9167 subtract the current location (for partial_inplace, PC relative
9168 relocations); see more below. */
252b5132 9169#ifndef OBJ_AOUT
718ddfc0 9170 if (IS_ELF
252b5132
RH		 9171#ifdef TE_PE
9172 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9173#endif
9174 )
9175 value += fixP->fx_where + fixP->fx_frag->fr_address;
9176#endif
9177#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9178 if (IS_ELF)
252b5132 9179 {
6539b54b 9180 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9181
6539b54b 9182 if ((sym_seg == seg
2f66722d 9183 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9184 && sym_seg != absolute_section))
af65af87 9185 && !generic_force_reloc (fixP))
2f66722d
AM		 9186 {
9187 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9188 bfd_install_relocation subtracts them out again. I think
9189 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9190 it. FIXME. */
9191 value += fixP->fx_where + fixP->fx_frag->fr_address;
9192 }
252b5132
RH		 9193 }
9194#endif
9195#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9196 /* For some reason, the PE format does not store a
9197 section address offset for a PC relative symbol. */
9198 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9199 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9200 value += md_pcrel_from (fixP);
9201#endif
9202 }
fbeb56a4 9203#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9204 if (fixP->fx_addsy != NULL
9205 && S_IS_WEAK (fixP->fx_addsy)
9206 /* PR 16858: Do not modify weak function references. */
9207 && ! fixP->fx_pcrel)
fbeb56a4 9208 {
296a8689
NC		 9209#if !defined (TE_PEP)
9210 /* For x86 PE weak function symbols are neither PC-relative
9211 nor do they set S_IS_FUNCTION. So the only reliable way
9212 to detect them is to check the flags of their containing
9213 section. */
9214 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9215 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9216 ;
9217 else
9218#endif
fbeb56a4
DK		 9219 value -= S_GET_VALUE (fixP->fx_addsy);
9220 }
9221#endif
252b5132
RH		 9222
9223 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9224 and we must not disappoint it. */
252b5132 9225#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9226 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9227 switch (fixP->fx_r_type)
9228 {
9229 case BFD_RELOC_386_PLT32:
3e73aa7c 9230 case BFD_RELOC_X86_64_PLT32:
c3320543 9231 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9232 /* Make the jump instruction point to the address of the operand. At
9233 runtime we merely add the offset to the actual PLT entry. */
9234 value = -4;
9235 break;
31312f95 9236
13ae64f3
JJ		 9237 case BFD_RELOC_386_TLS_GD:
9238 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9239 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9240 case BFD_RELOC_386_TLS_IE:
9241 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9242 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9243 case BFD_RELOC_X86_64_TLSGD:
9244 case BFD_RELOC_X86_64_TLSLD:
9245 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9246 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9247 value = 0; /* Fully resolved at runtime. No addend. */
9248 /* Fallthrough */
9249 case BFD_RELOC_386_TLS_LE:
9250 case BFD_RELOC_386_TLS_LDO_32:
9251 case BFD_RELOC_386_TLS_LE_32:
9252 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9253 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9254 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9255 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9256 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9257 break;
9258
67a4f2b7
AO		 9259 case BFD_RELOC_386_TLS_DESC_CALL:
9260 case BFD_RELOC_X86_64_TLSDESC_CALL:
9261 value = 0; /* Fully resolved at runtime. No addend. */
9262 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9263 fixP->fx_done = 0;
9264 return;
9265
00f7efb6
JJ		 9266 case BFD_RELOC_386_GOT32:
9267 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9268 value = 0; /* Fully resolved at runtime. No addend. */
9269 break;
47926f60
KH		 9270
9271 case BFD_RELOC_VTABLE_INHERIT:
9272 case BFD_RELOC_VTABLE_ENTRY:
9273 fixP->fx_done = 0;
94f592af 9274 return;
47926f60
KH		 9275
9276 default:
9277 break;
9278 }
9279#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9280 *valP = value;
f86103b7 9281#endif /* !defined (TE_Mach) */
3e73aa7c 9282
3e73aa7c 9283 /* Are we finished with this relocation now? */
c6682705 9284 if (fixP->fx_addsy == NULL)
3e73aa7c 9285 fixP->fx_done = 1;
fbeb56a4
DK		 9286#if defined (OBJ_COFF) && defined (TE_PE)
9287 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9288 {
9289 fixP->fx_done = 0;
9290 /* Remember value for tc_gen_reloc. */
9291 fixP->fx_addnumber = value;
9292 /* Clear out the frag for now. */
9293 value = 0;
9294 }
9295#endif
3e73aa7c
JH		 9296 else if (use_rela_relocations)
9297 {
9298 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9299 /* Remember value for tc_gen_reloc. */
9300 fixP->fx_addnumber = value;
3e73aa7c
JH		 9301 value = 0;
9302 }
f86103b7 9303
94f592af 9304 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9305}
252b5132 9306\f
252b5132 9307char *
499ac353 9308md_atof (int type, char *litP, int *sizeP)
252b5132 9309{
499ac353
NC		 9310 /* This outputs the LITTLENUMs in REVERSE order;
9311 in accord with the bigendian 386. */
9312 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9313}
9314\f
2d545b82 9315static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9316
252b5132 9317static char *
e3bb37b5 9318output_invalid (int c)
252b5132 9319{
3882b010 9320 if (ISPRINT (c))
f9f21a03
L		 9321 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9322 "'%c'", c);
252b5132 9323 else
f9f21a03 9324 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9325 "(0x%x)", (unsigned char) c);
252b5132
RH		 9326 return output_invalid_buf;
9327}
9328
af6bdddf 9329/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9330
9331static const reg_entry *
4d1bb795 9332parse_real_register (char *reg_string, char **end_op)
252b5132 9333{
af6bdddf
AM		 9334 char *s = reg_string;
9335 char *p;
252b5132
RH		 9336 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9337 const reg_entry *r;
9338
9339 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9340 if (*s == REGISTER_PREFIX)
9341 ++s;
9342
9343 if (is_space_char (*s))
9344 ++s;
9345
9346 p = reg_name_given;
af6bdddf 9347 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9348 {
9349 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9350 return (const reg_entry *) NULL;
9351 s++;
252b5132
RH		 9352 }
9353
6588847e
DN		 9354 /* For naked regs, make sure that we are not dealing with an identifier.
9355 This prevents confusing an identifier like `eax_var' with register
9356 `eax'. */
9357 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9358 return (const reg_entry *) NULL;
9359
af6bdddf 9360 *end_op = s;
252b5132
RH		 9361
9362 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9363
5f47d35b 9364 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9365 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9366 {
5f47d35b
AM		 9367 if (is_space_char (*s))
9368 ++s;
9369 if (*s == '(')
9370 {
af6bdddf 9371 ++s;
5f47d35b
AM		 9372 if (is_space_char (*s))
9373 ++s;
9374 if (*s >= '0' && *s <= '7')
9375 {
db557034 9376 int fpr = *s - '0';
af6bdddf 9377 ++s;
5f47d35b
AM		 9378 if (is_space_char (*s))
9379 ++s;
9380 if (*s == ')')
9381 {
9382 *end_op = s + 1;
1e9cc1c2 9383 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9384 know (r);
9385 return r + fpr;
5f47d35b 9386 }
5f47d35b 9387 }
47926f60 9388 /* We have "%st(" then garbage. */
5f47d35b
AM		 9389 return (const reg_entry *) NULL;
9390 }
9391 }
9392
a60de03c
JB		 9393 if (r == NULL || allow_pseudo_reg)
9394 return r;
9395
0dfbf9d7 9396 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9397 return (const reg_entry *) NULL;
9398
192dc9c6
JB		 9399 if ((r->reg_type.bitfield.reg32
9400 || r->reg_type.bitfield.sreg3
9401 || r->reg_type.bitfield.control
9402 || r->reg_type.bitfield.debug
9403 || r->reg_type.bitfield.test)
9404 && !cpu_arch_flags.bitfield.cpui386)
9405 return (const reg_entry *) NULL;
9406
309d3373
JB		 9407 if (r->reg_type.bitfield.floatreg
9408 && !cpu_arch_flags.bitfield.cpu8087
9409 && !cpu_arch_flags.bitfield.cpu287
9410 && !cpu_arch_flags.bitfield.cpu387)
9411 return (const reg_entry *) NULL;
9412
192dc9c6
JB		 9413 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9414 return (const reg_entry *) NULL;
9415
9416 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9417 return (const reg_entry *) NULL;
9418
40f12533
L		 9419 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9420 return (const reg_entry *) NULL;
9421
43234a1e
L		 9422 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9423 && !cpu_arch_flags.bitfield.cpuavx512f)
9424 return (const reg_entry *) NULL;
9425
db51cc60 9426 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9427 if (!allow_index_reg
db51cc60
L		 9428 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9429 return (const reg_entry *) NULL;
9430
43234a1e
L		 9431 /* Upper 16 vector register is only available with VREX in 64bit
9432 mode. */
9433 if ((r->reg_flags & RegVRex))
9434 {
9435 if (!cpu_arch_flags.bitfield.cpuvrex
9436 || flag_code != CODE_64BIT)
9437 return (const reg_entry *) NULL;
9438
9439 i.need_vrex = 1;
9440 }
9441
a60de03c
JB		 9442 if (((r->reg_flags & (RegRex64 | RegRex))
9443 || r->reg_type.bitfield.reg64)
40fb9820 9444 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9445 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9446 && flag_code != CODE_64BIT)
20f0a1fc 9447 return (const reg_entry *) NULL;
1ae00879 9448
b7240065
JB		 9449 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9450 return (const reg_entry *) NULL;
9451
252b5132
RH		 9452 return r;
9453}
4d1bb795
JB		 9454
9455/* REG_STRING starts *before* REGISTER_PREFIX. */
9456
9457static const reg_entry *
9458parse_register (char *reg_string, char **end_op)
9459{
9460 const reg_entry *r;
9461
9462 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9463 r = parse_real_register (reg_string, end_op);
9464 else
9465 r = NULL;
9466 if (!r)
9467 {
9468 char *save = input_line_pointer;
9469 char c;
9470 symbolS *symbolP;
9471
9472 input_line_pointer = reg_string;
9473 c = get_symbol_end ();
9474 symbolP = symbol_find (reg_string);
9475 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9476 {
9477 const expressionS *e = symbol_get_value_expression (symbolP);
9478
0398aac5 9479 know (e->X_op == O_register);
4eed87de 9480 know (e->X_add_number >= 0
c3fe08fa 9481 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9482 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9483 if ((r->reg_flags & RegVRex))
9484 i.need_vrex = 1;
4d1bb795
JB		 9485 *end_op = input_line_pointer;
9486 }
9487 *input_line_pointer = c;
9488 input_line_pointer = save;
9489 }
9490 return r;
9491}
9492
9493int
9494i386_parse_name (char *name, expressionS *e, char *nextcharP)
9495{
9496 const reg_entry *r;
9497 char *end = input_line_pointer;
9498
9499 *end = *nextcharP;
9500 r = parse_register (name, &input_line_pointer);
9501 if (r && end <= input_line_pointer)
9502 {
9503 *nextcharP = *input_line_pointer;
9504 *input_line_pointer = 0;
9505 e->X_op = O_register;
9506 e->X_add_number = r - i386_regtab;
9507 return 1;
9508 }
9509 input_line_pointer = end;
9510 *end = 0;
ee86248c 9511 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9512}
9513
9514void
9515md_operand (expressionS *e)
9516{
ee86248c
JB		 9517 char *end;
9518 const reg_entry *r;
4d1bb795 9519
ee86248c
JB		 9520 switch (*input_line_pointer)
9521 {
9522 case REGISTER_PREFIX:
9523 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9524 if (r)
9525 {
9526 e->X_op = O_register;
9527 e->X_add_number = r - i386_regtab;
9528 input_line_pointer = end;
9529 }
ee86248c
JB		 9530 break;
9531
9532 case '[':
9c2799c2 9533 gas_assert (intel_syntax);
ee86248c
JB		 9534 end = input_line_pointer++;
9535 expression (e);
9536 if (*input_line_pointer == ']')
9537 {
9538 ++input_line_pointer;
9539 e->X_op_symbol = make_expr_symbol (e);
9540 e->X_add_symbol = NULL;
9541 e->X_add_number = 0;
9542 e->X_op = O_index;
9543 }
9544 else
9545 {
9546 e->X_op = O_absent;
9547 input_line_pointer = end;
9548 }
9549 break;
4d1bb795
JB		 9550 }
9551}
9552
252b5132 9553\f
4cc782b5 9554#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9555const char *md_shortopts = "kVQ:sqn";
252b5132 9556#else
12b55ccc 9557const char *md_shortopts = "qn";
252b5132 9558#endif
6e0b89ee 9559
3e73aa7c 9560#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9561#define OPTION_64 (OPTION_MD_BASE + 1)
9562#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9563#define OPTION_MARCH (OPTION_MD_BASE + 3)
9564#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9565#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9566#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9567#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9568#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9569#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9570#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9571#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9572#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9573#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9574#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9575#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9576#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9577#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9578#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9579#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9580#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
b3b91714 9581
99ad8390
NC		 9582struct option md_longopts[] =
9583{
3e73aa7c 9584 {"32", no_argument, NULL, OPTION_32},
321098a5 9585#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9586 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9587 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9588#endif
9589#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9590 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9591#endif
b3b91714 9592 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9593 {"march", required_argument, NULL, OPTION_MARCH},
9594 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9595 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9596 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9597 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9598 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9599 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9600 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9601 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9602 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9603 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9604 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9605 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9606 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9607# if defined (TE_PE) || defined (TE_PEP)
9608 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9609#endif
a5094208 9610 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9611 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
252b5132
RH		 9612 {NULL, no_argument, NULL, 0}
9613};
9614size_t md_longopts_size = sizeof (md_longopts);
9615
9616int
9103f4f4 9617md_parse_option (int c, char *arg)
252b5132 9618{
91d6fa6a 9619 unsigned int j;
6305a203 9620 char *arch, *next;
9103f4f4 9621
252b5132
RH		 9622 switch (c)
9623 {
12b55ccc
L		 9624 case 'n':
9625 optimize_align_code = 0;
9626 break;
9627
a38cf1db
AM		 9628 case 'q':
9629 quiet_warnings = 1;
252b5132
RH		 9630 break;
9631
9632#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9633 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9634 should be emitted or not. FIXME: Not implemented. */
9635 case 'Q':
252b5132
RH		 9636 break;
9637
9638 /* -V: SVR4 argument to print version ID. */
9639 case 'V':
9640 print_version_id ();
9641 break;
9642
a38cf1db
AM		 9643 /* -k: Ignore for FreeBSD compatibility. */
9644 case 'k':
252b5132 9645 break;
4cc782b5
ILT		 9646
9647 case 's':
9648 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9649 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9650 break;
99ad8390 9651#endif
321098a5 9652#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9653 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9654 case OPTION_64:
9655 {
9656 const char **list, **l;
9657
3e73aa7c
JH		 9658 list = bfd_target_list ();
9659 for (l = list; *l != NULL; l++)
8620418b 9660 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9661 || strcmp (*l, "coff-x86-64") == 0
9662 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9663 || strcmp (*l, "pei-x86-64") == 0
9664 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9665 {
9666 default_arch = "x86_64";
9667 break;
9668 }
3e73aa7c 9669 if (*l == NULL)
2b5d6a91 9670 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9671 free (list);
9672 }
9673 break;
9674#endif
252b5132 9675
351f65ca 9676#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9677 case OPTION_X32:
351f65ca
L		 9678 if (IS_ELF)
9679 {
9680 const char **list, **l;
9681
9682 list = bfd_target_list ();
9683 for (l = list; *l != NULL; l++)
9684 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9685 {
9686 default_arch = "x86_64:32";
9687 break;
9688 }
9689 if (*l == NULL)
2b5d6a91 9690 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9691 free (list);
9692 }
9693 else
9694 as_fatal (_("32bit x86_64 is only supported for ELF"));
9695 break;
9696#endif
9697
6e0b89ee
AM		 9698 case OPTION_32:
9699 default_arch = "i386";
9700 break;
9701
b3b91714
AM		 9702 case OPTION_DIVIDE:
9703#ifdef SVR4_COMMENT_CHARS
9704 {
9705 char *n, *t;
9706 const char *s;
9707
9708 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9709 t = n;
9710 for (s = i386_comment_chars; *s != '\0'; s++)
9711 if (*s != '/')
9712 *t++ = *s;
9713 *t = '\0';
9714 i386_comment_chars = n;
9715 }
9716#endif
9717 break;
9718
9103f4f4 9719 case OPTION_MARCH:
6305a203
L		 9720 arch = xstrdup (arg);
9721 do
9103f4f4 9722 {
6305a203 9723 if (*arch == '.')
2b5d6a91 9724 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9725 next = strchr (arch, '+');
9726 if (next)
9727 *next++ = '\0';
91d6fa6a 9728 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9729 {
91d6fa6a 9730 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9731 {
6305a203 9732 /* Processor. */
1ded5609
JB		 9733 if (! cpu_arch[j].flags.bitfield.cpui386)
9734 continue;
9735
91d6fa6a 9736 cpu_arch_name = cpu_arch[j].name;
6305a203 9737 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9738 cpu_arch_flags = cpu_arch[j].flags;
9739 cpu_arch_isa = cpu_arch[j].type;
9740 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9741 if (!cpu_arch_tune_set)
9742 {
9743 cpu_arch_tune = cpu_arch_isa;
9744 cpu_arch_tune_flags = cpu_arch_isa_flags;
9745 }
9746 break;
9747 }
91d6fa6a
NC		 9748 else if (*cpu_arch [j].name == '.'
9749 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9750 {
9751 /* ISA entension. */
9752 i386_cpu_flags flags;
309d3373 9753
49021df2 9754 if (!cpu_arch[j].negated)
309d3373 9755 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9756 cpu_arch[j].flags);
309d3373
JB		 9757 else
9758 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9759 cpu_arch[j].flags);
0dfbf9d7 9760 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9761 {
9762 if (cpu_sub_arch_name)
9763 {
9764 char *name = cpu_sub_arch_name;
9765 cpu_sub_arch_name = concat (name,
91d6fa6a 9766 cpu_arch[j].name,
1bf57e9f 9767 (const char *) NULL);
6305a203
L		 9768 free (name);
9769 }
9770 else
91d6fa6a 9771 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9772 cpu_arch_flags = flags;
a586129e 9773 cpu_arch_isa_flags = flags;
6305a203
L		 9774 }
9775 break;
ccc9c027 9776 }
9103f4f4 9777 }
6305a203 9778
91d6fa6a 9779 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9780 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9781
9782 arch = next;
9103f4f4 9783 }
6305a203 9784 while (next != NULL );
9103f4f4
L		 9785 break;
9786
9787 case OPTION_MTUNE:
9788 if (*arg == '.')
2b5d6a91 9789 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9790 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9791 {
91d6fa6a 9792 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9793 {
ccc9c027 9794 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9795 cpu_arch_tune = cpu_arch [j].type;
9796 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9797 break;
9798 }
9799 }
91d6fa6a 9800 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9801 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9802 break;
9803
1efbbeb4
L		 9804 case OPTION_MMNEMONIC:
9805 if (strcasecmp (arg, "att") == 0)
9806 intel_mnemonic = 0;
9807 else if (strcasecmp (arg, "intel") == 0)
9808 intel_mnemonic = 1;
9809 else
2b5d6a91 9810 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9811 break;
9812
9813 case OPTION_MSYNTAX:
9814 if (strcasecmp (arg, "att") == 0)
9815 intel_syntax = 0;
9816 else if (strcasecmp (arg, "intel") == 0)
9817 intel_syntax = 1;
9818 else
2b5d6a91 9819 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9820 break;
9821
9822 case OPTION_MINDEX_REG:
9823 allow_index_reg = 1;
9824 break;
9825
9826 case OPTION_MNAKED_REG:
9827 allow_naked_reg = 1;
9828 break;
9829
9830 case OPTION_MOLD_GCC:
9831 old_gcc = 1;
1efbbeb4
L		 9832 break;
9833
c0f3af97
L		 9834 case OPTION_MSSE2AVX:
9835 sse2avx = 1;
9836 break;
9837
daf50ae7
L		 9838 case OPTION_MSSE_CHECK:
9839 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9840 sse_check = check_error;
daf50ae7 9841 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9842 sse_check = check_warning;
daf50ae7 9843 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9844 sse_check = check_none;
daf50ae7 9845 else
2b5d6a91 9846 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9847 break;
9848
7bab8ab5
JB		 9849 case OPTION_MOPERAND_CHECK:
9850 if (strcasecmp (arg, "error") == 0)
9851 operand_check = check_error;
9852 else if (strcasecmp (arg, "warning") == 0)
9853 operand_check = check_warning;
9854 else if (strcasecmp (arg, "none") == 0)
9855 operand_check = check_none;
9856 else
9857 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9858 break;
9859
539f890d
L		 9860 case OPTION_MAVXSCALAR:
9861 if (strcasecmp (arg, "128") == 0)
9862 avxscalar = vex128;
9863 else if (strcasecmp (arg, "256") == 0)
9864 avxscalar = vex256;
9865 else
2b5d6a91 9866 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9867 break;
9868
7e8b059b
L		 9869 case OPTION_MADD_BND_PREFIX:
9870 add_bnd_prefix = 1;
9871 break;
9872
43234a1e
L		 9873 case OPTION_MEVEXLIG:
9874 if (strcmp (arg, "128") == 0)
9875 evexlig = evexl128;
9876 else if (strcmp (arg, "256") == 0)
9877 evexlig = evexl256;
9878 else if (strcmp (arg, "512") == 0)
9879 evexlig = evexl512;
9880 else
9881 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9882 break;
9883
d3d3c6db
IT		 9884 case OPTION_MEVEXRCIG:
9885 if (strcmp (arg, "rne") == 0)
9886 evexrcig = rne;
9887 else if (strcmp (arg, "rd") == 0)
9888 evexrcig = rd;
9889 else if (strcmp (arg, "ru") == 0)
9890 evexrcig = ru;
9891 else if (strcmp (arg, "rz") == 0)
9892 evexrcig = rz;
9893 else
9894 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9895 break;
9896
43234a1e
L		 9897 case OPTION_MEVEXWIG:
9898 if (strcmp (arg, "0") == 0)
9899 evexwig = evexw0;
9900 else if (strcmp (arg, "1") == 0)
9901 evexwig = evexw1;
9902 else
9903 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9904 break;
9905
167ad85b
TG		 9906# if defined (TE_PE) || defined (TE_PEP)
9907 case OPTION_MBIG_OBJ:
9908 use_big_obj = 1;
9909 break;
9910#endif
9911
a5094208 9912 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9913 if (strcasecmp (arg, "yes") == 0)
9914 omit_lock_prefix = 1;
9915 else if (strcasecmp (arg, "no") == 0)
9916 omit_lock_prefix = 0;
9917 else
9918 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9919 break;
9920
252b5132
RH		 9921 default:
9922 return 0;
9923 }
9924 return 1;
9925}
9926
8a2c8fef
L		 9927#define MESSAGE_TEMPLATE \
9928" "
9929
9930static void
1ded5609 9931show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9932{
9933 static char message[] = MESSAGE_TEMPLATE;
9934 char *start = message + 27;
9935 char *p;
9936 int size = sizeof (MESSAGE_TEMPLATE);
9937 int left;
9938 const char *name;
9939 int len;
9940 unsigned int j;
9941
9942 p = start;
9943 left = size - (start - message);
9944 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9945 {
9946 /* Should it be skipped? */
9947 if (cpu_arch [j].skip)
9948 continue;
9949
9950 name = cpu_arch [j].name;
9951 len = cpu_arch [j].len;
9952 if (*name == '.')
9953 {
9954 /* It is an extension. Skip if we aren't asked to show it. */
9955 if (ext)
9956 {
9957 name++;
9958 len--;
9959 }
9960 else
9961 continue;
9962 }
9963 else if (ext)
9964 {
9965 /* It is an processor. Skip if we show only extension. */
9966 continue;
9967 }
1ded5609
JB		 9968 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9969 {
9970 /* It is an impossible processor - skip. */
9971 continue;
9972 }
8a2c8fef
L		 9973
9974 /* Reserve 2 spaces for ", " or ",\0" */
9975 left -= len + 2;
9976
9977 /* Check if there is any room. */
9978 if (left >= 0)
9979 {
9980 if (p != start)
9981 {
9982 *p++ = ',';
9983 *p++ = ' ';
9984 }
9985 p = mempcpy (p, name, len);
9986 }
9987 else
9988 {
9989 /* Output the current message now and start a new one. */
9990 *p++ = ',';
9991 *p = '\0';
9992 fprintf (stream, "%s\n", message);
9993 p = start;
9994 left = size - (start - message) - len - 2;
8d63c93e 9995
8a2c8fef
L		 9996 gas_assert (left >= 0);
9997
9998 p = mempcpy (p, name, len);
9999 }
10000 }
10001
10002 *p = '\0';
10003 fprintf (stream, "%s\n", message);
10004}
10005
252b5132 10006void
8a2c8fef 10007md_show_usage (FILE *stream)
252b5132 10008{
4cc782b5
ILT		 10009#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10010 fprintf (stream, _("\
a38cf1db
AM		 10011 -Q ignored\n\
10012 -V print assembler version number\n\
b3b91714
AM		 10013 -k ignored\n"));
10014#endif
10015 fprintf (stream, _("\
12b55ccc 10016 -n Do not optimize code alignment\n\
b3b91714
AM		 10017 -q quieten some warnings\n"));
10018#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10019 fprintf (stream, _("\
a38cf1db 10020 -s ignored\n"));
b3b91714 10021#endif
321098a5
L		 10022#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10023 || defined (TE_PE) || defined (TE_PEP))
751d281c 10024 fprintf (stream, _("\
570561f7 10025 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10026#endif
b3b91714
AM		 10027#ifdef SVR4_COMMENT_CHARS
10028 fprintf (stream, _("\
10029 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10030#else
10031 fprintf (stream, _("\
b3b91714 10032 --divide ignored\n"));
4cc782b5 10033#endif
9103f4f4 10034 fprintf (stream, _("\
6305a203 10035 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10036 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10037 show_arch (stream, 0, 1);
8a2c8fef
L		 10038 fprintf (stream, _("\
10039 EXTENSION is combination of:\n"));
1ded5609 10040 show_arch (stream, 1, 0);
6305a203 10041 fprintf (stream, _("\
8a2c8fef 10042 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10043 show_arch (stream, 0, 0);
ba104c83 10044 fprintf (stream, _("\
c0f3af97
L		 10045 -msse2avx encode SSE instructions with VEX prefix\n"));
10046 fprintf (stream, _("\
daf50ae7
L		 10047 -msse-check=[none|error|warning]\n\
10048 check SSE instructions\n"));
10049 fprintf (stream, _("\
7bab8ab5
JB		 10050 -moperand-check=[none|error|warning]\n\
10051 check operand combinations for validity\n"));
10052 fprintf (stream, _("\
539f890d
L		 10053 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10054 length\n"));
10055 fprintf (stream, _("\
43234a1e
L		 10056 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10057 length\n"));
10058 fprintf (stream, _("\
10059 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10060 for EVEX.W bit ignored instructions\n"));
10061 fprintf (stream, _("\
d3d3c6db
IT		 10062 -mevexrcig=[rne|rd|ru|rz]\n\
10063 encode EVEX instructions with specific EVEX.RC value\n\
10064 for SAE-only ignored instructions\n"));
10065 fprintf (stream, _("\
ba104c83
L		 10066 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10067 fprintf (stream, _("\
10068 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10069 fprintf (stream, _("\
10070 -mindex-reg support pseudo index registers\n"));
10071 fprintf (stream, _("\
10072 -mnaked-reg don't require `%%' prefix for registers\n"));
10073 fprintf (stream, _("\
10074 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10075 fprintf (stream, _("\
10076 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 10077# if defined (TE_PE) || defined (TE_PEP)
10078 fprintf (stream, _("\
10079 -mbig-obj generate big object files\n"));
10080#endif
d022bddd
IT		 10081 fprintf (stream, _("\
10082 -momit-lock-prefix=[no|yes]\n\
10083 strip all lock prefixes\n"));
252b5132
RH		 10084}
10085
3e73aa7c 10086#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10087 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10088 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10089
10090/* Pick the target format to use. */
10091
47926f60 10092const char *
e3bb37b5 10093i386_target_format (void)
252b5132 10094{
351f65ca
L		 10095 if (!strncmp (default_arch, "x86_64", 6))
10096 {
10097 update_code_flag (CODE_64BIT, 1);
10098 if (default_arch[6] == '\0')
7f56bc95 10099 x86_elf_abi = X86_64_ABI;
351f65ca 10100 else
7f56bc95 10101 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10102 }
3e73aa7c 10103 else if (!strcmp (default_arch, "i386"))
78f12dd3 10104 update_code_flag (CODE_32BIT, 1);
3e73aa7c 10105 else
2b5d6a91 10106 as_fatal (_("unknown architecture"));
89507696
JB		 10107
10108 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10109 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10110 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10111 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10112
252b5132
RH		 10113 switch (OUTPUT_FLAVOR)
10114 {
9384f2ff 10115#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10116 case bfd_target_aout_flavour:
47926f60 10117 return AOUT_TARGET_FORMAT;
4c63da97 10118#endif
9384f2ff
AM		 10119#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10120# if defined (TE_PE) || defined (TE_PEP)
10121 case bfd_target_coff_flavour:
167ad85b
TG		 10122 if (flag_code == CODE_64BIT)
10123 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10124 else
10125 return "pe-i386";
9384f2ff 10126# elif defined (TE_GO32)
0561d57c
JK		 10127 case bfd_target_coff_flavour:
10128 return "coff-go32";
9384f2ff 10129# else
252b5132
RH		 10130 case bfd_target_coff_flavour:
10131 return "coff-i386";
9384f2ff 10132# endif
4c63da97 10133#endif
3e73aa7c 10134#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10135 case bfd_target_elf_flavour:
3e73aa7c 10136 {
351f65ca
L		 10137 const char *format;
10138
10139 switch (x86_elf_abi)
4fa24527 10140 {
351f65ca
L		 10141 default:
10142 format = ELF_TARGET_FORMAT;
10143 break;
7f56bc95 10144 case X86_64_ABI:
351f65ca 10145 use_rela_relocations = 1;
4fa24527 10146 object_64bit = 1;
351f65ca
L		 10147 format = ELF_TARGET_FORMAT64;
10148 break;
7f56bc95 10149 case X86_64_X32_ABI:
4fa24527 10150 use_rela_relocations = 1;
351f65ca 10151 object_64bit = 1;
862be3fb 10152 disallow_64bit_reloc = 1;
351f65ca
L		 10153 format = ELF_TARGET_FORMAT32;
10154 break;
4fa24527 10155 }
3632d14b 10156 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10157 {
7f56bc95 10158 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10159 as_fatal (_("Intel L1OM is 64bit only"));
10160 return ELF_TARGET_L1OM_FORMAT;
10161 }
7a9068fe
L		 10162 if (cpu_arch_isa == PROCESSOR_K1OM)
10163 {
10164 if (x86_elf_abi != X86_64_ABI)
10165 as_fatal (_("Intel K1OM is 64bit only"));
10166 return ELF_TARGET_K1OM_FORMAT;
10167 }
8a9036a4 10168 else
351f65ca 10169 return format;
3e73aa7c 10170 }
e57f8c65
TG		 10171#endif
10172#if defined (OBJ_MACH_O)
10173 case bfd_target_mach_o_flavour:
d382c579
TG		 10174 if (flag_code == CODE_64BIT)
10175 {
10176 use_rela_relocations = 1;
10177 object_64bit = 1;
10178 return "mach-o-x86-64";
10179 }
10180 else
10181 return "mach-o-i386";
4c63da97 10182#endif
252b5132
RH		 10183 default:
10184 abort ();
10185 return NULL;
10186 }
10187}
10188
47926f60 10189#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10190
10191#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10192void
10193i386_elf_emit_arch_note (void)
a847613f 10194{
718ddfc0 10195 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10196 {
10197 char *p;
10198 asection *seg = now_seg;
10199 subsegT subseg = now_subseg;
10200 Elf_Internal_Note i_note;
10201 Elf_External_Note e_note;
10202 asection *note_secp;
10203 int len;
10204
10205 /* Create the .note section. */
10206 note_secp = subseg_new (".note", 0);
10207 bfd_set_section_flags (stdoutput,
10208 note_secp,
10209 SEC_HAS_CONTENTS | SEC_READONLY);
10210
10211 /* Process the arch string. */
10212 len = strlen (cpu_arch_name);
10213
10214 i_note.namesz = len + 1;
10215 i_note.descsz = 0;
10216 i_note.type = NT_ARCH;
10217 p = frag_more (sizeof (e_note.namesz));
10218 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10219 p = frag_more (sizeof (e_note.descsz));
10220 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10221 p = frag_more (sizeof (e_note.type));
10222 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10223 p = frag_more (len + 1);
10224 strcpy (p, cpu_arch_name);
10225
10226 frag_align (2, 0, 0);
10227
10228 subseg_set (seg, subseg);
10229 }
10230}
10231#endif
252b5132 10232\f
252b5132 10233symbolS *
7016a5d5 10234md_undefined_symbol (char *name)
252b5132 10235{
18dc2407
ILT		 10236 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10237 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10238 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10239 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10240 {
10241 if (!GOT_symbol)
10242 {
10243 if (symbol_find (name))
10244 as_bad (_("GOT already in symbol table"));
10245 GOT_symbol = symbol_new (name, undefined_section,
10246 (valueT) 0, &zero_address_frag);
10247 };
10248 return GOT_symbol;
10249 }
252b5132
RH		 10250 return 0;
10251}
10252
10253/* Round up a section size to the appropriate boundary. */
47926f60 10254
252b5132 10255valueT
7016a5d5 10256md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10257{
4c63da97
AM		 10258#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10259 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10260 {
10261 /* For a.out, force the section size to be aligned. If we don't do
10262 this, BFD will align it for us, but it will not write out the
10263 final bytes of the section. This may be a bug in BFD, but it is
10264 easier to fix it here since that is how the other a.out targets
10265 work. */
10266 int align;
10267
10268 align = bfd_get_section_alignment (stdoutput, segment);
10269 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10270 }
252b5132
RH		 10271#endif
10272
10273 return size;
10274}
10275
10276/* On the i386, PC-relative offsets are relative to the start of the
10277 next instruction. That is, the address of the offset, plus its
10278 size, since the offset is always the last part of the insn. */
10279
10280long
e3bb37b5 10281md_pcrel_from (fixS *fixP)
252b5132
RH		 10282{
10283 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10284}
10285
10286#ifndef I386COFF
10287
10288static void
e3bb37b5 10289s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10290{
29b0f896 10291 int temp;
252b5132 10292
8a75718c
JB		 10293#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10294 if (IS_ELF)
10295 obj_elf_section_change_hook ();
10296#endif
252b5132
RH		 10297 temp = get_absolute_expression ();
10298 subseg_set (bss_section, (subsegT) temp);
10299 demand_empty_rest_of_line ();
10300}
10301
10302#endif
10303
252b5132 10304void
e3bb37b5 10305i386_validate_fix (fixS *fixp)
252b5132
RH		 10306{
10307 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10308 {
23df1078
JH		 10309 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10310 {
4fa24527 10311 if (!object_64bit)
23df1078
JH		 10312 abort ();
10313 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10314 }
10315 else
10316 {
4fa24527 10317 if (!object_64bit)
d6ab8113
JB		 10318 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10319 else
10320 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10321 }
252b5132
RH		 10322 fixp->fx_subsy = 0;
10323 }
10324}
10325
252b5132 10326arelent *
7016a5d5 10327tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10328{
10329 arelent *rel;
10330 bfd_reloc_code_real_type code;
10331
10332 switch (fixp->fx_r_type)
10333 {
8ce3d284 10334#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10335 case BFD_RELOC_SIZE32:
10336 case BFD_RELOC_SIZE64:
10337 if (S_IS_DEFINED (fixp->fx_addsy)
10338 && !S_IS_EXTERNAL (fixp->fx_addsy))
10339 {
10340 /* Resolve size relocation against local symbol to size of
10341 the symbol plus addend. */
10342 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10343 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10344 && !fits_in_unsigned_long (value))
10345 as_bad_where (fixp->fx_file, fixp->fx_line,
10346 _("symbol size computation overflow"));
10347 fixp->fx_addsy = NULL;
10348 fixp->fx_subsy = NULL;
10349 md_apply_fix (fixp, (valueT *) &value, NULL);
10350 return NULL;
10351 }
8ce3d284 10352#endif
8fd4256d 10353
3e73aa7c 10354 case BFD_RELOC_X86_64_PLT32:
c3320543 10355 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10356 case BFD_RELOC_X86_64_GOT32:
10357 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10358 case BFD_RELOC_386_PLT32:
10359 case BFD_RELOC_386_GOT32:
10360 case BFD_RELOC_386_GOTOFF:
10361 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10362 case BFD_RELOC_386_TLS_GD:
10363 case BFD_RELOC_386_TLS_LDM:
10364 case BFD_RELOC_386_TLS_LDO_32:
10365 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10366 case BFD_RELOC_386_TLS_IE:
10367 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10368 case BFD_RELOC_386_TLS_LE_32:
10369 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10370 case BFD_RELOC_386_TLS_GOTDESC:
10371 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10372 case BFD_RELOC_X86_64_TLSGD:
10373 case BFD_RELOC_X86_64_TLSLD:
10374 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10375 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10376 case BFD_RELOC_X86_64_GOTTPOFF:
10377 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10378 case BFD_RELOC_X86_64_TPOFF64:
10379 case BFD_RELOC_X86_64_GOTOFF64:
10380 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10381 case BFD_RELOC_X86_64_GOT64:
10382 case BFD_RELOC_X86_64_GOTPCREL64:
10383 case BFD_RELOC_X86_64_GOTPC64:
10384 case BFD_RELOC_X86_64_GOTPLT64:
10385 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10386 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10387 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10388 case BFD_RELOC_RVA:
10389 case BFD_RELOC_VTABLE_ENTRY:
10390 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10391#ifdef TE_PE
10392 case BFD_RELOC_32_SECREL:
10393#endif
252b5132
RH		 10394 code = fixp->fx_r_type;
10395 break;
dbbaec26
L		 10396 case BFD_RELOC_X86_64_32S:
10397 if (!fixp->fx_pcrel)
10398 {
10399 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10400 code = fixp->fx_r_type;
10401 break;
10402 }
252b5132 10403 default:
93382f6d 10404 if (fixp->fx_pcrel)
252b5132 10405 {
93382f6d
AM		 10406 switch (fixp->fx_size)
10407 {
10408 default:
b091f402
AM		 10409 as_bad_where (fixp->fx_file, fixp->fx_line,
10410 _("can not do %d byte pc-relative relocation"),
10411 fixp->fx_size);
93382f6d
AM		 10412 code = BFD_RELOC_32_PCREL;
10413 break;
10414 case 1: code = BFD_RELOC_8_PCREL; break;
10415 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10416 case 4:
10417 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10418 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10419 break;
d6ab8113
JB		 10420#ifdef BFD64
10421 case 8: code = BFD_RELOC_64_PCREL; break;
10422#endif
93382f6d
AM		 10423 }
10424 }
10425 else
10426 {
10427 switch (fixp->fx_size)
10428 {
10429 default:
b091f402
AM		 10430 as_bad_where (fixp->fx_file, fixp->fx_line,
10431 _("can not do %d byte relocation"),
10432 fixp->fx_size);
93382f6d
AM		 10433 code = BFD_RELOC_32;
10434 break;
10435 case 1: code = BFD_RELOC_8; break;
10436 case 2: code = BFD_RELOC_16; break;
10437 case 4: code = BFD_RELOC_32; break;
937149dd 10438#ifdef BFD64
3e73aa7c 10439 case 8: code = BFD_RELOC_64; break;
937149dd 10440#endif
93382f6d 10441 }
252b5132
RH		 10442 }
10443 break;
10444 }
252b5132 10445
d182319b
JB		 10446 if ((code == BFD_RELOC_32
10447 || code == BFD_RELOC_32_PCREL
10448 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10449 && GOT_symbol
10450 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10451 {
4fa24527 10452 if (!object_64bit)
d6ab8113
JB		 10453 code = BFD_RELOC_386_GOTPC;
10454 else
10455 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10456 }
7b81dfbb
AJ		 10457 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10458 && GOT_symbol
10459 && fixp->fx_addsy == GOT_symbol)
10460 {
10461 code = BFD_RELOC_X86_64_GOTPC64;
10462 }
252b5132
RH		 10463
10464 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10465 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10466 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10467
10468 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10469
3e73aa7c
JH		 10470 if (!use_rela_relocations)
10471 {
10472 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10473 vtable entry to be used in the relocation's section offset. */
10474 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10475 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10476#if defined (OBJ_COFF) && defined (TE_PE)
10477 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10478 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10479 else
10480#endif
c6682705 10481 rel->addend = 0;
3e73aa7c
JH		 10482 }
10483 /* Use the rela in 64bit mode. */
252b5132 10484 else
3e73aa7c 10485 {
862be3fb
L		 10486 if (disallow_64bit_reloc)
10487 switch (code)
10488 {
862be3fb
L		 10489 case BFD_RELOC_X86_64_DTPOFF64:
10490 case BFD_RELOC_X86_64_TPOFF64:
10491 case BFD_RELOC_64_PCREL:
10492 case BFD_RELOC_X86_64_GOTOFF64:
10493 case BFD_RELOC_X86_64_GOT64:
10494 case BFD_RELOC_X86_64_GOTPCREL64:
10495 case BFD_RELOC_X86_64_GOTPC64:
10496 case BFD_RELOC_X86_64_GOTPLT64:
10497 case BFD_RELOC_X86_64_PLTOFF64:
10498 as_bad_where (fixp->fx_file, fixp->fx_line,
10499 _("cannot represent relocation type %s in x32 mode"),
10500 bfd_get_reloc_code_name (code));
10501 break;
10502 default:
10503 break;
10504 }
10505
062cd5e7
AS		 10506 if (!fixp->fx_pcrel)
10507 rel->addend = fixp->fx_offset;
10508 else
10509 switch (code)
10510 {
10511 case BFD_RELOC_X86_64_PLT32:
c3320543 10512 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10513 case BFD_RELOC_X86_64_GOT32:
10514 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10515 case BFD_RELOC_X86_64_TLSGD:
10516 case BFD_RELOC_X86_64_TLSLD:
10517 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10518 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10519 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10520 rel->addend = fixp->fx_offset - fixp->fx_size;
10521 break;
10522 default:
10523 rel->addend = (section->vma
10524 - fixp->fx_size
10525 + fixp->fx_addnumber
10526 + md_pcrel_from (fixp));
10527 break;
10528 }
3e73aa7c
JH		 10529 }
10530
252b5132
RH		 10531 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10532 if (rel->howto == NULL)
10533 {
10534 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10535 _("cannot represent relocation type %s"),
252b5132
RH		 10536 bfd_get_reloc_code_name (code));
10537 /* Set howto to a garbage value so that we can keep going. */
10538 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10539 gas_assert (rel->howto != NULL);
252b5132
RH		 10540 }
10541
10542 return rel;
10543}
10544
ee86248c 10545#include "tc-i386-intel.c"
54cfded0 10546
a60de03c
JB		 10547void
10548tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10549{
a60de03c
JB		 10550 int saved_naked_reg;
10551 char saved_register_dot;
54cfded0 10552
a60de03c
JB		 10553 saved_naked_reg = allow_naked_reg;
10554 allow_naked_reg = 1;
10555 saved_register_dot = register_chars['.'];
10556 register_chars['.'] = '.';
10557 allow_pseudo_reg = 1;
10558 expression_and_evaluate (exp);
10559 allow_pseudo_reg = 0;
10560 register_chars['.'] = saved_register_dot;
10561 allow_naked_reg = saved_naked_reg;
10562
e96d56a1 10563 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10564 {
a60de03c
JB		 10565 if ((addressT) exp->X_add_number < i386_regtab_size)
10566 {
10567 exp->X_op = O_constant;
10568 exp->X_add_number = i386_regtab[exp->X_add_number]
10569 .dw2_regnum[flag_code >> 1];
10570 }
10571 else
10572 exp->X_op = O_illegal;
54cfded0 10573 }
54cfded0
AM		 10574}
10575
10576void
10577tc_x86_frame_initial_instructions (void)
10578{
a60de03c
JB		 10579 static unsigned int sp_regno[2];
10580
10581 if (!sp_regno[flag_code >> 1])
10582 {
10583 char *saved_input = input_line_pointer;
10584 char sp[][4] = {"esp", "rsp"};
10585 expressionS exp;
a4447b93 10586
a60de03c
JB		 10587 input_line_pointer = sp[flag_code >> 1];
10588 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10589 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10590 sp_regno[flag_code >> 1] = exp.X_add_number;
10591 input_line_pointer = saved_input;
10592 }
a4447b93 10593
61ff971f
L		 10594 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10595 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10596}
d2b2c203 10597
d7921315
L		 10598int
10599x86_dwarf2_addr_size (void)
10600{
10601#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10602 if (x86_elf_abi == X86_64_X32_ABI)
10603 return 4;
10604#endif
10605 return bfd_arch_bits_per_address (stdoutput) / 8;
10606}
10607
d2b2c203
DJ		 10608int
10609i386_elf_section_type (const char *str, size_t len)
10610{
10611 if (flag_code == CODE_64BIT
10612 && len == sizeof ("unwind") - 1
10613 && strncmp (str, "unwind", 6) == 0)
10614 return SHT_X86_64_UNWIND;
10615
10616 return -1;
10617}
bb41ade5 10618
ad5fec3b
EB		 10619#ifdef TE_SOLARIS
10620void
10621i386_solaris_fix_up_eh_frame (segT sec)
10622{
10623 if (flag_code == CODE_64BIT)
10624 elf_section_type (sec) = SHT_X86_64_UNWIND;
10625}
10626#endif
10627
bb41ade5
AM		 10628#ifdef TE_PE
10629void
10630tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10631{
91d6fa6a 10632 expressionS exp;
bb41ade5 10633
91d6fa6a
NC		 10634 exp.X_op = O_secrel;
10635 exp.X_add_symbol = symbol;
10636 exp.X_add_number = 0;
10637 emit_expr (&exp, size);
bb41ade5
AM		 10638}
10639#endif
3b22753a
L		 10640
10641#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10642/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10643
01e1a5bc 10644bfd_vma
3b22753a
L		 10645x86_64_section_letter (int letter, char **ptr_msg)
10646{
10647 if (flag_code == CODE_64BIT)
10648 {
10649 if (letter == 'l')
10650 return SHF_X86_64_LARGE;
10651
8f3bae45 10652 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10653 }
3b22753a 10654 else
8f3bae45 10655 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10656 return -1;
10657}
10658
01e1a5bc 10659bfd_vma
3b22753a
L		 10660x86_64_section_word (char *str, size_t len)
10661{
8620418b 10662 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10663 return SHF_X86_64_LARGE;
10664
10665 return -1;
10666}
10667
10668static void
10669handle_large_common (int small ATTRIBUTE_UNUSED)
10670{
10671 if (flag_code != CODE_64BIT)
10672 {
10673 s_comm_internal (0, elf_common_parse);
10674 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10675 }
10676 else
10677 {
10678 static segT lbss_section;
10679 asection *saved_com_section_ptr = elf_com_section_ptr;
10680 asection *saved_bss_section = bss_section;
10681
10682 if (lbss_section == NULL)
10683 {
10684 flagword applicable;
10685 segT seg = now_seg;
10686 subsegT subseg = now_subseg;
10687
10688 /* The .lbss section is for local .largecomm symbols. */
10689 lbss_section = subseg_new (".lbss", 0);
10690 applicable = bfd_applicable_section_flags (stdoutput);
10691 bfd_set_section_flags (stdoutput, lbss_section,
10692 applicable & SEC_ALLOC);
10693 seg_info (lbss_section)->bss = 1;
10694
10695 subseg_set (seg, subseg);
10696 }
10697
10698 elf_com_section_ptr = &_bfd_elf_large_com_section;
10699 bss_section = lbss_section;
10700
10701 s_comm_internal (0, elf_common_parse);
10702
10703 elf_com_section_ptr = saved_com_section_ptr;
10704 bss_section = saved_bss_section;
10705 }
10706}
10707#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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