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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
2571583a 2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132 328
8325cc63
JB		 329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
252b5132
RH		 332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 338 addressing modes of this insn are encoded. */
252b5132 339 modrm_byte rm;
3e73aa7c 340 rex_byte rex;
43234a1e 341 rex_byte vrex;
252b5132 342 sib_byte sib;
c0f3af97 343 vex_prefix vex;
b6169b20 344
43234a1e
L		 345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
b6169b20 357 /* Swap operand in encoding. */
4473e004 358 unsigned int swap_operand;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
d5de92cf
L		 368 /* REP prefix. */
369 const char *rep_prefix;
370
165de32a
L		 371 /* HLE prefix. */
372 const char *hle_prefix;
42164a71 373
7e8b059b
L		 374 /* Have BND prefix. */
375 const char *bnd_prefix;
376
43234a1e
L		 377 /* Need VREX to support upper 16 registers. */
378 int need_vrex;
379
891edac4 380 /* Error message. */
a65babc9 381 enum i386_error error;
252b5132
RH		 382 };
383
384typedef struct _i386_insn i386_insn;
385
43234a1e
L		 386/* Link RC type with corresponding string, that'll be looked for in
387 asm. */
388struct RC_name
389{
390 enum rc_type type;
391 const char *name;
392 unsigned int len;
393};
394
395static const struct RC_name RC_NamesTable[] =
396{
397 { rne, STRING_COMMA_LEN ("rn-sae") },
398 { rd, STRING_COMMA_LEN ("rd-sae") },
399 { ru, STRING_COMMA_LEN ("ru-sae") },
400 { rz, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly, STRING_COMMA_LEN ("sae") },
402};
403
252b5132
RH		 404/* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 406const char extra_symbol_chars[] = "*%-([{"
252b5132 407#ifdef LEX_AT
32137342
NC		 408 "@"
409#endif
410#ifdef LEX_QM
411 "?"
252b5132 412#endif
32137342 413 ;
252b5132 414
29b0f896
AM		 415#if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 417 && !defined (TE_GNU) \
29b0f896 418 && !defined (TE_LINUX) \
8d63c93e
RM		 419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
29b0f896 421 && !defined (TE_FreeBSD) \
5b806d27 422 && !defined (TE_DragonFly) \
29b0f896 423 && !defined (TE_NetBSD)))
252b5132 424/* This array holds the chars that always start a comment. If the
b3b91714
AM		 425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427const char *i386_comment_chars = "#/";
428#define SVR4_COMMENT_CHARS 1
252b5132 429#define PREFIX_SEPARATOR '\\'
252b5132 430
b3b91714
AM		 431#else
432const char *i386_comment_chars = "#";
433#define PREFIX_SEPARATOR '/'
434#endif
435
252b5132
RH		 436/* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 440 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
252b5132 443 '/' isn't otherwise defined. */
b3b91714 444const char line_comment_chars[] = "#/";
252b5132 445
63a0b638 446const char line_separator_chars[] = ";";
252b5132 447
ce8a8b2f
AM		 448/* Chars that can be used to separate mant from exp in floating point
449 nums. */
252b5132
RH		 450const char EXP_CHARS[] = "eE";
451
ce8a8b2f
AM		 452/* Chars that mean this number is a floating point constant
453 As in 0f12.456
454 or 0d1.2345e12. */
252b5132
RH		 455const char FLT_CHARS[] = "fFdDxX";
456
ce8a8b2f 457/* Tables for lexical analysis. */
252b5132
RH		 458static char mnemonic_chars[256];
459static char register_chars[256];
460static char operand_chars[256];
461static char identifier_chars[256];
462static char digit_chars[256];
463
ce8a8b2f 464/* Lexical macros. */
252b5132
RH		 465#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466#define is_operand_char(x) (operand_chars[(unsigned char) x])
467#define is_register_char(x) (register_chars[(unsigned char) x])
468#define is_space_char(x) ((x) == ' ')
469#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470#define is_digit_char(x) (digit_chars[(unsigned char) x])
471
0234cb7c 472/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 473static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
474
475/* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
47926f60 478 assembler instruction). */
252b5132 479static char save_stack[32];
ce8a8b2f 480static char *save_stack_p;
252b5132
RH		 481#define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483#define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
485
47926f60 486/* The instruction we're assembling. */
252b5132
RH		 487static i386_insn i;
488
489/* Possible templates for current insn. */
490static const templates *current_templates;
491
31b2323c
L		 492/* Per instruction expressionS buffers: max displacements & immediates. */
493static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
494static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 495
47926f60 496/* Current operand we are working on. */
ee86248c 497static int this_operand = -1;
252b5132 498
3e73aa7c
JH		 499/* We support four different modes. FLAG_CODE variable is used to distinguish
500 these. */
501
502enum flag_code {
503 CODE_32BIT,
504 CODE_16BIT,
505 CODE_64BIT };
506
507static enum flag_code flag_code;
4fa24527 508static unsigned int object_64bit;
862be3fb 509static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 510static int use_rela_relocations = 0;
511
7af8ed2d
NC		 512#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
515
351f65ca
L		 516/* The ELF ABI to use. */
517enum x86_elf_abi
518{
519 I386_ABI,
7f56bc95
L		 520 X86_64_ABI,
521 X86_64_X32_ABI
351f65ca
L		 522};
523
524static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 525#endif
351f65ca 526
167ad85b
TG		 527#if defined (TE_PE) || defined (TE_PEP)
528/* Use big object file format. */
529static int use_big_obj = 0;
530#endif
531
8dcea932
L		 532#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533/* 1 if generating code for a shared library. */
534static int shared = 0;
535#endif
536
47926f60
KH		 537/* 1 for intel syntax,
538 0 if att syntax. */
539static int intel_syntax = 0;
252b5132 540
e89c5eaa
L		 541/* 1 for Intel64 ISA,
542 0 if AMD64 ISA. */
543static int intel64;
544
1efbbeb4
L		 545/* 1 for intel mnemonic,
546 0 if att mnemonic. */
547static int intel_mnemonic = !SYSV386_COMPAT;
548
5209009a 549/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 550static int old_gcc = OLDGCC_COMPAT;
551
a60de03c
JB		 552/* 1 if pseudo registers are permitted. */
553static int allow_pseudo_reg = 0;
554
47926f60
KH		 555/* 1 if register prefix % not required. */
556static int allow_naked_reg = 0;
252b5132 557
7e8b059b
L		 558/* 1 if the assembler should add BND prefix for all control-tranferring
559 instructions supporting it, even if this prefix wasn't specified
560 explicitly. */
561static int add_bnd_prefix = 0;
562
ba104c83 563/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 564static int allow_index_reg = 0;
565
d022bddd
IT		 566/* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568static int omit_lock_prefix = 0;
569
e4e00185
AS		 570/* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572static int avoid_fence = 0;
573
0cb4071e
L		 574/* 1 if the assembler should generate relax relocations. */
575
576static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
578
7bab8ab5 579static enum check_kind
daf50ae7 580 {
7bab8ab5
JB		 581 check_none = 0,
582 check_warning,
583 check_error
daf50ae7 584 }
7bab8ab5 585sse_check, operand_check = check_warning;
daf50ae7 586
2ca3ace5
L		 587/* Register prefix used for error message. */
588static const char *register_prefix = "%";
589
47926f60
KH		 590/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593static char stackop_size = '\0';
eecb386c 594
12b55ccc
L		 595/* Non-zero to optimize code alignment. */
596int optimize_align_code = 1;
597
47926f60
KH		 598/* Non-zero to quieten some warnings. */
599static int quiet_warnings = 0;
a38cf1db 600
47926f60
KH		 601/* CPU name. */
602static const char *cpu_arch_name = NULL;
6305a203 603static char *cpu_sub_arch_name = NULL;
a38cf1db 604
47926f60 605/* CPU feature flags. */
40fb9820
L		 606static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
607
ccc9c027
L		 608/* If we have selected a cpu we are generating instructions for. */
609static int cpu_arch_tune_set = 0;
610
9103f4f4 611/* Cpu we are generating instructions for. */
fbf3f584 612enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 613
614/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 615static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 616
ccc9c027 617/* CPU instruction set architecture used. */
fbf3f584 618enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 619
9103f4f4 620/* CPU feature flags of instruction set architecture used. */
fbf3f584 621i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 622
fddf5b5b
AM		 623/* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625static unsigned int no_cond_jump_promotion = 0;
626
c0f3af97
L		 627/* Encode SSE instructions with VEX prefix. */
628static unsigned int sse2avx;
629
539f890d
L		 630/* Encode scalar AVX instructions with specific vector length. */
631static enum
632 {
633 vex128 = 0,
634 vex256
635 } avxscalar;
636
43234a1e
L		 637/* Encode scalar EVEX LIG instructions with specific vector length. */
638static enum
639 {
640 evexl128 = 0,
641 evexl256,
642 evexl512
643 } evexlig;
644
645/* Encode EVEX WIG instructions with specific evex.w. */
646static enum
647 {
648 evexw0 = 0,
649 evexw1
650 } evexwig;
651
d3d3c6db
IT		 652/* Value to encode in EVEX RC bits, for SAE-only instructions. */
653static enum rc_type evexrcig = rne;
654
29b0f896 655/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 656static symbolS *GOT_symbol;
29b0f896 657
a4447b93
RH		 658/* The dwarf2 return column, adjusted for 32 or 64 bit. */
659unsigned int x86_dwarf2_return_column;
660
661/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662int x86_cie_data_alignment;
663
252b5132 664/* Interface to relax_segment.
fddf5b5b
AM		 665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
252b5132 668
47926f60 669/* Types. */
93c2a809
AM		 670#define UNCOND_JUMP 0
671#define COND_JUMP 1
672#define COND_JUMP86 2
fddf5b5b 673
47926f60 674/* Sizes. */
252b5132
RH		 675#define CODE16 1
676#define SMALL 0
29b0f896 677#define SMALL16 (SMALL | CODE16)
252b5132 678#define BIG 2
29b0f896 679#define BIG16 (BIG | CODE16)
252b5132
RH		 680
681#ifndef INLINE
682#ifdef __GNUC__
683#define INLINE __inline__
684#else
685#define INLINE
686#endif
687#endif
688
fddf5b5b
AM		 689#define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691#define TYPE_FROM_RELAX_STATE(s) \
692 ((s) >> 2)
693#define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 695
696/* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
703
704const relax_typeS md_relax_table[] =
705{
24eab124
AM		 706 /* The fields are:
707 1) most positive reach of this state,
708 2) most negative reach of this state,
93c2a809 709 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 710 4) which index into the table to try if we can't fit into this one. */
252b5132 711
fddf5b5b 712 /* UNCOND_JUMP states. */
93c2a809
AM		 713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
252b5132 717 {0, 0, 4, 0},
93c2a809
AM		 718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 720 {0, 0, 2, 0},
721
93c2a809
AM		 722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
727 {0, 0, 5, 0},
fddf5b5b 728 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 729 1 extra opcode byte, 2 displacement bytes. */
730 {0, 0, 3, 0},
731
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
737 {0, 0, 5, 0},
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
740 {0, 0, 4, 0}
252b5132
RH		 741};
742
9103f4f4
L		 743static const arch_entry cpu_arch[] =
744{
89507696
JB		 745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
8a2c8fef 747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 748 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 750 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 752 CPU_NONE_FLAGS, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 754 CPU_I186_FLAGS, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 756 CPU_I286_FLAGS, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 758 CPU_I386_FLAGS, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 760 CPU_I486_FLAGS, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 762 CPU_I586_FLAGS, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 764 CPU_I686_FLAGS, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 766 CPU_I586_FLAGS, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 768 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 770 CPU_P2_FLAGS, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 772 CPU_P3_FLAGS, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 774 CPU_P4_FLAGS, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 776 CPU_CORE_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 778 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 780 CPU_CORE_FLAGS, 1 },
8a2c8fef 781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 782 CPU_CORE_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 784 CPU_CORE2_FLAGS, 1 },
8a2c8fef 785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 786 CPU_CORE2_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 788 CPU_COREI7_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 790 CPU_L1OM_FLAGS, 0 },
7a9068fe 791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 792 CPU_K1OM_FLAGS, 0 },
81486035 793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 794 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 796 CPU_K6_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 798 CPU_K6_2_FLAGS, 0 },
8a2c8fef 799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 800 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 802 CPU_K8_FLAGS, 1 },
8a2c8fef 803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 804 CPU_K8_FLAGS, 0 },
8a2c8fef 805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 806 CPU_K8_FLAGS, 0 },
8a2c8fef 807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 808 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 810 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 812 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 814 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 816 CPU_BDVER4_FLAGS, 0 },
029f3522 817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 818 CPU_ZNVER1_FLAGS, 0 },
7b458c12 819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 820 CPU_BTVER1_FLAGS, 0 },
7b458c12 821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 822 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 824 CPU_8087_FLAGS, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 826 CPU_287_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 828 CPU_387_FLAGS, 0 },
1848e567
L		 829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
830 CPU_687_FLAGS, 0 },
8a2c8fef 831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 832 CPU_MMX_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 834 CPU_SSE_FLAGS, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 836 CPU_SSE2_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 838 CPU_SSE3_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 840 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 842 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 844 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 846 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 848 CPU_AVX_FLAGS, 0 },
6c30d220 849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 850 CPU_AVX2_FLAGS, 0 },
43234a1e 851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_AVX512F_FLAGS, 0 },
43234a1e 853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_AVX512CD_FLAGS, 0 },
43234a1e 855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_AVX512ER_FLAGS, 0 },
43234a1e 857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 858 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_VMX_FLAGS, 0 },
8729a6f6 867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_SMX_FLAGS, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_AES_FLAGS, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_F16C_FLAGS, 0 },
6c30d220 891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_BMI2_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_FMA_FLAGS, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_FMA4_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_XOP_FLAGS, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_LWP_FLAGS, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_MOVBE_FLAGS, 0 },
60aa667e 903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_CX16_FLAGS, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_EPT_FLAGS, 0 },
6c30d220 907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_LZCNT_FLAGS, 0 },
42164a71 909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_HLE_FLAGS, 0 },
42164a71 911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_RTM_FLAGS, 0 },
6c30d220 913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_CLFLUSH_FLAGS, 0 },
22109423 917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_NOP_FLAGS, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_SVME_FLAGS, 1 },
8a2c8fef 931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_SVME_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_ABM_FLAGS, 0 },
87973e9f 937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_BMI_FLAGS, 0 },
2a2a0f38 939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_TBM_FLAGS, 0 },
e2e1fcde 941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_ADX_FLAGS, 0 },
e2e1fcde 943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_PRFCHW_FLAGS, 0 },
5c111e37 947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SMAP_FLAGS, 0 },
7e8b059b 949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_MPX_FLAGS, 0 },
a0046408 951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_SHA_FLAGS, 0 },
963f3586 953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_SE1_FLAGS, 0 },
c5e7287a 959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 961 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 963 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 965 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
966 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 967 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
968 CPU_AVX512_4VNNIW_FLAGS, 0 },
029f3522 969 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_CLZERO_FLAGS, 0 },
9916071f 971 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_MWAITX_FLAGS, 0 },
8eab4136 973 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_OSPKE_FLAGS, 0 },
8bc52696 975 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 977 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
978 CPU_PTWRITE_FLAGS, 0 },
293f5f65
L		 979};
980
981static const noarch_entry cpu_noarch[] =
982{
983 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 984 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
985 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
986 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 987 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
988 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 989 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
990 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
991 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
992 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
993 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
994 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 995 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 996 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 997 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
998 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
999 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1000 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1001 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1002 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1003 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1004 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1005 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1006 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1007 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
e413e4e9
AM		 1008};
1009
704209c0 1010#ifdef I386COFF
a6c24e68
NC		 1011/* Like s_lcomm_internal in gas/read.c but the alignment string
1012 is allowed to be optional. */
1013
1014static symbolS *
1015pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1016{
1017 addressT align = 0;
1018
1019 SKIP_WHITESPACE ();
1020
7ab9ffdd 1021 if (needs_align
a6c24e68
NC		 1022 && *input_line_pointer == ',')
1023 {
1024 align = parse_align (needs_align - 1);
7ab9ffdd 1025
a6c24e68
NC		 1026 if (align == (addressT) -1)
1027 return NULL;
1028 }
1029 else
1030 {
1031 if (size >= 8)
1032 align = 3;
1033 else if (size >= 4)
1034 align = 2;
1035 else if (size >= 2)
1036 align = 1;
1037 else
1038 align = 0;
1039 }
1040
1041 bss_alloc (symbolP, size, align);
1042 return symbolP;
1043}
1044
704209c0 1045static void
a6c24e68
NC		 1046pe_lcomm (int needs_align)
1047{
1048 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1049}
704209c0 1050#endif
a6c24e68 1051
29b0f896
AM		 1052const pseudo_typeS md_pseudo_table[] =
1053{
1054#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1055 {"align", s_align_bytes, 0},
1056#else
1057 {"align", s_align_ptwo, 0},
1058#endif
1059 {"arch", set_cpu_arch, 0},
1060#ifndef I386COFF
1061 {"bss", s_bss, 0},
a6c24e68
NC		 1062#else
1063 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1064#endif
1065 {"ffloat", float_cons, 'f'},
1066 {"dfloat", float_cons, 'd'},
1067 {"tfloat", float_cons, 'x'},
1068 {"value", cons, 2},
d182319b 1069 {"slong", signed_cons, 4},
29b0f896
AM		 1070 {"noopt", s_ignore, 0},
1071 {"optim", s_ignore, 0},
1072 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1073 {"code16", set_code_flag, CODE_16BIT},
1074 {"code32", set_code_flag, CODE_32BIT},
1075 {"code64", set_code_flag, CODE_64BIT},
1076 {"intel_syntax", set_intel_syntax, 1},
1077 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1078 {"intel_mnemonic", set_intel_mnemonic, 1},
1079 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1080 {"allow_index_reg", set_allow_index_reg, 1},
1081 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1082 {"sse_check", set_check, 0},
1083 {"operand_check", set_check, 1},
3b22753a
L		 1084#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1085 {"largecomm", handle_large_common, 0},
07a53e5c 1086#else
e3bb37b5 1087 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1088 {"loc", dwarf2_directive_loc, 0},
1089 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1090#endif
6482c264
NC		 1091#ifdef TE_PE
1092 {"secrel32", pe_directive_secrel, 0},
1093#endif
29b0f896
AM		 1094 {0, 0, 0}
1095};
1096
1097/* For interface with expression (). */
1098extern char *input_line_pointer;
1099
1100/* Hash table for instruction mnemonic lookup. */
1101static struct hash_control *op_hash;
1102
1103/* Hash table for register lookup. */
1104static struct hash_control *reg_hash;
1105\f
252b5132 1106void
e3bb37b5 1107i386_align_code (fragS *fragP, int count)
252b5132 1108{
ce8a8b2f
AM		 1109 /* Various efficient no-op patterns for aligning code labels.
1110 Note: Don't try to assemble the instructions in the comments.
1111 0L and 0w are not legal. */
bad6e36d 1112 static const unsigned char f32_1[] =
252b5132 1113 {0x90}; /* nop */
bad6e36d 1114 static const unsigned char f32_2[] =
ccc9c027 1115 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1116 static const unsigned char f32_3[] =
252b5132 1117 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1118 static const unsigned char f32_4[] =
252b5132 1119 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1120 static const unsigned char f32_5[] =
252b5132
RH		 1121 {0x90, /* nop */
1122 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1123 static const unsigned char f32_6[] =
252b5132 1124 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1125 static const unsigned char f32_7[] =
252b5132 1126 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1127 static const unsigned char f32_8[] =
252b5132
RH		 1128 {0x90, /* nop */
1129 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1130 static const unsigned char f32_9[] =
252b5132
RH		 1131 {0x89,0xf6, /* movl %esi,%esi */
1132 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1133 static const unsigned char f32_10[] =
252b5132
RH		 1134 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1135 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1136 static const unsigned char f32_11[] =
252b5132
RH		 1137 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1138 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1139 static const unsigned char f32_12[] =
252b5132
RH		 1140 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1141 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1142 static const unsigned char f32_13[] =
252b5132
RH		 1143 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1144 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1145 static const unsigned char f32_14[] =
252b5132
RH		 1146 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1147 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1148 static const unsigned char f16_3[] =
c3332e24 1149 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1150 static const unsigned char f16_4[] =
252b5132 1151 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1152 static const unsigned char f16_5[] =
252b5132
RH		 1153 {0x90, /* nop */
1154 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1155 static const unsigned char f16_6[] =
252b5132
RH		 1156 {0x89,0xf6, /* mov %si,%si */
1157 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1158 static const unsigned char f16_7[] =
252b5132
RH		 1159 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1160 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1161 static const unsigned char f16_8[] =
252b5132
RH		 1162 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1163 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1164 static const unsigned char jump_31[] =
76bc74dc
L		 1165 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1166 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1167 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1168 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1169 static const unsigned char *const f32_patt[] = {
252b5132 1170 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1171 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1172 };
bad6e36d 1173 static const unsigned char *const f16_patt[] = {
76bc74dc 1174 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1175 };
ccc9c027 1176 /* nopl (%[re]ax) */
bad6e36d 1177 static const unsigned char alt_3[] =
ccc9c027
L		 1178 {0x0f,0x1f,0x00};
1179 /* nopl 0(%[re]ax) */
bad6e36d 1180 static const unsigned char alt_4[] =
ccc9c027
L		 1181 {0x0f,0x1f,0x40,0x00};
1182 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1183 static const unsigned char alt_5[] =
ccc9c027
L		 1184 {0x0f,0x1f,0x44,0x00,0x00};
1185 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1186 static const unsigned char alt_6[] =
ccc9c027
L		 1187 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1188 /* nopl 0L(%[re]ax) */
bad6e36d 1189 static const unsigned char alt_7[] =
ccc9c027
L		 1190 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1191 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1192 static const unsigned char alt_8[] =
ccc9c027
L		 1193 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1194 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1195 static const unsigned char alt_9[] =
ccc9c027
L		 1196 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1197 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1198 static const unsigned char alt_10[] =
ccc9c027 1199 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1200 static const unsigned char *const alt_patt[] = {
ccc9c027 1201 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1202 alt_9, alt_10
ccc9c027 1203 };
252b5132 1204
76bc74dc
L		 1205 /* Only align for at least a positive non-zero boundary. */
1206 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1207 return;
3e73aa7c 1208
ccc9c027
L		 1209 /* We need to decide which NOP sequence to use for 32bit and
1210 64bit. When -mtune= is used:
4eed87de 1211
76bc74dc
L		 1212 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1213 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1214 2. For the rest, alt_patt will be used.
1215
1216 When -mtune= isn't used, alt_patt will be used if
22109423 1217 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1218 be used.
ccc9c027
L		 1219
1220 When -march= or .arch is used, we can't use anything beyond
1221 cpu_arch_isa_flags. */
1222
1223 if (flag_code == CODE_16BIT)
1224 {
ccc9c027 1225 if (count > 8)
33fef721 1226 {
76bc74dc
L		 1227 memcpy (fragP->fr_literal + fragP->fr_fix,
1228 jump_31, count);
1229 /* Adjust jump offset. */
1230 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1231 }
76bc74dc
L		 1232 else
1233 memcpy (fragP->fr_literal + fragP->fr_fix,
1234 f16_patt[count - 1], count);
252b5132 1235 }
33fef721 1236 else
ccc9c027 1237 {
bad6e36d 1238 const unsigned char *const *patt = NULL;
ccc9c027 1239
fbf3f584 1240 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1241 {
1242 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1243 switch (cpu_arch_tune)
1244 {
1245 case PROCESSOR_UNKNOWN:
1246 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1247 optimize with nops. */
1248 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1249 patt = alt_patt;
ccc9c027
L		 1250 else
1251 patt = f32_patt;
1252 break;
ccc9c027
L		 1253 case PROCESSOR_PENTIUM4:
1254 case PROCESSOR_NOCONA:
ef05d495 1255 case PROCESSOR_CORE:
76bc74dc 1256 case PROCESSOR_CORE2:
bd5295b2 1257 case PROCESSOR_COREI7:
3632d14b 1258 case PROCESSOR_L1OM:
7a9068fe 1259 case PROCESSOR_K1OM:
76bc74dc 1260 case PROCESSOR_GENERIC64:
ccc9c027
L		 1261 case PROCESSOR_K6:
1262 case PROCESSOR_ATHLON:
1263 case PROCESSOR_K8:
4eed87de 1264 case PROCESSOR_AMDFAM10:
8aedb9fe 1265 case PROCESSOR_BD:
029f3522 1266 case PROCESSOR_ZNVER:
7b458c12 1267 case PROCESSOR_BT:
80b8656c 1268 patt = alt_patt;
ccc9c027 1269 break;
76bc74dc 1270 case PROCESSOR_I386:
ccc9c027
L		 1271 case PROCESSOR_I486:
1272 case PROCESSOR_PENTIUM:
2dde1948 1273 case PROCESSOR_PENTIUMPRO:
81486035 1274 case PROCESSOR_IAMCU:
ccc9c027
L		 1275 case PROCESSOR_GENERIC32:
1276 patt = f32_patt;
1277 break;
4eed87de 1278 }
ccc9c027
L		 1279 }
1280 else
1281 {
fbf3f584 1282 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1283 {
1284 case PROCESSOR_UNKNOWN:
e6a14101 1285 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1286 PROCESSOR_UNKNOWN. */
1287 abort ();
1288 break;
1289
76bc74dc 1290 case PROCESSOR_I386:
ccc9c027
L		 1291 case PROCESSOR_I486:
1292 case PROCESSOR_PENTIUM:
81486035 1293 case PROCESSOR_IAMCU:
ccc9c027
L		 1294 case PROCESSOR_K6:
1295 case PROCESSOR_ATHLON:
1296 case PROCESSOR_K8:
4eed87de 1297 case PROCESSOR_AMDFAM10:
8aedb9fe 1298 case PROCESSOR_BD:
029f3522 1299 case PROCESSOR_ZNVER:
7b458c12 1300 case PROCESSOR_BT:
ccc9c027
L		 1301 case PROCESSOR_GENERIC32:
1302 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1303 with nops. */
1304 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1305 patt = alt_patt;
ccc9c027
L		 1306 else
1307 patt = f32_patt;
1308 break;
76bc74dc
L		 1309 case PROCESSOR_PENTIUMPRO:
1310 case PROCESSOR_PENTIUM4:
1311 case PROCESSOR_NOCONA:
1312 case PROCESSOR_CORE:
ef05d495 1313 case PROCESSOR_CORE2:
bd5295b2 1314 case PROCESSOR_COREI7:
3632d14b 1315 case PROCESSOR_L1OM:
7a9068fe 1316 case PROCESSOR_K1OM:
22109423 1317 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1318 patt = alt_patt;
ccc9c027
L		 1319 else
1320 patt = f32_patt;
1321 break;
1322 case PROCESSOR_GENERIC64:
80b8656c 1323 patt = alt_patt;
ccc9c027 1324 break;
4eed87de 1325 }
ccc9c027
L		 1326 }
1327
76bc74dc
L		 1328 if (patt == f32_patt)
1329 {
1330 /* If the padding is less than 15 bytes, we use the normal
1331 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1332 its offset. */
1333 int limit;
76ba9986 1334
711eedef
L		 1335 /* For 64bit, the limit is 3 bytes. */
1336 if (flag_code == CODE_64BIT
1337 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1338 limit = 3;
1339 else
1340 limit = 15;
1341 if (count < limit)
76bc74dc
L		 1342 memcpy (fragP->fr_literal + fragP->fr_fix,
1343 patt[count - 1], count);
1344 else
1345 {
1346 memcpy (fragP->fr_literal + fragP->fr_fix,
1347 jump_31, count);
1348 /* Adjust jump offset. */
1349 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1350 }
1351 }
1352 else
1353 {
80b8656c
L		 1354 /* Maximum length of an instruction is 10 byte. If the
1355 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1356 we have to break it into smaller pieces. */
1357 int padding = count;
80b8656c 1358 while (padding > 10)
76bc74dc 1359 {
80b8656c 1360 padding -= 10;
76bc74dc 1361 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1362 patt [9], 10);
76bc74dc
L		 1363 }
1364
1365 if (padding)
1366 memcpy (fragP->fr_literal + fragP->fr_fix,
1367 patt [padding - 1], padding);
1368 }
ccc9c027 1369 }
33fef721 1370 fragP->fr_var = count;
252b5132
RH		 1371}
1372
c6fb90c8 1373static INLINE int
0dfbf9d7 1374operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1375{
0dfbf9d7 1376 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1377 {
1378 case 3:
0dfbf9d7 1379 if (x->array[2])
c6fb90c8 1380 return 0;
1a0670f3 1381 /* Fall through. */
c6fb90c8 1382 case 2:
0dfbf9d7 1383 if (x->array[1])
c6fb90c8 1384 return 0;
1a0670f3 1385 /* Fall through. */
c6fb90c8 1386 case 1:
0dfbf9d7 1387 return !x->array[0];
c6fb90c8
L		 1388 default:
1389 abort ();
1390 }
40fb9820
L		 1391}
1392
c6fb90c8 1393static INLINE void
0dfbf9d7 1394operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1395{
0dfbf9d7 1396 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1397 {
1398 case 3:
0dfbf9d7 1399 x->array[2] = v;
1a0670f3 1400 /* Fall through. */
c6fb90c8 1401 case 2:
0dfbf9d7 1402 x->array[1] = v;
1a0670f3 1403 /* Fall through. */
c6fb90c8 1404 case 1:
0dfbf9d7 1405 x->array[0] = v;
1a0670f3 1406 /* Fall through. */
c6fb90c8
L		 1407 break;
1408 default:
1409 abort ();
1410 }
1411}
40fb9820 1412
c6fb90c8 1413static INLINE int
0dfbf9d7
L		 1414operand_type_equal (const union i386_operand_type *x,
1415 const union i386_operand_type *y)
c6fb90c8 1416{
0dfbf9d7 1417 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1418 {
1419 case 3:
0dfbf9d7 1420 if (x->array[2] != y->array[2])
c6fb90c8 1421 return 0;
1a0670f3 1422 /* Fall through. */
c6fb90c8 1423 case 2:
0dfbf9d7 1424 if (x->array[1] != y->array[1])
c6fb90c8 1425 return 0;
1a0670f3 1426 /* Fall through. */
c6fb90c8 1427 case 1:
0dfbf9d7 1428 return x->array[0] == y->array[0];
c6fb90c8
L		 1429 break;
1430 default:
1431 abort ();
1432 }
1433}
40fb9820 1434
0dfbf9d7
L		 1435static INLINE int
1436cpu_flags_all_zero (const union i386_cpu_flags *x)
1437{
1438 switch (ARRAY_SIZE(x->array))
1439 {
1440 case 3:
1441 if (x->array[2])
1442 return 0;
1a0670f3 1443 /* Fall through. */
0dfbf9d7
L		 1444 case 2:
1445 if (x->array[1])
1446 return 0;
1a0670f3 1447 /* Fall through. */
0dfbf9d7
L		 1448 case 1:
1449 return !x->array[0];
1450 default:
1451 abort ();
1452 }
1453}
1454
0dfbf9d7
L		 1455static INLINE int
1456cpu_flags_equal (const union i386_cpu_flags *x,
1457 const union i386_cpu_flags *y)
1458{
1459 switch (ARRAY_SIZE(x->array))
1460 {
1461 case 3:
1462 if (x->array[2] != y->array[2])
1463 return 0;
1a0670f3 1464 /* Fall through. */
0dfbf9d7
L		 1465 case 2:
1466 if (x->array[1] != y->array[1])
1467 return 0;
1a0670f3 1468 /* Fall through. */
0dfbf9d7
L		 1469 case 1:
1470 return x->array[0] == y->array[0];
1471 break;
1472 default:
1473 abort ();
1474 }
1475}
c6fb90c8
L		 1476
1477static INLINE int
1478cpu_flags_check_cpu64 (i386_cpu_flags f)
1479{
1480 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1481 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1482}
1483
c6fb90c8
L		 1484static INLINE i386_cpu_flags
1485cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1486{
c6fb90c8
L		 1487 switch (ARRAY_SIZE (x.array))
1488 {
1489 case 3:
1490 x.array [2] &= y.array [2];
1a0670f3 1491 /* Fall through. */
c6fb90c8
L		 1492 case 2:
1493 x.array [1] &= y.array [1];
1a0670f3 1494 /* Fall through. */
c6fb90c8
L		 1495 case 1:
1496 x.array [0] &= y.array [0];
1497 break;
1498 default:
1499 abort ();
1500 }
1501 return x;
1502}
40fb9820 1503
c6fb90c8
L		 1504static INLINE i386_cpu_flags
1505cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1506{
c6fb90c8 1507 switch (ARRAY_SIZE (x.array))
40fb9820 1508 {
c6fb90c8
L		 1509 case 3:
1510 x.array [2] |= y.array [2];
1a0670f3 1511 /* Fall through. */
c6fb90c8
L		 1512 case 2:
1513 x.array [1] |= y.array [1];
1a0670f3 1514 /* Fall through. */
c6fb90c8
L		 1515 case 1:
1516 x.array [0] |= y.array [0];
40fb9820
L		 1517 break;
1518 default:
1519 abort ();
1520 }
40fb9820
L		 1521 return x;
1522}
1523
309d3373
JB		 1524static INLINE i386_cpu_flags
1525cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1526{
1527 switch (ARRAY_SIZE (x.array))
1528 {
1529 case 3:
1530 x.array [2] &= ~y.array [2];
1a0670f3 1531 /* Fall through. */
309d3373
JB		 1532 case 2:
1533 x.array [1] &= ~y.array [1];
1a0670f3 1534 /* Fall through. */
309d3373
JB		 1535 case 1:
1536 x.array [0] &= ~y.array [0];
1537 break;
1538 default:
1539 abort ();
1540 }
1541 return x;
1542}
1543
c0f3af97
L		 1544#define CPU_FLAGS_ARCH_MATCH 0x1
1545#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1546#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1547#define CPU_FLAGS_PCLMUL_MATCH 0x8
1548#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1549
a5ff0eb2 1550#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1551 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1552 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1553#define CPU_FLAGS_PERFECT_MATCH \
1554 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1555
1556/* Return CPU flags match bits. */
3629bb00 1557
40fb9820 1558static int
d3ce72d0 1559cpu_flags_match (const insn_template *t)
40fb9820 1560{
c0f3af97
L		 1561 i386_cpu_flags x = t->cpu_flags;
1562 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1563
1564 x.bitfield.cpu64 = 0;
1565 x.bitfield.cpuno64 = 0;
1566
0dfbf9d7 1567 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1568 {
1569 /* This instruction is available on all archs. */
1570 match |= CPU_FLAGS_32BIT_MATCH;
1571 }
3629bb00
L		 1572 else
1573 {
c0f3af97 1574 /* This instruction is available only on some archs. */
3629bb00
L		 1575 i386_cpu_flags cpu = cpu_arch_flags;
1576
3629bb00 1577 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1578 if (!cpu_flags_all_zero (&cpu))
1579 {
a5ff0eb2
L		 1580 if (x.bitfield.cpuavx)
1581 {
ce2f5b3c 1582 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1583 if (cpu.bitfield.cpuavx)
1584 {
1585 /* Check SSE2AVX. */
1586 if (!t->opcode_modifier.sse2avx|| sse2avx)
1587 {
1588 match |= (CPU_FLAGS_ARCH_MATCH
1589 | CPU_FLAGS_AVX_MATCH);
1590 /* Check AES. */
1591 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1592 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1593 /* Check PCLMUL. */
1594 if (!x.bitfield.cpupclmul
1595 || cpu.bitfield.cpupclmul)
1596 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1597 }
1598 }
1599 else
1600 match |= CPU_FLAGS_ARCH_MATCH;
1601 }
73b090a9
L		 1602 else if (x.bitfield.cpuavx512vl)
1603 {
1604 /* Match AVX512VL. */
1605 if (cpu.bitfield.cpuavx512vl)
1606 {
1607 /* Need another match. */
1608 cpu.bitfield.cpuavx512vl = 0;
1609 if (!cpu_flags_all_zero (&cpu))
1610 match |= CPU_FLAGS_32BIT_MATCH;
1611 else
1612 match |= CPU_FLAGS_ARCH_MATCH;
1613 }
1614 else
1615 match |= CPU_FLAGS_ARCH_MATCH;
1616 }
a5ff0eb2 1617 else
c0f3af97
L		 1618 match |= CPU_FLAGS_32BIT_MATCH;
1619 }
3629bb00 1620 }
c0f3af97 1621 return match;
40fb9820
L		 1622}
1623
c6fb90c8
L		 1624static INLINE i386_operand_type
1625operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1626{
c6fb90c8
L		 1627 switch (ARRAY_SIZE (x.array))
1628 {
1629 case 3:
1630 x.array [2] &= y.array [2];
1a0670f3 1631 /* Fall through. */
c6fb90c8
L		 1632 case 2:
1633 x.array [1] &= y.array [1];
1a0670f3 1634 /* Fall through. */
c6fb90c8
L		 1635 case 1:
1636 x.array [0] &= y.array [0];
1637 break;
1638 default:
1639 abort ();
1640 }
1641 return x;
40fb9820
L		 1642}
1643
c6fb90c8
L		 1644static INLINE i386_operand_type
1645operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1646{
c6fb90c8 1647 switch (ARRAY_SIZE (x.array))
40fb9820 1648 {
c6fb90c8
L		 1649 case 3:
1650 x.array [2] |= y.array [2];
1a0670f3 1651 /* Fall through. */
c6fb90c8
L		 1652 case 2:
1653 x.array [1] |= y.array [1];
1a0670f3 1654 /* Fall through. */
c6fb90c8
L		 1655 case 1:
1656 x.array [0] |= y.array [0];
40fb9820
L		 1657 break;
1658 default:
1659 abort ();
1660 }
c6fb90c8
L		 1661 return x;
1662}
40fb9820 1663
c6fb90c8
L		 1664static INLINE i386_operand_type
1665operand_type_xor (i386_operand_type x, i386_operand_type y)
1666{
1667 switch (ARRAY_SIZE (x.array))
1668 {
1669 case 3:
1670 x.array [2] ^= y.array [2];
1a0670f3 1671 /* Fall through. */
c6fb90c8
L		 1672 case 2:
1673 x.array [1] ^= y.array [1];
1a0670f3 1674 /* Fall through. */
c6fb90c8
L		 1675 case 1:
1676 x.array [0] ^= y.array [0];
1677 break;
1678 default:
1679 abort ();
1680 }
40fb9820
L		 1681 return x;
1682}
1683
1684static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1685static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1686static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1687static const i386_operand_type inoutportreg
1688 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1689static const i386_operand_type reg16_inoutportreg
1690 = OPERAND_TYPE_REG16_INOUTPORTREG;
1691static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1692static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1693static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1694static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1695static const i386_operand_type anydisp
1696 = OPERAND_TYPE_ANYDISP;
40fb9820 1697static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1698static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1699static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1700static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1701static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1702static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1703static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1704static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1705static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1706static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1707static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1708static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1709static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1710static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1711
1712enum operand_type
1713{
1714 reg,
40fb9820
L		 1715 imm,
1716 disp,
1717 anymem
1718};
1719
c6fb90c8 1720static INLINE int
40fb9820
L		 1721operand_type_check (i386_operand_type t, enum operand_type c)
1722{
1723 switch (c)
1724 {
1725 case reg:
1726 return (t.bitfield.reg8
1727 || t.bitfield.reg16
1728 || t.bitfield.reg32
1729 || t.bitfield.reg64);
1730
40fb9820
L		 1731 case imm:
1732 return (t.bitfield.imm8
1733 || t.bitfield.imm8s
1734 || t.bitfield.imm16
1735 || t.bitfield.imm32
1736 || t.bitfield.imm32s
1737 || t.bitfield.imm64);
1738
1739 case disp:
1740 return (t.bitfield.disp8
1741 || t.bitfield.disp16
1742 || t.bitfield.disp32
1743 || t.bitfield.disp32s
1744 || t.bitfield.disp64);
1745
1746 case anymem:
1747 return (t.bitfield.disp8
1748 || t.bitfield.disp16
1749 || t.bitfield.disp32
1750 || t.bitfield.disp32s
1751 || t.bitfield.disp64
1752 || t.bitfield.baseindex);
1753
1754 default:
1755 abort ();
1756 }
2cfe26b6
AM		 1757
1758 return 0;
40fb9820
L		 1759}
1760
5c07affc
L		 1761/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1762 operand J for instruction template T. */
1763
1764static INLINE int
d3ce72d0 1765match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1766{
1767 return !((i.types[j].bitfield.byte
1768 && !t->operand_types[j].bitfield.byte)
1769 || (i.types[j].bitfield.word
1770 && !t->operand_types[j].bitfield.word)
1771 || (i.types[j].bitfield.dword
1772 && !t->operand_types[j].bitfield.dword)
1773 || (i.types[j].bitfield.qword
1774 && !t->operand_types[j].bitfield.qword));
1775}
1776
1777/* Return 1 if there is no conflict in any size on operand J for
1778 instruction template T. */
1779
1780static INLINE int
d3ce72d0 1781match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1782{
1783 return (match_reg_size (t, j)
1784 && !((i.types[j].bitfield.unspecified
af508cb9 1785 && !i.broadcast
5c07affc
L		 1786 && !t->operand_types[j].bitfield.unspecified)
1787 || (i.types[j].bitfield.fword
1788 && !t->operand_types[j].bitfield.fword)
1789 || (i.types[j].bitfield.tbyte
1790 && !t->operand_types[j].bitfield.tbyte)
1791 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1792 && !t->operand_types[j].bitfield.xmmword)
1793 || (i.types[j].bitfield.ymmword
43234a1e
L		 1794 && !t->operand_types[j].bitfield.ymmword)
1795 || (i.types[j].bitfield.zmmword
1796 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1797}
1798
1799/* Return 1 if there is no size conflict on any operands for
1800 instruction template T. */
1801
1802static INLINE int
d3ce72d0 1803operand_size_match (const insn_template *t)
5c07affc
L		 1804{
1805 unsigned int j;
1806 int match = 1;
1807
1808 /* Don't check jump instructions. */
1809 if (t->opcode_modifier.jump
1810 || t->opcode_modifier.jumpbyte
1811 || t->opcode_modifier.jumpdword
1812 || t->opcode_modifier.jumpintersegment)
1813 return match;
1814
1815 /* Check memory and accumulator operand size. */
1816 for (j = 0; j < i.operands; j++)
1817 {
1818 if (t->operand_types[j].bitfield.anysize)
1819 continue;
1820
1821 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1822 {
1823 match = 0;
1824 break;
1825 }
1826
1827 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1828 {
1829 match = 0;
1830 break;
1831 }
1832 }
1833
891edac4 1834 if (match)
5c07affc 1835 return match;
891edac4
L		 1836 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1837 {
1838mismatch:
86e026a4 1839 i.error = operand_size_mismatch;
891edac4
L		 1840 return 0;
1841 }
5c07affc
L		 1842
1843 /* Check reverse. */
9c2799c2 1844 gas_assert (i.operands == 2);
5c07affc
L		 1845
1846 match = 1;
1847 for (j = 0; j < 2; j++)
1848 {
1849 if (t->operand_types[j].bitfield.acc
1850 && !match_reg_size (t, j ? 0 : 1))
891edac4 1851 goto mismatch;
5c07affc
L		 1852
1853 if (i.types[j].bitfield.mem
1854 && !match_mem_size (t, j ? 0 : 1))
891edac4 1855 goto mismatch;
5c07affc
L		 1856 }
1857
1858 return match;
1859}
1860
c6fb90c8 1861static INLINE int
40fb9820
L		 1862operand_type_match (i386_operand_type overlap,
1863 i386_operand_type given)
1864{
1865 i386_operand_type temp = overlap;
1866
1867 temp.bitfield.jumpabsolute = 0;
7d5e4556 1868 temp.bitfield.unspecified = 0;
5c07affc
L		 1869 temp.bitfield.byte = 0;
1870 temp.bitfield.word = 0;
1871 temp.bitfield.dword = 0;
1872 temp.bitfield.fword = 0;
1873 temp.bitfield.qword = 0;
1874 temp.bitfield.tbyte = 0;
1875 temp.bitfield.xmmword = 0;
c0f3af97 1876 temp.bitfield.ymmword = 0;
43234a1e 1877 temp.bitfield.zmmword = 0;
0dfbf9d7 1878 if (operand_type_all_zero (&temp))
891edac4 1879 goto mismatch;
40fb9820 1880
891edac4
L		 1881 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1882 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1883 return 1;
1884
1885mismatch:
a65babc9 1886 i.error = operand_type_mismatch;
891edac4 1887 return 0;
40fb9820
L		 1888}
1889
7d5e4556 1890/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1891 unless the expected operand type register overlap is null.
1892 Note that Acc in a template matches every size of reg. */
1893
c6fb90c8 1894static INLINE int
40fb9820
L		 1895operand_type_register_match (i386_operand_type m0,
1896 i386_operand_type g0,
1897 i386_operand_type t0,
1898 i386_operand_type m1,
1899 i386_operand_type g1,
1900 i386_operand_type t1)
1901{
1902 if (!operand_type_check (g0, reg))
1903 return 1;
1904
1905 if (!operand_type_check (g1, reg))
1906 return 1;
1907
1908 if (g0.bitfield.reg8 == g1.bitfield.reg8
1909 && g0.bitfield.reg16 == g1.bitfield.reg16
1910 && g0.bitfield.reg32 == g1.bitfield.reg32
1911 && g0.bitfield.reg64 == g1.bitfield.reg64)
1912 return 1;
1913
1914 if (m0.bitfield.acc)
1915 {
1916 t0.bitfield.reg8 = 1;
1917 t0.bitfield.reg16 = 1;
1918 t0.bitfield.reg32 = 1;
1919 t0.bitfield.reg64 = 1;
1920 }
1921
1922 if (m1.bitfield.acc)
1923 {
1924 t1.bitfield.reg8 = 1;
1925 t1.bitfield.reg16 = 1;
1926 t1.bitfield.reg32 = 1;
1927 t1.bitfield.reg64 = 1;
1928 }
1929
891edac4
L		 1930 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1931 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1932 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1933 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1934 return 1;
1935
a65babc9 1936 i.error = register_type_mismatch;
891edac4
L		 1937
1938 return 0;
40fb9820
L		 1939}
1940
4c692bc7
JB		 1941static INLINE unsigned int
1942register_number (const reg_entry *r)
1943{
1944 unsigned int nr = r->reg_num;
1945
1946 if (r->reg_flags & RegRex)
1947 nr += 8;
1948
200cbe0f
L		 1949 if (r->reg_flags & RegVRex)
1950 nr += 16;
1951
4c692bc7
JB		 1952 return nr;
1953}
1954
252b5132 1955static INLINE unsigned int
40fb9820 1956mode_from_disp_size (i386_operand_type t)
252b5132 1957{
43234a1e 1958 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1959 return 1;
1960 else if (t.bitfield.disp16
1961 || t.bitfield.disp32
1962 || t.bitfield.disp32s)
1963 return 2;
1964 else
1965 return 0;
252b5132
RH		 1966}
1967
1968static INLINE int
65879393 1969fits_in_signed_byte (addressT num)
252b5132 1970{
65879393 1971 return num + 0x80 <= 0xff;
47926f60 1972}
252b5132
RH		 1973
1974static INLINE int
65879393 1975fits_in_unsigned_byte (addressT num)
252b5132 1976{
65879393 1977 return num <= 0xff;
47926f60 1978}
252b5132
RH		 1979
1980static INLINE int
65879393 1981fits_in_unsigned_word (addressT num)
252b5132 1982{
65879393 1983 return num <= 0xffff;
47926f60 1984}
252b5132
RH		 1985
1986static INLINE int
65879393 1987fits_in_signed_word (addressT num)
252b5132 1988{
65879393 1989 return num + 0x8000 <= 0xffff;
47926f60 1990}
2a962e6d 1991
3e73aa7c 1992static INLINE int
65879393 1993fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1994{
1995#ifndef BFD64
1996 return 1;
1997#else
65879393 1998 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1999#endif
2000} /* fits_in_signed_long() */
2a962e6d 2001
3e73aa7c 2002static INLINE int
65879393 2003fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2004{
2005#ifndef BFD64
2006 return 1;
2007#else
65879393 2008 return num <= 0xffffffff;
3e73aa7c
JH		 2009#endif
2010} /* fits_in_unsigned_long() */
252b5132 2011
43234a1e
L		 2012static INLINE int
2013fits_in_vec_disp8 (offsetT num)
2014{
2015 int shift = i.memshift;
2016 unsigned int mask;
2017
2018 if (shift == -1)
2019 abort ();
2020
2021 mask = (1 << shift) - 1;
2022
2023 /* Return 0 if NUM isn't properly aligned. */
2024 if ((num & mask))
2025 return 0;
2026
2027 /* Check if NUM will fit in 8bit after shift. */
2028 return fits_in_signed_byte (num >> shift);
2029}
2030
a683cc34
SP		 2031static INLINE int
2032fits_in_imm4 (offsetT num)
2033{
2034 return (num & 0xf) == num;
2035}
2036
40fb9820 2037static i386_operand_type
e3bb37b5 2038smallest_imm_type (offsetT num)
252b5132 2039{
40fb9820 2040 i386_operand_type t;
7ab9ffdd 2041
0dfbf9d7 2042 operand_type_set (&t, 0);
40fb9820
L		 2043 t.bitfield.imm64 = 1;
2044
2045 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2046 {
2047 /* This code is disabled on the 486 because all the Imm1 forms
2048 in the opcode table are slower on the i486. They're the
2049 versions with the implicitly specified single-position
2050 displacement, which has another syntax if you really want to
2051 use that form. */
40fb9820
L		 2052 t.bitfield.imm1 = 1;
2053 t.bitfield.imm8 = 1;
2054 t.bitfield.imm8s = 1;
2055 t.bitfield.imm16 = 1;
2056 t.bitfield.imm32 = 1;
2057 t.bitfield.imm32s = 1;
2058 }
2059 else if (fits_in_signed_byte (num))
2060 {
2061 t.bitfield.imm8 = 1;
2062 t.bitfield.imm8s = 1;
2063 t.bitfield.imm16 = 1;
2064 t.bitfield.imm32 = 1;
2065 t.bitfield.imm32s = 1;
2066 }
2067 else if (fits_in_unsigned_byte (num))
2068 {
2069 t.bitfield.imm8 = 1;
2070 t.bitfield.imm16 = 1;
2071 t.bitfield.imm32 = 1;
2072 t.bitfield.imm32s = 1;
2073 }
2074 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2075 {
2076 t.bitfield.imm16 = 1;
2077 t.bitfield.imm32 = 1;
2078 t.bitfield.imm32s = 1;
2079 }
2080 else if (fits_in_signed_long (num))
2081 {
2082 t.bitfield.imm32 = 1;
2083 t.bitfield.imm32s = 1;
2084 }
2085 else if (fits_in_unsigned_long (num))
2086 t.bitfield.imm32 = 1;
2087
2088 return t;
47926f60 2089}
252b5132 2090
847f7ad4 2091static offsetT
e3bb37b5 2092offset_in_range (offsetT val, int size)
847f7ad4 2093{
508866be 2094 addressT mask;
ba2adb93 2095
847f7ad4
AM		 2096 switch (size)
2097 {
508866be
L		 2098 case 1: mask = ((addressT) 1 << 8) - 1; break;
2099 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2100 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2101#ifdef BFD64
2102 case 8: mask = ((addressT) 2 << 63) - 1; break;
2103#endif
47926f60 2104 default: abort ();
847f7ad4
AM		 2105 }
2106
9de868bf
L		 2107#ifdef BFD64
2108 /* If BFD64, sign extend val for 32bit address mode. */
2109 if (flag_code != CODE_64BIT
2110 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2111 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2112 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2113#endif
ba2adb93 2114
47926f60 2115 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2116 {
2117 char buf1[40], buf2[40];
2118
2119 sprint_value (buf1, val);
2120 sprint_value (buf2, val & mask);
2121 as_warn (_("%s shortened to %s"), buf1, buf2);
2122 }
2123 return val & mask;
2124}
2125
c32fa91d
L		 2126enum PREFIX_GROUP
2127{
2128 PREFIX_EXIST = 0,
2129 PREFIX_LOCK,
2130 PREFIX_REP,
2131 PREFIX_OTHER
2132};
2133
2134/* Returns
2135 a. PREFIX_EXIST if attempting to add a prefix where one from the
2136 same class already exists.
2137 b. PREFIX_LOCK if lock prefix is added.
2138 c. PREFIX_REP if rep/repne prefix is added.
2139 d. PREFIX_OTHER if other prefix is added.
2140 */
2141
2142static enum PREFIX_GROUP
e3bb37b5 2143add_prefix (unsigned int prefix)
252b5132 2144{
c32fa91d 2145 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2146 unsigned int q;
252b5132 2147
29b0f896
AM		 2148 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2149 && flag_code == CODE_64BIT)
b1905489 2150 {
161a04f6
L		 2151 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2152 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2153 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2154 ret = PREFIX_EXIST;
b1905489
JB		 2155 q = REX_PREFIX;
2156 }
3e73aa7c 2157 else
b1905489
JB		 2158 {
2159 switch (prefix)
2160 {
2161 default:
2162 abort ();
2163
2164 case CS_PREFIX_OPCODE:
2165 case DS_PREFIX_OPCODE:
2166 case ES_PREFIX_OPCODE:
2167 case FS_PREFIX_OPCODE:
2168 case GS_PREFIX_OPCODE:
2169 case SS_PREFIX_OPCODE:
2170 q = SEG_PREFIX;
2171 break;
2172
2173 case REPNE_PREFIX_OPCODE:
2174 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2175 q = REP_PREFIX;
2176 ret = PREFIX_REP;
2177 break;
2178
b1905489 2179 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2180 q = LOCK_PREFIX;
2181 ret = PREFIX_LOCK;
b1905489
JB		 2182 break;
2183
2184 case FWAIT_OPCODE:
2185 q = WAIT_PREFIX;
2186 break;
2187
2188 case ADDR_PREFIX_OPCODE:
2189 q = ADDR_PREFIX;
2190 break;
2191
2192 case DATA_PREFIX_OPCODE:
2193 q = DATA_PREFIX;
2194 break;
2195 }
2196 if (i.prefix[q] != 0)
c32fa91d 2197 ret = PREFIX_EXIST;
b1905489 2198 }
252b5132 2199
b1905489 2200 if (ret)
252b5132 2201 {
b1905489
JB		 2202 if (!i.prefix[q])
2203 ++i.prefixes;
2204 i.prefix[q] |= prefix;
252b5132 2205 }
b1905489
JB		 2206 else
2207 as_bad (_("same type of prefix used twice"));
252b5132 2208
252b5132
RH		 2209 return ret;
2210}
2211
2212static void
78f12dd3 2213update_code_flag (int value, int check)
eecb386c 2214{
78f12dd3
L		 2215 PRINTF_LIKE ((*as_error));
2216
1e9cc1c2 2217 flag_code = (enum flag_code) value;
40fb9820
L		 2218 if (flag_code == CODE_64BIT)
2219 {
2220 cpu_arch_flags.bitfield.cpu64 = 1;
2221 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2222 }
2223 else
2224 {
2225 cpu_arch_flags.bitfield.cpu64 = 0;
2226 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2227 }
2228 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2229 {
78f12dd3
L		 2230 if (check)
2231 as_error = as_fatal;
2232 else
2233 as_error = as_bad;
2234 (*as_error) (_("64bit mode not supported on `%s'."),
2235 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2236 }
40fb9820 2237 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2238 {
78f12dd3
L		 2239 if (check)
2240 as_error = as_fatal;
2241 else
2242 as_error = as_bad;
2243 (*as_error) (_("32bit mode not supported on `%s'."),
2244 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2245 }
eecb386c
AM		 2246 stackop_size = '\0';
2247}
2248
78f12dd3
L		 2249static void
2250set_code_flag (int value)
2251{
2252 update_code_flag (value, 0);
2253}
2254
eecb386c 2255static void
e3bb37b5 2256set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2257{
1e9cc1c2 2258 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2259 if (flag_code != CODE_16BIT)
2260 abort ();
2261 cpu_arch_flags.bitfield.cpu64 = 0;
2262 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2263 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2264}
2265
2266static void
e3bb37b5 2267set_intel_syntax (int syntax_flag)
252b5132
RH		 2268{
2269 /* Find out if register prefixing is specified. */
2270 int ask_naked_reg = 0;
2271
2272 SKIP_WHITESPACE ();
29b0f896 2273 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2274 {
d02603dc
NC		 2275 char *string;
2276 int e = get_symbol_name (&string);
252b5132 2277
47926f60 2278 if (strcmp (string, "prefix") == 0)
252b5132 2279 ask_naked_reg = 1;
47926f60 2280 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2281 ask_naked_reg = -1;
2282 else
d0b47220 2283 as_bad (_("bad argument to syntax directive."));
d02603dc 2284 (void) restore_line_pointer (e);
252b5132
RH		 2285 }
2286 demand_empty_rest_of_line ();
c3332e24 2287
252b5132
RH		 2288 intel_syntax = syntax_flag;
2289
2290 if (ask_naked_reg == 0)
f86103b7
AM		 2291 allow_naked_reg = (intel_syntax
2292 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2293 else
2294 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2295
ee86248c 2296 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2297
e4a3b5a4 2298 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2299 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2300 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2301}
2302
1efbbeb4
L		 2303static void
2304set_intel_mnemonic (int mnemonic_flag)
2305{
e1d4d893 2306 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2307}
2308
db51cc60
L		 2309static void
2310set_allow_index_reg (int flag)
2311{
2312 allow_index_reg = flag;
2313}
2314
cb19c032 2315static void
7bab8ab5 2316set_check (int what)
cb19c032 2317{
7bab8ab5
JB		 2318 enum check_kind *kind;
2319 const char *str;
2320
2321 if (what)
2322 {
2323 kind = &operand_check;
2324 str = "operand";
2325 }
2326 else
2327 {
2328 kind = &sse_check;
2329 str = "sse";
2330 }
2331
cb19c032
L		 2332 SKIP_WHITESPACE ();
2333
2334 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2335 {
d02603dc
NC		 2336 char *string;
2337 int e = get_symbol_name (&string);
cb19c032
L		 2338
2339 if (strcmp (string, "none") == 0)
7bab8ab5 2340 *kind = check_none;
cb19c032 2341 else if (strcmp (string, "warning") == 0)
7bab8ab5 2342 *kind = check_warning;
cb19c032 2343 else if (strcmp (string, "error") == 0)
7bab8ab5 2344 *kind = check_error;
cb19c032 2345 else
7bab8ab5 2346 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2347 (void) restore_line_pointer (e);
cb19c032
L		 2348 }
2349 else
7bab8ab5 2350 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2351
2352 demand_empty_rest_of_line ();
2353}
2354
8a9036a4
L		 2355static void
2356check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2357 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2358{
2359#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2360 static const char *arch;
2361
2362 /* Intel LIOM is only supported on ELF. */
2363 if (!IS_ELF)
2364 return;
2365
2366 if (!arch)
2367 {
2368 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2369 use default_arch. */
2370 arch = cpu_arch_name;
2371 if (!arch)
2372 arch = default_arch;
2373 }
2374
81486035
L		 2375 /* If we are targeting Intel MCU, we must enable it. */
2376 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2377 || new_flag.bitfield.cpuiamcu)
2378 return;
2379
3632d14b 2380 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2381 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2382 || new_flag.bitfield.cpul1om)
8a9036a4 2383 return;
76ba9986 2384
7a9068fe
L		 2385 /* If we are targeting Intel K1OM, we must enable it. */
2386 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2387 || new_flag.bitfield.cpuk1om)
2388 return;
2389
8a9036a4
L		 2390 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2391#endif
2392}
2393
e413e4e9 2394static void
e3bb37b5 2395set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2396{
47926f60 2397 SKIP_WHITESPACE ();
e413e4e9 2398
29b0f896 2399 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2400 {
d02603dc
NC		 2401 char *string;
2402 int e = get_symbol_name (&string);
91d6fa6a 2403 unsigned int j;
40fb9820 2404 i386_cpu_flags flags;
e413e4e9 2405
91d6fa6a 2406 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2407 {
91d6fa6a 2408 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2409 {
91d6fa6a 2410 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2411
5c6af06e
JB		 2412 if (*string != '.')
2413 {
91d6fa6a 2414 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2415 cpu_sub_arch_name = NULL;
91d6fa6a 2416 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2417 if (flag_code == CODE_64BIT)
2418 {
2419 cpu_arch_flags.bitfield.cpu64 = 1;
2420 cpu_arch_flags.bitfield.cpuno64 = 0;
2421 }
2422 else
2423 {
2424 cpu_arch_flags.bitfield.cpu64 = 0;
2425 cpu_arch_flags.bitfield.cpuno64 = 1;
2426 }
91d6fa6a
NC		 2427 cpu_arch_isa = cpu_arch[j].type;
2428 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2429 if (!cpu_arch_tune_set)
2430 {
2431 cpu_arch_tune = cpu_arch_isa;
2432 cpu_arch_tune_flags = cpu_arch_isa_flags;
2433 }
5c6af06e
JB		 2434 break;
2435 }
40fb9820 2436
293f5f65
L		 2437 flags = cpu_flags_or (cpu_arch_flags,
2438 cpu_arch[j].flags);
81486035 2439
5b64d091 2440 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2441 {
6305a203
L		 2442 if (cpu_sub_arch_name)
2443 {
2444 char *name = cpu_sub_arch_name;
2445 cpu_sub_arch_name = concat (name,
91d6fa6a 2446 cpu_arch[j].name,
1bf57e9f 2447 (const char *) NULL);
6305a203
L		 2448 free (name);
2449 }
2450 else
91d6fa6a 2451 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2452 cpu_arch_flags = flags;
a586129e 2453 cpu_arch_isa_flags = flags;
5c6af06e 2454 }
d02603dc 2455 (void) restore_line_pointer (e);
5c6af06e
JB		 2456 demand_empty_rest_of_line ();
2457 return;
e413e4e9
AM		 2458 }
2459 }
293f5f65
L		 2460
2461 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2462 {
2463 /* Disable an ISA entension. */
2464 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2465 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2466 {
2467 flags = cpu_flags_and_not (cpu_arch_flags,
2468 cpu_noarch[j].flags);
2469 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2470 {
2471 if (cpu_sub_arch_name)
2472 {
2473 char *name = cpu_sub_arch_name;
2474 cpu_sub_arch_name = concat (name, string,
2475 (const char *) NULL);
2476 free (name);
2477 }
2478 else
2479 cpu_sub_arch_name = xstrdup (string);
2480 cpu_arch_flags = flags;
2481 cpu_arch_isa_flags = flags;
2482 }
2483 (void) restore_line_pointer (e);
2484 demand_empty_rest_of_line ();
2485 return;
2486 }
2487
2488 j = ARRAY_SIZE (cpu_arch);
2489 }
2490
91d6fa6a 2491 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2492 as_bad (_("no such architecture: `%s'"), string);
2493
2494 *input_line_pointer = e;
2495 }
2496 else
2497 as_bad (_("missing cpu architecture"));
2498
fddf5b5b
AM		 2499 no_cond_jump_promotion = 0;
2500 if (*input_line_pointer == ','
29b0f896 2501 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2502 {
d02603dc
NC		 2503 char *string;
2504 char e;
2505
2506 ++input_line_pointer;
2507 e = get_symbol_name (&string);
fddf5b5b
AM		 2508
2509 if (strcmp (string, "nojumps") == 0)
2510 no_cond_jump_promotion = 1;
2511 else if (strcmp (string, "jumps") == 0)
2512 ;
2513 else
2514 as_bad (_("no such architecture modifier: `%s'"), string);
2515
d02603dc 2516 (void) restore_line_pointer (e);
fddf5b5b
AM		 2517 }
2518
e413e4e9
AM		 2519 demand_empty_rest_of_line ();
2520}
2521
8a9036a4
L		 2522enum bfd_architecture
2523i386_arch (void)
2524{
3632d14b 2525 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2526 {
2527 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2528 || flag_code != CODE_64BIT)
2529 as_fatal (_("Intel L1OM is 64bit ELF only"));
2530 return bfd_arch_l1om;
2531 }
7a9068fe
L		 2532 else if (cpu_arch_isa == PROCESSOR_K1OM)
2533 {
2534 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2535 || flag_code != CODE_64BIT)
2536 as_fatal (_("Intel K1OM is 64bit ELF only"));
2537 return bfd_arch_k1om;
2538 }
81486035
L		 2539 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2540 {
2541 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2542 || flag_code == CODE_64BIT)
2543 as_fatal (_("Intel MCU is 32bit ELF only"));
2544 return bfd_arch_iamcu;
2545 }
8a9036a4
L		 2546 else
2547 return bfd_arch_i386;
2548}
2549
b9d79e03 2550unsigned long
7016a5d5 2551i386_mach (void)
b9d79e03 2552{
351f65ca 2553 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2554 {
3632d14b 2555 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2556 {
351f65ca
L		 2557 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2558 || default_arch[6] != '\0')
8a9036a4
L		 2559 as_fatal (_("Intel L1OM is 64bit ELF only"));
2560 return bfd_mach_l1om;
2561 }
7a9068fe
L		 2562 else if (cpu_arch_isa == PROCESSOR_K1OM)
2563 {
2564 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2565 || default_arch[6] != '\0')
2566 as_fatal (_("Intel K1OM is 64bit ELF only"));
2567 return bfd_mach_k1om;
2568 }
351f65ca 2569 else if (default_arch[6] == '\0')
8a9036a4 2570 return bfd_mach_x86_64;
351f65ca
L		 2571 else
2572 return bfd_mach_x64_32;
8a9036a4 2573 }
5197d474
L		 2574 else if (!strcmp (default_arch, "i386")
2575 || !strcmp (default_arch, "iamcu"))
81486035
L		 2576 {
2577 if (cpu_arch_isa == PROCESSOR_IAMCU)
2578 {
2579 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2580 as_fatal (_("Intel MCU is 32bit ELF only"));
2581 return bfd_mach_i386_iamcu;
2582 }
2583 else
2584 return bfd_mach_i386_i386;
2585 }
b9d79e03 2586 else
2b5d6a91 2587 as_fatal (_("unknown architecture"));
b9d79e03 2588}
b9d79e03 2589\f
252b5132 2590void
7016a5d5 2591md_begin (void)
252b5132
RH		 2592{
2593 const char *hash_err;
2594
47926f60 2595 /* Initialize op_hash hash table. */
252b5132
RH		 2596 op_hash = hash_new ();
2597
2598 {
d3ce72d0 2599 const insn_template *optab;
29b0f896 2600 templates *core_optab;
252b5132 2601
47926f60
KH		 2602 /* Setup for loop. */
2603 optab = i386_optab;
add39d23 2604 core_optab = XNEW (templates);
252b5132
RH		 2605 core_optab->start = optab;
2606
2607 while (1)
2608 {
2609 ++optab;
2610 if (optab->name == NULL
2611 || strcmp (optab->name, (optab - 1)->name) != 0)
2612 {
2613 /* different name --> ship out current template list;
47926f60 2614 add to hash table; & begin anew. */
252b5132
RH		 2615 core_optab->end = optab;
2616 hash_err = hash_insert (op_hash,
2617 (optab - 1)->name,
5a49b8ac 2618 (void *) core_optab);
252b5132
RH		 2619 if (hash_err)
2620 {
b37df7c4 2621 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2622 (optab - 1)->name,
2623 hash_err);
2624 }
2625 if (optab->name == NULL)
2626 break;
add39d23 2627 core_optab = XNEW (templates);
252b5132
RH		 2628 core_optab->start = optab;
2629 }
2630 }
2631 }
2632
47926f60 2633 /* Initialize reg_hash hash table. */
252b5132
RH		 2634 reg_hash = hash_new ();
2635 {
29b0f896 2636 const reg_entry *regtab;
c3fe08fa 2637 unsigned int regtab_size = i386_regtab_size;
252b5132 2638
c3fe08fa 2639 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2640 {
5a49b8ac 2641 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2642 if (hash_err)
b37df7c4 2643 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2644 regtab->reg_name,
2645 hash_err);
252b5132
RH		 2646 }
2647 }
2648
47926f60 2649 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2650 {
29b0f896
AM		 2651 int c;
2652 char *p;
252b5132
RH		 2653
2654 for (c = 0; c < 256; c++)
2655 {
3882b010 2656 if (ISDIGIT (c))
252b5132
RH		 2657 {
2658 digit_chars[c] = c;
2659 mnemonic_chars[c] = c;
2660 register_chars[c] = c;
2661 operand_chars[c] = c;
2662 }
3882b010 2663 else if (ISLOWER (c))
252b5132
RH		 2664 {
2665 mnemonic_chars[c] = c;
2666 register_chars[c] = c;
2667 operand_chars[c] = c;
2668 }
3882b010 2669 else if (ISUPPER (c))
252b5132 2670 {
3882b010 2671 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2672 register_chars[c] = mnemonic_chars[c];
2673 operand_chars[c] = c;
2674 }
43234a1e
L		 2675 else if (c == '{' || c == '}')
2676 operand_chars[c] = c;
252b5132 2677
3882b010 2678 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2679 identifier_chars[c] = c;
2680 else if (c >= 128)
2681 {
2682 identifier_chars[c] = c;
2683 operand_chars[c] = c;
2684 }
2685 }
2686
2687#ifdef LEX_AT
2688 identifier_chars['@'] = '@';
32137342
NC		 2689#endif
2690#ifdef LEX_QM
2691 identifier_chars['?'] = '?';
2692 operand_chars['?'] = '?';
252b5132 2693#endif
252b5132 2694 digit_chars['-'] = '-';
c0f3af97 2695 mnemonic_chars['_'] = '_';
791fe849 2696 mnemonic_chars['-'] = '-';
0003779b 2697 mnemonic_chars['.'] = '.';
252b5132
RH		 2698 identifier_chars['_'] = '_';
2699 identifier_chars['.'] = '.';
2700
2701 for (p = operand_special_chars; *p != '\0'; p++)
2702 operand_chars[(unsigned char) *p] = *p;
2703 }
2704
a4447b93
RH		 2705 if (flag_code == CODE_64BIT)
2706 {
ca19b261
KT		 2707#if defined (OBJ_COFF) && defined (TE_PE)
2708 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2709 ? 32 : 16);
2710#else
a4447b93 2711 x86_dwarf2_return_column = 16;
ca19b261 2712#endif
61ff971f 2713 x86_cie_data_alignment = -8;
a4447b93
RH		 2714 }
2715 else
2716 {
2717 x86_dwarf2_return_column = 8;
2718 x86_cie_data_alignment = -4;
2719 }
252b5132
RH		 2720}
2721
2722void
e3bb37b5 2723i386_print_statistics (FILE *file)
252b5132
RH		 2724{
2725 hash_print_statistics (file, "i386 opcode", op_hash);
2726 hash_print_statistics (file, "i386 register", reg_hash);
2727}
2728\f
252b5132
RH		 2729#ifdef DEBUG386
2730
ce8a8b2f 2731/* Debugging routines for md_assemble. */
d3ce72d0 2732static void pte (insn_template *);
40fb9820 2733static void pt (i386_operand_type);
e3bb37b5
L		 2734static void pe (expressionS *);
2735static void ps (symbolS *);
252b5132
RH		 2736
2737static void
e3bb37b5 2738pi (char *line, i386_insn *x)
252b5132 2739{
09137c09 2740 unsigned int j;
252b5132
RH		 2741
2742 fprintf (stdout, "%s: template ", line);
2743 pte (&x->tm);
09f131f2
JH		 2744 fprintf (stdout, " address: base %s index %s scale %x\n",
2745 x->base_reg ? x->base_reg->reg_name : "none",
2746 x->index_reg ? x->index_reg->reg_name : "none",
2747 x->log2_scale_factor);
2748 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2749 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2750 fprintf (stdout, " sib: base %x index %x scale %x\n",
2751 x->sib.base, x->sib.index, x->sib.scale);
2752 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2753 (x->rex & REX_W) != 0,
2754 (x->rex & REX_R) != 0,
2755 (x->rex & REX_X) != 0,
2756 (x->rex & REX_B) != 0);
09137c09 2757 for (j = 0; j < x->operands; j++)
252b5132 2758 {
09137c09
SP		 2759 fprintf (stdout, " #%d: ", j + 1);
2760 pt (x->types[j]);
252b5132 2761 fprintf (stdout, "\n");
09137c09
SP		 2762 if (x->types[j].bitfield.reg8
2763 || x->types[j].bitfield.reg16
2764 || x->types[j].bitfield.reg32
2765 || x->types[j].bitfield.reg64
2766 || x->types[j].bitfield.regmmx
2767 || x->types[j].bitfield.regxmm
2768 || x->types[j].bitfield.regymm
43234a1e 2769 || x->types[j].bitfield.regzmm
09137c09
SP		 2770 || x->types[j].bitfield.sreg2
2771 || x->types[j].bitfield.sreg3
2772 || x->types[j].bitfield.control
2773 || x->types[j].bitfield.debug
2774 || x->types[j].bitfield.test)
2775 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2776 if (operand_type_check (x->types[j], imm))
2777 pe (x->op[j].imms);
2778 if (operand_type_check (x->types[j], disp))
2779 pe (x->op[j].disps);
252b5132
RH		 2780 }
2781}
2782
2783static void
d3ce72d0 2784pte (insn_template *t)
252b5132 2785{
09137c09 2786 unsigned int j;
252b5132 2787 fprintf (stdout, " %d operands ", t->operands);
47926f60 2788 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2789 if (t->extension_opcode != None)
2790 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2791 if (t->opcode_modifier.d)
252b5132 2792 fprintf (stdout, "D");
40fb9820 2793 if (t->opcode_modifier.w)
252b5132
RH		 2794 fprintf (stdout, "W");
2795 fprintf (stdout, "\n");
09137c09 2796 for (j = 0; j < t->operands; j++)
252b5132 2797 {
09137c09
SP		 2798 fprintf (stdout, " #%d type ", j + 1);
2799 pt (t->operand_types[j]);
252b5132
RH		 2800 fprintf (stdout, "\n");
2801 }
2802}
2803
2804static void
e3bb37b5 2805pe (expressionS *e)
252b5132 2806{
24eab124 2807 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2808 fprintf (stdout, " add_number %ld (%lx)\n",
2809 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2810 if (e->X_add_symbol)
2811 {
2812 fprintf (stdout, " add_symbol ");
2813 ps (e->X_add_symbol);
2814 fprintf (stdout, "\n");
2815 }
2816 if (e->X_op_symbol)
2817 {
2818 fprintf (stdout, " op_symbol ");
2819 ps (e->X_op_symbol);
2820 fprintf (stdout, "\n");
2821 }
2822}
2823
2824static void
e3bb37b5 2825ps (symbolS *s)
252b5132
RH		 2826{
2827 fprintf (stdout, "%s type %s%s",
2828 S_GET_NAME (s),
2829 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2830 segment_name (S_GET_SEGMENT (s)));
2831}
2832
7b81dfbb 2833static struct type_name
252b5132 2834 {
40fb9820
L		 2835 i386_operand_type mask;
2836 const char *name;
252b5132 2837 }
7b81dfbb 2838const type_names[] =
252b5132 2839{
40fb9820
L		 2840 { OPERAND_TYPE_REG8, "r8" },
2841 { OPERAND_TYPE_REG16, "r16" },
2842 { OPERAND_TYPE_REG32, "r32" },
2843 { OPERAND_TYPE_REG64, "r64" },
2844 { OPERAND_TYPE_IMM8, "i8" },
2845 { OPERAND_TYPE_IMM8, "i8s" },
2846 { OPERAND_TYPE_IMM16, "i16" },
2847 { OPERAND_TYPE_IMM32, "i32" },
2848 { OPERAND_TYPE_IMM32S, "i32s" },
2849 { OPERAND_TYPE_IMM64, "i64" },
2850 { OPERAND_TYPE_IMM1, "i1" },
2851 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2852 { OPERAND_TYPE_DISP8, "d8" },
2853 { OPERAND_TYPE_DISP16, "d16" },
2854 { OPERAND_TYPE_DISP32, "d32" },
2855 { OPERAND_TYPE_DISP32S, "d32s" },
2856 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2857 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2858 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2859 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2860 { OPERAND_TYPE_CONTROL, "control reg" },
2861 { OPERAND_TYPE_TEST, "test reg" },
2862 { OPERAND_TYPE_DEBUG, "debug reg" },
2863 { OPERAND_TYPE_FLOATREG, "FReg" },
2864 { OPERAND_TYPE_FLOATACC, "FAcc" },
2865 { OPERAND_TYPE_SREG2, "SReg2" },
2866 { OPERAND_TYPE_SREG3, "SReg3" },
2867 { OPERAND_TYPE_ACC, "Acc" },
2868 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2869 { OPERAND_TYPE_REGMMX, "rMMX" },
2870 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2871 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2872 { OPERAND_TYPE_REGZMM, "rZMM" },
2873 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2874 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2875};
2876
2877static void
40fb9820 2878pt (i386_operand_type t)
252b5132 2879{
40fb9820 2880 unsigned int j;
c6fb90c8 2881 i386_operand_type a;
252b5132 2882
40fb9820 2883 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2884 {
2885 a = operand_type_and (t, type_names[j].mask);
0349dc08 2886 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2887 fprintf (stdout, "%s, ", type_names[j].name);
2888 }
252b5132
RH		 2889 fflush (stdout);
2890}
2891
2892#endif /* DEBUG386 */
2893\f
252b5132 2894static bfd_reloc_code_real_type
3956db08 2895reloc (unsigned int size,
64e74474
AM		 2896 int pcrel,
2897 int sign,
2898 bfd_reloc_code_real_type other)
252b5132 2899{
47926f60 2900 if (other != NO_RELOC)
3956db08 2901 {
91d6fa6a 2902 reloc_howto_type *rel;
3956db08
JB		 2903
2904 if (size == 8)
2905 switch (other)
2906 {
64e74474
AM		 2907 case BFD_RELOC_X86_64_GOT32:
2908 return BFD_RELOC_X86_64_GOT64;
2909 break;
553d1284
L		 2910 case BFD_RELOC_X86_64_GOTPLT64:
2911 return BFD_RELOC_X86_64_GOTPLT64;
2912 break;
64e74474
AM		 2913 case BFD_RELOC_X86_64_PLTOFF64:
2914 return BFD_RELOC_X86_64_PLTOFF64;
2915 break;
2916 case BFD_RELOC_X86_64_GOTPC32:
2917 other = BFD_RELOC_X86_64_GOTPC64;
2918 break;
2919 case BFD_RELOC_X86_64_GOTPCREL:
2920 other = BFD_RELOC_X86_64_GOTPCREL64;
2921 break;
2922 case BFD_RELOC_X86_64_TPOFF32:
2923 other = BFD_RELOC_X86_64_TPOFF64;
2924 break;
2925 case BFD_RELOC_X86_64_DTPOFF32:
2926 other = BFD_RELOC_X86_64_DTPOFF64;
2927 break;
2928 default:
2929 break;
3956db08 2930 }
e05278af 2931
8ce3d284 2932#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2933 if (other == BFD_RELOC_SIZE32)
2934 {
2935 if (size == 8)
1ab668bf 2936 other = BFD_RELOC_SIZE64;
8fd4256d 2937 if (pcrel)
1ab668bf
AM		 2938 {
2939 as_bad (_("there are no pc-relative size relocations"));
2940 return NO_RELOC;
2941 }
8fd4256d 2942 }
8ce3d284 2943#endif
8fd4256d 2944
e05278af 2945 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2946 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2947 sign = -1;
2948
91d6fa6a
NC		 2949 rel = bfd_reloc_type_lookup (stdoutput, other);
2950 if (!rel)
3956db08 2951 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2952 else if (size != bfd_get_reloc_size (rel))
3956db08 2953 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2954 bfd_get_reloc_size (rel),
3956db08 2955 size);
91d6fa6a 2956 else if (pcrel && !rel->pc_relative)
3956db08 2957 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2958 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2959 && !sign)
91d6fa6a 2960 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2961 && sign > 0))
3956db08
JB		 2962 as_bad (_("relocated field and relocation type differ in signedness"));
2963 else
2964 return other;
2965 return NO_RELOC;
2966 }
252b5132
RH		 2967
2968 if (pcrel)
2969 {
3e73aa7c 2970 if (!sign)
3956db08 2971 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2972 switch (size)
2973 {
2974 case 1: return BFD_RELOC_8_PCREL;
2975 case 2: return BFD_RELOC_16_PCREL;
d258b828 2976 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2977 case 8: return BFD_RELOC_64_PCREL;
252b5132 2978 }
3956db08 2979 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2980 }
2981 else
2982 {
3956db08 2983 if (sign > 0)
e5cb08ac 2984 switch (size)
3e73aa7c
JH		 2985 {
2986 case 4: return BFD_RELOC_X86_64_32S;
2987 }
2988 else
2989 switch (size)
2990 {
2991 case 1: return BFD_RELOC_8;
2992 case 2: return BFD_RELOC_16;
2993 case 4: return BFD_RELOC_32;
2994 case 8: return BFD_RELOC_64;
2995 }
3956db08
JB		 2996 as_bad (_("cannot do %s %u byte relocation"),
2997 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2998 }
2999
0cc9e1d3 3000 return NO_RELOC;
252b5132
RH		 3001}
3002
47926f60
KH		 3003/* Here we decide which fixups can be adjusted to make them relative to
3004 the beginning of the section instead of the symbol. Basically we need
3005 to make sure that the dynamic relocations are done correctly, so in
3006 some cases we force the original symbol to be used. */
3007
252b5132 3008int
e3bb37b5 3009tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3010{
6d249963 3011#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3012 if (!IS_ELF)
31312f95
AM		 3013 return 1;
3014
a161fe53
AM		 3015 /* Don't adjust pc-relative references to merge sections in 64-bit
3016 mode. */
3017 if (use_rela_relocations
3018 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3019 && fixP->fx_pcrel)
252b5132 3020 return 0;
31312f95 3021
8d01d9a9
AJ		 3022 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3023 and changed later by validate_fix. */
3024 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3025 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3026 return 0;
3027
8fd4256d
L		 3028 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3029 for size relocations. */
3030 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3031 || fixP->fx_r_type == BFD_RELOC_SIZE64
3032 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3033 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3034 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3035 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3036 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3037 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3038 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3039 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3040 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3041 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3042 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3043 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3044 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3045 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3046 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3047 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3048 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3049 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3050 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3051 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3052 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3053 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3054 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3055 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3056 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3057 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3058 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3059 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3060 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3061 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3062 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3063 return 0;
31312f95 3064#endif
252b5132
RH		 3065 return 1;
3066}
252b5132 3067
b4cac588 3068static int
e3bb37b5 3069intel_float_operand (const char *mnemonic)
252b5132 3070{
9306ca4a
JB		 3071 /* Note that the value returned is meaningful only for opcodes with (memory)
3072 operands, hence the code here is free to improperly handle opcodes that
3073 have no operands (for better performance and smaller code). */
3074
3075 if (mnemonic[0] != 'f')
3076 return 0; /* non-math */
3077
3078 switch (mnemonic[1])
3079 {
3080 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3081 the fs segment override prefix not currently handled because no
3082 call path can make opcodes without operands get here */
3083 case 'i':
3084 return 2 /* integer op */;
3085 case 'l':
3086 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3087 return 3; /* fldcw/fldenv */
3088 break;
3089 case 'n':
3090 if (mnemonic[2] != 'o' /* fnop */)
3091 return 3; /* non-waiting control op */
3092 break;
3093 case 'r':
3094 if (mnemonic[2] == 's')
3095 return 3; /* frstor/frstpm */
3096 break;
3097 case 's':
3098 if (mnemonic[2] == 'a')
3099 return 3; /* fsave */
3100 if (mnemonic[2] == 't')
3101 {
3102 switch (mnemonic[3])
3103 {
3104 case 'c': /* fstcw */
3105 case 'd': /* fstdw */
3106 case 'e': /* fstenv */
3107 case 's': /* fsts[gw] */
3108 return 3;
3109 }
3110 }
3111 break;
3112 case 'x':
3113 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3114 return 0; /* fxsave/fxrstor are not really math ops */
3115 break;
3116 }
252b5132 3117
9306ca4a 3118 return 1;
252b5132
RH		 3119}
3120
c0f3af97
L		 3121/* Build the VEX prefix. */
3122
3123static void
d3ce72d0 3124build_vex_prefix (const insn_template *t)
c0f3af97
L		 3125{
3126 unsigned int register_specifier;
3127 unsigned int implied_prefix;
3128 unsigned int vector_length;
3129
3130 /* Check register specifier. */
3131 if (i.vex.register_specifier)
43234a1e
L		 3132 {
3133 register_specifier =
3134 ~register_number (i.vex.register_specifier) & 0xf;
3135 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3136 }
c0f3af97
L		 3137 else
3138 register_specifier = 0xf;
3139
fa99fab2
L		 3140 /* Use 2-byte VEX prefix by swappping destination and source
3141 operand. */
3142 if (!i.swap_operand
3143 && i.operands == i.reg_operands
7f399153 3144 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3145 && i.tm.opcode_modifier.s
3146 && i.rex == REX_B)
3147 {
3148 unsigned int xchg = i.operands - 1;
3149 union i386_op temp_op;
3150 i386_operand_type temp_type;
3151
3152 temp_type = i.types[xchg];
3153 i.types[xchg] = i.types[0];
3154 i.types[0] = temp_type;
3155 temp_op = i.op[xchg];
3156 i.op[xchg] = i.op[0];
3157 i.op[0] = temp_op;
3158
9c2799c2 3159 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3160
3161 i.rex = REX_R;
3162 xchg = i.rm.regmem;
3163 i.rm.regmem = i.rm.reg;
3164 i.rm.reg = xchg;
3165
3166 /* Use the next insn. */
3167 i.tm = t[1];
3168 }
3169
539f890d
L		 3170 if (i.tm.opcode_modifier.vex == VEXScalar)
3171 vector_length = avxscalar;
3172 else
3173 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3174
3175 switch ((i.tm.base_opcode >> 8) & 0xff)
3176 {
3177 case 0:
3178 implied_prefix = 0;
3179 break;
3180 case DATA_PREFIX_OPCODE:
3181 implied_prefix = 1;
3182 break;
3183 case REPE_PREFIX_OPCODE:
3184 implied_prefix = 2;
3185 break;
3186 case REPNE_PREFIX_OPCODE:
3187 implied_prefix = 3;
3188 break;
3189 default:
3190 abort ();
3191 }
3192
3193 /* Use 2-byte VEX prefix if possible. */
7f399153 3194 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3195 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3196 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3197 {
3198 /* 2-byte VEX prefix. */
3199 unsigned int r;
3200
3201 i.vex.length = 2;
3202 i.vex.bytes[0] = 0xc5;
3203
3204 /* Check the REX.R bit. */
3205 r = (i.rex & REX_R) ? 0 : 1;
3206 i.vex.bytes[1] = (r << 7
3207 | register_specifier << 3
3208 | vector_length << 2
3209 | implied_prefix);
3210 }
3211 else
3212 {
3213 /* 3-byte VEX prefix. */
3214 unsigned int m, w;
3215
f88c9eb0 3216 i.vex.length = 3;
f88c9eb0 3217
7f399153 3218 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3219 {
7f399153
L		 3220 case VEX0F:
3221 m = 0x1;
80de6e00 3222 i.vex.bytes[0] = 0xc4;
7f399153
L		 3223 break;
3224 case VEX0F38:
3225 m = 0x2;
80de6e00 3226 i.vex.bytes[0] = 0xc4;
7f399153
L		 3227 break;
3228 case VEX0F3A:
3229 m = 0x3;
80de6e00 3230 i.vex.bytes[0] = 0xc4;
7f399153
L		 3231 break;
3232 case XOP08:
5dd85c99
SP		 3233 m = 0x8;
3234 i.vex.bytes[0] = 0x8f;
7f399153
L		 3235 break;
3236 case XOP09:
f88c9eb0
SP		 3237 m = 0x9;
3238 i.vex.bytes[0] = 0x8f;
7f399153
L		 3239 break;
3240 case XOP0A:
f88c9eb0
SP		 3241 m = 0xa;
3242 i.vex.bytes[0] = 0x8f;
7f399153
L		 3243 break;
3244 default:
3245 abort ();
f88c9eb0 3246 }
c0f3af97 3247
c0f3af97
L		 3248 /* The high 3 bits of the second VEX byte are 1's compliment
3249 of RXB bits from REX. */
3250 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3251
3252 /* Check the REX.W bit. */
3253 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3254 if (i.tm.opcode_modifier.vexw == VEXW1)
3255 w = 1;
c0f3af97
L		 3256
3257 i.vex.bytes[2] = (w << 7
3258 | register_specifier << 3
3259 | vector_length << 2
3260 | implied_prefix);
3261 }
3262}
3263
43234a1e
L		 3264/* Build the EVEX prefix. */
3265
3266static void
3267build_evex_prefix (void)
3268{
3269 unsigned int register_specifier;
3270 unsigned int implied_prefix;
3271 unsigned int m, w;
3272 rex_byte vrex_used = 0;
3273
3274 /* Check register specifier. */
3275 if (i.vex.register_specifier)
3276 {
3277 gas_assert ((i.vrex & REX_X) == 0);
3278
3279 register_specifier = i.vex.register_specifier->reg_num;
3280 if ((i.vex.register_specifier->reg_flags & RegRex))
3281 register_specifier += 8;
3282 /* The upper 16 registers are encoded in the fourth byte of the
3283 EVEX prefix. */
3284 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3285 i.vex.bytes[3] = 0x8;
3286 register_specifier = ~register_specifier & 0xf;
3287 }
3288 else
3289 {
3290 register_specifier = 0xf;
3291
3292 /* Encode upper 16 vector index register in the fourth byte of
3293 the EVEX prefix. */
3294 if (!(i.vrex & REX_X))
3295 i.vex.bytes[3] = 0x8;
3296 else
3297 vrex_used |= REX_X;
3298 }
3299
3300 switch ((i.tm.base_opcode >> 8) & 0xff)
3301 {
3302 case 0:
3303 implied_prefix = 0;
3304 break;
3305 case DATA_PREFIX_OPCODE:
3306 implied_prefix = 1;
3307 break;
3308 case REPE_PREFIX_OPCODE:
3309 implied_prefix = 2;
3310 break;
3311 case REPNE_PREFIX_OPCODE:
3312 implied_prefix = 3;
3313 break;
3314 default:
3315 abort ();
3316 }
3317
3318 /* 4 byte EVEX prefix. */
3319 i.vex.length = 4;
3320 i.vex.bytes[0] = 0x62;
3321
3322 /* mmmm bits. */
3323 switch (i.tm.opcode_modifier.vexopcode)
3324 {
3325 case VEX0F:
3326 m = 1;
3327 break;
3328 case VEX0F38:
3329 m = 2;
3330 break;
3331 case VEX0F3A:
3332 m = 3;
3333 break;
3334 default:
3335 abort ();
3336 break;
3337 }
3338
3339 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3340 bits from REX. */
3341 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3342
3343 /* The fifth bit of the second EVEX byte is 1's compliment of the
3344 REX_R bit in VREX. */
3345 if (!(i.vrex & REX_R))
3346 i.vex.bytes[1] |= 0x10;
3347 else
3348 vrex_used |= REX_R;
3349
3350 if ((i.reg_operands + i.imm_operands) == i.operands)
3351 {
3352 /* When all operands are registers, the REX_X bit in REX is not
3353 used. We reuse it to encode the upper 16 registers, which is
3354 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3355 as 1's compliment. */
3356 if ((i.vrex & REX_B))
3357 {
3358 vrex_used |= REX_B;
3359 i.vex.bytes[1] &= ~0x40;
3360 }
3361 }
3362
3363 /* EVEX instructions shouldn't need the REX prefix. */
3364 i.vrex &= ~vrex_used;
3365 gas_assert (i.vrex == 0);
3366
3367 /* Check the REX.W bit. */
3368 w = (i.rex & REX_W) ? 1 : 0;
3369 if (i.tm.opcode_modifier.vexw)
3370 {
3371 if (i.tm.opcode_modifier.vexw == VEXW1)
3372 w = 1;
3373 }
3374 /* If w is not set it means we are dealing with WIG instruction. */
3375 else if (!w)
3376 {
3377 if (evexwig == evexw1)
3378 w = 1;
3379 }
3380
3381 /* Encode the U bit. */
3382 implied_prefix |= 0x4;
3383
3384 /* The third byte of the EVEX prefix. */
3385 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3386
3387 /* The fourth byte of the EVEX prefix. */
3388 /* The zeroing-masking bit. */
3389 if (i.mask && i.mask->zeroing)
3390 i.vex.bytes[3] |= 0x80;
3391
3392 /* Don't always set the broadcast bit if there is no RC. */
3393 if (!i.rounding)
3394 {
3395 /* Encode the vector length. */
3396 unsigned int vec_length;
3397
3398 switch (i.tm.opcode_modifier.evex)
3399 {
3400 case EVEXLIG: /* LL' is ignored */
3401 vec_length = evexlig << 5;
3402 break;
3403 case EVEX128:
3404 vec_length = 0 << 5;
3405 break;
3406 case EVEX256:
3407 vec_length = 1 << 5;
3408 break;
3409 case EVEX512:
3410 vec_length = 2 << 5;
3411 break;
3412 default:
3413 abort ();
3414 break;
3415 }
3416 i.vex.bytes[3] |= vec_length;
3417 /* Encode the broadcast bit. */
3418 if (i.broadcast)
3419 i.vex.bytes[3] |= 0x10;
3420 }
3421 else
3422 {
3423 if (i.rounding->type != saeonly)
3424 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3425 else
d3d3c6db 3426 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3427 }
3428
3429 if (i.mask && i.mask->mask)
3430 i.vex.bytes[3] |= i.mask->mask->reg_num;
3431}
3432
65da13b5
L		 3433static void
3434process_immext (void)
3435{
3436 expressionS *exp;
3437
4c692bc7
JB		 3438 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3439 && i.operands > 0)
65da13b5 3440 {
4c692bc7
JB		 3441 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3442 with an opcode suffix which is coded in the same place as an
3443 8-bit immediate field would be.
3444 Here we check those operands and remove them afterwards. */
65da13b5
L		 3445 unsigned int x;
3446
3447 for (x = 0; x < i.operands; x++)
4c692bc7 3448 if (register_number (i.op[x].regs) != x)
65da13b5 3449 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3450 register_prefix, i.op[x].regs->reg_name, x + 1,
3451 i.tm.name);
3452
3453 i.operands = 0;
65da13b5
L		 3454 }
3455
9916071f
AP		 3456 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3457 {
3458 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3459 suffix which is coded in the same place as an 8-bit immediate
3460 field would be.
3461 Here we check those operands and remove them afterwards. */
3462 unsigned int x;
3463
3464 if (i.operands != 3)
3465 abort();
3466
3467 for (x = 0; x < 2; x++)
3468 if (register_number (i.op[x].regs) != x)
3469 goto bad_register_operand;
3470
3471 /* Check for third operand for mwaitx/monitorx insn. */
3472 if (register_number (i.op[x].regs)
3473 != (x + (i.tm.extension_opcode == 0xfb)))
3474 {
3475bad_register_operand:
3476 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3477 register_prefix, i.op[x].regs->reg_name, x+1,
3478 i.tm.name);
3479 }
3480
3481 i.operands = 0;
3482 }
3483
c0f3af97 3484 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3485 which is coded in the same place as an 8-bit immediate field
3486 would be. Here we fake an 8-bit immediate operand from the
3487 opcode suffix stored in tm.extension_opcode.
3488
c1e679ec 3489 AVX instructions also use this encoding, for some of
c0f3af97 3490 3 argument instructions. */
65da13b5 3491
43234a1e 3492 gas_assert (i.imm_operands <= 1
7ab9ffdd 3493 && (i.operands <= 2
43234a1e
L		 3494 || ((i.tm.opcode_modifier.vex
3495 || i.tm.opcode_modifier.evex)
7ab9ffdd 3496 && i.operands <= 4)));
65da13b5
L		 3497
3498 exp = &im_expressions[i.imm_operands++];
3499 i.op[i.operands].imms = exp;
3500 i.types[i.operands] = imm8;
3501 i.operands++;
3502 exp->X_op = O_constant;
3503 exp->X_add_number = i.tm.extension_opcode;
3504 i.tm.extension_opcode = None;
3505}
3506
42164a71
L		 3507
3508static int
3509check_hle (void)
3510{
3511 switch (i.tm.opcode_modifier.hleprefixok)
3512 {
3513 default:
3514 abort ();
82c2def5 3515 case HLEPrefixNone:
165de32a
L		 3516 as_bad (_("invalid instruction `%s' after `%s'"),
3517 i.tm.name, i.hle_prefix);
42164a71 3518 return 0;
82c2def5 3519 case HLEPrefixLock:
42164a71
L		 3520 if (i.prefix[LOCK_PREFIX])
3521 return 1;
165de32a 3522 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3523 return 0;
82c2def5 3524 case HLEPrefixAny:
42164a71 3525 return 1;
82c2def5 3526 case HLEPrefixRelease:
42164a71
L		 3527 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3528 {
3529 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3530 i.tm.name);
3531 return 0;
3532 }
3533 if (i.mem_operands == 0
3534 || !operand_type_check (i.types[i.operands - 1], anymem))
3535 {
3536 as_bad (_("memory destination needed for instruction `%s'"
3537 " after `xrelease'"), i.tm.name);
3538 return 0;
3539 }
3540 return 1;
3541 }
3542}
3543
252b5132
RH		 3544/* This is the guts of the machine-dependent assembler. LINE points to a
3545 machine dependent instruction. This function is supposed to emit
3546 the frags/bytes it assembles to. */
3547
3548void
65da13b5 3549md_assemble (char *line)
252b5132 3550{
40fb9820 3551 unsigned int j;
83b16ac6 3552 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3553 const insn_template *t;
252b5132 3554
47926f60 3555 /* Initialize globals. */
252b5132
RH		 3556 memset (&i, '\0', sizeof (i));
3557 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3558 i.reloc[j] = NO_RELOC;
252b5132
RH		 3559 memset (disp_expressions, '\0', sizeof (disp_expressions));
3560 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3561 save_stack_p = save_stack;
252b5132
RH		 3562
3563 /* First parse an instruction mnemonic & call i386_operand for the operands.
3564 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3565 start of a (possibly prefixed) mnemonic. */
252b5132 3566
29b0f896
AM		 3567 line = parse_insn (line, mnemonic);
3568 if (line == NULL)
3569 return;
83b16ac6 3570 mnem_suffix = i.suffix;
252b5132 3571
29b0f896 3572 line = parse_operands (line, mnemonic);
ee86248c 3573 this_operand = -1;
8325cc63
JB		 3574 xfree (i.memop1_string);
3575 i.memop1_string = NULL;
29b0f896
AM		 3576 if (line == NULL)
3577 return;
252b5132 3578
29b0f896
AM		 3579 /* Now we've parsed the mnemonic into a set of templates, and have the
3580 operands at hand. */
3581
3582 /* All intel opcodes have reversed operands except for "bound" and
3583 "enter". We also don't reverse intersegment "jmp" and "call"
3584 instructions with 2 immediate operands so that the immediate segment
050dfa73 3585 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3586 if (intel_syntax
3587 && i.operands > 1
29b0f896 3588 && (strcmp (mnemonic, "bound") != 0)
30123838 3589 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3590 && !(operand_type_check (i.types[0], imm)
3591 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3592 swap_operands ();
3593
ec56d5c0
JB		 3594 /* The order of the immediates should be reversed
3595 for 2 immediates extrq and insertq instructions */
3596 if (i.imm_operands == 2
3597 && (strcmp (mnemonic, "extrq") == 0
3598 || strcmp (mnemonic, "insertq") == 0))
3599 swap_2_operands (0, 1);
3600
29b0f896
AM		 3601 if (i.imm_operands)
3602 optimize_imm ();
3603
b300c311
L		 3604 /* Don't optimize displacement for movabs since it only takes 64bit
3605 displacement. */
3606 if (i.disp_operands
a501d77e 3607 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3608 && (flag_code != CODE_64BIT
3609 || strcmp (mnemonic, "movabs") != 0))
3610 optimize_disp ();
29b0f896
AM		 3611
3612 /* Next, we find a template that matches the given insn,
3613 making sure the overlap of the given operands types is consistent
3614 with the template operand types. */
252b5132 3615
83b16ac6 3616 if (!(t = match_template (mnem_suffix)))
29b0f896 3617 return;
252b5132 3618
7bab8ab5 3619 if (sse_check != check_none
81f8a913 3620 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3621 && (i.tm.cpu_flags.bitfield.cpusse
3622 || i.tm.cpu_flags.bitfield.cpusse2
3623 || i.tm.cpu_flags.bitfield.cpusse3
3624 || i.tm.cpu_flags.bitfield.cpussse3
3625 || i.tm.cpu_flags.bitfield.cpusse4_1
3626 || i.tm.cpu_flags.bitfield.cpusse4_2))
3627 {
7bab8ab5 3628 (sse_check == check_warning
daf50ae7
L		 3629 ? as_warn
3630 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3631 }
3632
321fd21e
L		 3633 /* Zap movzx and movsx suffix. The suffix has been set from
3634 "word ptr" or "byte ptr" on the source operand in Intel syntax
3635 or extracted from mnemonic in AT&T syntax. But we'll use
3636 the destination register to choose the suffix for encoding. */
3637 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3638 {
321fd21e
L		 3639 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3640 there is no suffix, the default will be byte extension. */
3641 if (i.reg_operands != 2
3642 && !i.suffix
7ab9ffdd 3643 && intel_syntax)
321fd21e
L		 3644 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3645
3646 i.suffix = 0;
cd61ebfe 3647 }
24eab124 3648
40fb9820 3649 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3650 if (!add_prefix (FWAIT_OPCODE))
3651 return;
252b5132 3652
d5de92cf
L		 3653 /* Check if REP prefix is OK. */
3654 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3655 {
3656 as_bad (_("invalid instruction `%s' after `%s'"),
3657 i.tm.name, i.rep_prefix);
3658 return;
3659 }
3660
c1ba0266
L		 3661 /* Check for lock without a lockable instruction. Destination operand
3662 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3663 if (i.prefix[LOCK_PREFIX]
3664 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3665 || i.mem_operands == 0
3666 || (i.tm.base_opcode != 0x86
3667 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3668 {
3669 as_bad (_("expecting lockable instruction after `lock'"));
3670 return;
3671 }
3672
42164a71 3673 /* Check if HLE prefix is OK. */
165de32a 3674 if (i.hle_prefix && !check_hle ())
42164a71
L		 3675 return;
3676
7e8b059b
L		 3677 /* Check BND prefix. */
3678 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3679 as_bad (_("expecting valid branch instruction after `bnd'"));
3680
327e8c42
JB		 3681 if (i.tm.cpu_flags.bitfield.cpumpx)
3682 {
3683 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3684 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3685 else if (flag_code != CODE_16BIT
3686 ? i.prefix[ADDR_PREFIX]
3687 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3688 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3689 }
7e8b059b
L		 3690
3691 /* Insert BND prefix. */
3692 if (add_bnd_prefix
3693 && i.tm.opcode_modifier.bndprefixok
3694 && !i.prefix[BND_PREFIX])
3695 add_prefix (BND_PREFIX_OPCODE);
3696
29b0f896 3697 /* Check string instruction segment overrides. */
40fb9820 3698 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3699 {
3700 if (!check_string ())
5dd0794d 3701 return;
fc0763e6 3702 i.disp_operands = 0;
29b0f896 3703 }
5dd0794d 3704
29b0f896
AM		 3705 if (!process_suffix ())
3706 return;
e413e4e9 3707
bc0844ae
L		 3708 /* Update operand types. */
3709 for (j = 0; j < i.operands; j++)
3710 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3711
29b0f896
AM		 3712 /* Make still unresolved immediate matches conform to size of immediate
3713 given in i.suffix. */
3714 if (!finalize_imm ())
3715 return;
252b5132 3716
40fb9820 3717 if (i.types[0].bitfield.imm1)
29b0f896 3718 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3719
9afe6eb8
L		 3720 /* We only need to check those implicit registers for instructions
3721 with 3 operands or less. */
3722 if (i.operands <= 3)
3723 for (j = 0; j < i.operands; j++)
3724 if (i.types[j].bitfield.inoutportreg
3725 || i.types[j].bitfield.shiftcount
3726 || i.types[j].bitfield.acc
3727 || i.types[j].bitfield.floatacc)
3728 i.reg_operands--;
40fb9820 3729
c0f3af97
L		 3730 /* ImmExt should be processed after SSE2AVX. */
3731 if (!i.tm.opcode_modifier.sse2avx
3732 && i.tm.opcode_modifier.immext)
65da13b5 3733 process_immext ();
252b5132 3734
29b0f896
AM		 3735 /* For insns with operands there are more diddles to do to the opcode. */
3736 if (i.operands)
3737 {
3738 if (!process_operands ())
3739 return;
3740 }
40fb9820 3741 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3742 {
3743 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3744 as_warn (_("translating to `%sp'"), i.tm.name);
3745 }
252b5132 3746
9e5e5283
L		 3747 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3748 {
3749 if (flag_code == CODE_16BIT)
3750 {
3751 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3752 i.tm.name);
3753 return;
3754 }
c0f3af97 3755
9e5e5283
L		 3756 if (i.tm.opcode_modifier.vex)
3757 build_vex_prefix (t);
3758 else
3759 build_evex_prefix ();
3760 }
43234a1e 3761
5dd85c99
SP		 3762 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3763 instructions may define INT_OPCODE as well, so avoid this corner
3764 case for those instructions that use MODRM. */
3765 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3766 && !i.tm.opcode_modifier.modrm
3767 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3768 {
3769 i.tm.base_opcode = INT3_OPCODE;
3770 i.imm_operands = 0;
3771 }
252b5132 3772
40fb9820
L		 3773 if ((i.tm.opcode_modifier.jump
3774 || i.tm.opcode_modifier.jumpbyte
3775 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3776 && i.op[0].disps->X_op == O_constant)
3777 {
3778 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3779 the absolute address given by the constant. Since ix86 jumps and
3780 calls are pc relative, we need to generate a reloc. */
3781 i.op[0].disps->X_add_symbol = &abs_symbol;
3782 i.op[0].disps->X_op = O_symbol;
3783 }
252b5132 3784
40fb9820 3785 if (i.tm.opcode_modifier.rex64)
161a04f6 3786 i.rex |= REX_W;
252b5132 3787
29b0f896
AM		 3788 /* For 8 bit registers we need an empty rex prefix. Also if the
3789 instruction already has a prefix, we need to convert old
3790 registers to new ones. */
773f551c 3791
40fb9820 3792 if ((i.types[0].bitfield.reg8
29b0f896 3793 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3794 || (i.types[1].bitfield.reg8
29b0f896 3795 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3796 || ((i.types[0].bitfield.reg8
3797 || i.types[1].bitfield.reg8)
29b0f896
AM		 3798 && i.rex != 0))
3799 {
3800 int x;
726c5dcd 3801
29b0f896
AM		 3802 i.rex |= REX_OPCODE;
3803 for (x = 0; x < 2; x++)
3804 {
3805 /* Look for 8 bit operand that uses old registers. */
40fb9820 3806 if (i.types[x].bitfield.reg8
29b0f896 3807 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3808 {
29b0f896
AM		 3809 /* In case it is "hi" register, give up. */
3810 if (i.op[x].regs->reg_num > 3)
a540244d 3811 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3812 "instruction requiring REX prefix."),
a540244d 3813 register_prefix, i.op[x].regs->reg_name);
773f551c 3814
29b0f896
AM		 3815 /* Otherwise it is equivalent to the extended register.
3816 Since the encoding doesn't change this is merely
3817 cosmetic cleanup for debug output. */
3818
3819 i.op[x].regs = i.op[x].regs + 8;
773f551c 3820 }
29b0f896
AM		 3821 }
3822 }
773f551c 3823
7ab9ffdd 3824 if (i.rex != 0)
29b0f896
AM		 3825 add_prefix (REX_OPCODE | i.rex);
3826
3827 /* We are ready to output the insn. */
3828 output_insn ();
3829}
3830
3831static char *
e3bb37b5 3832parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3833{
3834 char *l = line;
3835 char *token_start = l;
3836 char *mnem_p;
5c6af06e 3837 int supported;
d3ce72d0 3838 const insn_template *t;
b6169b20 3839 char *dot_p = NULL;
29b0f896 3840
29b0f896
AM		 3841 while (1)
3842 {
3843 mnem_p = mnemonic;
3844 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3845 {
b6169b20
L		 3846 if (*mnem_p == '.')
3847 dot_p = mnem_p;
29b0f896
AM		 3848 mnem_p++;
3849 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3850 {
29b0f896
AM		 3851 as_bad (_("no such instruction: `%s'"), token_start);
3852 return NULL;
3853 }
3854 l++;
3855 }
3856 if (!is_space_char (*l)
3857 && *l != END_OF_INSN
e44823cf
JB		 3858 && (intel_syntax
3859 || (*l != PREFIX_SEPARATOR
3860 && *l != ',')))
29b0f896
AM		 3861 {
3862 as_bad (_("invalid character %s in mnemonic"),
3863 output_invalid (*l));
3864 return NULL;
3865 }
3866 if (token_start == l)
3867 {
e44823cf 3868 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3869 as_bad (_("expecting prefix; got nothing"));
3870 else
3871 as_bad (_("expecting mnemonic; got nothing"));
3872 return NULL;
3873 }
45288df1 3874
29b0f896 3875 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3876 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3877
29b0f896
AM		 3878 if (*l != END_OF_INSN
3879 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3880 && current_templates
40fb9820 3881 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3882 {
c6fb90c8 3883 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3884 {
3885 as_bad ((flag_code != CODE_64BIT
3886 ? _("`%s' is only supported in 64-bit mode")
3887 : _("`%s' is not supported in 64-bit mode")),
3888 current_templates->start->name);
3889 return NULL;
3890 }
29b0f896
AM		 3891 /* If we are in 16-bit mode, do not allow addr16 or data16.
3892 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3893 if ((current_templates->start->opcode_modifier.size16
3894 || current_templates->start->opcode_modifier.size32)
29b0f896 3895 && flag_code != CODE_64BIT
40fb9820 3896 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3897 ^ (flag_code == CODE_16BIT)))
3898 {
3899 as_bad (_("redundant %s prefix"),
3900 current_templates->start->name);
3901 return NULL;
45288df1 3902 }
29b0f896
AM		 3903 /* Add prefix, checking for repeated prefixes. */
3904 switch (add_prefix (current_templates->start->base_opcode))
3905 {
c32fa91d 3906 case PREFIX_EXIST:
29b0f896 3907 return NULL;
c32fa91d 3908 case PREFIX_REP:
42164a71 3909 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3910 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3911 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3912 i.bnd_prefix = current_templates->start->name;
42164a71 3913 else
d5de92cf 3914 i.rep_prefix = current_templates->start->name;
29b0f896 3915 break;
c32fa91d
L		 3916 default:
3917 break;
29b0f896
AM		 3918 }
3919 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3920 token_start = ++l;
3921 }
3922 else
3923 break;
3924 }
45288df1 3925
30a55f88 3926 if (!current_templates)
b6169b20 3927 {
f8a5c266
L		 3928 /* Check if we should swap operand or force 32bit displacement in
3929 encoding. */
30a55f88
L		 3930 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3931 i.swap_operand = 1;
8d63c93e 3932 else if (mnem_p - 3 == dot_p
a501d77e
L		 3933 && dot_p[1] == 'd'
3934 && dot_p[2] == '8')
3935 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3936 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3937 && dot_p[1] == 'd'
3938 && dot_p[2] == '3'
3939 && dot_p[3] == '2')
a501d77e 3940 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3941 else
3942 goto check_suffix;
3943 mnem_p = dot_p;
3944 *dot_p = '\0';
d3ce72d0 3945 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3946 }
3947
29b0f896
AM		 3948 if (!current_templates)
3949 {
b6169b20 3950check_suffix:
29b0f896
AM		 3951 /* See if we can get a match by trimming off a suffix. */
3952 switch (mnem_p[-1])
3953 {
3954 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3955 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3956 i.suffix = SHORT_MNEM_SUFFIX;
3957 else
1a0670f3 3958 /* Fall through. */
29b0f896
AM		 3959 case BYTE_MNEM_SUFFIX:
3960 case QWORD_MNEM_SUFFIX:
3961 i.suffix = mnem_p[-1];
3962 mnem_p[-1] = '\0';
d3ce72d0
NC		 3963 current_templates = (const templates *) hash_find (op_hash,
3964 mnemonic);
29b0f896
AM		 3965 break;
3966 case SHORT_MNEM_SUFFIX:
3967 case LONG_MNEM_SUFFIX:
3968 if (!intel_syntax)
3969 {
3970 i.suffix = mnem_p[-1];
3971 mnem_p[-1] = '\0';
d3ce72d0
NC		 3972 current_templates = (const templates *) hash_find (op_hash,
3973 mnemonic);
29b0f896
AM		 3974 }
3975 break;
252b5132 3976
29b0f896
AM		 3977 /* Intel Syntax. */
3978 case 'd':
3979 if (intel_syntax)
3980 {
9306ca4a 3981 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3982 i.suffix = SHORT_MNEM_SUFFIX;
3983 else
3984 i.suffix = LONG_MNEM_SUFFIX;
3985 mnem_p[-1] = '\0';
d3ce72d0
NC		 3986 current_templates = (const templates *) hash_find (op_hash,
3987 mnemonic);
29b0f896
AM		 3988 }
3989 break;
3990 }
3991 if (!current_templates)
3992 {
3993 as_bad (_("no such instruction: `%s'"), token_start);
3994 return NULL;
3995 }
3996 }
252b5132 3997
40fb9820
L		 3998 if (current_templates->start->opcode_modifier.jump
3999 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4000 {
4001 /* Check for a branch hint. We allow ",pt" and ",pn" for
4002 predict taken and predict not taken respectively.
4003 I'm not sure that branch hints actually do anything on loop
4004 and jcxz insns (JumpByte) for current Pentium4 chips. They
4005 may work in the future and it doesn't hurt to accept them
4006 now. */
4007 if (l[0] == ',' && l[1] == 'p')
4008 {
4009 if (l[2] == 't')
4010 {
4011 if (!add_prefix (DS_PREFIX_OPCODE))
4012 return NULL;
4013 l += 3;
4014 }
4015 else if (l[2] == 'n')
4016 {
4017 if (!add_prefix (CS_PREFIX_OPCODE))
4018 return NULL;
4019 l += 3;
4020 }
4021 }
4022 }
4023 /* Any other comma loses. */
4024 if (*l == ',')
4025 {
4026 as_bad (_("invalid character %s in mnemonic"),
4027 output_invalid (*l));
4028 return NULL;
4029 }
252b5132 4030
29b0f896 4031 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4032 supported = 0;
4033 for (t = current_templates->start; t < current_templates->end; ++t)
4034 {
c0f3af97
L		 4035 supported |= cpu_flags_match (t);
4036 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4037 goto skip;
5c6af06e 4038 }
3629bb00 4039
c0f3af97 4040 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4041 {
4042 as_bad (flag_code == CODE_64BIT
4043 ? _("`%s' is not supported in 64-bit mode")
4044 : _("`%s' is only supported in 64-bit mode"),
4045 current_templates->start->name);
4046 return NULL;
4047 }
c0f3af97 4048 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4049 {
3629bb00 4050 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4051 current_templates->start->name,
41aacd83 4052 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4053 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4054 return NULL;
29b0f896 4055 }
3629bb00
L		 4056
4057skip:
4058 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4059 && (flag_code != CODE_16BIT))
29b0f896
AM		 4060 {
4061 as_warn (_("use .code16 to ensure correct addressing mode"));
4062 }
252b5132 4063
29b0f896
AM		 4064 return l;
4065}
252b5132 4066
29b0f896 4067static char *
e3bb37b5 4068parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4069{
4070 char *token_start;
3138f287 4071
29b0f896
AM		 4072 /* 1 if operand is pending after ','. */
4073 unsigned int expecting_operand = 0;
252b5132 4074
29b0f896
AM		 4075 /* Non-zero if operand parens not balanced. */
4076 unsigned int paren_not_balanced;
4077
4078 while (*l != END_OF_INSN)
4079 {
4080 /* Skip optional white space before operand. */
4081 if (is_space_char (*l))
4082 ++l;
d02603dc 4083 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4084 {
4085 as_bad (_("invalid character %s before operand %d"),
4086 output_invalid (*l),
4087 i.operands + 1);
4088 return NULL;
4089 }
d02603dc 4090 token_start = l; /* After white space. */
29b0f896
AM		 4091 paren_not_balanced = 0;
4092 while (paren_not_balanced || *l != ',')
4093 {
4094 if (*l == END_OF_INSN)
4095 {
4096 if (paren_not_balanced)
4097 {
4098 if (!intel_syntax)
4099 as_bad (_("unbalanced parenthesis in operand %d."),
4100 i.operands + 1);
4101 else
4102 as_bad (_("unbalanced brackets in operand %d."),
4103 i.operands + 1);
4104 return NULL;
4105 }
4106 else
4107 break; /* we are done */
4108 }
d02603dc 4109 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4110 {
4111 as_bad (_("invalid character %s in operand %d"),
4112 output_invalid (*l),
4113 i.operands + 1);
4114 return NULL;
4115 }
4116 if (!intel_syntax)
4117 {
4118 if (*l == '(')
4119 ++paren_not_balanced;
4120 if (*l == ')')
4121 --paren_not_balanced;
4122 }
4123 else
4124 {
4125 if (*l == '[')
4126 ++paren_not_balanced;
4127 if (*l == ']')
4128 --paren_not_balanced;
4129 }
4130 l++;
4131 }
4132 if (l != token_start)
4133 { /* Yes, we've read in another operand. */
4134 unsigned int operand_ok;
4135 this_operand = i.operands++;
7d5e4556 4136 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4137 if (i.operands > MAX_OPERANDS)
4138 {
4139 as_bad (_("spurious operands; (%d operands/instruction max)"),
4140 MAX_OPERANDS);
4141 return NULL;
4142 }
4143 /* Now parse operand adding info to 'i' as we go along. */
4144 END_STRING_AND_SAVE (l);
4145
4146 if (intel_syntax)
4147 operand_ok =
4148 i386_intel_operand (token_start,
4149 intel_float_operand (mnemonic));
4150 else
a7619375 4151 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4152
4153 RESTORE_END_STRING (l);
4154 if (!operand_ok)
4155 return NULL;
4156 }
4157 else
4158 {
4159 if (expecting_operand)
4160 {
4161 expecting_operand_after_comma:
4162 as_bad (_("expecting operand after ','; got nothing"));
4163 return NULL;
4164 }
4165 if (*l == ',')
4166 {
4167 as_bad (_("expecting operand before ','; got nothing"));
4168 return NULL;
4169 }
4170 }
7f3f1ea2 4171
29b0f896
AM		 4172 /* Now *l must be either ',' or END_OF_INSN. */
4173 if (*l == ',')
4174 {
4175 if (*++l == END_OF_INSN)
4176 {
4177 /* Just skip it, if it's \n complain. */
4178 goto expecting_operand_after_comma;
4179 }
4180 expecting_operand = 1;
4181 }
4182 }
4183 return l;
4184}
7f3f1ea2 4185
050dfa73 4186static void
4d456e3d 4187swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4188{
4189 union i386_op temp_op;
40fb9820 4190 i386_operand_type temp_type;
050dfa73 4191 enum bfd_reloc_code_real temp_reloc;
4eed87de 4192
050dfa73
MM		 4193 temp_type = i.types[xchg2];
4194 i.types[xchg2] = i.types[xchg1];
4195 i.types[xchg1] = temp_type;
4196 temp_op = i.op[xchg2];
4197 i.op[xchg2] = i.op[xchg1];
4198 i.op[xchg1] = temp_op;
4199 temp_reloc = i.reloc[xchg2];
4200 i.reloc[xchg2] = i.reloc[xchg1];
4201 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4202
4203 if (i.mask)
4204 {
4205 if (i.mask->operand == xchg1)
4206 i.mask->operand = xchg2;
4207 else if (i.mask->operand == xchg2)
4208 i.mask->operand = xchg1;
4209 }
4210 if (i.broadcast)
4211 {
4212 if (i.broadcast->operand == xchg1)
4213 i.broadcast->operand = xchg2;
4214 else if (i.broadcast->operand == xchg2)
4215 i.broadcast->operand = xchg1;
4216 }
4217 if (i.rounding)
4218 {
4219 if (i.rounding->operand == xchg1)
4220 i.rounding->operand = xchg2;
4221 else if (i.rounding->operand == xchg2)
4222 i.rounding->operand = xchg1;
4223 }
050dfa73
MM		 4224}
4225
29b0f896 4226static void
e3bb37b5 4227swap_operands (void)
29b0f896 4228{
b7c61d9a 4229 switch (i.operands)
050dfa73 4230 {
c0f3af97 4231 case 5:
b7c61d9a 4232 case 4:
4d456e3d 4233 swap_2_operands (1, i.operands - 2);
1a0670f3 4234 /* Fall through. */
b7c61d9a
L		 4235 case 3:
4236 case 2:
4d456e3d 4237 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4238 break;
4239 default:
4240 abort ();
29b0f896 4241 }
29b0f896
AM		 4242
4243 if (i.mem_operands == 2)
4244 {
4245 const seg_entry *temp_seg;
4246 temp_seg = i.seg[0];
4247 i.seg[0] = i.seg[1];
4248 i.seg[1] = temp_seg;
4249 }
4250}
252b5132 4251
29b0f896
AM		 4252/* Try to ensure constant immediates are represented in the smallest
4253 opcode possible. */
4254static void
e3bb37b5 4255optimize_imm (void)
29b0f896
AM		 4256{
4257 char guess_suffix = 0;
4258 int op;
252b5132 4259
29b0f896
AM		 4260 if (i.suffix)
4261 guess_suffix = i.suffix;
4262 else if (i.reg_operands)
4263 {
4264 /* Figure out a suffix from the last register operand specified.
4265 We can't do this properly yet, ie. excluding InOutPortReg,
4266 but the following works for instructions with immediates.
4267 In any case, we can't set i.suffix yet. */
4268 for (op = i.operands; --op >= 0;)
40fb9820 4269 if (i.types[op].bitfield.reg8)
7ab9ffdd 4270 {
40fb9820
L		 4271 guess_suffix = BYTE_MNEM_SUFFIX;
4272 break;
4273 }
4274 else if (i.types[op].bitfield.reg16)
252b5132 4275 {
40fb9820
L		 4276 guess_suffix = WORD_MNEM_SUFFIX;
4277 break;
4278 }
4279 else if (i.types[op].bitfield.reg32)
4280 {
4281 guess_suffix = LONG_MNEM_SUFFIX;
4282 break;
4283 }
4284 else if (i.types[op].bitfield.reg64)
4285 {
4286 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4287 break;
252b5132 4288 }
29b0f896
AM		 4289 }
4290 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4291 guess_suffix = WORD_MNEM_SUFFIX;
4292
4293 for (op = i.operands; --op >= 0;)
40fb9820 4294 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4295 {
4296 switch (i.op[op].imms->X_op)
252b5132 4297 {
29b0f896
AM		 4298 case O_constant:
4299 /* If a suffix is given, this operand may be shortened. */
4300 switch (guess_suffix)
252b5132 4301 {
29b0f896 4302 case LONG_MNEM_SUFFIX:
40fb9820
L		 4303 i.types[op].bitfield.imm32 = 1;
4304 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4305 break;
4306 case WORD_MNEM_SUFFIX:
40fb9820
L		 4307 i.types[op].bitfield.imm16 = 1;
4308 i.types[op].bitfield.imm32 = 1;
4309 i.types[op].bitfield.imm32s = 1;
4310 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4311 break;
4312 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4313 i.types[op].bitfield.imm8 = 1;
4314 i.types[op].bitfield.imm8s = 1;
4315 i.types[op].bitfield.imm16 = 1;
4316 i.types[op].bitfield.imm32 = 1;
4317 i.types[op].bitfield.imm32s = 1;
4318 i.types[op].bitfield.imm64 = 1;
29b0f896 4319 break;
252b5132 4320 }
252b5132 4321
29b0f896
AM		 4322 /* If this operand is at most 16 bits, convert it
4323 to a signed 16 bit number before trying to see
4324 whether it will fit in an even smaller size.
4325 This allows a 16-bit operand such as $0xffe0 to
4326 be recognised as within Imm8S range. */
40fb9820 4327 if ((i.types[op].bitfield.imm16)
29b0f896 4328 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4329 {
29b0f896
AM		 4330 i.op[op].imms->X_add_number =
4331 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4332 }
a28def75
L		 4333#ifdef BFD64
4334 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4335 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4336 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4337 == 0))
4338 {
4339 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4340 ^ ((offsetT) 1 << 31))
4341 - ((offsetT) 1 << 31));
4342 }
a28def75 4343#endif
40fb9820 4344 i.types[op]
c6fb90c8
L		 4345 = operand_type_or (i.types[op],
4346 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4347
29b0f896
AM		 4348 /* We must avoid matching of Imm32 templates when 64bit
4349 only immediate is available. */
4350 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4351 i.types[op].bitfield.imm32 = 0;
29b0f896 4352 break;
252b5132 4353
29b0f896
AM		 4354 case O_absent:
4355 case O_register:
4356 abort ();
4357
4358 /* Symbols and expressions. */
4359 default:
9cd96992
JB		 4360 /* Convert symbolic operand to proper sizes for matching, but don't
4361 prevent matching a set of insns that only supports sizes other
4362 than those matching the insn suffix. */
4363 {
40fb9820 4364 i386_operand_type mask, allowed;
d3ce72d0 4365 const insn_template *t;
9cd96992 4366
0dfbf9d7
L		 4367 operand_type_set (&mask, 0);
4368 operand_type_set (&allowed, 0);
40fb9820 4369
4eed87de
AM		 4370 for (t = current_templates->start;
4371 t < current_templates->end;
4372 ++t)
c6fb90c8
L		 4373 allowed = operand_type_or (allowed,
4374 t->operand_types[op]);
9cd96992
JB		 4375 switch (guess_suffix)
4376 {
4377 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4378 mask.bitfield.imm64 = 1;
4379 mask.bitfield.imm32s = 1;
9cd96992
JB		 4380 break;
4381 case LONG_MNEM_SUFFIX:
40fb9820 4382 mask.bitfield.imm32 = 1;
9cd96992
JB		 4383 break;
4384 case WORD_MNEM_SUFFIX:
40fb9820 4385 mask.bitfield.imm16 = 1;
9cd96992
JB		 4386 break;
4387 case BYTE_MNEM_SUFFIX:
40fb9820 4388 mask.bitfield.imm8 = 1;
9cd96992
JB		 4389 break;
4390 default:
9cd96992
JB		 4391 break;
4392 }
c6fb90c8 4393 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4394 if (!operand_type_all_zero (&allowed))
c6fb90c8 4395 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4396 }
29b0f896 4397 break;
252b5132 4398 }
29b0f896
AM		 4399 }
4400}
47926f60 4401
29b0f896
AM		 4402/* Try to use the smallest displacement type too. */
4403static void
e3bb37b5 4404optimize_disp (void)
29b0f896
AM		 4405{
4406 int op;
3e73aa7c 4407
29b0f896 4408 for (op = i.operands; --op >= 0;)
40fb9820 4409 if (operand_type_check (i.types[op], disp))
252b5132 4410 {
b300c311 4411 if (i.op[op].disps->X_op == O_constant)
252b5132 4412 {
91d6fa6a 4413 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4414
40fb9820 4415 if (i.types[op].bitfield.disp16
91d6fa6a 4416 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4417 {
4418 /* If this operand is at most 16 bits, convert
4419 to a signed 16 bit number and don't use 64bit
4420 displacement. */
91d6fa6a 4421 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4422 i.types[op].bitfield.disp64 = 0;
b300c311 4423 }
a28def75
L		 4424#ifdef BFD64
4425 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4426 if (i.types[op].bitfield.disp32
91d6fa6a 4427 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4428 {
4429 /* If this operand is at most 32 bits, convert
4430 to a signed 32 bit number and don't use 64bit
4431 displacement. */
91d6fa6a
NC		 4432 op_disp &= (((offsetT) 2 << 31) - 1);
4433 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4434 i.types[op].bitfield.disp64 = 0;
b300c311 4435 }
a28def75 4436#endif
91d6fa6a 4437 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4438 {
40fb9820
L		 4439 i.types[op].bitfield.disp8 = 0;
4440 i.types[op].bitfield.disp16 = 0;
4441 i.types[op].bitfield.disp32 = 0;
4442 i.types[op].bitfield.disp32s = 0;
4443 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4444 i.op[op].disps = 0;
4445 i.disp_operands--;
4446 }
4447 else if (flag_code == CODE_64BIT)
4448 {
91d6fa6a 4449 if (fits_in_signed_long (op_disp))
28a9d8f5 4450 {
40fb9820
L		 4451 i.types[op].bitfield.disp64 = 0;
4452 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4453 }
0e1147d9 4454 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4455 && fits_in_unsigned_long (op_disp))
40fb9820 4456 i.types[op].bitfield.disp32 = 1;
b300c311 4457 }
40fb9820
L		 4458 if ((i.types[op].bitfield.disp32
4459 || i.types[op].bitfield.disp32s
4460 || i.types[op].bitfield.disp16)
91d6fa6a 4461 && fits_in_signed_byte (op_disp))
40fb9820 4462 i.types[op].bitfield.disp8 = 1;
252b5132 4463 }
67a4f2b7
AO		 4464 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4465 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4466 {
4467 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4468 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4469 i.types[op].bitfield.disp8 = 0;
4470 i.types[op].bitfield.disp16 = 0;
4471 i.types[op].bitfield.disp32 = 0;
4472 i.types[op].bitfield.disp32s = 0;
4473 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4474 }
4475 else
b300c311 4476 /* We only support 64bit displacement on constants. */
40fb9820 4477 i.types[op].bitfield.disp64 = 0;
252b5132 4478 }
29b0f896
AM		 4479}
4480
6c30d220
L		 4481/* Check if operands are valid for the instruction. */
4482
4483static int
4484check_VecOperands (const insn_template *t)
4485{
43234a1e
L		 4486 unsigned int op;
4487
6c30d220
L		 4488 /* Without VSIB byte, we can't have a vector register for index. */
4489 if (!t->opcode_modifier.vecsib
4490 && i.index_reg
4491 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4492 || i.index_reg->reg_type.bitfield.regymm
4493 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4494 {
4495 i.error = unsupported_vector_index_register;
4496 return 1;
4497 }
4498
ad8ecc81
MZ		 4499 /* Check if default mask is allowed. */
4500 if (t->opcode_modifier.nodefmask
4501 && (!i.mask || i.mask->mask->reg_num == 0))
4502 {
4503 i.error = no_default_mask;
4504 return 1;
4505 }
4506
7bab8ab5
JB		 4507 /* For VSIB byte, we need a vector register for index, and all vector
4508 registers must be distinct. */
4509 if (t->opcode_modifier.vecsib)
4510 {
4511 if (!i.index_reg
6c30d220
L		 4512 || !((t->opcode_modifier.vecsib == VecSIB128
4513 && i.index_reg->reg_type.bitfield.regxmm)
4514 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4515 && i.index_reg->reg_type.bitfield.regymm)
4516 || (t->opcode_modifier.vecsib == VecSIB512
4517 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4518 {
4519 i.error = invalid_vsib_address;
4520 return 1;
4521 }
4522
43234a1e
L		 4523 gas_assert (i.reg_operands == 2 || i.mask);
4524 if (i.reg_operands == 2 && !i.mask)
4525 {
4526 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4527 || i.types[0].bitfield.regymm);
43234a1e 4528 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4529 || i.types[2].bitfield.regymm);
43234a1e
L		 4530 if (operand_check == check_none)
4531 return 0;
4532 if (register_number (i.op[0].regs)
4533 != register_number (i.index_reg)
4534 && register_number (i.op[2].regs)
4535 != register_number (i.index_reg)
4536 && register_number (i.op[0].regs)
4537 != register_number (i.op[2].regs))
4538 return 0;
4539 if (operand_check == check_error)
4540 {
4541 i.error = invalid_vector_register_set;
4542 return 1;
4543 }
4544 as_warn (_("mask, index, and destination registers should be distinct"));
4545 }
8444f82a
MZ		 4546 else if (i.reg_operands == 1 && i.mask)
4547 {
4548 if ((i.types[1].bitfield.regymm
4549 || i.types[1].bitfield.regzmm)
4550 && (register_number (i.op[1].regs)
4551 == register_number (i.index_reg)))
4552 {
4553 if (operand_check == check_error)
4554 {
4555 i.error = invalid_vector_register_set;
4556 return 1;
4557 }
4558 if (operand_check != check_none)
4559 as_warn (_("index and destination registers should be distinct"));
4560 }
4561 }
43234a1e 4562 }
7bab8ab5 4563
43234a1e
L		 4564 /* Check if broadcast is supported by the instruction and is applied
4565 to the memory operand. */
4566 if (i.broadcast)
4567 {
4568 int broadcasted_opnd_size;
4569
4570 /* Check if specified broadcast is supported in this instruction,
4571 and it's applied to memory operand of DWORD or QWORD type,
4572 depending on VecESize. */
4573 if (i.broadcast->type != t->opcode_modifier.broadcast
4574 || !i.types[i.broadcast->operand].bitfield.mem
4575 || (t->opcode_modifier.vecesize == 0
4576 && !i.types[i.broadcast->operand].bitfield.dword
4577 && !i.types[i.broadcast->operand].bitfield.unspecified)
4578 || (t->opcode_modifier.vecesize == 1
4579 && !i.types[i.broadcast->operand].bitfield.qword
4580 && !i.types[i.broadcast->operand].bitfield.unspecified))
4581 goto bad_broadcast;
4582
4583 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4584 if (i.broadcast->type == BROADCAST_1TO16)
4585 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4586 else if (i.broadcast->type == BROADCAST_1TO8)
4587 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4588 else if (i.broadcast->type == BROADCAST_1TO4)
4589 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4590 else if (i.broadcast->type == BROADCAST_1TO2)
4591 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4592 else
4593 goto bad_broadcast;
4594
4595 if ((broadcasted_opnd_size == 256
4596 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4597 || (broadcasted_opnd_size == 512
4598 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4599 {
4600 bad_broadcast:
4601 i.error = unsupported_broadcast;
4602 return 1;
4603 }
4604 }
4605 /* If broadcast is supported in this instruction, we need to check if
4606 operand of one-element size isn't specified without broadcast. */
4607 else if (t->opcode_modifier.broadcast && i.mem_operands)
4608 {
4609 /* Find memory operand. */
4610 for (op = 0; op < i.operands; op++)
4611 if (operand_type_check (i.types[op], anymem))
4612 break;
4613 gas_assert (op < i.operands);
4614 /* Check size of the memory operand. */
4615 if ((t->opcode_modifier.vecesize == 0
4616 && i.types[op].bitfield.dword)
4617 || (t->opcode_modifier.vecesize == 1
4618 && i.types[op].bitfield.qword))
4619 {
4620 i.error = broadcast_needed;
4621 return 1;
4622 }
4623 }
4624
4625 /* Check if requested masking is supported. */
4626 if (i.mask
4627 && (!t->opcode_modifier.masking
4628 || (i.mask->zeroing
4629 && t->opcode_modifier.masking == MERGING_MASKING)))
4630 {
4631 i.error = unsupported_masking;
4632 return 1;
4633 }
4634
4635 /* Check if masking is applied to dest operand. */
4636 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4637 {
4638 i.error = mask_not_on_destination;
4639 return 1;
4640 }
4641
43234a1e
L		 4642 /* Check RC/SAE. */
4643 if (i.rounding)
4644 {
4645 if ((i.rounding->type != saeonly
4646 && !t->opcode_modifier.staticrounding)
4647 || (i.rounding->type == saeonly
4648 && (t->opcode_modifier.staticrounding
4649 || !t->opcode_modifier.sae)))
4650 {
4651 i.error = unsupported_rc_sae;
4652 return 1;
4653 }
4654 /* If the instruction has several immediate operands and one of
4655 them is rounding, the rounding operand should be the last
4656 immediate operand. */
4657 if (i.imm_operands > 1
4658 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4659 {
43234a1e 4660 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4661 return 1;
4662 }
6c30d220
L		 4663 }
4664
43234a1e
L		 4665 /* Check vector Disp8 operand. */
4666 if (t->opcode_modifier.disp8memshift)
4667 {
4668 if (i.broadcast)
4669 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4670 else
4671 i.memshift = t->opcode_modifier.disp8memshift;
4672
4673 for (op = 0; op < i.operands; op++)
4674 if (operand_type_check (i.types[op], disp)
4675 && i.op[op].disps->X_op == O_constant)
4676 {
4677 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4678 int vec_disp8_ok
4679 = (i.disp_encoding != disp_encoding_32bit
4680 && fits_in_vec_disp8 (value));
43234a1e
L		 4681 if (t->operand_types [op].bitfield.vec_disp8)
4682 {
4683 if (vec_disp8_ok)
4684 i.types[op].bitfield.vec_disp8 = 1;
4685 else
4686 {
4687 /* Vector insn can only have Vec_Disp8/Disp32 in
4688 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4689 mode. */
4690 i.types[op].bitfield.disp8 = 0;
4691 if (flag_code != CODE_16BIT)
4692 i.types[op].bitfield.disp16 = 0;
4693 }
4694 }
4695 else if (flag_code != CODE_16BIT)
4696 {
4697 /* One form of this instruction supports vector Disp8.
4698 Try vector Disp8 if we need to use Disp32. */
4699 if (vec_disp8_ok && !fits_in_signed_byte (value))
4700 {
4701 i.error = try_vector_disp8;
4702 return 1;
4703 }
4704 }
4705 }
4706 }
4707 else
4708 i.memshift = -1;
4709
6c30d220
L		 4710 return 0;
4711}
4712
43f3e2ee 4713/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4714 operand types. */
4715
4716static int
4717VEX_check_operands (const insn_template *t)
4718{
43234a1e
L		 4719 /* VREX is only valid with EVEX prefix. */
4720 if (i.need_vrex && !t->opcode_modifier.evex)
4721 {
4722 i.error = invalid_register_operand;
4723 return 1;
4724 }
4725
a683cc34
SP		 4726 if (!t->opcode_modifier.vex)
4727 return 0;
4728
4729 /* Only check VEX_Imm4, which must be the first operand. */
4730 if (t->operand_types[0].bitfield.vec_imm4)
4731 {
4732 if (i.op[0].imms->X_op != O_constant
4733 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4734 {
a65babc9 4735 i.error = bad_imm4;
891edac4
L		 4736 return 1;
4737 }
a683cc34
SP		 4738
4739 /* Turn off Imm8 so that update_imm won't complain. */
4740 i.types[0] = vec_imm4;
4741 }
4742
4743 return 0;
4744}
4745
d3ce72d0 4746static const insn_template *
83b16ac6 4747match_template (char mnem_suffix)
29b0f896
AM		 4748{
4749 /* Points to template once we've found it. */
d3ce72d0 4750 const insn_template *t;
40fb9820 4751 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4752 i386_operand_type overlap4;
29b0f896 4753 unsigned int found_reverse_match;
83b16ac6 4754 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4755 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4756 int addr_prefix_disp;
a5c311ca 4757 unsigned int j;
3629bb00 4758 unsigned int found_cpu_match;
45664ddb 4759 unsigned int check_register;
5614d22c 4760 enum i386_error specific_error = 0;
29b0f896 4761
c0f3af97
L		 4762#if MAX_OPERANDS != 5
4763# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4764#endif
4765
29b0f896 4766 found_reverse_match = 0;
539e75ad 4767 addr_prefix_disp = -1;
40fb9820
L		 4768
4769 memset (&suffix_check, 0, sizeof (suffix_check));
4770 if (i.suffix == BYTE_MNEM_SUFFIX)
4771 suffix_check.no_bsuf = 1;
4772 else if (i.suffix == WORD_MNEM_SUFFIX)
4773 suffix_check.no_wsuf = 1;
4774 else if (i.suffix == SHORT_MNEM_SUFFIX)
4775 suffix_check.no_ssuf = 1;
4776 else if (i.suffix == LONG_MNEM_SUFFIX)
4777 suffix_check.no_lsuf = 1;
4778 else if (i.suffix == QWORD_MNEM_SUFFIX)
4779 suffix_check.no_qsuf = 1;
4780 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4781 suffix_check.no_ldsuf = 1;
29b0f896 4782
83b16ac6
JB		 4783 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4784 if (intel_syntax)
4785 {
4786 switch (mnem_suffix)
4787 {
4788 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4789 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4790 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4791 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4792 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4793 }
4794 }
4795
01559ecc
L		 4796 /* Must have right number of operands. */
4797 i.error = number_of_operands_mismatch;
4798
45aa61fe 4799 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4800 {
539e75ad
L		 4801 addr_prefix_disp = -1;
4802
29b0f896
AM		 4803 if (i.operands != t->operands)
4804 continue;
4805
50aecf8c 4806 /* Check processor support. */
a65babc9 4807 i.error = unsupported;
c0f3af97
L		 4808 found_cpu_match = (cpu_flags_match (t)
4809 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4810 if (!found_cpu_match)
4811 continue;
4812
e1d4d893 4813 /* Check old gcc support. */
a65babc9 4814 i.error = old_gcc_only;
e1d4d893
L		 4815 if (!old_gcc && t->opcode_modifier.oldgcc)
4816 continue;
4817
4818 /* Check AT&T mnemonic. */
a65babc9 4819 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4820 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4821 continue;
4822
e92bae62 4823 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4824 i.error = unsupported_syntax;
5c07affc 4825 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4826 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4827 || (intel64 && t->opcode_modifier.amd64)
4828 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4829 continue;
4830
20592a94 4831 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4832 i.error = invalid_instruction_suffix;
567e4e96
L		 4833 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4834 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4835 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4836 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4837 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4838 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4839 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4840 continue;
83b16ac6
JB		 4841 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4842 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4843 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4844 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4845 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4846 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4847 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4848 continue;
29b0f896 4849
5c07affc 4850 if (!operand_size_match (t))
7d5e4556 4851 continue;
539e75ad 4852
5c07affc
L		 4853 for (j = 0; j < MAX_OPERANDS; j++)
4854 operand_types[j] = t->operand_types[j];
4855
45aa61fe
AM		 4856 /* In general, don't allow 64-bit operands in 32-bit mode. */
4857 if (i.suffix == QWORD_MNEM_SUFFIX
4858 && flag_code != CODE_64BIT
4859 && (intel_syntax
40fb9820 4860 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4861 && !intel_float_operand (t->name))
4862 : intel_float_operand (t->name) != 2)
40fb9820 4863 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4864 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4865 && !operand_types[0].bitfield.regymm
4866 && !operand_types[0].bitfield.regzmm)
40fb9820 4867 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4868 && operand_types[t->operands > 1].bitfield.regxmm
4869 && operand_types[t->operands > 1].bitfield.regymm
4870 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4871 && (t->base_opcode != 0x0fc7
4872 || t->extension_opcode != 1 /* cmpxchg8b */))
4873 continue;
4874
192dc9c6
JB		 4875 /* In general, don't allow 32-bit operands on pre-386. */
4876 else if (i.suffix == LONG_MNEM_SUFFIX
4877 && !cpu_arch_flags.bitfield.cpui386
4878 && (intel_syntax
4879 ? (!t->opcode_modifier.ignoresize
4880 && !intel_float_operand (t->name))
4881 : intel_float_operand (t->name) != 2)
4882 && ((!operand_types[0].bitfield.regmmx
4883 && !operand_types[0].bitfield.regxmm)
4884 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4885 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4886 continue;
4887
29b0f896 4888 /* Do not verify operands when there are none. */
50aecf8c 4889 else
29b0f896 4890 {
c6fb90c8 4891 if (!t->operands)
2dbab7d5
L		 4892 /* We've found a match; break out of loop. */
4893 break;
29b0f896 4894 }
252b5132 4895
539e75ad
L		 4896 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4897 into Disp32/Disp16/Disp32 operand. */
4898 if (i.prefix[ADDR_PREFIX] != 0)
4899 {
40fb9820 4900 /* There should be only one Disp operand. */
539e75ad
L		 4901 switch (flag_code)
4902 {
4903 case CODE_16BIT:
40fb9820
L		 4904 for (j = 0; j < MAX_OPERANDS; j++)
4905 {
4906 if (operand_types[j].bitfield.disp16)
4907 {
4908 addr_prefix_disp = j;
4909 operand_types[j].bitfield.disp32 = 1;
4910 operand_types[j].bitfield.disp16 = 0;
4911 break;
4912 }
4913 }
539e75ad
L		 4914 break;
4915 case CODE_32BIT:
40fb9820
L		 4916 for (j = 0; j < MAX_OPERANDS; j++)
4917 {
4918 if (operand_types[j].bitfield.disp32)
4919 {
4920 addr_prefix_disp = j;
4921 operand_types[j].bitfield.disp32 = 0;
4922 operand_types[j].bitfield.disp16 = 1;
4923 break;
4924 }
4925 }
539e75ad
L		 4926 break;
4927 case CODE_64BIT:
40fb9820
L		 4928 for (j = 0; j < MAX_OPERANDS; j++)
4929 {
4930 if (operand_types[j].bitfield.disp64)
4931 {
4932 addr_prefix_disp = j;
4933 operand_types[j].bitfield.disp64 = 0;
4934 operand_types[j].bitfield.disp32 = 1;
4935 break;
4936 }
4937 }
539e75ad
L		 4938 break;
4939 }
539e75ad
L		 4940 }
4941
02a86693
L		 4942 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4943 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4944 continue;
4945
56ffb741
L		 4946 /* We check register size if needed. */
4947 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4948 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4949 switch (t->operands)
4950 {
4951 case 1:
40fb9820 4952 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4953 continue;
4954 break;
4955 case 2:
8b38ad71
L		 4956 /* xchg %eax, %eax is a special case. It is an aliase for nop
4957 only in 32bit mode and we can use opcode 0x90. In 64bit
4958 mode, we can't use 0x90 for xchg %eax, %eax since it should
4959 zero-extend %eax to %rax. */
4960 if (flag_code == CODE_64BIT
4961 && t->base_opcode == 0x90
0dfbf9d7
L		 4962 && operand_type_equal (&i.types [0], &acc32)
4963 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4964 continue;
b6169b20
L		 4965 if (i.swap_operand)
4966 {
4967 /* If we swap operand in encoding, we either match
4968 the next one or reverse direction of operands. */
4969 if (t->opcode_modifier.s)
4970 continue;
4971 else if (t->opcode_modifier.d)
4972 goto check_reverse;
4973 }
1a0670f3 4974 /* Fall through. */
b6169b20 4975
29b0f896 4976 case 3:
fa99fab2
L		 4977 /* If we swap operand in encoding, we match the next one. */
4978 if (i.swap_operand && t->opcode_modifier.s)
4979 continue;
1a0670f3 4980 /* Fall through. */
f48ff2ae 4981 case 4:
c0f3af97 4982 case 5:
c6fb90c8 4983 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4984 if (!operand_type_match (overlap0, i.types[0])
4985 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4986 || (check_register
4987 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4988 operand_types[0],
4989 overlap1, i.types[1],
4990 operand_types[1])))
29b0f896
AM		 4991 {
4992 /* Check if other direction is valid ... */
40fb9820 4993 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4994 continue;
4995
b6169b20 4996check_reverse:
29b0f896 4997 /* Try reversing direction of operands. */
c6fb90c8
L		 4998 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4999 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5000 if (!operand_type_match (overlap0, i.types[0])
5001 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5002 || (check_register
5003 && !operand_type_register_match (overlap0,
5004 i.types[0],
5005 operand_types[1],
5006 overlap1,
5007 i.types[1],
5008 operand_types[0])))
29b0f896
AM		 5009 {
5010 /* Does not match either direction. */
5011 continue;
5012 }
5013 /* found_reverse_match holds which of D or FloatDR
5014 we've found. */
40fb9820 5015 if (t->opcode_modifier.d)
8a2ed489 5016 found_reverse_match = Opcode_D;
40fb9820 5017 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5018 found_reverse_match = Opcode_FloatD;
5019 else
5020 found_reverse_match = 0;
40fb9820 5021 if (t->opcode_modifier.floatr)
8a2ed489 5022 found_reverse_match |= Opcode_FloatR;
29b0f896 5023 }
f48ff2ae 5024 else
29b0f896 5025 {
f48ff2ae 5026 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5027 switch (t->operands)
5028 {
c0f3af97
L		 5029 case 5:
5030 overlap4 = operand_type_and (i.types[4],
5031 operand_types[4]);
1a0670f3 5032 /* Fall through. */
d1cbb4db 5033 case 4:
c6fb90c8
L		 5034 overlap3 = operand_type_and (i.types[3],
5035 operand_types[3]);
1a0670f3 5036 /* Fall through. */
d1cbb4db 5037 case 3:
c6fb90c8
L		 5038 overlap2 = operand_type_and (i.types[2],
5039 operand_types[2]);
d1cbb4db
L		 5040 break;
5041 }
29b0f896 5042
f48ff2ae
L		 5043 switch (t->operands)
5044 {
c0f3af97
L		 5045 case 5:
5046 if (!operand_type_match (overlap4, i.types[4])
5047 || !operand_type_register_match (overlap3,
5048 i.types[3],
5049 operand_types[3],
5050 overlap4,
5051 i.types[4],
5052 operand_types[4]))
5053 continue;
1a0670f3 5054 /* Fall through. */
f48ff2ae 5055 case 4:
40fb9820 5056 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5057 || (check_register
5058 && !operand_type_register_match (overlap2,
5059 i.types[2],
5060 operand_types[2],
5061 overlap3,
5062 i.types[3],
5063 operand_types[3])))
f48ff2ae 5064 continue;
1a0670f3 5065 /* Fall through. */
f48ff2ae
L		 5066 case 3:
5067 /* Here we make use of the fact that there are no
5068 reverse match 3 operand instructions, and all 3
5069 operand instructions only need to be checked for
5070 register consistency between operands 2 and 3. */
40fb9820 5071 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5072 || (check_register
5073 && !operand_type_register_match (overlap1,
5074 i.types[1],
5075 operand_types[1],
5076 overlap2,
5077 i.types[2],
5078 operand_types[2])))
f48ff2ae
L		 5079 continue;
5080 break;
5081 }
29b0f896 5082 }
f48ff2ae 5083 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5084 slip through to break. */
5085 }
3629bb00 5086 if (!found_cpu_match)
29b0f896
AM		 5087 {
5088 found_reverse_match = 0;
5089 continue;
5090 }
c0f3af97 5091
5614d22c
JB		 5092 /* Check if vector and VEX operands are valid. */
5093 if (check_VecOperands (t) || VEX_check_operands (t))
5094 {
5095 specific_error = i.error;
5096 continue;
5097 }
a683cc34 5098
29b0f896
AM		 5099 /* We've found a match; break out of loop. */
5100 break;
5101 }
5102
5103 if (t == current_templates->end)
5104 {
5105 /* We found no match. */
a65babc9 5106 const char *err_msg;
5614d22c 5107 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5108 {
5109 default:
5110 abort ();
86e026a4 5111 case operand_size_mismatch:
a65babc9
L		 5112 err_msg = _("operand size mismatch");
5113 break;
5114 case operand_type_mismatch:
5115 err_msg = _("operand type mismatch");
5116 break;
5117 case register_type_mismatch:
5118 err_msg = _("register type mismatch");
5119 break;
5120 case number_of_operands_mismatch:
5121 err_msg = _("number of operands mismatch");
5122 break;
5123 case invalid_instruction_suffix:
5124 err_msg = _("invalid instruction suffix");
5125 break;
5126 case bad_imm4:
4a2608e3 5127 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5128 break;
5129 case old_gcc_only:
5130 err_msg = _("only supported with old gcc");
5131 break;
5132 case unsupported_with_intel_mnemonic:
5133 err_msg = _("unsupported with Intel mnemonic");
5134 break;
5135 case unsupported_syntax:
5136 err_msg = _("unsupported syntax");
5137 break;
5138 case unsupported:
35262a23 5139 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5140 current_templates->start->name);
5141 return NULL;
6c30d220
L		 5142 case invalid_vsib_address:
5143 err_msg = _("invalid VSIB address");
5144 break;
7bab8ab5
JB		 5145 case invalid_vector_register_set:
5146 err_msg = _("mask, index, and destination registers must be distinct");
5147 break;
6c30d220
L		 5148 case unsupported_vector_index_register:
5149 err_msg = _("unsupported vector index register");
5150 break;
43234a1e
L		 5151 case unsupported_broadcast:
5152 err_msg = _("unsupported broadcast");
5153 break;
5154 case broadcast_not_on_src_operand:
5155 err_msg = _("broadcast not on source memory operand");
5156 break;
5157 case broadcast_needed:
5158 err_msg = _("broadcast is needed for operand of such type");
5159 break;
5160 case unsupported_masking:
5161 err_msg = _("unsupported masking");
5162 break;
5163 case mask_not_on_destination:
5164 err_msg = _("mask not on destination operand");
5165 break;
5166 case no_default_mask:
5167 err_msg = _("default mask isn't allowed");
5168 break;
5169 case unsupported_rc_sae:
5170 err_msg = _("unsupported static rounding/sae");
5171 break;
5172 case rc_sae_operand_not_last_imm:
5173 if (intel_syntax)
5174 err_msg = _("RC/SAE operand must precede immediate operands");
5175 else
5176 err_msg = _("RC/SAE operand must follow immediate operands");
5177 break;
5178 case invalid_register_operand:
5179 err_msg = _("invalid register operand");
5180 break;
a65babc9
L		 5181 }
5182 as_bad (_("%s for `%s'"), err_msg,
891edac4 5183 current_templates->start->name);
fa99fab2 5184 return NULL;
29b0f896 5185 }
252b5132 5186
29b0f896
AM		 5187 if (!quiet_warnings)
5188 {
5189 if (!intel_syntax
40fb9820
L		 5190 && (i.types[0].bitfield.jumpabsolute
5191 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5192 {
5193 as_warn (_("indirect %s without `*'"), t->name);
5194 }
5195
40fb9820
L		 5196 if (t->opcode_modifier.isprefix
5197 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5198 {
5199 /* Warn them that a data or address size prefix doesn't
5200 affect assembly of the next line of code. */
5201 as_warn (_("stand-alone `%s' prefix"), t->name);
5202 }
5203 }
5204
5205 /* Copy the template we found. */
5206 i.tm = *t;
539e75ad
L		 5207
5208 if (addr_prefix_disp != -1)
5209 i.tm.operand_types[addr_prefix_disp]
5210 = operand_types[addr_prefix_disp];
5211
29b0f896
AM		 5212 if (found_reverse_match)
5213 {
5214 /* If we found a reverse match we must alter the opcode
5215 direction bit. found_reverse_match holds bits to change
5216 (different for int & float insns). */
5217
5218 i.tm.base_opcode ^= found_reverse_match;
5219
539e75ad
L		 5220 i.tm.operand_types[0] = operand_types[1];
5221 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5222 }
5223
fa99fab2 5224 return t;
29b0f896
AM		 5225}
5226
5227static int
e3bb37b5 5228check_string (void)
29b0f896 5229{
40fb9820
L		 5230 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5231 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5232 {
5233 if (i.seg[0] != NULL && i.seg[0] != &es)
5234 {
a87af027 5235 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5236 i.tm.name,
a87af027
JB		 5237 mem_op + 1,
5238 register_prefix);
29b0f896
AM		 5239 return 0;
5240 }
5241 /* There's only ever one segment override allowed per instruction.
5242 This instruction possibly has a legal segment override on the
5243 second operand, so copy the segment to where non-string
5244 instructions store it, allowing common code. */
5245 i.seg[0] = i.seg[1];
5246 }
40fb9820 5247 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5248 {
5249 if (i.seg[1] != NULL && i.seg[1] != &es)
5250 {
a87af027 5251 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5252 i.tm.name,
a87af027
JB		 5253 mem_op + 2,
5254 register_prefix);
29b0f896
AM		 5255 return 0;
5256 }
5257 }
5258 return 1;
5259}
5260
5261static int
543613e9 5262process_suffix (void)
29b0f896
AM		 5263{
5264 /* If matched instruction specifies an explicit instruction mnemonic
5265 suffix, use it. */
40fb9820
L		 5266 if (i.tm.opcode_modifier.size16)
5267 i.suffix = WORD_MNEM_SUFFIX;
5268 else if (i.tm.opcode_modifier.size32)
5269 i.suffix = LONG_MNEM_SUFFIX;
5270 else if (i.tm.opcode_modifier.size64)
5271 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5272 else if (i.reg_operands)
5273 {
5274 /* If there's no instruction mnemonic suffix we try to invent one
5275 based on register operands. */
5276 if (!i.suffix)
5277 {
5278 /* We take i.suffix from the last register operand specified,
5279 Destination register type is more significant than source
381d071f
L		 5280 register type. crc32 in SSE4.2 prefers source register
5281 type. */
5282 if (i.tm.base_opcode == 0xf20f38f1)
5283 {
40fb9820
L		 5284 if (i.types[0].bitfield.reg16)
5285 i.suffix = WORD_MNEM_SUFFIX;
5286 else if (i.types[0].bitfield.reg32)
5287 i.suffix = LONG_MNEM_SUFFIX;
5288 else if (i.types[0].bitfield.reg64)
5289 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5290 }
9344ff29 5291 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5292 {
40fb9820 5293 if (i.types[0].bitfield.reg8)
20592a94
L		 5294 i.suffix = BYTE_MNEM_SUFFIX;
5295 }
381d071f
L		 5296
5297 if (!i.suffix)
5298 {
5299 int op;
5300
20592a94
L		 5301 if (i.tm.base_opcode == 0xf20f38f1
5302 || i.tm.base_opcode == 0xf20f38f0)
5303 {
5304 /* We have to know the operand size for crc32. */
5305 as_bad (_("ambiguous memory operand size for `%s`"),
5306 i.tm.name);
5307 return 0;
5308 }
5309
381d071f 5310 for (op = i.operands; --op >= 0;)
40fb9820 5311 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5312 {
40fb9820
L		 5313 if (i.types[op].bitfield.reg8)
5314 {
5315 i.suffix = BYTE_MNEM_SUFFIX;
5316 break;
5317 }
5318 else if (i.types[op].bitfield.reg16)
5319 {
5320 i.suffix = WORD_MNEM_SUFFIX;
5321 break;
5322 }
5323 else if (i.types[op].bitfield.reg32)
5324 {
5325 i.suffix = LONG_MNEM_SUFFIX;
5326 break;
5327 }
5328 else if (i.types[op].bitfield.reg64)
5329 {
5330 i.suffix = QWORD_MNEM_SUFFIX;
5331 break;
5332 }
381d071f
L		 5333 }
5334 }
29b0f896
AM		 5335 }
5336 else if (i.suffix == BYTE_MNEM_SUFFIX)
5337 {
2eb952a4
L		 5338 if (intel_syntax
5339 && i.tm.opcode_modifier.ignoresize
5340 && i.tm.opcode_modifier.no_bsuf)
5341 i.suffix = 0;
5342 else if (!check_byte_reg ())
29b0f896
AM		 5343 return 0;
5344 }
5345 else if (i.suffix == LONG_MNEM_SUFFIX)
5346 {
2eb952a4
L		 5347 if (intel_syntax
5348 && i.tm.opcode_modifier.ignoresize
5349 && i.tm.opcode_modifier.no_lsuf)
5350 i.suffix = 0;
5351 else if (!check_long_reg ())
29b0f896
AM		 5352 return 0;
5353 }
5354 else if (i.suffix == QWORD_MNEM_SUFFIX)
5355 {
955e1e6a
L		 5356 if (intel_syntax
5357 && i.tm.opcode_modifier.ignoresize
5358 && i.tm.opcode_modifier.no_qsuf)
5359 i.suffix = 0;
5360 else if (!check_qword_reg ())
29b0f896
AM		 5361 return 0;
5362 }
5363 else if (i.suffix == WORD_MNEM_SUFFIX)
5364 {
2eb952a4
L		 5365 if (intel_syntax
5366 && i.tm.opcode_modifier.ignoresize
5367 && i.tm.opcode_modifier.no_wsuf)
5368 i.suffix = 0;
5369 else if (!check_word_reg ())
29b0f896
AM		 5370 return 0;
5371 }
c0f3af97 5372 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5373 || i.suffix == YMMWORD_MNEM_SUFFIX
5374 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5375 {
43234a1e 5376 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5377 should check if it is a valid suffix. */
5378 }
40fb9820 5379 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5380 /* Do nothing if the instruction is going to ignore the prefix. */
5381 ;
5382 else
5383 abort ();
5384 }
40fb9820 5385 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5386 && !i.suffix
5387 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5388 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5389 {
5390 i.suffix = stackop_size;
5391 }
9306ca4a
JB		 5392 else if (intel_syntax
5393 && !i.suffix
40fb9820
L		 5394 && (i.tm.operand_types[0].bitfield.jumpabsolute
5395 || i.tm.opcode_modifier.jumpbyte
5396 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5397 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5398 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5399 {
5400 switch (flag_code)
5401 {
5402 case CODE_64BIT:
40fb9820 5403 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5404 {
5405 i.suffix = QWORD_MNEM_SUFFIX;
5406 break;
5407 }
1a0670f3 5408 /* Fall through. */
9306ca4a 5409 case CODE_32BIT:
40fb9820 5410 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5411 i.suffix = LONG_MNEM_SUFFIX;
5412 break;
5413 case CODE_16BIT:
40fb9820 5414 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5415 i.suffix = WORD_MNEM_SUFFIX;
5416 break;
5417 }
5418 }
252b5132 5419
9306ca4a 5420 if (!i.suffix)
29b0f896 5421 {
9306ca4a
JB		 5422 if (!intel_syntax)
5423 {
40fb9820 5424 if (i.tm.opcode_modifier.w)
9306ca4a 5425 {
4eed87de
AM		 5426 as_bad (_("no instruction mnemonic suffix given and "
5427 "no register operands; can't size instruction"));
9306ca4a
JB		 5428 return 0;
5429 }
5430 }
5431 else
5432 {
40fb9820 5433 unsigned int suffixes;
7ab9ffdd 5434
40fb9820
L		 5435 suffixes = !i.tm.opcode_modifier.no_bsuf;
5436 if (!i.tm.opcode_modifier.no_wsuf)
5437 suffixes |= 1 << 1;
5438 if (!i.tm.opcode_modifier.no_lsuf)
5439 suffixes |= 1 << 2;
fc4adea1 5440 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5441 suffixes |= 1 << 3;
5442 if (!i.tm.opcode_modifier.no_ssuf)
5443 suffixes |= 1 << 4;
5444 if (!i.tm.opcode_modifier.no_qsuf)
5445 suffixes |= 1 << 5;
5446
5447 /* There are more than suffix matches. */
5448 if (i.tm.opcode_modifier.w
9306ca4a 5449 || ((suffixes & (suffixes - 1))
40fb9820
L		 5450 && !i.tm.opcode_modifier.defaultsize
5451 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5452 {
5453 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5454 return 0;
5455 }
5456 }
29b0f896 5457 }
252b5132 5458
9306ca4a
JB		 5459 /* Change the opcode based on the operand size given by i.suffix;
5460 We don't need to change things for byte insns. */
5461
582d5edd
L		 5462 if (i.suffix
5463 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5464 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5465 && i.suffix != YMMWORD_MNEM_SUFFIX
5466 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5467 {
5468 /* It's not a byte, select word/dword operation. */
40fb9820 5469 if (i.tm.opcode_modifier.w)
29b0f896 5470 {
40fb9820 5471 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5472 i.tm.base_opcode |= 8;
5473 else
5474 i.tm.base_opcode |= 1;
5475 }
0f3f3d8b 5476
29b0f896
AM		 5477 /* Now select between word & dword operations via the operand
5478 size prefix, except for instructions that will ignore this
5479 prefix anyway. */
ca61edf2 5480 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5481 {
ca61edf2
L		 5482 /* The address size override prefix changes the size of the
5483 first operand. */
40fb9820
L		 5484 if ((flag_code == CODE_32BIT
5485 && i.op->regs[0].reg_type.bitfield.reg16)
5486 || (flag_code != CODE_32BIT
5487 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5488 if (!add_prefix (ADDR_PREFIX_OPCODE))
5489 return 0;
5490 }
5491 else if (i.suffix != QWORD_MNEM_SUFFIX
5492 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5493 && !i.tm.opcode_modifier.ignoresize
5494 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5495 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5496 || (flag_code == CODE_64BIT
40fb9820 5497 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5498 {
5499 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5500
40fb9820 5501 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5502 prefix = ADDR_PREFIX_OPCODE;
252b5132 5503
29b0f896
AM		 5504 if (!add_prefix (prefix))
5505 return 0;
24eab124 5506 }
252b5132 5507
29b0f896
AM		 5508 /* Set mode64 for an operand. */
5509 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5510 && flag_code == CODE_64BIT
40fb9820 5511 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5512 {
5513 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5514 need rex64. cmpxchg8b is also a special case. */
5515 if (! (i.operands == 2
5516 && i.tm.base_opcode == 0x90
5517 && i.tm.extension_opcode == None
0dfbf9d7
L		 5518 && operand_type_equal (&i.types [0], &acc64)
5519 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5520 && ! (i.operands == 1
5521 && i.tm.base_opcode == 0xfc7
5522 && i.tm.extension_opcode == 1
40fb9820
L		 5523 && !operand_type_check (i.types [0], reg)
5524 && operand_type_check (i.types [0], anymem)))
f6bee062 5525 i.rex |= REX_W;
46e883c5 5526 }
3e73aa7c 5527
29b0f896
AM		 5528 /* Size floating point instruction. */
5529 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5530 if (i.tm.opcode_modifier.floatmf)
543613e9 5531 i.tm.base_opcode ^= 4;
29b0f896 5532 }
7ecd2f8b 5533
29b0f896
AM		 5534 return 1;
5535}
3e73aa7c 5536
29b0f896 5537static int
543613e9 5538check_byte_reg (void)
29b0f896
AM		 5539{
5540 int op;
543613e9 5541
29b0f896
AM		 5542 for (op = i.operands; --op >= 0;)
5543 {
5544 /* If this is an eight bit register, it's OK. If it's the 16 or
5545 32 bit version of an eight bit register, we will just use the
5546 low portion, and that's OK too. */
40fb9820 5547 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5548 continue;
5549
5a819eb9
JB		 5550 /* I/O port address operands are OK too. */
5551 if (i.tm.operand_types[op].bitfield.inoutportreg)
5552 continue;
5553
9344ff29
L		 5554 /* crc32 doesn't generate this warning. */
5555 if (i.tm.base_opcode == 0xf20f38f0)
5556 continue;
5557
40fb9820
L		 5558 if ((i.types[op].bitfield.reg16
5559 || i.types[op].bitfield.reg32
5560 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5561 && i.op[op].regs->reg_num < 4
5562 /* Prohibit these changes in 64bit mode, since the lowering
5563 would be more complicated. */
5564 && flag_code != CODE_64BIT)
29b0f896 5565 {
29b0f896 5566#if REGISTER_WARNINGS
5a819eb9 5567 if (!quiet_warnings)
a540244d
L		 5568 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5569 register_prefix,
40fb9820 5570 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5571 ? REGNAM_AL - REGNAM_AX
5572 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5573 register_prefix,
29b0f896
AM		 5574 i.op[op].regs->reg_name,
5575 i.suffix);
5576#endif
5577 continue;
5578 }
5579 /* Any other register is bad. */
40fb9820
L		 5580 if (i.types[op].bitfield.reg16
5581 || i.types[op].bitfield.reg32
5582 || i.types[op].bitfield.reg64
5583 || i.types[op].bitfield.regmmx
5584 || i.types[op].bitfield.regxmm
c0f3af97 5585 || i.types[op].bitfield.regymm
43234a1e 5586 || i.types[op].bitfield.regzmm
40fb9820
L		 5587 || i.types[op].bitfield.sreg2
5588 || i.types[op].bitfield.sreg3
5589 || i.types[op].bitfield.control
5590 || i.types[op].bitfield.debug
5591 || i.types[op].bitfield.test
5592 || i.types[op].bitfield.floatreg
5593 || i.types[op].bitfield.floatacc)
29b0f896 5594 {
a540244d
L		 5595 as_bad (_("`%s%s' not allowed with `%s%c'"),
5596 register_prefix,
29b0f896
AM		 5597 i.op[op].regs->reg_name,
5598 i.tm.name,
5599 i.suffix);
5600 return 0;
5601 }
5602 }
5603 return 1;
5604}
5605
5606static int
e3bb37b5 5607check_long_reg (void)
29b0f896
AM		 5608{
5609 int op;
5610
5611 for (op = i.operands; --op >= 0;)
5612 /* Reject eight bit registers, except where the template requires
5613 them. (eg. movzb) */
40fb9820
L		 5614 if (i.types[op].bitfield.reg8
5615 && (i.tm.operand_types[op].bitfield.reg16
5616 || i.tm.operand_types[op].bitfield.reg32
5617 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5618 {
a540244d
L		 5619 as_bad (_("`%s%s' not allowed with `%s%c'"),
5620 register_prefix,
29b0f896
AM		 5621 i.op[op].regs->reg_name,
5622 i.tm.name,
5623 i.suffix);
5624 return 0;
5625 }
e4630f71 5626 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5627 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5628 && i.types[op].bitfield.reg16
5629 && (i.tm.operand_types[op].bitfield.reg32
5630 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5631 {
5632 /* Prohibit these changes in the 64bit mode, since the
5633 lowering is more complicated. */
5634 if (flag_code == CODE_64BIT)
252b5132 5635 {
2b5d6a91 5636 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5637 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5638 i.suffix);
5639 return 0;
252b5132 5640 }
29b0f896 5641#if REGISTER_WARNINGS
cecf1424
JB		 5642 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5643 register_prefix,
5644 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5645 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5646#endif
252b5132 5647 }
e4630f71 5648 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5649 else if (i.types[op].bitfield.reg64
5650 && (i.tm.operand_types[op].bitfield.reg32
5651 || i.tm.operand_types[op].bitfield.acc))
252b5132 5652 {
34828aad 5653 if (intel_syntax
ca61edf2 5654 && i.tm.opcode_modifier.toqword
40fb9820 5655 && !i.types[0].bitfield.regxmm)
34828aad 5656 {
ca61edf2 5657 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5658 i.suffix = QWORD_MNEM_SUFFIX;
5659 }
5660 else
5661 {
2b5d6a91 5662 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5663 register_prefix, i.op[op].regs->reg_name,
5664 i.suffix);
5665 return 0;
5666 }
29b0f896
AM		 5667 }
5668 return 1;
5669}
252b5132 5670
29b0f896 5671static int
e3bb37b5 5672check_qword_reg (void)
29b0f896
AM		 5673{
5674 int op;
252b5132 5675
29b0f896
AM		 5676 for (op = i.operands; --op >= 0; )
5677 /* Reject eight bit registers, except where the template requires
5678 them. (eg. movzb) */
40fb9820
L		 5679 if (i.types[op].bitfield.reg8
5680 && (i.tm.operand_types[op].bitfield.reg16
5681 || i.tm.operand_types[op].bitfield.reg32
5682 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5683 {
a540244d
L		 5684 as_bad (_("`%s%s' not allowed with `%s%c'"),
5685 register_prefix,
29b0f896
AM		 5686 i.op[op].regs->reg_name,
5687 i.tm.name,
5688 i.suffix);
5689 return 0;
5690 }
e4630f71 5691 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5692 else if ((i.types[op].bitfield.reg16
5693 || i.types[op].bitfield.reg32)
33d0ab95 5694 && (i.tm.operand_types[op].bitfield.reg64
40fb9820 5695 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5696 {
5697 /* Prohibit these changes in the 64bit mode, since the
5698 lowering is more complicated. */
34828aad 5699 if (intel_syntax
ca61edf2 5700 && i.tm.opcode_modifier.todword
40fb9820 5701 && !i.types[0].bitfield.regxmm)
34828aad 5702 {
ca61edf2 5703 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5704 i.suffix = LONG_MNEM_SUFFIX;
5705 }
5706 else
5707 {
2b5d6a91 5708 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5709 register_prefix, i.op[op].regs->reg_name,
5710 i.suffix);
5711 return 0;
5712 }
252b5132 5713 }
29b0f896
AM		 5714 return 1;
5715}
252b5132 5716
29b0f896 5717static int
e3bb37b5 5718check_word_reg (void)
29b0f896
AM		 5719{
5720 int op;
5721 for (op = i.operands; --op >= 0;)
5722 /* Reject eight bit registers, except where the template requires
5723 them. (eg. movzb) */
40fb9820
L		 5724 if (i.types[op].bitfield.reg8
5725 && (i.tm.operand_types[op].bitfield.reg16
5726 || i.tm.operand_types[op].bitfield.reg32
5727 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5728 {
a540244d
L		 5729 as_bad (_("`%s%s' not allowed with `%s%c'"),
5730 register_prefix,
29b0f896
AM		 5731 i.op[op].regs->reg_name,
5732 i.tm.name,
5733 i.suffix);
5734 return 0;
5735 }
e4630f71 5736 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5737 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5738 && (i.types[op].bitfield.reg32
5739 || i.types[op].bitfield.reg64)
40fb9820
L		 5740 && (i.tm.operand_types[op].bitfield.reg16
5741 || i.tm.operand_types[op].bitfield.acc))
252b5132 5742 {
29b0f896
AM		 5743 /* Prohibit these changes in the 64bit mode, since the
5744 lowering is more complicated. */
5745 if (flag_code == CODE_64BIT)
252b5132 5746 {
2b5d6a91 5747 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5748 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5749 i.suffix);
5750 return 0;
252b5132 5751 }
29b0f896 5752#if REGISTER_WARNINGS
cecf1424
JB		 5753 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5754 register_prefix,
5755 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5756 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5757#endif
5758 }
5759 return 1;
5760}
252b5132 5761
29b0f896 5762static int
40fb9820 5763update_imm (unsigned int j)
29b0f896 5764{
bc0844ae 5765 i386_operand_type overlap = i.types[j];
40fb9820
L		 5766 if ((overlap.bitfield.imm8
5767 || overlap.bitfield.imm8s
5768 || overlap.bitfield.imm16
5769 || overlap.bitfield.imm32
5770 || overlap.bitfield.imm32s
5771 || overlap.bitfield.imm64)
0dfbf9d7
L		 5772 && !operand_type_equal (&overlap, &imm8)
5773 && !operand_type_equal (&overlap, &imm8s)
5774 && !operand_type_equal (&overlap, &imm16)
5775 && !operand_type_equal (&overlap, &imm32)
5776 && !operand_type_equal (&overlap, &imm32s)
5777 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5778 {
5779 if (i.suffix)
5780 {
40fb9820
L		 5781 i386_operand_type temp;
5782
0dfbf9d7 5783 operand_type_set (&temp, 0);
7ab9ffdd 5784 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5785 {
5786 temp.bitfield.imm8 = overlap.bitfield.imm8;
5787 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5788 }
5789 else if (i.suffix == WORD_MNEM_SUFFIX)
5790 temp.bitfield.imm16 = overlap.bitfield.imm16;
5791 else if (i.suffix == QWORD_MNEM_SUFFIX)
5792 {
5793 temp.bitfield.imm64 = overlap.bitfield.imm64;
5794 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5795 }
5796 else
5797 temp.bitfield.imm32 = overlap.bitfield.imm32;
5798 overlap = temp;
29b0f896 5799 }
0dfbf9d7
L		 5800 else if (operand_type_equal (&overlap, &imm16_32_32s)
5801 || operand_type_equal (&overlap, &imm16_32)
5802 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5803 {
40fb9820 5804 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5805 overlap = imm16;
40fb9820 5806 else
65da13b5 5807 overlap = imm32s;
29b0f896 5808 }
0dfbf9d7
L		 5809 if (!operand_type_equal (&overlap, &imm8)
5810 && !operand_type_equal (&overlap, &imm8s)
5811 && !operand_type_equal (&overlap, &imm16)
5812 && !operand_type_equal (&overlap, &imm32)
5813 && !operand_type_equal (&overlap, &imm32s)
5814 && !operand_type_equal (&overlap, &imm64))
29b0f896 5815 {
4eed87de
AM		 5816 as_bad (_("no instruction mnemonic suffix given; "
5817 "can't determine immediate size"));
29b0f896
AM		 5818 return 0;
5819 }
5820 }
40fb9820 5821 i.types[j] = overlap;
29b0f896 5822
40fb9820
L		 5823 return 1;
5824}
5825
5826static int
5827finalize_imm (void)
5828{
bc0844ae 5829 unsigned int j, n;
29b0f896 5830
bc0844ae
L		 5831 /* Update the first 2 immediate operands. */
5832 n = i.operands > 2 ? 2 : i.operands;
5833 if (n)
5834 {
5835 for (j = 0; j < n; j++)
5836 if (update_imm (j) == 0)
5837 return 0;
40fb9820 5838
bc0844ae
L		 5839 /* The 3rd operand can't be immediate operand. */
5840 gas_assert (operand_type_check (i.types[2], imm) == 0);
5841 }
29b0f896
AM		 5842
5843 return 1;
5844}
5845
c0f3af97
L		 5846static int
5847bad_implicit_operand (int xmm)
5848{
91d6fa6a
NC		 5849 const char *ireg = xmm ? "xmm0" : "ymm0";
5850
c0f3af97
L		 5851 if (intel_syntax)
5852 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5853 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5854 else
5855 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5856 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5857 return 0;
5858}
5859
29b0f896 5860static int
e3bb37b5 5861process_operands (void)
29b0f896
AM		 5862{
5863 /* Default segment register this instruction will use for memory
5864 accesses. 0 means unknown. This is only for optimizing out
5865 unnecessary segment overrides. */
5866 const seg_entry *default_seg = 0;
5867
2426c15f 5868 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5869 {
91d6fa6a
NC		 5870 unsigned int dupl = i.operands;
5871 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5872 unsigned int j;
5873
c0f3af97 5874 /* The destination must be an xmm register. */
9c2799c2 5875 gas_assert (i.reg_operands
91d6fa6a 5876 && MAX_OPERANDS > dupl
7ab9ffdd 5877 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5878
5879 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5880 {
c0f3af97 5881 /* The first operand is implicit and must be xmm0. */
9c2799c2 5882 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5883 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5884 return bad_implicit_operand (1);
5885
8cd7925b 5886 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5887 {
5888 /* Keep xmm0 for instructions with VEX prefix and 3
5889 sources. */
5890 goto duplicate;
5891 }
e2ec9d29 5892 else
c0f3af97
L		 5893 {
5894 /* We remove the first xmm0 and keep the number of
5895 operands unchanged, which in fact duplicates the
5896 destination. */
5897 for (j = 1; j < i.operands; j++)
5898 {
5899 i.op[j - 1] = i.op[j];
5900 i.types[j - 1] = i.types[j];
5901 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5902 }
5903 }
5904 }
5905 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5906 {
91d6fa6a 5907 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5908 && (i.tm.opcode_modifier.vexsources
5909 == VEX3SOURCES));
c0f3af97
L		 5910
5911 /* Add the implicit xmm0 for instructions with VEX prefix
5912 and 3 sources. */
5913 for (j = i.operands; j > 0; j--)
5914 {
5915 i.op[j] = i.op[j - 1];
5916 i.types[j] = i.types[j - 1];
5917 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5918 }
5919 i.op[0].regs
5920 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5921 i.types[0] = regxmm;
c0f3af97
L		 5922 i.tm.operand_types[0] = regxmm;
5923
5924 i.operands += 2;
5925 i.reg_operands += 2;
5926 i.tm.operands += 2;
5927
91d6fa6a 5928 dupl++;
c0f3af97 5929 dest++;
91d6fa6a
NC		 5930 i.op[dupl] = i.op[dest];
5931 i.types[dupl] = i.types[dest];
5932 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5933 }
c0f3af97
L		 5934 else
5935 {
5936duplicate:
5937 i.operands++;
5938 i.reg_operands++;
5939 i.tm.operands++;
5940
91d6fa6a
NC		 5941 i.op[dupl] = i.op[dest];
5942 i.types[dupl] = i.types[dest];
5943 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5944 }
5945
5946 if (i.tm.opcode_modifier.immext)
5947 process_immext ();
5948 }
5949 else if (i.tm.opcode_modifier.firstxmm0)
5950 {
5951 unsigned int j;
5952
43234a1e 5953 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5954 gas_assert (i.reg_operands
7ab9ffdd 5955 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5956 || operand_type_equal (&i.types[0], &regymm)
5957 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5958 if (register_number (i.op[0].regs) != 0)
c0f3af97 5959 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5960
5961 for (j = 1; j < i.operands; j++)
5962 {
5963 i.op[j - 1] = i.op[j];
5964 i.types[j - 1] = i.types[j];
5965
5966 /* We need to adjust fields in i.tm since they are used by
5967 build_modrm_byte. */
5968 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5969 }
5970
e2ec9d29
L		 5971 i.operands--;
5972 i.reg_operands--;
e2ec9d29
L		 5973 i.tm.operands--;
5974 }
920d2ddc
IT		 5975 else if (i.tm.opcode_modifier.implicitquadgroup)
5976 {
5977 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
5978 gas_assert (i.operands >= 2
5979 && (operand_type_equal (&i.types[1], &regxmm)
5980 || operand_type_equal (&i.types[1], &regymm)
5981 || operand_type_equal (&i.types[1], &regzmm)));
5982 unsigned int regnum = register_number (i.op[1].regs);
5983 unsigned int first_reg_in_group = regnum & ~3;
5984 unsigned int last_reg_in_group = first_reg_in_group + 3;
5985 if (regnum != first_reg_in_group) {
5986 as_warn (_("the second source register `%s%s' implicitly denotes"
5987 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
5988 register_prefix, i.op[1].regs->reg_name,
5989 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
5990 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
5991 i.tm.name);
5992 }
5993 }
e2ec9d29
L		 5994 else if (i.tm.opcode_modifier.regkludge)
5995 {
5996 /* The imul $imm, %reg instruction is converted into
5997 imul $imm, %reg, %reg, and the clr %reg instruction
5998 is converted into xor %reg, %reg. */
5999
6000 unsigned int first_reg_op;
6001
6002 if (operand_type_check (i.types[0], reg))
6003 first_reg_op = 0;
6004 else
6005 first_reg_op = 1;
6006 /* Pretend we saw the extra register operand. */
9c2799c2 6007 gas_assert (i.reg_operands == 1
7ab9ffdd 6008 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6009 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6010 i.types[first_reg_op + 1] = i.types[first_reg_op];
6011 i.operands++;
6012 i.reg_operands++;
29b0f896
AM		 6013 }
6014
40fb9820 6015 if (i.tm.opcode_modifier.shortform)
29b0f896 6016 {
40fb9820
L		 6017 if (i.types[0].bitfield.sreg2
6018 || i.types[0].bitfield.sreg3)
29b0f896 6019 {
4eed87de
AM		 6020 if (i.tm.base_opcode == POP_SEG_SHORT
6021 && i.op[0].regs->reg_num == 1)
29b0f896 6022 {
a87af027 6023 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6024 return 0;
29b0f896 6025 }
4eed87de
AM		 6026 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6027 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6028 i.rex |= REX_B;
4eed87de
AM		 6029 }
6030 else
6031 {
7ab9ffdd 6032 /* The register or float register operand is in operand
85f10a01 6033 0 or 1. */
40fb9820 6034 unsigned int op;
7ab9ffdd
L		 6035
6036 if (i.types[0].bitfield.floatreg
6037 || operand_type_check (i.types[0], reg))
6038 op = 0;
6039 else
6040 op = 1;
4eed87de
AM		 6041 /* Register goes in low 3 bits of opcode. */
6042 i.tm.base_opcode |= i.op[op].regs->reg_num;
6043 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6044 i.rex |= REX_B;
40fb9820 6045 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6046 {
4eed87de
AM		 6047 /* Warn about some common errors, but press on regardless.
6048 The first case can be generated by gcc (<= 2.8.1). */
6049 if (i.operands == 2)
6050 {
6051 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6052 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6053 register_prefix, i.op[!intel_syntax].regs->reg_name,
6054 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6055 }
6056 else
6057 {
6058 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6059 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6060 register_prefix, i.op[0].regs->reg_name);
4eed87de 6061 }
29b0f896
AM		 6062 }
6063 }
6064 }
40fb9820 6065 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6066 {
6067 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6068 must be put into the modrm byte). Now, we make the modrm and
6069 index base bytes based on all the info we've collected. */
29b0f896
AM		 6070
6071 default_seg = build_modrm_byte ();
6072 }
8a2ed489 6073 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6074 {
6075 default_seg = &ds;
6076 }
40fb9820 6077 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6078 {
6079 /* For the string instructions that allow a segment override
6080 on one of their operands, the default segment is ds. */
6081 default_seg = &ds;
6082 }
6083
75178d9d
L		 6084 if (i.tm.base_opcode == 0x8d /* lea */
6085 && i.seg[0]
6086 && !quiet_warnings)
30123838 6087 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6088
6089 /* If a segment was explicitly specified, and the specified segment
6090 is not the default, use an opcode prefix to select it. If we
6091 never figured out what the default segment is, then default_seg
6092 will be zero at this point, and the specified segment prefix will
6093 always be used. */
29b0f896
AM		 6094 if ((i.seg[0]) && (i.seg[0] != default_seg))
6095 {
6096 if (!add_prefix (i.seg[0]->seg_prefix))
6097 return 0;
6098 }
6099 return 1;
6100}
6101
6102static const seg_entry *
e3bb37b5 6103build_modrm_byte (void)
29b0f896
AM		 6104{
6105 const seg_entry *default_seg = 0;
c0f3af97 6106 unsigned int source, dest;
8cd7925b 6107 int vex_3_sources;
c0f3af97
L		 6108
6109 /* The first operand of instructions with VEX prefix and 3 sources
6110 must be VEX_Imm4. */
8cd7925b 6111 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6112 if (vex_3_sources)
6113 {
91d6fa6a 6114 unsigned int nds, reg_slot;
4c2c6516 6115 expressionS *exp;
c0f3af97 6116
922d8de8 6117 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6118 && i.tm.opcode_modifier.immext)
6119 {
6120 dest = i.operands - 2;
6121 gas_assert (dest == 3);
6122 }
922d8de8 6123 else
a683cc34 6124 dest = i.operands - 1;
c0f3af97 6125 nds = dest - 1;
922d8de8 6126
a683cc34
SP		 6127 /* There are 2 kinds of instructions:
6128 1. 5 operands: 4 register operands or 3 register operands
6129 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6130 VexW0 or VexW1. The destination must be either XMM, YMM or
6131 ZMM register.
a683cc34
SP		 6132 2. 4 operands: 4 register operands or 3 register operands
6133 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6134 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6135 || (i.reg_operands == 3 && i.mem_operands == 1))
6136 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6137 && (i.tm.opcode_modifier.veximmext
6138 || (i.imm_operands == 1
6139 && i.types[0].bitfield.vec_imm4
6140 && (i.tm.opcode_modifier.vexw == VEXW0
6141 || i.tm.opcode_modifier.vexw == VEXW1)
6142 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6143 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6144 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6145
6146 if (i.imm_operands == 0)
6147 {
6148 /* When there is no immediate operand, generate an 8bit
6149 immediate operand to encode the first operand. */
6150 exp = &im_expressions[i.imm_operands++];
6151 i.op[i.operands].imms = exp;
6152 i.types[i.operands] = imm8;
6153 i.operands++;
6154 /* If VexW1 is set, the first operand is the source and
6155 the second operand is encoded in the immediate operand. */
6156 if (i.tm.opcode_modifier.vexw == VEXW1)
6157 {
6158 source = 0;
6159 reg_slot = 1;
6160 }
6161 else
6162 {
6163 source = 1;
6164 reg_slot = 0;
6165 }
6166
6167 /* FMA swaps REG and NDS. */
6168 if (i.tm.cpu_flags.bitfield.cpufma)
6169 {
6170 unsigned int tmp;
6171 tmp = reg_slot;
6172 reg_slot = nds;
6173 nds = tmp;
6174 }
6175
24981e7b
L		 6176 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6177 &regxmm)
a683cc34 6178 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6179 &regymm)
6180 || operand_type_equal (&i.tm.operand_types[reg_slot],
6181 &regzmm));
a683cc34 6182 exp->X_op = O_constant;
4c692bc7 6183 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6184 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6185 }
922d8de8 6186 else
a683cc34
SP		 6187 {
6188 unsigned int imm_slot;
6189
6190 if (i.tm.opcode_modifier.vexw == VEXW0)
6191 {
6192 /* If VexW0 is set, the third operand is the source and
6193 the second operand is encoded in the immediate
6194 operand. */
6195 source = 2;
6196 reg_slot = 1;
6197 }
6198 else
6199 {
6200 /* VexW1 is set, the second operand is the source and
6201 the third operand is encoded in the immediate
6202 operand. */
6203 source = 1;
6204 reg_slot = 2;
6205 }
6206
6207 if (i.tm.opcode_modifier.immext)
6208 {
6209 /* When ImmExt is set, the immdiate byte is the last
6210 operand. */
6211 imm_slot = i.operands - 1;
6212 source--;
6213 reg_slot--;
6214 }
6215 else
6216 {
6217 imm_slot = 0;
6218
6219 /* Turn on Imm8 so that output_imm will generate it. */
6220 i.types[imm_slot].bitfield.imm8 = 1;
6221 }
6222
24981e7b
L		 6223 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6224 &regxmm)
6225 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6226 &regymm)
6227 || operand_type_equal (&i.tm.operand_types[reg_slot],
6228 &regzmm));
a683cc34 6229 i.op[imm_slot].imms->X_add_number
4c692bc7 6230 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6231 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6232 }
6233
6234 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6235 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6236 &regymm)
6237 || operand_type_equal (&i.tm.operand_types[nds],
6238 &regzmm));
dae39acc 6239 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6240 }
6241 else
6242 source = dest = 0;
29b0f896
AM		 6243
6244 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6245 implicit registers do not count. If there are 3 register
6246 operands, it must be a instruction with VexNDS. For a
6247 instruction with VexNDD, the destination register is encoded
6248 in VEX prefix. If there are 4 register operands, it must be
6249 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6250 if (i.mem_operands == 0
6251 && ((i.reg_operands == 2
2426c15f 6252 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6253 || (i.reg_operands == 3
2426c15f 6254 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6255 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6256 {
cab737b9
L		 6257 switch (i.operands)
6258 {
6259 case 2:
6260 source = 0;
6261 break;
6262 case 3:
c81128dc
L		 6263 /* When there are 3 operands, one of them may be immediate,
6264 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6265 the first operand must be shift count register (cl) or it
6266 is an instruction with VexNDS. */
9c2799c2 6267 gas_assert (i.imm_operands == 1
7ab9ffdd 6268 || (i.imm_operands == 0
2426c15f 6269 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6270 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6271 if (operand_type_check (i.types[0], imm)
6272 || i.types[0].bitfield.shiftcount)
6273 source = 1;
6274 else
6275 source = 0;
cab737b9
L		 6276 break;
6277 case 4:
368d64cc
L		 6278 /* When there are 4 operands, the first two must be 8bit
6279 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6280 one.
6281
6282 For instructions with VexNDS, if the first operand
6283 an imm8, the source operand is the 2nd one. If the last
6284 operand is imm8, the source operand is the first one. */
9c2799c2 6285 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6286 && i.types[0].bitfield.imm8
6287 && i.types[1].bitfield.imm8)
2426c15f 6288 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6289 && i.imm_operands == 1
6290 && (i.types[0].bitfield.imm8
43234a1e
L		 6291 || i.types[i.operands - 1].bitfield.imm8
6292 || i.rounding)));
9f2670f2
L		 6293 if (i.imm_operands == 2)
6294 source = 2;
6295 else
c0f3af97
L		 6296 {
6297 if (i.types[0].bitfield.imm8)
6298 source = 1;
6299 else
6300 source = 0;
6301 }
c0f3af97
L		 6302 break;
6303 case 5:
43234a1e
L		 6304 if (i.tm.opcode_modifier.evex)
6305 {
6306 /* For EVEX instructions, when there are 5 operands, the
6307 first one must be immediate operand. If the second one
6308 is immediate operand, the source operand is the 3th
6309 one. If the last one is immediate operand, the source
6310 operand is the 2nd one. */
6311 gas_assert (i.imm_operands == 2
6312 && i.tm.opcode_modifier.sae
6313 && operand_type_check (i.types[0], imm));
6314 if (operand_type_check (i.types[1], imm))
6315 source = 2;
6316 else if (operand_type_check (i.types[4], imm))
6317 source = 1;
6318 else
6319 abort ();
6320 }
cab737b9
L		 6321 break;
6322 default:
6323 abort ();
6324 }
6325
c0f3af97
L		 6326 if (!vex_3_sources)
6327 {
6328 dest = source + 1;
6329
43234a1e
L		 6330 /* RC/SAE operand could be between DEST and SRC. That happens
6331 when one operand is GPR and the other one is XMM/YMM/ZMM
6332 register. */
6333 if (i.rounding && i.rounding->operand == (int) dest)
6334 dest++;
6335
2426c15f 6336 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6337 {
43234a1e
L		 6338 /* For instructions with VexNDS, the register-only source
6339 operand must be 32/64bit integer, XMM, YMM or ZMM
6340 register. It is encoded in VEX prefix. We need to
6341 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6342
6343 i386_operand_type op;
6344 unsigned int vvvv;
6345
6346 /* Check register-only source operand when two source
6347 operands are swapped. */
6348 if (!i.tm.operand_types[source].bitfield.baseindex
6349 && i.tm.operand_types[dest].bitfield.baseindex)
6350 {
6351 vvvv = source;
6352 source = dest;
6353 }
6354 else
6355 vvvv = dest;
6356
6357 op = i.tm.operand_types[vvvv];
fa99fab2 6358 op.bitfield.regmem = 0;
c0f3af97 6359 if ((dest + 1) >= i.operands
ac4eb736
AM		 6360 || (!op.bitfield.reg32
6361 && op.bitfield.reg64
f12dc422 6362 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6363 && !operand_type_equal (&op, &regymm)
6364 && !operand_type_equal (&op, &regzmm)
6365 && !operand_type_equal (&op, &regmask)))
c0f3af97 6366 abort ();
f12dc422 6367 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6368 dest++;
6369 }
6370 }
29b0f896
AM		 6371
6372 i.rm.mode = 3;
6373 /* One of the register operands will be encoded in the i.tm.reg
6374 field, the other in the combined i.tm.mode and i.tm.regmem
6375 fields. If no form of this instruction supports a memory
6376 destination operand, then we assume the source operand may
6377 sometimes be a memory operand and so we need to store the
6378 destination in the i.rm.reg field. */
40fb9820
L		 6379 if (!i.tm.operand_types[dest].bitfield.regmem
6380 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6381 {
6382 i.rm.reg = i.op[dest].regs->reg_num;
6383 i.rm.regmem = i.op[source].regs->reg_num;
6384 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6385 i.rex |= REX_R;
43234a1e
L		 6386 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6387 i.vrex |= REX_R;
29b0f896 6388 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6389 i.rex |= REX_B;
43234a1e
L		 6390 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6391 i.vrex |= REX_B;
29b0f896
AM		 6392 }
6393 else
6394 {
6395 i.rm.reg = i.op[source].regs->reg_num;
6396 i.rm.regmem = i.op[dest].regs->reg_num;
6397 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6398 i.rex |= REX_B;
43234a1e
L		 6399 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6400 i.vrex |= REX_B;
29b0f896 6401 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6402 i.rex |= REX_R;
43234a1e
L		 6403 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6404 i.vrex |= REX_R;
29b0f896 6405 }
161a04f6 6406 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6407 {
40fb9820
L		 6408 if (!i.types[0].bitfield.control
6409 && !i.types[1].bitfield.control)
c4a530c5 6410 abort ();
161a04f6 6411 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6412 add_prefix (LOCK_PREFIX_OPCODE);
6413 }
29b0f896
AM		 6414 }
6415 else
6416 { /* If it's not 2 reg operands... */
c0f3af97
L		 6417 unsigned int mem;
6418
29b0f896
AM		 6419 if (i.mem_operands)
6420 {
6421 unsigned int fake_zero_displacement = 0;
99018f42 6422 unsigned int op;
4eed87de 6423
7ab9ffdd
L		 6424 for (op = 0; op < i.operands; op++)
6425 if (operand_type_check (i.types[op], anymem))
6426 break;
7ab9ffdd 6427 gas_assert (op < i.operands);
29b0f896 6428
6c30d220
L		 6429 if (i.tm.opcode_modifier.vecsib)
6430 {
6431 if (i.index_reg->reg_num == RegEiz
6432 || i.index_reg->reg_num == RegRiz)
6433 abort ();
6434
6435 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6436 if (!i.base_reg)
6437 {
6438 i.sib.base = NO_BASE_REGISTER;
6439 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6440 /* No Vec_Disp8 if there is no base. */
6441 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6442 i.types[op].bitfield.disp8 = 0;
6443 i.types[op].bitfield.disp16 = 0;
6444 i.types[op].bitfield.disp64 = 0;
6445 if (flag_code != CODE_64BIT)
6446 {
6447 /* Must be 32 bit */
6448 i.types[op].bitfield.disp32 = 1;
6449 i.types[op].bitfield.disp32s = 0;
6450 }
6451 else
6452 {
6453 i.types[op].bitfield.disp32 = 0;
6454 i.types[op].bitfield.disp32s = 1;
6455 }
6456 }
6457 i.sib.index = i.index_reg->reg_num;
6458 if ((i.index_reg->reg_flags & RegRex) != 0)
6459 i.rex |= REX_X;
43234a1e
L		 6460 if ((i.index_reg->reg_flags & RegVRex) != 0)
6461 i.vrex |= REX_X;
6c30d220
L		 6462 }
6463
29b0f896
AM		 6464 default_seg = &ds;
6465
6466 if (i.base_reg == 0)
6467 {
6468 i.rm.mode = 0;
6469 if (!i.disp_operands)
6c30d220
L		 6470 {
6471 fake_zero_displacement = 1;
6472 /* Instructions with VSIB byte need 32bit displacement
6473 if there is no base register. */
6474 if (i.tm.opcode_modifier.vecsib)
6475 i.types[op].bitfield.disp32 = 1;
6476 }
29b0f896
AM		 6477 if (i.index_reg == 0)
6478 {
6c30d220 6479 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6480 /* Operand is just <disp> */
20f0a1fc 6481 if (flag_code == CODE_64BIT)
29b0f896
AM		 6482 {
6483 /* 64bit mode overwrites the 32bit absolute
6484 addressing by RIP relative addressing and
6485 absolute addressing is encoded by one of the
6486 redundant SIB forms. */
6487 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6488 i.sib.base = NO_BASE_REGISTER;
6489 i.sib.index = NO_INDEX_REGISTER;
fc225355 6490 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6491 ? disp32s : disp32);
20f0a1fc 6492 }
fc225355
L		 6493 else if ((flag_code == CODE_16BIT)
6494 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6495 {
6496 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6497 i.types[op] = disp16;
20f0a1fc
NC		 6498 }
6499 else
6500 {
6501 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6502 i.types[op] = disp32;
29b0f896
AM		 6503 }
6504 }
6c30d220 6505 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6506 {
6c30d220 6507 /* !i.base_reg && i.index_reg */
db51cc60
L		 6508 if (i.index_reg->reg_num == RegEiz
6509 || i.index_reg->reg_num == RegRiz)
6510 i.sib.index = NO_INDEX_REGISTER;
6511 else
6512 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6513 i.sib.base = NO_BASE_REGISTER;
6514 i.sib.scale = i.log2_scale_factor;
6515 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6516 /* No Vec_Disp8 if there is no base. */
6517 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6518 i.types[op].bitfield.disp8 = 0;
6519 i.types[op].bitfield.disp16 = 0;
6520 i.types[op].bitfield.disp64 = 0;
29b0f896 6521 if (flag_code != CODE_64BIT)
40fb9820
L		 6522 {
6523 /* Must be 32 bit */
6524 i.types[op].bitfield.disp32 = 1;
6525 i.types[op].bitfield.disp32s = 0;
6526 }
29b0f896 6527 else
40fb9820
L		 6528 {
6529 i.types[op].bitfield.disp32 = 0;
6530 i.types[op].bitfield.disp32s = 1;
6531 }
29b0f896 6532 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6533 i.rex |= REX_X;
29b0f896
AM		 6534 }
6535 }
6536 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6537 else if (i.base_reg->reg_num == RegRip ||
6538 i.base_reg->reg_num == RegEip)
29b0f896 6539 {
6c30d220 6540 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6541 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6542 i.types[op].bitfield.disp8 = 0;
6543 i.types[op].bitfield.disp16 = 0;
6544 i.types[op].bitfield.disp32 = 0;
6545 i.types[op].bitfield.disp32s = 1;
6546 i.types[op].bitfield.disp64 = 0;
43234a1e 6547 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6548 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6549 if (! i.disp_operands)
6550 fake_zero_displacement = 1;
29b0f896 6551 }
40fb9820 6552 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6553 {
6c30d220 6554 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6555 switch (i.base_reg->reg_num)
6556 {
6557 case 3: /* (%bx) */
6558 if (i.index_reg == 0)
6559 i.rm.regmem = 7;
6560 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6561 i.rm.regmem = i.index_reg->reg_num - 6;
6562 break;
6563 case 5: /* (%bp) */
6564 default_seg = &ss;
6565 if (i.index_reg == 0)
6566 {
6567 i.rm.regmem = 6;
40fb9820 6568 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6569 {
6570 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6571 if (i.tm.operand_types[op].bitfield.vec_disp8)
6572 i.types[op].bitfield.vec_disp8 = 1;
6573 else
6574 i.types[op].bitfield.disp8 = 1;
252b5132 6575 fake_zero_displacement = 1;
29b0f896
AM		 6576 }
6577 }
6578 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6579 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6580 break;
6581 default: /* (%si) -> 4 or (%di) -> 5 */
6582 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6583 }
6584 i.rm.mode = mode_from_disp_size (i.types[op]);
6585 }
6586 else /* i.base_reg and 32/64 bit mode */
6587 {
6588 if (flag_code == CODE_64BIT
40fb9820
L		 6589 && operand_type_check (i.types[op], disp))
6590 {
6591 i386_operand_type temp;
0dfbf9d7 6592 operand_type_set (&temp, 0);
40fb9820 6593 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6594 temp.bitfield.vec_disp8
6595 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6596 i.types[op] = temp;
6597 if (i.prefix[ADDR_PREFIX] == 0)
6598 i.types[op].bitfield.disp32s = 1;
6599 else
6600 i.types[op].bitfield.disp32 = 1;
6601 }
20f0a1fc 6602
6c30d220
L		 6603 if (!i.tm.opcode_modifier.vecsib)
6604 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6605 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6606 i.rex |= REX_B;
29b0f896
AM		 6607 i.sib.base = i.base_reg->reg_num;
6608 /* x86-64 ignores REX prefix bit here to avoid decoder
6609 complications. */
848930b2
JB		 6610 if (!(i.base_reg->reg_flags & RegRex)
6611 && (i.base_reg->reg_num == EBP_REG_NUM
6612 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6613 default_seg = &ss;
848930b2 6614 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6615 {
848930b2 6616 fake_zero_displacement = 1;
43234a1e
L		 6617 if (i.tm.operand_types [op].bitfield.vec_disp8)
6618 i.types[op].bitfield.vec_disp8 = 1;
6619 else
6620 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6621 }
6622 i.sib.scale = i.log2_scale_factor;
6623 if (i.index_reg == 0)
6624 {
6c30d220 6625 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6626 /* <disp>(%esp) becomes two byte modrm with no index
6627 register. We've already stored the code for esp
6628 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6629 Any base register besides %esp will not use the
6630 extra modrm byte. */
6631 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6632 }
6c30d220 6633 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6634 {
db51cc60
L		 6635 if (i.index_reg->reg_num == RegEiz
6636 || i.index_reg->reg_num == RegRiz)
6637 i.sib.index = NO_INDEX_REGISTER;
6638 else
6639 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6640 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6641 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6642 i.rex |= REX_X;
29b0f896 6643 }
67a4f2b7
AO		 6644
6645 if (i.disp_operands
6646 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6647 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6648 i.rm.mode = 0;
6649 else
a501d77e
L		 6650 {
6651 if (!fake_zero_displacement
6652 && !i.disp_operands
6653 && i.disp_encoding)
6654 {
6655 fake_zero_displacement = 1;
6656 if (i.disp_encoding == disp_encoding_8bit)
6657 i.types[op].bitfield.disp8 = 1;
6658 else
6659 i.types[op].bitfield.disp32 = 1;
6660 }
6661 i.rm.mode = mode_from_disp_size (i.types[op]);
6662 }
29b0f896 6663 }
252b5132 6664
29b0f896
AM		 6665 if (fake_zero_displacement)
6666 {
6667 /* Fakes a zero displacement assuming that i.types[op]
6668 holds the correct displacement size. */
6669 expressionS *exp;
6670
9c2799c2 6671 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6672 exp = &disp_expressions[i.disp_operands++];
6673 i.op[op].disps = exp;
6674 exp->X_op = O_constant;
6675 exp->X_add_number = 0;
6676 exp->X_add_symbol = (symbolS *) 0;
6677 exp->X_op_symbol = (symbolS *) 0;
6678 }
c0f3af97
L		 6679
6680 mem = op;
29b0f896 6681 }
c0f3af97
L		 6682 else
6683 mem = ~0;
252b5132 6684
8c43a48b 6685 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6686 {
6687 if (operand_type_check (i.types[0], imm))
6688 i.vex.register_specifier = NULL;
6689 else
6690 {
6691 /* VEX.vvvv encodes one of the sources when the first
6692 operand is not an immediate. */
1ef99a7b 6693 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6694 i.vex.register_specifier = i.op[0].regs;
6695 else
6696 i.vex.register_specifier = i.op[1].regs;
6697 }
6698
6699 /* Destination is a XMM register encoded in the ModRM.reg
6700 and VEX.R bit. */
6701 i.rm.reg = i.op[2].regs->reg_num;
6702 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6703 i.rex |= REX_R;
6704
6705 /* ModRM.rm and VEX.B encodes the other source. */
6706 if (!i.mem_operands)
6707 {
6708 i.rm.mode = 3;
6709
1ef99a7b 6710 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6711 i.rm.regmem = i.op[1].regs->reg_num;
6712 else
6713 i.rm.regmem = i.op[0].regs->reg_num;
6714
6715 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6716 i.rex |= REX_B;
6717 }
6718 }
2426c15f 6719 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6720 {
6721 i.vex.register_specifier = i.op[2].regs;
6722 if (!i.mem_operands)
6723 {
6724 i.rm.mode = 3;
6725 i.rm.regmem = i.op[1].regs->reg_num;
6726 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6727 i.rex |= REX_B;
6728 }
6729 }
29b0f896
AM		 6730 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6731 (if any) based on i.tm.extension_opcode. Again, we must be
6732 careful to make sure that segment/control/debug/test/MMX
6733 registers are coded into the i.rm.reg field. */
f88c9eb0 6734 else if (i.reg_operands)
29b0f896 6735 {
99018f42 6736 unsigned int op;
7ab9ffdd
L		 6737 unsigned int vex_reg = ~0;
6738
6739 for (op = 0; op < i.operands; op++)
6740 if (i.types[op].bitfield.reg8
6741 || i.types[op].bitfield.reg16
6742 || i.types[op].bitfield.reg32
6743 || i.types[op].bitfield.reg64
6744 || i.types[op].bitfield.regmmx
6745 || i.types[op].bitfield.regxmm
6746 || i.types[op].bitfield.regymm
7e8b059b 6747 || i.types[op].bitfield.regbnd
43234a1e
L		 6748 || i.types[op].bitfield.regzmm
6749 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6750 || i.types[op].bitfield.sreg2
6751 || i.types[op].bitfield.sreg3
6752 || i.types[op].bitfield.control
6753 || i.types[op].bitfield.debug
6754 || i.types[op].bitfield.test)
6755 break;
c0209578 6756
7ab9ffdd
L		 6757 if (vex_3_sources)
6758 op = dest;
2426c15f 6759 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6760 {
6761 /* For instructions with VexNDS, the register-only
6762 source operand is encoded in VEX prefix. */
6763 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6764
7ab9ffdd 6765 if (op > mem)
c0f3af97 6766 {
7ab9ffdd
L		 6767 vex_reg = op++;
6768 gas_assert (op < i.operands);
c0f3af97
L		 6769 }
6770 else
c0f3af97 6771 {
f12dc422
L		 6772 /* Check register-only source operand when two source
6773 operands are swapped. */
6774 if (!i.tm.operand_types[op].bitfield.baseindex
6775 && i.tm.operand_types[op + 1].bitfield.baseindex)
6776 {
6777 vex_reg = op;
6778 op += 2;
6779 gas_assert (mem == (vex_reg + 1)
6780 && op < i.operands);
6781 }
6782 else
6783 {
6784 vex_reg = op + 1;
6785 gas_assert (vex_reg < i.operands);
6786 }
c0f3af97 6787 }
7ab9ffdd 6788 }
2426c15f 6789 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6790 {
f12dc422 6791 /* For instructions with VexNDD, the register destination
7ab9ffdd 6792 is encoded in VEX prefix. */
f12dc422
L		 6793 if (i.mem_operands == 0)
6794 {
6795 /* There is no memory operand. */
6796 gas_assert ((op + 2) == i.operands);
6797 vex_reg = op + 1;
6798 }
6799 else
8d63c93e 6800 {
f12dc422
L		 6801 /* There are only 2 operands. */
6802 gas_assert (op < 2 && i.operands == 2);
6803 vex_reg = 1;
6804 }
7ab9ffdd
L		 6805 }
6806 else
6807 gas_assert (op < i.operands);
99018f42 6808
7ab9ffdd
L		 6809 if (vex_reg != (unsigned int) ~0)
6810 {
f12dc422 6811 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6812
f12dc422
L		 6813 if (type->bitfield.reg32 != 1
6814 && type->bitfield.reg64 != 1
6815 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6816 && !operand_type_equal (type, &regymm)
6817 && !operand_type_equal (type, &regzmm)
6818 && !operand_type_equal (type, &regmask))
7ab9ffdd 6819 abort ();
f88c9eb0 6820
7ab9ffdd
L		 6821 i.vex.register_specifier = i.op[vex_reg].regs;
6822 }
6823
1b9f0c97
L		 6824 /* Don't set OP operand twice. */
6825 if (vex_reg != op)
7ab9ffdd 6826 {
1b9f0c97
L		 6827 /* If there is an extension opcode to put here, the
6828 register number must be put into the regmem field. */
6829 if (i.tm.extension_opcode != None)
6830 {
6831 i.rm.regmem = i.op[op].regs->reg_num;
6832 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6833 i.rex |= REX_B;
43234a1e
L		 6834 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6835 i.vrex |= REX_B;
1b9f0c97
L		 6836 }
6837 else
6838 {
6839 i.rm.reg = i.op[op].regs->reg_num;
6840 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6841 i.rex |= REX_R;
43234a1e
L		 6842 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6843 i.vrex |= REX_R;
1b9f0c97 6844 }
7ab9ffdd 6845 }
252b5132 6846
29b0f896
AM		 6847 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6848 must set it to 3 to indicate this is a register operand
6849 in the regmem field. */
6850 if (!i.mem_operands)
6851 i.rm.mode = 3;
6852 }
252b5132 6853
29b0f896 6854 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6855 if (i.tm.extension_opcode != None)
29b0f896
AM		 6856 i.rm.reg = i.tm.extension_opcode;
6857 }
6858 return default_seg;
6859}
252b5132 6860
29b0f896 6861static void
e3bb37b5 6862output_branch (void)
29b0f896
AM		 6863{
6864 char *p;
f8a5c266 6865 int size;
29b0f896
AM		 6866 int code16;
6867 int prefix;
6868 relax_substateT subtype;
6869 symbolS *sym;
6870 offsetT off;
6871
f8a5c266 6872 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6873 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6874
6875 prefix = 0;
6876 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6877 {
29b0f896
AM		 6878 prefix = 1;
6879 i.prefixes -= 1;
6880 code16 ^= CODE16;
252b5132 6881 }
29b0f896
AM		 6882 /* Pentium4 branch hints. */
6883 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6884 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6885 {
29b0f896
AM		 6886 prefix++;
6887 i.prefixes--;
6888 }
6889 if (i.prefix[REX_PREFIX] != 0)
6890 {
6891 prefix++;
6892 i.prefixes--;
2f66722d
AM		 6893 }
6894
7e8b059b
L		 6895 /* BND prefixed jump. */
6896 if (i.prefix[BND_PREFIX] != 0)
6897 {
6898 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6899 i.prefixes -= 1;
6900 }
6901
29b0f896
AM		 6902 if (i.prefixes != 0 && !intel_syntax)
6903 as_warn (_("skipping prefixes on this instruction"));
6904
6905 /* It's always a symbol; End frag & setup for relax.
6906 Make sure there is enough room in this frag for the largest
6907 instruction we may generate in md_convert_frag. This is 2
6908 bytes for the opcode and room for the prefix and largest
6909 displacement. */
6910 frag_grow (prefix + 2 + 4);
6911 /* Prefix and 1 opcode byte go in fr_fix. */
6912 p = frag_more (prefix + 1);
6913 if (i.prefix[DATA_PREFIX] != 0)
6914 *p++ = DATA_PREFIX_OPCODE;
6915 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6916 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6917 *p++ = i.prefix[SEG_PREFIX];
6918 if (i.prefix[REX_PREFIX] != 0)
6919 *p++ = i.prefix[REX_PREFIX];
6920 *p = i.tm.base_opcode;
6921
6922 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6923 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6924 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6925 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6926 else
f8a5c266 6927 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6928 subtype |= code16;
3e73aa7c 6929
29b0f896
AM		 6930 sym = i.op[0].disps->X_add_symbol;
6931 off = i.op[0].disps->X_add_number;
3e73aa7c 6932
29b0f896
AM		 6933 if (i.op[0].disps->X_op != O_constant
6934 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6935 {
29b0f896
AM		 6936 /* Handle complex expressions. */
6937 sym = make_expr_symbol (i.op[0].disps);
6938 off = 0;
6939 }
3e73aa7c 6940
29b0f896
AM		 6941 /* 1 possible extra opcode + 4 byte displacement go in var part.
6942 Pass reloc in fr_var. */
d258b828 6943 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6944}
3e73aa7c 6945
29b0f896 6946static void
e3bb37b5 6947output_jump (void)
29b0f896
AM		 6948{
6949 char *p;
6950 int size;
3e02c1cc 6951 fixS *fixP;
29b0f896 6952
40fb9820 6953 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6954 {
6955 /* This is a loop or jecxz type instruction. */
6956 size = 1;
6957 if (i.prefix[ADDR_PREFIX] != 0)
6958 {
6959 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6960 i.prefixes -= 1;
6961 }
6962 /* Pentium4 branch hints. */
6963 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6964 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6965 {
6966 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6967 i.prefixes--;
3e73aa7c
JH		 6968 }
6969 }
29b0f896
AM		 6970 else
6971 {
6972 int code16;
3e73aa7c 6973
29b0f896
AM		 6974 code16 = 0;
6975 if (flag_code == CODE_16BIT)
6976 code16 = CODE16;
3e73aa7c 6977
29b0f896
AM		 6978 if (i.prefix[DATA_PREFIX] != 0)
6979 {
6980 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6981 i.prefixes -= 1;
6982 code16 ^= CODE16;
6983 }
252b5132 6984
29b0f896
AM		 6985 size = 4;
6986 if (code16)
6987 size = 2;
6988 }
9fcc94b6 6989
29b0f896
AM		 6990 if (i.prefix[REX_PREFIX] != 0)
6991 {
6992 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6993 i.prefixes -= 1;
6994 }
252b5132 6995
7e8b059b
L		 6996 /* BND prefixed jump. */
6997 if (i.prefix[BND_PREFIX] != 0)
6998 {
6999 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7000 i.prefixes -= 1;
7001 }
7002
29b0f896
AM		 7003 if (i.prefixes != 0 && !intel_syntax)
7004 as_warn (_("skipping prefixes on this instruction"));
e0890092 7005
42164a71
L		 7006 p = frag_more (i.tm.opcode_length + size);
7007 switch (i.tm.opcode_length)
7008 {
7009 case 2:
7010 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7011 /* Fall through. */
42164a71
L		 7012 case 1:
7013 *p++ = i.tm.base_opcode;
7014 break;
7015 default:
7016 abort ();
7017 }
e0890092 7018
3e02c1cc 7019 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7020 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7021
7022 /* All jumps handled here are signed, but don't use a signed limit
7023 check for 32 and 16 bit jumps as we want to allow wrap around at
7024 4G and 64k respectively. */
7025 if (size == 1)
7026 fixP->fx_signed = 1;
29b0f896 7027}
e0890092 7028
29b0f896 7029static void
e3bb37b5 7030output_interseg_jump (void)
29b0f896
AM		 7031{
7032 char *p;
7033 int size;
7034 int prefix;
7035 int code16;
252b5132 7036
29b0f896
AM		 7037 code16 = 0;
7038 if (flag_code == CODE_16BIT)
7039 code16 = CODE16;
a217f122 7040
29b0f896
AM		 7041 prefix = 0;
7042 if (i.prefix[DATA_PREFIX] != 0)
7043 {
7044 prefix = 1;
7045 i.prefixes -= 1;
7046 code16 ^= CODE16;
7047 }
7048 if (i.prefix[REX_PREFIX] != 0)
7049 {
7050 prefix++;
7051 i.prefixes -= 1;
7052 }
252b5132 7053
29b0f896
AM		 7054 size = 4;
7055 if (code16)
7056 size = 2;
252b5132 7057
29b0f896
AM		 7058 if (i.prefixes != 0 && !intel_syntax)
7059 as_warn (_("skipping prefixes on this instruction"));
252b5132 7060
29b0f896
AM		 7061 /* 1 opcode; 2 segment; offset */
7062 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7063
29b0f896
AM		 7064 if (i.prefix[DATA_PREFIX] != 0)
7065 *p++ = DATA_PREFIX_OPCODE;
252b5132 7066
29b0f896
AM		 7067 if (i.prefix[REX_PREFIX] != 0)
7068 *p++ = i.prefix[REX_PREFIX];
252b5132 7069
29b0f896
AM		 7070 *p++ = i.tm.base_opcode;
7071 if (i.op[1].imms->X_op == O_constant)
7072 {
7073 offsetT n = i.op[1].imms->X_add_number;
252b5132 7074
29b0f896
AM		 7075 if (size == 2
7076 && !fits_in_unsigned_word (n)
7077 && !fits_in_signed_word (n))
7078 {
7079 as_bad (_("16-bit jump out of range"));
7080 return;
7081 }
7082 md_number_to_chars (p, n, size);
7083 }
7084 else
7085 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7086 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7087 if (i.op[0].imms->X_op != O_constant)
7088 as_bad (_("can't handle non absolute segment in `%s'"),
7089 i.tm.name);
7090 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7091}
a217f122 7092
29b0f896 7093static void
e3bb37b5 7094output_insn (void)
29b0f896 7095{
2bbd9c25
JJ		 7096 fragS *insn_start_frag;
7097 offsetT insn_start_off;
7098
29b0f896
AM		 7099 /* Tie dwarf2 debug info to the address at the start of the insn.
7100 We can't do this after the insn has been output as the current
7101 frag may have been closed off. eg. by frag_var. */
7102 dwarf2_emit_insn (0);
7103
2bbd9c25
JJ		 7104 insn_start_frag = frag_now;
7105 insn_start_off = frag_now_fix ();
7106
29b0f896 7107 /* Output jumps. */
40fb9820 7108 if (i.tm.opcode_modifier.jump)
29b0f896 7109 output_branch ();
40fb9820
L		 7110 else if (i.tm.opcode_modifier.jumpbyte
7111 || i.tm.opcode_modifier.jumpdword)
29b0f896 7112 output_jump ();
40fb9820 7113 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7114 output_interseg_jump ();
7115 else
7116 {
7117 /* Output normal instructions here. */
7118 char *p;
7119 unsigned char *q;
47465058 7120 unsigned int j;
331d2d0d 7121 unsigned int prefix;
4dffcebc 7122
e4e00185
AS		 7123 if (avoid_fence
7124 && i.tm.base_opcode == 0xfae
7125 && i.operands == 1
7126 && i.imm_operands == 1
7127 && (i.op[0].imms->X_add_number == 0xe8
7128 || i.op[0].imms->X_add_number == 0xf0
7129 || i.op[0].imms->X_add_number == 0xf8))
7130 {
7131 /* Encode lfence, mfence, and sfence as
7132 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7133 offsetT val = 0x240483f0ULL;
7134 p = frag_more (5);
7135 md_number_to_chars (p, val, 5);
7136 return;
7137 }
7138
d022bddd
IT		 7139 /* Some processors fail on LOCK prefix. This options makes
7140 assembler ignore LOCK prefix and serves as a workaround. */
7141 if (omit_lock_prefix)
7142 {
7143 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7144 return;
7145 i.prefix[LOCK_PREFIX] = 0;
7146 }
7147
43234a1e
L		 7148 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7149 don't need the explicit prefix. */
7150 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7151 {
c0f3af97 7152 switch (i.tm.opcode_length)
bc4bd9ab 7153 {
c0f3af97
L		 7154 case 3:
7155 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7156 {
c0f3af97
L		 7157 prefix = (i.tm.base_opcode >> 24) & 0xff;
7158 goto check_prefix;
7159 }
7160 break;
7161 case 2:
7162 if ((i.tm.base_opcode & 0xff0000) != 0)
7163 {
7164 prefix = (i.tm.base_opcode >> 16) & 0xff;
7165 if (i.tm.cpu_flags.bitfield.cpupadlock)
7166 {
4dffcebc 7167check_prefix:
c0f3af97 7168 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7169 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7170 != REPE_PREFIX_OPCODE))
7171 add_prefix (prefix);
7172 }
7173 else
4dffcebc
L		 7174 add_prefix (prefix);
7175 }
c0f3af97
L		 7176 break;
7177 case 1:
7178 break;
7179 default:
7180 abort ();
bc4bd9ab 7181 }
c0f3af97 7182
6d19a37a 7183#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7184 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7185 R_X86_64_GOTTPOFF relocation so that linker can safely
7186 perform IE->LE optimization. */
7187 if (x86_elf_abi == X86_64_X32_ABI
7188 && i.operands == 2
7189 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7190 && i.prefix[REX_PREFIX] == 0)
7191 add_prefix (REX_OPCODE);
6d19a37a 7192#endif
cf61b747 7193
c0f3af97
L		 7194 /* The prefix bytes. */
7195 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7196 if (*q)
7197 FRAG_APPEND_1_CHAR (*q);
0f10071e 7198 }
ae5c1c7b 7199 else
c0f3af97
L		 7200 {
7201 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7202 if (*q)
7203 switch (j)
7204 {
7205 case REX_PREFIX:
7206 /* REX byte is encoded in VEX prefix. */
7207 break;
7208 case SEG_PREFIX:
7209 case ADDR_PREFIX:
7210 FRAG_APPEND_1_CHAR (*q);
7211 break;
7212 default:
7213 /* There should be no other prefixes for instructions
7214 with VEX prefix. */
7215 abort ();
7216 }
7217
43234a1e
L		 7218 /* For EVEX instructions i.vrex should become 0 after
7219 build_evex_prefix. For VEX instructions upper 16 registers
7220 aren't available, so VREX should be 0. */
7221 if (i.vrex)
7222 abort ();
c0f3af97
L		 7223 /* Now the VEX prefix. */
7224 p = frag_more (i.vex.length);
7225 for (j = 0; j < i.vex.length; j++)
7226 p[j] = i.vex.bytes[j];
7227 }
252b5132 7228
29b0f896 7229 /* Now the opcode; be careful about word order here! */
4dffcebc 7230 if (i.tm.opcode_length == 1)
29b0f896
AM		 7231 {
7232 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7233 }
7234 else
7235 {
4dffcebc 7236 switch (i.tm.opcode_length)
331d2d0d 7237 {
43234a1e
L		 7238 case 4:
7239 p = frag_more (4);
7240 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7241 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7242 break;
4dffcebc 7243 case 3:
331d2d0d
L		 7244 p = frag_more (3);
7245 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7246 break;
7247 case 2:
7248 p = frag_more (2);
7249 break;
7250 default:
7251 abort ();
7252 break;
331d2d0d 7253 }
0f10071e 7254
29b0f896
AM		 7255 /* Put out high byte first: can't use md_number_to_chars! */
7256 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7257 *p = i.tm.base_opcode & 0xff;
7258 }
3e73aa7c 7259
29b0f896 7260 /* Now the modrm byte and sib byte (if present). */
40fb9820 7261 if (i.tm.opcode_modifier.modrm)
29b0f896 7262 {
4a3523fa
L		 7263 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7264 | i.rm.reg << 3
7265 | i.rm.mode << 6));
29b0f896
AM		 7266 /* If i.rm.regmem == ESP (4)
7267 && i.rm.mode != (Register mode)
7268 && not 16 bit
7269 ==> need second modrm byte. */
7270 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7271 && i.rm.mode != 3
40fb9820 7272 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7273 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7274 | i.sib.index << 3
7275 | i.sib.scale << 6));
29b0f896 7276 }
3e73aa7c 7277
29b0f896 7278 if (i.disp_operands)
2bbd9c25 7279 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7280
29b0f896 7281 if (i.imm_operands)
2bbd9c25 7282 output_imm (insn_start_frag, insn_start_off);
29b0f896 7283 }
252b5132 7284
29b0f896
AM		 7285#ifdef DEBUG386
7286 if (flag_debug)
7287 {
7b81dfbb 7288 pi ("" /*line*/, &i);
29b0f896
AM		 7289 }
7290#endif /* DEBUG386 */
7291}
252b5132 7292
e205caa7
L		 7293/* Return the size of the displacement operand N. */
7294
7295static int
7296disp_size (unsigned int n)
7297{
7298 int size = 4;
43234a1e
L		 7299
7300 /* Vec_Disp8 has to be 8bit. */
7301 if (i.types[n].bitfield.vec_disp8)
7302 size = 1;
7303 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7304 size = 8;
7305 else if (i.types[n].bitfield.disp8)
7306 size = 1;
7307 else if (i.types[n].bitfield.disp16)
7308 size = 2;
e205caa7
L		 7309 return size;
7310}
7311
7312/* Return the size of the immediate operand N. */
7313
7314static int
7315imm_size (unsigned int n)
7316{
7317 int size = 4;
40fb9820
L		 7318 if (i.types[n].bitfield.imm64)
7319 size = 8;
7320 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7321 size = 1;
7322 else if (i.types[n].bitfield.imm16)
7323 size = 2;
e205caa7
L		 7324 return size;
7325}
7326
29b0f896 7327static void
64e74474 7328output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7329{
7330 char *p;
7331 unsigned int n;
252b5132 7332
29b0f896
AM		 7333 for (n = 0; n < i.operands; n++)
7334 {
43234a1e
L		 7335 if (i.types[n].bitfield.vec_disp8
7336 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7337 {
7338 if (i.op[n].disps->X_op == O_constant)
7339 {
e205caa7 7340 int size = disp_size (n);
43234a1e 7341 offsetT val = i.op[n].disps->X_add_number;
252b5132 7342
43234a1e
L		 7343 if (i.types[n].bitfield.vec_disp8)
7344 val >>= i.memshift;
7345 val = offset_in_range (val, size);
29b0f896
AM		 7346 p = frag_more (size);
7347 md_number_to_chars (p, val, size);
7348 }
7349 else
7350 {
f86103b7 7351 enum bfd_reloc_code_real reloc_type;
e205caa7 7352 int size = disp_size (n);
40fb9820 7353 int sign = i.types[n].bitfield.disp32s;
29b0f896 7354 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7355 fixS *fixP;
29b0f896 7356
e205caa7 7357 /* We can't have 8 bit displacement here. */
9c2799c2 7358 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7359
29b0f896
AM		 7360 /* The PC relative address is computed relative
7361 to the instruction boundary, so in case immediate
7362 fields follows, we need to adjust the value. */
7363 if (pcrel && i.imm_operands)
7364 {
29b0f896 7365 unsigned int n1;
e205caa7 7366 int sz = 0;
252b5132 7367
29b0f896 7368 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7369 if (operand_type_check (i.types[n1], imm))
252b5132 7370 {
e205caa7
L		 7371 /* Only one immediate is allowed for PC
7372 relative address. */
9c2799c2 7373 gas_assert (sz == 0);
e205caa7
L		 7374 sz = imm_size (n1);
7375 i.op[n].disps->X_add_number -= sz;
252b5132 7376 }
29b0f896 7377 /* We should find the immediate. */
9c2799c2 7378 gas_assert (sz != 0);
29b0f896 7379 }
520dc8e8 7380
29b0f896 7381 p = frag_more (size);
d258b828 7382 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7383 if (GOT_symbol
2bbd9c25 7384 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7385 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7386 || reloc_type == BFD_RELOC_X86_64_32S
7387 || (reloc_type == BFD_RELOC_64
7388 && object_64bit))
d6ab8113
JB		 7389 && (i.op[n].disps->X_op == O_symbol
7390 || (i.op[n].disps->X_op == O_add
7391 && ((symbol_get_value_expression
7392 (i.op[n].disps->X_op_symbol)->X_op)
7393 == O_subtract))))
7394 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7395 {
7396 offsetT add;
7397
7398 if (insn_start_frag == frag_now)
7399 add = (p - frag_now->fr_literal) - insn_start_off;
7400 else
7401 {
7402 fragS *fr;
7403
7404 add = insn_start_frag->fr_fix - insn_start_off;
7405 for (fr = insn_start_frag->fr_next;
7406 fr && fr != frag_now; fr = fr->fr_next)
7407 add += fr->fr_fix;
7408 add += p - frag_now->fr_literal;
7409 }
7410
4fa24527 7411 if (!object_64bit)
7b81dfbb
AJ		 7412 {
7413 reloc_type = BFD_RELOC_386_GOTPC;
7414 i.op[n].imms->X_add_number += add;
7415 }
7416 else if (reloc_type == BFD_RELOC_64)
7417 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7418 else
7b81dfbb
AJ		 7419 /* Don't do the adjustment for x86-64, as there
7420 the pcrel addressing is relative to the _next_
7421 insn, and that is taken care of in other code. */
d6ab8113 7422 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7423 }
02a86693
L		 7424 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7425 size, i.op[n].disps, pcrel,
7426 reloc_type);
7427 /* Check for "call/jmp *mem", "mov mem, %reg",
7428 "test %reg, mem" and "binop mem, %reg" where binop
7429 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7430 instructions. Always generate R_386_GOT32X for
7431 "sym*GOT" operand in 32-bit mode. */
7432 if ((generate_relax_relocations
7433 || (!object_64bit
7434 && i.rm.mode == 0
7435 && i.rm.regmem == 5))
7436 && (i.rm.mode == 2
7437 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7438 && ((i.operands == 1
7439 && i.tm.base_opcode == 0xff
7440 && (i.rm.reg == 2 || i.rm.reg == 4))
7441 || (i.operands == 2
7442 && (i.tm.base_opcode == 0x8b
7443 || i.tm.base_opcode == 0x85
7444 || (i.tm.base_opcode & 0xc7) == 0x03))))
7445 {
7446 if (object_64bit)
7447 {
7448 fixP->fx_tcbit = i.rex != 0;
7449 if (i.base_reg
7450 && (i.base_reg->reg_num == RegRip
7451 || i.base_reg->reg_num == RegEip))
7452 fixP->fx_tcbit2 = 1;
7453 }
7454 else
7455 fixP->fx_tcbit2 = 1;
7456 }
29b0f896
AM		 7457 }
7458 }
7459 }
7460}
252b5132 7461
29b0f896 7462static void
64e74474 7463output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7464{
7465 char *p;
7466 unsigned int n;
252b5132 7467
29b0f896
AM		 7468 for (n = 0; n < i.operands; n++)
7469 {
43234a1e
L		 7470 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7471 if (i.rounding && (int) n == i.rounding->operand)
7472 continue;
7473
40fb9820 7474 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7475 {
7476 if (i.op[n].imms->X_op == O_constant)
7477 {
e205caa7 7478 int size = imm_size (n);
29b0f896 7479 offsetT val;
b4cac588 7480
29b0f896
AM		 7481 val = offset_in_range (i.op[n].imms->X_add_number,
7482 size);
7483 p = frag_more (size);
7484 md_number_to_chars (p, val, size);
7485 }
7486 else
7487 {
7488 /* Not absolute_section.
7489 Need a 32-bit fixup (don't support 8bit
7490 non-absolute imms). Try to support other
7491 sizes ... */
f86103b7 7492 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7493 int size = imm_size (n);
7494 int sign;
29b0f896 7495
40fb9820 7496 if (i.types[n].bitfield.imm32s
a7d61044 7497 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7498 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7499 sign = 1;
e205caa7
L		 7500 else
7501 sign = 0;
520dc8e8 7502
29b0f896 7503 p = frag_more (size);
d258b828 7504 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7505
2bbd9c25
JJ		 7506 /* This is tough to explain. We end up with this one if we
7507 * have operands that look like
7508 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7509 * obtain the absolute address of the GOT, and it is strongly
7510 * preferable from a performance point of view to avoid using
7511 * a runtime relocation for this. The actual sequence of
7512 * instructions often look something like:
7513 *
7514 * call .L66
7515 * .L66:
7516 * popl %ebx
7517 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7518 *
7519 * The call and pop essentially return the absolute address
7520 * of the label .L66 and store it in %ebx. The linker itself
7521 * will ultimately change the first operand of the addl so
7522 * that %ebx points to the GOT, but to keep things simple, the
7523 * .o file must have this operand set so that it generates not
7524 * the absolute address of .L66, but the absolute address of
7525 * itself. This allows the linker itself simply treat a GOTPC
7526 * relocation as asking for a pcrel offset to the GOT to be
7527 * added in, and the addend of the relocation is stored in the
7528 * operand field for the instruction itself.
7529 *
7530 * Our job here is to fix the operand so that it would add
7531 * the correct offset so that %ebx would point to itself. The
7532 * thing that is tricky is that .-.L66 will point to the
7533 * beginning of the instruction, so we need to further modify
7534 * the operand so that it will point to itself. There are
7535 * other cases where you have something like:
7536 *
7537 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7538 *
7539 * and here no correction would be required. Internally in
7540 * the assembler we treat operands of this form as not being
7541 * pcrel since the '.' is explicitly mentioned, and I wonder
7542 * whether it would simplify matters to do it this way. Who
7543 * knows. In earlier versions of the PIC patches, the
7544 * pcrel_adjust field was used to store the correction, but
7545 * since the expression is not pcrel, I felt it would be
7546 * confusing to do it this way. */
7547
d6ab8113 7548 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7549 || reloc_type == BFD_RELOC_X86_64_32S
7550 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7551 && GOT_symbol
7552 && GOT_symbol == i.op[n].imms->X_add_symbol
7553 && (i.op[n].imms->X_op == O_symbol
7554 || (i.op[n].imms->X_op == O_add
7555 && ((symbol_get_value_expression
7556 (i.op[n].imms->X_op_symbol)->X_op)
7557 == O_subtract))))
7558 {
2bbd9c25
JJ		 7559 offsetT add;
7560
7561 if (insn_start_frag == frag_now)
7562 add = (p - frag_now->fr_literal) - insn_start_off;
7563 else
7564 {
7565 fragS *fr;
7566
7567 add = insn_start_frag->fr_fix - insn_start_off;
7568 for (fr = insn_start_frag->fr_next;
7569 fr && fr != frag_now; fr = fr->fr_next)
7570 add += fr->fr_fix;
7571 add += p - frag_now->fr_literal;
7572 }
7573
4fa24527 7574 if (!object_64bit)
d6ab8113 7575 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7576 else if (size == 4)
d6ab8113 7577 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7578 else if (size == 8)
7579 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7580 i.op[n].imms->X_add_number += add;
29b0f896 7581 }
29b0f896
AM		 7582 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7583 i.op[n].imms, 0, reloc_type);
7584 }
7585 }
7586 }
252b5132
RH		 7587}
7588\f
d182319b
JB		 7589/* x86_cons_fix_new is called via the expression parsing code when a
7590 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7591static int cons_sign = -1;
7592
7593void
e3bb37b5 7594x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7595 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7596{
d258b828 7597 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7598
7599#ifdef TE_PE
7600 if (exp->X_op == O_secrel)
7601 {
7602 exp->X_op = O_symbol;
7603 r = BFD_RELOC_32_SECREL;
7604 }
7605#endif
7606
7607 fix_new_exp (frag, off, len, exp, 0, r);
7608}
7609
357d1bd8
L		 7610/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7611 purpose of the `.dc.a' internal pseudo-op. */
7612
7613int
7614x86_address_bytes (void)
7615{
7616 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7617 return 4;
7618 return stdoutput->arch_info->bits_per_address / 8;
7619}
7620
d382c579
TG		 7621#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7622 || defined (LEX_AT)
d258b828 7623# define lex_got(reloc, adjust, types) NULL
718ddfc0 7624#else
f3c180ae
AM		 7625/* Parse operands of the form
7626 <symbol>@GOTOFF+<nnn>
7627 and similar .plt or .got references.
7628
7629 If we find one, set up the correct relocation in RELOC and copy the
7630 input string, minus the `@GOTOFF' into a malloc'd buffer for
7631 parsing by the calling routine. Return this buffer, and if ADJUST
7632 is non-null set it to the length of the string we removed from the
7633 input line. Otherwise return NULL. */
7634static char *
91d6fa6a 7635lex_got (enum bfd_reloc_code_real *rel,
64e74474 7636 int *adjust,
d258b828 7637 i386_operand_type *types)
f3c180ae 7638{
7b81dfbb
AJ		 7639 /* Some of the relocations depend on the size of what field is to
7640 be relocated. But in our callers i386_immediate and i386_displacement
7641 we don't yet know the operand size (this will be set by insn
7642 matching). Hence we record the word32 relocation here,
7643 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7644 static const struct {
7645 const char *str;
cff8d58a 7646 int len;
4fa24527 7647 const enum bfd_reloc_code_real rel[2];
40fb9820 7648 const i386_operand_type types64;
f3c180ae 7649 } gotrel[] = {
8ce3d284 7650#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7651 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7652 BFD_RELOC_SIZE32 },
7653 OPERAND_TYPE_IMM32_64 },
8ce3d284 7654#endif
cff8d58a
L		 7655 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7656 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7657 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7658 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7659 BFD_RELOC_X86_64_PLT32 },
40fb9820 7660 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7661 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7662 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7663 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7664 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7665 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7666 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7667 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7668 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7669 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7670 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7671 BFD_RELOC_X86_64_TLSGD },
40fb9820 7672 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7673 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7674 _dummy_first_bfd_reloc_code_real },
40fb9820 7675 OPERAND_TYPE_NONE },
cff8d58a
L		 7676 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7677 BFD_RELOC_X86_64_TLSLD },
40fb9820 7678 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7679 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7680 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7681 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7682 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7683 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7684 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7685 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7686 _dummy_first_bfd_reloc_code_real },
40fb9820 7687 OPERAND_TYPE_NONE },
cff8d58a
L		 7688 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7689 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7690 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7691 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7692 _dummy_first_bfd_reloc_code_real },
40fb9820 7693 OPERAND_TYPE_NONE },
cff8d58a
L		 7694 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7695 _dummy_first_bfd_reloc_code_real },
40fb9820 7696 OPERAND_TYPE_NONE },
cff8d58a
L		 7697 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7698 BFD_RELOC_X86_64_GOT32 },
40fb9820 7699 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7700 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7701 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7702 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7703 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7704 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7705 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7706 };
7707 char *cp;
7708 unsigned int j;
7709
d382c579 7710#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7711 if (!IS_ELF)
7712 return NULL;
d382c579 7713#endif
718ddfc0 7714
f3c180ae 7715 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7716 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7717 return NULL;
7718
47465058 7719 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7720 {
cff8d58a 7721 int len = gotrel[j].len;
28f81592 7722 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7723 {
4fa24527 7724 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7725 {
28f81592
AM		 7726 int first, second;
7727 char *tmpbuf, *past_reloc;
f3c180ae 7728
91d6fa6a 7729 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7730
3956db08
JB		 7731 if (types)
7732 {
7733 if (flag_code != CODE_64BIT)
40fb9820
L		 7734 {
7735 types->bitfield.imm32 = 1;
7736 types->bitfield.disp32 = 1;
7737 }
3956db08
JB		 7738 else
7739 *types = gotrel[j].types64;
7740 }
7741
8fd4256d 7742 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7743 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7744
28f81592 7745 /* The length of the first part of our input line. */
f3c180ae 7746 first = cp - input_line_pointer;
28f81592
AM		 7747
7748 /* The second part goes from after the reloc token until
67c11a9b 7749 (and including) an end_of_line char or comma. */
28f81592 7750 past_reloc = cp + 1 + len;
67c11a9b
AM		 7751 cp = past_reloc;
7752 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7753 ++cp;
7754 second = cp + 1 - past_reloc;
28f81592
AM		 7755
7756 /* Allocate and copy string. The trailing NUL shouldn't
7757 be necessary, but be safe. */
add39d23 7758 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7759 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7760 if (second != 0 && *past_reloc != ' ')
7761 /* Replace the relocation token with ' ', so that
7762 errors like foo@GOTOFF1 will be detected. */
7763 tmpbuf[first++] = ' ';
af89796a
L		 7764 else
7765 /* Increment length by 1 if the relocation token is
7766 removed. */
7767 len++;
7768 if (adjust)
7769 *adjust = len;
0787a12d
AM		 7770 memcpy (tmpbuf + first, past_reloc, second);
7771 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7772 return tmpbuf;
7773 }
7774
4fa24527
JB		 7775 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7776 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7777 return NULL;
7778 }
7779 }
7780
7781 /* Might be a symbol version string. Don't as_bad here. */
7782 return NULL;
7783}
4e4f7c87 7784#endif
f3c180ae 7785
a988325c
NC		 7786#ifdef TE_PE
7787#ifdef lex_got
7788#undef lex_got
7789#endif
7790/* Parse operands of the form
7791 <symbol>@SECREL32+<nnn>
7792
7793 If we find one, set up the correct relocation in RELOC and copy the
7794 input string, minus the `@SECREL32' into a malloc'd buffer for
7795 parsing by the calling routine. Return this buffer, and if ADJUST
7796 is non-null set it to the length of the string we removed from the
34bca508
L		 7797 input line. Otherwise return NULL.
7798
a988325c
NC		 7799 This function is copied from the ELF version above adjusted for PE targets. */
7800
7801static char *
7802lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7803 int *adjust ATTRIBUTE_UNUSED,
d258b828 7804 i386_operand_type *types)
a988325c
NC		 7805{
7806 static const struct
7807 {
7808 const char *str;
7809 int len;
7810 const enum bfd_reloc_code_real rel[2];
7811 const i386_operand_type types64;
7812 }
7813 gotrel[] =
7814 {
7815 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7816 BFD_RELOC_32_SECREL },
7817 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7818 };
7819
7820 char *cp;
7821 unsigned j;
7822
7823 for (cp = input_line_pointer; *cp != '@'; cp++)
7824 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7825 return NULL;
7826
7827 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7828 {
7829 int len = gotrel[j].len;
7830
7831 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7832 {
7833 if (gotrel[j].rel[object_64bit] != 0)
7834 {
7835 int first, second;
7836 char *tmpbuf, *past_reloc;
7837
7838 *rel = gotrel[j].rel[object_64bit];
7839 if (adjust)
7840 *adjust = len;
7841
7842 if (types)
7843 {
7844 if (flag_code != CODE_64BIT)
7845 {
7846 types->bitfield.imm32 = 1;
7847 types->bitfield.disp32 = 1;
7848 }
7849 else
7850 *types = gotrel[j].types64;
7851 }
7852
7853 /* The length of the first part of our input line. */
7854 first = cp - input_line_pointer;
7855
7856 /* The second part goes from after the reloc token until
7857 (and including) an end_of_line char or comma. */
7858 past_reloc = cp + 1 + len;
7859 cp = past_reloc;
7860 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7861 ++cp;
7862 second = cp + 1 - past_reloc;
7863
7864 /* Allocate and copy string. The trailing NUL shouldn't
7865 be necessary, but be safe. */
add39d23 7866 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7867 memcpy (tmpbuf, input_line_pointer, first);
7868 if (second != 0 && *past_reloc != ' ')
7869 /* Replace the relocation token with ' ', so that
7870 errors like foo@SECLREL321 will be detected. */
7871 tmpbuf[first++] = ' ';
7872 memcpy (tmpbuf + first, past_reloc, second);
7873 tmpbuf[first + second] = '\0';
7874 return tmpbuf;
7875 }
7876
7877 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7878 gotrel[j].str, 1 << (5 + object_64bit));
7879 return NULL;
7880 }
7881 }
7882
7883 /* Might be a symbol version string. Don't as_bad here. */
7884 return NULL;
7885}
7886
7887#endif /* TE_PE */
7888
62ebcb5c 7889bfd_reloc_code_real_type
e3bb37b5 7890x86_cons (expressionS *exp, int size)
f3c180ae 7891{
62ebcb5c
AM		 7892 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7893
ee86248c
JB		 7894 intel_syntax = -intel_syntax;
7895
3c7b9c2c 7896 exp->X_md = 0;
4fa24527 7897 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7898 {
7899 /* Handle @GOTOFF and the like in an expression. */
7900 char *save;
7901 char *gotfree_input_line;
4a57f2cf 7902 int adjust = 0;
f3c180ae
AM		 7903
7904 save = input_line_pointer;
d258b828 7905 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7906 if (gotfree_input_line)
7907 input_line_pointer = gotfree_input_line;
7908
7909 expression (exp);
7910
7911 if (gotfree_input_line)
7912 {
7913 /* expression () has merrily parsed up to the end of line,
7914 or a comma - in the wrong buffer. Transfer how far
7915 input_line_pointer has moved to the right buffer. */
7916 input_line_pointer = (save
7917 + (input_line_pointer - gotfree_input_line)
7918 + adjust);
7919 free (gotfree_input_line);
3992d3b7
AM		 7920 if (exp->X_op == O_constant
7921 || exp->X_op == O_absent
7922 || exp->X_op == O_illegal
0398aac5 7923 || exp->X_op == O_register
3992d3b7
AM		 7924 || exp->X_op == O_big)
7925 {
7926 char c = *input_line_pointer;
7927 *input_line_pointer = 0;
7928 as_bad (_("missing or invalid expression `%s'"), save);
7929 *input_line_pointer = c;
7930 }
f3c180ae
AM		 7931 }
7932 }
7933 else
7934 expression (exp);
ee86248c
JB		 7935
7936 intel_syntax = -intel_syntax;
7937
7938 if (intel_syntax)
7939 i386_intel_simplify (exp);
62ebcb5c
AM		 7940
7941 return got_reloc;
f3c180ae 7942}
f3c180ae 7943
9f32dd5b
L		 7944static void
7945signed_cons (int size)
6482c264 7946{
d182319b
JB		 7947 if (flag_code == CODE_64BIT)
7948 cons_sign = 1;
7949 cons (size);
7950 cons_sign = -1;
6482c264
NC		 7951}
7952
d182319b 7953#ifdef TE_PE
6482c264 7954static void
7016a5d5 7955pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7956{
7957 expressionS exp;
7958
7959 do
7960 {
7961 expression (&exp);
7962 if (exp.X_op == O_symbol)
7963 exp.X_op = O_secrel;
7964
7965 emit_expr (&exp, 4);
7966 }
7967 while (*input_line_pointer++ == ',');
7968
7969 input_line_pointer--;
7970 demand_empty_rest_of_line ();
7971}
6482c264
NC		 7972#endif
7973
43234a1e
L		 7974/* Handle Vector operations. */
7975
7976static char *
7977check_VecOperations (char *op_string, char *op_end)
7978{
7979 const reg_entry *mask;
7980 const char *saved;
7981 char *end_op;
7982
7983 while (*op_string
7984 && (op_end == NULL || op_string < op_end))
7985 {
7986 saved = op_string;
7987 if (*op_string == '{')
7988 {
7989 op_string++;
7990
7991 /* Check broadcasts. */
7992 if (strncmp (op_string, "1to", 3) == 0)
7993 {
7994 int bcst_type;
7995
7996 if (i.broadcast)
7997 goto duplicated_vec_op;
7998
7999 op_string += 3;
8000 if (*op_string == '8')
8001 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8002 else if (*op_string == '4')
8003 bcst_type = BROADCAST_1TO4;
8004 else if (*op_string == '2')
8005 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8006 else if (*op_string == '1'
8007 && *(op_string+1) == '6')
8008 {
8009 bcst_type = BROADCAST_1TO16;
8010 op_string++;
8011 }
8012 else
8013 {
8014 as_bad (_("Unsupported broadcast: `%s'"), saved);
8015 return NULL;
8016 }
8017 op_string++;
8018
8019 broadcast_op.type = bcst_type;
8020 broadcast_op.operand = this_operand;
8021 i.broadcast = &broadcast_op;
8022 }
8023 /* Check masking operation. */
8024 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8025 {
8026 /* k0 can't be used for write mask. */
8027 if (mask->reg_num == 0)
8028 {
8029 as_bad (_("`%s' can't be used for write mask"),
8030 op_string);
8031 return NULL;
8032 }
8033
8034 if (!i.mask)
8035 {
8036 mask_op.mask = mask;
8037 mask_op.zeroing = 0;
8038 mask_op.operand = this_operand;
8039 i.mask = &mask_op;
8040 }
8041 else
8042 {
8043 if (i.mask->mask)
8044 goto duplicated_vec_op;
8045
8046 i.mask->mask = mask;
8047
8048 /* Only "{z}" is allowed here. No need to check
8049 zeroing mask explicitly. */
8050 if (i.mask->operand != this_operand)
8051 {
8052 as_bad (_("invalid write mask `%s'"), saved);
8053 return NULL;
8054 }
8055 }
8056
8057 op_string = end_op;
8058 }
8059 /* Check zeroing-flag for masking operation. */
8060 else if (*op_string == 'z')
8061 {
8062 if (!i.mask)
8063 {
8064 mask_op.mask = NULL;
8065 mask_op.zeroing = 1;
8066 mask_op.operand = this_operand;
8067 i.mask = &mask_op;
8068 }
8069 else
8070 {
8071 if (i.mask->zeroing)
8072 {
8073 duplicated_vec_op:
8074 as_bad (_("duplicated `%s'"), saved);
8075 return NULL;
8076 }
8077
8078 i.mask->zeroing = 1;
8079
8080 /* Only "{%k}" is allowed here. No need to check mask
8081 register explicitly. */
8082 if (i.mask->operand != this_operand)
8083 {
8084 as_bad (_("invalid zeroing-masking `%s'"),
8085 saved);
8086 return NULL;
8087 }
8088 }
8089
8090 op_string++;
8091 }
8092 else
8093 goto unknown_vec_op;
8094
8095 if (*op_string != '}')
8096 {
8097 as_bad (_("missing `}' in `%s'"), saved);
8098 return NULL;
8099 }
8100 op_string++;
8101 continue;
8102 }
8103 unknown_vec_op:
8104 /* We don't know this one. */
8105 as_bad (_("unknown vector operation: `%s'"), saved);
8106 return NULL;
8107 }
8108
8109 return op_string;
8110}
8111
252b5132 8112static int
70e41ade 8113i386_immediate (char *imm_start)
252b5132
RH		 8114{
8115 char *save_input_line_pointer;
f3c180ae 8116 char *gotfree_input_line;
252b5132 8117 segT exp_seg = 0;
47926f60 8118 expressionS *exp;
40fb9820
L		 8119 i386_operand_type types;
8120
0dfbf9d7 8121 operand_type_set (&types, ~0);
252b5132
RH		 8122
8123 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8124 {
31b2323c
L		 8125 as_bad (_("at most %d immediate operands are allowed"),
8126 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8127 return 0;
8128 }
8129
8130 exp = &im_expressions[i.imm_operands++];
520dc8e8 8131 i.op[this_operand].imms = exp;
252b5132
RH		 8132
8133 if (is_space_char (*imm_start))
8134 ++imm_start;
8135
8136 save_input_line_pointer = input_line_pointer;
8137 input_line_pointer = imm_start;
8138
d258b828 8139 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8140 if (gotfree_input_line)
8141 input_line_pointer = gotfree_input_line;
252b5132
RH		 8142
8143 exp_seg = expression (exp);
8144
83183c0c 8145 SKIP_WHITESPACE ();
43234a1e
L		 8146
8147 /* Handle vector operations. */
8148 if (*input_line_pointer == '{')
8149 {
8150 input_line_pointer = check_VecOperations (input_line_pointer,
8151 NULL);
8152 if (input_line_pointer == NULL)
8153 return 0;
8154 }
8155
252b5132 8156 if (*input_line_pointer)
f3c180ae 8157 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8158
8159 input_line_pointer = save_input_line_pointer;
f3c180ae 8160 if (gotfree_input_line)
ee86248c
JB		 8161 {
8162 free (gotfree_input_line);
8163
8164 if (exp->X_op == O_constant || exp->X_op == O_register)
8165 exp->X_op = O_illegal;
8166 }
8167
8168 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8169}
252b5132 8170
ee86248c
JB		 8171static int
8172i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8173 i386_operand_type types, const char *imm_start)
8174{
8175 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8176 {
313c53d1
L		 8177 if (imm_start)
8178 as_bad (_("missing or invalid immediate expression `%s'"),
8179 imm_start);
3992d3b7 8180 return 0;
252b5132 8181 }
3e73aa7c 8182 else if (exp->X_op == O_constant)
252b5132 8183 {
47926f60 8184 /* Size it properly later. */
40fb9820 8185 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8186 /* If not 64bit, sign extend val. */
8187 if (flag_code != CODE_64BIT
4eed87de
AM		 8188 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8189 exp->X_add_number
8190 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8191 }
4c63da97 8192#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8193 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8194 && exp_seg != absolute_section
47926f60 8195 && exp_seg != text_section
24eab124
AM		 8196 && exp_seg != data_section
8197 && exp_seg != bss_section
8198 && exp_seg != undefined_section
f86103b7 8199 && !bfd_is_com_section (exp_seg))
252b5132 8200 {
d0b47220 8201 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8202 return 0;
8203 }
8204#endif
a841bdf5 8205 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8206 {
313c53d1
L		 8207 if (imm_start)
8208 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8209 return 0;
8210 }
252b5132
RH		 8211 else
8212 {
8213 /* This is an address. The size of the address will be
24eab124 8214 determined later, depending on destination register,
3e73aa7c 8215 suffix, or the default for the section. */
40fb9820
L		 8216 i.types[this_operand].bitfield.imm8 = 1;
8217 i.types[this_operand].bitfield.imm16 = 1;
8218 i.types[this_operand].bitfield.imm32 = 1;
8219 i.types[this_operand].bitfield.imm32s = 1;
8220 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8221 i.types[this_operand] = operand_type_and (i.types[this_operand],
8222 types);
252b5132
RH		 8223 }
8224
8225 return 1;
8226}
8227
551c1ca1 8228static char *
e3bb37b5 8229i386_scale (char *scale)
252b5132 8230{
551c1ca1
AM		 8231 offsetT val;
8232 char *save = input_line_pointer;
252b5132 8233
551c1ca1
AM		 8234 input_line_pointer = scale;
8235 val = get_absolute_expression ();
8236
8237 switch (val)
252b5132 8238 {
551c1ca1 8239 case 1:
252b5132
RH		 8240 i.log2_scale_factor = 0;
8241 break;
551c1ca1 8242 case 2:
252b5132
RH		 8243 i.log2_scale_factor = 1;
8244 break;
551c1ca1 8245 case 4:
252b5132
RH		 8246 i.log2_scale_factor = 2;
8247 break;
551c1ca1 8248 case 8:
252b5132
RH		 8249 i.log2_scale_factor = 3;
8250 break;
8251 default:
a724f0f4
JB		 8252 {
8253 char sep = *input_line_pointer;
8254
8255 *input_line_pointer = '\0';
8256 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8257 scale);
8258 *input_line_pointer = sep;
8259 input_line_pointer = save;
8260 return NULL;
8261 }
252b5132 8262 }
29b0f896 8263 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8264 {
8265 as_warn (_("scale factor of %d without an index register"),
24eab124 8266 1 << i.log2_scale_factor);
252b5132 8267 i.log2_scale_factor = 0;
252b5132 8268 }
551c1ca1
AM		 8269 scale = input_line_pointer;
8270 input_line_pointer = save;
8271 return scale;
252b5132
RH		 8272}
8273
252b5132 8274static int
e3bb37b5 8275i386_displacement (char *disp_start, char *disp_end)
252b5132 8276{
29b0f896 8277 expressionS *exp;
252b5132
RH		 8278 segT exp_seg = 0;
8279 char *save_input_line_pointer;
f3c180ae 8280 char *gotfree_input_line;
40fb9820
L		 8281 int override;
8282 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8283 int ret;
252b5132 8284
31b2323c
L		 8285 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8286 {
8287 as_bad (_("at most %d displacement operands are allowed"),
8288 MAX_MEMORY_OPERANDS);
8289 return 0;
8290 }
8291
0dfbf9d7 8292 operand_type_set (&bigdisp, 0);
40fb9820
L		 8293 if ((i.types[this_operand].bitfield.jumpabsolute)
8294 || (!current_templates->start->opcode_modifier.jump
8295 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8296 {
40fb9820 8297 bigdisp.bitfield.disp32 = 1;
e05278af 8298 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8299 if (flag_code == CODE_64BIT)
8300 {
8301 if (!override)
8302 {
8303 bigdisp.bitfield.disp32s = 1;
8304 bigdisp.bitfield.disp64 = 1;
8305 }
8306 }
8307 else if ((flag_code == CODE_16BIT) ^ override)
8308 {
8309 bigdisp.bitfield.disp32 = 0;
8310 bigdisp.bitfield.disp16 = 1;
8311 }
e05278af
JB		 8312 }
8313 else
8314 {
8315 /* For PC-relative branches, the width of the displacement
8316 is dependent upon data size, not address size. */
e05278af 8317 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8318 if (flag_code == CODE_64BIT)
8319 {
8320 if (override || i.suffix == WORD_MNEM_SUFFIX)
8321 bigdisp.bitfield.disp16 = 1;
8322 else
8323 {
8324 bigdisp.bitfield.disp32 = 1;
8325 bigdisp.bitfield.disp32s = 1;
8326 }
8327 }
8328 else
e05278af
JB		 8329 {
8330 if (!override)
8331 override = (i.suffix == (flag_code != CODE_16BIT
8332 ? WORD_MNEM_SUFFIX
8333 : LONG_MNEM_SUFFIX));
40fb9820
L		 8334 bigdisp.bitfield.disp32 = 1;
8335 if ((flag_code == CODE_16BIT) ^ override)
8336 {
8337 bigdisp.bitfield.disp32 = 0;
8338 bigdisp.bitfield.disp16 = 1;
8339 }
e05278af 8340 }
e05278af 8341 }
c6fb90c8
L		 8342 i.types[this_operand] = operand_type_or (i.types[this_operand],
8343 bigdisp);
252b5132
RH		 8344
8345 exp = &disp_expressions[i.disp_operands];
520dc8e8 8346 i.op[this_operand].disps = exp;
252b5132
RH		 8347 i.disp_operands++;
8348 save_input_line_pointer = input_line_pointer;
8349 input_line_pointer = disp_start;
8350 END_STRING_AND_SAVE (disp_end);
8351
8352#ifndef GCC_ASM_O_HACK
8353#define GCC_ASM_O_HACK 0
8354#endif
8355#if GCC_ASM_O_HACK
8356 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8357 if (i.types[this_operand].bitfield.baseIndex
24eab124 8358 && displacement_string_end[-1] == '+')
252b5132
RH		 8359 {
8360 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8361 constraint within gcc asm statements.
8362 For instance:
8363
8364 #define _set_tssldt_desc(n,addr,limit,type) \
8365 __asm__ __volatile__ ( \
8366 "movw %w2,%0\n\t" \
8367 "movw %w1,2+%0\n\t" \
8368 "rorl $16,%1\n\t" \
8369 "movb %b1,4+%0\n\t" \
8370 "movb %4,5+%0\n\t" \
8371 "movb $0,6+%0\n\t" \
8372 "movb %h1,7+%0\n\t" \
8373 "rorl $16,%1" \
8374 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8375
8376 This works great except that the output assembler ends
8377 up looking a bit weird if it turns out that there is
8378 no offset. You end up producing code that looks like:
8379
8380 #APP
8381 movw $235,(%eax)
8382 movw %dx,2+(%eax)
8383 rorl $16,%edx
8384 movb %dl,4+(%eax)
8385 movb $137,5+(%eax)
8386 movb $0,6+(%eax)
8387 movb %dh,7+(%eax)
8388 rorl $16,%edx
8389 #NO_APP
8390
47926f60 8391 So here we provide the missing zero. */
24eab124
AM		 8392
8393 *displacement_string_end = '0';
252b5132
RH		 8394 }
8395#endif
d258b828 8396 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8397 if (gotfree_input_line)
8398 input_line_pointer = gotfree_input_line;
252b5132 8399
24eab124 8400 exp_seg = expression (exp);
252b5132 8401
636c26b0
AM		 8402 SKIP_WHITESPACE ();
8403 if (*input_line_pointer)
8404 as_bad (_("junk `%s' after expression"), input_line_pointer);
8405#if GCC_ASM_O_HACK
8406 RESTORE_END_STRING (disp_end + 1);
8407#endif
636c26b0 8408 input_line_pointer = save_input_line_pointer;
636c26b0 8409 if (gotfree_input_line)
ee86248c
JB		 8410 {
8411 free (gotfree_input_line);
8412
8413 if (exp->X_op == O_constant || exp->X_op == O_register)
8414 exp->X_op = O_illegal;
8415 }
8416
8417 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8418
8419 RESTORE_END_STRING (disp_end);
8420
8421 return ret;
8422}
8423
8424static int
8425i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8426 i386_operand_type types, const char *disp_start)
8427{
8428 i386_operand_type bigdisp;
8429 int ret = 1;
636c26b0 8430
24eab124
AM		 8431 /* We do this to make sure that the section symbol is in
8432 the symbol table. We will ultimately change the relocation
47926f60 8433 to be relative to the beginning of the section. */
1ae12ab7 8434 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8435 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8436 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8437 {
636c26b0 8438 if (exp->X_op != O_symbol)
3992d3b7 8439 goto inv_disp;
636c26b0 8440
e5cb08ac 8441 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8442 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8443 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8444 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8445 exp->X_op = O_subtract;
8446 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8447 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8448 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8449 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8450 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8451 else
29b0f896 8452 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8453 }
252b5132 8454
3992d3b7
AM		 8455 else if (exp->X_op == O_absent
8456 || exp->X_op == O_illegal
ee86248c 8457 || exp->X_op == O_big)
2daf4fd8 8458 {
3992d3b7
AM		 8459 inv_disp:
8460 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8461 disp_start);
3992d3b7 8462 ret = 0;
2daf4fd8
AM		 8463 }
8464
0e1147d9
L		 8465 else if (flag_code == CODE_64BIT
8466 && !i.prefix[ADDR_PREFIX]
8467 && exp->X_op == O_constant)
8468 {
8469 /* Since displacement is signed extended to 64bit, don't allow
8470 disp32 and turn off disp32s if they are out of range. */
8471 i.types[this_operand].bitfield.disp32 = 0;
8472 if (!fits_in_signed_long (exp->X_add_number))
8473 {
8474 i.types[this_operand].bitfield.disp32s = 0;
8475 if (i.types[this_operand].bitfield.baseindex)
8476 {
8477 as_bad (_("0x%lx out range of signed 32bit displacement"),
8478 (long) exp->X_add_number);
8479 ret = 0;
8480 }
8481 }
8482 }
8483
4c63da97 8484#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8485 else if (exp->X_op != O_constant
8486 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8487 && exp_seg != absolute_section
8488 && exp_seg != text_section
8489 && exp_seg != data_section
8490 && exp_seg != bss_section
8491 && exp_seg != undefined_section
8492 && !bfd_is_com_section (exp_seg))
24eab124 8493 {
d0b47220 8494 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8495 ret = 0;
24eab124 8496 }
252b5132 8497#endif
3956db08 8498
40fb9820
L		 8499 /* Check if this is a displacement only operand. */
8500 bigdisp = i.types[this_operand];
8501 bigdisp.bitfield.disp8 = 0;
8502 bigdisp.bitfield.disp16 = 0;
8503 bigdisp.bitfield.disp32 = 0;
8504 bigdisp.bitfield.disp32s = 0;
8505 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8506 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8507 i.types[this_operand] = operand_type_and (i.types[this_operand],
8508 types);
3956db08 8509
3992d3b7 8510 return ret;
252b5132
RH		 8511}
8512
eecb386c 8513/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8514 Return 1 on success, 0 on a failure. */
8515
252b5132 8516static int
e3bb37b5 8517i386_index_check (const char *operand_string)
252b5132 8518{
fc0763e6 8519 const char *kind = "base/index";
be05d201
L		 8520 enum flag_code addr_mode;
8521
8522 if (i.prefix[ADDR_PREFIX])
8523 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8524 else
8525 {
8526 addr_mode = flag_code;
8527
24eab124 8528#if INFER_ADDR_PREFIX
be05d201
L		 8529 if (i.mem_operands == 0)
8530 {
8531 /* Infer address prefix from the first memory operand. */
8532 const reg_entry *addr_reg = i.base_reg;
8533
8534 if (addr_reg == NULL)
8535 addr_reg = i.index_reg;
eecb386c 8536
be05d201
L		 8537 if (addr_reg)
8538 {
8539 if (addr_reg->reg_num == RegEip
8540 || addr_reg->reg_num == RegEiz
8541 || addr_reg->reg_type.bitfield.reg32)
8542 addr_mode = CODE_32BIT;
8543 else if (flag_code != CODE_64BIT
8544 && addr_reg->reg_type.bitfield.reg16)
8545 addr_mode = CODE_16BIT;
8546
8547 if (addr_mode != flag_code)
8548 {
8549 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8550 i.prefixes += 1;
8551 /* Change the size of any displacement too. At most one
8552 of Disp16 or Disp32 is set.
8553 FIXME. There doesn't seem to be any real need for
8554 separate Disp16 and Disp32 flags. The same goes for
8555 Imm16 and Imm32. Removing them would probably clean
8556 up the code quite a lot. */
8557 if (flag_code != CODE_64BIT
8558 && (i.types[this_operand].bitfield.disp16
8559 || i.types[this_operand].bitfield.disp32))
8560 i.types[this_operand]
8561 = operand_type_xor (i.types[this_operand], disp16_32);
8562 }
8563 }
8564 }
24eab124 8565#endif
be05d201
L		 8566 }
8567
fc0763e6
JB		 8568 if (current_templates->start->opcode_modifier.isstring
8569 && !current_templates->start->opcode_modifier.immext
8570 && (current_templates->end[-1].opcode_modifier.isstring
8571 || i.mem_operands))
8572 {
8573 /* Memory operands of string insns are special in that they only allow
8574 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8575 const reg_entry *expected_reg;
8576 static const char *di_si[][2] =
8577 {
8578 { "esi", "edi" },
8579 { "si", "di" },
8580 { "rsi", "rdi" }
8581 };
8582 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8583
8584 kind = "string address";
8585
8325cc63 8586 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8587 {
8588 i386_operand_type type = current_templates->end[-1].operand_types[0];
8589
8590 if (!type.bitfield.baseindex
8591 || ((!i.mem_operands != !intel_syntax)
8592 && current_templates->end[-1].operand_types[1]
8593 .bitfield.baseindex))
8594 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8595 expected_reg = hash_find (reg_hash,
8596 di_si[addr_mode][type.bitfield.esseg]);
8597
fc0763e6
JB		 8598 }
8599 else
be05d201 8600 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8601
be05d201
L		 8602 if (i.base_reg != expected_reg
8603 || i.index_reg
fc0763e6 8604 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8605 {
be05d201
L		 8606 /* The second memory operand must have the same size as
8607 the first one. */
8608 if (i.mem_operands
8609 && i.base_reg
8610 && !((addr_mode == CODE_64BIT
8611 && i.base_reg->reg_type.bitfield.reg64)
8612 || (addr_mode == CODE_32BIT
8613 ? i.base_reg->reg_type.bitfield.reg32
8614 : i.base_reg->reg_type.bitfield.reg16)))
8615 goto bad_address;
8616
fc0763e6
JB		 8617 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8618 operand_string,
8619 intel_syntax ? '[' : '(',
8620 register_prefix,
be05d201 8621 expected_reg->reg_name,
fc0763e6 8622 intel_syntax ? ']' : ')');
be05d201 8623 return 1;
fc0763e6 8624 }
be05d201
L		 8625 else
8626 return 1;
8627
8628bad_address:
8629 as_bad (_("`%s' is not a valid %s expression"),
8630 operand_string, kind);
8631 return 0;
3e73aa7c
JH		 8632 }
8633 else
8634 {
be05d201
L		 8635 if (addr_mode != CODE_16BIT)
8636 {
8637 /* 32-bit/64-bit checks. */
8638 if ((i.base_reg
8639 && (addr_mode == CODE_64BIT
8640 ? !i.base_reg->reg_type.bitfield.reg64
8641 : !i.base_reg->reg_type.bitfield.reg32)
8642 && (i.index_reg
8643 || (i.base_reg->reg_num
8644 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8645 || (i.index_reg
8646 && !i.index_reg->reg_type.bitfield.regxmm
8647 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8648 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8649 && ((addr_mode == CODE_64BIT
8650 ? !(i.index_reg->reg_type.bitfield.reg64
8651 || i.index_reg->reg_num == RegRiz)
8652 : !(i.index_reg->reg_type.bitfield.reg32
8653 || i.index_reg->reg_num == RegEiz))
8654 || !i.index_reg->reg_type.bitfield.baseindex)))
8655 goto bad_address;
8178be5b
JB		 8656
8657 /* bndmk, bndldx, and bndstx have special restrictions. */
8658 if (current_templates->start->base_opcode == 0xf30f1b
8659 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8660 {
8661 /* They cannot use RIP-relative addressing. */
8662 if (i.base_reg && i.base_reg->reg_num == RegRip)
8663 {
8664 as_bad (_("`%s' cannot be used here"), operand_string);
8665 return 0;
8666 }
8667
8668 /* bndldx and bndstx ignore their scale factor. */
8669 if (current_templates->start->base_opcode != 0xf30f1b
8670 && i.log2_scale_factor)
8671 as_warn (_("register scaling is being ignored here"));
8672 }
be05d201
L		 8673 }
8674 else
3e73aa7c 8675 {
be05d201 8676 /* 16-bit checks. */
3e73aa7c 8677 if ((i.base_reg
40fb9820
L		 8678 && (!i.base_reg->reg_type.bitfield.reg16
8679 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8680 || (i.index_reg
40fb9820
L		 8681 && (!i.index_reg->reg_type.bitfield.reg16
8682 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8683 || !(i.base_reg
8684 && i.base_reg->reg_num < 6
8685 && i.index_reg->reg_num >= 6
8686 && i.log2_scale_factor == 0))))
be05d201 8687 goto bad_address;
3e73aa7c
JH		 8688 }
8689 }
be05d201 8690 return 1;
24eab124 8691}
252b5132 8692
43234a1e
L		 8693/* Handle vector immediates. */
8694
8695static int
8696RC_SAE_immediate (const char *imm_start)
8697{
8698 unsigned int match_found, j;
8699 const char *pstr = imm_start;
8700 expressionS *exp;
8701
8702 if (*pstr != '{')
8703 return 0;
8704
8705 pstr++;
8706 match_found = 0;
8707 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8708 {
8709 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8710 {
8711 if (!i.rounding)
8712 {
8713 rc_op.type = RC_NamesTable[j].type;
8714 rc_op.operand = this_operand;
8715 i.rounding = &rc_op;
8716 }
8717 else
8718 {
8719 as_bad (_("duplicated `%s'"), imm_start);
8720 return 0;
8721 }
8722 pstr += RC_NamesTable[j].len;
8723 match_found = 1;
8724 break;
8725 }
8726 }
8727 if (!match_found)
8728 return 0;
8729
8730 if (*pstr++ != '}')
8731 {
8732 as_bad (_("Missing '}': '%s'"), imm_start);
8733 return 0;
8734 }
8735 /* RC/SAE immediate string should contain nothing more. */;
8736 if (*pstr != 0)
8737 {
8738 as_bad (_("Junk after '}': '%s'"), imm_start);
8739 return 0;
8740 }
8741
8742 exp = &im_expressions[i.imm_operands++];
8743 i.op[this_operand].imms = exp;
8744
8745 exp->X_op = O_constant;
8746 exp->X_add_number = 0;
8747 exp->X_add_symbol = (symbolS *) 0;
8748 exp->X_op_symbol = (symbolS *) 0;
8749
8750 i.types[this_operand].bitfield.imm8 = 1;
8751 return 1;
8752}
8753
8325cc63
JB		 8754/* Only string instructions can have a second memory operand, so
8755 reduce current_templates to just those if it contains any. */
8756static int
8757maybe_adjust_templates (void)
8758{
8759 const insn_template *t;
8760
8761 gas_assert (i.mem_operands == 1);
8762
8763 for (t = current_templates->start; t < current_templates->end; ++t)
8764 if (t->opcode_modifier.isstring)
8765 break;
8766
8767 if (t < current_templates->end)
8768 {
8769 static templates aux_templates;
8770 bfd_boolean recheck;
8771
8772 aux_templates.start = t;
8773 for (; t < current_templates->end; ++t)
8774 if (!t->opcode_modifier.isstring)
8775 break;
8776 aux_templates.end = t;
8777
8778 /* Determine whether to re-check the first memory operand. */
8779 recheck = (aux_templates.start != current_templates->start
8780 || t != current_templates->end);
8781
8782 current_templates = &aux_templates;
8783
8784 if (recheck)
8785 {
8786 i.mem_operands = 0;
8787 if (i.memop1_string != NULL
8788 && i386_index_check (i.memop1_string) == 0)
8789 return 0;
8790 i.mem_operands = 1;
8791 }
8792 }
8793
8794 return 1;
8795}
8796
fc0763e6 8797/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8798 on error. */
252b5132 8799
252b5132 8800static int
a7619375 8801i386_att_operand (char *operand_string)
252b5132 8802{
af6bdddf
AM		 8803 const reg_entry *r;
8804 char *end_op;
24eab124 8805 char *op_string = operand_string;
252b5132 8806
24eab124 8807 if (is_space_char (*op_string))
252b5132
RH		 8808 ++op_string;
8809
24eab124 8810 /* We check for an absolute prefix (differentiating,
47926f60 8811 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8812 if (*op_string == ABSOLUTE_PREFIX)
8813 {
8814 ++op_string;
8815 if (is_space_char (*op_string))
8816 ++op_string;
40fb9820 8817 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8818 }
252b5132 8819
47926f60 8820 /* Check if operand is a register. */
4d1bb795 8821 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8822 {
40fb9820
L		 8823 i386_operand_type temp;
8824
24eab124
AM		 8825 /* Check for a segment override by searching for ':' after a
8826 segment register. */
8827 op_string = end_op;
8828 if (is_space_char (*op_string))
8829 ++op_string;
40fb9820
L		 8830 if (*op_string == ':'
8831 && (r->reg_type.bitfield.sreg2
8832 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8833 {
8834 switch (r->reg_num)
8835 {
8836 case 0:
8837 i.seg[i.mem_operands] = &es;
8838 break;
8839 case 1:
8840 i.seg[i.mem_operands] = &cs;
8841 break;
8842 case 2:
8843 i.seg[i.mem_operands] = &ss;
8844 break;
8845 case 3:
8846 i.seg[i.mem_operands] = &ds;
8847 break;
8848 case 4:
8849 i.seg[i.mem_operands] = &fs;
8850 break;
8851 case 5:
8852 i.seg[i.mem_operands] = &gs;
8853 break;
8854 }
252b5132 8855
24eab124 8856 /* Skip the ':' and whitespace. */
252b5132
RH		 8857 ++op_string;
8858 if (is_space_char (*op_string))
24eab124 8859 ++op_string;
252b5132 8860
24eab124
AM		 8861 if (!is_digit_char (*op_string)
8862 && !is_identifier_char (*op_string)
8863 && *op_string != '('
8864 && *op_string != ABSOLUTE_PREFIX)
8865 {
8866 as_bad (_("bad memory operand `%s'"), op_string);
8867 return 0;
8868 }
47926f60 8869 /* Handle case of %es:*foo. */
24eab124
AM		 8870 if (*op_string == ABSOLUTE_PREFIX)
8871 {
8872 ++op_string;
8873 if (is_space_char (*op_string))
8874 ++op_string;
40fb9820 8875 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8876 }
8877 goto do_memory_reference;
8878 }
43234a1e
L		 8879
8880 /* Handle vector operations. */
8881 if (*op_string == '{')
8882 {
8883 op_string = check_VecOperations (op_string, NULL);
8884 if (op_string == NULL)
8885 return 0;
8886 }
8887
24eab124
AM		 8888 if (*op_string)
8889 {
d0b47220 8890 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8891 return 0;
8892 }
40fb9820
L		 8893 temp = r->reg_type;
8894 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8895 i.types[this_operand] = operand_type_or (i.types[this_operand],
8896 temp);
7d5e4556 8897 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8898 i.op[this_operand].regs = r;
24eab124
AM		 8899 i.reg_operands++;
8900 }
af6bdddf
AM		 8901 else if (*op_string == REGISTER_PREFIX)
8902 {
8903 as_bad (_("bad register name `%s'"), op_string);
8904 return 0;
8905 }
24eab124 8906 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8907 {
24eab124 8908 ++op_string;
40fb9820 8909 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8910 {
d0b47220 8911 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8912 return 0;
8913 }
8914 if (!i386_immediate (op_string))
8915 return 0;
8916 }
43234a1e
L		 8917 else if (RC_SAE_immediate (operand_string))
8918 {
8919 /* If it is a RC or SAE immediate, do nothing. */
8920 ;
8921 }
24eab124
AM		 8922 else if (is_digit_char (*op_string)
8923 || is_identifier_char (*op_string)
d02603dc 8924 || *op_string == '"'
e5cb08ac 8925 || *op_string == '(')
24eab124 8926 {
47926f60 8927 /* This is a memory reference of some sort. */
af6bdddf 8928 char *base_string;
252b5132 8929
47926f60 8930 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8931 char *displacement_string_start;
8932 char *displacement_string_end;
43234a1e 8933 char *vop_start;
252b5132 8934
24eab124 8935 do_memory_reference:
8325cc63
JB		 8936 if (i.mem_operands == 1 && !maybe_adjust_templates ())
8937 return 0;
24eab124 8938 if ((i.mem_operands == 1
40fb9820 8939 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8940 || i.mem_operands == 2)
8941 {
8942 as_bad (_("too many memory references for `%s'"),
8943 current_templates->start->name);
8944 return 0;
8945 }
252b5132 8946
24eab124
AM		 8947 /* Check for base index form. We detect the base index form by
8948 looking for an ')' at the end of the operand, searching
8949 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8950 after the '('. */
af6bdddf 8951 base_string = op_string + strlen (op_string);
c3332e24 8952
43234a1e
L		 8953 /* Handle vector operations. */
8954 vop_start = strchr (op_string, '{');
8955 if (vop_start && vop_start < base_string)
8956 {
8957 if (check_VecOperations (vop_start, base_string) == NULL)
8958 return 0;
8959 base_string = vop_start;
8960 }
8961
af6bdddf
AM		 8962 --base_string;
8963 if (is_space_char (*base_string))
8964 --base_string;
252b5132 8965
47926f60 8966 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8967 displacement_string_start = op_string;
8968 displacement_string_end = base_string + 1;
252b5132 8969
24eab124
AM		 8970 if (*base_string == ')')
8971 {
af6bdddf 8972 char *temp_string;
24eab124
AM		 8973 unsigned int parens_balanced = 1;
8974 /* We've already checked that the number of left & right ()'s are
47926f60 8975 equal, so this loop will not be infinite. */
24eab124
AM		 8976 do
8977 {
8978 base_string--;
8979 if (*base_string == ')')
8980 parens_balanced++;
8981 if (*base_string == '(')
8982 parens_balanced--;
8983 }
8984 while (parens_balanced);
c3332e24 8985
af6bdddf 8986 temp_string = base_string;
c3332e24 8987
24eab124 8988 /* Skip past '(' and whitespace. */
252b5132
RH		 8989 ++base_string;
8990 if (is_space_char (*base_string))
24eab124 8991 ++base_string;
252b5132 8992
af6bdddf 8993 if (*base_string == ','
4eed87de
AM		 8994 || ((i.base_reg = parse_register (base_string, &end_op))
8995 != NULL))
252b5132 8996 {
af6bdddf 8997 displacement_string_end = temp_string;
252b5132 8998
40fb9820 8999 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9000
af6bdddf 9001 if (i.base_reg)
24eab124 9002 {
24eab124
AM		 9003 base_string = end_op;
9004 if (is_space_char (*base_string))
9005 ++base_string;
af6bdddf
AM		 9006 }
9007
9008 /* There may be an index reg or scale factor here. */
9009 if (*base_string == ',')
9010 {
9011 ++base_string;
9012 if (is_space_char (*base_string))
9013 ++base_string;
9014
4eed87de
AM		 9015 if ((i.index_reg = parse_register (base_string, &end_op))
9016 != NULL)
24eab124 9017 {
af6bdddf 9018 base_string = end_op;
24eab124
AM		 9019 if (is_space_char (*base_string))
9020 ++base_string;
af6bdddf
AM		 9021 if (*base_string == ',')
9022 {
9023 ++base_string;
9024 if (is_space_char (*base_string))
9025 ++base_string;
9026 }
e5cb08ac 9027 else if (*base_string != ')')
af6bdddf 9028 {
4eed87de
AM		 9029 as_bad (_("expecting `,' or `)' "
9030 "after index register in `%s'"),
af6bdddf
AM		 9031 operand_string);
9032 return 0;
9033 }
24eab124 9034 }
af6bdddf 9035 else if (*base_string == REGISTER_PREFIX)
24eab124 9036 {
f76bf5e0
L		 9037 end_op = strchr (base_string, ',');
9038 if (end_op)
9039 *end_op = '\0';
af6bdddf 9040 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9041 return 0;
9042 }
252b5132 9043
47926f60 9044 /* Check for scale factor. */
551c1ca1 9045 if (*base_string != ')')
af6bdddf 9046 {
551c1ca1
AM		 9047 char *end_scale = i386_scale (base_string);
9048
9049 if (!end_scale)
af6bdddf 9050 return 0;
24eab124 9051
551c1ca1 9052 base_string = end_scale;
af6bdddf
AM		 9053 if (is_space_char (*base_string))
9054 ++base_string;
9055 if (*base_string != ')')
9056 {
4eed87de
AM		 9057 as_bad (_("expecting `)' "
9058 "after scale factor in `%s'"),
af6bdddf
AM		 9059 operand_string);
9060 return 0;
9061 }
9062 }
9063 else if (!i.index_reg)
24eab124 9064 {
4eed87de
AM		 9065 as_bad (_("expecting index register or scale factor "
9066 "after `,'; got '%c'"),
af6bdddf 9067 *base_string);
24eab124
AM		 9068 return 0;
9069 }
9070 }
af6bdddf 9071 else if (*base_string != ')')
24eab124 9072 {
4eed87de
AM		 9073 as_bad (_("expecting `,' or `)' "
9074 "after base register in `%s'"),
af6bdddf 9075 operand_string);
24eab124
AM		 9076 return 0;
9077 }
c3332e24 9078 }
af6bdddf 9079 else if (*base_string == REGISTER_PREFIX)
c3332e24 9080 {
f76bf5e0
L		 9081 end_op = strchr (base_string, ',');
9082 if (end_op)
9083 *end_op = '\0';
af6bdddf 9084 as_bad (_("bad register name `%s'"), base_string);
24eab124 9085 return 0;
c3332e24 9086 }
24eab124
AM		 9087 }
9088
9089 /* If there's an expression beginning the operand, parse it,
9090 assuming displacement_string_start and
9091 displacement_string_end are meaningful. */
9092 if (displacement_string_start != displacement_string_end)
9093 {
9094 if (!i386_displacement (displacement_string_start,
9095 displacement_string_end))
9096 return 0;
9097 }
9098
9099 /* Special case for (%dx) while doing input/output op. */
9100 if (i.base_reg
0dfbf9d7
L		 9101 && operand_type_equal (&i.base_reg->reg_type,
9102 &reg16_inoutportreg)
24eab124
AM		 9103 && i.index_reg == 0
9104 && i.log2_scale_factor == 0
9105 && i.seg[i.mem_operands] == 0
40fb9820 9106 && !operand_type_check (i.types[this_operand], disp))
24eab124 9107 {
65da13b5 9108 i.types[this_operand] = inoutportreg;
24eab124
AM		 9109 return 1;
9110 }
9111
eecb386c
AM		 9112 if (i386_index_check (operand_string) == 0)
9113 return 0;
5c07affc 9114 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9115 if (i.mem_operands == 0)
9116 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9117 i.mem_operands++;
9118 }
9119 else
ce8a8b2f
AM		 9120 {
9121 /* It's not a memory operand; argh! */
24eab124
AM		 9122 as_bad (_("invalid char %s beginning operand %d `%s'"),
9123 output_invalid (*op_string),
9124 this_operand + 1,
9125 op_string);
9126 return 0;
9127 }
47926f60 9128 return 1; /* Normal return. */
252b5132
RH		 9129}
9130\f
fa94de6b
RM		 9131/* Calculate the maximum variable size (i.e., excluding fr_fix)
9132 that an rs_machine_dependent frag may reach. */
9133
9134unsigned int
9135i386_frag_max_var (fragS *frag)
9136{
9137 /* The only relaxable frags are for jumps.
9138 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9139 gas_assert (frag->fr_type == rs_machine_dependent);
9140 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9141}
9142
b084df0b
L		 9143#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9144static int
8dcea932 9145elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9146{
9147 /* STT_GNU_IFUNC symbol must go through PLT. */
9148 if ((symbol_get_bfdsym (fr_symbol)->flags
9149 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9150 return 0;
9151
9152 if (!S_IS_EXTERNAL (fr_symbol))
9153 /* Symbol may be weak or local. */
9154 return !S_IS_WEAK (fr_symbol);
9155
8dcea932
L		 9156 /* Global symbols with non-default visibility can't be preempted. */
9157 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9158 return 1;
9159
9160 if (fr_var != NO_RELOC)
9161 switch ((enum bfd_reloc_code_real) fr_var)
9162 {
9163 case BFD_RELOC_386_PLT32:
9164 case BFD_RELOC_X86_64_PLT32:
9165 /* Symbol with PLT relocatin may be preempted. */
9166 return 0;
9167 default:
9168 abort ();
9169 }
9170
b084df0b
L		 9171 /* Global symbols with default visibility in a shared library may be
9172 preempted by another definition. */
8dcea932 9173 return !shared;
b084df0b
L		 9174}
9175#endif
9176
ee7fcc42
AM		 9177/* md_estimate_size_before_relax()
9178
9179 Called just before relax() for rs_machine_dependent frags. The x86
9180 assembler uses these frags to handle variable size jump
9181 instructions.
9182
9183 Any symbol that is now undefined will not become defined.
9184 Return the correct fr_subtype in the frag.
9185 Return the initial "guess for variable size of frag" to caller.
9186 The guess is actually the growth beyond the fixed part. Whatever
9187 we do to grow the fixed or variable part contributes to our
9188 returned value. */
9189
252b5132 9190int
7016a5d5 9191md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9192{
252b5132 9193 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9194 check for un-relaxable symbols. On an ELF system, we can't relax
9195 an externally visible symbol, because it may be overridden by a
9196 shared library. */
9197 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9198#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9199 || (IS_ELF
8dcea932
L		 9200 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9201 fragP->fr_var))
fbeb56a4
DK		 9202#endif
9203#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9204 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9205 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9206#endif
9207 )
252b5132 9208 {
b98ef147
AM		 9209 /* Symbol is undefined in this segment, or we need to keep a
9210 reloc so that weak symbols can be overridden. */
9211 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9212 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9213 unsigned char *opcode;
9214 int old_fr_fix;
f6af82bd 9215
ee7fcc42 9216 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9217 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9218 else if (size == 2)
f6af82bd
AM		 9219 reloc_type = BFD_RELOC_16_PCREL;
9220 else
9221 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9222
ee7fcc42
AM		 9223 old_fr_fix = fragP->fr_fix;
9224 opcode = (unsigned char *) fragP->fr_opcode;
9225
fddf5b5b 9226 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9227 {
fddf5b5b
AM		 9228 case UNCOND_JUMP:
9229 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9230 opcode[0] = 0xe9;
252b5132 9231 fragP->fr_fix += size;
062cd5e7
AS		 9232 fix_new (fragP, old_fr_fix, size,
9233 fragP->fr_symbol,
9234 fragP->fr_offset, 1,
9235 reloc_type);
252b5132
RH		 9236 break;
9237
fddf5b5b 9238 case COND_JUMP86:
412167cb
AM		 9239 if (size == 2
9240 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9241 {
9242 /* Negate the condition, and branch past an
9243 unconditional jump. */
9244 opcode[0] ^= 1;
9245 opcode[1] = 3;
9246 /* Insert an unconditional jump. */
9247 opcode[2] = 0xe9;
9248 /* We added two extra opcode bytes, and have a two byte
9249 offset. */
9250 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9251 fix_new (fragP, old_fr_fix + 2, 2,
9252 fragP->fr_symbol,
9253 fragP->fr_offset, 1,
9254 reloc_type);
fddf5b5b
AM		 9255 break;
9256 }
9257 /* Fall through. */
9258
9259 case COND_JUMP:
412167cb
AM		 9260 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9261 {
3e02c1cc
AM		 9262 fixS *fixP;
9263
412167cb 9264 fragP->fr_fix += 1;
3e02c1cc
AM		 9265 fixP = fix_new (fragP, old_fr_fix, 1,
9266 fragP->fr_symbol,
9267 fragP->fr_offset, 1,
9268 BFD_RELOC_8_PCREL);
9269 fixP->fx_signed = 1;
412167cb
AM		 9270 break;
9271 }
93c2a809 9272
24eab124 9273 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9274 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9275 opcode[1] = opcode[0] + 0x10;
f6af82bd 9276 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9277 /* We've added an opcode byte. */
9278 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9279 fix_new (fragP, old_fr_fix + 1, size,
9280 fragP->fr_symbol,
9281 fragP->fr_offset, 1,
9282 reloc_type);
252b5132 9283 break;
fddf5b5b
AM		 9284
9285 default:
9286 BAD_CASE (fragP->fr_subtype);
9287 break;
252b5132
RH		 9288 }
9289 frag_wane (fragP);
ee7fcc42 9290 return fragP->fr_fix - old_fr_fix;
252b5132 9291 }
93c2a809 9292
93c2a809
AM		 9293 /* Guess size depending on current relax state. Initially the relax
9294 state will correspond to a short jump and we return 1, because
9295 the variable part of the frag (the branch offset) is one byte
9296 long. However, we can relax a section more than once and in that
9297 case we must either set fr_subtype back to the unrelaxed state,
9298 or return the value for the appropriate branch. */
9299 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9300}
9301
47926f60
KH		 9302/* Called after relax() is finished.
9303
9304 In: Address of frag.
9305 fr_type == rs_machine_dependent.
9306 fr_subtype is what the address relaxed to.
9307
9308 Out: Any fixSs and constants are set up.
9309 Caller will turn frag into a ".space 0". */
9310
252b5132 9311void
7016a5d5
TG		 9312md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9313 fragS *fragP)
252b5132 9314{
29b0f896 9315 unsigned char *opcode;
252b5132 9316 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9317 offsetT target_address;
9318 offsetT opcode_address;
252b5132 9319 unsigned int extension = 0;
847f7ad4 9320 offsetT displacement_from_opcode_start;
252b5132
RH		 9321
9322 opcode = (unsigned char *) fragP->fr_opcode;
9323
47926f60 9324 /* Address we want to reach in file space. */
252b5132 9325 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9326
47926f60 9327 /* Address opcode resides at in file space. */
252b5132
RH		 9328 opcode_address = fragP->fr_address + fragP->fr_fix;
9329
47926f60 9330 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9331 displacement_from_opcode_start = target_address - opcode_address;
9332
fddf5b5b 9333 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9334 {
47926f60
KH		 9335 /* Don't have to change opcode. */
9336 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9337 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9338 }
9339 else
9340 {
9341 if (no_cond_jump_promotion
9342 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9343 as_warn_where (fragP->fr_file, fragP->fr_line,
9344 _("long jump required"));
252b5132 9345
fddf5b5b
AM		 9346 switch (fragP->fr_subtype)
9347 {
9348 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9349 extension = 4; /* 1 opcode + 4 displacement */
9350 opcode[0] = 0xe9;
9351 where_to_put_displacement = &opcode[1];
9352 break;
252b5132 9353
fddf5b5b
AM		 9354 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9355 extension = 2; /* 1 opcode + 2 displacement */
9356 opcode[0] = 0xe9;
9357 where_to_put_displacement = &opcode[1];
9358 break;
252b5132 9359
fddf5b5b
AM		 9360 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9361 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9362 extension = 5; /* 2 opcode + 4 displacement */
9363 opcode[1] = opcode[0] + 0x10;
9364 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9365 where_to_put_displacement = &opcode[2];
9366 break;
252b5132 9367
fddf5b5b
AM		 9368 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9369 extension = 3; /* 2 opcode + 2 displacement */
9370 opcode[1] = opcode[0] + 0x10;
9371 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9372 where_to_put_displacement = &opcode[2];
9373 break;
252b5132 9374
fddf5b5b
AM		 9375 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9376 extension = 4;
9377 opcode[0] ^= 1;
9378 opcode[1] = 3;
9379 opcode[2] = 0xe9;
9380 where_to_put_displacement = &opcode[3];
9381 break;
9382
9383 default:
9384 BAD_CASE (fragP->fr_subtype);
9385 break;
9386 }
252b5132 9387 }
fddf5b5b 9388
7b81dfbb
AJ		 9389 /* If size if less then four we are sure that the operand fits,
9390 but if it's 4, then it could be that the displacement is larger
9391 then -/+ 2GB. */
9392 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9393 && object_64bit
9394 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9395 + ((addressT) 1 << 31))
9396 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9397 {
9398 as_bad_where (fragP->fr_file, fragP->fr_line,
9399 _("jump target out of range"));
9400 /* Make us emit 0. */
9401 displacement_from_opcode_start = extension;
9402 }
47926f60 9403 /* Now put displacement after opcode. */
252b5132
RH		 9404 md_number_to_chars ((char *) where_to_put_displacement,
9405 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9406 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9407 fragP->fr_fix += extension;
9408}
9409\f
7016a5d5 9410/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9411 by our caller that we have all the info we need to fix it up.
9412
7016a5d5
TG		 9413 Parameter valP is the pointer to the value of the bits.
9414
252b5132
RH		 9415 On the 386, immediates, displacements, and data pointers are all in
9416 the same (little-endian) format, so we don't need to care about which
9417 we are handling. */
9418
94f592af 9419void
7016a5d5 9420md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9421{
94f592af 9422 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9423 valueT value = *valP;
252b5132 9424
f86103b7 9425#if !defined (TE_Mach)
93382f6d
AM		 9426 if (fixP->fx_pcrel)
9427 {
9428 switch (fixP->fx_r_type)
9429 {
5865bb77
ILT		 9430 default:
9431 break;
9432
d6ab8113
JB		 9433 case BFD_RELOC_64:
9434 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9435 break;
93382f6d 9436 case BFD_RELOC_32:
ae8887b5 9437 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9438 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9439 break;
9440 case BFD_RELOC_16:
9441 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9442 break;
9443 case BFD_RELOC_8:
9444 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9445 break;
9446 }
9447 }
252b5132 9448
a161fe53 9449 if (fixP->fx_addsy != NULL
31312f95 9450 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9451 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9452 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9453 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9454 && !use_rela_relocations)
252b5132 9455 {
31312f95
AM		 9456 /* This is a hack. There should be a better way to handle this.
9457 This covers for the fact that bfd_install_relocation will
9458 subtract the current location (for partial_inplace, PC relative
9459 relocations); see more below. */
252b5132 9460#ifndef OBJ_AOUT
718ddfc0 9461 if (IS_ELF
252b5132
RH		 9462#ifdef TE_PE
9463 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9464#endif
9465 )
9466 value += fixP->fx_where + fixP->fx_frag->fr_address;
9467#endif
9468#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9469 if (IS_ELF)
252b5132 9470 {
6539b54b 9471 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9472
6539b54b 9473 if ((sym_seg == seg
2f66722d 9474 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9475 && sym_seg != absolute_section))
af65af87 9476 && !generic_force_reloc (fixP))
2f66722d
AM		 9477 {
9478 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9479 bfd_install_relocation subtracts them out again. I think
9480 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9481 it. FIXME. */
9482 value += fixP->fx_where + fixP->fx_frag->fr_address;
9483 }
252b5132
RH		 9484 }
9485#endif
9486#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9487 /* For some reason, the PE format does not store a
9488 section address offset for a PC relative symbol. */
9489 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9490 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9491 value += md_pcrel_from (fixP);
9492#endif
9493 }
fbeb56a4 9494#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9495 if (fixP->fx_addsy != NULL
9496 && S_IS_WEAK (fixP->fx_addsy)
9497 /* PR 16858: Do not modify weak function references. */
9498 && ! fixP->fx_pcrel)
fbeb56a4 9499 {
296a8689
NC		 9500#if !defined (TE_PEP)
9501 /* For x86 PE weak function symbols are neither PC-relative
9502 nor do they set S_IS_FUNCTION. So the only reliable way
9503 to detect them is to check the flags of their containing
9504 section. */
9505 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9506 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9507 ;
9508 else
9509#endif
fbeb56a4
DK		 9510 value -= S_GET_VALUE (fixP->fx_addsy);
9511 }
9512#endif
252b5132
RH		 9513
9514 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9515 and we must not disappoint it. */
252b5132 9516#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9517 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9518 switch (fixP->fx_r_type)
9519 {
9520 case BFD_RELOC_386_PLT32:
3e73aa7c 9521 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9522 /* Make the jump instruction point to the address of the operand. At
9523 runtime we merely add the offset to the actual PLT entry. */
9524 value = -4;
9525 break;
31312f95 9526
13ae64f3
JJ		 9527 case BFD_RELOC_386_TLS_GD:
9528 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9529 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9530 case BFD_RELOC_386_TLS_IE:
9531 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9532 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9533 case BFD_RELOC_X86_64_TLSGD:
9534 case BFD_RELOC_X86_64_TLSLD:
9535 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9536 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9537 value = 0; /* Fully resolved at runtime. No addend. */
9538 /* Fallthrough */
9539 case BFD_RELOC_386_TLS_LE:
9540 case BFD_RELOC_386_TLS_LDO_32:
9541 case BFD_RELOC_386_TLS_LE_32:
9542 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9543 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9544 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9545 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9546 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9547 break;
9548
67a4f2b7
AO		 9549 case BFD_RELOC_386_TLS_DESC_CALL:
9550 case BFD_RELOC_X86_64_TLSDESC_CALL:
9551 value = 0; /* Fully resolved at runtime. No addend. */
9552 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9553 fixP->fx_done = 0;
9554 return;
9555
47926f60
KH		 9556 case BFD_RELOC_VTABLE_INHERIT:
9557 case BFD_RELOC_VTABLE_ENTRY:
9558 fixP->fx_done = 0;
94f592af 9559 return;
47926f60
KH		 9560
9561 default:
9562 break;
9563 }
9564#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9565 *valP = value;
f86103b7 9566#endif /* !defined (TE_Mach) */
3e73aa7c 9567
3e73aa7c 9568 /* Are we finished with this relocation now? */
c6682705 9569 if (fixP->fx_addsy == NULL)
3e73aa7c 9570 fixP->fx_done = 1;
fbeb56a4
DK		 9571#if defined (OBJ_COFF) && defined (TE_PE)
9572 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9573 {
9574 fixP->fx_done = 0;
9575 /* Remember value for tc_gen_reloc. */
9576 fixP->fx_addnumber = value;
9577 /* Clear out the frag for now. */
9578 value = 0;
9579 }
9580#endif
3e73aa7c
JH		 9581 else if (use_rela_relocations)
9582 {
9583 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9584 /* Remember value for tc_gen_reloc. */
9585 fixP->fx_addnumber = value;
3e73aa7c
JH		 9586 value = 0;
9587 }
f86103b7 9588
94f592af 9589 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9590}
252b5132 9591\f
6d4af3c2 9592const char *
499ac353 9593md_atof (int type, char *litP, int *sizeP)
252b5132 9594{
499ac353
NC		 9595 /* This outputs the LITTLENUMs in REVERSE order;
9596 in accord with the bigendian 386. */
9597 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9598}
9599\f
2d545b82 9600static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9601
252b5132 9602static char *
e3bb37b5 9603output_invalid (int c)
252b5132 9604{
3882b010 9605 if (ISPRINT (c))
f9f21a03
L		 9606 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9607 "'%c'", c);
252b5132 9608 else
f9f21a03 9609 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9610 "(0x%x)", (unsigned char) c);
252b5132
RH		 9611 return output_invalid_buf;
9612}
9613
af6bdddf 9614/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9615
9616static const reg_entry *
4d1bb795 9617parse_real_register (char *reg_string, char **end_op)
252b5132 9618{
af6bdddf
AM		 9619 char *s = reg_string;
9620 char *p;
252b5132
RH		 9621 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9622 const reg_entry *r;
9623
9624 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9625 if (*s == REGISTER_PREFIX)
9626 ++s;
9627
9628 if (is_space_char (*s))
9629 ++s;
9630
9631 p = reg_name_given;
af6bdddf 9632 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9633 {
9634 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9635 return (const reg_entry *) NULL;
9636 s++;
252b5132
RH		 9637 }
9638
6588847e
DN		 9639 /* For naked regs, make sure that we are not dealing with an identifier.
9640 This prevents confusing an identifier like `eax_var' with register
9641 `eax'. */
9642 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9643 return (const reg_entry *) NULL;
9644
af6bdddf 9645 *end_op = s;
252b5132
RH		 9646
9647 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9648
5f47d35b 9649 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9650 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9651 {
5f47d35b
AM		 9652 if (is_space_char (*s))
9653 ++s;
9654 if (*s == '(')
9655 {
af6bdddf 9656 ++s;
5f47d35b
AM		 9657 if (is_space_char (*s))
9658 ++s;
9659 if (*s >= '0' && *s <= '7')
9660 {
db557034 9661 int fpr = *s - '0';
af6bdddf 9662 ++s;
5f47d35b
AM		 9663 if (is_space_char (*s))
9664 ++s;
9665 if (*s == ')')
9666 {
9667 *end_op = s + 1;
1e9cc1c2 9668 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9669 know (r);
9670 return r + fpr;
5f47d35b 9671 }
5f47d35b 9672 }
47926f60 9673 /* We have "%st(" then garbage. */
5f47d35b
AM		 9674 return (const reg_entry *) NULL;
9675 }
9676 }
9677
a60de03c
JB		 9678 if (r == NULL || allow_pseudo_reg)
9679 return r;
9680
0dfbf9d7 9681 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9682 return (const reg_entry *) NULL;
9683
192dc9c6
JB		 9684 if ((r->reg_type.bitfield.reg32
9685 || r->reg_type.bitfield.sreg3
9686 || r->reg_type.bitfield.control
9687 || r->reg_type.bitfield.debug
9688 || r->reg_type.bitfield.test)
9689 && !cpu_arch_flags.bitfield.cpui386)
9690 return (const reg_entry *) NULL;
9691
309d3373
JB		 9692 if (r->reg_type.bitfield.floatreg
9693 && !cpu_arch_flags.bitfield.cpu8087
9694 && !cpu_arch_flags.bitfield.cpu287
9695 && !cpu_arch_flags.bitfield.cpu387)
9696 return (const reg_entry *) NULL;
9697
1848e567 9698 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9699 return (const reg_entry *) NULL;
9700
1848e567 9701 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9702 return (const reg_entry *) NULL;
9703
1848e567 9704 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9705 return (const reg_entry *) NULL;
9706
1848e567
L		 9707 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9708 return (const reg_entry *) NULL;
9709
9710 if (r->reg_type.bitfield.regmask
9711 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9712 return (const reg_entry *) NULL;
9713
db51cc60 9714 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9715 if (!allow_index_reg
db51cc60
L		 9716 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9717 return (const reg_entry *) NULL;
9718
43234a1e
L		 9719 /* Upper 16 vector register is only available with VREX in 64bit
9720 mode. */
9721 if ((r->reg_flags & RegVRex))
9722 {
9723 if (!cpu_arch_flags.bitfield.cpuvrex
9724 || flag_code != CODE_64BIT)
9725 return (const reg_entry *) NULL;
9726
9727 i.need_vrex = 1;
9728 }
9729
a60de03c
JB		 9730 if (((r->reg_flags & (RegRex64 | RegRex))
9731 || r->reg_type.bitfield.reg64)
40fb9820 9732 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9733 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9734 && flag_code != CODE_64BIT)
20f0a1fc 9735 return (const reg_entry *) NULL;
1ae00879 9736
b7240065
JB		 9737 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9738 return (const reg_entry *) NULL;
9739
252b5132
RH		 9740 return r;
9741}
4d1bb795
JB		 9742
9743/* REG_STRING starts *before* REGISTER_PREFIX. */
9744
9745static const reg_entry *
9746parse_register (char *reg_string, char **end_op)
9747{
9748 const reg_entry *r;
9749
9750 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9751 r = parse_real_register (reg_string, end_op);
9752 else
9753 r = NULL;
9754 if (!r)
9755 {
9756 char *save = input_line_pointer;
9757 char c;
9758 symbolS *symbolP;
9759
9760 input_line_pointer = reg_string;
d02603dc 9761 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9762 symbolP = symbol_find (reg_string);
9763 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9764 {
9765 const expressionS *e = symbol_get_value_expression (symbolP);
9766
0398aac5 9767 know (e->X_op == O_register);
4eed87de 9768 know (e->X_add_number >= 0
c3fe08fa 9769 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9770 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9771 if ((r->reg_flags & RegVRex))
9772 i.need_vrex = 1;
4d1bb795
JB		 9773 *end_op = input_line_pointer;
9774 }
9775 *input_line_pointer = c;
9776 input_line_pointer = save;
9777 }
9778 return r;
9779}
9780
9781int
9782i386_parse_name (char *name, expressionS *e, char *nextcharP)
9783{
9784 const reg_entry *r;
9785 char *end = input_line_pointer;
9786
9787 *end = *nextcharP;
9788 r = parse_register (name, &input_line_pointer);
9789 if (r && end <= input_line_pointer)
9790 {
9791 *nextcharP = *input_line_pointer;
9792 *input_line_pointer = 0;
9793 e->X_op = O_register;
9794 e->X_add_number = r - i386_regtab;
9795 return 1;
9796 }
9797 input_line_pointer = end;
9798 *end = 0;
ee86248c 9799 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9800}
9801
9802void
9803md_operand (expressionS *e)
9804{
ee86248c
JB		 9805 char *end;
9806 const reg_entry *r;
4d1bb795 9807
ee86248c
JB		 9808 switch (*input_line_pointer)
9809 {
9810 case REGISTER_PREFIX:
9811 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9812 if (r)
9813 {
9814 e->X_op = O_register;
9815 e->X_add_number = r - i386_regtab;
9816 input_line_pointer = end;
9817 }
ee86248c
JB		 9818 break;
9819
9820 case '[':
9c2799c2 9821 gas_assert (intel_syntax);
ee86248c
JB		 9822 end = input_line_pointer++;
9823 expression (e);
9824 if (*input_line_pointer == ']')
9825 {
9826 ++input_line_pointer;
9827 e->X_op_symbol = make_expr_symbol (e);
9828 e->X_add_symbol = NULL;
9829 e->X_add_number = 0;
9830 e->X_op = O_index;
9831 }
9832 else
9833 {
9834 e->X_op = O_absent;
9835 input_line_pointer = end;
9836 }
9837 break;
4d1bb795
JB		 9838 }
9839}
9840
252b5132 9841\f
4cc782b5 9842#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9843const char *md_shortopts = "kVQ:sqn";
252b5132 9844#else
12b55ccc 9845const char *md_shortopts = "qn";
252b5132 9846#endif
6e0b89ee 9847
3e73aa7c 9848#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9849#define OPTION_64 (OPTION_MD_BASE + 1)
9850#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9851#define OPTION_MARCH (OPTION_MD_BASE + 3)
9852#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9853#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9854#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9855#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9856#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9857#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9858#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9859#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9860#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9861#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9862#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9863#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9864#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9865#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9866#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9867#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9868#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9869#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9870#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9871#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9872#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9873#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9874
99ad8390
NC		 9875struct option md_longopts[] =
9876{
3e73aa7c 9877 {"32", no_argument, NULL, OPTION_32},
321098a5 9878#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9879 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9880 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9881#endif
9882#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9883 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9884 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9885#endif
b3b91714 9886 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9887 {"march", required_argument, NULL, OPTION_MARCH},
9888 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9889 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9890 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9891 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9892 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9893 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9894 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9895 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9896 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9897 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9898 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9899 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9900 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9901# if defined (TE_PE) || defined (TE_PEP)
9902 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9903#endif
d1982f93 9904 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9905 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9906 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9907 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9908 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9909 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9910 {NULL, no_argument, NULL, 0}
9911};
9912size_t md_longopts_size = sizeof (md_longopts);
9913
9914int
17b9d67d 9915md_parse_option (int c, const char *arg)
252b5132 9916{
91d6fa6a 9917 unsigned int j;
293f5f65 9918 char *arch, *next, *saved;
9103f4f4 9919
252b5132
RH		 9920 switch (c)
9921 {
12b55ccc
L		 9922 case 'n':
9923 optimize_align_code = 0;
9924 break;
9925
a38cf1db
AM		 9926 case 'q':
9927 quiet_warnings = 1;
252b5132
RH		 9928 break;
9929
9930#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9931 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9932 should be emitted or not. FIXME: Not implemented. */
9933 case 'Q':
252b5132
RH		 9934 break;
9935
9936 /* -V: SVR4 argument to print version ID. */
9937 case 'V':
9938 print_version_id ();
9939 break;
9940
a38cf1db
AM		 9941 /* -k: Ignore for FreeBSD compatibility. */
9942 case 'k':
252b5132 9943 break;
4cc782b5
ILT		 9944
9945 case 's':
9946 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9947 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9948 break;
8dcea932
L		 9949
9950 case OPTION_MSHARED:
9951 shared = 1;
9952 break;
99ad8390 9953#endif
321098a5 9954#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9955 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9956 case OPTION_64:
9957 {
9958 const char **list, **l;
9959
3e73aa7c
JH		 9960 list = bfd_target_list ();
9961 for (l = list; *l != NULL; l++)
8620418b 9962 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9963 || strcmp (*l, "coff-x86-64") == 0
9964 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9965 || strcmp (*l, "pei-x86-64") == 0
9966 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9967 {
9968 default_arch = "x86_64";
9969 break;
9970 }
3e73aa7c 9971 if (*l == NULL)
2b5d6a91 9972 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9973 free (list);
9974 }
9975 break;
9976#endif
252b5132 9977
351f65ca 9978#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9979 case OPTION_X32:
351f65ca
L		 9980 if (IS_ELF)
9981 {
9982 const char **list, **l;
9983
9984 list = bfd_target_list ();
9985 for (l = list; *l != NULL; l++)
9986 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9987 {
9988 default_arch = "x86_64:32";
9989 break;
9990 }
9991 if (*l == NULL)
2b5d6a91 9992 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9993 free (list);
9994 }
9995 else
9996 as_fatal (_("32bit x86_64 is only supported for ELF"));
9997 break;
9998#endif
9999
6e0b89ee
AM		 10000 case OPTION_32:
10001 default_arch = "i386";
10002 break;
10003
b3b91714
AM		 10004 case OPTION_DIVIDE:
10005#ifdef SVR4_COMMENT_CHARS
10006 {
10007 char *n, *t;
10008 const char *s;
10009
add39d23 10010 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10011 t = n;
10012 for (s = i386_comment_chars; *s != '\0'; s++)
10013 if (*s != '/')
10014 *t++ = *s;
10015 *t = '\0';
10016 i386_comment_chars = n;
10017 }
10018#endif
10019 break;
10020
9103f4f4 10021 case OPTION_MARCH:
293f5f65
L		 10022 saved = xstrdup (arg);
10023 arch = saved;
10024 /* Allow -march=+nosse. */
10025 if (*arch == '+')
10026 arch++;
6305a203 10027 do
9103f4f4 10028 {
6305a203 10029 if (*arch == '.')
2b5d6a91 10030 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10031 next = strchr (arch, '+');
10032 if (next)
10033 *next++ = '\0';
91d6fa6a 10034 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10035 {
91d6fa6a 10036 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10037 {
6305a203 10038 /* Processor. */
1ded5609
JB		 10039 if (! cpu_arch[j].flags.bitfield.cpui386)
10040 continue;
10041
91d6fa6a 10042 cpu_arch_name = cpu_arch[j].name;
6305a203 10043 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10044 cpu_arch_flags = cpu_arch[j].flags;
10045 cpu_arch_isa = cpu_arch[j].type;
10046 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10047 if (!cpu_arch_tune_set)
10048 {
10049 cpu_arch_tune = cpu_arch_isa;
10050 cpu_arch_tune_flags = cpu_arch_isa_flags;
10051 }
10052 break;
10053 }
91d6fa6a
NC		 10054 else if (*cpu_arch [j].name == '.'
10055 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 10056 {
10057 /* ISA entension. */
10058 i386_cpu_flags flags;
309d3373 10059
293f5f65
L		 10060 flags = cpu_flags_or (cpu_arch_flags,
10061 cpu_arch[j].flags);
81486035 10062
5b64d091 10063 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10064 {
10065 if (cpu_sub_arch_name)
10066 {
10067 char *name = cpu_sub_arch_name;
10068 cpu_sub_arch_name = concat (name,
91d6fa6a 10069 cpu_arch[j].name,
1bf57e9f 10070 (const char *) NULL);
6305a203
L		 10071 free (name);
10072 }
10073 else
91d6fa6a 10074 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10075 cpu_arch_flags = flags;
a586129e 10076 cpu_arch_isa_flags = flags;
6305a203
L		 10077 }
10078 break;
ccc9c027 10079 }
9103f4f4 10080 }
6305a203 10081
293f5f65
L		 10082 if (j >= ARRAY_SIZE (cpu_arch))
10083 {
10084 /* Disable an ISA entension. */
10085 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10086 if (strcmp (arch, cpu_noarch [j].name) == 0)
10087 {
10088 i386_cpu_flags flags;
10089
10090 flags = cpu_flags_and_not (cpu_arch_flags,
10091 cpu_noarch[j].flags);
10092 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10093 {
10094 if (cpu_sub_arch_name)
10095 {
10096 char *name = cpu_sub_arch_name;
10097 cpu_sub_arch_name = concat (arch,
10098 (const char *) NULL);
10099 free (name);
10100 }
10101 else
10102 cpu_sub_arch_name = xstrdup (arch);
10103 cpu_arch_flags = flags;
10104 cpu_arch_isa_flags = flags;
10105 }
10106 break;
10107 }
10108
10109 if (j >= ARRAY_SIZE (cpu_noarch))
10110 j = ARRAY_SIZE (cpu_arch);
10111 }
10112
91d6fa6a 10113 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10114 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10115
10116 arch = next;
9103f4f4 10117 }
293f5f65
L		 10118 while (next != NULL);
10119 free (saved);
9103f4f4
L		 10120 break;
10121
10122 case OPTION_MTUNE:
10123 if (*arg == '.')
2b5d6a91 10124 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10125 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10126 {
91d6fa6a 10127 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10128 {
ccc9c027 10129 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10130 cpu_arch_tune = cpu_arch [j].type;
10131 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10132 break;
10133 }
10134 }
91d6fa6a 10135 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10136 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10137 break;
10138
1efbbeb4
L		 10139 case OPTION_MMNEMONIC:
10140 if (strcasecmp (arg, "att") == 0)
10141 intel_mnemonic = 0;
10142 else if (strcasecmp (arg, "intel") == 0)
10143 intel_mnemonic = 1;
10144 else
2b5d6a91 10145 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10146 break;
10147
10148 case OPTION_MSYNTAX:
10149 if (strcasecmp (arg, "att") == 0)
10150 intel_syntax = 0;
10151 else if (strcasecmp (arg, "intel") == 0)
10152 intel_syntax = 1;
10153 else
2b5d6a91 10154 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10155 break;
10156
10157 case OPTION_MINDEX_REG:
10158 allow_index_reg = 1;
10159 break;
10160
10161 case OPTION_MNAKED_REG:
10162 allow_naked_reg = 1;
10163 break;
10164
10165 case OPTION_MOLD_GCC:
10166 old_gcc = 1;
1efbbeb4
L		 10167 break;
10168
c0f3af97
L		 10169 case OPTION_MSSE2AVX:
10170 sse2avx = 1;
10171 break;
10172
daf50ae7
L		 10173 case OPTION_MSSE_CHECK:
10174 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10175 sse_check = check_error;
daf50ae7 10176 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10177 sse_check = check_warning;
daf50ae7 10178 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10179 sse_check = check_none;
daf50ae7 10180 else
2b5d6a91 10181 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10182 break;
10183
7bab8ab5
JB		 10184 case OPTION_MOPERAND_CHECK:
10185 if (strcasecmp (arg, "error") == 0)
10186 operand_check = check_error;
10187 else if (strcasecmp (arg, "warning") == 0)
10188 operand_check = check_warning;
10189 else if (strcasecmp (arg, "none") == 0)
10190 operand_check = check_none;
10191 else
10192 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10193 break;
10194
539f890d
L		 10195 case OPTION_MAVXSCALAR:
10196 if (strcasecmp (arg, "128") == 0)
10197 avxscalar = vex128;
10198 else if (strcasecmp (arg, "256") == 0)
10199 avxscalar = vex256;
10200 else
2b5d6a91 10201 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10202 break;
10203
7e8b059b
L		 10204 case OPTION_MADD_BND_PREFIX:
10205 add_bnd_prefix = 1;
10206 break;
10207
43234a1e
L		 10208 case OPTION_MEVEXLIG:
10209 if (strcmp (arg, "128") == 0)
10210 evexlig = evexl128;
10211 else if (strcmp (arg, "256") == 0)
10212 evexlig = evexl256;
10213 else if (strcmp (arg, "512") == 0)
10214 evexlig = evexl512;
10215 else
10216 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10217 break;
10218
d3d3c6db
IT		 10219 case OPTION_MEVEXRCIG:
10220 if (strcmp (arg, "rne") == 0)
10221 evexrcig = rne;
10222 else if (strcmp (arg, "rd") == 0)
10223 evexrcig = rd;
10224 else if (strcmp (arg, "ru") == 0)
10225 evexrcig = ru;
10226 else if (strcmp (arg, "rz") == 0)
10227 evexrcig = rz;
10228 else
10229 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10230 break;
10231
43234a1e
L		 10232 case OPTION_MEVEXWIG:
10233 if (strcmp (arg, "0") == 0)
10234 evexwig = evexw0;
10235 else if (strcmp (arg, "1") == 0)
10236 evexwig = evexw1;
10237 else
10238 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10239 break;
10240
167ad85b
TG		 10241# if defined (TE_PE) || defined (TE_PEP)
10242 case OPTION_MBIG_OBJ:
10243 use_big_obj = 1;
10244 break;
10245#endif
10246
d1982f93 10247 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10248 if (strcasecmp (arg, "yes") == 0)
10249 omit_lock_prefix = 1;
10250 else if (strcasecmp (arg, "no") == 0)
10251 omit_lock_prefix = 0;
10252 else
10253 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10254 break;
10255
e4e00185
AS		 10256 case OPTION_MFENCE_AS_LOCK_ADD:
10257 if (strcasecmp (arg, "yes") == 0)
10258 avoid_fence = 1;
10259 else if (strcasecmp (arg, "no") == 0)
10260 avoid_fence = 0;
10261 else
10262 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10263 break;
10264
0cb4071e
L		 10265 case OPTION_MRELAX_RELOCATIONS:
10266 if (strcasecmp (arg, "yes") == 0)
10267 generate_relax_relocations = 1;
10268 else if (strcasecmp (arg, "no") == 0)
10269 generate_relax_relocations = 0;
10270 else
10271 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10272 break;
10273
5db04b09 10274 case OPTION_MAMD64:
e89c5eaa 10275 intel64 = 0;
5db04b09
L		 10276 break;
10277
10278 case OPTION_MINTEL64:
e89c5eaa 10279 intel64 = 1;
5db04b09
L		 10280 break;
10281
252b5132
RH		 10282 default:
10283 return 0;
10284 }
10285 return 1;
10286}
10287
8a2c8fef
L		 10288#define MESSAGE_TEMPLATE \
10289" "
10290
293f5f65
L		 10291static char *
10292output_message (FILE *stream, char *p, char *message, char *start,
10293 int *left_p, const char *name, int len)
10294{
10295 int size = sizeof (MESSAGE_TEMPLATE);
10296 int left = *left_p;
10297
10298 /* Reserve 2 spaces for ", " or ",\0" */
10299 left -= len + 2;
10300
10301 /* Check if there is any room. */
10302 if (left >= 0)
10303 {
10304 if (p != start)
10305 {
10306 *p++ = ',';
10307 *p++ = ' ';
10308 }
10309 p = mempcpy (p, name, len);
10310 }
10311 else
10312 {
10313 /* Output the current message now and start a new one. */
10314 *p++ = ',';
10315 *p = '\0';
10316 fprintf (stream, "%s\n", message);
10317 p = start;
10318 left = size - (start - message) - len - 2;
10319
10320 gas_assert (left >= 0);
10321
10322 p = mempcpy (p, name, len);
10323 }
10324
10325 *left_p = left;
10326 return p;
10327}
10328
8a2c8fef 10329static void
1ded5609 10330show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10331{
10332 static char message[] = MESSAGE_TEMPLATE;
10333 char *start = message + 27;
10334 char *p;
10335 int size = sizeof (MESSAGE_TEMPLATE);
10336 int left;
10337 const char *name;
10338 int len;
10339 unsigned int j;
10340
10341 p = start;
10342 left = size - (start - message);
10343 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10344 {
10345 /* Should it be skipped? */
10346 if (cpu_arch [j].skip)
10347 continue;
10348
10349 name = cpu_arch [j].name;
10350 len = cpu_arch [j].len;
10351 if (*name == '.')
10352 {
10353 /* It is an extension. Skip if we aren't asked to show it. */
10354 if (ext)
10355 {
10356 name++;
10357 len--;
10358 }
10359 else
10360 continue;
10361 }
10362 else if (ext)
10363 {
10364 /* It is an processor. Skip if we show only extension. */
10365 continue;
10366 }
1ded5609
JB		 10367 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10368 {
10369 /* It is an impossible processor - skip. */
10370 continue;
10371 }
8a2c8fef 10372
293f5f65 10373 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10374 }
10375
293f5f65
L		 10376 /* Display disabled extensions. */
10377 if (ext)
10378 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10379 {
10380 name = cpu_noarch [j].name;
10381 len = cpu_noarch [j].len;
10382 p = output_message (stream, p, message, start, &left, name,
10383 len);
10384 }
10385
8a2c8fef
L		 10386 *p = '\0';
10387 fprintf (stream, "%s\n", message);
10388}
10389
252b5132 10390void
8a2c8fef 10391md_show_usage (FILE *stream)
252b5132 10392{
4cc782b5
ILT		 10393#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10394 fprintf (stream, _("\
a38cf1db
AM		 10395 -Q ignored\n\
10396 -V print assembler version number\n\
b3b91714
AM		 10397 -k ignored\n"));
10398#endif
10399 fprintf (stream, _("\
12b55ccc 10400 -n Do not optimize code alignment\n\
b3b91714
AM		 10401 -q quieten some warnings\n"));
10402#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10403 fprintf (stream, _("\
a38cf1db 10404 -s ignored\n"));
b3b91714 10405#endif
321098a5
L		 10406#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10407 || defined (TE_PE) || defined (TE_PEP))
751d281c 10408 fprintf (stream, _("\
570561f7 10409 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10410#endif
b3b91714
AM		 10411#ifdef SVR4_COMMENT_CHARS
10412 fprintf (stream, _("\
10413 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10414#else
10415 fprintf (stream, _("\
b3b91714 10416 --divide ignored\n"));
4cc782b5 10417#endif
9103f4f4 10418 fprintf (stream, _("\
6305a203 10419 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10420 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10421 show_arch (stream, 0, 1);
8a2c8fef
L		 10422 fprintf (stream, _("\
10423 EXTENSION is combination of:\n"));
1ded5609 10424 show_arch (stream, 1, 0);
6305a203 10425 fprintf (stream, _("\
8a2c8fef 10426 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10427 show_arch (stream, 0, 0);
ba104c83 10428 fprintf (stream, _("\
c0f3af97
L		 10429 -msse2avx encode SSE instructions with VEX prefix\n"));
10430 fprintf (stream, _("\
daf50ae7
L		 10431 -msse-check=[none|error|warning]\n\
10432 check SSE instructions\n"));
10433 fprintf (stream, _("\
7bab8ab5
JB		 10434 -moperand-check=[none|error|warning]\n\
10435 check operand combinations for validity\n"));
10436 fprintf (stream, _("\
539f890d
L		 10437 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10438 length\n"));
10439 fprintf (stream, _("\
43234a1e
L		 10440 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10441 length\n"));
10442 fprintf (stream, _("\
10443 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10444 for EVEX.W bit ignored instructions\n"));
10445 fprintf (stream, _("\
d3d3c6db
IT		 10446 -mevexrcig=[rne|rd|ru|rz]\n\
10447 encode EVEX instructions with specific EVEX.RC value\n\
10448 for SAE-only ignored instructions\n"));
10449 fprintf (stream, _("\
ba104c83
L		 10450 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10451 fprintf (stream, _("\
10452 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10453 fprintf (stream, _("\
10454 -mindex-reg support pseudo index registers\n"));
10455 fprintf (stream, _("\
10456 -mnaked-reg don't require `%%' prefix for registers\n"));
10457 fprintf (stream, _("\
10458 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10459 fprintf (stream, _("\
10460 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10461 fprintf (stream, _("\
10462 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10463# if defined (TE_PE) || defined (TE_PEP)
10464 fprintf (stream, _("\
10465 -mbig-obj generate big object files\n"));
10466#endif
d022bddd
IT		 10467 fprintf (stream, _("\
10468 -momit-lock-prefix=[no|yes]\n\
10469 strip all lock prefixes\n"));
5db04b09 10470 fprintf (stream, _("\
e4e00185
AS		 10471 -mfence-as-lock-add=[no|yes]\n\
10472 encode lfence, mfence and sfence as\n\
10473 lock addl $0x0, (%%{re}sp)\n"));
10474 fprintf (stream, _("\
0cb4071e
L		 10475 -mrelax-relocations=[no|yes]\n\
10476 generate relax relocations\n"));
10477 fprintf (stream, _("\
5db04b09
L		 10478 -mamd64 accept only AMD64 ISA\n"));
10479 fprintf (stream, _("\
10480 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10481}
10482
3e73aa7c 10483#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10484 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10485 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10486
10487/* Pick the target format to use. */
10488
47926f60 10489const char *
e3bb37b5 10490i386_target_format (void)
252b5132 10491{
351f65ca
L		 10492 if (!strncmp (default_arch, "x86_64", 6))
10493 {
10494 update_code_flag (CODE_64BIT, 1);
10495 if (default_arch[6] == '\0')
7f56bc95 10496 x86_elf_abi = X86_64_ABI;
351f65ca 10497 else
7f56bc95 10498 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10499 }
3e73aa7c 10500 else if (!strcmp (default_arch, "i386"))
78f12dd3 10501 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10502 else if (!strcmp (default_arch, "iamcu"))
10503 {
10504 update_code_flag (CODE_32BIT, 1);
10505 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10506 {
10507 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10508 cpu_arch_name = "iamcu";
10509 cpu_sub_arch_name = NULL;
10510 cpu_arch_flags = iamcu_flags;
10511 cpu_arch_isa = PROCESSOR_IAMCU;
10512 cpu_arch_isa_flags = iamcu_flags;
10513 if (!cpu_arch_tune_set)
10514 {
10515 cpu_arch_tune = cpu_arch_isa;
10516 cpu_arch_tune_flags = cpu_arch_isa_flags;
10517 }
10518 }
8d471ec1 10519 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10520 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10521 cpu_arch_name);
10522 }
3e73aa7c 10523 else
2b5d6a91 10524 as_fatal (_("unknown architecture"));
89507696
JB		 10525
10526 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10527 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10528 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10529 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10530
252b5132
RH		 10531 switch (OUTPUT_FLAVOR)
10532 {
9384f2ff 10533#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10534 case bfd_target_aout_flavour:
47926f60 10535 return AOUT_TARGET_FORMAT;
4c63da97 10536#endif
9384f2ff
AM		 10537#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10538# if defined (TE_PE) || defined (TE_PEP)
10539 case bfd_target_coff_flavour:
167ad85b
TG		 10540 if (flag_code == CODE_64BIT)
10541 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10542 else
10543 return "pe-i386";
9384f2ff 10544# elif defined (TE_GO32)
0561d57c
JK		 10545 case bfd_target_coff_flavour:
10546 return "coff-go32";
9384f2ff 10547# else
252b5132
RH		 10548 case bfd_target_coff_flavour:
10549 return "coff-i386";
9384f2ff 10550# endif
4c63da97 10551#endif
3e73aa7c 10552#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10553 case bfd_target_elf_flavour:
3e73aa7c 10554 {
351f65ca
L		 10555 const char *format;
10556
10557 switch (x86_elf_abi)
4fa24527 10558 {
351f65ca
L		 10559 default:
10560 format = ELF_TARGET_FORMAT;
10561 break;
7f56bc95 10562 case X86_64_ABI:
351f65ca 10563 use_rela_relocations = 1;
4fa24527 10564 object_64bit = 1;
351f65ca
L		 10565 format = ELF_TARGET_FORMAT64;
10566 break;
7f56bc95 10567 case X86_64_X32_ABI:
4fa24527 10568 use_rela_relocations = 1;
351f65ca 10569 object_64bit = 1;
862be3fb 10570 disallow_64bit_reloc = 1;
351f65ca
L		 10571 format = ELF_TARGET_FORMAT32;
10572 break;
4fa24527 10573 }
3632d14b 10574 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10575 {
7f56bc95 10576 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10577 as_fatal (_("Intel L1OM is 64bit only"));
10578 return ELF_TARGET_L1OM_FORMAT;
10579 }
b49f93f6 10580 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10581 {
10582 if (x86_elf_abi != X86_64_ABI)
10583 as_fatal (_("Intel K1OM is 64bit only"));
10584 return ELF_TARGET_K1OM_FORMAT;
10585 }
81486035
L		 10586 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10587 {
10588 if (x86_elf_abi != I386_ABI)
10589 as_fatal (_("Intel MCU is 32bit only"));
10590 return ELF_TARGET_IAMCU_FORMAT;
10591 }
8a9036a4 10592 else
351f65ca 10593 return format;
3e73aa7c 10594 }
e57f8c65
TG		 10595#endif
10596#if defined (OBJ_MACH_O)
10597 case bfd_target_mach_o_flavour:
d382c579
TG		 10598 if (flag_code == CODE_64BIT)
10599 {
10600 use_rela_relocations = 1;
10601 object_64bit = 1;
10602 return "mach-o-x86-64";
10603 }
10604 else
10605 return "mach-o-i386";
4c63da97 10606#endif
252b5132
RH		 10607 default:
10608 abort ();
10609 return NULL;
10610 }
10611}
10612
47926f60 10613#endif /* OBJ_MAYBE_ more than one */
252b5132 10614\f
252b5132 10615symbolS *
7016a5d5 10616md_undefined_symbol (char *name)
252b5132 10617{
18dc2407
ILT		 10618 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10619 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10620 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10621 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10622 {
10623 if (!GOT_symbol)
10624 {
10625 if (symbol_find (name))
10626 as_bad (_("GOT already in symbol table"));
10627 GOT_symbol = symbol_new (name, undefined_section,
10628 (valueT) 0, &zero_address_frag);
10629 };
10630 return GOT_symbol;
10631 }
252b5132
RH		 10632 return 0;
10633}
10634
10635/* Round up a section size to the appropriate boundary. */
47926f60 10636
252b5132 10637valueT
7016a5d5 10638md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10639{
4c63da97
AM		 10640#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10641 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10642 {
10643 /* For a.out, force the section size to be aligned. If we don't do
10644 this, BFD will align it for us, but it will not write out the
10645 final bytes of the section. This may be a bug in BFD, but it is
10646 easier to fix it here since that is how the other a.out targets
10647 work. */
10648 int align;
10649
10650 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10651 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10652 }
252b5132
RH		 10653#endif
10654
10655 return size;
10656}
10657
10658/* On the i386, PC-relative offsets are relative to the start of the
10659 next instruction. That is, the address of the offset, plus its
10660 size, since the offset is always the last part of the insn. */
10661
10662long
e3bb37b5 10663md_pcrel_from (fixS *fixP)
252b5132
RH		 10664{
10665 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10666}
10667
10668#ifndef I386COFF
10669
10670static void
e3bb37b5 10671s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10672{
29b0f896 10673 int temp;
252b5132 10674
8a75718c
JB		 10675#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10676 if (IS_ELF)
10677 obj_elf_section_change_hook ();
10678#endif
252b5132
RH		 10679 temp = get_absolute_expression ();
10680 subseg_set (bss_section, (subsegT) temp);
10681 demand_empty_rest_of_line ();
10682}
10683
10684#endif
10685
252b5132 10686void
e3bb37b5 10687i386_validate_fix (fixS *fixp)
252b5132 10688{
02a86693 10689 if (fixp->fx_subsy)
252b5132 10690 {
02a86693 10691 if (fixp->fx_subsy == GOT_symbol)
23df1078 10692 {
02a86693
L		 10693 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10694 {
10695 if (!object_64bit)
10696 abort ();
10697#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10698 if (fixp->fx_tcbit2)
56ceb5b5
L		 10699 fixp->fx_r_type = (fixp->fx_tcbit
10700 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10701 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10702 else
10703#endif
10704 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10705 }
d6ab8113 10706 else
02a86693
L		 10707 {
10708 if (!object_64bit)
10709 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10710 else
10711 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10712 }
10713 fixp->fx_subsy = 0;
23df1078 10714 }
252b5132 10715 }
02a86693
L		 10716#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10717 else if (!object_64bit)
10718 {
10719 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10720 && fixp->fx_tcbit2)
10721 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10722 }
10723#endif
252b5132
RH		 10724}
10725
252b5132 10726arelent *
7016a5d5 10727tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10728{
10729 arelent *rel;
10730 bfd_reloc_code_real_type code;
10731
10732 switch (fixp->fx_r_type)
10733 {
8ce3d284 10734#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10735 case BFD_RELOC_SIZE32:
10736 case BFD_RELOC_SIZE64:
10737 if (S_IS_DEFINED (fixp->fx_addsy)
10738 && !S_IS_EXTERNAL (fixp->fx_addsy))
10739 {
10740 /* Resolve size relocation against local symbol to size of
10741 the symbol plus addend. */
10742 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10743 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10744 && !fits_in_unsigned_long (value))
10745 as_bad_where (fixp->fx_file, fixp->fx_line,
10746 _("symbol size computation overflow"));
10747 fixp->fx_addsy = NULL;
10748 fixp->fx_subsy = NULL;
10749 md_apply_fix (fixp, (valueT *) &value, NULL);
10750 return NULL;
10751 }
8ce3d284 10752#endif
1a0670f3 10753 /* Fall through. */
8fd4256d 10754
3e73aa7c
JH		 10755 case BFD_RELOC_X86_64_PLT32:
10756 case BFD_RELOC_X86_64_GOT32:
10757 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10758 case BFD_RELOC_X86_64_GOTPCRELX:
10759 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10760 case BFD_RELOC_386_PLT32:
10761 case BFD_RELOC_386_GOT32:
02a86693 10762 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10763 case BFD_RELOC_386_GOTOFF:
10764 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10765 case BFD_RELOC_386_TLS_GD:
10766 case BFD_RELOC_386_TLS_LDM:
10767 case BFD_RELOC_386_TLS_LDO_32:
10768 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10769 case BFD_RELOC_386_TLS_IE:
10770 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10771 case BFD_RELOC_386_TLS_LE_32:
10772 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10773 case BFD_RELOC_386_TLS_GOTDESC:
10774 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10775 case BFD_RELOC_X86_64_TLSGD:
10776 case BFD_RELOC_X86_64_TLSLD:
10777 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10778 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10779 case BFD_RELOC_X86_64_GOTTPOFF:
10780 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10781 case BFD_RELOC_X86_64_TPOFF64:
10782 case BFD_RELOC_X86_64_GOTOFF64:
10783 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10784 case BFD_RELOC_X86_64_GOT64:
10785 case BFD_RELOC_X86_64_GOTPCREL64:
10786 case BFD_RELOC_X86_64_GOTPC64:
10787 case BFD_RELOC_X86_64_GOTPLT64:
10788 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10789 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10790 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10791 case BFD_RELOC_RVA:
10792 case BFD_RELOC_VTABLE_ENTRY:
10793 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10794#ifdef TE_PE
10795 case BFD_RELOC_32_SECREL:
10796#endif
252b5132
RH		 10797 code = fixp->fx_r_type;
10798 break;
dbbaec26
L		 10799 case BFD_RELOC_X86_64_32S:
10800 if (!fixp->fx_pcrel)
10801 {
10802 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10803 code = fixp->fx_r_type;
10804 break;
10805 }
1a0670f3 10806 /* Fall through. */
252b5132 10807 default:
93382f6d 10808 if (fixp->fx_pcrel)
252b5132 10809 {
93382f6d
AM		 10810 switch (fixp->fx_size)
10811 {
10812 default:
b091f402
AM		 10813 as_bad_where (fixp->fx_file, fixp->fx_line,
10814 _("can not do %d byte pc-relative relocation"),
10815 fixp->fx_size);
93382f6d
AM		 10816 code = BFD_RELOC_32_PCREL;
10817 break;
10818 case 1: code = BFD_RELOC_8_PCREL; break;
10819 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10820 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10821#ifdef BFD64
10822 case 8: code = BFD_RELOC_64_PCREL; break;
10823#endif
93382f6d
AM		 10824 }
10825 }
10826 else
10827 {
10828 switch (fixp->fx_size)
10829 {
10830 default:
b091f402
AM		 10831 as_bad_where (fixp->fx_file, fixp->fx_line,
10832 _("can not do %d byte relocation"),
10833 fixp->fx_size);
93382f6d
AM		 10834 code = BFD_RELOC_32;
10835 break;
10836 case 1: code = BFD_RELOC_8; break;
10837 case 2: code = BFD_RELOC_16; break;
10838 case 4: code = BFD_RELOC_32; break;
937149dd 10839#ifdef BFD64
3e73aa7c 10840 case 8: code = BFD_RELOC_64; break;
937149dd 10841#endif
93382f6d 10842 }
252b5132
RH		 10843 }
10844 break;
10845 }
252b5132 10846
d182319b
JB		 10847 if ((code == BFD_RELOC_32
10848 || code == BFD_RELOC_32_PCREL
10849 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10850 && GOT_symbol
10851 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10852 {
4fa24527 10853 if (!object_64bit)
d6ab8113
JB		 10854 code = BFD_RELOC_386_GOTPC;
10855 else
10856 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10857 }
7b81dfbb
AJ		 10858 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10859 && GOT_symbol
10860 && fixp->fx_addsy == GOT_symbol)
10861 {
10862 code = BFD_RELOC_X86_64_GOTPC64;
10863 }
252b5132 10864
add39d23
TS		 10865 rel = XNEW (arelent);
10866 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10867 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10868
10869 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10870
3e73aa7c
JH		 10871 if (!use_rela_relocations)
10872 {
10873 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10874 vtable entry to be used in the relocation's section offset. */
10875 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10876 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10877#if defined (OBJ_COFF) && defined (TE_PE)
10878 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10879 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10880 else
10881#endif
c6682705 10882 rel->addend = 0;
3e73aa7c
JH		 10883 }
10884 /* Use the rela in 64bit mode. */
252b5132 10885 else
3e73aa7c 10886 {
862be3fb
L		 10887 if (disallow_64bit_reloc)
10888 switch (code)
10889 {
862be3fb
L		 10890 case BFD_RELOC_X86_64_DTPOFF64:
10891 case BFD_RELOC_X86_64_TPOFF64:
10892 case BFD_RELOC_64_PCREL:
10893 case BFD_RELOC_X86_64_GOTOFF64:
10894 case BFD_RELOC_X86_64_GOT64:
10895 case BFD_RELOC_X86_64_GOTPCREL64:
10896 case BFD_RELOC_X86_64_GOTPC64:
10897 case BFD_RELOC_X86_64_GOTPLT64:
10898 case BFD_RELOC_X86_64_PLTOFF64:
10899 as_bad_where (fixp->fx_file, fixp->fx_line,
10900 _("cannot represent relocation type %s in x32 mode"),
10901 bfd_get_reloc_code_name (code));
10902 break;
10903 default:
10904 break;
10905 }
10906
062cd5e7
AS		 10907 if (!fixp->fx_pcrel)
10908 rel->addend = fixp->fx_offset;
10909 else
10910 switch (code)
10911 {
10912 case BFD_RELOC_X86_64_PLT32:
10913 case BFD_RELOC_X86_64_GOT32:
10914 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10915 case BFD_RELOC_X86_64_GOTPCRELX:
10916 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10917 case BFD_RELOC_X86_64_TLSGD:
10918 case BFD_RELOC_X86_64_TLSLD:
10919 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10920 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10921 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10922 rel->addend = fixp->fx_offset - fixp->fx_size;
10923 break;
10924 default:
10925 rel->addend = (section->vma
10926 - fixp->fx_size
10927 + fixp->fx_addnumber
10928 + md_pcrel_from (fixp));
10929 break;
10930 }
3e73aa7c
JH		 10931 }
10932
252b5132
RH		 10933 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10934 if (rel->howto == NULL)
10935 {
10936 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10937 _("cannot represent relocation type %s"),
252b5132
RH		 10938 bfd_get_reloc_code_name (code));
10939 /* Set howto to a garbage value so that we can keep going. */
10940 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10941 gas_assert (rel->howto != NULL);
252b5132
RH		 10942 }
10943
10944 return rel;
10945}
10946
ee86248c 10947#include "tc-i386-intel.c"
54cfded0 10948
a60de03c
JB		 10949void
10950tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10951{
a60de03c
JB		 10952 int saved_naked_reg;
10953 char saved_register_dot;
54cfded0 10954
a60de03c
JB		 10955 saved_naked_reg = allow_naked_reg;
10956 allow_naked_reg = 1;
10957 saved_register_dot = register_chars['.'];
10958 register_chars['.'] = '.';
10959 allow_pseudo_reg = 1;
10960 expression_and_evaluate (exp);
10961 allow_pseudo_reg = 0;
10962 register_chars['.'] = saved_register_dot;
10963 allow_naked_reg = saved_naked_reg;
10964
e96d56a1 10965 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10966 {
a60de03c
JB		 10967 if ((addressT) exp->X_add_number < i386_regtab_size)
10968 {
10969 exp->X_op = O_constant;
10970 exp->X_add_number = i386_regtab[exp->X_add_number]
10971 .dw2_regnum[flag_code >> 1];
10972 }
10973 else
10974 exp->X_op = O_illegal;
54cfded0 10975 }
54cfded0
AM		 10976}
10977
10978void
10979tc_x86_frame_initial_instructions (void)
10980{
a60de03c
JB		 10981 static unsigned int sp_regno[2];
10982
10983 if (!sp_regno[flag_code >> 1])
10984 {
10985 char *saved_input = input_line_pointer;
10986 char sp[][4] = {"esp", "rsp"};
10987 expressionS exp;
a4447b93 10988
a60de03c
JB		 10989 input_line_pointer = sp[flag_code >> 1];
10990 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10991 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10992 sp_regno[flag_code >> 1] = exp.X_add_number;
10993 input_line_pointer = saved_input;
10994 }
a4447b93 10995
61ff971f
L		 10996 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10997 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10998}
d2b2c203 10999
d7921315
L		 11000int
11001x86_dwarf2_addr_size (void)
11002{
11003#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11004 if (x86_elf_abi == X86_64_X32_ABI)
11005 return 4;
11006#endif
11007 return bfd_arch_bits_per_address (stdoutput) / 8;
11008}
11009
d2b2c203
DJ		 11010int
11011i386_elf_section_type (const char *str, size_t len)
11012{
11013 if (flag_code == CODE_64BIT
11014 && len == sizeof ("unwind") - 1
11015 && strncmp (str, "unwind", 6) == 0)
11016 return SHT_X86_64_UNWIND;
11017
11018 return -1;
11019}
bb41ade5 11020
ad5fec3b
EB		 11021#ifdef TE_SOLARIS
11022void
11023i386_solaris_fix_up_eh_frame (segT sec)
11024{
11025 if (flag_code == CODE_64BIT)
11026 elf_section_type (sec) = SHT_X86_64_UNWIND;
11027}
11028#endif
11029
bb41ade5
AM		 11030#ifdef TE_PE
11031void
11032tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11033{
91d6fa6a 11034 expressionS exp;
bb41ade5 11035
91d6fa6a
NC		 11036 exp.X_op = O_secrel;
11037 exp.X_add_symbol = symbol;
11038 exp.X_add_number = 0;
11039 emit_expr (&exp, size);
bb41ade5
AM		 11040}
11041#endif
3b22753a
L		 11042
11043#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11044/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11045
01e1a5bc 11046bfd_vma
6d4af3c2 11047x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11048{
11049 if (flag_code == CODE_64BIT)
11050 {
11051 if (letter == 'l')
11052 return SHF_X86_64_LARGE;
11053
8f3bae45 11054 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11055 }
3b22753a 11056 else
8f3bae45 11057 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11058 return -1;
11059}
11060
01e1a5bc 11061bfd_vma
3b22753a
L		 11062x86_64_section_word (char *str, size_t len)
11063{
8620418b 11064 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11065 return SHF_X86_64_LARGE;
11066
11067 return -1;
11068}
11069
11070static void
11071handle_large_common (int small ATTRIBUTE_UNUSED)
11072{
11073 if (flag_code != CODE_64BIT)
11074 {
11075 s_comm_internal (0, elf_common_parse);
11076 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11077 }
11078 else
11079 {
11080 static segT lbss_section;
11081 asection *saved_com_section_ptr = elf_com_section_ptr;
11082 asection *saved_bss_section = bss_section;
11083
11084 if (lbss_section == NULL)
11085 {
11086 flagword applicable;
11087 segT seg = now_seg;
11088 subsegT subseg = now_subseg;
11089
11090 /* The .lbss section is for local .largecomm symbols. */
11091 lbss_section = subseg_new (".lbss", 0);
11092 applicable = bfd_applicable_section_flags (stdoutput);
11093 bfd_set_section_flags (stdoutput, lbss_section,
11094 applicable & SEC_ALLOC);
11095 seg_info (lbss_section)->bss = 1;
11096
11097 subseg_set (seg, subseg);
11098 }
11099
11100 elf_com_section_ptr = &_bfd_elf_large_com_section;
11101 bss_section = lbss_section;
11102
11103 s_comm_internal (0, elf_common_parse);
11104
11105 elf_com_section_ptr = saved_com_section_ptr;
11106 bss_section = saved_bss_section;
11107 }
11108}
11109#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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