Commit | Line | Data |
---|---|---|
b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
219d1afa | 2 | Copyright (C) 1989-2018 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 68 | #define LOCK_PREFIX 5 |
4e9ac44a L |
69 | #define REX_PREFIX 6 /* must come last. */ |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
84 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 85 | #define YMMWORD_MNEM_SUFFIX 'y' |
43234a1e | 86 | #define ZMMWORD_MNEM_SUFFIX 'z' |
6305a203 L |
87 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
88 | in instructions. */ | |
89 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
90 | ||
91 | #define END_OF_INSN '\0' | |
92 | ||
93 | /* | |
94 | 'templates' is for grouping together 'template' structures for opcodes | |
95 | of the same name. This is only used for storing the insns in the grand | |
96 | ole hash table of insns. | |
97 | The templates themselves start at START and range up to (but not including) | |
98 | END. | |
99 | */ | |
100 | typedef struct | |
101 | { | |
d3ce72d0 NC |
102 | const insn_template *start; |
103 | const insn_template *end; | |
6305a203 L |
104 | } |
105 | templates; | |
106 | ||
107 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
108 | typedef struct | |
109 | { | |
110 | unsigned int regmem; /* codes register or memory operand */ | |
111 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
112 | unsigned int mode; /* how to interpret regmem & reg */ | |
113 | } | |
114 | modrm_byte; | |
115 | ||
116 | /* x86-64 extension prefix. */ | |
117 | typedef int rex_byte; | |
118 | ||
6305a203 L |
119 | /* 386 opcode byte to code indirect addressing. */ |
120 | typedef struct | |
121 | { | |
122 | unsigned base; | |
123 | unsigned index; | |
124 | unsigned scale; | |
125 | } | |
126 | sib_byte; | |
127 | ||
6305a203 L |
128 | /* x86 arch names, types and features */ |
129 | typedef struct | |
130 | { | |
131 | const char *name; /* arch name */ | |
8a2c8fef | 132 | unsigned int len; /* arch string length */ |
6305a203 L |
133 | enum processor_type type; /* arch type */ |
134 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 135 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
136 | } |
137 | arch_entry; | |
138 | ||
293f5f65 L |
139 | /* Used to turn off indicated flags. */ |
140 | typedef struct | |
141 | { | |
142 | const char *name; /* arch name */ | |
143 | unsigned int len; /* arch string length */ | |
144 | i386_cpu_flags flags; /* cpu feature flags */ | |
145 | } | |
146 | noarch_entry; | |
147 | ||
78f12dd3 | 148 | static void update_code_flag (int, int); |
e3bb37b5 L |
149 | static void set_code_flag (int); |
150 | static void set_16bit_gcc_code_flag (int); | |
151 | static void set_intel_syntax (int); | |
1efbbeb4 | 152 | static void set_intel_mnemonic (int); |
db51cc60 | 153 | static void set_allow_index_reg (int); |
7bab8ab5 | 154 | static void set_check (int); |
e3bb37b5 | 155 | static void set_cpu_arch (int); |
6482c264 | 156 | #ifdef TE_PE |
e3bb37b5 | 157 | static void pe_directive_secrel (int); |
6482c264 | 158 | #endif |
e3bb37b5 L |
159 | static void signed_cons (int); |
160 | static char *output_invalid (int c); | |
ee86248c JB |
161 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
162 | const char *); | |
163 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
164 | const char *); | |
a7619375 | 165 | static int i386_att_operand (char *); |
e3bb37b5 | 166 | static int i386_intel_operand (char *, int); |
ee86248c JB |
167 | static int i386_intel_simplify (expressionS *); |
168 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
169 | static const reg_entry *parse_register (char *, char **); |
170 | static char *parse_insn (char *, char *); | |
171 | static char *parse_operands (char *, const char *); | |
172 | static void swap_operands (void); | |
4d456e3d | 173 | static void swap_2_operands (int, int); |
e3bb37b5 L |
174 | static void optimize_imm (void); |
175 | static void optimize_disp (void); | |
83b16ac6 | 176 | static const insn_template *match_template (char); |
e3bb37b5 L |
177 | static int check_string (void); |
178 | static int process_suffix (void); | |
179 | static int check_byte_reg (void); | |
180 | static int check_long_reg (void); | |
181 | static int check_qword_reg (void); | |
182 | static int check_word_reg (void); | |
183 | static int finalize_imm (void); | |
184 | static int process_operands (void); | |
185 | static const seg_entry *build_modrm_byte (void); | |
186 | static void output_insn (void); | |
187 | static void output_imm (fragS *, offsetT); | |
188 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 189 | #ifndef I386COFF |
e3bb37b5 | 190 | static void s_bss (int); |
252b5132 | 191 | #endif |
17d4e2a2 L |
192 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
193 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
194 | #endif | |
252b5132 | 195 | |
a847613f | 196 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 197 | |
43234a1e L |
198 | /* This struct describes rounding control and SAE in the instruction. */ |
199 | struct RC_Operation | |
200 | { | |
201 | enum rc_type | |
202 | { | |
203 | rne = 0, | |
204 | rd, | |
205 | ru, | |
206 | rz, | |
207 | saeonly | |
208 | } type; | |
209 | int operand; | |
210 | }; | |
211 | ||
212 | static struct RC_Operation rc_op; | |
213 | ||
214 | /* The struct describes masking, applied to OPERAND in the instruction. | |
215 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
216 | whether merging or zeroing mask is used. */ | |
217 | struct Mask_Operation | |
218 | { | |
219 | const reg_entry *mask; | |
220 | unsigned int zeroing; | |
221 | /* The operand where this operation is associated. */ | |
222 | int operand; | |
223 | }; | |
224 | ||
225 | static struct Mask_Operation mask_op; | |
226 | ||
227 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
228 | broadcast factor. */ | |
229 | struct Broadcast_Operation | |
230 | { | |
231 | /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */ | |
232 | int type; | |
233 | ||
234 | /* Index of broadcasted operand. */ | |
235 | int operand; | |
236 | }; | |
237 | ||
238 | static struct Broadcast_Operation broadcast_op; | |
239 | ||
c0f3af97 L |
240 | /* VEX prefix. */ |
241 | typedef struct | |
242 | { | |
43234a1e L |
243 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
244 | unsigned char bytes[4]; | |
c0f3af97 L |
245 | unsigned int length; |
246 | /* Destination or source register specifier. */ | |
247 | const reg_entry *register_specifier; | |
248 | } vex_prefix; | |
249 | ||
252b5132 | 250 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 251 | i386_insn. */ |
252b5132 | 252 | |
520dc8e8 AM |
253 | union i386_op |
254 | { | |
255 | expressionS *disps; | |
256 | expressionS *imms; | |
257 | const reg_entry *regs; | |
258 | }; | |
259 | ||
a65babc9 L |
260 | enum i386_error |
261 | { | |
86e026a4 | 262 | operand_size_mismatch, |
a65babc9 L |
263 | operand_type_mismatch, |
264 | register_type_mismatch, | |
265 | number_of_operands_mismatch, | |
266 | invalid_instruction_suffix, | |
267 | bad_imm4, | |
268 | old_gcc_only, | |
269 | unsupported_with_intel_mnemonic, | |
270 | unsupported_syntax, | |
6c30d220 L |
271 | unsupported, |
272 | invalid_vsib_address, | |
7bab8ab5 | 273 | invalid_vector_register_set, |
43234a1e L |
274 | unsupported_vector_index_register, |
275 | unsupported_broadcast, | |
276 | broadcast_not_on_src_operand, | |
277 | broadcast_needed, | |
278 | unsupported_masking, | |
279 | mask_not_on_destination, | |
280 | no_default_mask, | |
281 | unsupported_rc_sae, | |
282 | rc_sae_operand_not_last_imm, | |
283 | invalid_register_operand, | |
a65babc9 L |
284 | }; |
285 | ||
252b5132 RH |
286 | struct _i386_insn |
287 | { | |
47926f60 | 288 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 289 | insn_template tm; |
252b5132 | 290 | |
7d5e4556 L |
291 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
292 | or qword, if given. */ | |
252b5132 RH |
293 | char suffix; |
294 | ||
47926f60 | 295 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
296 | unsigned int operands; |
297 | ||
298 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
299 | of given register, displacement, memory operands and immediate | |
47926f60 | 300 | operands. */ |
252b5132 RH |
301 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
302 | ||
303 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 304 | use OP[i] for the corresponding operand. */ |
40fb9820 | 305 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 306 | |
520dc8e8 AM |
307 | /* Displacement expression, immediate expression, or register for each |
308 | operand. */ | |
309 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 310 | |
3e73aa7c JH |
311 | /* Flags for operands. */ |
312 | unsigned int flags[MAX_OPERANDS]; | |
313 | #define Operand_PCrel 1 | |
314 | ||
252b5132 | 315 | /* Relocation type for operand */ |
f86103b7 | 316 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 317 | |
252b5132 RH |
318 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
319 | the base index byte below. */ | |
320 | const reg_entry *base_reg; | |
321 | const reg_entry *index_reg; | |
322 | unsigned int log2_scale_factor; | |
323 | ||
324 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 325 | explicit segment overrides are given. */ |
ce8a8b2f | 326 | const seg_entry *seg[2]; |
252b5132 | 327 | |
8325cc63 JB |
328 | /* Copied first memory operand string, for re-checking. */ |
329 | char *memop1_string; | |
330 | ||
252b5132 RH |
331 | /* PREFIX holds all the given prefix opcodes (usually null). |
332 | PREFIXES is the number of prefix opcodes. */ | |
333 | unsigned int prefixes; | |
334 | unsigned char prefix[MAX_PREFIXES]; | |
335 | ||
336 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 337 | addressing modes of this insn are encoded. */ |
252b5132 | 338 | modrm_byte rm; |
3e73aa7c | 339 | rex_byte rex; |
43234a1e | 340 | rex_byte vrex; |
252b5132 | 341 | sib_byte sib; |
c0f3af97 | 342 | vex_prefix vex; |
b6169b20 | 343 | |
43234a1e L |
344 | /* Masking attributes. */ |
345 | struct Mask_Operation *mask; | |
346 | ||
347 | /* Rounding control and SAE attributes. */ | |
348 | struct RC_Operation *rounding; | |
349 | ||
350 | /* Broadcasting attributes. */ | |
351 | struct Broadcast_Operation *broadcast; | |
352 | ||
353 | /* Compressed disp8*N attribute. */ | |
354 | unsigned int memshift; | |
355 | ||
86fa6981 L |
356 | /* Prefer load or store in encoding. */ |
357 | enum | |
358 | { | |
359 | dir_encoding_default = 0, | |
360 | dir_encoding_load, | |
361 | dir_encoding_store | |
362 | } dir_encoding; | |
891edac4 | 363 | |
a501d77e L |
364 | /* Prefer 8bit or 32bit displacement in encoding. */ |
365 | enum | |
366 | { | |
367 | disp_encoding_default = 0, | |
368 | disp_encoding_8bit, | |
369 | disp_encoding_32bit | |
370 | } disp_encoding; | |
f8a5c266 | 371 | |
86fa6981 L |
372 | /* How to encode vector instructions. */ |
373 | enum | |
374 | { | |
375 | vex_encoding_default = 0, | |
376 | vex_encoding_vex2, | |
377 | vex_encoding_vex3, | |
378 | vex_encoding_evex | |
379 | } vec_encoding; | |
380 | ||
d5de92cf L |
381 | /* REP prefix. */ |
382 | const char *rep_prefix; | |
383 | ||
165de32a L |
384 | /* HLE prefix. */ |
385 | const char *hle_prefix; | |
42164a71 | 386 | |
7e8b059b L |
387 | /* Have BND prefix. */ |
388 | const char *bnd_prefix; | |
389 | ||
04ef582a L |
390 | /* Have NOTRACK prefix. */ |
391 | const char *notrack_prefix; | |
392 | ||
891edac4 | 393 | /* Error message. */ |
a65babc9 | 394 | enum i386_error error; |
252b5132 RH |
395 | }; |
396 | ||
397 | typedef struct _i386_insn i386_insn; | |
398 | ||
43234a1e L |
399 | /* Link RC type with corresponding string, that'll be looked for in |
400 | asm. */ | |
401 | struct RC_name | |
402 | { | |
403 | enum rc_type type; | |
404 | const char *name; | |
405 | unsigned int len; | |
406 | }; | |
407 | ||
408 | static const struct RC_name RC_NamesTable[] = | |
409 | { | |
410 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
411 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
412 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
413 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
414 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
415 | }; | |
416 | ||
252b5132 RH |
417 | /* List of chars besides those in app.c:symbol_chars that can start an |
418 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 419 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 420 | #ifdef LEX_AT |
32137342 NC |
421 | "@" |
422 | #endif | |
423 | #ifdef LEX_QM | |
424 | "?" | |
252b5132 | 425 | #endif |
32137342 | 426 | ; |
252b5132 | 427 | |
29b0f896 AM |
428 | #if (defined (TE_I386AIX) \ |
429 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 430 | && !defined (TE_GNU) \ |
29b0f896 | 431 | && !defined (TE_LINUX) \ |
8d63c93e RM |
432 | && !defined (TE_NACL) \ |
433 | && !defined (TE_NETWARE) \ | |
29b0f896 | 434 | && !defined (TE_FreeBSD) \ |
5b806d27 | 435 | && !defined (TE_DragonFly) \ |
29b0f896 | 436 | && !defined (TE_NetBSD))) |
252b5132 | 437 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
438 | pre-processor is disabled, these aren't very useful. The option |
439 | --divide will remove '/' from this list. */ | |
440 | const char *i386_comment_chars = "#/"; | |
441 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 442 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 443 | |
b3b91714 AM |
444 | #else |
445 | const char *i386_comment_chars = "#"; | |
446 | #define PREFIX_SEPARATOR '/' | |
447 | #endif | |
448 | ||
252b5132 RH |
449 | /* This array holds the chars that only start a comment at the beginning of |
450 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
451 | .line and .file directives will appear in the pre-processed output. |
452 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 453 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
454 | #NO_APP at the beginning of its output. |
455 | Also note that comments started like this one will always work if | |
252b5132 | 456 | '/' isn't otherwise defined. */ |
b3b91714 | 457 | const char line_comment_chars[] = "#/"; |
252b5132 | 458 | |
63a0b638 | 459 | const char line_separator_chars[] = ";"; |
252b5132 | 460 | |
ce8a8b2f AM |
461 | /* Chars that can be used to separate mant from exp in floating point |
462 | nums. */ | |
252b5132 RH |
463 | const char EXP_CHARS[] = "eE"; |
464 | ||
ce8a8b2f AM |
465 | /* Chars that mean this number is a floating point constant |
466 | As in 0f12.456 | |
467 | or 0d1.2345e12. */ | |
252b5132 RH |
468 | const char FLT_CHARS[] = "fFdDxX"; |
469 | ||
ce8a8b2f | 470 | /* Tables for lexical analysis. */ |
252b5132 RH |
471 | static char mnemonic_chars[256]; |
472 | static char register_chars[256]; | |
473 | static char operand_chars[256]; | |
474 | static char identifier_chars[256]; | |
475 | static char digit_chars[256]; | |
476 | ||
ce8a8b2f | 477 | /* Lexical macros. */ |
252b5132 RH |
478 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
479 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
480 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
481 | #define is_space_char(x) ((x) == ' ') | |
482 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
483 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
484 | ||
0234cb7c | 485 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
486 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
487 | ||
488 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
489 | effect this we maintain a stack of saved characters that we've smashed | |
490 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 491 | assembler instruction). */ |
252b5132 | 492 | static char save_stack[32]; |
ce8a8b2f | 493 | static char *save_stack_p; |
252b5132 RH |
494 | #define END_STRING_AND_SAVE(s) \ |
495 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
496 | #define RESTORE_END_STRING(s) \ | |
497 | do { *(s) = *--save_stack_p; } while (0) | |
498 | ||
47926f60 | 499 | /* The instruction we're assembling. */ |
252b5132 RH |
500 | static i386_insn i; |
501 | ||
502 | /* Possible templates for current insn. */ | |
503 | static const templates *current_templates; | |
504 | ||
31b2323c L |
505 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
506 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
507 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 508 | |
47926f60 | 509 | /* Current operand we are working on. */ |
ee86248c | 510 | static int this_operand = -1; |
252b5132 | 511 | |
3e73aa7c JH |
512 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
513 | these. */ | |
514 | ||
515 | enum flag_code { | |
516 | CODE_32BIT, | |
517 | CODE_16BIT, | |
518 | CODE_64BIT }; | |
519 | ||
520 | static enum flag_code flag_code; | |
4fa24527 | 521 | static unsigned int object_64bit; |
862be3fb | 522 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
523 | static int use_rela_relocations = 0; |
524 | ||
7af8ed2d NC |
525 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
526 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
527 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
528 | ||
351f65ca L |
529 | /* The ELF ABI to use. */ |
530 | enum x86_elf_abi | |
531 | { | |
532 | I386_ABI, | |
7f56bc95 L |
533 | X86_64_ABI, |
534 | X86_64_X32_ABI | |
351f65ca L |
535 | }; |
536 | ||
537 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 538 | #endif |
351f65ca | 539 | |
167ad85b TG |
540 | #if defined (TE_PE) || defined (TE_PEP) |
541 | /* Use big object file format. */ | |
542 | static int use_big_obj = 0; | |
543 | #endif | |
544 | ||
8dcea932 L |
545 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
546 | /* 1 if generating code for a shared library. */ | |
547 | static int shared = 0; | |
548 | #endif | |
549 | ||
47926f60 KH |
550 | /* 1 for intel syntax, |
551 | 0 if att syntax. */ | |
552 | static int intel_syntax = 0; | |
252b5132 | 553 | |
e89c5eaa L |
554 | /* 1 for Intel64 ISA, |
555 | 0 if AMD64 ISA. */ | |
556 | static int intel64; | |
557 | ||
1efbbeb4 L |
558 | /* 1 for intel mnemonic, |
559 | 0 if att mnemonic. */ | |
560 | static int intel_mnemonic = !SYSV386_COMPAT; | |
561 | ||
5209009a | 562 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
563 | static int old_gcc = OLDGCC_COMPAT; |
564 | ||
a60de03c JB |
565 | /* 1 if pseudo registers are permitted. */ |
566 | static int allow_pseudo_reg = 0; | |
567 | ||
47926f60 KH |
568 | /* 1 if register prefix % not required. */ |
569 | static int allow_naked_reg = 0; | |
252b5132 | 570 | |
33eaf5de | 571 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
572 | instructions supporting it, even if this prefix wasn't specified |
573 | explicitly. */ | |
574 | static int add_bnd_prefix = 0; | |
575 | ||
ba104c83 | 576 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
577 | static int allow_index_reg = 0; |
578 | ||
d022bddd IT |
579 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
580 | specified explicitly. */ | |
581 | static int omit_lock_prefix = 0; | |
582 | ||
e4e00185 AS |
583 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
584 | "lock addl $0, (%{re}sp)". */ | |
585 | static int avoid_fence = 0; | |
586 | ||
0cb4071e L |
587 | /* 1 if the assembler should generate relax relocations. */ |
588 | ||
589 | static int generate_relax_relocations | |
590 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
591 | ||
7bab8ab5 | 592 | static enum check_kind |
daf50ae7 | 593 | { |
7bab8ab5 JB |
594 | check_none = 0, |
595 | check_warning, | |
596 | check_error | |
daf50ae7 | 597 | } |
7bab8ab5 | 598 | sse_check, operand_check = check_warning; |
daf50ae7 | 599 | |
2ca3ace5 L |
600 | /* Register prefix used for error message. */ |
601 | static const char *register_prefix = "%"; | |
602 | ||
47926f60 KH |
603 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
604 | leave, push, and pop instructions so that gcc has the same stack | |
605 | frame as in 32 bit mode. */ | |
606 | static char stackop_size = '\0'; | |
eecb386c | 607 | |
12b55ccc L |
608 | /* Non-zero to optimize code alignment. */ |
609 | int optimize_align_code = 1; | |
610 | ||
47926f60 KH |
611 | /* Non-zero to quieten some warnings. */ |
612 | static int quiet_warnings = 0; | |
a38cf1db | 613 | |
47926f60 KH |
614 | /* CPU name. */ |
615 | static const char *cpu_arch_name = NULL; | |
6305a203 | 616 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 617 | |
47926f60 | 618 | /* CPU feature flags. */ |
40fb9820 L |
619 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
620 | ||
ccc9c027 L |
621 | /* If we have selected a cpu we are generating instructions for. */ |
622 | static int cpu_arch_tune_set = 0; | |
623 | ||
9103f4f4 | 624 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 625 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
626 | |
627 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 628 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 629 | |
ccc9c027 | 630 | /* CPU instruction set architecture used. */ |
fbf3f584 | 631 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 632 | |
9103f4f4 | 633 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 634 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 635 | |
fddf5b5b AM |
636 | /* If set, conditional jumps are not automatically promoted to handle |
637 | larger than a byte offset. */ | |
638 | static unsigned int no_cond_jump_promotion = 0; | |
639 | ||
c0f3af97 L |
640 | /* Encode SSE instructions with VEX prefix. */ |
641 | static unsigned int sse2avx; | |
642 | ||
539f890d L |
643 | /* Encode scalar AVX instructions with specific vector length. */ |
644 | static enum | |
645 | { | |
646 | vex128 = 0, | |
647 | vex256 | |
648 | } avxscalar; | |
649 | ||
43234a1e L |
650 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
651 | static enum | |
652 | { | |
653 | evexl128 = 0, | |
654 | evexl256, | |
655 | evexl512 | |
656 | } evexlig; | |
657 | ||
658 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
659 | static enum | |
660 | { | |
661 | evexw0 = 0, | |
662 | evexw1 | |
663 | } evexwig; | |
664 | ||
d3d3c6db IT |
665 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
666 | static enum rc_type evexrcig = rne; | |
667 | ||
29b0f896 | 668 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 669 | static symbolS *GOT_symbol; |
29b0f896 | 670 | |
a4447b93 RH |
671 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
672 | unsigned int x86_dwarf2_return_column; | |
673 | ||
674 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
675 | int x86_cie_data_alignment; | |
676 | ||
252b5132 | 677 | /* Interface to relax_segment. |
fddf5b5b AM |
678 | There are 3 major relax states for 386 jump insns because the |
679 | different types of jumps add different sizes to frags when we're | |
680 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 681 | |
47926f60 | 682 | /* Types. */ |
93c2a809 AM |
683 | #define UNCOND_JUMP 0 |
684 | #define COND_JUMP 1 | |
685 | #define COND_JUMP86 2 | |
fddf5b5b | 686 | |
47926f60 | 687 | /* Sizes. */ |
252b5132 RH |
688 | #define CODE16 1 |
689 | #define SMALL 0 | |
29b0f896 | 690 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 691 | #define BIG 2 |
29b0f896 | 692 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
693 | |
694 | #ifndef INLINE | |
695 | #ifdef __GNUC__ | |
696 | #define INLINE __inline__ | |
697 | #else | |
698 | #define INLINE | |
699 | #endif | |
700 | #endif | |
701 | ||
fddf5b5b AM |
702 | #define ENCODE_RELAX_STATE(type, size) \ |
703 | ((relax_substateT) (((type) << 2) | (size))) | |
704 | #define TYPE_FROM_RELAX_STATE(s) \ | |
705 | ((s) >> 2) | |
706 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
707 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
708 | |
709 | /* This table is used by relax_frag to promote short jumps to long | |
710 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
711 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
712 | don't allow a short jump in a 32 bit code segment to be promoted to | |
713 | a 16 bit offset jump because it's slower (requires data size | |
714 | prefix), and doesn't work, unless the destination is in the bottom | |
715 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
716 | ||
717 | const relax_typeS md_relax_table[] = | |
718 | { | |
24eab124 AM |
719 | /* The fields are: |
720 | 1) most positive reach of this state, | |
721 | 2) most negative reach of this state, | |
93c2a809 | 722 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 723 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 724 | |
fddf5b5b | 725 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
726 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
727 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
728 | /* dword jmp adds 4 bytes to frag: | |
729 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 730 | {0, 0, 4, 0}, |
93c2a809 AM |
731 | /* word jmp adds 2 byte2 to frag: |
732 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
733 | {0, 0, 2, 0}, |
734 | ||
93c2a809 AM |
735 | /* COND_JUMP states. */ |
736 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
737 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
738 | /* dword conditionals adds 5 bytes to frag: | |
739 | 1 extra opcode byte, 4 displacement bytes. */ | |
740 | {0, 0, 5, 0}, | |
fddf5b5b | 741 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
742 | 1 extra opcode byte, 2 displacement bytes. */ |
743 | {0, 0, 3, 0}, | |
744 | ||
745 | /* COND_JUMP86 states. */ | |
746 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
747 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
748 | /* dword conditionals adds 5 bytes to frag: | |
749 | 1 extra opcode byte, 4 displacement bytes. */ | |
750 | {0, 0, 5, 0}, | |
751 | /* word conditionals add 4 bytes to frag: | |
752 | 1 displacement byte and a 3 byte long branch insn. */ | |
753 | {0, 0, 4, 0} | |
252b5132 RH |
754 | }; |
755 | ||
9103f4f4 L |
756 | static const arch_entry cpu_arch[] = |
757 | { | |
89507696 JB |
758 | /* Do not replace the first two entries - i386_target_format() |
759 | relies on them being there in this order. */ | |
8a2c8fef | 760 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 761 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 762 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 763 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 764 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 765 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 766 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 767 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 768 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 769 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 770 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 771 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 772 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 773 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 774 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 775 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 776 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 777 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 778 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 779 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 780 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 781 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 782 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 783 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 784 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 785 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 786 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 787 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 788 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 789 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 790 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 791 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 792 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 793 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 794 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 795 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 796 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 797 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 798 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 799 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 800 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 801 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 802 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 803 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 804 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 805 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 806 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 807 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 808 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 809 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 810 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 811 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 812 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 813 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 814 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 815 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 816 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 817 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 818 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 819 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 820 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 821 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 822 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 823 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 824 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 825 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 826 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 827 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 828 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 829 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 830 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 831 | CPU_ZNVER1_FLAGS, 0 }, |
7b458c12 | 832 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 833 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 834 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 835 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 836 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 837 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 838 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 839 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 840 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 841 | CPU_387_FLAGS, 0 }, |
1848e567 L |
842 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
843 | CPU_687_FLAGS, 0 }, | |
8a2c8fef | 844 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 845 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 846 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 847 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 848 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 849 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 850 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 851 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 852 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 853 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 854 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 855 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 856 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 857 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 858 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 859 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 860 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 861 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 862 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 863 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 864 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 865 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 866 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 867 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 868 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 869 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 870 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 871 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 872 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 873 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 874 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 875 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 876 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 877 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 878 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 879 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 880 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 881 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 882 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 883 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 884 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 885 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 886 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 887 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 888 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 889 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 890 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 891 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 892 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 893 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 894 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 895 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 896 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 897 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 898 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 899 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 900 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 901 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 902 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 903 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 904 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 905 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 906 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 907 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 908 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 909 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 910 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 911 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 912 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 913 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 914 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 915 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 916 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 917 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 918 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 919 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 920 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 921 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 922 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 923 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 924 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 925 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 926 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 927 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 928 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 929 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 930 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 931 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 932 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 933 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 934 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 935 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 936 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 937 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 938 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 939 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 940 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 941 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 942 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 943 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 944 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 945 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 946 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 947 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 948 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 949 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 950 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 951 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 952 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 953 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 954 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 955 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 956 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 957 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 958 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 959 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 960 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 961 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 962 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 963 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 964 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 965 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 966 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 967 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 968 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 969 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 970 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 971 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 972 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 973 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 974 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 975 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 976 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 977 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
978 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
979 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
980 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
981 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
982 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
983 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
984 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
985 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
986 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
987 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
988 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
989 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 990 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 991 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 992 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 993 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 994 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 995 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 996 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 997 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
998 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
999 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1000 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1001 | CPU_IBT_FLAGS, 0 }, | |
1002 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1003 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1004 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1005 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1006 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1007 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1008 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1009 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1010 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1011 | CPU_WBNOINVD_FLAGS, 0 }, | |
293f5f65 L |
1012 | }; |
1013 | ||
1014 | static const noarch_entry cpu_noarch[] = | |
1015 | { | |
1016 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1017 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1018 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1019 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
293f5f65 L |
1020 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1021 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1022 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1023 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1024 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1025 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1026 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1027 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1028 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1029 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1030 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1031 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1032 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1033 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1034 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1035 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1036 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1037 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1038 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1039 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1040 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1041 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1042 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1043 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1044 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1045 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1046 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
e413e4e9 AM |
1047 | }; |
1048 | ||
704209c0 | 1049 | #ifdef I386COFF |
a6c24e68 NC |
1050 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1051 | is allowed to be optional. */ | |
1052 | ||
1053 | static symbolS * | |
1054 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1055 | { | |
1056 | addressT align = 0; | |
1057 | ||
1058 | SKIP_WHITESPACE (); | |
1059 | ||
7ab9ffdd | 1060 | if (needs_align |
a6c24e68 NC |
1061 | && *input_line_pointer == ',') |
1062 | { | |
1063 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1064 | |
a6c24e68 NC |
1065 | if (align == (addressT) -1) |
1066 | return NULL; | |
1067 | } | |
1068 | else | |
1069 | { | |
1070 | if (size >= 8) | |
1071 | align = 3; | |
1072 | else if (size >= 4) | |
1073 | align = 2; | |
1074 | else if (size >= 2) | |
1075 | align = 1; | |
1076 | else | |
1077 | align = 0; | |
1078 | } | |
1079 | ||
1080 | bss_alloc (symbolP, size, align); | |
1081 | return symbolP; | |
1082 | } | |
1083 | ||
704209c0 | 1084 | static void |
a6c24e68 NC |
1085 | pe_lcomm (int needs_align) |
1086 | { | |
1087 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1088 | } | |
704209c0 | 1089 | #endif |
a6c24e68 | 1090 | |
29b0f896 AM |
1091 | const pseudo_typeS md_pseudo_table[] = |
1092 | { | |
1093 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1094 | {"align", s_align_bytes, 0}, | |
1095 | #else | |
1096 | {"align", s_align_ptwo, 0}, | |
1097 | #endif | |
1098 | {"arch", set_cpu_arch, 0}, | |
1099 | #ifndef I386COFF | |
1100 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1101 | #else |
1102 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1103 | #endif |
1104 | {"ffloat", float_cons, 'f'}, | |
1105 | {"dfloat", float_cons, 'd'}, | |
1106 | {"tfloat", float_cons, 'x'}, | |
1107 | {"value", cons, 2}, | |
d182319b | 1108 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1109 | {"noopt", s_ignore, 0}, |
1110 | {"optim", s_ignore, 0}, | |
1111 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1112 | {"code16", set_code_flag, CODE_16BIT}, | |
1113 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1114 | #ifdef BFD64 |
29b0f896 | 1115 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1116 | #endif |
29b0f896 AM |
1117 | {"intel_syntax", set_intel_syntax, 1}, |
1118 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1119 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1120 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1121 | {"allow_index_reg", set_allow_index_reg, 1}, |
1122 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1123 | {"sse_check", set_check, 0}, |
1124 | {"operand_check", set_check, 1}, | |
3b22753a L |
1125 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1126 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1127 | #else |
e3bb37b5 | 1128 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
1129 | {"loc", dwarf2_directive_loc, 0}, |
1130 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1131 | #endif |
6482c264 NC |
1132 | #ifdef TE_PE |
1133 | {"secrel32", pe_directive_secrel, 0}, | |
1134 | #endif | |
29b0f896 AM |
1135 | {0, 0, 0} |
1136 | }; | |
1137 | ||
1138 | /* For interface with expression (). */ | |
1139 | extern char *input_line_pointer; | |
1140 | ||
1141 | /* Hash table for instruction mnemonic lookup. */ | |
1142 | static struct hash_control *op_hash; | |
1143 | ||
1144 | /* Hash table for register lookup. */ | |
1145 | static struct hash_control *reg_hash; | |
1146 | \f | |
252b5132 | 1147 | void |
e3bb37b5 | 1148 | i386_align_code (fragS *fragP, int count) |
252b5132 | 1149 | { |
ce8a8b2f AM |
1150 | /* Various efficient no-op patterns for aligning code labels. |
1151 | Note: Don't try to assemble the instructions in the comments. | |
1152 | 0L and 0w are not legal. */ | |
bad6e36d | 1153 | static const unsigned char f32_1[] = |
252b5132 | 1154 | {0x90}; /* nop */ |
bad6e36d | 1155 | static const unsigned char f32_2[] = |
ccc9c027 | 1156 | {0x66,0x90}; /* xchg %ax,%ax */ |
bad6e36d | 1157 | static const unsigned char f32_3[] = |
252b5132 | 1158 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ |
bad6e36d | 1159 | static const unsigned char f32_4[] = |
252b5132 | 1160 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
bad6e36d | 1161 | static const unsigned char f32_5[] = |
252b5132 RH |
1162 | {0x90, /* nop */ |
1163 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
bad6e36d | 1164 | static const unsigned char f32_6[] = |
252b5132 | 1165 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ |
bad6e36d | 1166 | static const unsigned char f32_7[] = |
252b5132 | 1167 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
bad6e36d | 1168 | static const unsigned char f32_8[] = |
252b5132 RH |
1169 | {0x90, /* nop */ |
1170 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
bad6e36d | 1171 | static const unsigned char f32_9[] = |
252b5132 RH |
1172 | {0x89,0xf6, /* movl %esi,%esi */ |
1173 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1174 | static const unsigned char f32_10[] = |
252b5132 RH |
1175 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ |
1176 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1177 | static const unsigned char f32_11[] = |
252b5132 RH |
1178 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ |
1179 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1180 | static const unsigned char f32_12[] = |
252b5132 RH |
1181 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
1182 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
bad6e36d | 1183 | static const unsigned char f32_13[] = |
252b5132 RH |
1184 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
1185 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1186 | static const unsigned char f32_14[] = |
252b5132 RH |
1187 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ |
1188 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1189 | static const unsigned char f16_3[] = |
c3332e24 | 1190 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ |
bad6e36d | 1191 | static const unsigned char f16_4[] = |
252b5132 | 1192 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
bad6e36d | 1193 | static const unsigned char f16_5[] = |
252b5132 RH |
1194 | {0x90, /* nop */ |
1195 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
bad6e36d | 1196 | static const unsigned char f16_6[] = |
252b5132 RH |
1197 | {0x89,0xf6, /* mov %si,%si */ |
1198 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1199 | static const unsigned char f16_7[] = |
252b5132 RH |
1200 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
1201 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1202 | static const unsigned char f16_8[] = |
252b5132 RH |
1203 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
1204 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1205 | static const unsigned char jump_31[] = |
76bc74dc L |
1206 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ |
1207 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
1208 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
1209 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
bad6e36d | 1210 | static const unsigned char *const f32_patt[] = { |
252b5132 | 1211 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, |
76bc74dc | 1212 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 | 1213 | }; |
bad6e36d | 1214 | static const unsigned char *const f16_patt[] = { |
76bc74dc | 1215 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 1216 | }; |
ccc9c027 | 1217 | /* nopl (%[re]ax) */ |
bad6e36d | 1218 | static const unsigned char alt_3[] = |
ccc9c027 L |
1219 | {0x0f,0x1f,0x00}; |
1220 | /* nopl 0(%[re]ax) */ | |
bad6e36d | 1221 | static const unsigned char alt_4[] = |
ccc9c027 L |
1222 | {0x0f,0x1f,0x40,0x00}; |
1223 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1224 | static const unsigned char alt_5[] = |
ccc9c027 L |
1225 | {0x0f,0x1f,0x44,0x00,0x00}; |
1226 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1227 | static const unsigned char alt_6[] = |
ccc9c027 L |
1228 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; |
1229 | /* nopl 0L(%[re]ax) */ | |
bad6e36d | 1230 | static const unsigned char alt_7[] = |
ccc9c027 L |
1231 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; |
1232 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1233 | static const unsigned char alt_8[] = |
ccc9c027 L |
1234 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
1235 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1236 | static const unsigned char alt_9[] = |
ccc9c027 L |
1237 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
1238 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1239 | static const unsigned char alt_10[] = |
ccc9c027 | 1240 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
bad6e36d | 1241 | static const unsigned char *const alt_patt[] = { |
ccc9c027 | 1242 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, |
80b8656c | 1243 | alt_9, alt_10 |
ccc9c027 | 1244 | }; |
252b5132 | 1245 | |
76bc74dc L |
1246 | /* Only align for at least a positive non-zero boundary. */ |
1247 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 1248 | return; |
3e73aa7c | 1249 | |
ccc9c027 L |
1250 | /* We need to decide which NOP sequence to use for 32bit and |
1251 | 64bit. When -mtune= is used: | |
4eed87de | 1252 | |
76bc74dc L |
1253 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1254 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1255 | 2. For the rest, alt_patt will be used. |
1256 | ||
1257 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1258 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1259 | be used. |
ccc9c027 L |
1260 | |
1261 | When -march= or .arch is used, we can't use anything beyond | |
1262 | cpu_arch_isa_flags. */ | |
1263 | ||
1264 | if (flag_code == CODE_16BIT) | |
1265 | { | |
ccc9c027 | 1266 | if (count > 8) |
33fef721 | 1267 | { |
76bc74dc L |
1268 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1269 | jump_31, count); | |
1270 | /* Adjust jump offset. */ | |
1271 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 1272 | } |
76bc74dc L |
1273 | else |
1274 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1275 | f16_patt[count - 1], count); | |
252b5132 | 1276 | } |
33fef721 | 1277 | else |
ccc9c027 | 1278 | { |
bad6e36d | 1279 | const unsigned char *const *patt = NULL; |
ccc9c027 | 1280 | |
fbf3f584 | 1281 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1282 | { |
1283 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1284 | switch (cpu_arch_tune) | |
1285 | { | |
1286 | case PROCESSOR_UNKNOWN: | |
1287 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1288 | optimize with nops. */ |
1289 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1290 | patt = alt_patt; |
ccc9c027 L |
1291 | else |
1292 | patt = f32_patt; | |
1293 | break; | |
ccc9c027 L |
1294 | case PROCESSOR_PENTIUM4: |
1295 | case PROCESSOR_NOCONA: | |
ef05d495 | 1296 | case PROCESSOR_CORE: |
76bc74dc | 1297 | case PROCESSOR_CORE2: |
bd5295b2 | 1298 | case PROCESSOR_COREI7: |
3632d14b | 1299 | case PROCESSOR_L1OM: |
7a9068fe | 1300 | case PROCESSOR_K1OM: |
76bc74dc | 1301 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1302 | case PROCESSOR_K6: |
1303 | case PROCESSOR_ATHLON: | |
1304 | case PROCESSOR_K8: | |
4eed87de | 1305 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1306 | case PROCESSOR_BD: |
029f3522 | 1307 | case PROCESSOR_ZNVER: |
7b458c12 | 1308 | case PROCESSOR_BT: |
80b8656c | 1309 | patt = alt_patt; |
ccc9c027 | 1310 | break; |
76bc74dc | 1311 | case PROCESSOR_I386: |
ccc9c027 L |
1312 | case PROCESSOR_I486: |
1313 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1314 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1315 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1316 | case PROCESSOR_GENERIC32: |
1317 | patt = f32_patt; | |
1318 | break; | |
4eed87de | 1319 | } |
ccc9c027 L |
1320 | } |
1321 | else | |
1322 | { | |
fbf3f584 | 1323 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1324 | { |
1325 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1326 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1327 | PROCESSOR_UNKNOWN. */ |
1328 | abort (); | |
1329 | break; | |
1330 | ||
76bc74dc | 1331 | case PROCESSOR_I386: |
ccc9c027 L |
1332 | case PROCESSOR_I486: |
1333 | case PROCESSOR_PENTIUM: | |
81486035 | 1334 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1335 | case PROCESSOR_K6: |
1336 | case PROCESSOR_ATHLON: | |
1337 | case PROCESSOR_K8: | |
4eed87de | 1338 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1339 | case PROCESSOR_BD: |
029f3522 | 1340 | case PROCESSOR_ZNVER: |
7b458c12 | 1341 | case PROCESSOR_BT: |
ccc9c027 L |
1342 | case PROCESSOR_GENERIC32: |
1343 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1344 | with nops. */ |
1345 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1346 | patt = alt_patt; |
ccc9c027 L |
1347 | else |
1348 | patt = f32_patt; | |
1349 | break; | |
76bc74dc L |
1350 | case PROCESSOR_PENTIUMPRO: |
1351 | case PROCESSOR_PENTIUM4: | |
1352 | case PROCESSOR_NOCONA: | |
1353 | case PROCESSOR_CORE: | |
ef05d495 | 1354 | case PROCESSOR_CORE2: |
bd5295b2 | 1355 | case PROCESSOR_COREI7: |
3632d14b | 1356 | case PROCESSOR_L1OM: |
7a9068fe | 1357 | case PROCESSOR_K1OM: |
22109423 | 1358 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1359 | patt = alt_patt; |
ccc9c027 L |
1360 | else |
1361 | patt = f32_patt; | |
1362 | break; | |
1363 | case PROCESSOR_GENERIC64: | |
80b8656c | 1364 | patt = alt_patt; |
ccc9c027 | 1365 | break; |
4eed87de | 1366 | } |
ccc9c027 L |
1367 | } |
1368 | ||
76bc74dc L |
1369 | if (patt == f32_patt) |
1370 | { | |
1371 | /* If the padding is less than 15 bytes, we use the normal | |
1372 | ones. Otherwise, we use a jump instruction and adjust | |
711eedef L |
1373 | its offset. */ |
1374 | int limit; | |
76ba9986 | 1375 | |
711eedef L |
1376 | /* For 64bit, the limit is 3 bytes. */ |
1377 | if (flag_code == CODE_64BIT | |
1378 | && fragP->tc_frag_data.isa_flags.bitfield.cpulm) | |
1379 | limit = 3; | |
1380 | else | |
1381 | limit = 15; | |
1382 | if (count < limit) | |
76bc74dc L |
1383 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1384 | patt[count - 1], count); | |
1385 | else | |
1386 | { | |
1387 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1388 | jump_31, count); | |
1389 | /* Adjust jump offset. */ | |
1390 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1391 | } | |
1392 | } | |
1393 | else | |
1394 | { | |
80b8656c L |
1395 | /* Maximum length of an instruction is 10 byte. If the |
1396 | padding is greater than 10 bytes and we don't use jump, | |
76bc74dc L |
1397 | we have to break it into smaller pieces. */ |
1398 | int padding = count; | |
80b8656c | 1399 | while (padding > 10) |
76bc74dc | 1400 | { |
80b8656c | 1401 | padding -= 10; |
76bc74dc | 1402 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, |
80b8656c | 1403 | patt [9], 10); |
76bc74dc L |
1404 | } |
1405 | ||
1406 | if (padding) | |
1407 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1408 | patt [padding - 1], padding); | |
1409 | } | |
ccc9c027 | 1410 | } |
33fef721 | 1411 | fragP->fr_var = count; |
252b5132 RH |
1412 | } |
1413 | ||
c6fb90c8 | 1414 | static INLINE int |
0dfbf9d7 | 1415 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1416 | { |
0dfbf9d7 | 1417 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1418 | { |
1419 | case 3: | |
0dfbf9d7 | 1420 | if (x->array[2]) |
c6fb90c8 | 1421 | return 0; |
1a0670f3 | 1422 | /* Fall through. */ |
c6fb90c8 | 1423 | case 2: |
0dfbf9d7 | 1424 | if (x->array[1]) |
c6fb90c8 | 1425 | return 0; |
1a0670f3 | 1426 | /* Fall through. */ |
c6fb90c8 | 1427 | case 1: |
0dfbf9d7 | 1428 | return !x->array[0]; |
c6fb90c8 L |
1429 | default: |
1430 | abort (); | |
1431 | } | |
40fb9820 L |
1432 | } |
1433 | ||
c6fb90c8 | 1434 | static INLINE void |
0dfbf9d7 | 1435 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1436 | { |
0dfbf9d7 | 1437 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1438 | { |
1439 | case 3: | |
0dfbf9d7 | 1440 | x->array[2] = v; |
1a0670f3 | 1441 | /* Fall through. */ |
c6fb90c8 | 1442 | case 2: |
0dfbf9d7 | 1443 | x->array[1] = v; |
1a0670f3 | 1444 | /* Fall through. */ |
c6fb90c8 | 1445 | case 1: |
0dfbf9d7 | 1446 | x->array[0] = v; |
1a0670f3 | 1447 | /* Fall through. */ |
c6fb90c8 L |
1448 | break; |
1449 | default: | |
1450 | abort (); | |
1451 | } | |
1452 | } | |
40fb9820 | 1453 | |
c6fb90c8 | 1454 | static INLINE int |
0dfbf9d7 L |
1455 | operand_type_equal (const union i386_operand_type *x, |
1456 | const union i386_operand_type *y) | |
c6fb90c8 | 1457 | { |
0dfbf9d7 | 1458 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1459 | { |
1460 | case 3: | |
0dfbf9d7 | 1461 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1462 | return 0; |
1a0670f3 | 1463 | /* Fall through. */ |
c6fb90c8 | 1464 | case 2: |
0dfbf9d7 | 1465 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1466 | return 0; |
1a0670f3 | 1467 | /* Fall through. */ |
c6fb90c8 | 1468 | case 1: |
0dfbf9d7 | 1469 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1470 | break; |
1471 | default: | |
1472 | abort (); | |
1473 | } | |
1474 | } | |
40fb9820 | 1475 | |
0dfbf9d7 L |
1476 | static INLINE int |
1477 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1478 | { | |
1479 | switch (ARRAY_SIZE(x->array)) | |
1480 | { | |
53467f57 IT |
1481 | case 4: |
1482 | if (x->array[3]) | |
1483 | return 0; | |
1484 | /* Fall through. */ | |
0dfbf9d7 L |
1485 | case 3: |
1486 | if (x->array[2]) | |
1487 | return 0; | |
1a0670f3 | 1488 | /* Fall through. */ |
0dfbf9d7 L |
1489 | case 2: |
1490 | if (x->array[1]) | |
1491 | return 0; | |
1a0670f3 | 1492 | /* Fall through. */ |
0dfbf9d7 L |
1493 | case 1: |
1494 | return !x->array[0]; | |
1495 | default: | |
1496 | abort (); | |
1497 | } | |
1498 | } | |
1499 | ||
0dfbf9d7 L |
1500 | static INLINE int |
1501 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1502 | const union i386_cpu_flags *y) | |
1503 | { | |
1504 | switch (ARRAY_SIZE(x->array)) | |
1505 | { | |
53467f57 IT |
1506 | case 4: |
1507 | if (x->array[3] != y->array[3]) | |
1508 | return 0; | |
1509 | /* Fall through. */ | |
0dfbf9d7 L |
1510 | case 3: |
1511 | if (x->array[2] != y->array[2]) | |
1512 | return 0; | |
1a0670f3 | 1513 | /* Fall through. */ |
0dfbf9d7 L |
1514 | case 2: |
1515 | if (x->array[1] != y->array[1]) | |
1516 | return 0; | |
1a0670f3 | 1517 | /* Fall through. */ |
0dfbf9d7 L |
1518 | case 1: |
1519 | return x->array[0] == y->array[0]; | |
1520 | break; | |
1521 | default: | |
1522 | abort (); | |
1523 | } | |
1524 | } | |
c6fb90c8 L |
1525 | |
1526 | static INLINE int | |
1527 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1528 | { | |
1529 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1530 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1531 | } |
1532 | ||
c6fb90c8 L |
1533 | static INLINE i386_cpu_flags |
1534 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1535 | { |
c6fb90c8 L |
1536 | switch (ARRAY_SIZE (x.array)) |
1537 | { | |
53467f57 IT |
1538 | case 4: |
1539 | x.array [3] &= y.array [3]; | |
1540 | /* Fall through. */ | |
c6fb90c8 L |
1541 | case 3: |
1542 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1543 | /* Fall through. */ |
c6fb90c8 L |
1544 | case 2: |
1545 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1546 | /* Fall through. */ |
c6fb90c8 L |
1547 | case 1: |
1548 | x.array [0] &= y.array [0]; | |
1549 | break; | |
1550 | default: | |
1551 | abort (); | |
1552 | } | |
1553 | return x; | |
1554 | } | |
40fb9820 | 1555 | |
c6fb90c8 L |
1556 | static INLINE i386_cpu_flags |
1557 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1558 | { |
c6fb90c8 | 1559 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1560 | { |
53467f57 IT |
1561 | case 4: |
1562 | x.array [3] |= y.array [3]; | |
1563 | /* Fall through. */ | |
c6fb90c8 L |
1564 | case 3: |
1565 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1566 | /* Fall through. */ |
c6fb90c8 L |
1567 | case 2: |
1568 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1569 | /* Fall through. */ |
c6fb90c8 L |
1570 | case 1: |
1571 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1572 | break; |
1573 | default: | |
1574 | abort (); | |
1575 | } | |
40fb9820 L |
1576 | return x; |
1577 | } | |
1578 | ||
309d3373 JB |
1579 | static INLINE i386_cpu_flags |
1580 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1581 | { | |
1582 | switch (ARRAY_SIZE (x.array)) | |
1583 | { | |
53467f57 IT |
1584 | case 4: |
1585 | x.array [3] &= ~y.array [3]; | |
1586 | /* Fall through. */ | |
309d3373 JB |
1587 | case 3: |
1588 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1589 | /* Fall through. */ |
309d3373 JB |
1590 | case 2: |
1591 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1592 | /* Fall through. */ |
309d3373 JB |
1593 | case 1: |
1594 | x.array [0] &= ~y.array [0]; | |
1595 | break; | |
1596 | default: | |
1597 | abort (); | |
1598 | } | |
1599 | return x; | |
1600 | } | |
1601 | ||
c0f3af97 L |
1602 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1603 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1604 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1605 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1606 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1607 | |
a5ff0eb2 | 1608 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1609 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1610 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1611 | #define CPU_FLAGS_PERFECT_MATCH \ |
1612 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1613 | ||
1614 | /* Return CPU flags match bits. */ | |
3629bb00 | 1615 | |
40fb9820 | 1616 | static int |
d3ce72d0 | 1617 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1618 | { |
c0f3af97 L |
1619 | i386_cpu_flags x = t->cpu_flags; |
1620 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1621 | |
1622 | x.bitfield.cpu64 = 0; | |
1623 | x.bitfield.cpuno64 = 0; | |
1624 | ||
0dfbf9d7 | 1625 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1626 | { |
1627 | /* This instruction is available on all archs. */ | |
1628 | match |= CPU_FLAGS_32BIT_MATCH; | |
1629 | } | |
3629bb00 L |
1630 | else |
1631 | { | |
c0f3af97 | 1632 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1633 | i386_cpu_flags cpu = cpu_arch_flags; |
1634 | ||
3629bb00 | 1635 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1636 | if (!cpu_flags_all_zero (&cpu)) |
1637 | { | |
a5ff0eb2 L |
1638 | if (x.bitfield.cpuavx) |
1639 | { | |
ce2f5b3c | 1640 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1641 | if (cpu.bitfield.cpuavx) |
1642 | { | |
1643 | /* Check SSE2AVX. */ | |
1644 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1645 | { | |
1646 | match |= (CPU_FLAGS_ARCH_MATCH | |
1647 | | CPU_FLAGS_AVX_MATCH); | |
1648 | /* Check AES. */ | |
1649 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1650 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1651 | /* Check PCLMUL. */ |
1652 | if (!x.bitfield.cpupclmul | |
1653 | || cpu.bitfield.cpupclmul) | |
1654 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1655 | } |
1656 | } | |
1657 | else | |
1658 | match |= CPU_FLAGS_ARCH_MATCH; | |
1659 | } | |
73b090a9 L |
1660 | else if (x.bitfield.cpuavx512vl) |
1661 | { | |
1662 | /* Match AVX512VL. */ | |
1663 | if (cpu.bitfield.cpuavx512vl) | |
1664 | { | |
1665 | /* Need another match. */ | |
1666 | cpu.bitfield.cpuavx512vl = 0; | |
1667 | if (!cpu_flags_all_zero (&cpu)) | |
1668 | match |= CPU_FLAGS_32BIT_MATCH; | |
1669 | else | |
1670 | match |= CPU_FLAGS_ARCH_MATCH; | |
1671 | } | |
1672 | else | |
1673 | match |= CPU_FLAGS_ARCH_MATCH; | |
1674 | } | |
a5ff0eb2 | 1675 | else |
c0f3af97 L |
1676 | match |= CPU_FLAGS_32BIT_MATCH; |
1677 | } | |
3629bb00 | 1678 | } |
c0f3af97 | 1679 | return match; |
40fb9820 L |
1680 | } |
1681 | ||
c6fb90c8 L |
1682 | static INLINE i386_operand_type |
1683 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1684 | { |
c6fb90c8 L |
1685 | switch (ARRAY_SIZE (x.array)) |
1686 | { | |
1687 | case 3: | |
1688 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1689 | /* Fall through. */ |
c6fb90c8 L |
1690 | case 2: |
1691 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1692 | /* Fall through. */ |
c6fb90c8 L |
1693 | case 1: |
1694 | x.array [0] &= y.array [0]; | |
1695 | break; | |
1696 | default: | |
1697 | abort (); | |
1698 | } | |
1699 | return x; | |
40fb9820 L |
1700 | } |
1701 | ||
c6fb90c8 L |
1702 | static INLINE i386_operand_type |
1703 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1704 | { |
c6fb90c8 | 1705 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1706 | { |
c6fb90c8 L |
1707 | case 3: |
1708 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1709 | /* Fall through. */ |
c6fb90c8 L |
1710 | case 2: |
1711 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1712 | /* Fall through. */ |
c6fb90c8 L |
1713 | case 1: |
1714 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1715 | break; |
1716 | default: | |
1717 | abort (); | |
1718 | } | |
c6fb90c8 L |
1719 | return x; |
1720 | } | |
40fb9820 | 1721 | |
c6fb90c8 L |
1722 | static INLINE i386_operand_type |
1723 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1724 | { | |
1725 | switch (ARRAY_SIZE (x.array)) | |
1726 | { | |
1727 | case 3: | |
1728 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1729 | /* Fall through. */ |
c6fb90c8 L |
1730 | case 2: |
1731 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1732 | /* Fall through. */ |
c6fb90c8 L |
1733 | case 1: |
1734 | x.array [0] ^= y.array [0]; | |
1735 | break; | |
1736 | default: | |
1737 | abort (); | |
1738 | } | |
40fb9820 L |
1739 | return x; |
1740 | } | |
1741 | ||
1742 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1743 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1744 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1745 | static const i386_operand_type inoutportreg |
1746 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1747 | static const i386_operand_type reg16_inoutportreg |
1748 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1749 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1750 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1751 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1752 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1753 | static const i386_operand_type anydisp | |
1754 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1755 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1756 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1757 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1758 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1759 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1760 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1761 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1762 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1763 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1764 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1765 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1766 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1767 | |
1768 | enum operand_type | |
1769 | { | |
1770 | reg, | |
40fb9820 L |
1771 | imm, |
1772 | disp, | |
1773 | anymem | |
1774 | }; | |
1775 | ||
c6fb90c8 | 1776 | static INLINE int |
40fb9820 L |
1777 | operand_type_check (i386_operand_type t, enum operand_type c) |
1778 | { | |
1779 | switch (c) | |
1780 | { | |
1781 | case reg: | |
dc821c5f | 1782 | return t.bitfield.reg; |
40fb9820 | 1783 | |
40fb9820 L |
1784 | case imm: |
1785 | return (t.bitfield.imm8 | |
1786 | || t.bitfield.imm8s | |
1787 | || t.bitfield.imm16 | |
1788 | || t.bitfield.imm32 | |
1789 | || t.bitfield.imm32s | |
1790 | || t.bitfield.imm64); | |
1791 | ||
1792 | case disp: | |
1793 | return (t.bitfield.disp8 | |
1794 | || t.bitfield.disp16 | |
1795 | || t.bitfield.disp32 | |
1796 | || t.bitfield.disp32s | |
1797 | || t.bitfield.disp64); | |
1798 | ||
1799 | case anymem: | |
1800 | return (t.bitfield.disp8 | |
1801 | || t.bitfield.disp16 | |
1802 | || t.bitfield.disp32 | |
1803 | || t.bitfield.disp32s | |
1804 | || t.bitfield.disp64 | |
1805 | || t.bitfield.baseindex); | |
1806 | ||
1807 | default: | |
1808 | abort (); | |
1809 | } | |
2cfe26b6 AM |
1810 | |
1811 | return 0; | |
40fb9820 L |
1812 | } |
1813 | ||
ca0d63fe | 1814 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on |
5c07affc L |
1815 | operand J for instruction template T. */ |
1816 | ||
1817 | static INLINE int | |
d3ce72d0 | 1818 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1819 | { |
1820 | return !((i.types[j].bitfield.byte | |
1821 | && !t->operand_types[j].bitfield.byte) | |
1822 | || (i.types[j].bitfield.word | |
1823 | && !t->operand_types[j].bitfield.word) | |
1824 | || (i.types[j].bitfield.dword | |
1825 | && !t->operand_types[j].bitfield.dword) | |
1826 | || (i.types[j].bitfield.qword | |
ca0d63fe JB |
1827 | && !t->operand_types[j].bitfield.qword) |
1828 | || (i.types[j].bitfield.tbyte | |
1829 | && !t->operand_types[j].bitfield.tbyte)); | |
5c07affc L |
1830 | } |
1831 | ||
1b54b8d7 JB |
1832 | /* Return 1 if there is no conflict in SIMD register on |
1833 | operand J for instruction template T. */ | |
1834 | ||
1835 | static INLINE int | |
1836 | match_simd_size (const insn_template *t, unsigned int j) | |
1837 | { | |
1838 | return !((i.types[j].bitfield.xmmword | |
1839 | && !t->operand_types[j].bitfield.xmmword) | |
1840 | || (i.types[j].bitfield.ymmword | |
1841 | && !t->operand_types[j].bitfield.ymmword) | |
1842 | || (i.types[j].bitfield.zmmword | |
1843 | && !t->operand_types[j].bitfield.zmmword)); | |
1844 | } | |
1845 | ||
5c07affc L |
1846 | /* Return 1 if there is no conflict in any size on operand J for |
1847 | instruction template T. */ | |
1848 | ||
1849 | static INLINE int | |
d3ce72d0 | 1850 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1851 | { |
1852 | return (match_reg_size (t, j) | |
1853 | && !((i.types[j].bitfield.unspecified | |
af508cb9 | 1854 | && !i.broadcast |
5c07affc L |
1855 | && !t->operand_types[j].bitfield.unspecified) |
1856 | || (i.types[j].bitfield.fword | |
1857 | && !t->operand_types[j].bitfield.fword) | |
1b54b8d7 JB |
1858 | /* For scalar opcode templates to allow register and memory |
1859 | operands at the same time, some special casing is needed | |
1860 | here. */ | |
1861 | || ((t->operand_types[j].bitfield.regsimd | |
1862 | && !t->opcode_modifier.broadcast | |
1863 | && (t->operand_types[j].bitfield.dword | |
1864 | || t->operand_types[j].bitfield.qword)) | |
1865 | ? (i.types[j].bitfield.xmmword | |
1866 | || i.types[j].bitfield.ymmword | |
1867 | || i.types[j].bitfield.zmmword) | |
1868 | : !match_simd_size(t, j)))); | |
5c07affc L |
1869 | } |
1870 | ||
1871 | /* Return 1 if there is no size conflict on any operands for | |
1872 | instruction template T. */ | |
1873 | ||
1874 | static INLINE int | |
d3ce72d0 | 1875 | operand_size_match (const insn_template *t) |
5c07affc L |
1876 | { |
1877 | unsigned int j; | |
1878 | int match = 1; | |
1879 | ||
1880 | /* Don't check jump instructions. */ | |
1881 | if (t->opcode_modifier.jump | |
1882 | || t->opcode_modifier.jumpbyte | |
1883 | || t->opcode_modifier.jumpdword | |
1884 | || t->opcode_modifier.jumpintersegment) | |
1885 | return match; | |
1886 | ||
1887 | /* Check memory and accumulator operand size. */ | |
1888 | for (j = 0; j < i.operands; j++) | |
1889 | { | |
1b54b8d7 JB |
1890 | if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd |
1891 | && t->operand_types[j].bitfield.anysize) | |
5c07affc L |
1892 | continue; |
1893 | ||
1b54b8d7 | 1894 | if (t->operand_types[j].bitfield.reg |
dc821c5f | 1895 | && !match_reg_size (t, j)) |
5c07affc L |
1896 | { |
1897 | match = 0; | |
1898 | break; | |
1899 | } | |
1900 | ||
1b54b8d7 JB |
1901 | if (t->operand_types[j].bitfield.regsimd |
1902 | && !match_simd_size (t, j)) | |
1903 | { | |
1904 | match = 0; | |
1905 | break; | |
1906 | } | |
1907 | ||
1908 | if (t->operand_types[j].bitfield.acc | |
1909 | && (!match_reg_size (t, j) || !match_simd_size (t, j))) | |
1910 | { | |
1911 | match = 0; | |
1912 | break; | |
1913 | } | |
1914 | ||
5c07affc L |
1915 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) |
1916 | { | |
1917 | match = 0; | |
1918 | break; | |
1919 | } | |
1920 | } | |
1921 | ||
891edac4 | 1922 | if (match) |
5c07affc | 1923 | return match; |
891edac4 L |
1924 | else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
1925 | { | |
1926 | mismatch: | |
86e026a4 | 1927 | i.error = operand_size_mismatch; |
891edac4 L |
1928 | return 0; |
1929 | } | |
5c07affc L |
1930 | |
1931 | /* Check reverse. */ | |
9c2799c2 | 1932 | gas_assert (i.operands == 2); |
5c07affc L |
1933 | |
1934 | match = 1; | |
1935 | for (j = 0; j < 2; j++) | |
1936 | { | |
dc821c5f JB |
1937 | if ((t->operand_types[j].bitfield.reg |
1938 | || t->operand_types[j].bitfield.acc) | |
5c07affc | 1939 | && !match_reg_size (t, j ? 0 : 1)) |
891edac4 | 1940 | goto mismatch; |
5c07affc L |
1941 | |
1942 | if (i.types[j].bitfield.mem | |
1943 | && !match_mem_size (t, j ? 0 : 1)) | |
891edac4 | 1944 | goto mismatch; |
5c07affc L |
1945 | } |
1946 | ||
1947 | return match; | |
1948 | } | |
1949 | ||
c6fb90c8 | 1950 | static INLINE int |
40fb9820 L |
1951 | operand_type_match (i386_operand_type overlap, |
1952 | i386_operand_type given) | |
1953 | { | |
1954 | i386_operand_type temp = overlap; | |
1955 | ||
1956 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1957 | temp.bitfield.unspecified = 0; |
5c07affc L |
1958 | temp.bitfield.byte = 0; |
1959 | temp.bitfield.word = 0; | |
1960 | temp.bitfield.dword = 0; | |
1961 | temp.bitfield.fword = 0; | |
1962 | temp.bitfield.qword = 0; | |
1963 | temp.bitfield.tbyte = 0; | |
1964 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1965 | temp.bitfield.ymmword = 0; |
43234a1e | 1966 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 1967 | if (operand_type_all_zero (&temp)) |
891edac4 | 1968 | goto mismatch; |
40fb9820 | 1969 | |
891edac4 L |
1970 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
1971 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
1972 | return 1; | |
1973 | ||
1974 | mismatch: | |
a65babc9 | 1975 | i.error = operand_type_mismatch; |
891edac4 | 1976 | return 0; |
40fb9820 L |
1977 | } |
1978 | ||
7d5e4556 | 1979 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
1980 | unless the expected operand type register overlap is null. |
1981 | Memory operand size of certain SIMD instructions is also being checked | |
1982 | here. */ | |
40fb9820 | 1983 | |
c6fb90c8 | 1984 | static INLINE int |
dc821c5f | 1985 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 1986 | i386_operand_type t0, |
40fb9820 L |
1987 | i386_operand_type g1, |
1988 | i386_operand_type t1) | |
1989 | { | |
10c17abd JB |
1990 | if (!g0.bitfield.reg |
1991 | && !g0.bitfield.regsimd | |
1992 | && (!operand_type_check (g0, anymem) | |
1993 | || g0.bitfield.unspecified | |
1994 | || !t0.bitfield.regsimd)) | |
40fb9820 L |
1995 | return 1; |
1996 | ||
10c17abd JB |
1997 | if (!g1.bitfield.reg |
1998 | && !g1.bitfield.regsimd | |
1999 | && (!operand_type_check (g1, anymem) | |
2000 | || g1.bitfield.unspecified | |
2001 | || !t1.bitfield.regsimd)) | |
40fb9820 L |
2002 | return 1; |
2003 | ||
dc821c5f JB |
2004 | if (g0.bitfield.byte == g1.bitfield.byte |
2005 | && g0.bitfield.word == g1.bitfield.word | |
2006 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2007 | && g0.bitfield.qword == g1.bitfield.qword |
2008 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2009 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2010 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2011 | return 1; |
2012 | ||
dc821c5f JB |
2013 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2014 | && !(t0.bitfield.word & t1.bitfield.word) | |
2015 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2016 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2017 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2018 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2019 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2020 | return 1; |
2021 | ||
a65babc9 | 2022 | i.error = register_type_mismatch; |
891edac4 L |
2023 | |
2024 | return 0; | |
40fb9820 L |
2025 | } |
2026 | ||
4c692bc7 JB |
2027 | static INLINE unsigned int |
2028 | register_number (const reg_entry *r) | |
2029 | { | |
2030 | unsigned int nr = r->reg_num; | |
2031 | ||
2032 | if (r->reg_flags & RegRex) | |
2033 | nr += 8; | |
2034 | ||
200cbe0f L |
2035 | if (r->reg_flags & RegVRex) |
2036 | nr += 16; | |
2037 | ||
4c692bc7 JB |
2038 | return nr; |
2039 | } | |
2040 | ||
252b5132 | 2041 | static INLINE unsigned int |
40fb9820 | 2042 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2043 | { |
b5014f7a | 2044 | if (t.bitfield.disp8) |
40fb9820 L |
2045 | return 1; |
2046 | else if (t.bitfield.disp16 | |
2047 | || t.bitfield.disp32 | |
2048 | || t.bitfield.disp32s) | |
2049 | return 2; | |
2050 | else | |
2051 | return 0; | |
252b5132 RH |
2052 | } |
2053 | ||
2054 | static INLINE int | |
65879393 | 2055 | fits_in_signed_byte (addressT num) |
252b5132 | 2056 | { |
65879393 | 2057 | return num + 0x80 <= 0xff; |
47926f60 | 2058 | } |
252b5132 RH |
2059 | |
2060 | static INLINE int | |
65879393 | 2061 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2062 | { |
65879393 | 2063 | return num <= 0xff; |
47926f60 | 2064 | } |
252b5132 RH |
2065 | |
2066 | static INLINE int | |
65879393 | 2067 | fits_in_unsigned_word (addressT num) |
252b5132 | 2068 | { |
65879393 | 2069 | return num <= 0xffff; |
47926f60 | 2070 | } |
252b5132 RH |
2071 | |
2072 | static INLINE int | |
65879393 | 2073 | fits_in_signed_word (addressT num) |
252b5132 | 2074 | { |
65879393 | 2075 | return num + 0x8000 <= 0xffff; |
47926f60 | 2076 | } |
2a962e6d | 2077 | |
3e73aa7c | 2078 | static INLINE int |
65879393 | 2079 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2080 | { |
2081 | #ifndef BFD64 | |
2082 | return 1; | |
2083 | #else | |
65879393 | 2084 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2085 | #endif |
2086 | } /* fits_in_signed_long() */ | |
2a962e6d | 2087 | |
3e73aa7c | 2088 | static INLINE int |
65879393 | 2089 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2090 | { |
2091 | #ifndef BFD64 | |
2092 | return 1; | |
2093 | #else | |
65879393 | 2094 | return num <= 0xffffffff; |
3e73aa7c JH |
2095 | #endif |
2096 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2097 | |
43234a1e | 2098 | static INLINE int |
b5014f7a | 2099 | fits_in_disp8 (offsetT num) |
43234a1e L |
2100 | { |
2101 | int shift = i.memshift; | |
2102 | unsigned int mask; | |
2103 | ||
2104 | if (shift == -1) | |
2105 | abort (); | |
2106 | ||
2107 | mask = (1 << shift) - 1; | |
2108 | ||
2109 | /* Return 0 if NUM isn't properly aligned. */ | |
2110 | if ((num & mask)) | |
2111 | return 0; | |
2112 | ||
2113 | /* Check if NUM will fit in 8bit after shift. */ | |
2114 | return fits_in_signed_byte (num >> shift); | |
2115 | } | |
2116 | ||
a683cc34 SP |
2117 | static INLINE int |
2118 | fits_in_imm4 (offsetT num) | |
2119 | { | |
2120 | return (num & 0xf) == num; | |
2121 | } | |
2122 | ||
40fb9820 | 2123 | static i386_operand_type |
e3bb37b5 | 2124 | smallest_imm_type (offsetT num) |
252b5132 | 2125 | { |
40fb9820 | 2126 | i386_operand_type t; |
7ab9ffdd | 2127 | |
0dfbf9d7 | 2128 | operand_type_set (&t, 0); |
40fb9820 L |
2129 | t.bitfield.imm64 = 1; |
2130 | ||
2131 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2132 | { |
2133 | /* This code is disabled on the 486 because all the Imm1 forms | |
2134 | in the opcode table are slower on the i486. They're the | |
2135 | versions with the implicitly specified single-position | |
2136 | displacement, which has another syntax if you really want to | |
2137 | use that form. */ | |
40fb9820 L |
2138 | t.bitfield.imm1 = 1; |
2139 | t.bitfield.imm8 = 1; | |
2140 | t.bitfield.imm8s = 1; | |
2141 | t.bitfield.imm16 = 1; | |
2142 | t.bitfield.imm32 = 1; | |
2143 | t.bitfield.imm32s = 1; | |
2144 | } | |
2145 | else if (fits_in_signed_byte (num)) | |
2146 | { | |
2147 | t.bitfield.imm8 = 1; | |
2148 | t.bitfield.imm8s = 1; | |
2149 | t.bitfield.imm16 = 1; | |
2150 | t.bitfield.imm32 = 1; | |
2151 | t.bitfield.imm32s = 1; | |
2152 | } | |
2153 | else if (fits_in_unsigned_byte (num)) | |
2154 | { | |
2155 | t.bitfield.imm8 = 1; | |
2156 | t.bitfield.imm16 = 1; | |
2157 | t.bitfield.imm32 = 1; | |
2158 | t.bitfield.imm32s = 1; | |
2159 | } | |
2160 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2161 | { | |
2162 | t.bitfield.imm16 = 1; | |
2163 | t.bitfield.imm32 = 1; | |
2164 | t.bitfield.imm32s = 1; | |
2165 | } | |
2166 | else if (fits_in_signed_long (num)) | |
2167 | { | |
2168 | t.bitfield.imm32 = 1; | |
2169 | t.bitfield.imm32s = 1; | |
2170 | } | |
2171 | else if (fits_in_unsigned_long (num)) | |
2172 | t.bitfield.imm32 = 1; | |
2173 | ||
2174 | return t; | |
47926f60 | 2175 | } |
252b5132 | 2176 | |
847f7ad4 | 2177 | static offsetT |
e3bb37b5 | 2178 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2179 | { |
508866be | 2180 | addressT mask; |
ba2adb93 | 2181 | |
847f7ad4 AM |
2182 | switch (size) |
2183 | { | |
508866be L |
2184 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2185 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2186 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2187 | #ifdef BFD64 |
2188 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2189 | #endif | |
47926f60 | 2190 | default: abort (); |
847f7ad4 AM |
2191 | } |
2192 | ||
9de868bf L |
2193 | #ifdef BFD64 |
2194 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2195 | if (flag_code != CODE_64BIT | |
2196 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2197 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2198 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2199 | #endif |
ba2adb93 | 2200 | |
47926f60 | 2201 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2202 | { |
2203 | char buf1[40], buf2[40]; | |
2204 | ||
2205 | sprint_value (buf1, val); | |
2206 | sprint_value (buf2, val & mask); | |
2207 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2208 | } | |
2209 | return val & mask; | |
2210 | } | |
2211 | ||
c32fa91d L |
2212 | enum PREFIX_GROUP |
2213 | { | |
2214 | PREFIX_EXIST = 0, | |
2215 | PREFIX_LOCK, | |
2216 | PREFIX_REP, | |
04ef582a | 2217 | PREFIX_DS, |
c32fa91d L |
2218 | PREFIX_OTHER |
2219 | }; | |
2220 | ||
2221 | /* Returns | |
2222 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2223 | same class already exists. | |
2224 | b. PREFIX_LOCK if lock prefix is added. | |
2225 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2226 | d. PREFIX_DS if ds prefix is added. |
2227 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2228 | */ |
2229 | ||
2230 | static enum PREFIX_GROUP | |
e3bb37b5 | 2231 | add_prefix (unsigned int prefix) |
252b5132 | 2232 | { |
c32fa91d | 2233 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2234 | unsigned int q; |
252b5132 | 2235 | |
29b0f896 AM |
2236 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2237 | && flag_code == CODE_64BIT) | |
b1905489 | 2238 | { |
161a04f6 L |
2239 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
2240 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
2241 | && (prefix & (REX_R | REX_X | REX_B)))) | |
c32fa91d | 2242 | ret = PREFIX_EXIST; |
b1905489 JB |
2243 | q = REX_PREFIX; |
2244 | } | |
3e73aa7c | 2245 | else |
b1905489 JB |
2246 | { |
2247 | switch (prefix) | |
2248 | { | |
2249 | default: | |
2250 | abort (); | |
2251 | ||
b1905489 | 2252 | case DS_PREFIX_OPCODE: |
04ef582a L |
2253 | ret = PREFIX_DS; |
2254 | /* Fall through. */ | |
2255 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2256 | case ES_PREFIX_OPCODE: |
2257 | case FS_PREFIX_OPCODE: | |
2258 | case GS_PREFIX_OPCODE: | |
2259 | case SS_PREFIX_OPCODE: | |
2260 | q = SEG_PREFIX; | |
2261 | break; | |
2262 | ||
2263 | case REPNE_PREFIX_OPCODE: | |
2264 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2265 | q = REP_PREFIX; |
2266 | ret = PREFIX_REP; | |
2267 | break; | |
2268 | ||
b1905489 | 2269 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2270 | q = LOCK_PREFIX; |
2271 | ret = PREFIX_LOCK; | |
b1905489 JB |
2272 | break; |
2273 | ||
2274 | case FWAIT_OPCODE: | |
2275 | q = WAIT_PREFIX; | |
2276 | break; | |
2277 | ||
2278 | case ADDR_PREFIX_OPCODE: | |
2279 | q = ADDR_PREFIX; | |
2280 | break; | |
2281 | ||
2282 | case DATA_PREFIX_OPCODE: | |
2283 | q = DATA_PREFIX; | |
2284 | break; | |
2285 | } | |
2286 | if (i.prefix[q] != 0) | |
c32fa91d | 2287 | ret = PREFIX_EXIST; |
b1905489 | 2288 | } |
252b5132 | 2289 | |
b1905489 | 2290 | if (ret) |
252b5132 | 2291 | { |
b1905489 JB |
2292 | if (!i.prefix[q]) |
2293 | ++i.prefixes; | |
2294 | i.prefix[q] |= prefix; | |
252b5132 | 2295 | } |
b1905489 JB |
2296 | else |
2297 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2298 | |
252b5132 RH |
2299 | return ret; |
2300 | } | |
2301 | ||
2302 | static void | |
78f12dd3 | 2303 | update_code_flag (int value, int check) |
eecb386c | 2304 | { |
78f12dd3 L |
2305 | PRINTF_LIKE ((*as_error)); |
2306 | ||
1e9cc1c2 | 2307 | flag_code = (enum flag_code) value; |
40fb9820 L |
2308 | if (flag_code == CODE_64BIT) |
2309 | { | |
2310 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2311 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2312 | } |
2313 | else | |
2314 | { | |
2315 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2316 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2317 | } |
2318 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2319 | { |
78f12dd3 L |
2320 | if (check) |
2321 | as_error = as_fatal; | |
2322 | else | |
2323 | as_error = as_bad; | |
2324 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2325 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2326 | } |
40fb9820 | 2327 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2328 | { |
78f12dd3 L |
2329 | if (check) |
2330 | as_error = as_fatal; | |
2331 | else | |
2332 | as_error = as_bad; | |
2333 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2334 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2335 | } |
eecb386c AM |
2336 | stackop_size = '\0'; |
2337 | } | |
2338 | ||
78f12dd3 L |
2339 | static void |
2340 | set_code_flag (int value) | |
2341 | { | |
2342 | update_code_flag (value, 0); | |
2343 | } | |
2344 | ||
eecb386c | 2345 | static void |
e3bb37b5 | 2346 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2347 | { |
1e9cc1c2 | 2348 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2349 | if (flag_code != CODE_16BIT) |
2350 | abort (); | |
2351 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2352 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2353 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2354 | } |
2355 | ||
2356 | static void | |
e3bb37b5 | 2357 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2358 | { |
2359 | /* Find out if register prefixing is specified. */ | |
2360 | int ask_naked_reg = 0; | |
2361 | ||
2362 | SKIP_WHITESPACE (); | |
29b0f896 | 2363 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2364 | { |
d02603dc NC |
2365 | char *string; |
2366 | int e = get_symbol_name (&string); | |
252b5132 | 2367 | |
47926f60 | 2368 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2369 | ask_naked_reg = 1; |
47926f60 | 2370 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2371 | ask_naked_reg = -1; |
2372 | else | |
d0b47220 | 2373 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2374 | (void) restore_line_pointer (e); |
252b5132 RH |
2375 | } |
2376 | demand_empty_rest_of_line (); | |
c3332e24 | 2377 | |
252b5132 RH |
2378 | intel_syntax = syntax_flag; |
2379 | ||
2380 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2381 | allow_naked_reg = (intel_syntax |
2382 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2383 | else |
2384 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2385 | |
ee86248c | 2386 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2387 | |
e4a3b5a4 | 2388 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2389 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2390 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2391 | } |
2392 | ||
1efbbeb4 L |
2393 | static void |
2394 | set_intel_mnemonic (int mnemonic_flag) | |
2395 | { | |
e1d4d893 | 2396 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2397 | } |
2398 | ||
db51cc60 L |
2399 | static void |
2400 | set_allow_index_reg (int flag) | |
2401 | { | |
2402 | allow_index_reg = flag; | |
2403 | } | |
2404 | ||
cb19c032 | 2405 | static void |
7bab8ab5 | 2406 | set_check (int what) |
cb19c032 | 2407 | { |
7bab8ab5 JB |
2408 | enum check_kind *kind; |
2409 | const char *str; | |
2410 | ||
2411 | if (what) | |
2412 | { | |
2413 | kind = &operand_check; | |
2414 | str = "operand"; | |
2415 | } | |
2416 | else | |
2417 | { | |
2418 | kind = &sse_check; | |
2419 | str = "sse"; | |
2420 | } | |
2421 | ||
cb19c032 L |
2422 | SKIP_WHITESPACE (); |
2423 | ||
2424 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2425 | { | |
d02603dc NC |
2426 | char *string; |
2427 | int e = get_symbol_name (&string); | |
cb19c032 L |
2428 | |
2429 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2430 | *kind = check_none; |
cb19c032 | 2431 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2432 | *kind = check_warning; |
cb19c032 | 2433 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2434 | *kind = check_error; |
cb19c032 | 2435 | else |
7bab8ab5 | 2436 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2437 | (void) restore_line_pointer (e); |
cb19c032 L |
2438 | } |
2439 | else | |
7bab8ab5 | 2440 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2441 | |
2442 | demand_empty_rest_of_line (); | |
2443 | } | |
2444 | ||
8a9036a4 L |
2445 | static void |
2446 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2447 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2448 | { |
2449 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2450 | static const char *arch; | |
2451 | ||
2452 | /* Intel LIOM is only supported on ELF. */ | |
2453 | if (!IS_ELF) | |
2454 | return; | |
2455 | ||
2456 | if (!arch) | |
2457 | { | |
2458 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2459 | use default_arch. */ | |
2460 | arch = cpu_arch_name; | |
2461 | if (!arch) | |
2462 | arch = default_arch; | |
2463 | } | |
2464 | ||
81486035 L |
2465 | /* If we are targeting Intel MCU, we must enable it. */ |
2466 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2467 | || new_flag.bitfield.cpuiamcu) | |
2468 | return; | |
2469 | ||
3632d14b | 2470 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2471 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2472 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2473 | return; |
76ba9986 | 2474 | |
7a9068fe L |
2475 | /* If we are targeting Intel K1OM, we must enable it. */ |
2476 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2477 | || new_flag.bitfield.cpuk1om) | |
2478 | return; | |
2479 | ||
8a9036a4 L |
2480 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2481 | #endif | |
2482 | } | |
2483 | ||
e413e4e9 | 2484 | static void |
e3bb37b5 | 2485 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2486 | { |
47926f60 | 2487 | SKIP_WHITESPACE (); |
e413e4e9 | 2488 | |
29b0f896 | 2489 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2490 | { |
d02603dc NC |
2491 | char *string; |
2492 | int e = get_symbol_name (&string); | |
91d6fa6a | 2493 | unsigned int j; |
40fb9820 | 2494 | i386_cpu_flags flags; |
e413e4e9 | 2495 | |
91d6fa6a | 2496 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2497 | { |
91d6fa6a | 2498 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2499 | { |
91d6fa6a | 2500 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2501 | |
5c6af06e JB |
2502 | if (*string != '.') |
2503 | { | |
91d6fa6a | 2504 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2505 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2506 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2507 | if (flag_code == CODE_64BIT) |
2508 | { | |
2509 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2510 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2511 | } | |
2512 | else | |
2513 | { | |
2514 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2515 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2516 | } | |
91d6fa6a NC |
2517 | cpu_arch_isa = cpu_arch[j].type; |
2518 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2519 | if (!cpu_arch_tune_set) |
2520 | { | |
2521 | cpu_arch_tune = cpu_arch_isa; | |
2522 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2523 | } | |
5c6af06e JB |
2524 | break; |
2525 | } | |
40fb9820 | 2526 | |
293f5f65 L |
2527 | flags = cpu_flags_or (cpu_arch_flags, |
2528 | cpu_arch[j].flags); | |
81486035 | 2529 | |
5b64d091 | 2530 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2531 | { |
6305a203 L |
2532 | if (cpu_sub_arch_name) |
2533 | { | |
2534 | char *name = cpu_sub_arch_name; | |
2535 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2536 | cpu_arch[j].name, |
1bf57e9f | 2537 | (const char *) NULL); |
6305a203 L |
2538 | free (name); |
2539 | } | |
2540 | else | |
91d6fa6a | 2541 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2542 | cpu_arch_flags = flags; |
a586129e | 2543 | cpu_arch_isa_flags = flags; |
5c6af06e | 2544 | } |
d02603dc | 2545 | (void) restore_line_pointer (e); |
5c6af06e JB |
2546 | demand_empty_rest_of_line (); |
2547 | return; | |
e413e4e9 AM |
2548 | } |
2549 | } | |
293f5f65 L |
2550 | |
2551 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2552 | { | |
33eaf5de | 2553 | /* Disable an ISA extension. */ |
293f5f65 L |
2554 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2555 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2556 | { | |
2557 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2558 | cpu_noarch[j].flags); | |
2559 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2560 | { | |
2561 | if (cpu_sub_arch_name) | |
2562 | { | |
2563 | char *name = cpu_sub_arch_name; | |
2564 | cpu_sub_arch_name = concat (name, string, | |
2565 | (const char *) NULL); | |
2566 | free (name); | |
2567 | } | |
2568 | else | |
2569 | cpu_sub_arch_name = xstrdup (string); | |
2570 | cpu_arch_flags = flags; | |
2571 | cpu_arch_isa_flags = flags; | |
2572 | } | |
2573 | (void) restore_line_pointer (e); | |
2574 | demand_empty_rest_of_line (); | |
2575 | return; | |
2576 | } | |
2577 | ||
2578 | j = ARRAY_SIZE (cpu_arch); | |
2579 | } | |
2580 | ||
91d6fa6a | 2581 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2582 | as_bad (_("no such architecture: `%s'"), string); |
2583 | ||
2584 | *input_line_pointer = e; | |
2585 | } | |
2586 | else | |
2587 | as_bad (_("missing cpu architecture")); | |
2588 | ||
fddf5b5b AM |
2589 | no_cond_jump_promotion = 0; |
2590 | if (*input_line_pointer == ',' | |
29b0f896 | 2591 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2592 | { |
d02603dc NC |
2593 | char *string; |
2594 | char e; | |
2595 | ||
2596 | ++input_line_pointer; | |
2597 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2598 | |
2599 | if (strcmp (string, "nojumps") == 0) | |
2600 | no_cond_jump_promotion = 1; | |
2601 | else if (strcmp (string, "jumps") == 0) | |
2602 | ; | |
2603 | else | |
2604 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2605 | ||
d02603dc | 2606 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2607 | } |
2608 | ||
e413e4e9 AM |
2609 | demand_empty_rest_of_line (); |
2610 | } | |
2611 | ||
8a9036a4 L |
2612 | enum bfd_architecture |
2613 | i386_arch (void) | |
2614 | { | |
3632d14b | 2615 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2616 | { |
2617 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2618 | || flag_code != CODE_64BIT) | |
2619 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2620 | return bfd_arch_l1om; | |
2621 | } | |
7a9068fe L |
2622 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2623 | { | |
2624 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2625 | || flag_code != CODE_64BIT) | |
2626 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2627 | return bfd_arch_k1om; | |
2628 | } | |
81486035 L |
2629 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2630 | { | |
2631 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2632 | || flag_code == CODE_64BIT) | |
2633 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2634 | return bfd_arch_iamcu; | |
2635 | } | |
8a9036a4 L |
2636 | else |
2637 | return bfd_arch_i386; | |
2638 | } | |
2639 | ||
b9d79e03 | 2640 | unsigned long |
7016a5d5 | 2641 | i386_mach (void) |
b9d79e03 | 2642 | { |
351f65ca | 2643 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2644 | { |
3632d14b | 2645 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2646 | { |
351f65ca L |
2647 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2648 | || default_arch[6] != '\0') | |
8a9036a4 L |
2649 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2650 | return bfd_mach_l1om; | |
2651 | } | |
7a9068fe L |
2652 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2653 | { | |
2654 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2655 | || default_arch[6] != '\0') | |
2656 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2657 | return bfd_mach_k1om; | |
2658 | } | |
351f65ca | 2659 | else if (default_arch[6] == '\0') |
8a9036a4 | 2660 | return bfd_mach_x86_64; |
351f65ca L |
2661 | else |
2662 | return bfd_mach_x64_32; | |
8a9036a4 | 2663 | } |
5197d474 L |
2664 | else if (!strcmp (default_arch, "i386") |
2665 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2666 | { |
2667 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2668 | { | |
2669 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2670 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2671 | return bfd_mach_i386_iamcu; | |
2672 | } | |
2673 | else | |
2674 | return bfd_mach_i386_i386; | |
2675 | } | |
b9d79e03 | 2676 | else |
2b5d6a91 | 2677 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2678 | } |
b9d79e03 | 2679 | \f |
252b5132 | 2680 | void |
7016a5d5 | 2681 | md_begin (void) |
252b5132 RH |
2682 | { |
2683 | const char *hash_err; | |
2684 | ||
86fa6981 L |
2685 | /* Support pseudo prefixes like {disp32}. */ |
2686 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2687 | ||
47926f60 | 2688 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2689 | op_hash = hash_new (); |
2690 | ||
2691 | { | |
d3ce72d0 | 2692 | const insn_template *optab; |
29b0f896 | 2693 | templates *core_optab; |
252b5132 | 2694 | |
47926f60 KH |
2695 | /* Setup for loop. */ |
2696 | optab = i386_optab; | |
add39d23 | 2697 | core_optab = XNEW (templates); |
252b5132 RH |
2698 | core_optab->start = optab; |
2699 | ||
2700 | while (1) | |
2701 | { | |
2702 | ++optab; | |
2703 | if (optab->name == NULL | |
2704 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2705 | { | |
2706 | /* different name --> ship out current template list; | |
47926f60 | 2707 | add to hash table; & begin anew. */ |
252b5132 RH |
2708 | core_optab->end = optab; |
2709 | hash_err = hash_insert (op_hash, | |
2710 | (optab - 1)->name, | |
5a49b8ac | 2711 | (void *) core_optab); |
252b5132 RH |
2712 | if (hash_err) |
2713 | { | |
b37df7c4 | 2714 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2715 | (optab - 1)->name, |
2716 | hash_err); | |
2717 | } | |
2718 | if (optab->name == NULL) | |
2719 | break; | |
add39d23 | 2720 | core_optab = XNEW (templates); |
252b5132 RH |
2721 | core_optab->start = optab; |
2722 | } | |
2723 | } | |
2724 | } | |
2725 | ||
47926f60 | 2726 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2727 | reg_hash = hash_new (); |
2728 | { | |
29b0f896 | 2729 | const reg_entry *regtab; |
c3fe08fa | 2730 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2731 | |
c3fe08fa | 2732 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2733 | { |
5a49b8ac | 2734 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2735 | if (hash_err) |
b37df7c4 | 2736 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2737 | regtab->reg_name, |
2738 | hash_err); | |
252b5132 RH |
2739 | } |
2740 | } | |
2741 | ||
47926f60 | 2742 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2743 | { |
29b0f896 AM |
2744 | int c; |
2745 | char *p; | |
252b5132 RH |
2746 | |
2747 | for (c = 0; c < 256; c++) | |
2748 | { | |
3882b010 | 2749 | if (ISDIGIT (c)) |
252b5132 RH |
2750 | { |
2751 | digit_chars[c] = c; | |
2752 | mnemonic_chars[c] = c; | |
2753 | register_chars[c] = c; | |
2754 | operand_chars[c] = c; | |
2755 | } | |
3882b010 | 2756 | else if (ISLOWER (c)) |
252b5132 RH |
2757 | { |
2758 | mnemonic_chars[c] = c; | |
2759 | register_chars[c] = c; | |
2760 | operand_chars[c] = c; | |
2761 | } | |
3882b010 | 2762 | else if (ISUPPER (c)) |
252b5132 | 2763 | { |
3882b010 | 2764 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2765 | register_chars[c] = mnemonic_chars[c]; |
2766 | operand_chars[c] = c; | |
2767 | } | |
43234a1e | 2768 | else if (c == '{' || c == '}') |
86fa6981 L |
2769 | { |
2770 | mnemonic_chars[c] = c; | |
2771 | operand_chars[c] = c; | |
2772 | } | |
252b5132 | 2773 | |
3882b010 | 2774 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2775 | identifier_chars[c] = c; |
2776 | else if (c >= 128) | |
2777 | { | |
2778 | identifier_chars[c] = c; | |
2779 | operand_chars[c] = c; | |
2780 | } | |
2781 | } | |
2782 | ||
2783 | #ifdef LEX_AT | |
2784 | identifier_chars['@'] = '@'; | |
32137342 NC |
2785 | #endif |
2786 | #ifdef LEX_QM | |
2787 | identifier_chars['?'] = '?'; | |
2788 | operand_chars['?'] = '?'; | |
252b5132 | 2789 | #endif |
252b5132 | 2790 | digit_chars['-'] = '-'; |
c0f3af97 | 2791 | mnemonic_chars['_'] = '_'; |
791fe849 | 2792 | mnemonic_chars['-'] = '-'; |
0003779b | 2793 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2794 | identifier_chars['_'] = '_'; |
2795 | identifier_chars['.'] = '.'; | |
2796 | ||
2797 | for (p = operand_special_chars; *p != '\0'; p++) | |
2798 | operand_chars[(unsigned char) *p] = *p; | |
2799 | } | |
2800 | ||
a4447b93 RH |
2801 | if (flag_code == CODE_64BIT) |
2802 | { | |
ca19b261 KT |
2803 | #if defined (OBJ_COFF) && defined (TE_PE) |
2804 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2805 | ? 32 : 16); | |
2806 | #else | |
a4447b93 | 2807 | x86_dwarf2_return_column = 16; |
ca19b261 | 2808 | #endif |
61ff971f | 2809 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2810 | } |
2811 | else | |
2812 | { | |
2813 | x86_dwarf2_return_column = 8; | |
2814 | x86_cie_data_alignment = -4; | |
2815 | } | |
252b5132 RH |
2816 | } |
2817 | ||
2818 | void | |
e3bb37b5 | 2819 | i386_print_statistics (FILE *file) |
252b5132 RH |
2820 | { |
2821 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2822 | hash_print_statistics (file, "i386 register", reg_hash); | |
2823 | } | |
2824 | \f | |
252b5132 RH |
2825 | #ifdef DEBUG386 |
2826 | ||
ce8a8b2f | 2827 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2828 | static void pte (insn_template *); |
40fb9820 | 2829 | static void pt (i386_operand_type); |
e3bb37b5 L |
2830 | static void pe (expressionS *); |
2831 | static void ps (symbolS *); | |
252b5132 RH |
2832 | |
2833 | static void | |
e3bb37b5 | 2834 | pi (char *line, i386_insn *x) |
252b5132 | 2835 | { |
09137c09 | 2836 | unsigned int j; |
252b5132 RH |
2837 | |
2838 | fprintf (stdout, "%s: template ", line); | |
2839 | pte (&x->tm); | |
09f131f2 JH |
2840 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2841 | x->base_reg ? x->base_reg->reg_name : "none", | |
2842 | x->index_reg ? x->index_reg->reg_name : "none", | |
2843 | x->log2_scale_factor); | |
2844 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2845 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2846 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2847 | x->sib.base, x->sib.index, x->sib.scale); | |
2848 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2849 | (x->rex & REX_W) != 0, |
2850 | (x->rex & REX_R) != 0, | |
2851 | (x->rex & REX_X) != 0, | |
2852 | (x->rex & REX_B) != 0); | |
09137c09 | 2853 | for (j = 0; j < x->operands; j++) |
252b5132 | 2854 | { |
09137c09 SP |
2855 | fprintf (stdout, " #%d: ", j + 1); |
2856 | pt (x->types[j]); | |
252b5132 | 2857 | fprintf (stdout, "\n"); |
dc821c5f | 2858 | if (x->types[j].bitfield.reg |
09137c09 | 2859 | || x->types[j].bitfield.regmmx |
1b54b8d7 | 2860 | || x->types[j].bitfield.regsimd |
09137c09 SP |
2861 | || x->types[j].bitfield.sreg2 |
2862 | || x->types[j].bitfield.sreg3 | |
2863 | || x->types[j].bitfield.control | |
2864 | || x->types[j].bitfield.debug | |
2865 | || x->types[j].bitfield.test) | |
2866 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2867 | if (operand_type_check (x->types[j], imm)) | |
2868 | pe (x->op[j].imms); | |
2869 | if (operand_type_check (x->types[j], disp)) | |
2870 | pe (x->op[j].disps); | |
252b5132 RH |
2871 | } |
2872 | } | |
2873 | ||
2874 | static void | |
d3ce72d0 | 2875 | pte (insn_template *t) |
252b5132 | 2876 | { |
09137c09 | 2877 | unsigned int j; |
252b5132 | 2878 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2879 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2880 | if (t->extension_opcode != None) |
2881 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2882 | if (t->opcode_modifier.d) |
252b5132 | 2883 | fprintf (stdout, "D"); |
40fb9820 | 2884 | if (t->opcode_modifier.w) |
252b5132 RH |
2885 | fprintf (stdout, "W"); |
2886 | fprintf (stdout, "\n"); | |
09137c09 | 2887 | for (j = 0; j < t->operands; j++) |
252b5132 | 2888 | { |
09137c09 SP |
2889 | fprintf (stdout, " #%d type ", j + 1); |
2890 | pt (t->operand_types[j]); | |
252b5132 RH |
2891 | fprintf (stdout, "\n"); |
2892 | } | |
2893 | } | |
2894 | ||
2895 | static void | |
e3bb37b5 | 2896 | pe (expressionS *e) |
252b5132 | 2897 | { |
24eab124 | 2898 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2899 | fprintf (stdout, " add_number %ld (%lx)\n", |
2900 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2901 | if (e->X_add_symbol) |
2902 | { | |
2903 | fprintf (stdout, " add_symbol "); | |
2904 | ps (e->X_add_symbol); | |
2905 | fprintf (stdout, "\n"); | |
2906 | } | |
2907 | if (e->X_op_symbol) | |
2908 | { | |
2909 | fprintf (stdout, " op_symbol "); | |
2910 | ps (e->X_op_symbol); | |
2911 | fprintf (stdout, "\n"); | |
2912 | } | |
2913 | } | |
2914 | ||
2915 | static void | |
e3bb37b5 | 2916 | ps (symbolS *s) |
252b5132 RH |
2917 | { |
2918 | fprintf (stdout, "%s type %s%s", | |
2919 | S_GET_NAME (s), | |
2920 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2921 | segment_name (S_GET_SEGMENT (s))); | |
2922 | } | |
2923 | ||
7b81dfbb | 2924 | static struct type_name |
252b5132 | 2925 | { |
40fb9820 L |
2926 | i386_operand_type mask; |
2927 | const char *name; | |
252b5132 | 2928 | } |
7b81dfbb | 2929 | const type_names[] = |
252b5132 | 2930 | { |
40fb9820 L |
2931 | { OPERAND_TYPE_REG8, "r8" }, |
2932 | { OPERAND_TYPE_REG16, "r16" }, | |
2933 | { OPERAND_TYPE_REG32, "r32" }, | |
2934 | { OPERAND_TYPE_REG64, "r64" }, | |
2935 | { OPERAND_TYPE_IMM8, "i8" }, | |
2936 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2937 | { OPERAND_TYPE_IMM16, "i16" }, | |
2938 | { OPERAND_TYPE_IMM32, "i32" }, | |
2939 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2940 | { OPERAND_TYPE_IMM64, "i64" }, | |
2941 | { OPERAND_TYPE_IMM1, "i1" }, | |
2942 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2943 | { OPERAND_TYPE_DISP8, "d8" }, | |
2944 | { OPERAND_TYPE_DISP16, "d16" }, | |
2945 | { OPERAND_TYPE_DISP32, "d32" }, | |
2946 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2947 | { OPERAND_TYPE_DISP64, "d64" }, | |
2948 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
2949 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2950 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2951 | { OPERAND_TYPE_TEST, "test reg" }, | |
2952 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2953 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2954 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2955 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2956 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2957 | { OPERAND_TYPE_ACC, "Acc" }, | |
2958 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2959 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2960 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 2961 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
2962 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
2963 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 2964 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
2965 | }; |
2966 | ||
2967 | static void | |
40fb9820 | 2968 | pt (i386_operand_type t) |
252b5132 | 2969 | { |
40fb9820 | 2970 | unsigned int j; |
c6fb90c8 | 2971 | i386_operand_type a; |
252b5132 | 2972 | |
40fb9820 | 2973 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2974 | { |
2975 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 2976 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
2977 | fprintf (stdout, "%s, ", type_names[j].name); |
2978 | } | |
252b5132 RH |
2979 | fflush (stdout); |
2980 | } | |
2981 | ||
2982 | #endif /* DEBUG386 */ | |
2983 | \f | |
252b5132 | 2984 | static bfd_reloc_code_real_type |
3956db08 | 2985 | reloc (unsigned int size, |
64e74474 AM |
2986 | int pcrel, |
2987 | int sign, | |
2988 | bfd_reloc_code_real_type other) | |
252b5132 | 2989 | { |
47926f60 | 2990 | if (other != NO_RELOC) |
3956db08 | 2991 | { |
91d6fa6a | 2992 | reloc_howto_type *rel; |
3956db08 JB |
2993 | |
2994 | if (size == 8) | |
2995 | switch (other) | |
2996 | { | |
64e74474 AM |
2997 | case BFD_RELOC_X86_64_GOT32: |
2998 | return BFD_RELOC_X86_64_GOT64; | |
2999 | break; | |
553d1284 L |
3000 | case BFD_RELOC_X86_64_GOTPLT64: |
3001 | return BFD_RELOC_X86_64_GOTPLT64; | |
3002 | break; | |
64e74474 AM |
3003 | case BFD_RELOC_X86_64_PLTOFF64: |
3004 | return BFD_RELOC_X86_64_PLTOFF64; | |
3005 | break; | |
3006 | case BFD_RELOC_X86_64_GOTPC32: | |
3007 | other = BFD_RELOC_X86_64_GOTPC64; | |
3008 | break; | |
3009 | case BFD_RELOC_X86_64_GOTPCREL: | |
3010 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3011 | break; | |
3012 | case BFD_RELOC_X86_64_TPOFF32: | |
3013 | other = BFD_RELOC_X86_64_TPOFF64; | |
3014 | break; | |
3015 | case BFD_RELOC_X86_64_DTPOFF32: | |
3016 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3017 | break; | |
3018 | default: | |
3019 | break; | |
3956db08 | 3020 | } |
e05278af | 3021 | |
8ce3d284 | 3022 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3023 | if (other == BFD_RELOC_SIZE32) |
3024 | { | |
3025 | if (size == 8) | |
1ab668bf | 3026 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3027 | if (pcrel) |
1ab668bf AM |
3028 | { |
3029 | as_bad (_("there are no pc-relative size relocations")); | |
3030 | return NO_RELOC; | |
3031 | } | |
8fd4256d | 3032 | } |
8ce3d284 | 3033 | #endif |
8fd4256d | 3034 | |
e05278af | 3035 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3036 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3037 | sign = -1; |
3038 | ||
91d6fa6a NC |
3039 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3040 | if (!rel) | |
3956db08 | 3041 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3042 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3043 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3044 | bfd_get_reloc_size (rel), |
3956db08 | 3045 | size); |
91d6fa6a | 3046 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3047 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3048 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3049 | && !sign) |
91d6fa6a | 3050 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3051 | && sign > 0)) |
3956db08 JB |
3052 | as_bad (_("relocated field and relocation type differ in signedness")); |
3053 | else | |
3054 | return other; | |
3055 | return NO_RELOC; | |
3056 | } | |
252b5132 RH |
3057 | |
3058 | if (pcrel) | |
3059 | { | |
3e73aa7c | 3060 | if (!sign) |
3956db08 | 3061 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3062 | switch (size) |
3063 | { | |
3064 | case 1: return BFD_RELOC_8_PCREL; | |
3065 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3066 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3067 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3068 | } |
3956db08 | 3069 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3070 | } |
3071 | else | |
3072 | { | |
3956db08 | 3073 | if (sign > 0) |
e5cb08ac | 3074 | switch (size) |
3e73aa7c JH |
3075 | { |
3076 | case 4: return BFD_RELOC_X86_64_32S; | |
3077 | } | |
3078 | else | |
3079 | switch (size) | |
3080 | { | |
3081 | case 1: return BFD_RELOC_8; | |
3082 | case 2: return BFD_RELOC_16; | |
3083 | case 4: return BFD_RELOC_32; | |
3084 | case 8: return BFD_RELOC_64; | |
3085 | } | |
3956db08 JB |
3086 | as_bad (_("cannot do %s %u byte relocation"), |
3087 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3088 | } |
3089 | ||
0cc9e1d3 | 3090 | return NO_RELOC; |
252b5132 RH |
3091 | } |
3092 | ||
47926f60 KH |
3093 | /* Here we decide which fixups can be adjusted to make them relative to |
3094 | the beginning of the section instead of the symbol. Basically we need | |
3095 | to make sure that the dynamic relocations are done correctly, so in | |
3096 | some cases we force the original symbol to be used. */ | |
3097 | ||
252b5132 | 3098 | int |
e3bb37b5 | 3099 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3100 | { |
6d249963 | 3101 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3102 | if (!IS_ELF) |
31312f95 AM |
3103 | return 1; |
3104 | ||
a161fe53 AM |
3105 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3106 | mode. */ | |
3107 | if (use_rela_relocations | |
3108 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3109 | && fixP->fx_pcrel) | |
252b5132 | 3110 | return 0; |
31312f95 | 3111 | |
8d01d9a9 AJ |
3112 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3113 | and changed later by validate_fix. */ | |
3114 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3115 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3116 | return 0; | |
3117 | ||
8fd4256d L |
3118 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3119 | for size relocations. */ | |
3120 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3121 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3122 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3123 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3124 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3125 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3126 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3127 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3128 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3129 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3130 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3131 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3132 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3133 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3134 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3135 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3136 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3137 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3138 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3139 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3140 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3141 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3142 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3143 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3144 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3145 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3146 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3147 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3148 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3149 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3150 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3151 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3152 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3153 | return 0; | |
31312f95 | 3154 | #endif |
252b5132 RH |
3155 | return 1; |
3156 | } | |
252b5132 | 3157 | |
b4cac588 | 3158 | static int |
e3bb37b5 | 3159 | intel_float_operand (const char *mnemonic) |
252b5132 | 3160 | { |
9306ca4a JB |
3161 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3162 | operands, hence the code here is free to improperly handle opcodes that | |
3163 | have no operands (for better performance and smaller code). */ | |
3164 | ||
3165 | if (mnemonic[0] != 'f') | |
3166 | return 0; /* non-math */ | |
3167 | ||
3168 | switch (mnemonic[1]) | |
3169 | { | |
3170 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3171 | the fs segment override prefix not currently handled because no | |
3172 | call path can make opcodes without operands get here */ | |
3173 | case 'i': | |
3174 | return 2 /* integer op */; | |
3175 | case 'l': | |
3176 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3177 | return 3; /* fldcw/fldenv */ | |
3178 | break; | |
3179 | case 'n': | |
3180 | if (mnemonic[2] != 'o' /* fnop */) | |
3181 | return 3; /* non-waiting control op */ | |
3182 | break; | |
3183 | case 'r': | |
3184 | if (mnemonic[2] == 's') | |
3185 | return 3; /* frstor/frstpm */ | |
3186 | break; | |
3187 | case 's': | |
3188 | if (mnemonic[2] == 'a') | |
3189 | return 3; /* fsave */ | |
3190 | if (mnemonic[2] == 't') | |
3191 | { | |
3192 | switch (mnemonic[3]) | |
3193 | { | |
3194 | case 'c': /* fstcw */ | |
3195 | case 'd': /* fstdw */ | |
3196 | case 'e': /* fstenv */ | |
3197 | case 's': /* fsts[gw] */ | |
3198 | return 3; | |
3199 | } | |
3200 | } | |
3201 | break; | |
3202 | case 'x': | |
3203 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3204 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3205 | break; | |
3206 | } | |
252b5132 | 3207 | |
9306ca4a | 3208 | return 1; |
252b5132 RH |
3209 | } |
3210 | ||
c0f3af97 L |
3211 | /* Build the VEX prefix. */ |
3212 | ||
3213 | static void | |
d3ce72d0 | 3214 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3215 | { |
3216 | unsigned int register_specifier; | |
3217 | unsigned int implied_prefix; | |
3218 | unsigned int vector_length; | |
3219 | ||
3220 | /* Check register specifier. */ | |
3221 | if (i.vex.register_specifier) | |
43234a1e L |
3222 | { |
3223 | register_specifier = | |
3224 | ~register_number (i.vex.register_specifier) & 0xf; | |
3225 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3226 | } | |
c0f3af97 L |
3227 | else |
3228 | register_specifier = 0xf; | |
3229 | ||
33eaf5de | 3230 | /* Use 2-byte VEX prefix by swapping destination and source |
fa99fab2 | 3231 | operand. */ |
86fa6981 L |
3232 | if (i.vec_encoding != vex_encoding_vex3 |
3233 | && i.dir_encoding == dir_encoding_default | |
fa99fab2 | 3234 | && i.operands == i.reg_operands |
7f399153 | 3235 | && i.tm.opcode_modifier.vexopcode == VEX0F |
86fa6981 | 3236 | && i.tm.opcode_modifier.load |
fa99fab2 L |
3237 | && i.rex == REX_B) |
3238 | { | |
3239 | unsigned int xchg = i.operands - 1; | |
3240 | union i386_op temp_op; | |
3241 | i386_operand_type temp_type; | |
3242 | ||
3243 | temp_type = i.types[xchg]; | |
3244 | i.types[xchg] = i.types[0]; | |
3245 | i.types[0] = temp_type; | |
3246 | temp_op = i.op[xchg]; | |
3247 | i.op[xchg] = i.op[0]; | |
3248 | i.op[0] = temp_op; | |
3249 | ||
9c2799c2 | 3250 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3251 | |
3252 | i.rex = REX_R; | |
3253 | xchg = i.rm.regmem; | |
3254 | i.rm.regmem = i.rm.reg; | |
3255 | i.rm.reg = xchg; | |
3256 | ||
3257 | /* Use the next insn. */ | |
3258 | i.tm = t[1]; | |
3259 | } | |
3260 | ||
539f890d L |
3261 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3262 | vector_length = avxscalar; | |
10c17abd JB |
3263 | else if (i.tm.opcode_modifier.vex == VEX256) |
3264 | vector_length = 1; | |
539f890d | 3265 | else |
10c17abd JB |
3266 | { |
3267 | unsigned int op; | |
3268 | ||
3269 | vector_length = 0; | |
3270 | for (op = 0; op < t->operands; ++op) | |
3271 | if (t->operand_types[op].bitfield.xmmword | |
3272 | && t->operand_types[op].bitfield.ymmword | |
3273 | && i.types[op].bitfield.ymmword) | |
3274 | { | |
3275 | vector_length = 1; | |
3276 | break; | |
3277 | } | |
3278 | } | |
c0f3af97 L |
3279 | |
3280 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3281 | { | |
3282 | case 0: | |
3283 | implied_prefix = 0; | |
3284 | break; | |
3285 | case DATA_PREFIX_OPCODE: | |
3286 | implied_prefix = 1; | |
3287 | break; | |
3288 | case REPE_PREFIX_OPCODE: | |
3289 | implied_prefix = 2; | |
3290 | break; | |
3291 | case REPNE_PREFIX_OPCODE: | |
3292 | implied_prefix = 3; | |
3293 | break; | |
3294 | default: | |
3295 | abort (); | |
3296 | } | |
3297 | ||
3298 | /* Use 2-byte VEX prefix if possible. */ | |
86fa6981 L |
3299 | if (i.vec_encoding != vex_encoding_vex3 |
3300 | && i.tm.opcode_modifier.vexopcode == VEX0F | |
04251de0 | 3301 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
3302 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3303 | { | |
3304 | /* 2-byte VEX prefix. */ | |
3305 | unsigned int r; | |
3306 | ||
3307 | i.vex.length = 2; | |
3308 | i.vex.bytes[0] = 0xc5; | |
3309 | ||
3310 | /* Check the REX.R bit. */ | |
3311 | r = (i.rex & REX_R) ? 0 : 1; | |
3312 | i.vex.bytes[1] = (r << 7 | |
3313 | | register_specifier << 3 | |
3314 | | vector_length << 2 | |
3315 | | implied_prefix); | |
3316 | } | |
3317 | else | |
3318 | { | |
3319 | /* 3-byte VEX prefix. */ | |
3320 | unsigned int m, w; | |
3321 | ||
f88c9eb0 | 3322 | i.vex.length = 3; |
f88c9eb0 | 3323 | |
7f399153 | 3324 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3325 | { |
7f399153 L |
3326 | case VEX0F: |
3327 | m = 0x1; | |
80de6e00 | 3328 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3329 | break; |
3330 | case VEX0F38: | |
3331 | m = 0x2; | |
80de6e00 | 3332 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3333 | break; |
3334 | case VEX0F3A: | |
3335 | m = 0x3; | |
80de6e00 | 3336 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3337 | break; |
3338 | case XOP08: | |
5dd85c99 SP |
3339 | m = 0x8; |
3340 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3341 | break; |
3342 | case XOP09: | |
f88c9eb0 SP |
3343 | m = 0x9; |
3344 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3345 | break; |
3346 | case XOP0A: | |
f88c9eb0 SP |
3347 | m = 0xa; |
3348 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3349 | break; |
3350 | default: | |
3351 | abort (); | |
f88c9eb0 | 3352 | } |
c0f3af97 | 3353 | |
c0f3af97 L |
3354 | /* The high 3 bits of the second VEX byte are 1's compliment |
3355 | of RXB bits from REX. */ | |
3356 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3357 | ||
3358 | /* Check the REX.W bit. */ | |
3359 | w = (i.rex & REX_W) ? 1 : 0; | |
b28d1bda IT |
3360 | if (i.tm.opcode_modifier.vexw == VEXW1) |
3361 | w = 1; | |
c0f3af97 L |
3362 | |
3363 | i.vex.bytes[2] = (w << 7 | |
3364 | | register_specifier << 3 | |
3365 | | vector_length << 2 | |
3366 | | implied_prefix); | |
3367 | } | |
3368 | } | |
3369 | ||
43234a1e L |
3370 | /* Build the EVEX prefix. */ |
3371 | ||
3372 | static void | |
3373 | build_evex_prefix (void) | |
3374 | { | |
3375 | unsigned int register_specifier; | |
3376 | unsigned int implied_prefix; | |
3377 | unsigned int m, w; | |
3378 | rex_byte vrex_used = 0; | |
3379 | ||
3380 | /* Check register specifier. */ | |
3381 | if (i.vex.register_specifier) | |
3382 | { | |
3383 | gas_assert ((i.vrex & REX_X) == 0); | |
3384 | ||
3385 | register_specifier = i.vex.register_specifier->reg_num; | |
3386 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3387 | register_specifier += 8; | |
3388 | /* The upper 16 registers are encoded in the fourth byte of the | |
3389 | EVEX prefix. */ | |
3390 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3391 | i.vex.bytes[3] = 0x8; | |
3392 | register_specifier = ~register_specifier & 0xf; | |
3393 | } | |
3394 | else | |
3395 | { | |
3396 | register_specifier = 0xf; | |
3397 | ||
3398 | /* Encode upper 16 vector index register in the fourth byte of | |
3399 | the EVEX prefix. */ | |
3400 | if (!(i.vrex & REX_X)) | |
3401 | i.vex.bytes[3] = 0x8; | |
3402 | else | |
3403 | vrex_used |= REX_X; | |
3404 | } | |
3405 | ||
3406 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3407 | { | |
3408 | case 0: | |
3409 | implied_prefix = 0; | |
3410 | break; | |
3411 | case DATA_PREFIX_OPCODE: | |
3412 | implied_prefix = 1; | |
3413 | break; | |
3414 | case REPE_PREFIX_OPCODE: | |
3415 | implied_prefix = 2; | |
3416 | break; | |
3417 | case REPNE_PREFIX_OPCODE: | |
3418 | implied_prefix = 3; | |
3419 | break; | |
3420 | default: | |
3421 | abort (); | |
3422 | } | |
3423 | ||
3424 | /* 4 byte EVEX prefix. */ | |
3425 | i.vex.length = 4; | |
3426 | i.vex.bytes[0] = 0x62; | |
3427 | ||
3428 | /* mmmm bits. */ | |
3429 | switch (i.tm.opcode_modifier.vexopcode) | |
3430 | { | |
3431 | case VEX0F: | |
3432 | m = 1; | |
3433 | break; | |
3434 | case VEX0F38: | |
3435 | m = 2; | |
3436 | break; | |
3437 | case VEX0F3A: | |
3438 | m = 3; | |
3439 | break; | |
3440 | default: | |
3441 | abort (); | |
3442 | break; | |
3443 | } | |
3444 | ||
3445 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3446 | bits from REX. */ | |
3447 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3448 | ||
3449 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3450 | REX_R bit in VREX. */ | |
3451 | if (!(i.vrex & REX_R)) | |
3452 | i.vex.bytes[1] |= 0x10; | |
3453 | else | |
3454 | vrex_used |= REX_R; | |
3455 | ||
3456 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3457 | { | |
3458 | /* When all operands are registers, the REX_X bit in REX is not | |
3459 | used. We reuse it to encode the upper 16 registers, which is | |
3460 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3461 | as 1's compliment. */ | |
3462 | if ((i.vrex & REX_B)) | |
3463 | { | |
3464 | vrex_used |= REX_B; | |
3465 | i.vex.bytes[1] &= ~0x40; | |
3466 | } | |
3467 | } | |
3468 | ||
3469 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3470 | i.vrex &= ~vrex_used; | |
3471 | gas_assert (i.vrex == 0); | |
3472 | ||
3473 | /* Check the REX.W bit. */ | |
3474 | w = (i.rex & REX_W) ? 1 : 0; | |
3475 | if (i.tm.opcode_modifier.vexw) | |
3476 | { | |
3477 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
3478 | w = 1; | |
3479 | } | |
3480 | /* If w is not set it means we are dealing with WIG instruction. */ | |
3481 | else if (!w) | |
3482 | { | |
3483 | if (evexwig == evexw1) | |
3484 | w = 1; | |
3485 | } | |
3486 | ||
3487 | /* Encode the U bit. */ | |
3488 | implied_prefix |= 0x4; | |
3489 | ||
3490 | /* The third byte of the EVEX prefix. */ | |
3491 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3492 | ||
3493 | /* The fourth byte of the EVEX prefix. */ | |
3494 | /* The zeroing-masking bit. */ | |
3495 | if (i.mask && i.mask->zeroing) | |
3496 | i.vex.bytes[3] |= 0x80; | |
3497 | ||
3498 | /* Don't always set the broadcast bit if there is no RC. */ | |
3499 | if (!i.rounding) | |
3500 | { | |
3501 | /* Encode the vector length. */ | |
3502 | unsigned int vec_length; | |
3503 | ||
3504 | switch (i.tm.opcode_modifier.evex) | |
3505 | { | |
3506 | case EVEXLIG: /* LL' is ignored */ | |
3507 | vec_length = evexlig << 5; | |
3508 | break; | |
3509 | case EVEX128: | |
3510 | vec_length = 0 << 5; | |
3511 | break; | |
3512 | case EVEX256: | |
3513 | vec_length = 1 << 5; | |
3514 | break; | |
3515 | case EVEX512: | |
3516 | vec_length = 2 << 5; | |
3517 | break; | |
3518 | default: | |
3519 | abort (); | |
3520 | break; | |
3521 | } | |
3522 | i.vex.bytes[3] |= vec_length; | |
3523 | /* Encode the broadcast bit. */ | |
3524 | if (i.broadcast) | |
3525 | i.vex.bytes[3] |= 0x10; | |
3526 | } | |
3527 | else | |
3528 | { | |
3529 | if (i.rounding->type != saeonly) | |
3530 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3531 | else | |
d3d3c6db | 3532 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3533 | } |
3534 | ||
3535 | if (i.mask && i.mask->mask) | |
3536 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3537 | } | |
3538 | ||
65da13b5 L |
3539 | static void |
3540 | process_immext (void) | |
3541 | { | |
3542 | expressionS *exp; | |
3543 | ||
4c692bc7 JB |
3544 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3545 | && i.operands > 0) | |
65da13b5 | 3546 | { |
4c692bc7 JB |
3547 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3548 | with an opcode suffix which is coded in the same place as an | |
3549 | 8-bit immediate field would be. | |
3550 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3551 | unsigned int x; |
3552 | ||
3553 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3554 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3555 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3556 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3557 | i.tm.name); | |
3558 | ||
3559 | i.operands = 0; | |
65da13b5 L |
3560 | } |
3561 | ||
9916071f AP |
3562 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3563 | { | |
3564 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3565 | suffix which is coded in the same place as an 8-bit immediate | |
3566 | field would be. | |
3567 | Here we check those operands and remove them afterwards. */ | |
3568 | unsigned int x; | |
3569 | ||
3570 | if (i.operands != 3) | |
3571 | abort(); | |
3572 | ||
3573 | for (x = 0; x < 2; x++) | |
3574 | if (register_number (i.op[x].regs) != x) | |
3575 | goto bad_register_operand; | |
3576 | ||
3577 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3578 | if (register_number (i.op[x].regs) | |
3579 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3580 | { | |
3581 | bad_register_operand: | |
3582 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3583 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3584 | i.tm.name); | |
3585 | } | |
3586 | ||
3587 | i.operands = 0; | |
3588 | } | |
3589 | ||
c0f3af97 | 3590 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3591 | which is coded in the same place as an 8-bit immediate field |
3592 | would be. Here we fake an 8-bit immediate operand from the | |
3593 | opcode suffix stored in tm.extension_opcode. | |
3594 | ||
c1e679ec | 3595 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3596 | 3 argument instructions. */ |
65da13b5 | 3597 | |
43234a1e | 3598 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3599 | && (i.operands <= 2 |
43234a1e L |
3600 | || ((i.tm.opcode_modifier.vex |
3601 | || i.tm.opcode_modifier.evex) | |
7ab9ffdd | 3602 | && i.operands <= 4))); |
65da13b5 L |
3603 | |
3604 | exp = &im_expressions[i.imm_operands++]; | |
3605 | i.op[i.operands].imms = exp; | |
3606 | i.types[i.operands] = imm8; | |
3607 | i.operands++; | |
3608 | exp->X_op = O_constant; | |
3609 | exp->X_add_number = i.tm.extension_opcode; | |
3610 | i.tm.extension_opcode = None; | |
3611 | } | |
3612 | ||
42164a71 L |
3613 | |
3614 | static int | |
3615 | check_hle (void) | |
3616 | { | |
3617 | switch (i.tm.opcode_modifier.hleprefixok) | |
3618 | { | |
3619 | default: | |
3620 | abort (); | |
82c2def5 | 3621 | case HLEPrefixNone: |
165de32a L |
3622 | as_bad (_("invalid instruction `%s' after `%s'"), |
3623 | i.tm.name, i.hle_prefix); | |
42164a71 | 3624 | return 0; |
82c2def5 | 3625 | case HLEPrefixLock: |
42164a71 L |
3626 | if (i.prefix[LOCK_PREFIX]) |
3627 | return 1; | |
165de32a | 3628 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3629 | return 0; |
82c2def5 | 3630 | case HLEPrefixAny: |
42164a71 | 3631 | return 1; |
82c2def5 | 3632 | case HLEPrefixRelease: |
42164a71 L |
3633 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3634 | { | |
3635 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3636 | i.tm.name); | |
3637 | return 0; | |
3638 | } | |
3639 | if (i.mem_operands == 0 | |
3640 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3641 | { | |
3642 | as_bad (_("memory destination needed for instruction `%s'" | |
3643 | " after `xrelease'"), i.tm.name); | |
3644 | return 0; | |
3645 | } | |
3646 | return 1; | |
3647 | } | |
3648 | } | |
3649 | ||
252b5132 RH |
3650 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3651 | machine dependent instruction. This function is supposed to emit | |
3652 | the frags/bytes it assembles to. */ | |
3653 | ||
3654 | void | |
65da13b5 | 3655 | md_assemble (char *line) |
252b5132 | 3656 | { |
40fb9820 | 3657 | unsigned int j; |
83b16ac6 | 3658 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 3659 | const insn_template *t; |
252b5132 | 3660 | |
47926f60 | 3661 | /* Initialize globals. */ |
252b5132 RH |
3662 | memset (&i, '\0', sizeof (i)); |
3663 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 3664 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
3665 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
3666 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 3667 | save_stack_p = save_stack; |
252b5132 RH |
3668 | |
3669 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
3670 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 3671 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 3672 | |
29b0f896 AM |
3673 | line = parse_insn (line, mnemonic); |
3674 | if (line == NULL) | |
3675 | return; | |
83b16ac6 | 3676 | mnem_suffix = i.suffix; |
252b5132 | 3677 | |
29b0f896 | 3678 | line = parse_operands (line, mnemonic); |
ee86248c | 3679 | this_operand = -1; |
8325cc63 JB |
3680 | xfree (i.memop1_string); |
3681 | i.memop1_string = NULL; | |
29b0f896 AM |
3682 | if (line == NULL) |
3683 | return; | |
252b5132 | 3684 | |
29b0f896 AM |
3685 | /* Now we've parsed the mnemonic into a set of templates, and have the |
3686 | operands at hand. */ | |
3687 | ||
3688 | /* All intel opcodes have reversed operands except for "bound" and | |
3689 | "enter". We also don't reverse intersegment "jmp" and "call" | |
3690 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 3691 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
3692 | if (intel_syntax |
3693 | && i.operands > 1 | |
29b0f896 | 3694 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 3695 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
3696 | && !(operand_type_check (i.types[0], imm) |
3697 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
3698 | swap_operands (); |
3699 | ||
ec56d5c0 JB |
3700 | /* The order of the immediates should be reversed |
3701 | for 2 immediates extrq and insertq instructions */ | |
3702 | if (i.imm_operands == 2 | |
3703 | && (strcmp (mnemonic, "extrq") == 0 | |
3704 | || strcmp (mnemonic, "insertq") == 0)) | |
3705 | swap_2_operands (0, 1); | |
3706 | ||
29b0f896 AM |
3707 | if (i.imm_operands) |
3708 | optimize_imm (); | |
3709 | ||
b300c311 L |
3710 | /* Don't optimize displacement for movabs since it only takes 64bit |
3711 | displacement. */ | |
3712 | if (i.disp_operands | |
a501d77e | 3713 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
3714 | && (flag_code != CODE_64BIT |
3715 | || strcmp (mnemonic, "movabs") != 0)) | |
3716 | optimize_disp (); | |
29b0f896 AM |
3717 | |
3718 | /* Next, we find a template that matches the given insn, | |
3719 | making sure the overlap of the given operands types is consistent | |
3720 | with the template operand types. */ | |
252b5132 | 3721 | |
83b16ac6 | 3722 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 3723 | return; |
252b5132 | 3724 | |
7bab8ab5 | 3725 | if (sse_check != check_none |
81f8a913 | 3726 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
3727 | && (i.tm.cpu_flags.bitfield.cpusse |
3728 | || i.tm.cpu_flags.bitfield.cpusse2 | |
3729 | || i.tm.cpu_flags.bitfield.cpusse3 | |
3730 | || i.tm.cpu_flags.bitfield.cpussse3 | |
3731 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
3732 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
3733 | { | |
7bab8ab5 | 3734 | (sse_check == check_warning |
daf50ae7 L |
3735 | ? as_warn |
3736 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
3737 | } | |
3738 | ||
321fd21e L |
3739 | /* Zap movzx and movsx suffix. The suffix has been set from |
3740 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
3741 | or extracted from mnemonic in AT&T syntax. But we'll use | |
3742 | the destination register to choose the suffix for encoding. */ | |
3743 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 3744 | { |
321fd21e L |
3745 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
3746 | there is no suffix, the default will be byte extension. */ | |
3747 | if (i.reg_operands != 2 | |
3748 | && !i.suffix | |
7ab9ffdd | 3749 | && intel_syntax) |
321fd21e L |
3750 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
3751 | ||
3752 | i.suffix = 0; | |
cd61ebfe | 3753 | } |
24eab124 | 3754 | |
40fb9820 | 3755 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
3756 | if (!add_prefix (FWAIT_OPCODE)) |
3757 | return; | |
252b5132 | 3758 | |
d5de92cf L |
3759 | /* Check if REP prefix is OK. */ |
3760 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
3761 | { | |
3762 | as_bad (_("invalid instruction `%s' after `%s'"), | |
3763 | i.tm.name, i.rep_prefix); | |
3764 | return; | |
3765 | } | |
3766 | ||
c1ba0266 L |
3767 | /* Check for lock without a lockable instruction. Destination operand |
3768 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
3769 | if (i.prefix[LOCK_PREFIX] |
3770 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
3771 | || i.mem_operands == 0 |
3772 | || (i.tm.base_opcode != 0x86 | |
3773 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
3774 | { |
3775 | as_bad (_("expecting lockable instruction after `lock'")); | |
3776 | return; | |
3777 | } | |
3778 | ||
42164a71 | 3779 | /* Check if HLE prefix is OK. */ |
165de32a | 3780 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
3781 | return; |
3782 | ||
7e8b059b L |
3783 | /* Check BND prefix. */ |
3784 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
3785 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
3786 | ||
04ef582a | 3787 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
3788 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
3789 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 3790 | |
327e8c42 JB |
3791 | if (i.tm.cpu_flags.bitfield.cpumpx) |
3792 | { | |
3793 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
3794 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
3795 | else if (flag_code != CODE_16BIT | |
3796 | ? i.prefix[ADDR_PREFIX] | |
3797 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
3798 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
3799 | } | |
7e8b059b L |
3800 | |
3801 | /* Insert BND prefix. */ | |
3802 | if (add_bnd_prefix | |
3803 | && i.tm.opcode_modifier.bndprefixok | |
3804 | && !i.prefix[BND_PREFIX]) | |
3805 | add_prefix (BND_PREFIX_OPCODE); | |
3806 | ||
29b0f896 | 3807 | /* Check string instruction segment overrides. */ |
40fb9820 | 3808 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
3809 | { |
3810 | if (!check_string ()) | |
5dd0794d | 3811 | return; |
fc0763e6 | 3812 | i.disp_operands = 0; |
29b0f896 | 3813 | } |
5dd0794d | 3814 | |
29b0f896 AM |
3815 | if (!process_suffix ()) |
3816 | return; | |
e413e4e9 | 3817 | |
bc0844ae L |
3818 | /* Update operand types. */ |
3819 | for (j = 0; j < i.operands; j++) | |
3820 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3821 | ||
29b0f896 AM |
3822 | /* Make still unresolved immediate matches conform to size of immediate |
3823 | given in i.suffix. */ | |
3824 | if (!finalize_imm ()) | |
3825 | return; | |
252b5132 | 3826 | |
40fb9820 | 3827 | if (i.types[0].bitfield.imm1) |
29b0f896 | 3828 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 3829 | |
9afe6eb8 L |
3830 | /* We only need to check those implicit registers for instructions |
3831 | with 3 operands or less. */ | |
3832 | if (i.operands <= 3) | |
3833 | for (j = 0; j < i.operands; j++) | |
3834 | if (i.types[j].bitfield.inoutportreg | |
3835 | || i.types[j].bitfield.shiftcount | |
1b54b8d7 | 3836 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
9afe6eb8 | 3837 | i.reg_operands--; |
40fb9820 | 3838 | |
c0f3af97 L |
3839 | /* ImmExt should be processed after SSE2AVX. */ |
3840 | if (!i.tm.opcode_modifier.sse2avx | |
3841 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 3842 | process_immext (); |
252b5132 | 3843 | |
29b0f896 AM |
3844 | /* For insns with operands there are more diddles to do to the opcode. */ |
3845 | if (i.operands) | |
3846 | { | |
3847 | if (!process_operands ()) | |
3848 | return; | |
3849 | } | |
40fb9820 | 3850 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
3851 | { |
3852 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
3853 | as_warn (_("translating to `%sp'"), i.tm.name); | |
3854 | } | |
252b5132 | 3855 | |
9e5e5283 L |
3856 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) |
3857 | { | |
3858 | if (flag_code == CODE_16BIT) | |
3859 | { | |
3860 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
3861 | i.tm.name); | |
3862 | return; | |
3863 | } | |
c0f3af97 | 3864 | |
9e5e5283 L |
3865 | if (i.tm.opcode_modifier.vex) |
3866 | build_vex_prefix (t); | |
3867 | else | |
3868 | build_evex_prefix (); | |
3869 | } | |
43234a1e | 3870 | |
5dd85c99 SP |
3871 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
3872 | instructions may define INT_OPCODE as well, so avoid this corner | |
3873 | case for those instructions that use MODRM. */ | |
3874 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
3875 | && !i.tm.opcode_modifier.modrm |
3876 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
3877 | { |
3878 | i.tm.base_opcode = INT3_OPCODE; | |
3879 | i.imm_operands = 0; | |
3880 | } | |
252b5132 | 3881 | |
40fb9820 L |
3882 | if ((i.tm.opcode_modifier.jump |
3883 | || i.tm.opcode_modifier.jumpbyte | |
3884 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
3885 | && i.op[0].disps->X_op == O_constant) |
3886 | { | |
3887 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
3888 | the absolute address given by the constant. Since ix86 jumps and | |
3889 | calls are pc relative, we need to generate a reloc. */ | |
3890 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
3891 | i.op[0].disps->X_op = O_symbol; | |
3892 | } | |
252b5132 | 3893 | |
40fb9820 | 3894 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 3895 | i.rex |= REX_W; |
252b5132 | 3896 | |
29b0f896 AM |
3897 | /* For 8 bit registers we need an empty rex prefix. Also if the |
3898 | instruction already has a prefix, we need to convert old | |
3899 | registers to new ones. */ | |
773f551c | 3900 | |
dc821c5f | 3901 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte |
29b0f896 | 3902 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
dc821c5f | 3903 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte |
29b0f896 | 3904 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
dc821c5f JB |
3905 | || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
3906 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
3907 | && i.rex != 0)) |
3908 | { | |
3909 | int x; | |
726c5dcd | 3910 | |
29b0f896 AM |
3911 | i.rex |= REX_OPCODE; |
3912 | for (x = 0; x < 2; x++) | |
3913 | { | |
3914 | /* Look for 8 bit operand that uses old registers. */ | |
dc821c5f | 3915 | if (i.types[x].bitfield.reg && i.types[x].bitfield.byte |
29b0f896 | 3916 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 3917 | { |
29b0f896 AM |
3918 | /* In case it is "hi" register, give up. */ |
3919 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 3920 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 3921 | "instruction requiring REX prefix."), |
a540244d | 3922 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 3923 | |
29b0f896 AM |
3924 | /* Otherwise it is equivalent to the extended register. |
3925 | Since the encoding doesn't change this is merely | |
3926 | cosmetic cleanup for debug output. */ | |
3927 | ||
3928 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 3929 | } |
29b0f896 AM |
3930 | } |
3931 | } | |
773f551c | 3932 | |
7ab9ffdd | 3933 | if (i.rex != 0) |
29b0f896 AM |
3934 | add_prefix (REX_OPCODE | i.rex); |
3935 | ||
3936 | /* We are ready to output the insn. */ | |
3937 | output_insn (); | |
3938 | } | |
3939 | ||
3940 | static char * | |
e3bb37b5 | 3941 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
3942 | { |
3943 | char *l = line; | |
3944 | char *token_start = l; | |
3945 | char *mnem_p; | |
5c6af06e | 3946 | int supported; |
d3ce72d0 | 3947 | const insn_template *t; |
b6169b20 | 3948 | char *dot_p = NULL; |
29b0f896 | 3949 | |
29b0f896 AM |
3950 | while (1) |
3951 | { | |
3952 | mnem_p = mnemonic; | |
3953 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
3954 | { | |
b6169b20 L |
3955 | if (*mnem_p == '.') |
3956 | dot_p = mnem_p; | |
29b0f896 AM |
3957 | mnem_p++; |
3958 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 3959 | { |
29b0f896 AM |
3960 | as_bad (_("no such instruction: `%s'"), token_start); |
3961 | return NULL; | |
3962 | } | |
3963 | l++; | |
3964 | } | |
3965 | if (!is_space_char (*l) | |
3966 | && *l != END_OF_INSN | |
e44823cf JB |
3967 | && (intel_syntax |
3968 | || (*l != PREFIX_SEPARATOR | |
3969 | && *l != ','))) | |
29b0f896 AM |
3970 | { |
3971 | as_bad (_("invalid character %s in mnemonic"), | |
3972 | output_invalid (*l)); | |
3973 | return NULL; | |
3974 | } | |
3975 | if (token_start == l) | |
3976 | { | |
e44823cf | 3977 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
3978 | as_bad (_("expecting prefix; got nothing")); |
3979 | else | |
3980 | as_bad (_("expecting mnemonic; got nothing")); | |
3981 | return NULL; | |
3982 | } | |
45288df1 | 3983 | |
29b0f896 | 3984 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 3985 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 3986 | |
29b0f896 AM |
3987 | if (*l != END_OF_INSN |
3988 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
3989 | && current_templates | |
40fb9820 | 3990 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 3991 | { |
c6fb90c8 | 3992 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
3993 | { |
3994 | as_bad ((flag_code != CODE_64BIT | |
3995 | ? _("`%s' is only supported in 64-bit mode") | |
3996 | : _("`%s' is not supported in 64-bit mode")), | |
3997 | current_templates->start->name); | |
3998 | return NULL; | |
3999 | } | |
29b0f896 AM |
4000 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4001 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
4002 | if ((current_templates->start->opcode_modifier.size16 |
4003 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 4004 | && flag_code != CODE_64BIT |
40fb9820 | 4005 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
4006 | ^ (flag_code == CODE_16BIT))) |
4007 | { | |
4008 | as_bad (_("redundant %s prefix"), | |
4009 | current_templates->start->name); | |
4010 | return NULL; | |
45288df1 | 4011 | } |
86fa6981 | 4012 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4013 | { |
86fa6981 L |
4014 | /* Handle pseudo prefixes. */ |
4015 | switch (current_templates->start->base_opcode) | |
4016 | { | |
4017 | case 0x0: | |
4018 | /* {disp8} */ | |
4019 | i.disp_encoding = disp_encoding_8bit; | |
4020 | break; | |
4021 | case 0x1: | |
4022 | /* {disp32} */ | |
4023 | i.disp_encoding = disp_encoding_32bit; | |
4024 | break; | |
4025 | case 0x2: | |
4026 | /* {load} */ | |
4027 | i.dir_encoding = dir_encoding_load; | |
4028 | break; | |
4029 | case 0x3: | |
4030 | /* {store} */ | |
4031 | i.dir_encoding = dir_encoding_store; | |
4032 | break; | |
4033 | case 0x4: | |
4034 | /* {vex2} */ | |
4035 | i.vec_encoding = vex_encoding_vex2; | |
4036 | break; | |
4037 | case 0x5: | |
4038 | /* {vex3} */ | |
4039 | i.vec_encoding = vex_encoding_vex3; | |
4040 | break; | |
4041 | case 0x6: | |
4042 | /* {evex} */ | |
4043 | i.vec_encoding = vex_encoding_evex; | |
4044 | break; | |
4045 | default: | |
4046 | abort (); | |
4047 | } | |
4048 | } | |
4049 | else | |
4050 | { | |
4051 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4052 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4053 | { |
4e9ac44a L |
4054 | case PREFIX_EXIST: |
4055 | return NULL; | |
4056 | case PREFIX_DS: | |
d777820b | 4057 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4058 | i.notrack_prefix = current_templates->start->name; |
4059 | break; | |
4060 | case PREFIX_REP: | |
4061 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4062 | i.hle_prefix = current_templates->start->name; | |
4063 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4064 | i.bnd_prefix = current_templates->start->name; | |
4065 | else | |
4066 | i.rep_prefix = current_templates->start->name; | |
4067 | break; | |
4068 | default: | |
4069 | break; | |
86fa6981 | 4070 | } |
29b0f896 AM |
4071 | } |
4072 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4073 | token_start = ++l; | |
4074 | } | |
4075 | else | |
4076 | break; | |
4077 | } | |
45288df1 | 4078 | |
30a55f88 | 4079 | if (!current_templates) |
b6169b20 | 4080 | { |
f8a5c266 L |
4081 | /* Check if we should swap operand or force 32bit displacement in |
4082 | encoding. */ | |
30a55f88 | 4083 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
86fa6981 | 4084 | i.dir_encoding = dir_encoding_store; |
8d63c93e | 4085 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4086 | && dot_p[1] == 'd' |
4087 | && dot_p[2] == '8') | |
4088 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4089 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4090 | && dot_p[1] == 'd' |
4091 | && dot_p[2] == '3' | |
4092 | && dot_p[3] == '2') | |
a501d77e | 4093 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4094 | else |
4095 | goto check_suffix; | |
4096 | mnem_p = dot_p; | |
4097 | *dot_p = '\0'; | |
d3ce72d0 | 4098 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4099 | } |
4100 | ||
29b0f896 AM |
4101 | if (!current_templates) |
4102 | { | |
b6169b20 | 4103 | check_suffix: |
29b0f896 AM |
4104 | /* See if we can get a match by trimming off a suffix. */ |
4105 | switch (mnem_p[-1]) | |
4106 | { | |
4107 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
4108 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
4109 | i.suffix = SHORT_MNEM_SUFFIX; | |
4110 | else | |
1a0670f3 | 4111 | /* Fall through. */ |
29b0f896 AM |
4112 | case BYTE_MNEM_SUFFIX: |
4113 | case QWORD_MNEM_SUFFIX: | |
4114 | i.suffix = mnem_p[-1]; | |
4115 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4116 | current_templates = (const templates *) hash_find (op_hash, |
4117 | mnemonic); | |
29b0f896 AM |
4118 | break; |
4119 | case SHORT_MNEM_SUFFIX: | |
4120 | case LONG_MNEM_SUFFIX: | |
4121 | if (!intel_syntax) | |
4122 | { | |
4123 | i.suffix = mnem_p[-1]; | |
4124 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4125 | current_templates = (const templates *) hash_find (op_hash, |
4126 | mnemonic); | |
29b0f896 AM |
4127 | } |
4128 | break; | |
252b5132 | 4129 | |
29b0f896 AM |
4130 | /* Intel Syntax. */ |
4131 | case 'd': | |
4132 | if (intel_syntax) | |
4133 | { | |
9306ca4a | 4134 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
4135 | i.suffix = SHORT_MNEM_SUFFIX; |
4136 | else | |
4137 | i.suffix = LONG_MNEM_SUFFIX; | |
4138 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4139 | current_templates = (const templates *) hash_find (op_hash, |
4140 | mnemonic); | |
29b0f896 AM |
4141 | } |
4142 | break; | |
4143 | } | |
4144 | if (!current_templates) | |
4145 | { | |
4146 | as_bad (_("no such instruction: `%s'"), token_start); | |
4147 | return NULL; | |
4148 | } | |
4149 | } | |
252b5132 | 4150 | |
40fb9820 L |
4151 | if (current_templates->start->opcode_modifier.jump |
4152 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4153 | { |
4154 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4155 | predict taken and predict not taken respectively. | |
4156 | I'm not sure that branch hints actually do anything on loop | |
4157 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4158 | may work in the future and it doesn't hurt to accept them | |
4159 | now. */ | |
4160 | if (l[0] == ',' && l[1] == 'p') | |
4161 | { | |
4162 | if (l[2] == 't') | |
4163 | { | |
4164 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4165 | return NULL; | |
4166 | l += 3; | |
4167 | } | |
4168 | else if (l[2] == 'n') | |
4169 | { | |
4170 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4171 | return NULL; | |
4172 | l += 3; | |
4173 | } | |
4174 | } | |
4175 | } | |
4176 | /* Any other comma loses. */ | |
4177 | if (*l == ',') | |
4178 | { | |
4179 | as_bad (_("invalid character %s in mnemonic"), | |
4180 | output_invalid (*l)); | |
4181 | return NULL; | |
4182 | } | |
252b5132 | 4183 | |
29b0f896 | 4184 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4185 | supported = 0; |
4186 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4187 | { | |
c0f3af97 L |
4188 | supported |= cpu_flags_match (t); |
4189 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 4190 | goto skip; |
5c6af06e | 4191 | } |
3629bb00 | 4192 | |
c0f3af97 | 4193 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
4194 | { |
4195 | as_bad (flag_code == CODE_64BIT | |
4196 | ? _("`%s' is not supported in 64-bit mode") | |
4197 | : _("`%s' is only supported in 64-bit mode"), | |
4198 | current_templates->start->name); | |
4199 | return NULL; | |
4200 | } | |
c0f3af97 | 4201 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 4202 | { |
3629bb00 | 4203 | as_bad (_("`%s' is not supported on `%s%s'"), |
7ab9ffdd | 4204 | current_templates->start->name, |
41aacd83 | 4205 | cpu_arch_name ? cpu_arch_name : default_arch, |
3629bb00 L |
4206 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
4207 | return NULL; | |
29b0f896 | 4208 | } |
3629bb00 L |
4209 | |
4210 | skip: | |
4211 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 4212 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
4213 | { |
4214 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
4215 | } | |
252b5132 | 4216 | |
29b0f896 AM |
4217 | return l; |
4218 | } | |
252b5132 | 4219 | |
29b0f896 | 4220 | static char * |
e3bb37b5 | 4221 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4222 | { |
4223 | char *token_start; | |
3138f287 | 4224 | |
29b0f896 AM |
4225 | /* 1 if operand is pending after ','. */ |
4226 | unsigned int expecting_operand = 0; | |
252b5132 | 4227 | |
29b0f896 AM |
4228 | /* Non-zero if operand parens not balanced. */ |
4229 | unsigned int paren_not_balanced; | |
4230 | ||
4231 | while (*l != END_OF_INSN) | |
4232 | { | |
4233 | /* Skip optional white space before operand. */ | |
4234 | if (is_space_char (*l)) | |
4235 | ++l; | |
d02603dc | 4236 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4237 | { |
4238 | as_bad (_("invalid character %s before operand %d"), | |
4239 | output_invalid (*l), | |
4240 | i.operands + 1); | |
4241 | return NULL; | |
4242 | } | |
d02603dc | 4243 | token_start = l; /* After white space. */ |
29b0f896 AM |
4244 | paren_not_balanced = 0; |
4245 | while (paren_not_balanced || *l != ',') | |
4246 | { | |
4247 | if (*l == END_OF_INSN) | |
4248 | { | |
4249 | if (paren_not_balanced) | |
4250 | { | |
4251 | if (!intel_syntax) | |
4252 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4253 | i.operands + 1); | |
4254 | else | |
4255 | as_bad (_("unbalanced brackets in operand %d."), | |
4256 | i.operands + 1); | |
4257 | return NULL; | |
4258 | } | |
4259 | else | |
4260 | break; /* we are done */ | |
4261 | } | |
d02603dc | 4262 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4263 | { |
4264 | as_bad (_("invalid character %s in operand %d"), | |
4265 | output_invalid (*l), | |
4266 | i.operands + 1); | |
4267 | return NULL; | |
4268 | } | |
4269 | if (!intel_syntax) | |
4270 | { | |
4271 | if (*l == '(') | |
4272 | ++paren_not_balanced; | |
4273 | if (*l == ')') | |
4274 | --paren_not_balanced; | |
4275 | } | |
4276 | else | |
4277 | { | |
4278 | if (*l == '[') | |
4279 | ++paren_not_balanced; | |
4280 | if (*l == ']') | |
4281 | --paren_not_balanced; | |
4282 | } | |
4283 | l++; | |
4284 | } | |
4285 | if (l != token_start) | |
4286 | { /* Yes, we've read in another operand. */ | |
4287 | unsigned int operand_ok; | |
4288 | this_operand = i.operands++; | |
4289 | if (i.operands > MAX_OPERANDS) | |
4290 | { | |
4291 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4292 | MAX_OPERANDS); | |
4293 | return NULL; | |
4294 | } | |
9d46ce34 | 4295 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4296 | /* Now parse operand adding info to 'i' as we go along. */ |
4297 | END_STRING_AND_SAVE (l); | |
4298 | ||
4299 | if (intel_syntax) | |
4300 | operand_ok = | |
4301 | i386_intel_operand (token_start, | |
4302 | intel_float_operand (mnemonic)); | |
4303 | else | |
a7619375 | 4304 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4305 | |
4306 | RESTORE_END_STRING (l); | |
4307 | if (!operand_ok) | |
4308 | return NULL; | |
4309 | } | |
4310 | else | |
4311 | { | |
4312 | if (expecting_operand) | |
4313 | { | |
4314 | expecting_operand_after_comma: | |
4315 | as_bad (_("expecting operand after ','; got nothing")); | |
4316 | return NULL; | |
4317 | } | |
4318 | if (*l == ',') | |
4319 | { | |
4320 | as_bad (_("expecting operand before ','; got nothing")); | |
4321 | return NULL; | |
4322 | } | |
4323 | } | |
7f3f1ea2 | 4324 | |
29b0f896 AM |
4325 | /* Now *l must be either ',' or END_OF_INSN. */ |
4326 | if (*l == ',') | |
4327 | { | |
4328 | if (*++l == END_OF_INSN) | |
4329 | { | |
4330 | /* Just skip it, if it's \n complain. */ | |
4331 | goto expecting_operand_after_comma; | |
4332 | } | |
4333 | expecting_operand = 1; | |
4334 | } | |
4335 | } | |
4336 | return l; | |
4337 | } | |
7f3f1ea2 | 4338 | |
050dfa73 | 4339 | static void |
4d456e3d | 4340 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4341 | { |
4342 | union i386_op temp_op; | |
40fb9820 | 4343 | i386_operand_type temp_type; |
050dfa73 | 4344 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4345 | |
050dfa73 MM |
4346 | temp_type = i.types[xchg2]; |
4347 | i.types[xchg2] = i.types[xchg1]; | |
4348 | i.types[xchg1] = temp_type; | |
4349 | temp_op = i.op[xchg2]; | |
4350 | i.op[xchg2] = i.op[xchg1]; | |
4351 | i.op[xchg1] = temp_op; | |
4352 | temp_reloc = i.reloc[xchg2]; | |
4353 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4354 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4355 | |
4356 | if (i.mask) | |
4357 | { | |
4358 | if (i.mask->operand == xchg1) | |
4359 | i.mask->operand = xchg2; | |
4360 | else if (i.mask->operand == xchg2) | |
4361 | i.mask->operand = xchg1; | |
4362 | } | |
4363 | if (i.broadcast) | |
4364 | { | |
4365 | if (i.broadcast->operand == xchg1) | |
4366 | i.broadcast->operand = xchg2; | |
4367 | else if (i.broadcast->operand == xchg2) | |
4368 | i.broadcast->operand = xchg1; | |
4369 | } | |
4370 | if (i.rounding) | |
4371 | { | |
4372 | if (i.rounding->operand == xchg1) | |
4373 | i.rounding->operand = xchg2; | |
4374 | else if (i.rounding->operand == xchg2) | |
4375 | i.rounding->operand = xchg1; | |
4376 | } | |
050dfa73 MM |
4377 | } |
4378 | ||
29b0f896 | 4379 | static void |
e3bb37b5 | 4380 | swap_operands (void) |
29b0f896 | 4381 | { |
b7c61d9a | 4382 | switch (i.operands) |
050dfa73 | 4383 | { |
c0f3af97 | 4384 | case 5: |
b7c61d9a | 4385 | case 4: |
4d456e3d | 4386 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4387 | /* Fall through. */ |
b7c61d9a L |
4388 | case 3: |
4389 | case 2: | |
4d456e3d | 4390 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4391 | break; |
4392 | default: | |
4393 | abort (); | |
29b0f896 | 4394 | } |
29b0f896 AM |
4395 | |
4396 | if (i.mem_operands == 2) | |
4397 | { | |
4398 | const seg_entry *temp_seg; | |
4399 | temp_seg = i.seg[0]; | |
4400 | i.seg[0] = i.seg[1]; | |
4401 | i.seg[1] = temp_seg; | |
4402 | } | |
4403 | } | |
252b5132 | 4404 | |
29b0f896 AM |
4405 | /* Try to ensure constant immediates are represented in the smallest |
4406 | opcode possible. */ | |
4407 | static void | |
e3bb37b5 | 4408 | optimize_imm (void) |
29b0f896 AM |
4409 | { |
4410 | char guess_suffix = 0; | |
4411 | int op; | |
252b5132 | 4412 | |
29b0f896 AM |
4413 | if (i.suffix) |
4414 | guess_suffix = i.suffix; | |
4415 | else if (i.reg_operands) | |
4416 | { | |
4417 | /* Figure out a suffix from the last register operand specified. | |
4418 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4419 | but the following works for instructions with immediates. | |
4420 | In any case, we can't set i.suffix yet. */ | |
4421 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 4422 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
7ab9ffdd | 4423 | { |
40fb9820 L |
4424 | guess_suffix = BYTE_MNEM_SUFFIX; |
4425 | break; | |
4426 | } | |
dc821c5f | 4427 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
252b5132 | 4428 | { |
40fb9820 L |
4429 | guess_suffix = WORD_MNEM_SUFFIX; |
4430 | break; | |
4431 | } | |
dc821c5f | 4432 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
4433 | { |
4434 | guess_suffix = LONG_MNEM_SUFFIX; | |
4435 | break; | |
4436 | } | |
dc821c5f | 4437 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
4438 | { |
4439 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4440 | break; |
252b5132 | 4441 | } |
29b0f896 AM |
4442 | } |
4443 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4444 | guess_suffix = WORD_MNEM_SUFFIX; | |
4445 | ||
4446 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4447 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4448 | { |
4449 | switch (i.op[op].imms->X_op) | |
252b5132 | 4450 | { |
29b0f896 AM |
4451 | case O_constant: |
4452 | /* If a suffix is given, this operand may be shortened. */ | |
4453 | switch (guess_suffix) | |
252b5132 | 4454 | { |
29b0f896 | 4455 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
4456 | i.types[op].bitfield.imm32 = 1; |
4457 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4458 | break; |
4459 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
4460 | i.types[op].bitfield.imm16 = 1; |
4461 | i.types[op].bitfield.imm32 = 1; | |
4462 | i.types[op].bitfield.imm32s = 1; | |
4463 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4464 | break; |
4465 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
4466 | i.types[op].bitfield.imm8 = 1; |
4467 | i.types[op].bitfield.imm8s = 1; | |
4468 | i.types[op].bitfield.imm16 = 1; | |
4469 | i.types[op].bitfield.imm32 = 1; | |
4470 | i.types[op].bitfield.imm32s = 1; | |
4471 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 4472 | break; |
252b5132 | 4473 | } |
252b5132 | 4474 | |
29b0f896 AM |
4475 | /* If this operand is at most 16 bits, convert it |
4476 | to a signed 16 bit number before trying to see | |
4477 | whether it will fit in an even smaller size. | |
4478 | This allows a 16-bit operand such as $0xffe0 to | |
4479 | be recognised as within Imm8S range. */ | |
40fb9820 | 4480 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 4481 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 4482 | { |
29b0f896 AM |
4483 | i.op[op].imms->X_add_number = |
4484 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
4485 | } | |
a28def75 L |
4486 | #ifdef BFD64 |
4487 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 4488 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
4489 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
4490 | == 0)) | |
4491 | { | |
4492 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
4493 | ^ ((offsetT) 1 << 31)) | |
4494 | - ((offsetT) 1 << 31)); | |
4495 | } | |
a28def75 | 4496 | #endif |
40fb9820 | 4497 | i.types[op] |
c6fb90c8 L |
4498 | = operand_type_or (i.types[op], |
4499 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 4500 | |
29b0f896 AM |
4501 | /* We must avoid matching of Imm32 templates when 64bit |
4502 | only immediate is available. */ | |
4503 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 4504 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 4505 | break; |
252b5132 | 4506 | |
29b0f896 AM |
4507 | case O_absent: |
4508 | case O_register: | |
4509 | abort (); | |
4510 | ||
4511 | /* Symbols and expressions. */ | |
4512 | default: | |
9cd96992 JB |
4513 | /* Convert symbolic operand to proper sizes for matching, but don't |
4514 | prevent matching a set of insns that only supports sizes other | |
4515 | than those matching the insn suffix. */ | |
4516 | { | |
40fb9820 | 4517 | i386_operand_type mask, allowed; |
d3ce72d0 | 4518 | const insn_template *t; |
9cd96992 | 4519 | |
0dfbf9d7 L |
4520 | operand_type_set (&mask, 0); |
4521 | operand_type_set (&allowed, 0); | |
40fb9820 | 4522 | |
4eed87de AM |
4523 | for (t = current_templates->start; |
4524 | t < current_templates->end; | |
4525 | ++t) | |
c6fb90c8 L |
4526 | allowed = operand_type_or (allowed, |
4527 | t->operand_types[op]); | |
9cd96992 JB |
4528 | switch (guess_suffix) |
4529 | { | |
4530 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
4531 | mask.bitfield.imm64 = 1; |
4532 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
4533 | break; |
4534 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 4535 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
4536 | break; |
4537 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 4538 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
4539 | break; |
4540 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 4541 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
4542 | break; |
4543 | default: | |
9cd96992 JB |
4544 | break; |
4545 | } | |
c6fb90c8 | 4546 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 4547 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 4548 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 4549 | } |
29b0f896 | 4550 | break; |
252b5132 | 4551 | } |
29b0f896 AM |
4552 | } |
4553 | } | |
47926f60 | 4554 | |
29b0f896 AM |
4555 | /* Try to use the smallest displacement type too. */ |
4556 | static void | |
e3bb37b5 | 4557 | optimize_disp (void) |
29b0f896 AM |
4558 | { |
4559 | int op; | |
3e73aa7c | 4560 | |
29b0f896 | 4561 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4562 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 4563 | { |
b300c311 | 4564 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 4565 | { |
91d6fa6a | 4566 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 4567 | |
40fb9820 | 4568 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 4569 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
4570 | { |
4571 | /* If this operand is at most 16 bits, convert | |
4572 | to a signed 16 bit number and don't use 64bit | |
4573 | displacement. */ | |
91d6fa6a | 4574 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 4575 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4576 | } |
a28def75 L |
4577 | #ifdef BFD64 |
4578 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 4579 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 4580 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
4581 | { |
4582 | /* If this operand is at most 32 bits, convert | |
4583 | to a signed 32 bit number and don't use 64bit | |
4584 | displacement. */ | |
91d6fa6a NC |
4585 | op_disp &= (((offsetT) 2 << 31) - 1); |
4586 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 4587 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4588 | } |
a28def75 | 4589 | #endif |
91d6fa6a | 4590 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 4591 | { |
40fb9820 L |
4592 | i.types[op].bitfield.disp8 = 0; |
4593 | i.types[op].bitfield.disp16 = 0; | |
4594 | i.types[op].bitfield.disp32 = 0; | |
4595 | i.types[op].bitfield.disp32s = 0; | |
4596 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
4597 | i.op[op].disps = 0; |
4598 | i.disp_operands--; | |
4599 | } | |
4600 | else if (flag_code == CODE_64BIT) | |
4601 | { | |
91d6fa6a | 4602 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 4603 | { |
40fb9820 L |
4604 | i.types[op].bitfield.disp64 = 0; |
4605 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 4606 | } |
0e1147d9 | 4607 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 4608 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 4609 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 4610 | } |
40fb9820 L |
4611 | if ((i.types[op].bitfield.disp32 |
4612 | || i.types[op].bitfield.disp32s | |
4613 | || i.types[op].bitfield.disp16) | |
b5014f7a | 4614 | && fits_in_disp8 (op_disp)) |
40fb9820 | 4615 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 4616 | } |
67a4f2b7 AO |
4617 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
4618 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
4619 | { | |
4620 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
4621 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
4622 | i.types[op].bitfield.disp8 = 0; |
4623 | i.types[op].bitfield.disp16 = 0; | |
4624 | i.types[op].bitfield.disp32 = 0; | |
4625 | i.types[op].bitfield.disp32s = 0; | |
4626 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
4627 | } |
4628 | else | |
b300c311 | 4629 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 4630 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 4631 | } |
29b0f896 AM |
4632 | } |
4633 | ||
6c30d220 L |
4634 | /* Check if operands are valid for the instruction. */ |
4635 | ||
4636 | static int | |
4637 | check_VecOperands (const insn_template *t) | |
4638 | { | |
43234a1e L |
4639 | unsigned int op; |
4640 | ||
6c30d220 L |
4641 | /* Without VSIB byte, we can't have a vector register for index. */ |
4642 | if (!t->opcode_modifier.vecsib | |
4643 | && i.index_reg | |
1b54b8d7 JB |
4644 | && (i.index_reg->reg_type.bitfield.xmmword |
4645 | || i.index_reg->reg_type.bitfield.ymmword | |
4646 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
4647 | { |
4648 | i.error = unsupported_vector_index_register; | |
4649 | return 1; | |
4650 | } | |
4651 | ||
ad8ecc81 MZ |
4652 | /* Check if default mask is allowed. */ |
4653 | if (t->opcode_modifier.nodefmask | |
4654 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
4655 | { | |
4656 | i.error = no_default_mask; | |
4657 | return 1; | |
4658 | } | |
4659 | ||
7bab8ab5 JB |
4660 | /* For VSIB byte, we need a vector register for index, and all vector |
4661 | registers must be distinct. */ | |
4662 | if (t->opcode_modifier.vecsib) | |
4663 | { | |
4664 | if (!i.index_reg | |
6c30d220 | 4665 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 4666 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 4667 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 4668 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 4669 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 4670 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
4671 | { |
4672 | i.error = invalid_vsib_address; | |
4673 | return 1; | |
4674 | } | |
4675 | ||
43234a1e L |
4676 | gas_assert (i.reg_operands == 2 || i.mask); |
4677 | if (i.reg_operands == 2 && !i.mask) | |
4678 | { | |
1b54b8d7 JB |
4679 | gas_assert (i.types[0].bitfield.regsimd); |
4680 | gas_assert (i.types[0].bitfield.xmmword | |
4681 | || i.types[0].bitfield.ymmword); | |
4682 | gas_assert (i.types[2].bitfield.regsimd); | |
4683 | gas_assert (i.types[2].bitfield.xmmword | |
4684 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
4685 | if (operand_check == check_none) |
4686 | return 0; | |
4687 | if (register_number (i.op[0].regs) | |
4688 | != register_number (i.index_reg) | |
4689 | && register_number (i.op[2].regs) | |
4690 | != register_number (i.index_reg) | |
4691 | && register_number (i.op[0].regs) | |
4692 | != register_number (i.op[2].regs)) | |
4693 | return 0; | |
4694 | if (operand_check == check_error) | |
4695 | { | |
4696 | i.error = invalid_vector_register_set; | |
4697 | return 1; | |
4698 | } | |
4699 | as_warn (_("mask, index, and destination registers should be distinct")); | |
4700 | } | |
8444f82a MZ |
4701 | else if (i.reg_operands == 1 && i.mask) |
4702 | { | |
1b54b8d7 JB |
4703 | if (i.types[1].bitfield.regsimd |
4704 | && (i.types[1].bitfield.xmmword | |
4705 | || i.types[1].bitfield.ymmword | |
4706 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
4707 | && (register_number (i.op[1].regs) |
4708 | == register_number (i.index_reg))) | |
4709 | { | |
4710 | if (operand_check == check_error) | |
4711 | { | |
4712 | i.error = invalid_vector_register_set; | |
4713 | return 1; | |
4714 | } | |
4715 | if (operand_check != check_none) | |
4716 | as_warn (_("index and destination registers should be distinct")); | |
4717 | } | |
4718 | } | |
43234a1e | 4719 | } |
7bab8ab5 | 4720 | |
43234a1e L |
4721 | /* Check if broadcast is supported by the instruction and is applied |
4722 | to the memory operand. */ | |
4723 | if (i.broadcast) | |
4724 | { | |
4725 | int broadcasted_opnd_size; | |
4726 | ||
4727 | /* Check if specified broadcast is supported in this instruction, | |
4728 | and it's applied to memory operand of DWORD or QWORD type, | |
4729 | depending on VecESize. */ | |
4730 | if (i.broadcast->type != t->opcode_modifier.broadcast | |
4731 | || !i.types[i.broadcast->operand].bitfield.mem | |
4732 | || (t->opcode_modifier.vecesize == 0 | |
4733 | && !i.types[i.broadcast->operand].bitfield.dword | |
4734 | && !i.types[i.broadcast->operand].bitfield.unspecified) | |
4735 | || (t->opcode_modifier.vecesize == 1 | |
4736 | && !i.types[i.broadcast->operand].bitfield.qword | |
4737 | && !i.types[i.broadcast->operand].bitfield.unspecified)) | |
4738 | goto bad_broadcast; | |
4739 | ||
4740 | broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32; | |
4741 | if (i.broadcast->type == BROADCAST_1TO16) | |
4742 | broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */ | |
4743 | else if (i.broadcast->type == BROADCAST_1TO8) | |
4744 | broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */ | |
b28d1bda IT |
4745 | else if (i.broadcast->type == BROADCAST_1TO4) |
4746 | broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */ | |
4747 | else if (i.broadcast->type == BROADCAST_1TO2) | |
4748 | broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */ | |
43234a1e L |
4749 | else |
4750 | goto bad_broadcast; | |
4751 | ||
4752 | if ((broadcasted_opnd_size == 256 | |
4753 | && !t->operand_types[i.broadcast->operand].bitfield.ymmword) | |
4754 | || (broadcasted_opnd_size == 512 | |
4755 | && !t->operand_types[i.broadcast->operand].bitfield.zmmword)) | |
4756 | { | |
4757 | bad_broadcast: | |
4758 | i.error = unsupported_broadcast; | |
4759 | return 1; | |
4760 | } | |
4761 | } | |
4762 | /* If broadcast is supported in this instruction, we need to check if | |
4763 | operand of one-element size isn't specified without broadcast. */ | |
4764 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
4765 | { | |
4766 | /* Find memory operand. */ | |
4767 | for (op = 0; op < i.operands; op++) | |
4768 | if (operand_type_check (i.types[op], anymem)) | |
4769 | break; | |
4770 | gas_assert (op < i.operands); | |
4771 | /* Check size of the memory operand. */ | |
4772 | if ((t->opcode_modifier.vecesize == 0 | |
4773 | && i.types[op].bitfield.dword) | |
4774 | || (t->opcode_modifier.vecesize == 1 | |
4775 | && i.types[op].bitfield.qword)) | |
4776 | { | |
4777 | i.error = broadcast_needed; | |
4778 | return 1; | |
4779 | } | |
4780 | } | |
4781 | ||
4782 | /* Check if requested masking is supported. */ | |
4783 | if (i.mask | |
4784 | && (!t->opcode_modifier.masking | |
4785 | || (i.mask->zeroing | |
4786 | && t->opcode_modifier.masking == MERGING_MASKING))) | |
4787 | { | |
4788 | i.error = unsupported_masking; | |
4789 | return 1; | |
4790 | } | |
4791 | ||
4792 | /* Check if masking is applied to dest operand. */ | |
4793 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
4794 | { | |
4795 | i.error = mask_not_on_destination; | |
4796 | return 1; | |
4797 | } | |
4798 | ||
43234a1e L |
4799 | /* Check RC/SAE. */ |
4800 | if (i.rounding) | |
4801 | { | |
4802 | if ((i.rounding->type != saeonly | |
4803 | && !t->opcode_modifier.staticrounding) | |
4804 | || (i.rounding->type == saeonly | |
4805 | && (t->opcode_modifier.staticrounding | |
4806 | || !t->opcode_modifier.sae))) | |
4807 | { | |
4808 | i.error = unsupported_rc_sae; | |
4809 | return 1; | |
4810 | } | |
4811 | /* If the instruction has several immediate operands and one of | |
4812 | them is rounding, the rounding operand should be the last | |
4813 | immediate operand. */ | |
4814 | if (i.imm_operands > 1 | |
4815 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 4816 | { |
43234a1e | 4817 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
4818 | return 1; |
4819 | } | |
6c30d220 L |
4820 | } |
4821 | ||
43234a1e | 4822 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
4823 | if (t->opcode_modifier.disp8memshift |
4824 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
4825 | { |
4826 | if (i.broadcast) | |
4827 | i.memshift = t->opcode_modifier.vecesize ? 3 : 2; | |
4828 | else | |
4829 | i.memshift = t->opcode_modifier.disp8memshift; | |
4830 | ||
4831 | for (op = 0; op < i.operands; op++) | |
4832 | if (operand_type_check (i.types[op], disp) | |
4833 | && i.op[op].disps->X_op == O_constant) | |
4834 | { | |
b5014f7a | 4835 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 4836 | { |
b5014f7a JB |
4837 | i.types[op].bitfield.disp8 = 1; |
4838 | return 0; | |
43234a1e | 4839 | } |
b5014f7a | 4840 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
4841 | } |
4842 | } | |
b5014f7a JB |
4843 | |
4844 | i.memshift = 0; | |
43234a1e | 4845 | |
6c30d220 L |
4846 | return 0; |
4847 | } | |
4848 | ||
43f3e2ee | 4849 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
4850 | operand types. */ |
4851 | ||
4852 | static int | |
4853 | VEX_check_operands (const insn_template *t) | |
4854 | { | |
86fa6981 | 4855 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 4856 | { |
86fa6981 L |
4857 | /* This instruction must be encoded with EVEX prefix. */ |
4858 | if (!t->opcode_modifier.evex) | |
4859 | { | |
4860 | i.error = unsupported; | |
4861 | return 1; | |
4862 | } | |
4863 | return 0; | |
43234a1e L |
4864 | } |
4865 | ||
a683cc34 | 4866 | if (!t->opcode_modifier.vex) |
86fa6981 L |
4867 | { |
4868 | /* This instruction template doesn't have VEX prefix. */ | |
4869 | if (i.vec_encoding != vex_encoding_default) | |
4870 | { | |
4871 | i.error = unsupported; | |
4872 | return 1; | |
4873 | } | |
4874 | return 0; | |
4875 | } | |
a683cc34 SP |
4876 | |
4877 | /* Only check VEX_Imm4, which must be the first operand. */ | |
4878 | if (t->operand_types[0].bitfield.vec_imm4) | |
4879 | { | |
4880 | if (i.op[0].imms->X_op != O_constant | |
4881 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 4882 | { |
a65babc9 | 4883 | i.error = bad_imm4; |
891edac4 L |
4884 | return 1; |
4885 | } | |
a683cc34 SP |
4886 | |
4887 | /* Turn off Imm8 so that update_imm won't complain. */ | |
4888 | i.types[0] = vec_imm4; | |
4889 | } | |
4890 | ||
4891 | return 0; | |
4892 | } | |
4893 | ||
d3ce72d0 | 4894 | static const insn_template * |
83b16ac6 | 4895 | match_template (char mnem_suffix) |
29b0f896 AM |
4896 | { |
4897 | /* Points to template once we've found it. */ | |
d3ce72d0 | 4898 | const insn_template *t; |
40fb9820 | 4899 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 4900 | i386_operand_type overlap4; |
29b0f896 | 4901 | unsigned int found_reverse_match; |
83b16ac6 | 4902 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 4903 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 4904 | int addr_prefix_disp; |
a5c311ca | 4905 | unsigned int j; |
3629bb00 | 4906 | unsigned int found_cpu_match; |
45664ddb | 4907 | unsigned int check_register; |
5614d22c | 4908 | enum i386_error specific_error = 0; |
29b0f896 | 4909 | |
c0f3af97 L |
4910 | #if MAX_OPERANDS != 5 |
4911 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
4912 | #endif |
4913 | ||
29b0f896 | 4914 | found_reverse_match = 0; |
539e75ad | 4915 | addr_prefix_disp = -1; |
40fb9820 L |
4916 | |
4917 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
4918 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
4919 | suffix_check.no_bsuf = 1; | |
4920 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4921 | suffix_check.no_wsuf = 1; | |
4922 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
4923 | suffix_check.no_ssuf = 1; | |
4924 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4925 | suffix_check.no_lsuf = 1; | |
4926 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4927 | suffix_check.no_qsuf = 1; | |
4928 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 4929 | suffix_check.no_ldsuf = 1; |
29b0f896 | 4930 | |
83b16ac6 JB |
4931 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
4932 | if (intel_syntax) | |
4933 | { | |
4934 | switch (mnem_suffix) | |
4935 | { | |
4936 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
4937 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
4938 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
4939 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
4940 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
4941 | } | |
4942 | } | |
4943 | ||
01559ecc L |
4944 | /* Must have right number of operands. */ |
4945 | i.error = number_of_operands_mismatch; | |
4946 | ||
45aa61fe | 4947 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 4948 | { |
539e75ad L |
4949 | addr_prefix_disp = -1; |
4950 | ||
29b0f896 AM |
4951 | if (i.operands != t->operands) |
4952 | continue; | |
4953 | ||
50aecf8c | 4954 | /* Check processor support. */ |
a65babc9 | 4955 | i.error = unsupported; |
c0f3af97 L |
4956 | found_cpu_match = (cpu_flags_match (t) |
4957 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
4958 | if (!found_cpu_match) |
4959 | continue; | |
4960 | ||
e1d4d893 | 4961 | /* Check old gcc support. */ |
a65babc9 | 4962 | i.error = old_gcc_only; |
e1d4d893 L |
4963 | if (!old_gcc && t->opcode_modifier.oldgcc) |
4964 | continue; | |
4965 | ||
4966 | /* Check AT&T mnemonic. */ | |
a65babc9 | 4967 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 4968 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
4969 | continue; |
4970 | ||
e92bae62 | 4971 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 4972 | i.error = unsupported_syntax; |
5c07affc | 4973 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
4974 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
4975 | || (intel64 && t->opcode_modifier.amd64) | |
4976 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
4977 | continue; |
4978 | ||
20592a94 | 4979 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 4980 | i.error = invalid_instruction_suffix; |
567e4e96 L |
4981 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
4982 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
4983 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
4984 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
4985 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
4986 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
4987 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 4988 | continue; |
83b16ac6 JB |
4989 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
4990 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
4991 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
4992 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
4993 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
4994 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
4995 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
4996 | continue; | |
29b0f896 | 4997 | |
5c07affc | 4998 | if (!operand_size_match (t)) |
7d5e4556 | 4999 | continue; |
539e75ad | 5000 | |
5c07affc L |
5001 | for (j = 0; j < MAX_OPERANDS; j++) |
5002 | operand_types[j] = t->operand_types[j]; | |
5003 | ||
45aa61fe AM |
5004 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5005 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5006 | && flag_code != CODE_64BIT | |
5007 | && (intel_syntax | |
40fb9820 | 5008 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
5009 | && !intel_float_operand (t->name)) |
5010 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 5011 | && ((!operand_types[0].bitfield.regmmx |
1b54b8d7 | 5012 | && !operand_types[0].bitfield.regsimd) |
40fb9820 | 5013 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5014 | && !operand_types[t->operands > 1].bitfield.regsimd)) |
45aa61fe AM |
5015 | && (t->base_opcode != 0x0fc7 |
5016 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5017 | continue; | |
5018 | ||
192dc9c6 JB |
5019 | /* In general, don't allow 32-bit operands on pre-386. */ |
5020 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5021 | && !cpu_arch_flags.bitfield.cpui386 | |
5022 | && (intel_syntax | |
5023 | ? (!t->opcode_modifier.ignoresize | |
5024 | && !intel_float_operand (t->name)) | |
5025 | : intel_float_operand (t->name) != 2) | |
5026 | && ((!operand_types[0].bitfield.regmmx | |
1b54b8d7 | 5027 | && !operand_types[0].bitfield.regsimd) |
192dc9c6 | 5028 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5029 | && !operand_types[t->operands > 1].bitfield.regsimd))) |
192dc9c6 JB |
5030 | continue; |
5031 | ||
29b0f896 | 5032 | /* Do not verify operands when there are none. */ |
50aecf8c | 5033 | else |
29b0f896 | 5034 | { |
c6fb90c8 | 5035 | if (!t->operands) |
2dbab7d5 L |
5036 | /* We've found a match; break out of loop. */ |
5037 | break; | |
29b0f896 | 5038 | } |
252b5132 | 5039 | |
539e75ad L |
5040 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5041 | into Disp32/Disp16/Disp32 operand. */ | |
5042 | if (i.prefix[ADDR_PREFIX] != 0) | |
5043 | { | |
40fb9820 | 5044 | /* There should be only one Disp operand. */ |
539e75ad L |
5045 | switch (flag_code) |
5046 | { | |
5047 | case CODE_16BIT: | |
40fb9820 L |
5048 | for (j = 0; j < MAX_OPERANDS; j++) |
5049 | { | |
5050 | if (operand_types[j].bitfield.disp16) | |
5051 | { | |
5052 | addr_prefix_disp = j; | |
5053 | operand_types[j].bitfield.disp32 = 1; | |
5054 | operand_types[j].bitfield.disp16 = 0; | |
5055 | break; | |
5056 | } | |
5057 | } | |
539e75ad L |
5058 | break; |
5059 | case CODE_32BIT: | |
40fb9820 L |
5060 | for (j = 0; j < MAX_OPERANDS; j++) |
5061 | { | |
5062 | if (operand_types[j].bitfield.disp32) | |
5063 | { | |
5064 | addr_prefix_disp = j; | |
5065 | operand_types[j].bitfield.disp32 = 0; | |
5066 | operand_types[j].bitfield.disp16 = 1; | |
5067 | break; | |
5068 | } | |
5069 | } | |
539e75ad L |
5070 | break; |
5071 | case CODE_64BIT: | |
40fb9820 L |
5072 | for (j = 0; j < MAX_OPERANDS; j++) |
5073 | { | |
5074 | if (operand_types[j].bitfield.disp64) | |
5075 | { | |
5076 | addr_prefix_disp = j; | |
5077 | operand_types[j].bitfield.disp64 = 0; | |
5078 | operand_types[j].bitfield.disp32 = 1; | |
5079 | break; | |
5080 | } | |
5081 | } | |
539e75ad L |
5082 | break; |
5083 | } | |
539e75ad L |
5084 | } |
5085 | ||
02a86693 L |
5086 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5087 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5088 | continue; | |
5089 | ||
56ffb741 L |
5090 | /* We check register size if needed. */ |
5091 | check_register = t->opcode_modifier.checkregsize; | |
c6fb90c8 | 5092 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5093 | switch (t->operands) |
5094 | { | |
5095 | case 1: | |
40fb9820 | 5096 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5097 | continue; |
5098 | break; | |
5099 | case 2: | |
33eaf5de | 5100 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5101 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5102 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5103 | zero-extend %eax to %rax. */ | |
5104 | if (flag_code == CODE_64BIT | |
5105 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
5106 | && operand_type_equal (&i.types [0], &acc32) |
5107 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 5108 | continue; |
86fa6981 L |
5109 | /* If we want store form, we reverse direction of operands. */ |
5110 | if (i.dir_encoding == dir_encoding_store | |
5111 | && t->opcode_modifier.d) | |
5112 | goto check_reverse; | |
1a0670f3 | 5113 | /* Fall through. */ |
b6169b20 | 5114 | |
29b0f896 | 5115 | case 3: |
86fa6981 L |
5116 | /* If we want store form, we skip the current load. */ |
5117 | if (i.dir_encoding == dir_encoding_store | |
5118 | && i.mem_operands == 0 | |
5119 | && t->opcode_modifier.load) | |
fa99fab2 | 5120 | continue; |
1a0670f3 | 5121 | /* Fall through. */ |
f48ff2ae | 5122 | case 4: |
c0f3af97 | 5123 | case 5: |
c6fb90c8 | 5124 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5125 | if (!operand_type_match (overlap0, i.types[0]) |
5126 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb | 5127 | || (check_register |
dc821c5f | 5128 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5129 | operand_types[0], |
dc821c5f | 5130 | i.types[1], |
40fb9820 | 5131 | operand_types[1]))) |
29b0f896 AM |
5132 | { |
5133 | /* Check if other direction is valid ... */ | |
40fb9820 | 5134 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
5135 | continue; |
5136 | ||
b6169b20 | 5137 | check_reverse: |
29b0f896 | 5138 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
5139 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
5140 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
5141 | if (!operand_type_match (overlap0, i.types[0]) |
5142 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb | 5143 | || (check_register |
dc821c5f | 5144 | && !operand_type_register_match (i.types[0], |
45664ddb | 5145 | operand_types[1], |
45664ddb L |
5146 | i.types[1], |
5147 | operand_types[0]))) | |
29b0f896 AM |
5148 | { |
5149 | /* Does not match either direction. */ | |
5150 | continue; | |
5151 | } | |
5152 | /* found_reverse_match holds which of D or FloatDR | |
5153 | we've found. */ | |
40fb9820 | 5154 | if (t->opcode_modifier.d) |
8a2ed489 | 5155 | found_reverse_match = Opcode_D; |
40fb9820 | 5156 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
5157 | found_reverse_match = Opcode_FloatD; |
5158 | else | |
5159 | found_reverse_match = 0; | |
40fb9820 | 5160 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5161 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5162 | } |
f48ff2ae | 5163 | else |
29b0f896 | 5164 | { |
f48ff2ae | 5165 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5166 | switch (t->operands) |
5167 | { | |
c0f3af97 L |
5168 | case 5: |
5169 | overlap4 = operand_type_and (i.types[4], | |
5170 | operand_types[4]); | |
1a0670f3 | 5171 | /* Fall through. */ |
d1cbb4db | 5172 | case 4: |
c6fb90c8 L |
5173 | overlap3 = operand_type_and (i.types[3], |
5174 | operand_types[3]); | |
1a0670f3 | 5175 | /* Fall through. */ |
d1cbb4db | 5176 | case 3: |
c6fb90c8 L |
5177 | overlap2 = operand_type_and (i.types[2], |
5178 | operand_types[2]); | |
d1cbb4db L |
5179 | break; |
5180 | } | |
29b0f896 | 5181 | |
f48ff2ae L |
5182 | switch (t->operands) |
5183 | { | |
c0f3af97 L |
5184 | case 5: |
5185 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 5186 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 5187 | operand_types[3], |
c0f3af97 L |
5188 | i.types[4], |
5189 | operand_types[4])) | |
5190 | continue; | |
1a0670f3 | 5191 | /* Fall through. */ |
f48ff2ae | 5192 | case 4: |
40fb9820 | 5193 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb | 5194 | || (check_register |
dc821c5f | 5195 | && !operand_type_register_match (i.types[2], |
45664ddb | 5196 | operand_types[2], |
45664ddb L |
5197 | i.types[3], |
5198 | operand_types[3]))) | |
f48ff2ae | 5199 | continue; |
1a0670f3 | 5200 | /* Fall through. */ |
f48ff2ae L |
5201 | case 3: |
5202 | /* Here we make use of the fact that there are no | |
5203 | reverse match 3 operand instructions, and all 3 | |
5204 | operand instructions only need to be checked for | |
5205 | register consistency between operands 2 and 3. */ | |
40fb9820 | 5206 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb | 5207 | || (check_register |
dc821c5f | 5208 | && !operand_type_register_match (i.types[1], |
45664ddb | 5209 | operand_types[1], |
45664ddb L |
5210 | i.types[2], |
5211 | operand_types[2]))) | |
f48ff2ae L |
5212 | continue; |
5213 | break; | |
5214 | } | |
29b0f896 | 5215 | } |
f48ff2ae | 5216 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5217 | slip through to break. */ |
5218 | } | |
3629bb00 | 5219 | if (!found_cpu_match) |
29b0f896 AM |
5220 | { |
5221 | found_reverse_match = 0; | |
5222 | continue; | |
5223 | } | |
c0f3af97 | 5224 | |
5614d22c JB |
5225 | /* Check if vector and VEX operands are valid. */ |
5226 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5227 | { | |
5228 | specific_error = i.error; | |
5229 | continue; | |
5230 | } | |
a683cc34 | 5231 | |
29b0f896 AM |
5232 | /* We've found a match; break out of loop. */ |
5233 | break; | |
5234 | } | |
5235 | ||
5236 | if (t == current_templates->end) | |
5237 | { | |
5238 | /* We found no match. */ | |
a65babc9 | 5239 | const char *err_msg; |
5614d22c | 5240 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5241 | { |
5242 | default: | |
5243 | abort (); | |
86e026a4 | 5244 | case operand_size_mismatch: |
a65babc9 L |
5245 | err_msg = _("operand size mismatch"); |
5246 | break; | |
5247 | case operand_type_mismatch: | |
5248 | err_msg = _("operand type mismatch"); | |
5249 | break; | |
5250 | case register_type_mismatch: | |
5251 | err_msg = _("register type mismatch"); | |
5252 | break; | |
5253 | case number_of_operands_mismatch: | |
5254 | err_msg = _("number of operands mismatch"); | |
5255 | break; | |
5256 | case invalid_instruction_suffix: | |
5257 | err_msg = _("invalid instruction suffix"); | |
5258 | break; | |
5259 | case bad_imm4: | |
4a2608e3 | 5260 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 L |
5261 | break; |
5262 | case old_gcc_only: | |
5263 | err_msg = _("only supported with old gcc"); | |
5264 | break; | |
5265 | case unsupported_with_intel_mnemonic: | |
5266 | err_msg = _("unsupported with Intel mnemonic"); | |
5267 | break; | |
5268 | case unsupported_syntax: | |
5269 | err_msg = _("unsupported syntax"); | |
5270 | break; | |
5271 | case unsupported: | |
35262a23 | 5272 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
5273 | current_templates->start->name); |
5274 | return NULL; | |
6c30d220 L |
5275 | case invalid_vsib_address: |
5276 | err_msg = _("invalid VSIB address"); | |
5277 | break; | |
7bab8ab5 JB |
5278 | case invalid_vector_register_set: |
5279 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5280 | break; | |
6c30d220 L |
5281 | case unsupported_vector_index_register: |
5282 | err_msg = _("unsupported vector index register"); | |
5283 | break; | |
43234a1e L |
5284 | case unsupported_broadcast: |
5285 | err_msg = _("unsupported broadcast"); | |
5286 | break; | |
5287 | case broadcast_not_on_src_operand: | |
5288 | err_msg = _("broadcast not on source memory operand"); | |
5289 | break; | |
5290 | case broadcast_needed: | |
5291 | err_msg = _("broadcast is needed for operand of such type"); | |
5292 | break; | |
5293 | case unsupported_masking: | |
5294 | err_msg = _("unsupported masking"); | |
5295 | break; | |
5296 | case mask_not_on_destination: | |
5297 | err_msg = _("mask not on destination operand"); | |
5298 | break; | |
5299 | case no_default_mask: | |
5300 | err_msg = _("default mask isn't allowed"); | |
5301 | break; | |
5302 | case unsupported_rc_sae: | |
5303 | err_msg = _("unsupported static rounding/sae"); | |
5304 | break; | |
5305 | case rc_sae_operand_not_last_imm: | |
5306 | if (intel_syntax) | |
5307 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
5308 | else | |
5309 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
5310 | break; | |
5311 | case invalid_register_operand: | |
5312 | err_msg = _("invalid register operand"); | |
5313 | break; | |
a65babc9 L |
5314 | } |
5315 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 5316 | current_templates->start->name); |
fa99fab2 | 5317 | return NULL; |
29b0f896 | 5318 | } |
252b5132 | 5319 | |
29b0f896 AM |
5320 | if (!quiet_warnings) |
5321 | { | |
5322 | if (!intel_syntax | |
40fb9820 L |
5323 | && (i.types[0].bitfield.jumpabsolute |
5324 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
5325 | { |
5326 | as_warn (_("indirect %s without `*'"), t->name); | |
5327 | } | |
5328 | ||
40fb9820 L |
5329 | if (t->opcode_modifier.isprefix |
5330 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
5331 | { |
5332 | /* Warn them that a data or address size prefix doesn't | |
5333 | affect assembly of the next line of code. */ | |
5334 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
5335 | } | |
5336 | } | |
5337 | ||
5338 | /* Copy the template we found. */ | |
5339 | i.tm = *t; | |
539e75ad L |
5340 | |
5341 | if (addr_prefix_disp != -1) | |
5342 | i.tm.operand_types[addr_prefix_disp] | |
5343 | = operand_types[addr_prefix_disp]; | |
5344 | ||
29b0f896 AM |
5345 | if (found_reverse_match) |
5346 | { | |
5347 | /* If we found a reverse match we must alter the opcode | |
5348 | direction bit. found_reverse_match holds bits to change | |
5349 | (different for int & float insns). */ | |
5350 | ||
5351 | i.tm.base_opcode ^= found_reverse_match; | |
5352 | ||
539e75ad L |
5353 | i.tm.operand_types[0] = operand_types[1]; |
5354 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
5355 | } |
5356 | ||
fa99fab2 | 5357 | return t; |
29b0f896 AM |
5358 | } |
5359 | ||
5360 | static int | |
e3bb37b5 | 5361 | check_string (void) |
29b0f896 | 5362 | { |
40fb9820 L |
5363 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
5364 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
5365 | { |
5366 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
5367 | { | |
a87af027 | 5368 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5369 | i.tm.name, |
a87af027 JB |
5370 | mem_op + 1, |
5371 | register_prefix); | |
29b0f896 AM |
5372 | return 0; |
5373 | } | |
5374 | /* There's only ever one segment override allowed per instruction. | |
5375 | This instruction possibly has a legal segment override on the | |
5376 | second operand, so copy the segment to where non-string | |
5377 | instructions store it, allowing common code. */ | |
5378 | i.seg[0] = i.seg[1]; | |
5379 | } | |
40fb9820 | 5380 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
5381 | { |
5382 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
5383 | { | |
a87af027 | 5384 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5385 | i.tm.name, |
a87af027 JB |
5386 | mem_op + 2, |
5387 | register_prefix); | |
29b0f896 AM |
5388 | return 0; |
5389 | } | |
5390 | } | |
5391 | return 1; | |
5392 | } | |
5393 | ||
5394 | static int | |
543613e9 | 5395 | process_suffix (void) |
29b0f896 AM |
5396 | { |
5397 | /* If matched instruction specifies an explicit instruction mnemonic | |
5398 | suffix, use it. */ | |
40fb9820 L |
5399 | if (i.tm.opcode_modifier.size16) |
5400 | i.suffix = WORD_MNEM_SUFFIX; | |
5401 | else if (i.tm.opcode_modifier.size32) | |
5402 | i.suffix = LONG_MNEM_SUFFIX; | |
5403 | else if (i.tm.opcode_modifier.size64) | |
5404 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
5405 | else if (i.reg_operands) |
5406 | { | |
5407 | /* If there's no instruction mnemonic suffix we try to invent one | |
5408 | based on register operands. */ | |
5409 | if (!i.suffix) | |
5410 | { | |
5411 | /* We take i.suffix from the last register operand specified, | |
5412 | Destination register type is more significant than source | |
381d071f L |
5413 | register type. crc32 in SSE4.2 prefers source register |
5414 | type. */ | |
5415 | if (i.tm.base_opcode == 0xf20f38f1) | |
5416 | { | |
dc821c5f | 5417 | if (i.types[0].bitfield.reg && i.types[0].bitfield.word) |
40fb9820 | 5418 | i.suffix = WORD_MNEM_SUFFIX; |
dc821c5f | 5419 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword) |
40fb9820 | 5420 | i.suffix = LONG_MNEM_SUFFIX; |
dc821c5f | 5421 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword) |
40fb9820 | 5422 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f | 5423 | } |
9344ff29 | 5424 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 5425 | { |
dc821c5f | 5426 | if (i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
20592a94 L |
5427 | i.suffix = BYTE_MNEM_SUFFIX; |
5428 | } | |
381d071f L |
5429 | |
5430 | if (!i.suffix) | |
5431 | { | |
5432 | int op; | |
5433 | ||
20592a94 L |
5434 | if (i.tm.base_opcode == 0xf20f38f1 |
5435 | || i.tm.base_opcode == 0xf20f38f0) | |
5436 | { | |
5437 | /* We have to know the operand size for crc32. */ | |
5438 | as_bad (_("ambiguous memory operand size for `%s`"), | |
5439 | i.tm.name); | |
5440 | return 0; | |
5441 | } | |
5442 | ||
381d071f | 5443 | for (op = i.operands; --op >= 0;) |
b76bc5d5 JB |
5444 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
5445 | && !i.tm.operand_types[op].bitfield.shiftcount) | |
381d071f | 5446 | { |
dc821c5f | 5447 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
40fb9820 L |
5448 | { |
5449 | i.suffix = BYTE_MNEM_SUFFIX; | |
5450 | break; | |
5451 | } | |
dc821c5f | 5452 | if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
40fb9820 L |
5453 | { |
5454 | i.suffix = WORD_MNEM_SUFFIX; | |
5455 | break; | |
5456 | } | |
dc821c5f | 5457 | if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
5458 | { |
5459 | i.suffix = LONG_MNEM_SUFFIX; | |
5460 | break; | |
5461 | } | |
dc821c5f | 5462 | if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
5463 | { |
5464 | i.suffix = QWORD_MNEM_SUFFIX; | |
5465 | break; | |
5466 | } | |
381d071f L |
5467 | } |
5468 | } | |
29b0f896 AM |
5469 | } |
5470 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
5471 | { | |
2eb952a4 L |
5472 | if (intel_syntax |
5473 | && i.tm.opcode_modifier.ignoresize | |
5474 | && i.tm.opcode_modifier.no_bsuf) | |
5475 | i.suffix = 0; | |
5476 | else if (!check_byte_reg ()) | |
29b0f896 AM |
5477 | return 0; |
5478 | } | |
5479 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5480 | { | |
2eb952a4 L |
5481 | if (intel_syntax |
5482 | && i.tm.opcode_modifier.ignoresize | |
5483 | && i.tm.opcode_modifier.no_lsuf) | |
5484 | i.suffix = 0; | |
5485 | else if (!check_long_reg ()) | |
29b0f896 AM |
5486 | return 0; |
5487 | } | |
5488 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5489 | { | |
955e1e6a L |
5490 | if (intel_syntax |
5491 | && i.tm.opcode_modifier.ignoresize | |
5492 | && i.tm.opcode_modifier.no_qsuf) | |
5493 | i.suffix = 0; | |
5494 | else if (!check_qword_reg ()) | |
29b0f896 AM |
5495 | return 0; |
5496 | } | |
5497 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5498 | { | |
2eb952a4 L |
5499 | if (intel_syntax |
5500 | && i.tm.opcode_modifier.ignoresize | |
5501 | && i.tm.opcode_modifier.no_wsuf) | |
5502 | i.suffix = 0; | |
5503 | else if (!check_word_reg ()) | |
29b0f896 AM |
5504 | return 0; |
5505 | } | |
c0f3af97 | 5506 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
43234a1e L |
5507 | || i.suffix == YMMWORD_MNEM_SUFFIX |
5508 | || i.suffix == ZMMWORD_MNEM_SUFFIX) | |
582d5edd | 5509 | { |
43234a1e | 5510 | /* Skip if the instruction has x/y/z suffix. match_template |
582d5edd L |
5511 | should check if it is a valid suffix. */ |
5512 | } | |
40fb9820 | 5513 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
5514 | /* Do nothing if the instruction is going to ignore the prefix. */ |
5515 | ; | |
5516 | else | |
5517 | abort (); | |
5518 | } | |
40fb9820 | 5519 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
5520 | && !i.suffix |
5521 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 5522 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
5523 | { |
5524 | i.suffix = stackop_size; | |
5525 | } | |
9306ca4a JB |
5526 | else if (intel_syntax |
5527 | && !i.suffix | |
40fb9820 L |
5528 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
5529 | || i.tm.opcode_modifier.jumpbyte | |
5530 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
5531 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
5532 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
5533 | { |
5534 | switch (flag_code) | |
5535 | { | |
5536 | case CODE_64BIT: | |
40fb9820 | 5537 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
5538 | { |
5539 | i.suffix = QWORD_MNEM_SUFFIX; | |
5540 | break; | |
5541 | } | |
1a0670f3 | 5542 | /* Fall through. */ |
9306ca4a | 5543 | case CODE_32BIT: |
40fb9820 | 5544 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
5545 | i.suffix = LONG_MNEM_SUFFIX; |
5546 | break; | |
5547 | case CODE_16BIT: | |
40fb9820 | 5548 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
5549 | i.suffix = WORD_MNEM_SUFFIX; |
5550 | break; | |
5551 | } | |
5552 | } | |
252b5132 | 5553 | |
9306ca4a | 5554 | if (!i.suffix) |
29b0f896 | 5555 | { |
9306ca4a JB |
5556 | if (!intel_syntax) |
5557 | { | |
40fb9820 | 5558 | if (i.tm.opcode_modifier.w) |
9306ca4a | 5559 | { |
4eed87de AM |
5560 | as_bad (_("no instruction mnemonic suffix given and " |
5561 | "no register operands; can't size instruction")); | |
9306ca4a JB |
5562 | return 0; |
5563 | } | |
5564 | } | |
5565 | else | |
5566 | { | |
40fb9820 | 5567 | unsigned int suffixes; |
7ab9ffdd | 5568 | |
40fb9820 L |
5569 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
5570 | if (!i.tm.opcode_modifier.no_wsuf) | |
5571 | suffixes |= 1 << 1; | |
5572 | if (!i.tm.opcode_modifier.no_lsuf) | |
5573 | suffixes |= 1 << 2; | |
fc4adea1 | 5574 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
5575 | suffixes |= 1 << 3; |
5576 | if (!i.tm.opcode_modifier.no_ssuf) | |
5577 | suffixes |= 1 << 4; | |
c2b9da16 | 5578 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
5579 | suffixes |= 1 << 5; |
5580 | ||
5581 | /* There are more than suffix matches. */ | |
5582 | if (i.tm.opcode_modifier.w | |
9306ca4a | 5583 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
5584 | && !i.tm.opcode_modifier.defaultsize |
5585 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
5586 | { |
5587 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
5588 | return 0; | |
5589 | } | |
5590 | } | |
29b0f896 | 5591 | } |
252b5132 | 5592 | |
9306ca4a JB |
5593 | /* Change the opcode based on the operand size given by i.suffix; |
5594 | We don't need to change things for byte insns. */ | |
5595 | ||
582d5edd L |
5596 | if (i.suffix |
5597 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 | 5598 | && i.suffix != XMMWORD_MNEM_SUFFIX |
43234a1e L |
5599 | && i.suffix != YMMWORD_MNEM_SUFFIX |
5600 | && i.suffix != ZMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
5601 | { |
5602 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 5603 | if (i.tm.opcode_modifier.w) |
29b0f896 | 5604 | { |
40fb9820 | 5605 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
5606 | i.tm.base_opcode |= 8; |
5607 | else | |
5608 | i.tm.base_opcode |= 1; | |
5609 | } | |
0f3f3d8b | 5610 | |
29b0f896 AM |
5611 | /* Now select between word & dword operations via the operand |
5612 | size prefix, except for instructions that will ignore this | |
5613 | prefix anyway. */ | |
ca61edf2 | 5614 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 5615 | { |
ca61edf2 L |
5616 | /* The address size override prefix changes the size of the |
5617 | first operand. */ | |
40fb9820 | 5618 | if ((flag_code == CODE_32BIT |
dc821c5f | 5619 | && i.op->regs[0].reg_type.bitfield.word) |
40fb9820 | 5620 | || (flag_code != CODE_32BIT |
dc821c5f | 5621 | && i.op->regs[0].reg_type.bitfield.dword)) |
cb712a9e L |
5622 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
5623 | return 0; | |
5624 | } | |
5625 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
5626 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
5627 | && !i.tm.opcode_modifier.ignoresize |
5628 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
5629 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
5630 | || (flag_code == CODE_64BIT | |
40fb9820 | 5631 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
5632 | { |
5633 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 5634 | |
40fb9820 | 5635 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 5636 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 5637 | |
29b0f896 AM |
5638 | if (!add_prefix (prefix)) |
5639 | return 0; | |
24eab124 | 5640 | } |
252b5132 | 5641 | |
29b0f896 AM |
5642 | /* Set mode64 for an operand. */ |
5643 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 5644 | && flag_code == CODE_64BIT |
40fb9820 | 5645 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
5646 | { |
5647 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
5648 | need rex64. cmpxchg8b is also a special case. */ |
5649 | if (! (i.operands == 2 | |
5650 | && i.tm.base_opcode == 0x90 | |
5651 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
5652 | && operand_type_equal (&i.types [0], &acc64) |
5653 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
5654 | && ! (i.operands == 1 |
5655 | && i.tm.base_opcode == 0xfc7 | |
5656 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
5657 | && !operand_type_check (i.types [0], reg) |
5658 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 5659 | i.rex |= REX_W; |
46e883c5 | 5660 | } |
3e73aa7c | 5661 | |
29b0f896 AM |
5662 | /* Size floating point instruction. */ |
5663 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 5664 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 5665 | i.tm.base_opcode ^= 4; |
29b0f896 | 5666 | } |
7ecd2f8b | 5667 | |
29b0f896 AM |
5668 | return 1; |
5669 | } | |
3e73aa7c | 5670 | |
29b0f896 | 5671 | static int |
543613e9 | 5672 | check_byte_reg (void) |
29b0f896 AM |
5673 | { |
5674 | int op; | |
543613e9 | 5675 | |
29b0f896 AM |
5676 | for (op = i.operands; --op >= 0;) |
5677 | { | |
dc821c5f JB |
5678 | /* Skip non-register operands. */ |
5679 | if (!i.types[op].bitfield.reg) | |
5680 | continue; | |
5681 | ||
29b0f896 AM |
5682 | /* If this is an eight bit register, it's OK. If it's the 16 or |
5683 | 32 bit version of an eight bit register, we will just use the | |
5684 | low portion, and that's OK too. */ | |
dc821c5f | 5685 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
5686 | continue; |
5687 | ||
5a819eb9 JB |
5688 | /* I/O port address operands are OK too. */ |
5689 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
5690 | continue; | |
5691 | ||
9344ff29 L |
5692 | /* crc32 doesn't generate this warning. */ |
5693 | if (i.tm.base_opcode == 0xf20f38f0) | |
5694 | continue; | |
5695 | ||
dc821c5f JB |
5696 | if ((i.types[op].bitfield.word |
5697 | || i.types[op].bitfield.dword | |
5698 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
5699 | && i.op[op].regs->reg_num < 4 |
5700 | /* Prohibit these changes in 64bit mode, since the lowering | |
5701 | would be more complicated. */ | |
5702 | && flag_code != CODE_64BIT) | |
29b0f896 | 5703 | { |
29b0f896 | 5704 | #if REGISTER_WARNINGS |
5a819eb9 | 5705 | if (!quiet_warnings) |
a540244d L |
5706 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5707 | register_prefix, | |
dc821c5f | 5708 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
5709 | ? REGNAM_AL - REGNAM_AX |
5710 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 5711 | register_prefix, |
29b0f896 AM |
5712 | i.op[op].regs->reg_name, |
5713 | i.suffix); | |
5714 | #endif | |
5715 | continue; | |
5716 | } | |
5717 | /* Any other register is bad. */ | |
dc821c5f | 5718 | if (i.types[op].bitfield.reg |
40fb9820 | 5719 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 5720 | || i.types[op].bitfield.regsimd |
40fb9820 L |
5721 | || i.types[op].bitfield.sreg2 |
5722 | || i.types[op].bitfield.sreg3 | |
5723 | || i.types[op].bitfield.control | |
5724 | || i.types[op].bitfield.debug | |
ca0d63fe | 5725 | || i.types[op].bitfield.test) |
29b0f896 | 5726 | { |
a540244d L |
5727 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5728 | register_prefix, | |
29b0f896 AM |
5729 | i.op[op].regs->reg_name, |
5730 | i.tm.name, | |
5731 | i.suffix); | |
5732 | return 0; | |
5733 | } | |
5734 | } | |
5735 | return 1; | |
5736 | } | |
5737 | ||
5738 | static int | |
e3bb37b5 | 5739 | check_long_reg (void) |
29b0f896 AM |
5740 | { |
5741 | int op; | |
5742 | ||
5743 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
5744 | /* Skip non-register operands. */ |
5745 | if (!i.types[op].bitfield.reg) | |
5746 | continue; | |
29b0f896 AM |
5747 | /* Reject eight bit registers, except where the template requires |
5748 | them. (eg. movzb) */ | |
dc821c5f JB |
5749 | else if (i.types[op].bitfield.byte |
5750 | && (i.tm.operand_types[op].bitfield.reg | |
5751 | || i.tm.operand_types[op].bitfield.acc) | |
5752 | && (i.tm.operand_types[op].bitfield.word | |
5753 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 5754 | { |
a540244d L |
5755 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5756 | register_prefix, | |
29b0f896 AM |
5757 | i.op[op].regs->reg_name, |
5758 | i.tm.name, | |
5759 | i.suffix); | |
5760 | return 0; | |
5761 | } | |
e4630f71 | 5762 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 5763 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
5764 | && i.types[op].bitfield.word |
5765 | && (i.tm.operand_types[op].bitfield.reg | |
5766 | || i.tm.operand_types[op].bitfield.acc) | |
5767 | && i.tm.operand_types[op].bitfield.dword) | |
29b0f896 AM |
5768 | { |
5769 | /* Prohibit these changes in the 64bit mode, since the | |
5770 | lowering is more complicated. */ | |
5771 | if (flag_code == CODE_64BIT) | |
252b5132 | 5772 | { |
2b5d6a91 | 5773 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 5774 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
5775 | i.suffix); |
5776 | return 0; | |
252b5132 | 5777 | } |
29b0f896 | 5778 | #if REGISTER_WARNINGS |
cecf1424 JB |
5779 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5780 | register_prefix, | |
5781 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
5782 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 5783 | #endif |
252b5132 | 5784 | } |
e4630f71 | 5785 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f JB |
5786 | else if (i.types[op].bitfield.qword |
5787 | && (i.tm.operand_types[op].bitfield.reg | |
5788 | || i.tm.operand_types[op].bitfield.acc) | |
5789 | && i.tm.operand_types[op].bitfield.dword) | |
252b5132 | 5790 | { |
34828aad | 5791 | if (intel_syntax |
ca61edf2 | 5792 | && i.tm.opcode_modifier.toqword |
1b54b8d7 | 5793 | && !i.types[0].bitfield.regsimd) |
34828aad | 5794 | { |
ca61edf2 | 5795 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
5796 | i.suffix = QWORD_MNEM_SUFFIX; |
5797 | } | |
5798 | else | |
5799 | { | |
2b5d6a91 | 5800 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
5801 | register_prefix, i.op[op].regs->reg_name, |
5802 | i.suffix); | |
5803 | return 0; | |
5804 | } | |
29b0f896 AM |
5805 | } |
5806 | return 1; | |
5807 | } | |
252b5132 | 5808 | |
29b0f896 | 5809 | static int |
e3bb37b5 | 5810 | check_qword_reg (void) |
29b0f896 AM |
5811 | { |
5812 | int op; | |
252b5132 | 5813 | |
29b0f896 | 5814 | for (op = i.operands; --op >= 0; ) |
dc821c5f JB |
5815 | /* Skip non-register operands. */ |
5816 | if (!i.types[op].bitfield.reg) | |
5817 | continue; | |
29b0f896 AM |
5818 | /* Reject eight bit registers, except where the template requires |
5819 | them. (eg. movzb) */ | |
dc821c5f JB |
5820 | else if (i.types[op].bitfield.byte |
5821 | && (i.tm.operand_types[op].bitfield.reg | |
5822 | || i.tm.operand_types[op].bitfield.acc) | |
5823 | && (i.tm.operand_types[op].bitfield.word | |
5824 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 5825 | { |
a540244d L |
5826 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5827 | register_prefix, | |
29b0f896 AM |
5828 | i.op[op].regs->reg_name, |
5829 | i.tm.name, | |
5830 | i.suffix); | |
5831 | return 0; | |
5832 | } | |
e4630f71 | 5833 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
5834 | else if ((i.types[op].bitfield.word |
5835 | || i.types[op].bitfield.dword) | |
5836 | && (i.tm.operand_types[op].bitfield.reg | |
5837 | || i.tm.operand_types[op].bitfield.acc) | |
5838 | && i.tm.operand_types[op].bitfield.qword) | |
29b0f896 AM |
5839 | { |
5840 | /* Prohibit these changes in the 64bit mode, since the | |
5841 | lowering is more complicated. */ | |
34828aad | 5842 | if (intel_syntax |
ca61edf2 | 5843 | && i.tm.opcode_modifier.todword |
1b54b8d7 | 5844 | && !i.types[0].bitfield.regsimd) |
34828aad | 5845 | { |
ca61edf2 | 5846 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
5847 | i.suffix = LONG_MNEM_SUFFIX; |
5848 | } | |
5849 | else | |
5850 | { | |
2b5d6a91 | 5851 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
5852 | register_prefix, i.op[op].regs->reg_name, |
5853 | i.suffix); | |
5854 | return 0; | |
5855 | } | |
252b5132 | 5856 | } |
29b0f896 AM |
5857 | return 1; |
5858 | } | |
252b5132 | 5859 | |
29b0f896 | 5860 | static int |
e3bb37b5 | 5861 | check_word_reg (void) |
29b0f896 AM |
5862 | { |
5863 | int op; | |
5864 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
5865 | /* Skip non-register operands. */ |
5866 | if (!i.types[op].bitfield.reg) | |
5867 | continue; | |
29b0f896 AM |
5868 | /* Reject eight bit registers, except where the template requires |
5869 | them. (eg. movzb) */ | |
dc821c5f JB |
5870 | else if (i.types[op].bitfield.byte |
5871 | && (i.tm.operand_types[op].bitfield.reg | |
5872 | || i.tm.operand_types[op].bitfield.acc) | |
5873 | && (i.tm.operand_types[op].bitfield.word | |
5874 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 5875 | { |
a540244d L |
5876 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5877 | register_prefix, | |
29b0f896 AM |
5878 | i.op[op].regs->reg_name, |
5879 | i.tm.name, | |
5880 | i.suffix); | |
5881 | return 0; | |
5882 | } | |
e4630f71 | 5883 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 5884 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
5885 | && (i.types[op].bitfield.dword |
5886 | || i.types[op].bitfield.qword) | |
5887 | && (i.tm.operand_types[op].bitfield.reg | |
5888 | || i.tm.operand_types[op].bitfield.acc) | |
5889 | && i.tm.operand_types[op].bitfield.word) | |
252b5132 | 5890 | { |
29b0f896 AM |
5891 | /* Prohibit these changes in the 64bit mode, since the |
5892 | lowering is more complicated. */ | |
5893 | if (flag_code == CODE_64BIT) | |
252b5132 | 5894 | { |
2b5d6a91 | 5895 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 5896 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
5897 | i.suffix); |
5898 | return 0; | |
252b5132 | 5899 | } |
29b0f896 | 5900 | #if REGISTER_WARNINGS |
cecf1424 JB |
5901 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5902 | register_prefix, | |
5903 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
5904 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
5905 | #endif |
5906 | } | |
5907 | return 1; | |
5908 | } | |
252b5132 | 5909 | |
29b0f896 | 5910 | static int |
40fb9820 | 5911 | update_imm (unsigned int j) |
29b0f896 | 5912 | { |
bc0844ae | 5913 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
5914 | if ((overlap.bitfield.imm8 |
5915 | || overlap.bitfield.imm8s | |
5916 | || overlap.bitfield.imm16 | |
5917 | || overlap.bitfield.imm32 | |
5918 | || overlap.bitfield.imm32s | |
5919 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
5920 | && !operand_type_equal (&overlap, &imm8) |
5921 | && !operand_type_equal (&overlap, &imm8s) | |
5922 | && !operand_type_equal (&overlap, &imm16) | |
5923 | && !operand_type_equal (&overlap, &imm32) | |
5924 | && !operand_type_equal (&overlap, &imm32s) | |
5925 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
5926 | { |
5927 | if (i.suffix) | |
5928 | { | |
40fb9820 L |
5929 | i386_operand_type temp; |
5930 | ||
0dfbf9d7 | 5931 | operand_type_set (&temp, 0); |
7ab9ffdd | 5932 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
5933 | { |
5934 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
5935 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
5936 | } | |
5937 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5938 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
5939 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5940 | { | |
5941 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
5942 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
5943 | } | |
5944 | else | |
5945 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
5946 | overlap = temp; | |
29b0f896 | 5947 | } |
0dfbf9d7 L |
5948 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
5949 | || operand_type_equal (&overlap, &imm16_32) | |
5950 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 5951 | { |
40fb9820 | 5952 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 5953 | overlap = imm16; |
40fb9820 | 5954 | else |
65da13b5 | 5955 | overlap = imm32s; |
29b0f896 | 5956 | } |
0dfbf9d7 L |
5957 | if (!operand_type_equal (&overlap, &imm8) |
5958 | && !operand_type_equal (&overlap, &imm8s) | |
5959 | && !operand_type_equal (&overlap, &imm16) | |
5960 | && !operand_type_equal (&overlap, &imm32) | |
5961 | && !operand_type_equal (&overlap, &imm32s) | |
5962 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 5963 | { |
4eed87de AM |
5964 | as_bad (_("no instruction mnemonic suffix given; " |
5965 | "can't determine immediate size")); | |
29b0f896 AM |
5966 | return 0; |
5967 | } | |
5968 | } | |
40fb9820 | 5969 | i.types[j] = overlap; |
29b0f896 | 5970 | |
40fb9820 L |
5971 | return 1; |
5972 | } | |
5973 | ||
5974 | static int | |
5975 | finalize_imm (void) | |
5976 | { | |
bc0844ae | 5977 | unsigned int j, n; |
29b0f896 | 5978 | |
bc0844ae L |
5979 | /* Update the first 2 immediate operands. */ |
5980 | n = i.operands > 2 ? 2 : i.operands; | |
5981 | if (n) | |
5982 | { | |
5983 | for (j = 0; j < n; j++) | |
5984 | if (update_imm (j) == 0) | |
5985 | return 0; | |
40fb9820 | 5986 | |
bc0844ae L |
5987 | /* The 3rd operand can't be immediate operand. */ |
5988 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
5989 | } | |
29b0f896 AM |
5990 | |
5991 | return 1; | |
5992 | } | |
5993 | ||
5994 | static int | |
e3bb37b5 | 5995 | process_operands (void) |
29b0f896 AM |
5996 | { |
5997 | /* Default segment register this instruction will use for memory | |
5998 | accesses. 0 means unknown. This is only for optimizing out | |
5999 | unnecessary segment overrides. */ | |
6000 | const seg_entry *default_seg = 0; | |
6001 | ||
2426c15f | 6002 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6003 | { |
91d6fa6a NC |
6004 | unsigned int dupl = i.operands; |
6005 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6006 | unsigned int j; |
6007 | ||
c0f3af97 | 6008 | /* The destination must be an xmm register. */ |
9c2799c2 | 6009 | gas_assert (i.reg_operands |
91d6fa6a | 6010 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6011 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6012 | |
1b54b8d7 JB |
6013 | if (i.tm.operand_types[0].bitfield.acc |
6014 | && i.tm.operand_types[0].bitfield.xmmword) | |
e2ec9d29 | 6015 | { |
8cd7925b | 6016 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6017 | { |
6018 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6019 | sources. */ | |
1b54b8d7 JB |
6020 | i.tm.operand_types[0].bitfield.acc = 0; |
6021 | i.tm.operand_types[0].bitfield.regsimd = 1; | |
c0f3af97 L |
6022 | goto duplicate; |
6023 | } | |
e2ec9d29 | 6024 | else |
c0f3af97 L |
6025 | { |
6026 | /* We remove the first xmm0 and keep the number of | |
6027 | operands unchanged, which in fact duplicates the | |
6028 | destination. */ | |
6029 | for (j = 1; j < i.operands; j++) | |
6030 | { | |
6031 | i.op[j - 1] = i.op[j]; | |
6032 | i.types[j - 1] = i.types[j]; | |
6033 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
6034 | } | |
6035 | } | |
6036 | } | |
6037 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6038 | { |
91d6fa6a | 6039 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6040 | && (i.tm.opcode_modifier.vexsources |
6041 | == VEX3SOURCES)); | |
c0f3af97 L |
6042 | |
6043 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6044 | and 3 sources. */ | |
6045 | for (j = i.operands; j > 0; j--) | |
6046 | { | |
6047 | i.op[j] = i.op[j - 1]; | |
6048 | i.types[j] = i.types[j - 1]; | |
6049 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
6050 | } | |
6051 | i.op[0].regs | |
6052 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6053 | i.types[0] = regxmm; |
c0f3af97 L |
6054 | i.tm.operand_types[0] = regxmm; |
6055 | ||
6056 | i.operands += 2; | |
6057 | i.reg_operands += 2; | |
6058 | i.tm.operands += 2; | |
6059 | ||
91d6fa6a | 6060 | dupl++; |
c0f3af97 | 6061 | dest++; |
91d6fa6a NC |
6062 | i.op[dupl] = i.op[dest]; |
6063 | i.types[dupl] = i.types[dest]; | |
6064 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 6065 | } |
c0f3af97 L |
6066 | else |
6067 | { | |
6068 | duplicate: | |
6069 | i.operands++; | |
6070 | i.reg_operands++; | |
6071 | i.tm.operands++; | |
6072 | ||
91d6fa6a NC |
6073 | i.op[dupl] = i.op[dest]; |
6074 | i.types[dupl] = i.types[dest]; | |
6075 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
6076 | } |
6077 | ||
6078 | if (i.tm.opcode_modifier.immext) | |
6079 | process_immext (); | |
6080 | } | |
1b54b8d7 JB |
6081 | else if (i.tm.operand_types[0].bitfield.acc |
6082 | && i.tm.operand_types[0].bitfield.xmmword) | |
c0f3af97 L |
6083 | { |
6084 | unsigned int j; | |
6085 | ||
9fcfb3d7 L |
6086 | for (j = 1; j < i.operands; j++) |
6087 | { | |
6088 | i.op[j - 1] = i.op[j]; | |
6089 | i.types[j - 1] = i.types[j]; | |
6090 | ||
6091 | /* We need to adjust fields in i.tm since they are used by | |
6092 | build_modrm_byte. */ | |
6093 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
6094 | } | |
6095 | ||
e2ec9d29 L |
6096 | i.operands--; |
6097 | i.reg_operands--; | |
e2ec9d29 L |
6098 | i.tm.operands--; |
6099 | } | |
920d2ddc IT |
6100 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6101 | { | |
6102 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ | |
10c17abd | 6103 | gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); |
920d2ddc IT |
6104 | unsigned int regnum = register_number (i.op[1].regs); |
6105 | unsigned int first_reg_in_group = regnum & ~3; | |
6106 | unsigned int last_reg_in_group = first_reg_in_group + 3; | |
6107 | if (regnum != first_reg_in_group) { | |
6108 | as_warn (_("the second source register `%s%s' implicitly denotes" | |
6109 | " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"), | |
6110 | register_prefix, i.op[1].regs->reg_name, | |
6111 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6112 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6113 | i.tm.name); | |
6114 | } | |
6115 | } | |
e2ec9d29 L |
6116 | else if (i.tm.opcode_modifier.regkludge) |
6117 | { | |
6118 | /* The imul $imm, %reg instruction is converted into | |
6119 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6120 | is converted into xor %reg, %reg. */ | |
6121 | ||
6122 | unsigned int first_reg_op; | |
6123 | ||
6124 | if (operand_type_check (i.types[0], reg)) | |
6125 | first_reg_op = 0; | |
6126 | else | |
6127 | first_reg_op = 1; | |
6128 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6129 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6130 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6131 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6132 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6133 | i.operands++; | |
6134 | i.reg_operands++; | |
29b0f896 AM |
6135 | } |
6136 | ||
40fb9820 | 6137 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6138 | { |
40fb9820 L |
6139 | if (i.types[0].bitfield.sreg2 |
6140 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6141 | { |
4eed87de AM |
6142 | if (i.tm.base_opcode == POP_SEG_SHORT |
6143 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6144 | { |
a87af027 | 6145 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6146 | return 0; |
29b0f896 | 6147 | } |
4eed87de AM |
6148 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6149 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6150 | i.rex |= REX_B; |
4eed87de AM |
6151 | } |
6152 | else | |
6153 | { | |
7ab9ffdd | 6154 | /* The register or float register operand is in operand |
85f10a01 | 6155 | 0 or 1. */ |
40fb9820 | 6156 | unsigned int op; |
7ab9ffdd | 6157 | |
ca0d63fe | 6158 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte) |
7ab9ffdd L |
6159 | || operand_type_check (i.types[0], reg)) |
6160 | op = 0; | |
6161 | else | |
6162 | op = 1; | |
4eed87de AM |
6163 | /* Register goes in low 3 bits of opcode. */ |
6164 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6165 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6166 | i.rex |= REX_B; |
40fb9820 | 6167 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6168 | { |
4eed87de AM |
6169 | /* Warn about some common errors, but press on regardless. |
6170 | The first case can be generated by gcc (<= 2.8.1). */ | |
6171 | if (i.operands == 2) | |
6172 | { | |
6173 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6174 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6175 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6176 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6177 | } |
6178 | else | |
6179 | { | |
6180 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6181 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6182 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6183 | } |
29b0f896 AM |
6184 | } |
6185 | } | |
6186 | } | |
40fb9820 | 6187 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6188 | { |
6189 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6190 | must be put into the modrm byte). Now, we make the modrm and |
6191 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6192 | |
6193 | default_seg = build_modrm_byte (); | |
6194 | } | |
8a2ed489 | 6195 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6196 | { |
6197 | default_seg = &ds; | |
6198 | } | |
40fb9820 | 6199 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6200 | { |
6201 | /* For the string instructions that allow a segment override | |
6202 | on one of their operands, the default segment is ds. */ | |
6203 | default_seg = &ds; | |
6204 | } | |
6205 | ||
75178d9d L |
6206 | if (i.tm.base_opcode == 0x8d /* lea */ |
6207 | && i.seg[0] | |
6208 | && !quiet_warnings) | |
30123838 | 6209 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6210 | |
6211 | /* If a segment was explicitly specified, and the specified segment | |
6212 | is not the default, use an opcode prefix to select it. If we | |
6213 | never figured out what the default segment is, then default_seg | |
6214 | will be zero at this point, and the specified segment prefix will | |
6215 | always be used. */ | |
29b0f896 AM |
6216 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6217 | { | |
6218 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6219 | return 0; | |
6220 | } | |
6221 | return 1; | |
6222 | } | |
6223 | ||
6224 | static const seg_entry * | |
e3bb37b5 | 6225 | build_modrm_byte (void) |
29b0f896 AM |
6226 | { |
6227 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6228 | unsigned int source, dest; |
8cd7925b | 6229 | int vex_3_sources; |
c0f3af97 L |
6230 | |
6231 | /* The first operand of instructions with VEX prefix and 3 sources | |
6232 | must be VEX_Imm4. */ | |
8cd7925b | 6233 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6234 | if (vex_3_sources) |
6235 | { | |
91d6fa6a | 6236 | unsigned int nds, reg_slot; |
4c2c6516 | 6237 | expressionS *exp; |
c0f3af97 | 6238 | |
922d8de8 | 6239 | if (i.tm.opcode_modifier.veximmext |
a683cc34 SP |
6240 | && i.tm.opcode_modifier.immext) |
6241 | { | |
6242 | dest = i.operands - 2; | |
6243 | gas_assert (dest == 3); | |
6244 | } | |
922d8de8 | 6245 | else |
a683cc34 | 6246 | dest = i.operands - 1; |
c0f3af97 | 6247 | nds = dest - 1; |
922d8de8 | 6248 | |
a683cc34 SP |
6249 | /* There are 2 kinds of instructions: |
6250 | 1. 5 operands: 4 register operands or 3 register operands | |
6251 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
43234a1e L |
6252 | VexW0 or VexW1. The destination must be either XMM, YMM or |
6253 | ZMM register. | |
a683cc34 SP |
6254 | 2. 4 operands: 4 register operands or 3 register operands |
6255 | plus 1 memory operand, VexXDS, and VexImmExt */ | |
922d8de8 | 6256 | gas_assert ((i.reg_operands == 4 |
a683cc34 SP |
6257 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
6258 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
6259 | && (i.tm.opcode_modifier.veximmext | |
6260 | || (i.imm_operands == 1 | |
6261 | && i.types[0].bitfield.vec_imm4 | |
6262 | && (i.tm.opcode_modifier.vexw == VEXW0 | |
6263 | || i.tm.opcode_modifier.vexw == VEXW1) | |
10c17abd | 6264 | && i.tm.operand_types[dest].bitfield.regsimd))); |
a683cc34 SP |
6265 | |
6266 | if (i.imm_operands == 0) | |
6267 | { | |
6268 | /* When there is no immediate operand, generate an 8bit | |
6269 | immediate operand to encode the first operand. */ | |
6270 | exp = &im_expressions[i.imm_operands++]; | |
6271 | i.op[i.operands].imms = exp; | |
6272 | i.types[i.operands] = imm8; | |
6273 | i.operands++; | |
6274 | /* If VexW1 is set, the first operand is the source and | |
6275 | the second operand is encoded in the immediate operand. */ | |
6276 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
6277 | { | |
6278 | source = 0; | |
6279 | reg_slot = 1; | |
6280 | } | |
6281 | else | |
6282 | { | |
6283 | source = 1; | |
6284 | reg_slot = 0; | |
6285 | } | |
6286 | ||
6287 | /* FMA swaps REG and NDS. */ | |
6288 | if (i.tm.cpu_flags.bitfield.cpufma) | |
6289 | { | |
6290 | unsigned int tmp; | |
6291 | tmp = reg_slot; | |
6292 | reg_slot = nds; | |
6293 | nds = tmp; | |
6294 | } | |
6295 | ||
10c17abd | 6296 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); |
a683cc34 | 6297 | exp->X_op = O_constant; |
4c692bc7 | 6298 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
43234a1e L |
6299 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
6300 | } | |
922d8de8 | 6301 | else |
a683cc34 SP |
6302 | { |
6303 | unsigned int imm_slot; | |
6304 | ||
6305 | if (i.tm.opcode_modifier.vexw == VEXW0) | |
6306 | { | |
6307 | /* If VexW0 is set, the third operand is the source and | |
6308 | the second operand is encoded in the immediate | |
6309 | operand. */ | |
6310 | source = 2; | |
6311 | reg_slot = 1; | |
6312 | } | |
6313 | else | |
6314 | { | |
6315 | /* VexW1 is set, the second operand is the source and | |
6316 | the third operand is encoded in the immediate | |
6317 | operand. */ | |
6318 | source = 1; | |
6319 | reg_slot = 2; | |
6320 | } | |
6321 | ||
6322 | if (i.tm.opcode_modifier.immext) | |
6323 | { | |
33eaf5de | 6324 | /* When ImmExt is set, the immediate byte is the last |
a683cc34 SP |
6325 | operand. */ |
6326 | imm_slot = i.operands - 1; | |
6327 | source--; | |
6328 | reg_slot--; | |
6329 | } | |
6330 | else | |
6331 | { | |
6332 | imm_slot = 0; | |
6333 | ||
6334 | /* Turn on Imm8 so that output_imm will generate it. */ | |
6335 | i.types[imm_slot].bitfield.imm8 = 1; | |
6336 | } | |
6337 | ||
10c17abd | 6338 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); |
a683cc34 | 6339 | i.op[imm_slot].imms->X_add_number |
4c692bc7 | 6340 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 6341 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
a683cc34 SP |
6342 | } |
6343 | ||
10c17abd | 6344 | gas_assert (i.tm.operand_types[nds].bitfield.regsimd); |
dae39acc | 6345 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
6346 | } |
6347 | else | |
6348 | source = dest = 0; | |
29b0f896 AM |
6349 | |
6350 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
6351 | implicit registers do not count. If there are 3 register |
6352 | operands, it must be a instruction with VexNDS. For a | |
6353 | instruction with VexNDD, the destination register is encoded | |
6354 | in VEX prefix. If there are 4 register operands, it must be | |
6355 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
6356 | if (i.mem_operands == 0 |
6357 | && ((i.reg_operands == 2 | |
2426c15f | 6358 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 6359 | || (i.reg_operands == 3 |
2426c15f | 6360 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 6361 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 6362 | { |
cab737b9 L |
6363 | switch (i.operands) |
6364 | { | |
6365 | case 2: | |
6366 | source = 0; | |
6367 | break; | |
6368 | case 3: | |
c81128dc L |
6369 | /* When there are 3 operands, one of them may be immediate, |
6370 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
6371 | the first operand must be shift count register (cl) or it |
6372 | is an instruction with VexNDS. */ | |
9c2799c2 | 6373 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 6374 | || (i.imm_operands == 0 |
2426c15f | 6375 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 6376 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
6377 | if (operand_type_check (i.types[0], imm) |
6378 | || i.types[0].bitfield.shiftcount) | |
6379 | source = 1; | |
6380 | else | |
6381 | source = 0; | |
cab737b9 L |
6382 | break; |
6383 | case 4: | |
368d64cc L |
6384 | /* When there are 4 operands, the first two must be 8bit |
6385 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
6386 | one. |
6387 | ||
6388 | For instructions with VexNDS, if the first operand | |
6389 | an imm8, the source operand is the 2nd one. If the last | |
6390 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 6391 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
6392 | && i.types[0].bitfield.imm8 |
6393 | && i.types[1].bitfield.imm8) | |
2426c15f | 6394 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
6395 | && i.imm_operands == 1 |
6396 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
6397 | || i.types[i.operands - 1].bitfield.imm8 |
6398 | || i.rounding))); | |
9f2670f2 L |
6399 | if (i.imm_operands == 2) |
6400 | source = 2; | |
6401 | else | |
c0f3af97 L |
6402 | { |
6403 | if (i.types[0].bitfield.imm8) | |
6404 | source = 1; | |
6405 | else | |
6406 | source = 0; | |
6407 | } | |
c0f3af97 L |
6408 | break; |
6409 | case 5: | |
43234a1e L |
6410 | if (i.tm.opcode_modifier.evex) |
6411 | { | |
6412 | /* For EVEX instructions, when there are 5 operands, the | |
6413 | first one must be immediate operand. If the second one | |
6414 | is immediate operand, the source operand is the 3th | |
6415 | one. If the last one is immediate operand, the source | |
6416 | operand is the 2nd one. */ | |
6417 | gas_assert (i.imm_operands == 2 | |
6418 | && i.tm.opcode_modifier.sae | |
6419 | && operand_type_check (i.types[0], imm)); | |
6420 | if (operand_type_check (i.types[1], imm)) | |
6421 | source = 2; | |
6422 | else if (operand_type_check (i.types[4], imm)) | |
6423 | source = 1; | |
6424 | else | |
6425 | abort (); | |
6426 | } | |
cab737b9 L |
6427 | break; |
6428 | default: | |
6429 | abort (); | |
6430 | } | |
6431 | ||
c0f3af97 L |
6432 | if (!vex_3_sources) |
6433 | { | |
6434 | dest = source + 1; | |
6435 | ||
43234a1e L |
6436 | /* RC/SAE operand could be between DEST and SRC. That happens |
6437 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
6438 | register. */ | |
6439 | if (i.rounding && i.rounding->operand == (int) dest) | |
6440 | dest++; | |
6441 | ||
2426c15f | 6442 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 6443 | { |
43234a1e | 6444 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 6445 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
43234a1e L |
6446 | register. It is encoded in VEX prefix. We need to |
6447 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
6448 | |
6449 | i386_operand_type op; | |
6450 | unsigned int vvvv; | |
6451 | ||
6452 | /* Check register-only source operand when two source | |
6453 | operands are swapped. */ | |
6454 | if (!i.tm.operand_types[source].bitfield.baseindex | |
6455 | && i.tm.operand_types[dest].bitfield.baseindex) | |
6456 | { | |
6457 | vvvv = source; | |
6458 | source = dest; | |
6459 | } | |
6460 | else | |
6461 | vvvv = dest; | |
6462 | ||
6463 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 6464 | op.bitfield.regmem = 0; |
c0f3af97 | 6465 | if ((dest + 1) >= i.operands |
dc821c5f JB |
6466 | || ((!op.bitfield.reg |
6467 | || (!op.bitfield.dword && !op.bitfield.qword)) | |
10c17abd | 6468 | && !op.bitfield.regsimd |
43234a1e | 6469 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 6470 | abort (); |
f12dc422 | 6471 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
6472 | dest++; |
6473 | } | |
6474 | } | |
29b0f896 AM |
6475 | |
6476 | i.rm.mode = 3; | |
6477 | /* One of the register operands will be encoded in the i.tm.reg | |
6478 | field, the other in the combined i.tm.mode and i.tm.regmem | |
6479 | fields. If no form of this instruction supports a memory | |
6480 | destination operand, then we assume the source operand may | |
6481 | sometimes be a memory operand and so we need to store the | |
6482 | destination in the i.rm.reg field. */ | |
40fb9820 L |
6483 | if (!i.tm.operand_types[dest].bitfield.regmem |
6484 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
6485 | { |
6486 | i.rm.reg = i.op[dest].regs->reg_num; | |
6487 | i.rm.regmem = i.op[source].regs->reg_num; | |
6488 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6489 | i.rex |= REX_R; |
43234a1e L |
6490 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6491 | i.vrex |= REX_R; | |
29b0f896 | 6492 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6493 | i.rex |= REX_B; |
43234a1e L |
6494 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6495 | i.vrex |= REX_B; | |
29b0f896 AM |
6496 | } |
6497 | else | |
6498 | { | |
6499 | i.rm.reg = i.op[source].regs->reg_num; | |
6500 | i.rm.regmem = i.op[dest].regs->reg_num; | |
6501 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6502 | i.rex |= REX_B; |
43234a1e L |
6503 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6504 | i.vrex |= REX_B; | |
29b0f896 | 6505 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6506 | i.rex |= REX_R; |
43234a1e L |
6507 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6508 | i.vrex |= REX_R; | |
29b0f896 | 6509 | } |
161a04f6 | 6510 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 6511 | { |
40fb9820 L |
6512 | if (!i.types[0].bitfield.control |
6513 | && !i.types[1].bitfield.control) | |
c4a530c5 | 6514 | abort (); |
161a04f6 | 6515 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
6516 | add_prefix (LOCK_PREFIX_OPCODE); |
6517 | } | |
29b0f896 AM |
6518 | } |
6519 | else | |
6520 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
6521 | unsigned int mem; |
6522 | ||
29b0f896 AM |
6523 | if (i.mem_operands) |
6524 | { | |
6525 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 6526 | unsigned int op; |
4eed87de | 6527 | |
7ab9ffdd L |
6528 | for (op = 0; op < i.operands; op++) |
6529 | if (operand_type_check (i.types[op], anymem)) | |
6530 | break; | |
7ab9ffdd | 6531 | gas_assert (op < i.operands); |
29b0f896 | 6532 | |
6c30d220 L |
6533 | if (i.tm.opcode_modifier.vecsib) |
6534 | { | |
6535 | if (i.index_reg->reg_num == RegEiz | |
6536 | || i.index_reg->reg_num == RegRiz) | |
6537 | abort (); | |
6538 | ||
6539 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6540 | if (!i.base_reg) | |
6541 | { | |
6542 | i.sib.base = NO_BASE_REGISTER; | |
6543 | i.sib.scale = i.log2_scale_factor; | |
6544 | i.types[op].bitfield.disp8 = 0; | |
6545 | i.types[op].bitfield.disp16 = 0; | |
6546 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 6547 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
6548 | { |
6549 | /* Must be 32 bit */ | |
6550 | i.types[op].bitfield.disp32 = 1; | |
6551 | i.types[op].bitfield.disp32s = 0; | |
6552 | } | |
6553 | else | |
6554 | { | |
6555 | i.types[op].bitfield.disp32 = 0; | |
6556 | i.types[op].bitfield.disp32s = 1; | |
6557 | } | |
6558 | } | |
6559 | i.sib.index = i.index_reg->reg_num; | |
6560 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
6561 | i.rex |= REX_X; | |
43234a1e L |
6562 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
6563 | i.vrex |= REX_X; | |
6c30d220 L |
6564 | } |
6565 | ||
29b0f896 AM |
6566 | default_seg = &ds; |
6567 | ||
6568 | if (i.base_reg == 0) | |
6569 | { | |
6570 | i.rm.mode = 0; | |
6571 | if (!i.disp_operands) | |
9bb129e8 | 6572 | fake_zero_displacement = 1; |
29b0f896 AM |
6573 | if (i.index_reg == 0) |
6574 | { | |
6c30d220 | 6575 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6576 | /* Operand is just <disp> */ |
20f0a1fc | 6577 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
6578 | { |
6579 | /* 64bit mode overwrites the 32bit absolute | |
6580 | addressing by RIP relative addressing and | |
6581 | absolute addressing is encoded by one of the | |
6582 | redundant SIB forms. */ | |
6583 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6584 | i.sib.base = NO_BASE_REGISTER; | |
6585 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 6586 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 6587 | ? disp32s : disp32); |
20f0a1fc | 6588 | } |
fc225355 L |
6589 | else if ((flag_code == CODE_16BIT) |
6590 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
6591 | { |
6592 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 6593 | i.types[op] = disp16; |
20f0a1fc NC |
6594 | } |
6595 | else | |
6596 | { | |
6597 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 6598 | i.types[op] = disp32; |
29b0f896 AM |
6599 | } |
6600 | } | |
6c30d220 | 6601 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6602 | { |
6c30d220 | 6603 | /* !i.base_reg && i.index_reg */ |
db51cc60 L |
6604 | if (i.index_reg->reg_num == RegEiz |
6605 | || i.index_reg->reg_num == RegRiz) | |
6606 | i.sib.index = NO_INDEX_REGISTER; | |
6607 | else | |
6608 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6609 | i.sib.base = NO_BASE_REGISTER; |
6610 | i.sib.scale = i.log2_scale_factor; | |
6611 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
6612 | i.types[op].bitfield.disp8 = 0; |
6613 | i.types[op].bitfield.disp16 = 0; | |
6614 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 6615 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
6616 | { |
6617 | /* Must be 32 bit */ | |
6618 | i.types[op].bitfield.disp32 = 1; | |
6619 | i.types[op].bitfield.disp32s = 0; | |
6620 | } | |
29b0f896 | 6621 | else |
40fb9820 L |
6622 | { |
6623 | i.types[op].bitfield.disp32 = 0; | |
6624 | i.types[op].bitfield.disp32s = 1; | |
6625 | } | |
29b0f896 | 6626 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6627 | i.rex |= REX_X; |
29b0f896 AM |
6628 | } |
6629 | } | |
6630 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
6631 | else if (i.base_reg->reg_num == RegRip || |
6632 | i.base_reg->reg_num == RegEip) | |
29b0f896 | 6633 | { |
6c30d220 | 6634 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6635 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
6636 | i.types[op].bitfield.disp8 = 0; |
6637 | i.types[op].bitfield.disp16 = 0; | |
6638 | i.types[op].bitfield.disp32 = 0; | |
6639 | i.types[op].bitfield.disp32s = 1; | |
6640 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 6641 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
6642 | if (! i.disp_operands) |
6643 | fake_zero_displacement = 1; | |
29b0f896 | 6644 | } |
dc821c5f | 6645 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 6646 | { |
6c30d220 | 6647 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6648 | switch (i.base_reg->reg_num) |
6649 | { | |
6650 | case 3: /* (%bx) */ | |
6651 | if (i.index_reg == 0) | |
6652 | i.rm.regmem = 7; | |
6653 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
6654 | i.rm.regmem = i.index_reg->reg_num - 6; | |
6655 | break; | |
6656 | case 5: /* (%bp) */ | |
6657 | default_seg = &ss; | |
6658 | if (i.index_reg == 0) | |
6659 | { | |
6660 | i.rm.regmem = 6; | |
40fb9820 | 6661 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
6662 | { |
6663 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 6664 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 6665 | fake_zero_displacement = 1; |
29b0f896 AM |
6666 | } |
6667 | } | |
6668 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
6669 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
6670 | break; | |
6671 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
6672 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
6673 | } | |
6674 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6675 | } | |
6676 | else /* i.base_reg and 32/64 bit mode */ | |
6677 | { | |
6678 | if (flag_code == CODE_64BIT | |
40fb9820 L |
6679 | && operand_type_check (i.types[op], disp)) |
6680 | { | |
6681 | i386_operand_type temp; | |
0dfbf9d7 | 6682 | operand_type_set (&temp, 0); |
40fb9820 L |
6683 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
6684 | i.types[op] = temp; | |
6685 | if (i.prefix[ADDR_PREFIX] == 0) | |
6686 | i.types[op].bitfield.disp32s = 1; | |
6687 | else | |
6688 | i.types[op].bitfield.disp32 = 1; | |
6689 | } | |
20f0a1fc | 6690 | |
6c30d220 L |
6691 | if (!i.tm.opcode_modifier.vecsib) |
6692 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 6693 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6694 | i.rex |= REX_B; |
29b0f896 AM |
6695 | i.sib.base = i.base_reg->reg_num; |
6696 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
6697 | complications. */ | |
848930b2 JB |
6698 | if (!(i.base_reg->reg_flags & RegRex) |
6699 | && (i.base_reg->reg_num == EBP_REG_NUM | |
6700 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 6701 | default_seg = &ss; |
848930b2 | 6702 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 6703 | { |
848930b2 | 6704 | fake_zero_displacement = 1; |
b5014f7a | 6705 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
6706 | } |
6707 | i.sib.scale = i.log2_scale_factor; | |
6708 | if (i.index_reg == 0) | |
6709 | { | |
6c30d220 | 6710 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6711 | /* <disp>(%esp) becomes two byte modrm with no index |
6712 | register. We've already stored the code for esp | |
6713 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
6714 | Any base register besides %esp will not use the | |
6715 | extra modrm byte. */ | |
6716 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 6717 | } |
6c30d220 | 6718 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6719 | { |
db51cc60 L |
6720 | if (i.index_reg->reg_num == RegEiz |
6721 | || i.index_reg->reg_num == RegRiz) | |
6722 | i.sib.index = NO_INDEX_REGISTER; | |
6723 | else | |
6724 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6725 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
6726 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 6727 | i.rex |= REX_X; |
29b0f896 | 6728 | } |
67a4f2b7 AO |
6729 | |
6730 | if (i.disp_operands | |
6731 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
6732 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
6733 | i.rm.mode = 0; | |
6734 | else | |
a501d77e L |
6735 | { |
6736 | if (!fake_zero_displacement | |
6737 | && !i.disp_operands | |
6738 | && i.disp_encoding) | |
6739 | { | |
6740 | fake_zero_displacement = 1; | |
6741 | if (i.disp_encoding == disp_encoding_8bit) | |
6742 | i.types[op].bitfield.disp8 = 1; | |
6743 | else | |
6744 | i.types[op].bitfield.disp32 = 1; | |
6745 | } | |
6746 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6747 | } | |
29b0f896 | 6748 | } |
252b5132 | 6749 | |
29b0f896 AM |
6750 | if (fake_zero_displacement) |
6751 | { | |
6752 | /* Fakes a zero displacement assuming that i.types[op] | |
6753 | holds the correct displacement size. */ | |
6754 | expressionS *exp; | |
6755 | ||
9c2799c2 | 6756 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
6757 | exp = &disp_expressions[i.disp_operands++]; |
6758 | i.op[op].disps = exp; | |
6759 | exp->X_op = O_constant; | |
6760 | exp->X_add_number = 0; | |
6761 | exp->X_add_symbol = (symbolS *) 0; | |
6762 | exp->X_op_symbol = (symbolS *) 0; | |
6763 | } | |
c0f3af97 L |
6764 | |
6765 | mem = op; | |
29b0f896 | 6766 | } |
c0f3af97 L |
6767 | else |
6768 | mem = ~0; | |
252b5132 | 6769 | |
8c43a48b | 6770 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
6771 | { |
6772 | if (operand_type_check (i.types[0], imm)) | |
6773 | i.vex.register_specifier = NULL; | |
6774 | else | |
6775 | { | |
6776 | /* VEX.vvvv encodes one of the sources when the first | |
6777 | operand is not an immediate. */ | |
1ef99a7b | 6778 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
6779 | i.vex.register_specifier = i.op[0].regs; |
6780 | else | |
6781 | i.vex.register_specifier = i.op[1].regs; | |
6782 | } | |
6783 | ||
6784 | /* Destination is a XMM register encoded in the ModRM.reg | |
6785 | and VEX.R bit. */ | |
6786 | i.rm.reg = i.op[2].regs->reg_num; | |
6787 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
6788 | i.rex |= REX_R; | |
6789 | ||
6790 | /* ModRM.rm and VEX.B encodes the other source. */ | |
6791 | if (!i.mem_operands) | |
6792 | { | |
6793 | i.rm.mode = 3; | |
6794 | ||
1ef99a7b | 6795 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
6796 | i.rm.regmem = i.op[1].regs->reg_num; |
6797 | else | |
6798 | i.rm.regmem = i.op[0].regs->reg_num; | |
6799 | ||
6800 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
6801 | i.rex |= REX_B; | |
6802 | } | |
6803 | } | |
2426c15f | 6804 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
6805 | { |
6806 | i.vex.register_specifier = i.op[2].regs; | |
6807 | if (!i.mem_operands) | |
6808 | { | |
6809 | i.rm.mode = 3; | |
6810 | i.rm.regmem = i.op[1].regs->reg_num; | |
6811 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
6812 | i.rex |= REX_B; | |
6813 | } | |
6814 | } | |
29b0f896 AM |
6815 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
6816 | (if any) based on i.tm.extension_opcode. Again, we must be | |
6817 | careful to make sure that segment/control/debug/test/MMX | |
6818 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 6819 | else if (i.reg_operands) |
29b0f896 | 6820 | { |
99018f42 | 6821 | unsigned int op; |
7ab9ffdd L |
6822 | unsigned int vex_reg = ~0; |
6823 | ||
6824 | for (op = 0; op < i.operands; op++) | |
dc821c5f | 6825 | if (i.types[op].bitfield.reg |
7ab9ffdd | 6826 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 6827 | || i.types[op].bitfield.regsimd |
7e8b059b | 6828 | || i.types[op].bitfield.regbnd |
43234a1e | 6829 | || i.types[op].bitfield.regmask |
7ab9ffdd L |
6830 | || i.types[op].bitfield.sreg2 |
6831 | || i.types[op].bitfield.sreg3 | |
6832 | || i.types[op].bitfield.control | |
6833 | || i.types[op].bitfield.debug | |
6834 | || i.types[op].bitfield.test) | |
6835 | break; | |
c0209578 | 6836 | |
7ab9ffdd L |
6837 | if (vex_3_sources) |
6838 | op = dest; | |
2426c15f | 6839 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
6840 | { |
6841 | /* For instructions with VexNDS, the register-only | |
6842 | source operand is encoded in VEX prefix. */ | |
6843 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 6844 | |
7ab9ffdd | 6845 | if (op > mem) |
c0f3af97 | 6846 | { |
7ab9ffdd L |
6847 | vex_reg = op++; |
6848 | gas_assert (op < i.operands); | |
c0f3af97 L |
6849 | } |
6850 | else | |
c0f3af97 | 6851 | { |
f12dc422 L |
6852 | /* Check register-only source operand when two source |
6853 | operands are swapped. */ | |
6854 | if (!i.tm.operand_types[op].bitfield.baseindex | |
6855 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
6856 | { | |
6857 | vex_reg = op; | |
6858 | op += 2; | |
6859 | gas_assert (mem == (vex_reg + 1) | |
6860 | && op < i.operands); | |
6861 | } | |
6862 | else | |
6863 | { | |
6864 | vex_reg = op + 1; | |
6865 | gas_assert (vex_reg < i.operands); | |
6866 | } | |
c0f3af97 | 6867 | } |
7ab9ffdd | 6868 | } |
2426c15f | 6869 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 6870 | { |
f12dc422 | 6871 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 6872 | is encoded in VEX prefix. */ |
f12dc422 L |
6873 | if (i.mem_operands == 0) |
6874 | { | |
6875 | /* There is no memory operand. */ | |
6876 | gas_assert ((op + 2) == i.operands); | |
6877 | vex_reg = op + 1; | |
6878 | } | |
6879 | else | |
8d63c93e | 6880 | { |
f12dc422 L |
6881 | /* There are only 2 operands. */ |
6882 | gas_assert (op < 2 && i.operands == 2); | |
6883 | vex_reg = 1; | |
6884 | } | |
7ab9ffdd L |
6885 | } |
6886 | else | |
6887 | gas_assert (op < i.operands); | |
99018f42 | 6888 | |
7ab9ffdd L |
6889 | if (vex_reg != (unsigned int) ~0) |
6890 | { | |
f12dc422 | 6891 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 6892 | |
dc821c5f JB |
6893 | if ((!type->bitfield.reg |
6894 | || (!type->bitfield.dword && !type->bitfield.qword)) | |
10c17abd | 6895 | && !type->bitfield.regsimd |
43234a1e | 6896 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 6897 | abort (); |
f88c9eb0 | 6898 | |
7ab9ffdd L |
6899 | i.vex.register_specifier = i.op[vex_reg].regs; |
6900 | } | |
6901 | ||
1b9f0c97 L |
6902 | /* Don't set OP operand twice. */ |
6903 | if (vex_reg != op) | |
7ab9ffdd | 6904 | { |
1b9f0c97 L |
6905 | /* If there is an extension opcode to put here, the |
6906 | register number must be put into the regmem field. */ | |
6907 | if (i.tm.extension_opcode != None) | |
6908 | { | |
6909 | i.rm.regmem = i.op[op].regs->reg_num; | |
6910 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
6911 | i.rex |= REX_B; | |
43234a1e L |
6912 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
6913 | i.vrex |= REX_B; | |
1b9f0c97 L |
6914 | } |
6915 | else | |
6916 | { | |
6917 | i.rm.reg = i.op[op].regs->reg_num; | |
6918 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
6919 | i.rex |= REX_R; | |
43234a1e L |
6920 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
6921 | i.vrex |= REX_R; | |
1b9f0c97 | 6922 | } |
7ab9ffdd | 6923 | } |
252b5132 | 6924 | |
29b0f896 AM |
6925 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
6926 | must set it to 3 to indicate this is a register operand | |
6927 | in the regmem field. */ | |
6928 | if (!i.mem_operands) | |
6929 | i.rm.mode = 3; | |
6930 | } | |
252b5132 | 6931 | |
29b0f896 | 6932 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 6933 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
6934 | i.rm.reg = i.tm.extension_opcode; |
6935 | } | |
6936 | return default_seg; | |
6937 | } | |
252b5132 | 6938 | |
29b0f896 | 6939 | static void |
e3bb37b5 | 6940 | output_branch (void) |
29b0f896 AM |
6941 | { |
6942 | char *p; | |
f8a5c266 | 6943 | int size; |
29b0f896 AM |
6944 | int code16; |
6945 | int prefix; | |
6946 | relax_substateT subtype; | |
6947 | symbolS *sym; | |
6948 | offsetT off; | |
6949 | ||
f8a5c266 | 6950 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 6951 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
6952 | |
6953 | prefix = 0; | |
6954 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 6955 | { |
29b0f896 AM |
6956 | prefix = 1; |
6957 | i.prefixes -= 1; | |
6958 | code16 ^= CODE16; | |
252b5132 | 6959 | } |
29b0f896 AM |
6960 | /* Pentium4 branch hints. */ |
6961 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
6962 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 6963 | { |
29b0f896 AM |
6964 | prefix++; |
6965 | i.prefixes--; | |
6966 | } | |
6967 | if (i.prefix[REX_PREFIX] != 0) | |
6968 | { | |
6969 | prefix++; | |
6970 | i.prefixes--; | |
2f66722d AM |
6971 | } |
6972 | ||
7e8b059b L |
6973 | /* BND prefixed jump. */ |
6974 | if (i.prefix[BND_PREFIX] != 0) | |
6975 | { | |
6976 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
6977 | i.prefixes -= 1; | |
6978 | } | |
6979 | ||
29b0f896 AM |
6980 | if (i.prefixes != 0 && !intel_syntax) |
6981 | as_warn (_("skipping prefixes on this instruction")); | |
6982 | ||
6983 | /* It's always a symbol; End frag & setup for relax. | |
6984 | Make sure there is enough room in this frag for the largest | |
6985 | instruction we may generate in md_convert_frag. This is 2 | |
6986 | bytes for the opcode and room for the prefix and largest | |
6987 | displacement. */ | |
6988 | frag_grow (prefix + 2 + 4); | |
6989 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
6990 | p = frag_more (prefix + 1); | |
6991 | if (i.prefix[DATA_PREFIX] != 0) | |
6992 | *p++ = DATA_PREFIX_OPCODE; | |
6993 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
6994 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
6995 | *p++ = i.prefix[SEG_PREFIX]; | |
6996 | if (i.prefix[REX_PREFIX] != 0) | |
6997 | *p++ = i.prefix[REX_PREFIX]; | |
6998 | *p = i.tm.base_opcode; | |
6999 | ||
7000 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7001 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7002 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7003 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7004 | else |
f8a5c266 | 7005 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7006 | subtype |= code16; |
3e73aa7c | 7007 | |
29b0f896 AM |
7008 | sym = i.op[0].disps->X_add_symbol; |
7009 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7010 | |
29b0f896 AM |
7011 | if (i.op[0].disps->X_op != O_constant |
7012 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7013 | { |
29b0f896 AM |
7014 | /* Handle complex expressions. */ |
7015 | sym = make_expr_symbol (i.op[0].disps); | |
7016 | off = 0; | |
7017 | } | |
3e73aa7c | 7018 | |
29b0f896 AM |
7019 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7020 | Pass reloc in fr_var. */ | |
d258b828 | 7021 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7022 | } |
3e73aa7c | 7023 | |
29b0f896 | 7024 | static void |
e3bb37b5 | 7025 | output_jump (void) |
29b0f896 AM |
7026 | { |
7027 | char *p; | |
7028 | int size; | |
3e02c1cc | 7029 | fixS *fixP; |
29b0f896 | 7030 | |
40fb9820 | 7031 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7032 | { |
7033 | /* This is a loop or jecxz type instruction. */ | |
7034 | size = 1; | |
7035 | if (i.prefix[ADDR_PREFIX] != 0) | |
7036 | { | |
7037 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7038 | i.prefixes -= 1; | |
7039 | } | |
7040 | /* Pentium4 branch hints. */ | |
7041 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7042 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7043 | { | |
7044 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7045 | i.prefixes--; | |
3e73aa7c JH |
7046 | } |
7047 | } | |
29b0f896 AM |
7048 | else |
7049 | { | |
7050 | int code16; | |
3e73aa7c | 7051 | |
29b0f896 AM |
7052 | code16 = 0; |
7053 | if (flag_code == CODE_16BIT) | |
7054 | code16 = CODE16; | |
3e73aa7c | 7055 | |
29b0f896 AM |
7056 | if (i.prefix[DATA_PREFIX] != 0) |
7057 | { | |
7058 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7059 | i.prefixes -= 1; | |
7060 | code16 ^= CODE16; | |
7061 | } | |
252b5132 | 7062 | |
29b0f896 AM |
7063 | size = 4; |
7064 | if (code16) | |
7065 | size = 2; | |
7066 | } | |
9fcc94b6 | 7067 | |
29b0f896 AM |
7068 | if (i.prefix[REX_PREFIX] != 0) |
7069 | { | |
7070 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7071 | i.prefixes -= 1; | |
7072 | } | |
252b5132 | 7073 | |
7e8b059b L |
7074 | /* BND prefixed jump. */ |
7075 | if (i.prefix[BND_PREFIX] != 0) | |
7076 | { | |
7077 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7078 | i.prefixes -= 1; | |
7079 | } | |
7080 | ||
29b0f896 AM |
7081 | if (i.prefixes != 0 && !intel_syntax) |
7082 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7083 | |
42164a71 L |
7084 | p = frag_more (i.tm.opcode_length + size); |
7085 | switch (i.tm.opcode_length) | |
7086 | { | |
7087 | case 2: | |
7088 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7089 | /* Fall through. */ |
42164a71 L |
7090 | case 1: |
7091 | *p++ = i.tm.base_opcode; | |
7092 | break; | |
7093 | default: | |
7094 | abort (); | |
7095 | } | |
e0890092 | 7096 | |
3e02c1cc | 7097 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
d258b828 | 7098 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); |
3e02c1cc AM |
7099 | |
7100 | /* All jumps handled here are signed, but don't use a signed limit | |
7101 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7102 | 4G and 64k respectively. */ | |
7103 | if (size == 1) | |
7104 | fixP->fx_signed = 1; | |
29b0f896 | 7105 | } |
e0890092 | 7106 | |
29b0f896 | 7107 | static void |
e3bb37b5 | 7108 | output_interseg_jump (void) |
29b0f896 AM |
7109 | { |
7110 | char *p; | |
7111 | int size; | |
7112 | int prefix; | |
7113 | int code16; | |
252b5132 | 7114 | |
29b0f896 AM |
7115 | code16 = 0; |
7116 | if (flag_code == CODE_16BIT) | |
7117 | code16 = CODE16; | |
a217f122 | 7118 | |
29b0f896 AM |
7119 | prefix = 0; |
7120 | if (i.prefix[DATA_PREFIX] != 0) | |
7121 | { | |
7122 | prefix = 1; | |
7123 | i.prefixes -= 1; | |
7124 | code16 ^= CODE16; | |
7125 | } | |
7126 | if (i.prefix[REX_PREFIX] != 0) | |
7127 | { | |
7128 | prefix++; | |
7129 | i.prefixes -= 1; | |
7130 | } | |
252b5132 | 7131 | |
29b0f896 AM |
7132 | size = 4; |
7133 | if (code16) | |
7134 | size = 2; | |
252b5132 | 7135 | |
29b0f896 AM |
7136 | if (i.prefixes != 0 && !intel_syntax) |
7137 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7138 | |
29b0f896 AM |
7139 | /* 1 opcode; 2 segment; offset */ |
7140 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7141 | |
29b0f896 AM |
7142 | if (i.prefix[DATA_PREFIX] != 0) |
7143 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7144 | |
29b0f896 AM |
7145 | if (i.prefix[REX_PREFIX] != 0) |
7146 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7147 | |
29b0f896 AM |
7148 | *p++ = i.tm.base_opcode; |
7149 | if (i.op[1].imms->X_op == O_constant) | |
7150 | { | |
7151 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7152 | |
29b0f896 AM |
7153 | if (size == 2 |
7154 | && !fits_in_unsigned_word (n) | |
7155 | && !fits_in_signed_word (n)) | |
7156 | { | |
7157 | as_bad (_("16-bit jump out of range")); | |
7158 | return; | |
7159 | } | |
7160 | md_number_to_chars (p, n, size); | |
7161 | } | |
7162 | else | |
7163 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7164 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7165 | if (i.op[0].imms->X_op != O_constant) |
7166 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7167 | i.tm.name); | |
7168 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7169 | } | |
a217f122 | 7170 | |
29b0f896 | 7171 | static void |
e3bb37b5 | 7172 | output_insn (void) |
29b0f896 | 7173 | { |
2bbd9c25 JJ |
7174 | fragS *insn_start_frag; |
7175 | offsetT insn_start_off; | |
7176 | ||
29b0f896 AM |
7177 | /* Tie dwarf2 debug info to the address at the start of the insn. |
7178 | We can't do this after the insn has been output as the current | |
7179 | frag may have been closed off. eg. by frag_var. */ | |
7180 | dwarf2_emit_insn (0); | |
7181 | ||
2bbd9c25 JJ |
7182 | insn_start_frag = frag_now; |
7183 | insn_start_off = frag_now_fix (); | |
7184 | ||
29b0f896 | 7185 | /* Output jumps. */ |
40fb9820 | 7186 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 7187 | output_branch (); |
40fb9820 L |
7188 | else if (i.tm.opcode_modifier.jumpbyte |
7189 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 7190 | output_jump (); |
40fb9820 | 7191 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
7192 | output_interseg_jump (); |
7193 | else | |
7194 | { | |
7195 | /* Output normal instructions here. */ | |
7196 | char *p; | |
7197 | unsigned char *q; | |
47465058 | 7198 | unsigned int j; |
331d2d0d | 7199 | unsigned int prefix; |
4dffcebc | 7200 | |
e4e00185 AS |
7201 | if (avoid_fence |
7202 | && i.tm.base_opcode == 0xfae | |
7203 | && i.operands == 1 | |
7204 | && i.imm_operands == 1 | |
7205 | && (i.op[0].imms->X_add_number == 0xe8 | |
7206 | || i.op[0].imms->X_add_number == 0xf0 | |
7207 | || i.op[0].imms->X_add_number == 0xf8)) | |
7208 | { | |
7209 | /* Encode lfence, mfence, and sfence as | |
7210 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
7211 | offsetT val = 0x240483f0ULL; | |
7212 | p = frag_more (5); | |
7213 | md_number_to_chars (p, val, 5); | |
7214 | return; | |
7215 | } | |
7216 | ||
d022bddd IT |
7217 | /* Some processors fail on LOCK prefix. This options makes |
7218 | assembler ignore LOCK prefix and serves as a workaround. */ | |
7219 | if (omit_lock_prefix) | |
7220 | { | |
7221 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
7222 | return; | |
7223 | i.prefix[LOCK_PREFIX] = 0; | |
7224 | } | |
7225 | ||
43234a1e L |
7226 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
7227 | don't need the explicit prefix. */ | |
7228 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 7229 | { |
c0f3af97 | 7230 | switch (i.tm.opcode_length) |
bc4bd9ab | 7231 | { |
c0f3af97 L |
7232 | case 3: |
7233 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 7234 | { |
c0f3af97 L |
7235 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
7236 | goto check_prefix; | |
7237 | } | |
7238 | break; | |
7239 | case 2: | |
7240 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
7241 | { | |
7242 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
7243 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
7244 | { | |
4dffcebc | 7245 | check_prefix: |
c0f3af97 | 7246 | if (prefix != REPE_PREFIX_OPCODE |
c32fa91d | 7247 | || (i.prefix[REP_PREFIX] |
c0f3af97 L |
7248 | != REPE_PREFIX_OPCODE)) |
7249 | add_prefix (prefix); | |
7250 | } | |
7251 | else | |
4dffcebc L |
7252 | add_prefix (prefix); |
7253 | } | |
c0f3af97 L |
7254 | break; |
7255 | case 1: | |
7256 | break; | |
390c91cf L |
7257 | case 0: |
7258 | /* Check for pseudo prefixes. */ | |
7259 | as_bad_where (insn_start_frag->fr_file, | |
7260 | insn_start_frag->fr_line, | |
7261 | _("pseudo prefix without instruction")); | |
7262 | return; | |
c0f3af97 L |
7263 | default: |
7264 | abort (); | |
bc4bd9ab | 7265 | } |
c0f3af97 | 7266 | |
6d19a37a | 7267 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
7268 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
7269 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
7270 | perform IE->LE optimization. */ | |
7271 | if (x86_elf_abi == X86_64_X32_ABI | |
7272 | && i.operands == 2 | |
7273 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
7274 | && i.prefix[REX_PREFIX] == 0) | |
7275 | add_prefix (REX_OPCODE); | |
6d19a37a | 7276 | #endif |
cf61b747 | 7277 | |
c0f3af97 L |
7278 | /* The prefix bytes. */ |
7279 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
7280 | if (*q) | |
7281 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 7282 | } |
ae5c1c7b | 7283 | else |
c0f3af97 L |
7284 | { |
7285 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
7286 | if (*q) | |
7287 | switch (j) | |
7288 | { | |
7289 | case REX_PREFIX: | |
7290 | /* REX byte is encoded in VEX prefix. */ | |
7291 | break; | |
7292 | case SEG_PREFIX: | |
7293 | case ADDR_PREFIX: | |
7294 | FRAG_APPEND_1_CHAR (*q); | |
7295 | break; | |
7296 | default: | |
7297 | /* There should be no other prefixes for instructions | |
7298 | with VEX prefix. */ | |
7299 | abort (); | |
7300 | } | |
7301 | ||
43234a1e L |
7302 | /* For EVEX instructions i.vrex should become 0 after |
7303 | build_evex_prefix. For VEX instructions upper 16 registers | |
7304 | aren't available, so VREX should be 0. */ | |
7305 | if (i.vrex) | |
7306 | abort (); | |
c0f3af97 L |
7307 | /* Now the VEX prefix. */ |
7308 | p = frag_more (i.vex.length); | |
7309 | for (j = 0; j < i.vex.length; j++) | |
7310 | p[j] = i.vex.bytes[j]; | |
7311 | } | |
252b5132 | 7312 | |
29b0f896 | 7313 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 7314 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
7315 | { |
7316 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
7317 | } | |
7318 | else | |
7319 | { | |
4dffcebc | 7320 | switch (i.tm.opcode_length) |
331d2d0d | 7321 | { |
43234a1e L |
7322 | case 4: |
7323 | p = frag_more (4); | |
7324 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
7325 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
7326 | break; | |
4dffcebc | 7327 | case 3: |
331d2d0d L |
7328 | p = frag_more (3); |
7329 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
7330 | break; |
7331 | case 2: | |
7332 | p = frag_more (2); | |
7333 | break; | |
7334 | default: | |
7335 | abort (); | |
7336 | break; | |
331d2d0d | 7337 | } |
0f10071e | 7338 | |
29b0f896 AM |
7339 | /* Put out high byte first: can't use md_number_to_chars! */ |
7340 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
7341 | *p = i.tm.base_opcode & 0xff; | |
7342 | } | |
3e73aa7c | 7343 | |
29b0f896 | 7344 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 7345 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 7346 | { |
4a3523fa L |
7347 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
7348 | | i.rm.reg << 3 | |
7349 | | i.rm.mode << 6)); | |
29b0f896 AM |
7350 | /* If i.rm.regmem == ESP (4) |
7351 | && i.rm.mode != (Register mode) | |
7352 | && not 16 bit | |
7353 | ==> need second modrm byte. */ | |
7354 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
7355 | && i.rm.mode != 3 | |
dc821c5f | 7356 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
7357 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
7358 | | i.sib.index << 3 | |
7359 | | i.sib.scale << 6)); | |
29b0f896 | 7360 | } |
3e73aa7c | 7361 | |
29b0f896 | 7362 | if (i.disp_operands) |
2bbd9c25 | 7363 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 7364 | |
29b0f896 | 7365 | if (i.imm_operands) |
2bbd9c25 | 7366 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 7367 | } |
252b5132 | 7368 | |
29b0f896 AM |
7369 | #ifdef DEBUG386 |
7370 | if (flag_debug) | |
7371 | { | |
7b81dfbb | 7372 | pi ("" /*line*/, &i); |
29b0f896 AM |
7373 | } |
7374 | #endif /* DEBUG386 */ | |
7375 | } | |
252b5132 | 7376 | |
e205caa7 L |
7377 | /* Return the size of the displacement operand N. */ |
7378 | ||
7379 | static int | |
7380 | disp_size (unsigned int n) | |
7381 | { | |
7382 | int size = 4; | |
43234a1e | 7383 | |
b5014f7a | 7384 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
7385 | size = 8; |
7386 | else if (i.types[n].bitfield.disp8) | |
7387 | size = 1; | |
7388 | else if (i.types[n].bitfield.disp16) | |
7389 | size = 2; | |
e205caa7 L |
7390 | return size; |
7391 | } | |
7392 | ||
7393 | /* Return the size of the immediate operand N. */ | |
7394 | ||
7395 | static int | |
7396 | imm_size (unsigned int n) | |
7397 | { | |
7398 | int size = 4; | |
40fb9820 L |
7399 | if (i.types[n].bitfield.imm64) |
7400 | size = 8; | |
7401 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
7402 | size = 1; | |
7403 | else if (i.types[n].bitfield.imm16) | |
7404 | size = 2; | |
e205caa7 L |
7405 | return size; |
7406 | } | |
7407 | ||
29b0f896 | 7408 | static void |
64e74474 | 7409 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7410 | { |
7411 | char *p; | |
7412 | unsigned int n; | |
252b5132 | 7413 | |
29b0f896 AM |
7414 | for (n = 0; n < i.operands; n++) |
7415 | { | |
b5014f7a | 7416 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
7417 | { |
7418 | if (i.op[n].disps->X_op == O_constant) | |
7419 | { | |
e205caa7 | 7420 | int size = disp_size (n); |
43234a1e | 7421 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 7422 | |
b5014f7a | 7423 | val = offset_in_range (val >> i.memshift, size); |
29b0f896 AM |
7424 | p = frag_more (size); |
7425 | md_number_to_chars (p, val, size); | |
7426 | } | |
7427 | else | |
7428 | { | |
f86103b7 | 7429 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 7430 | int size = disp_size (n); |
40fb9820 | 7431 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 7432 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 7433 | fixS *fixP; |
29b0f896 | 7434 | |
e205caa7 | 7435 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 7436 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 7437 | |
29b0f896 AM |
7438 | /* The PC relative address is computed relative |
7439 | to the instruction boundary, so in case immediate | |
7440 | fields follows, we need to adjust the value. */ | |
7441 | if (pcrel && i.imm_operands) | |
7442 | { | |
29b0f896 | 7443 | unsigned int n1; |
e205caa7 | 7444 | int sz = 0; |
252b5132 | 7445 | |
29b0f896 | 7446 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 7447 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 7448 | { |
e205caa7 L |
7449 | /* Only one immediate is allowed for PC |
7450 | relative address. */ | |
9c2799c2 | 7451 | gas_assert (sz == 0); |
e205caa7 L |
7452 | sz = imm_size (n1); |
7453 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 7454 | } |
29b0f896 | 7455 | /* We should find the immediate. */ |
9c2799c2 | 7456 | gas_assert (sz != 0); |
29b0f896 | 7457 | } |
520dc8e8 | 7458 | |
29b0f896 | 7459 | p = frag_more (size); |
d258b828 | 7460 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 7461 | if (GOT_symbol |
2bbd9c25 | 7462 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 7463 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7464 | || reloc_type == BFD_RELOC_X86_64_32S |
7465 | || (reloc_type == BFD_RELOC_64 | |
7466 | && object_64bit)) | |
d6ab8113 JB |
7467 | && (i.op[n].disps->X_op == O_symbol |
7468 | || (i.op[n].disps->X_op == O_add | |
7469 | && ((symbol_get_value_expression | |
7470 | (i.op[n].disps->X_op_symbol)->X_op) | |
7471 | == O_subtract)))) | |
7472 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
7473 | { |
7474 | offsetT add; | |
7475 | ||
7476 | if (insn_start_frag == frag_now) | |
7477 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7478 | else | |
7479 | { | |
7480 | fragS *fr; | |
7481 | ||
7482 | add = insn_start_frag->fr_fix - insn_start_off; | |
7483 | for (fr = insn_start_frag->fr_next; | |
7484 | fr && fr != frag_now; fr = fr->fr_next) | |
7485 | add += fr->fr_fix; | |
7486 | add += p - frag_now->fr_literal; | |
7487 | } | |
7488 | ||
4fa24527 | 7489 | if (!object_64bit) |
7b81dfbb AJ |
7490 | { |
7491 | reloc_type = BFD_RELOC_386_GOTPC; | |
7492 | i.op[n].imms->X_add_number += add; | |
7493 | } | |
7494 | else if (reloc_type == BFD_RELOC_64) | |
7495 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 7496 | else |
7b81dfbb AJ |
7497 | /* Don't do the adjustment for x86-64, as there |
7498 | the pcrel addressing is relative to the _next_ | |
7499 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 7500 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 7501 | } |
02a86693 L |
7502 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
7503 | size, i.op[n].disps, pcrel, | |
7504 | reloc_type); | |
7505 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
7506 | "test %reg, mem" and "binop mem, %reg" where binop | |
7507 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
0cb4071e L |
7508 | instructions. Always generate R_386_GOT32X for |
7509 | "sym*GOT" operand in 32-bit mode. */ | |
7510 | if ((generate_relax_relocations | |
7511 | || (!object_64bit | |
7512 | && i.rm.mode == 0 | |
7513 | && i.rm.regmem == 5)) | |
7514 | && (i.rm.mode == 2 | |
7515 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
7516 | && ((i.operands == 1 |
7517 | && i.tm.base_opcode == 0xff | |
7518 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
7519 | || (i.operands == 2 | |
7520 | && (i.tm.base_opcode == 0x8b | |
7521 | || i.tm.base_opcode == 0x85 | |
7522 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
7523 | { | |
7524 | if (object_64bit) | |
7525 | { | |
7526 | fixP->fx_tcbit = i.rex != 0; | |
7527 | if (i.base_reg | |
7528 | && (i.base_reg->reg_num == RegRip | |
7529 | || i.base_reg->reg_num == RegEip)) | |
7530 | fixP->fx_tcbit2 = 1; | |
7531 | } | |
7532 | else | |
7533 | fixP->fx_tcbit2 = 1; | |
7534 | } | |
29b0f896 AM |
7535 | } |
7536 | } | |
7537 | } | |
7538 | } | |
252b5132 | 7539 | |
29b0f896 | 7540 | static void |
64e74474 | 7541 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7542 | { |
7543 | char *p; | |
7544 | unsigned int n; | |
252b5132 | 7545 | |
29b0f896 AM |
7546 | for (n = 0; n < i.operands; n++) |
7547 | { | |
43234a1e L |
7548 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
7549 | if (i.rounding && (int) n == i.rounding->operand) | |
7550 | continue; | |
7551 | ||
40fb9820 | 7552 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
7553 | { |
7554 | if (i.op[n].imms->X_op == O_constant) | |
7555 | { | |
e205caa7 | 7556 | int size = imm_size (n); |
29b0f896 | 7557 | offsetT val; |
b4cac588 | 7558 | |
29b0f896 AM |
7559 | val = offset_in_range (i.op[n].imms->X_add_number, |
7560 | size); | |
7561 | p = frag_more (size); | |
7562 | md_number_to_chars (p, val, size); | |
7563 | } | |
7564 | else | |
7565 | { | |
7566 | /* Not absolute_section. | |
7567 | Need a 32-bit fixup (don't support 8bit | |
7568 | non-absolute imms). Try to support other | |
7569 | sizes ... */ | |
f86103b7 | 7570 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
7571 | int size = imm_size (n); |
7572 | int sign; | |
29b0f896 | 7573 | |
40fb9820 | 7574 | if (i.types[n].bitfield.imm32s |
a7d61044 | 7575 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 7576 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 7577 | sign = 1; |
e205caa7 L |
7578 | else |
7579 | sign = 0; | |
520dc8e8 | 7580 | |
29b0f896 | 7581 | p = frag_more (size); |
d258b828 | 7582 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 7583 | |
2bbd9c25 JJ |
7584 | /* This is tough to explain. We end up with this one if we |
7585 | * have operands that look like | |
7586 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
7587 | * obtain the absolute address of the GOT, and it is strongly | |
7588 | * preferable from a performance point of view to avoid using | |
7589 | * a runtime relocation for this. The actual sequence of | |
7590 | * instructions often look something like: | |
7591 | * | |
7592 | * call .L66 | |
7593 | * .L66: | |
7594 | * popl %ebx | |
7595 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
7596 | * | |
7597 | * The call and pop essentially return the absolute address | |
7598 | * of the label .L66 and store it in %ebx. The linker itself | |
7599 | * will ultimately change the first operand of the addl so | |
7600 | * that %ebx points to the GOT, but to keep things simple, the | |
7601 | * .o file must have this operand set so that it generates not | |
7602 | * the absolute address of .L66, but the absolute address of | |
7603 | * itself. This allows the linker itself simply treat a GOTPC | |
7604 | * relocation as asking for a pcrel offset to the GOT to be | |
7605 | * added in, and the addend of the relocation is stored in the | |
7606 | * operand field for the instruction itself. | |
7607 | * | |
7608 | * Our job here is to fix the operand so that it would add | |
7609 | * the correct offset so that %ebx would point to itself. The | |
7610 | * thing that is tricky is that .-.L66 will point to the | |
7611 | * beginning of the instruction, so we need to further modify | |
7612 | * the operand so that it will point to itself. There are | |
7613 | * other cases where you have something like: | |
7614 | * | |
7615 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
7616 | * | |
7617 | * and here no correction would be required. Internally in | |
7618 | * the assembler we treat operands of this form as not being | |
7619 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
7620 | * whether it would simplify matters to do it this way. Who | |
7621 | * knows. In earlier versions of the PIC patches, the | |
7622 | * pcrel_adjust field was used to store the correction, but | |
7623 | * since the expression is not pcrel, I felt it would be | |
7624 | * confusing to do it this way. */ | |
7625 | ||
d6ab8113 | 7626 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7627 | || reloc_type == BFD_RELOC_X86_64_32S |
7628 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
7629 | && GOT_symbol |
7630 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
7631 | && (i.op[n].imms->X_op == O_symbol | |
7632 | || (i.op[n].imms->X_op == O_add | |
7633 | && ((symbol_get_value_expression | |
7634 | (i.op[n].imms->X_op_symbol)->X_op) | |
7635 | == O_subtract)))) | |
7636 | { | |
2bbd9c25 JJ |
7637 | offsetT add; |
7638 | ||
7639 | if (insn_start_frag == frag_now) | |
7640 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7641 | else | |
7642 | { | |
7643 | fragS *fr; | |
7644 | ||
7645 | add = insn_start_frag->fr_fix - insn_start_off; | |
7646 | for (fr = insn_start_frag->fr_next; | |
7647 | fr && fr != frag_now; fr = fr->fr_next) | |
7648 | add += fr->fr_fix; | |
7649 | add += p - frag_now->fr_literal; | |
7650 | } | |
7651 | ||
4fa24527 | 7652 | if (!object_64bit) |
d6ab8113 | 7653 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 7654 | else if (size == 4) |
d6ab8113 | 7655 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
7656 | else if (size == 8) |
7657 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 7658 | i.op[n].imms->X_add_number += add; |
29b0f896 | 7659 | } |
29b0f896 AM |
7660 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
7661 | i.op[n].imms, 0, reloc_type); | |
7662 | } | |
7663 | } | |
7664 | } | |
252b5132 RH |
7665 | } |
7666 | \f | |
d182319b JB |
7667 | /* x86_cons_fix_new is called via the expression parsing code when a |
7668 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
7669 | static int cons_sign = -1; |
7670 | ||
7671 | void | |
e3bb37b5 | 7672 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 7673 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 7674 | { |
d258b828 | 7675 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
7676 | |
7677 | #ifdef TE_PE | |
7678 | if (exp->X_op == O_secrel) | |
7679 | { | |
7680 | exp->X_op = O_symbol; | |
7681 | r = BFD_RELOC_32_SECREL; | |
7682 | } | |
7683 | #endif | |
7684 | ||
7685 | fix_new_exp (frag, off, len, exp, 0, r); | |
7686 | } | |
7687 | ||
357d1bd8 L |
7688 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
7689 | purpose of the `.dc.a' internal pseudo-op. */ | |
7690 | ||
7691 | int | |
7692 | x86_address_bytes (void) | |
7693 | { | |
7694 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
7695 | return 4; | |
7696 | return stdoutput->arch_info->bits_per_address / 8; | |
7697 | } | |
7698 | ||
d382c579 TG |
7699 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
7700 | || defined (LEX_AT) | |
d258b828 | 7701 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 7702 | #else |
f3c180ae AM |
7703 | /* Parse operands of the form |
7704 | <symbol>@GOTOFF+<nnn> | |
7705 | and similar .plt or .got references. | |
7706 | ||
7707 | If we find one, set up the correct relocation in RELOC and copy the | |
7708 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
7709 | parsing by the calling routine. Return this buffer, and if ADJUST | |
7710 | is non-null set it to the length of the string we removed from the | |
7711 | input line. Otherwise return NULL. */ | |
7712 | static char * | |
91d6fa6a | 7713 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 7714 | int *adjust, |
d258b828 | 7715 | i386_operand_type *types) |
f3c180ae | 7716 | { |
7b81dfbb AJ |
7717 | /* Some of the relocations depend on the size of what field is to |
7718 | be relocated. But in our callers i386_immediate and i386_displacement | |
7719 | we don't yet know the operand size (this will be set by insn | |
7720 | matching). Hence we record the word32 relocation here, | |
7721 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
7722 | static const struct { |
7723 | const char *str; | |
cff8d58a | 7724 | int len; |
4fa24527 | 7725 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 7726 | const i386_operand_type types64; |
f3c180ae | 7727 | } gotrel[] = { |
8ce3d284 | 7728 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
7729 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
7730 | BFD_RELOC_SIZE32 }, | |
7731 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 7732 | #endif |
cff8d58a L |
7733 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
7734 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 7735 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
7736 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
7737 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 7738 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7739 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
7740 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 7741 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
7742 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
7743 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 7744 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
7745 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
7746 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 7747 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7748 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
7749 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 7750 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7751 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
7752 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7753 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7754 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
7755 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 7756 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7757 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
7758 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 7759 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7760 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
7761 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 7762 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
7763 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
7764 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7765 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7766 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
7767 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 7768 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
7769 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
7770 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7771 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7772 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
7773 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7774 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7775 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
7776 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 7777 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
7778 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
7779 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 7780 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7781 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
7782 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 7783 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
7784 | }; |
7785 | char *cp; | |
7786 | unsigned int j; | |
7787 | ||
d382c579 | 7788 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
7789 | if (!IS_ELF) |
7790 | return NULL; | |
d382c579 | 7791 | #endif |
718ddfc0 | 7792 | |
f3c180ae | 7793 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 7794 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
7795 | return NULL; |
7796 | ||
47465058 | 7797 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 7798 | { |
cff8d58a | 7799 | int len = gotrel[j].len; |
28f81592 | 7800 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 7801 | { |
4fa24527 | 7802 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 7803 | { |
28f81592 AM |
7804 | int first, second; |
7805 | char *tmpbuf, *past_reloc; | |
f3c180ae | 7806 | |
91d6fa6a | 7807 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 7808 | |
3956db08 JB |
7809 | if (types) |
7810 | { | |
7811 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
7812 | { |
7813 | types->bitfield.imm32 = 1; | |
7814 | types->bitfield.disp32 = 1; | |
7815 | } | |
3956db08 JB |
7816 | else |
7817 | *types = gotrel[j].types64; | |
7818 | } | |
7819 | ||
8fd4256d | 7820 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
7821 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
7822 | ||
28f81592 | 7823 | /* The length of the first part of our input line. */ |
f3c180ae | 7824 | first = cp - input_line_pointer; |
28f81592 AM |
7825 | |
7826 | /* The second part goes from after the reloc token until | |
67c11a9b | 7827 | (and including) an end_of_line char or comma. */ |
28f81592 | 7828 | past_reloc = cp + 1 + len; |
67c11a9b AM |
7829 | cp = past_reloc; |
7830 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
7831 | ++cp; | |
7832 | second = cp + 1 - past_reloc; | |
28f81592 AM |
7833 | |
7834 | /* Allocate and copy string. The trailing NUL shouldn't | |
7835 | be necessary, but be safe. */ | |
add39d23 | 7836 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 7837 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
7838 | if (second != 0 && *past_reloc != ' ') |
7839 | /* Replace the relocation token with ' ', so that | |
7840 | errors like foo@GOTOFF1 will be detected. */ | |
7841 | tmpbuf[first++] = ' '; | |
af89796a L |
7842 | else |
7843 | /* Increment length by 1 if the relocation token is | |
7844 | removed. */ | |
7845 | len++; | |
7846 | if (adjust) | |
7847 | *adjust = len; | |
0787a12d AM |
7848 | memcpy (tmpbuf + first, past_reloc, second); |
7849 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
7850 | return tmpbuf; |
7851 | } | |
7852 | ||
4fa24527 JB |
7853 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
7854 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
7855 | return NULL; |
7856 | } | |
7857 | } | |
7858 | ||
7859 | /* Might be a symbol version string. Don't as_bad here. */ | |
7860 | return NULL; | |
7861 | } | |
4e4f7c87 | 7862 | #endif |
f3c180ae | 7863 | |
a988325c NC |
7864 | #ifdef TE_PE |
7865 | #ifdef lex_got | |
7866 | #undef lex_got | |
7867 | #endif | |
7868 | /* Parse operands of the form | |
7869 | <symbol>@SECREL32+<nnn> | |
7870 | ||
7871 | If we find one, set up the correct relocation in RELOC and copy the | |
7872 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
7873 | parsing by the calling routine. Return this buffer, and if ADJUST | |
7874 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
7875 | input line. Otherwise return NULL. |
7876 | ||
a988325c NC |
7877 | This function is copied from the ELF version above adjusted for PE targets. */ |
7878 | ||
7879 | static char * | |
7880 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
7881 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 7882 | i386_operand_type *types) |
a988325c NC |
7883 | { |
7884 | static const struct | |
7885 | { | |
7886 | const char *str; | |
7887 | int len; | |
7888 | const enum bfd_reloc_code_real rel[2]; | |
7889 | const i386_operand_type types64; | |
7890 | } | |
7891 | gotrel[] = | |
7892 | { | |
7893 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
7894 | BFD_RELOC_32_SECREL }, | |
7895 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
7896 | }; | |
7897 | ||
7898 | char *cp; | |
7899 | unsigned j; | |
7900 | ||
7901 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
7902 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
7903 | return NULL; | |
7904 | ||
7905 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
7906 | { | |
7907 | int len = gotrel[j].len; | |
7908 | ||
7909 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
7910 | { | |
7911 | if (gotrel[j].rel[object_64bit] != 0) | |
7912 | { | |
7913 | int first, second; | |
7914 | char *tmpbuf, *past_reloc; | |
7915 | ||
7916 | *rel = gotrel[j].rel[object_64bit]; | |
7917 | if (adjust) | |
7918 | *adjust = len; | |
7919 | ||
7920 | if (types) | |
7921 | { | |
7922 | if (flag_code != CODE_64BIT) | |
7923 | { | |
7924 | types->bitfield.imm32 = 1; | |
7925 | types->bitfield.disp32 = 1; | |
7926 | } | |
7927 | else | |
7928 | *types = gotrel[j].types64; | |
7929 | } | |
7930 | ||
7931 | /* The length of the first part of our input line. */ | |
7932 | first = cp - input_line_pointer; | |
7933 | ||
7934 | /* The second part goes from after the reloc token until | |
7935 | (and including) an end_of_line char or comma. */ | |
7936 | past_reloc = cp + 1 + len; | |
7937 | cp = past_reloc; | |
7938 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
7939 | ++cp; | |
7940 | second = cp + 1 - past_reloc; | |
7941 | ||
7942 | /* Allocate and copy string. The trailing NUL shouldn't | |
7943 | be necessary, but be safe. */ | |
add39d23 | 7944 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
7945 | memcpy (tmpbuf, input_line_pointer, first); |
7946 | if (second != 0 && *past_reloc != ' ') | |
7947 | /* Replace the relocation token with ' ', so that | |
7948 | errors like foo@SECLREL321 will be detected. */ | |
7949 | tmpbuf[first++] = ' '; | |
7950 | memcpy (tmpbuf + first, past_reloc, second); | |
7951 | tmpbuf[first + second] = '\0'; | |
7952 | return tmpbuf; | |
7953 | } | |
7954 | ||
7955 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
7956 | gotrel[j].str, 1 << (5 + object_64bit)); | |
7957 | return NULL; | |
7958 | } | |
7959 | } | |
7960 | ||
7961 | /* Might be a symbol version string. Don't as_bad here. */ | |
7962 | return NULL; | |
7963 | } | |
7964 | ||
7965 | #endif /* TE_PE */ | |
7966 | ||
62ebcb5c | 7967 | bfd_reloc_code_real_type |
e3bb37b5 | 7968 | x86_cons (expressionS *exp, int size) |
f3c180ae | 7969 | { |
62ebcb5c AM |
7970 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
7971 | ||
ee86248c JB |
7972 | intel_syntax = -intel_syntax; |
7973 | ||
3c7b9c2c | 7974 | exp->X_md = 0; |
4fa24527 | 7975 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
7976 | { |
7977 | /* Handle @GOTOFF and the like in an expression. */ | |
7978 | char *save; | |
7979 | char *gotfree_input_line; | |
4a57f2cf | 7980 | int adjust = 0; |
f3c180ae AM |
7981 | |
7982 | save = input_line_pointer; | |
d258b828 | 7983 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
7984 | if (gotfree_input_line) |
7985 | input_line_pointer = gotfree_input_line; | |
7986 | ||
7987 | expression (exp); | |
7988 | ||
7989 | if (gotfree_input_line) | |
7990 | { | |
7991 | /* expression () has merrily parsed up to the end of line, | |
7992 | or a comma - in the wrong buffer. Transfer how far | |
7993 | input_line_pointer has moved to the right buffer. */ | |
7994 | input_line_pointer = (save | |
7995 | + (input_line_pointer - gotfree_input_line) | |
7996 | + adjust); | |
7997 | free (gotfree_input_line); | |
3992d3b7 AM |
7998 | if (exp->X_op == O_constant |
7999 | || exp->X_op == O_absent | |
8000 | || exp->X_op == O_illegal | |
0398aac5 | 8001 | || exp->X_op == O_register |
3992d3b7 AM |
8002 | || exp->X_op == O_big) |
8003 | { | |
8004 | char c = *input_line_pointer; | |
8005 | *input_line_pointer = 0; | |
8006 | as_bad (_("missing or invalid expression `%s'"), save); | |
8007 | *input_line_pointer = c; | |
8008 | } | |
f3c180ae AM |
8009 | } |
8010 | } | |
8011 | else | |
8012 | expression (exp); | |
ee86248c JB |
8013 | |
8014 | intel_syntax = -intel_syntax; | |
8015 | ||
8016 | if (intel_syntax) | |
8017 | i386_intel_simplify (exp); | |
62ebcb5c AM |
8018 | |
8019 | return got_reloc; | |
f3c180ae | 8020 | } |
f3c180ae | 8021 | |
9f32dd5b L |
8022 | static void |
8023 | signed_cons (int size) | |
6482c264 | 8024 | { |
d182319b JB |
8025 | if (flag_code == CODE_64BIT) |
8026 | cons_sign = 1; | |
8027 | cons (size); | |
8028 | cons_sign = -1; | |
6482c264 NC |
8029 | } |
8030 | ||
d182319b | 8031 | #ifdef TE_PE |
6482c264 | 8032 | static void |
7016a5d5 | 8033 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
8034 | { |
8035 | expressionS exp; | |
8036 | ||
8037 | do | |
8038 | { | |
8039 | expression (&exp); | |
8040 | if (exp.X_op == O_symbol) | |
8041 | exp.X_op = O_secrel; | |
8042 | ||
8043 | emit_expr (&exp, 4); | |
8044 | } | |
8045 | while (*input_line_pointer++ == ','); | |
8046 | ||
8047 | input_line_pointer--; | |
8048 | demand_empty_rest_of_line (); | |
8049 | } | |
6482c264 NC |
8050 | #endif |
8051 | ||
43234a1e L |
8052 | /* Handle Vector operations. */ |
8053 | ||
8054 | static char * | |
8055 | check_VecOperations (char *op_string, char *op_end) | |
8056 | { | |
8057 | const reg_entry *mask; | |
8058 | const char *saved; | |
8059 | char *end_op; | |
8060 | ||
8061 | while (*op_string | |
8062 | && (op_end == NULL || op_string < op_end)) | |
8063 | { | |
8064 | saved = op_string; | |
8065 | if (*op_string == '{') | |
8066 | { | |
8067 | op_string++; | |
8068 | ||
8069 | /* Check broadcasts. */ | |
8070 | if (strncmp (op_string, "1to", 3) == 0) | |
8071 | { | |
8072 | int bcst_type; | |
8073 | ||
8074 | if (i.broadcast) | |
8075 | goto duplicated_vec_op; | |
8076 | ||
8077 | op_string += 3; | |
8078 | if (*op_string == '8') | |
8079 | bcst_type = BROADCAST_1TO8; | |
b28d1bda IT |
8080 | else if (*op_string == '4') |
8081 | bcst_type = BROADCAST_1TO4; | |
8082 | else if (*op_string == '2') | |
8083 | bcst_type = BROADCAST_1TO2; | |
43234a1e L |
8084 | else if (*op_string == '1' |
8085 | && *(op_string+1) == '6') | |
8086 | { | |
8087 | bcst_type = BROADCAST_1TO16; | |
8088 | op_string++; | |
8089 | } | |
8090 | else | |
8091 | { | |
8092 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
8093 | return NULL; | |
8094 | } | |
8095 | op_string++; | |
8096 | ||
8097 | broadcast_op.type = bcst_type; | |
8098 | broadcast_op.operand = this_operand; | |
8099 | i.broadcast = &broadcast_op; | |
8100 | } | |
8101 | /* Check masking operation. */ | |
8102 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
8103 | { | |
8104 | /* k0 can't be used for write mask. */ | |
6d2cd6b2 | 8105 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
43234a1e | 8106 | { |
6d2cd6b2 JB |
8107 | as_bad (_("`%s%s' can't be used for write mask"), |
8108 | register_prefix, mask->reg_name); | |
43234a1e L |
8109 | return NULL; |
8110 | } | |
8111 | ||
8112 | if (!i.mask) | |
8113 | { | |
8114 | mask_op.mask = mask; | |
8115 | mask_op.zeroing = 0; | |
8116 | mask_op.operand = this_operand; | |
8117 | i.mask = &mask_op; | |
8118 | } | |
8119 | else | |
8120 | { | |
8121 | if (i.mask->mask) | |
8122 | goto duplicated_vec_op; | |
8123 | ||
8124 | i.mask->mask = mask; | |
8125 | ||
8126 | /* Only "{z}" is allowed here. No need to check | |
8127 | zeroing mask explicitly. */ | |
8128 | if (i.mask->operand != this_operand) | |
8129 | { | |
8130 | as_bad (_("invalid write mask `%s'"), saved); | |
8131 | return NULL; | |
8132 | } | |
8133 | } | |
8134 | ||
8135 | op_string = end_op; | |
8136 | } | |
8137 | /* Check zeroing-flag for masking operation. */ | |
8138 | else if (*op_string == 'z') | |
8139 | { | |
8140 | if (!i.mask) | |
8141 | { | |
8142 | mask_op.mask = NULL; | |
8143 | mask_op.zeroing = 1; | |
8144 | mask_op.operand = this_operand; | |
8145 | i.mask = &mask_op; | |
8146 | } | |
8147 | else | |
8148 | { | |
8149 | if (i.mask->zeroing) | |
8150 | { | |
8151 | duplicated_vec_op: | |
8152 | as_bad (_("duplicated `%s'"), saved); | |
8153 | return NULL; | |
8154 | } | |
8155 | ||
8156 | i.mask->zeroing = 1; | |
8157 | ||
8158 | /* Only "{%k}" is allowed here. No need to check mask | |
8159 | register explicitly. */ | |
8160 | if (i.mask->operand != this_operand) | |
8161 | { | |
8162 | as_bad (_("invalid zeroing-masking `%s'"), | |
8163 | saved); | |
8164 | return NULL; | |
8165 | } | |
8166 | } | |
8167 | ||
8168 | op_string++; | |
8169 | } | |
8170 | else | |
8171 | goto unknown_vec_op; | |
8172 | ||
8173 | if (*op_string != '}') | |
8174 | { | |
8175 | as_bad (_("missing `}' in `%s'"), saved); | |
8176 | return NULL; | |
8177 | } | |
8178 | op_string++; | |
8179 | continue; | |
8180 | } | |
8181 | unknown_vec_op: | |
8182 | /* We don't know this one. */ | |
8183 | as_bad (_("unknown vector operation: `%s'"), saved); | |
8184 | return NULL; | |
8185 | } | |
8186 | ||
6d2cd6b2 JB |
8187 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
8188 | { | |
8189 | as_bad (_("zeroing-masking only allowed with write mask")); | |
8190 | return NULL; | |
8191 | } | |
8192 | ||
43234a1e L |
8193 | return op_string; |
8194 | } | |
8195 | ||
252b5132 | 8196 | static int |
70e41ade | 8197 | i386_immediate (char *imm_start) |
252b5132 RH |
8198 | { |
8199 | char *save_input_line_pointer; | |
f3c180ae | 8200 | char *gotfree_input_line; |
252b5132 | 8201 | segT exp_seg = 0; |
47926f60 | 8202 | expressionS *exp; |
40fb9820 L |
8203 | i386_operand_type types; |
8204 | ||
0dfbf9d7 | 8205 | operand_type_set (&types, ~0); |
252b5132 RH |
8206 | |
8207 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
8208 | { | |
31b2323c L |
8209 | as_bad (_("at most %d immediate operands are allowed"), |
8210 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
8211 | return 0; |
8212 | } | |
8213 | ||
8214 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 8215 | i.op[this_operand].imms = exp; |
252b5132 RH |
8216 | |
8217 | if (is_space_char (*imm_start)) | |
8218 | ++imm_start; | |
8219 | ||
8220 | save_input_line_pointer = input_line_pointer; | |
8221 | input_line_pointer = imm_start; | |
8222 | ||
d258b828 | 8223 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8224 | if (gotfree_input_line) |
8225 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
8226 | |
8227 | exp_seg = expression (exp); | |
8228 | ||
83183c0c | 8229 | SKIP_WHITESPACE (); |
43234a1e L |
8230 | |
8231 | /* Handle vector operations. */ | |
8232 | if (*input_line_pointer == '{') | |
8233 | { | |
8234 | input_line_pointer = check_VecOperations (input_line_pointer, | |
8235 | NULL); | |
8236 | if (input_line_pointer == NULL) | |
8237 | return 0; | |
8238 | } | |
8239 | ||
252b5132 | 8240 | if (*input_line_pointer) |
f3c180ae | 8241 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
8242 | |
8243 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 8244 | if (gotfree_input_line) |
ee86248c JB |
8245 | { |
8246 | free (gotfree_input_line); | |
8247 | ||
8248 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8249 | exp->X_op = O_illegal; | |
8250 | } | |
8251 | ||
8252 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
8253 | } | |
252b5132 | 8254 | |
ee86248c JB |
8255 | static int |
8256 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8257 | i386_operand_type types, const char *imm_start) | |
8258 | { | |
8259 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 8260 | { |
313c53d1 L |
8261 | if (imm_start) |
8262 | as_bad (_("missing or invalid immediate expression `%s'"), | |
8263 | imm_start); | |
3992d3b7 | 8264 | return 0; |
252b5132 | 8265 | } |
3e73aa7c | 8266 | else if (exp->X_op == O_constant) |
252b5132 | 8267 | { |
47926f60 | 8268 | /* Size it properly later. */ |
40fb9820 | 8269 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
8270 | /* If not 64bit, sign extend val. */ |
8271 | if (flag_code != CODE_64BIT | |
4eed87de AM |
8272 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
8273 | exp->X_add_number | |
8274 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 8275 | } |
4c63da97 | 8276 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 8277 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 8278 | && exp_seg != absolute_section |
47926f60 | 8279 | && exp_seg != text_section |
24eab124 AM |
8280 | && exp_seg != data_section |
8281 | && exp_seg != bss_section | |
8282 | && exp_seg != undefined_section | |
f86103b7 | 8283 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 8284 | { |
d0b47220 | 8285 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
8286 | return 0; |
8287 | } | |
8288 | #endif | |
a841bdf5 | 8289 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 8290 | { |
313c53d1 L |
8291 | if (imm_start) |
8292 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
8293 | return 0; |
8294 | } | |
252b5132 RH |
8295 | else |
8296 | { | |
8297 | /* This is an address. The size of the address will be | |
24eab124 | 8298 | determined later, depending on destination register, |
3e73aa7c | 8299 | suffix, or the default for the section. */ |
40fb9820 L |
8300 | i.types[this_operand].bitfield.imm8 = 1; |
8301 | i.types[this_operand].bitfield.imm16 = 1; | |
8302 | i.types[this_operand].bitfield.imm32 = 1; | |
8303 | i.types[this_operand].bitfield.imm32s = 1; | |
8304 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
8305 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8306 | types); | |
252b5132 RH |
8307 | } |
8308 | ||
8309 | return 1; | |
8310 | } | |
8311 | ||
551c1ca1 | 8312 | static char * |
e3bb37b5 | 8313 | i386_scale (char *scale) |
252b5132 | 8314 | { |
551c1ca1 AM |
8315 | offsetT val; |
8316 | char *save = input_line_pointer; | |
252b5132 | 8317 | |
551c1ca1 AM |
8318 | input_line_pointer = scale; |
8319 | val = get_absolute_expression (); | |
8320 | ||
8321 | switch (val) | |
252b5132 | 8322 | { |
551c1ca1 | 8323 | case 1: |
252b5132 RH |
8324 | i.log2_scale_factor = 0; |
8325 | break; | |
551c1ca1 | 8326 | case 2: |
252b5132 RH |
8327 | i.log2_scale_factor = 1; |
8328 | break; | |
551c1ca1 | 8329 | case 4: |
252b5132 RH |
8330 | i.log2_scale_factor = 2; |
8331 | break; | |
551c1ca1 | 8332 | case 8: |
252b5132 RH |
8333 | i.log2_scale_factor = 3; |
8334 | break; | |
8335 | default: | |
a724f0f4 JB |
8336 | { |
8337 | char sep = *input_line_pointer; | |
8338 | ||
8339 | *input_line_pointer = '\0'; | |
8340 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
8341 | scale); | |
8342 | *input_line_pointer = sep; | |
8343 | input_line_pointer = save; | |
8344 | return NULL; | |
8345 | } | |
252b5132 | 8346 | } |
29b0f896 | 8347 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
8348 | { |
8349 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 8350 | 1 << i.log2_scale_factor); |
252b5132 | 8351 | i.log2_scale_factor = 0; |
252b5132 | 8352 | } |
551c1ca1 AM |
8353 | scale = input_line_pointer; |
8354 | input_line_pointer = save; | |
8355 | return scale; | |
252b5132 RH |
8356 | } |
8357 | ||
252b5132 | 8358 | static int |
e3bb37b5 | 8359 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 8360 | { |
29b0f896 | 8361 | expressionS *exp; |
252b5132 RH |
8362 | segT exp_seg = 0; |
8363 | char *save_input_line_pointer; | |
f3c180ae | 8364 | char *gotfree_input_line; |
40fb9820 L |
8365 | int override; |
8366 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 8367 | int ret; |
252b5132 | 8368 | |
31b2323c L |
8369 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
8370 | { | |
8371 | as_bad (_("at most %d displacement operands are allowed"), | |
8372 | MAX_MEMORY_OPERANDS); | |
8373 | return 0; | |
8374 | } | |
8375 | ||
0dfbf9d7 | 8376 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
8377 | if ((i.types[this_operand].bitfield.jumpabsolute) |
8378 | || (!current_templates->start->opcode_modifier.jump | |
8379 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 8380 | { |
40fb9820 | 8381 | bigdisp.bitfield.disp32 = 1; |
e05278af | 8382 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
8383 | if (flag_code == CODE_64BIT) |
8384 | { | |
8385 | if (!override) | |
8386 | { | |
8387 | bigdisp.bitfield.disp32s = 1; | |
8388 | bigdisp.bitfield.disp64 = 1; | |
8389 | } | |
8390 | } | |
8391 | else if ((flag_code == CODE_16BIT) ^ override) | |
8392 | { | |
8393 | bigdisp.bitfield.disp32 = 0; | |
8394 | bigdisp.bitfield.disp16 = 1; | |
8395 | } | |
e05278af JB |
8396 | } |
8397 | else | |
8398 | { | |
8399 | /* For PC-relative branches, the width of the displacement | |
8400 | is dependent upon data size, not address size. */ | |
e05278af | 8401 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
8402 | if (flag_code == CODE_64BIT) |
8403 | { | |
8404 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
8405 | bigdisp.bitfield.disp16 = 1; | |
8406 | else | |
8407 | { | |
8408 | bigdisp.bitfield.disp32 = 1; | |
8409 | bigdisp.bitfield.disp32s = 1; | |
8410 | } | |
8411 | } | |
8412 | else | |
e05278af JB |
8413 | { |
8414 | if (!override) | |
8415 | override = (i.suffix == (flag_code != CODE_16BIT | |
8416 | ? WORD_MNEM_SUFFIX | |
8417 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
8418 | bigdisp.bitfield.disp32 = 1; |
8419 | if ((flag_code == CODE_16BIT) ^ override) | |
8420 | { | |
8421 | bigdisp.bitfield.disp32 = 0; | |
8422 | bigdisp.bitfield.disp16 = 1; | |
8423 | } | |
e05278af | 8424 | } |
e05278af | 8425 | } |
c6fb90c8 L |
8426 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8427 | bigdisp); | |
252b5132 RH |
8428 | |
8429 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 8430 | i.op[this_operand].disps = exp; |
252b5132 RH |
8431 | i.disp_operands++; |
8432 | save_input_line_pointer = input_line_pointer; | |
8433 | input_line_pointer = disp_start; | |
8434 | END_STRING_AND_SAVE (disp_end); | |
8435 | ||
8436 | #ifndef GCC_ASM_O_HACK | |
8437 | #define GCC_ASM_O_HACK 0 | |
8438 | #endif | |
8439 | #if GCC_ASM_O_HACK | |
8440 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 8441 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 8442 | && displacement_string_end[-1] == '+') |
252b5132 RH |
8443 | { |
8444 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
8445 | constraint within gcc asm statements. |
8446 | For instance: | |
8447 | ||
8448 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
8449 | __asm__ __volatile__ ( \ | |
8450 | "movw %w2,%0\n\t" \ | |
8451 | "movw %w1,2+%0\n\t" \ | |
8452 | "rorl $16,%1\n\t" \ | |
8453 | "movb %b1,4+%0\n\t" \ | |
8454 | "movb %4,5+%0\n\t" \ | |
8455 | "movb $0,6+%0\n\t" \ | |
8456 | "movb %h1,7+%0\n\t" \ | |
8457 | "rorl $16,%1" \ | |
8458 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
8459 | ||
8460 | This works great except that the output assembler ends | |
8461 | up looking a bit weird if it turns out that there is | |
8462 | no offset. You end up producing code that looks like: | |
8463 | ||
8464 | #APP | |
8465 | movw $235,(%eax) | |
8466 | movw %dx,2+(%eax) | |
8467 | rorl $16,%edx | |
8468 | movb %dl,4+(%eax) | |
8469 | movb $137,5+(%eax) | |
8470 | movb $0,6+(%eax) | |
8471 | movb %dh,7+(%eax) | |
8472 | rorl $16,%edx | |
8473 | #NO_APP | |
8474 | ||
47926f60 | 8475 | So here we provide the missing zero. */ |
24eab124 AM |
8476 | |
8477 | *displacement_string_end = '0'; | |
252b5132 RH |
8478 | } |
8479 | #endif | |
d258b828 | 8480 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8481 | if (gotfree_input_line) |
8482 | input_line_pointer = gotfree_input_line; | |
252b5132 | 8483 | |
24eab124 | 8484 | exp_seg = expression (exp); |
252b5132 | 8485 | |
636c26b0 AM |
8486 | SKIP_WHITESPACE (); |
8487 | if (*input_line_pointer) | |
8488 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
8489 | #if GCC_ASM_O_HACK | |
8490 | RESTORE_END_STRING (disp_end + 1); | |
8491 | #endif | |
636c26b0 | 8492 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 8493 | if (gotfree_input_line) |
ee86248c JB |
8494 | { |
8495 | free (gotfree_input_line); | |
8496 | ||
8497 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8498 | exp->X_op = O_illegal; | |
8499 | } | |
8500 | ||
8501 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
8502 | ||
8503 | RESTORE_END_STRING (disp_end); | |
8504 | ||
8505 | return ret; | |
8506 | } | |
8507 | ||
8508 | static int | |
8509 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8510 | i386_operand_type types, const char *disp_start) | |
8511 | { | |
8512 | i386_operand_type bigdisp; | |
8513 | int ret = 1; | |
636c26b0 | 8514 | |
24eab124 AM |
8515 | /* We do this to make sure that the section symbol is in |
8516 | the symbol table. We will ultimately change the relocation | |
47926f60 | 8517 | to be relative to the beginning of the section. */ |
1ae12ab7 | 8518 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
8519 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
8520 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 8521 | { |
636c26b0 | 8522 | if (exp->X_op != O_symbol) |
3992d3b7 | 8523 | goto inv_disp; |
636c26b0 | 8524 | |
e5cb08ac | 8525 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
8526 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
8527 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 8528 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
8529 | exp->X_op = O_subtract; |
8530 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 8531 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 8532 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
8533 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
8534 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 8535 | else |
29b0f896 | 8536 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 8537 | } |
252b5132 | 8538 | |
3992d3b7 AM |
8539 | else if (exp->X_op == O_absent |
8540 | || exp->X_op == O_illegal | |
ee86248c | 8541 | || exp->X_op == O_big) |
2daf4fd8 | 8542 | { |
3992d3b7 AM |
8543 | inv_disp: |
8544 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 8545 | disp_start); |
3992d3b7 | 8546 | ret = 0; |
2daf4fd8 AM |
8547 | } |
8548 | ||
0e1147d9 L |
8549 | else if (flag_code == CODE_64BIT |
8550 | && !i.prefix[ADDR_PREFIX] | |
8551 | && exp->X_op == O_constant) | |
8552 | { | |
8553 | /* Since displacement is signed extended to 64bit, don't allow | |
8554 | disp32 and turn off disp32s if they are out of range. */ | |
8555 | i.types[this_operand].bitfield.disp32 = 0; | |
8556 | if (!fits_in_signed_long (exp->X_add_number)) | |
8557 | { | |
8558 | i.types[this_operand].bitfield.disp32s = 0; | |
8559 | if (i.types[this_operand].bitfield.baseindex) | |
8560 | { | |
8561 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
8562 | (long) exp->X_add_number); | |
8563 | ret = 0; | |
8564 | } | |
8565 | } | |
8566 | } | |
8567 | ||
4c63da97 | 8568 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
8569 | else if (exp->X_op != O_constant |
8570 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
8571 | && exp_seg != absolute_section | |
8572 | && exp_seg != text_section | |
8573 | && exp_seg != data_section | |
8574 | && exp_seg != bss_section | |
8575 | && exp_seg != undefined_section | |
8576 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 8577 | { |
d0b47220 | 8578 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 8579 | ret = 0; |
24eab124 | 8580 | } |
252b5132 | 8581 | #endif |
3956db08 | 8582 | |
40fb9820 L |
8583 | /* Check if this is a displacement only operand. */ |
8584 | bigdisp = i.types[this_operand]; | |
8585 | bigdisp.bitfield.disp8 = 0; | |
8586 | bigdisp.bitfield.disp16 = 0; | |
8587 | bigdisp.bitfield.disp32 = 0; | |
8588 | bigdisp.bitfield.disp32s = 0; | |
8589 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 8590 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
8591 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8592 | types); | |
3956db08 | 8593 | |
3992d3b7 | 8594 | return ret; |
252b5132 RH |
8595 | } |
8596 | ||
2abc2bec JB |
8597 | /* Return the active addressing mode, taking address override and |
8598 | registers forming the address into consideration. Update the | |
8599 | address override prefix if necessary. */ | |
47926f60 | 8600 | |
2abc2bec JB |
8601 | static enum flag_code |
8602 | i386_addressing_mode (void) | |
252b5132 | 8603 | { |
be05d201 L |
8604 | enum flag_code addr_mode; |
8605 | ||
8606 | if (i.prefix[ADDR_PREFIX]) | |
8607 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
8608 | else | |
8609 | { | |
8610 | addr_mode = flag_code; | |
8611 | ||
24eab124 | 8612 | #if INFER_ADDR_PREFIX |
be05d201 L |
8613 | if (i.mem_operands == 0) |
8614 | { | |
8615 | /* Infer address prefix from the first memory operand. */ | |
8616 | const reg_entry *addr_reg = i.base_reg; | |
8617 | ||
8618 | if (addr_reg == NULL) | |
8619 | addr_reg = i.index_reg; | |
eecb386c | 8620 | |
be05d201 L |
8621 | if (addr_reg) |
8622 | { | |
8623 | if (addr_reg->reg_num == RegEip | |
8624 | || addr_reg->reg_num == RegEiz | |
dc821c5f | 8625 | || addr_reg->reg_type.bitfield.dword) |
be05d201 L |
8626 | addr_mode = CODE_32BIT; |
8627 | else if (flag_code != CODE_64BIT | |
dc821c5f | 8628 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
8629 | addr_mode = CODE_16BIT; |
8630 | ||
8631 | if (addr_mode != flag_code) | |
8632 | { | |
8633 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
8634 | i.prefixes += 1; | |
8635 | /* Change the size of any displacement too. At most one | |
8636 | of Disp16 or Disp32 is set. | |
8637 | FIXME. There doesn't seem to be any real need for | |
8638 | separate Disp16 and Disp32 flags. The same goes for | |
8639 | Imm16 and Imm32. Removing them would probably clean | |
8640 | up the code quite a lot. */ | |
8641 | if (flag_code != CODE_64BIT | |
8642 | && (i.types[this_operand].bitfield.disp16 | |
8643 | || i.types[this_operand].bitfield.disp32)) | |
8644 | i.types[this_operand] | |
8645 | = operand_type_xor (i.types[this_operand], disp16_32); | |
8646 | } | |
8647 | } | |
8648 | } | |
24eab124 | 8649 | #endif |
be05d201 L |
8650 | } |
8651 | ||
2abc2bec JB |
8652 | return addr_mode; |
8653 | } | |
8654 | ||
8655 | /* Make sure the memory operand we've been dealt is valid. | |
8656 | Return 1 on success, 0 on a failure. */ | |
8657 | ||
8658 | static int | |
8659 | i386_index_check (const char *operand_string) | |
8660 | { | |
8661 | const char *kind = "base/index"; | |
8662 | enum flag_code addr_mode = i386_addressing_mode (); | |
8663 | ||
fc0763e6 JB |
8664 | if (current_templates->start->opcode_modifier.isstring |
8665 | && !current_templates->start->opcode_modifier.immext | |
8666 | && (current_templates->end[-1].opcode_modifier.isstring | |
8667 | || i.mem_operands)) | |
8668 | { | |
8669 | /* Memory operands of string insns are special in that they only allow | |
8670 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
8671 | const reg_entry *expected_reg; |
8672 | static const char *di_si[][2] = | |
8673 | { | |
8674 | { "esi", "edi" }, | |
8675 | { "si", "di" }, | |
8676 | { "rsi", "rdi" } | |
8677 | }; | |
8678 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
8679 | |
8680 | kind = "string address"; | |
8681 | ||
8325cc63 | 8682 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
8683 | { |
8684 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
8685 | ||
8686 | if (!type.bitfield.baseindex | |
8687 | || ((!i.mem_operands != !intel_syntax) | |
8688 | && current_templates->end[-1].operand_types[1] | |
8689 | .bitfield.baseindex)) | |
8690 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
8691 | expected_reg = hash_find (reg_hash, |
8692 | di_si[addr_mode][type.bitfield.esseg]); | |
8693 | ||
fc0763e6 JB |
8694 | } |
8695 | else | |
be05d201 | 8696 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 8697 | |
be05d201 L |
8698 | if (i.base_reg != expected_reg |
8699 | || i.index_reg | |
fc0763e6 | 8700 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 8701 | { |
be05d201 L |
8702 | /* The second memory operand must have the same size as |
8703 | the first one. */ | |
8704 | if (i.mem_operands | |
8705 | && i.base_reg | |
8706 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 8707 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 8708 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
8709 | ? i.base_reg->reg_type.bitfield.dword |
8710 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
8711 | goto bad_address; |
8712 | ||
fc0763e6 JB |
8713 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
8714 | operand_string, | |
8715 | intel_syntax ? '[' : '(', | |
8716 | register_prefix, | |
be05d201 | 8717 | expected_reg->reg_name, |
fc0763e6 | 8718 | intel_syntax ? ']' : ')'); |
be05d201 | 8719 | return 1; |
fc0763e6 | 8720 | } |
be05d201 L |
8721 | else |
8722 | return 1; | |
8723 | ||
8724 | bad_address: | |
8725 | as_bad (_("`%s' is not a valid %s expression"), | |
8726 | operand_string, kind); | |
8727 | return 0; | |
3e73aa7c JH |
8728 | } |
8729 | else | |
8730 | { | |
be05d201 L |
8731 | if (addr_mode != CODE_16BIT) |
8732 | { | |
8733 | /* 32-bit/64-bit checks. */ | |
8734 | if ((i.base_reg | |
8735 | && (addr_mode == CODE_64BIT | |
dc821c5f JB |
8736 | ? !i.base_reg->reg_type.bitfield.qword |
8737 | : !i.base_reg->reg_type.bitfield.dword) | |
be05d201 L |
8738 | && (i.index_reg |
8739 | || (i.base_reg->reg_num | |
8740 | != (addr_mode == CODE_64BIT ? RegRip : RegEip)))) | |
8741 | || (i.index_reg | |
1b54b8d7 JB |
8742 | && !i.index_reg->reg_type.bitfield.xmmword |
8743 | && !i.index_reg->reg_type.bitfield.ymmword | |
8744 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 8745 | && ((addr_mode == CODE_64BIT |
dc821c5f | 8746 | ? !(i.index_reg->reg_type.bitfield.qword |
be05d201 | 8747 | || i.index_reg->reg_num == RegRiz) |
dc821c5f | 8748 | : !(i.index_reg->reg_type.bitfield.dword |
be05d201 L |
8749 | || i.index_reg->reg_num == RegEiz)) |
8750 | || !i.index_reg->reg_type.bitfield.baseindex))) | |
8751 | goto bad_address; | |
8178be5b JB |
8752 | |
8753 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
8754 | if (current_templates->start->base_opcode == 0xf30f1b | |
8755 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
8756 | { | |
8757 | /* They cannot use RIP-relative addressing. */ | |
8758 | if (i.base_reg && i.base_reg->reg_num == RegRip) | |
8759 | { | |
8760 | as_bad (_("`%s' cannot be used here"), operand_string); | |
8761 | return 0; | |
8762 | } | |
8763 | ||
8764 | /* bndldx and bndstx ignore their scale factor. */ | |
8765 | if (current_templates->start->base_opcode != 0xf30f1b | |
8766 | && i.log2_scale_factor) | |
8767 | as_warn (_("register scaling is being ignored here")); | |
8768 | } | |
be05d201 L |
8769 | } |
8770 | else | |
3e73aa7c | 8771 | { |
be05d201 | 8772 | /* 16-bit checks. */ |
3e73aa7c | 8773 | if ((i.base_reg |
dc821c5f | 8774 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 8775 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 8776 | || (i.index_reg |
dc821c5f | 8777 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 8778 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
8779 | || !(i.base_reg |
8780 | && i.base_reg->reg_num < 6 | |
8781 | && i.index_reg->reg_num >= 6 | |
8782 | && i.log2_scale_factor == 0)))) | |
be05d201 | 8783 | goto bad_address; |
3e73aa7c JH |
8784 | } |
8785 | } | |
be05d201 | 8786 | return 1; |
24eab124 | 8787 | } |
252b5132 | 8788 | |
43234a1e L |
8789 | /* Handle vector immediates. */ |
8790 | ||
8791 | static int | |
8792 | RC_SAE_immediate (const char *imm_start) | |
8793 | { | |
8794 | unsigned int match_found, j; | |
8795 | const char *pstr = imm_start; | |
8796 | expressionS *exp; | |
8797 | ||
8798 | if (*pstr != '{') | |
8799 | return 0; | |
8800 | ||
8801 | pstr++; | |
8802 | match_found = 0; | |
8803 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
8804 | { | |
8805 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
8806 | { | |
8807 | if (!i.rounding) | |
8808 | { | |
8809 | rc_op.type = RC_NamesTable[j].type; | |
8810 | rc_op.operand = this_operand; | |
8811 | i.rounding = &rc_op; | |
8812 | } | |
8813 | else | |
8814 | { | |
8815 | as_bad (_("duplicated `%s'"), imm_start); | |
8816 | return 0; | |
8817 | } | |
8818 | pstr += RC_NamesTable[j].len; | |
8819 | match_found = 1; | |
8820 | break; | |
8821 | } | |
8822 | } | |
8823 | if (!match_found) | |
8824 | return 0; | |
8825 | ||
8826 | if (*pstr++ != '}') | |
8827 | { | |
8828 | as_bad (_("Missing '}': '%s'"), imm_start); | |
8829 | return 0; | |
8830 | } | |
8831 | /* RC/SAE immediate string should contain nothing more. */; | |
8832 | if (*pstr != 0) | |
8833 | { | |
8834 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
8835 | return 0; | |
8836 | } | |
8837 | ||
8838 | exp = &im_expressions[i.imm_operands++]; | |
8839 | i.op[this_operand].imms = exp; | |
8840 | ||
8841 | exp->X_op = O_constant; | |
8842 | exp->X_add_number = 0; | |
8843 | exp->X_add_symbol = (symbolS *) 0; | |
8844 | exp->X_op_symbol = (symbolS *) 0; | |
8845 | ||
8846 | i.types[this_operand].bitfield.imm8 = 1; | |
8847 | return 1; | |
8848 | } | |
8849 | ||
8325cc63 JB |
8850 | /* Only string instructions can have a second memory operand, so |
8851 | reduce current_templates to just those if it contains any. */ | |
8852 | static int | |
8853 | maybe_adjust_templates (void) | |
8854 | { | |
8855 | const insn_template *t; | |
8856 | ||
8857 | gas_assert (i.mem_operands == 1); | |
8858 | ||
8859 | for (t = current_templates->start; t < current_templates->end; ++t) | |
8860 | if (t->opcode_modifier.isstring) | |
8861 | break; | |
8862 | ||
8863 | if (t < current_templates->end) | |
8864 | { | |
8865 | static templates aux_templates; | |
8866 | bfd_boolean recheck; | |
8867 | ||
8868 | aux_templates.start = t; | |
8869 | for (; t < current_templates->end; ++t) | |
8870 | if (!t->opcode_modifier.isstring) | |
8871 | break; | |
8872 | aux_templates.end = t; | |
8873 | ||
8874 | /* Determine whether to re-check the first memory operand. */ | |
8875 | recheck = (aux_templates.start != current_templates->start | |
8876 | || t != current_templates->end); | |
8877 | ||
8878 | current_templates = &aux_templates; | |
8879 | ||
8880 | if (recheck) | |
8881 | { | |
8882 | i.mem_operands = 0; | |
8883 | if (i.memop1_string != NULL | |
8884 | && i386_index_check (i.memop1_string) == 0) | |
8885 | return 0; | |
8886 | i.mem_operands = 1; | |
8887 | } | |
8888 | } | |
8889 | ||
8890 | return 1; | |
8891 | } | |
8892 | ||
fc0763e6 | 8893 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 8894 | on error. */ |
252b5132 | 8895 | |
252b5132 | 8896 | static int |
a7619375 | 8897 | i386_att_operand (char *operand_string) |
252b5132 | 8898 | { |
af6bdddf AM |
8899 | const reg_entry *r; |
8900 | char *end_op; | |
24eab124 | 8901 | char *op_string = operand_string; |
252b5132 | 8902 | |
24eab124 | 8903 | if (is_space_char (*op_string)) |
252b5132 RH |
8904 | ++op_string; |
8905 | ||
24eab124 | 8906 | /* We check for an absolute prefix (differentiating, |
47926f60 | 8907 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
8908 | if (*op_string == ABSOLUTE_PREFIX) |
8909 | { | |
8910 | ++op_string; | |
8911 | if (is_space_char (*op_string)) | |
8912 | ++op_string; | |
40fb9820 | 8913 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 8914 | } |
252b5132 | 8915 | |
47926f60 | 8916 | /* Check if operand is a register. */ |
4d1bb795 | 8917 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 8918 | { |
40fb9820 L |
8919 | i386_operand_type temp; |
8920 | ||
24eab124 AM |
8921 | /* Check for a segment override by searching for ':' after a |
8922 | segment register. */ | |
8923 | op_string = end_op; | |
8924 | if (is_space_char (*op_string)) | |
8925 | ++op_string; | |
40fb9820 L |
8926 | if (*op_string == ':' |
8927 | && (r->reg_type.bitfield.sreg2 | |
8928 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
8929 | { |
8930 | switch (r->reg_num) | |
8931 | { | |
8932 | case 0: | |
8933 | i.seg[i.mem_operands] = &es; | |
8934 | break; | |
8935 | case 1: | |
8936 | i.seg[i.mem_operands] = &cs; | |
8937 | break; | |
8938 | case 2: | |
8939 | i.seg[i.mem_operands] = &ss; | |
8940 | break; | |
8941 | case 3: | |
8942 | i.seg[i.mem_operands] = &ds; | |
8943 | break; | |
8944 | case 4: | |
8945 | i.seg[i.mem_operands] = &fs; | |
8946 | break; | |
8947 | case 5: | |
8948 | i.seg[i.mem_operands] = &gs; | |
8949 | break; | |
8950 | } | |
252b5132 | 8951 | |
24eab124 | 8952 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
8953 | ++op_string; |
8954 | if (is_space_char (*op_string)) | |
24eab124 | 8955 | ++op_string; |
252b5132 | 8956 | |
24eab124 AM |
8957 | if (!is_digit_char (*op_string) |
8958 | && !is_identifier_char (*op_string) | |
8959 | && *op_string != '(' | |
8960 | && *op_string != ABSOLUTE_PREFIX) | |
8961 | { | |
8962 | as_bad (_("bad memory operand `%s'"), op_string); | |
8963 | return 0; | |
8964 | } | |
47926f60 | 8965 | /* Handle case of %es:*foo. */ |
24eab124 AM |
8966 | if (*op_string == ABSOLUTE_PREFIX) |
8967 | { | |
8968 | ++op_string; | |
8969 | if (is_space_char (*op_string)) | |
8970 | ++op_string; | |
40fb9820 | 8971 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
8972 | } |
8973 | goto do_memory_reference; | |
8974 | } | |
43234a1e L |
8975 | |
8976 | /* Handle vector operations. */ | |
8977 | if (*op_string == '{') | |
8978 | { | |
8979 | op_string = check_VecOperations (op_string, NULL); | |
8980 | if (op_string == NULL) | |
8981 | return 0; | |
8982 | } | |
8983 | ||
24eab124 AM |
8984 | if (*op_string) |
8985 | { | |
d0b47220 | 8986 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
8987 | return 0; |
8988 | } | |
40fb9820 L |
8989 | temp = r->reg_type; |
8990 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
8991 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8992 | temp); | |
7d5e4556 | 8993 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 8994 | i.op[this_operand].regs = r; |
24eab124 AM |
8995 | i.reg_operands++; |
8996 | } | |
af6bdddf AM |
8997 | else if (*op_string == REGISTER_PREFIX) |
8998 | { | |
8999 | as_bad (_("bad register name `%s'"), op_string); | |
9000 | return 0; | |
9001 | } | |
24eab124 | 9002 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 9003 | { |
24eab124 | 9004 | ++op_string; |
40fb9820 | 9005 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 9006 | { |
d0b47220 | 9007 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
9008 | return 0; |
9009 | } | |
9010 | if (!i386_immediate (op_string)) | |
9011 | return 0; | |
9012 | } | |
43234a1e L |
9013 | else if (RC_SAE_immediate (operand_string)) |
9014 | { | |
9015 | /* If it is a RC or SAE immediate, do nothing. */ | |
9016 | ; | |
9017 | } | |
24eab124 AM |
9018 | else if (is_digit_char (*op_string) |
9019 | || is_identifier_char (*op_string) | |
d02603dc | 9020 | || *op_string == '"' |
e5cb08ac | 9021 | || *op_string == '(') |
24eab124 | 9022 | { |
47926f60 | 9023 | /* This is a memory reference of some sort. */ |
af6bdddf | 9024 | char *base_string; |
252b5132 | 9025 | |
47926f60 | 9026 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
9027 | char *displacement_string_start; |
9028 | char *displacement_string_end; | |
43234a1e | 9029 | char *vop_start; |
252b5132 | 9030 | |
24eab124 | 9031 | do_memory_reference: |
8325cc63 JB |
9032 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
9033 | return 0; | |
24eab124 | 9034 | if ((i.mem_operands == 1 |
40fb9820 | 9035 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
9036 | || i.mem_operands == 2) |
9037 | { | |
9038 | as_bad (_("too many memory references for `%s'"), | |
9039 | current_templates->start->name); | |
9040 | return 0; | |
9041 | } | |
252b5132 | 9042 | |
24eab124 AM |
9043 | /* Check for base index form. We detect the base index form by |
9044 | looking for an ')' at the end of the operand, searching | |
9045 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
9046 | after the '('. */ | |
af6bdddf | 9047 | base_string = op_string + strlen (op_string); |
c3332e24 | 9048 | |
43234a1e L |
9049 | /* Handle vector operations. */ |
9050 | vop_start = strchr (op_string, '{'); | |
9051 | if (vop_start && vop_start < base_string) | |
9052 | { | |
9053 | if (check_VecOperations (vop_start, base_string) == NULL) | |
9054 | return 0; | |
9055 | base_string = vop_start; | |
9056 | } | |
9057 | ||
af6bdddf AM |
9058 | --base_string; |
9059 | if (is_space_char (*base_string)) | |
9060 | --base_string; | |
252b5132 | 9061 | |
47926f60 | 9062 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
9063 | displacement_string_start = op_string; |
9064 | displacement_string_end = base_string + 1; | |
252b5132 | 9065 | |
24eab124 AM |
9066 | if (*base_string == ')') |
9067 | { | |
af6bdddf | 9068 | char *temp_string; |
24eab124 AM |
9069 | unsigned int parens_balanced = 1; |
9070 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 9071 | equal, so this loop will not be infinite. */ |
24eab124 AM |
9072 | do |
9073 | { | |
9074 | base_string--; | |
9075 | if (*base_string == ')') | |
9076 | parens_balanced++; | |
9077 | if (*base_string == '(') | |
9078 | parens_balanced--; | |
9079 | } | |
9080 | while (parens_balanced); | |
c3332e24 | 9081 | |
af6bdddf | 9082 | temp_string = base_string; |
c3332e24 | 9083 | |
24eab124 | 9084 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
9085 | ++base_string; |
9086 | if (is_space_char (*base_string)) | |
24eab124 | 9087 | ++base_string; |
252b5132 | 9088 | |
af6bdddf | 9089 | if (*base_string == ',' |
4eed87de AM |
9090 | || ((i.base_reg = parse_register (base_string, &end_op)) |
9091 | != NULL)) | |
252b5132 | 9092 | { |
af6bdddf | 9093 | displacement_string_end = temp_string; |
252b5132 | 9094 | |
40fb9820 | 9095 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 9096 | |
af6bdddf | 9097 | if (i.base_reg) |
24eab124 | 9098 | { |
24eab124 AM |
9099 | base_string = end_op; |
9100 | if (is_space_char (*base_string)) | |
9101 | ++base_string; | |
af6bdddf AM |
9102 | } |
9103 | ||
9104 | /* There may be an index reg or scale factor here. */ | |
9105 | if (*base_string == ',') | |
9106 | { | |
9107 | ++base_string; | |
9108 | if (is_space_char (*base_string)) | |
9109 | ++base_string; | |
9110 | ||
4eed87de AM |
9111 | if ((i.index_reg = parse_register (base_string, &end_op)) |
9112 | != NULL) | |
24eab124 | 9113 | { |
af6bdddf | 9114 | base_string = end_op; |
24eab124 AM |
9115 | if (is_space_char (*base_string)) |
9116 | ++base_string; | |
af6bdddf AM |
9117 | if (*base_string == ',') |
9118 | { | |
9119 | ++base_string; | |
9120 | if (is_space_char (*base_string)) | |
9121 | ++base_string; | |
9122 | } | |
e5cb08ac | 9123 | else if (*base_string != ')') |
af6bdddf | 9124 | { |
4eed87de AM |
9125 | as_bad (_("expecting `,' or `)' " |
9126 | "after index register in `%s'"), | |
af6bdddf AM |
9127 | operand_string); |
9128 | return 0; | |
9129 | } | |
24eab124 | 9130 | } |
af6bdddf | 9131 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 9132 | { |
f76bf5e0 L |
9133 | end_op = strchr (base_string, ','); |
9134 | if (end_op) | |
9135 | *end_op = '\0'; | |
af6bdddf | 9136 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
9137 | return 0; |
9138 | } | |
252b5132 | 9139 | |
47926f60 | 9140 | /* Check for scale factor. */ |
551c1ca1 | 9141 | if (*base_string != ')') |
af6bdddf | 9142 | { |
551c1ca1 AM |
9143 | char *end_scale = i386_scale (base_string); |
9144 | ||
9145 | if (!end_scale) | |
af6bdddf | 9146 | return 0; |
24eab124 | 9147 | |
551c1ca1 | 9148 | base_string = end_scale; |
af6bdddf AM |
9149 | if (is_space_char (*base_string)) |
9150 | ++base_string; | |
9151 | if (*base_string != ')') | |
9152 | { | |
4eed87de AM |
9153 | as_bad (_("expecting `)' " |
9154 | "after scale factor in `%s'"), | |
af6bdddf AM |
9155 | operand_string); |
9156 | return 0; | |
9157 | } | |
9158 | } | |
9159 | else if (!i.index_reg) | |
24eab124 | 9160 | { |
4eed87de AM |
9161 | as_bad (_("expecting index register or scale factor " |
9162 | "after `,'; got '%c'"), | |
af6bdddf | 9163 | *base_string); |
24eab124 AM |
9164 | return 0; |
9165 | } | |
9166 | } | |
af6bdddf | 9167 | else if (*base_string != ')') |
24eab124 | 9168 | { |
4eed87de AM |
9169 | as_bad (_("expecting `,' or `)' " |
9170 | "after base register in `%s'"), | |
af6bdddf | 9171 | operand_string); |
24eab124 AM |
9172 | return 0; |
9173 | } | |
c3332e24 | 9174 | } |
af6bdddf | 9175 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 9176 | { |
f76bf5e0 L |
9177 | end_op = strchr (base_string, ','); |
9178 | if (end_op) | |
9179 | *end_op = '\0'; | |
af6bdddf | 9180 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 9181 | return 0; |
c3332e24 | 9182 | } |
24eab124 AM |
9183 | } |
9184 | ||
9185 | /* If there's an expression beginning the operand, parse it, | |
9186 | assuming displacement_string_start and | |
9187 | displacement_string_end are meaningful. */ | |
9188 | if (displacement_string_start != displacement_string_end) | |
9189 | { | |
9190 | if (!i386_displacement (displacement_string_start, | |
9191 | displacement_string_end)) | |
9192 | return 0; | |
9193 | } | |
9194 | ||
9195 | /* Special case for (%dx) while doing input/output op. */ | |
9196 | if (i.base_reg | |
0dfbf9d7 L |
9197 | && operand_type_equal (&i.base_reg->reg_type, |
9198 | ®16_inoutportreg) | |
24eab124 AM |
9199 | && i.index_reg == 0 |
9200 | && i.log2_scale_factor == 0 | |
9201 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 9202 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 9203 | { |
65da13b5 | 9204 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
9205 | return 1; |
9206 | } | |
9207 | ||
eecb386c AM |
9208 | if (i386_index_check (operand_string) == 0) |
9209 | return 0; | |
5c07affc | 9210 | i.types[this_operand].bitfield.mem = 1; |
8325cc63 JB |
9211 | if (i.mem_operands == 0) |
9212 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
9213 | i.mem_operands++; |
9214 | } | |
9215 | else | |
ce8a8b2f AM |
9216 | { |
9217 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
9218 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
9219 | output_invalid (*op_string), | |
9220 | this_operand + 1, | |
9221 | op_string); | |
9222 | return 0; | |
9223 | } | |
47926f60 | 9224 | return 1; /* Normal return. */ |
252b5132 RH |
9225 | } |
9226 | \f | |
fa94de6b RM |
9227 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
9228 | that an rs_machine_dependent frag may reach. */ | |
9229 | ||
9230 | unsigned int | |
9231 | i386_frag_max_var (fragS *frag) | |
9232 | { | |
9233 | /* The only relaxable frags are for jumps. | |
9234 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
9235 | gas_assert (frag->fr_type == rs_machine_dependent); | |
9236 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
9237 | } | |
9238 | ||
b084df0b L |
9239 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9240 | static int | |
8dcea932 | 9241 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
9242 | { |
9243 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
9244 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
9245 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
9246 | return 0; | |
9247 | ||
9248 | if (!S_IS_EXTERNAL (fr_symbol)) | |
9249 | /* Symbol may be weak or local. */ | |
9250 | return !S_IS_WEAK (fr_symbol); | |
9251 | ||
8dcea932 L |
9252 | /* Global symbols with non-default visibility can't be preempted. */ |
9253 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
9254 | return 1; | |
9255 | ||
9256 | if (fr_var != NO_RELOC) | |
9257 | switch ((enum bfd_reloc_code_real) fr_var) | |
9258 | { | |
9259 | case BFD_RELOC_386_PLT32: | |
9260 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 9261 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
9262 | return 0; |
9263 | default: | |
9264 | abort (); | |
9265 | } | |
9266 | ||
b084df0b L |
9267 | /* Global symbols with default visibility in a shared library may be |
9268 | preempted by another definition. */ | |
8dcea932 | 9269 | return !shared; |
b084df0b L |
9270 | } |
9271 | #endif | |
9272 | ||
ee7fcc42 AM |
9273 | /* md_estimate_size_before_relax() |
9274 | ||
9275 | Called just before relax() for rs_machine_dependent frags. The x86 | |
9276 | assembler uses these frags to handle variable size jump | |
9277 | instructions. | |
9278 | ||
9279 | Any symbol that is now undefined will not become defined. | |
9280 | Return the correct fr_subtype in the frag. | |
9281 | Return the initial "guess for variable size of frag" to caller. | |
9282 | The guess is actually the growth beyond the fixed part. Whatever | |
9283 | we do to grow the fixed or variable part contributes to our | |
9284 | returned value. */ | |
9285 | ||
252b5132 | 9286 | int |
7016a5d5 | 9287 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 9288 | { |
252b5132 | 9289 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
9290 | check for un-relaxable symbols. On an ELF system, we can't relax |
9291 | an externally visible symbol, because it may be overridden by a | |
9292 | shared library. */ | |
9293 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 9294 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9295 | || (IS_ELF |
8dcea932 L |
9296 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
9297 | fragP->fr_var)) | |
fbeb56a4 DK |
9298 | #endif |
9299 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 9300 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 9301 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
9302 | #endif |
9303 | ) | |
252b5132 | 9304 | { |
b98ef147 AM |
9305 | /* Symbol is undefined in this segment, or we need to keep a |
9306 | reloc so that weak symbols can be overridden. */ | |
9307 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 9308 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
9309 | unsigned char *opcode; |
9310 | int old_fr_fix; | |
f6af82bd | 9311 | |
ee7fcc42 | 9312 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 9313 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 9314 | else if (size == 2) |
f6af82bd AM |
9315 | reloc_type = BFD_RELOC_16_PCREL; |
9316 | else | |
9317 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 9318 | |
ee7fcc42 AM |
9319 | old_fr_fix = fragP->fr_fix; |
9320 | opcode = (unsigned char *) fragP->fr_opcode; | |
9321 | ||
fddf5b5b | 9322 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 9323 | { |
fddf5b5b AM |
9324 | case UNCOND_JUMP: |
9325 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 9326 | opcode[0] = 0xe9; |
252b5132 | 9327 | fragP->fr_fix += size; |
062cd5e7 AS |
9328 | fix_new (fragP, old_fr_fix, size, |
9329 | fragP->fr_symbol, | |
9330 | fragP->fr_offset, 1, | |
9331 | reloc_type); | |
252b5132 RH |
9332 | break; |
9333 | ||
fddf5b5b | 9334 | case COND_JUMP86: |
412167cb AM |
9335 | if (size == 2 |
9336 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
9337 | { |
9338 | /* Negate the condition, and branch past an | |
9339 | unconditional jump. */ | |
9340 | opcode[0] ^= 1; | |
9341 | opcode[1] = 3; | |
9342 | /* Insert an unconditional jump. */ | |
9343 | opcode[2] = 0xe9; | |
9344 | /* We added two extra opcode bytes, and have a two byte | |
9345 | offset. */ | |
9346 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
9347 | fix_new (fragP, old_fr_fix + 2, 2, |
9348 | fragP->fr_symbol, | |
9349 | fragP->fr_offset, 1, | |
9350 | reloc_type); | |
fddf5b5b AM |
9351 | break; |
9352 | } | |
9353 | /* Fall through. */ | |
9354 | ||
9355 | case COND_JUMP: | |
412167cb AM |
9356 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
9357 | { | |
3e02c1cc AM |
9358 | fixS *fixP; |
9359 | ||
412167cb | 9360 | fragP->fr_fix += 1; |
3e02c1cc AM |
9361 | fixP = fix_new (fragP, old_fr_fix, 1, |
9362 | fragP->fr_symbol, | |
9363 | fragP->fr_offset, 1, | |
9364 | BFD_RELOC_8_PCREL); | |
9365 | fixP->fx_signed = 1; | |
412167cb AM |
9366 | break; |
9367 | } | |
93c2a809 | 9368 | |
24eab124 | 9369 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 9370 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 9371 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 9372 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
9373 | /* We've added an opcode byte. */ |
9374 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
9375 | fix_new (fragP, old_fr_fix + 1, size, |
9376 | fragP->fr_symbol, | |
9377 | fragP->fr_offset, 1, | |
9378 | reloc_type); | |
252b5132 | 9379 | break; |
fddf5b5b AM |
9380 | |
9381 | default: | |
9382 | BAD_CASE (fragP->fr_subtype); | |
9383 | break; | |
252b5132 RH |
9384 | } |
9385 | frag_wane (fragP); | |
ee7fcc42 | 9386 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 9387 | } |
93c2a809 | 9388 | |
93c2a809 AM |
9389 | /* Guess size depending on current relax state. Initially the relax |
9390 | state will correspond to a short jump and we return 1, because | |
9391 | the variable part of the frag (the branch offset) is one byte | |
9392 | long. However, we can relax a section more than once and in that | |
9393 | case we must either set fr_subtype back to the unrelaxed state, | |
9394 | or return the value for the appropriate branch. */ | |
9395 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
9396 | } |
9397 | ||
47926f60 KH |
9398 | /* Called after relax() is finished. |
9399 | ||
9400 | In: Address of frag. | |
9401 | fr_type == rs_machine_dependent. | |
9402 | fr_subtype is what the address relaxed to. | |
9403 | ||
9404 | Out: Any fixSs and constants are set up. | |
9405 | Caller will turn frag into a ".space 0". */ | |
9406 | ||
252b5132 | 9407 | void |
7016a5d5 TG |
9408 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
9409 | fragS *fragP) | |
252b5132 | 9410 | { |
29b0f896 | 9411 | unsigned char *opcode; |
252b5132 | 9412 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
9413 | offsetT target_address; |
9414 | offsetT opcode_address; | |
252b5132 | 9415 | unsigned int extension = 0; |
847f7ad4 | 9416 | offsetT displacement_from_opcode_start; |
252b5132 RH |
9417 | |
9418 | opcode = (unsigned char *) fragP->fr_opcode; | |
9419 | ||
47926f60 | 9420 | /* Address we want to reach in file space. */ |
252b5132 | 9421 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 9422 | |
47926f60 | 9423 | /* Address opcode resides at in file space. */ |
252b5132 RH |
9424 | opcode_address = fragP->fr_address + fragP->fr_fix; |
9425 | ||
47926f60 | 9426 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
9427 | displacement_from_opcode_start = target_address - opcode_address; |
9428 | ||
fddf5b5b | 9429 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 9430 | { |
47926f60 KH |
9431 | /* Don't have to change opcode. */ |
9432 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 9433 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
9434 | } |
9435 | else | |
9436 | { | |
9437 | if (no_cond_jump_promotion | |
9438 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
9439 | as_warn_where (fragP->fr_file, fragP->fr_line, |
9440 | _("long jump required")); | |
252b5132 | 9441 | |
fddf5b5b AM |
9442 | switch (fragP->fr_subtype) |
9443 | { | |
9444 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
9445 | extension = 4; /* 1 opcode + 4 displacement */ | |
9446 | opcode[0] = 0xe9; | |
9447 | where_to_put_displacement = &opcode[1]; | |
9448 | break; | |
252b5132 | 9449 | |
fddf5b5b AM |
9450 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
9451 | extension = 2; /* 1 opcode + 2 displacement */ | |
9452 | opcode[0] = 0xe9; | |
9453 | where_to_put_displacement = &opcode[1]; | |
9454 | break; | |
252b5132 | 9455 | |
fddf5b5b AM |
9456 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
9457 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
9458 | extension = 5; /* 2 opcode + 4 displacement */ | |
9459 | opcode[1] = opcode[0] + 0x10; | |
9460 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9461 | where_to_put_displacement = &opcode[2]; | |
9462 | break; | |
252b5132 | 9463 | |
fddf5b5b AM |
9464 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
9465 | extension = 3; /* 2 opcode + 2 displacement */ | |
9466 | opcode[1] = opcode[0] + 0x10; | |
9467 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9468 | where_to_put_displacement = &opcode[2]; | |
9469 | break; | |
252b5132 | 9470 | |
fddf5b5b AM |
9471 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
9472 | extension = 4; | |
9473 | opcode[0] ^= 1; | |
9474 | opcode[1] = 3; | |
9475 | opcode[2] = 0xe9; | |
9476 | where_to_put_displacement = &opcode[3]; | |
9477 | break; | |
9478 | ||
9479 | default: | |
9480 | BAD_CASE (fragP->fr_subtype); | |
9481 | break; | |
9482 | } | |
252b5132 | 9483 | } |
fddf5b5b | 9484 | |
7b81dfbb AJ |
9485 | /* If size if less then four we are sure that the operand fits, |
9486 | but if it's 4, then it could be that the displacement is larger | |
9487 | then -/+ 2GB. */ | |
9488 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
9489 | && object_64bit | |
9490 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
9491 | + ((addressT) 1 << 31)) |
9492 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
9493 | { |
9494 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9495 | _("jump target out of range")); | |
9496 | /* Make us emit 0. */ | |
9497 | displacement_from_opcode_start = extension; | |
9498 | } | |
47926f60 | 9499 | /* Now put displacement after opcode. */ |
252b5132 RH |
9500 | md_number_to_chars ((char *) where_to_put_displacement, |
9501 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 9502 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
9503 | fragP->fr_fix += extension; |
9504 | } | |
9505 | \f | |
7016a5d5 | 9506 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
9507 | by our caller that we have all the info we need to fix it up. |
9508 | ||
7016a5d5 TG |
9509 | Parameter valP is the pointer to the value of the bits. |
9510 | ||
252b5132 RH |
9511 | On the 386, immediates, displacements, and data pointers are all in |
9512 | the same (little-endian) format, so we don't need to care about which | |
9513 | we are handling. */ | |
9514 | ||
94f592af | 9515 | void |
7016a5d5 | 9516 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 9517 | { |
94f592af | 9518 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 9519 | valueT value = *valP; |
252b5132 | 9520 | |
f86103b7 | 9521 | #if !defined (TE_Mach) |
93382f6d AM |
9522 | if (fixP->fx_pcrel) |
9523 | { | |
9524 | switch (fixP->fx_r_type) | |
9525 | { | |
5865bb77 ILT |
9526 | default: |
9527 | break; | |
9528 | ||
d6ab8113 JB |
9529 | case BFD_RELOC_64: |
9530 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
9531 | break; | |
93382f6d | 9532 | case BFD_RELOC_32: |
ae8887b5 | 9533 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
9534 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
9535 | break; | |
9536 | case BFD_RELOC_16: | |
9537 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
9538 | break; | |
9539 | case BFD_RELOC_8: | |
9540 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
9541 | break; | |
9542 | } | |
9543 | } | |
252b5132 | 9544 | |
a161fe53 | 9545 | if (fixP->fx_addsy != NULL |
31312f95 | 9546 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 9547 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 9548 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 9549 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 9550 | && !use_rela_relocations) |
252b5132 | 9551 | { |
31312f95 AM |
9552 | /* This is a hack. There should be a better way to handle this. |
9553 | This covers for the fact that bfd_install_relocation will | |
9554 | subtract the current location (for partial_inplace, PC relative | |
9555 | relocations); see more below. */ | |
252b5132 | 9556 | #ifndef OBJ_AOUT |
718ddfc0 | 9557 | if (IS_ELF |
252b5132 RH |
9558 | #ifdef TE_PE |
9559 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
9560 | #endif | |
9561 | ) | |
9562 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9563 | #endif | |
9564 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 9565 | if (IS_ELF) |
252b5132 | 9566 | { |
6539b54b | 9567 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 9568 | |
6539b54b | 9569 | if ((sym_seg == seg |
2f66722d | 9570 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 9571 | && sym_seg != absolute_section)) |
af65af87 | 9572 | && !generic_force_reloc (fixP)) |
2f66722d AM |
9573 | { |
9574 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
9575 | bfd_install_relocation subtracts them out again. I think |
9576 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
9577 | it. FIXME. */ |
9578 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9579 | } | |
252b5132 RH |
9580 | } |
9581 | #endif | |
9582 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
9583 | /* For some reason, the PE format does not store a |
9584 | section address offset for a PC relative symbol. */ | |
9585 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 9586 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
9587 | value += md_pcrel_from (fixP); |
9588 | #endif | |
9589 | } | |
fbeb56a4 | 9590 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
9591 | if (fixP->fx_addsy != NULL |
9592 | && S_IS_WEAK (fixP->fx_addsy) | |
9593 | /* PR 16858: Do not modify weak function references. */ | |
9594 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 9595 | { |
296a8689 NC |
9596 | #if !defined (TE_PEP) |
9597 | /* For x86 PE weak function symbols are neither PC-relative | |
9598 | nor do they set S_IS_FUNCTION. So the only reliable way | |
9599 | to detect them is to check the flags of their containing | |
9600 | section. */ | |
9601 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
9602 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
9603 | ; | |
9604 | else | |
9605 | #endif | |
fbeb56a4 DK |
9606 | value -= S_GET_VALUE (fixP->fx_addsy); |
9607 | } | |
9608 | #endif | |
252b5132 RH |
9609 | |
9610 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 9611 | and we must not disappoint it. */ |
252b5132 | 9612 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9613 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
9614 | switch (fixP->fx_r_type) |
9615 | { | |
9616 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 9617 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
9618 | /* Make the jump instruction point to the address of the operand. At |
9619 | runtime we merely add the offset to the actual PLT entry. */ | |
9620 | value = -4; | |
9621 | break; | |
31312f95 | 9622 | |
13ae64f3 JJ |
9623 | case BFD_RELOC_386_TLS_GD: |
9624 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 9625 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
9626 | case BFD_RELOC_386_TLS_IE: |
9627 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 9628 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
9629 | case BFD_RELOC_X86_64_TLSGD: |
9630 | case BFD_RELOC_X86_64_TLSLD: | |
9631 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 9632 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
9633 | value = 0; /* Fully resolved at runtime. No addend. */ |
9634 | /* Fallthrough */ | |
9635 | case BFD_RELOC_386_TLS_LE: | |
9636 | case BFD_RELOC_386_TLS_LDO_32: | |
9637 | case BFD_RELOC_386_TLS_LE_32: | |
9638 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 9639 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 9640 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 9641 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
9642 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
9643 | break; | |
9644 | ||
67a4f2b7 AO |
9645 | case BFD_RELOC_386_TLS_DESC_CALL: |
9646 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9647 | value = 0; /* Fully resolved at runtime. No addend. */ | |
9648 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
9649 | fixP->fx_done = 0; | |
9650 | return; | |
9651 | ||
47926f60 KH |
9652 | case BFD_RELOC_VTABLE_INHERIT: |
9653 | case BFD_RELOC_VTABLE_ENTRY: | |
9654 | fixP->fx_done = 0; | |
94f592af | 9655 | return; |
47926f60 KH |
9656 | |
9657 | default: | |
9658 | break; | |
9659 | } | |
9660 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 9661 | *valP = value; |
f86103b7 | 9662 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 9663 | |
3e73aa7c | 9664 | /* Are we finished with this relocation now? */ |
c6682705 | 9665 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 9666 | fixP->fx_done = 1; |
fbeb56a4 DK |
9667 | #if defined (OBJ_COFF) && defined (TE_PE) |
9668 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
9669 | { | |
9670 | fixP->fx_done = 0; | |
9671 | /* Remember value for tc_gen_reloc. */ | |
9672 | fixP->fx_addnumber = value; | |
9673 | /* Clear out the frag for now. */ | |
9674 | value = 0; | |
9675 | } | |
9676 | #endif | |
3e73aa7c JH |
9677 | else if (use_rela_relocations) |
9678 | { | |
9679 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
9680 | /* Remember value for tc_gen_reloc. */ |
9681 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
9682 | value = 0; |
9683 | } | |
f86103b7 | 9684 | |
94f592af | 9685 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 9686 | } |
252b5132 | 9687 | \f |
6d4af3c2 | 9688 | const char * |
499ac353 | 9689 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 9690 | { |
499ac353 NC |
9691 | /* This outputs the LITTLENUMs in REVERSE order; |
9692 | in accord with the bigendian 386. */ | |
9693 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
9694 | } |
9695 | \f | |
2d545b82 | 9696 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 9697 | |
252b5132 | 9698 | static char * |
e3bb37b5 | 9699 | output_invalid (int c) |
252b5132 | 9700 | { |
3882b010 | 9701 | if (ISPRINT (c)) |
f9f21a03 L |
9702 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
9703 | "'%c'", c); | |
252b5132 | 9704 | else |
f9f21a03 | 9705 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 9706 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
9707 | return output_invalid_buf; |
9708 | } | |
9709 | ||
af6bdddf | 9710 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
9711 | |
9712 | static const reg_entry * | |
4d1bb795 | 9713 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 9714 | { |
af6bdddf AM |
9715 | char *s = reg_string; |
9716 | char *p; | |
252b5132 RH |
9717 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
9718 | const reg_entry *r; | |
9719 | ||
9720 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
9721 | if (*s == REGISTER_PREFIX) | |
9722 | ++s; | |
9723 | ||
9724 | if (is_space_char (*s)) | |
9725 | ++s; | |
9726 | ||
9727 | p = reg_name_given; | |
af6bdddf | 9728 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
9729 | { |
9730 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
9731 | return (const reg_entry *) NULL; |
9732 | s++; | |
252b5132 RH |
9733 | } |
9734 | ||
6588847e DN |
9735 | /* For naked regs, make sure that we are not dealing with an identifier. |
9736 | This prevents confusing an identifier like `eax_var' with register | |
9737 | `eax'. */ | |
9738 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
9739 | return (const reg_entry *) NULL; | |
9740 | ||
af6bdddf | 9741 | *end_op = s; |
252b5132 RH |
9742 | |
9743 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
9744 | ||
5f47d35b | 9745 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 9746 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 9747 | { |
5f47d35b AM |
9748 | if (is_space_char (*s)) |
9749 | ++s; | |
9750 | if (*s == '(') | |
9751 | { | |
af6bdddf | 9752 | ++s; |
5f47d35b AM |
9753 | if (is_space_char (*s)) |
9754 | ++s; | |
9755 | if (*s >= '0' && *s <= '7') | |
9756 | { | |
db557034 | 9757 | int fpr = *s - '0'; |
af6bdddf | 9758 | ++s; |
5f47d35b AM |
9759 | if (is_space_char (*s)) |
9760 | ++s; | |
9761 | if (*s == ')') | |
9762 | { | |
9763 | *end_op = s + 1; | |
1e9cc1c2 | 9764 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
9765 | know (r); |
9766 | return r + fpr; | |
5f47d35b | 9767 | } |
5f47d35b | 9768 | } |
47926f60 | 9769 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
9770 | return (const reg_entry *) NULL; |
9771 | } | |
9772 | } | |
9773 | ||
a60de03c JB |
9774 | if (r == NULL || allow_pseudo_reg) |
9775 | return r; | |
9776 | ||
0dfbf9d7 | 9777 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
9778 | return (const reg_entry *) NULL; |
9779 | ||
dc821c5f | 9780 | if ((r->reg_type.bitfield.dword |
192dc9c6 JB |
9781 | || r->reg_type.bitfield.sreg3 |
9782 | || r->reg_type.bitfield.control | |
9783 | || r->reg_type.bitfield.debug | |
9784 | || r->reg_type.bitfield.test) | |
9785 | && !cpu_arch_flags.bitfield.cpui386) | |
9786 | return (const reg_entry *) NULL; | |
9787 | ||
ca0d63fe | 9788 | if (r->reg_type.bitfield.tbyte |
309d3373 JB |
9789 | && !cpu_arch_flags.bitfield.cpu8087 |
9790 | && !cpu_arch_flags.bitfield.cpu287 | |
9791 | && !cpu_arch_flags.bitfield.cpu387) | |
9792 | return (const reg_entry *) NULL; | |
9793 | ||
1848e567 | 9794 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx) |
192dc9c6 JB |
9795 | return (const reg_entry *) NULL; |
9796 | ||
1b54b8d7 | 9797 | if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm) |
192dc9c6 JB |
9798 | return (const reg_entry *) NULL; |
9799 | ||
1b54b8d7 | 9800 | if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm) |
40f12533 L |
9801 | return (const reg_entry *) NULL; |
9802 | ||
1b54b8d7 | 9803 | if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm) |
1848e567 L |
9804 | return (const reg_entry *) NULL; |
9805 | ||
9806 | if (r->reg_type.bitfield.regmask | |
9807 | && !cpu_arch_flags.bitfield.cpuregmask) | |
43234a1e L |
9808 | return (const reg_entry *) NULL; |
9809 | ||
db51cc60 | 9810 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 9811 | if (!allow_index_reg |
db51cc60 L |
9812 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
9813 | return (const reg_entry *) NULL; | |
9814 | ||
43234a1e L |
9815 | /* Upper 16 vector register is only available with VREX in 64bit |
9816 | mode. */ | |
9817 | if ((r->reg_flags & RegVRex)) | |
9818 | { | |
86fa6981 L |
9819 | if (i.vec_encoding == vex_encoding_default) |
9820 | i.vec_encoding = vex_encoding_evex; | |
9821 | ||
43234a1e | 9822 | if (!cpu_arch_flags.bitfield.cpuvrex |
86fa6981 | 9823 | || i.vec_encoding != vex_encoding_evex |
43234a1e L |
9824 | || flag_code != CODE_64BIT) |
9825 | return (const reg_entry *) NULL; | |
43234a1e L |
9826 | } |
9827 | ||
a60de03c | 9828 | if (((r->reg_flags & (RegRex64 | RegRex)) |
dc821c5f | 9829 | || r->reg_type.bitfield.qword) |
40fb9820 | 9830 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 9831 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 9832 | && flag_code != CODE_64BIT) |
20f0a1fc | 9833 | return (const reg_entry *) NULL; |
1ae00879 | 9834 | |
b7240065 JB |
9835 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
9836 | return (const reg_entry *) NULL; | |
9837 | ||
252b5132 RH |
9838 | return r; |
9839 | } | |
4d1bb795 JB |
9840 | |
9841 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
9842 | ||
9843 | static const reg_entry * | |
9844 | parse_register (char *reg_string, char **end_op) | |
9845 | { | |
9846 | const reg_entry *r; | |
9847 | ||
9848 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
9849 | r = parse_real_register (reg_string, end_op); | |
9850 | else | |
9851 | r = NULL; | |
9852 | if (!r) | |
9853 | { | |
9854 | char *save = input_line_pointer; | |
9855 | char c; | |
9856 | symbolS *symbolP; | |
9857 | ||
9858 | input_line_pointer = reg_string; | |
d02603dc | 9859 | c = get_symbol_name (®_string); |
4d1bb795 JB |
9860 | symbolP = symbol_find (reg_string); |
9861 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
9862 | { | |
9863 | const expressionS *e = symbol_get_value_expression (symbolP); | |
9864 | ||
0398aac5 | 9865 | know (e->X_op == O_register); |
4eed87de | 9866 | know (e->X_add_number >= 0 |
c3fe08fa | 9867 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 9868 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 9869 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 9870 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
9871 | *end_op = input_line_pointer; |
9872 | } | |
9873 | *input_line_pointer = c; | |
9874 | input_line_pointer = save; | |
9875 | } | |
9876 | return r; | |
9877 | } | |
9878 | ||
9879 | int | |
9880 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
9881 | { | |
9882 | const reg_entry *r; | |
9883 | char *end = input_line_pointer; | |
9884 | ||
9885 | *end = *nextcharP; | |
9886 | r = parse_register (name, &input_line_pointer); | |
9887 | if (r && end <= input_line_pointer) | |
9888 | { | |
9889 | *nextcharP = *input_line_pointer; | |
9890 | *input_line_pointer = 0; | |
9891 | e->X_op = O_register; | |
9892 | e->X_add_number = r - i386_regtab; | |
9893 | return 1; | |
9894 | } | |
9895 | input_line_pointer = end; | |
9896 | *end = 0; | |
ee86248c | 9897 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
9898 | } |
9899 | ||
9900 | void | |
9901 | md_operand (expressionS *e) | |
9902 | { | |
ee86248c JB |
9903 | char *end; |
9904 | const reg_entry *r; | |
4d1bb795 | 9905 | |
ee86248c JB |
9906 | switch (*input_line_pointer) |
9907 | { | |
9908 | case REGISTER_PREFIX: | |
9909 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
9910 | if (r) |
9911 | { | |
9912 | e->X_op = O_register; | |
9913 | e->X_add_number = r - i386_regtab; | |
9914 | input_line_pointer = end; | |
9915 | } | |
ee86248c JB |
9916 | break; |
9917 | ||
9918 | case '[': | |
9c2799c2 | 9919 | gas_assert (intel_syntax); |
ee86248c JB |
9920 | end = input_line_pointer++; |
9921 | expression (e); | |
9922 | if (*input_line_pointer == ']') | |
9923 | { | |
9924 | ++input_line_pointer; | |
9925 | e->X_op_symbol = make_expr_symbol (e); | |
9926 | e->X_add_symbol = NULL; | |
9927 | e->X_add_number = 0; | |
9928 | e->X_op = O_index; | |
9929 | } | |
9930 | else | |
9931 | { | |
9932 | e->X_op = O_absent; | |
9933 | input_line_pointer = end; | |
9934 | } | |
9935 | break; | |
4d1bb795 JB |
9936 | } |
9937 | } | |
9938 | ||
252b5132 | 9939 | \f |
4cc782b5 | 9940 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 9941 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 9942 | #else |
12b55ccc | 9943 | const char *md_shortopts = "qn"; |
252b5132 | 9944 | #endif |
6e0b89ee | 9945 | |
3e73aa7c | 9946 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
9947 | #define OPTION_64 (OPTION_MD_BASE + 1) |
9948 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
9949 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
9950 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
9951 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
9952 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
9953 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
9954 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
9955 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 9956 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 9957 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
9958 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
9959 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
9960 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 9961 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
9962 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
9963 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 9964 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 9965 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 9966 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 9967 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
9968 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
9969 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 9970 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
0cb4071e | 9971 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25) |
b3b91714 | 9972 | |
99ad8390 NC |
9973 | struct option md_longopts[] = |
9974 | { | |
3e73aa7c | 9975 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 9976 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 9977 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 9978 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
9979 | #endif |
9980 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 9981 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 9982 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
6e0b89ee | 9983 | #endif |
b3b91714 | 9984 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
9985 | {"march", required_argument, NULL, OPTION_MARCH}, |
9986 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
9987 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
9988 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
9989 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
9990 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
9991 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 9992 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 9993 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 9994 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 9995 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
7e8b059b | 9996 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
9997 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
9998 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
9999 | # if defined (TE_PE) || defined (TE_PEP) |
10000 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
10001 | #endif | |
d1982f93 | 10002 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 10003 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 10004 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 10005 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
10006 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
10007 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
10008 | {NULL, no_argument, NULL, 0} |
10009 | }; | |
10010 | size_t md_longopts_size = sizeof (md_longopts); | |
10011 | ||
10012 | int | |
17b9d67d | 10013 | md_parse_option (int c, const char *arg) |
252b5132 | 10014 | { |
91d6fa6a | 10015 | unsigned int j; |
293f5f65 | 10016 | char *arch, *next, *saved; |
9103f4f4 | 10017 | |
252b5132 RH |
10018 | switch (c) |
10019 | { | |
12b55ccc L |
10020 | case 'n': |
10021 | optimize_align_code = 0; | |
10022 | break; | |
10023 | ||
a38cf1db AM |
10024 | case 'q': |
10025 | quiet_warnings = 1; | |
252b5132 RH |
10026 | break; |
10027 | ||
10028 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
10029 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
10030 | should be emitted or not. FIXME: Not implemented. */ | |
10031 | case 'Q': | |
252b5132 RH |
10032 | break; |
10033 | ||
10034 | /* -V: SVR4 argument to print version ID. */ | |
10035 | case 'V': | |
10036 | print_version_id (); | |
10037 | break; | |
10038 | ||
a38cf1db AM |
10039 | /* -k: Ignore for FreeBSD compatibility. */ |
10040 | case 'k': | |
252b5132 | 10041 | break; |
4cc782b5 ILT |
10042 | |
10043 | case 's': | |
10044 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 10045 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 10046 | break; |
8dcea932 L |
10047 | |
10048 | case OPTION_MSHARED: | |
10049 | shared = 1; | |
10050 | break; | |
99ad8390 | 10051 | #endif |
321098a5 | 10052 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10053 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
10054 | case OPTION_64: |
10055 | { | |
10056 | const char **list, **l; | |
10057 | ||
3e73aa7c JH |
10058 | list = bfd_target_list (); |
10059 | for (l = list; *l != NULL; l++) | |
8620418b | 10060 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
10061 | || strcmp (*l, "coff-x86-64") == 0 |
10062 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
10063 | || strcmp (*l, "pei-x86-64") == 0 |
10064 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
10065 | { |
10066 | default_arch = "x86_64"; | |
10067 | break; | |
10068 | } | |
3e73aa7c | 10069 | if (*l == NULL) |
2b5d6a91 | 10070 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
10071 | free (list); |
10072 | } | |
10073 | break; | |
10074 | #endif | |
252b5132 | 10075 | |
351f65ca | 10076 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 10077 | case OPTION_X32: |
351f65ca L |
10078 | if (IS_ELF) |
10079 | { | |
10080 | const char **list, **l; | |
10081 | ||
10082 | list = bfd_target_list (); | |
10083 | for (l = list; *l != NULL; l++) | |
10084 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
10085 | { | |
10086 | default_arch = "x86_64:32"; | |
10087 | break; | |
10088 | } | |
10089 | if (*l == NULL) | |
2b5d6a91 | 10090 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
10091 | free (list); |
10092 | } | |
10093 | else | |
10094 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
10095 | break; | |
10096 | #endif | |
10097 | ||
6e0b89ee AM |
10098 | case OPTION_32: |
10099 | default_arch = "i386"; | |
10100 | break; | |
10101 | ||
b3b91714 AM |
10102 | case OPTION_DIVIDE: |
10103 | #ifdef SVR4_COMMENT_CHARS | |
10104 | { | |
10105 | char *n, *t; | |
10106 | const char *s; | |
10107 | ||
add39d23 | 10108 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
10109 | t = n; |
10110 | for (s = i386_comment_chars; *s != '\0'; s++) | |
10111 | if (*s != '/') | |
10112 | *t++ = *s; | |
10113 | *t = '\0'; | |
10114 | i386_comment_chars = n; | |
10115 | } | |
10116 | #endif | |
10117 | break; | |
10118 | ||
9103f4f4 | 10119 | case OPTION_MARCH: |
293f5f65 L |
10120 | saved = xstrdup (arg); |
10121 | arch = saved; | |
10122 | /* Allow -march=+nosse. */ | |
10123 | if (*arch == '+') | |
10124 | arch++; | |
6305a203 | 10125 | do |
9103f4f4 | 10126 | { |
6305a203 | 10127 | if (*arch == '.') |
2b5d6a91 | 10128 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10129 | next = strchr (arch, '+'); |
10130 | if (next) | |
10131 | *next++ = '\0'; | |
91d6fa6a | 10132 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10133 | { |
91d6fa6a | 10134 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 10135 | { |
6305a203 | 10136 | /* Processor. */ |
1ded5609 JB |
10137 | if (! cpu_arch[j].flags.bitfield.cpui386) |
10138 | continue; | |
10139 | ||
91d6fa6a | 10140 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 10141 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
10142 | cpu_arch_flags = cpu_arch[j].flags; |
10143 | cpu_arch_isa = cpu_arch[j].type; | |
10144 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
10145 | if (!cpu_arch_tune_set) |
10146 | { | |
10147 | cpu_arch_tune = cpu_arch_isa; | |
10148 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10149 | } | |
10150 | break; | |
10151 | } | |
91d6fa6a NC |
10152 | else if (*cpu_arch [j].name == '.' |
10153 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 10154 | { |
33eaf5de | 10155 | /* ISA extension. */ |
6305a203 | 10156 | i386_cpu_flags flags; |
309d3373 | 10157 | |
293f5f65 L |
10158 | flags = cpu_flags_or (cpu_arch_flags, |
10159 | cpu_arch[j].flags); | |
81486035 | 10160 | |
5b64d091 | 10161 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
10162 | { |
10163 | if (cpu_sub_arch_name) | |
10164 | { | |
10165 | char *name = cpu_sub_arch_name; | |
10166 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 10167 | cpu_arch[j].name, |
1bf57e9f | 10168 | (const char *) NULL); |
6305a203 L |
10169 | free (name); |
10170 | } | |
10171 | else | |
91d6fa6a | 10172 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 10173 | cpu_arch_flags = flags; |
a586129e | 10174 | cpu_arch_isa_flags = flags; |
6305a203 L |
10175 | } |
10176 | break; | |
ccc9c027 | 10177 | } |
9103f4f4 | 10178 | } |
6305a203 | 10179 | |
293f5f65 L |
10180 | if (j >= ARRAY_SIZE (cpu_arch)) |
10181 | { | |
33eaf5de | 10182 | /* Disable an ISA extension. */ |
293f5f65 L |
10183 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
10184 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
10185 | { | |
10186 | i386_cpu_flags flags; | |
10187 | ||
10188 | flags = cpu_flags_and_not (cpu_arch_flags, | |
10189 | cpu_noarch[j].flags); | |
10190 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
10191 | { | |
10192 | if (cpu_sub_arch_name) | |
10193 | { | |
10194 | char *name = cpu_sub_arch_name; | |
10195 | cpu_sub_arch_name = concat (arch, | |
10196 | (const char *) NULL); | |
10197 | free (name); | |
10198 | } | |
10199 | else | |
10200 | cpu_sub_arch_name = xstrdup (arch); | |
10201 | cpu_arch_flags = flags; | |
10202 | cpu_arch_isa_flags = flags; | |
10203 | } | |
10204 | break; | |
10205 | } | |
10206 | ||
10207 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
10208 | j = ARRAY_SIZE (cpu_arch); | |
10209 | } | |
10210 | ||
91d6fa6a | 10211 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10212 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10213 | |
10214 | arch = next; | |
9103f4f4 | 10215 | } |
293f5f65 L |
10216 | while (next != NULL); |
10217 | free (saved); | |
9103f4f4 L |
10218 | break; |
10219 | ||
10220 | case OPTION_MTUNE: | |
10221 | if (*arg == '.') | |
2b5d6a91 | 10222 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 10223 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10224 | { |
91d6fa6a | 10225 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 10226 | { |
ccc9c027 | 10227 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
10228 | cpu_arch_tune = cpu_arch [j].type; |
10229 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
10230 | break; |
10231 | } | |
10232 | } | |
91d6fa6a | 10233 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10234 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
10235 | break; |
10236 | ||
1efbbeb4 L |
10237 | case OPTION_MMNEMONIC: |
10238 | if (strcasecmp (arg, "att") == 0) | |
10239 | intel_mnemonic = 0; | |
10240 | else if (strcasecmp (arg, "intel") == 0) | |
10241 | intel_mnemonic = 1; | |
10242 | else | |
2b5d6a91 | 10243 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
10244 | break; |
10245 | ||
10246 | case OPTION_MSYNTAX: | |
10247 | if (strcasecmp (arg, "att") == 0) | |
10248 | intel_syntax = 0; | |
10249 | else if (strcasecmp (arg, "intel") == 0) | |
10250 | intel_syntax = 1; | |
10251 | else | |
2b5d6a91 | 10252 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
10253 | break; |
10254 | ||
10255 | case OPTION_MINDEX_REG: | |
10256 | allow_index_reg = 1; | |
10257 | break; | |
10258 | ||
10259 | case OPTION_MNAKED_REG: | |
10260 | allow_naked_reg = 1; | |
10261 | break; | |
10262 | ||
10263 | case OPTION_MOLD_GCC: | |
10264 | old_gcc = 1; | |
1efbbeb4 L |
10265 | break; |
10266 | ||
c0f3af97 L |
10267 | case OPTION_MSSE2AVX: |
10268 | sse2avx = 1; | |
10269 | break; | |
10270 | ||
daf50ae7 L |
10271 | case OPTION_MSSE_CHECK: |
10272 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 10273 | sse_check = check_error; |
daf50ae7 | 10274 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 10275 | sse_check = check_warning; |
daf50ae7 | 10276 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 10277 | sse_check = check_none; |
daf50ae7 | 10278 | else |
2b5d6a91 | 10279 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
10280 | break; |
10281 | ||
7bab8ab5 JB |
10282 | case OPTION_MOPERAND_CHECK: |
10283 | if (strcasecmp (arg, "error") == 0) | |
10284 | operand_check = check_error; | |
10285 | else if (strcasecmp (arg, "warning") == 0) | |
10286 | operand_check = check_warning; | |
10287 | else if (strcasecmp (arg, "none") == 0) | |
10288 | operand_check = check_none; | |
10289 | else | |
10290 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
10291 | break; | |
10292 | ||
539f890d L |
10293 | case OPTION_MAVXSCALAR: |
10294 | if (strcasecmp (arg, "128") == 0) | |
10295 | avxscalar = vex128; | |
10296 | else if (strcasecmp (arg, "256") == 0) | |
10297 | avxscalar = vex256; | |
10298 | else | |
2b5d6a91 | 10299 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
10300 | break; |
10301 | ||
7e8b059b L |
10302 | case OPTION_MADD_BND_PREFIX: |
10303 | add_bnd_prefix = 1; | |
10304 | break; | |
10305 | ||
43234a1e L |
10306 | case OPTION_MEVEXLIG: |
10307 | if (strcmp (arg, "128") == 0) | |
10308 | evexlig = evexl128; | |
10309 | else if (strcmp (arg, "256") == 0) | |
10310 | evexlig = evexl256; | |
10311 | else if (strcmp (arg, "512") == 0) | |
10312 | evexlig = evexl512; | |
10313 | else | |
10314 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
10315 | break; | |
10316 | ||
d3d3c6db IT |
10317 | case OPTION_MEVEXRCIG: |
10318 | if (strcmp (arg, "rne") == 0) | |
10319 | evexrcig = rne; | |
10320 | else if (strcmp (arg, "rd") == 0) | |
10321 | evexrcig = rd; | |
10322 | else if (strcmp (arg, "ru") == 0) | |
10323 | evexrcig = ru; | |
10324 | else if (strcmp (arg, "rz") == 0) | |
10325 | evexrcig = rz; | |
10326 | else | |
10327 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
10328 | break; | |
10329 | ||
43234a1e L |
10330 | case OPTION_MEVEXWIG: |
10331 | if (strcmp (arg, "0") == 0) | |
10332 | evexwig = evexw0; | |
10333 | else if (strcmp (arg, "1") == 0) | |
10334 | evexwig = evexw1; | |
10335 | else | |
10336 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
10337 | break; | |
10338 | ||
167ad85b TG |
10339 | # if defined (TE_PE) || defined (TE_PEP) |
10340 | case OPTION_MBIG_OBJ: | |
10341 | use_big_obj = 1; | |
10342 | break; | |
10343 | #endif | |
10344 | ||
d1982f93 | 10345 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
10346 | if (strcasecmp (arg, "yes") == 0) |
10347 | omit_lock_prefix = 1; | |
10348 | else if (strcasecmp (arg, "no") == 0) | |
10349 | omit_lock_prefix = 0; | |
10350 | else | |
10351 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
10352 | break; | |
10353 | ||
e4e00185 AS |
10354 | case OPTION_MFENCE_AS_LOCK_ADD: |
10355 | if (strcasecmp (arg, "yes") == 0) | |
10356 | avoid_fence = 1; | |
10357 | else if (strcasecmp (arg, "no") == 0) | |
10358 | avoid_fence = 0; | |
10359 | else | |
10360 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
10361 | break; | |
10362 | ||
0cb4071e L |
10363 | case OPTION_MRELAX_RELOCATIONS: |
10364 | if (strcasecmp (arg, "yes") == 0) | |
10365 | generate_relax_relocations = 1; | |
10366 | else if (strcasecmp (arg, "no") == 0) | |
10367 | generate_relax_relocations = 0; | |
10368 | else | |
10369 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
10370 | break; | |
10371 | ||
5db04b09 | 10372 | case OPTION_MAMD64: |
e89c5eaa | 10373 | intel64 = 0; |
5db04b09 L |
10374 | break; |
10375 | ||
10376 | case OPTION_MINTEL64: | |
e89c5eaa | 10377 | intel64 = 1; |
5db04b09 L |
10378 | break; |
10379 | ||
252b5132 RH |
10380 | default: |
10381 | return 0; | |
10382 | } | |
10383 | return 1; | |
10384 | } | |
10385 | ||
8a2c8fef L |
10386 | #define MESSAGE_TEMPLATE \ |
10387 | " " | |
10388 | ||
293f5f65 L |
10389 | static char * |
10390 | output_message (FILE *stream, char *p, char *message, char *start, | |
10391 | int *left_p, const char *name, int len) | |
10392 | { | |
10393 | int size = sizeof (MESSAGE_TEMPLATE); | |
10394 | int left = *left_p; | |
10395 | ||
10396 | /* Reserve 2 spaces for ", " or ",\0" */ | |
10397 | left -= len + 2; | |
10398 | ||
10399 | /* Check if there is any room. */ | |
10400 | if (left >= 0) | |
10401 | { | |
10402 | if (p != start) | |
10403 | { | |
10404 | *p++ = ','; | |
10405 | *p++ = ' '; | |
10406 | } | |
10407 | p = mempcpy (p, name, len); | |
10408 | } | |
10409 | else | |
10410 | { | |
10411 | /* Output the current message now and start a new one. */ | |
10412 | *p++ = ','; | |
10413 | *p = '\0'; | |
10414 | fprintf (stream, "%s\n", message); | |
10415 | p = start; | |
10416 | left = size - (start - message) - len - 2; | |
10417 | ||
10418 | gas_assert (left >= 0); | |
10419 | ||
10420 | p = mempcpy (p, name, len); | |
10421 | } | |
10422 | ||
10423 | *left_p = left; | |
10424 | return p; | |
10425 | } | |
10426 | ||
8a2c8fef | 10427 | static void |
1ded5609 | 10428 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
10429 | { |
10430 | static char message[] = MESSAGE_TEMPLATE; | |
10431 | char *start = message + 27; | |
10432 | char *p; | |
10433 | int size = sizeof (MESSAGE_TEMPLATE); | |
10434 | int left; | |
10435 | const char *name; | |
10436 | int len; | |
10437 | unsigned int j; | |
10438 | ||
10439 | p = start; | |
10440 | left = size - (start - message); | |
10441 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
10442 | { | |
10443 | /* Should it be skipped? */ | |
10444 | if (cpu_arch [j].skip) | |
10445 | continue; | |
10446 | ||
10447 | name = cpu_arch [j].name; | |
10448 | len = cpu_arch [j].len; | |
10449 | if (*name == '.') | |
10450 | { | |
10451 | /* It is an extension. Skip if we aren't asked to show it. */ | |
10452 | if (ext) | |
10453 | { | |
10454 | name++; | |
10455 | len--; | |
10456 | } | |
10457 | else | |
10458 | continue; | |
10459 | } | |
10460 | else if (ext) | |
10461 | { | |
10462 | /* It is an processor. Skip if we show only extension. */ | |
10463 | continue; | |
10464 | } | |
1ded5609 JB |
10465 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
10466 | { | |
10467 | /* It is an impossible processor - skip. */ | |
10468 | continue; | |
10469 | } | |
8a2c8fef | 10470 | |
293f5f65 | 10471 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
10472 | } |
10473 | ||
293f5f65 L |
10474 | /* Display disabled extensions. */ |
10475 | if (ext) | |
10476 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
10477 | { | |
10478 | name = cpu_noarch [j].name; | |
10479 | len = cpu_noarch [j].len; | |
10480 | p = output_message (stream, p, message, start, &left, name, | |
10481 | len); | |
10482 | } | |
10483 | ||
8a2c8fef L |
10484 | *p = '\0'; |
10485 | fprintf (stream, "%s\n", message); | |
10486 | } | |
10487 | ||
252b5132 | 10488 | void |
8a2c8fef | 10489 | md_show_usage (FILE *stream) |
252b5132 | 10490 | { |
4cc782b5 ILT |
10491 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10492 | fprintf (stream, _("\ | |
a38cf1db AM |
10493 | -Q ignored\n\ |
10494 | -V print assembler version number\n\ | |
b3b91714 AM |
10495 | -k ignored\n")); |
10496 | #endif | |
10497 | fprintf (stream, _("\ | |
12b55ccc | 10498 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
10499 | -q quieten some warnings\n")); |
10500 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10501 | fprintf (stream, _("\ | |
a38cf1db | 10502 | -s ignored\n")); |
b3b91714 | 10503 | #endif |
321098a5 L |
10504 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
10505 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 10506 | fprintf (stream, _("\ |
570561f7 | 10507 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 10508 | #endif |
b3b91714 AM |
10509 | #ifdef SVR4_COMMENT_CHARS |
10510 | fprintf (stream, _("\ | |
10511 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
10512 | #else |
10513 | fprintf (stream, _("\ | |
b3b91714 | 10514 | --divide ignored\n")); |
4cc782b5 | 10515 | #endif |
9103f4f4 | 10516 | fprintf (stream, _("\ |
6305a203 | 10517 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 10518 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 10519 | show_arch (stream, 0, 1); |
8a2c8fef L |
10520 | fprintf (stream, _("\ |
10521 | EXTENSION is combination of:\n")); | |
1ded5609 | 10522 | show_arch (stream, 1, 0); |
6305a203 | 10523 | fprintf (stream, _("\ |
8a2c8fef | 10524 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 10525 | show_arch (stream, 0, 0); |
ba104c83 | 10526 | fprintf (stream, _("\ |
c0f3af97 L |
10527 | -msse2avx encode SSE instructions with VEX prefix\n")); |
10528 | fprintf (stream, _("\ | |
daf50ae7 L |
10529 | -msse-check=[none|error|warning]\n\ |
10530 | check SSE instructions\n")); | |
10531 | fprintf (stream, _("\ | |
7bab8ab5 JB |
10532 | -moperand-check=[none|error|warning]\n\ |
10533 | check operand combinations for validity\n")); | |
10534 | fprintf (stream, _("\ | |
539f890d L |
10535 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
10536 | length\n")); | |
10537 | fprintf (stream, _("\ | |
43234a1e L |
10538 | -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ |
10539 | length\n")); | |
10540 | fprintf (stream, _("\ | |
10541 | -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ | |
10542 | for EVEX.W bit ignored instructions\n")); | |
10543 | fprintf (stream, _("\ | |
d3d3c6db IT |
10544 | -mevexrcig=[rne|rd|ru|rz]\n\ |
10545 | encode EVEX instructions with specific EVEX.RC value\n\ | |
10546 | for SAE-only ignored instructions\n")); | |
10547 | fprintf (stream, _("\ | |
ba104c83 L |
10548 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
10549 | fprintf (stream, _("\ | |
10550 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
10551 | fprintf (stream, _("\ | |
10552 | -mindex-reg support pseudo index registers\n")); | |
10553 | fprintf (stream, _("\ | |
10554 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
10555 | fprintf (stream, _("\ | |
10556 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
7e8b059b L |
10557 | fprintf (stream, _("\ |
10558 | -madd-bnd-prefix add BND prefix for all valid branches\n")); | |
8dcea932 L |
10559 | fprintf (stream, _("\ |
10560 | -mshared disable branch optimization for shared code\n")); | |
167ad85b TG |
10561 | # if defined (TE_PE) || defined (TE_PEP) |
10562 | fprintf (stream, _("\ | |
10563 | -mbig-obj generate big object files\n")); | |
10564 | #endif | |
d022bddd IT |
10565 | fprintf (stream, _("\ |
10566 | -momit-lock-prefix=[no|yes]\n\ | |
10567 | strip all lock prefixes\n")); | |
5db04b09 | 10568 | fprintf (stream, _("\ |
e4e00185 AS |
10569 | -mfence-as-lock-add=[no|yes]\n\ |
10570 | encode lfence, mfence and sfence as\n\ | |
10571 | lock addl $0x0, (%%{re}sp)\n")); | |
10572 | fprintf (stream, _("\ | |
0cb4071e L |
10573 | -mrelax-relocations=[no|yes]\n\ |
10574 | generate relax relocations\n")); | |
10575 | fprintf (stream, _("\ | |
5db04b09 L |
10576 | -mamd64 accept only AMD64 ISA\n")); |
10577 | fprintf (stream, _("\ | |
10578 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
10579 | } |
10580 | ||
3e73aa7c | 10581 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 10582 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 10583 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
10584 | |
10585 | /* Pick the target format to use. */ | |
10586 | ||
47926f60 | 10587 | const char * |
e3bb37b5 | 10588 | i386_target_format (void) |
252b5132 | 10589 | { |
351f65ca L |
10590 | if (!strncmp (default_arch, "x86_64", 6)) |
10591 | { | |
10592 | update_code_flag (CODE_64BIT, 1); | |
10593 | if (default_arch[6] == '\0') | |
7f56bc95 | 10594 | x86_elf_abi = X86_64_ABI; |
351f65ca | 10595 | else |
7f56bc95 | 10596 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 10597 | } |
3e73aa7c | 10598 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 10599 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
10600 | else if (!strcmp (default_arch, "iamcu")) |
10601 | { | |
10602 | update_code_flag (CODE_32BIT, 1); | |
10603 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
10604 | { | |
10605 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
10606 | cpu_arch_name = "iamcu"; | |
10607 | cpu_sub_arch_name = NULL; | |
10608 | cpu_arch_flags = iamcu_flags; | |
10609 | cpu_arch_isa = PROCESSOR_IAMCU; | |
10610 | cpu_arch_isa_flags = iamcu_flags; | |
10611 | if (!cpu_arch_tune_set) | |
10612 | { | |
10613 | cpu_arch_tune = cpu_arch_isa; | |
10614 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10615 | } | |
10616 | } | |
8d471ec1 | 10617 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
10618 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
10619 | cpu_arch_name); | |
10620 | } | |
3e73aa7c | 10621 | else |
2b5d6a91 | 10622 | as_fatal (_("unknown architecture")); |
89507696 JB |
10623 | |
10624 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
10625 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
10626 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
10627 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
10628 | ||
252b5132 RH |
10629 | switch (OUTPUT_FLAVOR) |
10630 | { | |
9384f2ff | 10631 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 10632 | case bfd_target_aout_flavour: |
47926f60 | 10633 | return AOUT_TARGET_FORMAT; |
4c63da97 | 10634 | #endif |
9384f2ff AM |
10635 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
10636 | # if defined (TE_PE) || defined (TE_PEP) | |
10637 | case bfd_target_coff_flavour: | |
167ad85b TG |
10638 | if (flag_code == CODE_64BIT) |
10639 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
10640 | else | |
10641 | return "pe-i386"; | |
9384f2ff | 10642 | # elif defined (TE_GO32) |
0561d57c JK |
10643 | case bfd_target_coff_flavour: |
10644 | return "coff-go32"; | |
9384f2ff | 10645 | # else |
252b5132 RH |
10646 | case bfd_target_coff_flavour: |
10647 | return "coff-i386"; | |
9384f2ff | 10648 | # endif |
4c63da97 | 10649 | #endif |
3e73aa7c | 10650 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 10651 | case bfd_target_elf_flavour: |
3e73aa7c | 10652 | { |
351f65ca L |
10653 | const char *format; |
10654 | ||
10655 | switch (x86_elf_abi) | |
4fa24527 | 10656 | { |
351f65ca L |
10657 | default: |
10658 | format = ELF_TARGET_FORMAT; | |
10659 | break; | |
7f56bc95 | 10660 | case X86_64_ABI: |
351f65ca | 10661 | use_rela_relocations = 1; |
4fa24527 | 10662 | object_64bit = 1; |
351f65ca L |
10663 | format = ELF_TARGET_FORMAT64; |
10664 | break; | |
7f56bc95 | 10665 | case X86_64_X32_ABI: |
4fa24527 | 10666 | use_rela_relocations = 1; |
351f65ca | 10667 | object_64bit = 1; |
862be3fb | 10668 | disallow_64bit_reloc = 1; |
351f65ca L |
10669 | format = ELF_TARGET_FORMAT32; |
10670 | break; | |
4fa24527 | 10671 | } |
3632d14b | 10672 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 10673 | { |
7f56bc95 | 10674 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
10675 | as_fatal (_("Intel L1OM is 64bit only")); |
10676 | return ELF_TARGET_L1OM_FORMAT; | |
10677 | } | |
b49f93f6 | 10678 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
10679 | { |
10680 | if (x86_elf_abi != X86_64_ABI) | |
10681 | as_fatal (_("Intel K1OM is 64bit only")); | |
10682 | return ELF_TARGET_K1OM_FORMAT; | |
10683 | } | |
81486035 L |
10684 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
10685 | { | |
10686 | if (x86_elf_abi != I386_ABI) | |
10687 | as_fatal (_("Intel MCU is 32bit only")); | |
10688 | return ELF_TARGET_IAMCU_FORMAT; | |
10689 | } | |
8a9036a4 | 10690 | else |
351f65ca | 10691 | return format; |
3e73aa7c | 10692 | } |
e57f8c65 TG |
10693 | #endif |
10694 | #if defined (OBJ_MACH_O) | |
10695 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
10696 | if (flag_code == CODE_64BIT) |
10697 | { | |
10698 | use_rela_relocations = 1; | |
10699 | object_64bit = 1; | |
10700 | return "mach-o-x86-64"; | |
10701 | } | |
10702 | else | |
10703 | return "mach-o-i386"; | |
4c63da97 | 10704 | #endif |
252b5132 RH |
10705 | default: |
10706 | abort (); | |
10707 | return NULL; | |
10708 | } | |
10709 | } | |
10710 | ||
47926f60 | 10711 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 10712 | \f |
252b5132 | 10713 | symbolS * |
7016a5d5 | 10714 | md_undefined_symbol (char *name) |
252b5132 | 10715 | { |
18dc2407 ILT |
10716 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
10717 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
10718 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
10719 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
10720 | { |
10721 | if (!GOT_symbol) | |
10722 | { | |
10723 | if (symbol_find (name)) | |
10724 | as_bad (_("GOT already in symbol table")); | |
10725 | GOT_symbol = symbol_new (name, undefined_section, | |
10726 | (valueT) 0, &zero_address_frag); | |
10727 | }; | |
10728 | return GOT_symbol; | |
10729 | } | |
252b5132 RH |
10730 | return 0; |
10731 | } | |
10732 | ||
10733 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 10734 | |
252b5132 | 10735 | valueT |
7016a5d5 | 10736 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 10737 | { |
4c63da97 AM |
10738 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
10739 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
10740 | { | |
10741 | /* For a.out, force the section size to be aligned. If we don't do | |
10742 | this, BFD will align it for us, but it will not write out the | |
10743 | final bytes of the section. This may be a bug in BFD, but it is | |
10744 | easier to fix it here since that is how the other a.out targets | |
10745 | work. */ | |
10746 | int align; | |
10747 | ||
10748 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 10749 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 10750 | } |
252b5132 RH |
10751 | #endif |
10752 | ||
10753 | return size; | |
10754 | } | |
10755 | ||
10756 | /* On the i386, PC-relative offsets are relative to the start of the | |
10757 | next instruction. That is, the address of the offset, plus its | |
10758 | size, since the offset is always the last part of the insn. */ | |
10759 | ||
10760 | long | |
e3bb37b5 | 10761 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
10762 | { |
10763 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
10764 | } | |
10765 | ||
10766 | #ifndef I386COFF | |
10767 | ||
10768 | static void | |
e3bb37b5 | 10769 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 10770 | { |
29b0f896 | 10771 | int temp; |
252b5132 | 10772 | |
8a75718c JB |
10773 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10774 | if (IS_ELF) | |
10775 | obj_elf_section_change_hook (); | |
10776 | #endif | |
252b5132 RH |
10777 | temp = get_absolute_expression (); |
10778 | subseg_set (bss_section, (subsegT) temp); | |
10779 | demand_empty_rest_of_line (); | |
10780 | } | |
10781 | ||
10782 | #endif | |
10783 | ||
252b5132 | 10784 | void |
e3bb37b5 | 10785 | i386_validate_fix (fixS *fixp) |
252b5132 | 10786 | { |
02a86693 | 10787 | if (fixp->fx_subsy) |
252b5132 | 10788 | { |
02a86693 | 10789 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 10790 | { |
02a86693 L |
10791 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
10792 | { | |
10793 | if (!object_64bit) | |
10794 | abort (); | |
10795 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10796 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
10797 | fixp->fx_r_type = (fixp->fx_tcbit |
10798 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
10799 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
10800 | else |
10801 | #endif | |
10802 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
10803 | } | |
d6ab8113 | 10804 | else |
02a86693 L |
10805 | { |
10806 | if (!object_64bit) | |
10807 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
10808 | else | |
10809 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
10810 | } | |
10811 | fixp->fx_subsy = 0; | |
23df1078 | 10812 | } |
252b5132 | 10813 | } |
02a86693 L |
10814 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10815 | else if (!object_64bit) | |
10816 | { | |
10817 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
10818 | && fixp->fx_tcbit2) | |
10819 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
10820 | } | |
10821 | #endif | |
252b5132 RH |
10822 | } |
10823 | ||
252b5132 | 10824 | arelent * |
7016a5d5 | 10825 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
10826 | { |
10827 | arelent *rel; | |
10828 | bfd_reloc_code_real_type code; | |
10829 | ||
10830 | switch (fixp->fx_r_type) | |
10831 | { | |
8ce3d284 | 10832 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
10833 | case BFD_RELOC_SIZE32: |
10834 | case BFD_RELOC_SIZE64: | |
10835 | if (S_IS_DEFINED (fixp->fx_addsy) | |
10836 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
10837 | { | |
10838 | /* Resolve size relocation against local symbol to size of | |
10839 | the symbol plus addend. */ | |
10840 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
10841 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
10842 | && !fits_in_unsigned_long (value)) | |
10843 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10844 | _("symbol size computation overflow")); | |
10845 | fixp->fx_addsy = NULL; | |
10846 | fixp->fx_subsy = NULL; | |
10847 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
10848 | return NULL; | |
10849 | } | |
8ce3d284 | 10850 | #endif |
1a0670f3 | 10851 | /* Fall through. */ |
8fd4256d | 10852 | |
3e73aa7c JH |
10853 | case BFD_RELOC_X86_64_PLT32: |
10854 | case BFD_RELOC_X86_64_GOT32: | |
10855 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
10856 | case BFD_RELOC_X86_64_GOTPCRELX: |
10857 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
10858 | case BFD_RELOC_386_PLT32: |
10859 | case BFD_RELOC_386_GOT32: | |
02a86693 | 10860 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
10861 | case BFD_RELOC_386_GOTOFF: |
10862 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
10863 | case BFD_RELOC_386_TLS_GD: |
10864 | case BFD_RELOC_386_TLS_LDM: | |
10865 | case BFD_RELOC_386_TLS_LDO_32: | |
10866 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
10867 | case BFD_RELOC_386_TLS_IE: |
10868 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
10869 | case BFD_RELOC_386_TLS_LE_32: |
10870 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
10871 | case BFD_RELOC_386_TLS_GOTDESC: |
10872 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
10873 | case BFD_RELOC_X86_64_TLSGD: |
10874 | case BFD_RELOC_X86_64_TLSLD: | |
10875 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10876 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
10877 | case BFD_RELOC_X86_64_GOTTPOFF: |
10878 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
10879 | case BFD_RELOC_X86_64_TPOFF64: |
10880 | case BFD_RELOC_X86_64_GOTOFF64: | |
10881 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
10882 | case BFD_RELOC_X86_64_GOT64: |
10883 | case BFD_RELOC_X86_64_GOTPCREL64: | |
10884 | case BFD_RELOC_X86_64_GOTPC64: | |
10885 | case BFD_RELOC_X86_64_GOTPLT64: | |
10886 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
10887 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
10888 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
10889 | case BFD_RELOC_RVA: |
10890 | case BFD_RELOC_VTABLE_ENTRY: | |
10891 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
10892 | #ifdef TE_PE |
10893 | case BFD_RELOC_32_SECREL: | |
10894 | #endif | |
252b5132 RH |
10895 | code = fixp->fx_r_type; |
10896 | break; | |
dbbaec26 L |
10897 | case BFD_RELOC_X86_64_32S: |
10898 | if (!fixp->fx_pcrel) | |
10899 | { | |
10900 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
10901 | code = fixp->fx_r_type; | |
10902 | break; | |
10903 | } | |
1a0670f3 | 10904 | /* Fall through. */ |
252b5132 | 10905 | default: |
93382f6d | 10906 | if (fixp->fx_pcrel) |
252b5132 | 10907 | { |
93382f6d AM |
10908 | switch (fixp->fx_size) |
10909 | { | |
10910 | default: | |
b091f402 AM |
10911 | as_bad_where (fixp->fx_file, fixp->fx_line, |
10912 | _("can not do %d byte pc-relative relocation"), | |
10913 | fixp->fx_size); | |
93382f6d AM |
10914 | code = BFD_RELOC_32_PCREL; |
10915 | break; | |
10916 | case 1: code = BFD_RELOC_8_PCREL; break; | |
10917 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 10918 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
10919 | #ifdef BFD64 |
10920 | case 8: code = BFD_RELOC_64_PCREL; break; | |
10921 | #endif | |
93382f6d AM |
10922 | } |
10923 | } | |
10924 | else | |
10925 | { | |
10926 | switch (fixp->fx_size) | |
10927 | { | |
10928 | default: | |
b091f402 AM |
10929 | as_bad_where (fixp->fx_file, fixp->fx_line, |
10930 | _("can not do %d byte relocation"), | |
10931 | fixp->fx_size); | |
93382f6d AM |
10932 | code = BFD_RELOC_32; |
10933 | break; | |
10934 | case 1: code = BFD_RELOC_8; break; | |
10935 | case 2: code = BFD_RELOC_16; break; | |
10936 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 10937 | #ifdef BFD64 |
3e73aa7c | 10938 | case 8: code = BFD_RELOC_64; break; |
937149dd | 10939 | #endif |
93382f6d | 10940 | } |
252b5132 RH |
10941 | } |
10942 | break; | |
10943 | } | |
252b5132 | 10944 | |
d182319b JB |
10945 | if ((code == BFD_RELOC_32 |
10946 | || code == BFD_RELOC_32_PCREL | |
10947 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
10948 | && GOT_symbol |
10949 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 10950 | { |
4fa24527 | 10951 | if (!object_64bit) |
d6ab8113 JB |
10952 | code = BFD_RELOC_386_GOTPC; |
10953 | else | |
10954 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 10955 | } |
7b81dfbb AJ |
10956 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
10957 | && GOT_symbol | |
10958 | && fixp->fx_addsy == GOT_symbol) | |
10959 | { | |
10960 | code = BFD_RELOC_X86_64_GOTPC64; | |
10961 | } | |
252b5132 | 10962 | |
add39d23 TS |
10963 | rel = XNEW (arelent); |
10964 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 10965 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
10966 | |
10967 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 10968 | |
3e73aa7c JH |
10969 | if (!use_rela_relocations) |
10970 | { | |
10971 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
10972 | vtable entry to be used in the relocation's section offset. */ | |
10973 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10974 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
10975 | #if defined (OBJ_COFF) && defined (TE_PE) |
10976 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
10977 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
10978 | else | |
10979 | #endif | |
c6682705 | 10980 | rel->addend = 0; |
3e73aa7c JH |
10981 | } |
10982 | /* Use the rela in 64bit mode. */ | |
252b5132 | 10983 | else |
3e73aa7c | 10984 | { |
862be3fb L |
10985 | if (disallow_64bit_reloc) |
10986 | switch (code) | |
10987 | { | |
862be3fb L |
10988 | case BFD_RELOC_X86_64_DTPOFF64: |
10989 | case BFD_RELOC_X86_64_TPOFF64: | |
10990 | case BFD_RELOC_64_PCREL: | |
10991 | case BFD_RELOC_X86_64_GOTOFF64: | |
10992 | case BFD_RELOC_X86_64_GOT64: | |
10993 | case BFD_RELOC_X86_64_GOTPCREL64: | |
10994 | case BFD_RELOC_X86_64_GOTPC64: | |
10995 | case BFD_RELOC_X86_64_GOTPLT64: | |
10996 | case BFD_RELOC_X86_64_PLTOFF64: | |
10997 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10998 | _("cannot represent relocation type %s in x32 mode"), | |
10999 | bfd_get_reloc_code_name (code)); | |
11000 | break; | |
11001 | default: | |
11002 | break; | |
11003 | } | |
11004 | ||
062cd5e7 AS |
11005 | if (!fixp->fx_pcrel) |
11006 | rel->addend = fixp->fx_offset; | |
11007 | else | |
11008 | switch (code) | |
11009 | { | |
11010 | case BFD_RELOC_X86_64_PLT32: | |
11011 | case BFD_RELOC_X86_64_GOT32: | |
11012 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11013 | case BFD_RELOC_X86_64_GOTPCRELX: |
11014 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
11015 | case BFD_RELOC_X86_64_TLSGD: |
11016 | case BFD_RELOC_X86_64_TLSLD: | |
11017 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
11018 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11019 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
11020 | rel->addend = fixp->fx_offset - fixp->fx_size; |
11021 | break; | |
11022 | default: | |
11023 | rel->addend = (section->vma | |
11024 | - fixp->fx_size | |
11025 | + fixp->fx_addnumber | |
11026 | + md_pcrel_from (fixp)); | |
11027 | break; | |
11028 | } | |
3e73aa7c JH |
11029 | } |
11030 | ||
252b5132 RH |
11031 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
11032 | if (rel->howto == NULL) | |
11033 | { | |
11034 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 11035 | _("cannot represent relocation type %s"), |
252b5132 RH |
11036 | bfd_get_reloc_code_name (code)); |
11037 | /* Set howto to a garbage value so that we can keep going. */ | |
11038 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 11039 | gas_assert (rel->howto != NULL); |
252b5132 RH |
11040 | } |
11041 | ||
11042 | return rel; | |
11043 | } | |
11044 | ||
ee86248c | 11045 | #include "tc-i386-intel.c" |
54cfded0 | 11046 | |
a60de03c JB |
11047 | void |
11048 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 11049 | { |
a60de03c JB |
11050 | int saved_naked_reg; |
11051 | char saved_register_dot; | |
54cfded0 | 11052 | |
a60de03c JB |
11053 | saved_naked_reg = allow_naked_reg; |
11054 | allow_naked_reg = 1; | |
11055 | saved_register_dot = register_chars['.']; | |
11056 | register_chars['.'] = '.'; | |
11057 | allow_pseudo_reg = 1; | |
11058 | expression_and_evaluate (exp); | |
11059 | allow_pseudo_reg = 0; | |
11060 | register_chars['.'] = saved_register_dot; | |
11061 | allow_naked_reg = saved_naked_reg; | |
11062 | ||
e96d56a1 | 11063 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 11064 | { |
a60de03c JB |
11065 | if ((addressT) exp->X_add_number < i386_regtab_size) |
11066 | { | |
11067 | exp->X_op = O_constant; | |
11068 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
11069 | .dw2_regnum[flag_code >> 1]; | |
11070 | } | |
11071 | else | |
11072 | exp->X_op = O_illegal; | |
54cfded0 | 11073 | } |
54cfded0 AM |
11074 | } |
11075 | ||
11076 | void | |
11077 | tc_x86_frame_initial_instructions (void) | |
11078 | { | |
a60de03c JB |
11079 | static unsigned int sp_regno[2]; |
11080 | ||
11081 | if (!sp_regno[flag_code >> 1]) | |
11082 | { | |
11083 | char *saved_input = input_line_pointer; | |
11084 | char sp[][4] = {"esp", "rsp"}; | |
11085 | expressionS exp; | |
a4447b93 | 11086 | |
a60de03c JB |
11087 | input_line_pointer = sp[flag_code >> 1]; |
11088 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 11089 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
11090 | sp_regno[flag_code >> 1] = exp.X_add_number; |
11091 | input_line_pointer = saved_input; | |
11092 | } | |
a4447b93 | 11093 | |
61ff971f L |
11094 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
11095 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 11096 | } |
d2b2c203 | 11097 | |
d7921315 L |
11098 | int |
11099 | x86_dwarf2_addr_size (void) | |
11100 | { | |
11101 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
11102 | if (x86_elf_abi == X86_64_X32_ABI) | |
11103 | return 4; | |
11104 | #endif | |
11105 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
11106 | } | |
11107 | ||
d2b2c203 DJ |
11108 | int |
11109 | i386_elf_section_type (const char *str, size_t len) | |
11110 | { | |
11111 | if (flag_code == CODE_64BIT | |
11112 | && len == sizeof ("unwind") - 1 | |
11113 | && strncmp (str, "unwind", 6) == 0) | |
11114 | return SHT_X86_64_UNWIND; | |
11115 | ||
11116 | return -1; | |
11117 | } | |
bb41ade5 | 11118 | |
ad5fec3b EB |
11119 | #ifdef TE_SOLARIS |
11120 | void | |
11121 | i386_solaris_fix_up_eh_frame (segT sec) | |
11122 | { | |
11123 | if (flag_code == CODE_64BIT) | |
11124 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
11125 | } | |
11126 | #endif | |
11127 | ||
bb41ade5 AM |
11128 | #ifdef TE_PE |
11129 | void | |
11130 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
11131 | { | |
91d6fa6a | 11132 | expressionS exp; |
bb41ade5 | 11133 | |
91d6fa6a NC |
11134 | exp.X_op = O_secrel; |
11135 | exp.X_add_symbol = symbol; | |
11136 | exp.X_add_number = 0; | |
11137 | emit_expr (&exp, size); | |
bb41ade5 AM |
11138 | } |
11139 | #endif | |
3b22753a L |
11140 | |
11141 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11142 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
11143 | ||
01e1a5bc | 11144 | bfd_vma |
6d4af3c2 | 11145 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
11146 | { |
11147 | if (flag_code == CODE_64BIT) | |
11148 | { | |
11149 | if (letter == 'l') | |
11150 | return SHF_X86_64_LARGE; | |
11151 | ||
8f3bae45 | 11152 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 11153 | } |
3b22753a | 11154 | else |
8f3bae45 | 11155 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
11156 | return -1; |
11157 | } | |
11158 | ||
01e1a5bc | 11159 | bfd_vma |
3b22753a L |
11160 | x86_64_section_word (char *str, size_t len) |
11161 | { | |
8620418b | 11162 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
11163 | return SHF_X86_64_LARGE; |
11164 | ||
11165 | return -1; | |
11166 | } | |
11167 | ||
11168 | static void | |
11169 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
11170 | { | |
11171 | if (flag_code != CODE_64BIT) | |
11172 | { | |
11173 | s_comm_internal (0, elf_common_parse); | |
11174 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
11175 | } | |
11176 | else | |
11177 | { | |
11178 | static segT lbss_section; | |
11179 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
11180 | asection *saved_bss_section = bss_section; | |
11181 | ||
11182 | if (lbss_section == NULL) | |
11183 | { | |
11184 | flagword applicable; | |
11185 | segT seg = now_seg; | |
11186 | subsegT subseg = now_subseg; | |
11187 | ||
11188 | /* The .lbss section is for local .largecomm symbols. */ | |
11189 | lbss_section = subseg_new (".lbss", 0); | |
11190 | applicable = bfd_applicable_section_flags (stdoutput); | |
11191 | bfd_set_section_flags (stdoutput, lbss_section, | |
11192 | applicable & SEC_ALLOC); | |
11193 | seg_info (lbss_section)->bss = 1; | |
11194 | ||
11195 | subseg_set (seg, subseg); | |
11196 | } | |
11197 | ||
11198 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
11199 | bss_section = lbss_section; | |
11200 | ||
11201 | s_comm_internal (0, elf_common_parse); | |
11202 | ||
11203 | elf_com_section_ptr = saved_com_section_ptr; | |
11204 | bss_section = saved_bss_section; | |
11205 | } | |
11206 | } | |
11207 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |