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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
2571583a | 2 | Copyright (C) 1989-2017 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d L |
68 | #define LOCK_PREFIX 5 |
69 | #define REX_PREFIX 6 /* must come last. */ | |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
84 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 85 | #define YMMWORD_MNEM_SUFFIX 'y' |
43234a1e | 86 | #define ZMMWORD_MNEM_SUFFIX 'z' |
6305a203 L |
87 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
88 | in instructions. */ | |
89 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
90 | ||
91 | #define END_OF_INSN '\0' | |
92 | ||
93 | /* | |
94 | 'templates' is for grouping together 'template' structures for opcodes | |
95 | of the same name. This is only used for storing the insns in the grand | |
96 | ole hash table of insns. | |
97 | The templates themselves start at START and range up to (but not including) | |
98 | END. | |
99 | */ | |
100 | typedef struct | |
101 | { | |
d3ce72d0 NC |
102 | const insn_template *start; |
103 | const insn_template *end; | |
6305a203 L |
104 | } |
105 | templates; | |
106 | ||
107 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
108 | typedef struct | |
109 | { | |
110 | unsigned int regmem; /* codes register or memory operand */ | |
111 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
112 | unsigned int mode; /* how to interpret regmem & reg */ | |
113 | } | |
114 | modrm_byte; | |
115 | ||
116 | /* x86-64 extension prefix. */ | |
117 | typedef int rex_byte; | |
118 | ||
6305a203 L |
119 | /* 386 opcode byte to code indirect addressing. */ |
120 | typedef struct | |
121 | { | |
122 | unsigned base; | |
123 | unsigned index; | |
124 | unsigned scale; | |
125 | } | |
126 | sib_byte; | |
127 | ||
6305a203 L |
128 | /* x86 arch names, types and features */ |
129 | typedef struct | |
130 | { | |
131 | const char *name; /* arch name */ | |
8a2c8fef | 132 | unsigned int len; /* arch string length */ |
6305a203 L |
133 | enum processor_type type; /* arch type */ |
134 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 135 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
136 | } |
137 | arch_entry; | |
138 | ||
293f5f65 L |
139 | /* Used to turn off indicated flags. */ |
140 | typedef struct | |
141 | { | |
142 | const char *name; /* arch name */ | |
143 | unsigned int len; /* arch string length */ | |
144 | i386_cpu_flags flags; /* cpu feature flags */ | |
145 | } | |
146 | noarch_entry; | |
147 | ||
78f12dd3 | 148 | static void update_code_flag (int, int); |
e3bb37b5 L |
149 | static void set_code_flag (int); |
150 | static void set_16bit_gcc_code_flag (int); | |
151 | static void set_intel_syntax (int); | |
1efbbeb4 | 152 | static void set_intel_mnemonic (int); |
db51cc60 | 153 | static void set_allow_index_reg (int); |
7bab8ab5 | 154 | static void set_check (int); |
e3bb37b5 | 155 | static void set_cpu_arch (int); |
6482c264 | 156 | #ifdef TE_PE |
e3bb37b5 | 157 | static void pe_directive_secrel (int); |
6482c264 | 158 | #endif |
e3bb37b5 L |
159 | static void signed_cons (int); |
160 | static char *output_invalid (int c); | |
ee86248c JB |
161 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
162 | const char *); | |
163 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
164 | const char *); | |
a7619375 | 165 | static int i386_att_operand (char *); |
e3bb37b5 | 166 | static int i386_intel_operand (char *, int); |
ee86248c JB |
167 | static int i386_intel_simplify (expressionS *); |
168 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
169 | static const reg_entry *parse_register (char *, char **); |
170 | static char *parse_insn (char *, char *); | |
171 | static char *parse_operands (char *, const char *); | |
172 | static void swap_operands (void); | |
4d456e3d | 173 | static void swap_2_operands (int, int); |
e3bb37b5 L |
174 | static void optimize_imm (void); |
175 | static void optimize_disp (void); | |
83b16ac6 | 176 | static const insn_template *match_template (char); |
e3bb37b5 L |
177 | static int check_string (void); |
178 | static int process_suffix (void); | |
179 | static int check_byte_reg (void); | |
180 | static int check_long_reg (void); | |
181 | static int check_qword_reg (void); | |
182 | static int check_word_reg (void); | |
183 | static int finalize_imm (void); | |
184 | static int process_operands (void); | |
185 | static const seg_entry *build_modrm_byte (void); | |
186 | static void output_insn (void); | |
187 | static void output_imm (fragS *, offsetT); | |
188 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 189 | #ifndef I386COFF |
e3bb37b5 | 190 | static void s_bss (int); |
252b5132 | 191 | #endif |
17d4e2a2 L |
192 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
193 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
194 | #endif | |
252b5132 | 195 | |
a847613f | 196 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 197 | |
43234a1e L |
198 | /* This struct describes rounding control and SAE in the instruction. */ |
199 | struct RC_Operation | |
200 | { | |
201 | enum rc_type | |
202 | { | |
203 | rne = 0, | |
204 | rd, | |
205 | ru, | |
206 | rz, | |
207 | saeonly | |
208 | } type; | |
209 | int operand; | |
210 | }; | |
211 | ||
212 | static struct RC_Operation rc_op; | |
213 | ||
214 | /* The struct describes masking, applied to OPERAND in the instruction. | |
215 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
216 | whether merging or zeroing mask is used. */ | |
217 | struct Mask_Operation | |
218 | { | |
219 | const reg_entry *mask; | |
220 | unsigned int zeroing; | |
221 | /* The operand where this operation is associated. */ | |
222 | int operand; | |
223 | }; | |
224 | ||
225 | static struct Mask_Operation mask_op; | |
226 | ||
227 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
228 | broadcast factor. */ | |
229 | struct Broadcast_Operation | |
230 | { | |
231 | /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */ | |
232 | int type; | |
233 | ||
234 | /* Index of broadcasted operand. */ | |
235 | int operand; | |
236 | }; | |
237 | ||
238 | static struct Broadcast_Operation broadcast_op; | |
239 | ||
c0f3af97 L |
240 | /* VEX prefix. */ |
241 | typedef struct | |
242 | { | |
43234a1e L |
243 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
244 | unsigned char bytes[4]; | |
c0f3af97 L |
245 | unsigned int length; |
246 | /* Destination or source register specifier. */ | |
247 | const reg_entry *register_specifier; | |
248 | } vex_prefix; | |
249 | ||
252b5132 | 250 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 251 | i386_insn. */ |
252b5132 | 252 | |
520dc8e8 AM |
253 | union i386_op |
254 | { | |
255 | expressionS *disps; | |
256 | expressionS *imms; | |
257 | const reg_entry *regs; | |
258 | }; | |
259 | ||
a65babc9 L |
260 | enum i386_error |
261 | { | |
86e026a4 | 262 | operand_size_mismatch, |
a65babc9 L |
263 | operand_type_mismatch, |
264 | register_type_mismatch, | |
265 | number_of_operands_mismatch, | |
266 | invalid_instruction_suffix, | |
267 | bad_imm4, | |
268 | old_gcc_only, | |
269 | unsupported_with_intel_mnemonic, | |
270 | unsupported_syntax, | |
6c30d220 L |
271 | unsupported, |
272 | invalid_vsib_address, | |
7bab8ab5 | 273 | invalid_vector_register_set, |
43234a1e L |
274 | unsupported_vector_index_register, |
275 | unsupported_broadcast, | |
276 | broadcast_not_on_src_operand, | |
277 | broadcast_needed, | |
278 | unsupported_masking, | |
279 | mask_not_on_destination, | |
280 | no_default_mask, | |
281 | unsupported_rc_sae, | |
282 | rc_sae_operand_not_last_imm, | |
283 | invalid_register_operand, | |
284 | try_vector_disp8 | |
a65babc9 L |
285 | }; |
286 | ||
252b5132 RH |
287 | struct _i386_insn |
288 | { | |
47926f60 | 289 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 290 | insn_template tm; |
252b5132 | 291 | |
7d5e4556 L |
292 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
293 | or qword, if given. */ | |
252b5132 RH |
294 | char suffix; |
295 | ||
47926f60 | 296 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
297 | unsigned int operands; |
298 | ||
299 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
300 | of given register, displacement, memory operands and immediate | |
47926f60 | 301 | operands. */ |
252b5132 RH |
302 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
303 | ||
304 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 305 | use OP[i] for the corresponding operand. */ |
40fb9820 | 306 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 307 | |
520dc8e8 AM |
308 | /* Displacement expression, immediate expression, or register for each |
309 | operand. */ | |
310 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 311 | |
3e73aa7c JH |
312 | /* Flags for operands. */ |
313 | unsigned int flags[MAX_OPERANDS]; | |
314 | #define Operand_PCrel 1 | |
315 | ||
252b5132 | 316 | /* Relocation type for operand */ |
f86103b7 | 317 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 318 | |
252b5132 RH |
319 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
320 | the base index byte below. */ | |
321 | const reg_entry *base_reg; | |
322 | const reg_entry *index_reg; | |
323 | unsigned int log2_scale_factor; | |
324 | ||
325 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 326 | explicit segment overrides are given. */ |
ce8a8b2f | 327 | const seg_entry *seg[2]; |
252b5132 | 328 | |
8325cc63 JB |
329 | /* Copied first memory operand string, for re-checking. */ |
330 | char *memop1_string; | |
331 | ||
252b5132 RH |
332 | /* PREFIX holds all the given prefix opcodes (usually null). |
333 | PREFIXES is the number of prefix opcodes. */ | |
334 | unsigned int prefixes; | |
335 | unsigned char prefix[MAX_PREFIXES]; | |
336 | ||
337 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 338 | addressing modes of this insn are encoded. */ |
252b5132 | 339 | modrm_byte rm; |
3e73aa7c | 340 | rex_byte rex; |
43234a1e | 341 | rex_byte vrex; |
252b5132 | 342 | sib_byte sib; |
c0f3af97 | 343 | vex_prefix vex; |
b6169b20 | 344 | |
43234a1e L |
345 | /* Masking attributes. */ |
346 | struct Mask_Operation *mask; | |
347 | ||
348 | /* Rounding control and SAE attributes. */ | |
349 | struct RC_Operation *rounding; | |
350 | ||
351 | /* Broadcasting attributes. */ | |
352 | struct Broadcast_Operation *broadcast; | |
353 | ||
354 | /* Compressed disp8*N attribute. */ | |
355 | unsigned int memshift; | |
356 | ||
b6169b20 | 357 | /* Swap operand in encoding. */ |
4473e004 | 358 | unsigned int swap_operand; |
891edac4 | 359 | |
a501d77e L |
360 | /* Prefer 8bit or 32bit displacement in encoding. */ |
361 | enum | |
362 | { | |
363 | disp_encoding_default = 0, | |
364 | disp_encoding_8bit, | |
365 | disp_encoding_32bit | |
366 | } disp_encoding; | |
f8a5c266 | 367 | |
d5de92cf L |
368 | /* REP prefix. */ |
369 | const char *rep_prefix; | |
370 | ||
165de32a L |
371 | /* HLE prefix. */ |
372 | const char *hle_prefix; | |
42164a71 | 373 | |
7e8b059b L |
374 | /* Have BND prefix. */ |
375 | const char *bnd_prefix; | |
376 | ||
43234a1e L |
377 | /* Need VREX to support upper 16 registers. */ |
378 | int need_vrex; | |
379 | ||
891edac4 | 380 | /* Error message. */ |
a65babc9 | 381 | enum i386_error error; |
252b5132 RH |
382 | }; |
383 | ||
384 | typedef struct _i386_insn i386_insn; | |
385 | ||
43234a1e L |
386 | /* Link RC type with corresponding string, that'll be looked for in |
387 | asm. */ | |
388 | struct RC_name | |
389 | { | |
390 | enum rc_type type; | |
391 | const char *name; | |
392 | unsigned int len; | |
393 | }; | |
394 | ||
395 | static const struct RC_name RC_NamesTable[] = | |
396 | { | |
397 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
398 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
399 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
400 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
401 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
402 | }; | |
403 | ||
252b5132 RH |
404 | /* List of chars besides those in app.c:symbol_chars that can start an |
405 | operand. Used to prevent the scrubber eating vital white-space. */ | |
43234a1e | 406 | const char extra_symbol_chars[] = "*%-([{" |
252b5132 | 407 | #ifdef LEX_AT |
32137342 NC |
408 | "@" |
409 | #endif | |
410 | #ifdef LEX_QM | |
411 | "?" | |
252b5132 | 412 | #endif |
32137342 | 413 | ; |
252b5132 | 414 | |
29b0f896 AM |
415 | #if (defined (TE_I386AIX) \ |
416 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 417 | && !defined (TE_GNU) \ |
29b0f896 | 418 | && !defined (TE_LINUX) \ |
8d63c93e RM |
419 | && !defined (TE_NACL) \ |
420 | && !defined (TE_NETWARE) \ | |
29b0f896 | 421 | && !defined (TE_FreeBSD) \ |
5b806d27 | 422 | && !defined (TE_DragonFly) \ |
29b0f896 | 423 | && !defined (TE_NetBSD))) |
252b5132 | 424 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
425 | pre-processor is disabled, these aren't very useful. The option |
426 | --divide will remove '/' from this list. */ | |
427 | const char *i386_comment_chars = "#/"; | |
428 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 429 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 430 | |
b3b91714 AM |
431 | #else |
432 | const char *i386_comment_chars = "#"; | |
433 | #define PREFIX_SEPARATOR '/' | |
434 | #endif | |
435 | ||
252b5132 RH |
436 | /* This array holds the chars that only start a comment at the beginning of |
437 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
438 | .line and .file directives will appear in the pre-processed output. |
439 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 440 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
441 | #NO_APP at the beginning of its output. |
442 | Also note that comments started like this one will always work if | |
252b5132 | 443 | '/' isn't otherwise defined. */ |
b3b91714 | 444 | const char line_comment_chars[] = "#/"; |
252b5132 | 445 | |
63a0b638 | 446 | const char line_separator_chars[] = ";"; |
252b5132 | 447 | |
ce8a8b2f AM |
448 | /* Chars that can be used to separate mant from exp in floating point |
449 | nums. */ | |
252b5132 RH |
450 | const char EXP_CHARS[] = "eE"; |
451 | ||
ce8a8b2f AM |
452 | /* Chars that mean this number is a floating point constant |
453 | As in 0f12.456 | |
454 | or 0d1.2345e12. */ | |
252b5132 RH |
455 | const char FLT_CHARS[] = "fFdDxX"; |
456 | ||
ce8a8b2f | 457 | /* Tables for lexical analysis. */ |
252b5132 RH |
458 | static char mnemonic_chars[256]; |
459 | static char register_chars[256]; | |
460 | static char operand_chars[256]; | |
461 | static char identifier_chars[256]; | |
462 | static char digit_chars[256]; | |
463 | ||
ce8a8b2f | 464 | /* Lexical macros. */ |
252b5132 RH |
465 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
466 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
467 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
468 | #define is_space_char(x) ((x) == ' ') | |
469 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
470 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
471 | ||
0234cb7c | 472 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
473 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
474 | ||
475 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
476 | effect this we maintain a stack of saved characters that we've smashed | |
477 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 478 | assembler instruction). */ |
252b5132 | 479 | static char save_stack[32]; |
ce8a8b2f | 480 | static char *save_stack_p; |
252b5132 RH |
481 | #define END_STRING_AND_SAVE(s) \ |
482 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
483 | #define RESTORE_END_STRING(s) \ | |
484 | do { *(s) = *--save_stack_p; } while (0) | |
485 | ||
47926f60 | 486 | /* The instruction we're assembling. */ |
252b5132 RH |
487 | static i386_insn i; |
488 | ||
489 | /* Possible templates for current insn. */ | |
490 | static const templates *current_templates; | |
491 | ||
31b2323c L |
492 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
493 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
494 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 495 | |
47926f60 | 496 | /* Current operand we are working on. */ |
ee86248c | 497 | static int this_operand = -1; |
252b5132 | 498 | |
3e73aa7c JH |
499 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
500 | these. */ | |
501 | ||
502 | enum flag_code { | |
503 | CODE_32BIT, | |
504 | CODE_16BIT, | |
505 | CODE_64BIT }; | |
506 | ||
507 | static enum flag_code flag_code; | |
4fa24527 | 508 | static unsigned int object_64bit; |
862be3fb | 509 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
510 | static int use_rela_relocations = 0; |
511 | ||
7af8ed2d NC |
512 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
513 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
514 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
515 | ||
351f65ca L |
516 | /* The ELF ABI to use. */ |
517 | enum x86_elf_abi | |
518 | { | |
519 | I386_ABI, | |
7f56bc95 L |
520 | X86_64_ABI, |
521 | X86_64_X32_ABI | |
351f65ca L |
522 | }; |
523 | ||
524 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 525 | #endif |
351f65ca | 526 | |
167ad85b TG |
527 | #if defined (TE_PE) || defined (TE_PEP) |
528 | /* Use big object file format. */ | |
529 | static int use_big_obj = 0; | |
530 | #endif | |
531 | ||
8dcea932 L |
532 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
533 | /* 1 if generating code for a shared library. */ | |
534 | static int shared = 0; | |
535 | #endif | |
536 | ||
47926f60 KH |
537 | /* 1 for intel syntax, |
538 | 0 if att syntax. */ | |
539 | static int intel_syntax = 0; | |
252b5132 | 540 | |
e89c5eaa L |
541 | /* 1 for Intel64 ISA, |
542 | 0 if AMD64 ISA. */ | |
543 | static int intel64; | |
544 | ||
1efbbeb4 L |
545 | /* 1 for intel mnemonic, |
546 | 0 if att mnemonic. */ | |
547 | static int intel_mnemonic = !SYSV386_COMPAT; | |
548 | ||
5209009a | 549 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
550 | static int old_gcc = OLDGCC_COMPAT; |
551 | ||
a60de03c JB |
552 | /* 1 if pseudo registers are permitted. */ |
553 | static int allow_pseudo_reg = 0; | |
554 | ||
47926f60 KH |
555 | /* 1 if register prefix % not required. */ |
556 | static int allow_naked_reg = 0; | |
252b5132 | 557 | |
33eaf5de | 558 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
559 | instructions supporting it, even if this prefix wasn't specified |
560 | explicitly. */ | |
561 | static int add_bnd_prefix = 0; | |
562 | ||
ba104c83 | 563 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
564 | static int allow_index_reg = 0; |
565 | ||
d022bddd IT |
566 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
567 | specified explicitly. */ | |
568 | static int omit_lock_prefix = 0; | |
569 | ||
e4e00185 AS |
570 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
571 | "lock addl $0, (%{re}sp)". */ | |
572 | static int avoid_fence = 0; | |
573 | ||
0cb4071e L |
574 | /* 1 if the assembler should generate relax relocations. */ |
575 | ||
576 | static int generate_relax_relocations | |
577 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
578 | ||
7bab8ab5 | 579 | static enum check_kind |
daf50ae7 | 580 | { |
7bab8ab5 JB |
581 | check_none = 0, |
582 | check_warning, | |
583 | check_error | |
daf50ae7 | 584 | } |
7bab8ab5 | 585 | sse_check, operand_check = check_warning; |
daf50ae7 | 586 | |
2ca3ace5 L |
587 | /* Register prefix used for error message. */ |
588 | static const char *register_prefix = "%"; | |
589 | ||
47926f60 KH |
590 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
591 | leave, push, and pop instructions so that gcc has the same stack | |
592 | frame as in 32 bit mode. */ | |
593 | static char stackop_size = '\0'; | |
eecb386c | 594 | |
12b55ccc L |
595 | /* Non-zero to optimize code alignment. */ |
596 | int optimize_align_code = 1; | |
597 | ||
47926f60 KH |
598 | /* Non-zero to quieten some warnings. */ |
599 | static int quiet_warnings = 0; | |
a38cf1db | 600 | |
47926f60 KH |
601 | /* CPU name. */ |
602 | static const char *cpu_arch_name = NULL; | |
6305a203 | 603 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 604 | |
47926f60 | 605 | /* CPU feature flags. */ |
40fb9820 L |
606 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
607 | ||
ccc9c027 L |
608 | /* If we have selected a cpu we are generating instructions for. */ |
609 | static int cpu_arch_tune_set = 0; | |
610 | ||
9103f4f4 | 611 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 612 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
613 | |
614 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 615 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 616 | |
ccc9c027 | 617 | /* CPU instruction set architecture used. */ |
fbf3f584 | 618 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 619 | |
9103f4f4 | 620 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 621 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 622 | |
fddf5b5b AM |
623 | /* If set, conditional jumps are not automatically promoted to handle |
624 | larger than a byte offset. */ | |
625 | static unsigned int no_cond_jump_promotion = 0; | |
626 | ||
c0f3af97 L |
627 | /* Encode SSE instructions with VEX prefix. */ |
628 | static unsigned int sse2avx; | |
629 | ||
539f890d L |
630 | /* Encode scalar AVX instructions with specific vector length. */ |
631 | static enum | |
632 | { | |
633 | vex128 = 0, | |
634 | vex256 | |
635 | } avxscalar; | |
636 | ||
43234a1e L |
637 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
638 | static enum | |
639 | { | |
640 | evexl128 = 0, | |
641 | evexl256, | |
642 | evexl512 | |
643 | } evexlig; | |
644 | ||
645 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
646 | static enum | |
647 | { | |
648 | evexw0 = 0, | |
649 | evexw1 | |
650 | } evexwig; | |
651 | ||
d3d3c6db IT |
652 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
653 | static enum rc_type evexrcig = rne; | |
654 | ||
29b0f896 | 655 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 656 | static symbolS *GOT_symbol; |
29b0f896 | 657 | |
a4447b93 RH |
658 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
659 | unsigned int x86_dwarf2_return_column; | |
660 | ||
661 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
662 | int x86_cie_data_alignment; | |
663 | ||
252b5132 | 664 | /* Interface to relax_segment. |
fddf5b5b AM |
665 | There are 3 major relax states for 386 jump insns because the |
666 | different types of jumps add different sizes to frags when we're | |
667 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 668 | |
47926f60 | 669 | /* Types. */ |
93c2a809 AM |
670 | #define UNCOND_JUMP 0 |
671 | #define COND_JUMP 1 | |
672 | #define COND_JUMP86 2 | |
fddf5b5b | 673 | |
47926f60 | 674 | /* Sizes. */ |
252b5132 RH |
675 | #define CODE16 1 |
676 | #define SMALL 0 | |
29b0f896 | 677 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 678 | #define BIG 2 |
29b0f896 | 679 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
680 | |
681 | #ifndef INLINE | |
682 | #ifdef __GNUC__ | |
683 | #define INLINE __inline__ | |
684 | #else | |
685 | #define INLINE | |
686 | #endif | |
687 | #endif | |
688 | ||
fddf5b5b AM |
689 | #define ENCODE_RELAX_STATE(type, size) \ |
690 | ((relax_substateT) (((type) << 2) | (size))) | |
691 | #define TYPE_FROM_RELAX_STATE(s) \ | |
692 | ((s) >> 2) | |
693 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
694 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
695 | |
696 | /* This table is used by relax_frag to promote short jumps to long | |
697 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
698 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
699 | don't allow a short jump in a 32 bit code segment to be promoted to | |
700 | a 16 bit offset jump because it's slower (requires data size | |
701 | prefix), and doesn't work, unless the destination is in the bottom | |
702 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
703 | ||
704 | const relax_typeS md_relax_table[] = | |
705 | { | |
24eab124 AM |
706 | /* The fields are: |
707 | 1) most positive reach of this state, | |
708 | 2) most negative reach of this state, | |
93c2a809 | 709 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 710 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 711 | |
fddf5b5b | 712 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
713 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
714 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
715 | /* dword jmp adds 4 bytes to frag: | |
716 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 717 | {0, 0, 4, 0}, |
93c2a809 AM |
718 | /* word jmp adds 2 byte2 to frag: |
719 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
720 | {0, 0, 2, 0}, |
721 | ||
93c2a809 AM |
722 | /* COND_JUMP states. */ |
723 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
724 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
725 | /* dword conditionals adds 5 bytes to frag: | |
726 | 1 extra opcode byte, 4 displacement bytes. */ | |
727 | {0, 0, 5, 0}, | |
fddf5b5b | 728 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
729 | 1 extra opcode byte, 2 displacement bytes. */ |
730 | {0, 0, 3, 0}, | |
731 | ||
732 | /* COND_JUMP86 states. */ | |
733 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
734 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
735 | /* dword conditionals adds 5 bytes to frag: | |
736 | 1 extra opcode byte, 4 displacement bytes. */ | |
737 | {0, 0, 5, 0}, | |
738 | /* word conditionals add 4 bytes to frag: | |
739 | 1 displacement byte and a 3 byte long branch insn. */ | |
740 | {0, 0, 4, 0} | |
252b5132 RH |
741 | }; |
742 | ||
9103f4f4 L |
743 | static const arch_entry cpu_arch[] = |
744 | { | |
89507696 JB |
745 | /* Do not replace the first two entries - i386_target_format() |
746 | relies on them being there in this order. */ | |
8a2c8fef | 747 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 748 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 749 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 750 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 751 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 752 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 753 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 754 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 755 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 756 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 757 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 758 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 759 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 760 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 761 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 762 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 763 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 764 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 765 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 766 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 767 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 768 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 769 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 770 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 771 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 772 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 773 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 774 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 775 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 776 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 777 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 778 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 779 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 780 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 781 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 782 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 783 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 784 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 785 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 786 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 787 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 788 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 789 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 790 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 791 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 792 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 793 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 794 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 795 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 796 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 797 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 798 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 799 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 800 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 801 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 802 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 803 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 804 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 805 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 806 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 807 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 808 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 809 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 810 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 811 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 812 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 813 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 814 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 815 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 816 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 817 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 818 | CPU_ZNVER1_FLAGS, 0 }, |
7b458c12 | 819 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 820 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 821 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 822 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 823 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 824 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 825 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 826 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 827 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 828 | CPU_387_FLAGS, 0 }, |
1848e567 L |
829 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
830 | CPU_687_FLAGS, 0 }, | |
8a2c8fef | 831 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 832 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 833 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 834 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 835 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 836 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 837 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 838 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 839 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 840 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 841 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 842 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 843 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 844 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 845 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 846 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 847 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 848 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 849 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 850 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 851 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 852 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 853 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 854 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 855 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 856 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 857 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 858 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 859 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 860 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 861 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 862 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 863 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 864 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 865 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 866 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 867 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 868 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 869 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 870 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 871 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 872 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 873 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 874 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 875 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 876 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 877 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 878 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 879 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 880 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 881 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 882 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 883 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 884 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 885 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 886 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 887 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 888 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 889 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 890 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 891 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 892 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 893 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 894 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 895 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 896 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 897 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 898 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 899 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 900 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 901 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 902 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 903 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 904 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 905 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 906 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 907 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 908 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 909 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 910 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 911 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 912 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 913 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 915 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 917 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 919 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 920 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 922 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 923 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 924 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 925 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 926 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 927 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 928 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 929 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 930 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 931 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 932 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 933 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 934 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 935 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 936 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 937 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 938 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 939 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 940 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 941 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 942 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 943 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 944 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 945 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 946 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 947 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 948 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 949 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 950 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 951 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 952 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 953 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 954 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 955 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 956 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 957 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 958 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 959 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 960 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 961 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 962 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 963 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 964 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
965 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
966 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
967 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
968 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
969 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
970 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
029f3522 | 971 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 972 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 973 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 974 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 975 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 976 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 977 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 978 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
979 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
980 | CPU_PTWRITE_FLAGS, 0 }, | |
293f5f65 L |
981 | }; |
982 | ||
983 | static const noarch_entry cpu_noarch[] = | |
984 | { | |
985 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
986 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
987 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
988 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
293f5f65 L |
989 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
990 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
991 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
992 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
993 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
994 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
995 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
996 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 997 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 998 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
999 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1000 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1001 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1002 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1003 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1004 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1005 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1006 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1007 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1008 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1009 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1010 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
e413e4e9 AM |
1011 | }; |
1012 | ||
704209c0 | 1013 | #ifdef I386COFF |
a6c24e68 NC |
1014 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1015 | is allowed to be optional. */ | |
1016 | ||
1017 | static symbolS * | |
1018 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1019 | { | |
1020 | addressT align = 0; | |
1021 | ||
1022 | SKIP_WHITESPACE (); | |
1023 | ||
7ab9ffdd | 1024 | if (needs_align |
a6c24e68 NC |
1025 | && *input_line_pointer == ',') |
1026 | { | |
1027 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1028 | |
a6c24e68 NC |
1029 | if (align == (addressT) -1) |
1030 | return NULL; | |
1031 | } | |
1032 | else | |
1033 | { | |
1034 | if (size >= 8) | |
1035 | align = 3; | |
1036 | else if (size >= 4) | |
1037 | align = 2; | |
1038 | else if (size >= 2) | |
1039 | align = 1; | |
1040 | else | |
1041 | align = 0; | |
1042 | } | |
1043 | ||
1044 | bss_alloc (symbolP, size, align); | |
1045 | return symbolP; | |
1046 | } | |
1047 | ||
704209c0 | 1048 | static void |
a6c24e68 NC |
1049 | pe_lcomm (int needs_align) |
1050 | { | |
1051 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1052 | } | |
704209c0 | 1053 | #endif |
a6c24e68 | 1054 | |
29b0f896 AM |
1055 | const pseudo_typeS md_pseudo_table[] = |
1056 | { | |
1057 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1058 | {"align", s_align_bytes, 0}, | |
1059 | #else | |
1060 | {"align", s_align_ptwo, 0}, | |
1061 | #endif | |
1062 | {"arch", set_cpu_arch, 0}, | |
1063 | #ifndef I386COFF | |
1064 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1065 | #else |
1066 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1067 | #endif |
1068 | {"ffloat", float_cons, 'f'}, | |
1069 | {"dfloat", float_cons, 'd'}, | |
1070 | {"tfloat", float_cons, 'x'}, | |
1071 | {"value", cons, 2}, | |
d182319b | 1072 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1073 | {"noopt", s_ignore, 0}, |
1074 | {"optim", s_ignore, 0}, | |
1075 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1076 | {"code16", set_code_flag, CODE_16BIT}, | |
1077 | {"code32", set_code_flag, CODE_32BIT}, | |
1078 | {"code64", set_code_flag, CODE_64BIT}, | |
1079 | {"intel_syntax", set_intel_syntax, 1}, | |
1080 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1081 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1082 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1083 | {"allow_index_reg", set_allow_index_reg, 1}, |
1084 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1085 | {"sse_check", set_check, 0}, |
1086 | {"operand_check", set_check, 1}, | |
3b22753a L |
1087 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1088 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1089 | #else |
e3bb37b5 | 1090 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
1091 | {"loc", dwarf2_directive_loc, 0}, |
1092 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1093 | #endif |
6482c264 NC |
1094 | #ifdef TE_PE |
1095 | {"secrel32", pe_directive_secrel, 0}, | |
1096 | #endif | |
29b0f896 AM |
1097 | {0, 0, 0} |
1098 | }; | |
1099 | ||
1100 | /* For interface with expression (). */ | |
1101 | extern char *input_line_pointer; | |
1102 | ||
1103 | /* Hash table for instruction mnemonic lookup. */ | |
1104 | static struct hash_control *op_hash; | |
1105 | ||
1106 | /* Hash table for register lookup. */ | |
1107 | static struct hash_control *reg_hash; | |
1108 | \f | |
252b5132 | 1109 | void |
e3bb37b5 | 1110 | i386_align_code (fragS *fragP, int count) |
252b5132 | 1111 | { |
ce8a8b2f AM |
1112 | /* Various efficient no-op patterns for aligning code labels. |
1113 | Note: Don't try to assemble the instructions in the comments. | |
1114 | 0L and 0w are not legal. */ | |
bad6e36d | 1115 | static const unsigned char f32_1[] = |
252b5132 | 1116 | {0x90}; /* nop */ |
bad6e36d | 1117 | static const unsigned char f32_2[] = |
ccc9c027 | 1118 | {0x66,0x90}; /* xchg %ax,%ax */ |
bad6e36d | 1119 | static const unsigned char f32_3[] = |
252b5132 | 1120 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ |
bad6e36d | 1121 | static const unsigned char f32_4[] = |
252b5132 | 1122 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
bad6e36d | 1123 | static const unsigned char f32_5[] = |
252b5132 RH |
1124 | {0x90, /* nop */ |
1125 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
bad6e36d | 1126 | static const unsigned char f32_6[] = |
252b5132 | 1127 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ |
bad6e36d | 1128 | static const unsigned char f32_7[] = |
252b5132 | 1129 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
bad6e36d | 1130 | static const unsigned char f32_8[] = |
252b5132 RH |
1131 | {0x90, /* nop */ |
1132 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
bad6e36d | 1133 | static const unsigned char f32_9[] = |
252b5132 RH |
1134 | {0x89,0xf6, /* movl %esi,%esi */ |
1135 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1136 | static const unsigned char f32_10[] = |
252b5132 RH |
1137 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ |
1138 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1139 | static const unsigned char f32_11[] = |
252b5132 RH |
1140 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ |
1141 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1142 | static const unsigned char f32_12[] = |
252b5132 RH |
1143 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
1144 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
bad6e36d | 1145 | static const unsigned char f32_13[] = |
252b5132 RH |
1146 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
1147 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1148 | static const unsigned char f32_14[] = |
252b5132 RH |
1149 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ |
1150 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1151 | static const unsigned char f16_3[] = |
c3332e24 | 1152 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ |
bad6e36d | 1153 | static const unsigned char f16_4[] = |
252b5132 | 1154 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
bad6e36d | 1155 | static const unsigned char f16_5[] = |
252b5132 RH |
1156 | {0x90, /* nop */ |
1157 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
bad6e36d | 1158 | static const unsigned char f16_6[] = |
252b5132 RH |
1159 | {0x89,0xf6, /* mov %si,%si */ |
1160 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1161 | static const unsigned char f16_7[] = |
252b5132 RH |
1162 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
1163 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1164 | static const unsigned char f16_8[] = |
252b5132 RH |
1165 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
1166 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1167 | static const unsigned char jump_31[] = |
76bc74dc L |
1168 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ |
1169 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
1170 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
1171 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
bad6e36d | 1172 | static const unsigned char *const f32_patt[] = { |
252b5132 | 1173 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, |
76bc74dc | 1174 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 | 1175 | }; |
bad6e36d | 1176 | static const unsigned char *const f16_patt[] = { |
76bc74dc | 1177 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 1178 | }; |
ccc9c027 | 1179 | /* nopl (%[re]ax) */ |
bad6e36d | 1180 | static const unsigned char alt_3[] = |
ccc9c027 L |
1181 | {0x0f,0x1f,0x00}; |
1182 | /* nopl 0(%[re]ax) */ | |
bad6e36d | 1183 | static const unsigned char alt_4[] = |
ccc9c027 L |
1184 | {0x0f,0x1f,0x40,0x00}; |
1185 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1186 | static const unsigned char alt_5[] = |
ccc9c027 L |
1187 | {0x0f,0x1f,0x44,0x00,0x00}; |
1188 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1189 | static const unsigned char alt_6[] = |
ccc9c027 L |
1190 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; |
1191 | /* nopl 0L(%[re]ax) */ | |
bad6e36d | 1192 | static const unsigned char alt_7[] = |
ccc9c027 L |
1193 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; |
1194 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1195 | static const unsigned char alt_8[] = |
ccc9c027 L |
1196 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
1197 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1198 | static const unsigned char alt_9[] = |
ccc9c027 L |
1199 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
1200 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1201 | static const unsigned char alt_10[] = |
ccc9c027 | 1202 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
bad6e36d | 1203 | static const unsigned char *const alt_patt[] = { |
ccc9c027 | 1204 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, |
80b8656c | 1205 | alt_9, alt_10 |
ccc9c027 | 1206 | }; |
252b5132 | 1207 | |
76bc74dc L |
1208 | /* Only align for at least a positive non-zero boundary. */ |
1209 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 1210 | return; |
3e73aa7c | 1211 | |
ccc9c027 L |
1212 | /* We need to decide which NOP sequence to use for 32bit and |
1213 | 64bit. When -mtune= is used: | |
4eed87de | 1214 | |
76bc74dc L |
1215 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1216 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1217 | 2. For the rest, alt_patt will be used. |
1218 | ||
1219 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1220 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1221 | be used. |
ccc9c027 L |
1222 | |
1223 | When -march= or .arch is used, we can't use anything beyond | |
1224 | cpu_arch_isa_flags. */ | |
1225 | ||
1226 | if (flag_code == CODE_16BIT) | |
1227 | { | |
ccc9c027 | 1228 | if (count > 8) |
33fef721 | 1229 | { |
76bc74dc L |
1230 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1231 | jump_31, count); | |
1232 | /* Adjust jump offset. */ | |
1233 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 1234 | } |
76bc74dc L |
1235 | else |
1236 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1237 | f16_patt[count - 1], count); | |
252b5132 | 1238 | } |
33fef721 | 1239 | else |
ccc9c027 | 1240 | { |
bad6e36d | 1241 | const unsigned char *const *patt = NULL; |
ccc9c027 | 1242 | |
fbf3f584 | 1243 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1244 | { |
1245 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1246 | switch (cpu_arch_tune) | |
1247 | { | |
1248 | case PROCESSOR_UNKNOWN: | |
1249 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1250 | optimize with nops. */ |
1251 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1252 | patt = alt_patt; |
ccc9c027 L |
1253 | else |
1254 | patt = f32_patt; | |
1255 | break; | |
ccc9c027 L |
1256 | case PROCESSOR_PENTIUM4: |
1257 | case PROCESSOR_NOCONA: | |
ef05d495 | 1258 | case PROCESSOR_CORE: |
76bc74dc | 1259 | case PROCESSOR_CORE2: |
bd5295b2 | 1260 | case PROCESSOR_COREI7: |
3632d14b | 1261 | case PROCESSOR_L1OM: |
7a9068fe | 1262 | case PROCESSOR_K1OM: |
76bc74dc | 1263 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1264 | case PROCESSOR_K6: |
1265 | case PROCESSOR_ATHLON: | |
1266 | case PROCESSOR_K8: | |
4eed87de | 1267 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1268 | case PROCESSOR_BD: |
029f3522 | 1269 | case PROCESSOR_ZNVER: |
7b458c12 | 1270 | case PROCESSOR_BT: |
80b8656c | 1271 | patt = alt_patt; |
ccc9c027 | 1272 | break; |
76bc74dc | 1273 | case PROCESSOR_I386: |
ccc9c027 L |
1274 | case PROCESSOR_I486: |
1275 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1276 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1277 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1278 | case PROCESSOR_GENERIC32: |
1279 | patt = f32_patt; | |
1280 | break; | |
4eed87de | 1281 | } |
ccc9c027 L |
1282 | } |
1283 | else | |
1284 | { | |
fbf3f584 | 1285 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1286 | { |
1287 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1288 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1289 | PROCESSOR_UNKNOWN. */ |
1290 | abort (); | |
1291 | break; | |
1292 | ||
76bc74dc | 1293 | case PROCESSOR_I386: |
ccc9c027 L |
1294 | case PROCESSOR_I486: |
1295 | case PROCESSOR_PENTIUM: | |
81486035 | 1296 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1297 | case PROCESSOR_K6: |
1298 | case PROCESSOR_ATHLON: | |
1299 | case PROCESSOR_K8: | |
4eed87de | 1300 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1301 | case PROCESSOR_BD: |
029f3522 | 1302 | case PROCESSOR_ZNVER: |
7b458c12 | 1303 | case PROCESSOR_BT: |
ccc9c027 L |
1304 | case PROCESSOR_GENERIC32: |
1305 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1306 | with nops. */ |
1307 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1308 | patt = alt_patt; |
ccc9c027 L |
1309 | else |
1310 | patt = f32_patt; | |
1311 | break; | |
76bc74dc L |
1312 | case PROCESSOR_PENTIUMPRO: |
1313 | case PROCESSOR_PENTIUM4: | |
1314 | case PROCESSOR_NOCONA: | |
1315 | case PROCESSOR_CORE: | |
ef05d495 | 1316 | case PROCESSOR_CORE2: |
bd5295b2 | 1317 | case PROCESSOR_COREI7: |
3632d14b | 1318 | case PROCESSOR_L1OM: |
7a9068fe | 1319 | case PROCESSOR_K1OM: |
22109423 | 1320 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1321 | patt = alt_patt; |
ccc9c027 L |
1322 | else |
1323 | patt = f32_patt; | |
1324 | break; | |
1325 | case PROCESSOR_GENERIC64: | |
80b8656c | 1326 | patt = alt_patt; |
ccc9c027 | 1327 | break; |
4eed87de | 1328 | } |
ccc9c027 L |
1329 | } |
1330 | ||
76bc74dc L |
1331 | if (patt == f32_patt) |
1332 | { | |
1333 | /* If the padding is less than 15 bytes, we use the normal | |
1334 | ones. Otherwise, we use a jump instruction and adjust | |
711eedef L |
1335 | its offset. */ |
1336 | int limit; | |
76ba9986 | 1337 | |
711eedef L |
1338 | /* For 64bit, the limit is 3 bytes. */ |
1339 | if (flag_code == CODE_64BIT | |
1340 | && fragP->tc_frag_data.isa_flags.bitfield.cpulm) | |
1341 | limit = 3; | |
1342 | else | |
1343 | limit = 15; | |
1344 | if (count < limit) | |
76bc74dc L |
1345 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1346 | patt[count - 1], count); | |
1347 | else | |
1348 | { | |
1349 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1350 | jump_31, count); | |
1351 | /* Adjust jump offset. */ | |
1352 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1353 | } | |
1354 | } | |
1355 | else | |
1356 | { | |
80b8656c L |
1357 | /* Maximum length of an instruction is 10 byte. If the |
1358 | padding is greater than 10 bytes and we don't use jump, | |
76bc74dc L |
1359 | we have to break it into smaller pieces. */ |
1360 | int padding = count; | |
80b8656c | 1361 | while (padding > 10) |
76bc74dc | 1362 | { |
80b8656c | 1363 | padding -= 10; |
76bc74dc | 1364 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, |
80b8656c | 1365 | patt [9], 10); |
76bc74dc L |
1366 | } |
1367 | ||
1368 | if (padding) | |
1369 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1370 | patt [padding - 1], padding); | |
1371 | } | |
ccc9c027 | 1372 | } |
33fef721 | 1373 | fragP->fr_var = count; |
252b5132 RH |
1374 | } |
1375 | ||
c6fb90c8 | 1376 | static INLINE int |
0dfbf9d7 | 1377 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1378 | { |
0dfbf9d7 | 1379 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1380 | { |
1381 | case 3: | |
0dfbf9d7 | 1382 | if (x->array[2]) |
c6fb90c8 | 1383 | return 0; |
1a0670f3 | 1384 | /* Fall through. */ |
c6fb90c8 | 1385 | case 2: |
0dfbf9d7 | 1386 | if (x->array[1]) |
c6fb90c8 | 1387 | return 0; |
1a0670f3 | 1388 | /* Fall through. */ |
c6fb90c8 | 1389 | case 1: |
0dfbf9d7 | 1390 | return !x->array[0]; |
c6fb90c8 L |
1391 | default: |
1392 | abort (); | |
1393 | } | |
40fb9820 L |
1394 | } |
1395 | ||
c6fb90c8 | 1396 | static INLINE void |
0dfbf9d7 | 1397 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1398 | { |
0dfbf9d7 | 1399 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1400 | { |
1401 | case 3: | |
0dfbf9d7 | 1402 | x->array[2] = v; |
1a0670f3 | 1403 | /* Fall through. */ |
c6fb90c8 | 1404 | case 2: |
0dfbf9d7 | 1405 | x->array[1] = v; |
1a0670f3 | 1406 | /* Fall through. */ |
c6fb90c8 | 1407 | case 1: |
0dfbf9d7 | 1408 | x->array[0] = v; |
1a0670f3 | 1409 | /* Fall through. */ |
c6fb90c8 L |
1410 | break; |
1411 | default: | |
1412 | abort (); | |
1413 | } | |
1414 | } | |
40fb9820 | 1415 | |
c6fb90c8 | 1416 | static INLINE int |
0dfbf9d7 L |
1417 | operand_type_equal (const union i386_operand_type *x, |
1418 | const union i386_operand_type *y) | |
c6fb90c8 | 1419 | { |
0dfbf9d7 | 1420 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1421 | { |
1422 | case 3: | |
0dfbf9d7 | 1423 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1424 | return 0; |
1a0670f3 | 1425 | /* Fall through. */ |
c6fb90c8 | 1426 | case 2: |
0dfbf9d7 | 1427 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1428 | return 0; |
1a0670f3 | 1429 | /* Fall through. */ |
c6fb90c8 | 1430 | case 1: |
0dfbf9d7 | 1431 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1432 | break; |
1433 | default: | |
1434 | abort (); | |
1435 | } | |
1436 | } | |
40fb9820 | 1437 | |
0dfbf9d7 L |
1438 | static INLINE int |
1439 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1440 | { | |
1441 | switch (ARRAY_SIZE(x->array)) | |
1442 | { | |
1443 | case 3: | |
1444 | if (x->array[2]) | |
1445 | return 0; | |
1a0670f3 | 1446 | /* Fall through. */ |
0dfbf9d7 L |
1447 | case 2: |
1448 | if (x->array[1]) | |
1449 | return 0; | |
1a0670f3 | 1450 | /* Fall through. */ |
0dfbf9d7 L |
1451 | case 1: |
1452 | return !x->array[0]; | |
1453 | default: | |
1454 | abort (); | |
1455 | } | |
1456 | } | |
1457 | ||
0dfbf9d7 L |
1458 | static INLINE int |
1459 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1460 | const union i386_cpu_flags *y) | |
1461 | { | |
1462 | switch (ARRAY_SIZE(x->array)) | |
1463 | { | |
1464 | case 3: | |
1465 | if (x->array[2] != y->array[2]) | |
1466 | return 0; | |
1a0670f3 | 1467 | /* Fall through. */ |
0dfbf9d7 L |
1468 | case 2: |
1469 | if (x->array[1] != y->array[1]) | |
1470 | return 0; | |
1a0670f3 | 1471 | /* Fall through. */ |
0dfbf9d7 L |
1472 | case 1: |
1473 | return x->array[0] == y->array[0]; | |
1474 | break; | |
1475 | default: | |
1476 | abort (); | |
1477 | } | |
1478 | } | |
c6fb90c8 L |
1479 | |
1480 | static INLINE int | |
1481 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1482 | { | |
1483 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1484 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1485 | } |
1486 | ||
c6fb90c8 L |
1487 | static INLINE i386_cpu_flags |
1488 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1489 | { |
c6fb90c8 L |
1490 | switch (ARRAY_SIZE (x.array)) |
1491 | { | |
1492 | case 3: | |
1493 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1494 | /* Fall through. */ |
c6fb90c8 L |
1495 | case 2: |
1496 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1497 | /* Fall through. */ |
c6fb90c8 L |
1498 | case 1: |
1499 | x.array [0] &= y.array [0]; | |
1500 | break; | |
1501 | default: | |
1502 | abort (); | |
1503 | } | |
1504 | return x; | |
1505 | } | |
40fb9820 | 1506 | |
c6fb90c8 L |
1507 | static INLINE i386_cpu_flags |
1508 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1509 | { |
c6fb90c8 | 1510 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1511 | { |
c6fb90c8 L |
1512 | case 3: |
1513 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1514 | /* Fall through. */ |
c6fb90c8 L |
1515 | case 2: |
1516 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1517 | /* Fall through. */ |
c6fb90c8 L |
1518 | case 1: |
1519 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1520 | break; |
1521 | default: | |
1522 | abort (); | |
1523 | } | |
40fb9820 L |
1524 | return x; |
1525 | } | |
1526 | ||
309d3373 JB |
1527 | static INLINE i386_cpu_flags |
1528 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1529 | { | |
1530 | switch (ARRAY_SIZE (x.array)) | |
1531 | { | |
1532 | case 3: | |
1533 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1534 | /* Fall through. */ |
309d3373 JB |
1535 | case 2: |
1536 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1537 | /* Fall through. */ |
309d3373 JB |
1538 | case 1: |
1539 | x.array [0] &= ~y.array [0]; | |
1540 | break; | |
1541 | default: | |
1542 | abort (); | |
1543 | } | |
1544 | return x; | |
1545 | } | |
1546 | ||
c0f3af97 L |
1547 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1548 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1549 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1550 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1551 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1552 | |
a5ff0eb2 | 1553 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1554 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1555 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1556 | #define CPU_FLAGS_PERFECT_MATCH \ |
1557 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1558 | ||
1559 | /* Return CPU flags match bits. */ | |
3629bb00 | 1560 | |
40fb9820 | 1561 | static int |
d3ce72d0 | 1562 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1563 | { |
c0f3af97 L |
1564 | i386_cpu_flags x = t->cpu_flags; |
1565 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1566 | |
1567 | x.bitfield.cpu64 = 0; | |
1568 | x.bitfield.cpuno64 = 0; | |
1569 | ||
0dfbf9d7 | 1570 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1571 | { |
1572 | /* This instruction is available on all archs. */ | |
1573 | match |= CPU_FLAGS_32BIT_MATCH; | |
1574 | } | |
3629bb00 L |
1575 | else |
1576 | { | |
c0f3af97 | 1577 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1578 | i386_cpu_flags cpu = cpu_arch_flags; |
1579 | ||
3629bb00 | 1580 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1581 | if (!cpu_flags_all_zero (&cpu)) |
1582 | { | |
a5ff0eb2 L |
1583 | if (x.bitfield.cpuavx) |
1584 | { | |
ce2f5b3c | 1585 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1586 | if (cpu.bitfield.cpuavx) |
1587 | { | |
1588 | /* Check SSE2AVX. */ | |
1589 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1590 | { | |
1591 | match |= (CPU_FLAGS_ARCH_MATCH | |
1592 | | CPU_FLAGS_AVX_MATCH); | |
1593 | /* Check AES. */ | |
1594 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1595 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1596 | /* Check PCLMUL. */ |
1597 | if (!x.bitfield.cpupclmul | |
1598 | || cpu.bitfield.cpupclmul) | |
1599 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1600 | } |
1601 | } | |
1602 | else | |
1603 | match |= CPU_FLAGS_ARCH_MATCH; | |
1604 | } | |
73b090a9 L |
1605 | else if (x.bitfield.cpuavx512vl) |
1606 | { | |
1607 | /* Match AVX512VL. */ | |
1608 | if (cpu.bitfield.cpuavx512vl) | |
1609 | { | |
1610 | /* Need another match. */ | |
1611 | cpu.bitfield.cpuavx512vl = 0; | |
1612 | if (!cpu_flags_all_zero (&cpu)) | |
1613 | match |= CPU_FLAGS_32BIT_MATCH; | |
1614 | else | |
1615 | match |= CPU_FLAGS_ARCH_MATCH; | |
1616 | } | |
1617 | else | |
1618 | match |= CPU_FLAGS_ARCH_MATCH; | |
1619 | } | |
a5ff0eb2 | 1620 | else |
c0f3af97 L |
1621 | match |= CPU_FLAGS_32BIT_MATCH; |
1622 | } | |
3629bb00 | 1623 | } |
c0f3af97 | 1624 | return match; |
40fb9820 L |
1625 | } |
1626 | ||
c6fb90c8 L |
1627 | static INLINE i386_operand_type |
1628 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1629 | { |
c6fb90c8 L |
1630 | switch (ARRAY_SIZE (x.array)) |
1631 | { | |
1632 | case 3: | |
1633 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1634 | /* Fall through. */ |
c6fb90c8 L |
1635 | case 2: |
1636 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1637 | /* Fall through. */ |
c6fb90c8 L |
1638 | case 1: |
1639 | x.array [0] &= y.array [0]; | |
1640 | break; | |
1641 | default: | |
1642 | abort (); | |
1643 | } | |
1644 | return x; | |
40fb9820 L |
1645 | } |
1646 | ||
c6fb90c8 L |
1647 | static INLINE i386_operand_type |
1648 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1649 | { |
c6fb90c8 | 1650 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1651 | { |
c6fb90c8 L |
1652 | case 3: |
1653 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1654 | /* Fall through. */ |
c6fb90c8 L |
1655 | case 2: |
1656 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1657 | /* Fall through. */ |
c6fb90c8 L |
1658 | case 1: |
1659 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1660 | break; |
1661 | default: | |
1662 | abort (); | |
1663 | } | |
c6fb90c8 L |
1664 | return x; |
1665 | } | |
40fb9820 | 1666 | |
c6fb90c8 L |
1667 | static INLINE i386_operand_type |
1668 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1669 | { | |
1670 | switch (ARRAY_SIZE (x.array)) | |
1671 | { | |
1672 | case 3: | |
1673 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1674 | /* Fall through. */ |
c6fb90c8 L |
1675 | case 2: |
1676 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1677 | /* Fall through. */ |
c6fb90c8 L |
1678 | case 1: |
1679 | x.array [0] ^= y.array [0]; | |
1680 | break; | |
1681 | default: | |
1682 | abort (); | |
1683 | } | |
40fb9820 L |
1684 | return x; |
1685 | } | |
1686 | ||
1687 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1688 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1689 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1690 | static const i386_operand_type inoutportreg |
1691 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1692 | static const i386_operand_type reg16_inoutportreg |
1693 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1694 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1695 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1696 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1697 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1698 | static const i386_operand_type anydisp | |
1699 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1700 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
c0f3af97 | 1701 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
43234a1e L |
1702 | static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM; |
1703 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; | |
40fb9820 L |
1704 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1705 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1706 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1707 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1708 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1709 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1710 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1711 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1712 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1713 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1714 | |
1715 | enum operand_type | |
1716 | { | |
1717 | reg, | |
40fb9820 L |
1718 | imm, |
1719 | disp, | |
1720 | anymem | |
1721 | }; | |
1722 | ||
c6fb90c8 | 1723 | static INLINE int |
40fb9820 L |
1724 | operand_type_check (i386_operand_type t, enum operand_type c) |
1725 | { | |
1726 | switch (c) | |
1727 | { | |
1728 | case reg: | |
1729 | return (t.bitfield.reg8 | |
1730 | || t.bitfield.reg16 | |
1731 | || t.bitfield.reg32 | |
1732 | || t.bitfield.reg64); | |
1733 | ||
40fb9820 L |
1734 | case imm: |
1735 | return (t.bitfield.imm8 | |
1736 | || t.bitfield.imm8s | |
1737 | || t.bitfield.imm16 | |
1738 | || t.bitfield.imm32 | |
1739 | || t.bitfield.imm32s | |
1740 | || t.bitfield.imm64); | |
1741 | ||
1742 | case disp: | |
1743 | return (t.bitfield.disp8 | |
1744 | || t.bitfield.disp16 | |
1745 | || t.bitfield.disp32 | |
1746 | || t.bitfield.disp32s | |
1747 | || t.bitfield.disp64); | |
1748 | ||
1749 | case anymem: | |
1750 | return (t.bitfield.disp8 | |
1751 | || t.bitfield.disp16 | |
1752 | || t.bitfield.disp32 | |
1753 | || t.bitfield.disp32s | |
1754 | || t.bitfield.disp64 | |
1755 | || t.bitfield.baseindex); | |
1756 | ||
1757 | default: | |
1758 | abort (); | |
1759 | } | |
2cfe26b6 AM |
1760 | |
1761 | return 0; | |
40fb9820 L |
1762 | } |
1763 | ||
5c07affc L |
1764 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1765 | operand J for instruction template T. */ | |
1766 | ||
1767 | static INLINE int | |
d3ce72d0 | 1768 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1769 | { |
1770 | return !((i.types[j].bitfield.byte | |
1771 | && !t->operand_types[j].bitfield.byte) | |
1772 | || (i.types[j].bitfield.word | |
1773 | && !t->operand_types[j].bitfield.word) | |
1774 | || (i.types[j].bitfield.dword | |
1775 | && !t->operand_types[j].bitfield.dword) | |
1776 | || (i.types[j].bitfield.qword | |
1777 | && !t->operand_types[j].bitfield.qword)); | |
1778 | } | |
1779 | ||
1780 | /* Return 1 if there is no conflict in any size on operand J for | |
1781 | instruction template T. */ | |
1782 | ||
1783 | static INLINE int | |
d3ce72d0 | 1784 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1785 | { |
1786 | return (match_reg_size (t, j) | |
1787 | && !((i.types[j].bitfield.unspecified | |
af508cb9 | 1788 | && !i.broadcast |
5c07affc L |
1789 | && !t->operand_types[j].bitfield.unspecified) |
1790 | || (i.types[j].bitfield.fword | |
1791 | && !t->operand_types[j].bitfield.fword) | |
1792 | || (i.types[j].bitfield.tbyte | |
1793 | && !t->operand_types[j].bitfield.tbyte) | |
1794 | || (i.types[j].bitfield.xmmword | |
c0f3af97 L |
1795 | && !t->operand_types[j].bitfield.xmmword) |
1796 | || (i.types[j].bitfield.ymmword | |
43234a1e L |
1797 | && !t->operand_types[j].bitfield.ymmword) |
1798 | || (i.types[j].bitfield.zmmword | |
1799 | && !t->operand_types[j].bitfield.zmmword))); | |
5c07affc L |
1800 | } |
1801 | ||
1802 | /* Return 1 if there is no size conflict on any operands for | |
1803 | instruction template T. */ | |
1804 | ||
1805 | static INLINE int | |
d3ce72d0 | 1806 | operand_size_match (const insn_template *t) |
5c07affc L |
1807 | { |
1808 | unsigned int j; | |
1809 | int match = 1; | |
1810 | ||
1811 | /* Don't check jump instructions. */ | |
1812 | if (t->opcode_modifier.jump | |
1813 | || t->opcode_modifier.jumpbyte | |
1814 | || t->opcode_modifier.jumpdword | |
1815 | || t->opcode_modifier.jumpintersegment) | |
1816 | return match; | |
1817 | ||
1818 | /* Check memory and accumulator operand size. */ | |
1819 | for (j = 0; j < i.operands; j++) | |
1820 | { | |
1821 | if (t->operand_types[j].bitfield.anysize) | |
1822 | continue; | |
1823 | ||
1824 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1825 | { | |
1826 | match = 0; | |
1827 | break; | |
1828 | } | |
1829 | ||
1830 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1831 | { | |
1832 | match = 0; | |
1833 | break; | |
1834 | } | |
1835 | } | |
1836 | ||
891edac4 | 1837 | if (match) |
5c07affc | 1838 | return match; |
891edac4 L |
1839 | else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
1840 | { | |
1841 | mismatch: | |
86e026a4 | 1842 | i.error = operand_size_mismatch; |
891edac4 L |
1843 | return 0; |
1844 | } | |
5c07affc L |
1845 | |
1846 | /* Check reverse. */ | |
9c2799c2 | 1847 | gas_assert (i.operands == 2); |
5c07affc L |
1848 | |
1849 | match = 1; | |
1850 | for (j = 0; j < 2; j++) | |
1851 | { | |
1852 | if (t->operand_types[j].bitfield.acc | |
1853 | && !match_reg_size (t, j ? 0 : 1)) | |
891edac4 | 1854 | goto mismatch; |
5c07affc L |
1855 | |
1856 | if (i.types[j].bitfield.mem | |
1857 | && !match_mem_size (t, j ? 0 : 1)) | |
891edac4 | 1858 | goto mismatch; |
5c07affc L |
1859 | } |
1860 | ||
1861 | return match; | |
1862 | } | |
1863 | ||
c6fb90c8 | 1864 | static INLINE int |
40fb9820 L |
1865 | operand_type_match (i386_operand_type overlap, |
1866 | i386_operand_type given) | |
1867 | { | |
1868 | i386_operand_type temp = overlap; | |
1869 | ||
1870 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1871 | temp.bitfield.unspecified = 0; |
5c07affc L |
1872 | temp.bitfield.byte = 0; |
1873 | temp.bitfield.word = 0; | |
1874 | temp.bitfield.dword = 0; | |
1875 | temp.bitfield.fword = 0; | |
1876 | temp.bitfield.qword = 0; | |
1877 | temp.bitfield.tbyte = 0; | |
1878 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1879 | temp.bitfield.ymmword = 0; |
43234a1e | 1880 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 1881 | if (operand_type_all_zero (&temp)) |
891edac4 | 1882 | goto mismatch; |
40fb9820 | 1883 | |
891edac4 L |
1884 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
1885 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
1886 | return 1; | |
1887 | ||
1888 | mismatch: | |
a65babc9 | 1889 | i.error = operand_type_mismatch; |
891edac4 | 1890 | return 0; |
40fb9820 L |
1891 | } |
1892 | ||
7d5e4556 | 1893 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1894 | unless the expected operand type register overlap is null. |
1895 | Note that Acc in a template matches every size of reg. */ | |
1896 | ||
c6fb90c8 | 1897 | static INLINE int |
40fb9820 L |
1898 | operand_type_register_match (i386_operand_type m0, |
1899 | i386_operand_type g0, | |
1900 | i386_operand_type t0, | |
1901 | i386_operand_type m1, | |
1902 | i386_operand_type g1, | |
1903 | i386_operand_type t1) | |
1904 | { | |
1905 | if (!operand_type_check (g0, reg)) | |
1906 | return 1; | |
1907 | ||
1908 | if (!operand_type_check (g1, reg)) | |
1909 | return 1; | |
1910 | ||
1911 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1912 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1913 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1914 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1915 | return 1; | |
1916 | ||
1917 | if (m0.bitfield.acc) | |
1918 | { | |
1919 | t0.bitfield.reg8 = 1; | |
1920 | t0.bitfield.reg16 = 1; | |
1921 | t0.bitfield.reg32 = 1; | |
1922 | t0.bitfield.reg64 = 1; | |
1923 | } | |
1924 | ||
1925 | if (m1.bitfield.acc) | |
1926 | { | |
1927 | t1.bitfield.reg8 = 1; | |
1928 | t1.bitfield.reg16 = 1; | |
1929 | t1.bitfield.reg32 = 1; | |
1930 | t1.bitfield.reg64 = 1; | |
1931 | } | |
1932 | ||
891edac4 L |
1933 | if (!(t0.bitfield.reg8 & t1.bitfield.reg8) |
1934 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1935 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1936 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)) | |
1937 | return 1; | |
1938 | ||
a65babc9 | 1939 | i.error = register_type_mismatch; |
891edac4 L |
1940 | |
1941 | return 0; | |
40fb9820 L |
1942 | } |
1943 | ||
4c692bc7 JB |
1944 | static INLINE unsigned int |
1945 | register_number (const reg_entry *r) | |
1946 | { | |
1947 | unsigned int nr = r->reg_num; | |
1948 | ||
1949 | if (r->reg_flags & RegRex) | |
1950 | nr += 8; | |
1951 | ||
200cbe0f L |
1952 | if (r->reg_flags & RegVRex) |
1953 | nr += 16; | |
1954 | ||
4c692bc7 JB |
1955 | return nr; |
1956 | } | |
1957 | ||
252b5132 | 1958 | static INLINE unsigned int |
40fb9820 | 1959 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1960 | { |
43234a1e | 1961 | if (t.bitfield.disp8 || t.bitfield.vec_disp8) |
40fb9820 L |
1962 | return 1; |
1963 | else if (t.bitfield.disp16 | |
1964 | || t.bitfield.disp32 | |
1965 | || t.bitfield.disp32s) | |
1966 | return 2; | |
1967 | else | |
1968 | return 0; | |
252b5132 RH |
1969 | } |
1970 | ||
1971 | static INLINE int | |
65879393 | 1972 | fits_in_signed_byte (addressT num) |
252b5132 | 1973 | { |
65879393 | 1974 | return num + 0x80 <= 0xff; |
47926f60 | 1975 | } |
252b5132 RH |
1976 | |
1977 | static INLINE int | |
65879393 | 1978 | fits_in_unsigned_byte (addressT num) |
252b5132 | 1979 | { |
65879393 | 1980 | return num <= 0xff; |
47926f60 | 1981 | } |
252b5132 RH |
1982 | |
1983 | static INLINE int | |
65879393 | 1984 | fits_in_unsigned_word (addressT num) |
252b5132 | 1985 | { |
65879393 | 1986 | return num <= 0xffff; |
47926f60 | 1987 | } |
252b5132 RH |
1988 | |
1989 | static INLINE int | |
65879393 | 1990 | fits_in_signed_word (addressT num) |
252b5132 | 1991 | { |
65879393 | 1992 | return num + 0x8000 <= 0xffff; |
47926f60 | 1993 | } |
2a962e6d | 1994 | |
3e73aa7c | 1995 | static INLINE int |
65879393 | 1996 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1997 | { |
1998 | #ifndef BFD64 | |
1999 | return 1; | |
2000 | #else | |
65879393 | 2001 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2002 | #endif |
2003 | } /* fits_in_signed_long() */ | |
2a962e6d | 2004 | |
3e73aa7c | 2005 | static INLINE int |
65879393 | 2006 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2007 | { |
2008 | #ifndef BFD64 | |
2009 | return 1; | |
2010 | #else | |
65879393 | 2011 | return num <= 0xffffffff; |
3e73aa7c JH |
2012 | #endif |
2013 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2014 | |
43234a1e L |
2015 | static INLINE int |
2016 | fits_in_vec_disp8 (offsetT num) | |
2017 | { | |
2018 | int shift = i.memshift; | |
2019 | unsigned int mask; | |
2020 | ||
2021 | if (shift == -1) | |
2022 | abort (); | |
2023 | ||
2024 | mask = (1 << shift) - 1; | |
2025 | ||
2026 | /* Return 0 if NUM isn't properly aligned. */ | |
2027 | if ((num & mask)) | |
2028 | return 0; | |
2029 | ||
2030 | /* Check if NUM will fit in 8bit after shift. */ | |
2031 | return fits_in_signed_byte (num >> shift); | |
2032 | } | |
2033 | ||
a683cc34 SP |
2034 | static INLINE int |
2035 | fits_in_imm4 (offsetT num) | |
2036 | { | |
2037 | return (num & 0xf) == num; | |
2038 | } | |
2039 | ||
40fb9820 | 2040 | static i386_operand_type |
e3bb37b5 | 2041 | smallest_imm_type (offsetT num) |
252b5132 | 2042 | { |
40fb9820 | 2043 | i386_operand_type t; |
7ab9ffdd | 2044 | |
0dfbf9d7 | 2045 | operand_type_set (&t, 0); |
40fb9820 L |
2046 | t.bitfield.imm64 = 1; |
2047 | ||
2048 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2049 | { |
2050 | /* This code is disabled on the 486 because all the Imm1 forms | |
2051 | in the opcode table are slower on the i486. They're the | |
2052 | versions with the implicitly specified single-position | |
2053 | displacement, which has another syntax if you really want to | |
2054 | use that form. */ | |
40fb9820 L |
2055 | t.bitfield.imm1 = 1; |
2056 | t.bitfield.imm8 = 1; | |
2057 | t.bitfield.imm8s = 1; | |
2058 | t.bitfield.imm16 = 1; | |
2059 | t.bitfield.imm32 = 1; | |
2060 | t.bitfield.imm32s = 1; | |
2061 | } | |
2062 | else if (fits_in_signed_byte (num)) | |
2063 | { | |
2064 | t.bitfield.imm8 = 1; | |
2065 | t.bitfield.imm8s = 1; | |
2066 | t.bitfield.imm16 = 1; | |
2067 | t.bitfield.imm32 = 1; | |
2068 | t.bitfield.imm32s = 1; | |
2069 | } | |
2070 | else if (fits_in_unsigned_byte (num)) | |
2071 | { | |
2072 | t.bitfield.imm8 = 1; | |
2073 | t.bitfield.imm16 = 1; | |
2074 | t.bitfield.imm32 = 1; | |
2075 | t.bitfield.imm32s = 1; | |
2076 | } | |
2077 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2078 | { | |
2079 | t.bitfield.imm16 = 1; | |
2080 | t.bitfield.imm32 = 1; | |
2081 | t.bitfield.imm32s = 1; | |
2082 | } | |
2083 | else if (fits_in_signed_long (num)) | |
2084 | { | |
2085 | t.bitfield.imm32 = 1; | |
2086 | t.bitfield.imm32s = 1; | |
2087 | } | |
2088 | else if (fits_in_unsigned_long (num)) | |
2089 | t.bitfield.imm32 = 1; | |
2090 | ||
2091 | return t; | |
47926f60 | 2092 | } |
252b5132 | 2093 | |
847f7ad4 | 2094 | static offsetT |
e3bb37b5 | 2095 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2096 | { |
508866be | 2097 | addressT mask; |
ba2adb93 | 2098 | |
847f7ad4 AM |
2099 | switch (size) |
2100 | { | |
508866be L |
2101 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2102 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2103 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2104 | #ifdef BFD64 |
2105 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2106 | #endif | |
47926f60 | 2107 | default: abort (); |
847f7ad4 AM |
2108 | } |
2109 | ||
9de868bf L |
2110 | #ifdef BFD64 |
2111 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2112 | if (flag_code != CODE_64BIT | |
2113 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2114 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2115 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2116 | #endif |
ba2adb93 | 2117 | |
47926f60 | 2118 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2119 | { |
2120 | char buf1[40], buf2[40]; | |
2121 | ||
2122 | sprint_value (buf1, val); | |
2123 | sprint_value (buf2, val & mask); | |
2124 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2125 | } | |
2126 | return val & mask; | |
2127 | } | |
2128 | ||
c32fa91d L |
2129 | enum PREFIX_GROUP |
2130 | { | |
2131 | PREFIX_EXIST = 0, | |
2132 | PREFIX_LOCK, | |
2133 | PREFIX_REP, | |
2134 | PREFIX_OTHER | |
2135 | }; | |
2136 | ||
2137 | /* Returns | |
2138 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2139 | same class already exists. | |
2140 | b. PREFIX_LOCK if lock prefix is added. | |
2141 | c. PREFIX_REP if rep/repne prefix is added. | |
2142 | d. PREFIX_OTHER if other prefix is added. | |
2143 | */ | |
2144 | ||
2145 | static enum PREFIX_GROUP | |
e3bb37b5 | 2146 | add_prefix (unsigned int prefix) |
252b5132 | 2147 | { |
c32fa91d | 2148 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2149 | unsigned int q; |
252b5132 | 2150 | |
29b0f896 AM |
2151 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2152 | && flag_code == CODE_64BIT) | |
b1905489 | 2153 | { |
161a04f6 L |
2154 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
2155 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
2156 | && (prefix & (REX_R | REX_X | REX_B)))) | |
c32fa91d | 2157 | ret = PREFIX_EXIST; |
b1905489 JB |
2158 | q = REX_PREFIX; |
2159 | } | |
3e73aa7c | 2160 | else |
b1905489 JB |
2161 | { |
2162 | switch (prefix) | |
2163 | { | |
2164 | default: | |
2165 | abort (); | |
2166 | ||
2167 | case CS_PREFIX_OPCODE: | |
2168 | case DS_PREFIX_OPCODE: | |
2169 | case ES_PREFIX_OPCODE: | |
2170 | case FS_PREFIX_OPCODE: | |
2171 | case GS_PREFIX_OPCODE: | |
2172 | case SS_PREFIX_OPCODE: | |
2173 | q = SEG_PREFIX; | |
2174 | break; | |
2175 | ||
2176 | case REPNE_PREFIX_OPCODE: | |
2177 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2178 | q = REP_PREFIX; |
2179 | ret = PREFIX_REP; | |
2180 | break; | |
2181 | ||
b1905489 | 2182 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2183 | q = LOCK_PREFIX; |
2184 | ret = PREFIX_LOCK; | |
b1905489 JB |
2185 | break; |
2186 | ||
2187 | case FWAIT_OPCODE: | |
2188 | q = WAIT_PREFIX; | |
2189 | break; | |
2190 | ||
2191 | case ADDR_PREFIX_OPCODE: | |
2192 | q = ADDR_PREFIX; | |
2193 | break; | |
2194 | ||
2195 | case DATA_PREFIX_OPCODE: | |
2196 | q = DATA_PREFIX; | |
2197 | break; | |
2198 | } | |
2199 | if (i.prefix[q] != 0) | |
c32fa91d | 2200 | ret = PREFIX_EXIST; |
b1905489 | 2201 | } |
252b5132 | 2202 | |
b1905489 | 2203 | if (ret) |
252b5132 | 2204 | { |
b1905489 JB |
2205 | if (!i.prefix[q]) |
2206 | ++i.prefixes; | |
2207 | i.prefix[q] |= prefix; | |
252b5132 | 2208 | } |
b1905489 JB |
2209 | else |
2210 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2211 | |
252b5132 RH |
2212 | return ret; |
2213 | } | |
2214 | ||
2215 | static void | |
78f12dd3 | 2216 | update_code_flag (int value, int check) |
eecb386c | 2217 | { |
78f12dd3 L |
2218 | PRINTF_LIKE ((*as_error)); |
2219 | ||
1e9cc1c2 | 2220 | flag_code = (enum flag_code) value; |
40fb9820 L |
2221 | if (flag_code == CODE_64BIT) |
2222 | { | |
2223 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2224 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2225 | } |
2226 | else | |
2227 | { | |
2228 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2229 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2230 | } |
2231 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2232 | { |
78f12dd3 L |
2233 | if (check) |
2234 | as_error = as_fatal; | |
2235 | else | |
2236 | as_error = as_bad; | |
2237 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2238 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2239 | } |
40fb9820 | 2240 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2241 | { |
78f12dd3 L |
2242 | if (check) |
2243 | as_error = as_fatal; | |
2244 | else | |
2245 | as_error = as_bad; | |
2246 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2247 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2248 | } |
eecb386c AM |
2249 | stackop_size = '\0'; |
2250 | } | |
2251 | ||
78f12dd3 L |
2252 | static void |
2253 | set_code_flag (int value) | |
2254 | { | |
2255 | update_code_flag (value, 0); | |
2256 | } | |
2257 | ||
eecb386c | 2258 | static void |
e3bb37b5 | 2259 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2260 | { |
1e9cc1c2 | 2261 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2262 | if (flag_code != CODE_16BIT) |
2263 | abort (); | |
2264 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2265 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2266 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2267 | } |
2268 | ||
2269 | static void | |
e3bb37b5 | 2270 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2271 | { |
2272 | /* Find out if register prefixing is specified. */ | |
2273 | int ask_naked_reg = 0; | |
2274 | ||
2275 | SKIP_WHITESPACE (); | |
29b0f896 | 2276 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2277 | { |
d02603dc NC |
2278 | char *string; |
2279 | int e = get_symbol_name (&string); | |
252b5132 | 2280 | |
47926f60 | 2281 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2282 | ask_naked_reg = 1; |
47926f60 | 2283 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2284 | ask_naked_reg = -1; |
2285 | else | |
d0b47220 | 2286 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2287 | (void) restore_line_pointer (e); |
252b5132 RH |
2288 | } |
2289 | demand_empty_rest_of_line (); | |
c3332e24 | 2290 | |
252b5132 RH |
2291 | intel_syntax = syntax_flag; |
2292 | ||
2293 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2294 | allow_naked_reg = (intel_syntax |
2295 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2296 | else |
2297 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2298 | |
ee86248c | 2299 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2300 | |
e4a3b5a4 | 2301 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2302 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2303 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2304 | } |
2305 | ||
1efbbeb4 L |
2306 | static void |
2307 | set_intel_mnemonic (int mnemonic_flag) | |
2308 | { | |
e1d4d893 | 2309 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2310 | } |
2311 | ||
db51cc60 L |
2312 | static void |
2313 | set_allow_index_reg (int flag) | |
2314 | { | |
2315 | allow_index_reg = flag; | |
2316 | } | |
2317 | ||
cb19c032 | 2318 | static void |
7bab8ab5 | 2319 | set_check (int what) |
cb19c032 | 2320 | { |
7bab8ab5 JB |
2321 | enum check_kind *kind; |
2322 | const char *str; | |
2323 | ||
2324 | if (what) | |
2325 | { | |
2326 | kind = &operand_check; | |
2327 | str = "operand"; | |
2328 | } | |
2329 | else | |
2330 | { | |
2331 | kind = &sse_check; | |
2332 | str = "sse"; | |
2333 | } | |
2334 | ||
cb19c032 L |
2335 | SKIP_WHITESPACE (); |
2336 | ||
2337 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2338 | { | |
d02603dc NC |
2339 | char *string; |
2340 | int e = get_symbol_name (&string); | |
cb19c032 L |
2341 | |
2342 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2343 | *kind = check_none; |
cb19c032 | 2344 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2345 | *kind = check_warning; |
cb19c032 | 2346 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2347 | *kind = check_error; |
cb19c032 | 2348 | else |
7bab8ab5 | 2349 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2350 | (void) restore_line_pointer (e); |
cb19c032 L |
2351 | } |
2352 | else | |
7bab8ab5 | 2353 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2354 | |
2355 | demand_empty_rest_of_line (); | |
2356 | } | |
2357 | ||
8a9036a4 L |
2358 | static void |
2359 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2360 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2361 | { |
2362 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2363 | static const char *arch; | |
2364 | ||
2365 | /* Intel LIOM is only supported on ELF. */ | |
2366 | if (!IS_ELF) | |
2367 | return; | |
2368 | ||
2369 | if (!arch) | |
2370 | { | |
2371 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2372 | use default_arch. */ | |
2373 | arch = cpu_arch_name; | |
2374 | if (!arch) | |
2375 | arch = default_arch; | |
2376 | } | |
2377 | ||
81486035 L |
2378 | /* If we are targeting Intel MCU, we must enable it. */ |
2379 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2380 | || new_flag.bitfield.cpuiamcu) | |
2381 | return; | |
2382 | ||
3632d14b | 2383 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2384 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2385 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2386 | return; |
76ba9986 | 2387 | |
7a9068fe L |
2388 | /* If we are targeting Intel K1OM, we must enable it. */ |
2389 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2390 | || new_flag.bitfield.cpuk1om) | |
2391 | return; | |
2392 | ||
8a9036a4 L |
2393 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2394 | #endif | |
2395 | } | |
2396 | ||
e413e4e9 | 2397 | static void |
e3bb37b5 | 2398 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2399 | { |
47926f60 | 2400 | SKIP_WHITESPACE (); |
e413e4e9 | 2401 | |
29b0f896 | 2402 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2403 | { |
d02603dc NC |
2404 | char *string; |
2405 | int e = get_symbol_name (&string); | |
91d6fa6a | 2406 | unsigned int j; |
40fb9820 | 2407 | i386_cpu_flags flags; |
e413e4e9 | 2408 | |
91d6fa6a | 2409 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2410 | { |
91d6fa6a | 2411 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2412 | { |
91d6fa6a | 2413 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2414 | |
5c6af06e JB |
2415 | if (*string != '.') |
2416 | { | |
91d6fa6a | 2417 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2418 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2419 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2420 | if (flag_code == CODE_64BIT) |
2421 | { | |
2422 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2423 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2424 | } | |
2425 | else | |
2426 | { | |
2427 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2428 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2429 | } | |
91d6fa6a NC |
2430 | cpu_arch_isa = cpu_arch[j].type; |
2431 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2432 | if (!cpu_arch_tune_set) |
2433 | { | |
2434 | cpu_arch_tune = cpu_arch_isa; | |
2435 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2436 | } | |
5c6af06e JB |
2437 | break; |
2438 | } | |
40fb9820 | 2439 | |
293f5f65 L |
2440 | flags = cpu_flags_or (cpu_arch_flags, |
2441 | cpu_arch[j].flags); | |
81486035 | 2442 | |
5b64d091 | 2443 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2444 | { |
6305a203 L |
2445 | if (cpu_sub_arch_name) |
2446 | { | |
2447 | char *name = cpu_sub_arch_name; | |
2448 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2449 | cpu_arch[j].name, |
1bf57e9f | 2450 | (const char *) NULL); |
6305a203 L |
2451 | free (name); |
2452 | } | |
2453 | else | |
91d6fa6a | 2454 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2455 | cpu_arch_flags = flags; |
a586129e | 2456 | cpu_arch_isa_flags = flags; |
5c6af06e | 2457 | } |
d02603dc | 2458 | (void) restore_line_pointer (e); |
5c6af06e JB |
2459 | demand_empty_rest_of_line (); |
2460 | return; | |
e413e4e9 AM |
2461 | } |
2462 | } | |
293f5f65 L |
2463 | |
2464 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2465 | { | |
33eaf5de | 2466 | /* Disable an ISA extension. */ |
293f5f65 L |
2467 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2468 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2469 | { | |
2470 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2471 | cpu_noarch[j].flags); | |
2472 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2473 | { | |
2474 | if (cpu_sub_arch_name) | |
2475 | { | |
2476 | char *name = cpu_sub_arch_name; | |
2477 | cpu_sub_arch_name = concat (name, string, | |
2478 | (const char *) NULL); | |
2479 | free (name); | |
2480 | } | |
2481 | else | |
2482 | cpu_sub_arch_name = xstrdup (string); | |
2483 | cpu_arch_flags = flags; | |
2484 | cpu_arch_isa_flags = flags; | |
2485 | } | |
2486 | (void) restore_line_pointer (e); | |
2487 | demand_empty_rest_of_line (); | |
2488 | return; | |
2489 | } | |
2490 | ||
2491 | j = ARRAY_SIZE (cpu_arch); | |
2492 | } | |
2493 | ||
91d6fa6a | 2494 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2495 | as_bad (_("no such architecture: `%s'"), string); |
2496 | ||
2497 | *input_line_pointer = e; | |
2498 | } | |
2499 | else | |
2500 | as_bad (_("missing cpu architecture")); | |
2501 | ||
fddf5b5b AM |
2502 | no_cond_jump_promotion = 0; |
2503 | if (*input_line_pointer == ',' | |
29b0f896 | 2504 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2505 | { |
d02603dc NC |
2506 | char *string; |
2507 | char e; | |
2508 | ||
2509 | ++input_line_pointer; | |
2510 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2511 | |
2512 | if (strcmp (string, "nojumps") == 0) | |
2513 | no_cond_jump_promotion = 1; | |
2514 | else if (strcmp (string, "jumps") == 0) | |
2515 | ; | |
2516 | else | |
2517 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2518 | ||
d02603dc | 2519 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2520 | } |
2521 | ||
e413e4e9 AM |
2522 | demand_empty_rest_of_line (); |
2523 | } | |
2524 | ||
8a9036a4 L |
2525 | enum bfd_architecture |
2526 | i386_arch (void) | |
2527 | { | |
3632d14b | 2528 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2529 | { |
2530 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2531 | || flag_code != CODE_64BIT) | |
2532 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2533 | return bfd_arch_l1om; | |
2534 | } | |
7a9068fe L |
2535 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2536 | { | |
2537 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2538 | || flag_code != CODE_64BIT) | |
2539 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2540 | return bfd_arch_k1om; | |
2541 | } | |
81486035 L |
2542 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2543 | { | |
2544 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2545 | || flag_code == CODE_64BIT) | |
2546 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2547 | return bfd_arch_iamcu; | |
2548 | } | |
8a9036a4 L |
2549 | else |
2550 | return bfd_arch_i386; | |
2551 | } | |
2552 | ||
b9d79e03 | 2553 | unsigned long |
7016a5d5 | 2554 | i386_mach (void) |
b9d79e03 | 2555 | { |
351f65ca | 2556 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2557 | { |
3632d14b | 2558 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2559 | { |
351f65ca L |
2560 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2561 | || default_arch[6] != '\0') | |
8a9036a4 L |
2562 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2563 | return bfd_mach_l1om; | |
2564 | } | |
7a9068fe L |
2565 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2566 | { | |
2567 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2568 | || default_arch[6] != '\0') | |
2569 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2570 | return bfd_mach_k1om; | |
2571 | } | |
351f65ca | 2572 | else if (default_arch[6] == '\0') |
8a9036a4 | 2573 | return bfd_mach_x86_64; |
351f65ca L |
2574 | else |
2575 | return bfd_mach_x64_32; | |
8a9036a4 | 2576 | } |
5197d474 L |
2577 | else if (!strcmp (default_arch, "i386") |
2578 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2579 | { |
2580 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2581 | { | |
2582 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2583 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2584 | return bfd_mach_i386_iamcu; | |
2585 | } | |
2586 | else | |
2587 | return bfd_mach_i386_i386; | |
2588 | } | |
b9d79e03 | 2589 | else |
2b5d6a91 | 2590 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2591 | } |
b9d79e03 | 2592 | \f |
252b5132 | 2593 | void |
7016a5d5 | 2594 | md_begin (void) |
252b5132 RH |
2595 | { |
2596 | const char *hash_err; | |
2597 | ||
47926f60 | 2598 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2599 | op_hash = hash_new (); |
2600 | ||
2601 | { | |
d3ce72d0 | 2602 | const insn_template *optab; |
29b0f896 | 2603 | templates *core_optab; |
252b5132 | 2604 | |
47926f60 KH |
2605 | /* Setup for loop. */ |
2606 | optab = i386_optab; | |
add39d23 | 2607 | core_optab = XNEW (templates); |
252b5132 RH |
2608 | core_optab->start = optab; |
2609 | ||
2610 | while (1) | |
2611 | { | |
2612 | ++optab; | |
2613 | if (optab->name == NULL | |
2614 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2615 | { | |
2616 | /* different name --> ship out current template list; | |
47926f60 | 2617 | add to hash table; & begin anew. */ |
252b5132 RH |
2618 | core_optab->end = optab; |
2619 | hash_err = hash_insert (op_hash, | |
2620 | (optab - 1)->name, | |
5a49b8ac | 2621 | (void *) core_optab); |
252b5132 RH |
2622 | if (hash_err) |
2623 | { | |
b37df7c4 | 2624 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2625 | (optab - 1)->name, |
2626 | hash_err); | |
2627 | } | |
2628 | if (optab->name == NULL) | |
2629 | break; | |
add39d23 | 2630 | core_optab = XNEW (templates); |
252b5132 RH |
2631 | core_optab->start = optab; |
2632 | } | |
2633 | } | |
2634 | } | |
2635 | ||
47926f60 | 2636 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2637 | reg_hash = hash_new (); |
2638 | { | |
29b0f896 | 2639 | const reg_entry *regtab; |
c3fe08fa | 2640 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2641 | |
c3fe08fa | 2642 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2643 | { |
5a49b8ac | 2644 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2645 | if (hash_err) |
b37df7c4 | 2646 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2647 | regtab->reg_name, |
2648 | hash_err); | |
252b5132 RH |
2649 | } |
2650 | } | |
2651 | ||
47926f60 | 2652 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2653 | { |
29b0f896 AM |
2654 | int c; |
2655 | char *p; | |
252b5132 RH |
2656 | |
2657 | for (c = 0; c < 256; c++) | |
2658 | { | |
3882b010 | 2659 | if (ISDIGIT (c)) |
252b5132 RH |
2660 | { |
2661 | digit_chars[c] = c; | |
2662 | mnemonic_chars[c] = c; | |
2663 | register_chars[c] = c; | |
2664 | operand_chars[c] = c; | |
2665 | } | |
3882b010 | 2666 | else if (ISLOWER (c)) |
252b5132 RH |
2667 | { |
2668 | mnemonic_chars[c] = c; | |
2669 | register_chars[c] = c; | |
2670 | operand_chars[c] = c; | |
2671 | } | |
3882b010 | 2672 | else if (ISUPPER (c)) |
252b5132 | 2673 | { |
3882b010 | 2674 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2675 | register_chars[c] = mnemonic_chars[c]; |
2676 | operand_chars[c] = c; | |
2677 | } | |
43234a1e L |
2678 | else if (c == '{' || c == '}') |
2679 | operand_chars[c] = c; | |
252b5132 | 2680 | |
3882b010 | 2681 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2682 | identifier_chars[c] = c; |
2683 | else if (c >= 128) | |
2684 | { | |
2685 | identifier_chars[c] = c; | |
2686 | operand_chars[c] = c; | |
2687 | } | |
2688 | } | |
2689 | ||
2690 | #ifdef LEX_AT | |
2691 | identifier_chars['@'] = '@'; | |
32137342 NC |
2692 | #endif |
2693 | #ifdef LEX_QM | |
2694 | identifier_chars['?'] = '?'; | |
2695 | operand_chars['?'] = '?'; | |
252b5132 | 2696 | #endif |
252b5132 | 2697 | digit_chars['-'] = '-'; |
c0f3af97 | 2698 | mnemonic_chars['_'] = '_'; |
791fe849 | 2699 | mnemonic_chars['-'] = '-'; |
0003779b | 2700 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2701 | identifier_chars['_'] = '_'; |
2702 | identifier_chars['.'] = '.'; | |
2703 | ||
2704 | for (p = operand_special_chars; *p != '\0'; p++) | |
2705 | operand_chars[(unsigned char) *p] = *p; | |
2706 | } | |
2707 | ||
a4447b93 RH |
2708 | if (flag_code == CODE_64BIT) |
2709 | { | |
ca19b261 KT |
2710 | #if defined (OBJ_COFF) && defined (TE_PE) |
2711 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2712 | ? 32 : 16); | |
2713 | #else | |
a4447b93 | 2714 | x86_dwarf2_return_column = 16; |
ca19b261 | 2715 | #endif |
61ff971f | 2716 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2717 | } |
2718 | else | |
2719 | { | |
2720 | x86_dwarf2_return_column = 8; | |
2721 | x86_cie_data_alignment = -4; | |
2722 | } | |
252b5132 RH |
2723 | } |
2724 | ||
2725 | void | |
e3bb37b5 | 2726 | i386_print_statistics (FILE *file) |
252b5132 RH |
2727 | { |
2728 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2729 | hash_print_statistics (file, "i386 register", reg_hash); | |
2730 | } | |
2731 | \f | |
252b5132 RH |
2732 | #ifdef DEBUG386 |
2733 | ||
ce8a8b2f | 2734 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2735 | static void pte (insn_template *); |
40fb9820 | 2736 | static void pt (i386_operand_type); |
e3bb37b5 L |
2737 | static void pe (expressionS *); |
2738 | static void ps (symbolS *); | |
252b5132 RH |
2739 | |
2740 | static void | |
e3bb37b5 | 2741 | pi (char *line, i386_insn *x) |
252b5132 | 2742 | { |
09137c09 | 2743 | unsigned int j; |
252b5132 RH |
2744 | |
2745 | fprintf (stdout, "%s: template ", line); | |
2746 | pte (&x->tm); | |
09f131f2 JH |
2747 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2748 | x->base_reg ? x->base_reg->reg_name : "none", | |
2749 | x->index_reg ? x->index_reg->reg_name : "none", | |
2750 | x->log2_scale_factor); | |
2751 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2752 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2753 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2754 | x->sib.base, x->sib.index, x->sib.scale); | |
2755 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2756 | (x->rex & REX_W) != 0, |
2757 | (x->rex & REX_R) != 0, | |
2758 | (x->rex & REX_X) != 0, | |
2759 | (x->rex & REX_B) != 0); | |
09137c09 | 2760 | for (j = 0; j < x->operands; j++) |
252b5132 | 2761 | { |
09137c09 SP |
2762 | fprintf (stdout, " #%d: ", j + 1); |
2763 | pt (x->types[j]); | |
252b5132 | 2764 | fprintf (stdout, "\n"); |
09137c09 SP |
2765 | if (x->types[j].bitfield.reg8 |
2766 | || x->types[j].bitfield.reg16 | |
2767 | || x->types[j].bitfield.reg32 | |
2768 | || x->types[j].bitfield.reg64 | |
2769 | || x->types[j].bitfield.regmmx | |
2770 | || x->types[j].bitfield.regxmm | |
2771 | || x->types[j].bitfield.regymm | |
43234a1e | 2772 | || x->types[j].bitfield.regzmm |
09137c09 SP |
2773 | || x->types[j].bitfield.sreg2 |
2774 | || x->types[j].bitfield.sreg3 | |
2775 | || x->types[j].bitfield.control | |
2776 | || x->types[j].bitfield.debug | |
2777 | || x->types[j].bitfield.test) | |
2778 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2779 | if (operand_type_check (x->types[j], imm)) | |
2780 | pe (x->op[j].imms); | |
2781 | if (operand_type_check (x->types[j], disp)) | |
2782 | pe (x->op[j].disps); | |
252b5132 RH |
2783 | } |
2784 | } | |
2785 | ||
2786 | static void | |
d3ce72d0 | 2787 | pte (insn_template *t) |
252b5132 | 2788 | { |
09137c09 | 2789 | unsigned int j; |
252b5132 | 2790 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2791 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2792 | if (t->extension_opcode != None) |
2793 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2794 | if (t->opcode_modifier.d) |
252b5132 | 2795 | fprintf (stdout, "D"); |
40fb9820 | 2796 | if (t->opcode_modifier.w) |
252b5132 RH |
2797 | fprintf (stdout, "W"); |
2798 | fprintf (stdout, "\n"); | |
09137c09 | 2799 | for (j = 0; j < t->operands; j++) |
252b5132 | 2800 | { |
09137c09 SP |
2801 | fprintf (stdout, " #%d type ", j + 1); |
2802 | pt (t->operand_types[j]); | |
252b5132 RH |
2803 | fprintf (stdout, "\n"); |
2804 | } | |
2805 | } | |
2806 | ||
2807 | static void | |
e3bb37b5 | 2808 | pe (expressionS *e) |
252b5132 | 2809 | { |
24eab124 | 2810 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2811 | fprintf (stdout, " add_number %ld (%lx)\n", |
2812 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2813 | if (e->X_add_symbol) |
2814 | { | |
2815 | fprintf (stdout, " add_symbol "); | |
2816 | ps (e->X_add_symbol); | |
2817 | fprintf (stdout, "\n"); | |
2818 | } | |
2819 | if (e->X_op_symbol) | |
2820 | { | |
2821 | fprintf (stdout, " op_symbol "); | |
2822 | ps (e->X_op_symbol); | |
2823 | fprintf (stdout, "\n"); | |
2824 | } | |
2825 | } | |
2826 | ||
2827 | static void | |
e3bb37b5 | 2828 | ps (symbolS *s) |
252b5132 RH |
2829 | { |
2830 | fprintf (stdout, "%s type %s%s", | |
2831 | S_GET_NAME (s), | |
2832 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2833 | segment_name (S_GET_SEGMENT (s))); | |
2834 | } | |
2835 | ||
7b81dfbb | 2836 | static struct type_name |
252b5132 | 2837 | { |
40fb9820 L |
2838 | i386_operand_type mask; |
2839 | const char *name; | |
252b5132 | 2840 | } |
7b81dfbb | 2841 | const type_names[] = |
252b5132 | 2842 | { |
40fb9820 L |
2843 | { OPERAND_TYPE_REG8, "r8" }, |
2844 | { OPERAND_TYPE_REG16, "r16" }, | |
2845 | { OPERAND_TYPE_REG32, "r32" }, | |
2846 | { OPERAND_TYPE_REG64, "r64" }, | |
2847 | { OPERAND_TYPE_IMM8, "i8" }, | |
2848 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2849 | { OPERAND_TYPE_IMM16, "i16" }, | |
2850 | { OPERAND_TYPE_IMM32, "i32" }, | |
2851 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2852 | { OPERAND_TYPE_IMM64, "i64" }, | |
2853 | { OPERAND_TYPE_IMM1, "i1" }, | |
2854 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2855 | { OPERAND_TYPE_DISP8, "d8" }, | |
2856 | { OPERAND_TYPE_DISP16, "d16" }, | |
2857 | { OPERAND_TYPE_DISP32, "d32" }, | |
2858 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2859 | { OPERAND_TYPE_DISP64, "d64" }, | |
43234a1e | 2860 | { OPERAND_TYPE_VEC_DISP8, "Vector d8" }, |
40fb9820 L |
2861 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, |
2862 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2863 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2864 | { OPERAND_TYPE_TEST, "test reg" }, | |
2865 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2866 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2867 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2868 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2869 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2870 | { OPERAND_TYPE_ACC, "Acc" }, | |
2871 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2872 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2873 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 2874 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
2875 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
2876 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 2877 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
2878 | }; |
2879 | ||
2880 | static void | |
40fb9820 | 2881 | pt (i386_operand_type t) |
252b5132 | 2882 | { |
40fb9820 | 2883 | unsigned int j; |
c6fb90c8 | 2884 | i386_operand_type a; |
252b5132 | 2885 | |
40fb9820 | 2886 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2887 | { |
2888 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 2889 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
2890 | fprintf (stdout, "%s, ", type_names[j].name); |
2891 | } | |
252b5132 RH |
2892 | fflush (stdout); |
2893 | } | |
2894 | ||
2895 | #endif /* DEBUG386 */ | |
2896 | \f | |
252b5132 | 2897 | static bfd_reloc_code_real_type |
3956db08 | 2898 | reloc (unsigned int size, |
64e74474 AM |
2899 | int pcrel, |
2900 | int sign, | |
2901 | bfd_reloc_code_real_type other) | |
252b5132 | 2902 | { |
47926f60 | 2903 | if (other != NO_RELOC) |
3956db08 | 2904 | { |
91d6fa6a | 2905 | reloc_howto_type *rel; |
3956db08 JB |
2906 | |
2907 | if (size == 8) | |
2908 | switch (other) | |
2909 | { | |
64e74474 AM |
2910 | case BFD_RELOC_X86_64_GOT32: |
2911 | return BFD_RELOC_X86_64_GOT64; | |
2912 | break; | |
553d1284 L |
2913 | case BFD_RELOC_X86_64_GOTPLT64: |
2914 | return BFD_RELOC_X86_64_GOTPLT64; | |
2915 | break; | |
64e74474 AM |
2916 | case BFD_RELOC_X86_64_PLTOFF64: |
2917 | return BFD_RELOC_X86_64_PLTOFF64; | |
2918 | break; | |
2919 | case BFD_RELOC_X86_64_GOTPC32: | |
2920 | other = BFD_RELOC_X86_64_GOTPC64; | |
2921 | break; | |
2922 | case BFD_RELOC_X86_64_GOTPCREL: | |
2923 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2924 | break; | |
2925 | case BFD_RELOC_X86_64_TPOFF32: | |
2926 | other = BFD_RELOC_X86_64_TPOFF64; | |
2927 | break; | |
2928 | case BFD_RELOC_X86_64_DTPOFF32: | |
2929 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2930 | break; | |
2931 | default: | |
2932 | break; | |
3956db08 | 2933 | } |
e05278af | 2934 | |
8ce3d284 | 2935 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
2936 | if (other == BFD_RELOC_SIZE32) |
2937 | { | |
2938 | if (size == 8) | |
1ab668bf | 2939 | other = BFD_RELOC_SIZE64; |
8fd4256d | 2940 | if (pcrel) |
1ab668bf AM |
2941 | { |
2942 | as_bad (_("there are no pc-relative size relocations")); | |
2943 | return NO_RELOC; | |
2944 | } | |
8fd4256d | 2945 | } |
8ce3d284 | 2946 | #endif |
8fd4256d | 2947 | |
e05278af | 2948 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 2949 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
2950 | sign = -1; |
2951 | ||
91d6fa6a NC |
2952 | rel = bfd_reloc_type_lookup (stdoutput, other); |
2953 | if (!rel) | |
3956db08 | 2954 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 2955 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 2956 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 2957 | bfd_get_reloc_size (rel), |
3956db08 | 2958 | size); |
91d6fa6a | 2959 | else if (pcrel && !rel->pc_relative) |
3956db08 | 2960 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 2961 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 2962 | && !sign) |
91d6fa6a | 2963 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 2964 | && sign > 0)) |
3956db08 JB |
2965 | as_bad (_("relocated field and relocation type differ in signedness")); |
2966 | else | |
2967 | return other; | |
2968 | return NO_RELOC; | |
2969 | } | |
252b5132 RH |
2970 | |
2971 | if (pcrel) | |
2972 | { | |
3e73aa7c | 2973 | if (!sign) |
3956db08 | 2974 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2975 | switch (size) |
2976 | { | |
2977 | case 1: return BFD_RELOC_8_PCREL; | |
2978 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 2979 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 2980 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2981 | } |
3956db08 | 2982 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2983 | } |
2984 | else | |
2985 | { | |
3956db08 | 2986 | if (sign > 0) |
e5cb08ac | 2987 | switch (size) |
3e73aa7c JH |
2988 | { |
2989 | case 4: return BFD_RELOC_X86_64_32S; | |
2990 | } | |
2991 | else | |
2992 | switch (size) | |
2993 | { | |
2994 | case 1: return BFD_RELOC_8; | |
2995 | case 2: return BFD_RELOC_16; | |
2996 | case 4: return BFD_RELOC_32; | |
2997 | case 8: return BFD_RELOC_64; | |
2998 | } | |
3956db08 JB |
2999 | as_bad (_("cannot do %s %u byte relocation"), |
3000 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3001 | } |
3002 | ||
0cc9e1d3 | 3003 | return NO_RELOC; |
252b5132 RH |
3004 | } |
3005 | ||
47926f60 KH |
3006 | /* Here we decide which fixups can be adjusted to make them relative to |
3007 | the beginning of the section instead of the symbol. Basically we need | |
3008 | to make sure that the dynamic relocations are done correctly, so in | |
3009 | some cases we force the original symbol to be used. */ | |
3010 | ||
252b5132 | 3011 | int |
e3bb37b5 | 3012 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3013 | { |
6d249963 | 3014 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3015 | if (!IS_ELF) |
31312f95 AM |
3016 | return 1; |
3017 | ||
a161fe53 AM |
3018 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3019 | mode. */ | |
3020 | if (use_rela_relocations | |
3021 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3022 | && fixP->fx_pcrel) | |
252b5132 | 3023 | return 0; |
31312f95 | 3024 | |
8d01d9a9 AJ |
3025 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3026 | and changed later by validate_fix. */ | |
3027 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3028 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3029 | return 0; | |
3030 | ||
8fd4256d L |
3031 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3032 | for size relocations. */ | |
3033 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3034 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3035 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3036 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3037 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3038 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3039 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3040 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3041 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3042 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3043 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3044 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3045 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3046 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3047 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3048 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3049 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3050 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3051 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3052 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3053 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3054 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3055 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3056 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3057 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3058 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3059 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3060 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3061 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3062 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3063 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3064 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3065 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3066 | return 0; | |
31312f95 | 3067 | #endif |
252b5132 RH |
3068 | return 1; |
3069 | } | |
252b5132 | 3070 | |
b4cac588 | 3071 | static int |
e3bb37b5 | 3072 | intel_float_operand (const char *mnemonic) |
252b5132 | 3073 | { |
9306ca4a JB |
3074 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3075 | operands, hence the code here is free to improperly handle opcodes that | |
3076 | have no operands (for better performance and smaller code). */ | |
3077 | ||
3078 | if (mnemonic[0] != 'f') | |
3079 | return 0; /* non-math */ | |
3080 | ||
3081 | switch (mnemonic[1]) | |
3082 | { | |
3083 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3084 | the fs segment override prefix not currently handled because no | |
3085 | call path can make opcodes without operands get here */ | |
3086 | case 'i': | |
3087 | return 2 /* integer op */; | |
3088 | case 'l': | |
3089 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3090 | return 3; /* fldcw/fldenv */ | |
3091 | break; | |
3092 | case 'n': | |
3093 | if (mnemonic[2] != 'o' /* fnop */) | |
3094 | return 3; /* non-waiting control op */ | |
3095 | break; | |
3096 | case 'r': | |
3097 | if (mnemonic[2] == 's') | |
3098 | return 3; /* frstor/frstpm */ | |
3099 | break; | |
3100 | case 's': | |
3101 | if (mnemonic[2] == 'a') | |
3102 | return 3; /* fsave */ | |
3103 | if (mnemonic[2] == 't') | |
3104 | { | |
3105 | switch (mnemonic[3]) | |
3106 | { | |
3107 | case 'c': /* fstcw */ | |
3108 | case 'd': /* fstdw */ | |
3109 | case 'e': /* fstenv */ | |
3110 | case 's': /* fsts[gw] */ | |
3111 | return 3; | |
3112 | } | |
3113 | } | |
3114 | break; | |
3115 | case 'x': | |
3116 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3117 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3118 | break; | |
3119 | } | |
252b5132 | 3120 | |
9306ca4a | 3121 | return 1; |
252b5132 RH |
3122 | } |
3123 | ||
c0f3af97 L |
3124 | /* Build the VEX prefix. */ |
3125 | ||
3126 | static void | |
d3ce72d0 | 3127 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3128 | { |
3129 | unsigned int register_specifier; | |
3130 | unsigned int implied_prefix; | |
3131 | unsigned int vector_length; | |
3132 | ||
3133 | /* Check register specifier. */ | |
3134 | if (i.vex.register_specifier) | |
43234a1e L |
3135 | { |
3136 | register_specifier = | |
3137 | ~register_number (i.vex.register_specifier) & 0xf; | |
3138 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3139 | } | |
c0f3af97 L |
3140 | else |
3141 | register_specifier = 0xf; | |
3142 | ||
33eaf5de | 3143 | /* Use 2-byte VEX prefix by swapping destination and source |
fa99fab2 L |
3144 | operand. */ |
3145 | if (!i.swap_operand | |
3146 | && i.operands == i.reg_operands | |
7f399153 | 3147 | && i.tm.opcode_modifier.vexopcode == VEX0F |
fa99fab2 L |
3148 | && i.tm.opcode_modifier.s |
3149 | && i.rex == REX_B) | |
3150 | { | |
3151 | unsigned int xchg = i.operands - 1; | |
3152 | union i386_op temp_op; | |
3153 | i386_operand_type temp_type; | |
3154 | ||
3155 | temp_type = i.types[xchg]; | |
3156 | i.types[xchg] = i.types[0]; | |
3157 | i.types[0] = temp_type; | |
3158 | temp_op = i.op[xchg]; | |
3159 | i.op[xchg] = i.op[0]; | |
3160 | i.op[0] = temp_op; | |
3161 | ||
9c2799c2 | 3162 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3163 | |
3164 | i.rex = REX_R; | |
3165 | xchg = i.rm.regmem; | |
3166 | i.rm.regmem = i.rm.reg; | |
3167 | i.rm.reg = xchg; | |
3168 | ||
3169 | /* Use the next insn. */ | |
3170 | i.tm = t[1]; | |
3171 | } | |
3172 | ||
539f890d L |
3173 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3174 | vector_length = avxscalar; | |
3175 | else | |
3176 | vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; | |
c0f3af97 L |
3177 | |
3178 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3179 | { | |
3180 | case 0: | |
3181 | implied_prefix = 0; | |
3182 | break; | |
3183 | case DATA_PREFIX_OPCODE: | |
3184 | implied_prefix = 1; | |
3185 | break; | |
3186 | case REPE_PREFIX_OPCODE: | |
3187 | implied_prefix = 2; | |
3188 | break; | |
3189 | case REPNE_PREFIX_OPCODE: | |
3190 | implied_prefix = 3; | |
3191 | break; | |
3192 | default: | |
3193 | abort (); | |
3194 | } | |
3195 | ||
3196 | /* Use 2-byte VEX prefix if possible. */ | |
7f399153 | 3197 | if (i.tm.opcode_modifier.vexopcode == VEX0F |
04251de0 | 3198 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
3199 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3200 | { | |
3201 | /* 2-byte VEX prefix. */ | |
3202 | unsigned int r; | |
3203 | ||
3204 | i.vex.length = 2; | |
3205 | i.vex.bytes[0] = 0xc5; | |
3206 | ||
3207 | /* Check the REX.R bit. */ | |
3208 | r = (i.rex & REX_R) ? 0 : 1; | |
3209 | i.vex.bytes[1] = (r << 7 | |
3210 | | register_specifier << 3 | |
3211 | | vector_length << 2 | |
3212 | | implied_prefix); | |
3213 | } | |
3214 | else | |
3215 | { | |
3216 | /* 3-byte VEX prefix. */ | |
3217 | unsigned int m, w; | |
3218 | ||
f88c9eb0 | 3219 | i.vex.length = 3; |
f88c9eb0 | 3220 | |
7f399153 | 3221 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3222 | { |
7f399153 L |
3223 | case VEX0F: |
3224 | m = 0x1; | |
80de6e00 | 3225 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3226 | break; |
3227 | case VEX0F38: | |
3228 | m = 0x2; | |
80de6e00 | 3229 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3230 | break; |
3231 | case VEX0F3A: | |
3232 | m = 0x3; | |
80de6e00 | 3233 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3234 | break; |
3235 | case XOP08: | |
5dd85c99 SP |
3236 | m = 0x8; |
3237 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3238 | break; |
3239 | case XOP09: | |
f88c9eb0 SP |
3240 | m = 0x9; |
3241 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3242 | break; |
3243 | case XOP0A: | |
f88c9eb0 SP |
3244 | m = 0xa; |
3245 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3246 | break; |
3247 | default: | |
3248 | abort (); | |
f88c9eb0 | 3249 | } |
c0f3af97 | 3250 | |
c0f3af97 L |
3251 | /* The high 3 bits of the second VEX byte are 1's compliment |
3252 | of RXB bits from REX. */ | |
3253 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3254 | ||
3255 | /* Check the REX.W bit. */ | |
3256 | w = (i.rex & REX_W) ? 1 : 0; | |
b28d1bda IT |
3257 | if (i.tm.opcode_modifier.vexw == VEXW1) |
3258 | w = 1; | |
c0f3af97 L |
3259 | |
3260 | i.vex.bytes[2] = (w << 7 | |
3261 | | register_specifier << 3 | |
3262 | | vector_length << 2 | |
3263 | | implied_prefix); | |
3264 | } | |
3265 | } | |
3266 | ||
43234a1e L |
3267 | /* Build the EVEX prefix. */ |
3268 | ||
3269 | static void | |
3270 | build_evex_prefix (void) | |
3271 | { | |
3272 | unsigned int register_specifier; | |
3273 | unsigned int implied_prefix; | |
3274 | unsigned int m, w; | |
3275 | rex_byte vrex_used = 0; | |
3276 | ||
3277 | /* Check register specifier. */ | |
3278 | if (i.vex.register_specifier) | |
3279 | { | |
3280 | gas_assert ((i.vrex & REX_X) == 0); | |
3281 | ||
3282 | register_specifier = i.vex.register_specifier->reg_num; | |
3283 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3284 | register_specifier += 8; | |
3285 | /* The upper 16 registers are encoded in the fourth byte of the | |
3286 | EVEX prefix. */ | |
3287 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3288 | i.vex.bytes[3] = 0x8; | |
3289 | register_specifier = ~register_specifier & 0xf; | |
3290 | } | |
3291 | else | |
3292 | { | |
3293 | register_specifier = 0xf; | |
3294 | ||
3295 | /* Encode upper 16 vector index register in the fourth byte of | |
3296 | the EVEX prefix. */ | |
3297 | if (!(i.vrex & REX_X)) | |
3298 | i.vex.bytes[3] = 0x8; | |
3299 | else | |
3300 | vrex_used |= REX_X; | |
3301 | } | |
3302 | ||
3303 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3304 | { | |
3305 | case 0: | |
3306 | implied_prefix = 0; | |
3307 | break; | |
3308 | case DATA_PREFIX_OPCODE: | |
3309 | implied_prefix = 1; | |
3310 | break; | |
3311 | case REPE_PREFIX_OPCODE: | |
3312 | implied_prefix = 2; | |
3313 | break; | |
3314 | case REPNE_PREFIX_OPCODE: | |
3315 | implied_prefix = 3; | |
3316 | break; | |
3317 | default: | |
3318 | abort (); | |
3319 | } | |
3320 | ||
3321 | /* 4 byte EVEX prefix. */ | |
3322 | i.vex.length = 4; | |
3323 | i.vex.bytes[0] = 0x62; | |
3324 | ||
3325 | /* mmmm bits. */ | |
3326 | switch (i.tm.opcode_modifier.vexopcode) | |
3327 | { | |
3328 | case VEX0F: | |
3329 | m = 1; | |
3330 | break; | |
3331 | case VEX0F38: | |
3332 | m = 2; | |
3333 | break; | |
3334 | case VEX0F3A: | |
3335 | m = 3; | |
3336 | break; | |
3337 | default: | |
3338 | abort (); | |
3339 | break; | |
3340 | } | |
3341 | ||
3342 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3343 | bits from REX. */ | |
3344 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3345 | ||
3346 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3347 | REX_R bit in VREX. */ | |
3348 | if (!(i.vrex & REX_R)) | |
3349 | i.vex.bytes[1] |= 0x10; | |
3350 | else | |
3351 | vrex_used |= REX_R; | |
3352 | ||
3353 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3354 | { | |
3355 | /* When all operands are registers, the REX_X bit in REX is not | |
3356 | used. We reuse it to encode the upper 16 registers, which is | |
3357 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3358 | as 1's compliment. */ | |
3359 | if ((i.vrex & REX_B)) | |
3360 | { | |
3361 | vrex_used |= REX_B; | |
3362 | i.vex.bytes[1] &= ~0x40; | |
3363 | } | |
3364 | } | |
3365 | ||
3366 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3367 | i.vrex &= ~vrex_used; | |
3368 | gas_assert (i.vrex == 0); | |
3369 | ||
3370 | /* Check the REX.W bit. */ | |
3371 | w = (i.rex & REX_W) ? 1 : 0; | |
3372 | if (i.tm.opcode_modifier.vexw) | |
3373 | { | |
3374 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
3375 | w = 1; | |
3376 | } | |
3377 | /* If w is not set it means we are dealing with WIG instruction. */ | |
3378 | else if (!w) | |
3379 | { | |
3380 | if (evexwig == evexw1) | |
3381 | w = 1; | |
3382 | } | |
3383 | ||
3384 | /* Encode the U bit. */ | |
3385 | implied_prefix |= 0x4; | |
3386 | ||
3387 | /* The third byte of the EVEX prefix. */ | |
3388 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3389 | ||
3390 | /* The fourth byte of the EVEX prefix. */ | |
3391 | /* The zeroing-masking bit. */ | |
3392 | if (i.mask && i.mask->zeroing) | |
3393 | i.vex.bytes[3] |= 0x80; | |
3394 | ||
3395 | /* Don't always set the broadcast bit if there is no RC. */ | |
3396 | if (!i.rounding) | |
3397 | { | |
3398 | /* Encode the vector length. */ | |
3399 | unsigned int vec_length; | |
3400 | ||
3401 | switch (i.tm.opcode_modifier.evex) | |
3402 | { | |
3403 | case EVEXLIG: /* LL' is ignored */ | |
3404 | vec_length = evexlig << 5; | |
3405 | break; | |
3406 | case EVEX128: | |
3407 | vec_length = 0 << 5; | |
3408 | break; | |
3409 | case EVEX256: | |
3410 | vec_length = 1 << 5; | |
3411 | break; | |
3412 | case EVEX512: | |
3413 | vec_length = 2 << 5; | |
3414 | break; | |
3415 | default: | |
3416 | abort (); | |
3417 | break; | |
3418 | } | |
3419 | i.vex.bytes[3] |= vec_length; | |
3420 | /* Encode the broadcast bit. */ | |
3421 | if (i.broadcast) | |
3422 | i.vex.bytes[3] |= 0x10; | |
3423 | } | |
3424 | else | |
3425 | { | |
3426 | if (i.rounding->type != saeonly) | |
3427 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3428 | else | |
d3d3c6db | 3429 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3430 | } |
3431 | ||
3432 | if (i.mask && i.mask->mask) | |
3433 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3434 | } | |
3435 | ||
65da13b5 L |
3436 | static void |
3437 | process_immext (void) | |
3438 | { | |
3439 | expressionS *exp; | |
3440 | ||
4c692bc7 JB |
3441 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3442 | && i.operands > 0) | |
65da13b5 | 3443 | { |
4c692bc7 JB |
3444 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3445 | with an opcode suffix which is coded in the same place as an | |
3446 | 8-bit immediate field would be. | |
3447 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3448 | unsigned int x; |
3449 | ||
3450 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3451 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3452 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3453 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3454 | i.tm.name); | |
3455 | ||
3456 | i.operands = 0; | |
65da13b5 L |
3457 | } |
3458 | ||
9916071f AP |
3459 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3460 | { | |
3461 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3462 | suffix which is coded in the same place as an 8-bit immediate | |
3463 | field would be. | |
3464 | Here we check those operands and remove them afterwards. */ | |
3465 | unsigned int x; | |
3466 | ||
3467 | if (i.operands != 3) | |
3468 | abort(); | |
3469 | ||
3470 | for (x = 0; x < 2; x++) | |
3471 | if (register_number (i.op[x].regs) != x) | |
3472 | goto bad_register_operand; | |
3473 | ||
3474 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3475 | if (register_number (i.op[x].regs) | |
3476 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3477 | { | |
3478 | bad_register_operand: | |
3479 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3480 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3481 | i.tm.name); | |
3482 | } | |
3483 | ||
3484 | i.operands = 0; | |
3485 | } | |
3486 | ||
c0f3af97 | 3487 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3488 | which is coded in the same place as an 8-bit immediate field |
3489 | would be. Here we fake an 8-bit immediate operand from the | |
3490 | opcode suffix stored in tm.extension_opcode. | |
3491 | ||
c1e679ec | 3492 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3493 | 3 argument instructions. */ |
65da13b5 | 3494 | |
43234a1e | 3495 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3496 | && (i.operands <= 2 |
43234a1e L |
3497 | || ((i.tm.opcode_modifier.vex |
3498 | || i.tm.opcode_modifier.evex) | |
7ab9ffdd | 3499 | && i.operands <= 4))); |
65da13b5 L |
3500 | |
3501 | exp = &im_expressions[i.imm_operands++]; | |
3502 | i.op[i.operands].imms = exp; | |
3503 | i.types[i.operands] = imm8; | |
3504 | i.operands++; | |
3505 | exp->X_op = O_constant; | |
3506 | exp->X_add_number = i.tm.extension_opcode; | |
3507 | i.tm.extension_opcode = None; | |
3508 | } | |
3509 | ||
42164a71 L |
3510 | |
3511 | static int | |
3512 | check_hle (void) | |
3513 | { | |
3514 | switch (i.tm.opcode_modifier.hleprefixok) | |
3515 | { | |
3516 | default: | |
3517 | abort (); | |
82c2def5 | 3518 | case HLEPrefixNone: |
165de32a L |
3519 | as_bad (_("invalid instruction `%s' after `%s'"), |
3520 | i.tm.name, i.hle_prefix); | |
42164a71 | 3521 | return 0; |
82c2def5 | 3522 | case HLEPrefixLock: |
42164a71 L |
3523 | if (i.prefix[LOCK_PREFIX]) |
3524 | return 1; | |
165de32a | 3525 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3526 | return 0; |
82c2def5 | 3527 | case HLEPrefixAny: |
42164a71 | 3528 | return 1; |
82c2def5 | 3529 | case HLEPrefixRelease: |
42164a71 L |
3530 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3531 | { | |
3532 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3533 | i.tm.name); | |
3534 | return 0; | |
3535 | } | |
3536 | if (i.mem_operands == 0 | |
3537 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3538 | { | |
3539 | as_bad (_("memory destination needed for instruction `%s'" | |
3540 | " after `xrelease'"), i.tm.name); | |
3541 | return 0; | |
3542 | } | |
3543 | return 1; | |
3544 | } | |
3545 | } | |
3546 | ||
252b5132 RH |
3547 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3548 | machine dependent instruction. This function is supposed to emit | |
3549 | the frags/bytes it assembles to. */ | |
3550 | ||
3551 | void | |
65da13b5 | 3552 | md_assemble (char *line) |
252b5132 | 3553 | { |
40fb9820 | 3554 | unsigned int j; |
83b16ac6 | 3555 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 3556 | const insn_template *t; |
252b5132 | 3557 | |
47926f60 | 3558 | /* Initialize globals. */ |
252b5132 RH |
3559 | memset (&i, '\0', sizeof (i)); |
3560 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 3561 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
3562 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
3563 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 3564 | save_stack_p = save_stack; |
252b5132 RH |
3565 | |
3566 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
3567 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 3568 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 3569 | |
29b0f896 AM |
3570 | line = parse_insn (line, mnemonic); |
3571 | if (line == NULL) | |
3572 | return; | |
83b16ac6 | 3573 | mnem_suffix = i.suffix; |
252b5132 | 3574 | |
29b0f896 | 3575 | line = parse_operands (line, mnemonic); |
ee86248c | 3576 | this_operand = -1; |
8325cc63 JB |
3577 | xfree (i.memop1_string); |
3578 | i.memop1_string = NULL; | |
29b0f896 AM |
3579 | if (line == NULL) |
3580 | return; | |
252b5132 | 3581 | |
29b0f896 AM |
3582 | /* Now we've parsed the mnemonic into a set of templates, and have the |
3583 | operands at hand. */ | |
3584 | ||
3585 | /* All intel opcodes have reversed operands except for "bound" and | |
3586 | "enter". We also don't reverse intersegment "jmp" and "call" | |
3587 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 3588 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
3589 | if (intel_syntax |
3590 | && i.operands > 1 | |
29b0f896 | 3591 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 3592 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
3593 | && !(operand_type_check (i.types[0], imm) |
3594 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
3595 | swap_operands (); |
3596 | ||
ec56d5c0 JB |
3597 | /* The order of the immediates should be reversed |
3598 | for 2 immediates extrq and insertq instructions */ | |
3599 | if (i.imm_operands == 2 | |
3600 | && (strcmp (mnemonic, "extrq") == 0 | |
3601 | || strcmp (mnemonic, "insertq") == 0)) | |
3602 | swap_2_operands (0, 1); | |
3603 | ||
29b0f896 AM |
3604 | if (i.imm_operands) |
3605 | optimize_imm (); | |
3606 | ||
b300c311 L |
3607 | /* Don't optimize displacement for movabs since it only takes 64bit |
3608 | displacement. */ | |
3609 | if (i.disp_operands | |
a501d77e | 3610 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
3611 | && (flag_code != CODE_64BIT |
3612 | || strcmp (mnemonic, "movabs") != 0)) | |
3613 | optimize_disp (); | |
29b0f896 AM |
3614 | |
3615 | /* Next, we find a template that matches the given insn, | |
3616 | making sure the overlap of the given operands types is consistent | |
3617 | with the template operand types. */ | |
252b5132 | 3618 | |
83b16ac6 | 3619 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 3620 | return; |
252b5132 | 3621 | |
7bab8ab5 | 3622 | if (sse_check != check_none |
81f8a913 | 3623 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
3624 | && (i.tm.cpu_flags.bitfield.cpusse |
3625 | || i.tm.cpu_flags.bitfield.cpusse2 | |
3626 | || i.tm.cpu_flags.bitfield.cpusse3 | |
3627 | || i.tm.cpu_flags.bitfield.cpussse3 | |
3628 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
3629 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
3630 | { | |
7bab8ab5 | 3631 | (sse_check == check_warning |
daf50ae7 L |
3632 | ? as_warn |
3633 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
3634 | } | |
3635 | ||
321fd21e L |
3636 | /* Zap movzx and movsx suffix. The suffix has been set from |
3637 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
3638 | or extracted from mnemonic in AT&T syntax. But we'll use | |
3639 | the destination register to choose the suffix for encoding. */ | |
3640 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 3641 | { |
321fd21e L |
3642 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
3643 | there is no suffix, the default will be byte extension. */ | |
3644 | if (i.reg_operands != 2 | |
3645 | && !i.suffix | |
7ab9ffdd | 3646 | && intel_syntax) |
321fd21e L |
3647 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
3648 | ||
3649 | i.suffix = 0; | |
cd61ebfe | 3650 | } |
24eab124 | 3651 | |
40fb9820 | 3652 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
3653 | if (!add_prefix (FWAIT_OPCODE)) |
3654 | return; | |
252b5132 | 3655 | |
d5de92cf L |
3656 | /* Check if REP prefix is OK. */ |
3657 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
3658 | { | |
3659 | as_bad (_("invalid instruction `%s' after `%s'"), | |
3660 | i.tm.name, i.rep_prefix); | |
3661 | return; | |
3662 | } | |
3663 | ||
c1ba0266 L |
3664 | /* Check for lock without a lockable instruction. Destination operand |
3665 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
3666 | if (i.prefix[LOCK_PREFIX] |
3667 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
3668 | || i.mem_operands == 0 |
3669 | || (i.tm.base_opcode != 0x86 | |
3670 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
3671 | { |
3672 | as_bad (_("expecting lockable instruction after `lock'")); | |
3673 | return; | |
3674 | } | |
3675 | ||
42164a71 | 3676 | /* Check if HLE prefix is OK. */ |
165de32a | 3677 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
3678 | return; |
3679 | ||
7e8b059b L |
3680 | /* Check BND prefix. */ |
3681 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
3682 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
3683 | ||
327e8c42 JB |
3684 | if (i.tm.cpu_flags.bitfield.cpumpx) |
3685 | { | |
3686 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
3687 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
3688 | else if (flag_code != CODE_16BIT | |
3689 | ? i.prefix[ADDR_PREFIX] | |
3690 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
3691 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
3692 | } | |
7e8b059b L |
3693 | |
3694 | /* Insert BND prefix. */ | |
3695 | if (add_bnd_prefix | |
3696 | && i.tm.opcode_modifier.bndprefixok | |
3697 | && !i.prefix[BND_PREFIX]) | |
3698 | add_prefix (BND_PREFIX_OPCODE); | |
3699 | ||
29b0f896 | 3700 | /* Check string instruction segment overrides. */ |
40fb9820 | 3701 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
3702 | { |
3703 | if (!check_string ()) | |
5dd0794d | 3704 | return; |
fc0763e6 | 3705 | i.disp_operands = 0; |
29b0f896 | 3706 | } |
5dd0794d | 3707 | |
29b0f896 AM |
3708 | if (!process_suffix ()) |
3709 | return; | |
e413e4e9 | 3710 | |
bc0844ae L |
3711 | /* Update operand types. */ |
3712 | for (j = 0; j < i.operands; j++) | |
3713 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3714 | ||
29b0f896 AM |
3715 | /* Make still unresolved immediate matches conform to size of immediate |
3716 | given in i.suffix. */ | |
3717 | if (!finalize_imm ()) | |
3718 | return; | |
252b5132 | 3719 | |
40fb9820 | 3720 | if (i.types[0].bitfield.imm1) |
29b0f896 | 3721 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 3722 | |
9afe6eb8 L |
3723 | /* We only need to check those implicit registers for instructions |
3724 | with 3 operands or less. */ | |
3725 | if (i.operands <= 3) | |
3726 | for (j = 0; j < i.operands; j++) | |
3727 | if (i.types[j].bitfield.inoutportreg | |
3728 | || i.types[j].bitfield.shiftcount | |
3729 | || i.types[j].bitfield.acc | |
3730 | || i.types[j].bitfield.floatacc) | |
3731 | i.reg_operands--; | |
40fb9820 | 3732 | |
c0f3af97 L |
3733 | /* ImmExt should be processed after SSE2AVX. */ |
3734 | if (!i.tm.opcode_modifier.sse2avx | |
3735 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 3736 | process_immext (); |
252b5132 | 3737 | |
29b0f896 AM |
3738 | /* For insns with operands there are more diddles to do to the opcode. */ |
3739 | if (i.operands) | |
3740 | { | |
3741 | if (!process_operands ()) | |
3742 | return; | |
3743 | } | |
40fb9820 | 3744 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
3745 | { |
3746 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
3747 | as_warn (_("translating to `%sp'"), i.tm.name); | |
3748 | } | |
252b5132 | 3749 | |
9e5e5283 L |
3750 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) |
3751 | { | |
3752 | if (flag_code == CODE_16BIT) | |
3753 | { | |
3754 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
3755 | i.tm.name); | |
3756 | return; | |
3757 | } | |
c0f3af97 | 3758 | |
9e5e5283 L |
3759 | if (i.tm.opcode_modifier.vex) |
3760 | build_vex_prefix (t); | |
3761 | else | |
3762 | build_evex_prefix (); | |
3763 | } | |
43234a1e | 3764 | |
5dd85c99 SP |
3765 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
3766 | instructions may define INT_OPCODE as well, so avoid this corner | |
3767 | case for those instructions that use MODRM. */ | |
3768 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
3769 | && !i.tm.opcode_modifier.modrm |
3770 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
3771 | { |
3772 | i.tm.base_opcode = INT3_OPCODE; | |
3773 | i.imm_operands = 0; | |
3774 | } | |
252b5132 | 3775 | |
40fb9820 L |
3776 | if ((i.tm.opcode_modifier.jump |
3777 | || i.tm.opcode_modifier.jumpbyte | |
3778 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
3779 | && i.op[0].disps->X_op == O_constant) |
3780 | { | |
3781 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
3782 | the absolute address given by the constant. Since ix86 jumps and | |
3783 | calls are pc relative, we need to generate a reloc. */ | |
3784 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
3785 | i.op[0].disps->X_op = O_symbol; | |
3786 | } | |
252b5132 | 3787 | |
40fb9820 | 3788 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 3789 | i.rex |= REX_W; |
252b5132 | 3790 | |
29b0f896 AM |
3791 | /* For 8 bit registers we need an empty rex prefix. Also if the |
3792 | instruction already has a prefix, we need to convert old | |
3793 | registers to new ones. */ | |
773f551c | 3794 | |
40fb9820 | 3795 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 3796 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 3797 | || (i.types[1].bitfield.reg8 |
29b0f896 | 3798 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
3799 | || ((i.types[0].bitfield.reg8 |
3800 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
3801 | && i.rex != 0)) |
3802 | { | |
3803 | int x; | |
726c5dcd | 3804 | |
29b0f896 AM |
3805 | i.rex |= REX_OPCODE; |
3806 | for (x = 0; x < 2; x++) | |
3807 | { | |
3808 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 3809 | if (i.types[x].bitfield.reg8 |
29b0f896 | 3810 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 3811 | { |
29b0f896 AM |
3812 | /* In case it is "hi" register, give up. */ |
3813 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 3814 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 3815 | "instruction requiring REX prefix."), |
a540244d | 3816 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 3817 | |
29b0f896 AM |
3818 | /* Otherwise it is equivalent to the extended register. |
3819 | Since the encoding doesn't change this is merely | |
3820 | cosmetic cleanup for debug output. */ | |
3821 | ||
3822 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 3823 | } |
29b0f896 AM |
3824 | } |
3825 | } | |
773f551c | 3826 | |
7ab9ffdd | 3827 | if (i.rex != 0) |
29b0f896 AM |
3828 | add_prefix (REX_OPCODE | i.rex); |
3829 | ||
3830 | /* We are ready to output the insn. */ | |
3831 | output_insn (); | |
3832 | } | |
3833 | ||
3834 | static char * | |
e3bb37b5 | 3835 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
3836 | { |
3837 | char *l = line; | |
3838 | char *token_start = l; | |
3839 | char *mnem_p; | |
5c6af06e | 3840 | int supported; |
d3ce72d0 | 3841 | const insn_template *t; |
b6169b20 | 3842 | char *dot_p = NULL; |
29b0f896 | 3843 | |
29b0f896 AM |
3844 | while (1) |
3845 | { | |
3846 | mnem_p = mnemonic; | |
3847 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
3848 | { | |
b6169b20 L |
3849 | if (*mnem_p == '.') |
3850 | dot_p = mnem_p; | |
29b0f896 AM |
3851 | mnem_p++; |
3852 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 3853 | { |
29b0f896 AM |
3854 | as_bad (_("no such instruction: `%s'"), token_start); |
3855 | return NULL; | |
3856 | } | |
3857 | l++; | |
3858 | } | |
3859 | if (!is_space_char (*l) | |
3860 | && *l != END_OF_INSN | |
e44823cf JB |
3861 | && (intel_syntax |
3862 | || (*l != PREFIX_SEPARATOR | |
3863 | && *l != ','))) | |
29b0f896 AM |
3864 | { |
3865 | as_bad (_("invalid character %s in mnemonic"), | |
3866 | output_invalid (*l)); | |
3867 | return NULL; | |
3868 | } | |
3869 | if (token_start == l) | |
3870 | { | |
e44823cf | 3871 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
3872 | as_bad (_("expecting prefix; got nothing")); |
3873 | else | |
3874 | as_bad (_("expecting mnemonic; got nothing")); | |
3875 | return NULL; | |
3876 | } | |
45288df1 | 3877 | |
29b0f896 | 3878 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 3879 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 3880 | |
29b0f896 AM |
3881 | if (*l != END_OF_INSN |
3882 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
3883 | && current_templates | |
40fb9820 | 3884 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 3885 | { |
c6fb90c8 | 3886 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
3887 | { |
3888 | as_bad ((flag_code != CODE_64BIT | |
3889 | ? _("`%s' is only supported in 64-bit mode") | |
3890 | : _("`%s' is not supported in 64-bit mode")), | |
3891 | current_templates->start->name); | |
3892 | return NULL; | |
3893 | } | |
29b0f896 AM |
3894 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
3895 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
3896 | if ((current_templates->start->opcode_modifier.size16 |
3897 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 3898 | && flag_code != CODE_64BIT |
40fb9820 | 3899 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
3900 | ^ (flag_code == CODE_16BIT))) |
3901 | { | |
3902 | as_bad (_("redundant %s prefix"), | |
3903 | current_templates->start->name); | |
3904 | return NULL; | |
45288df1 | 3905 | } |
29b0f896 AM |
3906 | /* Add prefix, checking for repeated prefixes. */ |
3907 | switch (add_prefix (current_templates->start->base_opcode)) | |
3908 | { | |
c32fa91d | 3909 | case PREFIX_EXIST: |
29b0f896 | 3910 | return NULL; |
c32fa91d | 3911 | case PREFIX_REP: |
42164a71 | 3912 | if (current_templates->start->cpu_flags.bitfield.cpuhle) |
165de32a | 3913 | i.hle_prefix = current_templates->start->name; |
7e8b059b L |
3914 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) |
3915 | i.bnd_prefix = current_templates->start->name; | |
42164a71 | 3916 | else |
d5de92cf | 3917 | i.rep_prefix = current_templates->start->name; |
29b0f896 | 3918 | break; |
c32fa91d L |
3919 | default: |
3920 | break; | |
29b0f896 AM |
3921 | } |
3922 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
3923 | token_start = ++l; | |
3924 | } | |
3925 | else | |
3926 | break; | |
3927 | } | |
45288df1 | 3928 | |
30a55f88 | 3929 | if (!current_templates) |
b6169b20 | 3930 | { |
f8a5c266 L |
3931 | /* Check if we should swap operand or force 32bit displacement in |
3932 | encoding. */ | |
30a55f88 L |
3933 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
3934 | i.swap_operand = 1; | |
8d63c93e | 3935 | else if (mnem_p - 3 == dot_p |
a501d77e L |
3936 | && dot_p[1] == 'd' |
3937 | && dot_p[2] == '8') | |
3938 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 3939 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
3940 | && dot_p[1] == 'd' |
3941 | && dot_p[2] == '3' | |
3942 | && dot_p[3] == '2') | |
a501d77e | 3943 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
3944 | else |
3945 | goto check_suffix; | |
3946 | mnem_p = dot_p; | |
3947 | *dot_p = '\0'; | |
d3ce72d0 | 3948 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
3949 | } |
3950 | ||
29b0f896 AM |
3951 | if (!current_templates) |
3952 | { | |
b6169b20 | 3953 | check_suffix: |
29b0f896 AM |
3954 | /* See if we can get a match by trimming off a suffix. */ |
3955 | switch (mnem_p[-1]) | |
3956 | { | |
3957 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
3958 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
3959 | i.suffix = SHORT_MNEM_SUFFIX; | |
3960 | else | |
1a0670f3 | 3961 | /* Fall through. */ |
29b0f896 AM |
3962 | case BYTE_MNEM_SUFFIX: |
3963 | case QWORD_MNEM_SUFFIX: | |
3964 | i.suffix = mnem_p[-1]; | |
3965 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3966 | current_templates = (const templates *) hash_find (op_hash, |
3967 | mnemonic); | |
29b0f896 AM |
3968 | break; |
3969 | case SHORT_MNEM_SUFFIX: | |
3970 | case LONG_MNEM_SUFFIX: | |
3971 | if (!intel_syntax) | |
3972 | { | |
3973 | i.suffix = mnem_p[-1]; | |
3974 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3975 | current_templates = (const templates *) hash_find (op_hash, |
3976 | mnemonic); | |
29b0f896 AM |
3977 | } |
3978 | break; | |
252b5132 | 3979 | |
29b0f896 AM |
3980 | /* Intel Syntax. */ |
3981 | case 'd': | |
3982 | if (intel_syntax) | |
3983 | { | |
9306ca4a | 3984 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
3985 | i.suffix = SHORT_MNEM_SUFFIX; |
3986 | else | |
3987 | i.suffix = LONG_MNEM_SUFFIX; | |
3988 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3989 | current_templates = (const templates *) hash_find (op_hash, |
3990 | mnemonic); | |
29b0f896 AM |
3991 | } |
3992 | break; | |
3993 | } | |
3994 | if (!current_templates) | |
3995 | { | |
3996 | as_bad (_("no such instruction: `%s'"), token_start); | |
3997 | return NULL; | |
3998 | } | |
3999 | } | |
252b5132 | 4000 | |
40fb9820 L |
4001 | if (current_templates->start->opcode_modifier.jump |
4002 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4003 | { |
4004 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4005 | predict taken and predict not taken respectively. | |
4006 | I'm not sure that branch hints actually do anything on loop | |
4007 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4008 | may work in the future and it doesn't hurt to accept them | |
4009 | now. */ | |
4010 | if (l[0] == ',' && l[1] == 'p') | |
4011 | { | |
4012 | if (l[2] == 't') | |
4013 | { | |
4014 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4015 | return NULL; | |
4016 | l += 3; | |
4017 | } | |
4018 | else if (l[2] == 'n') | |
4019 | { | |
4020 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4021 | return NULL; | |
4022 | l += 3; | |
4023 | } | |
4024 | } | |
4025 | } | |
4026 | /* Any other comma loses. */ | |
4027 | if (*l == ',') | |
4028 | { | |
4029 | as_bad (_("invalid character %s in mnemonic"), | |
4030 | output_invalid (*l)); | |
4031 | return NULL; | |
4032 | } | |
252b5132 | 4033 | |
29b0f896 | 4034 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4035 | supported = 0; |
4036 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4037 | { | |
c0f3af97 L |
4038 | supported |= cpu_flags_match (t); |
4039 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 4040 | goto skip; |
5c6af06e | 4041 | } |
3629bb00 | 4042 | |
c0f3af97 | 4043 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
4044 | { |
4045 | as_bad (flag_code == CODE_64BIT | |
4046 | ? _("`%s' is not supported in 64-bit mode") | |
4047 | : _("`%s' is only supported in 64-bit mode"), | |
4048 | current_templates->start->name); | |
4049 | return NULL; | |
4050 | } | |
c0f3af97 | 4051 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 4052 | { |
3629bb00 | 4053 | as_bad (_("`%s' is not supported on `%s%s'"), |
7ab9ffdd | 4054 | current_templates->start->name, |
41aacd83 | 4055 | cpu_arch_name ? cpu_arch_name : default_arch, |
3629bb00 L |
4056 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
4057 | return NULL; | |
29b0f896 | 4058 | } |
3629bb00 L |
4059 | |
4060 | skip: | |
4061 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 4062 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
4063 | { |
4064 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
4065 | } | |
252b5132 | 4066 | |
29b0f896 AM |
4067 | return l; |
4068 | } | |
252b5132 | 4069 | |
29b0f896 | 4070 | static char * |
e3bb37b5 | 4071 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4072 | { |
4073 | char *token_start; | |
3138f287 | 4074 | |
29b0f896 AM |
4075 | /* 1 if operand is pending after ','. */ |
4076 | unsigned int expecting_operand = 0; | |
252b5132 | 4077 | |
29b0f896 AM |
4078 | /* Non-zero if operand parens not balanced. */ |
4079 | unsigned int paren_not_balanced; | |
4080 | ||
4081 | while (*l != END_OF_INSN) | |
4082 | { | |
4083 | /* Skip optional white space before operand. */ | |
4084 | if (is_space_char (*l)) | |
4085 | ++l; | |
d02603dc | 4086 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4087 | { |
4088 | as_bad (_("invalid character %s before operand %d"), | |
4089 | output_invalid (*l), | |
4090 | i.operands + 1); | |
4091 | return NULL; | |
4092 | } | |
d02603dc | 4093 | token_start = l; /* After white space. */ |
29b0f896 AM |
4094 | paren_not_balanced = 0; |
4095 | while (paren_not_balanced || *l != ',') | |
4096 | { | |
4097 | if (*l == END_OF_INSN) | |
4098 | { | |
4099 | if (paren_not_balanced) | |
4100 | { | |
4101 | if (!intel_syntax) | |
4102 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4103 | i.operands + 1); | |
4104 | else | |
4105 | as_bad (_("unbalanced brackets in operand %d."), | |
4106 | i.operands + 1); | |
4107 | return NULL; | |
4108 | } | |
4109 | else | |
4110 | break; /* we are done */ | |
4111 | } | |
d02603dc | 4112 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4113 | { |
4114 | as_bad (_("invalid character %s in operand %d"), | |
4115 | output_invalid (*l), | |
4116 | i.operands + 1); | |
4117 | return NULL; | |
4118 | } | |
4119 | if (!intel_syntax) | |
4120 | { | |
4121 | if (*l == '(') | |
4122 | ++paren_not_balanced; | |
4123 | if (*l == ')') | |
4124 | --paren_not_balanced; | |
4125 | } | |
4126 | else | |
4127 | { | |
4128 | if (*l == '[') | |
4129 | ++paren_not_balanced; | |
4130 | if (*l == ']') | |
4131 | --paren_not_balanced; | |
4132 | } | |
4133 | l++; | |
4134 | } | |
4135 | if (l != token_start) | |
4136 | { /* Yes, we've read in another operand. */ | |
4137 | unsigned int operand_ok; | |
4138 | this_operand = i.operands++; | |
4139 | if (i.operands > MAX_OPERANDS) | |
4140 | { | |
4141 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4142 | MAX_OPERANDS); | |
4143 | return NULL; | |
4144 | } | |
9d46ce34 | 4145 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4146 | /* Now parse operand adding info to 'i' as we go along. */ |
4147 | END_STRING_AND_SAVE (l); | |
4148 | ||
4149 | if (intel_syntax) | |
4150 | operand_ok = | |
4151 | i386_intel_operand (token_start, | |
4152 | intel_float_operand (mnemonic)); | |
4153 | else | |
a7619375 | 4154 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4155 | |
4156 | RESTORE_END_STRING (l); | |
4157 | if (!operand_ok) | |
4158 | return NULL; | |
4159 | } | |
4160 | else | |
4161 | { | |
4162 | if (expecting_operand) | |
4163 | { | |
4164 | expecting_operand_after_comma: | |
4165 | as_bad (_("expecting operand after ','; got nothing")); | |
4166 | return NULL; | |
4167 | } | |
4168 | if (*l == ',') | |
4169 | { | |
4170 | as_bad (_("expecting operand before ','; got nothing")); | |
4171 | return NULL; | |
4172 | } | |
4173 | } | |
7f3f1ea2 | 4174 | |
29b0f896 AM |
4175 | /* Now *l must be either ',' or END_OF_INSN. */ |
4176 | if (*l == ',') | |
4177 | { | |
4178 | if (*++l == END_OF_INSN) | |
4179 | { | |
4180 | /* Just skip it, if it's \n complain. */ | |
4181 | goto expecting_operand_after_comma; | |
4182 | } | |
4183 | expecting_operand = 1; | |
4184 | } | |
4185 | } | |
4186 | return l; | |
4187 | } | |
7f3f1ea2 | 4188 | |
050dfa73 | 4189 | static void |
4d456e3d | 4190 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4191 | { |
4192 | union i386_op temp_op; | |
40fb9820 | 4193 | i386_operand_type temp_type; |
050dfa73 | 4194 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4195 | |
050dfa73 MM |
4196 | temp_type = i.types[xchg2]; |
4197 | i.types[xchg2] = i.types[xchg1]; | |
4198 | i.types[xchg1] = temp_type; | |
4199 | temp_op = i.op[xchg2]; | |
4200 | i.op[xchg2] = i.op[xchg1]; | |
4201 | i.op[xchg1] = temp_op; | |
4202 | temp_reloc = i.reloc[xchg2]; | |
4203 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4204 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4205 | |
4206 | if (i.mask) | |
4207 | { | |
4208 | if (i.mask->operand == xchg1) | |
4209 | i.mask->operand = xchg2; | |
4210 | else if (i.mask->operand == xchg2) | |
4211 | i.mask->operand = xchg1; | |
4212 | } | |
4213 | if (i.broadcast) | |
4214 | { | |
4215 | if (i.broadcast->operand == xchg1) | |
4216 | i.broadcast->operand = xchg2; | |
4217 | else if (i.broadcast->operand == xchg2) | |
4218 | i.broadcast->operand = xchg1; | |
4219 | } | |
4220 | if (i.rounding) | |
4221 | { | |
4222 | if (i.rounding->operand == xchg1) | |
4223 | i.rounding->operand = xchg2; | |
4224 | else if (i.rounding->operand == xchg2) | |
4225 | i.rounding->operand = xchg1; | |
4226 | } | |
050dfa73 MM |
4227 | } |
4228 | ||
29b0f896 | 4229 | static void |
e3bb37b5 | 4230 | swap_operands (void) |
29b0f896 | 4231 | { |
b7c61d9a | 4232 | switch (i.operands) |
050dfa73 | 4233 | { |
c0f3af97 | 4234 | case 5: |
b7c61d9a | 4235 | case 4: |
4d456e3d | 4236 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4237 | /* Fall through. */ |
b7c61d9a L |
4238 | case 3: |
4239 | case 2: | |
4d456e3d | 4240 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4241 | break; |
4242 | default: | |
4243 | abort (); | |
29b0f896 | 4244 | } |
29b0f896 AM |
4245 | |
4246 | if (i.mem_operands == 2) | |
4247 | { | |
4248 | const seg_entry *temp_seg; | |
4249 | temp_seg = i.seg[0]; | |
4250 | i.seg[0] = i.seg[1]; | |
4251 | i.seg[1] = temp_seg; | |
4252 | } | |
4253 | } | |
252b5132 | 4254 | |
29b0f896 AM |
4255 | /* Try to ensure constant immediates are represented in the smallest |
4256 | opcode possible. */ | |
4257 | static void | |
e3bb37b5 | 4258 | optimize_imm (void) |
29b0f896 AM |
4259 | { |
4260 | char guess_suffix = 0; | |
4261 | int op; | |
252b5132 | 4262 | |
29b0f896 AM |
4263 | if (i.suffix) |
4264 | guess_suffix = i.suffix; | |
4265 | else if (i.reg_operands) | |
4266 | { | |
4267 | /* Figure out a suffix from the last register operand specified. | |
4268 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4269 | but the following works for instructions with immediates. | |
4270 | In any case, we can't set i.suffix yet. */ | |
4271 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4272 | if (i.types[op].bitfield.reg8) |
7ab9ffdd | 4273 | { |
40fb9820 L |
4274 | guess_suffix = BYTE_MNEM_SUFFIX; |
4275 | break; | |
4276 | } | |
4277 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 4278 | { |
40fb9820 L |
4279 | guess_suffix = WORD_MNEM_SUFFIX; |
4280 | break; | |
4281 | } | |
4282 | else if (i.types[op].bitfield.reg32) | |
4283 | { | |
4284 | guess_suffix = LONG_MNEM_SUFFIX; | |
4285 | break; | |
4286 | } | |
4287 | else if (i.types[op].bitfield.reg64) | |
4288 | { | |
4289 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4290 | break; |
252b5132 | 4291 | } |
29b0f896 AM |
4292 | } |
4293 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4294 | guess_suffix = WORD_MNEM_SUFFIX; | |
4295 | ||
4296 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4297 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4298 | { |
4299 | switch (i.op[op].imms->X_op) | |
252b5132 | 4300 | { |
29b0f896 AM |
4301 | case O_constant: |
4302 | /* If a suffix is given, this operand may be shortened. */ | |
4303 | switch (guess_suffix) | |
252b5132 | 4304 | { |
29b0f896 | 4305 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
4306 | i.types[op].bitfield.imm32 = 1; |
4307 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4308 | break; |
4309 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
4310 | i.types[op].bitfield.imm16 = 1; |
4311 | i.types[op].bitfield.imm32 = 1; | |
4312 | i.types[op].bitfield.imm32s = 1; | |
4313 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4314 | break; |
4315 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
4316 | i.types[op].bitfield.imm8 = 1; |
4317 | i.types[op].bitfield.imm8s = 1; | |
4318 | i.types[op].bitfield.imm16 = 1; | |
4319 | i.types[op].bitfield.imm32 = 1; | |
4320 | i.types[op].bitfield.imm32s = 1; | |
4321 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 4322 | break; |
252b5132 | 4323 | } |
252b5132 | 4324 | |
29b0f896 AM |
4325 | /* If this operand is at most 16 bits, convert it |
4326 | to a signed 16 bit number before trying to see | |
4327 | whether it will fit in an even smaller size. | |
4328 | This allows a 16-bit operand such as $0xffe0 to | |
4329 | be recognised as within Imm8S range. */ | |
40fb9820 | 4330 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 4331 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 4332 | { |
29b0f896 AM |
4333 | i.op[op].imms->X_add_number = |
4334 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
4335 | } | |
a28def75 L |
4336 | #ifdef BFD64 |
4337 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 4338 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
4339 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
4340 | == 0)) | |
4341 | { | |
4342 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
4343 | ^ ((offsetT) 1 << 31)) | |
4344 | - ((offsetT) 1 << 31)); | |
4345 | } | |
a28def75 | 4346 | #endif |
40fb9820 | 4347 | i.types[op] |
c6fb90c8 L |
4348 | = operand_type_or (i.types[op], |
4349 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 4350 | |
29b0f896 AM |
4351 | /* We must avoid matching of Imm32 templates when 64bit |
4352 | only immediate is available. */ | |
4353 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 4354 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 4355 | break; |
252b5132 | 4356 | |
29b0f896 AM |
4357 | case O_absent: |
4358 | case O_register: | |
4359 | abort (); | |
4360 | ||
4361 | /* Symbols and expressions. */ | |
4362 | default: | |
9cd96992 JB |
4363 | /* Convert symbolic operand to proper sizes for matching, but don't |
4364 | prevent matching a set of insns that only supports sizes other | |
4365 | than those matching the insn suffix. */ | |
4366 | { | |
40fb9820 | 4367 | i386_operand_type mask, allowed; |
d3ce72d0 | 4368 | const insn_template *t; |
9cd96992 | 4369 | |
0dfbf9d7 L |
4370 | operand_type_set (&mask, 0); |
4371 | operand_type_set (&allowed, 0); | |
40fb9820 | 4372 | |
4eed87de AM |
4373 | for (t = current_templates->start; |
4374 | t < current_templates->end; | |
4375 | ++t) | |
c6fb90c8 L |
4376 | allowed = operand_type_or (allowed, |
4377 | t->operand_types[op]); | |
9cd96992 JB |
4378 | switch (guess_suffix) |
4379 | { | |
4380 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
4381 | mask.bitfield.imm64 = 1; |
4382 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
4383 | break; |
4384 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 4385 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
4386 | break; |
4387 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 4388 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
4389 | break; |
4390 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 4391 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
4392 | break; |
4393 | default: | |
9cd96992 JB |
4394 | break; |
4395 | } | |
c6fb90c8 | 4396 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 4397 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 4398 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 4399 | } |
29b0f896 | 4400 | break; |
252b5132 | 4401 | } |
29b0f896 AM |
4402 | } |
4403 | } | |
47926f60 | 4404 | |
29b0f896 AM |
4405 | /* Try to use the smallest displacement type too. */ |
4406 | static void | |
e3bb37b5 | 4407 | optimize_disp (void) |
29b0f896 AM |
4408 | { |
4409 | int op; | |
3e73aa7c | 4410 | |
29b0f896 | 4411 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4412 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 4413 | { |
b300c311 | 4414 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 4415 | { |
91d6fa6a | 4416 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 4417 | |
40fb9820 | 4418 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 4419 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
4420 | { |
4421 | /* If this operand is at most 16 bits, convert | |
4422 | to a signed 16 bit number and don't use 64bit | |
4423 | displacement. */ | |
91d6fa6a | 4424 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 4425 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4426 | } |
a28def75 L |
4427 | #ifdef BFD64 |
4428 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 4429 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 4430 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
4431 | { |
4432 | /* If this operand is at most 32 bits, convert | |
4433 | to a signed 32 bit number and don't use 64bit | |
4434 | displacement. */ | |
91d6fa6a NC |
4435 | op_disp &= (((offsetT) 2 << 31) - 1); |
4436 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 4437 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4438 | } |
a28def75 | 4439 | #endif |
91d6fa6a | 4440 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 4441 | { |
40fb9820 L |
4442 | i.types[op].bitfield.disp8 = 0; |
4443 | i.types[op].bitfield.disp16 = 0; | |
4444 | i.types[op].bitfield.disp32 = 0; | |
4445 | i.types[op].bitfield.disp32s = 0; | |
4446 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
4447 | i.op[op].disps = 0; |
4448 | i.disp_operands--; | |
4449 | } | |
4450 | else if (flag_code == CODE_64BIT) | |
4451 | { | |
91d6fa6a | 4452 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 4453 | { |
40fb9820 L |
4454 | i.types[op].bitfield.disp64 = 0; |
4455 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 4456 | } |
0e1147d9 | 4457 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 4458 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 4459 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 4460 | } |
40fb9820 L |
4461 | if ((i.types[op].bitfield.disp32 |
4462 | || i.types[op].bitfield.disp32s | |
4463 | || i.types[op].bitfield.disp16) | |
91d6fa6a | 4464 | && fits_in_signed_byte (op_disp)) |
40fb9820 | 4465 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 4466 | } |
67a4f2b7 AO |
4467 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
4468 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
4469 | { | |
4470 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
4471 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
4472 | i.types[op].bitfield.disp8 = 0; |
4473 | i.types[op].bitfield.disp16 = 0; | |
4474 | i.types[op].bitfield.disp32 = 0; | |
4475 | i.types[op].bitfield.disp32s = 0; | |
4476 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
4477 | } |
4478 | else | |
b300c311 | 4479 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 4480 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 4481 | } |
29b0f896 AM |
4482 | } |
4483 | ||
6c30d220 L |
4484 | /* Check if operands are valid for the instruction. */ |
4485 | ||
4486 | static int | |
4487 | check_VecOperands (const insn_template *t) | |
4488 | { | |
43234a1e L |
4489 | unsigned int op; |
4490 | ||
6c30d220 L |
4491 | /* Without VSIB byte, we can't have a vector register for index. */ |
4492 | if (!t->opcode_modifier.vecsib | |
4493 | && i.index_reg | |
4494 | && (i.index_reg->reg_type.bitfield.regxmm | |
43234a1e L |
4495 | || i.index_reg->reg_type.bitfield.regymm |
4496 | || i.index_reg->reg_type.bitfield.regzmm)) | |
6c30d220 L |
4497 | { |
4498 | i.error = unsupported_vector_index_register; | |
4499 | return 1; | |
4500 | } | |
4501 | ||
ad8ecc81 MZ |
4502 | /* Check if default mask is allowed. */ |
4503 | if (t->opcode_modifier.nodefmask | |
4504 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
4505 | { | |
4506 | i.error = no_default_mask; | |
4507 | return 1; | |
4508 | } | |
4509 | ||
7bab8ab5 JB |
4510 | /* For VSIB byte, we need a vector register for index, and all vector |
4511 | registers must be distinct. */ | |
4512 | if (t->opcode_modifier.vecsib) | |
4513 | { | |
4514 | if (!i.index_reg | |
6c30d220 L |
4515 | || !((t->opcode_modifier.vecsib == VecSIB128 |
4516 | && i.index_reg->reg_type.bitfield.regxmm) | |
4517 | || (t->opcode_modifier.vecsib == VecSIB256 | |
43234a1e L |
4518 | && i.index_reg->reg_type.bitfield.regymm) |
4519 | || (t->opcode_modifier.vecsib == VecSIB512 | |
4520 | && i.index_reg->reg_type.bitfield.regzmm))) | |
7bab8ab5 JB |
4521 | { |
4522 | i.error = invalid_vsib_address; | |
4523 | return 1; | |
4524 | } | |
4525 | ||
43234a1e L |
4526 | gas_assert (i.reg_operands == 2 || i.mask); |
4527 | if (i.reg_operands == 2 && !i.mask) | |
4528 | { | |
4529 | gas_assert (i.types[0].bitfield.regxmm | |
7c84a0ca | 4530 | || i.types[0].bitfield.regymm); |
43234a1e | 4531 | gas_assert (i.types[2].bitfield.regxmm |
7c84a0ca | 4532 | || i.types[2].bitfield.regymm); |
43234a1e L |
4533 | if (operand_check == check_none) |
4534 | return 0; | |
4535 | if (register_number (i.op[0].regs) | |
4536 | != register_number (i.index_reg) | |
4537 | && register_number (i.op[2].regs) | |
4538 | != register_number (i.index_reg) | |
4539 | && register_number (i.op[0].regs) | |
4540 | != register_number (i.op[2].regs)) | |
4541 | return 0; | |
4542 | if (operand_check == check_error) | |
4543 | { | |
4544 | i.error = invalid_vector_register_set; | |
4545 | return 1; | |
4546 | } | |
4547 | as_warn (_("mask, index, and destination registers should be distinct")); | |
4548 | } | |
8444f82a MZ |
4549 | else if (i.reg_operands == 1 && i.mask) |
4550 | { | |
4551 | if ((i.types[1].bitfield.regymm | |
4552 | || i.types[1].bitfield.regzmm) | |
4553 | && (register_number (i.op[1].regs) | |
4554 | == register_number (i.index_reg))) | |
4555 | { | |
4556 | if (operand_check == check_error) | |
4557 | { | |
4558 | i.error = invalid_vector_register_set; | |
4559 | return 1; | |
4560 | } | |
4561 | if (operand_check != check_none) | |
4562 | as_warn (_("index and destination registers should be distinct")); | |
4563 | } | |
4564 | } | |
43234a1e | 4565 | } |
7bab8ab5 | 4566 | |
43234a1e L |
4567 | /* Check if broadcast is supported by the instruction and is applied |
4568 | to the memory operand. */ | |
4569 | if (i.broadcast) | |
4570 | { | |
4571 | int broadcasted_opnd_size; | |
4572 | ||
4573 | /* Check if specified broadcast is supported in this instruction, | |
4574 | and it's applied to memory operand of DWORD or QWORD type, | |
4575 | depending on VecESize. */ | |
4576 | if (i.broadcast->type != t->opcode_modifier.broadcast | |
4577 | || !i.types[i.broadcast->operand].bitfield.mem | |
4578 | || (t->opcode_modifier.vecesize == 0 | |
4579 | && !i.types[i.broadcast->operand].bitfield.dword | |
4580 | && !i.types[i.broadcast->operand].bitfield.unspecified) | |
4581 | || (t->opcode_modifier.vecesize == 1 | |
4582 | && !i.types[i.broadcast->operand].bitfield.qword | |
4583 | && !i.types[i.broadcast->operand].bitfield.unspecified)) | |
4584 | goto bad_broadcast; | |
4585 | ||
4586 | broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32; | |
4587 | if (i.broadcast->type == BROADCAST_1TO16) | |
4588 | broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */ | |
4589 | else if (i.broadcast->type == BROADCAST_1TO8) | |
4590 | broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */ | |
b28d1bda IT |
4591 | else if (i.broadcast->type == BROADCAST_1TO4) |
4592 | broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */ | |
4593 | else if (i.broadcast->type == BROADCAST_1TO2) | |
4594 | broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */ | |
43234a1e L |
4595 | else |
4596 | goto bad_broadcast; | |
4597 | ||
4598 | if ((broadcasted_opnd_size == 256 | |
4599 | && !t->operand_types[i.broadcast->operand].bitfield.ymmword) | |
4600 | || (broadcasted_opnd_size == 512 | |
4601 | && !t->operand_types[i.broadcast->operand].bitfield.zmmword)) | |
4602 | { | |
4603 | bad_broadcast: | |
4604 | i.error = unsupported_broadcast; | |
4605 | return 1; | |
4606 | } | |
4607 | } | |
4608 | /* If broadcast is supported in this instruction, we need to check if | |
4609 | operand of one-element size isn't specified without broadcast. */ | |
4610 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
4611 | { | |
4612 | /* Find memory operand. */ | |
4613 | for (op = 0; op < i.operands; op++) | |
4614 | if (operand_type_check (i.types[op], anymem)) | |
4615 | break; | |
4616 | gas_assert (op < i.operands); | |
4617 | /* Check size of the memory operand. */ | |
4618 | if ((t->opcode_modifier.vecesize == 0 | |
4619 | && i.types[op].bitfield.dword) | |
4620 | || (t->opcode_modifier.vecesize == 1 | |
4621 | && i.types[op].bitfield.qword)) | |
4622 | { | |
4623 | i.error = broadcast_needed; | |
4624 | return 1; | |
4625 | } | |
4626 | } | |
4627 | ||
4628 | /* Check if requested masking is supported. */ | |
4629 | if (i.mask | |
4630 | && (!t->opcode_modifier.masking | |
4631 | || (i.mask->zeroing | |
4632 | && t->opcode_modifier.masking == MERGING_MASKING))) | |
4633 | { | |
4634 | i.error = unsupported_masking; | |
4635 | return 1; | |
4636 | } | |
4637 | ||
4638 | /* Check if masking is applied to dest operand. */ | |
4639 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
4640 | { | |
4641 | i.error = mask_not_on_destination; | |
4642 | return 1; | |
4643 | } | |
4644 | ||
43234a1e L |
4645 | /* Check RC/SAE. */ |
4646 | if (i.rounding) | |
4647 | { | |
4648 | if ((i.rounding->type != saeonly | |
4649 | && !t->opcode_modifier.staticrounding) | |
4650 | || (i.rounding->type == saeonly | |
4651 | && (t->opcode_modifier.staticrounding | |
4652 | || !t->opcode_modifier.sae))) | |
4653 | { | |
4654 | i.error = unsupported_rc_sae; | |
4655 | return 1; | |
4656 | } | |
4657 | /* If the instruction has several immediate operands and one of | |
4658 | them is rounding, the rounding operand should be the last | |
4659 | immediate operand. */ | |
4660 | if (i.imm_operands > 1 | |
4661 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 4662 | { |
43234a1e | 4663 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
4664 | return 1; |
4665 | } | |
6c30d220 L |
4666 | } |
4667 | ||
43234a1e L |
4668 | /* Check vector Disp8 operand. */ |
4669 | if (t->opcode_modifier.disp8memshift) | |
4670 | { | |
4671 | if (i.broadcast) | |
4672 | i.memshift = t->opcode_modifier.vecesize ? 3 : 2; | |
4673 | else | |
4674 | i.memshift = t->opcode_modifier.disp8memshift; | |
4675 | ||
4676 | for (op = 0; op < i.operands; op++) | |
4677 | if (operand_type_check (i.types[op], disp) | |
4678 | && i.op[op].disps->X_op == O_constant) | |
4679 | { | |
4680 | offsetT value = i.op[op].disps->X_add_number; | |
5be33403 L |
4681 | int vec_disp8_ok |
4682 | = (i.disp_encoding != disp_encoding_32bit | |
4683 | && fits_in_vec_disp8 (value)); | |
43234a1e L |
4684 | if (t->operand_types [op].bitfield.vec_disp8) |
4685 | { | |
4686 | if (vec_disp8_ok) | |
4687 | i.types[op].bitfield.vec_disp8 = 1; | |
4688 | else | |
4689 | { | |
4690 | /* Vector insn can only have Vec_Disp8/Disp32 in | |
4691 | 32/64bit modes, and Vec_Disp8/Disp16 in 16bit | |
4692 | mode. */ | |
4693 | i.types[op].bitfield.disp8 = 0; | |
4694 | if (flag_code != CODE_16BIT) | |
4695 | i.types[op].bitfield.disp16 = 0; | |
4696 | } | |
4697 | } | |
4698 | else if (flag_code != CODE_16BIT) | |
4699 | { | |
4700 | /* One form of this instruction supports vector Disp8. | |
4701 | Try vector Disp8 if we need to use Disp32. */ | |
4702 | if (vec_disp8_ok && !fits_in_signed_byte (value)) | |
4703 | { | |
4704 | i.error = try_vector_disp8; | |
4705 | return 1; | |
4706 | } | |
4707 | } | |
4708 | } | |
4709 | } | |
4710 | else | |
4711 | i.memshift = -1; | |
4712 | ||
6c30d220 L |
4713 | return 0; |
4714 | } | |
4715 | ||
43f3e2ee | 4716 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
4717 | operand types. */ |
4718 | ||
4719 | static int | |
4720 | VEX_check_operands (const insn_template *t) | |
4721 | { | |
43234a1e L |
4722 | /* VREX is only valid with EVEX prefix. */ |
4723 | if (i.need_vrex && !t->opcode_modifier.evex) | |
4724 | { | |
4725 | i.error = invalid_register_operand; | |
4726 | return 1; | |
4727 | } | |
4728 | ||
a683cc34 SP |
4729 | if (!t->opcode_modifier.vex) |
4730 | return 0; | |
4731 | ||
4732 | /* Only check VEX_Imm4, which must be the first operand. */ | |
4733 | if (t->operand_types[0].bitfield.vec_imm4) | |
4734 | { | |
4735 | if (i.op[0].imms->X_op != O_constant | |
4736 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 4737 | { |
a65babc9 | 4738 | i.error = bad_imm4; |
891edac4 L |
4739 | return 1; |
4740 | } | |
a683cc34 SP |
4741 | |
4742 | /* Turn off Imm8 so that update_imm won't complain. */ | |
4743 | i.types[0] = vec_imm4; | |
4744 | } | |
4745 | ||
4746 | return 0; | |
4747 | } | |
4748 | ||
d3ce72d0 | 4749 | static const insn_template * |
83b16ac6 | 4750 | match_template (char mnem_suffix) |
29b0f896 AM |
4751 | { |
4752 | /* Points to template once we've found it. */ | |
d3ce72d0 | 4753 | const insn_template *t; |
40fb9820 | 4754 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 4755 | i386_operand_type overlap4; |
29b0f896 | 4756 | unsigned int found_reverse_match; |
83b16ac6 | 4757 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 4758 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 4759 | int addr_prefix_disp; |
a5c311ca | 4760 | unsigned int j; |
3629bb00 | 4761 | unsigned int found_cpu_match; |
45664ddb | 4762 | unsigned int check_register; |
5614d22c | 4763 | enum i386_error specific_error = 0; |
29b0f896 | 4764 | |
c0f3af97 L |
4765 | #if MAX_OPERANDS != 5 |
4766 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
4767 | #endif |
4768 | ||
29b0f896 | 4769 | found_reverse_match = 0; |
539e75ad | 4770 | addr_prefix_disp = -1; |
40fb9820 L |
4771 | |
4772 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
4773 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
4774 | suffix_check.no_bsuf = 1; | |
4775 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4776 | suffix_check.no_wsuf = 1; | |
4777 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
4778 | suffix_check.no_ssuf = 1; | |
4779 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4780 | suffix_check.no_lsuf = 1; | |
4781 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4782 | suffix_check.no_qsuf = 1; | |
4783 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 4784 | suffix_check.no_ldsuf = 1; |
29b0f896 | 4785 | |
83b16ac6 JB |
4786 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
4787 | if (intel_syntax) | |
4788 | { | |
4789 | switch (mnem_suffix) | |
4790 | { | |
4791 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
4792 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
4793 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
4794 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
4795 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
4796 | } | |
4797 | } | |
4798 | ||
01559ecc L |
4799 | /* Must have right number of operands. */ |
4800 | i.error = number_of_operands_mismatch; | |
4801 | ||
45aa61fe | 4802 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 4803 | { |
539e75ad L |
4804 | addr_prefix_disp = -1; |
4805 | ||
29b0f896 AM |
4806 | if (i.operands != t->operands) |
4807 | continue; | |
4808 | ||
50aecf8c | 4809 | /* Check processor support. */ |
a65babc9 | 4810 | i.error = unsupported; |
c0f3af97 L |
4811 | found_cpu_match = (cpu_flags_match (t) |
4812 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
4813 | if (!found_cpu_match) |
4814 | continue; | |
4815 | ||
e1d4d893 | 4816 | /* Check old gcc support. */ |
a65babc9 | 4817 | i.error = old_gcc_only; |
e1d4d893 L |
4818 | if (!old_gcc && t->opcode_modifier.oldgcc) |
4819 | continue; | |
4820 | ||
4821 | /* Check AT&T mnemonic. */ | |
a65babc9 | 4822 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 4823 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
4824 | continue; |
4825 | ||
e92bae62 | 4826 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 4827 | i.error = unsupported_syntax; |
5c07affc | 4828 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
4829 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
4830 | || (intel64 && t->opcode_modifier.amd64) | |
4831 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
4832 | continue; |
4833 | ||
20592a94 | 4834 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 4835 | i.error = invalid_instruction_suffix; |
567e4e96 L |
4836 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
4837 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
4838 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
4839 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
4840 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
4841 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
4842 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 4843 | continue; |
83b16ac6 JB |
4844 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
4845 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
4846 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
4847 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
4848 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
4849 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
4850 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
4851 | continue; | |
29b0f896 | 4852 | |
5c07affc | 4853 | if (!operand_size_match (t)) |
7d5e4556 | 4854 | continue; |
539e75ad | 4855 | |
5c07affc L |
4856 | for (j = 0; j < MAX_OPERANDS; j++) |
4857 | operand_types[j] = t->operand_types[j]; | |
4858 | ||
45aa61fe AM |
4859 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
4860 | if (i.suffix == QWORD_MNEM_SUFFIX | |
4861 | && flag_code != CODE_64BIT | |
4862 | && (intel_syntax | |
40fb9820 | 4863 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
4864 | && !intel_float_operand (t->name)) |
4865 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 4866 | && ((!operand_types[0].bitfield.regmmx |
c0f3af97 | 4867 | && !operand_types[0].bitfield.regxmm |
43234a1e L |
4868 | && !operand_types[0].bitfield.regymm |
4869 | && !operand_types[0].bitfield.regzmm) | |
40fb9820 | 4870 | || (!operand_types[t->operands > 1].bitfield.regmmx |
ac4eb736 AM |
4871 | && operand_types[t->operands > 1].bitfield.regxmm |
4872 | && operand_types[t->operands > 1].bitfield.regymm | |
4873 | && operand_types[t->operands > 1].bitfield.regzmm)) | |
45aa61fe AM |
4874 | && (t->base_opcode != 0x0fc7 |
4875 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
4876 | continue; | |
4877 | ||
192dc9c6 JB |
4878 | /* In general, don't allow 32-bit operands on pre-386. */ |
4879 | else if (i.suffix == LONG_MNEM_SUFFIX | |
4880 | && !cpu_arch_flags.bitfield.cpui386 | |
4881 | && (intel_syntax | |
4882 | ? (!t->opcode_modifier.ignoresize | |
4883 | && !intel_float_operand (t->name)) | |
4884 | : intel_float_operand (t->name) != 2) | |
4885 | && ((!operand_types[0].bitfield.regmmx | |
4886 | && !operand_types[0].bitfield.regxmm) | |
4887 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
ac4eb736 | 4888 | && operand_types[t->operands > 1].bitfield.regxmm))) |
192dc9c6 JB |
4889 | continue; |
4890 | ||
29b0f896 | 4891 | /* Do not verify operands when there are none. */ |
50aecf8c | 4892 | else |
29b0f896 | 4893 | { |
c6fb90c8 | 4894 | if (!t->operands) |
2dbab7d5 L |
4895 | /* We've found a match; break out of loop. */ |
4896 | break; | |
29b0f896 | 4897 | } |
252b5132 | 4898 | |
539e75ad L |
4899 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
4900 | into Disp32/Disp16/Disp32 operand. */ | |
4901 | if (i.prefix[ADDR_PREFIX] != 0) | |
4902 | { | |
40fb9820 | 4903 | /* There should be only one Disp operand. */ |
539e75ad L |
4904 | switch (flag_code) |
4905 | { | |
4906 | case CODE_16BIT: | |
40fb9820 L |
4907 | for (j = 0; j < MAX_OPERANDS; j++) |
4908 | { | |
4909 | if (operand_types[j].bitfield.disp16) | |
4910 | { | |
4911 | addr_prefix_disp = j; | |
4912 | operand_types[j].bitfield.disp32 = 1; | |
4913 | operand_types[j].bitfield.disp16 = 0; | |
4914 | break; | |
4915 | } | |
4916 | } | |
539e75ad L |
4917 | break; |
4918 | case CODE_32BIT: | |
40fb9820 L |
4919 | for (j = 0; j < MAX_OPERANDS; j++) |
4920 | { | |
4921 | if (operand_types[j].bitfield.disp32) | |
4922 | { | |
4923 | addr_prefix_disp = j; | |
4924 | operand_types[j].bitfield.disp32 = 0; | |
4925 | operand_types[j].bitfield.disp16 = 1; | |
4926 | break; | |
4927 | } | |
4928 | } | |
539e75ad L |
4929 | break; |
4930 | case CODE_64BIT: | |
40fb9820 L |
4931 | for (j = 0; j < MAX_OPERANDS; j++) |
4932 | { | |
4933 | if (operand_types[j].bitfield.disp64) | |
4934 | { | |
4935 | addr_prefix_disp = j; | |
4936 | operand_types[j].bitfield.disp64 = 0; | |
4937 | operand_types[j].bitfield.disp32 = 1; | |
4938 | break; | |
4939 | } | |
4940 | } | |
539e75ad L |
4941 | break; |
4942 | } | |
539e75ad L |
4943 | } |
4944 | ||
02a86693 L |
4945 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
4946 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
4947 | continue; | |
4948 | ||
56ffb741 L |
4949 | /* We check register size if needed. */ |
4950 | check_register = t->opcode_modifier.checkregsize; | |
c6fb90c8 | 4951 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
4952 | switch (t->operands) |
4953 | { | |
4954 | case 1: | |
40fb9820 | 4955 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
4956 | continue; |
4957 | break; | |
4958 | case 2: | |
33eaf5de | 4959 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
4960 | only in 32bit mode and we can use opcode 0x90. In 64bit |
4961 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
4962 | zero-extend %eax to %rax. */ | |
4963 | if (flag_code == CODE_64BIT | |
4964 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
4965 | && operand_type_equal (&i.types [0], &acc32) |
4966 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 4967 | continue; |
b6169b20 L |
4968 | if (i.swap_operand) |
4969 | { | |
4970 | /* If we swap operand in encoding, we either match | |
4971 | the next one or reverse direction of operands. */ | |
4972 | if (t->opcode_modifier.s) | |
4973 | continue; | |
4974 | else if (t->opcode_modifier.d) | |
4975 | goto check_reverse; | |
4976 | } | |
1a0670f3 | 4977 | /* Fall through. */ |
b6169b20 | 4978 | |
29b0f896 | 4979 | case 3: |
fa99fab2 L |
4980 | /* If we swap operand in encoding, we match the next one. */ |
4981 | if (i.swap_operand && t->opcode_modifier.s) | |
4982 | continue; | |
1a0670f3 | 4983 | /* Fall through. */ |
f48ff2ae | 4984 | case 4: |
c0f3af97 | 4985 | case 5: |
c6fb90c8 | 4986 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
4987 | if (!operand_type_match (overlap0, i.types[0]) |
4988 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
4989 | || (check_register |
4990 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
4991 | operand_types[0], |
4992 | overlap1, i.types[1], | |
4993 | operand_types[1]))) | |
29b0f896 AM |
4994 | { |
4995 | /* Check if other direction is valid ... */ | |
40fb9820 | 4996 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
4997 | continue; |
4998 | ||
b6169b20 | 4999 | check_reverse: |
29b0f896 | 5000 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
5001 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
5002 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
5003 | if (!operand_type_match (overlap0, i.types[0]) |
5004 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
5005 | || (check_register |
5006 | && !operand_type_register_match (overlap0, | |
5007 | i.types[0], | |
5008 | operand_types[1], | |
5009 | overlap1, | |
5010 | i.types[1], | |
5011 | operand_types[0]))) | |
29b0f896 AM |
5012 | { |
5013 | /* Does not match either direction. */ | |
5014 | continue; | |
5015 | } | |
5016 | /* found_reverse_match holds which of D or FloatDR | |
5017 | we've found. */ | |
40fb9820 | 5018 | if (t->opcode_modifier.d) |
8a2ed489 | 5019 | found_reverse_match = Opcode_D; |
40fb9820 | 5020 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
5021 | found_reverse_match = Opcode_FloatD; |
5022 | else | |
5023 | found_reverse_match = 0; | |
40fb9820 | 5024 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5025 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5026 | } |
f48ff2ae | 5027 | else |
29b0f896 | 5028 | { |
f48ff2ae | 5029 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5030 | switch (t->operands) |
5031 | { | |
c0f3af97 L |
5032 | case 5: |
5033 | overlap4 = operand_type_and (i.types[4], | |
5034 | operand_types[4]); | |
1a0670f3 | 5035 | /* Fall through. */ |
d1cbb4db | 5036 | case 4: |
c6fb90c8 L |
5037 | overlap3 = operand_type_and (i.types[3], |
5038 | operand_types[3]); | |
1a0670f3 | 5039 | /* Fall through. */ |
d1cbb4db | 5040 | case 3: |
c6fb90c8 L |
5041 | overlap2 = operand_type_and (i.types[2], |
5042 | operand_types[2]); | |
d1cbb4db L |
5043 | break; |
5044 | } | |
29b0f896 | 5045 | |
f48ff2ae L |
5046 | switch (t->operands) |
5047 | { | |
c0f3af97 L |
5048 | case 5: |
5049 | if (!operand_type_match (overlap4, i.types[4]) | |
5050 | || !operand_type_register_match (overlap3, | |
5051 | i.types[3], | |
5052 | operand_types[3], | |
5053 | overlap4, | |
5054 | i.types[4], | |
5055 | operand_types[4])) | |
5056 | continue; | |
1a0670f3 | 5057 | /* Fall through. */ |
f48ff2ae | 5058 | case 4: |
40fb9820 | 5059 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
5060 | || (check_register |
5061 | && !operand_type_register_match (overlap2, | |
5062 | i.types[2], | |
5063 | operand_types[2], | |
5064 | overlap3, | |
5065 | i.types[3], | |
5066 | operand_types[3]))) | |
f48ff2ae | 5067 | continue; |
1a0670f3 | 5068 | /* Fall through. */ |
f48ff2ae L |
5069 | case 3: |
5070 | /* Here we make use of the fact that there are no | |
5071 | reverse match 3 operand instructions, and all 3 | |
5072 | operand instructions only need to be checked for | |
5073 | register consistency between operands 2 and 3. */ | |
40fb9820 | 5074 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
5075 | || (check_register |
5076 | && !operand_type_register_match (overlap1, | |
5077 | i.types[1], | |
5078 | operand_types[1], | |
5079 | overlap2, | |
5080 | i.types[2], | |
5081 | operand_types[2]))) | |
f48ff2ae L |
5082 | continue; |
5083 | break; | |
5084 | } | |
29b0f896 | 5085 | } |
f48ff2ae | 5086 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5087 | slip through to break. */ |
5088 | } | |
3629bb00 | 5089 | if (!found_cpu_match) |
29b0f896 AM |
5090 | { |
5091 | found_reverse_match = 0; | |
5092 | continue; | |
5093 | } | |
c0f3af97 | 5094 | |
5614d22c JB |
5095 | /* Check if vector and VEX operands are valid. */ |
5096 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5097 | { | |
5098 | specific_error = i.error; | |
5099 | continue; | |
5100 | } | |
a683cc34 | 5101 | |
29b0f896 AM |
5102 | /* We've found a match; break out of loop. */ |
5103 | break; | |
5104 | } | |
5105 | ||
5106 | if (t == current_templates->end) | |
5107 | { | |
5108 | /* We found no match. */ | |
a65babc9 | 5109 | const char *err_msg; |
5614d22c | 5110 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5111 | { |
5112 | default: | |
5113 | abort (); | |
86e026a4 | 5114 | case operand_size_mismatch: |
a65babc9 L |
5115 | err_msg = _("operand size mismatch"); |
5116 | break; | |
5117 | case operand_type_mismatch: | |
5118 | err_msg = _("operand type mismatch"); | |
5119 | break; | |
5120 | case register_type_mismatch: | |
5121 | err_msg = _("register type mismatch"); | |
5122 | break; | |
5123 | case number_of_operands_mismatch: | |
5124 | err_msg = _("number of operands mismatch"); | |
5125 | break; | |
5126 | case invalid_instruction_suffix: | |
5127 | err_msg = _("invalid instruction suffix"); | |
5128 | break; | |
5129 | case bad_imm4: | |
4a2608e3 | 5130 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 L |
5131 | break; |
5132 | case old_gcc_only: | |
5133 | err_msg = _("only supported with old gcc"); | |
5134 | break; | |
5135 | case unsupported_with_intel_mnemonic: | |
5136 | err_msg = _("unsupported with Intel mnemonic"); | |
5137 | break; | |
5138 | case unsupported_syntax: | |
5139 | err_msg = _("unsupported syntax"); | |
5140 | break; | |
5141 | case unsupported: | |
35262a23 | 5142 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
5143 | current_templates->start->name); |
5144 | return NULL; | |
6c30d220 L |
5145 | case invalid_vsib_address: |
5146 | err_msg = _("invalid VSIB address"); | |
5147 | break; | |
7bab8ab5 JB |
5148 | case invalid_vector_register_set: |
5149 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5150 | break; | |
6c30d220 L |
5151 | case unsupported_vector_index_register: |
5152 | err_msg = _("unsupported vector index register"); | |
5153 | break; | |
43234a1e L |
5154 | case unsupported_broadcast: |
5155 | err_msg = _("unsupported broadcast"); | |
5156 | break; | |
5157 | case broadcast_not_on_src_operand: | |
5158 | err_msg = _("broadcast not on source memory operand"); | |
5159 | break; | |
5160 | case broadcast_needed: | |
5161 | err_msg = _("broadcast is needed for operand of such type"); | |
5162 | break; | |
5163 | case unsupported_masking: | |
5164 | err_msg = _("unsupported masking"); | |
5165 | break; | |
5166 | case mask_not_on_destination: | |
5167 | err_msg = _("mask not on destination operand"); | |
5168 | break; | |
5169 | case no_default_mask: | |
5170 | err_msg = _("default mask isn't allowed"); | |
5171 | break; | |
5172 | case unsupported_rc_sae: | |
5173 | err_msg = _("unsupported static rounding/sae"); | |
5174 | break; | |
5175 | case rc_sae_operand_not_last_imm: | |
5176 | if (intel_syntax) | |
5177 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
5178 | else | |
5179 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
5180 | break; | |
5181 | case invalid_register_operand: | |
5182 | err_msg = _("invalid register operand"); | |
5183 | break; | |
a65babc9 L |
5184 | } |
5185 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 5186 | current_templates->start->name); |
fa99fab2 | 5187 | return NULL; |
29b0f896 | 5188 | } |
252b5132 | 5189 | |
29b0f896 AM |
5190 | if (!quiet_warnings) |
5191 | { | |
5192 | if (!intel_syntax | |
40fb9820 L |
5193 | && (i.types[0].bitfield.jumpabsolute |
5194 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
5195 | { |
5196 | as_warn (_("indirect %s without `*'"), t->name); | |
5197 | } | |
5198 | ||
40fb9820 L |
5199 | if (t->opcode_modifier.isprefix |
5200 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
5201 | { |
5202 | /* Warn them that a data or address size prefix doesn't | |
5203 | affect assembly of the next line of code. */ | |
5204 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
5205 | } | |
5206 | } | |
5207 | ||
5208 | /* Copy the template we found. */ | |
5209 | i.tm = *t; | |
539e75ad L |
5210 | |
5211 | if (addr_prefix_disp != -1) | |
5212 | i.tm.operand_types[addr_prefix_disp] | |
5213 | = operand_types[addr_prefix_disp]; | |
5214 | ||
29b0f896 AM |
5215 | if (found_reverse_match) |
5216 | { | |
5217 | /* If we found a reverse match we must alter the opcode | |
5218 | direction bit. found_reverse_match holds bits to change | |
5219 | (different for int & float insns). */ | |
5220 | ||
5221 | i.tm.base_opcode ^= found_reverse_match; | |
5222 | ||
539e75ad L |
5223 | i.tm.operand_types[0] = operand_types[1]; |
5224 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
5225 | } |
5226 | ||
fa99fab2 | 5227 | return t; |
29b0f896 AM |
5228 | } |
5229 | ||
5230 | static int | |
e3bb37b5 | 5231 | check_string (void) |
29b0f896 | 5232 | { |
40fb9820 L |
5233 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
5234 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
5235 | { |
5236 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
5237 | { | |
a87af027 | 5238 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5239 | i.tm.name, |
a87af027 JB |
5240 | mem_op + 1, |
5241 | register_prefix); | |
29b0f896 AM |
5242 | return 0; |
5243 | } | |
5244 | /* There's only ever one segment override allowed per instruction. | |
5245 | This instruction possibly has a legal segment override on the | |
5246 | second operand, so copy the segment to where non-string | |
5247 | instructions store it, allowing common code. */ | |
5248 | i.seg[0] = i.seg[1]; | |
5249 | } | |
40fb9820 | 5250 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
5251 | { |
5252 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
5253 | { | |
a87af027 | 5254 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5255 | i.tm.name, |
a87af027 JB |
5256 | mem_op + 2, |
5257 | register_prefix); | |
29b0f896 AM |
5258 | return 0; |
5259 | } | |
5260 | } | |
5261 | return 1; | |
5262 | } | |
5263 | ||
5264 | static int | |
543613e9 | 5265 | process_suffix (void) |
29b0f896 AM |
5266 | { |
5267 | /* If matched instruction specifies an explicit instruction mnemonic | |
5268 | suffix, use it. */ | |
40fb9820 L |
5269 | if (i.tm.opcode_modifier.size16) |
5270 | i.suffix = WORD_MNEM_SUFFIX; | |
5271 | else if (i.tm.opcode_modifier.size32) | |
5272 | i.suffix = LONG_MNEM_SUFFIX; | |
5273 | else if (i.tm.opcode_modifier.size64) | |
5274 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
5275 | else if (i.reg_operands) |
5276 | { | |
5277 | /* If there's no instruction mnemonic suffix we try to invent one | |
5278 | based on register operands. */ | |
5279 | if (!i.suffix) | |
5280 | { | |
5281 | /* We take i.suffix from the last register operand specified, | |
5282 | Destination register type is more significant than source | |
381d071f L |
5283 | register type. crc32 in SSE4.2 prefers source register |
5284 | type. */ | |
5285 | if (i.tm.base_opcode == 0xf20f38f1) | |
5286 | { | |
40fb9820 L |
5287 | if (i.types[0].bitfield.reg16) |
5288 | i.suffix = WORD_MNEM_SUFFIX; | |
5289 | else if (i.types[0].bitfield.reg32) | |
5290 | i.suffix = LONG_MNEM_SUFFIX; | |
5291 | else if (i.types[0].bitfield.reg64) | |
5292 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 5293 | } |
9344ff29 | 5294 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 5295 | { |
40fb9820 | 5296 | if (i.types[0].bitfield.reg8) |
20592a94 L |
5297 | i.suffix = BYTE_MNEM_SUFFIX; |
5298 | } | |
381d071f L |
5299 | |
5300 | if (!i.suffix) | |
5301 | { | |
5302 | int op; | |
5303 | ||
20592a94 L |
5304 | if (i.tm.base_opcode == 0xf20f38f1 |
5305 | || i.tm.base_opcode == 0xf20f38f0) | |
5306 | { | |
5307 | /* We have to know the operand size for crc32. */ | |
5308 | as_bad (_("ambiguous memory operand size for `%s`"), | |
5309 | i.tm.name); | |
5310 | return 0; | |
5311 | } | |
5312 | ||
381d071f | 5313 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5314 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 5315 | { |
40fb9820 L |
5316 | if (i.types[op].bitfield.reg8) |
5317 | { | |
5318 | i.suffix = BYTE_MNEM_SUFFIX; | |
5319 | break; | |
5320 | } | |
5321 | else if (i.types[op].bitfield.reg16) | |
5322 | { | |
5323 | i.suffix = WORD_MNEM_SUFFIX; | |
5324 | break; | |
5325 | } | |
5326 | else if (i.types[op].bitfield.reg32) | |
5327 | { | |
5328 | i.suffix = LONG_MNEM_SUFFIX; | |
5329 | break; | |
5330 | } | |
5331 | else if (i.types[op].bitfield.reg64) | |
5332 | { | |
5333 | i.suffix = QWORD_MNEM_SUFFIX; | |
5334 | break; | |
5335 | } | |
381d071f L |
5336 | } |
5337 | } | |
29b0f896 AM |
5338 | } |
5339 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
5340 | { | |
2eb952a4 L |
5341 | if (intel_syntax |
5342 | && i.tm.opcode_modifier.ignoresize | |
5343 | && i.tm.opcode_modifier.no_bsuf) | |
5344 | i.suffix = 0; | |
5345 | else if (!check_byte_reg ()) | |
29b0f896 AM |
5346 | return 0; |
5347 | } | |
5348 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5349 | { | |
2eb952a4 L |
5350 | if (intel_syntax |
5351 | && i.tm.opcode_modifier.ignoresize | |
5352 | && i.tm.opcode_modifier.no_lsuf) | |
5353 | i.suffix = 0; | |
5354 | else if (!check_long_reg ()) | |
29b0f896 AM |
5355 | return 0; |
5356 | } | |
5357 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5358 | { | |
955e1e6a L |
5359 | if (intel_syntax |
5360 | && i.tm.opcode_modifier.ignoresize | |
5361 | && i.tm.opcode_modifier.no_qsuf) | |
5362 | i.suffix = 0; | |
5363 | else if (!check_qword_reg ()) | |
29b0f896 AM |
5364 | return 0; |
5365 | } | |
5366 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5367 | { | |
2eb952a4 L |
5368 | if (intel_syntax |
5369 | && i.tm.opcode_modifier.ignoresize | |
5370 | && i.tm.opcode_modifier.no_wsuf) | |
5371 | i.suffix = 0; | |
5372 | else if (!check_word_reg ()) | |
29b0f896 AM |
5373 | return 0; |
5374 | } | |
c0f3af97 | 5375 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
43234a1e L |
5376 | || i.suffix == YMMWORD_MNEM_SUFFIX |
5377 | || i.suffix == ZMMWORD_MNEM_SUFFIX) | |
582d5edd | 5378 | { |
43234a1e | 5379 | /* Skip if the instruction has x/y/z suffix. match_template |
582d5edd L |
5380 | should check if it is a valid suffix. */ |
5381 | } | |
40fb9820 | 5382 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
5383 | /* Do nothing if the instruction is going to ignore the prefix. */ |
5384 | ; | |
5385 | else | |
5386 | abort (); | |
5387 | } | |
40fb9820 | 5388 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
5389 | && !i.suffix |
5390 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 5391 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
5392 | { |
5393 | i.suffix = stackop_size; | |
5394 | } | |
9306ca4a JB |
5395 | else if (intel_syntax |
5396 | && !i.suffix | |
40fb9820 L |
5397 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
5398 | || i.tm.opcode_modifier.jumpbyte | |
5399 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
5400 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
5401 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
5402 | { |
5403 | switch (flag_code) | |
5404 | { | |
5405 | case CODE_64BIT: | |
40fb9820 | 5406 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
5407 | { |
5408 | i.suffix = QWORD_MNEM_SUFFIX; | |
5409 | break; | |
5410 | } | |
1a0670f3 | 5411 | /* Fall through. */ |
9306ca4a | 5412 | case CODE_32BIT: |
40fb9820 | 5413 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
5414 | i.suffix = LONG_MNEM_SUFFIX; |
5415 | break; | |
5416 | case CODE_16BIT: | |
40fb9820 | 5417 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
5418 | i.suffix = WORD_MNEM_SUFFIX; |
5419 | break; | |
5420 | } | |
5421 | } | |
252b5132 | 5422 | |
9306ca4a | 5423 | if (!i.suffix) |
29b0f896 | 5424 | { |
9306ca4a JB |
5425 | if (!intel_syntax) |
5426 | { | |
40fb9820 | 5427 | if (i.tm.opcode_modifier.w) |
9306ca4a | 5428 | { |
4eed87de AM |
5429 | as_bad (_("no instruction mnemonic suffix given and " |
5430 | "no register operands; can't size instruction")); | |
9306ca4a JB |
5431 | return 0; |
5432 | } | |
5433 | } | |
5434 | else | |
5435 | { | |
40fb9820 | 5436 | unsigned int suffixes; |
7ab9ffdd | 5437 | |
40fb9820 L |
5438 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
5439 | if (!i.tm.opcode_modifier.no_wsuf) | |
5440 | suffixes |= 1 << 1; | |
5441 | if (!i.tm.opcode_modifier.no_lsuf) | |
5442 | suffixes |= 1 << 2; | |
fc4adea1 | 5443 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
5444 | suffixes |= 1 << 3; |
5445 | if (!i.tm.opcode_modifier.no_ssuf) | |
5446 | suffixes |= 1 << 4; | |
5447 | if (!i.tm.opcode_modifier.no_qsuf) | |
5448 | suffixes |= 1 << 5; | |
5449 | ||
5450 | /* There are more than suffix matches. */ | |
5451 | if (i.tm.opcode_modifier.w | |
9306ca4a | 5452 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
5453 | && !i.tm.opcode_modifier.defaultsize |
5454 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
5455 | { |
5456 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
5457 | return 0; | |
5458 | } | |
5459 | } | |
29b0f896 | 5460 | } |
252b5132 | 5461 | |
9306ca4a JB |
5462 | /* Change the opcode based on the operand size given by i.suffix; |
5463 | We don't need to change things for byte insns. */ | |
5464 | ||
582d5edd L |
5465 | if (i.suffix |
5466 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 | 5467 | && i.suffix != XMMWORD_MNEM_SUFFIX |
43234a1e L |
5468 | && i.suffix != YMMWORD_MNEM_SUFFIX |
5469 | && i.suffix != ZMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
5470 | { |
5471 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 5472 | if (i.tm.opcode_modifier.w) |
29b0f896 | 5473 | { |
40fb9820 | 5474 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
5475 | i.tm.base_opcode |= 8; |
5476 | else | |
5477 | i.tm.base_opcode |= 1; | |
5478 | } | |
0f3f3d8b | 5479 | |
29b0f896 AM |
5480 | /* Now select between word & dword operations via the operand |
5481 | size prefix, except for instructions that will ignore this | |
5482 | prefix anyway. */ | |
ca61edf2 | 5483 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 5484 | { |
ca61edf2 L |
5485 | /* The address size override prefix changes the size of the |
5486 | first operand. */ | |
40fb9820 L |
5487 | if ((flag_code == CODE_32BIT |
5488 | && i.op->regs[0].reg_type.bitfield.reg16) | |
5489 | || (flag_code != CODE_32BIT | |
5490 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
5491 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
5492 | return 0; | |
5493 | } | |
5494 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
5495 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
5496 | && !i.tm.opcode_modifier.ignoresize |
5497 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
5498 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
5499 | || (flag_code == CODE_64BIT | |
40fb9820 | 5500 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
5501 | { |
5502 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 5503 | |
40fb9820 | 5504 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 5505 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 5506 | |
29b0f896 AM |
5507 | if (!add_prefix (prefix)) |
5508 | return 0; | |
24eab124 | 5509 | } |
252b5132 | 5510 | |
29b0f896 AM |
5511 | /* Set mode64 for an operand. */ |
5512 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 5513 | && flag_code == CODE_64BIT |
40fb9820 | 5514 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
5515 | { |
5516 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
5517 | need rex64. cmpxchg8b is also a special case. */ |
5518 | if (! (i.operands == 2 | |
5519 | && i.tm.base_opcode == 0x90 | |
5520 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
5521 | && operand_type_equal (&i.types [0], &acc64) |
5522 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
5523 | && ! (i.operands == 1 |
5524 | && i.tm.base_opcode == 0xfc7 | |
5525 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
5526 | && !operand_type_check (i.types [0], reg) |
5527 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 5528 | i.rex |= REX_W; |
46e883c5 | 5529 | } |
3e73aa7c | 5530 | |
29b0f896 AM |
5531 | /* Size floating point instruction. */ |
5532 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 5533 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 5534 | i.tm.base_opcode ^= 4; |
29b0f896 | 5535 | } |
7ecd2f8b | 5536 | |
29b0f896 AM |
5537 | return 1; |
5538 | } | |
3e73aa7c | 5539 | |
29b0f896 | 5540 | static int |
543613e9 | 5541 | check_byte_reg (void) |
29b0f896 AM |
5542 | { |
5543 | int op; | |
543613e9 | 5544 | |
29b0f896 AM |
5545 | for (op = i.operands; --op >= 0;) |
5546 | { | |
5547 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
5548 | 32 bit version of an eight bit register, we will just use the | |
5549 | low portion, and that's OK too. */ | |
40fb9820 | 5550 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
5551 | continue; |
5552 | ||
5a819eb9 JB |
5553 | /* I/O port address operands are OK too. */ |
5554 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
5555 | continue; | |
5556 | ||
9344ff29 L |
5557 | /* crc32 doesn't generate this warning. */ |
5558 | if (i.tm.base_opcode == 0xf20f38f0) | |
5559 | continue; | |
5560 | ||
40fb9820 L |
5561 | if ((i.types[op].bitfield.reg16 |
5562 | || i.types[op].bitfield.reg32 | |
5563 | || i.types[op].bitfield.reg64) | |
5a819eb9 JB |
5564 | && i.op[op].regs->reg_num < 4 |
5565 | /* Prohibit these changes in 64bit mode, since the lowering | |
5566 | would be more complicated. */ | |
5567 | && flag_code != CODE_64BIT) | |
29b0f896 | 5568 | { |
29b0f896 | 5569 | #if REGISTER_WARNINGS |
5a819eb9 | 5570 | if (!quiet_warnings) |
a540244d L |
5571 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5572 | register_prefix, | |
40fb9820 | 5573 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
5574 | ? REGNAM_AL - REGNAM_AX |
5575 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 5576 | register_prefix, |
29b0f896 AM |
5577 | i.op[op].regs->reg_name, |
5578 | i.suffix); | |
5579 | #endif | |
5580 | continue; | |
5581 | } | |
5582 | /* Any other register is bad. */ | |
40fb9820 L |
5583 | if (i.types[op].bitfield.reg16 |
5584 | || i.types[op].bitfield.reg32 | |
5585 | || i.types[op].bitfield.reg64 | |
5586 | || i.types[op].bitfield.regmmx | |
5587 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 5588 | || i.types[op].bitfield.regymm |
43234a1e | 5589 | || i.types[op].bitfield.regzmm |
40fb9820 L |
5590 | || i.types[op].bitfield.sreg2 |
5591 | || i.types[op].bitfield.sreg3 | |
5592 | || i.types[op].bitfield.control | |
5593 | || i.types[op].bitfield.debug | |
5594 | || i.types[op].bitfield.test | |
5595 | || i.types[op].bitfield.floatreg | |
5596 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 5597 | { |
a540244d L |
5598 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5599 | register_prefix, | |
29b0f896 AM |
5600 | i.op[op].regs->reg_name, |
5601 | i.tm.name, | |
5602 | i.suffix); | |
5603 | return 0; | |
5604 | } | |
5605 | } | |
5606 | return 1; | |
5607 | } | |
5608 | ||
5609 | static int | |
e3bb37b5 | 5610 | check_long_reg (void) |
29b0f896 AM |
5611 | { |
5612 | int op; | |
5613 | ||
5614 | for (op = i.operands; --op >= 0;) | |
5615 | /* Reject eight bit registers, except where the template requires | |
5616 | them. (eg. movzb) */ | |
40fb9820 L |
5617 | if (i.types[op].bitfield.reg8 |
5618 | && (i.tm.operand_types[op].bitfield.reg16 | |
5619 | || i.tm.operand_types[op].bitfield.reg32 | |
5620 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 5621 | { |
a540244d L |
5622 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5623 | register_prefix, | |
29b0f896 AM |
5624 | i.op[op].regs->reg_name, |
5625 | i.tm.name, | |
5626 | i.suffix); | |
5627 | return 0; | |
5628 | } | |
e4630f71 | 5629 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 5630 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
40fb9820 L |
5631 | && i.types[op].bitfield.reg16 |
5632 | && (i.tm.operand_types[op].bitfield.reg32 | |
5633 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
5634 | { |
5635 | /* Prohibit these changes in the 64bit mode, since the | |
5636 | lowering is more complicated. */ | |
5637 | if (flag_code == CODE_64BIT) | |
252b5132 | 5638 | { |
2b5d6a91 | 5639 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 5640 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
5641 | i.suffix); |
5642 | return 0; | |
252b5132 | 5643 | } |
29b0f896 | 5644 | #if REGISTER_WARNINGS |
cecf1424 JB |
5645 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5646 | register_prefix, | |
5647 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
5648 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 5649 | #endif |
252b5132 | 5650 | } |
e4630f71 | 5651 | /* Warn if the r prefix on a general reg is present. */ |
40fb9820 L |
5652 | else if (i.types[op].bitfield.reg64 |
5653 | && (i.tm.operand_types[op].bitfield.reg32 | |
5654 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 5655 | { |
34828aad | 5656 | if (intel_syntax |
ca61edf2 | 5657 | && i.tm.opcode_modifier.toqword |
40fb9820 | 5658 | && !i.types[0].bitfield.regxmm) |
34828aad | 5659 | { |
ca61edf2 | 5660 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
5661 | i.suffix = QWORD_MNEM_SUFFIX; |
5662 | } | |
5663 | else | |
5664 | { | |
2b5d6a91 | 5665 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
5666 | register_prefix, i.op[op].regs->reg_name, |
5667 | i.suffix); | |
5668 | return 0; | |
5669 | } | |
29b0f896 AM |
5670 | } |
5671 | return 1; | |
5672 | } | |
252b5132 | 5673 | |
29b0f896 | 5674 | static int |
e3bb37b5 | 5675 | check_qword_reg (void) |
29b0f896 AM |
5676 | { |
5677 | int op; | |
252b5132 | 5678 | |
29b0f896 AM |
5679 | for (op = i.operands; --op >= 0; ) |
5680 | /* Reject eight bit registers, except where the template requires | |
5681 | them. (eg. movzb) */ | |
40fb9820 L |
5682 | if (i.types[op].bitfield.reg8 |
5683 | && (i.tm.operand_types[op].bitfield.reg16 | |
5684 | || i.tm.operand_types[op].bitfield.reg32 | |
5685 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 5686 | { |
a540244d L |
5687 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5688 | register_prefix, | |
29b0f896 AM |
5689 | i.op[op].regs->reg_name, |
5690 | i.tm.name, | |
5691 | i.suffix); | |
5692 | return 0; | |
5693 | } | |
e4630f71 | 5694 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
5695 | else if ((i.types[op].bitfield.reg16 |
5696 | || i.types[op].bitfield.reg32) | |
33d0ab95 | 5697 | && (i.tm.operand_types[op].bitfield.reg64 |
40fb9820 | 5698 | || i.tm.operand_types[op].bitfield.acc)) |
29b0f896 AM |
5699 | { |
5700 | /* Prohibit these changes in the 64bit mode, since the | |
5701 | lowering is more complicated. */ | |
34828aad | 5702 | if (intel_syntax |
ca61edf2 | 5703 | && i.tm.opcode_modifier.todword |
40fb9820 | 5704 | && !i.types[0].bitfield.regxmm) |
34828aad | 5705 | { |
ca61edf2 | 5706 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
5707 | i.suffix = LONG_MNEM_SUFFIX; |
5708 | } | |
5709 | else | |
5710 | { | |
2b5d6a91 | 5711 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
5712 | register_prefix, i.op[op].regs->reg_name, |
5713 | i.suffix); | |
5714 | return 0; | |
5715 | } | |
252b5132 | 5716 | } |
29b0f896 AM |
5717 | return 1; |
5718 | } | |
252b5132 | 5719 | |
29b0f896 | 5720 | static int |
e3bb37b5 | 5721 | check_word_reg (void) |
29b0f896 AM |
5722 | { |
5723 | int op; | |
5724 | for (op = i.operands; --op >= 0;) | |
5725 | /* Reject eight bit registers, except where the template requires | |
5726 | them. (eg. movzb) */ | |
40fb9820 L |
5727 | if (i.types[op].bitfield.reg8 |
5728 | && (i.tm.operand_types[op].bitfield.reg16 | |
5729 | || i.tm.operand_types[op].bitfield.reg32 | |
5730 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 5731 | { |
a540244d L |
5732 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5733 | register_prefix, | |
29b0f896 AM |
5734 | i.op[op].regs->reg_name, |
5735 | i.tm.name, | |
5736 | i.suffix); | |
5737 | return 0; | |
5738 | } | |
e4630f71 | 5739 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 5740 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
e4630f71 JB |
5741 | && (i.types[op].bitfield.reg32 |
5742 | || i.types[op].bitfield.reg64) | |
40fb9820 L |
5743 | && (i.tm.operand_types[op].bitfield.reg16 |
5744 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 5745 | { |
29b0f896 AM |
5746 | /* Prohibit these changes in the 64bit mode, since the |
5747 | lowering is more complicated. */ | |
5748 | if (flag_code == CODE_64BIT) | |
252b5132 | 5749 | { |
2b5d6a91 | 5750 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 5751 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
5752 | i.suffix); |
5753 | return 0; | |
252b5132 | 5754 | } |
29b0f896 | 5755 | #if REGISTER_WARNINGS |
cecf1424 JB |
5756 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5757 | register_prefix, | |
5758 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
5759 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
5760 | #endif |
5761 | } | |
5762 | return 1; | |
5763 | } | |
252b5132 | 5764 | |
29b0f896 | 5765 | static int |
40fb9820 | 5766 | update_imm (unsigned int j) |
29b0f896 | 5767 | { |
bc0844ae | 5768 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
5769 | if ((overlap.bitfield.imm8 |
5770 | || overlap.bitfield.imm8s | |
5771 | || overlap.bitfield.imm16 | |
5772 | || overlap.bitfield.imm32 | |
5773 | || overlap.bitfield.imm32s | |
5774 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
5775 | && !operand_type_equal (&overlap, &imm8) |
5776 | && !operand_type_equal (&overlap, &imm8s) | |
5777 | && !operand_type_equal (&overlap, &imm16) | |
5778 | && !operand_type_equal (&overlap, &imm32) | |
5779 | && !operand_type_equal (&overlap, &imm32s) | |
5780 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
5781 | { |
5782 | if (i.suffix) | |
5783 | { | |
40fb9820 L |
5784 | i386_operand_type temp; |
5785 | ||
0dfbf9d7 | 5786 | operand_type_set (&temp, 0); |
7ab9ffdd | 5787 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
5788 | { |
5789 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
5790 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
5791 | } | |
5792 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5793 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
5794 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5795 | { | |
5796 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
5797 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
5798 | } | |
5799 | else | |
5800 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
5801 | overlap = temp; | |
29b0f896 | 5802 | } |
0dfbf9d7 L |
5803 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
5804 | || operand_type_equal (&overlap, &imm16_32) | |
5805 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 5806 | { |
40fb9820 | 5807 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 5808 | overlap = imm16; |
40fb9820 | 5809 | else |
65da13b5 | 5810 | overlap = imm32s; |
29b0f896 | 5811 | } |
0dfbf9d7 L |
5812 | if (!operand_type_equal (&overlap, &imm8) |
5813 | && !operand_type_equal (&overlap, &imm8s) | |
5814 | && !operand_type_equal (&overlap, &imm16) | |
5815 | && !operand_type_equal (&overlap, &imm32) | |
5816 | && !operand_type_equal (&overlap, &imm32s) | |
5817 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 5818 | { |
4eed87de AM |
5819 | as_bad (_("no instruction mnemonic suffix given; " |
5820 | "can't determine immediate size")); | |
29b0f896 AM |
5821 | return 0; |
5822 | } | |
5823 | } | |
40fb9820 | 5824 | i.types[j] = overlap; |
29b0f896 | 5825 | |
40fb9820 L |
5826 | return 1; |
5827 | } | |
5828 | ||
5829 | static int | |
5830 | finalize_imm (void) | |
5831 | { | |
bc0844ae | 5832 | unsigned int j, n; |
29b0f896 | 5833 | |
bc0844ae L |
5834 | /* Update the first 2 immediate operands. */ |
5835 | n = i.operands > 2 ? 2 : i.operands; | |
5836 | if (n) | |
5837 | { | |
5838 | for (j = 0; j < n; j++) | |
5839 | if (update_imm (j) == 0) | |
5840 | return 0; | |
40fb9820 | 5841 | |
bc0844ae L |
5842 | /* The 3rd operand can't be immediate operand. */ |
5843 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
5844 | } | |
29b0f896 AM |
5845 | |
5846 | return 1; | |
5847 | } | |
5848 | ||
c0f3af97 L |
5849 | static int |
5850 | bad_implicit_operand (int xmm) | |
5851 | { | |
91d6fa6a NC |
5852 | const char *ireg = xmm ? "xmm0" : "ymm0"; |
5853 | ||
c0f3af97 L |
5854 | if (intel_syntax) |
5855 | as_bad (_("the last operand of `%s' must be `%s%s'"), | |
91d6fa6a | 5856 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
5857 | else |
5858 | as_bad (_("the first operand of `%s' must be `%s%s'"), | |
91d6fa6a | 5859 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
5860 | return 0; |
5861 | } | |
5862 | ||
29b0f896 | 5863 | static int |
e3bb37b5 | 5864 | process_operands (void) |
29b0f896 AM |
5865 | { |
5866 | /* Default segment register this instruction will use for memory | |
5867 | accesses. 0 means unknown. This is only for optimizing out | |
5868 | unnecessary segment overrides. */ | |
5869 | const seg_entry *default_seg = 0; | |
5870 | ||
2426c15f | 5871 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 5872 | { |
91d6fa6a NC |
5873 | unsigned int dupl = i.operands; |
5874 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
5875 | unsigned int j; |
5876 | ||
c0f3af97 | 5877 | /* The destination must be an xmm register. */ |
9c2799c2 | 5878 | gas_assert (i.reg_operands |
91d6fa6a | 5879 | && MAX_OPERANDS > dupl |
7ab9ffdd | 5880 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 L |
5881 | |
5882 | if (i.tm.opcode_modifier.firstxmm0) | |
e2ec9d29 | 5883 | { |
c0f3af97 | 5884 | /* The first operand is implicit and must be xmm0. */ |
9c2799c2 | 5885 | gas_assert (operand_type_equal (&i.types[0], ®xmm)); |
4c692bc7 | 5886 | if (register_number (i.op[0].regs) != 0) |
c0f3af97 L |
5887 | return bad_implicit_operand (1); |
5888 | ||
8cd7925b | 5889 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
5890 | { |
5891 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
5892 | sources. */ | |
5893 | goto duplicate; | |
5894 | } | |
e2ec9d29 | 5895 | else |
c0f3af97 L |
5896 | { |
5897 | /* We remove the first xmm0 and keep the number of | |
5898 | operands unchanged, which in fact duplicates the | |
5899 | destination. */ | |
5900 | for (j = 1; j < i.operands; j++) | |
5901 | { | |
5902 | i.op[j - 1] = i.op[j]; | |
5903 | i.types[j - 1] = i.types[j]; | |
5904 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
5905 | } | |
5906 | } | |
5907 | } | |
5908 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 5909 | { |
91d6fa6a | 5910 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
5911 | && (i.tm.opcode_modifier.vexsources |
5912 | == VEX3SOURCES)); | |
c0f3af97 L |
5913 | |
5914 | /* Add the implicit xmm0 for instructions with VEX prefix | |
5915 | and 3 sources. */ | |
5916 | for (j = i.operands; j > 0; j--) | |
5917 | { | |
5918 | i.op[j] = i.op[j - 1]; | |
5919 | i.types[j] = i.types[j - 1]; | |
5920 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
5921 | } | |
5922 | i.op[0].regs | |
5923 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 5924 | i.types[0] = regxmm; |
c0f3af97 L |
5925 | i.tm.operand_types[0] = regxmm; |
5926 | ||
5927 | i.operands += 2; | |
5928 | i.reg_operands += 2; | |
5929 | i.tm.operands += 2; | |
5930 | ||
91d6fa6a | 5931 | dupl++; |
c0f3af97 | 5932 | dest++; |
91d6fa6a NC |
5933 | i.op[dupl] = i.op[dest]; |
5934 | i.types[dupl] = i.types[dest]; | |
5935 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 5936 | } |
c0f3af97 L |
5937 | else |
5938 | { | |
5939 | duplicate: | |
5940 | i.operands++; | |
5941 | i.reg_operands++; | |
5942 | i.tm.operands++; | |
5943 | ||
91d6fa6a NC |
5944 | i.op[dupl] = i.op[dest]; |
5945 | i.types[dupl] = i.types[dest]; | |
5946 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
5947 | } |
5948 | ||
5949 | if (i.tm.opcode_modifier.immext) | |
5950 | process_immext (); | |
5951 | } | |
5952 | else if (i.tm.opcode_modifier.firstxmm0) | |
5953 | { | |
5954 | unsigned int j; | |
5955 | ||
43234a1e | 5956 | /* The first operand is implicit and must be xmm0/ymm0/zmm0. */ |
9c2799c2 | 5957 | gas_assert (i.reg_operands |
7ab9ffdd | 5958 | && (operand_type_equal (&i.types[0], ®xmm) |
43234a1e L |
5959 | || operand_type_equal (&i.types[0], ®ymm) |
5960 | || operand_type_equal (&i.types[0], ®zmm))); | |
4c692bc7 | 5961 | if (register_number (i.op[0].regs) != 0) |
c0f3af97 | 5962 | return bad_implicit_operand (i.types[0].bitfield.regxmm); |
9fcfb3d7 L |
5963 | |
5964 | for (j = 1; j < i.operands; j++) | |
5965 | { | |
5966 | i.op[j - 1] = i.op[j]; | |
5967 | i.types[j - 1] = i.types[j]; | |
5968 | ||
5969 | /* We need to adjust fields in i.tm since they are used by | |
5970 | build_modrm_byte. */ | |
5971 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
5972 | } | |
5973 | ||
e2ec9d29 L |
5974 | i.operands--; |
5975 | i.reg_operands--; | |
e2ec9d29 L |
5976 | i.tm.operands--; |
5977 | } | |
920d2ddc IT |
5978 | else if (i.tm.opcode_modifier.implicitquadgroup) |
5979 | { | |
5980 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ | |
5981 | gas_assert (i.operands >= 2 | |
5982 | && (operand_type_equal (&i.types[1], ®xmm) | |
5983 | || operand_type_equal (&i.types[1], ®ymm) | |
5984 | || operand_type_equal (&i.types[1], ®zmm))); | |
5985 | unsigned int regnum = register_number (i.op[1].regs); | |
5986 | unsigned int first_reg_in_group = regnum & ~3; | |
5987 | unsigned int last_reg_in_group = first_reg_in_group + 3; | |
5988 | if (regnum != first_reg_in_group) { | |
5989 | as_warn (_("the second source register `%s%s' implicitly denotes" | |
5990 | " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"), | |
5991 | register_prefix, i.op[1].regs->reg_name, | |
5992 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
5993 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
5994 | i.tm.name); | |
5995 | } | |
5996 | } | |
e2ec9d29 L |
5997 | else if (i.tm.opcode_modifier.regkludge) |
5998 | { | |
5999 | /* The imul $imm, %reg instruction is converted into | |
6000 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6001 | is converted into xor %reg, %reg. */ | |
6002 | ||
6003 | unsigned int first_reg_op; | |
6004 | ||
6005 | if (operand_type_check (i.types[0], reg)) | |
6006 | first_reg_op = 0; | |
6007 | else | |
6008 | first_reg_op = 1; | |
6009 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6010 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6011 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6012 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6013 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6014 | i.operands++; | |
6015 | i.reg_operands++; | |
29b0f896 AM |
6016 | } |
6017 | ||
40fb9820 | 6018 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6019 | { |
40fb9820 L |
6020 | if (i.types[0].bitfield.sreg2 |
6021 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6022 | { |
4eed87de AM |
6023 | if (i.tm.base_opcode == POP_SEG_SHORT |
6024 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6025 | { |
a87af027 | 6026 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6027 | return 0; |
29b0f896 | 6028 | } |
4eed87de AM |
6029 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6030 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6031 | i.rex |= REX_B; |
4eed87de AM |
6032 | } |
6033 | else | |
6034 | { | |
7ab9ffdd | 6035 | /* The register or float register operand is in operand |
85f10a01 | 6036 | 0 or 1. */ |
40fb9820 | 6037 | unsigned int op; |
7ab9ffdd L |
6038 | |
6039 | if (i.types[0].bitfield.floatreg | |
6040 | || operand_type_check (i.types[0], reg)) | |
6041 | op = 0; | |
6042 | else | |
6043 | op = 1; | |
4eed87de AM |
6044 | /* Register goes in low 3 bits of opcode. */ |
6045 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6046 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6047 | i.rex |= REX_B; |
40fb9820 | 6048 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6049 | { |
4eed87de AM |
6050 | /* Warn about some common errors, but press on regardless. |
6051 | The first case can be generated by gcc (<= 2.8.1). */ | |
6052 | if (i.operands == 2) | |
6053 | { | |
6054 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6055 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6056 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6057 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6058 | } |
6059 | else | |
6060 | { | |
6061 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6062 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6063 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6064 | } |
29b0f896 AM |
6065 | } |
6066 | } | |
6067 | } | |
40fb9820 | 6068 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6069 | { |
6070 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6071 | must be put into the modrm byte). Now, we make the modrm and |
6072 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6073 | |
6074 | default_seg = build_modrm_byte (); | |
6075 | } | |
8a2ed489 | 6076 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6077 | { |
6078 | default_seg = &ds; | |
6079 | } | |
40fb9820 | 6080 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6081 | { |
6082 | /* For the string instructions that allow a segment override | |
6083 | on one of their operands, the default segment is ds. */ | |
6084 | default_seg = &ds; | |
6085 | } | |
6086 | ||
75178d9d L |
6087 | if (i.tm.base_opcode == 0x8d /* lea */ |
6088 | && i.seg[0] | |
6089 | && !quiet_warnings) | |
30123838 | 6090 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6091 | |
6092 | /* If a segment was explicitly specified, and the specified segment | |
6093 | is not the default, use an opcode prefix to select it. If we | |
6094 | never figured out what the default segment is, then default_seg | |
6095 | will be zero at this point, and the specified segment prefix will | |
6096 | always be used. */ | |
29b0f896 AM |
6097 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6098 | { | |
6099 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6100 | return 0; | |
6101 | } | |
6102 | return 1; | |
6103 | } | |
6104 | ||
6105 | static const seg_entry * | |
e3bb37b5 | 6106 | build_modrm_byte (void) |
29b0f896 AM |
6107 | { |
6108 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6109 | unsigned int source, dest; |
8cd7925b | 6110 | int vex_3_sources; |
c0f3af97 L |
6111 | |
6112 | /* The first operand of instructions with VEX prefix and 3 sources | |
6113 | must be VEX_Imm4. */ | |
8cd7925b | 6114 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6115 | if (vex_3_sources) |
6116 | { | |
91d6fa6a | 6117 | unsigned int nds, reg_slot; |
4c2c6516 | 6118 | expressionS *exp; |
c0f3af97 | 6119 | |
922d8de8 | 6120 | if (i.tm.opcode_modifier.veximmext |
a683cc34 SP |
6121 | && i.tm.opcode_modifier.immext) |
6122 | { | |
6123 | dest = i.operands - 2; | |
6124 | gas_assert (dest == 3); | |
6125 | } | |
922d8de8 | 6126 | else |
a683cc34 | 6127 | dest = i.operands - 1; |
c0f3af97 | 6128 | nds = dest - 1; |
922d8de8 | 6129 | |
a683cc34 SP |
6130 | /* There are 2 kinds of instructions: |
6131 | 1. 5 operands: 4 register operands or 3 register operands | |
6132 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
43234a1e L |
6133 | VexW0 or VexW1. The destination must be either XMM, YMM or |
6134 | ZMM register. | |
a683cc34 SP |
6135 | 2. 4 operands: 4 register operands or 3 register operands |
6136 | plus 1 memory operand, VexXDS, and VexImmExt */ | |
922d8de8 | 6137 | gas_assert ((i.reg_operands == 4 |
a683cc34 SP |
6138 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
6139 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
6140 | && (i.tm.opcode_modifier.veximmext | |
6141 | || (i.imm_operands == 1 | |
6142 | && i.types[0].bitfield.vec_imm4 | |
6143 | && (i.tm.opcode_modifier.vexw == VEXW0 | |
6144 | || i.tm.opcode_modifier.vexw == VEXW1) | |
6145 | && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) | |
43234a1e L |
6146 | || operand_type_equal (&i.tm.operand_types[dest], ®ymm) |
6147 | || operand_type_equal (&i.tm.operand_types[dest], ®zmm))))); | |
a683cc34 SP |
6148 | |
6149 | if (i.imm_operands == 0) | |
6150 | { | |
6151 | /* When there is no immediate operand, generate an 8bit | |
6152 | immediate operand to encode the first operand. */ | |
6153 | exp = &im_expressions[i.imm_operands++]; | |
6154 | i.op[i.operands].imms = exp; | |
6155 | i.types[i.operands] = imm8; | |
6156 | i.operands++; | |
6157 | /* If VexW1 is set, the first operand is the source and | |
6158 | the second operand is encoded in the immediate operand. */ | |
6159 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
6160 | { | |
6161 | source = 0; | |
6162 | reg_slot = 1; | |
6163 | } | |
6164 | else | |
6165 | { | |
6166 | source = 1; | |
6167 | reg_slot = 0; | |
6168 | } | |
6169 | ||
6170 | /* FMA swaps REG and NDS. */ | |
6171 | if (i.tm.cpu_flags.bitfield.cpufma) | |
6172 | { | |
6173 | unsigned int tmp; | |
6174 | tmp = reg_slot; | |
6175 | reg_slot = nds; | |
6176 | nds = tmp; | |
6177 | } | |
6178 | ||
24981e7b L |
6179 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
6180 | ®xmm) | |
a683cc34 | 6181 | || operand_type_equal (&i.tm.operand_types[reg_slot], |
43234a1e L |
6182 | ®ymm) |
6183 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
6184 | ®zmm)); | |
a683cc34 | 6185 | exp->X_op = O_constant; |
4c692bc7 | 6186 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
43234a1e L |
6187 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
6188 | } | |
922d8de8 | 6189 | else |
a683cc34 SP |
6190 | { |
6191 | unsigned int imm_slot; | |
6192 | ||
6193 | if (i.tm.opcode_modifier.vexw == VEXW0) | |
6194 | { | |
6195 | /* If VexW0 is set, the third operand is the source and | |
6196 | the second operand is encoded in the immediate | |
6197 | operand. */ | |
6198 | source = 2; | |
6199 | reg_slot = 1; | |
6200 | } | |
6201 | else | |
6202 | { | |
6203 | /* VexW1 is set, the second operand is the source and | |
6204 | the third operand is encoded in the immediate | |
6205 | operand. */ | |
6206 | source = 1; | |
6207 | reg_slot = 2; | |
6208 | } | |
6209 | ||
6210 | if (i.tm.opcode_modifier.immext) | |
6211 | { | |
33eaf5de | 6212 | /* When ImmExt is set, the immediate byte is the last |
a683cc34 SP |
6213 | operand. */ |
6214 | imm_slot = i.operands - 1; | |
6215 | source--; | |
6216 | reg_slot--; | |
6217 | } | |
6218 | else | |
6219 | { | |
6220 | imm_slot = 0; | |
6221 | ||
6222 | /* Turn on Imm8 so that output_imm will generate it. */ | |
6223 | i.types[imm_slot].bitfield.imm8 = 1; | |
6224 | } | |
6225 | ||
24981e7b L |
6226 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
6227 | ®xmm) | |
6228 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
43234a1e L |
6229 | ®ymm) |
6230 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
6231 | ®zmm)); | |
a683cc34 | 6232 | i.op[imm_slot].imms->X_add_number |
4c692bc7 | 6233 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 6234 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
a683cc34 SP |
6235 | } |
6236 | ||
6237 | gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) | |
6238 | || operand_type_equal (&i.tm.operand_types[nds], | |
43234a1e L |
6239 | ®ymm) |
6240 | || operand_type_equal (&i.tm.operand_types[nds], | |
6241 | ®zmm)); | |
dae39acc | 6242 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
6243 | } |
6244 | else | |
6245 | source = dest = 0; | |
29b0f896 AM |
6246 | |
6247 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
6248 | implicit registers do not count. If there are 3 register |
6249 | operands, it must be a instruction with VexNDS. For a | |
6250 | instruction with VexNDD, the destination register is encoded | |
6251 | in VEX prefix. If there are 4 register operands, it must be | |
6252 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
6253 | if (i.mem_operands == 0 |
6254 | && ((i.reg_operands == 2 | |
2426c15f | 6255 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 6256 | || (i.reg_operands == 3 |
2426c15f | 6257 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 6258 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 6259 | { |
cab737b9 L |
6260 | switch (i.operands) |
6261 | { | |
6262 | case 2: | |
6263 | source = 0; | |
6264 | break; | |
6265 | case 3: | |
c81128dc L |
6266 | /* When there are 3 operands, one of them may be immediate, |
6267 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
6268 | the first operand must be shift count register (cl) or it |
6269 | is an instruction with VexNDS. */ | |
9c2799c2 | 6270 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 6271 | || (i.imm_operands == 0 |
2426c15f | 6272 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 6273 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
6274 | if (operand_type_check (i.types[0], imm) |
6275 | || i.types[0].bitfield.shiftcount) | |
6276 | source = 1; | |
6277 | else | |
6278 | source = 0; | |
cab737b9 L |
6279 | break; |
6280 | case 4: | |
368d64cc L |
6281 | /* When there are 4 operands, the first two must be 8bit |
6282 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
6283 | one. |
6284 | ||
6285 | For instructions with VexNDS, if the first operand | |
6286 | an imm8, the source operand is the 2nd one. If the last | |
6287 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 6288 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
6289 | && i.types[0].bitfield.imm8 |
6290 | && i.types[1].bitfield.imm8) | |
2426c15f | 6291 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
6292 | && i.imm_operands == 1 |
6293 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
6294 | || i.types[i.operands - 1].bitfield.imm8 |
6295 | || i.rounding))); | |
9f2670f2 L |
6296 | if (i.imm_operands == 2) |
6297 | source = 2; | |
6298 | else | |
c0f3af97 L |
6299 | { |
6300 | if (i.types[0].bitfield.imm8) | |
6301 | source = 1; | |
6302 | else | |
6303 | source = 0; | |
6304 | } | |
c0f3af97 L |
6305 | break; |
6306 | case 5: | |
43234a1e L |
6307 | if (i.tm.opcode_modifier.evex) |
6308 | { | |
6309 | /* For EVEX instructions, when there are 5 operands, the | |
6310 | first one must be immediate operand. If the second one | |
6311 | is immediate operand, the source operand is the 3th | |
6312 | one. If the last one is immediate operand, the source | |
6313 | operand is the 2nd one. */ | |
6314 | gas_assert (i.imm_operands == 2 | |
6315 | && i.tm.opcode_modifier.sae | |
6316 | && operand_type_check (i.types[0], imm)); | |
6317 | if (operand_type_check (i.types[1], imm)) | |
6318 | source = 2; | |
6319 | else if (operand_type_check (i.types[4], imm)) | |
6320 | source = 1; | |
6321 | else | |
6322 | abort (); | |
6323 | } | |
cab737b9 L |
6324 | break; |
6325 | default: | |
6326 | abort (); | |
6327 | } | |
6328 | ||
c0f3af97 L |
6329 | if (!vex_3_sources) |
6330 | { | |
6331 | dest = source + 1; | |
6332 | ||
43234a1e L |
6333 | /* RC/SAE operand could be between DEST and SRC. That happens |
6334 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
6335 | register. */ | |
6336 | if (i.rounding && i.rounding->operand == (int) dest) | |
6337 | dest++; | |
6338 | ||
2426c15f | 6339 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 6340 | { |
43234a1e L |
6341 | /* For instructions with VexNDS, the register-only source |
6342 | operand must be 32/64bit integer, XMM, YMM or ZMM | |
6343 | register. It is encoded in VEX prefix. We need to | |
6344 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
6345 | |
6346 | i386_operand_type op; | |
6347 | unsigned int vvvv; | |
6348 | ||
6349 | /* Check register-only source operand when two source | |
6350 | operands are swapped. */ | |
6351 | if (!i.tm.operand_types[source].bitfield.baseindex | |
6352 | && i.tm.operand_types[dest].bitfield.baseindex) | |
6353 | { | |
6354 | vvvv = source; | |
6355 | source = dest; | |
6356 | } | |
6357 | else | |
6358 | vvvv = dest; | |
6359 | ||
6360 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 6361 | op.bitfield.regmem = 0; |
c0f3af97 | 6362 | if ((dest + 1) >= i.operands |
ac4eb736 AM |
6363 | || (!op.bitfield.reg32 |
6364 | && op.bitfield.reg64 | |
f12dc422 | 6365 | && !operand_type_equal (&op, ®xmm) |
43234a1e L |
6366 | && !operand_type_equal (&op, ®ymm) |
6367 | && !operand_type_equal (&op, ®zmm) | |
6368 | && !operand_type_equal (&op, ®mask))) | |
c0f3af97 | 6369 | abort (); |
f12dc422 | 6370 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
6371 | dest++; |
6372 | } | |
6373 | } | |
29b0f896 AM |
6374 | |
6375 | i.rm.mode = 3; | |
6376 | /* One of the register operands will be encoded in the i.tm.reg | |
6377 | field, the other in the combined i.tm.mode and i.tm.regmem | |
6378 | fields. If no form of this instruction supports a memory | |
6379 | destination operand, then we assume the source operand may | |
6380 | sometimes be a memory operand and so we need to store the | |
6381 | destination in the i.rm.reg field. */ | |
40fb9820 L |
6382 | if (!i.tm.operand_types[dest].bitfield.regmem |
6383 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
6384 | { |
6385 | i.rm.reg = i.op[dest].regs->reg_num; | |
6386 | i.rm.regmem = i.op[source].regs->reg_num; | |
6387 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6388 | i.rex |= REX_R; |
43234a1e L |
6389 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6390 | i.vrex |= REX_R; | |
29b0f896 | 6391 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6392 | i.rex |= REX_B; |
43234a1e L |
6393 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6394 | i.vrex |= REX_B; | |
29b0f896 AM |
6395 | } |
6396 | else | |
6397 | { | |
6398 | i.rm.reg = i.op[source].regs->reg_num; | |
6399 | i.rm.regmem = i.op[dest].regs->reg_num; | |
6400 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6401 | i.rex |= REX_B; |
43234a1e L |
6402 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6403 | i.vrex |= REX_B; | |
29b0f896 | 6404 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6405 | i.rex |= REX_R; |
43234a1e L |
6406 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6407 | i.vrex |= REX_R; | |
29b0f896 | 6408 | } |
161a04f6 | 6409 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 6410 | { |
40fb9820 L |
6411 | if (!i.types[0].bitfield.control |
6412 | && !i.types[1].bitfield.control) | |
c4a530c5 | 6413 | abort (); |
161a04f6 | 6414 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
6415 | add_prefix (LOCK_PREFIX_OPCODE); |
6416 | } | |
29b0f896 AM |
6417 | } |
6418 | else | |
6419 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
6420 | unsigned int mem; |
6421 | ||
29b0f896 AM |
6422 | if (i.mem_operands) |
6423 | { | |
6424 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 6425 | unsigned int op; |
4eed87de | 6426 | |
7ab9ffdd L |
6427 | for (op = 0; op < i.operands; op++) |
6428 | if (operand_type_check (i.types[op], anymem)) | |
6429 | break; | |
7ab9ffdd | 6430 | gas_assert (op < i.operands); |
29b0f896 | 6431 | |
6c30d220 L |
6432 | if (i.tm.opcode_modifier.vecsib) |
6433 | { | |
6434 | if (i.index_reg->reg_num == RegEiz | |
6435 | || i.index_reg->reg_num == RegRiz) | |
6436 | abort (); | |
6437 | ||
6438 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6439 | if (!i.base_reg) | |
6440 | { | |
6441 | i.sib.base = NO_BASE_REGISTER; | |
6442 | i.sib.scale = i.log2_scale_factor; | |
43234a1e L |
6443 | /* No Vec_Disp8 if there is no base. */ |
6444 | i.types[op].bitfield.vec_disp8 = 0; | |
6c30d220 L |
6445 | i.types[op].bitfield.disp8 = 0; |
6446 | i.types[op].bitfield.disp16 = 0; | |
6447 | i.types[op].bitfield.disp64 = 0; | |
6448 | if (flag_code != CODE_64BIT) | |
6449 | { | |
6450 | /* Must be 32 bit */ | |
6451 | i.types[op].bitfield.disp32 = 1; | |
6452 | i.types[op].bitfield.disp32s = 0; | |
6453 | } | |
6454 | else | |
6455 | { | |
6456 | i.types[op].bitfield.disp32 = 0; | |
6457 | i.types[op].bitfield.disp32s = 1; | |
6458 | } | |
6459 | } | |
6460 | i.sib.index = i.index_reg->reg_num; | |
6461 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
6462 | i.rex |= REX_X; | |
43234a1e L |
6463 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
6464 | i.vrex |= REX_X; | |
6c30d220 L |
6465 | } |
6466 | ||
29b0f896 AM |
6467 | default_seg = &ds; |
6468 | ||
6469 | if (i.base_reg == 0) | |
6470 | { | |
6471 | i.rm.mode = 0; | |
6472 | if (!i.disp_operands) | |
6c30d220 L |
6473 | { |
6474 | fake_zero_displacement = 1; | |
6475 | /* Instructions with VSIB byte need 32bit displacement | |
6476 | if there is no base register. */ | |
6477 | if (i.tm.opcode_modifier.vecsib) | |
6478 | i.types[op].bitfield.disp32 = 1; | |
6479 | } | |
29b0f896 AM |
6480 | if (i.index_reg == 0) |
6481 | { | |
6c30d220 | 6482 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6483 | /* Operand is just <disp> */ |
20f0a1fc | 6484 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
6485 | { |
6486 | /* 64bit mode overwrites the 32bit absolute | |
6487 | addressing by RIP relative addressing and | |
6488 | absolute addressing is encoded by one of the | |
6489 | redundant SIB forms. */ | |
6490 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6491 | i.sib.base = NO_BASE_REGISTER; | |
6492 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 6493 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 6494 | ? disp32s : disp32); |
20f0a1fc | 6495 | } |
fc225355 L |
6496 | else if ((flag_code == CODE_16BIT) |
6497 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
6498 | { |
6499 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 6500 | i.types[op] = disp16; |
20f0a1fc NC |
6501 | } |
6502 | else | |
6503 | { | |
6504 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 6505 | i.types[op] = disp32; |
29b0f896 AM |
6506 | } |
6507 | } | |
6c30d220 | 6508 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6509 | { |
6c30d220 | 6510 | /* !i.base_reg && i.index_reg */ |
db51cc60 L |
6511 | if (i.index_reg->reg_num == RegEiz |
6512 | || i.index_reg->reg_num == RegRiz) | |
6513 | i.sib.index = NO_INDEX_REGISTER; | |
6514 | else | |
6515 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6516 | i.sib.base = NO_BASE_REGISTER; |
6517 | i.sib.scale = i.log2_scale_factor; | |
6518 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
43234a1e L |
6519 | /* No Vec_Disp8 if there is no base. */ |
6520 | i.types[op].bitfield.vec_disp8 = 0; | |
40fb9820 L |
6521 | i.types[op].bitfield.disp8 = 0; |
6522 | i.types[op].bitfield.disp16 = 0; | |
6523 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 6524 | if (flag_code != CODE_64BIT) |
40fb9820 L |
6525 | { |
6526 | /* Must be 32 bit */ | |
6527 | i.types[op].bitfield.disp32 = 1; | |
6528 | i.types[op].bitfield.disp32s = 0; | |
6529 | } | |
29b0f896 | 6530 | else |
40fb9820 L |
6531 | { |
6532 | i.types[op].bitfield.disp32 = 0; | |
6533 | i.types[op].bitfield.disp32s = 1; | |
6534 | } | |
29b0f896 | 6535 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6536 | i.rex |= REX_X; |
29b0f896 AM |
6537 | } |
6538 | } | |
6539 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
6540 | else if (i.base_reg->reg_num == RegRip || |
6541 | i.base_reg->reg_num == RegEip) | |
29b0f896 | 6542 | { |
6c30d220 | 6543 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6544 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
6545 | i.types[op].bitfield.disp8 = 0; |
6546 | i.types[op].bitfield.disp16 = 0; | |
6547 | i.types[op].bitfield.disp32 = 0; | |
6548 | i.types[op].bitfield.disp32s = 1; | |
6549 | i.types[op].bitfield.disp64 = 0; | |
43234a1e | 6550 | i.types[op].bitfield.vec_disp8 = 0; |
71903a11 | 6551 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
6552 | if (! i.disp_operands) |
6553 | fake_zero_displacement = 1; | |
29b0f896 | 6554 | } |
40fb9820 | 6555 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 | 6556 | { |
6c30d220 | 6557 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6558 | switch (i.base_reg->reg_num) |
6559 | { | |
6560 | case 3: /* (%bx) */ | |
6561 | if (i.index_reg == 0) | |
6562 | i.rm.regmem = 7; | |
6563 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
6564 | i.rm.regmem = i.index_reg->reg_num - 6; | |
6565 | break; | |
6566 | case 5: /* (%bp) */ | |
6567 | default_seg = &ss; | |
6568 | if (i.index_reg == 0) | |
6569 | { | |
6570 | i.rm.regmem = 6; | |
40fb9820 | 6571 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
6572 | { |
6573 | /* fake (%bp) into 0(%bp) */ | |
43234a1e L |
6574 | if (i.tm.operand_types[op].bitfield.vec_disp8) |
6575 | i.types[op].bitfield.vec_disp8 = 1; | |
6576 | else | |
6577 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 6578 | fake_zero_displacement = 1; |
29b0f896 AM |
6579 | } |
6580 | } | |
6581 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
6582 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
6583 | break; | |
6584 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
6585 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
6586 | } | |
6587 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6588 | } | |
6589 | else /* i.base_reg and 32/64 bit mode */ | |
6590 | { | |
6591 | if (flag_code == CODE_64BIT | |
40fb9820 L |
6592 | && operand_type_check (i.types[op], disp)) |
6593 | { | |
6594 | i386_operand_type temp; | |
0dfbf9d7 | 6595 | operand_type_set (&temp, 0); |
40fb9820 | 6596 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
43234a1e L |
6597 | temp.bitfield.vec_disp8 |
6598 | = i.types[op].bitfield.vec_disp8; | |
40fb9820 L |
6599 | i.types[op] = temp; |
6600 | if (i.prefix[ADDR_PREFIX] == 0) | |
6601 | i.types[op].bitfield.disp32s = 1; | |
6602 | else | |
6603 | i.types[op].bitfield.disp32 = 1; | |
6604 | } | |
20f0a1fc | 6605 | |
6c30d220 L |
6606 | if (!i.tm.opcode_modifier.vecsib) |
6607 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 6608 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6609 | i.rex |= REX_B; |
29b0f896 AM |
6610 | i.sib.base = i.base_reg->reg_num; |
6611 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
6612 | complications. */ | |
848930b2 JB |
6613 | if (!(i.base_reg->reg_flags & RegRex) |
6614 | && (i.base_reg->reg_num == EBP_REG_NUM | |
6615 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 6616 | default_seg = &ss; |
848930b2 | 6617 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 6618 | { |
848930b2 | 6619 | fake_zero_displacement = 1; |
43234a1e L |
6620 | if (i.tm.operand_types [op].bitfield.vec_disp8) |
6621 | i.types[op].bitfield.vec_disp8 = 1; | |
6622 | else | |
6623 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
6624 | } |
6625 | i.sib.scale = i.log2_scale_factor; | |
6626 | if (i.index_reg == 0) | |
6627 | { | |
6c30d220 | 6628 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6629 | /* <disp>(%esp) becomes two byte modrm with no index |
6630 | register. We've already stored the code for esp | |
6631 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
6632 | Any base register besides %esp will not use the | |
6633 | extra modrm byte. */ | |
6634 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 6635 | } |
6c30d220 | 6636 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6637 | { |
db51cc60 L |
6638 | if (i.index_reg->reg_num == RegEiz |
6639 | || i.index_reg->reg_num == RegRiz) | |
6640 | i.sib.index = NO_INDEX_REGISTER; | |
6641 | else | |
6642 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6643 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
6644 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 6645 | i.rex |= REX_X; |
29b0f896 | 6646 | } |
67a4f2b7 AO |
6647 | |
6648 | if (i.disp_operands | |
6649 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
6650 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
6651 | i.rm.mode = 0; | |
6652 | else | |
a501d77e L |
6653 | { |
6654 | if (!fake_zero_displacement | |
6655 | && !i.disp_operands | |
6656 | && i.disp_encoding) | |
6657 | { | |
6658 | fake_zero_displacement = 1; | |
6659 | if (i.disp_encoding == disp_encoding_8bit) | |
6660 | i.types[op].bitfield.disp8 = 1; | |
6661 | else | |
6662 | i.types[op].bitfield.disp32 = 1; | |
6663 | } | |
6664 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6665 | } | |
29b0f896 | 6666 | } |
252b5132 | 6667 | |
29b0f896 AM |
6668 | if (fake_zero_displacement) |
6669 | { | |
6670 | /* Fakes a zero displacement assuming that i.types[op] | |
6671 | holds the correct displacement size. */ | |
6672 | expressionS *exp; | |
6673 | ||
9c2799c2 | 6674 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
6675 | exp = &disp_expressions[i.disp_operands++]; |
6676 | i.op[op].disps = exp; | |
6677 | exp->X_op = O_constant; | |
6678 | exp->X_add_number = 0; | |
6679 | exp->X_add_symbol = (symbolS *) 0; | |
6680 | exp->X_op_symbol = (symbolS *) 0; | |
6681 | } | |
c0f3af97 L |
6682 | |
6683 | mem = op; | |
29b0f896 | 6684 | } |
c0f3af97 L |
6685 | else |
6686 | mem = ~0; | |
252b5132 | 6687 | |
8c43a48b | 6688 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
6689 | { |
6690 | if (operand_type_check (i.types[0], imm)) | |
6691 | i.vex.register_specifier = NULL; | |
6692 | else | |
6693 | { | |
6694 | /* VEX.vvvv encodes one of the sources when the first | |
6695 | operand is not an immediate. */ | |
1ef99a7b | 6696 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
6697 | i.vex.register_specifier = i.op[0].regs; |
6698 | else | |
6699 | i.vex.register_specifier = i.op[1].regs; | |
6700 | } | |
6701 | ||
6702 | /* Destination is a XMM register encoded in the ModRM.reg | |
6703 | and VEX.R bit. */ | |
6704 | i.rm.reg = i.op[2].regs->reg_num; | |
6705 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
6706 | i.rex |= REX_R; | |
6707 | ||
6708 | /* ModRM.rm and VEX.B encodes the other source. */ | |
6709 | if (!i.mem_operands) | |
6710 | { | |
6711 | i.rm.mode = 3; | |
6712 | ||
1ef99a7b | 6713 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
6714 | i.rm.regmem = i.op[1].regs->reg_num; |
6715 | else | |
6716 | i.rm.regmem = i.op[0].regs->reg_num; | |
6717 | ||
6718 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
6719 | i.rex |= REX_B; | |
6720 | } | |
6721 | } | |
2426c15f | 6722 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
6723 | { |
6724 | i.vex.register_specifier = i.op[2].regs; | |
6725 | if (!i.mem_operands) | |
6726 | { | |
6727 | i.rm.mode = 3; | |
6728 | i.rm.regmem = i.op[1].regs->reg_num; | |
6729 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
6730 | i.rex |= REX_B; | |
6731 | } | |
6732 | } | |
29b0f896 AM |
6733 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
6734 | (if any) based on i.tm.extension_opcode. Again, we must be | |
6735 | careful to make sure that segment/control/debug/test/MMX | |
6736 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 6737 | else if (i.reg_operands) |
29b0f896 | 6738 | { |
99018f42 | 6739 | unsigned int op; |
7ab9ffdd L |
6740 | unsigned int vex_reg = ~0; |
6741 | ||
6742 | for (op = 0; op < i.operands; op++) | |
6743 | if (i.types[op].bitfield.reg8 | |
6744 | || i.types[op].bitfield.reg16 | |
6745 | || i.types[op].bitfield.reg32 | |
6746 | || i.types[op].bitfield.reg64 | |
6747 | || i.types[op].bitfield.regmmx | |
6748 | || i.types[op].bitfield.regxmm | |
6749 | || i.types[op].bitfield.regymm | |
7e8b059b | 6750 | || i.types[op].bitfield.regbnd |
43234a1e L |
6751 | || i.types[op].bitfield.regzmm |
6752 | || i.types[op].bitfield.regmask | |
7ab9ffdd L |
6753 | || i.types[op].bitfield.sreg2 |
6754 | || i.types[op].bitfield.sreg3 | |
6755 | || i.types[op].bitfield.control | |
6756 | || i.types[op].bitfield.debug | |
6757 | || i.types[op].bitfield.test) | |
6758 | break; | |
c0209578 | 6759 | |
7ab9ffdd L |
6760 | if (vex_3_sources) |
6761 | op = dest; | |
2426c15f | 6762 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
6763 | { |
6764 | /* For instructions with VexNDS, the register-only | |
6765 | source operand is encoded in VEX prefix. */ | |
6766 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 6767 | |
7ab9ffdd | 6768 | if (op > mem) |
c0f3af97 | 6769 | { |
7ab9ffdd L |
6770 | vex_reg = op++; |
6771 | gas_assert (op < i.operands); | |
c0f3af97 L |
6772 | } |
6773 | else | |
c0f3af97 | 6774 | { |
f12dc422 L |
6775 | /* Check register-only source operand when two source |
6776 | operands are swapped. */ | |
6777 | if (!i.tm.operand_types[op].bitfield.baseindex | |
6778 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
6779 | { | |
6780 | vex_reg = op; | |
6781 | op += 2; | |
6782 | gas_assert (mem == (vex_reg + 1) | |
6783 | && op < i.operands); | |
6784 | } | |
6785 | else | |
6786 | { | |
6787 | vex_reg = op + 1; | |
6788 | gas_assert (vex_reg < i.operands); | |
6789 | } | |
c0f3af97 | 6790 | } |
7ab9ffdd | 6791 | } |
2426c15f | 6792 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 6793 | { |
f12dc422 | 6794 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 6795 | is encoded in VEX prefix. */ |
f12dc422 L |
6796 | if (i.mem_operands == 0) |
6797 | { | |
6798 | /* There is no memory operand. */ | |
6799 | gas_assert ((op + 2) == i.operands); | |
6800 | vex_reg = op + 1; | |
6801 | } | |
6802 | else | |
8d63c93e | 6803 | { |
f12dc422 L |
6804 | /* There are only 2 operands. */ |
6805 | gas_assert (op < 2 && i.operands == 2); | |
6806 | vex_reg = 1; | |
6807 | } | |
7ab9ffdd L |
6808 | } |
6809 | else | |
6810 | gas_assert (op < i.operands); | |
99018f42 | 6811 | |
7ab9ffdd L |
6812 | if (vex_reg != (unsigned int) ~0) |
6813 | { | |
f12dc422 | 6814 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 6815 | |
f12dc422 L |
6816 | if (type->bitfield.reg32 != 1 |
6817 | && type->bitfield.reg64 != 1 | |
6818 | && !operand_type_equal (type, ®xmm) | |
43234a1e L |
6819 | && !operand_type_equal (type, ®ymm) |
6820 | && !operand_type_equal (type, ®zmm) | |
6821 | && !operand_type_equal (type, ®mask)) | |
7ab9ffdd | 6822 | abort (); |
f88c9eb0 | 6823 | |
7ab9ffdd L |
6824 | i.vex.register_specifier = i.op[vex_reg].regs; |
6825 | } | |
6826 | ||
1b9f0c97 L |
6827 | /* Don't set OP operand twice. */ |
6828 | if (vex_reg != op) | |
7ab9ffdd | 6829 | { |
1b9f0c97 L |
6830 | /* If there is an extension opcode to put here, the |
6831 | register number must be put into the regmem field. */ | |
6832 | if (i.tm.extension_opcode != None) | |
6833 | { | |
6834 | i.rm.regmem = i.op[op].regs->reg_num; | |
6835 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
6836 | i.rex |= REX_B; | |
43234a1e L |
6837 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
6838 | i.vrex |= REX_B; | |
1b9f0c97 L |
6839 | } |
6840 | else | |
6841 | { | |
6842 | i.rm.reg = i.op[op].regs->reg_num; | |
6843 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
6844 | i.rex |= REX_R; | |
43234a1e L |
6845 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
6846 | i.vrex |= REX_R; | |
1b9f0c97 | 6847 | } |
7ab9ffdd | 6848 | } |
252b5132 | 6849 | |
29b0f896 AM |
6850 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
6851 | must set it to 3 to indicate this is a register operand | |
6852 | in the regmem field. */ | |
6853 | if (!i.mem_operands) | |
6854 | i.rm.mode = 3; | |
6855 | } | |
252b5132 | 6856 | |
29b0f896 | 6857 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 6858 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
6859 | i.rm.reg = i.tm.extension_opcode; |
6860 | } | |
6861 | return default_seg; | |
6862 | } | |
252b5132 | 6863 | |
29b0f896 | 6864 | static void |
e3bb37b5 | 6865 | output_branch (void) |
29b0f896 AM |
6866 | { |
6867 | char *p; | |
f8a5c266 | 6868 | int size; |
29b0f896 AM |
6869 | int code16; |
6870 | int prefix; | |
6871 | relax_substateT subtype; | |
6872 | symbolS *sym; | |
6873 | offsetT off; | |
6874 | ||
f8a5c266 | 6875 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 6876 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
6877 | |
6878 | prefix = 0; | |
6879 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 6880 | { |
29b0f896 AM |
6881 | prefix = 1; |
6882 | i.prefixes -= 1; | |
6883 | code16 ^= CODE16; | |
252b5132 | 6884 | } |
29b0f896 AM |
6885 | /* Pentium4 branch hints. */ |
6886 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
6887 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 6888 | { |
29b0f896 AM |
6889 | prefix++; |
6890 | i.prefixes--; | |
6891 | } | |
6892 | if (i.prefix[REX_PREFIX] != 0) | |
6893 | { | |
6894 | prefix++; | |
6895 | i.prefixes--; | |
2f66722d AM |
6896 | } |
6897 | ||
7e8b059b L |
6898 | /* BND prefixed jump. */ |
6899 | if (i.prefix[BND_PREFIX] != 0) | |
6900 | { | |
6901 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
6902 | i.prefixes -= 1; | |
6903 | } | |
6904 | ||
29b0f896 AM |
6905 | if (i.prefixes != 0 && !intel_syntax) |
6906 | as_warn (_("skipping prefixes on this instruction")); | |
6907 | ||
6908 | /* It's always a symbol; End frag & setup for relax. | |
6909 | Make sure there is enough room in this frag for the largest | |
6910 | instruction we may generate in md_convert_frag. This is 2 | |
6911 | bytes for the opcode and room for the prefix and largest | |
6912 | displacement. */ | |
6913 | frag_grow (prefix + 2 + 4); | |
6914 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
6915 | p = frag_more (prefix + 1); | |
6916 | if (i.prefix[DATA_PREFIX] != 0) | |
6917 | *p++ = DATA_PREFIX_OPCODE; | |
6918 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
6919 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
6920 | *p++ = i.prefix[SEG_PREFIX]; | |
6921 | if (i.prefix[REX_PREFIX] != 0) | |
6922 | *p++ = i.prefix[REX_PREFIX]; | |
6923 | *p = i.tm.base_opcode; | |
6924 | ||
6925 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 6926 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 6927 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 6928 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 6929 | else |
f8a5c266 | 6930 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 6931 | subtype |= code16; |
3e73aa7c | 6932 | |
29b0f896 AM |
6933 | sym = i.op[0].disps->X_add_symbol; |
6934 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 6935 | |
29b0f896 AM |
6936 | if (i.op[0].disps->X_op != O_constant |
6937 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 6938 | { |
29b0f896 AM |
6939 | /* Handle complex expressions. */ |
6940 | sym = make_expr_symbol (i.op[0].disps); | |
6941 | off = 0; | |
6942 | } | |
3e73aa7c | 6943 | |
29b0f896 AM |
6944 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
6945 | Pass reloc in fr_var. */ | |
d258b828 | 6946 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 6947 | } |
3e73aa7c | 6948 | |
29b0f896 | 6949 | static void |
e3bb37b5 | 6950 | output_jump (void) |
29b0f896 AM |
6951 | { |
6952 | char *p; | |
6953 | int size; | |
3e02c1cc | 6954 | fixS *fixP; |
29b0f896 | 6955 | |
40fb9820 | 6956 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
6957 | { |
6958 | /* This is a loop or jecxz type instruction. */ | |
6959 | size = 1; | |
6960 | if (i.prefix[ADDR_PREFIX] != 0) | |
6961 | { | |
6962 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
6963 | i.prefixes -= 1; | |
6964 | } | |
6965 | /* Pentium4 branch hints. */ | |
6966 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
6967 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
6968 | { | |
6969 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
6970 | i.prefixes--; | |
3e73aa7c JH |
6971 | } |
6972 | } | |
29b0f896 AM |
6973 | else |
6974 | { | |
6975 | int code16; | |
3e73aa7c | 6976 | |
29b0f896 AM |
6977 | code16 = 0; |
6978 | if (flag_code == CODE_16BIT) | |
6979 | code16 = CODE16; | |
3e73aa7c | 6980 | |
29b0f896 AM |
6981 | if (i.prefix[DATA_PREFIX] != 0) |
6982 | { | |
6983 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
6984 | i.prefixes -= 1; | |
6985 | code16 ^= CODE16; | |
6986 | } | |
252b5132 | 6987 | |
29b0f896 AM |
6988 | size = 4; |
6989 | if (code16) | |
6990 | size = 2; | |
6991 | } | |
9fcc94b6 | 6992 | |
29b0f896 AM |
6993 | if (i.prefix[REX_PREFIX] != 0) |
6994 | { | |
6995 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
6996 | i.prefixes -= 1; | |
6997 | } | |
252b5132 | 6998 | |
7e8b059b L |
6999 | /* BND prefixed jump. */ |
7000 | if (i.prefix[BND_PREFIX] != 0) | |
7001 | { | |
7002 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7003 | i.prefixes -= 1; | |
7004 | } | |
7005 | ||
29b0f896 AM |
7006 | if (i.prefixes != 0 && !intel_syntax) |
7007 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7008 | |
42164a71 L |
7009 | p = frag_more (i.tm.opcode_length + size); |
7010 | switch (i.tm.opcode_length) | |
7011 | { | |
7012 | case 2: | |
7013 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7014 | /* Fall through. */ |
42164a71 L |
7015 | case 1: |
7016 | *p++ = i.tm.base_opcode; | |
7017 | break; | |
7018 | default: | |
7019 | abort (); | |
7020 | } | |
e0890092 | 7021 | |
3e02c1cc | 7022 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
d258b828 | 7023 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); |
3e02c1cc AM |
7024 | |
7025 | /* All jumps handled here are signed, but don't use a signed limit | |
7026 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7027 | 4G and 64k respectively. */ | |
7028 | if (size == 1) | |
7029 | fixP->fx_signed = 1; | |
29b0f896 | 7030 | } |
e0890092 | 7031 | |
29b0f896 | 7032 | static void |
e3bb37b5 | 7033 | output_interseg_jump (void) |
29b0f896 AM |
7034 | { |
7035 | char *p; | |
7036 | int size; | |
7037 | int prefix; | |
7038 | int code16; | |
252b5132 | 7039 | |
29b0f896 AM |
7040 | code16 = 0; |
7041 | if (flag_code == CODE_16BIT) | |
7042 | code16 = CODE16; | |
a217f122 | 7043 | |
29b0f896 AM |
7044 | prefix = 0; |
7045 | if (i.prefix[DATA_PREFIX] != 0) | |
7046 | { | |
7047 | prefix = 1; | |
7048 | i.prefixes -= 1; | |
7049 | code16 ^= CODE16; | |
7050 | } | |
7051 | if (i.prefix[REX_PREFIX] != 0) | |
7052 | { | |
7053 | prefix++; | |
7054 | i.prefixes -= 1; | |
7055 | } | |
252b5132 | 7056 | |
29b0f896 AM |
7057 | size = 4; |
7058 | if (code16) | |
7059 | size = 2; | |
252b5132 | 7060 | |
29b0f896 AM |
7061 | if (i.prefixes != 0 && !intel_syntax) |
7062 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7063 | |
29b0f896 AM |
7064 | /* 1 opcode; 2 segment; offset */ |
7065 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7066 | |
29b0f896 AM |
7067 | if (i.prefix[DATA_PREFIX] != 0) |
7068 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7069 | |
29b0f896 AM |
7070 | if (i.prefix[REX_PREFIX] != 0) |
7071 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7072 | |
29b0f896 AM |
7073 | *p++ = i.tm.base_opcode; |
7074 | if (i.op[1].imms->X_op == O_constant) | |
7075 | { | |
7076 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7077 | |
29b0f896 AM |
7078 | if (size == 2 |
7079 | && !fits_in_unsigned_word (n) | |
7080 | && !fits_in_signed_word (n)) | |
7081 | { | |
7082 | as_bad (_("16-bit jump out of range")); | |
7083 | return; | |
7084 | } | |
7085 | md_number_to_chars (p, n, size); | |
7086 | } | |
7087 | else | |
7088 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7089 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7090 | if (i.op[0].imms->X_op != O_constant) |
7091 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7092 | i.tm.name); | |
7093 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7094 | } | |
a217f122 | 7095 | |
29b0f896 | 7096 | static void |
e3bb37b5 | 7097 | output_insn (void) |
29b0f896 | 7098 | { |
2bbd9c25 JJ |
7099 | fragS *insn_start_frag; |
7100 | offsetT insn_start_off; | |
7101 | ||
29b0f896 AM |
7102 | /* Tie dwarf2 debug info to the address at the start of the insn. |
7103 | We can't do this after the insn has been output as the current | |
7104 | frag may have been closed off. eg. by frag_var. */ | |
7105 | dwarf2_emit_insn (0); | |
7106 | ||
2bbd9c25 JJ |
7107 | insn_start_frag = frag_now; |
7108 | insn_start_off = frag_now_fix (); | |
7109 | ||
29b0f896 | 7110 | /* Output jumps. */ |
40fb9820 | 7111 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 7112 | output_branch (); |
40fb9820 L |
7113 | else if (i.tm.opcode_modifier.jumpbyte |
7114 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 7115 | output_jump (); |
40fb9820 | 7116 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
7117 | output_interseg_jump (); |
7118 | else | |
7119 | { | |
7120 | /* Output normal instructions here. */ | |
7121 | char *p; | |
7122 | unsigned char *q; | |
47465058 | 7123 | unsigned int j; |
331d2d0d | 7124 | unsigned int prefix; |
4dffcebc | 7125 | |
e4e00185 AS |
7126 | if (avoid_fence |
7127 | && i.tm.base_opcode == 0xfae | |
7128 | && i.operands == 1 | |
7129 | && i.imm_operands == 1 | |
7130 | && (i.op[0].imms->X_add_number == 0xe8 | |
7131 | || i.op[0].imms->X_add_number == 0xf0 | |
7132 | || i.op[0].imms->X_add_number == 0xf8)) | |
7133 | { | |
7134 | /* Encode lfence, mfence, and sfence as | |
7135 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
7136 | offsetT val = 0x240483f0ULL; | |
7137 | p = frag_more (5); | |
7138 | md_number_to_chars (p, val, 5); | |
7139 | return; | |
7140 | } | |
7141 | ||
d022bddd IT |
7142 | /* Some processors fail on LOCK prefix. This options makes |
7143 | assembler ignore LOCK prefix and serves as a workaround. */ | |
7144 | if (omit_lock_prefix) | |
7145 | { | |
7146 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
7147 | return; | |
7148 | i.prefix[LOCK_PREFIX] = 0; | |
7149 | } | |
7150 | ||
43234a1e L |
7151 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
7152 | don't need the explicit prefix. */ | |
7153 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 7154 | { |
c0f3af97 | 7155 | switch (i.tm.opcode_length) |
bc4bd9ab | 7156 | { |
c0f3af97 L |
7157 | case 3: |
7158 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 7159 | { |
c0f3af97 L |
7160 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
7161 | goto check_prefix; | |
7162 | } | |
7163 | break; | |
7164 | case 2: | |
7165 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
7166 | { | |
7167 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
7168 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
7169 | { | |
4dffcebc | 7170 | check_prefix: |
c0f3af97 | 7171 | if (prefix != REPE_PREFIX_OPCODE |
c32fa91d | 7172 | || (i.prefix[REP_PREFIX] |
c0f3af97 L |
7173 | != REPE_PREFIX_OPCODE)) |
7174 | add_prefix (prefix); | |
7175 | } | |
7176 | else | |
4dffcebc L |
7177 | add_prefix (prefix); |
7178 | } | |
c0f3af97 L |
7179 | break; |
7180 | case 1: | |
7181 | break; | |
7182 | default: | |
7183 | abort (); | |
bc4bd9ab | 7184 | } |
c0f3af97 | 7185 | |
6d19a37a | 7186 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
7187 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
7188 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
7189 | perform IE->LE optimization. */ | |
7190 | if (x86_elf_abi == X86_64_X32_ABI | |
7191 | && i.operands == 2 | |
7192 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
7193 | && i.prefix[REX_PREFIX] == 0) | |
7194 | add_prefix (REX_OPCODE); | |
6d19a37a | 7195 | #endif |
cf61b747 | 7196 | |
c0f3af97 L |
7197 | /* The prefix bytes. */ |
7198 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
7199 | if (*q) | |
7200 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 7201 | } |
ae5c1c7b | 7202 | else |
c0f3af97 L |
7203 | { |
7204 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
7205 | if (*q) | |
7206 | switch (j) | |
7207 | { | |
7208 | case REX_PREFIX: | |
7209 | /* REX byte is encoded in VEX prefix. */ | |
7210 | break; | |
7211 | case SEG_PREFIX: | |
7212 | case ADDR_PREFIX: | |
7213 | FRAG_APPEND_1_CHAR (*q); | |
7214 | break; | |
7215 | default: | |
7216 | /* There should be no other prefixes for instructions | |
7217 | with VEX prefix. */ | |
7218 | abort (); | |
7219 | } | |
7220 | ||
43234a1e L |
7221 | /* For EVEX instructions i.vrex should become 0 after |
7222 | build_evex_prefix. For VEX instructions upper 16 registers | |
7223 | aren't available, so VREX should be 0. */ | |
7224 | if (i.vrex) | |
7225 | abort (); | |
c0f3af97 L |
7226 | /* Now the VEX prefix. */ |
7227 | p = frag_more (i.vex.length); | |
7228 | for (j = 0; j < i.vex.length; j++) | |
7229 | p[j] = i.vex.bytes[j]; | |
7230 | } | |
252b5132 | 7231 | |
29b0f896 | 7232 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 7233 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
7234 | { |
7235 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
7236 | } | |
7237 | else | |
7238 | { | |
4dffcebc | 7239 | switch (i.tm.opcode_length) |
331d2d0d | 7240 | { |
43234a1e L |
7241 | case 4: |
7242 | p = frag_more (4); | |
7243 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
7244 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
7245 | break; | |
4dffcebc | 7246 | case 3: |
331d2d0d L |
7247 | p = frag_more (3); |
7248 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
7249 | break; |
7250 | case 2: | |
7251 | p = frag_more (2); | |
7252 | break; | |
7253 | default: | |
7254 | abort (); | |
7255 | break; | |
331d2d0d | 7256 | } |
0f10071e | 7257 | |
29b0f896 AM |
7258 | /* Put out high byte first: can't use md_number_to_chars! */ |
7259 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
7260 | *p = i.tm.base_opcode & 0xff; | |
7261 | } | |
3e73aa7c | 7262 | |
29b0f896 | 7263 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 7264 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 7265 | { |
4a3523fa L |
7266 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
7267 | | i.rm.reg << 3 | |
7268 | | i.rm.mode << 6)); | |
29b0f896 AM |
7269 | /* If i.rm.regmem == ESP (4) |
7270 | && i.rm.mode != (Register mode) | |
7271 | && not 16 bit | |
7272 | ==> need second modrm byte. */ | |
7273 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
7274 | && i.rm.mode != 3 | |
40fb9820 | 7275 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
7276 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
7277 | | i.sib.index << 3 | |
7278 | | i.sib.scale << 6)); | |
29b0f896 | 7279 | } |
3e73aa7c | 7280 | |
29b0f896 | 7281 | if (i.disp_operands) |
2bbd9c25 | 7282 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 7283 | |
29b0f896 | 7284 | if (i.imm_operands) |
2bbd9c25 | 7285 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 7286 | } |
252b5132 | 7287 | |
29b0f896 AM |
7288 | #ifdef DEBUG386 |
7289 | if (flag_debug) | |
7290 | { | |
7b81dfbb | 7291 | pi ("" /*line*/, &i); |
29b0f896 AM |
7292 | } |
7293 | #endif /* DEBUG386 */ | |
7294 | } | |
252b5132 | 7295 | |
e205caa7 L |
7296 | /* Return the size of the displacement operand N. */ |
7297 | ||
7298 | static int | |
7299 | disp_size (unsigned int n) | |
7300 | { | |
7301 | int size = 4; | |
43234a1e L |
7302 | |
7303 | /* Vec_Disp8 has to be 8bit. */ | |
7304 | if (i.types[n].bitfield.vec_disp8) | |
7305 | size = 1; | |
7306 | else if (i.types[n].bitfield.disp64) | |
40fb9820 L |
7307 | size = 8; |
7308 | else if (i.types[n].bitfield.disp8) | |
7309 | size = 1; | |
7310 | else if (i.types[n].bitfield.disp16) | |
7311 | size = 2; | |
e205caa7 L |
7312 | return size; |
7313 | } | |
7314 | ||
7315 | /* Return the size of the immediate operand N. */ | |
7316 | ||
7317 | static int | |
7318 | imm_size (unsigned int n) | |
7319 | { | |
7320 | int size = 4; | |
40fb9820 L |
7321 | if (i.types[n].bitfield.imm64) |
7322 | size = 8; | |
7323 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
7324 | size = 1; | |
7325 | else if (i.types[n].bitfield.imm16) | |
7326 | size = 2; | |
e205caa7 L |
7327 | return size; |
7328 | } | |
7329 | ||
29b0f896 | 7330 | static void |
64e74474 | 7331 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7332 | { |
7333 | char *p; | |
7334 | unsigned int n; | |
252b5132 | 7335 | |
29b0f896 AM |
7336 | for (n = 0; n < i.operands; n++) |
7337 | { | |
43234a1e L |
7338 | if (i.types[n].bitfield.vec_disp8 |
7339 | || operand_type_check (i.types[n], disp)) | |
29b0f896 AM |
7340 | { |
7341 | if (i.op[n].disps->X_op == O_constant) | |
7342 | { | |
e205caa7 | 7343 | int size = disp_size (n); |
43234a1e | 7344 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 7345 | |
43234a1e L |
7346 | if (i.types[n].bitfield.vec_disp8) |
7347 | val >>= i.memshift; | |
7348 | val = offset_in_range (val, size); | |
29b0f896 AM |
7349 | p = frag_more (size); |
7350 | md_number_to_chars (p, val, size); | |
7351 | } | |
7352 | else | |
7353 | { | |
f86103b7 | 7354 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 7355 | int size = disp_size (n); |
40fb9820 | 7356 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 7357 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 7358 | fixS *fixP; |
29b0f896 | 7359 | |
e205caa7 | 7360 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 7361 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 7362 | |
29b0f896 AM |
7363 | /* The PC relative address is computed relative |
7364 | to the instruction boundary, so in case immediate | |
7365 | fields follows, we need to adjust the value. */ | |
7366 | if (pcrel && i.imm_operands) | |
7367 | { | |
29b0f896 | 7368 | unsigned int n1; |
e205caa7 | 7369 | int sz = 0; |
252b5132 | 7370 | |
29b0f896 | 7371 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 7372 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 7373 | { |
e205caa7 L |
7374 | /* Only one immediate is allowed for PC |
7375 | relative address. */ | |
9c2799c2 | 7376 | gas_assert (sz == 0); |
e205caa7 L |
7377 | sz = imm_size (n1); |
7378 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 7379 | } |
29b0f896 | 7380 | /* We should find the immediate. */ |
9c2799c2 | 7381 | gas_assert (sz != 0); |
29b0f896 | 7382 | } |
520dc8e8 | 7383 | |
29b0f896 | 7384 | p = frag_more (size); |
d258b828 | 7385 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 7386 | if (GOT_symbol |
2bbd9c25 | 7387 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 7388 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7389 | || reloc_type == BFD_RELOC_X86_64_32S |
7390 | || (reloc_type == BFD_RELOC_64 | |
7391 | && object_64bit)) | |
d6ab8113 JB |
7392 | && (i.op[n].disps->X_op == O_symbol |
7393 | || (i.op[n].disps->X_op == O_add | |
7394 | && ((symbol_get_value_expression | |
7395 | (i.op[n].disps->X_op_symbol)->X_op) | |
7396 | == O_subtract)))) | |
7397 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
7398 | { |
7399 | offsetT add; | |
7400 | ||
7401 | if (insn_start_frag == frag_now) | |
7402 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7403 | else | |
7404 | { | |
7405 | fragS *fr; | |
7406 | ||
7407 | add = insn_start_frag->fr_fix - insn_start_off; | |
7408 | for (fr = insn_start_frag->fr_next; | |
7409 | fr && fr != frag_now; fr = fr->fr_next) | |
7410 | add += fr->fr_fix; | |
7411 | add += p - frag_now->fr_literal; | |
7412 | } | |
7413 | ||
4fa24527 | 7414 | if (!object_64bit) |
7b81dfbb AJ |
7415 | { |
7416 | reloc_type = BFD_RELOC_386_GOTPC; | |
7417 | i.op[n].imms->X_add_number += add; | |
7418 | } | |
7419 | else if (reloc_type == BFD_RELOC_64) | |
7420 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 7421 | else |
7b81dfbb AJ |
7422 | /* Don't do the adjustment for x86-64, as there |
7423 | the pcrel addressing is relative to the _next_ | |
7424 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 7425 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 7426 | } |
02a86693 L |
7427 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
7428 | size, i.op[n].disps, pcrel, | |
7429 | reloc_type); | |
7430 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
7431 | "test %reg, mem" and "binop mem, %reg" where binop | |
7432 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
0cb4071e L |
7433 | instructions. Always generate R_386_GOT32X for |
7434 | "sym*GOT" operand in 32-bit mode. */ | |
7435 | if ((generate_relax_relocations | |
7436 | || (!object_64bit | |
7437 | && i.rm.mode == 0 | |
7438 | && i.rm.regmem == 5)) | |
7439 | && (i.rm.mode == 2 | |
7440 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
7441 | && ((i.operands == 1 |
7442 | && i.tm.base_opcode == 0xff | |
7443 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
7444 | || (i.operands == 2 | |
7445 | && (i.tm.base_opcode == 0x8b | |
7446 | || i.tm.base_opcode == 0x85 | |
7447 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
7448 | { | |
7449 | if (object_64bit) | |
7450 | { | |
7451 | fixP->fx_tcbit = i.rex != 0; | |
7452 | if (i.base_reg | |
7453 | && (i.base_reg->reg_num == RegRip | |
7454 | || i.base_reg->reg_num == RegEip)) | |
7455 | fixP->fx_tcbit2 = 1; | |
7456 | } | |
7457 | else | |
7458 | fixP->fx_tcbit2 = 1; | |
7459 | } | |
29b0f896 AM |
7460 | } |
7461 | } | |
7462 | } | |
7463 | } | |
252b5132 | 7464 | |
29b0f896 | 7465 | static void |
64e74474 | 7466 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7467 | { |
7468 | char *p; | |
7469 | unsigned int n; | |
252b5132 | 7470 | |
29b0f896 AM |
7471 | for (n = 0; n < i.operands; n++) |
7472 | { | |
43234a1e L |
7473 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
7474 | if (i.rounding && (int) n == i.rounding->operand) | |
7475 | continue; | |
7476 | ||
40fb9820 | 7477 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
7478 | { |
7479 | if (i.op[n].imms->X_op == O_constant) | |
7480 | { | |
e205caa7 | 7481 | int size = imm_size (n); |
29b0f896 | 7482 | offsetT val; |
b4cac588 | 7483 | |
29b0f896 AM |
7484 | val = offset_in_range (i.op[n].imms->X_add_number, |
7485 | size); | |
7486 | p = frag_more (size); | |
7487 | md_number_to_chars (p, val, size); | |
7488 | } | |
7489 | else | |
7490 | { | |
7491 | /* Not absolute_section. | |
7492 | Need a 32-bit fixup (don't support 8bit | |
7493 | non-absolute imms). Try to support other | |
7494 | sizes ... */ | |
f86103b7 | 7495 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
7496 | int size = imm_size (n); |
7497 | int sign; | |
29b0f896 | 7498 | |
40fb9820 | 7499 | if (i.types[n].bitfield.imm32s |
a7d61044 | 7500 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 7501 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 7502 | sign = 1; |
e205caa7 L |
7503 | else |
7504 | sign = 0; | |
520dc8e8 | 7505 | |
29b0f896 | 7506 | p = frag_more (size); |
d258b828 | 7507 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 7508 | |
2bbd9c25 JJ |
7509 | /* This is tough to explain. We end up with this one if we |
7510 | * have operands that look like | |
7511 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
7512 | * obtain the absolute address of the GOT, and it is strongly | |
7513 | * preferable from a performance point of view to avoid using | |
7514 | * a runtime relocation for this. The actual sequence of | |
7515 | * instructions often look something like: | |
7516 | * | |
7517 | * call .L66 | |
7518 | * .L66: | |
7519 | * popl %ebx | |
7520 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
7521 | * | |
7522 | * The call and pop essentially return the absolute address | |
7523 | * of the label .L66 and store it in %ebx. The linker itself | |
7524 | * will ultimately change the first operand of the addl so | |
7525 | * that %ebx points to the GOT, but to keep things simple, the | |
7526 | * .o file must have this operand set so that it generates not | |
7527 | * the absolute address of .L66, but the absolute address of | |
7528 | * itself. This allows the linker itself simply treat a GOTPC | |
7529 | * relocation as asking for a pcrel offset to the GOT to be | |
7530 | * added in, and the addend of the relocation is stored in the | |
7531 | * operand field for the instruction itself. | |
7532 | * | |
7533 | * Our job here is to fix the operand so that it would add | |
7534 | * the correct offset so that %ebx would point to itself. The | |
7535 | * thing that is tricky is that .-.L66 will point to the | |
7536 | * beginning of the instruction, so we need to further modify | |
7537 | * the operand so that it will point to itself. There are | |
7538 | * other cases where you have something like: | |
7539 | * | |
7540 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
7541 | * | |
7542 | * and here no correction would be required. Internally in | |
7543 | * the assembler we treat operands of this form as not being | |
7544 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
7545 | * whether it would simplify matters to do it this way. Who | |
7546 | * knows. In earlier versions of the PIC patches, the | |
7547 | * pcrel_adjust field was used to store the correction, but | |
7548 | * since the expression is not pcrel, I felt it would be | |
7549 | * confusing to do it this way. */ | |
7550 | ||
d6ab8113 | 7551 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7552 | || reloc_type == BFD_RELOC_X86_64_32S |
7553 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
7554 | && GOT_symbol |
7555 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
7556 | && (i.op[n].imms->X_op == O_symbol | |
7557 | || (i.op[n].imms->X_op == O_add | |
7558 | && ((symbol_get_value_expression | |
7559 | (i.op[n].imms->X_op_symbol)->X_op) | |
7560 | == O_subtract)))) | |
7561 | { | |
2bbd9c25 JJ |
7562 | offsetT add; |
7563 | ||
7564 | if (insn_start_frag == frag_now) | |
7565 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7566 | else | |
7567 | { | |
7568 | fragS *fr; | |
7569 | ||
7570 | add = insn_start_frag->fr_fix - insn_start_off; | |
7571 | for (fr = insn_start_frag->fr_next; | |
7572 | fr && fr != frag_now; fr = fr->fr_next) | |
7573 | add += fr->fr_fix; | |
7574 | add += p - frag_now->fr_literal; | |
7575 | } | |
7576 | ||
4fa24527 | 7577 | if (!object_64bit) |
d6ab8113 | 7578 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 7579 | else if (size == 4) |
d6ab8113 | 7580 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
7581 | else if (size == 8) |
7582 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 7583 | i.op[n].imms->X_add_number += add; |
29b0f896 | 7584 | } |
29b0f896 AM |
7585 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
7586 | i.op[n].imms, 0, reloc_type); | |
7587 | } | |
7588 | } | |
7589 | } | |
252b5132 RH |
7590 | } |
7591 | \f | |
d182319b JB |
7592 | /* x86_cons_fix_new is called via the expression parsing code when a |
7593 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
7594 | static int cons_sign = -1; |
7595 | ||
7596 | void | |
e3bb37b5 | 7597 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 7598 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 7599 | { |
d258b828 | 7600 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
7601 | |
7602 | #ifdef TE_PE | |
7603 | if (exp->X_op == O_secrel) | |
7604 | { | |
7605 | exp->X_op = O_symbol; | |
7606 | r = BFD_RELOC_32_SECREL; | |
7607 | } | |
7608 | #endif | |
7609 | ||
7610 | fix_new_exp (frag, off, len, exp, 0, r); | |
7611 | } | |
7612 | ||
357d1bd8 L |
7613 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
7614 | purpose of the `.dc.a' internal pseudo-op. */ | |
7615 | ||
7616 | int | |
7617 | x86_address_bytes (void) | |
7618 | { | |
7619 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
7620 | return 4; | |
7621 | return stdoutput->arch_info->bits_per_address / 8; | |
7622 | } | |
7623 | ||
d382c579 TG |
7624 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
7625 | || defined (LEX_AT) | |
d258b828 | 7626 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 7627 | #else |
f3c180ae AM |
7628 | /* Parse operands of the form |
7629 | <symbol>@GOTOFF+<nnn> | |
7630 | and similar .plt or .got references. | |
7631 | ||
7632 | If we find one, set up the correct relocation in RELOC and copy the | |
7633 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
7634 | parsing by the calling routine. Return this buffer, and if ADJUST | |
7635 | is non-null set it to the length of the string we removed from the | |
7636 | input line. Otherwise return NULL. */ | |
7637 | static char * | |
91d6fa6a | 7638 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 7639 | int *adjust, |
d258b828 | 7640 | i386_operand_type *types) |
f3c180ae | 7641 | { |
7b81dfbb AJ |
7642 | /* Some of the relocations depend on the size of what field is to |
7643 | be relocated. But in our callers i386_immediate and i386_displacement | |
7644 | we don't yet know the operand size (this will be set by insn | |
7645 | matching). Hence we record the word32 relocation here, | |
7646 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
7647 | static const struct { |
7648 | const char *str; | |
cff8d58a | 7649 | int len; |
4fa24527 | 7650 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 7651 | const i386_operand_type types64; |
f3c180ae | 7652 | } gotrel[] = { |
8ce3d284 | 7653 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
7654 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
7655 | BFD_RELOC_SIZE32 }, | |
7656 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 7657 | #endif |
cff8d58a L |
7658 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
7659 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 7660 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
7661 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
7662 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 7663 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7664 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
7665 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 7666 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
7667 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
7668 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 7669 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
7670 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
7671 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 7672 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7673 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
7674 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 7675 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7676 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
7677 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7678 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7679 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
7680 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 7681 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7682 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
7683 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 7684 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7685 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
7686 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 7687 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
7688 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
7689 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7690 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7691 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
7692 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 7693 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
7694 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
7695 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7696 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7697 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
7698 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7699 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7700 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
7701 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 7702 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
7703 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
7704 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 7705 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7706 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
7707 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 7708 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
7709 | }; |
7710 | char *cp; | |
7711 | unsigned int j; | |
7712 | ||
d382c579 | 7713 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
7714 | if (!IS_ELF) |
7715 | return NULL; | |
d382c579 | 7716 | #endif |
718ddfc0 | 7717 | |
f3c180ae | 7718 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 7719 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
7720 | return NULL; |
7721 | ||
47465058 | 7722 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 7723 | { |
cff8d58a | 7724 | int len = gotrel[j].len; |
28f81592 | 7725 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 7726 | { |
4fa24527 | 7727 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 7728 | { |
28f81592 AM |
7729 | int first, second; |
7730 | char *tmpbuf, *past_reloc; | |
f3c180ae | 7731 | |
91d6fa6a | 7732 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 7733 | |
3956db08 JB |
7734 | if (types) |
7735 | { | |
7736 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
7737 | { |
7738 | types->bitfield.imm32 = 1; | |
7739 | types->bitfield.disp32 = 1; | |
7740 | } | |
3956db08 JB |
7741 | else |
7742 | *types = gotrel[j].types64; | |
7743 | } | |
7744 | ||
8fd4256d | 7745 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
7746 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
7747 | ||
28f81592 | 7748 | /* The length of the first part of our input line. */ |
f3c180ae | 7749 | first = cp - input_line_pointer; |
28f81592 AM |
7750 | |
7751 | /* The second part goes from after the reloc token until | |
67c11a9b | 7752 | (and including) an end_of_line char or comma. */ |
28f81592 | 7753 | past_reloc = cp + 1 + len; |
67c11a9b AM |
7754 | cp = past_reloc; |
7755 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
7756 | ++cp; | |
7757 | second = cp + 1 - past_reloc; | |
28f81592 AM |
7758 | |
7759 | /* Allocate and copy string. The trailing NUL shouldn't | |
7760 | be necessary, but be safe. */ | |
add39d23 | 7761 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 7762 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
7763 | if (second != 0 && *past_reloc != ' ') |
7764 | /* Replace the relocation token with ' ', so that | |
7765 | errors like foo@GOTOFF1 will be detected. */ | |
7766 | tmpbuf[first++] = ' '; | |
af89796a L |
7767 | else |
7768 | /* Increment length by 1 if the relocation token is | |
7769 | removed. */ | |
7770 | len++; | |
7771 | if (adjust) | |
7772 | *adjust = len; | |
0787a12d AM |
7773 | memcpy (tmpbuf + first, past_reloc, second); |
7774 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
7775 | return tmpbuf; |
7776 | } | |
7777 | ||
4fa24527 JB |
7778 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
7779 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
7780 | return NULL; |
7781 | } | |
7782 | } | |
7783 | ||
7784 | /* Might be a symbol version string. Don't as_bad here. */ | |
7785 | return NULL; | |
7786 | } | |
4e4f7c87 | 7787 | #endif |
f3c180ae | 7788 | |
a988325c NC |
7789 | #ifdef TE_PE |
7790 | #ifdef lex_got | |
7791 | #undef lex_got | |
7792 | #endif | |
7793 | /* Parse operands of the form | |
7794 | <symbol>@SECREL32+<nnn> | |
7795 | ||
7796 | If we find one, set up the correct relocation in RELOC and copy the | |
7797 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
7798 | parsing by the calling routine. Return this buffer, and if ADJUST | |
7799 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
7800 | input line. Otherwise return NULL. |
7801 | ||
a988325c NC |
7802 | This function is copied from the ELF version above adjusted for PE targets. */ |
7803 | ||
7804 | static char * | |
7805 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
7806 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 7807 | i386_operand_type *types) |
a988325c NC |
7808 | { |
7809 | static const struct | |
7810 | { | |
7811 | const char *str; | |
7812 | int len; | |
7813 | const enum bfd_reloc_code_real rel[2]; | |
7814 | const i386_operand_type types64; | |
7815 | } | |
7816 | gotrel[] = | |
7817 | { | |
7818 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
7819 | BFD_RELOC_32_SECREL }, | |
7820 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
7821 | }; | |
7822 | ||
7823 | char *cp; | |
7824 | unsigned j; | |
7825 | ||
7826 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
7827 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
7828 | return NULL; | |
7829 | ||
7830 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
7831 | { | |
7832 | int len = gotrel[j].len; | |
7833 | ||
7834 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
7835 | { | |
7836 | if (gotrel[j].rel[object_64bit] != 0) | |
7837 | { | |
7838 | int first, second; | |
7839 | char *tmpbuf, *past_reloc; | |
7840 | ||
7841 | *rel = gotrel[j].rel[object_64bit]; | |
7842 | if (adjust) | |
7843 | *adjust = len; | |
7844 | ||
7845 | if (types) | |
7846 | { | |
7847 | if (flag_code != CODE_64BIT) | |
7848 | { | |
7849 | types->bitfield.imm32 = 1; | |
7850 | types->bitfield.disp32 = 1; | |
7851 | } | |
7852 | else | |
7853 | *types = gotrel[j].types64; | |
7854 | } | |
7855 | ||
7856 | /* The length of the first part of our input line. */ | |
7857 | first = cp - input_line_pointer; | |
7858 | ||
7859 | /* The second part goes from after the reloc token until | |
7860 | (and including) an end_of_line char or comma. */ | |
7861 | past_reloc = cp + 1 + len; | |
7862 | cp = past_reloc; | |
7863 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
7864 | ++cp; | |
7865 | second = cp + 1 - past_reloc; | |
7866 | ||
7867 | /* Allocate and copy string. The trailing NUL shouldn't | |
7868 | be necessary, but be safe. */ | |
add39d23 | 7869 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
7870 | memcpy (tmpbuf, input_line_pointer, first); |
7871 | if (second != 0 && *past_reloc != ' ') | |
7872 | /* Replace the relocation token with ' ', so that | |
7873 | errors like foo@SECLREL321 will be detected. */ | |
7874 | tmpbuf[first++] = ' '; | |
7875 | memcpy (tmpbuf + first, past_reloc, second); | |
7876 | tmpbuf[first + second] = '\0'; | |
7877 | return tmpbuf; | |
7878 | } | |
7879 | ||
7880 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
7881 | gotrel[j].str, 1 << (5 + object_64bit)); | |
7882 | return NULL; | |
7883 | } | |
7884 | } | |
7885 | ||
7886 | /* Might be a symbol version string. Don't as_bad here. */ | |
7887 | return NULL; | |
7888 | } | |
7889 | ||
7890 | #endif /* TE_PE */ | |
7891 | ||
62ebcb5c | 7892 | bfd_reloc_code_real_type |
e3bb37b5 | 7893 | x86_cons (expressionS *exp, int size) |
f3c180ae | 7894 | { |
62ebcb5c AM |
7895 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
7896 | ||
ee86248c JB |
7897 | intel_syntax = -intel_syntax; |
7898 | ||
3c7b9c2c | 7899 | exp->X_md = 0; |
4fa24527 | 7900 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
7901 | { |
7902 | /* Handle @GOTOFF and the like in an expression. */ | |
7903 | char *save; | |
7904 | char *gotfree_input_line; | |
4a57f2cf | 7905 | int adjust = 0; |
f3c180ae AM |
7906 | |
7907 | save = input_line_pointer; | |
d258b828 | 7908 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
7909 | if (gotfree_input_line) |
7910 | input_line_pointer = gotfree_input_line; | |
7911 | ||
7912 | expression (exp); | |
7913 | ||
7914 | if (gotfree_input_line) | |
7915 | { | |
7916 | /* expression () has merrily parsed up to the end of line, | |
7917 | or a comma - in the wrong buffer. Transfer how far | |
7918 | input_line_pointer has moved to the right buffer. */ | |
7919 | input_line_pointer = (save | |
7920 | + (input_line_pointer - gotfree_input_line) | |
7921 | + adjust); | |
7922 | free (gotfree_input_line); | |
3992d3b7 AM |
7923 | if (exp->X_op == O_constant |
7924 | || exp->X_op == O_absent | |
7925 | || exp->X_op == O_illegal | |
0398aac5 | 7926 | || exp->X_op == O_register |
3992d3b7 AM |
7927 | || exp->X_op == O_big) |
7928 | { | |
7929 | char c = *input_line_pointer; | |
7930 | *input_line_pointer = 0; | |
7931 | as_bad (_("missing or invalid expression `%s'"), save); | |
7932 | *input_line_pointer = c; | |
7933 | } | |
f3c180ae AM |
7934 | } |
7935 | } | |
7936 | else | |
7937 | expression (exp); | |
ee86248c JB |
7938 | |
7939 | intel_syntax = -intel_syntax; | |
7940 | ||
7941 | if (intel_syntax) | |
7942 | i386_intel_simplify (exp); | |
62ebcb5c AM |
7943 | |
7944 | return got_reloc; | |
f3c180ae | 7945 | } |
f3c180ae | 7946 | |
9f32dd5b L |
7947 | static void |
7948 | signed_cons (int size) | |
6482c264 | 7949 | { |
d182319b JB |
7950 | if (flag_code == CODE_64BIT) |
7951 | cons_sign = 1; | |
7952 | cons (size); | |
7953 | cons_sign = -1; | |
6482c264 NC |
7954 | } |
7955 | ||
d182319b | 7956 | #ifdef TE_PE |
6482c264 | 7957 | static void |
7016a5d5 | 7958 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
7959 | { |
7960 | expressionS exp; | |
7961 | ||
7962 | do | |
7963 | { | |
7964 | expression (&exp); | |
7965 | if (exp.X_op == O_symbol) | |
7966 | exp.X_op = O_secrel; | |
7967 | ||
7968 | emit_expr (&exp, 4); | |
7969 | } | |
7970 | while (*input_line_pointer++ == ','); | |
7971 | ||
7972 | input_line_pointer--; | |
7973 | demand_empty_rest_of_line (); | |
7974 | } | |
6482c264 NC |
7975 | #endif |
7976 | ||
43234a1e L |
7977 | /* Handle Vector operations. */ |
7978 | ||
7979 | static char * | |
7980 | check_VecOperations (char *op_string, char *op_end) | |
7981 | { | |
7982 | const reg_entry *mask; | |
7983 | const char *saved; | |
7984 | char *end_op; | |
7985 | ||
7986 | while (*op_string | |
7987 | && (op_end == NULL || op_string < op_end)) | |
7988 | { | |
7989 | saved = op_string; | |
7990 | if (*op_string == '{') | |
7991 | { | |
7992 | op_string++; | |
7993 | ||
7994 | /* Check broadcasts. */ | |
7995 | if (strncmp (op_string, "1to", 3) == 0) | |
7996 | { | |
7997 | int bcst_type; | |
7998 | ||
7999 | if (i.broadcast) | |
8000 | goto duplicated_vec_op; | |
8001 | ||
8002 | op_string += 3; | |
8003 | if (*op_string == '8') | |
8004 | bcst_type = BROADCAST_1TO8; | |
b28d1bda IT |
8005 | else if (*op_string == '4') |
8006 | bcst_type = BROADCAST_1TO4; | |
8007 | else if (*op_string == '2') | |
8008 | bcst_type = BROADCAST_1TO2; | |
43234a1e L |
8009 | else if (*op_string == '1' |
8010 | && *(op_string+1) == '6') | |
8011 | { | |
8012 | bcst_type = BROADCAST_1TO16; | |
8013 | op_string++; | |
8014 | } | |
8015 | else | |
8016 | { | |
8017 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
8018 | return NULL; | |
8019 | } | |
8020 | op_string++; | |
8021 | ||
8022 | broadcast_op.type = bcst_type; | |
8023 | broadcast_op.operand = this_operand; | |
8024 | i.broadcast = &broadcast_op; | |
8025 | } | |
8026 | /* Check masking operation. */ | |
8027 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
8028 | { | |
8029 | /* k0 can't be used for write mask. */ | |
8030 | if (mask->reg_num == 0) | |
8031 | { | |
8032 | as_bad (_("`%s' can't be used for write mask"), | |
8033 | op_string); | |
8034 | return NULL; | |
8035 | } | |
8036 | ||
8037 | if (!i.mask) | |
8038 | { | |
8039 | mask_op.mask = mask; | |
8040 | mask_op.zeroing = 0; | |
8041 | mask_op.operand = this_operand; | |
8042 | i.mask = &mask_op; | |
8043 | } | |
8044 | else | |
8045 | { | |
8046 | if (i.mask->mask) | |
8047 | goto duplicated_vec_op; | |
8048 | ||
8049 | i.mask->mask = mask; | |
8050 | ||
8051 | /* Only "{z}" is allowed here. No need to check | |
8052 | zeroing mask explicitly. */ | |
8053 | if (i.mask->operand != this_operand) | |
8054 | { | |
8055 | as_bad (_("invalid write mask `%s'"), saved); | |
8056 | return NULL; | |
8057 | } | |
8058 | } | |
8059 | ||
8060 | op_string = end_op; | |
8061 | } | |
8062 | /* Check zeroing-flag for masking operation. */ | |
8063 | else if (*op_string == 'z') | |
8064 | { | |
8065 | if (!i.mask) | |
8066 | { | |
8067 | mask_op.mask = NULL; | |
8068 | mask_op.zeroing = 1; | |
8069 | mask_op.operand = this_operand; | |
8070 | i.mask = &mask_op; | |
8071 | } | |
8072 | else | |
8073 | { | |
8074 | if (i.mask->zeroing) | |
8075 | { | |
8076 | duplicated_vec_op: | |
8077 | as_bad (_("duplicated `%s'"), saved); | |
8078 | return NULL; | |
8079 | } | |
8080 | ||
8081 | i.mask->zeroing = 1; | |
8082 | ||
8083 | /* Only "{%k}" is allowed here. No need to check mask | |
8084 | register explicitly. */ | |
8085 | if (i.mask->operand != this_operand) | |
8086 | { | |
8087 | as_bad (_("invalid zeroing-masking `%s'"), | |
8088 | saved); | |
8089 | return NULL; | |
8090 | } | |
8091 | } | |
8092 | ||
8093 | op_string++; | |
8094 | } | |
8095 | else | |
8096 | goto unknown_vec_op; | |
8097 | ||
8098 | if (*op_string != '}') | |
8099 | { | |
8100 | as_bad (_("missing `}' in `%s'"), saved); | |
8101 | return NULL; | |
8102 | } | |
8103 | op_string++; | |
8104 | continue; | |
8105 | } | |
8106 | unknown_vec_op: | |
8107 | /* We don't know this one. */ | |
8108 | as_bad (_("unknown vector operation: `%s'"), saved); | |
8109 | return NULL; | |
8110 | } | |
8111 | ||
8112 | return op_string; | |
8113 | } | |
8114 | ||
252b5132 | 8115 | static int |
70e41ade | 8116 | i386_immediate (char *imm_start) |
252b5132 RH |
8117 | { |
8118 | char *save_input_line_pointer; | |
f3c180ae | 8119 | char *gotfree_input_line; |
252b5132 | 8120 | segT exp_seg = 0; |
47926f60 | 8121 | expressionS *exp; |
40fb9820 L |
8122 | i386_operand_type types; |
8123 | ||
0dfbf9d7 | 8124 | operand_type_set (&types, ~0); |
252b5132 RH |
8125 | |
8126 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
8127 | { | |
31b2323c L |
8128 | as_bad (_("at most %d immediate operands are allowed"), |
8129 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
8130 | return 0; |
8131 | } | |
8132 | ||
8133 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 8134 | i.op[this_operand].imms = exp; |
252b5132 RH |
8135 | |
8136 | if (is_space_char (*imm_start)) | |
8137 | ++imm_start; | |
8138 | ||
8139 | save_input_line_pointer = input_line_pointer; | |
8140 | input_line_pointer = imm_start; | |
8141 | ||
d258b828 | 8142 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8143 | if (gotfree_input_line) |
8144 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
8145 | |
8146 | exp_seg = expression (exp); | |
8147 | ||
83183c0c | 8148 | SKIP_WHITESPACE (); |
43234a1e L |
8149 | |
8150 | /* Handle vector operations. */ | |
8151 | if (*input_line_pointer == '{') | |
8152 | { | |
8153 | input_line_pointer = check_VecOperations (input_line_pointer, | |
8154 | NULL); | |
8155 | if (input_line_pointer == NULL) | |
8156 | return 0; | |
8157 | } | |
8158 | ||
252b5132 | 8159 | if (*input_line_pointer) |
f3c180ae | 8160 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
8161 | |
8162 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 8163 | if (gotfree_input_line) |
ee86248c JB |
8164 | { |
8165 | free (gotfree_input_line); | |
8166 | ||
8167 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8168 | exp->X_op = O_illegal; | |
8169 | } | |
8170 | ||
8171 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
8172 | } | |
252b5132 | 8173 | |
ee86248c JB |
8174 | static int |
8175 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8176 | i386_operand_type types, const char *imm_start) | |
8177 | { | |
8178 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 8179 | { |
313c53d1 L |
8180 | if (imm_start) |
8181 | as_bad (_("missing or invalid immediate expression `%s'"), | |
8182 | imm_start); | |
3992d3b7 | 8183 | return 0; |
252b5132 | 8184 | } |
3e73aa7c | 8185 | else if (exp->X_op == O_constant) |
252b5132 | 8186 | { |
47926f60 | 8187 | /* Size it properly later. */ |
40fb9820 | 8188 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
8189 | /* If not 64bit, sign extend val. */ |
8190 | if (flag_code != CODE_64BIT | |
4eed87de AM |
8191 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
8192 | exp->X_add_number | |
8193 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 8194 | } |
4c63da97 | 8195 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 8196 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 8197 | && exp_seg != absolute_section |
47926f60 | 8198 | && exp_seg != text_section |
24eab124 AM |
8199 | && exp_seg != data_section |
8200 | && exp_seg != bss_section | |
8201 | && exp_seg != undefined_section | |
f86103b7 | 8202 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 8203 | { |
d0b47220 | 8204 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
8205 | return 0; |
8206 | } | |
8207 | #endif | |
a841bdf5 | 8208 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 8209 | { |
313c53d1 L |
8210 | if (imm_start) |
8211 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
8212 | return 0; |
8213 | } | |
252b5132 RH |
8214 | else |
8215 | { | |
8216 | /* This is an address. The size of the address will be | |
24eab124 | 8217 | determined later, depending on destination register, |
3e73aa7c | 8218 | suffix, or the default for the section. */ |
40fb9820 L |
8219 | i.types[this_operand].bitfield.imm8 = 1; |
8220 | i.types[this_operand].bitfield.imm16 = 1; | |
8221 | i.types[this_operand].bitfield.imm32 = 1; | |
8222 | i.types[this_operand].bitfield.imm32s = 1; | |
8223 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
8224 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8225 | types); | |
252b5132 RH |
8226 | } |
8227 | ||
8228 | return 1; | |
8229 | } | |
8230 | ||
551c1ca1 | 8231 | static char * |
e3bb37b5 | 8232 | i386_scale (char *scale) |
252b5132 | 8233 | { |
551c1ca1 AM |
8234 | offsetT val; |
8235 | char *save = input_line_pointer; | |
252b5132 | 8236 | |
551c1ca1 AM |
8237 | input_line_pointer = scale; |
8238 | val = get_absolute_expression (); | |
8239 | ||
8240 | switch (val) | |
252b5132 | 8241 | { |
551c1ca1 | 8242 | case 1: |
252b5132 RH |
8243 | i.log2_scale_factor = 0; |
8244 | break; | |
551c1ca1 | 8245 | case 2: |
252b5132 RH |
8246 | i.log2_scale_factor = 1; |
8247 | break; | |
551c1ca1 | 8248 | case 4: |
252b5132 RH |
8249 | i.log2_scale_factor = 2; |
8250 | break; | |
551c1ca1 | 8251 | case 8: |
252b5132 RH |
8252 | i.log2_scale_factor = 3; |
8253 | break; | |
8254 | default: | |
a724f0f4 JB |
8255 | { |
8256 | char sep = *input_line_pointer; | |
8257 | ||
8258 | *input_line_pointer = '\0'; | |
8259 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
8260 | scale); | |
8261 | *input_line_pointer = sep; | |
8262 | input_line_pointer = save; | |
8263 | return NULL; | |
8264 | } | |
252b5132 | 8265 | } |
29b0f896 | 8266 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
8267 | { |
8268 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 8269 | 1 << i.log2_scale_factor); |
252b5132 | 8270 | i.log2_scale_factor = 0; |
252b5132 | 8271 | } |
551c1ca1 AM |
8272 | scale = input_line_pointer; |
8273 | input_line_pointer = save; | |
8274 | return scale; | |
252b5132 RH |
8275 | } |
8276 | ||
252b5132 | 8277 | static int |
e3bb37b5 | 8278 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 8279 | { |
29b0f896 | 8280 | expressionS *exp; |
252b5132 RH |
8281 | segT exp_seg = 0; |
8282 | char *save_input_line_pointer; | |
f3c180ae | 8283 | char *gotfree_input_line; |
40fb9820 L |
8284 | int override; |
8285 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 8286 | int ret; |
252b5132 | 8287 | |
31b2323c L |
8288 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
8289 | { | |
8290 | as_bad (_("at most %d displacement operands are allowed"), | |
8291 | MAX_MEMORY_OPERANDS); | |
8292 | return 0; | |
8293 | } | |
8294 | ||
0dfbf9d7 | 8295 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
8296 | if ((i.types[this_operand].bitfield.jumpabsolute) |
8297 | || (!current_templates->start->opcode_modifier.jump | |
8298 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 8299 | { |
40fb9820 | 8300 | bigdisp.bitfield.disp32 = 1; |
e05278af | 8301 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
8302 | if (flag_code == CODE_64BIT) |
8303 | { | |
8304 | if (!override) | |
8305 | { | |
8306 | bigdisp.bitfield.disp32s = 1; | |
8307 | bigdisp.bitfield.disp64 = 1; | |
8308 | } | |
8309 | } | |
8310 | else if ((flag_code == CODE_16BIT) ^ override) | |
8311 | { | |
8312 | bigdisp.bitfield.disp32 = 0; | |
8313 | bigdisp.bitfield.disp16 = 1; | |
8314 | } | |
e05278af JB |
8315 | } |
8316 | else | |
8317 | { | |
8318 | /* For PC-relative branches, the width of the displacement | |
8319 | is dependent upon data size, not address size. */ | |
e05278af | 8320 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
8321 | if (flag_code == CODE_64BIT) |
8322 | { | |
8323 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
8324 | bigdisp.bitfield.disp16 = 1; | |
8325 | else | |
8326 | { | |
8327 | bigdisp.bitfield.disp32 = 1; | |
8328 | bigdisp.bitfield.disp32s = 1; | |
8329 | } | |
8330 | } | |
8331 | else | |
e05278af JB |
8332 | { |
8333 | if (!override) | |
8334 | override = (i.suffix == (flag_code != CODE_16BIT | |
8335 | ? WORD_MNEM_SUFFIX | |
8336 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
8337 | bigdisp.bitfield.disp32 = 1; |
8338 | if ((flag_code == CODE_16BIT) ^ override) | |
8339 | { | |
8340 | bigdisp.bitfield.disp32 = 0; | |
8341 | bigdisp.bitfield.disp16 = 1; | |
8342 | } | |
e05278af | 8343 | } |
e05278af | 8344 | } |
c6fb90c8 L |
8345 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8346 | bigdisp); | |
252b5132 RH |
8347 | |
8348 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 8349 | i.op[this_operand].disps = exp; |
252b5132 RH |
8350 | i.disp_operands++; |
8351 | save_input_line_pointer = input_line_pointer; | |
8352 | input_line_pointer = disp_start; | |
8353 | END_STRING_AND_SAVE (disp_end); | |
8354 | ||
8355 | #ifndef GCC_ASM_O_HACK | |
8356 | #define GCC_ASM_O_HACK 0 | |
8357 | #endif | |
8358 | #if GCC_ASM_O_HACK | |
8359 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 8360 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 8361 | && displacement_string_end[-1] == '+') |
252b5132 RH |
8362 | { |
8363 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
8364 | constraint within gcc asm statements. |
8365 | For instance: | |
8366 | ||
8367 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
8368 | __asm__ __volatile__ ( \ | |
8369 | "movw %w2,%0\n\t" \ | |
8370 | "movw %w1,2+%0\n\t" \ | |
8371 | "rorl $16,%1\n\t" \ | |
8372 | "movb %b1,4+%0\n\t" \ | |
8373 | "movb %4,5+%0\n\t" \ | |
8374 | "movb $0,6+%0\n\t" \ | |
8375 | "movb %h1,7+%0\n\t" \ | |
8376 | "rorl $16,%1" \ | |
8377 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
8378 | ||
8379 | This works great except that the output assembler ends | |
8380 | up looking a bit weird if it turns out that there is | |
8381 | no offset. You end up producing code that looks like: | |
8382 | ||
8383 | #APP | |
8384 | movw $235,(%eax) | |
8385 | movw %dx,2+(%eax) | |
8386 | rorl $16,%edx | |
8387 | movb %dl,4+(%eax) | |
8388 | movb $137,5+(%eax) | |
8389 | movb $0,6+(%eax) | |
8390 | movb %dh,7+(%eax) | |
8391 | rorl $16,%edx | |
8392 | #NO_APP | |
8393 | ||
47926f60 | 8394 | So here we provide the missing zero. */ |
24eab124 AM |
8395 | |
8396 | *displacement_string_end = '0'; | |
252b5132 RH |
8397 | } |
8398 | #endif | |
d258b828 | 8399 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8400 | if (gotfree_input_line) |
8401 | input_line_pointer = gotfree_input_line; | |
252b5132 | 8402 | |
24eab124 | 8403 | exp_seg = expression (exp); |
252b5132 | 8404 | |
636c26b0 AM |
8405 | SKIP_WHITESPACE (); |
8406 | if (*input_line_pointer) | |
8407 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
8408 | #if GCC_ASM_O_HACK | |
8409 | RESTORE_END_STRING (disp_end + 1); | |
8410 | #endif | |
636c26b0 | 8411 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 8412 | if (gotfree_input_line) |
ee86248c JB |
8413 | { |
8414 | free (gotfree_input_line); | |
8415 | ||
8416 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8417 | exp->X_op = O_illegal; | |
8418 | } | |
8419 | ||
8420 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
8421 | ||
8422 | RESTORE_END_STRING (disp_end); | |
8423 | ||
8424 | return ret; | |
8425 | } | |
8426 | ||
8427 | static int | |
8428 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8429 | i386_operand_type types, const char *disp_start) | |
8430 | { | |
8431 | i386_operand_type bigdisp; | |
8432 | int ret = 1; | |
636c26b0 | 8433 | |
24eab124 AM |
8434 | /* We do this to make sure that the section symbol is in |
8435 | the symbol table. We will ultimately change the relocation | |
47926f60 | 8436 | to be relative to the beginning of the section. */ |
1ae12ab7 | 8437 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
8438 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
8439 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 8440 | { |
636c26b0 | 8441 | if (exp->X_op != O_symbol) |
3992d3b7 | 8442 | goto inv_disp; |
636c26b0 | 8443 | |
e5cb08ac | 8444 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
8445 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
8446 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 8447 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
8448 | exp->X_op = O_subtract; |
8449 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 8450 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 8451 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
8452 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
8453 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 8454 | else |
29b0f896 | 8455 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 8456 | } |
252b5132 | 8457 | |
3992d3b7 AM |
8458 | else if (exp->X_op == O_absent |
8459 | || exp->X_op == O_illegal | |
ee86248c | 8460 | || exp->X_op == O_big) |
2daf4fd8 | 8461 | { |
3992d3b7 AM |
8462 | inv_disp: |
8463 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 8464 | disp_start); |
3992d3b7 | 8465 | ret = 0; |
2daf4fd8 AM |
8466 | } |
8467 | ||
0e1147d9 L |
8468 | else if (flag_code == CODE_64BIT |
8469 | && !i.prefix[ADDR_PREFIX] | |
8470 | && exp->X_op == O_constant) | |
8471 | { | |
8472 | /* Since displacement is signed extended to 64bit, don't allow | |
8473 | disp32 and turn off disp32s if they are out of range. */ | |
8474 | i.types[this_operand].bitfield.disp32 = 0; | |
8475 | if (!fits_in_signed_long (exp->X_add_number)) | |
8476 | { | |
8477 | i.types[this_operand].bitfield.disp32s = 0; | |
8478 | if (i.types[this_operand].bitfield.baseindex) | |
8479 | { | |
8480 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
8481 | (long) exp->X_add_number); | |
8482 | ret = 0; | |
8483 | } | |
8484 | } | |
8485 | } | |
8486 | ||
4c63da97 | 8487 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
8488 | else if (exp->X_op != O_constant |
8489 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
8490 | && exp_seg != absolute_section | |
8491 | && exp_seg != text_section | |
8492 | && exp_seg != data_section | |
8493 | && exp_seg != bss_section | |
8494 | && exp_seg != undefined_section | |
8495 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 8496 | { |
d0b47220 | 8497 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 8498 | ret = 0; |
24eab124 | 8499 | } |
252b5132 | 8500 | #endif |
3956db08 | 8501 | |
40fb9820 L |
8502 | /* Check if this is a displacement only operand. */ |
8503 | bigdisp = i.types[this_operand]; | |
8504 | bigdisp.bitfield.disp8 = 0; | |
8505 | bigdisp.bitfield.disp16 = 0; | |
8506 | bigdisp.bitfield.disp32 = 0; | |
8507 | bigdisp.bitfield.disp32s = 0; | |
8508 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 8509 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
8510 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8511 | types); | |
3956db08 | 8512 | |
3992d3b7 | 8513 | return ret; |
252b5132 RH |
8514 | } |
8515 | ||
eecb386c | 8516 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
8517 | Return 1 on success, 0 on a failure. */ |
8518 | ||
252b5132 | 8519 | static int |
e3bb37b5 | 8520 | i386_index_check (const char *operand_string) |
252b5132 | 8521 | { |
fc0763e6 | 8522 | const char *kind = "base/index"; |
be05d201 L |
8523 | enum flag_code addr_mode; |
8524 | ||
8525 | if (i.prefix[ADDR_PREFIX]) | |
8526 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
8527 | else | |
8528 | { | |
8529 | addr_mode = flag_code; | |
8530 | ||
24eab124 | 8531 | #if INFER_ADDR_PREFIX |
be05d201 L |
8532 | if (i.mem_operands == 0) |
8533 | { | |
8534 | /* Infer address prefix from the first memory operand. */ | |
8535 | const reg_entry *addr_reg = i.base_reg; | |
8536 | ||
8537 | if (addr_reg == NULL) | |
8538 | addr_reg = i.index_reg; | |
eecb386c | 8539 | |
be05d201 L |
8540 | if (addr_reg) |
8541 | { | |
8542 | if (addr_reg->reg_num == RegEip | |
8543 | || addr_reg->reg_num == RegEiz | |
8544 | || addr_reg->reg_type.bitfield.reg32) | |
8545 | addr_mode = CODE_32BIT; | |
8546 | else if (flag_code != CODE_64BIT | |
8547 | && addr_reg->reg_type.bitfield.reg16) | |
8548 | addr_mode = CODE_16BIT; | |
8549 | ||
8550 | if (addr_mode != flag_code) | |
8551 | { | |
8552 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
8553 | i.prefixes += 1; | |
8554 | /* Change the size of any displacement too. At most one | |
8555 | of Disp16 or Disp32 is set. | |
8556 | FIXME. There doesn't seem to be any real need for | |
8557 | separate Disp16 and Disp32 flags. The same goes for | |
8558 | Imm16 and Imm32. Removing them would probably clean | |
8559 | up the code quite a lot. */ | |
8560 | if (flag_code != CODE_64BIT | |
8561 | && (i.types[this_operand].bitfield.disp16 | |
8562 | || i.types[this_operand].bitfield.disp32)) | |
8563 | i.types[this_operand] | |
8564 | = operand_type_xor (i.types[this_operand], disp16_32); | |
8565 | } | |
8566 | } | |
8567 | } | |
24eab124 | 8568 | #endif |
be05d201 L |
8569 | } |
8570 | ||
fc0763e6 JB |
8571 | if (current_templates->start->opcode_modifier.isstring |
8572 | && !current_templates->start->opcode_modifier.immext | |
8573 | && (current_templates->end[-1].opcode_modifier.isstring | |
8574 | || i.mem_operands)) | |
8575 | { | |
8576 | /* Memory operands of string insns are special in that they only allow | |
8577 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
8578 | const reg_entry *expected_reg; |
8579 | static const char *di_si[][2] = | |
8580 | { | |
8581 | { "esi", "edi" }, | |
8582 | { "si", "di" }, | |
8583 | { "rsi", "rdi" } | |
8584 | }; | |
8585 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
8586 | |
8587 | kind = "string address"; | |
8588 | ||
8325cc63 | 8589 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
8590 | { |
8591 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
8592 | ||
8593 | if (!type.bitfield.baseindex | |
8594 | || ((!i.mem_operands != !intel_syntax) | |
8595 | && current_templates->end[-1].operand_types[1] | |
8596 | .bitfield.baseindex)) | |
8597 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
8598 | expected_reg = hash_find (reg_hash, |
8599 | di_si[addr_mode][type.bitfield.esseg]); | |
8600 | ||
fc0763e6 JB |
8601 | } |
8602 | else | |
be05d201 | 8603 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 8604 | |
be05d201 L |
8605 | if (i.base_reg != expected_reg |
8606 | || i.index_reg | |
fc0763e6 | 8607 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 8608 | { |
be05d201 L |
8609 | /* The second memory operand must have the same size as |
8610 | the first one. */ | |
8611 | if (i.mem_operands | |
8612 | && i.base_reg | |
8613 | && !((addr_mode == CODE_64BIT | |
8614 | && i.base_reg->reg_type.bitfield.reg64) | |
8615 | || (addr_mode == CODE_32BIT | |
8616 | ? i.base_reg->reg_type.bitfield.reg32 | |
8617 | : i.base_reg->reg_type.bitfield.reg16))) | |
8618 | goto bad_address; | |
8619 | ||
fc0763e6 JB |
8620 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
8621 | operand_string, | |
8622 | intel_syntax ? '[' : '(', | |
8623 | register_prefix, | |
be05d201 | 8624 | expected_reg->reg_name, |
fc0763e6 | 8625 | intel_syntax ? ']' : ')'); |
be05d201 | 8626 | return 1; |
fc0763e6 | 8627 | } |
be05d201 L |
8628 | else |
8629 | return 1; | |
8630 | ||
8631 | bad_address: | |
8632 | as_bad (_("`%s' is not a valid %s expression"), | |
8633 | operand_string, kind); | |
8634 | return 0; | |
3e73aa7c JH |
8635 | } |
8636 | else | |
8637 | { | |
be05d201 L |
8638 | if (addr_mode != CODE_16BIT) |
8639 | { | |
8640 | /* 32-bit/64-bit checks. */ | |
8641 | if ((i.base_reg | |
8642 | && (addr_mode == CODE_64BIT | |
8643 | ? !i.base_reg->reg_type.bitfield.reg64 | |
8644 | : !i.base_reg->reg_type.bitfield.reg32) | |
8645 | && (i.index_reg | |
8646 | || (i.base_reg->reg_num | |
8647 | != (addr_mode == CODE_64BIT ? RegRip : RegEip)))) | |
8648 | || (i.index_reg | |
8649 | && !i.index_reg->reg_type.bitfield.regxmm | |
8650 | && !i.index_reg->reg_type.bitfield.regymm | |
43234a1e | 8651 | && !i.index_reg->reg_type.bitfield.regzmm |
be05d201 L |
8652 | && ((addr_mode == CODE_64BIT |
8653 | ? !(i.index_reg->reg_type.bitfield.reg64 | |
8654 | || i.index_reg->reg_num == RegRiz) | |
8655 | : !(i.index_reg->reg_type.bitfield.reg32 | |
8656 | || i.index_reg->reg_num == RegEiz)) | |
8657 | || !i.index_reg->reg_type.bitfield.baseindex))) | |
8658 | goto bad_address; | |
8178be5b JB |
8659 | |
8660 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
8661 | if (current_templates->start->base_opcode == 0xf30f1b | |
8662 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
8663 | { | |
8664 | /* They cannot use RIP-relative addressing. */ | |
8665 | if (i.base_reg && i.base_reg->reg_num == RegRip) | |
8666 | { | |
8667 | as_bad (_("`%s' cannot be used here"), operand_string); | |
8668 | return 0; | |
8669 | } | |
8670 | ||
8671 | /* bndldx and bndstx ignore their scale factor. */ | |
8672 | if (current_templates->start->base_opcode != 0xf30f1b | |
8673 | && i.log2_scale_factor) | |
8674 | as_warn (_("register scaling is being ignored here")); | |
8675 | } | |
be05d201 L |
8676 | } |
8677 | else | |
3e73aa7c | 8678 | { |
be05d201 | 8679 | /* 16-bit checks. */ |
3e73aa7c | 8680 | if ((i.base_reg |
40fb9820 L |
8681 | && (!i.base_reg->reg_type.bitfield.reg16 |
8682 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 8683 | || (i.index_reg |
40fb9820 L |
8684 | && (!i.index_reg->reg_type.bitfield.reg16 |
8685 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
8686 | || !(i.base_reg |
8687 | && i.base_reg->reg_num < 6 | |
8688 | && i.index_reg->reg_num >= 6 | |
8689 | && i.log2_scale_factor == 0)))) | |
be05d201 | 8690 | goto bad_address; |
3e73aa7c JH |
8691 | } |
8692 | } | |
be05d201 | 8693 | return 1; |
24eab124 | 8694 | } |
252b5132 | 8695 | |
43234a1e L |
8696 | /* Handle vector immediates. */ |
8697 | ||
8698 | static int | |
8699 | RC_SAE_immediate (const char *imm_start) | |
8700 | { | |
8701 | unsigned int match_found, j; | |
8702 | const char *pstr = imm_start; | |
8703 | expressionS *exp; | |
8704 | ||
8705 | if (*pstr != '{') | |
8706 | return 0; | |
8707 | ||
8708 | pstr++; | |
8709 | match_found = 0; | |
8710 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
8711 | { | |
8712 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
8713 | { | |
8714 | if (!i.rounding) | |
8715 | { | |
8716 | rc_op.type = RC_NamesTable[j].type; | |
8717 | rc_op.operand = this_operand; | |
8718 | i.rounding = &rc_op; | |
8719 | } | |
8720 | else | |
8721 | { | |
8722 | as_bad (_("duplicated `%s'"), imm_start); | |
8723 | return 0; | |
8724 | } | |
8725 | pstr += RC_NamesTable[j].len; | |
8726 | match_found = 1; | |
8727 | break; | |
8728 | } | |
8729 | } | |
8730 | if (!match_found) | |
8731 | return 0; | |
8732 | ||
8733 | if (*pstr++ != '}') | |
8734 | { | |
8735 | as_bad (_("Missing '}': '%s'"), imm_start); | |
8736 | return 0; | |
8737 | } | |
8738 | /* RC/SAE immediate string should contain nothing more. */; | |
8739 | if (*pstr != 0) | |
8740 | { | |
8741 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
8742 | return 0; | |
8743 | } | |
8744 | ||
8745 | exp = &im_expressions[i.imm_operands++]; | |
8746 | i.op[this_operand].imms = exp; | |
8747 | ||
8748 | exp->X_op = O_constant; | |
8749 | exp->X_add_number = 0; | |
8750 | exp->X_add_symbol = (symbolS *) 0; | |
8751 | exp->X_op_symbol = (symbolS *) 0; | |
8752 | ||
8753 | i.types[this_operand].bitfield.imm8 = 1; | |
8754 | return 1; | |
8755 | } | |
8756 | ||
8325cc63 JB |
8757 | /* Only string instructions can have a second memory operand, so |
8758 | reduce current_templates to just those if it contains any. */ | |
8759 | static int | |
8760 | maybe_adjust_templates (void) | |
8761 | { | |
8762 | const insn_template *t; | |
8763 | ||
8764 | gas_assert (i.mem_operands == 1); | |
8765 | ||
8766 | for (t = current_templates->start; t < current_templates->end; ++t) | |
8767 | if (t->opcode_modifier.isstring) | |
8768 | break; | |
8769 | ||
8770 | if (t < current_templates->end) | |
8771 | { | |
8772 | static templates aux_templates; | |
8773 | bfd_boolean recheck; | |
8774 | ||
8775 | aux_templates.start = t; | |
8776 | for (; t < current_templates->end; ++t) | |
8777 | if (!t->opcode_modifier.isstring) | |
8778 | break; | |
8779 | aux_templates.end = t; | |
8780 | ||
8781 | /* Determine whether to re-check the first memory operand. */ | |
8782 | recheck = (aux_templates.start != current_templates->start | |
8783 | || t != current_templates->end); | |
8784 | ||
8785 | current_templates = &aux_templates; | |
8786 | ||
8787 | if (recheck) | |
8788 | { | |
8789 | i.mem_operands = 0; | |
8790 | if (i.memop1_string != NULL | |
8791 | && i386_index_check (i.memop1_string) == 0) | |
8792 | return 0; | |
8793 | i.mem_operands = 1; | |
8794 | } | |
8795 | } | |
8796 | ||
8797 | return 1; | |
8798 | } | |
8799 | ||
fc0763e6 | 8800 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 8801 | on error. */ |
252b5132 | 8802 | |
252b5132 | 8803 | static int |
a7619375 | 8804 | i386_att_operand (char *operand_string) |
252b5132 | 8805 | { |
af6bdddf AM |
8806 | const reg_entry *r; |
8807 | char *end_op; | |
24eab124 | 8808 | char *op_string = operand_string; |
252b5132 | 8809 | |
24eab124 | 8810 | if (is_space_char (*op_string)) |
252b5132 RH |
8811 | ++op_string; |
8812 | ||
24eab124 | 8813 | /* We check for an absolute prefix (differentiating, |
47926f60 | 8814 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
8815 | if (*op_string == ABSOLUTE_PREFIX) |
8816 | { | |
8817 | ++op_string; | |
8818 | if (is_space_char (*op_string)) | |
8819 | ++op_string; | |
40fb9820 | 8820 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 8821 | } |
252b5132 | 8822 | |
47926f60 | 8823 | /* Check if operand is a register. */ |
4d1bb795 | 8824 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 8825 | { |
40fb9820 L |
8826 | i386_operand_type temp; |
8827 | ||
24eab124 AM |
8828 | /* Check for a segment override by searching for ':' after a |
8829 | segment register. */ | |
8830 | op_string = end_op; | |
8831 | if (is_space_char (*op_string)) | |
8832 | ++op_string; | |
40fb9820 L |
8833 | if (*op_string == ':' |
8834 | && (r->reg_type.bitfield.sreg2 | |
8835 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
8836 | { |
8837 | switch (r->reg_num) | |
8838 | { | |
8839 | case 0: | |
8840 | i.seg[i.mem_operands] = &es; | |
8841 | break; | |
8842 | case 1: | |
8843 | i.seg[i.mem_operands] = &cs; | |
8844 | break; | |
8845 | case 2: | |
8846 | i.seg[i.mem_operands] = &ss; | |
8847 | break; | |
8848 | case 3: | |
8849 | i.seg[i.mem_operands] = &ds; | |
8850 | break; | |
8851 | case 4: | |
8852 | i.seg[i.mem_operands] = &fs; | |
8853 | break; | |
8854 | case 5: | |
8855 | i.seg[i.mem_operands] = &gs; | |
8856 | break; | |
8857 | } | |
252b5132 | 8858 | |
24eab124 | 8859 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
8860 | ++op_string; |
8861 | if (is_space_char (*op_string)) | |
24eab124 | 8862 | ++op_string; |
252b5132 | 8863 | |
24eab124 AM |
8864 | if (!is_digit_char (*op_string) |
8865 | && !is_identifier_char (*op_string) | |
8866 | && *op_string != '(' | |
8867 | && *op_string != ABSOLUTE_PREFIX) | |
8868 | { | |
8869 | as_bad (_("bad memory operand `%s'"), op_string); | |
8870 | return 0; | |
8871 | } | |
47926f60 | 8872 | /* Handle case of %es:*foo. */ |
24eab124 AM |
8873 | if (*op_string == ABSOLUTE_PREFIX) |
8874 | { | |
8875 | ++op_string; | |
8876 | if (is_space_char (*op_string)) | |
8877 | ++op_string; | |
40fb9820 | 8878 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
8879 | } |
8880 | goto do_memory_reference; | |
8881 | } | |
43234a1e L |
8882 | |
8883 | /* Handle vector operations. */ | |
8884 | if (*op_string == '{') | |
8885 | { | |
8886 | op_string = check_VecOperations (op_string, NULL); | |
8887 | if (op_string == NULL) | |
8888 | return 0; | |
8889 | } | |
8890 | ||
24eab124 AM |
8891 | if (*op_string) |
8892 | { | |
d0b47220 | 8893 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
8894 | return 0; |
8895 | } | |
40fb9820 L |
8896 | temp = r->reg_type; |
8897 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
8898 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8899 | temp); | |
7d5e4556 | 8900 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 8901 | i.op[this_operand].regs = r; |
24eab124 AM |
8902 | i.reg_operands++; |
8903 | } | |
af6bdddf AM |
8904 | else if (*op_string == REGISTER_PREFIX) |
8905 | { | |
8906 | as_bad (_("bad register name `%s'"), op_string); | |
8907 | return 0; | |
8908 | } | |
24eab124 | 8909 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 8910 | { |
24eab124 | 8911 | ++op_string; |
40fb9820 | 8912 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 8913 | { |
d0b47220 | 8914 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
8915 | return 0; |
8916 | } | |
8917 | if (!i386_immediate (op_string)) | |
8918 | return 0; | |
8919 | } | |
43234a1e L |
8920 | else if (RC_SAE_immediate (operand_string)) |
8921 | { | |
8922 | /* If it is a RC or SAE immediate, do nothing. */ | |
8923 | ; | |
8924 | } | |
24eab124 AM |
8925 | else if (is_digit_char (*op_string) |
8926 | || is_identifier_char (*op_string) | |
d02603dc | 8927 | || *op_string == '"' |
e5cb08ac | 8928 | || *op_string == '(') |
24eab124 | 8929 | { |
47926f60 | 8930 | /* This is a memory reference of some sort. */ |
af6bdddf | 8931 | char *base_string; |
252b5132 | 8932 | |
47926f60 | 8933 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
8934 | char *displacement_string_start; |
8935 | char *displacement_string_end; | |
43234a1e | 8936 | char *vop_start; |
252b5132 | 8937 | |
24eab124 | 8938 | do_memory_reference: |
8325cc63 JB |
8939 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
8940 | return 0; | |
24eab124 | 8941 | if ((i.mem_operands == 1 |
40fb9820 | 8942 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
8943 | || i.mem_operands == 2) |
8944 | { | |
8945 | as_bad (_("too many memory references for `%s'"), | |
8946 | current_templates->start->name); | |
8947 | return 0; | |
8948 | } | |
252b5132 | 8949 | |
24eab124 AM |
8950 | /* Check for base index form. We detect the base index form by |
8951 | looking for an ')' at the end of the operand, searching | |
8952 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
8953 | after the '('. */ | |
af6bdddf | 8954 | base_string = op_string + strlen (op_string); |
c3332e24 | 8955 | |
43234a1e L |
8956 | /* Handle vector operations. */ |
8957 | vop_start = strchr (op_string, '{'); | |
8958 | if (vop_start && vop_start < base_string) | |
8959 | { | |
8960 | if (check_VecOperations (vop_start, base_string) == NULL) | |
8961 | return 0; | |
8962 | base_string = vop_start; | |
8963 | } | |
8964 | ||
af6bdddf AM |
8965 | --base_string; |
8966 | if (is_space_char (*base_string)) | |
8967 | --base_string; | |
252b5132 | 8968 | |
47926f60 | 8969 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
8970 | displacement_string_start = op_string; |
8971 | displacement_string_end = base_string + 1; | |
252b5132 | 8972 | |
24eab124 AM |
8973 | if (*base_string == ')') |
8974 | { | |
af6bdddf | 8975 | char *temp_string; |
24eab124 AM |
8976 | unsigned int parens_balanced = 1; |
8977 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 8978 | equal, so this loop will not be infinite. */ |
24eab124 AM |
8979 | do |
8980 | { | |
8981 | base_string--; | |
8982 | if (*base_string == ')') | |
8983 | parens_balanced++; | |
8984 | if (*base_string == '(') | |
8985 | parens_balanced--; | |
8986 | } | |
8987 | while (parens_balanced); | |
c3332e24 | 8988 | |
af6bdddf | 8989 | temp_string = base_string; |
c3332e24 | 8990 | |
24eab124 | 8991 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
8992 | ++base_string; |
8993 | if (is_space_char (*base_string)) | |
24eab124 | 8994 | ++base_string; |
252b5132 | 8995 | |
af6bdddf | 8996 | if (*base_string == ',' |
4eed87de AM |
8997 | || ((i.base_reg = parse_register (base_string, &end_op)) |
8998 | != NULL)) | |
252b5132 | 8999 | { |
af6bdddf | 9000 | displacement_string_end = temp_string; |
252b5132 | 9001 | |
40fb9820 | 9002 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 9003 | |
af6bdddf | 9004 | if (i.base_reg) |
24eab124 | 9005 | { |
24eab124 AM |
9006 | base_string = end_op; |
9007 | if (is_space_char (*base_string)) | |
9008 | ++base_string; | |
af6bdddf AM |
9009 | } |
9010 | ||
9011 | /* There may be an index reg or scale factor here. */ | |
9012 | if (*base_string == ',') | |
9013 | { | |
9014 | ++base_string; | |
9015 | if (is_space_char (*base_string)) | |
9016 | ++base_string; | |
9017 | ||
4eed87de AM |
9018 | if ((i.index_reg = parse_register (base_string, &end_op)) |
9019 | != NULL) | |
24eab124 | 9020 | { |
af6bdddf | 9021 | base_string = end_op; |
24eab124 AM |
9022 | if (is_space_char (*base_string)) |
9023 | ++base_string; | |
af6bdddf AM |
9024 | if (*base_string == ',') |
9025 | { | |
9026 | ++base_string; | |
9027 | if (is_space_char (*base_string)) | |
9028 | ++base_string; | |
9029 | } | |
e5cb08ac | 9030 | else if (*base_string != ')') |
af6bdddf | 9031 | { |
4eed87de AM |
9032 | as_bad (_("expecting `,' or `)' " |
9033 | "after index register in `%s'"), | |
af6bdddf AM |
9034 | operand_string); |
9035 | return 0; | |
9036 | } | |
24eab124 | 9037 | } |
af6bdddf | 9038 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 9039 | { |
f76bf5e0 L |
9040 | end_op = strchr (base_string, ','); |
9041 | if (end_op) | |
9042 | *end_op = '\0'; | |
af6bdddf | 9043 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
9044 | return 0; |
9045 | } | |
252b5132 | 9046 | |
47926f60 | 9047 | /* Check for scale factor. */ |
551c1ca1 | 9048 | if (*base_string != ')') |
af6bdddf | 9049 | { |
551c1ca1 AM |
9050 | char *end_scale = i386_scale (base_string); |
9051 | ||
9052 | if (!end_scale) | |
af6bdddf | 9053 | return 0; |
24eab124 | 9054 | |
551c1ca1 | 9055 | base_string = end_scale; |
af6bdddf AM |
9056 | if (is_space_char (*base_string)) |
9057 | ++base_string; | |
9058 | if (*base_string != ')') | |
9059 | { | |
4eed87de AM |
9060 | as_bad (_("expecting `)' " |
9061 | "after scale factor in `%s'"), | |
af6bdddf AM |
9062 | operand_string); |
9063 | return 0; | |
9064 | } | |
9065 | } | |
9066 | else if (!i.index_reg) | |
24eab124 | 9067 | { |
4eed87de AM |
9068 | as_bad (_("expecting index register or scale factor " |
9069 | "after `,'; got '%c'"), | |
af6bdddf | 9070 | *base_string); |
24eab124 AM |
9071 | return 0; |
9072 | } | |
9073 | } | |
af6bdddf | 9074 | else if (*base_string != ')') |
24eab124 | 9075 | { |
4eed87de AM |
9076 | as_bad (_("expecting `,' or `)' " |
9077 | "after base register in `%s'"), | |
af6bdddf | 9078 | operand_string); |
24eab124 AM |
9079 | return 0; |
9080 | } | |
c3332e24 | 9081 | } |
af6bdddf | 9082 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 9083 | { |
f76bf5e0 L |
9084 | end_op = strchr (base_string, ','); |
9085 | if (end_op) | |
9086 | *end_op = '\0'; | |
af6bdddf | 9087 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 9088 | return 0; |
c3332e24 | 9089 | } |
24eab124 AM |
9090 | } |
9091 | ||
9092 | /* If there's an expression beginning the operand, parse it, | |
9093 | assuming displacement_string_start and | |
9094 | displacement_string_end are meaningful. */ | |
9095 | if (displacement_string_start != displacement_string_end) | |
9096 | { | |
9097 | if (!i386_displacement (displacement_string_start, | |
9098 | displacement_string_end)) | |
9099 | return 0; | |
9100 | } | |
9101 | ||
9102 | /* Special case for (%dx) while doing input/output op. */ | |
9103 | if (i.base_reg | |
0dfbf9d7 L |
9104 | && operand_type_equal (&i.base_reg->reg_type, |
9105 | ®16_inoutportreg) | |
24eab124 AM |
9106 | && i.index_reg == 0 |
9107 | && i.log2_scale_factor == 0 | |
9108 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 9109 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 9110 | { |
65da13b5 | 9111 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
9112 | return 1; |
9113 | } | |
9114 | ||
eecb386c AM |
9115 | if (i386_index_check (operand_string) == 0) |
9116 | return 0; | |
5c07affc | 9117 | i.types[this_operand].bitfield.mem = 1; |
8325cc63 JB |
9118 | if (i.mem_operands == 0) |
9119 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
9120 | i.mem_operands++; |
9121 | } | |
9122 | else | |
ce8a8b2f AM |
9123 | { |
9124 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
9125 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
9126 | output_invalid (*op_string), | |
9127 | this_operand + 1, | |
9128 | op_string); | |
9129 | return 0; | |
9130 | } | |
47926f60 | 9131 | return 1; /* Normal return. */ |
252b5132 RH |
9132 | } |
9133 | \f | |
fa94de6b RM |
9134 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
9135 | that an rs_machine_dependent frag may reach. */ | |
9136 | ||
9137 | unsigned int | |
9138 | i386_frag_max_var (fragS *frag) | |
9139 | { | |
9140 | /* The only relaxable frags are for jumps. | |
9141 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
9142 | gas_assert (frag->fr_type == rs_machine_dependent); | |
9143 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
9144 | } | |
9145 | ||
b084df0b L |
9146 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9147 | static int | |
8dcea932 | 9148 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
9149 | { |
9150 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
9151 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
9152 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
9153 | return 0; | |
9154 | ||
9155 | if (!S_IS_EXTERNAL (fr_symbol)) | |
9156 | /* Symbol may be weak or local. */ | |
9157 | return !S_IS_WEAK (fr_symbol); | |
9158 | ||
8dcea932 L |
9159 | /* Global symbols with non-default visibility can't be preempted. */ |
9160 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
9161 | return 1; | |
9162 | ||
9163 | if (fr_var != NO_RELOC) | |
9164 | switch ((enum bfd_reloc_code_real) fr_var) | |
9165 | { | |
9166 | case BFD_RELOC_386_PLT32: | |
9167 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 9168 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
9169 | return 0; |
9170 | default: | |
9171 | abort (); | |
9172 | } | |
9173 | ||
b084df0b L |
9174 | /* Global symbols with default visibility in a shared library may be |
9175 | preempted by another definition. */ | |
8dcea932 | 9176 | return !shared; |
b084df0b L |
9177 | } |
9178 | #endif | |
9179 | ||
ee7fcc42 AM |
9180 | /* md_estimate_size_before_relax() |
9181 | ||
9182 | Called just before relax() for rs_machine_dependent frags. The x86 | |
9183 | assembler uses these frags to handle variable size jump | |
9184 | instructions. | |
9185 | ||
9186 | Any symbol that is now undefined will not become defined. | |
9187 | Return the correct fr_subtype in the frag. | |
9188 | Return the initial "guess for variable size of frag" to caller. | |
9189 | The guess is actually the growth beyond the fixed part. Whatever | |
9190 | we do to grow the fixed or variable part contributes to our | |
9191 | returned value. */ | |
9192 | ||
252b5132 | 9193 | int |
7016a5d5 | 9194 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 9195 | { |
252b5132 | 9196 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
9197 | check for un-relaxable symbols. On an ELF system, we can't relax |
9198 | an externally visible symbol, because it may be overridden by a | |
9199 | shared library. */ | |
9200 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 9201 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9202 | || (IS_ELF |
8dcea932 L |
9203 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
9204 | fragP->fr_var)) | |
fbeb56a4 DK |
9205 | #endif |
9206 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 9207 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 9208 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
9209 | #endif |
9210 | ) | |
252b5132 | 9211 | { |
b98ef147 AM |
9212 | /* Symbol is undefined in this segment, or we need to keep a |
9213 | reloc so that weak symbols can be overridden. */ | |
9214 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 9215 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
9216 | unsigned char *opcode; |
9217 | int old_fr_fix; | |
f6af82bd | 9218 | |
ee7fcc42 | 9219 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 9220 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 9221 | else if (size == 2) |
f6af82bd AM |
9222 | reloc_type = BFD_RELOC_16_PCREL; |
9223 | else | |
9224 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 9225 | |
ee7fcc42 AM |
9226 | old_fr_fix = fragP->fr_fix; |
9227 | opcode = (unsigned char *) fragP->fr_opcode; | |
9228 | ||
fddf5b5b | 9229 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 9230 | { |
fddf5b5b AM |
9231 | case UNCOND_JUMP: |
9232 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 9233 | opcode[0] = 0xe9; |
252b5132 | 9234 | fragP->fr_fix += size; |
062cd5e7 AS |
9235 | fix_new (fragP, old_fr_fix, size, |
9236 | fragP->fr_symbol, | |
9237 | fragP->fr_offset, 1, | |
9238 | reloc_type); | |
252b5132 RH |
9239 | break; |
9240 | ||
fddf5b5b | 9241 | case COND_JUMP86: |
412167cb AM |
9242 | if (size == 2 |
9243 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
9244 | { |
9245 | /* Negate the condition, and branch past an | |
9246 | unconditional jump. */ | |
9247 | opcode[0] ^= 1; | |
9248 | opcode[1] = 3; | |
9249 | /* Insert an unconditional jump. */ | |
9250 | opcode[2] = 0xe9; | |
9251 | /* We added two extra opcode bytes, and have a two byte | |
9252 | offset. */ | |
9253 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
9254 | fix_new (fragP, old_fr_fix + 2, 2, |
9255 | fragP->fr_symbol, | |
9256 | fragP->fr_offset, 1, | |
9257 | reloc_type); | |
fddf5b5b AM |
9258 | break; |
9259 | } | |
9260 | /* Fall through. */ | |
9261 | ||
9262 | case COND_JUMP: | |
412167cb AM |
9263 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
9264 | { | |
3e02c1cc AM |
9265 | fixS *fixP; |
9266 | ||
412167cb | 9267 | fragP->fr_fix += 1; |
3e02c1cc AM |
9268 | fixP = fix_new (fragP, old_fr_fix, 1, |
9269 | fragP->fr_symbol, | |
9270 | fragP->fr_offset, 1, | |
9271 | BFD_RELOC_8_PCREL); | |
9272 | fixP->fx_signed = 1; | |
412167cb AM |
9273 | break; |
9274 | } | |
93c2a809 | 9275 | |
24eab124 | 9276 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 9277 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 9278 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 9279 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
9280 | /* We've added an opcode byte. */ |
9281 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
9282 | fix_new (fragP, old_fr_fix + 1, size, |
9283 | fragP->fr_symbol, | |
9284 | fragP->fr_offset, 1, | |
9285 | reloc_type); | |
252b5132 | 9286 | break; |
fddf5b5b AM |
9287 | |
9288 | default: | |
9289 | BAD_CASE (fragP->fr_subtype); | |
9290 | break; | |
252b5132 RH |
9291 | } |
9292 | frag_wane (fragP); | |
ee7fcc42 | 9293 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 9294 | } |
93c2a809 | 9295 | |
93c2a809 AM |
9296 | /* Guess size depending on current relax state. Initially the relax |
9297 | state will correspond to a short jump and we return 1, because | |
9298 | the variable part of the frag (the branch offset) is one byte | |
9299 | long. However, we can relax a section more than once and in that | |
9300 | case we must either set fr_subtype back to the unrelaxed state, | |
9301 | or return the value for the appropriate branch. */ | |
9302 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
9303 | } |
9304 | ||
47926f60 KH |
9305 | /* Called after relax() is finished. |
9306 | ||
9307 | In: Address of frag. | |
9308 | fr_type == rs_machine_dependent. | |
9309 | fr_subtype is what the address relaxed to. | |
9310 | ||
9311 | Out: Any fixSs and constants are set up. | |
9312 | Caller will turn frag into a ".space 0". */ | |
9313 | ||
252b5132 | 9314 | void |
7016a5d5 TG |
9315 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
9316 | fragS *fragP) | |
252b5132 | 9317 | { |
29b0f896 | 9318 | unsigned char *opcode; |
252b5132 | 9319 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
9320 | offsetT target_address; |
9321 | offsetT opcode_address; | |
252b5132 | 9322 | unsigned int extension = 0; |
847f7ad4 | 9323 | offsetT displacement_from_opcode_start; |
252b5132 RH |
9324 | |
9325 | opcode = (unsigned char *) fragP->fr_opcode; | |
9326 | ||
47926f60 | 9327 | /* Address we want to reach in file space. */ |
252b5132 | 9328 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 9329 | |
47926f60 | 9330 | /* Address opcode resides at in file space. */ |
252b5132 RH |
9331 | opcode_address = fragP->fr_address + fragP->fr_fix; |
9332 | ||
47926f60 | 9333 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
9334 | displacement_from_opcode_start = target_address - opcode_address; |
9335 | ||
fddf5b5b | 9336 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 9337 | { |
47926f60 KH |
9338 | /* Don't have to change opcode. */ |
9339 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 9340 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
9341 | } |
9342 | else | |
9343 | { | |
9344 | if (no_cond_jump_promotion | |
9345 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
9346 | as_warn_where (fragP->fr_file, fragP->fr_line, |
9347 | _("long jump required")); | |
252b5132 | 9348 | |
fddf5b5b AM |
9349 | switch (fragP->fr_subtype) |
9350 | { | |
9351 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
9352 | extension = 4; /* 1 opcode + 4 displacement */ | |
9353 | opcode[0] = 0xe9; | |
9354 | where_to_put_displacement = &opcode[1]; | |
9355 | break; | |
252b5132 | 9356 | |
fddf5b5b AM |
9357 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
9358 | extension = 2; /* 1 opcode + 2 displacement */ | |
9359 | opcode[0] = 0xe9; | |
9360 | where_to_put_displacement = &opcode[1]; | |
9361 | break; | |
252b5132 | 9362 | |
fddf5b5b AM |
9363 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
9364 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
9365 | extension = 5; /* 2 opcode + 4 displacement */ | |
9366 | opcode[1] = opcode[0] + 0x10; | |
9367 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9368 | where_to_put_displacement = &opcode[2]; | |
9369 | break; | |
252b5132 | 9370 | |
fddf5b5b AM |
9371 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
9372 | extension = 3; /* 2 opcode + 2 displacement */ | |
9373 | opcode[1] = opcode[0] + 0x10; | |
9374 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9375 | where_to_put_displacement = &opcode[2]; | |
9376 | break; | |
252b5132 | 9377 | |
fddf5b5b AM |
9378 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
9379 | extension = 4; | |
9380 | opcode[0] ^= 1; | |
9381 | opcode[1] = 3; | |
9382 | opcode[2] = 0xe9; | |
9383 | where_to_put_displacement = &opcode[3]; | |
9384 | break; | |
9385 | ||
9386 | default: | |
9387 | BAD_CASE (fragP->fr_subtype); | |
9388 | break; | |
9389 | } | |
252b5132 | 9390 | } |
fddf5b5b | 9391 | |
7b81dfbb AJ |
9392 | /* If size if less then four we are sure that the operand fits, |
9393 | but if it's 4, then it could be that the displacement is larger | |
9394 | then -/+ 2GB. */ | |
9395 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
9396 | && object_64bit | |
9397 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
9398 | + ((addressT) 1 << 31)) |
9399 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
9400 | { |
9401 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9402 | _("jump target out of range")); | |
9403 | /* Make us emit 0. */ | |
9404 | displacement_from_opcode_start = extension; | |
9405 | } | |
47926f60 | 9406 | /* Now put displacement after opcode. */ |
252b5132 RH |
9407 | md_number_to_chars ((char *) where_to_put_displacement, |
9408 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 9409 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
9410 | fragP->fr_fix += extension; |
9411 | } | |
9412 | \f | |
7016a5d5 | 9413 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
9414 | by our caller that we have all the info we need to fix it up. |
9415 | ||
7016a5d5 TG |
9416 | Parameter valP is the pointer to the value of the bits. |
9417 | ||
252b5132 RH |
9418 | On the 386, immediates, displacements, and data pointers are all in |
9419 | the same (little-endian) format, so we don't need to care about which | |
9420 | we are handling. */ | |
9421 | ||
94f592af | 9422 | void |
7016a5d5 | 9423 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 9424 | { |
94f592af | 9425 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 9426 | valueT value = *valP; |
252b5132 | 9427 | |
f86103b7 | 9428 | #if !defined (TE_Mach) |
93382f6d AM |
9429 | if (fixP->fx_pcrel) |
9430 | { | |
9431 | switch (fixP->fx_r_type) | |
9432 | { | |
5865bb77 ILT |
9433 | default: |
9434 | break; | |
9435 | ||
d6ab8113 JB |
9436 | case BFD_RELOC_64: |
9437 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
9438 | break; | |
93382f6d | 9439 | case BFD_RELOC_32: |
ae8887b5 | 9440 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
9441 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
9442 | break; | |
9443 | case BFD_RELOC_16: | |
9444 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
9445 | break; | |
9446 | case BFD_RELOC_8: | |
9447 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
9448 | break; | |
9449 | } | |
9450 | } | |
252b5132 | 9451 | |
a161fe53 | 9452 | if (fixP->fx_addsy != NULL |
31312f95 | 9453 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 9454 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 9455 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 9456 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 9457 | && !use_rela_relocations) |
252b5132 | 9458 | { |
31312f95 AM |
9459 | /* This is a hack. There should be a better way to handle this. |
9460 | This covers for the fact that bfd_install_relocation will | |
9461 | subtract the current location (for partial_inplace, PC relative | |
9462 | relocations); see more below. */ | |
252b5132 | 9463 | #ifndef OBJ_AOUT |
718ddfc0 | 9464 | if (IS_ELF |
252b5132 RH |
9465 | #ifdef TE_PE |
9466 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
9467 | #endif | |
9468 | ) | |
9469 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9470 | #endif | |
9471 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 9472 | if (IS_ELF) |
252b5132 | 9473 | { |
6539b54b | 9474 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 9475 | |
6539b54b | 9476 | if ((sym_seg == seg |
2f66722d | 9477 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 9478 | && sym_seg != absolute_section)) |
af65af87 | 9479 | && !generic_force_reloc (fixP)) |
2f66722d AM |
9480 | { |
9481 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
9482 | bfd_install_relocation subtracts them out again. I think |
9483 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
9484 | it. FIXME. */ |
9485 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9486 | } | |
252b5132 RH |
9487 | } |
9488 | #endif | |
9489 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
9490 | /* For some reason, the PE format does not store a |
9491 | section address offset for a PC relative symbol. */ | |
9492 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 9493 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
9494 | value += md_pcrel_from (fixP); |
9495 | #endif | |
9496 | } | |
fbeb56a4 | 9497 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
9498 | if (fixP->fx_addsy != NULL |
9499 | && S_IS_WEAK (fixP->fx_addsy) | |
9500 | /* PR 16858: Do not modify weak function references. */ | |
9501 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 9502 | { |
296a8689 NC |
9503 | #if !defined (TE_PEP) |
9504 | /* For x86 PE weak function symbols are neither PC-relative | |
9505 | nor do they set S_IS_FUNCTION. So the only reliable way | |
9506 | to detect them is to check the flags of their containing | |
9507 | section. */ | |
9508 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
9509 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
9510 | ; | |
9511 | else | |
9512 | #endif | |
fbeb56a4 DK |
9513 | value -= S_GET_VALUE (fixP->fx_addsy); |
9514 | } | |
9515 | #endif | |
252b5132 RH |
9516 | |
9517 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 9518 | and we must not disappoint it. */ |
252b5132 | 9519 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9520 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
9521 | switch (fixP->fx_r_type) |
9522 | { | |
9523 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 9524 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
9525 | /* Make the jump instruction point to the address of the operand. At |
9526 | runtime we merely add the offset to the actual PLT entry. */ | |
9527 | value = -4; | |
9528 | break; | |
31312f95 | 9529 | |
13ae64f3 JJ |
9530 | case BFD_RELOC_386_TLS_GD: |
9531 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 9532 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
9533 | case BFD_RELOC_386_TLS_IE: |
9534 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 9535 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
9536 | case BFD_RELOC_X86_64_TLSGD: |
9537 | case BFD_RELOC_X86_64_TLSLD: | |
9538 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 9539 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
9540 | value = 0; /* Fully resolved at runtime. No addend. */ |
9541 | /* Fallthrough */ | |
9542 | case BFD_RELOC_386_TLS_LE: | |
9543 | case BFD_RELOC_386_TLS_LDO_32: | |
9544 | case BFD_RELOC_386_TLS_LE_32: | |
9545 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 9546 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 9547 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 9548 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
9549 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
9550 | break; | |
9551 | ||
67a4f2b7 AO |
9552 | case BFD_RELOC_386_TLS_DESC_CALL: |
9553 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9554 | value = 0; /* Fully resolved at runtime. No addend. */ | |
9555 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
9556 | fixP->fx_done = 0; | |
9557 | return; | |
9558 | ||
47926f60 KH |
9559 | case BFD_RELOC_VTABLE_INHERIT: |
9560 | case BFD_RELOC_VTABLE_ENTRY: | |
9561 | fixP->fx_done = 0; | |
94f592af | 9562 | return; |
47926f60 KH |
9563 | |
9564 | default: | |
9565 | break; | |
9566 | } | |
9567 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 9568 | *valP = value; |
f86103b7 | 9569 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 9570 | |
3e73aa7c | 9571 | /* Are we finished with this relocation now? */ |
c6682705 | 9572 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 9573 | fixP->fx_done = 1; |
fbeb56a4 DK |
9574 | #if defined (OBJ_COFF) && defined (TE_PE) |
9575 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
9576 | { | |
9577 | fixP->fx_done = 0; | |
9578 | /* Remember value for tc_gen_reloc. */ | |
9579 | fixP->fx_addnumber = value; | |
9580 | /* Clear out the frag for now. */ | |
9581 | value = 0; | |
9582 | } | |
9583 | #endif | |
3e73aa7c JH |
9584 | else if (use_rela_relocations) |
9585 | { | |
9586 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
9587 | /* Remember value for tc_gen_reloc. */ |
9588 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
9589 | value = 0; |
9590 | } | |
f86103b7 | 9591 | |
94f592af | 9592 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 9593 | } |
252b5132 | 9594 | \f |
6d4af3c2 | 9595 | const char * |
499ac353 | 9596 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 9597 | { |
499ac353 NC |
9598 | /* This outputs the LITTLENUMs in REVERSE order; |
9599 | in accord with the bigendian 386. */ | |
9600 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
9601 | } |
9602 | \f | |
2d545b82 | 9603 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 9604 | |
252b5132 | 9605 | static char * |
e3bb37b5 | 9606 | output_invalid (int c) |
252b5132 | 9607 | { |
3882b010 | 9608 | if (ISPRINT (c)) |
f9f21a03 L |
9609 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
9610 | "'%c'", c); | |
252b5132 | 9611 | else |
f9f21a03 | 9612 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 9613 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
9614 | return output_invalid_buf; |
9615 | } | |
9616 | ||
af6bdddf | 9617 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
9618 | |
9619 | static const reg_entry * | |
4d1bb795 | 9620 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 9621 | { |
af6bdddf AM |
9622 | char *s = reg_string; |
9623 | char *p; | |
252b5132 RH |
9624 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
9625 | const reg_entry *r; | |
9626 | ||
9627 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
9628 | if (*s == REGISTER_PREFIX) | |
9629 | ++s; | |
9630 | ||
9631 | if (is_space_char (*s)) | |
9632 | ++s; | |
9633 | ||
9634 | p = reg_name_given; | |
af6bdddf | 9635 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
9636 | { |
9637 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
9638 | return (const reg_entry *) NULL; |
9639 | s++; | |
252b5132 RH |
9640 | } |
9641 | ||
6588847e DN |
9642 | /* For naked regs, make sure that we are not dealing with an identifier. |
9643 | This prevents confusing an identifier like `eax_var' with register | |
9644 | `eax'. */ | |
9645 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
9646 | return (const reg_entry *) NULL; | |
9647 | ||
af6bdddf | 9648 | *end_op = s; |
252b5132 RH |
9649 | |
9650 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
9651 | ||
5f47d35b | 9652 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 9653 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 9654 | { |
5f47d35b AM |
9655 | if (is_space_char (*s)) |
9656 | ++s; | |
9657 | if (*s == '(') | |
9658 | { | |
af6bdddf | 9659 | ++s; |
5f47d35b AM |
9660 | if (is_space_char (*s)) |
9661 | ++s; | |
9662 | if (*s >= '0' && *s <= '7') | |
9663 | { | |
db557034 | 9664 | int fpr = *s - '0'; |
af6bdddf | 9665 | ++s; |
5f47d35b AM |
9666 | if (is_space_char (*s)) |
9667 | ++s; | |
9668 | if (*s == ')') | |
9669 | { | |
9670 | *end_op = s + 1; | |
1e9cc1c2 | 9671 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
9672 | know (r); |
9673 | return r + fpr; | |
5f47d35b | 9674 | } |
5f47d35b | 9675 | } |
47926f60 | 9676 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
9677 | return (const reg_entry *) NULL; |
9678 | } | |
9679 | } | |
9680 | ||
a60de03c JB |
9681 | if (r == NULL || allow_pseudo_reg) |
9682 | return r; | |
9683 | ||
0dfbf9d7 | 9684 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
9685 | return (const reg_entry *) NULL; |
9686 | ||
192dc9c6 JB |
9687 | if ((r->reg_type.bitfield.reg32 |
9688 | || r->reg_type.bitfield.sreg3 | |
9689 | || r->reg_type.bitfield.control | |
9690 | || r->reg_type.bitfield.debug | |
9691 | || r->reg_type.bitfield.test) | |
9692 | && !cpu_arch_flags.bitfield.cpui386) | |
9693 | return (const reg_entry *) NULL; | |
9694 | ||
309d3373 JB |
9695 | if (r->reg_type.bitfield.floatreg |
9696 | && !cpu_arch_flags.bitfield.cpu8087 | |
9697 | && !cpu_arch_flags.bitfield.cpu287 | |
9698 | && !cpu_arch_flags.bitfield.cpu387) | |
9699 | return (const reg_entry *) NULL; | |
9700 | ||
1848e567 | 9701 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx) |
192dc9c6 JB |
9702 | return (const reg_entry *) NULL; |
9703 | ||
1848e567 | 9704 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm) |
192dc9c6 JB |
9705 | return (const reg_entry *) NULL; |
9706 | ||
1848e567 | 9707 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm) |
40f12533 L |
9708 | return (const reg_entry *) NULL; |
9709 | ||
1848e567 L |
9710 | if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm) |
9711 | return (const reg_entry *) NULL; | |
9712 | ||
9713 | if (r->reg_type.bitfield.regmask | |
9714 | && !cpu_arch_flags.bitfield.cpuregmask) | |
43234a1e L |
9715 | return (const reg_entry *) NULL; |
9716 | ||
db51cc60 | 9717 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 9718 | if (!allow_index_reg |
db51cc60 L |
9719 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
9720 | return (const reg_entry *) NULL; | |
9721 | ||
43234a1e L |
9722 | /* Upper 16 vector register is only available with VREX in 64bit |
9723 | mode. */ | |
9724 | if ((r->reg_flags & RegVRex)) | |
9725 | { | |
9726 | if (!cpu_arch_flags.bitfield.cpuvrex | |
9727 | || flag_code != CODE_64BIT) | |
9728 | return (const reg_entry *) NULL; | |
9729 | ||
9730 | i.need_vrex = 1; | |
9731 | } | |
9732 | ||
a60de03c JB |
9733 | if (((r->reg_flags & (RegRex64 | RegRex)) |
9734 | || r->reg_type.bitfield.reg64) | |
40fb9820 | 9735 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 9736 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 9737 | && flag_code != CODE_64BIT) |
20f0a1fc | 9738 | return (const reg_entry *) NULL; |
1ae00879 | 9739 | |
b7240065 JB |
9740 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
9741 | return (const reg_entry *) NULL; | |
9742 | ||
252b5132 RH |
9743 | return r; |
9744 | } | |
4d1bb795 JB |
9745 | |
9746 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
9747 | ||
9748 | static const reg_entry * | |
9749 | parse_register (char *reg_string, char **end_op) | |
9750 | { | |
9751 | const reg_entry *r; | |
9752 | ||
9753 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
9754 | r = parse_real_register (reg_string, end_op); | |
9755 | else | |
9756 | r = NULL; | |
9757 | if (!r) | |
9758 | { | |
9759 | char *save = input_line_pointer; | |
9760 | char c; | |
9761 | symbolS *symbolP; | |
9762 | ||
9763 | input_line_pointer = reg_string; | |
d02603dc | 9764 | c = get_symbol_name (®_string); |
4d1bb795 JB |
9765 | symbolP = symbol_find (reg_string); |
9766 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
9767 | { | |
9768 | const expressionS *e = symbol_get_value_expression (symbolP); | |
9769 | ||
0398aac5 | 9770 | know (e->X_op == O_register); |
4eed87de | 9771 | know (e->X_add_number >= 0 |
c3fe08fa | 9772 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 9773 | r = i386_regtab + e->X_add_number; |
d3bb6b49 IT |
9774 | if ((r->reg_flags & RegVRex)) |
9775 | i.need_vrex = 1; | |
4d1bb795 JB |
9776 | *end_op = input_line_pointer; |
9777 | } | |
9778 | *input_line_pointer = c; | |
9779 | input_line_pointer = save; | |
9780 | } | |
9781 | return r; | |
9782 | } | |
9783 | ||
9784 | int | |
9785 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
9786 | { | |
9787 | const reg_entry *r; | |
9788 | char *end = input_line_pointer; | |
9789 | ||
9790 | *end = *nextcharP; | |
9791 | r = parse_register (name, &input_line_pointer); | |
9792 | if (r && end <= input_line_pointer) | |
9793 | { | |
9794 | *nextcharP = *input_line_pointer; | |
9795 | *input_line_pointer = 0; | |
9796 | e->X_op = O_register; | |
9797 | e->X_add_number = r - i386_regtab; | |
9798 | return 1; | |
9799 | } | |
9800 | input_line_pointer = end; | |
9801 | *end = 0; | |
ee86248c | 9802 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
9803 | } |
9804 | ||
9805 | void | |
9806 | md_operand (expressionS *e) | |
9807 | { | |
ee86248c JB |
9808 | char *end; |
9809 | const reg_entry *r; | |
4d1bb795 | 9810 | |
ee86248c JB |
9811 | switch (*input_line_pointer) |
9812 | { | |
9813 | case REGISTER_PREFIX: | |
9814 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
9815 | if (r) |
9816 | { | |
9817 | e->X_op = O_register; | |
9818 | e->X_add_number = r - i386_regtab; | |
9819 | input_line_pointer = end; | |
9820 | } | |
ee86248c JB |
9821 | break; |
9822 | ||
9823 | case '[': | |
9c2799c2 | 9824 | gas_assert (intel_syntax); |
ee86248c JB |
9825 | end = input_line_pointer++; |
9826 | expression (e); | |
9827 | if (*input_line_pointer == ']') | |
9828 | { | |
9829 | ++input_line_pointer; | |
9830 | e->X_op_symbol = make_expr_symbol (e); | |
9831 | e->X_add_symbol = NULL; | |
9832 | e->X_add_number = 0; | |
9833 | e->X_op = O_index; | |
9834 | } | |
9835 | else | |
9836 | { | |
9837 | e->X_op = O_absent; | |
9838 | input_line_pointer = end; | |
9839 | } | |
9840 | break; | |
4d1bb795 JB |
9841 | } |
9842 | } | |
9843 | ||
252b5132 | 9844 | \f |
4cc782b5 | 9845 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 9846 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 9847 | #else |
12b55ccc | 9848 | const char *md_shortopts = "qn"; |
252b5132 | 9849 | #endif |
6e0b89ee | 9850 | |
3e73aa7c | 9851 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
9852 | #define OPTION_64 (OPTION_MD_BASE + 1) |
9853 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
9854 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
9855 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
9856 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
9857 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
9858 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
9859 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
9860 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 9861 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 9862 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
9863 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
9864 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
9865 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 9866 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
9867 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
9868 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 9869 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 9870 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 9871 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 9872 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
9873 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
9874 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 9875 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
0cb4071e | 9876 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25) |
b3b91714 | 9877 | |
99ad8390 NC |
9878 | struct option md_longopts[] = |
9879 | { | |
3e73aa7c | 9880 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 9881 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 9882 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 9883 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
9884 | #endif |
9885 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 9886 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 9887 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
6e0b89ee | 9888 | #endif |
b3b91714 | 9889 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
9890 | {"march", required_argument, NULL, OPTION_MARCH}, |
9891 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
9892 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
9893 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
9894 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
9895 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
9896 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 9897 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 9898 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 9899 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 9900 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
7e8b059b | 9901 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
9902 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
9903 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
9904 | # if defined (TE_PE) || defined (TE_PEP) |
9905 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
9906 | #endif | |
d1982f93 | 9907 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 9908 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 9909 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 9910 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
9911 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
9912 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
9913 | {NULL, no_argument, NULL, 0} |
9914 | }; | |
9915 | size_t md_longopts_size = sizeof (md_longopts); | |
9916 | ||
9917 | int | |
17b9d67d | 9918 | md_parse_option (int c, const char *arg) |
252b5132 | 9919 | { |
91d6fa6a | 9920 | unsigned int j; |
293f5f65 | 9921 | char *arch, *next, *saved; |
9103f4f4 | 9922 | |
252b5132 RH |
9923 | switch (c) |
9924 | { | |
12b55ccc L |
9925 | case 'n': |
9926 | optimize_align_code = 0; | |
9927 | break; | |
9928 | ||
a38cf1db AM |
9929 | case 'q': |
9930 | quiet_warnings = 1; | |
252b5132 RH |
9931 | break; |
9932 | ||
9933 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
9934 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
9935 | should be emitted or not. FIXME: Not implemented. */ | |
9936 | case 'Q': | |
252b5132 RH |
9937 | break; |
9938 | ||
9939 | /* -V: SVR4 argument to print version ID. */ | |
9940 | case 'V': | |
9941 | print_version_id (); | |
9942 | break; | |
9943 | ||
a38cf1db AM |
9944 | /* -k: Ignore for FreeBSD compatibility. */ |
9945 | case 'k': | |
252b5132 | 9946 | break; |
4cc782b5 ILT |
9947 | |
9948 | case 's': | |
9949 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 9950 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 9951 | break; |
8dcea932 L |
9952 | |
9953 | case OPTION_MSHARED: | |
9954 | shared = 1; | |
9955 | break; | |
99ad8390 | 9956 | #endif |
321098a5 | 9957 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 9958 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
9959 | case OPTION_64: |
9960 | { | |
9961 | const char **list, **l; | |
9962 | ||
3e73aa7c JH |
9963 | list = bfd_target_list (); |
9964 | for (l = list; *l != NULL; l++) | |
8620418b | 9965 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
9966 | || strcmp (*l, "coff-x86-64") == 0 |
9967 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
9968 | || strcmp (*l, "pei-x86-64") == 0 |
9969 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
9970 | { |
9971 | default_arch = "x86_64"; | |
9972 | break; | |
9973 | } | |
3e73aa7c | 9974 | if (*l == NULL) |
2b5d6a91 | 9975 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
9976 | free (list); |
9977 | } | |
9978 | break; | |
9979 | #endif | |
252b5132 | 9980 | |
351f65ca | 9981 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 9982 | case OPTION_X32: |
351f65ca L |
9983 | if (IS_ELF) |
9984 | { | |
9985 | const char **list, **l; | |
9986 | ||
9987 | list = bfd_target_list (); | |
9988 | for (l = list; *l != NULL; l++) | |
9989 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
9990 | { | |
9991 | default_arch = "x86_64:32"; | |
9992 | break; | |
9993 | } | |
9994 | if (*l == NULL) | |
2b5d6a91 | 9995 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
9996 | free (list); |
9997 | } | |
9998 | else | |
9999 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
10000 | break; | |
10001 | #endif | |
10002 | ||
6e0b89ee AM |
10003 | case OPTION_32: |
10004 | default_arch = "i386"; | |
10005 | break; | |
10006 | ||
b3b91714 AM |
10007 | case OPTION_DIVIDE: |
10008 | #ifdef SVR4_COMMENT_CHARS | |
10009 | { | |
10010 | char *n, *t; | |
10011 | const char *s; | |
10012 | ||
add39d23 | 10013 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
10014 | t = n; |
10015 | for (s = i386_comment_chars; *s != '\0'; s++) | |
10016 | if (*s != '/') | |
10017 | *t++ = *s; | |
10018 | *t = '\0'; | |
10019 | i386_comment_chars = n; | |
10020 | } | |
10021 | #endif | |
10022 | break; | |
10023 | ||
9103f4f4 | 10024 | case OPTION_MARCH: |
293f5f65 L |
10025 | saved = xstrdup (arg); |
10026 | arch = saved; | |
10027 | /* Allow -march=+nosse. */ | |
10028 | if (*arch == '+') | |
10029 | arch++; | |
6305a203 | 10030 | do |
9103f4f4 | 10031 | { |
6305a203 | 10032 | if (*arch == '.') |
2b5d6a91 | 10033 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10034 | next = strchr (arch, '+'); |
10035 | if (next) | |
10036 | *next++ = '\0'; | |
91d6fa6a | 10037 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10038 | { |
91d6fa6a | 10039 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 10040 | { |
6305a203 | 10041 | /* Processor. */ |
1ded5609 JB |
10042 | if (! cpu_arch[j].flags.bitfield.cpui386) |
10043 | continue; | |
10044 | ||
91d6fa6a | 10045 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 10046 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
10047 | cpu_arch_flags = cpu_arch[j].flags; |
10048 | cpu_arch_isa = cpu_arch[j].type; | |
10049 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
10050 | if (!cpu_arch_tune_set) |
10051 | { | |
10052 | cpu_arch_tune = cpu_arch_isa; | |
10053 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10054 | } | |
10055 | break; | |
10056 | } | |
91d6fa6a NC |
10057 | else if (*cpu_arch [j].name == '.' |
10058 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 10059 | { |
33eaf5de | 10060 | /* ISA extension. */ |
6305a203 | 10061 | i386_cpu_flags flags; |
309d3373 | 10062 | |
293f5f65 L |
10063 | flags = cpu_flags_or (cpu_arch_flags, |
10064 | cpu_arch[j].flags); | |
81486035 | 10065 | |
5b64d091 | 10066 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
10067 | { |
10068 | if (cpu_sub_arch_name) | |
10069 | { | |
10070 | char *name = cpu_sub_arch_name; | |
10071 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 10072 | cpu_arch[j].name, |
1bf57e9f | 10073 | (const char *) NULL); |
6305a203 L |
10074 | free (name); |
10075 | } | |
10076 | else | |
91d6fa6a | 10077 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 10078 | cpu_arch_flags = flags; |
a586129e | 10079 | cpu_arch_isa_flags = flags; |
6305a203 L |
10080 | } |
10081 | break; | |
ccc9c027 | 10082 | } |
9103f4f4 | 10083 | } |
6305a203 | 10084 | |
293f5f65 L |
10085 | if (j >= ARRAY_SIZE (cpu_arch)) |
10086 | { | |
33eaf5de | 10087 | /* Disable an ISA extension. */ |
293f5f65 L |
10088 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
10089 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
10090 | { | |
10091 | i386_cpu_flags flags; | |
10092 | ||
10093 | flags = cpu_flags_and_not (cpu_arch_flags, | |
10094 | cpu_noarch[j].flags); | |
10095 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
10096 | { | |
10097 | if (cpu_sub_arch_name) | |
10098 | { | |
10099 | char *name = cpu_sub_arch_name; | |
10100 | cpu_sub_arch_name = concat (arch, | |
10101 | (const char *) NULL); | |
10102 | free (name); | |
10103 | } | |
10104 | else | |
10105 | cpu_sub_arch_name = xstrdup (arch); | |
10106 | cpu_arch_flags = flags; | |
10107 | cpu_arch_isa_flags = flags; | |
10108 | } | |
10109 | break; | |
10110 | } | |
10111 | ||
10112 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
10113 | j = ARRAY_SIZE (cpu_arch); | |
10114 | } | |
10115 | ||
91d6fa6a | 10116 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10117 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10118 | |
10119 | arch = next; | |
9103f4f4 | 10120 | } |
293f5f65 L |
10121 | while (next != NULL); |
10122 | free (saved); | |
9103f4f4 L |
10123 | break; |
10124 | ||
10125 | case OPTION_MTUNE: | |
10126 | if (*arg == '.') | |
2b5d6a91 | 10127 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 10128 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10129 | { |
91d6fa6a | 10130 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 10131 | { |
ccc9c027 | 10132 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
10133 | cpu_arch_tune = cpu_arch [j].type; |
10134 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
10135 | break; |
10136 | } | |
10137 | } | |
91d6fa6a | 10138 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10139 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
10140 | break; |
10141 | ||
1efbbeb4 L |
10142 | case OPTION_MMNEMONIC: |
10143 | if (strcasecmp (arg, "att") == 0) | |
10144 | intel_mnemonic = 0; | |
10145 | else if (strcasecmp (arg, "intel") == 0) | |
10146 | intel_mnemonic = 1; | |
10147 | else | |
2b5d6a91 | 10148 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
10149 | break; |
10150 | ||
10151 | case OPTION_MSYNTAX: | |
10152 | if (strcasecmp (arg, "att") == 0) | |
10153 | intel_syntax = 0; | |
10154 | else if (strcasecmp (arg, "intel") == 0) | |
10155 | intel_syntax = 1; | |
10156 | else | |
2b5d6a91 | 10157 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
10158 | break; |
10159 | ||
10160 | case OPTION_MINDEX_REG: | |
10161 | allow_index_reg = 1; | |
10162 | break; | |
10163 | ||
10164 | case OPTION_MNAKED_REG: | |
10165 | allow_naked_reg = 1; | |
10166 | break; | |
10167 | ||
10168 | case OPTION_MOLD_GCC: | |
10169 | old_gcc = 1; | |
1efbbeb4 L |
10170 | break; |
10171 | ||
c0f3af97 L |
10172 | case OPTION_MSSE2AVX: |
10173 | sse2avx = 1; | |
10174 | break; | |
10175 | ||
daf50ae7 L |
10176 | case OPTION_MSSE_CHECK: |
10177 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 10178 | sse_check = check_error; |
daf50ae7 | 10179 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 10180 | sse_check = check_warning; |
daf50ae7 | 10181 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 10182 | sse_check = check_none; |
daf50ae7 | 10183 | else |
2b5d6a91 | 10184 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
10185 | break; |
10186 | ||
7bab8ab5 JB |
10187 | case OPTION_MOPERAND_CHECK: |
10188 | if (strcasecmp (arg, "error") == 0) | |
10189 | operand_check = check_error; | |
10190 | else if (strcasecmp (arg, "warning") == 0) | |
10191 | operand_check = check_warning; | |
10192 | else if (strcasecmp (arg, "none") == 0) | |
10193 | operand_check = check_none; | |
10194 | else | |
10195 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
10196 | break; | |
10197 | ||
539f890d L |
10198 | case OPTION_MAVXSCALAR: |
10199 | if (strcasecmp (arg, "128") == 0) | |
10200 | avxscalar = vex128; | |
10201 | else if (strcasecmp (arg, "256") == 0) | |
10202 | avxscalar = vex256; | |
10203 | else | |
2b5d6a91 | 10204 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
10205 | break; |
10206 | ||
7e8b059b L |
10207 | case OPTION_MADD_BND_PREFIX: |
10208 | add_bnd_prefix = 1; | |
10209 | break; | |
10210 | ||
43234a1e L |
10211 | case OPTION_MEVEXLIG: |
10212 | if (strcmp (arg, "128") == 0) | |
10213 | evexlig = evexl128; | |
10214 | else if (strcmp (arg, "256") == 0) | |
10215 | evexlig = evexl256; | |
10216 | else if (strcmp (arg, "512") == 0) | |
10217 | evexlig = evexl512; | |
10218 | else | |
10219 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
10220 | break; | |
10221 | ||
d3d3c6db IT |
10222 | case OPTION_MEVEXRCIG: |
10223 | if (strcmp (arg, "rne") == 0) | |
10224 | evexrcig = rne; | |
10225 | else if (strcmp (arg, "rd") == 0) | |
10226 | evexrcig = rd; | |
10227 | else if (strcmp (arg, "ru") == 0) | |
10228 | evexrcig = ru; | |
10229 | else if (strcmp (arg, "rz") == 0) | |
10230 | evexrcig = rz; | |
10231 | else | |
10232 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
10233 | break; | |
10234 | ||
43234a1e L |
10235 | case OPTION_MEVEXWIG: |
10236 | if (strcmp (arg, "0") == 0) | |
10237 | evexwig = evexw0; | |
10238 | else if (strcmp (arg, "1") == 0) | |
10239 | evexwig = evexw1; | |
10240 | else | |
10241 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
10242 | break; | |
10243 | ||
167ad85b TG |
10244 | # if defined (TE_PE) || defined (TE_PEP) |
10245 | case OPTION_MBIG_OBJ: | |
10246 | use_big_obj = 1; | |
10247 | break; | |
10248 | #endif | |
10249 | ||
d1982f93 | 10250 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
10251 | if (strcasecmp (arg, "yes") == 0) |
10252 | omit_lock_prefix = 1; | |
10253 | else if (strcasecmp (arg, "no") == 0) | |
10254 | omit_lock_prefix = 0; | |
10255 | else | |
10256 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
10257 | break; | |
10258 | ||
e4e00185 AS |
10259 | case OPTION_MFENCE_AS_LOCK_ADD: |
10260 | if (strcasecmp (arg, "yes") == 0) | |
10261 | avoid_fence = 1; | |
10262 | else if (strcasecmp (arg, "no") == 0) | |
10263 | avoid_fence = 0; | |
10264 | else | |
10265 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
10266 | break; | |
10267 | ||
0cb4071e L |
10268 | case OPTION_MRELAX_RELOCATIONS: |
10269 | if (strcasecmp (arg, "yes") == 0) | |
10270 | generate_relax_relocations = 1; | |
10271 | else if (strcasecmp (arg, "no") == 0) | |
10272 | generate_relax_relocations = 0; | |
10273 | else | |
10274 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
10275 | break; | |
10276 | ||
5db04b09 | 10277 | case OPTION_MAMD64: |
e89c5eaa | 10278 | intel64 = 0; |
5db04b09 L |
10279 | break; |
10280 | ||
10281 | case OPTION_MINTEL64: | |
e89c5eaa | 10282 | intel64 = 1; |
5db04b09 L |
10283 | break; |
10284 | ||
252b5132 RH |
10285 | default: |
10286 | return 0; | |
10287 | } | |
10288 | return 1; | |
10289 | } | |
10290 | ||
8a2c8fef L |
10291 | #define MESSAGE_TEMPLATE \ |
10292 | " " | |
10293 | ||
293f5f65 L |
10294 | static char * |
10295 | output_message (FILE *stream, char *p, char *message, char *start, | |
10296 | int *left_p, const char *name, int len) | |
10297 | { | |
10298 | int size = sizeof (MESSAGE_TEMPLATE); | |
10299 | int left = *left_p; | |
10300 | ||
10301 | /* Reserve 2 spaces for ", " or ",\0" */ | |
10302 | left -= len + 2; | |
10303 | ||
10304 | /* Check if there is any room. */ | |
10305 | if (left >= 0) | |
10306 | { | |
10307 | if (p != start) | |
10308 | { | |
10309 | *p++ = ','; | |
10310 | *p++ = ' '; | |
10311 | } | |
10312 | p = mempcpy (p, name, len); | |
10313 | } | |
10314 | else | |
10315 | { | |
10316 | /* Output the current message now and start a new one. */ | |
10317 | *p++ = ','; | |
10318 | *p = '\0'; | |
10319 | fprintf (stream, "%s\n", message); | |
10320 | p = start; | |
10321 | left = size - (start - message) - len - 2; | |
10322 | ||
10323 | gas_assert (left >= 0); | |
10324 | ||
10325 | p = mempcpy (p, name, len); | |
10326 | } | |
10327 | ||
10328 | *left_p = left; | |
10329 | return p; | |
10330 | } | |
10331 | ||
8a2c8fef | 10332 | static void |
1ded5609 | 10333 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
10334 | { |
10335 | static char message[] = MESSAGE_TEMPLATE; | |
10336 | char *start = message + 27; | |
10337 | char *p; | |
10338 | int size = sizeof (MESSAGE_TEMPLATE); | |
10339 | int left; | |
10340 | const char *name; | |
10341 | int len; | |
10342 | unsigned int j; | |
10343 | ||
10344 | p = start; | |
10345 | left = size - (start - message); | |
10346 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
10347 | { | |
10348 | /* Should it be skipped? */ | |
10349 | if (cpu_arch [j].skip) | |
10350 | continue; | |
10351 | ||
10352 | name = cpu_arch [j].name; | |
10353 | len = cpu_arch [j].len; | |
10354 | if (*name == '.') | |
10355 | { | |
10356 | /* It is an extension. Skip if we aren't asked to show it. */ | |
10357 | if (ext) | |
10358 | { | |
10359 | name++; | |
10360 | len--; | |
10361 | } | |
10362 | else | |
10363 | continue; | |
10364 | } | |
10365 | else if (ext) | |
10366 | { | |
10367 | /* It is an processor. Skip if we show only extension. */ | |
10368 | continue; | |
10369 | } | |
1ded5609 JB |
10370 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
10371 | { | |
10372 | /* It is an impossible processor - skip. */ | |
10373 | continue; | |
10374 | } | |
8a2c8fef | 10375 | |
293f5f65 | 10376 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
10377 | } |
10378 | ||
293f5f65 L |
10379 | /* Display disabled extensions. */ |
10380 | if (ext) | |
10381 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
10382 | { | |
10383 | name = cpu_noarch [j].name; | |
10384 | len = cpu_noarch [j].len; | |
10385 | p = output_message (stream, p, message, start, &left, name, | |
10386 | len); | |
10387 | } | |
10388 | ||
8a2c8fef L |
10389 | *p = '\0'; |
10390 | fprintf (stream, "%s\n", message); | |
10391 | } | |
10392 | ||
252b5132 | 10393 | void |
8a2c8fef | 10394 | md_show_usage (FILE *stream) |
252b5132 | 10395 | { |
4cc782b5 ILT |
10396 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10397 | fprintf (stream, _("\ | |
a38cf1db AM |
10398 | -Q ignored\n\ |
10399 | -V print assembler version number\n\ | |
b3b91714 AM |
10400 | -k ignored\n")); |
10401 | #endif | |
10402 | fprintf (stream, _("\ | |
12b55ccc | 10403 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
10404 | -q quieten some warnings\n")); |
10405 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10406 | fprintf (stream, _("\ | |
a38cf1db | 10407 | -s ignored\n")); |
b3b91714 | 10408 | #endif |
321098a5 L |
10409 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
10410 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 10411 | fprintf (stream, _("\ |
570561f7 | 10412 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 10413 | #endif |
b3b91714 AM |
10414 | #ifdef SVR4_COMMENT_CHARS |
10415 | fprintf (stream, _("\ | |
10416 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
10417 | #else |
10418 | fprintf (stream, _("\ | |
b3b91714 | 10419 | --divide ignored\n")); |
4cc782b5 | 10420 | #endif |
9103f4f4 | 10421 | fprintf (stream, _("\ |
6305a203 | 10422 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 10423 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 10424 | show_arch (stream, 0, 1); |
8a2c8fef L |
10425 | fprintf (stream, _("\ |
10426 | EXTENSION is combination of:\n")); | |
1ded5609 | 10427 | show_arch (stream, 1, 0); |
6305a203 | 10428 | fprintf (stream, _("\ |
8a2c8fef | 10429 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 10430 | show_arch (stream, 0, 0); |
ba104c83 | 10431 | fprintf (stream, _("\ |
c0f3af97 L |
10432 | -msse2avx encode SSE instructions with VEX prefix\n")); |
10433 | fprintf (stream, _("\ | |
daf50ae7 L |
10434 | -msse-check=[none|error|warning]\n\ |
10435 | check SSE instructions\n")); | |
10436 | fprintf (stream, _("\ | |
7bab8ab5 JB |
10437 | -moperand-check=[none|error|warning]\n\ |
10438 | check operand combinations for validity\n")); | |
10439 | fprintf (stream, _("\ | |
539f890d L |
10440 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
10441 | length\n")); | |
10442 | fprintf (stream, _("\ | |
43234a1e L |
10443 | -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ |
10444 | length\n")); | |
10445 | fprintf (stream, _("\ | |
10446 | -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ | |
10447 | for EVEX.W bit ignored instructions\n")); | |
10448 | fprintf (stream, _("\ | |
d3d3c6db IT |
10449 | -mevexrcig=[rne|rd|ru|rz]\n\ |
10450 | encode EVEX instructions with specific EVEX.RC value\n\ | |
10451 | for SAE-only ignored instructions\n")); | |
10452 | fprintf (stream, _("\ | |
ba104c83 L |
10453 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
10454 | fprintf (stream, _("\ | |
10455 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
10456 | fprintf (stream, _("\ | |
10457 | -mindex-reg support pseudo index registers\n")); | |
10458 | fprintf (stream, _("\ | |
10459 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
10460 | fprintf (stream, _("\ | |
10461 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
7e8b059b L |
10462 | fprintf (stream, _("\ |
10463 | -madd-bnd-prefix add BND prefix for all valid branches\n")); | |
8dcea932 L |
10464 | fprintf (stream, _("\ |
10465 | -mshared disable branch optimization for shared code\n")); | |
167ad85b TG |
10466 | # if defined (TE_PE) || defined (TE_PEP) |
10467 | fprintf (stream, _("\ | |
10468 | -mbig-obj generate big object files\n")); | |
10469 | #endif | |
d022bddd IT |
10470 | fprintf (stream, _("\ |
10471 | -momit-lock-prefix=[no|yes]\n\ | |
10472 | strip all lock prefixes\n")); | |
5db04b09 | 10473 | fprintf (stream, _("\ |
e4e00185 AS |
10474 | -mfence-as-lock-add=[no|yes]\n\ |
10475 | encode lfence, mfence and sfence as\n\ | |
10476 | lock addl $0x0, (%%{re}sp)\n")); | |
10477 | fprintf (stream, _("\ | |
0cb4071e L |
10478 | -mrelax-relocations=[no|yes]\n\ |
10479 | generate relax relocations\n")); | |
10480 | fprintf (stream, _("\ | |
5db04b09 L |
10481 | -mamd64 accept only AMD64 ISA\n")); |
10482 | fprintf (stream, _("\ | |
10483 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
10484 | } |
10485 | ||
3e73aa7c | 10486 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 10487 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 10488 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
10489 | |
10490 | /* Pick the target format to use. */ | |
10491 | ||
47926f60 | 10492 | const char * |
e3bb37b5 | 10493 | i386_target_format (void) |
252b5132 | 10494 | { |
351f65ca L |
10495 | if (!strncmp (default_arch, "x86_64", 6)) |
10496 | { | |
10497 | update_code_flag (CODE_64BIT, 1); | |
10498 | if (default_arch[6] == '\0') | |
7f56bc95 | 10499 | x86_elf_abi = X86_64_ABI; |
351f65ca | 10500 | else |
7f56bc95 | 10501 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 10502 | } |
3e73aa7c | 10503 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 10504 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
10505 | else if (!strcmp (default_arch, "iamcu")) |
10506 | { | |
10507 | update_code_flag (CODE_32BIT, 1); | |
10508 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
10509 | { | |
10510 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
10511 | cpu_arch_name = "iamcu"; | |
10512 | cpu_sub_arch_name = NULL; | |
10513 | cpu_arch_flags = iamcu_flags; | |
10514 | cpu_arch_isa = PROCESSOR_IAMCU; | |
10515 | cpu_arch_isa_flags = iamcu_flags; | |
10516 | if (!cpu_arch_tune_set) | |
10517 | { | |
10518 | cpu_arch_tune = cpu_arch_isa; | |
10519 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10520 | } | |
10521 | } | |
8d471ec1 | 10522 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
10523 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
10524 | cpu_arch_name); | |
10525 | } | |
3e73aa7c | 10526 | else |
2b5d6a91 | 10527 | as_fatal (_("unknown architecture")); |
89507696 JB |
10528 | |
10529 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
10530 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
10531 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
10532 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
10533 | ||
252b5132 RH |
10534 | switch (OUTPUT_FLAVOR) |
10535 | { | |
9384f2ff | 10536 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 10537 | case bfd_target_aout_flavour: |
47926f60 | 10538 | return AOUT_TARGET_FORMAT; |
4c63da97 | 10539 | #endif |
9384f2ff AM |
10540 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
10541 | # if defined (TE_PE) || defined (TE_PEP) | |
10542 | case bfd_target_coff_flavour: | |
167ad85b TG |
10543 | if (flag_code == CODE_64BIT) |
10544 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
10545 | else | |
10546 | return "pe-i386"; | |
9384f2ff | 10547 | # elif defined (TE_GO32) |
0561d57c JK |
10548 | case bfd_target_coff_flavour: |
10549 | return "coff-go32"; | |
9384f2ff | 10550 | # else |
252b5132 RH |
10551 | case bfd_target_coff_flavour: |
10552 | return "coff-i386"; | |
9384f2ff | 10553 | # endif |
4c63da97 | 10554 | #endif |
3e73aa7c | 10555 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 10556 | case bfd_target_elf_flavour: |
3e73aa7c | 10557 | { |
351f65ca L |
10558 | const char *format; |
10559 | ||
10560 | switch (x86_elf_abi) | |
4fa24527 | 10561 | { |
351f65ca L |
10562 | default: |
10563 | format = ELF_TARGET_FORMAT; | |
10564 | break; | |
7f56bc95 | 10565 | case X86_64_ABI: |
351f65ca | 10566 | use_rela_relocations = 1; |
4fa24527 | 10567 | object_64bit = 1; |
351f65ca L |
10568 | format = ELF_TARGET_FORMAT64; |
10569 | break; | |
7f56bc95 | 10570 | case X86_64_X32_ABI: |
4fa24527 | 10571 | use_rela_relocations = 1; |
351f65ca | 10572 | object_64bit = 1; |
862be3fb | 10573 | disallow_64bit_reloc = 1; |
351f65ca L |
10574 | format = ELF_TARGET_FORMAT32; |
10575 | break; | |
4fa24527 | 10576 | } |
3632d14b | 10577 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 10578 | { |
7f56bc95 | 10579 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
10580 | as_fatal (_("Intel L1OM is 64bit only")); |
10581 | return ELF_TARGET_L1OM_FORMAT; | |
10582 | } | |
b49f93f6 | 10583 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
10584 | { |
10585 | if (x86_elf_abi != X86_64_ABI) | |
10586 | as_fatal (_("Intel K1OM is 64bit only")); | |
10587 | return ELF_TARGET_K1OM_FORMAT; | |
10588 | } | |
81486035 L |
10589 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
10590 | { | |
10591 | if (x86_elf_abi != I386_ABI) | |
10592 | as_fatal (_("Intel MCU is 32bit only")); | |
10593 | return ELF_TARGET_IAMCU_FORMAT; | |
10594 | } | |
8a9036a4 | 10595 | else |
351f65ca | 10596 | return format; |
3e73aa7c | 10597 | } |
e57f8c65 TG |
10598 | #endif |
10599 | #if defined (OBJ_MACH_O) | |
10600 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
10601 | if (flag_code == CODE_64BIT) |
10602 | { | |
10603 | use_rela_relocations = 1; | |
10604 | object_64bit = 1; | |
10605 | return "mach-o-x86-64"; | |
10606 | } | |
10607 | else | |
10608 | return "mach-o-i386"; | |
4c63da97 | 10609 | #endif |
252b5132 RH |
10610 | default: |
10611 | abort (); | |
10612 | return NULL; | |
10613 | } | |
10614 | } | |
10615 | ||
47926f60 | 10616 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 10617 | \f |
252b5132 | 10618 | symbolS * |
7016a5d5 | 10619 | md_undefined_symbol (char *name) |
252b5132 | 10620 | { |
18dc2407 ILT |
10621 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
10622 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
10623 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
10624 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
10625 | { |
10626 | if (!GOT_symbol) | |
10627 | { | |
10628 | if (symbol_find (name)) | |
10629 | as_bad (_("GOT already in symbol table")); | |
10630 | GOT_symbol = symbol_new (name, undefined_section, | |
10631 | (valueT) 0, &zero_address_frag); | |
10632 | }; | |
10633 | return GOT_symbol; | |
10634 | } | |
252b5132 RH |
10635 | return 0; |
10636 | } | |
10637 | ||
10638 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 10639 | |
252b5132 | 10640 | valueT |
7016a5d5 | 10641 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 10642 | { |
4c63da97 AM |
10643 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
10644 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
10645 | { | |
10646 | /* For a.out, force the section size to be aligned. If we don't do | |
10647 | this, BFD will align it for us, but it will not write out the | |
10648 | final bytes of the section. This may be a bug in BFD, but it is | |
10649 | easier to fix it here since that is how the other a.out targets | |
10650 | work. */ | |
10651 | int align; | |
10652 | ||
10653 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 10654 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 10655 | } |
252b5132 RH |
10656 | #endif |
10657 | ||
10658 | return size; | |
10659 | } | |
10660 | ||
10661 | /* On the i386, PC-relative offsets are relative to the start of the | |
10662 | next instruction. That is, the address of the offset, plus its | |
10663 | size, since the offset is always the last part of the insn. */ | |
10664 | ||
10665 | long | |
e3bb37b5 | 10666 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
10667 | { |
10668 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
10669 | } | |
10670 | ||
10671 | #ifndef I386COFF | |
10672 | ||
10673 | static void | |
e3bb37b5 | 10674 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 10675 | { |
29b0f896 | 10676 | int temp; |
252b5132 | 10677 | |
8a75718c JB |
10678 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10679 | if (IS_ELF) | |
10680 | obj_elf_section_change_hook (); | |
10681 | #endif | |
252b5132 RH |
10682 | temp = get_absolute_expression (); |
10683 | subseg_set (bss_section, (subsegT) temp); | |
10684 | demand_empty_rest_of_line (); | |
10685 | } | |
10686 | ||
10687 | #endif | |
10688 | ||
252b5132 | 10689 | void |
e3bb37b5 | 10690 | i386_validate_fix (fixS *fixp) |
252b5132 | 10691 | { |
02a86693 | 10692 | if (fixp->fx_subsy) |
252b5132 | 10693 | { |
02a86693 | 10694 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 10695 | { |
02a86693 L |
10696 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
10697 | { | |
10698 | if (!object_64bit) | |
10699 | abort (); | |
10700 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10701 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
10702 | fixp->fx_r_type = (fixp->fx_tcbit |
10703 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
10704 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
10705 | else |
10706 | #endif | |
10707 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
10708 | } | |
d6ab8113 | 10709 | else |
02a86693 L |
10710 | { |
10711 | if (!object_64bit) | |
10712 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
10713 | else | |
10714 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
10715 | } | |
10716 | fixp->fx_subsy = 0; | |
23df1078 | 10717 | } |
252b5132 | 10718 | } |
02a86693 L |
10719 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10720 | else if (!object_64bit) | |
10721 | { | |
10722 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
10723 | && fixp->fx_tcbit2) | |
10724 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
10725 | } | |
10726 | #endif | |
252b5132 RH |
10727 | } |
10728 | ||
252b5132 | 10729 | arelent * |
7016a5d5 | 10730 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
10731 | { |
10732 | arelent *rel; | |
10733 | bfd_reloc_code_real_type code; | |
10734 | ||
10735 | switch (fixp->fx_r_type) | |
10736 | { | |
8ce3d284 | 10737 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
10738 | case BFD_RELOC_SIZE32: |
10739 | case BFD_RELOC_SIZE64: | |
10740 | if (S_IS_DEFINED (fixp->fx_addsy) | |
10741 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
10742 | { | |
10743 | /* Resolve size relocation against local symbol to size of | |
10744 | the symbol plus addend. */ | |
10745 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
10746 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
10747 | && !fits_in_unsigned_long (value)) | |
10748 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10749 | _("symbol size computation overflow")); | |
10750 | fixp->fx_addsy = NULL; | |
10751 | fixp->fx_subsy = NULL; | |
10752 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
10753 | return NULL; | |
10754 | } | |
8ce3d284 | 10755 | #endif |
1a0670f3 | 10756 | /* Fall through. */ |
8fd4256d | 10757 | |
3e73aa7c JH |
10758 | case BFD_RELOC_X86_64_PLT32: |
10759 | case BFD_RELOC_X86_64_GOT32: | |
10760 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
10761 | case BFD_RELOC_X86_64_GOTPCRELX: |
10762 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
10763 | case BFD_RELOC_386_PLT32: |
10764 | case BFD_RELOC_386_GOT32: | |
02a86693 | 10765 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
10766 | case BFD_RELOC_386_GOTOFF: |
10767 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
10768 | case BFD_RELOC_386_TLS_GD: |
10769 | case BFD_RELOC_386_TLS_LDM: | |
10770 | case BFD_RELOC_386_TLS_LDO_32: | |
10771 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
10772 | case BFD_RELOC_386_TLS_IE: |
10773 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
10774 | case BFD_RELOC_386_TLS_LE_32: |
10775 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
10776 | case BFD_RELOC_386_TLS_GOTDESC: |
10777 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
10778 | case BFD_RELOC_X86_64_TLSGD: |
10779 | case BFD_RELOC_X86_64_TLSLD: | |
10780 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10781 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
10782 | case BFD_RELOC_X86_64_GOTTPOFF: |
10783 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
10784 | case BFD_RELOC_X86_64_TPOFF64: |
10785 | case BFD_RELOC_X86_64_GOTOFF64: | |
10786 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
10787 | case BFD_RELOC_X86_64_GOT64: |
10788 | case BFD_RELOC_X86_64_GOTPCREL64: | |
10789 | case BFD_RELOC_X86_64_GOTPC64: | |
10790 | case BFD_RELOC_X86_64_GOTPLT64: | |
10791 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
10792 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
10793 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
10794 | case BFD_RELOC_RVA: |
10795 | case BFD_RELOC_VTABLE_ENTRY: | |
10796 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
10797 | #ifdef TE_PE |
10798 | case BFD_RELOC_32_SECREL: | |
10799 | #endif | |
252b5132 RH |
10800 | code = fixp->fx_r_type; |
10801 | break; | |
dbbaec26 L |
10802 | case BFD_RELOC_X86_64_32S: |
10803 | if (!fixp->fx_pcrel) | |
10804 | { | |
10805 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
10806 | code = fixp->fx_r_type; | |
10807 | break; | |
10808 | } | |
1a0670f3 | 10809 | /* Fall through. */ |
252b5132 | 10810 | default: |
93382f6d | 10811 | if (fixp->fx_pcrel) |
252b5132 | 10812 | { |
93382f6d AM |
10813 | switch (fixp->fx_size) |
10814 | { | |
10815 | default: | |
b091f402 AM |
10816 | as_bad_where (fixp->fx_file, fixp->fx_line, |
10817 | _("can not do %d byte pc-relative relocation"), | |
10818 | fixp->fx_size); | |
93382f6d AM |
10819 | code = BFD_RELOC_32_PCREL; |
10820 | break; | |
10821 | case 1: code = BFD_RELOC_8_PCREL; break; | |
10822 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 10823 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
10824 | #ifdef BFD64 |
10825 | case 8: code = BFD_RELOC_64_PCREL; break; | |
10826 | #endif | |
93382f6d AM |
10827 | } |
10828 | } | |
10829 | else | |
10830 | { | |
10831 | switch (fixp->fx_size) | |
10832 | { | |
10833 | default: | |
b091f402 AM |
10834 | as_bad_where (fixp->fx_file, fixp->fx_line, |
10835 | _("can not do %d byte relocation"), | |
10836 | fixp->fx_size); | |
93382f6d AM |
10837 | code = BFD_RELOC_32; |
10838 | break; | |
10839 | case 1: code = BFD_RELOC_8; break; | |
10840 | case 2: code = BFD_RELOC_16; break; | |
10841 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 10842 | #ifdef BFD64 |
3e73aa7c | 10843 | case 8: code = BFD_RELOC_64; break; |
937149dd | 10844 | #endif |
93382f6d | 10845 | } |
252b5132 RH |
10846 | } |
10847 | break; | |
10848 | } | |
252b5132 | 10849 | |
d182319b JB |
10850 | if ((code == BFD_RELOC_32 |
10851 | || code == BFD_RELOC_32_PCREL | |
10852 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
10853 | && GOT_symbol |
10854 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 10855 | { |
4fa24527 | 10856 | if (!object_64bit) |
d6ab8113 JB |
10857 | code = BFD_RELOC_386_GOTPC; |
10858 | else | |
10859 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 10860 | } |
7b81dfbb AJ |
10861 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
10862 | && GOT_symbol | |
10863 | && fixp->fx_addsy == GOT_symbol) | |
10864 | { | |
10865 | code = BFD_RELOC_X86_64_GOTPC64; | |
10866 | } | |
252b5132 | 10867 | |
add39d23 TS |
10868 | rel = XNEW (arelent); |
10869 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 10870 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
10871 | |
10872 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 10873 | |
3e73aa7c JH |
10874 | if (!use_rela_relocations) |
10875 | { | |
10876 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
10877 | vtable entry to be used in the relocation's section offset. */ | |
10878 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10879 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
10880 | #if defined (OBJ_COFF) && defined (TE_PE) |
10881 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
10882 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
10883 | else | |
10884 | #endif | |
c6682705 | 10885 | rel->addend = 0; |
3e73aa7c JH |
10886 | } |
10887 | /* Use the rela in 64bit mode. */ | |
252b5132 | 10888 | else |
3e73aa7c | 10889 | { |
862be3fb L |
10890 | if (disallow_64bit_reloc) |
10891 | switch (code) | |
10892 | { | |
862be3fb L |
10893 | case BFD_RELOC_X86_64_DTPOFF64: |
10894 | case BFD_RELOC_X86_64_TPOFF64: | |
10895 | case BFD_RELOC_64_PCREL: | |
10896 | case BFD_RELOC_X86_64_GOTOFF64: | |
10897 | case BFD_RELOC_X86_64_GOT64: | |
10898 | case BFD_RELOC_X86_64_GOTPCREL64: | |
10899 | case BFD_RELOC_X86_64_GOTPC64: | |
10900 | case BFD_RELOC_X86_64_GOTPLT64: | |
10901 | case BFD_RELOC_X86_64_PLTOFF64: | |
10902 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10903 | _("cannot represent relocation type %s in x32 mode"), | |
10904 | bfd_get_reloc_code_name (code)); | |
10905 | break; | |
10906 | default: | |
10907 | break; | |
10908 | } | |
10909 | ||
062cd5e7 AS |
10910 | if (!fixp->fx_pcrel) |
10911 | rel->addend = fixp->fx_offset; | |
10912 | else | |
10913 | switch (code) | |
10914 | { | |
10915 | case BFD_RELOC_X86_64_PLT32: | |
10916 | case BFD_RELOC_X86_64_GOT32: | |
10917 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
10918 | case BFD_RELOC_X86_64_GOTPCRELX: |
10919 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
10920 | case BFD_RELOC_X86_64_TLSGD: |
10921 | case BFD_RELOC_X86_64_TLSLD: | |
10922 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
10923 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
10924 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
10925 | rel->addend = fixp->fx_offset - fixp->fx_size; |
10926 | break; | |
10927 | default: | |
10928 | rel->addend = (section->vma | |
10929 | - fixp->fx_size | |
10930 | + fixp->fx_addnumber | |
10931 | + md_pcrel_from (fixp)); | |
10932 | break; | |
10933 | } | |
3e73aa7c JH |
10934 | } |
10935 | ||
252b5132 RH |
10936 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
10937 | if (rel->howto == NULL) | |
10938 | { | |
10939 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 10940 | _("cannot represent relocation type %s"), |
252b5132 RH |
10941 | bfd_get_reloc_code_name (code)); |
10942 | /* Set howto to a garbage value so that we can keep going. */ | |
10943 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 10944 | gas_assert (rel->howto != NULL); |
252b5132 RH |
10945 | } |
10946 | ||
10947 | return rel; | |
10948 | } | |
10949 | ||
ee86248c | 10950 | #include "tc-i386-intel.c" |
54cfded0 | 10951 | |
a60de03c JB |
10952 | void |
10953 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 10954 | { |
a60de03c JB |
10955 | int saved_naked_reg; |
10956 | char saved_register_dot; | |
54cfded0 | 10957 | |
a60de03c JB |
10958 | saved_naked_reg = allow_naked_reg; |
10959 | allow_naked_reg = 1; | |
10960 | saved_register_dot = register_chars['.']; | |
10961 | register_chars['.'] = '.'; | |
10962 | allow_pseudo_reg = 1; | |
10963 | expression_and_evaluate (exp); | |
10964 | allow_pseudo_reg = 0; | |
10965 | register_chars['.'] = saved_register_dot; | |
10966 | allow_naked_reg = saved_naked_reg; | |
10967 | ||
e96d56a1 | 10968 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 10969 | { |
a60de03c JB |
10970 | if ((addressT) exp->X_add_number < i386_regtab_size) |
10971 | { | |
10972 | exp->X_op = O_constant; | |
10973 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
10974 | .dw2_regnum[flag_code >> 1]; | |
10975 | } | |
10976 | else | |
10977 | exp->X_op = O_illegal; | |
54cfded0 | 10978 | } |
54cfded0 AM |
10979 | } |
10980 | ||
10981 | void | |
10982 | tc_x86_frame_initial_instructions (void) | |
10983 | { | |
a60de03c JB |
10984 | static unsigned int sp_regno[2]; |
10985 | ||
10986 | if (!sp_regno[flag_code >> 1]) | |
10987 | { | |
10988 | char *saved_input = input_line_pointer; | |
10989 | char sp[][4] = {"esp", "rsp"}; | |
10990 | expressionS exp; | |
a4447b93 | 10991 | |
a60de03c JB |
10992 | input_line_pointer = sp[flag_code >> 1]; |
10993 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 10994 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
10995 | sp_regno[flag_code >> 1] = exp.X_add_number; |
10996 | input_line_pointer = saved_input; | |
10997 | } | |
a4447b93 | 10998 | |
61ff971f L |
10999 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
11000 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 11001 | } |
d2b2c203 | 11002 | |
d7921315 L |
11003 | int |
11004 | x86_dwarf2_addr_size (void) | |
11005 | { | |
11006 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
11007 | if (x86_elf_abi == X86_64_X32_ABI) | |
11008 | return 4; | |
11009 | #endif | |
11010 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
11011 | } | |
11012 | ||
d2b2c203 DJ |
11013 | int |
11014 | i386_elf_section_type (const char *str, size_t len) | |
11015 | { | |
11016 | if (flag_code == CODE_64BIT | |
11017 | && len == sizeof ("unwind") - 1 | |
11018 | && strncmp (str, "unwind", 6) == 0) | |
11019 | return SHT_X86_64_UNWIND; | |
11020 | ||
11021 | return -1; | |
11022 | } | |
bb41ade5 | 11023 | |
ad5fec3b EB |
11024 | #ifdef TE_SOLARIS |
11025 | void | |
11026 | i386_solaris_fix_up_eh_frame (segT sec) | |
11027 | { | |
11028 | if (flag_code == CODE_64BIT) | |
11029 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
11030 | } | |
11031 | #endif | |
11032 | ||
bb41ade5 AM |
11033 | #ifdef TE_PE |
11034 | void | |
11035 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
11036 | { | |
91d6fa6a | 11037 | expressionS exp; |
bb41ade5 | 11038 | |
91d6fa6a NC |
11039 | exp.X_op = O_secrel; |
11040 | exp.X_add_symbol = symbol; | |
11041 | exp.X_add_number = 0; | |
11042 | emit_expr (&exp, size); | |
bb41ade5 AM |
11043 | } |
11044 | #endif | |
3b22753a L |
11045 | |
11046 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11047 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
11048 | ||
01e1a5bc | 11049 | bfd_vma |
6d4af3c2 | 11050 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
11051 | { |
11052 | if (flag_code == CODE_64BIT) | |
11053 | { | |
11054 | if (letter == 'l') | |
11055 | return SHF_X86_64_LARGE; | |
11056 | ||
8f3bae45 | 11057 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 11058 | } |
3b22753a | 11059 | else |
8f3bae45 | 11060 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
11061 | return -1; |
11062 | } | |
11063 | ||
01e1a5bc | 11064 | bfd_vma |
3b22753a L |
11065 | x86_64_section_word (char *str, size_t len) |
11066 | { | |
8620418b | 11067 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
11068 | return SHF_X86_64_LARGE; |
11069 | ||
11070 | return -1; | |
11071 | } | |
11072 | ||
11073 | static void | |
11074 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
11075 | { | |
11076 | if (flag_code != CODE_64BIT) | |
11077 | { | |
11078 | s_comm_internal (0, elf_common_parse); | |
11079 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
11080 | } | |
11081 | else | |
11082 | { | |
11083 | static segT lbss_section; | |
11084 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
11085 | asection *saved_bss_section = bss_section; | |
11086 | ||
11087 | if (lbss_section == NULL) | |
11088 | { | |
11089 | flagword applicable; | |
11090 | segT seg = now_seg; | |
11091 | subsegT subseg = now_subseg; | |
11092 | ||
11093 | /* The .lbss section is for local .largecomm symbols. */ | |
11094 | lbss_section = subseg_new (".lbss", 0); | |
11095 | applicable = bfd_applicable_section_flags (stdoutput); | |
11096 | bfd_set_section_flags (stdoutput, lbss_section, | |
11097 | applicable & SEC_ALLOC); | |
11098 | seg_info (lbss_section)->bss = 1; | |
11099 | ||
11100 | subseg_set (seg, subseg); | |
11101 | } | |
11102 | ||
11103 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
11104 | bss_section = lbss_section; | |
11105 | ||
11106 | s_comm_internal (0, elf_common_parse); | |
11107 | ||
11108 | elf_com_section_ptr = saved_com_section_ptr; | |
11109 | bss_section = saved_bss_section; | |
11110 | } | |
11111 | } | |
11112 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |