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Add script to build and test GDB using enable-targets=all.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
99 const template *start;
100 const template *end;
101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
116/* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119#define DREX_OC0(x) (((x) & 1) != 0)
120#define DREX_OC1(x) (((x) & 2) != 0)
121
122#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
124
125/* OC mappings */
126#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
130
131#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
133
134/* Information needed to create the DREX byte in SSE5 instructions. */
135typedef struct
136{
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
141} drex_byte;
142
143/* 386 opcode byte to code indirect addressing. */
144typedef struct
145{
146 unsigned base;
147 unsigned index;
148 unsigned scale;
149}
150sib_byte;
151
152enum processor_type
153{
154 PROCESSOR_UNKNOWN,
155 PROCESSOR_I386,
156 PROCESSOR_I486,
157 PROCESSOR_PENTIUM,
158 PROCESSOR_PENTIUMPRO,
159 PROCESSOR_PENTIUM4,
160 PROCESSOR_NOCONA,
161 PROCESSOR_CORE,
162 PROCESSOR_CORE2,
163 PROCESSOR_K6,
164 PROCESSOR_ATHLON,
165 PROCESSOR_K8,
166 PROCESSOR_GENERIC32,
167 PROCESSOR_GENERIC64,
168 PROCESSOR_AMDFAM10
169};
170
171/* x86 arch names, types and features */
172typedef struct
173{
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
177}
178arch_entry;
179
e3bb37b5
L		 180static void set_code_flag (int);
181static void set_16bit_gcc_code_flag (int);
182static void set_intel_syntax (int);
1efbbeb4 183static void set_intel_mnemonic (int);
db51cc60 184static void set_allow_index_reg (int);
e3bb37b5 185static void set_cpu_arch (int);
6482c264 186#ifdef TE_PE
e3bb37b5 187static void pe_directive_secrel (int);
6482c264 188#endif
e3bb37b5
L		 189static void signed_cons (int);
190static char *output_invalid (int c);
a7619375 191static int i386_att_operand (char *);
e3bb37b5
L		 192static int i386_intel_operand (char *, int);
193static const reg_entry *parse_register (char *, char **);
194static char *parse_insn (char *, char *);
195static char *parse_operands (char *, const char *);
196static void swap_operands (void);
4d456e3d 197static void swap_2_operands (int, int);
e3bb37b5
L		 198static void optimize_imm (void);
199static void optimize_disp (void);
200static int match_template (void);
201static int check_string (void);
202static int process_suffix (void);
203static int check_byte_reg (void);
204static int check_long_reg (void);
205static int check_qword_reg (void);
206static int check_word_reg (void);
207static int finalize_imm (void);
85f10a01 208static void process_drex (void);
e3bb37b5
L		 209static int process_operands (void);
210static const seg_entry *build_modrm_byte (void);
211static void output_insn (void);
212static void output_imm (fragS *, offsetT);
213static void output_disp (fragS *, offsetT);
29b0f896 214#ifndef I386COFF
e3bb37b5 215static void s_bss (int);
252b5132 216#endif
17d4e2a2
L		 217#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218static void handle_large_common (int small ATTRIBUTE_UNUSED);
219#endif
252b5132 220
a847613f 221static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 222
252b5132 223/* 'md_assemble ()' gathers together information and puts it into a
47926f60 224 i386_insn. */
252b5132 225
520dc8e8
AM		 226union i386_op
227 {
228 expressionS *disps;
229 expressionS *imms;
230 const reg_entry *regs;
231 };
232
252b5132
RH		 233struct _i386_insn
234 {
47926f60 235 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 236 template tm;
237
7d5e4556
L		 238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
252b5132
RH		 240 char suffix;
241
47926f60 242 /* OPERANDS gives the number of given operands. */
252b5132
RH		 243 unsigned int operands;
244
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
47926f60 247 operands. */
252b5132
RH		 248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
249
250 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 251 use OP[i] for the corresponding operand. */
40fb9820 252 i386_operand_type types[MAX_OPERANDS];
252b5132 253
520dc8e8
AM		 254 /* Displacement expression, immediate expression, or register for each
255 operand. */
256 union i386_op op[MAX_OPERANDS];
252b5132 257
3e73aa7c
JH		 258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260#define Operand_PCrel 1
261
252b5132 262 /* Relocation type for operand */
f86103b7 263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 264
252b5132
RH		 265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
270
271 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 272 explicit segment overrides are given. */
ce8a8b2f 273 const seg_entry *seg[2];
252b5132
RH		 274
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
279
280 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
252b5132
RH		 283
284 modrm_byte rm;
3e73aa7c 285 rex_byte rex;
252b5132 286 sib_byte sib;
85f10a01 287 drex_byte drex;
252b5132
RH		 288 };
289
290typedef struct _i386_insn i386_insn;
291
292/* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
32137342 294const char extra_symbol_chars[] = "*%-(["
252b5132 295#ifdef LEX_AT
32137342
NC		 296 "@"
297#endif
298#ifdef LEX_QM
299 "?"
252b5132 300#endif
32137342 301 ;
252b5132 302
29b0f896
AM		 303#if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 305 && !defined (TE_GNU) \
29b0f896 306 && !defined (TE_LINUX) \
32137342 307 && !defined (TE_NETWARE) \
29b0f896
AM		 308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
252b5132 310/* This array holds the chars that always start a comment. If the
b3b91714
AM		 311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313const char *i386_comment_chars = "#/";
314#define SVR4_COMMENT_CHARS 1
252b5132 315#define PREFIX_SEPARATOR '\\'
252b5132 316
b3b91714
AM		 317#else
318const char *i386_comment_chars = "#";
319#define PREFIX_SEPARATOR '/'
320#endif
321
252b5132
RH		 322/* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 326 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
252b5132 329 '/' isn't otherwise defined. */
b3b91714 330const char line_comment_chars[] = "#/";
252b5132 331
63a0b638 332const char line_separator_chars[] = ";";
252b5132 333
ce8a8b2f
AM		 334/* Chars that can be used to separate mant from exp in floating point
335 nums. */
252b5132
RH		 336const char EXP_CHARS[] = "eE";
337
ce8a8b2f
AM		 338/* Chars that mean this number is a floating point constant
339 As in 0f12.456
340 or 0d1.2345e12. */
252b5132
RH		 341const char FLT_CHARS[] = "fFdDxX";
342
ce8a8b2f 343/* Tables for lexical analysis. */
252b5132
RH		 344static char mnemonic_chars[256];
345static char register_chars[256];
346static char operand_chars[256];
347static char identifier_chars[256];
348static char digit_chars[256];
349
ce8a8b2f 350/* Lexical macros. */
252b5132
RH		 351#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352#define is_operand_char(x) (operand_chars[(unsigned char) x])
353#define is_register_char(x) (register_chars[(unsigned char) x])
354#define is_space_char(x) ((x) == ' ')
355#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356#define is_digit_char(x) (digit_chars[(unsigned char) x])
357
0234cb7c 358/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 359static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
360
361/* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
47926f60 364 assembler instruction). */
252b5132 365static char save_stack[32];
ce8a8b2f 366static char *save_stack_p;
252b5132
RH		 367#define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369#define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
371
47926f60 372/* The instruction we're assembling. */
252b5132
RH		 373static i386_insn i;
374
375/* Possible templates for current insn. */
376static const templates *current_templates;
377
31b2323c
L		 378/* Per instruction expressionS buffers: max displacements & immediates. */
379static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 381
47926f60
KH		 382/* Current operand we are working on. */
383static int this_operand;
252b5132 384
3e73aa7c
JH		 385/* We support four different modes. FLAG_CODE variable is used to distinguish
386 these. */
387
388enum flag_code {
389 CODE_32BIT,
390 CODE_16BIT,
391 CODE_64BIT };
392
393static enum flag_code flag_code;
4fa24527 394static unsigned int object_64bit;
3e73aa7c
JH		 395static int use_rela_relocations = 0;
396
397/* The names used to print error messages. */
b77a7acd 398static const char *flag_code_names[] =
3e73aa7c
JH		 399 {
400 "32",
401 "16",
402 "64"
403 };
252b5132 404
47926f60
KH		 405/* 1 for intel syntax,
406 0 if att syntax. */
407static int intel_syntax = 0;
252b5132 408
1efbbeb4
L		 409/* 1 for intel mnemonic,
410 0 if att mnemonic. */
411static int intel_mnemonic = !SYSV386_COMPAT;
412
5209009a 413/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 414static int old_gcc = OLDGCC_COMPAT;
415
47926f60
KH		 416/* 1 if register prefix % not required. */
417static int allow_naked_reg = 0;
252b5132 418
ba104c83 419/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 420static int allow_index_reg = 0;
421
2ca3ace5
L		 422/* Register prefix used for error message. */
423static const char *register_prefix = "%";
424
47926f60
KH		 425/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
426 leave, push, and pop instructions so that gcc has the same stack
427 frame as in 32 bit mode. */
428static char stackop_size = '\0';
eecb386c 429
12b55ccc
L		 430/* Non-zero to optimize code alignment. */
431int optimize_align_code = 1;
432
47926f60
KH		 433/* Non-zero to quieten some warnings. */
434static int quiet_warnings = 0;
a38cf1db 435
47926f60
KH		 436/* CPU name. */
437static const char *cpu_arch_name = NULL;
6305a203 438static char *cpu_sub_arch_name = NULL;
a38cf1db 439
47926f60 440/* CPU feature flags. */
40fb9820
L		 441static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
442
ccc9c027
L		 443/* If we have selected a cpu we are generating instructions for. */
444static int cpu_arch_tune_set = 0;
445
9103f4f4
L		 446/* Cpu we are generating instructions for. */
447static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
448
449/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 450static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 451
ccc9c027
L		 452/* CPU instruction set architecture used. */
453static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
454
9103f4f4 455/* CPU feature flags of instruction set architecture used. */
40fb9820 456static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 457
fddf5b5b
AM		 458/* If set, conditional jumps are not automatically promoted to handle
459 larger than a byte offset. */
460static unsigned int no_cond_jump_promotion = 0;
461
29b0f896 462/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 463static symbolS *GOT_symbol;
29b0f896 464
a4447b93
RH		 465/* The dwarf2 return column, adjusted for 32 or 64 bit. */
466unsigned int x86_dwarf2_return_column;
467
468/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
469int x86_cie_data_alignment;
470
252b5132 471/* Interface to relax_segment.
fddf5b5b
AM		 472 There are 3 major relax states for 386 jump insns because the
473 different types of jumps add different sizes to frags when we're
474 figuring out what sort of jump to choose to reach a given label. */
252b5132 475
47926f60 476/* Types. */
93c2a809
AM		 477#define UNCOND_JUMP 0
478#define COND_JUMP 1
479#define COND_JUMP86 2
fddf5b5b 480
47926f60 481/* Sizes. */
252b5132
RH		 482#define CODE16 1
483#define SMALL 0
29b0f896 484#define SMALL16 (SMALL | CODE16)
252b5132 485#define BIG 2
29b0f896 486#define BIG16 (BIG | CODE16)
252b5132
RH		 487
488#ifndef INLINE
489#ifdef __GNUC__
490#define INLINE __inline__
491#else
492#define INLINE
493#endif
494#endif
495
fddf5b5b
AM		 496#define ENCODE_RELAX_STATE(type, size) \
497 ((relax_substateT) (((type) << 2) | (size)))
498#define TYPE_FROM_RELAX_STATE(s) \
499 ((s) >> 2)
500#define DISP_SIZE_FROM_RELAX_STATE(s) \
501 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 502
503/* This table is used by relax_frag to promote short jumps to long
504 ones where necessary. SMALL (short) jumps may be promoted to BIG
505 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
506 don't allow a short jump in a 32 bit code segment to be promoted to
507 a 16 bit offset jump because it's slower (requires data size
508 prefix), and doesn't work, unless the destination is in the bottom
509 64k of the code segment (The top 16 bits of eip are zeroed). */
510
511const relax_typeS md_relax_table[] =
512{
24eab124
AM		 513 /* The fields are:
514 1) most positive reach of this state,
515 2) most negative reach of this state,
93c2a809 516 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 517 4) which index into the table to try if we can't fit into this one. */
252b5132 518
fddf5b5b 519 /* UNCOND_JUMP states. */
93c2a809
AM		 520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
521 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
522 /* dword jmp adds 4 bytes to frag:
523 0 extra opcode bytes, 4 displacement bytes. */
252b5132 524 {0, 0, 4, 0},
93c2a809
AM		 525 /* word jmp adds 2 byte2 to frag:
526 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 527 {0, 0, 2, 0},
528
93c2a809
AM		 529 /* COND_JUMP states. */
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
532 /* dword conditionals adds 5 bytes to frag:
533 1 extra opcode byte, 4 displacement bytes. */
534 {0, 0, 5, 0},
fddf5b5b 535 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 536 1 extra opcode byte, 2 displacement bytes. */
537 {0, 0, 3, 0},
538
539 /* COND_JUMP86 states. */
540 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
542 /* dword conditionals adds 5 bytes to frag:
543 1 extra opcode byte, 4 displacement bytes. */
544 {0, 0, 5, 0},
545 /* word conditionals add 4 bytes to frag:
546 1 displacement byte and a 3 byte long branch insn. */
547 {0, 0, 4, 0}
252b5132
RH		 548};
549
9103f4f4
L		 550static const arch_entry cpu_arch[] =
551{
6305a203
L		 552 { "generic32", PROCESSOR_GENERIC32,
553 CPU_GENERIC32_FLAGS },
554 { "generic64", PROCESSOR_GENERIC64,
555 CPU_GENERIC64_FLAGS },
556 { "i8086", PROCESSOR_UNKNOWN,
557 CPU_NONE_FLAGS },
558 { "i186", PROCESSOR_UNKNOWN,
559 CPU_I186_FLAGS },
560 { "i286", PROCESSOR_UNKNOWN,
561 CPU_I286_FLAGS },
562 { "i386", PROCESSOR_I386,
563 CPU_I386_FLAGS },
564 { "i486", PROCESSOR_I486,
565 CPU_I486_FLAGS },
566 { "i586", PROCESSOR_PENTIUM,
567 CPU_I586_FLAGS },
568 { "i686", PROCESSOR_PENTIUMPRO,
569 CPU_I686_FLAGS },
570 { "pentium", PROCESSOR_PENTIUM,
571 CPU_I586_FLAGS },
572 { "pentiumpro", PROCESSOR_PENTIUMPRO,
573 CPU_I686_FLAGS },
574 { "pentiumii", PROCESSOR_PENTIUMPRO,
575 CPU_P2_FLAGS },
576 { "pentiumiii",PROCESSOR_PENTIUMPRO,
577 CPU_P3_FLAGS },
578 { "pentium4", PROCESSOR_PENTIUM4,
579 CPU_P4_FLAGS },
580 { "prescott", PROCESSOR_NOCONA,
581 CPU_CORE_FLAGS },
582 { "nocona", PROCESSOR_NOCONA,
583 CPU_NOCONA_FLAGS },
584 { "yonah", PROCESSOR_CORE,
585 CPU_CORE_FLAGS },
586 { "core", PROCESSOR_CORE,
587 CPU_CORE_FLAGS },
588 { "merom", PROCESSOR_CORE2,
589 CPU_CORE2_FLAGS },
590 { "core2", PROCESSOR_CORE2,
591 CPU_CORE2_FLAGS },
592 { "k6", PROCESSOR_K6,
593 CPU_K6_FLAGS },
594 { "k6_2", PROCESSOR_K6,
595 CPU_K6_2_FLAGS },
596 { "athlon", PROCESSOR_ATHLON,
597 CPU_ATHLON_FLAGS },
598 { "sledgehammer", PROCESSOR_K8,
599 CPU_K8_FLAGS },
600 { "opteron", PROCESSOR_K8,
601 CPU_K8_FLAGS },
602 { "k8", PROCESSOR_K8,
603 CPU_K8_FLAGS },
604 { "amdfam10", PROCESSOR_AMDFAM10,
605 CPU_AMDFAM10_FLAGS },
606 { ".mmx", PROCESSOR_UNKNOWN,
607 CPU_MMX_FLAGS },
608 { ".sse", PROCESSOR_UNKNOWN,
609 CPU_SSE_FLAGS },
610 { ".sse2", PROCESSOR_UNKNOWN,
611 CPU_SSE2_FLAGS },
612 { ".sse3", PROCESSOR_UNKNOWN,
613 CPU_SSE3_FLAGS },
614 { ".ssse3", PROCESSOR_UNKNOWN,
615 CPU_SSSE3_FLAGS },
616 { ".sse4.1", PROCESSOR_UNKNOWN,
617 CPU_SSE4_1_FLAGS },
618 { ".sse4.2", PROCESSOR_UNKNOWN,
619 CPU_SSE4_2_FLAGS },
620 { ".sse4", PROCESSOR_UNKNOWN,
621 CPU_SSE4_2_FLAGS },
622 { ".vmx", PROCESSOR_UNKNOWN,
623 CPU_VMX_FLAGS },
624 { ".smx", PROCESSOR_UNKNOWN,
625 CPU_SMX_FLAGS },
f03fe4c1
L		 626 { ".xsave", PROCESSOR_UNKNOWN,
627 CPU_XSAVE_FLAGS },
6305a203
L		 628 { ".3dnow", PROCESSOR_UNKNOWN,
629 CPU_3DNOW_FLAGS },
630 { ".3dnowa", PROCESSOR_UNKNOWN,
631 CPU_3DNOWA_FLAGS },
632 { ".padlock", PROCESSOR_UNKNOWN,
633 CPU_PADLOCK_FLAGS },
634 { ".pacifica", PROCESSOR_UNKNOWN,
635 CPU_SVME_FLAGS },
636 { ".svme", PROCESSOR_UNKNOWN,
637 CPU_SVME_FLAGS },
638 { ".sse4a", PROCESSOR_UNKNOWN,
639 CPU_SSE4A_FLAGS },
640 { ".abm", PROCESSOR_UNKNOWN,
641 CPU_ABM_FLAGS },
642 { ".sse5", PROCESSOR_UNKNOWN,
643 CPU_SSE5_FLAGS },
e413e4e9
AM		 644};
645
29b0f896
AM		 646const pseudo_typeS md_pseudo_table[] =
647{
648#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
649 {"align", s_align_bytes, 0},
650#else
651 {"align", s_align_ptwo, 0},
652#endif
653 {"arch", set_cpu_arch, 0},
654#ifndef I386COFF
655 {"bss", s_bss, 0},
656#endif
657 {"ffloat", float_cons, 'f'},
658 {"dfloat", float_cons, 'd'},
659 {"tfloat", float_cons, 'x'},
660 {"value", cons, 2},
d182319b 661 {"slong", signed_cons, 4},
29b0f896
AM		 662 {"noopt", s_ignore, 0},
663 {"optim", s_ignore, 0},
664 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
665 {"code16", set_code_flag, CODE_16BIT},
666 {"code32", set_code_flag, CODE_32BIT},
667 {"code64", set_code_flag, CODE_64BIT},
668 {"intel_syntax", set_intel_syntax, 1},
669 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 670 {"intel_mnemonic", set_intel_mnemonic, 1},
671 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 672 {"allow_index_reg", set_allow_index_reg, 1},
673 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 674#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
675 {"largecomm", handle_large_common, 0},
07a53e5c 676#else
e3bb37b5 677 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 678 {"loc", dwarf2_directive_loc, 0},
679 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 680#endif
6482c264
NC		 681#ifdef TE_PE
682 {"secrel32", pe_directive_secrel, 0},
683#endif
29b0f896
AM		 684 {0, 0, 0}
685};
686
687/* For interface with expression (). */
688extern char *input_line_pointer;
689
690/* Hash table for instruction mnemonic lookup. */
691static struct hash_control *op_hash;
692
693/* Hash table for register lookup. */
694static struct hash_control *reg_hash;
695\f
252b5132 696void
e3bb37b5 697i386_align_code (fragS *fragP, int count)
252b5132 698{
ce8a8b2f
AM		 699 /* Various efficient no-op patterns for aligning code labels.
700 Note: Don't try to assemble the instructions in the comments.
701 0L and 0w are not legal. */
252b5132
RH		 702 static const char f32_1[] =
703 {0x90}; /* nop */
704 static const char f32_2[] =
ccc9c027 705 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 706 static const char f32_3[] =
707 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
708 static const char f32_4[] =
709 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
710 static const char f32_5[] =
711 {0x90, /* nop */
712 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
713 static const char f32_6[] =
714 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
715 static const char f32_7[] =
716 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
717 static const char f32_8[] =
718 {0x90, /* nop */
719 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
720 static const char f32_9[] =
721 {0x89,0xf6, /* movl %esi,%esi */
722 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
723 static const char f32_10[] =
724 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
725 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
726 static const char f32_11[] =
727 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
728 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
729 static const char f32_12[] =
730 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
731 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
732 static const char f32_13[] =
733 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
734 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
735 static const char f32_14[] =
736 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
737 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 738 static const char f16_3[] =
739 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 740 static const char f16_4[] =
741 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
742 static const char f16_5[] =
743 {0x90, /* nop */
744 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
745 static const char f16_6[] =
746 {0x89,0xf6, /* mov %si,%si */
747 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
748 static const char f16_7[] =
749 {0x8d,0x74,0x00, /* lea 0(%si),%si */
750 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
751 static const char f16_8[] =
752 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
753 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 754 static const char jump_31[] =
755 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
756 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
757 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
758 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 759 static const char *const f32_patt[] = {
760 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 761 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 762 };
763 static const char *const f16_patt[] = {
76bc74dc 764 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 765 };
ccc9c027
L		 766 /* nopl (%[re]ax) */
767 static const char alt_3[] =
768 {0x0f,0x1f,0x00};
769 /* nopl 0(%[re]ax) */
770 static const char alt_4[] =
771 {0x0f,0x1f,0x40,0x00};
772 /* nopl 0(%[re]ax,%[re]ax,1) */
773 static const char alt_5[] =
774 {0x0f,0x1f,0x44,0x00,0x00};
775 /* nopw 0(%[re]ax,%[re]ax,1) */
776 static const char alt_6[] =
777 {0x66,0x0f,0x1f,0x44,0x00,0x00};
778 /* nopl 0L(%[re]ax) */
779 static const char alt_7[] =
780 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
781 /* nopl 0L(%[re]ax,%[re]ax,1) */
782 static const char alt_8[] =
783 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
784 /* nopw 0L(%[re]ax,%[re]ax,1) */
785 static const char alt_9[] =
786 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
787 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
788 static const char alt_10[] =
789 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
790 /* data16
791 nopw %cs:0L(%[re]ax,%[re]ax,1) */
792 static const char alt_long_11[] =
793 {0x66,
794 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
795 /* data16
796 data16
797 nopw %cs:0L(%[re]ax,%[re]ax,1) */
798 static const char alt_long_12[] =
799 {0x66,
800 0x66,
801 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
802 /* data16
803 data16
804 data16
805 nopw %cs:0L(%[re]ax,%[re]ax,1) */
806 static const char alt_long_13[] =
807 {0x66,
808 0x66,
809 0x66,
810 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
811 /* data16
812 data16
813 data16
814 data16
815 nopw %cs:0L(%[re]ax,%[re]ax,1) */
816 static const char alt_long_14[] =
817 {0x66,
818 0x66,
819 0x66,
820 0x66,
821 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
822 /* data16
823 data16
824 data16
825 data16
826 data16
827 nopw %cs:0L(%[re]ax,%[re]ax,1) */
828 static const char alt_long_15[] =
829 {0x66,
830 0x66,
831 0x66,
832 0x66,
833 0x66,
834 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
835 /* nopl 0(%[re]ax,%[re]ax,1)
836 nopw 0(%[re]ax,%[re]ax,1) */
837 static const char alt_short_11[] =
838 {0x0f,0x1f,0x44,0x00,0x00,
839 0x66,0x0f,0x1f,0x44,0x00,0x00};
840 /* nopw 0(%[re]ax,%[re]ax,1)
841 nopw 0(%[re]ax,%[re]ax,1) */
842 static const char alt_short_12[] =
843 {0x66,0x0f,0x1f,0x44,0x00,0x00,
844 0x66,0x0f,0x1f,0x44,0x00,0x00};
845 /* nopw 0(%[re]ax,%[re]ax,1)
846 nopl 0L(%[re]ax) */
847 static const char alt_short_13[] =
848 {0x66,0x0f,0x1f,0x44,0x00,0x00,
849 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
850 /* nopl 0L(%[re]ax)
851 nopl 0L(%[re]ax) */
852 static const char alt_short_14[] =
853 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
854 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
855 /* nopl 0L(%[re]ax)
856 nopl 0L(%[re]ax,%[re]ax,1) */
857 static const char alt_short_15[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
859 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 static const char *const alt_short_patt[] = {
861 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
862 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
863 alt_short_14, alt_short_15
864 };
865 static const char *const alt_long_patt[] = {
866 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
867 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
868 alt_long_14, alt_long_15
869 };
252b5132 870
76bc74dc
L		 871 /* Only align for at least a positive non-zero boundary. */
872 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 873 return;
3e73aa7c 874
ccc9c027
L		 875 /* We need to decide which NOP sequence to use for 32bit and
876 64bit. When -mtune= is used:
4eed87de 877
76bc74dc
L		 878 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
879 PROCESSOR_GENERIC32, f32_patt will be used.
880 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
881 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
882 alt_long_patt will be used.
883 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
884 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 885
76bc74dc
L		 886 When -mtune= isn't used, alt_long_patt will be used if
887 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
888 be used.
ccc9c027
L		 889
890 When -march= or .arch is used, we can't use anything beyond
891 cpu_arch_isa_flags. */
892
893 if (flag_code == CODE_16BIT)
894 {
ccc9c027 895 if (count > 8)
33fef721 896 {
76bc74dc
L		 897 memcpy (fragP->fr_literal + fragP->fr_fix,
898 jump_31, count);
899 /* Adjust jump offset. */
900 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 901 }
76bc74dc
L		 902 else
903 memcpy (fragP->fr_literal + fragP->fr_fix,
904 f16_patt[count - 1], count);
252b5132 905 }
33fef721 906 else
ccc9c027
L		 907 {
908 const char *const *patt = NULL;
909
910 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
911 {
912 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
913 switch (cpu_arch_tune)
914 {
915 case PROCESSOR_UNKNOWN:
916 /* We use cpu_arch_isa_flags to check if we SHOULD
917 optimize for Cpu686. */
40fb9820 918 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 919 patt = alt_long_patt;
ccc9c027
L		 920 else
921 patt = f32_patt;
922 break;
ccc9c027
L		 923 case PROCESSOR_PENTIUMPRO:
924 case PROCESSOR_PENTIUM4:
925 case PROCESSOR_NOCONA:
ef05d495 926 case PROCESSOR_CORE:
76bc74dc
L		 927 case PROCESSOR_CORE2:
928 case PROCESSOR_GENERIC64:
929 patt = alt_long_patt;
930 break;
ccc9c027
L		 931 case PROCESSOR_K6:
932 case PROCESSOR_ATHLON:
933 case PROCESSOR_K8:
4eed87de 934 case PROCESSOR_AMDFAM10:
ccc9c027
L		 935 patt = alt_short_patt;
936 break;
76bc74dc 937 case PROCESSOR_I386:
ccc9c027
L		 938 case PROCESSOR_I486:
939 case PROCESSOR_PENTIUM:
940 case PROCESSOR_GENERIC32:
941 patt = f32_patt;
942 break;
4eed87de 943 }
ccc9c027
L		 944 }
945 else
946 {
947 switch (cpu_arch_tune)
948 {
949 case PROCESSOR_UNKNOWN:
950 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
951 PROCESSOR_UNKNOWN. */
952 abort ();
953 break;
954
76bc74dc 955 case PROCESSOR_I386:
ccc9c027
L		 956 case PROCESSOR_I486:
957 case PROCESSOR_PENTIUM:
ccc9c027
L		 958 case PROCESSOR_K6:
959 case PROCESSOR_ATHLON:
960 case PROCESSOR_K8:
4eed87de 961 case PROCESSOR_AMDFAM10:
ccc9c027
L		 962 case PROCESSOR_GENERIC32:
963 /* We use cpu_arch_isa_flags to check if we CAN optimize
964 for Cpu686. */
40fb9820 965 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 966 patt = alt_short_patt;
967 else
968 patt = f32_patt;
969 break;
76bc74dc
L		 970 case PROCESSOR_PENTIUMPRO:
971 case PROCESSOR_PENTIUM4:
972 case PROCESSOR_NOCONA:
973 case PROCESSOR_CORE:
ef05d495 974 case PROCESSOR_CORE2:
40fb9820 975 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 976 patt = alt_long_patt;
977 else
978 patt = f32_patt;
979 break;
980 case PROCESSOR_GENERIC64:
76bc74dc 981 patt = alt_long_patt;
ccc9c027 982 break;
4eed87de 983 }
ccc9c027
L		 984 }
985
76bc74dc
L		 986 if (patt == f32_patt)
987 {
988 /* If the padding is less than 15 bytes, we use the normal
989 ones. Otherwise, we use a jump instruction and adjust
990 its offset. */
991 if (count < 15)
992 memcpy (fragP->fr_literal + fragP->fr_fix,
993 patt[count - 1], count);
994 else
995 {
996 memcpy (fragP->fr_literal + fragP->fr_fix,
997 jump_31, count);
998 /* Adjust jump offset. */
999 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1000 }
1001 }
1002 else
1003 {
1004 /* Maximum length of an instruction is 15 byte. If the
1005 padding is greater than 15 bytes and we don't use jump,
1006 we have to break it into smaller pieces. */
1007 int padding = count;
1008 while (padding > 15)
1009 {
1010 padding -= 15;
1011 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1012 patt [14], 15);
1013 }
1014
1015 if (padding)
1016 memcpy (fragP->fr_literal + fragP->fr_fix,
1017 patt [padding - 1], padding);
1018 }
ccc9c027 1019 }
33fef721 1020 fragP->fr_var = count;
252b5132
RH		 1021}
1022
c6fb90c8
L		 1023static INLINE int
1024uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 1025{
c6fb90c8
L		 1026 switch (size)
1027 {
1028 case 3:
1029 if (x[2])
1030 return 0;
1031 case 2:
1032 if (x[1])
1033 return 0;
1034 case 1:
1035 return !x[0];
1036 default:
1037 abort ();
1038 }
40fb9820
L		 1039}
1040
c6fb90c8
L		 1041static INLINE void
1042uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 1043{
c6fb90c8
L		 1044 switch (size)
1045 {
1046 case 3:
1047 x[2] = v;
1048 case 2:
1049 x[1] = v;
1050 case 1:
1051 x[0] = v;
1052 break;
1053 default:
1054 abort ();
1055 }
1056}
40fb9820 1057
c6fb90c8
L		 1058static INLINE int
1059uints_equal (const unsigned int *x, const unsigned int *y,
1060 unsigned int size)
1061{
1062 switch (size)
1063 {
1064 case 3:
1065 if (x[2] != y [2])
1066 return 0;
1067 case 2:
1068 if (x[1] != y [1])
1069 return 0;
1070 case 1:
1071 return x[0] == y [0];
1072 break;
1073 default:
1074 abort ();
1075 }
1076}
40fb9820 1077
c6fb90c8
L		 1078#define UINTS_ALL_ZERO(x) \
1079 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
1080#define UINTS_SET(x, v) \
1081 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
1082#define UINTS_CLEAR(x) \
1083 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
1084#define UINTS_EQUAL(x, y) \
1085 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
1086
1087static INLINE int
1088cpu_flags_check_cpu64 (i386_cpu_flags f)
1089{
1090 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1091 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1092}
1093
c6fb90c8
L		 1094static INLINE i386_cpu_flags
1095cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1096{
c6fb90c8
L		 1097 switch (ARRAY_SIZE (x.array))
1098 {
1099 case 3:
1100 x.array [2] &= y.array [2];
1101 case 2:
1102 x.array [1] &= y.array [1];
1103 case 1:
1104 x.array [0] &= y.array [0];
1105 break;
1106 default:
1107 abort ();
1108 }
1109 return x;
1110}
40fb9820 1111
c6fb90c8
L		 1112static INLINE i386_cpu_flags
1113cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1114{
c6fb90c8 1115 switch (ARRAY_SIZE (x.array))
40fb9820 1116 {
c6fb90c8
L		 1117 case 3:
1118 x.array [2] |= y.array [2];
1119 case 2:
1120 x.array [1] |= y.array [1];
1121 case 1:
1122 x.array [0] |= y.array [0];
40fb9820
L		 1123 break;
1124 default:
1125 abort ();
1126 }
40fb9820
L		 1127 return x;
1128}
1129
3629bb00
L		 1130/* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1131 1 if compatible with arch, 0 if there is no match. */
1132
40fb9820
L		 1133static int
1134cpu_flags_match (i386_cpu_flags x)
1135{
3629bb00 1136 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
40fb9820
L		 1137
1138 x.bitfield.cpu64 = 0;
1139 x.bitfield.cpuno64 = 0;
1140
3629bb00
L		 1141 if (UINTS_ALL_ZERO (x))
1142 overlap |= 1;
1143 else
1144 {
1145 i386_cpu_flags cpu = cpu_arch_flags;
1146
1147 cpu.bitfield.cpu64 = 0;
1148 cpu.bitfield.cpuno64 = 0;
1149 cpu = cpu_flags_and (x, cpu);
1150 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1151 }
1152 return overlap;
40fb9820
L		 1153}
1154
c6fb90c8
L		 1155static INLINE i386_operand_type
1156operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1157{
c6fb90c8
L		 1158 switch (ARRAY_SIZE (x.array))
1159 {
1160 case 3:
1161 x.array [2] &= y.array [2];
1162 case 2:
1163 x.array [1] &= y.array [1];
1164 case 1:
1165 x.array [0] &= y.array [0];
1166 break;
1167 default:
1168 abort ();
1169 }
1170 return x;
40fb9820
L		 1171}
1172
c6fb90c8
L		 1173static INLINE i386_operand_type
1174operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1175{
c6fb90c8 1176 switch (ARRAY_SIZE (x.array))
40fb9820 1177 {
c6fb90c8
L		 1178 case 3:
1179 x.array [2] |= y.array [2];
1180 case 2:
1181 x.array [1] |= y.array [1];
1182 case 1:
1183 x.array [0] |= y.array [0];
40fb9820
L		 1184 break;
1185 default:
1186 abort ();
1187 }
c6fb90c8
L		 1188 return x;
1189}
40fb9820 1190
c6fb90c8
L		 1191static INLINE i386_operand_type
1192operand_type_xor (i386_operand_type x, i386_operand_type y)
1193{
1194 switch (ARRAY_SIZE (x.array))
1195 {
1196 case 3:
1197 x.array [2] ^= y.array [2];
1198 case 2:
1199 x.array [1] ^= y.array [1];
1200 case 1:
1201 x.array [0] ^= y.array [0];
1202 break;
1203 default:
1204 abort ();
1205 }
40fb9820
L		 1206 return x;
1207}
1208
1209static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1210static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1211static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1212static const i386_operand_type reg16_inoutportreg
1213 = OPERAND_TYPE_REG16_INOUTPORTREG;
1214static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1215static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1216static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1217static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1218static const i386_operand_type anydisp
1219 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1220static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1221static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1222static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1223static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1224static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1225static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1226static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1227static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1228static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1229static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1230
1231enum operand_type
1232{
1233 reg,
40fb9820
L		 1234 imm,
1235 disp,
1236 anymem
1237};
1238
c6fb90c8 1239static INLINE int
40fb9820
L		 1240operand_type_check (i386_operand_type t, enum operand_type c)
1241{
1242 switch (c)
1243 {
1244 case reg:
1245 return (t.bitfield.reg8
1246 || t.bitfield.reg16
1247 || t.bitfield.reg32
1248 || t.bitfield.reg64);
1249
40fb9820
L		 1250 case imm:
1251 return (t.bitfield.imm8
1252 || t.bitfield.imm8s
1253 || t.bitfield.imm16
1254 || t.bitfield.imm32
1255 || t.bitfield.imm32s
1256 || t.bitfield.imm64);
1257
1258 case disp:
1259 return (t.bitfield.disp8
1260 || t.bitfield.disp16
1261 || t.bitfield.disp32
1262 || t.bitfield.disp32s
1263 || t.bitfield.disp64);
1264
1265 case anymem:
1266 return (t.bitfield.disp8
1267 || t.bitfield.disp16
1268 || t.bitfield.disp32
1269 || t.bitfield.disp32s
1270 || t.bitfield.disp64
1271 || t.bitfield.baseindex);
1272
1273 default:
1274 abort ();
1275 }
1276}
1277
5c07affc
L		 1278/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1279 operand J for instruction template T. */
1280
1281static INLINE int
1282match_reg_size (const template *t, unsigned int j)
1283{
1284 return !((i.types[j].bitfield.byte
1285 && !t->operand_types[j].bitfield.byte)
1286 || (i.types[j].bitfield.word
1287 && !t->operand_types[j].bitfield.word)
1288 || (i.types[j].bitfield.dword
1289 && !t->operand_types[j].bitfield.dword)
1290 || (i.types[j].bitfield.qword
1291 && !t->operand_types[j].bitfield.qword));
1292}
1293
1294/* Return 1 if there is no conflict in any size on operand J for
1295 instruction template T. */
1296
1297static INLINE int
1298match_mem_size (const template *t, unsigned int j)
1299{
1300 return (match_reg_size (t, j)
1301 && !((i.types[j].bitfield.unspecified
1302 && !t->operand_types[j].bitfield.unspecified)
1303 || (i.types[j].bitfield.fword
1304 && !t->operand_types[j].bitfield.fword)
1305 || (i.types[j].bitfield.tbyte
1306 && !t->operand_types[j].bitfield.tbyte)
1307 || (i.types[j].bitfield.xmmword
1308 && !t->operand_types[j].bitfield.xmmword)));
1309}
1310
1311/* Return 1 if there is no size conflict on any operands for
1312 instruction template T. */
1313
1314static INLINE int
1315operand_size_match (const template *t)
1316{
1317 unsigned int j;
1318 int match = 1;
1319
1320 /* Don't check jump instructions. */
1321 if (t->opcode_modifier.jump
1322 || t->opcode_modifier.jumpbyte
1323 || t->opcode_modifier.jumpdword
1324 || t->opcode_modifier.jumpintersegment)
1325 return match;
1326
1327 /* Check memory and accumulator operand size. */
1328 for (j = 0; j < i.operands; j++)
1329 {
1330 if (t->operand_types[j].bitfield.anysize)
1331 continue;
1332
1333 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1334 {
1335 match = 0;
1336 break;
1337 }
1338
1339 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1340 {
1341 match = 0;
1342 break;
1343 }
1344 }
1345
1346 if (match
1347 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1348 return match;
1349
1350 /* Check reverse. */
1351 assert (i.operands == 2);
1352
1353 match = 1;
1354 for (j = 0; j < 2; j++)
1355 {
1356 if (t->operand_types[j].bitfield.acc
1357 && !match_reg_size (t, j ? 0 : 1))
1358 {
1359 match = 0;
1360 break;
1361 }
1362
1363 if (i.types[j].bitfield.mem
1364 && !match_mem_size (t, j ? 0 : 1))
1365 {
1366 match = 0;
1367 break;
1368 }
1369 }
1370
1371 return match;
1372}
1373
c6fb90c8 1374static INLINE int
40fb9820
L		 1375operand_type_match (i386_operand_type overlap,
1376 i386_operand_type given)
1377{
1378 i386_operand_type temp = overlap;
1379
1380 temp.bitfield.jumpabsolute = 0;
7d5e4556 1381 temp.bitfield.unspecified = 0;
5c07affc
L		 1382 temp.bitfield.byte = 0;
1383 temp.bitfield.word = 0;
1384 temp.bitfield.dword = 0;
1385 temp.bitfield.fword = 0;
1386 temp.bitfield.qword = 0;
1387 temp.bitfield.tbyte = 0;
1388 temp.bitfield.xmmword = 0;
c6fb90c8 1389 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1390 return 0;
1391
1392 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1393 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1394}
1395
7d5e4556 1396/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1397 unless the expected operand type register overlap is null.
1398 Note that Acc in a template matches every size of reg. */
1399
c6fb90c8 1400static INLINE int
40fb9820
L		 1401operand_type_register_match (i386_operand_type m0,
1402 i386_operand_type g0,
1403 i386_operand_type t0,
1404 i386_operand_type m1,
1405 i386_operand_type g1,
1406 i386_operand_type t1)
1407{
1408 if (!operand_type_check (g0, reg))
1409 return 1;
1410
1411 if (!operand_type_check (g1, reg))
1412 return 1;
1413
1414 if (g0.bitfield.reg8 == g1.bitfield.reg8
1415 && g0.bitfield.reg16 == g1.bitfield.reg16
1416 && g0.bitfield.reg32 == g1.bitfield.reg32
1417 && g0.bitfield.reg64 == g1.bitfield.reg64)
1418 return 1;
1419
1420 if (m0.bitfield.acc)
1421 {
1422 t0.bitfield.reg8 = 1;
1423 t0.bitfield.reg16 = 1;
1424 t0.bitfield.reg32 = 1;
1425 t0.bitfield.reg64 = 1;
1426 }
1427
1428 if (m1.bitfield.acc)
1429 {
1430 t1.bitfield.reg8 = 1;
1431 t1.bitfield.reg16 = 1;
1432 t1.bitfield.reg32 = 1;
1433 t1.bitfield.reg64 = 1;
1434 }
1435
1436 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1437 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1438 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1439 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1440}
1441
252b5132 1442static INLINE unsigned int
40fb9820 1443mode_from_disp_size (i386_operand_type t)
252b5132 1444{
40fb9820
L		 1445 if (t.bitfield.disp8)
1446 return 1;
1447 else if (t.bitfield.disp16
1448 || t.bitfield.disp32
1449 || t.bitfield.disp32s)
1450 return 2;
1451 else
1452 return 0;
252b5132
RH		 1453}
1454
1455static INLINE int
e3bb37b5 1456fits_in_signed_byte (offsetT num)
252b5132
RH		 1457{
1458 return (num >= -128) && (num <= 127);
47926f60 1459}
252b5132
RH		 1460
1461static INLINE int
e3bb37b5 1462fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1463{
1464 return (num & 0xff) == num;
47926f60 1465}
252b5132
RH		 1466
1467static INLINE int
e3bb37b5 1468fits_in_unsigned_word (offsetT num)
252b5132
RH		 1469{
1470 return (num & 0xffff) == num;
47926f60 1471}
252b5132
RH		 1472
1473static INLINE int
e3bb37b5 1474fits_in_signed_word (offsetT num)
252b5132
RH		 1475{
1476 return (-32768 <= num) && (num <= 32767);
47926f60 1477}
2a962e6d 1478
3e73aa7c 1479static INLINE int
e3bb37b5 1480fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1481{
1482#ifndef BFD64
1483 return 1;
1484#else
1485 return (!(((offsetT) -1 << 31) & num)
1486 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1487#endif
1488} /* fits_in_signed_long() */
2a962e6d 1489
3e73aa7c 1490static INLINE int
e3bb37b5 1491fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1492{
1493#ifndef BFD64
1494 return 1;
1495#else
1496 return (num & (((offsetT) 2 << 31) - 1)) == num;
1497#endif
1498} /* fits_in_unsigned_long() */
252b5132 1499
40fb9820 1500static i386_operand_type
e3bb37b5 1501smallest_imm_type (offsetT num)
252b5132 1502{
40fb9820
L		 1503 i386_operand_type t;
1504
c6fb90c8 1505 UINTS_CLEAR (t);
40fb9820
L		 1506 t.bitfield.imm64 = 1;
1507
1508 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1509 {
1510 /* This code is disabled on the 486 because all the Imm1 forms
1511 in the opcode table are slower on the i486. They're the
1512 versions with the implicitly specified single-position
1513 displacement, which has another syntax if you really want to
1514 use that form. */
40fb9820
L		 1515 t.bitfield.imm1 = 1;
1516 t.bitfield.imm8 = 1;
1517 t.bitfield.imm8s = 1;
1518 t.bitfield.imm16 = 1;
1519 t.bitfield.imm32 = 1;
1520 t.bitfield.imm32s = 1;
1521 }
1522 else if (fits_in_signed_byte (num))
1523 {
1524 t.bitfield.imm8 = 1;
1525 t.bitfield.imm8s = 1;
1526 t.bitfield.imm16 = 1;
1527 t.bitfield.imm32 = 1;
1528 t.bitfield.imm32s = 1;
1529 }
1530 else if (fits_in_unsigned_byte (num))
1531 {
1532 t.bitfield.imm8 = 1;
1533 t.bitfield.imm16 = 1;
1534 t.bitfield.imm32 = 1;
1535 t.bitfield.imm32s = 1;
1536 }
1537 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1538 {
1539 t.bitfield.imm16 = 1;
1540 t.bitfield.imm32 = 1;
1541 t.bitfield.imm32s = 1;
1542 }
1543 else if (fits_in_signed_long (num))
1544 {
1545 t.bitfield.imm32 = 1;
1546 t.bitfield.imm32s = 1;
1547 }
1548 else if (fits_in_unsigned_long (num))
1549 t.bitfield.imm32 = 1;
1550
1551 return t;
47926f60 1552}
252b5132 1553
847f7ad4 1554static offsetT
e3bb37b5 1555offset_in_range (offsetT val, int size)
847f7ad4 1556{
508866be 1557 addressT mask;
ba2adb93 1558
847f7ad4
AM		 1559 switch (size)
1560 {
508866be
L		 1561 case 1: mask = ((addressT) 1 << 8) - 1; break;
1562 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1563 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1564#ifdef BFD64
1565 case 8: mask = ((addressT) 2 << 63) - 1; break;
1566#endif
47926f60 1567 default: abort ();
847f7ad4
AM		 1568 }
1569
ba2adb93 1570 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1571 if (!use_rela_relocations)
1572 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1573 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1574
47926f60 1575 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1576 {
1577 char buf1[40], buf2[40];
1578
1579 sprint_value (buf1, val);
1580 sprint_value (buf2, val & mask);
1581 as_warn (_("%s shortened to %s"), buf1, buf2);
1582 }
1583 return val & mask;
1584}
1585
252b5132
RH		 1586/* Returns 0 if attempting to add a prefix where one from the same
1587 class already exists, 1 if non rep/repne added, 2 if rep/repne
1588 added. */
1589static int
e3bb37b5 1590add_prefix (unsigned int prefix)
252b5132
RH		 1591{
1592 int ret = 1;
b1905489 1593 unsigned int q;
252b5132 1594
29b0f896
AM		 1595 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1596 && flag_code == CODE_64BIT)
b1905489 1597 {
161a04f6
L		 1598 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1599 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1600 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1601 ret = 0;
1602 q = REX_PREFIX;
1603 }
3e73aa7c 1604 else
b1905489
JB		 1605 {
1606 switch (prefix)
1607 {
1608 default:
1609 abort ();
1610
1611 case CS_PREFIX_OPCODE:
1612 case DS_PREFIX_OPCODE:
1613 case ES_PREFIX_OPCODE:
1614 case FS_PREFIX_OPCODE:
1615 case GS_PREFIX_OPCODE:
1616 case SS_PREFIX_OPCODE:
1617 q = SEG_PREFIX;
1618 break;
1619
1620 case REPNE_PREFIX_OPCODE:
1621 case REPE_PREFIX_OPCODE:
1622 ret = 2;
1623 /* fall thru */
1624 case LOCK_PREFIX_OPCODE:
1625 q = LOCKREP_PREFIX;
1626 break;
1627
1628 case FWAIT_OPCODE:
1629 q = WAIT_PREFIX;
1630 break;
1631
1632 case ADDR_PREFIX_OPCODE:
1633 q = ADDR_PREFIX;
1634 break;
1635
1636 case DATA_PREFIX_OPCODE:
1637 q = DATA_PREFIX;
1638 break;
1639 }
1640 if (i.prefix[q] != 0)
1641 ret = 0;
1642 }
252b5132 1643
b1905489 1644 if (ret)
252b5132 1645 {
b1905489
JB		 1646 if (!i.prefix[q])
1647 ++i.prefixes;
1648 i.prefix[q] |= prefix;
252b5132 1649 }
b1905489
JB		 1650 else
1651 as_bad (_("same type of prefix used twice"));
252b5132 1652
252b5132
RH		 1653 return ret;
1654}
1655
1656static void
e3bb37b5 1657set_code_flag (int value)
eecb386c 1658{
3e73aa7c 1659 flag_code = value;
40fb9820
L		 1660 if (flag_code == CODE_64BIT)
1661 {
1662 cpu_arch_flags.bitfield.cpu64 = 1;
1663 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1664 }
1665 else
1666 {
1667 cpu_arch_flags.bitfield.cpu64 = 0;
1668 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1669 }
1670 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1671 {
1672 as_bad (_("64bit mode not supported on this CPU."));
1673 }
40fb9820 1674 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1675 {
1676 as_bad (_("32bit mode not supported on this CPU."));
1677 }
eecb386c
AM		 1678 stackop_size = '\0';
1679}
1680
1681static void
e3bb37b5 1682set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1683{
3e73aa7c 1684 flag_code = new_code_flag;
40fb9820
L		 1685 if (flag_code != CODE_16BIT)
1686 abort ();
1687 cpu_arch_flags.bitfield.cpu64 = 0;
1688 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1689 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1690}
1691
1692static void
e3bb37b5 1693set_intel_syntax (int syntax_flag)
252b5132
RH		 1694{
1695 /* Find out if register prefixing is specified. */
1696 int ask_naked_reg = 0;
1697
1698 SKIP_WHITESPACE ();
29b0f896 1699 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1700 {
1701 char *string = input_line_pointer;
1702 int e = get_symbol_end ();
1703
47926f60 1704 if (strcmp (string, "prefix") == 0)
252b5132 1705 ask_naked_reg = 1;
47926f60 1706 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1707 ask_naked_reg = -1;
1708 else
d0b47220 1709 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1710 *input_line_pointer = e;
1711 }
1712 demand_empty_rest_of_line ();
c3332e24 1713
252b5132
RH		 1714 intel_syntax = syntax_flag;
1715
1716 if (ask_naked_reg == 0)
f86103b7
AM		 1717 allow_naked_reg = (intel_syntax
1718 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1719 else
1720 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1721
e4a3b5a4 1722 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1723 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1724 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1725}
1726
1efbbeb4
L		 1727static void
1728set_intel_mnemonic (int mnemonic_flag)
1729{
e1d4d893 1730 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1731}
1732
db51cc60
L		 1733static void
1734set_allow_index_reg (int flag)
1735{
1736 allow_index_reg = flag;
1737}
1738
e413e4e9 1739static void
e3bb37b5 1740set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1741{
47926f60 1742 SKIP_WHITESPACE ();
e413e4e9 1743
29b0f896 1744 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1745 {
1746 char *string = input_line_pointer;
1747 int e = get_symbol_end ();
9103f4f4 1748 unsigned int i;
40fb9820 1749 i386_cpu_flags flags;
e413e4e9 1750
9103f4f4 1751 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1752 {
1753 if (strcmp (string, cpu_arch[i].name) == 0)
1754 {
5c6af06e
JB		 1755 if (*string != '.')
1756 {
1757 cpu_arch_name = cpu_arch[i].name;
1758 cpu_sub_arch_name = NULL;
40fb9820
L		 1759 cpu_arch_flags = cpu_arch[i].flags;
1760 if (flag_code == CODE_64BIT)
1761 {
1762 cpu_arch_flags.bitfield.cpu64 = 1;
1763 cpu_arch_flags.bitfield.cpuno64 = 0;
1764 }
1765 else
1766 {
1767 cpu_arch_flags.bitfield.cpu64 = 0;
1768 cpu_arch_flags.bitfield.cpuno64 = 1;
1769 }
ccc9c027 1770 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1771 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1772 if (!cpu_arch_tune_set)
1773 {
1774 cpu_arch_tune = cpu_arch_isa;
1775 cpu_arch_tune_flags = cpu_arch_isa_flags;
1776 }
5c6af06e
JB		 1777 break;
1778 }
40fb9820 1779
c6fb90c8
L		 1780 flags = cpu_flags_or (cpu_arch_flags,
1781 cpu_arch[i].flags);
1782 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e 1783 {
6305a203
L		 1784 if (cpu_sub_arch_name)
1785 {
1786 char *name = cpu_sub_arch_name;
1787 cpu_sub_arch_name = concat (name,
1788 cpu_arch[i].name,
1bf57e9f 1789 (const char *) NULL);
6305a203
L		 1790 free (name);
1791 }
1792 else
1793 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1794 cpu_arch_flags = flags;
5c6af06e
JB		 1795 }
1796 *input_line_pointer = e;
1797 demand_empty_rest_of_line ();
1798 return;
e413e4e9
AM		 1799 }
1800 }
9103f4f4 1801 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1802 as_bad (_("no such architecture: `%s'"), string);
1803
1804 *input_line_pointer = e;
1805 }
1806 else
1807 as_bad (_("missing cpu architecture"));
1808
fddf5b5b
AM		 1809 no_cond_jump_promotion = 0;
1810 if (*input_line_pointer == ','
29b0f896 1811 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1812 {
1813 char *string = ++input_line_pointer;
1814 int e = get_symbol_end ();
1815
1816 if (strcmp (string, "nojumps") == 0)
1817 no_cond_jump_promotion = 1;
1818 else if (strcmp (string, "jumps") == 0)
1819 ;
1820 else
1821 as_bad (_("no such architecture modifier: `%s'"), string);
1822
1823 *input_line_pointer = e;
1824 }
1825
e413e4e9
AM		 1826 demand_empty_rest_of_line ();
1827}
1828
b9d79e03
JH		 1829unsigned long
1830i386_mach ()
1831{
1832 if (!strcmp (default_arch, "x86_64"))
1833 return bfd_mach_x86_64;
1834 else if (!strcmp (default_arch, "i386"))
1835 return bfd_mach_i386_i386;
1836 else
1837 as_fatal (_("Unknown architecture"));
1838}
b9d79e03 1839\f
252b5132
RH		 1840void
1841md_begin ()
1842{
1843 const char *hash_err;
1844
47926f60 1845 /* Initialize op_hash hash table. */
252b5132
RH		 1846 op_hash = hash_new ();
1847
1848 {
29b0f896
AM		 1849 const template *optab;
1850 templates *core_optab;
252b5132 1851
47926f60
KH		 1852 /* Setup for loop. */
1853 optab = i386_optab;
252b5132
RH		 1854 core_optab = (templates *) xmalloc (sizeof (templates));
1855 core_optab->start = optab;
1856
1857 while (1)
1858 {
1859 ++optab;
1860 if (optab->name == NULL
1861 || strcmp (optab->name, (optab - 1)->name) != 0)
1862 {
1863 /* different name --> ship out current template list;
47926f60 1864 add to hash table; & begin anew. */
252b5132
RH		 1865 core_optab->end = optab;
1866 hash_err = hash_insert (op_hash,
1867 (optab - 1)->name,
1868 (PTR) core_optab);
1869 if (hash_err)
1870 {
252b5132
RH		 1871 as_fatal (_("Internal Error: Can't hash %s: %s"),
1872 (optab - 1)->name,
1873 hash_err);
1874 }
1875 if (optab->name == NULL)
1876 break;
1877 core_optab = (templates *) xmalloc (sizeof (templates));
1878 core_optab->start = optab;
1879 }
1880 }
1881 }
1882
47926f60 1883 /* Initialize reg_hash hash table. */
252b5132
RH		 1884 reg_hash = hash_new ();
1885 {
29b0f896 1886 const reg_entry *regtab;
c3fe08fa 1887 unsigned int regtab_size = i386_regtab_size;
252b5132 1888
c3fe08fa 1889 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1890 {
1891 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1892 if (hash_err)
3e73aa7c
JH		 1893 as_fatal (_("Internal Error: Can't hash %s: %s"),
1894 regtab->reg_name,
1895 hash_err);
252b5132
RH		 1896 }
1897 }
1898
47926f60 1899 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1900 {
29b0f896
AM		 1901 int c;
1902 char *p;
252b5132
RH		 1903
1904 for (c = 0; c < 256; c++)
1905 {
3882b010 1906 if (ISDIGIT (c))
252b5132
RH		 1907 {
1908 digit_chars[c] = c;
1909 mnemonic_chars[c] = c;
1910 register_chars[c] = c;
1911 operand_chars[c] = c;
1912 }
3882b010 1913 else if (ISLOWER (c))
252b5132
RH		 1914 {
1915 mnemonic_chars[c] = c;
1916 register_chars[c] = c;
1917 operand_chars[c] = c;
1918 }
3882b010 1919 else if (ISUPPER (c))
252b5132 1920 {
3882b010 1921 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1922 register_chars[c] = mnemonic_chars[c];
1923 operand_chars[c] = c;
1924 }
1925
3882b010 1926 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1927 identifier_chars[c] = c;
1928 else if (c >= 128)
1929 {
1930 identifier_chars[c] = c;
1931 operand_chars[c] = c;
1932 }
1933 }
1934
1935#ifdef LEX_AT
1936 identifier_chars['@'] = '@';
32137342
NC		 1937#endif
1938#ifdef LEX_QM
1939 identifier_chars['?'] = '?';
1940 operand_chars['?'] = '?';
252b5132 1941#endif
252b5132 1942 digit_chars['-'] = '-';
791fe849 1943 mnemonic_chars['-'] = '-';
0003779b 1944 mnemonic_chars['.'] = '.';
252b5132
RH		 1945 identifier_chars['_'] = '_';
1946 identifier_chars['.'] = '.';
1947
1948 for (p = operand_special_chars; *p != '\0'; p++)
1949 operand_chars[(unsigned char) *p] = *p;
1950 }
1951
1952#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1953 if (IS_ELF)
252b5132
RH		 1954 {
1955 record_alignment (text_section, 2);
1956 record_alignment (data_section, 2);
1957 record_alignment (bss_section, 2);
1958 }
1959#endif
a4447b93
RH		 1960
1961 if (flag_code == CODE_64BIT)
1962 {
1963 x86_dwarf2_return_column = 16;
1964 x86_cie_data_alignment = -8;
1965 }
1966 else
1967 {
1968 x86_dwarf2_return_column = 8;
1969 x86_cie_data_alignment = -4;
1970 }
252b5132
RH		 1971}
1972
1973void
e3bb37b5 1974i386_print_statistics (FILE *file)
252b5132
RH		 1975{
1976 hash_print_statistics (file, "i386 opcode", op_hash);
1977 hash_print_statistics (file, "i386 register", reg_hash);
1978}
1979\f
252b5132
RH		 1980#ifdef DEBUG386
1981
ce8a8b2f 1982/* Debugging routines for md_assemble. */
e3bb37b5 1983static void pte (template *);
40fb9820 1984static void pt (i386_operand_type);
e3bb37b5
L		 1985static void pe (expressionS *);
1986static void ps (symbolS *);
252b5132
RH		 1987
1988static void
e3bb37b5 1989pi (char *line, i386_insn *x)
252b5132 1990{
09f131f2 1991 unsigned int i;
252b5132
RH		 1992
1993 fprintf (stdout, "%s: template ", line);
1994 pte (&x->tm);
09f131f2
JH		 1995 fprintf (stdout, " address: base %s index %s scale %x\n",
1996 x->base_reg ? x->base_reg->reg_name : "none",
1997 x->index_reg ? x->index_reg->reg_name : "none",
1998 x->log2_scale_factor);
1999 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2000 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2001 fprintf (stdout, " sib: base %x index %x scale %x\n",
2002 x->sib.base, x->sib.index, x->sib.scale);
2003 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2004 (x->rex & REX_W) != 0,
2005 (x->rex & REX_R) != 0,
2006 (x->rex & REX_X) != 0,
2007 (x->rex & REX_B) != 0);
85f10a01
MM		 2008 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2009 x->drex.reg, x->drex.rex);
252b5132
RH		 2010 for (i = 0; i < x->operands; i++)
2011 {
2012 fprintf (stdout, " #%d: ", i + 1);
2013 pt (x->types[i]);
2014 fprintf (stdout, "\n");
40fb9820
L		 2015 if (x->types[i].bitfield.reg8
2016 || x->types[i].bitfield.reg16
2017 || x->types[i].bitfield.reg32
2018 || x->types[i].bitfield.reg64
2019 || x->types[i].bitfield.regmmx
2020 || x->types[i].bitfield.regxmm
2021 || x->types[i].bitfield.sreg2
2022 || x->types[i].bitfield.sreg3
2023 || x->types[i].bitfield.control
2024 || x->types[i].bitfield.debug
2025 || x->types[i].bitfield.test)
520dc8e8 2026 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2027 if (operand_type_check (x->types[i], imm))
520dc8e8 2028 pe (x->op[i].imms);
40fb9820 2029 if (operand_type_check (x->types[i], disp))
520dc8e8 2030 pe (x->op[i].disps);
252b5132
RH		 2031 }
2032}
2033
2034static void
e3bb37b5 2035pte (template *t)
252b5132 2036{
09f131f2 2037 unsigned int i;
252b5132 2038 fprintf (stdout, " %d operands ", t->operands);
47926f60 2039 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2040 if (t->extension_opcode != None)
2041 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2042 if (t->opcode_modifier.d)
252b5132 2043 fprintf (stdout, "D");
40fb9820 2044 if (t->opcode_modifier.w)
252b5132
RH		 2045 fprintf (stdout, "W");
2046 fprintf (stdout, "\n");
2047 for (i = 0; i < t->operands; i++)
2048 {
2049 fprintf (stdout, " #%d type ", i + 1);
2050 pt (t->operand_types[i]);
2051 fprintf (stdout, "\n");
2052 }
2053}
2054
2055static void
e3bb37b5 2056pe (expressionS *e)
252b5132 2057{
24eab124 2058 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2059 fprintf (stdout, " add_number %ld (%lx)\n",
2060 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2061 if (e->X_add_symbol)
2062 {
2063 fprintf (stdout, " add_symbol ");
2064 ps (e->X_add_symbol);
2065 fprintf (stdout, "\n");
2066 }
2067 if (e->X_op_symbol)
2068 {
2069 fprintf (stdout, " op_symbol ");
2070 ps (e->X_op_symbol);
2071 fprintf (stdout, "\n");
2072 }
2073}
2074
2075static void
e3bb37b5 2076ps (symbolS *s)
252b5132
RH		 2077{
2078 fprintf (stdout, "%s type %s%s",
2079 S_GET_NAME (s),
2080 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2081 segment_name (S_GET_SEGMENT (s)));
2082}
2083
7b81dfbb 2084static struct type_name
252b5132 2085 {
40fb9820
L		 2086 i386_operand_type mask;
2087 const char *name;
252b5132 2088 }
7b81dfbb 2089const type_names[] =
252b5132 2090{
40fb9820
L		 2091 { OPERAND_TYPE_REG8, "r8" },
2092 { OPERAND_TYPE_REG16, "r16" },
2093 { OPERAND_TYPE_REG32, "r32" },
2094 { OPERAND_TYPE_REG64, "r64" },
2095 { OPERAND_TYPE_IMM8, "i8" },
2096 { OPERAND_TYPE_IMM8, "i8s" },
2097 { OPERAND_TYPE_IMM16, "i16" },
2098 { OPERAND_TYPE_IMM32, "i32" },
2099 { OPERAND_TYPE_IMM32S, "i32s" },
2100 { OPERAND_TYPE_IMM64, "i64" },
2101 { OPERAND_TYPE_IMM1, "i1" },
2102 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2103 { OPERAND_TYPE_DISP8, "d8" },
2104 { OPERAND_TYPE_DISP16, "d16" },
2105 { OPERAND_TYPE_DISP32, "d32" },
2106 { OPERAND_TYPE_DISP32S, "d32s" },
2107 { OPERAND_TYPE_DISP64, "d64" },
2108 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2109 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2110 { OPERAND_TYPE_CONTROL, "control reg" },
2111 { OPERAND_TYPE_TEST, "test reg" },
2112 { OPERAND_TYPE_DEBUG, "debug reg" },
2113 { OPERAND_TYPE_FLOATREG, "FReg" },
2114 { OPERAND_TYPE_FLOATACC, "FAcc" },
2115 { OPERAND_TYPE_SREG2, "SReg2" },
2116 { OPERAND_TYPE_SREG3, "SReg3" },
2117 { OPERAND_TYPE_ACC, "Acc" },
2118 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2119 { OPERAND_TYPE_REGMMX, "rMMX" },
2120 { OPERAND_TYPE_REGXMM, "rXMM" },
2121 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2122};
2123
2124static void
40fb9820 2125pt (i386_operand_type t)
252b5132 2126{
40fb9820 2127 unsigned int j;
c6fb90c8 2128 i386_operand_type a;
252b5132 2129
40fb9820 2130 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2131 {
2132 a = operand_type_and (t, type_names[j].mask);
2133 if (!UINTS_ALL_ZERO (a))
2134 fprintf (stdout, "%s, ", type_names[j].name);
2135 }
252b5132
RH		 2136 fflush (stdout);
2137}
2138
2139#endif /* DEBUG386 */
2140\f
252b5132 2141static bfd_reloc_code_real_type
3956db08 2142reloc (unsigned int size,
64e74474
AM		 2143 int pcrel,
2144 int sign,
2145 bfd_reloc_code_real_type other)
252b5132 2146{
47926f60 2147 if (other != NO_RELOC)
3956db08
JB		 2148 {
2149 reloc_howto_type *reloc;
2150
2151 if (size == 8)
2152 switch (other)
2153 {
64e74474
AM		 2154 case BFD_RELOC_X86_64_GOT32:
2155 return BFD_RELOC_X86_64_GOT64;
2156 break;
2157 case BFD_RELOC_X86_64_PLTOFF64:
2158 return BFD_RELOC_X86_64_PLTOFF64;
2159 break;
2160 case BFD_RELOC_X86_64_GOTPC32:
2161 other = BFD_RELOC_X86_64_GOTPC64;
2162 break;
2163 case BFD_RELOC_X86_64_GOTPCREL:
2164 other = BFD_RELOC_X86_64_GOTPCREL64;
2165 break;
2166 case BFD_RELOC_X86_64_TPOFF32:
2167 other = BFD_RELOC_X86_64_TPOFF64;
2168 break;
2169 case BFD_RELOC_X86_64_DTPOFF32:
2170 other = BFD_RELOC_X86_64_DTPOFF64;
2171 break;
2172 default:
2173 break;
3956db08 2174 }
e05278af
JB		 2175
2176 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2177 if (size == 4 && flag_code != CODE_64BIT)
2178 sign = -1;
2179
3956db08
JB		 2180 reloc = bfd_reloc_type_lookup (stdoutput, other);
2181 if (!reloc)
2182 as_bad (_("unknown relocation (%u)"), other);
2183 else if (size != bfd_get_reloc_size (reloc))
2184 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2185 bfd_get_reloc_size (reloc),
2186 size);
2187 else if (pcrel && !reloc->pc_relative)
2188 as_bad (_("non-pc-relative relocation for pc-relative field"));
2189 else if ((reloc->complain_on_overflow == complain_overflow_signed
2190 && !sign)
2191 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2192 && sign > 0))
3956db08
JB		 2193 as_bad (_("relocated field and relocation type differ in signedness"));
2194 else
2195 return other;
2196 return NO_RELOC;
2197 }
252b5132
RH		 2198
2199 if (pcrel)
2200 {
3e73aa7c 2201 if (!sign)
3956db08 2202 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2203 switch (size)
2204 {
2205 case 1: return BFD_RELOC_8_PCREL;
2206 case 2: return BFD_RELOC_16_PCREL;
2207 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2208 case 8: return BFD_RELOC_64_PCREL;
252b5132 2209 }
3956db08 2210 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2211 }
2212 else
2213 {
3956db08 2214 if (sign > 0)
e5cb08ac 2215 switch (size)
3e73aa7c
JH		 2216 {
2217 case 4: return BFD_RELOC_X86_64_32S;
2218 }
2219 else
2220 switch (size)
2221 {
2222 case 1: return BFD_RELOC_8;
2223 case 2: return BFD_RELOC_16;
2224 case 4: return BFD_RELOC_32;
2225 case 8: return BFD_RELOC_64;
2226 }
3956db08
JB		 2227 as_bad (_("cannot do %s %u byte relocation"),
2228 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2229 }
2230
bfb32b52 2231 abort ();
252b5132
RH		 2232 return BFD_RELOC_NONE;
2233}
2234
47926f60
KH		 2235/* Here we decide which fixups can be adjusted to make them relative to
2236 the beginning of the section instead of the symbol. Basically we need
2237 to make sure that the dynamic relocations are done correctly, so in
2238 some cases we force the original symbol to be used. */
2239
252b5132 2240int
e3bb37b5 2241tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2242{
6d249963 2243#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2244 if (!IS_ELF)
31312f95
AM		 2245 return 1;
2246
a161fe53
AM		 2247 /* Don't adjust pc-relative references to merge sections in 64-bit
2248 mode. */
2249 if (use_rela_relocations
2250 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2251 && fixP->fx_pcrel)
252b5132 2252 return 0;
31312f95 2253
8d01d9a9
AJ		 2254 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2255 and changed later by validate_fix. */
2256 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2257 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2258 return 0;
2259
ce8a8b2f 2260 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2261 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2262 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2263 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2264 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2265 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2266 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2267 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2268 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2269 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2270 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2271 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2272 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2273 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2274 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2275 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2276 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2277 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2278 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2279 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2280 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2281 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2282 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2283 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2284 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2285 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2286 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2287 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2288 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2289 return 0;
31312f95 2290#endif
252b5132
RH		 2291 return 1;
2292}
252b5132 2293
b4cac588 2294static int
e3bb37b5 2295intel_float_operand (const char *mnemonic)
252b5132 2296{
9306ca4a
JB		 2297 /* Note that the value returned is meaningful only for opcodes with (memory)
2298 operands, hence the code here is free to improperly handle opcodes that
2299 have no operands (for better performance and smaller code). */
2300
2301 if (mnemonic[0] != 'f')
2302 return 0; /* non-math */
2303
2304 switch (mnemonic[1])
2305 {
2306 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2307 the fs segment override prefix not currently handled because no
2308 call path can make opcodes without operands get here */
2309 case 'i':
2310 return 2 /* integer op */;
2311 case 'l':
2312 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2313 return 3; /* fldcw/fldenv */
2314 break;
2315 case 'n':
2316 if (mnemonic[2] != 'o' /* fnop */)
2317 return 3; /* non-waiting control op */
2318 break;
2319 case 'r':
2320 if (mnemonic[2] == 's')
2321 return 3; /* frstor/frstpm */
2322 break;
2323 case 's':
2324 if (mnemonic[2] == 'a')
2325 return 3; /* fsave */
2326 if (mnemonic[2] == 't')
2327 {
2328 switch (mnemonic[3])
2329 {
2330 case 'c': /* fstcw */
2331 case 'd': /* fstdw */
2332 case 'e': /* fstenv */
2333 case 's': /* fsts[gw] */
2334 return 3;
2335 }
2336 }
2337 break;
2338 case 'x':
2339 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2340 return 0; /* fxsave/fxrstor are not really math ops */
2341 break;
2342 }
252b5132 2343
9306ca4a 2344 return 1;
252b5132
RH		 2345}
2346
2347/* This is the guts of the machine-dependent assembler. LINE points to a
2348 machine dependent instruction. This function is supposed to emit
2349 the frags/bytes it assembles to. */
2350
2351void
2352md_assemble (line)
2353 char *line;
2354{
40fb9820 2355 unsigned int j;
252b5132
RH		 2356 char mnemonic[MAX_MNEM_SIZE];
2357
47926f60 2358 /* Initialize globals. */
252b5132
RH		 2359 memset (&i, '\0', sizeof (i));
2360 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2361 i.reloc[j] = NO_RELOC;
252b5132
RH		 2362 memset (disp_expressions, '\0', sizeof (disp_expressions));
2363 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2364 save_stack_p = save_stack;
252b5132
RH		 2365
2366 /* First parse an instruction mnemonic & call i386_operand for the operands.
2367 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2368 start of a (possibly prefixed) mnemonic. */
252b5132 2369
29b0f896
AM		 2370 line = parse_insn (line, mnemonic);
2371 if (line == NULL)
2372 return;
252b5132 2373
29b0f896
AM		 2374 line = parse_operands (line, mnemonic);
2375 if (line == NULL)
2376 return;
252b5132 2377
29b0f896
AM		 2378 /* Now we've parsed the mnemonic into a set of templates, and have the
2379 operands at hand. */
2380
2381 /* All intel opcodes have reversed operands except for "bound" and
2382 "enter". We also don't reverse intersegment "jmp" and "call"
2383 instructions with 2 immediate operands so that the immediate segment
050dfa73 2384 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2385 if (intel_syntax
2386 && i.operands > 1
29b0f896 2387 && (strcmp (mnemonic, "bound") != 0)
30123838 2388 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2389 && !(operand_type_check (i.types[0], imm)
2390 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2391 swap_operands ();
2392
ec56d5c0
JB		 2393 /* The order of the immediates should be reversed
2394 for 2 immediates extrq and insertq instructions */
2395 if (i.imm_operands == 2
2396 && (strcmp (mnemonic, "extrq") == 0
2397 || strcmp (mnemonic, "insertq") == 0))
2398 swap_2_operands (0, 1);
2399
29b0f896
AM		 2400 if (i.imm_operands)
2401 optimize_imm ();
2402
b300c311
L		 2403 /* Don't optimize displacement for movabs since it only takes 64bit
2404 displacement. */
2405 if (i.disp_operands
2406 && (flag_code != CODE_64BIT
2407 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2408 optimize_disp ();
2409
2410 /* Next, we find a template that matches the given insn,
2411 making sure the overlap of the given operands types is consistent
2412 with the template operand types. */
252b5132 2413
29b0f896
AM		 2414 if (!match_template ())
2415 return;
252b5132 2416
321fd21e
L		 2417 /* Zap movzx and movsx suffix. The suffix has been set from
2418 "word ptr" or "byte ptr" on the source operand in Intel syntax
2419 or extracted from mnemonic in AT&T syntax. But we'll use
2420 the destination register to choose the suffix for encoding. */
2421 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2422 {
321fd21e
L		 2423 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2424 there is no suffix, the default will be byte extension. */
2425 if (i.reg_operands != 2
2426 && !i.suffix
2427 && intel_syntax)
2428 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2429
2430 i.suffix = 0;
cd61ebfe 2431 }
24eab124 2432
40fb9820 2433 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2434 if (!add_prefix (FWAIT_OPCODE))
2435 return;
252b5132 2436
29b0f896 2437 /* Check string instruction segment overrides. */
40fb9820 2438 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2439 {
2440 if (!check_string ())
5dd0794d 2441 return;
29b0f896 2442 }
5dd0794d 2443
29b0f896
AM		 2444 if (!process_suffix ())
2445 return;
e413e4e9 2446
29b0f896
AM		 2447 /* Make still unresolved immediate matches conform to size of immediate
2448 given in i.suffix. */
2449 if (!finalize_imm ())
2450 return;
252b5132 2451
40fb9820 2452 if (i.types[0].bitfield.imm1)
29b0f896 2453 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2454
40fb9820 2455 for (j = 0; j < 3; j++)
c6fb90c8
L		 2456 if (i.types[j].bitfield.inoutportreg
2457 || i.types[j].bitfield.shiftcount
2458 || i.types[j].bitfield.acc
2459 || i.types[j].bitfield.floatacc)
40fb9820
L		 2460 i.reg_operands--;
2461
2462 if (i.tm.opcode_modifier.immext)
29b0f896 2463 {
02fc3089
L		 2464 expressionS *exp;
2465
40fb9820 2466 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2467 {
b7d9ef37 2468 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2469 operands with an opcode suffix which is coded in the same
2470 place as an 8-bit immediate field would be. Here we check
2471 those operands and remove them afterwards. */
2472 unsigned int x;
2473
a4622f40 2474 for (x = 0; x < i.operands; x++)
ca164297 2475 if (i.op[x].regs->reg_num != x)
a540244d
L		 2476 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2477 register_prefix,
2478 i.op[x].regs->reg_name,
2479 x + 1,
2480 i.tm.name);
ca164297
L		 2481 i.operands = 0;
2482 }
2483
29b0f896
AM		 2484 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2485 opcode suffix which is coded in the same place as an 8-bit
2486 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2487 operand from the opcode suffix stored in tm.extension_opcode.
2488 SSE5 also uses this encoding, for some of its 3 argument
2489 instructions. */
252b5132 2490
85f10a01
MM		 2491 assert (i.imm_operands == 0
2492 && (i.operands <= 2
2493 || (i.tm.cpu_flags.bitfield.cpusse5
2494 && i.operands <= 3)));
252b5132 2495
29b0f896
AM		 2496 exp = &im_expressions[i.imm_operands++];
2497 i.op[i.operands].imms = exp;
c6fb90c8 2498 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2499 i.types[i.operands].bitfield.imm8 = 1;
2500 i.operands++;
29b0f896
AM		 2501 exp->X_op = O_constant;
2502 exp->X_add_number = i.tm.extension_opcode;
2503 i.tm.extension_opcode = None;
2504 }
252b5132 2505
29b0f896
AM		 2506 /* For insns with operands there are more diddles to do to the opcode. */
2507 if (i.operands)
2508 {
2509 if (!process_operands ())
2510 return;
2511 }
40fb9820 2512 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2513 {
2514 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2515 as_warn (_("translating to `%sp'"), i.tm.name);
2516 }
252b5132 2517
29b0f896
AM		 2518 /* Handle conversion of 'int $3' --> special int3 insn. */
2519 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2520 {
2521 i.tm.base_opcode = INT3_OPCODE;
2522 i.imm_operands = 0;
2523 }
252b5132 2524
40fb9820
L		 2525 if ((i.tm.opcode_modifier.jump
2526 || i.tm.opcode_modifier.jumpbyte
2527 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2528 && i.op[0].disps->X_op == O_constant)
2529 {
2530 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2531 the absolute address given by the constant. Since ix86 jumps and
2532 calls are pc relative, we need to generate a reloc. */
2533 i.op[0].disps->X_add_symbol = &abs_symbol;
2534 i.op[0].disps->X_op = O_symbol;
2535 }
252b5132 2536
40fb9820 2537 if (i.tm.opcode_modifier.rex64)
161a04f6 2538 i.rex |= REX_W;
252b5132 2539
29b0f896
AM		 2540 /* For 8 bit registers we need an empty rex prefix. Also if the
2541 instruction already has a prefix, we need to convert old
2542 registers to new ones. */
773f551c 2543
40fb9820 2544 if ((i.types[0].bitfield.reg8
29b0f896 2545 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2546 || (i.types[1].bitfield.reg8
29b0f896 2547 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2548 || ((i.types[0].bitfield.reg8
2549 || i.types[1].bitfield.reg8)
29b0f896
AM		 2550 && i.rex != 0))
2551 {
2552 int x;
726c5dcd 2553
29b0f896
AM		 2554 i.rex |= REX_OPCODE;
2555 for (x = 0; x < 2; x++)
2556 {
2557 /* Look for 8 bit operand that uses old registers. */
40fb9820 2558 if (i.types[x].bitfield.reg8
29b0f896 2559 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2560 {
29b0f896
AM		 2561 /* In case it is "hi" register, give up. */
2562 if (i.op[x].regs->reg_num > 3)
a540244d 2563 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2564 "instruction requiring REX prefix."),
a540244d 2565 register_prefix, i.op[x].regs->reg_name);
773f551c 2566
29b0f896
AM		 2567 /* Otherwise it is equivalent to the extended register.
2568 Since the encoding doesn't change this is merely
2569 cosmetic cleanup for debug output. */
2570
2571 i.op[x].regs = i.op[x].regs + 8;
773f551c 2572 }
29b0f896
AM		 2573 }
2574 }
773f551c 2575
85f10a01
MM		 2576 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2577 REX prefix. */
2578 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2579 {
2580 i.drex.rex = i.rex;
2581 i.rex = 0;
2582 }
2583 else if (i.rex != 0)
29b0f896
AM		 2584 add_prefix (REX_OPCODE | i.rex);
2585
2586 /* We are ready to output the insn. */
2587 output_insn ();
2588}
2589
2590static char *
e3bb37b5 2591parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2592{
2593 char *l = line;
2594 char *token_start = l;
2595 char *mnem_p;
5c6af06e
JB		 2596 int supported;
2597 const template *t;
29b0f896
AM		 2598
2599 /* Non-zero if we found a prefix only acceptable with string insns. */
2600 const char *expecting_string_instruction = NULL;
45288df1 2601
29b0f896
AM		 2602 while (1)
2603 {
2604 mnem_p = mnemonic;
2605 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2606 {
2607 mnem_p++;
2608 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2609 {
29b0f896
AM		 2610 as_bad (_("no such instruction: `%s'"), token_start);
2611 return NULL;
2612 }
2613 l++;
2614 }
2615 if (!is_space_char (*l)
2616 && *l != END_OF_INSN
e44823cf
JB		 2617 && (intel_syntax
2618 || (*l != PREFIX_SEPARATOR
2619 && *l != ',')))
29b0f896
AM		 2620 {
2621 as_bad (_("invalid character %s in mnemonic"),
2622 output_invalid (*l));
2623 return NULL;
2624 }
2625 if (token_start == l)
2626 {
e44823cf 2627 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2628 as_bad (_("expecting prefix; got nothing"));
2629 else
2630 as_bad (_("expecting mnemonic; got nothing"));
2631 return NULL;
2632 }
45288df1 2633
29b0f896
AM		 2634 /* Look up instruction (or prefix) via hash table. */
2635 current_templates = hash_find (op_hash, mnemonic);
47926f60 2636
29b0f896
AM		 2637 if (*l != END_OF_INSN
2638 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2639 && current_templates
40fb9820 2640 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2641 {
c6fb90c8 2642 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2643 {
2644 as_bad ((flag_code != CODE_64BIT
2645 ? _("`%s' is only supported in 64-bit mode")
2646 : _("`%s' is not supported in 64-bit mode")),
2647 current_templates->start->name);
2648 return NULL;
2649 }
29b0f896
AM		 2650 /* If we are in 16-bit mode, do not allow addr16 or data16.
2651 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2652 if ((current_templates->start->opcode_modifier.size16
2653 || current_templates->start->opcode_modifier.size32)
29b0f896 2654 && flag_code != CODE_64BIT
40fb9820 2655 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2656 ^ (flag_code == CODE_16BIT)))
2657 {
2658 as_bad (_("redundant %s prefix"),
2659 current_templates->start->name);
2660 return NULL;
45288df1 2661 }
29b0f896
AM		 2662 /* Add prefix, checking for repeated prefixes. */
2663 switch (add_prefix (current_templates->start->base_opcode))
2664 {
2665 case 0:
2666 return NULL;
2667 case 2:
2668 expecting_string_instruction = current_templates->start->name;
2669 break;
2670 }
2671 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2672 token_start = ++l;
2673 }
2674 else
2675 break;
2676 }
45288df1 2677
29b0f896
AM		 2678 if (!current_templates)
2679 {
2680 /* See if we can get a match by trimming off a suffix. */
2681 switch (mnem_p[-1])
2682 {
2683 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2684 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2685 i.suffix = SHORT_MNEM_SUFFIX;
2686 else
29b0f896
AM		 2687 case BYTE_MNEM_SUFFIX:
2688 case QWORD_MNEM_SUFFIX:
2689 i.suffix = mnem_p[-1];
2690 mnem_p[-1] = '\0';
2691 current_templates = hash_find (op_hash, mnemonic);
2692 break;
2693 case SHORT_MNEM_SUFFIX:
2694 case LONG_MNEM_SUFFIX:
2695 if (!intel_syntax)
2696 {
2697 i.suffix = mnem_p[-1];
2698 mnem_p[-1] = '\0';
2699 current_templates = hash_find (op_hash, mnemonic);
2700 }
2701 break;
252b5132 2702
29b0f896
AM		 2703 /* Intel Syntax. */
2704 case 'd':
2705 if (intel_syntax)
2706 {
9306ca4a 2707 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2708 i.suffix = SHORT_MNEM_SUFFIX;
2709 else
2710 i.suffix = LONG_MNEM_SUFFIX;
2711 mnem_p[-1] = '\0';
2712 current_templates = hash_find (op_hash, mnemonic);
2713 }
2714 break;
2715 }
2716 if (!current_templates)
2717 {
2718 as_bad (_("no such instruction: `%s'"), token_start);
2719 return NULL;
2720 }
2721 }
252b5132 2722
40fb9820
L		 2723 if (current_templates->start->opcode_modifier.jump
2724 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2725 {
2726 /* Check for a branch hint. We allow ",pt" and ",pn" for
2727 predict taken and predict not taken respectively.
2728 I'm not sure that branch hints actually do anything on loop
2729 and jcxz insns (JumpByte) for current Pentium4 chips. They
2730 may work in the future and it doesn't hurt to accept them
2731 now. */
2732 if (l[0] == ',' && l[1] == 'p')
2733 {
2734 if (l[2] == 't')
2735 {
2736 if (!add_prefix (DS_PREFIX_OPCODE))
2737 return NULL;
2738 l += 3;
2739 }
2740 else if (l[2] == 'n')
2741 {
2742 if (!add_prefix (CS_PREFIX_OPCODE))
2743 return NULL;
2744 l += 3;
2745 }
2746 }
2747 }
2748 /* Any other comma loses. */
2749 if (*l == ',')
2750 {
2751 as_bad (_("invalid character %s in mnemonic"),
2752 output_invalid (*l));
2753 return NULL;
2754 }
252b5132 2755
29b0f896 2756 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2757 supported = 0;
2758 for (t = current_templates->start; t < current_templates->end; ++t)
2759 {
3629bb00
L		 2760 supported |= cpu_flags_match (t->cpu_flags);
2761 if (supported == 3)
2762 goto skip;
5c6af06e 2763 }
3629bb00 2764
5c6af06e
JB		 2765 if (!(supported & 2))
2766 {
2767 as_bad (flag_code == CODE_64BIT
2768 ? _("`%s' is not supported in 64-bit mode")
2769 : _("`%s' is only supported in 64-bit mode"),
2770 current_templates->start->name);
2771 return NULL;
2772 }
2773 if (!(supported & 1))
29b0f896 2774 {
3629bb00
L		 2775 as_bad (_("`%s' is not supported on `%s%s'"),
2776 current_templates->start->name, cpu_arch_name,
2777 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2778 return NULL;
29b0f896 2779 }
3629bb00
L		 2780
2781skip:
2782 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 2783 && (flag_code != CODE_16BIT))
29b0f896
AM		 2784 {
2785 as_warn (_("use .code16 to ensure correct addressing mode"));
2786 }
252b5132 2787
29b0f896 2788 /* Check for rep/repne without a string instruction. */
f41bbced 2789 if (expecting_string_instruction)
29b0f896 2790 {
f41bbced
JB		 2791 static templates override;
2792
2793 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2794 if (t->opcode_modifier.isstring)
f41bbced
JB		 2795 break;
2796 if (t >= current_templates->end)
2797 {
2798 as_bad (_("expecting string instruction after `%s'"),
64e74474 2799 expecting_string_instruction);
f41bbced
JB		 2800 return NULL;
2801 }
2802 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2803 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2804 break;
2805 override.end = t;
2806 current_templates = &override;
29b0f896 2807 }
252b5132 2808
29b0f896
AM		 2809 return l;
2810}
252b5132 2811
29b0f896 2812static char *
e3bb37b5 2813parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2814{
2815 char *token_start;
3138f287 2816
29b0f896
AM		 2817 /* 1 if operand is pending after ','. */
2818 unsigned int expecting_operand = 0;
252b5132 2819
29b0f896
AM		 2820 /* Non-zero if operand parens not balanced. */
2821 unsigned int paren_not_balanced;
2822
2823 while (*l != END_OF_INSN)
2824 {
2825 /* Skip optional white space before operand. */
2826 if (is_space_char (*l))
2827 ++l;
2828 if (!is_operand_char (*l) && *l != END_OF_INSN)
2829 {
2830 as_bad (_("invalid character %s before operand %d"),
2831 output_invalid (*l),
2832 i.operands + 1);
2833 return NULL;
2834 }
2835 token_start = l; /* after white space */
2836 paren_not_balanced = 0;
2837 while (paren_not_balanced || *l != ',')
2838 {
2839 if (*l == END_OF_INSN)
2840 {
2841 if (paren_not_balanced)
2842 {
2843 if (!intel_syntax)
2844 as_bad (_("unbalanced parenthesis in operand %d."),
2845 i.operands + 1);
2846 else
2847 as_bad (_("unbalanced brackets in operand %d."),
2848 i.operands + 1);
2849 return NULL;
2850 }
2851 else
2852 break; /* we are done */
2853 }
2854 else if (!is_operand_char (*l) && !is_space_char (*l))
2855 {
2856 as_bad (_("invalid character %s in operand %d"),
2857 output_invalid (*l),
2858 i.operands + 1);
2859 return NULL;
2860 }
2861 if (!intel_syntax)
2862 {
2863 if (*l == '(')
2864 ++paren_not_balanced;
2865 if (*l == ')')
2866 --paren_not_balanced;
2867 }
2868 else
2869 {
2870 if (*l == '[')
2871 ++paren_not_balanced;
2872 if (*l == ']')
2873 --paren_not_balanced;
2874 }
2875 l++;
2876 }
2877 if (l != token_start)
2878 { /* Yes, we've read in another operand. */
2879 unsigned int operand_ok;
2880 this_operand = i.operands++;
7d5e4556 2881 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 2882 if (i.operands > MAX_OPERANDS)
2883 {
2884 as_bad (_("spurious operands; (%d operands/instruction max)"),
2885 MAX_OPERANDS);
2886 return NULL;
2887 }
2888 /* Now parse operand adding info to 'i' as we go along. */
2889 END_STRING_AND_SAVE (l);
2890
2891 if (intel_syntax)
2892 operand_ok =
2893 i386_intel_operand (token_start,
2894 intel_float_operand (mnemonic));
2895 else
a7619375 2896 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 2897
2898 RESTORE_END_STRING (l);
2899 if (!operand_ok)
2900 return NULL;
2901 }
2902 else
2903 {
2904 if (expecting_operand)
2905 {
2906 expecting_operand_after_comma:
2907 as_bad (_("expecting operand after ','; got nothing"));
2908 return NULL;
2909 }
2910 if (*l == ',')
2911 {
2912 as_bad (_("expecting operand before ','; got nothing"));
2913 return NULL;
2914 }
2915 }
7f3f1ea2 2916
29b0f896
AM		 2917 /* Now *l must be either ',' or END_OF_INSN. */
2918 if (*l == ',')
2919 {
2920 if (*++l == END_OF_INSN)
2921 {
2922 /* Just skip it, if it's \n complain. */
2923 goto expecting_operand_after_comma;
2924 }
2925 expecting_operand = 1;
2926 }
2927 }
2928 return l;
2929}
7f3f1ea2 2930
050dfa73 2931static void
4d456e3d 2932swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2933{
2934 union i386_op temp_op;
40fb9820 2935 i386_operand_type temp_type;
050dfa73 2936 enum bfd_reloc_code_real temp_reloc;
4eed87de 2937
050dfa73
MM		 2938 temp_type = i.types[xchg2];
2939 i.types[xchg2] = i.types[xchg1];
2940 i.types[xchg1] = temp_type;
2941 temp_op = i.op[xchg2];
2942 i.op[xchg2] = i.op[xchg1];
2943 i.op[xchg1] = temp_op;
2944 temp_reloc = i.reloc[xchg2];
2945 i.reloc[xchg2] = i.reloc[xchg1];
2946 i.reloc[xchg1] = temp_reloc;
2947}
2948
29b0f896 2949static void
e3bb37b5 2950swap_operands (void)
29b0f896 2951{
b7c61d9a 2952 switch (i.operands)
050dfa73 2953 {
b7c61d9a 2954 case 4:
4d456e3d 2955 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2956 case 3:
2957 case 2:
4d456e3d 2958 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2959 break;
2960 default:
2961 abort ();
29b0f896 2962 }
29b0f896
AM		 2963
2964 if (i.mem_operands == 2)
2965 {
2966 const seg_entry *temp_seg;
2967 temp_seg = i.seg[0];
2968 i.seg[0] = i.seg[1];
2969 i.seg[1] = temp_seg;
2970 }
2971}
252b5132 2972
29b0f896
AM		 2973/* Try to ensure constant immediates are represented in the smallest
2974 opcode possible. */
2975static void
e3bb37b5 2976optimize_imm (void)
29b0f896
AM		 2977{
2978 char guess_suffix = 0;
2979 int op;
252b5132 2980
29b0f896
AM		 2981 if (i.suffix)
2982 guess_suffix = i.suffix;
2983 else if (i.reg_operands)
2984 {
2985 /* Figure out a suffix from the last register operand specified.
2986 We can't do this properly yet, ie. excluding InOutPortReg,
2987 but the following works for instructions with immediates.
2988 In any case, we can't set i.suffix yet. */
2989 for (op = i.operands; --op >= 0;)
40fb9820
L		 2990 if (i.types[op].bitfield.reg8)
2991 {
2992 guess_suffix = BYTE_MNEM_SUFFIX;
2993 break;
2994 }
2995 else if (i.types[op].bitfield.reg16)
252b5132 2996 {
40fb9820
L		 2997 guess_suffix = WORD_MNEM_SUFFIX;
2998 break;
2999 }
3000 else if (i.types[op].bitfield.reg32)
3001 {
3002 guess_suffix = LONG_MNEM_SUFFIX;
3003 break;
3004 }
3005 else if (i.types[op].bitfield.reg64)
3006 {
3007 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3008 break;
252b5132 3009 }
29b0f896
AM		 3010 }
3011 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3012 guess_suffix = WORD_MNEM_SUFFIX;
3013
3014 for (op = i.operands; --op >= 0;)
40fb9820 3015 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3016 {
3017 switch (i.op[op].imms->X_op)
252b5132 3018 {
29b0f896
AM		 3019 case O_constant:
3020 /* If a suffix is given, this operand may be shortened. */
3021 switch (guess_suffix)
252b5132 3022 {
29b0f896 3023 case LONG_MNEM_SUFFIX:
40fb9820
L		 3024 i.types[op].bitfield.imm32 = 1;
3025 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3026 break;
3027 case WORD_MNEM_SUFFIX:
40fb9820
L		 3028 i.types[op].bitfield.imm16 = 1;
3029 i.types[op].bitfield.imm32 = 1;
3030 i.types[op].bitfield.imm32s = 1;
3031 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3032 break;
3033 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3034 i.types[op].bitfield.imm8 = 1;
3035 i.types[op].bitfield.imm8s = 1;
3036 i.types[op].bitfield.imm16 = 1;
3037 i.types[op].bitfield.imm32 = 1;
3038 i.types[op].bitfield.imm32s = 1;
3039 i.types[op].bitfield.imm64 = 1;
29b0f896 3040 break;
252b5132 3041 }
252b5132 3042
29b0f896
AM		 3043 /* If this operand is at most 16 bits, convert it
3044 to a signed 16 bit number before trying to see
3045 whether it will fit in an even smaller size.
3046 This allows a 16-bit operand such as $0xffe0 to
3047 be recognised as within Imm8S range. */
40fb9820 3048 if ((i.types[op].bitfield.imm16)
29b0f896 3049 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3050 {
29b0f896
AM		 3051 i.op[op].imms->X_add_number =
3052 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3053 }
40fb9820 3054 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3055 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3056 == 0))
3057 {
3058 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3059 ^ ((offsetT) 1 << 31))
3060 - ((offsetT) 1 << 31));
3061 }
40fb9820 3062 i.types[op]
c6fb90c8
L		 3063 = operand_type_or (i.types[op],
3064 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3065
29b0f896
AM		 3066 /* We must avoid matching of Imm32 templates when 64bit
3067 only immediate is available. */
3068 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3069 i.types[op].bitfield.imm32 = 0;
29b0f896 3070 break;
252b5132 3071
29b0f896
AM		 3072 case O_absent:
3073 case O_register:
3074 abort ();
3075
3076 /* Symbols and expressions. */
3077 default:
9cd96992
JB		 3078 /* Convert symbolic operand to proper sizes for matching, but don't
3079 prevent matching a set of insns that only supports sizes other
3080 than those matching the insn suffix. */
3081 {
40fb9820 3082 i386_operand_type mask, allowed;
9cd96992
JB		 3083 const template *t;
3084
c6fb90c8
L		 3085 UINTS_CLEAR (mask);
3086 UINTS_CLEAR (allowed);
40fb9820 3087
4eed87de
AM		 3088 for (t = current_templates->start;
3089 t < current_templates->end;
3090 ++t)
c6fb90c8
L		 3091 allowed = operand_type_or (allowed,
3092 t->operand_types[op]);
9cd96992
JB		 3093 switch (guess_suffix)
3094 {
3095 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3096 mask.bitfield.imm64 = 1;
3097 mask.bitfield.imm32s = 1;
9cd96992
JB		 3098 break;
3099 case LONG_MNEM_SUFFIX:
40fb9820 3100 mask.bitfield.imm32 = 1;
9cd96992
JB		 3101 break;
3102 case WORD_MNEM_SUFFIX:
40fb9820 3103 mask.bitfield.imm16 = 1;
9cd96992
JB		 3104 break;
3105 case BYTE_MNEM_SUFFIX:
40fb9820 3106 mask.bitfield.imm8 = 1;
9cd96992
JB		 3107 break;
3108 default:
9cd96992
JB		 3109 break;
3110 }
c6fb90c8
L		 3111 allowed = operand_type_and (mask, allowed);
3112 if (!UINTS_ALL_ZERO (allowed))
3113 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3114 }
29b0f896 3115 break;
252b5132 3116 }
29b0f896
AM		 3117 }
3118}
47926f60 3119
29b0f896
AM		 3120/* Try to use the smallest displacement type too. */
3121static void
e3bb37b5 3122optimize_disp (void)
29b0f896
AM		 3123{
3124 int op;
3e73aa7c 3125
29b0f896 3126 for (op = i.operands; --op >= 0;)
40fb9820 3127 if (operand_type_check (i.types[op], disp))
252b5132 3128 {
b300c311 3129 if (i.op[op].disps->X_op == O_constant)
252b5132 3130 {
b300c311 3131 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3132
40fb9820 3133 if (i.types[op].bitfield.disp16
b300c311
L		 3134 && (disp & ~(offsetT) 0xffff) == 0)
3135 {
3136 /* If this operand is at most 16 bits, convert
3137 to a signed 16 bit number and don't use 64bit
3138 displacement. */
3139 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3140 i.types[op].bitfield.disp64 = 0;
b300c311 3141 }
40fb9820 3142 if (i.types[op].bitfield.disp32
b300c311
L		 3143 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3144 {
3145 /* If this operand is at most 32 bits, convert
3146 to a signed 32 bit number and don't use 64bit
3147 displacement. */
3148 disp &= (((offsetT) 2 << 31) - 1);
3149 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3150 i.types[op].bitfield.disp64 = 0;
b300c311 3151 }
40fb9820 3152 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3153 {
40fb9820
L		 3154 i.types[op].bitfield.disp8 = 0;
3155 i.types[op].bitfield.disp16 = 0;
3156 i.types[op].bitfield.disp32 = 0;
3157 i.types[op].bitfield.disp32s = 0;
3158 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3159 i.op[op].disps = 0;
3160 i.disp_operands--;
3161 }
3162 else if (flag_code == CODE_64BIT)
3163 {
3164 if (fits_in_signed_long (disp))
28a9d8f5 3165 {
40fb9820
L		 3166 i.types[op].bitfield.disp64 = 0;
3167 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3168 }
b300c311 3169 if (fits_in_unsigned_long (disp))
40fb9820 3170 i.types[op].bitfield.disp32 = 1;
b300c311 3171 }
40fb9820
L		 3172 if ((i.types[op].bitfield.disp32
3173 || i.types[op].bitfield.disp32s
3174 || i.types[op].bitfield.disp16)
b300c311 3175 && fits_in_signed_byte (disp))
40fb9820 3176 i.types[op].bitfield.disp8 = 1;
252b5132 3177 }
67a4f2b7
AO		 3178 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3179 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3180 {
3181 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3182 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3183 i.types[op].bitfield.disp8 = 0;
3184 i.types[op].bitfield.disp16 = 0;
3185 i.types[op].bitfield.disp32 = 0;
3186 i.types[op].bitfield.disp32s = 0;
3187 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3188 }
3189 else
b300c311 3190 /* We only support 64bit displacement on constants. */
40fb9820 3191 i.types[op].bitfield.disp64 = 0;
252b5132 3192 }
29b0f896
AM		 3193}
3194
3195static int
e3bb37b5 3196match_template (void)
29b0f896
AM		 3197{
3198 /* Points to template once we've found it. */
3199 const template *t;
40fb9820 3200 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 3201 unsigned int found_reverse_match;
40fb9820
L		 3202 i386_opcode_modifier suffix_check;
3203 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3204 int addr_prefix_disp;
a5c311ca 3205 unsigned int j;
3629bb00 3206 unsigned int found_cpu_match;
45664ddb 3207 unsigned int check_register;
29b0f896 3208
f48ff2ae
L		 3209#if MAX_OPERANDS != 4
3210# error "MAX_OPERANDS must be 4."
3211#endif
3212
29b0f896 3213 found_reverse_match = 0;
539e75ad 3214 addr_prefix_disp = -1;
40fb9820
L		 3215
3216 memset (&suffix_check, 0, sizeof (suffix_check));
3217 if (i.suffix == BYTE_MNEM_SUFFIX)
3218 suffix_check.no_bsuf = 1;
3219 else if (i.suffix == WORD_MNEM_SUFFIX)
3220 suffix_check.no_wsuf = 1;
3221 else if (i.suffix == SHORT_MNEM_SUFFIX)
3222 suffix_check.no_ssuf = 1;
3223 else if (i.suffix == LONG_MNEM_SUFFIX)
3224 suffix_check.no_lsuf = 1;
3225 else if (i.suffix == QWORD_MNEM_SUFFIX)
3226 suffix_check.no_qsuf = 1;
3227 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3228 suffix_check.no_ldsuf = 1;
29b0f896 3229
45aa61fe 3230 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3231 {
539e75ad
L		 3232 addr_prefix_disp = -1;
3233
29b0f896
AM		 3234 /* Must have right number of operands. */
3235 if (i.operands != t->operands)
3236 continue;
3237
50aecf8c
L		 3238 /* Check processor support. */
3239 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3240 if (!found_cpu_match)
3241 continue;
3242
e1d4d893
L		 3243 /* Check old gcc support. */
3244 if (!old_gcc && t->opcode_modifier.oldgcc)
3245 continue;
3246
3247 /* Check AT&T mnemonic. */
3248 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3249 continue;
3250
5c07affc
L		 3251 /* Check AT&T syntax Intel syntax. */
3252 if ((intel_syntax && t->opcode_modifier.attsyntax)
3253 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3254 continue;
3255
20592a94 3256 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3257 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3258 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3259 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3260 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3261 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3262 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3263 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3264 continue;
3265
5c07affc 3266 if (!operand_size_match (t))
7d5e4556 3267 continue;
539e75ad 3268
5c07affc
L		 3269 for (j = 0; j < MAX_OPERANDS; j++)
3270 operand_types[j] = t->operand_types[j];
3271
45aa61fe
AM		 3272 /* In general, don't allow 64-bit operands in 32-bit mode. */
3273 if (i.suffix == QWORD_MNEM_SUFFIX
3274 && flag_code != CODE_64BIT
3275 && (intel_syntax
40fb9820 3276 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3277 && !intel_float_operand (t->name))
3278 : intel_float_operand (t->name) != 2)
40fb9820
L		 3279 && ((!operand_types[0].bitfield.regmmx
3280 && !operand_types[0].bitfield.regxmm)
3281 || (!operand_types[t->operands > 1].bitfield.regmmx
3282 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3283 && (t->base_opcode != 0x0fc7
3284 || t->extension_opcode != 1 /* cmpxchg8b */))
3285 continue;
3286
29b0f896 3287 /* Do not verify operands when there are none. */
50aecf8c 3288 else
29b0f896 3289 {
c6fb90c8 3290 if (!t->operands)
2dbab7d5
L		 3291 /* We've found a match; break out of loop. */
3292 break;
29b0f896 3293 }
252b5132 3294
539e75ad
L		 3295 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3296 into Disp32/Disp16/Disp32 operand. */
3297 if (i.prefix[ADDR_PREFIX] != 0)
3298 {
40fb9820 3299 /* There should be only one Disp operand. */
539e75ad
L		 3300 switch (flag_code)
3301 {
3302 case CODE_16BIT:
40fb9820
L		 3303 for (j = 0; j < MAX_OPERANDS; j++)
3304 {
3305 if (operand_types[j].bitfield.disp16)
3306 {
3307 addr_prefix_disp = j;
3308 operand_types[j].bitfield.disp32 = 1;
3309 operand_types[j].bitfield.disp16 = 0;
3310 break;
3311 }
3312 }
539e75ad
L		 3313 break;
3314 case CODE_32BIT:
40fb9820
L		 3315 for (j = 0; j < MAX_OPERANDS; j++)
3316 {
3317 if (operand_types[j].bitfield.disp32)
3318 {
3319 addr_prefix_disp = j;
3320 operand_types[j].bitfield.disp32 = 0;
3321 operand_types[j].bitfield.disp16 = 1;
3322 break;
3323 }
3324 }
539e75ad
L		 3325 break;
3326 case CODE_64BIT:
40fb9820
L		 3327 for (j = 0; j < MAX_OPERANDS; j++)
3328 {
3329 if (operand_types[j].bitfield.disp64)
3330 {
3331 addr_prefix_disp = j;
3332 operand_types[j].bitfield.disp64 = 0;
3333 operand_types[j].bitfield.disp32 = 1;
3334 break;
3335 }
3336 }
539e75ad
L		 3337 break;
3338 }
539e75ad
L		 3339 }
3340
45664ddb
L		 3341 /* We check register size only if size of operands can be
3342 encoded the canonical way. */
3343 check_register = t->opcode_modifier.w;
c6fb90c8 3344 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3345 switch (t->operands)
3346 {
3347 case 1:
40fb9820 3348 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3349 continue;
3350 break;
3351 case 2:
8b38ad71
L		 3352 /* xchg %eax, %eax is a special case. It is an aliase for nop
3353 only in 32bit mode and we can use opcode 0x90. In 64bit
3354 mode, we can't use 0x90 for xchg %eax, %eax since it should
3355 zero-extend %eax to %rax. */
3356 if (flag_code == CODE_64BIT
3357 && t->base_opcode == 0x90
c6fb90c8
L		 3358 && UINTS_EQUAL (i.types [0], acc32)
3359 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3360 continue;
29b0f896 3361 case 3:
f48ff2ae 3362 case 4:
c6fb90c8 3363 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3364 if (!operand_type_match (overlap0, i.types[0])
3365 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3366 || (check_register
3367 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3368 operand_types[0],
3369 overlap1, i.types[1],
3370 operand_types[1])))
29b0f896
AM		 3371 {
3372 /* Check if other direction is valid ... */
40fb9820 3373 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3374 continue;
3375
3376 /* Try reversing direction of operands. */
c6fb90c8
L		 3377 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3378 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3379 if (!operand_type_match (overlap0, i.types[0])
3380 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3381 || (check_register
3382 && !operand_type_register_match (overlap0,
3383 i.types[0],
3384 operand_types[1],
3385 overlap1,
3386 i.types[1],
3387 operand_types[0])))
29b0f896
AM		 3388 {
3389 /* Does not match either direction. */
3390 continue;
3391 }
3392 /* found_reverse_match holds which of D or FloatDR
3393 we've found. */
40fb9820 3394 if (t->opcode_modifier.d)
8a2ed489 3395 found_reverse_match = Opcode_D;
40fb9820 3396 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3397 found_reverse_match = Opcode_FloatD;
3398 else
3399 found_reverse_match = 0;
40fb9820 3400 if (t->opcode_modifier.floatr)
8a2ed489 3401 found_reverse_match |= Opcode_FloatR;
29b0f896 3402 }
f48ff2ae 3403 else
29b0f896 3404 {
f48ff2ae 3405 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3406 switch (t->operands)
3407 {
3408 case 4:
c6fb90c8
L		 3409 overlap3 = operand_type_and (i.types[3],
3410 operand_types[3]);
d1cbb4db 3411 case 3:
c6fb90c8
L		 3412 overlap2 = operand_type_and (i.types[2],
3413 operand_types[2]);
d1cbb4db
L		 3414 break;
3415 }
29b0f896 3416
f48ff2ae
L		 3417 switch (t->operands)
3418 {
3419 case 4:
40fb9820 3420 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3421 || (check_register
3422 && !operand_type_register_match (overlap2,
3423 i.types[2],
3424 operand_types[2],
3425 overlap3,
3426 i.types[3],
3427 operand_types[3])))
f48ff2ae
L		 3428 continue;
3429 case 3:
3430 /* Here we make use of the fact that there are no
3431 reverse match 3 operand instructions, and all 3
3432 operand instructions only need to be checked for
3433 register consistency between operands 2 and 3. */
40fb9820 3434 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3435 || (check_register
3436 && !operand_type_register_match (overlap1,
3437 i.types[1],
3438 operand_types[1],
3439 overlap2,
3440 i.types[2],
3441 operand_types[2])))
f48ff2ae
L		 3442 continue;
3443 break;
3444 }
29b0f896 3445 }
f48ff2ae 3446 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3447 slip through to break. */
3448 }
3629bb00 3449 if (!found_cpu_match)
29b0f896
AM		 3450 {
3451 found_reverse_match = 0;
3452 continue;
3453 }
3454 /* We've found a match; break out of loop. */
3455 break;
3456 }
3457
3458 if (t == current_templates->end)
3459 {
3460 /* We found no match. */
3461 as_bad (_("suffix or operands invalid for `%s'"),
3462 current_templates->start->name);
3463 return 0;
3464 }
252b5132 3465
29b0f896
AM		 3466 if (!quiet_warnings)
3467 {
3468 if (!intel_syntax
40fb9820
L		 3469 && (i.types[0].bitfield.jumpabsolute
3470 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3471 {
3472 as_warn (_("indirect %s without `*'"), t->name);
3473 }
3474
40fb9820
L		 3475 if (t->opcode_modifier.isprefix
3476 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3477 {
3478 /* Warn them that a data or address size prefix doesn't
3479 affect assembly of the next line of code. */
3480 as_warn (_("stand-alone `%s' prefix"), t->name);
3481 }
3482 }
3483
3484 /* Copy the template we found. */
3485 i.tm = *t;
539e75ad
L		 3486
3487 if (addr_prefix_disp != -1)
3488 i.tm.operand_types[addr_prefix_disp]
3489 = operand_types[addr_prefix_disp];
3490
29b0f896
AM		 3491 if (found_reverse_match)
3492 {
3493 /* If we found a reverse match we must alter the opcode
3494 direction bit. found_reverse_match holds bits to change
3495 (different for int & float insns). */
3496
3497 i.tm.base_opcode ^= found_reverse_match;
3498
539e75ad
L		 3499 i.tm.operand_types[0] = operand_types[1];
3500 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3501 }
3502
3503 return 1;
3504}
3505
3506static int
e3bb37b5 3507check_string (void)
29b0f896 3508{
40fb9820
L		 3509 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3510 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3511 {
3512 if (i.seg[0] != NULL && i.seg[0] != &es)
3513 {
3514 as_bad (_("`%s' operand %d must use `%%es' segment"),
3515 i.tm.name,
3516 mem_op + 1);
3517 return 0;
3518 }
3519 /* There's only ever one segment override allowed per instruction.
3520 This instruction possibly has a legal segment override on the
3521 second operand, so copy the segment to where non-string
3522 instructions store it, allowing common code. */
3523 i.seg[0] = i.seg[1];
3524 }
40fb9820 3525 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3526 {
3527 if (i.seg[1] != NULL && i.seg[1] != &es)
3528 {
3529 as_bad (_("`%s' operand %d must use `%%es' segment"),
3530 i.tm.name,
3531 mem_op + 2);
3532 return 0;
3533 }
3534 }
3535 return 1;
3536}
3537
3538static int
543613e9 3539process_suffix (void)
29b0f896
AM		 3540{
3541 /* If matched instruction specifies an explicit instruction mnemonic
3542 suffix, use it. */
40fb9820
L		 3543 if (i.tm.opcode_modifier.size16)
3544 i.suffix = WORD_MNEM_SUFFIX;
3545 else if (i.tm.opcode_modifier.size32)
3546 i.suffix = LONG_MNEM_SUFFIX;
3547 else if (i.tm.opcode_modifier.size64)
3548 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3549 else if (i.reg_operands)
3550 {
3551 /* If there's no instruction mnemonic suffix we try to invent one
3552 based on register operands. */
3553 if (!i.suffix)
3554 {
3555 /* We take i.suffix from the last register operand specified,
3556 Destination register type is more significant than source
381d071f
L		 3557 register type. crc32 in SSE4.2 prefers source register
3558 type. */
3559 if (i.tm.base_opcode == 0xf20f38f1)
3560 {
40fb9820
L		 3561 if (i.types[0].bitfield.reg16)
3562 i.suffix = WORD_MNEM_SUFFIX;
3563 else if (i.types[0].bitfield.reg32)
3564 i.suffix = LONG_MNEM_SUFFIX;
3565 else if (i.types[0].bitfield.reg64)
3566 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3567 }
9344ff29 3568 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3569 {
40fb9820 3570 if (i.types[0].bitfield.reg8)
20592a94
L		 3571 i.suffix = BYTE_MNEM_SUFFIX;
3572 }
381d071f
L		 3573
3574 if (!i.suffix)
3575 {
3576 int op;
3577
20592a94
L		 3578 if (i.tm.base_opcode == 0xf20f38f1
3579 || i.tm.base_opcode == 0xf20f38f0)
3580 {
3581 /* We have to know the operand size for crc32. */
3582 as_bad (_("ambiguous memory operand size for `%s`"),
3583 i.tm.name);
3584 return 0;
3585 }
3586
381d071f 3587 for (op = i.operands; --op >= 0;)
40fb9820 3588 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3589 {
40fb9820
L		 3590 if (i.types[op].bitfield.reg8)
3591 {
3592 i.suffix = BYTE_MNEM_SUFFIX;
3593 break;
3594 }
3595 else if (i.types[op].bitfield.reg16)
3596 {
3597 i.suffix = WORD_MNEM_SUFFIX;
3598 break;
3599 }
3600 else if (i.types[op].bitfield.reg32)
3601 {
3602 i.suffix = LONG_MNEM_SUFFIX;
3603 break;
3604 }
3605 else if (i.types[op].bitfield.reg64)
3606 {
3607 i.suffix = QWORD_MNEM_SUFFIX;
3608 break;
3609 }
381d071f
L		 3610 }
3611 }
29b0f896
AM		 3612 }
3613 else if (i.suffix == BYTE_MNEM_SUFFIX)
3614 {
3615 if (!check_byte_reg ())
3616 return 0;
3617 }
3618 else if (i.suffix == LONG_MNEM_SUFFIX)
3619 {
3620 if (!check_long_reg ())
3621 return 0;
3622 }
3623 else if (i.suffix == QWORD_MNEM_SUFFIX)
3624 {
955e1e6a
L		 3625 if (intel_syntax
3626 && i.tm.opcode_modifier.ignoresize
3627 && i.tm.opcode_modifier.no_qsuf)
3628 i.suffix = 0;
3629 else if (!check_qword_reg ())
29b0f896
AM		 3630 return 0;
3631 }
3632 else if (i.suffix == WORD_MNEM_SUFFIX)
3633 {
3634 if (!check_word_reg ())
3635 return 0;
3636 }
582d5edd
L		 3637 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3638 {
3639 /* Skip if the instruction has x suffix. match_template
3640 should check if it is a valid suffix. */
3641 }
40fb9820 3642 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3643 /* Do nothing if the instruction is going to ignore the prefix. */
3644 ;
3645 else
3646 abort ();
3647 }
40fb9820 3648 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3649 && !i.suffix
3650 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3651 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3652 {
3653 i.suffix = stackop_size;
3654 }
9306ca4a
JB		 3655 else if (intel_syntax
3656 && !i.suffix
40fb9820
L		 3657 && (i.tm.operand_types[0].bitfield.jumpabsolute
3658 || i.tm.opcode_modifier.jumpbyte
3659 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3660 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3661 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3662 {
3663 switch (flag_code)
3664 {
3665 case CODE_64BIT:
40fb9820 3666 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3667 {
3668 i.suffix = QWORD_MNEM_SUFFIX;
3669 break;
3670 }
3671 case CODE_32BIT:
40fb9820 3672 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3673 i.suffix = LONG_MNEM_SUFFIX;
3674 break;
3675 case CODE_16BIT:
40fb9820 3676 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3677 i.suffix = WORD_MNEM_SUFFIX;
3678 break;
3679 }
3680 }
252b5132 3681
9306ca4a 3682 if (!i.suffix)
29b0f896 3683 {
9306ca4a
JB		 3684 if (!intel_syntax)
3685 {
40fb9820 3686 if (i.tm.opcode_modifier.w)
9306ca4a 3687 {
4eed87de
AM		 3688 as_bad (_("no instruction mnemonic suffix given and "
3689 "no register operands; can't size instruction"));
9306ca4a
JB		 3690 return 0;
3691 }
3692 }
3693 else
3694 {
40fb9820
L		 3695 unsigned int suffixes;
3696
3697 suffixes = !i.tm.opcode_modifier.no_bsuf;
3698 if (!i.tm.opcode_modifier.no_wsuf)
3699 suffixes |= 1 << 1;
3700 if (!i.tm.opcode_modifier.no_lsuf)
3701 suffixes |= 1 << 2;
fc4adea1 3702 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 3703 suffixes |= 1 << 3;
3704 if (!i.tm.opcode_modifier.no_ssuf)
3705 suffixes |= 1 << 4;
3706 if (!i.tm.opcode_modifier.no_qsuf)
3707 suffixes |= 1 << 5;
3708
3709 /* There are more than suffix matches. */
3710 if (i.tm.opcode_modifier.w
9306ca4a 3711 || ((suffixes & (suffixes - 1))
40fb9820
L		 3712 && !i.tm.opcode_modifier.defaultsize
3713 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3714 {
3715 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3716 return 0;
3717 }
3718 }
29b0f896 3719 }
252b5132 3720
9306ca4a
JB		 3721 /* Change the opcode based on the operand size given by i.suffix;
3722 We don't need to change things for byte insns. */
3723
582d5edd
L		 3724 if (i.suffix
3725 && i.suffix != BYTE_MNEM_SUFFIX
3726 && i.suffix != XMMWORD_MNEM_SUFFIX)
29b0f896
AM		 3727 {
3728 /* It's not a byte, select word/dword operation. */
40fb9820 3729 if (i.tm.opcode_modifier.w)
29b0f896 3730 {
40fb9820 3731 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3732 i.tm.base_opcode |= 8;
3733 else
3734 i.tm.base_opcode |= 1;
3735 }
0f3f3d8b 3736
29b0f896
AM		 3737 /* Now select between word & dword operations via the operand
3738 size prefix, except for instructions that will ignore this
3739 prefix anyway. */
ca61edf2 3740 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3741 {
ca61edf2
L		 3742 /* The address size override prefix changes the size of the
3743 first operand. */
40fb9820
L		 3744 if ((flag_code == CODE_32BIT
3745 && i.op->regs[0].reg_type.bitfield.reg16)
3746 || (flag_code != CODE_32BIT
3747 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3748 if (!add_prefix (ADDR_PREFIX_OPCODE))
3749 return 0;
3750 }
3751 else if (i.suffix != QWORD_MNEM_SUFFIX
3752 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3753 && !i.tm.opcode_modifier.ignoresize
3754 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3755 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3756 || (flag_code == CODE_64BIT
40fb9820 3757 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3758 {
3759 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3760
40fb9820 3761 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3762 prefix = ADDR_PREFIX_OPCODE;
252b5132 3763
29b0f896
AM		 3764 if (!add_prefix (prefix))
3765 return 0;
24eab124 3766 }
252b5132 3767
29b0f896
AM		 3768 /* Set mode64 for an operand. */
3769 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3770 && flag_code == CODE_64BIT
40fb9820 3771 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3772 {
3773 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3774 need rex64. cmpxchg8b is also a special case. */
3775 if (! (i.operands == 2
3776 && i.tm.base_opcode == 0x90
3777 && i.tm.extension_opcode == None
c6fb90c8
L		 3778 && UINTS_EQUAL (i.types [0], acc64)
3779 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3780 && ! (i.operands == 1
3781 && i.tm.base_opcode == 0xfc7
3782 && i.tm.extension_opcode == 1
40fb9820
L		 3783 && !operand_type_check (i.types [0], reg)
3784 && operand_type_check (i.types [0], anymem)))
f6bee062 3785 i.rex |= REX_W;
46e883c5 3786 }
3e73aa7c 3787
29b0f896
AM		 3788 /* Size floating point instruction. */
3789 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3790 if (i.tm.opcode_modifier.floatmf)
543613e9 3791 i.tm.base_opcode ^= 4;
29b0f896 3792 }
7ecd2f8b 3793
29b0f896
AM		 3794 return 1;
3795}
3e73aa7c 3796
29b0f896 3797static int
543613e9 3798check_byte_reg (void)
29b0f896
AM		 3799{
3800 int op;
543613e9 3801
29b0f896
AM		 3802 for (op = i.operands; --op >= 0;)
3803 {
3804 /* If this is an eight bit register, it's OK. If it's the 16 or
3805 32 bit version of an eight bit register, we will just use the
3806 low portion, and that's OK too. */
40fb9820 3807 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3808 continue;
3809
ca61edf2
L		 3810 /* Don't generate this warning if not needed. */
3811 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3812 continue;
3813
9344ff29
L		 3814 /* crc32 doesn't generate this warning. */
3815 if (i.tm.base_opcode == 0xf20f38f0)
3816 continue;
3817
40fb9820
L		 3818 if ((i.types[op].bitfield.reg16
3819 || i.types[op].bitfield.reg32
3820 || i.types[op].bitfield.reg64)
3821 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3822 {
3823 /* Prohibit these changes in the 64bit mode, since the
3824 lowering is more complicated. */
3825 if (flag_code == CODE_64BIT
40fb9820 3826 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3827 {
2ca3ace5
L		 3828 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3829 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3830 i.suffix);
3831 return 0;
3832 }
3833#if REGISTER_WARNINGS
3834 if (!quiet_warnings
40fb9820 3835 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3836 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3837 register_prefix,
40fb9820 3838 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3839 ? REGNAM_AL - REGNAM_AX
3840 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3841 register_prefix,
29b0f896
AM		 3842 i.op[op].regs->reg_name,
3843 i.suffix);
3844#endif
3845 continue;
3846 }
3847 /* Any other register is bad. */
40fb9820
L		 3848 if (i.types[op].bitfield.reg16
3849 || i.types[op].bitfield.reg32
3850 || i.types[op].bitfield.reg64
3851 || i.types[op].bitfield.regmmx
3852 || i.types[op].bitfield.regxmm
3853 || i.types[op].bitfield.sreg2
3854 || i.types[op].bitfield.sreg3
3855 || i.types[op].bitfield.control
3856 || i.types[op].bitfield.debug
3857 || i.types[op].bitfield.test
3858 || i.types[op].bitfield.floatreg
3859 || i.types[op].bitfield.floatacc)
29b0f896 3860 {
a540244d
L		 3861 as_bad (_("`%s%s' not allowed with `%s%c'"),
3862 register_prefix,
29b0f896
AM		 3863 i.op[op].regs->reg_name,
3864 i.tm.name,
3865 i.suffix);
3866 return 0;
3867 }
3868 }
3869 return 1;
3870}
3871
3872static int
e3bb37b5 3873check_long_reg (void)
29b0f896
AM		 3874{
3875 int op;
3876
3877 for (op = i.operands; --op >= 0;)
3878 /* Reject eight bit registers, except where the template requires
3879 them. (eg. movzb) */
40fb9820
L		 3880 if (i.types[op].bitfield.reg8
3881 && (i.tm.operand_types[op].bitfield.reg16
3882 || i.tm.operand_types[op].bitfield.reg32
3883 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3884 {
a540244d
L		 3885 as_bad (_("`%s%s' not allowed with `%s%c'"),
3886 register_prefix,
29b0f896
AM		 3887 i.op[op].regs->reg_name,
3888 i.tm.name,
3889 i.suffix);
3890 return 0;
3891 }
3892 /* Warn if the e prefix on a general reg is missing. */
3893 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3894 && i.types[op].bitfield.reg16
3895 && (i.tm.operand_types[op].bitfield.reg32
3896 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3897 {
3898 /* Prohibit these changes in the 64bit mode, since the
3899 lowering is more complicated. */
3900 if (flag_code == CODE_64BIT)
252b5132 3901 {
2ca3ace5
L		 3902 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3903 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3904 i.suffix);
3905 return 0;
252b5132 3906 }
29b0f896
AM		 3907#if REGISTER_WARNINGS
3908 else
a540244d
L		 3909 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3910 register_prefix,
29b0f896 3911 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3912 register_prefix,
29b0f896
AM		 3913 i.op[op].regs->reg_name,
3914 i.suffix);
3915#endif
252b5132 3916 }
29b0f896 3917 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3918 else if (i.types[op].bitfield.reg64
3919 && (i.tm.operand_types[op].bitfield.reg32
3920 || i.tm.operand_types[op].bitfield.acc))
252b5132 3921 {
34828aad 3922 if (intel_syntax
ca61edf2 3923 && i.tm.opcode_modifier.toqword
40fb9820 3924 && !i.types[0].bitfield.regxmm)
34828aad 3925 {
ca61edf2 3926 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3927 i.suffix = QWORD_MNEM_SUFFIX;
3928 }
3929 else
3930 {
3931 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3932 register_prefix, i.op[op].regs->reg_name,
3933 i.suffix);
3934 return 0;
3935 }
29b0f896
AM		 3936 }
3937 return 1;
3938}
252b5132 3939
29b0f896 3940static int
e3bb37b5 3941check_qword_reg (void)
29b0f896
AM		 3942{
3943 int op;
252b5132 3944
29b0f896
AM		 3945 for (op = i.operands; --op >= 0; )
3946 /* Reject eight bit registers, except where the template requires
3947 them. (eg. movzb) */
40fb9820
L		 3948 if (i.types[op].bitfield.reg8
3949 && (i.tm.operand_types[op].bitfield.reg16
3950 || i.tm.operand_types[op].bitfield.reg32
3951 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3952 {
a540244d
L		 3953 as_bad (_("`%s%s' not allowed with `%s%c'"),
3954 register_prefix,
29b0f896
AM		 3955 i.op[op].regs->reg_name,
3956 i.tm.name,
3957 i.suffix);
3958 return 0;
3959 }
3960 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3961 else if ((i.types[op].bitfield.reg16
3962 || i.types[op].bitfield.reg32)
3963 && (i.tm.operand_types[op].bitfield.reg32
3964 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3965 {
3966 /* Prohibit these changes in the 64bit mode, since the
3967 lowering is more complicated. */
34828aad 3968 if (intel_syntax
ca61edf2 3969 && i.tm.opcode_modifier.todword
40fb9820 3970 && !i.types[0].bitfield.regxmm)
34828aad 3971 {
ca61edf2 3972 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 3973 i.suffix = LONG_MNEM_SUFFIX;
3974 }
3975 else
3976 {
3977 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3978 register_prefix, i.op[op].regs->reg_name,
3979 i.suffix);
3980 return 0;
3981 }
252b5132 3982 }
29b0f896
AM		 3983 return 1;
3984}
252b5132 3985
29b0f896 3986static int
e3bb37b5 3987check_word_reg (void)
29b0f896
AM		 3988{
3989 int op;
3990 for (op = i.operands; --op >= 0;)
3991 /* Reject eight bit registers, except where the template requires
3992 them. (eg. movzb) */
40fb9820
L		 3993 if (i.types[op].bitfield.reg8
3994 && (i.tm.operand_types[op].bitfield.reg16
3995 || i.tm.operand_types[op].bitfield.reg32
3996 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3997 {
a540244d
L		 3998 as_bad (_("`%s%s' not allowed with `%s%c'"),
3999 register_prefix,
29b0f896
AM		 4000 i.op[op].regs->reg_name,
4001 i.tm.name,
4002 i.suffix);
4003 return 0;
4004 }
4005 /* Warn if the e prefix on a general reg is present. */
4006 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4007 && i.types[op].bitfield.reg32
4008 && (i.tm.operand_types[op].bitfield.reg16
4009 || i.tm.operand_types[op].bitfield.acc))
252b5132 4010 {
29b0f896
AM		 4011 /* Prohibit these changes in the 64bit mode, since the
4012 lowering is more complicated. */
4013 if (flag_code == CODE_64BIT)
252b5132 4014 {
2ca3ace5
L		 4015 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4016 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4017 i.suffix);
4018 return 0;
252b5132 4019 }
29b0f896
AM		 4020 else
4021#if REGISTER_WARNINGS
a540244d
L		 4022 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4023 register_prefix,
29b0f896 4024 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4025 register_prefix,
29b0f896
AM		 4026 i.op[op].regs->reg_name,
4027 i.suffix);
4028#endif
4029 }
4030 return 1;
4031}
252b5132 4032
29b0f896 4033static int
40fb9820 4034update_imm (unsigned int j)
29b0f896 4035{
40fb9820
L		 4036 i386_operand_type overlap;
4037
c6fb90c8 4038 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4039 if ((overlap.bitfield.imm8
4040 || overlap.bitfield.imm8s
4041 || overlap.bitfield.imm16
4042 || overlap.bitfield.imm32
4043 || overlap.bitfield.imm32s
4044 || overlap.bitfield.imm64)
c6fb90c8
L		 4045 && !UINTS_EQUAL (overlap, imm8)
4046 && !UINTS_EQUAL (overlap, imm8s)
4047 && !UINTS_EQUAL (overlap, imm16)
4048 && !UINTS_EQUAL (overlap, imm32)
4049 && !UINTS_EQUAL (overlap, imm32s)
4050 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 4051 {
4052 if (i.suffix)
4053 {
40fb9820
L		 4054 i386_operand_type temp;
4055
c6fb90c8 4056 UINTS_CLEAR (temp);
40fb9820
L		 4057 if (i.suffix == BYTE_MNEM_SUFFIX)
4058 {
4059 temp.bitfield.imm8 = overlap.bitfield.imm8;
4060 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4061 }
4062 else if (i.suffix == WORD_MNEM_SUFFIX)
4063 temp.bitfield.imm16 = overlap.bitfield.imm16;
4064 else if (i.suffix == QWORD_MNEM_SUFFIX)
4065 {
4066 temp.bitfield.imm64 = overlap.bitfield.imm64;
4067 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4068 }
4069 else
4070 temp.bitfield.imm32 = overlap.bitfield.imm32;
4071 overlap = temp;
29b0f896 4072 }
c6fb90c8
L		 4073 else if (UINTS_EQUAL (overlap, imm16_32_32s)
4074 || UINTS_EQUAL (overlap, imm16_32)
4075 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 4076 {
c6fb90c8 4077 UINTS_CLEAR (overlap);
40fb9820
L		 4078 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4079 overlap.bitfield.imm16 = 1;
4080 else
4081 overlap.bitfield.imm32s = 1;
29b0f896 4082 }
c6fb90c8
L		 4083 if (!UINTS_EQUAL (overlap, imm8)
4084 && !UINTS_EQUAL (overlap, imm8s)
4085 && !UINTS_EQUAL (overlap, imm16)
4086 && !UINTS_EQUAL (overlap, imm32)
4087 && !UINTS_EQUAL (overlap, imm32s)
4088 && !UINTS_EQUAL (overlap, imm64))
29b0f896 4089 {
4eed87de
AM		 4090 as_bad (_("no instruction mnemonic suffix given; "
4091 "can't determine immediate size"));
29b0f896
AM		 4092 return 0;
4093 }
4094 }
40fb9820 4095 i.types[j] = overlap;
29b0f896 4096
40fb9820
L		 4097 return 1;
4098}
4099
4100static int
4101finalize_imm (void)
4102{
4103 unsigned int j;
29b0f896 4104
40fb9820
L		 4105 for (j = 0; j < 2; j++)
4106 if (update_imm (j) == 0)
4107 return 0;
4108
c6fb90c8 4109 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4110 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4111
4112 return 1;
4113}
4114
85f10a01
MM		 4115static void
4116process_drex (void)
4117{
5dd15031
JJ		 4118 i.drex.modrm_reg = 0;
4119 i.drex.modrm_regmem = 0;
85f10a01
MM		 4120
4121 /* SSE5 4 operand instructions must have the destination the same as
4122 one of the inputs. Figure out the destination register and cache
4123 it away in the drex field, and remember which fields to use for
4124 the modrm byte. */
4125 if (i.tm.opcode_modifier.drex
4126 && i.tm.opcode_modifier.drexv
4127 && i.operands == 4)
4128 {
4129 i.tm.extension_opcode = None;
4130
4131 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4132 if (i.types[0].bitfield.regxmm != 0
4133 && i.types[1].bitfield.regxmm != 0
4134 && i.types[2].bitfield.regxmm != 0
4135 && i.types[3].bitfield.regxmm != 0
4136 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4137 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4138 {
4139 /* Clear the arguments that are stored in drex. */
4140 UINTS_CLEAR (i.types[0]);
4141 UINTS_CLEAR (i.types[3]);
4142 i.reg_operands -= 2;
4143
4144 /* There are two different ways to encode a 4 operand
4145 instruction with all registers that uses OC1 set to
4146 0 or 1. Favor setting OC1 to 0 since this mimics the
4147 actions of other SSE5 assemblers. Use modrm encoding 2
4148 for register/register. Include the high order bit that
4149 is normally stored in the REX byte in the register
4150 field. */
4151 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4152 i.drex.modrm_reg = 2;
4153 i.drex.modrm_regmem = 1;
4154 i.drex.reg = (i.op[3].regs->reg_num
4155 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4156 }
4157
4158 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4159 else if (i.types[0].bitfield.regxmm != 0
4160 && i.types[1].bitfield.regxmm != 0
4161 && (i.types[2].bitfield.regxmm
4162 || operand_type_check (i.types[2], anymem))
4163 && i.types[3].bitfield.regxmm != 0
4164 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4165 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4166 {
4167 /* clear the arguments that are stored in drex */
4168 UINTS_CLEAR (i.types[0]);
4169 UINTS_CLEAR (i.types[3]);
4170 i.reg_operands -= 2;
4171
4172 /* Specify the modrm encoding for memory addressing. Include
4173 the high order bit that is normally stored in the REX byte
4174 in the register field. */
4175 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4176 i.drex.modrm_reg = 1;
4177 i.drex.modrm_regmem = 2;
4178 i.drex.reg = (i.op[3].regs->reg_num
4179 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4180 }
4181
4182 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4183 else if (i.types[0].bitfield.regxmm != 0
4184 && operand_type_check (i.types[1], anymem) != 0
4185 && i.types[2].bitfield.regxmm != 0
4186 && i.types[3].bitfield.regxmm != 0
4187 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4188 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4189 {
4190 /* Clear the arguments that are stored in drex. */
4191 UINTS_CLEAR (i.types[0]);
4192 UINTS_CLEAR (i.types[3]);
4193 i.reg_operands -= 2;
4194
4195 /* Specify the modrm encoding for memory addressing. Include
4196 the high order bit that is normally stored in the REX byte
4197 in the register field. */
4198 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4199 i.drex.modrm_reg = 2;
4200 i.drex.modrm_regmem = 1;
4201 i.drex.reg = (i.op[3].regs->reg_num
4202 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4203 }
4204
4205 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4206 else if (i.types[0].bitfield.regxmm != 0
4207 && i.types[1].bitfield.regxmm != 0
4208 && i.types[2].bitfield.regxmm != 0
4209 && i.types[3].bitfield.regxmm != 0
4210 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4211 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4212 {
4213 /* clear the arguments that are stored in drex */
4214 UINTS_CLEAR (i.types[2]);
4215 UINTS_CLEAR (i.types[3]);
4216 i.reg_operands -= 2;
4217
4218 /* There are two different ways to encode a 4 operand
4219 instruction with all registers that uses OC1 set to
4220 0 or 1. Favor setting OC1 to 0 since this mimics the
4221 actions of other SSE5 assemblers. Use modrm encoding
4222 2 for register/register. Include the high order bit that
4223 is normally stored in the REX byte in the register
4224 field. */
4225 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4226 i.drex.modrm_reg = 1;
4227 i.drex.modrm_regmem = 0;
4228
4229 /* Remember the register, including the upper bits */
4230 i.drex.reg = (i.op[3].regs->reg_num
4231 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4232 }
4233
4234 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4235 else if (i.types[0].bitfield.regxmm != 0
4236 && (i.types[1].bitfield.regxmm
4237 || operand_type_check (i.types[1], anymem))
4238 && i.types[2].bitfield.regxmm != 0
4239 && i.types[3].bitfield.regxmm != 0
4240 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4241 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4242 {
4243 /* Clear the arguments that are stored in drex. */
4244 UINTS_CLEAR (i.types[2]);
4245 UINTS_CLEAR (i.types[3]);
4246 i.reg_operands -= 2;
4247
4248 /* Specify the modrm encoding and remember the register
4249 including the bits normally stored in the REX byte. */
4250 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4251 i.drex.modrm_reg = 0;
4252 i.drex.modrm_regmem = 1;
4253 i.drex.reg = (i.op[3].regs->reg_num
4254 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4255 }
4256
4257 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4258 else if (operand_type_check (i.types[0], anymem) != 0
4259 && i.types[1].bitfield.regxmm != 0
4260 && i.types[2].bitfield.regxmm != 0
4261 && i.types[3].bitfield.regxmm != 0
4262 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4263 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4264 {
4265 /* clear the arguments that are stored in drex */
4266 UINTS_CLEAR (i.types[2]);
4267 UINTS_CLEAR (i.types[3]);
4268 i.reg_operands -= 2;
4269
4270 /* Specify the modrm encoding and remember the register
4271 including the bits normally stored in the REX byte. */
4272 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4273 i.drex.modrm_reg = 1;
4274 i.drex.modrm_regmem = 0;
4275 i.drex.reg = (i.op[3].regs->reg_num
4276 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4277 }
4278
4279 else
4280 as_bad (_("Incorrect operands for the '%s' instruction"),
4281 i.tm.name);
4282 }
4283
4284 /* SSE5 instructions with the DREX byte where the only memory operand
4285 is in the 2nd argument, and the first and last xmm register must
4286 match, and is encoded in the DREX byte. */
4287 else if (i.tm.opcode_modifier.drex
4288 && !i.tm.opcode_modifier.drexv
4289 && i.operands == 4)
4290 {
4291 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4292 if (i.types[0].bitfield.regxmm != 0
4293 && (i.types[1].bitfield.regxmm
4294 || operand_type_check(i.types[1], anymem))
4295 && i.types[2].bitfield.regxmm != 0
4296 && i.types[3].bitfield.regxmm != 0
4297 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4298 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4299 {
4300 /* clear the arguments that are stored in drex */
4301 UINTS_CLEAR (i.types[0]);
4302 UINTS_CLEAR (i.types[3]);
4303 i.reg_operands -= 2;
4304
4305 /* Specify the modrm encoding and remember the register
4306 including the high bit normally stored in the REX
4307 byte. */
4308 i.drex.modrm_reg = 2;
4309 i.drex.modrm_regmem = 1;
4310 i.drex.reg = (i.op[3].regs->reg_num
4311 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4312 }
4313
4314 else
4315 as_bad (_("Incorrect operands for the '%s' instruction"),
4316 i.tm.name);
4317 }
4318
4319 /* SSE5 3 operand instructions that the result is a register, being
4320 either operand can be a memory operand, using OC0 to note which
4321 one is the memory. */
4322 else if (i.tm.opcode_modifier.drex
4323 && i.tm.opcode_modifier.drexv
4324 && i.operands == 3)
4325 {
4326 i.tm.extension_opcode = None;
4327
4328 /* Case 1: 3 operand insn, src1 = register. */
4329 if (i.types[0].bitfield.regxmm != 0
4330 && i.types[1].bitfield.regxmm != 0
4331 && i.types[2].bitfield.regxmm != 0)
4332 {
4333 /* Clear the arguments that are stored in drex. */
4334 UINTS_CLEAR (i.types[2]);
4335 i.reg_operands--;
4336
4337 /* Specify the modrm encoding and remember the register
4338 including the high bit normally stored in the REX byte. */
4339 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4340 i.drex.modrm_reg = 1;
4341 i.drex.modrm_regmem = 0;
4342 i.drex.reg = (i.op[2].regs->reg_num
4343 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4344 }
4345
4346 /* Case 2: 3 operand insn, src1 = memory. */
4347 else if (operand_type_check (i.types[0], anymem) != 0
4348 && i.types[1].bitfield.regxmm != 0
4349 && i.types[2].bitfield.regxmm != 0)
4350 {
4351 /* Clear the arguments that are stored in drex. */
4352 UINTS_CLEAR (i.types[2]);
4353 i.reg_operands--;
4354
4355 /* Specify the modrm encoding and remember the register
4356 including the high bit normally stored in the REX
4357 byte. */
4358 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4359 i.drex.modrm_reg = 1;
4360 i.drex.modrm_regmem = 0;
4361 i.drex.reg = (i.op[2].regs->reg_num
4362 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4363 }
4364
4365 /* Case 3: 3 operand insn, src2 = memory. */
4366 else if (i.types[0].bitfield.regxmm != 0
4367 && operand_type_check (i.types[1], anymem) != 0
4368 && i.types[2].bitfield.regxmm != 0)
4369 {
4370 /* Clear the arguments that are stored in drex. */
4371 UINTS_CLEAR (i.types[2]);
4372 i.reg_operands--;
4373
4374 /* Specify the modrm encoding and remember the register
4375 including the high bit normally stored in the REX byte. */
4376 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4377 i.drex.modrm_reg = 0;
4378 i.drex.modrm_regmem = 1;
4379 i.drex.reg = (i.op[2].regs->reg_num
4380 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4381 }
4382
4383 else
4384 as_bad (_("Incorrect operands for the '%s' instruction"),
4385 i.tm.name);
4386 }
4387
4388 /* SSE5 4 operand instructions that are the comparison instructions
4389 where the first operand is the immediate value of the comparison
4390 to be done. */
4391 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4392 {
4393 /* Case 1: 4 operand insn, src1 = reg/memory. */
4394 if (operand_type_check (i.types[0], imm) != 0
4395 && (i.types[1].bitfield.regxmm
4396 || operand_type_check (i.types[1], anymem))
4397 && i.types[2].bitfield.regxmm != 0
4398 && i.types[3].bitfield.regxmm != 0)
4399 {
4400 /* clear the arguments that are stored in drex */
4401 UINTS_CLEAR (i.types[3]);
4402 i.reg_operands--;
4403
4404 /* Specify the modrm encoding and remember the register
4405 including the high bit normally stored in the REX byte. */
4406 i.drex.modrm_reg = 2;
4407 i.drex.modrm_regmem = 1;
4408 i.drex.reg = (i.op[3].regs->reg_num
4409 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4410 }
4411
4412 /* Case 2: 3 operand insn with ImmExt that places the
4413 opcode_extension as an immediate argument. This is used for
4414 all of the varients of comparison that supplies the appropriate
4415 value as part of the instruction. */
4416 else if ((i.types[0].bitfield.regxmm
4417 || operand_type_check (i.types[0], anymem))
4418 && i.types[1].bitfield.regxmm != 0
4419 && i.types[2].bitfield.regxmm != 0
4420 && operand_type_check (i.types[3], imm) != 0)
4421 {
4422 /* clear the arguments that are stored in drex */
4423 UINTS_CLEAR (i.types[2]);
4424 i.reg_operands--;
4425
4426 /* Specify the modrm encoding and remember the register
4427 including the high bit normally stored in the REX byte. */
4428 i.drex.modrm_reg = 1;
4429 i.drex.modrm_regmem = 0;
4430 i.drex.reg = (i.op[2].regs->reg_num
4431 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4432 }
4433
4434 else
4435 as_bad (_("Incorrect operands for the '%s' instruction"),
4436 i.tm.name);
4437 }
4438
4439 else if (i.tm.opcode_modifier.drex
4440 || i.tm.opcode_modifier.drexv
4441 || i.tm.opcode_modifier.drexc)
4442 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4443}
4444
29b0f896 4445static int
e3bb37b5 4446process_operands (void)
29b0f896
AM		 4447{
4448 /* Default segment register this instruction will use for memory
4449 accesses. 0 means unknown. This is only for optimizing out
4450 unnecessary segment overrides. */
4451 const seg_entry *default_seg = 0;
4452
85f10a01
MM		 4453 /* Handle all of the DREX munging that SSE5 needs. */
4454 if (i.tm.opcode_modifier.drex
4455 || i.tm.opcode_modifier.drexv
4456 || i.tm.opcode_modifier.drexc)
4457 process_drex ();
4458
e2ec9d29 4459 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4460 {
9fcfb3d7
L		 4461 unsigned int j;
4462
e2ec9d29
L		 4463 /* The first operand is implicit and must be xmm0. */
4464 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4465 if (i.op[0].regs->reg_num != 0)
4466 {
4467 if (intel_syntax)
4468 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4469 i.tm.name, register_prefix);
4470 else
4471 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4472 i.tm.name, register_prefix);
4473 return 0;
4474 }
9fcfb3d7
L		 4475
4476 for (j = 1; j < i.operands; j++)
4477 {
4478 i.op[j - 1] = i.op[j];
4479 i.types[j - 1] = i.types[j];
4480
4481 /* We need to adjust fields in i.tm since they are used by
4482 build_modrm_byte. */
4483 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4484 }
4485
e2ec9d29
L		 4486 i.operands--;
4487 i.reg_operands--;
e2ec9d29
L		 4488 i.tm.operands--;
4489 }
4490 else if (i.tm.opcode_modifier.regkludge)
4491 {
4492 /* The imul $imm, %reg instruction is converted into
4493 imul $imm, %reg, %reg, and the clr %reg instruction
4494 is converted into xor %reg, %reg. */
4495
4496 unsigned int first_reg_op;
4497
4498 if (operand_type_check (i.types[0], reg))
4499 first_reg_op = 0;
4500 else
4501 first_reg_op = 1;
4502 /* Pretend we saw the extra register operand. */
4503 assert (i.reg_operands == 1
4504 && i.op[first_reg_op + 1].regs == 0);
4505 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4506 i.types[first_reg_op + 1] = i.types[first_reg_op];
4507 i.operands++;
4508 i.reg_operands++;
29b0f896
AM		 4509 }
4510
40fb9820 4511 if (i.tm.opcode_modifier.shortform)
29b0f896 4512 {
40fb9820
L		 4513 if (i.types[0].bitfield.sreg2
4514 || i.types[0].bitfield.sreg3)
29b0f896 4515 {
4eed87de
AM		 4516 if (i.tm.base_opcode == POP_SEG_SHORT
4517 && i.op[0].regs->reg_num == 1)
29b0f896 4518 {
4eed87de
AM		 4519 as_bad (_("you can't `pop %%cs'"));
4520 return 0;
29b0f896 4521 }
4eed87de
AM		 4522 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4523 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4524 i.rex |= REX_B;
4eed87de
AM		 4525 }
4526 else
4527 {
85f10a01
MM		 4528 /* The register or float register operand is in operand
4529 0 or 1. */
40fb9820
L		 4530 unsigned int op;
4531
4532 if (i.types[0].bitfield.floatreg
4533 || operand_type_check (i.types[0], reg))
4534 op = 0;
4535 else
4536 op = 1;
4eed87de
AM		 4537 /* Register goes in low 3 bits of opcode. */
4538 i.tm.base_opcode |= i.op[op].regs->reg_num;
4539 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4540 i.rex |= REX_B;
40fb9820 4541 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4542 {
4eed87de
AM		 4543 /* Warn about some common errors, but press on regardless.
4544 The first case can be generated by gcc (<= 2.8.1). */
4545 if (i.operands == 2)
4546 {
4547 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4548 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4549 register_prefix, i.op[1].regs->reg_name,
4550 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4551 }
4552 else
4553 {
4554 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4555 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4556 register_prefix, i.op[0].regs->reg_name);
4eed87de 4557 }
29b0f896
AM		 4558 }
4559 }
4560 }
40fb9820 4561 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4562 {
4563 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4564 must be put into the modrm byte). Now, we make the modrm and
4565 index base bytes based on all the info we've collected. */
29b0f896
AM		 4566
4567 default_seg = build_modrm_byte ();
4568 }
8a2ed489 4569 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4570 {
4571 default_seg = &ds;
4572 }
40fb9820 4573 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4574 {
4575 /* For the string instructions that allow a segment override
4576 on one of their operands, the default segment is ds. */
4577 default_seg = &ds;
4578 }
4579
75178d9d
L		 4580 if (i.tm.base_opcode == 0x8d /* lea */
4581 && i.seg[0]
4582 && !quiet_warnings)
30123838 4583 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4584
4585 /* If a segment was explicitly specified, and the specified segment
4586 is not the default, use an opcode prefix to select it. If we
4587 never figured out what the default segment is, then default_seg
4588 will be zero at this point, and the specified segment prefix will
4589 always be used. */
29b0f896
AM		 4590 if ((i.seg[0]) && (i.seg[0] != default_seg))
4591 {
4592 if (!add_prefix (i.seg[0]->seg_prefix))
4593 return 0;
4594 }
4595 return 1;
4596}
4597
4598static const seg_entry *
e3bb37b5 4599build_modrm_byte (void)
29b0f896
AM		 4600{
4601 const seg_entry *default_seg = 0;
4602
85f10a01
MM		 4603 /* SSE5 4 operand instructions are encoded in such a way that one of
4604 the inputs must match the destination register. Process_drex hides
4605 the 3rd argument in the drex field, so that by the time we get
4606 here, it looks to GAS as if this is a 2 operand instruction. */
4607 if ((i.tm.opcode_modifier.drex
4608 || i.tm.opcode_modifier.drexv
b5016f89 4609 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4610 && i.reg_operands == 2)
4611 {
4612 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4613 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4614
4615 i.rm.reg = reg->reg_num;
4616 i.rm.regmem = regmem->reg_num;
4617 i.rm.mode = 3;
4618 if ((reg->reg_flags & RegRex) != 0)
4619 i.rex |= REX_R;
4620 if ((regmem->reg_flags & RegRex) != 0)
4621 i.rex |= REX_B;
4622 }
4623
29b0f896
AM		 4624 /* i.reg_operands MUST be the number of real register operands;
4625 implicit registers do not count. */
85f10a01 4626 else if (i.reg_operands == 2)
29b0f896
AM		 4627 {
4628 unsigned int source, dest;
cab737b9
L		 4629
4630 switch (i.operands)
4631 {
4632 case 2:
4633 source = 0;
4634 break;
4635 case 3:
c81128dc
L		 4636 /* When there are 3 operands, one of them may be immediate,
4637 which may be the first or the last operand. Otherwise,
4638 the first operand must be shift count register (cl). */
4639 assert (i.imm_operands == 1
4640 || (i.imm_operands == 0
40fb9820
L		 4641 && i.types[0].bitfield.shiftcount));
4642 if (operand_type_check (i.types[0], imm)
4643 || i.types[0].bitfield.shiftcount)
4644 source = 1;
4645 else
4646 source = 0;
cab737b9
L		 4647 break;
4648 case 4:
368d64cc
L		 4649 /* When there are 4 operands, the first two must be 8bit
4650 immediate operands. The source operand will be the 3rd
4651 one. */
cab737b9 4652 assert (i.imm_operands == 2
368d64cc
L		 4653 && i.types[0].bitfield.imm8
4654 && i.types[1].bitfield.imm8);
cab737b9
L		 4655 source = 2;
4656 break;
4657 default:
4658 abort ();
4659 }
4660
29b0f896
AM		 4661 dest = source + 1;
4662
4663 i.rm.mode = 3;
4664 /* One of the register operands will be encoded in the i.tm.reg
4665 field, the other in the combined i.tm.mode and i.tm.regmem
4666 fields. If no form of this instruction supports a memory
4667 destination operand, then we assume the source operand may
4668 sometimes be a memory operand and so we need to store the
4669 destination in the i.rm.reg field. */
40fb9820
L		 4670 if (!i.tm.operand_types[dest].bitfield.regmem
4671 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4672 {
4673 i.rm.reg = i.op[dest].regs->reg_num;
4674 i.rm.regmem = i.op[source].regs->reg_num;
4675 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4676 i.rex |= REX_R;
29b0f896 4677 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4678 i.rex |= REX_B;
29b0f896
AM		 4679 }
4680 else
4681 {
4682 i.rm.reg = i.op[source].regs->reg_num;
4683 i.rm.regmem = i.op[dest].regs->reg_num;
4684 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4685 i.rex |= REX_B;
29b0f896 4686 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4687 i.rex |= REX_R;
29b0f896 4688 }
161a04f6 4689 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4690 {
40fb9820
L		 4691 if (!i.types[0].bitfield.control
4692 && !i.types[1].bitfield.control)
c4a530c5 4693 abort ();
161a04f6 4694 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4695 add_prefix (LOCK_PREFIX_OPCODE);
4696 }
29b0f896
AM		 4697 }
4698 else
4699 { /* If it's not 2 reg operands... */
4700 if (i.mem_operands)
4701 {
4702 unsigned int fake_zero_displacement = 0;
99018f42 4703 unsigned int op;
4eed87de 4704
85f10a01
MM		 4705 /* This has been precalculated for SSE5 instructions
4706 that have a DREX field earlier in process_drex. */
b5016f89
L		 4707 if (i.tm.opcode_modifier.drex
4708 || i.tm.opcode_modifier.drexv
4709 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4710 op = i.drex.modrm_regmem;
4711 else
4712 {
c0209578
L		 4713 for (op = 0; op < i.operands; op++)
4714 if (operand_type_check (i.types[op], anymem))
4715 break;
4716 assert (op < i.operands);
85f10a01 4717 }
29b0f896
AM		 4718
4719 default_seg = &ds;
4720
4721 if (i.base_reg == 0)
4722 {
4723 i.rm.mode = 0;
4724 if (!i.disp_operands)
4725 fake_zero_displacement = 1;
4726 if (i.index_reg == 0)
4727 {
4728 /* Operand is just <disp> */
20f0a1fc 4729 if (flag_code == CODE_64BIT)
29b0f896
AM		 4730 {
4731 /* 64bit mode overwrites the 32bit absolute
4732 addressing by RIP relative addressing and
4733 absolute addressing is encoded by one of the
4734 redundant SIB forms. */
4735 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4736 i.sib.base = NO_BASE_REGISTER;
4737 i.sib.index = NO_INDEX_REGISTER;
fc225355 4738 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4739 ? disp32s : disp32);
20f0a1fc 4740 }
fc225355
L		 4741 else if ((flag_code == CODE_16BIT)
4742 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4743 {
4744 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4745 i.types[op] = disp16;
20f0a1fc
NC		 4746 }
4747 else
4748 {
4749 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4750 i.types[op] = disp32;
29b0f896
AM		 4751 }
4752 }
4753 else /* !i.base_reg && i.index_reg */
4754 {
db51cc60
L		 4755 if (i.index_reg->reg_num == RegEiz
4756 || i.index_reg->reg_num == RegRiz)
4757 i.sib.index = NO_INDEX_REGISTER;
4758 else
4759 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4760 i.sib.base = NO_BASE_REGISTER;
4761 i.sib.scale = i.log2_scale_factor;
4762 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4763 i.types[op].bitfield.disp8 = 0;
4764 i.types[op].bitfield.disp16 = 0;
4765 i.types[op].bitfield.disp64 = 0;
29b0f896 4766 if (flag_code != CODE_64BIT)
40fb9820
L		 4767 {
4768 /* Must be 32 bit */
4769 i.types[op].bitfield.disp32 = 1;
4770 i.types[op].bitfield.disp32s = 0;
4771 }
29b0f896 4772 else
40fb9820
L		 4773 {
4774 i.types[op].bitfield.disp32 = 0;
4775 i.types[op].bitfield.disp32s = 1;
4776 }
29b0f896 4777 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4778 i.rex |= REX_X;
29b0f896
AM		 4779 }
4780 }
4781 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4782 else if (i.base_reg->reg_num == RegRip ||
4783 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4784 {
4785 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4786 i.types[op].bitfield.disp8 = 0;
4787 i.types[op].bitfield.disp16 = 0;
4788 i.types[op].bitfield.disp32 = 0;
4789 i.types[op].bitfield.disp32s = 1;
4790 i.types[op].bitfield.disp64 = 0;
71903a11 4791 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4792 if (! i.disp_operands)
4793 fake_zero_displacement = 1;
29b0f896 4794 }
40fb9820 4795 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4796 {
4797 switch (i.base_reg->reg_num)
4798 {
4799 case 3: /* (%bx) */
4800 if (i.index_reg == 0)
4801 i.rm.regmem = 7;
4802 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4803 i.rm.regmem = i.index_reg->reg_num - 6;
4804 break;
4805 case 5: /* (%bp) */
4806 default_seg = &ss;
4807 if (i.index_reg == 0)
4808 {
4809 i.rm.regmem = 6;
40fb9820 4810 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4811 {
4812 /* fake (%bp) into 0(%bp) */
40fb9820 4813 i.types[op].bitfield.disp8 = 1;
252b5132 4814 fake_zero_displacement = 1;
29b0f896
AM		 4815 }
4816 }
4817 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4818 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4819 break;
4820 default: /* (%si) -> 4 or (%di) -> 5 */
4821 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4822 }
4823 i.rm.mode = mode_from_disp_size (i.types[op]);
4824 }
4825 else /* i.base_reg and 32/64 bit mode */
4826 {
4827 if (flag_code == CODE_64BIT
40fb9820
L		 4828 && operand_type_check (i.types[op], disp))
4829 {
4830 i386_operand_type temp;
c6fb90c8 4831 UINTS_CLEAR (temp);
40fb9820
L		 4832 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4833 i.types[op] = temp;
4834 if (i.prefix[ADDR_PREFIX] == 0)
4835 i.types[op].bitfield.disp32s = 1;
4836 else
4837 i.types[op].bitfield.disp32 = 1;
4838 }
20f0a1fc 4839
29b0f896
AM		 4840 i.rm.regmem = i.base_reg->reg_num;
4841 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4842 i.rex |= REX_B;
29b0f896
AM		 4843 i.sib.base = i.base_reg->reg_num;
4844 /* x86-64 ignores REX prefix bit here to avoid decoder
4845 complications. */
4846 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4847 {
4848 default_seg = &ss;
4849 if (i.disp_operands == 0)
4850 {
4851 fake_zero_displacement = 1;
40fb9820 4852 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4853 }
4854 }
4855 else if (i.base_reg->reg_num == ESP_REG_NUM)
4856 {
4857 default_seg = &ss;
4858 }
4859 i.sib.scale = i.log2_scale_factor;
4860 if (i.index_reg == 0)
4861 {
4862 /* <disp>(%esp) becomes two byte modrm with no index
4863 register. We've already stored the code for esp
4864 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4865 Any base register besides %esp will not use the
4866 extra modrm byte. */
4867 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4868 }
4869 else
4870 {
db51cc60
L		 4871 if (i.index_reg->reg_num == RegEiz
4872 || i.index_reg->reg_num == RegRiz)
4873 i.sib.index = NO_INDEX_REGISTER;
4874 else
4875 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4876 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4877 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4878 i.rex |= REX_X;
29b0f896 4879 }
67a4f2b7
AO		 4880
4881 if (i.disp_operands
4882 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4883 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4884 i.rm.mode = 0;
4885 else
4886 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4887 }
252b5132 4888
29b0f896
AM		 4889 if (fake_zero_displacement)
4890 {
4891 /* Fakes a zero displacement assuming that i.types[op]
4892 holds the correct displacement size. */
4893 expressionS *exp;
4894
4895 assert (i.op[op].disps == 0);
4896 exp = &disp_expressions[i.disp_operands++];
4897 i.op[op].disps = exp;
4898 exp->X_op = O_constant;
4899 exp->X_add_number = 0;
4900 exp->X_add_symbol = (symbolS *) 0;
4901 exp->X_op_symbol = (symbolS *) 0;
4902 }
4903 }
252b5132 4904
29b0f896
AM		 4905 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4906 (if any) based on i.tm.extension_opcode. Again, we must be
4907 careful to make sure that segment/control/debug/test/MMX
4908 registers are coded into the i.rm.reg field. */
4909 if (i.reg_operands)
4910 {
99018f42
L		 4911 unsigned int op;
4912
85f10a01
MM		 4913 /* This has been precalculated for SSE5 instructions
4914 that have a DREX field earlier in process_drex. */
b5016f89
L		 4915 if (i.tm.opcode_modifier.drex
4916 || i.tm.opcode_modifier.drexv
4917 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4918 {
4919 op = i.drex.modrm_reg;
4920 i.rm.reg = i.op[op].regs->reg_num;
4921 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4922 i.rex |= REX_R;
4923 }
4924 else
4925 {
c0209578
L		 4926 for (op = 0; op < i.operands; op++)
4927 if (i.types[op].bitfield.reg8
4928 || i.types[op].bitfield.reg16
4929 || i.types[op].bitfield.reg32
4930 || i.types[op].bitfield.reg64
4931 || i.types[op].bitfield.regmmx
4932 || i.types[op].bitfield.regxmm
4933 || i.types[op].bitfield.sreg2
4934 || i.types[op].bitfield.sreg3
4935 || i.types[op].bitfield.control
4936 || i.types[op].bitfield.debug
4937 || i.types[op].bitfield.test)
4938 break;
4939
4940 assert (op < i.operands);
99018f42 4941
85f10a01
MM		 4942 /* If there is an extension opcode to put here, the
4943 register number must be put into the regmem field. */
c0209578
L		 4944 if (i.tm.extension_opcode != None)
4945 {
4946 i.rm.regmem = i.op[op].regs->reg_num;
4947 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4948 i.rex |= REX_B;
4949 }
4950 else
4951 {
4952 i.rm.reg = i.op[op].regs->reg_num;
4953 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4954 i.rex |= REX_R;
4955 }
85f10a01 4956 }
252b5132 4957
29b0f896
AM		 4958 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4959 must set it to 3 to indicate this is a register operand
4960 in the regmem field. */
4961 if (!i.mem_operands)
4962 i.rm.mode = 3;
4963 }
252b5132 4964
29b0f896 4965 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4966 if (i.tm.extension_opcode != None
4967 && !(i.tm.opcode_modifier.drex
4968 || i.tm.opcode_modifier.drexv
4969 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4970 i.rm.reg = i.tm.extension_opcode;
4971 }
4972 return default_seg;
4973}
252b5132 4974
29b0f896 4975static void
e3bb37b5 4976output_branch (void)
29b0f896
AM		 4977{
4978 char *p;
4979 int code16;
4980 int prefix;
4981 relax_substateT subtype;
4982 symbolS *sym;
4983 offsetT off;
4984
4985 code16 = 0;
4986 if (flag_code == CODE_16BIT)
4987 code16 = CODE16;
4988
4989 prefix = 0;
4990 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4991 {
29b0f896
AM		 4992 prefix = 1;
4993 i.prefixes -= 1;
4994 code16 ^= CODE16;
252b5132 4995 }
29b0f896
AM		 4996 /* Pentium4 branch hints. */
4997 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4998 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4999 {
29b0f896
AM		 5000 prefix++;
5001 i.prefixes--;
5002 }
5003 if (i.prefix[REX_PREFIX] != 0)
5004 {
5005 prefix++;
5006 i.prefixes--;
2f66722d
AM		 5007 }
5008
29b0f896
AM		 5009 if (i.prefixes != 0 && !intel_syntax)
5010 as_warn (_("skipping prefixes on this instruction"));
5011
5012 /* It's always a symbol; End frag & setup for relax.
5013 Make sure there is enough room in this frag for the largest
5014 instruction we may generate in md_convert_frag. This is 2
5015 bytes for the opcode and room for the prefix and largest
5016 displacement. */
5017 frag_grow (prefix + 2 + 4);
5018 /* Prefix and 1 opcode byte go in fr_fix. */
5019 p = frag_more (prefix + 1);
5020 if (i.prefix[DATA_PREFIX] != 0)
5021 *p++ = DATA_PREFIX_OPCODE;
5022 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5023 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5024 *p++ = i.prefix[SEG_PREFIX];
5025 if (i.prefix[REX_PREFIX] != 0)
5026 *p++ = i.prefix[REX_PREFIX];
5027 *p = i.tm.base_opcode;
5028
5029 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5030 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5031 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5032 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5033 else
5034 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5035 subtype |= code16;
3e73aa7c 5036
29b0f896
AM		 5037 sym = i.op[0].disps->X_add_symbol;
5038 off = i.op[0].disps->X_add_number;
3e73aa7c 5039
29b0f896
AM		 5040 if (i.op[0].disps->X_op != O_constant
5041 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5042 {
29b0f896
AM		 5043 /* Handle complex expressions. */
5044 sym = make_expr_symbol (i.op[0].disps);
5045 off = 0;
5046 }
3e73aa7c 5047
29b0f896
AM		 5048 /* 1 possible extra opcode + 4 byte displacement go in var part.
5049 Pass reloc in fr_var. */
5050 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5051}
3e73aa7c 5052
29b0f896 5053static void
e3bb37b5 5054output_jump (void)
29b0f896
AM		 5055{
5056 char *p;
5057 int size;
3e02c1cc 5058 fixS *fixP;
29b0f896 5059
40fb9820 5060 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5061 {
5062 /* This is a loop or jecxz type instruction. */
5063 size = 1;
5064 if (i.prefix[ADDR_PREFIX] != 0)
5065 {
5066 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5067 i.prefixes -= 1;
5068 }
5069 /* Pentium4 branch hints. */
5070 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5071 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5072 {
5073 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5074 i.prefixes--;
3e73aa7c
JH		 5075 }
5076 }
29b0f896
AM		 5077 else
5078 {
5079 int code16;
3e73aa7c 5080
29b0f896
AM		 5081 code16 = 0;
5082 if (flag_code == CODE_16BIT)
5083 code16 = CODE16;
3e73aa7c 5084
29b0f896
AM		 5085 if (i.prefix[DATA_PREFIX] != 0)
5086 {
5087 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5088 i.prefixes -= 1;
5089 code16 ^= CODE16;
5090 }
252b5132 5091
29b0f896
AM		 5092 size = 4;
5093 if (code16)
5094 size = 2;
5095 }
9fcc94b6 5096
29b0f896
AM		 5097 if (i.prefix[REX_PREFIX] != 0)
5098 {
5099 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5100 i.prefixes -= 1;
5101 }
252b5132 5102
29b0f896
AM		 5103 if (i.prefixes != 0 && !intel_syntax)
5104 as_warn (_("skipping prefixes on this instruction"));
e0890092 5105
29b0f896
AM		 5106 p = frag_more (1 + size);
5107 *p++ = i.tm.base_opcode;
e0890092 5108
3e02c1cc
AM		 5109 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5110 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5111
5112 /* All jumps handled here are signed, but don't use a signed limit
5113 check for 32 and 16 bit jumps as we want to allow wrap around at
5114 4G and 64k respectively. */
5115 if (size == 1)
5116 fixP->fx_signed = 1;
29b0f896 5117}
e0890092 5118
29b0f896 5119static void
e3bb37b5 5120output_interseg_jump (void)
29b0f896
AM		 5121{
5122 char *p;
5123 int size;
5124 int prefix;
5125 int code16;
252b5132 5126
29b0f896
AM		 5127 code16 = 0;
5128 if (flag_code == CODE_16BIT)
5129 code16 = CODE16;
a217f122 5130
29b0f896
AM		 5131 prefix = 0;
5132 if (i.prefix[DATA_PREFIX] != 0)
5133 {
5134 prefix = 1;
5135 i.prefixes -= 1;
5136 code16 ^= CODE16;
5137 }
5138 if (i.prefix[REX_PREFIX] != 0)
5139 {
5140 prefix++;
5141 i.prefixes -= 1;
5142 }
252b5132 5143
29b0f896
AM		 5144 size = 4;
5145 if (code16)
5146 size = 2;
252b5132 5147
29b0f896
AM		 5148 if (i.prefixes != 0 && !intel_syntax)
5149 as_warn (_("skipping prefixes on this instruction"));
252b5132 5150
29b0f896
AM		 5151 /* 1 opcode; 2 segment; offset */
5152 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5153
29b0f896
AM		 5154 if (i.prefix[DATA_PREFIX] != 0)
5155 *p++ = DATA_PREFIX_OPCODE;
252b5132 5156
29b0f896
AM		 5157 if (i.prefix[REX_PREFIX] != 0)
5158 *p++ = i.prefix[REX_PREFIX];
252b5132 5159
29b0f896
AM		 5160 *p++ = i.tm.base_opcode;
5161 if (i.op[1].imms->X_op == O_constant)
5162 {
5163 offsetT n = i.op[1].imms->X_add_number;
252b5132 5164
29b0f896
AM		 5165 if (size == 2
5166 && !fits_in_unsigned_word (n)
5167 && !fits_in_signed_word (n))
5168 {
5169 as_bad (_("16-bit jump out of range"));
5170 return;
5171 }
5172 md_number_to_chars (p, n, size);
5173 }
5174 else
5175 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5176 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5177 if (i.op[0].imms->X_op != O_constant)
5178 as_bad (_("can't handle non absolute segment in `%s'"),
5179 i.tm.name);
5180 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5181}
a217f122 5182
29b0f896 5183static void
e3bb37b5 5184output_insn (void)
29b0f896 5185{
2bbd9c25
JJ		 5186 fragS *insn_start_frag;
5187 offsetT insn_start_off;
5188
29b0f896
AM		 5189 /* Tie dwarf2 debug info to the address at the start of the insn.
5190 We can't do this after the insn has been output as the current
5191 frag may have been closed off. eg. by frag_var. */
5192 dwarf2_emit_insn (0);
5193
2bbd9c25
JJ		 5194 insn_start_frag = frag_now;
5195 insn_start_off = frag_now_fix ();
5196
29b0f896 5197 /* Output jumps. */
40fb9820 5198 if (i.tm.opcode_modifier.jump)
29b0f896 5199 output_branch ();
40fb9820
L		 5200 else if (i.tm.opcode_modifier.jumpbyte
5201 || i.tm.opcode_modifier.jumpdword)
29b0f896 5202 output_jump ();
40fb9820 5203 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5204 output_interseg_jump ();
5205 else
5206 {
5207 /* Output normal instructions here. */
5208 char *p;
5209 unsigned char *q;
47465058 5210 unsigned int j;
331d2d0d 5211 unsigned int prefix;
4dffcebc
L		 5212
5213 switch (i.tm.opcode_length)
bc4bd9ab 5214 {
4dffcebc 5215 case 3:
331d2d0d
L		 5216 if (i.tm.base_opcode & 0xff000000)
5217 {
5218 prefix = (i.tm.base_opcode >> 24) & 0xff;
5219 goto check_prefix;
5220 }
4dffcebc
L		 5221 break;
5222 case 2:
5223 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 5224 {
4dffcebc
L		 5225 prefix = (i.tm.base_opcode >> 16) & 0xff;
5226 if (i.tm.cpu_flags.bitfield.cpupadlock)
5227 {
5228check_prefix:
5229 if (prefix != REPE_PREFIX_OPCODE
5230 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5231 add_prefix (prefix);
5232 }
5233 else
bc4bd9ab
MK		 5234 add_prefix (prefix);
5235 }
4dffcebc
L		 5236 break;
5237 case 1:
5238 break;
5239 default:
5240 abort ();
0f10071e 5241 }
252b5132 5242
29b0f896 5243 /* The prefix bytes. */
47465058
L		 5244 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5245 if (*q)
5246 FRAG_APPEND_1_CHAR (*q);
252b5132 5247
29b0f896 5248 /* Now the opcode; be careful about word order here! */
4dffcebc 5249 if (i.tm.opcode_length == 1)
29b0f896
AM		 5250 {
5251 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5252 }
5253 else
5254 {
4dffcebc 5255 switch (i.tm.opcode_length)
331d2d0d 5256 {
4dffcebc 5257 case 3:
331d2d0d
L		 5258 p = frag_more (3);
5259 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5260 break;
5261 case 2:
5262 p = frag_more (2);
5263 break;
5264 default:
5265 abort ();
5266 break;
331d2d0d 5267 }
0f10071e 5268
29b0f896
AM		 5269 /* Put out high byte first: can't use md_number_to_chars! */
5270 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5271 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5272
5273 /* On SSE5, encode the OC1 bit in the DREX field if this
5274 encoding has multiple formats. */
5275 if (i.tm.opcode_modifier.drex
5276 && i.tm.opcode_modifier.drexv
5277 && DREX_OC1 (i.tm.extension_opcode))
5278 *p |= DREX_OC1_MASK;
29b0f896 5279 }
3e73aa7c 5280
29b0f896 5281 /* Now the modrm byte and sib byte (if present). */
40fb9820 5282 if (i.tm.opcode_modifier.modrm)
29b0f896 5283 {
4a3523fa
L		 5284 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5285 | i.rm.reg << 3
5286 | i.rm.mode << 6));
29b0f896
AM		 5287 /* If i.rm.regmem == ESP (4)
5288 && i.rm.mode != (Register mode)
5289 && not 16 bit
5290 ==> need second modrm byte. */
5291 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5292 && i.rm.mode != 3
40fb9820 5293 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5294 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5295 | i.sib.index << 3
5296 | i.sib.scale << 6));
29b0f896 5297 }
3e73aa7c 5298
85f10a01
MM		 5299 /* Write the DREX byte if needed. */
5300 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5301 {
5302 p = frag_more (1);
5303 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5304
5305 /* Encode the OC0 bit if this encoding has multiple
5306 formats. */
5307 if ((i.tm.opcode_modifier.drex
5308 || i.tm.opcode_modifier.drexv)
5309 && DREX_OC0 (i.tm.extension_opcode))
5310 *p |= DREX_OC0_MASK;
5311 }
5312
29b0f896 5313 if (i.disp_operands)
2bbd9c25 5314 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5315
29b0f896 5316 if (i.imm_operands)
2bbd9c25 5317 output_imm (insn_start_frag, insn_start_off);
29b0f896 5318 }
252b5132 5319
29b0f896
AM		 5320#ifdef DEBUG386
5321 if (flag_debug)
5322 {
7b81dfbb 5323 pi ("" /*line*/, &i);
29b0f896
AM		 5324 }
5325#endif /* DEBUG386 */
5326}
252b5132 5327
e205caa7
L		 5328/* Return the size of the displacement operand N. */
5329
5330static int
5331disp_size (unsigned int n)
5332{
5333 int size = 4;
40fb9820
L		 5334 if (i.types[n].bitfield.disp64)
5335 size = 8;
5336 else if (i.types[n].bitfield.disp8)
5337 size = 1;
5338 else if (i.types[n].bitfield.disp16)
5339 size = 2;
e205caa7
L		 5340 return size;
5341}
5342
5343/* Return the size of the immediate operand N. */
5344
5345static int
5346imm_size (unsigned int n)
5347{
5348 int size = 4;
40fb9820
L		 5349 if (i.types[n].bitfield.imm64)
5350 size = 8;
5351 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5352 size = 1;
5353 else if (i.types[n].bitfield.imm16)
5354 size = 2;
e205caa7
L		 5355 return size;
5356}
5357
29b0f896 5358static void
64e74474 5359output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5360{
5361 char *p;
5362 unsigned int n;
252b5132 5363
29b0f896
AM		 5364 for (n = 0; n < i.operands; n++)
5365 {
40fb9820 5366 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5367 {
5368 if (i.op[n].disps->X_op == O_constant)
5369 {
e205caa7 5370 int size = disp_size (n);
29b0f896 5371 offsetT val;
252b5132 5372
29b0f896
AM		 5373 val = offset_in_range (i.op[n].disps->X_add_number,
5374 size);
5375 p = frag_more (size);
5376 md_number_to_chars (p, val, size);
5377 }
5378 else
5379 {
f86103b7 5380 enum bfd_reloc_code_real reloc_type;
e205caa7 5381 int size = disp_size (n);
40fb9820 5382 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5383 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5384
e205caa7 5385 /* We can't have 8 bit displacement here. */
40fb9820 5386 assert (!i.types[n].bitfield.disp8);
e205caa7 5387
29b0f896
AM		 5388 /* The PC relative address is computed relative
5389 to the instruction boundary, so in case immediate
5390 fields follows, we need to adjust the value. */
5391 if (pcrel && i.imm_operands)
5392 {
29b0f896 5393 unsigned int n1;
e205caa7 5394 int sz = 0;
252b5132 5395
29b0f896 5396 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5397 if (operand_type_check (i.types[n1], imm))
252b5132 5398 {
e205caa7
L		 5399 /* Only one immediate is allowed for PC
5400 relative address. */
5401 assert (sz == 0);
5402 sz = imm_size (n1);
5403 i.op[n].disps->X_add_number -= sz;
252b5132 5404 }
29b0f896 5405 /* We should find the immediate. */
e205caa7 5406 assert (sz != 0);
29b0f896 5407 }
520dc8e8 5408
29b0f896 5409 p = frag_more (size);
2bbd9c25 5410 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5411 if (GOT_symbol
2bbd9c25 5412 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5413 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5414 || reloc_type == BFD_RELOC_X86_64_32S
5415 || (reloc_type == BFD_RELOC_64
5416 && object_64bit))
d6ab8113
JB		 5417 && (i.op[n].disps->X_op == O_symbol
5418 || (i.op[n].disps->X_op == O_add
5419 && ((symbol_get_value_expression
5420 (i.op[n].disps->X_op_symbol)->X_op)
5421 == O_subtract))))
5422 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5423 {
5424 offsetT add;
5425
5426 if (insn_start_frag == frag_now)
5427 add = (p - frag_now->fr_literal) - insn_start_off;
5428 else
5429 {
5430 fragS *fr;
5431
5432 add = insn_start_frag->fr_fix - insn_start_off;
5433 for (fr = insn_start_frag->fr_next;
5434 fr && fr != frag_now; fr = fr->fr_next)
5435 add += fr->fr_fix;
5436 add += p - frag_now->fr_literal;
5437 }
5438
4fa24527 5439 if (!object_64bit)
7b81dfbb
AJ		 5440 {
5441 reloc_type = BFD_RELOC_386_GOTPC;
5442 i.op[n].imms->X_add_number += add;
5443 }
5444 else if (reloc_type == BFD_RELOC_64)
5445 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5446 else
7b81dfbb
AJ		 5447 /* Don't do the adjustment for x86-64, as there
5448 the pcrel addressing is relative to the _next_
5449 insn, and that is taken care of in other code. */
d6ab8113 5450 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5451 }
062cd5e7 5452 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5453 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5454 }
5455 }
5456 }
5457}
252b5132 5458
29b0f896 5459static void
64e74474 5460output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5461{
5462 char *p;
5463 unsigned int n;
252b5132 5464
29b0f896
AM		 5465 for (n = 0; n < i.operands; n++)
5466 {
40fb9820 5467 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5468 {
5469 if (i.op[n].imms->X_op == O_constant)
5470 {
e205caa7 5471 int size = imm_size (n);
29b0f896 5472 offsetT val;
b4cac588 5473
29b0f896
AM		 5474 val = offset_in_range (i.op[n].imms->X_add_number,
5475 size);
5476 p = frag_more (size);
5477 md_number_to_chars (p, val, size);
5478 }
5479 else
5480 {
5481 /* Not absolute_section.
5482 Need a 32-bit fixup (don't support 8bit
5483 non-absolute imms). Try to support other
5484 sizes ... */
f86103b7 5485 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5486 int size = imm_size (n);
5487 int sign;
29b0f896 5488
40fb9820 5489 if (i.types[n].bitfield.imm32s
a7d61044 5490 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5491 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5492 sign = 1;
e205caa7
L		 5493 else
5494 sign = 0;
520dc8e8 5495
29b0f896
AM		 5496 p = frag_more (size);
5497 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5498
2bbd9c25
JJ		 5499 /* This is tough to explain. We end up with this one if we
5500 * have operands that look like
5501 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5502 * obtain the absolute address of the GOT, and it is strongly
5503 * preferable from a performance point of view to avoid using
5504 * a runtime relocation for this. The actual sequence of
5505 * instructions often look something like:
5506 *
5507 * call .L66
5508 * .L66:
5509 * popl %ebx
5510 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5511 *
5512 * The call and pop essentially return the absolute address
5513 * of the label .L66 and store it in %ebx. The linker itself
5514 * will ultimately change the first operand of the addl so
5515 * that %ebx points to the GOT, but to keep things simple, the
5516 * .o file must have this operand set so that it generates not
5517 * the absolute address of .L66, but the absolute address of
5518 * itself. This allows the linker itself simply treat a GOTPC
5519 * relocation as asking for a pcrel offset to the GOT to be
5520 * added in, and the addend of the relocation is stored in the
5521 * operand field for the instruction itself.
5522 *
5523 * Our job here is to fix the operand so that it would add
5524 * the correct offset so that %ebx would point to itself. The
5525 * thing that is tricky is that .-.L66 will point to the
5526 * beginning of the instruction, so we need to further modify
5527 * the operand so that it will point to itself. There are
5528 * other cases where you have something like:
5529 *
5530 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5531 *
5532 * and here no correction would be required. Internally in
5533 * the assembler we treat operands of this form as not being
5534 * pcrel since the '.' is explicitly mentioned, and I wonder
5535 * whether it would simplify matters to do it this way. Who
5536 * knows. In earlier versions of the PIC patches, the
5537 * pcrel_adjust field was used to store the correction, but
5538 * since the expression is not pcrel, I felt it would be
5539 * confusing to do it this way. */
5540
d6ab8113 5541 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5542 || reloc_type == BFD_RELOC_X86_64_32S
5543 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5544 && GOT_symbol
5545 && GOT_symbol == i.op[n].imms->X_add_symbol
5546 && (i.op[n].imms->X_op == O_symbol
5547 || (i.op[n].imms->X_op == O_add
5548 && ((symbol_get_value_expression
5549 (i.op[n].imms->X_op_symbol)->X_op)
5550 == O_subtract))))
5551 {
2bbd9c25
JJ		 5552 offsetT add;
5553
5554 if (insn_start_frag == frag_now)
5555 add = (p - frag_now->fr_literal) - insn_start_off;
5556 else
5557 {
5558 fragS *fr;
5559
5560 add = insn_start_frag->fr_fix - insn_start_off;
5561 for (fr = insn_start_frag->fr_next;
5562 fr && fr != frag_now; fr = fr->fr_next)
5563 add += fr->fr_fix;
5564 add += p - frag_now->fr_literal;
5565 }
5566
4fa24527 5567 if (!object_64bit)
d6ab8113 5568 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5569 else if (size == 4)
d6ab8113 5570 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5571 else if (size == 8)
5572 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5573 i.op[n].imms->X_add_number += add;
29b0f896 5574 }
29b0f896
AM		 5575 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5576 i.op[n].imms, 0, reloc_type);
5577 }
5578 }
5579 }
252b5132
RH		 5580}
5581\f
d182319b
JB		 5582/* x86_cons_fix_new is called via the expression parsing code when a
5583 reloc is needed. We use this hook to get the correct .got reloc. */
5584static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5585static int cons_sign = -1;
5586
5587void
e3bb37b5 5588x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5589 expressionS *exp)
d182319b
JB		 5590{
5591 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5592
5593 got_reloc = NO_RELOC;
5594
5595#ifdef TE_PE
5596 if (exp->X_op == O_secrel)
5597 {
5598 exp->X_op = O_symbol;
5599 r = BFD_RELOC_32_SECREL;
5600 }
5601#endif
5602
5603 fix_new_exp (frag, off, len, exp, 0, r);
5604}
5605
718ddfc0
JB		 5606#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5607# define lex_got(reloc, adjust, types) NULL
5608#else
f3c180ae
AM		 5609/* Parse operands of the form
5610 <symbol>@GOTOFF+<nnn>
5611 and similar .plt or .got references.
5612
5613 If we find one, set up the correct relocation in RELOC and copy the
5614 input string, minus the `@GOTOFF' into a malloc'd buffer for
5615 parsing by the calling routine. Return this buffer, and if ADJUST
5616 is non-null set it to the length of the string we removed from the
5617 input line. Otherwise return NULL. */
5618static char *
3956db08 5619lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5620 int *adjust,
40fb9820 5621 i386_operand_type *types)
f3c180ae 5622{
7b81dfbb
AJ		 5623 /* Some of the relocations depend on the size of what field is to
5624 be relocated. But in our callers i386_immediate and i386_displacement
5625 we don't yet know the operand size (this will be set by insn
5626 matching). Hence we record the word32 relocation here,
5627 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5628 static const struct {
5629 const char *str;
4fa24527 5630 const enum bfd_reloc_code_real rel[2];
40fb9820 5631 const i386_operand_type types64;
f3c180ae 5632 } gotrel[] = {
4eed87de
AM		 5633 { "PLTOFF", { 0,
5634 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5635 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5636 { "PLT", { BFD_RELOC_386_PLT32,
5637 BFD_RELOC_X86_64_PLT32 },
40fb9820 5638 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5639 { "GOTPLT", { 0,
5640 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5641 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5642 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5643 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5644 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5645 { "GOTPCREL", { 0,
5646 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5647 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5648 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5649 BFD_RELOC_X86_64_TLSGD },
40fb9820 5650 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5651 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5652 0 },
40fb9820 5653 OPERAND_TYPE_NONE },
4eed87de
AM		 5654 { "TLSLD", { 0,
5655 BFD_RELOC_X86_64_TLSLD },
40fb9820 5656 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5657 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5658 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5659 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5660 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5661 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5662 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5663 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5664 0 },
40fb9820 5665 OPERAND_TYPE_NONE },
4eed87de
AM		 5666 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5667 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5668
5669 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5670 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5671 0 },
40fb9820 5672 OPERAND_TYPE_NONE },
4eed87de
AM		 5673 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5674 0 },
40fb9820 5675 OPERAND_TYPE_NONE },
4eed87de
AM		 5676 { "GOT", { BFD_RELOC_386_GOT32,
5677 BFD_RELOC_X86_64_GOT32 },
40fb9820 5678 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5679 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5680 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5681 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5682 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5683 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5684 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5685 };
5686 char *cp;
5687 unsigned int j;
5688
718ddfc0
JB		 5689 if (!IS_ELF)
5690 return NULL;
5691
f3c180ae 5692 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5693 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5694 return NULL;
5695
47465058 5696 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5697 {
5698 int len;
5699
5700 len = strlen (gotrel[j].str);
28f81592 5701 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5702 {
4fa24527 5703 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5704 {
28f81592
AM		 5705 int first, second;
5706 char *tmpbuf, *past_reloc;
f3c180ae 5707
4fa24527 5708 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5709 if (adjust)
5710 *adjust = len;
f3c180ae 5711
3956db08
JB		 5712 if (types)
5713 {
5714 if (flag_code != CODE_64BIT)
40fb9820
L		 5715 {
5716 types->bitfield.imm32 = 1;
5717 types->bitfield.disp32 = 1;
5718 }
3956db08
JB		 5719 else
5720 *types = gotrel[j].types64;
5721 }
5722
f3c180ae
AM		 5723 if (GOT_symbol == NULL)
5724 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5725
28f81592 5726 /* The length of the first part of our input line. */
f3c180ae 5727 first = cp - input_line_pointer;
28f81592
AM		 5728
5729 /* The second part goes from after the reloc token until
67c11a9b 5730 (and including) an end_of_line char or comma. */
28f81592 5731 past_reloc = cp + 1 + len;
67c11a9b
AM		 5732 cp = past_reloc;
5733 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5734 ++cp;
5735 second = cp + 1 - past_reloc;
28f81592
AM		 5736
5737 /* Allocate and copy string. The trailing NUL shouldn't
5738 be necessary, but be safe. */
5739 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5740 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5741 if (second != 0 && *past_reloc != ' ')
5742 /* Replace the relocation token with ' ', so that
5743 errors like foo@GOTOFF1 will be detected. */
5744 tmpbuf[first++] = ' ';
5745 memcpy (tmpbuf + first, past_reloc, second);
5746 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5747 return tmpbuf;
5748 }
5749
4fa24527
JB		 5750 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5751 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5752 return NULL;
5753 }
5754 }
5755
5756 /* Might be a symbol version string. Don't as_bad here. */
5757 return NULL;
5758}
5759
f3c180ae 5760void
e3bb37b5 5761x86_cons (expressionS *exp, int size)
f3c180ae 5762{
4fa24527 5763 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5764 {
5765 /* Handle @GOTOFF and the like in an expression. */
5766 char *save;
5767 char *gotfree_input_line;
5768 int adjust;
5769
5770 save = input_line_pointer;
3956db08 5771 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5772 if (gotfree_input_line)
5773 input_line_pointer = gotfree_input_line;
5774
5775 expression (exp);
5776
5777 if (gotfree_input_line)
5778 {
5779 /* expression () has merrily parsed up to the end of line,
5780 or a comma - in the wrong buffer. Transfer how far
5781 input_line_pointer has moved to the right buffer. */
5782 input_line_pointer = (save
5783 + (input_line_pointer - gotfree_input_line)
5784 + adjust);
5785 free (gotfree_input_line);
3992d3b7
AM		 5786 if (exp->X_op == O_constant
5787 || exp->X_op == O_absent
5788 || exp->X_op == O_illegal
5789 || exp->X_op == O_register
5790 || exp->X_op == O_big)
5791 {
5792 char c = *input_line_pointer;
5793 *input_line_pointer = 0;
5794 as_bad (_("missing or invalid expression `%s'"), save);
5795 *input_line_pointer = c;
5796 }
f3c180ae
AM		 5797 }
5798 }
5799 else
5800 expression (exp);
5801}
5802#endif
5803
d182319b 5804static void signed_cons (int size)
6482c264 5805{
d182319b
JB		 5806 if (flag_code == CODE_64BIT)
5807 cons_sign = 1;
5808 cons (size);
5809 cons_sign = -1;
6482c264
NC		 5810}
5811
d182319b 5812#ifdef TE_PE
6482c264
NC		 5813static void
5814pe_directive_secrel (dummy)
5815 int dummy ATTRIBUTE_UNUSED;
5816{
5817 expressionS exp;
5818
5819 do
5820 {
5821 expression (&exp);
5822 if (exp.X_op == O_symbol)
5823 exp.X_op = O_secrel;
5824
5825 emit_expr (&exp, 4);
5826 }
5827 while (*input_line_pointer++ == ',');
5828
5829 input_line_pointer--;
5830 demand_empty_rest_of_line ();
5831}
6482c264
NC		 5832#endif
5833
252b5132 5834static int
70e41ade 5835i386_immediate (char *imm_start)
252b5132
RH		 5836{
5837 char *save_input_line_pointer;
f3c180ae 5838 char *gotfree_input_line;
252b5132 5839 segT exp_seg = 0;
47926f60 5840 expressionS *exp;
40fb9820
L		 5841 i386_operand_type types;
5842
c6fb90c8 5843 UINTS_SET (types, ~0);
252b5132
RH		 5844
5845 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5846 {
31b2323c
L		 5847 as_bad (_("at most %d immediate operands are allowed"),
5848 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5849 return 0;
5850 }
5851
5852 exp = &im_expressions[i.imm_operands++];
520dc8e8 5853 i.op[this_operand].imms = exp;
252b5132
RH		 5854
5855 if (is_space_char (*imm_start))
5856 ++imm_start;
5857
5858 save_input_line_pointer = input_line_pointer;
5859 input_line_pointer = imm_start;
5860
3956db08 5861 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5862 if (gotfree_input_line)
5863 input_line_pointer = gotfree_input_line;
252b5132
RH		 5864
5865 exp_seg = expression (exp);
5866
83183c0c 5867 SKIP_WHITESPACE ();
252b5132 5868 if (*input_line_pointer)
f3c180ae 5869 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5870
5871 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5872 if (gotfree_input_line)
5873 free (gotfree_input_line);
252b5132 5874
3992d3b7
AM		 5875 if (exp->X_op == O_absent
5876 || exp->X_op == O_illegal
5877 || exp->X_op == O_big
5878 || (gotfree_input_line
5879 && (exp->X_op == O_constant
5880 || exp->X_op == O_register)))
252b5132 5881 {
3992d3b7 5882 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5883 imm_start);
3992d3b7 5884 return 0;
252b5132 5885 }
3e73aa7c 5886 else if (exp->X_op == O_constant)
252b5132 5887 {
47926f60 5888 /* Size it properly later. */
40fb9820 5889 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5890 /* If BFD64, sign extend val. */
4eed87de
AM		 5891 if (!use_rela_relocations
5892 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5893 exp->X_add_number
5894 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5895 }
4c63da97 5896#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5897 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5898 && exp_seg != absolute_section
47926f60 5899 && exp_seg != text_section
24eab124
AM		 5900 && exp_seg != data_section
5901 && exp_seg != bss_section
5902 && exp_seg != undefined_section
f86103b7 5903 && !bfd_is_com_section (exp_seg))
252b5132 5904 {
d0b47220 5905 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5906 return 0;
5907 }
5908#endif
bb8f5920
L		 5909 else if (!intel_syntax && exp->X_op == O_register)
5910 {
5911 as_bad (_("illegal immediate register operand %s"), imm_start);
5912 return 0;
5913 }
252b5132
RH		 5914 else
5915 {
5916 /* This is an address. The size of the address will be
24eab124 5917 determined later, depending on destination register,
3e73aa7c 5918 suffix, or the default for the section. */
40fb9820
L		 5919 i.types[this_operand].bitfield.imm8 = 1;
5920 i.types[this_operand].bitfield.imm16 = 1;
5921 i.types[this_operand].bitfield.imm32 = 1;
5922 i.types[this_operand].bitfield.imm32s = 1;
5923 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5924 i.types[this_operand] = operand_type_and (i.types[this_operand],
5925 types);
252b5132
RH		 5926 }
5927
5928 return 1;
5929}
5930
551c1ca1 5931static char *
e3bb37b5 5932i386_scale (char *scale)
252b5132 5933{
551c1ca1
AM		 5934 offsetT val;
5935 char *save = input_line_pointer;
252b5132 5936
551c1ca1
AM		 5937 input_line_pointer = scale;
5938 val = get_absolute_expression ();
5939
5940 switch (val)
252b5132 5941 {
551c1ca1 5942 case 1:
252b5132
RH		 5943 i.log2_scale_factor = 0;
5944 break;
551c1ca1 5945 case 2:
252b5132
RH		 5946 i.log2_scale_factor = 1;
5947 break;
551c1ca1 5948 case 4:
252b5132
RH		 5949 i.log2_scale_factor = 2;
5950 break;
551c1ca1 5951 case 8:
252b5132
RH		 5952 i.log2_scale_factor = 3;
5953 break;
5954 default:
a724f0f4
JB		 5955 {
5956 char sep = *input_line_pointer;
5957
5958 *input_line_pointer = '\0';
5959 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5960 scale);
5961 *input_line_pointer = sep;
5962 input_line_pointer = save;
5963 return NULL;
5964 }
252b5132 5965 }
29b0f896 5966 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5967 {
5968 as_warn (_("scale factor of %d without an index register"),
24eab124 5969 1 << i.log2_scale_factor);
252b5132 5970 i.log2_scale_factor = 0;
252b5132 5971 }
551c1ca1
AM		 5972 scale = input_line_pointer;
5973 input_line_pointer = save;
5974 return scale;
252b5132
RH		 5975}
5976
252b5132 5977static int
e3bb37b5 5978i386_displacement (char *disp_start, char *disp_end)
252b5132 5979{
29b0f896 5980 expressionS *exp;
252b5132
RH		 5981 segT exp_seg = 0;
5982 char *save_input_line_pointer;
f3c180ae 5983 char *gotfree_input_line;
40fb9820
L		 5984 int override;
5985 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5986 int ret;
252b5132 5987
31b2323c
L		 5988 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5989 {
5990 as_bad (_("at most %d displacement operands are allowed"),
5991 MAX_MEMORY_OPERANDS);
5992 return 0;
5993 }
5994
c6fb90c8 5995 UINTS_CLEAR (bigdisp);
40fb9820
L		 5996 if ((i.types[this_operand].bitfield.jumpabsolute)
5997 || (!current_templates->start->opcode_modifier.jump
5998 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5999 {
40fb9820 6000 bigdisp.bitfield.disp32 = 1;
e05278af 6001 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6002 if (flag_code == CODE_64BIT)
6003 {
6004 if (!override)
6005 {
6006 bigdisp.bitfield.disp32s = 1;
6007 bigdisp.bitfield.disp64 = 1;
6008 }
6009 }
6010 else if ((flag_code == CODE_16BIT) ^ override)
6011 {
6012 bigdisp.bitfield.disp32 = 0;
6013 bigdisp.bitfield.disp16 = 1;
6014 }
e05278af
JB		 6015 }
6016 else
6017 {
6018 /* For PC-relative branches, the width of the displacement
6019 is dependent upon data size, not address size. */
e05278af 6020 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6021 if (flag_code == CODE_64BIT)
6022 {
6023 if (override || i.suffix == WORD_MNEM_SUFFIX)
6024 bigdisp.bitfield.disp16 = 1;
6025 else
6026 {
6027 bigdisp.bitfield.disp32 = 1;
6028 bigdisp.bitfield.disp32s = 1;
6029 }
6030 }
6031 else
e05278af
JB		 6032 {
6033 if (!override)
6034 override = (i.suffix == (flag_code != CODE_16BIT
6035 ? WORD_MNEM_SUFFIX
6036 : LONG_MNEM_SUFFIX));
40fb9820
L		 6037 bigdisp.bitfield.disp32 = 1;
6038 if ((flag_code == CODE_16BIT) ^ override)
6039 {
6040 bigdisp.bitfield.disp32 = 0;
6041 bigdisp.bitfield.disp16 = 1;
6042 }
e05278af 6043 }
e05278af 6044 }
c6fb90c8
L		 6045 i.types[this_operand] = operand_type_or (i.types[this_operand],
6046 bigdisp);
252b5132
RH		 6047
6048 exp = &disp_expressions[i.disp_operands];
520dc8e8 6049 i.op[this_operand].disps = exp;
252b5132
RH		 6050 i.disp_operands++;
6051 save_input_line_pointer = input_line_pointer;
6052 input_line_pointer = disp_start;
6053 END_STRING_AND_SAVE (disp_end);
6054
6055#ifndef GCC_ASM_O_HACK
6056#define GCC_ASM_O_HACK 0
6057#endif
6058#if GCC_ASM_O_HACK
6059 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6060 if (i.types[this_operand].bitfield.baseIndex
24eab124 6061 && displacement_string_end[-1] == '+')
252b5132
RH		 6062 {
6063 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6064 constraint within gcc asm statements.
6065 For instance:
6066
6067 #define _set_tssldt_desc(n,addr,limit,type) \
6068 __asm__ __volatile__ ( \
6069 "movw %w2,%0\n\t" \
6070 "movw %w1,2+%0\n\t" \
6071 "rorl $16,%1\n\t" \
6072 "movb %b1,4+%0\n\t" \
6073 "movb %4,5+%0\n\t" \
6074 "movb $0,6+%0\n\t" \
6075 "movb %h1,7+%0\n\t" \
6076 "rorl $16,%1" \
6077 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6078
6079 This works great except that the output assembler ends
6080 up looking a bit weird if it turns out that there is
6081 no offset. You end up producing code that looks like:
6082
6083 #APP
6084 movw $235,(%eax)
6085 movw %dx,2+(%eax)
6086 rorl $16,%edx
6087 movb %dl,4+(%eax)
6088 movb $137,5+(%eax)
6089 movb $0,6+(%eax)
6090 movb %dh,7+(%eax)
6091 rorl $16,%edx
6092 #NO_APP
6093
47926f60 6094 So here we provide the missing zero. */
24eab124
AM		 6095
6096 *displacement_string_end = '0';
252b5132
RH		 6097 }
6098#endif
3956db08 6099 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6100 if (gotfree_input_line)
6101 input_line_pointer = gotfree_input_line;
252b5132 6102
24eab124 6103 exp_seg = expression (exp);
252b5132 6104
636c26b0
AM		 6105 SKIP_WHITESPACE ();
6106 if (*input_line_pointer)
6107 as_bad (_("junk `%s' after expression"), input_line_pointer);
6108#if GCC_ASM_O_HACK
6109 RESTORE_END_STRING (disp_end + 1);
6110#endif
636c26b0 6111 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6112 if (gotfree_input_line)
6113 free (gotfree_input_line);
3992d3b7 6114 ret = 1;
636c26b0 6115
24eab124
AM		 6116 /* We do this to make sure that the section symbol is in
6117 the symbol table. We will ultimately change the relocation
47926f60 6118 to be relative to the beginning of the section. */
1ae12ab7 6119 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6120 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6121 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6122 {
636c26b0 6123 if (exp->X_op != O_symbol)
3992d3b7 6124 goto inv_disp;
636c26b0 6125
e5cb08ac 6126 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6127 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6128 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6129 exp->X_op = O_subtract;
6130 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6131 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6132 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6133 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6134 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6135 else
29b0f896 6136 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6137 }
252b5132 6138
3992d3b7
AM		 6139 else if (exp->X_op == O_absent
6140 || exp->X_op == O_illegal
6141 || exp->X_op == O_big
6142 || (gotfree_input_line
6143 && (exp->X_op == O_constant
6144 || exp->X_op == O_register)))
2daf4fd8 6145 {
3992d3b7
AM		 6146 inv_disp:
6147 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6148 disp_start);
3992d3b7 6149 ret = 0;
2daf4fd8
AM		 6150 }
6151
4c63da97 6152#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6153 else if (exp->X_op != O_constant
6154 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6155 && exp_seg != absolute_section
6156 && exp_seg != text_section
6157 && exp_seg != data_section
6158 && exp_seg != bss_section
6159 && exp_seg != undefined_section
6160 && !bfd_is_com_section (exp_seg))
24eab124 6161 {
d0b47220 6162 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6163 ret = 0;
24eab124 6164 }
252b5132 6165#endif
3956db08 6166
3992d3b7
AM		 6167 RESTORE_END_STRING (disp_end);
6168
40fb9820
L		 6169 /* Check if this is a displacement only operand. */
6170 bigdisp = i.types[this_operand];
6171 bigdisp.bitfield.disp8 = 0;
6172 bigdisp.bitfield.disp16 = 0;
6173 bigdisp.bitfield.disp32 = 0;
6174 bigdisp.bitfield.disp32s = 0;
6175 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 6176 if (UINTS_ALL_ZERO (bigdisp))
6177 i.types[this_operand] = operand_type_and (i.types[this_operand],
6178 types);
3956db08 6179
3992d3b7 6180 return ret;
252b5132
RH		 6181}
6182
eecb386c 6183/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6184 Return 1 on success, 0 on a failure. */
6185
252b5132 6186static int
e3bb37b5 6187i386_index_check (const char *operand_string)
252b5132 6188{
3e73aa7c 6189 int ok;
24eab124 6190#if INFER_ADDR_PREFIX
eecb386c
AM		 6191 int fudged = 0;
6192
24eab124
AM		 6193 tryprefix:
6194#endif
3e73aa7c 6195 ok = 1;
75178d9d 6196 if (flag_code == CODE_64BIT)
64e74474 6197 {
64e74474 6198 if ((i.base_reg
40fb9820
L		 6199 && ((i.prefix[ADDR_PREFIX] == 0
6200 && !i.base_reg->reg_type.bitfield.reg64)
6201 || (i.prefix[ADDR_PREFIX]
6202 && !i.base_reg->reg_type.bitfield.reg32))
6203 && (i.index_reg
9a04903e
JB		 6204 || i.base_reg->reg_num !=
6205 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6206 || (i.index_reg
40fb9820
L		 6207 && (!i.index_reg->reg_type.bitfield.baseindex
6208 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6209 && i.index_reg->reg_num != RegRiz
6210 && !i.index_reg->reg_type.bitfield.reg64
6211 )
40fb9820 6212 || (i.prefix[ADDR_PREFIX]
db51cc60 6213 && i.index_reg->reg_num != RegEiz
40fb9820 6214 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6215 ok = 0;
3e73aa7c
JH		 6216 }
6217 else
6218 {
6219 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6220 {
6221 /* 16bit checks. */
6222 if ((i.base_reg
40fb9820
L		 6223 && (!i.base_reg->reg_type.bitfield.reg16
6224 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6225 || (i.index_reg
40fb9820
L		 6226 && (!i.index_reg->reg_type.bitfield.reg16
6227 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6228 || !(i.base_reg
6229 && i.base_reg->reg_num < 6
6230 && i.index_reg->reg_num >= 6
6231 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6232 ok = 0;
6233 }
6234 else
e5cb08ac 6235 {
3e73aa7c
JH		 6236 /* 32bit checks. */
6237 if ((i.base_reg
40fb9820 6238 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6239 || (i.index_reg
db51cc60
L		 6240 && ((!i.index_reg->reg_type.bitfield.reg32
6241 && i.index_reg->reg_num != RegEiz)
40fb9820 6242 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6243 ok = 0;
3e73aa7c
JH		 6244 }
6245 }
6246 if (!ok)
24eab124
AM		 6247 {
6248#if INFER_ADDR_PREFIX
20f0a1fc 6249 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6250 {
6251 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6252 i.prefixes += 1;
b23bac36
AM		 6253 /* Change the size of any displacement too. At most one of
6254 Disp16 or Disp32 is set.
6255 FIXME. There doesn't seem to be any real need for separate
6256 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6257 Removing them would probably clean up the code quite a lot. */
4eed87de 6258 if (flag_code != CODE_64BIT
40fb9820
L		 6259 && (i.types[this_operand].bitfield.disp16
6260 || i.types[this_operand].bitfield.disp32))
6261 i.types[this_operand]
c6fb90c8 6262 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6263 fudged = 1;
24eab124
AM		 6264 goto tryprefix;
6265 }
eecb386c
AM		 6266 if (fudged)
6267 as_bad (_("`%s' is not a valid base/index expression"),
6268 operand_string);
6269 else
c388dee8 6270#endif
eecb386c
AM		 6271 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6272 operand_string,
3e73aa7c 6273 flag_code_names[flag_code]);
24eab124 6274 }
20f0a1fc 6275 return ok;
24eab124 6276}
252b5132 6277
252b5132 6278/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6279 on error. */
252b5132 6280
252b5132 6281static int
a7619375 6282i386_att_operand (char *operand_string)
252b5132 6283{
af6bdddf
AM		 6284 const reg_entry *r;
6285 char *end_op;
24eab124 6286 char *op_string = operand_string;
252b5132 6287
24eab124 6288 if (is_space_char (*op_string))
252b5132
RH		 6289 ++op_string;
6290
24eab124 6291 /* We check for an absolute prefix (differentiating,
47926f60 6292 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6293 if (*op_string == ABSOLUTE_PREFIX)
6294 {
6295 ++op_string;
6296 if (is_space_char (*op_string))
6297 ++op_string;
40fb9820 6298 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6299 }
252b5132 6300
47926f60 6301 /* Check if operand is a register. */
4d1bb795 6302 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6303 {
40fb9820
L		 6304 i386_operand_type temp;
6305
24eab124
AM		 6306 /* Check for a segment override by searching for ':' after a
6307 segment register. */
6308 op_string = end_op;
6309 if (is_space_char (*op_string))
6310 ++op_string;
40fb9820
L		 6311 if (*op_string == ':'
6312 && (r->reg_type.bitfield.sreg2
6313 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6314 {
6315 switch (r->reg_num)
6316 {
6317 case 0:
6318 i.seg[i.mem_operands] = &es;
6319 break;
6320 case 1:
6321 i.seg[i.mem_operands] = &cs;
6322 break;
6323 case 2:
6324 i.seg[i.mem_operands] = &ss;
6325 break;
6326 case 3:
6327 i.seg[i.mem_operands] = &ds;
6328 break;
6329 case 4:
6330 i.seg[i.mem_operands] = &fs;
6331 break;
6332 case 5:
6333 i.seg[i.mem_operands] = &gs;
6334 break;
6335 }
252b5132 6336
24eab124 6337 /* Skip the ':' and whitespace. */
252b5132
RH		 6338 ++op_string;
6339 if (is_space_char (*op_string))
24eab124 6340 ++op_string;
252b5132 6341
24eab124
AM		 6342 if (!is_digit_char (*op_string)
6343 && !is_identifier_char (*op_string)
6344 && *op_string != '('
6345 && *op_string != ABSOLUTE_PREFIX)
6346 {
6347 as_bad (_("bad memory operand `%s'"), op_string);
6348 return 0;
6349 }
47926f60 6350 /* Handle case of %es:*foo. */
24eab124
AM		 6351 if (*op_string == ABSOLUTE_PREFIX)
6352 {
6353 ++op_string;
6354 if (is_space_char (*op_string))
6355 ++op_string;
40fb9820 6356 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6357 }
6358 goto do_memory_reference;
6359 }
6360 if (*op_string)
6361 {
d0b47220 6362 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6363 return 0;
6364 }
40fb9820
L		 6365 temp = r->reg_type;
6366 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6367 i.types[this_operand] = operand_type_or (i.types[this_operand],
6368 temp);
7d5e4556 6369 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6370 i.op[this_operand].regs = r;
24eab124
AM		 6371 i.reg_operands++;
6372 }
af6bdddf
AM		 6373 else if (*op_string == REGISTER_PREFIX)
6374 {
6375 as_bad (_("bad register name `%s'"), op_string);
6376 return 0;
6377 }
24eab124 6378 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6379 {
24eab124 6380 ++op_string;
40fb9820 6381 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6382 {
d0b47220 6383 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6384 return 0;
6385 }
6386 if (!i386_immediate (op_string))
6387 return 0;
6388 }
6389 else if (is_digit_char (*op_string)
6390 || is_identifier_char (*op_string)
e5cb08ac 6391 || *op_string == '(')
24eab124 6392 {
47926f60 6393 /* This is a memory reference of some sort. */
af6bdddf 6394 char *base_string;
252b5132 6395
47926f60 6396 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6397 char *displacement_string_start;
6398 char *displacement_string_end;
252b5132 6399
24eab124 6400 do_memory_reference:
24eab124 6401 if ((i.mem_operands == 1
40fb9820 6402 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6403 || i.mem_operands == 2)
6404 {
6405 as_bad (_("too many memory references for `%s'"),
6406 current_templates->start->name);
6407 return 0;
6408 }
252b5132 6409
24eab124
AM		 6410 /* Check for base index form. We detect the base index form by
6411 looking for an ')' at the end of the operand, searching
6412 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6413 after the '('. */
af6bdddf 6414 base_string = op_string + strlen (op_string);
c3332e24 6415
af6bdddf
AM		 6416 --base_string;
6417 if (is_space_char (*base_string))
6418 --base_string;
252b5132 6419
47926f60 6420 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6421 displacement_string_start = op_string;
6422 displacement_string_end = base_string + 1;
252b5132 6423
24eab124
AM		 6424 if (*base_string == ')')
6425 {
af6bdddf 6426 char *temp_string;
24eab124
AM		 6427 unsigned int parens_balanced = 1;
6428 /* We've already checked that the number of left & right ()'s are
47926f60 6429 equal, so this loop will not be infinite. */
24eab124
AM		 6430 do
6431 {
6432 base_string--;
6433 if (*base_string == ')')
6434 parens_balanced++;
6435 if (*base_string == '(')
6436 parens_balanced--;
6437 }
6438 while (parens_balanced);
c3332e24 6439
af6bdddf 6440 temp_string = base_string;
c3332e24 6441
24eab124 6442 /* Skip past '(' and whitespace. */
252b5132
RH		 6443 ++base_string;
6444 if (is_space_char (*base_string))
24eab124 6445 ++base_string;
252b5132 6446
af6bdddf 6447 if (*base_string == ','
4eed87de
AM		 6448 || ((i.base_reg = parse_register (base_string, &end_op))
6449 != NULL))
252b5132 6450 {
af6bdddf 6451 displacement_string_end = temp_string;
252b5132 6452
40fb9820 6453 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6454
af6bdddf 6455 if (i.base_reg)
24eab124 6456 {
24eab124
AM		 6457 base_string = end_op;
6458 if (is_space_char (*base_string))
6459 ++base_string;
af6bdddf
AM		 6460 }
6461
6462 /* There may be an index reg or scale factor here. */
6463 if (*base_string == ',')
6464 {
6465 ++base_string;
6466 if (is_space_char (*base_string))
6467 ++base_string;
6468
4eed87de
AM		 6469 if ((i.index_reg = parse_register (base_string, &end_op))
6470 != NULL)
24eab124 6471 {
af6bdddf 6472 base_string = end_op;
24eab124
AM		 6473 if (is_space_char (*base_string))
6474 ++base_string;
af6bdddf
AM		 6475 if (*base_string == ',')
6476 {
6477 ++base_string;
6478 if (is_space_char (*base_string))
6479 ++base_string;
6480 }
e5cb08ac 6481 else if (*base_string != ')')
af6bdddf 6482 {
4eed87de
AM		 6483 as_bad (_("expecting `,' or `)' "
6484 "after index register in `%s'"),
af6bdddf
AM		 6485 operand_string);
6486 return 0;
6487 }
24eab124 6488 }
af6bdddf 6489 else if (*base_string == REGISTER_PREFIX)
24eab124 6490 {
af6bdddf 6491 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6492 return 0;
6493 }
252b5132 6494
47926f60 6495 /* Check for scale factor. */
551c1ca1 6496 if (*base_string != ')')
af6bdddf 6497 {
551c1ca1
AM		 6498 char *end_scale = i386_scale (base_string);
6499
6500 if (!end_scale)
af6bdddf 6501 return 0;
24eab124 6502
551c1ca1 6503 base_string = end_scale;
af6bdddf
AM		 6504 if (is_space_char (*base_string))
6505 ++base_string;
6506 if (*base_string != ')')
6507 {
4eed87de
AM		 6508 as_bad (_("expecting `)' "
6509 "after scale factor in `%s'"),
af6bdddf
AM		 6510 operand_string);
6511 return 0;
6512 }
6513 }
6514 else if (!i.index_reg)
24eab124 6515 {
4eed87de
AM		 6516 as_bad (_("expecting index register or scale factor "
6517 "after `,'; got '%c'"),
af6bdddf 6518 *base_string);
24eab124
AM		 6519 return 0;
6520 }
6521 }
af6bdddf 6522 else if (*base_string != ')')
24eab124 6523 {
4eed87de
AM		 6524 as_bad (_("expecting `,' or `)' "
6525 "after base register in `%s'"),
af6bdddf 6526 operand_string);
24eab124
AM		 6527 return 0;
6528 }
c3332e24 6529 }
af6bdddf 6530 else if (*base_string == REGISTER_PREFIX)
c3332e24 6531 {
af6bdddf 6532 as_bad (_("bad register name `%s'"), base_string);
24eab124 6533 return 0;
c3332e24 6534 }
24eab124
AM		 6535 }
6536
6537 /* If there's an expression beginning the operand, parse it,
6538 assuming displacement_string_start and
6539 displacement_string_end are meaningful. */
6540 if (displacement_string_start != displacement_string_end)
6541 {
6542 if (!i386_displacement (displacement_string_start,
6543 displacement_string_end))
6544 return 0;
6545 }
6546
6547 /* Special case for (%dx) while doing input/output op. */
6548 if (i.base_reg
c6fb90c8 6549 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6550 && i.index_reg == 0
6551 && i.log2_scale_factor == 0
6552 && i.seg[i.mem_operands] == 0
40fb9820 6553 && !operand_type_check (i.types[this_operand], disp))
24eab124 6554 {
c6fb90c8 6555 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6556 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6557 return 1;
6558 }
6559
eecb386c
AM		 6560 if (i386_index_check (operand_string) == 0)
6561 return 0;
5c07affc 6562 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6563 i.mem_operands++;
6564 }
6565 else
ce8a8b2f
AM		 6566 {
6567 /* It's not a memory operand; argh! */
24eab124
AM		 6568 as_bad (_("invalid char %s beginning operand %d `%s'"),
6569 output_invalid (*op_string),
6570 this_operand + 1,
6571 op_string);
6572 return 0;
6573 }
47926f60 6574 return 1; /* Normal return. */
252b5132
RH		 6575}
6576\f
ee7fcc42
AM		 6577/* md_estimate_size_before_relax()
6578
6579 Called just before relax() for rs_machine_dependent frags. The x86
6580 assembler uses these frags to handle variable size jump
6581 instructions.
6582
6583 Any symbol that is now undefined will not become defined.
6584 Return the correct fr_subtype in the frag.
6585 Return the initial "guess for variable size of frag" to caller.
6586 The guess is actually the growth beyond the fixed part. Whatever
6587 we do to grow the fixed or variable part contributes to our
6588 returned value. */
6589
252b5132
RH		 6590int
6591md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6592 fragS *fragP;
6593 segT segment;
252b5132 6594{
252b5132 6595 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6596 check for un-relaxable symbols. On an ELF system, we can't relax
6597 an externally visible symbol, because it may be overridden by a
6598 shared library. */
6599 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6600#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6601 || (IS_ELF
31312f95
AM		 6602 && (S_IS_EXTERNAL (fragP->fr_symbol)
6603 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6604#endif
6605 )
252b5132 6606 {
b98ef147
AM		 6607 /* Symbol is undefined in this segment, or we need to keep a
6608 reloc so that weak symbols can be overridden. */
6609 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6610 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6611 unsigned char *opcode;
6612 int old_fr_fix;
f6af82bd 6613
ee7fcc42
AM		 6614 if (fragP->fr_var != NO_RELOC)
6615 reloc_type = fragP->fr_var;
b98ef147 6616 else if (size == 2)
f6af82bd
AM		 6617 reloc_type = BFD_RELOC_16_PCREL;
6618 else
6619 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6620
ee7fcc42
AM		 6621 old_fr_fix = fragP->fr_fix;
6622 opcode = (unsigned char *) fragP->fr_opcode;
6623
fddf5b5b 6624 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6625 {
fddf5b5b
AM		 6626 case UNCOND_JUMP:
6627 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6628 opcode[0] = 0xe9;
252b5132 6629 fragP->fr_fix += size;
062cd5e7
AS		 6630 fix_new (fragP, old_fr_fix, size,
6631 fragP->fr_symbol,
6632 fragP->fr_offset, 1,
6633 reloc_type);
252b5132
RH		 6634 break;
6635
fddf5b5b 6636 case COND_JUMP86:
412167cb
AM		 6637 if (size == 2
6638 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6639 {
6640 /* Negate the condition, and branch past an
6641 unconditional jump. */
6642 opcode[0] ^= 1;
6643 opcode[1] = 3;
6644 /* Insert an unconditional jump. */
6645 opcode[2] = 0xe9;
6646 /* We added two extra opcode bytes, and have a two byte
6647 offset. */
6648 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6649 fix_new (fragP, old_fr_fix + 2, 2,
6650 fragP->fr_symbol,
6651 fragP->fr_offset, 1,
6652 reloc_type);
fddf5b5b
AM		 6653 break;
6654 }
6655 /* Fall through. */
6656
6657 case COND_JUMP:
412167cb
AM		 6658 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6659 {
3e02c1cc
AM		 6660 fixS *fixP;
6661
412167cb 6662 fragP->fr_fix += 1;
3e02c1cc
AM		 6663 fixP = fix_new (fragP, old_fr_fix, 1,
6664 fragP->fr_symbol,
6665 fragP->fr_offset, 1,
6666 BFD_RELOC_8_PCREL);
6667 fixP->fx_signed = 1;
412167cb
AM		 6668 break;
6669 }
93c2a809 6670
24eab124 6671 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6672 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6673 opcode[1] = opcode[0] + 0x10;
f6af82bd 6674 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6675 /* We've added an opcode byte. */
6676 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6677 fix_new (fragP, old_fr_fix + 1, size,
6678 fragP->fr_symbol,
6679 fragP->fr_offset, 1,
6680 reloc_type);
252b5132 6681 break;
fddf5b5b
AM		 6682
6683 default:
6684 BAD_CASE (fragP->fr_subtype);
6685 break;
252b5132
RH		 6686 }
6687 frag_wane (fragP);
ee7fcc42 6688 return fragP->fr_fix - old_fr_fix;
252b5132 6689 }
93c2a809 6690
93c2a809
AM		 6691 /* Guess size depending on current relax state. Initially the relax
6692 state will correspond to a short jump and we return 1, because
6693 the variable part of the frag (the branch offset) is one byte
6694 long. However, we can relax a section more than once and in that
6695 case we must either set fr_subtype back to the unrelaxed state,
6696 or return the value for the appropriate branch. */
6697 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6698}
6699
47926f60
KH		 6700/* Called after relax() is finished.
6701
6702 In: Address of frag.
6703 fr_type == rs_machine_dependent.
6704 fr_subtype is what the address relaxed to.
6705
6706 Out: Any fixSs and constants are set up.
6707 Caller will turn frag into a ".space 0". */
6708
252b5132
RH		 6709void
6710md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6711 bfd *abfd ATTRIBUTE_UNUSED;
6712 segT sec ATTRIBUTE_UNUSED;
29b0f896 6713 fragS *fragP;
252b5132 6714{
29b0f896 6715 unsigned char *opcode;
252b5132 6716 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6717 offsetT target_address;
6718 offsetT opcode_address;
252b5132 6719 unsigned int extension = 0;
847f7ad4 6720 offsetT displacement_from_opcode_start;
252b5132
RH		 6721
6722 opcode = (unsigned char *) fragP->fr_opcode;
6723
47926f60 6724 /* Address we want to reach in file space. */
252b5132 6725 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6726
47926f60 6727 /* Address opcode resides at in file space. */
252b5132
RH		 6728 opcode_address = fragP->fr_address + fragP->fr_fix;
6729
47926f60 6730 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6731 displacement_from_opcode_start = target_address - opcode_address;
6732
fddf5b5b 6733 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6734 {
47926f60
KH		 6735 /* Don't have to change opcode. */
6736 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6737 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6738 }
6739 else
6740 {
6741 if (no_cond_jump_promotion
6742 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6743 as_warn_where (fragP->fr_file, fragP->fr_line,
6744 _("long jump required"));
252b5132 6745
fddf5b5b
AM		 6746 switch (fragP->fr_subtype)
6747 {
6748 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6749 extension = 4; /* 1 opcode + 4 displacement */
6750 opcode[0] = 0xe9;
6751 where_to_put_displacement = &opcode[1];
6752 break;
252b5132 6753
fddf5b5b
AM		 6754 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6755 extension = 2; /* 1 opcode + 2 displacement */
6756 opcode[0] = 0xe9;
6757 where_to_put_displacement = &opcode[1];
6758 break;
252b5132 6759
fddf5b5b
AM		 6760 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6761 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6762 extension = 5; /* 2 opcode + 4 displacement */
6763 opcode[1] = opcode[0] + 0x10;
6764 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6765 where_to_put_displacement = &opcode[2];
6766 break;
252b5132 6767
fddf5b5b
AM		 6768 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6769 extension = 3; /* 2 opcode + 2 displacement */
6770 opcode[1] = opcode[0] + 0x10;
6771 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6772 where_to_put_displacement = &opcode[2];
6773 break;
252b5132 6774
fddf5b5b
AM		 6775 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6776 extension = 4;
6777 opcode[0] ^= 1;
6778 opcode[1] = 3;
6779 opcode[2] = 0xe9;
6780 where_to_put_displacement = &opcode[3];
6781 break;
6782
6783 default:
6784 BAD_CASE (fragP->fr_subtype);
6785 break;
6786 }
252b5132 6787 }
fddf5b5b 6788
7b81dfbb
AJ		 6789 /* If size if less then four we are sure that the operand fits,
6790 but if it's 4, then it could be that the displacement is larger
6791 then -/+ 2GB. */
6792 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6793 && object_64bit
6794 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6795 + ((addressT) 1 << 31))
6796 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6797 {
6798 as_bad_where (fragP->fr_file, fragP->fr_line,
6799 _("jump target out of range"));
6800 /* Make us emit 0. */
6801 displacement_from_opcode_start = extension;
6802 }
47926f60 6803 /* Now put displacement after opcode. */
252b5132
RH		 6804 md_number_to_chars ((char *) where_to_put_displacement,
6805 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6806 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6807 fragP->fr_fix += extension;
6808}
6809\f
252b5132
RH		 6810/* Apply a fixup (fixS) to segment data, once it has been determined
6811 by our caller that we have all the info we need to fix it up.
6812
6813 On the 386, immediates, displacements, and data pointers are all in
6814 the same (little-endian) format, so we don't need to care about which
6815 we are handling. */
6816
94f592af 6817void
55cf6793 6818md_apply_fix (fixP, valP, seg)
47926f60
KH		 6819 /* The fix we're to put in. */
6820 fixS *fixP;
47926f60 6821 /* Pointer to the value of the bits. */
c6682705 6822 valueT *valP;
47926f60
KH		 6823 /* Segment fix is from. */
6824 segT seg ATTRIBUTE_UNUSED;
252b5132 6825{
94f592af 6826 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6827 valueT value = *valP;
252b5132 6828
f86103b7 6829#if !defined (TE_Mach)
93382f6d
AM		 6830 if (fixP->fx_pcrel)
6831 {
6832 switch (fixP->fx_r_type)
6833 {
5865bb77
ILT		 6834 default:
6835 break;
6836
d6ab8113
JB		 6837 case BFD_RELOC_64:
6838 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6839 break;
93382f6d 6840 case BFD_RELOC_32:
ae8887b5 6841 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6842 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6843 break;
6844 case BFD_RELOC_16:
6845 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6846 break;
6847 case BFD_RELOC_8:
6848 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6849 break;
6850 }
6851 }
252b5132 6852
a161fe53 6853 if (fixP->fx_addsy != NULL
31312f95 6854 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6855 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6856 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6857 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6858 && !use_rela_relocations)
252b5132 6859 {
31312f95
AM		 6860 /* This is a hack. There should be a better way to handle this.
6861 This covers for the fact that bfd_install_relocation will
6862 subtract the current location (for partial_inplace, PC relative
6863 relocations); see more below. */
252b5132 6864#ifndef OBJ_AOUT
718ddfc0 6865 if (IS_ELF
252b5132
RH		 6866#ifdef TE_PE
6867 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6868#endif
6869 )
6870 value += fixP->fx_where + fixP->fx_frag->fr_address;
6871#endif
6872#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6873 if (IS_ELF)
252b5132 6874 {
6539b54b 6875 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6876
6539b54b 6877 if ((sym_seg == seg
2f66722d 6878 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6879 && sym_seg != absolute_section))
ae6063d4 6880 && !generic_force_reloc (fixP))
2f66722d
AM		 6881 {
6882 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6883 bfd_install_relocation subtracts them out again. I think
6884 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6885 it. FIXME. */
6886 value += fixP->fx_where + fixP->fx_frag->fr_address;
6887 }
252b5132
RH		 6888 }
6889#endif
6890#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6891 /* For some reason, the PE format does not store a
6892 section address offset for a PC relative symbol. */
6893 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6894 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6895 value += md_pcrel_from (fixP);
6896#endif
6897 }
6898
6899 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6900 and we must not disappoint it. */
252b5132 6901#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6902 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6903 switch (fixP->fx_r_type)
6904 {
6905 case BFD_RELOC_386_PLT32:
3e73aa7c 6906 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6907 /* Make the jump instruction point to the address of the operand. At
6908 runtime we merely add the offset to the actual PLT entry. */
6909 value = -4;
6910 break;
31312f95 6911
13ae64f3
JJ		 6912 case BFD_RELOC_386_TLS_GD:
6913 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6914 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6915 case BFD_RELOC_386_TLS_IE:
6916 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6917 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6918 case BFD_RELOC_X86_64_TLSGD:
6919 case BFD_RELOC_X86_64_TLSLD:
6920 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6921 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6922 value = 0; /* Fully resolved at runtime. No addend. */
6923 /* Fallthrough */
6924 case BFD_RELOC_386_TLS_LE:
6925 case BFD_RELOC_386_TLS_LDO_32:
6926 case BFD_RELOC_386_TLS_LE_32:
6927 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6928 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6929 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6930 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6931 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6932 break;
6933
67a4f2b7
AO		 6934 case BFD_RELOC_386_TLS_DESC_CALL:
6935 case BFD_RELOC_X86_64_TLSDESC_CALL:
6936 value = 0; /* Fully resolved at runtime. No addend. */
6937 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6938 fixP->fx_done = 0;
6939 return;
6940
00f7efb6
JJ		 6941 case BFD_RELOC_386_GOT32:
6942 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6943 value = 0; /* Fully resolved at runtime. No addend. */
6944 break;
47926f60
KH		 6945
6946 case BFD_RELOC_VTABLE_INHERIT:
6947 case BFD_RELOC_VTABLE_ENTRY:
6948 fixP->fx_done = 0;
94f592af 6949 return;
47926f60
KH		 6950
6951 default:
6952 break;
6953 }
6954#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6955 *valP = value;
f86103b7 6956#endif /* !defined (TE_Mach) */
3e73aa7c 6957
3e73aa7c 6958 /* Are we finished with this relocation now? */
c6682705 6959 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6960 fixP->fx_done = 1;
6961 else if (use_rela_relocations)
6962 {
6963 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6964 /* Remember value for tc_gen_reloc. */
6965 fixP->fx_addnumber = value;
3e73aa7c
JH		 6966 value = 0;
6967 }
f86103b7 6968
94f592af 6969 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6970}
252b5132 6971\f
252b5132 6972char *
499ac353 6973md_atof (int type, char *litP, int *sizeP)
252b5132 6974{
499ac353
NC		 6975 /* This outputs the LITTLENUMs in REVERSE order;
6976 in accord with the bigendian 386. */
6977 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 6978}
6979\f
2d545b82 6980static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6981
252b5132 6982static char *
e3bb37b5 6983output_invalid (int c)
252b5132 6984{
3882b010 6985 if (ISPRINT (c))
f9f21a03
L		 6986 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6987 "'%c'", c);
252b5132 6988 else
f9f21a03 6989 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6990 "(0x%x)", (unsigned char) c);
252b5132
RH		 6991 return output_invalid_buf;
6992}
6993
af6bdddf 6994/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6995
6996static const reg_entry *
4d1bb795 6997parse_real_register (char *reg_string, char **end_op)
252b5132 6998{
af6bdddf
AM		 6999 char *s = reg_string;
7000 char *p;
252b5132
RH		 7001 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7002 const reg_entry *r;
7003
7004 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7005 if (*s == REGISTER_PREFIX)
7006 ++s;
7007
7008 if (is_space_char (*s))
7009 ++s;
7010
7011 p = reg_name_given;
af6bdddf 7012 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7013 {
7014 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7015 return (const reg_entry *) NULL;
7016 s++;
252b5132
RH		 7017 }
7018
6588847e
DN		 7019 /* For naked regs, make sure that we are not dealing with an identifier.
7020 This prevents confusing an identifier like `eax_var' with register
7021 `eax'. */
7022 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7023 return (const reg_entry *) NULL;
7024
af6bdddf 7025 *end_op = s;
252b5132
RH		 7026
7027 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7028
5f47d35b 7029 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7030 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7031 {
5f47d35b
AM		 7032 if (is_space_char (*s))
7033 ++s;
7034 if (*s == '(')
7035 {
af6bdddf 7036 ++s;
5f47d35b
AM		 7037 if (is_space_char (*s))
7038 ++s;
7039 if (*s >= '0' && *s <= '7')
7040 {
db557034 7041 int fpr = *s - '0';
af6bdddf 7042 ++s;
5f47d35b
AM		 7043 if (is_space_char (*s))
7044 ++s;
7045 if (*s == ')')
7046 {
7047 *end_op = s + 1;
db557034
AM		 7048 r = hash_find (reg_hash, "st(0)");
7049 know (r);
7050 return r + fpr;
5f47d35b 7051 }
5f47d35b 7052 }
47926f60 7053 /* We have "%st(" then garbage. */
5f47d35b
AM		 7054 return (const reg_entry *) NULL;
7055 }
7056 }
7057
db51cc60
L		 7058 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7059 if (r != NULL
7060 && !allow_index_reg
7061 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7062 return (const reg_entry *) NULL;
7063
1ae00879 7064 if (r != NULL
d946b91f 7065 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 7066 || r->reg_type.bitfield.reg64)
7067 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 7068 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 7069 && flag_code != CODE_64BIT)
20f0a1fc 7070 return (const reg_entry *) NULL;
1ae00879 7071
252b5132
RH		 7072 return r;
7073}
4d1bb795
JB		 7074
7075/* REG_STRING starts *before* REGISTER_PREFIX. */
7076
7077static const reg_entry *
7078parse_register (char *reg_string, char **end_op)
7079{
7080 const reg_entry *r;
7081
7082 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7083 r = parse_real_register (reg_string, end_op);
7084 else
7085 r = NULL;
7086 if (!r)
7087 {
7088 char *save = input_line_pointer;
7089 char c;
7090 symbolS *symbolP;
7091
7092 input_line_pointer = reg_string;
7093 c = get_symbol_end ();
7094 symbolP = symbol_find (reg_string);
7095 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7096 {
7097 const expressionS *e = symbol_get_value_expression (symbolP);
7098
7099 know (e->X_op == O_register);
4eed87de 7100 know (e->X_add_number >= 0
c3fe08fa 7101 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7102 r = i386_regtab + e->X_add_number;
7103 *end_op = input_line_pointer;
7104 }
7105 *input_line_pointer = c;
7106 input_line_pointer = save;
7107 }
7108 return r;
7109}
7110
7111int
7112i386_parse_name (char *name, expressionS *e, char *nextcharP)
7113{
7114 const reg_entry *r;
7115 char *end = input_line_pointer;
7116
7117 *end = *nextcharP;
7118 r = parse_register (name, &input_line_pointer);
7119 if (r && end <= input_line_pointer)
7120 {
7121 *nextcharP = *input_line_pointer;
7122 *input_line_pointer = 0;
7123 e->X_op = O_register;
7124 e->X_add_number = r - i386_regtab;
7125 return 1;
7126 }
7127 input_line_pointer = end;
7128 *end = 0;
7129 return 0;
7130}
7131
7132void
7133md_operand (expressionS *e)
7134{
7135 if (*input_line_pointer == REGISTER_PREFIX)
7136 {
7137 char *end;
7138 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7139
7140 if (r)
7141 {
7142 e->X_op = O_register;
7143 e->X_add_number = r - i386_regtab;
7144 input_line_pointer = end;
7145 }
7146 }
7147}
7148
252b5132 7149\f
4cc782b5 7150#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7151const char *md_shortopts = "kVQ:sqn";
252b5132 7152#else
12b55ccc 7153const char *md_shortopts = "qn";
252b5132 7154#endif
6e0b89ee 7155
3e73aa7c 7156#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7157#define OPTION_64 (OPTION_MD_BASE + 1)
7158#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7159#define OPTION_MARCH (OPTION_MD_BASE + 3)
7160#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7161#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7162#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7163#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7164#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7165#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
b3b91714 7166
99ad8390
NC		 7167struct option md_longopts[] =
7168{
3e73aa7c 7169 {"32", no_argument, NULL, OPTION_32},
99ad8390 7170#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7171 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7172#endif
b3b91714 7173 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7174 {"march", required_argument, NULL, OPTION_MARCH},
7175 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7176 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7177 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7178 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7179 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7180 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
252b5132
RH		 7181 {NULL, no_argument, NULL, 0}
7182};
7183size_t md_longopts_size = sizeof (md_longopts);
7184
7185int
9103f4f4 7186md_parse_option (int c, char *arg)
252b5132 7187{
9103f4f4 7188 unsigned int i;
6305a203 7189 char *arch, *next;
9103f4f4 7190
252b5132
RH		 7191 switch (c)
7192 {
12b55ccc
L		 7193 case 'n':
7194 optimize_align_code = 0;
7195 break;
7196
a38cf1db
AM		 7197 case 'q':
7198 quiet_warnings = 1;
252b5132
RH		 7199 break;
7200
7201#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7202 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7203 should be emitted or not. FIXME: Not implemented. */
7204 case 'Q':
252b5132
RH		 7205 break;
7206
7207 /* -V: SVR4 argument to print version ID. */
7208 case 'V':
7209 print_version_id ();
7210 break;
7211
a38cf1db
AM		 7212 /* -k: Ignore for FreeBSD compatibility. */
7213 case 'k':
252b5132 7214 break;
4cc782b5
ILT		 7215
7216 case 's':
7217 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7218 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7219 break;
99ad8390
NC		 7220#endif
7221#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7222 case OPTION_64:
7223 {
7224 const char **list, **l;
7225
3e73aa7c
JH		 7226 list = bfd_target_list ();
7227 for (l = list; *l != NULL; l++)
8620418b 7228 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7229 || strcmp (*l, "coff-x86-64") == 0
7230 || strcmp (*l, "pe-x86-64") == 0
7231 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7232 {
7233 default_arch = "x86_64";
7234 break;
7235 }
3e73aa7c 7236 if (*l == NULL)
6e0b89ee 7237 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7238 free (list);
7239 }
7240 break;
7241#endif
252b5132 7242
6e0b89ee
AM		 7243 case OPTION_32:
7244 default_arch = "i386";
7245 break;
7246
b3b91714
AM		 7247 case OPTION_DIVIDE:
7248#ifdef SVR4_COMMENT_CHARS
7249 {
7250 char *n, *t;
7251 const char *s;
7252
7253 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7254 t = n;
7255 for (s = i386_comment_chars; *s != '\0'; s++)
7256 if (*s != '/')
7257 *t++ = *s;
7258 *t = '\0';
7259 i386_comment_chars = n;
7260 }
7261#endif
7262 break;
7263
9103f4f4 7264 case OPTION_MARCH:
6305a203
L		 7265 arch = xstrdup (arg);
7266 do
9103f4f4 7267 {
6305a203
L		 7268 if (*arch == '.')
7269 as_fatal (_("Invalid -march= option: `%s'"), arg);
7270 next = strchr (arch, '+');
7271 if (next)
7272 *next++ = '\0';
7273 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7274 {
6305a203 7275 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7276 {
6305a203
L		 7277 /* Processor. */
7278 cpu_arch_name = cpu_arch[i].name;
7279 cpu_sub_arch_name = NULL;
7280 cpu_arch_flags = cpu_arch[i].flags;
7281 cpu_arch_isa = cpu_arch[i].type;
7282 cpu_arch_isa_flags = cpu_arch[i].flags;
7283 if (!cpu_arch_tune_set)
7284 {
7285 cpu_arch_tune = cpu_arch_isa;
7286 cpu_arch_tune_flags = cpu_arch_isa_flags;
7287 }
7288 break;
7289 }
7290 else if (*cpu_arch [i].name == '.'
7291 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7292 {
7293 /* ISA entension. */
7294 i386_cpu_flags flags;
7295 flags = cpu_flags_or (cpu_arch_flags,
7296 cpu_arch[i].flags);
7297 if (!UINTS_EQUAL (flags, cpu_arch_flags))
7298 {
7299 if (cpu_sub_arch_name)
7300 {
7301 char *name = cpu_sub_arch_name;
7302 cpu_sub_arch_name = concat (name,
7303 cpu_arch[i].name,
1bf57e9f 7304 (const char *) NULL);
6305a203
L		 7305 free (name);
7306 }
7307 else
7308 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7309 cpu_arch_flags = flags;
7310 }
7311 break;
ccc9c027 7312 }
9103f4f4 7313 }
6305a203
L		 7314
7315 if (i >= ARRAY_SIZE (cpu_arch))
7316 as_fatal (_("Invalid -march= option: `%s'"), arg);
7317
7318 arch = next;
9103f4f4 7319 }
6305a203 7320 while (next != NULL );
9103f4f4
L		 7321 break;
7322
7323 case OPTION_MTUNE:
7324 if (*arg == '.')
7325 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7326 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7327 {
7328 if (strcmp (arg, cpu_arch [i].name) == 0)
7329 {
ccc9c027 7330 cpu_arch_tune_set = 1;
9103f4f4
L		 7331 cpu_arch_tune = cpu_arch [i].type;
7332 cpu_arch_tune_flags = cpu_arch[i].flags;
7333 break;
7334 }
7335 }
7336 if (i >= ARRAY_SIZE (cpu_arch))
7337 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7338 break;
7339
1efbbeb4
L		 7340 case OPTION_MMNEMONIC:
7341 if (strcasecmp (arg, "att") == 0)
7342 intel_mnemonic = 0;
7343 else if (strcasecmp (arg, "intel") == 0)
7344 intel_mnemonic = 1;
7345 else
7346 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7347 break;
7348
7349 case OPTION_MSYNTAX:
7350 if (strcasecmp (arg, "att") == 0)
7351 intel_syntax = 0;
7352 else if (strcasecmp (arg, "intel") == 0)
7353 intel_syntax = 1;
7354 else
7355 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7356 break;
7357
7358 case OPTION_MINDEX_REG:
7359 allow_index_reg = 1;
7360 break;
7361
7362 case OPTION_MNAKED_REG:
7363 allow_naked_reg = 1;
7364 break;
7365
7366 case OPTION_MOLD_GCC:
7367 old_gcc = 1;
1efbbeb4
L		 7368 break;
7369
252b5132
RH		 7370 default:
7371 return 0;
7372 }
7373 return 1;
7374}
7375
7376void
7377md_show_usage (stream)
7378 FILE *stream;
7379{
4cc782b5
ILT		 7380#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7381 fprintf (stream, _("\
a38cf1db
AM		 7382 -Q ignored\n\
7383 -V print assembler version number\n\
b3b91714
AM		 7384 -k ignored\n"));
7385#endif
7386 fprintf (stream, _("\
12b55ccc 7387 -n Do not optimize code alignment\n\
b3b91714
AM		 7388 -q quieten some warnings\n"));
7389#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7390 fprintf (stream, _("\
a38cf1db 7391 -s ignored\n"));
b3b91714 7392#endif
751d281c
L		 7393#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7394 fprintf (stream, _("\
7395 --32/--64 generate 32bit/64bit code\n"));
7396#endif
b3b91714
AM		 7397#ifdef SVR4_COMMENT_CHARS
7398 fprintf (stream, _("\
7399 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7400#else
7401 fprintf (stream, _("\
b3b91714 7402 --divide ignored\n"));
4cc782b5 7403#endif
9103f4f4 7404 fprintf (stream, _("\
6305a203
L		 7405 -march=CPU[,+EXTENSION...]\n\
7406 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 7407 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7408 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7409 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7410 generic32, generic64\n\
599121aa
L		 7411 EXTENSION is combination of:\n\
7412 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f03fe4c1
L		 7413 vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\
7414 abm, padlock\n"));
6305a203 7415 fprintf (stream, _("\
2cb4f3d5
L		 7416 -mtune=CPU optimize for CPU, CPU is one of:\n\
7417 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7418 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7419 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7420 generic32, generic64\n"));
ba104c83
L		 7421 fprintf (stream, _("\
7422 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7423 fprintf (stream, _("\
7424 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7425 fprintf (stream, _("\
7426 -mindex-reg support pseudo index registers\n"));
7427 fprintf (stream, _("\
7428 -mnaked-reg don't require `%%' prefix for registers\n"));
7429 fprintf (stream, _("\
7430 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7431}
7432
3e73aa7c 7433#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7434 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7435
7436/* Pick the target format to use. */
7437
47926f60 7438const char *
e3bb37b5 7439i386_target_format (void)
252b5132 7440{
3e73aa7c 7441 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7442 {
7443 set_code_flag (CODE_64BIT);
c6fb90c8 7444 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7445 {
7446 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7447 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7448 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7449 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7450 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7451 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7452 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7453 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 7454 cpu_arch_isa_flags.bitfield.cpusse = 1;
7455 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7456 }
c6fb90c8 7457 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7458 {
7459 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7460 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7461 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7462 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7463 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7464 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7465 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7466 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 7467 cpu_arch_tune_flags.bitfield.cpusse = 1;
7468 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7469 }
9103f4f4 7470 }
3e73aa7c 7471 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7472 {
7473 set_code_flag (CODE_32BIT);
c6fb90c8 7474 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7475 {
7476 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7477 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7478 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7479 }
c6fb90c8 7480 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7481 {
7482 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7483 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7484 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7485 }
9103f4f4 7486 }
3e73aa7c
JH		 7487 else
7488 as_fatal (_("Unknown architecture"));
252b5132
RH		 7489 switch (OUTPUT_FLAVOR)
7490 {
872ce6ff
L		 7491#ifdef TE_PEP
7492 case bfd_target_coff_flavour:
7493 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7494 break;
7495#endif
4c63da97
AM		 7496#ifdef OBJ_MAYBE_AOUT
7497 case bfd_target_aout_flavour:
47926f60 7498 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7499#endif
7500#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7501 case bfd_target_coff_flavour:
7502 return "coff-i386";
4c63da97 7503#endif
3e73aa7c 7504#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7505 case bfd_target_elf_flavour:
3e73aa7c 7506 {
e5cb08ac 7507 if (flag_code == CODE_64BIT)
4fa24527
JB		 7508 {
7509 object_64bit = 1;
7510 use_rela_relocations = 1;
7511 }
9d7cbccd 7512 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7513 }
4c63da97 7514#endif
252b5132
RH		 7515 default:
7516 abort ();
7517 return NULL;
7518 }
7519}
7520
47926f60 7521#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7522
7523#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7524void
7525i386_elf_emit_arch_note (void)
a847613f 7526{
718ddfc0 7527 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7528 {
7529 char *p;
7530 asection *seg = now_seg;
7531 subsegT subseg = now_subseg;
7532 Elf_Internal_Note i_note;
7533 Elf_External_Note e_note;
7534 asection *note_secp;
7535 int len;
7536
7537 /* Create the .note section. */
7538 note_secp = subseg_new (".note", 0);
7539 bfd_set_section_flags (stdoutput,
7540 note_secp,
7541 SEC_HAS_CONTENTS | SEC_READONLY);
7542
7543 /* Process the arch string. */
7544 len = strlen (cpu_arch_name);
7545
7546 i_note.namesz = len + 1;
7547 i_note.descsz = 0;
7548 i_note.type = NT_ARCH;
7549 p = frag_more (sizeof (e_note.namesz));
7550 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7551 p = frag_more (sizeof (e_note.descsz));
7552 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7553 p = frag_more (sizeof (e_note.type));
7554 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7555 p = frag_more (len + 1);
7556 strcpy (p, cpu_arch_name);
7557
7558 frag_align (2, 0, 0);
7559
7560 subseg_set (seg, subseg);
7561 }
7562}
7563#endif
252b5132 7564\f
252b5132
RH		 7565symbolS *
7566md_undefined_symbol (name)
7567 char *name;
7568{
18dc2407
ILT		 7569 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7570 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7571 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7572 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7573 {
7574 if (!GOT_symbol)
7575 {
7576 if (symbol_find (name))
7577 as_bad (_("GOT already in symbol table"));
7578 GOT_symbol = symbol_new (name, undefined_section,
7579 (valueT) 0, &zero_address_frag);
7580 };
7581 return GOT_symbol;
7582 }
252b5132
RH		 7583 return 0;
7584}
7585
7586/* Round up a section size to the appropriate boundary. */
47926f60 7587
252b5132
RH		 7588valueT
7589md_section_align (segment, size)
ab9da554 7590 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7591 valueT size;
7592{
4c63da97
AM		 7593#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7594 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7595 {
7596 /* For a.out, force the section size to be aligned. If we don't do
7597 this, BFD will align it for us, but it will not write out the
7598 final bytes of the section. This may be a bug in BFD, but it is
7599 easier to fix it here since that is how the other a.out targets
7600 work. */
7601 int align;
7602
7603 align = bfd_get_section_alignment (stdoutput, segment);
7604 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7605 }
252b5132
RH		 7606#endif
7607
7608 return size;
7609}
7610
7611/* On the i386, PC-relative offsets are relative to the start of the
7612 next instruction. That is, the address of the offset, plus its
7613 size, since the offset is always the last part of the insn. */
7614
7615long
e3bb37b5 7616md_pcrel_from (fixS *fixP)
252b5132
RH		 7617{
7618 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7619}
7620
7621#ifndef I386COFF
7622
7623static void
e3bb37b5 7624s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7625{
29b0f896 7626 int temp;
252b5132 7627
8a75718c
JB		 7628#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7629 if (IS_ELF)
7630 obj_elf_section_change_hook ();
7631#endif
252b5132
RH		 7632 temp = get_absolute_expression ();
7633 subseg_set (bss_section, (subsegT) temp);
7634 demand_empty_rest_of_line ();
7635}
7636
7637#endif
7638
252b5132 7639void
e3bb37b5 7640i386_validate_fix (fixS *fixp)
252b5132
RH		 7641{
7642 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7643 {
23df1078
JH		 7644 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7645 {
4fa24527 7646 if (!object_64bit)
23df1078
JH		 7647 abort ();
7648 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7649 }
7650 else
7651 {
4fa24527 7652 if (!object_64bit)
d6ab8113
JB		 7653 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7654 else
7655 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7656 }
252b5132
RH		 7657 fixp->fx_subsy = 0;
7658 }
7659}
7660
252b5132
RH		 7661arelent *
7662tc_gen_reloc (section, fixp)
ab9da554 7663 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7664 fixS *fixp;
7665{
7666 arelent *rel;
7667 bfd_reloc_code_real_type code;
7668
7669 switch (fixp->fx_r_type)
7670 {
3e73aa7c
JH		 7671 case BFD_RELOC_X86_64_PLT32:
7672 case BFD_RELOC_X86_64_GOT32:
7673 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7674 case BFD_RELOC_386_PLT32:
7675 case BFD_RELOC_386_GOT32:
7676 case BFD_RELOC_386_GOTOFF:
7677 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7678 case BFD_RELOC_386_TLS_GD:
7679 case BFD_RELOC_386_TLS_LDM:
7680 case BFD_RELOC_386_TLS_LDO_32:
7681 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7682 case BFD_RELOC_386_TLS_IE:
7683 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7684 case BFD_RELOC_386_TLS_LE_32:
7685 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7686 case BFD_RELOC_386_TLS_GOTDESC:
7687 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7688 case BFD_RELOC_X86_64_TLSGD:
7689 case BFD_RELOC_X86_64_TLSLD:
7690 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7691 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7692 case BFD_RELOC_X86_64_GOTTPOFF:
7693 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7694 case BFD_RELOC_X86_64_TPOFF64:
7695 case BFD_RELOC_X86_64_GOTOFF64:
7696 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7697 case BFD_RELOC_X86_64_GOT64:
7698 case BFD_RELOC_X86_64_GOTPCREL64:
7699 case BFD_RELOC_X86_64_GOTPC64:
7700 case BFD_RELOC_X86_64_GOTPLT64:
7701 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7702 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7703 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7704 case BFD_RELOC_RVA:
7705 case BFD_RELOC_VTABLE_ENTRY:
7706 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7707#ifdef TE_PE
7708 case BFD_RELOC_32_SECREL:
7709#endif
252b5132
RH		 7710 code = fixp->fx_r_type;
7711 break;
dbbaec26
L		 7712 case BFD_RELOC_X86_64_32S:
7713 if (!fixp->fx_pcrel)
7714 {
7715 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7716 code = fixp->fx_r_type;
7717 break;
7718 }
252b5132 7719 default:
93382f6d 7720 if (fixp->fx_pcrel)
252b5132 7721 {
93382f6d
AM		 7722 switch (fixp->fx_size)
7723 {
7724 default:
b091f402
AM		 7725 as_bad_where (fixp->fx_file, fixp->fx_line,
7726 _("can not do %d byte pc-relative relocation"),
7727 fixp->fx_size);
93382f6d
AM		 7728 code = BFD_RELOC_32_PCREL;
7729 break;
7730 case 1: code = BFD_RELOC_8_PCREL; break;
7731 case 2: code = BFD_RELOC_16_PCREL; break;
7732 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7733#ifdef BFD64
7734 case 8: code = BFD_RELOC_64_PCREL; break;
7735#endif
93382f6d
AM		 7736 }
7737 }
7738 else
7739 {
7740 switch (fixp->fx_size)
7741 {
7742 default:
b091f402
AM		 7743 as_bad_where (fixp->fx_file, fixp->fx_line,
7744 _("can not do %d byte relocation"),
7745 fixp->fx_size);
93382f6d
AM		 7746 code = BFD_RELOC_32;
7747 break;
7748 case 1: code = BFD_RELOC_8; break;
7749 case 2: code = BFD_RELOC_16; break;
7750 case 4: code = BFD_RELOC_32; break;
937149dd 7751#ifdef BFD64
3e73aa7c 7752 case 8: code = BFD_RELOC_64; break;
937149dd 7753#endif
93382f6d 7754 }
252b5132
RH		 7755 }
7756 break;
7757 }
252b5132 7758
d182319b
JB		 7759 if ((code == BFD_RELOC_32
7760 || code == BFD_RELOC_32_PCREL
7761 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7762 && GOT_symbol
7763 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7764 {
4fa24527 7765 if (!object_64bit)
d6ab8113
JB		 7766 code = BFD_RELOC_386_GOTPC;
7767 else
7768 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7769 }
7b81dfbb
AJ		 7770 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7771 && GOT_symbol
7772 && fixp->fx_addsy == GOT_symbol)
7773 {
7774 code = BFD_RELOC_X86_64_GOTPC64;
7775 }
252b5132
RH		 7776
7777 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7778 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7779 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7780
7781 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7782
3e73aa7c
JH		 7783 if (!use_rela_relocations)
7784 {
7785 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7786 vtable entry to be used in the relocation's section offset. */
7787 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7788 rel->address = fixp->fx_offset;
252b5132 7789
c6682705 7790 rel->addend = 0;
3e73aa7c
JH		 7791 }
7792 /* Use the rela in 64bit mode. */
252b5132 7793 else
3e73aa7c 7794 {
062cd5e7
AS		 7795 if (!fixp->fx_pcrel)
7796 rel->addend = fixp->fx_offset;
7797 else
7798 switch (code)
7799 {
7800 case BFD_RELOC_X86_64_PLT32:
7801 case BFD_RELOC_X86_64_GOT32:
7802 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7803 case BFD_RELOC_X86_64_TLSGD:
7804 case BFD_RELOC_X86_64_TLSLD:
7805 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7806 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7807 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7808 rel->addend = fixp->fx_offset - fixp->fx_size;
7809 break;
7810 default:
7811 rel->addend = (section->vma
7812 - fixp->fx_size
7813 + fixp->fx_addnumber
7814 + md_pcrel_from (fixp));
7815 break;
7816 }
3e73aa7c
JH		 7817 }
7818
252b5132
RH		 7819 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7820 if (rel->howto == NULL)
7821 {
7822 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7823 _("cannot represent relocation type %s"),
252b5132
RH		 7824 bfd_get_reloc_code_name (code));
7825 /* Set howto to a garbage value so that we can keep going. */
7826 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7827 assert (rel->howto != NULL);
7828 }
7829
7830 return rel;
7831}
7832
64a0c779
DN		 7833\f
7834/* Parse operands using Intel syntax. This implements a recursive descent
7835 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7836 Programmer's Guide.
7837
7838 FIXME: We do not recognize the full operand grammar defined in the MASM
7839 documentation. In particular, all the structure/union and
7840 high-level macro operands are missing.
7841
7842 Uppercase words are terminals, lower case words are non-terminals.
7843 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7844 bars '|' denote choices. Most grammar productions are implemented in
7845 functions called 'intel_<production>'.
7846
7847 Initial production is 'expr'.
7848
9306ca4a 7849 addOp + | -
64a0c779
DN		 7850
7851 alpha [a-zA-Z]
7852
9306ca4a
JB		 7853 binOp & | AND | \| | OR | ^ | XOR
7854
64a0c779
DN		 7855 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7856
7857 constant digits [[ radixOverride ]]
7858
9306ca4a 7859 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7860
7861 digits decdigit
b77a7acd
AJ		 7862 | digits decdigit
7863 | digits hexdigit
64a0c779
DN		 7864
7865 decdigit [0-9]
7866
9306ca4a
JB		 7867 e04 e04 addOp e05
7868 | e05
7869
7870 e05 e05 binOp e06
b77a7acd 7871 | e06
64a0c779
DN		 7872
7873 e06 e06 mulOp e09
b77a7acd 7874 | e09
64a0c779
DN		 7875
7876 e09 OFFSET e10
a724f0f4
JB		 7877 | SHORT e10
7878 | + e10
7879 | - e10
9306ca4a
JB		 7880 | ~ e10
7881 | NOT e10
64a0c779
DN		 7882 | e09 PTR e10
7883 | e09 : e10
7884 | e10
7885
7886 e10 e10 [ expr ]
b77a7acd 7887 | e11
64a0c779
DN		 7888
7889 e11 ( expr )
b77a7acd 7890 | [ expr ]
64a0c779
DN		 7891 | constant
7892 | dataType
7893 | id
7894 | $
7895 | register
7896
a724f0f4 7897 => expr expr cmpOp e04
9306ca4a 7898 | e04
64a0c779
DN		 7899
7900 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7901 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7902
7903 hexdigit a | b | c | d | e | f
b77a7acd 7904 | A | B | C | D | E | F
64a0c779
DN		 7905
7906 id alpha
b77a7acd 7907 | id alpha
64a0c779
DN		 7908 | id decdigit
7909
9306ca4a 7910 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7911
7912 quote " | '
7913
7914 register specialRegister
b77a7acd 7915 | gpRegister
64a0c779
DN		 7916 | byteRegister
7917
7918 segmentRegister CS | DS | ES | FS | GS | SS
7919
9306ca4a 7920 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7921 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7922 | TR3 | TR4 | TR5 | TR6 | TR7
7923
64a0c779
DN		 7924 We simplify the grammar in obvious places (e.g., register parsing is
7925 done by calling parse_register) and eliminate immediate left recursion
7926 to implement a recursive-descent parser.
7927
a724f0f4
JB		 7928 expr e04 expr'
7929
7930 expr' cmpOp e04 expr'
7931 | Empty
9306ca4a
JB		 7932
7933 e04 e05 e04'
7934
7935 e04' addOp e05 e04'
7936 | Empty
64a0c779
DN		 7937
7938 e05 e06 e05'
7939
9306ca4a 7940 e05' binOp e06 e05'
b77a7acd 7941 | Empty
64a0c779
DN		 7942
7943 e06 e09 e06'
7944
7945 e06' mulOp e09 e06'
b77a7acd 7946 | Empty
64a0c779
DN		 7947
7948 e09 OFFSET e10 e09'
a724f0f4
JB		 7949 | SHORT e10'
7950 | + e10'
7951 | - e10'
7952 | ~ e10'
7953 | NOT e10'
b77a7acd 7954 | e10 e09'
64a0c779
DN		 7955
7956 e09' PTR e10 e09'
b77a7acd 7957 | : e10 e09'
64a0c779
DN		 7958 | Empty
7959
7960 e10 e11 e10'
7961
7962 e10' [ expr ] e10'
b77a7acd 7963 | Empty
64a0c779
DN		 7964
7965 e11 ( expr )
b77a7acd 7966 | [ expr ]
64a0c779
DN		 7967 | BYTE
7968 | WORD
7969 | DWORD
9306ca4a 7970 | FWORD
64a0c779 7971 | QWORD
9306ca4a
JB		 7972 | TBYTE
7973 | OWORD
7974 | XMMWORD
64a0c779
DN		 7975 | .
7976 | $
7977 | register
7978 | id
7979 | constant */
7980
7981/* Parsing structure for the intel syntax parser. Used to implement the
7982 semantic actions for the operand grammar. */
7983struct intel_parser_s
7984 {
7985 char *op_string; /* The string being parsed. */
7986 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7987 int op_modifier; /* Operand modifier. */
64a0c779 7988 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7989 int in_offset; /* >=1 if parsing operand of offset. */
7990 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7991 const reg_entry *reg; /* Last register reference found. */
7992 char *disp; /* Displacement string being built. */
a724f0f4 7993 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7994 };
7995
7996static struct intel_parser_s intel_parser;
7997
7998/* Token structure for parsing intel syntax. */
7999struct intel_token
8000 {
8001 int code; /* Token code. */
8002 const reg_entry *reg; /* Register entry for register tokens. */
8003 char *str; /* String representation. */
8004 };
8005
8006static struct intel_token cur_token, prev_token;
8007
50705ef4
AM		 8008/* Token codes for the intel parser. Since T_SHORT is already used
8009 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8010#define T_NIL -1
8011#define T_CONST 1
8012#define T_REG 2
8013#define T_BYTE 3
8014#define T_WORD 4
9306ca4a
JB		 8015#define T_DWORD 5
8016#define T_FWORD 6
8017#define T_QWORD 7
8018#define T_TBYTE 8
8019#define T_XMMWORD 9
50705ef4 8020#undef T_SHORT
9306ca4a
JB		 8021#define T_SHORT 10
8022#define T_OFFSET 11
8023#define T_PTR 12
8024#define T_ID 13
8025#define T_SHL 14
8026#define T_SHR 15
64a0c779
DN		 8027
8028/* Prototypes for intel parser functions. */
e3bb37b5
L		 8029static int intel_match_token (int);
8030static void intel_putback_token (void);
8031static void intel_get_token (void);
8032static int intel_expr (void);
8033static int intel_e04 (void);
8034static int intel_e05 (void);
8035static int intel_e06 (void);
8036static int intel_e09 (void);
8037static int intel_e10 (void);
8038static int intel_e11 (void);
64a0c779 8039
64a0c779 8040static int
e3bb37b5 8041i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8042{
8043 int ret;
8044 char *p;
8045
a724f0f4
JB		 8046 p = intel_parser.op_string = xstrdup (operand_string);
8047 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8048
8049 for (;;)
64a0c779 8050 {
a724f0f4
JB		 8051 /* Initialize token holders. */
8052 cur_token.code = prev_token.code = T_NIL;
8053 cur_token.reg = prev_token.reg = NULL;
8054 cur_token.str = prev_token.str = NULL;
8055
8056 /* Initialize parser structure. */
8057 intel_parser.got_a_float = got_a_float;
8058 intel_parser.op_modifier = 0;
8059 intel_parser.is_mem = 0;
8060 intel_parser.in_offset = 0;
8061 intel_parser.in_bracket = 0;
8062 intel_parser.reg = NULL;
8063 intel_parser.disp[0] = '\0';
8064 intel_parser.next_operand = NULL;
8065
8066 /* Read the first token and start the parser. */
8067 intel_get_token ();
8068 ret = intel_expr ();
8069
8070 if (!ret)
8071 break;
8072
9306ca4a
JB		 8073 if (cur_token.code != T_NIL)
8074 {
8075 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8076 current_templates->start->name, cur_token.str);
8077 ret = 0;
8078 }
64a0c779
DN		 8079 /* If we found a memory reference, hand it over to i386_displacement
8080 to fill in the rest of the operand fields. */
9306ca4a 8081 else if (intel_parser.is_mem)
64a0c779
DN		 8082 {
8083 if ((i.mem_operands == 1
40fb9820 8084 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8085 || i.mem_operands == 2)
8086 {
8087 as_bad (_("too many memory references for '%s'"),
8088 current_templates->start->name);
8089 ret = 0;
8090 }
8091 else
8092 {
8093 char *s = intel_parser.disp;
5c07affc 8094 i.types[this_operand].bitfield.mem = 1;
64a0c779
DN		 8095 i.mem_operands++;
8096
a724f0f4
JB		 8097 if (!quiet_warnings && intel_parser.is_mem < 0)
8098 /* See the comments in intel_bracket_expr. */
8099 as_warn (_("Treating `%s' as memory reference"), operand_string);
8100
64a0c779
DN		 8101 /* Add the displacement expression. */
8102 if (*s != '\0')
a4622f40
AM		 8103 ret = i386_displacement (s, s + strlen (s));
8104 if (ret)
a724f0f4
JB		 8105 {
8106 /* Swap base and index in 16-bit memory operands like
8107 [si+bx]. Since i386_index_check is also used in AT&T
8108 mode we have to do that here. */
8109 if (i.base_reg
8110 && i.index_reg
40fb9820
L		 8111 && i.base_reg->reg_type.bitfield.reg16
8112 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8113 && i.base_reg->reg_num >= 6
8114 && i.index_reg->reg_num < 6)
8115 {
8116 const reg_entry *base = i.index_reg;
8117
8118 i.index_reg = i.base_reg;
8119 i.base_reg = base;
8120 }
8121 ret = i386_index_check (operand_string);
8122 }
64a0c779
DN		 8123 }
8124 }
8125
8126 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8127 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 8128 || intel_parser.reg == NULL)
8129 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 8130
8131 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8132 ret = 0;
a724f0f4
JB		 8133 if (!ret || !intel_parser.next_operand)
8134 break;
8135 intel_parser.op_string = intel_parser.next_operand;
8136 this_operand = i.operands++;
7d5e4556 8137 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8138 }
8139
8140 free (p);
8141 free (intel_parser.disp);
8142
8143 return ret;
8144}
8145
a724f0f4
JB		 8146#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8147
8148/* expr e04 expr'
8149
8150 expr' cmpOp e04 expr'
8151 | Empty */
64a0c779 8152static int
e3bb37b5 8153intel_expr (void)
64a0c779 8154{
a724f0f4
JB		 8155 /* XXX Implement the comparison operators. */
8156 return intel_e04 ();
9306ca4a
JB		 8157}
8158
a724f0f4 8159/* e04 e05 e04'
9306ca4a 8160
a724f0f4 8161 e04' addOp e05 e04'
9306ca4a
JB		 8162 | Empty */
8163static int
e3bb37b5 8164intel_e04 (void)
9306ca4a 8165{
a724f0f4 8166 int nregs = -1;
9306ca4a 8167
a724f0f4 8168 for (;;)
9306ca4a 8169 {
a724f0f4
JB		 8170 if (!intel_e05())
8171 return 0;
9306ca4a 8172
a724f0f4
JB		 8173 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8174 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 8175
a724f0f4
JB		 8176 if (cur_token.code == '+')
8177 nregs = -1;
8178 else if (cur_token.code == '-')
8179 nregs = NUM_ADDRESS_REGS;
8180 else
8181 return 1;
64a0c779 8182
a724f0f4
JB		 8183 strcat (intel_parser.disp, cur_token.str);
8184 intel_match_token (cur_token.code);
8185 }
64a0c779
DN		 8186}
8187
64a0c779
DN		 8188/* e05 e06 e05'
8189
9306ca4a 8190 e05' binOp e06 e05'
64a0c779
DN		 8191 | Empty */
8192static int
e3bb37b5 8193intel_e05 (void)
64a0c779 8194{
a724f0f4 8195 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8196
a724f0f4 8197 for (;;)
64a0c779 8198 {
a724f0f4
JB		 8199 if (!intel_e06())
8200 return 0;
8201
4eed87de
AM		 8202 if (cur_token.code == '&'
8203 || cur_token.code == '|'
8204 || cur_token.code == '^')
a724f0f4
JB		 8205 {
8206 char str[2];
8207
8208 str[0] = cur_token.code;
8209 str[1] = 0;
8210 strcat (intel_parser.disp, str);
8211 }
8212 else
8213 break;
9306ca4a 8214
64a0c779
DN		 8215 intel_match_token (cur_token.code);
8216
a724f0f4
JB		 8217 if (nregs < 0)
8218 nregs = ~nregs;
64a0c779 8219 }
a724f0f4
JB		 8220 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8221 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8222 return 1;
4a1805b1 8223}
64a0c779
DN		 8224
8225/* e06 e09 e06'
8226
8227 e06' mulOp e09 e06'
b77a7acd 8228 | Empty */
64a0c779 8229static int
e3bb37b5 8230intel_e06 (void)
64a0c779 8231{
a724f0f4 8232 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8233
a724f0f4 8234 for (;;)
64a0c779 8235 {
a724f0f4
JB		 8236 if (!intel_e09())
8237 return 0;
9306ca4a 8238
4eed87de
AM		 8239 if (cur_token.code == '*'
8240 || cur_token.code == '/'
8241 || cur_token.code == '%')
a724f0f4
JB		 8242 {
8243 char str[2];
9306ca4a 8244
a724f0f4
JB		 8245 str[0] = cur_token.code;
8246 str[1] = 0;
8247 strcat (intel_parser.disp, str);
8248 }
8249 else if (cur_token.code == T_SHL)
8250 strcat (intel_parser.disp, "<<");
8251 else if (cur_token.code == T_SHR)
8252 strcat (intel_parser.disp, ">>");
8253 else
8254 break;
9306ca4a 8255
64e74474 8256 intel_match_token (cur_token.code);
64a0c779 8257
a724f0f4
JB		 8258 if (nregs < 0)
8259 nregs = ~nregs;
64a0c779 8260 }
a724f0f4
JB		 8261 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8262 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8263 return 1;
64a0c779
DN		 8264}
8265
a724f0f4
JB		 8266/* e09 OFFSET e09
8267 | SHORT e09
8268 | + e09
8269 | - e09
8270 | ~ e09
8271 | NOT e09
9306ca4a
JB		 8272 | e10 e09'
8273
64a0c779 8274 e09' PTR e10 e09'
b77a7acd 8275 | : e10 e09'
64a0c779
DN		 8276 | Empty */
8277static int
e3bb37b5 8278intel_e09 (void)
64a0c779 8279{
a724f0f4
JB		 8280 int nregs = ~NUM_ADDRESS_REGS;
8281 int in_offset = 0;
8282
8283 for (;;)
64a0c779 8284 {
a724f0f4
JB		 8285 /* Don't consume constants here. */
8286 if (cur_token.code == '+' || cur_token.code == '-')
8287 {
8288 /* Need to look one token ahead - if the next token
8289 is a constant, the current token is its sign. */
8290 int next_code;
8291
8292 intel_match_token (cur_token.code);
8293 next_code = cur_token.code;
8294 intel_putback_token ();
8295 if (next_code == T_CONST)
8296 break;
8297 }
8298
8299 /* e09 OFFSET e09 */
8300 if (cur_token.code == T_OFFSET)
8301 {
8302 if (!in_offset++)
8303 ++intel_parser.in_offset;
8304 }
8305
8306 /* e09 SHORT e09 */
8307 else if (cur_token.code == T_SHORT)
8308 intel_parser.op_modifier |= 1 << T_SHORT;
8309
8310 /* e09 + e09 */
8311 else if (cur_token.code == '+')
8312 strcat (intel_parser.disp, "+");
8313
8314 /* e09 - e09
8315 | ~ e09
8316 | NOT e09 */
8317 else if (cur_token.code == '-' || cur_token.code == '~')
8318 {
8319 char str[2];
64a0c779 8320
a724f0f4
JB		 8321 if (nregs < 0)
8322 nregs = ~nregs;
8323 str[0] = cur_token.code;
8324 str[1] = 0;
8325 strcat (intel_parser.disp, str);
8326 }
8327
8328 /* e09 e10 e09' */
8329 else
8330 break;
8331
8332 intel_match_token (cur_token.code);
64a0c779
DN		 8333 }
8334
a724f0f4 8335 for (;;)
9306ca4a 8336 {
a724f0f4
JB		 8337 if (!intel_e10 ())
8338 return 0;
9306ca4a 8339
a724f0f4
JB		 8340 /* e09' PTR e10 e09' */
8341 if (cur_token.code == T_PTR)
8342 {
8343 char suffix;
9306ca4a 8344
a724f0f4 8345 if (prev_token.code == T_BYTE)
7d5e4556
L		 8346 {
8347 suffix = BYTE_MNEM_SUFFIX;
8348 i.types[this_operand].bitfield.byte = 1;
8349 }
9306ca4a 8350
a724f0f4
JB		 8351 else if (prev_token.code == T_WORD)
8352 {
8353 if (current_templates->start->name[0] == 'l'
8354 && current_templates->start->name[2] == 's'
8355 && current_templates->start->name[3] == 0)
8356 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8357 else if (intel_parser.got_a_float == 2) /* "fi..." */
8358 suffix = SHORT_MNEM_SUFFIX;
8359 else
8360 suffix = WORD_MNEM_SUFFIX;
7d5e4556 8361 i.types[this_operand].bitfield.word = 1;
a724f0f4 8362 }
64a0c779 8363
a724f0f4
JB		 8364 else if (prev_token.code == T_DWORD)
8365 {
8366 if (current_templates->start->name[0] == 'l'
8367 && current_templates->start->name[2] == 's'
8368 && current_templates->start->name[3] == 0)
8369 suffix = WORD_MNEM_SUFFIX;
8370 else if (flag_code == CODE_16BIT
40fb9820
L		 8371 && (current_templates->start->opcode_modifier.jump
8372 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8373 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8374 else if (intel_parser.got_a_float == 1) /* "f..." */
8375 suffix = SHORT_MNEM_SUFFIX;
8376 else
8377 suffix = LONG_MNEM_SUFFIX;
7d5e4556 8378 i.types[this_operand].bitfield.dword = 1;
a724f0f4 8379 }
9306ca4a 8380
a724f0f4
JB		 8381 else if (prev_token.code == T_FWORD)
8382 {
8383 if (current_templates->start->name[0] == 'l'
8384 && current_templates->start->name[2] == 's'
8385 && current_templates->start->name[3] == 0)
8386 suffix = LONG_MNEM_SUFFIX;
8387 else if (!intel_parser.got_a_float)
8388 {
8389 if (flag_code == CODE_16BIT)
8390 add_prefix (DATA_PREFIX_OPCODE);
8391 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8392 }
8393 else
8394 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 8395 i.types[this_operand].bitfield.fword = 1;
a724f0f4 8396 }
64a0c779 8397
a724f0f4
JB		 8398 else if (prev_token.code == T_QWORD)
8399 {
8400 if (intel_parser.got_a_float == 1) /* "f..." */
8401 suffix = LONG_MNEM_SUFFIX;
8402 else
7d5e4556
L		 8403 suffix = QWORD_MNEM_SUFFIX;
8404 i.types[this_operand].bitfield.qword = 1;
a724f0f4 8405 }
64a0c779 8406
a724f0f4
JB		 8407 else if (prev_token.code == T_TBYTE)
8408 {
8409 if (intel_parser.got_a_float == 1)
8410 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8411 else
8412 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8413 }
9306ca4a 8414
a724f0f4 8415 else if (prev_token.code == T_XMMWORD)
9306ca4a 8416 {
582d5edd 8417 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 8418 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 8419 }
64a0c779 8420
f16b83df 8421 else
a724f0f4
JB		 8422 {
8423 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8424 return 0;
8425 }
8426
7d5e4556
L		 8427 i.types[this_operand].bitfield.unspecified = 0;
8428
435acd52
JB		 8429 /* Operands for jump/call using 'ptr' notation denote absolute
8430 addresses. */
40fb9820
L		 8431 if (current_templates->start->opcode_modifier.jump
8432 || current_templates->start->opcode_modifier.jumpdword)
8433 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8434
a724f0f4
JB		 8435 if (current_templates->start->base_opcode == 0x8d /* lea */)
8436 ;
8437 else if (!i.suffix)
8438 i.suffix = suffix;
8439 else if (i.suffix != suffix)
8440 {
8441 as_bad (_("Conflicting operand modifiers"));
8442 return 0;
8443 }
64a0c779 8444
9306ca4a
JB		 8445 }
8446
a724f0f4
JB		 8447 /* e09' : e10 e09' */
8448 else if (cur_token.code == ':')
9306ca4a 8449 {
a724f0f4
JB		 8450 if (prev_token.code != T_REG)
8451 {
8452 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8453 segment/group identifier (which we don't have), using comma
8454 as the operand separator there is even less consistent, since
8455 there all branches only have a single operand. */
8456 if (this_operand != 0
8457 || intel_parser.in_offset
8458 || intel_parser.in_bracket
40fb9820
L		 8459 || (!current_templates->start->opcode_modifier.jump
8460 && !current_templates->start->opcode_modifier.jumpdword
8461 && !current_templates->start->opcode_modifier.jumpintersegment
8462 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8463 return intel_match_token (T_NIL);
8464 /* Remember the start of the 2nd operand and terminate 1st
8465 operand here.
8466 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8467 another expression), but it gets at least the simplest case
8468 (a plain number or symbol on the left side) right. */
8469 intel_parser.next_operand = intel_parser.op_string;
8470 *--intel_parser.op_string = '\0';
8471 return intel_match_token (':');
8472 }
9306ca4a 8473 }
64a0c779 8474
a724f0f4 8475 /* e09' Empty */
64a0c779 8476 else
a724f0f4 8477 break;
64a0c779 8478
a724f0f4
JB		 8479 intel_match_token (cur_token.code);
8480
8481 }
8482
8483 if (in_offset)
8484 {
8485 --intel_parser.in_offset;
8486 if (nregs < 0)
8487 nregs = ~nregs;
8488 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8489 {
a724f0f4 8490 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8491 return 0;
8492 }
a724f0f4
JB		 8493 intel_parser.op_modifier |= 1 << T_OFFSET;
8494 }
9306ca4a 8495
a724f0f4
JB		 8496 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8497 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8498 return 1;
8499}
64a0c779 8500
a724f0f4 8501static int
e3bb37b5 8502intel_bracket_expr (void)
a724f0f4
JB		 8503{
8504 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8505 const char *start = intel_parser.op_string;
8506 int len;
8507
8508 if (i.op[this_operand].regs)
8509 return intel_match_token (T_NIL);
8510
8511 intel_match_token ('[');
8512
8513 /* Mark as a memory operand only if it's not already known to be an
8514 offset expression. If it's an offset expression, we need to keep
8515 the brace in. */
8516 if (!intel_parser.in_offset)
8517 {
8518 ++intel_parser.in_bracket;
435acd52
JB		 8519
8520 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8521 if (current_templates->start->opcode_modifier.jump
8522 || current_templates->start->opcode_modifier.jumpdword)
8523 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8524
a724f0f4
JB		 8525 /* Unfortunately gas always diverged from MASM in a respect that can't
8526 be easily fixed without risking to break code sequences likely to be
8527 encountered (the testsuite even check for this): MASM doesn't consider
8528 an expression inside brackets unconditionally as a memory reference.
8529 When that is e.g. a constant, an offset expression, or the sum of the
8530 two, this is still taken as a constant load. gas, however, always
8531 treated these as memory references. As a compromise, we'll try to make
8532 offset expressions inside brackets work the MASM way (since that's
8533 less likely to be found in real world code), but make constants alone
8534 continue to work the traditional gas way. In either case, issue a
8535 warning. */
8536 intel_parser.op_modifier &= ~was_offset;
64a0c779 8537 }
a724f0f4 8538 else
64e74474 8539 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8540
8541 /* Add a '+' to the displacement string if necessary. */
8542 if (*intel_parser.disp != '\0'
8543 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8544 strcat (intel_parser.disp, "+");
64a0c779 8545
a724f0f4
JB		 8546 if (intel_expr ()
8547 && (len = intel_parser.op_string - start - 1,
8548 intel_match_token (']')))
64a0c779 8549 {
a724f0f4
JB		 8550 /* Preserve brackets when the operand is an offset expression. */
8551 if (intel_parser.in_offset)
8552 strcat (intel_parser.disp, "]");
8553 else
8554 {
8555 --intel_parser.in_bracket;
8556 if (i.base_reg || i.index_reg)
8557 intel_parser.is_mem = 1;
8558 if (!intel_parser.is_mem)
8559 {
8560 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8561 /* Defer the warning until all of the operand was parsed. */
8562 intel_parser.is_mem = -1;
8563 else if (!quiet_warnings)
4eed87de
AM		 8564 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8565 len, start, len, start);
a724f0f4
JB		 8566 }
8567 }
8568 intel_parser.op_modifier |= was_offset;
64a0c779 8569
a724f0f4 8570 return 1;
64a0c779 8571 }
a724f0f4 8572 return 0;
64a0c779
DN		 8573}
8574
8575/* e10 e11 e10'
8576
8577 e10' [ expr ] e10'
b77a7acd 8578 | Empty */
64a0c779 8579static int
e3bb37b5 8580intel_e10 (void)
64a0c779 8581{
a724f0f4
JB		 8582 if (!intel_e11 ())
8583 return 0;
64a0c779 8584
a724f0f4 8585 while (cur_token.code == '[')
64a0c779 8586 {
a724f0f4 8587 if (!intel_bracket_expr ())
21d6c4af 8588 return 0;
64a0c779
DN		 8589 }
8590
a724f0f4 8591 return 1;
64a0c779
DN		 8592}
8593
64a0c779 8594/* e11 ( expr )
b77a7acd 8595 | [ expr ]
64a0c779
DN		 8596 | BYTE
8597 | WORD
8598 | DWORD
9306ca4a 8599 | FWORD
64a0c779 8600 | QWORD
9306ca4a
JB		 8601 | TBYTE
8602 | OWORD
8603 | XMMWORD
4a1805b1 8604 | $
64a0c779
DN		 8605 | .
8606 | register
8607 | id
8608 | constant */
8609static int
e3bb37b5 8610intel_e11 (void)
64a0c779 8611{
a724f0f4 8612 switch (cur_token.code)
64a0c779 8613 {
a724f0f4
JB		 8614 /* e11 ( expr ) */
8615 case '(':
64a0c779
DN		 8616 intel_match_token ('(');
8617 strcat (intel_parser.disp, "(");
8618
8619 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8620 {
8621 strcat (intel_parser.disp, ")");
8622 return 1;
8623 }
a724f0f4 8624 return 0;
4a1805b1 8625
a724f0f4
JB		 8626 /* e11 [ expr ] */
8627 case '[':
a724f0f4 8628 return intel_bracket_expr ();
64a0c779 8629
a724f0f4
JB		 8630 /* e11 $
8631 | . */
8632 case '.':
64a0c779
DN		 8633 strcat (intel_parser.disp, cur_token.str);
8634 intel_match_token (cur_token.code);
21d6c4af
DN		 8635
8636 /* Mark as a memory operand only if it's not already known to be an
8637 offset expression. */
a724f0f4 8638 if (!intel_parser.in_offset)
21d6c4af 8639 intel_parser.is_mem = 1;
64a0c779
DN		 8640
8641 return 1;
64a0c779 8642
a724f0f4
JB		 8643 /* e11 register */
8644 case T_REG:
8645 {
8646 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8647
a724f0f4 8648 intel_match_token (T_REG);
64a0c779 8649
a724f0f4
JB		 8650 /* Check for segment change. */
8651 if (cur_token.code == ':')
8652 {
40fb9820
L		 8653 if (!reg->reg_type.bitfield.sreg2
8654 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8655 {
4eed87de
AM		 8656 as_bad (_("`%s' is not a valid segment register"),
8657 reg->reg_name);
a724f0f4
JB		 8658 return 0;
8659 }
8660 else if (i.seg[i.mem_operands])
8661 as_warn (_("Extra segment override ignored"));
8662 else
8663 {
8664 if (!intel_parser.in_offset)
8665 intel_parser.is_mem = 1;
8666 switch (reg->reg_num)
8667 {
8668 case 0:
8669 i.seg[i.mem_operands] = &es;
8670 break;
8671 case 1:
8672 i.seg[i.mem_operands] = &cs;
8673 break;
8674 case 2:
8675 i.seg[i.mem_operands] = &ss;
8676 break;
8677 case 3:
8678 i.seg[i.mem_operands] = &ds;
8679 break;
8680 case 4:
8681 i.seg[i.mem_operands] = &fs;
8682 break;
8683 case 5:
8684 i.seg[i.mem_operands] = &gs;
8685 break;
8686 }
8687 }
8688 }
64a0c779 8689
a724f0f4
JB		 8690 /* Not a segment register. Check for register scaling. */
8691 else if (cur_token.code == '*')
8692 {
8693 if (!intel_parser.in_bracket)
8694 {
8695 as_bad (_("Register scaling only allowed in memory operands"));
8696 return 0;
8697 }
64a0c779 8698
40fb9820 8699 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8700 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8701 else if (i.index_reg)
8702 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8703
a724f0f4
JB		 8704 /* What follows must be a valid scale. */
8705 intel_match_token ('*');
8706 i.index_reg = reg;
40fb9820 8707 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8708
a724f0f4
JB		 8709 /* Set the scale after setting the register (otherwise,
8710 i386_scale will complain) */
8711 if (cur_token.code == '+' || cur_token.code == '-')
8712 {
8713 char *str, sign = cur_token.code;
8714 intel_match_token (cur_token.code);
8715 if (cur_token.code != T_CONST)
8716 {
8717 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8718 cur_token.str);
8719 return 0;
8720 }
8721 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8722 strcpy (str + 1, cur_token.str);
8723 *str = sign;
8724 if (!i386_scale (str))
8725 return 0;
8726 free (str);
8727 }
8728 else if (!i386_scale (cur_token.str))
64a0c779 8729 return 0;
a724f0f4
JB		 8730 intel_match_token (cur_token.code);
8731 }
64a0c779 8732
a724f0f4
JB		 8733 /* No scaling. If this is a memory operand, the register is either a
8734 base register (first occurrence) or an index register (second
8735 occurrence). */
7b0441f6 8736 else if (intel_parser.in_bracket)
a724f0f4 8737 {
64a0c779 8738
a724f0f4
JB		 8739 if (!i.base_reg)
8740 i.base_reg = reg;
8741 else if (!i.index_reg)
8742 i.index_reg = reg;
8743 else
8744 {
8745 as_bad (_("Too many register references in memory operand"));
8746 return 0;
8747 }
64a0c779 8748
40fb9820 8749 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8750 }
4a1805b1 8751
4d1bb795
JB		 8752 /* It's neither base nor index. */
8753 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8754 {
40fb9820
L		 8755 i386_operand_type temp = reg->reg_type;
8756 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8757 i.types[this_operand] = operand_type_or (i.types[this_operand],
8758 temp);
7d5e4556 8759 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 8760 i.op[this_operand].regs = reg;
8761 i.reg_operands++;
8762 }
8763 else
8764 {
8765 as_bad (_("Invalid use of register"));
8766 return 0;
8767 }
64a0c779 8768
a724f0f4
JB		 8769 /* Since registers are not part of the displacement string (except
8770 when we're parsing offset operands), we may need to remove any
8771 preceding '+' from the displacement string. */
8772 if (*intel_parser.disp != '\0'
8773 && !intel_parser.in_offset)
8774 {
8775 char *s = intel_parser.disp;
8776 s += strlen (s) - 1;
8777 if (*s == '+')
8778 *s = '\0';
8779 }
4a1805b1 8780
a724f0f4
JB		 8781 return 1;
8782 }
8783
8784 /* e11 BYTE
8785 | WORD
8786 | DWORD
8787 | FWORD
8788 | QWORD
8789 | TBYTE
8790 | OWORD
8791 | XMMWORD */
8792 case T_BYTE:
8793 case T_WORD:
8794 case T_DWORD:
8795 case T_FWORD:
8796 case T_QWORD:
8797 case T_TBYTE:
8798 case T_XMMWORD:
8799 intel_match_token (cur_token.code);
64a0c779 8800
a724f0f4
JB		 8801 if (cur_token.code == T_PTR)
8802 return 1;
8803
8804 /* It must have been an identifier. */
8805 intel_putback_token ();
8806 cur_token.code = T_ID;
8807 /* FALLTHRU */
8808
8809 /* e11 id
8810 | constant */
8811 case T_ID:
8812 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8813 {
8814 symbolS *symbolP;
8815
a724f0f4
JB		 8816 /* The identifier represents a memory reference only if it's not
8817 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8818 symbolP = symbol_find(cur_token.str);
8819 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8820 intel_parser.is_mem = 1;
8821 }
a724f0f4 8822 /* FALLTHRU */
64a0c779 8823
a724f0f4
JB		 8824 case T_CONST:
8825 case '-':
8826 case '+':
8827 {
8828 char *save_str, sign = 0;
64a0c779 8829
a724f0f4
JB		 8830 /* Allow constants that start with `+' or `-'. */
8831 if (cur_token.code == '-' || cur_token.code == '+')
8832 {
8833 sign = cur_token.code;
8834 intel_match_token (cur_token.code);
8835 if (cur_token.code != T_CONST)
8836 {
8837 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8838 cur_token.str);
8839 return 0;
8840 }
8841 }
64a0c779 8842
a724f0f4
JB		 8843 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8844 strcpy (save_str + !!sign, cur_token.str);
8845 if (sign)
8846 *save_str = sign;
64a0c779 8847
a724f0f4
JB		 8848 /* Get the next token to check for register scaling. */
8849 intel_match_token (cur_token.code);
64a0c779 8850
4eed87de
AM		 8851 /* Check if this constant is a scaling factor for an
8852 index register. */
a724f0f4
JB		 8853 if (cur_token.code == '*')
8854 {
8855 if (intel_match_token ('*') && cur_token.code == T_REG)
8856 {
8857 const reg_entry *reg = cur_token.reg;
8858
8859 if (!intel_parser.in_bracket)
8860 {
4eed87de
AM		 8861 as_bad (_("Register scaling only allowed "
8862 "in memory operands"));
a724f0f4
JB		 8863 return 0;
8864 }
8865
4eed87de
AM		 8866 /* Disallow things like [1*si].
8867 sp and esp are invalid as index. */
40fb9820 8868 if (reg->reg_type.bitfield.reg16)
4eed87de 8869 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8870 else if (i.index_reg)
4eed87de 8871 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8872
8873 /* The constant is followed by `* reg', so it must be
8874 a valid scale. */
8875 i.index_reg = reg;
40fb9820 8876 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8877
8878 /* Set the scale after setting the register (otherwise,
8879 i386_scale will complain) */
8880 if (!i386_scale (save_str))
64a0c779 8881 return 0;
a724f0f4
JB		 8882 intel_match_token (T_REG);
8883
8884 /* Since registers are not part of the displacement
8885 string, we may need to remove any preceding '+' from
8886 the displacement string. */
8887 if (*intel_parser.disp != '\0')
8888 {
8889 char *s = intel_parser.disp;
8890 s += strlen (s) - 1;
8891 if (*s == '+')
8892 *s = '\0';
8893 }
8894
8895 free (save_str);
8896
8897 return 1;
8898 }
64a0c779 8899
a724f0f4
JB		 8900 /* The constant was not used for register scaling. Since we have
8901 already consumed the token following `*' we now need to put it
8902 back in the stream. */
64a0c779 8903 intel_putback_token ();
a724f0f4 8904 }
64a0c779 8905
a724f0f4
JB		 8906 /* Add the constant to the displacement string. */
8907 strcat (intel_parser.disp, save_str);
8908 free (save_str);
64a0c779 8909
a724f0f4
JB		 8910 return 1;
8911 }
64a0c779
DN		 8912 }
8913
64a0c779
DN		 8914 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8915 return 0;
8916}
8917
64a0c779
DN		 8918/* Match the given token against cur_token. If they match, read the next
8919 token from the operand string. */
8920static int
e3bb37b5 8921intel_match_token (int code)
64a0c779
DN		 8922{
8923 if (cur_token.code == code)
8924 {
8925 intel_get_token ();
8926 return 1;
8927 }
8928 else
8929 {
0477af35 8930 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8931 return 0;
8932 }
8933}
8934
64a0c779
DN		 8935/* Read a new token from intel_parser.op_string and store it in cur_token. */
8936static void
e3bb37b5 8937intel_get_token (void)
64a0c779
DN		 8938{
8939 char *end_op;
8940 const reg_entry *reg;
8941 struct intel_token new_token;
8942
8943 new_token.code = T_NIL;
8944 new_token.reg = NULL;
8945 new_token.str = NULL;
8946
4a1805b1 8947 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8948 cur_token to prev_token. */
8949 if (prev_token.str)
8950 free (prev_token.str);
8951
8952 prev_token = cur_token;
8953
8954 /* Skip whitespace. */
8955 while (is_space_char (*intel_parser.op_string))
8956 intel_parser.op_string++;
8957
8958 /* Return an empty token if we find nothing else on the line. */
8959 if (*intel_parser.op_string == '\0')
8960 {
8961 cur_token = new_token;
8962 return;
8963 }
8964
8965 /* The new token cannot be larger than the remainder of the operand
8966 string. */
a724f0f4 8967 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8968 new_token.str[0] = '\0';
8969
8970 if (strchr ("0123456789", *intel_parser.op_string))
8971 {
8972 char *p = new_token.str;
8973 char *q = intel_parser.op_string;
8974 new_token.code = T_CONST;
8975
8976 /* Allow any kind of identifier char to encompass floating point and
8977 hexadecimal numbers. */
8978 while (is_identifier_char (*q))
8979 *p++ = *q++;
8980 *p = '\0';
8981
8982 /* Recognize special symbol names [0-9][bf]. */
8983 if (strlen (intel_parser.op_string) == 2
4a1805b1 8984 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8985 || intel_parser.op_string[1] == 'f'))
8986 new_token.code = T_ID;
8987 }
8988
4d1bb795 8989 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8990 {
4d1bb795
JB		 8991 size_t len = end_op - intel_parser.op_string;
8992
64a0c779
DN		 8993 new_token.code = T_REG;
8994 new_token.reg = reg;
8995
4d1bb795
JB		 8996 memcpy (new_token.str, intel_parser.op_string, len);
8997 new_token.str[len] = '\0';
64a0c779
DN		 8998 }
8999
9000 else if (is_identifier_char (*intel_parser.op_string))
9001 {
9002 char *p = new_token.str;
9003 char *q = intel_parser.op_string;
9004
9005 /* A '.' or '$' followed by an identifier char is an identifier.
9006 Otherwise, it's operator '.' followed by an expression. */
9007 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9008 {
9306ca4a
JB		 9009 new_token.code = '.';
9010 new_token.str[0] = '.';
64a0c779
DN		 9011 new_token.str[1] = '\0';
9012 }
9013 else
9014 {
9015 while (is_identifier_char (*q) || *q == '@')
9016 *p++ = *q++;
9017 *p = '\0';
9018
9306ca4a
JB		 9019 if (strcasecmp (new_token.str, "NOT") == 0)
9020 new_token.code = '~';
9021
9022 else if (strcasecmp (new_token.str, "MOD") == 0)
9023 new_token.code = '%';
9024
9025 else if (strcasecmp (new_token.str, "AND") == 0)
9026 new_token.code = '&';
9027
9028 else if (strcasecmp (new_token.str, "OR") == 0)
9029 new_token.code = '|';
9030
9031 else if (strcasecmp (new_token.str, "XOR") == 0)
9032 new_token.code = '^';
9033
9034 else if (strcasecmp (new_token.str, "SHL") == 0)
9035 new_token.code = T_SHL;
9036
9037 else if (strcasecmp (new_token.str, "SHR") == 0)
9038 new_token.code = T_SHR;
9039
9040 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9041 new_token.code = T_BYTE;
9042
9043 else if (strcasecmp (new_token.str, "WORD") == 0)
9044 new_token.code = T_WORD;
9045
9046 else if (strcasecmp (new_token.str, "DWORD") == 0)
9047 new_token.code = T_DWORD;
9048
9306ca4a
JB		 9049 else if (strcasecmp (new_token.str, "FWORD") == 0)
9050 new_token.code = T_FWORD;
9051
64a0c779
DN		 9052 else if (strcasecmp (new_token.str, "QWORD") == 0)
9053 new_token.code = T_QWORD;
9054
9306ca4a
JB		 9055 else if (strcasecmp (new_token.str, "TBYTE") == 0
9056 /* XXX remove (gcc still uses it) */
9057 || strcasecmp (new_token.str, "XWORD") == 0)
9058 new_token.code = T_TBYTE;
9059
9060 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9061 || strcasecmp (new_token.str, "OWORD") == 0)
9062 new_token.code = T_XMMWORD;
64a0c779
DN		 9063
9064 else if (strcasecmp (new_token.str, "PTR") == 0)
9065 new_token.code = T_PTR;
9066
9067 else if (strcasecmp (new_token.str, "SHORT") == 0)
9068 new_token.code = T_SHORT;
9069
9070 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9071 {
9072 new_token.code = T_OFFSET;
9073
9074 /* ??? This is not mentioned in the MASM grammar but gcc
9075 makes use of it with -mintel-syntax. OFFSET may be
9076 followed by FLAT: */
9077 if (strncasecmp (q, " FLAT:", 6) == 0)
9078 strcat (new_token.str, " FLAT:");
9079 }
9080
9081 /* ??? This is not mentioned in the MASM grammar. */
9082 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 9083 {
9084 new_token.code = T_OFFSET;
9085 if (*q == ':')
9086 strcat (new_token.str, ":");
9087 else
9088 as_bad (_("`:' expected"));
9089 }
64a0c779
DN		 9090
9091 else
9092 new_token.code = T_ID;
9093 }
9094 }
9095
9306ca4a
JB		 9096 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9097 {
9098 new_token.code = *intel_parser.op_string;
9099 new_token.str[0] = *intel_parser.op_string;
9100 new_token.str[1] = '\0';
9101 }
9102
9103 else if (strchr ("<>", *intel_parser.op_string)
9104 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9105 {
9106 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9107 new_token.str[0] = *intel_parser.op_string;
9108 new_token.str[1] = *intel_parser.op_string;
9109 new_token.str[2] = '\0';
9110 }
9111
64a0c779 9112 else
0477af35 9113 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9114
9115 intel_parser.op_string += strlen (new_token.str);
9116 cur_token = new_token;
9117}
9118
64a0c779
DN		 9119/* Put cur_token back into the token stream and make cur_token point to
9120 prev_token. */
9121static void
e3bb37b5 9122intel_putback_token (void)
64a0c779 9123{
a724f0f4
JB		 9124 if (cur_token.code != T_NIL)
9125 {
9126 intel_parser.op_string -= strlen (cur_token.str);
9127 free (cur_token.str);
9128 }
64a0c779 9129 cur_token = prev_token;
4a1805b1 9130
64a0c779
DN		 9131 /* Forget prev_token. */
9132 prev_token.code = T_NIL;
9133 prev_token.reg = NULL;
9134 prev_token.str = NULL;
9135}
54cfded0 9136
a4447b93 9137int
1df69f4f 9138tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 9139{
9140 unsigned int regnum;
9141 unsigned int regnames_count;
089dfecd 9142 static const char *const regnames_32[] =
54cfded0 9143 {
a4447b93
RH		 9144 "eax", "ecx", "edx", "ebx",
9145 "esp", "ebp", "esi", "edi",
089dfecd
JB		 9146 "eip", "eflags", NULL,
9147 "st0", "st1", "st2", "st3",
9148 "st4", "st5", "st6", "st7",
9149 NULL, NULL,
9150 "xmm0", "xmm1", "xmm2", "xmm3",
9151 "xmm4", "xmm5", "xmm6", "xmm7",
9152 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 9153 "mm4", "mm5", "mm6", "mm7",
9154 "fcw", "fsw", "mxcsr",
9155 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
9156 "tr", "ldtr"
54cfded0 9157 };
089dfecd 9158 static const char *const regnames_64[] =
54cfded0 9159 {
089dfecd
JB		 9160 "rax", "rdx", "rcx", "rbx",
9161 "rsi", "rdi", "rbp", "rsp",
9162 "r8", "r9", "r10", "r11",
54cfded0 9163 "r12", "r13", "r14", "r15",
089dfecd
JB		 9164 "rip",
9165 "xmm0", "xmm1", "xmm2", "xmm3",
9166 "xmm4", "xmm5", "xmm6", "xmm7",
9167 "xmm8", "xmm9", "xmm10", "xmm11",
9168 "xmm12", "xmm13", "xmm14", "xmm15",
9169 "st0", "st1", "st2", "st3",
9170 "st4", "st5", "st6", "st7",
9171 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 9172 "mm4", "mm5", "mm6", "mm7",
9173 "rflags",
9174 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
9175 "fs.base", "gs.base", NULL, NULL,
9176 "tr", "ldtr",
9177 "mxcsr", "fcw", "fsw"
54cfded0 9178 };
089dfecd 9179 const char *const *regnames;
54cfded0
AM		 9180
9181 if (flag_code == CODE_64BIT)
9182 {
9183 regnames = regnames_64;
0cea6190 9184 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 9185 }
9186 else
9187 {
9188 regnames = regnames_32;
0cea6190 9189 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 9190 }
9191
9192 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 9193 if (regnames[regnum] != NULL
9194 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 9195 return regnum;
9196
54cfded0
AM		 9197 return -1;
9198}
9199
9200void
9201tc_x86_frame_initial_instructions (void)
9202{
a4447b93
RH		 9203 static unsigned int sp_regno;
9204
9205 if (!sp_regno)
9206 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
9207 ? "rsp" : "esp");
9208
9209 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
9210 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9211}
d2b2c203
DJ		 9212
9213int
9214i386_elf_section_type (const char *str, size_t len)
9215{
9216 if (flag_code == CODE_64BIT
9217 && len == sizeof ("unwind") - 1
9218 && strncmp (str, "unwind", 6) == 0)
9219 return SHT_X86_64_UNWIND;
9220
9221 return -1;
9222}
bb41ade5
AM		 9223
9224#ifdef TE_PE
9225void
9226tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9227{
9228 expressionS expr;
9229
9230 expr.X_op = O_secrel;
9231 expr.X_add_symbol = symbol;
9232 expr.X_add_number = 0;
9233 emit_expr (&expr, size);
9234}
9235#endif
3b22753a
L		 9236
9237#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9238/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9239
9240int
9241x86_64_section_letter (int letter, char **ptr_msg)
9242{
9243 if (flag_code == CODE_64BIT)
9244 {
9245 if (letter == 'l')
9246 return SHF_X86_64_LARGE;
9247
9248 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9249 }
3b22753a 9250 else
64e74474 9251 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9252 return -1;
9253}
9254
9255int
9256x86_64_section_word (char *str, size_t len)
9257{
8620418b 9258 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9259 return SHF_X86_64_LARGE;
9260
9261 return -1;
9262}
9263
9264static void
9265handle_large_common (int small ATTRIBUTE_UNUSED)
9266{
9267 if (flag_code != CODE_64BIT)
9268 {
9269 s_comm_internal (0, elf_common_parse);
9270 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9271 }
9272 else
9273 {
9274 static segT lbss_section;
9275 asection *saved_com_section_ptr = elf_com_section_ptr;
9276 asection *saved_bss_section = bss_section;
9277
9278 if (lbss_section == NULL)
9279 {
9280 flagword applicable;
9281 segT seg = now_seg;
9282 subsegT subseg = now_subseg;
9283
9284 /* The .lbss section is for local .largecomm symbols. */
9285 lbss_section = subseg_new (".lbss", 0);
9286 applicable = bfd_applicable_section_flags (stdoutput);
9287 bfd_set_section_flags (stdoutput, lbss_section,
9288 applicable & SEC_ALLOC);
9289 seg_info (lbss_section)->bss = 1;
9290
9291 subseg_set (seg, subseg);
9292 }
9293
9294 elf_com_section_ptr = &_bfd_elf_large_com_section;
9295 bss_section = lbss_section;
9296
9297 s_comm_internal (0, elf_common_parse);
9298
9299 elf_com_section_ptr = saved_com_section_ptr;
9300 bss_section = saved_bss_section;
9301 }
9302}
9303#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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